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Reworked XMC4500 IAR project to use latest system files and include build configurati...
authorrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Wed, 4 Sep 2013 15:44:48 +0000 (15:44 +0000)
committerrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Wed, 4 Sep 2013 15:44:48 +0000 (15:44 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2024 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

34 files changed:
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewp patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.c [deleted file] patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.cspy.bat [deleted file] patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dbgdt [deleted file] patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dni [deleted file] patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.wsdt [deleted file] patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/System_XMC4500.c [deleted file] patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/XMC4500.h [deleted file] patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/startup/iar/vector_table_M_forXMC4500.s [deleted file] patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/system_XMC4500.h [deleted file] patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4200.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4400.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4200.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4400.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4500.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/low_level_init.c [deleted file] patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4200.s [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4400.s [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4500.s [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4200.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4400.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.c [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.h [new file with mode: 0644] patch | blob
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c patch | blob | history
FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c patch | blob | history

diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c
index 0e24f3c5939ef67adbf43c6aaa19025ff7e8c00c..4e425431f0db667b69593faea2e607c9a3169421 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c
@@ -113,16 +113,12 @@
 \r
 /* Standard demo application includes. */\r
 #include "flop.h"\r
-#include "integer.h"\r
-#include "PollQ.h"\r
 #include "semtest.h"\r
 #include "dynamic.h"\r
-#include "BlockQ.h"\r
 #include "blocktim.h"\r
 #include "countsem.h"\r
 #include "GenQTest.h"\r
 #include "recmutex.h"\r
-#include "death.h"\r
 \r
 /* Priorities for the demo application tasks. */\r
 #define mainQUEUE_POLL_PRIORITY                                ( tskIDLE_PRIORITY + 2UL )\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h
index 92373f513d7db23be972ce3977ce49751adb2f39..51df1616b8c768e1774890f6bb90f46a4cf32777 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h
@@ -87,12 +87,12 @@
 \r
 #define configUSE_PREEMPTION                   1\r
 #define configUSE_IDLE_HOOK                            0\r
-#define configUSE_TICK_HOOK                            0\r
+#define configUSE_TICK_HOOK                            1\r
 #define configCPU_CLOCK_HZ                             ( SystemCoreClock )\r
 #define configTICK_RATE_HZ                             ( ( portTickType ) 1000 )\r
 #define configMAX_PRIORITIES                   ( ( unsigned portBASE_TYPE ) 5 )\r
 #define configMINIMAL_STACK_SIZE               ( ( unsigned short ) 130 )\r
-#define configTOTAL_HEAP_SIZE                  ( ( size_t ) ( 40960 ) )\r
+#define configTOTAL_HEAP_SIZE                  ( ( size_t ) ( 22800 ) )\r
 #define configMAX_TASK_NAME_LEN                        ( 10 )\r
 #define configUSE_TRACE_FACILITY               1\r
 #define configUSE_16_BIT_TICKS                 0\r
@@ -105,6 +105,7 @@
 #define configUSE_APPLICATION_TASK_TAG 0\r
 #define configUSE_COUNTING_SEMAPHORES  1\r
 #define configGENERATE_RUN_TIME_STATS  0\r
+#define configUSE_QUEUE_SETS                   1\r
 \r
 /* Co-routine definitions. */\r
 #define configUSE_CO_ROUTINES          0\r
@@ -150,16 +151,50 @@ to all Cortex-M ports, and do not rely on any particular library functions. */
 /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY   ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
-       \r
+\r
 /* Normal assert() semantics without relying on the provision of an assert.h\r
 header file. */\r
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }    \r
-       \r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
 /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
 standard names. */\r
 #define vPortSVCHandler SVC_Handler\r
 #define xPortPendSVHandler PendSV_Handler\r
 #define xPortSysTickHandler SysTick_Handler\r
 \r
+/* Demo application specific settings. */\r
+#ifdef __ICCARM__\r
+       #if defined( PART_XMC4500 )\r
+               /* Hardware includes. */\r
+               #include "XMC4500.h"\r
+               #include "System_XMC4500.h"\r
+\r
+               /* Configure pin P3.9 for the LED. */\r
+               #define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 )\r
+               /* To toggle the single LED */\r
+               #define configTOGGLE_LED()      ( PORT3->OMR =  0x02000200 )\r
+       #elif defined( PART_XMC4400 )\r
+               /* Hardware includes. */\r
+               #include "XMC4400.h"\r
+               #include "System_XMC4200.h"\r
+\r
+               /* Configure pin P5.2 for the LED. */\r
+               #define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 )\r
+               /* To toggle the single LED */\r
+               #define configTOGGLE_LED()      ( PORT5->OMR =  0x00040004 )\r
+       #elif defined( PART_XMC4200 )\r
+               /* Hardware includes. */\r
+               #include "XMC4200.h"\r
+               #include "System_XMC4200.h"\r
+\r
+               /* Configure pin P2.1 for the LED. */\r
+               #define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL\r
+               /* To toggle the single LED */\r
+               #define configTOGGLE_LED()      ( PORT2->OMR =  0x00020002 )\r
+       #else\r
+               #error Part number not specified in project options\r
+       #endif\r
+#endif\r
+\r
 #endif /* FREERTOS_CONFIG_H */\r
 \r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd
index d423de17559c3224859d766e6090330d2620a8c3..10b837d2315e293323814c33dfbb0b4fdd0d2333 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd
@@ -3,7 +3,7 @@
 <project>\r
   <fileVersion>2</fileVersion>\r
   <configuration>\r
-    <name>Debug</name>\r
+    <name>XMC4500</name>\r
     <toolchain>\r
       <name>ARM</name>\r
     </toolchain>\r
@@ -12,7 +12,7 @@
       <name>C-SPY</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>23</version>\r
+        <version>25</version>\r
         <wantNonLocal>1</wantNonLocal>\r
         <debug>1</debug>\r
         <option>\r
@@ -45,7 +45,7 @@
         </option>\r
         <option>\r
           <name>MemFile</name>\r
-          <state>$TOOLKIT_DIR$\CONFIG\debugger\Infineon\xmc4500.svd.xml</state>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\Infineon\xmc4500.ddf</state>\r
         </option>\r
         <option>\r
           <name>RunToEnable</name>\r
@@ -77,7 +77,7 @@
         </option>\r
         <option>\r
           <name>OCDownloadVerifyAll</name>\r
-          <state>0</state>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
           <name>OCProductVersion</name>\r
@@ -89,7 +89,7 @@
         </option>\r
         <option>\r
           <name>OCLastSavedByProductVersion</name>\r
-          <state>6.30.7.53437</state>\r
+          <state>6.60.1.5099</state>\r
         </option>\r
         <option>\r
           <name>OCDownloadAttachToProgram</name>\r
@@ -97,7 +97,7 @@
         </option>\r
         <option>\r
           <name>UseFlashLoader</name>\r
-          <state>0</state>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
           <name>CLowLevel</name>\r
@@ -175,6 +175,14 @@
           <name>OCDeviceConfigMacroFile</name>\r
           <state>1</state>\r
         </option>\r
+        <option>\r
+          <name>OCDebuggerExtraOption</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCAllMTBOptions</name>\r
+          <state>1</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
@@ -245,6 +253,153 @@
         </option>\r
       </data>\r
     </settings>\r
+    <settings>\r
+      <name>CMSISDAP_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCIarProbeScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPResetList</name>\r
+          <version>1</version>\r
+          <state>10</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPHWResetDuration</name>\r
+          <state>300</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPHWResetDelay</name>\r
+          <state>200</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiTargetEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPJtagSpeedList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPRestoreBreakpointsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPUpdateBreakpointsEdit</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchCHKERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiCPUEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiCPUNumber</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
     <settings>\r
       <name>GDBSERVER_ID</name>\r
       <archiveVersion>2</archiveVersion>\r
@@ -314,233 +469,437 @@
       </data>\r
     </settings>\r
     <settings>\r
-      <name>JLINK_ID</name>\r
+      <name>IJET_ID</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>14</version>\r
+        <version>2</version>\r
         <wantNonLocal>1</wantNonLocal>\r
         <debug>1</debug>\r
         <option>\r
-          <name>JLinkSpeed</name>\r
-          <state>32</state>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkDoLogfile</name>\r
-          <state>0</state>\r
+          <name>IjetAttachSlave</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkLogFile</name>\r
-          <state>$PROJ_DIR$\cspycomm.log</state>\r
+          <name>OCIarProbeScriptFile</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkHWResetDelay</name>\r
-          <state>0</state>\r
+          <name>IjetResetList</name>\r
+          <version>1</version>\r
+          <state>10</state>\r
         </option>\r
         <option>\r
-          <name>OCDriverInfo</name>\r
-          <state>1</state>\r
+          <name>IjetHWResetDuration</name>\r
+          <state>300</state>\r
         </option>\r
         <option>\r
-          <name>JLinkInitialSpeed</name>\r
-          <state>32</state>\r
+          <name>IjetHWResetDelay</name>\r
+          <state>200</state>\r
         </option>\r
         <option>\r
-          <name>CCDoJlinkMultiTarget</name>\r
-          <state>0</state>\r
+          <name>IjetPowerFromProbe</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCScanChainNonARMDevices</name>\r
+          <name>IjetPowerRadio</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkMultiTarget</name>\r
+          <name>IjetDoLogfile</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkIRLength</name>\r
-          <state>0</state>\r
+          <name>IjetLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkCommRadio</name>\r
+          <name>IjetInterfaceRadio</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkTCPIP</name>\r
-          <state>aaa.bbb.ccc.ddd</state>\r
+          <name>IjetInterfaceCmdLine</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkSpeedRadioV2</name>\r
+          <name>IjetMultiTargetEnable</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCUSBDevice</name>\r
-          <version>1</version>\r
-          <state>1</state>\r
+          <name>IjetMultiTarget</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCRDICatchReset</name>\r
+          <name>IjetScanChainNonARMDevices</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCRDICatchUndef</name>\r
+          <name>IjetIRLength</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCRDICatchSWI</name>\r
+          <name>IjetJtagSpeedList</name>\r
+          <version>0</version>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCRDICatchData</name>\r
+          <name>IjetProtocolRadio</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCRDICatchPrefetch</name>\r
+          <name>IjetSwoPin</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCRDICatchIRQ</name>\r
-          <state>0</state>\r
+          <name>IjetCpuClockEdit</name>\r
+          <state>72.0</state>\r
         </option>\r
         <option>\r
-          <name>CCRDICatchFIQ</name>\r
+          <name>IjetSwoPrescalerList</name>\r
+          <version>1</version>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkBreakpointRadio</name>\r
+          <name>IjetBreakpointRadio</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <name>IjetRestoreBreakpointsCheck</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkUpdateBreakpoints</name>\r
+          <name>IjetUpdateBreakpointsEdit</name>\r
           <state>_call_main</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkInterfaceRadio</name>\r
+          <name>RDICatchReset</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCJLinkAttachSlave</name>\r
+          <name>RDICatchUndef</name>\r
           <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkResetList</name>\r
-          <version>6</version>\r
-          <state>7</state>\r
+          <name>RDICatchSWI</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkInterfaceCmdLine</name>\r
-          <state>0</state>\r
+          <name>RDICatchData</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCCatchCORERESET</name>\r
-          <state>0</state>\r
+          <name>RDICatchPrefetch</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCCatchMMERR</name>\r
+          <name>RDICatchIRQ</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCCatchNOCPERR</name>\r
+          <name>RDICatchFIQ</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCCatchCHRERR</name>\r
+          <name>CatchCORERESET</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCCatchSTATERR</name>\r
-          <state>0</state>\r
+          <name>CatchMMERR</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCCatchBUSERR</name>\r
-          <state>0</state>\r
+          <name>CatchNOCPERR</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCCatchINTERR</name>\r
-          <state>0</state>\r
+          <name>CatchCHKERR</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCCatchHARDERR</name>\r
-          <state>0</state>\r
+          <name>CatchSTATERR</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCCatchDummy</name>\r
-          <state>0</state>\r
+          <name>CatchBUSERR</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>OCJLinkScriptFile</name>\r
+          <name>CatchINTERR</name>\r
           <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkUsbSerialNo</name>\r
-          <state></state>\r
+          <name>CatchHARDERR</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCTcpIpAlt</name>\r
-          <version>0</version>\r
+          <name>CatchDummy</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCJLinkTcpIpSerialNo</name>\r
-          <state></state>\r
+          <name>OCProbeCfgOverride</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCCpuClockEdit</name>\r
-          <state>72.0</state>\r
+          <name>OCProbeConfig</name>\r
+          <state></state>\r
         </option>\r
         <option>\r
-          <name>CCSwoClockAuto</name>\r
+          <name>IjetProbeConfigRadio</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCSwoClockEdit</name>\r
-          <state>2000</state>\r
+          <name>IjetMultiCPUEnable</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCJLinkTraceSource</name>\r
+          <name>IjetMultiCPUNumber</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCJLinkTraceSourceDummy</name>\r
+          <name>IjetSelectedCPUBehaviour</name>\r
           <state>0</state>\r
         </option>\r
+        <option>\r
+          <name>ICpuName</name>\r
+          <state></state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
-      <name>LMIFTDI_ID</name>\r
+      <name>JLINK_ID</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>2</version>\r
+        <version>15</version>\r
         <wantNonLocal>1</wantNonLocal>\r
         <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
         <option>\r
           <name>OCDriverInfo</name>\r
           <state>1</state>\r
         </option>\r
         <option>\r
-          <name>LmiftdiSpeed</name>\r
-          <state>500</state>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
         </option>\r
         <option>\r
-          <name>CCLmiftdiDoLogfile</name>\r
+          <name>CCDoJlinkMultiTarget</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCLmiftdiLogFile</name>\r
-          <state>$PROJ_DIR$\cspycomm.log</state>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <name>CCJLinkMultiTarget</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <name>CCJLinkIRLength</name>\r
           <state>0</state>\r
         </option>\r
-      </data>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>1</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>6</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCHRERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUsbSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCTcpIpAlt</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTcpIpSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkTraceSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkTraceSourceDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkDeviceName</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
     </settings>\r
     <settings>\r
       <name>MACRAIGOR_ID</name>\r
@@ -635,7 +994,7 @@
       <name>PEMICRO_ID</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>0</version>\r
+        <version>1</version>\r
         <wantNonLocal>1</wantNonLocal>\r
         <debug>1</debug>\r
         <option>\r
@@ -693,6 +1052,14 @@
           <name>CCPEMicroCommCmdLineProducer</name>\r
           <state>0</state>\r
         </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
@@ -752,63 +1119,6 @@
         </option>\r
       </data>\r
     </settings>\r
-    <settings>\r
-      <name>RDIJTAGJET_ID</name>\r
-      <archiveVersion>0</archiveVersion>\r
-      <data>\r
-        <version>1</version>\r
-        <wantNonLocal>1</wantNonLocal>\r
-        <debug>1</debug>\r
-        <option>\r
-          <name>CRDILogFileCheck</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CRDILogFileEdit</name>\r
-          <state>$PROJ_DIR$\cspycomm.log</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDIHWReset</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchReset</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchUndef</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchSWI</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchData</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchPrefetch</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchIRQ</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchFIQ</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>OCDriverInfo</name>\r
-          <state>1</state>\r
-        </option>\r
-        <option>\r
-          <name>JTAGjetConfigure</name>\r
-          <state></state>\r
-        </option>\r
-      </data>\r
-    </settings>\r
     <settings>\r
       <name>STLINK_ID</name>\r
       <archiveVersion>2</archiveVersion>\r
@@ -876,7 +1186,7 @@
       <name>XDS100_ID</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>1</version>\r
+        <version>2</version>\r
         <wantNonLocal>1</wantNonLocal>\r
         <debug>1</debug>\r
         <option>\r
@@ -897,17 +1207,29 @@
         </option>\r
         <option>\r
           <name>CCXds100InterfaceList</name>\r
-          <version>0</version>\r
+          <version>1</version>\r
           <state>0</state>\r
         </option>\r
         <option>\r
           <name>BoardFile</name>\r
           <state></state>\r
         </option>\r
-      </data>\r
-    </settings>\r
-    <debuggerPlugins>\r
-      <plugin>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
         <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
         <loadFlag>0</loadFlag>\r
       </plugin>\r
@@ -968,28 +1290,28 @@
         <loadFlag>0</loadFlag>\r
       </plugin>\r
       <plugin>\r
-        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
         <loadFlag>1</loadFlag>\r
       </plugin>\r
       <plugin>\r
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
-        <loadFlag>1</loadFlag>\r
+        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
       </plugin>\r
     </debuggerPlugins>\r
   </configuration>\r
   <configuration>\r
-    <name>Release</name>\r
+    <name>XMC4200</name>\r
     <toolchain>\r
       <name>ARM</name>\r
     </toolchain>\r
-    <debug>0</debug>\r
+    <debug>1</debug>\r
     <settings>\r
       <name>C-SPY</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>23</version>\r
+        <version>25</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>CInput</name>\r
           <state>1</state>\r
@@ -1020,7 +1342,7 @@
         </option>\r
         <option>\r
           <name>MemFile</name>\r
-          <state></state>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\Infineon\xmc4200.ddf</state>\r
         </option>\r
         <option>\r
           <name>RunToEnable</name>\r
@@ -1052,239 +1374,1891 @@
         </option>\r
         <option>\r
           <name>OCDownloadVerifyAll</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>6.30.7.53437</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>6.60.1.5099</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state>$TOOLKIT_DIR$\config\flashloader\Infineon\FlashXMC4200.board</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDeviceConfigMacroFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDebuggerExtraOption</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCAllMTBOptions</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CMSISDAP_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCIarProbeScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPResetList</name>\r
+          <version>1</version>\r
+          <state>10</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPHWResetDuration</name>\r
+          <state>300</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPHWResetDelay</name>\r
+          <state>200</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiTargetEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPJtagSpeedList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPRestoreBreakpointsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPUpdateBreakpointsEdit</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchCHKERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiCPUEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiCPUNumber</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IJET_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCIarProbeScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetResetList</name>\r
+          <version>1</version>\r
+          <state>10</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetHWResetDuration</name>\r
+          <state>300</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetHWResetDelay</name>\r
+          <state>200</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetPowerFromProbe</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetPowerRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetMultiTargetEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetJtagSpeedList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetProtocolRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetSwoPin</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetSwoPrescalerList</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetRestoreBreakpointsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetUpdateBreakpointsEdit</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchUndef</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchData</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchPrefetch</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchMMERR</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchNOCPERR</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchCHKERR</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchSTATERR</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchBUSERR</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchINTERR</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchHARDERR</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProbeCfgOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProbeConfig</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IjetProbeConfigRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetMultiCPUEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetMultiCPUNumber</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetSelectedCPUBehaviour</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ICpuName</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>15</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>1</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>6</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCHRERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUsbSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCTcpIpAlt</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTcpIpSerialNo</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkTraceSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkTraceSourceDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkDeviceName</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>PEMICRO_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCPEMicroAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroInterfaceList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroJtagSpeed</name>\r
+          <state>#UNINITIALIZED#</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroShowSettings</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroSerialPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroTCPIP</name>\r
+          <state>10.0.0.1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroCommCmdLineProducer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkResetList</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockAuto</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSwoClockEdit</name>\r
+          <state>2000</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>XDS100_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCXDS100AttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TIPackageOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>TIPackage</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCXds100InterfaceList</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>BoardFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+  <configuration>\r
+    <name>XMC4400</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>25</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\Infineon\xmc4400.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>6.30.7.53437</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>6.60.1.5099</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state>$TOOLKIT_DIR$\config\flashloader\Infineon\FlashXMC4400.board</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDeviceConfigMacroFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDebuggerExtraOption</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCAllMTBOptions</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CMSISDAP_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCIarProbeScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPResetList</name>\r
+          <version>1</version>\r
+          <state>10</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPHWResetDuration</name>\r
+          <state>300</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPHWResetDelay</name>\r
+          <state>200</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiTargetEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPJtagSpeedList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPRestoreBreakpointsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPUpdateBreakpointsEdit</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>RDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchCHKERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiCPUEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CMSISDAPMultiCPUNumber</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCProductVersion</name>\r
-          <state>6.30.7.53437</state>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
         </option>\r
         <option>\r
-          <name>OCDynDriverList</name>\r
-          <state>ARMSIM_ID</state>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
         </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IJET_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
         <option>\r
-          <name>OCLastSavedByProductVersion</name>\r
-          <state></state>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>OCDownloadAttachToProgram</name>\r
-          <state>0</state>\r
+          <name>IjetAttachSlave</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>UseFlashLoader</name>\r
-          <state>0</state>\r
+          <name>OCIarProbeScriptFile</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CLowLevel</name>\r
-          <state>1</state>\r
+          <name>IjetResetList</name>\r
+          <version>1</version>\r
+          <state>10</state>\r
         </option>\r
         <option>\r
-          <name>OCBE8Slave</name>\r
-          <state>1</state>\r
+          <name>IjetHWResetDuration</name>\r
+          <state>300</state>\r
         </option>\r
         <option>\r
-          <name>MacFile2</name>\r
-          <state></state>\r
+          <name>IjetHWResetDelay</name>\r
+          <state>200</state>\r
         </option>\r
         <option>\r
-          <name>CDevice</name>\r
+          <name>IjetPowerFromProbe</name>\r
           <state>1</state>\r
         </option>\r
         <option>\r
-          <name>FlashLoadersV3</name>\r
-          <state></state>\r
+          <name>IjetPowerRadio</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesSuppressCheck1</name>\r
+          <name>IjetDoLogfile</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesPath1</name>\r
-          <state></state>\r
+          <name>IjetLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesSuppressCheck2</name>\r
+          <name>IjetInterfaceRadio</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesPath2</name>\r
-          <state></state>\r
+          <name>IjetInterfaceCmdLine</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesSuppressCheck3</name>\r
+          <name>IjetMultiTargetEnable</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesPath3</name>\r
-          <state></state>\r
+          <name>IjetMultiTarget</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OverrideDefFlashBoard</name>\r
+          <name>IjetScanChainNonARMDevices</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesOffset1</name>\r
-          <state></state>\r
+          <name>IjetIRLength</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesOffset2</name>\r
-          <state></state>\r
+          <name>IjetJtagSpeedList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesOffset3</name>\r
-          <state></state>\r
+          <name>IjetProtocolRadio</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesUse1</name>\r
+          <name>IjetSwoPin</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesUse2</name>\r
+          <name>IjetCpuClockEdit</name>\r
+          <state>72.0</state>\r
+        </option>\r
+        <option>\r
+          <name>IjetSwoPrescalerList</name>\r
+          <version>1</version>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCImagesUse3</name>\r
+          <name>IjetBreakpointRadio</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCDeviceConfigMacroFile</name>\r
-          <state>1</state>\r
+          <name>IjetRestoreBreakpointsCheck</name>\r
+          <state>0</state>\r
         </option>\r
-      </data>\r
-    </settings>\r
-    <settings>\r
-      <name>ARMSIM_ID</name>\r
-      <archiveVersion>2</archiveVersion>\r
-      <data>\r
-        <version>1</version>\r
-        <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
         <option>\r
-          <name>OCSimDriverInfo</name>\r
-          <state>1</state>\r
+          <name>IjetUpdateBreakpointsEdit</name>\r
+          <state>_call_main</state>\r
         </option>\r
         <option>\r
-          <name>OCSimEnablePSP</name>\r
+          <name>RDICatchReset</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCSimPspOverrideConfig</name>\r
-          <state>0</state>\r
+          <name>RDICatchUndef</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>OCSimPspConfigFile</name>\r
-          <state></state>\r
+          <name>RDICatchSWI</name>\r
+          <state>0</state>\r
         </option>\r
-      </data>\r
-    </settings>\r
-    <settings>\r
-      <name>ANGEL_ID</name>\r
-      <archiveVersion>2</archiveVersion>\r
-      <data>\r
-        <version>0</version>\r
-        <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
         <option>\r
-          <name>CCAngelHeartbeat</name>\r
+          <name>RDICatchData</name>\r
           <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CAngelCommunication</name>\r
+          <name>RDICatchPrefetch</name>\r
           <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CAngelCommBaud</name>\r
-          <version>0</version>\r
-          <state>3</state>\r
+          <name>RDICatchIRQ</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CAngelCommPort</name>\r
-          <version>0</version>\r
+          <name>RDICatchFIQ</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>ANGELTCPIP</name>\r
-          <state>aaa.bbb.ccc.ddd</state>\r
+          <name>CatchCORERESET</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>DoAngelLogfile</name>\r
-          <state>0</state>\r
+          <name>CatchMMERR</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>AngelLogFile</name>\r
-          <state>$PROJ_DIR$\cspycomm.log</state>\r
+          <name>CatchNOCPERR</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>OCDriverInfo</name>\r
+          <name>CatchCHKERR</name>\r
           <state>1</state>\r
         </option>\r
-      </data>\r
-    </settings>\r
-    <settings>\r
-      <name>GDBSERVER_ID</name>\r
-      <archiveVersion>2</archiveVersion>\r
-      <data>\r
-        <version>0</version>\r
-        <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
         <option>\r
-          <name>OCDriverInfo</name>\r
+          <name>CatchSTATERR</name>\r
           <state>1</state>\r
         </option>\r
         <option>\r
-          <name>TCPIP</name>\r
-          <state>aaa.bbb.ccc.ddd</state>\r
+          <name>CatchBUSERR</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>DoLogfile</name>\r
-          <state>0</state>\r
+          <name>CatchINTERR</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>LogFile</name>\r
-          <state>$PROJ_DIR$\cspycomm.log</state>\r
+          <name>CatchHARDERR</name>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
-          <name>CCJTagBreakpointRadio</name>\r
+          <name>CatchDummy</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <name>OCProbeCfgOverride</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CCJTagUpdateBreakpoints</name>\r
-          <state>_call_main</state>\r
+          <name>OCProbeConfig</name>\r
+          <state></state>\r
         </option>\r
-      </data>\r
-    </settings>\r
-    <settings>\r
-      <name>IARROM_ID</name>\r
-      <archiveVersion>2</archiveVersion>\r
-      <data>\r
-        <version>1</version>\r
-        <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
         <option>\r
-          <name>CRomLogFileCheck</name>\r
+          <name>IjetProbeConfigRadio</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CRomLogFileEditB</name>\r
-          <state>$PROJ_DIR$\cspycomm.log</state>\r
+          <name>IjetMultiCPUEnable</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CRomCommPort</name>\r
-          <version>0</version>\r
+          <name>IjetMultiCPUNumber</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
-          <name>CRomCommBaud</name>\r
-          <version>0</version>\r
-          <state>7</state>\r
+          <name>IjetSelectedCPUBehaviour</name>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
-          <name>OCDriverInfo</name>\r
-          <state>1</state>\r
+          <name>ICpuName</name>\r
+          <state></state>\r
         </option>\r
       </data>\r
     </settings>\r
@@ -1292,9 +3266,9 @@
       <name>JLINK_ID</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>14</version>\r
+        <version>15</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>JLinkSpeed</name>\r
           <state>32</state>\r
@@ -1394,7 +3368,7 @@
         </option>\r
         <option>\r
           <name>CCJLinkInterfaceRadio</name>\r
-          <state>0</state>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
           <name>OCJLinkAttachSlave</name>\r
@@ -1403,7 +3377,7 @@
         <option>\r
           <name>CCJLinkResetList</name>\r
           <version>6</version>\r
-          <state>5</state>\r
+          <state>7</state>\r
         </option>\r
         <option>\r
           <name>CCJLinkInterfaceCmdLine</name>\r
@@ -1482,6 +3456,10 @@
           <name>OCJLinkTraceSourceDummy</name>\r
           <state>0</state>\r
         </option>\r
+        <option>\r
+          <name>OCJLinkDeviceName</name>\r
+          <state>1</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
@@ -1490,7 +3468,7 @@
       <data>\r
         <version>2</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>OCDriverInfo</name>\r
           <state>1</state>\r
@@ -1523,7 +3501,7 @@
       <data>\r
         <version>3</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>jtag</name>\r
           <version>0</version>\r
@@ -1610,9 +3588,9 @@
       <name>PEMICRO_ID</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>0</version>\r
+        <version>1</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>OCDriverInfo</name>\r
           <state>1</state>\r
@@ -1668,6 +3646,14 @@
           <name>CCPEMicroCommCmdLineProducer</name>\r
           <state>0</state>\r
         </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
@@ -1676,7 +3662,7 @@
       <data>\r
         <version>2</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>CRDIDriverDll</name>\r
           <state>###Uninitialized###</state>\r
@@ -1727,70 +3713,13 @@
         </option>\r
       </data>\r
     </settings>\r
-    <settings>\r
-      <name>RDIJTAGJET_ID</name>\r
-      <archiveVersion>0</archiveVersion>\r
-      <data>\r
-        <version>1</version>\r
-        <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
-        <option>\r
-          <name>CRDILogFileCheck</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CRDILogFileEdit</name>\r
-          <state>$PROJ_DIR$\cspycomm.log</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDIHWReset</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchReset</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchUndef</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchSWI</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchData</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchPrefetch</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchIRQ</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>CCRDICatchFIQ</name>\r
-          <state>0</state>\r
-        </option>\r
-        <option>\r
-          <name>OCDriverInfo</name>\r
-          <state>1</state>\r
-        </option>\r
-        <option>\r
-          <name>JTAGjetConfigure</name>\r
-          <state></state>\r
-        </option>\r
-      </data>\r
-    </settings>\r
     <settings>\r
       <name>STLINK_ID</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
         <version>2</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>OCDriverInfo</name>\r
           <state>1</state>\r
@@ -1828,7 +3757,7 @@
       <data>\r
         <version>0</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>CThirdPartyDriverDll</name>\r
           <state>###Uninitialized###</state>\r
@@ -1851,9 +3780,9 @@
       <name>XDS100_ID</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>1</version>\r
+        <version>2</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>OCDriverInfo</name>\r
           <state>1</state>\r
@@ -1872,16 +3801,28 @@
         </option>\r
         <option>\r
           <name>CCXds100InterfaceList</name>\r
-          <version>0</version>\r
+          <version>1</version>\r
           <state>0</state>\r
         </option>\r
         <option>\r
           <name>BoardFile</name>\r
           <state></state>\r
         </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
       <plugin>\r
         <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
         <loadFlag>0</loadFlag>\r
@@ -1943,12 +3884,12 @@
         <loadFlag>0</loadFlag>\r
       </plugin>\r
       <plugin>\r
-        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
         <loadFlag>1</loadFlag>\r
       </plugin>\r
       <plugin>\r
-        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
-        <loadFlag>1</loadFlag>\r
+        <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
       </plugin>\r
     </debuggerPlugins>\r
   </configuration>\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewp
index 934a2b4b8bb6aac80e1bbf5cea9aaa6fef5cf5a4..402737146bba9b6d3bb5bc34a92ab9c056b1a03e 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewp
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewp
@@ -3,7 +3,7 @@
 <project>\r
   <fileVersion>2</fileVersion>\r
   <configuration>\r
-    <name>Debug</name>\r
+    <name>XMC4500</name>\r
     <toolchain>\r
       <name>ARM</name>\r
     </toolchain>\r
@@ -12,20 +12,20 @@
       <name>General</name>\r
       <archiveVersion>3</archiveVersion>\r
       <data>\r
-        <version>21</version>\r
+        <version>22</version>\r
         <wantNonLocal>1</wantNonLocal>\r
         <debug>1</debug>\r
         <option>\r
           <name>ExePath</name>\r
-          <state>Debug\Exe</state>\r
+          <state>XMC4500\Exe</state>\r
         </option>\r
         <option>\r
           <name>ObjPath</name>\r
-          <state>Debug\Obj</state>\r
+          <state>XMC4500\Obj</state>\r
         </option>\r
         <option>\r
           <name>ListPath</name>\r
-          <state>Debug\List</state>\r
+          <state>XMC4500\List</state>\r
         </option>\r
         <option>\r
           <name>Variant</name>\r
@@ -87,7 +87,7 @@
         </option>\r
         <option>\r
           <name>OGLastSavedByProductVersion</name>\r
-          <state>6.50.1.4445</state>\r
+          <state>6.60.1.5099</state>\r
         </option>\r
         <option>\r
           <name>GeneralEnableMisra</name>\r
@@ -153,13 +153,953 @@
           <name>OGUseCmsisDspLib</name>\r
           <state>0</state>\r
         </option>\r
+        <option>\r
+          <name>GRuntimeLibThreads</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>29</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCOptimizationNoSizeConstraints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state>PART_XMC4500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state>Pa082</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarning</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagError</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCAllowList</name>\r
+          <version>1</version>\r
+          <state>0000000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDebugInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IEndianMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangConformance</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSignedPlainChar</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRequirePrototypes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMultibyteSupport</name>\r
+          <state>0</state>\r
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+          <state></state>\r
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+          <name>IlinkStackCallGraphFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlgorithm</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcUnitSize</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkThreadsSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <configuration>\r
+    <name>XMC4200</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>22</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>XMC4200\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>XMC4200\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>XMC4200\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>20</version>\r
+          <state>40</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>3</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>Full formatting.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>2</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>Full formatting.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>2</version>\r
+          <state>5</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.10.0.159</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>6.60.1.5099</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>xmc4200       Infineon xmc4200</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath2</name>\r
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+        </option>\r
+        <option>\r
+          <name>GFPUCoreSlave</name>\r
+          <version>20</version>\r
+          <state>40</state>\r
+        </option>\r
+        <option>\r
+          <name>GBECoreSlave</name>\r
+          <version>20</version>\r
+          <state>40</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsis</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGUseCmsisDspLib</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibThreads</name>\r
+          <state>0</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
       <name>ICCARM</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>28</version>\r
+        <version>29</version>\r
         <wantNonLocal>1</wantNonLocal>\r
         <debug>1</debug>\r
         <option>\r
@@ -168,7 +1108,7 @@
         </option>\r
         <option>\r
           <name>CCDefines</name>\r
-          <state></state>\r
+          <state>PART_XMC4200</state>\r
         </option>\r
         <option>\r
           <name>CCPreprocFile</name>\r
@@ -298,7 +1238,7 @@
         <option>\r
           <name>CCIncludePath2</name>\r
           <state>$PROJ_DIR$\</state>\r
-          <state>$PROJ_DIR$\system\CMSIS\DeviceSupport\Infineon\XMC45xx</state>\r
+          <state>$PROJ_DIR$\system\</state>\r
           <state>$PROJ_DIR$\..\..\Source\include</state>\r
           <state>$PROJ_DIR$\..\common\include</state>\r
           <state>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F</state>\r
@@ -394,13 +1334,17 @@
           <name>IccFloatSemantics</name>\r
           <state>0</state>\r
         </option>\r
+        <option>\r
+          <name>CCNoLiteralPool</name>\r
+          <state>0</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
       <name>AARM</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>8</version>\r
+        <version>9</version>\r
         <wantNonLocal>1</wantNonLocal>\r
         <debug>1</debug>\r
         <option>\r
@@ -556,6 +1500,10 @@
           <name>AExtraOptionsV2</name>\r
           <state></state>\r
         </option>\r
+        <option>\r
+          <name>AsmNoLiteralPool</name>\r
+          <state>0</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
@@ -613,7 +1561,7 @@
       <name>ILINK</name>\r
       <archiveVersion>0</archiveVersion>\r
       <data>\r
-        <version>15</version>\r
+        <version>16</version>\r
         <wantNonLocal>1</wantNonLocal>\r
         <debug>1</debug>\r
         <option>\r
@@ -690,11 +1638,11 @@
         </option>\r
         <option>\r
           <name>IlinkIcfOverride</name>\r
-          <state>1</state>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
           <name>IlinkIcfFile</name>\r
-          <state>$PROJ_DIR$\XMC4500_Flash.icf</state>\r
+          <state>$TOOLKIT_DIR$\config\linker\Infineon\xmc4200.icf</state>\r
         </option>\r
         <option>\r
           <name>IlinkIcfFileSlave</name>\r
@@ -893,6 +1841,10 @@
           <version>0</version>\r
           <state>0</state>\r
         </option>\r
+        <option>\r
+          <name>IlinkThreadsSlave</name>\r
+          <state>1</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
@@ -923,34 +1875,34 @@
     </settings>\r
   </configuration>\r
   <configuration>\r
-    <name>Release</name>\r
+    <name>XMC4400</name>\r
     <toolchain>\r
       <name>ARM</name>\r
     </toolchain>\r
-    <debug>0</debug>\r
+    <debug>1</debug>\r
     <settings>\r
       <name>General</name>\r
       <archiveVersion>3</archiveVersion>\r
       <data>\r
-        <version>21</version>\r
+        <version>22</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>ExePath</name>\r
-          <state>Release\Exe</state>\r
+          <state>XMC4400\Exe</state>\r
         </option>\r
         <option>\r
           <name>ObjPath</name>\r
-          <state>Release\Obj</state>\r
+          <state>XMC4400\Obj</state>\r
         </option>\r
         <option>\r
           <name>ListPath</name>\r
-          <state>Release\List</state>\r
+          <state>XMC4400\List</state>\r
         </option>\r
         <option>\r
           <name>Variant</name>\r
           <version>20</version>\r
-          <state>0</state>\r
+          <state>40</state>\r
         </option>\r
         <option>\r
           <name>GEndianMode</name>\r
@@ -981,11 +1933,11 @@
         <option>\r
           <name>FPU</name>\r
           <version>2</version>\r
-          <state>0</state>\r
+          <state>5</state>\r
         </option>\r
         <option>\r
           <name>OGCoreOrChip</name>\r
-          <state>0</state>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
           <name>GRuntimeLibSelect</name>\r
@@ -1007,7 +1959,7 @@
         </option>\r
         <option>\r
           <name>OGLastSavedByProductVersion</name>\r
-          <state>6.30.1.53141</state>\r
+          <state>6.60.1.5099</state>\r
         </option>\r
         <option>\r
           <name>GeneralEnableMisra</name>\r
@@ -1019,15 +1971,15 @@
         </option>\r
         <option>\r
           <name>OGChipSelectEditMenu</name>\r
-          <state>default       None</state>\r
+          <state>xmc4400       Infineon xmc4400</state>\r
         </option>\r
         <option>\r
           <name>GenLowLevelInterface</name>\r
-          <state>0</state>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
           <name>GEndianModeBE</name>\r
-          <state>0</state>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
           <name>OGBufferedTerminalOutput</name>\r
@@ -1058,37 +2010,41 @@
         <option>\r
           <name>GFPUCoreSlave</name>\r
           <version>20</version>\r
-          <state>0</state>\r
+          <state>40</state>\r
         </option>\r
         <option>\r
           <name>GBECoreSlave</name>\r
           <version>20</version>\r
-          <state>0</state>\r
+          <state>40</state>\r
         </option>\r
         <option>\r
           <name>OGUseCmsis</name>\r
-          <state>0</state>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
           <name>OGUseCmsisDspLib</name>\r
           <state>0</state>\r
         </option>\r
+        <option>\r
+          <name>GRuntimeLibThreads</name>\r
+          <state>0</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
       <name>ICCARM</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>28</version>\r
+        <version>29</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>CCOptimizationNoSizeConstraints</name>\r
           <state>0</state>\r
         </option>\r
         <option>\r
           <name>CCDefines</name>\r
-          <state>NDEBUG</state>\r
+          <state>PART_XMC4400</state>\r
         </option>\r
         <option>\r
           <name>CCPreprocFile</name>\r
@@ -1128,7 +2084,7 @@
         </option>\r
         <option>\r
           <name>CCDiagSuppress</name>\r
-          <state></state>\r
+          <state>Pa082</state>\r
         </option>\r
         <option>\r
           <name>CCDiagRemark</name>\r
@@ -1149,11 +2105,11 @@
         <option>\r
           <name>CCAllowList</name>\r
           <version>1</version>\r
-          <state>1111111</state>\r
+          <state>0000000</state>\r
         </option>\r
         <option>\r
           <name>CCDebugInfo</name>\r
-          <state>0</state>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
           <name>IEndianMode</name>\r
@@ -1217,7 +2173,11 @@
         </option>\r
         <option>\r
           <name>CCIncludePath2</name>\r
-          <state></state>\r
+          <state>$PROJ_DIR$\</state>\r
+          <state>$PROJ_DIR$\system\</state>\r
+          <state>$PROJ_DIR$\..\..\Source\include</state>\r
+          <state>$PROJ_DIR$\..\common\include</state>\r
+          <state>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F</state>\r
         </option>\r
         <option>\r
           <name>CCStdIncCheck</name>\r
@@ -1229,7 +2189,7 @@
         </option>\r
         <option>\r
           <name>IInterwork2</name>\r
-          <state>1</state>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
           <name>IProcessorMode2</name>\r
@@ -1237,7 +2197,7 @@
         </option>\r
         <option>\r
           <name>CCOptLevel</name>\r
-          <state>3</state>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
           <name>CCOptStrategy</name>\r
@@ -1246,7 +2206,7 @@
         </option>\r
         <option>\r
           <name>CCOptLevelSlave</name>\r
-          <state>3</state>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
           <name>CompilerMisraRules98</name>\r
@@ -1310,15 +2270,19 @@
           <name>IccFloatSemantics</name>\r
           <state>0</state>\r
         </option>\r
+        <option>\r
+          <name>CCNoLiteralPool</name>\r
+          <state>0</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
       <name>AARM</name>\r
       <archiveVersion>2</archiveVersion>\r
       <data>\r
-        <version>8</version>\r
+        <version>9</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>AObjPrefix</name>\r
           <state>1</state>\r
@@ -1358,7 +2322,7 @@
         </option>\r
         <option>\r
           <name>ADebug</name>\r
-          <state>0</state>\r
+          <state>1</state>\r
         </option>\r
         <option>\r
           <name>AltRegisterNames</name>\r
@@ -1462,7 +2426,7 @@
         </option>\r
         <option>\r
           <name>AUserIncludes</name>\r
-          <state></state>\r
+          <state>$PROJ_DIR$\</state>\r
         </option>\r
         <option>\r
           <name>AExtraOptionsCheckV2</name>\r
@@ -1472,6 +2436,10 @@
           <name>AExtraOptionsV2</name>\r
           <state></state>\r
         </option>\r
+        <option>\r
+          <name>AsmNoLiteralPool</name>\r
+          <state>0</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
@@ -1480,7 +2448,7 @@
       <data>\r
         <version>1</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>OOCOutputFormat</name>\r
           <version>2</version>\r
@@ -1529,9 +2497,9 @@
       <name>ILINK</name>\r
       <archiveVersion>0</archiveVersion>\r
       <data>\r
-        <version>15</version>\r
+        <version>16</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>IlinkOutputFile</name>\r
           <state>c.out</state>\r
@@ -1610,7 +2578,7 @@
         </option>\r
         <option>\r
           <name>IlinkIcfFile</name>\r
-          <state>$TOOLKIT_DIR$\CONFIG\generic.icf</state>\r
+          <state>$TOOLKIT_DIR$\config\linker\Infineon\xmc4400.icf</state>\r
         </option>\r
         <option>\r
           <name>IlinkIcfFileSlave</name>\r
@@ -1670,7 +2638,7 @@
         </option>\r
         <option>\r
           <name>IlinkProgramEntryLabel</name>\r
-          <state></state>\r
+          <state>__iar_program_start</state>\r
         </option>\r
         <option>\r
           <name>DoFill</name>\r
@@ -1761,7 +2729,7 @@
         </option>\r
         <option>\r
           <name>IlinkOptInline</name>\r
-          <state>1</state>\r
+          <state>0</state>\r
         </option>\r
         <option>\r
           <name>IlinkOptExceptionsAllow</name>\r
@@ -1809,6 +2777,10 @@
           <version>0</version>\r
           <state>0</state>\r
         </option>\r
+        <option>\r
+          <name>IlinkThreadsSlave</name>\r
+          <state>1</state>\r
+        </option>\r
       </data>\r
     </settings>\r
     <settings>\r
@@ -1817,7 +2789,7 @@
       <data>\r
         <version>0</version>\r
         <wantNonLocal>1</wantNonLocal>\r
-        <debug>0</debug>\r
+        <debug>1</debug>\r
         <option>\r
           <name>IarchiveInputs</name>\r
           <state></state>\r
@@ -1840,18 +2812,9 @@
   </configuration>\r
   <group>\r
     <name>Common_Demo_Source</name>\r
-    <file>\r
-      <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
-    </file>\r
     <file>\r
       <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
     </file>\r
-    <file>\r
-      <name>$PROJ_DIR$\..\Common\Minimal\countsem.c</name>\r
-    </file>\r
-    <file>\r
-      <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
-    </file>\r
     <file>\r
       <name>$PROJ_DIR$\..\Common\Minimal\dynamic.c</name>\r
     </file>\r
@@ -1859,17 +2822,14 @@
       <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
     </file>\r
     <file>\r
-      <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c</name>\r
     </file>\r
     <file>\r
-      <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\QueueSet.c</name>\r
     </file>\r
     <file>\r
       <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
     </file>\r
-    <file>\r
-      <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
-    </file>\r
     <file>\r
       <name>$PROJ_DIR$\..\Common\Minimal\sp_flop.c</name>\r
     </file>\r
@@ -1877,7 +2837,7 @@
   <group>\r
     <name>FreeRTOS_Source</name>\r
     <file>\r
-      <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</name>\r
     </file>\r
     <file>\r
       <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
@@ -1901,12 +2861,51 @@
   <group>\r
     <name>System</name>\r
     <file>\r
-      <name>$PROJ_DIR$\system\low_level_init.c</name>\r
+      <name>$PROJ_DIR$\system\startup_XMC4200.s</name>\r
+      <excluded>\r
+        <configuration>XMC4500</configuration>\r
+        <configuration>XMC4400</configuration>\r
+      </excluded>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system\startup_XMC4400.s</name>\r
+      <excluded>\r
+        <configuration>XMC4500</configuration>\r
+        <configuration>XMC4200</configuration>\r
+      </excluded>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system\startup_XMC4500.s</name>\r
+      <excluded>\r
+        <configuration>XMC4200</configuration>\r
+        <configuration>XMC4400</configuration>\r
+      </excluded>\r
     </file>\r
     <file>\r
-      <name>$PROJ_DIR$\system\CMSIS\DeviceSupport\Infineon\XMC45xx\System_XMC4500.c</name>\r
+      <name>$PROJ_DIR$\system\System_XMC4200.c</name>\r
+      <excluded>\r
+        <configuration>XMC4500</configuration>\r
+        <configuration>XMC4400</configuration>\r
+      </excluded>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system\System_XMC4400.c</name>\r
+      <excluded>\r
+        <configuration>XMC4500</configuration>\r
+        <configuration>XMC4200</configuration>\r
+      </excluded>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system\system_XMC4500.c</name>\r
+      <excluded>\r
+        <configuration>XMC4200</configuration>\r
+        <configuration>XMC4400</configuration>\r
+      </excluded>\r
     </file>\r
   </group>\r
+  <file>\r
+    <name>$PROJ_DIR$\FreeRTOSConfig.h</name>\r
+  </file>\r
   <file>\r
     <name>$PROJ_DIR$\main.c</name>\r
   </file>\r
@@ -1919,9 +2918,6 @@
   <file>\r
     <name>$PROJ_DIR$\RegTest.s</name>\r
   </file>\r
-  <file>\r
-    <name>$PROJ_DIR$\system\CMSIS\DeviceSupport\Infineon\XMC45xx\startup\iar\vector_table_M_forXMC4500.s</name>\r
-  </file>\r
 </project>\r
 \r
 \r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.c
deleted file mode 100644 (file)
index cf2aeae..0000000
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.c
+++ /dev/null
@@ -1,513 +0,0 @@
-/*\r
-    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
-    ***************************************************************************\r
-     *                                                                       *\r
-     *    FreeRTOS provides completely free yet professionally developed,    *\r
-     *    robust, strictly quality controlled, supported, and cross          *\r
-     *    platform software that has become a de facto standard.             *\r
-     *                                                                       *\r
-     *    Help yourself get started quickly and support the FreeRTOS         *\r
-     *    project by purchasing a FreeRTOS tutorial book, reference          *\r
-     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
-     *                                                                       *\r
-     *    Thank you!                                                         *\r
-     *                                                                       *\r
-    ***************************************************************************\r
-\r
-    This file is part of the FreeRTOS distribution.\r
-\r
-    FreeRTOS is free software; you can redistribute it and/or modify it under\r
-    the terms of the GNU General Public License (version 2) as published by the\r
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
-    >>! NOTE: The modification to the GPL is included to allow you to distribute\r
-    >>! a combined work that includes FreeRTOS without being obliged to provide\r
-    >>! the source code for proprietary components outside of the FreeRTOS\r
-    >>! kernel.\r
-\r
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
-    FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
-    link: http://www.freertos.org/a00114.html\r
-\r
-    1 tab == 4 spaces!\r
-\r
-    ***************************************************************************\r
-     *                                                                       *\r
-     *    Having a problem?  Start by reading the FAQ "My application does   *\r
-     *    not run, what could be wrong?"                                     *\r
-     *                                                                       *\r
-     *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
-     *                                                                       *\r
-    ***************************************************************************\r
-\r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
-    license and Real Time Engineers Ltd. contact details.\r
-\r
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
-    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
-    licenses offer ticketed support, indemnification and middleware.\r
-\r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
-    engineered and independently SIL3 certified version for use in safety and\r
-    mission critical applications that require provable dependability.\r
-\r
-    1 tab == 4 spaces!\r
-*/\r
-\r
-\r
-__asm vRegTest1Task( void )\r
-{\r
-       PRESERVE8\r
-       IMPORT ulRegTest1LoopCounter\r
-\r
-       /* Fill the core registers with known values. */\r
-       mov r0, #100\r
-       mov r1, #101\r
-       mov r2, #102\r
-       mov r3, #103\r
-       mov     r4, #104\r
-       mov     r5, #105\r
-       mov     r6, #106\r
-       mov r7, #107\r
-       mov     r8, #108\r
-       mov     r9, #109\r
-       mov     r10, #110\r
-       mov     r11, #111\r
-       mov r12, #112\r
-\r
-       /* Fill the VFP registers with known values. */\r
-       vmov d0, r0, r1\r
-       vmov d1, r2, r3\r
-       vmov d2, r4, r5\r
-       vmov d3, r6, r7\r
-       vmov d4, r8, r9\r
-       vmov d5, r10, r11\r
-       vmov d6, r0, r1\r
-       vmov d7, r2, r3\r
-       vmov d8, r4, r5\r
-       vmov d9, r6, r7\r
-       vmov d10, r8, r9\r
-       vmov d11, r10, r11\r
-       vmov d12, r0, r1\r
-       vmov d13, r2, r3\r
-       vmov d14, r4, r5\r
-       vmov d15, r6, r7\r
-\r
-reg1_loop\r
-       /* Check all the VFP registers still contain the values set above.\r
-       First save registers that are clobbered by the test. */\r
-       push { r0-r1 }\r
-       \r
-       vmov r0, r1, d0\r
-       cmp r0, #100\r
-       bne reg1_error_loopf\r
-       cmp r1, #101\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d1\r
-       cmp r0, #102\r
-       bne reg1_error_loopf\r
-       cmp r1, #103\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d2\r
-       cmp r0, #104\r
-       bne reg1_error_loopf\r
-       cmp r1, #105\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d3\r
-       cmp r0, #106\r
-       bne reg1_error_loopf\r
-       cmp r1, #107\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d4\r
-       cmp r0, #108\r
-       bne reg1_error_loopf\r
-       cmp r1, #109\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d5\r
-       cmp r0, #110\r
-       bne reg1_error_loopf\r
-       cmp r1, #111\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d6\r
-       cmp r0, #100\r
-       bne reg1_error_loopf\r
-       cmp r1, #101\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d7\r
-       cmp r0, #102\r
-       bne reg1_error_loopf\r
-       cmp r1, #103\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d8\r
-       cmp r0, #104\r
-       bne reg1_error_loopf\r
-       cmp r1, #105\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d9\r
-       cmp r0, #106\r
-       bne reg1_error_loopf\r
-       cmp r1, #107\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d10\r
-       cmp r0, #108\r
-       bne reg1_error_loopf\r
-       cmp r1, #109\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d11\r
-       cmp r0, #110\r
-       bne reg1_error_loopf\r
-       cmp r1, #111\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d12\r
-       cmp r0, #100\r
-       bne reg1_error_loopf\r
-       cmp r1, #101\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d13\r
-       cmp r0, #102\r
-       bne reg1_error_loopf\r
-       cmp r1, #103\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d14\r
-       cmp r0, #104\r
-       bne reg1_error_loopf\r
-       cmp r1, #105\r
-       bne reg1_error_loopf\r
-       vmov r0, r1, d15\r
-       cmp r0, #106\r
-       bne reg1_error_loopf\r
-       cmp r1, #107\r
-       bne reg1_error_loopf\r
-       \r
-       /* Restore the registers that were clobbered by the test. */\r
-       pop {r0-r1}\r
-       \r
-       /* VFP register test passed.  Jump to the core register test. */\r
-       b reg1_loopf_pass\r
-\r
-reg1_error_loopf\r
-       /* If this line is hit then a VFP register value was found to be\r
-       incorrect. */\r
-       b reg1_error_loopf\r
-\r
-reg1_loopf_pass\r
-\r
-       cmp     r0, #100\r
-       bne     reg1_error_loop\r
-       cmp     r1, #101\r
-       bne     reg1_error_loop\r
-       cmp     r2, #102\r
-       bne     reg1_error_loop\r
-       cmp r3, #103\r
-       bne     reg1_error_loop\r
-       cmp     r4, #104\r
-       bne     reg1_error_loop\r
-       cmp     r5, #105\r
-       bne     reg1_error_loop\r
-       cmp     r6, #106\r
-       bne     reg1_error_loop\r
-       cmp     r7, #107\r
-       bne     reg1_error_loop\r
-       cmp     r8, #108\r
-       bne     reg1_error_loop\r
-       cmp     r9, #109\r
-       bne     reg1_error_loop\r
-       cmp     r10, #110\r
-       bne     reg1_error_loop\r
-       cmp     r11, #111\r
-       bne     reg1_error_loop\r
-       cmp     r12, #112\r
-       bne     reg1_error_loop\r
-       \r
-       /* Everything passed, increment the loop counter. */\r
-       push { r0-r1 }\r
-       ldr     r0, =ulRegTest1LoopCounter\r
-       ldr r1, [r0]\r
-       adds r1, r1, #1\r
-       str r1, [r0]\r
-       pop { r0-r1 }\r
-       \r
-       /* Start again. */\r
-       b reg1_loop\r
-\r
-reg1_error_loop\r
-       /* If this line is hit then there was an error in a core register value.\r
-       The loop ensures the loop counter stops incrementing. */\r
-       b reg1_error_loop\r
-       nop\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-__asm vRegTest2Task( void )\r
-{\r
-       PRESERVE8\r
-       IMPORT ulRegTest2LoopCounter\r
-\r
-       /* Set all the core registers to known values. */\r
-       mov r0, #-1\r
-       mov r1, #1\r
-       mov r2, #2\r
-       mov r3, #3\r
-       mov     r4, #4\r
-       mov     r5, #5\r
-       mov     r6, #6\r
-       mov r7, #7\r
-       mov     r8, #8\r
-       mov     r9, #9\r
-       mov     r10, #10\r
-       mov     r11, #11\r
-       mov r12, #12\r
-\r
-       /* Set all the VFP to known values. */\r
-       vmov d0, r0, r1\r
-       vmov d1, r2, r3\r
-       vmov d2, r4, r5\r
-       vmov d3, r6, r7\r
-       vmov d4, r8, r9\r
-       vmov d5, r10, r11\r
-       vmov d6, r0, r1\r
-       vmov d7, r2, r3\r
-       vmov d8, r4, r5\r
-       vmov d9, r6, r7\r
-       vmov d10, r8, r9\r
-       vmov d11, r10, r11\r
-       vmov d12, r0, r1\r
-       vmov d13, r2, r3\r
-       vmov d14, r4, r5\r
-       vmov d15, r6, r7\r
-\r
-reg2_loop\r
-       \r
-       /* Check all the VFP registers still contain the values set above.\r
-       First save registers that are clobbered by the test. */\r
-       push { r0-r1 }\r
-       \r
-       vmov r0, r1, d0\r
-       cmp r0, #-1\r
-       bne reg2_error_loopf\r
-       cmp r1, #1\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d1\r
-       cmp r0, #2\r
-       bne reg2_error_loopf\r
-       cmp r1, #3\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d2\r
-       cmp r0, #4\r
-       bne reg2_error_loopf\r
-       cmp r1, #5\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d3\r
-       cmp r0, #6\r
-       bne reg2_error_loopf\r
-       cmp r1, #7\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d4\r
-       cmp r0, #8\r
-       bne reg2_error_loopf\r
-       cmp r1, #9\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d5\r
-       cmp r0, #10\r
-       bne reg2_error_loopf\r
-       cmp r1, #11\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d6\r
-       cmp r0, #-1\r
-       bne reg2_error_loopf\r
-       cmp r1, #1\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d7\r
-       cmp r0, #2\r
-       bne reg2_error_loopf\r
-       cmp r1, #3\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d8\r
-       cmp r0, #4\r
-       bne reg2_error_loopf\r
-       cmp r1, #5\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d9\r
-       cmp r0, #6\r
-       bne reg2_error_loopf\r
-       cmp r1, #7\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d10\r
-       cmp r0, #8\r
-       bne reg2_error_loopf\r
-       cmp r1, #9\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d11\r
-       cmp r0, #10\r
-       bne reg2_error_loopf\r
-       cmp r1, #11\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d12\r
-       cmp r0, #-1\r
-       bne reg2_error_loopf\r
-       cmp r1, #1\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d13\r
-       cmp r0, #2\r
-       bne reg2_error_loopf\r
-       cmp r1, #3\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d14\r
-       cmp r0, #4\r
-       bne reg2_error_loopf\r
-       cmp r1, #5\r
-       bne reg2_error_loopf\r
-       vmov r0, r1, d15\r
-       cmp r0, #6\r
-       bne reg2_error_loopf\r
-       cmp r1, #7\r
-       bne reg2_error_loopf\r
-       \r
-       /* Restore the registers that were clobbered by the test. */\r
-       pop {r0-r1}\r
-       \r
-       /* VFP register test passed.  Jump to the core register test. */\r
-       b reg2_loopf_pass\r
-\r
-reg2_error_loopf\r
-       /* If this line is hit then a VFP register value was found to be\r
-       incorrect. */\r
-       b reg2_error_loopf\r
-\r
-reg2_loopf_pass\r
-\r
-       cmp     r0, #-1\r
-       bne     reg2_error_loop\r
-       cmp     r1, #1\r
-       bne     reg2_error_loop\r
-       cmp     r2, #2\r
-       bne     reg2_error_loop\r
-       cmp r3, #3\r
-       bne     reg2_error_loop\r
-       cmp     r4, #4\r
-       bne     reg2_error_loop\r
-       cmp     r5, #5\r
-       bne     reg2_error_loop\r
-       cmp     r6, #6\r
-       bne     reg2_error_loop\r
-       cmp     r7, #7\r
-       bne     reg2_error_loop\r
-       cmp     r8, #8\r
-       bne     reg2_error_loop\r
-       cmp     r9, #9\r
-       bne     reg2_error_loop\r
-       cmp     r10, #10\r
-       bne     reg2_error_loop\r
-       cmp     r11, #11\r
-       bne     reg2_error_loop\r
-       cmp     r12, #12\r
-       bne     reg2_error_loop\r
-       \r
-       /* Increment the loop counter to indicate this test is still functioning\r
-       correctly. */\r
-       push { r0-r1 }\r
-       ldr     r0, =ulRegTest2LoopCounter\r
-       ldr r1, [r0]\r
-       adds r1, r1, #1\r
-       str r1, [r0]\r
-       pop { r0-r1 }\r
-       \r
-       /* Start again. */\r
-       b reg2_loop\r
-\r
-reg2_error_loop\r
-       /* If this line is hit then there was an error in a core register value.\r
-       This loop ensures the loop counter variable stops incrementing. */\r
-       b reg2_error_loop\r
-       nop\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue        )\r
-{\r
-       PRESERVE8\r
-\r
-       /* Clobber the auto saved registers. */\r
-       vmov d0, r0, r0\r
-       vmov d1, r0, r0\r
-       vmov d2, r0, r0\r
-       vmov d3, r0, r0\r
-       vmov d4, r0, r0\r
-       vmov d5, r0, r0\r
-       vmov d6, r0, r0\r
-       vmov d7, r0, r0\r
-       bx lr\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue )\r
-{\r
-       PRESERVE8\r
-\r
-       vmov r1, s0\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s1\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s2\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s3\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s4\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s5\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s6\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s7\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s8\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s9\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s10\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s11\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s12\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s13\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s14\r
-       cmp r0, r1\r
-       bne return_error\r
-       vmov r1, s15\r
-       cmp r0, r1\r
-       bne return_error\r
-       \r
-return_pass\r
-       mov r0, #1\r
-       bx lr\r
-\r
-return_error\r
-       mov r0, #0\r
-       bx lr\r
-}\r
-\r
-       \r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s
index bd89de3f78340b8ddc80d0c620c49ca419d9ea21..45105d369bbbdd2cdaed5266e1ffb694e5f883bb 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s
@@ -75,7 +75,7 @@
        PUBLIC vRegTest2Task\r
        PUBLIC vRegTestClearFlopRegistersToParameterValue\r
        PUBLIC ulRegTestCheckFlopRegistersContainParameterValue\r
-       \r
+\r
 /*-----------------------------------------------------------*/\r
 \r
 vRegTest1Task\r
@@ -117,7 +117,7 @@ reg1_loop:
        /* Check all the VFP registers still contain the values set above.\r
        First save registers that are clobbered by the test. */\r
        push { r0-r1 }\r
-       \r
+\r
        vmov r0, r1, d0\r
        cmp r0, #100\r
        bne reg1_error_loopf\r
@@ -198,10 +198,10 @@ reg1_loop:
        bne reg1_error_loopf\r
        cmp r1, #107\r
        bne reg1_error_loopf\r
-       \r
+\r
        /* Restore the registers that were clobbered by the test. */\r
        pop {r0-r1}\r
-       \r
+\r
        /* VFP register test passed.  Jump to the core register test. */\r
        b reg1_loopf_pass\r
 \r
@@ -238,7 +238,7 @@ reg1_loopf_pass
        bne     reg1_error_loop\r
        cmp     r12, #112\r
        bne     reg1_error_loop\r
-       \r
+\r
        /* Everything passed, increment the loop counter. */\r
        push { r0-r1 }\r
        ldr     r0, =ulRegTest1LoopCounter\r
@@ -246,7 +246,7 @@ reg1_loopf_pass
        adds r1, r1, #1\r
        str r1, [r0]\r
        pop { r0-r1 }\r
-       \r
+\r
        /* Start again. */\r
        b reg1_loop\r
 \r
@@ -294,11 +294,11 @@ vRegTest2Task
        vmov d15, r6, r7\r
 \r
 reg2_loop:\r
-       \r
+\r
        /* Check all the VFP registers still contain the values set above.\r
        First save registers that are clobbered by the test. */\r
        push { r0-r1 }\r
-       \r
+\r
        vmov r0, r1, d0\r
        cmp r0, #-1\r
        bne reg2_error_loopf\r
@@ -379,10 +379,10 @@ reg2_loop:
        bne reg2_error_loopf\r
        cmp r1, #7\r
        bne reg2_error_loopf\r
-       \r
+\r
        /* Restore the registers that were clobbered by the test. */\r
        pop {r0-r1}\r
-       \r
+\r
        /* VFP register test passed.  Jump to the core register test. */\r
        b reg2_loopf_pass\r
 \r
@@ -419,7 +419,7 @@ reg2_loopf_pass
        bne     reg2_error_loop\r
        cmp     r12, #12\r
        bne     reg2_error_loop\r
-       \r
+\r
        /* Increment the loop counter to indicate this test is still functioning\r
        correctly. */\r
        push { r0-r1 }\r
@@ -427,8 +427,16 @@ reg2_loopf_pass
        ldr r1, [r0]\r
        adds r1, r1, #1\r
        str r1, [r0]\r
+\r
+       /* Yield to increase test coverage. */\r
+       movs r0, #0x01\r
+       ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */\r
+       lsl r0, r0, #28 /* Shift to PendSV bit */\r
+       str r0, [r1]\r
+       dsb\r
+\r
        pop { r0-r1 }\r
-       \r
+\r
        /* Start again. */\r
        b reg2_loop\r
 \r
@@ -504,7 +512,7 @@ ulRegTestCheckFlopRegistersContainParameterValue
        vmov r1, s15\r
        cmp r0, r1\r
        bne return_error\r
-       \r
+\r
 return_pass\r
        mov r0, #1\r
        bx lr\r
@@ -514,4 +522,4 @@ return_error
        bx lr\r
 \r
        END\r
-       \r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c
index b9ad4ebb424b76cb8f42dd2661c14b70c9ef2d09..9dfc362fd02e8075f1125f64311e729d2f5764ba 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c
@@ -92,9 +92,9 @@
 #include "FreeRTOS.h"\r
 #include "task.h"\r
 \r
-/* Hardware includes. */\r
-#include "XMC4500.h"\r
-#include "System_XMC4500.h"\r
+/* Standard demo includes. */\r
+#include "QueueSet.h"\r
+#include "QueueOverwrite.h"\r
 \r
 /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
 or 0 to run the more comprehensive test and demo application. */\r
@@ -139,13 +139,7 @@ int main( void )
 \r
 static void prvSetupHardware( void )\r
 {\r
-extern void SystemCoreClockUpdate( void );\r
-\r
-       /* Ensure SystemCoreClock variable is set. */\r
-       SystemCoreClockUpdate();\r
-\r
-       /* Configure pin P3.9 for the LED. */\r
-       PORT3->IOCR8 = 0x00008000;\r
+       configCONFIGURE_LED();\r
 \r
        /* Ensure all priority bits are assigned as preemption priority bits. */\r
        NVIC_SetPriorityGrouping( 0 );\r
@@ -203,6 +197,17 @@ void vApplicationTickHook( void )
        added here, but the tick hook is called from an interrupt context, so\r
        code must not attempt to block, and only the interrupt safe FreeRTOS API\r
        functions can be used (those that end in FromISR()). */\r
+\r
+       #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0\r
+       {\r
+               /* Write to a queue that is in use as part of the queue set demo to\r
+               demonstrate using queue sets from an ISR. */\r
+               vQueueSetAccessQueueSetFromISR();\r
+\r
+               /* Test the ISR safe queue overwrite functions. */\r
+               vQueueOverwritePeriodicISRDemo();\r
+       }\r
+       #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -214,12 +219,12 @@ long lHigherPriorityTaskWoken = pdFALSE;
 \r
        /* Clear the interrupt if necessary. */\r
        Dummy_ClearITPendingBit();\r
-       \r
+\r
        /* This interrupt does nothing more than demonstrate how to synchronise a\r
        task with an interrupt.  A semaphore is used for this purpose.  Note\r
        lHigherPriorityTaskWoken is initialised to zero. */\r
        xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );\r
-       \r
+\r
        /* If there was a task that was blocked on the semaphore, and giving the\r
        semaphore caused the task to unblock, and the unblocked task has a priority\r
        higher than the current Running state task (the task that this interrupt\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c
index cbc2ba905bada86b0db57dc4b9a898c65c65bc86..83d8398d80fc65e954e9312fc8304004f4c4b39b 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c
@@ -107,10 +107,6 @@
 #include "task.h"\r
 #include "semphr.h"\r
 \r
-/* Hardware includes. */\r
-#include "XMC4500.h"\r
-#include "System_XMC4500.h"\r
-\r
 /* Priorities at which the tasks are created. */\r
 #define mainQUEUE_RECEIVE_TASK_PRIORITY                ( tskIDLE_PRIORITY + 2 )\r
 #define        mainQUEUE_SEND_TASK_PRIORITY            ( tskIDLE_PRIORITY + 1 )\r
@@ -129,9 +125,6 @@ functionality. */
 #define mainQUEUE_SEND_PARAMETER                       ( 0x1111UL )\r
 #define mainQUEUE_RECEIVE_PARAMETER                    ( 0x22UL )\r
 \r
-/* To toggle the single LED */\r
-#define mainTOGGLE_LED()                                       ( PORT3->OMR =  0x02000200 )\r
-\r
 /*-----------------------------------------------------------*/\r
 \r
 /*\r
@@ -146,11 +139,6 @@ static void prvQueueSendTask( void *pvParameters );
  */\r
 void main_blinky( void );\r
 \r
-/*\r
- * The hardware only has a single LED.  Simply toggle it.\r
- */\r
-extern void vMainToggleLED( void );\r
-\r
 /*-----------------------------------------------------------*/\r
 \r
 /* The queue used by both tasks. */\r
@@ -235,7 +223,7 @@ unsigned long ulReceivedValue;
                is it the expected value?  If it is, toggle the LED. */\r
                if( ulReceivedValue == 100UL )\r
                {\r
-                       mainTOGGLE_LED();\r
+                       configTOGGLE_LED();\r
                        ulReceivedValue = 0U;\r
                }\r
        }\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c
index ded660a6eef8a9fcf6b87fdbe8989cc91c16b887..29c5be7bdaa581240b56fadde395e46de180fc19 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c
@@ -75,8 +75,8 @@
  ******************************************************************************\r
  *\r
  * main_full() creates all the demo application tasks and a software timer, then\r
- * starts the scheduler.  The web documentation provides more details of the \r
- * standard demo application tasks, which provide no particular functionality, \r
+ * starts the scheduler.  The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
  * but do provide a good example of how to use the FreeRTOS API.\r
  *\r
  * In addition to the standard demo tasks, the following tasks and tests are\r
@@ -113,20 +113,14 @@
 \r
 /* Standard demo application includes. */\r
 #include "flop.h"\r
-#include "integer.h"\r
-#include "PollQ.h"\r
 #include "semtest.h"\r
 #include "dynamic.h"\r
-#include "BlockQ.h"\r
 #include "blocktim.h"\r
 #include "countsem.h"\r
 #include "GenQTest.h"\r
 #include "recmutex.h"\r
-#include "death.h"\r
-\r
-/* Hardware includes. */\r
-#include "XMC4500.h"\r
-#include "System_XMC4500.h"\r
+#include "QueueSet.h"\r
+#include "QueueOverwrite.h"\r
 \r
 /* Priorities for the demo application tasks. */\r
 #define mainQUEUE_POLL_PRIORITY                                ( tskIDLE_PRIORITY + 2UL )\r
@@ -135,9 +129,6 @@
 #define mainCREATOR_TASK_PRIORITY                      ( tskIDLE_PRIORITY + 3UL )\r
 #define mainFLOP_TASK_PRIORITY                         ( tskIDLE_PRIORITY )\r
 \r
-/* To toggle the single LED */\r
-#define mainTOGGLE_LED()                                       ( PORT3->OMR =  0x02000200 )\r
-\r
 /* A block time of zero simply means "don't block". */\r
 #define mainDONT_BLOCK                                         ( 0UL )\r
 \r
@@ -183,17 +174,14 @@ xTimerHandle xCheckTimer = NULL;
        /* Start all the other standard demo/test tasks.  The have not particular\r
        functionality, but do demonstrate how to use the FreeRTOS API and test the\r
        kernel port. */\r
-       vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+       vStartQueueSetTasks();\r
+       vStartQueueOverwriteTask( tskIDLE_PRIORITY );\r
        vStartDynamicPriorityTasks();\r
-       vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
        vCreateBlockTimeTasks();\r
-       vStartCountingSemaphoreTasks();\r
        vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
        vStartRecursiveMutexTasks();\r
-       vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
-       vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
        vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
-       \r
+\r
        /* Create the register check tasks, as described at the top of this\r
        file */\r
        xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
@@ -206,27 +194,22 @@ xTimerHandle xCheckTimer = NULL;
                                                                pdTRUE,                                                         /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
                                                                ( void * ) 0,                                           /* The ID is not used, so can be set to anything. */\r
                                                                prvCheckTimerCallback                           /* The callback function that inspects the status of all the other tasks. */\r
-                                                         );    \r
-       \r
+                                                         );\r
+\r
        if( xCheckTimer != NULL )\r
        {\r
                xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
        }\r
 \r
-       /* The set of tasks created by the following function call have to be \r
-       created last as they keep account of the number of tasks they expect to see \r
-       running. */\r
-       vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
-\r
        /* Start the scheduler. */\r
        vTaskStartScheduler();\r
-       \r
+\r
        /* If all is well, the scheduler will now be running, and the following line\r
        will never be reached.  If the following line does execute, then there was\r
        insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
        to be created.  See the memory management section on the FreeRTOS web site\r
        for more details. */\r
-       for( ;; );      \r
+       for( ;; );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -244,21 +227,11 @@ unsigned long ulErrorFound = pdFALSE;
                ulErrorFound = pdTRUE;\r
        }\r
 \r
-       if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
-       {\r
-               ulErrorFound = pdTRUE;\r
-       }\r
-\r
        if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
        {\r
                ulErrorFound = pdTRUE;\r
        }\r
 \r
-       if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
-       {\r
-               ulErrorFound = pdTRUE;\r
-       }\r
-\r
        if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
        {\r
                ulErrorFound = pdTRUE;\r
@@ -274,21 +247,16 @@ unsigned long ulErrorFound = pdFALSE;
                ulErrorFound = pdTRUE;\r
        }\r
 \r
-       if( xIsCreateTaskStillRunning() != pdTRUE )\r
+       if( xAreQueueSetTasksStillRunning() != pdTRUE )\r
        {\r
                ulErrorFound = pdTRUE;\r
        }\r
 \r
-       if( xArePollingQueuesStillRunning() != pdTRUE )\r
+       if( xIsQueueOverwriteTaskStillRunning() != pdTRUE )\r
        {\r
                ulErrorFound = pdTRUE;\r
        }\r
 \r
-       if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
-       {\r
-               ulErrorFound = pdTRUE;\r
-       }\r
-       \r
        /* Check that the register test 1 task is still running. */\r
        if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
        {\r
@@ -306,8 +274,8 @@ unsigned long ulErrorFound = pdFALSE;
        /* Toggle the check LED to give an indication of the system status.  If\r
        the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
        everything is ok.  A faster toggle indicates an error. */\r
-       mainTOGGLE_LED();       \r
-       \r
+       configTOGGLE_LED();\r
+\r
        /* Have any errors been latch in ulErrorFound?  If so, shorten the\r
        period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
        This will result in an increase in the rate at which mainCHECK_LED\r
@@ -317,7 +285,7 @@ unsigned long ulErrorFound = pdFALSE;
                if( lChangedTimerPeriodAlready == pdFALSE )\r
                {\r
                        lChangedTimerPeriodAlready = pdTRUE;\r
-                       \r
+\r
                        /* This call to xTimerChangePeriod() uses a zero block time.\r
                        Functions called from inside of a timer callback function must\r
                        *never* attempt to block. */\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.cspy.bat b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.cspy.bat
deleted file mode 100644 (file)
index 58a8004..0000000
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.cspy.bat
+++ /dev/null
@@ -1,24 +0,0 @@
-@REM This batch file has been generated by the IAR Embedded Workbench\r
-@REM C-SPY Debugger, as an aid to preparing a command line for running\r
-@REM the cspybat command line utility using the appropriate settings.\r
-@REM\r
-@REM Note that this file is generated every time a new debug session\r
-@REM is initialized, so you may want to move or rename the file before\r
-@REM making changes.\r
-@REM\r
-@REM You can launch cspybat by typing the name of this batch file followed\r
-@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
-@REM\r
-@REM Read about available command line parameters in the C-SPY Debugging\r
-@REM Guide. Hints about additional command line parameters that may be\r
-@REM useful in specific cases:\r
-@REM   --download_only   Downloads a code image without starting a debug\r
-@REM                     session afterwards.\r
-@REM   --silent          Omits the sign-on message.\r
-@REM   --timeout         Limits the maximum allowed execution time.\r
-@REM \r
-\r
-\r
-"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armjlink.dll"  %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --macro "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\Infineon\Trace_XMC4500.dmac" --backend -B "--endian=little" "--cpu=Cortex-M4F" "--fpu=VFPv4" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\Infineon\xmc4500.ddf" "--semihosting" "--device=xmc4500" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--drv_catch_exceptions=0x000" "--jlink_script_file=C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\Infineon\XMC4500.jlinkscript" "--drv_swo_clock_setup=72000000,0,2000000" \r
-\r
-\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dbgdt
deleted file mode 100644 (file)
index 33f4649..0000000
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dbgdt
+++ /dev/null
@@ -1,5 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>\r
-\r
-<Project/>\r
-\r
-\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dni
deleted file mode 100644 (file)
index 297b672..0000000
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dni
+++ /dev/null
@@ -1,17 +0,0 @@
-[Stack]\r
-FillEnabled=0\r
-OverflowWarningsEnabled=1\r
-WarningThreshold=90\r
-SpWarningsEnabled=1\r
-WarnLogOnly=1\r
-UseTrigger=1\r
-TriggerName=main\r
-LimitSize=0\r
-ByteLimit=50\r
-[Disassemble mode]\r
-mode=0\r
-[Breakpoints2]\r
-Count=0\r
-[Aliases]\r
-Count=0\r
-SuppressDialog=0\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.wsdt
deleted file mode 100644 (file)
index 81d8753..0000000
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.wsdt
+++ /dev/null
@@ -1,49 +0,0 @@
-<?xml version="1.0" encoding="iso-8859-1"?>\r
-\r
-<Workspace>\r
-  <ConfigDictionary>\r
-    \r
-  <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
-  <Desktop>\r
-    <Static>\r
-      <Workspace>\r
-        <ColumnWidths>\r
-          \r
-          \r
-          \r
-          \r
-        <Column0>124</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
-      </Workspace>\r
-    <Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build></Static>\r
-    <Windows>\r
-      \r
-    <Wnd2>\r
-        <Tabs>\r
-          <Tab>\r
-            <Identity>TabID-11195-18312</Identity>\r
-            <TabName>Workspace</TabName>\r
-            <Factory>Workspace</Factory>\r
-            <Session>\r
-              \r
-            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode></NodeDict></Session>\r
-          </Tab>\r
-        </Tabs>\r
-        \r
-      <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-6727-18343</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
-    <Editor>\r
-      \r
-      \r
-      \r
-      \r
-    <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>63</YPos2><SelStart2>0</SelStart2><SelEnd2>0</SelEnd2></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
-    <Positions>\r
-      \r
-      \r
-      \r
-      \r
-      \r
-    <Top><Row0><Sizes><Toolbar-013491e8><key>iaridepm.enu1</key></Toolbar-013491e8></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>198</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
-  </Desktop>\r
-</Workspace>\r
-\r
-\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/System_XMC4500.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/System_XMC4500.c
deleted file mode 100644 (file)
index c4f5fe8..0000000
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/System_XMC4500.c
+++ /dev/null
@@ -1,412 +0,0 @@
-/******************************************************************************\r
- * @file     system_XMC4500.c\r
- * @brief    Device specific initialization for the XMC4500-Series according to CMSIS\r
- * @version  V2.2\r
- * @date     20. January 2012\r
- *\r
- * @note\r
- * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.\r
-\r
- *\r
- * @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon\92s microcontrollers.  \r
- * This file can be freely distributed within development tools that are supporting such microcontrollers. \r
-\r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- *\r
- ******************************************************************************/\r
-\r
-#include "System_XMC4500.h"\r
-#include <XMC4500.h>\r
-\r
-/*----------------------------------------------------------------------------\r
-  Define clocks        is located in System_XMC4500.h\r
- *----------------------------------------------------------------------------*/\r
-\r
-/*----------------------------------------------------------------------------\r
-  Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-/*!< System Clock Frequency (Core Clock)*/\r
-uint32_t SystemCoreClock = CLOCK_OSC_HP;\r
-\r
-/*\r
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
-*/\r
-\r
-\r
-\r
-/*--------------------- Watchdog Configuration -------------------------------\r
-//\r
-// <e> Watchdog Configuration\r
-//     <o1.0> Disable Watchdog\r
-//\r
-// </e>\r
-*/\r
-#define WDT_SETUP               1\r
-#define WDTENB_nVal             0x00000001\r
-\r
-/*--------------------- CLOCK Configuration -------------------------------\r
-//\r
-// <e> Main Clock Configuration\r
-//     <o1.0..1> CPU clock divider\r
-//                     <0=> fCPU = fSYS \r
-//                     <1=> fCPU = fSYS / 2\r
-//     <o2.0..1>  Peripheral Bus clock divider\r
-//                     <0=> fPB        = fCPU\r
-//                     <1=> fPB        = fCPU / 2\r
-//     <o3.0..1>  CCU Bus clock divider\r
-//                     <0=> fCCU = fCPU\r
-//                     <1=> fCCU = fCPU / 2\r
-//\r
-// </e>\r
-// \r
-*/\r
-\r
-#define SCU_CLOCK_SETUP               1\r
-#define        SCU_CPUCLKCR_DIV                0x00000000\r
-#define        SCU_PBCLKCR_DIV             0x00000000\r
-#define        SCU_CCUCLKCR_DIV                0x00000000\r
-\r
-\r
-\r
-/*--------------------- USB CLOCK Configuration ---------------------------\r
-//\r
-// <e> USB Clock Configuration\r
-//\r
-// </e>\r
-// \r
-*/\r
-\r
-#define SCU_USB_CLOCK_SETUP              0\r
-\r
-\r
-/*--------------------- CLOCKOUT Configuration -------------------------------\r
-//\r
-// <e> Clock OUT Configuration\r
-//     <o1.0..1>   Clockout Source Selection\r
-//                     <0=> System Clock\r
-//                     <2=> USB Clock\r
-//                     <3=> Divided value of PLL Clock\r
-//     <o2.0..1>   Clockout Pin Selection\r
-//                     <0=> P1.15\r
-//                     <1=> P0.8\r
-//                     \r
-//\r
-// </e>\r
-// \r
-*/\r
-\r
-#define SCU_CLOCKOUT_SETUP              0  // recommended to keep disabled\r
-#define        SCU_CLOCKOUT_SOURCE             0x00000000\r
-#define        SCU_CLOCKOUT_PIN                0x00000000\r
-\r
-/*----------------------------------------------------------------------------\r
-  static functions declarations\r
- *----------------------------------------------------------------------------*/\r
-#if (SCU_CLOCK_SETUP == 1)\r
-static int SystemClockSetup(void);\r
-#endif\r
-\r
-#if (SCU_USB_CLOCK_SETUP == 1)\r
-static void USBClockSetup(void);\r
-#endif\r
-\r
-/**\r
-  * @brief  Setup the microcontroller system.\r
-  *         Initialize the PLL and update the \r
-  *         SystemCoreClock variable.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-void SystemInit(void)\r
-{\r
-/* Setup the WDT */\r
-#if (WDT_SETUP == 1)\r
-WDT->CTR &= ~WDTENB_nVal; \r
-#endif\r
-\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
-SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */\r
-               (3UL << 11*2)  );               /* set CP11 Full Access */\r
-#endif\r
-\r
-/* Disable branch prediction - PCON.PBS = 1 */\r
-PREF->PCON |= (PREF_PCON_PBS_Msk);\r
-\r
-/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
-SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
-\r
-/* Setup the clockout */\r
-/* README README README README README README README README README README */\r
-/*\r
- * Please use the CLOCKOUT feature with diligence. Use this only if you know\r
- * what you are doing.\r
- *\r
- * You must be aware that the settings below can potentially be in conflict\r
- * with DAVE code generation engine preferences.\r
- *\r
- * Even worse, the setting below configures the ports as output ports while in\r
- * reality, the board on which this chip is mounted may have a source driving\r
- * the ports.\r
- *\r
- * So use this feature only when you are absolutely sure that the port must \r
- * indeed be configured as an output AND you are NOT linking this startup code\r
- * with code that was generated by DAVE code engine.\r
- */\r
-#if (SCU_CLOCKOUT_SETUP == 1)\r
-SCU_CLK->EXTCLKCR      |= SCU_CLOCKOUT_SOURCE;\r
-\r
-if (SCU_CLOCKOUT_PIN) {\r
-              PORT0->IOCR8 = 0x00000088;  /*P0.8 --> ALT1 select +  HWSEL */\r
-              PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
-              }\r
-else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */\r
-#endif\r
-\r
-/* Setup the System clock */ \r
-#if (SCU_CLOCK_SETUP == 1)\r
-SystemClockSetup();\r
-#endif\r
-\r
-/* Setup the USB PL */ \r
-#if (SCU_USB_CLOCK_SETUP == 1)\r
-USBClockSetup();\r
-#endif\r
-\r
-}\r
-\r
-\r
-/**\r
-  * @brief  Update SystemCoreClock according to Clock Register Values\r
-  * @note   -  \r
-  * @param  None\r
-  * @retval None\r
-  */\r
-void SystemCoreClockUpdate(void)\r
-{\r
-\r
-/*----------------------------------------------------------------------------\r
-  Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/\r
-\r
-}\r
-\r
-\r
-/**\r
-  * @brief  -\r
-  * @note   -  \r
-  * @param  None\r
-  * @retval None\r
-  */\r
-#if (SCU_CLOCK_SETUP == 1)\r
-static int SystemClockSetup(void)\r
-{\r
-/* enable PLL first */\r
-  SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | \r
-                                                                                                       SCU_PLL_PLLCON0_PLLPWD_Msk);\r
-\r
-/* Enable OSC_HP */\r
-  if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
-  {\r
-   /* Enable the OSC_HP*/\r
-   SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4);       \r
-   /* Setup OSC WDG devider */\r
-   SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);         \r
-   /* Select external OSC as PLL input */\r
-   SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
-   /* Restart OSC Watchdog */\r
-   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
-\r
-   do \r
-   {\r
-       ;  /* here a timeout need to be added */\r
-   }while(!( (SCU_PLL->PLLSTAT) & \r
-                                          (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |\r
-                                           SCU_PLL_PLLSTAT_PLLSP_Msk)\r
-                                        )\r
-         ); \r
-\r
-  }\r
-\r
-/* Setup Main PLL */\r
-   /* Select FOFI as system clock */\r
-   if(SCU_CLK->SYSCLKCR != 0X000000)\r
-         SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/\r
-\r
-        /* Go to bypass the Main PLL */\r
-   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
-\r
-        /* disconnect OSC_HP to PLL */\r
-   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
-\r
-        /* Setup devider settings for main PLL */\r
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
-                                     (PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24));\r
-\r
-        /* we may have to set OSCDISCDIS */\r
-   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
-\r
-        /* connect OSC_HP to PLL */\r
-   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
-\r
-        /* restart PLL Lock detection */\r
-   SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
-\r
-        /* wait for PLL Lock */\r
-   while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk));\r
-\r
-       /* Go back to the Main PLL */\r
-   SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
-\r
-   /*********************************************************\r
-   here we need to setup the system clock divider\r
-   *********************************************************/\r
-\r
-       SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
-       SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;     \r
-       SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
-\r
-   /* Switch system clock to PLL */\r
-   SCU_CLK->SYSCLKCR |=  0x00010000; \r
-                                                                                                                         \r
-   /*********************************************************\r
-   here the ramp up of the system clock starts\r
-   *********************************************************/\r
-    /* Delay for next K2 step ~50µs */\r
-   /********************************/\r
-   /* Set reload register */\r
-   SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
-   /* Load the SysTick Counter Value */\r
-   SysTick->VAL   = 0;                                         \r
-\r
-   /* Enable SysTick IRQ and SysTick Timer */\r
-   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
-                   SysTick_CTRL_ENABLE_Msk;                    \r
-   \r
-        /* wait for ~50µs  */\r
-   while (SysTick->VAL >= 100);                                                                   \r
-\r
-   /* Stop SysTick Timer */\r
-   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 \r
-   /********************************/\r
-\r
-   /* Setup devider settings for main PLL */\r
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
-                                     (PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24));\r
-\r
-   /* Delay for next K2 step ~50µs */\r
-   /********************************/\r
-   SysTick->LOAD  = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
-   /* Load the SysTick Counter Value */\r
-   SysTick->VAL   = 0;\r
-\r
-   /* Enable SysTick IRQ and SysTick Timer */\r
-   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
-                                                                   \r
-   /* Wait for ~50µs  */\r
-   while (SysTick->VAL >= 100);                                                                   \r
-\r
-   /* Stop SysTick Timer */\r
-   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 \r
-   /********************************/\r
-\r
-   /* Setup devider settings for main PLL */\r
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | \r
-                                                                                           (PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24));\r
-\r
-   /* Delay for next K2 step ~50µs */\r
-   /********************************/\r
-   SysTick->LOAD  = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
-\r
-   /* Load the SysTick Counter Value */\r
-   SysTick->VAL   = 0;                                         \r
-\r
-   /* Enable SysTick IRQ and SysTick Timer */\r
-   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r
-                                       \r
-   /* Wait for ~50µs  */\r
-   while (SysTick->VAL >= 100);                                                                   \r
-\r
-   /* Stop SysTick Timer */\r
-   SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 \r
-   /********************************/\r
-\r
-   /* Setup devider settings for main PLL */\r
-   SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) | \r
-                                                               (PLL_PDIV<<24));\r
-\r
-        /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
-   SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | \r
-                                                                           SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  \r
-\r
-   return(1);\r
-\r
-}\r
-#endif\r
-\r
-/**\r
-  * @brief  -\r
-  * @note   -  \r
-  * @param  None\r
-  * @retval None\r
-  */\r
-#if(SCU_USB_CLOCK_SETUP == 1)\r
-static void USBClockSetup(void)\r
-{\r
-/* enable PLL first */\r
-  SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | \r
-                                                                                                      SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
-\r
-/* check and if not already running enable OSC_HP */\r
-  if(!((SCU_PLL->PLLSTAT) & \r
-                        (SCU_PLL_PLLSTAT_PLLHV_Msk | \r
-        SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)))\r
-  {\r
-         if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
-         {\r
-       \r
-          SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4);        /*enable the OSC_HP*/\r
-          /* setup OSC WDG devider */\r
-          SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16);         \r
-          /* select external OSC as PLL input */\r
-          SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
-          /* restart OSC Watchdog */\r
-          SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
-       \r
-          do \r
-          {\r
-               ;  /* here a timeout need to be added */\r
-          }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | \r
-               SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))); \r
-       \r
-         }\r
-  }\r
-\r
-\r
-/* Setup USB PLL */\r
-   /* Go to bypass the Main PLL */\r
-   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
-   /* disconnect OSC_FI to PLL */\r
-   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
-   /* Setup devider settings for main PLL */\r
-   SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24));\r
-   /* we may have to set OSCDISCDIS */\r
-   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
-   /* connect OSC_FI to PLL */\r
-   SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
-   /* restart PLL Lock detection */\r
-   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
-   /* wait for PLL Lock */\r
-   while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
- }\r
-#endif
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/XMC4500.h
deleted file mode 100644 (file)
index 20791a8..0000000
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/XMC4500.h
+++ /dev/null
@@ -1,20654 +0,0 @@
-/****************************************************************************/\r
-/**\r
-* @file     XMC4500.h\r
-*           XMC4000 Device Series\r
-* @version  V1.14\r
-* @date     23 Feb 2012\r
-*\r
-Copyright (C) 2011-2012 Infineon Technologies AG. All rights reserved.\r
-*\r
-*\r
-* @par\r
-* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon's\r
-* microcontrollers.  This file can be freely distributed\r
-* within development tools that are supporting such microcontrollers.\r
-*\r
-* @par\r
-* THIS SOFTWARE IS PROVIDED AS IS.  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
-* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
-* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
-*\r
-******************************************************************************/\r
-\r
-/** @mainpage  CMSIS device specific (XMC4500) peripheral access layer.\r
-*\r
-* @par\r
-* This file provides the XMC4500 Device specific peripheral access layer for\r
-* all peripherals. This file contains all the data structures and the address\r
-* mapping of the device specific peripherals.\r
-* @par\r
-* The file also provides interrupt numbers (IRQHandler) for all core and device\r
-* specific exceptions and interrupts.\r
-*\r
-*/\r
-\r
-#ifndef __XMC4500_H__\r
-#define __XMC4500_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-\r
-\r
-/********************************************\r
-** Start of section using anonymous unions **\r
-*********************************************/\r
-#if defined(__CC_ARM)\r
-  #pragma push\r
-  #pragma anon_unions\r
-#elif defined(__ICCARM__)\r
-  #pragma language=extended\r
-#elif defined(__GNUC__)\r
-  /* anonymous unions are enabled by default */\r
-  #elif defined(__TMS470__)\r
-/* anonymous unions are enabled by default */\r
-#elif defined(__TASKING__)\r
-  #pragma warning 586\r
-#else\r
-  #warning Not supported compiler type\r
-#endif\r
-\r
-/*\r
-* ==========================================================================\r
-* --------------------- __NVIC_PRIO_BITS -----------------------------------\r
-* ==========================================================================\r
-*/\r
-#ifndef __NVIC_PRIO_BITS\r
-#define __NVIC_PRIO_BITS (6)\r
-#endif\r
-\r
-/*\r
-* ==========================================================================\r
-* ----------------------------- M4 Stuff -----------------------------------\r
-* ==========================================================================\r
-*/\r
-#define __CM4_REV                      0x0001    /**< Core revision r0p1 */\r
-#define __MPU_PRESENT                  1         /**< MPU present or not */\r
-#define __Vendor_SysTickConfig         0         /**< Set to 1 if different SysTick Config is used */\r
-#define __FPU_PRESENT                  1         /**< FPU present or not */\r
-\r
-/*\r
-* ==========================================================================\r
-* ---------- Interrupt Number Definition -----------------------------------\r
-* ==========================================================================\r
-*/\r
-\r
-typedef enum IRQn\r
-{\r
-/******  Cortex-M3 Processor Exceptions Numbers **********************************/\r
-NMI_IRQn            = -14,      /*!<  2 Non Maskable Interrupt                */\r
-MemManage_IRQn         = -12,      /*!<  4 Cortex-M4 Memory Management Interrupt */\r
-BusFault_IRQn          = -11,      /*!<  5 Cortex-M4 Bus Fault Interrupt         */\r
-UsageFault_IRQn        = -10,      /*!<  6 Cortex-M4 Usage Fault Interrupt       */\r
-SVC_IRQn               = -5,       /*!< 11 Cortex-M4 SV Call Interrupt           */\r
-DebugMon_IRQn          = -4,       /*!< 12 Cortex-M4 Debug Monitor Interrupt     */\r
-PendSV_IRQn            = -2,       /*!< 14 Cortex-M4 Pend SV Interrupt           */\r
-SysTick_IRQn           = -1,       /*!< 15 Cortex-M4 System Tick Interrupt       */\r
-\r
-/******  XMC45xx Specific Interrupt Numbers ***************************************/\r
-SCU_0_IRQn              =   0,      /*!< SCU SR0 Interrupt                        */\r
-ERU0_0_IRQn             =   1,      /*!< SCU SR1 Interrupt                        */\r
-ERU0_1_IRQn             =   2,      /*!< SCU SR2 Interrupt                        */\r
-ERU0_2_IRQn             =   3,      /*!< SCU SR3 Interrupt                        */\r
-ERU0_3_IRQn             =   4,      /*!< SCU SR4 Interrupt                        */\r
-ERU1_0_IRQn             =   5,      /*!< SCU SR5 Interrupt                        */\r
-ERU1_1_IRQn             =   6,      /*!< SCU SR6 Interrupt                        */\r
-ERU1_2_IRQn             =   7,      /*!< SCU SR7 Interrupt                        */\r
-ERU1_3_IRQn             =   8,      /*!< SCU SR8 Interrupt                        */\r
-PMU0_0_IRQn             =  12,      /*!< PMU SR0 Interrupt                        */\r
-VADC0_C0_0_IRQn         =  14,      /*!< VADC SR0 Interrupt                       */\r
-VADC0_C0_1_IRQn         =  15,      /*!< VADC SR1 Interrupt                       */\r
-VADC0_C0_2_IRQn         =  16,      /*!< VADC SR2 Interrupt                       */\r
-VADC0_C0_3_IRQn         =  17,      /*!< VADC SR3 Interrupt                       */\r
-VADC0_G0_0_IRQn         =  18,      /*!< VADC SR4 Interrupt                       */\r
-VADC0_G0_1_IRQn         =  19,      /*!< VADC SR5 Interrupt                       */\r
-VADC0_G0_2_IRQn         =  20,      /*!< VADC SR6 Interrupt                       */\r
-VADC0_G0_3_IRQn         =  21,      /*!< VADC SR7 Interrupt                       */\r
-VADC0_G1_0_IRQn         =  22,      /*!< VADC SR8 Interrupt                       */\r
-VADC0_G1_1_IRQn         =  23,      /*!< VADC SR9 Interrupt                       */\r
-VADC0_G1_2_IRQn         =  24,      /*!< VADC SR10 Interrupt                      */\r
-VADC0_G1_3_IRQn         =  25,      /*!< VADC SR11 Interrupt                      */\r
-VADC0_G2_0_IRQn         =  26,      /*!< VADC SR12 Interrupt                      */\r
-VADC0_G2_1_IRQn         =  27,      /*!< VADC SR13 Interrupt                      */\r
-VADC0_G2_2_IRQn         =  28,      /*!< VADC SR14 Interrupt                      */\r
-VADC0_G2_3_IRQn         =  29,      /*!< VADC SR15 Interrupt                      */\r
-VADC0_G3_0_IRQn         =  30,      /*!< VADC SR16 Interrupt                      */\r
-VADC0_G3_1_IRQn         =  31,      /*!< VADC SR17 Interrupt                      */\r
-VADC0_G3_2_IRQn         =  32,      /*!< VADC SR18 Interrupt                      */\r
-VADC0_G3_3_IRQn         =  33,      /*!< VADC SR19 Interrupt                      */\r
-DSD0_M_0_IRQn           =  34,      /*!< DSD SR0 Interrupt                        */\r
-DSD0_M_1_IRQn           =  35,      /*!< DSD SR1 Interrupt                        */\r
-DSD0_M_2_IRQn           =  36,      /*!< DSD SR2 Interrupt                        */\r
-DSD0_M_3_IRQn           =  37,      /*!< DSD SR3 Interrupt                        */\r
-DSD0_A_4_IRQn           =  38,      /*!< DSD SR4 Interrupt                        */\r
-DSD0_A_5_IRQn           =  39,      /*!< DSD SR5 Interrupt                        */\r
-DSD0_A_6_IRQn           =  40,      /*!< DSD SR6 Interrupt                        */\r
-DSD0_A_7_IRQn           =  41,      /*!< DSD SR7 Interrupt                        */\r
-DAC0_0_IRQn             =  42,      /*!< DAC SR0 Interrupt                        */\r
-DAC1_1_IRQn             =  43,      /*!< DAC SR1 Interrupt                        */\r
-CCU40_0_IRQn            =  44,      /*!< CCU40 SR0 Interrupt                      */\r
-CCU40_1_IRQn            =  45,      /*!< CCU40 SR1 Interrupt                      */\r
-CCU40_2_IRQn            =  46,      /*!< CCU40 SR2 Interrupt                      */\r
-CCU40_3_IRQn            =  47,      /*!< CCU40 SR3 Interrupt                      */\r
-CCU41_0_IRQn            =  48,      /*!< CCU41 SR0 Interrupt                      */\r
-CCU41_1_IRQn            =  49,      /*!< CCU41 SR1 Interrupt                      */\r
-CCU41_2_IRQn            =  50,      /*!< CCU41 SR2 Interrupt                      */\r
-CCU41_3_IRQn            =  51,      /*!< CCU41 SR3 Interrupt                      */\r
-CCU42_0_IRQn            =  52,      /*!< CCU42 SR0 Interrupt                      */\r
-CCU42_1_IRQn            =  53,      /*!< CCU42 SR1 Interrupt                      */\r
-CCU42_2_IRQn            =  54,      /*!< CCU42 SR2 Interrupt                      */\r
-CCU42_3_IRQn            =  55,      /*!< CCU42 SR3 Interrupt                      */\r
-CCU43_0_IRQn            =  56,      /*!< CCU43 SR0 Interrupt                      */\r
-CCU43_1_IRQn            =  57,      /*!< CCU43 SR1 Interrupt                      */\r
-CCU43_2_IRQn            =  58,      /*!< CCU43 SR2 Interrupt                      */\r
-CCU43_3_IRQn            =  59,      /*!< CCU43 SR3 Interrupt                      */\r
-CCU80_0_IRQn            =  60,      /*!< CCU80 SR0 Interrupt                      */\r
-CCU80_1_IRQn            =  61,      /*!< CCU80 SR1 Interrupt                      */\r
-CCU80_2_IRQn            =  62,      /*!< CCU80 SR2 Interrupt                      */\r
-CCU80_3_IRQn            =  63,      /*!< CCU80 SR3 Interrupt                      */\r
-CCU81_0_IRQn            =  64,      /*!< CCU81 SR0 Interrupt                      */\r
-CCU81_1_IRQn            =  65,      /*!< CCU81 SR1 Interrupt                      */\r
-CCU81_2_IRQn            =  66,      /*!< CCU81 SR2 Interrupt                      */\r
-CCU81_3_IRQn            =  67,      /*!< CCU81 SR3 Interrupt                      */\r
-POSIF0_0_IRQn           =  68,      /*!< POSIF0 SR0 Interrupt                     */\r
-POSIF0_1_IRQn           =  69,      /*!< POSIF0 SR1 Interrupt                     */\r
-POSIF1_0_IRQn           =  70,      /*!< POSIF1 SR0 Interrupt                     */\r
-POSIF1_1_IRQn           =  71,      /*!< POSIF1 SR1 Interrupt                     */\r
-CAN0_0_IRQn             =  76,      /*!< MCAN SR0 Interrupt                       */\r
-CAN0_1_IRQn             =  77,      /*!< MCAN SR1 Interrupt                       */\r
-CAN0_2_IRQn             =  78,      /*!< MCAN SR2 Interrupt                       */\r
-CAN0_3_IRQn             =  79,      /*!< MCAN SR3 Interrupt                       */\r
-CAN0_4_IRQn             =  80,      /*!< MCAN SR4 Interrupt                       */\r
-CAN0_5_IRQn             =  81,      /*!< MCAN SR5 Interrupt                       */\r
-CAN0_6_IRQn             =  82,      /*!< MCAN SR6 Interrupt                       */\r
-CAN0_7_IRQn             =  83,      /*!< MCAN SR7 Interrupt                       */\r
-USIC0_0_IRQn            =  84,      /*!< USIC0 SR0 Interrupt                      */\r
-USIC0_1_IRQn            =  85,      /*!< USIC0 SR1 Interrupt                      */\r
-USIC0_2_IRQn            =  86,      /*!< USIC0 SR2 Interrupt                      */\r
-USIC0_3_IRQn            =  87,      /*!< USIC0 SR3 Interrupt                      */\r
-USIC0_4_IRQn            =  88,      /*!< USIC0 SR4 Interrupt                      */\r
-USIC0_5_IRQn            =  89,      /*!< USIC0 SR5 Interrupt                      */\r
-USIC1_0_IRQn            =  90,      /*!< USIC1 SR0 Interrupt                      */\r
-USIC1_1_IRQn            =  91,      /*!< USIC1 SR1 Interrupt                      */\r
-USIC1_2_IRQn            =  92,      /*!< USIC1 SR2 Interrupt                      */\r
-USIC1_3_IRQn            =  93,      /*!< USIC1 SR3 Interrupt                      */\r
-USIC1_4_IRQn            =  94,      /*!< USIC1 SR4 Interrupt                      */\r
-USIC1_5_IRQn            =  95,      /*!< USIC1 SR5 Interrupt                      */\r
-USIC2_0_IRQn            =  96,      /*!< USIC2 SR0 Interrupt                      */\r
-USIC2_1_IRQn            =  97,      /*!< USIC2 SR1 Interrupt                      */\r
-USIC2_2_IRQn            =  98,      /*!< USIC2 SR2 Interrupt                      */\r
-USIC2_3_IRQn            =  99,      /*!< USIC2 SR3 Interrupt                      */\r
-USIC2_4_IRQn            = 100,      /*!< USIC2 SR4 Interrupt                      */\r
-USIC2_5_IRQn                                      = 101,      /*!< USIC2 SR5 Interrupt                      */\r
-LEDTS0_0_IRQn           = 102,      /*!< LEDTSU SR0 Interrupt                     */\r
-FCE0_0_IRQn             = 104,      /*!< FCE SR0 Interrupt                        */\r
-GPDMA0_0_IRQn           = 105,      /*!< GPDMA SR0 Interrupt                      */\r
-SDMMC0_0_IRQn           = 106,      /*!< MMCI SR0 Interrupt                       */\r
-USB0_0_IRQn             = 107,      /*!< USB SR0 Interrupt                        */\r
-ETH0_0_IRQn             = 108,      /*!< ETH SR0 Interrupt                        */\r
-GPDMA1_0_IRQn           = 110       /*!< GPDMA1 SR0 Interrupt                     */\r
-}IRQn_Type;\r
-\r
-\r
-/*\r
-* ==========================================================================\r
-* ----------- Processor and Core Peripheral Section ------------------------\r
-* ==========================================================================\r
-*/\r
-\r
-/** Macro to write new value to the bits in register */\r
-#define WR_REG(reg, mask, pos, val) {  \\r
-                     reg &= ~(mask);\\r
-                     reg |= (val << pos) & mask;\\r
-                    }\r
-\r
-/** Macro to read the bits in register */\r
-#define RD_REG(reg, mask, pos)            (((reg)&mask) >> pos)\r
-/** Macro to set the particular bit in register */\r
-#define SET_BIT(reg, pos)                 (reg) |= (1U<<pos)\r
-/** Macro to clear the particular bit in register */\r
-#define CLR_BIT(reg, pos)                 (reg) &= ~(1U<<pos)\r
-\r
-#include <core_cm4.h>    /* Cortex-M4 processor and core peripherals       */\r
-#include "system_XMC4500.h"\r
-\r
-/******************************************************************************/\r
-/*                Device Specific Peripheral registers structures             */\r
-/******************************************************************************/\r
-\r
-/***************************************************************************/\r
-/*                     CAN                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *CAN GLOBAL registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  CLC; /*!<CAN Clock Control Register Offset  0x0000*/\r
-__I  uint32_t  RESERVED1;\r
-__I uint32_t   ID; /*!<Module Identification Register Offset  0x0008*/\r
-__IO uint32_t  FDR; /*!<CAN Fractional Divider Register Offset  0x000C*/\r
-__I  uint32_t  RESERVED2[60];\r
-__I uint32_t   LIST[8]; /*!<List Register 0 Offset  0x0100*/\r
-__I  uint32_t  RESERVED3[8];\r
-__IO uint32_t  MSPND[8]; /*!<Message Pending Register 0 Offset  0x0140*/\r
-__I  uint32_t  RESERVED4[8];\r
-__I uint32_t   MSID[8]; /*!<Message Index Register 0 Offset  0x0180*/\r
-__I  uint32_t  RESERVED5[8];\r
-__IO uint32_t  MSIMASK; /*!<Message Index Mask Register Offset  0x01C0*/\r
-__IO uint32_t  PANCTR; /*!<Panel Control Register Offset  0x01C4*/\r
-__IO uint32_t  MCR; /*!<Module Control Register Offset  0x01C8*/\r
-__O uint32_t   MITR; /*!<Module Interrupt Trigger Register Offset  0x01CC*/\r
-}CAN_GLOBAL_TypeDef;\r
-\r
-  /*\r
-  *CAN NODE registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  NCR; /*!<Node 0 Control Register Offset  0x0200*/\r
-__IO uint32_t  NSR; /*!<Node 0 Status Register Offset  0x0204*/\r
-__IO uint32_t  NIPR; /*!<Node 0 Interrupt Pointer Register Offset  0x0208*/\r
-__IO uint32_t  NPCR; /*!<Node 0 Port Control Register Offset  0x020C*/\r
-__IO uint32_t  NBTR; /*!<Node 0 Bit Timing Register Offset  0x0210*/\r
-__IO uint32_t  NECNT; /*!<Node 0 Error Counter Register Offset  0x0214*/\r
-__IO uint32_t  NFCR; /*!<Node 0 Frame Counter Register Offset  0x0218*/\r
-}CAN_NODE_TypeDef;\r
-\r
-  /*\r
-  *CAN MO registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  MOFCR; /*!<Message Object 0 Function Control Register Offset  0x1000*/\r
-__IO uint32_t  MOFGPR; /*!<Message Object 0 FIFO/Gateway Pointer Register Offset  0x1004*/\r
-__IO uint32_t  MOIPR; /*!<Message Object 0 Interrupt Pointer Register Offset  0x1008*/\r
-__IO uint32_t  MOAMR; /*!<Message Object 0 Acceptance Mask Register Offset  0x100C*/\r
-__IO uint32_t  MODATAL; /*!<Message Object 0 Data Register Low Offset  0x1010*/\r
-__IO uint32_t  MODATAH; /*!<Message Object 0 Data Register High Offset  0x1014*/\r
-__IO uint32_t  MOAR; /*!<Message Object 0 Arbitration Register Offset  0x1018*/\r
-union\r
- {\r
-__O uint32_t   MOCTR; /*!<Message Object 0 Control Register Offset  0x101C*/\r
-__I uint32_t   MOSTAT; /*!<Message Object 0 Status Register Offset  0x101C*/\r
- };\r
-}CAN_MO_TypeDef;\r
-\r
-#define   CAN_BASE                      ((uint32_t)0x48014000U)\r
-#define   CAN_GLOBAL_BASE               (0x0000U)\r
-#define   CAN_NODE0_BASE                (0x0200U)\r
-#define   CAN_NODE1_BASE                (0x0300U)\r
-#define   CAN_NODE2_BASE                (0x0400U)\r
-#define   CAN_MO0_BASE          (0x1000U)\r
-#define   CAN_MO1_BASE          (0x1020U)\r
-#define   CAN_MO2_BASE          (0x1040U)\r
-#define   CAN_MO3_BASE          (0x1060U)\r
-#define   CAN_MO4_BASE          (0x1080U)\r
-#define   CAN_MO5_BASE          (0x10A0U)\r
-#define   CAN_MO6_BASE          (0x10C0U)\r
-#define   CAN_MO7_BASE          (0x10E0U)\r
-#define   CAN_MO8_BASE          (0x1100U)\r
-#define   CAN_MO9_BASE          (0x1120U)\r
-#define   CAN_MO10_BASE                 (0x1140U)\r
-#define   CAN_MO11_BASE                 (0x1160U)\r
-#define   CAN_MO12_BASE                 (0x1180U)\r
-#define   CAN_MO13_BASE                 (0x11A0U)\r
-#define   CAN_MO14_BASE                 (0x11C0U)\r
-#define   CAN_MO15_BASE                 (0x11E0U)\r
-#define   CAN_MO16_BASE                 (0x1200U)\r
-#define   CAN_MO17_BASE                 (0x1220U)\r
-#define   CAN_MO18_BASE                 (0x1240U)\r
-#define   CAN_MO19_BASE                 (0x1260U)\r
-#define   CAN_MO20_BASE                 (0x1280U)\r
-#define   CAN_MO21_BASE                 (0x12A0U)\r
-#define   CAN_MO22_BASE                 (0x12C0U)\r
-#define   CAN_MO23_BASE                 (0x12E0U)\r
-#define   CAN_MO24_BASE                 (0x1300U)\r
-#define   CAN_MO25_BASE                 (0x1320U)\r
-#define   CAN_MO26_BASE                 (0x1340U)\r
-#define   CAN_MO27_BASE                 (0x1360U)\r
-#define   CAN_MO28_BASE                 (0x1380U)\r
-#define   CAN_MO29_BASE                 (0x13A0U)\r
-#define   CAN_MO30_BASE                 (0x13C0U)\r
-#define   CAN_MO31_BASE                 (0x13E0U)\r
-#define   CAN_MO32_BASE                 (0x1400U)\r
-#define   CAN_MO33_BASE                 (0x1420U)\r
-#define   CAN_MO34_BASE                 (0x1440U)\r
-#define   CAN_MO35_BASE                 (0x1460U)\r
-#define   CAN_MO36_BASE                 (0x1480U)\r
-#define   CAN_MO37_BASE                 (0x14A0U)\r
-#define   CAN_MO38_BASE                 (0x14C0U)\r
-#define   CAN_MO39_BASE                 (0x14E0U)\r
-#define   CAN_MO40_BASE                 (0x1500U)\r
-#define   CAN_MO41_BASE                 (0x1520U)\r
-#define   CAN_MO42_BASE                 (0x1540U)\r
-#define   CAN_MO43_BASE                 (0x1560U)\r
-#define   CAN_MO44_BASE                 (0x1580U)\r
-#define   CAN_MO45_BASE                 (0x15A0U)\r
-#define   CAN_MO46_BASE                 (0x15C0U)\r
-#define   CAN_MO47_BASE                 (0x15E0U)\r
-#define   CAN_MO48_BASE                 (0x1600U)\r
-#define   CAN_MO49_BASE                 (0x1620U)\r
-#define   CAN_MO50_BASE                 (0x1640U)\r
-#define   CAN_MO51_BASE                 (0x1660U)\r
-#define   CAN_MO52_BASE                 (0x1680U)\r
-#define   CAN_MO53_BASE                 (0x16A0U)\r
-#define   CAN_MO54_BASE                 (0x16C0U)\r
-#define   CAN_MO55_BASE                 (0x16E0U)\r
-#define   CAN_MO56_BASE                 (0x1700U)\r
-#define   CAN_MO57_BASE                 (0x1720U)\r
-#define   CAN_MO58_BASE                 (0x1740U)\r
-#define   CAN_MO59_BASE                 (0x1760U)\r
-#define   CAN_MO60_BASE                 (0x1780U)\r
-#define   CAN_MO61_BASE                 (0x17A0U)\r
-#define   CAN_MO62_BASE                 (0x17C0U)\r
-#define   CAN_MO63_BASE                 (0x17E0U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   CAN           ((CAN_GLOBAL_TypeDef*)(CAN_BASE + CAN_GLOBAL_BASE))\r
-#define   CAN_NODE0             ((CAN_NODE_TypeDef*)(CAN_BASE + CAN_NODE0_BASE))\r
-#define   CAN_NODE1             ((CAN_NODE_TypeDef*)(CAN_BASE + CAN_NODE1_BASE))\r
-#define   CAN_NODE2             ((CAN_NODE_TypeDef*)(CAN_BASE + CAN_NODE2_BASE))\r
-#define   CAN_MO0               ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO0_BASE))\r
-#define   CAN_MO1               ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO1_BASE))\r
-#define   CAN_MO2               ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO2_BASE))\r
-#define   CAN_MO3               ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO3_BASE))\r
-#define   CAN_MO4               ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO4_BASE))\r
-#define   CAN_MO5               ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO5_BASE))\r
-#define   CAN_MO6               ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO6_BASE))\r
-#define   CAN_MO7               ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO7_BASE))\r
-#define   CAN_MO8               ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO8_BASE))\r
-#define   CAN_MO9               ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO9_BASE))\r
-#define   CAN_MO10              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO10_BASE))\r
-#define   CAN_MO11              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO11_BASE))\r
-#define   CAN_MO12              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO12_BASE))\r
-#define   CAN_MO13              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO13_BASE))\r
-#define   CAN_MO14              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO14_BASE))\r
-#define   CAN_MO15              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO15_BASE))\r
-#define   CAN_MO16              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO16_BASE))\r
-#define   CAN_MO17              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO17_BASE))\r
-#define   CAN_MO18              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO18_BASE))\r
-#define   CAN_MO19              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO19_BASE))\r
-#define   CAN_MO20              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO20_BASE))\r
-#define   CAN_MO21              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO21_BASE))\r
-#define   CAN_MO22              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO22_BASE))\r
-#define   CAN_MO23              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO23_BASE))\r
-#define   CAN_MO24              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO24_BASE))\r
-#define   CAN_MO25              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO25_BASE))\r
-#define   CAN_MO26              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO26_BASE))\r
-#define   CAN_MO27              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO27_BASE))\r
-#define   CAN_MO28              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO28_BASE))\r
-#define   CAN_MO29              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO29_BASE))\r
-#define   CAN_MO30              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO30_BASE))\r
-#define   CAN_MO31              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO31_BASE))\r
-#define   CAN_MO32              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO32_BASE))\r
-#define   CAN_MO33              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO33_BASE))\r
-#define   CAN_MO34              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO34_BASE))\r
-#define   CAN_MO35              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO35_BASE))\r
-#define   CAN_MO36              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO36_BASE))\r
-#define   CAN_MO37              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO37_BASE))\r
-#define   CAN_MO38              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO38_BASE))\r
-#define   CAN_MO39              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO39_BASE))\r
-#define   CAN_MO40              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO40_BASE))\r
-#define   CAN_MO41              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO41_BASE))\r
-#define   CAN_MO42              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO42_BASE))\r
-#define   CAN_MO43              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO43_BASE))\r
-#define   CAN_MO44              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO44_BASE))\r
-#define   CAN_MO45              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO45_BASE))\r
-#define   CAN_MO46              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO46_BASE))\r
-#define   CAN_MO47              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO47_BASE))\r
-#define   CAN_MO48              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO48_BASE))\r
-#define   CAN_MO49              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO49_BASE))\r
-#define   CAN_MO50              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO50_BASE))\r
-#define   CAN_MO51              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO51_BASE))\r
-#define   CAN_MO52              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO52_BASE))\r
-#define   CAN_MO53              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO53_BASE))\r
-#define   CAN_MO54              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO54_BASE))\r
-#define   CAN_MO55              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO55_BASE))\r
-#define   CAN_MO56              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO56_BASE))\r
-#define   CAN_MO57              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO57_BASE))\r
-#define   CAN_MO58              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO58_BASE))\r
-#define   CAN_MO59              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO59_BASE))\r
-#define   CAN_MO60              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO60_BASE))\r
-#define   CAN_MO61              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO61_BASE))\r
-#define   CAN_MO62              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO62_BASE))\r
-#define   CAN_MO63              ((CAN_MO_TypeDef*)(CAN_BASE + CAN_MO63_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     CCU4x                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *CAPCOM4 Global Registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  GCTRL; /*!<Global Control Register Offset  0x0000*/\r
-__I uint32_t   GSTAT; /*!<Global Status Register Offset  0x0004*/\r
-__O uint32_t   GIDLS; /*!<Global Idle Set Offset  0x0008*/\r
-__O uint32_t   GIDLC; /*!<Global Idle Clear Offset  0x000C*/\r
-__O uint32_t   GCSS; /*!<Global Channel Set Offset  0x0010*/\r
-__O uint32_t   GCSC; /*!<Global Channel Clear Offset  0x0014*/\r
-__I uint32_t   GCST; /*!<Global Channel Status Offset  0x0018*/\r
-__I  uint32_t  RESERVED1[13];\r
-__I uint32_t   ECRD; /*!<Extended Capture Mode Read Offset  0x0050*/\r
-__I  uint32_t  RESERVED2[11];\r
-__I uint32_t   MIDR; /*!<Module Identification Offset  0x0080*/\r
-}CCU4_GLOBAL_TypeDef;\r
-\r
-  /*\r
-  *CC40 Registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  INS; /*!<Input Selector Configuration Offset  0x0100*/\r
-__IO uint32_t  CMC; /*!<Connection Matrix Control Offset  0x0104*/\r
-__I uint32_t   TCST; /*!<Slice Timer Status Offset  0x0108*/\r
-__O uint32_t   TCSET; /*!<Slice Timer Run Set Offset  0x010C*/\r
-__O uint32_t   TCCLR; /*!<Slice Timer Clear Offset  0x0110*/\r
-__IO uint32_t  TC; /*!<Slice Timer Control Offset  0x0114*/\r
-__IO uint32_t  PSL; /*!<Passive Level Config Offset  0x0118*/\r
-__I uint32_t   DIT; /*!<Dither Config Offset  0x011C*/\r
-__IO uint32_t  DITS; /*!<Dither Shadow Register Offset  0x0120*/\r
-__IO uint32_t  PSC; /*!<Prescaler Control Offset  0x0124*/\r
-__IO uint32_t  FPC; /*!<Floating Prescaler Control Offset  0x0128*/\r
-__IO uint32_t  FPCS; /*!<Floating Prescaler Shadow Offset  0x012C*/\r
-__I uint32_t   PR; /*!<Timer Period Value Offset  0x0130*/\r
-__IO uint32_t  PRS; /*!<Timer Shadow Period Value Offset  0x0134*/\r
-__I uint32_t   CR; /*!<Timer Compare Value Offset  0x0138*/\r
-__IO uint32_t  CRS; /*!<Timer Shadow Compare Value Offset  0x013C*/\r
-__I  uint32_t  RESERVED1[12];\r
-__IO uint32_t  TIMER; /*!<Timer Value Offset  0x0170*/\r
-__I uint32_t   CV[4]; /*!<Capture Register 0 Offset  0x0174*/\r
-__I  uint32_t  RESERVED2[7];\r
-__I uint32_t   INTS; /*!<Interrupt Status Offset  0x01A0*/\r
-__IO uint32_t  INTE; /*!<Interrupt Enable Control Offset  0x01A4*/\r
-__IO uint32_t  SRS; /*!<Service Request Selector Offset  0x01A8*/\r
-__O uint32_t   SWS; /*!<Interrupt Status Set Offset  0x01AC*/\r
-__O uint32_t   SWR; /*!<Interrupt Status Clear Offset  0x01B0*/\r
-}CCU4_CC4_TypeDef;\r
-\r
-#define   CCU40_BASE                    ((uint32_t)0x4000C000U)\r
-#define   CCU41_BASE                    ((uint32_t)0x40010000U)\r
-#define   CCU42_BASE                    ((uint32_t)0x40014000U)\r
-#define   CCU43_BASE                    ((uint32_t)0x48004000U)\r
-#define   CCU4_GLOBAL_BASE              (0x0000U)\r
-#define   CCU40_CC40_BASE               (0x0100U)\r
-#define   CCU40_CC41_BASE               (0x0200U)\r
-#define   CCU40_CC42_BASE               (0x0300U)\r
-#define   CCU40_CC43_BASE               (0x0400U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   CCU40                 ((CCU4_GLOBAL_TypeDef*)(CCU40_BASE + CCU4_GLOBAL_BASE))\r
-#define   CCU40_CC40            ((CCU4_CC4_TypeDef*)(CCU40_BASE + CCU40_CC40_BASE))\r
-#define   CCU40_CC41            ((CCU4_CC4_TypeDef*)(CCU40_BASE + CCU40_CC41_BASE))\r
-#define   CCU40_CC42            ((CCU4_CC4_TypeDef*)(CCU40_BASE + CCU40_CC42_BASE))\r
-#define   CCU40_CC43            ((CCU4_CC4_TypeDef*)(CCU40_BASE + CCU40_CC43_BASE))\r
-#define   CCU41                 ((CCU4_GLOBAL_TypeDef*)(CCU41_BASE + CCU4_GLOBAL_BASE))\r
-#define   CCU41_CC40            ((CCU4_CC4_TypeDef*)(CCU41_BASE + CCU40_CC40_BASE))\r
-#define   CCU41_CC41            ((CCU4_CC4_TypeDef*)(CCU41_BASE + CCU40_CC41_BASE))\r
-#define   CCU41_CC42            ((CCU4_CC4_TypeDef*)(CCU41_BASE + CCU40_CC42_BASE))\r
-#define   CCU41_CC43            ((CCU4_CC4_TypeDef*)(CCU41_BASE + CCU40_CC43_BASE))\r
-#define   CCU42                 ((CCU4_GLOBAL_TypeDef*)(CCU42_BASE + CCU4_GLOBAL_BASE))\r
-#define   CCU42_CC40            ((CCU4_CC4_TypeDef*)(CCU42_BASE + CCU40_CC40_BASE))\r
-#define   CCU42_CC41            ((CCU4_CC4_TypeDef*)(CCU42_BASE + CCU40_CC41_BASE))\r
-#define   CCU42_CC42            ((CCU4_CC4_TypeDef*)(CCU42_BASE + CCU40_CC42_BASE))\r
-#define   CCU42_CC43            ((CCU4_CC4_TypeDef*)(CCU42_BASE + CCU40_CC43_BASE))\r
-#define   CCU43                 ((CCU4_GLOBAL_TypeDef*)(CCU43_BASE + CCU4_GLOBAL_BASE))\r
-#define   CCU43_CC40            ((CCU4_CC4_TypeDef*)(CCU43_BASE + CCU40_CC40_BASE))\r
-#define   CCU43_CC41            ((CCU4_CC4_TypeDef*)(CCU43_BASE + CCU40_CC41_BASE))\r
-#define   CCU43_CC42            ((CCU4_CC4_TypeDef*)(CCU43_BASE + CCU40_CC42_BASE))\r
-#define   CCU43_CC43            ((CCU4_CC4_TypeDef*)(CCU43_BASE + CCU40_CC43_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     CCU8x                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *CAPCOM8 Global Registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  GCTRL; /*!<Global Control Register Offset  0x0000*/\r
-__I uint32_t   GSTAT; /*!<Global Status Register Offset  0x0004*/\r
-__O uint32_t   GIDLS; /*!<Global Idle Set Offset  0x0008*/\r
-__O uint32_t   GIDLC; /*!<Global Idle Clear Offset  0x000C*/\r
-__O uint32_t   GCSS; /*!<Global Channel Set Offset  0x0010*/\r
-__O uint32_t   GCSC; /*!<Global Channel Clear Offset  0x0014*/\r
-__I uint32_t   GCST; /*!<Global Channel status Offset  0x0018*/\r
-__IO uint32_t  GPCHK; /*!<Parity Checker Configuration Offset  0x001C*/\r
-__I  uint32_t  RESERVED1[12];\r
-__I uint32_t   ECRD; /*!<Extended Capture Mode Read Offset  0x0050*/\r
-__I  uint32_t  RESERVED2[11];\r
-__I uint32_t   MIDR; /*!<Module Identification Offset  0x0080*/\r
-}CCU8_GLOBAL_TypeDef;\r
-\r
-  /*\r
-  *CC8x Registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  INS; /*!<Input Selector Configuration Offset  0x0100*/\r
-__IO uint32_t  CMC; /*!<Connection Matrix Control Offset  0x0104*/\r
-__I uint32_t   TCST; /*!<Slice Timer Status Offset  0x0108*/\r
-__O uint32_t   TCSET; /*!<Slice Timer Run Set Offset  0x010C*/\r
-__O uint32_t   TCCLR; /*!<Slice Timer Clear Offset  0x0110*/\r
-__IO uint32_t  TC; /*!<Slice Timer Control Offset  0x0114*/\r
-__IO uint32_t  PSL; /*!<Passive Level Config Offset  0x0118*/\r
-__I uint32_t   DIT; /*!<Dither Config Offset  0x011C*/\r
-__IO uint32_t  DITS; /*!<Dither Shadow Register Offset  0x0120*/\r
-__IO uint32_t  PSC; /*!<Prescaler Control Offset  0x0124*/\r
-__IO uint32_t  FPC; /*!<Floating Prescaler Control Offset  0x0128*/\r
-__IO uint32_t  FPCS; /*!<Floating Prescaler Shadow Offset  0x012C*/\r
-__I uint32_t   PR; /*!<Timer Period Value Offset  0x0130*/\r
-__IO uint32_t  PRS; /*!<Timer Shadow Period Value Offset  0x0134*/\r
-__I uint32_t   CR1; /*!<Channel 1 Compare Value Offset  0x0138*/\r
-__IO uint32_t  CR1S; /*!<Channel 1 Compare Shadow Value Offset  0x013C*/\r
-__I uint32_t   CR2; /*!<Channel 2 Compare Value Offset  0x0140*/\r
-__IO uint32_t  CR2S; /*!<Channel 2 Compare Shadow Value Offset  0x0144*/\r
-__IO uint32_t  CHC; /*!<Channel Control Offset  0x0148*/\r
-__IO uint32_t  DTC; /*!<Dead Time Control Offset  0x014C*/\r
-__IO uint32_t  DC1R; /*!<Channel 1 Dead Time Values Offset  0x0150*/\r
-__IO uint32_t  DC2R; /*!<Channel 2 Dead Time Values Offset  0x0154*/\r
-__I  uint32_t  RESERVED1[6];\r
-__IO uint32_t  TIMER; /*!<Timer Value Offset  0x0170*/\r
-__I uint32_t   CV[4]; /*!<Capture Register 0 Offset  0x0174*/\r
-__I  uint32_t  RESERVED2[7];\r
-__I uint32_t   INTS; /*!<Interrupt Status Offset  0x01A0*/\r
-__IO uint32_t  INTE; /*!<Interrupt Enable Control Offset  0x01A4*/\r
-__IO uint32_t  SRS; /*!<Service Request Selector Offset  0x01A8*/\r
-__O uint32_t   SWS; /*!<Interrupt Status Set Offset  0x01AC*/\r
-__O uint32_t   SWR; /*!<Interrupt Status Clear Offset  0x01B0*/\r
-}CCU8_CC8_TypeDef;\r
-\r
-#define   CCU80_BASE                    ((uint32_t)0x40020000U)\r
-#define   CCU81_BASE                    ((uint32_t)0x40024000U)\r
-#define   CCU8_GLOBAL_BASE              (0x0000U)\r
-#define   CCU80_CC80_BASE               (0x0100U)\r
-#define   CCU80_CC81_BASE               (0x0200U)\r
-#define   CCU80_CC82_BASE               (0x0300U)\r
-#define   CCU80_CC83_BASE               (0x0400U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   CCU80                 ((CCU8_GLOBAL_TypeDef*)(CCU80_BASE + CCU8_GLOBAL_BASE))\r
-#define   CCU80_CC80            ((CCU8_CC8_TypeDef*)(CCU80_BASE + CCU80_CC80_BASE))\r
-#define   CCU80_CC81            ((CCU8_CC8_TypeDef*)(CCU80_BASE + CCU80_CC81_BASE))\r
-#define   CCU80_CC82            ((CCU8_CC8_TypeDef*)(CCU80_BASE + CCU80_CC82_BASE))\r
-#define   CCU80_CC83            ((CCU8_CC8_TypeDef*)(CCU80_BASE + CCU80_CC83_BASE))\r
-#define   CCU81                 ((CCU8_GLOBAL_TypeDef*)(CCU81_BASE + CCU8_GLOBAL_BASE))\r
-#define   CCU81_CC80            ((CCU8_CC8_TypeDef*)(CCU81_BASE + CCU80_CC80_BASE))\r
-#define   CCU81_CC81            ((CCU8_CC8_TypeDef*)(CCU81_BASE + CCU80_CC81_BASE))\r
-#define   CCU81_CC82            ((CCU8_CC8_TypeDef*)(CCU81_BASE + CCU80_CC82_BASE))\r
-#define   CCU81_CC83            ((CCU8_CC8_TypeDef*)(CCU81_BASE + CCU80_CC83_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     DAC                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *DAC Kernel Registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   ID; /*!<Module Identification Register Offset  0x0000*/\r
-__IO uint32_t  DAC0CFG0; /*!<DAC0 Configuration Register 0 Offset  0x0004*/\r
-__IO uint32_t  DAC0CFG1; /*!<DAC0 Configuration Register 1 Offset  0x0008*/\r
-__IO uint32_t  DAC1CFG0; /*!<DAC1 Configuration Register 0 Offset  0x000C*/\r
-__IO uint32_t  DAC1CFG1; /*!<DAC1 Configuration Register 1 Offset  0x0010*/\r
-__IO uint32_t  DAC0DATA; /*!<DAC0 Data Register Offset  0x0014*/\r
-__IO uint32_t  DAC1DATA; /*!<DAC1 Data Register Offset  0x0018*/\r
-__IO uint32_t  DAC01DATA; /*!<DAC01 Data Register Offset  0x001C*/\r
-__IO uint32_t  DAC0PATL; /*!<DAC0 Lower Pattern Register Offset  0x0020*/\r
-__IO uint32_t  DAC0PATH; /*!<DAC0 Higher Pattern Register Offset  0x0024*/\r
-__IO uint32_t  DAC1PATL; /*!<DAC1 Lower Pattern Register Offset  0x0028*/\r
-__IO uint32_t  DAC1PATH; /*!<DAC1 Higher Pattern Register Offset  0x002C*/\r
-}DAC_GLOBAL_TypeDef;\r
-\r
-#define   DAC_BASE                      ((uint32_t)0x48018000U)\r
-#define   DAC_GLOBAL_BASE               (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   DAC           ((DAC_GLOBAL_TypeDef*)(DAC_BASE + DAC_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     DLR                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *DLR registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   OVRSTAT; /*!<GPDMA Overrun Status Offset  0x0000*/\r
-__O uint32_t   OVRCLR; /*!<GPDMA Overrun Clear Offset  0x0004*/\r
-__IO uint32_t  SRSEL0; /*!<GPDMA Service Request Selection 0 Offset  0x0008*/\r
-__IO uint32_t  SRSEL1; /*!<GPDMA Service Request Selection 1 Offset  0x000C*/\r
-__IO uint32_t  LNEN; /*!<GPDMA Line Enable Offset  0x0010*/\r
-}DLR_GLOBAL_TypeDef;\r
-\r
-#define   DLR_BASE                      ((uint32_t)0x50004900U)\r
-#define   DLR_GLOBAL_BASE               (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   DLR           ((DLR_GLOBAL_TypeDef*)(DLR_BASE + DLR_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     GPDMA1                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Channel Related registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  SAR; /*!<Source Address Register for Channel 0 Offset  0x0000*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  DAR; /*!<Destination Address Register for Channel 0 Offset  0x0008*/\r
-__I  uint32_t  RESERVED2[3];\r
-__IO uint32_t  CTLL; /*!<Control Register for Channel 0 Low Word Offset  0x0018*/\r
-__IO uint32_t  CTLH; /*!<Control Register for Channel 0 High Word Offset  0x001C*/\r
-__I  uint32_t  RESERVED3[8];\r
-__IO uint32_t  CFGL; /*!<Configuration Register for Channel 0 Low Word Offset  0x0040*/\r
-__IO uint32_t  CFGH; /*!<Configuration Register for Channel 0 High Word Offset  0x0044*/\r
-}GPDMA1_CH_TypeDef;\r
-\r
-  /*\r
-  *GPDMA1 Global registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  RAWTFR; /*!<Raw IntTfr Status Offset  0x02C0*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  RAWBLOCK; /*!<Raw IntBlock Status Offset  0x02C8*/\r
-__I  uint32_t  RESERVED2;\r
-__IO uint32_t  RAWSRCTRAN; /*!<Raw IntSrcTran Status Offset  0x02D0*/\r
-__I  uint32_t  RESERVED3;\r
-__IO uint32_t  RAWDSTTRAN; /*!<Raw IntBlock Status Offset  0x02D8*/\r
-__I  uint32_t  RESERVED4;\r
-__IO uint32_t  RAWERR; /*!<Raw IntErr Status Offset  0x02E0*/\r
-__I  uint32_t  RESERVED5;\r
-__I uint32_t   STATUSTFR; /*!<IntTfr Status Offset  0x02E8*/\r
-__I  uint32_t  RESERVED6;\r
-__I uint32_t   STATUSBLOCK; /*!<IntBlock Status Offset  0x02F0*/\r
-__I  uint32_t  RESERVED7;\r
-__I uint32_t   STATUSSRCTRAN; /*!<IntSrcTran Status Offset  0x02F8*/\r
-__I  uint32_t  RESERVED8;\r
-__I uint32_t   STATUSDSTTRAN; /*!<IntBlock Status Offset  0x0300*/\r
-__I  uint32_t  RESERVED9;\r
-__I uint32_t   STATUSERR; /*!<IntErr Status Offset  0x0308*/\r
-__I  uint32_t  RESERVED10;\r
-__IO uint32_t  MASKTFR; /*!<Mask for Raw IntTfr Status Offset  0x0310*/\r
-__I  uint32_t  RESERVED11;\r
-__IO uint32_t  MASKBLOCK; /*!<Mask for Raw IntBlock Status Offset  0x0318*/\r
-__I  uint32_t  RESERVED12;\r
-__IO uint32_t  MASKSRCTRAN; /*!<Mask for Raw IntSrcTran Status Offset  0x0320*/\r
-__I  uint32_t  RESERVED13;\r
-__IO uint32_t  MASKDSTTRAN; /*!<Mask for Raw IntBlock Status Offset  0x0328*/\r
-__I  uint32_t  RESERVED14;\r
-__IO uint32_t  MASKERR; /*!<Mask for Raw IntErr Status Offset  0x0330*/\r
-__I  uint32_t  RESERVED15;\r
-__O uint32_t   CLEARTFR; /*!<IntTfr Status Offset  0x0338*/\r
-__I  uint32_t  RESERVED16;\r
-__O uint32_t   CLEARBLOCK; /*!<IntBlock Status Offset  0x0340*/\r
-__I  uint32_t  RESERVED17;\r
-__O uint32_t   CLEARSRCTRAN; /*!<IntSrcTran Status Offset  0x0348*/\r
-__I  uint32_t  RESERVED18;\r
-__O uint32_t   CLEARDSTTRAN; /*!<IntBlock Status Offset  0x0350*/\r
-__I  uint32_t  RESERVED19;\r
-__O uint32_t   CLEARERR; /*!<IntErr Status Offset  0x0358*/\r
-__I  uint32_t  RESERVED20;\r
-__I uint32_t   STATUSINT; /*!<Combined Interrupt Status Register Offset  0x0360*/\r
-__I  uint32_t  RESERVED21;\r
-__IO uint32_t  REQSRCREG; /*!<Source Software Transaction Request Register Offset  0x0368*/\r
-__I  uint32_t  RESERVED22;\r
-__IO uint32_t  REQDSTREG; /*!<Destination Software Transaction Request Register Offset  0x0370*/\r
-__I  uint32_t  RESERVED23;\r
-__IO uint32_t  SGLREQSRCREG; /*!<Single Source Transaction Request Register Offset  0x0378*/\r
-__I  uint32_t  RESERVED24;\r
-__IO uint32_t  SGLREQDSTREG; /*!<Single Destination Transaction Request Register Offset  0x0380*/\r
-__I  uint32_t  RESERVED25;\r
-__IO uint32_t  LSTSRCREG; /*!<Last Source Transaction Request Register Offset  0x0388*/\r
-__I  uint32_t  RESERVED26;\r
-__IO uint32_t  LSTDSTREG; /*!<Last Destination Transaction Request Register Offset  0x0390*/\r
-__I  uint32_t  RESERVED27;\r
-__IO uint32_t  DMACFGREG; /*!<GPDMA Configuration Register Offset  0x0398*/\r
-__I  uint32_t  RESERVED28;\r
-__IO uint32_t  CHENREG; /*!<GPDMA Channel Enable Register Offset  0x03A0*/\r
-__I  uint32_t  RESERVED29;\r
-__I uint32_t   ID; /*!<GPDMA1 ID Register Offset  0x03A8*/\r
-__I  uint32_t  RESERVED30[19];\r
-__I uint32_t   TYPE; /*!<GPDMA Component Type Offset  0x03F8*/\r
-__I uint32_t   VERSION; /*!<DMA Component Version Offset  0x03FC*/\r
-}GPDMA1_GLOBAL_TypeDef;\r
-\r
-#define   GPDMA1_BASE                   ((uint32_t)0x50018000U)\r
-#define   GPDMA1_CH0_BASE               (0x0000U)\r
-#define   GPDMA1_CH1_BASE               (0x0058U)\r
-#define   GPDMA1_CH2_BASE               (0x00B0U)\r
-#define   GPDMA1_CH3_BASE               (0x0108U)\r
-#define   GPDMA1_GLOBAL_BASE            (0x02C0U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   GPDMA1_CH0            ((GPDMA1_CH_TypeDef*)(GPDMA1_BASE + GPDMA1_CH0_BASE))\r
-#define   GPDMA1_CH1            ((GPDMA1_CH_TypeDef*)(GPDMA1_BASE + GPDMA1_CH1_BASE))\r
-#define   GPDMA1_CH2            ((GPDMA1_CH_TypeDef*)(GPDMA1_BASE + GPDMA1_CH2_BASE))\r
-#define   GPDMA1_CH3            ((GPDMA1_CH_TypeDef*)(GPDMA1_BASE + GPDMA1_CH3_BASE))\r
-#define   GPDMA1                ((GPDMA1_GLOBAL_TypeDef*)(GPDMA1_BASE + GPDMA1_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     GPDMA0                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Channel Related registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  SAR; /*!<Source Address Register for Channel 0 Offset  0x0000*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  DAR; /*!<Destination Address Register for Channel 0 Offset  0x0008*/\r
-__I  uint32_t  RESERVED2;\r
-__IO uint32_t  LLP; /*!<Linked List Pointer Register for Channel 0 Offset  0x0010*/\r
-__I  uint32_t  RESERVED3;\r
-__IO uint32_t  CTLL; /*!<Control Register for Channel 0 Low Word Offset  0x0018*/\r
-__IO uint32_t  CTLH; /*!<Control Register for Channel 0 High Word Offset  0x001C*/\r
-__IO uint32_t  SSTAT; /*!<Source Status Register for Channel 0 Offset  0x0020*/\r
-__I  uint32_t  RESERVED4;\r
-__IO uint32_t  DSTAT; /*!<Destination Status Register for Channel 0 Offset  0x0028*/\r
-__I  uint32_t  RESERVED5;\r
-__IO uint32_t  SSTATAR; /*!<Source Status Address Register for Channel 0 Offset  0x0030*/\r
-__I  uint32_t  RESERVED6;\r
-__IO uint32_t  DSTATAR; /*!<Destination Status Address Register for Channel 0 Offset  0x0038*/\r
-__I  uint32_t  RESERVED7;\r
-__IO uint32_t  CFGL; /*!<Configuration Register for Channel 0 Low Word Offset  0x0040*/\r
-__IO uint32_t  CFGH; /*!<Configuration Register for Channel 0 High Word Offset  0x0044*/\r
-__IO uint32_t  SGR; /*!<Source Gather Register for Channel 0 Offset  0x0048*/\r
-__I  uint32_t  RESERVED8;\r
-__IO uint32_t  DSR; /*!<Destination Scatter Register for Channel 0 Offset  0x0050*/\r
-}GPDMA0_CH_TypeDef;\r
-\r
-  /*\r
-  *GPDMA0 Global registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  RAWTFR; /*!<Raw IntTfr Status Offset  0x02C0*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  RAWBLOCK; /*!<Raw IntBlock Status Offset  0x02C8*/\r
-__I  uint32_t  RESERVED2;\r
-__IO uint32_t  RAWSRCTRAN; /*!<Raw IntSrcTran Status Offset  0x02D0*/\r
-__I  uint32_t  RESERVED3;\r
-__IO uint32_t  RAWDSTTRAN; /*!<Raw IntBlock Status Offset  0x02D8*/\r
-__I  uint32_t  RESERVED4;\r
-__IO uint32_t  RAWERR; /*!<Raw IntErr Status Offset  0x02E0*/\r
-__I  uint32_t  RESERVED5;\r
-__I uint32_t   STATUSTFR; /*!<IntTfr Status Offset  0x02E8*/\r
-__I  uint32_t  RESERVED6;\r
-__I uint32_t   STATUSBLOCK; /*!<IntBlock Status Offset  0x02F0*/\r
-__I  uint32_t  RESERVED7;\r
-__I uint32_t   STATUSSRCTRAN; /*!<IntSrcTran Status Offset  0x02F8*/\r
-__I  uint32_t  RESERVED8;\r
-__I uint32_t   STATUSDSTTRAN; /*!<IntBlock Status Offset  0x0300*/\r
-__I  uint32_t  RESERVED9;\r
-__I uint32_t   STATUSERR; /*!<IntErr Status Offset  0x0308*/\r
-__I  uint32_t  RESERVED10;\r
-__IO uint32_t  MASKTFR; /*!<Mask for Raw IntTfr Status Offset  0x0310*/\r
-__I  uint32_t  RESERVED11;\r
-__IO uint32_t  MASKBLOCK; /*!<Mask for Raw IntBlock Status Offset  0x0318*/\r
-__I  uint32_t  RESERVED12;\r
-__IO uint32_t  MASKSRCTRAN; /*!<Mask for Raw IntSrcTran Status Offset  0x0320*/\r
-__I  uint32_t  RESERVED13;\r
-__IO uint32_t  MASKDSTTRAN; /*!<Mask for Raw IntBlock Status Offset  0x0328*/\r
-__I  uint32_t  RESERVED14;\r
-__IO uint32_t  MASKERR; /*!<Mask for Raw IntErr Status Offset  0x0330*/\r
-__I  uint32_t  RESERVED15;\r
-__O uint32_t   CLEARTFR; /*!<IntTfr Status Offset  0x0338*/\r
-__I  uint32_t  RESERVED16;\r
-__O uint32_t   CLEARBLOCK; /*!<IntBlock Status Offset  0x0340*/\r
-__I  uint32_t  RESERVED17;\r
-__O uint32_t   CLEARSRCTRAN; /*!<IntSrcTran Status Offset  0x0348*/\r
-__I  uint32_t  RESERVED18;\r
-__O uint32_t   CLEARDSTTRAN; /*!<IntBlock Status Offset  0x0350*/\r
-__I  uint32_t  RESERVED19;\r
-__O uint32_t   CLEARERR; /*!<IntErr Status Offset  0x0358*/\r
-__I  uint32_t  RESERVED20;\r
-__I uint32_t   STATUSINT; /*!<Combined Interrupt Status Register Offset  0x0360*/\r
-__I  uint32_t  RESERVED21;\r
-__IO uint32_t  REQSRCREG; /*!<Source Software Transaction Request Register Offset  0x0368*/\r
-__I  uint32_t  RESERVED22;\r
-__IO uint32_t  REQDSTREG; /*!<Destination Software Transaction Request Register Offset  0x0370*/\r
-__I  uint32_t  RESERVED23;\r
-__IO uint32_t  SGLREQSRCREG; /*!<Single Source Transaction Request Register Offset  0x0378*/\r
-__I  uint32_t  RESERVED24;\r
-__IO uint32_t  SGLREQDSTREG; /*!<Single Destination Transaction Request Register Offset  0x0380*/\r
-__I  uint32_t  RESERVED25;\r
-__IO uint32_t  LSTSRCREG; /*!<Last Source Transaction Request Register Offset  0x0388*/\r
-__I  uint32_t  RESERVED26;\r
-__IO uint32_t  LSTDSTREG; /*!<Last Destination Transaction Request Register Offset  0x0390*/\r
-__I  uint32_t  RESERVED27;\r
-__IO uint32_t  DMACFGREG; /*!<GPDMA Configuration Register Offset  0x0398*/\r
-__I  uint32_t  RESERVED28;\r
-__IO uint32_t  CHENREG; /*!<GPDMA Channel Enable Register Offset  0x03A0*/\r
-__I  uint32_t  RESERVED29;\r
-__I uint32_t   ID; /*!<GPDMA0 ID Register Offset  0x03A8*/\r
-__I  uint32_t  RESERVED30[19];\r
-__I uint32_t   TYPE; /*!<GPDMA Component Type Offset  0x03F8*/\r
-__I uint32_t   VERSION; /*!<DMA Component Version Offset  0x03FC*/\r
-}GPDMA0_GLOBAL_TypeDef;\r
-\r
-#define   GPDMA0_BASE                   ((uint32_t)0x50014000U)\r
-#define   GPDMA0_CH0_BASE               (0x0000U)\r
-#define   GPDMA0_CH1_BASE               (0x0058U)\r
-#define   GPDMA0_CH2_BASE               (0x00B0U)\r
-#define   GPDMA0_CH3_BASE               (0x0108U)\r
-#define   GPDMA0_CH4_BASE               (0x0160U)\r
-#define   GPDMA0_CH5_BASE               (0x01B8U)\r
-#define   GPDMA0_CH6_BASE               (0x0210U)\r
-#define   GPDMA0_CH7_BASE               (0x0268U)\r
-#define   GPDMA0_GLOBAL_BASE            (0x02C0U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   GPDMA0_CH0            ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH0_BASE))\r
-#define   GPDMA0_CH1            ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH1_BASE))\r
-#define   GPDMA0_CH2            ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH2_BASE))\r
-#define   GPDMA0_CH3            ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH3_BASE))\r
-#define   GPDMA0_CH4            ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH4_BASE))\r
-#define   GPDMA0_CH5            ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH5_BASE))\r
-#define   GPDMA0_CH6            ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH6_BASE))\r
-#define   GPDMA0_CH7            ((GPDMA0_CH_TypeDef*)(GPDMA0_BASE + GPDMA0_CH7_BASE))\r
-#define   GPDMA0                ((GPDMA0_GLOBAL_TypeDef*)(GPDMA0_BASE + GPDMA0_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     DSD                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *DSD Global Registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  CLC; /*!<Clock Control Register Offset  0x0000*/\r
-__I  uint32_t  RESERVED1;\r
-__I uint32_t   ID; /*!<Module Identification Register Offset  0x0008*/\r
-__I  uint32_t  RESERVED2[7];\r
-__IO uint32_t  OCS; /*!<OCDS Control and Status Register Offset  0x0028*/\r
-__I  uint32_t  RESERVED3[21];\r
-__IO uint32_t  GLOBCFG; /*!<Global Configuration Register Offset  0x0080*/\r
-__I  uint32_t  RESERVED4;\r
-__IO uint32_t  GLOBRC; /*!<Global Run Control Register Offset  0x0088*/\r
-__I  uint32_t  RESERVED5[5];\r
-__IO uint32_t  CGCFG; /*!<Carrier Generator Configuration Register Offset  0x00A0*/\r
-__I  uint32_t  RESERVED6[15];\r
-__IO uint32_t  EVFLAG; /*!<Event Flag Register Offset  0x00E0*/\r
-__O uint32_t   EVFLAGCLR; /*!<Event Flag Clear Register Offset  0x00E4*/\r
-}DSD_GLOBAL_TypeDef;\r
-\r
-  /*\r
-  *DSD CHANNEL Registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  MODCFG; /*!<Modulator Configuration Register 0 Offset  0x0100*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  DICFG; /*!<Demodulator Input Configuration Register 0 Offset  0x0108*/\r
-__I  uint32_t  RESERVED2[2];\r
-__IO uint32_t  FCFGC; /*!<Filter Configuration Register 0, Main Comb Filter Offset  0x0114*/\r
-__IO uint32_t  FCFGA; /*!<Filter Configuration Register 0, Auxiliary Filter Offset  0x0118*/\r
-__I  uint32_t  RESERVED3;\r
-__IO uint32_t  IWCTR; /*!<Integration Window Control Register 0 Offset  0x0120*/\r
-__I  uint32_t  RESERVED4;\r
-__IO uint32_t  BOUNDSEL; /*!<Boundary Select Register 0 Offset  0x0128*/\r
-__I  uint32_t  RESERVED5;\r
-__I uint32_t   RESM; /*!<Result Register 0 Main Filter Offset  0x0130*/\r
-__I  uint32_t  RESERVED6;\r
-__IO uint32_t  OFFM; /*!<Offset Register 0 Main Filter Offset  0x0138*/\r
-__I  uint32_t  RESERVED7;\r
-__I uint32_t   RESA; /*!<Result Register 0 Auxiliary Filter Offset  0x0140*/\r
-__I  uint32_t  RESERVED8[3];\r
-__I uint32_t   TSTMP; /*!<Time-Stamp Register 0 Offset  0x0150*/\r
-__I  uint32_t  RESERVED9[19];\r
-__IO uint32_t  CGSYNC; /*!<Carrier Generator Synchronization Register 0 Offset  0x01A0*/\r
-__I  uint32_t  RESERVED10;\r
-__IO uint32_t  RECTCFG; /*!<Rectification Configuration Register 0 Offset  0x01A8*/\r
-}DSD_CH_TypeDef;\r
-\r
-#define   DSD_BASE                      ((uint32_t)0x40008000U)\r
-#define   DSD_GLOBAL_BASE               (0x0000U)\r
-#define   DSD_CH0_BASE          (0x0100U)\r
-#define   DSD_CH1_BASE          (0x0200U)\r
-#define   DSD_CH2_BASE          (0x0300U)\r
-#define   DSD_CH3_BASE          (0x0400U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   DSD           ((DSD_GLOBAL_TypeDef*)(DSD_BASE + DSD_GLOBAL_BASE))\r
-#define   DSD_CH0               ((DSD_CH_TypeDef*)(DSD_BASE + DSD_CH0_BASE))\r
-#define   DSD_CH1               ((DSD_CH_TypeDef*)(DSD_BASE + DSD_CH1_BASE))\r
-#define   DSD_CH2               ((DSD_CH_TypeDef*)(DSD_BASE + DSD_CH2_BASE))\r
-#define   DSD_CH3               ((DSD_CH_TypeDef*)(DSD_BASE + DSD_CH3_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     EBU                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *EBU GLOBAL registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  CLC; /*!<EBU Clock Control Register Offset  0x0000*/\r
-__IO uint32_t  MODCON; /*!<EBU Configuration Register Offset  0x0004*/\r
-__I uint32_t   ID; /*!<EBU Module Identification Register Offset  0x0008*/\r
-__IO uint32_t  USERCON; /*!<EBU Test/Control Configuration Register Offset  0x000C*/\r
-}EBU_GLOBAL_TypeDef;\r
-\r
-  /*\r
-  *EBU chipselect registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  ADDRSEL; /*!<EBU Address Select Register 0 Offset  0x0018*/\r
-__I  uint32_t  RESERVED1[3];\r
-__IO uint32_t  BUSRCON; /*!<EBU Bus Configuration Register Offset  0x0028*/\r
-__IO uint32_t  BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset  0x002C*/\r
-__IO uint32_t  BUSWCON; /*!<EBU Bus Write Configuration Register Offset  0x0030*/\r
-__IO uint32_t  BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset  0x0034*/\r
-}EBU_CS0_TypeDef;\r
-\r
-typedef struct {\r
-__IO uint32_t  ADDRSEL; /*!<EBU Address Select Register 0 Offset  0x001C*/\r
-__I  uint32_t  RESERVED1[6];\r
-__IO uint32_t  BUSRCON; /*!<EBU Bus Configuration Register Offset  0x0038*/\r
-__IO uint32_t  BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset*/\r
-__IO uint32_t  BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/\r
-__IO uint32_t  BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/\r
-}EBU_CS1_TypeDef;\r
-\r
-typedef struct {\r
-__IO uint32_t  ADDRSEL; /*!<EBU Address Select Register 0 Offset  0x0020*/\r
-__I  uint32_t  RESERVED1[9];\r
-__IO uint32_t  BUSRCON; /*!<EBU Bus Configuration Register Offset  0x0048*/\r
-__IO uint32_t  BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset*/\r
-__IO uint32_t  BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/\r
-__IO uint32_t  BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/\r
-}EBU_CS2_TypeDef;\r
-\r
-typedef struct {\r
-__IO uint32_t  ADDRSEL; /*!<EBU Address Select Register 0 Offset  0x0024*/\r
-__I  uint32_t  RESERVED1[12];\r
-__IO uint32_t  BUSRCON; /*!<EBU Bus Configuration Register Offset  0x0058*/\r
-__IO uint32_t  BUSRAP; /*!<EBU Bus Read Access Parameter Register Offset*/\r
-__IO uint32_t  BUSWCON; /*!<EBU Bus Write Configuration Register Offset*/\r
-__IO uint32_t  BUSWAP; /*!<EBU Bus Write Access Parameter Register Offset*/\r
-}EBU_CS3_TypeDef;\r
-\r
-  /*\r
-  *EBU SDRAM registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  SDRMCON; /*!<EBU SDRAM Control Register Offset  0x0068*/\r
-__IO uint32_t  SDRMOD; /*!<EBU SDRAM Mode Register Offset  0x006C*/\r
-__IO uint32_t  SDRMREF; /*!<EBU SDRAM Refresh Control Register Offset  0x0070*/\r
-__I uint32_t   SDRSTAT; /*!<EBU SDRAM Status Register Offset  0x0074*/\r
-}EBU_SDRAM_TypeDef;\r
-\r
-#define   EBU_BASE                      ((uint32_t)0x58008000U)\r
-#define   EBU_GLOBAL_BASE      (0x0000U)\r
-#define   EBU_CS0_BASE          (0x0018U)\r
-#define   EBU_CS1_BASE          (0x001CU)\r
-#define   EBU_CS2_BASE          (0x0020U)\r
-#define   EBU_CS3_BASE          (0x0024U)\r
-#define   EBU_SDRAM_BASE        (0x0068U)\r
-\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   EBU           ((EBU_GLOBAL_TypeDef*)(EBU_BASE + EBU_GLOBAL_BASE))\r
-#define   EBU_CS0               ((EBU_CS0_TypeDef*)(EBU_BASE + EBU_CS0_BASE))\r
-#define   EBU_CS1               ((EBU_CS1_TypeDef*)(EBU_BASE + EBU_CS1_BASE))\r
-#define   EBU_CS2               ((EBU_CS2_TypeDef*)(EBU_BASE + EBU_CS2_BASE))\r
-#define   EBU_CS3               ((EBU_CS3_TypeDef*)(EBU_BASE + EBU_CS3_BASE))\r
-#define   EBU_SDRAM             ((EBU_SDRAM_TypeDef*)(EBU_BASE + EBU_SDRAM_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     ERUx                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *ERU Registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  EXISEL; /*!<Event Input Select Register 0 Offset  0x0000*/\r
-__I  uint32_t  RESERVED1[3];\r
-__IO uint32_t  EXICON[4]; /*!<Event Input Control 0 Register Offset  0x0010*/\r
-__IO uint32_t  EXOCON[4]; /*!<Event Output Trigger Control 0 Register Offset  0x0020*/\r
-}ERU_GLOBAL_TypeDef;\r
-\r
-#define   ERU0_BASE                     ((uint32_t)0x50004800U)\r
-#define   ERU1_BASE                     ((uint32_t)0x40044000U)\r
-#define   ERU_GLOBAL_BASE               (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   ERU0          ((ERU_GLOBAL_TypeDef*)(ERU0_BASE + ERU_GLOBAL_BASE))\r
-#define   ERU1          ((ERU_GLOBAL_TypeDef*)(ERU1_BASE + ERU_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     ETHx                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Ethernet Unit\r
-  */\r
-typedef struct {\r
-__IO uint32_t  MAC_CONFIGURATION; /*!<Register 0 [MAC Configuration Register] Offset  0x0000*/\r
-__IO uint32_t  MAC_FRAME_FILTER; /*!<Register 1 [MAC Frame Filter] Offset  0x0004*/\r
-__IO uint32_t  HASH_TABLE_HIGH; /*!<Register 2 [Hash Table High Register] Offset  0x0008*/\r
-__IO uint32_t  HASH_TABLE_LOW; /*!<Register 3 [Hash Table Low Register] Offset  0x000C*/\r
-__IO uint32_t  GMII_ADDRESS; /*!<Register 4 [MII Address Register) Offset  0x0010*/\r
-__IO uint32_t  GMII_DATA; /*!<Register 5 [MII Data Register] Offset  0x0014*/\r
-__IO uint32_t  FLOW_CONTROL; /*!<Register 6 [Flow Control Register] Offset  0x0018*/\r
-__IO uint32_t  VLAN_TAG; /*!<Register 7 [VLAN Tag Register] Offset  0x001C*/\r
-__I uint32_t   VERSION; /*!<Register 8 [Version Register] Offset  0x0020*/\r
-__I uint32_t   DEBUG; /*!<Register 9 [Debug Register] Offset  0x0024*/\r
-__IO uint32_t  REMOTE_WAKE_UP_FRAME_FILTER; /*!< Offset  0x0028*/\r
-__IO uint32_t  PMT_CONTROL_STATUS; /*!<Register 11 [PMT Control and Status Register] Offset  0x002C*/\r
-__I  uint32_t  RESERVED1[2];\r
-__I uint32_t   INTERRUPT_STATUS; /*!<Register 14 [Interrupt Register] Offset  0x0038*/\r
-__IO uint32_t  INTERRUPT_MASK; /*!<Register 15 [Interrupt Mask Register] Offset  0x003C*/\r
-__IO uint32_t  MAC_ADDRESS0_HIGH; /*!<Register 16 [MAC Address0 High Register] Offset  0x0040*/\r
-__IO uint32_t  MAC_ADDRESS0_LOW; /*!<Register 17 [MAC Address0 Low Register] Offset  0x0044*/\r
-__IO uint32_t  MAC_ADDRESS1_HIGH; /*!<Register 18 [MAC Address1 High Register] Offset  0x0048*/\r
-__IO uint32_t  MAC_ADDRESS1_LOW; /*!<Register 19 [MAC Address1 Low Register] Offset  0x004C*/\r
-__IO uint32_t  MAC_ADDRESS2_HIGH; /*!<Register 20 [MAC Address2 High Register] Offset  0x0050*/\r
-__IO uint32_t  MAC_ADDRESS2_LOW; /*!<Register 21 [MAC Address2 Low Register] Offset  0x0054*/\r
-__IO uint32_t  MAC_ADDRESS3_HIGH; /*!<Register 22 [MAC Address3 High Register] Offset  0x0058*/\r
-__IO uint32_t  MAC_ADDRESS3_LOW; /*!<Register 23 [MAC Address3 Low Register] Offset  0x005C*/\r
-__I  uint32_t  RESERVED2[40];\r
-__IO uint32_t  MMC_CONTROL; /*!<Register 64 [MMC Control Register] Offset  0x0100*/\r
-__I uint32_t   MMC_RECEIVE_INTERRUPT; /*!<Register 65 [MMC Receive Interrupt Register] Offset  0x0104*/\r
-__I uint32_t   MMC_TRANSMIT_INTERRUPT; /*!<Register 66 [MMC Transmit Interrupt Register] Offset  0x0108*/\r
-__IO uint32_t  MMC_RECEIVE_INTERRUPT_MASK; /*!< Offset  0x010C*/\r
-__IO uint32_t  MMC_TRANSMIT_INTERRUPT_MASK; /*!< Offset  0x0110*/\r
-__I uint32_t   TX_OCTET_COUNT_GOOD_BAD; /*!<Register 69 [Transmit Octet Count for Good and Bad Frames] Offset  0x0114*/\r
-__I uint32_t   TX_FRAME_COUNT_GOOD_BAD; /*!<Register 70 [Transmit Frame Count for Good and Bad Frames] Offset  0x0118*/\r
-__I uint32_t   TX_BROADCAST_FRAMES_GOOD; /*!<Register 71 [Transmit Frame Count for Good Broadcast Frames] Offset  0x011C*/\r
-__I uint32_t   TX_MULTICAST_FRAMES_GOOD; /*!<Register 72 [Transmit Frame Count for Good Multicast Frames] Offset  0x0120*/\r
-__I uint32_t   TX_64OCTETS_FRAMES_GOOD_BAD; /*!<Register 73 [Transmit Octet Count for Good and Bad 64 Byte Frames] Offset  0x0124*/\r
-__I uint32_t   TX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!<Register 74 [Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames] Offset  0x0128*/\r
-__I uint32_t   TX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!<Register 75 [Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames] Offset  0x012C*/\r
-__I uint32_t   TX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!<Register 76 [Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames] Offset  0x0130*/\r
-__I uint32_t   TX_512TO1023OCTETS_FRAMES_GOOD_BAD; /*!<Register 77 [Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames] Offset  0x0134*/\r
-__I uint32_t   TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD; /*!<Register 78 [Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames] Offset  0x0138*/\r
-__I uint32_t   TX_UNICAST_FRAMES_GOOD_BAD; /*!<Register 79 [Transmit Frame Count for Good and Bad Unicast Frames] Offset  0x013C*/\r
-__I uint32_t   TX_MULTICAST_FRAMES_GOOD_BAD; /*!<Register 80 [Transmit Frame Count for Good and Bad Multicast Frames] Offset  0x0140*/\r
-__I uint32_t   TX_BROADCAST_FRAMES_GOOD_BAD; /*!<Register 81 [Transmit Frame Count for Good and Bad Broadcast Frames] Offset  0x0144*/\r
-__I uint32_t   TX_UNDERFLOW_ERROR_FRAMES; /*!<Register 82 [Transmit Frame Count for Underflow Error Frames] Offset  0x0148*/\r
-__I uint32_t   TX_SINGLE_COLLISION_GOOD_FRAMES; /*!<Register 83 [Transmit Frame Count for Frames Transmitted after Single Collision] Offset  0x014C*/\r
-__I uint32_t   TX_MULTIPLE_COLLISION_GOOD_FRAMES; /*!<Register 84 [Transmit Frame Count for Frames Transmitted after Multiple Collision] Offset  0x0150*/\r
-__I uint32_t   TX_DEFERRED_FRAMES; /*!< Offset  0x0154*/\r
-__I uint32_t   TX_LATE_COLLISION_FRAMES; /*!<Register 86 [Transmit Frame Count for Late Collision Error Frames] Offset  0x0158*/\r
-__I uint32_t   TX_EXCESSIVE_COLLISION_FRAMES; /*!<Register 87 [Transmit Frame Count for Excessive Collision Error Frames] Offset  0x015C*/\r
-__I uint32_t   TX_CARRIER_ERROR_FRAMES; /*!<Register 88 [Transmit Frame Count for Carrier Sense Error Frames] Offset  0x0160*/\r
-__I uint32_t   TX_OCTET_COUNT_GOOD; /*!< Offset  0x0164*/\r
-__I uint32_t   TX_FRAME_COUNT_GOOD; /*!< Offset  0x0168*/\r
-__I uint32_t   TX_EXCESSIVE_DEFERRAL_ERROR; /*!<Register 91 [Transmit Frame Count for Excessive Deferral Error Frames] Offset  0x016C*/\r
-__I uint32_t   TX_PAUSE_FRAMES; /*!<Register 92 [Transmit Frame Count for Good PAUSE Frames] Offset  0x0170*/\r
-__I uint32_t   TX_VLAN_FRAMES_GOOD; /*!<Register 93 [Transmit Frame Count for Good VLAN Frames] Offset  0x0174*/\r
-__I uint32_t   TX_OSIZE_FRAMES_GOOD; /*!<Register 94 [Transmit Frame Count for Good Oversize Frames] Offset  0x0178*/\r
-__I  uint32_t  RESERVED3;\r
-__I uint32_t   RX_FRAMES_COUNT_GOOD_BAD; /*!<Register 96 [Receive Frame Count for Good and Bad Frames] Offset  0x0180*/\r
-__I uint32_t   RX_OCTET_COUNT_GOOD_BAD; /*!<Register 97 [Receive Octet Count for Good and Bad Frames] Offset  0x0184*/\r
-__I uint32_t   RX_OCTET_COUNT_GOOD; /*!< Offset  0x0188*/\r
-__I uint32_t   RX_BROADCAST_FRAMES_GOOD; /*!<Register 99 [Receive Frame Count for Good Broadcast Frames] Offset  0x018C*/\r
-__I uint32_t   RX_MULTICAST_FRAMES_GOOD; /*!<Register 100 [Receive Frame Count for Good Multicast Frames] Offset  0x0190*/\r
-__I uint32_t   RX_CRC_ERROR_FRAMES; /*!<Register 101 [Receive Frame Count for CRC Error Frames] Offset  0x0194*/\r
-__I uint32_t   RX_ALIGNMENT_ERROR_FRAMES; /*!<Register 102 [Receive Frame Count for Alignment Error Frames] Offset  0x0198*/\r
-__I uint32_t   RX_RUNT_ERROR_FRAMES; /*!<Register 103 [Receive Frame Count for Runt Error Frames] Offset  0x019C*/\r
-__I uint32_t   RX_JABBER_ERROR_FRAMES; /*!<Register 104 [Receive Frame Count for Jabber Error Frames] Offset  0x01A0*/\r
-__I uint32_t   RX_UNDERSIZE_FRAMES_GOOD; /*!<Register 105 [Receive Frame Count for Undersize Frames] Offset  0x01A4*/\r
-__I uint32_t   RX_OVERSIZE_FRAMES_GOOD; /*!< Offset  0x01A8*/\r
-__I uint32_t   RX_64OCTETS_FRAMES_GOOD_BAD; /*!<Register 107 [Receive Frame Count for Good and Bad 64 Byte Frames] Offset  0x01AC*/\r
-__I uint32_t   RX_65TO127OCTETS_FRAMES_GOOD_BAD; /*!<Register 108 [Receive Frame Count for Good and Bad 65 to 127 Bytes Frames] Offset  0x01B0*/\r
-__I uint32_t   RX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!<Register 109 [Receive Frame Count for Good and Bad 128 to 255 Bytes Frames] Offset  0x01B4*/\r
-__I uint32_t   RX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!<Register 110 [Receive Frame Count for Good and Bad 256 to 511 Bytes Frames] Offset  0x01B8*/\r
-__I uint32_t   RX_512TO1023OCTETS_FRAMES_GOOD_BAD; /*!<Register 111 [Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames] Offset  0x01BC*/\r
-__I uint32_t   RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD; /*!<Register 112 [Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames] Offset  0x01C0*/\r
-__I uint32_t   RX_UNICAST_FRAMES_GOOD; /*!<Register 113 [Receive Frame Count for Good Unicast Frames] Offset  0x01C4*/\r
-__I uint32_t   RX_LENGTH_ERROR_FRAMES; /*!<Register 114 [Receive Frame Count for Length Error Frames] Offset  0x01C8*/\r
-__I uint32_t   RX_OUT_OF_RANGE_TYPE_FRAMES; /*!<Register 115 [Receive Frame Count for Out of Range Frames] Offset  0x01CC*/\r
-__I uint32_t   RX_PAUSE_FRAMES; /*!<Register 116 [Receive Frame Count for PAUSE Frames] Offset  0x01D0*/\r
-__I uint32_t   RX_FIFO_OVERFLOW_FRAMES; /*!<Register 117 [Receive Frame Count for FIFO Overflow Frames] Offset  0x01D4*/\r
-__I uint32_t   RX_VLAN_FRAMES_GOOD_BAD; /*!<Register 118 [Receive Frame Count for Good and Bad VLAN Frames] Offset  0x01D8*/\r
-__I uint32_t   RX_WATCHDOG_ERROR_FRAMES; /*!<Register 119 [Receive Frame Count for Watchdog Error Frames] Offset  0x01DC*/\r
-__I uint32_t   RX_RECEIVE_ERROR_FRAMES; /*!<Register 120 [Receive Frame Count for Receive Error Frames] Offset  0x01E0*/\r
-__I uint32_t   RX_CONTROL_FRAMES_GOOD; /*!<Register 121 [Receive Frame Count for Good Control Frames Frames] Offset  0x01E4*/\r
-__I  uint32_t  RESERVED4[6];\r
-__IO uint32_t  MMC_IPC_RECEIVE_INTERRUPT_MASK; /*!<Register 128 [MMC Receive Checksum Offload Interrupt Mask Register] Offset  0x0200*/\r
-__I  uint32_t  RESERVED5;\r
-__I uint32_t   MMC_IPC_RECEIVE_INTERRUPT; /*!<Register 130 [MMC Receive Checksum Offload Interrupt Register] Offset  0x0208*/\r
-__I  uint32_t  RESERVED6;\r
-__I uint32_t   RXIPV4_GOOD_FRAMES; /*!< Offset  0x0210*/\r
-__I uint32_t   RXIPV4_HEADER_ERROR_FRAMES; /*!<Register 133 [Receive IPV4 Header Error Frame Counter Register] Offset  0x0214*/\r
-__I uint32_t   RXIPV4_NO_PAYLOAD_FRAMES; /*!<Register 134 [Receive IPV4 No Payload Frame Counter Register] Offset  0x0218*/\r
-__I uint32_t   RXIPV4_FRAGMENTED_FRAMES; /*!<Register 135 [Receive IPV4 Fragmented Frame Counter Register] Offset  0x021C*/\r
-__I uint32_t   RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES; /*!<Register 136 [Receive IPV4 UDP Checksum Disabled Frame Counter Register] Offset  0x0220*/\r
-__I uint32_t   RXIPV6_GOOD_FRAMES; /*!< Offset  0x0224*/\r
-__I uint32_t   RXIPV6_HEADER_ERROR_FRAMES; /*!<Register 138 [Receive IPV6 Header Error Frame Counter Register] Offset  0x0228*/\r
-__I uint32_t   RXIPV6_NO_PAYLOAD_FRAMES; /*!<Register 139 [Receive IPV6 No Payload Frame Counter Register] Offset  0x022C*/\r
-__I uint32_t   RXUDP_GOOD_FRAMES; /*!< Offset  0x0230*/\r
-__I uint32_t   RXUDP_ERROR_FRAMES; /*!< Offset  0x0234*/\r
-__I uint32_t   RXTCP_GOOD_FRAMES; /*!< Offset  0x0238*/\r
-__I uint32_t   RXTCP_ERROR_FRAMES; /*!< Offset  0x023C*/\r
-__I uint32_t   RXICMP_GOOD_FRAMES; /*!< Offset  0x0240*/\r
-__I uint32_t   RXICMP_ERROR_FRAMES; /*!< Offset  0x0244*/\r
-__I  uint32_t  RESERVED7[2];\r
-__I uint32_t   RXIPV4_GOOD_OCTETS; /*!< Offset  0x0250*/\r
-__I uint32_t   RXIPV4_HEADER_ERROR_OCTETS; /*!<Register 149 [Receive IPV4 Header Error Octet Counter Register] Offset  0x0254*/\r
-__I uint32_t   RXIPV4_NO_PAYLOAD_OCTETS; /*!<Register 150 [Receive IPV4 No Payload Octet Counter Register] Offset  0x0258*/\r
-__I uint32_t   RXIPV4_FRAGMENTED_OCTETS; /*!<Register 151 [Receive IPV4 Fragmented Octet Counter Register] Offset  0x025C*/\r
-__I uint32_t   RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /*!<Register 152 [Receive IPV4 Fragmented Octet Counter Register] Offset  0x0260*/\r
-__I uint32_t   RXIPV6_GOOD_OCTETS; /*!< Offset  0x0264*/\r
-__I uint32_t   RXIPV6_HEADER_ERROR_OCTETS; /*!<Register 154 [Receive IPV6 Header Error Octet Counter Register] Offset  0x0268*/\r
-__I uint32_t   RXIPV6_NO_PAYLOAD_OCTETS; /*!<Register 155 [Receive IPV6 No Payload Octet Counter Register] Offset  0x026C*/\r
-__I uint32_t   RXUDP_GOOD_OCTETS; /*!< Offset  0x0270*/\r
-__I uint32_t   RXUDP_ERROR_OCTETS; /*!< Offset  0x0274*/\r
-__I uint32_t   RXTCP_GOOD_OCTETS; /*!< Offset  0x0278*/\r
-__I uint32_t   RXTCP_ERROR_OCTETS; /*!< Offset  0x027C*/\r
-__I uint32_t   RXICMP_GOOD_OCTETS; /*!< Offset  0x0280*/\r
-__I uint32_t   RXICMP_ERROR_OCTETS; /*!< Offset  0x0284*/\r
-__I  uint32_t  RESERVED8[286];\r
-__IO uint32_t  TIMESTAMP_CONTROL; /*!<Register 448 [Timestamp Control Register] Offset  0x0700*/\r
-__IO uint32_t  SUB_SECOND_INCREMENT; /*!<Register 449 [Sub-Second Increment Register] Offset  0x0704*/\r
-__I uint32_t   SYSTEM_TIME_SECONDS; /*!<Register 450 [System Time - Seconds Register] Offset  0x0708*/\r
-__I uint32_t   SYSTEM_TIME_NANOSECONDS; /*!< Offset  0x070C*/\r
-__IO uint32_t  SYSTEM_TIME_SECONDS_UPDATE; /*!<Register 452 [System Time - Seconds Update Register] Offset  0x0710*/\r
-__IO uint32_t  SYSTEM_TIME_NANOSECONDS_UPDATE; /*!< Offset  0x0714*/\r
-__IO uint32_t  TIMESTAMP_ADDEND; /*!<Register 454 [Timestamp Addend Register] Offset  0x0718*/\r
-__IO uint32_t  TARGET_TIME_SECONDS; /*!<Register 455 [Target Time Seconds Register] Offset  0x071C*/\r
-__IO uint32_t  TARGET_TIME_NANOSECONDS; /*!< Offset  0x0720*/\r
-__IO uint32_t  SYSTEM_TIME_HIGHER_WORD_SECONDS; /*!<Register 457 [System Time - Higher Word Seconds Register] Offset  0x0724*/\r
-__I uint32_t   TIMESTAMP_STATUS; /*!<Register 458 [Timestamp Status Register] Offset  0x0728*/\r
-__IO uint32_t  PPS_CONTROL; /*!<Register 459 [PPS Control Register] Offset  0x072C*/\r
-__I  uint32_t  RESERVED9[564];\r
-__IO uint32_t  BUS_MODE; /*!<Register 0 [Bus Mode Register] Offset  0x1000*/\r
-__IO uint32_t  TRANSMIT_POLL_DEMAND; /*!<Register 1 [Transmit Poll Demand Register] Offset  0x1004*/\r
-__IO uint32_t  RECEIVE_POLL_DEMAND; /*!< Offset  0x1008*/\r
-__IO uint32_t  RECEIVE_DESCRIPTOR_LIST_ADDRESS; /*!< Offset  0x100C*/\r
-__IO uint32_t  TRANSMIT_DESCRIPTOR_LIST_ADDRESS; /*!< Offset  0x1010*/\r
-__IO uint32_t  STATUS; /*!< Offset  0x1014*/\r
-__IO uint32_t  OPERATION_MODE; /*!<Register 6 [Operation Mode Register] Offset  0x1018*/\r
-__IO uint32_t  INTERRUPT_ENABLE; /*!<Register 7 [Interrupt Enable Register] Offset  0x101C*/\r
-__I uint32_t   MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER; /*!< Offset  0x1020*/\r
-__IO uint32_t  RECEIVE_INTERRUPT_WATCHDOG_TIMER; /*!< Offset  0x1024*/\r
-__I  uint32_t  RESERVED10;\r
-__I uint32_t   AHB_STATUS; /*!<Register 11 [AHB Status Register] Offset  0x102C*/\r
-__I  uint32_t  RESERVED11[6];\r
-__I uint32_t   CURRENT_HOST_TRANSMIT_DESCRIPTOR; /*!< Offset  0x1048*/\r
-__I uint32_t   CURRENT_HOST_RECEIVE_DESCRIPTOR; /*!< Offset  0x104C*/\r
-__I uint32_t   CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS; /*!<Register 20 [Current Host Transmit Buffer Address Register] Offset  0x1050*/\r
-__I uint32_t   CURRENT_HOST_RECEIVE_BUFFER_ADDRESS; /*!<Register 21 [Current Host Receive Buffer Address Register] Offset  0x1054*/\r
-__IO uint32_t  HW_FEATURE; /*!<Register 22 [HW Feature Register] Offset  0x1058*/\r
-}ETH_GLOBAL_TypeDef;\r
-\r
-#define   ETH0_BASE                     ((uint32_t)0x5000C000U)\r
-#define   ETH_GLOBAL_BASE               (0x0000U)\r
-\r
-/***************************************************************************/\r
-/*                     ETH0_CON                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Ethernet I/O Control Register\r
-  */\r
-typedef struct {\r
-__IO uint32_t  CON; /*!<Ethernet 0 Port Control Register Offset  0x0000*/\r
-}ETH0_CON_GLOBAL_TypeDef;\r
-\r
-#define   ETH0_CON_BASE                         ((uint32_t)0x50004040U)\r
-#define   ETH0_CON_GLOBAL_BASE          (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   ETH0_CON              ((ETH0_CON_GLOBAL_TypeDef*)(ETH0_CON_BASE + ETH0_CON_GLOBAL_BASE))\r
-#define   ETH0          ((ETH_GLOBAL_TypeDef*)(ETH0_BASE + ETH_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     ETM                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Cortex M4 - Embedded Trace Macrocell\r
-  */\r
-typedef struct {                            /*!< ETM Structure                         */\r
-  __IO uint32_t  ETMCR;                     /*!< The ETMCR characteristics are:Purpose Controls general operation of the ETM, such as whether tracing is enabled.Configurations This register is only available if the processor is configured to use the ETM. */\r
-  __I  uint32_t  ETMCCR;                    /*!< The ETM Configuration Code Register characteristics are:Purpose Enables software to read the implementation-specific configuration of the ETM.Configurations This register is only available if the processor is configured to use the ETM. */\r
-  __IO uint32_t  ETMTRIGGER;                /*!< The Trigger Event Register defines the event that controls the trigger. It is: register 0x02, at offset 0x08 in a memory-mapped implementation a write-only register, although in architecture versions 3.1 and later it is read/write when bit [11] ofthe Configuration Code Extension Register is set, see Configuration Code Extension Register,ETMv3.1 and later on page 3-76. */\r
-  __I  uint32_t  RESERVED0;\r
-  __IO uint32_t  ETMSR;                     /*!< The ETM Status Register provides information about the current status of the trace and trigger logic. It is: register 0x04, at offset 0x10 in a memory-mapped implementation a read/write register */\r
-  __I  uint32_t  ETMSCR;                    /*!< The ETMSCR characteristics are:Purpose Shows the ETM features supported by the implementation of the ETM macrocell.Configurations This register is only available if the processor is configured to use the ETM. */\r
-  __I  uint32_t  RESERVED1[2];\r
-  __IO uint32_t  ETMTEEVR;                  /*!< The TraceEnable Event Register defines the TraceEnable enabling event. It is: register 0x08, at offset 0x20 in a memory-mapped implementation a write-only register, although in architecture versions 3.1 and later it is read/write when bit [11] of the Configuration Code Extension Register is set, see Configuration Code Extension Register, ETMv3.1 and later on page 3-76. */\r
-  __IO uint32_t  ETMTECR1;                  /*!< The ETMTECR1 characteristics are:Purpose Enables the start/stop logic used for trace enable.Configurations This register is only available if the processor is configured to use the ETM. */\r
-  __IO uint32_t  ETMFFLR;                   /*!< The FIFOFULL Level Register holds the level below which the FIFO is considered full, although its function varies for different ETM architectures. From ETMv3.0 the value in this register also controls the point at which data trace suppression occurs.The FIFOFULL Level Register is: register 0x0B, at offset 0x2C in a memory-mapped implementation a read/write register in ETM architecture versions 2.0 and later. */\r
-  __I  uint32_t  RESERVED2[69];\r
-  __IO uint32_t  ETMCNTRLDVR1;              /*!< A Counter Reload Value Register specifies the starting value of the associated counter. The counter is automatically loaded with this value when this register is programmed and when the ETM Programming bit is set. It is then reloaded with this value whenever the counter reload event, specified by the Counter Reload Event Register, is active. The Counter Reload Value Registers are: registers 0x50 to 0x53, at offsets 0x140, 0x144, 0x148, and 0x14C in a memory-mapped implementation write-only registers, altho */\r
-  __I  uint32_t  RESERVED3[39];\r
-  __I  uint32_t  ETMSYNCFR;                 /*!< The ETMSYNCFR characteristics are:Purpose Holds the trace synchronization frequency value.From ETMv3.5, this value must be set to a value greater than the size of the FIFO, or to zero. Values greater than zero but less than the FIFO size are still not permitted.A value of zero disables periodic synchronization based on the synchronization frequency counter. This does not affect other sources of synchronization, such as external requests from a CoreSight system. */\r
-  __I  uint32_t  ETMIDR;                    /*!< The ETMIDR characteristics are:Purpose Holds the ETM architecture variant, and defines the programmers model for the ETM.Configurations This register is only available if the processor is configured to use the ETM. */\r
-  __I  uint32_t  ETMCCER;                   /*!< The ETMCCER characteristics are:Purpose Holds ETM configuration information additional to that in the ETMCCR.See Configuration Code Register, ETMCCR on page 10-14.Configurations This register is only available if the processor is configured to use the ETM. */\r
-  __I  uint32_t  RESERVED4;\r
-  __IO uint32_t  ETMTESSEICR;               /*!< The Trace Start/Stop EmbeddedICE Control Register specifies the EmbeddedICE watchpoint comparator inputs that are used as trace start and stop resources. It is: register 0x7C, at offset 0x1F0 in a memory-mapped implementation a write-only register, that is read/write when bit [11] of the Configuration Code Extension Register is set, see Configuration Code Extension Register, ETMv3.1 and later on page 3-76. */\r
-  __I  uint32_t  RESERVED5;\r
-  __IO uint32_t  ETMTSEVR;                  /*!< The ETMTSEVR characteristics are:Purpose Defines an event that requests the insertion of a timestamp into the trace stream. */\r
-  __I  uint32_t  RESERVED6;\r
-  __IO uint32_t  ETMTRACEIDR;               /*!< The ETMTRACEIDR characteristics are:Purpose Defines the 7-bit Trace ID, for output to the trace bus.This register is used in systems where multiple trace sources are present and tracing simultaneously. For example, where an ETM outputs trace onto the AMBA version 3 Advanced Trace Bus (ATB), a unique ID is required for each trace source so that the trace can be uniquely identified as coming from a particular trace source. For more information about the AMBA version 3 ATB, see the CoreSight Architecture Spec */\r
-  __I  uint32_t  RESERVED7;\r
-  __I  uint32_t  ETMIDR2;                   /*!< The ETMIDR2 characteristics are:Purpose Provides an extension to the ETM ID register, ETMIDR. */\r
-  __I  uint32_t  RESERVED8[66];\r
-  __I  uint32_t  ETMPDSR;                   /*!< The ETMPDSR characteristics are:Purpose Indicates the power-down status of the ETM.Configurations This register is only available if the processor is configured to use an ETM. */\r
-  __I  uint32_t  RESERVED9[754];\r
-  __I  uint32_t  ITMISCIN;                  /*!< The ITMISCIN characteristics are:Purpose Integration test.Configurations This register is only available if the processor is configured to use the ETM. */\r
-  __I  uint32_t  RESERVED10;\r
-  __IO uint32_t  ITTRIGOUT;                 /*!< The ITMISCIN characteristics are:Purpose Integration test.Usage constraints You must set bit [0] of ETMITCTRL to use this register.Configurations This register is only available if the processor is configured to use the ETM. */\r
-  __I  uint32_t  RESERVED11;\r
-  __I  uint32_t  ETM_ITATBCTR2;             /*!< The ETM_ITATBCTR2 characteristics are:Purpose Integration test.Usage constraints You must set bit [0] of ETMITCTRL to use this register.Configurations This register is only available if the processor is configured to use the ETM. */\r
-  __I  uint32_t  RESERVED12;\r
-  __IO uint32_t  ETM_ITATBCTR0;             /*!< The Integration Test ATB Control (ETM_ITATBCTR0) characteristics are:Purpose Integration test.Usage constraints You must set bit [0] of ETMITCTRL to use this register.Configurations This register is only available if the processor is configured to use the ETM. */\r
-  __I  uint32_t  RESERVED13;\r
-  __IO uint32_t  ETMITCTRL;                 /*!< The Integration Mode Control Register (ITCTRL) is used to enable topology detection or to check integration testing. It is: register 0x3C0, at offset 0xF00 in a memory-mapped implementation */\r
-  __I  uint32_t  RESERVED14[39];\r
-  __IO uint32_t  ETMCLAIMSET;               /*!< The Claim Tag Set Register (CLAIMSET) is used to set bits in the claim tag and find the number of bits supported by the claim tag. It is: register 0x3E8, at offset 0xFA0 in a memory-mapped implementation */\r
-  __IO uint32_t  ETMCLAIMCLR;               /*!< The Claim Tag Clear Register (CLAIMCLR) is used to clear bits in the claim tag to 0, and to find the current value of the claim tag. It is: register 0x3E9, at offset 0xFA4 in a memory-mapped implementation */\r
-  __I  uint32_t  RESERVED15[2];\r
-  __IO uint32_t  ETMLAR;                    /*!< The Lock Access Register (LAR or LOCKACCESS) is used to lock and unlock access to all other ETM registers. It is: register 0x3EC, at offset 0xFB0 in a memory-mapped implementation */\r
-  __I  uint32_t  ETMLSR;                    /*!< The Lock Status Register (LSR or LOCKSTATUS) has two uses: If you read this register from any interface, you can check bit [0] to find out whether the lock registers are implemented for the interface you are using. If you read this register from an interface for which lock registers are implemented, you can check bit [1] to find out whether the registers are currently locked.The Lock Status Register is: register 0x3ED, at offset 0xFB4 in a memory-mapped implementation */\r
-  __I  uint32_t  ETMAUTHSTATUS;             /*!< The Authentication Status Register (AUTHSTATUS) reports the level of tracing currently permitted by the authentication signals provided to the ETM. It is: register 0x3EE, at offset 0xFB8 in a memory-mapped implementation */\r
-  __I  uint32_t  RESERVED16[4];\r
-  __I  uint32_t  ETMDEVTYPE;                /*!< The Device Type Register (DEVTYPE) returns the CoreSight device type of the component. It is: register 0x3F3, at offset 0xFCC in a memory-mapped implementation present in all CoreSight components. */\r
-  __I  uint32_t  ETMPIDR4;                  /*!< The Peripheral ID4 Register holds peripheral identification information. */\r
-  __I  uint32_t  ETMPIDR5;                  /*!< Peripheral Identification register5. See ARM Embedded TraceMacrocell Architecture Specification */\r
-  __I  uint32_t  ETMPIDR6;                  /*!< Peripheral Identification register6. See ARM Embedded TraceMacrocell Architecture Specification */\r
-  __I  uint32_t  ETMPIDR7;                  /*!< Peripheral Identification register7. See ARM Embedded TraceMacrocell Architecture Specification */\r
-  __I  uint32_t  ETMPIDR0;                  /*!< The Peripheral ID0 Register holds peripheral identification information. */\r
-  __I  uint32_t  ETMPIDR1;                  /*!< The Peripheral ID1 Register holds peripheral identification information. */\r
-  __I  uint32_t  ETMPIDR2;                  /*!< The Peripheral ID2 Register holds peripheral identification information. */\r
-  __I  uint32_t  ETMPIDR3;                  /*!< The Peripheral ID3 Register holds peripheral identification information. */\r
-  __I  uint32_t  ETMCIDR0;                  /*!< The Component ID0 Register holds byte 0 of the CoreSight preamble information. */\r
-  __I  uint32_t  ETMCIDR1;                  /*!< The Component ID1 Register holds byte 1 of the CoreSight preamble information. */\r
-  __I  uint32_t  ETMCIDR2;                  /*!< The Component ID2 Register holds byte 2 of the CoreSight preamble information. */\r
-  __I  uint32_t  ETMCIDR3;                  /*!< The Component ID3 Register holds byte 3 of the CoreSight preamble information. */\r
-} ETM_Type;\r
-\r
-#define   ETM_BASE                      ((uint32_t)0xE0041000U)\r
-#define   ETM_GLOBAL_BASE               (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   ETM           ((ETM_Type *)(ETM_BASE + ETM_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     FCE                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Global registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  CLC; /*!<Clock Control Register Offset  0x0000*/\r
-__I  uint32_t  RESERVED1;\r
-__I uint32_t   ID; /*!<Module Identification Register Offset  0x0008*/\r
-}FCE_GLOBAL_TypeDef;\r
-\r
-  /*\r
-  *Generic CRC Engine registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  IR; /*!<Input Register 0 Offset  0x0020*/\r
-__I uint32_t   RES; /*!<CRC Result Register 0 Offset  0x0024*/\r
-__IO uint32_t  CFG; /*!<CRC Configuration Register 0 Offset  0x0028*/\r
-__IO uint32_t  STS; /*!<CRC Status Register 0 Offset  0x002C*/\r
-__IO uint32_t  LENGTH; /*!<CRC Length Register 0 Offset  0x0030*/\r
-__IO uint32_t  CHECK; /*!<CRC Check Register 0 Offset  0x0034*/\r
-__IO uint32_t  CRC; /*!<CRC Register 0 Offset  0x0038*/\r
-__IO uint32_t  CTR; /*!<CRC Test Register 0 Offset  0x003C*/\r
-}FCE_KE_TypeDef;\r
-\r
-#define   FCE_BASE                      ((uint32_t)0x50020000U)\r
-#define   FCE_GLOBAL_BASE               (0x0000U)\r
-#define   FCE_KE0_BASE          (0x0020U)\r
-#define   FCE_KE1_BASE          (0x0040U)\r
-#define   FCE_KE2_BASE          (0x0060U)\r
-#define   FCE_KE3_BASE          (0x0080U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   FCE           ((FCE_GLOBAL_TypeDef*)(FCE_BASE + FCE_GLOBAL_BASE))\r
-#define   FCE_KE0               ((FCE_KE_TypeDef*)(FCE_BASE + FCE_KE0_BASE))\r
-#define   FCE_KE1               ((FCE_KE_TypeDef*)(FCE_BASE + FCE_KE1_BASE))\r
-#define   FCE_KE2               ((FCE_KE_TypeDef*)(FCE_BASE + FCE_KE2_BASE))\r
-#define   FCE_KE3               ((FCE_KE_TypeDef*)(FCE_BASE + FCE_KE3_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     FLASH0                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *FLASH0 GLOBAL registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   ID; /*!<Flash Module Identification Register Offset  0x1008*/\r
-__I  uint32_t  RESERVED1;\r
-__I uint32_t   FSR; /*!<Flash Status Register Offset  0x1010*/\r
-__IO uint32_t  FCON; /*!<Flash Configuration Register Offset  0x1014*/\r
-__IO uint32_t  MARP; /*!<Margin Control Register PFLASH Offset  0x1018*/\r
-__I  uint32_t  RESERVED2;\r
-__I uint32_t   PROCON0; /*!<Flash Protection Configuration Register User 0 Offset  0x1020*/\r
-__I uint32_t   PROCON1; /*!<Flash Protection Configuration Register User 1 Offset  0x1024*/\r
-__I uint32_t   PROCON2; /*!<Flash Protection Configuration Register User 2 Offset  0x1028*/\r
-}FLASH0_GLOBAL_TypeDef;\r
-\r
-#define   FLASH0_BASE                   ((uint32_t)0x58001000U)\r
-#define   FLASH0_GLOBAL_BASE            (0x1008U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   FLASH0                ((FLASH0_GLOBAL_TypeDef*)(FLASH0_BASE + FLASH0_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     FPB                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Cortex M4 - Flash Patch and Breakpoint\r
-  */\r
-typedef struct {                            /*!< FPB Structure                         */\r
-  __IO uint32_t  FP_CTRL;                   /*!< The FP_CTRL Register characteristics are:Purpose Provides FPB implementation information, and the global enable for the FPB unit.If implemented: The instruction address comparators start at FP_COMP0. This means the last instruction address comparator is FP_COMPn, where n = (NUM_CODE-1). The maximum number of instruction address comparators is 127. The literal address comparators start at FP_COMPm, where m=NUM_CODE. This means the last literal address comparator is at FP_COMPp, where p=(NUM_CODE+NUM_LIT-1). */\r
-  __IO uint32_t  FP_REMAP;                  /*!< The FP_REMAP register characteristics are:Purpose Indicates whether the implementation supports flash patch remap, and if it does, holds the SRAM address for remap.The remap base address must be aligned to the number of words required to support the implemented comparators, that is to (NUM_CODE+NUM_LIT) words, with a minimum alignment of 8 words. Because remap is into the SRAM memory region, 0x20000000-0x3FFFFFFF, bits [31:29] of the remap address are 0b001. */\r
-  __IO uint32_t  FP_COMP0;                  /*!< The FP_COMP0 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */\r
-  __IO uint32_t  FP_COMP1;                  /*!< The FP_COMP1 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */\r
-  __IO uint32_t  FP_COMP2;                  /*!< The FP_COMP2 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */\r
-  __IO uint32_t  FP_COMP3;                  /*!< The FP_COMP3 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */\r
-  __IO uint32_t  FP_COMP4;                  /*!< The FP_COMP4 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */\r
-  __IO uint32_t  FP_COMP5;                  /*!< The FP_COMP5 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */\r
-  __IO uint32_t  FP_COMP6;                  /*!< The FP_COMP6 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */\r
-  __IO uint32_t  FP_COMP7;                  /*!< The FP_COMP7 register characteristics are:Purpose Holds an address for comparison with addresses in the Code memory region, see The system address map on page B3-704. The effect of a match depends on whether the comparator is an instruction address comparator or a literal address comparator:Instruction address comparatorsEither: defines an instruction address to remap to an address based on the address specified in the FP_REMAP register defines a breakpoint address.Literal address comparatorsDefines a lite */\r
-  __I  uint32_t  RESERVED0[1002];\r
-  __I  uint32_t  FPBPID4;                   /*!< Peripheral identification register4   */\r
-  __I  uint32_t  FPBPID5;                   /*!< Peripheral identification register5   */\r
-  __I  uint32_t  FPBPID6;                   /*!< Peripheral identification register6   */\r
-  __I  uint32_t  FPBPID7;                   /*!< Peripheral identification register7   */\r
-  __I  uint32_t  FPBPID0;                   /*!< Peripheral identification register0   */\r
-  __I  uint32_t  FPBPID1;                   /*!< Peripheral identification register1   */\r
-  __I  uint32_t  FPBPID2;                   /*!< Peripheral identification register2   */\r
-  __I  uint32_t  FPBPID3;                   /*!< Peripheral identification register3   */\r
-  __I  uint32_t  FPBCID0;                   /*!< Component identification register0    */\r
-  __I  uint32_t  FPBCID1;                   /*!< Component identification register1    */\r
-  __I  uint32_t  FPBCID2;                   /*!< Component identification register2    */\r
-  __I  uint32_t  FPBCID3;                   /*!< Component identification register3    */\r
-} FPB_Type;\r
-\r
-#define   FPB_BASE                      ((uint32_t)0xE0002000U)\r
-#define   FPB_GLOBAL_BASE               (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   FPB           ((FPB_Type *)(FPB_BASE + FPB_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     LEDTS0                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *LEDTS0 KERNEL registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   ID; /*!<Module Identification Register Offset  0x0000*/\r
-__IO uint32_t  GLOBCTL; /*!<Global Control Register Offset  0x0004*/\r
-__IO uint32_t  FNCTL; /*!<Function Control Register Offset  0x0008*/\r
-__IO uint32_t  EVFR; /*!<Event Flag Register Offset  0x000C*/\r
-__IO uint32_t  TSVAL; /*!<Touch-sense TS-Counter Value Offset  0x0010*/\r
-__IO uint32_t  LINE0; /*!<Line Pattern Register 0 Offset  0x0014*/\r
-__IO uint32_t  LINE1; /*!<Line Pattern Register 1 Offset  0x0018*/\r
-__IO uint32_t  LDCMP0; /*!<LED Compare Register 0 Offset  0x001C*/\r
-__IO uint32_t  LDCMP1; /*!<LED Compare Register 1 Offset  0x0020*/\r
-__IO uint32_t  TSCMP0; /*!<Touch-sense Compare Register 0 Offset  0x0024*/\r
-__IO uint32_t  TSCMP1; /*!<Touch-sense Compare Register 1 Offset  0x0028*/\r
-}LEDTS0_GLOBAL_TypeDef;\r
-\r
-#define   LEDTS0_BASE                   ((uint32_t)0x48010000U)\r
-#define   LEDTS0_GLOBAL_BASE            (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   LEDTS0                ((LEDTS0_GLOBAL_TypeDef*)(LEDTS0_BASE + LEDTS0_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     PBAx                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Peripheral Bridge Status and Write Error Address registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  STS; /*!<Peripheral Bridge Status Register Offset  0x0000*/\r
-__I uint32_t   WADDR; /*!<PBA Write Error Address Register Offset  0x0004*/\r
-}PBA_GLOBAL_TypeDef;\r
-\r
-#define   PBA0_BASE                     ((uint32_t)0x40000000U)\r
-#define   PBA1_BASE                     ((uint32_t)0x48000000U)\r
-#define   PBA_GLOBAL_BASE               (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   PBA0          ((PBA_GLOBAL_TypeDef*)(PBA0_BASE + PBA_GLOBAL_BASE))\r
-#define   PBA1          ((PBA_GLOBAL_TypeDef*)(PBA1_BASE + PBA_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     PMU0                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *PMU0 ID register\r
-  */\r
-typedef struct {\r
-__I uint32_t   ID; /*!<PMU0 Identification Register Offset  0x0508*/\r
-}PMU0_GLOBAL_TypeDef;\r
-\r
-#define   PMU0_BASE                     ((uint32_t)0x58000000U)\r
-#define   PMU0_GLOBAL_BASE              (0x0508U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   PMU0          ((PMU0_GLOBAL_TypeDef*)(PMU0_BASE + PMU0_GLOBAL_BASE))\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                         PORT0                                        -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
-  * @brief Port 0 (PORT0)\r
-  */\r
-\r
-typedef struct {                            /*!< PORT0 Structure                       */\r
-  __IO uint32_t  OUT;                       /*!< Port 0 Output Register                */\r
-  __O  uint32_t  OMR;                       /*!< Port 0 Output Modification Register   */\r
-  __I  uint32_t  RESERVED0[2];\r
-  __IO uint32_t  IOCR0;                     /*!< Port 0 Input/Output Control Register 0 */\r
-  __IO uint32_t  IOCR4;                     /*!< Port 0 Input/Output Control Register 4 */\r
-  __IO uint32_t  IOCR8;                     /*!< Port 0 Input/Output Control Register 8 */\r
-  __IO uint32_t  IOCR12;                    /*!< Port 0 Input/Output Control Register 12 */\r
-  __I  uint32_t  RESERVED1;\r
-  __I  uint32_t  IN;                        /*!< Port 0 Input Register                 */\r
-  __I  uint32_t  RESERVED2[6];\r
-  __IO uint32_t  PDR0;                      /*!< Port 0 Pad Driver Mode 0 Register     */\r
-  __IO uint32_t  PDR1;                      /*!< Port 0 Pad Driver Mode 1 Register     */\r
-  __I  uint32_t  RESERVED3[6];\r
-  __I  uint32_t  PDISC;                     /*!< Port 0 Pin Function Decision Control Register */\r
-  __I  uint32_t  RESERVED4[3];\r
-  __IO uint32_t  PPS;                       /*!< Port 0 Pin Power Save Register        */\r
-  __IO uint32_t  HWSEL;                     /*!< Port 0 Pin Hardware Select Register   */\r
-} PORT0_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                         PORT1                                        -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
-  * @brief Port 1 (PORT1)\r
-  */\r
-\r
-typedef struct {                            /*!< PORT1 Structure                       */\r
-  __IO uint32_t  OUT;                       /*!< Port 1 Output Register                */\r
-  __O  uint32_t  OMR;                       /*!< Port 1 Output Modification Register   */\r
-  __I  uint32_t  RESERVED0[2];\r
-  __IO uint32_t  IOCR0;                     /*!< Port 1 Input/Output Control Register 0 */\r
-  __IO uint32_t  IOCR4;                     /*!< Port 1 Input/Output Control Register 4 */\r
-  __IO uint32_t  IOCR8;                     /*!< Port 1 Input/Output Control Register 8 */\r
-  __IO uint32_t  IOCR12;                    /*!< Port 1 Input/Output Control Register 12 */\r
-  __I  uint32_t  RESERVED1;\r
-  __I  uint32_t  IN;                        /*!< Port 1 Input Register                 */\r
-  __I  uint32_t  RESERVED2[6];\r
-  __IO uint32_t  PDR0;                      /*!< Port 1 Pad Driver Mode 0 Register     */\r
-  __IO uint32_t  PDR1;                      /*!< Port 1 Pad Driver Mode 1 Register     */\r
-  __I  uint32_t  RESERVED3[6];\r
-  __I  uint32_t  PDISC;                     /*!< Port 1 Pin Function Decision Control Register */\r
-  __I  uint32_t  RESERVED4[3];\r
-  __IO uint32_t  PPS;                       /*!< Port 1 Pin Power Save Register        */\r
-  __IO uint32_t  HWSEL;                     /*!< Port 1 Pin Hardware Select Register   */\r
-} PORT1_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                         PORT2                                        -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
-  * @brief Port 2 (PORT2)\r
-  */\r
-\r
-typedef struct {                            /*!< PORT2 Structure                       */\r
-  __IO uint32_t  OUT;                       /*!< Port 2 Output Register                */\r
-  __O  uint32_t  OMR;                       /*!< Port 2 Output Modification Register   */\r
-  __I  uint32_t  RESERVED0[2];\r
-  __IO uint32_t  IOCR0;                     /*!< Port 2 Input/Output Control Register 0 */\r
-  __IO uint32_t  IOCR4;                     /*!< Port 2 Input/Output Control Register 4 */\r
-  __IO uint32_t  IOCR8;                     /*!< Port 2 Input/Output Control Register 8 */\r
-  __IO uint32_t  IOCR12;                    /*!< Port 2 Input/Output Control Register 12 */\r
-  __I  uint32_t  RESERVED1;\r
-  __I  uint32_t  IN;                        /*!< Port 2 Input Register                 */\r
-  __I  uint32_t  RESERVED2[6];\r
-  __IO uint32_t  PDR0;                      /*!< Port 2 Pad Driver Mode 0 Register     */\r
-  __IO uint32_t  PDR1;                      /*!< Port 2 Pad Driver Mode 1 Register     */\r
-  __I  uint32_t  RESERVED3[6];\r
-  __I  uint32_t  PDISC;                     /*!< Port 2 Pin Function Decision Control Register */\r
-  __I  uint32_t  RESERVED4[3];\r
-  __IO uint32_t  PPS;                       /*!< Port 2 Pin Power Save Register        */\r
-  __IO uint32_t  HWSEL;                     /*!< Port 2 Pin Hardware Select Register   */\r
-} PORT2_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                         PORT3                                        -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
-  * @brief Port 3 (PORT3)\r
-  */\r
-\r
-typedef struct {                            /*!< PORT3 Structure                       */\r
-  __IO uint32_t  OUT;                       /*!< Port 3 Output Register                */\r
-  __O  uint32_t  OMR;                       /*!< Port 3 Output Modification Register   */\r
-  __I  uint32_t  RESERVED0[2];\r
-  __IO uint32_t  IOCR0;                     /*!< Port 3 Input/Output Control Register 0 */\r
-  __IO uint32_t  IOCR4;                     /*!< Port 3 Input/Output Control Register 4 */\r
-  __IO uint32_t  IOCR8;                     /*!< Port 3 Input/Output Control Register 8 */\r
-  __IO uint32_t  IOCR12;                    /*!< Port 3 Input/Output Control Register 12 */\r
-  __I  uint32_t  RESERVED1;\r
-  __I  uint32_t  IN;                        /*!< Port 3 Input Register                 */\r
-  __I  uint32_t  RESERVED2[6];\r
-  __IO uint32_t  PDR0;                      /*!< Port 3 Pad Driver Mode 0 Register     */\r
-  __IO uint32_t  PDR1;                      /*!< Port 3 Pad Driver Mode 1 Register     */\r
-  __I  uint32_t  RESERVED3[6];\r
-  __I  uint32_t  PDISC;                     /*!< Port 3 Pin Function Decision Control Register */\r
-  __I  uint32_t  RESERVED4[3];\r
-  __IO uint32_t  PPS;                       /*!< Port 3 Pin Power Save Register        */\r
-  __IO uint32_t  HWSEL;                     /*!< Port 3 Pin Hardware Select Register   */\r
-} PORT3_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                         PORT4                                        -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
-  * @brief Port 4 (PORT4)\r
-  */\r
-\r
-typedef struct {                            /*!< PORT4 Structure                       */\r
-  __IO uint32_t  OUT;                       /*!< Port 4 Output Register                */\r
-  __O  uint32_t  OMR;                       /*!< Port 4 Output Modification Register   */\r
-  __I  uint32_t  RESERVED0[2];\r
-  __IO uint32_t  IOCR0;                     /*!< Port 4 Input/Output Control Register 0 */\r
-  __IO uint32_t  IOCR4;                     /*!< Port 4 Input/Output Control Register 4 */\r
-  __I  uint32_t  RESERVED1[3];\r
-  __I  uint32_t  IN;                        /*!< Port 4 Input Register                 */\r
-  __I  uint32_t  RESERVED2[6];\r
-  __IO uint32_t  PDR0;                      /*!< Port 4 Pad Driver Mode 0 Register     */\r
-  __I  uint32_t  RESERVED3[7];\r
-  __I  uint32_t  PDISC;                     /*!< Port 4 Pin Function Decision Control Register */\r
-  __I  uint32_t  RESERVED4[3];\r
-  __IO uint32_t  PPS;                       /*!< Port 4 Pin Power Save Register        */\r
-  __IO uint32_t  HWSEL;                     /*!< Port 4 Pin Hardware Select Register   */\r
-} PORT4_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                         PORT5                                        -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
-  * @brief Port 5 (PORT5)\r
-  */\r
-\r
-typedef struct {                            /*!< PORT5 Structure                       */\r
-  __IO uint32_t  OUT;                       /*!< Port 5 Output Register                */\r
-  __O  uint32_t  OMR;                       /*!< Port 5 Output Modification Register   */\r
-  __I  uint32_t  RESERVED0[2];\r
-  __IO uint32_t  IOCR0;                     /*!< Port 5 Input/Output Control Register 0 */\r
-  __IO uint32_t  IOCR4;                     /*!< Port 5 Input/Output Control Register 4 */\r
-  __IO uint32_t  IOCR8;                     /*!< Port 5 Input/Output Control Register 8 */\r
-  __I  uint32_t  RESERVED1[2];\r
-  __I  uint32_t  IN;                        /*!< Port 5 Input Register                 */\r
-  __I  uint32_t  RESERVED2[6];\r
-  __IO uint32_t  PDR0;                      /*!< Port 5 Pad Driver Mode 0 Register     */\r
-  __IO uint32_t  PDR1;                      /*!< Port 5 Pad Driver Mode 1 Register     */\r
-  __I  uint32_t  RESERVED3[6];\r
-  __I  uint32_t  PDISC;                     /*!< Port 5 Pin Function Decision Control Register */\r
-  __I  uint32_t  RESERVED4[3];\r
-  __IO uint32_t  PPS;                       /*!< Port 5 Pin Power Save Register        */\r
-  __IO uint32_t  HWSEL;                     /*!< Port 5 Pin Hardware Select Register   */\r
-} PORT5_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                         PORT6                                        -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
-  * @brief Port 6 (PORT6)\r
-  */\r
-\r
-typedef struct {                            /*!< PORT6 Structure                       */\r
-  __IO uint32_t  OUT;                       /*!< Port 6 Output Register                */\r
-  __O  uint32_t  OMR;                       /*!< Port 6 Output Modification Register   */\r
-  __I  uint32_t  RESERVED0[2];\r
-  __IO uint32_t  IOCR0;                     /*!< Port 6 Input/Output Control Register 0 */\r
-  __IO uint32_t  IOCR4;                     /*!< Port 6 Input/Output Control Register 4 */\r
-  __I  uint32_t  RESERVED1[3];\r
-  __I  uint32_t  IN;                        /*!< Port 6 Input Register                 */\r
-  __I  uint32_t  RESERVED2[6];\r
-  __IO uint32_t  PDR0;                      /*!< Port 6 Pad Driver Mode 0 Register     */\r
-  __I  uint32_t  RESERVED3[7];\r
-  __I  uint32_t  PDISC;                     /*!< Port 6 Pin Function Decision Control Register */\r
-  __I  uint32_t  RESERVED4[3];\r
-  __IO uint32_t  PPS;                       /*!< Port 6 Pin Power Save Register        */\r
-  __IO uint32_t  HWSEL;                     /*!< Port 6 Pin Hardware Select Register   */\r
-} PORT6_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                        PORT14                                        -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
-  * @brief Port 14 (PORT14)\r
-  */\r
-\r
-typedef struct {                            /*!< PORT14 Structure                      */\r
-  __IO uint32_t  OUT;                       /*!< Port 14 Output Register               */\r
-  __O  uint32_t  OMR;                       /*!< Port 14 Output Modification Register  */\r
-  __I  uint32_t  RESERVED0[2];\r
-  __IO uint32_t  IOCR0;                     /*!< Port 14 Input/Output Control Register 0 */\r
-  __IO uint32_t  IOCR4;                     /*!< Port 14 Input/Output Control Register 4 */\r
-  __IO uint32_t  IOCR8;                     /*!< Port 14 Input/Output Control Register 8 */\r
-  __IO uint32_t  IOCR12;                    /*!< Port 14 Input/Output Control Register 12 */\r
-  __I  uint32_t  RESERVED1;\r
-  __I  uint32_t  IN;                        /*!< Port 14 Input Register                */\r
-  __I  uint32_t  RESERVED2[14];\r
-  __IO uint32_t  PDISC;                     /*!< Port 14 Pin Function Decision Control Register */\r
-  __I  uint32_t  RESERVED3[3];\r
-  __IO uint32_t  PPS;                       /*!< Port 14 Pin Power Save Register       */\r
-  __IO uint32_t  HWSEL;                     /*!< Port 14 Pin Hardware Select Register  */\r
-} PORT14_Type;\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                        PORT15                                        -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
-  * @brief Port 15 (PORT15)\r
-  */\r
-\r
-typedef struct {                            /*!< PORT15 Structure                      */\r
-  __IO uint32_t  OUT;                       /*!< Port 15 Output Register               */\r
-  __O  uint32_t  OMR;                       /*!< Port 15 Output Modification Register  */\r
-  __I  uint32_t  RESERVED0[2];\r
-  __IO uint32_t  IOCR0;                     /*!< Port 15 Input/Output Control Register 0 */\r
-  __IO uint32_t  IOCR4;                     /*!< Port 15 Input/Output Control Register 4 */\r
-  __IO uint32_t  IOCR8;                     /*!< Port 15 Input/Output Control Register 8 */\r
-  __IO uint32_t  IOCR12;                    /*!< Port 15 Input/Output Control Register 12 */\r
-  __I  uint32_t  RESERVED1;\r
-  __I  uint32_t  IN;                        /*!< Port 15 Input Register                */\r
-  __I  uint32_t  RESERVED2[14];\r
-  __IO uint32_t  PDISC;                     /*!< Port 15 Pin Function Decision Control Register */\r
-  __I  uint32_t  RESERVED3[3];\r
-  __IO uint32_t  PPS;                       /*!< Port 15 Pin Power Save Register       */\r
-  __IO uint32_t  HWSEL;                     /*!< Port 15 Pin Hardware Select Register  */\r
-} PORT15_Type;\r
-\r
-#define PORT0_BASE                0x48028000\r
-#define PORT1_BASE                0x48028100\r
-#define PORT2_BASE                0x48028200\r
-#define PORT3_BASE                0x48028300\r
-#define PORT4_BASE                0x48028400\r
-#define PORT5_BASE                0x48028500\r
-#define PORT6_BASE                0x48028600\r
-#define PORT14_BASE               0x48028E00\r
-#define PORT15_BASE               0x48028F00\r
-\r
-#define PORT0                     ((PORT0_Type              *) PORT0_BASE)\r
-#define PORT1                     ((PORT1_Type              *) PORT1_BASE)\r
-#define PORT2                     ((PORT2_Type              *) PORT2_BASE)\r
-#define PORT3                     ((PORT3_Type              *) PORT3_BASE)\r
-#define PORT4                     ((PORT4_Type              *) PORT4_BASE)\r
-#define PORT5                     ((PORT5_Type              *) PORT5_BASE)\r
-#define PORT6                     ((PORT6_Type              *) PORT6_BASE)\r
-#define PORT14                    ((PORT14_Type             *) PORT14_BASE)\r
-#define PORT15                    ((PORT15_Type             *) PORT15_BASE)\r
-\r
-\r
-/***************************************************************************/\r
-/*                     POSIFx                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Position Interface\r
-  */\r
-typedef struct {\r
-__IO uint32_t  PCONF; /*!<Architectural Overview configuration Offset  0x0000*/\r
-__IO uint32_t  PSUS; /*!<Architectural Overview Suspend Config Offset  0x0004*/\r
-__O uint32_t   PRUNS; /*!<Architectural Overview Run Bit Set Offset  0x0008*/\r
-__O uint32_t   PRUNC; /*!<Architectural Overview Run Bit Clear Offset  0x000C*/\r
-__I uint32_t   PRUN; /*!<Architectural Overview Run Bit Status Offset  0x0010*/\r
-__I  uint32_t  RESERVED1[3];\r
-__I uint32_t   MIDR; /*!<Module Identification register Offset  0x0020*/\r
-__I  uint32_t  RESERVED2[3];\r
-__I uint32_t   HALP; /*!<Hall Sensor Patterns Offset  0x0030*/\r
-__IO uint32_t  HALPS; /*!<Hall Sensor Shadow Patterns Offset  0x0034*/\r
-__I  uint32_t  RESERVED3[2];\r
-__I uint32_t   MCM; /*!<Multi Channel Pattern Offset  0x0040*/\r
-__IO uint32_t  MCSM; /*!<Multi Channel Shadow Pattern Offset  0x0044*/\r
-__O uint32_t   MCMS; /*!<Multi Channel Pattern Control set Offset  0x0048*/\r
-__O uint32_t   MCMC; /*!<Multi Channel Pattern Control clear Offset  0x004C*/\r
-__I uint32_t   MCMF; /*!<Multi Channel Pattern Control flag Offset  0x0050*/\r
-__I  uint32_t  RESERVED4[3];\r
-__IO uint32_t  QDC; /*!<Quadrature Decoder Control Offset  0x0060*/\r
-__I  uint32_t  RESERVED5[3];\r
-__I uint32_t   PFLG; /*!<Architectural Overview Interrupt Flags Offset  0x0070*/\r
-__IO uint32_t  PFLGE; /*!<Architectural Overview Interrupt Enable Offset  0x0074*/\r
-__O uint32_t   SPFLG; /*!<Architectural Overview Interrupt Set Offset  0x0078*/\r
-__O uint32_t   RPFLG; /*!<Architectural Overview Interrupt Clear Offset  0x007C*/\r
-}POSIF_GLOBAL_TypeDef;\r
-\r
-#define   POSIF0_BASE                   ((uint32_t)0x40028000U)\r
-#define   POSIF1_BASE                   ((uint32_t)0x4002C000U)\r
-#define   POSIF_GLOBAL_BASE             (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   POSIF0                ((POSIF_GLOBAL_TypeDef*)(POSIF0_BASE + POSIF_GLOBAL_BASE))\r
-#define   POSIF1                ((POSIF_GLOBAL_TypeDef*)(POSIF1_BASE + POSIF_GLOBAL_BASE))\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                          PPB                                         -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-/**\r
-  * @brief Cortex-M4 Private Peripheral Block (PPB)\r
-  */\r
-\r
-typedef struct {                            /*!< (@ 0xE000E000) PPB Structure          */\r
-  __I  uint32_t  RESERVED0[2];\r
-  __IO uint32_t  ACTLR;                     /*!< (@ 0xE000E008) Auxiliary Control Register */\r
-  __I  uint32_t  RESERVED1;\r
-  __IO uint32_t  SYST_CSR;                  /*!< (@ 0xE000E010) SysTick Control and Status Register */\r
-  __IO uint32_t  SYST_RVR;                  /*!< (@ 0xE000E014) SysTick Reload Value Register */\r
-  __IO uint32_t  SYST_CVR;                  /*!< (@ 0xE000E018) SysTick Current Value Register */\r
-  __IO uint32_t  SYST_CALIB;                /*!< (@ 0xE000E01C) SysTick Calibration Value Register r */\r
-  __I  uint32_t  RESERVED2[56];\r
-  __IO uint32_t  NVIC_ISER0;                /*!< (@ 0xE000E100) Interrupt Set-enable Register 0 */\r
-  __IO uint32_t  NVIC_ISER1;                /*!< (@ 0xE000E104) Interrupt Set-enable Register 1 */\r
-  __IO uint32_t  NVIC_ISER2;                /*!< (@ 0xE000E108) Interrupt Set-enable Register 2 */\r
-  __IO uint32_t  NVIC_ISER3;                /*!< (@ 0xE000E10C) Interrupt Set-enable Register 3 */\r
-  __I  uint32_t  RESERVED3[28];\r
-  __IO uint32_t  NVIC_ISCER0;               /*!< (@ 0xE000E180) Interrupt Clear-enable Register 0 */\r
-  __IO uint32_t  NVIC_ISCER1;               /*!< (@ 0xE000E184) Interrupt Clear-enable Register 1 */\r
-  __IO uint32_t  NVIC_ISCER2;               /*!< (@ 0xE000E188) Interrupt Clear-enable Register 2 */\r
-  __IO uint32_t  NVIC_ISCER3;               /*!< (@ 0xE000E18C) Interrupt Clear-enable Register 3 */\r
-  __I  uint32_t  RESERVED4[28];\r
-  __IO uint32_t  NVIC_ISSPR0;               /*!< (@ 0xE000E200) Interrupt Set-pending Register 0 */\r
-  __IO uint32_t  NVIC_ISSPR1;               /*!< (@ 0xE000E204) Interrupt Set-pending Register 1 */\r
-  __IO uint32_t  NVIC_ISSPR2;               /*!< (@ 0xE000E208) Interrupt Set-pending Register 2 */\r
-  __IO uint32_t  NVIC_ISSPR3;               /*!< (@ 0xE000E20C) Interrupt Set-pending Register 3 */\r
-  __I  uint32_t  RESERVED5[28];\r
-  __IO uint32_t  NVIC_ICPR0;                /*!< (@ 0xE000E280) Interrupt Clear-pending Register 0 */\r
-  __IO uint32_t  NVIC_ICPR1;                /*!< (@ 0xE000E284) Interrupt Clear-pending Register 1 */\r
-  __IO uint32_t  NVIC_ICPR2;                /*!< (@ 0xE000E288) Interrupt Clear-pending Register 2 */\r
-  __IO uint32_t  NVIC_ICPR3;                /*!< (@ 0xE000E28C) Interrupt Clear-pending Register 3 */\r
-  __I  uint32_t  RESERVED6[28];\r
-  __IO uint32_t  NVIC_IABR0;                /*!< (@ 0xE000E300) Interrupt Active Bit Register 0 */\r
-  __IO uint32_t  NVIC_IABR1;                /*!< (@ 0xE000E304) Interrupt Active Bit Register 1 */\r
-  __IO uint32_t  NVIC_IABR2;                /*!< (@ 0xE000E308) Interrupt Active Bit Register 2 */\r
-  __IO uint32_t  NVIC_IABR3;                /*!< (@ 0xE000E30C) Interrupt Active Bit Register 3 */\r
-  __I  uint32_t  RESERVED7[60];\r
-  __IO uint32_t  NVIC_IPR0;                 /*!< (@ 0xE000E400) Interrupt Priority Register 0 */\r
-  __IO uint32_t  NVIC_IPR1;                 /*!< (@ 0xE000E404) Interrupt Priority Register 1 */\r
-  __IO uint32_t  NVIC_IPR2;                 /*!< (@ 0xE000E408) Interrupt Priority Register 2 */\r
-  __IO uint32_t  NVIC_IPR3;                 /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */\r
-  __IO uint32_t  NVIC_IPR4;                 /*!< (@ 0xE000E410) Interrupt Priority Register 4 */\r
-  __IO uint32_t  NVIC_IPR5;                 /*!< (@ 0xE000E414) Interrupt Priority Register 5 */\r
-  __IO uint32_t  NVIC_IPR6;                 /*!< (@ 0xE000E418) Interrupt Priority Register 6 */\r
-  __IO uint32_t  NVIC_IPR7;                 /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */\r
-  __IO uint32_t  NVIC_IPR8;                 /*!< (@ 0xE000E420) Interrupt Priority Register 8 */\r
-  __IO uint32_t  NVIC_IPR9;                 /*!< (@ 0xE000E424) Interrupt Priority Register 9 */\r
-  __IO uint32_t  NVIC_IPR10;                /*!< (@ 0xE000E428) Interrupt Priority Register 10 */\r
-  __IO uint32_t  NVIC_IPR11;                /*!< (@ 0xE000E42C) Interrupt Priority Register 11 */\r
-  __IO uint32_t  NVIC_IPR12;                /*!< (@ 0xE000E430) Interrupt Priority Register 12 */\r
-  __IO uint32_t  NVIC_IPR13;                /*!< (@ 0xE000E434) Interrupt Priority Register 13 */\r
-  __IO uint32_t  NVIC_IPR14;                /*!< (@ 0xE000E438) Interrupt Priority Register 14 */\r
-  __IO uint32_t  NVIC_IPR15;                /*!< (@ 0xE000E43C) Interrupt Priority Register 15 */\r
-  __IO uint32_t  NVIC_IPR16;                /*!< (@ 0xE000E440) Interrupt Priority Register 16 */\r
-  __IO uint32_t  NVIC_IPR17;                /*!< (@ 0xE000E444) Interrupt Priority Register 17 */\r
-  __IO uint32_t  NVIC_IPR18;                /*!< (@ 0xE000E448) Interrupt Priority Register 18 */\r
-  __IO uint32_t  NVIC_IPR19;                /*!< (@ 0xE000E44C) Interrupt Priority Register 19 */\r
-  __IO uint32_t  NVIC_IPR20;                /*!< (@ 0xE000E450) Interrupt Priority Register 20 */\r
-  __IO uint32_t  NVIC_IPR21;                /*!< (@ 0xE000E454) Interrupt Priority Register 21 */\r
-  __IO uint32_t  NVIC_IPR22;                /*!< (@ 0xE000E458) Interrupt Priority Register 22 */\r
-  __IO uint32_t  NVIC_IPR23;                /*!< (@ 0xE000E45C) Interrupt Priority Register 23 */\r
-  __IO uint32_t  NVIC_IPR24;                /*!< (@ 0xE000E460) Interrupt Priority Register 24 */\r
-  __IO uint32_t  NVIC_IPR25;                /*!< (@ 0xE000E464) Interrupt Priority Register 25 */\r
-  __IO uint32_t  NVIC_IPR26;                /*!< (@ 0xE000E468) Interrupt Priority Register 26 */\r
-  __IO uint32_t  NVIC_IPR27;                /*!< (@ 0xE000E46C) Interrupt Priority Register 27 */\r
-  __I  uint32_t  RESERVED8[548];\r
-  __I  uint32_t  CPUID;                     /*!< (@ 0xE000ED00) CPUID Base Register    */\r
-  __IO uint32_t  ICSR;                      /*!< (@ 0xE000ED04) Interrupt Control and State Register */\r
-  __IO uint32_t  VTOR;                      /*!< (@ 0xE000ED08) Vector Table Offset Register */\r
-  __IO uint32_t  AIRCR;                     /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */\r
-  __IO uint32_t  SCR;                       /*!< (@ 0xE000ED10) System Control Register */\r
-  __IO uint32_t  CCR;                       /*!< (@ 0xE000ED14) Configuration and Control Register */\r
-  __IO uint32_t  SHPR1;                     /*!< (@ 0xE000ED18) System Handler Priority Register 1 */\r
-  __IO uint32_t  SHPR2;                     /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */\r
-  __IO uint32_t  SHPR3;                     /*!< (@ 0xE000ED20) System Handler Priority Register 3 */\r
-  __IO uint32_t  SHCSR;                     /*!< (@ 0xE000ED24) System Handler Control and State Register */\r
-  __IO uint32_t  CFSR;                      /*!< (@ 0xE000ED28) Configurable Fault Status Register */\r
-  __IO uint32_t  HFSR;                      /*!< (@ 0xE000ED2C) HardFault Status Register */\r
-  __I  uint32_t  RESERVED9;\r
-  __IO uint32_t  MMFAR;                     /*!< (@ 0xE000ED34) MemManage Fault Address Register */\r
-  __IO uint32_t  BFAR;                      /*!< (@ 0xE000ED38) BusFault Address Register */\r
-  __IO uint32_t  AFSR;                      /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register */\r
-  __I  uint32_t  RESERVED10[18];\r
-  __IO uint32_t  CPACR;                     /*!< (@ 0xE000ED88) Coprocessor Access Control Register */\r
-  __I  uint32_t  RESERVED11;\r
-  __I  uint32_t  MPU_TYPE;                  /*!< (@ 0xE000ED90) MPU Type Register      */\r
-  __IO uint32_t  MPU_CTRL;                  /*!< (@ 0xE000ED94) MPU Control Register   */\r
-  __IO uint32_t  MPU_RNR;                   /*!< (@ 0xE000ED98) MPU Region Number Register */\r
-  __IO uint32_t  MPU_RBAR;                  /*!< (@ 0xE000ED9C) MPU Region Base Address Register */\r
-  __IO uint32_t  MPU_RASR;                  /*!< (@ 0xE000EDA0) MPU Region Attribute and Size Register */\r
-  __IO uint32_t  MPU_RBAR_A1;               /*!< (@ 0xE000EDA4) MPU Region Base Address Register A1 */\r
-  __IO uint32_t  MPU_RASR_A1;               /*!< (@ 0xE000EDA8) MPU Region Attribute and Size Register A1 */\r
-  __IO uint32_t  MPU_RBAR_A2;               /*!< (@ 0xE000EDAC) MPU Region Base Address Register A2 */\r
-  __IO uint32_t  MPU_RASR_A2;               /*!< (@ 0xE000EDB0) MPU Region Attribute and Size Register A2 */\r
-  __IO uint32_t  MPU_RBAR_A3;               /*!< (@ 0xE000EDB4) MPU Region Base Address Register A3 */\r
-  __IO uint32_t  MPU_RASR_A3;               /*!< (@ 0xE000EDB8) MPU Region Attribute and Size Register A3 */\r
-  __I  uint32_t  RESERVED12[81];\r
-  __O  uint32_t  STIR;                      /*!< (@ 0xE000EF00) Software Trigger Interrupt Register */\r
-  __I  uint32_t  RESERVED13[12];\r
-  __IO uint32_t  FPCCR;                     /*!< (@ 0xE000EF34) Floating-point Context Control Register */\r
-  __IO uint32_t  FPCAR;                     /*!< (@ 0xE000EF38) Floating-point Context Address Register */\r
-  __IO uint32_t  FPDSCR;                    /*!< (@ 0xE000EF3C) Floating-point Default Status Control Register */\r
-} PPB_Type;\r
-\r
-#define PPB_BASE                  0xE000E000\r
-#define PPB                       ((PPB_Type                *) PPB_BASE)\r
-\r
-\r
-/***************************************************************************/\r
-/*                     PREF                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Prefetch\r
-  */\r
-typedef struct {\r
-__IO uint32_t  PCON; /*!<Prefetch Configuration Register Offset  0x0000*/\r
-}PREF_GLOBAL_TypeDef;\r
-\r
-#define   PREF_BASE                     ((uint32_t)0x58004000U)\r
-#define   PREF_GLOBAL_BASE              (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   PREF          ((PREF_GLOBAL_TypeDef*)(PREF_BASE + PREF_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     RTC                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *RTC Kernel registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   ID; /*!<RTC ID Register Offset  0x0000*/\r
-__IO uint32_t  CTR; /*!<RTC Control Register Offset  0x0004*/\r
-__I uint32_t   RAWSTAT; /*!<RTC Raw Service Request Register Offset  0x0008*/\r
-__I uint32_t   STSSR; /*!<RTC Service Request Status Register Offset  0x000C*/\r
-__IO uint32_t  MSKSR; /*!<RTC Service Request Mask Register Offset  0x0010*/\r
-__O uint32_t   CLRSR; /*!<RTC Clear Service Request Register Offset  0x0014*/\r
-__IO uint32_t  ATIM0; /*!<RTC Alarm Time Register 0 Offset  0x0018*/\r
-__IO uint32_t  ATIM1; /*!<RTC Alarm Time Register 1 Offset  0x001C*/\r
-__IO uint32_t  TIM0; /*!<RTC Time Register 0 Offset  0x0020*/\r
-__IO uint32_t  TIM1; /*!<RTC Time Register 1 Offset  0x0024*/\r
-}RTC_GLOBAL_TypeDef;\r
-\r
-#define   RTC_BASE                      ((uint32_t)0x50004A00U)\r
-#define   RTC_GLOBAL_BASE               (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   RTC           ((RTC_GLOBAL_TypeDef*)(RTC_BASE + RTC_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     SCU                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *SCU CCU PLL registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   PLLSTAT; /*!<PLL Status Register Offset  0x0710*/\r
-__IO uint32_t  PLLCON0; /*!<PLL Configuration 0 Register Offset  0x0714*/\r
-__IO uint32_t  PLLCON1; /*!<PLL Configuration 1 Register Offset  0x0718*/\r
-__IO uint32_t  PLLCON2; /*!<PLL Configuration 2 Register Offset  0x071C*/\r
-__I uint32_t   USBPLLSTAT; /*!<USB PLL Status Register Offset  0x0720*/\r
-__IO uint32_t  USBPLLCON; /*!<USB PLL Configuration Register Offset  0x0724*/\r
-__I  uint32_t  RESERVED1[4];\r
-__I uint32_t   CLKMXSTAT; /*!<Clock Multiplexing Status Register Offset  0x0738*/\r
-}SCU_PLL_TypeDef;\r
-\r
-  /*\r
-  *SCU CCU OSC registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   OSCHPSTAT; /*!<OSC_HP Status Register Offset  0x0700*/\r
-__IO uint32_t  OSCHPCTRL; /*!<OSC_HP Control Register Offset  0x0704*/\r
-}SCU_OSC_TypeDef;\r
-\r
-  /*\r
-  *SCU CCU Clock Control registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   CLKSTAT; /*!<Clock Status Register Offset  0x0600*/\r
-__O uint32_t   CLKSET; /*!<CLK Set Register Offset  0x0604*/\r
-__O uint32_t   CLKCLR; /*!<CLK Clear Register Offset  0x0608*/\r
-__IO uint32_t  SYSCLKCR; /*!<System Clock Control Register Offset  0x060C*/\r
-__IO uint32_t  CPUCLKCR; /*!<CPU Clock Control Register Offset  0x0610*/\r
-__IO uint32_t  PBCLKCR; /*!<Peripheral Bus Clock Control Register Offset  0x0614*/\r
-__IO uint32_t  USBCLKCR; /*!<USB Clock Control Register Offset  0x0618*/\r
-__IO uint32_t  EBUCLKCR; /*!<EBU Clock Control Register Offset  0x061C*/\r
-__IO uint32_t  CCUCLKCR; /*!<CCU Clock Control Register Offset  0x0620*/\r
-__IO uint32_t  WDTCLKCR; /*!<WDT Clock Control Register Offset  0x0624*/\r
-__IO uint32_t  EXTCLKCR; /*!<External Clock Control Offset  0x0628*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  SLEEPCR; /*!<Sleep Control Register Offset  0x0630*/\r
-__IO uint32_t  DSLEEPCR; /*!<Deep Sleep Control Register Offset  0x0634*/\r
-}SCU_CLK_TypeDef;\r
-\r
-#define   SCU_BASE                      ((uint32_t)0x50004000U)\r
-#define   SCU_PLL_BASE          (0x0710U)\r
-#define   SCU_OSC_BASE          (0x0700U)\r
-#define   SCU_CLK_BASE          (0x0600U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   SCU_PLL               ((SCU_PLL_TypeDef*)(SCU_BASE + SCU_PLL_BASE))\r
-#define   SCU_OSC               ((SCU_OSC_TypeDef*)(SCU_BASE + SCU_OSC_BASE))\r
-#define   SCU_CLK               ((SCU_CLK_TypeDef*)(SCU_BASE + SCU_CLK_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     SCU                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *SCU GCU CONTROL registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   ID; /*!<SCU Module ID Register Offset  0x0000*/\r
-__I uint32_t   IDCHIP; /*!<Chip ID Register Offset  0x0004*/\r
-__I uint32_t   IDMANUF; /*!<Manufactory ID Register Offset  0x0008*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  STCON; /*!<Startup Configuration Register Offset  0x0010*/\r
-__I  uint32_t  RESERVED2[6];\r
-__IO uint32_t GPR[2];  /*!< General Purpose Register 0  Offset  0x002C*/\r
-__I  uint32_t  RESERVED3[6];\r
-__IO uint32_t  CCUCON; /*!<CCU Control Register Offset  0x004C*/\r
-__I  uint32_t  RESERVED4[15];\r
-__IO uint32_t  DTSCON; /*!<Die Temperature Sensor Control Register Offset  0x008C*/\r
-__I uint32_t   DTSSTAT; /*!<Die Temperature Sensor Status Register Offset  0x0090*/\r
-__I  uint32_t  RESERVED5[2];\r
-__IO uint32_t  SDMMCDEL; /*!<SD-MMC Delay Control Register Offset  0x009C*/\r
-__IO uint32_t  GORCEN[2]; /*!<Out of Range Comparator Enable Register 0 Offset  0x00A0*/\r
-__I  uint32_t  RESERVED6[7];\r
-__I uint32_t   MIRRSTS; /*!<Mirror Update Status Register Offset  0x00C4*/\r
-__IO uint32_t  RMACR; /*!<Retention Memory Access Control Register Offset  0x00C8*/\r
-__IO uint32_t  RMDATA; /*!<Retention Memory Access Data Register Offset  0x00CC*/\r
-}SCU_GENERAL_TypeDef;\r
-\r
-  /*\r
-  *SCU GCU PARITY registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  PEEN; /*!<Parity Error Enable Register Offset  0x013C*/\r
-__IO uint32_t  MCHKCON; /*!<Memory Checking Control Register Offset  0x0140*/\r
-__IO uint32_t  PETE; /*!<Parity Error Trap Enable Register Offset  0x0144*/\r
-__IO uint32_t  PERSTEN; /*!<Parity Error Reset Enable Register Offset  0x0148*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  PEFLAG; /*!<Parity Error Flag Register Offset  0x0150*/\r
-__IO uint32_t  PMTPR; /*!<Parity Memory Test Pattern Register Offset  0x0154*/\r
-__IO uint32_t  PMTSR; /*!<Parity Memory Test Select Register Offset  0x0158*/\r
-}SCU_PARITY_TypeDef;\r
-\r
-  /*\r
-  *SCU GCU INTERRUPT registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   SRSTAT; /*!<SCU Service Request Status Offset  0x0074*/\r
-__I uint32_t   SRRAW; /*!<SCU Raw Service Request Status Offset  0x0078*/\r
-__IO uint32_t  SRMSK; /*!<SCU Service Request Mask Offset  0x007C*/\r
-__O uint32_t   SRCLR; /*!<SCU Service Request Clear Offset  0x0080*/\r
-__O uint32_t   SRSET; /*!<SCU Service Request Set Offset  0x0084*/\r
-__IO uint32_t  NMIREQEN; /*!<SCU Service Request Mask Offset  0x0088*/\r
-}SCU_INTERRUPT_TypeDef;\r
-\r
-  /*\r
-  *SCU TRAP registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   TRAPSTAT; /*!<Trap Status Register Offset  0x0160*/\r
-__I uint32_t   TRAPRAW; /*!<Trap Raw Status Register Offset  0x0164*/\r
-__IO uint32_t  TRAPDIS; /*!<Trap Disable Register Offset  0x0168*/\r
-__O uint32_t   TRAPCLR; /*!<Trap Clear Register Offset  0x016C*/\r
-__O uint32_t   TRAPSET; /*!<Trap Set Register Offset  0x0170*/\r
-}SCU_TRAP_TypeDef;\r
-\r
-#define   SCU_BASE                      ((uint32_t)0x50004000U)\r
-#define   SCU_GENERAL_BASE              (0x0000U)\r
-#define   SCU_PARITY_BASE               (0x013CU)\r
-#define   SCU_INTERRUPT_BASE            (0x0074U)\r
-#define   SCU_TRAP_BASE                 (0x0160U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   SCU_GENERAL           ((SCU_GENERAL_TypeDef*)(SCU_BASE + SCU_GENERAL_BASE))\r
-#define   SCU_PARITY            ((SCU_PARITY_TypeDef*)(SCU_BASE + SCU_PARITY_BASE))\r
-#define   SCU_INTERRUPT                 ((SCU_INTERRUPT_TypeDef*)(SCU_BASE + SCU_INTERRUPT_BASE))\r
-#define   SCU_TRAP              ((SCU_TRAP_TypeDef*)(SCU_BASE + SCU_TRAP_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     SCU                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *SCU HIBERNATE registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   HDSTAT; /*!<Hibernate Domain Control & Status Register Offset  0x0300*/\r
-__O uint32_t   HDCLR; /*!<Hibernate Domain Status Clear Register Offset  0x0304*/\r
-__O uint32_t   HDSET; /*!<Hibernate Domain Status Set Register Offset  0x0308*/\r
-__IO uint32_t  HDCR; /*!<Hibernate Domain Configuration Register Offset  0x030C*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  OSCSICTRL; /*!<OSC_SI Control Register Offset  0x0314*/\r
-__I uint32_t   OSCULSTAT; /*!<OSC_ULP Status Register Offset  0x0318*/\r
-__IO uint32_t  OSCULCTRL; /*!<OSC_ULP Control Register Offset  0x031C*/\r
-}SCU_HIBERNATE_TypeDef;\r
-\r
-#define   SCU_BASE                      ((uint32_t)0x50004000U)\r
-#define   SCU_HIBERNATE_BASE            (0x0300U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   SCU_HIBERNATE                 ((SCU_HIBERNATE_TypeDef*)(SCU_BASE + SCU_HIBERNATE_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     SCU                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *SCU PWRCTRL registers\r
-  */\r
-typedef struct {\r
-__I  uint32_t  PWRSTAT; /*!<PCU Status Register Offset  0x0200*/\r
-__O  uint32_t  PWRSET; /*!<PCU Set Control Register Offset  0x0204*/\r
-__O  uint32_t  PWRCLR; /*!<PCU Clear Control Register Offset  0x0208*/\r
-__I  uint32_t  RESERVED1;\r
-__I  uint32_t  EVRSTAT; /*!<EVR Status Register Offset  0x0210*/\r
-__I  uint32_t  EVRVADCSTAT; /*!<EVR VADC Status Register Offset  0x0214*/\r
-__I  uint32_t RESERVED2[5];\r
-__IO uint32_t PWRMON; /*!< Power Monitor Control  Offset  0x022C*/\r
-}SCU_POWER_TypeDef;\r
-\r
-#define   SCU_BASE                      ((uint32_t)0x50004000U)\r
-#define   SCU_POWER_BASE                (0x0200U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   SCU_POWER             ((SCU_POWER_TypeDef*)(SCU_BASE + SCU_POWER_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     SCU                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *SCU RESET CONTROL registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   RSTSTAT; /*!<RCU Reset Status Offset  0x0400*/\r
-__O uint32_t   RSTSET; /*!<RCU Reset Set Register Offset  0x0404*/\r
-__O uint32_t   RSTCLR; /*!<RCU Reset Clear Register Offset  0x0408*/\r
-__I uint32_t   PRSTAT0; /*!<RCU Peripheral 0 Reset Status Offset  0x040C*/\r
-__O uint32_t   PRSET0; /*!<RCU Peripheral 0 Reset Set Offset  0x0410*/\r
-__O uint32_t   PRCLR0; /*!<RCU Peripheral 0 Reset Clear Offset  0x0414*/\r
-__I uint32_t   PRSTAT1; /*!<RCU Peripheral 1 Reset Status Offset  0x0418*/\r
-__O uint32_t   PRSET1; /*!<RCU Peripheral 1 Reset Set Offset  0x041C*/\r
-__O uint32_t   PRCLR1; /*!<RCU Peripheral 1 Reset Clear Offset  0x0420*/\r
-__I uint32_t   PRSTAT2; /*!<RCU Peripheral 2 Reset Status Offset  0x0424*/\r
-__O uint32_t   PRSET2; /*!<RCU Peripheral 2 Reset Set Offset  0x0428*/\r
-__O uint32_t   PRCLR2; /*!<RCU Peripheral 2 Reset Clear Offset  0x042C*/\r
-__I uint32_t   PRSTAT3; /*!<RCU Peripheral 3 Reset Status Offset  0x0430*/\r
-__O uint32_t   PRSET3; /*!<RCU Peripheral 3 Reset Set Offset  0x0434*/\r
-__O uint32_t   PRCLR3; /*!<RCU Peripheral 3 Reset Clear Offset  0x0438*/\r
-}SCU_RESET_TypeDef;\r
-\r
-#define   SCU_BASE                      ((uint32_t)0x50004000U)\r
-#define   SCU_RESET_BASE                (0x0400U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   SCU_RESET             ((SCU_RESET_TypeDef*)(SCU_BASE + SCU_RESET_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     SDMMC                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *SDMMC registers\r
-  */\r
-typedef struct {\r
-__IO uint16_t  BLOCK_SIZE; /*!<Block Size Register Offset  0x0004*/\r
-__IO uint16_t  BLOCK_COUNT; /*!<Block Count Register Offset  0x0006*/\r
-__IO uint32_t  ARGUMENT1; /*!<Argument1 Register Offset  0x0008*/\r
-__IO uint16_t  TRANSFER_MODE; /*!<Transfer Mode Register Offset  0x000C*/\r
-__IO uint16_t  COMMAND; /*!<Command Register Offset  0x000E*/\r
-__I uint32_t   RESPONSE0; /*!<Response 0 Register Offset  0x0010*/\r
-__I uint32_t   RESPONSE2; /*!<Response 2 Register Offset  0x0014*/\r
-__I uint32_t   RESPONSE4; /*!<Response 4 Register Offset  0x0018*/\r
-__I uint32_t   RESPONSE6; /*!<Response 6 Register Offset  0x001C*/\r
-__IO uint32_t  DATA_BUFFER; /*!<Data Buffer Register Offset  0x0020*/\r
-__I uint32_t   PRESENT_STATE; /*!<Present State Register Offset  0x0024*/\r
-__IO uint8_t   HOST_CTRL; /*!<Host Control Register Offset  0x0028*/\r
-__IO uint8_t   POWER_CTRL; /*!<Power Control Register Offset  0x0029*/\r
-__IO uint8_t   BLOCK_GAP_CTRL; /*!<Block Gap Control Register Offset  0x002A*/\r
-__IO uint8_t   WAKEUP_CTRL; /*!<Wake-up Control Register Offset  0x002B*/\r
-__IO uint16_t  CLOCK_CTRL; /*!<Clock Control Register Offset  0x002C*/\r
-__IO uint8_t   TIMEOUT_CTRL; /*!<Timeout Control Register Offset  0x002E*/\r
-__IO uint8_t   SW_RESET; /*!<Software Reset Register Offset  0x002F*/\r
-__IO uint16_t  INT_STATUS_NORM; /*!<Normal Interrupt Status Register Offset  0x0030*/\r
-__IO uint16_t  INT_STATUS_ERR; /*!<Error Interrupt Status Register Offset  0x0032*/\r
-__IO uint16_t  EN_INT_STATUS_NORM; /*!<Normal Interrupt Status Enable Register Offset  0x0034*/\r
-__IO uint16_t  EN_INT_STATUS_ERR; /*!<Error Interrupt Status Enable Register Offset  0x0036*/\r
-__IO uint16_t  EN_INT_SIGNAL_NORM; /*!<Normal Interrupt Signal Enable Register Offset  0x0038*/\r
-__IO uint16_t  EN_INT_SIGNAL_ERR; /*!<Error Interrupt Signal Enable Register Offset  0x003A*/\r
-__I uint16_t   ACMD_ERR_STATUS; /*!<Auto CMD Error Status Register Offset  0x003C*/\r
-__I  uint16_t  RESERVED0;\r
-__I  uint32_t  RESERVED1[4];\r
-__O uint16_t   FORCE_EVENT_ACMD_ERR_STATUS; /*!<Force Event Register for Auto CMD Error Status Offset  0x0050*/\r
-__O uint16_t   FORCE_EVENT_ERR_STATUS; /*!<Force Event Register for Error Interrupt Status Offset  0x0052*/\r
-__I  uint32_t  RESERVED2;\r
-__I  uint32_t  RESERVED3[7];\r
-__O uint32_t   DEBUG_SEL; /*!<Debug Selection Register Offset  0x0074*/\r
-__I  uint32_t  RESERVED4[30];\r
-__IO uint32_t  SPI; /*!<SPI Interrupt Support Register Offset  0x00F0*/\r
-__I  uint32_t  RESERVED5[2];\r
-__I uint16_t   SLOT_INT_STATUS; /*!<Slot Interrupt Status Register Offset  0x00FC*/\r
-}SDMMC_GLOBAL_TypeDef;\r
-\r
-#define   SDMMC_BASE                    ((uint32_t)0x4801C000U)\r
-#define   SDMMC_GLOBAL_BASE             (0x0004U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   SDMMC                 ((SDMMC_GLOBAL_TypeDef*)(SDMMC_BASE + SDMMC_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     TPIU                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Cortex M4 - Trace Port Interface Unit\r
-  */\r
-typedef struct {                            /*!< TPIU Structure                        */\r
-  __I  uint32_t  TPIU_SSPSR;                /*!< The TPIU_SSPSR characteristics are:Purpose Indicates the supported parallel trace port sizes.If TPIU_TYPE.PTINVALID is RAO, this register is UNK. For more information see TPIU Type register, TPIU_TYPE on page C1-902. */\r
-  __IO uint32_t  TPIU_CSPSR;                /*!< The TPIU_CSPSR characteristics are:Purpose Defines the width of the current parallel trace port.Usage constraints Has the same format as the TPIU_SSPSR, but: only one bit is set to 1, all others must be zero the effect of writing a value with more than one bit set to 1 is UNPREDICTABLE the effect of a write to an unsupported bit is UNPREDICTABLE.If TPIU_TYPE.PTINVALID is RAO, this register is UNK/SBZP. For more information see TPIU Type register, TPIU_TYPE on page C1-902.Attributes See Table C1-40 on page  */\r
-  __I  uint32_t  RESERVED0[2];\r
-  __IO uint32_t  TPIU_ACPR;                 /*!< The TPIU_ACPR characteristics are:Purpose Scales the baud rate of the asynchronous output. */\r
-  __I  uint32_t  RESERVED1[55];\r
-  __IO uint32_t  TPIU_SPPR;                 /*!< The TPIU_SPPR characteristics are:Purpose Selects the protocol used for trace output.Usage constraints If a debugger changes the register value while the TPIU is transmitting data, the effect on the output stream is UNPREDICTABLE and the required recovery process is IMPLEMENTATION DEFINED. Bits [11:9] of the TPIU_TYPE register define the trace output protocols supported by the implementation, see TPIU Type register, TPIU_TYPE on page C1-902. The effect of selecting an unsupported mode is UNPREDICTABLE. */\r
-  __I  uint32_t  RESERVED2[131];\r
-  __I  uint32_t  TPIU_FFSR;                 /*!< The TPIU_FFSR characteristics are:Purpose Indicates the status of the TPIU formatter. */\r
-  __IO uint32_t  TPIU_FFCR;                 /*!< The TPIU_FFCR characteristics are:Purpose Controls the TPIU formatter.When one of the two SWO modes is selected, bit [1] of TPIU_FFCR enables the formatter to be bypassed. If the formatter is bypassed, only the ITM and DWT trace source passes through.The TPIU accepts and discards data from the ETM. This function is can be used to connect a device containing an ETM to a trace capture device that is only able to capture SWO data.Enabling or disabling the formatter causes momentary data corruption.NoteIf TPIU */\r
-  __I  uint32_t  TPIU_FSCR;                 /*!< The global synchronization trigger is generated by the Program Counter (PC) Sampler block. This means that there is no synchronization counter in the TPIU */\r
-  __I  uint32_t  RESERVED3[759];\r
-  __I  uint32_t  TRIGGER;                   /*!< The TRIGGER characteristics are:Purpose Integration test of the TRIGGER input. */\r
-  __I  uint32_t  FIFO_Data0;                /*!< The Integration ETM Data characteristics are:Purpose Trace data integration testing.Usage constraints You must set bit [1] of TPIU_ITCTRL to use this register. See Integration Mode Control, TPIU_ITCTRL on page 11-11. */\r
-  __I  uint32_t  ITATBCTR2;                 /*!< The ITATBCTR2 characteristics are:Purpose Integration test.Usage constraints You must set bit [0] of TPIU_ITCTRL to use this register. See Integration Mode Control, TPIU_ITCTRL on page 11-11. */\r
-  __I  uint32_t  RESERVED4;\r
-  __I  uint32_t  ITATBCTR0;                 /*!< The ITATBCTR0 characteristics are:Purpose Integration test. */\r
-  __I  uint32_t  FIFO_Data1;                /*!< The Integration ITM Data characteristics are:Purpose Trace data integration testing.Usage constraints You must set bit [1] of TPIU_ITCTRL to use this register. See Integration Mode Control, TPIU_ITCTRL on page 11-11. */\r
-  __IO uint32_t  ITCTRL;                    /*!< The TPIU_ITCTRL characteristics are:Purpose Specifies normal or integration mode for the TPIU. */\r
-  __I  uint32_t  RESERVED5[39];\r
-  __IO uint32_t  CLAIMSET;                  /*!< This register forms one half of the Claim Tag value. This location enables individual bits to be set, write, and returns the number of bits that can be set, read.Read Each bit is considered separately:0 = this claim tag bit is not implemented1 = this claim tag bit is implemented.Write Each bit is considered separately:0 = no effect1 = set this bit in the claim tag. */\r
-  __IO uint32_t  CLAIMCLR;                  /*!< This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read.The width (n) of this register can be determined from reading the Claim Tag Set Register.Read Current Claim Tag ValueWrite Each bit is considered separately:0 = no effect1 = clear this bit in the claim tag. */\r
-  __I  uint32_t  RESERVED6[8];\r
-  __I  uint32_t  DEVID;                     /*!< The TPIU_DEVID characteristics are:Purpose Indicates the functions provided by the TPIU for use in topology detection. */\r
-  __I  uint32_t  DEVTYPE;                   /*!< The Device Type Identifier Register is read-only. It provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information.The TPIU_DEVTYPE characteristics are:Purpose Indicates the type of functionality the component supports.Attributes The Device Type reads as 0x11 and indicates this device is a trace sink and specifically a TPIU */\r
-  __I  uint32_t  TPIUPID4;                  /*!< Peripheral identification register4   */\r
-  __I  uint32_t  TPIUPID5;                  /*!< Peripheral identification register5   */\r
-  __I  uint32_t  TPIUPID6;                  /*!< Peripheral identification register6   */\r
-  __I  uint32_t  TPIUPID7;                  /*!< Peripheral identification register7   */\r
-  __I  uint32_t  TPIUPID0;                  /*!< Peripheral identification register0   */\r
-  __I  uint32_t  TPIUPID1;                  /*!< Peripheral identification register1   */\r
-  __I  uint32_t  TPIUPID2;                  /*!< Peripheral identification register2   */\r
-  __I  uint32_t  TPIUPID3;                  /*!< Peripheral identification register3   */\r
-  __I  uint32_t  TPIUCID0;                  /*!< Component identification register0    */\r
-  __I  uint32_t  TPIUCID1;                  /*!< Component identification register1    */\r
-  __I  uint32_t  TPIUCID2;                  /*!< Component identification register2    */\r
-  __I  uint32_t  TPIUCID3;                  /*!< Component identification register3    */\r
-} TPIU_Type;\r
-\r
-#define   TPIU_BASE                     ((uint32_t)0xE0040000U)\r
-#define   TPIU_GLOBAL_BASE              (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   TPIU          ((TPIU_Type *)(TPIU_BASE + TPIU_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     USB0                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *CONTROL registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  GOTGCTL; /*!<Control and Status Register Offset  0x0000*/\r
-__IO uint32_t  GOTGINT; /*!<OTG Interrupt Register Offset  0x0004*/\r
-__IO uint32_t  GAHBCFG; /*!<AHB Configuration Register Offset  0x0008*/\r
-__IO uint32_t  GUSBCFG; /*!<USB Configuration Register Offset  0x000C*/\r
-__IO uint32_t  GRSTCTL; /*!<Reset Register Offset  0x0010*/\r
-union\r
- {\r
-__IO uint32_t  GINTSTS_HOSTMODE; /*!<Interrupt Register [Host Mode] Offset  0x0014*/\r
-__IO uint32_t  GINTSTS_DEVICEMODE; /*!<Interrupt Register [Device Mode] Offset  0x0014*/\r
- };\r
-union\r
- {\r
-__IO uint32_t  GINTMSK_HOSTMODE; /*!<Interrupt Mask Register [Host Mode] Offset  0x0018*/\r
-__IO uint32_t  GINTMSK_DEVICEMODE; /*!<Interrupt Mask Register [Device Mode] Offset  0x0018*/\r
- };\r
-union\r
- {\r
-__I uint32_t   GRXSTSR_HOSTMODE; /*!<Receive Status Debug Read Register [Host Mode] Offset  0x001C*/\r
-__I uint32_t   GRXSTSR_DEVICEMODE; /*!<Receive Status Debug Read Register [Device Mode] Offset  0x001C*/\r
- };\r
-union\r
- {\r
-__I uint32_t   GRXSTSP_HOSTMODE; /*!<Receive Status Read and Pop Register [Host Mode] Offset  0x0020*/\r
-__I uint32_t   GRXSTSP_DEVICEMODE; /*!<Receive Status Read and Pop Register [Device Mode] Offset  0x0020*/\r
- };\r
-__IO uint32_t  GRXFSIZ; /*!<Receive FIFO Size Register Offset  0x0024*/\r
-union\r
- {\r
-__IO uint32_t  GNPTXFSIZ_HOSTMODE; /*!<Non-Periodic Transmit FIFO Size Register [Host Mode] Offset  0x0028*/\r
-__IO uint32_t  GNPTXFSIZ_DEVICEMODE; /*!<Non-Periodic Transmit FIFO Size Register [Device Mode] Offset  0x0028*/\r
- };\r
-__I uint32_t   GNPTXSTS; /*!<Non-Periodic Transmit FIFO/Queue Status Register Offset  0x002C*/\r
-__I  uint32_t  RESERVED1[3];\r
-__IO uint32_t  GUID; /*!<User ID Register Offset  0x003C*/\r
-__I  uint32_t  RESERVED2[7];\r
-__IO uint32_t  GDFIFOCFG; /*!<Global DFIFO Software Config Register Offset  0x005C*/\r
-__I  uint32_t  RESERVED3[40];\r
-__IO uint32_t  HPTXFSIZ; /*!<Host Periodic Transmit FIFO Size Register Offset  0x0100*/\r
-__IO uint32_t  DIEPTXF1; /*!<Device IN Endpoint Transmit FIFO Size Register Offset  0x0104*/\r
-__IO uint32_t  DIEPTXF2; /*!<Device IN Endpoint Transmit FIFO Size Register Offset  0x0108*/\r
-__IO uint32_t  DIEPTXF3; /*!<Device IN Endpoint Transmit FIFO Size Register Offset  0x010C*/\r
-__IO uint32_t  DIEPTXF4; /*!<Device IN Endpoint Transmit FIFO Size Register Offset  0x0110*/\r
-__IO uint32_t  DIEPTXF5; /*!<Device IN Endpoint Transmit FIFO Size Register Offset  0x0114*/\r
-__IO uint32_t  DIEPTXF6; /*!<Device IN Endpoint Transmit FIFO Size Register Offset  0x0118*/\r
-__I  uint32_t  RESERVED4[185];\r
-__IO uint32_t  HCFG; /*!<Host Configuration Register Offset  0x0400*/\r
-__IO uint32_t  HFIR; /*!<Host Frame Interval Register Offset  0x0404*/\r
-__IO uint32_t  HFNUM; /*!<Host Frame Number/Frame Time Remaining Register Offset  0x0408*/\r
-__I  uint32_t  RESERVED5;\r
-__IO uint32_t  HPTXSTS; /*!<Host Periodic Transmit FIFO/ Queue Status Register Offset  0x0410*/\r
-__I uint32_t   HAINT; /*!<Host All Channels Interrupt Register Offset  0x0414*/\r
-__IO uint32_t  HAINTMSK; /*!<Host All Channels Interrupt Mask Register Offset  0x0418*/\r
-__IO uint32_t  HFLBADDR; /*!<Host Frame List Base Address Register Offset  0x041C*/\r
-__I  uint32_t  RESERVED6[8];\r
-__IO uint32_t  HPRT; /*!<Host Port Control and Status Register Offset  0x0440*/\r
-__I  uint32_t  RESERVED7[239];\r
-__IO uint32_t  DCFG; /*!<Device Configuration Register Offset  0x0800*/\r
-__IO uint32_t  DCTL; /*!<Device Control Register Offset  0x0804*/\r
-__I uint32_t   DSTS; /*!<Device Status Register Offset  0x0808*/\r
-__I  uint32_t  RESERVED8;\r
-__IO uint32_t  DIEPMSK; /*!<Device IN Endpoint Common Interrupt Mask Register Offset  0x0810*/\r
-__IO uint32_t  DOEPMSK; /*!<Device OUT Endpoint Common Interrupt Mask Register Offset  0x0814*/\r
-__I uint32_t   DAINT; /*!<Device All Endpoints Interrupt Register Offset  0x0818*/\r
-__IO uint32_t  DAINTMSK; /*!<Device All Endpoints Interrupt Mask Register Offset  0x081C*/\r
-__I  uint32_t  RESERVED9[2];\r
-__IO uint32_t  DVBUSDIS; /*!<Device VBUS Discharge Time Register Offset  0x0828*/\r
-__IO uint32_t  DVBUSPULSE; /*!<Device VBUS Pulsing Time Register Offset  0x082C*/\r
-__I  uint32_t  RESERVED10;\r
-__IO uint32_t  DIEPEMPMSK; /*!<Device IN Endpoint FIFO Empty Interrupt Mask Register Offset  0x0834*/\r
-__I  uint32_t  RESERVED11[370];\r
-__IO uint32_t  PCGCCTL; /*!<Power and Clock Gating Control Register Offset  0x0E00*/\r
-}USB0_GLOBAL_TypeDef;\r
-\r
-  /*\r
-  *ENDPOINT-0 registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  DIEPCTL0; /*!<Device Control IN Endpoint 0 Control Register Offset  0x0900*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  DIEPINT0; /*!<Device Endpoint-0 Interrupt Register Offset  0x0908*/\r
-__I  uint32_t  RESERVED2;\r
-__IO uint32_t  DIEPTSIZ0; /*!<Device IN Endpoint 0 Transfer Size Register Offset  0x0910*/\r
-__IO uint32_t  DIEPDMA0; /*!<Device Endpoint-0 DMA Address Register Offset  0x0914*/\r
-__I uint32_t   DTXFSTS0; /*!<Device IN Endpoint Transmit FIFO Status Register Offset  0x0918*/\r
-__I uint32_t   DIEPDMAB0; /*!<Device Endpoint-0 DMA Buffer Address Register Offset  0x091C*/\r
-__I  uint32_t  RESERVED3[120];\r
-__IO uint32_t  DOEPCTL0; /*!<Device Control OUT Endpoint 0 Control Register Offset  0x0B00*/\r
-__I  uint32_t  RESERVED4;\r
-__IO uint32_t  DOEPINT0; /*!<Device Endpoint-0 Interrupt Register Offset  0x0B08*/\r
-__I  uint32_t  RESERVED5;\r
-__IO uint32_t  DOEPTSIZ0; /*!<Device OUT Endpoint 0 Transfer Size Register Offset  0x0B10*/\r
-__IO uint32_t  DOEPDMA0; /*!<Device Endpoint-0 DMA Address Register Offset  0x0B14*/\r
-__I  uint32_t  RESERVED6;\r
-__I uint32_t   DOEPDMAB0; /*!<Device Endpoint-0 DMA Buffer Address Register Offset  0x0B1C*/\r
-}USB0_EP0_TypeDef;\r
-\r
-  /*\r
-  *ENDPOINTx registers\r
-  */\r
-typedef struct {\r
-union\r
- {\r
-__IO uint32_t  DIEPCTL_INTBULK; /*!<Device Endpoint-1 Control Register [Interrupt/Bulk Endpoint] Offset  0x0920*/\r
-__IO uint32_t  DIEPCTL_ISOCONT; /*!<Device Endpoint-1 Control Register [Isochronous/Control Endpoint] Offset  0x0920*/\r
- };\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  DIEPINT; /*!<Device Endpoint-1 Interrupt Register Offset  0x0928*/\r
-__I  uint32_t  RESERVED2;\r
-__IO uint32_t  DIEPTSIZ; /*!<Device Endpoint-1 Transfer Size Register Offset  0x0930*/\r
-__IO uint32_t  DIEPDMA; /*!<Device Endpoint-1 DMA Address Register Offset  0x0934*/\r
-__I uint32_t   DTXFSTS; /*!<Device IN Endpoint Transmit FIFO Status Register Offset  0x0938*/\r
-__I uint32_t   DIEPDMAB; /*!<Device Endpoint-1 DMA Buffer Address Register Offset  0x093C*/\r
-__I  uint32_t  RESERVED3[120];\r
-union\r
- {\r
-__IO uint32_t  DOEPCTL_INTBULK; /*!<Device Endpoint-1 Control Register [Interrupt/Bulk Endpoint] Offset  0x0B20*/\r
-__IO uint32_t  DOEPCTL_ISOCONT; /*!<Device Endpoint-1 Control Register [Isochronous/Control Endpoint] Offset  0x0B20*/\r
- };\r
-__I  uint32_t  RESERVED4;\r
-__IO uint32_t  DOEPINT; /*!<Device Endpoint-1 Interrupt Register Offset  0x0B28*/\r
-__I  uint32_t  RESERVED5;\r
-union\r
- {\r
-__IO uint32_t  DOEPTSIZ_ISO; /*!<Device Endpoint-1 Transfer Size Register [Isochronous OUT Endpoint] Offset  0x0B30*/\r
-__IO uint32_t  DOEPTSIZ_CONTROL; /*!<Device Endpoint-1 Transfer Size Register [Control OUT Endpoint] Offset  0x0B30*/\r
- };\r
-__IO uint32_t  DOEPDMA; /*!<Device Endpoint-1 DMA Address Register Offset  0x0B34*/\r
-__I  uint32_t  RESERVED6;\r
-__I uint32_t   DOEPDMAB; /*!<Device Endpoint-1 DMA Buffer Address Register Offset  0x0B3C*/\r
-}USB0_EP_TypeDef;\r
-\r
-  /*\r
-  *CHANNEL registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  HCCHAR; /*!<Host Channel-0 Characteristics Register Offset  0x0500*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint32_t  HCINT; /*!<Host Channel-0 Interrupt Register Offset  0x0508*/\r
-__IO uint32_t  HCINTMSK; /*!<Host Channel-0 Interrupt Mask Register Offset  0x050C*/\r
-union\r
- {\r
-__IO uint32_t  HCTSIZ_SCATGATHER; /*!<Host Channel-0 Transfer Size Register [Scatter/Gather DMA Mode] Offset  0x0510*/\r
-__IO uint32_t  HCTSIZ_BUFFERMODE; /*!<Host Channel-0 Transfer Size Register [Buffer DMA Mode] Offset  0x0510*/\r
- };\r
-union\r
- {\r
-__IO uint32_t  HCDMA_SCATGATHER; /*!<Host Channel-0 DMA Address Register [Scatter/Gather DMA Mode] Offset  0x0514*/\r
-__IO uint32_t  HCDMA_BUFFERMODE; /*!<Host Channel-0 DMA Address Register [Buffer DMA Mode] Offset  0x0514*/\r
- };\r
-__I  uint32_t  RESERVED2;\r
-__I uint32_t   HCDMAB; /*!<Host Channel-0 DMA Buffer Address Register Offset  0x051C*/\r
-}USB0_CH_TypeDef;\r
-\r
-#define   USB0_BASE                     ((uint32_t)0x50040000U)\r
-#define   USB0_GLOBAL_BASE              (0x0000U)\r
-#define   USB0_EP0_BASE                 (0x0900U)\r
-#define   USB0_EP1_BASE                 (0x0920U)\r
-#define   USB0_EP2_BASE                 (0x0940U)\r
-#define   USB0_EP3_BASE                 (0x0960U)\r
-#define   USB0_EP4_BASE                 (0x0980U)\r
-#define   USB0_EP5_BASE                 (0x09A0U)\r
-#define   USB0_EP6_BASE                 (0x09C0U)\r
-#define   USB0_CH0_BASE                 (0x0500U)\r
-#define   USB0_CH1_BASE                 (0x0520U)\r
-#define   USB0_CH2_BASE                 (0x0540U)\r
-#define   USB0_CH3_BASE                 (0x0560U)\r
-#define   USB0_CH4_BASE                 (0x0580U)\r
-#define   USB0_CH5_BASE                 (0x05A0U)\r
-#define   USB0_CH6_BASE                 (0x05C0U)\r
-#define   USB0_CH7_BASE                 (0x05E0U)\r
-#define   USB0_CH8_BASE                 (0x0600U)\r
-#define   USB0_CH9_BASE                 (0x0620U)\r
-#define   USB0_CH10_BASE                (0x0640U)\r
-#define   USB0_CH11_BASE                (0x0660U)\r
-#define   USB0_CH12_BASE                (0x0680U)\r
-#define   USB0_CH13_BASE                (0x06A0U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   USB0          ((USB0_GLOBAL_TypeDef*)(USB0_BASE + USB0_GLOBAL_BASE))\r
-#define   USB0_EP0              ((USB0_EP0_TypeDef*)(USB0_BASE + USB0_EP0_BASE))\r
-#define   USB0_EP1              ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP1_BASE))\r
-#define   USB0_EP2              ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP2_BASE))\r
-#define   USB0_EP3              ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP3_BASE))\r
-#define   USB0_EP4              ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP4_BASE))\r
-#define   USB0_EP5              ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP5_BASE))\r
-#define   USB0_EP6              ((USB0_EP_TypeDef*)(USB0_BASE + USB0_EP6_BASE))\r
-#define   USB0_CH0              ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH0_BASE))\r
-#define   USB0_CH1              ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH1_BASE))\r
-#define   USB0_CH2              ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH2_BASE))\r
-#define   USB0_CH3              ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH3_BASE))\r
-#define   USB0_CH4              ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH4_BASE))\r
-#define   USB0_CH5              ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH5_BASE))\r
-#define   USB0_CH6              ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH6_BASE))\r
-#define   USB0_CH7              ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH7_BASE))\r
-#define   USB0_CH8              ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH8_BASE))\r
-#define   USB0_CH9              ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH9_BASE))\r
-#define   USB0_CH10             ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH10_BASE))\r
-#define   USB0_CH11             ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH11_BASE))\r
-#define   USB0_CH12             ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH12_BASE))\r
-#define   USB0_CH13             ((USB0_CH_TypeDef*)(USB0_BASE + USB0_CH13_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     USICx                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *Module wide registers\r
-  */\r
-typedef struct {\r
-__I  uint32_t  RESERVED1[2];\r
-__I uint32_t   ID; /*!<Module Identification Register Offset  0x0008*/\r
-}USIC_GLOBAL_TypeDef;\r
-\r
-  /*\r
-  *Channel Related registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   CCFG; /*!<Channel Configuration Register Offset  0x0004*/\r
-__I  uint32_t  RESERVED1;\r
-__IO uint16_t  KSCFG; /*!<Kernel State Configuration Register Offset  0x000C*/\r
-__I  uint16_t  RESERVED2;\r
-__IO uint32_t  FDR; /*!<Fractional Divider Register Offset  0x0010*/\r
-__IO uint32_t  BRG; /*!<Baud Rate Generator Register Offset  0x0014*/\r
-__IO uint32_t  INPR; /*!<Interrupt Node Pointer Register Offset  0x0018*/\r
-__IO uint32_t  DX0CR; /*!<Input Control Register 0 Offset  0x001C*/\r
-__IO uint32_t  DX1CR; /*!<Input Control Register 1 Offset  0x0020*/\r
-__IO uint32_t  DX2CR; /*!<Input Control Register 2 Offset  0x0024*/\r
-__IO uint32_t  DX3CR; /*!<Input Control Register 3 Offset  0x0028*/\r
-__IO uint32_t  DX4CR; /*!<Input Control Register 4 Offset  0x002C*/\r
-__IO uint32_t  DX5CR; /*!<Input Control Register 5 Offset  0x0030*/\r
-__IO uint32_t  SCTR; /*!<Shift Control Register Offset  0x0034*/\r
-__IO uint32_t  TCSR; /*!<Transmit Control/Status Register Offset  0x0038*/\r
-union\r
- {\r
-__IO uint32_t  PCR_ASCMode; /*!<Protocol Control Register [ASC Mode] Offset  0x003C*/\r
-__IO uint32_t  PCR_SSCMode; /*!<Protocol Control Register [SSC Mode] Offset  0x003C*/\r
-__IO uint32_t  PCR_IISMode; /*!<Protocol Control Register [IIS Mode] Offset  0x003C*/\r
-__IO uint32_t  PCR_IICMode; /*!<Protocol Control Register [IIC Mode] Offset  0x003C*/\r
- };\r
-__IO uint32_t  CCR; /*!<Channel Control Register Offset  0x0040*/\r
-__IO uint32_t  CMTR; /*!<Capture Mode Timer Register Offset  0x0044*/\r
-union\r
- {\r
-__IO uint32_t  PSR_ASCMode; /*!<Protocol Status Register [ASC Mode] Offset  0x0048*/\r
-__IO uint32_t  PSR_SSCMode; /*!<Protocol Status Register [SSC Mode] Offset  0x0048*/\r
-__IO uint32_t  PSR_IISMode; /*!<Protocol Status Register [IIS Mode] Offset  0x0048*/\r
-__IO uint32_t  PSR_IICMode; /*!<Protocol Status Register [IIC Mode] Offset  0x0048*/\r
- };\r
-__O uint32_t   PSCR; /*!<Protocol Status Clear Register Offset  0x004C*/\r
-__I uint32_t   RBUFSR; /*!<Receiver Buffer Status Register Offset  0x0050*/\r
-__I uint32_t   RBUF; /*!<Receiver Buffer Register Offset  0x0054*/\r
-__I uint32_t   RBUFD; /*!<Receiver Buffer Register for Debugger Offset  0x0058*/\r
-__I uint32_t   RBUF0; /*!<Receiver Buffer Register 0 Offset  0x005C*/\r
-__I uint32_t   RBUF1; /*!<Receiver Buffer Register 1 Offset  0x0060*/\r
-__I uint32_t   RBUF01SR; /*!<Receiver Buffer 01 Status Register Offset  0x0064*/\r
-__O uint32_t   FMR; /*!<Flag Modification Register Offset  0x0068*/\r
-__I  uint32_t  RESERVED3[5];\r
-__IO uint32_t  TBUF[32]; /*!<Transmit Buffer Input Location 00 Offset  0x0080*/\r
-__IO uint32_t  BYP; /*!<Bypass Data Register Offset  0x0100*/\r
-__IO uint32_t  BYPCR; /*!<Bypass Control Register Offset  0x0104*/\r
-__IO uint32_t  TBCTR; /*!<Transmitter Buffer Control Register Offset  0x0108*/\r
-__IO uint32_t  RBCTR; /*!<Receiver Buffer Control Register Offset  0x010C*/\r
-__I uint32_t   TRBPTR; /*!<Transmit/Receive Buffer Pointer Register Offset  0x0110*/\r
-__IO uint32_t  TRBSR; /*!<Transmit/Receive Buffer Status Register Offset  0x0114*/\r
-__O uint32_t   TRBSCR; /*!<Transmit/Receive Buffer Status Clear Register Offset  0x0118*/\r
-__I uint32_t   OUTR; /*!<Receiver Buffer Output Register Offset  0x011C*/\r
-__I uint32_t   OUTDR; /*!<Receiver Buffer Output Register L for Debugger Offset  0x0120*/\r
-__I  uint32_t  RESERVED4[23];\r
-__O uint32_t   IN[32]; /*!<Transmit FIFO Buffer Input Location 00 Offset  0x0180*/\r
-}USIC_CH_TypeDef;\r
-\r
-#define   USIC0_BASE                    ((uint32_t)0x40030000U)\r
-#define   USIC1_BASE                    ((uint32_t)0x48020000U)\r
-#define   USIC2_BASE                    ((uint32_t)0x48024000U)\r
-#define   USIC_GLOBAL_BASE              (0x0000U)\r
-#define   USIC0_CH0_BASE                (0x0004U)\r
-#define   USIC0_CH1_BASE                (0x0204U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   USIC0                 ((USIC_GLOBAL_TypeDef*)(USIC0_BASE + USIC_GLOBAL_BASE))\r
-#define   USIC0_CH0             ((USIC_CH_TypeDef*)(USIC0_BASE + USIC0_CH0_BASE))\r
-#define   USIC0_CH1             ((USIC_CH_TypeDef*)(USIC0_BASE + USIC0_CH1_BASE))\r
-#define   USIC1                 ((USIC_GLOBAL_TypeDef*)(USIC1_BASE + USIC_GLOBAL_BASE))\r
-#define   USIC1_CH0             ((USIC_CH_TypeDef*)(USIC1_BASE + USIC0_CH0_BASE))\r
-#define   USIC1_CH1             ((USIC_CH_TypeDef*)(USIC1_BASE + USIC0_CH1_BASE))\r
-#define   USIC2                 ((USIC_GLOBAL_TypeDef*)(USIC2_BASE + USIC_GLOBAL_BASE))\r
-#define   USIC2_CH0             ((USIC_CH_TypeDef*)(USIC2_BASE + USIC0_CH0_BASE))\r
-#define   USIC2_CH1             ((USIC_CH_TypeDef*)(USIC2_BASE + USIC0_CH1_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     VADC                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *ADC Group registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  ARBCFG; /*!<Arbitration Configuration Register, Group 0 Offset  0x0480*/\r
-__IO uint32_t  ARBPR; /*!<Arbitration Priority Register, Group 0 Offset  0x0484*/\r
-__IO uint32_t  CHASS; /*!<Channel Assignment Register, Group 0 Offset  0x0488*/\r
-__I  uint32_t  RESERVED1[5];\r
-__IO uint32_t  ICLASS[2]; /*!<Input Class Register , Group 0 Offset  0x04A0*/\r
-__I  uint32_t  RESERVED2[2];\r
-__IO uint32_t  ALIAS; /*!<Alias Register, Group 0 Offset  0x04B0*/\r
-__I  uint32_t  RESERVED3;\r
-__IO uint32_t  BOUND; /*!<Boundary Select Register, Group 0 Offset  0x04B8*/\r
-__I  uint32_t  RESERVED4;\r
-__IO uint32_t  SYNCTR; /*!<Synchronization Control Register, Group 0 Offset  0x04C0*/\r
-__I  uint32_t  RESERVED5;\r
-__IO uint32_t  BFL; /*!<Boundary Flag Register, Group 0 Offset  0x04C8*/\r
-__I  uint32_t  RESERVED6[13];\r
-__IO uint32_t  QCTRL0; /*!<Queue 0 Source Control Register, Group 0 Offset  0x0500*/\r
-__IO uint32_t  QMR0; /*!<Queue 0 Mode Register, Group 0 Offset  0x0504*/\r
-__I uint32_t   QSR0; /*!<Queue 0 Status Register, Group 0 Offset  0x0508*/\r
-__I uint32_t   Q0R0; /*!<Queue 0 Register 0, Group 0 Offset  0x050C*/\r
-union\r
- {\r
-__I uint32_t   QBUR0; /*!<Queue 0 Backup Register, Group 0 Offset  0x0510*/\r
-__O uint32_t   QINR0; /*!<Queue 0 Input Register, Group 0 Offset  0x0510*/\r
- };\r
-__I  uint32_t  RESERVED7[3];\r
-__IO uint32_t  ASCTRL; /*!<Autoscan Source Control Register, Group 0 Offset  0x0520*/\r
-__IO uint32_t  ASMR; /*!<Autoscan Source Mode Register, Group 0 Offset  0x0524*/\r
-__IO uint32_t  ASSEL; /*!<Autoscan Source Channel Select Register, Group 0 Offset  0x0528*/\r
-__IO uint32_t  ASPND; /*!<Autoscan Source Pending Register, Group 0 Offset  0x052C*/\r
-__I  uint32_t  RESERVED8[20];\r
-__IO uint32_t  CEFLAG; /*!<Channel Event Flag Register, Group 0 Offset  0x0580*/\r
-__IO uint32_t  REFLAG; /*!<Result Event Flag Register, Group 0 Offset  0x0584*/\r
-__IO uint32_t  SEFLAG; /*!<Source Event Flag Register, Group 0 Offset  0x0588*/\r
-__I  uint32_t  RESERVED9;\r
-__O uint32_t   CEFCLR; /*!<Channel Event Flag Clear Register, Group 0 Offset  0x0590*/\r
-__O uint32_t   REFCLR; /*!<Result Event Flag Clear Register, Group 0 Offset  0x0594*/\r
-__O uint32_t   SEFCLR; /*!<Source Event Flag Clear Register, Group 0 Offset  0x0598*/\r
-__I  uint32_t  RESERVED10;\r
-__IO uint32_t  CEVNP0; /*!<Channel Event Node Pointer Register 0, Group 0 Offset  0x05A0*/\r
-__I  uint32_t  RESERVED11[3];\r
-__IO uint32_t  REVNP0; /*!<Result Event Node Pointer Register 0, Group 0 Offset  0x05B0*/\r
-__IO uint32_t  REVNP1; /*!<Result Event Node Pointer Register 1, Group 0 Offset  0x05B4*/\r
-__I  uint32_t  RESERVED12[2];\r
-__IO uint32_t  SEVNP; /*!<Source Event Node Pointer Register, Group 0 Offset  0x05C0*/\r
-__I  uint32_t  RESERVED13;\r
-__O uint32_t   SRACT; /*!<Service Request Software Activation Trigger, Group 0 Offset  0x05C8*/\r
-__I  uint32_t  RESERVED14[9];\r
-__IO uint32_t  EMUXCTR; /*!<E0ternal Multiplexer Control Register, Group x Offset  0x05F0*/\r
-__I  uint32_t  RESERVED15;\r
-__IO uint32_t  VFR; /*!<Valid Flag Register, Group 0 Offset  0x05F8*/\r
-__I  uint32_t  RESERVED16;\r
-__IO uint32_t  CHCTR[8]; /*!<Group 0, Channel 0 Ctrl. Reg. Offset  0x0600*/\r
-__I  uint32_t  RESERVED17[24];\r
-__IO uint32_t  RCR[16]; /*!<Group 0 Result Control Reg. 0 Offset  0x0680*/\r
-__I  uint32_t  RESERVED18[16];\r
-__IO uint32_t  RES[16]; /*!<Group 0 Result Register 0 Offset  0x0700*/\r
-__I  uint32_t  RESERVED19[16];\r
-__I uint32_t   RESD[16]; /*!<Group 0 Result Reg. 0, Debug Offset  0x0780*/\r
-}VADC_G_TypeDef;\r
-\r
-  /*\r
-  *ADC global registers\r
-  */\r
-typedef struct {\r
-__IO uint32_t  CLC; /*!<Clock Control Register Offset  0x0000*/\r
-__I  uint32_t  RESERVED1;\r
-__I uint32_t   ID; /*!<Module Identification Register Offset  0x0008*/\r
-__I  uint32_t  RESERVED2[7];\r
-__IO uint32_t  OCS; /*!<OCDS Control and Status Register Offset  0x0028*/\r
-__I  uint32_t  RESERVED3[21];\r
-__IO uint32_t  GLOBCFG; /*!<Global Configuration Register Offset  0x0080*/\r
-__I  uint32_t  RESERVED4[7];\r
-__IO uint32_t  GLOBICLASS[2]; /*!<Input Class Register 0, Global Offset  0x00A0*/\r
-__I  uint32_t  RESERVED5[4];\r
-__IO uint32_t  GLOBBOUND; /*!<Global Boundary Select Register Offset  0x00B8*/\r
-__I  uint32_t  RESERVED6[9];\r
-__IO uint32_t  GLOBEFLAG; /*!<Global Event Flag Register Offset  0x00E0*/\r
-__I  uint32_t  RESERVED7[23];\r
-__IO uint32_t  GLOBEVNP; /*!<Global Event Node Pointer Register Offset  0x0140*/\r
-__I  uint32_t  RESERVED8[7];\r
-__IO uint32_t  GLOBTF; /*!<Global Test Functions Register Offset  0x0160*/\r
-__I  uint32_t  RESERVED9[7];\r
-__IO uint32_t  BRSSEL[4]; /*!<Background Request Source Channel Select Register, Group 0 Offset  0x0180*/\r
-__I  uint32_t  RESERVED10[12];\r
-__IO uint32_t  BRSPND[4]; /*!<Background Request Source Pending Register, Group 0 Offset  0x01C0*/\r
-__I  uint32_t  RESERVED11[12];\r
-__IO uint32_t  BRSCTRL; /*!<Background Request Source Control Register Offset  0x0200*/\r
-__IO uint32_t  BRSMR; /*!<Background Request Source Mode Register Offset  0x0204*/\r
-__I  uint32_t  RESERVED12[30];\r
-__IO uint32_t  GLOBRCR; /*!<Global Result Control Register Offset  0x0280*/\r
-__I  uint32_t  RESERVED13[31];\r
-__IO uint32_t  GLOBRES; /*!<Global Result Register Offset  0x0300*/\r
-__I  uint32_t  RESERVED14[31];\r
-__IO uint32_t  GLOBRESD; /*!<Global Result Register, Debug Offset  0x0380*/\r
-__I  uint32_t  RESERVED15[27];\r
-__IO uint32_t  EMUXSEL; /*!<External Multiplexer Select Register Offset  0x03F0*/\r
-}VADC_GLOBAL_TypeDef;\r
-\r
-#define   VADC_BASE                     ((uint32_t)0x40004000U)\r
-#define   VADC_G0_BASE          (0x0480U)\r
-#define   VADC_G1_BASE          (0x0880U)\r
-#define   VADC_G2_BASE          (0x0C80U)\r
-#define   VADC_G3_BASE          (0x1080U)\r
-#define   VADC_GLOBAL_BASE              (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   VADC_G0               ((VADC_G_TypeDef*)(VADC_BASE + VADC_G0_BASE))\r
-#define   VADC_G1               ((VADC_G_TypeDef*)(VADC_BASE + VADC_G1_BASE))\r
-#define   VADC_G2               ((VADC_G_TypeDef*)(VADC_BASE + VADC_G2_BASE))\r
-#define   VADC_G3               ((VADC_G_TypeDef*)(VADC_BASE + VADC_G3_BASE))\r
-#define   VADC          ((VADC_GLOBAL_TypeDef*)(VADC_BASE + VADC_GLOBAL_BASE))\r
-\r
-/***************************************************************************/\r
-/*                     WDT                          */\r
-/***************************************************************************/\r
-\r
-  /*\r
-  *WDT Kernel registers\r
-  */\r
-typedef struct {\r
-__I uint32_t   ID; /*!<WDT ID Register Offset  0x0000*/\r
-__IO uint32_t  CTR; /*!<WDT Control Register Offset  0x0004*/\r
-__O uint32_t   SRV; /*!<WDT Service Register Offset  0x0008*/\r
-__I uint32_t   TIM; /*!<WDT Timer Register Offset  0x000C*/\r
-__IO uint32_t  WLB; /*!<WDT Window Lower Bound Register Offset  0x0010*/\r
-__IO uint32_t  WUB; /*!<WDT Window Upper Bound Register Offset  0x0014*/\r
-__I uint32_t   WDTSTS; /*!<WDT Status Register Offset  0x0018*/\r
-__O uint32_t   WDTCLR; /*!<WDT Clear Register Offset  0x001C*/\r
-}WDT_GLOBAL_TypeDef;\r
-\r
-#define   WDT_BASE                      ((uint32_t)0x50008000U)\r
-#define   WDT_GLOBAL_BASE               (0x0000U)\r
-/***************************************************************************/\r
-/* Peripheral Declaration                                                  */\r
-/***************************************************************************/\r
-#define   WDT           ((WDT_GLOBAL_TypeDef*)(WDT_BASE + WDT_GLOBAL_BASE))\r
-\r
-\r
-/************************** Bit Fileds *************************************/\r
-/***************************************************************************/\r
-\r
-\r
-/***   CAN Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* CAN_CLC  =  CAN Clock Control Register*/\r
-#define   CAN_CLC_DISR_Pos     (0U)\r
-#define   CAN_CLC_DISR_Msk     (0x00000001U  << CAN_CLC_DISR_Pos)\r
-\r
-#define   CAN_CLC_DISS_Pos     (1U)\r
-#define   CAN_CLC_DISS_Msk     (0x00000001U  << CAN_CLC_DISS_Pos)\r
-\r
-#define   CAN_CLC_EDIS_Pos     (3U)\r
-#define   CAN_CLC_EDIS_Msk     (0x00000001U  << CAN_CLC_EDIS_Pos)\r
-\r
-#define   CAN_CLC_SBWE_Pos     (4U)\r
-#define   CAN_CLC_SBWE_Msk     (0x00000001U  << CAN_CLC_SBWE_Pos)\r
-\r
-/* CAN_ID  =  Module Identification Register*/\r
-#define   CAN_ID_MOD_REV_Pos   (0U)\r
-#define   CAN_ID_MOD_REV_Msk   (0x000000FFU  << CAN_ID_MOD_REV_Pos)\r
-\r
-#define   CAN_ID_MOD_TYPE_Pos          (8U)\r
-#define   CAN_ID_MOD_TYPE_Msk          (0x000000FFU  << CAN_ID_MOD_TYPE_Pos)\r
-\r
-#define   CAN_ID_MOD_NUMBER_Pos        (16U)\r
-#define   CAN_ID_MOD_NUMBER_Msk        (0x0000FFFFU  << CAN_ID_MOD_NUMBER_Pos)\r
-\r
-/* CAN_FDR  =  CAN Fractional Divider Register*/\r
-#define   CAN_FDR_STEP_Pos     (0U)\r
-#define   CAN_FDR_STEP_Msk     (0x000003FFU  << CAN_FDR_STEP_Pos)\r
-\r
-#define   CAN_FDR_SM_Pos       (11U)\r
-#define   CAN_FDR_SM_Msk       (0x00000001U  << CAN_FDR_SM_Pos)\r
-\r
-#define   CAN_FDR_SC_Pos       (12U)\r
-#define   CAN_FDR_SC_Msk       (0x00000003U  << CAN_FDR_SC_Pos)\r
-\r
-#define   CAN_FDR_DM_Pos       (14U)\r
-#define   CAN_FDR_DM_Msk       (0x00000003U  << CAN_FDR_DM_Pos)\r
-\r
-#define   CAN_FDR_RESULT_Pos   (16U)\r
-#define   CAN_FDR_RESULT_Msk   (0x000003FFU  << CAN_FDR_RESULT_Pos)\r
-\r
-#define   CAN_FDR_SUSACK_Pos   (28U)\r
-#define   CAN_FDR_SUSACK_Msk   (0x00000001U  << CAN_FDR_SUSACK_Pos)\r
-\r
-#define   CAN_FDR_SUSREQ_Pos   (29U)\r
-#define   CAN_FDR_SUSREQ_Msk   (0x00000001U  << CAN_FDR_SUSREQ_Pos)\r
-\r
-#define   CAN_FDR_ENHW_Pos     (30U)\r
-#define   CAN_FDR_ENHW_Msk     (0x00000001U  << CAN_FDR_ENHW_Pos)\r
-\r
-#define   CAN_FDR_DISCLK_Pos   (31U)\r
-#define   CAN_FDR_DISCLK_Msk   (0x00000001U  << CAN_FDR_DISCLK_Pos)\r
-\r
-/* CAN_LIST  =  List Register 0*/\r
-#define   CAN_LIST_BEGIN_Pos   (0U)\r
-#define   CAN_LIST_BEGIN_Msk   (0x000000FFU  << CAN_LIST_BEGIN_Pos)\r
-\r
-#define   CAN_LIST_END_Pos     (8U)\r
-#define   CAN_LIST_END_Msk     (0x000000FFU  << CAN_LIST_END_Pos)\r
-\r
-#define   CAN_LIST_SIZE_Pos    (16U)\r
-#define   CAN_LIST_SIZE_Msk    (0x000000FFU  << CAN_LIST_SIZE_Pos)\r
-\r
-#define   CAN_LIST_EMPTY_Pos   (24U)\r
-#define   CAN_LIST_EMPTY_Msk   (0x00000001U  << CAN_LIST_EMPTY_Pos)\r
-\r
-/* CAN_MSPND  =  Message Pending Register 0*/\r
-#define   CAN_MSPND_PND_Pos    (0U)\r
-#define   CAN_MSPND_PND_Msk    (0xFFFFFFFFU  << CAN_MSPND_PND_Pos)\r
-\r
-/* CAN_MSID  =  Message Index Register 0*/\r
-#define   CAN_MSID_INDEX_Pos   (0U)\r
-#define   CAN_MSID_INDEX_Msk   (0x0000003FU  << CAN_MSID_INDEX_Pos)\r
-\r
-/* CAN_MSIMASK  =  Message Index Mask Register*/\r
-#define   CAN_MSIMASK_IM_Pos   (0U)\r
-#define   CAN_MSIMASK_IM_Msk   (0xFFFFFFFFU  << CAN_MSIMASK_IM_Pos)\r
-\r
-/* CAN_PANCTR  =  Panel Control Register*/\r
-#define   CAN_PANCTR_PANCMD_Pos        (0U)\r
-#define   CAN_PANCTR_PANCMD_Msk        (0x000000FFU  << CAN_PANCTR_PANCMD_Pos)\r
-\r
-#define   CAN_PANCTR_BUSY_Pos          (8U)\r
-#define   CAN_PANCTR_BUSY_Msk          (0x00000001U  << CAN_PANCTR_BUSY_Pos)\r
-\r
-#define   CAN_PANCTR_RBUSY_Pos         (9U)\r
-#define   CAN_PANCTR_RBUSY_Msk         (0x00000001U  << CAN_PANCTR_RBUSY_Pos)\r
-\r
-#define   CAN_PANCTR_PANAR1_Pos        (16U)\r
-#define   CAN_PANCTR_PANAR1_Msk        (0x000000FFU  << CAN_PANCTR_PANAR1_Pos)\r
-\r
-#define   CAN_PANCTR_PANAR2_Pos        (24U)\r
-#define   CAN_PANCTR_PANAR2_Msk        (0x000000FFU  << CAN_PANCTR_PANAR2_Pos)\r
-\r
-/* CAN_MCR  =  Module Control Register*/\r
-#define   CAN_MCR_MPSEL_Pos    (12U)\r
-#define   CAN_MCR_MPSEL_Msk    (0x0000000FU  << CAN_MCR_MPSEL_Pos)\r
-\r
-/* CAN_MITR  =  Module Interrupt Trigger Register*/\r
-#define   CAN_MITR_IT_Pos      (0U)\r
-#define   CAN_MITR_IT_Msk      (0x000000FFU  << CAN_MITR_IT_Pos)\r
-\r
-/* CAN_NODE_NCRx  =  Node x Control Register*/\r
-#define   CAN_NODE_NCR_INIT_Pos        (0U)\r
-#define   CAN_NODE_NCR_INIT_Msk        (0x00000001U  << CAN_NODE_NCR_INIT_Pos)\r
-\r
-#define   CAN_NODE_NCR_TRIE_Pos        (1U)\r
-#define   CAN_NODE_NCR_TRIE_Msk        (0x00000001U  << CAN_NODE_NCR_TRIE_Pos)\r
-\r
-#define   CAN_NODE_NCR_LECIE_Pos       (2U)\r
-#define   CAN_NODE_NCR_LECIE_Msk       (0x00000001U  << CAN_NODE_NCR_LECIE_Pos)\r
-\r
-#define   CAN_NODE_NCR_ALIE_Pos        (3U)\r
-#define   CAN_NODE_NCR_ALIE_Msk        (0x00000001U  << CAN_NODE_NCR_ALIE_Pos)\r
-\r
-#define   CAN_NODE_NCR_CANDIS_Pos      (4U)\r
-#define   CAN_NODE_NCR_CANDIS_Msk      (0x00000001U  << CAN_NODE_NCR_CANDIS_Pos)\r
-\r
-#define   CAN_NODE_NCR_CCE_Pos         (6U)\r
-#define   CAN_NODE_NCR_CCE_Msk         (0x00000001U  << CAN_NODE_NCR_CCE_Pos)\r
-\r
-#define   CAN_NODE_NCR_CALM_Pos        (7U)\r
-#define   CAN_NODE_NCR_CALM_Msk        (0x00000001U  << CAN_NODE_NCR_CALM_Pos)\r
-\r
-#define   CAN_NODE_NCR_SUSEN_Pos       (8U)\r
-#define   CAN_NODE_NCR_SUSEN_Msk       (0x00000001U  << CAN_NODE_NCR_SUSEN_Pos)\r
-\r
-/* CAN_NODE_NSRx  =  Node x Status Register*/\r
-#define   CAN_NODE_NSR_LEC_Pos         (0U)\r
-#define   CAN_NODE_NSR_LEC_Msk         (0x00000007U  << CAN_NODE_NSR_LEC_Pos)\r
-\r
-#define   CAN_NODE_NSR_TXOK_Pos        (3U)\r
-#define   CAN_NODE_NSR_TXOK_Msk        (0x00000001U  << CAN_NODE_NSR_TXOK_Pos)\r
-\r
-#define   CAN_NODE_NSR_RXOK_Pos        (4U)\r
-#define   CAN_NODE_NSR_RXOK_Msk        (0x00000001U  << CAN_NODE_NSR_RXOK_Pos)\r
-\r
-#define   CAN_NODE_NSR_ALERT_Pos       (5U)\r
-#define   CAN_NODE_NSR_ALERT_Msk       (0x00000001U  << CAN_NODE_NSR_ALERT_Pos)\r
-\r
-#define   CAN_NODE_NSR_EWRN_Pos        (6U)\r
-#define   CAN_NODE_NSR_EWRN_Msk        (0x00000001U  << CAN_NODE_NSR_EWRN_Pos)\r
-\r
-#define   CAN_NODE_NSR_BOFF_Pos        (7U)\r
-#define   CAN_NODE_NSR_BOFF_Msk        (0x00000001U  << CAN_NODE_NSR_BOFF_Pos)\r
-\r
-#define   CAN_NODE_NSR_LLE_Pos         (8U)\r
-#define   CAN_NODE_NSR_LLE_Msk         (0x00000001U  << CAN_NODE_NSR_LLE_Pos)\r
-\r
-#define   CAN_NODE_NSR_LOE_Pos         (9U)\r
-#define   CAN_NODE_NSR_LOE_Msk         (0x00000001U  << CAN_NODE_NSR_LOE_Pos)\r
-\r
-#define   CAN_NODE_NSR_SUSACK_Pos      (10U)\r
-#define   CAN_NODE_NSR_SUSACK_Msk      (0x00000001U  << CAN_NODE_NSR_SUSACK_Pos)\r
-\r
-/* CAN_NODE_NIPRx  =  Node x Interrupt Pointer Register*/\r
-#define   CAN_NODE_NIPR_ALINP_Pos      (0U)\r
-#define   CAN_NODE_NIPR_ALINP_Msk      (0x00000007U  << CAN_NODE_NIPR_ALINP_Pos)\r
-\r
-#define   CAN_NODE_NIPR_LECINP_Pos     (4U)\r
-#define   CAN_NODE_NIPR_LECINP_Msk     (0x00000007U  << CAN_NODE_NIPR_LECINP_Pos)\r
-\r
-#define   CAN_NODE_NIPR_TRINP_Pos      (8U)\r
-#define   CAN_NODE_NIPR_TRINP_Msk      (0x00000007U  << CAN_NODE_NIPR_TRINP_Pos)\r
-\r
-#define   CAN_NODE_NIPR_CFCINP_Pos     (12U)\r
-#define   CAN_NODE_NIPR_CFCINP_Msk     (0x00000007U  << CAN_NODE_NIPR_CFCINP_Pos)\r
-\r
-/* CAN_NODE_NPCRx  =  Node x Port Control Register*/\r
-#define   CAN_NODE_NPCR_RXSEL_Pos      (0U)\r
-#define   CAN_NODE_NPCR_RXSEL_Msk      (0x00000007U  << CAN_NODE_NPCR_RXSEL_Pos)\r
-\r
-#define   CAN_NODE_NPCR_LBM_Pos        (8U)\r
-#define   CAN_NODE_NPCR_LBM_Msk        (0x00000001U  << CAN_NODE_NPCR_LBM_Pos)\r
-\r
-/* CAN_NODE_NBTRx  =  Node x Bit Timing Register*/\r
-#define   CAN_NODE_NBTR_BRP_Pos        (0U)\r
-#define   CAN_NODE_NBTR_BRP_Msk        (0x0000003FU  << CAN_NODE_NBTR_BRP_Pos)\r
-\r
-#define   CAN_NODE_NBTR_SJW_Pos        (6U)\r
-#define   CAN_NODE_NBTR_SJW_Msk        (0x00000003U  << CAN_NODE_NBTR_SJW_Pos)\r
-\r
-#define   CAN_NODE_NBTR_TSEG1_Pos      (8U)\r
-#define   CAN_NODE_NBTR_TSEG1_Msk      (0x0000000FU  << CAN_NODE_NBTR_TSEG1_Pos)\r
-\r
-#define   CAN_NODE_NBTR_TSEG2_Pos      (12U)\r
-#define   CAN_NODE_NBTR_TSEG2_Msk      (0x00000007U  << CAN_NODE_NBTR_TSEG2_Pos)\r
-\r
-#define   CAN_NODE_NBTR_DIV8_Pos       (15U)\r
-#define   CAN_NODE_NBTR_DIV8_Msk       (0x00000001U  << CAN_NODE_NBTR_DIV8_Pos)\r
-\r
-/* CAN_NODE_NECNTx  =  Node x Error Counter Register*/\r
-#define   CAN_NODE_NECNT_REC_Pos       (0U)\r
-#define   CAN_NODE_NECNT_REC_Msk       (0x000000FFU  << CAN_NODE_NECNT_REC_Pos)\r
-\r
-#define   CAN_NODE_NECNT_TEC_Pos       (8U)\r
-#define   CAN_NODE_NECNT_TEC_Msk       (0x000000FFU  << CAN_NODE_NECNT_TEC_Pos)\r
-\r
-#define   CAN_NODE_NECNT_EWRNLVL_Pos   (16U)\r
-#define   CAN_NODE_NECNT_EWRNLVL_Msk   (0x000000FFU  << CAN_NODE_NECNT_EWRNLVL_Pos)\r
-\r
-#define   CAN_NODE_NECNT_LETD_Pos      (24U)\r
-#define   CAN_NODE_NECNT_LETD_Msk      (0x00000001U  << CAN_NODE_NECNT_LETD_Pos)\r
-\r
-#define   CAN_NODE_NECNT_LEINC_Pos     (25U)\r
-#define   CAN_NODE_NECNT_LEINC_Msk     (0x00000001U  << CAN_NODE_NECNT_LEINC_Pos)\r
-\r
-/* CAN_NODE_NFCRx  =  Node x Frame Counter Register*/\r
-#define   CAN_NODE_NFCR_CFC_Pos        (0U)\r
-#define   CAN_NODE_NFCR_CFC_Msk        (0x0000FFFFU  << CAN_NODE_NFCR_CFC_Pos)\r
-\r
-#define   CAN_NODE_NFCR_CFSEL_Pos      (16U)\r
-#define   CAN_NODE_NFCR_CFSEL_Msk      (0x00000007U  << CAN_NODE_NFCR_CFSEL_Pos)\r
-\r
-#define   CAN_NODE_NFCR_CFMOD_Pos      (19U)\r
-#define   CAN_NODE_NFCR_CFMOD_Msk      (0x00000003U  << CAN_NODE_NFCR_CFMOD_Pos)\r
-\r
-#define   CAN_NODE_NFCR_CFCIE_Pos      (22U)\r
-#define   CAN_NODE_NFCR_CFCIE_Msk      (0x00000001U  << CAN_NODE_NFCR_CFCIE_Pos)\r
-\r
-#define   CAN_NODE_NFCR_CFCOV_Pos      (23U)\r
-#define   CAN_NODE_NFCR_CFCOV_Msk      (0x00000001U  << CAN_NODE_NFCR_CFCOV_Pos)\r
-\r
-/* CAN_MO_MOFCRx  =  Message Object x Function Control Register*/\r
-#define   CAN_MO_MOFCR_MMC_Pos         (0U)\r
-#define   CAN_MO_MOFCR_MMC_Msk         (0x0000000FU  << CAN_MO_MOFCR_MMC_Pos)\r
-\r
-#define   CAN_MO_MOFCR_GDFS_Pos        (8U)\r
-#define   CAN_MO_MOFCR_GDFS_Msk        (0x00000001U  << CAN_MO_MOFCR_GDFS_Pos)\r
-\r
-#define   CAN_MO_MOFCR_IDC_Pos         (9U)\r
-#define   CAN_MO_MOFCR_IDC_Msk         (0x00000001U  << CAN_MO_MOFCR_IDC_Pos)\r
-\r
-#define   CAN_MO_MOFCR_DLCC_Pos        (10U)\r
-#define   CAN_MO_MOFCR_DLCC_Msk        (0x00000001U  << CAN_MO_MOFCR_DLCC_Pos)\r
-\r
-#define   CAN_MO_MOFCR_DATC_Pos        (11U)\r
-#define   CAN_MO_MOFCR_DATC_Msk        (0x00000001U  << CAN_MO_MOFCR_DATC_Pos)\r
-\r
-#define   CAN_MO_MOFCR_RXIE_Pos        (16U)\r
-#define   CAN_MO_MOFCR_RXIE_Msk        (0x00000001U  << CAN_MO_MOFCR_RXIE_Pos)\r
-\r
-#define   CAN_MO_MOFCR_TXIE_Pos        (17U)\r
-#define   CAN_MO_MOFCR_TXIE_Msk        (0x00000001U  << CAN_MO_MOFCR_TXIE_Pos)\r
-\r
-#define   CAN_MO_MOFCR_OVIE_Pos        (18U)\r
-#define   CAN_MO_MOFCR_OVIE_Msk        (0x00000001U  << CAN_MO_MOFCR_OVIE_Pos)\r
-\r
-#define   CAN_MO_MOFCR_FRREN_Pos       (20U)\r
-#define   CAN_MO_MOFCR_FRREN_Msk       (0x00000001U  << CAN_MO_MOFCR_FRREN_Pos)\r
-\r
-#define   CAN_MO_MOFCR_RMM_Pos         (21U)\r
-#define   CAN_MO_MOFCR_RMM_Msk         (0x00000001U  << CAN_MO_MOFCR_RMM_Pos)\r
-\r
-#define   CAN_MO_MOFCR_SDT_Pos         (22U)\r
-#define   CAN_MO_MOFCR_SDT_Msk         (0x00000001U  << CAN_MO_MOFCR_SDT_Pos)\r
-\r
-#define   CAN_MO_MOFCR_STT_Pos         (23U)\r
-#define   CAN_MO_MOFCR_STT_Msk         (0x00000001U  << CAN_MO_MOFCR_STT_Pos)\r
-\r
-#define   CAN_MO_MOFCR_DLC_Pos         (24U)\r
-#define   CAN_MO_MOFCR_DLC_Msk         (0x0000000FU  << CAN_MO_MOFCR_DLC_Pos)\r
-\r
-/* CAN_MO_MOFGPRx  =  Message Object x FIFO/Gateway Pointer Register*/\r
-#define   CAN_MO_MOFGPR_BOT_Pos        (0U)\r
-#define   CAN_MO_MOFGPR_BOT_Msk        (0x000000FFU  << CAN_MO_MOFGPR_BOT_Pos)\r
-\r
-#define   CAN_MO_MOFGPR_TOP_Pos        (8U)\r
-#define   CAN_MO_MOFGPR_TOP_Msk        (0x000000FFU  << CAN_MO_MOFGPR_TOP_Pos)\r
-\r
-#define   CAN_MO_MOFGPR_CUR_Pos        (16U)\r
-#define   CAN_MO_MOFGPR_CUR_Msk        (0x000000FFU  << CAN_MO_MOFGPR_CUR_Pos)\r
-\r
-#define   CAN_MO_MOFGPR_SEL_Pos        (24U)\r
-#define   CAN_MO_MOFGPR_SEL_Msk        (0x000000FFU  << CAN_MO_MOFGPR_SEL_Pos)\r
-\r
-/* CAN_MO_MOIPRx  =  Message Object x Interrupt Pointer Register*/\r
-#define   CAN_MO_MOIPR_RXINP_Pos       (0U)\r
-#define   CAN_MO_MOIPR_RXINP_Msk       (0x00000007U  << CAN_MO_MOIPR_RXINP_Pos)\r
-\r
-#define   CAN_MO_MOIPR_TXINP_Pos       (4U)\r
-#define   CAN_MO_MOIPR_TXINP_Msk       (0x00000007U  << CAN_MO_MOIPR_TXINP_Pos)\r
-\r
-#define   CAN_MO_MOIPR_MPN_Pos         (8U)\r
-#define   CAN_MO_MOIPR_MPN_Msk         (0x000000FFU  << CAN_MO_MOIPR_MPN_Pos)\r
-\r
-#define   CAN_MO_MOIPR_CFCVAL_Pos      (16U)\r
-#define   CAN_MO_MOIPR_CFCVAL_Msk      (0x0000FFFFU  << CAN_MO_MOIPR_CFCVAL_Pos)\r
-\r
-/* CAN_MO_MOAMRx  =  Message Object x Acceptance Mask Register*/\r
-#define   CAN_MO_MOAMR_AM_Pos          (0U)\r
-#define   CAN_MO_MOAMR_AM_Msk          (0x1FFFFFFFU  << CAN_MO_MOAMR_AM_Pos)\r
-\r
-#define   CAN_MO_MOAMR_MIDE_Pos        (29U)\r
-#define   CAN_MO_MOAMR_MIDE_Msk        (0x00000001U  << CAN_MO_MOAMR_MIDE_Pos)\r
-\r
-/* CAN_MO_MODATALx  =  Message Object x Data Register Low*/\r
-#define   CAN_MO_MODATAL_DB0_Pos       (0U)\r
-#define   CAN_MO_MODATAL_DB0_Msk       (0x000000FFU  << CAN_MO_MODATAL_DB0_Pos)\r
-\r
-#define   CAN_MO_MODATAL_DB1_Pos       (8U)\r
-#define   CAN_MO_MODATAL_DB1_Msk       (0x000000FFU  << CAN_MO_MODATAL_DB1_Pos)\r
-\r
-#define   CAN_MO_MODATAL_DB2_Pos       (16U)\r
-#define   CAN_MO_MODATAL_DB2_Msk       (0x000000FFU  << CAN_MO_MODATAL_DB2_Pos)\r
-\r
-#define   CAN_MO_MODATAL_DB3_Pos       (24U)\r
-#define   CAN_MO_MODATAL_DB3_Msk       (0x000000FFU  << CAN_MO_MODATAL_DB3_Pos)\r
-\r
-/* CAN_MO_MODATAHx  =  Message Object x Data Register High*/\r
-#define   CAN_MO_MODATAH_DB4_Pos       (0U)\r
-#define   CAN_MO_MODATAH_DB4_Msk       (0x000000FFU  << CAN_MO_MODATAH_DB4_Pos)\r
-\r
-#define   CAN_MO_MODATAH_DB5_Pos       (8U)\r
-#define   CAN_MO_MODATAH_DB5_Msk       (0x000000FFU  << CAN_MO_MODATAH_DB5_Pos)\r
-\r
-#define   CAN_MO_MODATAH_DB6_Pos       (16U)\r
-#define   CAN_MO_MODATAH_DB6_Msk       (0x000000FFU  << CAN_MO_MODATAH_DB6_Pos)\r
-\r
-#define   CAN_MO_MODATAH_DB7_Pos       (24U)\r
-#define   CAN_MO_MODATAH_DB7_Msk       (0x000000FFU  << CAN_MO_MODATAH_DB7_Pos)\r
-\r
-/* CAN_MO_MOARx  =  Message Object x Arbitration Register*/\r
-#define   CAN_MO_MOAR_ID_Pos   (0U)\r
-#define   CAN_MO_MOAR_ID_Msk   (0x1FFFFFFFU  << CAN_MO_MOAR_ID_Pos)\r
-\r
-#define   CAN_MO_MOAR_IDE_Pos          (29U)\r
-#define   CAN_MO_MOAR_IDE_Msk          (0x00000001U  << CAN_MO_MOAR_IDE_Pos)\r
-\r
-#define   CAN_MO_MOAR_PRI_Pos          (30U)\r
-#define   CAN_MO_MOAR_PRI_Msk          (0x00000003U  << CAN_MO_MOAR_PRI_Pos)\r
-\r
-/* CAN_MO_MOCTRx  =  Message Object x Control Register*/\r
-#define   CAN_MO_MOCTR_RESRXPND_Pos    (0U)\r
-#define   CAN_MO_MOCTR_RESRXPND_Msk    (0x00000001U  << CAN_MO_MOCTR_RESRXPND_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETRXPND_Pos    (16U)\r
-#define   CAN_MO_MOCTR_SETRXPND_Msk    (0x00000001U  << CAN_MO_MOCTR_SETRXPND_Pos)\r
-\r
-#define   CAN_MO_MOCTR_RESTXPND_Pos    (1U)\r
-#define   CAN_MO_MOCTR_RESTXPND_Msk    (0x00000001U  << CAN_MO_MOCTR_RESTXPND_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETTXPND_Pos    (17U)\r
-#define   CAN_MO_MOCTR_SETTXPND_Msk    (0x00000001U  << CAN_MO_MOCTR_SETTXPND_Pos)\r
-\r
-#define   CAN_MO_MOCTR_RESRXUPD_Pos    (2U)\r
-#define   CAN_MO_MOCTR_RESRXUPD_Msk    (0x00000001U  << CAN_MO_MOCTR_RESRXUPD_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETRXUPD_Pos    (18U)\r
-#define   CAN_MO_MOCTR_SETRXUPD_Msk    (0x00000001U  << CAN_MO_MOCTR_SETRXUPD_Pos)\r
-\r
-#define   CAN_MO_MOCTR_RESNEWDAT_Pos   (3U)\r
-#define   CAN_MO_MOCTR_RESNEWDAT_Msk   (0x00000001U  << CAN_MO_MOCTR_RESNEWDAT_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETNEWDAT_Pos   (19U)\r
-#define   CAN_MO_MOCTR_SETNEWDAT_Msk   (0x00000001U  << CAN_MO_MOCTR_SETNEWDAT_Pos)\r
-\r
-#define   CAN_MO_MOCTR_RESMSGLST_Pos   (4U)\r
-#define   CAN_MO_MOCTR_RESMSGLST_Msk   (0x00000001U  << CAN_MO_MOCTR_RESMSGLST_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETMSGLST_Pos   (20U)\r
-#define   CAN_MO_MOCTR_SETMSGLST_Msk   (0x00000001U  << CAN_MO_MOCTR_SETMSGLST_Pos)\r
-\r
-#define   CAN_MO_MOCTR_RESMSGVAL_Pos   (5U)\r
-#define   CAN_MO_MOCTR_RESMSGVAL_Msk   (0x00000001U  << CAN_MO_MOCTR_RESMSGVAL_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETMSGVAL_Pos   (21U)\r
-#define   CAN_MO_MOCTR_SETMSGVAL_Msk   (0x00000001U  << CAN_MO_MOCTR_SETMSGVAL_Pos)\r
-\r
-#define   CAN_MO_MOCTR_RESRTSEL_Pos    (6U)\r
-#define   CAN_MO_MOCTR_RESRTSEL_Msk    (0x00000001U  << CAN_MO_MOCTR_RESRTSEL_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETRTSEL_Pos    (22U)\r
-#define   CAN_MO_MOCTR_SETRTSEL_Msk    (0x00000001U  << CAN_MO_MOCTR_SETRTSEL_Pos)\r
-\r
-#define   CAN_MO_MOCTR_RESRXEN_Pos     (7U)\r
-#define   CAN_MO_MOCTR_RESRXEN_Msk     (0x00000001U  << CAN_MO_MOCTR_RESRXEN_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETRXEN_Pos     (23U)\r
-#define   CAN_MO_MOCTR_SETRXEN_Msk     (0x00000001U  << CAN_MO_MOCTR_SETRXEN_Pos)\r
-\r
-#define   CAN_MO_MOCTR_RESTXRQ_Pos     (8U)\r
-#define   CAN_MO_MOCTR_RESTXRQ_Msk     (0x00000001U  << CAN_MO_MOCTR_RESTXRQ_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETTXRQ_Pos     (24U)\r
-#define   CAN_MO_MOCTR_SETTXRQ_Msk     (0x00000001U  << CAN_MO_MOCTR_SETTXRQ_Pos)\r
-\r
-#define   CAN_MO_MOCTR_RESTXEN0_Pos    (9U)\r
-#define   CAN_MO_MOCTR_RESTXEN0_Msk    (0x00000001U  << CAN_MO_MOCTR_RESTXEN0_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETTXEN0_Pos    (25U)\r
-#define   CAN_MO_MOCTR_SETTXEN0_Msk    (0x00000001U  << CAN_MO_MOCTR_SETTXEN0_Pos)\r
-\r
-#define   CAN_MO_MOCTR_RESTXEN1_Pos    (10U)\r
-#define   CAN_MO_MOCTR_RESTXEN1_Msk    (0x00000001U  << CAN_MO_MOCTR_RESTXEN1_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETTXEN1_Pos    (26U)\r
-#define   CAN_MO_MOCTR_SETTXEN1_Msk    (0x00000001U  << CAN_MO_MOCTR_SETTXEN1_Pos)\r
-\r
-#define   CAN_MO_MOCTR_RESDIR_Pos      (11U)\r
-#define   CAN_MO_MOCTR_RESDIR_Msk      (0x00000001U  << CAN_MO_MOCTR_RESDIR_Pos)\r
-\r
-#define   CAN_MO_MOCTR_SETDIR_Pos      (27U)\r
-#define   CAN_MO_MOCTR_SETDIR_Msk      (0x00000001U  << CAN_MO_MOCTR_SETDIR_Pos)\r
-\r
-/* CAN_MO_MOSTATx  =  Message Object x Status Register*/\r
-#define   CAN_MO_MOSTAT_RXPND_Pos      (0U)\r
-#define   CAN_MO_MOSTAT_RXPND_Msk      (0x00000001U  << CAN_MO_MOSTAT_RXPND_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_TXPND_Pos      (1U)\r
-#define   CAN_MO_MOSTAT_TXPND_Msk      (0x00000001U  << CAN_MO_MOSTAT_TXPND_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_RXUPD_Pos      (2U)\r
-#define   CAN_MO_MOSTAT_RXUPD_Msk      (0x00000001U  << CAN_MO_MOSTAT_RXUPD_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_NEWDAT_Pos     (3U)\r
-#define   CAN_MO_MOSTAT_NEWDAT_Msk     (0x00000001U  << CAN_MO_MOSTAT_NEWDAT_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_MSGLST_Pos     (4U)\r
-#define   CAN_MO_MOSTAT_MSGLST_Msk     (0x00000001U  << CAN_MO_MOSTAT_MSGLST_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_MSGVAL_Pos     (5U)\r
-#define   CAN_MO_MOSTAT_MSGVAL_Msk     (0x00000001U  << CAN_MO_MOSTAT_MSGVAL_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_RTSEL_Pos      (6U)\r
-#define   CAN_MO_MOSTAT_RTSEL_Msk      (0x00000001U  << CAN_MO_MOSTAT_RTSEL_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_RXEN_Pos       (7U)\r
-#define   CAN_MO_MOSTAT_RXEN_Msk       (0x00000001U  << CAN_MO_MOSTAT_RXEN_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_TXRQ_Pos       (8U)\r
-#define   CAN_MO_MOSTAT_TXRQ_Msk       (0x00000001U  << CAN_MO_MOSTAT_TXRQ_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_TXEN0_Pos      (9U)\r
-#define   CAN_MO_MOSTAT_TXEN0_Msk      (0x00000001U  << CAN_MO_MOSTAT_TXEN0_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_TXEN1_Pos      (10U)\r
-#define   CAN_MO_MOSTAT_TXEN1_Msk      (0x00000001U  << CAN_MO_MOSTAT_TXEN1_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_DIR_Pos        (11U)\r
-#define   CAN_MO_MOSTAT_DIR_Msk        (0x00000001U  << CAN_MO_MOSTAT_DIR_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_LIST_Pos       (12U)\r
-#define   CAN_MO_MOSTAT_LIST_Msk       (0x0000000FU  << CAN_MO_MOSTAT_LIST_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_PPREV_Pos      (16U)\r
-#define   CAN_MO_MOSTAT_PPREV_Msk      (0x000000FFU  << CAN_MO_MOSTAT_PPREV_Pos)\r
-\r
-#define   CAN_MO_MOSTAT_PNEXT_Pos      (24U)\r
-#define   CAN_MO_MOSTAT_PNEXT_Msk      (0x000000FFU  << CAN_MO_MOSTAT_PNEXT_Pos)\r
-\r
-\r
-\r
-/***   CCU4x Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* CCU4_GCTRL  =  Global Control Register*/\r
-#define   CCU4_GCTRL_PRBC_Pos          (0U)\r
-#define   CCU4_GCTRL_PRBC_Msk          (0x00000007U  << CCU4_GCTRL_PRBC_Pos)\r
-\r
-#define   CCU4_GCTRL_PCIS_Pos          (4U)\r
-#define   CCU4_GCTRL_PCIS_Msk          (0x00000003U  << CCU4_GCTRL_PCIS_Pos)\r
-\r
-#define   CCU4_GCTRL_SUSCFG_Pos        (8U)\r
-#define   CCU4_GCTRL_SUSCFG_Msk        (0x00000003U  << CCU4_GCTRL_SUSCFG_Pos)\r
-\r
-#define   CCU4_GCTRL_MSE0_Pos          (10U)\r
-#define   CCU4_GCTRL_MSE0_Msk          (0x00000001U  << CCU4_GCTRL_MSE0_Pos)\r
-\r
-#define   CCU4_GCTRL_MSE1_Pos          (11U)\r
-#define   CCU4_GCTRL_MSE1_Msk          (0x00000001U  << CCU4_GCTRL_MSE1_Pos)\r
-\r
-#define   CCU4_GCTRL_MSE2_Pos          (12U)\r
-#define   CCU4_GCTRL_MSE2_Msk          (0x00000001U  << CCU4_GCTRL_MSE2_Pos)\r
-\r
-#define   CCU4_GCTRL_MSE3_Pos          (13U)\r
-#define   CCU4_GCTRL_MSE3_Msk          (0x00000001U  << CCU4_GCTRL_MSE3_Pos)\r
-\r
-#define   CCU4_GCTRL_MSDE_Pos          (14U)\r
-#define   CCU4_GCTRL_MSDE_Msk          (0x00000003U  << CCU4_GCTRL_MSDE_Pos)\r
-\r
-/* CCU4_GSTAT  =  Global Status Register*/\r
-#define   CCU4_GSTAT_S0I_Pos   (0U)\r
-#define   CCU4_GSTAT_S0I_Msk   (0x00000001U  << CCU4_GSTAT_S0I_Pos)\r
-\r
-#define   CCU4_GSTAT_S1I_Pos   (1U)\r
-#define   CCU4_GSTAT_S1I_Msk   (0x00000001U  << CCU4_GSTAT_S1I_Pos)\r
-\r
-#define   CCU4_GSTAT_S2I_Pos   (2U)\r
-#define   CCU4_GSTAT_S2I_Msk   (0x00000001U  << CCU4_GSTAT_S2I_Pos)\r
-\r
-#define   CCU4_GSTAT_S3I_Pos   (3U)\r
-#define   CCU4_GSTAT_S3I_Msk   (0x00000001U  << CCU4_GSTAT_S3I_Pos)\r
-\r
-#define   CCU4_GSTAT_PRB_Pos   (8U)\r
-#define   CCU4_GSTAT_PRB_Msk   (0x00000001U  << CCU4_GSTAT_PRB_Pos)\r
-\r
-/* CCU4_GIDLS  =  Global Idle Set*/\r
-#define   CCU4_GIDLS_SS0I_Pos          (0U)\r
-#define   CCU4_GIDLS_SS0I_Msk          (0x00000001U  << CCU4_GIDLS_SS0I_Pos)\r
-\r
-#define   CCU4_GIDLS_SS1I_Pos          (1U)\r
-#define   CCU4_GIDLS_SS1I_Msk          (0x00000001U  << CCU4_GIDLS_SS1I_Pos)\r
-\r
-#define   CCU4_GIDLS_SS2I_Pos          (2U)\r
-#define   CCU4_GIDLS_SS2I_Msk          (0x00000001U  << CCU4_GIDLS_SS2I_Pos)\r
-\r
-#define   CCU4_GIDLS_SS3I_Pos          (3U)\r
-#define   CCU4_GIDLS_SS3I_Msk          (0x00000001U  << CCU4_GIDLS_SS3I_Pos)\r
-\r
-#define   CCU4_GIDLS_CPRB_Pos          (8U)\r
-#define   CCU4_GIDLS_CPRB_Msk          (0x00000001U  << CCU4_GIDLS_CPRB_Pos)\r
-\r
-#define   CCU4_GIDLS_PSIC_Pos          (9U)\r
-#define   CCU4_GIDLS_PSIC_Msk          (0x00000001U  << CCU4_GIDLS_PSIC_Pos)\r
-\r
-/* CCU4_GIDLC  =  Global Idle Clear*/\r
-#define   CCU4_GIDLC_CS0I_Pos          (0U)\r
-#define   CCU4_GIDLC_CS0I_Msk          (0x00000001U  << CCU4_GIDLC_CS0I_Pos)\r
-\r
-#define   CCU4_GIDLC_CS1I_Pos          (1U)\r
-#define   CCU4_GIDLC_CS1I_Msk          (0x00000001U  << CCU4_GIDLC_CS1I_Pos)\r
-\r
-#define   CCU4_GIDLC_CS2I_Pos          (2U)\r
-#define   CCU4_GIDLC_CS2I_Msk          (0x00000001U  << CCU4_GIDLC_CS2I_Pos)\r
-\r
-#define   CCU4_GIDLC_CS3I_Pos          (3U)\r
-#define   CCU4_GIDLC_CS3I_Msk          (0x00000001U  << CCU4_GIDLC_CS3I_Pos)\r
-\r
-#define   CCU4_GIDLC_SPRB_Pos          (8U)\r
-#define   CCU4_GIDLC_SPRB_Msk          (0x00000001U  << CCU4_GIDLC_SPRB_Pos)\r
-\r
-/* CCU4_GCSS  =  Global Channel Set*/\r
-#define   CCU4_GCSS_S0SE_Pos   (0U)\r
-#define   CCU4_GCSS_S0SE_Msk   (0x00000001U  << CCU4_GCSS_S0SE_Pos)\r
-\r
-#define   CCU4_GCSS_S0DSE_Pos          (1U)\r
-#define   CCU4_GCSS_S0DSE_Msk          (0x00000001U  << CCU4_GCSS_S0DSE_Pos)\r
-\r
-#define   CCU4_GCSS_S0PSE_Pos          (2U)\r
-#define   CCU4_GCSS_S0PSE_Msk          (0x00000001U  << CCU4_GCSS_S0PSE_Pos)\r
-\r
-#define   CCU4_GCSS_S1SE_Pos   (4U)\r
-#define   CCU4_GCSS_S1SE_Msk   (0x00000001U  << CCU4_GCSS_S1SE_Pos)\r
-\r
-#define   CCU4_GCSS_S1DSE_Pos          (5U)\r
-#define   CCU4_GCSS_S1DSE_Msk          (0x00000001U  << CCU4_GCSS_S1DSE_Pos)\r
-\r
-#define   CCU4_GCSS_S1PSE_Pos          (6U)\r
-#define   CCU4_GCSS_S1PSE_Msk          (0x00000001U  << CCU4_GCSS_S1PSE_Pos)\r
-\r
-#define   CCU4_GCSS_S2SE_Pos   (8U)\r
-#define   CCU4_GCSS_S2SE_Msk   (0x00000001U  << CCU4_GCSS_S2SE_Pos)\r
-\r
-#define   CCU4_GCSS_S2DSE_Pos          (9U)\r
-#define   CCU4_GCSS_S2DSE_Msk          (0x00000001U  << CCU4_GCSS_S2DSE_Pos)\r
-\r
-#define   CCU4_GCSS_S2PSE_Pos          (10U)\r
-#define   CCU4_GCSS_S2PSE_Msk          (0x00000001U  << CCU4_GCSS_S2PSE_Pos)\r
-\r
-#define   CCU4_GCSS_S3SE_Pos   (12U)\r
-#define   CCU4_GCSS_S3SE_Msk   (0x00000001U  << CCU4_GCSS_S3SE_Pos)\r
-\r
-#define   CCU4_GCSS_S3DSE_Pos          (13U)\r
-#define   CCU4_GCSS_S3DSE_Msk          (0x00000001U  << CCU4_GCSS_S3DSE_Pos)\r
-\r
-#define   CCU4_GCSS_S3PSE_Pos          (14U)\r
-#define   CCU4_GCSS_S3PSE_Msk          (0x00000001U  << CCU4_GCSS_S3PSE_Pos)\r
-\r
-#define   CCU4_GCSS_S0STS_Pos          (16U)\r
-#define   CCU4_GCSS_S0STS_Msk          (0x00000001U  << CCU4_GCSS_S0STS_Pos)\r
-\r
-#define   CCU4_GCSS_S1STS_Pos          (17U)\r
-#define   CCU4_GCSS_S1STS_Msk          (0x00000001U  << CCU4_GCSS_S1STS_Pos)\r
-\r
-#define   CCU4_GCSS_S2STS_Pos          (18U)\r
-#define   CCU4_GCSS_S2STS_Msk          (0x00000001U  << CCU4_GCSS_S2STS_Pos)\r
-\r
-#define   CCU4_GCSS_S3STS_Pos          (19U)\r
-#define   CCU4_GCSS_S3STS_Msk          (0x00000001U  << CCU4_GCSS_S3STS_Pos)\r
-\r
-/* CCU4_GCSC  =  Global Channel Clear*/\r
-#define   CCU4_GCSC_S0SC_Pos   (0U)\r
-#define   CCU4_GCSC_S0SC_Msk   (0x00000001U  << CCU4_GCSC_S0SC_Pos)\r
-\r
-#define   CCU4_GCSC_S0DSC_Pos          (1U)\r
-#define   CCU4_GCSC_S0DSC_Msk          (0x00000001U  << CCU4_GCSC_S0DSC_Pos)\r
-\r
-#define   CCU4_GCSC_S0PSC_Pos          (2U)\r
-#define   CCU4_GCSC_S0PSC_Msk          (0x00000001U  << CCU4_GCSC_S0PSC_Pos)\r
-\r
-#define   CCU4_GCSC_S1SC_Pos   (4U)\r
-#define   CCU4_GCSC_S1SC_Msk   (0x00000001U  << CCU4_GCSC_S1SC_Pos)\r
-\r
-#define   CCU4_GCSC_S1DSC_Pos          (5U)\r
-#define   CCU4_GCSC_S1DSC_Msk          (0x00000001U  << CCU4_GCSC_S1DSC_Pos)\r
-\r
-#define   CCU4_GCSC_S1PSC_Pos          (6U)\r
-#define   CCU4_GCSC_S1PSC_Msk          (0x00000001U  << CCU4_GCSC_S1PSC_Pos)\r
-\r
-#define   CCU4_GCSC_S2SC_Pos   (8U)\r
-#define   CCU4_GCSC_S2SC_Msk   (0x00000001U  << CCU4_GCSC_S2SC_Pos)\r
-\r
-#define   CCU4_GCSC_S2DSC_Pos          (9U)\r
-#define   CCU4_GCSC_S2DSC_Msk          (0x00000001U  << CCU4_GCSC_S2DSC_Pos)\r
-\r
-#define   CCU4_GCSC_S2PSC_Pos          (10U)\r
-#define   CCU4_GCSC_S2PSC_Msk          (0x00000001U  << CCU4_GCSC_S2PSC_Pos)\r
-\r
-#define   CCU4_GCSC_S3SC_Pos   (12U)\r
-#define   CCU4_GCSC_S3SC_Msk   (0x00000001U  << CCU4_GCSC_S3SC_Pos)\r
-\r
-#define   CCU4_GCSC_S3DSC_Pos          (13U)\r
-#define   CCU4_GCSC_S3DSC_Msk          (0x00000001U  << CCU4_GCSC_S3DSC_Pos)\r
-\r
-#define   CCU4_GCSC_S3PSC_Pos          (14U)\r
-#define   CCU4_GCSC_S3PSC_Msk          (0x00000001U  << CCU4_GCSC_S3PSC_Pos)\r
-\r
-#define   CCU4_GCSC_S0STC_Pos          (16U)\r
-#define   CCU4_GCSC_S0STC_Msk          (0x00000001U  << CCU4_GCSC_S0STC_Pos)\r
-\r
-#define   CCU4_GCSC_S1STC_Pos          (17U)\r
-#define   CCU4_GCSC_S1STC_Msk          (0x00000001U  << CCU4_GCSC_S1STC_Pos)\r
-\r
-#define   CCU4_GCSC_S2STC_Pos          (18U)\r
-#define   CCU4_GCSC_S2STC_Msk          (0x00000001U  << CCU4_GCSC_S2STC_Pos)\r
-\r
-#define   CCU4_GCSC_S3STC_Pos          (19U)\r
-#define   CCU4_GCSC_S3STC_Msk          (0x00000001U  << CCU4_GCSC_S3STC_Pos)\r
-\r
-/* CCU4_GCST  =  Global Channel Status*/\r
-#define   CCU4_GCST_S0SS_Pos   (0U)\r
-#define   CCU4_GCST_S0SS_Msk   (0x00000001U  << CCU4_GCST_S0SS_Pos)\r
-\r
-#define   CCU4_GCST_S0DSS_Pos          (1U)\r
-#define   CCU4_GCST_S0DSS_Msk          (0x00000001U  << CCU4_GCST_S0DSS_Pos)\r
-\r
-#define   CCU4_GCST_S0PSS_Pos          (2U)\r
-#define   CCU4_GCST_S0PSS_Msk          (0x00000001U  << CCU4_GCST_S0PSS_Pos)\r
-\r
-#define   CCU4_GCST_S1SS_Pos   (4U)\r
-#define   CCU4_GCST_S1SS_Msk   (0x00000001U  << CCU4_GCST_S1SS_Pos)\r
-\r
-#define   CCU4_GCST_S1DSS_Pos          (5U)\r
-#define   CCU4_GCST_S1DSS_Msk          (0x00000001U  << CCU4_GCST_S1DSS_Pos)\r
-\r
-#define   CCU4_GCST_S1PSS_Pos          (6U)\r
-#define   CCU4_GCST_S1PSS_Msk          (0x00000001U  << CCU4_GCST_S1PSS_Pos)\r
-\r
-#define   CCU4_GCST_S2SS_Pos   (8U)\r
-#define   CCU4_GCST_S2SS_Msk   (0x00000001U  << CCU4_GCST_S2SS_Pos)\r
-\r
-#define   CCU4_GCST_S2DSS_Pos          (9U)\r
-#define   CCU4_GCST_S2DSS_Msk          (0x00000001U  << CCU4_GCST_S2DSS_Pos)\r
-\r
-#define   CCU4_GCST_S2PSS_Pos          (10U)\r
-#define   CCU4_GCST_S2PSS_Msk          (0x00000001U  << CCU4_GCST_S2PSS_Pos)\r
-\r
-#define   CCU4_GCST_S3SS_Pos   (12U)\r
-#define   CCU4_GCST_S3SS_Msk   (0x00000001U  << CCU4_GCST_S3SS_Pos)\r
-\r
-#define   CCU4_GCST_S3DSS_Pos          (13U)\r
-#define   CCU4_GCST_S3DSS_Msk          (0x00000001U  << CCU4_GCST_S3DSS_Pos)\r
-\r
-#define   CCU4_GCST_S3PSS_Pos          (14U)\r
-#define   CCU4_GCST_S3PSS_Msk          (0x00000001U  << CCU4_GCST_S3PSS_Pos)\r
-\r
-#define   CCU4_GCST_CC40ST_Pos         (16U)\r
-#define   CCU4_GCST_CC40ST_Msk         (0x00000001U  << CCU4_GCST_CC40ST_Pos)\r
-\r
-#define   CCU4_GCST_CC41ST_Pos         (17U)\r
-#define   CCU4_GCST_CC41ST_Msk         (0x00000001U  << CCU4_GCST_CC41ST_Pos)\r
-\r
-#define   CCU4_GCST_CC42ST_Pos         (18U)\r
-#define   CCU4_GCST_CC42ST_Msk         (0x00000001U  << CCU4_GCST_CC42ST_Pos)\r
-\r
-#define   CCU4_GCST_CC43ST_Pos         (19U)\r
-#define   CCU4_GCST_CC43ST_Msk         (0x00000001U  << CCU4_GCST_CC43ST_Pos)\r
-\r
-/* CCU4_ECRD  =  Extended Capture Mode Read*/\r
-#define   CCU4_ECRD_CAPV_Pos   (0U)\r
-#define   CCU4_ECRD_CAPV_Msk   (0x0000FFFFU  << CCU4_ECRD_CAPV_Pos)\r
-\r
-#define   CCU4_ECRD_FPCV_Pos   (16U)\r
-#define   CCU4_ECRD_FPCV_Msk   (0x0000000FU  << CCU4_ECRD_FPCV_Pos)\r
-\r
-#define   CCU4_ECRD_SPTR_Pos   (20U)\r
-#define   CCU4_ECRD_SPTR_Msk   (0x00000003U  << CCU4_ECRD_SPTR_Pos)\r
-\r
-#define   CCU4_ECRD_VPTR_Pos   (22U)\r
-#define   CCU4_ECRD_VPTR_Msk   (0x00000003U  << CCU4_ECRD_VPTR_Pos)\r
-\r
-#define   CCU4_ECRD_FFL_Pos    (24U)\r
-#define   CCU4_ECRD_FFL_Msk    (0x00000001U  << CCU4_ECRD_FFL_Pos)\r
-\r
-/* CCU4_MIDR  =  Module Identification*/\r
-#define   CCU4_MIDR_MODR_Pos   (0U)\r
-#define   CCU4_MIDR_MODR_Msk   (0x000000FFU  << CCU4_MIDR_MODR_Pos)\r
-\r
-#define   CCU4_MIDR_MODT_Pos   (8U)\r
-#define   CCU4_MIDR_MODT_Msk   (0x000000FFU  << CCU4_MIDR_MODT_Pos)\r
-\r
-#define   CCU4_MIDR_MODN_Pos   (16U)\r
-#define   CCU4_MIDR_MODN_Msk   (0x0000FFFFU  << CCU4_MIDR_MODN_Pos)\r
-\r
-/* CCU4_CC4_INS  =  Input Selector Configuration*/\r
-#define   CCU4_CC4_INS_EV0IS_Pos       (0U)\r
-#define   CCU4_CC4_INS_EV0IS_Msk       (0x0000000FU  << CCU4_CC4_INS_EV0IS_Pos)\r
-\r
-#define   CCU4_CC4_INS_EV1IS_Pos       (4U)\r
-#define   CCU4_CC4_INS_EV1IS_Msk       (0x0000000FU  << CCU4_CC4_INS_EV1IS_Pos)\r
-\r
-#define   CCU4_CC4_INS_EV2S_Pos        (8U)\r
-#define   CCU4_CC4_INS_EV2S_Msk        (0x0000000FU  << CCU4_CC4_INS_EV2S_Pos)\r
-\r
-#define   CCU4_CC4_INS_EV0EM_Pos       (16U)\r
-#define   CCU4_CC4_INS_EV0EM_Msk       (0x00000003U  << CCU4_CC4_INS_EV0EM_Pos)\r
-\r
-#define   CCU4_CC4_INS_EV1EM_Pos       (18U)\r
-#define   CCU4_CC4_INS_EV1EM_Msk       (0x00000003U  << CCU4_CC4_INS_EV1EM_Pos)\r
-\r
-#define   CCU4_CC4_INS_EV2EM_Pos       (20U)\r
-#define   CCU4_CC4_INS_EV2EM_Msk       (0x00000003U  << CCU4_CC4_INS_EV2EM_Pos)\r
-\r
-#define   CCU4_CC4_INS_EV0LM_Pos       (22U)\r
-#define   CCU4_CC4_INS_EV0LM_Msk       (0x00000001U  << CCU4_CC4_INS_EV0LM_Pos)\r
-\r
-#define   CCU4_CC4_INS_EV1LM_Pos       (23U)\r
-#define   CCU4_CC4_INS_EV1LM_Msk       (0x00000001U  << CCU4_CC4_INS_EV1LM_Pos)\r
-\r
-#define   CCU4_CC4_INS_EV2LM_Pos       (24U)\r
-#define   CCU4_CC4_INS_EV2LM_Msk       (0x00000001U  << CCU4_CC4_INS_EV2LM_Pos)\r
-\r
-#define   CCU4_CC4_INS_LPF0M_Pos       (25U)\r
-#define   CCU4_CC4_INS_LPF0M_Msk       (0x00000003U  << CCU4_CC4_INS_LPF0M_Pos)\r
-\r
-#define   CCU4_CC4_INS_LPF1M_Pos       (27U)\r
-#define   CCU4_CC4_INS_LPF1M_Msk       (0x00000003U  << CCU4_CC4_INS_LPF1M_Pos)\r
-\r
-#define   CCU4_CC4_INS_LPF2M_Pos       (29U)\r
-#define   CCU4_CC4_INS_LPF2M_Msk       (0x00000003U  << CCU4_CC4_INS_LPF2M_Pos)\r
-\r
-/* CCU4_CC4_CMC  =  Connection Matrix Control*/\r
-#define   CCU4_CC4_CMC_STRTS_Pos       (0U)\r
-#define   CCU4_CC4_CMC_STRTS_Msk       (0x00000003U  << CCU4_CC4_CMC_STRTS_Pos)\r
-\r
-#define   CCU4_CC4_CMC_ENDS_Pos        (2U)\r
-#define   CCU4_CC4_CMC_ENDS_Msk        (0x00000003U  << CCU4_CC4_CMC_ENDS_Pos)\r
-\r
-#define   CCU4_CC4_CMC_CAP0S_Pos       (4U)\r
-#define   CCU4_CC4_CMC_CAP0S_Msk       (0x00000003U  << CCU4_CC4_CMC_CAP0S_Pos)\r
-\r
-#define   CCU4_CC4_CMC_CAP1S_Pos       (6U)\r
-#define   CCU4_CC4_CMC_CAP1S_Msk       (0x00000003U  << CCU4_CC4_CMC_CAP1S_Pos)\r
-\r
-#define   CCU4_CC4_CMC_GATES_Pos       (8U)\r
-#define   CCU4_CC4_CMC_GATES_Msk       (0x00000003U  << CCU4_CC4_CMC_GATES_Pos)\r
-\r
-#define   CCU4_CC4_CMC_UDS_Pos         (10U)\r
-#define   CCU4_CC4_CMC_UDS_Msk         (0x00000003U  << CCU4_CC4_CMC_UDS_Pos)\r
-\r
-#define   CCU4_CC4_CMC_LDS_Pos         (12U)\r
-#define   CCU4_CC4_CMC_LDS_Msk         (0x00000003U  << CCU4_CC4_CMC_LDS_Pos)\r
-\r
-#define   CCU4_CC4_CMC_CNTS_Pos        (14U)\r
-#define   CCU4_CC4_CMC_CNTS_Msk        (0x00000003U  << CCU4_CC4_CMC_CNTS_Pos)\r
-\r
-#define   CCU4_CC4_CMC_OFS_Pos         (16U)\r
-#define   CCU4_CC4_CMC_OFS_Msk         (0x00000001U  << CCU4_CC4_CMC_OFS_Pos)\r
-\r
-#define   CCU4_CC4_CMC_TS_Pos          (17U)\r
-#define   CCU4_CC4_CMC_TS_Msk          (0x00000001U  << CCU4_CC4_CMC_TS_Pos)\r
-\r
-#define   CCU4_CC4_CMC_MOS_Pos         (18U)\r
-#define   CCU4_CC4_CMC_MOS_Msk         (0x00000003U  << CCU4_CC4_CMC_MOS_Pos)\r
-\r
-#define   CCU4_CC4_CMC_TCE_Pos         (20U)\r
-#define   CCU4_CC4_CMC_TCE_Msk         (0x00000001U  << CCU4_CC4_CMC_TCE_Pos)\r
-\r
-/* CCU4_CC4_TCST  =  Slice Timer Status*/\r
-#define   CCU4_CC4_TCST_TRB_Pos        (0U)\r
-#define   CCU4_CC4_TCST_TRB_Msk        (0x00000001U  << CCU4_CC4_TCST_TRB_Pos)\r
-\r
-#define   CCU4_CC4_TCST_CDIR_Pos       (1U)\r
-#define   CCU4_CC4_TCST_CDIR_Msk       (0x00000001U  << CCU4_CC4_TCST_CDIR_Pos)\r
-\r
-/* CCU4_CC4_TCSET  =  Slice Timer Run Set*/\r
-#define   CCU4_CC4_TCSET_TRBS_Pos      (0U)\r
-#define   CCU4_CC4_TCSET_TRBS_Msk      (0x00000001U  << CCU4_CC4_TCSET_TRBS_Pos)\r
-\r
-/* CCU4_CC4_TCCLR  =  Slice Timer Clear*/\r
-#define   CCU4_CC4_TCCLR_TRBC_Pos      (0U)\r
-#define   CCU4_CC4_TCCLR_TRBC_Msk      (0x00000001U  << CCU4_CC4_TCCLR_TRBC_Pos)\r
-\r
-#define   CCU4_CC4_TCCLR_TCC_Pos       (1U)\r
-#define   CCU4_CC4_TCCLR_TCC_Msk       (0x00000001U  << CCU4_CC4_TCCLR_TCC_Pos)\r
-\r
-#define   CCU4_CC4_TCCLR_DITC_Pos      (2U)\r
-#define   CCU4_CC4_TCCLR_DITC_Msk      (0x00000001U  << CCU4_CC4_TCCLR_DITC_Pos)\r
-\r
-/* CCU4_CC4_TC  =  Slice Timer Control*/\r
-#define   CCU4_CC4_TC_TCM_Pos          (0U)\r
-#define   CCU4_CC4_TC_TCM_Msk          (0x00000001U  << CCU4_CC4_TC_TCM_Pos)\r
-\r
-#define   CCU4_CC4_TC_TSSM_Pos         (1U)\r
-#define   CCU4_CC4_TC_TSSM_Msk         (0x00000001U  << CCU4_CC4_TC_TSSM_Pos)\r
-\r
-#define   CCU4_CC4_TC_CLST_Pos         (2U)\r
-#define   CCU4_CC4_TC_CLST_Msk         (0x00000001U  << CCU4_CC4_TC_CLST_Pos)\r
-\r
-#define   CCU4_CC4_TC_CMOD_Pos         (3U)\r
-#define   CCU4_CC4_TC_CMOD_Msk         (0x00000001U  << CCU4_CC4_TC_CMOD_Pos)\r
-\r
-#define   CCU4_CC4_TC_ECM_Pos          (4U)\r
-#define   CCU4_CC4_TC_ECM_Msk          (0x00000001U  << CCU4_CC4_TC_ECM_Pos)\r
-\r
-#define   CCU4_CC4_TC_CAPC_Pos         (5U)\r
-#define   CCU4_CC4_TC_CAPC_Msk         (0x00000003U  << CCU4_CC4_TC_CAPC_Pos)\r
-\r
-#define   CCU4_CC4_TC_ENDM_Pos         (8U)\r
-#define   CCU4_CC4_TC_ENDM_Msk         (0x00000003U  << CCU4_CC4_TC_ENDM_Pos)\r
-\r
-#define   CCU4_CC4_TC_STRM_Pos         (10U)\r
-#define   CCU4_CC4_TC_STRM_Msk         (0x00000001U  << CCU4_CC4_TC_STRM_Pos)\r
-\r
-#define   CCU4_CC4_TC_SCE_Pos          (11U)\r
-#define   CCU4_CC4_TC_SCE_Msk          (0x00000001U  << CCU4_CC4_TC_SCE_Pos)\r
-\r
-#define   CCU4_CC4_TC_CCS_Pos          (12U)\r
-#define   CCU4_CC4_TC_CCS_Msk          (0x00000001U  << CCU4_CC4_TC_CCS_Pos)\r
-\r
-#define   CCU4_CC4_TC_DITHE_Pos        (13U)\r
-#define   CCU4_CC4_TC_DITHE_Msk        (0x00000003U  << CCU4_CC4_TC_DITHE_Pos)\r
-\r
-#define   CCU4_CC4_TC_DIM_Pos          (15U)\r
-#define   CCU4_CC4_TC_DIM_Msk          (0x00000001U  << CCU4_CC4_TC_DIM_Pos)\r
-\r
-#define   CCU4_CC4_TC_FPE_Pos          (16U)\r
-#define   CCU4_CC4_TC_FPE_Msk          (0x00000001U  << CCU4_CC4_TC_FPE_Pos)\r
-\r
-#define   CCU4_CC4_TC_TRAPE_Pos        (17U)\r
-#define   CCU4_CC4_TC_TRAPE_Msk        (0x00000001U  << CCU4_CC4_TC_TRAPE_Pos)\r
-\r
-#define   CCU4_CC4_TC_TRPSE_Pos        (21U)\r
-#define   CCU4_CC4_TC_TRPSE_Msk        (0x00000001U  << CCU4_CC4_TC_TRPSE_Pos)\r
-\r
-#define   CCU4_CC4_TC_TRPSW_Pos        (22U)\r
-#define   CCU4_CC4_TC_TRPSW_Msk        (0x00000001U  << CCU4_CC4_TC_TRPSW_Pos)\r
-\r
-#define   CCU4_CC4_TC_EMS_Pos          (23U)\r
-#define   CCU4_CC4_TC_EMS_Msk          (0x00000001U  << CCU4_CC4_TC_EMS_Pos)\r
-\r
-#define   CCU4_CC4_TC_EMT_Pos          (24U)\r
-#define   CCU4_CC4_TC_EMT_Msk          (0x00000001U  << CCU4_CC4_TC_EMT_Pos)\r
-\r
-#define   CCU4_CC4_TC_MCME_Pos         (25U)\r
-#define   CCU4_CC4_TC_MCME_Msk         (0x00000001U  << CCU4_CC4_TC_MCME_Pos)\r
-\r
-/* CCU4_CC4_PSL  =  Passive Level Config*/\r
-#define   CCU4_CC4_PSL_PSL_Pos         (0U)\r
-#define   CCU4_CC4_PSL_PSL_Msk         (0x00000001U  << CCU4_CC4_PSL_PSL_Pos)\r
-\r
-/* CCU4_CC4_DIT  =  Dither Config*/\r
-#define   CCU4_CC4_DIT_DCV_Pos         (0U)\r
-#define   CCU4_CC4_DIT_DCV_Msk         (0x0000000FU  << CCU4_CC4_DIT_DCV_Pos)\r
-\r
-#define   CCU4_CC4_DIT_DCNT_Pos        (8U)\r
-#define   CCU4_CC4_DIT_DCNT_Msk        (0x0000000FU  << CCU4_CC4_DIT_DCNT_Pos)\r
-\r
-/* CCU4_CC4_DITS  =  Dither Shadow Register*/\r
-#define   CCU4_CC4_DITS_DCVS_Pos       (0U)\r
-#define   CCU4_CC4_DITS_DCVS_Msk       (0x0000000FU  << CCU4_CC4_DITS_DCVS_Pos)\r
-\r
-/* CCU4_CC4_PSC  =  Prescaler Control*/\r
-#define   CCU4_CC4_PSC_PSIV_Pos        (0U)\r
-#define   CCU4_CC4_PSC_PSIV_Msk        (0x0000000FU  << CCU4_CC4_PSC_PSIV_Pos)\r
-\r
-/* CCU4_CC4_FPC  =  Floating Prescaler Control*/\r
-#define   CCU4_CC4_FPC_PCMP_Pos        (0U)\r
-#define   CCU4_CC4_FPC_PCMP_Msk        (0x0000000FU  << CCU4_CC4_FPC_PCMP_Pos)\r
-\r
-#define   CCU4_CC4_FPC_PVAL_Pos        (8U)\r
-#define   CCU4_CC4_FPC_PVAL_Msk        (0x0000000FU  << CCU4_CC4_FPC_PVAL_Pos)\r
-\r
-/* CCU4_CC4_FPCS  =  Floating Prescaler Shadow*/\r
-#define   CCU4_CC4_FPCS_PCMP_Pos       (0U)\r
-#define   CCU4_CC4_FPCS_PCMP_Msk       (0x0000000FU  << CCU4_CC4_FPCS_PCMP_Pos)\r
-\r
-/* CCU4_CC4_PR  =  Timer Period Value*/\r
-#define   CCU4_CC4_PR_PR_Pos   (0U)\r
-#define   CCU4_CC4_PR_PR_Msk   (0x0000FFFFU  << CCU4_CC4_PR_PR_Pos)\r
-\r
-/* CCU4_CC4_PRS  =  Timer Shadow Period Value*/\r
-#define   CCU4_CC4_PRS_PRS_Pos         (0U)\r
-#define   CCU4_CC4_PRS_PRS_Msk         (0x0000FFFFU  << CCU4_CC4_PRS_PRS_Pos)\r
-\r
-/* CCU4_CC4_CR  =  Timer Compare Value*/\r
-#define   CCU4_CC4_CR_CR_Pos   (0U)\r
-#define   CCU4_CC4_CR_CR_Msk   (0x0000FFFFU  << CCU4_CC4_CR_CR_Pos)\r
-\r
-/* CCU4_CC4_CRS  =  Timer Shadow Compare Value*/\r
-#define   CCU4_CC4_CRS_CRS_Pos         (0U)\r
-#define   CCU4_CC4_CRS_CRS_Msk         (0x0000FFFFU  << CCU4_CC4_CRS_CRS_Pos)\r
-\r
-/* CCU4_CC4_TIMER  =  Timer Value*/\r
-#define   CCU4_CC4_TIMER_TVAL_Pos      (0U)\r
-#define   CCU4_CC4_TIMER_TVAL_Msk      (0x0000FFFFU  << CCU4_CC4_TIMER_TVAL_Pos)\r
-\r
-/* CCU4_CC4_C0V  =  Capture Register 0*/\r
-#define   CCU4_CC4_CV_CAPTV_Pos        (0U)\r
-#define   CCU4_CC4_CV_CAPTV_Msk        (0x0000FFFFU  << CCU4_CC4_CV_CAPTV_Pos)\r
-\r
-#define   CCU4_CC4_CV_FPCV_Pos         (16U)\r
-#define   CCU4_CC4_CV_FPCV_Msk         (0x0000000FU  << CCU4_CC4_CV_FPCV_Pos)\r
-\r
-#define   CCU4_CC4_CV_FFL_Pos          (20U)\r
-#define   CCU4_CC4_CV_FFL_Msk          (0x00000001U  << CCU4_CC4_CV_FFL_Pos)\r
-\r
-/* CCU4_CC4_INTS  =  Interrupt Status*/\r
-#define   CCU4_CC4_INTS_PMUS_Pos       (0U)\r
-#define   CCU4_CC4_INTS_PMUS_Msk       (0x00000001U  << CCU4_CC4_INTS_PMUS_Pos)\r
-\r
-#define   CCU4_CC4_INTS_OMDS_Pos       (1U)\r
-#define   CCU4_CC4_INTS_OMDS_Msk       (0x00000001U  << CCU4_CC4_INTS_OMDS_Pos)\r
-\r
-#define   CCU4_CC4_INTS_CMUS_Pos       (2U)\r
-#define   CCU4_CC4_INTS_CMUS_Msk       (0x00000001U  << CCU4_CC4_INTS_CMUS_Pos)\r
-\r
-#define   CCU4_CC4_INTS_CMDS_Pos       (3U)\r
-#define   CCU4_CC4_INTS_CMDS_Msk       (0x00000001U  << CCU4_CC4_INTS_CMDS_Pos)\r
-\r
-#define   CCU4_CC4_INTS_E0AS_Pos       (8U)\r
-#define   CCU4_CC4_INTS_E0AS_Msk       (0x00000001U  << CCU4_CC4_INTS_E0AS_Pos)\r
-\r
-#define   CCU4_CC4_INTS_E1AS_Pos       (9U)\r
-#define   CCU4_CC4_INTS_E1AS_Msk       (0x00000001U  << CCU4_CC4_INTS_E1AS_Pos)\r
-\r
-#define   CCU4_CC4_INTS_E2AS_Pos       (10U)\r
-#define   CCU4_CC4_INTS_E2AS_Msk       (0x00000001U  << CCU4_CC4_INTS_E2AS_Pos)\r
-\r
-#define   CCU4_CC4_INTS_TRPF_Pos       (11U)\r
-#define   CCU4_CC4_INTS_TRPF_Msk       (0x00000001U  << CCU4_CC4_INTS_TRPF_Pos)\r
-\r
-/* CCU4_CC4_INTE  =  Interrupt Enable Control*/\r
-#define   CCU4_CC4_INTE_PME_Pos        (0U)\r
-#define   CCU4_CC4_INTE_PME_Msk        (0x00000001U  << CCU4_CC4_INTE_PME_Pos)\r
-\r
-#define   CCU4_CC4_INTE_OME_Pos        (1U)\r
-#define   CCU4_CC4_INTE_OME_Msk        (0x00000001U  << CCU4_CC4_INTE_OME_Pos)\r
-\r
-#define   CCU4_CC4_INTE_CMUE_Pos       (2U)\r
-#define   CCU4_CC4_INTE_CMUE_Msk       (0x00000001U  << CCU4_CC4_INTE_CMUE_Pos)\r
-\r
-#define   CCU4_CC4_INTE_CMDE_Pos       (3U)\r
-#define   CCU4_CC4_INTE_CMDE_Msk       (0x00000001U  << CCU4_CC4_INTE_CMDE_Pos)\r
-\r
-#define   CCU4_CC4_INTE_E0AE_Pos       (8U)\r
-#define   CCU4_CC4_INTE_E0AE_Msk       (0x00000001U  << CCU4_CC4_INTE_E0AE_Pos)\r
-\r
-#define   CCU4_CC4_INTE_E1AE_Pos       (9U)\r
-#define   CCU4_CC4_INTE_E1AE_Msk       (0x00000001U  << CCU4_CC4_INTE_E1AE_Pos)\r
-\r
-#define   CCU4_CC4_INTE_E2AE_Pos       (10U)\r
-#define   CCU4_CC4_INTE_E2AE_Msk       (0x00000001U  << CCU4_CC4_INTE_E2AE_Pos)\r
-\r
-/* CCU4_CC4_SRS  =  Service Request Selector*/\r
-#define   CCU4_CC4_SRS_POSR_Pos        (0U)\r
-#define   CCU4_CC4_SRS_POSR_Msk        (0x00000003U  << CCU4_CC4_SRS_POSR_Pos)\r
-\r
-#define   CCU4_CC4_SRS_CMSR_Pos        (2U)\r
-#define   CCU4_CC4_SRS_CMSR_Msk        (0x00000003U  << CCU4_CC4_SRS_CMSR_Pos)\r
-\r
-#define   CCU4_CC4_SRS_E0SR_Pos        (8U)\r
-#define   CCU4_CC4_SRS_E0SR_Msk        (0x00000003U  << CCU4_CC4_SRS_E0SR_Pos)\r
-\r
-#define   CCU4_CC4_SRS_E1SR_Pos        (10U)\r
-#define   CCU4_CC4_SRS_E1SR_Msk        (0x00000003U  << CCU4_CC4_SRS_E1SR_Pos)\r
-\r
-#define   CCU4_CC4_SRS_E2SR_Pos        (12U)\r
-#define   CCU4_CC4_SRS_E2SR_Msk        (0x00000003U  << CCU4_CC4_SRS_E2SR_Pos)\r
-\r
-/* CCU4_CC4_SWS  =  Interrupt Status Set*/\r
-#define   CCU4_CC4_SWS_SPM_Pos         (0U)\r
-#define   CCU4_CC4_SWS_SPM_Msk         (0x00000001U  << CCU4_CC4_SWS_SPM_Pos)\r
-\r
-#define   CCU4_CC4_SWS_SOM_Pos         (1U)\r
-#define   CCU4_CC4_SWS_SOM_Msk         (0x00000001U  << CCU4_CC4_SWS_SOM_Pos)\r
-\r
-#define   CCU4_CC4_SWS_SCMU_Pos        (2U)\r
-#define   CCU4_CC4_SWS_SCMU_Msk        (0x00000001U  << CCU4_CC4_SWS_SCMU_Pos)\r
-\r
-#define   CCU4_CC4_SWS_SCMD_Pos        (3U)\r
-#define   CCU4_CC4_SWS_SCMD_Msk        (0x00000001U  << CCU4_CC4_SWS_SCMD_Pos)\r
-\r
-#define   CCU4_CC4_SWS_SE0A_Pos        (8U)\r
-#define   CCU4_CC4_SWS_SE0A_Msk        (0x00000001U  << CCU4_CC4_SWS_SE0A_Pos)\r
-\r
-#define   CCU4_CC4_SWS_SE1A_Pos        (9U)\r
-#define   CCU4_CC4_SWS_SE1A_Msk        (0x00000001U  << CCU4_CC4_SWS_SE1A_Pos)\r
-\r
-#define   CCU4_CC4_SWS_SE2A_Pos        (10U)\r
-#define   CCU4_CC4_SWS_SE2A_Msk        (0x00000001U  << CCU4_CC4_SWS_SE2A_Pos)\r
-\r
-#define   CCU4_CC4_SWS_STRPF_Pos       (11U)\r
-#define   CCU4_CC4_SWS_STRPF_Msk       (0x00000001U  << CCU4_CC4_SWS_STRPF_Pos)\r
-\r
-/* CCU4_CC4_SWR  =  Interrupt Status Clear*/\r
-#define   CCU4_CC4_SWR_RPM_Pos         (0U)\r
-#define   CCU4_CC4_SWR_RPM_Msk         (0x00000001U  << CCU4_CC4_SWR_RPM_Pos)\r
-\r
-#define   CCU4_CC4_SWR_ROM_Pos         (1U)\r
-#define   CCU4_CC4_SWR_ROM_Msk         (0x00000001U  << CCU4_CC4_SWR_ROM_Pos)\r
-\r
-#define   CCU4_CC4_SWR_RCMU_Pos        (2U)\r
-#define   CCU4_CC4_SWR_RCMU_Msk        (0x00000001U  << CCU4_CC4_SWR_RCMU_Pos)\r
-\r
-#define   CCU4_CC4_SWR_RCMD_Pos        (3U)\r
-#define   CCU4_CC4_SWR_RCMD_Msk        (0x00000001U  << CCU4_CC4_SWR_RCMD_Pos)\r
-\r
-#define   CCU4_CC4_SWR_RE0A_Pos        (8U)\r
-#define   CCU4_CC4_SWR_RE0A_Msk        (0x00000001U  << CCU4_CC4_SWR_RE0A_Pos)\r
-\r
-#define   CCU4_CC4_SWR_RE1A_Pos        (9U)\r
-#define   CCU4_CC4_SWR_RE1A_Msk        (0x00000001U  << CCU4_CC4_SWR_RE1A_Pos)\r
-\r
-#define   CCU4_CC4_SWR_RE2A_Pos        (10U)\r
-#define   CCU4_CC4_SWR_RE2A_Msk        (0x00000001U  << CCU4_CC4_SWR_RE2A_Pos)\r
-\r
-#define   CCU4_CC4_SWR_RTRPF_Pos       (11U)\r
-#define   CCU4_CC4_SWR_RTRPF_Msk       (0x00000001U  << CCU4_CC4_SWR_RTRPF_Pos)\r
-\r
-\r
-\r
-/***   CCU8x Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* CCU8_GCTRL  =  Global Control Register*/\r
-#define   CCU8_GCTRL_PRBC_Pos          (0U)\r
-#define   CCU8_GCTRL_PRBC_Msk          (0x00000007U  << CCU8_GCTRL_PRBC_Pos)\r
-\r
-#define   CCU8_GCTRL_PCIS_Pos          (4U)\r
-#define   CCU8_GCTRL_PCIS_Msk          (0x00000003U  << CCU8_GCTRL_PCIS_Pos)\r
-\r
-#define   CCU8_GCTRL_SUSCFG_Pos        (8U)\r
-#define   CCU8_GCTRL_SUSCFG_Msk        (0x00000003U  << CCU8_GCTRL_SUSCFG_Pos)\r
-\r
-#define   CCU8_GCTRL_MSE0_Pos          (10U)\r
-#define   CCU8_GCTRL_MSE0_Msk          (0x00000001U  << CCU8_GCTRL_MSE0_Pos)\r
-\r
-#define   CCU8_GCTRL_MSE1_Pos          (11U)\r
-#define   CCU8_GCTRL_MSE1_Msk          (0x00000001U  << CCU8_GCTRL_MSE1_Pos)\r
-\r
-#define   CCU8_GCTRL_MSE2_Pos          (12U)\r
-#define   CCU8_GCTRL_MSE2_Msk          (0x00000001U  << CCU8_GCTRL_MSE2_Pos)\r
-\r
-#define   CCU8_GCTRL_MSE3_Pos          (13U)\r
-#define   CCU8_GCTRL_MSE3_Msk          (0x00000001U  << CCU8_GCTRL_MSE3_Pos)\r
-\r
-#define   CCU8_GCTRL_MSDE_Pos          (14U)\r
-#define   CCU8_GCTRL_MSDE_Msk          (0x00000003U  << CCU8_GCTRL_MSDE_Pos)\r
-\r
-/* CCU8_GSTAT  =  Global Status Register*/\r
-#define   CCU8_GSTAT_S0I_Pos   (0U)\r
-#define   CCU8_GSTAT_S0I_Msk   (0x00000001U  << CCU8_GSTAT_S0I_Pos)\r
-\r
-#define   CCU8_GSTAT_S1I_Pos   (1U)\r
-#define   CCU8_GSTAT_S1I_Msk   (0x00000001U  << CCU8_GSTAT_S1I_Pos)\r
-\r
-#define   CCU8_GSTAT_S2I_Pos   (2U)\r
-#define   CCU8_GSTAT_S2I_Msk   (0x00000001U  << CCU8_GSTAT_S2I_Pos)\r
-\r
-#define   CCU8_GSTAT_S3I_Pos   (3U)\r
-#define   CCU8_GSTAT_S3I_Msk   (0x00000001U  << CCU8_GSTAT_S3I_Pos)\r
-\r
-#define   CCU8_GSTAT_PRB_Pos   (8U)\r
-#define   CCU8_GSTAT_PRB_Msk   (0x00000001U  << CCU8_GSTAT_PRB_Pos)\r
-\r
-#define   CCU8_GSTAT_PCRB_Pos          (10U)\r
-#define   CCU8_GSTAT_PCRB_Msk          (0x00000001U  << CCU8_GSTAT_PCRB_Pos)\r
-\r
-/* CCU8_GIDLS  =  Global Idle Set*/\r
-#define   CCU8_GIDLS_SS0I_Pos          (0U)\r
-#define   CCU8_GIDLS_SS0I_Msk          (0x00000001U  << CCU8_GIDLS_SS0I_Pos)\r
-\r
-#define   CCU8_GIDLS_SS1I_Pos          (1U)\r
-#define   CCU8_GIDLS_SS1I_Msk          (0x00000001U  << CCU8_GIDLS_SS1I_Pos)\r
-\r
-#define   CCU8_GIDLS_SS2I_Pos          (2U)\r
-#define   CCU8_GIDLS_SS2I_Msk          (0x00000001U  << CCU8_GIDLS_SS2I_Pos)\r
-\r
-#define   CCU8_GIDLS_SS3I_Pos          (3U)\r
-#define   CCU8_GIDLS_SS3I_Msk          (0x00000001U  << CCU8_GIDLS_SS3I_Pos)\r
-\r
-#define   CCU8_GIDLS_CPRB_Pos          (8U)\r
-#define   CCU8_GIDLS_CPRB_Msk          (0x00000001U  << CCU8_GIDLS_CPRB_Pos)\r
-\r
-#define   CCU8_GIDLS_PSIC_Pos          (9U)\r
-#define   CCU8_GIDLS_PSIC_Msk          (0x00000001U  << CCU8_GIDLS_PSIC_Pos)\r
-\r
-#define   CCU8_GIDLS_CPCH_Pos          (10U)\r
-#define   CCU8_GIDLS_CPCH_Msk          (0x00000001U  << CCU8_GIDLS_CPCH_Pos)\r
-\r
-/* CCU8_GIDLC  =  Global Idle Clear*/\r
-#define   CCU8_GIDLC_CS0I_Pos          (0U)\r
-#define   CCU8_GIDLC_CS0I_Msk          (0x00000001U  << CCU8_GIDLC_CS0I_Pos)\r
-\r
-#define   CCU8_GIDLC_CS1I_Pos          (1U)\r
-#define   CCU8_GIDLC_CS1I_Msk          (0x00000001U  << CCU8_GIDLC_CS1I_Pos)\r
-\r
-#define   CCU8_GIDLC_CS2I_Pos          (2U)\r
-#define   CCU8_GIDLC_CS2I_Msk          (0x00000001U  << CCU8_GIDLC_CS2I_Pos)\r
-\r
-#define   CCU8_GIDLC_CS3I_Pos          (3U)\r
-#define   CCU8_GIDLC_CS3I_Msk          (0x00000001U  << CCU8_GIDLC_CS3I_Pos)\r
-\r
-#define   CCU8_GIDLC_SPRB_Pos          (8U)\r
-#define   CCU8_GIDLC_SPRB_Msk          (0x00000001U  << CCU8_GIDLC_SPRB_Pos)\r
-\r
-#define   CCU8_GIDLC_SPCH_Pos          (10U)\r
-#define   CCU8_GIDLC_SPCH_Msk          (0x00000001U  << CCU8_GIDLC_SPCH_Pos)\r
-\r
-/* CCU8_GCSS  =  Global Channel Set*/\r
-#define   CCU8_GCSS_S0SE_Pos   (0U)\r
-#define   CCU8_GCSS_S0SE_Msk   (0x00000001U  << CCU8_GCSS_S0SE_Pos)\r
-\r
-#define   CCU8_GCSS_S0DSE_Pos          (1U)\r
-#define   CCU8_GCSS_S0DSE_Msk          (0x00000001U  << CCU8_GCSS_S0DSE_Pos)\r
-\r
-#define   CCU8_GCSS_S0PSE_Pos          (2U)\r
-#define   CCU8_GCSS_S0PSE_Msk          (0x00000001U  << CCU8_GCSS_S0PSE_Pos)\r
-\r
-#define   CCU8_GCSS_S1SE_Pos   (4U)\r
-#define   CCU8_GCSS_S1SE_Msk   (0x00000001U  << CCU8_GCSS_S1SE_Pos)\r
-\r
-#define   CCU8_GCSS_S1DSE_Pos          (5U)\r
-#define   CCU8_GCSS_S1DSE_Msk          (0x00000001U  << CCU8_GCSS_S1DSE_Pos)\r
-\r
-#define   CCU8_GCSS_S1PSE_Pos          (6U)\r
-#define   CCU8_GCSS_S1PSE_Msk          (0x00000001U  << CCU8_GCSS_S1PSE_Pos)\r
-\r
-#define   CCU8_GCSS_S2SE_Pos   (8U)\r
-#define   CCU8_GCSS_S2SE_Msk   (0x00000001U  << CCU8_GCSS_S2SE_Pos)\r
-\r
-#define   CCU8_GCSS_S2DSE_Pos          (9U)\r
-#define   CCU8_GCSS_S2DSE_Msk          (0x00000001U  << CCU8_GCSS_S2DSE_Pos)\r
-\r
-#define   CCU8_GCSS_S2PSE_Pos          (10U)\r
-#define   CCU8_GCSS_S2PSE_Msk          (0x00000001U  << CCU8_GCSS_S2PSE_Pos)\r
-\r
-#define   CCU8_GCSS_S3SE_Pos   (12U)\r
-#define   CCU8_GCSS_S3SE_Msk   (0x00000001U  << CCU8_GCSS_S3SE_Pos)\r
-\r
-#define   CCU8_GCSS_S3DSE_Pos          (13U)\r
-#define   CCU8_GCSS_S3DSE_Msk          (0x00000001U  << CCU8_GCSS_S3DSE_Pos)\r
-\r
-#define   CCU8_GCSS_S3PSE_Pos          (14U)\r
-#define   CCU8_GCSS_S3PSE_Msk          (0x00000001U  << CCU8_GCSS_S3PSE_Pos)\r
-\r
-#define   CCU8_GCSS_S0ST1S_Pos         (16U)\r
-#define   CCU8_GCSS_S0ST1S_Msk         (0x00000001U  << CCU8_GCSS_S0ST1S_Pos)\r
-\r
-#define   CCU8_GCSS_S1ST1S_Pos         (17U)\r
-#define   CCU8_GCSS_S1ST1S_Msk         (0x00000001U  << CCU8_GCSS_S1ST1S_Pos)\r
-\r
-#define   CCU8_GCSS_S2ST1S_Pos         (18U)\r
-#define   CCU8_GCSS_S2ST1S_Msk         (0x00000001U  << CCU8_GCSS_S2ST1S_Pos)\r
-\r
-#define   CCU8_GCSS_S3ST1S_Pos         (19U)\r
-#define   CCU8_GCSS_S3ST1S_Msk         (0x00000001U  << CCU8_GCSS_S3ST1S_Pos)\r
-\r
-#define   CCU8_GCSS_S0ST2S_Pos         (20U)\r
-#define   CCU8_GCSS_S0ST2S_Msk         (0x00000001U  << CCU8_GCSS_S0ST2S_Pos)\r
-\r
-#define   CCU8_GCSS_S1ST2S_Pos         (21U)\r
-#define   CCU8_GCSS_S1ST2S_Msk         (0x00000001U  << CCU8_GCSS_S1ST2S_Pos)\r
-\r
-#define   CCU8_GCSS_S2ST2S_Pos         (22U)\r
-#define   CCU8_GCSS_S2ST2S_Msk         (0x00000001U  << CCU8_GCSS_S2ST2S_Pos)\r
-\r
-#define   CCU8_GCSS_S3ST2S_Pos         (23U)\r
-#define   CCU8_GCSS_S3ST2S_Msk         (0x00000001U  << CCU8_GCSS_S3ST2S_Pos)\r
-\r
-/* CCU8_GCSC  =  Global Channel Clear*/\r
-#define   CCU8_GCSC_S0SC_Pos   (0U)\r
-#define   CCU8_GCSC_S0SC_Msk   (0x00000001U  << CCU8_GCSC_S0SC_Pos)\r
-\r
-#define   CCU8_GCSC_S0DSC_Pos          (1U)\r
-#define   CCU8_GCSC_S0DSC_Msk          (0x00000001U  << CCU8_GCSC_S0DSC_Pos)\r
-\r
-#define   CCU8_GCSC_S0PSC_Pos          (2U)\r
-#define   CCU8_GCSC_S0PSC_Msk          (0x00000001U  << CCU8_GCSC_S0PSC_Pos)\r
-\r
-#define   CCU8_GCSC_S1SC_Pos   (4U)\r
-#define   CCU8_GCSC_S1SC_Msk   (0x00000001U  << CCU8_GCSC_S1SC_Pos)\r
-\r
-#define   CCU8_GCSC_S1DSC_Pos          (5U)\r
-#define   CCU8_GCSC_S1DSC_Msk          (0x00000001U  << CCU8_GCSC_S1DSC_Pos)\r
-\r
-#define   CCU8_GCSC_S1PSC_Pos          (6U)\r
-#define   CCU8_GCSC_S1PSC_Msk          (0x00000001U  << CCU8_GCSC_S1PSC_Pos)\r
-\r
-#define   CCU8_GCSC_S2SC_Pos   (8U)\r
-#define   CCU8_GCSC_S2SC_Msk   (0x00000001U  << CCU8_GCSC_S2SC_Pos)\r
-\r
-#define   CCU8_GCSC_S2DSC_Pos          (9U)\r
-#define   CCU8_GCSC_S2DSC_Msk          (0x00000001U  << CCU8_GCSC_S2DSC_Pos)\r
-\r
-#define   CCU8_GCSC_S2PSC_Pos          (10U)\r
-#define   CCU8_GCSC_S2PSC_Msk          (0x00000001U  << CCU8_GCSC_S2PSC_Pos)\r
-\r
-#define   CCU8_GCSC_S3SC_Pos   (12U)\r
-#define   CCU8_GCSC_S3SC_Msk   (0x00000001U  << CCU8_GCSC_S3SC_Pos)\r
-\r
-#define   CCU8_GCSC_S3DSC_Pos          (13U)\r
-#define   CCU8_GCSC_S3DSC_Msk          (0x00000001U  << CCU8_GCSC_S3DSC_Pos)\r
-\r
-#define   CCU8_GCSC_S3PSC_Pos          (14U)\r
-#define   CCU8_GCSC_S3PSC_Msk          (0x00000001U  << CCU8_GCSC_S3PSC_Pos)\r
-\r
-#define   CCU8_GCSC_S0ST1C_Pos         (16U)\r
-#define   CCU8_GCSC_S0ST1C_Msk         (0x00000001U  << CCU8_GCSC_S0ST1C_Pos)\r
-\r
-#define   CCU8_GCSC_S1ST1C_Pos         (17U)\r
-#define   CCU8_GCSC_S1ST1C_Msk         (0x00000001U  << CCU8_GCSC_S1ST1C_Pos)\r
-\r
-#define   CCU8_GCSC_S2ST1C_Pos         (18U)\r
-#define   CCU8_GCSC_S2ST1C_Msk         (0x00000001U  << CCU8_GCSC_S2ST1C_Pos)\r
-\r
-#define   CCU8_GCSC_S3ST1C_Pos         (19U)\r
-#define   CCU8_GCSC_S3ST1C_Msk         (0x00000001U  << CCU8_GCSC_S3ST1C_Pos)\r
-\r
-#define   CCU8_GCSC_S0ST2C_Pos         (20U)\r
-#define   CCU8_GCSC_S0ST2C_Msk         (0x00000001U  << CCU8_GCSC_S0ST2C_Pos)\r
-\r
-#define   CCU8_GCSC_S1ST2C_Pos         (21U)\r
-#define   CCU8_GCSC_S1ST2C_Msk         (0x00000001U  << CCU8_GCSC_S1ST2C_Pos)\r
-\r
-#define   CCU8_GCSC_S2ST2C_Pos         (22U)\r
-#define   CCU8_GCSC_S2ST2C_Msk         (0x00000001U  << CCU8_GCSC_S2ST2C_Pos)\r
-\r
-#define   CCU8_GCSC_S3ST2C_Pos         (23U)\r
-#define   CCU8_GCSC_S3ST2C_Msk         (0x00000001U  << CCU8_GCSC_S3ST2C_Pos)\r
-\r
-/* CCU8_GCST  =  Global Channel status*/\r
-#define   CCU8_GCST_S0SS_Pos   (0U)\r
-#define   CCU8_GCST_S0SS_Msk   (0x00000001U  << CCU8_GCST_S0SS_Pos)\r
-\r
-#define   CCU8_GCST_S0DSS_Pos          (1U)\r
-#define   CCU8_GCST_S0DSS_Msk          (0x00000001U  << CCU8_GCST_S0DSS_Pos)\r
-\r
-#define   CCU8_GCST_S0PSS_Pos          (2U)\r
-#define   CCU8_GCST_S0PSS_Msk          (0x00000001U  << CCU8_GCST_S0PSS_Pos)\r
-\r
-#define   CCU8_GCST_S1SS_Pos   (4U)\r
-#define   CCU8_GCST_S1SS_Msk   (0x00000001U  << CCU8_GCST_S1SS_Pos)\r
-\r
-#define   CCU8_GCST_S1DSS_Pos          (5U)\r
-#define   CCU8_GCST_S1DSS_Msk          (0x00000001U  << CCU8_GCST_S1DSS_Pos)\r
-\r
-#define   CCU8_GCST_S1PSS_Pos          (6U)\r
-#define   CCU8_GCST_S1PSS_Msk          (0x00000001U  << CCU8_GCST_S1PSS_Pos)\r
-\r
-#define   CCU8_GCST_S2SS_Pos   (8U)\r
-#define   CCU8_GCST_S2SS_Msk   (0x00000001U  << CCU8_GCST_S2SS_Pos)\r
-\r
-#define   CCU8_GCST_S2DSS_Pos          (9U)\r
-#define   CCU8_GCST_S2DSS_Msk          (0x00000001U  << CCU8_GCST_S2DSS_Pos)\r
-\r
-#define   CCU8_GCST_S2PSS_Pos          (10U)\r
-#define   CCU8_GCST_S2PSS_Msk          (0x00000001U  << CCU8_GCST_S2PSS_Pos)\r
-\r
-#define   CCU8_GCST_S3SS_Pos   (12U)\r
-#define   CCU8_GCST_S3SS_Msk   (0x00000001U  << CCU8_GCST_S3SS_Pos)\r
-\r
-#define   CCU8_GCST_S3DSS_Pos          (13U)\r
-#define   CCU8_GCST_S3DSS_Msk          (0x00000001U  << CCU8_GCST_S3DSS_Pos)\r
-\r
-#define   CCU8_GCST_S3PSS_Pos          (14U)\r
-#define   CCU8_GCST_S3PSS_Msk          (0x00000001U  << CCU8_GCST_S3PSS_Pos)\r
-\r
-#define   CCU8_GCST_CC80ST1_Pos        (16U)\r
-#define   CCU8_GCST_CC80ST1_Msk        (0x00000001U  << CCU8_GCST_CC80ST1_Pos)\r
-\r
-#define   CCU8_GCST_CC81ST1_Pos        (17U)\r
-#define   CCU8_GCST_CC81ST1_Msk        (0x00000001U  << CCU8_GCST_CC81ST1_Pos)\r
-\r
-#define   CCU8_GCST_CC82ST1_Pos        (18U)\r
-#define   CCU8_GCST_CC82ST1_Msk        (0x00000001U  << CCU8_GCST_CC82ST1_Pos)\r
-\r
-#define   CCU8_GCST_CC83ST1_Pos        (19U)\r
-#define   CCU8_GCST_CC83ST1_Msk        (0x00000001U  << CCU8_GCST_CC83ST1_Pos)\r
-\r
-#define   CCU8_GCST_CC80ST2_Pos        (20U)\r
-#define   CCU8_GCST_CC80ST2_Msk        (0x00000001U  << CCU8_GCST_CC80ST2_Pos)\r
-\r
-#define   CCU8_GCST_CC81ST2_Pos        (21U)\r
-#define   CCU8_GCST_CC81ST2_Msk        (0x00000001U  << CCU8_GCST_CC81ST2_Pos)\r
-\r
-#define   CCU8_GCST_CC82ST2_Pos        (22U)\r
-#define   CCU8_GCST_CC82ST2_Msk        (0x00000001U  << CCU8_GCST_CC82ST2_Pos)\r
-\r
-#define   CCU8_GCST_CC83ST2_Pos        (23U)\r
-#define   CCU8_GCST_CC83ST2_Msk        (0x00000001U  << CCU8_GCST_CC83ST2_Pos)\r
-\r
-/* CCU8_GPCHK  =  Parity Checker Configuration*/\r
-#define   CCU8_GPCHK_PASE_Pos          (0U)\r
-#define   CCU8_GPCHK_PASE_Msk          (0x00000001U  << CCU8_GPCHK_PASE_Pos)\r
-\r
-#define   CCU8_GPCHK_PACS_Pos          (1U)\r
-#define   CCU8_GPCHK_PACS_Msk          (0x00000003U  << CCU8_GPCHK_PACS_Pos)\r
-\r
-#define   CCU8_GPCHK_PISEL_Pos         (3U)\r
-#define   CCU8_GPCHK_PISEL_Msk         (0x00000003U  << CCU8_GPCHK_PISEL_Pos)\r
-\r
-#define   CCU8_GPCHK_PCDS_Pos          (5U)\r
-#define   CCU8_GPCHK_PCDS_Msk          (0x00000003U  << CCU8_GPCHK_PCDS_Pos)\r
-\r
-#define   CCU8_GPCHK_PCTS_Pos          (7U)\r
-#define   CCU8_GPCHK_PCTS_Msk          (0x00000001U  << CCU8_GPCHK_PCTS_Pos)\r
-\r
-#define   CCU8_GPCHK_PCST_Pos          (15U)\r
-#define   CCU8_GPCHK_PCST_Msk          (0x00000001U  << CCU8_GPCHK_PCST_Pos)\r
-\r
-#define   CCU8_GPCHK_PCSEL0_Pos        (16U)\r
-#define   CCU8_GPCHK_PCSEL0_Msk        (0x0000000FU  << CCU8_GPCHK_PCSEL0_Pos)\r
-\r
-#define   CCU8_GPCHK_PCSEL1_Pos        (20U)\r
-#define   CCU8_GPCHK_PCSEL1_Msk        (0x0000000FU  << CCU8_GPCHK_PCSEL1_Pos)\r
-\r
-#define   CCU8_GPCHK_PCSEL2_Pos        (24U)\r
-#define   CCU8_GPCHK_PCSEL2_Msk        (0x0000000FU  << CCU8_GPCHK_PCSEL2_Pos)\r
-\r
-#define   CCU8_GPCHK_PCSEL3_Pos        (28U)\r
-#define   CCU8_GPCHK_PCSEL3_Msk        (0x0000000FU  << CCU8_GPCHK_PCSEL3_Pos)\r
-\r
-/* CCU8_ECRD  =  Extended Capture Mode Read*/\r
-#define   CCU8_ECRD_CAPV_Pos   (0U)\r
-#define   CCU8_ECRD_CAPV_Msk   (0x0000FFFFU  << CCU8_ECRD_CAPV_Pos)\r
-\r
-#define   CCU8_ECRD_FPCV_Pos   (16U)\r
-#define   CCU8_ECRD_FPCV_Msk   (0x0000000FU  << CCU8_ECRD_FPCV_Pos)\r
-\r
-#define   CCU8_ECRD_SPTR_Pos   (20U)\r
-#define   CCU8_ECRD_SPTR_Msk   (0x00000003U  << CCU8_ECRD_SPTR_Pos)\r
-\r
-#define   CCU8_ECRD_VPTR_Pos   (22U)\r
-#define   CCU8_ECRD_VPTR_Msk   (0x00000003U  << CCU8_ECRD_VPTR_Pos)\r
-\r
-#define   CCU8_ECRD_FFL_Pos    (24U)\r
-#define   CCU8_ECRD_FFL_Msk    (0x00000001U  << CCU8_ECRD_FFL_Pos)\r
-\r
-/* CCU8_MIDR  =  Module Identification*/\r
-#define   CCU8_MIDR_MODR_Pos   (0U)\r
-#define   CCU8_MIDR_MODR_Msk   (0x000000FFU  << CCU8_MIDR_MODR_Pos)\r
-\r
-#define   CCU8_MIDR_MODT_Pos   (8U)\r
-#define   CCU8_MIDR_MODT_Msk   (0x000000FFU  << CCU8_MIDR_MODT_Pos)\r
-\r
-#define   CCU8_MIDR_MODN_Pos   (16U)\r
-#define   CCU8_MIDR_MODN_Msk   (0x0000FFFFU  << CCU8_MIDR_MODN_Pos)\r
-\r
-/* CCU8_CC8_INS  =  Input Selector Configuration*/\r
-#define   CCU8_CC8_INS_EV0IS_Pos       (0U)\r
-#define   CCU8_CC8_INS_EV0IS_Msk       (0x0000000FU  << CCU8_CC8_INS_EV0IS_Pos)\r
-\r
-#define   CCU8_CC8_INS_EV1IS_Pos       (4U)\r
-#define   CCU8_CC8_INS_EV1IS_Msk       (0x0000000FU  << CCU8_CC8_INS_EV1IS_Pos)\r
-\r
-#define   CCU8_CC8_INS_EV2S_Pos        (8U)\r
-#define   CCU8_CC8_INS_EV2S_Msk        (0x0000000FU  << CCU8_CC8_INS_EV2S_Pos)\r
-\r
-#define   CCU8_CC8_INS_EV0EM_Pos       (16U)\r
-#define   CCU8_CC8_INS_EV0EM_Msk       (0x00000003U  << CCU8_CC8_INS_EV0EM_Pos)\r
-\r
-#define   CCU8_CC8_INS_EV1EM_Pos       (18U)\r
-#define   CCU8_CC8_INS_EV1EM_Msk       (0x00000003U  << CCU8_CC8_INS_EV1EM_Pos)\r
-\r
-#define   CCU8_CC8_INS_EV2EM_Pos       (20U)\r
-#define   CCU8_CC8_INS_EV2EM_Msk       (0x00000003U  << CCU8_CC8_INS_EV2EM_Pos)\r
-\r
-#define   CCU8_CC8_INS_EV0LM_Pos       (22U)\r
-#define   CCU8_CC8_INS_EV0LM_Msk       (0x00000001U  << CCU8_CC8_INS_EV0LM_Pos)\r
-\r
-#define   CCU8_CC8_INS_EV1LM_Pos       (23U)\r
-#define   CCU8_CC8_INS_EV1LM_Msk       (0x00000001U  << CCU8_CC8_INS_EV1LM_Pos)\r
-\r
-#define   CCU8_CC8_INS_EV2LM_Pos       (24U)\r
-#define   CCU8_CC8_INS_EV2LM_Msk       (0x00000001U  << CCU8_CC8_INS_EV2LM_Pos)\r
-\r
-#define   CCU8_CC8_INS_LPF0M_Pos       (25U)\r
-#define   CCU8_CC8_INS_LPF0M_Msk       (0x00000003U  << CCU8_CC8_INS_LPF0M_Pos)\r
-\r
-#define   CCU8_CC8_INS_LPF1M_Pos       (27U)\r
-#define   CCU8_CC8_INS_LPF1M_Msk       (0x00000003U  << CCU8_CC8_INS_LPF1M_Pos)\r
-\r
-#define   CCU8_CC8_INS_LPF2M_Pos       (29U)\r
-#define   CCU8_CC8_INS_LPF2M_Msk       (0x00000003U  << CCU8_CC8_INS_LPF2M_Pos)\r
-\r
-/* CCU8_CC8_CMC  =  Connection Matrix Control*/\r
-#define   CCU8_CC8_CMC_STRTS_Pos       (0U)\r
-#define   CCU8_CC8_CMC_STRTS_Msk       (0x00000003U  << CCU8_CC8_CMC_STRTS_Pos)\r
-\r
-#define   CCU8_CC8_CMC_ENDS_Pos        (2U)\r
-#define   CCU8_CC8_CMC_ENDS_Msk        (0x00000003U  << CCU8_CC8_CMC_ENDS_Pos)\r
-\r
-#define   CCU8_CC8_CMC_CAP0S_Pos       (4U)\r
-#define   CCU8_CC8_CMC_CAP0S_Msk       (0x00000003U  << CCU8_CC8_CMC_CAP0S_Pos)\r
-\r
-#define   CCU8_CC8_CMC_CAP1S_Pos       (6U)\r
-#define   CCU8_CC8_CMC_CAP1S_Msk       (0x00000003U  << CCU8_CC8_CMC_CAP1S_Pos)\r
-\r
-#define   CCU8_CC8_CMC_GATES_Pos       (8U)\r
-#define   CCU8_CC8_CMC_GATES_Msk       (0x00000003U  << CCU8_CC8_CMC_GATES_Pos)\r
-\r
-#define   CCU8_CC8_CMC_UDS_Pos         (10U)\r
-#define   CCU8_CC8_CMC_UDS_Msk         (0x00000003U  << CCU8_CC8_CMC_UDS_Pos)\r
-\r
-#define   CCU8_CC8_CMC_LDS_Pos         (12U)\r
-#define   CCU8_CC8_CMC_LDS_Msk         (0x00000003U  << CCU8_CC8_CMC_LDS_Pos)\r
-\r
-#define   CCU8_CC8_CMC_CNTS_Pos        (14U)\r
-#define   CCU8_CC8_CMC_CNTS_Msk        (0x00000003U  << CCU8_CC8_CMC_CNTS_Pos)\r
-\r
-#define   CCU8_CC8_CMC_OFS_Pos         (16U)\r
-#define   CCU8_CC8_CMC_OFS_Msk         (0x00000001U  << CCU8_CC8_CMC_OFS_Pos)\r
-\r
-#define   CCU8_CC8_CMC_TS_Pos          (17U)\r
-#define   CCU8_CC8_CMC_TS_Msk          (0x00000001U  << CCU8_CC8_CMC_TS_Pos)\r
-\r
-#define   CCU8_CC8_CMC_MOS_Pos         (18U)\r
-#define   CCU8_CC8_CMC_MOS_Msk         (0x00000003U  << CCU8_CC8_CMC_MOS_Pos)\r
-\r
-#define   CCU8_CC8_CMC_TCE_Pos         (20U)\r
-#define   CCU8_CC8_CMC_TCE_Msk         (0x00000001U  << CCU8_CC8_CMC_TCE_Pos)\r
-\r
-/* CCU8_CC8_TCST  =  Slice Timer Status*/\r
-#define   CCU8_CC8_TCST_TRB_Pos        (0U)\r
-#define   CCU8_CC8_TCST_TRB_Msk        (0x00000001U  << CCU8_CC8_TCST_TRB_Pos)\r
-\r
-#define   CCU8_CC8_TCST_CDIR_Pos       (1U)\r
-#define   CCU8_CC8_TCST_CDIR_Msk       (0x00000001U  << CCU8_CC8_TCST_CDIR_Pos)\r
-\r
-#define   CCU8_CC8_TCST_DTR1_Pos       (3U)\r
-#define   CCU8_CC8_TCST_DTR1_Msk       (0x00000001U  << CCU8_CC8_TCST_DTR1_Pos)\r
-\r
-#define   CCU8_CC8_TCST_DTR2_Pos       (4U)\r
-#define   CCU8_CC8_TCST_DTR2_Msk       (0x00000001U  << CCU8_CC8_TCST_DTR2_Pos)\r
-\r
-/* CCU8_CC8_TCSET  =  Slice Timer Run Set*/\r
-#define   CCU8_CC8_TCSET_TRBS_Pos      (0U)\r
-#define   CCU8_CC8_TCSET_TRBS_Msk      (0x00000001U  << CCU8_CC8_TCSET_TRBS_Pos)\r
-\r
-/* CCU8_CC8_TCCLR  =  Slice Timer Clear*/\r
-#define   CCU8_CC8_TCCLR_TRBC_Pos      (0U)\r
-#define   CCU8_CC8_TCCLR_TRBC_Msk      (0x00000001U  << CCU8_CC8_TCCLR_TRBC_Pos)\r
-\r
-#define   CCU8_CC8_TCCLR_TCC_Pos       (1U)\r
-#define   CCU8_CC8_TCCLR_TCC_Msk       (0x00000001U  << CCU8_CC8_TCCLR_TCC_Pos)\r
-\r
-#define   CCU8_CC8_TCCLR_DITC_Pos      (2U)\r
-#define   CCU8_CC8_TCCLR_DITC_Msk      (0x00000001U  << CCU8_CC8_TCCLR_DITC_Pos)\r
-\r
-#define   CCU8_CC8_TCCLR_DTC1C_Pos     (3U)\r
-#define   CCU8_CC8_TCCLR_DTC1C_Msk     (0x00000001U  << CCU8_CC8_TCCLR_DTC1C_Pos)\r
-\r
-#define   CCU8_CC8_TCCLR_DTC2C_Pos     (4U)\r
-#define   CCU8_CC8_TCCLR_DTC2C_Msk     (0x00000001U  << CCU8_CC8_TCCLR_DTC2C_Pos)\r
-\r
-/* CCU8_CC8_TC  =  Slice Timer Control*/\r
-#define   CCU8_CC8_TC_TCM_Pos          (0U)\r
-#define   CCU8_CC8_TC_TCM_Msk          (0x00000001U  << CCU8_CC8_TC_TCM_Pos)\r
-\r
-#define   CCU8_CC8_TC_TSSM_Pos         (1U)\r
-#define   CCU8_CC8_TC_TSSM_Msk         (0x00000001U  << CCU8_CC8_TC_TSSM_Pos)\r
-\r
-#define   CCU8_CC8_TC_CLST_Pos         (2U)\r
-#define   CCU8_CC8_TC_CLST_Msk         (0x00000001U  << CCU8_CC8_TC_CLST_Pos)\r
-\r
-#define   CCU8_CC8_TC_CMOD_Pos         (3U)\r
-#define   CCU8_CC8_TC_CMOD_Msk         (0x00000001U  << CCU8_CC8_TC_CMOD_Pos)\r
-\r
-#define   CCU8_CC8_TC_ECM_Pos          (4U)\r
-#define   CCU8_CC8_TC_ECM_Msk          (0x00000001U  << CCU8_CC8_TC_ECM_Pos)\r
-\r
-#define   CCU8_CC8_TC_CAPC_Pos         (5U)\r
-#define   CCU8_CC8_TC_CAPC_Msk         (0x00000003U  << CCU8_CC8_TC_CAPC_Pos)\r
-\r
-#define   CCU8_CC8_TC_TLS_Pos          (7U)\r
-#define   CCU8_CC8_TC_TLS_Msk          (0x00000001U  << CCU8_CC8_TC_TLS_Pos)\r
-\r
-#define   CCU8_CC8_TC_ENDM_Pos         (8U)\r
-#define   CCU8_CC8_TC_ENDM_Msk         (0x00000003U  << CCU8_CC8_TC_ENDM_Pos)\r
-\r
-#define   CCU8_CC8_TC_STRM_Pos         (10U)\r
-#define   CCU8_CC8_TC_STRM_Msk         (0x00000001U  << CCU8_CC8_TC_STRM_Pos)\r
-\r
-#define   CCU8_CC8_TC_SCE_Pos          (11U)\r
-#define   CCU8_CC8_TC_SCE_Msk          (0x00000001U  << CCU8_CC8_TC_SCE_Pos)\r
-\r
-#define   CCU8_CC8_TC_CCS_Pos          (12U)\r
-#define   CCU8_CC8_TC_CCS_Msk          (0x00000001U  << CCU8_CC8_TC_CCS_Pos)\r
-\r
-#define   CCU8_CC8_TC_DITHE_Pos        (13U)\r
-#define   CCU8_CC8_TC_DITHE_Msk        (0x00000003U  << CCU8_CC8_TC_DITHE_Pos)\r
-\r
-#define   CCU8_CC8_TC_DIM_Pos          (15U)\r
-#define   CCU8_CC8_TC_DIM_Msk          (0x00000001U  << CCU8_CC8_TC_DIM_Pos)\r
-\r
-#define   CCU8_CC8_TC_FPE_Pos          (16U)\r
-#define   CCU8_CC8_TC_FPE_Msk          (0x00000001U  << CCU8_CC8_TC_FPE_Pos)\r
-\r
-#define   CCU8_CC8_TC_TRAPE0_Pos       (17U)\r
-#define   CCU8_CC8_TC_TRAPE0_Msk       (0x00000001U  << CCU8_CC8_TC_TRAPE0_Pos)\r
-\r
-#define   CCU8_CC8_TC_TRAPE1_Pos       (18U)\r
-#define   CCU8_CC8_TC_TRAPE1_Msk       (0x00000001U  << CCU8_CC8_TC_TRAPE1_Pos)\r
-\r
-#define   CCU8_CC8_TC_TRAPE2_Pos       (19U)\r
-#define   CCU8_CC8_TC_TRAPE2_Msk       (0x00000001U  << CCU8_CC8_TC_TRAPE2_Pos)\r
-\r
-#define   CCU8_CC8_TC_TRAPE3_Pos       (20U)\r
-#define   CCU8_CC8_TC_TRAPE3_Msk       (0x00000001U  << CCU8_CC8_TC_TRAPE3_Pos)\r
-\r
-#define   CCU8_CC8_TC_TRPSE_Pos        (21U)\r
-#define   CCU8_CC8_TC_TRPSE_Msk        (0x00000001U  << CCU8_CC8_TC_TRPSE_Pos)\r
-\r
-#define   CCU8_CC8_TC_TRPSW_Pos        (22U)\r
-#define   CCU8_CC8_TC_TRPSW_Msk        (0x00000001U  << CCU8_CC8_TC_TRPSW_Pos)\r
-\r
-#define   CCU8_CC8_TC_EMS_Pos          (23U)\r
-#define   CCU8_CC8_TC_EMS_Msk          (0x00000001U  << CCU8_CC8_TC_EMS_Pos)\r
-\r
-#define   CCU8_CC8_TC_EMT_Pos          (24U)\r
-#define   CCU8_CC8_TC_EMT_Msk          (0x00000001U  << CCU8_CC8_TC_EMT_Pos)\r
-\r
-#define   CCU8_CC8_TC_MCME1_Pos        (25U)\r
-#define   CCU8_CC8_TC_MCME1_Msk        (0x00000001U  << CCU8_CC8_TC_MCME1_Pos)\r
-\r
-#define   CCU8_CC8_TC_MCME2_Pos        (26U)\r
-#define   CCU8_CC8_TC_MCME2_Msk        (0x00000001U  << CCU8_CC8_TC_MCME2_Pos)\r
-\r
-#define   CCU8_CC8_TC_EME_Pos          (27U)\r
-#define   CCU8_CC8_TC_EME_Msk          (0x00000003U  << CCU8_CC8_TC_EME_Pos)\r
-\r
-#define   CCU8_CC8_TC_STOS_Pos         (29U)\r
-#define   CCU8_CC8_TC_STOS_Msk         (0x00000003U  << CCU8_CC8_TC_STOS_Pos)\r
-\r
-/* CCU8_CC8_PSL  =  Passive Level Config*/\r
-#define   CCU8_CC8_PSL_PSL11_Pos       (0U)\r
-#define   CCU8_CC8_PSL_PSL11_Msk       (0x00000001U  << CCU8_CC8_PSL_PSL11_Pos)\r
-\r
-#define   CCU8_CC8_PSL_PSL12_Pos       (1U)\r
-#define   CCU8_CC8_PSL_PSL12_Msk       (0x00000001U  << CCU8_CC8_PSL_PSL12_Pos)\r
-\r
-#define   CCU8_CC8_PSL_PSL21_Pos       (2U)\r
-#define   CCU8_CC8_PSL_PSL21_Msk       (0x00000001U  << CCU8_CC8_PSL_PSL21_Pos)\r
-\r
-#define   CCU8_CC8_PSL_PSL22_Pos       (3U)\r
-#define   CCU8_CC8_PSL_PSL22_Msk       (0x00000001U  << CCU8_CC8_PSL_PSL22_Pos)\r
-\r
-/* CCU8_CC8_DIT  =  Dither Config*/\r
-#define   CCU8_CC8_DIT_DCV_Pos         (0U)\r
-#define   CCU8_CC8_DIT_DCV_Msk         (0x0000000FU  << CCU8_CC8_DIT_DCV_Pos)\r
-\r
-#define   CCU8_CC8_DIT_DCNT_Pos        (8U)\r
-#define   CCU8_CC8_DIT_DCNT_Msk        (0x0000000FU  << CCU8_CC8_DIT_DCNT_Pos)\r
-\r
-/* CCU8_CC8_DITS  =  Dither Shadow Register*/\r
-#define   CCU8_CC8_DITS_DCVS_Pos       (0U)\r
-#define   CCU8_CC8_DITS_DCVS_Msk       (0x0000000FU  << CCU8_CC8_DITS_DCVS_Pos)\r
-\r
-/* CCU8_CC8_PSC  =  Prescaler Control*/\r
-#define   CCU8_CC8_PSC_PSIV_Pos        (0U)\r
-#define   CCU8_CC8_PSC_PSIV_Msk        (0x0000000FU  << CCU8_CC8_PSC_PSIV_Pos)\r
-\r
-/* CCU8_CC8_FPC  =  Floating Prescaler Control*/\r
-#define   CCU8_CC8_FPC_PCMP_Pos        (0U)\r
-#define   CCU8_CC8_FPC_PCMP_Msk        (0x0000000FU  << CCU8_CC8_FPC_PCMP_Pos)\r
-\r
-#define   CCU8_CC8_FPC_PVAL_Pos        (8U)\r
-#define   CCU8_CC8_FPC_PVAL_Msk        (0x0000000FU  << CCU8_CC8_FPC_PVAL_Pos)\r
-\r
-/* CCU8_CC8_FPCS  =  Floating Prescaler Shadow*/\r
-#define   CCU8_CC8_FPCS_PCMP_Pos       (0U)\r
-#define   CCU8_CC8_FPCS_PCMP_Msk       (0x0000000FU  << CCU8_CC8_FPCS_PCMP_Pos)\r
-\r
-/* CCU8_CC8_PR  =  Timer Period Value*/\r
-#define   CCU8_CC8_PR_PR_Pos   (0U)\r
-#define   CCU8_CC8_PR_PR_Msk   (0x0000FFFFU  << CCU8_CC8_PR_PR_Pos)\r
-\r
-/* CCU8_CC8_PRS  =  Timer Shadow Period Value*/\r
-#define   CCU8_CC8_PRS_PRS_Pos         (0U)\r
-#define   CCU8_CC8_PRS_PRS_Msk         (0x0000FFFFU  << CCU8_CC8_PRS_PRS_Pos)\r
-\r
-/* CCU8_CC8_CR1  =  Channel 1 Compare Value*/\r
-#define   CCU8_CC8_CR1_CR1_Pos         (0U)\r
-#define   CCU8_CC8_CR1_CR1_Msk         (0x0000FFFFU  << CCU8_CC8_CR1_CR1_Pos)\r
-\r
-/* CCU8_CC8_CR1S  =  Channel 1 Compare Shadow Value*/\r
-#define   CCU8_CC8_CR1S_CR1S_Pos       (0U)\r
-#define   CCU8_CC8_CR1S_CR1S_Msk       (0x0000FFFFU  << CCU8_CC8_CR1S_CR1S_Pos)\r
-\r
-/* CCU8_CC8_CR2  =  Channel 2 Compare Value*/\r
-#define   CCU8_CC8_CR2_CR2_Pos         (0U)\r
-#define   CCU8_CC8_CR2_CR2_Msk         (0x0000FFFFU  << CCU8_CC8_CR2_CR2_Pos)\r
-\r
-/* CCU8_CC8_CR2S  =  Channel 2 Compare Shadow Value*/\r
-#define   CCU8_CC8_CR2S_CR2S_Pos       (0U)\r
-#define   CCU8_CC8_CR2S_CR2S_Msk       (0x0000FFFFU  << CCU8_CC8_CR2S_CR2S_Pos)\r
-\r
-/* CCU8_CC8_CHC  =  Channel Control*/\r
-#define   CCU8_CC8_CHC_ASE_Pos         (0U)\r
-#define   CCU8_CC8_CHC_ASE_Msk         (0x00000001U  << CCU8_CC8_CHC_ASE_Pos)\r
-\r
-#define   CCU8_CC8_CHC_OCS1_Pos        (1U)\r
-#define   CCU8_CC8_CHC_OCS1_Msk        (0x00000001U  << CCU8_CC8_CHC_OCS1_Pos)\r
-\r
-#define   CCU8_CC8_CHC_OCS2_Pos        (2U)\r
-#define   CCU8_CC8_CHC_OCS2_Msk        (0x00000001U  << CCU8_CC8_CHC_OCS2_Pos)\r
-\r
-#define   CCU8_CC8_CHC_OCS3_Pos        (3U)\r
-#define   CCU8_CC8_CHC_OCS3_Msk        (0x00000001U  << CCU8_CC8_CHC_OCS3_Pos)\r
-\r
-#define   CCU8_CC8_CHC_OCS4_Pos        (4U)\r
-#define   CCU8_CC8_CHC_OCS4_Msk        (0x00000001U  << CCU8_CC8_CHC_OCS4_Pos)\r
-\r
-/* CCU8_CC8_DTC  =  Dead Time Control*/\r
-#define   CCU8_CC8_DTC_DTE1_Pos        (0U)\r
-#define   CCU8_CC8_DTC_DTE1_Msk        (0x00000001U  << CCU8_CC8_DTC_DTE1_Pos)\r
-\r
-#define   CCU8_CC8_DTC_DTE2_Pos        (1U)\r
-#define   CCU8_CC8_DTC_DTE2_Msk        (0x00000001U  << CCU8_CC8_DTC_DTE2_Pos)\r
-\r
-#define   CCU8_CC8_DTC_DCEN1_Pos       (2U)\r
-#define   CCU8_CC8_DTC_DCEN1_Msk       (0x00000001U  << CCU8_CC8_DTC_DCEN1_Pos)\r
-\r
-#define   CCU8_CC8_DTC_DCEN2_Pos       (3U)\r
-#define   CCU8_CC8_DTC_DCEN2_Msk       (0x00000001U  << CCU8_CC8_DTC_DCEN2_Pos)\r
-\r
-#define   CCU8_CC8_DTC_DCEN3_Pos       (4U)\r
-#define   CCU8_CC8_DTC_DCEN3_Msk       (0x00000001U  << CCU8_CC8_DTC_DCEN3_Pos)\r
-\r
-#define   CCU8_CC8_DTC_DCEN4_Pos       (5U)\r
-#define   CCU8_CC8_DTC_DCEN4_Msk       (0x00000001U  << CCU8_CC8_DTC_DCEN4_Pos)\r
-\r
-#define   CCU8_CC8_DTC_DTCC_Pos        (6U)\r
-#define   CCU8_CC8_DTC_DTCC_Msk        (0x00000003U  << CCU8_CC8_DTC_DTCC_Pos)\r
-\r
-/* CCU8_CC8_DC1R  =  Channel 1 Dead Time Values*/\r
-#define   CCU8_CC8_DC1R_DT1R_Pos       (0U)\r
-#define   CCU8_CC8_DC1R_DT1R_Msk       (0x000000FFU  << CCU8_CC8_DC1R_DT1R_Pos)\r
-\r
-#define   CCU8_CC8_DC1R_DT1F_Pos       (8U)\r
-#define   CCU8_CC8_DC1R_DT1F_Msk       (0x000000FFU  << CCU8_CC8_DC1R_DT1F_Pos)\r
-\r
-/* CCU8_CC8_DC2R  =  Channel 2 Dead Time Values*/\r
-#define   CCU8_CC8_DC2R_DT2R_Pos       (0U)\r
-#define   CCU8_CC8_DC2R_DT2R_Msk       (0x000000FFU  << CCU8_CC8_DC2R_DT2R_Pos)\r
-\r
-#define   CCU8_CC8_DC2R_DT2F_Pos       (8U)\r
-#define   CCU8_CC8_DC2R_DT2F_Msk       (0x000000FFU  << CCU8_CC8_DC2R_DT2F_Pos)\r
-\r
-/* CCU8_CC8_TIMER  =  Timer Value*/\r
-#define   CCU8_CC8_TIMER_TVAL_Pos      (0U)\r
-#define   CCU8_CC8_TIMER_TVAL_Msk      (0x0000FFFFU  << CCU8_CC8_TIMER_TVAL_Pos)\r
-\r
-/* CCU8_CC8_C0V  =  Capture Register 0*/\r
-#define   CCU8_CC8_CV_CAPTV_Pos        (0U)\r
-#define   CCU8_CC8_CV_CAPTV_Msk        (0x0000FFFFU  << CCU8_CC8_CV_CAPTV_Pos)\r
-\r
-#define   CCU8_CC8_CV_FPCV_Pos         (16U)\r
-#define   CCU8_CC8_CV_FPCV_Msk         (0x0000000FU  << CCU8_CC8_CV_FPCV_Pos)\r
-\r
-#define   CCU8_CC8_CV_FFL_Pos          (20U)\r
-#define   CCU8_CC8_CV_FFL_Msk          (0x00000001U  << CCU8_CC8_CV_FFL_Pos)\r
-\r
-/* CCU8_CC8_INTS  =  Interrupt Status*/\r
-#define   CCU8_CC8_INTS_PMUS_Pos       (0U)\r
-#define   CCU8_CC8_INTS_PMUS_Msk       (0x00000001U  << CCU8_CC8_INTS_PMUS_Pos)\r
-\r
-#define   CCU8_CC8_INTS_OMDS_Pos       (1U)\r
-#define   CCU8_CC8_INTS_OMDS_Msk       (0x00000001U  << CCU8_CC8_INTS_OMDS_Pos)\r
-\r
-#define   CCU8_CC8_INTS_CMU1S_Pos      (2U)\r
-#define   CCU8_CC8_INTS_CMU1S_Msk      (0x00000001U  << CCU8_CC8_INTS_CMU1S_Pos)\r
-\r
-#define   CCU8_CC8_INTS_CMD1S_Pos      (3U)\r
-#define   CCU8_CC8_INTS_CMD1S_Msk      (0x00000001U  << CCU8_CC8_INTS_CMD1S_Pos)\r
-\r
-#define   CCU8_CC8_INTS_CMU2S_Pos      (4U)\r
-#define   CCU8_CC8_INTS_CMU2S_Msk      (0x00000001U  << CCU8_CC8_INTS_CMU2S_Pos)\r
-\r
-#define   CCU8_CC8_INTS_CMD2S_Pos      (5U)\r
-#define   CCU8_CC8_INTS_CMD2S_Msk      (0x00000001U  << CCU8_CC8_INTS_CMD2S_Pos)\r
-\r
-#define   CCU8_CC8_INTS_E0AS_Pos       (8U)\r
-#define   CCU8_CC8_INTS_E0AS_Msk       (0x00000001U  << CCU8_CC8_INTS_E0AS_Pos)\r
-\r
-#define   CCU8_CC8_INTS_E1AS_Pos       (9U)\r
-#define   CCU8_CC8_INTS_E1AS_Msk       (0x00000001U  << CCU8_CC8_INTS_E1AS_Pos)\r
-\r
-#define   CCU8_CC8_INTS_E2AS_Pos       (10U)\r
-#define   CCU8_CC8_INTS_E2AS_Msk       (0x00000001U  << CCU8_CC8_INTS_E2AS_Pos)\r
-\r
-#define   CCU8_CC8_INTS_TRPF_Pos       (11U)\r
-#define   CCU8_CC8_INTS_TRPF_Msk       (0x00000001U  << CCU8_CC8_INTS_TRPF_Pos)\r
-\r
-/* CCU8_CC8_INTE  =  Interrupt Enable Control*/\r
-#define   CCU8_CC8_INTE_PME_Pos        (0U)\r
-#define   CCU8_CC8_INTE_PME_Msk        (0x00000001U  << CCU8_CC8_INTE_PME_Pos)\r
-\r
-#define   CCU8_CC8_INTE_OME_Pos        (1U)\r
-#define   CCU8_CC8_INTE_OME_Msk        (0x00000001U  << CCU8_CC8_INTE_OME_Pos)\r
-\r
-#define   CCU8_CC8_INTE_CMU1E_Pos      (2U)\r
-#define   CCU8_CC8_INTE_CMU1E_Msk      (0x00000001U  << CCU8_CC8_INTE_CMU1E_Pos)\r
-\r
-#define   CCU8_CC8_INTE_CMD1E_Pos      (3U)\r
-#define   CCU8_CC8_INTE_CMD1E_Msk      (0x00000001U  << CCU8_CC8_INTE_CMD1E_Pos)\r
-\r
-#define   CCU8_CC8_INTE_CMU2E_Pos      (4U)\r
-#define   CCU8_CC8_INTE_CMU2E_Msk      (0x00000001U  << CCU8_CC8_INTE_CMU2E_Pos)\r
-\r
-#define   CCU8_CC8_INTE_CMD2E_Pos      (5U)\r
-#define   CCU8_CC8_INTE_CMD2E_Msk      (0x00000001U  << CCU8_CC8_INTE_CMD2E_Pos)\r
-\r
-#define   CCU8_CC8_INTE_E0AE_Pos       (8U)\r
-#define   CCU8_CC8_INTE_E0AE_Msk       (0x00000001U  << CCU8_CC8_INTE_E0AE_Pos)\r
-\r
-#define   CCU8_CC8_INTE_E1AE_Pos       (9U)\r
-#define   CCU8_CC8_INTE_E1AE_Msk       (0x00000001U  << CCU8_CC8_INTE_E1AE_Pos)\r
-\r
-#define   CCU8_CC8_INTE_E2AE_Pos       (10U)\r
-#define   CCU8_CC8_INTE_E2AE_Msk       (0x00000001U  << CCU8_CC8_INTE_E2AE_Pos)\r
-\r
-/* CCU8_CC8_SRS  =  Service Request Selector*/\r
-#define   CCU8_CC8_SRS_POSR_Pos        (0U)\r
-#define   CCU8_CC8_SRS_POSR_Msk        (0x00000003U  << CCU8_CC8_SRS_POSR_Pos)\r
-\r
-#define   CCU8_CC8_SRS_CM1SR_Pos       (2U)\r
-#define   CCU8_CC8_SRS_CM1SR_Msk       (0x00000003U  << CCU8_CC8_SRS_CM1SR_Pos)\r
-\r
-#define   CCU8_CC8_SRS_CM2SR_Pos       (4U)\r
-#define   CCU8_CC8_SRS_CM2SR_Msk       (0x00000003U  << CCU8_CC8_SRS_CM2SR_Pos)\r
-\r
-#define   CCU8_CC8_SRS_E0SR_Pos        (8U)\r
-#define   CCU8_CC8_SRS_E0SR_Msk        (0x00000003U  << CCU8_CC8_SRS_E0SR_Pos)\r
-\r
-#define   CCU8_CC8_SRS_E1SR_Pos        (10U)\r
-#define   CCU8_CC8_SRS_E1SR_Msk        (0x00000003U  << CCU8_CC8_SRS_E1SR_Pos)\r
-\r
-#define   CCU8_CC8_SRS_E2SR_Pos        (12U)\r
-#define   CCU8_CC8_SRS_E2SR_Msk        (0x00000003U  << CCU8_CC8_SRS_E2SR_Pos)\r
-\r
-/* CCU8_CC8_SWS  =  Interrupt Status Set*/\r
-#define   CCU8_CC8_SWS_SPM_Pos         (0U)\r
-#define   CCU8_CC8_SWS_SPM_Msk         (0x00000001U  << CCU8_CC8_SWS_SPM_Pos)\r
-\r
-#define   CCU8_CC8_SWS_SOM_Pos         (1U)\r
-#define   CCU8_CC8_SWS_SOM_Msk         (0x00000001U  << CCU8_CC8_SWS_SOM_Pos)\r
-\r
-#define   CCU8_CC8_SWS_SCM1U_Pos       (2U)\r
-#define   CCU8_CC8_SWS_SCM1U_Msk       (0x00000001U  << CCU8_CC8_SWS_SCM1U_Pos)\r
-\r
-#define   CCU8_CC8_SWS_SCM1D_Pos       (3U)\r
-#define   CCU8_CC8_SWS_SCM1D_Msk       (0x00000001U  << CCU8_CC8_SWS_SCM1D_Pos)\r
-\r
-#define   CCU8_CC8_SWS_SCM2U_Pos       (4U)\r
-#define   CCU8_CC8_SWS_SCM2U_Msk       (0x00000001U  << CCU8_CC8_SWS_SCM2U_Pos)\r
-\r
-#define   CCU8_CC8_SWS_SCM2D_Pos       (5U)\r
-#define   CCU8_CC8_SWS_SCM2D_Msk       (0x00000001U  << CCU8_CC8_SWS_SCM2D_Pos)\r
-\r
-#define   CCU8_CC8_SWS_SE0A_Pos        (8U)\r
-#define   CCU8_CC8_SWS_SE0A_Msk        (0x00000001U  << CCU8_CC8_SWS_SE0A_Pos)\r
-\r
-#define   CCU8_CC8_SWS_SE1A_Pos        (9U)\r
-#define   CCU8_CC8_SWS_SE1A_Msk        (0x00000001U  << CCU8_CC8_SWS_SE1A_Pos)\r
-\r
-#define   CCU8_CC8_SWS_SE2A_Pos        (10U)\r
-#define   CCU8_CC8_SWS_SE2A_Msk        (0x00000001U  << CCU8_CC8_SWS_SE2A_Pos)\r
-\r
-#define   CCU8_CC8_SWS_STRPF_Pos       (11U)\r
-#define   CCU8_CC8_SWS_STRPF_Msk       (0x00000001U  << CCU8_CC8_SWS_STRPF_Pos)\r
-\r
-/* CCU8_CC8_SWR  =  Interrupt Status Clear*/\r
-#define   CCU8_CC8_SWR_RPM_Pos         (0U)\r
-#define   CCU8_CC8_SWR_RPM_Msk         (0x00000001U  << CCU8_CC8_SWR_RPM_Pos)\r
-\r
-#define   CCU8_CC8_SWR_ROM_Pos         (1U)\r
-#define   CCU8_CC8_SWR_ROM_Msk         (0x00000001U  << CCU8_CC8_SWR_ROM_Pos)\r
-\r
-#define   CCU8_CC8_SWR_RCM1U_Pos       (2U)\r
-#define   CCU8_CC8_SWR_RCM1U_Msk       (0x00000001U  << CCU8_CC8_SWR_RCM1U_Pos)\r
-\r
-#define   CCU8_CC8_SWR_RCM1D_Pos       (3U)\r
-#define   CCU8_CC8_SWR_RCM1D_Msk       (0x00000001U  << CCU8_CC8_SWR_RCM1D_Pos)\r
-\r
-#define   CCU8_CC8_SWR_RCM2U_Pos       (4U)\r
-#define   CCU8_CC8_SWR_RCM2U_Msk       (0x00000001U  << CCU8_CC8_SWR_RCM2U_Pos)\r
-\r
-#define   CCU8_CC8_SWR_RCM2D_Pos       (5U)\r
-#define   CCU8_CC8_SWR_RCM2D_Msk       (0x00000001U  << CCU8_CC8_SWR_RCM2D_Pos)\r
-\r
-#define   CCU8_CC8_SWR_RE0A_Pos        (8U)\r
-#define   CCU8_CC8_SWR_RE0A_Msk        (0x00000001U  << CCU8_CC8_SWR_RE0A_Pos)\r
-\r
-#define   CCU8_CC8_SWR_RE1A_Pos        (9U)\r
-#define   CCU8_CC8_SWR_RE1A_Msk        (0x00000001U  << CCU8_CC8_SWR_RE1A_Pos)\r
-\r
-#define   CCU8_CC8_SWR_RE2A_Pos        (10U)\r
-#define   CCU8_CC8_SWR_RE2A_Msk        (0x00000001U  << CCU8_CC8_SWR_RE2A_Pos)\r
-\r
-#define   CCU8_CC8_SWR_RTRPF_Pos       (11U)\r
-#define   CCU8_CC8_SWR_RTRPF_Msk       (0x00000001U  << CCU8_CC8_SWR_RTRPF_Pos)\r
-\r
-\r
-\r
-/***   DAC Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* DAC_ID  =  Module Identification Register*/\r
-#define   DAC_ID_MODR_Pos      (0U)\r
-#define   DAC_ID_MODR_Msk      (0x000000FFU  << DAC_ID_MODR_Pos)\r
-\r
-#define   DAC_ID_MODT_Pos      (8U)\r
-#define   DAC_ID_MODT_Msk      (0x000000FFU  << DAC_ID_MODT_Pos)\r
-\r
-#define   DAC_ID_MODN_Pos      (16U)\r
-#define   DAC_ID_MODN_Msk      (0x0000FFFFU  << DAC_ID_MODN_Pos)\r
-\r
-/* DAC_DAC0CFG0  =  DAC0 Configuration Register 0*/\r
-#define   DAC_DAC0CFG0_FREQ_Pos        (0U)\r
-#define   DAC_DAC0CFG0_FREQ_Msk        (0x000FFFFFU  << DAC_DAC0CFG0_FREQ_Pos)\r
-\r
-#define   DAC_DAC0CFG0_MODE_Pos        (20U)\r
-#define   DAC_DAC0CFG0_MODE_Msk        (0x00000007U  << DAC_DAC0CFG0_MODE_Pos)\r
-\r
-#define   DAC_DAC0CFG0_SIGN_Pos        (23U)\r
-#define   DAC_DAC0CFG0_SIGN_Msk        (0x00000001U  << DAC_DAC0CFG0_SIGN_Pos)\r
-\r
-#define   DAC_DAC0CFG0_FIFOIND_Pos     (24U)\r
-#define   DAC_DAC0CFG0_FIFOIND_Msk     (0x00000003U  << DAC_DAC0CFG0_FIFOIND_Pos)\r
-\r
-#define   DAC_DAC0CFG0_FIFOEMP_Pos     (26U)\r
-#define   DAC_DAC0CFG0_FIFOEMP_Msk     (0x00000001U  << DAC_DAC0CFG0_FIFOEMP_Pos)\r
-\r
-#define   DAC_DAC0CFG0_FIFOFUL_Pos     (27U)\r
-#define   DAC_DAC0CFG0_FIFOFUL_Msk     (0x00000001U  << DAC_DAC0CFG0_FIFOFUL_Pos)\r
-\r
-#define   DAC_DAC0CFG0_SIGNEN_Pos      (29U)\r
-#define   DAC_DAC0CFG0_SIGNEN_Msk      (0x00000001U  << DAC_DAC0CFG0_SIGNEN_Pos)\r
-\r
-#define   DAC_DAC0CFG0_SREN_Pos        (30U)\r
-#define   DAC_DAC0CFG0_SREN_Msk        (0x00000001U  << DAC_DAC0CFG0_SREN_Pos)\r
-\r
-#define   DAC_DAC0CFG0_RUN_Pos         (31U)\r
-#define   DAC_DAC0CFG0_RUN_Msk         (0x00000001U  << DAC_DAC0CFG0_RUN_Pos)\r
-\r
-/* DAC_DAC0CFG1  =  DAC0 Configuration Register 1*/\r
-#define   DAC_DAC0CFG1_SCALE_Pos       (0U)\r
-#define   DAC_DAC0CFG1_SCALE_Msk       (0x00000007U  << DAC_DAC0CFG1_SCALE_Pos)\r
-\r
-#define   DAC_DAC0CFG1_MULDIV_Pos      (3U)\r
-#define   DAC_DAC0CFG1_MULDIV_Msk      (0x00000001U  << DAC_DAC0CFG1_MULDIV_Pos)\r
-\r
-#define   DAC_DAC0CFG1_OFFS_Pos        (4U)\r
-#define   DAC_DAC0CFG1_OFFS_Msk        (0x000000FFU  << DAC_DAC0CFG1_OFFS_Pos)\r
-\r
-#define   DAC_DAC0CFG1_TRIGSEL_Pos     (12U)\r
-#define   DAC_DAC0CFG1_TRIGSEL_Msk     (0x00000007U  << DAC_DAC0CFG1_TRIGSEL_Pos)\r
-\r
-#define   DAC_DAC0CFG1_DATMOD_Pos      (15U)\r
-#define   DAC_DAC0CFG1_DATMOD_Msk      (0x00000001U  << DAC_DAC0CFG1_DATMOD_Pos)\r
-\r
-#define   DAC_DAC0CFG1_SWTRIG_Pos      (16U)\r
-#define   DAC_DAC0CFG1_SWTRIG_Msk      (0x00000001U  << DAC_DAC0CFG1_SWTRIG_Pos)\r
-\r
-#define   DAC_DAC0CFG1_TRIGMOD_Pos     (17U)\r
-#define   DAC_DAC0CFG1_TRIGMOD_Msk     (0x00000003U  << DAC_DAC0CFG1_TRIGMOD_Pos)\r
-\r
-#define   DAC_DAC0CFG1_ANACFG_Pos      (19U)\r
-#define   DAC_DAC0CFG1_ANACFG_Msk      (0x0000001FU  << DAC_DAC0CFG1_ANACFG_Pos)\r
-\r
-#define   DAC_DAC0CFG1_ANAEN_Pos       (24U)\r
-#define   DAC_DAC0CFG1_ANAEN_Msk       (0x00000001U  << DAC_DAC0CFG1_ANAEN_Pos)\r
-\r
-#define   DAC_DAC0CFG1_REFCFGL_Pos     (28U)\r
-#define   DAC_DAC0CFG1_REFCFGL_Msk     (0x0000000FU  << DAC_DAC0CFG1_REFCFGL_Pos)\r
-\r
-/* DAC_DAC1CFG0  =  DAC1 Configuration Register 0*/\r
-#define   DAC_DAC1CFG0_FREQ_Pos        (0U)\r
-#define   DAC_DAC1CFG0_FREQ_Msk        (0x000FFFFFU  << DAC_DAC1CFG0_FREQ_Pos)\r
-\r
-#define   DAC_DAC1CFG0_MODE_Pos        (20U)\r
-#define   DAC_DAC1CFG0_MODE_Msk        (0x00000007U  << DAC_DAC1CFG0_MODE_Pos)\r
-\r
-#define   DAC_DAC1CFG0_SIGN_Pos        (23U)\r
-#define   DAC_DAC1CFG0_SIGN_Msk        (0x00000001U  << DAC_DAC1CFG0_SIGN_Pos)\r
-\r
-#define   DAC_DAC1CFG0_FIFOIND_Pos     (24U)\r
-#define   DAC_DAC1CFG0_FIFOIND_Msk     (0x00000003U  << DAC_DAC1CFG0_FIFOIND_Pos)\r
-\r
-#define   DAC_DAC1CFG0_FIFOEMP_Pos     (26U)\r
-#define   DAC_DAC1CFG0_FIFOEMP_Msk     (0x00000001U  << DAC_DAC1CFG0_FIFOEMP_Pos)\r
-\r
-#define   DAC_DAC1CFG0_FIFOFUL_Pos     (27U)\r
-#define   DAC_DAC1CFG0_FIFOFUL_Msk     (0x00000001U  << DAC_DAC1CFG0_FIFOFUL_Pos)\r
-\r
-#define   DAC_DAC1CFG0_SIGNEN_Pos      (29U)\r
-#define   DAC_DAC1CFG0_SIGNEN_Msk      (0x00000001U  << DAC_DAC1CFG0_SIGNEN_Pos)\r
-\r
-#define   DAC_DAC1CFG0_SREN_Pos        (30U)\r
-#define   DAC_DAC1CFG0_SREN_Msk        (0x00000001U  << DAC_DAC1CFG0_SREN_Pos)\r
-\r
-#define   DAC_DAC1CFG0_RUN_Pos         (31U)\r
-#define   DAC_DAC1CFG0_RUN_Msk         (0x00000001U  << DAC_DAC1CFG0_RUN_Pos)\r
-\r
-/* DAC_DAC1CFG1  =  DAC1 Configuration Register 1*/\r
-#define   DAC_DAC1CFG1_SCALE_Pos       (0U)\r
-#define   DAC_DAC1CFG1_SCALE_Msk       (0x00000007U  << DAC_DAC1CFG1_SCALE_Pos)\r
-\r
-#define   DAC_DAC1CFG1_MULDIV_Pos      (3U)\r
-#define   DAC_DAC1CFG1_MULDIV_Msk      (0x00000001U  << DAC_DAC1CFG1_MULDIV_Pos)\r
-\r
-#define   DAC_DAC1CFG1_OFFS_Pos        (4U)\r
-#define   DAC_DAC1CFG1_OFFS_Msk        (0x000000FFU  << DAC_DAC1CFG1_OFFS_Pos)\r
-\r
-#define   DAC_DAC1CFG1_TRIGSEL_Pos     (12U)\r
-#define   DAC_DAC1CFG1_TRIGSEL_Msk     (0x00000007U  << DAC_DAC1CFG1_TRIGSEL_Pos)\r
-\r
-#define   DAC_DAC1CFG1_SWTRIG_Pos      (16U)\r
-#define   DAC_DAC1CFG1_SWTRIG_Msk      (0x00000001U  << DAC_DAC1CFG1_SWTRIG_Pos)\r
-\r
-#define   DAC_DAC1CFG1_TRIGMOD_Pos     (17U)\r
-#define   DAC_DAC1CFG1_TRIGMOD_Msk     (0x00000003U  << DAC_DAC1CFG1_TRIGMOD_Pos)\r
-\r
-#define   DAC_DAC1CFG1_ANACFG_Pos      (19U)\r
-#define   DAC_DAC1CFG1_ANACFG_Msk      (0x0000001FU  << DAC_DAC1CFG1_ANACFG_Pos)\r
-\r
-#define   DAC_DAC1CFG1_ANAEN_Pos       (24U)\r
-#define   DAC_DAC1CFG1_ANAEN_Msk       (0x00000001U  << DAC_DAC1CFG1_ANAEN_Pos)\r
-\r
-#define   DAC_DAC1CFG1_REFCFGH_Pos     (28U)\r
-#define   DAC_DAC1CFG1_REFCFGH_Msk     (0x0000000FU  << DAC_DAC1CFG1_REFCFGH_Pos)\r
-\r
-/* DAC_DAC0DATA  =  DAC0 Data Register*/\r
-#define   DAC_DAC0DATA_DATA0_Pos       (0U)\r
-#define   DAC_DAC0DATA_DATA0_Msk       (0x00000FFFU  << DAC_DAC0DATA_DATA0_Pos)\r
-\r
-/* DAC_DAC1DATA  =  DAC1 Data Register*/\r
-#define   DAC_DAC1DATA_DATA1_Pos       (0U)\r
-#define   DAC_DAC1DATA_DATA1_Msk       (0x00000FFFU  << DAC_DAC1DATA_DATA1_Pos)\r
-\r
-/* DAC_DAC01DATA  =  DAC01 Data Register*/\r
-#define   DAC_DAC01DATA_DATA0_Pos      (0U)\r
-#define   DAC_DAC01DATA_DATA0_Msk      (0x00000FFFU  << DAC_DAC01DATA_DATA0_Pos)\r
-\r
-#define   DAC_DAC01DATA_DATA1_Pos      (16U)\r
-#define   DAC_DAC01DATA_DATA1_Msk      (0x00000FFFU  << DAC_DAC01DATA_DATA1_Pos)\r
-\r
-/* DAC_DAC0PATL  =  DAC0 Lower Pattern Register*/\r
-#define   DAC_DAC0PATL_PAT0_Pos        (0U)\r
-#define   DAC_DAC0PATL_PAT0_Msk        (0x0000001FU  << DAC_DAC0PATL_PAT0_Pos)\r
-\r
-#define   DAC_DAC0PATL_PAT1_Pos        (5U)\r
-#define   DAC_DAC0PATL_PAT1_Msk        (0x0000001FU  << DAC_DAC0PATL_PAT1_Pos)\r
-\r
-#define   DAC_DAC0PATL_PAT2_Pos        (10U)\r
-#define   DAC_DAC0PATL_PAT2_Msk        (0x0000001FU  << DAC_DAC0PATL_PAT2_Pos)\r
-\r
-#define   DAC_DAC0PATL_PAT3_Pos        (15U)\r
-#define   DAC_DAC0PATL_PAT3_Msk        (0x0000001FU  << DAC_DAC0PATL_PAT3_Pos)\r
-\r
-#define   DAC_DAC0PATL_PAT4_Pos        (20U)\r
-#define   DAC_DAC0PATL_PAT4_Msk        (0x0000001FU  << DAC_DAC0PATL_PAT4_Pos)\r
-\r
-#define   DAC_DAC0PATL_PAT5_Pos        (25U)\r
-#define   DAC_DAC0PATL_PAT5_Msk        (0x0000001FU  << DAC_DAC0PATL_PAT5_Pos)\r
-\r
-/* DAC_DAC0PATH  =  DAC0 Higher Pattern Register*/\r
-#define   DAC_DAC0PATH_PAT6_Pos        (0U)\r
-#define   DAC_DAC0PATH_PAT6_Msk        (0x0000001FU  << DAC_DAC0PATH_PAT6_Pos)\r
-\r
-#define   DAC_DAC0PATH_PAT7_Pos        (5U)\r
-#define   DAC_DAC0PATH_PAT7_Msk        (0x0000001FU  << DAC_DAC0PATH_PAT7_Pos)\r
-\r
-#define   DAC_DAC0PATH_PAT8_Pos        (10U)\r
-#define   DAC_DAC0PATH_PAT8_Msk        (0x0000001FU  << DAC_DAC0PATH_PAT8_Pos)\r
-\r
-/* DAC_DAC1PATL  =  DAC1 Lower Pattern Register*/\r
-#define   DAC_DAC1PATL_PAT0_Pos        (0U)\r
-#define   DAC_DAC1PATL_PAT0_Msk        (0x0000001FU  << DAC_DAC1PATL_PAT0_Pos)\r
-\r
-#define   DAC_DAC1PATL_PAT1_Pos        (5U)\r
-#define   DAC_DAC1PATL_PAT1_Msk        (0x0000001FU  << DAC_DAC1PATL_PAT1_Pos)\r
-\r
-#define   DAC_DAC1PATL_PAT2_Pos        (10U)\r
-#define   DAC_DAC1PATL_PAT2_Msk        (0x0000001FU  << DAC_DAC1PATL_PAT2_Pos)\r
-\r
-#define   DAC_DAC1PATL_PAT3_Pos        (15U)\r
-#define   DAC_DAC1PATL_PAT3_Msk        (0x0000001FU  << DAC_DAC1PATL_PAT3_Pos)\r
-\r
-#define   DAC_DAC1PATL_PAT4_Pos        (20U)\r
-#define   DAC_DAC1PATL_PAT4_Msk        (0x0000001FU  << DAC_DAC1PATL_PAT4_Pos)\r
-\r
-#define   DAC_DAC1PATL_PAT5_Pos        (25U)\r
-#define   DAC_DAC1PATL_PAT5_Msk        (0x0000001FU  << DAC_DAC1PATL_PAT5_Pos)\r
-\r
-/* DAC_DAC1PATH  =  DAC1 Higher Pattern Register*/\r
-#define   DAC_DAC1PATH_PAT6_Pos        (0U)\r
-#define   DAC_DAC1PATH_PAT6_Msk        (0x0000001FU  << DAC_DAC1PATH_PAT6_Pos)\r
-\r
-#define   DAC_DAC1PATH_PAT7_Pos        (5U)\r
-#define   DAC_DAC1PATH_PAT7_Msk        (0x0000001FU  << DAC_DAC1PATH_PAT7_Pos)\r
-\r
-#define   DAC_DAC1PATH_PAT8_Pos        (10U)\r
-#define   DAC_DAC1PATH_PAT8_Msk        (0x0000001FU  << DAC_DAC1PATH_PAT8_Pos)\r
-\r
-\r
-\r
-/***   DLR Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* DLR_OVRSTAT  =  GPDMA Overrun Status*/\r
-#define   DLR_OVRSTAT_LN0_Pos          (0U)\r
-#define   DLR_OVRSTAT_LN0_Msk          (0x00000001U  << DLR_OVRSTAT_LN0_Pos)\r
-\r
-#define   DLR_OVRSTAT_LN1_Pos          (1U)\r
-#define   DLR_OVRSTAT_LN1_Msk          (0x00000001U  << DLR_OVRSTAT_LN1_Pos)\r
-\r
-#define   DLR_OVRSTAT_LN2_Pos          (2U)\r
-#define   DLR_OVRSTAT_LN2_Msk          (0x00000001U  << DLR_OVRSTAT_LN2_Pos)\r
-\r
-#define   DLR_OVRSTAT_LN3_Pos          (3U)\r
-#define   DLR_OVRSTAT_LN3_Msk          (0x00000001U  << DLR_OVRSTAT_LN3_Pos)\r
-\r
-#define   DLR_OVRSTAT_LN4_Pos          (4U)\r
-#define   DLR_OVRSTAT_LN4_Msk          (0x00000001U  << DLR_OVRSTAT_LN4_Pos)\r
-\r
-#define   DLR_OVRSTAT_LN5_Pos          (5U)\r
-#define   DLR_OVRSTAT_LN5_Msk          (0x00000001U  << DLR_OVRSTAT_LN5_Pos)\r
-\r
-#define   DLR_OVRSTAT_LN6_Pos          (6U)\r
-#define   DLR_OVRSTAT_LN6_Msk          (0x00000001U  << DLR_OVRSTAT_LN6_Pos)\r
-\r
-#define   DLR_OVRSTAT_LN7_Pos          (7U)\r
-#define   DLR_OVRSTAT_LN7_Msk          (0x00000001U  << DLR_OVRSTAT_LN7_Pos)\r
-\r
-#define   DLR_OVRSTAT_LN8_Pos          (8U)\r
-#define   DLR_OVRSTAT_LN8_Msk          (0x00000001U  << DLR_OVRSTAT_LN8_Pos)\r
-\r
-#define   DLR_OVRSTAT_LN9_Pos          (9U)\r
-#define   DLR_OVRSTAT_LN9_Msk          (0x00000001U  << DLR_OVRSTAT_LN9_Pos)\r
-\r
-#define   DLR_OVRSTAT_LN10_Pos         (10U)\r
-#define   DLR_OVRSTAT_LN10_Msk         (0x00000001U  << DLR_OVRSTAT_LN10_Pos)\r
-\r
-#define   DLR_OVRSTAT_LN11_Pos         (11U)\r
-#define   DLR_OVRSTAT_LN11_Msk         (0x00000001U  << DLR_OVRSTAT_LN11_Pos)\r
-\r
-/* DLR_OVRCLR  =  GPDMA Overrun Clear*/\r
-#define   DLR_OVRCLR_LN0_Pos   (0U)\r
-#define   DLR_OVRCLR_LN0_Msk   (0x00000001U  << DLR_OVRCLR_LN0_Pos)\r
-\r
-#define   DLR_OVRCLR_LN1_Pos   (1U)\r
-#define   DLR_OVRCLR_LN1_Msk   (0x00000001U  << DLR_OVRCLR_LN1_Pos)\r
-\r
-#define   DLR_OVRCLR_LN2_Pos   (2U)\r
-#define   DLR_OVRCLR_LN2_Msk   (0x00000001U  << DLR_OVRCLR_LN2_Pos)\r
-\r
-#define   DLR_OVRCLR_LN3_Pos   (3U)\r
-#define   DLR_OVRCLR_LN3_Msk   (0x00000001U  << DLR_OVRCLR_LN3_Pos)\r
-\r
-#define   DLR_OVRCLR_LN4_Pos   (4U)\r
-#define   DLR_OVRCLR_LN4_Msk   (0x00000001U  << DLR_OVRCLR_LN4_Pos)\r
-\r
-#define   DLR_OVRCLR_LN5_Pos   (5U)\r
-#define   DLR_OVRCLR_LN5_Msk   (0x00000001U  << DLR_OVRCLR_LN5_Pos)\r
-\r
-#define   DLR_OVRCLR_LN6_Pos   (6U)\r
-#define   DLR_OVRCLR_LN6_Msk   (0x00000001U  << DLR_OVRCLR_LN6_Pos)\r
-\r
-#define   DLR_OVRCLR_LN7_Pos   (7U)\r
-#define   DLR_OVRCLR_LN7_Msk   (0x00000001U  << DLR_OVRCLR_LN7_Pos)\r
-\r
-#define   DLR_OVRCLR_LN8_Pos   (8U)\r
-#define   DLR_OVRCLR_LN8_Msk   (0x00000001U  << DLR_OVRCLR_LN8_Pos)\r
-\r
-#define   DLR_OVRCLR_LN9_Pos   (9U)\r
-#define   DLR_OVRCLR_LN9_Msk   (0x00000001U  << DLR_OVRCLR_LN9_Pos)\r
-\r
-#define   DLR_OVRCLR_LN10_Pos          (10U)\r
-#define   DLR_OVRCLR_LN10_Msk          (0x00000001U  << DLR_OVRCLR_LN10_Pos)\r
-\r
-#define   DLR_OVRCLR_LN11_Pos          (11U)\r
-#define   DLR_OVRCLR_LN11_Msk          (0x00000001U  << DLR_OVRCLR_LN11_Pos)\r
-\r
-/* DLR_SRSEL0  =  GPDMA Service Request Selection 0*/\r
-#define   DLR_SRSEL0_RS0_Pos   (0U)\r
-#define   DLR_SRSEL0_RS0_Msk   (0x0000000FU  << DLR_SRSEL0_RS0_Pos)\r
-\r
-#define   DLR_SRSEL0_RS1_Pos   (4U)\r
-#define   DLR_SRSEL0_RS1_Msk   (0x0000000FU  << DLR_SRSEL0_RS1_Pos)\r
-\r
-#define   DLR_SRSEL0_RS2_Pos   (8U)\r
-#define   DLR_SRSEL0_RS2_Msk   (0x0000000FU  << DLR_SRSEL0_RS2_Pos)\r
-\r
-#define   DLR_SRSEL0_RS3_Pos   (12U)\r
-#define   DLR_SRSEL0_RS3_Msk   (0x0000000FU  << DLR_SRSEL0_RS3_Pos)\r
-\r
-#define   DLR_SRSEL0_RS4_Pos   (16U)\r
-#define   DLR_SRSEL0_RS4_Msk   (0x0000000FU  << DLR_SRSEL0_RS4_Pos)\r
-\r
-#define   DLR_SRSEL0_RS5_Pos   (20U)\r
-#define   DLR_SRSEL0_RS5_Msk   (0x0000000FU  << DLR_SRSEL0_RS5_Pos)\r
-\r
-#define   DLR_SRSEL0_RS6_Pos   (24U)\r
-#define   DLR_SRSEL0_RS6_Msk   (0x0000000FU  << DLR_SRSEL0_RS6_Pos)\r
-\r
-#define   DLR_SRSEL0_RS7_Pos   (28U)\r
-#define   DLR_SRSEL0_RS7_Msk   (0x0000000FU  << DLR_SRSEL0_RS7_Pos)\r
-\r
-/* DLR_SRSEL1  =  GPDMA Service Request Selection 1*/\r
-#define   DLR_SRSEL1_RS8_Pos   (0U)\r
-#define   DLR_SRSEL1_RS8_Msk   (0x0000000FU  << DLR_SRSEL1_RS8_Pos)\r
-\r
-#define   DLR_SRSEL1_RS9_Pos   (4U)\r
-#define   DLR_SRSEL1_RS9_Msk   (0x0000000FU  << DLR_SRSEL1_RS9_Pos)\r
-\r
-#define   DLR_SRSEL1_RS10_Pos          (8U)\r
-#define   DLR_SRSEL1_RS10_Msk          (0x0000000FU  << DLR_SRSEL1_RS10_Pos)\r
-\r
-#define   DLR_SRSEL1_RS11_Pos          (12U)\r
-#define   DLR_SRSEL1_RS11_Msk          (0x0000000FU  << DLR_SRSEL1_RS11_Pos)\r
-\r
-/* DLR_LNEN  =  GPDMA Line Enable*/\r
-#define   DLR_LNEN_LN0_Pos     (0U)\r
-#define   DLR_LNEN_LN0_Msk     (0x00000001U  << DLR_LNEN_LN0_Pos)\r
-\r
-#define   DLR_LNEN_LN1_Pos     (1U)\r
-#define   DLR_LNEN_LN1_Msk     (0x00000001U  << DLR_LNEN_LN1_Pos)\r
-\r
-#define   DLR_LNEN_LN2_Pos     (2U)\r
-#define   DLR_LNEN_LN2_Msk     (0x00000001U  << DLR_LNEN_LN2_Pos)\r
-\r
-#define   DLR_LNEN_LN3_Pos     (3U)\r
-#define   DLR_LNEN_LN3_Msk     (0x00000001U  << DLR_LNEN_LN3_Pos)\r
-\r
-#define   DLR_LNEN_LN4_Pos     (4U)\r
-#define   DLR_LNEN_LN4_Msk     (0x00000001U  << DLR_LNEN_LN4_Pos)\r
-\r
-#define   DLR_LNEN_LN5_Pos     (5U)\r
-#define   DLR_LNEN_LN5_Msk     (0x00000001U  << DLR_LNEN_LN5_Pos)\r
-\r
-#define   DLR_LNEN_LN6_Pos     (6U)\r
-#define   DLR_LNEN_LN6_Msk     (0x00000001U  << DLR_LNEN_LN6_Pos)\r
-\r
-#define   DLR_LNEN_LN7_Pos     (7U)\r
-#define   DLR_LNEN_LN7_Msk     (0x00000001U  << DLR_LNEN_LN7_Pos)\r
-\r
-#define   DLR_LNEN_LN8_Pos     (8U)\r
-#define   DLR_LNEN_LN8_Msk     (0x00000001U  << DLR_LNEN_LN8_Pos)\r
-\r
-#define   DLR_LNEN_LN9_Pos     (9U)\r
-#define   DLR_LNEN_LN9_Msk     (0x00000001U  << DLR_LNEN_LN9_Pos)\r
-\r
-#define   DLR_LNEN_LN10_Pos    (10U)\r
-#define   DLR_LNEN_LN10_Msk    (0x00000001U  << DLR_LNEN_LN10_Pos)\r
-\r
-#define   DLR_LNEN_LN11_Pos    (11U)\r
-#define   DLR_LNEN_LN11_Msk    (0x00000001U  << DLR_LNEN_LN11_Pos)\r
-\r
-\r
-\r
-/***   GPDMA1 Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* GPDMA1_SARx  =  Source Address Register for Channel 0*/\r
-#define   GPDMA1_SAR_SAR_Pos   (0U)\r
-#define   GPDMA1_SAR_SAR_Msk   (0xFFFFFFFFU  << GPDMA1_SAR_SAR_Pos)\r
-\r
-/* GPDMA1_DARx  =  Destination Address Register for Channel 0*/\r
-#define   GPDMA1_DAR_DAR_Pos   (0U)\r
-#define   GPDMA1_DAR_DAR_Msk   (0xFFFFFFFFU  << GPDMA1_DAR_DAR_Pos)\r
-\r
-/* GPDMA1_CH_CTLL  =  Control Register for Channel x Low Word*/\r
-#define   GPDMA1_CH_CTLL_TT_FC_Pos     (20U)\r
-#define   GPDMA1_CH_CTLL_TT_FC_Msk     (0x00000007U  << GPDMA1_CH_CTLL_TT_FC_Pos)\r
-\r
-#define   GPDMA1_CH_CTLL_SRC_MSIZE_Pos         (14U)\r
-#define   GPDMA1_CH_CTLL_SRC_MSIZE_Msk         (0x00000007U  << GPDMA1_CH_CTLL_SRC_MSIZE_Pos)\r
-\r
-#define   GPDMA1_CH_CTLL_DEST_MSIZE_Pos        (11U)\r
-#define   GPDMA1_CH_CTLL_DEST_MSIZE_Msk        (0x00000007U  << GPDMA1_CH_CTLL_DEST_MSIZE_Pos)\r
-\r
-#define   GPDMA1_CH_CTLL_SINC_Pos      (9U)\r
-#define   GPDMA1_CH_CTLL_SINC_Msk      (0x00000003U  << GPDMA1_CH_CTLL_SINC_Pos)\r
-\r
-#define   GPDMA1_CH_CTLL_DINC_Pos      (7U)\r
-#define   GPDMA1_CH_CTLL_DINC_Msk      (0x00000003U  << GPDMA1_CH_CTLL_DINC_Pos)\r
-\r
-#define   GPDMA1_CH_CTLL_SRC_TR_WIDTH_Pos      (4U)\r
-#define   GPDMA1_CH_CTLL_SRC_TR_WIDTH_Msk      (0x00000007U  << GPDMA1_CH_CTLL_SRC_TR_WIDTH_Pos)\r
-\r
-#define   GPDMA1_CH_CTLL_DST_TR_WIDTH_Pos      (1U)\r
-#define   GPDMA1_CH_CTLL_DST_TR_WIDTH_Msk      (0x00000007U  << GPDMA1_CH_CTLL_DST_TR_WIDTH_Pos)\r
-\r
-#define   GPDMA1_CH_CTLL_INT_EN_Pos    (0U)\r
-#define   GPDMA1_CH_CTLL_INT_EN_Msk    (0x00000001U  << GPDMA1_CH_CTLL_INT_EN_Pos)\r
-\r
-/* GPDMA1_CH_CTLH  =  Control Register for Channel x High Word*/\r
-#define   GPDMA1_CH_CTLH_DONE_Pos      (12U)\r
-#define   GPDMA1_CH_CTLH_DONE_Msk      (0x00000001U  << GPDMA1_CH_CTLH_DONE_Pos)\r
-\r
-#define   GPDMA1_CH_CTLH_BLOCK_TS_Pos          (0U)\r
-#define   GPDMA1_CH_CTLH_BLOCK_TS_Msk          (0x00000FFFU  << GPDMA1_CH_CTLH_BLOCK_TS_Pos)\r
-\r
-/* GPDMA1_CH_CFGL  =  Configuration Register for Channel x Low Word*/\r
-#define   GPDMA1_CH_CFGL_MAX_ABRST_Pos         (20U)\r
-#define   GPDMA1_CH_CFGL_MAX_ABRST_Msk         (0x000003FFU  << GPDMA1_CH_CFGL_MAX_ABRST_Pos)\r
-\r
-#define   GPDMA1_CH_CFGL_SRC_HS_POL_Pos        (19U)\r
-#define   GPDMA1_CH_CFGL_SRC_HS_POL_Msk        (0x00000001U  << GPDMA1_CH_CFGL_SRC_HS_POL_Pos)\r
-\r
-#define   GPDMA1_CH_CFGL_DST_HS_POL_Pos        (18U)\r
-#define   GPDMA1_CH_CFGL_DST_HS_POL_Msk        (0x00000001U  << GPDMA1_CH_CFGL_DST_HS_POL_Pos)\r
-\r
-#define   GPDMA1_CH_CFGL_LOCK_B_Pos    (17U)\r
-#define   GPDMA1_CH_CFGL_LOCK_B_Msk    (0x00000001U  << GPDMA1_CH_CFGL_LOCK_B_Pos)\r
-\r
-#define   GPDMA1_CH_CFGL_LOCK_CH_Pos   (16U)\r
-#define   GPDMA1_CH_CFGL_LOCK_CH_Msk   (0x00000001U  << GPDMA1_CH_CFGL_LOCK_CH_Pos)\r
-\r
-#define   GPDMA1_CH_CFGL_LOCK_B_L_Pos          (14U)\r
-#define   GPDMA1_CH_CFGL_LOCK_B_L_Msk          (0x00000003U  << GPDMA1_CH_CFGL_LOCK_B_L_Pos)\r
-\r
-#define   GPDMA1_CH_CFGL_LOCK_CH_L_Pos         (12U)\r
-#define   GPDMA1_CH_CFGL_LOCK_CH_L_Msk         (0x00000003U  << GPDMA1_CH_CFGL_LOCK_CH_L_Pos)\r
-\r
-#define   GPDMA1_CH_CFGL_HS_SEL_SRC_Pos        (11U)\r
-#define   GPDMA1_CH_CFGL_HS_SEL_SRC_Msk        (0x00000001U  << GPDMA1_CH_CFGL_HS_SEL_SRC_Pos)\r
-\r
-#define   GPDMA1_CH_CFGL_HS_SEL_DST_Pos        (10U)\r
-#define   GPDMA1_CH_CFGL_HS_SEL_DST_Msk        (0x00000001U  << GPDMA1_CH_CFGL_HS_SEL_DST_Pos)\r
-\r
-#define   GPDMA1_CH_CFGL_FIFO_EMPTY_Pos        (9U)\r
-#define   GPDMA1_CH_CFGL_FIFO_EMPTY_Msk        (0x00000001U  << GPDMA1_CH_CFGL_FIFO_EMPTY_Pos)\r
-\r
-#define   GPDMA1_CH_CFGL_CH_SUSP_Pos   (8U)\r
-#define   GPDMA1_CH_CFGL_CH_SUSP_Msk   (0x00000001U  << GPDMA1_CH_CFGL_CH_SUSP_Pos)\r
-\r
-#define   GPDMA1_CH_CFGL_CH_PRIOR_Pos          (5U)\r
-#define   GPDMA1_CH_CFGL_CH_PRIOR_Msk          (0x00000007U  << GPDMA1_CH_CFGL_CH_PRIOR_Pos)\r
-\r
-/* GPDMA1_CH_CFGH  =  Configuration Register for Channel x High Word*/\r
-#define   GPDMA1_CH_CFGH_DEST_PER_Pos          (11U)\r
-#define   GPDMA1_CH_CFGH_DEST_PER_Msk          (0x0000000FU  << GPDMA1_CH_CFGH_DEST_PER_Pos)\r
-\r
-#define   GPDMA1_CH_CFGH_SRC_PER_Pos   (7U)\r
-#define   GPDMA1_CH_CFGH_SRC_PER_Msk   (0x0000000FU  << GPDMA1_CH_CFGH_SRC_PER_Pos)\r
-\r
-#define   GPDMA1_CH_CFGH_PROTCTL_Pos   (2U)\r
-#define   GPDMA1_CH_CFGH_PROTCTL_Msk   (0x00000007U  << GPDMA1_CH_CFGH_PROTCTL_Pos)\r
-\r
-#define   GPDMA1_CH_CFGH_FIFO_MODE_Pos         (1U)\r
-#define   GPDMA1_CH_CFGH_FIFO_MODE_Msk         (0x00000001U  << GPDMA1_CH_CFGH_FIFO_MODE_Pos)\r
-\r
-#define   GPDMA1_CH_CFGH_FCMODE_Pos    (0U)\r
-#define   GPDMA1_CH_CFGH_FCMODE_Msk    (0x00000001U  << GPDMA1_CH_CFGH_FCMODE_Pos)\r
-\r
-/* GPDMA1_RAWTFR  =  Raw IntTfr Status*/\r
-#define   GPDMA1_RAWTFR_CH0_Pos        (0U)\r
-#define   GPDMA1_RAWTFR_CH0_Msk        (0x00000001U  << GPDMA1_RAWTFR_CH0_Pos)\r
-\r
-#define   GPDMA1_RAWTFR_CH1_Pos        (1U)\r
-#define   GPDMA1_RAWTFR_CH1_Msk        (0x00000001U  << GPDMA1_RAWTFR_CH1_Pos)\r
-\r
-#define   GPDMA1_RAWTFR_CH2_Pos        (2U)\r
-#define   GPDMA1_RAWTFR_CH2_Msk        (0x00000001U  << GPDMA1_RAWTFR_CH2_Pos)\r
-\r
-#define   GPDMA1_RAWTFR_CH3_Pos        (3U)\r
-#define   GPDMA1_RAWTFR_CH3_Msk        (0x00000001U  << GPDMA1_RAWTFR_CH3_Pos)\r
-\r
-/* GPDMA1_RAWBLOCK  =  Raw IntBlock Status*/\r
-#define   GPDMA1_RAWBLOCK_CH0_Pos      (0U)\r
-#define   GPDMA1_RAWBLOCK_CH0_Msk      (0x00000001U  << GPDMA1_RAWBLOCK_CH0_Pos)\r
-\r
-#define   GPDMA1_RAWBLOCK_CH1_Pos      (1U)\r
-#define   GPDMA1_RAWBLOCK_CH1_Msk      (0x00000001U  << GPDMA1_RAWBLOCK_CH1_Pos)\r
-\r
-#define   GPDMA1_RAWBLOCK_CH2_Pos      (2U)\r
-#define   GPDMA1_RAWBLOCK_CH2_Msk      (0x00000001U  << GPDMA1_RAWBLOCK_CH2_Pos)\r
-\r
-#define   GPDMA1_RAWBLOCK_CH3_Pos      (3U)\r
-#define   GPDMA1_RAWBLOCK_CH3_Msk      (0x00000001U  << GPDMA1_RAWBLOCK_CH3_Pos)\r
-\r
-/* GPDMA1_RAWSRCTRAN  =  Raw IntSrcTran Status*/\r
-#define   GPDMA1_RAWSRCTRAN_CH0_Pos    (0U)\r
-#define   GPDMA1_RAWSRCTRAN_CH0_Msk    (0x00000001U  << GPDMA1_RAWSRCTRAN_CH0_Pos)\r
-\r
-#define   GPDMA1_RAWSRCTRAN_CH1_Pos    (1U)\r
-#define   GPDMA1_RAWSRCTRAN_CH1_Msk    (0x00000001U  << GPDMA1_RAWSRCTRAN_CH1_Pos)\r
-\r
-#define   GPDMA1_RAWSRCTRAN_CH2_Pos    (2U)\r
-#define   GPDMA1_RAWSRCTRAN_CH2_Msk    (0x00000001U  << GPDMA1_RAWSRCTRAN_CH2_Pos)\r
-\r
-#define   GPDMA1_RAWSRCTRAN_CH3_Pos    (3U)\r
-#define   GPDMA1_RAWSRCTRAN_CH3_Msk    (0x00000001U  << GPDMA1_RAWSRCTRAN_CH3_Pos)\r
-\r
-/* GPDMA1_RAWDSTTRAN  =  Raw IntBlock Status*/\r
-#define   GPDMA1_RAWDSTTRAN_CH0_Pos    (0U)\r
-#define   GPDMA1_RAWDSTTRAN_CH0_Msk    (0x00000001U  << GPDMA1_RAWDSTTRAN_CH0_Pos)\r
-\r
-#define   GPDMA1_RAWDSTTRAN_CH1_Pos    (1U)\r
-#define   GPDMA1_RAWDSTTRAN_CH1_Msk    (0x00000001U  << GPDMA1_RAWDSTTRAN_CH1_Pos)\r
-\r
-#define   GPDMA1_RAWDSTTRAN_CH2_Pos    (2U)\r
-#define   GPDMA1_RAWDSTTRAN_CH2_Msk    (0x00000001U  << GPDMA1_RAWDSTTRAN_CH2_Pos)\r
-\r
-#define   GPDMA1_RAWDSTTRAN_CH3_Pos    (3U)\r
-#define   GPDMA1_RAWDSTTRAN_CH3_Msk    (0x00000001U  << GPDMA1_RAWDSTTRAN_CH3_Pos)\r
-\r
-/* GPDMA1_RAWERR  =  Raw IntErr Status*/\r
-#define   GPDMA1_RAWERR_CH0_Pos        (0U)\r
-#define   GPDMA1_RAWERR_CH0_Msk        (0x00000001U  << GPDMA1_RAWERR_CH0_Pos)\r
-\r
-#define   GPDMA1_RAWERR_CH1_Pos        (1U)\r
-#define   GPDMA1_RAWERR_CH1_Msk        (0x00000001U  << GPDMA1_RAWERR_CH1_Pos)\r
-\r
-#define   GPDMA1_RAWERR_CH2_Pos        (2U)\r
-#define   GPDMA1_RAWERR_CH2_Msk        (0x00000001U  << GPDMA1_RAWERR_CH2_Pos)\r
-\r
-#define   GPDMA1_RAWERR_CH3_Pos        (3U)\r
-#define   GPDMA1_RAWERR_CH3_Msk        (0x00000001U  << GPDMA1_RAWERR_CH3_Pos)\r
-\r
-/* GPDMA1_STATUSTFR  =  IntTfr Status*/\r
-#define   GPDMA1_STATUSTFR_CH0_Pos     (0U)\r
-#define   GPDMA1_STATUSTFR_CH0_Msk     (0x00000001U  << GPDMA1_STATUSTFR_CH0_Pos)\r
-\r
-#define   GPDMA1_STATUSTFR_CH1_Pos     (1U)\r
-#define   GPDMA1_STATUSTFR_CH1_Msk     (0x00000001U  << GPDMA1_STATUSTFR_CH1_Pos)\r
-\r
-#define   GPDMA1_STATUSTFR_CH2_Pos     (2U)\r
-#define   GPDMA1_STATUSTFR_CH2_Msk     (0x00000001U  << GPDMA1_STATUSTFR_CH2_Pos)\r
-\r
-#define   GPDMA1_STATUSTFR_CH3_Pos     (3U)\r
-#define   GPDMA1_STATUSTFR_CH3_Msk     (0x00000001U  << GPDMA1_STATUSTFR_CH3_Pos)\r
-\r
-/* GPDMA1_STATUSBLOCK  =  IntBlock Status*/\r
-#define   GPDMA1_STATUSBLOCK_CH0_Pos   (0U)\r
-#define   GPDMA1_STATUSBLOCK_CH0_Msk   (0x00000001U  << GPDMA1_STATUSBLOCK_CH0_Pos)\r
-\r
-#define   GPDMA1_STATUSBLOCK_CH1_Pos   (1U)\r
-#define   GPDMA1_STATUSBLOCK_CH1_Msk   (0x00000001U  << GPDMA1_STATUSBLOCK_CH1_Pos)\r
-\r
-#define   GPDMA1_STATUSBLOCK_CH2_Pos   (2U)\r
-#define   GPDMA1_STATUSBLOCK_CH2_Msk   (0x00000001U  << GPDMA1_STATUSBLOCK_CH2_Pos)\r
-\r
-#define   GPDMA1_STATUSBLOCK_CH3_Pos   (3U)\r
-#define   GPDMA1_STATUSBLOCK_CH3_Msk   (0x00000001U  << GPDMA1_STATUSBLOCK_CH3_Pos)\r
-\r
-/* GPDMA1_STATUSSRCTRAN  =  IntSrcTran Status*/\r
-#define   GPDMA1_STATUSSRCTRAN_CH0_Pos         (0U)\r
-#define   GPDMA1_STATUSSRCTRAN_CH0_Msk         (0x00000001U  << GPDMA1_STATUSSRCTRAN_CH0_Pos)\r
-\r
-#define   GPDMA1_STATUSSRCTRAN_CH1_Pos         (1U)\r
-#define   GPDMA1_STATUSSRCTRAN_CH1_Msk         (0x00000001U  << GPDMA1_STATUSSRCTRAN_CH1_Pos)\r
-\r
-#define   GPDMA1_STATUSSRCTRAN_CH2_Pos         (2U)\r
-#define   GPDMA1_STATUSSRCTRAN_CH2_Msk         (0x00000001U  << GPDMA1_STATUSSRCTRAN_CH2_Pos)\r
-\r
-#define   GPDMA1_STATUSSRCTRAN_CH3_Pos         (3U)\r
-#define   GPDMA1_STATUSSRCTRAN_CH3_Msk         (0x00000001U  << GPDMA1_STATUSSRCTRAN_CH3_Pos)\r
-\r
-/* GPDMA1_STATUSDSTTRAN  =  IntBlock Status*/\r
-#define   GPDMA1_STATUSDSTTRAN_CH0_Pos         (0U)\r
-#define   GPDMA1_STATUSDSTTRAN_CH0_Msk         (0x00000001U  << GPDMA1_STATUSDSTTRAN_CH0_Pos)\r
-\r
-#define   GPDMA1_STATUSDSTTRAN_CH1_Pos         (1U)\r
-#define   GPDMA1_STATUSDSTTRAN_CH1_Msk         (0x00000001U  << GPDMA1_STATUSDSTTRAN_CH1_Pos)\r
-\r
-#define   GPDMA1_STATUSDSTTRAN_CH2_Pos         (2U)\r
-#define   GPDMA1_STATUSDSTTRAN_CH2_Msk         (0x00000001U  << GPDMA1_STATUSDSTTRAN_CH2_Pos)\r
-\r
-#define   GPDMA1_STATUSDSTTRAN_CH3_Pos         (3U)\r
-#define   GPDMA1_STATUSDSTTRAN_CH3_Msk         (0x00000001U  << GPDMA1_STATUSDSTTRAN_CH3_Pos)\r
-\r
-/* GPDMA1_STATUSERR  =  IntErr Status*/\r
-#define   GPDMA1_STATUSERR_CH0_Pos     (0U)\r
-#define   GPDMA1_STATUSERR_CH0_Msk     (0x00000001U  << GPDMA1_STATUSERR_CH0_Pos)\r
-\r
-#define   GPDMA1_STATUSERR_CH1_Pos     (1U)\r
-#define   GPDMA1_STATUSERR_CH1_Msk     (0x00000001U  << GPDMA1_STATUSERR_CH1_Pos)\r
-\r
-#define   GPDMA1_STATUSERR_CH2_Pos     (2U)\r
-#define   GPDMA1_STATUSERR_CH2_Msk     (0x00000001U  << GPDMA1_STATUSERR_CH2_Pos)\r
-\r
-#define   GPDMA1_STATUSERR_CH3_Pos     (3U)\r
-#define   GPDMA1_STATUSERR_CH3_Msk     (0x00000001U  << GPDMA1_STATUSERR_CH3_Pos)\r
-\r
-/* GPDMA1_MASKTFR  =  Mask for Raw IntTfr Status*/\r
-#define   GPDMA1_MASKTFR_WE_CH0_Pos    (8U)\r
-#define   GPDMA1_MASKTFR_WE_CH0_Msk    (0x00000001U  << GPDMA1_MASKTFR_WE_CH0_Pos)\r
-\r
-#define   GPDMA1_MASKTFR_WE_CH1_Pos    (9U)\r
-#define   GPDMA1_MASKTFR_WE_CH1_Msk    (0x00000001U  << GPDMA1_MASKTFR_WE_CH1_Pos)\r
-\r
-#define   GPDMA1_MASKTFR_WE_CH2_Pos    (10U)\r
-#define   GPDMA1_MASKTFR_WE_CH2_Msk    (0x00000001U  << GPDMA1_MASKTFR_WE_CH2_Pos)\r
-\r
-#define   GPDMA1_MASKTFR_WE_CH3_Pos    (11U)\r
-#define   GPDMA1_MASKTFR_WE_CH3_Msk    (0x00000001U  << GPDMA1_MASKTFR_WE_CH3_Pos)\r
-\r
-#define   GPDMA1_MASKTFR_CH0_Pos       (0U)\r
-#define   GPDMA1_MASKTFR_CH0_Msk       (0x00000001U  << GPDMA1_MASKTFR_CH0_Pos)\r
-\r
-#define   GPDMA1_MASKTFR_CH1_Pos       (1U)\r
-#define   GPDMA1_MASKTFR_CH1_Msk       (0x00000001U  << GPDMA1_MASKTFR_CH1_Pos)\r
-\r
-#define   GPDMA1_MASKTFR_CH2_Pos       (2U)\r
-#define   GPDMA1_MASKTFR_CH2_Msk       (0x00000001U  << GPDMA1_MASKTFR_CH2_Pos)\r
-\r
-#define   GPDMA1_MASKTFR_CH3_Pos       (3U)\r
-#define   GPDMA1_MASKTFR_CH3_Msk       (0x00000001U  << GPDMA1_MASKTFR_CH3_Pos)\r
-\r
-/* GPDMA1_MASKBLOCK  =  Mask for Raw IntBlock Status*/\r
-#define   GPDMA1_MASKBLOCK_WE_CH0_Pos          (8U)\r
-#define   GPDMA1_MASKBLOCK_WE_CH0_Msk          (0x00000001U  << GPDMA1_MASKBLOCK_WE_CH0_Pos)\r
-\r
-#define   GPDMA1_MASKBLOCK_WE_CH1_Pos          (9U)\r
-#define   GPDMA1_MASKBLOCK_WE_CH1_Msk          (0x00000001U  << GPDMA1_MASKBLOCK_WE_CH1_Pos)\r
-\r
-#define   GPDMA1_MASKBLOCK_WE_CH2_Pos          (10U)\r
-#define   GPDMA1_MASKBLOCK_WE_CH2_Msk          (0x00000001U  << GPDMA1_MASKBLOCK_WE_CH2_Pos)\r
-\r
-#define   GPDMA1_MASKBLOCK_WE_CH3_Pos          (11U)\r
-#define   GPDMA1_MASKBLOCK_WE_CH3_Msk          (0x00000001U  << GPDMA1_MASKBLOCK_WE_CH3_Pos)\r
-\r
-#define   GPDMA1_MASKBLOCK_CH0_Pos     (0U)\r
-#define   GPDMA1_MASKBLOCK_CH0_Msk     (0x00000001U  << GPDMA1_MASKBLOCK_CH0_Pos)\r
-\r
-#define   GPDMA1_MASKBLOCK_CH1_Pos     (1U)\r
-#define   GPDMA1_MASKBLOCK_CH1_Msk     (0x00000001U  << GPDMA1_MASKBLOCK_CH1_Pos)\r
-\r
-#define   GPDMA1_MASKBLOCK_CH2_Pos     (2U)\r
-#define   GPDMA1_MASKBLOCK_CH2_Msk     (0x00000001U  << GPDMA1_MASKBLOCK_CH2_Pos)\r
-\r
-#define   GPDMA1_MASKBLOCK_CH3_Pos     (3U)\r
-#define   GPDMA1_MASKBLOCK_CH3_Msk     (0x00000001U  << GPDMA1_MASKBLOCK_CH3_Pos)\r
-\r
-/* GPDMA1_MASKSRCTRAN  =  Mask for Raw IntSrcTran Status*/\r
-#define   GPDMA1_MASKSRCTRAN_WE_CH0_Pos        (8U)\r
-#define   GPDMA1_MASKSRCTRAN_WE_CH0_Msk        (0x00000001U  << GPDMA1_MASKSRCTRAN_WE_CH0_Pos)\r
-\r
-#define   GPDMA1_MASKSRCTRAN_WE_CH1_Pos        (9U)\r
-#define   GPDMA1_MASKSRCTRAN_WE_CH1_Msk        (0x00000001U  << GPDMA1_MASKSRCTRAN_WE_CH1_Pos)\r
-\r
-#define   GPDMA1_MASKSRCTRAN_WE_CH2_Pos        (10U)\r
-#define   GPDMA1_MASKSRCTRAN_WE_CH2_Msk        (0x00000001U  << GPDMA1_MASKSRCTRAN_WE_CH2_Pos)\r
-\r
-#define   GPDMA1_MASKSRCTRAN_WE_CH3_Pos        (11U)\r
-#define   GPDMA1_MASKSRCTRAN_WE_CH3_Msk        (0x00000001U  << GPDMA1_MASKSRCTRAN_WE_CH3_Pos)\r
-\r
-#define   GPDMA1_MASKSRCTRAN_CH0_Pos   (0U)\r
-#define   GPDMA1_MASKSRCTRAN_CH0_Msk   (0x00000001U  << GPDMA1_MASKSRCTRAN_CH0_Pos)\r
-\r
-#define   GPDMA1_MASKSRCTRAN_CH1_Pos   (1U)\r
-#define   GPDMA1_MASKSRCTRAN_CH1_Msk   (0x00000001U  << GPDMA1_MASKSRCTRAN_CH1_Pos)\r
-\r
-#define   GPDMA1_MASKSRCTRAN_CH2_Pos   (2U)\r
-#define   GPDMA1_MASKSRCTRAN_CH2_Msk   (0x00000001U  << GPDMA1_MASKSRCTRAN_CH2_Pos)\r
-\r
-#define   GPDMA1_MASKSRCTRAN_CH3_Pos   (3U)\r
-#define   GPDMA1_MASKSRCTRAN_CH3_Msk   (0x00000001U  << GPDMA1_MASKSRCTRAN_CH3_Pos)\r
-\r
-/* GPDMA1_MASKDSTTRAN  =  Mask for Raw IntBlock Status*/\r
-#define   GPDMA1_MASKDSTTRAN_WE_CH0_Pos        (8U)\r
-#define   GPDMA1_MASKDSTTRAN_WE_CH0_Msk        (0x00000001U  << GPDMA1_MASKDSTTRAN_WE_CH0_Pos)\r
-\r
-#define   GPDMA1_MASKDSTTRAN_WE_CH1_Pos        (9U)\r
-#define   GPDMA1_MASKDSTTRAN_WE_CH1_Msk        (0x00000001U  << GPDMA1_MASKDSTTRAN_WE_CH1_Pos)\r
-\r
-#define   GPDMA1_MASKDSTTRAN_WE_CH2_Pos        (10U)\r
-#define   GPDMA1_MASKDSTTRAN_WE_CH2_Msk        (0x00000001U  << GPDMA1_MASKDSTTRAN_WE_CH2_Pos)\r
-\r
-#define   GPDMA1_MASKDSTTRAN_WE_CH3_Pos        (11U)\r
-#define   GPDMA1_MASKDSTTRAN_WE_CH3_Msk        (0x00000001U  << GPDMA1_MASKDSTTRAN_WE_CH3_Pos)\r
-\r
-#define   GPDMA1_MASKDSTTRAN_CH0_Pos   (0U)\r
-#define   GPDMA1_MASKDSTTRAN_CH0_Msk   (0x00000001U  << GPDMA1_MASKDSTTRAN_CH0_Pos)\r
-\r
-#define   GPDMA1_MASKDSTTRAN_CH1_Pos   (1U)\r
-#define   GPDMA1_MASKDSTTRAN_CH1_Msk   (0x00000001U  << GPDMA1_MASKDSTTRAN_CH1_Pos)\r
-\r
-#define   GPDMA1_MASKDSTTRAN_CH2_Pos   (2U)\r
-#define   GPDMA1_MASKDSTTRAN_CH2_Msk   (0x00000001U  << GPDMA1_MASKDSTTRAN_CH2_Pos)\r
-\r
-#define   GPDMA1_MASKDSTTRAN_CH3_Pos   (3U)\r
-#define   GPDMA1_MASKDSTTRAN_CH3_Msk   (0x00000001U  << GPDMA1_MASKDSTTRAN_CH3_Pos)\r
-\r
-/* GPDMA1_MASKERR  =  Mask for Raw IntErr Status*/\r
-#define   GPDMA1_MASKERR_WE_CH0_Pos    (8U)\r
-#define   GPDMA1_MASKERR_WE_CH0_Msk    (0x00000001U  << GPDMA1_MASKERR_WE_CH0_Pos)\r
-\r
-#define   GPDMA1_MASKERR_WE_CH1_Pos    (9U)\r
-#define   GPDMA1_MASKERR_WE_CH1_Msk    (0x00000001U  << GPDMA1_MASKERR_WE_CH1_Pos)\r
-\r
-#define   GPDMA1_MASKERR_WE_CH2_Pos    (10U)\r
-#define   GPDMA1_MASKERR_WE_CH2_Msk    (0x00000001U  << GPDMA1_MASKERR_WE_CH2_Pos)\r
-\r
-#define   GPDMA1_MASKERR_WE_CH3_Pos    (11U)\r
-#define   GPDMA1_MASKERR_WE_CH3_Msk    (0x00000001U  << GPDMA1_MASKERR_WE_CH3_Pos)\r
-\r
-#define   GPDMA1_MASKERR_CH0_Pos       (0U)\r
-#define   GPDMA1_MASKERR_CH0_Msk       (0x00000001U  << GPDMA1_MASKERR_CH0_Pos)\r
-\r
-#define   GPDMA1_MASKERR_CH1_Pos       (1U)\r
-#define   GPDMA1_MASKERR_CH1_Msk       (0x00000001U  << GPDMA1_MASKERR_CH1_Pos)\r
-\r
-#define   GPDMA1_MASKERR_CH2_Pos       (2U)\r
-#define   GPDMA1_MASKERR_CH2_Msk       (0x00000001U  << GPDMA1_MASKERR_CH2_Pos)\r
-\r
-#define   GPDMA1_MASKERR_CH3_Pos       (3U)\r
-#define   GPDMA1_MASKERR_CH3_Msk       (0x00000001U  << GPDMA1_MASKERR_CH3_Pos)\r
-\r
-/* GPDMA1_CLEARTFR  =  IntTfr Status*/\r
-#define   GPDMA1_CLEARTFR_CH0_Pos      (0U)\r
-#define   GPDMA1_CLEARTFR_CH0_Msk      (0x00000001U  << GPDMA1_CLEARTFR_CH0_Pos)\r
-\r
-#define   GPDMA1_CLEARTFR_CH1_Pos      (1U)\r
-#define   GPDMA1_CLEARTFR_CH1_Msk      (0x00000001U  << GPDMA1_CLEARTFR_CH1_Pos)\r
-\r
-#define   GPDMA1_CLEARTFR_CH2_Pos      (2U)\r
-#define   GPDMA1_CLEARTFR_CH2_Msk      (0x00000001U  << GPDMA1_CLEARTFR_CH2_Pos)\r
-\r
-#define   GPDMA1_CLEARTFR_CH3_Pos      (3U)\r
-#define   GPDMA1_CLEARTFR_CH3_Msk      (0x00000001U  << GPDMA1_CLEARTFR_CH3_Pos)\r
-\r
-/* GPDMA1_CLEARBLOCK  =  IntBlock Status*/\r
-#define   GPDMA1_CLEARBLOCK_CH0_Pos    (0U)\r
-#define   GPDMA1_CLEARBLOCK_CH0_Msk    (0x00000001U  << GPDMA1_CLEARBLOCK_CH0_Pos)\r
-\r
-#define   GPDMA1_CLEARBLOCK_CH1_Pos    (1U)\r
-#define   GPDMA1_CLEARBLOCK_CH1_Msk    (0x00000001U  << GPDMA1_CLEARBLOCK_CH1_Pos)\r
-\r
-#define   GPDMA1_CLEARBLOCK_CH2_Pos    (2U)\r
-#define   GPDMA1_CLEARBLOCK_CH2_Msk    (0x00000001U  << GPDMA1_CLEARBLOCK_CH2_Pos)\r
-\r
-#define   GPDMA1_CLEARBLOCK_CH3_Pos    (3U)\r
-#define   GPDMA1_CLEARBLOCK_CH3_Msk    (0x00000001U  << GPDMA1_CLEARBLOCK_CH3_Pos)\r
-\r
-/* GPDMA1_CLEARSRCTRAN  =  IntSrcTran Status*/\r
-#define   GPDMA1_CLEARSRCTRAN_CH0_Pos          (0U)\r
-#define   GPDMA1_CLEARSRCTRAN_CH0_Msk          (0x00000001U  << GPDMA1_CLEARSRCTRAN_CH0_Pos)\r
-\r
-#define   GPDMA1_CLEARSRCTRAN_CH1_Pos          (1U)\r
-#define   GPDMA1_CLEARSRCTRAN_CH1_Msk          (0x00000001U  << GPDMA1_CLEARSRCTRAN_CH1_Pos)\r
-\r
-#define   GPDMA1_CLEARSRCTRAN_CH2_Pos          (2U)\r
-#define   GPDMA1_CLEARSRCTRAN_CH2_Msk          (0x00000001U  << GPDMA1_CLEARSRCTRAN_CH2_Pos)\r
-\r
-#define   GPDMA1_CLEARSRCTRAN_CH3_Pos          (3U)\r
-#define   GPDMA1_CLEARSRCTRAN_CH3_Msk          (0x00000001U  << GPDMA1_CLEARSRCTRAN_CH3_Pos)\r
-\r
-/* GPDMA1_CLEARDSTTRAN  =  IntBlock Status*/\r
-#define   GPDMA1_CLEARDSTTRAN_CH0_Pos          (0U)\r
-#define   GPDMA1_CLEARDSTTRAN_CH0_Msk          (0x00000001U  << GPDMA1_CLEARDSTTRAN_CH0_Pos)\r
-\r
-#define   GPDMA1_CLEARDSTTRAN_CH1_Pos          (1U)\r
-#define   GPDMA1_CLEARDSTTRAN_CH1_Msk          (0x00000001U  << GPDMA1_CLEARDSTTRAN_CH1_Pos)\r
-\r
-#define   GPDMA1_CLEARDSTTRAN_CH2_Pos          (2U)\r
-#define   GPDMA1_CLEARDSTTRAN_CH2_Msk          (0x00000001U  << GPDMA1_CLEARDSTTRAN_CH2_Pos)\r
-\r
-#define   GPDMA1_CLEARDSTTRAN_CH3_Pos          (3U)\r
-#define   GPDMA1_CLEARDSTTRAN_CH3_Msk          (0x00000001U  << GPDMA1_CLEARDSTTRAN_CH3_Pos)\r
-\r
-/* GPDMA1_CLEARERR  =  IntErr Status*/\r
-#define   GPDMA1_CLEARERR_CH0_Pos      (0U)\r
-#define   GPDMA1_CLEARERR_CH0_Msk      (0x00000001U  << GPDMA1_CLEARERR_CH0_Pos)\r
-\r
-#define   GPDMA1_CLEARERR_CH1_Pos      (1U)\r
-#define   GPDMA1_CLEARERR_CH1_Msk      (0x00000001U  << GPDMA1_CLEARERR_CH1_Pos)\r
-\r
-#define   GPDMA1_CLEARERR_CH2_Pos      (2U)\r
-#define   GPDMA1_CLEARERR_CH2_Msk      (0x00000001U  << GPDMA1_CLEARERR_CH2_Pos)\r
-\r
-#define   GPDMA1_CLEARERR_CH3_Pos      (3U)\r
-#define   GPDMA1_CLEARERR_CH3_Msk      (0x00000001U  << GPDMA1_CLEARERR_CH3_Pos)\r
-\r
-/* GPDMA1_STATUSINT  =  Combined Interrupt Status Register*/\r
-#define   GPDMA1_STATUSINT_ERR_Pos     (4U)\r
-#define   GPDMA1_STATUSINT_ERR_Msk     (0x00000001U  << GPDMA1_STATUSINT_ERR_Pos)\r
-\r
-#define   GPDMA1_STATUSINT_DSTT_Pos    (3U)\r
-#define   GPDMA1_STATUSINT_DSTT_Msk    (0x00000001U  << GPDMA1_STATUSINT_DSTT_Pos)\r
-\r
-#define   GPDMA1_STATUSINT_SRCT_Pos    (2U)\r
-#define   GPDMA1_STATUSINT_SRCT_Msk    (0x00000001U  << GPDMA1_STATUSINT_SRCT_Pos)\r
-\r
-#define   GPDMA1_STATUSINT_BLOCK_Pos   (1U)\r
-#define   GPDMA1_STATUSINT_BLOCK_Msk   (0x00000001U  << GPDMA1_STATUSINT_BLOCK_Pos)\r
-\r
-#define   GPDMA1_STATUSINT_TFR_Pos     (0U)\r
-#define   GPDMA1_STATUSINT_TFR_Msk     (0x00000001U  << GPDMA1_STATUSINT_TFR_Pos)\r
-\r
-/* GPDMA1_REQSRCREG  =  Source Software Transaction Request Register*/\r
-#define   GPDMA1_REQSRCREG_WE_CH0_Pos          (8U)\r
-#define   GPDMA1_REQSRCREG_WE_CH0_Msk          (0x00000001U  << GPDMA1_REQSRCREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA1_REQSRCREG_WE_CH1_Pos          (9U)\r
-#define   GPDMA1_REQSRCREG_WE_CH1_Msk          (0x00000001U  << GPDMA1_REQSRCREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA1_REQSRCREG_WE_CH2_Pos          (10U)\r
-#define   GPDMA1_REQSRCREG_WE_CH2_Msk          (0x00000001U  << GPDMA1_REQSRCREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA1_REQSRCREG_WE_CH3_Pos          (11U)\r
-#define   GPDMA1_REQSRCREG_WE_CH3_Msk          (0x00000001U  << GPDMA1_REQSRCREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA1_REQSRCREG_CH0_Pos     (0U)\r
-#define   GPDMA1_REQSRCREG_CH0_Msk     (0x00000001U  << GPDMA1_REQSRCREG_CH0_Pos)\r
-\r
-#define   GPDMA1_REQSRCREG_CH1_Pos     (1U)\r
-#define   GPDMA1_REQSRCREG_CH1_Msk     (0x00000001U  << GPDMA1_REQSRCREG_CH1_Pos)\r
-\r
-#define   GPDMA1_REQSRCREG_CH2_Pos     (2U)\r
-#define   GPDMA1_REQSRCREG_CH2_Msk     (0x00000001U  << GPDMA1_REQSRCREG_CH2_Pos)\r
-\r
-#define   GPDMA1_REQSRCREG_CH3_Pos     (3U)\r
-#define   GPDMA1_REQSRCREG_CH3_Msk     (0x00000001U  << GPDMA1_REQSRCREG_CH3_Pos)\r
-\r
-/* GPDMA1_REQDSTREG  =  Destination Software Transaction Request Register*/\r
-#define   GPDMA1_REQDSTREG_WE_CH0_Pos          (8U)\r
-#define   GPDMA1_REQDSTREG_WE_CH0_Msk          (0x00000001U  << GPDMA1_REQDSTREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA1_REQDSTREG_WE_CH1_Pos          (9U)\r
-#define   GPDMA1_REQDSTREG_WE_CH1_Msk          (0x00000001U  << GPDMA1_REQDSTREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA1_REQDSTREG_WE_CH2_Pos          (10U)\r
-#define   GPDMA1_REQDSTREG_WE_CH2_Msk          (0x00000001U  << GPDMA1_REQDSTREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA1_REQDSTREG_WE_CH3_Pos          (11U)\r
-#define   GPDMA1_REQDSTREG_WE_CH3_Msk          (0x00000001U  << GPDMA1_REQDSTREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA1_REQDSTREG_CH0_Pos     (0U)\r
-#define   GPDMA1_REQDSTREG_CH0_Msk     (0x00000001U  << GPDMA1_REQDSTREG_CH0_Pos)\r
-\r
-#define   GPDMA1_REQDSTREG_CH1_Pos     (1U)\r
-#define   GPDMA1_REQDSTREG_CH1_Msk     (0x00000001U  << GPDMA1_REQDSTREG_CH1_Pos)\r
-\r
-#define   GPDMA1_REQDSTREG_CH2_Pos     (2U)\r
-#define   GPDMA1_REQDSTREG_CH2_Msk     (0x00000001U  << GPDMA1_REQDSTREG_CH2_Pos)\r
-\r
-#define   GPDMA1_REQDSTREG_CH3_Pos     (3U)\r
-#define   GPDMA1_REQDSTREG_CH3_Msk     (0x00000001U  << GPDMA1_REQDSTREG_CH3_Pos)\r
-\r
-/* GPDMA1_SGLREQSRCREG  =  Single Source Transaction Request Register*/\r
-#define   GPDMA1_SGLREQSRCREG_WE_CH0_Pos       (8U)\r
-#define   GPDMA1_SGLREQSRCREG_WE_CH0_Msk       (0x00000001U  << GPDMA1_SGLREQSRCREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA1_SGLREQSRCREG_WE_CH1_Pos       (9U)\r
-#define   GPDMA1_SGLREQSRCREG_WE_CH1_Msk       (0x00000001U  << GPDMA1_SGLREQSRCREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA1_SGLREQSRCREG_WE_CH2_Pos       (10U)\r
-#define   GPDMA1_SGLREQSRCREG_WE_CH2_Msk       (0x00000001U  << GPDMA1_SGLREQSRCREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA1_SGLREQSRCREG_WE_CH3_Pos       (11U)\r
-#define   GPDMA1_SGLREQSRCREG_WE_CH3_Msk       (0x00000001U  << GPDMA1_SGLREQSRCREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA1_SGLREQSRCREG_CH0_Pos          (0U)\r
-#define   GPDMA1_SGLREQSRCREG_CH0_Msk          (0x00000001U  << GPDMA1_SGLREQSRCREG_CH0_Pos)\r
-\r
-#define   GPDMA1_SGLREQSRCREG_CH1_Pos          (1U)\r
-#define   GPDMA1_SGLREQSRCREG_CH1_Msk          (0x00000001U  << GPDMA1_SGLREQSRCREG_CH1_Pos)\r
-\r
-#define   GPDMA1_SGLREQSRCREG_CH2_Pos          (2U)\r
-#define   GPDMA1_SGLREQSRCREG_CH2_Msk          (0x00000001U  << GPDMA1_SGLREQSRCREG_CH2_Pos)\r
-\r
-#define   GPDMA1_SGLREQSRCREG_CH3_Pos          (3U)\r
-#define   GPDMA1_SGLREQSRCREG_CH3_Msk          (0x00000001U  << GPDMA1_SGLREQSRCREG_CH3_Pos)\r
-\r
-/* GPDMA1_SGLREQDSTREG  =  Single Destination Transaction Request Register*/\r
-#define   GPDMA1_SGLREQDSTREG_WE_CH0_Pos       (8U)\r
-#define   GPDMA1_SGLREQDSTREG_WE_CH0_Msk       (0x00000001U  << GPDMA1_SGLREQDSTREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA1_SGLREQDSTREG_WE_CH1_Pos       (9U)\r
-#define   GPDMA1_SGLREQDSTREG_WE_CH1_Msk       (0x00000001U  << GPDMA1_SGLREQDSTREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA1_SGLREQDSTREG_WE_CH2_Pos       (10U)\r
-#define   GPDMA1_SGLREQDSTREG_WE_CH2_Msk       (0x00000001U  << GPDMA1_SGLREQDSTREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA1_SGLREQDSTREG_WE_CH3_Pos       (11U)\r
-#define   GPDMA1_SGLREQDSTREG_WE_CH3_Msk       (0x00000001U  << GPDMA1_SGLREQDSTREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA1_SGLREQDSTREG_CH0_Pos          (0U)\r
-#define   GPDMA1_SGLREQDSTREG_CH0_Msk          (0x00000001U  << GPDMA1_SGLREQDSTREG_CH0_Pos)\r
-\r
-#define   GPDMA1_SGLREQDSTREG_CH1_Pos          (1U)\r
-#define   GPDMA1_SGLREQDSTREG_CH1_Msk          (0x00000001U  << GPDMA1_SGLREQDSTREG_CH1_Pos)\r
-\r
-#define   GPDMA1_SGLREQDSTREG_CH2_Pos          (2U)\r
-#define   GPDMA1_SGLREQDSTREG_CH2_Msk          (0x00000001U  << GPDMA1_SGLREQDSTREG_CH2_Pos)\r
-\r
-#define   GPDMA1_SGLREQDSTREG_CH3_Pos          (3U)\r
-#define   GPDMA1_SGLREQDSTREG_CH3_Msk          (0x00000001U  << GPDMA1_SGLREQDSTREG_CH3_Pos)\r
-\r
-/* GPDMA1_LSTSRCREG  =  Last Source Transaction Request Register*/\r
-#define   GPDMA1_LSTSRCREG_WE_CH0_Pos          (8U)\r
-#define   GPDMA1_LSTSRCREG_WE_CH0_Msk          (0x00000001U  << GPDMA1_LSTSRCREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA1_LSTSRCREG_WE_CH1_Pos          (9U)\r
-#define   GPDMA1_LSTSRCREG_WE_CH1_Msk          (0x00000001U  << GPDMA1_LSTSRCREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA1_LSTSRCREG_WE_CH2_Pos          (10U)\r
-#define   GPDMA1_LSTSRCREG_WE_CH2_Msk          (0x00000001U  << GPDMA1_LSTSRCREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA1_LSTSRCREG_WE_CH3_Pos          (11U)\r
-#define   GPDMA1_LSTSRCREG_WE_CH3_Msk          (0x00000001U  << GPDMA1_LSTSRCREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA1_LSTSRCREG_CH0_Pos     (0U)\r
-#define   GPDMA1_LSTSRCREG_CH0_Msk     (0x00000001U  << GPDMA1_LSTSRCREG_CH0_Pos)\r
-\r
-#define   GPDMA1_LSTSRCREG_CH1_Pos     (1U)\r
-#define   GPDMA1_LSTSRCREG_CH1_Msk     (0x00000001U  << GPDMA1_LSTSRCREG_CH1_Pos)\r
-\r
-#define   GPDMA1_LSTSRCREG_CH2_Pos     (2U)\r
-#define   GPDMA1_LSTSRCREG_CH2_Msk     (0x00000001U  << GPDMA1_LSTSRCREG_CH2_Pos)\r
-\r
-#define   GPDMA1_LSTSRCREG_CH3_Pos     (3U)\r
-#define   GPDMA1_LSTSRCREG_CH3_Msk     (0x00000001U  << GPDMA1_LSTSRCREG_CH3_Pos)\r
-\r
-/* GPDMA1_LSTDSTREG  =  Last Destination Transaction Request Register*/\r
-#define   GPDMA1_LSTDSTREG_WE_CH0_Pos          (8U)\r
-#define   GPDMA1_LSTDSTREG_WE_CH0_Msk          (0x00000001U  << GPDMA1_LSTDSTREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA1_LSTDSTREG_WE_CH1_Pos          (9U)\r
-#define   GPDMA1_LSTDSTREG_WE_CH1_Msk          (0x00000001U  << GPDMA1_LSTDSTREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA1_LSTDSTREG_WE_CH2_Pos          (10U)\r
-#define   GPDMA1_LSTDSTREG_WE_CH2_Msk          (0x00000001U  << GPDMA1_LSTDSTREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA1_LSTDSTREG_WE_CH3_Pos          (11U)\r
-#define   GPDMA1_LSTDSTREG_WE_CH3_Msk          (0x00000001U  << GPDMA1_LSTDSTREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA1_LSTDSTREG_CH0_Pos     (0U)\r
-#define   GPDMA1_LSTDSTREG_CH0_Msk     (0x00000001U  << GPDMA1_LSTDSTREG_CH0_Pos)\r
-\r
-#define   GPDMA1_LSTDSTREG_CH1_Pos     (1U)\r
-#define   GPDMA1_LSTDSTREG_CH1_Msk     (0x00000001U  << GPDMA1_LSTDSTREG_CH1_Pos)\r
-\r
-#define   GPDMA1_LSTDSTREG_CH2_Pos     (2U)\r
-#define   GPDMA1_LSTDSTREG_CH2_Msk     (0x00000001U  << GPDMA1_LSTDSTREG_CH2_Pos)\r
-\r
-#define   GPDMA1_LSTDSTREG_CH3_Pos     (3U)\r
-#define   GPDMA1_LSTDSTREG_CH3_Msk     (0x00000001U  << GPDMA1_LSTDSTREG_CH3_Pos)\r
-\r
-/* GPDMA1_DMACFGREG  =  GPDMA Configuration Register*/\r
-#define   GPDMA1_DMACFGREG_DMA_EN_Pos          (0U)\r
-#define   GPDMA1_DMACFGREG_DMA_EN_Msk          (0x00000001U  << GPDMA1_DMACFGREG_DMA_EN_Pos)\r
-\r
-/* GPDMA1_CHENREG  =  GPDMA Channel Enable Register*/\r
-#define   GPDMA1_CHENREG_WE_CH_Pos     (8U)\r
-#define   GPDMA1_CHENREG_WE_CH_Msk     (0x0000000FU  << GPDMA1_CHENREG_WE_CH_Pos)\r
-\r
-#define   GPDMA1_CHENREG_CH_Pos        (0U)\r
-#define   GPDMA1_CHENREG_CH_Msk        (0x0000000FU  << GPDMA1_CHENREG_CH_Pos)\r
-\r
-/* GPDMA1_ID  =  GPDMA1 ID Register*/\r
-#define   GPDMA1_ID_VALUE_Pos          (0U)\r
-#define   GPDMA1_ID_VALUE_Msk          (0xFFFFFFFFU  << GPDMA1_ID_VALUE_Pos)\r
-\r
-/* GPDMA1_TYPE  =  GPDMA Component Type*/\r
-#define   GPDMA1_TYPE_VALUE_Pos        (0U)\r
-#define   GPDMA1_TYPE_VALUE_Msk        (0xFFFFFFFFU  << GPDMA1_TYPE_VALUE_Pos)\r
-\r
-/* GPDMA1_VERSION  =  DMA Component Version*/\r
-#define   GPDMA1_VERSION_VALUE_Pos     (0U)\r
-#define   GPDMA1_VERSION_VALUE_Msk     (0xFFFFFFFFU  << GPDMA1_VERSION_VALUE_Pos)\r
-\r
-\r
-\r
-/***   GPDMA0 Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* GPDMA0_CH_SARx  =  Source Address Register for Channel 0*/\r
-#define   GPDMA0_CH_SAR_SAR_Pos        (0U)\r
-#define   GPDMA0_CH_SAR_SAR_Msk        (0xFFFFFFFFU  << GPDMA0_CH_SAR_SAR_Pos)\r
-\r
-/* GPDMA0_CH_DARx  =  Destination Address Register for Channel 0*/\r
-#define   GPDMA0_CH_DAR_DAR_Pos        (0U)\r
-#define   GPDMA0_CH_DAR_DAR_Msk        (0xFFFFFFFFU  << GPDMA0_CH_DAR_DAR_Pos)\r
-\r
-/* GPDMA0_CH_LLPx  =  Linked List Pointer Register for Channel 0*/\r
-#define   GPDMA0_CH_LLP_LOC_Pos        (2U)\r
-#define   GPDMA0_CH_LLP_LOC_Msk        (0x3FFFFFFFU  << GPDMA0_CH_LLP_LOC_Pos)\r
-\r
-/* GPDMA0_CH_CTLL  =  Control Register for Channel x Low Word*/\r
-#define   GPDMA0_CH_CTLL_LLP_SRC_EN_Pos        (28U)\r
-#define   GPDMA0_CH_CTLL_LLP_SRC_EN_Msk        (0x00000001U  << GPDMA0_CH_CTLL_LLP_SRC_EN_Pos)\r
-\r
-#define   GPDMA0_CH_CTLL_LLP_DST_EN_Pos        (27U)\r
-#define   GPDMA0_CH_CTLL_LLP_DST_EN_Msk        (0x00000001U  << GPDMA0_CH_CTLL_LLP_DST_EN_Pos)\r
-\r
-#define   GPDMA0_CH_CTLL_TT_FC_Pos     (20U)\r
-#define   GPDMA0_CH_CTLL_TT_FC_Msk     (0x00000007U  << GPDMA0_CH_CTLL_TT_FC_Pos)\r
-\r
-#define   GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos    (18U)\r
-#define   GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk    (0x00000001U  << GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos)\r
-\r
-#define   GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos     (17U)\r
-#define   GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk     (0x00000001U  << GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos)\r
-\r
-#define   GPDMA0_CH_CTLL_SRC_MSIZE_Pos         (14U)\r
-#define   GPDMA0_CH_CTLL_SRC_MSIZE_Msk         (0x00000007U  << GPDMA0_CH_CTLL_SRC_MSIZE_Pos)\r
-\r
-#define   GPDMA0_CH_CTLL_DEST_MSIZE_Pos        (11U)\r
-#define   GPDMA0_CH_CTLL_DEST_MSIZE_Msk        (0x00000007U  << GPDMA0_CH_CTLL_DEST_MSIZE_Pos)\r
-\r
-#define   GPDMA0_CH_CTLL_SINC_Pos      (9U)\r
-#define   GPDMA0_CH_CTLL_SINC_Msk      (0x00000003U  << GPDMA0_CH_CTLL_SINC_Pos)\r
-\r
-#define   GPDMA0_CH_CTLL_DINC_Pos      (7U)\r
-#define   GPDMA0_CH_CTLL_DINC_Msk      (0x00000003U  << GPDMA0_CH_CTLL_DINC_Pos)\r
-\r
-#define   GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos      (4U)\r
-#define   GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk      (0x00000007U  << GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos)\r
-\r
-#define   GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos      (1U)\r
-#define   GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk      (0x00000007U  << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos)\r
-\r
-#define   GPDMA0_CH_CTLL_INT_EN_Pos    (0U)\r
-#define   GPDMA0_CH_CTLL_INT_EN_Msk    (0x00000001U  << GPDMA0_CH_CTLL_INT_EN_Pos)\r
-\r
-/* GPDMA0_CH_CTLH  =  Control Register for Channel x High Word*/\r
-#define   GPDMA0_CH_CTLH_DONE_Pos      (12U)\r
-#define   GPDMA0_CH_CTLH_DONE_Msk      (0x00000001U  << GPDMA0_CH_CTLH_DONE_Pos)\r
-\r
-#define   GPDMA0_CH_CTLH_BLOCK_TS_Pos          (0U)\r
-#define   GPDMA0_CH_CTLH_BLOCK_TS_Msk          (0x00000FFFU  << GPDMA0_CH_CTLH_BLOCK_TS_Pos)\r
-\r
-/* GPDMA0_CH_SSTATx  =  Source Status Register for Channel 0*/\r
-#define   GPDMA0_CH_SSTAT_SSTAT_Pos    (0U)\r
-#define   GPDMA0_CH_SSTAT_SSTAT_Msk    (0xFFFFFFFFU  << GPDMA0_CH_SSTAT_SSTAT_Pos)\r
-\r
-/* GPDMA0_CH_DSTATx  =  Destination Status Register for Channel 0*/\r
-#define   GPDMA0_CH_DSTAT_DSTAT_Pos    (0U)\r
-#define   GPDMA0_CH_DSTAT_DSTAT_Msk    (0xFFFFFFFFU  << GPDMA0_CH_DSTAT_DSTAT_Pos)\r
-\r
-/* GPDMA0_CH_SSTATARx  =  Source Status Address Register for Channel 0*/\r
-#define   GPDMA0_CH_SSTATAR_SSTATAR_Pos        (0U)\r
-#define   GPDMA0_CH_SSTATAR_SSTATAR_Msk        (0xFFFFFFFFU  << GPDMA0_CH_SSTATAR_SSTATAR_Pos)\r
-\r
-/* GPDMA0_CH_DSTATARx  =  Destination Status Address Register for Channel 0*/\r
-#define   GPDMA0_CH_DSTATAR_DSTATAR_Pos        (0U)\r
-#define   GPDMA0_CH_DSTATAR_DSTATAR_Msk        (0xFFFFFFFFU  << GPDMA0_CH_DSTATAR_DSTATAR_Pos)\r
-\r
-/* GPDMA0_CH_CFGL  =  Configuration Register for Channel x Low Word*/\r
-#define   GPDMA0_CH_CFGL_RELOAD_DST_Pos        (31U)\r
-#define   GPDMA0_CH_CFGL_RELOAD_DST_Msk        (0x00000001U  << GPDMA0_CH_CFGL_RELOAD_DST_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_RELOAD_SRC_Pos        (30U)\r
-#define   GPDMA0_CH_CFGL_RELOAD_SRC_Msk        (0x00000001U  << GPDMA0_CH_CFGL_RELOAD_SRC_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_MAX_ABRST_Pos         (20U)\r
-#define   GPDMA0_CH_CFGL_MAX_ABRST_Msk         (0x000003FFU  << GPDMA0_CH_CFGL_MAX_ABRST_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_SRC_HS_POL_Pos        (19U)\r
-#define   GPDMA0_CH_CFGL_SRC_HS_POL_Msk        (0x00000001U  << GPDMA0_CH_CFGL_SRC_HS_POL_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_DST_HS_POL_Pos        (18U)\r
-#define   GPDMA0_CH_CFGL_DST_HS_POL_Msk        (0x00000001U  << GPDMA0_CH_CFGL_DST_HS_POL_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_LOCK_B_Pos    (17U)\r
-#define   GPDMA0_CH_CFGL_LOCK_B_Msk    (0x00000001U  << GPDMA0_CH_CFGL_LOCK_B_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_LOCK_CH_Pos   (16U)\r
-#define   GPDMA0_CH_CFGL_LOCK_CH_Msk   (0x00000001U  << GPDMA0_CH_CFGL_LOCK_CH_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_LOCK_B_L_Pos          (14U)\r
-#define   GPDMA0_CH_CFGL_LOCK_B_L_Msk          (0x00000003U  << GPDMA0_CH_CFGL_LOCK_B_L_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_LOCK_CH_L_Pos         (12U)\r
-#define   GPDMA0_CH_CFGL_LOCK_CH_L_Msk         (0x00000003U  << GPDMA0_CH_CFGL_LOCK_CH_L_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_HS_SEL_SRC_Pos        (11U)\r
-#define   GPDMA0_CH_CFGL_HS_SEL_SRC_Msk        (0x00000001U  << GPDMA0_CH_CFGL_HS_SEL_SRC_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_HS_SEL_DST_Pos        (10U)\r
-#define   GPDMA0_CH_CFGL_HS_SEL_DST_Msk        (0x00000001U  << GPDMA0_CH_CFGL_HS_SEL_DST_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_FIFO_EMPTY_Pos        (9U)\r
-#define   GPDMA0_CH_CFGL_FIFO_EMPTY_Msk        (0x00000001U  << GPDMA0_CH_CFGL_FIFO_EMPTY_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_CH_SUSP_Pos   (8U)\r
-#define   GPDMA0_CH_CFGL_CH_SUSP_Msk   (0x00000001U  << GPDMA0_CH_CFGL_CH_SUSP_Pos)\r
-\r
-#define   GPDMA0_CH_CFGL_CH_PRIOR_Pos          (5U)\r
-#define   GPDMA0_CH_CFGL_CH_PRIOR_Msk          (0x00000007U  << GPDMA0_CH_CFGL_CH_PRIOR_Pos)\r
-\r
-/* GPDMA0_CH_CFGH  =  Configuration Register for Channel x High Word*/\r
-#define   GPDMA0_CH_CFGH_DEST_PER_Pos          (11U)\r
-#define   GPDMA0_CH_CFGH_DEST_PER_Msk          (0x0000000FU  << GPDMA0_CH_CFGH_DEST_PER_Pos)\r
-\r
-#define   GPDMA0_CH_CFGH_SRC_PER_Pos   (7U)\r
-#define   GPDMA0_CH_CFGH_SRC_PER_Msk   (0x0000000FU  << GPDMA0_CH_CFGH_SRC_PER_Pos)\r
-\r
-#define   GPDMA0_CH_CFGH_SS_UPD_EN_Pos         (6U)\r
-#define   GPDMA0_CH_CFGH_SS_UPD_EN_Msk         (0x00000001U  << GPDMA0_CH_CFGH_SS_UPD_EN_Pos)\r
-\r
-#define   GPDMA0_CH_CFGH_DS_UPD_EN_Pos         (5U)\r
-#define   GPDMA0_CH_CFGH_DS_UPD_EN_Msk         (0x00000001U  << GPDMA0_CH_CFGH_DS_UPD_EN_Pos)\r
-\r
-#define   GPDMA0_CH_CFGH_PROTCTL_Pos   (2U)\r
-#define   GPDMA0_CH_CFGH_PROTCTL_Msk   (0x00000007U  << GPDMA0_CH_CFGH_PROTCTL_Pos)\r
-\r
-#define   GPDMA0_CH_CFGH_FIFO_MODE_Pos         (1U)\r
-#define   GPDMA0_CH_CFGH_FIFO_MODE_Msk         (0x00000001U  << GPDMA0_CH_CFGH_FIFO_MODE_Pos)\r
-\r
-#define   GPDMA0_CH_CFGH_FCMODE_Pos    (0U)\r
-#define   GPDMA0_CH_CFGH_FCMODE_Msk    (0x00000001U  << GPDMA0_CH_CFGH_FCMODE_Pos)\r
-\r
-/* GPDMA0_CH_SGRx  =  Source Gather Register for Channel 0*/\r
-#define   GPDMA0_CH_SGR_SGC_Pos        (20U)\r
-#define   GPDMA0_CH_SGR_SGC_Msk        (0x00000FFFU  << GPDMA0_CH_SGR_SGC_Pos)\r
-\r
-#define   GPDMA0_CH_SGR_SGI_Pos        (0U)\r
-#define   GPDMA0_CH_SGR_SGI_Msk        (0x000FFFFFU  << GPDMA0_CH_SGR_SGI_Pos)\r
-\r
-/* GPDMA0_CH_DSRx  =  Destination Scatter Register for Channel 0*/\r
-#define   GPDMA0_CH_DSR_DSC_Pos        (20U)\r
-#define   GPDMA0_CH_DSR_DSC_Msk        (0x00000FFFU  << GPDMA0_CH_DSR_DSC_Pos)\r
-\r
-#define   GPDMA0_CH_DSR_DSI_Pos        (0U)\r
-#define   GPDMA0_CH_DSR_DSI_Msk        (0x000FFFFFU  << GPDMA0_CH_DSR_DSI_Pos)\r
-\r
-/* GPDMA0_RAWTFR  =  Raw IntTfr Status*/\r
-#define   GPDMA0_RAWTFR_CH0_Pos        (0U)\r
-#define   GPDMA0_RAWTFR_CH0_Msk        (0x00000001U  << GPDMA0_RAWTFR_CH0_Pos)\r
-\r
-#define   GPDMA0_RAWTFR_CH1_Pos        (1U)\r
-#define   GPDMA0_RAWTFR_CH1_Msk        (0x00000001U  << GPDMA0_RAWTFR_CH1_Pos)\r
-\r
-#define   GPDMA0_RAWTFR_CH2_Pos        (2U)\r
-#define   GPDMA0_RAWTFR_CH2_Msk        (0x00000001U  << GPDMA0_RAWTFR_CH2_Pos)\r
-\r
-#define   GPDMA0_RAWTFR_CH3_Pos        (3U)\r
-#define   GPDMA0_RAWTFR_CH3_Msk        (0x00000001U  << GPDMA0_RAWTFR_CH3_Pos)\r
-\r
-#define   GPDMA0_RAWTFR_CH4_Pos        (4U)\r
-#define   GPDMA0_RAWTFR_CH4_Msk        (0x00000001U  << GPDMA0_RAWTFR_CH4_Pos)\r
-\r
-#define   GPDMA0_RAWTFR_CH5_Pos        (5U)\r
-#define   GPDMA0_RAWTFR_CH5_Msk        (0x00000001U  << GPDMA0_RAWTFR_CH5_Pos)\r
-\r
-#define   GPDMA0_RAWTFR_CH6_Pos        (6U)\r
-#define   GPDMA0_RAWTFR_CH6_Msk        (0x00000001U  << GPDMA0_RAWTFR_CH6_Pos)\r
-\r
-#define   GPDMA0_RAWTFR_CH7_Pos        (7U)\r
-#define   GPDMA0_RAWTFR_CH7_Msk        (0x00000001U  << GPDMA0_RAWTFR_CH7_Pos)\r
-\r
-/* GPDMA0_RAWBLOCK  =  Raw IntBlock Status*/\r
-#define   GPDMA0_RAWBLOCK_CH0_Pos      (0U)\r
-#define   GPDMA0_RAWBLOCK_CH0_Msk      (0x00000001U  << GPDMA0_RAWBLOCK_CH0_Pos)\r
-\r
-#define   GPDMA0_RAWBLOCK_CH1_Pos      (1U)\r
-#define   GPDMA0_RAWBLOCK_CH1_Msk      (0x00000001U  << GPDMA0_RAWBLOCK_CH1_Pos)\r
-\r
-#define   GPDMA0_RAWBLOCK_CH2_Pos      (2U)\r
-#define   GPDMA0_RAWBLOCK_CH2_Msk      (0x00000001U  << GPDMA0_RAWBLOCK_CH2_Pos)\r
-\r
-#define   GPDMA0_RAWBLOCK_CH3_Pos      (3U)\r
-#define   GPDMA0_RAWBLOCK_CH3_Msk      (0x00000001U  << GPDMA0_RAWBLOCK_CH3_Pos)\r
-\r
-#define   GPDMA0_RAWBLOCK_CH4_Pos      (4U)\r
-#define   GPDMA0_RAWBLOCK_CH4_Msk      (0x00000001U  << GPDMA0_RAWBLOCK_CH4_Pos)\r
-\r
-#define   GPDMA0_RAWBLOCK_CH5_Pos      (5U)\r
-#define   GPDMA0_RAWBLOCK_CH5_Msk      (0x00000001U  << GPDMA0_RAWBLOCK_CH5_Pos)\r
-\r
-#define   GPDMA0_RAWBLOCK_CH6_Pos      (6U)\r
-#define   GPDMA0_RAWBLOCK_CH6_Msk      (0x00000001U  << GPDMA0_RAWBLOCK_CH6_Pos)\r
-\r
-#define   GPDMA0_RAWBLOCK_CH7_Pos      (7U)\r
-#define   GPDMA0_RAWBLOCK_CH7_Msk      (0x00000001U  << GPDMA0_RAWBLOCK_CH7_Pos)\r
-\r
-/* GPDMA0_RAWSRCTRAN  =  Raw IntSrcTran Status*/\r
-#define   GPDMA0_RAWSRCTRAN_CH0_Pos    (0U)\r
-#define   GPDMA0_RAWSRCTRAN_CH0_Msk    (0x00000001U  << GPDMA0_RAWSRCTRAN_CH0_Pos)\r
-\r
-#define   GPDMA0_RAWSRCTRAN_CH1_Pos    (1U)\r
-#define   GPDMA0_RAWSRCTRAN_CH1_Msk    (0x00000001U  << GPDMA0_RAWSRCTRAN_CH1_Pos)\r
-\r
-#define   GPDMA0_RAWSRCTRAN_CH2_Pos    (2U)\r
-#define   GPDMA0_RAWSRCTRAN_CH2_Msk    (0x00000001U  << GPDMA0_RAWSRCTRAN_CH2_Pos)\r
-\r
-#define   GPDMA0_RAWSRCTRAN_CH3_Pos    (3U)\r
-#define   GPDMA0_RAWSRCTRAN_CH3_Msk    (0x00000001U  << GPDMA0_RAWSRCTRAN_CH3_Pos)\r
-\r
-#define   GPDMA0_RAWSRCTRAN_CH4_Pos    (4U)\r
-#define   GPDMA0_RAWSRCTRAN_CH4_Msk    (0x00000001U  << GPDMA0_RAWSRCTRAN_CH4_Pos)\r
-\r
-#define   GPDMA0_RAWSRCTRAN_CH5_Pos    (5U)\r
-#define   GPDMA0_RAWSRCTRAN_CH5_Msk    (0x00000001U  << GPDMA0_RAWSRCTRAN_CH5_Pos)\r
-\r
-#define   GPDMA0_RAWSRCTRAN_CH6_Pos    (6U)\r
-#define   GPDMA0_RAWSRCTRAN_CH6_Msk    (0x00000001U  << GPDMA0_RAWSRCTRAN_CH6_Pos)\r
-\r
-#define   GPDMA0_RAWSRCTRAN_CH7_Pos    (7U)\r
-#define   GPDMA0_RAWSRCTRAN_CH7_Msk    (0x00000001U  << GPDMA0_RAWSRCTRAN_CH7_Pos)\r
-\r
-/* GPDMA0_RAWDSTTRAN  =  Raw IntBlock Status*/\r
-#define   GPDMA0_RAWDSTTRAN_CH0_Pos    (0U)\r
-#define   GPDMA0_RAWDSTTRAN_CH0_Msk    (0x00000001U  << GPDMA0_RAWDSTTRAN_CH0_Pos)\r
-\r
-#define   GPDMA0_RAWDSTTRAN_CH1_Pos    (1U)\r
-#define   GPDMA0_RAWDSTTRAN_CH1_Msk    (0x00000001U  << GPDMA0_RAWDSTTRAN_CH1_Pos)\r
-\r
-#define   GPDMA0_RAWDSTTRAN_CH2_Pos    (2U)\r
-#define   GPDMA0_RAWDSTTRAN_CH2_Msk    (0x00000001U  << GPDMA0_RAWDSTTRAN_CH2_Pos)\r
-\r
-#define   GPDMA0_RAWDSTTRAN_CH3_Pos    (3U)\r
-#define   GPDMA0_RAWDSTTRAN_CH3_Msk    (0x00000001U  << GPDMA0_RAWDSTTRAN_CH3_Pos)\r
-\r
-#define   GPDMA0_RAWDSTTRAN_CH4_Pos    (4U)\r
-#define   GPDMA0_RAWDSTTRAN_CH4_Msk    (0x00000001U  << GPDMA0_RAWDSTTRAN_CH4_Pos)\r
-\r
-#define   GPDMA0_RAWDSTTRAN_CH5_Pos    (5U)\r
-#define   GPDMA0_RAWDSTTRAN_CH5_Msk    (0x00000001U  << GPDMA0_RAWDSTTRAN_CH5_Pos)\r
-\r
-#define   GPDMA0_RAWDSTTRAN_CH6_Pos    (6U)\r
-#define   GPDMA0_RAWDSTTRAN_CH6_Msk    (0x00000001U  << GPDMA0_RAWDSTTRAN_CH6_Pos)\r
-\r
-#define   GPDMA0_RAWDSTTRAN_CH7_Pos    (7U)\r
-#define   GPDMA0_RAWDSTTRAN_CH7_Msk    (0x00000001U  << GPDMA0_RAWDSTTRAN_CH7_Pos)\r
-\r
-/* GPDMA0_RAWERR  =  Raw IntErr Status*/\r
-#define   GPDMA0_RAWERR_CH0_Pos        (0U)\r
-#define   GPDMA0_RAWERR_CH0_Msk        (0x00000001U  << GPDMA0_RAWERR_CH0_Pos)\r
-\r
-#define   GPDMA0_RAWERR_CH1_Pos        (1U)\r
-#define   GPDMA0_RAWERR_CH1_Msk        (0x00000001U  << GPDMA0_RAWERR_CH1_Pos)\r
-\r
-#define   GPDMA0_RAWERR_CH2_Pos        (2U)\r
-#define   GPDMA0_RAWERR_CH2_Msk        (0x00000001U  << GPDMA0_RAWERR_CH2_Pos)\r
-\r
-#define   GPDMA0_RAWERR_CH3_Pos        (3U)\r
-#define   GPDMA0_RAWERR_CH3_Msk        (0x00000001U  << GPDMA0_RAWERR_CH3_Pos)\r
-\r
-#define   GPDMA0_RAWERR_CH4_Pos        (4U)\r
-#define   GPDMA0_RAWERR_CH4_Msk        (0x00000001U  << GPDMA0_RAWERR_CH4_Pos)\r
-\r
-#define   GPDMA0_RAWERR_CH5_Pos        (5U)\r
-#define   GPDMA0_RAWERR_CH5_Msk        (0x00000001U  << GPDMA0_RAWERR_CH5_Pos)\r
-\r
-#define   GPDMA0_RAWERR_CH6_Pos        (6U)\r
-#define   GPDMA0_RAWERR_CH6_Msk        (0x00000001U  << GPDMA0_RAWERR_CH6_Pos)\r
-\r
-#define   GPDMA0_RAWERR_CH7_Pos        (7U)\r
-#define   GPDMA0_RAWERR_CH7_Msk        (0x00000001U  << GPDMA0_RAWERR_CH7_Pos)\r
-\r
-/* GPDMA0_STATUSTFR  =  IntTfr Status*/\r
-#define   GPDMA0_STATUSTFR_CH0_Pos     (0U)\r
-#define   GPDMA0_STATUSTFR_CH0_Msk     (0x00000001U  << GPDMA0_STATUSTFR_CH0_Pos)\r
-\r
-#define   GPDMA0_STATUSTFR_CH1_Pos     (1U)\r
-#define   GPDMA0_STATUSTFR_CH1_Msk     (0x00000001U  << GPDMA0_STATUSTFR_CH1_Pos)\r
-\r
-#define   GPDMA0_STATUSTFR_CH2_Pos     (2U)\r
-#define   GPDMA0_STATUSTFR_CH2_Msk     (0x00000001U  << GPDMA0_STATUSTFR_CH2_Pos)\r
-\r
-#define   GPDMA0_STATUSTFR_CH3_Pos     (3U)\r
-#define   GPDMA0_STATUSTFR_CH3_Msk     (0x00000001U  << GPDMA0_STATUSTFR_CH3_Pos)\r
-\r
-#define   GPDMA0_STATUSTFR_CH4_Pos     (4U)\r
-#define   GPDMA0_STATUSTFR_CH4_Msk     (0x00000001U  << GPDMA0_STATUSTFR_CH4_Pos)\r
-\r
-#define   GPDMA0_STATUSTFR_CH5_Pos     (5U)\r
-#define   GPDMA0_STATUSTFR_CH5_Msk     (0x00000001U  << GPDMA0_STATUSTFR_CH5_Pos)\r
-\r
-#define   GPDMA0_STATUSTFR_CH6_Pos     (6U)\r
-#define   GPDMA0_STATUSTFR_CH6_Msk     (0x00000001U  << GPDMA0_STATUSTFR_CH6_Pos)\r
-\r
-#define   GPDMA0_STATUSTFR_CH7_Pos     (7U)\r
-#define   GPDMA0_STATUSTFR_CH7_Msk     (0x00000001U  << GPDMA0_STATUSTFR_CH7_Pos)\r
-\r
-/* GPDMA0_STATUSBLOCK  =  IntBlock Status*/\r
-#define   GPDMA0_STATUSBLOCK_CH0_Pos   (0U)\r
-#define   GPDMA0_STATUSBLOCK_CH0_Msk   (0x00000001U  << GPDMA0_STATUSBLOCK_CH0_Pos)\r
-\r
-#define   GPDMA0_STATUSBLOCK_CH1_Pos   (1U)\r
-#define   GPDMA0_STATUSBLOCK_CH1_Msk   (0x00000001U  << GPDMA0_STATUSBLOCK_CH1_Pos)\r
-\r
-#define   GPDMA0_STATUSBLOCK_CH2_Pos   (2U)\r
-#define   GPDMA0_STATUSBLOCK_CH2_Msk   (0x00000001U  << GPDMA0_STATUSBLOCK_CH2_Pos)\r
-\r
-#define   GPDMA0_STATUSBLOCK_CH3_Pos   (3U)\r
-#define   GPDMA0_STATUSBLOCK_CH3_Msk   (0x00000001U  << GPDMA0_STATUSBLOCK_CH3_Pos)\r
-\r
-#define   GPDMA0_STATUSBLOCK_CH4_Pos   (4U)\r
-#define   GPDMA0_STATUSBLOCK_CH4_Msk   (0x00000001U  << GPDMA0_STATUSBLOCK_CH4_Pos)\r
-\r
-#define   GPDMA0_STATUSBLOCK_CH5_Pos   (5U)\r
-#define   GPDMA0_STATUSBLOCK_CH5_Msk   (0x00000001U  << GPDMA0_STATUSBLOCK_CH5_Pos)\r
-\r
-#define   GPDMA0_STATUSBLOCK_CH6_Pos   (6U)\r
-#define   GPDMA0_STATUSBLOCK_CH6_Msk   (0x00000001U  << GPDMA0_STATUSBLOCK_CH6_Pos)\r
-\r
-#define   GPDMA0_STATUSBLOCK_CH7_Pos   (7U)\r
-#define   GPDMA0_STATUSBLOCK_CH7_Msk   (0x00000001U  << GPDMA0_STATUSBLOCK_CH7_Pos)\r
-\r
-/* GPDMA0_STATUSSRCTRAN  =  IntSrcTran Status*/\r
-#define   GPDMA0_STATUSSRCTRAN_CH0_Pos         (0U)\r
-#define   GPDMA0_STATUSSRCTRAN_CH0_Msk         (0x00000001U  << GPDMA0_STATUSSRCTRAN_CH0_Pos)\r
-\r
-#define   GPDMA0_STATUSSRCTRAN_CH1_Pos         (1U)\r
-#define   GPDMA0_STATUSSRCTRAN_CH1_Msk         (0x00000001U  << GPDMA0_STATUSSRCTRAN_CH1_Pos)\r
-\r
-#define   GPDMA0_STATUSSRCTRAN_CH2_Pos         (2U)\r
-#define   GPDMA0_STATUSSRCTRAN_CH2_Msk         (0x00000001U  << GPDMA0_STATUSSRCTRAN_CH2_Pos)\r
-\r
-#define   GPDMA0_STATUSSRCTRAN_CH3_Pos         (3U)\r
-#define   GPDMA0_STATUSSRCTRAN_CH3_Msk         (0x00000001U  << GPDMA0_STATUSSRCTRAN_CH3_Pos)\r
-\r
-#define   GPDMA0_STATUSSRCTRAN_CH4_Pos         (4U)\r
-#define   GPDMA0_STATUSSRCTRAN_CH4_Msk         (0x00000001U  << GPDMA0_STATUSSRCTRAN_CH4_Pos)\r
-\r
-#define   GPDMA0_STATUSSRCTRAN_CH5_Pos         (5U)\r
-#define   GPDMA0_STATUSSRCTRAN_CH5_Msk         (0x00000001U  << GPDMA0_STATUSSRCTRAN_CH5_Pos)\r
-\r
-#define   GPDMA0_STATUSSRCTRAN_CH6_Pos         (6U)\r
-#define   GPDMA0_STATUSSRCTRAN_CH6_Msk         (0x00000001U  << GPDMA0_STATUSSRCTRAN_CH6_Pos)\r
-\r
-#define   GPDMA0_STATUSSRCTRAN_CH7_Pos         (7U)\r
-#define   GPDMA0_STATUSSRCTRAN_CH7_Msk         (0x00000001U  << GPDMA0_STATUSSRCTRAN_CH7_Pos)\r
-\r
-/* GPDMA0_STATUSDSTTRAN  =  IntBlock Status*/\r
-#define   GPDMA0_STATUSDSTTRAN_CH0_Pos         (0U)\r
-#define   GPDMA0_STATUSDSTTRAN_CH0_Msk         (0x00000001U  << GPDMA0_STATUSDSTTRAN_CH0_Pos)\r
-\r
-#define   GPDMA0_STATUSDSTTRAN_CH1_Pos         (1U)\r
-#define   GPDMA0_STATUSDSTTRAN_CH1_Msk         (0x00000001U  << GPDMA0_STATUSDSTTRAN_CH1_Pos)\r
-\r
-#define   GPDMA0_STATUSDSTTRAN_CH2_Pos         (2U)\r
-#define   GPDMA0_STATUSDSTTRAN_CH2_Msk         (0x00000001U  << GPDMA0_STATUSDSTTRAN_CH2_Pos)\r
-\r
-#define   GPDMA0_STATUSDSTTRAN_CH3_Pos         (3U)\r
-#define   GPDMA0_STATUSDSTTRAN_CH3_Msk         (0x00000001U  << GPDMA0_STATUSDSTTRAN_CH3_Pos)\r
-\r
-#define   GPDMA0_STATUSDSTTRAN_CH4_Pos         (4U)\r
-#define   GPDMA0_STATUSDSTTRAN_CH4_Msk         (0x00000001U  << GPDMA0_STATUSDSTTRAN_CH4_Pos)\r
-\r
-#define   GPDMA0_STATUSDSTTRAN_CH5_Pos         (5U)\r
-#define   GPDMA0_STATUSDSTTRAN_CH5_Msk         (0x00000001U  << GPDMA0_STATUSDSTTRAN_CH5_Pos)\r
-\r
-#define   GPDMA0_STATUSDSTTRAN_CH6_Pos         (6U)\r
-#define   GPDMA0_STATUSDSTTRAN_CH6_Msk         (0x00000001U  << GPDMA0_STATUSDSTTRAN_CH6_Pos)\r
-\r
-#define   GPDMA0_STATUSDSTTRAN_CH7_Pos         (7U)\r
-#define   GPDMA0_STATUSDSTTRAN_CH7_Msk         (0x00000001U  << GPDMA0_STATUSDSTTRAN_CH7_Pos)\r
-\r
-/* GPDMA0_STATUSERR  =  IntErr Status*/\r
-#define   GPDMA0_STATUSERR_CH0_Pos     (0U)\r
-#define   GPDMA0_STATUSERR_CH0_Msk     (0x00000001U  << GPDMA0_STATUSERR_CH0_Pos)\r
-\r
-#define   GPDMA0_STATUSERR_CH1_Pos     (1U)\r
-#define   GPDMA0_STATUSERR_CH1_Msk     (0x00000001U  << GPDMA0_STATUSERR_CH1_Pos)\r
-\r
-#define   GPDMA0_STATUSERR_CH2_Pos     (2U)\r
-#define   GPDMA0_STATUSERR_CH2_Msk     (0x00000001U  << GPDMA0_STATUSERR_CH2_Pos)\r
-\r
-#define   GPDMA0_STATUSERR_CH3_Pos     (3U)\r
-#define   GPDMA0_STATUSERR_CH3_Msk     (0x00000001U  << GPDMA0_STATUSERR_CH3_Pos)\r
-\r
-#define   GPDMA0_STATUSERR_CH4_Pos     (4U)\r
-#define   GPDMA0_STATUSERR_CH4_Msk     (0x00000001U  << GPDMA0_STATUSERR_CH4_Pos)\r
-\r
-#define   GPDMA0_STATUSERR_CH5_Pos     (5U)\r
-#define   GPDMA0_STATUSERR_CH5_Msk     (0x00000001U  << GPDMA0_STATUSERR_CH5_Pos)\r
-\r
-#define   GPDMA0_STATUSERR_CH6_Pos     (6U)\r
-#define   GPDMA0_STATUSERR_CH6_Msk     (0x00000001U  << GPDMA0_STATUSERR_CH6_Pos)\r
-\r
-#define   GPDMA0_STATUSERR_CH7_Pos     (7U)\r
-#define   GPDMA0_STATUSERR_CH7_Msk     (0x00000001U  << GPDMA0_STATUSERR_CH7_Pos)\r
-\r
-/* GPDMA0_MASKTFR  =  Mask for Raw IntTfr Status*/\r
-#define   GPDMA0_MASKTFR_WE_CH0_Pos    (8U)\r
-#define   GPDMA0_MASKTFR_WE_CH0_Msk    (0x00000001U  << GPDMA0_MASKTFR_WE_CH0_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_WE_CH1_Pos    (9U)\r
-#define   GPDMA0_MASKTFR_WE_CH1_Msk    (0x00000001U  << GPDMA0_MASKTFR_WE_CH1_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_WE_CH2_Pos    (10U)\r
-#define   GPDMA0_MASKTFR_WE_CH2_Msk    (0x00000001U  << GPDMA0_MASKTFR_WE_CH2_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_WE_CH3_Pos    (11U)\r
-#define   GPDMA0_MASKTFR_WE_CH3_Msk    (0x00000001U  << GPDMA0_MASKTFR_WE_CH3_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_WE_CH4_Pos    (12U)\r
-#define   GPDMA0_MASKTFR_WE_CH4_Msk    (0x00000001U  << GPDMA0_MASKTFR_WE_CH4_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_WE_CH5_Pos    (13U)\r
-#define   GPDMA0_MASKTFR_WE_CH5_Msk    (0x00000001U  << GPDMA0_MASKTFR_WE_CH5_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_WE_CH6_Pos    (14U)\r
-#define   GPDMA0_MASKTFR_WE_CH6_Msk    (0x00000001U  << GPDMA0_MASKTFR_WE_CH6_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_WE_CH7_Pos    (15U)\r
-#define   GPDMA0_MASKTFR_WE_CH7_Msk    (0x00000001U  << GPDMA0_MASKTFR_WE_CH7_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_CH0_Pos       (0U)\r
-#define   GPDMA0_MASKTFR_CH0_Msk       (0x00000001U  << GPDMA0_MASKTFR_CH0_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_CH1_Pos       (1U)\r
-#define   GPDMA0_MASKTFR_CH1_Msk       (0x00000001U  << GPDMA0_MASKTFR_CH1_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_CH2_Pos       (2U)\r
-#define   GPDMA0_MASKTFR_CH2_Msk       (0x00000001U  << GPDMA0_MASKTFR_CH2_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_CH3_Pos       (3U)\r
-#define   GPDMA0_MASKTFR_CH3_Msk       (0x00000001U  << GPDMA0_MASKTFR_CH3_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_CH4_Pos       (4U)\r
-#define   GPDMA0_MASKTFR_CH4_Msk       (0x00000001U  << GPDMA0_MASKTFR_CH4_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_CH5_Pos       (5U)\r
-#define   GPDMA0_MASKTFR_CH5_Msk       (0x00000001U  << GPDMA0_MASKTFR_CH5_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_CH6_Pos       (6U)\r
-#define   GPDMA0_MASKTFR_CH6_Msk       (0x00000001U  << GPDMA0_MASKTFR_CH6_Pos)\r
-\r
-#define   GPDMA0_MASKTFR_CH7_Pos       (7U)\r
-#define   GPDMA0_MASKTFR_CH7_Msk       (0x00000001U  << GPDMA0_MASKTFR_CH7_Pos)\r
-\r
-/* GPDMA0_MASKBLOCK  =  Mask for Raw IntBlock Status*/\r
-#define   GPDMA0_MASKBLOCK_WE_CH0_Pos          (8U)\r
-#define   GPDMA0_MASKBLOCK_WE_CH0_Msk          (0x00000001U  << GPDMA0_MASKBLOCK_WE_CH0_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_WE_CH1_Pos          (9U)\r
-#define   GPDMA0_MASKBLOCK_WE_CH1_Msk          (0x00000001U  << GPDMA0_MASKBLOCK_WE_CH1_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_WE_CH2_Pos          (10U)\r
-#define   GPDMA0_MASKBLOCK_WE_CH2_Msk          (0x00000001U  << GPDMA0_MASKBLOCK_WE_CH2_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_WE_CH3_Pos          (11U)\r
-#define   GPDMA0_MASKBLOCK_WE_CH3_Msk          (0x00000001U  << GPDMA0_MASKBLOCK_WE_CH3_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_WE_CH4_Pos          (12U)\r
-#define   GPDMA0_MASKBLOCK_WE_CH4_Msk          (0x00000001U  << GPDMA0_MASKBLOCK_WE_CH4_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_WE_CH5_Pos          (13U)\r
-#define   GPDMA0_MASKBLOCK_WE_CH5_Msk          (0x00000001U  << GPDMA0_MASKBLOCK_WE_CH5_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_WE_CH6_Pos          (14U)\r
-#define   GPDMA0_MASKBLOCK_WE_CH6_Msk          (0x00000001U  << GPDMA0_MASKBLOCK_WE_CH6_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_WE_CH7_Pos          (15U)\r
-#define   GPDMA0_MASKBLOCK_WE_CH7_Msk          (0x00000001U  << GPDMA0_MASKBLOCK_WE_CH7_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_CH0_Pos     (0U)\r
-#define   GPDMA0_MASKBLOCK_CH0_Msk     (0x00000001U  << GPDMA0_MASKBLOCK_CH0_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_CH1_Pos     (1U)\r
-#define   GPDMA0_MASKBLOCK_CH1_Msk     (0x00000001U  << GPDMA0_MASKBLOCK_CH1_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_CH2_Pos     (2U)\r
-#define   GPDMA0_MASKBLOCK_CH2_Msk     (0x00000001U  << GPDMA0_MASKBLOCK_CH2_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_CH3_Pos     (3U)\r
-#define   GPDMA0_MASKBLOCK_CH3_Msk     (0x00000001U  << GPDMA0_MASKBLOCK_CH3_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_CH4_Pos     (4U)\r
-#define   GPDMA0_MASKBLOCK_CH4_Msk     (0x00000001U  << GPDMA0_MASKBLOCK_CH4_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_CH5_Pos     (5U)\r
-#define   GPDMA0_MASKBLOCK_CH5_Msk     (0x00000001U  << GPDMA0_MASKBLOCK_CH5_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_CH6_Pos     (6U)\r
-#define   GPDMA0_MASKBLOCK_CH6_Msk     (0x00000001U  << GPDMA0_MASKBLOCK_CH6_Pos)\r
-\r
-#define   GPDMA0_MASKBLOCK_CH7_Pos     (7U)\r
-#define   GPDMA0_MASKBLOCK_CH7_Msk     (0x00000001U  << GPDMA0_MASKBLOCK_CH7_Pos)\r
-\r
-/* GPDMA0_MASKSRCTRAN  =  Mask for Raw IntSrcTran Status*/\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH0_Pos        (8U)\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH0_Msk        (0x00000001U  << GPDMA0_MASKSRCTRAN_WE_CH0_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH1_Pos        (9U)\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH1_Msk        (0x00000001U  << GPDMA0_MASKSRCTRAN_WE_CH1_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH2_Pos        (10U)\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH2_Msk        (0x00000001U  << GPDMA0_MASKSRCTRAN_WE_CH2_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH3_Pos        (11U)\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH3_Msk        (0x00000001U  << GPDMA0_MASKSRCTRAN_WE_CH3_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH4_Pos        (12U)\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH4_Msk        (0x00000001U  << GPDMA0_MASKSRCTRAN_WE_CH4_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH5_Pos        (13U)\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH5_Msk        (0x00000001U  << GPDMA0_MASKSRCTRAN_WE_CH5_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH6_Pos        (14U)\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH6_Msk        (0x00000001U  << GPDMA0_MASKSRCTRAN_WE_CH6_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH7_Pos        (15U)\r
-#define   GPDMA0_MASKSRCTRAN_WE_CH7_Msk        (0x00000001U  << GPDMA0_MASKSRCTRAN_WE_CH7_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_CH0_Pos   (0U)\r
-#define   GPDMA0_MASKSRCTRAN_CH0_Msk   (0x00000001U  << GPDMA0_MASKSRCTRAN_CH0_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_CH1_Pos   (1U)\r
-#define   GPDMA0_MASKSRCTRAN_CH1_Msk   (0x00000001U  << GPDMA0_MASKSRCTRAN_CH1_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_CH2_Pos   (2U)\r
-#define   GPDMA0_MASKSRCTRAN_CH2_Msk   (0x00000001U  << GPDMA0_MASKSRCTRAN_CH2_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_CH3_Pos   (3U)\r
-#define   GPDMA0_MASKSRCTRAN_CH3_Msk   (0x00000001U  << GPDMA0_MASKSRCTRAN_CH3_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_CH4_Pos   (4U)\r
-#define   GPDMA0_MASKSRCTRAN_CH4_Msk   (0x00000001U  << GPDMA0_MASKSRCTRAN_CH4_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_CH5_Pos   (5U)\r
-#define   GPDMA0_MASKSRCTRAN_CH5_Msk   (0x00000001U  << GPDMA0_MASKSRCTRAN_CH5_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_CH6_Pos   (6U)\r
-#define   GPDMA0_MASKSRCTRAN_CH6_Msk   (0x00000001U  << GPDMA0_MASKSRCTRAN_CH6_Pos)\r
-\r
-#define   GPDMA0_MASKSRCTRAN_CH7_Pos   (7U)\r
-#define   GPDMA0_MASKSRCTRAN_CH7_Msk   (0x00000001U  << GPDMA0_MASKSRCTRAN_CH7_Pos)\r
-\r
-/* GPDMA0_MASKDSTTRAN  =  Mask for Raw IntBlock Status*/\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH0_Pos        (8U)\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH0_Msk        (0x00000001U  << GPDMA0_MASKDSTTRAN_WE_CH0_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH1_Pos        (9U)\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH1_Msk        (0x00000001U  << GPDMA0_MASKDSTTRAN_WE_CH1_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH2_Pos        (10U)\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH2_Msk        (0x00000001U  << GPDMA0_MASKDSTTRAN_WE_CH2_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH3_Pos        (11U)\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH3_Msk        (0x00000001U  << GPDMA0_MASKDSTTRAN_WE_CH3_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH4_Pos        (12U)\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH4_Msk        (0x00000001U  << GPDMA0_MASKDSTTRAN_WE_CH4_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH5_Pos        (13U)\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH5_Msk        (0x00000001U  << GPDMA0_MASKDSTTRAN_WE_CH5_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH6_Pos        (14U)\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH6_Msk        (0x00000001U  << GPDMA0_MASKDSTTRAN_WE_CH6_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH7_Pos        (15U)\r
-#define   GPDMA0_MASKDSTTRAN_WE_CH7_Msk        (0x00000001U  << GPDMA0_MASKDSTTRAN_WE_CH7_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_CH0_Pos   (0U)\r
-#define   GPDMA0_MASKDSTTRAN_CH0_Msk   (0x00000001U  << GPDMA0_MASKDSTTRAN_CH0_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_CH1_Pos   (1U)\r
-#define   GPDMA0_MASKDSTTRAN_CH1_Msk   (0x00000001U  << GPDMA0_MASKDSTTRAN_CH1_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_CH2_Pos   (2U)\r
-#define   GPDMA0_MASKDSTTRAN_CH2_Msk   (0x00000001U  << GPDMA0_MASKDSTTRAN_CH2_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_CH3_Pos   (3U)\r
-#define   GPDMA0_MASKDSTTRAN_CH3_Msk   (0x00000001U  << GPDMA0_MASKDSTTRAN_CH3_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_CH4_Pos   (4U)\r
-#define   GPDMA0_MASKDSTTRAN_CH4_Msk   (0x00000001U  << GPDMA0_MASKDSTTRAN_CH4_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_CH5_Pos   (5U)\r
-#define   GPDMA0_MASKDSTTRAN_CH5_Msk   (0x00000001U  << GPDMA0_MASKDSTTRAN_CH5_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_CH6_Pos   (6U)\r
-#define   GPDMA0_MASKDSTTRAN_CH6_Msk   (0x00000001U  << GPDMA0_MASKDSTTRAN_CH6_Pos)\r
-\r
-#define   GPDMA0_MASKDSTTRAN_CH7_Pos   (7U)\r
-#define   GPDMA0_MASKDSTTRAN_CH7_Msk   (0x00000001U  << GPDMA0_MASKDSTTRAN_CH7_Pos)\r
-\r
-/* GPDMA0_MASKERR  =  Mask for Raw IntErr Status*/\r
-#define   GPDMA0_MASKERR_WE_CH0_Pos    (8U)\r
-#define   GPDMA0_MASKERR_WE_CH0_Msk    (0x00000001U  << GPDMA0_MASKERR_WE_CH0_Pos)\r
-\r
-#define   GPDMA0_MASKERR_WE_CH1_Pos    (9U)\r
-#define   GPDMA0_MASKERR_WE_CH1_Msk    (0x00000001U  << GPDMA0_MASKERR_WE_CH1_Pos)\r
-\r
-#define   GPDMA0_MASKERR_WE_CH2_Pos    (10U)\r
-#define   GPDMA0_MASKERR_WE_CH2_Msk    (0x00000001U  << GPDMA0_MASKERR_WE_CH2_Pos)\r
-\r
-#define   GPDMA0_MASKERR_WE_CH3_Pos    (11U)\r
-#define   GPDMA0_MASKERR_WE_CH3_Msk    (0x00000001U  << GPDMA0_MASKERR_WE_CH3_Pos)\r
-\r
-#define   GPDMA0_MASKERR_WE_CH4_Pos    (12U)\r
-#define   GPDMA0_MASKERR_WE_CH4_Msk    (0x00000001U  << GPDMA0_MASKERR_WE_CH4_Pos)\r
-\r
-#define   GPDMA0_MASKERR_WE_CH5_Pos    (13U)\r
-#define   GPDMA0_MASKERR_WE_CH5_Msk    (0x00000001U  << GPDMA0_MASKERR_WE_CH5_Pos)\r
-\r
-#define   GPDMA0_MASKERR_WE_CH6_Pos    (14U)\r
-#define   GPDMA0_MASKERR_WE_CH6_Msk    (0x00000001U  << GPDMA0_MASKERR_WE_CH6_Pos)\r
-\r
-#define   GPDMA0_MASKERR_WE_CH7_Pos    (15U)\r
-#define   GPDMA0_MASKERR_WE_CH7_Msk    (0x00000001U  << GPDMA0_MASKERR_WE_CH7_Pos)\r
-\r
-#define   GPDMA0_MASKERR_CH0_Pos       (0U)\r
-#define   GPDMA0_MASKERR_CH0_Msk       (0x00000001U  << GPDMA0_MASKERR_CH0_Pos)\r
-\r
-#define   GPDMA0_MASKERR_CH1_Pos       (1U)\r
-#define   GPDMA0_MASKERR_CH1_Msk       (0x00000001U  << GPDMA0_MASKERR_CH1_Pos)\r
-\r
-#define   GPDMA0_MASKERR_CH2_Pos       (2U)\r
-#define   GPDMA0_MASKERR_CH2_Msk       (0x00000001U  << GPDMA0_MASKERR_CH2_Pos)\r
-\r
-#define   GPDMA0_MASKERR_CH3_Pos       (3U)\r
-#define   GPDMA0_MASKERR_CH3_Msk       (0x00000001U  << GPDMA0_MASKERR_CH3_Pos)\r
-\r
-#define   GPDMA0_MASKERR_CH4_Pos       (4U)\r
-#define   GPDMA0_MASKERR_CH4_Msk       (0x00000001U  << GPDMA0_MASKERR_CH4_Pos)\r
-\r
-#define   GPDMA0_MASKERR_CH5_Pos       (5U)\r
-#define   GPDMA0_MASKERR_CH5_Msk       (0x00000001U  << GPDMA0_MASKERR_CH5_Pos)\r
-\r
-#define   GPDMA0_MASKERR_CH6_Pos       (6U)\r
-#define   GPDMA0_MASKERR_CH6_Msk       (0x00000001U  << GPDMA0_MASKERR_CH6_Pos)\r
-\r
-#define   GPDMA0_MASKERR_CH7_Pos       (7U)\r
-#define   GPDMA0_MASKERR_CH7_Msk       (0x00000001U  << GPDMA0_MASKERR_CH7_Pos)\r
-\r
-/* GPDMA0_CLEARTFR  =  IntTfr Status*/\r
-#define   GPDMA0_CLEARTFR_CH0_Pos      (0U)\r
-#define   GPDMA0_CLEARTFR_CH0_Msk      (0x00000001U  << GPDMA0_CLEARTFR_CH0_Pos)\r
-\r
-#define   GPDMA0_CLEARTFR_CH1_Pos      (1U)\r
-#define   GPDMA0_CLEARTFR_CH1_Msk      (0x00000001U  << GPDMA0_CLEARTFR_CH1_Pos)\r
-\r
-#define   GPDMA0_CLEARTFR_CH2_Pos      (2U)\r
-#define   GPDMA0_CLEARTFR_CH2_Msk      (0x00000001U  << GPDMA0_CLEARTFR_CH2_Pos)\r
-\r
-#define   GPDMA0_CLEARTFR_CH3_Pos      (3U)\r
-#define   GPDMA0_CLEARTFR_CH3_Msk      (0x00000001U  << GPDMA0_CLEARTFR_CH3_Pos)\r
-\r
-#define   GPDMA0_CLEARTFR_CH4_Pos      (4U)\r
-#define   GPDMA0_CLEARTFR_CH4_Msk      (0x00000001U  << GPDMA0_CLEARTFR_CH4_Pos)\r
-\r
-#define   GPDMA0_CLEARTFR_CH5_Pos      (5U)\r
-#define   GPDMA0_CLEARTFR_CH5_Msk      (0x00000001U  << GPDMA0_CLEARTFR_CH5_Pos)\r
-\r
-#define   GPDMA0_CLEARTFR_CH6_Pos      (6U)\r
-#define   GPDMA0_CLEARTFR_CH6_Msk      (0x00000001U  << GPDMA0_CLEARTFR_CH6_Pos)\r
-\r
-#define   GPDMA0_CLEARTFR_CH7_Pos      (7U)\r
-#define   GPDMA0_CLEARTFR_CH7_Msk      (0x00000001U  << GPDMA0_CLEARTFR_CH7_Pos)\r
-\r
-/* GPDMA0_CLEARBLOCK  =  IntBlock Status*/\r
-#define   GPDMA0_CLEARBLOCK_CH0_Pos    (0U)\r
-#define   GPDMA0_CLEARBLOCK_CH0_Msk    (0x00000001U  << GPDMA0_CLEARBLOCK_CH0_Pos)\r
-\r
-#define   GPDMA0_CLEARBLOCK_CH1_Pos    (1U)\r
-#define   GPDMA0_CLEARBLOCK_CH1_Msk    (0x00000001U  << GPDMA0_CLEARBLOCK_CH1_Pos)\r
-\r
-#define   GPDMA0_CLEARBLOCK_CH2_Pos    (2U)\r
-#define   GPDMA0_CLEARBLOCK_CH2_Msk    (0x00000001U  << GPDMA0_CLEARBLOCK_CH2_Pos)\r
-\r
-#define   GPDMA0_CLEARBLOCK_CH3_Pos    (3U)\r
-#define   GPDMA0_CLEARBLOCK_CH3_Msk    (0x00000001U  << GPDMA0_CLEARBLOCK_CH3_Pos)\r
-\r
-#define   GPDMA0_CLEARBLOCK_CH4_Pos    (4U)\r
-#define   GPDMA0_CLEARBLOCK_CH4_Msk    (0x00000001U  << GPDMA0_CLEARBLOCK_CH4_Pos)\r
-\r
-#define   GPDMA0_CLEARBLOCK_CH5_Pos    (5U)\r
-#define   GPDMA0_CLEARBLOCK_CH5_Msk    (0x00000001U  << GPDMA0_CLEARBLOCK_CH5_Pos)\r
-\r
-#define   GPDMA0_CLEARBLOCK_CH6_Pos    (6U)\r
-#define   GPDMA0_CLEARBLOCK_CH6_Msk    (0x00000001U  << GPDMA0_CLEARBLOCK_CH6_Pos)\r
-\r
-#define   GPDMA0_CLEARBLOCK_CH7_Pos    (7U)\r
-#define   GPDMA0_CLEARBLOCK_CH7_Msk    (0x00000001U  << GPDMA0_CLEARBLOCK_CH7_Pos)\r
-\r
-/* GPDMA0_CLEARSRCTRAN  =  IntSrcTran Status*/\r
-#define   GPDMA0_CLEARSRCTRAN_CH0_Pos          (0U)\r
-#define   GPDMA0_CLEARSRCTRAN_CH0_Msk          (0x00000001U  << GPDMA0_CLEARSRCTRAN_CH0_Pos)\r
-\r
-#define   GPDMA0_CLEARSRCTRAN_CH1_Pos          (1U)\r
-#define   GPDMA0_CLEARSRCTRAN_CH1_Msk          (0x00000001U  << GPDMA0_CLEARSRCTRAN_CH1_Pos)\r
-\r
-#define   GPDMA0_CLEARSRCTRAN_CH2_Pos          (2U)\r
-#define   GPDMA0_CLEARSRCTRAN_CH2_Msk          (0x00000001U  << GPDMA0_CLEARSRCTRAN_CH2_Pos)\r
-\r
-#define   GPDMA0_CLEARSRCTRAN_CH3_Pos          (3U)\r
-#define   GPDMA0_CLEARSRCTRAN_CH3_Msk          (0x00000001U  << GPDMA0_CLEARSRCTRAN_CH3_Pos)\r
-\r
-#define   GPDMA0_CLEARSRCTRAN_CH4_Pos          (4U)\r
-#define   GPDMA0_CLEARSRCTRAN_CH4_Msk          (0x00000001U  << GPDMA0_CLEARSRCTRAN_CH4_Pos)\r
-\r
-#define   GPDMA0_CLEARSRCTRAN_CH5_Pos          (5U)\r
-#define   GPDMA0_CLEARSRCTRAN_CH5_Msk          (0x00000001U  << GPDMA0_CLEARSRCTRAN_CH5_Pos)\r
-\r
-#define   GPDMA0_CLEARSRCTRAN_CH6_Pos          (6U)\r
-#define   GPDMA0_CLEARSRCTRAN_CH6_Msk          (0x00000001U  << GPDMA0_CLEARSRCTRAN_CH6_Pos)\r
-\r
-#define   GPDMA0_CLEARSRCTRAN_CH7_Pos          (7U)\r
-#define   GPDMA0_CLEARSRCTRAN_CH7_Msk          (0x00000001U  << GPDMA0_CLEARSRCTRAN_CH7_Pos)\r
-\r
-/* GPDMA0_CLEARDSTTRAN  =  IntBlock Status*/\r
-#define   GPDMA0_CLEARDSTTRAN_CH0_Pos          (0U)\r
-#define   GPDMA0_CLEARDSTTRAN_CH0_Msk          (0x00000001U  << GPDMA0_CLEARDSTTRAN_CH0_Pos)\r
-\r
-#define   GPDMA0_CLEARDSTTRAN_CH1_Pos          (1U)\r
-#define   GPDMA0_CLEARDSTTRAN_CH1_Msk          (0x00000001U  << GPDMA0_CLEARDSTTRAN_CH1_Pos)\r
-\r
-#define   GPDMA0_CLEARDSTTRAN_CH2_Pos          (2U)\r
-#define   GPDMA0_CLEARDSTTRAN_CH2_Msk          (0x00000001U  << GPDMA0_CLEARDSTTRAN_CH2_Pos)\r
-\r
-#define   GPDMA0_CLEARDSTTRAN_CH3_Pos          (3U)\r
-#define   GPDMA0_CLEARDSTTRAN_CH3_Msk          (0x00000001U  << GPDMA0_CLEARDSTTRAN_CH3_Pos)\r
-\r
-#define   GPDMA0_CLEARDSTTRAN_CH4_Pos          (4U)\r
-#define   GPDMA0_CLEARDSTTRAN_CH4_Msk          (0x00000001U  << GPDMA0_CLEARDSTTRAN_CH4_Pos)\r
-\r
-#define   GPDMA0_CLEARDSTTRAN_CH5_Pos          (5U)\r
-#define   GPDMA0_CLEARDSTTRAN_CH5_Msk          (0x00000001U  << GPDMA0_CLEARDSTTRAN_CH5_Pos)\r
-\r
-#define   GPDMA0_CLEARDSTTRAN_CH6_Pos          (6U)\r
-#define   GPDMA0_CLEARDSTTRAN_CH6_Msk          (0x00000001U  << GPDMA0_CLEARDSTTRAN_CH6_Pos)\r
-\r
-#define   GPDMA0_CLEARDSTTRAN_CH7_Pos          (7U)\r
-#define   GPDMA0_CLEARDSTTRAN_CH7_Msk          (0x00000001U  << GPDMA0_CLEARDSTTRAN_CH7_Pos)\r
-\r
-/* GPDMA0_CLEARERR  =  IntErr Status*/\r
-#define   GPDMA0_CLEARERR_CH0_Pos      (0U)\r
-#define   GPDMA0_CLEARERR_CH0_Msk      (0x00000001U  << GPDMA0_CLEARERR_CH0_Pos)\r
-\r
-#define   GPDMA0_CLEARERR_CH1_Pos      (1U)\r
-#define   GPDMA0_CLEARERR_CH1_Msk      (0x00000001U  << GPDMA0_CLEARERR_CH1_Pos)\r
-\r
-#define   GPDMA0_CLEARERR_CH2_Pos      (2U)\r
-#define   GPDMA0_CLEARERR_CH2_Msk      (0x00000001U  << GPDMA0_CLEARERR_CH2_Pos)\r
-\r
-#define   GPDMA0_CLEARERR_CH3_Pos      (3U)\r
-#define   GPDMA0_CLEARERR_CH3_Msk      (0x00000001U  << GPDMA0_CLEARERR_CH3_Pos)\r
-\r
-#define   GPDMA0_CLEARERR_CH4_Pos      (4U)\r
-#define   GPDMA0_CLEARERR_CH4_Msk      (0x00000001U  << GPDMA0_CLEARERR_CH4_Pos)\r
-\r
-#define   GPDMA0_CLEARERR_CH5_Pos      (5U)\r
-#define   GPDMA0_CLEARERR_CH5_Msk      (0x00000001U  << GPDMA0_CLEARERR_CH5_Pos)\r
-\r
-#define   GPDMA0_CLEARERR_CH6_Pos      (6U)\r
-#define   GPDMA0_CLEARERR_CH6_Msk      (0x00000001U  << GPDMA0_CLEARERR_CH6_Pos)\r
-\r
-#define   GPDMA0_CLEARERR_CH7_Pos      (7U)\r
-#define   GPDMA0_CLEARERR_CH7_Msk      (0x00000001U  << GPDMA0_CLEARERR_CH7_Pos)\r
-\r
-/* GPDMA0_STATUSINT  =  Combined Interrupt Status Register*/\r
-#define   GPDMA0_STATUSINT_ERR_Pos     (4U)\r
-#define   GPDMA0_STATUSINT_ERR_Msk     (0x00000001U  << GPDMA0_STATUSINT_ERR_Pos)\r
-\r
-#define   GPDMA0_STATUSINT_DSTT_Pos    (3U)\r
-#define   GPDMA0_STATUSINT_DSTT_Msk    (0x00000001U  << GPDMA0_STATUSINT_DSTT_Pos)\r
-\r
-#define   GPDMA0_STATUSINT_SRCT_Pos    (2U)\r
-#define   GPDMA0_STATUSINT_SRCT_Msk    (0x00000001U  << GPDMA0_STATUSINT_SRCT_Pos)\r
-\r
-#define   GPDMA0_STATUSINT_BLOCK_Pos   (1U)\r
-#define   GPDMA0_STATUSINT_BLOCK_Msk   (0x00000001U  << GPDMA0_STATUSINT_BLOCK_Pos)\r
-\r
-#define   GPDMA0_STATUSINT_TFR_Pos     (0U)\r
-#define   GPDMA0_STATUSINT_TFR_Msk     (0x00000001U  << GPDMA0_STATUSINT_TFR_Pos)\r
-\r
-/* GPDMA0_REQSRCREG  =  Source Software Transaction Request Register*/\r
-#define   GPDMA0_REQSRCREG_WE_CH0_Pos          (8U)\r
-#define   GPDMA0_REQSRCREG_WE_CH0_Msk          (0x00000001U  << GPDMA0_REQSRCREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_WE_CH1_Pos          (9U)\r
-#define   GPDMA0_REQSRCREG_WE_CH1_Msk          (0x00000001U  << GPDMA0_REQSRCREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_WE_CH2_Pos          (10U)\r
-#define   GPDMA0_REQSRCREG_WE_CH2_Msk          (0x00000001U  << GPDMA0_REQSRCREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_WE_CH3_Pos          (11U)\r
-#define   GPDMA0_REQSRCREG_WE_CH3_Msk          (0x00000001U  << GPDMA0_REQSRCREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_WE_CH4_Pos          (12U)\r
-#define   GPDMA0_REQSRCREG_WE_CH4_Msk          (0x00000001U  << GPDMA0_REQSRCREG_WE_CH4_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_WE_CH5_Pos          (13U)\r
-#define   GPDMA0_REQSRCREG_WE_CH5_Msk          (0x00000001U  << GPDMA0_REQSRCREG_WE_CH5_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_WE_CH6_Pos          (14U)\r
-#define   GPDMA0_REQSRCREG_WE_CH6_Msk          (0x00000001U  << GPDMA0_REQSRCREG_WE_CH6_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_WE_CH7_Pos          (15U)\r
-#define   GPDMA0_REQSRCREG_WE_CH7_Msk          (0x00000001U  << GPDMA0_REQSRCREG_WE_CH7_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_CH0_Pos     (0U)\r
-#define   GPDMA0_REQSRCREG_CH0_Msk     (0x00000001U  << GPDMA0_REQSRCREG_CH0_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_CH1_Pos     (1U)\r
-#define   GPDMA0_REQSRCREG_CH1_Msk     (0x00000001U  << GPDMA0_REQSRCREG_CH1_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_CH2_Pos     (2U)\r
-#define   GPDMA0_REQSRCREG_CH2_Msk     (0x00000001U  << GPDMA0_REQSRCREG_CH2_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_CH3_Pos     (3U)\r
-#define   GPDMA0_REQSRCREG_CH3_Msk     (0x00000001U  << GPDMA0_REQSRCREG_CH3_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_CH4_Pos     (4U)\r
-#define   GPDMA0_REQSRCREG_CH4_Msk     (0x00000001U  << GPDMA0_REQSRCREG_CH4_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_CH5_Pos     (5U)\r
-#define   GPDMA0_REQSRCREG_CH5_Msk     (0x00000001U  << GPDMA0_REQSRCREG_CH5_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_CH6_Pos     (6U)\r
-#define   GPDMA0_REQSRCREG_CH6_Msk     (0x00000001U  << GPDMA0_REQSRCREG_CH6_Pos)\r
-\r
-#define   GPDMA0_REQSRCREG_CH7_Pos     (7U)\r
-#define   GPDMA0_REQSRCREG_CH7_Msk     (0x00000001U  << GPDMA0_REQSRCREG_CH7_Pos)\r
-\r
-/* GPDMA0_REQDSTREG  =  Destination Software Transaction Request Register*/\r
-#define   GPDMA0_REQDSTREG_WE_CH0_Pos          (8U)\r
-#define   GPDMA0_REQDSTREG_WE_CH0_Msk          (0x00000001U  << GPDMA0_REQDSTREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_WE_CH1_Pos          (9U)\r
-#define   GPDMA0_REQDSTREG_WE_CH1_Msk          (0x00000001U  << GPDMA0_REQDSTREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_WE_CH2_Pos          (10U)\r
-#define   GPDMA0_REQDSTREG_WE_CH2_Msk          (0x00000001U  << GPDMA0_REQDSTREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_WE_CH3_Pos          (11U)\r
-#define   GPDMA0_REQDSTREG_WE_CH3_Msk          (0x00000001U  << GPDMA0_REQDSTREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_WE_CH4_Pos          (12U)\r
-#define   GPDMA0_REQDSTREG_WE_CH4_Msk          (0x00000001U  << GPDMA0_REQDSTREG_WE_CH4_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_WE_CH5_Pos          (13U)\r
-#define   GPDMA0_REQDSTREG_WE_CH5_Msk          (0x00000001U  << GPDMA0_REQDSTREG_WE_CH5_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_WE_CH6_Pos          (14U)\r
-#define   GPDMA0_REQDSTREG_WE_CH6_Msk          (0x00000001U  << GPDMA0_REQDSTREG_WE_CH6_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_WE_CH7_Pos          (15U)\r
-#define   GPDMA0_REQDSTREG_WE_CH7_Msk          (0x00000001U  << GPDMA0_REQDSTREG_WE_CH7_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_CH0_Pos     (0U)\r
-#define   GPDMA0_REQDSTREG_CH0_Msk     (0x00000001U  << GPDMA0_REQDSTREG_CH0_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_CH1_Pos     (1U)\r
-#define   GPDMA0_REQDSTREG_CH1_Msk     (0x00000001U  << GPDMA0_REQDSTREG_CH1_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_CH2_Pos     (2U)\r
-#define   GPDMA0_REQDSTREG_CH2_Msk     (0x00000001U  << GPDMA0_REQDSTREG_CH2_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_CH3_Pos     (3U)\r
-#define   GPDMA0_REQDSTREG_CH3_Msk     (0x00000001U  << GPDMA0_REQDSTREG_CH3_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_CH4_Pos     (4U)\r
-#define   GPDMA0_REQDSTREG_CH4_Msk     (0x00000001U  << GPDMA0_REQDSTREG_CH4_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_CH5_Pos     (5U)\r
-#define   GPDMA0_REQDSTREG_CH5_Msk     (0x00000001U  << GPDMA0_REQDSTREG_CH5_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_CH6_Pos     (6U)\r
-#define   GPDMA0_REQDSTREG_CH6_Msk     (0x00000001U  << GPDMA0_REQDSTREG_CH6_Pos)\r
-\r
-#define   GPDMA0_REQDSTREG_CH7_Pos     (7U)\r
-#define   GPDMA0_REQDSTREG_CH7_Msk     (0x00000001U  << GPDMA0_REQDSTREG_CH7_Pos)\r
-\r
-/* GPDMA0_SGLREQSRCREG  =  Single Source Transaction Request Register*/\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH0_Pos       (8U)\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH0_Msk       (0x00000001U  << GPDMA0_SGLREQSRCREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH1_Pos       (9U)\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH1_Msk       (0x00000001U  << GPDMA0_SGLREQSRCREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH2_Pos       (10U)\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH2_Msk       (0x00000001U  << GPDMA0_SGLREQSRCREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH3_Pos       (11U)\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH3_Msk       (0x00000001U  << GPDMA0_SGLREQSRCREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH4_Pos       (12U)\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH4_Msk       (0x00000001U  << GPDMA0_SGLREQSRCREG_WE_CH4_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH5_Pos       (13U)\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH5_Msk       (0x00000001U  << GPDMA0_SGLREQSRCREG_WE_CH5_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH6_Pos       (14U)\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH6_Msk       (0x00000001U  << GPDMA0_SGLREQSRCREG_WE_CH6_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH7_Pos       (15U)\r
-#define   GPDMA0_SGLREQSRCREG_WE_CH7_Msk       (0x00000001U  << GPDMA0_SGLREQSRCREG_WE_CH7_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_CH0_Pos          (0U)\r
-#define   GPDMA0_SGLREQSRCREG_CH0_Msk          (0x00000001U  << GPDMA0_SGLREQSRCREG_CH0_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_CH1_Pos          (1U)\r
-#define   GPDMA0_SGLREQSRCREG_CH1_Msk          (0x00000001U  << GPDMA0_SGLREQSRCREG_CH1_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_CH2_Pos          (2U)\r
-#define   GPDMA0_SGLREQSRCREG_CH2_Msk          (0x00000001U  << GPDMA0_SGLREQSRCREG_CH2_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_CH3_Pos          (3U)\r
-#define   GPDMA0_SGLREQSRCREG_CH3_Msk          (0x00000001U  << GPDMA0_SGLREQSRCREG_CH3_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_CH4_Pos          (4U)\r
-#define   GPDMA0_SGLREQSRCREG_CH4_Msk          (0x00000001U  << GPDMA0_SGLREQSRCREG_CH4_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_CH5_Pos          (5U)\r
-#define   GPDMA0_SGLREQSRCREG_CH5_Msk          (0x00000001U  << GPDMA0_SGLREQSRCREG_CH5_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_CH6_Pos          (6U)\r
-#define   GPDMA0_SGLREQSRCREG_CH6_Msk          (0x00000001U  << GPDMA0_SGLREQSRCREG_CH6_Pos)\r
-\r
-#define   GPDMA0_SGLREQSRCREG_CH7_Pos          (7U)\r
-#define   GPDMA0_SGLREQSRCREG_CH7_Msk          (0x00000001U  << GPDMA0_SGLREQSRCREG_CH7_Pos)\r
-\r
-/* GPDMA0_SGLREQDSTREG  =  Single Destination Transaction Request Register*/\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH0_Pos       (8U)\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH0_Msk       (0x00000001U  << GPDMA0_SGLREQDSTREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH1_Pos       (9U)\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH1_Msk       (0x00000001U  << GPDMA0_SGLREQDSTREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH2_Pos       (10U)\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH2_Msk       (0x00000001U  << GPDMA0_SGLREQDSTREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH3_Pos       (11U)\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH3_Msk       (0x00000001U  << GPDMA0_SGLREQDSTREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH4_Pos       (12U)\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH4_Msk       (0x00000001U  << GPDMA0_SGLREQDSTREG_WE_CH4_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH5_Pos       (13U)\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH5_Msk       (0x00000001U  << GPDMA0_SGLREQDSTREG_WE_CH5_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH6_Pos       (14U)\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH6_Msk       (0x00000001U  << GPDMA0_SGLREQDSTREG_WE_CH6_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH7_Pos       (15U)\r
-#define   GPDMA0_SGLREQDSTREG_WE_CH7_Msk       (0x00000001U  << GPDMA0_SGLREQDSTREG_WE_CH7_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_CH0_Pos          (0U)\r
-#define   GPDMA0_SGLREQDSTREG_CH0_Msk          (0x00000001U  << GPDMA0_SGLREQDSTREG_CH0_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_CH1_Pos          (1U)\r
-#define   GPDMA0_SGLREQDSTREG_CH1_Msk          (0x00000001U  << GPDMA0_SGLREQDSTREG_CH1_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_CH2_Pos          (2U)\r
-#define   GPDMA0_SGLREQDSTREG_CH2_Msk          (0x00000001U  << GPDMA0_SGLREQDSTREG_CH2_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_CH3_Pos          (3U)\r
-#define   GPDMA0_SGLREQDSTREG_CH3_Msk          (0x00000001U  << GPDMA0_SGLREQDSTREG_CH3_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_CH4_Pos          (4U)\r
-#define   GPDMA0_SGLREQDSTREG_CH4_Msk          (0x00000001U  << GPDMA0_SGLREQDSTREG_CH4_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_CH5_Pos          (5U)\r
-#define   GPDMA0_SGLREQDSTREG_CH5_Msk          (0x00000001U  << GPDMA0_SGLREQDSTREG_CH5_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_CH6_Pos          (6U)\r
-#define   GPDMA0_SGLREQDSTREG_CH6_Msk          (0x00000001U  << GPDMA0_SGLREQDSTREG_CH6_Pos)\r
-\r
-#define   GPDMA0_SGLREQDSTREG_CH7_Pos          (7U)\r
-#define   GPDMA0_SGLREQDSTREG_CH7_Msk          (0x00000001U  << GPDMA0_SGLREQDSTREG_CH7_Pos)\r
-\r
-/* GPDMA0_LSTSRCREG  =  Last Source Transaction Request Register*/\r
-#define   GPDMA0_LSTSRCREG_WE_CH0_Pos          (8U)\r
-#define   GPDMA0_LSTSRCREG_WE_CH0_Msk          (0x00000001U  << GPDMA0_LSTSRCREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_WE_CH1_Pos          (9U)\r
-#define   GPDMA0_LSTSRCREG_WE_CH1_Msk          (0x00000001U  << GPDMA0_LSTSRCREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_WE_CH2_Pos          (10U)\r
-#define   GPDMA0_LSTSRCREG_WE_CH2_Msk          (0x00000001U  << GPDMA0_LSTSRCREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_WE_CH3_Pos          (11U)\r
-#define   GPDMA0_LSTSRCREG_WE_CH3_Msk          (0x00000001U  << GPDMA0_LSTSRCREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_WE_CH4_Pos          (12U)\r
-#define   GPDMA0_LSTSRCREG_WE_CH4_Msk          (0x00000001U  << GPDMA0_LSTSRCREG_WE_CH4_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_WE_CH5_Pos          (13U)\r
-#define   GPDMA0_LSTSRCREG_WE_CH5_Msk          (0x00000001U  << GPDMA0_LSTSRCREG_WE_CH5_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_WE_CH6_Pos          (14U)\r
-#define   GPDMA0_LSTSRCREG_WE_CH6_Msk          (0x00000001U  << GPDMA0_LSTSRCREG_WE_CH6_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_WE_CH7_Pos          (15U)\r
-#define   GPDMA0_LSTSRCREG_WE_CH7_Msk          (0x00000001U  << GPDMA0_LSTSRCREG_WE_CH7_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_CH0_Pos     (0U)\r
-#define   GPDMA0_LSTSRCREG_CH0_Msk     (0x00000001U  << GPDMA0_LSTSRCREG_CH0_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_CH1_Pos     (1U)\r
-#define   GPDMA0_LSTSRCREG_CH1_Msk     (0x00000001U  << GPDMA0_LSTSRCREG_CH1_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_CH2_Pos     (2U)\r
-#define   GPDMA0_LSTSRCREG_CH2_Msk     (0x00000001U  << GPDMA0_LSTSRCREG_CH2_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_CH3_Pos     (3U)\r
-#define   GPDMA0_LSTSRCREG_CH3_Msk     (0x00000001U  << GPDMA0_LSTSRCREG_CH3_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_CH4_Pos     (4U)\r
-#define   GPDMA0_LSTSRCREG_CH4_Msk     (0x00000001U  << GPDMA0_LSTSRCREG_CH4_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_CH5_Pos     (5U)\r
-#define   GPDMA0_LSTSRCREG_CH5_Msk     (0x00000001U  << GPDMA0_LSTSRCREG_CH5_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_CH6_Pos     (6U)\r
-#define   GPDMA0_LSTSRCREG_CH6_Msk     (0x00000001U  << GPDMA0_LSTSRCREG_CH6_Pos)\r
-\r
-#define   GPDMA0_LSTSRCREG_CH7_Pos     (7U)\r
-#define   GPDMA0_LSTSRCREG_CH7_Msk     (0x00000001U  << GPDMA0_LSTSRCREG_CH7_Pos)\r
-\r
-/* GPDMA0_LSTDSTREG  =  Last Destination Transaction Request Register*/\r
-#define   GPDMA0_LSTDSTREG_WE_CH0_Pos          (8U)\r
-#define   GPDMA0_LSTDSTREG_WE_CH0_Msk          (0x00000001U  << GPDMA0_LSTDSTREG_WE_CH0_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_WE_CH1_Pos          (9U)\r
-#define   GPDMA0_LSTDSTREG_WE_CH1_Msk          (0x00000001U  << GPDMA0_LSTDSTREG_WE_CH1_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_WE_CH2_Pos          (10U)\r
-#define   GPDMA0_LSTDSTREG_WE_CH2_Msk          (0x00000001U  << GPDMA0_LSTDSTREG_WE_CH2_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_WE_CH3_Pos          (11U)\r
-#define   GPDMA0_LSTDSTREG_WE_CH3_Msk          (0x00000001U  << GPDMA0_LSTDSTREG_WE_CH3_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_WE_CH4_Pos          (12U)\r
-#define   GPDMA0_LSTDSTREG_WE_CH4_Msk          (0x00000001U  << GPDMA0_LSTDSTREG_WE_CH4_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_WE_CH5_Pos          (13U)\r
-#define   GPDMA0_LSTDSTREG_WE_CH5_Msk          (0x00000001U  << GPDMA0_LSTDSTREG_WE_CH5_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_WE_CH6_Pos          (14U)\r
-#define   GPDMA0_LSTDSTREG_WE_CH6_Msk          (0x00000001U  << GPDMA0_LSTDSTREG_WE_CH6_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_WE_CH7_Pos          (15U)\r
-#define   GPDMA0_LSTDSTREG_WE_CH7_Msk          (0x00000001U  << GPDMA0_LSTDSTREG_WE_CH7_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_CH0_Pos     (0U)\r
-#define   GPDMA0_LSTDSTREG_CH0_Msk     (0x00000001U  << GPDMA0_LSTDSTREG_CH0_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_CH1_Pos     (1U)\r
-#define   GPDMA0_LSTDSTREG_CH1_Msk     (0x00000001U  << GPDMA0_LSTDSTREG_CH1_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_CH2_Pos     (2U)\r
-#define   GPDMA0_LSTDSTREG_CH2_Msk     (0x00000001U  << GPDMA0_LSTDSTREG_CH2_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_CH3_Pos     (3U)\r
-#define   GPDMA0_LSTDSTREG_CH3_Msk     (0x00000001U  << GPDMA0_LSTDSTREG_CH3_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_CH4_Pos     (4U)\r
-#define   GPDMA0_LSTDSTREG_CH4_Msk     (0x00000001U  << GPDMA0_LSTDSTREG_CH4_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_CH5_Pos     (5U)\r
-#define   GPDMA0_LSTDSTREG_CH5_Msk     (0x00000001U  << GPDMA0_LSTDSTREG_CH5_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_CH6_Pos     (6U)\r
-#define   GPDMA0_LSTDSTREG_CH6_Msk     (0x00000001U  << GPDMA0_LSTDSTREG_CH6_Pos)\r
-\r
-#define   GPDMA0_LSTDSTREG_CH7_Pos     (7U)\r
-#define   GPDMA0_LSTDSTREG_CH7_Msk     (0x00000001U  << GPDMA0_LSTDSTREG_CH7_Pos)\r
-\r
-/* GPDMA0_DMACFGREG  =  GPDMA Configuration Register*/\r
-#define   GPDMA0_DMACFGREG_DMA_EN_Pos          (0U)\r
-#define   GPDMA0_DMACFGREG_DMA_EN_Msk          (0x00000001U  << GPDMA0_DMACFGREG_DMA_EN_Pos)\r
-\r
-/* GPDMA0_CHENREG  =  GPDMA Channel Enable Register*/\r
-#define   GPDMA0_CHENREG_WE_CH_Pos     (8U)\r
-#define   GPDMA0_CHENREG_WE_CH_Msk     (0x000000FFU  << GPDMA0_CHENREG_WE_CH_Pos)\r
-\r
-#define   GPDMA0_CHENREG_CH_Pos        (0U)\r
-#define   GPDMA0_CHENREG_CH_Msk        (0x000000FFU  << GPDMA0_CHENREG_CH_Pos)\r
-\r
-/* GPDMA0_ID  =  GPDMA0 ID Register*/\r
-#define   GPDMA0_ID_VALUE_Pos          (0U)\r
-#define   GPDMA0_ID_VALUE_Msk          (0xFFFFFFFFU  << GPDMA0_ID_VALUE_Pos)\r
-\r
-/* GPDMA0_TYPE  =  GPDMA Component Type*/\r
-#define   GPDMA0_TYPE_VALUE_Pos        (0U)\r
-#define   GPDMA0_TYPE_VALUE_Msk        (0xFFFFFFFFU  << GPDMA0_TYPE_VALUE_Pos)\r
-\r
-/* GPDMA0_VERSION  =  DMA Component Version*/\r
-#define   GPDMA0_VERSION_VALUE_Pos     (0U)\r
-#define   GPDMA0_VERSION_VALUE_Msk     (0xFFFFFFFFU  << GPDMA0_VERSION_VALUE_Pos)\r
-\r
-\r
-\r
-/***   DSD Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* DSD_CLC  =  Clock Control Register*/\r
-#define   DSD_CLC_DISR_Pos     (0U)\r
-#define   DSD_CLC_DISR_Msk     (0x00000001U  << DSD_CLC_DISR_Pos)\r
-\r
-#define   DSD_CLC_DISS_Pos     (1U)\r
-#define   DSD_CLC_DISS_Msk     (0x00000001U  << DSD_CLC_DISS_Pos)\r
-\r
-#define   DSD_CLC_EDIS_Pos     (3U)\r
-#define   DSD_CLC_EDIS_Msk     (0x00000001U  << DSD_CLC_EDIS_Pos)\r
-\r
-/* DSD_ID  =  Module Identification Register*/\r
-#define   DSD_ID_MOD_REV_Pos   (0U)\r
-#define   DSD_ID_MOD_REV_Msk   (0x000000FFU  << DSD_ID_MOD_REV_Pos)\r
-\r
-#define   DSD_ID_MOD_TYPE_Pos          (8U)\r
-#define   DSD_ID_MOD_TYPE_Msk          (0x000000FFU  << DSD_ID_MOD_TYPE_Pos)\r
-\r
-#define   DSD_ID_MOD_NUMBER_Pos        (16U)\r
-#define   DSD_ID_MOD_NUMBER_Msk        (0x0000FFFFU  << DSD_ID_MOD_NUMBER_Pos)\r
-\r
-/* DSD_OCS  =  OCDS Control and Status Register*/\r
-#define   DSD_OCS_SUS_Pos      (24U)\r
-#define   DSD_OCS_SUS_Msk      (0x0000000FU  << DSD_OCS_SUS_Pos)\r
-\r
-#define   DSD_OCS_SUS_P_Pos    (28U)\r
-#define   DSD_OCS_SUS_P_Msk    (0x00000001U  << DSD_OCS_SUS_P_Pos)\r
-\r
-#define   DSD_OCS_SUSSTA_Pos   (29U)\r
-#define   DSD_OCS_SUSSTA_Msk   (0x00000001U  << DSD_OCS_SUSSTA_Pos)\r
-\r
-/* DSD_GLOBCFG  =  Global Configuration Register*/\r
-#define   DSD_GLOBCFG_MCSEL_Pos        (0U)\r
-#define   DSD_GLOBCFG_MCSEL_Msk        (0x00000007U  << DSD_GLOBCFG_MCSEL_Pos)\r
-\r
-/* DSD_GLOBRC  =  Global Run Control Register*/\r
-#define   DSD_GLOBRC_CHRUN_Pos         (0U)\r
-#define   DSD_GLOBRC_CHRUN_Msk         (0x0000000FU  << DSD_GLOBRC_CHRUN_Pos)\r
-\r
-/* DSD_CGCFG  =  Carrier Generator Configuration Register*/\r
-#define   DSD_CGCFG_CGMOD_Pos          (0U)\r
-#define   DSD_CGCFG_CGMOD_Msk          (0x00000003U  << DSD_CGCFG_CGMOD_Pos)\r
-\r
-#define   DSD_CGCFG_BREV_Pos   (2U)\r
-#define   DSD_CGCFG_BREV_Msk   (0x00000001U  << DSD_CGCFG_BREV_Pos)\r
-\r
-#define   DSD_CGCFG_SIGPOL_Pos         (3U)\r
-#define   DSD_CGCFG_SIGPOL_Msk         (0x00000001U  << DSD_CGCFG_SIGPOL_Pos)\r
-\r
-#define   DSD_CGCFG_DIVCG_Pos          (4U)\r
-#define   DSD_CGCFG_DIVCG_Msk          (0x0000000FU  << DSD_CGCFG_DIVCG_Pos)\r
-\r
-#define   DSD_CGCFG_RUN_Pos    (15U)\r
-#define   DSD_CGCFG_RUN_Msk    (0x00000001U  << DSD_CGCFG_RUN_Pos)\r
-\r
-#define   DSD_CGCFG_BITCOUNT_Pos       (16U)\r
-#define   DSD_CGCFG_BITCOUNT_Msk       (0x0000001FU  << DSD_CGCFG_BITCOUNT_Pos)\r
-\r
-#define   DSD_CGCFG_STEPCOUNT_Pos      (24U)\r
-#define   DSD_CGCFG_STEPCOUNT_Msk      (0x0000000FU  << DSD_CGCFG_STEPCOUNT_Pos)\r
-\r
-#define   DSD_CGCFG_STEPS_Pos          (28U)\r
-#define   DSD_CGCFG_STEPS_Msk          (0x00000001U  << DSD_CGCFG_STEPS_Pos)\r
-\r
-#define   DSD_CGCFG_STEPD_Pos          (29U)\r
-#define   DSD_CGCFG_STEPD_Msk          (0x00000001U  << DSD_CGCFG_STEPD_Pos)\r
-\r
-#define   DSD_CGCFG_SGNCG_Pos          (30U)\r
-#define   DSD_CGCFG_SGNCG_Msk          (0x00000001U  << DSD_CGCFG_SGNCG_Pos)\r
-\r
-/* DSD_EVFLAG  =  Event Flag Register*/\r
-#define   DSD_EVFLAG_RESEV0_Pos        (0U)\r
-#define   DSD_EVFLAG_RESEV0_Msk        (0x00000001U  << DSD_EVFLAG_RESEV0_Pos)\r
-\r
-#define   DSD_EVFLAG_RESEV1_Pos        (1U)\r
-#define   DSD_EVFLAG_RESEV1_Msk        (0x00000001U  << DSD_EVFLAG_RESEV1_Pos)\r
-\r
-#define   DSD_EVFLAG_RESEV2_Pos        (2U)\r
-#define   DSD_EVFLAG_RESEV2_Msk        (0x00000001U  << DSD_EVFLAG_RESEV2_Pos)\r
-\r
-#define   DSD_EVFLAG_RESEV3_Pos        (3U)\r
-#define   DSD_EVFLAG_RESEV3_Msk        (0x00000001U  << DSD_EVFLAG_RESEV3_Pos)\r
-\r
-#define   DSD_EVFLAG_ALEV0_Pos         (16U)\r
-#define   DSD_EVFLAG_ALEV0_Msk         (0x00000001U  << DSD_EVFLAG_ALEV0_Pos)\r
-\r
-#define   DSD_EVFLAG_ALEV1_Pos         (17U)\r
-#define   DSD_EVFLAG_ALEV1_Msk         (0x00000001U  << DSD_EVFLAG_ALEV1_Pos)\r
-\r
-#define   DSD_EVFLAG_ALEV2_Pos         (18U)\r
-#define   DSD_EVFLAG_ALEV2_Msk         (0x00000001U  << DSD_EVFLAG_ALEV2_Pos)\r
-\r
-#define   DSD_EVFLAG_ALEV3_Pos         (19U)\r
-#define   DSD_EVFLAG_ALEV3_Msk         (0x00000001U  << DSD_EVFLAG_ALEV3_Pos)\r
-\r
-#define   DSD_EVFLAG_ALEV4_Pos         (20U)\r
-#define   DSD_EVFLAG_ALEV4_Msk         (0x00000001U  << DSD_EVFLAG_ALEV4_Pos)\r
-\r
-#define   DSD_EVFLAG_ALEV5_Pos         (21U)\r
-#define   DSD_EVFLAG_ALEV5_Msk         (0x00000001U  << DSD_EVFLAG_ALEV5_Pos)\r
-\r
-#define   DSD_EVFLAG_ALEV6_Pos         (22U)\r
-#define   DSD_EVFLAG_ALEV6_Msk         (0x00000001U  << DSD_EVFLAG_ALEV6_Pos)\r
-\r
-#define   DSD_EVFLAG_ALEV7_Pos         (23U)\r
-#define   DSD_EVFLAG_ALEV7_Msk         (0x00000001U  << DSD_EVFLAG_ALEV7_Pos)\r
-\r
-#define   DSD_EVFLAG_ALEV8_Pos         (24U)\r
-#define   DSD_EVFLAG_ALEV8_Msk         (0x00000001U  << DSD_EVFLAG_ALEV8_Pos)\r
-\r
-#define   DSD_EVFLAG_ALEV9_Pos         (25U)\r
-#define   DSD_EVFLAG_ALEV9_Msk         (0x00000001U  << DSD_EVFLAG_ALEV9_Pos)\r
-\r
-/* DSD_EVFLAGCLR  =  Event Flag Clear Register*/\r
-#define   DSD_EVFLAGCLR_RESEC0_Pos     (0U)\r
-#define   DSD_EVFLAGCLR_RESEC0_Msk     (0x00000001U  << DSD_EVFLAGCLR_RESEC0_Pos)\r
-\r
-#define   DSD_EVFLAGCLR_RESEC1_Pos     (1U)\r
-#define   DSD_EVFLAGCLR_RESEC1_Msk     (0x00000001U  << DSD_EVFLAGCLR_RESEC1_Pos)\r
-\r
-#define   DSD_EVFLAGCLR_RESEC2_Pos     (2U)\r
-#define   DSD_EVFLAGCLR_RESEC2_Msk     (0x00000001U  << DSD_EVFLAGCLR_RESEC2_Pos)\r
-\r
-#define   DSD_EVFLAGCLR_RESEC3_Pos     (3U)\r
-#define   DSD_EVFLAGCLR_RESEC3_Msk     (0x00000001U  << DSD_EVFLAGCLR_RESEC3_Pos)\r
-\r
-#define   DSD_EVFLAGCLR_ALEC0_Pos      (16U)\r
-#define   DSD_EVFLAGCLR_ALEC0_Msk      (0x00000001U  << DSD_EVFLAGCLR_ALEC0_Pos)\r
-\r
-#define   DSD_EVFLAGCLR_ALEC1_Pos      (17U)\r
-#define   DSD_EVFLAGCLR_ALEC1_Msk      (0x00000001U  << DSD_EVFLAGCLR_ALEC1_Pos)\r
-\r
-#define   DSD_EVFLAGCLR_ALEC2_Pos      (18U)\r
-#define   DSD_EVFLAGCLR_ALEC2_Msk      (0x00000001U  << DSD_EVFLAGCLR_ALEC2_Pos)\r
-\r
-#define   DSD_EVFLAGCLR_ALEC3_Pos      (19U)\r
-#define   DSD_EVFLAGCLR_ALEC3_Msk      (0x00000001U  << DSD_EVFLAGCLR_ALEC3_Pos)\r
-\r
-/* DSD_CH_MODCFGx  =  Modulator Configuration Register 0*/\r
-#define   DSD_CH_MODCFG_DIVM_Pos       (16U)\r
-#define   DSD_CH_MODCFG_DIVM_Msk       (0x0000000FU  << DSD_CH_MODCFG_DIVM_Pos)\r
-\r
-#define   DSD_CH_MODCFG_DWC_Pos        (23U)\r
-#define   DSD_CH_MODCFG_DWC_Msk        (0x00000001U  << DSD_CH_MODCFG_DWC_Pos)\r
-\r
-/* DSD_CH_DICFGx  =  Demodulator Input Configuration Register 0*/\r
-#define   DSD_CH_DICFG_DSRC_Pos        (0U)\r
-#define   DSD_CH_DICFG_DSRC_Msk        (0x0000000FU  << DSD_CH_DICFG_DSRC_Pos)\r
-\r
-#define   DSD_CH_DICFG_DSWC_Pos        (7U)\r
-#define   DSD_CH_DICFG_DSWC_Msk        (0x00000001U  << DSD_CH_DICFG_DSWC_Pos)\r
-\r
-#define   DSD_CH_DICFG_ITRMODE_Pos     (8U)\r
-#define   DSD_CH_DICFG_ITRMODE_Msk     (0x00000003U  << DSD_CH_DICFG_ITRMODE_Pos)\r
-\r
-#define   DSD_CH_DICFG_TSTRMODE_Pos    (10U)\r
-#define   DSD_CH_DICFG_TSTRMODE_Msk    (0x00000003U  << DSD_CH_DICFG_TSTRMODE_Pos)\r
-\r
-#define   DSD_CH_DICFG_TRSEL_Pos       (12U)\r
-#define   DSD_CH_DICFG_TRSEL_Msk       (0x00000007U  << DSD_CH_DICFG_TRSEL_Pos)\r
-\r
-#define   DSD_CH_DICFG_TRWC_Pos        (15U)\r
-#define   DSD_CH_DICFG_TRWC_Msk        (0x00000001U  << DSD_CH_DICFG_TRWC_Pos)\r
-\r
-#define   DSD_CH_DICFG_CSRC_Pos        (16U)\r
-#define   DSD_CH_DICFG_CSRC_Msk        (0x0000000FU  << DSD_CH_DICFG_CSRC_Pos)\r
-\r
-#define   DSD_CH_DICFG_STROBE_Pos      (20U)\r
-#define   DSD_CH_DICFG_STROBE_Msk      (0x0000000FU  << DSD_CH_DICFG_STROBE_Pos)\r
-\r
-#define   DSD_CH_DICFG_SCWC_Pos        (31U)\r
-#define   DSD_CH_DICFG_SCWC_Msk        (0x00000001U  << DSD_CH_DICFG_SCWC_Pos)\r
-\r
-/* DSD_CH_FCFGCx  =  Filter Configuration Register 0, Main Comb Filter*/\r
-#define   DSD_CH_FCFGC_CFMDF_Pos       (0U)\r
-#define   DSD_CH_FCFGC_CFMDF_Msk       (0x000000FFU  << DSD_CH_FCFGC_CFMDF_Pos)\r
-\r
-#define   DSD_CH_FCFGC_CFMC_Pos        (8U)\r
-#define   DSD_CH_FCFGC_CFMC_Msk        (0x00000003U  << DSD_CH_FCFGC_CFMC_Pos)\r
-\r
-#define   DSD_CH_FCFGC_CFEN_Pos        (10U)\r
-#define   DSD_CH_FCFGC_CFEN_Msk        (0x00000001U  << DSD_CH_FCFGC_CFEN_Pos)\r
-\r
-#define   DSD_CH_FCFGC_SRGM_Pos        (14U)\r
-#define   DSD_CH_FCFGC_SRGM_Msk        (0x00000003U  << DSD_CH_FCFGC_SRGM_Pos)\r
-\r
-#define   DSD_CH_FCFGC_CFMSV_Pos       (16U)\r
-#define   DSD_CH_FCFGC_CFMSV_Msk       (0x000000FFU  << DSD_CH_FCFGC_CFMSV_Pos)\r
-\r
-#define   DSD_CH_FCFGC_CFMDCNT_Pos     (24U)\r
-#define   DSD_CH_FCFGC_CFMDCNT_Msk     (0x000000FFU  << DSD_CH_FCFGC_CFMDCNT_Pos)\r
-\r
-/* DSD_CH_FCFGAx  =  Filter Configuration Register 0, Auxiliary Filter*/\r
-#define   DSD_CH_FCFGA_CFADF_Pos       (0U)\r
-#define   DSD_CH_FCFGA_CFADF_Msk       (0x000000FFU  << DSD_CH_FCFGA_CFADF_Pos)\r
-\r
-#define   DSD_CH_FCFGA_CFAC_Pos        (8U)\r
-#define   DSD_CH_FCFGA_CFAC_Msk        (0x00000003U  << DSD_CH_FCFGA_CFAC_Pos)\r
-\r
-#define   DSD_CH_FCFGA_SRGA_Pos        (10U)\r
-#define   DSD_CH_FCFGA_SRGA_Msk        (0x00000003U  << DSD_CH_FCFGA_SRGA_Pos)\r
-\r
-#define   DSD_CH_FCFGA_ESEL_Pos        (12U)\r
-#define   DSD_CH_FCFGA_ESEL_Msk        (0x00000003U  << DSD_CH_FCFGA_ESEL_Pos)\r
-\r
-#define   DSD_CH_FCFGA_EGT_Pos         (14U)\r
-#define   DSD_CH_FCFGA_EGT_Msk         (0x00000001U  << DSD_CH_FCFGA_EGT_Pos)\r
-\r
-#define   DSD_CH_FCFGA_CFADCNT_Pos     (24U)\r
-#define   DSD_CH_FCFGA_CFADCNT_Msk     (0x000000FFU  << DSD_CH_FCFGA_CFADCNT_Pos)\r
-\r
-/* DSD_CH_IWCTRx  =  Integration Window Control Register 0*/\r
-#define   DSD_CH_IWCTR_NVALCNT_Pos     (0U)\r
-#define   DSD_CH_IWCTR_NVALCNT_Msk     (0x0000003FU  << DSD_CH_IWCTR_NVALCNT_Pos)\r
-\r
-#define   DSD_CH_IWCTR_INTEN_Pos       (7U)\r
-#define   DSD_CH_IWCTR_INTEN_Msk       (0x00000001U  << DSD_CH_IWCTR_INTEN_Pos)\r
-\r
-#define   DSD_CH_IWCTR_REPCNT_Pos      (8U)\r
-#define   DSD_CH_IWCTR_REPCNT_Msk      (0x0000000FU  << DSD_CH_IWCTR_REPCNT_Pos)\r
-\r
-#define   DSD_CH_IWCTR_REPVAL_Pos      (12U)\r
-#define   DSD_CH_IWCTR_REPVAL_Msk      (0x0000000FU  << DSD_CH_IWCTR_REPVAL_Pos)\r
-\r
-#define   DSD_CH_IWCTR_NVALDIS_Pos     (16U)\r
-#define   DSD_CH_IWCTR_NVALDIS_Msk     (0x0000003FU  << DSD_CH_IWCTR_NVALDIS_Pos)\r
-\r
-#define   DSD_CH_IWCTR_IWS_Pos         (23U)\r
-#define   DSD_CH_IWCTR_IWS_Msk         (0x00000001U  << DSD_CH_IWCTR_IWS_Pos)\r
-\r
-#define   DSD_CH_IWCTR_NVALINT_Pos     (24U)\r
-#define   DSD_CH_IWCTR_NVALINT_Msk     (0x0000003FU  << DSD_CH_IWCTR_NVALINT_Pos)\r
-\r
-/* DSD_CH_BOUNDSELx  =  Boundary Select Register 0*/\r
-#define   DSD_CH_BOUNDSEL_BOUNDARYL_Pos        (0U)\r
-#define   DSD_CH_BOUNDSEL_BOUNDARYL_Msk        (0x0000FFFFU  << DSD_CH_BOUNDSEL_BOUNDARYL_Pos)\r
-\r
-#define   DSD_CH_BOUNDSEL_BOUNDARYU_Pos        (16U)\r
-#define   DSD_CH_BOUNDSEL_BOUNDARYU_Msk        (0x0000FFFFU  << DSD_CH_BOUNDSEL_BOUNDARYU_Pos)\r
-\r
-/* DSD_CH_RESMx  =  Result Register x Main Filter*/\r
-#define   DSD_CH_RESM_RESULT_Pos       (0U)\r
-#define   DSD_CH_RESM_RESULT_Msk       (0x0000FFFFU  << DSD_CH_RESM_RESULT_Pos)\r
-\r
-/* DSD_CH_OFFMx  =  Offset Register x Main Filter*/\r
-#define   DSD_CH_OFFM_OFFSET_Pos       (0U)\r
-#define   DSD_CH_OFFM_OFFSET_Msk       (0x0000FFFFU  << DSD_CH_OFFM_OFFSET_Pos)\r
-\r
-/* DSD_CH_RESAx  =  Result Register x Auxiliary Filter*/\r
-#define   DSD_CH_RESA_RESULT_Pos       (0U)\r
-#define   DSD_CH_RESA_RESULT_Msk       (0x0000FFFFU  << DSD_CH_RESA_RESULT_Pos)\r
-\r
-/* DSD_CH_TSTMPx  =  Time-Stamp Register 0*/\r
-#define   DSD_CH_TSTMP_RESULT_Pos      (0U)\r
-#define   DSD_CH_TSTMP_RESULT_Msk      (0x0000FFFFU  << DSD_CH_TSTMP_RESULT_Pos)\r
-\r
-#define   DSD_CH_TSTMP_CFMDCNT_Pos     (16U)\r
-#define   DSD_CH_TSTMP_CFMDCNT_Msk     (0x000000FFU  << DSD_CH_TSTMP_CFMDCNT_Pos)\r
-\r
-#define   DSD_CH_TSTMP_NVALCNT_Pos     (24U)\r
-#define   DSD_CH_TSTMP_NVALCNT_Msk     (0x0000003FU  << DSD_CH_TSTMP_NVALCNT_Pos)\r
-\r
-/* DSD_CH_CGSYNCx  =  Carrier Generator Synchronization Register 0*/\r
-#define   DSD_CH_CGSYNC_SDCOUNT_Pos    (0U)\r
-#define   DSD_CH_CGSYNC_SDCOUNT_Msk    (0x000000FFU  << DSD_CH_CGSYNC_SDCOUNT_Pos)\r
-\r
-#define   DSD_CH_CGSYNC_SDCAP_Pos      (8U)\r
-#define   DSD_CH_CGSYNC_SDCAP_Msk      (0x000000FFU  << DSD_CH_CGSYNC_SDCAP_Pos)\r
-\r
-#define   DSD_CH_CGSYNC_SDPOS_Pos      (16U)\r
-#define   DSD_CH_CGSYNC_SDPOS_Msk      (0x000000FFU  << DSD_CH_CGSYNC_SDPOS_Pos)\r
-\r
-#define   DSD_CH_CGSYNC_SDNEG_Pos      (24U)\r
-#define   DSD_CH_CGSYNC_SDNEG_Msk      (0x000000FFU  << DSD_CH_CGSYNC_SDNEG_Pos)\r
-\r
-/* DSD_CH_RECTCFGx  =  Rectification Configuration Register 0*/\r
-#define   DSD_CH_RECTCFG_RFEN_Pos      (0U)\r
-#define   DSD_CH_RECTCFG_RFEN_Msk      (0x00000001U  << DSD_CH_RECTCFG_RFEN_Pos)\r
-\r
-#define   DSD_CH_RECTCFG_SSRC_Pos      (4U)\r
-#define   DSD_CH_RECTCFG_SSRC_Msk      (0x00000003U  << DSD_CH_RECTCFG_SSRC_Pos)\r
-\r
-#define   DSD_CH_RECTCFG_SDVAL_Pos     (15U)\r
-#define   DSD_CH_RECTCFG_SDVAL_Msk     (0x00000001U  << DSD_CH_RECTCFG_SDVAL_Pos)\r
-\r
-#define   DSD_CH_RECTCFG_SGNCS_Pos     (30U)\r
-#define   DSD_CH_RECTCFG_SGNCS_Msk     (0x00000001U  << DSD_CH_RECTCFG_SGNCS_Pos)\r
-\r
-#define   DSD_CH_RECTCFG_SGND_Pos      (31U)\r
-#define   DSD_CH_RECTCFG_SGND_Msk      (0x00000001U  << DSD_CH_RECTCFG_SGND_Pos)\r
-\r
-\r
-\r
-// --------------------------------------  DWT_DWT_CTRL  ------------------------------------------\r
-#define DWT_DWT_CTRL_CYCCNTENA_Pos                            0                                                         /*!< DWT DWT_CTRL: CYCCNTENA Position    */\r
-#define DWT_DWT_CTRL_CYCCNTENA_Msk                            (0x01UL << DWT_DWT_CTRL_CYCCNTENA_Pos)                    /*!< DWT DWT_CTRL: CYCCNTENA Mask        */\r
-#define DWT_DWT_CTRL_POSTPRESET_Pos                           1                                                         /*!< DWT DWT_CTRL: POSTPRESET Position   */\r
-#define DWT_DWT_CTRL_POSTPRESET_Msk                           (0x0fUL << DWT_DWT_CTRL_POSTPRESET_Pos)                   /*!< DWT DWT_CTRL: POSTPRESET Mask       */\r
-#define DWT_DWT_CTRL_POSTINIT_Pos                             5                                                         /*!< DWT DWT_CTRL: POSTINIT Position     */\r
-#define DWT_DWT_CTRL_POSTINIT_Msk                             (0x0fUL << DWT_DWT_CTRL_POSTINIT_Pos)                     /*!< DWT DWT_CTRL: POSTINIT Mask         */\r
-#define DWT_DWT_CTRL_CYCTAP_Pos                               9                                                         /*!< DWT DWT_CTRL: CYCTAP Position       */\r
-#define DWT_DWT_CTRL_CYCTAP_Msk                               (0x01UL << DWT_DWT_CTRL_CYCTAP_Pos)                       /*!< DWT DWT_CTRL: CYCTAP Mask           */\r
-#define DWT_DWT_CTRL_SYNCTAP_Pos                              10                                                        /*!< DWT DWT_CTRL: SYNCTAP Position      */\r
-#define DWT_DWT_CTRL_SYNCTAP_Msk                              (0x03UL << DWT_DWT_CTRL_SYNCTAP_Pos)                      /*!< DWT DWT_CTRL: SYNCTAP Mask          */\r
-#define DWT_DWT_CTRL_PCSAMPLEENA_Pos                          12                                                        /*!< DWT DWT_CTRL: PCSAMPLEENA Position  */\r
-#define DWT_DWT_CTRL_PCSAMPLEENA_Msk                          (0x01UL << DWT_DWT_CTRL_PCSAMPLEENA_Pos)                  /*!< DWT DWT_CTRL: PCSAMPLEENA Mask      */\r
-#define DWT_DWT_CTRL_Reserved_Pos                             13                                                        /*!< DWT DWT_CTRL: Reserved Position     */\r
-#define DWT_DWT_CTRL_Reserved_Msk                             (0x07UL << DWT_DWT_CTRL_Reserved_Pos)                     /*!< DWT DWT_CTRL: Reserved Mask         */\r
-#define DWT_DWT_CTRL_EXCTRCENA_Pos                            16                                                        /*!< DWT DWT_CTRL: EXCTRCENA Position    */\r
-#define DWT_DWT_CTRL_EXCTRCENA_Msk                            (0x01UL << DWT_DWT_CTRL_EXCTRCENA_Pos)                    /*!< DWT DWT_CTRL: EXCTRCENA Mask        */\r
-#define DWT_DWT_CTRL_CPIEVTENA_Pos                            17                                                        /*!< DWT DWT_CTRL: CPIEVTENA Position    */\r
-#define DWT_DWT_CTRL_CPIEVTENA_Msk                            (0x01UL << DWT_DWT_CTRL_CPIEVTENA_Pos)                    /*!< DWT DWT_CTRL: CPIEVTENA Mask        */\r
-#define DWT_DWT_CTRL_EXCEVTENA_Pos                            18                                                        /*!< DWT DWT_CTRL: EXCEVTENA Position    */\r
-#define DWT_DWT_CTRL_EXCEVTENA_Msk                            (0x01UL << DWT_DWT_CTRL_EXCEVTENA_Pos)                    /*!< DWT DWT_CTRL: EXCEVTENA Mask        */\r
-#define DWT_DWT_CTRL_SLEEPEVTENA_Pos                          19                                                        /*!< DWT DWT_CTRL: SLEEPEVTENA Position  */\r
-#define DWT_DWT_CTRL_SLEEPEVTENA_Msk                          (0x01UL << DWT_DWT_CTRL_SLEEPEVTENA_Pos)                  /*!< DWT DWT_CTRL: SLEEPEVTENA Mask      */\r
-#define DWT_DWT_CTRL_LSUEVTENA_Pos                            20                                                        /*!< DWT DWT_CTRL: LSUEVTENA Position    */\r
-#define DWT_DWT_CTRL_LSUEVTENA_Msk                            (0x01UL << DWT_DWT_CTRL_LSUEVTENA_Pos)                    /*!< DWT DWT_CTRL: LSUEVTENA Mask        */\r
-#define DWT_DWT_CTRL_FOLDEVTENA_Pos                           21                                                        /*!< DWT DWT_CTRL: FOLDEVTENA Position   */\r
-#define DWT_DWT_CTRL_FOLDEVTENA_Msk                           (0x01UL << DWT_DWT_CTRL_FOLDEVTENA_Pos)                   /*!< DWT DWT_CTRL: FOLDEVTENA Mask       */\r
-#define DWT_DWT_CTRL_CYCEVTENA_Pos                            22                                                        /*!< DWT DWT_CTRL: CYCEVTENA Position    */\r
-#define DWT_DWT_CTRL_CYCEVTENA_Msk                            (0x01UL << DWT_DWT_CTRL_CYCEVTENA_Pos)                    /*!< DWT DWT_CTRL: CYCEVTENA Mask        */\r
-#define DWT_DWT_CTRL_Reserved1_Pos                            23                                                        /*!< DWT DWT_CTRL: Reserved1 Position    */\r
-#define DWT_DWT_CTRL_Reserved1_Msk                            (0x01UL << DWT_DWT_CTRL_Reserved1_Pos)                    /*!< DWT DWT_CTRL: Reserved1 Mask        */\r
-#define DWT_DWT_CTRL_NOPRFCNT_Pos                             24                                                        /*!< DWT DWT_CTRL: NOPRFCNT Position     */\r
-#define DWT_DWT_CTRL_NOPRFCNT_Msk                             (0x01UL << DWT_DWT_CTRL_NOPRFCNT_Pos)                     /*!< DWT DWT_CTRL: NOPRFCNT Mask         */\r
-#define DWT_DWT_CTRL_NOCYCCNT_Pos                             25                                                        /*!< DWT DWT_CTRL: NOCYCCNT Position     */\r
-#define DWT_DWT_CTRL_NOCYCCNT_Msk                             (0x01UL << DWT_DWT_CTRL_NOCYCCNT_Pos)                     /*!< DWT DWT_CTRL: NOCYCCNT Mask         */\r
-#define DWT_DWT_CTRL_NOEXTTRIG_Pos                            26                                                        /*!< DWT DWT_CTRL: NOEXTTRIG Position    */\r
-#define DWT_DWT_CTRL_NOEXTTRIG_Msk                            (0x01UL << DWT_DWT_CTRL_NOEXTTRIG_Pos)                    /*!< DWT DWT_CTRL: NOEXTTRIG Mask        */\r
-#define DWT_DWT_CTRL_NOTRCPKT_Pos                             27                                                        /*!< DWT DWT_CTRL: NOTRCPKT Position     */\r
-#define DWT_DWT_CTRL_NOTRCPKT_Msk                             (0x01UL << DWT_DWT_CTRL_NOTRCPKT_Pos)                     /*!< DWT DWT_CTRL: NOTRCPKT Mask         */\r
-#define DWT_DWT_CTRL_NUMCOMP_Pos                              28                                                        /*!< DWT DWT_CTRL: NUMCOMP Position      */\r
-#define DWT_DWT_CTRL_NUMCOMP_Msk                              (0x0fUL << DWT_DWT_CTRL_NUMCOMP_Pos)                      /*!< DWT DWT_CTRL: NUMCOMP Mask          */\r
-\r
-// -------------------------------------  DWT_DWT_CYCCNT  -----------------------------------------\r
-#define DWT_DWT_CYCCNT_CYCCNT_Pos                             0                                                         /*!< DWT DWT_CYCCNT: CYCCNT Position     */\r
-#define DWT_DWT_CYCCNT_CYCCNT_Msk                             (0xffffffffUL << DWT_DWT_CYCCNT_CYCCNT_Pos)               /*!< DWT DWT_CYCCNT: CYCCNT Mask         */\r
-\r
-// -------------------------------------  DWT_DWT_CPICNT  -----------------------------------------\r
-#define DWT_DWT_CPICNT_CPICNT_Pos                             0                                                         /*!< DWT DWT_CPICNT: CPICNT Position     */\r
-#define DWT_DWT_CPICNT_CPICNT_Msk                             (0x000000ffUL << DWT_DWT_CPICNT_CPICNT_Pos)               /*!< DWT DWT_CPICNT: CPICNT Mask         */\r
-#define DWT_DWT_CPICNT_Reserved_Pos                           8                                                         /*!< DWT DWT_CPICNT: Reserved Position   */\r
-#define DWT_DWT_CPICNT_Reserved_Msk                           (0x00ffffffUL << DWT_DWT_CPICNT_Reserved_Pos)             /*!< DWT DWT_CPICNT: Reserved Mask       */\r
-\r
-// -------------------------------------  DWT_DWT_EXCCNT  -----------------------------------------\r
-#define DWT_DWT_EXCCNT_EXCCNT_Pos                             0                                                         /*!< DWT DWT_EXCCNT: EXCCNT Position     */\r
-#define DWT_DWT_EXCCNT_EXCCNT_Msk                             (0x000000ffUL << DWT_DWT_EXCCNT_EXCCNT_Pos)               /*!< DWT DWT_EXCCNT: EXCCNT Mask         */\r
-#define DWT_DWT_EXCCNT_Reserved_Pos                           8                                                         /*!< DWT DWT_EXCCNT: Reserved Position   */\r
-#define DWT_DWT_EXCCNT_Reserved_Msk                           (0x00ffffffUL << DWT_DWT_EXCCNT_Reserved_Pos)             /*!< DWT DWT_EXCCNT: Reserved Mask       */\r
-\r
-// ------------------------------------  DWT_DWT_SLEEPCNT  ----------------------------------------\r
-#define DWT_DWT_SLEEPCNT_SLEEPCNT_Pos                         0                                                         /*!< DWT DWT_SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_DWT_SLEEPCNT_SLEEPCNT_Msk                         (0x000000ffUL << DWT_DWT_SLEEPCNT_SLEEPCNT_Pos)           /*!< DWT DWT_SLEEPCNT: SLEEPCNT Mask     */\r
-#define DWT_DWT_SLEEPCNT_Reserved_Pos                         8                                                         /*!< DWT DWT_SLEEPCNT: Reserved Position */\r
-#define DWT_DWT_SLEEPCNT_Reserved_Msk                         (0x00ffffffUL << DWT_DWT_SLEEPCNT_Reserved_Pos)           /*!< DWT DWT_SLEEPCNT: Reserved Mask     */\r
-\r
-// -------------------------------------  DWT_DWT_LSUCNT  -----------------------------------------\r
-#define DWT_DWT_LSUCNT_LSUCNT_Pos                             0                                                         /*!< DWT DWT_LSUCNT: LSUCNT Position     */\r
-#define DWT_DWT_LSUCNT_LSUCNT_Msk                             (0x000000ffUL << DWT_DWT_LSUCNT_LSUCNT_Pos)               /*!< DWT DWT_LSUCNT: LSUCNT Mask         */\r
-#define DWT_DWT_LSUCNT_Reserved_Pos                           8                                                         /*!< DWT DWT_LSUCNT: Reserved Position   */\r
-#define DWT_DWT_LSUCNT_Reserved_Msk                           (0x00ffffffUL << DWT_DWT_LSUCNT_Reserved_Pos)             /*!< DWT DWT_LSUCNT: Reserved Mask       */\r
-\r
-// -------------------------------------  DWT_DWT_FOLDCNT  ----------------------------------------\r
-#define DWT_DWT_FOLDCNT_FOLDCNT_Pos                           0                                                         /*!< DWT DWT_FOLDCNT: FOLDCNT Position   */\r
-#define DWT_DWT_FOLDCNT_FOLDCNT_Msk                           (0x000000ffUL << DWT_DWT_FOLDCNT_FOLDCNT_Pos)             /*!< DWT DWT_FOLDCNT: FOLDCNT Mask       */\r
-#define DWT_DWT_FOLDCNT_Reserved_Pos                          8                                                         /*!< DWT DWT_FOLDCNT: Reserved Position  */\r
-#define DWT_DWT_FOLDCNT_Reserved_Msk                          (0x00ffffffUL << DWT_DWT_FOLDCNT_Reserved_Pos)            /*!< DWT DWT_FOLDCNT: Reserved Mask      */\r
-\r
-// --------------------------------------  DWT_DWT_PCSR  ------------------------------------------\r
-#define DWT_DWT_PCSR_EIASAMPLE_Pos                            0                                                         /*!< DWT DWT_PCSR: EIASAMPLE Position    */\r
-#define DWT_DWT_PCSR_EIASAMPLE_Msk                            (0xffffffffUL << DWT_DWT_PCSR_EIASAMPLE_Pos)              /*!< DWT DWT_PCSR: EIASAMPLE Mask        */\r
-\r
-// --------------------------------------  DWT_DWT_COMP0  -----------------------------------------\r
-#define DWT_DWT_COMP0_COMP_Pos                                0                                                         /*!< DWT DWT_COMP0: COMP Position        */\r
-#define DWT_DWT_COMP0_COMP_Msk                                (0xffffffffUL << DWT_DWT_COMP0_COMP_Pos)                  /*!< DWT DWT_COMP0: COMP Mask            */\r
-\r
-// --------------------------------------  DWT_DWT_MASK0  -----------------------------------------\r
-#define DWT_DWT_MASK0_MASK_Pos                                0                                                         /*!< DWT DWT_MASK0: MASK Position        */\r
-#define DWT_DWT_MASK0_MASK_Msk                                (0x1fUL << DWT_DWT_MASK0_MASK_Pos)                        /*!< DWT DWT_MASK0: MASK Mask            */\r
-#define DWT_DWT_MASK0_Reserved_Pos                            5                                                         /*!< DWT DWT_MASK0: Reserved Position    */\r
-#define DWT_DWT_MASK0_Reserved_Msk                            (0x07ffffffUL << DWT_DWT_MASK0_Reserved_Pos)              /*!< DWT DWT_MASK0: Reserved Mask        */\r
-\r
-// ------------------------------------  DWT_DWT_FUNCTION0  ---------------------------------------\r
-#define DWT_DWT_FUNCTION0_FUNCTION_Pos                        0                                                         /*!< DWT DWT_FUNCTION0: FUNCTION Position */\r
-#define DWT_DWT_FUNCTION0_FUNCTION_Msk                        (0x0fUL << DWT_DWT_FUNCTION0_FUNCTION_Pos)                /*!< DWT DWT_FUNCTION0: FUNCTION Mask    */\r
-#define DWT_DWT_FUNCTION0_Reserved_Pos                        4                                                         /*!< DWT DWT_FUNCTION0: Reserved Position */\r
-#define DWT_DWT_FUNCTION0_Reserved_Msk                        (0x01UL << DWT_DWT_FUNCTION0_Reserved_Pos)                /*!< DWT DWT_FUNCTION0: Reserved Mask    */\r
-#define DWT_DWT_FUNCTION0_EMITRANGE_Pos                       5                                                         /*!< DWT DWT_FUNCTION0: EMITRANGE Position */\r
-#define DWT_DWT_FUNCTION0_EMITRANGE_Msk                       (0x01UL << DWT_DWT_FUNCTION0_EMITRANGE_Pos)               /*!< DWT DWT_FUNCTION0: EMITRANGE Mask   */\r
-#define DWT_DWT_FUNCTION0_Reserved1_Pos                       6                                                         /*!< DWT DWT_FUNCTION0: Reserved1 Position */\r
-#define DWT_DWT_FUNCTION0_Reserved1_Msk                       (0x01UL << DWT_DWT_FUNCTION0_Reserved1_Pos)               /*!< DWT DWT_FUNCTION0: Reserved1 Mask   */\r
-#define DWT_DWT_FUNCTION0_CYCMATCH_Pos                        7                                                         /*!< DWT DWT_FUNCTION0: CYCMATCH Position */\r
-#define DWT_DWT_FUNCTION0_CYCMATCH_Msk                        (0x01UL << DWT_DWT_FUNCTION0_CYCMATCH_Pos)                /*!< DWT DWT_FUNCTION0: CYCMATCH Mask    */\r
-#define DWT_DWT_FUNCTION0_DATAVMATCH_Pos                      8                                                         /*!< DWT DWT_FUNCTION0: DATAVMATCH Position */\r
-#define DWT_DWT_FUNCTION0_DATAVMATCH_Msk                      (0x01UL << DWT_DWT_FUNCTION0_DATAVMATCH_Pos)              /*!< DWT DWT_FUNCTION0: DATAVMATCH Mask  */\r
-#define DWT_DWT_FUNCTION0_LNK1ENA_Pos                         9                                                         /*!< DWT DWT_FUNCTION0: LNK1ENA Position */\r
-#define DWT_DWT_FUNCTION0_LNK1ENA_Msk                         (0x01UL << DWT_DWT_FUNCTION0_LNK1ENA_Pos)                 /*!< DWT DWT_FUNCTION0: LNK1ENA Mask     */\r
-#define DWT_DWT_FUNCTION0_DATAVSIZE_Pos                       10                                                        /*!< DWT DWT_FUNCTION0: DATAVSIZE Position */\r
-#define DWT_DWT_FUNCTION0_DATAVSIZE_Msk                       (0x03UL << DWT_DWT_FUNCTION0_DATAVSIZE_Pos)               /*!< DWT DWT_FUNCTION0: DATAVSIZE Mask   */\r
-#define DWT_DWT_FUNCTION0_DATAVADDR0_Pos                      12                                                        /*!< DWT DWT_FUNCTION0: DATAVADDR0 Position */\r
-#define DWT_DWT_FUNCTION0_DATAVADDR0_Msk                      (0x0fUL << DWT_DWT_FUNCTION0_DATAVADDR0_Pos)              /*!< DWT DWT_FUNCTION0: DATAVADDR0 Mask  */\r
-#define DWT_DWT_FUNCTION0_DATAVADDR1_Pos                      16                                                        /*!< DWT DWT_FUNCTION0: DATAVADDR1 Position */\r
-#define DWT_DWT_FUNCTION0_DATAVADDR1_Msk                      (0x0fUL << DWT_DWT_FUNCTION0_DATAVADDR1_Pos)              /*!< DWT DWT_FUNCTION0: DATAVADDR1 Mask  */\r
-#define DWT_DWT_FUNCTION0_Reserved2_Pos                       20                                                        /*!< DWT DWT_FUNCTION0: Reserved2 Position */\r
-#define DWT_DWT_FUNCTION0_Reserved2_Msk                       (0x0fUL << DWT_DWT_FUNCTION0_Reserved2_Pos)               /*!< DWT DWT_FUNCTION0: Reserved2 Mask   */\r
-#define DWT_DWT_FUNCTION0_MATCHED_Pos                         24                                                        /*!< DWT DWT_FUNCTION0: MATCHED Position */\r
-#define DWT_DWT_FUNCTION0_MATCHED_Msk                         (0x01UL << DWT_DWT_FUNCTION0_MATCHED_Pos)                 /*!< DWT DWT_FUNCTION0: MATCHED Mask     */\r
-#define DWT_DWT_FUNCTION0_Reserved3_Pos                       25                                                        /*!< DWT DWT_FUNCTION0: Reserved3 Position */\r
-#define DWT_DWT_FUNCTION0_Reserved3_Msk                       (0x7fUL << DWT_DWT_FUNCTION0_Reserved3_Pos)               /*!< DWT DWT_FUNCTION0: Reserved3 Mask   */\r
-\r
-// --------------------------------------  DWT_DWT_COMP1  -----------------------------------------\r
-#define DWT_DWT_COMP1_COMP_Pos                                0                                                         /*!< DWT DWT_COMP1: COMP Position        */\r
-#define DWT_DWT_COMP1_COMP_Msk                                (0xffffffffUL << DWT_DWT_COMP1_COMP_Pos)                  /*!< DWT DWT_COMP1: COMP Mask            */\r
-\r
-// --------------------------------------  DWT_DWT_MASK1  -----------------------------------------\r
-#define DWT_DWT_MASK1_MASK_Pos                                0                                                         /*!< DWT DWT_MASK1: MASK Position        */\r
-#define DWT_DWT_MASK1_MASK_Msk                                (0x1fUL << DWT_DWT_MASK1_MASK_Pos)                        /*!< DWT DWT_MASK1: MASK Mask            */\r
-#define DWT_DWT_MASK1_Reserved_Pos                            5                                                         /*!< DWT DWT_MASK1: Reserved Position    */\r
-#define DWT_DWT_MASK1_Reserved_Msk                            (0x07ffffffUL << DWT_DWT_MASK1_Reserved_Pos)              /*!< DWT DWT_MASK1: Reserved Mask        */\r
-\r
-// ------------------------------------  DWT_DWT_FUNCTION1  ---------------------------------------\r
-#define DWT_DWT_FUNCTION1_FUNCTION_Pos                        0                                                         /*!< DWT DWT_FUNCTION1: FUNCTION Position */\r
-#define DWT_DWT_FUNCTION1_FUNCTION_Msk                        (0x0fUL << DWT_DWT_FUNCTION1_FUNCTION_Pos)                /*!< DWT DWT_FUNCTION1: FUNCTION Mask    */\r
-#define DWT_DWT_FUNCTION1_Reserved_Pos                        4                                                         /*!< DWT DWT_FUNCTION1: Reserved Position */\r
-#define DWT_DWT_FUNCTION1_Reserved_Msk                        (0x01UL << DWT_DWT_FUNCTION1_Reserved_Pos)                /*!< DWT DWT_FUNCTION1: Reserved Mask    */\r
-#define DWT_DWT_FUNCTION1_EMITRANGE_Pos                       5                                                         /*!< DWT DWT_FUNCTION1: EMITRANGE Position */\r
-#define DWT_DWT_FUNCTION1_EMITRANGE_Msk                       (0x01UL << DWT_DWT_FUNCTION1_EMITRANGE_Pos)               /*!< DWT DWT_FUNCTION1: EMITRANGE Mask   */\r
-#define DWT_DWT_FUNCTION1_Reserved1_Pos                       6                                                         /*!< DWT DWT_FUNCTION1: Reserved1 Position */\r
-#define DWT_DWT_FUNCTION1_Reserved1_Msk                       (0x03UL << DWT_DWT_FUNCTION1_Reserved1_Pos)               /*!< DWT DWT_FUNCTION1: Reserved1 Mask   */\r
-#define DWT_DWT_FUNCTION1_DATAVMATCH_Pos                      8                                                         /*!< DWT DWT_FUNCTION1: DATAVMATCH Position */\r
-#define DWT_DWT_FUNCTION1_DATAVMATCH_Msk                      (0x01UL << DWT_DWT_FUNCTION1_DATAVMATCH_Pos)              /*!< DWT DWT_FUNCTION1: DATAVMATCH Mask  */\r
-#define DWT_DWT_FUNCTION1_LNK1ENA_Pos                         9                                                         /*!< DWT DWT_FUNCTION1: LNK1ENA Position */\r
-#define DWT_DWT_FUNCTION1_LNK1ENA_Msk                         (0x01UL << DWT_DWT_FUNCTION1_LNK1ENA_Pos)                 /*!< DWT DWT_FUNCTION1: LNK1ENA Mask     */\r
-#define DWT_DWT_FUNCTION1_DATAVSIZE_Pos                       10                                                        /*!< DWT DWT_FUNCTION1: DATAVSIZE Position */\r
-#define DWT_DWT_FUNCTION1_DATAVSIZE_Msk                       (0x03UL << DWT_DWT_FUNCTION1_DATAVSIZE_Pos)               /*!< DWT DWT_FUNCTION1: DATAVSIZE Mask   */\r
-#define DWT_DWT_FUNCTION1_DATAVADDR0_Pos                      12                                                        /*!< DWT DWT_FUNCTION1: DATAVADDR0 Position */\r
-#define DWT_DWT_FUNCTION1_DATAVADDR0_Msk                      (0x0fUL << DWT_DWT_FUNCTION1_DATAVADDR0_Pos)              /*!< DWT DWT_FUNCTION1: DATAVADDR0 Mask  */\r
-#define DWT_DWT_FUNCTION1_DATAVADDR1_Pos                      16                                                        /*!< DWT DWT_FUNCTION1: DATAVADDR1 Position */\r
-#define DWT_DWT_FUNCTION1_DATAVADDR1_Msk                      (0x0fUL << DWT_DWT_FUNCTION1_DATAVADDR1_Pos)              /*!< DWT DWT_FUNCTION1: DATAVADDR1 Mask  */\r
-#define DWT_DWT_FUNCTION1_Reserved2_Pos                       20                                                        /*!< DWT DWT_FUNCTION1: Reserved2 Position */\r
-#define DWT_DWT_FUNCTION1_Reserved2_Msk                       (0x0fUL << DWT_DWT_FUNCTION1_Reserved2_Pos)               /*!< DWT DWT_FUNCTION1: Reserved2 Mask   */\r
-#define DWT_DWT_FUNCTION1_MATCHED_Pos                         24                                                        /*!< DWT DWT_FUNCTION1: MATCHED Position */\r
-#define DWT_DWT_FUNCTION1_MATCHED_Msk                         (0x01UL << DWT_DWT_FUNCTION1_MATCHED_Pos)                 /*!< DWT DWT_FUNCTION1: MATCHED Mask     */\r
-#define DWT_DWT_FUNCTION1_Reserved3_Pos                       25                                                        /*!< DWT DWT_FUNCTION1: Reserved3 Position */\r
-#define DWT_DWT_FUNCTION1_Reserved3_Msk                       (0x7fUL << DWT_DWT_FUNCTION1_Reserved3_Pos)               /*!< DWT DWT_FUNCTION1: Reserved3 Mask   */\r
-\r
-// --------------------------------------  DWT_DWT_COMP2  -----------------------------------------\r
-#define DWT_DWT_COMP2_COMP_Pos                                0                                                         /*!< DWT DWT_COMP2: COMP Position        */\r
-#define DWT_DWT_COMP2_COMP_Msk                                (0xffffffffUL << DWT_DWT_COMP2_COMP_Pos)                  /*!< DWT DWT_COMP2: COMP Mask            */\r
-\r
-// --------------------------------------  DWT_DWT_MASK2  -----------------------------------------\r
-#define DWT_DWT_MASK2_MASK_Pos                                0                                                         /*!< DWT DWT_MASK2: MASK Position        */\r
-#define DWT_DWT_MASK2_MASK_Msk                                (0x1fUL << DWT_DWT_MASK2_MASK_Pos)                        /*!< DWT DWT_MASK2: MASK Mask            */\r
-#define DWT_DWT_MASK2_Reserved_Pos                            5                                                         /*!< DWT DWT_MASK2: Reserved Position    */\r
-#define DWT_DWT_MASK2_Reserved_Msk                            (0x07ffffffUL << DWT_DWT_MASK2_Reserved_Pos)              /*!< DWT DWT_MASK2: Reserved Mask        */\r
-\r
-// ------------------------------------  DWT_DWT_FUNCTION2  ---------------------------------------\r
-#define DWT_DWT_FUNCTION2_FUNCTION_Pos                        0                                                         /*!< DWT DWT_FUNCTION2: FUNCTION Position */\r
-#define DWT_DWT_FUNCTION2_FUNCTION_Msk                        (0x0fUL << DWT_DWT_FUNCTION2_FUNCTION_Pos)                /*!< DWT DWT_FUNCTION2: FUNCTION Mask    */\r
-#define DWT_DWT_FUNCTION2_Reserved_Pos                        4                                                         /*!< DWT DWT_FUNCTION2: Reserved Position */\r
-#define DWT_DWT_FUNCTION2_Reserved_Msk                        (0x01UL << DWT_DWT_FUNCTION2_Reserved_Pos)                /*!< DWT DWT_FUNCTION2: Reserved Mask    */\r
-#define DWT_DWT_FUNCTION2_EMITRANGE_Pos                       5                                                         /*!< DWT DWT_FUNCTION2: EMITRANGE Position */\r
-#define DWT_DWT_FUNCTION2_EMITRANGE_Msk                       (0x01UL << DWT_DWT_FUNCTION2_EMITRANGE_Pos)               /*!< DWT DWT_FUNCTION2: EMITRANGE Mask   */\r
-#define DWT_DWT_FUNCTION2_Reserved1_Pos                       6                                                         /*!< DWT DWT_FUNCTION2: Reserved1 Position */\r
-#define DWT_DWT_FUNCTION2_Reserved1_Msk                       (0x03UL << DWT_DWT_FUNCTION2_Reserved1_Pos)               /*!< DWT DWT_FUNCTION2: Reserved1 Mask   */\r
-#define DWT_DWT_FUNCTION2_DATAVMATCH_Pos                      8                                                         /*!< DWT DWT_FUNCTION2: DATAVMATCH Position */\r
-#define DWT_DWT_FUNCTION2_DATAVMATCH_Msk                      (0x01UL << DWT_DWT_FUNCTION2_DATAVMATCH_Pos)              /*!< DWT DWT_FUNCTION2: DATAVMATCH Mask  */\r
-#define DWT_DWT_FUNCTION2_LNK1ENA_Pos                         9                                                         /*!< DWT DWT_FUNCTION2: LNK1ENA Position */\r
-#define DWT_DWT_FUNCTION2_LNK1ENA_Msk                         (0x01UL << DWT_DWT_FUNCTION2_LNK1ENA_Pos)                 /*!< DWT DWT_FUNCTION2: LNK1ENA Mask     */\r
-#define DWT_DWT_FUNCTION2_DATAVSIZE_Pos                       10                                                        /*!< DWT DWT_FUNCTION2: DATAVSIZE Position */\r
-#define DWT_DWT_FUNCTION2_DATAVSIZE_Msk                       (0x03UL << DWT_DWT_FUNCTION2_DATAVSIZE_Pos)               /*!< DWT DWT_FUNCTION2: DATAVSIZE Mask   */\r
-#define DWT_DWT_FUNCTION2_DATAVADDR0_Pos                      12                                                        /*!< DWT DWT_FUNCTION2: DATAVADDR0 Position */\r
-#define DWT_DWT_FUNCTION2_DATAVADDR0_Msk                      (0x0fUL << DWT_DWT_FUNCTION2_DATAVADDR0_Pos)              /*!< DWT DWT_FUNCTION2: DATAVADDR0 Mask  */\r
-#define DWT_DWT_FUNCTION2_DATAVADDR1_Pos                      16                                                        /*!< DWT DWT_FUNCTION2: DATAVADDR1 Position */\r
-#define DWT_DWT_FUNCTION2_DATAVADDR1_Msk                      (0x0fUL << DWT_DWT_FUNCTION2_DATAVADDR1_Pos)              /*!< DWT DWT_FUNCTION2: DATAVADDR1 Mask  */\r
-#define DWT_DWT_FUNCTION2_Reserved2_Pos                       20                                                        /*!< DWT DWT_FUNCTION2: Reserved2 Position */\r
-#define DWT_DWT_FUNCTION2_Reserved2_Msk                       (0x0fUL << DWT_DWT_FUNCTION2_Reserved2_Pos)               /*!< DWT DWT_FUNCTION2: Reserved2 Mask   */\r
-#define DWT_DWT_FUNCTION2_MATCHED_Pos                         24                                                        /*!< DWT DWT_FUNCTION2: MATCHED Position */\r
-#define DWT_DWT_FUNCTION2_MATCHED_Msk                         (0x01UL << DWT_DWT_FUNCTION2_MATCHED_Pos)                 /*!< DWT DWT_FUNCTION2: MATCHED Mask     */\r
-#define DWT_DWT_FUNCTION2_Reserved3_Pos                       25                                                        /*!< DWT DWT_FUNCTION2: Reserved3 Position */\r
-#define DWT_DWT_FUNCTION2_Reserved3_Msk                       (0x7fUL << DWT_DWT_FUNCTION2_Reserved3_Pos)               /*!< DWT DWT_FUNCTION2: Reserved3 Mask   */\r
-\r
-// --------------------------------------  DWT_DWT_COMP3  -----------------------------------------\r
-#define DWT_DWT_COMP3_COMP_Pos                                0                                                         /*!< DWT DWT_COMP3: COMP Position        */\r
-#define DWT_DWT_COMP3_COMP_Msk                                (0xffffffffUL << DWT_DWT_COMP3_COMP_Pos)                  /*!< DWT DWT_COMP3: COMP Mask            */\r
-\r
-// --------------------------------------  DWT_DWT_MASK3  -----------------------------------------\r
-#define DWT_DWT_MASK3_MASK_Pos                                0                                                         /*!< DWT DWT_MASK3: MASK Position        */\r
-#define DWT_DWT_MASK3_MASK_Msk                                (0x1fUL << DWT_DWT_MASK3_MASK_Pos)                        /*!< DWT DWT_MASK3: MASK Mask            */\r
-#define DWT_DWT_MASK3_Reserved_Pos                            5                                                         /*!< DWT DWT_MASK3: Reserved Position    */\r
-#define DWT_DWT_MASK3_Reserved_Msk                            (0x07ffffffUL << DWT_DWT_MASK3_Reserved_Pos)              /*!< DWT DWT_MASK3: Reserved Mask        */\r
-\r
-// ------------------------------------  DWT_DWT_FUNCTION3  ---------------------------------------\r
-#define DWT_DWT_FUNCTION3_FUNCTION_Pos                        0                                                         /*!< DWT DWT_FUNCTION3: FUNCTION Position */\r
-#define DWT_DWT_FUNCTION3_FUNCTION_Msk                        (0x0fUL << DWT_DWT_FUNCTION3_FUNCTION_Pos)                /*!< DWT DWT_FUNCTION3: FUNCTION Mask    */\r
-#define DWT_DWT_FUNCTION3_Reserved_Pos                        4                                                         /*!< DWT DWT_FUNCTION3: Reserved Position */\r
-#define DWT_DWT_FUNCTION3_Reserved_Msk                        (0x01UL << DWT_DWT_FUNCTION3_Reserved_Pos)                /*!< DWT DWT_FUNCTION3: Reserved Mask    */\r
-#define DWT_DWT_FUNCTION3_EMITRANGE_Pos                       5                                                         /*!< DWT DWT_FUNCTION3: EMITRANGE Position */\r
-#define DWT_DWT_FUNCTION3_EMITRANGE_Msk                       (0x01UL << DWT_DWT_FUNCTION3_EMITRANGE_Pos)               /*!< DWT DWT_FUNCTION3: EMITRANGE Mask   */\r
-#define DWT_DWT_FUNCTION3_Reserved1_Pos                       6                                                         /*!< DWT DWT_FUNCTION3: Reserved1 Position */\r
-#define DWT_DWT_FUNCTION3_Reserved1_Msk                       (0x03UL << DWT_DWT_FUNCTION3_Reserved1_Pos)               /*!< DWT DWT_FUNCTION3: Reserved1 Mask   */\r
-#define DWT_DWT_FUNCTION3_DATAVMATCH_Pos                      8                                                         /*!< DWT DWT_FUNCTION3: DATAVMATCH Position */\r
-#define DWT_DWT_FUNCTION3_DATAVMATCH_Msk                      (0x01UL << DWT_DWT_FUNCTION3_DATAVMATCH_Pos)              /*!< DWT DWT_FUNCTION3: DATAVMATCH Mask  */\r
-#define DWT_DWT_FUNCTION3_LNK1ENA_Pos                         9                                                         /*!< DWT DWT_FUNCTION3: LNK1ENA Position */\r
-#define DWT_DWT_FUNCTION3_LNK1ENA_Msk                         (0x01UL << DWT_DWT_FUNCTION3_LNK1ENA_Pos)                 /*!< DWT DWT_FUNCTION3: LNK1ENA Mask     */\r
-#define DWT_DWT_FUNCTION3_DATAVSIZE_Pos                       10                                                        /*!< DWT DWT_FUNCTION3: DATAVSIZE Position */\r
-#define DWT_DWT_FUNCTION3_DATAVSIZE_Msk                       (0x03UL << DWT_DWT_FUNCTION3_DATAVSIZE_Pos)               /*!< DWT DWT_FUNCTION3: DATAVSIZE Mask   */\r
-#define DWT_DWT_FUNCTION3_DATAVADDR0_Pos                      12                                                        /*!< DWT DWT_FUNCTION3: DATAVADDR0 Position */\r
-#define DWT_DWT_FUNCTION3_DATAVADDR0_Msk                      (0x0fUL << DWT_DWT_FUNCTION3_DATAVADDR0_Pos)              /*!< DWT DWT_FUNCTION3: DATAVADDR0 Mask  */\r
-#define DWT_DWT_FUNCTION3_DATAVADDR1_Pos                      16                                                        /*!< DWT DWT_FUNCTION3: DATAVADDR1 Position */\r
-#define DWT_DWT_FUNCTION3_DATAVADDR1_Msk                      (0x0fUL << DWT_DWT_FUNCTION3_DATAVADDR1_Pos)              /*!< DWT DWT_FUNCTION3: DATAVADDR1 Mask  */\r
-#define DWT_DWT_FUNCTION3_Reserved2_Pos                       20                                                        /*!< DWT DWT_FUNCTION3: Reserved2 Position */\r
-#define DWT_DWT_FUNCTION3_Reserved2_Msk                       (0x0fUL << DWT_DWT_FUNCTION3_Reserved2_Pos)               /*!< DWT DWT_FUNCTION3: Reserved2 Mask   */\r
-#define DWT_DWT_FUNCTION3_MATCHED_Pos                         24                                                        /*!< DWT DWT_FUNCTION3: MATCHED Position */\r
-#define DWT_DWT_FUNCTION3_MATCHED_Msk                         (0x01UL << DWT_DWT_FUNCTION3_MATCHED_Pos)                 /*!< DWT DWT_FUNCTION3: MATCHED Mask     */\r
-#define DWT_DWT_FUNCTION3_Reserved3_Pos                       25                                                        /*!< DWT DWT_FUNCTION3: Reserved3 Position */\r
-#define DWT_DWT_FUNCTION3_Reserved3_Msk                       (0x7fUL << DWT_DWT_FUNCTION3_Reserved3_Pos)               /*!< DWT DWT_FUNCTION3: Reserved3 Mask   */\r
-\r
-// ---------------------------------------  DWT_DWTPID4  ------------------------------------------\r
-#define DWT_DWTPID4_PID4_Pos                                  0                                                         /*!< DWT DWTPID4: PID4 Position          */\r
-#define DWT_DWTPID4_PID4_Msk                                  (0xffffffffUL << DWT_DWTPID4_PID4_Pos)                    /*!< DWT DWTPID4: PID4 Mask              */\r
-\r
-// ---------------------------------------  DWT_DWTPID5  ------------------------------------------\r
-#define DWT_DWTPID5_PID5_Pos                                  0                                                         /*!< DWT DWTPID5: PID5 Position          */\r
-#define DWT_DWTPID5_PID5_Msk                                  (0xffffffffUL << DWT_DWTPID5_PID5_Pos)                    /*!< DWT DWTPID5: PID5 Mask              */\r
-\r
-// ---------------------------------------  DWT_DWTPID6  ------------------------------------------\r
-#define DWT_DWTPID6_PID6_Pos                                  0                                                         /*!< DWT DWTPID6: PID6 Position          */\r
-#define DWT_DWTPID6_PID6_Msk                                  (0xffffffffUL << DWT_DWTPID6_PID6_Pos)                    /*!< DWT DWTPID6: PID6 Mask              */\r
-\r
-// ---------------------------------------  DWT_DWTPID7  ------------------------------------------\r
-#define DWT_DWTPID7_PID7_Pos                                  0                                                         /*!< DWT DWTPID7: PID7 Position          */\r
-#define DWT_DWTPID7_PID7_Msk                                  (0xffffffffUL << DWT_DWTPID7_PID7_Pos)                    /*!< DWT DWTPID7: PID7 Mask              */\r
-\r
-// ---------------------------------------  DWT_DWTPID0  ------------------------------------------\r
-#define DWT_DWTPID0_PID0_Pos                                  0                                                         /*!< DWT DWTPID0: PID0 Position          */\r
-#define DWT_DWTPID0_PID0_Msk                                  (0xffffffffUL << DWT_DWTPID0_PID0_Pos)                    /*!< DWT DWTPID0: PID0 Mask              */\r
-\r
-// ---------------------------------------  DWT_DWTPID1  ------------------------------------------\r
-#define DWT_DWTPID1_PID1_Pos                                  0                                                         /*!< DWT DWTPID1: PID1 Position          */\r
-#define DWT_DWTPID1_PID1_Msk                                  (0xffffffffUL << DWT_DWTPID1_PID1_Pos)                    /*!< DWT DWTPID1: PID1 Mask              */\r
-\r
-// ---------------------------------------  DWT_DWTPID2  ------------------------------------------\r
-#define DWT_DWTPID2_PID2_Pos                                  0                                                         /*!< DWT DWTPID2: PID2 Position          */\r
-#define DWT_DWTPID2_PID2_Msk                                  (0xffffffffUL << DWT_DWTPID2_PID2_Pos)                    /*!< DWT DWTPID2: PID2 Mask              */\r
-\r
-// ---------------------------------------  DWT_DWTPID3  ------------------------------------------\r
-#define DWT_DWTPID3_PID3_Pos                                  0                                                         /*!< DWT DWTPID3: PID3 Position          */\r
-#define DWT_DWTPID3_PID3_Msk                                  (0xffffffffUL << DWT_DWTPID3_PID3_Pos)                    /*!< DWT DWTPID3: PID3 Mask              */\r
-\r
-// ---------------------------------------  DWT_DWTCID0  ------------------------------------------\r
-#define DWT_DWTCID0_CID0_Pos                                  0                                                         /*!< DWT DWTCID0: CID0 Position          */\r
-#define DWT_DWTCID0_CID0_Msk                                  (0xffffffffUL << DWT_DWTCID0_CID0_Pos)                    /*!< DWT DWTCID0: CID0 Mask              */\r
-\r
-// ---------------------------------------  DWT_DWTCID1  ------------------------------------------\r
-#define DWT_DWTCID1_CID1_Pos                                  0                                                         /*!< DWT DWTCID1: CID1 Position          */\r
-#define DWT_DWTCID1_CID1_Msk                                  (0xffffffffUL << DWT_DWTCID1_CID1_Pos)                    /*!< DWT DWTCID1: CID1 Mask              */\r
-\r
-// ---------------------------------------  DWT_DWTCID2  ------------------------------------------\r
-#define DWT_DWTCID2_CID2_Pos                                  0                                                         /*!< DWT DWTCID2: CID2 Position          */\r
-#define DWT_DWTCID2_CID2_Msk                                  (0xffffffffUL << DWT_DWTCID2_CID2_Pos)                    /*!< DWT DWTCID2: CID2 Mask              */\r
-\r
-// ---------------------------------------  DWT_DWTCID3  ------------------------------------------\r
-#define DWT_DWTCID3_CID3_Pos                                  0                                                         /*!< DWT DWTCID3: CID3 Position          */\r
-#define DWT_DWTCID3_CID3_Msk                                  (0xffffffffUL << DWT_DWTCID3_CID3_Pos)                    /*!< DWT DWTCID3: CID3 Mask              */\r
-\r
-\r
-\r
-/***   EBU Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* EBU_CLC  =  EBU Clock Control Register*/\r
-#define   EBU_CLC_DISR_Pos     (0U)\r
-#define   EBU_CLC_DISR_Msk     (0x00000001U  << EBU_CLC_DISR_Pos)\r
-\r
-#define   EBU_CLC_DISS_Pos     (1U)\r
-#define   EBU_CLC_DISS_Msk     (0x00000001U  << EBU_CLC_DISS_Pos)\r
-\r
-#define   EBU_CLC_SYNC_Pos     (16U)\r
-#define   EBU_CLC_SYNC_Msk     (0x00000001U  << EBU_CLC_SYNC_Pos)\r
-\r
-#define   EBU_CLC_DIV2_Pos     (17U)\r
-#define   EBU_CLC_DIV2_Msk     (0x00000001U  << EBU_CLC_DIV2_Pos)\r
-\r
-#define   EBU_CLC_EBUDIV_Pos   (18U)\r
-#define   EBU_CLC_EBUDIV_Msk   (0x00000003U  << EBU_CLC_EBUDIV_Pos)\r
-\r
-#define   EBU_CLC_SYNCACK_Pos          (20U)\r
-#define   EBU_CLC_SYNCACK_Msk          (0x00000001U  << EBU_CLC_SYNCACK_Pos)\r
-\r
-#define   EBU_CLC_DIV2ACK_Pos          (21U)\r
-#define   EBU_CLC_DIV2ACK_Msk          (0x00000001U  << EBU_CLC_DIV2ACK_Pos)\r
-\r
-#define   EBU_CLC_EBUDIVACK_Pos        (22U)\r
-#define   EBU_CLC_EBUDIVACK_Msk        (0x00000003U  << EBU_CLC_EBUDIVACK_Pos)\r
-\r
-/* EBU_MODCON  =  EBU Configuration Register*/\r
-#define   EBU_MODCON_STS_Pos   (0U)\r
-#define   EBU_MODCON_STS_Msk   (0x00000001U  << EBU_MODCON_STS_Pos)\r
-\r
-#define   EBU_MODCON_LCKABRT_Pos       (1U)\r
-#define   EBU_MODCON_LCKABRT_Msk       (0x00000001U  << EBU_MODCON_LCKABRT_Pos)\r
-\r
-#define   EBU_MODCON_SDTRI_Pos         (2U)\r
-#define   EBU_MODCON_SDTRI_Msk         (0x00000001U  << EBU_MODCON_SDTRI_Pos)\r
-\r
-#define   EBU_MODCON_EXTLOCK_Pos       (4U)\r
-#define   EBU_MODCON_EXTLOCK_Msk       (0x00000001U  << EBU_MODCON_EXTLOCK_Pos)\r
-\r
-#define   EBU_MODCON_ARBSYNC_Pos       (5U)\r
-#define   EBU_MODCON_ARBSYNC_Msk       (0x00000001U  << EBU_MODCON_ARBSYNC_Pos)\r
-\r
-#define   EBU_MODCON_ARBMODE_Pos       (6U)\r
-#define   EBU_MODCON_ARBMODE_Msk       (0x00000003U  << EBU_MODCON_ARBMODE_Pos)\r
-\r
-#define   EBU_MODCON_TIMEOUTC_Pos      (8U)\r
-#define   EBU_MODCON_TIMEOUTC_Msk      (0x000000FFU  << EBU_MODCON_TIMEOUTC_Pos)\r
-\r
-#define   EBU_MODCON_LOCKTIMEOUT_Pos   (16U)\r
-#define   EBU_MODCON_LOCKTIMEOUT_Msk   (0x000000FFU  << EBU_MODCON_LOCKTIMEOUT_Pos)\r
-\r
-#define   EBU_MODCON_GLOBALCS_Pos      (24U)\r
-#define   EBU_MODCON_GLOBALCS_Msk      (0x0000000FU  << EBU_MODCON_GLOBALCS_Pos)\r
-\r
-#define   EBU_MODCON_ACCSINH_Pos       (28U)\r
-#define   EBU_MODCON_ACCSINH_Msk       (0x00000001U  << EBU_MODCON_ACCSINH_Pos)\r
-\r
-#define   EBU_MODCON_ACCSINHACK_Pos    (29U)\r
-#define   EBU_MODCON_ACCSINHACK_Msk    (0x00000001U  << EBU_MODCON_ACCSINHACK_Pos)\r
-\r
-#define   EBU_MODCON_ALE_Pos   (31U)\r
-#define   EBU_MODCON_ALE_Msk   (0x00000001U  << EBU_MODCON_ALE_Pos)\r
-\r
-/* EBU_ID  =  EBU Module Identification Register*/\r
-#define   EBU_ID_MOD_REV_Pos   (0U)\r
-#define   EBU_ID_MOD_REV_Msk   (0x000000FFU  << EBU_ID_MOD_REV_Pos)\r
-\r
-#define   EBU_ID_MOD_TYPE_Pos          (8U)\r
-#define   EBU_ID_MOD_TYPE_Msk          (0x000000FFU  << EBU_ID_MOD_TYPE_Pos)\r
-\r
-#define   EBU_ID_MOD_NUMBER_Pos        (16U)\r
-#define   EBU_ID_MOD_NUMBER_Msk        (0x0000FFFFU  << EBU_ID_MOD_NUMBER_Pos)\r
-\r
-/* EBU_USERCON  =  EBU Test/Control Configuration Register*/\r
-#define   EBU_USERCON_DIP_Pos          (0U)\r
-#define   EBU_USERCON_DIP_Msk          (0x00000001U  << EBU_USERCON_DIP_Pos)\r
-\r
-#define   EBU_USERCON_ADDIO_Pos        (16U)\r
-#define   EBU_USERCON_ADDIO_Msk        (0x000001FFU  << EBU_USERCON_ADDIO_Pos)\r
-\r
-#define   EBU_USERCON_ADVIO_Pos        (25U)\r
-#define   EBU_USERCON_ADVIO_Msk        (0x00000001U  << EBU_USERCON_ADVIO_Pos)\r
-\r
-/* EBU_CS_ADDRSELx  =  EBU Address Select Register 0*/\r
-#define   EBU_CS_ADDRSEL_REGENAB_Pos   (0U)\r
-#define   EBU_CS_ADDRSEL_REGENAB_Msk   (0x00000001U  << EBU_CS_ADDRSEL_REGENAB_Pos)\r
-\r
-#define   EBU_CS_ADDRSEL_ALTENAB_Pos   (1U)\r
-#define   EBU_CS_ADDRSEL_ALTENAB_Msk   (0x00000001U  << EBU_CS_ADDRSEL_ALTENAB_Pos)\r
-\r
-#define   EBU_CS_ADDRSEL_WPROT_Pos     (2U)\r
-#define   EBU_CS_ADDRSEL_WPROT_Msk     (0x00000001U  << EBU_CS_ADDRSEL_WPROT_Pos)\r
-\r
-/* EBU_CS_BUSRCONx  =  EBU Bus Configuration Register*/\r
-#define   EBU_CS_BUSRCON_FETBLEN_Pos   (0U)\r
-#define   EBU_CS_BUSRCON_FETBLEN_Msk   (0x00000007U  << EBU_CS_BUSRCON_FETBLEN_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_FBBMSEL_Pos   (3U)\r
-#define   EBU_CS_BUSRCON_FBBMSEL_Msk   (0x00000001U  << EBU_CS_BUSRCON_FBBMSEL_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_BFSSS_Pos     (4U)\r
-#define   EBU_CS_BUSRCON_BFSSS_Msk     (0x00000001U  << EBU_CS_BUSRCON_BFSSS_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_FDBKEN_Pos    (5U)\r
-#define   EBU_CS_BUSRCON_FDBKEN_Msk    (0x00000001U  << EBU_CS_BUSRCON_FDBKEN_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_BFCMSEL_Pos   (6U)\r
-#define   EBU_CS_BUSRCON_BFCMSEL_Msk   (0x00000001U  << EBU_CS_BUSRCON_BFCMSEL_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_NAA_Pos       (7U)\r
-#define   EBU_CS_BUSRCON_NAA_Msk       (0x00000001U  << EBU_CS_BUSRCON_NAA_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_ECSE_Pos      (16U)\r
-#define   EBU_CS_BUSRCON_ECSE_Msk      (0x00000001U  << EBU_CS_BUSRCON_ECSE_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_EBSE_Pos      (17U)\r
-#define   EBU_CS_BUSRCON_EBSE_Msk      (0x00000001U  << EBU_CS_BUSRCON_EBSE_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_DBA_Pos       (18U)\r
-#define   EBU_CS_BUSRCON_DBA_Msk       (0x00000001U  << EBU_CS_BUSRCON_DBA_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_WAITINV_Pos   (19U)\r
-#define   EBU_CS_BUSRCON_WAITINV_Msk   (0x00000001U  << EBU_CS_BUSRCON_WAITINV_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_BCGEN_Pos     (20U)\r
-#define   EBU_CS_BUSRCON_BCGEN_Msk     (0x00000003U  << EBU_CS_BUSRCON_BCGEN_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_PORTW_Pos     (22U)\r
-#define   EBU_CS_BUSRCON_PORTW_Msk     (0x00000003U  << EBU_CS_BUSRCON_PORTW_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_WAIT_Pos      (24U)\r
-#define   EBU_CS_BUSRCON_WAIT_Msk      (0x00000003U  << EBU_CS_BUSRCON_WAIT_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_AAP_Pos       (26U)\r
-#define   EBU_CS_BUSRCON_AAP_Msk       (0x00000001U  << EBU_CS_BUSRCON_AAP_Pos)\r
-\r
-#define   EBU_CS_BUSRCON_AGEN_Pos      (28U)\r
-#define   EBU_CS_BUSRCON_AGEN_Msk      (0x0000000FU  << EBU_CS_BUSRCON_AGEN_Pos)\r
-\r
-/* EBU_CS_BUSRAPx  =  EBU Bus Read Access Parameter Register*/\r
-#define   EBU_CS_BUSRAP_RDDTACS_Pos    (0U)\r
-#define   EBU_CS_BUSRAP_RDDTACS_Msk    (0x0000000FU  << EBU_CS_BUSRAP_RDDTACS_Pos)\r
-\r
-#define   EBU_CS_BUSRAP_RDRECOVC_Pos   (4U)\r
-#define   EBU_CS_BUSRAP_RDRECOVC_Msk   (0x00000007U  << EBU_CS_BUSRAP_RDRECOVC_Pos)\r
-\r
-#define   EBU_CS_BUSRAP_WAITRDC_Pos    (7U)\r
-#define   EBU_CS_BUSRAP_WAITRDC_Msk    (0x0000001FU  << EBU_CS_BUSRAP_WAITRDC_Pos)\r
-\r
-#define   EBU_CS_BUSRAP_DATAC_Pos      (12U)\r
-#define   EBU_CS_BUSRAP_DATAC_Msk      (0x0000000FU  << EBU_CS_BUSRAP_DATAC_Pos)\r
-\r
-#define   EBU_CS_BUSRAP_EXTCLOCK_Pos   (16U)\r
-#define   EBU_CS_BUSRAP_EXTCLOCK_Msk   (0x00000003U  << EBU_CS_BUSRAP_EXTCLOCK_Pos)\r
-\r
-#define   EBU_CS_BUSRAP_EXTDATA_Pos    (18U)\r
-#define   EBU_CS_BUSRAP_EXTDATA_Msk    (0x00000003U  << EBU_CS_BUSRAP_EXTDATA_Pos)\r
-\r
-#define   EBU_CS_BUSRAP_CMDDELAY_Pos   (20U)\r
-#define   EBU_CS_BUSRAP_CMDDELAY_Msk   (0x0000000FU  << EBU_CS_BUSRAP_CMDDELAY_Pos)\r
-\r
-#define   EBU_CS_BUSRAP_AHOLDC_Pos     (24U)\r
-#define   EBU_CS_BUSRAP_AHOLDC_Msk     (0x0000000FU  << EBU_CS_BUSRAP_AHOLDC_Pos)\r
-\r
-#define   EBU_CS_BUSRAP_ADDRC_Pos      (28U)\r
-#define   EBU_CS_BUSRAP_ADDRC_Msk      (0x0000000FU  << EBU_CS_BUSRAP_ADDRC_Pos)\r
-\r
-/* EBU_CS_BUSWCONx  =  EBU Bus Write Configuration Register*/\r
-#define   EBU_CS_BUSWCON_FETBLEN_Pos   (0U)\r
-#define   EBU_CS_BUSWCON_FETBLEN_Msk   (0x00000007U  << EBU_CS_BUSWCON_FETBLEN_Pos)\r
-\r
-#define   EBU_CS_BUSWCON_FBBMSEL_Pos   (3U)\r
-#define   EBU_CS_BUSWCON_FBBMSEL_Msk   (0x00000001U  << EBU_CS_BUSWCON_FBBMSEL_Pos)\r
-\r
-#define   EBU_CS_BUSWCON_NAA_Pos       (7U)\r
-#define   EBU_CS_BUSWCON_NAA_Msk       (0x00000001U  << EBU_CS_BUSWCON_NAA_Pos)\r
-\r
-#define   EBU_CS_BUSWCON_ECSE_Pos      (16U)\r
-#define   EBU_CS_BUSWCON_ECSE_Msk      (0x00000001U  << EBU_CS_BUSWCON_ECSE_Pos)\r
-\r
-#define   EBU_CS_BUSWCON_EBSE_Pos      (17U)\r
-#define   EBU_CS_BUSWCON_EBSE_Msk      (0x00000001U  << EBU_CS_BUSWCON_EBSE_Pos)\r
-\r
-#define   EBU_CS_BUSWCON_WAITINV_Pos   (19U)\r
-#define   EBU_CS_BUSWCON_WAITINV_Msk   (0x00000001U  << EBU_CS_BUSWCON_WAITINV_Pos)\r
-\r
-#define   EBU_CS_BUSWCON_BCGEN_Pos     (20U)\r
-#define   EBU_CS_BUSWCON_BCGEN_Msk     (0x00000003U  << EBU_CS_BUSWCON_BCGEN_Pos)\r
-\r
-#define   EBU_CS_BUSWCON_PORTW_Pos     (22U)\r
-#define   EBU_CS_BUSWCON_PORTW_Msk     (0x00000003U  << EBU_CS_BUSWCON_PORTW_Pos)\r
-\r
-#define   EBU_CS_BUSWCON_WAIT_Pos      (24U)\r
-#define   EBU_CS_BUSWCON_WAIT_Msk      (0x00000003U  << EBU_CS_BUSWCON_WAIT_Pos)\r
-\r
-#define   EBU_CS_BUSWCON_AAP_Pos       (26U)\r
-#define   EBU_CS_BUSWCON_AAP_Msk       (0x00000001U  << EBU_CS_BUSWCON_AAP_Pos)\r
-\r
-#define   EBU_CS_BUSWCON_LOCKCS_Pos    (27U)\r
-#define   EBU_CS_BUSWCON_LOCKCS_Msk    (0x00000001U  << EBU_CS_BUSWCON_LOCKCS_Pos)\r
-\r
-#define   EBU_CS_BUSWCON_AGEN_Pos      (28U)\r
-#define   EBU_CS_BUSWCON_AGEN_Msk      (0x0000000FU  << EBU_CS_BUSWCON_AGEN_Pos)\r
-\r
-/* EBU_CS_BUSWAPx  =  EBU Bus Write Access Parameter Register*/\r
-#define   EBU_CS_BUSWAP_WRDTACS_Pos    (0U)\r
-#define   EBU_CS_BUSWAP_WRDTACS_Msk    (0x0000000FU  << EBU_CS_BUSWAP_WRDTACS_Pos)\r
-\r
-#define   EBU_CS_BUSWAP_WRRECOVC_Pos   (4U)\r
-#define   EBU_CS_BUSWAP_WRRECOVC_Msk   (0x00000007U  << EBU_CS_BUSWAP_WRRECOVC_Pos)\r
-\r
-#define   EBU_CS_BUSWAP_WAITWRC_Pos    (7U)\r
-#define   EBU_CS_BUSWAP_WAITWRC_Msk    (0x0000001FU  << EBU_CS_BUSWAP_WAITWRC_Pos)\r
-\r
-#define   EBU_CS_BUSWAP_DATAC_Pos      (12U)\r
-#define   EBU_CS_BUSWAP_DATAC_Msk      (0x0000000FU  << EBU_CS_BUSWAP_DATAC_Pos)\r
-\r
-#define   EBU_CS_BUSWAP_EXTCLOCK_Pos   (16U)\r
-#define   EBU_CS_BUSWAP_EXTCLOCK_Msk   (0x00000003U  << EBU_CS_BUSWAP_EXTCLOCK_Pos)\r
-\r
-#define   EBU_CS_BUSWAP_EXTDATA_Pos    (18U)\r
-#define   EBU_CS_BUSWAP_EXTDATA_Msk    (0x00000003U  << EBU_CS_BUSWAP_EXTDATA_Pos)\r
-\r
-#define   EBU_CS_BUSWAP_CMDDELAY_Pos   (20U)\r
-#define   EBU_CS_BUSWAP_CMDDELAY_Msk   (0x0000000FU  << EBU_CS_BUSWAP_CMDDELAY_Pos)\r
-\r
-#define   EBU_CS_BUSWAP_AHOLDC_Pos     (24U)\r
-#define   EBU_CS_BUSWAP_AHOLDC_Msk     (0x0000000FU  << EBU_CS_BUSWAP_AHOLDC_Pos)\r
-\r
-#define   EBU_CS_BUSWAP_ADDRC_Pos      (28U)\r
-#define   EBU_CS_BUSWAP_ADDRC_Msk      (0x0000000FU  << EBU_CS_BUSWAP_ADDRC_Pos)\r
-\r
-/* EBU_SDRAM_SDRMCON  =  EBU SDRAM Control Register*/\r
-#define   EBU_SDRAM_SDRMCON_SDCMSEL_Pos        (31U)\r
-#define   EBU_SDRAM_SDRMCON_SDCMSEL_Msk        (0x00000001U  << EBU_SDRAM_SDRMCON_SDCMSEL_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_PWR_MODE_Pos       (29U)\r
-#define   EBU_SDRAM_SDRMCON_PWR_MODE_Msk       (0x00000003U  << EBU_SDRAM_SDRMCON_PWR_MODE_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_CLKDIS_Pos         (28U)\r
-#define   EBU_SDRAM_SDRMCON_CLKDIS_Msk         (0x00000001U  << EBU_SDRAM_SDRMCON_CLKDIS_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_CRCE_Pos   (25U)\r
-#define   EBU_SDRAM_SDRMCON_CRCE_Msk   (0x00000007U  << EBU_SDRAM_SDRMCON_CRCE_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_BANKM_Pos          (22U)\r
-#define   EBU_SDRAM_SDRMCON_BANKM_Msk          (0x00000007U  << EBU_SDRAM_SDRMCON_BANKM_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_ROWM_Pos   (19U)\r
-#define   EBU_SDRAM_SDRMCON_ROWM_Msk   (0x00000007U  << EBU_SDRAM_SDRMCON_ROWM_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_CRC_Pos    (16U)\r
-#define   EBU_SDRAM_SDRMCON_CRC_Msk    (0x00000007U  << EBU_SDRAM_SDRMCON_CRC_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_CRCD_Pos   (14U)\r
-#define   EBU_SDRAM_SDRMCON_CRCD_Msk   (0x00000003U  << EBU_SDRAM_SDRMCON_CRCD_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_AWIDTH_Pos         (12U)\r
-#define   EBU_SDRAM_SDRMCON_AWIDTH_Msk         (0x00000003U  << EBU_SDRAM_SDRMCON_AWIDTH_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_CRP_Pos    (10U)\r
-#define   EBU_SDRAM_SDRMCON_CRP_Msk    (0x00000003U  << EBU_SDRAM_SDRMCON_CRP_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_CRSC_Pos   (8U)\r
-#define   EBU_SDRAM_SDRMCON_CRSC_Msk   (0x00000003U  << EBU_SDRAM_SDRMCON_CRSC_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_CRFSH_Pos          (4U)\r
-#define   EBU_SDRAM_SDRMCON_CRFSH_Msk          (0x0000000FU  << EBU_SDRAM_SDRMCON_CRFSH_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMCON_CRAS_Pos   (0U)\r
-#define   EBU_SDRAM_SDRMCON_CRAS_Msk   (0x0000000FU  << EBU_SDRAM_SDRMCON_CRAS_Pos)\r
-\r
-/* EBU_SDRAM_SDRMOD  =  EBU SDRAM Mode Register*/\r
-#define   EBU_SDRAM_SDRMOD_XBA_Pos     (28U)\r
-#define   EBU_SDRAM_SDRMOD_XBA_Msk     (0x0000000FU  << EBU_SDRAM_SDRMOD_XBA_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMOD_XOPM_Pos    (16U)\r
-#define   EBU_SDRAM_SDRMOD_XOPM_Msk    (0x00000FFFU  << EBU_SDRAM_SDRMOD_XOPM_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMOD_COLDSTART_Pos       (15U)\r
-#define   EBU_SDRAM_SDRMOD_COLDSTART_Msk       (0x00000001U  << EBU_SDRAM_SDRMOD_COLDSTART_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMOD_OPMODE_Pos          (7U)\r
-#define   EBU_SDRAM_SDRMOD_OPMODE_Msk          (0x0000007FU  << EBU_SDRAM_SDRMOD_OPMODE_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMOD_CASLAT_Pos          (4U)\r
-#define   EBU_SDRAM_SDRMOD_CASLAT_Msk          (0x00000007U  << EBU_SDRAM_SDRMOD_CASLAT_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMOD_BTYP_Pos    (3U)\r
-#define   EBU_SDRAM_SDRMOD_BTYP_Msk    (0x00000001U  << EBU_SDRAM_SDRMOD_BTYP_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMOD_BURSTL_Pos          (0U)\r
-#define   EBU_SDRAM_SDRMOD_BURSTL_Msk          (0x00000007U  << EBU_SDRAM_SDRMOD_BURSTL_Pos)\r
-\r
-/* EBU_SDRAM_SDRMREF  =  EBU SDRAM Refresh Control Register*/\r
-#define   EBU_SDRAM_SDRMREF_RES_DLY_Pos        (25U)\r
-#define   EBU_SDRAM_SDRMREF_RES_DLY_Msk        (0x00000007U  << EBU_SDRAM_SDRMREF_RES_DLY_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMREF_ARFSH_Pos          (24U)\r
-#define   EBU_SDRAM_SDRMREF_ARFSH_Msk          (0x00000001U  << EBU_SDRAM_SDRMREF_ARFSH_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMREF_SELFREX_DLY_Pos    (16U)\r
-#define   EBU_SDRAM_SDRMREF_SELFREX_DLY_Msk    (0x000000FFU  << EBU_SDRAM_SDRMREF_SELFREX_DLY_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMREF_ERFSHC_Pos         (14U)\r
-#define   EBU_SDRAM_SDRMREF_ERFSHC_Msk         (0x00000003U  << EBU_SDRAM_SDRMREF_ERFSHC_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMREF_AUTOSELFR_Pos      (13U)\r
-#define   EBU_SDRAM_SDRMREF_AUTOSELFR_Msk      (0x00000001U  << EBU_SDRAM_SDRMREF_AUTOSELFR_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMREF_SELFREN_Pos        (12U)\r
-#define   EBU_SDRAM_SDRMREF_SELFREN_Msk        (0x00000001U  << EBU_SDRAM_SDRMREF_SELFREN_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMREF_SELFRENST_Pos      (11U)\r
-#define   EBU_SDRAM_SDRMREF_SELFRENST_Msk      (0x00000001U  << EBU_SDRAM_SDRMREF_SELFRENST_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMREF_SELFREX_Pos        (10U)\r
-#define   EBU_SDRAM_SDRMREF_SELFREX_Msk        (0x00000001U  << EBU_SDRAM_SDRMREF_SELFREX_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMREF_SELFREXST_Pos      (9U)\r
-#define   EBU_SDRAM_SDRMREF_SELFREXST_Msk      (0x00000001U  << EBU_SDRAM_SDRMREF_SELFREXST_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMREF_REFRESHR_Pos       (6U)\r
-#define   EBU_SDRAM_SDRMREF_REFRESHR_Msk       (0x00000007U  << EBU_SDRAM_SDRMREF_REFRESHR_Pos)\r
-\r
-#define   EBU_SDRAM_SDRMREF_REFRESHC_Pos       (0U)\r
-#define   EBU_SDRAM_SDRMREF_REFRESHC_Msk       (0x0000003FU  << EBU_SDRAM_SDRMREF_REFRESHC_Pos)\r
-\r
-/* EBU_SDRAM_SDRSTAT  =  EBU SDRAM Status Register*/\r
-#define   EBU_SDRAM_SDRSTAT_SDERR_Pos          (2U)\r
-#define   EBU_SDRAM_SDRSTAT_SDERR_Msk          (0x00000001U  << EBU_SDRAM_SDRSTAT_SDERR_Pos)\r
-\r
-#define   EBU_SDRAM_SDRSTAT_SDRMBUSY_Pos       (1U)\r
-#define   EBU_SDRAM_SDRSTAT_SDRMBUSY_Msk       (0x00000001U  << EBU_SDRAM_SDRSTAT_SDRMBUSY_Pos)\r
-\r
-#define   EBU_SDRAM_SDRSTAT_REFERR_Pos         (0U)\r
-#define   EBU_SDRAM_SDRSTAT_REFERR_Msk         (0x00000001U  << EBU_SDRAM_SDRSTAT_REFERR_Pos)\r
-\r
-\r
-\r
-/***   ERUx Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* ERU_EXISEL  =  Event Input Select Register 0*/\r
-#define   ERU_EXISEL_EXS0A_Pos         (0U)\r
-#define   ERU_EXISEL_EXS0A_Msk         (0x00000003U  << ERU_EXISEL_EXS0A_Pos)\r
-\r
-#define   ERU_EXISEL_EXS0B_Pos         (2U)\r
-#define   ERU_EXISEL_EXS0B_Msk         (0x00000003U  << ERU_EXISEL_EXS0B_Pos)\r
-\r
-#define   ERU_EXISEL_EXS1A_Pos         (4U)\r
-#define   ERU_EXISEL_EXS1A_Msk         (0x00000003U  << ERU_EXISEL_EXS1A_Pos)\r
-\r
-#define   ERU_EXISEL_EXS1B_Pos         (6U)\r
-#define   ERU_EXISEL_EXS1B_Msk         (0x00000003U  << ERU_EXISEL_EXS1B_Pos)\r
-\r
-#define   ERU_EXISEL_EXS2A_Pos         (8U)\r
-#define   ERU_EXISEL_EXS2A_Msk         (0x00000003U  << ERU_EXISEL_EXS2A_Pos)\r
-\r
-#define   ERU_EXISEL_EXS2B_Pos         (10U)\r
-#define   ERU_EXISEL_EXS2B_Msk         (0x00000003U  << ERU_EXISEL_EXS2B_Pos)\r
-\r
-#define   ERU_EXISEL_EXS3A_Pos         (12U)\r
-#define   ERU_EXISEL_EXS3A_Msk         (0x00000003U  << ERU_EXISEL_EXS3A_Pos)\r
-\r
-#define   ERU_EXISEL_EXS3B_Pos         (14U)\r
-#define   ERU_EXISEL_EXS3B_Msk         (0x00000003U  << ERU_EXISEL_EXS3B_Pos)\r
-\r
-/* ERU_EXICON0  =  Event Input Control x Register*/\r
-#define   ERU_EXICON_PE_Pos    (0U)\r
-#define   ERU_EXICON_PE_Msk    (0x00000001U  << ERU_EXICON_PE_Pos)\r
-\r
-#define   ERU_EXICON_LD_Pos    (1U)\r
-#define   ERU_EXICON_LD_Msk    (0x00000001U  << ERU_EXICON_LD_Pos)\r
-\r
-#define   ERU_EXICON_RE_Pos    (2U)\r
-#define   ERU_EXICON_RE_Msk    (0x00000001U  << ERU_EXICON_RE_Pos)\r
-\r
-#define   ERU_EXICON_FE_Pos    (3U)\r
-#define   ERU_EXICON_FE_Msk    (0x00000001U  << ERU_EXICON_FE_Pos)\r
-\r
-#define   ERU_EXICON_OCS_Pos   (4U)\r
-#define   ERU_EXICON_OCS_Msk   (0x00000007U  << ERU_EXICON_OCS_Pos)\r
-\r
-#define   ERU_EXICON_FL_Pos    (7U)\r
-#define   ERU_EXICON_FL_Msk    (0x00000001U  << ERU_EXICON_FL_Pos)\r
-\r
-#define   ERU_EXICON_SS_Pos    (8U)\r
-#define   ERU_EXICON_SS_Msk    (0x00000003U  << ERU_EXICON_SS_Pos)\r
-\r
-#define   ERU_EXICON_NA_Pos    (10U)\r
-#define   ERU_EXICON_NA_Msk    (0x00000001U  << ERU_EXICON_NA_Pos)\r
-\r
-#define   ERU_EXICON_NB_Pos    (11U)\r
-#define   ERU_EXICON_NB_Msk    (0x00000001U  << ERU_EXICON_NB_Pos)\r
-\r
-\r
-/* ERU_EXOCON0  =  Event Output Trigger Control x Register*/\r
-#define   ERU_EXOCON_ISS_Pos   (0U)\r
-#define   ERU_EXOCON_ISS_Msk   (0x00000003U  << ERU_EXOCON_ISS_Pos)\r
-\r
-#define   ERU_EXOCON_GEEN_Pos          (2U)\r
-#define   ERU_EXOCON_GEEN_Msk          (0x00000001U  << ERU_EXOCON_GEEN_Pos)\r
-\r
-#define   ERU_EXOCON_PDR_Pos   (3U)\r
-#define   ERU_EXOCON_PDR_Msk   (0x00000001U  << ERU_EXOCON_PDR_Pos)\r
-\r
-#define   ERU_EXOCON_GP_Pos    (4U)\r
-#define   ERU_EXOCON_GP_Msk    (0x00000003U  << ERU_EXOCON_GP_Pos)\r
-\r
-#define   ERU_EXOCON_IPEN0_Pos         (12U)\r
-#define   ERU_EXOCON_IPEN0_Msk         (0x00000001U  << ERU_EXOCON_IPEN0_Pos)\r
-\r
-#define   ERU_EXOCON_IPEN1_Pos         (13U)\r
-#define   ERU_EXOCON_IPEN1_Msk         (0x00000001U  << ERU_EXOCON_IPEN1_Pos)\r
-\r
-#define   ERU_EXOCON_IPEN2_Pos         (14U)\r
-#define   ERU_EXOCON_IPEN2_Msk         (0x00000001U  << ERU_EXOCON_IPEN2_Pos)\r
-\r
-#define   ERU_EXOCON_IPEN3_Pos         (15U)\r
-#define   ERU_EXOCON_IPEN3_Msk         (0x00000001U  << ERU_EXOCON_IPEN3_Pos)\r
-\r
-\r
-/***   ETHx Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* ETH_MAC_CONFIGURATION  =  Register x [MAC Configuration Register]*/\r
-#define   ETH_MAC_CONFIGURATION_PRELEN_Pos     (0U)\r
-#define   ETH_MAC_CONFIGURATION_PRELEN_Msk     (0x00000003U  << ETH_MAC_CONFIGURATION_PRELEN_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_RE_Pos         (2U)\r
-#define   ETH_MAC_CONFIGURATION_RE_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_RE_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_TE_Pos         (3U)\r
-#define   ETH_MAC_CONFIGURATION_TE_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_TE_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_DC_Pos         (4U)\r
-#define   ETH_MAC_CONFIGURATION_DC_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_DC_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_BL_Pos         (5U)\r
-#define   ETH_MAC_CONFIGURATION_BL_Msk         (0x00000003U  << ETH_MAC_CONFIGURATION_BL_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_ACS_Pos        (7U)\r
-#define   ETH_MAC_CONFIGURATION_ACS_Msk        (0x00000001U  << ETH_MAC_CONFIGURATION_ACS_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_LUD_Pos        (8U)\r
-#define   ETH_MAC_CONFIGURATION_LUD_Msk        (0x00000001U  << ETH_MAC_CONFIGURATION_LUD_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_DR_Pos         (9U)\r
-#define   ETH_MAC_CONFIGURATION_DR_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_DR_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_IPC_Pos        (10U)\r
-#define   ETH_MAC_CONFIGURATION_IPC_Msk        (0x00000001U  << ETH_MAC_CONFIGURATION_IPC_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_DM_Pos         (11U)\r
-#define   ETH_MAC_CONFIGURATION_DM_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_DM_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_LM_Pos         (12U)\r
-#define   ETH_MAC_CONFIGURATION_LM_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_LM_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_DO_Pos         (13U)\r
-#define   ETH_MAC_CONFIGURATION_DO_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_DO_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_FES_Pos        (14U)\r
-#define   ETH_MAC_CONFIGURATION_FES_Msk        (0x00000001U  << ETH_MAC_CONFIGURATION_FES_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_Reserved_Pos   (15U)\r
-#define   ETH_MAC_CONFIGURATION_Reserved_Msk   (0x00000001U  << ETH_MAC_CONFIGURATION_Reserved_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_DCRS_Pos       (16U)\r
-#define   ETH_MAC_CONFIGURATION_DCRS_Msk       (0x00000001U  << ETH_MAC_CONFIGURATION_DCRS_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_IFG_Pos        (17U)\r
-#define   ETH_MAC_CONFIGURATION_IFG_Msk        (0x00000007U  << ETH_MAC_CONFIGURATION_IFG_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_JE_Pos         (20U)\r
-#define   ETH_MAC_CONFIGURATION_JE_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_JE_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_BE_Pos         (21U)\r
-#define   ETH_MAC_CONFIGURATION_BE_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_BE_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_JD_Pos         (22U)\r
-#define   ETH_MAC_CONFIGURATION_JD_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_JD_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_WD_Pos         (23U)\r
-#define   ETH_MAC_CONFIGURATION_WD_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_WD_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_TC_Pos         (24U)\r
-#define   ETH_MAC_CONFIGURATION_TC_Msk         (0x00000001U  << ETH_MAC_CONFIGURATION_TC_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_CST_Pos        (25U)\r
-#define   ETH_MAC_CONFIGURATION_CST_Msk        (0x00000001U  << ETH_MAC_CONFIGURATION_CST_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_Reserved_26_Pos        (26U)\r
-#define   ETH_MAC_CONFIGURATION_Reserved_26_Msk        (0x00000001U  << ETH_MAC_CONFIGURATION_Reserved_26_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_TWOKPE_Pos     (27U)\r
-#define   ETH_MAC_CONFIGURATION_TWOKPE_Msk     (0x00000001U  << ETH_MAC_CONFIGURATION_TWOKPE_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_SARC_Pos       (28U)\r
-#define   ETH_MAC_CONFIGURATION_SARC_Msk       (0x00000007U  << ETH_MAC_CONFIGURATION_SARC_Pos)\r
-\r
-#define   ETH_MAC_CONFIGURATION_Reserved_31_Pos        (31U)\r
-#define   ETH_MAC_CONFIGURATION_Reserved_31_Msk        (0x00000001U  << ETH_MAC_CONFIGURATION_Reserved_31_Pos)\r
-\r
-/* ETH_MAC_FRAME_FILTER  =  Register 1 [MAC Frame Filter]*/\r
-#define   ETH_MAC_FRAME_FILTER_PR_Pos          (0U)\r
-#define   ETH_MAC_FRAME_FILTER_PR_Msk          (0x00000001U  << ETH_MAC_FRAME_FILTER_PR_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_HUC_Pos         (1U)\r
-#define   ETH_MAC_FRAME_FILTER_HUC_Msk         (0x00000001U  << ETH_MAC_FRAME_FILTER_HUC_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_HMC_Pos         (2U)\r
-#define   ETH_MAC_FRAME_FILTER_HMC_Msk         (0x00000001U  << ETH_MAC_FRAME_FILTER_HMC_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_DAIF_Pos        (3U)\r
-#define   ETH_MAC_FRAME_FILTER_DAIF_Msk        (0x00000001U  << ETH_MAC_FRAME_FILTER_DAIF_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_PM_Pos          (4U)\r
-#define   ETH_MAC_FRAME_FILTER_PM_Msk          (0x00000001U  << ETH_MAC_FRAME_FILTER_PM_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_DBF_Pos         (5U)\r
-#define   ETH_MAC_FRAME_FILTER_DBF_Msk         (0x00000001U  << ETH_MAC_FRAME_FILTER_DBF_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_PCF_Pos         (6U)\r
-#define   ETH_MAC_FRAME_FILTER_PCF_Msk         (0x00000003U  << ETH_MAC_FRAME_FILTER_PCF_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_SAIF_Pos        (8U)\r
-#define   ETH_MAC_FRAME_FILTER_SAIF_Msk        (0x00000001U  << ETH_MAC_FRAME_FILTER_SAIF_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_SAF_Pos         (9U)\r
-#define   ETH_MAC_FRAME_FILTER_SAF_Msk         (0x00000001U  << ETH_MAC_FRAME_FILTER_SAF_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_HPF_Pos         (10U)\r
-#define   ETH_MAC_FRAME_FILTER_HPF_Msk         (0x00000001U  << ETH_MAC_FRAME_FILTER_HPF_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_Reserved_15_11_Pos      (11U)\r
-#define   ETH_MAC_FRAME_FILTER_Reserved_15_11_Msk      (0x0000001FU  << ETH_MAC_FRAME_FILTER_Reserved_15_11_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_VTFE_Pos        (16U)\r
-#define   ETH_MAC_FRAME_FILTER_VTFE_Msk        (0x00000001U  << ETH_MAC_FRAME_FILTER_VTFE_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_Reserved_19_17_Pos      (17U)\r
-#define   ETH_MAC_FRAME_FILTER_Reserved_19_17_Msk      (0x00000007U  << ETH_MAC_FRAME_FILTER_Reserved_19_17_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_IPFE_Pos        (20U)\r
-#define   ETH_MAC_FRAME_FILTER_IPFE_Msk        (0x00000001U  << ETH_MAC_FRAME_FILTER_IPFE_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_DNTU_Pos        (21U)\r
-#define   ETH_MAC_FRAME_FILTER_DNTU_Msk        (0x00000001U  << ETH_MAC_FRAME_FILTER_DNTU_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_Reserved_30_22_Pos      (22U)\r
-#define   ETH_MAC_FRAME_FILTER_Reserved_30_22_Msk      (0x000001FFU  << ETH_MAC_FRAME_FILTER_Reserved_30_22_Pos)\r
-\r
-#define   ETH_MAC_FRAME_FILTER_RA_Pos          (31U)\r
-#define   ETH_MAC_FRAME_FILTER_RA_Msk          (0x00000001U  << ETH_MAC_FRAME_FILTER_RA_Pos)\r
-\r
-/* ETH_HASH_TABLE_HIGH  =  Register 2 [Hash Table High Register]*/\r
-#define   ETH_HASH_TABLE_HIGH_HTH_Pos          (0U)\r
-#define   ETH_HASH_TABLE_HIGH_HTH_Msk          (0xFFFFFFFFU  << ETH_HASH_TABLE_HIGH_HTH_Pos)\r
-\r
-/* ETH_HASH_TABLE_LOW  =  Register 3 [Hash Table Low Register]*/\r
-#define   ETH_HASH_TABLE_LOW_HTL_Pos   (0U)\r
-#define   ETH_HASH_TABLE_LOW_HTL_Msk   (0xFFFFFFFFU  << ETH_HASH_TABLE_LOW_HTL_Pos)\r
-\r
-/* ETH_GMII_ADDRESS  =  Register 4 [MII Address Register)*/\r
-#define   ETH_GMII_ADDRESS_MB_Pos      (0U)\r
-#define   ETH_GMII_ADDRESS_MB_Msk      (0x00000001U  << ETH_GMII_ADDRESS_MB_Pos)\r
-\r
-#define   ETH_GMII_ADDRESS_MW_Pos      (1U)\r
-#define   ETH_GMII_ADDRESS_MW_Msk      (0x00000001U  << ETH_GMII_ADDRESS_MW_Pos)\r
-\r
-#define   ETH_GMII_ADDRESS_CR_Pos      (2U)\r
-#define   ETH_GMII_ADDRESS_CR_Msk      (0x0000000FU  << ETH_GMII_ADDRESS_CR_Pos)\r
-\r
-#define   ETH_GMII_ADDRESS_MR_Pos      (6U)\r
-#define   ETH_GMII_ADDRESS_MR_Msk      (0x0000001FU  << ETH_GMII_ADDRESS_MR_Pos)\r
-\r
-#define   ETH_GMII_ADDRESS_PA_Pos      (11U)\r
-#define   ETH_GMII_ADDRESS_PA_Msk      (0x0000001FU  << ETH_GMII_ADDRESS_PA_Pos)\r
-\r
-#define   ETH_GMII_ADDRESS_Reserved_31_16_Pos          (16U)\r
-#define   ETH_GMII_ADDRESS_Reserved_31_16_Msk          (0x0000FFFFU  << ETH_GMII_ADDRESS_Reserved_31_16_Pos)\r
-\r
-/* ETH_GMII_DATA  =  Register 5 [MII Data Register]*/\r
-#define   ETH_GMII_DATA_MD_Pos         (0U)\r
-#define   ETH_GMII_DATA_MD_Msk         (0x0000FFFFU  << ETH_GMII_DATA_MD_Pos)\r
-\r
-#define   ETH_GMII_DATA_Reserved_31_16_Pos     (16U)\r
-#define   ETH_GMII_DATA_Reserved_31_16_Msk     (0x0000FFFFU  << ETH_GMII_DATA_Reserved_31_16_Pos)\r
-\r
-/* ETH_FLOW_CONTROL  =  Register 6 [Flow Control Register]*/\r
-#define   ETH_FLOW_CONTROL_FCA_BPA_Pos         (0U)\r
-#define   ETH_FLOW_CONTROL_FCA_BPA_Msk         (0x00000001U  << ETH_FLOW_CONTROL_FCA_BPA_Pos)\r
-\r
-#define   ETH_FLOW_CONTROL_TFE_Pos     (1U)\r
-#define   ETH_FLOW_CONTROL_TFE_Msk     (0x00000001U  << ETH_FLOW_CONTROL_TFE_Pos)\r
-\r
-#define   ETH_FLOW_CONTROL_RFE_Pos     (2U)\r
-#define   ETH_FLOW_CONTROL_RFE_Msk     (0x00000001U  << ETH_FLOW_CONTROL_RFE_Pos)\r
-\r
-#define   ETH_FLOW_CONTROL_UP_Pos      (3U)\r
-#define   ETH_FLOW_CONTROL_UP_Msk      (0x00000001U  << ETH_FLOW_CONTROL_UP_Pos)\r
-\r
-#define   ETH_FLOW_CONTROL_PLT_Pos     (4U)\r
-#define   ETH_FLOW_CONTROL_PLT_Msk     (0x00000003U  << ETH_FLOW_CONTROL_PLT_Pos)\r
-\r
-#define   ETH_FLOW_CONTROL_Reserved_6_Pos      (6U)\r
-#define   ETH_FLOW_CONTROL_Reserved_6_Msk      (0x00000001U  << ETH_FLOW_CONTROL_Reserved_6_Pos)\r
-\r
-#define   ETH_FLOW_CONTROL_DZPQ_Pos    (7U)\r
-#define   ETH_FLOW_CONTROL_DZPQ_Msk    (0x00000001U  << ETH_FLOW_CONTROL_DZPQ_Pos)\r
-\r
-#define   ETH_FLOW_CONTROL_Reserved_15_8_Pos   (8U)\r
-#define   ETH_FLOW_CONTROL_Reserved_15_8_Msk   (0x000000FFU  << ETH_FLOW_CONTROL_Reserved_15_8_Pos)\r
-\r
-#define   ETH_FLOW_CONTROL_PT_Pos      (16U)\r
-#define   ETH_FLOW_CONTROL_PT_Msk      (0x0000FFFFU  << ETH_FLOW_CONTROL_PT_Pos)\r
-\r
-/* ETH_VLAN_TAG  =  Register 7 [VLAN Tag Register]*/\r
-#define   ETH_VLAN_TAG_VL_Pos          (0U)\r
-#define   ETH_VLAN_TAG_VL_Msk          (0x0000FFFFU  << ETH_VLAN_TAG_VL_Pos)\r
-\r
-#define   ETH_VLAN_TAG_ETV_Pos         (16U)\r
-#define   ETH_VLAN_TAG_ETV_Msk         (0x00000001U  << ETH_VLAN_TAG_ETV_Pos)\r
-\r
-#define   ETH_VLAN_TAG_VTIM_Pos        (17U)\r
-#define   ETH_VLAN_TAG_VTIM_Msk        (0x00000001U  << ETH_VLAN_TAG_VTIM_Pos)\r
-\r
-#define   ETH_VLAN_TAG_ESVL_Pos        (18U)\r
-#define   ETH_VLAN_TAG_ESVL_Msk        (0x00000001U  << ETH_VLAN_TAG_ESVL_Pos)\r
-\r
-#define   ETH_VLAN_TAG_VTHM_Pos        (19U)\r
-#define   ETH_VLAN_TAG_VTHM_Msk        (0x00000001U  << ETH_VLAN_TAG_VTHM_Pos)\r
-\r
-#define   ETH_VLAN_TAG_Reserved_31_20_Pos      (20U)\r
-#define   ETH_VLAN_TAG_Reserved_31_20_Msk      (0x00000FFFU  << ETH_VLAN_TAG_Reserved_31_20_Pos)\r
-\r
-/* ETH_VERSION  =  Register 8 [Version Register]*/\r
-#define   ETH_VERSION_SNPSVER_Pos      (0U)\r
-#define   ETH_VERSION_SNPSVER_Msk      (0x000000FFU  << ETH_VERSION_SNPSVER_Pos)\r
-\r
-#define   ETH_VERSION_USERVER_Pos      (8U)\r
-#define   ETH_VERSION_USERVER_Msk      (0x000000FFU  << ETH_VERSION_USERVER_Pos)\r
-\r
-#define   ETH_VERSION_Reserved_31_16_Pos       (16U)\r
-#define   ETH_VERSION_Reserved_31_16_Msk       (0x0000FFFFU  << ETH_VERSION_Reserved_31_16_Pos)\r
-\r
-/* ETH_DEBUG  =  Register 9 [Debug Register]*/\r
-#define   ETH_DEBUG_RPESTS_Pos         (0U)\r
-#define   ETH_DEBUG_RPESTS_Msk         (0x00000001U  << ETH_DEBUG_RPESTS_Pos)\r
-\r
-#define   ETH_DEBUG_RFCFCSTS_Pos       (1U)\r
-#define   ETH_DEBUG_RFCFCSTS_Msk       (0x00000003U  << ETH_DEBUG_RFCFCSTS_Pos)\r
-\r
-#define   ETH_DEBUG_Reserved_3_Pos     (3U)\r
-#define   ETH_DEBUG_Reserved_3_Msk     (0x00000001U  << ETH_DEBUG_Reserved_3_Pos)\r
-\r
-#define   ETH_DEBUG_RWCSTS_Pos         (4U)\r
-#define   ETH_DEBUG_RWCSTS_Msk         (0x00000001U  << ETH_DEBUG_RWCSTS_Pos)\r
-\r
-#define   ETH_DEBUG_RRCSTS_Pos         (5U)\r
-#define   ETH_DEBUG_RRCSTS_Msk         (0x00000003U  << ETH_DEBUG_RRCSTS_Pos)\r
-\r
-#define   ETH_DEBUG_Reserved_7_Pos     (7U)\r
-#define   ETH_DEBUG_Reserved_7_Msk     (0x00000001U  << ETH_DEBUG_Reserved_7_Pos)\r
-\r
-#define   ETH_DEBUG_RXFSTS_Pos         (8U)\r
-#define   ETH_DEBUG_RXFSTS_Msk         (0x00000003U  << ETH_DEBUG_RXFSTS_Pos)\r
-\r
-#define   ETH_DEBUG_Reserved_15_10_Pos         (10U)\r
-#define   ETH_DEBUG_Reserved_15_10_Msk         (0x0000003FU  << ETH_DEBUG_Reserved_15_10_Pos)\r
-\r
-#define   ETH_DEBUG_TPESTS_Pos         (16U)\r
-#define   ETH_DEBUG_TPESTS_Msk         (0x00000001U  << ETH_DEBUG_TPESTS_Pos)\r
-\r
-#define   ETH_DEBUG_TFCSTS_Pos         (17U)\r
-#define   ETH_DEBUG_TFCSTS_Msk         (0x00000003U  << ETH_DEBUG_TFCSTS_Pos)\r
-\r
-#define   ETH_DEBUG_TXPAUSED_Pos       (19U)\r
-#define   ETH_DEBUG_TXPAUSED_Msk       (0x00000001U  << ETH_DEBUG_TXPAUSED_Pos)\r
-\r
-#define   ETH_DEBUG_TRCSTS_Pos         (20U)\r
-#define   ETH_DEBUG_TRCSTS_Msk         (0x00000003U  << ETH_DEBUG_TRCSTS_Pos)\r
-\r
-#define   ETH_DEBUG_TWCSTS_Pos         (22U)\r
-#define   ETH_DEBUG_TWCSTS_Msk         (0x00000001U  << ETH_DEBUG_TWCSTS_Pos)\r
-\r
-#define   ETH_DEBUG_Reserved_23_Pos    (23U)\r
-#define   ETH_DEBUG_Reserved_23_Msk    (0x00000001U  << ETH_DEBUG_Reserved_23_Pos)\r
-\r
-#define   ETH_DEBUG_TXFSTS_Pos         (24U)\r
-#define   ETH_DEBUG_TXFSTS_Msk         (0x00000001U  << ETH_DEBUG_TXFSTS_Pos)\r
-\r
-#define   ETH_DEBUG_TXSTSFSTS_Pos      (25U)\r
-#define   ETH_DEBUG_TXSTSFSTS_Msk      (0x00000001U  << ETH_DEBUG_TXSTSFSTS_Pos)\r
-\r
-#define   ETH_DEBUG_Reserved_31_26_Pos         (26U)\r
-#define   ETH_DEBUG_Reserved_31_26_Msk         (0x0000003FU  << ETH_DEBUG_Reserved_31_26_Pos)\r
-\r
-/* ETH_REMOTE_WAKE_UP_FRAME_FILTER  =  */\r
-#define   ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos       (0U)\r
-#define   ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Msk       (0xFFFFFFFFU  << ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos)\r
-\r
-/* ETH_PMT_CONTROL_STATUS  =  Register 11 [PMT Control and Status Register]*/\r
-#define   ETH_PMT_CONTROL_STATUS_PWRDWN_Pos    (0U)\r
-#define   ETH_PMT_CONTROL_STATUS_PWRDWN_Msk    (0x00000001U  << ETH_PMT_CONTROL_STATUS_PWRDWN_Pos)\r
-\r
-#define   ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos          (1U)\r
-#define   ETH_PMT_CONTROL_STATUS_MGKPKTEN_Msk          (0x00000001U  << ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos)\r
-\r
-#define   ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos          (2U)\r
-#define   ETH_PMT_CONTROL_STATUS_RWKPKTEN_Msk          (0x00000001U  << ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos)\r
-\r
-#define   ETH_PMT_CONTROL_STATUS_Reserved_4_3_Pos      (3U)\r
-#define   ETH_PMT_CONTROL_STATUS_Reserved_4_3_Msk      (0x00000003U  << ETH_PMT_CONTROL_STATUS_Reserved_4_3_Pos)\r
-\r
-#define   ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos          (5U)\r
-#define   ETH_PMT_CONTROL_STATUS_MGKPRCVD_Msk          (0x00000001U  << ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos)\r
-\r
-#define   ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos          (6U)\r
-#define   ETH_PMT_CONTROL_STATUS_RWKPRCVD_Msk          (0x00000001U  << ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos)\r
-\r
-#define   ETH_PMT_CONTROL_STATUS_Reserved_8_7_Pos      (7U)\r
-#define   ETH_PMT_CONTROL_STATUS_Reserved_8_7_Msk      (0x00000003U  << ETH_PMT_CONTROL_STATUS_Reserved_8_7_Pos)\r
-\r
-#define   ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos         (9U)\r
-#define   ETH_PMT_CONTROL_STATUS_GLBLUCAST_Msk         (0x00000001U  << ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos)\r
-\r
-#define   ETH_PMT_CONTROL_STATUS_Reserved_30_10_Pos    (10U)\r
-#define   ETH_PMT_CONTROL_STATUS_Reserved_30_10_Msk    (0x001FFFFFU  << ETH_PMT_CONTROL_STATUS_Reserved_30_10_Pos)\r
-\r
-#define   ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos        (31U)\r
-#define   ETH_PMT_CONTROL_STATUS_RWKFILTRST_Msk        (0x00000001U  << ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos)\r
-\r
-/* ETH_INTERRUPT_STATUS  =  Register 14 [Interrupt Register]*/\r
-#define   ETH_INTERRUPT_STATUS_RMIIIS_Pos      (0U)\r
-#define   ETH_INTERRUPT_STATUS_RMIIIS_Msk      (0x00000001U  << ETH_INTERRUPT_STATUS_RMIIIS_Pos)\r
-\r
-#define   ETH_INTERRUPT_STATUS_Reserved_1_Pos          (1U)\r
-#define   ETH_INTERRUPT_STATUS_Reserved_1_Msk          (0x00000001U  << ETH_INTERRUPT_STATUS_Reserved_1_Pos)\r
-\r
-#define   ETH_INTERRUPT_STATUS_Reserved_2_Pos          (2U)\r
-#define   ETH_INTERRUPT_STATUS_Reserved_2_Msk          (0x00000001U  << ETH_INTERRUPT_STATUS_Reserved_2_Pos)\r
-\r
-#define   ETH_INTERRUPT_STATUS_PMTIS_Pos       (3U)\r
-#define   ETH_INTERRUPT_STATUS_PMTIS_Msk       (0x00000001U  << ETH_INTERRUPT_STATUS_PMTIS_Pos)\r
-\r
-#define   ETH_INTERRUPT_STATUS_MMCIS_Pos       (4U)\r
-#define   ETH_INTERRUPT_STATUS_MMCIS_Msk       (0x00000001U  << ETH_INTERRUPT_STATUS_MMCIS_Pos)\r
-\r
-#define   ETH_INTERRUPT_STATUS_MMCRXIS_Pos     (5U)\r
-#define   ETH_INTERRUPT_STATUS_MMCRXIS_Msk     (0x00000001U  << ETH_INTERRUPT_STATUS_MMCRXIS_Pos)\r
-\r
-#define   ETH_INTERRUPT_STATUS_MMCTXIS_Pos     (6U)\r
-#define   ETH_INTERRUPT_STATUS_MMCTXIS_Msk     (0x00000001U  << ETH_INTERRUPT_STATUS_MMCTXIS_Pos)\r
-\r
-#define   ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos   (7U)\r
-#define   ETH_INTERRUPT_STATUS_MMCRXIPIS_Msk   (0x00000001U  << ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos)\r
-\r
-#define   ETH_INTERRUPT_STATUS_Reserved_8_Pos          (8U)\r
-#define   ETH_INTERRUPT_STATUS_Reserved_8_Msk          (0x00000001U  << ETH_INTERRUPT_STATUS_Reserved_8_Pos)\r
-\r
-#define   ETH_INTERRUPT_STATUS_TSIS_Pos        (9U)\r
-#define   ETH_INTERRUPT_STATUS_TSIS_Msk        (0x00000001U  << ETH_INTERRUPT_STATUS_TSIS_Pos)\r
-\r
-#define   ETH_INTERRUPT_STATUS_LPIIS_Pos       (10U)\r
-#define   ETH_INTERRUPT_STATUS_LPIIS_Msk       (0x00000001U  << ETH_INTERRUPT_STATUS_LPIIS_Pos)\r
-\r
-#define   ETH_INTERRUPT_STATUS_Reserved_31_11_Pos      (11U)\r
-#define   ETH_INTERRUPT_STATUS_Reserved_31_11_Msk      (0x001FFFFFU  << ETH_INTERRUPT_STATUS_Reserved_31_11_Pos)\r
-\r
-/* ETH_INTERRUPT_MASK  =  Register 15 [Interrupt Mask Register]*/\r
-#define   ETH_INTERRUPT_MASK_RMIIIM_Pos        (0U)\r
-#define   ETH_INTERRUPT_MASK_RMIIIM_Msk        (0x00000001U  << ETH_INTERRUPT_MASK_RMIIIM_Pos)\r
-\r
-#define   ETH_INTERRUPT_MASK_Reserved_1_Pos    (1U)\r
-#define   ETH_INTERRUPT_MASK_Reserved_1_Msk    (0x00000001U  << ETH_INTERRUPT_MASK_Reserved_1_Pos)\r
-\r
-#define   ETH_INTERRUPT_MASK_Reserved_2_Pos    (2U)\r
-#define   ETH_INTERRUPT_MASK_Reserved_2_Msk    (0x00000001U  << ETH_INTERRUPT_MASK_Reserved_2_Pos)\r
-\r
-#define   ETH_INTERRUPT_MASK_PMTIM_Pos         (3U)\r
-#define   ETH_INTERRUPT_MASK_PMTIM_Msk         (0x00000001U  << ETH_INTERRUPT_MASK_PMTIM_Pos)\r
-\r
-#define   ETH_INTERRUPT_MASK_Reserved_8_4_Pos          (4U)\r
-#define   ETH_INTERRUPT_MASK_Reserved_8_4_Msk          (0x0000001FU  << ETH_INTERRUPT_MASK_Reserved_8_4_Pos)\r
-\r
-#define   ETH_INTERRUPT_MASK_TSIM_Pos          (9U)\r
-#define   ETH_INTERRUPT_MASK_TSIM_Msk          (0x00000001U  << ETH_INTERRUPT_MASK_TSIM_Pos)\r
-\r
-#define   ETH_INTERRUPT_MASK_LPIIM_Pos         (10U)\r
-#define   ETH_INTERRUPT_MASK_LPIIM_Msk         (0x00000001U  << ETH_INTERRUPT_MASK_LPIIM_Pos)\r
-\r
-#define   ETH_INTERRUPT_MASK_Reserved_31_11_Pos        (11U)\r
-#define   ETH_INTERRUPT_MASK_Reserved_31_11_Msk        (0x001FFFFFU  << ETH_INTERRUPT_MASK_Reserved_31_11_Pos)\r
-\r
-/* ETH_MAC_ADDRESS0_HIGH  =  Register 16 [MAC Address0 High Register]*/\r
-#define   ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos     (0U)\r
-#define   ETH_MAC_ADDRESS0_HIGH_ADDRHI_Msk     (0x0000FFFFU  << ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Pos     (16U)\r
-#define   ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Msk     (0x00007FFFU  << ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS0_HIGH_AE_Pos         (31U)\r
-#define   ETH_MAC_ADDRESS0_HIGH_AE_Msk         (0x00000001U  << ETH_MAC_ADDRESS0_HIGH_AE_Pos)\r
-\r
-/* ETH_MAC_ADDRESS0_LOW  =  Register 17 [MAC Address0 Low Register]*/\r
-#define   ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos      (0U)\r
-#define   ETH_MAC_ADDRESS0_LOW_ADDRLO_Msk      (0xFFFFFFFFU  << ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos)\r
-\r
-/* ETH_MAC_ADDRESS1_HIGH  =  Register 18 [MAC Address1 High Register]*/\r
-#define   ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos     (0U)\r
-#define   ETH_MAC_ADDRESS1_HIGH_ADDRHI_Msk     (0x0000FFFFU  << ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Pos     (16U)\r
-#define   ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Msk     (0x000000FFU  << ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS1_HIGH_MBC_Pos        (24U)\r
-#define   ETH_MAC_ADDRESS1_HIGH_MBC_Msk        (0x0000003FU  << ETH_MAC_ADDRESS1_HIGH_MBC_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS1_HIGH_SA_Pos         (30U)\r
-#define   ETH_MAC_ADDRESS1_HIGH_SA_Msk         (0x00000001U  << ETH_MAC_ADDRESS1_HIGH_SA_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS1_HIGH_AE_Pos         (31U)\r
-#define   ETH_MAC_ADDRESS1_HIGH_AE_Msk         (0x00000001U  << ETH_MAC_ADDRESS1_HIGH_AE_Pos)\r
-\r
-/* ETH_MAC_ADDRESS1_LOW  =  Register 19 [MAC Address1 Low Register]*/\r
-#define   ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos      (0U)\r
-#define   ETH_MAC_ADDRESS1_LOW_ADDRLO_Msk      (0xFFFFFFFFU  << ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos)\r
-\r
-/* ETH_MAC_ADDRESS2_HIGH  =  Register 20 [MAC Address2 High Register]*/\r
-#define   ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos     (0U)\r
-#define   ETH_MAC_ADDRESS2_HIGH_ADDRHI_Msk     (0x0000FFFFU  << ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Pos     (16U)\r
-#define   ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Msk     (0x000000FFU  << ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS2_HIGH_MBC_Pos        (24U)\r
-#define   ETH_MAC_ADDRESS2_HIGH_MBC_Msk        (0x0000003FU  << ETH_MAC_ADDRESS2_HIGH_MBC_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS2_HIGH_SA_Pos         (30U)\r
-#define   ETH_MAC_ADDRESS2_HIGH_SA_Msk         (0x00000001U  << ETH_MAC_ADDRESS2_HIGH_SA_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS2_HIGH_AE_Pos         (31U)\r
-#define   ETH_MAC_ADDRESS2_HIGH_AE_Msk         (0x00000001U  << ETH_MAC_ADDRESS2_HIGH_AE_Pos)\r
-\r
-/* ETH_MAC_ADDRESS2_LOW  =  Register 21 [MAC Address2 Low Register]*/\r
-#define   ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos      (0U)\r
-#define   ETH_MAC_ADDRESS2_LOW_ADDRLO_Msk      (0xFFFFFFFFU  << ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos)\r
-\r
-/* ETH_MAC_ADDRESS3_HIGH  =  Register 22 [MAC Address3 High Register]*/\r
-#define   ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos     (0U)\r
-#define   ETH_MAC_ADDRESS3_HIGH_ADDRHI_Msk     (0x0000FFFFU  << ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Pos     (16U)\r
-#define   ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Msk     (0x000000FFU  << ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS3_HIGH_MBC_Pos        (24U)\r
-#define   ETH_MAC_ADDRESS3_HIGH_MBC_Msk        (0x0000003FU  << ETH_MAC_ADDRESS3_HIGH_MBC_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS3_HIGH_SA_Pos         (30U)\r
-#define   ETH_MAC_ADDRESS3_HIGH_SA_Msk         (0x00000001U  << ETH_MAC_ADDRESS3_HIGH_SA_Pos)\r
-\r
-#define   ETH_MAC_ADDRESS3_HIGH_AE_Pos         (31U)\r
-#define   ETH_MAC_ADDRESS3_HIGH_AE_Msk         (0x00000001U  << ETH_MAC_ADDRESS3_HIGH_AE_Pos)\r
-\r
-/* ETH_MAC_ADDRESS3_LOW  =  Register 23 [MAC Address3 Low Register]*/\r
-#define   ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos      (0U)\r
-#define   ETH_MAC_ADDRESS3_LOW_ADDRLO_Msk      (0xFFFFFFFFU  << ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos)\r
-\r
-/* ETH_MMC_CONTROL  =  Register 64 [MMC Control Register]*/\r
-#define   ETH_MMC_CONTROL_CNTRST_Pos   (0U)\r
-#define   ETH_MMC_CONTROL_CNTRST_Msk   (0x00000001U  << ETH_MMC_CONTROL_CNTRST_Pos)\r
-\r
-#define   ETH_MMC_CONTROL_CNTSTOPRO_Pos        (1U)\r
-#define   ETH_MMC_CONTROL_CNTSTOPRO_Msk        (0x00000001U  << ETH_MMC_CONTROL_CNTSTOPRO_Pos)\r
-\r
-#define   ETH_MMC_CONTROL_RSTONRD_Pos          (2U)\r
-#define   ETH_MMC_CONTROL_RSTONRD_Msk          (0x00000001U  << ETH_MMC_CONTROL_RSTONRD_Pos)\r
-\r
-#define   ETH_MMC_CONTROL_CNTFREEZ_Pos         (3U)\r
-#define   ETH_MMC_CONTROL_CNTFREEZ_Msk         (0x00000001U  << ETH_MMC_CONTROL_CNTFREEZ_Pos)\r
-\r
-#define   ETH_MMC_CONTROL_CNTPRST_Pos          (4U)\r
-#define   ETH_MMC_CONTROL_CNTPRST_Msk          (0x00000001U  << ETH_MMC_CONTROL_CNTPRST_Pos)\r
-\r
-#define   ETH_MMC_CONTROL_CNTPRSTLVL_Pos       (5U)\r
-#define   ETH_MMC_CONTROL_CNTPRSTLVL_Msk       (0x00000001U  << ETH_MMC_CONTROL_CNTPRSTLVL_Pos)\r
-\r
-#define   ETH_MMC_CONTROL_Reserved_7_6_Pos     (6U)\r
-#define   ETH_MMC_CONTROL_Reserved_7_6_Msk     (0x00000003U  << ETH_MMC_CONTROL_Reserved_7_6_Pos)\r
-\r
-#define   ETH_MMC_CONTROL_UCDBC_Pos    (8U)\r
-#define   ETH_MMC_CONTROL_UCDBC_Msk    (0x00000001U  << ETH_MMC_CONTROL_UCDBC_Pos)\r
-\r
-#define   ETH_MMC_CONTROL_Reserved_31_9_Pos    (9U)\r
-#define   ETH_MMC_CONTROL_Reserved_31_9_Msk    (0x007FFFFFU  << ETH_MMC_CONTROL_Reserved_31_9_Pos)\r
-\r
-/* ETH_MMC_RECEIVE_INTERRUPT  =  Register 65 [MMC Receive Interrupt Register]*/\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos      (0U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Msk      (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos      (1U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Msk      (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos       (2U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos       (3U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos       (4U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos     (5U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Msk     (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos    (6U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Msk    (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos      (7U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Msk      (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos     (8U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Msk     (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos    (9U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Msk    (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos    (10U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Msk    (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos   (11U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Msk   (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos       (12U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos      (13U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Msk      (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos      (14U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Msk      (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos     (15U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Msk     (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos     (16U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Msk     (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos       (17U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos     (18U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Msk     (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos    (19U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Msk    (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos      (20U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Msk      (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos       (21U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos    (22U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Msk    (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos      (23U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Msk      (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos    (24U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Msk    (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos      (25U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Msk      (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Pos         (26U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Msk         (0x0000003FU  << ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Pos)\r
-\r
-/* ETH_MMC_TRANSMIT_INTERRUPT  =  Register 66 [MMC Transmit Interrupt Register]*/\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos     (0U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Msk     (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos     (1U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Msk     (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos      (2U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Msk      (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos      (3U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Msk      (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos          (4U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Msk          (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos      (5U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Msk      (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos     (6U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Msk     (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos     (7U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Msk     (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos    (8U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Msk    (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos    (9U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Msk    (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos     (10U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Msk     (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos     (11U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Msk     (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos     (12U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Msk     (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos          (13U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Msk          (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos    (14U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Msk    (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos    (15U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Msk    (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos      (16U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Msk      (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos   (17U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Msk   (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos    (18U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Msk    (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos    (19U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Msk    (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos      (20U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Msk      (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos      (21U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Msk      (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos    (22U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Msk    (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos     (23U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Msk     (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos    (24U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Msk    (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos   (25U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Msk   (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Pos        (26U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Msk        (0x0000003FU  << ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Pos)\r
-\r
-/* ETH_MMC_RECEIVE_INTERRUPT_MASK  =  */\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos         (0U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Msk         (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos         (1U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Msk         (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos          (2U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Msk          (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos          (3U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Msk          (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos          (4U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Msk          (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos        (5U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Msk        (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos       (6U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos         (7U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Msk         (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos        (8U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Msk        (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos       (9U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos       (10U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos      (11U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Msk      (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos          (12U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Msk          (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos         (13U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Msk         (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos         (14U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Msk         (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos        (15U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Msk        (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos        (16U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Msk        (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos          (17U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Msk          (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos        (18U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Msk        (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos       (19U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos         (20U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Msk         (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos          (21U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Msk          (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos       (22U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos         (23U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Msk         (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos       (24U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Msk       (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos         (25U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Msk         (0x00000001U  << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos)\r
-\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Pos    (26U)\r
-#define   ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Msk    (0x0000003FU  << ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Pos)\r
-\r
-/* ETH_MMC_TRANSMIT_INTERRUPT_MASK  =  */\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos        (0U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Msk        (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos        (1U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Msk        (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos         (2U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Msk         (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos         (3U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Msk         (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos     (4U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Msk     (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos         (5U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Msk         (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos        (6U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Msk        (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos        (7U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Msk        (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos       (8U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Msk       (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos       (9U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Msk       (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos        (10U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Msk        (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos        (11U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Msk        (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos        (12U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Msk        (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos     (13U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Msk     (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos       (14U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Msk       (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos       (15U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Msk       (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos         (16U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Msk         (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos      (17U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Msk      (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos       (18U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Msk       (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos       (19U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Msk       (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos         (20U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Msk         (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos         (21U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Msk         (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos       (22U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Msk       (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos        (23U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Msk        (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos       (24U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Msk       (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos      (25U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Msk      (0x00000001U  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos)\r
-\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Pos   (26U)\r
-#define   ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Msk   (0x0000003FU  << ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Pos)\r
-\r
-/* ETH_TX_OCTET_COUNT_GOOD_BAD  =  Register 69 [Transmit Octet Count for Good and Bad Frames]*/\r
-#define   ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos      (0U)\r
-#define   ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Msk      (0xFFFFFFFFU  << ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos)\r
-\r
-/* ETH_TX_FRAME_COUNT_GOOD_BAD  =  Register 70 [Transmit Frame Count for Good and Bad Frames]*/\r
-#define   ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos      (0U)\r
-#define   ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Msk      (0xFFFFFFFFU  << ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos)\r
-\r
-/* ETH_TX_BROADCAST_FRAMES_GOOD  =  Register 71 [Transmit Frame Count for Good Broadcast Frames]*/\r
-#define   ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos    (0U)\r
-#define   ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Msk    (0xFFFFFFFFU  << ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos)\r
-\r
-/* ETH_TX_MULTICAST_FRAMES_GOOD  =  Register 72 [Transmit Frame Count for Good Multicast Frames]*/\r
-#define   ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos    (0U)\r
-#define   ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Msk    (0xFFFFFFFFU  << ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos)\r
-\r
-/* ETH_TX_64OCTETS_FRAMES_GOOD_BAD  =  Register 73 [Transmit Octet Count for Good and Bad 64 Byte Frames]*/\r
-#define   ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos        (0U)\r
-#define   ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Msk        (0xFFFFFFFFU  << ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos)\r
-\r
-/* ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD  =  Register 74 [Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames]*/\r
-#define   ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos       (0U)\r
-#define   ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Msk       (0xFFFFFFFFU  << ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos)\r
-\r
-/* ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD  =  Register 75 [Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames]*/\r
-#define   ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos     (0U)\r
-#define   ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Msk     (0xFFFFFFFFU  << ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos)\r
-\r
-/* ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD  =  Register 76 [Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames]*/\r
-#define   ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos     (0U)\r
-#define   ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Msk     (0xFFFFFFFFU  << ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos)\r
-\r
-/* ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD  =  Register 77 [Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames]*/\r
-#define   ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos   (0U)\r
-#define   ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Msk   (0xFFFFFFFFU  << ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos)\r
-\r
-/* ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD  =  Register 78 [Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames]*/\r
-#define   ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos   (0U)\r
-#define   ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Msk   (0xFFFFFFFFU  << ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos)\r
-\r
-/* ETH_TX_UNICAST_FRAMES_GOOD_BAD  =  Register 79 [Transmit Frame Count for Good and Bad Unicast Frames]*/\r
-#define   ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos         (0U)\r
-#define   ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Msk         (0xFFFFFFFFU  << ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos)\r
-\r
-/* ETH_TX_MULTICAST_FRAMES_GOOD_BAD  =  Register 80 [Transmit Frame Count for Good and Bad Multicast Frames]*/\r
-#define   ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos       (0U)\r
-#define   ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Msk       (0xFFFFFFFFU  << ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos)\r
-\r
-/* ETH_TX_BROADCAST_FRAMES_GOOD_BAD  =  Register 81 [Transmit Frame Count for Good and Bad Broadcast Frames]*/\r
-#define   ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos       (0U)\r
-#define   ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Msk       (0xFFFFFFFFU  << ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos)\r
-\r
-/* ETH_TX_UNDERFLOW_ERROR_FRAMES  =  Register 82 [Transmit Frame Count for Underflow Error Frames]*/\r
-#define   ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos          (0U)\r
-#define   ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Msk          (0xFFFFFFFFU  << ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos)\r
-\r
-/* ETH_TX_SINGLE_COLLISION_GOOD_FRAMES  =  Register 83 [Transmit Frame Count for Frames Transmitted after Single Collision]*/\r
-#define   ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos   (0U)\r
-#define   ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Msk   (0xFFFFFFFFU  << ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos)\r
-\r
-/* ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES  =  Register 84 [Transmit Frame Count for Frames Transmitted after Multiple Collision]*/\r
-#define   ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos         (0U)\r
-#define   ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Msk         (0xFFFFFFFFU  << ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos)\r
-\r
-/* ETH_TX_DEFERRED_FRAMES  =  */\r
-#define   ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos   (0U)\r
-#define   ETH_TX_DEFERRED_FRAMES_TXDEFRD_Msk   (0xFFFFFFFFU  << ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos)\r
-\r
-/* ETH_TX_LATE_COLLISION_FRAMES  =  Register 86 [Transmit Frame Count for Late Collision Error Frames]*/\r
-#define   ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos   (0U)\r
-#define   ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Msk   (0xFFFFFFFFU  << ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos)\r
-\r
-/* ETH_TX_EXCESSIVE_COLLISION_FRAMES  =  Register 87 [Transmit Frame Count for Excessive Collision Error Frames]*/\r
-#define   ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos       (0U)\r
-#define   ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Msk       (0xFFFFFFFFU  << ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos)\r
-\r
-/* ETH_TX_CARRIER_ERROR_FRAMES  =  Register 88 [Transmit Frame Count for Carrier Sense Error Frames]*/\r
-#define   ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos       (0U)\r
-#define   ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Msk       (0xFFFFFFFFU  << ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos)\r
-\r
-/* ETH_TX_OCTET_COUNT_GOOD  =  */\r
-#define   ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos   (0U)\r
-#define   ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Msk   (0xFFFFFFFFU  << ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos)\r
-\r
-/* ETH_TX_FRAME_COUNT_GOOD  =  */\r
-#define   ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos   (0U)\r
-#define   ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Msk   (0xFFFFFFFFU  << ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos)\r
-\r
-/* ETH_TX_EXCESSIVE_DEFERRAL_ERROR  =  Register 91 [Transmit Frame Count for Excessive Deferral Error Frames]*/\r
-#define   ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos         (0U)\r
-#define   ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Msk         (0xFFFFFFFFU  << ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos)\r
-\r
-/* ETH_TX_PAUSE_FRAMES  =  Register 92 [Transmit Frame Count for Good PAUSE Frames]*/\r
-#define   ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos      (0U)\r
-#define   ETH_TX_PAUSE_FRAMES_TXPAUSE_Msk      (0xFFFFFFFFU  << ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos)\r
-\r
-/* ETH_TX_VLAN_FRAMES_GOOD  =  Register 93 [Transmit Frame Count for Good VLAN Frames]*/\r
-#define   ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos          (0U)\r
-#define   ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Msk          (0xFFFFFFFFU  << ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos)\r
-\r
-/* ETH_TX_OSIZE_FRAMES_GOOD  =  Register 94 [Transmit Frame Count for Good Oversize Frames]*/\r
-#define   ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos         (0U)\r
-#define   ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Msk         (0xFFFFFFFFU  << ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos)\r
-\r
-/* ETH_RX_FRAMES_COUNT_GOOD_BAD  =  Register 96 [Receive Frame Count for Good and Bad Frames]*/\r
-#define   ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos     (0U)\r
-#define   ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Msk     (0xFFFFFFFFU  << ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos)\r
-\r
-/* ETH_RX_OCTET_COUNT_GOOD_BAD  =  Register 97 [Receive Octet Count for Good and Bad Frames]*/\r
-#define   ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos      (0U)\r
-#define   ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Msk      (0xFFFFFFFFU  << ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos)\r
-\r
-/* ETH_RX_OCTET_COUNT_GOOD  =  */\r
-#define   ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos   (0U)\r
-#define   ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Msk   (0xFFFFFFFFU  << ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos)\r
-\r
-/* ETH_RX_BROADCAST_FRAMES_GOOD  =  Register 99 [Receive Frame Count for Good Broadcast Frames]*/\r
-#define   ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos    (0U)\r
-#define   ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Msk    (0xFFFFFFFFU  << ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos)\r
-\r
-/* ETH_RX_MULTICAST_FRAMES_GOOD  =  Register 100 [Receive Frame Count for Good Multicast Frames]*/\r
-#define   ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos    (0U)\r
-#define   ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Msk    (0xFFFFFFFFU  << ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos)\r
-\r
-/* ETH_RX_CRC_ERROR_FRAMES  =  Register 101 [Receive Frame Count for CRC Error Frames]*/\r
-#define   ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos         (0U)\r
-#define   ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Msk         (0xFFFFFFFFU  << ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos)\r
-\r
-/* ETH_RX_ALIGNMENT_ERROR_FRAMES  =  Register 102 [Receive Frame Count for Alignment Error Frames]*/\r
-#define   ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos          (0U)\r
-#define   ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Msk          (0xFFFFFFFFU  << ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos)\r
-\r
-/* ETH_RX_RUNT_ERROR_FRAMES  =  Register 103 [Receive Frame Count for Runt Error Frames]*/\r
-#define   ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos       (0U)\r
-#define   ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Msk       (0xFFFFFFFFU  << ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos)\r
-\r
-/* ETH_RX_JABBER_ERROR_FRAMES  =  Register 104 [Receive Frame Count for Jabber Error Frames]*/\r
-#define   ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos      (0U)\r
-#define   ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Msk      (0xFFFFFFFFU  << ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos)\r
-\r
-/* ETH_RX_UNDERSIZE_FRAMES_GOOD  =  Register 105 [Receive Frame Count for Undersize Frames]*/\r
-#define   ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos          (0U)\r
-#define   ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Msk          (0xFFFFFFFFU  << ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos)\r
-\r
-/* ETH_RX_OVERSIZE_FRAMES_GOOD  =  */\r
-#define   ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos    (0U)\r
-#define   ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Msk    (0xFFFFFFFFU  << ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos)\r
-\r
-/* ETH_RX_64OCTETS_FRAMES_GOOD_BAD  =  Register 107 [Receive Frame Count for Good and Bad 64 Byte Frames]*/\r
-#define   ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos        (0U)\r
-#define   ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Msk        (0xFFFFFFFFU  << ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos)\r
-\r
-/* ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD  =  Register 108 [Receive Frame Count for Good and Bad 65 to 127 Bytes Frames]*/\r
-#define   ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos       (0U)\r
-#define   ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Msk       (0xFFFFFFFFU  << ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos)\r
-\r
-/* ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD  =  Register 109 [Receive Frame Count for Good and Bad 128 to 255 Bytes Frames]*/\r
-#define   ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos     (0U)\r
-#define   ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Msk     (0xFFFFFFFFU  << ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos)\r
-\r
-/* ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD  =  Register 110 [Receive Frame Count for Good and Bad 256 to 511 Bytes Frames]*/\r
-#define   ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos     (0U)\r
-#define   ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Msk     (0xFFFFFFFFU  << ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos)\r
-\r
-/* ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD  =  Register 111 [Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames]*/\r
-#define   ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos   (0U)\r
-#define   ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Msk   (0xFFFFFFFFU  << ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos)\r
-\r
-/* ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD  =  Register 112 [Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames]*/\r
-#define   ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos   (0U)\r
-#define   ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Msk   (0xFFFFFFFFU  << ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos)\r
-\r
-/* ETH_RX_UNICAST_FRAMES_GOOD  =  Register 113 [Receive Frame Count for Good Unicast Frames]*/\r
-#define   ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos      (0U)\r
-#define   ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Msk      (0xFFFFFFFFU  << ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos)\r
-\r
-/* ETH_RX_LENGTH_ERROR_FRAMES  =  Register 114 [Receive Frame Count for Length Error Frames]*/\r
-#define   ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos      (0U)\r
-#define   ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Msk      (0xFFFFFFFFU  << ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos)\r
-\r
-/* ETH_RX_OUT_OF_RANGE_TYPE_FRAMES  =  Register 115 [Receive Frame Count for Out of Range Frames]*/\r
-#define   ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos       (0U)\r
-#define   ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Msk       (0xFFFFFFFFU  << ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos)\r
-\r
-/* ETH_RX_PAUSE_FRAMES  =  Register 116 [Receive Frame Count for PAUSE Frames]*/\r
-#define   ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos   (0U)\r
-#define   ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Msk   (0xFFFFFFFFU  << ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos)\r
-\r
-/* ETH_RX_FIFO_OVERFLOW_FRAMES  =  Register 117 [Receive Frame Count for FIFO Overflow Frames]*/\r
-#define   ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos   (0U)\r
-#define   ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Msk   (0xFFFFFFFFU  << ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos)\r
-\r
-/* ETH_RX_VLAN_FRAMES_GOOD_BAD  =  Register 118 [Receive Frame Count for Good and Bad VLAN Frames]*/\r
-#define   ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos   (0U)\r
-#define   ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Msk   (0xFFFFFFFFU  << ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos)\r
-\r
-/* ETH_RX_WATCHDOG_ERROR_FRAMES  =  Register 119 [Receive Frame Count for Watchdog Error Frames]*/\r
-#define   ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos    (0U)\r
-#define   ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Msk    (0xFFFFFFFFU  << ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos)\r
-\r
-/* ETH_RX_RECEIVE_ERROR_FRAMES  =  Register 120 [Receive Frame Count for Receive Error Frames]*/\r
-#define   ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos     (0U)\r
-#define   ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Msk     (0xFFFFFFFFU  << ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos)\r
-\r
-/* ETH_RX_CONTROL_FRAMES_GOOD  =  Register 121 [Receive Frame Count for Good Control Frames Frames]*/\r
-#define   ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos       (0U)\r
-#define   ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Msk       (0xFFFFFFFFU  << ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos)\r
-\r
-/* ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK  =  Register 128 [MMC Receive Checksum Offload Interrupt Mask Register]*/\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos    (0U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Msk    (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos          (1U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Msk          (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos        (2U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Msk        (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos         (3U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos        (4U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Msk        (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos    (5U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Msk    (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos          (6U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Msk          (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos        (7U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Msk        (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos     (8U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Msk     (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos    (9U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Msk    (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos     (10U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Msk     (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos    (11U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Msk    (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos    (12U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Msk    (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos   (13U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Msk   (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Pos        (14U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Msk        (0x00000003U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos    (16U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Msk    (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos          (17U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Msk          (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos        (18U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Msk        (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos         (19U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos        (20U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Msk        (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos    (21U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Msk    (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos          (22U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Msk          (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos        (23U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Msk        (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos     (24U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Msk     (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos    (25U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Msk    (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos     (26U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Msk     (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos    (27U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Msk    (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos    (28U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Msk    (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos   (29U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Msk   (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Pos        (30U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Msk        (0x00000003U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Pos)\r
-\r
-/* ETH_MMC_IPC_RECEIVE_INTERRUPT  =  Register 130 [MMC Receive Checksum Offload Interrupt Register]*/\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos         (0U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos       (1U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Msk       (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos     (2U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Msk     (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos      (3U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Msk      (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos     (4U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Msk     (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos         (5U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos       (6U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Msk       (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos     (7U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Msk     (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos          (8U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Msk          (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos         (9U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos          (10U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Msk          (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos         (11U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos         (12U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos        (13U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Msk        (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Pos     (14U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Msk     (0x00000003U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos         (16U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos       (17U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Msk       (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos     (18U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Msk     (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos      (19U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Msk      (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos     (20U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Msk     (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos         (21U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos       (22U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Msk       (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos     (23U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Msk     (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos          (24U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Msk          (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos         (25U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos          (26U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Msk          (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos         (27U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos         (28U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Msk         (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos        (29U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Msk        (0x00000001U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos)\r
-\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Pos     (30U)\r
-#define   ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Msk     (0x00000003U  << ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Pos)\r
-\r
-/* ETH_RXIPV4_GOOD_FRAMES  =  */\r
-#define   ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos       (0U)\r
-#define   ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Msk       (0xFFFFFFFFU  << ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos)\r
-\r
-/* ETH_RXIPV4_HEADER_ERROR_FRAMES  =  Register 133 [Receive IPV4 Header Error Frame Counter Register]*/\r
-#define   ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos   (0U)\r
-#define   ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Msk   (0xFFFFFFFFU  << ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos)\r
-\r
-/* ETH_RXIPV4_NO_PAYLOAD_FRAMES  =  Register 134 [Receive IPV4 No Payload Frame Counter Register]*/\r
-#define   ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos      (0U)\r
-#define   ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Msk      (0xFFFFFFFFU  << ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos)\r
-\r
-/* ETH_RXIPV4_FRAGMENTED_FRAMES  =  Register 135 [Receive IPV4 Fragmented Frame Counter Register]*/\r
-#define   ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos       (0U)\r
-#define   ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Msk       (0xFFFFFFFFU  << ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos)\r
-\r
-/* ETH_RXIPV4_UDPORT_CHECKSUM_DISABLED_FRAMES  =  Register 136 [Receive IPV4 UDP Checksum Disabled Frame Counter Register]*/\r
-#define   ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos   (0U)\r
-#define   ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Msk   (0xFFFFFFFFU  << ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos)\r
-\r
-/* ETH_RXIPV6_GOOD_FRAMES  =  */\r
-#define   ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos       (0U)\r
-#define   ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Msk       (0xFFFFFFFFU  << ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos)\r
-\r
-/* ETH_RXIPV6_HEADER_ERROR_FRAMES  =  Register 138 [Receive IPV6 Header Error Frame Counter Register]*/\r
-#define   ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos   (0U)\r
-#define   ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Msk   (0xFFFFFFFFU  << ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos)\r
-\r
-/* ETH_RXIPV6_NO_PAYLOAD_FRAMES  =  Register 139 [Receive IPV6 No Payload Frame Counter Register]*/\r
-#define   ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos      (0U)\r
-#define   ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Msk      (0xFFFFFFFFU  << ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos)\r
-\r
-/* ETH_RXUDPORT_GOOD_FRAMES  =  */\r
-#define   ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos         (0U)\r
-#define   ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Msk         (0xFFFFFFFFU  << ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos)\r
-\r
-/* ETH_RXUDPORT_ERROR_FRAMES  =  */\r
-#define   ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos       (0U)\r
-#define   ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Msk       (0xFFFFFFFFU  << ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos)\r
-\r
-/* ETH_RXTCPORT_GOOD_FRAMES  =  */\r
-#define   ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos         (0U)\r
-#define   ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Msk         (0xFFFFFFFFU  << ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos)\r
-\r
-/* ETH_RXTCPORT_ERROR_FRAMES  =  */\r
-#define   ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos       (0U)\r
-#define   ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Msk       (0xFFFFFFFFU  << ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos)\r
-\r
-/* ETH_RXICMP_GOOD_FRAMES  =  */\r
-#define   ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos       (0U)\r
-#define   ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Msk       (0xFFFFFFFFU  << ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos)\r
-\r
-/* ETH_RXICMP_ERROR_FRAMES  =  */\r
-#define   ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos     (0U)\r
-#define   ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Msk     (0xFFFFFFFFU  << ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos)\r
-\r
-/* ETH_RXIPV4_GOOD_OCTETS  =  */\r
-#define   ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos       (0U)\r
-#define   ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Msk       (0xFFFFFFFFU  << ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos)\r
-\r
-/* ETH_RXIPV4_HEADER_ERROR_OCTETS  =  Register 149 [Receive IPV4 Header Error Octet Counter Register]*/\r
-#define   ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos   (0U)\r
-#define   ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Msk   (0xFFFFFFFFU  << ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos)\r
-\r
-/* ETH_RXIPV4_NO_PAYLOAD_OCTETS  =  Register 150 [Receive IPV4 No Payload Octet Counter Register]*/\r
-#define   ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos      (0U)\r
-#define   ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Msk      (0xFFFFFFFFU  << ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos)\r
-\r
-/* ETH_RXIPV4_FRAGMENTED_OCTETS  =  Register 151 [Receive IPV4 Fragmented Octet Counter Register]*/\r
-#define   ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos       (0U)\r
-#define   ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Msk       (0xFFFFFFFFU  << ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos)\r
-\r
-/* ETH_RXIPV4_UDPORT_CHECKSUM_DISABLE_OCTETS  =  Register 152 [Receive IPV4 Fragmented Octet Counter Register]*/\r
-#define   ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos    (0U)\r
-#define   ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Msk    (0xFFFFFFFFU  << ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos)\r
-\r
-/* ETH_RXIPV6_GOOD_OCTETS  =  */\r
-#define   ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos       (0U)\r
-#define   ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Msk       (0xFFFFFFFFU  << ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos)\r
-\r
-/* ETH_RXIPV6_HEADER_ERROR_OCTETS  =  Register 154 [Receive IPV6 Header Error Octet Counter Register]*/\r
-#define   ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos   (0U)\r
-#define   ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Msk   (0xFFFFFFFFU  << ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos)\r
-\r
-/* ETH_RXIPV6_NO_PAYLOAD_OCTETS  =  Register 155 [Receive IPV6 No Payload Octet Counter Register]*/\r
-#define   ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos      (0U)\r
-#define   ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Msk      (0xFFFFFFFFU  << ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos)\r
-\r
-/* ETH_RXUDPORT_GOOD_OCTETS  =  */\r
-#define   ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos         (0U)\r
-#define   ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Msk         (0xFFFFFFFFU  << ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos)\r
-\r
-/* ETH_RXUDPORT_ERROR_OCTETS  =  */\r
-#define   ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos       (0U)\r
-#define   ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Msk       (0xFFFFFFFFU  << ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos)\r
-\r
-/* ETH_RXTCPORT_GOOD_OCTETS  =  */\r
-#define   ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos         (0U)\r
-#define   ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Msk         (0xFFFFFFFFU  << ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos)\r
-\r
-/* ETH_RXTCPORT_ERROR_OCTETS  =  */\r
-#define   ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos       (0U)\r
-#define   ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Msk       (0xFFFFFFFFU  << ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos)\r
-\r
-/* ETH_RXICMP_GOOD_OCTETS  =  */\r
-#define   ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos       (0U)\r
-#define   ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Msk       (0xFFFFFFFFU  << ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos)\r
-\r
-/* ETH_RXICMP_ERROR_OCTETS  =  */\r
-#define   ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos     (0U)\r
-#define   ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Msk     (0xFFFFFFFFU  << ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos)\r
-\r
-/* ETH_TIMESTAMP_CONTROL  =  Register 448 [Timestamp Control Register]*/\r
-#define   ETH_TIMESTAMP_CONTROL_TSENA_Pos      (0U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSENA_Msk      (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSENA_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos   (1U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk   (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSINIT_Pos     (2U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSINIT_Msk     (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSINIT_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSUPDT_Pos     (3U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSUPDT_Msk     (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSUPDT_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSTRIG_Pos     (4U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSTRIG_Msk     (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSTRIG_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSADDREG_Pos   (5U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSADDREG_Msk   (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSADDREG_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_Reserved_7_6_Pos       (6U)\r
-#define   ETH_TIMESTAMP_CONTROL_Reserved_7_6_Msk       (0x00000003U  << ETH_TIMESTAMP_CONTROL_Reserved_7_6_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSENALL_Pos    (8U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSENALL_Msk    (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSENALL_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos          (9U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk          (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos          (10U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSVER2ENA_Msk          (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSIPENA_Pos    (11U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSIPENA_Msk    (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSIPENA_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos          (12U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Msk          (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos          (13U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Msk          (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos          (14U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSEVNTENA_Msk          (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos          (15U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSMSTRENA_Msk          (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos         (16U)\r
-#define   ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Msk         (0x00000003U  << ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos        (18U)\r
-#define   ETH_TIMESTAMP_CONTROL_TSENMACADDR_Msk        (0x00000001U  << ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_Reserved_23_19_Pos     (19U)\r
-#define   ETH_TIMESTAMP_CONTROL_Reserved_23_19_Msk     (0x0000001FU  << ETH_TIMESTAMP_CONTROL_Reserved_23_19_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_ATSFC_Pos      (24U)\r
-#define   ETH_TIMESTAMP_CONTROL_ATSFC_Msk      (0x00000001U  << ETH_TIMESTAMP_CONTROL_ATSFC_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_ATSEN0_Pos     (25U)\r
-#define   ETH_TIMESTAMP_CONTROL_ATSEN0_Msk     (0x00000001U  << ETH_TIMESTAMP_CONTROL_ATSEN0_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_ATSEN1_Pos     (26U)\r
-#define   ETH_TIMESTAMP_CONTROL_ATSEN1_Msk     (0x00000001U  << ETH_TIMESTAMP_CONTROL_ATSEN1_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_ATSEN2_Pos     (27U)\r
-#define   ETH_TIMESTAMP_CONTROL_ATSEN2_Msk     (0x00000001U  << ETH_TIMESTAMP_CONTROL_ATSEN2_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_ATSEN3_Pos     (28U)\r
-#define   ETH_TIMESTAMP_CONTROL_ATSEN3_Msk     (0x00000001U  << ETH_TIMESTAMP_CONTROL_ATSEN3_Pos)\r
-\r
-#define   ETH_TIMESTAMP_CONTROL_Reserved_31_29_Pos     (29U)\r
-#define   ETH_TIMESTAMP_CONTROL_Reserved_31_29_Msk     (0x00000007U  << ETH_TIMESTAMP_CONTROL_Reserved_31_29_Pos)\r
-\r
-/* ETH_SUB_SECOND_INCREMENT  =  Register 449 [Sub-Second Increment Register]*/\r
-#define   ETH_SUB_SECOND_INCREMENT_SSINC_Pos   (0U)\r
-#define   ETH_SUB_SECOND_INCREMENT_SSINC_Msk   (0x000000FFU  << ETH_SUB_SECOND_INCREMENT_SSINC_Pos)\r
-\r
-#define   ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Pos   (8U)\r
-#define   ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Msk   (0x00FFFFFFU  << ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Pos)\r
-\r
-/* ETH_SYSTEM_TIME_SECONDS  =  Register 450 [System Time - Seconds Register]*/\r
-#define   ETH_SYSTEM_TIME_SECONDS_TSS_Pos      (0U)\r
-#define   ETH_SYSTEM_TIME_SECONDS_TSS_Msk      (0xFFFFFFFFU  << ETH_SYSTEM_TIME_SECONDS_TSS_Pos)\r
-\r
-/* ETH_SYSTEM_TIME_NANOSECONDS  =  */\r
-#define   ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos         (0U)\r
-#define   ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Msk         (0x7FFFFFFFU  << ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos)\r
-\r
-#define   ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Pos          (31U)\r
-#define   ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Msk          (0x00000001U  << ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Pos)\r
-\r
-/* ETH_SYSTEM_TIME_SECONDS_UPDATE  =  Register 452 [System Time - Seconds Update Register]*/\r
-#define   ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos       (0U)\r
-#define   ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Msk       (0xFFFFFFFFU  << ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos)\r
-\r
-/* ETH_SYSTEM_TIME_NANOSECONDS_UPDATE  =  */\r
-#define   ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos          (0U)\r
-#define   ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Msk          (0x7FFFFFFFU  << ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos)\r
-\r
-#define   ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos        (31U)\r
-#define   ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk        (0x00000001U  << ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos)\r
-\r
-/* ETH_TIMESTAMP_ADDEND  =  Register 454 [Timestamp Addend Register]*/\r
-#define   ETH_TIMESTAMP_ADDEND_TSAR_Pos        (0U)\r
-#define   ETH_TIMESTAMP_ADDEND_TSAR_Msk        (0xFFFFFFFFU  << ETH_TIMESTAMP_ADDEND_TSAR_Pos)\r
-\r
-/* ETH_TARGET_TIME_SECONDS  =  Register 455 [Target Time Seconds Register]*/\r
-#define   ETH_TARGET_TIME_SECONDS_TSTR_Pos     (0U)\r
-#define   ETH_TARGET_TIME_SECONDS_TSTR_Msk     (0xFFFFFFFFU  << ETH_TARGET_TIME_SECONDS_TSTR_Pos)\r
-\r
-/* ETH_TARGET_TIME_NANOSECONDS  =  */\r
-#define   ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos        (0U)\r
-#define   ETH_TARGET_TIME_NANOSECONDS_TTSLO_Msk        (0x7FFFFFFFU  << ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos)\r
-\r
-#define   ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos     (31U)\r
-#define   ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Msk     (0x00000001U  << ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos)\r
-\r
-/* ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS  =  Register 457 [System Time - Higher Word Seconds Register]*/\r
-#define   ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos        (0U)\r
-#define   ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Msk        (0x0000FFFFU  << ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos)\r
-\r
-#define   ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Pos       (16U)\r
-#define   ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Msk       (0x0000FFFFU  << ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Pos)\r
-\r
-/* ETH_TIMESTAMP_STATUS  =  Register 458 [Timestamp Status Register]*/\r
-#define   ETH_TIMESTAMP_STATUS_TSSOVF_Pos      (0U)\r
-#define   ETH_TIMESTAMP_STATUS_TSSOVF_Msk      (0x00000001U  << ETH_TIMESTAMP_STATUS_TSSOVF_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_TSTARGT_Pos     (1U)\r
-#define   ETH_TIMESTAMP_STATUS_TSTARGT_Msk     (0x00000001U  << ETH_TIMESTAMP_STATUS_TSTARGT_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_AUXTSTRIG_Pos   (2U)\r
-#define   ETH_TIMESTAMP_STATUS_AUXTSTRIG_Msk   (0x00000001U  << ETH_TIMESTAMP_STATUS_AUXTSTRIG_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos   (3U)\r
-#define   ETH_TIMESTAMP_STATUS_TSTRGTERR_Msk   (0x00000001U  << ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_TSTARGT1_Pos    (4U)\r
-#define   ETH_TIMESTAMP_STATUS_TSTARGT1_Msk    (0x00000001U  << ETH_TIMESTAMP_STATUS_TSTARGT1_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos          (5U)\r
-#define   ETH_TIMESTAMP_STATUS_TSTRGTERR1_Msk          (0x00000001U  << ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_TSTARGT2_Pos    (6U)\r
-#define   ETH_TIMESTAMP_STATUS_TSTARGT2_Msk    (0x00000001U  << ETH_TIMESTAMP_STATUS_TSTARGT2_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos          (7U)\r
-#define   ETH_TIMESTAMP_STATUS_TSTRGTERR2_Msk          (0x00000001U  << ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_TSTARGT3_Pos    (8U)\r
-#define   ETH_TIMESTAMP_STATUS_TSTARGT3_Msk    (0x00000001U  << ETH_TIMESTAMP_STATUS_TSTARGT3_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos          (9U)\r
-#define   ETH_TIMESTAMP_STATUS_TSTRGTERR3_Msk          (0x00000001U  << ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_Reserved_15_10_Pos      (10U)\r
-#define   ETH_TIMESTAMP_STATUS_Reserved_15_10_Msk      (0x0000003FU  << ETH_TIMESTAMP_STATUS_Reserved_15_10_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_ATSSTN_Pos      (16U)\r
-#define   ETH_TIMESTAMP_STATUS_ATSSTN_Msk      (0x0000000FU  << ETH_TIMESTAMP_STATUS_ATSSTN_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_Reserved_23_20_Pos      (20U)\r
-#define   ETH_TIMESTAMP_STATUS_Reserved_23_20_Msk      (0x0000000FU  << ETH_TIMESTAMP_STATUS_Reserved_23_20_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_ATSSTM_Pos      (24U)\r
-#define   ETH_TIMESTAMP_STATUS_ATSSTM_Msk      (0x00000001U  << ETH_TIMESTAMP_STATUS_ATSSTM_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_ATSNS_Pos       (25U)\r
-#define   ETH_TIMESTAMP_STATUS_ATSNS_Msk       (0x0000001FU  << ETH_TIMESTAMP_STATUS_ATSNS_Pos)\r
-\r
-#define   ETH_TIMESTAMP_STATUS_Reserved_31_30_Pos      (30U)\r
-#define   ETH_TIMESTAMP_STATUS_Reserved_31_30_Msk      (0x00000003U  << ETH_TIMESTAMP_STATUS_Reserved_31_30_Pos)\r
-\r
-/* ETH_PPS_CONTROL  =  Register 459 [PPS Control Register]*/\r
-#define   ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos   (0U)\r
-#define   ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Msk   (0x0000000FU  << ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_PPSEN0_Pos   (4U)\r
-#define   ETH_PPS_CONTROL_PPSEN0_Msk   (0x00000001U  << ETH_PPS_CONTROL_PPSEN0_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_TRGTMODSEL0_Pos      (5U)\r
-#define   ETH_PPS_CONTROL_TRGTMODSEL0_Msk      (0x00000003U  << ETH_PPS_CONTROL_TRGTMODSEL0_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_Reserved_7_Pos       (7U)\r
-#define   ETH_PPS_CONTROL_Reserved_7_Msk       (0x00000001U  << ETH_PPS_CONTROL_Reserved_7_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_PPSCMD1_Pos          (8U)\r
-#define   ETH_PPS_CONTROL_PPSCMD1_Msk          (0x00000007U  << ETH_PPS_CONTROL_PPSCMD1_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_Reserved_12_11_Pos   (11U)\r
-#define   ETH_PPS_CONTROL_Reserved_12_11_Msk   (0x00000003U  << ETH_PPS_CONTROL_Reserved_12_11_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_TRGTMODSEL1_Pos      (13U)\r
-#define   ETH_PPS_CONTROL_TRGTMODSEL1_Msk      (0x00000003U  << ETH_PPS_CONTROL_TRGTMODSEL1_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_Reserved_15_Pos      (15U)\r
-#define   ETH_PPS_CONTROL_Reserved_15_Msk      (0x00000001U  << ETH_PPS_CONTROL_Reserved_15_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_PPSCMD2_Pos          (16U)\r
-#define   ETH_PPS_CONTROL_PPSCMD2_Msk          (0x00000007U  << ETH_PPS_CONTROL_PPSCMD2_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_Reserved_20_19_Pos   (19U)\r
-#define   ETH_PPS_CONTROL_Reserved_20_19_Msk   (0x00000003U  << ETH_PPS_CONTROL_Reserved_20_19_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_TRGTMODSEL2_Pos      (21U)\r
-#define   ETH_PPS_CONTROL_TRGTMODSEL2_Msk      (0x00000003U  << ETH_PPS_CONTROL_TRGTMODSEL2_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_Reserved_23_Pos      (23U)\r
-#define   ETH_PPS_CONTROL_Reserved_23_Msk      (0x00000001U  << ETH_PPS_CONTROL_Reserved_23_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_PPSCMD3_Pos          (24U)\r
-#define   ETH_PPS_CONTROL_PPSCMD3_Msk          (0x00000007U  << ETH_PPS_CONTROL_PPSCMD3_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_Reserved_28_27_Pos   (27U)\r
-#define   ETH_PPS_CONTROL_Reserved_28_27_Msk   (0x00000003U  << ETH_PPS_CONTROL_Reserved_28_27_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_TRGTMODSEL3_Pos      (29U)\r
-#define   ETH_PPS_CONTROL_TRGTMODSEL3_Msk      (0x00000003U  << ETH_PPS_CONTROL_TRGTMODSEL3_Pos)\r
-\r
-#define   ETH_PPS_CONTROL_Reserved_31_Pos      (31U)\r
-#define   ETH_PPS_CONTROL_Reserved_31_Msk      (0x00000001U  << ETH_PPS_CONTROL_Reserved_31_Pos)\r
-\r
-/* ETH_BUS_MODE  =  Register x [Bus Mode Register]*/\r
-#define   ETH_BUS_MODE_SWR_Pos         (0U)\r
-#define   ETH_BUS_MODE_SWR_Msk         (0x00000001U  << ETH_BUS_MODE_SWR_Pos)\r
-\r
-#define   ETH_BUS_MODE_DA_Pos          (1U)\r
-#define   ETH_BUS_MODE_DA_Msk          (0x00000001U  << ETH_BUS_MODE_DA_Pos)\r
-\r
-#define   ETH_BUS_MODE_DSL_Pos         (2U)\r
-#define   ETH_BUS_MODE_DSL_Msk         (0x0000001FU  << ETH_BUS_MODE_DSL_Pos)\r
-\r
-#define   ETH_BUS_MODE_Reserved_7_Pos          (7U)\r
-#define   ETH_BUS_MODE_Reserved_7_Msk          (0x00000001U  << ETH_BUS_MODE_Reserved_7_Pos)\r
-\r
-#define   ETH_BUS_MODE_PBL_Pos         (8U)\r
-#define   ETH_BUS_MODE_PBL_Msk         (0x0000003FU  << ETH_BUS_MODE_PBL_Pos)\r
-\r
-#define   ETH_BUS_MODE_PR_Pos          (14U)\r
-#define   ETH_BUS_MODE_PR_Msk          (0x00000003U  << ETH_BUS_MODE_PR_Pos)\r
-\r
-#define   ETH_BUS_MODE_FB_Pos          (16U)\r
-#define   ETH_BUS_MODE_FB_Msk          (0x00000001U  << ETH_BUS_MODE_FB_Pos)\r
-\r
-#define   ETH_BUS_MODE_RPBL_Pos        (17U)\r
-#define   ETH_BUS_MODE_RPBL_Msk        (0x0000003FU  << ETH_BUS_MODE_RPBL_Pos)\r
-\r
-#define   ETH_BUS_MODE_USP_Pos         (23U)\r
-#define   ETH_BUS_MODE_USP_Msk         (0x00000001U  << ETH_BUS_MODE_USP_Pos)\r
-\r
-#define   ETH_BUS_MODE_EIGHTxPBL_Pos   (24U)\r
-#define   ETH_BUS_MODE_EIGHTxPBL_Msk   (0x00000001U  << ETH_BUS_MODE_EIGHTxPBL_Pos)\r
-\r
-#define   ETH_BUS_MODE_AAL_Pos         (25U)\r
-#define   ETH_BUS_MODE_AAL_Msk         (0x00000001U  << ETH_BUS_MODE_AAL_Pos)\r
-\r
-#define   ETH_BUS_MODE_MB_Pos          (26U)\r
-#define   ETH_BUS_MODE_MB_Msk          (0x00000001U  << ETH_BUS_MODE_MB_Pos)\r
-\r
-#define   ETH_BUS_MODE_TXPR_Pos        (27U)\r
-#define   ETH_BUS_MODE_TXPR_Msk        (0x00000001U  << ETH_BUS_MODE_TXPR_Pos)\r
-\r
-#define   ETH_BUS_MODE_PRWG_Pos        (28U)\r
-#define   ETH_BUS_MODE_PRWG_Msk        (0x00000003U  << ETH_BUS_MODE_PRWG_Pos)\r
-\r
-#define   ETH_BUS_MODE_Reserved_31_30_Pos      (30U)\r
-#define   ETH_BUS_MODE_Reserved_31_30_Msk      (0x00000003U  << ETH_BUS_MODE_Reserved_31_30_Pos)\r
-\r
-/* ETH_TRANSMIT_POLL_DEMAND  =  Register 1 [Transmit Poll Demand Register]*/\r
-#define   ETH_TRANSMIT_POLL_DEMAND_TPD_Pos     (0U)\r
-#define   ETH_TRANSMIT_POLL_DEMAND_TPD_Msk     (0xFFFFFFFFU  << ETH_TRANSMIT_POLL_DEMAND_TPD_Pos)\r
-\r
-/* ETH_RECEIVE_POLL_DEMAND  =  */\r
-#define   ETH_RECEIVE_POLL_DEMAND_RPD_Pos      (0U)\r
-#define   ETH_RECEIVE_POLL_DEMAND_RPD_Msk      (0xFFFFFFFFU  << ETH_RECEIVE_POLL_DEMAND_RPD_Pos)\r
-\r
-/* ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS  =  */\r
-#define   ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos         (0U)\r
-#define   ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Msk         (0x00000003U  << ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos)\r
-\r
-#define   ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos         (2U)\r
-#define   ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Msk         (0x3FFFFFFFU  << ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos)\r
-\r
-/* ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS  =  */\r
-#define   ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos        (0U)\r
-#define   ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Msk        (0x00000003U  << ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos)\r
-\r
-#define   ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos        (2U)\r
-#define   ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Msk        (0x3FFFFFFFU  << ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos)\r
-\r
-/* ETH_STATUS  =  */\r
-#define   ETH_STATUS_TI_Pos    (0U)\r
-#define   ETH_STATUS_TI_Msk    (0x00000001U  << ETH_STATUS_TI_Pos)\r
-\r
-#define   ETH_STATUS_TPS_Pos   (1U)\r
-#define   ETH_STATUS_TPS_Msk   (0x00000001U  << ETH_STATUS_TPS_Pos)\r
-\r
-#define   ETH_STATUS_TU_Pos    (2U)\r
-#define   ETH_STATUS_TU_Msk    (0x00000001U  << ETH_STATUS_TU_Pos)\r
-\r
-#define   ETH_STATUS_TJT_Pos   (3U)\r
-#define   ETH_STATUS_TJT_Msk   (0x00000001U  << ETH_STATUS_TJT_Pos)\r
-\r
-#define   ETH_STATUS_OVF_Pos   (4U)\r
-#define   ETH_STATUS_OVF_Msk   (0x00000001U  << ETH_STATUS_OVF_Pos)\r
-\r
-#define   ETH_STATUS_UNF_Pos   (5U)\r
-#define   ETH_STATUS_UNF_Msk   (0x00000001U  << ETH_STATUS_UNF_Pos)\r
-\r
-#define   ETH_STATUS_RI_Pos    (6U)\r
-#define   ETH_STATUS_RI_Msk    (0x00000001U  << ETH_STATUS_RI_Pos)\r
-\r
-#define   ETH_STATUS_RU_Pos    (7U)\r
-#define   ETH_STATUS_RU_Msk    (0x00000001U  << ETH_STATUS_RU_Pos)\r
-\r
-#define   ETH_STATUS_RPS_Pos   (8U)\r
-#define   ETH_STATUS_RPS_Msk   (0x00000001U  << ETH_STATUS_RPS_Pos)\r
-\r
-#define   ETH_STATUS_RWT_Pos   (9U)\r
-#define   ETH_STATUS_RWT_Msk   (0x00000001U  << ETH_STATUS_RWT_Pos)\r
-\r
-#define   ETH_STATUS_ETI_Pos   (10U)\r
-#define   ETH_STATUS_ETI_Msk   (0x00000001U  << ETH_STATUS_ETI_Pos)\r
-\r
-#define   ETH_STATUS_Reserved_12_11_Pos        (11U)\r
-#define   ETH_STATUS_Reserved_12_11_Msk        (0x00000003U  << ETH_STATUS_Reserved_12_11_Pos)\r
-\r
-#define   ETH_STATUS_FBI_Pos   (13U)\r
-#define   ETH_STATUS_FBI_Msk   (0x00000001U  << ETH_STATUS_FBI_Pos)\r
-\r
-#define   ETH_STATUS_ERI_Pos   (14U)\r
-#define   ETH_STATUS_ERI_Msk   (0x00000001U  << ETH_STATUS_ERI_Pos)\r
-\r
-#define   ETH_STATUS_AIS_Pos   (15U)\r
-#define   ETH_STATUS_AIS_Msk   (0x00000001U  << ETH_STATUS_AIS_Pos)\r
-\r
-#define   ETH_STATUS_NIS_Pos   (16U)\r
-#define   ETH_STATUS_NIS_Msk   (0x00000001U  << ETH_STATUS_NIS_Pos)\r
-\r
-#define   ETH_STATUS_RS_Pos    (17U)\r
-#define   ETH_STATUS_RS_Msk    (0x00000007U  << ETH_STATUS_RS_Pos)\r
-\r
-#define   ETH_STATUS_TS_Pos    (20U)\r
-#define   ETH_STATUS_TS_Msk    (0x00000007U  << ETH_STATUS_TS_Pos)\r
-\r
-#define   ETH_STATUS_EB_Pos    (23U)\r
-#define   ETH_STATUS_EB_Msk    (0x00000007U  << ETH_STATUS_EB_Pos)\r
-\r
-#define   ETH_STATUS_MLI_Pos   (26U)\r
-#define   ETH_STATUS_MLI_Msk   (0x00000001U  << ETH_STATUS_MLI_Pos)\r
-\r
-#define   ETH_STATUS_EMI_Pos   (27U)\r
-#define   ETH_STATUS_EMI_Msk   (0x00000001U  << ETH_STATUS_EMI_Pos)\r
-\r
-#define   ETH_STATUS_EPI_Pos   (28U)\r
-#define   ETH_STATUS_EPI_Msk   (0x00000001U  << ETH_STATUS_EPI_Pos)\r
-\r
-#define   ETH_STATUS_TTI_Pos   (29U)\r
-#define   ETH_STATUS_TTI_Msk   (0x00000001U  << ETH_STATUS_TTI_Pos)\r
-\r
-#define   ETH_STATUS_ELPII_Pos         (30U)\r
-#define   ETH_STATUS_ELPII_Msk         (0x00000001U  << ETH_STATUS_ELPII_Pos)\r
-\r
-#define   ETH_STATUS_Reserved_31_Pos   (31U)\r
-#define   ETH_STATUS_Reserved_31_Msk   (0x00000001U  << ETH_STATUS_Reserved_31_Pos)\r
-\r
-/* ETH_OPERATION_MODE  =  Register 6 [Operation Mode Register]*/\r
-#define   ETH_OPERATION_MODE_Reserved_0_Pos    (0U)\r
-#define   ETH_OPERATION_MODE_Reserved_0_Msk    (0x00000001U  << ETH_OPERATION_MODE_Reserved_0_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_SR_Pos    (1U)\r
-#define   ETH_OPERATION_MODE_SR_Msk    (0x00000001U  << ETH_OPERATION_MODE_SR_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_OSF_Pos   (2U)\r
-#define   ETH_OPERATION_MODE_OSF_Msk   (0x00000001U  << ETH_OPERATION_MODE_OSF_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_RTC_Pos   (3U)\r
-#define   ETH_OPERATION_MODE_RTC_Msk   (0x00000003U  << ETH_OPERATION_MODE_RTC_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_Reserved_5_Pos    (5U)\r
-#define   ETH_OPERATION_MODE_Reserved_5_Msk    (0x00000001U  << ETH_OPERATION_MODE_Reserved_5_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_FUF_Pos   (6U)\r
-#define   ETH_OPERATION_MODE_FUF_Msk   (0x00000001U  << ETH_OPERATION_MODE_FUF_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_FEF_Pos   (7U)\r
-#define   ETH_OPERATION_MODE_FEF_Msk   (0x00000001U  << ETH_OPERATION_MODE_FEF_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_EFC_Pos   (8U)\r
-#define   ETH_OPERATION_MODE_EFC_Msk   (0x00000001U  << ETH_OPERATION_MODE_EFC_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_RFA_Pos   (9U)\r
-#define   ETH_OPERATION_MODE_RFA_Msk   (0x00000003U  << ETH_OPERATION_MODE_RFA_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_RFD_Pos   (11U)\r
-#define   ETH_OPERATION_MODE_RFD_Msk   (0x00000003U  << ETH_OPERATION_MODE_RFD_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_ST_Pos    (13U)\r
-#define   ETH_OPERATION_MODE_ST_Msk    (0x00000001U  << ETH_OPERATION_MODE_ST_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_TTC_Pos   (14U)\r
-#define   ETH_OPERATION_MODE_TTC_Msk   (0x00000007U  << ETH_OPERATION_MODE_TTC_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_Reserved_19_17_Pos        (17U)\r
-#define   ETH_OPERATION_MODE_Reserved_19_17_Msk        (0x00000007U  << ETH_OPERATION_MODE_Reserved_19_17_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_FTF_Pos   (20U)\r
-#define   ETH_OPERATION_MODE_FTF_Msk   (0x00000001U  << ETH_OPERATION_MODE_FTF_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_TSF_Pos   (21U)\r
-#define   ETH_OPERATION_MODE_TSF_Msk   (0x00000001U  << ETH_OPERATION_MODE_TSF_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_RFD2_Pos          (22U)\r
-#define   ETH_OPERATION_MODE_RFD2_Msk          (0x00000001U  << ETH_OPERATION_MODE_RFD2_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_RFA2_Pos          (23U)\r
-#define   ETH_OPERATION_MODE_RFA2_Msk          (0x00000001U  << ETH_OPERATION_MODE_RFA2_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_DFF_Pos   (24U)\r
-#define   ETH_OPERATION_MODE_DFF_Msk   (0x00000001U  << ETH_OPERATION_MODE_DFF_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_RSF_Pos   (25U)\r
-#define   ETH_OPERATION_MODE_RSF_Msk   (0x00000001U  << ETH_OPERATION_MODE_RSF_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_DT_Pos    (26U)\r
-#define   ETH_OPERATION_MODE_DT_Msk    (0x00000001U  << ETH_OPERATION_MODE_DT_Pos)\r
-\r
-#define   ETH_OPERATION_MODE_Reserved_31_27_Pos        (27U)\r
-#define   ETH_OPERATION_MODE_Reserved_31_27_Msk        (0x0000001FU  << ETH_OPERATION_MODE_Reserved_31_27_Pos)\r
-\r
-/* ETH_INTERRUPT_ENABLE  =  Register 7 [Interrupt Enable Register]*/\r
-#define   ETH_INTERRUPT_ENABLE_TIE_Pos         (0U)\r
-#define   ETH_INTERRUPT_ENABLE_TIE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_TIE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_TSE_Pos         (1U)\r
-#define   ETH_INTERRUPT_ENABLE_TSE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_TSE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_TUE_Pos         (2U)\r
-#define   ETH_INTERRUPT_ENABLE_TUE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_TUE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_TJE_Pos         (3U)\r
-#define   ETH_INTERRUPT_ENABLE_TJE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_TJE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_OVE_Pos         (4U)\r
-#define   ETH_INTERRUPT_ENABLE_OVE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_OVE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_UNE_Pos         (5U)\r
-#define   ETH_INTERRUPT_ENABLE_UNE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_UNE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_RIE_Pos         (6U)\r
-#define   ETH_INTERRUPT_ENABLE_RIE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_RIE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_RUE_Pos         (7U)\r
-#define   ETH_INTERRUPT_ENABLE_RUE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_RUE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_RSE_Pos         (8U)\r
-#define   ETH_INTERRUPT_ENABLE_RSE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_RSE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_RWE_Pos         (9U)\r
-#define   ETH_INTERRUPT_ENABLE_RWE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_RWE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_ETE_Pos         (10U)\r
-#define   ETH_INTERRUPT_ENABLE_ETE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_ETE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_Reserved_12_11_Pos      (11U)\r
-#define   ETH_INTERRUPT_ENABLE_Reserved_12_11_Msk      (0x00000003U  << ETH_INTERRUPT_ENABLE_Reserved_12_11_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_FBE_Pos         (13U)\r
-#define   ETH_INTERRUPT_ENABLE_FBE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_FBE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_ERE_Pos         (14U)\r
-#define   ETH_INTERRUPT_ENABLE_ERE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_ERE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_AIE_Pos         (15U)\r
-#define   ETH_INTERRUPT_ENABLE_AIE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_AIE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_NIE_Pos         (16U)\r
-#define   ETH_INTERRUPT_ENABLE_NIE_Msk         (0x00000001U  << ETH_INTERRUPT_ENABLE_NIE_Pos)\r
-\r
-#define   ETH_INTERRUPT_ENABLE_Reserved_31_17_Pos      (17U)\r
-#define   ETH_INTERRUPT_ENABLE_Reserved_31_17_Msk      (0x00007FFFU  << ETH_INTERRUPT_ENABLE_Reserved_31_17_Pos)\r
-\r
-/* ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER  =  */\r
-#define   ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos   (0U)\r
-#define   ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Msk   (0x0000FFFFU  << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos)\r
-\r
-#define   ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos   (16U)\r
-#define   ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Msk   (0x00000001U  << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos)\r
-\r
-#define   ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos   (17U)\r
-#define   ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Msk   (0x000007FFU  << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos)\r
-\r
-#define   ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos   (28U)\r
-#define   ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Msk   (0x00000001U  << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos)\r
-\r
-#define   ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Pos      (29U)\r
-#define   ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Msk      (0x00000007U  << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Pos)\r
-\r
-/* ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER  =  */\r
-#define   ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos        (0U)\r
-#define   ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Msk        (0x000000FFU  << ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos)\r
-\r
-#define   ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Pos       (8U)\r
-#define   ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Msk       (0x00FFFFFFU  << ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Pos)\r
-\r
-/* ETH_AHB_STATUS  =  Register 11 [AHB Status Register]*/\r
-#define   ETH_AHB_STATUS_AHBMS_Pos     (0U)\r
-#define   ETH_AHB_STATUS_AHBMS_Msk     (0x00000001U  << ETH_AHB_STATUS_AHBMS_Pos)\r
-\r
-#define   ETH_AHB_STATUS_Reserved_1_Pos        (1U)\r
-#define   ETH_AHB_STATUS_Reserved_1_Msk        (0x00000001U  << ETH_AHB_STATUS_Reserved_1_Pos)\r
-\r
-#define   ETH_AHB_STATUS_Reserved_31_2_Pos     (2U)\r
-#define   ETH_AHB_STATUS_Reserved_31_2_Msk     (0x3FFFFFFFU  << ETH_AHB_STATUS_Reserved_31_2_Pos)\r
-\r
-/* ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR  =  */\r
-#define   ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos         (0U)\r
-#define   ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Msk         (0xFFFFFFFFU  << ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos)\r
-\r
-/* ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR  =  */\r
-#define   ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos          (0U)\r
-#define   ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Msk          (0xFFFFFFFFU  << ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos)\r
-\r
-/* ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS  =  Register 20 [Current Host Transmit Buffer Address Register]*/\r
-#define   ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos     (0U)\r
-#define   ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Msk     (0xFFFFFFFFU  << ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos)\r
-\r
-/* ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS  =  Register 21 [Current Host Receive Buffer Address Register]*/\r
-#define   ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos      (0U)\r
-#define   ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Msk      (0xFFFFFFFFU  << ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos)\r
-\r
-/* ETH_HW_FEATURE  =  Register 22 [HW Feature Register]*/\r
-#define   ETH_HW_FEATURE_MIISEL_Pos    (0U)\r
-#define   ETH_HW_FEATURE_MIISEL_Msk    (0x00000001U  << ETH_HW_FEATURE_MIISEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_GMIISEL_Pos   (1U)\r
-#define   ETH_HW_FEATURE_GMIISEL_Msk   (0x00000001U  << ETH_HW_FEATURE_GMIISEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_HDSEL_Pos     (2U)\r
-#define   ETH_HW_FEATURE_HDSEL_Msk     (0x00000001U  << ETH_HW_FEATURE_HDSEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_EXTHASHEN_Pos         (3U)\r
-#define   ETH_HW_FEATURE_EXTHASHEN_Msk         (0x00000001U  << ETH_HW_FEATURE_EXTHASHEN_Pos)\r
-\r
-#define   ETH_HW_FEATURE_HASHSEL_Pos   (4U)\r
-#define   ETH_HW_FEATURE_HASHSEL_Msk   (0x00000001U  << ETH_HW_FEATURE_HASHSEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_ADDMACADRSEL_Pos      (5U)\r
-#define   ETH_HW_FEATURE_ADDMACADRSEL_Msk      (0x00000001U  << ETH_HW_FEATURE_ADDMACADRSEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_PCSSEL_Pos    (6U)\r
-#define   ETH_HW_FEATURE_PCSSEL_Msk    (0x00000001U  << ETH_HW_FEATURE_PCSSEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_L3L4FLTREN_Pos        (7U)\r
-#define   ETH_HW_FEATURE_L3L4FLTREN_Msk        (0x00000001U  << ETH_HW_FEATURE_L3L4FLTREN_Pos)\r
-\r
-#define   ETH_HW_FEATURE_SMASEL_Pos    (8U)\r
-#define   ETH_HW_FEATURE_SMASEL_Msk    (0x00000001U  << ETH_HW_FEATURE_SMASEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_RWKSEL_Pos    (9U)\r
-#define   ETH_HW_FEATURE_RWKSEL_Msk    (0x00000001U  << ETH_HW_FEATURE_RWKSEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_MGKSEL_Pos    (10U)\r
-#define   ETH_HW_FEATURE_MGKSEL_Msk    (0x00000001U  << ETH_HW_FEATURE_MGKSEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_MMCSEL_Pos    (11U)\r
-#define   ETH_HW_FEATURE_MMCSEL_Msk    (0x00000001U  << ETH_HW_FEATURE_MMCSEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_TSVER1SEL_Pos         (12U)\r
-#define   ETH_HW_FEATURE_TSVER1SEL_Msk         (0x00000001U  << ETH_HW_FEATURE_TSVER1SEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_TSVER2SEL_Pos         (13U)\r
-#define   ETH_HW_FEATURE_TSVER2SEL_Msk         (0x00000001U  << ETH_HW_FEATURE_TSVER2SEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_EEESEL_Pos    (14U)\r
-#define   ETH_HW_FEATURE_EEESEL_Msk    (0x00000001U  << ETH_HW_FEATURE_EEESEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_AVSEL_Pos     (15U)\r
-#define   ETH_HW_FEATURE_AVSEL_Msk     (0x00000001U  << ETH_HW_FEATURE_AVSEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_TXCOESEL_Pos          (16U)\r
-#define   ETH_HW_FEATURE_TXCOESEL_Msk          (0x00000001U  << ETH_HW_FEATURE_TXCOESEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_RXTYP1COE_Pos         (17U)\r
-#define   ETH_HW_FEATURE_RXTYP1COE_Msk         (0x00000001U  << ETH_HW_FEATURE_RXTYP1COE_Pos)\r
-\r
-#define   ETH_HW_FEATURE_RXTYP2COE_Pos         (18U)\r
-#define   ETH_HW_FEATURE_RXTYP2COE_Msk         (0x00000001U  << ETH_HW_FEATURE_RXTYP2COE_Pos)\r
-\r
-#define   ETH_HW_FEATURE_RXFIFOSIZE_Pos        (19U)\r
-#define   ETH_HW_FEATURE_RXFIFOSIZE_Msk        (0x00000001U  << ETH_HW_FEATURE_RXFIFOSIZE_Pos)\r
-\r
-#define   ETH_HW_FEATURE_RXCHCNT_Pos   (20U)\r
-#define   ETH_HW_FEATURE_RXCHCNT_Msk   (0x00000003U  << ETH_HW_FEATURE_RXCHCNT_Pos)\r
-\r
-#define   ETH_HW_FEATURE_TXCHCNT_Pos   (22U)\r
-#define   ETH_HW_FEATURE_TXCHCNT_Msk   (0x00000003U  << ETH_HW_FEATURE_TXCHCNT_Pos)\r
-\r
-#define   ETH_HW_FEATURE_ENHDESSEL_Pos         (24U)\r
-#define   ETH_HW_FEATURE_ENHDESSEL_Msk         (0x00000001U  << ETH_HW_FEATURE_ENHDESSEL_Pos)\r
-\r
-#define   ETH_HW_FEATURE_INTTSEN_Pos   (25U)\r
-#define   ETH_HW_FEATURE_INTTSEN_Msk   (0x00000001U  << ETH_HW_FEATURE_INTTSEN_Pos)\r
-\r
-#define   ETH_HW_FEATURE_FLEXIPPSEN_Pos        (26U)\r
-#define   ETH_HW_FEATURE_FLEXIPPSEN_Msk        (0x00000001U  << ETH_HW_FEATURE_FLEXIPPSEN_Pos)\r
-\r
-#define   ETH_HW_FEATURE_SAVLANINS_Pos         (27U)\r
-#define   ETH_HW_FEATURE_SAVLANINS_Msk         (0x00000001U  << ETH_HW_FEATURE_SAVLANINS_Pos)\r
-\r
-#define   ETH_HW_FEATURE_ACTPHYIF_Pos          (28U)\r
-#define   ETH_HW_FEATURE_ACTPHYIF_Msk          (0x00000007U  << ETH_HW_FEATURE_ACTPHYIF_Pos)\r
-\r
-#define   ETH_HW_FEATURE_Reserved_31_Pos       (31U)\r
-#define   ETH_HW_FEATURE_Reserved_31_Msk       (0x00000001U  << ETH_HW_FEATURE_Reserved_31_Pos)\r
-\r
-\r
-\r
-/***   ETH0_CON Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* ETH0_CON  =  Ethernet x Port Control Register*/\r
-#define   ETH_CON_RXD0_Pos     (0U)\r
-#define   ETH_CON_RXD0_Msk     (0x00000003U  << ETH_CON_RXD0_Pos)\r
-\r
-#define   ETH_CON_RXD1_Pos     (2U)\r
-#define   ETH_CON_RXD1_Msk     (0x00000003U  << ETH_CON_RXD1_Pos)\r
-\r
-#define   ETH_CON_RXD2_Pos     (4U)\r
-#define   ETH_CON_RXD2_Msk     (0x00000003U  << ETH_CON_RXD2_Pos)\r
-\r
-#define   ETH_CON_RXD3_Pos     (6U)\r
-#define   ETH_CON_RXD3_Msk     (0x00000003U  << ETH_CON_RXD3_Pos)\r
-\r
-#define   ETH_CON_CLK_RMII_Pos         (8U)\r
-#define   ETH_CON_CLK_RMII_Msk         (0x00000003U  << ETH_CON_CLK_RMII_Pos)\r
-\r
-#define   ETH_CON_CRS_DV_Pos   (10U)\r
-#define   ETH_CON_CRS_DV_Msk   (0x00000003U  << ETH_CON_CRS_DV_Pos)\r
-\r
-#define   ETH_CON_CRS_Pos      (12U)\r
-#define   ETH_CON_CRS_Msk      (0x00000003U  << ETH_CON_CRS_Pos)\r
-\r
-#define   ETH_CON_RXER_Pos     (14U)\r
-#define   ETH_CON_RXER_Msk     (0x00000003U  << ETH_CON_RXER_Pos)\r
-\r
-#define   ETH_CON_COL_Pos      (16U)\r
-#define   ETH_CON_COL_Msk      (0x00000003U  << ETH_CON_COL_Pos)\r
-\r
-#define   ETH_CON_CLK_TX_Pos   (18U)\r
-#define   ETH_CON_CLK_TX_Msk   (0x00000003U  << ETH_CON_CLK_TX_Pos)\r
-\r
-#define   ETH_CON_MDIO_Pos     (22U)\r
-#define   ETH_CON_MDIO_Msk     (0x00000003U  << ETH_CON_MDIO_Pos)\r
-\r
-#define   ETH_CON_INFSEL_Pos   (26U)\r
-#define   ETH_CON_INFSEL_Msk   (0x00000001U  << ETH_CON_INFSEL_Pos)\r
-\r
-\r
-\r
-/***   ETM Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-// ----------------------------------------  ETM_ETMCR  -------------------------------------------\r
-#define ETM_ETMCR_ETM_PowerDown_Pos                           0                                                         /*!< ETM ETMCR: ETM_PowerDown Position   */\r
-#define ETM_ETMCR_ETM_PowerDown_Msk                           (0x01UL << ETM_ETMCR_ETM_PowerDown_Pos)                   /*!< ETM ETMCR: ETM_PowerDown Mask       */\r
-#define ETM_ETMCR_Reserved_Pos                                1                                                         /*!< ETM ETMCR: Reserved Position        */\r
-#define ETM_ETMCR_Reserved_Msk                                (0x07UL << ETM_ETMCR_Reserved_Pos)                        /*!< ETM ETMCR: Reserved Mask            */\r
-#define ETM_ETMCR_PortSize_2_0_Pos                            4                                                         /*!< ETM ETMCR: PortSize_2_0 Position    */\r
-#define ETM_ETMCR_PortSize_2_0_Msk                            (0x07UL << ETM_ETMCR_PortSize_2_0_Pos)                    /*!< ETM ETMCR: PortSize_2_0 Mask        */\r
-#define ETM_ETMCR_StallProcessor_Pos                          7                                                         /*!< ETM ETMCR: StallProcessor Position  */\r
-#define ETM_ETMCR_StallProcessor_Msk                          (0x01UL << ETM_ETMCR_StallProcessor_Pos)                  /*!< ETM ETMCR: StallProcessor Mask      */\r
-#define ETM_ETMCR_BranchOutput_Pos                            8                                                         /*!< ETM ETMCR: BranchOutput Position    */\r
-#define ETM_ETMCR_BranchOutput_Msk                            (0x01UL << ETM_ETMCR_BranchOutput_Pos)                    /*!< ETM ETMCR: BranchOutput Mask        */\r
-#define ETM_ETMCR_DebugRequestControl_Pos                     9                                                         /*!< ETM ETMCR: DebugRequestControl Position */\r
-#define ETM_ETMCR_DebugRequestControl_Msk                     (0x01UL << ETM_ETMCR_DebugRequestControl_Pos)             /*!< ETM ETMCR: DebugRequestControl Mask */\r
-#define ETM_ETMCR_ETM_Programming_Pos                         10                                                        /*!< ETM ETMCR: ETM_Programming Position */\r
-#define ETM_ETMCR_ETM_Programming_Msk                         (0x01UL << ETM_ETMCR_ETM_Programming_Pos)                 /*!< ETM ETMCR: ETM_Programming Mask     */\r
-#define ETM_ETMCR_ETM_PortSelection_Pos                       11                                                        /*!< ETM ETMCR: ETM_PortSelection Position */\r
-#define ETM_ETMCR_ETM_PortSelection_Msk                       (0x01UL << ETM_ETMCR_ETM_PortSelection_Pos)               /*!< ETM ETMCR: ETM_PortSelection Mask   */\r
-#define ETM_ETMCR_Reserved1_Pos                               12                                                        /*!< ETM ETMCR: Reserved1 Position       */\r
-#define ETM_ETMCR_Reserved1_Msk                               (0x01UL << ETM_ETMCR_Reserved1_Pos)                       /*!< ETM ETMCR: Reserved1 Mask           */\r
-#define ETM_ETMCR_PortMode_2_Pos                              13                                                        /*!< ETM ETMCR: PortMode_2 Position      */\r
-#define ETM_ETMCR_PortMode_2_Msk                              (0x01UL << ETM_ETMCR_PortMode_2_Pos)                      /*!< ETM ETMCR: PortMode_2 Mask          */\r
-#define ETM_ETMCR_Reserved2_Pos                               14                                                        /*!< ETM ETMCR: Reserved2 Position       */\r
-#define ETM_ETMCR_Reserved2_Msk                               (0x03UL << ETM_ETMCR_Reserved2_Pos)                       /*!< ETM ETMCR: Reserved2 Mask           */\r
-#define ETM_ETMCR_PortMode_1_0_Pos                            16                                                        /*!< ETM ETMCR: PortMode_1_0 Position    */\r
-#define ETM_ETMCR_PortMode_1_0_Msk                            (0x03UL << ETM_ETMCR_PortMode_1_0_Pos)                    /*!< ETM ETMCR: PortMode_1_0 Mask        */\r
-#define ETM_ETMCR_Reserved3_Pos                               18                                                        /*!< ETM ETMCR: Reserved3 Position       */\r
-#define ETM_ETMCR_Reserved3_Msk                               (0x07UL << ETM_ETMCR_Reserved3_Pos)                       /*!< ETM ETMCR: Reserved3 Mask           */\r
-#define ETM_ETMCR_PortSize_3_Pos                              21                                                        /*!< ETM ETMCR: PortSize_3 Position      */\r
-#define ETM_ETMCR_PortSize_3_Msk                              (0x01UL << ETM_ETMCR_PortSize_3_Pos)                      /*!< ETM ETMCR: PortSize_3 Mask          */\r
-#define ETM_ETMCR_Reserved4_Pos                               22                                                        /*!< ETM ETMCR: Reserved4 Position       */\r
-#define ETM_ETMCR_Reserved4_Msk                               (0x3fUL << ETM_ETMCR_Reserved4_Pos)                       /*!< ETM ETMCR: Reserved4 Mask           */\r
-#define ETM_ETMCR_Timestamp_Pos                               28                                                        /*!< ETM ETMCR: Timestamp Position       */\r
-#define ETM_ETMCR_Timestamp_Msk                               (0x01UL << ETM_ETMCR_Timestamp_Pos)                       /*!< ETM ETMCR: Timestamp Mask           */\r
-#define ETM_ETMCR_Reserved5_Pos                               29                                                        /*!< ETM ETMCR: Reserved5 Position       */\r
-#define ETM_ETMCR_Reserved5_Msk                               (0x07UL << ETM_ETMCR_Reserved5_Pos)                       /*!< ETM ETMCR: Reserved5 Mask           */\r
-\r
-// ---------------------------------------  ETM_ETMCCR  -------------------------------------------\r
-#define ETM_ETMCCR_NumberOfAddressComparatorPairs_Pos         0                                                         /*!< ETM ETMCCR: NumberOfAddressComparatorPairs Position */\r
-#define ETM_ETMCCR_NumberOfAddressComparatorPairs_Msk         (0x0fUL << ETM_ETMCCR_NumberOfAddressComparatorPairs_Pos) /*!< ETM ETMCCR: NumberOfAddressComparatorPairs Mask */\r
-#define ETM_ETMCCR_NumberOfDataValueComparators_Pos           4                                                         /*!< ETM ETMCCR: NumberOfDataValueComparators Position */\r
-#define ETM_ETMCCR_NumberOfDataValueComparators_Msk           (0x0fUL << ETM_ETMCCR_NumberOfDataValueComparators_Pos)   /*!< ETM ETMCCR: NumberOfDataValueComparators Mask */\r
-#define ETM_ETMCCR_NumberOfMemoryMapDecoders_Pos              8                                                         /*!< ETM ETMCCR: NumberOfMemoryMapDecoders Position */\r
-#define ETM_ETMCCR_NumberOfMemoryMapDecoders_Msk              (0x1fUL << ETM_ETMCCR_NumberOfMemoryMapDecoders_Pos)      /*!< ETM ETMCCR: NumberOfMemoryMapDecoders Mask */\r
-#define ETM_ETMCCR_NumberOfCounters_Pos                       13                                                        /*!< ETM ETMCCR: NumberOfCounters Position */\r
-#define ETM_ETMCCR_NumberOfCounters_Msk                       (0x07UL << ETM_ETMCCR_NumberOfCounters_Pos)               /*!< ETM ETMCCR: NumberOfCounters Mask   */\r
-#define ETM_ETMCCR_SequencerPresent_Pos                       16                                                        /*!< ETM ETMCCR: SequencerPresent Position */\r
-#define ETM_ETMCCR_SequencerPresent_Msk                       (0x01UL << ETM_ETMCCR_SequencerPresent_Pos)               /*!< ETM ETMCCR: SequencerPresent Mask   */\r
-#define ETM_ETMCCR_NumberOfExternalIinputs_Pos                17                                                        /*!< ETM ETMCCR: NumberOfExternalIinputs Position */\r
-#define ETM_ETMCCR_NumberOfExternalIinputs_Msk                (0x07UL << ETM_ETMCCR_NumberOfExternalIinputs_Pos)        /*!< ETM ETMCCR: NumberOfExternalIinputs Mask */\r
-#define ETM_ETMCCR_NumberOfExternalOutputs_Pos                20                                                        /*!< ETM ETMCCR: NumberOfExternalOutputs Position */\r
-#define ETM_ETMCCR_NumberOfExternalOutputs_Msk                (0x07UL << ETM_ETMCCR_NumberOfExternalOutputs_Pos)        /*!< ETM ETMCCR: NumberOfExternalOutputs Mask */\r
-#define ETM_ETMCCR_FIFOFULL_LogicPresent_Pos                  23                                                        /*!< ETM ETMCCR: FIFOFULL_LogicPresent Position */\r
-#define ETM_ETMCCR_FIFOFULL_LogicPresent_Msk                  (0x01UL << ETM_ETMCCR_FIFOFULL_LogicPresent_Pos)          /*!< ETM ETMCCR: FIFOFULL_LogicPresent Mask */\r
-#define ETM_ETMCCR_NumberOfContextID_Comparators_Pos          24                                                        /*!< ETM ETMCCR: NumberOfContextID_Comparators Position */\r
-#define ETM_ETMCCR_NumberOfContextID_Comparators_Msk          (0x03UL << ETM_ETMCCR_NumberOfContextID_Comparators_Pos)  /*!< ETM ETMCCR: NumberOfContextID_Comparators Mask */\r
-#define ETM_ETMCCR_TraceStartStopBlockPresent_Pos             26                                                        /*!< ETM ETMCCR: TraceStartStopBlockPresent Position */\r
-#define ETM_ETMCCR_TraceStartStopBlockPresent_Msk             (0x01UL << ETM_ETMCCR_TraceStartStopBlockPresent_Pos)     /*!< ETM ETMCCR: TraceStartStopBlockPresent Mask */\r
-#define ETM_ETMCCR_CoprocessorAndMemoryAccess_Pos             27                                                        /*!< ETM ETMCCR: CoprocessorAndMemoryAccess Position */\r
-#define ETM_ETMCCR_CoprocessorAndMemoryAccess_Msk             (0x01UL << ETM_ETMCCR_CoprocessorAndMemoryAccess_Pos)     /*!< ETM ETMCCR: CoprocessorAndMemoryAccess Mask */\r
-#define ETM_ETMCCR_Reserved_Pos                               28                                                        /*!< ETM ETMCCR: Reserved Position       */\r
-#define ETM_ETMCCR_Reserved_Msk                               (0x07UL << ETM_ETMCCR_Reserved_Pos)                       /*!< ETM ETMCCR: Reserved Mask           */\r
-#define ETM_ETMCCR_ETM_ID_RegisterPresent_Pos                 31                                                        /*!< ETM ETMCCR: ETM_ID_RegisterPresent Position */\r
-#define ETM_ETMCCR_ETM_ID_RegisterPresent_Msk                 (0x01UL << ETM_ETMCCR_ETM_ID_RegisterPresent_Pos)         /*!< ETM ETMCCR: ETM_ID_RegisterPresent Mask */\r
-\r
-// -------------------------------------  ETM_ETMTRIGGER  -----------------------------------------\r
-#define ETM_ETMTRIGGER_ResourceA_Pos                          0                                                         /*!< ETM ETMTRIGGER: ResourceA Position  */\r
-#define ETM_ETMTRIGGER_ResourceA_Msk                          (0x7fUL << ETM_ETMTRIGGER_ResourceA_Pos)                  /*!< ETM ETMTRIGGER: ResourceA Mask      */\r
-#define ETM_ETMTRIGGER_ResourceB_Pos                          7                                                         /*!< ETM ETMTRIGGER: ResourceB Position  */\r
-#define ETM_ETMTRIGGER_ResourceB_Msk                          (0x7fUL << ETM_ETMTRIGGER_ResourceB_Pos)                  /*!< ETM ETMTRIGGER: ResourceB Mask      */\r
-#define ETM_ETMTRIGGER_Function_Pos                           14                                                        /*!< ETM ETMTRIGGER: Function Position   */\r
-#define ETM_ETMTRIGGER_Function_Msk                           (0x07UL << ETM_ETMTRIGGER_Function_Pos)                   /*!< ETM ETMTRIGGER: Function Mask       */\r
-#define ETM_ETMTRIGGER_Reserved_Pos                           17                                                        /*!< ETM ETMTRIGGER: Reserved Position   */\r
-#define ETM_ETMTRIGGER_Reserved_Msk                           (0x00007fffUL << ETM_ETMTRIGGER_Reserved_Pos)             /*!< ETM ETMTRIGGER: Reserved Mask       */\r
-\r
-// ----------------------------------------  ETM_ETMSR  -------------------------------------------\r
-#define ETM_ETMSR_UntracedOverflowFlag_Pos                    0                                                         /*!< ETM ETMSR: UntracedOverflowFlag Position */\r
-#define ETM_ETMSR_UntracedOverflowFlag_Msk                    (0x01UL << ETM_ETMSR_UntracedOverflowFlag_Pos)            /*!< ETM ETMSR: UntracedOverflowFlag Mask */\r
-#define ETM_ETMSR_Progbit_Pos                                 1                                                         /*!< ETM ETMSR: Progbit Position         */\r
-#define ETM_ETMSR_Progbit_Msk                                 (0x01UL << ETM_ETMSR_Progbit_Pos)                         /*!< ETM ETMSR: Progbit Mask             */\r
-#define ETM_ETMSR_TraceStartStopResourceStatus_Pos            2                                                         /*!< ETM ETMSR: TraceStartStopResourceStatus Position */\r
-#define ETM_ETMSR_TraceStartStopResourceStatus_Msk            (0x01UL << ETM_ETMSR_TraceStartStopResourceStatus_Pos)    /*!< ETM ETMSR: TraceStartStopResourceStatus Mask */\r
-#define ETM_ETMSR_TriggerFlag_Pos                             3                                                         /*!< ETM ETMSR: TriggerFlag Position     */\r
-#define ETM_ETMSR_TriggerFlag_Msk                             (0x01UL << ETM_ETMSR_TriggerFlag_Pos)                     /*!< ETM ETMSR: TriggerFlag Mask         */\r
-#define ETM_ETMSR_Reserved_Pos                                4                                                         /*!< ETM ETMSR: Reserved Position        */\r
-#define ETM_ETMSR_Reserved_Msk                                (0x0fffffffUL << ETM_ETMSR_Reserved_Pos)                  /*!< ETM ETMSR: Reserved Mask            */\r
-\r
-// ---------------------------------------  ETM_ETMSCR  -------------------------------------------\r
-#define ETM_ETMSCR_MaximumPortSize_2_0_Pos                    0                                                         /*!< ETM ETMSCR: MaximumPortSize_2_0 Position */\r
-#define ETM_ETMSCR_MaximumPortSize_2_0_Msk                    (0x07UL << ETM_ETMSCR_MaximumPortSize_2_0_Pos)            /*!< ETM ETMSCR: MaximumPortSize_2_0 Mask */\r
-#define ETM_ETMSCR_Reserved_Pos                               3                                                         /*!< ETM ETMSCR: Reserved Position       */\r
-#define ETM_ETMSCR_Reserved_Msk                               (0x01UL << ETM_ETMSCR_Reserved_Pos)                       /*!< ETM ETMSCR: Reserved Mask           */\r
-#define ETM_ETMSCR_Reserved1_Pos                              4                                                         /*!< ETM ETMSCR: Reserved1 Position      */\r
-#define ETM_ETMSCR_Reserved1_Msk                              (0x0fUL << ETM_ETMSCR_Reserved1_Pos)                      /*!< ETM ETMSCR: Reserved1 Mask          */\r
-#define ETM_ETMSCR_FIFOFULL_Supported_Pos                     8                                                         /*!< ETM ETMSCR: FIFOFULL_Supported Position */\r
-#define ETM_ETMSCR_FIFOFULL_Supported_Msk                     (0x01UL << ETM_ETMSCR_FIFOFULL_Supported_Pos)             /*!< ETM ETMSCR: FIFOFULL_Supported Mask */\r
-#define ETM_ETMSCR_MaximumPortSize_3_Pos                      9                                                         /*!< ETM ETMSCR: MaximumPortSize_3 Position */\r
-#define ETM_ETMSCR_MaximumPortSize_3_Msk                      (0x01UL << ETM_ETMSCR_MaximumPortSize_3_Pos)              /*!< ETM ETMSCR: MaximumPortSize_3 Mask  */\r
-#define ETM_ETMSCR_PortSizeSupported_Pos                      10                                                        /*!< ETM ETMSCR: PortSizeSupported Position */\r
-#define ETM_ETMSCR_PortSizeSupported_Msk                      (0x01UL << ETM_ETMSCR_PortSizeSupported_Pos)              /*!< ETM ETMSCR: PortSizeSupported Mask  */\r
-#define ETM_ETMSCR_PortModeSupported_Pos                      11                                                        /*!< ETM ETMSCR: PortModeSupported Position */\r
-#define ETM_ETMSCR_PortModeSupported_Msk                      (0x01UL << ETM_ETMSCR_PortModeSupported_Pos)              /*!< ETM ETMSCR: PortModeSupported Mask  */\r
-#define ETM_ETMSCR_N_Minus_1_Pos                              12                                                        /*!< ETM ETMSCR: N_Minus_1 Position      */\r
-#define ETM_ETMSCR_N_Minus_1_Msk                              (0x07UL << ETM_ETMSCR_N_Minus_1_Pos)                      /*!< ETM ETMSCR: N_Minus_1 Mask          */\r
-#define ETM_ETMSCR_Reserved2_Pos                              15                                                        /*!< ETM ETMSCR: Reserved2 Position      */\r
-#define ETM_ETMSCR_Reserved2_Msk                              (0x03UL << ETM_ETMSCR_Reserved2_Pos)                      /*!< ETM ETMSCR: Reserved2 Mask          */\r
-#define ETM_ETMSCR_NoFetchComparisons_Pos                     17                                                        /*!< ETM ETMSCR: NoFetchComparisons Position */\r
-#define ETM_ETMSCR_NoFetchComparisons_Msk                     (0x01UL << ETM_ETMSCR_NoFetchComparisons_Pos)             /*!< ETM ETMSCR: NoFetchComparisons Mask */\r
-#define ETM_ETMSCR_Reserved3_Pos                              18                                                        /*!< ETM ETMSCR: Reserved3 Position      */\r
-#define ETM_ETMSCR_Reserved3_Msk                              (0x00003fffUL << ETM_ETMSCR_Reserved3_Pos)                /*!< ETM ETMSCR: Reserved3 Mask          */\r
-\r
-// --------------------------------------  ETM_ETMTEEVR  ------------------------------------------\r
-#define ETM_ETMTEEVR_ResourceA_Pos                            0                                                         /*!< ETM ETMTEEVR: ResourceA Position    */\r
-#define ETM_ETMTEEVR_ResourceA_Msk                            (0x7fUL << ETM_ETMTEEVR_ResourceA_Pos)                    /*!< ETM ETMTEEVR: ResourceA Mask        */\r
-#define ETM_ETMTEEVR_ResourceB_Pos                            7                                                         /*!< ETM ETMTEEVR: ResourceB Position    */\r
-#define ETM_ETMTEEVR_ResourceB_Msk                            (0x7fUL << ETM_ETMTEEVR_ResourceB_Pos)                    /*!< ETM ETMTEEVR: ResourceB Mask        */\r
-#define ETM_ETMTEEVR_Function_Pos                             14                                                        /*!< ETM ETMTEEVR: Function Position     */\r
-#define ETM_ETMTEEVR_Function_Msk                             (0x07UL << ETM_ETMTEEVR_Function_Pos)                     /*!< ETM ETMTEEVR: Function Mask         */\r
-#define ETM_ETMTEEVR_Reserved_Pos                             17                                                        /*!< ETM ETMTEEVR: Reserved Position     */\r
-#define ETM_ETMTEEVR_Reserved_Msk                             (0x00007fffUL << ETM_ETMTEEVR_Reserved_Pos)               /*!< ETM ETMTEEVR: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMTECR1  ------------------------------------------\r
-#define ETM_ETMTECR1_Reserved_Pos                             0                                                         /*!< ETM ETMTECR1: Reserved Position     */\r
-#define ETM_ETMTECR1_Reserved_Msk                             (0x01ffffffUL << ETM_ETMTECR1_Reserved_Pos)               /*!< ETM ETMTECR1: Reserved Mask         */\r
-#define ETM_ETMTECR1_TraceStartStopEnable_Pos                 25                                                        /*!< ETM ETMTECR1: TraceStartStopEnable Position */\r
-#define ETM_ETMTECR1_TraceStartStopEnable_Msk                 (0x01UL << ETM_ETMTECR1_TraceStartStopEnable_Pos)         /*!< ETM ETMTECR1: TraceStartStopEnable Mask */\r
-#define ETM_ETMTECR1_Reserved1_Pos                            26                                                        /*!< ETM ETMTECR1: Reserved1 Position    */\r
-#define ETM_ETMTECR1_Reserved1_Msk                            (0x3fUL << ETM_ETMTECR1_Reserved1_Pos)                    /*!< ETM ETMTECR1: Reserved1 Mask        */\r
-\r
-// ---------------------------------------  ETM_ETMFFLR  ------------------------------------------\r
-#define ETM_ETMFFLR_FIFO_FullLevel_Pos                        0                                                         /*!< ETM ETMFFLR: FIFO_FullLevel Position */\r
-#define ETM_ETMFFLR_FIFO_FullLevel_Msk                        (0x000000ffUL << ETM_ETMFFLR_FIFO_FullLevel_Pos)          /*!< ETM ETMFFLR: FIFO_FullLevel Mask    */\r
-#define ETM_ETMFFLR_Reserved_Pos                              8                                                         /*!< ETM ETMFFLR: Reserved Position      */\r
-#define ETM_ETMFFLR_Reserved_Msk                              (0x00ffffffUL << ETM_ETMFFLR_Reserved_Pos)                /*!< ETM ETMFFLR: Reserved Mask          */\r
-\r
-// ------------------------------------  ETM_ETMCNTRLDVR1  ----------------------------------------\r
-#define ETM_ETMCNTRLDVR1_InitialCount_Pos                     0                                                         /*!< ETM ETMCNTRLDVR1: InitialCount Position */\r
-#define ETM_ETMCNTRLDVR1_InitialCount_Msk                     (0x0000ffffUL << ETM_ETMCNTRLDVR1_InitialCount_Pos)       /*!< ETM ETMCNTRLDVR1: InitialCount Mask */\r
-#define ETM_ETMCNTRLDVR1_Reserved_Pos                         16                                                        /*!< ETM ETMCNTRLDVR1: Reserved Position */\r
-#define ETM_ETMCNTRLDVR1_Reserved_Msk                         (0x0000ffffUL << ETM_ETMCNTRLDVR1_Reserved_Pos)           /*!< ETM ETMCNTRLDVR1: Reserved Mask     */\r
-\r
-// --------------------------------------  ETM_ETMSYNCFR  -----------------------------------------\r
-#define ETM_ETMSYNCFR_SynchronizationFrequency_Pos            0                                                         /*!< ETM ETMSYNCFR: SynchronizationFrequency Position */\r
-#define ETM_ETMSYNCFR_SynchronizationFrequency_Msk            (0x00000fffUL << ETM_ETMSYNCFR_SynchronizationFrequency_Pos)/*!< ETM ETMSYNCFR: SynchronizationFrequency Mask */\r
-#define ETM_ETMSYNCFR_Reserved_Pos                            12                                                        /*!< ETM ETMSYNCFR: Reserved Position    */\r
-#define ETM_ETMSYNCFR_Reserved_Msk                            (0x000fffffUL << ETM_ETMSYNCFR_Reserved_Pos)              /*!< ETM ETMSYNCFR: Reserved Mask        */\r
-\r
-// ---------------------------------------  ETM_ETMIDR  -------------------------------------------\r
-#define ETM_ETMIDR_ImplementationRevision_Pos                 0                                                         /*!< ETM ETMIDR: ImplementationRevision Position */\r
-#define ETM_ETMIDR_ImplementationRevision_Msk                 (0x0fUL << ETM_ETMIDR_ImplementationRevision_Pos)         /*!< ETM ETMIDR: ImplementationRevision Mask */\r
-#define ETM_ETMIDR_MinorETM_ArchitectureVersion_Pos           4                                                         /*!< ETM ETMIDR: MinorETM_ArchitectureVersion Position */\r
-#define ETM_ETMIDR_MinorETM_ArchitectureVersion_Msk           (0x0fUL << ETM_ETMIDR_MinorETM_ArchitectureVersion_Pos)   /*!< ETM ETMIDR: MinorETM_ArchitectureVersion Mask */\r
-#define ETM_ETMIDR_MajorETM_ArchitectureVersion_Pos           8                                                         /*!< ETM ETMIDR: MajorETM_ArchitectureVersion Position */\r
-#define ETM_ETMIDR_MajorETM_ArchitectureVersion_Msk           (0x0fUL << ETM_ETMIDR_MajorETM_ArchitectureVersion_Pos)   /*!< ETM ETMIDR: MajorETM_ArchitectureVersion Mask */\r
-#define ETM_ETMIDR_ProcessorFamily_Pos                        12                                                        /*!< ETM ETMIDR: ProcessorFamily Position */\r
-#define ETM_ETMIDR_ProcessorFamily_Msk                        (0x0fUL << ETM_ETMIDR_ProcessorFamily_Pos)                /*!< ETM ETMIDR: ProcessorFamily Mask    */\r
-#define ETM_ETMIDR_LoadPC_First_Pos                           16                                                        /*!< ETM ETMIDR: LoadPC_First Position   */\r
-#define ETM_ETMIDR_LoadPC_First_Msk                           (0x01UL << ETM_ETMIDR_LoadPC_First_Pos)                   /*!< ETM ETMIDR: LoadPC_First Mask       */\r
-#define ETM_ETMIDR_Reserved_Pos                               17                                                        /*!< ETM ETMIDR: Reserved Position       */\r
-#define ETM_ETMIDR_Reserved_Msk                               (0x01UL << ETM_ETMIDR_Reserved_Pos)                       /*!< ETM ETMIDR: Reserved Mask           */\r
-#define ETM_ETMIDR_Bitfield_32bitThumbInstructionTracing_Pos  18                                                        /*!< ETM ETMIDR: Bitfield_32bitThumbInstructionTracing Position */\r
-#define ETM_ETMIDR_Bitfield_32bitThumbInstructionTracing_Msk  (0x01UL << ETM_ETMIDR_Bitfield_32bitThumbInstructionTracing_Pos)/*!< ETM ETMIDR: Bitfield_32bitThumbInstructionTracing Mask */\r
-#define ETM_ETMIDR_SecurityExtensionsSupport_Pos              19                                                        /*!< ETM ETMIDR: SecurityExtensionsSupport Position */\r
-#define ETM_ETMIDR_SecurityExtensionsSupport_Msk              (0x01UL << ETM_ETMIDR_SecurityExtensionsSupport_Pos)      /*!< ETM ETMIDR: SecurityExtensionsSupport Mask */\r
-#define ETM_ETMIDR_BranchPacketEncoding_Pos                   20                                                        /*!< ETM ETMIDR: BranchPacketEncoding Position */\r
-#define ETM_ETMIDR_BranchPacketEncoding_Msk                   (0x01UL << ETM_ETMIDR_BranchPacketEncoding_Pos)           /*!< ETM ETMIDR: BranchPacketEncoding Mask */\r
-#define ETM_ETMIDR_Reserved1_Pos                              21                                                        /*!< ETM ETMIDR: Reserved1 Position      */\r
-#define ETM_ETMIDR_Reserved1_Msk                              (0x07UL << ETM_ETMIDR_Reserved1_Pos)                      /*!< ETM ETMIDR: Reserved1 Mask          */\r
-#define ETM_ETMIDR_ImplementerCode_Pos                        24                                                        /*!< ETM ETMIDR: ImplementerCode Position */\r
-#define ETM_ETMIDR_ImplementerCode_Msk                        (0x000000ffUL << ETM_ETMIDR_ImplementerCode_Pos)          /*!< ETM ETMIDR: ImplementerCode Mask    */\r
-\r
-// ---------------------------------------  ETM_ETMCCER  ------------------------------------------\r
-#define ETM_ETMCCER_ExtendedExternalInputSelectors_Pos        0                                                         /*!< ETM ETMCCER: ExtendedExternalInputSelectors Position */\r
-#define ETM_ETMCCER_ExtendedExternalInputSelectors_Msk        (0x07UL << ETM_ETMCCER_ExtendedExternalInputSelectors_Pos)/*!< ETM ETMCCER: ExtendedExternalInputSelectors Mask */\r
-#define ETM_ETMCCER_ExtendedExternalInputBus_Pos              3                                                         /*!< ETM ETMCCER: ExtendedExternalInputBus Position */\r
-#define ETM_ETMCCER_ExtendedExternalInputBus_Msk              (0x000000ffUL << ETM_ETMCCER_ExtendedExternalInputBus_Pos)/*!< ETM ETMCCER: ExtendedExternalInputBus Mask */\r
-#define ETM_ETMCCER_ReadableRegisters_Pos                     11                                                        /*!< ETM ETMCCER: ReadableRegisters Position */\r
-#define ETM_ETMCCER_ReadableRegisters_Msk                     (0x01UL << ETM_ETMCCER_ReadableRegisters_Pos)             /*!< ETM ETMCCER: ReadableRegisters Mask */\r
-#define ETM_ETMCCER_DataAddressComparisons_Pos                12                                                        /*!< ETM ETMCCER: DataAddressComparisons Position */\r
-#define ETM_ETMCCER_DataAddressComparisons_Msk                (0x01UL << ETM_ETMCCER_DataAddressComparisons_Pos)        /*!< ETM ETMCCER: DataAddressComparisons Mask */\r
-#define ETM_ETMCCER_InstrumentationResources_Pos              13                                                        /*!< ETM ETMCCER: InstrumentationResources Position */\r
-#define ETM_ETMCCER_InstrumentationResources_Msk              (0x07UL << ETM_ETMCCER_InstrumentationResources_Pos)      /*!< ETM ETMCCER: InstrumentationResources Mask */\r
-#define ETM_ETMCCER_EmbeddedICE_WatchpointInputs_Pos          16                                                        /*!< ETM ETMCCER: EmbeddedICE_WatchpointInputs Position */\r
-#define ETM_ETMCCER_EmbeddedICE_WatchpointInputs_Msk          (0x0fUL << ETM_ETMCCER_EmbeddedICE_WatchpointInputs_Pos)  /*!< ETM ETMCCER: EmbeddedICE_WatchpointInputs Mask */\r
-#define ETM_ETMCCER_TraceStartStopBlockUsesEmbeddediceWatchpointInputs_Pos20                                            /*!< ETM ETMCCER: TraceStartStopBlockUsesEmbeddediceWatchpointInputs Position */\r
-#define ETM_ETMCCER_TraceStartStopBlockUsesEmbeddediceWatchpointInputs_Msk (0x01UL << ETM_ETMCCER_TraceStartStopBlockUsesEmbeddediceWatchpointInputs_Pos)/*!< ETM ETMCCER: TraceStartStopBlockUsesEmbeddediceWatchpointInputs Mask */\r
-#define ETM_ETMCCER_EmbeddediceBehaviorControlImplemented_Pos 21                                                        /*!< ETM ETMCCER: EmbeddediceBehaviorControlImplemented Position */\r
-#define ETM_ETMCCER_EmbeddediceBehaviorControlImplemented_Msk (0x01UL << ETM_ETMCCER_EmbeddediceBehaviorControlImplemented_Pos)/*!< ETM ETMCCER: EmbeddediceBehaviorControlImplemented Mask */\r
-#define ETM_ETMCCER_TimestampingImplemented_Pos               22                                                        /*!< ETM ETMCCER: TimestampingImplemented Position */\r
-#define ETM_ETMCCER_TimestampingImplemented_Msk               (0x01UL << ETM_ETMCCER_TimestampingImplemented_Pos)       /*!< ETM ETMCCER: TimestampingImplemented Mask */\r
-#define ETM_ETMCCER_Reserved_Pos                              23                                                        /*!< ETM ETMCCER: Reserved Position      */\r
-#define ETM_ETMCCER_Reserved_Msk                              (0x0fUL << ETM_ETMCCER_Reserved_Pos)                      /*!< ETM ETMCCER: Reserved Mask          */\r
-#define ETM_ETMCCER_ReducedFunctionCounter_Pos                27                                                        /*!< ETM ETMCCER: ReducedFunctionCounter Position */\r
-#define ETM_ETMCCER_ReducedFunctionCounter_Msk                (0x01UL << ETM_ETMCCER_ReducedFunctionCounter_Pos)        /*!< ETM ETMCCER: ReducedFunctionCounter Mask */\r
-#define ETM_ETMCCER_TimestampEncoding_Pos                     28                                                        /*!< ETM ETMCCER: TimestampEncoding Position */\r
-#define ETM_ETMCCER_TimestampEncoding_Msk                     (0x01UL << ETM_ETMCCER_TimestampEncoding_Pos)             /*!< ETM ETMCCER: TimestampEncoding Mask */\r
-#define ETM_ETMCCER_TimestampSize_Pos                         29                                                        /*!< ETM ETMCCER: TimestampSize Position */\r
-#define ETM_ETMCCER_TimestampSize_Msk                         (0x01UL << ETM_ETMCCER_TimestampSize_Pos)                 /*!< ETM ETMCCER: TimestampSize Mask     */\r
-#define ETM_ETMCCER_Reserved1_Pos                             30                                                        /*!< ETM ETMCCER: Reserved1 Position     */\r
-#define ETM_ETMCCER_Reserved1_Msk                             (0x03UL << ETM_ETMCCER_Reserved1_Pos)                     /*!< ETM ETMCCER: Reserved1 Mask         */\r
-\r
-// -------------------------------------  ETM_ETMTESSEICR  ----------------------------------------\r
-#define ETM_ETMTESSEICR_StartResourceSelect_Pos               0                                                         /*!< ETM ETMTESSEICR: StartResourceSelect Position */\r
-#define ETM_ETMTESSEICR_StartResourceSelect_Msk               (0x000000ffUL << ETM_ETMTESSEICR_StartResourceSelect_Pos) /*!< ETM ETMTESSEICR: StartResourceSelect Mask */\r
-#define ETM_ETMTESSEICR_Reserved_Pos                          8                                                         /*!< ETM ETMTESSEICR: Reserved Position  */\r
-#define ETM_ETMTESSEICR_Reserved_Msk                          (0x000000ffUL << ETM_ETMTESSEICR_Reserved_Pos)            /*!< ETM ETMTESSEICR: Reserved Mask      */\r
-#define ETM_ETMTESSEICR_StopResourceSelect_Pos                16                                                        /*!< ETM ETMTESSEICR: StopResourceSelect Position */\r
-#define ETM_ETMTESSEICR_StopResourceSelect_Msk                (0x000000ffUL << ETM_ETMTESSEICR_StopResourceSelect_Pos)  /*!< ETM ETMTESSEICR: StopResourceSelect Mask */\r
-#define ETM_ETMTESSEICR_Reserved1_Pos                         24                                                        /*!< ETM ETMTESSEICR: Reserved1 Position */\r
-#define ETM_ETMTESSEICR_Reserved1_Msk                         (0x000000ffUL << ETM_ETMTESSEICR_Reserved1_Pos)           /*!< ETM ETMTESSEICR: Reserved1 Mask     */\r
-\r
-// --------------------------------------  ETM_ETMTSEVR  ------------------------------------------\r
-#define ETM_ETMTSEVR_ResourceA_Pos                            0                                                         /*!< ETM ETMTSEVR: ResourceA Position    */\r
-#define ETM_ETMTSEVR_ResourceA_Msk                            (0x7fUL << ETM_ETMTSEVR_ResourceA_Pos)                    /*!< ETM ETMTSEVR: ResourceA Mask        */\r
-#define ETM_ETMTSEVR_ResourceB_Pos                            7                                                         /*!< ETM ETMTSEVR: ResourceB Position    */\r
-#define ETM_ETMTSEVR_ResourceB_Msk                            (0x7fUL << ETM_ETMTSEVR_ResourceB_Pos)                    /*!< ETM ETMTSEVR: ResourceB Mask        */\r
-#define ETM_ETMTSEVR_Function_Pos                             14                                                        /*!< ETM ETMTSEVR: Function Position     */\r
-#define ETM_ETMTSEVR_Function_Msk                             (0x07UL << ETM_ETMTSEVR_Function_Pos)                     /*!< ETM ETMTSEVR: Function Mask         */\r
-#define ETM_ETMTSEVR_Reserved_Pos                             17                                                        /*!< ETM ETMTSEVR: Reserved Position     */\r
-#define ETM_ETMTSEVR_Reserved_Msk                             (0x00007fffUL << ETM_ETMTSEVR_Reserved_Pos)               /*!< ETM ETMTSEVR: Reserved Mask         */\r
-\r
-// -------------------------------------  ETM_ETMTRACEIDR  ----------------------------------------\r
-#define ETM_ETMTRACEIDR_EmbeddedICE_WatchpointInputs_Pos      0                                                         /*!< ETM ETMTRACEIDR: EmbeddedICE_WatchpointInputs Position */\r
-#define ETM_ETMTRACEIDR_EmbeddedICE_WatchpointInputs_Msk      (0x7fUL << ETM_ETMTRACEIDR_EmbeddedICE_WatchpointInputs_Pos)/*!< ETM ETMTRACEIDR: EmbeddedICE_WatchpointInputs Mask */\r
-#define ETM_ETMTRACEIDR_Reserved_Pos                          7                                                         /*!< ETM ETMTRACEIDR: Reserved Position  */\r
-#define ETM_ETMTRACEIDR_Reserved_Msk                          (0x01ffffffUL << ETM_ETMTRACEIDR_Reserved_Pos)            /*!< ETM ETMTRACEIDR: Reserved Mask      */\r
-\r
-// ---------------------------------------  ETM_ETMIDR2  ------------------------------------------\r
-#define ETM_ETMIDR2_RFE_TransferOrder_Pos                     0                                                         /*!< ETM ETMIDR2: RFE_TransferOrder Position */\r
-#define ETM_ETMIDR2_RFE_TransferOrder_Msk                     (0x01UL << ETM_ETMIDR2_RFE_TransferOrder_Pos)             /*!< ETM ETMIDR2: RFE_TransferOrder Mask */\r
-#define ETM_ETMIDR2_SWP_TransferOrder_Pos                     1                                                         /*!< ETM ETMIDR2: SWP_TransferOrder Position */\r
-#define ETM_ETMIDR2_SWP_TransferOrder_Msk                     (0x01UL << ETM_ETMIDR2_SWP_TransferOrder_Pos)             /*!< ETM ETMIDR2: SWP_TransferOrder Mask */\r
-#define ETM_ETMIDR2_Reserved_Pos                              2                                                         /*!< ETM ETMIDR2: Reserved Position      */\r
-#define ETM_ETMIDR2_Reserved_Msk                              (0x3fffffffUL << ETM_ETMIDR2_Reserved_Pos)                /*!< ETM ETMIDR2: Reserved Mask          */\r
-\r
-// ---------------------------------------  ETM_ETMPDSR  ------------------------------------------\r
-#define ETM_ETMPDSR_ETM_PoweredUp_Pos                         0                                                         /*!< ETM ETMPDSR: ETM_PoweredUp Position */\r
-#define ETM_ETMPDSR_ETM_PoweredUp_Msk                         (0x01UL << ETM_ETMPDSR_ETM_PoweredUp_Pos)                 /*!< ETM ETMPDSR: ETM_PoweredUp Mask     */\r
-#define ETM_ETMPDSR_Reserved_Pos                              1                                                         /*!< ETM ETMPDSR: Reserved Position      */\r
-#define ETM_ETMPDSR_Reserved_Msk                              (0x7fffffffUL << ETM_ETMPDSR_Reserved_Pos)                /*!< ETM ETMPDSR: Reserved Mask          */\r
-\r
-// --------------------------------------  ETM_ITMISCIN  ------------------------------------------\r
-#define ETM_ITMISCIN_EXTIN_1_0_Pos                            0                                                         /*!< ETM ITMISCIN: EXTIN_1_0 Position    */\r
-#define ETM_ITMISCIN_EXTIN_1_0_Msk                            (0x03UL << ETM_ITMISCIN_EXTIN_1_0_Pos)                    /*!< ETM ITMISCIN: EXTIN_1_0 Mask        */\r
-#define ETM_ITMISCIN_Reserved_Pos                             2                                                         /*!< ETM ITMISCIN: Reserved Position     */\r
-#define ETM_ITMISCIN_Reserved_Msk                             (0x03UL << ETM_ITMISCIN_Reserved_Pos)                     /*!< ETM ITMISCIN: Reserved Mask         */\r
-#define ETM_ITMISCIN_COREHALT_Pos                             4                                                         /*!< ETM ITMISCIN: COREHALT Position     */\r
-#define ETM_ITMISCIN_COREHALT_Msk                             (0x01UL << ETM_ITMISCIN_COREHALT_Pos)                     /*!< ETM ITMISCIN: COREHALT Mask         */\r
-#define ETM_ITMISCIN_Reserved1_Pos                            5                                                         /*!< ETM ITMISCIN: Reserved1 Position    */\r
-#define ETM_ITMISCIN_Reserved1_Msk                            (0x07ffffffUL << ETM_ITMISCIN_Reserved1_Pos)              /*!< ETM ITMISCIN: Reserved1 Mask        */\r
-\r
-// --------------------------------------  ETM_ITTRIGOUT  -----------------------------------------\r
-#define ETM_ITTRIGOUT_TRIGGER_OutputValue_Pos                 0                                                         /*!< ETM ITTRIGOUT: TRIGGER_OutputValue Position */\r
-#define ETM_ITTRIGOUT_TRIGGER_OutputValue_Msk                 (0x01UL << ETM_ITTRIGOUT_TRIGGER_OutputValue_Pos)         /*!< ETM ITTRIGOUT: TRIGGER_OutputValue Mask */\r
-#define ETM_ITTRIGOUT_Reserved_Pos                            1                                                         /*!< ETM ITTRIGOUT: Reserved Position    */\r
-#define ETM_ITTRIGOUT_Reserved_Msk                            (0x7fffffffUL << ETM_ITTRIGOUT_Reserved_Pos)              /*!< ETM ITTRIGOUT: Reserved Mask        */\r
-\r
-// ------------------------------------  ETM_ETM_ITATBCTR2  ---------------------------------------\r
-#define ETM_ETM_ITATBCTR2_ATREADYInputValue_Pos               0                                                         /*!< ETM ETM_ITATBCTR2: ATREADYInputValue Position */\r
-#define ETM_ETM_ITATBCTR2_ATREADYInputValue_Msk               (0x01UL << ETM_ETM_ITATBCTR2_ATREADYInputValue_Pos)       /*!< ETM ETM_ITATBCTR2: ATREADYInputValue Mask */\r
-#define ETM_ETM_ITATBCTR2_Reserved_Pos                        1                                                         /*!< ETM ETM_ITATBCTR2: Reserved Position */\r
-#define ETM_ETM_ITATBCTR2_Reserved_Msk                        (0x7fffffffUL << ETM_ETM_ITATBCTR2_Reserved_Pos)          /*!< ETM ETM_ITATBCTR2: Reserved Mask    */\r
-\r
-// ------------------------------------  ETM_ETM_ITATBCTR0  ---------------------------------------\r
-#define ETM_ETM_ITATBCTR0_ATVALIDOutputValue_Pos              0                                                         /*!< ETM ETM_ITATBCTR0: ATVALIDOutputValue Position */\r
-#define ETM_ETM_ITATBCTR0_ATVALIDOutputValue_Msk              (0x01UL << ETM_ETM_ITATBCTR0_ATVALIDOutputValue_Pos)      /*!< ETM ETM_ITATBCTR0: ATVALIDOutputValue Mask */\r
-#define ETM_ETM_ITATBCTR0_Reserved_Pos                        1                                                         /*!< ETM ETM_ITATBCTR0: Reserved Position */\r
-#define ETM_ETM_ITATBCTR0_Reserved_Msk                        (0x7fffffffUL << ETM_ETM_ITATBCTR0_Reserved_Pos)          /*!< ETM ETM_ITATBCTR0: Reserved Mask    */\r
-\r
-// --------------------------------------  ETM_ETMITCTRL  -----------------------------------------\r
-#define ETM_ETMITCTRL_EnableIntegrationMode_Pos               0                                                         /*!< ETM ETMITCTRL: EnableIntegrationMode Position */\r
-#define ETM_ETMITCTRL_EnableIntegrationMode_Msk               (0x01UL << ETM_ETMITCTRL_EnableIntegrationMode_Pos)       /*!< ETM ETMITCTRL: EnableIntegrationMode Mask */\r
-#define ETM_ETMITCTRL_Reserved_Pos                            1                                                         /*!< ETM ETMITCTRL: Reserved Position    */\r
-#define ETM_ETMITCTRL_Reserved_Msk                            (0x7fffffffUL << ETM_ETMITCTRL_Reserved_Pos)              /*!< ETM ETMITCTRL: Reserved Mask        */\r
-\r
-// -------------------------------------  ETM_ETMCLAIMSET  ----------------------------------------\r
-#define ETM_ETMCLAIMSET_ClaimTag_Pos                          0                                                         /*!< ETM ETMCLAIMSET: ClaimTag Position  */\r
-#define ETM_ETMCLAIMSET_ClaimTag_Msk                          (0x000000ffUL << ETM_ETMCLAIMSET_ClaimTag_Pos)            /*!< ETM ETMCLAIMSET: ClaimTag Mask      */\r
-#define ETM_ETMCLAIMSET_Reserved_Pos                          8                                                         /*!< ETM ETMCLAIMSET: Reserved Position  */\r
-#define ETM_ETMCLAIMSET_Reserved_Msk                          (0x00ffffffUL << ETM_ETMCLAIMSET_Reserved_Pos)            /*!< ETM ETMCLAIMSET: Reserved Mask      */\r
-\r
-// -------------------------------------  ETM_ETMCLAIMCLR  ----------------------------------------\r
-#define ETM_ETMCLAIMCLR_ClaimTag_Pos                          0                                                         /*!< ETM ETMCLAIMCLR: ClaimTag Position  */\r
-#define ETM_ETMCLAIMCLR_ClaimTag_Msk                          (0x000000ffUL << ETM_ETMCLAIMCLR_ClaimTag_Pos)            /*!< ETM ETMCLAIMCLR: ClaimTag Mask      */\r
-#define ETM_ETMCLAIMCLR_Reserved_Pos                          8                                                         /*!< ETM ETMCLAIMCLR: Reserved Position  */\r
-#define ETM_ETMCLAIMCLR_Reserved_Msk                          (0x00ffffffUL << ETM_ETMCLAIMCLR_Reserved_Pos)            /*!< ETM ETMCLAIMCLR: Reserved Mask      */\r
-\r
-// ---------------------------------------  ETM_ETMLAR  -------------------------------------------\r
-#define ETM_ETMLAR_KeyValue_Pos                               0                                                         /*!< ETM ETMLAR: KeyValue Position       */\r
-#define ETM_ETMLAR_KeyValue_Msk                               (0xffffffffUL << ETM_ETMLAR_KeyValue_Pos)                 /*!< ETM ETMLAR: KeyValue Mask           */\r
-\r
-// ---------------------------------------  ETM_ETMLSR  -------------------------------------------\r
-#define ETM_ETMLSR_ETM_LockingImplemented_Pos                 0                                                         /*!< ETM ETMLSR: ETM_LockingImplemented Position */\r
-#define ETM_ETMLSR_ETM_LockingImplemented_Msk                 (0x01UL << ETM_ETMLSR_ETM_LockingImplemented_Pos)         /*!< ETM ETMLSR: ETM_LockingImplemented Mask */\r
-#define ETM_ETMLSR_ETM_Locked_Pos                             1                                                         /*!< ETM ETMLSR: ETM_Locked Position     */\r
-#define ETM_ETMLSR_ETM_Locked_Msk                             (0x01UL << ETM_ETMLSR_ETM_Locked_Pos)                     /*!< ETM ETMLSR: ETM_Locked Mask         */\r
-#define ETM_ETMLSR_ReadsAsZero_Pos                            2                                                         /*!< ETM ETMLSR: ReadsAsZero Position    */\r
-#define ETM_ETMLSR_ReadsAsZero_Msk                            (0x01UL << ETM_ETMLSR_ReadsAsZero_Pos)                    /*!< ETM ETMLSR: ReadsAsZero Mask        */\r
-#define ETM_ETMLSR_Reserved_Pos                               3                                                         /*!< ETM ETMLSR: Reserved Position       */\r
-#define ETM_ETMLSR_Reserved_Msk                               (0x1fffffffUL << ETM_ETMLSR_Reserved_Pos)                 /*!< ETM ETMLSR: Reserved Mask           */\r
-\r
-// ------------------------------------  ETM_ETMAUTHSTATUS  ---------------------------------------\r
-#define ETM_ETMAUTHSTATUS_NonsecureInvasiveDebug_Pos          0                                                         /*!< ETM ETMAUTHSTATUS: NonsecureInvasiveDebug Position */\r
-#define ETM_ETMAUTHSTATUS_NonsecureInvasiveDebug_Msk          (0x03UL << ETM_ETMAUTHSTATUS_NonsecureInvasiveDebug_Pos)  /*!< ETM ETMAUTHSTATUS: NonsecureInvasiveDebug Mask */\r
-#define ETM_ETMAUTHSTATUS_NonsecureNonInvasiveDebug_Pos       2                                                         /*!< ETM ETMAUTHSTATUS: NonsecureNonInvasiveDebug Position */\r
-#define ETM_ETMAUTHSTATUS_NonsecureNonInvasiveDebug_Msk       (0x03UL << ETM_ETMAUTHSTATUS_NonsecureNonInvasiveDebug_Pos)/*!< ETM ETMAUTHSTATUS: NonsecureNonInvasiveDebug Mask */\r
-#define ETM_ETMAUTHSTATUS_SecureInvasiveDebug_Pos             4                                                         /*!< ETM ETMAUTHSTATUS: SecureInvasiveDebug Position */\r
-#define ETM_ETMAUTHSTATUS_SecureInvasiveDebug_Msk             (0x03UL << ETM_ETMAUTHSTATUS_SecureInvasiveDebug_Pos)     /*!< ETM ETMAUTHSTATUS: SecureInvasiveDebug Mask */\r
-#define ETM_ETMAUTHSTATUS_SecureNonInvasiveDebug_Pos          6                                                         /*!< ETM ETMAUTHSTATUS: SecureNonInvasiveDebug Position */\r
-#define ETM_ETMAUTHSTATUS_SecureNonInvasiveDebug_Msk          (0x03UL << ETM_ETMAUTHSTATUS_SecureNonInvasiveDebug_Pos)  /*!< ETM ETMAUTHSTATUS: SecureNonInvasiveDebug Mask */\r
-#define ETM_ETMAUTHSTATUS_Reserved_Pos                        8                                                         /*!< ETM ETMAUTHSTATUS: Reserved Position */\r
-#define ETM_ETMAUTHSTATUS_Reserved_Msk                        (0x00ffffffUL << ETM_ETMAUTHSTATUS_Reserved_Pos)          /*!< ETM ETMAUTHSTATUS: Reserved Mask    */\r
-\r
-// -------------------------------------  ETM_ETMDEVTYPE  -----------------------------------------\r
-#define ETM_ETMDEVTYPE_MainType_Pos                           0                                                         /*!< ETM ETMDEVTYPE: MainType Position   */\r
-#define ETM_ETMDEVTYPE_MainType_Msk                           (0x0fUL << ETM_ETMDEVTYPE_MainType_Pos)                   /*!< ETM ETMDEVTYPE: MainType Mask       */\r
-#define ETM_ETMDEVTYPE_SubType_Pos                            4                                                         /*!< ETM ETMDEVTYPE: SubType Position    */\r
-#define ETM_ETMDEVTYPE_SubType_Msk                            (0x0fUL << ETM_ETMDEVTYPE_SubType_Pos)                    /*!< ETM ETMDEVTYPE: SubType Mask        */\r
-#define ETM_ETMDEVTYPE_Reserved_Pos                           8                                                         /*!< ETM ETMDEVTYPE: Reserved Position   */\r
-#define ETM_ETMDEVTYPE_Reserved_Msk                           (0x00ffffffUL << ETM_ETMDEVTYPE_Reserved_Pos)             /*!< ETM ETMDEVTYPE: Reserved Mask       */\r
-\r
-// --------------------------------------  ETM_ETMPIDR4  ------------------------------------------\r
-#define ETM_ETMPIDR4_JEP106ContinuationCode_Pos               0                                                         /*!< ETM ETMPIDR4: JEP106ContinuationCode Position */\r
-#define ETM_ETMPIDR4_JEP106ContinuationCode_Msk               (0x0fUL << ETM_ETMPIDR4_JEP106ContinuationCode_Pos)       /*!< ETM ETMPIDR4: JEP106ContinuationCode Mask */\r
-#define ETM_ETMPIDR4_Bitfield_4KBcount_Pos                    4                                                         /*!< ETM ETMPIDR4: Bitfield_4KBcount Position */\r
-#define ETM_ETMPIDR4_Bitfield_4KBcount_Msk                    (0x0fUL << ETM_ETMPIDR4_Bitfield_4KBcount_Pos)            /*!< ETM ETMPIDR4: Bitfield_4KBcount Mask */\r
-#define ETM_ETMPIDR4_Reserved_Pos                             8                                                         /*!< ETM ETMPIDR4: Reserved Position     */\r
-#define ETM_ETMPIDR4_Reserved_Msk                             (0x00ffffffUL << ETM_ETMPIDR4_Reserved_Pos)               /*!< ETM ETMPIDR4: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMPIDR5  ------------------------------------------\r
-#define ETM_ETMPIDR5_ReservedForFutureUse_Pos                 0                                                         /*!< ETM ETMPIDR5: ReservedForFutureUse Position */\r
-#define ETM_ETMPIDR5_ReservedForFutureUse_Msk                 (0x000000ffUL << ETM_ETMPIDR5_ReservedForFutureUse_Pos)   /*!< ETM ETMPIDR5: ReservedForFutureUse Mask */\r
-#define ETM_ETMPIDR5_Reserved_Pos                             8                                                         /*!< ETM ETMPIDR5: Reserved Position     */\r
-#define ETM_ETMPIDR5_Reserved_Msk                             (0x00ffffffUL << ETM_ETMPIDR5_Reserved_Pos)               /*!< ETM ETMPIDR5: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMPIDR6  ------------------------------------------\r
-#define ETM_ETMPIDR6_ReservedForFutureUse_Pos                 0                                                         /*!< ETM ETMPIDR6: ReservedForFutureUse Position */\r
-#define ETM_ETMPIDR6_ReservedForFutureUse_Msk                 (0x000000ffUL << ETM_ETMPIDR6_ReservedForFutureUse_Pos)   /*!< ETM ETMPIDR6: ReservedForFutureUse Mask */\r
-#define ETM_ETMPIDR6_Reserved_Pos                             8                                                         /*!< ETM ETMPIDR6: Reserved Position     */\r
-#define ETM_ETMPIDR6_Reserved_Msk                             (0x00ffffffUL << ETM_ETMPIDR6_Reserved_Pos)               /*!< ETM ETMPIDR6: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMPIDR7  ------------------------------------------\r
-#define ETM_ETMPIDR7_ReservedForFutureUse_Pos                 0                                                         /*!< ETM ETMPIDR7: ReservedForFutureUse Position */\r
-#define ETM_ETMPIDR7_ReservedForFutureUse_Msk                 (0x000000ffUL << ETM_ETMPIDR7_ReservedForFutureUse_Pos)   /*!< ETM ETMPIDR7: ReservedForFutureUse Mask */\r
-#define ETM_ETMPIDR7_Reserved_Pos                             8                                                         /*!< ETM ETMPIDR7: Reserved Position     */\r
-#define ETM_ETMPIDR7_Reserved_Msk                             (0x00ffffffUL << ETM_ETMPIDR7_Reserved_Pos)               /*!< ETM ETMPIDR7: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMPIDR0  ------------------------------------------\r
-#define ETM_ETMPIDR0_PartNumber_7_0_Pos                       0                                                         /*!< ETM ETMPIDR0: PartNumber_7_0 Position */\r
-#define ETM_ETMPIDR0_PartNumber_7_0_Msk                       (0x000000ffUL << ETM_ETMPIDR0_PartNumber_7_0_Pos)         /*!< ETM ETMPIDR0: PartNumber_7_0 Mask   */\r
-#define ETM_ETMPIDR0_Reserved_Pos                             8                                                         /*!< ETM ETMPIDR0: Reserved Position     */\r
-#define ETM_ETMPIDR0_Reserved_Msk                             (0x00ffffffUL << ETM_ETMPIDR0_Reserved_Pos)               /*!< ETM ETMPIDR0: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMPIDR1  ------------------------------------------\r
-#define ETM_ETMPIDR1_PartNumber_11_8_Pos                      0                                                         /*!< ETM ETMPIDR1: PartNumber_11_8 Position */\r
-#define ETM_ETMPIDR1_PartNumber_11_8_Msk                      (0x0fUL << ETM_ETMPIDR1_PartNumber_11_8_Pos)              /*!< ETM ETMPIDR1: PartNumber_11_8 Mask  */\r
-#define ETM_ETMPIDR1_JEP106IdentityCode_3_0_Pos               4                                                         /*!< ETM ETMPIDR1: JEP106IdentityCode_3_0 Position */\r
-#define ETM_ETMPIDR1_JEP106IdentityCode_3_0_Msk               (0x0fUL << ETM_ETMPIDR1_JEP106IdentityCode_3_0_Pos)       /*!< ETM ETMPIDR1: JEP106IdentityCode_3_0 Mask */\r
-#define ETM_ETMPIDR1_Reserved_Pos                             8                                                         /*!< ETM ETMPIDR1: Reserved Position     */\r
-#define ETM_ETMPIDR1_Reserved_Msk                             (0x00ffffffUL << ETM_ETMPIDR1_Reserved_Pos)               /*!< ETM ETMPIDR1: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMPIDR2  ------------------------------------------\r
-#define ETM_ETMPIDR2_JEP106IdentityCode_6_4_Pos               0                                                         /*!< ETM ETMPIDR2: JEP106IdentityCode_6_4 Position */\r
-#define ETM_ETMPIDR2_JEP106IdentityCode_6_4_Msk               (0x0fUL << ETM_ETMPIDR2_JEP106IdentityCode_6_4_Pos)       /*!< ETM ETMPIDR2: JEP106IdentityCode_6_4 Mask */\r
-#define ETM_ETMPIDR2_Always1_Pos                              4                                                         /*!< ETM ETMPIDR2: Always1 Position      */\r
-#define ETM_ETMPIDR2_Always1_Msk                              (0x01UL << ETM_ETMPIDR2_Always1_Pos)                      /*!< ETM ETMPIDR2: Always1 Mask          */\r
-#define ETM_ETMPIDR2_Revision_Pos                             5                                                         /*!< ETM ETMPIDR2: Revision Position     */\r
-#define ETM_ETMPIDR2_Revision_Msk                             (0x07UL << ETM_ETMPIDR2_Revision_Pos)                     /*!< ETM ETMPIDR2: Revision Mask         */\r
-#define ETM_ETMPIDR2_Reserved_Pos                             8                                                         /*!< ETM ETMPIDR2: Reserved Position     */\r
-#define ETM_ETMPIDR2_Reserved_Msk                             (0x00ffffffUL << ETM_ETMPIDR2_Reserved_Pos)               /*!< ETM ETMPIDR2: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMPIDR3  ------------------------------------------\r
-#define ETM_ETMPIDR3_CustomerModified_Pos                     0                                                         /*!< ETM ETMPIDR3: CustomerModified Position */\r
-#define ETM_ETMPIDR3_CustomerModified_Msk                     (0x0fUL << ETM_ETMPIDR3_CustomerModified_Pos)             /*!< ETM ETMPIDR3: CustomerModified Mask */\r
-#define ETM_ETMPIDR3_RevAnd_Pos                               4                                                         /*!< ETM ETMPIDR3: RevAnd Position       */\r
-#define ETM_ETMPIDR3_RevAnd_Msk                               (0x0fUL << ETM_ETMPIDR3_RevAnd_Pos)                       /*!< ETM ETMPIDR3: RevAnd Mask           */\r
-#define ETM_ETMPIDR3_Reserved_Pos                             8                                                         /*!< ETM ETMPIDR3: Reserved Position     */\r
-#define ETM_ETMPIDR3_Reserved_Msk                             (0x00ffffffUL << ETM_ETMPIDR3_Reserved_Pos)               /*!< ETM ETMPIDR3: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMCIDR0  ------------------------------------------\r
-#define ETM_ETMCIDR0_CID0_Pos                                 0                                                         /*!< ETM ETMCIDR0: CID0 Position         */\r
-#define ETM_ETMCIDR0_CID0_Msk                                 (0x000000ffUL << ETM_ETMCIDR0_CID0_Pos)                   /*!< ETM ETMCIDR0: CID0 Mask             */\r
-#define ETM_ETMCIDR0_Reserved_Pos                             8                                                         /*!< ETM ETMCIDR0: Reserved Position     */\r
-#define ETM_ETMCIDR0_Reserved_Msk                             (0x00ffffffUL << ETM_ETMCIDR0_Reserved_Pos)               /*!< ETM ETMCIDR0: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMCIDR1  ------------------------------------------\r
-#define ETM_ETMCIDR1_CID1_Pos                                 0                                                         /*!< ETM ETMCIDR1: CID1 Position         */\r
-#define ETM_ETMCIDR1_CID1_Msk                                 (0x000000ffUL << ETM_ETMCIDR1_CID1_Pos)                   /*!< ETM ETMCIDR1: CID1 Mask             */\r
-#define ETM_ETMCIDR1_Reserved_Pos                             8                                                         /*!< ETM ETMCIDR1: Reserved Position     */\r
-#define ETM_ETMCIDR1_Reserved_Msk                             (0x00ffffffUL << ETM_ETMCIDR1_Reserved_Pos)               /*!< ETM ETMCIDR1: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMCIDR2  ------------------------------------------\r
-#define ETM_ETMCIDR2_CID2_Pos                                 0                                                         /*!< ETM ETMCIDR2: CID2 Position         */\r
-#define ETM_ETMCIDR2_CID2_Msk                                 (0x000000ffUL << ETM_ETMCIDR2_CID2_Pos)                   /*!< ETM ETMCIDR2: CID2 Mask             */\r
-#define ETM_ETMCIDR2_Reserved_Pos                             8                                                         /*!< ETM ETMCIDR2: Reserved Position     */\r
-#define ETM_ETMCIDR2_Reserved_Msk                             (0x00ffffffUL << ETM_ETMCIDR2_Reserved_Pos)               /*!< ETM ETMCIDR2: Reserved Mask         */\r
-\r
-// --------------------------------------  ETM_ETMCIDR3  ------------------------------------------\r
-#define ETM_ETMCIDR3_CID3_Pos                                 0                                                         /*!< ETM ETMCIDR3: CID3 Position         */\r
-#define ETM_ETMCIDR3_CID3_Msk                                 (0x000000ffUL << ETM_ETMCIDR3_CID3_Pos)                   /*!< ETM ETMCIDR3: CID3 Mask             */\r
-#define ETM_ETMCIDR3_Reserved_Pos                             8                                                         /*!< ETM ETMCIDR3: Reserved Position     */\r
-#define ETM_ETMCIDR3_Reserved_Msk                             (0x00ffffffUL << ETM_ETMCIDR3_Reserved_Pos)               /*!< ETM ETMCIDR3: Reserved Mask         */\r
-\r
-\r
-\r
-/***   FCE Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* FCE_CLC  =  Clock Control Register*/\r
-#define   FCE_CLC_DISR_Pos     (0U)\r
-#define   FCE_CLC_DISR_Msk     (0x00000001U  << FCE_CLC_DISR_Pos)\r
-\r
-#define   FCE_CLC_DISS_Pos     (1U)\r
-#define   FCE_CLC_DISS_Msk     (0x00000001U  << FCE_CLC_DISS_Pos)\r
-\r
-/* FCE_ID  =  Module Identification Register*/\r
-#define   FCE_ID_MOD_REV_Pos   (0U)\r
-#define   FCE_ID_MOD_REV_Msk   (0x000000FFU  << FCE_ID_MOD_REV_Pos)\r
-\r
-#define   FCE_ID_MOD_TYPE_Pos          (8U)\r
-#define   FCE_ID_MOD_TYPE_Msk          (0x000000FFU  << FCE_ID_MOD_TYPE_Pos)\r
-\r
-#define   FCE_ID_MOD_NUMBER_Pos        (16U)\r
-#define   FCE_ID_MOD_NUMBER_Msk        (0x0000FFFFU  << FCE_ID_MOD_NUMBER_Pos)\r
-\r
-/* FCE_KE_IRx  =  Input Register 0*/\r
-#define   FCE_KE_IR_IR_Pos     (0U)\r
-#define   FCE_KE_IR_IR_Msk     (0xFFFFFFFFU  << FCE_KE_IR_IR_Pos)\r
-\r
-/* FCE_KE_RESx  =  CRC Result Register 0*/\r
-#define   FCE_KE_RES_RES_Pos   (0U)\r
-#define   FCE_KE_RES_RES_Msk   (0xFFFFFFFFU  << FCE_KE_RES_RES_Pos)\r
-\r
-/* FCE_KE_CFGx  =  CRC Configuration Register 0*/\r
-#define   FCE_KE_CFG_CMI_Pos   (0U)\r
-#define   FCE_KE_CFG_CMI_Msk   (0x00000001U  << FCE_KE_CFG_CMI_Pos)\r
-\r
-#define   FCE_KE_CFG_CEI_Pos   (1U)\r
-#define   FCE_KE_CFG_CEI_Msk   (0x00000001U  << FCE_KE_CFG_CEI_Pos)\r
-\r
-#define   FCE_KE_CFG_LEI_Pos   (2U)\r
-#define   FCE_KE_CFG_LEI_Msk   (0x00000001U  << FCE_KE_CFG_LEI_Pos)\r
-\r
-#define   FCE_KE_CFG_BEI_Pos   (3U)\r
-#define   FCE_KE_CFG_BEI_Msk   (0x00000001U  << FCE_KE_CFG_BEI_Pos)\r
-\r
-#define   FCE_KE_CFG_CCE_Pos   (4U)\r
-#define   FCE_KE_CFG_CCE_Msk   (0x00000001U  << FCE_KE_CFG_CCE_Pos)\r
-\r
-#define   FCE_KE_CFG_ALR_Pos   (5U)\r
-#define   FCE_KE_CFG_ALR_Msk   (0x00000001U  << FCE_KE_CFG_ALR_Pos)\r
-\r
-#define   FCE_KE_CFG_REFIN_Pos         (8U)\r
-#define   FCE_KE_CFG_REFIN_Msk         (0x00000001U  << FCE_KE_CFG_REFIN_Pos)\r
-\r
-#define   FCE_KE_CFG_REFOUT_Pos        (9U)\r
-#define   FCE_KE_CFG_REFOUT_Msk        (0x00000001U  << FCE_KE_CFG_REFOUT_Pos)\r
-\r
-#define   FCE_KE_CFG_XSEL_Pos          (10U)\r
-#define   FCE_KE_CFG_XSEL_Msk          (0x00000001U  << FCE_KE_CFG_XSEL_Pos)\r
-\r
-/* FCE_KE_STSx  =  CRC Status Register 0*/\r
-#define   FCE_KE_STS_CMF_Pos   (0U)\r
-#define   FCE_KE_STS_CMF_Msk   (0x00000001U  << FCE_KE_STS_CMF_Pos)\r
-\r
-#define   FCE_KE_STS_CEF_Pos   (1U)\r
-#define   FCE_KE_STS_CEF_Msk   (0x00000001U  << FCE_KE_STS_CEF_Pos)\r
-\r
-#define   FCE_KE_STS_LEF_Pos   (2U)\r
-#define   FCE_KE_STS_LEF_Msk   (0x00000001U  << FCE_KE_STS_LEF_Pos)\r
-\r
-#define   FCE_KE_STS_BEF_Pos   (3U)\r
-#define   FCE_KE_STS_BEF_Msk   (0x00000001U  << FCE_KE_STS_BEF_Pos)\r
-\r
-/* FCE_KE_LENGTHx  =  CRC Length Register 0*/\r
-#define   FCE_KE_LENGTH_LENGTH_Pos     (0U)\r
-#define   FCE_KE_LENGTH_LENGTH_Msk     (0x0000FFFFU  << FCE_KE_LENGTH_LENGTH_Pos)\r
-\r
-/* FCE_KE_CHECKx  =  CRC Check Register 0*/\r
-#define   FCE_KE_CHECK_CHECK_Pos       (0U)\r
-#define   FCE_KE_CHECK_CHECK_Msk       (0xFFFFFFFFU  << FCE_KE_CHECK_CHECK_Pos)\r
-\r
-/* FCE_KE_CRCx  =  CRC Register 0*/\r
-#define   FCE_KE_CRC_CRC_Pos   (0U)\r
-#define   FCE_KE_CRC_CRC_Msk   (0xFFFFFFFFU  << FCE_KE_CRC_CRC_Pos)\r
-\r
-/* FCE_KE_CTRx  =  CRC Test Register 0*/\r
-#define   FCE_KE_CTR_FCM_Pos   (0U)\r
-#define   FCE_KE_CTR_FCM_Msk   (0x00000001U  << FCE_KE_CTR_FCM_Pos)\r
-\r
-#define   FCE_KE_CTR_FRM_CFG_Pos       (1U)\r
-#define   FCE_KE_CTR_FRM_CFG_Msk       (0x00000001U  << FCE_KE_CTR_FRM_CFG_Pos)\r
-\r
-#define   FCE_KE_CTR_FRM_CHECK_Pos     (2U)\r
-#define   FCE_KE_CTR_FRM_CHECK_Msk     (0x00000001U  << FCE_KE_CTR_FRM_CHECK_Pos)\r
-\r
-\r
-\r
-/***   FLASH0 Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* FLASH_ID  =  Flash Module Identification Register*/\r
-#define   FLASH_ID_MOD_REV_Pos         (0U)\r
-#define   FLASH_ID_MOD_REV_Msk         (0x000000FFU  << FLASH_ID_MOD_REV_Pos)\r
-\r
-#define   FLASH_ID_MOD_TYPE_Pos        (8U)\r
-#define   FLASH_ID_MOD_TYPE_Msk        (0x000000FFU  << FLASH_ID_MOD_TYPE_Pos)\r
-\r
-#define   FLASH_ID_MOD_NUMBER_Pos      (16U)\r
-#define   FLASH_ID_MOD_NUMBER_Msk      (0x0000FFFFU  << FLASH_ID_MOD_NUMBER_Pos)\r
-\r
-/* FLASH_FSR  =  Flash Status Register*/\r
-#define   FLASH_FSR_PBUSY_Pos          (0U)\r
-#define   FLASH_FSR_PBUSY_Msk          (0x00000001U  << FLASH_FSR_PBUSY_Pos)\r
-\r
-#define   FLASH_FSR_FABUSY_Pos         (1U)\r
-#define   FLASH_FSR_FABUSY_Msk         (0x00000001U  << FLASH_FSR_FABUSY_Pos)\r
-\r
-#define   FLASH_FSR_PROG_Pos   (4U)\r
-#define   FLASH_FSR_PROG_Msk   (0x00000001U  << FLASH_FSR_PROG_Pos)\r
-\r
-#define   FLASH_FSR_ERASE_Pos          (5U)\r
-#define   FLASH_FSR_ERASE_Msk          (0x00000001U  << FLASH_FSR_ERASE_Pos)\r
-\r
-#define   FLASH_FSR_PFPAGE_Pos         (6U)\r
-#define   FLASH_FSR_PFPAGE_Msk         (0x00000001U  << FLASH_FSR_PFPAGE_Pos)\r
-\r
-#define   FLASH_FSR_PFOPER_Pos         (8U)\r
-#define   FLASH_FSR_PFOPER_Msk         (0x00000001U  << FLASH_FSR_PFOPER_Pos)\r
-\r
-#define   FLASH_FSR_SQER_Pos   (10U)\r
-#define   FLASH_FSR_SQER_Msk   (0x00000001U  << FLASH_FSR_SQER_Pos)\r
-\r
-#define   FLASH_FSR_PROER_Pos          (11U)\r
-#define   FLASH_FSR_PROER_Msk          (0x00000001U  << FLASH_FSR_PROER_Pos)\r
-\r
-#define   FLASH_FSR_PFSBER_Pos         (12U)\r
-#define   FLASH_FSR_PFSBER_Msk         (0x00000001U  << FLASH_FSR_PFSBER_Pos)\r
-\r
-#define   FLASH_FSR_PFDBER_Pos         (14U)\r
-#define   FLASH_FSR_PFDBER_Msk         (0x00000001U  << FLASH_FSR_PFDBER_Pos)\r
-\r
-#define   FLASH_FSR_PROIN_Pos          (16U)\r
-#define   FLASH_FSR_PROIN_Msk          (0x00000001U  << FLASH_FSR_PROIN_Pos)\r
-\r
-#define   FLASH_FSR_RPROIN_Pos         (18U)\r
-#define   FLASH_FSR_RPROIN_Msk         (0x00000001U  << FLASH_FSR_RPROIN_Pos)\r
-\r
-#define   FLASH_FSR_RPRODIS_Pos        (19U)\r
-#define   FLASH_FSR_RPRODIS_Msk        (0x00000001U  << FLASH_FSR_RPRODIS_Pos)\r
-\r
-#define   FLASH_FSR_WPROIN0_Pos        (21U)\r
-#define   FLASH_FSR_WPROIN0_Msk        (0x00000001U  << FLASH_FSR_WPROIN0_Pos)\r
-\r
-#define   FLASH_FSR_WPROIN1_Pos        (22U)\r
-#define   FLASH_FSR_WPROIN1_Msk        (0x00000001U  << FLASH_FSR_WPROIN1_Pos)\r
-\r
-#define   FLASH_FSR_WPROIN2_Pos        (23U)\r
-#define   FLASH_FSR_WPROIN2_Msk        (0x00000001U  << FLASH_FSR_WPROIN2_Pos)\r
-\r
-#define   FLASH_FSR_WPRODIS0_Pos       (25U)\r
-#define   FLASH_FSR_WPRODIS0_Msk       (0x00000001U  << FLASH_FSR_WPRODIS0_Pos)\r
-\r
-#define   FLASH_FSR_WPRODIS1_Pos       (26U)\r
-#define   FLASH_FSR_WPRODIS1_Msk       (0x00000001U  << FLASH_FSR_WPRODIS1_Pos)\r
-\r
-#define   FLASH_FSR_SLM_Pos    (28U)\r
-#define   FLASH_FSR_SLM_Msk    (0x00000001U  << FLASH_FSR_SLM_Pos)\r
-\r
-#define   FLASH_FSR_X_Pos      (30U)\r
-#define   FLASH_FSR_X_Msk      (0x00000001U  << FLASH_FSR_X_Pos)\r
-\r
-#define   FLASH_FSR_VER_Pos    (31U)\r
-#define   FLASH_FSR_VER_Msk    (0x00000001U  << FLASH_FSR_VER_Pos)\r
-\r
-/* FLASH_FCON  =  Flash Configuration Register*/\r
-#define   FLASH_FCON_WSPFLASH_Pos      (0U)\r
-#define   FLASH_FCON_WSPFLASH_Msk      (0x0000000FU  << FLASH_FCON_WSPFLASH_Pos)\r
-\r
-#define   FLASH_FCON_WSECPF_Pos        (4U)\r
-#define   FLASH_FCON_WSECPF_Msk        (0x00000001U  << FLASH_FCON_WSECPF_Pos)\r
-\r
-#define   FLASH_FCON_IDLE_Pos          (13U)\r
-#define   FLASH_FCON_IDLE_Msk          (0x00000001U  << FLASH_FCON_IDLE_Pos)\r
-\r
-#define   FLASH_FCON_ESLDIS_Pos        (14U)\r
-#define   FLASH_FCON_ESLDIS_Msk        (0x00000001U  << FLASH_FCON_ESLDIS_Pos)\r
-\r
-#define   FLASH_FCON_SLEEP_Pos         (15U)\r
-#define   FLASH_FCON_SLEEP_Msk         (0x00000001U  << FLASH_FCON_SLEEP_Pos)\r
-\r
-#define   FLASH_FCON_RPA_Pos   (16U)\r
-#define   FLASH_FCON_RPA_Msk   (0x00000001U  << FLASH_FCON_RPA_Pos)\r
-\r
-#define   FLASH_FCON_DCF_Pos   (17U)\r
-#define   FLASH_FCON_DCF_Msk   (0x00000001U  << FLASH_FCON_DCF_Pos)\r
-\r
-#define   FLASH_FCON_DDF_Pos   (18U)\r
-#define   FLASH_FCON_DDF_Msk   (0x00000001U  << FLASH_FCON_DDF_Pos)\r
-\r
-#define   FLASH_FCON_VOPERM_Pos        (24U)\r
-#define   FLASH_FCON_VOPERM_Msk        (0x00000001U  << FLASH_FCON_VOPERM_Pos)\r
-\r
-#define   FLASH_FCON_SQERM_Pos         (25U)\r
-#define   FLASH_FCON_SQERM_Msk         (0x00000001U  << FLASH_FCON_SQERM_Pos)\r
-\r
-#define   FLASH_FCON_PROERM_Pos        (26U)\r
-#define   FLASH_FCON_PROERM_Msk        (0x00000001U  << FLASH_FCON_PROERM_Pos)\r
-\r
-#define   FLASH_FCON_PFSBERM_Pos       (27U)\r
-#define   FLASH_FCON_PFSBERM_Msk       (0x00000001U  << FLASH_FCON_PFSBERM_Pos)\r
-\r
-#define   FLASH_FCON_PFDBERM_Pos       (29U)\r
-#define   FLASH_FCON_PFDBERM_Msk       (0x00000001U  << FLASH_FCON_PFDBERM_Pos)\r
-\r
-#define   FLASH_FCON_EOBM_Pos          (31U)\r
-#define   FLASH_FCON_EOBM_Msk          (0x00000001U  << FLASH_FCON_EOBM_Pos)\r
-\r
-/* FLASH_MARP  =  Margin Control Register PFLASH*/\r
-#define   FLASH_MARP_MARGIN_Pos        (0U)\r
-#define   FLASH_MARP_MARGIN_Msk        (0x0000000FU  << FLASH_MARP_MARGIN_Pos)\r
-\r
-#define   FLASH_MARP_TRAPDIS_Pos       (15U)\r
-#define   FLASH_MARP_TRAPDIS_Msk       (0x00000001U  << FLASH_MARP_TRAPDIS_Pos)\r
-\r
-/* FLASH_PROCON0  =  Flash Protection Configuration Register User 0*/\r
-#define   FLASH_PROCON0_S0L_Pos        (0U)\r
-#define   FLASH_PROCON0_S0L_Msk        (0x00000001U  << FLASH_PROCON0_S0L_Pos)\r
-\r
-#define   FLASH_PROCON0_S1L_Pos        (1U)\r
-#define   FLASH_PROCON0_S1L_Msk        (0x00000001U  << FLASH_PROCON0_S1L_Pos)\r
-\r
-#define   FLASH_PROCON0_S2L_Pos        (2U)\r
-#define   FLASH_PROCON0_S2L_Msk        (0x00000001U  << FLASH_PROCON0_S2L_Pos)\r
-\r
-#define   FLASH_PROCON0_S3L_Pos        (3U)\r
-#define   FLASH_PROCON0_S3L_Msk        (0x00000001U  << FLASH_PROCON0_S3L_Pos)\r
-\r
-#define   FLASH_PROCON0_S4L_Pos        (4U)\r
-#define   FLASH_PROCON0_S4L_Msk        (0x00000001U  << FLASH_PROCON0_S4L_Pos)\r
-\r
-#define   FLASH_PROCON0_S5L_Pos        (5U)\r
-#define   FLASH_PROCON0_S5L_Msk        (0x00000001U  << FLASH_PROCON0_S5L_Pos)\r
-\r
-#define   FLASH_PROCON0_S6L_Pos        (6U)\r
-#define   FLASH_PROCON0_S6L_Msk        (0x00000001U  << FLASH_PROCON0_S6L_Pos)\r
-\r
-#define   FLASH_PROCON0_S7L_Pos        (7U)\r
-#define   FLASH_PROCON0_S7L_Msk        (0x00000001U  << FLASH_PROCON0_S7L_Pos)\r
-\r
-#define   FLASH_PROCON0_S8L_Pos        (8U)\r
-#define   FLASH_PROCON0_S8L_Msk        (0x00000001U  << FLASH_PROCON0_S8L_Pos)\r
-\r
-#define   FLASH_PROCON0_S9L_Pos        (9U)\r
-#define   FLASH_PROCON0_S9L_Msk        (0x00000001U  << FLASH_PROCON0_S9L_Pos)\r
-\r
-#define   FLASH_PROCON0_S10_S11L_Pos   (10U)\r
-#define   FLASH_PROCON0_S10_S11L_Msk   (0x00000001U  << FLASH_PROCON0_S10_S11L_Pos)\r
-\r
-#define   FLASH_PROCON0_RPRO_Pos       (15U)\r
-#define   FLASH_PROCON0_RPRO_Msk       (0x00000001U  << FLASH_PROCON0_RPRO_Pos)\r
-\r
-/* FLASH_PROCON1  =  Flash Protection Configuration Register User 1*/\r
-#define   FLASH_PROCON1_S0L_Pos        (0U)\r
-#define   FLASH_PROCON1_S0L_Msk        (0x00000001U  << FLASH_PROCON1_S0L_Pos)\r
-\r
-#define   FLASH_PROCON1_S1L_Pos        (1U)\r
-#define   FLASH_PROCON1_S1L_Msk        (0x00000001U  << FLASH_PROCON1_S1L_Pos)\r
-\r
-#define   FLASH_PROCON1_S2L_Pos        (2U)\r
-#define   FLASH_PROCON1_S2L_Msk        (0x00000001U  << FLASH_PROCON1_S2L_Pos)\r
-\r
-#define   FLASH_PROCON1_S3L_Pos        (3U)\r
-#define   FLASH_PROCON1_S3L_Msk        (0x00000001U  << FLASH_PROCON1_S3L_Pos)\r
-\r
-#define   FLASH_PROCON1_S4L_Pos        (4U)\r
-#define   FLASH_PROCON1_S4L_Msk        (0x00000001U  << FLASH_PROCON1_S4L_Pos)\r
-\r
-#define   FLASH_PROCON1_S5L_Pos        (5U)\r
-#define   FLASH_PROCON1_S5L_Msk        (0x00000001U  << FLASH_PROCON1_S5L_Pos)\r
-\r
-#define   FLASH_PROCON1_S6L_Pos        (6U)\r
-#define   FLASH_PROCON1_S6L_Msk        (0x00000001U  << FLASH_PROCON1_S6L_Pos)\r
-\r
-#define   FLASH_PROCON1_S7L_Pos        (7U)\r
-#define   FLASH_PROCON1_S7L_Msk        (0x00000001U  << FLASH_PROCON1_S7L_Pos)\r
-\r
-#define   FLASH_PROCON1_S8L_Pos        (8U)\r
-#define   FLASH_PROCON1_S8L_Msk        (0x00000001U  << FLASH_PROCON1_S8L_Pos)\r
-\r
-#define   FLASH_PROCON1_S9L_Pos        (9U)\r
-#define   FLASH_PROCON1_S9L_Msk        (0x00000001U  << FLASH_PROCON1_S9L_Pos)\r
-\r
-#define   FLASH_PROCON1_S10_S11L_Pos   (10U)\r
-#define   FLASH_PROCON1_S10_S11L_Msk   (0x00000001U  << FLASH_PROCON1_S10_S11L_Pos)\r
-\r
-/* FLASH_PROCON2  =  Flash Protection Configuration Register User 2*/\r
-#define   FLASH_PROCON2_S0ROM_Pos      (0U)\r
-#define   FLASH_PROCON2_S0ROM_Msk      (0x00000001U  << FLASH_PROCON2_S0ROM_Pos)\r
-\r
-#define   FLASH_PROCON2_S1ROM_Pos      (1U)\r
-#define   FLASH_PROCON2_S1ROM_Msk      (0x00000001U  << FLASH_PROCON2_S1ROM_Pos)\r
-\r
-#define   FLASH_PROCON2_S2ROM_Pos      (2U)\r
-#define   FLASH_PROCON2_S2ROM_Msk      (0x00000001U  << FLASH_PROCON2_S2ROM_Pos)\r
-\r
-#define   FLASH_PROCON2_S3ROM_Pos      (3U)\r
-#define   FLASH_PROCON2_S3ROM_Msk      (0x00000001U  << FLASH_PROCON2_S3ROM_Pos)\r
-\r
-#define   FLASH_PROCON2_S4ROM_Pos      (4U)\r
-#define   FLASH_PROCON2_S4ROM_Msk      (0x00000001U  << FLASH_PROCON2_S4ROM_Pos)\r
-\r
-#define   FLASH_PROCON2_S5ROM_Pos      (5U)\r
-#define   FLASH_PROCON2_S5ROM_Msk      (0x00000001U  << FLASH_PROCON2_S5ROM_Pos)\r
-\r
-#define   FLASH_PROCON2_S6ROM_Pos      (6U)\r
-#define   FLASH_PROCON2_S6ROM_Msk      (0x00000001U  << FLASH_PROCON2_S6ROM_Pos)\r
-\r
-#define   FLASH_PROCON2_S7ROM_Pos      (7U)\r
-#define   FLASH_PROCON2_S7ROM_Msk      (0x00000001U  << FLASH_PROCON2_S7ROM_Pos)\r
-\r
-#define   FLASH_PROCON2_S8ROM_Pos      (8U)\r
-#define   FLASH_PROCON2_S8ROM_Msk      (0x00000001U  << FLASH_PROCON2_S8ROM_Pos)\r
-\r
-#define   FLASH_PROCON2_S9ROM_Pos      (9U)\r
-#define   FLASH_PROCON2_S9ROM_Msk      (0x00000001U  << FLASH_PROCON2_S9ROM_Pos)\r
-\r
-#define   FLASH_PROCON2_S10_S11ROM_Pos         (10U)\r
-#define   FLASH_PROCON2_S10_S11ROM_Msk         (0x00000001U  << FLASH_PROCON2_S10_S11ROM_Pos)\r
-\r
-\r
-\r
-/***   FPB Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-// ---------------------------------------  FPB_FP_CTRL  ------------------------------------------\r
-#define FPB_FP_CTRL_ENABLE_Pos                                0                                                         /*!< FPB FP_CTRL: ENABLE Position        */\r
-#define FPB_FP_CTRL_ENABLE_Msk                                (0x01UL << FPB_FP_CTRL_ENABLE_Pos)                        /*!< FPB FP_CTRL: ENABLE Mask            */\r
-#define FPB_FP_CTRL_KEY_Pos                                   1                                                         /*!< FPB FP_CTRL: KEY Position           */\r
-#define FPB_FP_CTRL_KEY_Msk                                   (0x01UL << FPB_FP_CTRL_KEY_Pos)                           /*!< FPB FP_CTRL: KEY Mask               */\r
-#define FPB_FP_CTRL_Reserved_Pos                              2                                                         /*!< FPB FP_CTRL: Reserved Position      */\r
-#define FPB_FP_CTRL_Reserved_Msk                              (0x03UL << FPB_FP_CTRL_Reserved_Pos)                      /*!< FPB FP_CTRL: Reserved Mask          */\r
-#define FPB_FP_CTRL_NUM_CODE_3_0_Pos                          4                                                         /*!< FPB FP_CTRL: NUM_CODE_3_0 Position  */\r
-#define FPB_FP_CTRL_NUM_CODE_3_0_Msk                          (0x0fUL << FPB_FP_CTRL_NUM_CODE_3_0_Pos)                  /*!< FPB FP_CTRL: NUM_CODE_3_0 Mask      */\r
-#define FPB_FP_CTRL_NUM_LIT_Pos                               8                                                         /*!< FPB FP_CTRL: NUM_LIT Position       */\r
-#define FPB_FP_CTRL_NUM_LIT_Msk                               (0x0fUL << FPB_FP_CTRL_NUM_LIT_Pos)                       /*!< FPB FP_CTRL: NUM_LIT Mask           */\r
-#define FPB_FP_CTRL_NUM_CODE_6_4_Pos                          12                                                        /*!< FPB FP_CTRL: NUM_CODE_6_4 Position  */\r
-#define FPB_FP_CTRL_NUM_CODE_6_4_Msk                          (0x07UL << FPB_FP_CTRL_NUM_CODE_6_4_Pos)                  /*!< FPB FP_CTRL: NUM_CODE_6_4 Mask      */\r
-#define FPB_FP_CTRL_Reserved1_Pos                             15                                                        /*!< FPB FP_CTRL: Reserved1 Position     */\r
-#define FPB_FP_CTRL_Reserved1_Msk                             (0x0001ffffUL << FPB_FP_CTRL_Reserved1_Pos)               /*!< FPB FP_CTRL: Reserved1 Mask         */\r
-\r
-// --------------------------------------  FPB_FP_REMAP  ------------------------------------------\r
-#define FPB_FP_REMAP_Reserved_Pos                             0                                                         /*!< FPB FP_REMAP: Reserved Position     */\r
-#define FPB_FP_REMAP_Reserved_Msk                             (0x1fUL << FPB_FP_REMAP_Reserved_Pos)                     /*!< FPB FP_REMAP: Reserved Mask         */\r
-#define FPB_FP_REMAP_REMAP_Pos                                5                                                         /*!< FPB FP_REMAP: REMAP Position        */\r
-#define FPB_FP_REMAP_REMAP_Msk                                (0x00ffffffUL << FPB_FP_REMAP_REMAP_Pos)                  /*!< FPB FP_REMAP: REMAP Mask            */\r
-#define FPB_FP_REMAP_RMPSPT_Pos                               29                                                        /*!< FPB FP_REMAP: RMPSPT Position       */\r
-#define FPB_FP_REMAP_RMPSPT_Msk                               (0x01UL << FPB_FP_REMAP_RMPSPT_Pos)                       /*!< FPB FP_REMAP: RMPSPT Mask           */\r
-#define FPB_FP_REMAP_Reserved1_Pos                            30                                                        /*!< FPB FP_REMAP: Reserved1 Position    */\r
-#define FPB_FP_REMAP_Reserved1_Msk                            (0x03UL << FPB_FP_REMAP_Reserved1_Pos)                    /*!< FPB FP_REMAP: Reserved1 Mask        */\r
-\r
-// --------------------------------------  FPB_FP_COMP0  ------------------------------------------\r
-#define FPB_FP_COMP0_ENABLE_Pos                               0                                                         /*!< FPB FP_COMP0: ENABLE Position       */\r
-#define FPB_FP_COMP0_ENABLE_Msk                               (0x01UL << FPB_FP_COMP0_ENABLE_Pos)                       /*!< FPB FP_COMP0: ENABLE Mask           */\r
-#define FPB_FP_COMP0_Reserved_Pos                             1                                                         /*!< FPB FP_COMP0: Reserved Position     */\r
-#define FPB_FP_COMP0_Reserved_Msk                             (0x01UL << FPB_FP_COMP0_Reserved_Pos)                     /*!< FPB FP_COMP0: Reserved Mask         */\r
-#define FPB_FP_COMP0_COMP_Pos                                 2                                                         /*!< FPB FP_COMP0: COMP Position         */\r
-#define FPB_FP_COMP0_COMP_Msk                                 (0x07ffffffUL << FPB_FP_COMP0_COMP_Pos)                   /*!< FPB FP_COMP0: COMP Mask             */\r
-#define FPB_FP_COMP0_Reserved1_Pos                            29                                                        /*!< FPB FP_COMP0: Reserved1 Position    */\r
-#define FPB_FP_COMP0_Reserved1_Msk                            (0x01UL << FPB_FP_COMP0_Reserved1_Pos)                    /*!< FPB FP_COMP0: Reserved1 Mask        */\r
-#define FPB_FP_COMP0_REPLACE_Pos                              30                                                        /*!< FPB FP_COMP0: REPLACE Position      */\r
-#define FPB_FP_COMP0_REPLACE_Msk                              (0x03UL << FPB_FP_COMP0_REPLACE_Pos)                      /*!< FPB FP_COMP0: REPLACE Mask          */\r
-\r
-// --------------------------------------  FPB_FP_COMP1  ------------------------------------------\r
-#define FPB_FP_COMP1_ENABLE_Pos                               0                                                         /*!< FPB FP_COMP1: ENABLE Position       */\r
-#define FPB_FP_COMP1_ENABLE_Msk                               (0x01UL << FPB_FP_COMP1_ENABLE_Pos)                       /*!< FPB FP_COMP1: ENABLE Mask           */\r
-#define FPB_FP_COMP1_Reserved_Pos                             1                                                         /*!< FPB FP_COMP1: Reserved Position     */\r
-#define FPB_FP_COMP1_Reserved_Msk                             (0x01UL << FPB_FP_COMP1_Reserved_Pos)                     /*!< FPB FP_COMP1: Reserved Mask         */\r
-#define FPB_FP_COMP1_COMP_Pos                                 2                                                         /*!< FPB FP_COMP1: COMP Position         */\r
-#define FPB_FP_COMP1_COMP_Msk                                 (0x07ffffffUL << FPB_FP_COMP1_COMP_Pos)                   /*!< FPB FP_COMP1: COMP Mask             */\r
-#define FPB_FP_COMP1_Reserved1_Pos                            29                                                        /*!< FPB FP_COMP1: Reserved1 Position    */\r
-#define FPB_FP_COMP1_Reserved1_Msk                            (0x01UL << FPB_FP_COMP1_Reserved1_Pos)                    /*!< FPB FP_COMP1: Reserved1 Mask        */\r
-#define FPB_FP_COMP1_REPLACE_Pos                              30                                                        /*!< FPB FP_COMP1: REPLACE Position      */\r
-#define FPB_FP_COMP1_REPLACE_Msk                              (0x03UL << FPB_FP_COMP1_REPLACE_Pos)                      /*!< FPB FP_COMP1: REPLACE Mask          */\r
-\r
-// --------------------------------------  FPB_FP_COMP2  ------------------------------------------\r
-#define FPB_FP_COMP2_ENABLE_Pos                               0                                                         /*!< FPB FP_COMP2: ENABLE Position       */\r
-#define FPB_FP_COMP2_ENABLE_Msk                               (0x01UL << FPB_FP_COMP2_ENABLE_Pos)                       /*!< FPB FP_COMP2: ENABLE Mask           */\r
-#define FPB_FP_COMP2_Reserved_Pos                             1                                                         /*!< FPB FP_COMP2: Reserved Position     */\r
-#define FPB_FP_COMP2_Reserved_Msk                             (0x01UL << FPB_FP_COMP2_Reserved_Pos)                     /*!< FPB FP_COMP2: Reserved Mask         */\r
-#define FPB_FP_COMP2_COMP_Pos                                 2                                                         /*!< FPB FP_COMP2: COMP Position         */\r
-#define FPB_FP_COMP2_COMP_Msk                                 (0x07ffffffUL << FPB_FP_COMP2_COMP_Pos)                   /*!< FPB FP_COMP2: COMP Mask             */\r
-#define FPB_FP_COMP2_Reserved1_Pos                            29                                                        /*!< FPB FP_COMP2: Reserved1 Position    */\r
-#define FPB_FP_COMP2_Reserved1_Msk                            (0x01UL << FPB_FP_COMP2_Reserved1_Pos)                    /*!< FPB FP_COMP2: Reserved1 Mask        */\r
-#define FPB_FP_COMP2_REPLACE_Pos                              30                                                        /*!< FPB FP_COMP2: REPLACE Position      */\r
-#define FPB_FP_COMP2_REPLACE_Msk                              (0x03UL << FPB_FP_COMP2_REPLACE_Pos)                      /*!< FPB FP_COMP2: REPLACE Mask          */\r
-\r
-// --------------------------------------  FPB_FP_COMP3  ------------------------------------------\r
-#define FPB_FP_COMP3_ENABLE_Pos                               0                                                         /*!< FPB FP_COMP3: ENABLE Position       */\r
-#define FPB_FP_COMP3_ENABLE_Msk                               (0x01UL << FPB_FP_COMP3_ENABLE_Pos)                       /*!< FPB FP_COMP3: ENABLE Mask           */\r
-#define FPB_FP_COMP3_Reserved_Pos                             1                                                         /*!< FPB FP_COMP3: Reserved Position     */\r
-#define FPB_FP_COMP3_Reserved_Msk                             (0x01UL << FPB_FP_COMP3_Reserved_Pos)                     /*!< FPB FP_COMP3: Reserved Mask         */\r
-#define FPB_FP_COMP3_COMP_Pos                                 2                                                         /*!< FPB FP_COMP3: COMP Position         */\r
-#define FPB_FP_COMP3_COMP_Msk                                 (0x07ffffffUL << FPB_FP_COMP3_COMP_Pos)                   /*!< FPB FP_COMP3: COMP Mask             */\r
-#define FPB_FP_COMP3_Reserved1_Pos                            29                                                        /*!< FPB FP_COMP3: Reserved1 Position    */\r
-#define FPB_FP_COMP3_Reserved1_Msk                            (0x01UL << FPB_FP_COMP3_Reserved1_Pos)                    /*!< FPB FP_COMP3: Reserved1 Mask        */\r
-#define FPB_FP_COMP3_REPLACE_Pos                              30                                                        /*!< FPB FP_COMP3: REPLACE Position      */\r
-#define FPB_FP_COMP3_REPLACE_Msk                              (0x03UL << FPB_FP_COMP3_REPLACE_Pos)                      /*!< FPB FP_COMP3: REPLACE Mask          */\r
-\r
-// --------------------------------------  FPB_FP_COMP4  ------------------------------------------\r
-#define FPB_FP_COMP4_ENABLE_Pos                               0                                                         /*!< FPB FP_COMP4: ENABLE Position       */\r
-#define FPB_FP_COMP4_ENABLE_Msk                               (0x01UL << FPB_FP_COMP4_ENABLE_Pos)                       /*!< FPB FP_COMP4: ENABLE Mask           */\r
-#define FPB_FP_COMP4_Reserved_Pos                             1                                                         /*!< FPB FP_COMP4: Reserved Position     */\r
-#define FPB_FP_COMP4_Reserved_Msk                             (0x01UL << FPB_FP_COMP4_Reserved_Pos)                     /*!< FPB FP_COMP4: Reserved Mask         */\r
-#define FPB_FP_COMP4_COMP_Pos                                 2                                                         /*!< FPB FP_COMP4: COMP Position         */\r
-#define FPB_FP_COMP4_COMP_Msk                                 (0x07ffffffUL << FPB_FP_COMP4_COMP_Pos)                   /*!< FPB FP_COMP4: COMP Mask             */\r
-#define FPB_FP_COMP4_Reserved1_Pos                            29                                                        /*!< FPB FP_COMP4: Reserved1 Position    */\r
-#define FPB_FP_COMP4_Reserved1_Msk                            (0x01UL << FPB_FP_COMP4_Reserved1_Pos)                    /*!< FPB FP_COMP4: Reserved1 Mask        */\r
-#define FPB_FP_COMP4_REPLACE_Pos                              30                                                        /*!< FPB FP_COMP4: REPLACE Position      */\r
-#define FPB_FP_COMP4_REPLACE_Msk                              (0x03UL << FPB_FP_COMP4_REPLACE_Pos)                      /*!< FPB FP_COMP4: REPLACE Mask          */\r
-\r
-// --------------------------------------  FPB_FP_COMP5  ------------------------------------------\r
-#define FPB_FP_COMP5_ENABLE_Pos                               0                                                         /*!< FPB FP_COMP5: ENABLE Position       */\r
-#define FPB_FP_COMP5_ENABLE_Msk                               (0x01UL << FPB_FP_COMP5_ENABLE_Pos)                       /*!< FPB FP_COMP5: ENABLE Mask           */\r
-#define FPB_FP_COMP5_Reserved_Pos                             1                                                         /*!< FPB FP_COMP5: Reserved Position     */\r
-#define FPB_FP_COMP5_Reserved_Msk                             (0x01UL << FPB_FP_COMP5_Reserved_Pos)                     /*!< FPB FP_COMP5: Reserved Mask         */\r
-#define FPB_FP_COMP5_COMP_Pos                                 2                                                         /*!< FPB FP_COMP5: COMP Position         */\r
-#define FPB_FP_COMP5_COMP_Msk                                 (0x07ffffffUL << FPB_FP_COMP5_COMP_Pos)                   /*!< FPB FP_COMP5: COMP Mask             */\r
-#define FPB_FP_COMP5_Reserved1_Pos                            29                                                        /*!< FPB FP_COMP5: Reserved1 Position    */\r
-#define FPB_FP_COMP5_Reserved1_Msk                            (0x01UL << FPB_FP_COMP5_Reserved1_Pos)                    /*!< FPB FP_COMP5: Reserved1 Mask        */\r
-#define FPB_FP_COMP5_REPLACE_Pos                              30                                                        /*!< FPB FP_COMP5: REPLACE Position      */\r
-#define FPB_FP_COMP5_REPLACE_Msk                              (0x03UL << FPB_FP_COMP5_REPLACE_Pos)                      /*!< FPB FP_COMP5: REPLACE Mask          */\r
-\r
-// --------------------------------------  FPB_FP_COMP6  ------------------------------------------\r
-#define FPB_FP_COMP6_ENABLE_Pos                               0                                                         /*!< FPB FP_COMP6: ENABLE Position       */\r
-#define FPB_FP_COMP6_ENABLE_Msk                               (0x01UL << FPB_FP_COMP6_ENABLE_Pos)                       /*!< FPB FP_COMP6: ENABLE Mask           */\r
-#define FPB_FP_COMP6_Reserved_Pos                             1                                                         /*!< FPB FP_COMP6: Reserved Position     */\r
-#define FPB_FP_COMP6_Reserved_Msk                             (0x01UL << FPB_FP_COMP6_Reserved_Pos)                     /*!< FPB FP_COMP6: Reserved Mask         */\r
-#define FPB_FP_COMP6_COMP_Pos                                 2                                                         /*!< FPB FP_COMP6: COMP Position         */\r
-#define FPB_FP_COMP6_COMP_Msk                                 (0x07ffffffUL << FPB_FP_COMP6_COMP_Pos)                   /*!< FPB FP_COMP6: COMP Mask             */\r
-#define FPB_FP_COMP6_Reserved1_Pos                            29                                                        /*!< FPB FP_COMP6: Reserved1 Position    */\r
-#define FPB_FP_COMP6_Reserved1_Msk                            (0x01UL << FPB_FP_COMP6_Reserved1_Pos)                    /*!< FPB FP_COMP6: Reserved1 Mask        */\r
-#define FPB_FP_COMP6_REPLACE_Pos                              30                                                        /*!< FPB FP_COMP6: REPLACE Position      */\r
-#define FPB_FP_COMP6_REPLACE_Msk                              (0x03UL << FPB_FP_COMP6_REPLACE_Pos)                      /*!< FPB FP_COMP6: REPLACE Mask          */\r
-\r
-// --------------------------------------  FPB_FP_COMP7  ------------------------------------------\r
-#define FPB_FP_COMP7_ENABLE_Pos                               0                                                         /*!< FPB FP_COMP7: ENABLE Position       */\r
-#define FPB_FP_COMP7_ENABLE_Msk                               (0x01UL << FPB_FP_COMP7_ENABLE_Pos)                       /*!< FPB FP_COMP7: ENABLE Mask           */\r
-#define FPB_FP_COMP7_Reserved_Pos                             1                                                         /*!< FPB FP_COMP7: Reserved Position     */\r
-#define FPB_FP_COMP7_Reserved_Msk                             (0x01UL << FPB_FP_COMP7_Reserved_Pos)                     /*!< FPB FP_COMP7: Reserved Mask         */\r
-#define FPB_FP_COMP7_COMP_Pos                                 2                                                         /*!< FPB FP_COMP7: COMP Position         */\r
-#define FPB_FP_COMP7_COMP_Msk                                 (0x07ffffffUL << FPB_FP_COMP7_COMP_Pos)                   /*!< FPB FP_COMP7: COMP Mask             */\r
-#define FPB_FP_COMP7_Reserved1_Pos                            29                                                        /*!< FPB FP_COMP7: Reserved1 Position    */\r
-#define FPB_FP_COMP7_Reserved1_Msk                            (0x01UL << FPB_FP_COMP7_Reserved1_Pos)                    /*!< FPB FP_COMP7: Reserved1 Mask        */\r
-#define FPB_FP_COMP7_REPLACE_Pos                              30                                                        /*!< FPB FP_COMP7: REPLACE Position      */\r
-#define FPB_FP_COMP7_REPLACE_Msk                              (0x03UL << FPB_FP_COMP7_REPLACE_Pos)                      /*!< FPB FP_COMP7: REPLACE Mask          */\r
-\r
-// ---------------------------------------  FPB_FPBPID4  ------------------------------------------\r
-#define FPB_FPBPID4_PID4_Pos                                  0                                                         /*!< FPB FPBPID4: PID4 Position          */\r
-#define FPB_FPBPID4_PID4_Msk                                  (0xffffffffUL << FPB_FPBPID4_PID4_Pos)                    /*!< FPB FPBPID4: PID4 Mask              */\r
-\r
-// ---------------------------------------  FPB_FPBPID5  ------------------------------------------\r
-#define FPB_FPBPID5_PID5_Pos                                  0                                                         /*!< FPB FPBPID5: PID5 Position          */\r
-#define FPB_FPBPID5_PID5_Msk                                  (0xffffffffUL << FPB_FPBPID5_PID5_Pos)                    /*!< FPB FPBPID5: PID5 Mask              */\r
-\r
-// ---------------------------------------  FPB_FPBPID6  ------------------------------------------\r
-#define FPB_FPBPID6_PID6_Pos                                  0                                                         /*!< FPB FPBPID6: PID6 Position          */\r
-#define FPB_FPBPID6_PID6_Msk                                  (0xffffffffUL << FPB_FPBPID6_PID6_Pos)                    /*!< FPB FPBPID6: PID6 Mask              */\r
-\r
-// ---------------------------------------  FPB_FPBPID7  ------------------------------------------\r
-#define FPB_FPBPID7_PID7_Pos                                  0                                                         /*!< FPB FPBPID7: PID7 Position          */\r
-#define FPB_FPBPID7_PID7_Msk                                  (0xffffffffUL << FPB_FPBPID7_PID7_Pos)                    /*!< FPB FPBPID7: PID7 Mask              */\r
-\r
-// ---------------------------------------  FPB_FPBPID0  ------------------------------------------\r
-#define FPB_FPBPID0_PID0_Pos                                  0                                                         /*!< FPB FPBPID0: PID0 Position          */\r
-#define FPB_FPBPID0_PID0_Msk                                  (0xffffffffUL << FPB_FPBPID0_PID0_Pos)                    /*!< FPB FPBPID0: PID0 Mask              */\r
-\r
-// ---------------------------------------  FPB_FPBPID1  ------------------------------------------\r
-#define FPB_FPBPID1_PID1_Pos                                  0                                                         /*!< FPB FPBPID1: PID1 Position          */\r
-#define FPB_FPBPID1_PID1_Msk                                  (0xffffffffUL << FPB_FPBPID1_PID1_Pos)                    /*!< FPB FPBPID1: PID1 Mask              */\r
-\r
-// ---------------------------------------  FPB_FPBPID2  ------------------------------------------\r
-#define FPB_FPBPID2_PID2_Pos                                  0                                                         /*!< FPB FPBPID2: PID2 Position          */\r
-#define FPB_FPBPID2_PID2_Msk                                  (0xffffffffUL << FPB_FPBPID2_PID2_Pos)                    /*!< FPB FPBPID2: PID2 Mask              */\r
-\r
-// ---------------------------------------  FPB_FPBPID3  ------------------------------------------\r
-#define FPB_FPBPID3_PID3_Pos                                  0                                                         /*!< FPB FPBPID3: PID3 Position          */\r
-#define FPB_FPBPID3_PID3_Msk                                  (0xffffffffUL << FPB_FPBPID3_PID3_Pos)                    /*!< FPB FPBPID3: PID3 Mask              */\r
-\r
-// ---------------------------------------  FPB_FPBCID0  ------------------------------------------\r
-#define FPB_FPBCID0_CID0_Pos                                  0                                                         /*!< FPB FPBCID0: CID0 Position          */\r
-#define FPB_FPBCID0_CID0_Msk                                  (0xffffffffUL << FPB_FPBCID0_CID0_Pos)                    /*!< FPB FPBCID0: CID0 Mask              */\r
-\r
-// ---------------------------------------  FPB_FPBCID1  ------------------------------------------\r
-#define FPB_FPBCID1_CID1_Pos                                  0                                                         /*!< FPB FPBCID1: CID1 Position          */\r
-#define FPB_FPBCID1_CID1_Msk                                  (0xffffffffUL << FPB_FPBCID1_CID1_Pos)                    /*!< FPB FPBCID1: CID1 Mask              */\r
-\r
-// ---------------------------------------  FPB_FPBCID2  ------------------------------------------\r
-#define FPB_FPBCID2_CID2_Pos                                  0                                                         /*!< FPB FPBCID2: CID2 Position          */\r
-#define FPB_FPBCID2_CID2_Msk                                  (0xffffffffUL << FPB_FPBCID2_CID2_Pos)                    /*!< FPB FPBCID2: CID2 Mask              */\r
-\r
-// ---------------------------------------  FPB_FPBCID3  ------------------------------------------\r
-#define FPB_FPBCID3_CID3_Pos                                  0                                                         /*!< FPB FPBCID3: CID3 Position          */\r
-#define FPB_FPBCID3_CID3_Msk                                  (0xffffffffUL << FPB_FPBCID3_CID3_Pos)                    /*!< FPB FPBCID3: CID3 Mask              */\r
-\r
-\r
-\r
-/***   LEDTS0 Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* LEDTS_ID  =  Module Identification Register*/\r
-#define   LEDTS_ID_MOD_REV_Pos         (0U)\r
-#define   LEDTS_ID_MOD_REV_Msk         (0x000000FFU  << LEDTS_ID_MOD_REV_Pos)\r
-\r
-#define   LEDTS_ID_MOD_TYPE_Pos        (8U)\r
-#define   LEDTS_ID_MOD_TYPE_Msk        (0x000000FFU  << LEDTS_ID_MOD_TYPE_Pos)\r
-\r
-#define   LEDTS_ID_MOD_NUMBER_Pos      (16U)\r
-#define   LEDTS_ID_MOD_NUMBER_Msk      (0x0000FFFFU  << LEDTS_ID_MOD_NUMBER_Pos)\r
-\r
-/* LEDTS_GLOBCTL  =  Global Control Register*/\r
-#define   LEDTS_GLOBCTL_TS_EN_Pos      (0U)\r
-#define   LEDTS_GLOBCTL_TS_EN_Msk      (0x00000001U  << LEDTS_GLOBCTL_TS_EN_Pos)\r
-\r
-#define   LEDTS_GLOBCTL_LD_EN_Pos      (1U)\r
-#define   LEDTS_GLOBCTL_LD_EN_Msk      (0x00000001U  << LEDTS_GLOBCTL_LD_EN_Pos)\r
-\r
-#define   LEDTS_GLOBCTL_CMTR_Pos       (2U)\r
-#define   LEDTS_GLOBCTL_CMTR_Msk       (0x00000001U  << LEDTS_GLOBCTL_CMTR_Pos)\r
-\r
-#define   LEDTS_GLOBCTL_ENSYNC_Pos     (3U)\r
-#define   LEDTS_GLOBCTL_ENSYNC_Msk     (0x00000001U  << LEDTS_GLOBCTL_ENSYNC_Pos)\r
-\r
-#define   LEDTS_GLOBCTL_SUSCFG_Pos     (8U)\r
-#define   LEDTS_GLOBCTL_SUSCFG_Msk     (0x00000001U  << LEDTS_GLOBCTL_SUSCFG_Pos)\r
-\r
-#define   LEDTS_GLOBCTL_MASKVAL_Pos    (9U)\r
-#define   LEDTS_GLOBCTL_MASKVAL_Msk    (0x00000007U  << LEDTS_GLOBCTL_MASKVAL_Pos)\r
-\r
-#define   LEDTS_GLOBCTL_FENVAL_Pos     (12U)\r
-#define   LEDTS_GLOBCTL_FENVAL_Msk     (0x00000001U  << LEDTS_GLOBCTL_FENVAL_Pos)\r
-\r
-#define   LEDTS_GLOBCTL_ITS_EN_Pos     (13U)\r
-#define   LEDTS_GLOBCTL_ITS_EN_Msk     (0x00000001U  << LEDTS_GLOBCTL_ITS_EN_Pos)\r
-\r
-#define   LEDTS_GLOBCTL_ITF_EN_Pos     (14U)\r
-#define   LEDTS_GLOBCTL_ITF_EN_Msk     (0x00000001U  << LEDTS_GLOBCTL_ITF_EN_Pos)\r
-\r
-#define   LEDTS_GLOBCTL_ITP_EN_Pos     (15U)\r
-#define   LEDTS_GLOBCTL_ITP_EN_Msk     (0x00000001U  << LEDTS_GLOBCTL_ITP_EN_Pos)\r
-\r
-#define   LEDTS_GLOBCTL_CLK_PS_Pos     (16U)\r
-#define   LEDTS_GLOBCTL_CLK_PS_Msk     (0x0000FFFFU  << LEDTS_GLOBCTL_CLK_PS_Pos)\r
-\r
-/* LEDTS_FNCTL  =  Function Control Register*/\r
-#define   LEDTS_FNCTL_PADT_Pos         (0U)\r
-#define   LEDTS_FNCTL_PADT_Msk         (0x00000007U  << LEDTS_FNCTL_PADT_Pos)\r
-\r
-#define   LEDTS_FNCTL_PADTSW_Pos       (3U)\r
-#define   LEDTS_FNCTL_PADTSW_Msk       (0x00000001U  << LEDTS_FNCTL_PADTSW_Pos)\r
-\r
-#define   LEDTS_FNCTL_EPULL_Pos        (4U)\r
-#define   LEDTS_FNCTL_EPULL_Msk        (0x00000001U  << LEDTS_FNCTL_EPULL_Pos)\r
-\r
-#define   LEDTS_FNCTL_FNCOL_Pos        (5U)\r
-#define   LEDTS_FNCTL_FNCOL_Msk        (0x00000007U  << LEDTS_FNCTL_FNCOL_Pos)\r
-\r
-#define   LEDTS_FNCTL_ACCCNT_Pos       (16U)\r
-#define   LEDTS_FNCTL_ACCCNT_Msk       (0x0000000FU  << LEDTS_FNCTL_ACCCNT_Pos)\r
-\r
-#define   LEDTS_FNCTL_TSCCMP_Pos       (20U)\r
-#define   LEDTS_FNCTL_TSCCMP_Msk       (0x00000001U  << LEDTS_FNCTL_TSCCMP_Pos)\r
-\r
-#define   LEDTS_FNCTL_TSOEXT_Pos       (21U)\r
-#define   LEDTS_FNCTL_TSOEXT_Msk       (0x00000003U  << LEDTS_FNCTL_TSOEXT_Pos)\r
-\r
-#define   LEDTS_FNCTL_TSCTRR_Pos       (23U)\r
-#define   LEDTS_FNCTL_TSCTRR_Msk       (0x00000001U  << LEDTS_FNCTL_TSCTRR_Pos)\r
-\r
-#define   LEDTS_FNCTL_TSCTRSAT_Pos     (24U)\r
-#define   LEDTS_FNCTL_TSCTRSAT_Msk     (0x00000001U  << LEDTS_FNCTL_TSCTRSAT_Pos)\r
-\r
-#define   LEDTS_FNCTL_NR_TSIN_Pos      (25U)\r
-#define   LEDTS_FNCTL_NR_TSIN_Msk      (0x00000007U  << LEDTS_FNCTL_NR_TSIN_Pos)\r
-\r
-#define   LEDTS_FNCTL_COLLEV_Pos       (28U)\r
-#define   LEDTS_FNCTL_COLLEV_Msk       (0x00000001U  << LEDTS_FNCTL_COLLEV_Pos)\r
-\r
-#define   LEDTS_FNCTL_NR_LEDCOL_Pos    (29U)\r
-#define   LEDTS_FNCTL_NR_LEDCOL_Msk    (0x00000007U  << LEDTS_FNCTL_NR_LEDCOL_Pos)\r
-\r
-/* LEDTS_EVFR  =  Event Flag Register*/\r
-#define   LEDTS_EVFR_TSF_Pos   (0U)\r
-#define   LEDTS_EVFR_TSF_Msk   (0x00000001U  << LEDTS_EVFR_TSF_Pos)\r
-\r
-#define   LEDTS_EVFR_TFF_Pos   (1U)\r
-#define   LEDTS_EVFR_TFF_Msk   (0x00000001U  << LEDTS_EVFR_TFF_Pos)\r
-\r
-#define   LEDTS_EVFR_TPF_Pos   (2U)\r
-#define   LEDTS_EVFR_TPF_Msk   (0x00000001U  << LEDTS_EVFR_TPF_Pos)\r
-\r
-#define   LEDTS_EVFR_TSCTROVF_Pos      (3U)\r
-#define   LEDTS_EVFR_TSCTROVF_Msk      (0x00000001U  << LEDTS_EVFR_TSCTROVF_Pos)\r
-\r
-#define   LEDTS_EVFR_CTSF_Pos          (16U)\r
-#define   LEDTS_EVFR_CTSF_Msk          (0x00000001U  << LEDTS_EVFR_CTSF_Pos)\r
-\r
-#define   LEDTS_EVFR_CTFF_Pos          (17U)\r
-#define   LEDTS_EVFR_CTFF_Msk          (0x00000001U  << LEDTS_EVFR_CTFF_Pos)\r
-\r
-#define   LEDTS_EVFR_CTPF_Pos          (18U)\r
-#define   LEDTS_EVFR_CTPF_Msk          (0x00000001U  << LEDTS_EVFR_CTPF_Pos)\r
-\r
-/* LEDTS_TSVAL  =  Touch-sense TS-Counter Value*/\r
-#define   LEDTS_TSVAL_TSCTRVALR_Pos    (0U)\r
-#define   LEDTS_TSVAL_TSCTRVALR_Msk    (0x0000FFFFU  << LEDTS_TSVAL_TSCTRVALR_Pos)\r
-\r
-#define   LEDTS_TSVAL_TSCTRVAL_Pos     (16U)\r
-#define   LEDTS_TSVAL_TSCTRVAL_Msk     (0x0000FFFFU  << LEDTS_TSVAL_TSCTRVAL_Pos)\r
-\r
-/* LEDTS_LINE0  =  Line Pattern Register 0*/\r
-#define   LEDTS_LINE0_LINE_0_Pos       (0U)\r
-#define   LEDTS_LINE0_LINE_0_Msk       (0x000000FFU  << LEDTS_LINE0_LINE_0_Pos)\r
-\r
-#define   LEDTS_LINE0_LINE_1_Pos       (8U)\r
-#define   LEDTS_LINE0_LINE_1_Msk       (0x000000FFU  << LEDTS_LINE0_LINE_1_Pos)\r
-\r
-#define   LEDTS_LINE0_LINE_2_Pos       (16U)\r
-#define   LEDTS_LINE0_LINE_2_Msk       (0x000000FFU  << LEDTS_LINE0_LINE_2_Pos)\r
-\r
-#define   LEDTS_LINE0_LINE_3_Pos       (24U)\r
-#define   LEDTS_LINE0_LINE_3_Msk       (0x000000FFU  << LEDTS_LINE0_LINE_3_Pos)\r
-\r
-/* LEDTS_LINE1  =  Line Pattern Register 1*/\r
-#define   LEDTS_LINE1_LINE_4_Pos       (0U)\r
-#define   LEDTS_LINE1_LINE_4_Msk       (0x000000FFU  << LEDTS_LINE1_LINE_4_Pos)\r
-\r
-#define   LEDTS_LINE1_LINE_5_Pos       (8U)\r
-#define   LEDTS_LINE1_LINE_5_Msk       (0x000000FFU  << LEDTS_LINE1_LINE_5_Pos)\r
-\r
-#define   LEDTS_LINE1_LINE_6_Pos       (16U)\r
-#define   LEDTS_LINE1_LINE_6_Msk       (0x000000FFU  << LEDTS_LINE1_LINE_6_Pos)\r
-\r
-#define   LEDTS_LINE1_LINE_A_Pos       (24U)\r
-#define   LEDTS_LINE1_LINE_A_Msk       (0x000000FFU  << LEDTS_LINE1_LINE_A_Pos)\r
-\r
-/* LEDTS_LDCMP0  =  LED Compare Register 0*/\r
-#define   LEDTS_LDCMP0_CMP_LD0_Pos     (0U)\r
-#define   LEDTS_LDCMP0_CMP_LD0_Msk     (0x000000FFU  << LEDTS_LDCMP0_CMP_LD0_Pos)\r
-\r
-#define   LEDTS_LDCMP0_CMP_LD1_Pos     (8U)\r
-#define   LEDTS_LDCMP0_CMP_LD1_Msk     (0x000000FFU  << LEDTS_LDCMP0_CMP_LD1_Pos)\r
-\r
-#define   LEDTS_LDCMP0_CMP_LD2_Pos     (16U)\r
-#define   LEDTS_LDCMP0_CMP_LD2_Msk     (0x000000FFU  << LEDTS_LDCMP0_CMP_LD2_Pos)\r
-\r
-#define   LEDTS_LDCMP0_CMP_LD3_Pos     (24U)\r
-#define   LEDTS_LDCMP0_CMP_LD3_Msk     (0x000000FFU  << LEDTS_LDCMP0_CMP_LD3_Pos)\r
-\r
-/* LEDTS_LDCMP1  =  LED Compare Register 1*/\r
-#define   LEDTS_LDCMP1_CMP_LD4_Pos     (0U)\r
-#define   LEDTS_LDCMP1_CMP_LD4_Msk     (0x000000FFU  << LEDTS_LDCMP1_CMP_LD4_Pos)\r
-\r
-#define   LEDTS_LDCMP1_CMP_LD5_Pos     (8U)\r
-#define   LEDTS_LDCMP1_CMP_LD5_Msk     (0x000000FFU  << LEDTS_LDCMP1_CMP_LD5_Pos)\r
-\r
-#define   LEDTS_LDCMP1_CMP_LD6_Pos     (16U)\r
-#define   LEDTS_LDCMP1_CMP_LD6_Msk     (0x000000FFU  << LEDTS_LDCMP1_CMP_LD6_Pos)\r
-\r
-#define   LEDTS_LDCMP1_CMP_LDATSCOM_Pos        (24U)\r
-#define   LEDTS_LDCMP1_CMP_LDATSCOM_Msk        (0x000000FFU  << LEDTS_LDCMP1_CMP_LDATSCOM_Pos)\r
-\r
-/* LEDTS_TSCMP0  =  Touch-sense Compare Register 0*/\r
-#define   LEDTS_TSCMP0_CMP_TS0_Pos     (0U)\r
-#define   LEDTS_TSCMP0_CMP_TS0_Msk     (0x000000FFU  << LEDTS_TSCMP0_CMP_TS0_Pos)\r
-\r
-#define   LEDTS_TSCMP0_CMP_TS1_Pos     (8U)\r
-#define   LEDTS_TSCMP0_CMP_TS1_Msk     (0x000000FFU  << LEDTS_TSCMP0_CMP_TS1_Pos)\r
-\r
-#define   LEDTS_TSCMP0_CMP_TS2_Pos     (16U)\r
-#define   LEDTS_TSCMP0_CMP_TS2_Msk     (0x000000FFU  << LEDTS_TSCMP0_CMP_TS2_Pos)\r
-\r
-#define   LEDTS_TSCMP0_CMP_TS3_Pos     (24U)\r
-#define   LEDTS_TSCMP0_CMP_TS3_Msk     (0x000000FFU  << LEDTS_TSCMP0_CMP_TS3_Pos)\r
-\r
-/* LEDTS_TSCMP1  =  Touch-sense Compare Register 1*/\r
-#define   LEDTS_TSCMP1_CMP_TS4_Pos     (0U)\r
-#define   LEDTS_TSCMP1_CMP_TS4_Msk     (0x000000FFU  << LEDTS_TSCMP1_CMP_TS4_Pos)\r
-\r
-#define   LEDTS_TSCMP1_CMP_TS5_Pos     (8U)\r
-#define   LEDTS_TSCMP1_CMP_TS5_Msk     (0x000000FFU  << LEDTS_TSCMP1_CMP_TS5_Pos)\r
-\r
-#define   LEDTS_TSCMP1_CMP_TS6_Pos     (16U)\r
-#define   LEDTS_TSCMP1_CMP_TS6_Msk     (0x000000FFU  << LEDTS_TSCMP1_CMP_TS6_Pos)\r
-\r
-#define   LEDTS_TSCMP1_CMP_TS7_Pos     (24U)\r
-#define   LEDTS_TSCMP1_CMP_TS7_Msk     (0x000000FFU  << LEDTS_TSCMP1_CMP_TS7_Pos)\r
-\r
-\r
-\r
-/***   PBAx Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* PBA_STS  =  Peripheral Bridge Status Register*/\r
-#define   PBA_STS_WERR_Pos     (0U)\r
-#define   PBA_STS_WERR_Msk     (0x00000001U  << PBA_STS_WERR_Pos)\r
-\r
-/* PBA_WADDR  =  PBA Write Error Address Register*/\r
-#define   PBA_WADDR_WADDR_Pos          (0U)\r
-#define   PBA_WADDR_WADDR_Msk          (0xFFFFFFFFU  << PBA_WADDR_WADDR_Pos)\r
-\r
-\r
-\r
-/***   PMU0 Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* PMU_ID  =  PMU0 Identification Register*/\r
-#define   PMU_ID_MOD_REV_Pos   (0U)\r
-#define   PMU_ID_MOD_REV_Msk   (0x000000FFU  << PMU_ID_MOD_REV_Pos)\r
-\r
-#define   PMU_ID_MOD_TYPE_Pos          (8U)\r
-#define   PMU_ID_MOD_TYPE_Msk          (0x000000FFU  << PMU_ID_MOD_TYPE_Pos)\r
-\r
-#define   PMU_ID_MOD_NUMBER_Pos        (16U)\r
-#define   PMU_ID_MOD_NUMBER_Msk        (0x0000FFFFU  << PMU_ID_MOD_NUMBER_Pos)\r
-\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                 PORT0 Position & Mask                                -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------  PORT0_OUT  -------------------------------------------\r
-#define PORT0_OUT_P0_Pos                                      0                                                         /*!< PORT0 OUT: P0 Position              */\r
-#define PORT0_OUT_P0_Msk                                      (0x01UL << PORT0_OUT_P0_Pos)                              /*!< PORT0 OUT: P0 Mask                  */\r
-#define PORT0_OUT_P1_Pos                                      1                                                         /*!< PORT0 OUT: P1 Position              */\r
-#define PORT0_OUT_P1_Msk                                      (0x01UL << PORT0_OUT_P1_Pos)                              /*!< PORT0 OUT: P1 Mask                  */\r
-#define PORT0_OUT_P2_Pos                                      2                                                         /*!< PORT0 OUT: P2 Position              */\r
-#define PORT0_OUT_P2_Msk                                      (0x01UL << PORT0_OUT_P2_Pos)                              /*!< PORT0 OUT: P2 Mask                  */\r
-#define PORT0_OUT_P3_Pos                                      3                                                         /*!< PORT0 OUT: P3 Position              */\r
-#define PORT0_OUT_P3_Msk                                      (0x01UL << PORT0_OUT_P3_Pos)                              /*!< PORT0 OUT: P3 Mask                  */\r
-#define PORT0_OUT_P4_Pos                                      4                                                         /*!< PORT0 OUT: P4 Position              */\r
-#define PORT0_OUT_P4_Msk                                      (0x01UL << PORT0_OUT_P4_Pos)                              /*!< PORT0 OUT: P4 Mask                  */\r
-#define PORT0_OUT_P5_Pos                                      5                                                         /*!< PORT0 OUT: P5 Position              */\r
-#define PORT0_OUT_P5_Msk                                      (0x01UL << PORT0_OUT_P5_Pos)                              /*!< PORT0 OUT: P5 Mask                  */\r
-#define PORT0_OUT_P6_Pos                                      6                                                         /*!< PORT0 OUT: P6 Position              */\r
-#define PORT0_OUT_P6_Msk                                      (0x01UL << PORT0_OUT_P6_Pos)                              /*!< PORT0 OUT: P6 Mask                  */\r
-#define PORT0_OUT_P7_Pos                                      7                                                         /*!< PORT0 OUT: P7 Position              */\r
-#define PORT0_OUT_P7_Msk                                      (0x01UL << PORT0_OUT_P7_Pos)                              /*!< PORT0 OUT: P7 Mask                  */\r
-#define PORT0_OUT_P8_Pos                                      8                                                         /*!< PORT0 OUT: P8 Position              */\r
-#define PORT0_OUT_P8_Msk                                      (0x01UL << PORT0_OUT_P8_Pos)                              /*!< PORT0 OUT: P8 Mask                  */\r
-#define PORT0_OUT_P9_Pos                                      9                                                         /*!< PORT0 OUT: P9 Position              */\r
-#define PORT0_OUT_P9_Msk                                      (0x01UL << PORT0_OUT_P9_Pos)                              /*!< PORT0 OUT: P9 Mask                  */\r
-#define PORT0_OUT_P10_Pos                                     10                                                        /*!< PORT0 OUT: P10 Position             */\r
-#define PORT0_OUT_P10_Msk                                     (0x01UL << PORT0_OUT_P10_Pos)                             /*!< PORT0 OUT: P10 Mask                 */\r
-#define PORT0_OUT_P11_Pos                                     11                                                        /*!< PORT0 OUT: P11 Position             */\r
-#define PORT0_OUT_P11_Msk                                     (0x01UL << PORT0_OUT_P11_Pos)                             /*!< PORT0 OUT: P11 Mask                 */\r
-#define PORT0_OUT_P12_Pos                                     12                                                        /*!< PORT0 OUT: P12 Position             */\r
-#define PORT0_OUT_P12_Msk                                     (0x01UL << PORT0_OUT_P12_Pos)                             /*!< PORT0 OUT: P12 Mask                 */\r
-#define PORT0_OUT_P13_Pos                                     13                                                        /*!< PORT0 OUT: P13 Position             */\r
-#define PORT0_OUT_P13_Msk                                     (0x01UL << PORT0_OUT_P13_Pos)                             /*!< PORT0 OUT: P13 Mask                 */\r
-#define PORT0_OUT_P14_Pos                                     14                                                        /*!< PORT0 OUT: P14 Position             */\r
-#define PORT0_OUT_P14_Msk                                     (0x01UL << PORT0_OUT_P14_Pos)                             /*!< PORT0 OUT: P14 Mask                 */\r
-#define PORT0_OUT_P15_Pos                                     15                                                        /*!< PORT0 OUT: P15 Position             */\r
-#define PORT0_OUT_P15_Msk                                     (0x01UL << PORT0_OUT_P15_Pos)                             /*!< PORT0 OUT: P15 Mask                 */\r
-\r
-// ----------------------------------------  PORT0_OMR  -------------------------------------------\r
-#define PORT0_OMR_PS0_Pos                                     0                                                         /*!< PORT0 OMR: PS0 Position             */\r
-#define PORT0_OMR_PS0_Msk                                     (0x01UL << PORT0_OMR_PS0_Pos)                             /*!< PORT0 OMR: PS0 Mask                 */\r
-#define PORT0_OMR_PS1_Pos                                     1                                                         /*!< PORT0 OMR: PS1 Position             */\r
-#define PORT0_OMR_PS1_Msk                                     (0x01UL << PORT0_OMR_PS1_Pos)                             /*!< PORT0 OMR: PS1 Mask                 */\r
-#define PORT0_OMR_PS2_Pos                                     2                                                         /*!< PORT0 OMR: PS2 Position             */\r
-#define PORT0_OMR_PS2_Msk                                     (0x01UL << PORT0_OMR_PS2_Pos)                             /*!< PORT0 OMR: PS2 Mask                 */\r
-#define PORT0_OMR_PS3_Pos                                     3                                                         /*!< PORT0 OMR: PS3 Position             */\r
-#define PORT0_OMR_PS3_Msk                                     (0x01UL << PORT0_OMR_PS3_Pos)                             /*!< PORT0 OMR: PS3 Mask                 */\r
-#define PORT0_OMR_PS4_Pos                                     4                                                         /*!< PORT0 OMR: PS4 Position             */\r
-#define PORT0_OMR_PS4_Msk                                     (0x01UL << PORT0_OMR_PS4_Pos)                             /*!< PORT0 OMR: PS4 Mask                 */\r
-#define PORT0_OMR_PS5_Pos                                     5                                                         /*!< PORT0 OMR: PS5 Position             */\r
-#define PORT0_OMR_PS5_Msk                                     (0x01UL << PORT0_OMR_PS5_Pos)                             /*!< PORT0 OMR: PS5 Mask                 */\r
-#define PORT0_OMR_PS6_Pos                                     6                                                         /*!< PORT0 OMR: PS6 Position             */\r
-#define PORT0_OMR_PS6_Msk                                     (0x01UL << PORT0_OMR_PS6_Pos)                             /*!< PORT0 OMR: PS6 Mask                 */\r
-#define PORT0_OMR_PS7_Pos                                     7                                                         /*!< PORT0 OMR: PS7 Position             */\r
-#define PORT0_OMR_PS7_Msk                                     (0x01UL << PORT0_OMR_PS7_Pos)                             /*!< PORT0 OMR: PS7 Mask                 */\r
-#define PORT0_OMR_PS8_Pos                                     8                                                         /*!< PORT0 OMR: PS8 Position             */\r
-#define PORT0_OMR_PS8_Msk                                     (0x01UL << PORT0_OMR_PS8_Pos)                             /*!< PORT0 OMR: PS8 Mask                 */\r
-#define PORT0_OMR_PS9_Pos                                     9                                                         /*!< PORT0 OMR: PS9 Position             */\r
-#define PORT0_OMR_PS9_Msk                                     (0x01UL << PORT0_OMR_PS9_Pos)                             /*!< PORT0 OMR: PS9 Mask                 */\r
-#define PORT0_OMR_PS10_Pos                                    10                                                        /*!< PORT0 OMR: PS10 Position            */\r
-#define PORT0_OMR_PS10_Msk                                    (0x01UL << PORT0_OMR_PS10_Pos)                            /*!< PORT0 OMR: PS10 Mask                */\r
-#define PORT0_OMR_PS11_Pos                                    11                                                        /*!< PORT0 OMR: PS11 Position            */\r
-#define PORT0_OMR_PS11_Msk                                    (0x01UL << PORT0_OMR_PS11_Pos)                            /*!< PORT0 OMR: PS11 Mask                */\r
-#define PORT0_OMR_PS12_Pos                                    12                                                        /*!< PORT0 OMR: PS12 Position            */\r
-#define PORT0_OMR_PS12_Msk                                    (0x01UL << PORT0_OMR_PS12_Pos)                            /*!< PORT0 OMR: PS12 Mask                */\r
-#define PORT0_OMR_PS13_Pos                                    13                                                        /*!< PORT0 OMR: PS13 Position            */\r
-#define PORT0_OMR_PS13_Msk                                    (0x01UL << PORT0_OMR_PS13_Pos)                            /*!< PORT0 OMR: PS13 Mask                */\r
-#define PORT0_OMR_PS14_Pos                                    14                                                        /*!< PORT0 OMR: PS14 Position            */\r
-#define PORT0_OMR_PS14_Msk                                    (0x01UL << PORT0_OMR_PS14_Pos)                            /*!< PORT0 OMR: PS14 Mask                */\r
-#define PORT0_OMR_PS15_Pos                                    15                                                        /*!< PORT0 OMR: PS15 Position            */\r
-#define PORT0_OMR_PS15_Msk                                    (0x01UL << PORT0_OMR_PS15_Pos)                            /*!< PORT0 OMR: PS15 Mask                */\r
-#define PORT0_OMR_PR0_Pos                                     16                                                        /*!< PORT0 OMR: PR0 Position             */\r
-#define PORT0_OMR_PR0_Msk                                     (0x01UL << PORT0_OMR_PR0_Pos)                             /*!< PORT0 OMR: PR0 Mask                 */\r
-#define PORT0_OMR_PR1_Pos                                     17                                                        /*!< PORT0 OMR: PR1 Position             */\r
-#define PORT0_OMR_PR1_Msk                                     (0x01UL << PORT0_OMR_PR1_Pos)                             /*!< PORT0 OMR: PR1 Mask                 */\r
-#define PORT0_OMR_PR2_Pos                                     18                                                        /*!< PORT0 OMR: PR2 Position             */\r
-#define PORT0_OMR_PR2_Msk                                     (0x01UL << PORT0_OMR_PR2_Pos)                             /*!< PORT0 OMR: PR2 Mask                 */\r
-#define PORT0_OMR_PR3_Pos                                     19                                                        /*!< PORT0 OMR: PR3 Position             */\r
-#define PORT0_OMR_PR3_Msk                                     (0x01UL << PORT0_OMR_PR3_Pos)                             /*!< PORT0 OMR: PR3 Mask                 */\r
-#define PORT0_OMR_PR4_Pos                                     20                                                        /*!< PORT0 OMR: PR4 Position             */\r
-#define PORT0_OMR_PR4_Msk                                     (0x01UL << PORT0_OMR_PR4_Pos)                             /*!< PORT0 OMR: PR4 Mask                 */\r
-#define PORT0_OMR_PR5_Pos                                     21                                                        /*!< PORT0 OMR: PR5 Position             */\r
-#define PORT0_OMR_PR5_Msk                                     (0x01UL << PORT0_OMR_PR5_Pos)                             /*!< PORT0 OMR: PR5 Mask                 */\r
-#define PORT0_OMR_PR6_Pos                                     22                                                        /*!< PORT0 OMR: PR6 Position             */\r
-#define PORT0_OMR_PR6_Msk                                     (0x01UL << PORT0_OMR_PR6_Pos)                             /*!< PORT0 OMR: PR6 Mask                 */\r
-#define PORT0_OMR_PR7_Pos                                     23                                                        /*!< PORT0 OMR: PR7 Position             */\r
-#define PORT0_OMR_PR7_Msk                                     (0x01UL << PORT0_OMR_PR7_Pos)                             /*!< PORT0 OMR: PR7 Mask                 */\r
-#define PORT0_OMR_PR8_Pos                                     24                                                        /*!< PORT0 OMR: PR8 Position             */\r
-#define PORT0_OMR_PR8_Msk                                     (0x01UL << PORT0_OMR_PR8_Pos)                             /*!< PORT0 OMR: PR8 Mask                 */\r
-#define PORT0_OMR_PR9_Pos                                     25                                                        /*!< PORT0 OMR: PR9 Position             */\r
-#define PORT0_OMR_PR9_Msk                                     (0x01UL << PORT0_OMR_PR9_Pos)                             /*!< PORT0 OMR: PR9 Mask                 */\r
-#define PORT0_OMR_PR10_Pos                                    26                                                        /*!< PORT0 OMR: PR10 Position            */\r
-#define PORT0_OMR_PR10_Msk                                    (0x01UL << PORT0_OMR_PR10_Pos)                            /*!< PORT0 OMR: PR10 Mask                */\r
-#define PORT0_OMR_PR11_Pos                                    27                                                        /*!< PORT0 OMR: PR11 Position            */\r
-#define PORT0_OMR_PR11_Msk                                    (0x01UL << PORT0_OMR_PR11_Pos)                            /*!< PORT0 OMR: PR11 Mask                */\r
-#define PORT0_OMR_PR12_Pos                                    28                                                        /*!< PORT0 OMR: PR12 Position            */\r
-#define PORT0_OMR_PR12_Msk                                    (0x01UL << PORT0_OMR_PR12_Pos)                            /*!< PORT0 OMR: PR12 Mask                */\r
-#define PORT0_OMR_PR13_Pos                                    29                                                        /*!< PORT0 OMR: PR13 Position            */\r
-#define PORT0_OMR_PR13_Msk                                    (0x01UL << PORT0_OMR_PR13_Pos)                            /*!< PORT0 OMR: PR13 Mask                */\r
-#define PORT0_OMR_PR14_Pos                                    30                                                        /*!< PORT0 OMR: PR14 Position            */\r
-#define PORT0_OMR_PR14_Msk                                    (0x01UL << PORT0_OMR_PR14_Pos)                            /*!< PORT0 OMR: PR14 Mask                */\r
-#define PORT0_OMR_PR15_Pos                                    31                                                        /*!< PORT0 OMR: PR15 Position            */\r
-#define PORT0_OMR_PR15_Msk                                    (0x01UL << PORT0_OMR_PR15_Pos)                            /*!< PORT0 OMR: PR15 Mask                */\r
-\r
-// ---------------------------------------  PORT0_IOCR0  ------------------------------------------\r
-#define PORT0_IOCR0_PC0_Pos                                   3                                                         /*!< PORT0 IOCR0: PC0 Position           */\r
-#define PORT0_IOCR0_PC0_Msk                                   (0x1fUL << PORT0_IOCR0_PC0_Pos)                           /*!< PORT0 IOCR0: PC0 Mask               */\r
-#define PORT0_IOCR0_PC1_Pos                                   11                                                        /*!< PORT0 IOCR0: PC1 Position           */\r
-#define PORT0_IOCR0_PC1_Msk                                   (0x1fUL << PORT0_IOCR0_PC1_Pos)                           /*!< PORT0 IOCR0: PC1 Mask               */\r
-#define PORT0_IOCR0_PC2_Pos                                   19                                                        /*!< PORT0 IOCR0: PC2 Position           */\r
-#define PORT0_IOCR0_PC2_Msk                                   (0x1fUL << PORT0_IOCR0_PC2_Pos)                           /*!< PORT0 IOCR0: PC2 Mask               */\r
-#define PORT0_IOCR0_PC3_Pos                                   27                                                        /*!< PORT0 IOCR0: PC3 Position           */\r
-#define PORT0_IOCR0_PC3_Msk                                   (0x1fUL << PORT0_IOCR0_PC3_Pos)                           /*!< PORT0 IOCR0: PC3 Mask               */\r
-\r
-// ---------------------------------------  PORT0_IOCR4  ------------------------------------------\r
-#define PORT0_IOCR4_PC4_Pos                                   3                                                         /*!< PORT0 IOCR4: PC4 Position           */\r
-#define PORT0_IOCR4_PC4_Msk                                   (0x1fUL << PORT0_IOCR4_PC4_Pos)                           /*!< PORT0 IOCR4: PC4 Mask               */\r
-#define PORT0_IOCR4_PC5_Pos                                   11                                                        /*!< PORT0 IOCR4: PC5 Position           */\r
-#define PORT0_IOCR4_PC5_Msk                                   (0x1fUL << PORT0_IOCR4_PC5_Pos)                           /*!< PORT0 IOCR4: PC5 Mask               */\r
-#define PORT0_IOCR4_PC6_Pos                                   19                                                        /*!< PORT0 IOCR4: PC6 Position           */\r
-#define PORT0_IOCR4_PC6_Msk                                   (0x1fUL << PORT0_IOCR4_PC6_Pos)                           /*!< PORT0 IOCR4: PC6 Mask               */\r
-#define PORT0_IOCR4_PC7_Pos                                   27                                                        /*!< PORT0 IOCR4: PC7 Position           */\r
-#define PORT0_IOCR4_PC7_Msk                                   (0x1fUL << PORT0_IOCR4_PC7_Pos)                           /*!< PORT0 IOCR4: PC7 Mask               */\r
-\r
-// ---------------------------------------  PORT0_IOCR8  ------------------------------------------\r
-#define PORT0_IOCR8_PC8_Pos                                   3                                                         /*!< PORT0 IOCR8: PC8 Position           */\r
-#define PORT0_IOCR8_PC8_Msk                                   (0x1fUL << PORT0_IOCR8_PC8_Pos)                           /*!< PORT0 IOCR8: PC8 Mask               */\r
-#define PORT0_IOCR8_PC9_Pos                                   11                                                        /*!< PORT0 IOCR8: PC9 Position           */\r
-#define PORT0_IOCR8_PC9_Msk                                   (0x1fUL << PORT0_IOCR8_PC9_Pos)                           /*!< PORT0 IOCR8: PC9 Mask               */\r
-#define PORT0_IOCR8_PC10_Pos                                  19                                                        /*!< PORT0 IOCR8: PC10 Position          */\r
-#define PORT0_IOCR8_PC10_Msk                                  (0x1fUL << PORT0_IOCR8_PC10_Pos)                          /*!< PORT0 IOCR8: PC10 Mask              */\r
-#define PORT0_IOCR8_PC11_Pos                                  27                                                        /*!< PORT0 IOCR8: PC11 Position          */\r
-#define PORT0_IOCR8_PC11_Msk                                  (0x1fUL << PORT0_IOCR8_PC11_Pos)                          /*!< PORT0 IOCR8: PC11 Mask              */\r
-\r
-// --------------------------------------  PORT0_IOCR12  ------------------------------------------\r
-#define PORT0_IOCR12_PC12_Pos                                 3                                                         /*!< PORT0 IOCR12: PC12 Position         */\r
-#define PORT0_IOCR12_PC12_Msk                                 (0x1fUL << PORT0_IOCR12_PC12_Pos)                         /*!< PORT0 IOCR12: PC12 Mask             */\r
-#define PORT0_IOCR12_PC13_Pos                                 11                                                        /*!< PORT0 IOCR12: PC13 Position         */\r
-#define PORT0_IOCR12_PC13_Msk                                 (0x1fUL << PORT0_IOCR12_PC13_Pos)                         /*!< PORT0 IOCR12: PC13 Mask             */\r
-#define PORT0_IOCR12_PC14_Pos                                 19                                                        /*!< PORT0 IOCR12: PC14 Position         */\r
-#define PORT0_IOCR12_PC14_Msk                                 (0x1fUL << PORT0_IOCR12_PC14_Pos)                         /*!< PORT0 IOCR12: PC14 Mask             */\r
-#define PORT0_IOCR12_PC15_Pos                                 27                                                        /*!< PORT0 IOCR12: PC15 Position         */\r
-#define PORT0_IOCR12_PC15_Msk                                 (0x1fUL << PORT0_IOCR12_PC15_Pos)                         /*!< PORT0 IOCR12: PC15 Mask             */\r
-\r
-// ----------------------------------------  PORT0_IN  --------------------------------------------\r
-#define PORT0_IN_P0_Pos                                       0                                                         /*!< PORT0 IN: P0 Position               */\r
-#define PORT0_IN_P0_Msk                                       (0x01UL << PORT0_IN_P0_Pos)                               /*!< PORT0 IN: P0 Mask                   */\r
-#define PORT0_IN_P1_Pos                                       1                                                         /*!< PORT0 IN: P1 Position               */\r
-#define PORT0_IN_P1_Msk                                       (0x01UL << PORT0_IN_P1_Pos)                               /*!< PORT0 IN: P1 Mask                   */\r
-#define PORT0_IN_P2_Pos                                       2                                                         /*!< PORT0 IN: P2 Position               */\r
-#define PORT0_IN_P2_Msk                                       (0x01UL << PORT0_IN_P2_Pos)                               /*!< PORT0 IN: P2 Mask                   */\r
-#define PORT0_IN_P3_Pos                                       3                                                         /*!< PORT0 IN: P3 Position               */\r
-#define PORT0_IN_P3_Msk                                       (0x01UL << PORT0_IN_P3_Pos)                               /*!< PORT0 IN: P3 Mask                   */\r
-#define PORT0_IN_P4_Pos                                       4                                                         /*!< PORT0 IN: P4 Position               */\r
-#define PORT0_IN_P4_Msk                                       (0x01UL << PORT0_IN_P4_Pos)                               /*!< PORT0 IN: P4 Mask                   */\r
-#define PORT0_IN_P5_Pos                                       5                                                         /*!< PORT0 IN: P5 Position               */\r
-#define PORT0_IN_P5_Msk                                       (0x01UL << PORT0_IN_P5_Pos)                               /*!< PORT0 IN: P5 Mask                   */\r
-#define PORT0_IN_P6_Pos                                       6                                                         /*!< PORT0 IN: P6 Position               */\r
-#define PORT0_IN_P6_Msk                                       (0x01UL << PORT0_IN_P6_Pos)                               /*!< PORT0 IN: P6 Mask                   */\r
-#define PORT0_IN_P7_Pos                                       7                                                         /*!< PORT0 IN: P7 Position               */\r
-#define PORT0_IN_P7_Msk                                       (0x01UL << PORT0_IN_P7_Pos)                               /*!< PORT0 IN: P7 Mask                   */\r
-#define PORT0_IN_P8_Pos                                       8                                                         /*!< PORT0 IN: P8 Position               */\r
-#define PORT0_IN_P8_Msk                                       (0x01UL << PORT0_IN_P8_Pos)                               /*!< PORT0 IN: P8 Mask                   */\r
-#define PORT0_IN_P9_Pos                                       9                                                         /*!< PORT0 IN: P9 Position               */\r
-#define PORT0_IN_P9_Msk                                       (0x01UL << PORT0_IN_P9_Pos)                               /*!< PORT0 IN: P9 Mask                   */\r
-#define PORT0_IN_P10_Pos                                      10                                                        /*!< PORT0 IN: P10 Position              */\r
-#define PORT0_IN_P10_Msk                                      (0x01UL << PORT0_IN_P10_Pos)                              /*!< PORT0 IN: P10 Mask                  */\r
-#define PORT0_IN_P11_Pos                                      11                                                        /*!< PORT0 IN: P11 Position              */\r
-#define PORT0_IN_P11_Msk                                      (0x01UL << PORT0_IN_P11_Pos)                              /*!< PORT0 IN: P11 Mask                  */\r
-#define PORT0_IN_P12_Pos                                      12                                                        /*!< PORT0 IN: P12 Position              */\r
-#define PORT0_IN_P12_Msk                                      (0x01UL << PORT0_IN_P12_Pos)                              /*!< PORT0 IN: P12 Mask                  */\r
-#define PORT0_IN_P13_Pos                                      13                                                        /*!< PORT0 IN: P13 Position              */\r
-#define PORT0_IN_P13_Msk                                      (0x01UL << PORT0_IN_P13_Pos)                              /*!< PORT0 IN: P13 Mask                  */\r
-#define PORT0_IN_P14_Pos                                      14                                                        /*!< PORT0 IN: P14 Position              */\r
-#define PORT0_IN_P14_Msk                                      (0x01UL << PORT0_IN_P14_Pos)                              /*!< PORT0 IN: P14 Mask                  */\r
-#define PORT0_IN_P15_Pos                                      15                                                        /*!< PORT0 IN: P15 Position              */\r
-#define PORT0_IN_P15_Msk                                      (0x01UL << PORT0_IN_P15_Pos)                              /*!< PORT0 IN: P15 Mask                  */\r
-\r
-// ---------------------------------------  PORT0_PDR0  -------------------------------------------\r
-#define PORT0_PDR0_PD0_Pos                                    0                                                         /*!< PORT0 PDR0: PD0 Position            */\r
-#define PORT0_PDR0_PD0_Msk                                    (0x07UL << PORT0_PDR0_PD0_Pos)                            /*!< PORT0 PDR0: PD0 Mask                */\r
-#define PORT0_PDR0_PD1_Pos                                    4                                                         /*!< PORT0 PDR0: PD1 Position            */\r
-#define PORT0_PDR0_PD1_Msk                                    (0x07UL << PORT0_PDR0_PD1_Pos)                            /*!< PORT0 PDR0: PD1 Mask                */\r
-#define PORT0_PDR0_PD2_Pos                                    8                                                         /*!< PORT0 PDR0: PD2 Position            */\r
-#define PORT0_PDR0_PD2_Msk                                    (0x07UL << PORT0_PDR0_PD2_Pos)                            /*!< PORT0 PDR0: PD2 Mask                */\r
-#define PORT0_PDR0_PD3_Pos                                    12                                                        /*!< PORT0 PDR0: PD3 Position            */\r
-#define PORT0_PDR0_PD3_Msk                                    (0x07UL << PORT0_PDR0_PD3_Pos)                            /*!< PORT0 PDR0: PD3 Mask                */\r
-#define PORT0_PDR0_PD4_Pos                                    16                                                        /*!< PORT0 PDR0: PD4 Position            */\r
-#define PORT0_PDR0_PD4_Msk                                    (0x07UL << PORT0_PDR0_PD4_Pos)                            /*!< PORT0 PDR0: PD4 Mask                */\r
-#define PORT0_PDR0_PD5_Pos                                    20                                                        /*!< PORT0 PDR0: PD5 Position            */\r
-#define PORT0_PDR0_PD5_Msk                                    (0x07UL << PORT0_PDR0_PD5_Pos)                            /*!< PORT0 PDR0: PD5 Mask                */\r
-#define PORT0_PDR0_PD6_Pos                                    24                                                        /*!< PORT0 PDR0: PD6 Position            */\r
-#define PORT0_PDR0_PD6_Msk                                    (0x07UL << PORT0_PDR0_PD6_Pos)                            /*!< PORT0 PDR0: PD6 Mask                */\r
-#define PORT0_PDR0_PD7_Pos                                    28                                                        /*!< PORT0 PDR0: PD7 Position            */\r
-#define PORT0_PDR0_PD7_Msk                                    (0x07UL << PORT0_PDR0_PD7_Pos)                            /*!< PORT0 PDR0: PD7 Mask                */\r
-\r
-// ---------------------------------------  PORT0_PDR1  -------------------------------------------\r
-#define PORT0_PDR1_PD8_Pos                                    0                                                         /*!< PORT0 PDR1: PD8 Position            */\r
-#define PORT0_PDR1_PD8_Msk                                    (0x07UL << PORT0_PDR1_PD8_Pos)                            /*!< PORT0 PDR1: PD8 Mask                */\r
-#define PORT0_PDR1_PD9_Pos                                    4                                                         /*!< PORT0 PDR1: PD9 Position            */\r
-#define PORT0_PDR1_PD9_Msk                                    (0x07UL << PORT0_PDR1_PD9_Pos)                            /*!< PORT0 PDR1: PD9 Mask                */\r
-#define PORT0_PDR1_PD10_Pos                                   8                                                         /*!< PORT0 PDR1: PD10 Position           */\r
-#define PORT0_PDR1_PD10_Msk                                   (0x07UL << PORT0_PDR1_PD10_Pos)                           /*!< PORT0 PDR1: PD10 Mask               */\r
-#define PORT0_PDR1_PD11_Pos                                   12                                                        /*!< PORT0 PDR1: PD11 Position           */\r
-#define PORT0_PDR1_PD11_Msk                                   (0x07UL << PORT0_PDR1_PD11_Pos)                           /*!< PORT0 PDR1: PD11 Mask               */\r
-#define PORT0_PDR1_PD12_Pos                                   16                                                        /*!< PORT0 PDR1: PD12 Position           */\r
-#define PORT0_PDR1_PD12_Msk                                   (0x07UL << PORT0_PDR1_PD12_Pos)                           /*!< PORT0 PDR1: PD12 Mask               */\r
-#define PORT0_PDR1_PD13_Pos                                   20                                                        /*!< PORT0 PDR1: PD13 Position           */\r
-#define PORT0_PDR1_PD13_Msk                                   (0x07UL << PORT0_PDR1_PD13_Pos)                           /*!< PORT0 PDR1: PD13 Mask               */\r
-#define PORT0_PDR1_PD14_Pos                                   24                                                        /*!< PORT0 PDR1: PD14 Position           */\r
-#define PORT0_PDR1_PD14_Msk                                   (0x07UL << PORT0_PDR1_PD14_Pos)                           /*!< PORT0 PDR1: PD14 Mask               */\r
-#define PORT0_PDR1_PD15_Pos                                   28                                                        /*!< PORT0 PDR1: PD15 Position           */\r
-#define PORT0_PDR1_PD15_Msk                                   (0x07UL << PORT0_PDR1_PD15_Pos)                           /*!< PORT0 PDR1: PD15 Mask               */\r
-\r
-// ---------------------------------------  PORT0_PDISC  ------------------------------------------\r
-#define PORT0_PDISC_PDIS0_Pos                                 0                                                         /*!< PORT0 PDISC: PDIS0 Position         */\r
-#define PORT0_PDISC_PDIS0_Msk                                 (0x01UL << PORT0_PDISC_PDIS0_Pos)                         /*!< PORT0 PDISC: PDIS0 Mask             */\r
-#define PORT0_PDISC_PDIS1_Pos                                 1                                                         /*!< PORT0 PDISC: PDIS1 Position         */\r
-#define PORT0_PDISC_PDIS1_Msk                                 (0x01UL << PORT0_PDISC_PDIS1_Pos)                         /*!< PORT0 PDISC: PDIS1 Mask             */\r
-#define PORT0_PDISC_PDIS2_Pos                                 2                                                         /*!< PORT0 PDISC: PDIS2 Position         */\r
-#define PORT0_PDISC_PDIS2_Msk                                 (0x01UL << PORT0_PDISC_PDIS2_Pos)                         /*!< PORT0 PDISC: PDIS2 Mask             */\r
-#define PORT0_PDISC_PDIS3_Pos                                 3                                                         /*!< PORT0 PDISC: PDIS3 Position         */\r
-#define PORT0_PDISC_PDIS3_Msk                                 (0x01UL << PORT0_PDISC_PDIS3_Pos)                         /*!< PORT0 PDISC: PDIS3 Mask             */\r
-#define PORT0_PDISC_PDIS4_Pos                                 4                                                         /*!< PORT0 PDISC: PDIS4 Position         */\r
-#define PORT0_PDISC_PDIS4_Msk                                 (0x01UL << PORT0_PDISC_PDIS4_Pos)                         /*!< PORT0 PDISC: PDIS4 Mask             */\r
-#define PORT0_PDISC_PDIS5_Pos                                 5                                                         /*!< PORT0 PDISC: PDIS5 Position         */\r
-#define PORT0_PDISC_PDIS5_Msk                                 (0x01UL << PORT0_PDISC_PDIS5_Pos)                         /*!< PORT0 PDISC: PDIS5 Mask             */\r
-#define PORT0_PDISC_PDIS6_Pos                                 6                                                         /*!< PORT0 PDISC: PDIS6 Position         */\r
-#define PORT0_PDISC_PDIS6_Msk                                 (0x01UL << PORT0_PDISC_PDIS6_Pos)                         /*!< PORT0 PDISC: PDIS6 Mask             */\r
-#define PORT0_PDISC_PDIS7_Pos                                 7                                                         /*!< PORT0 PDISC: PDIS7 Position         */\r
-#define PORT0_PDISC_PDIS7_Msk                                 (0x01UL << PORT0_PDISC_PDIS7_Pos)                         /*!< PORT0 PDISC: PDIS7 Mask             */\r
-#define PORT0_PDISC_PDIS8_Pos                                 8                                                         /*!< PORT0 PDISC: PDIS8 Position         */\r
-#define PORT0_PDISC_PDIS8_Msk                                 (0x01UL << PORT0_PDISC_PDIS8_Pos)                         /*!< PORT0 PDISC: PDIS8 Mask             */\r
-#define PORT0_PDISC_PDIS9_Pos                                 9                                                         /*!< PORT0 PDISC: PDIS9 Position         */\r
-#define PORT0_PDISC_PDIS9_Msk                                 (0x01UL << PORT0_PDISC_PDIS9_Pos)                         /*!< PORT0 PDISC: PDIS9 Mask             */\r
-#define PORT0_PDISC_PDIS10_Pos                                10                                                        /*!< PORT0 PDISC: PDIS10 Position        */\r
-#define PORT0_PDISC_PDIS10_Msk                                (0x01UL << PORT0_PDISC_PDIS10_Pos)                        /*!< PORT0 PDISC: PDIS10 Mask            */\r
-#define PORT0_PDISC_PDIS11_Pos                                11                                                        /*!< PORT0 PDISC: PDIS11 Position        */\r
-#define PORT0_PDISC_PDIS11_Msk                                (0x01UL << PORT0_PDISC_PDIS11_Pos)                        /*!< PORT0 PDISC: PDIS11 Mask            */\r
-#define PORT0_PDISC_PDIS12_Pos                                12                                                        /*!< PORT0 PDISC: PDIS12 Position        */\r
-#define PORT0_PDISC_PDIS12_Msk                                (0x01UL << PORT0_PDISC_PDIS12_Pos)                        /*!< PORT0 PDISC: PDIS12 Mask            */\r
-#define PORT0_PDISC_PDIS13_Pos                                13                                                        /*!< PORT0 PDISC: PDIS13 Position        */\r
-#define PORT0_PDISC_PDIS13_Msk                                (0x01UL << PORT0_PDISC_PDIS13_Pos)                        /*!< PORT0 PDISC: PDIS13 Mask            */\r
-#define PORT0_PDISC_PDIS14_Pos                                14                                                        /*!< PORT0 PDISC: PDIS14 Position        */\r
-#define PORT0_PDISC_PDIS14_Msk                                (0x01UL << PORT0_PDISC_PDIS14_Pos)                        /*!< PORT0 PDISC: PDIS14 Mask            */\r
-#define PORT0_PDISC_PDIS15_Pos                                15                                                        /*!< PORT0 PDISC: PDIS15 Position        */\r
-#define PORT0_PDISC_PDIS15_Msk                                (0x01UL << PORT0_PDISC_PDIS15_Pos)                        /*!< PORT0 PDISC: PDIS15 Mask            */\r
-\r
-// ----------------------------------------  PORT0_PPS  -------------------------------------------\r
-#define PORT0_PPS_PPS0_Pos                                    0                                                         /*!< PORT0 PPS: PPS0 Position            */\r
-#define PORT0_PPS_PPS0_Msk                                    (0x01UL << PORT0_PPS_PPS0_Pos)                            /*!< PORT0 PPS: PPS0 Mask                */\r
-#define PORT0_PPS_PPS1_Pos                                    1                                                         /*!< PORT0 PPS: PPS1 Position            */\r
-#define PORT0_PPS_PPS1_Msk                                    (0x01UL << PORT0_PPS_PPS1_Pos)                            /*!< PORT0 PPS: PPS1 Mask                */\r
-#define PORT0_PPS_PPS2_Pos                                    2                                                         /*!< PORT0 PPS: PPS2 Position            */\r
-#define PORT0_PPS_PPS2_Msk                                    (0x01UL << PORT0_PPS_PPS2_Pos)                            /*!< PORT0 PPS: PPS2 Mask                */\r
-#define PORT0_PPS_PPS3_Pos                                    3                                                         /*!< PORT0 PPS: PPS3 Position            */\r
-#define PORT0_PPS_PPS3_Msk                                    (0x01UL << PORT0_PPS_PPS3_Pos)                            /*!< PORT0 PPS: PPS3 Mask                */\r
-#define PORT0_PPS_PPS4_Pos                                    4                                                         /*!< PORT0 PPS: PPS4 Position            */\r
-#define PORT0_PPS_PPS4_Msk                                    (0x01UL << PORT0_PPS_PPS4_Pos)                            /*!< PORT0 PPS: PPS4 Mask                */\r
-#define PORT0_PPS_PPS5_Pos                                    5                                                         /*!< PORT0 PPS: PPS5 Position            */\r
-#define PORT0_PPS_PPS5_Msk                                    (0x01UL << PORT0_PPS_PPS5_Pos)                            /*!< PORT0 PPS: PPS5 Mask                */\r
-#define PORT0_PPS_PPS6_Pos                                    6                                                         /*!< PORT0 PPS: PPS6 Position            */\r
-#define PORT0_PPS_PPS6_Msk                                    (0x01UL << PORT0_PPS_PPS6_Pos)                            /*!< PORT0 PPS: PPS6 Mask                */\r
-#define PORT0_PPS_PPS7_Pos                                    7                                                         /*!< PORT0 PPS: PPS7 Position            */\r
-#define PORT0_PPS_PPS7_Msk                                    (0x01UL << PORT0_PPS_PPS7_Pos)                            /*!< PORT0 PPS: PPS7 Mask                */\r
-#define PORT0_PPS_PPS8_Pos                                    8                                                         /*!< PORT0 PPS: PPS8 Position            */\r
-#define PORT0_PPS_PPS8_Msk                                    (0x01UL << PORT0_PPS_PPS8_Pos)                            /*!< PORT0 PPS: PPS8 Mask                */\r
-#define PORT0_PPS_PPS9_Pos                                    9                                                         /*!< PORT0 PPS: PPS9 Position            */\r
-#define PORT0_PPS_PPS9_Msk                                    (0x01UL << PORT0_PPS_PPS9_Pos)                            /*!< PORT0 PPS: PPS9 Mask                */\r
-#define PORT0_PPS_PPS10_Pos                                   10                                                        /*!< PORT0 PPS: PPS10 Position           */\r
-#define PORT0_PPS_PPS10_Msk                                   (0x01UL << PORT0_PPS_PPS10_Pos)                           /*!< PORT0 PPS: PPS10 Mask               */\r
-#define PORT0_PPS_PPS11_Pos                                   11                                                        /*!< PORT0 PPS: PPS11 Position           */\r
-#define PORT0_PPS_PPS11_Msk                                   (0x01UL << PORT0_PPS_PPS11_Pos)                           /*!< PORT0 PPS: PPS11 Mask               */\r
-#define PORT0_PPS_PPS12_Pos                                   12                                                        /*!< PORT0 PPS: PPS12 Position           */\r
-#define PORT0_PPS_PPS12_Msk                                   (0x01UL << PORT0_PPS_PPS12_Pos)                           /*!< PORT0 PPS: PPS12 Mask               */\r
-#define PORT0_PPS_PPS13_Pos                                   13                                                        /*!< PORT0 PPS: PPS13 Position           */\r
-#define PORT0_PPS_PPS13_Msk                                   (0x01UL << PORT0_PPS_PPS13_Pos)                           /*!< PORT0 PPS: PPS13 Mask               */\r
-#define PORT0_PPS_PPS14_Pos                                   14                                                        /*!< PORT0 PPS: PPS14 Position           */\r
-#define PORT0_PPS_PPS14_Msk                                   (0x01UL << PORT0_PPS_PPS14_Pos)                           /*!< PORT0 PPS: PPS14 Mask               */\r
-#define PORT0_PPS_PPS15_Pos                                   15                                                        /*!< PORT0 PPS: PPS15 Position           */\r
-#define PORT0_PPS_PPS15_Msk                                   (0x01UL << PORT0_PPS_PPS15_Pos)                           /*!< PORT0 PPS: PPS15 Mask               */\r
-\r
-// ---------------------------------------  PORT0_HWSEL  ------------------------------------------\r
-#define PORT0_HWSEL_HW0_Pos                                   0                                                         /*!< PORT0 HWSEL: HW0 Position           */\r
-#define PORT0_HWSEL_HW0_Msk                                   (0x03UL << PORT0_HWSEL_HW0_Pos)                           /*!< PORT0 HWSEL: HW0 Mask               */\r
-#define PORT0_HWSEL_HW1_Pos                                   2                                                         /*!< PORT0 HWSEL: HW1 Position           */\r
-#define PORT0_HWSEL_HW1_Msk                                   (0x03UL << PORT0_HWSEL_HW1_Pos)                           /*!< PORT0 HWSEL: HW1 Mask               */\r
-#define PORT0_HWSEL_HW2_Pos                                   4                                                         /*!< PORT0 HWSEL: HW2 Position           */\r
-#define PORT0_HWSEL_HW2_Msk                                   (0x03UL << PORT0_HWSEL_HW2_Pos)                           /*!< PORT0 HWSEL: HW2 Mask               */\r
-#define PORT0_HWSEL_HW3_Pos                                   6                                                         /*!< PORT0 HWSEL: HW3 Position           */\r
-#define PORT0_HWSEL_HW3_Msk                                   (0x03UL << PORT0_HWSEL_HW3_Pos)                           /*!< PORT0 HWSEL: HW3 Mask               */\r
-#define PORT0_HWSEL_HW4_Pos                                   8                                                         /*!< PORT0 HWSEL: HW4 Position           */\r
-#define PORT0_HWSEL_HW4_Msk                                   (0x03UL << PORT0_HWSEL_HW4_Pos)                           /*!< PORT0 HWSEL: HW4 Mask               */\r
-#define PORT0_HWSEL_HW5_Pos                                   10                                                        /*!< PORT0 HWSEL: HW5 Position           */\r
-#define PORT0_HWSEL_HW5_Msk                                   (0x03UL << PORT0_HWSEL_HW5_Pos)                           /*!< PORT0 HWSEL: HW5 Mask               */\r
-#define PORT0_HWSEL_HW6_Pos                                   12                                                        /*!< PORT0 HWSEL: HW6 Position           */\r
-#define PORT0_HWSEL_HW6_Msk                                   (0x03UL << PORT0_HWSEL_HW6_Pos)                           /*!< PORT0 HWSEL: HW6 Mask               */\r
-#define PORT0_HWSEL_HW7_Pos                                   14                                                        /*!< PORT0 HWSEL: HW7 Position           */\r
-#define PORT0_HWSEL_HW7_Msk                                   (0x03UL << PORT0_HWSEL_HW7_Pos)                           /*!< PORT0 HWSEL: HW7 Mask               */\r
-#define PORT0_HWSEL_HW8_Pos                                   16                                                        /*!< PORT0 HWSEL: HW8 Position           */\r
-#define PORT0_HWSEL_HW8_Msk                                   (0x03UL << PORT0_HWSEL_HW8_Pos)                           /*!< PORT0 HWSEL: HW8 Mask               */\r
-#define PORT0_HWSEL_HW9_Pos                                   18                                                        /*!< PORT0 HWSEL: HW9 Position           */\r
-#define PORT0_HWSEL_HW9_Msk                                   (0x03UL << PORT0_HWSEL_HW9_Pos)                           /*!< PORT0 HWSEL: HW9 Mask               */\r
-#define PORT0_HWSEL_HW10_Pos                                  20                                                        /*!< PORT0 HWSEL: HW10 Position          */\r
-#define PORT0_HWSEL_HW10_Msk                                  (0x03UL << PORT0_HWSEL_HW10_Pos)                          /*!< PORT0 HWSEL: HW10 Mask              */\r
-#define PORT0_HWSEL_HW11_Pos                                  22                                                        /*!< PORT0 HWSEL: HW11 Position          */\r
-#define PORT0_HWSEL_HW11_Msk                                  (0x03UL << PORT0_HWSEL_HW11_Pos)                          /*!< PORT0 HWSEL: HW11 Mask              */\r
-#define PORT0_HWSEL_HW12_Pos                                  24                                                        /*!< PORT0 HWSEL: HW12 Position          */\r
-#define PORT0_HWSEL_HW12_Msk                                  (0x03UL << PORT0_HWSEL_HW12_Pos)                          /*!< PORT0 HWSEL: HW12 Mask              */\r
-#define PORT0_HWSEL_HW13_Pos                                  26                                                        /*!< PORT0 HWSEL: HW13 Position          */\r
-#define PORT0_HWSEL_HW13_Msk                                  (0x03UL << PORT0_HWSEL_HW13_Pos)                          /*!< PORT0 HWSEL: HW13 Mask              */\r
-#define PORT0_HWSEL_HW14_Pos                                  28                                                        /*!< PORT0 HWSEL: HW14 Position          */\r
-#define PORT0_HWSEL_HW14_Msk                                  (0x03UL << PORT0_HWSEL_HW14_Pos)                          /*!< PORT0 HWSEL: HW14 Mask              */\r
-#define PORT0_HWSEL_HW15_Pos                                  30                                                        /*!< PORT0 HWSEL: HW15 Position          */\r
-#define PORT0_HWSEL_HW15_Msk                                  (0x03UL << PORT0_HWSEL_HW15_Pos)                          /*!< PORT0 HWSEL: HW15 Mask              */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                 PORT1 Position & Mask                                -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------  PORT1_OUT  -------------------------------------------\r
-#define PORT1_OUT_P0_Pos                                      0                                                         /*!< PORT1 OUT: P0 Position              */\r
-#define PORT1_OUT_P0_Msk                                      (0x01UL << PORT1_OUT_P0_Pos)                              /*!< PORT1 OUT: P0 Mask                  */\r
-#define PORT1_OUT_P1_Pos                                      1                                                         /*!< PORT1 OUT: P1 Position              */\r
-#define PORT1_OUT_P1_Msk                                      (0x01UL << PORT1_OUT_P1_Pos)                              /*!< PORT1 OUT: P1 Mask                  */\r
-#define PORT1_OUT_P2_Pos                                      2                                                         /*!< PORT1 OUT: P2 Position              */\r
-#define PORT1_OUT_P2_Msk                                      (0x01UL << PORT1_OUT_P2_Pos)                              /*!< PORT1 OUT: P2 Mask                  */\r
-#define PORT1_OUT_P3_Pos                                      3                                                         /*!< PORT1 OUT: P3 Position              */\r
-#define PORT1_OUT_P3_Msk                                      (0x01UL << PORT1_OUT_P3_Pos)                              /*!< PORT1 OUT: P3 Mask                  */\r
-#define PORT1_OUT_P4_Pos                                      4                                                         /*!< PORT1 OUT: P4 Position              */\r
-#define PORT1_OUT_P4_Msk                                      (0x01UL << PORT1_OUT_P4_Pos)                              /*!< PORT1 OUT: P4 Mask                  */\r
-#define PORT1_OUT_P5_Pos                                      5                                                         /*!< PORT1 OUT: P5 Position              */\r
-#define PORT1_OUT_P5_Msk                                      (0x01UL << PORT1_OUT_P5_Pos)                              /*!< PORT1 OUT: P5 Mask                  */\r
-#define PORT1_OUT_P6_Pos                                      6                                                         /*!< PORT1 OUT: P6 Position              */\r
-#define PORT1_OUT_P6_Msk                                      (0x01UL << PORT1_OUT_P6_Pos)                              /*!< PORT1 OUT: P6 Mask                  */\r
-#define PORT1_OUT_P7_Pos                                      7                                                         /*!< PORT1 OUT: P7 Position              */\r
-#define PORT1_OUT_P7_Msk                                      (0x01UL << PORT1_OUT_P7_Pos)                              /*!< PORT1 OUT: P7 Mask                  */\r
-#define PORT1_OUT_P8_Pos                                      8                                                         /*!< PORT1 OUT: P8 Position              */\r
-#define PORT1_OUT_P8_Msk                                      (0x01UL << PORT1_OUT_P8_Pos)                              /*!< PORT1 OUT: P8 Mask                  */\r
-#define PORT1_OUT_P9_Pos                                      9                                                         /*!< PORT1 OUT: P9 Position              */\r
-#define PORT1_OUT_P9_Msk                                      (0x01UL << PORT1_OUT_P9_Pos)                              /*!< PORT1 OUT: P9 Mask                  */\r
-#define PORT1_OUT_P10_Pos                                     10                                                        /*!< PORT1 OUT: P10 Position             */\r
-#define PORT1_OUT_P10_Msk                                     (0x01UL << PORT1_OUT_P10_Pos)                             /*!< PORT1 OUT: P10 Mask                 */\r
-#define PORT1_OUT_P11_Pos                                     11                                                        /*!< PORT1 OUT: P11 Position             */\r
-#define PORT1_OUT_P11_Msk                                     (0x01UL << PORT1_OUT_P11_Pos)                             /*!< PORT1 OUT: P11 Mask                 */\r
-#define PORT1_OUT_P12_Pos                                     12                                                        /*!< PORT1 OUT: P12 Position             */\r
-#define PORT1_OUT_P12_Msk                                     (0x01UL << PORT1_OUT_P12_Pos)                             /*!< PORT1 OUT: P12 Mask                 */\r
-#define PORT1_OUT_P13_Pos                                     13                                                        /*!< PORT1 OUT: P13 Position             */\r
-#define PORT1_OUT_P13_Msk                                     (0x01UL << PORT1_OUT_P13_Pos)                             /*!< PORT1 OUT: P13 Mask                 */\r
-#define PORT1_OUT_P14_Pos                                     14                                                        /*!< PORT1 OUT: P14 Position             */\r
-#define PORT1_OUT_P14_Msk                                     (0x01UL << PORT1_OUT_P14_Pos)                             /*!< PORT1 OUT: P14 Mask                 */\r
-#define PORT1_OUT_P15_Pos                                     15                                                        /*!< PORT1 OUT: P15 Position             */\r
-#define PORT1_OUT_P15_Msk                                     (0x01UL << PORT1_OUT_P15_Pos)                             /*!< PORT1 OUT: P15 Mask                 */\r
-\r
-// ----------------------------------------  PORT1_OMR  -------------------------------------------\r
-#define PORT1_OMR_PS0_Pos                                     0                                                         /*!< PORT1 OMR: PS0 Position             */\r
-#define PORT1_OMR_PS0_Msk                                     (0x01UL << PORT1_OMR_PS0_Pos)                             /*!< PORT1 OMR: PS0 Mask                 */\r
-#define PORT1_OMR_PS1_Pos                                     1                                                         /*!< PORT1 OMR: PS1 Position             */\r
-#define PORT1_OMR_PS1_Msk                                     (0x01UL << PORT1_OMR_PS1_Pos)                             /*!< PORT1 OMR: PS1 Mask                 */\r
-#define PORT1_OMR_PS2_Pos                                     2                                                         /*!< PORT1 OMR: PS2 Position             */\r
-#define PORT1_OMR_PS2_Msk                                     (0x01UL << PORT1_OMR_PS2_Pos)                             /*!< PORT1 OMR: PS2 Mask                 */\r
-#define PORT1_OMR_PS3_Pos                                     3                                                         /*!< PORT1 OMR: PS3 Position             */\r
-#define PORT1_OMR_PS3_Msk                                     (0x01UL << PORT1_OMR_PS3_Pos)                             /*!< PORT1 OMR: PS3 Mask                 */\r
-#define PORT1_OMR_PS4_Pos                                     4                                                         /*!< PORT1 OMR: PS4 Position             */\r
-#define PORT1_OMR_PS4_Msk                                     (0x01UL << PORT1_OMR_PS4_Pos)                             /*!< PORT1 OMR: PS4 Mask                 */\r
-#define PORT1_OMR_PS5_Pos                                     5                                                         /*!< PORT1 OMR: PS5 Position             */\r
-#define PORT1_OMR_PS5_Msk                                     (0x01UL << PORT1_OMR_PS5_Pos)                             /*!< PORT1 OMR: PS5 Mask                 */\r
-#define PORT1_OMR_PS6_Pos                                     6                                                         /*!< PORT1 OMR: PS6 Position             */\r
-#define PORT1_OMR_PS6_Msk                                     (0x01UL << PORT1_OMR_PS6_Pos)                             /*!< PORT1 OMR: PS6 Mask                 */\r
-#define PORT1_OMR_PS7_Pos                                     7                                                         /*!< PORT1 OMR: PS7 Position             */\r
-#define PORT1_OMR_PS7_Msk                                     (0x01UL << PORT1_OMR_PS7_Pos)                             /*!< PORT1 OMR: PS7 Mask                 */\r
-#define PORT1_OMR_PS8_Pos                                     8                                                         /*!< PORT1 OMR: PS8 Position             */\r
-#define PORT1_OMR_PS8_Msk                                     (0x01UL << PORT1_OMR_PS8_Pos)                             /*!< PORT1 OMR: PS8 Mask                 */\r
-#define PORT1_OMR_PS9_Pos                                     9                                                         /*!< PORT1 OMR: PS9 Position             */\r
-#define PORT1_OMR_PS9_Msk                                     (0x01UL << PORT1_OMR_PS9_Pos)                             /*!< PORT1 OMR: PS9 Mask                 */\r
-#define PORT1_OMR_PS10_Pos                                    10                                                        /*!< PORT1 OMR: PS10 Position            */\r
-#define PORT1_OMR_PS10_Msk                                    (0x01UL << PORT1_OMR_PS10_Pos)                            /*!< PORT1 OMR: PS10 Mask                */\r
-#define PORT1_OMR_PS11_Pos                                    11                                                        /*!< PORT1 OMR: PS11 Position            */\r
-#define PORT1_OMR_PS11_Msk                                    (0x01UL << PORT1_OMR_PS11_Pos)                            /*!< PORT1 OMR: PS11 Mask                */\r
-#define PORT1_OMR_PS12_Pos                                    12                                                        /*!< PORT1 OMR: PS12 Position            */\r
-#define PORT1_OMR_PS12_Msk                                    (0x01UL << PORT1_OMR_PS12_Pos)                            /*!< PORT1 OMR: PS12 Mask                */\r
-#define PORT1_OMR_PS13_Pos                                    13                                                        /*!< PORT1 OMR: PS13 Position            */\r
-#define PORT1_OMR_PS13_Msk                                    (0x01UL << PORT1_OMR_PS13_Pos)                            /*!< PORT1 OMR: PS13 Mask                */\r
-#define PORT1_OMR_PS14_Pos                                    14                                                        /*!< PORT1 OMR: PS14 Position            */\r
-#define PORT1_OMR_PS14_Msk                                    (0x01UL << PORT1_OMR_PS14_Pos)                            /*!< PORT1 OMR: PS14 Mask                */\r
-#define PORT1_OMR_PS15_Pos                                    15                                                        /*!< PORT1 OMR: PS15 Position            */\r
-#define PORT1_OMR_PS15_Msk                                    (0x01UL << PORT1_OMR_PS15_Pos)                            /*!< PORT1 OMR: PS15 Mask                */\r
-#define PORT1_OMR_PR0_Pos                                     16                                                        /*!< PORT1 OMR: PR0 Position             */\r
-#define PORT1_OMR_PR0_Msk                                     (0x01UL << PORT1_OMR_PR0_Pos)                             /*!< PORT1 OMR: PR0 Mask                 */\r
-#define PORT1_OMR_PR1_Pos                                     17                                                        /*!< PORT1 OMR: PR1 Position             */\r
-#define PORT1_OMR_PR1_Msk                                     (0x01UL << PORT1_OMR_PR1_Pos)                             /*!< PORT1 OMR: PR1 Mask                 */\r
-#define PORT1_OMR_PR2_Pos                                     18                                                        /*!< PORT1 OMR: PR2 Position             */\r
-#define PORT1_OMR_PR2_Msk                                     (0x01UL << PORT1_OMR_PR2_Pos)                             /*!< PORT1 OMR: PR2 Mask                 */\r
-#define PORT1_OMR_PR3_Pos                                     19                                                        /*!< PORT1 OMR: PR3 Position             */\r
-#define PORT1_OMR_PR3_Msk                                     (0x01UL << PORT1_OMR_PR3_Pos)                             /*!< PORT1 OMR: PR3 Mask                 */\r
-#define PORT1_OMR_PR4_Pos                                     20                                                        /*!< PORT1 OMR: PR4 Position             */\r
-#define PORT1_OMR_PR4_Msk                                     (0x01UL << PORT1_OMR_PR4_Pos)                             /*!< PORT1 OMR: PR4 Mask                 */\r
-#define PORT1_OMR_PR5_Pos                                     21                                                        /*!< PORT1 OMR: PR5 Position             */\r
-#define PORT1_OMR_PR5_Msk                                     (0x01UL << PORT1_OMR_PR5_Pos)                             /*!< PORT1 OMR: PR5 Mask                 */\r
-#define PORT1_OMR_PR6_Pos                                     22                                                        /*!< PORT1 OMR: PR6 Position             */\r
-#define PORT1_OMR_PR6_Msk                                     (0x01UL << PORT1_OMR_PR6_Pos)                             /*!< PORT1 OMR: PR6 Mask                 */\r
-#define PORT1_OMR_PR7_Pos                                     23                                                        /*!< PORT1 OMR: PR7 Position             */\r
-#define PORT1_OMR_PR7_Msk                                     (0x01UL << PORT1_OMR_PR7_Pos)                             /*!< PORT1 OMR: PR7 Mask                 */\r
-#define PORT1_OMR_PR8_Pos                                     24                                                        /*!< PORT1 OMR: PR8 Position             */\r
-#define PORT1_OMR_PR8_Msk                                     (0x01UL << PORT1_OMR_PR8_Pos)                             /*!< PORT1 OMR: PR8 Mask                 */\r
-#define PORT1_OMR_PR9_Pos                                     25                                                        /*!< PORT1 OMR: PR9 Position             */\r
-#define PORT1_OMR_PR9_Msk                                     (0x01UL << PORT1_OMR_PR9_Pos)                             /*!< PORT1 OMR: PR9 Mask                 */\r
-#define PORT1_OMR_PR10_Pos                                    26                                                        /*!< PORT1 OMR: PR10 Position            */\r
-#define PORT1_OMR_PR10_Msk                                    (0x01UL << PORT1_OMR_PR10_Pos)                            /*!< PORT1 OMR: PR10 Mask                */\r
-#define PORT1_OMR_PR11_Pos                                    27                                                        /*!< PORT1 OMR: PR11 Position            */\r
-#define PORT1_OMR_PR11_Msk                                    (0x01UL << PORT1_OMR_PR11_Pos)                            /*!< PORT1 OMR: PR11 Mask                */\r
-#define PORT1_OMR_PR12_Pos                                    28                                                        /*!< PORT1 OMR: PR12 Position            */\r
-#define PORT1_OMR_PR12_Msk                                    (0x01UL << PORT1_OMR_PR12_Pos)                            /*!< PORT1 OMR: PR12 Mask                */\r
-#define PORT1_OMR_PR13_Pos                                    29                                                        /*!< PORT1 OMR: PR13 Position            */\r
-#define PORT1_OMR_PR13_Msk                                    (0x01UL << PORT1_OMR_PR13_Pos)                            /*!< PORT1 OMR: PR13 Mask                */\r
-#define PORT1_OMR_PR14_Pos                                    30                                                        /*!< PORT1 OMR: PR14 Position            */\r
-#define PORT1_OMR_PR14_Msk                                    (0x01UL << PORT1_OMR_PR14_Pos)                            /*!< PORT1 OMR: PR14 Mask                */\r
-#define PORT1_OMR_PR15_Pos                                    31                                                        /*!< PORT1 OMR: PR15 Position            */\r
-#define PORT1_OMR_PR15_Msk                                    (0x01UL << PORT1_OMR_PR15_Pos)                            /*!< PORT1 OMR: PR15 Mask                */\r
-\r
-// ---------------------------------------  PORT1_IOCR0  ------------------------------------------\r
-#define PORT1_IOCR0_PC0_Pos                                   3                                                         /*!< PORT1 IOCR0: PC0 Position           */\r
-#define PORT1_IOCR0_PC0_Msk                                   (0x1fUL << PORT1_IOCR0_PC0_Pos)                           /*!< PORT1 IOCR0: PC0 Mask               */\r
-#define PORT1_IOCR0_PC1_Pos                                   11                                                        /*!< PORT1 IOCR0: PC1 Position           */\r
-#define PORT1_IOCR0_PC1_Msk                                   (0x1fUL << PORT1_IOCR0_PC1_Pos)                           /*!< PORT1 IOCR0: PC1 Mask               */\r
-#define PORT1_IOCR0_PC2_Pos                                   19                                                        /*!< PORT1 IOCR0: PC2 Position           */\r
-#define PORT1_IOCR0_PC2_Msk                                   (0x1fUL << PORT1_IOCR0_PC2_Pos)                           /*!< PORT1 IOCR0: PC2 Mask               */\r
-#define PORT1_IOCR0_PC3_Pos                                   27                                                        /*!< PORT1 IOCR0: PC3 Position           */\r
-#define PORT1_IOCR0_PC3_Msk                                   (0x1fUL << PORT1_IOCR0_PC3_Pos)                           /*!< PORT1 IOCR0: PC3 Mask               */\r
-\r
-// ---------------------------------------  PORT1_IOCR4  ------------------------------------------\r
-#define PORT1_IOCR4_PC4_Pos                                   3                                                         /*!< PORT1 IOCR4: PC4 Position           */\r
-#define PORT1_IOCR4_PC4_Msk                                   (0x1fUL << PORT1_IOCR4_PC4_Pos)                           /*!< PORT1 IOCR4: PC4 Mask               */\r
-#define PORT1_IOCR4_PC5_Pos                                   11                                                        /*!< PORT1 IOCR4: PC5 Position           */\r
-#define PORT1_IOCR4_PC5_Msk                                   (0x1fUL << PORT1_IOCR4_PC5_Pos)                           /*!< PORT1 IOCR4: PC5 Mask               */\r
-#define PORT1_IOCR4_PC6_Pos                                   19                                                        /*!< PORT1 IOCR4: PC6 Position           */\r
-#define PORT1_IOCR4_PC6_Msk                                   (0x1fUL << PORT1_IOCR4_PC6_Pos)                           /*!< PORT1 IOCR4: PC6 Mask               */\r
-#define PORT1_IOCR4_PC7_Pos                                   27                                                        /*!< PORT1 IOCR4: PC7 Position           */\r
-#define PORT1_IOCR4_PC7_Msk                                   (0x1fUL << PORT1_IOCR4_PC7_Pos)                           /*!< PORT1 IOCR4: PC7 Mask               */\r
-\r
-// ---------------------------------------  PORT1_IOCR8  ------------------------------------------\r
-#define PORT1_IOCR8_PC8_Pos                                   3                                                         /*!< PORT1 IOCR8: PC8 Position           */\r
-#define PORT1_IOCR8_PC8_Msk                                   (0x1fUL << PORT1_IOCR8_PC8_Pos)                           /*!< PORT1 IOCR8: PC8 Mask               */\r
-#define PORT1_IOCR8_PC9_Pos                                   11                                                        /*!< PORT1 IOCR8: PC9 Position           */\r
-#define PORT1_IOCR8_PC9_Msk                                   (0x1fUL << PORT1_IOCR8_PC9_Pos)                           /*!< PORT1 IOCR8: PC9 Mask               */\r
-#define PORT1_IOCR8_PC10_Pos                                  19                                                        /*!< PORT1 IOCR8: PC10 Position          */\r
-#define PORT1_IOCR8_PC10_Msk                                  (0x1fUL << PORT1_IOCR8_PC10_Pos)                          /*!< PORT1 IOCR8: PC10 Mask              */\r
-#define PORT1_IOCR8_PC11_Pos                                  27                                                        /*!< PORT1 IOCR8: PC11 Position          */\r
-#define PORT1_IOCR8_PC11_Msk                                  (0x1fUL << PORT1_IOCR8_PC11_Pos)                          /*!< PORT1 IOCR8: PC11 Mask              */\r
-\r
-// --------------------------------------  PORT1_IOCR12  ------------------------------------------\r
-#define PORT1_IOCR12_PC12_Pos                                 3                                                         /*!< PORT1 IOCR12: PC12 Position         */\r
-#define PORT1_IOCR12_PC12_Msk                                 (0x1fUL << PORT1_IOCR12_PC12_Pos)                         /*!< PORT1 IOCR12: PC12 Mask             */\r
-#define PORT1_IOCR12_PC13_Pos                                 11                                                        /*!< PORT1 IOCR12: PC13 Position         */\r
-#define PORT1_IOCR12_PC13_Msk                                 (0x1fUL << PORT1_IOCR12_PC13_Pos)                         /*!< PORT1 IOCR12: PC13 Mask             */\r
-#define PORT1_IOCR12_PC14_Pos                                 19                                                        /*!< PORT1 IOCR12: PC14 Position         */\r
-#define PORT1_IOCR12_PC14_Msk                                 (0x1fUL << PORT1_IOCR12_PC14_Pos)                         /*!< PORT1 IOCR12: PC14 Mask             */\r
-#define PORT1_IOCR12_PC15_Pos                                 27                                                        /*!< PORT1 IOCR12: PC15 Position         */\r
-#define PORT1_IOCR12_PC15_Msk                                 (0x1fUL << PORT1_IOCR12_PC15_Pos)                         /*!< PORT1 IOCR12: PC15 Mask             */\r
-\r
-// ----------------------------------------  PORT1_IN  --------------------------------------------\r
-#define PORT1_IN_P0_Pos                                       0                                                         /*!< PORT1 IN: P0 Position               */\r
-#define PORT1_IN_P0_Msk                                       (0x01UL << PORT1_IN_P0_Pos)                               /*!< PORT1 IN: P0 Mask                   */\r
-#define PORT1_IN_P1_Pos                                       1                                                         /*!< PORT1 IN: P1 Position               */\r
-#define PORT1_IN_P1_Msk                                       (0x01UL << PORT1_IN_P1_Pos)                               /*!< PORT1 IN: P1 Mask                   */\r
-#define PORT1_IN_P2_Pos                                       2                                                         /*!< PORT1 IN: P2 Position               */\r
-#define PORT1_IN_P2_Msk                                       (0x01UL << PORT1_IN_P2_Pos)                               /*!< PORT1 IN: P2 Mask                   */\r
-#define PORT1_IN_P3_Pos                                       3                                                         /*!< PORT1 IN: P3 Position               */\r
-#define PORT1_IN_P3_Msk                                       (0x01UL << PORT1_IN_P3_Pos)                               /*!< PORT1 IN: P3 Mask                   */\r
-#define PORT1_IN_P4_Pos                                       4                                                         /*!< PORT1 IN: P4 Position               */\r
-#define PORT1_IN_P4_Msk                                       (0x01UL << PORT1_IN_P4_Pos)                               /*!< PORT1 IN: P4 Mask                   */\r
-#define PORT1_IN_P5_Pos                                       5                                                         /*!< PORT1 IN: P5 Position               */\r
-#define PORT1_IN_P5_Msk                                       (0x01UL << PORT1_IN_P5_Pos)                               /*!< PORT1 IN: P5 Mask                   */\r
-#define PORT1_IN_P6_Pos                                       6                                                         /*!< PORT1 IN: P6 Position               */\r
-#define PORT1_IN_P6_Msk                                       (0x01UL << PORT1_IN_P6_Pos)                               /*!< PORT1 IN: P6 Mask                   */\r
-#define PORT1_IN_P7_Pos                                       7                                                         /*!< PORT1 IN: P7 Position               */\r
-#define PORT1_IN_P7_Msk                                       (0x01UL << PORT1_IN_P7_Pos)                               /*!< PORT1 IN: P7 Mask                   */\r
-#define PORT1_IN_P8_Pos                                       8                                                         /*!< PORT1 IN: P8 Position               */\r
-#define PORT1_IN_P8_Msk                                       (0x01UL << PORT1_IN_P8_Pos)                               /*!< PORT1 IN: P8 Mask                   */\r
-#define PORT1_IN_P9_Pos                                       9                                                         /*!< PORT1 IN: P9 Position               */\r
-#define PORT1_IN_P9_Msk                                       (0x01UL << PORT1_IN_P9_Pos)                               /*!< PORT1 IN: P9 Mask                   */\r
-#define PORT1_IN_P10_Pos                                      10                                                        /*!< PORT1 IN: P10 Position              */\r
-#define PORT1_IN_P10_Msk                                      (0x01UL << PORT1_IN_P10_Pos)                              /*!< PORT1 IN: P10 Mask                  */\r
-#define PORT1_IN_P11_Pos                                      11                                                        /*!< PORT1 IN: P11 Position              */\r
-#define PORT1_IN_P11_Msk                                      (0x01UL << PORT1_IN_P11_Pos)                              /*!< PORT1 IN: P11 Mask                  */\r
-#define PORT1_IN_P12_Pos                                      12                                                        /*!< PORT1 IN: P12 Position              */\r
-#define PORT1_IN_P12_Msk                                      (0x01UL << PORT1_IN_P12_Pos)                              /*!< PORT1 IN: P12 Mask                  */\r
-#define PORT1_IN_P13_Pos                                      13                                                        /*!< PORT1 IN: P13 Position              */\r
-#define PORT1_IN_P13_Msk                                      (0x01UL << PORT1_IN_P13_Pos)                              /*!< PORT1 IN: P13 Mask                  */\r
-#define PORT1_IN_P14_Pos                                      14                                                        /*!< PORT1 IN: P14 Position              */\r
-#define PORT1_IN_P14_Msk                                      (0x01UL << PORT1_IN_P14_Pos)                              /*!< PORT1 IN: P14 Mask                  */\r
-#define PORT1_IN_P15_Pos                                      15                                                        /*!< PORT1 IN: P15 Position              */\r
-#define PORT1_IN_P15_Msk                                      (0x01UL << PORT1_IN_P15_Pos)                              /*!< PORT1 IN: P15 Mask                  */\r
-\r
-// ---------------------------------------  PORT1_PDR0  -------------------------------------------\r
-#define PORT1_PDR0_PD0_Pos                                    0                                                         /*!< PORT1 PDR0: PD0 Position            */\r
-#define PORT1_PDR0_PD0_Msk                                    (0x07UL << PORT1_PDR0_PD0_Pos)                            /*!< PORT1 PDR0: PD0 Mask                */\r
-#define PORT1_PDR0_PD1_Pos                                    4                                                         /*!< PORT1 PDR0: PD1 Position            */\r
-#define PORT1_PDR0_PD1_Msk                                    (0x07UL << PORT1_PDR0_PD1_Pos)                            /*!< PORT1 PDR0: PD1 Mask                */\r
-#define PORT1_PDR0_PD2_Pos                                    8                                                         /*!< PORT1 PDR0: PD2 Position            */\r
-#define PORT1_PDR0_PD2_Msk                                    (0x07UL << PORT1_PDR0_PD2_Pos)                            /*!< PORT1 PDR0: PD2 Mask                */\r
-#define PORT1_PDR0_PD3_Pos                                    12                                                        /*!< PORT1 PDR0: PD3 Position            */\r
-#define PORT1_PDR0_PD3_Msk                                    (0x07UL << PORT1_PDR0_PD3_Pos)                            /*!< PORT1 PDR0: PD3 Mask                */\r
-#define PORT1_PDR0_PD4_Pos                                    16                                                        /*!< PORT1 PDR0: PD4 Position            */\r
-#define PORT1_PDR0_PD4_Msk                                    (0x07UL << PORT1_PDR0_PD4_Pos)                            /*!< PORT1 PDR0: PD4 Mask                */\r
-#define PORT1_PDR0_PD5_Pos                                    20                                                        /*!< PORT1 PDR0: PD5 Position            */\r
-#define PORT1_PDR0_PD5_Msk                                    (0x07UL << PORT1_PDR0_PD5_Pos)                            /*!< PORT1 PDR0: PD5 Mask                */\r
-#define PORT1_PDR0_PD6_Pos                                    24                                                        /*!< PORT1 PDR0: PD6 Position            */\r
-#define PORT1_PDR0_PD6_Msk                                    (0x07UL << PORT1_PDR0_PD6_Pos)                            /*!< PORT1 PDR0: PD6 Mask                */\r
-#define PORT1_PDR0_PD7_Pos                                    28                                                        /*!< PORT1 PDR0: PD7 Position            */\r
-#define PORT1_PDR0_PD7_Msk                                    (0x07UL << PORT1_PDR0_PD7_Pos)                            /*!< PORT1 PDR0: PD7 Mask                */\r
-\r
-// ---------------------------------------  PORT1_PDR1  -------------------------------------------\r
-#define PORT1_PDR1_PD8_Pos                                    0                                                         /*!< PORT1 PDR1: PD8 Position            */\r
-#define PORT1_PDR1_PD8_Msk                                    (0x07UL << PORT1_PDR1_PD8_Pos)                            /*!< PORT1 PDR1: PD8 Mask                */\r
-#define PORT1_PDR1_PD9_Pos                                    4                                                         /*!< PORT1 PDR1: PD9 Position            */\r
-#define PORT1_PDR1_PD9_Msk                                    (0x07UL << PORT1_PDR1_PD9_Pos)                            /*!< PORT1 PDR1: PD9 Mask                */\r
-#define PORT1_PDR1_PD10_Pos                                   8                                                         /*!< PORT1 PDR1: PD10 Position           */\r
-#define PORT1_PDR1_PD10_Msk                                   (0x07UL << PORT1_PDR1_PD10_Pos)                           /*!< PORT1 PDR1: PD10 Mask               */\r
-#define PORT1_PDR1_PD11_Pos                                   12                                                        /*!< PORT1 PDR1: PD11 Position           */\r
-#define PORT1_PDR1_PD11_Msk                                   (0x07UL << PORT1_PDR1_PD11_Pos)                           /*!< PORT1 PDR1: PD11 Mask               */\r
-#define PORT1_PDR1_PD12_Pos                                   16                                                        /*!< PORT1 PDR1: PD12 Position           */\r
-#define PORT1_PDR1_PD12_Msk                                   (0x07UL << PORT1_PDR1_PD12_Pos)                           /*!< PORT1 PDR1: PD12 Mask               */\r
-#define PORT1_PDR1_PD13_Pos                                   20                                                        /*!< PORT1 PDR1: PD13 Position           */\r
-#define PORT1_PDR1_PD13_Msk                                   (0x07UL << PORT1_PDR1_PD13_Pos)                           /*!< PORT1 PDR1: PD13 Mask               */\r
-#define PORT1_PDR1_PD14_Pos                                   24                                                        /*!< PORT1 PDR1: PD14 Position           */\r
-#define PORT1_PDR1_PD14_Msk                                   (0x07UL << PORT1_PDR1_PD14_Pos)                           /*!< PORT1 PDR1: PD14 Mask               */\r
-#define PORT1_PDR1_PD15_Pos                                   28                                                        /*!< PORT1 PDR1: PD15 Position           */\r
-#define PORT1_PDR1_PD15_Msk                                   (0x07UL << PORT1_PDR1_PD15_Pos)                           /*!< PORT1 PDR1: PD15 Mask               */\r
-\r
-// ---------------------------------------  PORT1_PDISC  ------------------------------------------\r
-#define PORT1_PDISC_PDIS0_Pos                                 0                                                         /*!< PORT1 PDISC: PDIS0 Position         */\r
-#define PORT1_PDISC_PDIS0_Msk                                 (0x01UL << PORT1_PDISC_PDIS0_Pos)                         /*!< PORT1 PDISC: PDIS0 Mask             */\r
-#define PORT1_PDISC_PDIS1_Pos                                 1                                                         /*!< PORT1 PDISC: PDIS1 Position         */\r
-#define PORT1_PDISC_PDIS1_Msk                                 (0x01UL << PORT1_PDISC_PDIS1_Pos)                         /*!< PORT1 PDISC: PDIS1 Mask             */\r
-#define PORT1_PDISC_PDIS2_Pos                                 2                                                         /*!< PORT1 PDISC: PDIS2 Position         */\r
-#define PORT1_PDISC_PDIS2_Msk                                 (0x01UL << PORT1_PDISC_PDIS2_Pos)                         /*!< PORT1 PDISC: PDIS2 Mask             */\r
-#define PORT1_PDISC_PDIS3_Pos                                 3                                                         /*!< PORT1 PDISC: PDIS3 Position         */\r
-#define PORT1_PDISC_PDIS3_Msk                                 (0x01UL << PORT1_PDISC_PDIS3_Pos)                         /*!< PORT1 PDISC: PDIS3 Mask             */\r
-#define PORT1_PDISC_PDIS4_Pos                                 4                                                         /*!< PORT1 PDISC: PDIS4 Position         */\r
-#define PORT1_PDISC_PDIS4_Msk                                 (0x01UL << PORT1_PDISC_PDIS4_Pos)                         /*!< PORT1 PDISC: PDIS4 Mask             */\r
-#define PORT1_PDISC_PDIS5_Pos                                 5                                                         /*!< PORT1 PDISC: PDIS5 Position         */\r
-#define PORT1_PDISC_PDIS5_Msk                                 (0x01UL << PORT1_PDISC_PDIS5_Pos)                         /*!< PORT1 PDISC: PDIS5 Mask             */\r
-#define PORT1_PDISC_PDIS6_Pos                                 6                                                         /*!< PORT1 PDISC: PDIS6 Position         */\r
-#define PORT1_PDISC_PDIS6_Msk                                 (0x01UL << PORT1_PDISC_PDIS6_Pos)                         /*!< PORT1 PDISC: PDIS6 Mask             */\r
-#define PORT1_PDISC_PDIS7_Pos                                 7                                                         /*!< PORT1 PDISC: PDIS7 Position         */\r
-#define PORT1_PDISC_PDIS7_Msk                                 (0x01UL << PORT1_PDISC_PDIS7_Pos)                         /*!< PORT1 PDISC: PDIS7 Mask             */\r
-#define PORT1_PDISC_PDIS8_Pos                                 8                                                         /*!< PORT1 PDISC: PDIS8 Position         */\r
-#define PORT1_PDISC_PDIS8_Msk                                 (0x01UL << PORT1_PDISC_PDIS8_Pos)                         /*!< PORT1 PDISC: PDIS8 Mask             */\r
-#define PORT1_PDISC_PDIS9_Pos                                 9                                                         /*!< PORT1 PDISC: PDIS9 Position         */\r
-#define PORT1_PDISC_PDIS9_Msk                                 (0x01UL << PORT1_PDISC_PDIS9_Pos)                         /*!< PORT1 PDISC: PDIS9 Mask             */\r
-#define PORT1_PDISC_PDIS10_Pos                                10                                                        /*!< PORT1 PDISC: PDIS10 Position        */\r
-#define PORT1_PDISC_PDIS10_Msk                                (0x01UL << PORT1_PDISC_PDIS10_Pos)                        /*!< PORT1 PDISC: PDIS10 Mask            */\r
-#define PORT1_PDISC_PDIS11_Pos                                11                                                        /*!< PORT1 PDISC: PDIS11 Position        */\r
-#define PORT1_PDISC_PDIS11_Msk                                (0x01UL << PORT1_PDISC_PDIS11_Pos)                        /*!< PORT1 PDISC: PDIS11 Mask            */\r
-#define PORT1_PDISC_PDIS12_Pos                                12                                                        /*!< PORT1 PDISC: PDIS12 Position        */\r
-#define PORT1_PDISC_PDIS12_Msk                                (0x01UL << PORT1_PDISC_PDIS12_Pos)                        /*!< PORT1 PDISC: PDIS12 Mask            */\r
-#define PORT1_PDISC_PDIS13_Pos                                13                                                        /*!< PORT1 PDISC: PDIS13 Position        */\r
-#define PORT1_PDISC_PDIS13_Msk                                (0x01UL << PORT1_PDISC_PDIS13_Pos)                        /*!< PORT1 PDISC: PDIS13 Mask            */\r
-#define PORT1_PDISC_PDIS14_Pos                                14                                                        /*!< PORT1 PDISC: PDIS14 Position        */\r
-#define PORT1_PDISC_PDIS14_Msk                                (0x01UL << PORT1_PDISC_PDIS14_Pos)                        /*!< PORT1 PDISC: PDIS14 Mask            */\r
-#define PORT1_PDISC_PDIS15_Pos                                15                                                        /*!< PORT1 PDISC: PDIS15 Position        */\r
-#define PORT1_PDISC_PDIS15_Msk                                (0x01UL << PORT1_PDISC_PDIS15_Pos)                        /*!< PORT1 PDISC: PDIS15 Mask            */\r
-\r
-// ----------------------------------------  PORT1_PPS  -------------------------------------------\r
-#define PORT1_PPS_PPS0_Pos                                    0                                                         /*!< PORT1 PPS: PPS0 Position            */\r
-#define PORT1_PPS_PPS0_Msk                                    (0x01UL << PORT1_PPS_PPS0_Pos)                            /*!< PORT1 PPS: PPS0 Mask                */\r
-#define PORT1_PPS_PPS1_Pos                                    1                                                         /*!< PORT1 PPS: PPS1 Position            */\r
-#define PORT1_PPS_PPS1_Msk                                    (0x01UL << PORT1_PPS_PPS1_Pos)                            /*!< PORT1 PPS: PPS1 Mask                */\r
-#define PORT1_PPS_PPS2_Pos                                    2                                                         /*!< PORT1 PPS: PPS2 Position            */\r
-#define PORT1_PPS_PPS2_Msk                                    (0x01UL << PORT1_PPS_PPS2_Pos)                            /*!< PORT1 PPS: PPS2 Mask                */\r
-#define PORT1_PPS_PPS3_Pos                                    3                                                         /*!< PORT1 PPS: PPS3 Position            */\r
-#define PORT1_PPS_PPS3_Msk                                    (0x01UL << PORT1_PPS_PPS3_Pos)                            /*!< PORT1 PPS: PPS3 Mask                */\r
-#define PORT1_PPS_PPS4_Pos                                    4                                                         /*!< PORT1 PPS: PPS4 Position            */\r
-#define PORT1_PPS_PPS4_Msk                                    (0x01UL << PORT1_PPS_PPS4_Pos)                            /*!< PORT1 PPS: PPS4 Mask                */\r
-#define PORT1_PPS_PPS5_Pos                                    5                                                         /*!< PORT1 PPS: PPS5 Position            */\r
-#define PORT1_PPS_PPS5_Msk                                    (0x01UL << PORT1_PPS_PPS5_Pos)                            /*!< PORT1 PPS: PPS5 Mask                */\r
-#define PORT1_PPS_PPS6_Pos                                    6                                                         /*!< PORT1 PPS: PPS6 Position            */\r
-#define PORT1_PPS_PPS6_Msk                                    (0x01UL << PORT1_PPS_PPS6_Pos)                            /*!< PORT1 PPS: PPS6 Mask                */\r
-#define PORT1_PPS_PPS7_Pos                                    7                                                         /*!< PORT1 PPS: PPS7 Position            */\r
-#define PORT1_PPS_PPS7_Msk                                    (0x01UL << PORT1_PPS_PPS7_Pos)                            /*!< PORT1 PPS: PPS7 Mask                */\r
-#define PORT1_PPS_PPS8_Pos                                    8                                                         /*!< PORT1 PPS: PPS8 Position            */\r
-#define PORT1_PPS_PPS8_Msk                                    (0x01UL << PORT1_PPS_PPS8_Pos)                            /*!< PORT1 PPS: PPS8 Mask                */\r
-#define PORT1_PPS_PPS9_Pos                                    9                                                         /*!< PORT1 PPS: PPS9 Position            */\r
-#define PORT1_PPS_PPS9_Msk                                    (0x01UL << PORT1_PPS_PPS9_Pos)                            /*!< PORT1 PPS: PPS9 Mask                */\r
-#define PORT1_PPS_PPS10_Pos                                   10                                                        /*!< PORT1 PPS: PPS10 Position           */\r
-#define PORT1_PPS_PPS10_Msk                                   (0x01UL << PORT1_PPS_PPS10_Pos)                           /*!< PORT1 PPS: PPS10 Mask               */\r
-#define PORT1_PPS_PPS11_Pos                                   11                                                        /*!< PORT1 PPS: PPS11 Position           */\r
-#define PORT1_PPS_PPS11_Msk                                   (0x01UL << PORT1_PPS_PPS11_Pos)                           /*!< PORT1 PPS: PPS11 Mask               */\r
-#define PORT1_PPS_PPS12_Pos                                   12                                                        /*!< PORT1 PPS: PPS12 Position           */\r
-#define PORT1_PPS_PPS12_Msk                                   (0x01UL << PORT1_PPS_PPS12_Pos)                           /*!< PORT1 PPS: PPS12 Mask               */\r
-#define PORT1_PPS_PPS13_Pos                                   13                                                        /*!< PORT1 PPS: PPS13 Position           */\r
-#define PORT1_PPS_PPS13_Msk                                   (0x01UL << PORT1_PPS_PPS13_Pos)                           /*!< PORT1 PPS: PPS13 Mask               */\r
-#define PORT1_PPS_PPS14_Pos                                   14                                                        /*!< PORT1 PPS: PPS14 Position           */\r
-#define PORT1_PPS_PPS14_Msk                                   (0x01UL << PORT1_PPS_PPS14_Pos)                           /*!< PORT1 PPS: PPS14 Mask               */\r
-#define PORT1_PPS_PPS15_Pos                                   15                                                        /*!< PORT1 PPS: PPS15 Position           */\r
-#define PORT1_PPS_PPS15_Msk                                   (0x01UL << PORT1_PPS_PPS15_Pos)                           /*!< PORT1 PPS: PPS15 Mask               */\r
-\r
-// ---------------------------------------  PORT1_HWSEL  ------------------------------------------\r
-#define PORT1_HWSEL_HW0_Pos                                   0                                                         /*!< PORT1 HWSEL: HW0 Position           */\r
-#define PORT1_HWSEL_HW0_Msk                                   (0x03UL << PORT1_HWSEL_HW0_Pos)                           /*!< PORT1 HWSEL: HW0 Mask               */\r
-#define PORT1_HWSEL_HW1_Pos                                   2                                                         /*!< PORT1 HWSEL: HW1 Position           */\r
-#define PORT1_HWSEL_HW1_Msk                                   (0x03UL << PORT1_HWSEL_HW1_Pos)                           /*!< PORT1 HWSEL: HW1 Mask               */\r
-#define PORT1_HWSEL_HW2_Pos                                   4                                                         /*!< PORT1 HWSEL: HW2 Position           */\r
-#define PORT1_HWSEL_HW2_Msk                                   (0x03UL << PORT1_HWSEL_HW2_Pos)                           /*!< PORT1 HWSEL: HW2 Mask               */\r
-#define PORT1_HWSEL_HW3_Pos                                   6                                                         /*!< PORT1 HWSEL: HW3 Position           */\r
-#define PORT1_HWSEL_HW3_Msk                                   (0x03UL << PORT1_HWSEL_HW3_Pos)                           /*!< PORT1 HWSEL: HW3 Mask               */\r
-#define PORT1_HWSEL_HW4_Pos                                   8                                                         /*!< PORT1 HWSEL: HW4 Position           */\r
-#define PORT1_HWSEL_HW4_Msk                                   (0x03UL << PORT1_HWSEL_HW4_Pos)                           /*!< PORT1 HWSEL: HW4 Mask               */\r
-#define PORT1_HWSEL_HW5_Pos                                   10                                                        /*!< PORT1 HWSEL: HW5 Position           */\r
-#define PORT1_HWSEL_HW5_Msk                                   (0x03UL << PORT1_HWSEL_HW5_Pos)                           /*!< PORT1 HWSEL: HW5 Mask               */\r
-#define PORT1_HWSEL_HW6_Pos                                   12                                                        /*!< PORT1 HWSEL: HW6 Position           */\r
-#define PORT1_HWSEL_HW6_Msk                                   (0x03UL << PORT1_HWSEL_HW6_Pos)                           /*!< PORT1 HWSEL: HW6 Mask               */\r
-#define PORT1_HWSEL_HW7_Pos                                   14                                                        /*!< PORT1 HWSEL: HW7 Position           */\r
-#define PORT1_HWSEL_HW7_Msk                                   (0x03UL << PORT1_HWSEL_HW7_Pos)                           /*!< PORT1 HWSEL: HW7 Mask               */\r
-#define PORT1_HWSEL_HW8_Pos                                   16                                                        /*!< PORT1 HWSEL: HW8 Position           */\r
-#define PORT1_HWSEL_HW8_Msk                                   (0x03UL << PORT1_HWSEL_HW8_Pos)                           /*!< PORT1 HWSEL: HW8 Mask               */\r
-#define PORT1_HWSEL_HW9_Pos                                   18                                                        /*!< PORT1 HWSEL: HW9 Position           */\r
-#define PORT1_HWSEL_HW9_Msk                                   (0x03UL << PORT1_HWSEL_HW9_Pos)                           /*!< PORT1 HWSEL: HW9 Mask               */\r
-#define PORT1_HWSEL_HW10_Pos                                  20                                                        /*!< PORT1 HWSEL: HW10 Position          */\r
-#define PORT1_HWSEL_HW10_Msk                                  (0x03UL << PORT1_HWSEL_HW10_Pos)                          /*!< PORT1 HWSEL: HW10 Mask              */\r
-#define PORT1_HWSEL_HW11_Pos                                  22                                                        /*!< PORT1 HWSEL: HW11 Position          */\r
-#define PORT1_HWSEL_HW11_Msk                                  (0x03UL << PORT1_HWSEL_HW11_Pos)                          /*!< PORT1 HWSEL: HW11 Mask              */\r
-#define PORT1_HWSEL_HW12_Pos                                  24                                                        /*!< PORT1 HWSEL: HW12 Position          */\r
-#define PORT1_HWSEL_HW12_Msk                                  (0x03UL << PORT1_HWSEL_HW12_Pos)                          /*!< PORT1 HWSEL: HW12 Mask              */\r
-#define PORT1_HWSEL_HW13_Pos                                  26                                                        /*!< PORT1 HWSEL: HW13 Position          */\r
-#define PORT1_HWSEL_HW13_Msk                                  (0x03UL << PORT1_HWSEL_HW13_Pos)                          /*!< PORT1 HWSEL: HW13 Mask              */\r
-#define PORT1_HWSEL_HW14_Pos                                  28                                                        /*!< PORT1 HWSEL: HW14 Position          */\r
-#define PORT1_HWSEL_HW14_Msk                                  (0x03UL << PORT1_HWSEL_HW14_Pos)                          /*!< PORT1 HWSEL: HW14 Mask              */\r
-#define PORT1_HWSEL_HW15_Pos                                  30                                                        /*!< PORT1 HWSEL: HW15 Position          */\r
-#define PORT1_HWSEL_HW15_Msk                                  (0x03UL << PORT1_HWSEL_HW15_Pos)                          /*!< PORT1 HWSEL: HW15 Mask              */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                 PORT2 Position & Mask                                -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------  PORT2_OUT  -------------------------------------------\r
-#define PORT2_OUT_P0_Pos                                      0                                                         /*!< PORT2 OUT: P0 Position              */\r
-#define PORT2_OUT_P0_Msk                                      (0x01UL << PORT2_OUT_P0_Pos)                              /*!< PORT2 OUT: P0 Mask                  */\r
-#define PORT2_OUT_P1_Pos                                      1                                                         /*!< PORT2 OUT: P1 Position              */\r
-#define PORT2_OUT_P1_Msk                                      (0x01UL << PORT2_OUT_P1_Pos)                              /*!< PORT2 OUT: P1 Mask                  */\r
-#define PORT2_OUT_P2_Pos                                      2                                                         /*!< PORT2 OUT: P2 Position              */\r
-#define PORT2_OUT_P2_Msk                                      (0x01UL << PORT2_OUT_P2_Pos)                              /*!< PORT2 OUT: P2 Mask                  */\r
-#define PORT2_OUT_P3_Pos                                      3                                                         /*!< PORT2 OUT: P3 Position              */\r
-#define PORT2_OUT_P3_Msk                                      (0x01UL << PORT2_OUT_P3_Pos)                              /*!< PORT2 OUT: P3 Mask                  */\r
-#define PORT2_OUT_P4_Pos                                      4                                                         /*!< PORT2 OUT: P4 Position              */\r
-#define PORT2_OUT_P4_Msk                                      (0x01UL << PORT2_OUT_P4_Pos)                              /*!< PORT2 OUT: P4 Mask                  */\r
-#define PORT2_OUT_P5_Pos                                      5                                                         /*!< PORT2 OUT: P5 Position              */\r
-#define PORT2_OUT_P5_Msk                                      (0x01UL << PORT2_OUT_P5_Pos)                              /*!< PORT2 OUT: P5 Mask                  */\r
-#define PORT2_OUT_P6_Pos                                      6                                                         /*!< PORT2 OUT: P6 Position              */\r
-#define PORT2_OUT_P6_Msk                                      (0x01UL << PORT2_OUT_P6_Pos)                              /*!< PORT2 OUT: P6 Mask                  */\r
-#define PORT2_OUT_P7_Pos                                      7                                                         /*!< PORT2 OUT: P7 Position              */\r
-#define PORT2_OUT_P7_Msk                                      (0x01UL << PORT2_OUT_P7_Pos)                              /*!< PORT2 OUT: P7 Mask                  */\r
-#define PORT2_OUT_P8_Pos                                      8                                                         /*!< PORT2 OUT: P8 Position              */\r
-#define PORT2_OUT_P8_Msk                                      (0x01UL << PORT2_OUT_P8_Pos)                              /*!< PORT2 OUT: P8 Mask                  */\r
-#define PORT2_OUT_P9_Pos                                      9                                                         /*!< PORT2 OUT: P9 Position              */\r
-#define PORT2_OUT_P9_Msk                                      (0x01UL << PORT2_OUT_P9_Pos)                              /*!< PORT2 OUT: P9 Mask                  */\r
-#define PORT2_OUT_P10_Pos                                     10                                                        /*!< PORT2 OUT: P10 Position             */\r
-#define PORT2_OUT_P10_Msk                                     (0x01UL << PORT2_OUT_P10_Pos)                             /*!< PORT2 OUT: P10 Mask                 */\r
-#define PORT2_OUT_P11_Pos                                     11                                                        /*!< PORT2 OUT: P11 Position             */\r
-#define PORT2_OUT_P11_Msk                                     (0x01UL << PORT2_OUT_P11_Pos)                             /*!< PORT2 OUT: P11 Mask                 */\r
-#define PORT2_OUT_P12_Pos                                     12                                                        /*!< PORT2 OUT: P12 Position             */\r
-#define PORT2_OUT_P12_Msk                                     (0x01UL << PORT2_OUT_P12_Pos)                             /*!< PORT2 OUT: P12 Mask                 */\r
-#define PORT2_OUT_P13_Pos                                     13                                                        /*!< PORT2 OUT: P13 Position             */\r
-#define PORT2_OUT_P13_Msk                                     (0x01UL << PORT2_OUT_P13_Pos)                             /*!< PORT2 OUT: P13 Mask                 */\r
-#define PORT2_OUT_P14_Pos                                     14                                                        /*!< PORT2 OUT: P14 Position             */\r
-#define PORT2_OUT_P14_Msk                                     (0x01UL << PORT2_OUT_P14_Pos)                             /*!< PORT2 OUT: P14 Mask                 */\r
-#define PORT2_OUT_P15_Pos                                     15                                                        /*!< PORT2 OUT: P15 Position             */\r
-#define PORT2_OUT_P15_Msk                                     (0x01UL << PORT2_OUT_P15_Pos)                             /*!< PORT2 OUT: P15 Mask                 */\r
-\r
-// ----------------------------------------  PORT2_OMR  -------------------------------------------\r
-#define PORT2_OMR_PS0_Pos                                     0                                                         /*!< PORT2 OMR: PS0 Position             */\r
-#define PORT2_OMR_PS0_Msk                                     (0x01UL << PORT2_OMR_PS0_Pos)                             /*!< PORT2 OMR: PS0 Mask                 */\r
-#define PORT2_OMR_PS1_Pos                                     1                                                         /*!< PORT2 OMR: PS1 Position             */\r
-#define PORT2_OMR_PS1_Msk                                     (0x01UL << PORT2_OMR_PS1_Pos)                             /*!< PORT2 OMR: PS1 Mask                 */\r
-#define PORT2_OMR_PS2_Pos                                     2                                                         /*!< PORT2 OMR: PS2 Position             */\r
-#define PORT2_OMR_PS2_Msk                                     (0x01UL << PORT2_OMR_PS2_Pos)                             /*!< PORT2 OMR: PS2 Mask                 */\r
-#define PORT2_OMR_PS3_Pos                                     3                                                         /*!< PORT2 OMR: PS3 Position             */\r
-#define PORT2_OMR_PS3_Msk                                     (0x01UL << PORT2_OMR_PS3_Pos)                             /*!< PORT2 OMR: PS3 Mask                 */\r
-#define PORT2_OMR_PS4_Pos                                     4                                                         /*!< PORT2 OMR: PS4 Position             */\r
-#define PORT2_OMR_PS4_Msk                                     (0x01UL << PORT2_OMR_PS4_Pos)                             /*!< PORT2 OMR: PS4 Mask                 */\r
-#define PORT2_OMR_PS5_Pos                                     5                                                         /*!< PORT2 OMR: PS5 Position             */\r
-#define PORT2_OMR_PS5_Msk                                     (0x01UL << PORT2_OMR_PS5_Pos)                             /*!< PORT2 OMR: PS5 Mask                 */\r
-#define PORT2_OMR_PS6_Pos                                     6                                                         /*!< PORT2 OMR: PS6 Position             */\r
-#define PORT2_OMR_PS6_Msk                                     (0x01UL << PORT2_OMR_PS6_Pos)                             /*!< PORT2 OMR: PS6 Mask                 */\r
-#define PORT2_OMR_PS7_Pos                                     7                                                         /*!< PORT2 OMR: PS7 Position             */\r
-#define PORT2_OMR_PS7_Msk                                     (0x01UL << PORT2_OMR_PS7_Pos)                             /*!< PORT2 OMR: PS7 Mask                 */\r
-#define PORT2_OMR_PS8_Pos                                     8                                                         /*!< PORT2 OMR: PS8 Position             */\r
-#define PORT2_OMR_PS8_Msk                                     (0x01UL << PORT2_OMR_PS8_Pos)                             /*!< PORT2 OMR: PS8 Mask                 */\r
-#define PORT2_OMR_PS9_Pos                                     9                                                         /*!< PORT2 OMR: PS9 Position             */\r
-#define PORT2_OMR_PS9_Msk                                     (0x01UL << PORT2_OMR_PS9_Pos)                             /*!< PORT2 OMR: PS9 Mask                 */\r
-#define PORT2_OMR_PS10_Pos                                    10                                                        /*!< PORT2 OMR: PS10 Position            */\r
-#define PORT2_OMR_PS10_Msk                                    (0x01UL << PORT2_OMR_PS10_Pos)                            /*!< PORT2 OMR: PS10 Mask                */\r
-#define PORT2_OMR_PS11_Pos                                    11                                                        /*!< PORT2 OMR: PS11 Position            */\r
-#define PORT2_OMR_PS11_Msk                                    (0x01UL << PORT2_OMR_PS11_Pos)                            /*!< PORT2 OMR: PS11 Mask                */\r
-#define PORT2_OMR_PS12_Pos                                    12                                                        /*!< PORT2 OMR: PS12 Position            */\r
-#define PORT2_OMR_PS12_Msk                                    (0x01UL << PORT2_OMR_PS12_Pos)                            /*!< PORT2 OMR: PS12 Mask                */\r
-#define PORT2_OMR_PS13_Pos                                    13                                                        /*!< PORT2 OMR: PS13 Position            */\r
-#define PORT2_OMR_PS13_Msk                                    (0x01UL << PORT2_OMR_PS13_Pos)                            /*!< PORT2 OMR: PS13 Mask                */\r
-#define PORT2_OMR_PS14_Pos                                    14                                                        /*!< PORT2 OMR: PS14 Position            */\r
-#define PORT2_OMR_PS14_Msk                                    (0x01UL << PORT2_OMR_PS14_Pos)                            /*!< PORT2 OMR: PS14 Mask                */\r
-#define PORT2_OMR_PS15_Pos                                    15                                                        /*!< PORT2 OMR: PS15 Position            */\r
-#define PORT2_OMR_PS15_Msk                                    (0x01UL << PORT2_OMR_PS15_Pos)                            /*!< PORT2 OMR: PS15 Mask                */\r
-#define PORT2_OMR_PR0_Pos                                     16                                                        /*!< PORT2 OMR: PR0 Position             */\r
-#define PORT2_OMR_PR0_Msk                                     (0x01UL << PORT2_OMR_PR0_Pos)                             /*!< PORT2 OMR: PR0 Mask                 */\r
-#define PORT2_OMR_PR1_Pos                                     17                                                        /*!< PORT2 OMR: PR1 Position             */\r
-#define PORT2_OMR_PR1_Msk                                     (0x01UL << PORT2_OMR_PR1_Pos)                             /*!< PORT2 OMR: PR1 Mask                 */\r
-#define PORT2_OMR_PR2_Pos                                     18                                                        /*!< PORT2 OMR: PR2 Position             */\r
-#define PORT2_OMR_PR2_Msk                                     (0x01UL << PORT2_OMR_PR2_Pos)                             /*!< PORT2 OMR: PR2 Mask                 */\r
-#define PORT2_OMR_PR3_Pos                                     19                                                        /*!< PORT2 OMR: PR3 Position             */\r
-#define PORT2_OMR_PR3_Msk                                     (0x01UL << PORT2_OMR_PR3_Pos)                             /*!< PORT2 OMR: PR3 Mask                 */\r
-#define PORT2_OMR_PR4_Pos                                     20                                                        /*!< PORT2 OMR: PR4 Position             */\r
-#define PORT2_OMR_PR4_Msk                                     (0x01UL << PORT2_OMR_PR4_Pos)                             /*!< PORT2 OMR: PR4 Mask                 */\r
-#define PORT2_OMR_PR5_Pos                                     21                                                        /*!< PORT2 OMR: PR5 Position             */\r
-#define PORT2_OMR_PR5_Msk                                     (0x01UL << PORT2_OMR_PR5_Pos)                             /*!< PORT2 OMR: PR5 Mask                 */\r
-#define PORT2_OMR_PR6_Pos                                     22                                                        /*!< PORT2 OMR: PR6 Position             */\r
-#define PORT2_OMR_PR6_Msk                                     (0x01UL << PORT2_OMR_PR6_Pos)                             /*!< PORT2 OMR: PR6 Mask                 */\r
-#define PORT2_OMR_PR7_Pos                                     23                                                        /*!< PORT2 OMR: PR7 Position             */\r
-#define PORT2_OMR_PR7_Msk                                     (0x01UL << PORT2_OMR_PR7_Pos)                             /*!< PORT2 OMR: PR7 Mask                 */\r
-#define PORT2_OMR_PR8_Pos                                     24                                                        /*!< PORT2 OMR: PR8 Position             */\r
-#define PORT2_OMR_PR8_Msk                                     (0x01UL << PORT2_OMR_PR8_Pos)                             /*!< PORT2 OMR: PR8 Mask                 */\r
-#define PORT2_OMR_PR9_Pos                                     25                                                        /*!< PORT2 OMR: PR9 Position             */\r
-#define PORT2_OMR_PR9_Msk                                     (0x01UL << PORT2_OMR_PR9_Pos)                             /*!< PORT2 OMR: PR9 Mask                 */\r
-#define PORT2_OMR_PR10_Pos                                    26                                                        /*!< PORT2 OMR: PR10 Position            */\r
-#define PORT2_OMR_PR10_Msk                                    (0x01UL << PORT2_OMR_PR10_Pos)                            /*!< PORT2 OMR: PR10 Mask                */\r
-#define PORT2_OMR_PR11_Pos                                    27                                                        /*!< PORT2 OMR: PR11 Position            */\r
-#define PORT2_OMR_PR11_Msk                                    (0x01UL << PORT2_OMR_PR11_Pos)                            /*!< PORT2 OMR: PR11 Mask                */\r
-#define PORT2_OMR_PR12_Pos                                    28                                                        /*!< PORT2 OMR: PR12 Position            */\r
-#define PORT2_OMR_PR12_Msk                                    (0x01UL << PORT2_OMR_PR12_Pos)                            /*!< PORT2 OMR: PR12 Mask                */\r
-#define PORT2_OMR_PR13_Pos                                    29                                                        /*!< PORT2 OMR: PR13 Position            */\r
-#define PORT2_OMR_PR13_Msk                                    (0x01UL << PORT2_OMR_PR13_Pos)                            /*!< PORT2 OMR: PR13 Mask                */\r
-#define PORT2_OMR_PR14_Pos                                    30                                                        /*!< PORT2 OMR: PR14 Position            */\r
-#define PORT2_OMR_PR14_Msk                                    (0x01UL << PORT2_OMR_PR14_Pos)                            /*!< PORT2 OMR: PR14 Mask                */\r
-#define PORT2_OMR_PR15_Pos                                    31                                                        /*!< PORT2 OMR: PR15 Position            */\r
-#define PORT2_OMR_PR15_Msk                                    (0x01UL << PORT2_OMR_PR15_Pos)                            /*!< PORT2 OMR: PR15 Mask                */\r
-\r
-// ---------------------------------------  PORT2_IOCR0  ------------------------------------------\r
-#define PORT2_IOCR0_PC0_Pos                                   3                                                         /*!< PORT2 IOCR0: PC0 Position           */\r
-#define PORT2_IOCR0_PC0_Msk                                   (0x1fUL << PORT2_IOCR0_PC0_Pos)                           /*!< PORT2 IOCR0: PC0 Mask               */\r
-#define PORT2_IOCR0_PC1_Pos                                   11                                                        /*!< PORT2 IOCR0: PC1 Position           */\r
-#define PORT2_IOCR0_PC1_Msk                                   (0x1fUL << PORT2_IOCR0_PC1_Pos)                           /*!< PORT2 IOCR0: PC1 Mask               */\r
-#define PORT2_IOCR0_PC2_Pos                                   19                                                        /*!< PORT2 IOCR0: PC2 Position           */\r
-#define PORT2_IOCR0_PC2_Msk                                   (0x1fUL << PORT2_IOCR0_PC2_Pos)                           /*!< PORT2 IOCR0: PC2 Mask               */\r
-#define PORT2_IOCR0_PC3_Pos                                   27                                                        /*!< PORT2 IOCR0: PC3 Position           */\r
-#define PORT2_IOCR0_PC3_Msk                                   (0x1fUL << PORT2_IOCR0_PC3_Pos)                           /*!< PORT2 IOCR0: PC3 Mask               */\r
-\r
-// ---------------------------------------  PORT2_IOCR4  ------------------------------------------\r
-#define PORT2_IOCR4_PC4_Pos                                   3                                                         /*!< PORT2 IOCR4: PC4 Position           */\r
-#define PORT2_IOCR4_PC4_Msk                                   (0x1fUL << PORT2_IOCR4_PC4_Pos)                           /*!< PORT2 IOCR4: PC4 Mask               */\r
-#define PORT2_IOCR4_PC5_Pos                                   11                                                        /*!< PORT2 IOCR4: PC5 Position           */\r
-#define PORT2_IOCR4_PC5_Msk                                   (0x1fUL << PORT2_IOCR4_PC5_Pos)                           /*!< PORT2 IOCR4: PC5 Mask               */\r
-#define PORT2_IOCR4_PC6_Pos                                   19                                                        /*!< PORT2 IOCR4: PC6 Position           */\r
-#define PORT2_IOCR4_PC6_Msk                                   (0x1fUL << PORT2_IOCR4_PC6_Pos)                           /*!< PORT2 IOCR4: PC6 Mask               */\r
-#define PORT2_IOCR4_PC7_Pos                                   27                                                        /*!< PORT2 IOCR4: PC7 Position           */\r
-#define PORT2_IOCR4_PC7_Msk                                   (0x1fUL << PORT2_IOCR4_PC7_Pos)                           /*!< PORT2 IOCR4: PC7 Mask               */\r
-\r
-// ---------------------------------------  PORT2_IOCR8  ------------------------------------------\r
-#define PORT2_IOCR8_PC8_Pos                                   3                                                         /*!< PORT2 IOCR8: PC8 Position           */\r
-#define PORT2_IOCR8_PC8_Msk                                   (0x1fUL << PORT2_IOCR8_PC8_Pos)                           /*!< PORT2 IOCR8: PC8 Mask               */\r
-#define PORT2_IOCR8_PC9_Pos                                   11                                                        /*!< PORT2 IOCR8: PC9 Position           */\r
-#define PORT2_IOCR8_PC9_Msk                                   (0x1fUL << PORT2_IOCR8_PC9_Pos)                           /*!< PORT2 IOCR8: PC9 Mask               */\r
-#define PORT2_IOCR8_PC10_Pos                                  19                                                        /*!< PORT2 IOCR8: PC10 Position          */\r
-#define PORT2_IOCR8_PC10_Msk                                  (0x1fUL << PORT2_IOCR8_PC10_Pos)                          /*!< PORT2 IOCR8: PC10 Mask              */\r
-#define PORT2_IOCR8_PC11_Pos                                  27                                                        /*!< PORT2 IOCR8: PC11 Position          */\r
-#define PORT2_IOCR8_PC11_Msk                                  (0x1fUL << PORT2_IOCR8_PC11_Pos)                          /*!< PORT2 IOCR8: PC11 Mask              */\r
-\r
-// --------------------------------------  PORT2_IOCR12  ------------------------------------------\r
-#define PORT2_IOCR12_PC12_Pos                                 3                                                         /*!< PORT2 IOCR12: PC12 Position         */\r
-#define PORT2_IOCR12_PC12_Msk                                 (0x1fUL << PORT2_IOCR12_PC12_Pos)                         /*!< PORT2 IOCR12: PC12 Mask             */\r
-#define PORT2_IOCR12_PC13_Pos                                 11                                                        /*!< PORT2 IOCR12: PC13 Position         */\r
-#define PORT2_IOCR12_PC13_Msk                                 (0x1fUL << PORT2_IOCR12_PC13_Pos)                         /*!< PORT2 IOCR12: PC13 Mask             */\r
-#define PORT2_IOCR12_PC14_Pos                                 19                                                        /*!< PORT2 IOCR12: PC14 Position         */\r
-#define PORT2_IOCR12_PC14_Msk                                 (0x1fUL << PORT2_IOCR12_PC14_Pos)                         /*!< PORT2 IOCR12: PC14 Mask             */\r
-#define PORT2_IOCR12_PC15_Pos                                 27                                                        /*!< PORT2 IOCR12: PC15 Position         */\r
-#define PORT2_IOCR12_PC15_Msk                                 (0x1fUL << PORT2_IOCR12_PC15_Pos)                         /*!< PORT2 IOCR12: PC15 Mask             */\r
-\r
-// ----------------------------------------  PORT2_IN  --------------------------------------------\r
-#define PORT2_IN_P0_Pos                                       0                                                         /*!< PORT2 IN: P0 Position               */\r
-#define PORT2_IN_P0_Msk                                       (0x01UL << PORT2_IN_P0_Pos)                               /*!< PORT2 IN: P0 Mask                   */\r
-#define PORT2_IN_P1_Pos                                       1                                                         /*!< PORT2 IN: P1 Position               */\r
-#define PORT2_IN_P1_Msk                                       (0x01UL << PORT2_IN_P1_Pos)                               /*!< PORT2 IN: P1 Mask                   */\r
-#define PORT2_IN_P2_Pos                                       2                                                         /*!< PORT2 IN: P2 Position               */\r
-#define PORT2_IN_P2_Msk                                       (0x01UL << PORT2_IN_P2_Pos)                               /*!< PORT2 IN: P2 Mask                   */\r
-#define PORT2_IN_P3_Pos                                       3                                                         /*!< PORT2 IN: P3 Position               */\r
-#define PORT2_IN_P3_Msk                                       (0x01UL << PORT2_IN_P3_Pos)                               /*!< PORT2 IN: P3 Mask                   */\r
-#define PORT2_IN_P4_Pos                                       4                                                         /*!< PORT2 IN: P4 Position               */\r
-#define PORT2_IN_P4_Msk                                       (0x01UL << PORT2_IN_P4_Pos)                               /*!< PORT2 IN: P4 Mask                   */\r
-#define PORT2_IN_P5_Pos                                       5                                                         /*!< PORT2 IN: P5 Position               */\r
-#define PORT2_IN_P5_Msk                                       (0x01UL << PORT2_IN_P5_Pos)                               /*!< PORT2 IN: P5 Mask                   */\r
-#define PORT2_IN_P6_Pos                                       6                                                         /*!< PORT2 IN: P6 Position               */\r
-#define PORT2_IN_P6_Msk                                       (0x01UL << PORT2_IN_P6_Pos)                               /*!< PORT2 IN: P6 Mask                   */\r
-#define PORT2_IN_P7_Pos                                       7                                                         /*!< PORT2 IN: P7 Position               */\r
-#define PORT2_IN_P7_Msk                                       (0x01UL << PORT2_IN_P7_Pos)                               /*!< PORT2 IN: P7 Mask                   */\r
-#define PORT2_IN_P8_Pos                                       8                                                         /*!< PORT2 IN: P8 Position               */\r
-#define PORT2_IN_P8_Msk                                       (0x01UL << PORT2_IN_P8_Pos)                               /*!< PORT2 IN: P8 Mask                   */\r
-#define PORT2_IN_P9_Pos                                       9                                                         /*!< PORT2 IN: P9 Position               */\r
-#define PORT2_IN_P9_Msk                                       (0x01UL << PORT2_IN_P9_Pos)                               /*!< PORT2 IN: P9 Mask                   */\r
-#define PORT2_IN_P10_Pos                                      10                                                        /*!< PORT2 IN: P10 Position              */\r
-#define PORT2_IN_P10_Msk                                      (0x01UL << PORT2_IN_P10_Pos)                              /*!< PORT2 IN: P10 Mask                  */\r
-#define PORT2_IN_P11_Pos                                      11                                                        /*!< PORT2 IN: P11 Position              */\r
-#define PORT2_IN_P11_Msk                                      (0x01UL << PORT2_IN_P11_Pos)                              /*!< PORT2 IN: P11 Mask                  */\r
-#define PORT2_IN_P12_Pos                                      12                                                        /*!< PORT2 IN: P12 Position              */\r
-#define PORT2_IN_P12_Msk                                      (0x01UL << PORT2_IN_P12_Pos)                              /*!< PORT2 IN: P12 Mask                  */\r
-#define PORT2_IN_P13_Pos                                      13                                                        /*!< PORT2 IN: P13 Position              */\r
-#define PORT2_IN_P13_Msk                                      (0x01UL << PORT2_IN_P13_Pos)                              /*!< PORT2 IN: P13 Mask                  */\r
-#define PORT2_IN_P14_Pos                                      14                                                        /*!< PORT2 IN: P14 Position              */\r
-#define PORT2_IN_P14_Msk                                      (0x01UL << PORT2_IN_P14_Pos)                              /*!< PORT2 IN: P14 Mask                  */\r
-#define PORT2_IN_P15_Pos                                      15                                                        /*!< PORT2 IN: P15 Position              */\r
-#define PORT2_IN_P15_Msk                                      (0x01UL << PORT2_IN_P15_Pos)                              /*!< PORT2 IN: P15 Mask                  */\r
-\r
-// ---------------------------------------  PORT2_PDR0  -------------------------------------------\r
-#define PORT2_PDR0_PD0_Pos                                    0                                                         /*!< PORT2 PDR0: PD0 Position            */\r
-#define PORT2_PDR0_PD0_Msk                                    (0x07UL << PORT2_PDR0_PD0_Pos)                            /*!< PORT2 PDR0: PD0 Mask                */\r
-#define PORT2_PDR0_PD1_Pos                                    4                                                         /*!< PORT2 PDR0: PD1 Position            */\r
-#define PORT2_PDR0_PD1_Msk                                    (0x07UL << PORT2_PDR0_PD1_Pos)                            /*!< PORT2 PDR0: PD1 Mask                */\r
-#define PORT2_PDR0_PD2_Pos                                    8                                                         /*!< PORT2 PDR0: PD2 Position            */\r
-#define PORT2_PDR0_PD2_Msk                                    (0x07UL << PORT2_PDR0_PD2_Pos)                            /*!< PORT2 PDR0: PD2 Mask                */\r
-#define PORT2_PDR0_PD3_Pos                                    12                                                        /*!< PORT2 PDR0: PD3 Position            */\r
-#define PORT2_PDR0_PD3_Msk                                    (0x07UL << PORT2_PDR0_PD3_Pos)                            /*!< PORT2 PDR0: PD3 Mask                */\r
-#define PORT2_PDR0_PD4_Pos                                    16                                                        /*!< PORT2 PDR0: PD4 Position            */\r
-#define PORT2_PDR0_PD4_Msk                                    (0x07UL << PORT2_PDR0_PD4_Pos)                            /*!< PORT2 PDR0: PD4 Mask                */\r
-#define PORT2_PDR0_PD5_Pos                                    20                                                        /*!< PORT2 PDR0: PD5 Position            */\r
-#define PORT2_PDR0_PD5_Msk                                    (0x07UL << PORT2_PDR0_PD5_Pos)                            /*!< PORT2 PDR0: PD5 Mask                */\r
-#define PORT2_PDR0_PD6_Pos                                    24                                                        /*!< PORT2 PDR0: PD6 Position            */\r
-#define PORT2_PDR0_PD6_Msk                                    (0x07UL << PORT2_PDR0_PD6_Pos)                            /*!< PORT2 PDR0: PD6 Mask                */\r
-#define PORT2_PDR0_PD7_Pos                                    28                                                        /*!< PORT2 PDR0: PD7 Position            */\r
-#define PORT2_PDR0_PD7_Msk                                    (0x07UL << PORT2_PDR0_PD7_Pos)                            /*!< PORT2 PDR0: PD7 Mask                */\r
-\r
-// ---------------------------------------  PORT2_PDR1  -------------------------------------------\r
-#define PORT2_PDR1_PD8_Pos                                    0                                                         /*!< PORT2 PDR1: PD8 Position            */\r
-#define PORT2_PDR1_PD8_Msk                                    (0x07UL << PORT2_PDR1_PD8_Pos)                            /*!< PORT2 PDR1: PD8 Mask                */\r
-#define PORT2_PDR1_PD9_Pos                                    4                                                         /*!< PORT2 PDR1: PD9 Position            */\r
-#define PORT2_PDR1_PD9_Msk                                    (0x07UL << PORT2_PDR1_PD9_Pos)                            /*!< PORT2 PDR1: PD9 Mask                */\r
-#define PORT2_PDR1_PD10_Pos                                   8                                                         /*!< PORT2 PDR1: PD10 Position           */\r
-#define PORT2_PDR1_PD10_Msk                                   (0x07UL << PORT2_PDR1_PD10_Pos)                           /*!< PORT2 PDR1: PD10 Mask               */\r
-#define PORT2_PDR1_PD11_Pos                                   12                                                        /*!< PORT2 PDR1: PD11 Position           */\r
-#define PORT2_PDR1_PD11_Msk                                   (0x07UL << PORT2_PDR1_PD11_Pos)                           /*!< PORT2 PDR1: PD11 Mask               */\r
-#define PORT2_PDR1_PD12_Pos                                   16                                                        /*!< PORT2 PDR1: PD12 Position           */\r
-#define PORT2_PDR1_PD12_Msk                                   (0x07UL << PORT2_PDR1_PD12_Pos)                           /*!< PORT2 PDR1: PD12 Mask               */\r
-#define PORT2_PDR1_PD13_Pos                                   20                                                        /*!< PORT2 PDR1: PD13 Position           */\r
-#define PORT2_PDR1_PD13_Msk                                   (0x07UL << PORT2_PDR1_PD13_Pos)                           /*!< PORT2 PDR1: PD13 Mask               */\r
-#define PORT2_PDR1_PD14_Pos                                   24                                                        /*!< PORT2 PDR1: PD14 Position           */\r
-#define PORT2_PDR1_PD14_Msk                                   (0x07UL << PORT2_PDR1_PD14_Pos)                           /*!< PORT2 PDR1: PD14 Mask               */\r
-#define PORT2_PDR1_PD15_Pos                                   28                                                        /*!< PORT2 PDR1: PD15 Position           */\r
-#define PORT2_PDR1_PD15_Msk                                   (0x07UL << PORT2_PDR1_PD15_Pos)                           /*!< PORT2 PDR1: PD15 Mask               */\r
-\r
-// ---------------------------------------  PORT2_PDISC  ------------------------------------------\r
-#define PORT2_PDISC_PDIS0_Pos                                 0                                                         /*!< PORT2 PDISC: PDIS0 Position         */\r
-#define PORT2_PDISC_PDIS0_Msk                                 (0x01UL << PORT2_PDISC_PDIS0_Pos)                         /*!< PORT2 PDISC: PDIS0 Mask             */\r
-#define PORT2_PDISC_PDIS1_Pos                                 1                                                         /*!< PORT2 PDISC: PDIS1 Position         */\r
-#define PORT2_PDISC_PDIS1_Msk                                 (0x01UL << PORT2_PDISC_PDIS1_Pos)                         /*!< PORT2 PDISC: PDIS1 Mask             */\r
-#define PORT2_PDISC_PDIS2_Pos                                 2                                                         /*!< PORT2 PDISC: PDIS2 Position         */\r
-#define PORT2_PDISC_PDIS2_Msk                                 (0x01UL << PORT2_PDISC_PDIS2_Pos)                         /*!< PORT2 PDISC: PDIS2 Mask             */\r
-#define PORT2_PDISC_PDIS3_Pos                                 3                                                         /*!< PORT2 PDISC: PDIS3 Position         */\r
-#define PORT2_PDISC_PDIS3_Msk                                 (0x01UL << PORT2_PDISC_PDIS3_Pos)                         /*!< PORT2 PDISC: PDIS3 Mask             */\r
-#define PORT2_PDISC_PDIS4_Pos                                 4                                                         /*!< PORT2 PDISC: PDIS4 Position         */\r
-#define PORT2_PDISC_PDIS4_Msk                                 (0x01UL << PORT2_PDISC_PDIS4_Pos)                         /*!< PORT2 PDISC: PDIS4 Mask             */\r
-#define PORT2_PDISC_PDIS5_Pos                                 5                                                         /*!< PORT2 PDISC: PDIS5 Position         */\r
-#define PORT2_PDISC_PDIS5_Msk                                 (0x01UL << PORT2_PDISC_PDIS5_Pos)                         /*!< PORT2 PDISC: PDIS5 Mask             */\r
-#define PORT2_PDISC_PDIS6_Pos                                 6                                                         /*!< PORT2 PDISC: PDIS6 Position         */\r
-#define PORT2_PDISC_PDIS6_Msk                                 (0x01UL << PORT2_PDISC_PDIS6_Pos)                         /*!< PORT2 PDISC: PDIS6 Mask             */\r
-#define PORT2_PDISC_PDIS7_Pos                                 7                                                         /*!< PORT2 PDISC: PDIS7 Position         */\r
-#define PORT2_PDISC_PDIS7_Msk                                 (0x01UL << PORT2_PDISC_PDIS7_Pos)                         /*!< PORT2 PDISC: PDIS7 Mask             */\r
-#define PORT2_PDISC_PDIS8_Pos                                 8                                                         /*!< PORT2 PDISC: PDIS8 Position         */\r
-#define PORT2_PDISC_PDIS8_Msk                                 (0x01UL << PORT2_PDISC_PDIS8_Pos)                         /*!< PORT2 PDISC: PDIS8 Mask             */\r
-#define PORT2_PDISC_PDIS9_Pos                                 9                                                         /*!< PORT2 PDISC: PDIS9 Position         */\r
-#define PORT2_PDISC_PDIS9_Msk                                 (0x01UL << PORT2_PDISC_PDIS9_Pos)                         /*!< PORT2 PDISC: PDIS9 Mask             */\r
-#define PORT2_PDISC_PDIS10_Pos                                10                                                        /*!< PORT2 PDISC: PDIS10 Position        */\r
-#define PORT2_PDISC_PDIS10_Msk                                (0x01UL << PORT2_PDISC_PDIS10_Pos)                        /*!< PORT2 PDISC: PDIS10 Mask            */\r
-#define PORT2_PDISC_PDIS11_Pos                                11                                                        /*!< PORT2 PDISC: PDIS11 Position        */\r
-#define PORT2_PDISC_PDIS11_Msk                                (0x01UL << PORT2_PDISC_PDIS11_Pos)                        /*!< PORT2 PDISC: PDIS11 Mask            */\r
-#define PORT2_PDISC_PDIS12_Pos                                12                                                        /*!< PORT2 PDISC: PDIS12 Position        */\r
-#define PORT2_PDISC_PDIS12_Msk                                (0x01UL << PORT2_PDISC_PDIS12_Pos)                        /*!< PORT2 PDISC: PDIS12 Mask            */\r
-#define PORT2_PDISC_PDIS13_Pos                                13                                                        /*!< PORT2 PDISC: PDIS13 Position        */\r
-#define PORT2_PDISC_PDIS13_Msk                                (0x01UL << PORT2_PDISC_PDIS13_Pos)                        /*!< PORT2 PDISC: PDIS13 Mask            */\r
-#define PORT2_PDISC_PDIS14_Pos                                14                                                        /*!< PORT2 PDISC: PDIS14 Position        */\r
-#define PORT2_PDISC_PDIS14_Msk                                (0x01UL << PORT2_PDISC_PDIS14_Pos)                        /*!< PORT2 PDISC: PDIS14 Mask            */\r
-#define PORT2_PDISC_PDIS15_Pos                                15                                                        /*!< PORT2 PDISC: PDIS15 Position        */\r
-#define PORT2_PDISC_PDIS15_Msk                                (0x01UL << PORT2_PDISC_PDIS15_Pos)                        /*!< PORT2 PDISC: PDIS15 Mask            */\r
-\r
-// ----------------------------------------  PORT2_PPS  -------------------------------------------\r
-#define PORT2_PPS_PPS0_Pos                                    0                                                         /*!< PORT2 PPS: PPS0 Position            */\r
-#define PORT2_PPS_PPS0_Msk                                    (0x01UL << PORT2_PPS_PPS0_Pos)                            /*!< PORT2 PPS: PPS0 Mask                */\r
-#define PORT2_PPS_PPS1_Pos                                    1                                                         /*!< PORT2 PPS: PPS1 Position            */\r
-#define PORT2_PPS_PPS1_Msk                                    (0x01UL << PORT2_PPS_PPS1_Pos)                            /*!< PORT2 PPS: PPS1 Mask                */\r
-#define PORT2_PPS_PPS2_Pos                                    2                                                         /*!< PORT2 PPS: PPS2 Position            */\r
-#define PORT2_PPS_PPS2_Msk                                    (0x01UL << PORT2_PPS_PPS2_Pos)                            /*!< PORT2 PPS: PPS2 Mask                */\r
-#define PORT2_PPS_PPS3_Pos                                    3                                                         /*!< PORT2 PPS: PPS3 Position            */\r
-#define PORT2_PPS_PPS3_Msk                                    (0x01UL << PORT2_PPS_PPS3_Pos)                            /*!< PORT2 PPS: PPS3 Mask                */\r
-#define PORT2_PPS_PPS4_Pos                                    4                                                         /*!< PORT2 PPS: PPS4 Position            */\r
-#define PORT2_PPS_PPS4_Msk                                    (0x01UL << PORT2_PPS_PPS4_Pos)                            /*!< PORT2 PPS: PPS4 Mask                */\r
-#define PORT2_PPS_PPS5_Pos                                    5                                                         /*!< PORT2 PPS: PPS5 Position            */\r
-#define PORT2_PPS_PPS5_Msk                                    (0x01UL << PORT2_PPS_PPS5_Pos)                            /*!< PORT2 PPS: PPS5 Mask                */\r
-#define PORT2_PPS_PPS6_Pos                                    6                                                         /*!< PORT2 PPS: PPS6 Position            */\r
-#define PORT2_PPS_PPS6_Msk                                    (0x01UL << PORT2_PPS_PPS6_Pos)                            /*!< PORT2 PPS: PPS6 Mask                */\r
-#define PORT2_PPS_PPS7_Pos                                    7                                                         /*!< PORT2 PPS: PPS7 Position            */\r
-#define PORT2_PPS_PPS7_Msk                                    (0x01UL << PORT2_PPS_PPS7_Pos)                            /*!< PORT2 PPS: PPS7 Mask                */\r
-#define PORT2_PPS_PPS8_Pos                                    8                                                         /*!< PORT2 PPS: PPS8 Position            */\r
-#define PORT2_PPS_PPS8_Msk                                    (0x01UL << PORT2_PPS_PPS8_Pos)                            /*!< PORT2 PPS: PPS8 Mask                */\r
-#define PORT2_PPS_PPS9_Pos                                    9                                                         /*!< PORT2 PPS: PPS9 Position            */\r
-#define PORT2_PPS_PPS9_Msk                                    (0x01UL << PORT2_PPS_PPS9_Pos)                            /*!< PORT2 PPS: PPS9 Mask                */\r
-#define PORT2_PPS_PPS10_Pos                                   10                                                        /*!< PORT2 PPS: PPS10 Position           */\r
-#define PORT2_PPS_PPS10_Msk                                   (0x01UL << PORT2_PPS_PPS10_Pos)                           /*!< PORT2 PPS: PPS10 Mask               */\r
-#define PORT2_PPS_PPS11_Pos                                   11                                                        /*!< PORT2 PPS: PPS11 Position           */\r
-#define PORT2_PPS_PPS11_Msk                                   (0x01UL << PORT2_PPS_PPS11_Pos)                           /*!< PORT2 PPS: PPS11 Mask               */\r
-#define PORT2_PPS_PPS12_Pos                                   12                                                        /*!< PORT2 PPS: PPS12 Position           */\r
-#define PORT2_PPS_PPS12_Msk                                   (0x01UL << PORT2_PPS_PPS12_Pos)                           /*!< PORT2 PPS: PPS12 Mask               */\r
-#define PORT2_PPS_PPS13_Pos                                   13                                                        /*!< PORT2 PPS: PPS13 Position           */\r
-#define PORT2_PPS_PPS13_Msk                                   (0x01UL << PORT2_PPS_PPS13_Pos)                           /*!< PORT2 PPS: PPS13 Mask               */\r
-#define PORT2_PPS_PPS14_Pos                                   14                                                        /*!< PORT2 PPS: PPS14 Position           */\r
-#define PORT2_PPS_PPS14_Msk                                   (0x01UL << PORT2_PPS_PPS14_Pos)                           /*!< PORT2 PPS: PPS14 Mask               */\r
-#define PORT2_PPS_PPS15_Pos                                   15                                                        /*!< PORT2 PPS: PPS15 Position           */\r
-#define PORT2_PPS_PPS15_Msk                                   (0x01UL << PORT2_PPS_PPS15_Pos)                           /*!< PORT2 PPS: PPS15 Mask               */\r
-\r
-// ---------------------------------------  PORT2_HWSEL  ------------------------------------------\r
-#define PORT2_HWSEL_HW0_Pos                                   0                                                         /*!< PORT2 HWSEL: HW0 Position           */\r
-#define PORT2_HWSEL_HW0_Msk                                   (0x03UL << PORT2_HWSEL_HW0_Pos)                           /*!< PORT2 HWSEL: HW0 Mask               */\r
-#define PORT2_HWSEL_HW1_Pos                                   2                                                         /*!< PORT2 HWSEL: HW1 Position           */\r
-#define PORT2_HWSEL_HW1_Msk                                   (0x03UL << PORT2_HWSEL_HW1_Pos)                           /*!< PORT2 HWSEL: HW1 Mask               */\r
-#define PORT2_HWSEL_HW2_Pos                                   4                                                         /*!< PORT2 HWSEL: HW2 Position           */\r
-#define PORT2_HWSEL_HW2_Msk                                   (0x03UL << PORT2_HWSEL_HW2_Pos)                           /*!< PORT2 HWSEL: HW2 Mask               */\r
-#define PORT2_HWSEL_HW3_Pos                                   6                                                         /*!< PORT2 HWSEL: HW3 Position           */\r
-#define PORT2_HWSEL_HW3_Msk                                   (0x03UL << PORT2_HWSEL_HW3_Pos)                           /*!< PORT2 HWSEL: HW3 Mask               */\r
-#define PORT2_HWSEL_HW4_Pos                                   8                                                         /*!< PORT2 HWSEL: HW4 Position           */\r
-#define PORT2_HWSEL_HW4_Msk                                   (0x03UL << PORT2_HWSEL_HW4_Pos)                           /*!< PORT2 HWSEL: HW4 Mask               */\r
-#define PORT2_HWSEL_HW5_Pos                                   10                                                        /*!< PORT2 HWSEL: HW5 Position           */\r
-#define PORT2_HWSEL_HW5_Msk                                   (0x03UL << PORT2_HWSEL_HW5_Pos)                           /*!< PORT2 HWSEL: HW5 Mask               */\r
-#define PORT2_HWSEL_HW6_Pos                                   12                                                        /*!< PORT2 HWSEL: HW6 Position           */\r
-#define PORT2_HWSEL_HW6_Msk                                   (0x03UL << PORT2_HWSEL_HW6_Pos)                           /*!< PORT2 HWSEL: HW6 Mask               */\r
-#define PORT2_HWSEL_HW7_Pos                                   14                                                        /*!< PORT2 HWSEL: HW7 Position           */\r
-#define PORT2_HWSEL_HW7_Msk                                   (0x03UL << PORT2_HWSEL_HW7_Pos)                           /*!< PORT2 HWSEL: HW7 Mask               */\r
-#define PORT2_HWSEL_HW8_Pos                                   16                                                        /*!< PORT2 HWSEL: HW8 Position           */\r
-#define PORT2_HWSEL_HW8_Msk                                   (0x03UL << PORT2_HWSEL_HW8_Pos)                           /*!< PORT2 HWSEL: HW8 Mask               */\r
-#define PORT2_HWSEL_HW9_Pos                                   18                                                        /*!< PORT2 HWSEL: HW9 Position           */\r
-#define PORT2_HWSEL_HW9_Msk                                   (0x03UL << PORT2_HWSEL_HW9_Pos)                           /*!< PORT2 HWSEL: HW9 Mask               */\r
-#define PORT2_HWSEL_HW10_Pos                                  20                                                        /*!< PORT2 HWSEL: HW10 Position          */\r
-#define PORT2_HWSEL_HW10_Msk                                  (0x03UL << PORT2_HWSEL_HW10_Pos)                          /*!< PORT2 HWSEL: HW10 Mask              */\r
-#define PORT2_HWSEL_HW11_Pos                                  22                                                        /*!< PORT2 HWSEL: HW11 Position          */\r
-#define PORT2_HWSEL_HW11_Msk                                  (0x03UL << PORT2_HWSEL_HW11_Pos)                          /*!< PORT2 HWSEL: HW11 Mask              */\r
-#define PORT2_HWSEL_HW12_Pos                                  24                                                        /*!< PORT2 HWSEL: HW12 Position          */\r
-#define PORT2_HWSEL_HW12_Msk                                  (0x03UL << PORT2_HWSEL_HW12_Pos)                          /*!< PORT2 HWSEL: HW12 Mask              */\r
-#define PORT2_HWSEL_HW13_Pos                                  26                                                        /*!< PORT2 HWSEL: HW13 Position          */\r
-#define PORT2_HWSEL_HW13_Msk                                  (0x03UL << PORT2_HWSEL_HW13_Pos)                          /*!< PORT2 HWSEL: HW13 Mask              */\r
-#define PORT2_HWSEL_HW14_Pos                                  28                                                        /*!< PORT2 HWSEL: HW14 Position          */\r
-#define PORT2_HWSEL_HW14_Msk                                  (0x03UL << PORT2_HWSEL_HW14_Pos)                          /*!< PORT2 HWSEL: HW14 Mask              */\r
-#define PORT2_HWSEL_HW15_Pos                                  30                                                        /*!< PORT2 HWSEL: HW15 Position          */\r
-#define PORT2_HWSEL_HW15_Msk                                  (0x03UL << PORT2_HWSEL_HW15_Pos)                          /*!< PORT2 HWSEL: HW15 Mask              */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                 PORT3 Position & Mask                                -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------  PORT3_OUT  -------------------------------------------\r
-#define PORT3_OUT_P0_Pos                                      0                                                         /*!< PORT3 OUT: P0 Position              */\r
-#define PORT3_OUT_P0_Msk                                      (0x01UL << PORT3_OUT_P0_Pos)                              /*!< PORT3 OUT: P0 Mask                  */\r
-#define PORT3_OUT_P1_Pos                                      1                                                         /*!< PORT3 OUT: P1 Position              */\r
-#define PORT3_OUT_P1_Msk                                      (0x01UL << PORT3_OUT_P1_Pos)                              /*!< PORT3 OUT: P1 Mask                  */\r
-#define PORT3_OUT_P2_Pos                                      2                                                         /*!< PORT3 OUT: P2 Position              */\r
-#define PORT3_OUT_P2_Msk                                      (0x01UL << PORT3_OUT_P2_Pos)                              /*!< PORT3 OUT: P2 Mask                  */\r
-#define PORT3_OUT_P3_Pos                                      3                                                         /*!< PORT3 OUT: P3 Position              */\r
-#define PORT3_OUT_P3_Msk                                      (0x01UL << PORT3_OUT_P3_Pos)                              /*!< PORT3 OUT: P3 Mask                  */\r
-#define PORT3_OUT_P4_Pos                                      4                                                         /*!< PORT3 OUT: P4 Position              */\r
-#define PORT3_OUT_P4_Msk                                      (0x01UL << PORT3_OUT_P4_Pos)                              /*!< PORT3 OUT: P4 Mask                  */\r
-#define PORT3_OUT_P5_Pos                                      5                                                         /*!< PORT3 OUT: P5 Position              */\r
-#define PORT3_OUT_P5_Msk                                      (0x01UL << PORT3_OUT_P5_Pos)                              /*!< PORT3 OUT: P5 Mask                  */\r
-#define PORT3_OUT_P6_Pos                                      6                                                         /*!< PORT3 OUT: P6 Position              */\r
-#define PORT3_OUT_P6_Msk                                      (0x01UL << PORT3_OUT_P6_Pos)                              /*!< PORT3 OUT: P6 Mask                  */\r
-#define PORT3_OUT_P7_Pos                                      7                                                         /*!< PORT3 OUT: P7 Position              */\r
-#define PORT3_OUT_P7_Msk                                      (0x01UL << PORT3_OUT_P7_Pos)                              /*!< PORT3 OUT: P7 Mask                  */\r
-#define PORT3_OUT_P8_Pos                                      8                                                         /*!< PORT3 OUT: P8 Position              */\r
-#define PORT3_OUT_P8_Msk                                      (0x01UL << PORT3_OUT_P8_Pos)                              /*!< PORT3 OUT: P8 Mask                  */\r
-#define PORT3_OUT_P9_Pos                                      9                                                         /*!< PORT3 OUT: P9 Position              */\r
-#define PORT3_OUT_P9_Msk                                      (0x01UL << PORT3_OUT_P9_Pos)                              /*!< PORT3 OUT: P9 Mask                  */\r
-#define PORT3_OUT_P10_Pos                                     10                                                        /*!< PORT3 OUT: P10 Position             */\r
-#define PORT3_OUT_P10_Msk                                     (0x01UL << PORT3_OUT_P10_Pos)                             /*!< PORT3 OUT: P10 Mask                 */\r
-#define PORT3_OUT_P11_Pos                                     11                                                        /*!< PORT3 OUT: P11 Position             */\r
-#define PORT3_OUT_P11_Msk                                     (0x01UL << PORT3_OUT_P11_Pos)                             /*!< PORT3 OUT: P11 Mask                 */\r
-#define PORT3_OUT_P12_Pos                                     12                                                        /*!< PORT3 OUT: P12 Position             */\r
-#define PORT3_OUT_P12_Msk                                     (0x01UL << PORT3_OUT_P12_Pos)                             /*!< PORT3 OUT: P12 Mask                 */\r
-#define PORT3_OUT_P13_Pos                                     13                                                        /*!< PORT3 OUT: P13 Position             */\r
-#define PORT3_OUT_P13_Msk                                     (0x01UL << PORT3_OUT_P13_Pos)                             /*!< PORT3 OUT: P13 Mask                 */\r
-#define PORT3_OUT_P14_Pos                                     14                                                        /*!< PORT3 OUT: P14 Position             */\r
-#define PORT3_OUT_P14_Msk                                     (0x01UL << PORT3_OUT_P14_Pos)                             /*!< PORT3 OUT: P14 Mask                 */\r
-#define PORT3_OUT_P15_Pos                                     15                                                        /*!< PORT3 OUT: P15 Position             */\r
-#define PORT3_OUT_P15_Msk                                     (0x01UL << PORT3_OUT_P15_Pos)                             /*!< PORT3 OUT: P15 Mask                 */\r
-\r
-// ----------------------------------------  PORT3_OMR  -------------------------------------------\r
-#define PORT3_OMR_PS0_Pos                                     0                                                         /*!< PORT3 OMR: PS0 Position             */\r
-#define PORT3_OMR_PS0_Msk                                     (0x01UL << PORT3_OMR_PS0_Pos)                             /*!< PORT3 OMR: PS0 Mask                 */\r
-#define PORT3_OMR_PS1_Pos                                     1                                                         /*!< PORT3 OMR: PS1 Position             */\r
-#define PORT3_OMR_PS1_Msk                                     (0x01UL << PORT3_OMR_PS1_Pos)                             /*!< PORT3 OMR: PS1 Mask                 */\r
-#define PORT3_OMR_PS2_Pos                                     2                                                         /*!< PORT3 OMR: PS2 Position             */\r
-#define PORT3_OMR_PS2_Msk                                     (0x01UL << PORT3_OMR_PS2_Pos)                             /*!< PORT3 OMR: PS2 Mask                 */\r
-#define PORT3_OMR_PS3_Pos                                     3                                                         /*!< PORT3 OMR: PS3 Position             */\r
-#define PORT3_OMR_PS3_Msk                                     (0x01UL << PORT3_OMR_PS3_Pos)                             /*!< PORT3 OMR: PS3 Mask                 */\r
-#define PORT3_OMR_PS4_Pos                                     4                                                         /*!< PORT3 OMR: PS4 Position             */\r
-#define PORT3_OMR_PS4_Msk                                     (0x01UL << PORT3_OMR_PS4_Pos)                             /*!< PORT3 OMR: PS4 Mask                 */\r
-#define PORT3_OMR_PS5_Pos                                     5                                                         /*!< PORT3 OMR: PS5 Position             */\r
-#define PORT3_OMR_PS5_Msk                                     (0x01UL << PORT3_OMR_PS5_Pos)                             /*!< PORT3 OMR: PS5 Mask                 */\r
-#define PORT3_OMR_PS6_Pos                                     6                                                         /*!< PORT3 OMR: PS6 Position             */\r
-#define PORT3_OMR_PS6_Msk                                     (0x01UL << PORT3_OMR_PS6_Pos)                             /*!< PORT3 OMR: PS6 Mask                 */\r
-#define PORT3_OMR_PS7_Pos                                     7                                                         /*!< PORT3 OMR: PS7 Position             */\r
-#define PORT3_OMR_PS7_Msk                                     (0x01UL << PORT3_OMR_PS7_Pos)                             /*!< PORT3 OMR: PS7 Mask                 */\r
-#define PORT3_OMR_PS8_Pos                                     8                                                         /*!< PORT3 OMR: PS8 Position             */\r
-#define PORT3_OMR_PS8_Msk                                     (0x01UL << PORT3_OMR_PS8_Pos)                             /*!< PORT3 OMR: PS8 Mask                 */\r
-#define PORT3_OMR_PS9_Pos                                     9                                                         /*!< PORT3 OMR: PS9 Position             */\r
-#define PORT3_OMR_PS9_Msk                                     (0x01UL << PORT3_OMR_PS9_Pos)                             /*!< PORT3 OMR: PS9 Mask                 */\r
-#define PORT3_OMR_PS10_Pos                                    10                                                        /*!< PORT3 OMR: PS10 Position            */\r
-#define PORT3_OMR_PS10_Msk                                    (0x01UL << PORT3_OMR_PS10_Pos)                            /*!< PORT3 OMR: PS10 Mask                */\r
-#define PORT3_OMR_PS11_Pos                                    11                                                        /*!< PORT3 OMR: PS11 Position            */\r
-#define PORT3_OMR_PS11_Msk                                    (0x01UL << PORT3_OMR_PS11_Pos)                            /*!< PORT3 OMR: PS11 Mask                */\r
-#define PORT3_OMR_PS12_Pos                                    12                                                        /*!< PORT3 OMR: PS12 Position            */\r
-#define PORT3_OMR_PS12_Msk                                    (0x01UL << PORT3_OMR_PS12_Pos)                            /*!< PORT3 OMR: PS12 Mask                */\r
-#define PORT3_OMR_PS13_Pos                                    13                                                        /*!< PORT3 OMR: PS13 Position            */\r
-#define PORT3_OMR_PS13_Msk                                    (0x01UL << PORT3_OMR_PS13_Pos)                            /*!< PORT3 OMR: PS13 Mask                */\r
-#define PORT3_OMR_PS14_Pos                                    14                                                        /*!< PORT3 OMR: PS14 Position            */\r
-#define PORT3_OMR_PS14_Msk                                    (0x01UL << PORT3_OMR_PS14_Pos)                            /*!< PORT3 OMR: PS14 Mask                */\r
-#define PORT3_OMR_PS15_Pos                                    15                                                        /*!< PORT3 OMR: PS15 Position            */\r
-#define PORT3_OMR_PS15_Msk                                    (0x01UL << PORT3_OMR_PS15_Pos)                            /*!< PORT3 OMR: PS15 Mask                */\r
-#define PORT3_OMR_PR0_Pos                                     16                                                        /*!< PORT3 OMR: PR0 Position             */\r
-#define PORT3_OMR_PR0_Msk                                     (0x01UL << PORT3_OMR_PR0_Pos)                             /*!< PORT3 OMR: PR0 Mask                 */\r
-#define PORT3_OMR_PR1_Pos                                     17                                                        /*!< PORT3 OMR: PR1 Position             */\r
-#define PORT3_OMR_PR1_Msk                                     (0x01UL << PORT3_OMR_PR1_Pos)                             /*!< PORT3 OMR: PR1 Mask                 */\r
-#define PORT3_OMR_PR2_Pos                                     18                                                        /*!< PORT3 OMR: PR2 Position             */\r
-#define PORT3_OMR_PR2_Msk                                     (0x01UL << PORT3_OMR_PR2_Pos)                             /*!< PORT3 OMR: PR2 Mask                 */\r
-#define PORT3_OMR_PR3_Pos                                     19                                                        /*!< PORT3 OMR: PR3 Position             */\r
-#define PORT3_OMR_PR3_Msk                                     (0x01UL << PORT3_OMR_PR3_Pos)                             /*!< PORT3 OMR: PR3 Mask                 */\r
-#define PORT3_OMR_PR4_Pos                                     20                                                        /*!< PORT3 OMR: PR4 Position             */\r
-#define PORT3_OMR_PR4_Msk                                     (0x01UL << PORT3_OMR_PR4_Pos)                             /*!< PORT3 OMR: PR4 Mask                 */\r
-#define PORT3_OMR_PR5_Pos                                     21                                                        /*!< PORT3 OMR: PR5 Position             */\r
-#define PORT3_OMR_PR5_Msk                                     (0x01UL << PORT3_OMR_PR5_Pos)                             /*!< PORT3 OMR: PR5 Mask                 */\r
-#define PORT3_OMR_PR6_Pos                                     22                                                        /*!< PORT3 OMR: PR6 Position             */\r
-#define PORT3_OMR_PR6_Msk                                     (0x01UL << PORT3_OMR_PR6_Pos)                             /*!< PORT3 OMR: PR6 Mask                 */\r
-#define PORT3_OMR_PR7_Pos                                     23                                                        /*!< PORT3 OMR: PR7 Position             */\r
-#define PORT3_OMR_PR7_Msk                                     (0x01UL << PORT3_OMR_PR7_Pos)                             /*!< PORT3 OMR: PR7 Mask                 */\r
-#define PORT3_OMR_PR8_Pos                                     24                                                        /*!< PORT3 OMR: PR8 Position             */\r
-#define PORT3_OMR_PR8_Msk                                     (0x01UL << PORT3_OMR_PR8_Pos)                             /*!< PORT3 OMR: PR8 Mask                 */\r
-#define PORT3_OMR_PR9_Pos                                     25                                                        /*!< PORT3 OMR: PR9 Position             */\r
-#define PORT3_OMR_PR9_Msk                                     (0x01UL << PORT3_OMR_PR9_Pos)                             /*!< PORT3 OMR: PR9 Mask                 */\r
-#define PORT3_OMR_PR10_Pos                                    26                                                        /*!< PORT3 OMR: PR10 Position            */\r
-#define PORT3_OMR_PR10_Msk                                    (0x01UL << PORT3_OMR_PR10_Pos)                            /*!< PORT3 OMR: PR10 Mask                */\r
-#define PORT3_OMR_PR11_Pos                                    27                                                        /*!< PORT3 OMR: PR11 Position            */\r
-#define PORT3_OMR_PR11_Msk                                    (0x01UL << PORT3_OMR_PR11_Pos)                            /*!< PORT3 OMR: PR11 Mask                */\r
-#define PORT3_OMR_PR12_Pos                                    28                                                        /*!< PORT3 OMR: PR12 Position            */\r
-#define PORT3_OMR_PR12_Msk                                    (0x01UL << PORT3_OMR_PR12_Pos)                            /*!< PORT3 OMR: PR12 Mask                */\r
-#define PORT3_OMR_PR13_Pos                                    29                                                        /*!< PORT3 OMR: PR13 Position            */\r
-#define PORT3_OMR_PR13_Msk                                    (0x01UL << PORT3_OMR_PR13_Pos)                            /*!< PORT3 OMR: PR13 Mask                */\r
-#define PORT3_OMR_PR14_Pos                                    30                                                        /*!< PORT3 OMR: PR14 Position            */\r
-#define PORT3_OMR_PR14_Msk                                    (0x01UL << PORT3_OMR_PR14_Pos)                            /*!< PORT3 OMR: PR14 Mask                */\r
-#define PORT3_OMR_PR15_Pos                                    31                                                        /*!< PORT3 OMR: PR15 Position            */\r
-#define PORT3_OMR_PR15_Msk                                    (0x01UL << PORT3_OMR_PR15_Pos)                            /*!< PORT3 OMR: PR15 Mask                */\r
-\r
-// ---------------------------------------  PORT3_IOCR0  ------------------------------------------\r
-#define PORT3_IOCR0_PC0_Pos                                   3                                                         /*!< PORT3 IOCR0: PC0 Position           */\r
-#define PORT3_IOCR0_PC0_Msk                                   (0x1fUL << PORT3_IOCR0_PC0_Pos)                           /*!< PORT3 IOCR0: PC0 Mask               */\r
-#define PORT3_IOCR0_PC1_Pos                                   11                                                        /*!< PORT3 IOCR0: PC1 Position           */\r
-#define PORT3_IOCR0_PC1_Msk                                   (0x1fUL << PORT3_IOCR0_PC1_Pos)                           /*!< PORT3 IOCR0: PC1 Mask               */\r
-#define PORT3_IOCR0_PC2_Pos                                   19                                                        /*!< PORT3 IOCR0: PC2 Position           */\r
-#define PORT3_IOCR0_PC2_Msk                                   (0x1fUL << PORT3_IOCR0_PC2_Pos)                           /*!< PORT3 IOCR0: PC2 Mask               */\r
-#define PORT3_IOCR0_PC3_Pos                                   27                                                        /*!< PORT3 IOCR0: PC3 Position           */\r
-#define PORT3_IOCR0_PC3_Msk                                   (0x1fUL << PORT3_IOCR0_PC3_Pos)                           /*!< PORT3 IOCR0: PC3 Mask               */\r
-\r
-// ---------------------------------------  PORT3_IOCR4  ------------------------------------------\r
-#define PORT3_IOCR4_PC4_Pos                                   3                                                         /*!< PORT3 IOCR4: PC4 Position           */\r
-#define PORT3_IOCR4_PC4_Msk                                   (0x1fUL << PORT3_IOCR4_PC4_Pos)                           /*!< PORT3 IOCR4: PC4 Mask               */\r
-#define PORT3_IOCR4_PC5_Pos                                   11                                                        /*!< PORT3 IOCR4: PC5 Position           */\r
-#define PORT3_IOCR4_PC5_Msk                                   (0x1fUL << PORT3_IOCR4_PC5_Pos)                           /*!< PORT3 IOCR4: PC5 Mask               */\r
-#define PORT3_IOCR4_PC6_Pos                                   19                                                        /*!< PORT3 IOCR4: PC6 Position           */\r
-#define PORT3_IOCR4_PC6_Msk                                   (0x1fUL << PORT3_IOCR4_PC6_Pos)                           /*!< PORT3 IOCR4: PC6 Mask               */\r
-#define PORT3_IOCR4_PC7_Pos                                   27                                                        /*!< PORT3 IOCR4: PC7 Position           */\r
-#define PORT3_IOCR4_PC7_Msk                                   (0x1fUL << PORT3_IOCR4_PC7_Pos)                           /*!< PORT3 IOCR4: PC7 Mask               */\r
-\r
-// ---------------------------------------  PORT3_IOCR8  ------------------------------------------\r
-#define PORT3_IOCR8_PC8_Pos                                   3                                                         /*!< PORT3 IOCR8: PC8 Position           */\r
-#define PORT3_IOCR8_PC8_Msk                                   (0x1fUL << PORT3_IOCR8_PC8_Pos)                           /*!< PORT3 IOCR8: PC8 Mask               */\r
-#define PORT3_IOCR8_PC9_Pos                                   11                                                        /*!< PORT3 IOCR8: PC9 Position           */\r
-#define PORT3_IOCR8_PC9_Msk                                   (0x1fUL << PORT3_IOCR8_PC9_Pos)                           /*!< PORT3 IOCR8: PC9 Mask               */\r
-#define PORT3_IOCR8_PC10_Pos                                  19                                                        /*!< PORT3 IOCR8: PC10 Position          */\r
-#define PORT3_IOCR8_PC10_Msk                                  (0x1fUL << PORT3_IOCR8_PC10_Pos)                          /*!< PORT3 IOCR8: PC10 Mask              */\r
-#define PORT3_IOCR8_PC11_Pos                                  27                                                        /*!< PORT3 IOCR8: PC11 Position          */\r
-#define PORT3_IOCR8_PC11_Msk                                  (0x1fUL << PORT3_IOCR8_PC11_Pos)                          /*!< PORT3 IOCR8: PC11 Mask              */\r
-\r
-// --------------------------------------  PORT3_IOCR12  ------------------------------------------\r
-#define PORT3_IOCR12_PC12_Pos                                 3                                                         /*!< PORT3 IOCR12: PC12 Position         */\r
-#define PORT3_IOCR12_PC12_Msk                                 (0x1fUL << PORT3_IOCR12_PC12_Pos)                         /*!< PORT3 IOCR12: PC12 Mask             */\r
-#define PORT3_IOCR12_PC13_Pos                                 11                                                        /*!< PORT3 IOCR12: PC13 Position         */\r
-#define PORT3_IOCR12_PC13_Msk                                 (0x1fUL << PORT3_IOCR12_PC13_Pos)                         /*!< PORT3 IOCR12: PC13 Mask             */\r
-#define PORT3_IOCR12_PC14_Pos                                 19                                                        /*!< PORT3 IOCR12: PC14 Position         */\r
-#define PORT3_IOCR12_PC14_Msk                                 (0x1fUL << PORT3_IOCR12_PC14_Pos)                         /*!< PORT3 IOCR12: PC14 Mask             */\r
-#define PORT3_IOCR12_PC15_Pos                                 27                                                        /*!< PORT3 IOCR12: PC15 Position         */\r
-#define PORT3_IOCR12_PC15_Msk                                 (0x1fUL << PORT3_IOCR12_PC15_Pos)                         /*!< PORT3 IOCR12: PC15 Mask             */\r
-\r
-// ----------------------------------------  PORT3_IN  --------------------------------------------\r
-#define PORT3_IN_P0_Pos                                       0                                                         /*!< PORT3 IN: P0 Position               */\r
-#define PORT3_IN_P0_Msk                                       (0x01UL << PORT3_IN_P0_Pos)                               /*!< PORT3 IN: P0 Mask                   */\r
-#define PORT3_IN_P1_Pos                                       1                                                         /*!< PORT3 IN: P1 Position               */\r
-#define PORT3_IN_P1_Msk                                       (0x01UL << PORT3_IN_P1_Pos)                               /*!< PORT3 IN: P1 Mask                   */\r
-#define PORT3_IN_P2_Pos                                       2                                                         /*!< PORT3 IN: P2 Position               */\r
-#define PORT3_IN_P2_Msk                                       (0x01UL << PORT3_IN_P2_Pos)                               /*!< PORT3 IN: P2 Mask                   */\r
-#define PORT3_IN_P3_Pos                                       3                                                         /*!< PORT3 IN: P3 Position               */\r
-#define PORT3_IN_P3_Msk                                       (0x01UL << PORT3_IN_P3_Pos)                               /*!< PORT3 IN: P3 Mask                   */\r
-#define PORT3_IN_P4_Pos                                       4                                                         /*!< PORT3 IN: P4 Position               */\r
-#define PORT3_IN_P4_Msk                                       (0x01UL << PORT3_IN_P4_Pos)                               /*!< PORT3 IN: P4 Mask                   */\r
-#define PORT3_IN_P5_Pos                                       5                                                         /*!< PORT3 IN: P5 Position               */\r
-#define PORT3_IN_P5_Msk                                       (0x01UL << PORT3_IN_P5_Pos)                               /*!< PORT3 IN: P5 Mask                   */\r
-#define PORT3_IN_P6_Pos                                       6                                                         /*!< PORT3 IN: P6 Position               */\r
-#define PORT3_IN_P6_Msk                                       (0x01UL << PORT3_IN_P6_Pos)                               /*!< PORT3 IN: P6 Mask                   */\r
-#define PORT3_IN_P7_Pos                                       7                                                         /*!< PORT3 IN: P7 Position               */\r
-#define PORT3_IN_P7_Msk                                       (0x01UL << PORT3_IN_P7_Pos)                               /*!< PORT3 IN: P7 Mask                   */\r
-#define PORT3_IN_P8_Pos                                       8                                                         /*!< PORT3 IN: P8 Position               */\r
-#define PORT3_IN_P8_Msk                                       (0x01UL << PORT3_IN_P8_Pos)                               /*!< PORT3 IN: P8 Mask                   */\r
-#define PORT3_IN_P9_Pos                                       9                                                         /*!< PORT3 IN: P9 Position               */\r
-#define PORT3_IN_P9_Msk                                       (0x01UL << PORT3_IN_P9_Pos)                               /*!< PORT3 IN: P9 Mask                   */\r
-#define PORT3_IN_P10_Pos                                      10                                                        /*!< PORT3 IN: P10 Position              */\r
-#define PORT3_IN_P10_Msk                                      (0x01UL << PORT3_IN_P10_Pos)                              /*!< PORT3 IN: P10 Mask                  */\r
-#define PORT3_IN_P11_Pos                                      11                                                        /*!< PORT3 IN: P11 Position              */\r
-#define PORT3_IN_P11_Msk                                      (0x01UL << PORT3_IN_P11_Pos)                              /*!< PORT3 IN: P11 Mask                  */\r
-#define PORT3_IN_P12_Pos                                      12                                                        /*!< PORT3 IN: P12 Position              */\r
-#define PORT3_IN_P12_Msk                                      (0x01UL << PORT3_IN_P12_Pos)                              /*!< PORT3 IN: P12 Mask                  */\r
-#define PORT3_IN_P13_Pos                                      13                                                        /*!< PORT3 IN: P13 Position              */\r
-#define PORT3_IN_P13_Msk                                      (0x01UL << PORT3_IN_P13_Pos)                              /*!< PORT3 IN: P13 Mask                  */\r
-#define PORT3_IN_P14_Pos                                      14                                                        /*!< PORT3 IN: P14 Position              */\r
-#define PORT3_IN_P14_Msk                                      (0x01UL << PORT3_IN_P14_Pos)                              /*!< PORT3 IN: P14 Mask                  */\r
-#define PORT3_IN_P15_Pos                                      15                                                        /*!< PORT3 IN: P15 Position              */\r
-#define PORT3_IN_P15_Msk                                      (0x01UL << PORT3_IN_P15_Pos)                              /*!< PORT3 IN: P15 Mask                  */\r
-\r
-// ---------------------------------------  PORT3_PDR0  -------------------------------------------\r
-#define PORT3_PDR0_PD0_Pos                                    0                                                         /*!< PORT3 PDR0: PD0 Position            */\r
-#define PORT3_PDR0_PD0_Msk                                    (0x07UL << PORT3_PDR0_PD0_Pos)                            /*!< PORT3 PDR0: PD0 Mask                */\r
-#define PORT3_PDR0_PD1_Pos                                    4                                                         /*!< PORT3 PDR0: PD1 Position            */\r
-#define PORT3_PDR0_PD1_Msk                                    (0x07UL << PORT3_PDR0_PD1_Pos)                            /*!< PORT3 PDR0: PD1 Mask                */\r
-#define PORT3_PDR0_PD2_Pos                                    8                                                         /*!< PORT3 PDR0: PD2 Position            */\r
-#define PORT3_PDR0_PD2_Msk                                    (0x07UL << PORT3_PDR0_PD2_Pos)                            /*!< PORT3 PDR0: PD2 Mask                */\r
-#define PORT3_PDR0_PD3_Pos                                    12                                                        /*!< PORT3 PDR0: PD3 Position            */\r
-#define PORT3_PDR0_PD3_Msk                                    (0x07UL << PORT3_PDR0_PD3_Pos)                            /*!< PORT3 PDR0: PD3 Mask                */\r
-#define PORT3_PDR0_PD4_Pos                                    16                                                        /*!< PORT3 PDR0: PD4 Position            */\r
-#define PORT3_PDR0_PD4_Msk                                    (0x07UL << PORT3_PDR0_PD4_Pos)                            /*!< PORT3 PDR0: PD4 Mask                */\r
-#define PORT3_PDR0_PD5_Pos                                    20                                                        /*!< PORT3 PDR0: PD5 Position            */\r
-#define PORT3_PDR0_PD5_Msk                                    (0x07UL << PORT3_PDR0_PD5_Pos)                            /*!< PORT3 PDR0: PD5 Mask                */\r
-#define PORT3_PDR0_PD6_Pos                                    24                                                        /*!< PORT3 PDR0: PD6 Position            */\r
-#define PORT3_PDR0_PD6_Msk                                    (0x07UL << PORT3_PDR0_PD6_Pos)                            /*!< PORT3 PDR0: PD6 Mask                */\r
-#define PORT3_PDR0_PD7_Pos                                    28                                                        /*!< PORT3 PDR0: PD7 Position            */\r
-#define PORT3_PDR0_PD7_Msk                                    (0x07UL << PORT3_PDR0_PD7_Pos)                            /*!< PORT3 PDR0: PD7 Mask                */\r
-\r
-// ---------------------------------------  PORT3_PDR1  -------------------------------------------\r
-#define PORT3_PDR1_PD8_Pos                                    0                                                         /*!< PORT3 PDR1: PD8 Position            */\r
-#define PORT3_PDR1_PD8_Msk                                    (0x07UL << PORT3_PDR1_PD8_Pos)                            /*!< PORT3 PDR1: PD8 Mask                */\r
-#define PORT3_PDR1_PD9_Pos                                    4                                                         /*!< PORT3 PDR1: PD9 Position            */\r
-#define PORT3_PDR1_PD9_Msk                                    (0x07UL << PORT3_PDR1_PD9_Pos)                            /*!< PORT3 PDR1: PD9 Mask                */\r
-#define PORT3_PDR1_PD10_Pos                                   8                                                         /*!< PORT3 PDR1: PD10 Position           */\r
-#define PORT3_PDR1_PD10_Msk                                   (0x07UL << PORT3_PDR1_PD10_Pos)                           /*!< PORT3 PDR1: PD10 Mask               */\r
-#define PORT3_PDR1_PD11_Pos                                   12                                                        /*!< PORT3 PDR1: PD11 Position           */\r
-#define PORT3_PDR1_PD11_Msk                                   (0x07UL << PORT3_PDR1_PD11_Pos)                           /*!< PORT3 PDR1: PD11 Mask               */\r
-#define PORT3_PDR1_PD12_Pos                                   16                                                        /*!< PORT3 PDR1: PD12 Position           */\r
-#define PORT3_PDR1_PD12_Msk                                   (0x07UL << PORT3_PDR1_PD12_Pos)                           /*!< PORT3 PDR1: PD12 Mask               */\r
-#define PORT3_PDR1_PD13_Pos                                   20                                                        /*!< PORT3 PDR1: PD13 Position           */\r
-#define PORT3_PDR1_PD13_Msk                                   (0x07UL << PORT3_PDR1_PD13_Pos)                           /*!< PORT3 PDR1: PD13 Mask               */\r
-#define PORT3_PDR1_PD14_Pos                                   24                                                        /*!< PORT3 PDR1: PD14 Position           */\r
-#define PORT3_PDR1_PD14_Msk                                   (0x07UL << PORT3_PDR1_PD14_Pos)                           /*!< PORT3 PDR1: PD14 Mask               */\r
-#define PORT3_PDR1_PD15_Pos                                   28                                                        /*!< PORT3 PDR1: PD15 Position           */\r
-#define PORT3_PDR1_PD15_Msk                                   (0x07UL << PORT3_PDR1_PD15_Pos)                           /*!< PORT3 PDR1: PD15 Mask               */\r
-\r
-// ---------------------------------------  PORT3_PDISC  ------------------------------------------\r
-#define PORT3_PDISC_PDIS0_Pos                                 0                                                         /*!< PORT3 PDISC: PDIS0 Position         */\r
-#define PORT3_PDISC_PDIS0_Msk                                 (0x01UL << PORT3_PDISC_PDIS0_Pos)                         /*!< PORT3 PDISC: PDIS0 Mask             */\r
-#define PORT3_PDISC_PDIS1_Pos                                 1                                                         /*!< PORT3 PDISC: PDIS1 Position         */\r
-#define PORT3_PDISC_PDIS1_Msk                                 (0x01UL << PORT3_PDISC_PDIS1_Pos)                         /*!< PORT3 PDISC: PDIS1 Mask             */\r
-#define PORT3_PDISC_PDIS2_Pos                                 2                                                         /*!< PORT3 PDISC: PDIS2 Position         */\r
-#define PORT3_PDISC_PDIS2_Msk                                 (0x01UL << PORT3_PDISC_PDIS2_Pos)                         /*!< PORT3 PDISC: PDIS2 Mask             */\r
-#define PORT3_PDISC_PDIS3_Pos                                 3                                                         /*!< PORT3 PDISC: PDIS3 Position         */\r
-#define PORT3_PDISC_PDIS3_Msk                                 (0x01UL << PORT3_PDISC_PDIS3_Pos)                         /*!< PORT3 PDISC: PDIS3 Mask             */\r
-#define PORT3_PDISC_PDIS4_Pos                                 4                                                         /*!< PORT3 PDISC: PDIS4 Position         */\r
-#define PORT3_PDISC_PDIS4_Msk                                 (0x01UL << PORT3_PDISC_PDIS4_Pos)                         /*!< PORT3 PDISC: PDIS4 Mask             */\r
-#define PORT3_PDISC_PDIS5_Pos                                 5                                                         /*!< PORT3 PDISC: PDIS5 Position         */\r
-#define PORT3_PDISC_PDIS5_Msk                                 (0x01UL << PORT3_PDISC_PDIS5_Pos)                         /*!< PORT3 PDISC: PDIS5 Mask             */\r
-#define PORT3_PDISC_PDIS6_Pos                                 6                                                         /*!< PORT3 PDISC: PDIS6 Position         */\r
-#define PORT3_PDISC_PDIS6_Msk                                 (0x01UL << PORT3_PDISC_PDIS6_Pos)                         /*!< PORT3 PDISC: PDIS6 Mask             */\r
-#define PORT3_PDISC_PDIS7_Pos                                 7                                                         /*!< PORT3 PDISC: PDIS7 Position         */\r
-#define PORT3_PDISC_PDIS7_Msk                                 (0x01UL << PORT3_PDISC_PDIS7_Pos)                         /*!< PORT3 PDISC: PDIS7 Mask             */\r
-#define PORT3_PDISC_PDIS8_Pos                                 8                                                         /*!< PORT3 PDISC: PDIS8 Position         */\r
-#define PORT3_PDISC_PDIS8_Msk                                 (0x01UL << PORT3_PDISC_PDIS8_Pos)                         /*!< PORT3 PDISC: PDIS8 Mask             */\r
-#define PORT3_PDISC_PDIS9_Pos                                 9                                                         /*!< PORT3 PDISC: PDIS9 Position         */\r
-#define PORT3_PDISC_PDIS9_Msk                                 (0x01UL << PORT3_PDISC_PDIS9_Pos)                         /*!< PORT3 PDISC: PDIS9 Mask             */\r
-#define PORT3_PDISC_PDIS10_Pos                                10                                                        /*!< PORT3 PDISC: PDIS10 Position        */\r
-#define PORT3_PDISC_PDIS10_Msk                                (0x01UL << PORT3_PDISC_PDIS10_Pos)                        /*!< PORT3 PDISC: PDIS10 Mask            */\r
-#define PORT3_PDISC_PDIS11_Pos                                11                                                        /*!< PORT3 PDISC: PDIS11 Position        */\r
-#define PORT3_PDISC_PDIS11_Msk                                (0x01UL << PORT3_PDISC_PDIS11_Pos)                        /*!< PORT3 PDISC: PDIS11 Mask            */\r
-#define PORT3_PDISC_PDIS12_Pos                                12                                                        /*!< PORT3 PDISC: PDIS12 Position        */\r
-#define PORT3_PDISC_PDIS12_Msk                                (0x01UL << PORT3_PDISC_PDIS12_Pos)                        /*!< PORT3 PDISC: PDIS12 Mask            */\r
-#define PORT3_PDISC_PDIS13_Pos                                13                                                        /*!< PORT3 PDISC: PDIS13 Position        */\r
-#define PORT3_PDISC_PDIS13_Msk                                (0x01UL << PORT3_PDISC_PDIS13_Pos)                        /*!< PORT3 PDISC: PDIS13 Mask            */\r
-#define PORT3_PDISC_PDIS14_Pos                                14                                                        /*!< PORT3 PDISC: PDIS14 Position        */\r
-#define PORT3_PDISC_PDIS14_Msk                                (0x01UL << PORT3_PDISC_PDIS14_Pos)                        /*!< PORT3 PDISC: PDIS14 Mask            */\r
-#define PORT3_PDISC_PDIS15_Pos                                15                                                        /*!< PORT3 PDISC: PDIS15 Position        */\r
-#define PORT3_PDISC_PDIS15_Msk                                (0x01UL << PORT3_PDISC_PDIS15_Pos)                        /*!< PORT3 PDISC: PDIS15 Mask            */\r
-\r
-// ----------------------------------------  PORT3_PPS  -------------------------------------------\r
-#define PORT3_PPS_PPS0_Pos                                    0                                                         /*!< PORT3 PPS: PPS0 Position            */\r
-#define PORT3_PPS_PPS0_Msk                                    (0x01UL << PORT3_PPS_PPS0_Pos)                            /*!< PORT3 PPS: PPS0 Mask                */\r
-#define PORT3_PPS_PPS1_Pos                                    1                                                         /*!< PORT3 PPS: PPS1 Position            */\r
-#define PORT3_PPS_PPS1_Msk                                    (0x01UL << PORT3_PPS_PPS1_Pos)                            /*!< PORT3 PPS: PPS1 Mask                */\r
-#define PORT3_PPS_PPS2_Pos                                    2                                                         /*!< PORT3 PPS: PPS2 Position            */\r
-#define PORT3_PPS_PPS2_Msk                                    (0x01UL << PORT3_PPS_PPS2_Pos)                            /*!< PORT3 PPS: PPS2 Mask                */\r
-#define PORT3_PPS_PPS3_Pos                                    3                                                         /*!< PORT3 PPS: PPS3 Position            */\r
-#define PORT3_PPS_PPS3_Msk                                    (0x01UL << PORT3_PPS_PPS3_Pos)                            /*!< PORT3 PPS: PPS3 Mask                */\r
-#define PORT3_PPS_PPS4_Pos                                    4                                                         /*!< PORT3 PPS: PPS4 Position            */\r
-#define PORT3_PPS_PPS4_Msk                                    (0x01UL << PORT3_PPS_PPS4_Pos)                            /*!< PORT3 PPS: PPS4 Mask                */\r
-#define PORT3_PPS_PPS5_Pos                                    5                                                         /*!< PORT3 PPS: PPS5 Position            */\r
-#define PORT3_PPS_PPS5_Msk                                    (0x01UL << PORT3_PPS_PPS5_Pos)                            /*!< PORT3 PPS: PPS5 Mask                */\r
-#define PORT3_PPS_PPS6_Pos                                    6                                                         /*!< PORT3 PPS: PPS6 Position            */\r
-#define PORT3_PPS_PPS6_Msk                                    (0x01UL << PORT3_PPS_PPS6_Pos)                            /*!< PORT3 PPS: PPS6 Mask                */\r
-#define PORT3_PPS_PPS7_Pos                                    7                                                         /*!< PORT3 PPS: PPS7 Position            */\r
-#define PORT3_PPS_PPS7_Msk                                    (0x01UL << PORT3_PPS_PPS7_Pos)                            /*!< PORT3 PPS: PPS7 Mask                */\r
-#define PORT3_PPS_PPS8_Pos                                    8                                                         /*!< PORT3 PPS: PPS8 Position            */\r
-#define PORT3_PPS_PPS8_Msk                                    (0x01UL << PORT3_PPS_PPS8_Pos)                            /*!< PORT3 PPS: PPS8 Mask                */\r
-#define PORT3_PPS_PPS9_Pos                                    9                                                         /*!< PORT3 PPS: PPS9 Position            */\r
-#define PORT3_PPS_PPS9_Msk                                    (0x01UL << PORT3_PPS_PPS9_Pos)                            /*!< PORT3 PPS: PPS9 Mask                */\r
-#define PORT3_PPS_PPS10_Pos                                   10                                                        /*!< PORT3 PPS: PPS10 Position           */\r
-#define PORT3_PPS_PPS10_Msk                                   (0x01UL << PORT3_PPS_PPS10_Pos)                           /*!< PORT3 PPS: PPS10 Mask               */\r
-#define PORT3_PPS_PPS11_Pos                                   11                                                        /*!< PORT3 PPS: PPS11 Position           */\r
-#define PORT3_PPS_PPS11_Msk                                   (0x01UL << PORT3_PPS_PPS11_Pos)                           /*!< PORT3 PPS: PPS11 Mask               */\r
-#define PORT3_PPS_PPS12_Pos                                   12                                                        /*!< PORT3 PPS: PPS12 Position           */\r
-#define PORT3_PPS_PPS12_Msk                                   (0x01UL << PORT3_PPS_PPS12_Pos)                           /*!< PORT3 PPS: PPS12 Mask               */\r
-#define PORT3_PPS_PPS13_Pos                                   13                                                        /*!< PORT3 PPS: PPS13 Position           */\r
-#define PORT3_PPS_PPS13_Msk                                   (0x01UL << PORT3_PPS_PPS13_Pos)                           /*!< PORT3 PPS: PPS13 Mask               */\r
-#define PORT3_PPS_PPS14_Pos                                   14                                                        /*!< PORT3 PPS: PPS14 Position           */\r
-#define PORT3_PPS_PPS14_Msk                                   (0x01UL << PORT3_PPS_PPS14_Pos)                           /*!< PORT3 PPS: PPS14 Mask               */\r
-#define PORT3_PPS_PPS15_Pos                                   15                                                        /*!< PORT3 PPS: PPS15 Position           */\r
-#define PORT3_PPS_PPS15_Msk                                   (0x01UL << PORT3_PPS_PPS15_Pos)                           /*!< PORT3 PPS: PPS15 Mask               */\r
-\r
-// ---------------------------------------  PORT3_HWSEL  ------------------------------------------\r
-#define PORT3_HWSEL_HW0_Pos                                   0                                                         /*!< PORT3 HWSEL: HW0 Position           */\r
-#define PORT3_HWSEL_HW0_Msk                                   (0x03UL << PORT3_HWSEL_HW0_Pos)                           /*!< PORT3 HWSEL: HW0 Mask               */\r
-#define PORT3_HWSEL_HW1_Pos                                   2                                                         /*!< PORT3 HWSEL: HW1 Position           */\r
-#define PORT3_HWSEL_HW1_Msk                                   (0x03UL << PORT3_HWSEL_HW1_Pos)                           /*!< PORT3 HWSEL: HW1 Mask               */\r
-#define PORT3_HWSEL_HW2_Pos                                   4                                                         /*!< PORT3 HWSEL: HW2 Position           */\r
-#define PORT3_HWSEL_HW2_Msk                                   (0x03UL << PORT3_HWSEL_HW2_Pos)                           /*!< PORT3 HWSEL: HW2 Mask               */\r
-#define PORT3_HWSEL_HW3_Pos                                   6                                                         /*!< PORT3 HWSEL: HW3 Position           */\r
-#define PORT3_HWSEL_HW3_Msk                                   (0x03UL << PORT3_HWSEL_HW3_Pos)                           /*!< PORT3 HWSEL: HW3 Mask               */\r
-#define PORT3_HWSEL_HW4_Pos                                   8                                                         /*!< PORT3 HWSEL: HW4 Position           */\r
-#define PORT3_HWSEL_HW4_Msk                                   (0x03UL << PORT3_HWSEL_HW4_Pos)                           /*!< PORT3 HWSEL: HW4 Mask               */\r
-#define PORT3_HWSEL_HW5_Pos                                   10                                                        /*!< PORT3 HWSEL: HW5 Position           */\r
-#define PORT3_HWSEL_HW5_Msk                                   (0x03UL << PORT3_HWSEL_HW5_Pos)                           /*!< PORT3 HWSEL: HW5 Mask               */\r
-#define PORT3_HWSEL_HW6_Pos                                   12                                                        /*!< PORT3 HWSEL: HW6 Position           */\r
-#define PORT3_HWSEL_HW6_Msk                                   (0x03UL << PORT3_HWSEL_HW6_Pos)                           /*!< PORT3 HWSEL: HW6 Mask               */\r
-#define PORT3_HWSEL_HW7_Pos                                   14                                                        /*!< PORT3 HWSEL: HW7 Position           */\r
-#define PORT3_HWSEL_HW7_Msk                                   (0x03UL << PORT3_HWSEL_HW7_Pos)                           /*!< PORT3 HWSEL: HW7 Mask               */\r
-#define PORT3_HWSEL_HW8_Pos                                   16                                                        /*!< PORT3 HWSEL: HW8 Position           */\r
-#define PORT3_HWSEL_HW8_Msk                                   (0x03UL << PORT3_HWSEL_HW8_Pos)                           /*!< PORT3 HWSEL: HW8 Mask               */\r
-#define PORT3_HWSEL_HW9_Pos                                   18                                                        /*!< PORT3 HWSEL: HW9 Position           */\r
-#define PORT3_HWSEL_HW9_Msk                                   (0x03UL << PORT3_HWSEL_HW9_Pos)                           /*!< PORT3 HWSEL: HW9 Mask               */\r
-#define PORT3_HWSEL_HW10_Pos                                  20                                                        /*!< PORT3 HWSEL: HW10 Position          */\r
-#define PORT3_HWSEL_HW10_Msk                                  (0x03UL << PORT3_HWSEL_HW10_Pos)                          /*!< PORT3 HWSEL: HW10 Mask              */\r
-#define PORT3_HWSEL_HW11_Pos                                  22                                                        /*!< PORT3 HWSEL: HW11 Position          */\r
-#define PORT3_HWSEL_HW11_Msk                                  (0x03UL << PORT3_HWSEL_HW11_Pos)                          /*!< PORT3 HWSEL: HW11 Mask              */\r
-#define PORT3_HWSEL_HW12_Pos                                  24                                                        /*!< PORT3 HWSEL: HW12 Position          */\r
-#define PORT3_HWSEL_HW12_Msk                                  (0x03UL << PORT3_HWSEL_HW12_Pos)                          /*!< PORT3 HWSEL: HW12 Mask              */\r
-#define PORT3_HWSEL_HW13_Pos                                  26                                                        /*!< PORT3 HWSEL: HW13 Position          */\r
-#define PORT3_HWSEL_HW13_Msk                                  (0x03UL << PORT3_HWSEL_HW13_Pos)                          /*!< PORT3 HWSEL: HW13 Mask              */\r
-#define PORT3_HWSEL_HW14_Pos                                  28                                                        /*!< PORT3 HWSEL: HW14 Position          */\r
-#define PORT3_HWSEL_HW14_Msk                                  (0x03UL << PORT3_HWSEL_HW14_Pos)                          /*!< PORT3 HWSEL: HW14 Mask              */\r
-#define PORT3_HWSEL_HW15_Pos                                  30                                                        /*!< PORT3 HWSEL: HW15 Position          */\r
-#define PORT3_HWSEL_HW15_Msk                                  (0x03UL << PORT3_HWSEL_HW15_Pos)                          /*!< PORT3 HWSEL: HW15 Mask              */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                 PORT4 Position & Mask                                -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------  PORT4_OUT  -------------------------------------------\r
-#define PORT4_OUT_P0_Pos                                      0                                                         /*!< PORT4 OUT: P0 Position              */\r
-#define PORT4_OUT_P0_Msk                                      (0x01UL << PORT4_OUT_P0_Pos)                              /*!< PORT4 OUT: P0 Mask                  */\r
-#define PORT4_OUT_P1_Pos                                      1                                                         /*!< PORT4 OUT: P1 Position              */\r
-#define PORT4_OUT_P1_Msk                                      (0x01UL << PORT4_OUT_P1_Pos)                              /*!< PORT4 OUT: P1 Mask                  */\r
-#define PORT4_OUT_P2_Pos                                      2                                                         /*!< PORT4 OUT: P2 Position              */\r
-#define PORT4_OUT_P2_Msk                                      (0x01UL << PORT4_OUT_P2_Pos)                              /*!< PORT4 OUT: P2 Mask                  */\r
-#define PORT4_OUT_P3_Pos                                      3                                                         /*!< PORT4 OUT: P3 Position              */\r
-#define PORT4_OUT_P3_Msk                                      (0x01UL << PORT4_OUT_P3_Pos)                              /*!< PORT4 OUT: P3 Mask                  */\r
-#define PORT4_OUT_P4_Pos                                      4                                                         /*!< PORT4 OUT: P4 Position              */\r
-#define PORT4_OUT_P4_Msk                                      (0x01UL << PORT4_OUT_P4_Pos)                              /*!< PORT4 OUT: P4 Mask                  */\r
-#define PORT4_OUT_P5_Pos                                      5                                                         /*!< PORT4 OUT: P5 Position              */\r
-#define PORT4_OUT_P5_Msk                                      (0x01UL << PORT4_OUT_P5_Pos)                              /*!< PORT4 OUT: P5 Mask                  */\r
-#define PORT4_OUT_P6_Pos                                      6                                                         /*!< PORT4 OUT: P6 Position              */\r
-#define PORT4_OUT_P6_Msk                                      (0x01UL << PORT4_OUT_P6_Pos)                              /*!< PORT4 OUT: P6 Mask                  */\r
-#define PORT4_OUT_P7_Pos                                      7                                                         /*!< PORT4 OUT: P7 Position              */\r
-#define PORT4_OUT_P7_Msk                                      (0x01UL << PORT4_OUT_P7_Pos)                              /*!< PORT4 OUT: P7 Mask                  */\r
-#define PORT4_OUT_P8_Pos                                      8                                                         /*!< PORT4 OUT: P8 Position              */\r
-#define PORT4_OUT_P8_Msk                                      (0x01UL << PORT4_OUT_P8_Pos)                              /*!< PORT4 OUT: P8 Mask                  */\r
-#define PORT4_OUT_P9_Pos                                      9                                                         /*!< PORT4 OUT: P9 Position              */\r
-#define PORT4_OUT_P9_Msk                                      (0x01UL << PORT4_OUT_P9_Pos)                              /*!< PORT4 OUT: P9 Mask                  */\r
-#define PORT4_OUT_P10_Pos                                     10                                                        /*!< PORT4 OUT: P10 Position             */\r
-#define PORT4_OUT_P10_Msk                                     (0x01UL << PORT4_OUT_P10_Pos)                             /*!< PORT4 OUT: P10 Mask                 */\r
-#define PORT4_OUT_P11_Pos                                     11                                                        /*!< PORT4 OUT: P11 Position             */\r
-#define PORT4_OUT_P11_Msk                                     (0x01UL << PORT4_OUT_P11_Pos)                             /*!< PORT4 OUT: P11 Mask                 */\r
-#define PORT4_OUT_P12_Pos                                     12                                                        /*!< PORT4 OUT: P12 Position             */\r
-#define PORT4_OUT_P12_Msk                                     (0x01UL << PORT4_OUT_P12_Pos)                             /*!< PORT4 OUT: P12 Mask                 */\r
-#define PORT4_OUT_P13_Pos                                     13                                                        /*!< PORT4 OUT: P13 Position             */\r
-#define PORT4_OUT_P13_Msk                                     (0x01UL << PORT4_OUT_P13_Pos)                             /*!< PORT4 OUT: P13 Mask                 */\r
-#define PORT4_OUT_P14_Pos                                     14                                                        /*!< PORT4 OUT: P14 Position             */\r
-#define PORT4_OUT_P14_Msk                                     (0x01UL << PORT4_OUT_P14_Pos)                             /*!< PORT4 OUT: P14 Mask                 */\r
-#define PORT4_OUT_P15_Pos                                     15                                                        /*!< PORT4 OUT: P15 Position             */\r
-#define PORT4_OUT_P15_Msk                                     (0x01UL << PORT4_OUT_P15_Pos)                             /*!< PORT4 OUT: P15 Mask                 */\r
-\r
-// ----------------------------------------  PORT4_OMR  -------------------------------------------\r
-#define PORT4_OMR_PS0_Pos                                     0                                                         /*!< PORT4 OMR: PS0 Position             */\r
-#define PORT4_OMR_PS0_Msk                                     (0x01UL << PORT4_OMR_PS0_Pos)                             /*!< PORT4 OMR: PS0 Mask                 */\r
-#define PORT4_OMR_PS1_Pos                                     1                                                         /*!< PORT4 OMR: PS1 Position             */\r
-#define PORT4_OMR_PS1_Msk                                     (0x01UL << PORT4_OMR_PS1_Pos)                             /*!< PORT4 OMR: PS1 Mask                 */\r
-#define PORT4_OMR_PS2_Pos                                     2                                                         /*!< PORT4 OMR: PS2 Position             */\r
-#define PORT4_OMR_PS2_Msk                                     (0x01UL << PORT4_OMR_PS2_Pos)                             /*!< PORT4 OMR: PS2 Mask                 */\r
-#define PORT4_OMR_PS3_Pos                                     3                                                         /*!< PORT4 OMR: PS3 Position             */\r
-#define PORT4_OMR_PS3_Msk                                     (0x01UL << PORT4_OMR_PS3_Pos)                             /*!< PORT4 OMR: PS3 Mask                 */\r
-#define PORT4_OMR_PS4_Pos                                     4                                                         /*!< PORT4 OMR: PS4 Position             */\r
-#define PORT4_OMR_PS4_Msk                                     (0x01UL << PORT4_OMR_PS4_Pos)                             /*!< PORT4 OMR: PS4 Mask                 */\r
-#define PORT4_OMR_PS5_Pos                                     5                                                         /*!< PORT4 OMR: PS5 Position             */\r
-#define PORT4_OMR_PS5_Msk                                     (0x01UL << PORT4_OMR_PS5_Pos)                             /*!< PORT4 OMR: PS5 Mask                 */\r
-#define PORT4_OMR_PS6_Pos                                     6                                                         /*!< PORT4 OMR: PS6 Position             */\r
-#define PORT4_OMR_PS6_Msk                                     (0x01UL << PORT4_OMR_PS6_Pos)                             /*!< PORT4 OMR: PS6 Mask                 */\r
-#define PORT4_OMR_PS7_Pos                                     7                                                         /*!< PORT4 OMR: PS7 Position             */\r
-#define PORT4_OMR_PS7_Msk                                     (0x01UL << PORT4_OMR_PS7_Pos)                             /*!< PORT4 OMR: PS7 Mask                 */\r
-#define PORT4_OMR_PS8_Pos                                     8                                                         /*!< PORT4 OMR: PS8 Position             */\r
-#define PORT4_OMR_PS8_Msk                                     (0x01UL << PORT4_OMR_PS8_Pos)                             /*!< PORT4 OMR: PS8 Mask                 */\r
-#define PORT4_OMR_PS9_Pos                                     9                                                         /*!< PORT4 OMR: PS9 Position             */\r
-#define PORT4_OMR_PS9_Msk                                     (0x01UL << PORT4_OMR_PS9_Pos)                             /*!< PORT4 OMR: PS9 Mask                 */\r
-#define PORT4_OMR_PS10_Pos                                    10                                                        /*!< PORT4 OMR: PS10 Position            */\r
-#define PORT4_OMR_PS10_Msk                                    (0x01UL << PORT4_OMR_PS10_Pos)                            /*!< PORT4 OMR: PS10 Mask                */\r
-#define PORT4_OMR_PS11_Pos                                    11                                                        /*!< PORT4 OMR: PS11 Position            */\r
-#define PORT4_OMR_PS11_Msk                                    (0x01UL << PORT4_OMR_PS11_Pos)                            /*!< PORT4 OMR: PS11 Mask                */\r
-#define PORT4_OMR_PS12_Pos                                    12                                                        /*!< PORT4 OMR: PS12 Position            */\r
-#define PORT4_OMR_PS12_Msk                                    (0x01UL << PORT4_OMR_PS12_Pos)                            /*!< PORT4 OMR: PS12 Mask                */\r
-#define PORT4_OMR_PS13_Pos                                    13                                                        /*!< PORT4 OMR: PS13 Position            */\r
-#define PORT4_OMR_PS13_Msk                                    (0x01UL << PORT4_OMR_PS13_Pos)                            /*!< PORT4 OMR: PS13 Mask                */\r
-#define PORT4_OMR_PS14_Pos                                    14                                                        /*!< PORT4 OMR: PS14 Position            */\r
-#define PORT4_OMR_PS14_Msk                                    (0x01UL << PORT4_OMR_PS14_Pos)                            /*!< PORT4 OMR: PS14 Mask                */\r
-#define PORT4_OMR_PS15_Pos                                    15                                                        /*!< PORT4 OMR: PS15 Position            */\r
-#define PORT4_OMR_PS15_Msk                                    (0x01UL << PORT4_OMR_PS15_Pos)                            /*!< PORT4 OMR: PS15 Mask                */\r
-#define PORT4_OMR_PR0_Pos                                     16                                                        /*!< PORT4 OMR: PR0 Position             */\r
-#define PORT4_OMR_PR0_Msk                                     (0x01UL << PORT4_OMR_PR0_Pos)                             /*!< PORT4 OMR: PR0 Mask                 */\r
-#define PORT4_OMR_PR1_Pos                                     17                                                        /*!< PORT4 OMR: PR1 Position             */\r
-#define PORT4_OMR_PR1_Msk                                     (0x01UL << PORT4_OMR_PR1_Pos)                             /*!< PORT4 OMR: PR1 Mask                 */\r
-#define PORT4_OMR_PR2_Pos                                     18                                                        /*!< PORT4 OMR: PR2 Position             */\r
-#define PORT4_OMR_PR2_Msk                                     (0x01UL << PORT4_OMR_PR2_Pos)                             /*!< PORT4 OMR: PR2 Mask                 */\r
-#define PORT4_OMR_PR3_Pos                                     19                                                        /*!< PORT4 OMR: PR3 Position             */\r
-#define PORT4_OMR_PR3_Msk                                     (0x01UL << PORT4_OMR_PR3_Pos)                             /*!< PORT4 OMR: PR3 Mask                 */\r
-#define PORT4_OMR_PR4_Pos                                     20                                                        /*!< PORT4 OMR: PR4 Position             */\r
-#define PORT4_OMR_PR4_Msk                                     (0x01UL << PORT4_OMR_PR4_Pos)                             /*!< PORT4 OMR: PR4 Mask                 */\r
-#define PORT4_OMR_PR5_Pos                                     21                                                        /*!< PORT4 OMR: PR5 Position             */\r
-#define PORT4_OMR_PR5_Msk                                     (0x01UL << PORT4_OMR_PR5_Pos)                             /*!< PORT4 OMR: PR5 Mask                 */\r
-#define PORT4_OMR_PR6_Pos                                     22                                                        /*!< PORT4 OMR: PR6 Position             */\r
-#define PORT4_OMR_PR6_Msk                                     (0x01UL << PORT4_OMR_PR6_Pos)                             /*!< PORT4 OMR: PR6 Mask                 */\r
-#define PORT4_OMR_PR7_Pos                                     23                                                        /*!< PORT4 OMR: PR7 Position             */\r
-#define PORT4_OMR_PR7_Msk                                     (0x01UL << PORT4_OMR_PR7_Pos)                             /*!< PORT4 OMR: PR7 Mask                 */\r
-#define PORT4_OMR_PR8_Pos                                     24                                                        /*!< PORT4 OMR: PR8 Position             */\r
-#define PORT4_OMR_PR8_Msk                                     (0x01UL << PORT4_OMR_PR8_Pos)                             /*!< PORT4 OMR: PR8 Mask                 */\r
-#define PORT4_OMR_PR9_Pos                                     25                                                        /*!< PORT4 OMR: PR9 Position             */\r
-#define PORT4_OMR_PR9_Msk                                     (0x01UL << PORT4_OMR_PR9_Pos)                             /*!< PORT4 OMR: PR9 Mask                 */\r
-#define PORT4_OMR_PR10_Pos                                    26                                                        /*!< PORT4 OMR: PR10 Position            */\r
-#define PORT4_OMR_PR10_Msk                                    (0x01UL << PORT4_OMR_PR10_Pos)                            /*!< PORT4 OMR: PR10 Mask                */\r
-#define PORT4_OMR_PR11_Pos                                    27                                                        /*!< PORT4 OMR: PR11 Position            */\r
-#define PORT4_OMR_PR11_Msk                                    (0x01UL << PORT4_OMR_PR11_Pos)                            /*!< PORT4 OMR: PR11 Mask                */\r
-#define PORT4_OMR_PR12_Pos                                    28                                                        /*!< PORT4 OMR: PR12 Position            */\r
-#define PORT4_OMR_PR12_Msk                                    (0x01UL << PORT4_OMR_PR12_Pos)                            /*!< PORT4 OMR: PR12 Mask                */\r
-#define PORT4_OMR_PR13_Pos                                    29                                                        /*!< PORT4 OMR: PR13 Position            */\r
-#define PORT4_OMR_PR13_Msk                                    (0x01UL << PORT4_OMR_PR13_Pos)                            /*!< PORT4 OMR: PR13 Mask                */\r
-#define PORT4_OMR_PR14_Pos                                    30                                                        /*!< PORT4 OMR: PR14 Position            */\r
-#define PORT4_OMR_PR14_Msk                                    (0x01UL << PORT4_OMR_PR14_Pos)                            /*!< PORT4 OMR: PR14 Mask                */\r
-#define PORT4_OMR_PR15_Pos                                    31                                                        /*!< PORT4 OMR: PR15 Position            */\r
-#define PORT4_OMR_PR15_Msk                                    (0x01UL << PORT4_OMR_PR15_Pos)                            /*!< PORT4 OMR: PR15 Mask                */\r
-\r
-// ---------------------------------------  PORT4_IOCR0  ------------------------------------------\r
-#define PORT4_IOCR0_PC0_Pos                                   3                                                         /*!< PORT4 IOCR0: PC0 Position           */\r
-#define PORT4_IOCR0_PC0_Msk                                   (0x1fUL << PORT4_IOCR0_PC0_Pos)                           /*!< PORT4 IOCR0: PC0 Mask               */\r
-#define PORT4_IOCR0_PC1_Pos                                   11                                                        /*!< PORT4 IOCR0: PC1 Position           */\r
-#define PORT4_IOCR0_PC1_Msk                                   (0x1fUL << PORT4_IOCR0_PC1_Pos)                           /*!< PORT4 IOCR0: PC1 Mask               */\r
-#define PORT4_IOCR0_PC2_Pos                                   19                                                        /*!< PORT4 IOCR0: PC2 Position           */\r
-#define PORT4_IOCR0_PC2_Msk                                   (0x1fUL << PORT4_IOCR0_PC2_Pos)                           /*!< PORT4 IOCR0: PC2 Mask               */\r
-#define PORT4_IOCR0_PC3_Pos                                   27                                                        /*!< PORT4 IOCR0: PC3 Position           */\r
-#define PORT4_IOCR0_PC3_Msk                                   (0x1fUL << PORT4_IOCR0_PC3_Pos)                           /*!< PORT4 IOCR0: PC3 Mask               */\r
-\r
-// ---------------------------------------  PORT4_IOCR4  ------------------------------------------\r
-#define PORT4_IOCR4_PC4_Pos                                   3                                                         /*!< PORT4 IOCR4: PC4 Position           */\r
-#define PORT4_IOCR4_PC4_Msk                                   (0x1fUL << PORT4_IOCR4_PC4_Pos)                           /*!< PORT4 IOCR4: PC4 Mask               */\r
-#define PORT4_IOCR4_PC5_Pos                                   11                                                        /*!< PORT4 IOCR4: PC5 Position           */\r
-#define PORT4_IOCR4_PC5_Msk                                   (0x1fUL << PORT4_IOCR4_PC5_Pos)                           /*!< PORT4 IOCR4: PC5 Mask               */\r
-#define PORT4_IOCR4_PC6_Pos                                   19                                                        /*!< PORT4 IOCR4: PC6 Position           */\r
-#define PORT4_IOCR4_PC6_Msk                                   (0x1fUL << PORT4_IOCR4_PC6_Pos)                           /*!< PORT4 IOCR4: PC6 Mask               */\r
-#define PORT4_IOCR4_PC7_Pos                                   27                                                        /*!< PORT4 IOCR4: PC7 Position           */\r
-#define PORT4_IOCR4_PC7_Msk                                   (0x1fUL << PORT4_IOCR4_PC7_Pos)                           /*!< PORT4 IOCR4: PC7 Mask               */\r
-\r
-// ----------------------------------------  PORT4_IN  --------------------------------------------\r
-#define PORT4_IN_P0_Pos                                       0                                                         /*!< PORT4 IN: P0 Position               */\r
-#define PORT4_IN_P0_Msk                                       (0x01UL << PORT4_IN_P0_Pos)                               /*!< PORT4 IN: P0 Mask                   */\r
-#define PORT4_IN_P1_Pos                                       1                                                         /*!< PORT4 IN: P1 Position               */\r
-#define PORT4_IN_P1_Msk                                       (0x01UL << PORT4_IN_P1_Pos)                               /*!< PORT4 IN: P1 Mask                   */\r
-#define PORT4_IN_P2_Pos                                       2                                                         /*!< PORT4 IN: P2 Position               */\r
-#define PORT4_IN_P2_Msk                                       (0x01UL << PORT4_IN_P2_Pos)                               /*!< PORT4 IN: P2 Mask                   */\r
-#define PORT4_IN_P3_Pos                                       3                                                         /*!< PORT4 IN: P3 Position               */\r
-#define PORT4_IN_P3_Msk                                       (0x01UL << PORT4_IN_P3_Pos)                               /*!< PORT4 IN: P3 Mask                   */\r
-#define PORT4_IN_P4_Pos                                       4                                                         /*!< PORT4 IN: P4 Position               */\r
-#define PORT4_IN_P4_Msk                                       (0x01UL << PORT4_IN_P4_Pos)                               /*!< PORT4 IN: P4 Mask                   */\r
-#define PORT4_IN_P5_Pos                                       5                                                         /*!< PORT4 IN: P5 Position               */\r
-#define PORT4_IN_P5_Msk                                       (0x01UL << PORT4_IN_P5_Pos)                               /*!< PORT4 IN: P5 Mask                   */\r
-#define PORT4_IN_P6_Pos                                       6                                                         /*!< PORT4 IN: P6 Position               */\r
-#define PORT4_IN_P6_Msk                                       (0x01UL << PORT4_IN_P6_Pos)                               /*!< PORT4 IN: P6 Mask                   */\r
-#define PORT4_IN_P7_Pos                                       7                                                         /*!< PORT4 IN: P7 Position               */\r
-#define PORT4_IN_P7_Msk                                       (0x01UL << PORT4_IN_P7_Pos)                               /*!< PORT4 IN: P7 Mask                   */\r
-#define PORT4_IN_P8_Pos                                       8                                                         /*!< PORT4 IN: P8 Position               */\r
-#define PORT4_IN_P8_Msk                                       (0x01UL << PORT4_IN_P8_Pos)                               /*!< PORT4 IN: P8 Mask                   */\r
-#define PORT4_IN_P9_Pos                                       9                                                         /*!< PORT4 IN: P9 Position               */\r
-#define PORT4_IN_P9_Msk                                       (0x01UL << PORT4_IN_P9_Pos)                               /*!< PORT4 IN: P9 Mask                   */\r
-#define PORT4_IN_P10_Pos                                      10                                                        /*!< PORT4 IN: P10 Position              */\r
-#define PORT4_IN_P10_Msk                                      (0x01UL << PORT4_IN_P10_Pos)                              /*!< PORT4 IN: P10 Mask                  */\r
-#define PORT4_IN_P11_Pos                                      11                                                        /*!< PORT4 IN: P11 Position              */\r
-#define PORT4_IN_P11_Msk                                      (0x01UL << PORT4_IN_P11_Pos)                              /*!< PORT4 IN: P11 Mask                  */\r
-#define PORT4_IN_P12_Pos                                      12                                                        /*!< PORT4 IN: P12 Position              */\r
-#define PORT4_IN_P12_Msk                                      (0x01UL << PORT4_IN_P12_Pos)                              /*!< PORT4 IN: P12 Mask                  */\r
-#define PORT4_IN_P13_Pos                                      13                                                        /*!< PORT4 IN: P13 Position              */\r
-#define PORT4_IN_P13_Msk                                      (0x01UL << PORT4_IN_P13_Pos)                              /*!< PORT4 IN: P13 Mask                  */\r
-#define PORT4_IN_P14_Pos                                      14                                                        /*!< PORT4 IN: P14 Position              */\r
-#define PORT4_IN_P14_Msk                                      (0x01UL << PORT4_IN_P14_Pos)                              /*!< PORT4 IN: P14 Mask                  */\r
-#define PORT4_IN_P15_Pos                                      15                                                        /*!< PORT4 IN: P15 Position              */\r
-#define PORT4_IN_P15_Msk                                      (0x01UL << PORT4_IN_P15_Pos)                              /*!< PORT4 IN: P15 Mask                  */\r
-\r
-// ---------------------------------------  PORT4_PDR0  -------------------------------------------\r
-#define PORT4_PDR0_PD0_Pos                                    0                                                         /*!< PORT4 PDR0: PD0 Position            */\r
-#define PORT4_PDR0_PD0_Msk                                    (0x07UL << PORT4_PDR0_PD0_Pos)                            /*!< PORT4 PDR0: PD0 Mask                */\r
-#define PORT4_PDR0_PD1_Pos                                    4                                                         /*!< PORT4 PDR0: PD1 Position            */\r
-#define PORT4_PDR0_PD1_Msk                                    (0x07UL << PORT4_PDR0_PD1_Pos)                            /*!< PORT4 PDR0: PD1 Mask                */\r
-#define PORT4_PDR0_PD2_Pos                                    8                                                         /*!< PORT4 PDR0: PD2 Position            */\r
-#define PORT4_PDR0_PD2_Msk                                    (0x07UL << PORT4_PDR0_PD2_Pos)                            /*!< PORT4 PDR0: PD2 Mask                */\r
-#define PORT4_PDR0_PD3_Pos                                    12                                                        /*!< PORT4 PDR0: PD3 Position            */\r
-#define PORT4_PDR0_PD3_Msk                                    (0x07UL << PORT4_PDR0_PD3_Pos)                            /*!< PORT4 PDR0: PD3 Mask                */\r
-#define PORT4_PDR0_PD4_Pos                                    16                                                        /*!< PORT4 PDR0: PD4 Position            */\r
-#define PORT4_PDR0_PD4_Msk                                    (0x07UL << PORT4_PDR0_PD4_Pos)                            /*!< PORT4 PDR0: PD4 Mask                */\r
-#define PORT4_PDR0_PD5_Pos                                    20                                                        /*!< PORT4 PDR0: PD5 Position            */\r
-#define PORT4_PDR0_PD5_Msk                                    (0x07UL << PORT4_PDR0_PD5_Pos)                            /*!< PORT4 PDR0: PD5 Mask                */\r
-#define PORT4_PDR0_PD6_Pos                                    24                                                        /*!< PORT4 PDR0: PD6 Position            */\r
-#define PORT4_PDR0_PD6_Msk                                    (0x07UL << PORT4_PDR0_PD6_Pos)                            /*!< PORT4 PDR0: PD6 Mask                */\r
-#define PORT4_PDR0_PD7_Pos                                    28                                                        /*!< PORT4 PDR0: PD7 Position            */\r
-#define PORT4_PDR0_PD7_Msk                                    (0x07UL << PORT4_PDR0_PD7_Pos)                            /*!< PORT4 PDR0: PD7 Mask                */\r
-\r
-// ---------------------------------------  PORT4_PDISC  ------------------------------------------\r
-#define PORT4_PDISC_PDIS0_Pos                                 0                                                         /*!< PORT4 PDISC: PDIS0 Position         */\r
-#define PORT4_PDISC_PDIS0_Msk                                 (0x01UL << PORT4_PDISC_PDIS0_Pos)                         /*!< PORT4 PDISC: PDIS0 Mask             */\r
-#define PORT4_PDISC_PDIS1_Pos                                 1                                                         /*!< PORT4 PDISC: PDIS1 Position         */\r
-#define PORT4_PDISC_PDIS1_Msk                                 (0x01UL << PORT4_PDISC_PDIS1_Pos)                         /*!< PORT4 PDISC: PDIS1 Mask             */\r
-#define PORT4_PDISC_PDIS2_Pos                                 2                                                         /*!< PORT4 PDISC: PDIS2 Position         */\r
-#define PORT4_PDISC_PDIS2_Msk                                 (0x01UL << PORT4_PDISC_PDIS2_Pos)                         /*!< PORT4 PDISC: PDIS2 Mask             */\r
-#define PORT4_PDISC_PDIS3_Pos                                 3                                                         /*!< PORT4 PDISC: PDIS3 Position         */\r
-#define PORT4_PDISC_PDIS3_Msk                                 (0x01UL << PORT4_PDISC_PDIS3_Pos)                         /*!< PORT4 PDISC: PDIS3 Mask             */\r
-#define PORT4_PDISC_PDIS4_Pos                                 4                                                         /*!< PORT4 PDISC: PDIS4 Position         */\r
-#define PORT4_PDISC_PDIS4_Msk                                 (0x01UL << PORT4_PDISC_PDIS4_Pos)                         /*!< PORT4 PDISC: PDIS4 Mask             */\r
-#define PORT4_PDISC_PDIS5_Pos                                 5                                                         /*!< PORT4 PDISC: PDIS5 Position         */\r
-#define PORT4_PDISC_PDIS5_Msk                                 (0x01UL << PORT4_PDISC_PDIS5_Pos)                         /*!< PORT4 PDISC: PDIS5 Mask             */\r
-#define PORT4_PDISC_PDIS6_Pos                                 6                                                         /*!< PORT4 PDISC: PDIS6 Position         */\r
-#define PORT4_PDISC_PDIS6_Msk                                 (0x01UL << PORT4_PDISC_PDIS6_Pos)                         /*!< PORT4 PDISC: PDIS6 Mask             */\r
-#define PORT4_PDISC_PDIS7_Pos                                 7                                                         /*!< PORT4 PDISC: PDIS7 Position         */\r
-#define PORT4_PDISC_PDIS7_Msk                                 (0x01UL << PORT4_PDISC_PDIS7_Pos)                         /*!< PORT4 PDISC: PDIS7 Mask             */\r
-#define PORT4_PDISC_PDIS8_Pos                                 8                                                         /*!< PORT4 PDISC: PDIS8 Position         */\r
-#define PORT4_PDISC_PDIS8_Msk                                 (0x01UL << PORT4_PDISC_PDIS8_Pos)                         /*!< PORT4 PDISC: PDIS8 Mask             */\r
-#define PORT4_PDISC_PDIS9_Pos                                 9                                                         /*!< PORT4 PDISC: PDIS9 Position         */\r
-#define PORT4_PDISC_PDIS9_Msk                                 (0x01UL << PORT4_PDISC_PDIS9_Pos)                         /*!< PORT4 PDISC: PDIS9 Mask             */\r
-#define PORT4_PDISC_PDIS10_Pos                                10                                                        /*!< PORT4 PDISC: PDIS10 Position        */\r
-#define PORT4_PDISC_PDIS10_Msk                                (0x01UL << PORT4_PDISC_PDIS10_Pos)                        /*!< PORT4 PDISC: PDIS10 Mask            */\r
-#define PORT4_PDISC_PDIS11_Pos                                11                                                        /*!< PORT4 PDISC: PDIS11 Position        */\r
-#define PORT4_PDISC_PDIS11_Msk                                (0x01UL << PORT4_PDISC_PDIS11_Pos)                        /*!< PORT4 PDISC: PDIS11 Mask            */\r
-#define PORT4_PDISC_PDIS12_Pos                                12                                                        /*!< PORT4 PDISC: PDIS12 Position        */\r
-#define PORT4_PDISC_PDIS12_Msk                                (0x01UL << PORT4_PDISC_PDIS12_Pos)                        /*!< PORT4 PDISC: PDIS12 Mask            */\r
-#define PORT4_PDISC_PDIS13_Pos                                13                                                        /*!< PORT4 PDISC: PDIS13 Position        */\r
-#define PORT4_PDISC_PDIS13_Msk                                (0x01UL << PORT4_PDISC_PDIS13_Pos)                        /*!< PORT4 PDISC: PDIS13 Mask            */\r
-#define PORT4_PDISC_PDIS14_Pos                                14                                                        /*!< PORT4 PDISC: PDIS14 Position        */\r
-#define PORT4_PDISC_PDIS14_Msk                                (0x01UL << PORT4_PDISC_PDIS14_Pos)                        /*!< PORT4 PDISC: PDIS14 Mask            */\r
-#define PORT4_PDISC_PDIS15_Pos                                15                                                        /*!< PORT4 PDISC: PDIS15 Position        */\r
-#define PORT4_PDISC_PDIS15_Msk                                (0x01UL << PORT4_PDISC_PDIS15_Pos)                        /*!< PORT4 PDISC: PDIS15 Mask            */\r
-\r
-// ----------------------------------------  PORT4_PPS  -------------------------------------------\r
-#define PORT4_PPS_PPS0_Pos                                    0                                                         /*!< PORT4 PPS: PPS0 Position            */\r
-#define PORT4_PPS_PPS0_Msk                                    (0x01UL << PORT4_PPS_PPS0_Pos)                            /*!< PORT4 PPS: PPS0 Mask                */\r
-#define PORT4_PPS_PPS1_Pos                                    1                                                         /*!< PORT4 PPS: PPS1 Position            */\r
-#define PORT4_PPS_PPS1_Msk                                    (0x01UL << PORT4_PPS_PPS1_Pos)                            /*!< PORT4 PPS: PPS1 Mask                */\r
-#define PORT4_PPS_PPS2_Pos                                    2                                                         /*!< PORT4 PPS: PPS2 Position            */\r
-#define PORT4_PPS_PPS2_Msk                                    (0x01UL << PORT4_PPS_PPS2_Pos)                            /*!< PORT4 PPS: PPS2 Mask                */\r
-#define PORT4_PPS_PPS3_Pos                                    3                                                         /*!< PORT4 PPS: PPS3 Position            */\r
-#define PORT4_PPS_PPS3_Msk                                    (0x01UL << PORT4_PPS_PPS3_Pos)                            /*!< PORT4 PPS: PPS3 Mask                */\r
-#define PORT4_PPS_PPS4_Pos                                    4                                                         /*!< PORT4 PPS: PPS4 Position            */\r
-#define PORT4_PPS_PPS4_Msk                                    (0x01UL << PORT4_PPS_PPS4_Pos)                            /*!< PORT4 PPS: PPS4 Mask                */\r
-#define PORT4_PPS_PPS5_Pos                                    5                                                         /*!< PORT4 PPS: PPS5 Position            */\r
-#define PORT4_PPS_PPS5_Msk                                    (0x01UL << PORT4_PPS_PPS5_Pos)                            /*!< PORT4 PPS: PPS5 Mask                */\r
-#define PORT4_PPS_PPS6_Pos                                    6                                                         /*!< PORT4 PPS: PPS6 Position            */\r
-#define PORT4_PPS_PPS6_Msk                                    (0x01UL << PORT4_PPS_PPS6_Pos)                            /*!< PORT4 PPS: PPS6 Mask                */\r
-#define PORT4_PPS_PPS7_Pos                                    7                                                         /*!< PORT4 PPS: PPS7 Position            */\r
-#define PORT4_PPS_PPS7_Msk                                    (0x01UL << PORT4_PPS_PPS7_Pos)                            /*!< PORT4 PPS: PPS7 Mask                */\r
-#define PORT4_PPS_PPS8_Pos                                    8                                                         /*!< PORT4 PPS: PPS8 Position            */\r
-#define PORT4_PPS_PPS8_Msk                                    (0x01UL << PORT4_PPS_PPS8_Pos)                            /*!< PORT4 PPS: PPS8 Mask                */\r
-#define PORT4_PPS_PPS9_Pos                                    9                                                         /*!< PORT4 PPS: PPS9 Position            */\r
-#define PORT4_PPS_PPS9_Msk                                    (0x01UL << PORT4_PPS_PPS9_Pos)                            /*!< PORT4 PPS: PPS9 Mask                */\r
-#define PORT4_PPS_PPS10_Pos                                   10                                                        /*!< PORT4 PPS: PPS10 Position           */\r
-#define PORT4_PPS_PPS10_Msk                                   (0x01UL << PORT4_PPS_PPS10_Pos)                           /*!< PORT4 PPS: PPS10 Mask               */\r
-#define PORT4_PPS_PPS11_Pos                                   11                                                        /*!< PORT4 PPS: PPS11 Position           */\r
-#define PORT4_PPS_PPS11_Msk                                   (0x01UL << PORT4_PPS_PPS11_Pos)                           /*!< PORT4 PPS: PPS11 Mask               */\r
-#define PORT4_PPS_PPS12_Pos                                   12                                                        /*!< PORT4 PPS: PPS12 Position           */\r
-#define PORT4_PPS_PPS12_Msk                                   (0x01UL << PORT4_PPS_PPS12_Pos)                           /*!< PORT4 PPS: PPS12 Mask               */\r
-#define PORT4_PPS_PPS13_Pos                                   13                                                        /*!< PORT4 PPS: PPS13 Position           */\r
-#define PORT4_PPS_PPS13_Msk                                   (0x01UL << PORT4_PPS_PPS13_Pos)                           /*!< PORT4 PPS: PPS13 Mask               */\r
-#define PORT4_PPS_PPS14_Pos                                   14                                                        /*!< PORT4 PPS: PPS14 Position           */\r
-#define PORT4_PPS_PPS14_Msk                                   (0x01UL << PORT4_PPS_PPS14_Pos)                           /*!< PORT4 PPS: PPS14 Mask               */\r
-#define PORT4_PPS_PPS15_Pos                                   15                                                        /*!< PORT4 PPS: PPS15 Position           */\r
-#define PORT4_PPS_PPS15_Msk                                   (0x01UL << PORT4_PPS_PPS15_Pos)                           /*!< PORT4 PPS: PPS15 Mask               */\r
-\r
-// ---------------------------------------  PORT4_HWSEL  ------------------------------------------\r
-#define PORT4_HWSEL_HW0_Pos                                   0                                                         /*!< PORT4 HWSEL: HW0 Position           */\r
-#define PORT4_HWSEL_HW0_Msk                                   (0x03UL << PORT4_HWSEL_HW0_Pos)                           /*!< PORT4 HWSEL: HW0 Mask               */\r
-#define PORT4_HWSEL_HW1_Pos                                   2                                                         /*!< PORT4 HWSEL: HW1 Position           */\r
-#define PORT4_HWSEL_HW1_Msk                                   (0x03UL << PORT4_HWSEL_HW1_Pos)                           /*!< PORT4 HWSEL: HW1 Mask               */\r
-#define PORT4_HWSEL_HW2_Pos                                   4                                                         /*!< PORT4 HWSEL: HW2 Position           */\r
-#define PORT4_HWSEL_HW2_Msk                                   (0x03UL << PORT4_HWSEL_HW2_Pos)                           /*!< PORT4 HWSEL: HW2 Mask               */\r
-#define PORT4_HWSEL_HW3_Pos                                   6                                                         /*!< PORT4 HWSEL: HW3 Position           */\r
-#define PORT4_HWSEL_HW3_Msk                                   (0x03UL << PORT4_HWSEL_HW3_Pos)                           /*!< PORT4 HWSEL: HW3 Mask               */\r
-#define PORT4_HWSEL_HW4_Pos                                   8                                                         /*!< PORT4 HWSEL: HW4 Position           */\r
-#define PORT4_HWSEL_HW4_Msk                                   (0x03UL << PORT4_HWSEL_HW4_Pos)                           /*!< PORT4 HWSEL: HW4 Mask               */\r
-#define PORT4_HWSEL_HW5_Pos                                   10                                                        /*!< PORT4 HWSEL: HW5 Position           */\r
-#define PORT4_HWSEL_HW5_Msk                                   (0x03UL << PORT4_HWSEL_HW5_Pos)                           /*!< PORT4 HWSEL: HW5 Mask               */\r
-#define PORT4_HWSEL_HW6_Pos                                   12                                                        /*!< PORT4 HWSEL: HW6 Position           */\r
-#define PORT4_HWSEL_HW6_Msk                                   (0x03UL << PORT4_HWSEL_HW6_Pos)                           /*!< PORT4 HWSEL: HW6 Mask               */\r
-#define PORT4_HWSEL_HW7_Pos                                   14                                                        /*!< PORT4 HWSEL: HW7 Position           */\r
-#define PORT4_HWSEL_HW7_Msk                                   (0x03UL << PORT4_HWSEL_HW7_Pos)                           /*!< PORT4 HWSEL: HW7 Mask               */\r
-#define PORT4_HWSEL_HW8_Pos                                   16                                                        /*!< PORT4 HWSEL: HW8 Position           */\r
-#define PORT4_HWSEL_HW8_Msk                                   (0x03UL << PORT4_HWSEL_HW8_Pos)                           /*!< PORT4 HWSEL: HW8 Mask               */\r
-#define PORT4_HWSEL_HW9_Pos                                   18                                                        /*!< PORT4 HWSEL: HW9 Position           */\r
-#define PORT4_HWSEL_HW9_Msk                                   (0x03UL << PORT4_HWSEL_HW9_Pos)                           /*!< PORT4 HWSEL: HW9 Mask               */\r
-#define PORT4_HWSEL_HW10_Pos                                  20                                                        /*!< PORT4 HWSEL: HW10 Position          */\r
-#define PORT4_HWSEL_HW10_Msk                                  (0x03UL << PORT4_HWSEL_HW10_Pos)                          /*!< PORT4 HWSEL: HW10 Mask              */\r
-#define PORT4_HWSEL_HW11_Pos                                  22                                                        /*!< PORT4 HWSEL: HW11 Position          */\r
-#define PORT4_HWSEL_HW11_Msk                                  (0x03UL << PORT4_HWSEL_HW11_Pos)                          /*!< PORT4 HWSEL: HW11 Mask              */\r
-#define PORT4_HWSEL_HW12_Pos                                  24                                                        /*!< PORT4 HWSEL: HW12 Position          */\r
-#define PORT4_HWSEL_HW12_Msk                                  (0x03UL << PORT4_HWSEL_HW12_Pos)                          /*!< PORT4 HWSEL: HW12 Mask              */\r
-#define PORT4_HWSEL_HW13_Pos                                  26                                                        /*!< PORT4 HWSEL: HW13 Position          */\r
-#define PORT4_HWSEL_HW13_Msk                                  (0x03UL << PORT4_HWSEL_HW13_Pos)                          /*!< PORT4 HWSEL: HW13 Mask              */\r
-#define PORT4_HWSEL_HW14_Pos                                  28                                                        /*!< PORT4 HWSEL: HW14 Position          */\r
-#define PORT4_HWSEL_HW14_Msk                                  (0x03UL << PORT4_HWSEL_HW14_Pos)                          /*!< PORT4 HWSEL: HW14 Mask              */\r
-#define PORT4_HWSEL_HW15_Pos                                  30                                                        /*!< PORT4 HWSEL: HW15 Position          */\r
-#define PORT4_HWSEL_HW15_Msk                                  (0x03UL << PORT4_HWSEL_HW15_Pos)                          /*!< PORT4 HWSEL: HW15 Mask              */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                 PORT5 Position & Mask                                -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------  PORT5_OUT  -------------------------------------------\r
-#define PORT5_OUT_P0_Pos                                      0                                                         /*!< PORT5 OUT: P0 Position              */\r
-#define PORT5_OUT_P0_Msk                                      (0x01UL << PORT5_OUT_P0_Pos)                              /*!< PORT5 OUT: P0 Mask                  */\r
-#define PORT5_OUT_P1_Pos                                      1                                                         /*!< PORT5 OUT: P1 Position              */\r
-#define PORT5_OUT_P1_Msk                                      (0x01UL << PORT5_OUT_P1_Pos)                              /*!< PORT5 OUT: P1 Mask                  */\r
-#define PORT5_OUT_P2_Pos                                      2                                                         /*!< PORT5 OUT: P2 Position              */\r
-#define PORT5_OUT_P2_Msk                                      (0x01UL << PORT5_OUT_P2_Pos)                              /*!< PORT5 OUT: P2 Mask                  */\r
-#define PORT5_OUT_P3_Pos                                      3                                                         /*!< PORT5 OUT: P3 Position              */\r
-#define PORT5_OUT_P3_Msk                                      (0x01UL << PORT5_OUT_P3_Pos)                              /*!< PORT5 OUT: P3 Mask                  */\r
-#define PORT5_OUT_P4_Pos                                      4                                                         /*!< PORT5 OUT: P4 Position              */\r
-#define PORT5_OUT_P4_Msk                                      (0x01UL << PORT5_OUT_P4_Pos)                              /*!< PORT5 OUT: P4 Mask                  */\r
-#define PORT5_OUT_P5_Pos                                      5                                                         /*!< PORT5 OUT: P5 Position              */\r
-#define PORT5_OUT_P5_Msk                                      (0x01UL << PORT5_OUT_P5_Pos)                              /*!< PORT5 OUT: P5 Mask                  */\r
-#define PORT5_OUT_P6_Pos                                      6                                                         /*!< PORT5 OUT: P6 Position              */\r
-#define PORT5_OUT_P6_Msk                                      (0x01UL << PORT5_OUT_P6_Pos)                              /*!< PORT5 OUT: P6 Mask                  */\r
-#define PORT5_OUT_P7_Pos                                      7                                                         /*!< PORT5 OUT: P7 Position              */\r
-#define PORT5_OUT_P7_Msk                                      (0x01UL << PORT5_OUT_P7_Pos)                              /*!< PORT5 OUT: P7 Mask                  */\r
-#define PORT5_OUT_P8_Pos                                      8                                                         /*!< PORT5 OUT: P8 Position              */\r
-#define PORT5_OUT_P8_Msk                                      (0x01UL << PORT5_OUT_P8_Pos)                              /*!< PORT5 OUT: P8 Mask                  */\r
-#define PORT5_OUT_P9_Pos                                      9                                                         /*!< PORT5 OUT: P9 Position              */\r
-#define PORT5_OUT_P9_Msk                                      (0x01UL << PORT5_OUT_P9_Pos)                              /*!< PORT5 OUT: P9 Mask                  */\r
-#define PORT5_OUT_P10_Pos                                     10                                                        /*!< PORT5 OUT: P10 Position             */\r
-#define PORT5_OUT_P10_Msk                                     (0x01UL << PORT5_OUT_P10_Pos)                             /*!< PORT5 OUT: P10 Mask                 */\r
-#define PORT5_OUT_P11_Pos                                     11                                                        /*!< PORT5 OUT: P11 Position             */\r
-#define PORT5_OUT_P11_Msk                                     (0x01UL << PORT5_OUT_P11_Pos)                             /*!< PORT5 OUT: P11 Mask                 */\r
-#define PORT5_OUT_P12_Pos                                     12                                                        /*!< PORT5 OUT: P12 Position             */\r
-#define PORT5_OUT_P12_Msk                                     (0x01UL << PORT5_OUT_P12_Pos)                             /*!< PORT5 OUT: P12 Mask                 */\r
-#define PORT5_OUT_P13_Pos                                     13                                                        /*!< PORT5 OUT: P13 Position             */\r
-#define PORT5_OUT_P13_Msk                                     (0x01UL << PORT5_OUT_P13_Pos)                             /*!< PORT5 OUT: P13 Mask                 */\r
-#define PORT5_OUT_P14_Pos                                     14                                                        /*!< PORT5 OUT: P14 Position             */\r
-#define PORT5_OUT_P14_Msk                                     (0x01UL << PORT5_OUT_P14_Pos)                             /*!< PORT5 OUT: P14 Mask                 */\r
-#define PORT5_OUT_P15_Pos                                     15                                                        /*!< PORT5 OUT: P15 Position             */\r
-#define PORT5_OUT_P15_Msk                                     (0x01UL << PORT5_OUT_P15_Pos)                             /*!< PORT5 OUT: P15 Mask                 */\r
-\r
-// ----------------------------------------  PORT5_OMR  -------------------------------------------\r
-#define PORT5_OMR_PS0_Pos                                     0                                                         /*!< PORT5 OMR: PS0 Position             */\r
-#define PORT5_OMR_PS0_Msk                                     (0x01UL << PORT5_OMR_PS0_Pos)                             /*!< PORT5 OMR: PS0 Mask                 */\r
-#define PORT5_OMR_PS1_Pos                                     1                                                         /*!< PORT5 OMR: PS1 Position             */\r
-#define PORT5_OMR_PS1_Msk                                     (0x01UL << PORT5_OMR_PS1_Pos)                             /*!< PORT5 OMR: PS1 Mask                 */\r
-#define PORT5_OMR_PS2_Pos                                     2                                                         /*!< PORT5 OMR: PS2 Position             */\r
-#define PORT5_OMR_PS2_Msk                                     (0x01UL << PORT5_OMR_PS2_Pos)                             /*!< PORT5 OMR: PS2 Mask                 */\r
-#define PORT5_OMR_PS3_Pos                                     3                                                         /*!< PORT5 OMR: PS3 Position             */\r
-#define PORT5_OMR_PS3_Msk                                     (0x01UL << PORT5_OMR_PS3_Pos)                             /*!< PORT5 OMR: PS3 Mask                 */\r
-#define PORT5_OMR_PS4_Pos                                     4                                                         /*!< PORT5 OMR: PS4 Position             */\r
-#define PORT5_OMR_PS4_Msk                                     (0x01UL << PORT5_OMR_PS4_Pos)                             /*!< PORT5 OMR: PS4 Mask                 */\r
-#define PORT5_OMR_PS5_Pos                                     5                                                         /*!< PORT5 OMR: PS5 Position             */\r
-#define PORT5_OMR_PS5_Msk                                     (0x01UL << PORT5_OMR_PS5_Pos)                             /*!< PORT5 OMR: PS5 Mask                 */\r
-#define PORT5_OMR_PS6_Pos                                     6                                                         /*!< PORT5 OMR: PS6 Position             */\r
-#define PORT5_OMR_PS6_Msk                                     (0x01UL << PORT5_OMR_PS6_Pos)                             /*!< PORT5 OMR: PS6 Mask                 */\r
-#define PORT5_OMR_PS7_Pos                                     7                                                         /*!< PORT5 OMR: PS7 Position             */\r
-#define PORT5_OMR_PS7_Msk                                     (0x01UL << PORT5_OMR_PS7_Pos)                             /*!< PORT5 OMR: PS7 Mask                 */\r
-#define PORT5_OMR_PS8_Pos                                     8                                                         /*!< PORT5 OMR: PS8 Position             */\r
-#define PORT5_OMR_PS8_Msk                                     (0x01UL << PORT5_OMR_PS8_Pos)                             /*!< PORT5 OMR: PS8 Mask                 */\r
-#define PORT5_OMR_PS9_Pos                                     9                                                         /*!< PORT5 OMR: PS9 Position             */\r
-#define PORT5_OMR_PS9_Msk                                     (0x01UL << PORT5_OMR_PS9_Pos)                             /*!< PORT5 OMR: PS9 Mask                 */\r
-#define PORT5_OMR_PS10_Pos                                    10                                                        /*!< PORT5 OMR: PS10 Position            */\r
-#define PORT5_OMR_PS10_Msk                                    (0x01UL << PORT5_OMR_PS10_Pos)                            /*!< PORT5 OMR: PS10 Mask                */\r
-#define PORT5_OMR_PS11_Pos                                    11                                                        /*!< PORT5 OMR: PS11 Position            */\r
-#define PORT5_OMR_PS11_Msk                                    (0x01UL << PORT5_OMR_PS11_Pos)                            /*!< PORT5 OMR: PS11 Mask                */\r
-#define PORT5_OMR_PS12_Pos                                    12                                                        /*!< PORT5 OMR: PS12 Position            */\r
-#define PORT5_OMR_PS12_Msk                                    (0x01UL << PORT5_OMR_PS12_Pos)                            /*!< PORT5 OMR: PS12 Mask                */\r
-#define PORT5_OMR_PS13_Pos                                    13                                                        /*!< PORT5 OMR: PS13 Position            */\r
-#define PORT5_OMR_PS13_Msk                                    (0x01UL << PORT5_OMR_PS13_Pos)                            /*!< PORT5 OMR: PS13 Mask                */\r
-#define PORT5_OMR_PS14_Pos                                    14                                                        /*!< PORT5 OMR: PS14 Position            */\r
-#define PORT5_OMR_PS14_Msk                                    (0x01UL << PORT5_OMR_PS14_Pos)                            /*!< PORT5 OMR: PS14 Mask                */\r
-#define PORT5_OMR_PS15_Pos                                    15                                                        /*!< PORT5 OMR: PS15 Position            */\r
-#define PORT5_OMR_PS15_Msk                                    (0x01UL << PORT5_OMR_PS15_Pos)                            /*!< PORT5 OMR: PS15 Mask                */\r
-#define PORT5_OMR_PR0_Pos                                     16                                                        /*!< PORT5 OMR: PR0 Position             */\r
-#define PORT5_OMR_PR0_Msk                                     (0x01UL << PORT5_OMR_PR0_Pos)                             /*!< PORT5 OMR: PR0 Mask                 */\r
-#define PORT5_OMR_PR1_Pos                                     17                                                        /*!< PORT5 OMR: PR1 Position             */\r
-#define PORT5_OMR_PR1_Msk                                     (0x01UL << PORT5_OMR_PR1_Pos)                             /*!< PORT5 OMR: PR1 Mask                 */\r
-#define PORT5_OMR_PR2_Pos                                     18                                                        /*!< PORT5 OMR: PR2 Position             */\r
-#define PORT5_OMR_PR2_Msk                                     (0x01UL << PORT5_OMR_PR2_Pos)                             /*!< PORT5 OMR: PR2 Mask                 */\r
-#define PORT5_OMR_PR3_Pos                                     19                                                        /*!< PORT5 OMR: PR3 Position             */\r
-#define PORT5_OMR_PR3_Msk                                     (0x01UL << PORT5_OMR_PR3_Pos)                             /*!< PORT5 OMR: PR3 Mask                 */\r
-#define PORT5_OMR_PR4_Pos                                     20                                                        /*!< PORT5 OMR: PR4 Position             */\r
-#define PORT5_OMR_PR4_Msk                                     (0x01UL << PORT5_OMR_PR4_Pos)                             /*!< PORT5 OMR: PR4 Mask                 */\r
-#define PORT5_OMR_PR5_Pos                                     21                                                        /*!< PORT5 OMR: PR5 Position             */\r
-#define PORT5_OMR_PR5_Msk                                     (0x01UL << PORT5_OMR_PR5_Pos)                             /*!< PORT5 OMR: PR5 Mask                 */\r
-#define PORT5_OMR_PR6_Pos                                     22                                                        /*!< PORT5 OMR: PR6 Position             */\r
-#define PORT5_OMR_PR6_Msk                                     (0x01UL << PORT5_OMR_PR6_Pos)                             /*!< PORT5 OMR: PR6 Mask                 */\r
-#define PORT5_OMR_PR7_Pos                                     23                                                        /*!< PORT5 OMR: PR7 Position             */\r
-#define PORT5_OMR_PR7_Msk                                     (0x01UL << PORT5_OMR_PR7_Pos)                             /*!< PORT5 OMR: PR7 Mask                 */\r
-#define PORT5_OMR_PR8_Pos                                     24                                                        /*!< PORT5 OMR: PR8 Position             */\r
-#define PORT5_OMR_PR8_Msk                                     (0x01UL << PORT5_OMR_PR8_Pos)                             /*!< PORT5 OMR: PR8 Mask                 */\r
-#define PORT5_OMR_PR9_Pos                                     25                                                        /*!< PORT5 OMR: PR9 Position             */\r
-#define PORT5_OMR_PR9_Msk                                     (0x01UL << PORT5_OMR_PR9_Pos)                             /*!< PORT5 OMR: PR9 Mask                 */\r
-#define PORT5_OMR_PR10_Pos                                    26                                                        /*!< PORT5 OMR: PR10 Position            */\r
-#define PORT5_OMR_PR10_Msk                                    (0x01UL << PORT5_OMR_PR10_Pos)                            /*!< PORT5 OMR: PR10 Mask                */\r
-#define PORT5_OMR_PR11_Pos                                    27                                                        /*!< PORT5 OMR: PR11 Position            */\r
-#define PORT5_OMR_PR11_Msk                                    (0x01UL << PORT5_OMR_PR11_Pos)                            /*!< PORT5 OMR: PR11 Mask                */\r
-#define PORT5_OMR_PR12_Pos                                    28                                                        /*!< PORT5 OMR: PR12 Position            */\r
-#define PORT5_OMR_PR12_Msk                                    (0x01UL << PORT5_OMR_PR12_Pos)                            /*!< PORT5 OMR: PR12 Mask                */\r
-#define PORT5_OMR_PR13_Pos                                    29                                                        /*!< PORT5 OMR: PR13 Position            */\r
-#define PORT5_OMR_PR13_Msk                                    (0x01UL << PORT5_OMR_PR13_Pos)                            /*!< PORT5 OMR: PR13 Mask                */\r
-#define PORT5_OMR_PR14_Pos                                    30                                                        /*!< PORT5 OMR: PR14 Position            */\r
-#define PORT5_OMR_PR14_Msk                                    (0x01UL << PORT5_OMR_PR14_Pos)                            /*!< PORT5 OMR: PR14 Mask                */\r
-#define PORT5_OMR_PR15_Pos                                    31                                                        /*!< PORT5 OMR: PR15 Position            */\r
-#define PORT5_OMR_PR15_Msk                                    (0x01UL << PORT5_OMR_PR15_Pos)                            /*!< PORT5 OMR: PR15 Mask                */\r
-\r
-// ---------------------------------------  PORT5_IOCR0  ------------------------------------------\r
-#define PORT5_IOCR0_PC0_Pos                                   3                                                         /*!< PORT5 IOCR0: PC0 Position           */\r
-#define PORT5_IOCR0_PC0_Msk                                   (0x1fUL << PORT5_IOCR0_PC0_Pos)                           /*!< PORT5 IOCR0: PC0 Mask               */\r
-#define PORT5_IOCR0_PC1_Pos                                   11                                                        /*!< PORT5 IOCR0: PC1 Position           */\r
-#define PORT5_IOCR0_PC1_Msk                                   (0x1fUL << PORT5_IOCR0_PC1_Pos)                           /*!< PORT5 IOCR0: PC1 Mask               */\r
-#define PORT5_IOCR0_PC2_Pos                                   19                                                        /*!< PORT5 IOCR0: PC2 Position           */\r
-#define PORT5_IOCR0_PC2_Msk                                   (0x1fUL << PORT5_IOCR0_PC2_Pos)                           /*!< PORT5 IOCR0: PC2 Mask               */\r
-#define PORT5_IOCR0_PC3_Pos                                   27                                                        /*!< PORT5 IOCR0: PC3 Position           */\r
-#define PORT5_IOCR0_PC3_Msk                                   (0x1fUL << PORT5_IOCR0_PC3_Pos)                           /*!< PORT5 IOCR0: PC3 Mask               */\r
-\r
-// ---------------------------------------  PORT5_IOCR4  ------------------------------------------\r
-#define PORT5_IOCR4_PC4_Pos                                   3                                                         /*!< PORT5 IOCR4: PC4 Position           */\r
-#define PORT5_IOCR4_PC4_Msk                                   (0x1fUL << PORT5_IOCR4_PC4_Pos)                           /*!< PORT5 IOCR4: PC4 Mask               */\r
-#define PORT5_IOCR4_PC5_Pos                                   11                                                        /*!< PORT5 IOCR4: PC5 Position           */\r
-#define PORT5_IOCR4_PC5_Msk                                   (0x1fUL << PORT5_IOCR4_PC5_Pos)                           /*!< PORT5 IOCR4: PC5 Mask               */\r
-#define PORT5_IOCR4_PC6_Pos                                   19                                                        /*!< PORT5 IOCR4: PC6 Position           */\r
-#define PORT5_IOCR4_PC6_Msk                                   (0x1fUL << PORT5_IOCR4_PC6_Pos)                           /*!< PORT5 IOCR4: PC6 Mask               */\r
-#define PORT5_IOCR4_PC7_Pos                                   27                                                        /*!< PORT5 IOCR4: PC7 Position           */\r
-#define PORT5_IOCR4_PC7_Msk                                   (0x1fUL << PORT5_IOCR4_PC7_Pos)                           /*!< PORT5 IOCR4: PC7 Mask               */\r
-\r
-// ---------------------------------------  PORT5_IOCR8  ------------------------------------------\r
-#define PORT5_IOCR8_PC8_Pos                                   3                                                         /*!< PORT5 IOCR8: PC8 Position           */\r
-#define PORT5_IOCR8_PC8_Msk                                   (0x1fUL << PORT5_IOCR8_PC8_Pos)                           /*!< PORT5 IOCR8: PC8 Mask               */\r
-#define PORT5_IOCR8_PC9_Pos                                   11                                                        /*!< PORT5 IOCR8: PC9 Position           */\r
-#define PORT5_IOCR8_PC9_Msk                                   (0x1fUL << PORT5_IOCR8_PC9_Pos)                           /*!< PORT5 IOCR8: PC9 Mask               */\r
-#define PORT5_IOCR8_PC10_Pos                                  19                                                        /*!< PORT5 IOCR8: PC10 Position          */\r
-#define PORT5_IOCR8_PC10_Msk                                  (0x1fUL << PORT5_IOCR8_PC10_Pos)                          /*!< PORT5 IOCR8: PC10 Mask              */\r
-#define PORT5_IOCR8_PC11_Pos                                  27                                                        /*!< PORT5 IOCR8: PC11 Position          */\r
-#define PORT5_IOCR8_PC11_Msk                                  (0x1fUL << PORT5_IOCR8_PC11_Pos)                          /*!< PORT5 IOCR8: PC11 Mask              */\r
-\r
-// ----------------------------------------  PORT5_IN  --------------------------------------------\r
-#define PORT5_IN_P0_Pos                                       0                                                         /*!< PORT5 IN: P0 Position               */\r
-#define PORT5_IN_P0_Msk                                       (0x01UL << PORT5_IN_P0_Pos)                               /*!< PORT5 IN: P0 Mask                   */\r
-#define PORT5_IN_P1_Pos                                       1                                                         /*!< PORT5 IN: P1 Position               */\r
-#define PORT5_IN_P1_Msk                                       (0x01UL << PORT5_IN_P1_Pos)                               /*!< PORT5 IN: P1 Mask                   */\r
-#define PORT5_IN_P2_Pos                                       2                                                         /*!< PORT5 IN: P2 Position               */\r
-#define PORT5_IN_P2_Msk                                       (0x01UL << PORT5_IN_P2_Pos)                               /*!< PORT5 IN: P2 Mask                   */\r
-#define PORT5_IN_P3_Pos                                       3                                                         /*!< PORT5 IN: P3 Position               */\r
-#define PORT5_IN_P3_Msk                                       (0x01UL << PORT5_IN_P3_Pos)                               /*!< PORT5 IN: P3 Mask                   */\r
-#define PORT5_IN_P4_Pos                                       4                                                         /*!< PORT5 IN: P4 Position               */\r
-#define PORT5_IN_P4_Msk                                       (0x01UL << PORT5_IN_P4_Pos)                               /*!< PORT5 IN: P4 Mask                   */\r
-#define PORT5_IN_P5_Pos                                       5                                                         /*!< PORT5 IN: P5 Position               */\r
-#define PORT5_IN_P5_Msk                                       (0x01UL << PORT5_IN_P5_Pos)                               /*!< PORT5 IN: P5 Mask                   */\r
-#define PORT5_IN_P6_Pos                                       6                                                         /*!< PORT5 IN: P6 Position               */\r
-#define PORT5_IN_P6_Msk                                       (0x01UL << PORT5_IN_P6_Pos)                               /*!< PORT5 IN: P6 Mask                   */\r
-#define PORT5_IN_P7_Pos                                       7                                                         /*!< PORT5 IN: P7 Position               */\r
-#define PORT5_IN_P7_Msk                                       (0x01UL << PORT5_IN_P7_Pos)                               /*!< PORT5 IN: P7 Mask                   */\r
-#define PORT5_IN_P8_Pos                                       8                                                         /*!< PORT5 IN: P8 Position               */\r
-#define PORT5_IN_P8_Msk                                       (0x01UL << PORT5_IN_P8_Pos)                               /*!< PORT5 IN: P8 Mask                   */\r
-#define PORT5_IN_P9_Pos                                       9                                                         /*!< PORT5 IN: P9 Position               */\r
-#define PORT5_IN_P9_Msk                                       (0x01UL << PORT5_IN_P9_Pos)                               /*!< PORT5 IN: P9 Mask                   */\r
-#define PORT5_IN_P10_Pos                                      10                                                        /*!< PORT5 IN: P10 Position              */\r
-#define PORT5_IN_P10_Msk                                      (0x01UL << PORT5_IN_P10_Pos)                              /*!< PORT5 IN: P10 Mask                  */\r
-#define PORT5_IN_P11_Pos                                      11                                                        /*!< PORT5 IN: P11 Position              */\r
-#define PORT5_IN_P11_Msk                                      (0x01UL << PORT5_IN_P11_Pos)                              /*!< PORT5 IN: P11 Mask                  */\r
-#define PORT5_IN_P12_Pos                                      12                                                        /*!< PORT5 IN: P12 Position              */\r
-#define PORT5_IN_P12_Msk                                      (0x01UL << PORT5_IN_P12_Pos)                              /*!< PORT5 IN: P12 Mask                  */\r
-#define PORT5_IN_P13_Pos                                      13                                                        /*!< PORT5 IN: P13 Position              */\r
-#define PORT5_IN_P13_Msk                                      (0x01UL << PORT5_IN_P13_Pos)                              /*!< PORT5 IN: P13 Mask                  */\r
-#define PORT5_IN_P14_Pos                                      14                                                        /*!< PORT5 IN: P14 Position              */\r
-#define PORT5_IN_P14_Msk                                      (0x01UL << PORT5_IN_P14_Pos)                              /*!< PORT5 IN: P14 Mask                  */\r
-#define PORT5_IN_P15_Pos                                      15                                                        /*!< PORT5 IN: P15 Position              */\r
-#define PORT5_IN_P15_Msk                                      (0x01UL << PORT5_IN_P15_Pos)                              /*!< PORT5 IN: P15 Mask                  */\r
-\r
-// ---------------------------------------  PORT5_PDR0  -------------------------------------------\r
-#define PORT5_PDR0_PD0_Pos                                    0                                                         /*!< PORT5 PDR0: PD0 Position            */\r
-#define PORT5_PDR0_PD0_Msk                                    (0x07UL << PORT5_PDR0_PD0_Pos)                            /*!< PORT5 PDR0: PD0 Mask                */\r
-#define PORT5_PDR0_PD1_Pos                                    4                                                         /*!< PORT5 PDR0: PD1 Position            */\r
-#define PORT5_PDR0_PD1_Msk                                    (0x07UL << PORT5_PDR0_PD1_Pos)                            /*!< PORT5 PDR0: PD1 Mask                */\r
-#define PORT5_PDR0_PD2_Pos                                    8                                                         /*!< PORT5 PDR0: PD2 Position            */\r
-#define PORT5_PDR0_PD2_Msk                                    (0x07UL << PORT5_PDR0_PD2_Pos)                            /*!< PORT5 PDR0: PD2 Mask                */\r
-#define PORT5_PDR0_PD3_Pos                                    12                                                        /*!< PORT5 PDR0: PD3 Position            */\r
-#define PORT5_PDR0_PD3_Msk                                    (0x07UL << PORT5_PDR0_PD3_Pos)                            /*!< PORT5 PDR0: PD3 Mask                */\r
-#define PORT5_PDR0_PD4_Pos                                    16                                                        /*!< PORT5 PDR0: PD4 Position            */\r
-#define PORT5_PDR0_PD4_Msk                                    (0x07UL << PORT5_PDR0_PD4_Pos)                            /*!< PORT5 PDR0: PD4 Mask                */\r
-#define PORT5_PDR0_PD5_Pos                                    20                                                        /*!< PORT5 PDR0: PD5 Position            */\r
-#define PORT5_PDR0_PD5_Msk                                    (0x07UL << PORT5_PDR0_PD5_Pos)                            /*!< PORT5 PDR0: PD5 Mask                */\r
-#define PORT5_PDR0_PD6_Pos                                    24                                                        /*!< PORT5 PDR0: PD6 Position            */\r
-#define PORT5_PDR0_PD6_Msk                                    (0x07UL << PORT5_PDR0_PD6_Pos)                            /*!< PORT5 PDR0: PD6 Mask                */\r
-#define PORT5_PDR0_PD7_Pos                                    28                                                        /*!< PORT5 PDR0: PD7 Position            */\r
-#define PORT5_PDR0_PD7_Msk                                    (0x07UL << PORT5_PDR0_PD7_Pos)                            /*!< PORT5 PDR0: PD7 Mask                */\r
-\r
-// ---------------------------------------  PORT5_PDR1  -------------------------------------------\r
-#define PORT5_PDR1_PD8_Pos                                    0                                                         /*!< PORT5 PDR1: PD8 Position            */\r
-#define PORT5_PDR1_PD8_Msk                                    (0x07UL << PORT5_PDR1_PD8_Pos)                            /*!< PORT5 PDR1: PD8 Mask                */\r
-#define PORT5_PDR1_PD9_Pos                                    4                                                         /*!< PORT5 PDR1: PD9 Position            */\r
-#define PORT5_PDR1_PD9_Msk                                    (0x07UL << PORT5_PDR1_PD9_Pos)                            /*!< PORT5 PDR1: PD9 Mask                */\r
-#define PORT5_PDR1_PD10_Pos                                   8                                                         /*!< PORT5 PDR1: PD10 Position           */\r
-#define PORT5_PDR1_PD10_Msk                                   (0x07UL << PORT5_PDR1_PD10_Pos)                           /*!< PORT5 PDR1: PD10 Mask               */\r
-#define PORT5_PDR1_PD11_Pos                                   12                                                        /*!< PORT5 PDR1: PD11 Position           */\r
-#define PORT5_PDR1_PD11_Msk                                   (0x07UL << PORT5_PDR1_PD11_Pos)                           /*!< PORT5 PDR1: PD11 Mask               */\r
-#define PORT5_PDR1_PD12_Pos                                   16                                                        /*!< PORT5 PDR1: PD12 Position           */\r
-#define PORT5_PDR1_PD12_Msk                                   (0x07UL << PORT5_PDR1_PD12_Pos)                           /*!< PORT5 PDR1: PD12 Mask               */\r
-#define PORT5_PDR1_PD13_Pos                                   20                                                        /*!< PORT5 PDR1: PD13 Position           */\r
-#define PORT5_PDR1_PD13_Msk                                   (0x07UL << PORT5_PDR1_PD13_Pos)                           /*!< PORT5 PDR1: PD13 Mask               */\r
-#define PORT5_PDR1_PD14_Pos                                   24                                                        /*!< PORT5 PDR1: PD14 Position           */\r
-#define PORT5_PDR1_PD14_Msk                                   (0x07UL << PORT5_PDR1_PD14_Pos)                           /*!< PORT5 PDR1: PD14 Mask               */\r
-#define PORT5_PDR1_PD15_Pos                                   28                                                        /*!< PORT5 PDR1: PD15 Position           */\r
-#define PORT5_PDR1_PD15_Msk                                   (0x07UL << PORT5_PDR1_PD15_Pos)                           /*!< PORT5 PDR1: PD15 Mask               */\r
-\r
-// ---------------------------------------  PORT5_PDISC  ------------------------------------------\r
-#define PORT5_PDISC_PDIS0_Pos                                 0                                                         /*!< PORT5 PDISC: PDIS0 Position         */\r
-#define PORT5_PDISC_PDIS0_Msk                                 (0x01UL << PORT5_PDISC_PDIS0_Pos)                         /*!< PORT5 PDISC: PDIS0 Mask             */\r
-#define PORT5_PDISC_PDIS1_Pos                                 1                                                         /*!< PORT5 PDISC: PDIS1 Position         */\r
-#define PORT5_PDISC_PDIS1_Msk                                 (0x01UL << PORT5_PDISC_PDIS1_Pos)                         /*!< PORT5 PDISC: PDIS1 Mask             */\r
-#define PORT5_PDISC_PDIS2_Pos                                 2                                                         /*!< PORT5 PDISC: PDIS2 Position         */\r
-#define PORT5_PDISC_PDIS2_Msk                                 (0x01UL << PORT5_PDISC_PDIS2_Pos)                         /*!< PORT5 PDISC: PDIS2 Mask             */\r
-#define PORT5_PDISC_PDIS3_Pos                                 3                                                         /*!< PORT5 PDISC: PDIS3 Position         */\r
-#define PORT5_PDISC_PDIS3_Msk                                 (0x01UL << PORT5_PDISC_PDIS3_Pos)                         /*!< PORT5 PDISC: PDIS3 Mask             */\r
-#define PORT5_PDISC_PDIS4_Pos                                 4                                                         /*!< PORT5 PDISC: PDIS4 Position         */\r
-#define PORT5_PDISC_PDIS4_Msk                                 (0x01UL << PORT5_PDISC_PDIS4_Pos)                         /*!< PORT5 PDISC: PDIS4 Mask             */\r
-#define PORT5_PDISC_PDIS5_Pos                                 5                                                         /*!< PORT5 PDISC: PDIS5 Position         */\r
-#define PORT5_PDISC_PDIS5_Msk                                 (0x01UL << PORT5_PDISC_PDIS5_Pos)                         /*!< PORT5 PDISC: PDIS5 Mask             */\r
-#define PORT5_PDISC_PDIS6_Pos                                 6                                                         /*!< PORT5 PDISC: PDIS6 Position         */\r
-#define PORT5_PDISC_PDIS6_Msk                                 (0x01UL << PORT5_PDISC_PDIS6_Pos)                         /*!< PORT5 PDISC: PDIS6 Mask             */\r
-#define PORT5_PDISC_PDIS7_Pos                                 7                                                         /*!< PORT5 PDISC: PDIS7 Position         */\r
-#define PORT5_PDISC_PDIS7_Msk                                 (0x01UL << PORT5_PDISC_PDIS7_Pos)                         /*!< PORT5 PDISC: PDIS7 Mask             */\r
-#define PORT5_PDISC_PDIS8_Pos                                 8                                                         /*!< PORT5 PDISC: PDIS8 Position         */\r
-#define PORT5_PDISC_PDIS8_Msk                                 (0x01UL << PORT5_PDISC_PDIS8_Pos)                         /*!< PORT5 PDISC: PDIS8 Mask             */\r
-#define PORT5_PDISC_PDIS9_Pos                                 9                                                         /*!< PORT5 PDISC: PDIS9 Position         */\r
-#define PORT5_PDISC_PDIS9_Msk                                 (0x01UL << PORT5_PDISC_PDIS9_Pos)                         /*!< PORT5 PDISC: PDIS9 Mask             */\r
-#define PORT5_PDISC_PDIS10_Pos                                10                                                        /*!< PORT5 PDISC: PDIS10 Position        */\r
-#define PORT5_PDISC_PDIS10_Msk                                (0x01UL << PORT5_PDISC_PDIS10_Pos)                        /*!< PORT5 PDISC: PDIS10 Mask            */\r
-#define PORT5_PDISC_PDIS11_Pos                                11                                                        /*!< PORT5 PDISC: PDIS11 Position        */\r
-#define PORT5_PDISC_PDIS11_Msk                                (0x01UL << PORT5_PDISC_PDIS11_Pos)                        /*!< PORT5 PDISC: PDIS11 Mask            */\r
-#define PORT5_PDISC_PDIS12_Pos                                12                                                        /*!< PORT5 PDISC: PDIS12 Position        */\r
-#define PORT5_PDISC_PDIS12_Msk                                (0x01UL << PORT5_PDISC_PDIS12_Pos)                        /*!< PORT5 PDISC: PDIS12 Mask            */\r
-#define PORT5_PDISC_PDIS13_Pos                                13                                                        /*!< PORT5 PDISC: PDIS13 Position        */\r
-#define PORT5_PDISC_PDIS13_Msk                                (0x01UL << PORT5_PDISC_PDIS13_Pos)                        /*!< PORT5 PDISC: PDIS13 Mask            */\r
-#define PORT5_PDISC_PDIS14_Pos                                14                                                        /*!< PORT5 PDISC: PDIS14 Position        */\r
-#define PORT5_PDISC_PDIS14_Msk                                (0x01UL << PORT5_PDISC_PDIS14_Pos)                        /*!< PORT5 PDISC: PDIS14 Mask            */\r
-#define PORT5_PDISC_PDIS15_Pos                                15                                                        /*!< PORT5 PDISC: PDIS15 Position        */\r
-#define PORT5_PDISC_PDIS15_Msk                                (0x01UL << PORT5_PDISC_PDIS15_Pos)                        /*!< PORT5 PDISC: PDIS15 Mask            */\r
-\r
-// ----------------------------------------  PORT5_PPS  -------------------------------------------\r
-#define PORT5_PPS_PPS0_Pos                                    0                                                         /*!< PORT5 PPS: PPS0 Position            */\r
-#define PORT5_PPS_PPS0_Msk                                    (0x01UL << PORT5_PPS_PPS0_Pos)                            /*!< PORT5 PPS: PPS0 Mask                */\r
-#define PORT5_PPS_PPS1_Pos                                    1                                                         /*!< PORT5 PPS: PPS1 Position            */\r
-#define PORT5_PPS_PPS1_Msk                                    (0x01UL << PORT5_PPS_PPS1_Pos)                            /*!< PORT5 PPS: PPS1 Mask                */\r
-#define PORT5_PPS_PPS2_Pos                                    2                                                         /*!< PORT5 PPS: PPS2 Position            */\r
-#define PORT5_PPS_PPS2_Msk                                    (0x01UL << PORT5_PPS_PPS2_Pos)                            /*!< PORT5 PPS: PPS2 Mask                */\r
-#define PORT5_PPS_PPS3_Pos                                    3                                                         /*!< PORT5 PPS: PPS3 Position            */\r
-#define PORT5_PPS_PPS3_Msk                                    (0x01UL << PORT5_PPS_PPS3_Pos)                            /*!< PORT5 PPS: PPS3 Mask                */\r
-#define PORT5_PPS_PPS4_Pos                                    4                                                         /*!< PORT5 PPS: PPS4 Position            */\r
-#define PORT5_PPS_PPS4_Msk                                    (0x01UL << PORT5_PPS_PPS4_Pos)                            /*!< PORT5 PPS: PPS4 Mask                */\r
-#define PORT5_PPS_PPS5_Pos                                    5                                                         /*!< PORT5 PPS: PPS5 Position            */\r
-#define PORT5_PPS_PPS5_Msk                                    (0x01UL << PORT5_PPS_PPS5_Pos)                            /*!< PORT5 PPS: PPS5 Mask                */\r
-#define PORT5_PPS_PPS6_Pos                                    6                                                         /*!< PORT5 PPS: PPS6 Position            */\r
-#define PORT5_PPS_PPS6_Msk                                    (0x01UL << PORT5_PPS_PPS6_Pos)                            /*!< PORT5 PPS: PPS6 Mask                */\r
-#define PORT5_PPS_PPS7_Pos                                    7                                                         /*!< PORT5 PPS: PPS7 Position            */\r
-#define PORT5_PPS_PPS7_Msk                                    (0x01UL << PORT5_PPS_PPS7_Pos)                            /*!< PORT5 PPS: PPS7 Mask                */\r
-#define PORT5_PPS_PPS8_Pos                                    8                                                         /*!< PORT5 PPS: PPS8 Position            */\r
-#define PORT5_PPS_PPS8_Msk                                    (0x01UL << PORT5_PPS_PPS8_Pos)                            /*!< PORT5 PPS: PPS8 Mask                */\r
-#define PORT5_PPS_PPS9_Pos                                    9                                                         /*!< PORT5 PPS: PPS9 Position            */\r
-#define PORT5_PPS_PPS9_Msk                                    (0x01UL << PORT5_PPS_PPS9_Pos)                            /*!< PORT5 PPS: PPS9 Mask                */\r
-#define PORT5_PPS_PPS10_Pos                                   10                                                        /*!< PORT5 PPS: PPS10 Position           */\r
-#define PORT5_PPS_PPS10_Msk                                   (0x01UL << PORT5_PPS_PPS10_Pos)                           /*!< PORT5 PPS: PPS10 Mask               */\r
-#define PORT5_PPS_PPS11_Pos                                   11                                                        /*!< PORT5 PPS: PPS11 Position           */\r
-#define PORT5_PPS_PPS11_Msk                                   (0x01UL << PORT5_PPS_PPS11_Pos)                           /*!< PORT5 PPS: PPS11 Mask               */\r
-#define PORT5_PPS_PPS12_Pos                                   12                                                        /*!< PORT5 PPS: PPS12 Position           */\r
-#define PORT5_PPS_PPS12_Msk                                   (0x01UL << PORT5_PPS_PPS12_Pos)                           /*!< PORT5 PPS: PPS12 Mask               */\r
-#define PORT5_PPS_PPS13_Pos                                   13                                                        /*!< PORT5 PPS: PPS13 Position           */\r
-#define PORT5_PPS_PPS13_Msk                                   (0x01UL << PORT5_PPS_PPS13_Pos)                           /*!< PORT5 PPS: PPS13 Mask               */\r
-#define PORT5_PPS_PPS14_Pos                                   14                                                        /*!< PORT5 PPS: PPS14 Position           */\r
-#define PORT5_PPS_PPS14_Msk                                   (0x01UL << PORT5_PPS_PPS14_Pos)                           /*!< PORT5 PPS: PPS14 Mask               */\r
-#define PORT5_PPS_PPS15_Pos                                   15                                                        /*!< PORT5 PPS: PPS15 Position           */\r
-#define PORT5_PPS_PPS15_Msk                                   (0x01UL << PORT5_PPS_PPS15_Pos)                           /*!< PORT5 PPS: PPS15 Mask               */\r
-\r
-// ---------------------------------------  PORT5_HWSEL  ------------------------------------------\r
-#define PORT5_HWSEL_HW0_Pos                                   0                                                         /*!< PORT5 HWSEL: HW0 Position           */\r
-#define PORT5_HWSEL_HW0_Msk                                   (0x03UL << PORT5_HWSEL_HW0_Pos)                           /*!< PORT5 HWSEL: HW0 Mask               */\r
-#define PORT5_HWSEL_HW1_Pos                                   2                                                         /*!< PORT5 HWSEL: HW1 Position           */\r
-#define PORT5_HWSEL_HW1_Msk                                   (0x03UL << PORT5_HWSEL_HW1_Pos)                           /*!< PORT5 HWSEL: HW1 Mask               */\r
-#define PORT5_HWSEL_HW2_Pos                                   4                                                         /*!< PORT5 HWSEL: HW2 Position           */\r
-#define PORT5_HWSEL_HW2_Msk                                   (0x03UL << PORT5_HWSEL_HW2_Pos)                           /*!< PORT5 HWSEL: HW2 Mask               */\r
-#define PORT5_HWSEL_HW3_Pos                                   6                                                         /*!< PORT5 HWSEL: HW3 Position           */\r
-#define PORT5_HWSEL_HW3_Msk                                   (0x03UL << PORT5_HWSEL_HW3_Pos)                           /*!< PORT5 HWSEL: HW3 Mask               */\r
-#define PORT5_HWSEL_HW4_Pos                                   8                                                         /*!< PORT5 HWSEL: HW4 Position           */\r
-#define PORT5_HWSEL_HW4_Msk                                   (0x03UL << PORT5_HWSEL_HW4_Pos)                           /*!< PORT5 HWSEL: HW4 Mask               */\r
-#define PORT5_HWSEL_HW5_Pos                                   10                                                        /*!< PORT5 HWSEL: HW5 Position           */\r
-#define PORT5_HWSEL_HW5_Msk                                   (0x03UL << PORT5_HWSEL_HW5_Pos)                           /*!< PORT5 HWSEL: HW5 Mask               */\r
-#define PORT5_HWSEL_HW6_Pos                                   12                                                        /*!< PORT5 HWSEL: HW6 Position           */\r
-#define PORT5_HWSEL_HW6_Msk                                   (0x03UL << PORT5_HWSEL_HW6_Pos)                           /*!< PORT5 HWSEL: HW6 Mask               */\r
-#define PORT5_HWSEL_HW7_Pos                                   14                                                        /*!< PORT5 HWSEL: HW7 Position           */\r
-#define PORT5_HWSEL_HW7_Msk                                   (0x03UL << PORT5_HWSEL_HW7_Pos)                           /*!< PORT5 HWSEL: HW7 Mask               */\r
-#define PORT5_HWSEL_HW8_Pos                                   16                                                        /*!< PORT5 HWSEL: HW8 Position           */\r
-#define PORT5_HWSEL_HW8_Msk                                   (0x03UL << PORT5_HWSEL_HW8_Pos)                           /*!< PORT5 HWSEL: HW8 Mask               */\r
-#define PORT5_HWSEL_HW9_Pos                                   18                                                        /*!< PORT5 HWSEL: HW9 Position           */\r
-#define PORT5_HWSEL_HW9_Msk                                   (0x03UL << PORT5_HWSEL_HW9_Pos)                           /*!< PORT5 HWSEL: HW9 Mask               */\r
-#define PORT5_HWSEL_HW10_Pos                                  20                                                        /*!< PORT5 HWSEL: HW10 Position          */\r
-#define PORT5_HWSEL_HW10_Msk                                  (0x03UL << PORT5_HWSEL_HW10_Pos)                          /*!< PORT5 HWSEL: HW10 Mask              */\r
-#define PORT5_HWSEL_HW11_Pos                                  22                                                        /*!< PORT5 HWSEL: HW11 Position          */\r
-#define PORT5_HWSEL_HW11_Msk                                  (0x03UL << PORT5_HWSEL_HW11_Pos)                          /*!< PORT5 HWSEL: HW11 Mask              */\r
-#define PORT5_HWSEL_HW12_Pos                                  24                                                        /*!< PORT5 HWSEL: HW12 Position          */\r
-#define PORT5_HWSEL_HW12_Msk                                  (0x03UL << PORT5_HWSEL_HW12_Pos)                          /*!< PORT5 HWSEL: HW12 Mask              */\r
-#define PORT5_HWSEL_HW13_Pos                                  26                                                        /*!< PORT5 HWSEL: HW13 Position          */\r
-#define PORT5_HWSEL_HW13_Msk                                  (0x03UL << PORT5_HWSEL_HW13_Pos)                          /*!< PORT5 HWSEL: HW13 Mask              */\r
-#define PORT5_HWSEL_HW14_Pos                                  28                                                        /*!< PORT5 HWSEL: HW14 Position          */\r
-#define PORT5_HWSEL_HW14_Msk                                  (0x03UL << PORT5_HWSEL_HW14_Pos)                          /*!< PORT5 HWSEL: HW14 Mask              */\r
-#define PORT5_HWSEL_HW15_Pos                                  30                                                        /*!< PORT5 HWSEL: HW15 Position          */\r
-#define PORT5_HWSEL_HW15_Msk                                  (0x03UL << PORT5_HWSEL_HW15_Pos)                          /*!< PORT5 HWSEL: HW15 Mask              */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                 PORT6 Position & Mask                                -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ----------------------------------------  PORT6_OUT  -------------------------------------------\r
-#define PORT6_OUT_P0_Pos                                      0                                                         /*!< PORT6 OUT: P0 Position              */\r
-#define PORT6_OUT_P0_Msk                                      (0x01UL << PORT6_OUT_P0_Pos)                              /*!< PORT6 OUT: P0 Mask                  */\r
-#define PORT6_OUT_P1_Pos                                      1                                                         /*!< PORT6 OUT: P1 Position              */\r
-#define PORT6_OUT_P1_Msk                                      (0x01UL << PORT6_OUT_P1_Pos)                              /*!< PORT6 OUT: P1 Mask                  */\r
-#define PORT6_OUT_P2_Pos                                      2                                                         /*!< PORT6 OUT: P2 Position              */\r
-#define PORT6_OUT_P2_Msk                                      (0x01UL << PORT6_OUT_P2_Pos)                              /*!< PORT6 OUT: P2 Mask                  */\r
-#define PORT6_OUT_P3_Pos                                      3                                                         /*!< PORT6 OUT: P3 Position              */\r
-#define PORT6_OUT_P3_Msk                                      (0x01UL << PORT6_OUT_P3_Pos)                              /*!< PORT6 OUT: P3 Mask                  */\r
-#define PORT6_OUT_P4_Pos                                      4                                                         /*!< PORT6 OUT: P4 Position              */\r
-#define PORT6_OUT_P4_Msk                                      (0x01UL << PORT6_OUT_P4_Pos)                              /*!< PORT6 OUT: P4 Mask                  */\r
-#define PORT6_OUT_P5_Pos                                      5                                                         /*!< PORT6 OUT: P5 Position              */\r
-#define PORT6_OUT_P5_Msk                                      (0x01UL << PORT6_OUT_P5_Pos)                              /*!< PORT6 OUT: P5 Mask                  */\r
-#define PORT6_OUT_P6_Pos                                      6                                                         /*!< PORT6 OUT: P6 Position              */\r
-#define PORT6_OUT_P6_Msk                                      (0x01UL << PORT6_OUT_P6_Pos)                              /*!< PORT6 OUT: P6 Mask                  */\r
-#define PORT6_OUT_P7_Pos                                      7                                                         /*!< PORT6 OUT: P7 Position              */\r
-#define PORT6_OUT_P7_Msk                                      (0x01UL << PORT6_OUT_P7_Pos)                              /*!< PORT6 OUT: P7 Mask                  */\r
-#define PORT6_OUT_P8_Pos                                      8                                                         /*!< PORT6 OUT: P8 Position              */\r
-#define PORT6_OUT_P8_Msk                                      (0x01UL << PORT6_OUT_P8_Pos)                              /*!< PORT6 OUT: P8 Mask                  */\r
-#define PORT6_OUT_P9_Pos                                      9                                                         /*!< PORT6 OUT: P9 Position              */\r
-#define PORT6_OUT_P9_Msk                                      (0x01UL << PORT6_OUT_P9_Pos)                              /*!< PORT6 OUT: P9 Mask                  */\r
-#define PORT6_OUT_P10_Pos                                     10                                                        /*!< PORT6 OUT: P10 Position             */\r
-#define PORT6_OUT_P10_Msk                                     (0x01UL << PORT6_OUT_P10_Pos)                             /*!< PORT6 OUT: P10 Mask                 */\r
-#define PORT6_OUT_P11_Pos                                     11                                                        /*!< PORT6 OUT: P11 Position             */\r
-#define PORT6_OUT_P11_Msk                                     (0x01UL << PORT6_OUT_P11_Pos)                             /*!< PORT6 OUT: P11 Mask                 */\r
-#define PORT6_OUT_P12_Pos                                     12                                                        /*!< PORT6 OUT: P12 Position             */\r
-#define PORT6_OUT_P12_Msk                                     (0x01UL << PORT6_OUT_P12_Pos)                             /*!< PORT6 OUT: P12 Mask                 */\r
-#define PORT6_OUT_P13_Pos                                     13                                                        /*!< PORT6 OUT: P13 Position             */\r
-#define PORT6_OUT_P13_Msk                                     (0x01UL << PORT6_OUT_P13_Pos)                             /*!< PORT6 OUT: P13 Mask                 */\r
-#define PORT6_OUT_P14_Pos                                     14                                                        /*!< PORT6 OUT: P14 Position             */\r
-#define PORT6_OUT_P14_Msk                                     (0x01UL << PORT6_OUT_P14_Pos)                             /*!< PORT6 OUT: P14 Mask                 */\r
-#define PORT6_OUT_P15_Pos                                     15                                                        /*!< PORT6 OUT: P15 Position             */\r
-#define PORT6_OUT_P15_Msk                                     (0x01UL << PORT6_OUT_P15_Pos)                             /*!< PORT6 OUT: P15 Mask                 */\r
-\r
-// ----------------------------------------  PORT6_OMR  -------------------------------------------\r
-#define PORT6_OMR_PS0_Pos                                     0                                                         /*!< PORT6 OMR: PS0 Position             */\r
-#define PORT6_OMR_PS0_Msk                                     (0x01UL << PORT6_OMR_PS0_Pos)                             /*!< PORT6 OMR: PS0 Mask                 */\r
-#define PORT6_OMR_PS1_Pos                                     1                                                         /*!< PORT6 OMR: PS1 Position             */\r
-#define PORT6_OMR_PS1_Msk                                     (0x01UL << PORT6_OMR_PS1_Pos)                             /*!< PORT6 OMR: PS1 Mask                 */\r
-#define PORT6_OMR_PS2_Pos                                     2                                                         /*!< PORT6 OMR: PS2 Position             */\r
-#define PORT6_OMR_PS2_Msk                                     (0x01UL << PORT6_OMR_PS2_Pos)                             /*!< PORT6 OMR: PS2 Mask                 */\r
-#define PORT6_OMR_PS3_Pos                                     3                                                         /*!< PORT6 OMR: PS3 Position             */\r
-#define PORT6_OMR_PS3_Msk                                     (0x01UL << PORT6_OMR_PS3_Pos)                             /*!< PORT6 OMR: PS3 Mask                 */\r
-#define PORT6_OMR_PS4_Pos                                     4                                                         /*!< PORT6 OMR: PS4 Position             */\r
-#define PORT6_OMR_PS4_Msk                                     (0x01UL << PORT6_OMR_PS4_Pos)                             /*!< PORT6 OMR: PS4 Mask                 */\r
-#define PORT6_OMR_PS5_Pos                                     5                                                         /*!< PORT6 OMR: PS5 Position             */\r
-#define PORT6_OMR_PS5_Msk                                     (0x01UL << PORT6_OMR_PS5_Pos)                             /*!< PORT6 OMR: PS5 Mask                 */\r
-#define PORT6_OMR_PS6_Pos                                     6                                                         /*!< PORT6 OMR: PS6 Position             */\r
-#define PORT6_OMR_PS6_Msk                                     (0x01UL << PORT6_OMR_PS6_Pos)                             /*!< PORT6 OMR: PS6 Mask                 */\r
-#define PORT6_OMR_PS7_Pos                                     7                                                         /*!< PORT6 OMR: PS7 Position             */\r
-#define PORT6_OMR_PS7_Msk                                     (0x01UL << PORT6_OMR_PS7_Pos)                             /*!< PORT6 OMR: PS7 Mask                 */\r
-#define PORT6_OMR_PS8_Pos                                     8                                                         /*!< PORT6 OMR: PS8 Position             */\r
-#define PORT6_OMR_PS8_Msk                                     (0x01UL << PORT6_OMR_PS8_Pos)                             /*!< PORT6 OMR: PS8 Mask                 */\r
-#define PORT6_OMR_PS9_Pos                                     9                                                         /*!< PORT6 OMR: PS9 Position             */\r
-#define PORT6_OMR_PS9_Msk                                     (0x01UL << PORT6_OMR_PS9_Pos)                             /*!< PORT6 OMR: PS9 Mask                 */\r
-#define PORT6_OMR_PS10_Pos                                    10                                                        /*!< PORT6 OMR: PS10 Position            */\r
-#define PORT6_OMR_PS10_Msk                                    (0x01UL << PORT6_OMR_PS10_Pos)                            /*!< PORT6 OMR: PS10 Mask                */\r
-#define PORT6_OMR_PS11_Pos                                    11                                                        /*!< PORT6 OMR: PS11 Position            */\r
-#define PORT6_OMR_PS11_Msk                                    (0x01UL << PORT6_OMR_PS11_Pos)                            /*!< PORT6 OMR: PS11 Mask                */\r
-#define PORT6_OMR_PS12_Pos                                    12                                                        /*!< PORT6 OMR: PS12 Position            */\r
-#define PORT6_OMR_PS12_Msk                                    (0x01UL << PORT6_OMR_PS12_Pos)                            /*!< PORT6 OMR: PS12 Mask                */\r
-#define PORT6_OMR_PS13_Pos                                    13                                                        /*!< PORT6 OMR: PS13 Position            */\r
-#define PORT6_OMR_PS13_Msk                                    (0x01UL << PORT6_OMR_PS13_Pos)                            /*!< PORT6 OMR: PS13 Mask                */\r
-#define PORT6_OMR_PS14_Pos                                    14                                                        /*!< PORT6 OMR: PS14 Position            */\r
-#define PORT6_OMR_PS14_Msk                                    (0x01UL << PORT6_OMR_PS14_Pos)                            /*!< PORT6 OMR: PS14 Mask                */\r
-#define PORT6_OMR_PS15_Pos                                    15                                                        /*!< PORT6 OMR: PS15 Position            */\r
-#define PORT6_OMR_PS15_Msk                                    (0x01UL << PORT6_OMR_PS15_Pos)                            /*!< PORT6 OMR: PS15 Mask                */\r
-#define PORT6_OMR_PR0_Pos                                     16                                                        /*!< PORT6 OMR: PR0 Position             */\r
-#define PORT6_OMR_PR0_Msk                                     (0x01UL << PORT6_OMR_PR0_Pos)                             /*!< PORT6 OMR: PR0 Mask                 */\r
-#define PORT6_OMR_PR1_Pos                                     17                                                        /*!< PORT6 OMR: PR1 Position             */\r
-#define PORT6_OMR_PR1_Msk                                     (0x01UL << PORT6_OMR_PR1_Pos)                             /*!< PORT6 OMR: PR1 Mask                 */\r
-#define PORT6_OMR_PR2_Pos                                     18                                                        /*!< PORT6 OMR: PR2 Position             */\r
-#define PORT6_OMR_PR2_Msk                                     (0x01UL << PORT6_OMR_PR2_Pos)                             /*!< PORT6 OMR: PR2 Mask                 */\r
-#define PORT6_OMR_PR3_Pos                                     19                                                        /*!< PORT6 OMR: PR3 Position             */\r
-#define PORT6_OMR_PR3_Msk                                     (0x01UL << PORT6_OMR_PR3_Pos)                             /*!< PORT6 OMR: PR3 Mask                 */\r
-#define PORT6_OMR_PR4_Pos                                     20                                                        /*!< PORT6 OMR: PR4 Position             */\r
-#define PORT6_OMR_PR4_Msk                                     (0x01UL << PORT6_OMR_PR4_Pos)                             /*!< PORT6 OMR: PR4 Mask                 */\r
-#define PORT6_OMR_PR5_Pos                                     21                                                        /*!< PORT6 OMR: PR5 Position             */\r
-#define PORT6_OMR_PR5_Msk                                     (0x01UL << PORT6_OMR_PR5_Pos)                             /*!< PORT6 OMR: PR5 Mask                 */\r
-#define PORT6_OMR_PR6_Pos                                     22                                                        /*!< PORT6 OMR: PR6 Position             */\r
-#define PORT6_OMR_PR6_Msk                                     (0x01UL << PORT6_OMR_PR6_Pos)                             /*!< PORT6 OMR: PR6 Mask                 */\r
-#define PORT6_OMR_PR7_Pos                                     23                                                        /*!< PORT6 OMR: PR7 Position             */\r
-#define PORT6_OMR_PR7_Msk                                     (0x01UL << PORT6_OMR_PR7_Pos)                             /*!< PORT6 OMR: PR7 Mask                 */\r
-#define PORT6_OMR_PR8_Pos                                     24                                                        /*!< PORT6 OMR: PR8 Position             */\r
-#define PORT6_OMR_PR8_Msk                                     (0x01UL << PORT6_OMR_PR8_Pos)                             /*!< PORT6 OMR: PR8 Mask                 */\r
-#define PORT6_OMR_PR9_Pos                                     25                                                        /*!< PORT6 OMR: PR9 Position             */\r
-#define PORT6_OMR_PR9_Msk                                     (0x01UL << PORT6_OMR_PR9_Pos)                             /*!< PORT6 OMR: PR9 Mask                 */\r
-#define PORT6_OMR_PR10_Pos                                    26                                                        /*!< PORT6 OMR: PR10 Position            */\r
-#define PORT6_OMR_PR10_Msk                                    (0x01UL << PORT6_OMR_PR10_Pos)                            /*!< PORT6 OMR: PR10 Mask                */\r
-#define PORT6_OMR_PR11_Pos                                    27                                                        /*!< PORT6 OMR: PR11 Position            */\r
-#define PORT6_OMR_PR11_Msk                                    (0x01UL << PORT6_OMR_PR11_Pos)                            /*!< PORT6 OMR: PR11 Mask                */\r
-#define PORT6_OMR_PR12_Pos                                    28                                                        /*!< PORT6 OMR: PR12 Position            */\r
-#define PORT6_OMR_PR12_Msk                                    (0x01UL << PORT6_OMR_PR12_Pos)                            /*!< PORT6 OMR: PR12 Mask                */\r
-#define PORT6_OMR_PR13_Pos                                    29                                                        /*!< PORT6 OMR: PR13 Position            */\r
-#define PORT6_OMR_PR13_Msk                                    (0x01UL << PORT6_OMR_PR13_Pos)                            /*!< PORT6 OMR: PR13 Mask                */\r
-#define PORT6_OMR_PR14_Pos                                    30                                                        /*!< PORT6 OMR: PR14 Position            */\r
-#define PORT6_OMR_PR14_Msk                                    (0x01UL << PORT6_OMR_PR14_Pos)                            /*!< PORT6 OMR: PR14 Mask                */\r
-#define PORT6_OMR_PR15_Pos                                    31                                                        /*!< PORT6 OMR: PR15 Position            */\r
-#define PORT6_OMR_PR15_Msk                                    (0x01UL << PORT6_OMR_PR15_Pos)                            /*!< PORT6 OMR: PR15 Mask                */\r
-\r
-// ---------------------------------------  PORT6_IOCR0  ------------------------------------------\r
-#define PORT6_IOCR0_PC0_Pos                                   3                                                         /*!< PORT6 IOCR0: PC0 Position           */\r
-#define PORT6_IOCR0_PC0_Msk                                   (0x1fUL << PORT6_IOCR0_PC0_Pos)                           /*!< PORT6 IOCR0: PC0 Mask               */\r
-#define PORT6_IOCR0_PC1_Pos                                   11                                                        /*!< PORT6 IOCR0: PC1 Position           */\r
-#define PORT6_IOCR0_PC1_Msk                                   (0x1fUL << PORT6_IOCR0_PC1_Pos)                           /*!< PORT6 IOCR0: PC1 Mask               */\r
-#define PORT6_IOCR0_PC2_Pos                                   19                                                        /*!< PORT6 IOCR0: PC2 Position           */\r
-#define PORT6_IOCR0_PC2_Msk                                   (0x1fUL << PORT6_IOCR0_PC2_Pos)                           /*!< PORT6 IOCR0: PC2 Mask               */\r
-#define PORT6_IOCR0_PC3_Pos                                   27                                                        /*!< PORT6 IOCR0: PC3 Position           */\r
-#define PORT6_IOCR0_PC3_Msk                                   (0x1fUL << PORT6_IOCR0_PC3_Pos)                           /*!< PORT6 IOCR0: PC3 Mask               */\r
-\r
-// ---------------------------------------  PORT6_IOCR4  ------------------------------------------\r
-#define PORT6_IOCR4_PC4_Pos                                   3                                                         /*!< PORT6 IOCR4: PC4 Position           */\r
-#define PORT6_IOCR4_PC4_Msk                                   (0x1fUL << PORT6_IOCR4_PC4_Pos)                           /*!< PORT6 IOCR4: PC4 Mask               */\r
-#define PORT6_IOCR4_PC5_Pos                                   11                                                        /*!< PORT6 IOCR4: PC5 Position           */\r
-#define PORT6_IOCR4_PC5_Msk                                   (0x1fUL << PORT6_IOCR4_PC5_Pos)                           /*!< PORT6 IOCR4: PC5 Mask               */\r
-#define PORT6_IOCR4_PC6_Pos                                   19                                                        /*!< PORT6 IOCR4: PC6 Position           */\r
-#define PORT6_IOCR4_PC6_Msk                                   (0x1fUL << PORT6_IOCR4_PC6_Pos)                           /*!< PORT6 IOCR4: PC6 Mask               */\r
-#define PORT6_IOCR4_PC7_Pos                                   27                                                        /*!< PORT6 IOCR4: PC7 Position           */\r
-#define PORT6_IOCR4_PC7_Msk                                   (0x1fUL << PORT6_IOCR4_PC7_Pos)                           /*!< PORT6 IOCR4: PC7 Mask               */\r
-\r
-// ----------------------------------------  PORT6_IN  --------------------------------------------\r
-#define PORT6_IN_P0_Pos                                       0                                                         /*!< PORT6 IN: P0 Position               */\r
-#define PORT6_IN_P0_Msk                                       (0x01UL << PORT6_IN_P0_Pos)                               /*!< PORT6 IN: P0 Mask                   */\r
-#define PORT6_IN_P1_Pos                                       1                                                         /*!< PORT6 IN: P1 Position               */\r
-#define PORT6_IN_P1_Msk                                       (0x01UL << PORT6_IN_P1_Pos)                               /*!< PORT6 IN: P1 Mask                   */\r
-#define PORT6_IN_P2_Pos                                       2                                                         /*!< PORT6 IN: P2 Position               */\r
-#define PORT6_IN_P2_Msk                                       (0x01UL << PORT6_IN_P2_Pos)                               /*!< PORT6 IN: P2 Mask                   */\r
-#define PORT6_IN_P3_Pos                                       3                                                         /*!< PORT6 IN: P3 Position               */\r
-#define PORT6_IN_P3_Msk                                       (0x01UL << PORT6_IN_P3_Pos)                               /*!< PORT6 IN: P3 Mask                   */\r
-#define PORT6_IN_P4_Pos                                       4                                                         /*!< PORT6 IN: P4 Position               */\r
-#define PORT6_IN_P4_Msk                                       (0x01UL << PORT6_IN_P4_Pos)                               /*!< PORT6 IN: P4 Mask                   */\r
-#define PORT6_IN_P5_Pos                                       5                                                         /*!< PORT6 IN: P5 Position               */\r
-#define PORT6_IN_P5_Msk                                       (0x01UL << PORT6_IN_P5_Pos)                               /*!< PORT6 IN: P5 Mask                   */\r
-#define PORT6_IN_P6_Pos                                       6                                                         /*!< PORT6 IN: P6 Position               */\r
-#define PORT6_IN_P6_Msk                                       (0x01UL << PORT6_IN_P6_Pos)                               /*!< PORT6 IN: P6 Mask                   */\r
-#define PORT6_IN_P7_Pos                                       7                                                         /*!< PORT6 IN: P7 Position               */\r
-#define PORT6_IN_P7_Msk                                       (0x01UL << PORT6_IN_P7_Pos)                               /*!< PORT6 IN: P7 Mask                   */\r
-#define PORT6_IN_P8_Pos                                       8                                                         /*!< PORT6 IN: P8 Position               */\r
-#define PORT6_IN_P8_Msk                                       (0x01UL << PORT6_IN_P8_Pos)                               /*!< PORT6 IN: P8 Mask                   */\r
-#define PORT6_IN_P9_Pos                                       9                                                         /*!< PORT6 IN: P9 Position               */\r
-#define PORT6_IN_P9_Msk                                       (0x01UL << PORT6_IN_P9_Pos)                               /*!< PORT6 IN: P9 Mask                   */\r
-#define PORT6_IN_P10_Pos                                      10                                                        /*!< PORT6 IN: P10 Position              */\r
-#define PORT6_IN_P10_Msk                                      (0x01UL << PORT6_IN_P10_Pos)                              /*!< PORT6 IN: P10 Mask                  */\r
-#define PORT6_IN_P11_Pos                                      11                                                        /*!< PORT6 IN: P11 Position              */\r
-#define PORT6_IN_P11_Msk                                      (0x01UL << PORT6_IN_P11_Pos)                              /*!< PORT6 IN: P11 Mask                  */\r
-#define PORT6_IN_P12_Pos                                      12                                                        /*!< PORT6 IN: P12 Position              */\r
-#define PORT6_IN_P12_Msk                                      (0x01UL << PORT6_IN_P12_Pos)                              /*!< PORT6 IN: P12 Mask                  */\r
-#define PORT6_IN_P13_Pos                                      13                                                        /*!< PORT6 IN: P13 Position              */\r
-#define PORT6_IN_P13_Msk                                      (0x01UL << PORT6_IN_P13_Pos)                              /*!< PORT6 IN: P13 Mask                  */\r
-#define PORT6_IN_P14_Pos                                      14                                                        /*!< PORT6 IN: P14 Position              */\r
-#define PORT6_IN_P14_Msk                                      (0x01UL << PORT6_IN_P14_Pos)                              /*!< PORT6 IN: P14 Mask                  */\r
-#define PORT6_IN_P15_Pos                                      15                                                        /*!< PORT6 IN: P15 Position              */\r
-#define PORT6_IN_P15_Msk                                      (0x01UL << PORT6_IN_P15_Pos)                              /*!< PORT6 IN: P15 Mask                  */\r
-\r
-// ---------------------------------------  PORT6_PDR0  -------------------------------------------\r
-#define PORT6_PDR0_PD0_Pos                                    0                                                         /*!< PORT6 PDR0: PD0 Position            */\r
-#define PORT6_PDR0_PD0_Msk                                    (0x07UL << PORT6_PDR0_PD0_Pos)                            /*!< PORT6 PDR0: PD0 Mask                */\r
-#define PORT6_PDR0_PD1_Pos                                    4                                                         /*!< PORT6 PDR0: PD1 Position            */\r
-#define PORT6_PDR0_PD1_Msk                                    (0x07UL << PORT6_PDR0_PD1_Pos)                            /*!< PORT6 PDR0: PD1 Mask                */\r
-#define PORT6_PDR0_PD2_Pos                                    8                                                         /*!< PORT6 PDR0: PD2 Position            */\r
-#define PORT6_PDR0_PD2_Msk                                    (0x07UL << PORT6_PDR0_PD2_Pos)                            /*!< PORT6 PDR0: PD2 Mask                */\r
-#define PORT6_PDR0_PD3_Pos                                    12                                                        /*!< PORT6 PDR0: PD3 Position            */\r
-#define PORT6_PDR0_PD3_Msk                                    (0x07UL << PORT6_PDR0_PD3_Pos)                            /*!< PORT6 PDR0: PD3 Mask                */\r
-#define PORT6_PDR0_PD4_Pos                                    16                                                        /*!< PORT6 PDR0: PD4 Position            */\r
-#define PORT6_PDR0_PD4_Msk                                    (0x07UL << PORT6_PDR0_PD4_Pos)                            /*!< PORT6 PDR0: PD4 Mask                */\r
-#define PORT6_PDR0_PD5_Pos                                    20                                                        /*!< PORT6 PDR0: PD5 Position            */\r
-#define PORT6_PDR0_PD5_Msk                                    (0x07UL << PORT6_PDR0_PD5_Pos)                            /*!< PORT6 PDR0: PD5 Mask                */\r
-#define PORT6_PDR0_PD6_Pos                                    24                                                        /*!< PORT6 PDR0: PD6 Position            */\r
-#define PORT6_PDR0_PD6_Msk                                    (0x07UL << PORT6_PDR0_PD6_Pos)                            /*!< PORT6 PDR0: PD6 Mask                */\r
-#define PORT6_PDR0_PD7_Pos                                    28                                                        /*!< PORT6 PDR0: PD7 Position            */\r
-#define PORT6_PDR0_PD7_Msk                                    (0x07UL << PORT6_PDR0_PD7_Pos)                            /*!< PORT6 PDR0: PD7 Mask                */\r
-\r
-// ---------------------------------------  PORT6_PDISC  ------------------------------------------\r
-#define PORT6_PDISC_PDIS0_Pos                                 0                                                         /*!< PORT6 PDISC: PDIS0 Position         */\r
-#define PORT6_PDISC_PDIS0_Msk                                 (0x01UL << PORT6_PDISC_PDIS0_Pos)                         /*!< PORT6 PDISC: PDIS0 Mask             */\r
-#define PORT6_PDISC_PDIS1_Pos                                 1                                                         /*!< PORT6 PDISC: PDIS1 Position         */\r
-#define PORT6_PDISC_PDIS1_Msk                                 (0x01UL << PORT6_PDISC_PDIS1_Pos)                         /*!< PORT6 PDISC: PDIS1 Mask             */\r
-#define PORT6_PDISC_PDIS2_Pos                                 2                                                         /*!< PORT6 PDISC: PDIS2 Position         */\r
-#define PORT6_PDISC_PDIS2_Msk                                 (0x01UL << PORT6_PDISC_PDIS2_Pos)                         /*!< PORT6 PDISC: PDIS2 Mask             */\r
-#define PORT6_PDISC_PDIS3_Pos                                 3                                                         /*!< PORT6 PDISC: PDIS3 Position         */\r
-#define PORT6_PDISC_PDIS3_Msk                                 (0x01UL << PORT6_PDISC_PDIS3_Pos)                         /*!< PORT6 PDISC: PDIS3 Mask             */\r
-#define PORT6_PDISC_PDIS4_Pos                                 4                                                         /*!< PORT6 PDISC: PDIS4 Position         */\r
-#define PORT6_PDISC_PDIS4_Msk                                 (0x01UL << PORT6_PDISC_PDIS4_Pos)                         /*!< PORT6 PDISC: PDIS4 Mask             */\r
-#define PORT6_PDISC_PDIS5_Pos                                 5                                                         /*!< PORT6 PDISC: PDIS5 Position         */\r
-#define PORT6_PDISC_PDIS5_Msk                                 (0x01UL << PORT6_PDISC_PDIS5_Pos)                         /*!< PORT6 PDISC: PDIS5 Mask             */\r
-#define PORT6_PDISC_PDIS6_Pos                                 6                                                         /*!< PORT6 PDISC: PDIS6 Position         */\r
-#define PORT6_PDISC_PDIS6_Msk                                 (0x01UL << PORT6_PDISC_PDIS6_Pos)                         /*!< PORT6 PDISC: PDIS6 Mask             */\r
-#define PORT6_PDISC_PDIS7_Pos                                 7                                                         /*!< PORT6 PDISC: PDIS7 Position         */\r
-#define PORT6_PDISC_PDIS7_Msk                                 (0x01UL << PORT6_PDISC_PDIS7_Pos)                         /*!< PORT6 PDISC: PDIS7 Mask             */\r
-#define PORT6_PDISC_PDIS8_Pos                                 8                                                         /*!< PORT6 PDISC: PDIS8 Position         */\r
-#define PORT6_PDISC_PDIS8_Msk                                 (0x01UL << PORT6_PDISC_PDIS8_Pos)                         /*!< PORT6 PDISC: PDIS8 Mask             */\r
-#define PORT6_PDISC_PDIS9_Pos                                 9                                                         /*!< PORT6 PDISC: PDIS9 Position         */\r
-#define PORT6_PDISC_PDIS9_Msk                                 (0x01UL << PORT6_PDISC_PDIS9_Pos)                         /*!< PORT6 PDISC: PDIS9 Mask             */\r
-#define PORT6_PDISC_PDIS10_Pos                                10                                                        /*!< PORT6 PDISC: PDIS10 Position        */\r
-#define PORT6_PDISC_PDIS10_Msk                                (0x01UL << PORT6_PDISC_PDIS10_Pos)                        /*!< PORT6 PDISC: PDIS10 Mask            */\r
-#define PORT6_PDISC_PDIS11_Pos                                11                                                        /*!< PORT6 PDISC: PDIS11 Position        */\r
-#define PORT6_PDISC_PDIS11_Msk                                (0x01UL << PORT6_PDISC_PDIS11_Pos)                        /*!< PORT6 PDISC: PDIS11 Mask            */\r
-#define PORT6_PDISC_PDIS12_Pos                                12                                                        /*!< PORT6 PDISC: PDIS12 Position        */\r
-#define PORT6_PDISC_PDIS12_Msk                                (0x01UL << PORT6_PDISC_PDIS12_Pos)                        /*!< PORT6 PDISC: PDIS12 Mask            */\r
-#define PORT6_PDISC_PDIS13_Pos                                13                                                        /*!< PORT6 PDISC: PDIS13 Position        */\r
-#define PORT6_PDISC_PDIS13_Msk                                (0x01UL << PORT6_PDISC_PDIS13_Pos)                        /*!< PORT6 PDISC: PDIS13 Mask            */\r
-#define PORT6_PDISC_PDIS14_Pos                                14                                                        /*!< PORT6 PDISC: PDIS14 Position        */\r
-#define PORT6_PDISC_PDIS14_Msk                                (0x01UL << PORT6_PDISC_PDIS14_Pos)                        /*!< PORT6 PDISC: PDIS14 Mask            */\r
-#define PORT6_PDISC_PDIS15_Pos                                15                                                        /*!< PORT6 PDISC: PDIS15 Position        */\r
-#define PORT6_PDISC_PDIS15_Msk                                (0x01UL << PORT6_PDISC_PDIS15_Pos)                        /*!< PORT6 PDISC: PDIS15 Mask            */\r
-\r
-// ----------------------------------------  PORT6_PPS  -------------------------------------------\r
-#define PORT6_PPS_PPS0_Pos                                    0                                                         /*!< PORT6 PPS: PPS0 Position            */\r
-#define PORT6_PPS_PPS0_Msk                                    (0x01UL << PORT6_PPS_PPS0_Pos)                            /*!< PORT6 PPS: PPS0 Mask                */\r
-#define PORT6_PPS_PPS1_Pos                                    1                                                         /*!< PORT6 PPS: PPS1 Position            */\r
-#define PORT6_PPS_PPS1_Msk                                    (0x01UL << PORT6_PPS_PPS1_Pos)                            /*!< PORT6 PPS: PPS1 Mask                */\r
-#define PORT6_PPS_PPS2_Pos                                    2                                                         /*!< PORT6 PPS: PPS2 Position            */\r
-#define PORT6_PPS_PPS2_Msk                                    (0x01UL << PORT6_PPS_PPS2_Pos)                            /*!< PORT6 PPS: PPS2 Mask                */\r
-#define PORT6_PPS_PPS3_Pos                                    3                                                         /*!< PORT6 PPS: PPS3 Position            */\r
-#define PORT6_PPS_PPS3_Msk                                    (0x01UL << PORT6_PPS_PPS3_Pos)                            /*!< PORT6 PPS: PPS3 Mask                */\r
-#define PORT6_PPS_PPS4_Pos                                    4                                                         /*!< PORT6 PPS: PPS4 Position            */\r
-#define PORT6_PPS_PPS4_Msk                                    (0x01UL << PORT6_PPS_PPS4_Pos)                            /*!< PORT6 PPS: PPS4 Mask                */\r
-#define PORT6_PPS_PPS5_Pos                                    5                                                         /*!< PORT6 PPS: PPS5 Position            */\r
-#define PORT6_PPS_PPS5_Msk                                    (0x01UL << PORT6_PPS_PPS5_Pos)                            /*!< PORT6 PPS: PPS5 Mask                */\r
-#define PORT6_PPS_PPS6_Pos                                    6                                                         /*!< PORT6 PPS: PPS6 Position            */\r
-#define PORT6_PPS_PPS6_Msk                                    (0x01UL << PORT6_PPS_PPS6_Pos)                            /*!< PORT6 PPS: PPS6 Mask                */\r
-#define PORT6_PPS_PPS7_Pos                                    7                                                         /*!< PORT6 PPS: PPS7 Position            */\r
-#define PORT6_PPS_PPS7_Msk                                    (0x01UL << PORT6_PPS_PPS7_Pos)                            /*!< PORT6 PPS: PPS7 Mask                */\r
-#define PORT6_PPS_PPS8_Pos                                    8                                                         /*!< PORT6 PPS: PPS8 Position            */\r
-#define PORT6_PPS_PPS8_Msk                                    (0x01UL << PORT6_PPS_PPS8_Pos)                            /*!< PORT6 PPS: PPS8 Mask                */\r
-#define PORT6_PPS_PPS9_Pos                                    9                                                         /*!< PORT6 PPS: PPS9 Position            */\r
-#define PORT6_PPS_PPS9_Msk                                    (0x01UL << PORT6_PPS_PPS9_Pos)                            /*!< PORT6 PPS: PPS9 Mask                */\r
-#define PORT6_PPS_PPS10_Pos                                   10                                                        /*!< PORT6 PPS: PPS10 Position           */\r
-#define PORT6_PPS_PPS10_Msk                                   (0x01UL << PORT6_PPS_PPS10_Pos)                           /*!< PORT6 PPS: PPS10 Mask               */\r
-#define PORT6_PPS_PPS11_Pos                                   11                                                        /*!< PORT6 PPS: PPS11 Position           */\r
-#define PORT6_PPS_PPS11_Msk                                   (0x01UL << PORT6_PPS_PPS11_Pos)                           /*!< PORT6 PPS: PPS11 Mask               */\r
-#define PORT6_PPS_PPS12_Pos                                   12                                                        /*!< PORT6 PPS: PPS12 Position           */\r
-#define PORT6_PPS_PPS12_Msk                                   (0x01UL << PORT6_PPS_PPS12_Pos)                           /*!< PORT6 PPS: PPS12 Mask               */\r
-#define PORT6_PPS_PPS13_Pos                                   13                                                        /*!< PORT6 PPS: PPS13 Position           */\r
-#define PORT6_PPS_PPS13_Msk                                   (0x01UL << PORT6_PPS_PPS13_Pos)                           /*!< PORT6 PPS: PPS13 Mask               */\r
-#define PORT6_PPS_PPS14_Pos                                   14                                                        /*!< PORT6 PPS: PPS14 Position           */\r
-#define PORT6_PPS_PPS14_Msk                                   (0x01UL << PORT6_PPS_PPS14_Pos)                           /*!< PORT6 PPS: PPS14 Mask               */\r
-#define PORT6_PPS_PPS15_Pos                                   15                                                        /*!< PORT6 PPS: PPS15 Position           */\r
-#define PORT6_PPS_PPS15_Msk                                   (0x01UL << PORT6_PPS_PPS15_Pos)                           /*!< PORT6 PPS: PPS15 Mask               */\r
-\r
-// ---------------------------------------  PORT6_HWSEL  ------------------------------------------\r
-#define PORT6_HWSEL_HW0_Pos                                   0                                                         /*!< PORT6 HWSEL: HW0 Position           */\r
-#define PORT6_HWSEL_HW0_Msk                                   (0x03UL << PORT6_HWSEL_HW0_Pos)                           /*!< PORT6 HWSEL: HW0 Mask               */\r
-#define PORT6_HWSEL_HW1_Pos                                   2                                                         /*!< PORT6 HWSEL: HW1 Position           */\r
-#define PORT6_HWSEL_HW1_Msk                                   (0x03UL << PORT6_HWSEL_HW1_Pos)                           /*!< PORT6 HWSEL: HW1 Mask               */\r
-#define PORT6_HWSEL_HW2_Pos                                   4                                                         /*!< PORT6 HWSEL: HW2 Position           */\r
-#define PORT6_HWSEL_HW2_Msk                                   (0x03UL << PORT6_HWSEL_HW2_Pos)                           /*!< PORT6 HWSEL: HW2 Mask               */\r
-#define PORT6_HWSEL_HW3_Pos                                   6                                                         /*!< PORT6 HWSEL: HW3 Position           */\r
-#define PORT6_HWSEL_HW3_Msk                                   (0x03UL << PORT6_HWSEL_HW3_Pos)                           /*!< PORT6 HWSEL: HW3 Mask               */\r
-#define PORT6_HWSEL_HW4_Pos                                   8                                                         /*!< PORT6 HWSEL: HW4 Position           */\r
-#define PORT6_HWSEL_HW4_Msk                                   (0x03UL << PORT6_HWSEL_HW4_Pos)                           /*!< PORT6 HWSEL: HW4 Mask               */\r
-#define PORT6_HWSEL_HW5_Pos                                   10                                                        /*!< PORT6 HWSEL: HW5 Position           */\r
-#define PORT6_HWSEL_HW5_Msk                                   (0x03UL << PORT6_HWSEL_HW5_Pos)                           /*!< PORT6 HWSEL: HW5 Mask               */\r
-#define PORT6_HWSEL_HW6_Pos                                   12                                                        /*!< PORT6 HWSEL: HW6 Position           */\r
-#define PORT6_HWSEL_HW6_Msk                                   (0x03UL << PORT6_HWSEL_HW6_Pos)                           /*!< PORT6 HWSEL: HW6 Mask               */\r
-#define PORT6_HWSEL_HW7_Pos                                   14                                                        /*!< PORT6 HWSEL: HW7 Position           */\r
-#define PORT6_HWSEL_HW7_Msk                                   (0x03UL << PORT6_HWSEL_HW7_Pos)                           /*!< PORT6 HWSEL: HW7 Mask               */\r
-#define PORT6_HWSEL_HW8_Pos                                   16                                                        /*!< PORT6 HWSEL: HW8 Position           */\r
-#define PORT6_HWSEL_HW8_Msk                                   (0x03UL << PORT6_HWSEL_HW8_Pos)                           /*!< PORT6 HWSEL: HW8 Mask               */\r
-#define PORT6_HWSEL_HW9_Pos                                   18                                                        /*!< PORT6 HWSEL: HW9 Position           */\r
-#define PORT6_HWSEL_HW9_Msk                                   (0x03UL << PORT6_HWSEL_HW9_Pos)                           /*!< PORT6 HWSEL: HW9 Mask               */\r
-#define PORT6_HWSEL_HW10_Pos                                  20                                                        /*!< PORT6 HWSEL: HW10 Position          */\r
-#define PORT6_HWSEL_HW10_Msk                                  (0x03UL << PORT6_HWSEL_HW10_Pos)                          /*!< PORT6 HWSEL: HW10 Mask              */\r
-#define PORT6_HWSEL_HW11_Pos                                  22                                                        /*!< PORT6 HWSEL: HW11 Position          */\r
-#define PORT6_HWSEL_HW11_Msk                                  (0x03UL << PORT6_HWSEL_HW11_Pos)                          /*!< PORT6 HWSEL: HW11 Mask              */\r
-#define PORT6_HWSEL_HW12_Pos                                  24                                                        /*!< PORT6 HWSEL: HW12 Position          */\r
-#define PORT6_HWSEL_HW12_Msk                                  (0x03UL << PORT6_HWSEL_HW12_Pos)                          /*!< PORT6 HWSEL: HW12 Mask              */\r
-#define PORT6_HWSEL_HW13_Pos                                  26                                                        /*!< PORT6 HWSEL: HW13 Position          */\r
-#define PORT6_HWSEL_HW13_Msk                                  (0x03UL << PORT6_HWSEL_HW13_Pos)                          /*!< PORT6 HWSEL: HW13 Mask              */\r
-#define PORT6_HWSEL_HW14_Pos                                  28                                                        /*!< PORT6 HWSEL: HW14 Position          */\r
-#define PORT6_HWSEL_HW14_Msk                                  (0x03UL << PORT6_HWSEL_HW14_Pos)                          /*!< PORT6 HWSEL: HW14 Mask              */\r
-#define PORT6_HWSEL_HW15_Pos                                  30                                                        /*!< PORT6 HWSEL: HW15 Position          */\r
-#define PORT6_HWSEL_HW15_Msk                                  (0x03UL << PORT6_HWSEL_HW15_Pos)                          /*!< PORT6 HWSEL: HW15 Mask              */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                PORT14 Position & Mask                                -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------  PORT14_OUT  -------------------------------------------\r
-#define PORT14_OUT_P0_Pos                                     0                                                         /*!< PORT14 OUT: P0 Position             */\r
-#define PORT14_OUT_P0_Msk                                     (0x01UL << PORT14_OUT_P0_Pos)                             /*!< PORT14 OUT: P0 Mask                 */\r
-#define PORT14_OUT_P1_Pos                                     1                                                         /*!< PORT14 OUT: P1 Position             */\r
-#define PORT14_OUT_P1_Msk                                     (0x01UL << PORT14_OUT_P1_Pos)                             /*!< PORT14 OUT: P1 Mask                 */\r
-#define PORT14_OUT_P2_Pos                                     2                                                         /*!< PORT14 OUT: P2 Position             */\r
-#define PORT14_OUT_P2_Msk                                     (0x01UL << PORT14_OUT_P2_Pos)                             /*!< PORT14 OUT: P2 Mask                 */\r
-#define PORT14_OUT_P3_Pos                                     3                                                         /*!< PORT14 OUT: P3 Position             */\r
-#define PORT14_OUT_P3_Msk                                     (0x01UL << PORT14_OUT_P3_Pos)                             /*!< PORT14 OUT: P3 Mask                 */\r
-#define PORT14_OUT_P4_Pos                                     4                                                         /*!< PORT14 OUT: P4 Position             */\r
-#define PORT14_OUT_P4_Msk                                     (0x01UL << PORT14_OUT_P4_Pos)                             /*!< PORT14 OUT: P4 Mask                 */\r
-#define PORT14_OUT_P5_Pos                                     5                                                         /*!< PORT14 OUT: P5 Position             */\r
-#define PORT14_OUT_P5_Msk                                     (0x01UL << PORT14_OUT_P5_Pos)                             /*!< PORT14 OUT: P5 Mask                 */\r
-#define PORT14_OUT_P6_Pos                                     6                                                         /*!< PORT14 OUT: P6 Position             */\r
-#define PORT14_OUT_P6_Msk                                     (0x01UL << PORT14_OUT_P6_Pos)                             /*!< PORT14 OUT: P6 Mask                 */\r
-#define PORT14_OUT_P7_Pos                                     7                                                         /*!< PORT14 OUT: P7 Position             */\r
-#define PORT14_OUT_P7_Msk                                     (0x01UL << PORT14_OUT_P7_Pos)                             /*!< PORT14 OUT: P7 Mask                 */\r
-#define PORT14_OUT_P8_Pos                                     8                                                         /*!< PORT14 OUT: P8 Position             */\r
-#define PORT14_OUT_P8_Msk                                     (0x01UL << PORT14_OUT_P8_Pos)                             /*!< PORT14 OUT: P8 Mask                 */\r
-#define PORT14_OUT_P9_Pos                                     9                                                         /*!< PORT14 OUT: P9 Position             */\r
-#define PORT14_OUT_P9_Msk                                     (0x01UL << PORT14_OUT_P9_Pos)                             /*!< PORT14 OUT: P9 Mask                 */\r
-#define PORT14_OUT_P10_Pos                                    10                                                        /*!< PORT14 OUT: P10 Position            */\r
-#define PORT14_OUT_P10_Msk                                    (0x01UL << PORT14_OUT_P10_Pos)                            /*!< PORT14 OUT: P10 Mask                */\r
-#define PORT14_OUT_P11_Pos                                    11                                                        /*!< PORT14 OUT: P11 Position            */\r
-#define PORT14_OUT_P11_Msk                                    (0x01UL << PORT14_OUT_P11_Pos)                            /*!< PORT14 OUT: P11 Mask                */\r
-#define PORT14_OUT_P12_Pos                                    12                                                        /*!< PORT14 OUT: P12 Position            */\r
-#define PORT14_OUT_P12_Msk                                    (0x01UL << PORT14_OUT_P12_Pos)                            /*!< PORT14 OUT: P12 Mask                */\r
-#define PORT14_OUT_P13_Pos                                    13                                                        /*!< PORT14 OUT: P13 Position            */\r
-#define PORT14_OUT_P13_Msk                                    (0x01UL << PORT14_OUT_P13_Pos)                            /*!< PORT14 OUT: P13 Mask                */\r
-#define PORT14_OUT_P14_Pos                                    14                                                        /*!< PORT14 OUT: P14 Position            */\r
-#define PORT14_OUT_P14_Msk                                    (0x01UL << PORT14_OUT_P14_Pos)                            /*!< PORT14 OUT: P14 Mask                */\r
-#define PORT14_OUT_P15_Pos                                    15                                                        /*!< PORT14 OUT: P15 Position            */\r
-#define PORT14_OUT_P15_Msk                                    (0x01UL << PORT14_OUT_P15_Pos)                            /*!< PORT14 OUT: P15 Mask                */\r
-\r
-// ---------------------------------------  PORT14_OMR  -------------------------------------------\r
-#define PORT14_OMR_PS0_Pos                                    0                                                         /*!< PORT14 OMR: PS0 Position            */\r
-#define PORT14_OMR_PS0_Msk                                    (0x01UL << PORT14_OMR_PS0_Pos)                            /*!< PORT14 OMR: PS0 Mask                */\r
-#define PORT14_OMR_PS1_Pos                                    1                                                         /*!< PORT14 OMR: PS1 Position            */\r
-#define PORT14_OMR_PS1_Msk                                    (0x01UL << PORT14_OMR_PS1_Pos)                            /*!< PORT14 OMR: PS1 Mask                */\r
-#define PORT14_OMR_PS2_Pos                                    2                                                         /*!< PORT14 OMR: PS2 Position            */\r
-#define PORT14_OMR_PS2_Msk                                    (0x01UL << PORT14_OMR_PS2_Pos)                            /*!< PORT14 OMR: PS2 Mask                */\r
-#define PORT14_OMR_PS3_Pos                                    3                                                         /*!< PORT14 OMR: PS3 Position            */\r
-#define PORT14_OMR_PS3_Msk                                    (0x01UL << PORT14_OMR_PS3_Pos)                            /*!< PORT14 OMR: PS3 Mask                */\r
-#define PORT14_OMR_PS4_Pos                                    4                                                         /*!< PORT14 OMR: PS4 Position            */\r
-#define PORT14_OMR_PS4_Msk                                    (0x01UL << PORT14_OMR_PS4_Pos)                            /*!< PORT14 OMR: PS4 Mask                */\r
-#define PORT14_OMR_PS5_Pos                                    5                                                         /*!< PORT14 OMR: PS5 Position            */\r
-#define PORT14_OMR_PS5_Msk                                    (0x01UL << PORT14_OMR_PS5_Pos)                            /*!< PORT14 OMR: PS5 Mask                */\r
-#define PORT14_OMR_PS6_Pos                                    6                                                         /*!< PORT14 OMR: PS6 Position            */\r
-#define PORT14_OMR_PS6_Msk                                    (0x01UL << PORT14_OMR_PS6_Pos)                            /*!< PORT14 OMR: PS6 Mask                */\r
-#define PORT14_OMR_PS7_Pos                                    7                                                         /*!< PORT14 OMR: PS7 Position            */\r
-#define PORT14_OMR_PS7_Msk                                    (0x01UL << PORT14_OMR_PS7_Pos)                            /*!< PORT14 OMR: PS7 Mask                */\r
-#define PORT14_OMR_PS8_Pos                                    8                                                         /*!< PORT14 OMR: PS8 Position            */\r
-#define PORT14_OMR_PS8_Msk                                    (0x01UL << PORT14_OMR_PS8_Pos)                            /*!< PORT14 OMR: PS8 Mask                */\r
-#define PORT14_OMR_PS9_Pos                                    9                                                         /*!< PORT14 OMR: PS9 Position            */\r
-#define PORT14_OMR_PS9_Msk                                    (0x01UL << PORT14_OMR_PS9_Pos)                            /*!< PORT14 OMR: PS9 Mask                */\r
-#define PORT14_OMR_PS10_Pos                                   10                                                        /*!< PORT14 OMR: PS10 Position           */\r
-#define PORT14_OMR_PS10_Msk                                   (0x01UL << PORT14_OMR_PS10_Pos)                           /*!< PORT14 OMR: PS10 Mask               */\r
-#define PORT14_OMR_PS11_Pos                                   11                                                        /*!< PORT14 OMR: PS11 Position           */\r
-#define PORT14_OMR_PS11_Msk                                   (0x01UL << PORT14_OMR_PS11_Pos)                           /*!< PORT14 OMR: PS11 Mask               */\r
-#define PORT14_OMR_PS12_Pos                                   12                                                        /*!< PORT14 OMR: PS12 Position           */\r
-#define PORT14_OMR_PS12_Msk                                   (0x01UL << PORT14_OMR_PS12_Pos)                           /*!< PORT14 OMR: PS12 Mask               */\r
-#define PORT14_OMR_PS13_Pos                                   13                                                        /*!< PORT14 OMR: PS13 Position           */\r
-#define PORT14_OMR_PS13_Msk                                   (0x01UL << PORT14_OMR_PS13_Pos)                           /*!< PORT14 OMR: PS13 Mask               */\r
-#define PORT14_OMR_PS14_Pos                                   14                                                        /*!< PORT14 OMR: PS14 Position           */\r
-#define PORT14_OMR_PS14_Msk                                   (0x01UL << PORT14_OMR_PS14_Pos)                           /*!< PORT14 OMR: PS14 Mask               */\r
-#define PORT14_OMR_PS15_Pos                                   15                                                        /*!< PORT14 OMR: PS15 Position           */\r
-#define PORT14_OMR_PS15_Msk                                   (0x01UL << PORT14_OMR_PS15_Pos)                           /*!< PORT14 OMR: PS15 Mask               */\r
-#define PORT14_OMR_PR0_Pos                                    16                                                        /*!< PORT14 OMR: PR0 Position            */\r
-#define PORT14_OMR_PR0_Msk                                    (0x01UL << PORT14_OMR_PR0_Pos)                            /*!< PORT14 OMR: PR0 Mask                */\r
-#define PORT14_OMR_PR1_Pos                                    17                                                        /*!< PORT14 OMR: PR1 Position            */\r
-#define PORT14_OMR_PR1_Msk                                    (0x01UL << PORT14_OMR_PR1_Pos)                            /*!< PORT14 OMR: PR1 Mask                */\r
-#define PORT14_OMR_PR2_Pos                                    18                                                        /*!< PORT14 OMR: PR2 Position            */\r
-#define PORT14_OMR_PR2_Msk                                    (0x01UL << PORT14_OMR_PR2_Pos)                            /*!< PORT14 OMR: PR2 Mask                */\r
-#define PORT14_OMR_PR3_Pos                                    19                                                        /*!< PORT14 OMR: PR3 Position            */\r
-#define PORT14_OMR_PR3_Msk                                    (0x01UL << PORT14_OMR_PR3_Pos)                            /*!< PORT14 OMR: PR3 Mask                */\r
-#define PORT14_OMR_PR4_Pos                                    20                                                        /*!< PORT14 OMR: PR4 Position            */\r
-#define PORT14_OMR_PR4_Msk                                    (0x01UL << PORT14_OMR_PR4_Pos)                            /*!< PORT14 OMR: PR4 Mask                */\r
-#define PORT14_OMR_PR5_Pos                                    21                                                        /*!< PORT14 OMR: PR5 Position            */\r
-#define PORT14_OMR_PR5_Msk                                    (0x01UL << PORT14_OMR_PR5_Pos)                            /*!< PORT14 OMR: PR5 Mask                */\r
-#define PORT14_OMR_PR6_Pos                                    22                                                        /*!< PORT14 OMR: PR6 Position            */\r
-#define PORT14_OMR_PR6_Msk                                    (0x01UL << PORT14_OMR_PR6_Pos)                            /*!< PORT14 OMR: PR6 Mask                */\r
-#define PORT14_OMR_PR7_Pos                                    23                                                        /*!< PORT14 OMR: PR7 Position            */\r
-#define PORT14_OMR_PR7_Msk                                    (0x01UL << PORT14_OMR_PR7_Pos)                            /*!< PORT14 OMR: PR7 Mask                */\r
-#define PORT14_OMR_PR8_Pos                                    24                                                        /*!< PORT14 OMR: PR8 Position            */\r
-#define PORT14_OMR_PR8_Msk                                    (0x01UL << PORT14_OMR_PR8_Pos)                            /*!< PORT14 OMR: PR8 Mask                */\r
-#define PORT14_OMR_PR9_Pos                                    25                                                        /*!< PORT14 OMR: PR9 Position            */\r
-#define PORT14_OMR_PR9_Msk                                    (0x01UL << PORT14_OMR_PR9_Pos)                            /*!< PORT14 OMR: PR9 Mask                */\r
-#define PORT14_OMR_PR10_Pos                                   26                                                        /*!< PORT14 OMR: PR10 Position           */\r
-#define PORT14_OMR_PR10_Msk                                   (0x01UL << PORT14_OMR_PR10_Pos)                           /*!< PORT14 OMR: PR10 Mask               */\r
-#define PORT14_OMR_PR11_Pos                                   27                                                        /*!< PORT14 OMR: PR11 Position           */\r
-#define PORT14_OMR_PR11_Msk                                   (0x01UL << PORT14_OMR_PR11_Pos)                           /*!< PORT14 OMR: PR11 Mask               */\r
-#define PORT14_OMR_PR12_Pos                                   28                                                        /*!< PORT14 OMR: PR12 Position           */\r
-#define PORT14_OMR_PR12_Msk                                   (0x01UL << PORT14_OMR_PR12_Pos)                           /*!< PORT14 OMR: PR12 Mask               */\r
-#define PORT14_OMR_PR13_Pos                                   29                                                        /*!< PORT14 OMR: PR13 Position           */\r
-#define PORT14_OMR_PR13_Msk                                   (0x01UL << PORT14_OMR_PR13_Pos)                           /*!< PORT14 OMR: PR13 Mask               */\r
-#define PORT14_OMR_PR14_Pos                                   30                                                        /*!< PORT14 OMR: PR14 Position           */\r
-#define PORT14_OMR_PR14_Msk                                   (0x01UL << PORT14_OMR_PR14_Pos)                           /*!< PORT14 OMR: PR14 Mask               */\r
-#define PORT14_OMR_PR15_Pos                                   31                                                        /*!< PORT14 OMR: PR15 Position           */\r
-#define PORT14_OMR_PR15_Msk                                   (0x01UL << PORT14_OMR_PR15_Pos)                           /*!< PORT14 OMR: PR15 Mask               */\r
-\r
-// --------------------------------------  PORT14_IOCR0  ------------------------------------------\r
-#define PORT14_IOCR0_PC0_Pos                                  3                                                         /*!< PORT14 IOCR0: PC0 Position          */\r
-#define PORT14_IOCR0_PC0_Msk                                  (0x1fUL << PORT14_IOCR0_PC0_Pos)                          /*!< PORT14 IOCR0: PC0 Mask              */\r
-#define PORT14_IOCR0_PC1_Pos                                  11                                                        /*!< PORT14 IOCR0: PC1 Position          */\r
-#define PORT14_IOCR0_PC1_Msk                                  (0x1fUL << PORT14_IOCR0_PC1_Pos)                          /*!< PORT14 IOCR0: PC1 Mask              */\r
-#define PORT14_IOCR0_PC2_Pos                                  19                                                        /*!< PORT14 IOCR0: PC2 Position          */\r
-#define PORT14_IOCR0_PC2_Msk                                  (0x1fUL << PORT14_IOCR0_PC2_Pos)                          /*!< PORT14 IOCR0: PC2 Mask              */\r
-#define PORT14_IOCR0_PC3_Pos                                  27                                                        /*!< PORT14 IOCR0: PC3 Position          */\r
-#define PORT14_IOCR0_PC3_Msk                                  (0x1fUL << PORT14_IOCR0_PC3_Pos)                          /*!< PORT14 IOCR0: PC3 Mask              */\r
-\r
-// --------------------------------------  PORT14_IOCR4  ------------------------------------------\r
-#define PORT14_IOCR4_PC4_Pos                                  3                                                         /*!< PORT14 IOCR4: PC4 Position          */\r
-#define PORT14_IOCR4_PC4_Msk                                  (0x1fUL << PORT14_IOCR4_PC4_Pos)                          /*!< PORT14 IOCR4: PC4 Mask              */\r
-#define PORT14_IOCR4_PC5_Pos                                  11                                                        /*!< PORT14 IOCR4: PC5 Position          */\r
-#define PORT14_IOCR4_PC5_Msk                                  (0x1fUL << PORT14_IOCR4_PC5_Pos)                          /*!< PORT14 IOCR4: PC5 Mask              */\r
-#define PORT14_IOCR4_PC6_Pos                                  19                                                        /*!< PORT14 IOCR4: PC6 Position          */\r
-#define PORT14_IOCR4_PC6_Msk                                  (0x1fUL << PORT14_IOCR4_PC6_Pos)                          /*!< PORT14 IOCR4: PC6 Mask              */\r
-#define PORT14_IOCR4_PC7_Pos                                  27                                                        /*!< PORT14 IOCR4: PC7 Position          */\r
-#define PORT14_IOCR4_PC7_Msk                                  (0x1fUL << PORT14_IOCR4_PC7_Pos)                          /*!< PORT14 IOCR4: PC7 Mask              */\r
-\r
-// --------------------------------------  PORT14_IOCR8  ------------------------------------------\r
-#define PORT14_IOCR8_PC8_Pos                                  3                                                         /*!< PORT14 IOCR8: PC8 Position          */\r
-#define PORT14_IOCR8_PC8_Msk                                  (0x1fUL << PORT14_IOCR8_PC8_Pos)                          /*!< PORT14 IOCR8: PC8 Mask              */\r
-#define PORT14_IOCR8_PC9_Pos                                  11                                                        /*!< PORT14 IOCR8: PC9 Position          */\r
-#define PORT14_IOCR8_PC9_Msk                                  (0x1fUL << PORT14_IOCR8_PC9_Pos)                          /*!< PORT14 IOCR8: PC9 Mask              */\r
-#define PORT14_IOCR8_PC10_Pos                                 19                                                        /*!< PORT14 IOCR8: PC10 Position         */\r
-#define PORT14_IOCR8_PC10_Msk                                 (0x1fUL << PORT14_IOCR8_PC10_Pos)                         /*!< PORT14 IOCR8: PC10 Mask             */\r
-#define PORT14_IOCR8_PC11_Pos                                 27                                                        /*!< PORT14 IOCR8: PC11 Position         */\r
-#define PORT14_IOCR8_PC11_Msk                                 (0x1fUL << PORT14_IOCR8_PC11_Pos)                         /*!< PORT14 IOCR8: PC11 Mask             */\r
-\r
-// --------------------------------------  PORT14_IOCR12  -----------------------------------------\r
-#define PORT14_IOCR12_PC12_Pos                                3                                                         /*!< PORT14 IOCR12: PC12 Position        */\r
-#define PORT14_IOCR12_PC12_Msk                                (0x1fUL << PORT14_IOCR12_PC12_Pos)                        /*!< PORT14 IOCR12: PC12 Mask            */\r
-#define PORT14_IOCR12_PC13_Pos                                11                                                        /*!< PORT14 IOCR12: PC13 Position        */\r
-#define PORT14_IOCR12_PC13_Msk                                (0x1fUL << PORT14_IOCR12_PC13_Pos)                        /*!< PORT14 IOCR12: PC13 Mask            */\r
-#define PORT14_IOCR12_PC14_Pos                                19                                                        /*!< PORT14 IOCR12: PC14 Position        */\r
-#define PORT14_IOCR12_PC14_Msk                                (0x1fUL << PORT14_IOCR12_PC14_Pos)                        /*!< PORT14 IOCR12: PC14 Mask            */\r
-#define PORT14_IOCR12_PC15_Pos                                27                                                        /*!< PORT14 IOCR12: PC15 Position        */\r
-#define PORT14_IOCR12_PC15_Msk                                (0x1fUL << PORT14_IOCR12_PC15_Pos)                        /*!< PORT14 IOCR12: PC15 Mask            */\r
-\r
-// ----------------------------------------  PORT14_IN  -------------------------------------------\r
-#define PORT14_IN_P0_Pos                                      0                                                         /*!< PORT14 IN: P0 Position              */\r
-#define PORT14_IN_P0_Msk                                      (0x01UL << PORT14_IN_P0_Pos)                              /*!< PORT14 IN: P0 Mask                  */\r
-#define PORT14_IN_P1_Pos                                      1                                                         /*!< PORT14 IN: P1 Position              */\r
-#define PORT14_IN_P1_Msk                                      (0x01UL << PORT14_IN_P1_Pos)                              /*!< PORT14 IN: P1 Mask                  */\r
-#define PORT14_IN_P2_Pos                                      2                                                         /*!< PORT14 IN: P2 Position              */\r
-#define PORT14_IN_P2_Msk                                      (0x01UL << PORT14_IN_P2_Pos)                              /*!< PORT14 IN: P2 Mask                  */\r
-#define PORT14_IN_P3_Pos                                      3                                                         /*!< PORT14 IN: P3 Position              */\r
-#define PORT14_IN_P3_Msk                                      (0x01UL << PORT14_IN_P3_Pos)                              /*!< PORT14 IN: P3 Mask                  */\r
-#define PORT14_IN_P4_Pos                                      4                                                         /*!< PORT14 IN: P4 Position              */\r
-#define PORT14_IN_P4_Msk                                      (0x01UL << PORT14_IN_P4_Pos)                              /*!< PORT14 IN: P4 Mask                  */\r
-#define PORT14_IN_P5_Pos                                      5                                                         /*!< PORT14 IN: P5 Position              */\r
-#define PORT14_IN_P5_Msk                                      (0x01UL << PORT14_IN_P5_Pos)                              /*!< PORT14 IN: P5 Mask                  */\r
-#define PORT14_IN_P6_Pos                                      6                                                         /*!< PORT14 IN: P6 Position              */\r
-#define PORT14_IN_P6_Msk                                      (0x01UL << PORT14_IN_P6_Pos)                              /*!< PORT14 IN: P6 Mask                  */\r
-#define PORT14_IN_P7_Pos                                      7                                                         /*!< PORT14 IN: P7 Position              */\r
-#define PORT14_IN_P7_Msk                                      (0x01UL << PORT14_IN_P7_Pos)                              /*!< PORT14 IN: P7 Mask                  */\r
-#define PORT14_IN_P8_Pos                                      8                                                         /*!< PORT14 IN: P8 Position              */\r
-#define PORT14_IN_P8_Msk                                      (0x01UL << PORT14_IN_P8_Pos)                              /*!< PORT14 IN: P8 Mask                  */\r
-#define PORT14_IN_P9_Pos                                      9                                                         /*!< PORT14 IN: P9 Position              */\r
-#define PORT14_IN_P9_Msk                                      (0x01UL << PORT14_IN_P9_Pos)                              /*!< PORT14 IN: P9 Mask                  */\r
-#define PORT14_IN_P10_Pos                                     10                                                        /*!< PORT14 IN: P10 Position             */\r
-#define PORT14_IN_P10_Msk                                     (0x01UL << PORT14_IN_P10_Pos)                             /*!< PORT14 IN: P10 Mask                 */\r
-#define PORT14_IN_P11_Pos                                     11                                                        /*!< PORT14 IN: P11 Position             */\r
-#define PORT14_IN_P11_Msk                                     (0x01UL << PORT14_IN_P11_Pos)                             /*!< PORT14 IN: P11 Mask                 */\r
-#define PORT14_IN_P12_Pos                                     12                                                        /*!< PORT14 IN: P12 Position             */\r
-#define PORT14_IN_P12_Msk                                     (0x01UL << PORT14_IN_P12_Pos)                             /*!< PORT14 IN: P12 Mask                 */\r
-#define PORT14_IN_P13_Pos                                     13                                                        /*!< PORT14 IN: P13 Position             */\r
-#define PORT14_IN_P13_Msk                                     (0x01UL << PORT14_IN_P13_Pos)                             /*!< PORT14 IN: P13 Mask                 */\r
-#define PORT14_IN_P14_Pos                                     14                                                        /*!< PORT14 IN: P14 Position             */\r
-#define PORT14_IN_P14_Msk                                     (0x01UL << PORT14_IN_P14_Pos)                             /*!< PORT14 IN: P14 Mask                 */\r
-#define PORT14_IN_P15_Pos                                     15                                                        /*!< PORT14 IN: P15 Position             */\r
-#define PORT14_IN_P15_Msk                                     (0x01UL << PORT14_IN_P15_Pos)                             /*!< PORT14 IN: P15 Mask                 */\r
-\r
-// --------------------------------------  PORT14_PDISC  ------------------------------------------\r
-#define PORT14_PDISC_PDIS0_Pos                                0                                                         /*!< PORT14 PDISC: PDIS0 Position        */\r
-#define PORT14_PDISC_PDIS0_Msk                                (0x01UL << PORT14_PDISC_PDIS0_Pos)                        /*!< PORT14 PDISC: PDIS0 Mask            */\r
-#define PORT14_PDISC_PDIS1_Pos                                1                                                         /*!< PORT14 PDISC: PDIS1 Position        */\r
-#define PORT14_PDISC_PDIS1_Msk                                (0x01UL << PORT14_PDISC_PDIS1_Pos)                        /*!< PORT14 PDISC: PDIS1 Mask            */\r
-#define PORT14_PDISC_PDIS2_Pos                                2                                                         /*!< PORT14 PDISC: PDIS2 Position        */\r
-#define PORT14_PDISC_PDIS2_Msk                                (0x01UL << PORT14_PDISC_PDIS2_Pos)                        /*!< PORT14 PDISC: PDIS2 Mask            */\r
-#define PORT14_PDISC_PDIS3_Pos                                3                                                         /*!< PORT14 PDISC: PDIS3 Position        */\r
-#define PORT14_PDISC_PDIS3_Msk                                (0x01UL << PORT14_PDISC_PDIS3_Pos)                        /*!< PORT14 PDISC: PDIS3 Mask            */\r
-#define PORT14_PDISC_PDIS4_Pos                                4                                                         /*!< PORT14 PDISC: PDIS4 Position        */\r
-#define PORT14_PDISC_PDIS4_Msk                                (0x01UL << PORT14_PDISC_PDIS4_Pos)                        /*!< PORT14 PDISC: PDIS4 Mask            */\r
-#define PORT14_PDISC_PDIS5_Pos                                5                                                         /*!< PORT14 PDISC: PDIS5 Position        */\r
-#define PORT14_PDISC_PDIS5_Msk                                (0x01UL << PORT14_PDISC_PDIS5_Pos)                        /*!< PORT14 PDISC: PDIS5 Mask            */\r
-#define PORT14_PDISC_PDIS6_Pos                                6                                                         /*!< PORT14 PDISC: PDIS6 Position        */\r
-#define PORT14_PDISC_PDIS6_Msk                                (0x01UL << PORT14_PDISC_PDIS6_Pos)                        /*!< PORT14 PDISC: PDIS6 Mask            */\r
-#define PORT14_PDISC_PDIS7_Pos                                7                                                         /*!< PORT14 PDISC: PDIS7 Position        */\r
-#define PORT14_PDISC_PDIS7_Msk                                (0x01UL << PORT14_PDISC_PDIS7_Pos)                        /*!< PORT14 PDISC: PDIS7 Mask            */\r
-#define PORT14_PDISC_PDIS8_Pos                                8                                                         /*!< PORT14 PDISC: PDIS8 Position        */\r
-#define PORT14_PDISC_PDIS8_Msk                                (0x01UL << PORT14_PDISC_PDIS8_Pos)                        /*!< PORT14 PDISC: PDIS8 Mask            */\r
-#define PORT14_PDISC_PDIS9_Pos                                9                                                         /*!< PORT14 PDISC: PDIS9 Position        */\r
-#define PORT14_PDISC_PDIS9_Msk                                (0x01UL << PORT14_PDISC_PDIS9_Pos)                        /*!< PORT14 PDISC: PDIS9 Mask            */\r
-#define PORT14_PDISC_PDIS12_Pos                               12                                                        /*!< PORT14 PDISC: PDIS12 Position       */\r
-#define PORT14_PDISC_PDIS12_Msk                               (0x01UL << PORT14_PDISC_PDIS12_Pos)                       /*!< PORT14 PDISC: PDIS12 Mask           */\r
-#define PORT14_PDISC_PDIS13_Pos                               13                                                        /*!< PORT14 PDISC: PDIS13 Position       */\r
-#define PORT14_PDISC_PDIS13_Msk                               (0x01UL << PORT14_PDISC_PDIS13_Pos)                       /*!< PORT14 PDISC: PDIS13 Mask           */\r
-#define PORT14_PDISC_PDIS14_Pos                               14                                                        /*!< PORT14 PDISC: PDIS14 Position       */\r
-#define PORT14_PDISC_PDIS14_Msk                               (0x01UL << PORT14_PDISC_PDIS14_Pos)                       /*!< PORT14 PDISC: PDIS14 Mask           */\r
-#define PORT14_PDISC_PDIS15_Pos                               15                                                        /*!< PORT14 PDISC: PDIS15 Position       */\r
-#define PORT14_PDISC_PDIS15_Msk                               (0x01UL << PORT14_PDISC_PDIS15_Pos)                       /*!< PORT14 PDISC: PDIS15 Mask           */\r
-\r
-// ---------------------------------------  PORT14_PPS  -------------------------------------------\r
-#define PORT14_PPS_PPS0_Pos                                   0                                                         /*!< PORT14 PPS: PPS0 Position           */\r
-#define PORT14_PPS_PPS0_Msk                                   (0x01UL << PORT14_PPS_PPS0_Pos)                           /*!< PORT14 PPS: PPS0 Mask               */\r
-#define PORT14_PPS_PPS1_Pos                                   1                                                         /*!< PORT14 PPS: PPS1 Position           */\r
-#define PORT14_PPS_PPS1_Msk                                   (0x01UL << PORT14_PPS_PPS1_Pos)                           /*!< PORT14 PPS: PPS1 Mask               */\r
-#define PORT14_PPS_PPS2_Pos                                   2                                                         /*!< PORT14 PPS: PPS2 Position           */\r
-#define PORT14_PPS_PPS2_Msk                                   (0x01UL << PORT14_PPS_PPS2_Pos)                           /*!< PORT14 PPS: PPS2 Mask               */\r
-#define PORT14_PPS_PPS3_Pos                                   3                                                         /*!< PORT14 PPS: PPS3 Position           */\r
-#define PORT14_PPS_PPS3_Msk                                   (0x01UL << PORT14_PPS_PPS3_Pos)                           /*!< PORT14 PPS: PPS3 Mask               */\r
-#define PORT14_PPS_PPS4_Pos                                   4                                                         /*!< PORT14 PPS: PPS4 Position           */\r
-#define PORT14_PPS_PPS4_Msk                                   (0x01UL << PORT14_PPS_PPS4_Pos)                           /*!< PORT14 PPS: PPS4 Mask               */\r
-#define PORT14_PPS_PPS5_Pos                                   5                                                         /*!< PORT14 PPS: PPS5 Position           */\r
-#define PORT14_PPS_PPS5_Msk                                   (0x01UL << PORT14_PPS_PPS5_Pos)                           /*!< PORT14 PPS: PPS5 Mask               */\r
-#define PORT14_PPS_PPS6_Pos                                   6                                                         /*!< PORT14 PPS: PPS6 Position           */\r
-#define PORT14_PPS_PPS6_Msk                                   (0x01UL << PORT14_PPS_PPS6_Pos)                           /*!< PORT14 PPS: PPS6 Mask               */\r
-#define PORT14_PPS_PPS7_Pos                                   7                                                         /*!< PORT14 PPS: PPS7 Position           */\r
-#define PORT14_PPS_PPS7_Msk                                   (0x01UL << PORT14_PPS_PPS7_Pos)                           /*!< PORT14 PPS: PPS7 Mask               */\r
-#define PORT14_PPS_PPS8_Pos                                   8                                                         /*!< PORT14 PPS: PPS8 Position           */\r
-#define PORT14_PPS_PPS8_Msk                                   (0x01UL << PORT14_PPS_PPS8_Pos)                           /*!< PORT14 PPS: PPS8 Mask               */\r
-#define PORT14_PPS_PPS9_Pos                                   9                                                         /*!< PORT14 PPS: PPS9 Position           */\r
-#define PORT14_PPS_PPS9_Msk                                   (0x01UL << PORT14_PPS_PPS9_Pos)                           /*!< PORT14 PPS: PPS9 Mask               */\r
-#define PORT14_PPS_PPS10_Pos                                  10                                                        /*!< PORT14 PPS: PPS10 Position          */\r
-#define PORT14_PPS_PPS10_Msk                                  (0x01UL << PORT14_PPS_PPS10_Pos)                          /*!< PORT14 PPS: PPS10 Mask              */\r
-#define PORT14_PPS_PPS11_Pos                                  11                                                        /*!< PORT14 PPS: PPS11 Position          */\r
-#define PORT14_PPS_PPS11_Msk                                  (0x01UL << PORT14_PPS_PPS11_Pos)                          /*!< PORT14 PPS: PPS11 Mask              */\r
-#define PORT14_PPS_PPS12_Pos                                  12                                                        /*!< PORT14 PPS: PPS12 Position          */\r
-#define PORT14_PPS_PPS12_Msk                                  (0x01UL << PORT14_PPS_PPS12_Pos)                          /*!< PORT14 PPS: PPS12 Mask              */\r
-#define PORT14_PPS_PPS13_Pos                                  13                                                        /*!< PORT14 PPS: PPS13 Position          */\r
-#define PORT14_PPS_PPS13_Msk                                  (0x01UL << PORT14_PPS_PPS13_Pos)                          /*!< PORT14 PPS: PPS13 Mask              */\r
-#define PORT14_PPS_PPS14_Pos                                  14                                                        /*!< PORT14 PPS: PPS14 Position          */\r
-#define PORT14_PPS_PPS14_Msk                                  (0x01UL << PORT14_PPS_PPS14_Pos)                          /*!< PORT14 PPS: PPS14 Mask              */\r
-#define PORT14_PPS_PPS15_Pos                                  15                                                        /*!< PORT14 PPS: PPS15 Position          */\r
-#define PORT14_PPS_PPS15_Msk                                  (0x01UL << PORT14_PPS_PPS15_Pos)                          /*!< PORT14 PPS: PPS15 Mask              */\r
-\r
-// --------------------------------------  PORT14_HWSEL  ------------------------------------------\r
-#define PORT14_HWSEL_HW0_Pos                                  0                                                         /*!< PORT14 HWSEL: HW0 Position          */\r
-#define PORT14_HWSEL_HW0_Msk                                  (0x03UL << PORT14_HWSEL_HW0_Pos)                          /*!< PORT14 HWSEL: HW0 Mask              */\r
-#define PORT14_HWSEL_HW1_Pos                                  2                                                         /*!< PORT14 HWSEL: HW1 Position          */\r
-#define PORT14_HWSEL_HW1_Msk                                  (0x03UL << PORT14_HWSEL_HW1_Pos)                          /*!< PORT14 HWSEL: HW1 Mask              */\r
-#define PORT14_HWSEL_HW2_Pos                                  4                                                         /*!< PORT14 HWSEL: HW2 Position          */\r
-#define PORT14_HWSEL_HW2_Msk                                  (0x03UL << PORT14_HWSEL_HW2_Pos)                          /*!< PORT14 HWSEL: HW2 Mask              */\r
-#define PORT14_HWSEL_HW3_Pos                                  6                                                         /*!< PORT14 HWSEL: HW3 Position          */\r
-#define PORT14_HWSEL_HW3_Msk                                  (0x03UL << PORT14_HWSEL_HW3_Pos)                          /*!< PORT14 HWSEL: HW3 Mask              */\r
-#define PORT14_HWSEL_HW4_Pos                                  8                                                         /*!< PORT14 HWSEL: HW4 Position          */\r
-#define PORT14_HWSEL_HW4_Msk                                  (0x03UL << PORT14_HWSEL_HW4_Pos)                          /*!< PORT14 HWSEL: HW4 Mask              */\r
-#define PORT14_HWSEL_HW5_Pos                                  10                                                        /*!< PORT14 HWSEL: HW5 Position          */\r
-#define PORT14_HWSEL_HW5_Msk                                  (0x03UL << PORT14_HWSEL_HW5_Pos)                          /*!< PORT14 HWSEL: HW5 Mask              */\r
-#define PORT14_HWSEL_HW6_Pos                                  12                                                        /*!< PORT14 HWSEL: HW6 Position          */\r
-#define PORT14_HWSEL_HW6_Msk                                  (0x03UL << PORT14_HWSEL_HW6_Pos)                          /*!< PORT14 HWSEL: HW6 Mask              */\r
-#define PORT14_HWSEL_HW7_Pos                                  14                                                        /*!< PORT14 HWSEL: HW7 Position          */\r
-#define PORT14_HWSEL_HW7_Msk                                  (0x03UL << PORT14_HWSEL_HW7_Pos)                          /*!< PORT14 HWSEL: HW7 Mask              */\r
-#define PORT14_HWSEL_HW8_Pos                                  16                                                        /*!< PORT14 HWSEL: HW8 Position          */\r
-#define PORT14_HWSEL_HW8_Msk                                  (0x03UL << PORT14_HWSEL_HW8_Pos)                          /*!< PORT14 HWSEL: HW8 Mask              */\r
-#define PORT14_HWSEL_HW9_Pos                                  18                                                        /*!< PORT14 HWSEL: HW9 Position          */\r
-#define PORT14_HWSEL_HW9_Msk                                  (0x03UL << PORT14_HWSEL_HW9_Pos)                          /*!< PORT14 HWSEL: HW9 Mask              */\r
-#define PORT14_HWSEL_HW10_Pos                                 20                                                        /*!< PORT14 HWSEL: HW10 Position         */\r
-#define PORT14_HWSEL_HW10_Msk                                 (0x03UL << PORT14_HWSEL_HW10_Pos)                         /*!< PORT14 HWSEL: HW10 Mask             */\r
-#define PORT14_HWSEL_HW11_Pos                                 22                                                        /*!< PORT14 HWSEL: HW11 Position         */\r
-#define PORT14_HWSEL_HW11_Msk                                 (0x03UL << PORT14_HWSEL_HW11_Pos)                         /*!< PORT14 HWSEL: HW11 Mask             */\r
-#define PORT14_HWSEL_HW12_Pos                                 24                                                        /*!< PORT14 HWSEL: HW12 Position         */\r
-#define PORT14_HWSEL_HW12_Msk                                 (0x03UL << PORT14_HWSEL_HW12_Pos)                         /*!< PORT14 HWSEL: HW12 Mask             */\r
-#define PORT14_HWSEL_HW13_Pos                                 26                                                        /*!< PORT14 HWSEL: HW13 Position         */\r
-#define PORT14_HWSEL_HW13_Msk                                 (0x03UL << PORT14_HWSEL_HW13_Pos)                         /*!< PORT14 HWSEL: HW13 Mask             */\r
-#define PORT14_HWSEL_HW14_Pos                                 28                                                        /*!< PORT14 HWSEL: HW14 Position         */\r
-#define PORT14_HWSEL_HW14_Msk                                 (0x03UL << PORT14_HWSEL_HW14_Pos)                         /*!< PORT14 HWSEL: HW14 Mask             */\r
-#define PORT14_HWSEL_HW15_Pos                                 30                                                        /*!< PORT14 HWSEL: HW15 Position         */\r
-#define PORT14_HWSEL_HW15_Msk                                 (0x03UL << PORT14_HWSEL_HW15_Pos)                         /*!< PORT14 HWSEL: HW15 Mask             */\r
-\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                PORT15 Position & Mask                                -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-\r
-// ---------------------------------------  PORT15_OUT  -------------------------------------------\r
-#define PORT15_OUT_P0_Pos                                     0                                                         /*!< PORT15 OUT: P0 Position             */\r
-#define PORT15_OUT_P0_Msk                                     (0x01UL << PORT15_OUT_P0_Pos)                             /*!< PORT15 OUT: P0 Mask                 */\r
-#define PORT15_OUT_P1_Pos                                     1                                                         /*!< PORT15 OUT: P1 Position             */\r
-#define PORT15_OUT_P1_Msk                                     (0x01UL << PORT15_OUT_P1_Pos)                             /*!< PORT15 OUT: P1 Mask                 */\r
-#define PORT15_OUT_P2_Pos                                     2                                                         /*!< PORT15 OUT: P2 Position             */\r
-#define PORT15_OUT_P2_Msk                                     (0x01UL << PORT15_OUT_P2_Pos)                             /*!< PORT15 OUT: P2 Mask                 */\r
-#define PORT15_OUT_P3_Pos                                     3                                                         /*!< PORT15 OUT: P3 Position             */\r
-#define PORT15_OUT_P3_Msk                                     (0x01UL << PORT15_OUT_P3_Pos)                             /*!< PORT15 OUT: P3 Mask                 */\r
-#define PORT15_OUT_P4_Pos                                     4                                                         /*!< PORT15 OUT: P4 Position             */\r
-#define PORT15_OUT_P4_Msk                                     (0x01UL << PORT15_OUT_P4_Pos)                             /*!< PORT15 OUT: P4 Mask                 */\r
-#define PORT15_OUT_P5_Pos                                     5                                                         /*!< PORT15 OUT: P5 Position             */\r
-#define PORT15_OUT_P5_Msk                                     (0x01UL << PORT15_OUT_P5_Pos)                             /*!< PORT15 OUT: P5 Mask                 */\r
-#define PORT15_OUT_P6_Pos                                     6                                                         /*!< PORT15 OUT: P6 Position             */\r
-#define PORT15_OUT_P6_Msk                                     (0x01UL << PORT15_OUT_P6_Pos)                             /*!< PORT15 OUT: P6 Mask                 */\r
-#define PORT15_OUT_P7_Pos                                     7                                                         /*!< PORT15 OUT: P7 Position             */\r
-#define PORT15_OUT_P7_Msk                                     (0x01UL << PORT15_OUT_P7_Pos)                             /*!< PORT15 OUT: P7 Mask                 */\r
-#define PORT15_OUT_P8_Pos                                     8                                                         /*!< PORT15 OUT: P8 Position             */\r
-#define PORT15_OUT_P8_Msk                                     (0x01UL << PORT15_OUT_P8_Pos)                             /*!< PORT15 OUT: P8 Mask                 */\r
-#define PORT15_OUT_P9_Pos                                     9                                                         /*!< PORT15 OUT: P9 Position             */\r
-#define PORT15_OUT_P9_Msk                                     (0x01UL << PORT15_OUT_P9_Pos)                             /*!< PORT15 OUT: P9 Mask                 */\r
-#define PORT15_OUT_P10_Pos                                    10                                                        /*!< PORT15 OUT: P10 Position            */\r
-#define PORT15_OUT_P10_Msk                                    (0x01UL << PORT15_OUT_P10_Pos)                            /*!< PORT15 OUT: P10 Mask                */\r
-#define PORT15_OUT_P11_Pos                                    11                                                        /*!< PORT15 OUT: P11 Position            */\r
-#define PORT15_OUT_P11_Msk                                    (0x01UL << PORT15_OUT_P11_Pos)                            /*!< PORT15 OUT: P11 Mask                */\r
-#define PORT15_OUT_P12_Pos                                    12                                                        /*!< PORT15 OUT: P12 Position            */\r
-#define PORT15_OUT_P12_Msk                                    (0x01UL << PORT15_OUT_P12_Pos)                            /*!< PORT15 OUT: P12 Mask                */\r
-#define PORT15_OUT_P13_Pos                                    13                                                        /*!< PORT15 OUT: P13 Position            */\r
-#define PORT15_OUT_P13_Msk                                    (0x01UL << PORT15_OUT_P13_Pos)                            /*!< PORT15 OUT: P13 Mask                */\r
-#define PORT15_OUT_P14_Pos                                    14                                                        /*!< PORT15 OUT: P14 Position            */\r
-#define PORT15_OUT_P14_Msk                                    (0x01UL << PORT15_OUT_P14_Pos)                            /*!< PORT15 OUT: P14 Mask                */\r
-#define PORT15_OUT_P15_Pos                                    15                                                        /*!< PORT15 OUT: P15 Position            */\r
-#define PORT15_OUT_P15_Msk                                    (0x01UL << PORT15_OUT_P15_Pos)                            /*!< PORT15 OUT: P15 Mask                */\r
-\r
-// ---------------------------------------  PORT15_OMR  -------------------------------------------\r
-#define PORT15_OMR_PS0_Pos                                    0                                                         /*!< PORT15 OMR: PS0 Position            */\r
-#define PORT15_OMR_PS0_Msk                                    (0x01UL << PORT15_OMR_PS0_Pos)                            /*!< PORT15 OMR: PS0 Mask                */\r
-#define PORT15_OMR_PS1_Pos                                    1                                                         /*!< PORT15 OMR: PS1 Position            */\r
-#define PORT15_OMR_PS1_Msk                                    (0x01UL << PORT15_OMR_PS1_Pos)                            /*!< PORT15 OMR: PS1 Mask                */\r
-#define PORT15_OMR_PS2_Pos                                    2                                                         /*!< PORT15 OMR: PS2 Position            */\r
-#define PORT15_OMR_PS2_Msk                                    (0x01UL << PORT15_OMR_PS2_Pos)                            /*!< PORT15 OMR: PS2 Mask                */\r
-#define PORT15_OMR_PS3_Pos                                    3                                                         /*!< PORT15 OMR: PS3 Position            */\r
-#define PORT15_OMR_PS3_Msk                                    (0x01UL << PORT15_OMR_PS3_Pos)                            /*!< PORT15 OMR: PS3 Mask                */\r
-#define PORT15_OMR_PS4_Pos                                    4                                                         /*!< PORT15 OMR: PS4 Position            */\r
-#define PORT15_OMR_PS4_Msk                                    (0x01UL << PORT15_OMR_PS4_Pos)                            /*!< PORT15 OMR: PS4 Mask                */\r
-#define PORT15_OMR_PS5_Pos                                    5                                                         /*!< PORT15 OMR: PS5 Position            */\r
-#define PORT15_OMR_PS5_Msk                                    (0x01UL << PORT15_OMR_PS5_Pos)                            /*!< PORT15 OMR: PS5 Mask                */\r
-#define PORT15_OMR_PS6_Pos                                    6                                                         /*!< PORT15 OMR: PS6 Position            */\r
-#define PORT15_OMR_PS6_Msk                                    (0x01UL << PORT15_OMR_PS6_Pos)                            /*!< PORT15 OMR: PS6 Mask                */\r
-#define PORT15_OMR_PS7_Pos                                    7                                                         /*!< PORT15 OMR: PS7 Position            */\r
-#define PORT15_OMR_PS7_Msk                                    (0x01UL << PORT15_OMR_PS7_Pos)                            /*!< PORT15 OMR: PS7 Mask                */\r
-#define PORT15_OMR_PS8_Pos                                    8                                                         /*!< PORT15 OMR: PS8 Position            */\r
-#define PORT15_OMR_PS8_Msk                                    (0x01UL << PORT15_OMR_PS8_Pos)                            /*!< PORT15 OMR: PS8 Mask                */\r
-#define PORT15_OMR_PS9_Pos                                    9                                                         /*!< PORT15 OMR: PS9 Position            */\r
-#define PORT15_OMR_PS9_Msk                                    (0x01UL << PORT15_OMR_PS9_Pos)                            /*!< PORT15 OMR: PS9 Mask                */\r
-#define PORT15_OMR_PS10_Pos                                   10                                                        /*!< PORT15 OMR: PS10 Position           */\r
-#define PORT15_OMR_PS10_Msk                                   (0x01UL << PORT15_OMR_PS10_Pos)                           /*!< PORT15 OMR: PS10 Mask               */\r
-#define PORT15_OMR_PS11_Pos                                   11                                                        /*!< PORT15 OMR: PS11 Position           */\r
-#define PORT15_OMR_PS11_Msk                                   (0x01UL << PORT15_OMR_PS11_Pos)                           /*!< PORT15 OMR: PS11 Mask               */\r
-#define PORT15_OMR_PS12_Pos                                   12                                                        /*!< PORT15 OMR: PS12 Position           */\r
-#define PORT15_OMR_PS12_Msk                                   (0x01UL << PORT15_OMR_PS12_Pos)                           /*!< PORT15 OMR: PS12 Mask               */\r
-#define PORT15_OMR_PS13_Pos                                   13                                                        /*!< PORT15 OMR: PS13 Position           */\r
-#define PORT15_OMR_PS13_Msk                                   (0x01UL << PORT15_OMR_PS13_Pos)                           /*!< PORT15 OMR: PS13 Mask               */\r
-#define PORT15_OMR_PS14_Pos                                   14                                                        /*!< PORT15 OMR: PS14 Position           */\r
-#define PORT15_OMR_PS14_Msk                                   (0x01UL << PORT15_OMR_PS14_Pos)                           /*!< PORT15 OMR: PS14 Mask               */\r
-#define PORT15_OMR_PS15_Pos                                   15                                                        /*!< PORT15 OMR: PS15 Position           */\r
-#define PORT15_OMR_PS15_Msk                                   (0x01UL << PORT15_OMR_PS15_Pos)                           /*!< PORT15 OMR: PS15 Mask               */\r
-#define PORT15_OMR_PR0_Pos                                    16                                                        /*!< PORT15 OMR: PR0 Position            */\r
-#define PORT15_OMR_PR0_Msk                                    (0x01UL << PORT15_OMR_PR0_Pos)                            /*!< PORT15 OMR: PR0 Mask                */\r
-#define PORT15_OMR_PR1_Pos                                    17                                                        /*!< PORT15 OMR: PR1 Position            */\r
-#define PORT15_OMR_PR1_Msk                                    (0x01UL << PORT15_OMR_PR1_Pos)                            /*!< PORT15 OMR: PR1 Mask                */\r
-#define PORT15_OMR_PR2_Pos                                    18                                                        /*!< PORT15 OMR: PR2 Position            */\r
-#define PORT15_OMR_PR2_Msk                                    (0x01UL << PORT15_OMR_PR2_Pos)                            /*!< PORT15 OMR: PR2 Mask                */\r
-#define PORT15_OMR_PR3_Pos                                    19                                                        /*!< PORT15 OMR: PR3 Position            */\r
-#define PORT15_OMR_PR3_Msk                                    (0x01UL << PORT15_OMR_PR3_Pos)                            /*!< PORT15 OMR: PR3 Mask                */\r
-#define PORT15_OMR_PR4_Pos                                    20                                                        /*!< PORT15 OMR: PR4 Position            */\r
-#define PORT15_OMR_PR4_Msk                                    (0x01UL << PORT15_OMR_PR4_Pos)                            /*!< PORT15 OMR: PR4 Mask                */\r
-#define PORT15_OMR_PR5_Pos                                    21                                                        /*!< PORT15 OMR: PR5 Position            */\r
-#define PORT15_OMR_PR5_Msk                                    (0x01UL << PORT15_OMR_PR5_Pos)                            /*!< PORT15 OMR: PR5 Mask                */\r
-#define PORT15_OMR_PR6_Pos                                    22                                                        /*!< PORT15 OMR: PR6 Position            */\r
-#define PORT15_OMR_PR6_Msk                                    (0x01UL << PORT15_OMR_PR6_Pos)                            /*!< PORT15 OMR: PR6 Mask                */\r
-#define PORT15_OMR_PR7_Pos                                    23                                                        /*!< PORT15 OMR: PR7 Position            */\r
-#define PORT15_OMR_PR7_Msk                                    (0x01UL << PORT15_OMR_PR7_Pos)                            /*!< PORT15 OMR: PR7 Mask                */\r
-#define PORT15_OMR_PR8_Pos                                    24                                                        /*!< PORT15 OMR: PR8 Position            */\r
-#define PORT15_OMR_PR8_Msk                                    (0x01UL << PORT15_OMR_PR8_Pos)                            /*!< PORT15 OMR: PR8 Mask                */\r
-#define PORT15_OMR_PR9_Pos                                    25                                                        /*!< PORT15 OMR: PR9 Position            */\r
-#define PORT15_OMR_PR9_Msk                                    (0x01UL << PORT15_OMR_PR9_Pos)                            /*!< PORT15 OMR: PR9 Mask                */\r
-#define PORT15_OMR_PR10_Pos                                   26                                                        /*!< PORT15 OMR: PR10 Position           */\r
-#define PORT15_OMR_PR10_Msk                                   (0x01UL << PORT15_OMR_PR10_Pos)                           /*!< PORT15 OMR: PR10 Mask               */\r
-#define PORT15_OMR_PR11_Pos                                   27                                                        /*!< PORT15 OMR: PR11 Position           */\r
-#define PORT15_OMR_PR11_Msk                                   (0x01UL << PORT15_OMR_PR11_Pos)                           /*!< PORT15 OMR: PR11 Mask               */\r
-#define PORT15_OMR_PR12_Pos                                   28                                                        /*!< PORT15 OMR: PR12 Position           */\r
-#define PORT15_OMR_PR12_Msk                                   (0x01UL << PORT15_OMR_PR12_Pos)                           /*!< PORT15 OMR: PR12 Mask               */\r
-#define PORT15_OMR_PR13_Pos                                   29                                                        /*!< PORT15 OMR: PR13 Position           */\r
-#define PORT15_OMR_PR13_Msk                                   (0x01UL << PORT15_OMR_PR13_Pos)                           /*!< PORT15 OMR: PR13 Mask               */\r
-#define PORT15_OMR_PR14_Pos                                   30                                                        /*!< PORT15 OMR: PR14 Position           */\r
-#define PORT15_OMR_PR14_Msk                                   (0x01UL << PORT15_OMR_PR14_Pos)                           /*!< PORT15 OMR: PR14 Mask               */\r
-#define PORT15_OMR_PR15_Pos                                   31                                                        /*!< PORT15 OMR: PR15 Position           */\r
-#define PORT15_OMR_PR15_Msk                                   (0x01UL << PORT15_OMR_PR15_Pos)                           /*!< PORT15 OMR: PR15 Mask               */\r
-\r
-// --------------------------------------  PORT15_IOCR0  ------------------------------------------\r
-#define PORT15_IOCR0_PC0_Pos                                  3                                                         /*!< PORT15 IOCR0: PC0 Position          */\r
-#define PORT15_IOCR0_PC0_Msk                                  (0x1fUL << PORT15_IOCR0_PC0_Pos)                          /*!< PORT15 IOCR0: PC0 Mask              */\r
-#define PORT15_IOCR0_PC1_Pos                                  11                                                        /*!< PORT15 IOCR0: PC1 Position          */\r
-#define PORT15_IOCR0_PC1_Msk                                  (0x1fUL << PORT15_IOCR0_PC1_Pos)                          /*!< PORT15 IOCR0: PC1 Mask              */\r
-#define PORT15_IOCR0_PC2_Pos                                  19                                                        /*!< PORT15 IOCR0: PC2 Position          */\r
-#define PORT15_IOCR0_PC2_Msk                                  (0x1fUL << PORT15_IOCR0_PC2_Pos)                          /*!< PORT15 IOCR0: PC2 Mask              */\r
-#define PORT15_IOCR0_PC3_Pos                                  27                                                        /*!< PORT15 IOCR0: PC3 Position          */\r
-#define PORT15_IOCR0_PC3_Msk                                  (0x1fUL << PORT15_IOCR0_PC3_Pos)                          /*!< PORT15 IOCR0: PC3 Mask              */\r
-\r
-// --------------------------------------  PORT15_IOCR4  ------------------------------------------\r
-#define PORT15_IOCR4_PC4_Pos                                  3                                                         /*!< PORT15 IOCR4: PC4 Position          */\r
-#define PORT15_IOCR4_PC4_Msk                                  (0x1fUL << PORT15_IOCR4_PC4_Pos)                          /*!< PORT15 IOCR4: PC4 Mask              */\r
-#define PORT15_IOCR4_PC5_Pos                                  11                                                        /*!< PORT15 IOCR4: PC5 Position          */\r
-#define PORT15_IOCR4_PC5_Msk                                  (0x1fUL << PORT15_IOCR4_PC5_Pos)                          /*!< PORT15 IOCR4: PC5 Mask              */\r
-#define PORT15_IOCR4_PC6_Pos                                  19                                                        /*!< PORT15 IOCR4: PC6 Position          */\r
-#define PORT15_IOCR4_PC6_Msk                                  (0x1fUL << PORT15_IOCR4_PC6_Pos)                          /*!< PORT15 IOCR4: PC6 Mask              */\r
-#define PORT15_IOCR4_PC7_Pos                                  27                                                        /*!< PORT15 IOCR4: PC7 Position          */\r
-#define PORT15_IOCR4_PC7_Msk                                  (0x1fUL << PORT15_IOCR4_PC7_Pos)                          /*!< PORT15 IOCR4: PC7 Mask              */\r
-\r
-// --------------------------------------  PORT15_IOCR8  ------------------------------------------\r
-#define PORT15_IOCR8_PC8_Pos                                  3                                                         /*!< PORT15 IOCR8: PC8 Position          */\r
-#define PORT15_IOCR8_PC8_Msk                                  (0x1fUL << PORT15_IOCR8_PC8_Pos)                          /*!< PORT15 IOCR8: PC8 Mask              */\r
-#define PORT15_IOCR8_PC9_Pos                                  11                                                        /*!< PORT15 IOCR8: PC9 Position          */\r
-#define PORT15_IOCR8_PC9_Msk                                  (0x1fUL << PORT15_IOCR8_PC9_Pos)                          /*!< PORT15 IOCR8: PC9 Mask              */\r
-#define PORT15_IOCR8_PC10_Pos                                 19                                                        /*!< PORT15 IOCR8: PC10 Position         */\r
-#define PORT15_IOCR8_PC10_Msk                                 (0x1fUL << PORT15_IOCR8_PC10_Pos)                         /*!< PORT15 IOCR8: PC10 Mask             */\r
-#define PORT15_IOCR8_PC11_Pos                                 27                                                        /*!< PORT15 IOCR8: PC11 Position         */\r
-#define PORT15_IOCR8_PC11_Msk                                 (0x1fUL << PORT15_IOCR8_PC11_Pos)                         /*!< PORT15 IOCR8: PC11 Mask             */\r
-\r
-// --------------------------------------  PORT15_IOCR12  -----------------------------------------\r
-#define PORT15_IOCR12_PC12_Pos                                3                                                         /*!< PORT15 IOCR12: PC12 Position        */\r
-#define PORT15_IOCR12_PC12_Msk                                (0x1fUL << PORT15_IOCR12_PC12_Pos)                        /*!< PORT15 IOCR12: PC12 Mask            */\r
-#define PORT15_IOCR12_PC13_Pos                                11                                                        /*!< PORT15 IOCR12: PC13 Position        */\r
-#define PORT15_IOCR12_PC13_Msk                                (0x1fUL << PORT15_IOCR12_PC13_Pos)                        /*!< PORT15 IOCR12: PC13 Mask            */\r
-#define PORT15_IOCR12_PC14_Pos                                19                                                        /*!< PORT15 IOCR12: PC14 Position        */\r
-#define PORT15_IOCR12_PC14_Msk                                (0x1fUL << PORT15_IOCR12_PC14_Pos)                        /*!< PORT15 IOCR12: PC14 Mask            */\r
-#define PORT15_IOCR12_PC15_Pos                                27                                                        /*!< PORT15 IOCR12: PC15 Position        */\r
-#define PORT15_IOCR12_PC15_Msk                                (0x1fUL << PORT15_IOCR12_PC15_Pos)                        /*!< PORT15 IOCR12: PC15 Mask            */\r
-\r
-// ----------------------------------------  PORT15_IN  -------------------------------------------\r
-#define PORT15_IN_P0_Pos                                      0                                                         /*!< PORT15 IN: P0 Position              */\r
-#define PORT15_IN_P0_Msk                                      (0x01UL << PORT15_IN_P0_Pos)                              /*!< PORT15 IN: P0 Mask                  */\r
-#define PORT15_IN_P1_Pos                                      1                                                         /*!< PORT15 IN: P1 Position              */\r
-#define PORT15_IN_P1_Msk                                      (0x01UL << PORT15_IN_P1_Pos)                              /*!< PORT15 IN: P1 Mask                  */\r
-#define PORT15_IN_P2_Pos                                      2                                                         /*!< PORT15 IN: P2 Position              */\r
-#define PORT15_IN_P2_Msk                                      (0x01UL << PORT15_IN_P2_Pos)                              /*!< PORT15 IN: P2 Mask                  */\r
-#define PORT15_IN_P3_Pos                                      3                                                         /*!< PORT15 IN: P3 Position              */\r
-#define PORT15_IN_P3_Msk                                      (0x01UL << PORT15_IN_P3_Pos)                              /*!< PORT15 IN: P3 Mask                  */\r
-#define PORT15_IN_P4_Pos                                      4                                                         /*!< PORT15 IN: P4 Position              */\r
-#define PORT15_IN_P4_Msk                                      (0x01UL << PORT15_IN_P4_Pos)                              /*!< PORT15 IN: P4 Mask                  */\r
-#define PORT15_IN_P5_Pos                                      5                                                         /*!< PORT15 IN: P5 Position              */\r
-#define PORT15_IN_P5_Msk                                      (0x01UL << PORT15_IN_P5_Pos)                              /*!< PORT15 IN: P5 Mask                  */\r
-#define PORT15_IN_P6_Pos                                      6                                                         /*!< PORT15 IN: P6 Position              */\r
-#define PORT15_IN_P6_Msk                                      (0x01UL << PORT15_IN_P6_Pos)                              /*!< PORT15 IN: P6 Mask                  */\r
-#define PORT15_IN_P7_Pos                                      7                                                         /*!< PORT15 IN: P7 Position              */\r
-#define PORT15_IN_P7_Msk                                      (0x01UL << PORT15_IN_P7_Pos)                              /*!< PORT15 IN: P7 Mask                  */\r
-#define PORT15_IN_P8_Pos                                      8                                                         /*!< PORT15 IN: P8 Position              */\r
-#define PORT15_IN_P8_Msk                                      (0x01UL << PORT15_IN_P8_Pos)                              /*!< PORT15 IN: P8 Mask                  */\r
-#define PORT15_IN_P9_Pos                                      9                                                         /*!< PORT15 IN: P9 Position              */\r
-#define PORT15_IN_P9_Msk                                      (0x01UL << PORT15_IN_P9_Pos)                              /*!< PORT15 IN: P9 Mask                  */\r
-#define PORT15_IN_P10_Pos                                     10                                                        /*!< PORT15 IN: P10 Position             */\r
-#define PORT15_IN_P10_Msk                                     (0x01UL << PORT15_IN_P10_Pos)                             /*!< PORT15 IN: P10 Mask                 */\r
-#define PORT15_IN_P11_Pos                                     11                                                        /*!< PORT15 IN: P11 Position             */\r
-#define PORT15_IN_P11_Msk                                     (0x01UL << PORT15_IN_P11_Pos)                             /*!< PORT15 IN: P11 Mask                 */\r
-#define PORT15_IN_P12_Pos                                     12                                                        /*!< PORT15 IN: P12 Position             */\r
-#define PORT15_IN_P12_Msk                                     (0x01UL << PORT15_IN_P12_Pos)                             /*!< PORT15 IN: P12 Mask                 */\r
-#define PORT15_IN_P13_Pos                                     13                                                        /*!< PORT15 IN: P13 Position             */\r
-#define PORT15_IN_P13_Msk                                     (0x01UL << PORT15_IN_P13_Pos)                             /*!< PORT15 IN: P13 Mask                 */\r
-#define PORT15_IN_P14_Pos                                     14                                                        /*!< PORT15 IN: P14 Position             */\r
-#define PORT15_IN_P14_Msk                                     (0x01UL << PORT15_IN_P14_Pos)                             /*!< PORT15 IN: P14 Mask                 */\r
-#define PORT15_IN_P15_Pos                                     15                                                        /*!< PORT15 IN: P15 Position             */\r
-#define PORT15_IN_P15_Msk                                     (0x01UL << PORT15_IN_P15_Pos)                             /*!< PORT15 IN: P15 Mask                 */\r
-\r
-// --------------------------------------  PORT15_PDISC  ------------------------------------------\r
-#define PORT15_PDISC_PDIS2_Pos                                2                                                         /*!< PORT15 PDISC: PDIS2 Position        */\r
-#define PORT15_PDISC_PDIS2_Msk                                (0x01UL << PORT15_PDISC_PDIS2_Pos)                        /*!< PORT15 PDISC: PDIS2 Mask            */\r
-#define PORT15_PDISC_PDIS3_Pos                                3                                                         /*!< PORT15 PDISC: PDIS3 Position        */\r
-#define PORT15_PDISC_PDIS3_Msk                                (0x01UL << PORT15_PDISC_PDIS3_Pos)                        /*!< PORT15 PDISC: PDIS3 Mask            */\r
-#define PORT15_PDISC_PDIS4_Pos                                4                                                         /*!< PORT15 PDISC: PDIS4 Position        */\r
-#define PORT15_PDISC_PDIS4_Msk                                (0x01UL << PORT15_PDISC_PDIS4_Pos)                        /*!< PORT15 PDISC: PDIS4 Mask            */\r
-#define PORT15_PDISC_PDIS5_Pos                                5                                                         /*!< PORT15 PDISC: PDIS5 Position        */\r
-#define PORT15_PDISC_PDIS5_Msk                                (0x01UL << PORT15_PDISC_PDIS5_Pos)                        /*!< PORT15 PDISC: PDIS5 Mask            */\r
-#define PORT15_PDISC_PDIS6_Pos                                6                                                         /*!< PORT15 PDISC: PDIS6 Position        */\r
-#define PORT15_PDISC_PDIS6_Msk                                (0x01UL << PORT15_PDISC_PDIS6_Pos)                        /*!< PORT15 PDISC: PDIS6 Mask            */\r
-#define PORT15_PDISC_PDIS7_Pos                                7                                                         /*!< PORT15 PDISC: PDIS7 Position        */\r
-#define PORT15_PDISC_PDIS7_Msk                                (0x01UL << PORT15_PDISC_PDIS7_Pos)                        /*!< PORT15 PDISC: PDIS7 Mask            */\r
-#define PORT15_PDISC_PDIS8_Pos                                8                                                         /*!< PORT15 PDISC: PDIS8 Position        */\r
-#define PORT15_PDISC_PDIS8_Msk                                (0x01UL << PORT15_PDISC_PDIS8_Pos)                        /*!< PORT15 PDISC: PDIS8 Mask            */\r
-#define PORT15_PDISC_PDIS9_Pos                                9                                                         /*!< PORT15 PDISC: PDIS9 Position        */\r
-#define PORT15_PDISC_PDIS9_Msk                                (0x01UL << PORT15_PDISC_PDIS9_Pos)                        /*!< PORT15 PDISC: PDIS9 Mask            */\r
-#define PORT15_PDISC_PDIS12_Pos                               12                                                        /*!< PORT15 PDISC: PDIS12 Position       */\r
-#define PORT15_PDISC_PDIS12_Msk                               (0x01UL << PORT15_PDISC_PDIS12_Pos)                       /*!< PORT15 PDISC: PDIS12 Mask           */\r
-#define PORT15_PDISC_PDIS13_Pos                               13                                                        /*!< PORT15 PDISC: PDIS13 Position       */\r
-#define PORT15_PDISC_PDIS13_Msk                               (0x01UL << PORT15_PDISC_PDIS13_Pos)                       /*!< PORT15 PDISC: PDIS13 Mask           */\r
-#define PORT15_PDISC_PDIS14_Pos                               14                                                        /*!< PORT15 PDISC: PDIS14 Position       */\r
-#define PORT15_PDISC_PDIS14_Msk                               (0x01UL << PORT15_PDISC_PDIS14_Pos)                       /*!< PORT15 PDISC: PDIS14 Mask           */\r
-#define PORT15_PDISC_PDIS15_Pos                               15                                                        /*!< PORT15 PDISC: PDIS15 Position       */\r
-#define PORT15_PDISC_PDIS15_Msk                               (0x01UL << PORT15_PDISC_PDIS15_Pos)                       /*!< PORT15 PDISC: PDIS15 Mask           */\r
-\r
-// ---------------------------------------  PORT15_PPS  -------------------------------------------\r
-#define PORT15_PPS_PPS0_Pos                                   0                                                         /*!< PORT15 PPS: PPS0 Position           */\r
-#define PORT15_PPS_PPS0_Msk                                   (0x01UL << PORT15_PPS_PPS0_Pos)                           /*!< PORT15 PPS: PPS0 Mask               */\r
-#define PORT15_PPS_PPS1_Pos                                   1                                                         /*!< PORT15 PPS: PPS1 Position           */\r
-#define PORT15_PPS_PPS1_Msk                                   (0x01UL << PORT15_PPS_PPS1_Pos)                           /*!< PORT15 PPS: PPS1 Mask               */\r
-#define PORT15_PPS_PPS2_Pos                                   2                                                         /*!< PORT15 PPS: PPS2 Position           */\r
-#define PORT15_PPS_PPS2_Msk                                   (0x01UL << PORT15_PPS_PPS2_Pos)                           /*!< PORT15 PPS: PPS2 Mask               */\r
-#define PORT15_PPS_PPS3_Pos                                   3                                                         /*!< PORT15 PPS: PPS3 Position           */\r
-#define PORT15_PPS_PPS3_Msk                                   (0x01UL << PORT15_PPS_PPS3_Pos)                           /*!< PORT15 PPS: PPS3 Mask               */\r
-#define PORT15_PPS_PPS4_Pos                                   4                                                         /*!< PORT15 PPS: PPS4 Position           */\r
-#define PORT15_PPS_PPS4_Msk                                   (0x01UL << PORT15_PPS_PPS4_Pos)                           /*!< PORT15 PPS: PPS4 Mask               */\r
-#define PORT15_PPS_PPS5_Pos                                   5                                                         /*!< PORT15 PPS: PPS5 Position           */\r
-#define PORT15_PPS_PPS5_Msk                                   (0x01UL << PORT15_PPS_PPS5_Pos)                           /*!< PORT15 PPS: PPS5 Mask               */\r
-#define PORT15_PPS_PPS6_Pos                                   6                                                         /*!< PORT15 PPS: PPS6 Position           */\r
-#define PORT15_PPS_PPS6_Msk                                   (0x01UL << PORT15_PPS_PPS6_Pos)                           /*!< PORT15 PPS: PPS6 Mask               */\r
-#define PORT15_PPS_PPS7_Pos                                   7                                                         /*!< PORT15 PPS: PPS7 Position           */\r
-#define PORT15_PPS_PPS7_Msk                                   (0x01UL << PORT15_PPS_PPS7_Pos)                           /*!< PORT15 PPS: PPS7 Mask               */\r
-#define PORT15_PPS_PPS8_Pos                                   8                                                         /*!< PORT15 PPS: PPS8 Position           */\r
-#define PORT15_PPS_PPS8_Msk                                   (0x01UL << PORT15_PPS_PPS8_Pos)                           /*!< PORT15 PPS: PPS8 Mask               */\r
-#define PORT15_PPS_PPS9_Pos                                   9                                                         /*!< PORT15 PPS: PPS9 Position           */\r
-#define PORT15_PPS_PPS9_Msk                                   (0x01UL << PORT15_PPS_PPS9_Pos)                           /*!< PORT15 PPS: PPS9 Mask               */\r
-#define PORT15_PPS_PPS10_Pos                                  10                                                        /*!< PORT15 PPS: PPS10 Position          */\r
-#define PORT15_PPS_PPS10_Msk                                  (0x01UL << PORT15_PPS_PPS10_Pos)                          /*!< PORT15 PPS: PPS10 Mask              */\r
-#define PORT15_PPS_PPS11_Pos                                  11                                                        /*!< PORT15 PPS: PPS11 Position          */\r
-#define PORT15_PPS_PPS11_Msk                                  (0x01UL << PORT15_PPS_PPS11_Pos)                          /*!< PORT15 PPS: PPS11 Mask              */\r
-#define PORT15_PPS_PPS12_Pos                                  12                                                        /*!< PORT15 PPS: PPS12 Position          */\r
-#define PORT15_PPS_PPS12_Msk                                  (0x01UL << PORT15_PPS_PPS12_Pos)                          /*!< PORT15 PPS: PPS12 Mask              */\r
-#define PORT15_PPS_PPS13_Pos                                  13                                                        /*!< PORT15 PPS: PPS13 Position          */\r
-#define PORT15_PPS_PPS13_Msk                                  (0x01UL << PORT15_PPS_PPS13_Pos)                          /*!< PORT15 PPS: PPS13 Mask              */\r
-#define PORT15_PPS_PPS14_Pos                                  14                                                        /*!< PORT15 PPS: PPS14 Position          */\r
-#define PORT15_PPS_PPS14_Msk                                  (0x01UL << PORT15_PPS_PPS14_Pos)                          /*!< PORT15 PPS: PPS14 Mask              */\r
-#define PORT15_PPS_PPS15_Pos                                  15                                                        /*!< PORT15 PPS: PPS15 Position          */\r
-#define PORT15_PPS_PPS15_Msk                                  (0x01UL << PORT15_PPS_PPS15_Pos)                          /*!< PORT15 PPS: PPS15 Mask              */\r
-\r
-// --------------------------------------  PORT15_HWSEL  ------------------------------------------\r
-#define PORT15_HWSEL_HW0_Pos                                  0                                                         /*!< PORT15 HWSEL: HW0 Position          */\r
-#define PORT15_HWSEL_HW0_Msk                                  (0x03UL << PORT15_HWSEL_HW0_Pos)                          /*!< PORT15 HWSEL: HW0 Mask              */\r
-#define PORT15_HWSEL_HW1_Pos                                  2                                                         /*!< PORT15 HWSEL: HW1 Position          */\r
-#define PORT15_HWSEL_HW1_Msk                                  (0x03UL << PORT15_HWSEL_HW1_Pos)                          /*!< PORT15 HWSEL: HW1 Mask              */\r
-#define PORT15_HWSEL_HW2_Pos                                  4                                                         /*!< PORT15 HWSEL: HW2 Position          */\r
-#define PORT15_HWSEL_HW2_Msk                                  (0x03UL << PORT15_HWSEL_HW2_Pos)                          /*!< PORT15 HWSEL: HW2 Mask              */\r
-#define PORT15_HWSEL_HW3_Pos                                  6                                                         /*!< PORT15 HWSEL: HW3 Position          */\r
-#define PORT15_HWSEL_HW3_Msk                                  (0x03UL << PORT15_HWSEL_HW3_Pos)                          /*!< PORT15 HWSEL: HW3 Mask              */\r
-#define PORT15_HWSEL_HW4_Pos                                  8                                                         /*!< PORT15 HWSEL: HW4 Position          */\r
-#define PORT15_HWSEL_HW4_Msk                                  (0x03UL << PORT15_HWSEL_HW4_Pos)                          /*!< PORT15 HWSEL: HW4 Mask              */\r
-#define PORT15_HWSEL_HW5_Pos                                  10                                                        /*!< PORT15 HWSEL: HW5 Position          */\r
-#define PORT15_HWSEL_HW5_Msk                                  (0x03UL << PORT15_HWSEL_HW5_Pos)                          /*!< PORT15 HWSEL: HW5 Mask              */\r
-#define PORT15_HWSEL_HW6_Pos                                  12                                                        /*!< PORT15 HWSEL: HW6 Position          */\r
-#define PORT15_HWSEL_HW6_Msk                                  (0x03UL << PORT15_HWSEL_HW6_Pos)                          /*!< PORT15 HWSEL: HW6 Mask              */\r
-#define PORT15_HWSEL_HW7_Pos                                  14                                                        /*!< PORT15 HWSEL: HW7 Position          */\r
-#define PORT15_HWSEL_HW7_Msk                                  (0x03UL << PORT15_HWSEL_HW7_Pos)                          /*!< PORT15 HWSEL: HW7 Mask              */\r
-#define PORT15_HWSEL_HW8_Pos                                  16                                                        /*!< PORT15 HWSEL: HW8 Position          */\r
-#define PORT15_HWSEL_HW8_Msk                                  (0x03UL << PORT15_HWSEL_HW8_Pos)                          /*!< PORT15 HWSEL: HW8 Mask              */\r
-#define PORT15_HWSEL_HW9_Pos                                  18                                                        /*!< PORT15 HWSEL: HW9 Position          */\r
-#define PORT15_HWSEL_HW9_Msk                                  (0x03UL << PORT15_HWSEL_HW9_Pos)                          /*!< PORT15 HWSEL: HW9 Mask              */\r
-#define PORT15_HWSEL_HW10_Pos                                 20                                                        /*!< PORT15 HWSEL: HW10 Position         */\r
-#define PORT15_HWSEL_HW10_Msk                                 (0x03UL << PORT15_HWSEL_HW10_Pos)                         /*!< PORT15 HWSEL: HW10 Mask             */\r
-#define PORT15_HWSEL_HW11_Pos                                 22                                                        /*!< PORT15 HWSEL: HW11 Position         */\r
-#define PORT15_HWSEL_HW11_Msk                                 (0x03UL << PORT15_HWSEL_HW11_Pos)                         /*!< PORT15 HWSEL: HW11 Mask             */\r
-#define PORT15_HWSEL_HW12_Pos                                 24                                                        /*!< PORT15 HWSEL: HW12 Position         */\r
-#define PORT15_HWSEL_HW12_Msk                                 (0x03UL << PORT15_HWSEL_HW12_Pos)                         /*!< PORT15 HWSEL: HW12 Mask             */\r
-#define PORT15_HWSEL_HW13_Pos                                 26                                                        /*!< PORT15 HWSEL: HW13 Position         */\r
-#define PORT15_HWSEL_HW13_Msk                                 (0x03UL << PORT15_HWSEL_HW13_Pos)                         /*!< PORT15 HWSEL: HW13 Mask             */\r
-#define PORT15_HWSEL_HW14_Pos                                 28                                                        /*!< PORT15 HWSEL: HW14 Position         */\r
-#define PORT15_HWSEL_HW14_Msk                                 (0x03UL << PORT15_HWSEL_HW14_Pos)                         /*!< PORT15 HWSEL: HW14 Mask             */\r
-#define PORT15_HWSEL_HW15_Pos                                 30                                                        /*!< PORT15 HWSEL: HW15 Position         */\r
-#define PORT15_HWSEL_HW15_Msk                                 (0x03UL << PORT15_HWSEL_HW15_Pos)                         /*!< PORT15 HWSEL: HW15 Mask             */\r
-\r
-\r
-/***   POSIFx Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* POSIF_PCONF  =  Architectural Overview configuration*/\r
-#define   POSIF_PCONF_FSEL_Pos         (0U)\r
-#define   POSIF_PCONF_FSEL_Msk         (0x00000003U  << POSIF_PCONF_FSEL_Pos)\r
-\r
-#define   POSIF_PCONF_QDCM_Pos         (2U)\r
-#define   POSIF_PCONF_QDCM_Msk         (0x00000001U  << POSIF_PCONF_QDCM_Pos)\r
-\r
-#define   POSIF_PCONF_HIDG_Pos         (4U)\r
-#define   POSIF_PCONF_HIDG_Msk         (0x00000001U  << POSIF_PCONF_HIDG_Pos)\r
-\r
-#define   POSIF_PCONF_MCUE_Pos         (5U)\r
-#define   POSIF_PCONF_MCUE_Msk         (0x00000001U  << POSIF_PCONF_MCUE_Pos)\r
-\r
-#define   POSIF_PCONF_INSEL0_Pos       (8U)\r
-#define   POSIF_PCONF_INSEL0_Msk       (0x00000003U  << POSIF_PCONF_INSEL0_Pos)\r
-\r
-#define   POSIF_PCONF_INSEL1_Pos       (10U)\r
-#define   POSIF_PCONF_INSEL1_Msk       (0x00000003U  << POSIF_PCONF_INSEL1_Pos)\r
-\r
-#define   POSIF_PCONF_INSEL2_Pos       (12U)\r
-#define   POSIF_PCONF_INSEL2_Msk       (0x00000003U  << POSIF_PCONF_INSEL2_Pos)\r
-\r
-#define   POSIF_PCONF_DSEL_Pos         (16U)\r
-#define   POSIF_PCONF_DSEL_Msk         (0x00000001U  << POSIF_PCONF_DSEL_Pos)\r
-\r
-#define   POSIF_PCONF_SPES_Pos         (17U)\r
-#define   POSIF_PCONF_SPES_Msk         (0x00000001U  << POSIF_PCONF_SPES_Pos)\r
-\r
-#define   POSIF_PCONF_MSETS_Pos        (18U)\r
-#define   POSIF_PCONF_MSETS_Msk        (0x00000007U  << POSIF_PCONF_MSETS_Pos)\r
-\r
-#define   POSIF_PCONF_MSES_Pos         (21U)\r
-#define   POSIF_PCONF_MSES_Msk         (0x00000001U  << POSIF_PCONF_MSES_Pos)\r
-\r
-#define   POSIF_PCONF_MSYNS_Pos        (22U)\r
-#define   POSIF_PCONF_MSYNS_Msk        (0x00000003U  << POSIF_PCONF_MSYNS_Pos)\r
-\r
-#define   POSIF_PCONF_EWIS_Pos         (24U)\r
-#define   POSIF_PCONF_EWIS_Msk         (0x00000003U  << POSIF_PCONF_EWIS_Pos)\r
-\r
-#define   POSIF_PCONF_EWIE_Pos         (26U)\r
-#define   POSIF_PCONF_EWIE_Msk         (0x00000001U  << POSIF_PCONF_EWIE_Pos)\r
-\r
-#define   POSIF_PCONF_EWIL_Pos         (27U)\r
-#define   POSIF_PCONF_EWIL_Msk         (0x00000001U  << POSIF_PCONF_EWIL_Pos)\r
-\r
-#define   POSIF_PCONF_LPC_Pos          (28U)\r
-#define   POSIF_PCONF_LPC_Msk          (0x00000007U  << POSIF_PCONF_LPC_Pos)\r
-\r
-/* POSIF_PSUS  =  Architectural Overview Suspend Config*/\r
-#define   POSIF_PSUS_QSUS_Pos          (0U)\r
-#define   POSIF_PSUS_QSUS_Msk          (0x00000003U  << POSIF_PSUS_QSUS_Pos)\r
-\r
-#define   POSIF_PSUS_MSUS_Pos          (2U)\r
-#define   POSIF_PSUS_MSUS_Msk          (0x00000003U  << POSIF_PSUS_MSUS_Pos)\r
-\r
-/* POSIF_PRUNS  =  Architectural Overview Run Bit Set*/\r
-#define   POSIF_PRUNS_SRB_Pos          (0U)\r
-#define   POSIF_PRUNS_SRB_Msk          (0x00000001U  << POSIF_PRUNS_SRB_Pos)\r
-\r
-/* POSIF_PRUNC  =  Architectural Overview Run Bit Clear*/\r
-#define   POSIF_PRUNC_CRB_Pos          (0U)\r
-#define   POSIF_PRUNC_CRB_Msk          (0x00000001U  << POSIF_PRUNC_CRB_Pos)\r
-\r
-#define   POSIF_PRUNC_CSM_Pos          (1U)\r
-#define   POSIF_PRUNC_CSM_Msk          (0x00000001U  << POSIF_PRUNC_CSM_Pos)\r
-\r
-/* POSIF_PRUN  =  Architectural Overview Run Bit Status*/\r
-#define   POSIF_PRUN_RB_Pos    (0U)\r
-#define   POSIF_PRUN_RB_Msk    (0x00000001U  << POSIF_PRUN_RB_Pos)\r
-\r
-/* POSIF_MIDR  =  Module Identification register*/\r
-#define   POSIF_MIDR_MODR_Pos          (0U)\r
-#define   POSIF_MIDR_MODR_Msk          (0x000000FFU  << POSIF_MIDR_MODR_Pos)\r
-\r
-#define   POSIF_MIDR_MODT_Pos          (8U)\r
-#define   POSIF_MIDR_MODT_Msk          (0x000000FFU  << POSIF_MIDR_MODT_Pos)\r
-\r
-#define   POSIF_MIDR_MODN_Pos          (16U)\r
-#define   POSIF_MIDR_MODN_Msk          (0x0000FFFFU  << POSIF_MIDR_MODN_Pos)\r
-\r
-/* POSIF_HALP  =  Hall Sensor Patterns*/\r
-#define   POSIF_HALP_HCP_Pos   (0U)\r
-#define   POSIF_HALP_HCP_Msk   (0x00000007U  << POSIF_HALP_HCP_Pos)\r
-\r
-#define   POSIF_HALP_HEP_Pos   (3U)\r
-#define   POSIF_HALP_HEP_Msk   (0x00000007U  << POSIF_HALP_HEP_Pos)\r
-\r
-/* POSIF_HALPS  =  Hall Sensor Shadow Patterns*/\r
-#define   POSIF_HALPS_HCPS_Pos         (0U)\r
-#define   POSIF_HALPS_HCPS_Msk         (0x00000007U  << POSIF_HALPS_HCPS_Pos)\r
-\r
-#define   POSIF_HALPS_HEPS_Pos         (3U)\r
-#define   POSIF_HALPS_HEPS_Msk         (0x00000007U  << POSIF_HALPS_HEPS_Pos)\r
-\r
-/* POSIF_MCM  =  Multi Channel Pattern*/\r
-#define   POSIF_MCM_MCMP_Pos   (0U)\r
-#define   POSIF_MCM_MCMP_Msk   (0x0000FFFFU  << POSIF_MCM_MCMP_Pos)\r
-\r
-/* POSIF_MCSM  =  Multi Channel Shadow Pattern*/\r
-#define   POSIF_MCSM_MCMPS_Pos         (0U)\r
-#define   POSIF_MCSM_MCMPS_Msk         (0x0000FFFFU  << POSIF_MCSM_MCMPS_Pos)\r
-\r
-/* POSIF_MCMS  =  Multi Channel Pattern Control set*/\r
-#define   POSIF_MCMS_MNPS_Pos          (0U)\r
-#define   POSIF_MCMS_MNPS_Msk          (0x00000001U  << POSIF_MCMS_MNPS_Pos)\r
-\r
-#define   POSIF_MCMS_STHR_Pos          (1U)\r
-#define   POSIF_MCMS_STHR_Msk          (0x00000001U  << POSIF_MCMS_STHR_Pos)\r
-\r
-#define   POSIF_MCMS_STMR_Pos          (2U)\r
-#define   POSIF_MCMS_STMR_Msk          (0x00000001U  << POSIF_MCMS_STMR_Pos)\r
-\r
-/* POSIF_MCMC  =  Multi Channel Pattern Control clear*/\r
-#define   POSIF_MCMC_MNPC_Pos          (0U)\r
-#define   POSIF_MCMC_MNPC_Msk          (0x00000001U  << POSIF_MCMC_MNPC_Pos)\r
-\r
-#define   POSIF_MCMC_MPC_Pos   (1U)\r
-#define   POSIF_MCMC_MPC_Msk   (0x00000001U  << POSIF_MCMC_MPC_Pos)\r
-\r
-/* POSIF_MCMF  =  Multi Channel Pattern Control flag*/\r
-#define   POSIF_MCMF_MSS_Pos   (0U)\r
-#define   POSIF_MCMF_MSS_Msk   (0x00000001U  << POSIF_MCMF_MSS_Pos)\r
-\r
-/* POSIF_QDC  =  Quadrature Decoder Control*/\r
-#define   POSIF_QDC_PALS_Pos   (0U)\r
-#define   POSIF_QDC_PALS_Msk   (0x00000001U  << POSIF_QDC_PALS_Pos)\r
-\r
-#define   POSIF_QDC_PBLS_Pos   (1U)\r
-#define   POSIF_QDC_PBLS_Msk   (0x00000001U  << POSIF_QDC_PBLS_Pos)\r
-\r
-#define   POSIF_QDC_PHS_Pos    (2U)\r
-#define   POSIF_QDC_PHS_Msk    (0x00000001U  << POSIF_QDC_PHS_Pos)\r
-\r
-#define   POSIF_QDC_ICM_Pos    (4U)\r
-#define   POSIF_QDC_ICM_Msk    (0x00000003U  << POSIF_QDC_ICM_Pos)\r
-\r
-#define   POSIF_QDC_DVAL_Pos   (8U)\r
-#define   POSIF_QDC_DVAL_Msk   (0x00000001U  << POSIF_QDC_DVAL_Pos)\r
-\r
-/* POSIF_PFLG  =  Architectural Overview Interrupt Flags*/\r
-#define   POSIF_PFLG_CHES_Pos          (0U)\r
-#define   POSIF_PFLG_CHES_Msk          (0x00000001U  << POSIF_PFLG_CHES_Pos)\r
-\r
-#define   POSIF_PFLG_WHES_Pos          (1U)\r
-#define   POSIF_PFLG_WHES_Msk          (0x00000001U  << POSIF_PFLG_WHES_Pos)\r
-\r
-#define   POSIF_PFLG_HIES_Pos          (2U)\r
-#define   POSIF_PFLG_HIES_Msk          (0x00000001U  << POSIF_PFLG_HIES_Pos)\r
-\r
-#define   POSIF_PFLG_MSTS_Pos          (4U)\r
-#define   POSIF_PFLG_MSTS_Msk          (0x00000001U  << POSIF_PFLG_MSTS_Pos)\r
-\r
-#define   POSIF_PFLG_INDXS_Pos         (8U)\r
-#define   POSIF_PFLG_INDXS_Msk         (0x00000001U  << POSIF_PFLG_INDXS_Pos)\r
-\r
-#define   POSIF_PFLG_ERRS_Pos          (9U)\r
-#define   POSIF_PFLG_ERRS_Msk          (0x00000001U  << POSIF_PFLG_ERRS_Pos)\r
-\r
-#define   POSIF_PFLG_CNTS_Pos          (10U)\r
-#define   POSIF_PFLG_CNTS_Msk          (0x00000001U  << POSIF_PFLG_CNTS_Pos)\r
-\r
-#define   POSIF_PFLG_DIRS_Pos          (11U)\r
-#define   POSIF_PFLG_DIRS_Msk          (0x00000001U  << POSIF_PFLG_DIRS_Pos)\r
-\r
-#define   POSIF_PFLG_PCLKS_Pos         (12U)\r
-#define   POSIF_PFLG_PCLKS_Msk         (0x00000001U  << POSIF_PFLG_PCLKS_Pos)\r
-\r
-/* POSIF_PFLGE  =  Architectural Overview Interrupt Enable*/\r
-#define   POSIF_PFLGE_ECHE_Pos         (0U)\r
-#define   POSIF_PFLGE_ECHE_Msk         (0x00000001U  << POSIF_PFLGE_ECHE_Pos)\r
-\r
-#define   POSIF_PFLGE_EWHE_Pos         (1U)\r
-#define   POSIF_PFLGE_EWHE_Msk         (0x00000001U  << POSIF_PFLGE_EWHE_Pos)\r
-\r
-#define   POSIF_PFLGE_EHIE_Pos         (2U)\r
-#define   POSIF_PFLGE_EHIE_Msk         (0x00000001U  << POSIF_PFLGE_EHIE_Pos)\r
-\r
-#define   POSIF_PFLGE_EMST_Pos         (4U)\r
-#define   POSIF_PFLGE_EMST_Msk         (0x00000001U  << POSIF_PFLGE_EMST_Pos)\r
-\r
-#define   POSIF_PFLGE_EINDX_Pos        (8U)\r
-#define   POSIF_PFLGE_EINDX_Msk        (0x00000001U  << POSIF_PFLGE_EINDX_Pos)\r
-\r
-#define   POSIF_PFLGE_EERR_Pos         (9U)\r
-#define   POSIF_PFLGE_EERR_Msk         (0x00000001U  << POSIF_PFLGE_EERR_Pos)\r
-\r
-#define   POSIF_PFLGE_ECNT_Pos         (10U)\r
-#define   POSIF_PFLGE_ECNT_Msk         (0x00000001U  << POSIF_PFLGE_ECNT_Pos)\r
-\r
-#define   POSIF_PFLGE_EDIR_Pos         (11U)\r
-#define   POSIF_PFLGE_EDIR_Msk         (0x00000001U  << POSIF_PFLGE_EDIR_Pos)\r
-\r
-#define   POSIF_PFLGE_EPCLK_Pos        (12U)\r
-#define   POSIF_PFLGE_EPCLK_Msk        (0x00000001U  << POSIF_PFLGE_EPCLK_Pos)\r
-\r
-#define   POSIF_PFLGE_CHESEL_Pos       (16U)\r
-#define   POSIF_PFLGE_CHESEL_Msk       (0x00000001U  << POSIF_PFLGE_CHESEL_Pos)\r
-\r
-#define   POSIF_PFLGE_WHESEL_Pos       (17U)\r
-#define   POSIF_PFLGE_WHESEL_Msk       (0x00000001U  << POSIF_PFLGE_WHESEL_Pos)\r
-\r
-#define   POSIF_PFLGE_HIESEL_Pos       (18U)\r
-#define   POSIF_PFLGE_HIESEL_Msk       (0x00000001U  << POSIF_PFLGE_HIESEL_Pos)\r
-\r
-#define   POSIF_PFLGE_MSTSEL_Pos       (20U)\r
-#define   POSIF_PFLGE_MSTSEL_Msk       (0x00000001U  << POSIF_PFLGE_MSTSEL_Pos)\r
-\r
-#define   POSIF_PFLGE_INDSEL_Pos       (24U)\r
-#define   POSIF_PFLGE_INDSEL_Msk       (0x00000001U  << POSIF_PFLGE_INDSEL_Pos)\r
-\r
-#define   POSIF_PFLGE_ERRSEL_Pos       (25U)\r
-#define   POSIF_PFLGE_ERRSEL_Msk       (0x00000001U  << POSIF_PFLGE_ERRSEL_Pos)\r
-\r
-#define   POSIF_PFLGE_CNTSEL_Pos       (26U)\r
-#define   POSIF_PFLGE_CNTSEL_Msk       (0x00000001U  << POSIF_PFLGE_CNTSEL_Pos)\r
-\r
-#define   POSIF_PFLGE_DIRSEL_Pos       (27U)\r
-#define   POSIF_PFLGE_DIRSEL_Msk       (0x00000001U  << POSIF_PFLGE_DIRSEL_Pos)\r
-\r
-#define   POSIF_PFLGE_PCLSEL_Pos       (28U)\r
-#define   POSIF_PFLGE_PCLSEL_Msk       (0x00000001U  << POSIF_PFLGE_PCLSEL_Pos)\r
-\r
-/* POSIF_SPFLG  =  Architectural Overview Interrupt Set*/\r
-#define   POSIF_SPFLG_SCHE_Pos         (0U)\r
-#define   POSIF_SPFLG_SCHE_Msk         (0x00000001U  << POSIF_SPFLG_SCHE_Pos)\r
-\r
-#define   POSIF_SPFLG_SWHE_Pos         (1U)\r
-#define   POSIF_SPFLG_SWHE_Msk         (0x00000001U  << POSIF_SPFLG_SWHE_Pos)\r
-\r
-#define   POSIF_SPFLG_SHIE_Pos         (2U)\r
-#define   POSIF_SPFLG_SHIE_Msk         (0x00000001U  << POSIF_SPFLG_SHIE_Pos)\r
-\r
-#define   POSIF_SPFLG_SMST_Pos         (4U)\r
-#define   POSIF_SPFLG_SMST_Msk         (0x00000001U  << POSIF_SPFLG_SMST_Pos)\r
-\r
-#define   POSIF_SPFLG_SINDX_Pos        (8U)\r
-#define   POSIF_SPFLG_SINDX_Msk        (0x00000001U  << POSIF_SPFLG_SINDX_Pos)\r
-\r
-#define   POSIF_SPFLG_SERR_Pos         (9U)\r
-#define   POSIF_SPFLG_SERR_Msk         (0x00000001U  << POSIF_SPFLG_SERR_Pos)\r
-\r
-#define   POSIF_SPFLG_SCNT_Pos         (10U)\r
-#define   POSIF_SPFLG_SCNT_Msk         (0x00000001U  << POSIF_SPFLG_SCNT_Pos)\r
-\r
-#define   POSIF_SPFLG_SDIR_Pos         (11U)\r
-#define   POSIF_SPFLG_SDIR_Msk         (0x00000001U  << POSIF_SPFLG_SDIR_Pos)\r
-\r
-#define   POSIF_SPFLG_SPCLK_Pos        (12U)\r
-#define   POSIF_SPFLG_SPCLK_Msk        (0x00000001U  << POSIF_SPFLG_SPCLK_Pos)\r
-\r
-/* POSIF_RPFLG  =  Architectural Overview Interrupt Clear*/\r
-#define   POSIF_RPFLG_RCHE_Pos         (0U)\r
-#define   POSIF_RPFLG_RCHE_Msk         (0x00000001U  << POSIF_RPFLG_RCHE_Pos)\r
-\r
-#define   POSIF_RPFLG_RWHE_Pos         (1U)\r
-#define   POSIF_RPFLG_RWHE_Msk         (0x00000001U  << POSIF_RPFLG_RWHE_Pos)\r
-\r
-#define   POSIF_RPFLG_RHIE_Pos         (2U)\r
-#define   POSIF_RPFLG_RHIE_Msk         (0x00000001U  << POSIF_RPFLG_RHIE_Pos)\r
-\r
-#define   POSIF_RPFLG_RMST_Pos         (4U)\r
-#define   POSIF_RPFLG_RMST_Msk         (0x00000001U  << POSIF_RPFLG_RMST_Pos)\r
-\r
-#define   POSIF_RPFLG_RINDX_Pos        (8U)\r
-#define   POSIF_RPFLG_RINDX_Msk        (0x00000001U  << POSIF_RPFLG_RINDX_Pos)\r
-\r
-#define   POSIF_RPFLG_RERR_Pos         (9U)\r
-#define   POSIF_RPFLG_RERR_Msk         (0x00000001U  << POSIF_RPFLG_RERR_Pos)\r
-\r
-#define   POSIF_RPFLG_RCNT_Pos         (10U)\r
-#define   POSIF_RPFLG_RCNT_Msk         (0x00000001U  << POSIF_RPFLG_RCNT_Pos)\r
-\r
-#define   POSIF_RPFLG_RDIR_Pos         (11U)\r
-#define   POSIF_RPFLG_RDIR_Msk         (0x00000001U  << POSIF_RPFLG_RDIR_Pos)\r
-\r
-#define   POSIF_RPFLG_RPCLK_Pos        (12U)\r
-#define   POSIF_RPFLG_RPCLK_Msk        (0x00000001U  << POSIF_RPFLG_RPCLK_Pos)\r
-\r
-// ------------------------------------------------------------------------------------------------\r
-// -----                                  PPB Position & Mask                                 -----\r
-// ------------------------------------------------------------------------------------------------\r
-\r
-// ----------------------------------------  PPB_ACTLR  -------------------------------------------\r
-#define PPB_ACTLR_DISMCYCINT_Pos                              0                                                         /*!< PPB ACTLR: DISMCYCINT Position      */\r
-#define PPB_ACTLR_DISMCYCINT_Msk                              (0x01UL << PPB_ACTLR_DISMCYCINT_Pos)                      /*!< PPB ACTLR: DISMCYCINT Mask          */\r
-#define PPB_ACTLR_DISDEFWBUF_Pos                              1                                                         /*!< PPB ACTLR: DISDEFWBUF Position      */\r
-#define PPB_ACTLR_DISDEFWBUF_Msk                              (0x01UL << PPB_ACTLR_DISDEFWBUF_Pos)                      /*!< PPB ACTLR: DISDEFWBUF Mask          */\r
-#define PPB_ACTLR_DISFOLD_Pos                                 2                                                         /*!< PPB ACTLR: DISFOLD Position         */\r
-#define PPB_ACTLR_DISFOLD_Msk                                 (0x01UL << PPB_ACTLR_DISFOLD_Pos)                         /*!< PPB ACTLR: DISFOLD Mask             */\r
-#define PPB_ACTLR_DISFPCA_Pos                                 8                                                         /*!< PPB ACTLR: DISFPCA Position         */\r
-#define PPB_ACTLR_DISFPCA_Msk                                 (0x01UL << PPB_ACTLR_DISFPCA_Pos)                         /*!< PPB ACTLR: DISFPCA Mask             */\r
-#define PPB_ACTLR_DISOOFP_Pos                                 9                                                         /*!< PPB ACTLR: DISOOFP Position         */\r
-#define PPB_ACTLR_DISOOFP_Msk                                 (0x01UL << PPB_ACTLR_DISOOFP_Pos)                         /*!< PPB ACTLR: DISOOFP Mask             */\r
-\r
-// --------------------------------------  PPB_SYST_CSR  ------------------------------------------\r
-#define PPB_SYST_CSR_ENABLE_Pos                               0                                                         /*!< PPB SYST_CSR: ENABLE Position       */\r
-#define PPB_SYST_CSR_ENABLE_Msk                               (0x01UL << PPB_SYST_CSR_ENABLE_Pos)                       /*!< PPB SYST_CSR: ENABLE Mask           */\r
-#define PPB_SYST_CSR_TICKINT_Pos                              1                                                         /*!< PPB SYST_CSR: TICKINT Position      */\r
-#define PPB_SYST_CSR_TICKINT_Msk                              (0x01UL << PPB_SYST_CSR_TICKINT_Pos)                      /*!< PPB SYST_CSR: TICKINT Mask          */\r
-#define PPB_SYST_CSR_CLKSOURCE_Pos                            2                                                         /*!< PPB SYST_CSR: CLKSOURCE Position    */\r
-#define PPB_SYST_CSR_CLKSOURCE_Msk                            (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos)                    /*!< PPB SYST_CSR: CLKSOURCE Mask        */\r
-#define PPB_SYST_CSR_COUNTFLAG_Pos                            16                                                        /*!< PPB SYST_CSR: COUNTFLAG Position    */\r
-#define PPB_SYST_CSR_COUNTFLAG_Msk                            (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos)                    /*!< PPB SYST_CSR: COUNTFLAG Mask        */\r
-\r
-// --------------------------------------  PPB_SYST_RVR  ------------------------------------------\r
-#define PPB_SYST_RVR_RELOAD_Pos                               0                                                         /*!< PPB SYST_RVR: RELOAD Position       */\r
-#define PPB_SYST_RVR_RELOAD_Msk                               (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos)                 /*!< PPB SYST_RVR: RELOAD Mask           */\r
-\r
-// --------------------------------------  PPB_SYST_CVR  ------------------------------------------\r
-#define PPB_SYST_CVR_CURRENT_Pos                              0                                                         /*!< PPB SYST_CVR: CURRENT Position      */\r
-#define PPB_SYST_CVR_CURRENT_Msk                              (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos)                /*!< PPB SYST_CVR: CURRENT Mask          */\r
-\r
-// -------------------------------------  PPB_SYST_CALIB  -----------------------------------------\r
-#define PPB_SYST_CALIB_TENMS_Pos                              0                                                         /*!< PPB SYST_CALIB: TENMS Position      */\r
-#define PPB_SYST_CALIB_TENMS_Msk                              (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos)                /*!< PPB SYST_CALIB: TENMS Mask          */\r
-#define PPB_SYST_CALIB_SKEW_Pos                               30                                                        /*!< PPB SYST_CALIB: SKEW Position       */\r
-#define PPB_SYST_CALIB_SKEW_Msk                               (0x01UL << PPB_SYST_CALIB_SKEW_Pos)                       /*!< PPB SYST_CALIB: SKEW Mask           */\r
-#define PPB_SYST_CALIB_NOREF_Pos                              31                                                        /*!< PPB SYST_CALIB: NOREF Position      */\r
-#define PPB_SYST_CALIB_NOREF_Msk                              (0x01UL << PPB_SYST_CALIB_NOREF_Pos)                      /*!< PPB SYST_CALIB: NOREF Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_ISER0  -----------------------------------------\r
-#define PPB_NVIC_ISER0_SETENA_Pos                             0                                                         /*!< PPB NVIC_ISER0: SETENA Position     */\r
-#define PPB_NVIC_ISER0_SETENA_Msk                             (0xffffffffUL << PPB_NVIC_ISER0_SETENA_Pos)               /*!< PPB NVIC_ISER0: SETENA Mask         */\r
-\r
-// -------------------------------------  PPB_NVIC_ISER1  -----------------------------------------\r
-#define PPB_NVIC_ISER1_SETENA_Pos                             0                                                         /*!< PPB NVIC_ISER1: SETENA Position     */\r
-#define PPB_NVIC_ISER1_SETENA_Msk                             (0xffffffffUL << PPB_NVIC_ISER1_SETENA_Pos)               /*!< PPB NVIC_ISER1: SETENA Mask         */\r
-\r
-// -------------------------------------  PPB_NVIC_ISER2  -----------------------------------------\r
-#define PPB_NVIC_ISER2_SETENA_Pos                             0                                                         /*!< PPB NVIC_ISER2: SETENA Position     */\r
-#define PPB_NVIC_ISER2_SETENA_Msk                             (0xffffffffUL << PPB_NVIC_ISER2_SETENA_Pos)               /*!< PPB NVIC_ISER2: SETENA Mask         */\r
-\r
-// -------------------------------------  PPB_NVIC_ISER3  -----------------------------------------\r
-#define PPB_NVIC_ISER3_SETENA_Pos                             0                                                         /*!< PPB NVIC_ISER3: SETENA Position     */\r
-#define PPB_NVIC_ISER3_SETENA_Msk                             (0xffffffffUL << PPB_NVIC_ISER3_SETENA_Pos)               /*!< PPB NVIC_ISER3: SETENA Mask         */\r
-\r
-// -------------------------------------  PPB_NVIC_ISCER0  ----------------------------------------\r
-#define PPB_NVIC_ISCER0_CLRENA_Pos                            0                                                         /*!< PPB NVIC_ISCER0: CLRENA Position    */\r
-#define PPB_NVIC_ISCER0_CLRENA_Msk                            (0xffffffffUL << PPB_NVIC_ISCER0_CLRENA_Pos)              /*!< PPB NVIC_ISCER0: CLRENA Mask        */\r
-\r
-// -------------------------------------  PPB_NVIC_ISCER1  ----------------------------------------\r
-#define PPB_NVIC_ISCER1_CLRENA_Pos                            0                                                         /*!< PPB NVIC_ISCER1: CLRENA Position    */\r
-#define PPB_NVIC_ISCER1_CLRENA_Msk                            (0xffffffffUL << PPB_NVIC_ISCER1_CLRENA_Pos)              /*!< PPB NVIC_ISCER1: CLRENA Mask        */\r
-\r
-// -------------------------------------  PPB_NVIC_ISCER2  ----------------------------------------\r
-#define PPB_NVIC_ISCER2_CLRENA_Pos                            0                                                         /*!< PPB NVIC_ISCER2: CLRENA Position    */\r
-#define PPB_NVIC_ISCER2_CLRENA_Msk                            (0xffffffffUL << PPB_NVIC_ISCER2_CLRENA_Pos)              /*!< PPB NVIC_ISCER2: CLRENA Mask        */\r
-\r
-// -------------------------------------  PPB_NVIC_ISCER3  ----------------------------------------\r
-#define PPB_NVIC_ISCER3_CLRENA_Pos                            0                                                         /*!< PPB NVIC_ISCER3: CLRENA Position    */\r
-#define PPB_NVIC_ISCER3_CLRENA_Msk                            (0xffffffffUL << PPB_NVIC_ISCER3_CLRENA_Pos)              /*!< PPB NVIC_ISCER3: CLRENA Mask        */\r
-\r
-// -------------------------------------  PPB_NVIC_ISSPR0  ----------------------------------------\r
-#define PPB_NVIC_ISSPR0_SETPEND_Pos                           0                                                         /*!< PPB NVIC_ISSPR0: SETPEND Position   */\r
-#define PPB_NVIC_ISSPR0_SETPEND_Msk                           (0xffffffffUL << PPB_NVIC_ISSPR0_SETPEND_Pos)             /*!< PPB NVIC_ISSPR0: SETPEND Mask       */\r
-\r
-// -------------------------------------  PPB_NVIC_ISSPR1  ----------------------------------------\r
-#define PPB_NVIC_ISSPR1_SETPEND_Pos                           0                                                         /*!< PPB NVIC_ISSPR1: SETPEND Position   */\r
-#define PPB_NVIC_ISSPR1_SETPEND_Msk                           (0xffffffffUL << PPB_NVIC_ISSPR1_SETPEND_Pos)             /*!< PPB NVIC_ISSPR1: SETPEND Mask       */\r
-\r
-// -------------------------------------  PPB_NVIC_ISSPR2  ----------------------------------------\r
-#define PPB_NVIC_ISSPR2_SETPEND_Pos                           0                                                         /*!< PPB NVIC_ISSPR2: SETPEND Position   */\r
-#define PPB_NVIC_ISSPR2_SETPEND_Msk                           (0xffffffffUL << PPB_NVIC_ISSPR2_SETPEND_Pos)             /*!< PPB NVIC_ISSPR2: SETPEND Mask       */\r
-\r
-// -------------------------------------  PPB_NVIC_ISSPR3  ----------------------------------------\r
-#define PPB_NVIC_ISSPR3_SETPEND_Pos                           0                                                         /*!< PPB NVIC_ISSPR3: SETPEND Position   */\r
-#define PPB_NVIC_ISSPR3_SETPEND_Msk                           (0xffffffffUL << PPB_NVIC_ISSPR3_SETPEND_Pos)             /*!< PPB NVIC_ISSPR3: SETPEND Mask       */\r
-\r
-// -------------------------------------  PPB_NVIC_ICPR0  -----------------------------------------\r
-#define PPB_NVIC_ICPR0_CLRPEND_Pos                            0                                                         /*!< PPB NVIC_ICPR0: CLRPEND Position    */\r
-#define PPB_NVIC_ICPR0_CLRPEND_Msk                            (0xffffffffUL << PPB_NVIC_ICPR0_CLRPEND_Pos)              /*!< PPB NVIC_ICPR0: CLRPEND Mask        */\r
-\r
-// -------------------------------------  PPB_NVIC_ICPR1  -----------------------------------------\r
-#define PPB_NVIC_ICPR1_CLRPEND_Pos                            0                                                         /*!< PPB NVIC_ICPR1: CLRPEND Position    */\r
-#define PPB_NVIC_ICPR1_CLRPEND_Msk                            (0xffffffffUL << PPB_NVIC_ICPR1_CLRPEND_Pos)              /*!< PPB NVIC_ICPR1: CLRPEND Mask        */\r
-\r
-// -------------------------------------  PPB_NVIC_ICPR2  -----------------------------------------\r
-#define PPB_NVIC_ICPR2_CLRPEND_Pos                            0                                                         /*!< PPB NVIC_ICPR2: CLRPEND Position    */\r
-#define PPB_NVIC_ICPR2_CLRPEND_Msk                            (0xffffffffUL << PPB_NVIC_ICPR2_CLRPEND_Pos)              /*!< PPB NVIC_ICPR2: CLRPEND Mask        */\r
-\r
-// -------------------------------------  PPB_NVIC_ICPR3  -----------------------------------------\r
-#define PPB_NVIC_ICPR3_CLRPEND_Pos                            0                                                         /*!< PPB NVIC_ICPR3: CLRPEND Position    */\r
-#define PPB_NVIC_ICPR3_CLRPEND_Msk                            (0xffffffffUL << PPB_NVIC_ICPR3_CLRPEND_Pos)              /*!< PPB NVIC_ICPR3: CLRPEND Mask        */\r
-\r
-// -------------------------------------  PPB_NVIC_IABR0  -----------------------------------------\r
-#define PPB_NVIC_IABR0_ACTIVE_Pos                             0                                                         /*!< PPB NVIC_IABR0: ACTIVE Position     */\r
-#define PPB_NVIC_IABR0_ACTIVE_Msk                             (0xffffffffUL << PPB_NVIC_IABR0_ACTIVE_Pos)               /*!< PPB NVIC_IABR0: ACTIVE Mask         */\r
-\r
-// -------------------------------------  PPB_NVIC_IABR1  -----------------------------------------\r
-#define PPB_NVIC_IABR1_ACTIVE_Pos                             0                                                         /*!< PPB NVIC_IABR1: ACTIVE Position     */\r
-#define PPB_NVIC_IABR1_ACTIVE_Msk                             (0xffffffffUL << PPB_NVIC_IABR1_ACTIVE_Pos)               /*!< PPB NVIC_IABR1: ACTIVE Mask         */\r
-\r
-// -------------------------------------  PPB_NVIC_IABR2  -----------------------------------------\r
-#define PPB_NVIC_IABR2_ACTIVE_Pos                             0                                                         /*!< PPB NVIC_IABR2: ACTIVE Position     */\r
-#define PPB_NVIC_IABR2_ACTIVE_Msk                             (0xffffffffUL << PPB_NVIC_IABR2_ACTIVE_Pos)               /*!< PPB NVIC_IABR2: ACTIVE Mask         */\r
-\r
-// -------------------------------------  PPB_NVIC_IABR3  -----------------------------------------\r
-#define PPB_NVIC_IABR3_ACTIVE_Pos                             0                                                         /*!< PPB NVIC_IABR3: ACTIVE Position     */\r
-#define PPB_NVIC_IABR3_ACTIVE_Msk                             (0xffffffffUL << PPB_NVIC_IABR3_ACTIVE_Pos)               /*!< PPB NVIC_IABR3: ACTIVE Mask         */\r
-\r
-// --------------------------------------  PPB_NVIC_IPR0  -----------------------------------------\r
-#define PPB_NVIC_IPR0_PRI_0_Pos                               0                                                         /*!< PPB NVIC_IPR0: PRI_0 Position       */\r
-#define PPB_NVIC_IPR0_PRI_0_Msk                               (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos)                 /*!< PPB NVIC_IPR0: PRI_0 Mask           */\r
-#define PPB_NVIC_IPR0_PRI_1_Pos                               8                                                         /*!< PPB NVIC_IPR0: PRI_1 Position       */\r
-#define PPB_NVIC_IPR0_PRI_1_Msk                               (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos)                 /*!< PPB NVIC_IPR0: PRI_1 Mask           */\r
-#define PPB_NVIC_IPR0_PRI_2_Pos                               16                                                        /*!< PPB NVIC_IPR0: PRI_2 Position       */\r
-#define PPB_NVIC_IPR0_PRI_2_Msk                               (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos)                 /*!< PPB NVIC_IPR0: PRI_2 Mask           */\r
-#define PPB_NVIC_IPR0_PRI_3_Pos                               24                                                        /*!< PPB NVIC_IPR0: PRI_3 Position       */\r
-#define PPB_NVIC_IPR0_PRI_3_Msk                               (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos)                 /*!< PPB NVIC_IPR0: PRI_3 Mask           */\r
-\r
-// --------------------------------------  PPB_NVIC_IPR1  -----------------------------------------\r
-#define PPB_NVIC_IPR1_PRI_0_Pos                               0                                                         /*!< PPB NVIC_IPR1: PRI_0 Position       */\r
-#define PPB_NVIC_IPR1_PRI_0_Msk                               (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos)                 /*!< PPB NVIC_IPR1: PRI_0 Mask           */\r
-#define PPB_NVIC_IPR1_PRI_1_Pos                               8                                                         /*!< PPB NVIC_IPR1: PRI_1 Position       */\r
-#define PPB_NVIC_IPR1_PRI_1_Msk                               (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos)                 /*!< PPB NVIC_IPR1: PRI_1 Mask           */\r
-#define PPB_NVIC_IPR1_PRI_2_Pos                               16                                                        /*!< PPB NVIC_IPR1: PRI_2 Position       */\r
-#define PPB_NVIC_IPR1_PRI_2_Msk                               (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos)                 /*!< PPB NVIC_IPR1: PRI_2 Mask           */\r
-#define PPB_NVIC_IPR1_PRI_3_Pos                               24                                                        /*!< PPB NVIC_IPR1: PRI_3 Position       */\r
-#define PPB_NVIC_IPR1_PRI_3_Msk                               (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos)                 /*!< PPB NVIC_IPR1: PRI_3 Mask           */\r
-\r
-// --------------------------------------  PPB_NVIC_IPR2  -----------------------------------------\r
-#define PPB_NVIC_IPR2_PRI_0_Pos                               0                                                         /*!< PPB NVIC_IPR2: PRI_0 Position       */\r
-#define PPB_NVIC_IPR2_PRI_0_Msk                               (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos)                 /*!< PPB NVIC_IPR2: PRI_0 Mask           */\r
-#define PPB_NVIC_IPR2_PRI_1_Pos                               8                                                         /*!< PPB NVIC_IPR2: PRI_1 Position       */\r
-#define PPB_NVIC_IPR2_PRI_1_Msk                               (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos)                 /*!< PPB NVIC_IPR2: PRI_1 Mask           */\r
-#define PPB_NVIC_IPR2_PRI_2_Pos                               16                                                        /*!< PPB NVIC_IPR2: PRI_2 Position       */\r
-#define PPB_NVIC_IPR2_PRI_2_Msk                               (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos)                 /*!< PPB NVIC_IPR2: PRI_2 Mask           */\r
-#define PPB_NVIC_IPR2_PRI_3_Pos                               24                                                        /*!< PPB NVIC_IPR2: PRI_3 Position       */\r
-#define PPB_NVIC_IPR2_PRI_3_Msk                               (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos)                 /*!< PPB NVIC_IPR2: PRI_3 Mask           */\r
-\r
-// --------------------------------------  PPB_NVIC_IPR3  -----------------------------------------\r
-#define PPB_NVIC_IPR3_PRI_0_Pos                               0                                                         /*!< PPB NVIC_IPR3: PRI_0 Position       */\r
-#define PPB_NVIC_IPR3_PRI_0_Msk                               (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos)                 /*!< PPB NVIC_IPR3: PRI_0 Mask           */\r
-#define PPB_NVIC_IPR3_PRI_1_Pos                               8                                                         /*!< PPB NVIC_IPR3: PRI_1 Position       */\r
-#define PPB_NVIC_IPR3_PRI_1_Msk                               (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos)                 /*!< PPB NVIC_IPR3: PRI_1 Mask           */\r
-#define PPB_NVIC_IPR3_PRI_2_Pos                               16                                                        /*!< PPB NVIC_IPR3: PRI_2 Position       */\r
-#define PPB_NVIC_IPR3_PRI_2_Msk                               (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos)                 /*!< PPB NVIC_IPR3: PRI_2 Mask           */\r
-#define PPB_NVIC_IPR3_PRI_3_Pos                               24                                                        /*!< PPB NVIC_IPR3: PRI_3 Position       */\r
-#define PPB_NVIC_IPR3_PRI_3_Msk                               (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos)                 /*!< PPB NVIC_IPR3: PRI_3 Mask           */\r
-\r
-// --------------------------------------  PPB_NVIC_IPR4  -----------------------------------------\r
-#define PPB_NVIC_IPR4_PRI_0_Pos                               0                                                         /*!< PPB NVIC_IPR4: PRI_0 Position       */\r
-#define PPB_NVIC_IPR4_PRI_0_Msk                               (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos)                 /*!< PPB NVIC_IPR4: PRI_0 Mask           */\r
-#define PPB_NVIC_IPR4_PRI_1_Pos                               8                                                         /*!< PPB NVIC_IPR4: PRI_1 Position       */\r
-#define PPB_NVIC_IPR4_PRI_1_Msk                               (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos)                 /*!< PPB NVIC_IPR4: PRI_1 Mask           */\r
-#define PPB_NVIC_IPR4_PRI_2_Pos                               16                                                        /*!< PPB NVIC_IPR4: PRI_2 Position       */\r
-#define PPB_NVIC_IPR4_PRI_2_Msk                               (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos)                 /*!< PPB NVIC_IPR4: PRI_2 Mask           */\r
-#define PPB_NVIC_IPR4_PRI_3_Pos                               24                                                        /*!< PPB NVIC_IPR4: PRI_3 Position       */\r
-#define PPB_NVIC_IPR4_PRI_3_Msk                               (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos)                 /*!< PPB NVIC_IPR4: PRI_3 Mask           */\r
-\r
-// --------------------------------------  PPB_NVIC_IPR5  -----------------------------------------\r
-#define PPB_NVIC_IPR5_PRI_0_Pos                               0                                                         /*!< PPB NVIC_IPR5: PRI_0 Position       */\r
-#define PPB_NVIC_IPR5_PRI_0_Msk                               (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos)                 /*!< PPB NVIC_IPR5: PRI_0 Mask           */\r
-#define PPB_NVIC_IPR5_PRI_1_Pos                               8                                                         /*!< PPB NVIC_IPR5: PRI_1 Position       */\r
-#define PPB_NVIC_IPR5_PRI_1_Msk                               (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos)                 /*!< PPB NVIC_IPR5: PRI_1 Mask           */\r
-#define PPB_NVIC_IPR5_PRI_2_Pos                               16                                                        /*!< PPB NVIC_IPR5: PRI_2 Position       */\r
-#define PPB_NVIC_IPR5_PRI_2_Msk                               (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos)                 /*!< PPB NVIC_IPR5: PRI_2 Mask           */\r
-#define PPB_NVIC_IPR5_PRI_3_Pos                               24                                                        /*!< PPB NVIC_IPR5: PRI_3 Position       */\r
-#define PPB_NVIC_IPR5_PRI_3_Msk                               (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos)                 /*!< PPB NVIC_IPR5: PRI_3 Mask           */\r
-\r
-// --------------------------------------  PPB_NVIC_IPR6  -----------------------------------------\r
-#define PPB_NVIC_IPR6_PRI_0_Pos                               0                                                         /*!< PPB NVIC_IPR6: PRI_0 Position       */\r
-#define PPB_NVIC_IPR6_PRI_0_Msk                               (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos)                 /*!< PPB NVIC_IPR6: PRI_0 Mask           */\r
-#define PPB_NVIC_IPR6_PRI_1_Pos                               8                                                         /*!< PPB NVIC_IPR6: PRI_1 Position       */\r
-#define PPB_NVIC_IPR6_PRI_1_Msk                               (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos)                 /*!< PPB NVIC_IPR6: PRI_1 Mask           */\r
-#define PPB_NVIC_IPR6_PRI_2_Pos                               16                                                        /*!< PPB NVIC_IPR6: PRI_2 Position       */\r
-#define PPB_NVIC_IPR6_PRI_2_Msk                               (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos)                 /*!< PPB NVIC_IPR6: PRI_2 Mask           */\r
-#define PPB_NVIC_IPR6_PRI_3_Pos                               24                                                        /*!< PPB NVIC_IPR6: PRI_3 Position       */\r
-#define PPB_NVIC_IPR6_PRI_3_Msk                               (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos)                 /*!< PPB NVIC_IPR6: PRI_3 Mask           */\r
-\r
-// --------------------------------------  PPB_NVIC_IPR7  -----------------------------------------\r
-#define PPB_NVIC_IPR7_PRI_0_Pos                               0                                                         /*!< PPB NVIC_IPR7: PRI_0 Position       */\r
-#define PPB_NVIC_IPR7_PRI_0_Msk                               (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos)                 /*!< PPB NVIC_IPR7: PRI_0 Mask           */\r
-#define PPB_NVIC_IPR7_PRI_1_Pos                               8                                                         /*!< PPB NVIC_IPR7: PRI_1 Position       */\r
-#define PPB_NVIC_IPR7_PRI_1_Msk                               (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos)                 /*!< PPB NVIC_IPR7: PRI_1 Mask           */\r
-#define PPB_NVIC_IPR7_PRI_2_Pos                               16                                                        /*!< PPB NVIC_IPR7: PRI_2 Position       */\r
-#define PPB_NVIC_IPR7_PRI_2_Msk                               (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos)                 /*!< PPB NVIC_IPR7: PRI_2 Mask           */\r
-#define PPB_NVIC_IPR7_PRI_3_Pos                               24                                                        /*!< PPB NVIC_IPR7: PRI_3 Position       */\r
-#define PPB_NVIC_IPR7_PRI_3_Msk                               (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos)                 /*!< PPB NVIC_IPR7: PRI_3 Mask           */\r
-\r
-// --------------------------------------  PPB_NVIC_IPR8  -----------------------------------------\r
-#define PPB_NVIC_IPR8_PRI_0_Pos                               0                                                         /*!< PPB NVIC_IPR8: PRI_0 Position       */\r
-#define PPB_NVIC_IPR8_PRI_0_Msk                               (0x000000ffUL << PPB_NVIC_IPR8_PRI_0_Pos)                 /*!< PPB NVIC_IPR8: PRI_0 Mask           */\r
-#define PPB_NVIC_IPR8_PRI_1_Pos                               8                                                         /*!< PPB NVIC_IPR8: PRI_1 Position       */\r
-#define PPB_NVIC_IPR8_PRI_1_Msk                               (0x000000ffUL << PPB_NVIC_IPR8_PRI_1_Pos)                 /*!< PPB NVIC_IPR8: PRI_1 Mask           */\r
-#define PPB_NVIC_IPR8_PRI_2_Pos                               16                                                        /*!< PPB NVIC_IPR8: PRI_2 Position       */\r
-#define PPB_NVIC_IPR8_PRI_2_Msk                               (0x000000ffUL << PPB_NVIC_IPR8_PRI_2_Pos)                 /*!< PPB NVIC_IPR8: PRI_2 Mask           */\r
-#define PPB_NVIC_IPR8_PRI_3_Pos                               24                                                        /*!< PPB NVIC_IPR8: PRI_3 Position       */\r
-#define PPB_NVIC_IPR8_PRI_3_Msk                               (0x000000ffUL << PPB_NVIC_IPR8_PRI_3_Pos)                 /*!< PPB NVIC_IPR8: PRI_3 Mask           */\r
-\r
-// --------------------------------------  PPB_NVIC_IPR9  -----------------------------------------\r
-#define PPB_NVIC_IPR9_PRI_0_Pos                               0                                                         /*!< PPB NVIC_IPR9: PRI_0 Position       */\r
-#define PPB_NVIC_IPR9_PRI_0_Msk                               (0x000000ffUL << PPB_NVIC_IPR9_PRI_0_Pos)                 /*!< PPB NVIC_IPR9: PRI_0 Mask           */\r
-#define PPB_NVIC_IPR9_PRI_1_Pos                               8                                                         /*!< PPB NVIC_IPR9: PRI_1 Position       */\r
-#define PPB_NVIC_IPR9_PRI_1_Msk                               (0x000000ffUL << PPB_NVIC_IPR9_PRI_1_Pos)                 /*!< PPB NVIC_IPR9: PRI_1 Mask           */\r
-#define PPB_NVIC_IPR9_PRI_2_Pos                               16                                                        /*!< PPB NVIC_IPR9: PRI_2 Position       */\r
-#define PPB_NVIC_IPR9_PRI_2_Msk                               (0x000000ffUL << PPB_NVIC_IPR9_PRI_2_Pos)                 /*!< PPB NVIC_IPR9: PRI_2 Mask           */\r
-#define PPB_NVIC_IPR9_PRI_3_Pos                               24                                                        /*!< PPB NVIC_IPR9: PRI_3 Position       */\r
-#define PPB_NVIC_IPR9_PRI_3_Msk                               (0x000000ffUL << PPB_NVIC_IPR9_PRI_3_Pos)                 /*!< PPB NVIC_IPR9: PRI_3 Mask           */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR10  -----------------------------------------\r
-#define PPB_NVIC_IPR10_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR10: PRI_0 Position      */\r
-#define PPB_NVIC_IPR10_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR10_PRI_0_Pos)                /*!< PPB NVIC_IPR10: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR10_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR10: PRI_1 Position      */\r
-#define PPB_NVIC_IPR10_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR10_PRI_1_Pos)                /*!< PPB NVIC_IPR10: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR10_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR10: PRI_2 Position      */\r
-#define PPB_NVIC_IPR10_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR10_PRI_2_Pos)                /*!< PPB NVIC_IPR10: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR10_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR10: PRI_3 Position      */\r
-#define PPB_NVIC_IPR10_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR10_PRI_3_Pos)                /*!< PPB NVIC_IPR10: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR11  -----------------------------------------\r
-#define PPB_NVIC_IPR11_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR11: PRI_0 Position      */\r
-#define PPB_NVIC_IPR11_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR11_PRI_0_Pos)                /*!< PPB NVIC_IPR11: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR11_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR11: PRI_1 Position      */\r
-#define PPB_NVIC_IPR11_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR11_PRI_1_Pos)                /*!< PPB NVIC_IPR11: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR11_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR11: PRI_2 Position      */\r
-#define PPB_NVIC_IPR11_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR11_PRI_2_Pos)                /*!< PPB NVIC_IPR11: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR11_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR11: PRI_3 Position      */\r
-#define PPB_NVIC_IPR11_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR11_PRI_3_Pos)                /*!< PPB NVIC_IPR11: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR12  -----------------------------------------\r
-#define PPB_NVIC_IPR12_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR12: PRI_0 Position      */\r
-#define PPB_NVIC_IPR12_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR12_PRI_0_Pos)                /*!< PPB NVIC_IPR12: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR12_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR12: PRI_1 Position      */\r
-#define PPB_NVIC_IPR12_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR12_PRI_1_Pos)                /*!< PPB NVIC_IPR12: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR12_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR12: PRI_2 Position      */\r
-#define PPB_NVIC_IPR12_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR12_PRI_2_Pos)                /*!< PPB NVIC_IPR12: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR12_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR12: PRI_3 Position      */\r
-#define PPB_NVIC_IPR12_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR12_PRI_3_Pos)                /*!< PPB NVIC_IPR12: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR13  -----------------------------------------\r
-#define PPB_NVIC_IPR13_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR13: PRI_0 Position      */\r
-#define PPB_NVIC_IPR13_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR13_PRI_0_Pos)                /*!< PPB NVIC_IPR13: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR13_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR13: PRI_1 Position      */\r
-#define PPB_NVIC_IPR13_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR13_PRI_1_Pos)                /*!< PPB NVIC_IPR13: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR13_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR13: PRI_2 Position      */\r
-#define PPB_NVIC_IPR13_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR13_PRI_2_Pos)                /*!< PPB NVIC_IPR13: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR13_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR13: PRI_3 Position      */\r
-#define PPB_NVIC_IPR13_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR13_PRI_3_Pos)                /*!< PPB NVIC_IPR13: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR14  -----------------------------------------\r
-#define PPB_NVIC_IPR14_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR14: PRI_0 Position      */\r
-#define PPB_NVIC_IPR14_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR14_PRI_0_Pos)                /*!< PPB NVIC_IPR14: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR14_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR14: PRI_1 Position      */\r
-#define PPB_NVIC_IPR14_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR14_PRI_1_Pos)                /*!< PPB NVIC_IPR14: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR14_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR14: PRI_2 Position      */\r
-#define PPB_NVIC_IPR14_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR14_PRI_2_Pos)                /*!< PPB NVIC_IPR14: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR14_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR14: PRI_3 Position      */\r
-#define PPB_NVIC_IPR14_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR14_PRI_3_Pos)                /*!< PPB NVIC_IPR14: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR15  -----------------------------------------\r
-#define PPB_NVIC_IPR15_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR15: PRI_0 Position      */\r
-#define PPB_NVIC_IPR15_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR15_PRI_0_Pos)                /*!< PPB NVIC_IPR15: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR15_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR15: PRI_1 Position      */\r
-#define PPB_NVIC_IPR15_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR15_PRI_1_Pos)                /*!< PPB NVIC_IPR15: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR15_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR15: PRI_2 Position      */\r
-#define PPB_NVIC_IPR15_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR15_PRI_2_Pos)                /*!< PPB NVIC_IPR15: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR15_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR15: PRI_3 Position      */\r
-#define PPB_NVIC_IPR15_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR15_PRI_3_Pos)                /*!< PPB NVIC_IPR15: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR16  -----------------------------------------\r
-#define PPB_NVIC_IPR16_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR16: PRI_0 Position      */\r
-#define PPB_NVIC_IPR16_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR16_PRI_0_Pos)                /*!< PPB NVIC_IPR16: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR16_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR16: PRI_1 Position      */\r
-#define PPB_NVIC_IPR16_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR16_PRI_1_Pos)                /*!< PPB NVIC_IPR16: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR16_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR16: PRI_2 Position      */\r
-#define PPB_NVIC_IPR16_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR16_PRI_2_Pos)                /*!< PPB NVIC_IPR16: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR16_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR16: PRI_3 Position      */\r
-#define PPB_NVIC_IPR16_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR16_PRI_3_Pos)                /*!< PPB NVIC_IPR16: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR17  -----------------------------------------\r
-#define PPB_NVIC_IPR17_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR17: PRI_0 Position      */\r
-#define PPB_NVIC_IPR17_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR17_PRI_0_Pos)                /*!< PPB NVIC_IPR17: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR17_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR17: PRI_1 Position      */\r
-#define PPB_NVIC_IPR17_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR17_PRI_1_Pos)                /*!< PPB NVIC_IPR17: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR17_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR17: PRI_2 Position      */\r
-#define PPB_NVIC_IPR17_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR17_PRI_2_Pos)                /*!< PPB NVIC_IPR17: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR17_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR17: PRI_3 Position      */\r
-#define PPB_NVIC_IPR17_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR17_PRI_3_Pos)                /*!< PPB NVIC_IPR17: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR18  -----------------------------------------\r
-#define PPB_NVIC_IPR18_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR18: PRI_0 Position      */\r
-#define PPB_NVIC_IPR18_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR18_PRI_0_Pos)                /*!< PPB NVIC_IPR18: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR18_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR18: PRI_1 Position      */\r
-#define PPB_NVIC_IPR18_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR18_PRI_1_Pos)                /*!< PPB NVIC_IPR18: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR18_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR18: PRI_2 Position      */\r
-#define PPB_NVIC_IPR18_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR18_PRI_2_Pos)                /*!< PPB NVIC_IPR18: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR18_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR18: PRI_3 Position      */\r
-#define PPB_NVIC_IPR18_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR18_PRI_3_Pos)                /*!< PPB NVIC_IPR18: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR19  -----------------------------------------\r
-#define PPB_NVIC_IPR19_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR19: PRI_0 Position      */\r
-#define PPB_NVIC_IPR19_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR19_PRI_0_Pos)                /*!< PPB NVIC_IPR19: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR19_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR19: PRI_1 Position      */\r
-#define PPB_NVIC_IPR19_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR19_PRI_1_Pos)                /*!< PPB NVIC_IPR19: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR19_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR19: PRI_2 Position      */\r
-#define PPB_NVIC_IPR19_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR19_PRI_2_Pos)                /*!< PPB NVIC_IPR19: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR19_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR19: PRI_3 Position      */\r
-#define PPB_NVIC_IPR19_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR19_PRI_3_Pos)                /*!< PPB NVIC_IPR19: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR20  -----------------------------------------\r
-#define PPB_NVIC_IPR20_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR20: PRI_0 Position      */\r
-#define PPB_NVIC_IPR20_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR20_PRI_0_Pos)                /*!< PPB NVIC_IPR20: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR20_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR20: PRI_1 Position      */\r
-#define PPB_NVIC_IPR20_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR20_PRI_1_Pos)                /*!< PPB NVIC_IPR20: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR20_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR20: PRI_2 Position      */\r
-#define PPB_NVIC_IPR20_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR20_PRI_2_Pos)                /*!< PPB NVIC_IPR20: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR20_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR20: PRI_3 Position      */\r
-#define PPB_NVIC_IPR20_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR20_PRI_3_Pos)                /*!< PPB NVIC_IPR20: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR21  -----------------------------------------\r
-#define PPB_NVIC_IPR21_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR21: PRI_0 Position      */\r
-#define PPB_NVIC_IPR21_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR21_PRI_0_Pos)                /*!< PPB NVIC_IPR21: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR21_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR21: PRI_1 Position      */\r
-#define PPB_NVIC_IPR21_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR21_PRI_1_Pos)                /*!< PPB NVIC_IPR21: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR21_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR21: PRI_2 Position      */\r
-#define PPB_NVIC_IPR21_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR21_PRI_2_Pos)                /*!< PPB NVIC_IPR21: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR21_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR21: PRI_3 Position      */\r
-#define PPB_NVIC_IPR21_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR21_PRI_3_Pos)                /*!< PPB NVIC_IPR21: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR22  -----------------------------------------\r
-#define PPB_NVIC_IPR22_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR22: PRI_0 Position      */\r
-#define PPB_NVIC_IPR22_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR22_PRI_0_Pos)                /*!< PPB NVIC_IPR22: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR22_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR22: PRI_1 Position      */\r
-#define PPB_NVIC_IPR22_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR22_PRI_1_Pos)                /*!< PPB NVIC_IPR22: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR22_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR22: PRI_2 Position      */\r
-#define PPB_NVIC_IPR22_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR22_PRI_2_Pos)                /*!< PPB NVIC_IPR22: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR22_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR22: PRI_3 Position      */\r
-#define PPB_NVIC_IPR22_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR22_PRI_3_Pos)                /*!< PPB NVIC_IPR22: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR23  -----------------------------------------\r
-#define PPB_NVIC_IPR23_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR23: PRI_0 Position      */\r
-#define PPB_NVIC_IPR23_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR23_PRI_0_Pos)                /*!< PPB NVIC_IPR23: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR23_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR23: PRI_1 Position      */\r
-#define PPB_NVIC_IPR23_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR23_PRI_1_Pos)                /*!< PPB NVIC_IPR23: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR23_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR23: PRI_2 Position      */\r
-#define PPB_NVIC_IPR23_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR23_PRI_2_Pos)                /*!< PPB NVIC_IPR23: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR23_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR23: PRI_3 Position      */\r
-#define PPB_NVIC_IPR23_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR23_PRI_3_Pos)                /*!< PPB NVIC_IPR23: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR24  -----------------------------------------\r
-#define PPB_NVIC_IPR24_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR24: PRI_0 Position      */\r
-#define PPB_NVIC_IPR24_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR24_PRI_0_Pos)                /*!< PPB NVIC_IPR24: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR24_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR24: PRI_1 Position      */\r
-#define PPB_NVIC_IPR24_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR24_PRI_1_Pos)                /*!< PPB NVIC_IPR24: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR24_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR24: PRI_2 Position      */\r
-#define PPB_NVIC_IPR24_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR24_PRI_2_Pos)                /*!< PPB NVIC_IPR24: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR24_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR24: PRI_3 Position      */\r
-#define PPB_NVIC_IPR24_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR24_PRI_3_Pos)                /*!< PPB NVIC_IPR24: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR25  -----------------------------------------\r
-#define PPB_NVIC_IPR25_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR25: PRI_0 Position      */\r
-#define PPB_NVIC_IPR25_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR25_PRI_0_Pos)                /*!< PPB NVIC_IPR25: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR25_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR25: PRI_1 Position      */\r
-#define PPB_NVIC_IPR25_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR25_PRI_1_Pos)                /*!< PPB NVIC_IPR25: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR25_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR25: PRI_2 Position      */\r
-#define PPB_NVIC_IPR25_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR25_PRI_2_Pos)                /*!< PPB NVIC_IPR25: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR25_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR25: PRI_3 Position      */\r
-#define PPB_NVIC_IPR25_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR25_PRI_3_Pos)                /*!< PPB NVIC_IPR25: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR26  -----------------------------------------\r
-#define PPB_NVIC_IPR26_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR26: PRI_0 Position      */\r
-#define PPB_NVIC_IPR26_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR26_PRI_0_Pos)                /*!< PPB NVIC_IPR26: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR26_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR26: PRI_1 Position      */\r
-#define PPB_NVIC_IPR26_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR26_PRI_1_Pos)                /*!< PPB NVIC_IPR26: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR26_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR26: PRI_2 Position      */\r
-#define PPB_NVIC_IPR26_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR26_PRI_2_Pos)                /*!< PPB NVIC_IPR26: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR26_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR26: PRI_3 Position      */\r
-#define PPB_NVIC_IPR26_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR26_PRI_3_Pos)                /*!< PPB NVIC_IPR26: PRI_3 Mask          */\r
-\r
-// -------------------------------------  PPB_NVIC_IPR27  -----------------------------------------\r
-#define PPB_NVIC_IPR27_PRI_0_Pos                              0                                                         /*!< PPB NVIC_IPR27: PRI_0 Position      */\r
-#define PPB_NVIC_IPR27_PRI_0_Msk                              (0x000000ffUL << PPB_NVIC_IPR27_PRI_0_Pos)                /*!< PPB NVIC_IPR27: PRI_0 Mask          */\r
-#define PPB_NVIC_IPR27_PRI_1_Pos                              8                                                         /*!< PPB NVIC_IPR27: PRI_1 Position      */\r
-#define PPB_NVIC_IPR27_PRI_1_Msk                              (0x000000ffUL << PPB_NVIC_IPR27_PRI_1_Pos)                /*!< PPB NVIC_IPR27: PRI_1 Mask          */\r
-#define PPB_NVIC_IPR27_PRI_2_Pos                              16                                                        /*!< PPB NVIC_IPR27: PRI_2 Position      */\r
-#define PPB_NVIC_IPR27_PRI_2_Msk                              (0x000000ffUL << PPB_NVIC_IPR27_PRI_2_Pos)                /*!< PPB NVIC_IPR27: PRI_2 Mask          */\r
-#define PPB_NVIC_IPR27_PRI_3_Pos                              24                                                        /*!< PPB NVIC_IPR27: PRI_3 Position      */\r
-#define PPB_NVIC_IPR27_PRI_3_Msk                              (0x000000ffUL << PPB_NVIC_IPR27_PRI_3_Pos)                /*!< PPB NVIC_IPR27: PRI_3 Mask          */\r
-\r
-// ----------------------------------------  PPB_CPUID  -------------------------------------------\r
-#define PPB_CPUID_Revision_Pos                                0                                                         /*!< PPB CPUID: Revision Position        */\r
-#define PPB_CPUID_Revision_Msk                                (0x0fUL << PPB_CPUID_Revision_Pos)                        /*!< PPB CPUID: Revision Mask            */\r
-#define PPB_CPUID_PartNo_Pos                                  4                                                         /*!< PPB CPUID: PartNo Position          */\r
-#define PPB_CPUID_PartNo_Msk                                  (0x00000fffUL << PPB_CPUID_PartNo_Pos)                    /*!< PPB CPUID: PartNo Mask              */\r
-#define PPB_CPUID_Constant_Pos                                16                                                        /*!< PPB CPUID: Constant Position        */\r
-#define PPB_CPUID_Constant_Msk                                (0x0fUL << PPB_CPUID_Constant_Pos)                        /*!< PPB CPUID: Constant Mask            */\r
-#define PPB_CPUID_Variant_Pos                                 20                                                        /*!< PPB CPUID: Variant Position         */\r
-#define PPB_CPUID_Variant_Msk                                 (0x0fUL << PPB_CPUID_Variant_Pos)                         /*!< PPB CPUID: Variant Mask             */\r
-#define PPB_CPUID_Implementer_Pos                             24                                                        /*!< PPB CPUID: Implementer Position     */\r
-#define PPB_CPUID_Implementer_Msk                             (0x000000ffUL << PPB_CPUID_Implementer_Pos)               /*!< PPB CPUID: Implementer Mask         */\r
-\r
-// ----------------------------------------  PPB_ICSR  --------------------------------------------\r
-#define PPB_ICSR_VECTACTIVE_Pos                               0                                                         /*!< PPB ICSR: VECTACTIVE Position       */\r
-#define PPB_ICSR_VECTACTIVE_Msk                               (0x000001ffUL << PPB_ICSR_VECTACTIVE_Pos)                 /*!< PPB ICSR: VECTACTIVE Mask           */\r
-#define PPB_ICSR_RETTOBASE_Pos                                11                                                        /*!< PPB ICSR: RETTOBASE Position        */\r
-#define PPB_ICSR_RETTOBASE_Msk                                (0x01UL << PPB_ICSR_RETTOBASE_Pos)                        /*!< PPB ICSR: RETTOBASE Mask            */\r
-#define PPB_ICSR_VECTPENDING_Pos                              12                                                        /*!< PPB ICSR: VECTPENDING Position      */\r
-#define PPB_ICSR_VECTPENDING_Msk                              (0x3fUL << PPB_ICSR_VECTPENDING_Pos)                      /*!< PPB ICSR: VECTPENDING Mask          */\r
-#define PPB_ICSR_ISRPENDING_Pos                               22                                                        /*!< PPB ICSR: ISRPENDING Position       */\r
-#define PPB_ICSR_ISRPENDING_Msk                               (0x01UL << PPB_ICSR_ISRPENDING_Pos)                       /*!< PPB ICSR: ISRPENDING Mask           */\r
-#define PPB_ICSR_Res_Pos                                      23                                                        /*!< PPB ICSR: Res Position              */\r
-#define PPB_ICSR_Res_Msk                                      (0x01UL << PPB_ICSR_Res_Pos)                              /*!< PPB ICSR: Res Mask                  */\r
-#define PPB_ICSR_PENDSTCLR_Pos                                25                                                        /*!< PPB ICSR: PENDSTCLR Position        */\r
-#define PPB_ICSR_PENDSTCLR_Msk                                (0x01UL << PPB_ICSR_PENDSTCLR_Pos)                        /*!< PPB ICSR: PENDSTCLR Mask            */\r
-#define PPB_ICSR_PENDSTSET_Pos                                26                                                        /*!< PPB ICSR: PENDSTSET Position        */\r
-#define PPB_ICSR_PENDSTSET_Msk                                (0x01UL << PPB_ICSR_PENDSTSET_Pos)                        /*!< PPB ICSR: PENDSTSET Mask            */\r
-#define PPB_ICSR_PENDSVCLR_Pos                                27                                                        /*!< PPB ICSR: PENDSVCLR Position        */\r
-#define PPB_ICSR_PENDSVCLR_Msk                                (0x01UL << PPB_ICSR_PENDSVCLR_Pos)                        /*!< PPB ICSR: PENDSVCLR Mask            */\r
-#define PPB_ICSR_PENDSVSET_Pos                                28                                                        /*!< PPB ICSR: PENDSVSET Position        */\r
-#define PPB_ICSR_PENDSVSET_Msk                                (0x01UL << PPB_ICSR_PENDSVSET_Pos)                        /*!< PPB ICSR: PENDSVSET Mask            */\r
-#define PPB_ICSR_NMIPENDSET_Pos                               31                                                        /*!< PPB ICSR: NMIPENDSET Position       */\r
-#define PPB_ICSR_NMIPENDSET_Msk                               (0x01UL << PPB_ICSR_NMIPENDSET_Pos)                       /*!< PPB ICSR: NMIPENDSET Mask           */\r
-\r
-// ----------------------------------------  PPB_VTOR  --------------------------------------------\r
-#define PPB_VTOR_TBLOFF_Pos                                   8                                                         /*!< PPB VTOR: TBLOFF Position           */\r
-#define PPB_VTOR_TBLOFF_Msk                                   (0x00ffffffUL << PPB_VTOR_TBLOFF_Pos)                     /*!< PPB VTOR: TBLOFF Mask               */\r
-\r
-// ----------------------------------------  PPB_AIRCR  -------------------------------------------\r
-#define PPB_AIRCR_VECTRESET_Pos                               0                                                         /*!< PPB AIRCR: VECTRESET Position       */\r
-#define PPB_AIRCR_VECTRESET_Msk                               (0x01UL << PPB_AIRCR_VECTRESET_Pos)                       /*!< PPB AIRCR: VECTRESET Mask           */\r
-#define PPB_AIRCR_VECTCLRACTIVE_Pos                           1                                                         /*!< PPB AIRCR: VECTCLRACTIVE Position   */\r
-#define PPB_AIRCR_VECTCLRACTIVE_Msk                           (0x01UL << PPB_AIRCR_VECTCLRACTIVE_Pos)                   /*!< PPB AIRCR: VECTCLRACTIVE Mask       */\r
-#define PPB_AIRCR_SYSRESETREQ_Pos                             2                                                         /*!< PPB AIRCR: SYSRESETREQ Position     */\r
-#define PPB_AIRCR_SYSRESETREQ_Msk                             (0x01UL << PPB_AIRCR_SYSRESETREQ_Pos)                     /*!< PPB AIRCR: SYSRESETREQ Mask         */\r
-#define PPB_AIRCR_PRIGROUP_Pos                                8                                                         /*!< PPB AIRCR: PRIGROUP Position        */\r
-#define PPB_AIRCR_PRIGROUP_Msk                                (0x07UL << PPB_AIRCR_PRIGROUP_Pos)                        /*!< PPB AIRCR: PRIGROUP Mask            */\r
-#define PPB_AIRCR_ENDIANNESS_Pos                              15                                                        /*!< PPB AIRCR: ENDIANNESS Position      */\r
-#define PPB_AIRCR_ENDIANNESS_Msk                              (0x01UL << PPB_AIRCR_ENDIANNESS_Pos)                      /*!< PPB AIRCR: ENDIANNESS Mask          */\r
-#define PPB_AIRCR_VECTKEY_Pos                                 16                                                        /*!< PPB AIRCR: VECTKEY Position         */\r
-#define PPB_AIRCR_VECTKEY_Msk                                 (0x0000ffffUL << PPB_AIRCR_VECTKEY_Pos)                   /*!< PPB AIRCR: VECTKEY Mask             */\r
-\r
-// -----------------------------------------  PPB_SCR  --------------------------------------------\r
-#define PPB_SCR_SLEEPONEXIT_Pos                               1                                                         /*!< PPB SCR: SLEEPONEXIT Position       */\r
-#define PPB_SCR_SLEEPONEXIT_Msk                               (0x01UL << PPB_SCR_SLEEPONEXIT_Pos)                       /*!< PPB SCR: SLEEPONEXIT Mask           */\r
-#define PPB_SCR_SLEEPDEEP_Pos                                 2                                                         /*!< PPB SCR: SLEEPDEEP Position         */\r
-#define PPB_SCR_SLEEPDEEP_Msk                                 (0x01UL << PPB_SCR_SLEEPDEEP_Pos)                         /*!< PPB SCR: SLEEPDEEP Mask             */\r
-#define PPB_SCR_SEVONPEND_Pos                                 4                                                         /*!< PPB SCR: SEVONPEND Position         */\r
-#define PPB_SCR_SEVONPEND_Msk                                 (0x01UL << PPB_SCR_SEVONPEND_Pos)                         /*!< PPB SCR: SEVONPEND Mask             */\r
-\r
-// -----------------------------------------  PPB_CCR  --------------------------------------------\r
-#define PPB_CCR_NONBASETHRDENA_Pos                            0                                                         /*!< PPB CCR: NONBASETHRDENA Position    */\r
-#define PPB_CCR_NONBASETHRDENA_Msk                            (0x01UL << PPB_CCR_NONBASETHRDENA_Pos)                    /*!< PPB CCR: NONBASETHRDENA Mask        */\r
-#define PPB_CCR_USERSETMPEND_Pos                              1                                                         /*!< PPB CCR: USERSETMPEND Position      */\r
-#define PPB_CCR_USERSETMPEND_Msk                              (0x01UL << PPB_CCR_USERSETMPEND_Pos)                      /*!< PPB CCR: USERSETMPEND Mask          */\r
-#define PPB_CCR_UNALIGN_TRP_Pos                               3                                                         /*!< PPB CCR: UNALIGN_TRP Position       */\r
-#define PPB_CCR_UNALIGN_TRP_Msk                               (0x01UL << PPB_CCR_UNALIGN_TRP_Pos)                       /*!< PPB CCR: UNALIGN_TRP Mask           */\r
-#define PPB_CCR_DIV_0_TRP_Pos                                 4                                                         /*!< PPB CCR: DIV_0_TRP Position         */\r
-#define PPB_CCR_DIV_0_TRP_Msk                                 (0x01UL << PPB_CCR_DIV_0_TRP_Pos)                         /*!< PPB CCR: DIV_0_TRP Mask             */\r
-#define PPB_CCR_BFHFNMIGN_Pos                                 8                                                         /*!< PPB CCR: BFHFNMIGN Position         */\r
-#define PPB_CCR_BFHFNMIGN_Msk                                 (0x01UL << PPB_CCR_BFHFNMIGN_Pos)                         /*!< PPB CCR: BFHFNMIGN Mask             */\r
-#define PPB_CCR_STKALIGN_Pos                                  9                                                         /*!< PPB CCR: STKALIGN Position          */\r
-#define PPB_CCR_STKALIGN_Msk                                  (0x01UL << PPB_CCR_STKALIGN_Pos)                          /*!< PPB CCR: STKALIGN Mask              */\r
-\r
-// ----------------------------------------  PPB_SHPR1  -------------------------------------------\r
-#define PPB_SHPR1_PRI_4_Pos                                   0                                                         /*!< PPB SHPR1: PRI_4 Position           */\r
-#define PPB_SHPR1_PRI_4_Msk                                   (0x000000ffUL << PPB_SHPR1_PRI_4_Pos)                     /*!< PPB SHPR1: PRI_4 Mask               */\r
-#define PPB_SHPR1_PRI_5_Pos                                   8                                                         /*!< PPB SHPR1: PRI_5 Position           */\r
-#define PPB_SHPR1_PRI_5_Msk                                   (0x000000ffUL << PPB_SHPR1_PRI_5_Pos)                     /*!< PPB SHPR1: PRI_5 Mask               */\r
-#define PPB_SHPR1_PRI_6_Pos                                   16                                                        /*!< PPB SHPR1: PRI_6 Position           */\r
-#define PPB_SHPR1_PRI_6_Msk                                   (0x000000ffUL << PPB_SHPR1_PRI_6_Pos)                     /*!< PPB SHPR1: PRI_6 Mask               */\r
-\r
-// ----------------------------------------  PPB_SHPR2  -------------------------------------------\r
-#define PPB_SHPR2_PRI_11_Pos                                  24                                                        /*!< PPB SHPR2: PRI_11 Position          */\r
-#define PPB_SHPR2_PRI_11_Msk                                  (0x000000ffUL << PPB_SHPR2_PRI_11_Pos)                    /*!< PPB SHPR2: PRI_11 Mask              */\r
-\r
-// ----------------------------------------  PPB_SHPR3  -------------------------------------------\r
-#define PPB_SHPR3_PRI_14_Pos                                  16                                                        /*!< PPB SHPR3: PRI_14 Position          */\r
-#define PPB_SHPR3_PRI_14_Msk                                  (0x000000ffUL << PPB_SHPR3_PRI_14_Pos)                    /*!< PPB SHPR3: PRI_14 Mask              */\r
-#define PPB_SHPR3_PRI_15_Pos                                  24                                                        /*!< PPB SHPR3: PRI_15 Position          */\r
-#define PPB_SHPR3_PRI_15_Msk                                  (0x000000ffUL << PPB_SHPR3_PRI_15_Pos)                    /*!< PPB SHPR3: PRI_15 Mask              */\r
-\r
-// ----------------------------------------  PPB_SHCSR  -------------------------------------------\r
-#define PPB_SHCSR_MEMFAULTACT_Pos                             0                                                         /*!< PPB SHCSR: MEMFAULTACT Position     */\r
-#define PPB_SHCSR_MEMFAULTACT_Msk                             (0x01UL << PPB_SHCSR_MEMFAULTACT_Pos)                     /*!< PPB SHCSR: MEMFAULTACT Mask         */\r
-#define PPB_SHCSR_BUSFAULTACT_Pos                             1                                                         /*!< PPB SHCSR: BUSFAULTACT Position     */\r
-#define PPB_SHCSR_BUSFAULTACT_Msk                             (0x01UL << PPB_SHCSR_BUSFAULTACT_Pos)                     /*!< PPB SHCSR: BUSFAULTACT Mask         */\r
-#define PPB_SHCSR_USGFAULTACT_Pos                             3                                                         /*!< PPB SHCSR: USGFAULTACT Position     */\r
-#define PPB_SHCSR_USGFAULTACT_Msk                             (0x01UL << PPB_SHCSR_USGFAULTACT_Pos)                     /*!< PPB SHCSR: USGFAULTACT Mask         */\r
-#define PPB_SHCSR_SVCALLACT_Pos                               7                                                         /*!< PPB SHCSR: SVCALLACT Position       */\r
-#define PPB_SHCSR_SVCALLACT_Msk                               (0x01UL << PPB_SHCSR_SVCALLACT_Pos)                       /*!< PPB SHCSR: SVCALLACT Mask           */\r
-#define PPB_SHCSR_MONITORACT_Pos                              8                                                         /*!< PPB SHCSR: MONITORACT Position      */\r
-#define PPB_SHCSR_MONITORACT_Msk                              (0x01UL << PPB_SHCSR_MONITORACT_Pos)                      /*!< PPB SHCSR: MONITORACT Mask          */\r
-#define PPB_SHCSR_PENDSVACT_Pos                               10                                                        /*!< PPB SHCSR: PENDSVACT Position       */\r
-#define PPB_SHCSR_PENDSVACT_Msk                               (0x01UL << PPB_SHCSR_PENDSVACT_Pos)                       /*!< PPB SHCSR: PENDSVACT Mask           */\r
-#define PPB_SHCSR_SYSTICKACT_Pos                              11                                                        /*!< PPB SHCSR: SYSTICKACT Position      */\r
-#define PPB_SHCSR_SYSTICKACT_Msk                              (0x01UL << PPB_SHCSR_SYSTICKACT_Pos)                      /*!< PPB SHCSR: SYSTICKACT Mask          */\r
-#define PPB_SHCSR_USGFAULTPENDED_Pos                          12                                                        /*!< PPB SHCSR: USGFAULTPENDED Position  */\r
-#define PPB_SHCSR_USGFAULTPENDED_Msk                          (0x01UL << PPB_SHCSR_USGFAULTPENDED_Pos)                  /*!< PPB SHCSR: USGFAULTPENDED Mask      */\r
-#define PPB_SHCSR_MEMFAULTPENDED_Pos                          13                                                        /*!< PPB SHCSR: MEMFAULTPENDED Position  */\r
-#define PPB_SHCSR_MEMFAULTPENDED_Msk                          (0x01UL << PPB_SHCSR_MEMFAULTPENDED_Pos)                  /*!< PPB SHCSR: MEMFAULTPENDED Mask      */\r
-#define PPB_SHCSR_BUSFAULTPENDED_Pos                          14                                                        /*!< PPB SHCSR: BUSFAULTPENDED Position  */\r
-#define PPB_SHCSR_BUSFAULTPENDED_Msk                          (0x01UL << PPB_SHCSR_BUSFAULTPENDED_Pos)                  /*!< PPB SHCSR: BUSFAULTPENDED Mask      */\r
-#define PPB_SHCSR_SVCALLPENDED_Pos                            15                                                        /*!< PPB SHCSR: SVCALLPENDED Position    */\r
-#define PPB_SHCSR_SVCALLPENDED_Msk                            (0x01UL << PPB_SHCSR_SVCALLPENDED_Pos)                    /*!< PPB SHCSR: SVCALLPENDED Mask        */\r
-#define PPB_SHCSR_MEMFAULTENA_Pos                             16                                                        /*!< PPB SHCSR: MEMFAULTENA Position     */\r
-#define PPB_SHCSR_MEMFAULTENA_Msk                             (0x01UL << PPB_SHCSR_MEMFAULTENA_Pos)                     /*!< PPB SHCSR: MEMFAULTENA Mask         */\r
-#define PPB_SHCSR_BUSFAULTENA_Pos                             17                                                        /*!< PPB SHCSR: BUSFAULTENA Position     */\r
-#define PPB_SHCSR_BUSFAULTENA_Msk                             (0x01UL << PPB_SHCSR_BUSFAULTENA_Pos)                     /*!< PPB SHCSR: BUSFAULTENA Mask         */\r
-#define PPB_SHCSR_USGFAULTENA_Pos                             18                                                        /*!< PPB SHCSR: USGFAULTENA Position     */\r
-#define PPB_SHCSR_USGFAULTENA_Msk                             (0x01UL << PPB_SHCSR_USGFAULTENA_Pos)                     /*!< PPB SHCSR: USGFAULTENA Mask         */\r
-\r
-// ----------------------------------------  PPB_CFSR  --------------------------------------------\r
-#define PPB_CFSR_IACCVIOL_Pos                                 0                                                         /*!< PPB CFSR: IACCVIOL Position         */\r
-#define PPB_CFSR_IACCVIOL_Msk                                 (0x01UL << PPB_CFSR_IACCVIOL_Pos)                         /*!< PPB CFSR: IACCVIOL Mask             */\r
-#define PPB_CFSR_DACCVIOL_Pos                                 1                                                         /*!< PPB CFSR: DACCVIOL Position         */\r
-#define PPB_CFSR_DACCVIOL_Msk                                 (0x01UL << PPB_CFSR_DACCVIOL_Pos)                         /*!< PPB CFSR: DACCVIOL Mask             */\r
-#define PPB_CFSR_MUNSTKERR_Pos                                3                                                         /*!< PPB CFSR: MUNSTKERR Position        */\r
-#define PPB_CFSR_MUNSTKERR_Msk                                (0x01UL << PPB_CFSR_MUNSTKERR_Pos)                        /*!< PPB CFSR: MUNSTKERR Mask            */\r
-#define PPB_CFSR_MSTKERR_Pos                                  4                                                         /*!< PPB CFSR: MSTKERR Position          */\r
-#define PPB_CFSR_MSTKERR_Msk                                  (0x01UL << PPB_CFSR_MSTKERR_Pos)                          /*!< PPB CFSR: MSTKERR Mask              */\r
-#define PPB_CFSR_MLSPERR_Pos                                  5                                                         /*!< PPB CFSR: MLSPERR Position          */\r
-#define PPB_CFSR_MLSPERR_Msk                                  (0x01UL << PPB_CFSR_MLSPERR_Pos)                          /*!< PPB CFSR: MLSPERR Mask              */\r
-#define PPB_CFSR_MMARVALID_Pos                                7                                                         /*!< PPB CFSR: MMARVALID Position        */\r
-#define PPB_CFSR_MMARVALID_Msk                                (0x01UL << PPB_CFSR_MMARVALID_Pos)                        /*!< PPB CFSR: MMARVALID Mask            */\r
-#define PPB_CFSR_IBUSERR_Pos                                  8                                                         /*!< PPB CFSR: IBUSERR Position          */\r
-#define PPB_CFSR_IBUSERR_Msk                                  (0x01UL << PPB_CFSR_IBUSERR_Pos)                          /*!< PPB CFSR: IBUSERR Mask              */\r
-#define PPB_CFSR_PRECISERR_Pos                                9                                                         /*!< PPB CFSR: PRECISERR Position        */\r
-#define PPB_CFSR_PRECISERR_Msk                                (0x01UL << PPB_CFSR_PRECISERR_Pos)                        /*!< PPB CFSR: PRECISERR Mask            */\r
-#define PPB_CFSR_IMPRECISERR_Pos                              10                                                        /*!< PPB CFSR: IMPRECISERR Position      */\r
-#define PPB_CFSR_IMPRECISERR_Msk                              (0x01UL << PPB_CFSR_IMPRECISERR_Pos)                      /*!< PPB CFSR: IMPRECISERR Mask          */\r
-#define PPB_CFSR_UNSTKERR_Pos                                 11                                                        /*!< PPB CFSR: UNSTKERR Position         */\r
-#define PPB_CFSR_UNSTKERR_Msk                                 (0x01UL << PPB_CFSR_UNSTKERR_Pos)                         /*!< PPB CFSR: UNSTKERR Mask             */\r
-#define PPB_CFSR_STKERR_Pos                                   12                                                        /*!< PPB CFSR: STKERR Position           */\r
-#define PPB_CFSR_STKERR_Msk                                   (0x01UL << PPB_CFSR_STKERR_Pos)                           /*!< PPB CFSR: STKERR Mask               */\r
-#define PPB_CFSR_LSPERR_Pos                                   13                                                        /*!< PPB CFSR: LSPERR Position           */\r
-#define PPB_CFSR_LSPERR_Msk                                   (0x01UL << PPB_CFSR_LSPERR_Pos)                           /*!< PPB CFSR: LSPERR Mask               */\r
-#define PPB_CFSR_BFARVALID_Pos                                15                                                        /*!< PPB CFSR: BFARVALID Position        */\r
-#define PPB_CFSR_BFARVALID_Msk                                (0x01UL << PPB_CFSR_BFARVALID_Pos)                        /*!< PPB CFSR: BFARVALID Mask            */\r
-#define PPB_CFSR_UNDEFINSTR_Pos                               16                                                        /*!< PPB CFSR: UNDEFINSTR Position       */\r
-#define PPB_CFSR_UNDEFINSTR_Msk                               (0x01UL << PPB_CFSR_UNDEFINSTR_Pos)                       /*!< PPB CFSR: UNDEFINSTR Mask           */\r
-#define PPB_CFSR_INVSTATE_Pos                                 17                                                        /*!< PPB CFSR: INVSTATE Position         */\r
-#define PPB_CFSR_INVSTATE_Msk                                 (0x01UL << PPB_CFSR_INVSTATE_Pos)                         /*!< PPB CFSR: INVSTATE Mask             */\r
-#define PPB_CFSR_INVPC_Pos                                    18                                                        /*!< PPB CFSR: INVPC Position            */\r
-#define PPB_CFSR_INVPC_Msk                                    (0x01UL << PPB_CFSR_INVPC_Pos)                            /*!< PPB CFSR: INVPC Mask                */\r
-#define PPB_CFSR_NOCP_Pos                                     19                                                        /*!< PPB CFSR: NOCP Position             */\r
-#define PPB_CFSR_NOCP_Msk                                     (0x01UL << PPB_CFSR_NOCP_Pos)                             /*!< PPB CFSR: NOCP Mask                 */\r
-#define PPB_CFSR_UNALIGNED_Pos                                24                                                        /*!< PPB CFSR: UNALIGNED Position        */\r
-#define PPB_CFSR_UNALIGNED_Msk                                (0x01UL << PPB_CFSR_UNALIGNED_Pos)                        /*!< PPB CFSR: UNALIGNED Mask            */\r
-#define PPB_CFSR_DIVBYZERO_Pos                                25                                                        /*!< PPB CFSR: DIVBYZERO Position        */\r
-#define PPB_CFSR_DIVBYZERO_Msk                                (0x01UL << PPB_CFSR_DIVBYZERO_Pos)                        /*!< PPB CFSR: DIVBYZERO Mask            */\r
-\r
-// ----------------------------------------  PPB_HFSR  --------------------------------------------\r
-#define PPB_HFSR_VECTTBL_Pos                                  1                                                         /*!< PPB HFSR: VECTTBL Position          */\r
-#define PPB_HFSR_VECTTBL_Msk                                  (0x01UL << PPB_HFSR_VECTTBL_Pos)                          /*!< PPB HFSR: VECTTBL Mask              */\r
-#define PPB_HFSR_FORCED_Pos                                   30                                                        /*!< PPB HFSR: FORCED Position           */\r
-#define PPB_HFSR_FORCED_Msk                                   (0x01UL << PPB_HFSR_FORCED_Pos)                           /*!< PPB HFSR: FORCED Mask               */\r
-#define PPB_HFSR_DEBUGEVT_Pos                                 31                                                        /*!< PPB HFSR: DEBUGEVT Position         */\r
-#define PPB_HFSR_DEBUGEVT_Msk                                 (0x01UL << PPB_HFSR_DEBUGEVT_Pos)                         /*!< PPB HFSR: DEBUGEVT Mask             */\r
-\r
-// ----------------------------------------  PPB_MMFAR  -------------------------------------------\r
-#define PPB_MMFAR_ADDRESS_Pos                                 0                                                         /*!< PPB MMFAR: ADDRESS Position         */\r
-#define PPB_MMFAR_ADDRESS_Msk                                 (0xffffffffUL << PPB_MMFAR_ADDRESS_Pos)                   /*!< PPB MMFAR: ADDRESS Mask             */\r
-\r
-// ----------------------------------------  PPB_BFAR  --------------------------------------------\r
-#define PPB_BFAR_ADDRESS_Pos                                  0                                                         /*!< PPB BFAR: ADDRESS Position          */\r
-#define PPB_BFAR_ADDRESS_Msk                                  (0xffffffffUL << PPB_BFAR_ADDRESS_Pos)                    /*!< PPB BFAR: ADDRESS Mask              */\r
-\r
-// ----------------------------------------  PPB_AFSR  --------------------------------------------\r
-#define PPB_AFSR_VALUE_Pos                                    0                                                         /*!< PPB AFSR: VALUE Position            */\r
-#define PPB_AFSR_VALUE_Msk                                    (0xffffffffUL << PPB_AFSR_VALUE_Pos)                      /*!< PPB AFSR: VALUE Mask                */\r
-\r
-// ----------------------------------------  PPB_CPACR  -------------------------------------------\r
-#define PPB_CPACR_CP10_Pos                                    20                                                        /*!< PPB CPACR: CP10 Position            */\r
-#define PPB_CPACR_CP10_Msk                                    (0x03UL << PPB_CPACR_CP10_Pos)                            /*!< PPB CPACR: CP10 Mask                */\r
-#define PPB_CPACR_CP11_Pos                                    22                                                        /*!< PPB CPACR: CP11 Position            */\r
-#define PPB_CPACR_CP11_Msk                                    (0x03UL << PPB_CPACR_CP11_Pos)                            /*!< PPB CPACR: CP11 Mask                */\r
-\r
-// --------------------------------------  PPB_MPU_TYPE  ------------------------------------------\r
-#define PPB_MPU_TYPE_SEPARATE_Pos                             0                                                         /*!< PPB MPU_TYPE: SEPARATE Position     */\r
-#define PPB_MPU_TYPE_SEPARATE_Msk                             (0x01UL << PPB_MPU_TYPE_SEPARATE_Pos)                     /*!< PPB MPU_TYPE: SEPARATE Mask         */\r
-#define PPB_MPU_TYPE_DREGION_Pos                              8                                                         /*!< PPB MPU_TYPE: DREGION Position      */\r
-#define PPB_MPU_TYPE_DREGION_Msk                              (0x000000ffUL << PPB_MPU_TYPE_DREGION_Pos)                /*!< PPB MPU_TYPE: DREGION Mask          */\r
-#define PPB_MPU_TYPE_IREGION_Pos                              16                                                        /*!< PPB MPU_TYPE: IREGION Position      */\r
-#define PPB_MPU_TYPE_IREGION_Msk                              (0x000000ffUL << PPB_MPU_TYPE_IREGION_Pos)                /*!< PPB MPU_TYPE: IREGION Mask          */\r
-\r
-// --------------------------------------  PPB_MPU_CTRL  ------------------------------------------\r
-#define PPB_MPU_CTRL_ENABLE_Pos                               0                                                         /*!< PPB MPU_CTRL: ENABLE Position       */\r
-#define PPB_MPU_CTRL_ENABLE_Msk                               (0x01UL << PPB_MPU_CTRL_ENABLE_Pos)                       /*!< PPB MPU_CTRL: ENABLE Mask           */\r
-#define PPB_MPU_CTRL_HFNMIENA_Pos                             1                                                         /*!< PPB MPU_CTRL: HFNMIENA Position     */\r
-#define PPB_MPU_CTRL_HFNMIENA_Msk                             (0x01UL << PPB_MPU_CTRL_HFNMIENA_Pos)                     /*!< PPB MPU_CTRL: HFNMIENA Mask         */\r
-#define PPB_MPU_CTRL_PRIVDEFENA_Pos                           2                                                         /*!< PPB MPU_CTRL: PRIVDEFENA Position   */\r
-#define PPB_MPU_CTRL_PRIVDEFENA_Msk                           (0x01UL << PPB_MPU_CTRL_PRIVDEFENA_Pos)                   /*!< PPB MPU_CTRL: PRIVDEFENA Mask       */\r
-\r
-// ---------------------------------------  PPB_MPU_RNR  ------------------------------------------\r
-#define PPB_MPU_RNR_REGION_Pos                                0                                                         /*!< PPB MPU_RNR: REGION Position        */\r
-#define PPB_MPU_RNR_REGION_Msk                                (0x000000ffUL << PPB_MPU_RNR_REGION_Pos)                  /*!< PPB MPU_RNR: REGION Mask            */\r
-\r
-// --------------------------------------  PPB_MPU_RBAR  ------------------------------------------\r
-#define PPB_MPU_RBAR_REGION_Pos                               0                                                         /*!< PPB MPU_RBAR: REGION Position       */\r
-#define PPB_MPU_RBAR_REGION_Msk                               (0x0fUL << PPB_MPU_RBAR_REGION_Pos)                       /*!< PPB MPU_RBAR: REGION Mask           */\r
-#define PPB_MPU_RBAR_VALID_Pos                                4                                                         /*!< PPB MPU_RBAR: VALID Position        */\r
-#define PPB_MPU_RBAR_VALID_Msk                                (0x01UL << PPB_MPU_RBAR_VALID_Pos)                        /*!< PPB MPU_RBAR: VALID Mask            */\r
-#define PPB_MPU_RBAR_ADDR_Pos                                 9                                                         /*!< PPB MPU_RBAR: ADDR Position         */\r
-#define PPB_MPU_RBAR_ADDR_Msk                                 (0x007fffffUL << PPB_MPU_RBAR_ADDR_Pos)                   /*!< PPB MPU_RBAR: ADDR Mask             */\r
-\r
-// --------------------------------------  PPB_MPU_RASR  ------------------------------------------\r
-#define PPB_MPU_RASR_ENABLE_Pos                               0                                                         /*!< PPB MPU_RASR: ENABLE Position       */\r
-#define PPB_MPU_RASR_ENABLE_Msk                               (0x01UL << PPB_MPU_RASR_ENABLE_Pos)                       /*!< PPB MPU_RASR: ENABLE Mask           */\r
-#define PPB_MPU_RASR_SIZE_Pos                                 1                                                         /*!< PPB MPU_RASR: SIZE Position         */\r
-#define PPB_MPU_RASR_SIZE_Msk                                 (0x1fUL << PPB_MPU_RASR_SIZE_Pos)                         /*!< PPB MPU_RASR: SIZE Mask             */\r
-#define PPB_MPU_RASR_SRD_Pos                                  8                                                         /*!< PPB MPU_RASR: SRD Position          */\r
-#define PPB_MPU_RASR_SRD_Msk                                  (0x000000ffUL << PPB_MPU_RASR_SRD_Pos)                    /*!< PPB MPU_RASR: SRD Mask              */\r
-#define PPB_MPU_RASR_B_Pos                                    16                                                        /*!< PPB MPU_RASR: B Position            */\r
-#define PPB_MPU_RASR_B_Msk                                    (0x01UL << PPB_MPU_RASR_B_Pos)                            /*!< PPB MPU_RASR: B Mask                */\r
-#define PPB_MPU_RASR_C_Pos                                    17                                                        /*!< PPB MPU_RASR: C Position            */\r
-#define PPB_MPU_RASR_C_Msk                                    (0x01UL << PPB_MPU_RASR_C_Pos)                            /*!< PPB MPU_RASR: C Mask                */\r
-#define PPB_MPU_RASR_S_Pos                                    18                                                        /*!< PPB MPU_RASR: S Position            */\r
-#define PPB_MPU_RASR_S_Msk                                    (0x01UL << PPB_MPU_RASR_S_Pos)                            /*!< PPB MPU_RASR: S Mask                */\r
-#define PPB_MPU_RASR_TEX_Pos                                  19                                                        /*!< PPB MPU_RASR: TEX Position          */\r
-#define PPB_MPU_RASR_TEX_Msk                                  (0x07UL << PPB_MPU_RASR_TEX_Pos)                          /*!< PPB MPU_RASR: TEX Mask              */\r
-#define PPB_MPU_RASR_AP_Pos                                   24                                                        /*!< PPB MPU_RASR: AP Position           */\r
-#define PPB_MPU_RASR_AP_Msk                                   (0x07UL << PPB_MPU_RASR_AP_Pos)                           /*!< PPB MPU_RASR: AP Mask               */\r
-#define PPB_MPU_RASR_XN_Pos                                   28                                                        /*!< PPB MPU_RASR: XN Position           */\r
-#define PPB_MPU_RASR_XN_Msk                                   (0x01UL << PPB_MPU_RASR_XN_Pos)                           /*!< PPB MPU_RASR: XN Mask               */\r
-\r
-// -------------------------------------  PPB_MPU_RBAR_A1  ----------------------------------------\r
-#define PPB_MPU_RBAR_A1_REGION_Pos                            0                                                         /*!< PPB MPU_RBAR_A1: REGION Position    */\r
-#define PPB_MPU_RBAR_A1_REGION_Msk                            (0x0fUL << PPB_MPU_RBAR_A1_REGION_Pos)                    /*!< PPB MPU_RBAR_A1: REGION Mask        */\r
-#define PPB_MPU_RBAR_A1_VALID_Pos                             4                                                         /*!< PPB MPU_RBAR_A1: VALID Position     */\r
-#define PPB_MPU_RBAR_A1_VALID_Msk                             (0x01UL << PPB_MPU_RBAR_A1_VALID_Pos)                     /*!< PPB MPU_RBAR_A1: VALID Mask         */\r
-#define PPB_MPU_RBAR_A1_ADDR_Pos                              9                                                         /*!< PPB MPU_RBAR_A1: ADDR Position      */\r
-#define PPB_MPU_RBAR_A1_ADDR_Msk                              (0x007fffffUL << PPB_MPU_RBAR_A1_ADDR_Pos)                /*!< PPB MPU_RBAR_A1: ADDR Mask          */\r
-\r
-// -------------------------------------  PPB_MPU_RASR_A1  ----------------------------------------\r
-#define PPB_MPU_RASR_A1_ENABLE_Pos                            0                                                         /*!< PPB MPU_RASR_A1: ENABLE Position    */\r
-#define PPB_MPU_RASR_A1_ENABLE_Msk                            (0x01UL << PPB_MPU_RASR_A1_ENABLE_Pos)                    /*!< PPB MPU_RASR_A1: ENABLE Mask        */\r
-#define PPB_MPU_RASR_A1_SIZE_Pos                              1                                                         /*!< PPB MPU_RASR_A1: SIZE Position      */\r
-#define PPB_MPU_RASR_A1_SIZE_Msk                              (0x1fUL << PPB_MPU_RASR_A1_SIZE_Pos)                      /*!< PPB MPU_RASR_A1: SIZE Mask          */\r
-#define PPB_MPU_RASR_A1_SRD_Pos                               8                                                         /*!< PPB MPU_RASR_A1: SRD Position       */\r
-#define PPB_MPU_RASR_A1_SRD_Msk                               (0x000000ffUL << PPB_MPU_RASR_A1_SRD_Pos)                 /*!< PPB MPU_RASR_A1: SRD Mask           */\r
-#define PPB_MPU_RASR_A1_B_Pos                                 16                                                        /*!< PPB MPU_RASR_A1: B Position         */\r
-#define PPB_MPU_RASR_A1_B_Msk                                 (0x01UL << PPB_MPU_RASR_A1_B_Pos)                         /*!< PPB MPU_RASR_A1: B Mask             */\r
-#define PPB_MPU_RASR_A1_C_Pos                                 17                                                        /*!< PPB MPU_RASR_A1: C Position         */\r
-#define PPB_MPU_RASR_A1_C_Msk                                 (0x01UL << PPB_MPU_RASR_A1_C_Pos)                         /*!< PPB MPU_RASR_A1: C Mask             */\r
-#define PPB_MPU_RASR_A1_S_Pos                                 18                                                        /*!< PPB MPU_RASR_A1: S Position         */\r
-#define PPB_MPU_RASR_A1_S_Msk                                 (0x01UL << PPB_MPU_RASR_A1_S_Pos)                         /*!< PPB MPU_RASR_A1: S Mask             */\r
-#define PPB_MPU_RASR_A1_TEX_Pos                               19                                                        /*!< PPB MPU_RASR_A1: TEX Position       */\r
-#define PPB_MPU_RASR_A1_TEX_Msk                               (0x07UL << PPB_MPU_RASR_A1_TEX_Pos)                       /*!< PPB MPU_RASR_A1: TEX Mask           */\r
-#define PPB_MPU_RASR_A1_AP_Pos                                24                                                        /*!< PPB MPU_RASR_A1: AP Position        */\r
-#define PPB_MPU_RASR_A1_AP_Msk                                (0x07UL << PPB_MPU_RASR_A1_AP_Pos)                        /*!< PPB MPU_RASR_A1: AP Mask            */\r
-#define PPB_MPU_RASR_A1_XN_Pos                                28                                                        /*!< PPB MPU_RASR_A1: XN Position        */\r
-#define PPB_MPU_RASR_A1_XN_Msk                                (0x01UL << PPB_MPU_RASR_A1_XN_Pos)                        /*!< PPB MPU_RASR_A1: XN Mask            */\r
-\r
-// -------------------------------------  PPB_MPU_RBAR_A2  ----------------------------------------\r
-#define PPB_MPU_RBAR_A2_REGION_Pos                            0                                                         /*!< PPB MPU_RBAR_A2: REGION Position    */\r
-#define PPB_MPU_RBAR_A2_REGION_Msk                            (0x0fUL << PPB_MPU_RBAR_A2_REGION_Pos)                    /*!< PPB MPU_RBAR_A2: REGION Mask        */\r
-#define PPB_MPU_RBAR_A2_VALID_Pos                             4                                                         /*!< PPB MPU_RBAR_A2: VALID Position     */\r
-#define PPB_MPU_RBAR_A2_VALID_Msk                             (0x01UL << PPB_MPU_RBAR_A2_VALID_Pos)                     /*!< PPB MPU_RBAR_A2: VALID Mask         */\r
-#define PPB_MPU_RBAR_A2_ADDR_Pos                              9                                                         /*!< PPB MPU_RBAR_A2: ADDR Position      */\r
-#define PPB_MPU_RBAR_A2_ADDR_Msk                              (0x007fffffUL << PPB_MPU_RBAR_A2_ADDR_Pos)                /*!< PPB MPU_RBAR_A2: ADDR Mask          */\r
-\r
-// -------------------------------------  PPB_MPU_RASR_A2  ----------------------------------------\r
-#define PPB_MPU_RASR_A2_ENABLE_Pos                            0                                                         /*!< PPB MPU_RASR_A2: ENABLE Position    */\r
-#define PPB_MPU_RASR_A2_ENABLE_Msk                            (0x01UL << PPB_MPU_RASR_A2_ENABLE_Pos)                    /*!< PPB MPU_RASR_A2: ENABLE Mask        */\r
-#define PPB_MPU_RASR_A2_SIZE_Pos                              1                                                         /*!< PPB MPU_RASR_A2: SIZE Position      */\r
-#define PPB_MPU_RASR_A2_SIZE_Msk                              (0x1fUL << PPB_MPU_RASR_A2_SIZE_Pos)                      /*!< PPB MPU_RASR_A2: SIZE Mask          */\r
-#define PPB_MPU_RASR_A2_SRD_Pos                               8                                                         /*!< PPB MPU_RASR_A2: SRD Position       */\r
-#define PPB_MPU_RASR_A2_SRD_Msk                               (0x000000ffUL << PPB_MPU_RASR_A2_SRD_Pos)                 /*!< PPB MPU_RASR_A2: SRD Mask           */\r
-#define PPB_MPU_RASR_A2_B_Pos                                 16                                                        /*!< PPB MPU_RASR_A2: B Position         */\r
-#define PPB_MPU_RASR_A2_B_Msk                                 (0x01UL << PPB_MPU_RASR_A2_B_Pos)                         /*!< PPB MPU_RASR_A2: B Mask             */\r
-#define PPB_MPU_RASR_A2_C_Pos                                 17                                                        /*!< PPB MPU_RASR_A2: C Position         */\r
-#define PPB_MPU_RASR_A2_C_Msk                                 (0x01UL << PPB_MPU_RASR_A2_C_Pos)                         /*!< PPB MPU_RASR_A2: C Mask             */\r
-#define PPB_MPU_RASR_A2_S_Pos                                 18                                                        /*!< PPB MPU_RASR_A2: S Position         */\r
-#define PPB_MPU_RASR_A2_S_Msk                                 (0x01UL << PPB_MPU_RASR_A2_S_Pos)                         /*!< PPB MPU_RASR_A2: S Mask             */\r
-#define PPB_MPU_RASR_A2_TEX_Pos                               19                                                        /*!< PPB MPU_RASR_A2: TEX Position       */\r
-#define PPB_MPU_RASR_A2_TEX_Msk                               (0x07UL << PPB_MPU_RASR_A2_TEX_Pos)                       /*!< PPB MPU_RASR_A2: TEX Mask           */\r
-#define PPB_MPU_RASR_A2_AP_Pos                                24                                                        /*!< PPB MPU_RASR_A2: AP Position        */\r
-#define PPB_MPU_RASR_A2_AP_Msk                                (0x07UL << PPB_MPU_RASR_A2_AP_Pos)                        /*!< PPB MPU_RASR_A2: AP Mask            */\r
-#define PPB_MPU_RASR_A2_XN_Pos                                28                                                        /*!< PPB MPU_RASR_A2: XN Position        */\r
-#define PPB_MPU_RASR_A2_XN_Msk                                (0x01UL << PPB_MPU_RASR_A2_XN_Pos)                        /*!< PPB MPU_RASR_A2: XN Mask            */\r
-\r
-// -------------------------------------  PPB_MPU_RBAR_A3  ----------------------------------------\r
-#define PPB_MPU_RBAR_A3_REGION_Pos                            0                                                         /*!< PPB MPU_RBAR_A3: REGION Position    */\r
-#define PPB_MPU_RBAR_A3_REGION_Msk                            (0x0fUL << PPB_MPU_RBAR_A3_REGION_Pos)                    /*!< PPB MPU_RBAR_A3: REGION Mask        */\r
-#define PPB_MPU_RBAR_A3_VALID_Pos                             4                                                         /*!< PPB MPU_RBAR_A3: VALID Position     */\r
-#define PPB_MPU_RBAR_A3_VALID_Msk                             (0x01UL << PPB_MPU_RBAR_A3_VALID_Pos)                     /*!< PPB MPU_RBAR_A3: VALID Mask         */\r
-#define PPB_MPU_RBAR_A3_ADDR_Pos                              9                                                         /*!< PPB MPU_RBAR_A3: ADDR Position      */\r
-#define PPB_MPU_RBAR_A3_ADDR_Msk                              (0x007fffffUL << PPB_MPU_RBAR_A3_ADDR_Pos)                /*!< PPB MPU_RBAR_A3: ADDR Mask          */\r
-\r
-// -------------------------------------  PPB_MPU_RASR_A3  ----------------------------------------\r
-#define PPB_MPU_RASR_A3_ENABLE_Pos                            0                                                         /*!< PPB MPU_RASR_A3: ENABLE Position    */\r
-#define PPB_MPU_RASR_A3_ENABLE_Msk                            (0x01UL << PPB_MPU_RASR_A3_ENABLE_Pos)                    /*!< PPB MPU_RASR_A3: ENABLE Mask        */\r
-#define PPB_MPU_RASR_A3_SIZE_Pos                              1                                                         /*!< PPB MPU_RASR_A3: SIZE Position      */\r
-#define PPB_MPU_RASR_A3_SIZE_Msk                              (0x1fUL << PPB_MPU_RASR_A3_SIZE_Pos)                      /*!< PPB MPU_RASR_A3: SIZE Mask          */\r
-#define PPB_MPU_RASR_A3_SRD_Pos                               8                                                         /*!< PPB MPU_RASR_A3: SRD Position       */\r
-#define PPB_MPU_RASR_A3_SRD_Msk                               (0x000000ffUL << PPB_MPU_RASR_A3_SRD_Pos)                 /*!< PPB MPU_RASR_A3: SRD Mask           */\r
-#define PPB_MPU_RASR_A3_B_Pos                                 16                                                        /*!< PPB MPU_RASR_A3: B Position         */\r
-#define PPB_MPU_RASR_A3_B_Msk                                 (0x01UL << PPB_MPU_RASR_A3_B_Pos)                         /*!< PPB MPU_RASR_A3: B Mask             */\r
-#define PPB_MPU_RASR_A3_C_Pos                                 17                                                        /*!< PPB MPU_RASR_A3: C Position         */\r
-#define PPB_MPU_RASR_A3_C_Msk                                 (0x01UL << PPB_MPU_RASR_A3_C_Pos)                         /*!< PPB MPU_RASR_A3: C Mask             */\r
-#define PPB_MPU_RASR_A3_S_Pos                                 18                                                        /*!< PPB MPU_RASR_A3: S Position         */\r
-#define PPB_MPU_RASR_A3_S_Msk                                 (0x01UL << PPB_MPU_RASR_A3_S_Pos)                         /*!< PPB MPU_RASR_A3: S Mask             */\r
-#define PPB_MPU_RASR_A3_TEX_Pos                               19                                                        /*!< PPB MPU_RASR_A3: TEX Position       */\r
-#define PPB_MPU_RASR_A3_TEX_Msk                               (0x07UL << PPB_MPU_RASR_A3_TEX_Pos)                       /*!< PPB MPU_RASR_A3: TEX Mask           */\r
-#define PPB_MPU_RASR_A3_AP_Pos                                24                                                        /*!< PPB MPU_RASR_A3: AP Position        */\r
-#define PPB_MPU_RASR_A3_AP_Msk                                (0x07UL << PPB_MPU_RASR_A3_AP_Pos)                        /*!< PPB MPU_RASR_A3: AP Mask            */\r
-#define PPB_MPU_RASR_A3_XN_Pos                                28                                                        /*!< PPB MPU_RASR_A3: XN Position        */\r
-#define PPB_MPU_RASR_A3_XN_Msk                                (0x01UL << PPB_MPU_RASR_A3_XN_Pos)                        /*!< PPB MPU_RASR_A3: XN Mask            */\r
-\r
-// ----------------------------------------  PPB_STIR  --------------------------------------------\r
-#define PPB_STIR_INTID_Pos                                    0                                                         /*!< PPB STIR: INTID Position            */\r
-#define PPB_STIR_INTID_Msk                                    (0x000001ffUL << PPB_STIR_INTID_Pos)                      /*!< PPB STIR: INTID Mask                */\r
-\r
-// ----------------------------------------  PPB_FPCCR  -------------------------------------------\r
-#define PPB_FPCCR_LSPACT_Pos                                  0                                                         /*!< PPB FPCCR: LSPACT Position          */\r
-#define PPB_FPCCR_LSPACT_Msk                                  (0x01UL << PPB_FPCCR_LSPACT_Pos)                          /*!< PPB FPCCR: LSPACT Mask              */\r
-#define PPB_FPCCR_USER_Pos                                    1                                                         /*!< PPB FPCCR: USER Position            */\r
-#define PPB_FPCCR_USER_Msk                                    (0x01UL << PPB_FPCCR_USER_Pos)                            /*!< PPB FPCCR: USER Mask                */\r
-#define PPB_FPCCR_THREAD_Pos                                  3                                                         /*!< PPB FPCCR: THREAD Position          */\r
-#define PPB_FPCCR_THREAD_Msk                                  (0x01UL << PPB_FPCCR_THREAD_Pos)                          /*!< PPB FPCCR: THREAD Mask              */\r
-#define PPB_FPCCR_HFRDY_Pos                                   4                                                         /*!< PPB FPCCR: HFRDY Position           */\r
-#define PPB_FPCCR_HFRDY_Msk                                   (0x01UL << PPB_FPCCR_HFRDY_Pos)                           /*!< PPB FPCCR: HFRDY Mask               */\r
-#define PPB_FPCCR_MMRDY_Pos                                   5                                                         /*!< PPB FPCCR: MMRDY Position           */\r
-#define PPB_FPCCR_MMRDY_Msk                                   (0x01UL << PPB_FPCCR_MMRDY_Pos)                           /*!< PPB FPCCR: MMRDY Mask               */\r
-#define PPB_FPCCR_BFRDY_Pos                                   6                                                         /*!< PPB FPCCR: BFRDY Position           */\r
-#define PPB_FPCCR_BFRDY_Msk                                   (0x01UL << PPB_FPCCR_BFRDY_Pos)                           /*!< PPB FPCCR: BFRDY Mask               */\r
-#define PPB_FPCCR_MONRDY_Pos                                  8                                                         /*!< PPB FPCCR: MONRDY Position          */\r
-#define PPB_FPCCR_MONRDY_Msk                                  (0x01UL << PPB_FPCCR_MONRDY_Pos)                          /*!< PPB FPCCR: MONRDY Mask              */\r
-#define PPB_FPCCR_LSPEN_Pos                                   30                                                        /*!< PPB FPCCR: LSPEN Position           */\r
-#define PPB_FPCCR_LSPEN_Msk                                   (0x01UL << PPB_FPCCR_LSPEN_Pos)                           /*!< PPB FPCCR: LSPEN Mask               */\r
-#define PPB_FPCCR_ASPEN_Pos                                   31                                                        /*!< PPB FPCCR: ASPEN Position           */\r
-#define PPB_FPCCR_ASPEN_Msk                                   (0x01UL << PPB_FPCCR_ASPEN_Pos)                           /*!< PPB FPCCR: ASPEN Mask               */\r
-\r
-// ----------------------------------------  PPB_FPCAR  -------------------------------------------\r
-#define PPB_FPCAR_ADDRESS_Pos                                 3                                                         /*!< PPB FPCAR: ADDRESS Position         */\r
-#define PPB_FPCAR_ADDRESS_Msk                                 (0x1fffffffUL << PPB_FPCAR_ADDRESS_Pos)                   /*!< PPB FPCAR: ADDRESS Mask             */\r
-\r
-// ---------------------------------------  PPB_FPDSCR  -------------------------------------------\r
-#define PPB_FPDSCR_RMode_Pos                                  22                                                        /*!< PPB FPDSCR: RMode Position          */\r
-#define PPB_FPDSCR_RMode_Msk                                  (0x03UL << PPB_FPDSCR_RMode_Pos)                          /*!< PPB FPDSCR: RMode Mask              */\r
-#define PPB_FPDSCR_FZ_Pos                                     24                                                        /*!< PPB FPDSCR: FZ Position             */\r
-#define PPB_FPDSCR_FZ_Msk                                     (0x01UL << PPB_FPDSCR_FZ_Pos)                             /*!< PPB FPDSCR: FZ Mask                 */\r
-#define PPB_FPDSCR_DN_Pos                                     25                                                        /*!< PPB FPDSCR: DN Position             */\r
-#define PPB_FPDSCR_DN_Msk                                     (0x01UL << PPB_FPDSCR_DN_Pos)                             /*!< PPB FPDSCR: DN Mask                 */\r
-#define PPB_FPDSCR_AHP_Pos                                    26                                                        /*!< PPB FPDSCR: AHP Position            */\r
-#define PPB_FPDSCR_AHP_Msk                                    (0x01UL << PPB_FPDSCR_AHP_Pos)                            /*!< PPB FPDSCR: AHP Mask                */\r
-\r
-/***   PREF Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* PREF_PCON  =  Prefetch Configuration Register*/\r
-#define   PREF_PCON_IBYP_Pos   (0U)\r
-#define   PREF_PCON_IBYP_Msk   (0x00000001U  << PREF_PCON_IBYP_Pos)\r
-\r
-#define   PREF_PCON_IINV_Pos   (1U)\r
-#define   PREF_PCON_IINV_Msk   (0x00000001U  << PREF_PCON_IINV_Pos)\r
-\r
-#define   PREF_PCON_PBS_Pos    (16U)\r
-#define   PREF_PCON_PBS_Msk    (0x00000001U  << PREF_PCON_PBS_Pos)\r
-\r
-\r
-\r
-/***   RTC Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* RTC_ID  =  RTC ID Register*/\r
-#define   RTC_ID_ID_Pos        (0U)\r
-#define   RTC_ID_ID_Msk        (0xFFFFFFFFU  << RTC_ID_ID_Pos)\r
-\r
-/* RTC_CTR  =  RTC Control Register*/\r
-#define   RTC_CTR_ENB_Pos      (0U)\r
-#define   RTC_CTR_ENB_Msk      (0x00000001U  << RTC_CTR_ENB_Pos)\r
-\r
-#define   RTC_CTR_TAE_Pos      (2U)\r
-#define   RTC_CTR_TAE_Msk      (0x00000001U  << RTC_CTR_TAE_Pos)\r
-\r
-#define   RTC_CTR_ESEC_Pos     (8U)\r
-#define   RTC_CTR_ESEC_Msk     (0x00000001U  << RTC_CTR_ESEC_Pos)\r
-\r
-#define   RTC_CTR_EMIC_Pos     (9U)\r
-#define   RTC_CTR_EMIC_Msk     (0x00000001U  << RTC_CTR_EMIC_Pos)\r
-\r
-#define   RTC_CTR_EHOC_Pos     (10U)\r
-#define   RTC_CTR_EHOC_Msk     (0x00000001U  << RTC_CTR_EHOC_Pos)\r
-\r
-#define   RTC_CTR_EDAC_Pos     (11U)\r
-#define   RTC_CTR_EDAC_Msk     (0x00000001U  << RTC_CTR_EDAC_Pos)\r
-\r
-#define   RTC_CTR_EDAWEC_Pos   (12U)\r
-#define   RTC_CTR_EDAWEC_Msk   (0x00000001U  << RTC_CTR_EDAWEC_Pos)\r
-\r
-#define   RTC_CTR_EMOC_Pos     (13U)\r
-#define   RTC_CTR_EMOC_Msk     (0x00000001U  << RTC_CTR_EMOC_Pos)\r
-\r
-#define   RTC_CTR_EYEC_Pos     (14U)\r
-#define   RTC_CTR_EYEC_Msk     (0x00000001U  << RTC_CTR_EYEC_Pos)\r
-\r
-#define   RTC_CTR_DIV_Pos      (16U)\r
-#define   RTC_CTR_DIV_Msk      (0x0000FFFFU  << RTC_CTR_DIV_Pos)\r
-\r
-/* RTC_RAWSTAT  =  RTC Raw Service Request Register*/\r
-#define   RTC_RAWSTAT_RPSE_Pos         (0U)\r
-#define   RTC_RAWSTAT_RPSE_Msk         (0x00000001U  << RTC_RAWSTAT_RPSE_Pos)\r
-\r
-#define   RTC_RAWSTAT_RPMI_Pos         (1U)\r
-#define   RTC_RAWSTAT_RPMI_Msk         (0x00000001U  << RTC_RAWSTAT_RPMI_Pos)\r
-\r
-#define   RTC_RAWSTAT_RPHO_Pos         (2U)\r
-#define   RTC_RAWSTAT_RPHO_Msk         (0x00000001U  << RTC_RAWSTAT_RPHO_Pos)\r
-\r
-#define   RTC_RAWSTAT_RPDA_Pos         (3U)\r
-#define   RTC_RAWSTAT_RPDA_Msk         (0x00000001U  << RTC_RAWSTAT_RPDA_Pos)\r
-\r
-#define   RTC_RAWSTAT_RPMO_Pos         (5U)\r
-#define   RTC_RAWSTAT_RPMO_Msk         (0x00000001U  << RTC_RAWSTAT_RPMO_Pos)\r
-\r
-#define   RTC_RAWSTAT_RPYE_Pos         (6U)\r
-#define   RTC_RAWSTAT_RPYE_Msk         (0x00000001U  << RTC_RAWSTAT_RPYE_Pos)\r
-\r
-#define   RTC_RAWSTAT_RAI_Pos          (8U)\r
-#define   RTC_RAWSTAT_RAI_Msk          (0x00000001U  << RTC_RAWSTAT_RAI_Pos)\r
-\r
-/* RTC_STSSR  =  RTC Service Request Status Register*/\r
-#define   RTC_STSSR_SPSE_Pos   (0U)\r
-#define   RTC_STSSR_SPSE_Msk   (0x00000001U  << RTC_STSSR_SPSE_Pos)\r
-\r
-#define   RTC_STSSR_SPMI_Pos   (1U)\r
-#define   RTC_STSSR_SPMI_Msk   (0x00000001U  << RTC_STSSR_SPMI_Pos)\r
-\r
-#define   RTC_STSSR_SPHO_Pos   (2U)\r
-#define   RTC_STSSR_SPHO_Msk   (0x00000001U  << RTC_STSSR_SPHO_Pos)\r
-\r
-#define   RTC_STSSR_SPDA_Pos   (3U)\r
-#define   RTC_STSSR_SPDA_Msk   (0x00000001U  << RTC_STSSR_SPDA_Pos)\r
-\r
-#define   RTC_STSSR_SPMO_Pos   (5U)\r
-#define   RTC_STSSR_SPMO_Msk   (0x00000001U  << RTC_STSSR_SPMO_Pos)\r
-\r
-#define   RTC_STSSR_SPYE_Pos   (6U)\r
-#define   RTC_STSSR_SPYE_Msk   (0x00000001U  << RTC_STSSR_SPYE_Pos)\r
-\r
-#define   RTC_STSSR_SAI_Pos    (8U)\r
-#define   RTC_STSSR_SAI_Msk    (0x00000001U  << RTC_STSSR_SAI_Pos)\r
-\r
-/* RTC_MSKSR  =  RTC Service Request Mask Register*/\r
-#define   RTC_MSKSR_MPSE_Pos   (0U)\r
-#define   RTC_MSKSR_MPSE_Msk   (0x00000001U  << RTC_MSKSR_MPSE_Pos)\r
-\r
-#define   RTC_MSKSR_MPMI_Pos   (1U)\r
-#define   RTC_MSKSR_MPMI_Msk   (0x00000001U  << RTC_MSKSR_MPMI_Pos)\r
-\r
-#define   RTC_MSKSR_MPHO_Pos   (2U)\r
-#define   RTC_MSKSR_MPHO_Msk   (0x00000001U  << RTC_MSKSR_MPHO_Pos)\r
-\r
-#define   RTC_MSKSR_MPDA_Pos   (3U)\r
-#define   RTC_MSKSR_MPDA_Msk   (0x00000001U  << RTC_MSKSR_MPDA_Pos)\r
-\r
-#define   RTC_MSKSR_MPMO_Pos   (5U)\r
-#define   RTC_MSKSR_MPMO_Msk   (0x00000001U  << RTC_MSKSR_MPMO_Pos)\r
-\r
-#define   RTC_MSKSR_MPYE_Pos   (6U)\r
-#define   RTC_MSKSR_MPYE_Msk   (0x00000001U  << RTC_MSKSR_MPYE_Pos)\r
-\r
-#define   RTC_MSKSR_MAI_Pos    (8U)\r
-#define   RTC_MSKSR_MAI_Msk    (0x00000001U  << RTC_MSKSR_MAI_Pos)\r
-\r
-/* RTC_CLRSR  =  RTC Clear Service Request Register*/\r
-#define   RTC_CLRSR_RPSE_Pos   (0U)\r
-#define   RTC_CLRSR_RPSE_Msk   (0x00000001U  << RTC_CLRSR_RPSE_Pos)\r
-\r
-#define   RTC_CLRSR_RPMI_Pos   (1U)\r
-#define   RTC_CLRSR_RPMI_Msk   (0x00000001U  << RTC_CLRSR_RPMI_Pos)\r
-\r
-#define   RTC_CLRSR_RPHO_Pos   (2U)\r
-#define   RTC_CLRSR_RPHO_Msk   (0x00000001U  << RTC_CLRSR_RPHO_Pos)\r
-\r
-#define   RTC_CLRSR_RPDA_Pos   (3U)\r
-#define   RTC_CLRSR_RPDA_Msk   (0x00000001U  << RTC_CLRSR_RPDA_Pos)\r
-\r
-#define   RTC_CLRSR_RPMO_Pos   (5U)\r
-#define   RTC_CLRSR_RPMO_Msk   (0x00000001U  << RTC_CLRSR_RPMO_Pos)\r
-\r
-#define   RTC_CLRSR_RPYE_Pos   (6U)\r
-#define   RTC_CLRSR_RPYE_Msk   (0x00000001U  << RTC_CLRSR_RPYE_Pos)\r
-\r
-#define   RTC_CLRSR_RAI_Pos    (8U)\r
-#define   RTC_CLRSR_RAI_Msk    (0x00000001U  << RTC_CLRSR_RAI_Pos)\r
-\r
-/* RTC_ATIM0  =  RTC Alarm Time Register 0*/\r
-#define   RTC_ATIM0_ASE_Pos    (0U)\r
-#define   RTC_ATIM0_ASE_Msk    (0x0000003FU  << RTC_ATIM0_ASE_Pos)\r
-\r
-#define   RTC_ATIM0_AMI_Pos    (8U)\r
-#define   RTC_ATIM0_AMI_Msk    (0x0000003FU  << RTC_ATIM0_AMI_Pos)\r
-\r
-#define   RTC_ATIM0_AHO_Pos    (16U)\r
-#define   RTC_ATIM0_AHO_Msk    (0x0000001FU  << RTC_ATIM0_AHO_Pos)\r
-\r
-#define   RTC_ATIM0_ADA_Pos    (24U)\r
-#define   RTC_ATIM0_ADA_Msk    (0x0000001FU  << RTC_ATIM0_ADA_Pos)\r
-\r
-/* RTC_ATIM1  =  RTC Alarm Time Register 1*/\r
-#define   RTC_ATIM1_ADAWE_Pos          (0U)\r
-#define   RTC_ATIM1_ADAWE_Msk          (0x00000007U  << RTC_ATIM1_ADAWE_Pos)\r
-\r
-#define   RTC_ATIM1_AMO_Pos    (8U)\r
-#define   RTC_ATIM1_AMO_Msk    (0x0000000FU  << RTC_ATIM1_AMO_Pos)\r
-\r
-#define   RTC_ATIM1_AYE_Pos    (16U)\r
-#define   RTC_ATIM1_AYE_Msk    (0x0000FFFFU  << RTC_ATIM1_AYE_Pos)\r
-\r
-/* RTC_TIM0  =  RTC Time Register 0*/\r
-#define   RTC_TIM0_SE_Pos      (0U)\r
-#define   RTC_TIM0_SE_Msk      (0x0000003FU  << RTC_TIM0_SE_Pos)\r
-\r
-#define   RTC_TIM0_MI_Pos      (8U)\r
-#define   RTC_TIM0_MI_Msk      (0x0000003FU  << RTC_TIM0_MI_Pos)\r
-\r
-#define   RTC_TIM0_HO_Pos      (16U)\r
-#define   RTC_TIM0_HO_Msk      (0x0000001FU  << RTC_TIM0_HO_Pos)\r
-\r
-#define   RTC_TIM0_DA_Pos      (24U)\r
-#define   RTC_TIM0_DA_Msk      (0x0000001FU  << RTC_TIM0_DA_Pos)\r
-\r
-/* RTC_TIM1  =  RTC Time Register 1*/\r
-#define   RTC_TIM1_DAWE_Pos    (0U)\r
-#define   RTC_TIM1_DAWE_Msk    (0x00000007U  << RTC_TIM1_DAWE_Pos)\r
-\r
-#define   RTC_TIM1_MO_Pos      (8U)\r
-#define   RTC_TIM1_MO_Msk      (0x0000000FU  << RTC_TIM1_MO_Pos)\r
-\r
-#define   RTC_TIM1_YE_Pos      (16U)\r
-#define   RTC_TIM1_YE_Msk      (0x0000FFFFU  << RTC_TIM1_YE_Pos)\r
-\r
-\r
-\r
-/***   SCU Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* SCU_PLL_PLLSTAT  =  PLL Status Register*/\r
-#define   SCU_PLL_PLLSTAT_VCOBYST_Pos          (0U)\r
-#define   SCU_PLL_PLLSTAT_VCOBYST_Msk          (0x00000001U  << SCU_PLL_PLLSTAT_VCOBYST_Pos)\r
-\r
-#define   SCU_PLL_PLLSTAT_PWDSTAT_Pos          (1U)\r
-#define   SCU_PLL_PLLSTAT_PWDSTAT_Msk          (0x00000001U  << SCU_PLL_PLLSTAT_PWDSTAT_Pos)\r
-\r
-#define   SCU_PLL_PLLSTAT_VCOLOCK_Pos          (2U)\r
-#define   SCU_PLL_PLLSTAT_VCOLOCK_Msk          (0x00000001U  << SCU_PLL_PLLSTAT_VCOLOCK_Pos)\r
-\r
-#define   SCU_PLL_PLLSTAT_K1RDY_Pos    (4U)\r
-#define   SCU_PLL_PLLSTAT_K1RDY_Msk    (0x00000001U  << SCU_PLL_PLLSTAT_K1RDY_Pos)\r
-\r
-#define   SCU_PLL_PLLSTAT_K2RDY_Pos    (5U)\r
-#define   SCU_PLL_PLLSTAT_K2RDY_Msk    (0x00000001U  << SCU_PLL_PLLSTAT_K2RDY_Pos)\r
-\r
-#define   SCU_PLL_PLLSTAT_BY_Pos       (6U)\r
-#define   SCU_PLL_PLLSTAT_BY_Msk       (0x00000001U  << SCU_PLL_PLLSTAT_BY_Pos)\r
-\r
-#define   SCU_PLL_PLLSTAT_PLLLV_Pos    (7U)\r
-#define   SCU_PLL_PLLSTAT_PLLLV_Msk    (0x00000001U  << SCU_PLL_PLLSTAT_PLLLV_Pos)\r
-\r
-#define   SCU_PLL_PLLSTAT_PLLHV_Pos    (8U)\r
-#define   SCU_PLL_PLLSTAT_PLLHV_Msk    (0x00000001U  << SCU_PLL_PLLSTAT_PLLHV_Pos)\r
-\r
-#define   SCU_PLL_PLLSTAT_PLLSP_Pos    (9U)\r
-#define   SCU_PLL_PLLSTAT_PLLSP_Msk    (0x00000001U  << SCU_PLL_PLLSTAT_PLLSP_Pos)\r
-\r
-/* SCU_PLL_PLLCON0  =  PLL Configuration x Register*/\r
-#define   SCU_PLL_PLLCON0_VCOBYP_Pos   (0U)\r
-#define   SCU_PLL_PLLCON0_VCOBYP_Msk   (0x00000001U  << SCU_PLL_PLLCON0_VCOBYP_Pos)\r
-\r
-#define   SCU_PLL_PLLCON0_VCOPWD_Pos   (1U)\r
-#define   SCU_PLL_PLLCON0_VCOPWD_Msk   (0x00000001U  << SCU_PLL_PLLCON0_VCOPWD_Pos)\r
-\r
-#define   SCU_PLL_PLLCON0_VCOTR_Pos    (2U)\r
-#define   SCU_PLL_PLLCON0_VCOTR_Msk    (0x00000001U  << SCU_PLL_PLLCON0_VCOTR_Pos)\r
-\r
-#define   SCU_PLL_PLLCON0_FINDIS_Pos   (4U)\r
-#define   SCU_PLL_PLLCON0_FINDIS_Msk   (0x00000001U  << SCU_PLL_PLLCON0_FINDIS_Pos)\r
-\r
-#define   SCU_PLL_PLLCON0_OSCDISCDIS_Pos       (6U)\r
-#define   SCU_PLL_PLLCON0_OSCDISCDIS_Msk       (0x00000001U  << SCU_PLL_PLLCON0_OSCDISCDIS_Pos)\r
-\r
-#define   SCU_PLL_PLLCON0_PLLPWD_Pos   (16U)\r
-#define   SCU_PLL_PLLCON0_PLLPWD_Msk   (0x00000001U  << SCU_PLL_PLLCON0_PLLPWD_Pos)\r
-\r
-#define   SCU_PLL_PLLCON0_OSCRES_Pos   (17U)\r
-#define   SCU_PLL_PLLCON0_OSCRES_Msk   (0x00000001U  << SCU_PLL_PLLCON0_OSCRES_Pos)\r
-\r
-#define   SCU_PLL_PLLCON0_RESLD_Pos    (18U)\r
-#define   SCU_PLL_PLLCON0_RESLD_Msk    (0x00000001U  << SCU_PLL_PLLCON0_RESLD_Pos)\r
-\r
-#define   SCU_PLL_PLLCON0_AOTREN_Pos   (19U)\r
-#define   SCU_PLL_PLLCON0_AOTREN_Msk   (0x00000001U  << SCU_PLL_PLLCON0_AOTREN_Pos)\r
-\r
-#define   SCU_PLL_PLLCON0_FOTR_Pos     (20U)\r
-#define   SCU_PLL_PLLCON0_FOTR_Msk     (0x00000001U  << SCU_PLL_PLLCON0_FOTR_Pos)\r
-\r
-/* SCU_PLL_PLLCON1  =  PLL Configuration 1 Register*/\r
-#define   SCU_PLL_PLLCON1_K1DIV_Pos    (0U)\r
-#define   SCU_PLL_PLLCON1_K1DIV_Msk    (0x0000007FU  << SCU_PLL_PLLCON1_K1DIV_Pos)\r
-\r
-#define   SCU_PLL_PLLCON1_NDIV_Pos     (8U)\r
-#define   SCU_PLL_PLLCON1_NDIV_Msk     (0x0000007FU  << SCU_PLL_PLLCON1_NDIV_Pos)\r
-\r
-#define   SCU_PLL_PLLCON1_K2DIV_Pos    (16U)\r
-#define   SCU_PLL_PLLCON1_K2DIV_Msk    (0x0000007FU  << SCU_PLL_PLLCON1_K2DIV_Pos)\r
-\r
-#define   SCU_PLL_PLLCON1_PDIV_Pos     (24U)\r
-#define   SCU_PLL_PLLCON1_PDIV_Msk     (0x0000000FU  << SCU_PLL_PLLCON1_PDIV_Pos)\r
-\r
-/* SCU_PLL_PLLCON2  =  PLL Configuration 2 Register*/\r
-#define   SCU_PLL_PLLCON2_PINSEL_Pos   (0U)\r
-#define   SCU_PLL_PLLCON2_PINSEL_Msk   (0x00000001U  << SCU_PLL_PLLCON2_PINSEL_Pos)\r
-\r
-#define   SCU_PLL_PLLCON2_K1INSEL_Pos          (8U)\r
-#define   SCU_PLL_PLLCON2_K1INSEL_Msk          (0x00000001U  << SCU_PLL_PLLCON2_K1INSEL_Pos)\r
-\r
-/* SCU_PLL_USBPLL_PLLSTAT  =  USB PLL Status Register*/\r
-#define   SCU_PLL_USBPLLSTAT_VCOBYST_Pos       (0U)\r
-#define   SCU_PLL_USBPLLSTAT_VCOBYST_Msk       (0x00000001U  << SCU_PLL_USBPLLSTAT_VCOBYST_Pos)\r
-\r
-#define   SCU_PLL_USBPLLSTAT_PWDSTAT_Pos       (1U)\r
-#define   SCU_PLL_USBPLLSTAT_PWDSTAT_Msk       (0x00000001U  << SCU_PLL_USBPLLSTAT_PWDSTAT_Pos)\r
-\r
-#define   SCU_PLL_USBPLLSTAT_VCOLOCK_Pos       (2U)\r
-#define   SCU_PLL_USBPLLSTAT_VCOLOCK_Msk       (0x00000001U  << SCU_PLL_USBPLLSTAT_VCOLOCK_Pos)\r
-\r
-#define   SCU_PLL_USBPLLSTAT_BY_Pos    (6U)\r
-#define   SCU_PLL_USBPLLSTAT_BY_Msk    (0x00000001U  << SCU_PLL_USBPLLSTAT_BY_Pos)\r
-\r
-#define   SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos     (7U)\r
-#define   SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk     (0x00000001U  << SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos)\r
-\r
-/* SCU_PLL_USBPLLCON  =  USB PLL Configuration Register*/\r
-#define   SCU_PLL_USBPLLCON_VCOBYP_Pos         (0U)\r
-#define   SCU_PLL_USBPLLCON_VCOBYP_Msk         (0x00000001U  << SCU_PLL_USBPLLCON_VCOBYP_Pos)\r
-\r
-#define   SCU_PLL_USBPLLCON_VCOPWD_Pos         (1U)\r
-#define   SCU_PLL_USBPLLCON_VCOPWD_Msk         (0x00000001U  << SCU_PLL_USBPLLCON_VCOPWD_Pos)\r
-\r
-#define   SCU_PLL_USBPLLCON_VCOTR_Pos          (2U)\r
-#define   SCU_PLL_USBPLLCON_VCOTR_Msk          (0x00000001U  << SCU_PLL_USBPLLCON_VCOTR_Pos)\r
-\r
-#define   SCU_PLL_USBPLLCON_FINDIS_Pos         (4U)\r
-#define   SCU_PLL_USBPLLCON_FINDIS_Msk         (0x00000001U  << SCU_PLL_USBPLLCON_FINDIS_Pos)\r
-\r
-#define   SCU_PLL_USBPLLCON_OSCDISCDIS_Pos     (6U)\r
-#define   SCU_PLL_USBPLLCON_OSCDISCDIS_Msk     (0x00000001U  << SCU_PLL_USBPLLCON_OSCDISCDIS_Pos)\r
-\r
-#define   SCU_PLL_USBPLLCON_NDIV_Pos   (8U)\r
-#define   SCU_PLL_USBPLLCON_NDIV_Msk   (0x0000007FU  << SCU_PLL_USBPLLCON_NDIV_Pos)\r
-\r
-#define   SCU_PLL_USBPLLCON_PLLPWD_Pos         (16U)\r
-#define   SCU_PLL_USBPLLCON_PLLPWD_Msk         (0x00000001U  << SCU_PLL_USBPLLCON_PLLPWD_Pos)\r
-\r
-#define   SCU_PLL_USBPLLCON_RESLD_Pos          (18U)\r
-#define   SCU_PLL_USBPLLCON_RESLD_Msk          (0x00000001U  << SCU_PLL_USBPLLCON_RESLD_Pos)\r
-\r
-#define   SCU_PLL_USBPLLCON_PDIV_Pos   (24U)\r
-#define   SCU_PLL_USBPLLCON_PDIV_Msk   (0x0000000FU  << SCU_PLL_USBPLLCON_PDIV_Pos)\r
-\r
-/* SCU_PLL_CLKMXSTAT  =  Clock Multiplexing Status Register*/\r
-#define   SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos      (0U)\r
-#define   SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk      (0x00000007U  << SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos)\r
-\r
-/* SCU_OSC_OSCHPSTAT  =  OSC_HP Status Register*/\r
-#define   SCU_OSC_OSCHPSTAT_X1D_Pos    (0U)\r
-#define   SCU_OSC_OSCHPSTAT_X1D_Msk    (0x00000001U  << SCU_OSC_OSCHPSTAT_X1D_Pos)\r
-\r
-/* SCU_OSC_OSCHPCTRL  =  OSC_HP Control Register*/\r
-#define   SCU_OSC_OSCHPCTRL_X1DEN_Pos          (0U)\r
-#define   SCU_OSC_OSCHPCTRL_X1DEN_Msk          (0x00000001U  << SCU_OSC_OSCHPCTRL_X1DEN_Pos)\r
-\r
-#define   SCU_OSC_OSCHPCTRL_SHBY_Pos   (1U)\r
-#define   SCU_OSC_OSCHPCTRL_SHBY_Msk   (0x00000001U  << SCU_OSC_OSCHPCTRL_SHBY_Pos)\r
-\r
-#define   SCU_OSC_OSCHPCTRL_GAINSEL_Pos        (2U)\r
-#define   SCU_OSC_OSCHPCTRL_GAINSEL_Msk        (0x00000003U  << SCU_OSC_OSCHPCTRL_GAINSEL_Pos)\r
-\r
-#define   SCU_OSC_OSCHPCTRL_MODE_Pos   (4U)\r
-#define   SCU_OSC_OSCHPCTRL_MODE_Msk   (0x00000003U  << SCU_OSC_OSCHPCTRL_MODE_Pos)\r
-\r
-#define   SCU_OSC_OSCHPCTRL_OSCVAL_Pos         (16U)\r
-#define   SCU_OSC_OSCHPCTRL_OSCVAL_Msk         (0x0000001FU  << SCU_OSC_OSCHPCTRL_OSCVAL_Pos)\r
-\r
-/* SCU_CLK_CLKSTAT  =  Clock Status Register*/\r
-#define   SCU_CLK_CLKSTAT_USBCST_Pos   (0U)\r
-#define   SCU_CLK_CLKSTAT_USBCST_Msk   (0x00000001U  << SCU_CLK_CLKSTAT_USBCST_Pos)\r
-\r
-#define   SCU_CLK_CLKSTAT_MMCCST_Pos   (1U)\r
-#define   SCU_CLK_CLKSTAT_MMCCST_Msk   (0x00000001U  << SCU_CLK_CLKSTAT_MMCCST_Pos)\r
-\r
-#define   SCU_CLK_CLKSTAT_ETH0CST_Pos          (2U)\r
-#define   SCU_CLK_CLKSTAT_ETH0CST_Msk          (0x00000001U  << SCU_CLK_CLKSTAT_ETH0CST_Pos)\r
-\r
-#define   SCU_CLK_CLKSTAT_EBUCST_Pos   (3U)\r
-#define   SCU_CLK_CLKSTAT_EBUCST_Msk   (0x00000001U  << SCU_CLK_CLKSTAT_EBUCST_Pos)\r
-\r
-#define   SCU_CLK_CLKSTAT_CCUCST_Pos   (4U)\r
-#define   SCU_CLK_CLKSTAT_CCUCST_Msk   (0x00000001U  << SCU_CLK_CLKSTAT_CCUCST_Pos)\r
-\r
-#define   SCU_CLK_CLKSTAT_WDTCST_Pos   (5U)\r
-#define   SCU_CLK_CLKSTAT_WDTCST_Msk   (0x00000001U  << SCU_CLK_CLKSTAT_WDTCST_Pos)\r
-\r
-/* SCU_CLK_CLKSET  =  CLK Set Register*/\r
-#define   SCU_CLK_CLKSET_USBCEN_Pos    (0U)\r
-#define   SCU_CLK_CLKSET_USBCEN_Msk    (0x00000001U  << SCU_CLK_CLKSET_USBCEN_Pos)\r
-\r
-#define   SCU_CLK_CLKSET_MMCCEN_Pos    (1U)\r
-#define   SCU_CLK_CLKSET_MMCCEN_Msk    (0x00000001U  << SCU_CLK_CLKSET_MMCCEN_Pos)\r
-\r
-#define   SCU_CLK_CLKSET_ETH0CEN_Pos   (2U)\r
-#define   SCU_CLK_CLKSET_ETH0CEN_Msk   (0x00000001U  << SCU_CLK_CLKSET_ETH0CEN_Pos)\r
-\r
-#define   SCU_CLK_CLKSET_EBUCEN_Pos    (3U)\r
-#define   SCU_CLK_CLKSET_EBUCEN_Msk    (0x00000001U  << SCU_CLK_CLKSET_EBUCEN_Pos)\r
-\r
-#define   SCU_CLK_CLKSET_CCUCEN_Pos    (4U)\r
-#define   SCU_CLK_CLKSET_CCUCEN_Msk    (0x00000001U  << SCU_CLK_CLKSET_CCUCEN_Pos)\r
-\r
-#define   SCU_CLK_CLKSET_WDTCEN_Pos    (5U)\r
-#define   SCU_CLK_CLKSET_WDTCEN_Msk    (0x00000001U  << SCU_CLK_CLKSET_WDTCEN_Pos)\r
-\r
-/* SCU_CLK_CLKCLR  =  CLK Clear Register*/\r
-#define   SCU_CLK_CLKCLR_USBCDI_Pos    (0U)\r
-#define   SCU_CLK_CLKCLR_USBCDI_Msk    (0x00000001U  << SCU_CLK_CLKCLR_USBCDI_Pos)\r
-\r
-#define   SCU_CLK_CLKCLR_MMCCDI_Pos    (1U)\r
-#define   SCU_CLK_CLKCLR_MMCCDI_Msk    (0x00000001U  << SCU_CLK_CLKCLR_MMCCDI_Pos)\r
-\r
-#define   SCU_CLK_CLKCLR_ETH0CDI_Pos   (2U)\r
-#define   SCU_CLK_CLKCLR_ETH0CDI_Msk   (0x00000001U  << SCU_CLK_CLKCLR_ETH0CDI_Pos)\r
-\r
-#define   SCU_CLK_CLKCLR_EBUCDI_Pos    (3U)\r
-#define   SCU_CLK_CLKCLR_EBUCDI_Msk    (0x00000001U  << SCU_CLK_CLKCLR_EBUCDI_Pos)\r
-\r
-#define   SCU_CLK_CLKCLR_CCUCDI_Pos    (4U)\r
-#define   SCU_CLK_CLKCLR_CCUCDI_Msk    (0x00000001U  << SCU_CLK_CLKCLR_CCUCDI_Pos)\r
-\r
-#define   SCU_CLK_CLKCLR_WDTCDI_Pos    (5U)\r
-#define   SCU_CLK_CLKCLR_WDTCDI_Msk    (0x00000001U  << SCU_CLK_CLKCLR_WDTCDI_Pos)\r
-\r
-/* SCU_CLK_SYSCLKCR  =  System Clock Control Register*/\r
-#define   SCU_CLK_SYSCLKCR_SYSDIV_Pos          (0U)\r
-#define   SCU_CLK_SYSCLKCR_SYSDIV_Msk          (0x000000FFU  << SCU_CLK_SYSCLKCR_SYSDIV_Pos)\r
-\r
-#define   SCU_CLK_SYSCLKCR_SYSSEL_Pos          (16U)\r
-#define   SCU_CLK_SYSCLKCR_SYSSEL_Msk          (0x00000003U  << SCU_CLK_SYSCLKCR_SYSSEL_Pos)\r
-\r
-/* SCU_CLK_CPUCLKCR  =  CPU Clock Control Register*/\r
-#define   SCU_CLK_CPUCLKCR_CPUDIV_Pos          (0U)\r
-#define   SCU_CLK_CPUCLKCR_CPUDIV_Msk          (0x00000001U  << SCU_CLK_CPUCLKCR_CPUDIV_Pos)\r
-\r
-/* SCU_CLK_PBCLKCR  =  Peripheral Bus Clock Control Register*/\r
-#define   SCU_CLK_PBCLKCR_PBDIV_Pos    (0U)\r
-#define   SCU_CLK_PBCLKCR_PBDIV_Msk    (0x00000001U  << SCU_CLK_PBCLKCR_PBDIV_Pos)\r
-\r
-/* SCU_CLK_USBCLKCR  =  USB Clock Control Register*/\r
-#define   SCU_CLK_USBCLKCR_USBDIV_Pos          (0U)\r
-#define   SCU_CLK_USBCLKCR_USBDIV_Msk          (0x00000007U  << SCU_CLK_USBCLKCR_USBDIV_Pos)\r
-\r
-#define   SCU_CLK_USBCLKCR_USBSEL_Pos          (16U)\r
-#define   SCU_CLK_USBCLKCR_USBSEL_Msk          (0x00000001U  << SCU_CLK_USBCLKCR_USBSEL_Pos)\r
-\r
-/* SCU_CLK_EBUCLKCR  =  EBU Clock Control Register*/\r
-#define   SCU_CLK_EBUCLKCR_EBUDIV_Pos          (0U)\r
-#define   SCU_CLK_EBUCLKCR_EBUDIV_Msk          (0x0000003FU  << SCU_CLK_EBUCLKCR_EBUDIV_Pos)\r
-\r
-/* SCU_CLK_CCUCLKCR  =  CCU Clock Control Register*/\r
-#define   SCU_CLK_CCUCLKCR_CCUDIV_Pos          (0U)\r
-#define   SCU_CLK_CCUCLKCR_CCUDIV_Msk          (0x00000001U  << SCU_CLK_CCUCLKCR_CCUDIV_Pos)\r
-\r
-/* SCU_CLK_WDTCLKCR  =  WDT Clock Control Register*/\r
-#define   SCU_CLK_WDTCLKCR_WDTDIV_Pos          (0U)\r
-#define   SCU_CLK_WDTCLKCR_WDTDIV_Msk          (0x000000FFU  << SCU_CLK_WDTCLKCR_WDTDIV_Pos)\r
-\r
-#define   SCU_CLK_WDTCLKCR_WDTSEL_Pos          (16U)\r
-#define   SCU_CLK_WDTCLKCR_WDTSEL_Msk          (0x00000003U  << SCU_CLK_WDTCLKCR_WDTSEL_Pos)\r
-\r
-/* SCU_CLK_EXTCLKCR  =  External Clock Control*/\r
-#define   SCU_CLK_EXTCLKCR_ECKSEL_Pos          (0U)\r
-#define   SCU_CLK_EXTCLKCR_ECKSEL_Msk          (0x00000003U  << SCU_CLK_EXTCLKCR_ECKSEL_Pos)\r
-\r
-#define   SCU_CLK_EXTCLKCR_ECKDIV_Pos          (16U)\r
-#define   SCU_CLK_EXTCLKCR_ECKDIV_Msk          (0x000001FFU  << SCU_CLK_EXTCLKCR_ECKDIV_Pos)\r
-\r
-/* SCU_CLK_SLEEPCR  =  Sleep Control Register*/\r
-#define   SCU_CLK_SLEEPCR_SYSSEL_Pos   (0U)\r
-#define   SCU_CLK_SLEEPCR_SYSSEL_Msk   (0x00000003U  << SCU_CLK_SLEEPCR_SYSSEL_Pos)\r
-\r
-#define   SCU_CLK_SLEEPCR_USBCR_Pos    (16U)\r
-#define   SCU_CLK_SLEEPCR_USBCR_Msk    (0x00000001U  << SCU_CLK_SLEEPCR_USBCR_Pos)\r
-\r
-#define   SCU_CLK_SLEEPCR_MMCCR_Pos    (17U)\r
-#define   SCU_CLK_SLEEPCR_MMCCR_Msk    (0x00000001U  << SCU_CLK_SLEEPCR_MMCCR_Pos)\r
-\r
-#define   SCU_CLK_SLEEPCR_ETH0CR_Pos   (18U)\r
-#define   SCU_CLK_SLEEPCR_ETH0CR_Msk   (0x00000001U  << SCU_CLK_SLEEPCR_ETH0CR_Pos)\r
-\r
-#define   SCU_CLK_SLEEPCR_EBUCR_Pos    (19U)\r
-#define   SCU_CLK_SLEEPCR_EBUCR_Msk    (0x00000001U  << SCU_CLK_SLEEPCR_EBUCR_Pos)\r
-\r
-#define   SCU_CLK_SLEEPCR_CCUCR_Pos    (20U)\r
-#define   SCU_CLK_SLEEPCR_CCUCR_Msk    (0x00000001U  << SCU_CLK_SLEEPCR_CCUCR_Pos)\r
-\r
-#define   SCU_CLK_SLEEPCR_WDTCR_Pos    (21U)\r
-#define   SCU_CLK_SLEEPCR_WDTCR_Msk    (0x00000001U  << SCU_CLK_SLEEPCR_WDTCR_Pos)\r
-\r
-/* SCU_CLK_DSLEEPCR  =  Deep Sleep Control Register*/\r
-#define   SCU_CLK_DSLEEPCR_SYSSEL_Pos          (0U)\r
-#define   SCU_CLK_DSLEEPCR_SYSSEL_Msk          (0x00000003U  << SCU_CLK_DSLEEPCR_SYSSEL_Pos)\r
-\r
-#define   SCU_CLK_DSLEEPCR_FPDN_Pos    (11U)\r
-#define   SCU_CLK_DSLEEPCR_FPDN_Msk    (0x00000001U  << SCU_CLK_DSLEEPCR_FPDN_Pos)\r
-\r
-#define   SCU_CLK_DSLEEPCR_PLLPDN_Pos          (12U)\r
-#define   SCU_CLK_DSLEEPCR_PLLPDN_Msk          (0x00000001U  << SCU_CLK_DSLEEPCR_PLLPDN_Pos)\r
-\r
-#define   SCU_CLK_DSLEEPCR_VCOPDN_Pos          (13U)\r
-#define   SCU_CLK_DSLEEPCR_VCOPDN_Msk          (0x00000001U  << SCU_CLK_DSLEEPCR_VCOPDN_Pos)\r
-\r
-#define   SCU_CLK_DSLEEPCR_USBCR_Pos   (16U)\r
-#define   SCU_CLK_DSLEEPCR_USBCR_Msk   (0x00000001U  << SCU_CLK_DSLEEPCR_USBCR_Pos)\r
-\r
-#define   SCU_CLK_DSLEEPCR_MMCCR_Pos   (17U)\r
-#define   SCU_CLK_DSLEEPCR_MMCCR_Msk   (0x00000001U  << SCU_CLK_DSLEEPCR_MMCCR_Pos)\r
-\r
-#define   SCU_CLK_DSLEEPCR_ETH0CR_Pos          (18U)\r
-#define   SCU_CLK_DSLEEPCR_ETH0CR_Msk          (0x00000001U  << SCU_CLK_DSLEEPCR_ETH0CR_Pos)\r
-\r
-#define   SCU_CLK_DSLEEPCR_EBUCR_Pos   (19U)\r
-#define   SCU_CLK_DSLEEPCR_EBUCR_Msk   (0x00000001U  << SCU_CLK_DSLEEPCR_EBUCR_Pos)\r
-\r
-#define   SCU_CLK_DSLEEPCR_CCUCR_Pos   (20U)\r
-#define   SCU_CLK_DSLEEPCR_CCUCR_Msk   (0x00000001U  << SCU_CLK_DSLEEPCR_CCUCR_Pos)\r
-\r
-#define   SCU_CLK_DSLEEPCR_WDTCR_Pos   (21U)\r
-#define   SCU_CLK_DSLEEPCR_WDTCR_Msk   (0x00000001U  << SCU_CLK_DSLEEPCR_WDTCR_Pos)\r
-\r
-\r
-\r
-/***   SCU Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* SCU_GENERAL_ID  =  SCU Module ID Register*/\r
-#define   SCU_GENERAL_ID_ID_Pos        (0U)\r
-#define   SCU_GENERAL_ID_ID_Msk        (0xFFFFFFFFU  << SCU_GENERAL_ID_ID_Pos)\r
-\r
-/* SCU_GENERAL_IDCHIP  =  Chip ID Register*/\r
-#define   SCU_GENERAL_IDCHIP_IDCHIP_Pos        (0U)\r
-#define   SCU_GENERAL_IDCHIP_IDCHIP_Msk        (0xFFFFFFFFU  << SCU_GENERAL_IDCHIP_IDCHIP_Pos)\r
-\r
-/* SCU_GENERAL_IDMANUF  =  Manufactory ID Register*/\r
-#define   SCU_GENERAL_IDMANUF_IDMANUF_Pos      (0U)\r
-#define   SCU_GENERAL_IDMANUF_IDMANUF_Msk      (0xFFFFFFFFU  << SCU_GENERAL_IDMANUF_IDMANUF_Pos)\r
-\r
-/* SCU_GENERAL_STCON  =  Startup Configuration Register*/\r
-#define   SCU_GENERAL_STCON_HWCON_Pos          (0U)\r
-#define   SCU_GENERAL_STCON_HWCON_Msk          (0x00000003U  << SCU_GENERAL_STCON_HWCON_Pos)\r
-\r
-#define   SCU_GENERAL_STCON_SWCON_Pos          (8U)\r
-#define   SCU_GENERAL_STCON_SWCON_Msk          (0x0000000FU  << SCU_GENERAL_STCON_SWCON_Pos)\r
-\r
-/* SCU_GENERAL_GPRx  =  General Purpose Register*/\r
-#define   SCU_GENERAL_GPR_DAT_Pos      (0U)\r
-#define   SCU_GENERAL_GPR_DAT_Msk      (0xFFFFFFFFU  << SCU_GENERAL_GPR_DAT_Pos)\r
-\r
-/* SCU_GENERAL_CCUCON  =  CCU Control Register*/\r
-#define   SCU_GENERAL_CCUCON_GSC40_Pos         (0U)\r
-#define   SCU_GENERAL_CCUCON_GSC40_Msk         (0x00000001U  << SCU_GENERAL_CCUCON_GSC40_Pos)\r
-\r
-#define   SCU_GENERAL_CCUCON_GSC41_Pos         (1U)\r
-#define   SCU_GENERAL_CCUCON_GSC41_Msk         (0x00000001U  << SCU_GENERAL_CCUCON_GSC41_Pos)\r
-\r
-#define   SCU_GENERAL_CCUCON_GSC42_Pos         (2U)\r
-#define   SCU_GENERAL_CCUCON_GSC42_Msk         (0x00000001U  << SCU_GENERAL_CCUCON_GSC42_Pos)\r
-\r
-#define   SCU_GENERAL_CCUCON_GSC43_Pos         (3U)\r
-#define   SCU_GENERAL_CCUCON_GSC43_Msk         (0x00000001U  << SCU_GENERAL_CCUCON_GSC43_Pos)\r
-\r
-#define   SCU_GENERAL_CCUCON_GSC80_Pos         (8U)\r
-#define   SCU_GENERAL_CCUCON_GSC80_Msk         (0x00000001U  << SCU_GENERAL_CCUCON_GSC80_Pos)\r
-\r
-#define   SCU_GENERAL_CCUCON_GSC81_Pos         (9U)\r
-#define   SCU_GENERAL_CCUCON_GSC81_Msk         (0x00000001U  << SCU_GENERAL_CCUCON_GSC81_Pos)\r
-\r
-/* SCU_GENERAL_DTSCON  =  Die Temperature Sensor Control Register*/\r
-#define   SCU_GENERAL_DTSCON_PWD_Pos   (0U)\r
-#define   SCU_GENERAL_DTSCON_PWD_Msk   (0x00000001U  << SCU_GENERAL_DTSCON_PWD_Pos)\r
-\r
-#define   SCU_GENERAL_DTSCON_START_Pos         (1U)\r
-#define   SCU_GENERAL_DTSCON_START_Msk         (0x00000001U  << SCU_GENERAL_DTSCON_START_Pos)\r
-\r
-#define   SCU_GENERAL_DTSCON_OFFSET_Pos        (4U)\r
-#define   SCU_GENERAL_DTSCON_OFFSET_Msk        (0x0000007FU  << SCU_GENERAL_DTSCON_OFFSET_Pos)\r
-\r
-#define   SCU_GENERAL_DTSCON_GAIN_Pos          (11U)\r
-#define   SCU_GENERAL_DTSCON_GAIN_Msk          (0x0000003FU  << SCU_GENERAL_DTSCON_GAIN_Pos)\r
-\r
-#define   SCU_GENERAL_DTSCON_REFTRIM_Pos       (17U)\r
-#define   SCU_GENERAL_DTSCON_REFTRIM_Msk       (0x00000007U  << SCU_GENERAL_DTSCON_REFTRIM_Pos)\r
-\r
-#define   SCU_GENERAL_DTSCON_BGTRIM_Pos        (20U)\r
-#define   SCU_GENERAL_DTSCON_BGTRIM_Msk        (0x0000000FU  << SCU_GENERAL_DTSCON_BGTRIM_Pos)\r
-\r
-/* SCU_GENERAL_DTSSTAT  =  Die Temperature Sensor Status Register*/\r
-#define   SCU_GENERAL_DTSSTAT_RESULT_Pos       (0U)\r
-#define   SCU_GENERAL_DTSSTAT_RESULT_Msk       (0x000003FFU  << SCU_GENERAL_DTSSTAT_RESULT_Pos)\r
-\r
-#define   SCU_GENERAL_DTSSTAT_RDY_Pos          (14U)\r
-#define   SCU_GENERAL_DTSSTAT_RDY_Msk          (0x00000001U  << SCU_GENERAL_DTSSTAT_RDY_Pos)\r
-\r
-#define   SCU_GENERAL_DTSSTAT_BUSY_Pos         (15U)\r
-#define   SCU_GENERAL_DTSSTAT_BUSY_Msk         (0x00000001U  << SCU_GENERAL_DTSSTAT_BUSY_Pos)\r
-\r
-/* SCU_GENERAL_SDMMCDEL  =  SD-MMC Delay Control Register*/\r
-#define   SCU_GENERAL_SDMMCDEL_TAPEN_Pos       (0U)\r
-#define   SCU_GENERAL_SDMMCDEL_TAPEN_Msk       (0x00000001U  << SCU_GENERAL_SDMMCDEL_TAPEN_Pos)\r
-\r
-#define   SCU_GENERAL_SDMMCDEL_DLYCTRL_Pos     (2U)\r
-#define   SCU_GENERAL_SDMMCDEL_DLYCTRL_Msk     (0x00000003U  << SCU_GENERAL_SDMMCDEL_DLYCTRL_Pos)\r
-\r
-#define   SCU_GENERAL_SDMMCDEL_TAPDEL_Pos      (4U)\r
-#define   SCU_GENERAL_SDMMCDEL_TAPDEL_Msk      (0x0000000FU  << SCU_GENERAL_SDMMCDEL_TAPDEL_Pos)\r
-\r
-/* SCU_GENERAL_GORCEN  =  Out of Range Comparator Enable Register 0*/\r
-#define   SCU_GENERAL_GORCEN_ENORC6_Pos        (6U)\r
-#define   SCU_GENERAL_GORCEN_ENORC6_Msk        (0x00000001U  << SCU_GENERAL_GORCEN_ENORC6_Pos)\r
-\r
-#define   SCU_GENERAL_GORCEN_ENORC7_Pos        (7U)\r
-#define   SCU_GENERAL_GORCEN_ENORC7_Msk        (0x00000001U  << SCU_GENERAL_GORCEN_ENORC7_Pos)\r
-\r
-/* SCU_GENERAL_MIRRSTS  =  Mirror Update Status Register*/\r
-#define   SCU_GENERAL_MIRRSTS_HDSTAT_Pos       (0U)\r
-#define   SCU_GENERAL_MIRRSTS_HDSTAT_Msk       (0x00000001U  << SCU_GENERAL_MIRRSTS_HDSTAT_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_HDCLR_Pos        (1U)\r
-#define   SCU_GENERAL_MIRRSTS_HDCLR_Msk        (0x00000001U  << SCU_GENERAL_MIRRSTS_HDCLR_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_HDSET_Pos        (2U)\r
-#define   SCU_GENERAL_MIRRSTS_HDSET_Msk        (0x00000001U  << SCU_GENERAL_MIRRSTS_HDSET_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_HDCR_Pos         (3U)\r
-#define   SCU_GENERAL_MIRRSTS_HDCR_Msk         (0x00000001U  << SCU_GENERAL_MIRRSTS_HDCR_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_OSCSITRIM_Pos    (4U)\r
-#define   SCU_GENERAL_MIRRSTS_OSCSITRIM_Msk    (0x00000001U  << SCU_GENERAL_MIRRSTS_OSCSITRIM_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos    (5U)\r
-#define   SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk    (0x00000001U  << SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos    (6U)\r
-#define   SCU_GENERAL_MIRRSTS_OSCULSTAT_Msk    (0x00000001U  << SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos    (7U)\r
-#define   SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk    (0x00000001U  << SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_RTC_CTR_Pos      (8U)\r
-#define   SCU_GENERAL_MIRRSTS_RTC_CTR_Msk      (0x00000001U  << SCU_GENERAL_MIRRSTS_RTC_CTR_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos    (9U)\r
-#define   SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk    (0x00000001U  << SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos    (10U)\r
-#define   SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk    (0x00000001U  << SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos     (11U)\r
-#define   SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk     (0x00000001U  << SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos     (12U)\r
-#define   SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk     (0x00000001U  << SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos)\r
-\r
-#define   SCU_GENERAL_MIRRSTS_RMX_Pos          (13U)\r
-#define   SCU_GENERAL_MIRRSTS_RMX_Msk          (0x00000001U  << SCU_GENERAL_MIRRSTS_RMX_Pos)\r
-\r
-/* SCU_GENERAL_RMACR  =  Retention Memory Access Control Register*/\r
-#define   SCU_GENERAL_RMACR_RDWR_Pos   (0U)\r
-#define   SCU_GENERAL_RMACR_RDWR_Msk   (0x00000001U  << SCU_GENERAL_RMACR_RDWR_Pos)\r
-\r
-#define   SCU_GENERAL_RMACR_ADDR_Pos   (16U)\r
-#define   SCU_GENERAL_RMACR_ADDR_Msk   (0x0000000FU  << SCU_GENERAL_RMACR_ADDR_Pos)\r
-\r
-/* SCU_GENERAL_RMDATA  =  Retention Memory Access Data Register*/\r
-#define   SCU_GENERAL_RMDATA_DATA_Pos          (0U)\r
-#define   SCU_GENERAL_RMDATA_DATA_Msk          (0xFFFFFFFFU  << SCU_GENERAL_RMDATA_DATA_Pos)\r
-\r
-/* SCU_PARITY_PETE  =  Parity Error Trap Enable Register*/\r
-#define   SCU_PARITY_PETE_PETEPS_Pos   (0U)\r
-#define   SCU_PARITY_PETE_PETEPS_Msk   (0x00000001U  << SCU_PARITY_PETE_PETEPS_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETEDS1_Pos          (1U)\r
-#define   SCU_PARITY_PETE_PETEDS1_Msk          (0x00000001U  << SCU_PARITY_PETE_PETEDS1_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETEDS2_Pos          (2U)\r
-#define   SCU_PARITY_PETE_PETEDS2_Msk          (0x00000001U  << SCU_PARITY_PETE_PETEDS2_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETEU0_Pos   (8U)\r
-#define   SCU_PARITY_PETE_PETEU0_Msk   (0x00000001U  << SCU_PARITY_PETE_PETEU0_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETEU1_Pos   (9U)\r
-#define   SCU_PARITY_PETE_PETEU1_Msk   (0x00000001U  << SCU_PARITY_PETE_PETEU1_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETEU2_Pos   (10U)\r
-#define   SCU_PARITY_PETE_PETEU2_Msk   (0x00000001U  << SCU_PARITY_PETE_PETEU2_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETEMC_Pos   (12U)\r
-#define   SCU_PARITY_PETE_PETEMC_Msk   (0x00000001U  << SCU_PARITY_PETE_PETEMC_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETEPPRF_Pos         (13U)\r
-#define   SCU_PARITY_PETE_PETEPPRF_Msk         (0x00000001U  << SCU_PARITY_PETE_PETEPPRF_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETEUSB_Pos          (16U)\r
-#define   SCU_PARITY_PETE_PETEUSB_Msk          (0x00000001U  << SCU_PARITY_PETE_PETEUSB_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETEETH0TX_Pos       (17U)\r
-#define   SCU_PARITY_PETE_PETEETH0TX_Msk       (0x00000001U  << SCU_PARITY_PETE_PETEETH0TX_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETEETH0RX_Pos       (18U)\r
-#define   SCU_PARITY_PETE_PETEETH0RX_Msk       (0x00000001U  << SCU_PARITY_PETE_PETEETH0RX_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETESD0_Pos          (19U)\r
-#define   SCU_PARITY_PETE_PETESD0_Msk          (0x00000001U  << SCU_PARITY_PETE_PETESD0_Pos)\r
-\r
-#define   SCU_PARITY_PETE_PETESD1_Pos          (20U)\r
-#define   SCU_PARITY_PETE_PETESD1_Msk          (0x00000001U  << SCU_PARITY_PETE_PETESD1_Pos)\r
-\r
-/* SCU_PARITY_MCHKCON  =  Memory Checking Control Register*/\r
-#define   SCU_PARITY_MCHKCON_SELPS_Pos         (0U)\r
-#define   SCU_PARITY_MCHKCON_SELPS_Msk         (0x00000001U  << SCU_PARITY_MCHKCON_SELPS_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_SELDS1_Pos        (1U)\r
-#define   SCU_PARITY_MCHKCON_SELDS1_Msk        (0x00000001U  << SCU_PARITY_MCHKCON_SELDS1_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_SELDS2_Pos        (2U)\r
-#define   SCU_PARITY_MCHKCON_SELDS2_Msk        (0x00000001U  << SCU_PARITY_MCHKCON_SELDS2_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_USIC0DRA_Pos      (8U)\r
-#define   SCU_PARITY_MCHKCON_USIC0DRA_Msk      (0x00000001U  << SCU_PARITY_MCHKCON_USIC0DRA_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_USIC1DRA_Pos      (9U)\r
-#define   SCU_PARITY_MCHKCON_USIC1DRA_Msk      (0x00000001U  << SCU_PARITY_MCHKCON_USIC1DRA_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_USIC2DRA_Pos      (10U)\r
-#define   SCU_PARITY_MCHKCON_USIC2DRA_Msk      (0x00000001U  << SCU_PARITY_MCHKCON_USIC2DRA_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_MCANDRA_Pos       (12U)\r
-#define   SCU_PARITY_MCHKCON_MCANDRA_Msk       (0x00000001U  << SCU_PARITY_MCHKCON_MCANDRA_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_PPRFDRA_Pos       (13U)\r
-#define   SCU_PARITY_MCHKCON_PPRFDRA_Msk       (0x00000001U  << SCU_PARITY_MCHKCON_PPRFDRA_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_SELUSB_Pos        (16U)\r
-#define   SCU_PARITY_MCHKCON_SELUSB_Msk        (0x00000001U  << SCU_PARITY_MCHKCON_SELUSB_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_SELETH0TX_Pos     (17U)\r
-#define   SCU_PARITY_MCHKCON_SELETH0TX_Msk     (0x00000001U  << SCU_PARITY_MCHKCON_SELETH0TX_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_SELETH0RX_Pos     (18U)\r
-#define   SCU_PARITY_MCHKCON_SELETH0RX_Msk     (0x00000001U  << SCU_PARITY_MCHKCON_SELETH0RX_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_SELSD0_Pos        (19U)\r
-#define   SCU_PARITY_MCHKCON_SELSD0_Msk        (0x00000001U  << SCU_PARITY_MCHKCON_SELSD0_Pos)\r
-\r
-#define   SCU_PARITY_MCHKCON_SELSD1_Pos        (20U)\r
-#define   SCU_PARITY_MCHKCON_SELSD1_Msk        (0x00000001U  << SCU_PARITY_MCHKCON_SELSD1_Pos)\r
-\r
-/* SCU_PARITY_PEEN  =  Parity Error Enable Register*/\r
-#define   SCU_PARITY_PEEN_PEENPS_Pos   (0U)\r
-#define   SCU_PARITY_PEEN_PEENPS_Msk   (0x00000001U  << SCU_PARITY_PEEN_PEENPS_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENDS1_Pos          (1U)\r
-#define   SCU_PARITY_PEEN_PEENDS1_Msk          (0x00000001U  << SCU_PARITY_PEEN_PEENDS1_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENDS2_Pos          (2U)\r
-#define   SCU_PARITY_PEEN_PEENDS2_Msk          (0x00000001U  << SCU_PARITY_PEEN_PEENDS2_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENU0_Pos   (8U)\r
-#define   SCU_PARITY_PEEN_PEENU0_Msk   (0x00000001U  << SCU_PARITY_PEEN_PEENU0_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENU1_Pos   (9U)\r
-#define   SCU_PARITY_PEEN_PEENU1_Msk   (0x00000001U  << SCU_PARITY_PEEN_PEENU1_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENU2_Pos   (10U)\r
-#define   SCU_PARITY_PEEN_PEENU2_Msk   (0x00000001U  << SCU_PARITY_PEEN_PEENU2_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENMC_Pos   (12U)\r
-#define   SCU_PARITY_PEEN_PEENMC_Msk   (0x00000001U  << SCU_PARITY_PEEN_PEENMC_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENPPRF_Pos         (13U)\r
-#define   SCU_PARITY_PEEN_PEENPPRF_Msk         (0x00000001U  << SCU_PARITY_PEEN_PEENPPRF_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENUSB_Pos          (16U)\r
-#define   SCU_PARITY_PEEN_PEENUSB_Msk          (0x00000001U  << SCU_PARITY_PEEN_PEENUSB_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENETH0TX_Pos       (17U)\r
-#define   SCU_PARITY_PEEN_PEENETH0TX_Msk       (0x00000001U  << SCU_PARITY_PEEN_PEENETH0TX_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENETH0RX_Pos       (18U)\r
-#define   SCU_PARITY_PEEN_PEENETH0RX_Msk       (0x00000001U  << SCU_PARITY_PEEN_PEENETH0RX_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENSD0_Pos          (19U)\r
-#define   SCU_PARITY_PEEN_PEENSD0_Msk          (0x00000001U  << SCU_PARITY_PEEN_PEENSD0_Pos)\r
-\r
-#define   SCU_PARITY_PEEN_PEENSD1_Pos          (20U)\r
-#define   SCU_PARITY_PEEN_PEENSD1_Msk          (0x00000001U  << SCU_PARITY_PEEN_PEENSD1_Pos)\r
-\r
-/* SCU_PARITY_PERSTEN  =  Parity Error Reset Enable Register*/\r
-#define   SCU_PARITY_PERSTEN_RSEN_Pos          (0U)\r
-#define   SCU_PARITY_PERSTEN_RSEN_Msk          (0x00000001U  << SCU_PARITY_PERSTEN_RSEN_Pos)\r
-\r
-/* SCU_PARITY_PEFLAG  =  Parity Error Flag Register*/\r
-#define   SCU_PARITY_PEFLAG_PEFPS_Pos          (0U)\r
-#define   SCU_PARITY_PEFLAG_PEFPS_Msk          (0x00000001U  << SCU_PARITY_PEFLAG_PEFPS_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PEFDS1_Pos         (1U)\r
-#define   SCU_PARITY_PEFLAG_PEFDS1_Msk         (0x00000001U  << SCU_PARITY_PEFLAG_PEFDS1_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PEFDS2_Pos         (2U)\r
-#define   SCU_PARITY_PEFLAG_PEFDS2_Msk         (0x00000001U  << SCU_PARITY_PEFLAG_PEFDS2_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PEFU0_Pos          (8U)\r
-#define   SCU_PARITY_PEFLAG_PEFU0_Msk          (0x00000001U  << SCU_PARITY_PEFLAG_PEFU0_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PEFU1_Pos          (9U)\r
-#define   SCU_PARITY_PEFLAG_PEFU1_Msk          (0x00000001U  << SCU_PARITY_PEFLAG_PEFU1_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PEFU2_Pos          (10U)\r
-#define   SCU_PARITY_PEFLAG_PEFU2_Msk          (0x00000001U  << SCU_PARITY_PEFLAG_PEFU2_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PEFMC_Pos          (12U)\r
-#define   SCU_PARITY_PEFLAG_PEFMC_Msk          (0x00000001U  << SCU_PARITY_PEFLAG_PEFMC_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PEFPPRF_Pos        (13U)\r
-#define   SCU_PARITY_PEFLAG_PEFPPRF_Msk        (0x00000001U  << SCU_PARITY_PEFLAG_PEFPPRF_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PEUSB_Pos          (16U)\r
-#define   SCU_PARITY_PEFLAG_PEUSB_Msk          (0x00000001U  << SCU_PARITY_PEFLAG_PEUSB_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PEETH0TX_Pos       (17U)\r
-#define   SCU_PARITY_PEFLAG_PEETH0TX_Msk       (0x00000001U  << SCU_PARITY_PEFLAG_PEETH0TX_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PEETH0RX_Pos       (18U)\r
-#define   SCU_PARITY_PEFLAG_PEETH0RX_Msk       (0x00000001U  << SCU_PARITY_PEFLAG_PEETH0RX_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PESD0_Pos          (19U)\r
-#define   SCU_PARITY_PEFLAG_PESD0_Msk          (0x00000001U  << SCU_PARITY_PEFLAG_PESD0_Pos)\r
-\r
-#define   SCU_PARITY_PEFLAG_PESD1_Pos          (20U)\r
-#define   SCU_PARITY_PEFLAG_PESD1_Msk          (0x00000001U  << SCU_PARITY_PEFLAG_PESD1_Pos)\r
-\r
-/* SCU_PARITY_PMTPR  =  Parity Memory Test Pattern Register*/\r
-#define   SCU_PARITY_PMTPR_PRD_Pos     (8U)\r
-#define   SCU_PARITY_PMTPR_PRD_Msk     (0x000000FFU  << SCU_PARITY_PMTPR_PRD_Pos)\r
-\r
-#define   SCU_PARITY_PMTPR_PWR_Pos     (0U)\r
-#define   SCU_PARITY_PMTPR_PWR_Msk     (0x000000FFU  << SCU_PARITY_PMTPR_PWR_Pos)\r
-\r
-/* SCU_PARITY_PMTSR  =  Parity Memory Test Select Register*/\r
-#define   SCU_PARITY_PMTSR_MTENPS_Pos          (0U)\r
-#define   SCU_PARITY_PMTSR_MTENPS_Msk          (0x00000001U  << SCU_PARITY_PMTSR_MTENPS_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTENDS1_Pos         (1U)\r
-#define   SCU_PARITY_PMTSR_MTENDS1_Msk         (0x00000001U  << SCU_PARITY_PMTSR_MTENDS1_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTENDS2_Pos         (2U)\r
-#define   SCU_PARITY_PMTSR_MTENDS2_Msk         (0x00000001U  << SCU_PARITY_PMTSR_MTENDS2_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTEU0_Pos   (8U)\r
-#define   SCU_PARITY_PMTSR_MTEU0_Msk   (0x00000001U  << SCU_PARITY_PMTSR_MTEU0_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTEU1_Pos   (9U)\r
-#define   SCU_PARITY_PMTSR_MTEU1_Msk   (0x00000001U  << SCU_PARITY_PMTSR_MTEU1_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTEU2_Pos   (10U)\r
-#define   SCU_PARITY_PMTSR_MTEU2_Msk   (0x00000001U  << SCU_PARITY_PMTSR_MTEU2_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTEMC_Pos   (12U)\r
-#define   SCU_PARITY_PMTSR_MTEMC_Msk   (0x00000001U  << SCU_PARITY_PMTSR_MTEMC_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTEPPRF_Pos         (13U)\r
-#define   SCU_PARITY_PMTSR_MTEPPRF_Msk         (0x00000001U  << SCU_PARITY_PMTSR_MTEPPRF_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTUSB_Pos   (16U)\r
-#define   SCU_PARITY_PMTSR_MTUSB_Msk   (0x00000001U  << SCU_PARITY_PMTSR_MTUSB_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTETH0TX_Pos        (17U)\r
-#define   SCU_PARITY_PMTSR_MTETH0TX_Msk        (0x00000001U  << SCU_PARITY_PMTSR_MTETH0TX_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTETH0RX_Pos        (18U)\r
-#define   SCU_PARITY_PMTSR_MTETH0RX_Msk        (0x00000001U  << SCU_PARITY_PMTSR_MTETH0RX_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTSD0_Pos   (19U)\r
-#define   SCU_PARITY_PMTSR_MTSD0_Msk   (0x00000001U  << SCU_PARITY_PMTSR_MTSD0_Pos)\r
-\r
-#define   SCU_PARITY_PMTSR_MTSD1_Pos   (20U)\r
-#define   SCU_PARITY_PMTSR_MTSD1_Msk   (0x00000001U  << SCU_PARITY_PMTSR_MTSD1_Pos)\r
-\r
-/* SCU_INTERRUPT_SRSTAT  =  SCU Service Request Status*/\r
-#define   SCU_INTERRUPT_SRSTAT_PRWARN_Pos      (0U)\r
-#define   SCU_INTERRUPT_SRSTAT_PRWARN_Msk      (0x00000001U  << SCU_INTERRUPT_SRSTAT_PRWARN_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_PI_Pos          (1U)\r
-#define   SCU_INTERRUPT_SRSTAT_PI_Msk          (0x00000001U  << SCU_INTERRUPT_SRSTAT_PI_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_AI_Pos          (2U)\r
-#define   SCU_INTERRUPT_SRSTAT_AI_Msk          (0x00000001U  << SCU_INTERRUPT_SRSTAT_AI_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_DLROVR_Pos      (3U)\r
-#define   SCU_INTERRUPT_SRSTAT_DLROVR_Msk      (0x00000001U  << SCU_INTERRUPT_SRSTAT_DLROVR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_HDSTAT_Pos      (16U)\r
-#define   SCU_INTERRUPT_SRSTAT_HDSTAT_Msk      (0x00000001U  << SCU_INTERRUPT_SRSTAT_HDSTAT_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_HDCLR_Pos       (17U)\r
-#define   SCU_INTERRUPT_SRSTAT_HDCLR_Msk       (0x00000001U  << SCU_INTERRUPT_SRSTAT_HDCLR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_HDSET_Pos       (18U)\r
-#define   SCU_INTERRUPT_SRSTAT_HDSET_Msk       (0x00000001U  << SCU_INTERRUPT_SRSTAT_HDSET_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_HDCR_Pos        (19U)\r
-#define   SCU_INTERRUPT_SRSTAT_HDCR_Msk        (0x00000001U  << SCU_INTERRUPT_SRSTAT_HDCR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_OSCSITRIM_Pos   (20U)\r
-#define   SCU_INTERRUPT_SRSTAT_OSCSITRIM_Msk   (0x00000001U  << SCU_INTERRUPT_SRSTAT_OSCSITRIM_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos   (21U)\r
-#define   SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk   (0x00000001U  << SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos   (22U)\r
-#define   SCU_INTERRUPT_SRSTAT_OSCULSTAT_Msk   (0x00000001U  << SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos   (23U)\r
-#define   SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk   (0x00000001U  << SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos     (24U)\r
-#define   SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk     (0x00000001U  << SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos   (25U)\r
-#define   SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk   (0x00000001U  << SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos   (26U)\r
-#define   SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk   (0x00000001U  << SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos    (27U)\r
-#define   SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk    (0x00000001U  << SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos    (28U)\r
-#define   SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk    (0x00000001U  << SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSTAT_RMX_Pos         (29U)\r
-#define   SCU_INTERRUPT_SRSTAT_RMX_Msk         (0x00000001U  << SCU_INTERRUPT_SRSTAT_RMX_Pos)\r
-\r
-/* SCU_INTERRUPT_SRRAW  =  SCU Raw Service Request Status*/\r
-#define   SCU_INTERRUPT_SRRAW_PRWARN_Pos       (0U)\r
-#define   SCU_INTERRUPT_SRRAW_PRWARN_Msk       (0x00000001U  << SCU_INTERRUPT_SRRAW_PRWARN_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_PI_Pos   (1U)\r
-#define   SCU_INTERRUPT_SRRAW_PI_Msk   (0x00000001U  << SCU_INTERRUPT_SRRAW_PI_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_AI_Pos   (2U)\r
-#define   SCU_INTERRUPT_SRRAW_AI_Msk   (0x00000001U  << SCU_INTERRUPT_SRRAW_AI_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_DLROVR_Pos       (3U)\r
-#define   SCU_INTERRUPT_SRRAW_DLROVR_Msk       (0x00000001U  << SCU_INTERRUPT_SRRAW_DLROVR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_HDSTAT_Pos       (16U)\r
-#define   SCU_INTERRUPT_SRRAW_HDSTAT_Msk       (0x00000001U  << SCU_INTERRUPT_SRRAW_HDSTAT_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_HDCLR_Pos        (17U)\r
-#define   SCU_INTERRUPT_SRRAW_HDCLR_Msk        (0x00000001U  << SCU_INTERRUPT_SRRAW_HDCLR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_HDSET_Pos        (18U)\r
-#define   SCU_INTERRUPT_SRRAW_HDSET_Msk        (0x00000001U  << SCU_INTERRUPT_SRRAW_HDSET_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_HDCR_Pos         (19U)\r
-#define   SCU_INTERRUPT_SRRAW_HDCR_Msk         (0x00000001U  << SCU_INTERRUPT_SRRAW_HDCR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_OSCSITRIM_Pos    (20U)\r
-#define   SCU_INTERRUPT_SRRAW_OSCSITRIM_Msk    (0x00000001U  << SCU_INTERRUPT_SRRAW_OSCSITRIM_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos    (21U)\r
-#define   SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk    (0x00000001U  << SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos    (22U)\r
-#define   SCU_INTERRUPT_SRRAW_OSCULSTAT_Msk    (0x00000001U  << SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos    (23U)\r
-#define   SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk    (0x00000001U  << SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_RTC_CTR_Pos      (24U)\r
-#define   SCU_INTERRUPT_SRRAW_RTC_CTR_Msk      (0x00000001U  << SCU_INTERRUPT_SRRAW_RTC_CTR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos    (25U)\r
-#define   SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk    (0x00000001U  << SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos    (26U)\r
-#define   SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk    (0x00000001U  << SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos     (27U)\r
-#define   SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk     (0x00000001U  << SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos     (28U)\r
-#define   SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk     (0x00000001U  << SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRRAW_RMX_Pos          (29U)\r
-#define   SCU_INTERRUPT_SRRAW_RMX_Msk          (0x00000001U  << SCU_INTERRUPT_SRRAW_RMX_Pos)\r
-\r
-/* SCU_INTERRUPT_SRMSK  =  SCU Service Request Mask*/\r
-#define   SCU_INTERRUPT_SRMSK_PRWARN_Pos       (0U)\r
-#define   SCU_INTERRUPT_SRMSK_PRWARN_Msk       (0x00000001U  << SCU_INTERRUPT_SRMSK_PRWARN_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_PI_Pos   (1U)\r
-#define   SCU_INTERRUPT_SRMSK_PI_Msk   (0x00000001U  << SCU_INTERRUPT_SRMSK_PI_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_AI_Pos   (2U)\r
-#define   SCU_INTERRUPT_SRMSK_AI_Msk   (0x00000001U  << SCU_INTERRUPT_SRMSK_AI_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_DLROVR_Pos       (3U)\r
-#define   SCU_INTERRUPT_SRMSK_DLROVR_Msk       (0x00000001U  << SCU_INTERRUPT_SRMSK_DLROVR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_HDSTAT_Pos       (16U)\r
-#define   SCU_INTERRUPT_SRMSK_HDSTAT_Msk       (0x00000001U  << SCU_INTERRUPT_SRMSK_HDSTAT_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_HDCLR_Pos        (17U)\r
-#define   SCU_INTERRUPT_SRMSK_HDCLR_Msk        (0x00000001U  << SCU_INTERRUPT_SRMSK_HDCLR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_HDSET_Pos        (18U)\r
-#define   SCU_INTERRUPT_SRMSK_HDSET_Msk        (0x00000001U  << SCU_INTERRUPT_SRMSK_HDSET_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_HDCR_Pos         (19U)\r
-#define   SCU_INTERRUPT_SRMSK_HDCR_Msk         (0x00000001U  << SCU_INTERRUPT_SRMSK_HDCR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_OSCSITRIM_Pos    (20U)\r
-#define   SCU_INTERRUPT_SRMSK_OSCSITRIM_Msk    (0x00000001U  << SCU_INTERRUPT_SRMSK_OSCSITRIM_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos    (21U)\r
-#define   SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk    (0x00000001U  << SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos    (22U)\r
-#define   SCU_INTERRUPT_SRMSK_OSCULSTAT_Msk    (0x00000001U  << SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos    (23U)\r
-#define   SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk    (0x00000001U  << SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_RTC_CTR_Pos      (24U)\r
-#define   SCU_INTERRUPT_SRMSK_RTC_CTR_Msk      (0x00000001U  << SCU_INTERRUPT_SRMSK_RTC_CTR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos    (25U)\r
-#define   SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk    (0x00000001U  << SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos    (26U)\r
-#define   SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk    (0x00000001U  << SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos     (27U)\r
-#define   SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk     (0x00000001U  << SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos     (28U)\r
-#define   SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk     (0x00000001U  << SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRMSK_RMX_Pos          (29U)\r
-#define   SCU_INTERRUPT_SRMSK_RMX_Msk          (0x00000001U  << SCU_INTERRUPT_SRMSK_RMX_Pos)\r
-\r
-/* SCU_INTERRUPT_SRCLR  =  SCU Service Request Clear*/\r
-#define   SCU_INTERRUPT_SRCLR_PRWARN_Pos       (0U)\r
-#define   SCU_INTERRUPT_SRCLR_PRWARN_Msk       (0x00000001U  << SCU_INTERRUPT_SRCLR_PRWARN_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_PI_Pos   (1U)\r
-#define   SCU_INTERRUPT_SRCLR_PI_Msk   (0x00000001U  << SCU_INTERRUPT_SRCLR_PI_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_AI_Pos   (2U)\r
-#define   SCU_INTERRUPT_SRCLR_AI_Msk   (0x00000001U  << SCU_INTERRUPT_SRCLR_AI_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_DLROVR_Pos       (3U)\r
-#define   SCU_INTERRUPT_SRCLR_DLROVR_Msk       (0x00000001U  << SCU_INTERRUPT_SRCLR_DLROVR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_HDSTAT_Pos       (16U)\r
-#define   SCU_INTERRUPT_SRCLR_HDSTAT_Msk       (0x00000001U  << SCU_INTERRUPT_SRCLR_HDSTAT_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_HDCLR_Pos        (17U)\r
-#define   SCU_INTERRUPT_SRCLR_HDCLR_Msk        (0x00000001U  << SCU_INTERRUPT_SRCLR_HDCLR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_HDSET_Pos        (18U)\r
-#define   SCU_INTERRUPT_SRCLR_HDSET_Msk        (0x00000001U  << SCU_INTERRUPT_SRCLR_HDSET_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_HDCR_Pos         (19U)\r
-#define   SCU_INTERRUPT_SRCLR_HDCR_Msk         (0x00000001U  << SCU_INTERRUPT_SRCLR_HDCR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_OSCSITRIM_Pos    (20U)\r
-#define   SCU_INTERRUPT_SRCLR_OSCSITRIM_Msk    (0x00000001U  << SCU_INTERRUPT_SRCLR_OSCSITRIM_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos    (21U)\r
-#define   SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk    (0x00000001U  << SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos    (22U)\r
-#define   SCU_INTERRUPT_SRCLR_OSCULSTAT_Msk    (0x00000001U  << SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos    (23U)\r
-#define   SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk    (0x00000001U  << SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_RTC_CTR_Pos      (24U)\r
-#define   SCU_INTERRUPT_SRCLR_RTC_CTR_Msk      (0x00000001U  << SCU_INTERRUPT_SRCLR_RTC_CTR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos    (25U)\r
-#define   SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk    (0x00000001U  << SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos    (26U)\r
-#define   SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk    (0x00000001U  << SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos     (27U)\r
-#define   SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk     (0x00000001U  << SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos     (28U)\r
-#define   SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk     (0x00000001U  << SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRCLR_RMX_Pos          (29U)\r
-#define   SCU_INTERRUPT_SRCLR_RMX_Msk          (0x00000001U  << SCU_INTERRUPT_SRCLR_RMX_Pos)\r
-\r
-/* SCU_INTERRUPT_SRSET  =  SCU Service Request Set*/\r
-#define   SCU_INTERRUPT_SRSET_PRWARN_Pos       (0U)\r
-#define   SCU_INTERRUPT_SRSET_PRWARN_Msk       (0x00000001U  << SCU_INTERRUPT_SRSET_PRWARN_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_PI_Pos   (1U)\r
-#define   SCU_INTERRUPT_SRSET_PI_Msk   (0x00000001U  << SCU_INTERRUPT_SRSET_PI_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_AI_Pos   (2U)\r
-#define   SCU_INTERRUPT_SRSET_AI_Msk   (0x00000001U  << SCU_INTERRUPT_SRSET_AI_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_DLROVR_Pos       (3U)\r
-#define   SCU_INTERRUPT_SRSET_DLROVR_Msk       (0x00000001U  << SCU_INTERRUPT_SRSET_DLROVR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_HDSTAT_Pos       (16U)\r
-#define   SCU_INTERRUPT_SRSET_HDSTAT_Msk       (0x00000001U  << SCU_INTERRUPT_SRSET_HDSTAT_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_HDCRCLR_Pos      (17U)\r
-#define   SCU_INTERRUPT_SRSET_HDCRCLR_Msk      (0x00000001U  << SCU_INTERRUPT_SRSET_HDCRCLR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_HDCRSET_Pos      (18U)\r
-#define   SCU_INTERRUPT_SRSET_HDCRSET_Msk      (0x00000001U  << SCU_INTERRUPT_SRSET_HDCRSET_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_HDCR_Pos         (19U)\r
-#define   SCU_INTERRUPT_SRSET_HDCR_Msk         (0x00000001U  << SCU_INTERRUPT_SRSET_HDCR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_OSCSITRIM_Pos    (20U)\r
-#define   SCU_INTERRUPT_SRSET_OSCSITRIM_Msk    (0x00000001U  << SCU_INTERRUPT_SRSET_OSCSITRIM_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_OSCSICTRL_Pos    (21U)\r
-#define   SCU_INTERRUPT_SRSET_OSCSICTRL_Msk    (0x00000001U  << SCU_INTERRUPT_SRSET_OSCSICTRL_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_OSCULSTAT_Pos    (22U)\r
-#define   SCU_INTERRUPT_SRSET_OSCULSTAT_Msk    (0x00000001U  << SCU_INTERRUPT_SRSET_OSCULSTAT_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_OSCULCTRL_Pos    (23U)\r
-#define   SCU_INTERRUPT_SRSET_OSCULCTRL_Msk    (0x00000001U  << SCU_INTERRUPT_SRSET_OSCULCTRL_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_RTC_CTR_Pos      (24U)\r
-#define   SCU_INTERRUPT_SRSET_RTC_CTR_Msk      (0x00000001U  << SCU_INTERRUPT_SRSET_RTC_CTR_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos    (25U)\r
-#define   SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk    (0x00000001U  << SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos    (26U)\r
-#define   SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk    (0x00000001U  << SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_RTC_TIM0_Pos     (27U)\r
-#define   SCU_INTERRUPT_SRSET_RTC_TIM0_Msk     (0x00000001U  << SCU_INTERRUPT_SRSET_RTC_TIM0_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_RTC_TIM1_Pos     (28U)\r
-#define   SCU_INTERRUPT_SRSET_RTC_TIM1_Msk     (0x00000001U  << SCU_INTERRUPT_SRSET_RTC_TIM1_Pos)\r
-\r
-#define   SCU_INTERRUPT_SRSET_RMX_Pos          (29U)\r
-#define   SCU_INTERRUPT_SRSET_RMX_Msk          (0x00000001U  << SCU_INTERRUPT_SRSET_RMX_Pos)\r
-\r
-/* SCU_INTERRUPT_NMIREQEN  =  SCU Service Request Mask*/\r
-#define   SCU_INTERRUPT_NMIREQEN_PRWARN_Pos    (0U)\r
-#define   SCU_INTERRUPT_NMIREQEN_PRWARN_Msk    (0x00000001U  << SCU_INTERRUPT_NMIREQEN_PRWARN_Pos)\r
-\r
-#define   SCU_INTERRUPT_NMIREQEN_PI_Pos        (1U)\r
-#define   SCU_INTERRUPT_NMIREQEN_PI_Msk        (0x00000001U  << SCU_INTERRUPT_NMIREQEN_PI_Pos)\r
-\r
-#define   SCU_INTERRUPT_NMIREQEN_AI_Pos        (2U)\r
-#define   SCU_INTERRUPT_NMIREQEN_AI_Msk        (0x00000001U  << SCU_INTERRUPT_NMIREQEN_AI_Pos)\r
-\r
-#define   SCU_INTERRUPT_NMIREQEN_ERU00_Pos     (16U)\r
-#define   SCU_INTERRUPT_NMIREQEN_ERU00_Msk     (0x00000001U  << SCU_INTERRUPT_NMIREQEN_ERU00_Pos)\r
-\r
-#define   SCU_INTERRUPT_NMIREQEN_ERU01_Pos     (17U)\r
-#define   SCU_INTERRUPT_NMIREQEN_ERU01_Msk     (0x00000001U  << SCU_INTERRUPT_NMIREQEN_ERU01_Pos)\r
-\r
-#define   SCU_INTERRUPT_NMIREQEN_ERU02_Pos     (18U)\r
-#define   SCU_INTERRUPT_NMIREQEN_ERU02_Msk     (0x00000001U  << SCU_INTERRUPT_NMIREQEN_ERU02_Pos)\r
-\r
-#define   SCU_INTERRUPT_NMIREQEN_ERU03_Pos     (19U)\r
-#define   SCU_INTERRUPT_NMIREQEN_ERU03_Msk     (0x00000001U  << SCU_INTERRUPT_NMIREQEN_ERU03_Pos)\r
-\r
-/* SCU_TRAP_TRAPSTAT  =  Trap Status Register*/\r
-#define   SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos       (0U)\r
-#define   SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk       (0x00000001U  << SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos       (2U)\r
-#define   SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk       (0x00000001U  << SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos       (3U)\r
-#define   SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk       (0x00000001U  << SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSTAT_PET_Pos    (4U)\r
-#define   SCU_TRAP_TRAPSTAT_PET_Msk    (0x00000001U  << SCU_TRAP_TRAPSTAT_PET_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSTAT_BRWNT_Pos          (5U)\r
-#define   SCU_TRAP_TRAPSTAT_BRWNT_Msk          (0x00000001U  << SCU_TRAP_TRAPSTAT_BRWNT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSTAT_ULPWDGT_Pos        (6U)\r
-#define   SCU_TRAP_TRAPSTAT_ULPWDGT_Msk        (0x00000001U  << SCU_TRAP_TRAPSTAT_ULPWDGT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSTAT_BWERR0T_Pos        (7U)\r
-#define   SCU_TRAP_TRAPSTAT_BWERR0T_Msk        (0x00000001U  << SCU_TRAP_TRAPSTAT_BWERR0T_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSTAT_BWERR1T_Pos        (8U)\r
-#define   SCU_TRAP_TRAPSTAT_BWERR1T_Msk        (0x00000001U  << SCU_TRAP_TRAPSTAT_BWERR1T_Pos)\r
-\r
-/* SCU_TRAP_TRAPRAW  =  Trap Raw Status Register*/\r
-#define   SCU_TRAP_TRAPRAW_SOSCWDGT_Pos        (0U)\r
-#define   SCU_TRAP_TRAPRAW_SOSCWDGT_Msk        (0x00000001U  << SCU_TRAP_TRAPRAW_SOSCWDGT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPRAW_SVCOLCKT_Pos        (2U)\r
-#define   SCU_TRAP_TRAPRAW_SVCOLCKT_Msk        (0x00000001U  << SCU_TRAP_TRAPRAW_SVCOLCKT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPRAW_UVCOLCKT_Pos        (3U)\r
-#define   SCU_TRAP_TRAPRAW_UVCOLCKT_Msk        (0x00000001U  << SCU_TRAP_TRAPRAW_UVCOLCKT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPRAW_PET_Pos     (4U)\r
-#define   SCU_TRAP_TRAPRAW_PET_Msk     (0x00000001U  << SCU_TRAP_TRAPRAW_PET_Pos)\r
-\r
-#define   SCU_TRAP_TRAPRAW_BRWNT_Pos   (5U)\r
-#define   SCU_TRAP_TRAPRAW_BRWNT_Msk   (0x00000001U  << SCU_TRAP_TRAPRAW_BRWNT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPRAW_ULPWDGT_Pos         (6U)\r
-#define   SCU_TRAP_TRAPRAW_ULPWDGT_Msk         (0x00000001U  << SCU_TRAP_TRAPRAW_ULPWDGT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPRAW_BWERR0T_Pos         (7U)\r
-#define   SCU_TRAP_TRAPRAW_BWERR0T_Msk         (0x00000001U  << SCU_TRAP_TRAPRAW_BWERR0T_Pos)\r
-\r
-#define   SCU_TRAP_TRAPRAW_BWERR1T_Pos         (8U)\r
-#define   SCU_TRAP_TRAPRAW_BWERR1T_Msk         (0x00000001U  << SCU_TRAP_TRAPRAW_BWERR1T_Pos)\r
-\r
-/* SCU_TRAP_TRAPDIS  =  Trap Disable Register*/\r
-#define   SCU_TRAP_TRAPDIS_SOSCWDGT_Pos        (0U)\r
-#define   SCU_TRAP_TRAPDIS_SOSCWDGT_Msk        (0x00000001U  << SCU_TRAP_TRAPDIS_SOSCWDGT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPDIS_SVCOLCKT_Pos        (2U)\r
-#define   SCU_TRAP_TRAPDIS_SVCOLCKT_Msk        (0x00000001U  << SCU_TRAP_TRAPDIS_SVCOLCKT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPDIS_UVCOLCKT_Pos        (3U)\r
-#define   SCU_TRAP_TRAPDIS_UVCOLCKT_Msk        (0x00000001U  << SCU_TRAP_TRAPDIS_UVCOLCKT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPDIS_PET_Pos     (4U)\r
-#define   SCU_TRAP_TRAPDIS_PET_Msk     (0x00000001U  << SCU_TRAP_TRAPDIS_PET_Pos)\r
-\r
-#define   SCU_TRAP_TRAPDIS_BRWNT_Pos   (5U)\r
-#define   SCU_TRAP_TRAPDIS_BRWNT_Msk   (0x00000001U  << SCU_TRAP_TRAPDIS_BRWNT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPDIS_ULPWDGT_Pos         (6U)\r
-#define   SCU_TRAP_TRAPDIS_ULPWDGT_Msk         (0x00000001U  << SCU_TRAP_TRAPDIS_ULPWDGT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPDIS_BWERR0T_Pos         (7U)\r
-#define   SCU_TRAP_TRAPDIS_BWERR0T_Msk         (0x00000001U  << SCU_TRAP_TRAPDIS_BWERR0T_Pos)\r
-\r
-#define   SCU_TRAP_TRAPDIS_BWERR1T_Pos         (8U)\r
-#define   SCU_TRAP_TRAPDIS_BWERR1T_Msk         (0x00000001U  << SCU_TRAP_TRAPDIS_BWERR1T_Pos)\r
-\r
-/* SCU_TRAP_TRAPCLR  =  Trap Clear Register*/\r
-#define   SCU_TRAP_TRAPCLR_SOSCWDGT_Pos        (0U)\r
-#define   SCU_TRAP_TRAPCLR_SOSCWDGT_Msk        (0x00000001U  << SCU_TRAP_TRAPCLR_SOSCWDGT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPCLR_SVCOLCKT_Pos        (2U)\r
-#define   SCU_TRAP_TRAPCLR_SVCOLCKT_Msk        (0x00000001U  << SCU_TRAP_TRAPCLR_SVCOLCKT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPCLR_UVCOLCKT_Pos        (3U)\r
-#define   SCU_TRAP_TRAPCLR_UVCOLCKT_Msk        (0x00000001U  << SCU_TRAP_TRAPCLR_UVCOLCKT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPCLR_PET_Pos     (4U)\r
-#define   SCU_TRAP_TRAPCLR_PET_Msk     (0x00000001U  << SCU_TRAP_TRAPCLR_PET_Pos)\r
-\r
-#define   SCU_TRAP_TRAPCLR_BRWNT_Pos   (5U)\r
-#define   SCU_TRAP_TRAPCLR_BRWNT_Msk   (0x00000001U  << SCU_TRAP_TRAPCLR_BRWNT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPCLR_ULPWDGT_Pos         (6U)\r
-#define   SCU_TRAP_TRAPCLR_ULPWDGT_Msk         (0x00000001U  << SCU_TRAP_TRAPCLR_ULPWDGT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPCLR_BWERR0T_Pos         (7U)\r
-#define   SCU_TRAP_TRAPCLR_BWERR0T_Msk         (0x00000001U  << SCU_TRAP_TRAPCLR_BWERR0T_Pos)\r
-\r
-#define   SCU_TRAP_TRAPCLR_BWERR1T_Pos         (8U)\r
-#define   SCU_TRAP_TRAPCLR_BWERR1T_Msk         (0x00000001U  << SCU_TRAP_TRAPCLR_BWERR1T_Pos)\r
-\r
-/* SCU_TRAP_TRAPSET  =  Trap Set Register*/\r
-#define   SCU_TRAP_TRAPSET_SOSCWDGT_Pos        (0U)\r
-#define   SCU_TRAP_TRAPSET_SOSCWDGT_Msk        (0x00000001U  << SCU_TRAP_TRAPSET_SOSCWDGT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSET_SVCOLCKT_Pos        (2U)\r
-#define   SCU_TRAP_TRAPSET_SVCOLCKT_Msk        (0x00000001U  << SCU_TRAP_TRAPSET_SVCOLCKT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSET_UVCOLCKT_Pos        (3U)\r
-#define   SCU_TRAP_TRAPSET_UVCOLCKT_Msk        (0x00000001U  << SCU_TRAP_TRAPSET_UVCOLCKT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSET_PET_Pos     (4U)\r
-#define   SCU_TRAP_TRAPSET_PET_Msk     (0x00000001U  << SCU_TRAP_TRAPSET_PET_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSET_BRWNT_Pos   (5U)\r
-#define   SCU_TRAP_TRAPSET_BRWNT_Msk   (0x00000001U  << SCU_TRAP_TRAPSET_BRWNT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSET_ULPWDT_Pos          (6U)\r
-#define   SCU_TRAP_TRAPSET_ULPWDT_Msk          (0x00000001U  << SCU_TRAP_TRAPSET_ULPWDT_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSET_BWERR0T_Pos         (7U)\r
-#define   SCU_TRAP_TRAPSET_BWERR0T_Msk         (0x00000001U  << SCU_TRAP_TRAPSET_BWERR0T_Pos)\r
-\r
-#define   SCU_TRAP_TRAPSET_BWERR1T_Pos         (8U)\r
-#define   SCU_TRAP_TRAPSET_BWERR1T_Msk         (0x00000001U  << SCU_TRAP_TRAPSET_BWERR1T_Pos)\r
-\r
-\r
-\r
-/***   SCU Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* SCU_HIBERNATE_HDSTAT  =  Hibernate Domain Control & Status Register*/\r
-#define   SCU_HIBERNATE_HDSTAT_EPEV_Pos        (0U)\r
-#define   SCU_HIBERNATE_HDSTAT_EPEV_Msk        (0x00000001U  << SCU_HIBERNATE_HDSTAT_EPEV_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDSTAT_ENEV_Pos        (1U)\r
-#define   SCU_HIBERNATE_HDSTAT_ENEV_Msk        (0x00000001U  << SCU_HIBERNATE_HDSTAT_ENEV_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDSTAT_RTCEV_Pos       (2U)\r
-#define   SCU_HIBERNATE_HDSTAT_RTCEV_Msk       (0x00000001U  << SCU_HIBERNATE_HDSTAT_RTCEV_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDSTAT_ULPWDG_Pos      (3U)\r
-#define   SCU_HIBERNATE_HDSTAT_ULPWDG_Msk      (0x00000001U  << SCU_HIBERNATE_HDSTAT_ULPWDG_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos     (4U)\r
-#define   SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk     (0x00000001U  << SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos)\r
-\r
-/* SCU_HIBERNATE_HDCLR  =  Hibernate Domain Status Clear Register*/\r
-#define   SCU_HIBERNATE_HDCLR_EPEV_Pos         (0U)\r
-#define   SCU_HIBERNATE_HDCLR_EPEV_Msk         (0x00000001U  << SCU_HIBERNATE_HDCLR_EPEV_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCLR_ENEV_Pos         (1U)\r
-#define   SCU_HIBERNATE_HDCLR_ENEV_Msk         (0x00000001U  << SCU_HIBERNATE_HDCLR_ENEV_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCLR_RTCEV_Pos        (2U)\r
-#define   SCU_HIBERNATE_HDCLR_RTCEV_Msk        (0x00000001U  << SCU_HIBERNATE_HDCLR_RTCEV_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCLR_ULPWDG_Pos       (3U)\r
-#define   SCU_HIBERNATE_HDCLR_ULPWDG_Msk       (0x00000001U  << SCU_HIBERNATE_HDCLR_ULPWDG_Pos)\r
-\r
-/* SCU_HIBERNATE_HDSET  =  Hibernate Domain Status Set Register*/\r
-#define   SCU_HIBERNATE_HDSET_EPEV_Pos         (0U)\r
-#define   SCU_HIBERNATE_HDSET_EPEV_Msk         (0x00000001U  << SCU_HIBERNATE_HDSET_EPEV_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDSET_ENEV_Pos         (1U)\r
-#define   SCU_HIBERNATE_HDSET_ENEV_Msk         (0x00000001U  << SCU_HIBERNATE_HDSET_ENEV_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDSET_RTCEV_Pos        (2U)\r
-#define   SCU_HIBERNATE_HDSET_RTCEV_Msk        (0x00000001U  << SCU_HIBERNATE_HDSET_RTCEV_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDSET_ULPWDG_Pos       (3U)\r
-#define   SCU_HIBERNATE_HDSET_ULPWDG_Msk       (0x00000001U  << SCU_HIBERNATE_HDSET_ULPWDG_Pos)\r
-\r
-/* SCU_HIBERNATE_HDCR  =  Hibernate Domain Configuration Register*/\r
-#define   SCU_HIBERNATE_HDCR_WKPEP_Pos         (0U)\r
-#define   SCU_HIBERNATE_HDCR_WKPEP_Msk         (0x00000001U  << SCU_HIBERNATE_HDCR_WKPEP_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_WKPEN_Pos         (1U)\r
-#define   SCU_HIBERNATE_HDCR_WKPEN_Msk         (0x00000001U  << SCU_HIBERNATE_HDCR_WKPEN_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_RTCE_Pos          (2U)\r
-#define   SCU_HIBERNATE_HDCR_RTCE_Msk          (0x00000001U  << SCU_HIBERNATE_HDCR_RTCE_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_ULPWDGEN_Pos      (3U)\r
-#define   SCU_HIBERNATE_HDCR_ULPWDGEN_Msk      (0x00000001U  << SCU_HIBERNATE_HDCR_ULPWDGEN_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_HIB_Pos   (4U)\r
-#define   SCU_HIBERNATE_HDCR_HIB_Msk   (0x00000001U  << SCU_HIBERNATE_HDCR_HIB_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_RCS_Pos   (6U)\r
-#define   SCU_HIBERNATE_HDCR_RCS_Msk   (0x00000001U  << SCU_HIBERNATE_HDCR_RCS_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_STDBYSEL_Pos      (7U)\r
-#define   SCU_HIBERNATE_HDCR_STDBYSEL_Msk      (0x00000001U  << SCU_HIBERNATE_HDCR_STDBYSEL_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_WKUPSEL_Pos       (8U)\r
-#define   SCU_HIBERNATE_HDCR_WKUPSEL_Msk       (0x00000001U  << SCU_HIBERNATE_HDCR_WKUPSEL_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_GPI0SEL_Pos       (10U)\r
-#define   SCU_HIBERNATE_HDCR_GPI0SEL_Msk       (0x00000001U  << SCU_HIBERNATE_HDCR_GPI0SEL_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_HIBIO0POL_Pos     (12U)\r
-#define   SCU_HIBERNATE_HDCR_HIBIO0POL_Msk     (0x00000001U  << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_HIBIO1POL_Pos     (13U)\r
-#define   SCU_HIBERNATE_HDCR_HIBIO1POL_Msk     (0x00000001U  << SCU_HIBERNATE_HDCR_HIBIO1POL_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos     (16U)\r
-#define   SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk     (0x0000000FU  << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos)\r
-\r
-#define   SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos     (20U)\r
-#define   SCU_HIBERNATE_HDCR_HIBIO1SEL_Msk     (0x0000000FU  << SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos)\r
-\r
-/* SCU_HIBERNATE_OSCSICTRL  =  OSC_SI Control Register*/\r
-#define   SCU_HIBERNATE_OSCSICTRL_PWD_Pos      (0U)\r
-#define   SCU_HIBERNATE_OSCSICTRL_PWD_Msk      (0x00000001U  << SCU_HIBERNATE_OSCSICTRL_PWD_Pos)\r
-\r
-/* SCU_HIBERNATE_OSCULSTAT  =  OSC_ULP Status Register*/\r
-#define   SCU_HIBERNATE_OSCULSTAT_X1D_Pos      (0U)\r
-#define   SCU_HIBERNATE_OSCULSTAT_X1D_Msk      (0x00000001U  << SCU_HIBERNATE_OSCULSTAT_X1D_Pos)\r
-\r
-/* SCU_HIBERNATE_OSCULCTRL  =  OSC_ULP Control Register*/\r
-#define   SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos    (0U)\r
-#define   SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk    (0x00000001U  << SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos)\r
-\r
-#define   SCU_HIBERNATE_OSCULCTRL_MODE_Pos     (4U)\r
-#define   SCU_HIBERNATE_OSCULCTRL_MODE_Msk     (0x00000003U  << SCU_HIBERNATE_OSCULCTRL_MODE_Pos)\r
-\r
-\r
-/***   SCU Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* SCU_POWER_PWRSTAT  =  PCU Status Register*/\r
-#define   SCU_POWER_PWRSTAT_HIBEN_Pos          (0U)\r
-#define   SCU_POWER_PWRSTAT_HIBEN_Msk          (0x00000001U  << SCU_POWER_PWRSTAT_HIBEN_Pos)\r
-\r
-#define   SCU_POWER_PWRSTAT_HPSS_Pos   (1U)\r
-#define   SCU_POWER_PWRSTAT_HPSS_Msk   (0x00000001U  << SCU_POWER_PWRSTAT_HPSS_Pos)\r
-\r
-#define   SCU_POWER_PWRSTAT_USBPHYPDQ_Pos      (16U)\r
-#define   SCU_POWER_PWRSTAT_USBPHYPDQ_Msk      (0x00000001U  << SCU_POWER_PWRSTAT_USBPHYPDQ_Pos)\r
-\r
-#define   SCU_POWER_PWRSTAT_USBOTGEN_Pos       (17U)\r
-#define   SCU_POWER_PWRSTAT_USBOTGEN_Msk       (0x00000001U  << SCU_POWER_PWRSTAT_USBOTGEN_Pos)\r
-\r
-#define   SCU_POWER_PWRSTAT_USBPUWQ_Pos        (18U)\r
-#define   SCU_POWER_PWRSTAT_USBPUWQ_Msk        (0x00000001U  << SCU_POWER_PWRSTAT_USBPUWQ_Pos)\r
-\r
-/* SCU_POWER_PWRSET  =  PCU Set Control Register*/\r
-#define   SCU_POWER_PWRSET_HIB_Pos     (0U)\r
-#define   SCU_POWER_PWRSET_HIB_Msk     (0x00000001U  << SCU_POWER_PWRSET_HIB_Pos)\r
-\r
-#define   SCU_POWER_PWRSET_USBPHYPDQ_Pos       (16U)\r
-#define   SCU_POWER_PWRSET_USBPHYPDQ_Msk       (0x00000001U  << SCU_POWER_PWRSET_USBPHYPDQ_Pos)\r
-\r
-#define   SCU_POWER_PWRSET_USBOTGEN_Pos        (17U)\r
-#define   SCU_POWER_PWRSET_USBOTGEN_Msk        (0x00000001U  << SCU_POWER_PWRSET_USBOTGEN_Pos)\r
-\r
-#define   SCU_POWER_PWRSET_USBPUWQ_Pos         (18U)\r
-#define   SCU_POWER_PWRSET_USBPUWQ_Msk         (0x00000001U  << SCU_POWER_PWRSET_USBPUWQ_Pos)\r
-\r
-/* SCU_POWER_PWRCLR  =  PCU Clear Control Register*/\r
-#define   SCU_POWER_PWRCLR_HIB_Pos     (0U)\r
-#define   SCU_POWER_PWRCLR_HIB_Msk     (0x00000001U  << SCU_POWER_PWRCLR_HIB_Pos)\r
-\r
-#define   SCU_POWER_PWRCLR_USBPHYPDQ_Pos       (16U)\r
-#define   SCU_POWER_PWRCLR_USBPHYPDQ_Msk       (0x00000001U  << SCU_POWER_PWRCLR_USBPHYPDQ_Pos)\r
-\r
-#define   SCU_POWER_PWRCLR_USBOTGEN_Pos        (17U)\r
-#define   SCU_POWER_PWRCLR_USBOTGEN_Msk        (0x00000001U  << SCU_POWER_PWRCLR_USBOTGEN_Pos)\r
-\r
-#define   SCU_POWER_PWRCLR_USBPUWQ_Pos         (18U)\r
-#define   SCU_POWER_PWRCLR_USBPUWQ_Msk         (0x00000001U  << SCU_POWER_PWRCLR_USBPUWQ_Pos)\r
-\r
-/* SCU_POWER_EVRSTAT  =  EVR Status Register*/\r
-#define   SCU_POWER_EVRSTAT_OV13_Pos   (1U)\r
-#define   SCU_POWER_EVRSTAT_OV13_Msk   (0x00000001U  << SCU_POWER_EVRSTAT_OV13_Pos)\r
-\r
-/* SCU_POWER_EVRVADCSTAT  =  EVR VADC Status Register*/\r
-#define   SCU_POWER_EVRVADCSTAT_VADC13V_Pos    (0U)\r
-#define   SCU_POWER_EVRVADCSTAT_VADC13V_Msk    (0x000000FFU  << SCU_POWER_EVRVADCSTAT_VADC13V_Pos)\r
-\r
-#define   SCU_POWER_EVRVADCSTAT_VADC33V_Pos    (8U)\r
-#define   SCU_POWER_EVRVADCSTAT_VADC33V_Msk    (0x000000FFU  << SCU_POWER_EVRVADCSTAT_VADC33V_Pos)\r
-\r
-/* SCU_POWER_PWRMON  =  EVR Power Monitor Control Register*/\r
-#define   SCU_POWER_PWRMON_THRS_Pos    (0U)\r
-#define   SCU_POWER_PWRMON_THRS_Msk    (0x000000FFU  << SCU_POWER_PWRMON_THRS_Pos)\r
-\r
-#define   SCU_POWER_PWRMON_INTV_Pos    (8U)\r
-#define   SCU_POWER_PWRMON_INTV_Msk    (0x000000FFU  << SCU_POWER_PWRMON_INTV_Pos)\r
-\r
-#define   SCU_POWER_PWRMON_ENB_Pos     (16U)\r
-#define   SCU_POWER_PWRMON_ENB_Msk     (0x00000001U  << SCU_POWER_PWRMON_ENB_Pos)\r
-\r
-\r
-/***   SCU Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* SCU_RESET_RSTSTAT  =  RCU Reset Status*/\r
-#define   SCU_RESET_RSTSTAT_RSTSTAT_Pos        (0U)\r
-#define   SCU_RESET_RSTSTAT_RSTSTAT_Msk        (0x000000FFU  << SCU_RESET_RSTSTAT_RSTSTAT_Pos)\r
-\r
-#define   SCU_RESET_RSTSTAT_HIBWK_Pos          (8U)\r
-#define   SCU_RESET_RSTSTAT_HIBWK_Msk          (0x00000001U  << SCU_RESET_RSTSTAT_HIBWK_Pos)\r
-\r
-#define   SCU_RESET_RSTSTAT_HIBRS_Pos          (9U)\r
-#define   SCU_RESET_RSTSTAT_HIBRS_Msk          (0x00000001U  << SCU_RESET_RSTSTAT_HIBRS_Pos)\r
-\r
-#define   SCU_RESET_RSTSTAT_LCKEN_Pos          (10U)\r
-#define   SCU_RESET_RSTSTAT_LCKEN_Msk          (0x00000001U  << SCU_RESET_RSTSTAT_LCKEN_Pos)\r
-\r
-/* SCU_RESET_RSTSET  =  RCU Reset Set Register*/\r
-#define   SCU_RESET_RSTSET_HIBWK_Pos   (8U)\r
-#define   SCU_RESET_RSTSET_HIBWK_Msk   (0x00000001U  << SCU_RESET_RSTSET_HIBWK_Pos)\r
-\r
-#define   SCU_RESET_RSTSET_HIBRS_Pos   (9U)\r
-#define   SCU_RESET_RSTSET_HIBRS_Msk   (0x00000001U  << SCU_RESET_RSTSET_HIBRS_Pos)\r
-\r
-#define   SCU_RESET_RSTSET_LCKEN_Pos   (10U)\r
-#define   SCU_RESET_RSTSET_LCKEN_Msk   (0x00000001U  << SCU_RESET_RSTSET_LCKEN_Pos)\r
-\r
-/* SCU_RESET_RSTCLR  =  RCU Reset Clear Register*/\r
-#define   SCU_RESET_RSTCLR_RSCLR_Pos   (0U)\r
-#define   SCU_RESET_RSTCLR_RSCLR_Msk   (0x00000001U  << SCU_RESET_RSTCLR_RSCLR_Pos)\r
-\r
-#define   SCU_RESET_RSTCLR_HIBWK_Pos   (8U)\r
-#define   SCU_RESET_RSTCLR_HIBWK_Msk   (0x00000001U  << SCU_RESET_RSTCLR_HIBWK_Pos)\r
-\r
-#define   SCU_RESET_RSTCLR_HIBRS_Pos   (9U)\r
-#define   SCU_RESET_RSTCLR_HIBRS_Msk   (0x00000001U  << SCU_RESET_RSTCLR_HIBRS_Pos)\r
-\r
-#define   SCU_RESET_RSTCLR_LCKEN_Pos   (10U)\r
-#define   SCU_RESET_RSTCLR_LCKEN_Msk   (0x00000001U  << SCU_RESET_RSTCLR_LCKEN_Pos)\r
-\r
-/* SCU_RESET_PRSTAT0  =  RCU Peripheral x Reset Status*/\r
-#define   SCU_RESET_PRSTAT0_VADCRS_Pos         (0U)\r
-#define   SCU_RESET_PRSTAT0_VADCRS_Msk         (0x00000001U  << SCU_RESET_PRSTAT0_VADCRS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT0_DSDRS_Pos          (1U)\r
-#define   SCU_RESET_PRSTAT0_DSDRS_Msk          (0x00000001U  << SCU_RESET_PRSTAT0_DSDRS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT0_CCU40RS_Pos        (2U)\r
-#define   SCU_RESET_PRSTAT0_CCU40RS_Msk        (0x00000001U  << SCU_RESET_PRSTAT0_CCU40RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT0_CCU41RS_Pos        (3U)\r
-#define   SCU_RESET_PRSTAT0_CCU41RS_Msk        (0x00000001U  << SCU_RESET_PRSTAT0_CCU41RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT0_CCU42RS_Pos        (4U)\r
-#define   SCU_RESET_PRSTAT0_CCU42RS_Msk        (0x00000001U  << SCU_RESET_PRSTAT0_CCU42RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT0_CCU80RS_Pos        (7U)\r
-#define   SCU_RESET_PRSTAT0_CCU80RS_Msk        (0x00000001U  << SCU_RESET_PRSTAT0_CCU80RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT0_CCU81RS_Pos        (8U)\r
-#define   SCU_RESET_PRSTAT0_CCU81RS_Msk        (0x00000001U  << SCU_RESET_PRSTAT0_CCU81RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT0_POSIF0RS_Pos       (9U)\r
-#define   SCU_RESET_PRSTAT0_POSIF0RS_Msk       (0x00000001U  << SCU_RESET_PRSTAT0_POSIF0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT0_POSIF1RS_Pos       (10U)\r
-#define   SCU_RESET_PRSTAT0_POSIF1RS_Msk       (0x00000001U  << SCU_RESET_PRSTAT0_POSIF1RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT0_USIC0RS_Pos        (11U)\r
-#define   SCU_RESET_PRSTAT0_USIC0RS_Msk        (0x00000001U  << SCU_RESET_PRSTAT0_USIC0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT0_ERU1RS_Pos         (16U)\r
-#define   SCU_RESET_PRSTAT0_ERU1RS_Msk         (0x00000001U  << SCU_RESET_PRSTAT0_ERU1RS_Pos)\r
-\r
-/* SCU_RESET_PRSET0  =  RCU Peripheral x Reset Set*/\r
-#define   SCU_RESET_PRSET0_VADCRS_Pos          (0U)\r
-#define   SCU_RESET_PRSET0_VADCRS_Msk          (0x00000001U  << SCU_RESET_PRSET0_VADCRS_Pos)\r
-\r
-#define   SCU_RESET_PRSET0_DSDRS_Pos   (1U)\r
-#define   SCU_RESET_PRSET0_DSDRS_Msk   (0x00000001U  << SCU_RESET_PRSET0_DSDRS_Pos)\r
-\r
-#define   SCU_RESET_PRSET0_CCU40RS_Pos         (2U)\r
-#define   SCU_RESET_PRSET0_CCU40RS_Msk         (0x00000001U  << SCU_RESET_PRSET0_CCU40RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET0_CCU41RS_Pos         (3U)\r
-#define   SCU_RESET_PRSET0_CCU41RS_Msk         (0x00000001U  << SCU_RESET_PRSET0_CCU41RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET0_CCU42RS_Pos         (4U)\r
-#define   SCU_RESET_PRSET0_CCU42RS_Msk         (0x00000001U  << SCU_RESET_PRSET0_CCU42RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET0_CCU80RS_Pos         (7U)\r
-#define   SCU_RESET_PRSET0_CCU80RS_Msk         (0x00000001U  << SCU_RESET_PRSET0_CCU80RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET0_CCU81RS_Pos         (8U)\r
-#define   SCU_RESET_PRSET0_CCU81RS_Msk         (0x00000001U  << SCU_RESET_PRSET0_CCU81RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET0_POSIF0RS_Pos        (9U)\r
-#define   SCU_RESET_PRSET0_POSIF0RS_Msk        (0x00000001U  << SCU_RESET_PRSET0_POSIF0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET0_POSIF1RS_Pos        (10U)\r
-#define   SCU_RESET_PRSET0_POSIF1RS_Msk        (0x00000001U  << SCU_RESET_PRSET0_POSIF1RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET0_USIC0RS_Pos         (11U)\r
-#define   SCU_RESET_PRSET0_USIC0RS_Msk         (0x00000001U  << SCU_RESET_PRSET0_USIC0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET0_ERU1RS_Pos          (16U)\r
-#define   SCU_RESET_PRSET0_ERU1RS_Msk          (0x00000001U  << SCU_RESET_PRSET0_ERU1RS_Pos)\r
-\r
-/* SCU_RESET_PRCLR0  =  RCU Peripheral x Reset Clear*/\r
-#define   SCU_RESET_PRCLR0_VADCRS_Pos          (0U)\r
-#define   SCU_RESET_PRCLR0_VADCRS_Msk          (0x00000001U  << SCU_RESET_PRCLR0_VADCRS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR0_DSDRS_Pos   (1U)\r
-#define   SCU_RESET_PRCLR0_DSDRS_Msk   (0x00000001U  << SCU_RESET_PRCLR0_DSDRS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR0_CCU40RS_Pos         (2U)\r
-#define   SCU_RESET_PRCLR0_CCU40RS_Msk         (0x00000001U  << SCU_RESET_PRCLR0_CCU40RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR0_CCU41RS_Pos         (3U)\r
-#define   SCU_RESET_PRCLR0_CCU41RS_Msk         (0x00000001U  << SCU_RESET_PRCLR0_CCU41RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR0_CCU42RS_Pos         (4U)\r
-#define   SCU_RESET_PRCLR0_CCU42RS_Msk         (0x00000001U  << SCU_RESET_PRCLR0_CCU42RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR0_CCU80RS_Pos         (7U)\r
-#define   SCU_RESET_PRCLR0_CCU80RS_Msk         (0x00000001U  << SCU_RESET_PRCLR0_CCU80RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR0_CCU81RS_Pos         (8U)\r
-#define   SCU_RESET_PRCLR0_CCU81RS_Msk         (0x00000001U  << SCU_RESET_PRCLR0_CCU81RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR0_POSIF0RS_Pos        (9U)\r
-#define   SCU_RESET_PRCLR0_POSIF0RS_Msk        (0x00000001U  << SCU_RESET_PRCLR0_POSIF0RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR0_POSIF1RS_Pos        (10U)\r
-#define   SCU_RESET_PRCLR0_POSIF1RS_Msk        (0x00000001U  << SCU_RESET_PRCLR0_POSIF1RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR0_USIC0RS_Pos         (11U)\r
-#define   SCU_RESET_PRCLR0_USIC0RS_Msk         (0x00000001U  << SCU_RESET_PRCLR0_USIC0RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR0_ERU1RS_Pos          (16U)\r
-#define   SCU_RESET_PRCLR0_ERU1RS_Msk          (0x00000001U  << SCU_RESET_PRCLR0_ERU1RS_Pos)\r
-\r
-/* SCU_RESET_PRSTAT1  =  RCU Peripheral 1 Reset Status*/\r
-#define   SCU_RESET_PRSTAT1_CCU43RS_Pos        (0U)\r
-#define   SCU_RESET_PRSTAT1_CCU43RS_Msk        (0x00000001U  << SCU_RESET_PRSTAT1_CCU43RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos     (3U)\r
-#define   SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk     (0x00000001U  << SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT1_MCAN0RS_Pos        (4U)\r
-#define   SCU_RESET_PRSTAT1_MCAN0RS_Msk        (0x00000001U  << SCU_RESET_PRSTAT1_MCAN0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT1_DACRS_Pos          (5U)\r
-#define   SCU_RESET_PRSTAT1_DACRS_Msk          (0x00000001U  << SCU_RESET_PRSTAT1_DACRS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT1_MMCIRS_Pos         (6U)\r
-#define   SCU_RESET_PRSTAT1_MMCIRS_Msk         (0x00000001U  << SCU_RESET_PRSTAT1_MMCIRS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT1_USIC1RS_Pos        (7U)\r
-#define   SCU_RESET_PRSTAT1_USIC1RS_Msk        (0x00000001U  << SCU_RESET_PRSTAT1_USIC1RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT1_USIC2RS_Pos        (8U)\r
-#define   SCU_RESET_PRSTAT1_USIC2RS_Msk        (0x00000001U  << SCU_RESET_PRSTAT1_USIC2RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT1_PPORTSRS_Pos       (9U)\r
-#define   SCU_RESET_PRSTAT1_PPORTSRS_Msk       (0x00000001U  << SCU_RESET_PRSTAT1_PPORTSRS_Pos)\r
-\r
-/* SCU_RESET_PRSET1  =  RCU Peripheral 1 Reset Set*/\r
-#define   SCU_RESET_PRSET1_CCU43RS_Pos         (0U)\r
-#define   SCU_RESET_PRSET1_CCU43RS_Msk         (0x00000001U  << SCU_RESET_PRSET1_CCU43RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET1_LEDTSCU0RS_Pos      (3U)\r
-#define   SCU_RESET_PRSET1_LEDTSCU0RS_Msk      (0x00000001U  << SCU_RESET_PRSET1_LEDTSCU0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET1_MCAN0RS_Pos         (4U)\r
-#define   SCU_RESET_PRSET1_MCAN0RS_Msk         (0x00000001U  << SCU_RESET_PRSET1_MCAN0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET1_DACRS_Pos   (5U)\r
-#define   SCU_RESET_PRSET1_DACRS_Msk   (0x00000001U  << SCU_RESET_PRSET1_DACRS_Pos)\r
-\r
-#define   SCU_RESET_PRSET1_MMCIRS_Pos          (6U)\r
-#define   SCU_RESET_PRSET1_MMCIRS_Msk          (0x00000001U  << SCU_RESET_PRSET1_MMCIRS_Pos)\r
-\r
-#define   SCU_RESET_PRSET1_USIC1RS_Pos         (7U)\r
-#define   SCU_RESET_PRSET1_USIC1RS_Msk         (0x00000001U  << SCU_RESET_PRSET1_USIC1RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET1_USIC2RS_Pos         (8U)\r
-#define   SCU_RESET_PRSET1_USIC2RS_Msk         (0x00000001U  << SCU_RESET_PRSET1_USIC2RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET1_PPORTSRS_Pos        (9U)\r
-#define   SCU_RESET_PRSET1_PPORTSRS_Msk        (0x00000001U  << SCU_RESET_PRSET1_PPORTSRS_Pos)\r
-\r
-/* SCU_RESET_PRCLR1  =  RCU Peripheral 1 Reset Clear*/\r
-#define   SCU_RESET_PRCLR1_CCU43RS_Pos         (0U)\r
-#define   SCU_RESET_PRCLR1_CCU43RS_Msk         (0x00000001U  << SCU_RESET_PRCLR1_CCU43RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR1_LEDTSCU0RS_Pos      (3U)\r
-#define   SCU_RESET_PRCLR1_LEDTSCU0RS_Msk      (0x00000001U  << SCU_RESET_PRCLR1_LEDTSCU0RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR1_MCAN0RS_Pos         (4U)\r
-#define   SCU_RESET_PRCLR1_MCAN0RS_Msk         (0x00000001U  << SCU_RESET_PRCLR1_MCAN0RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR1_DACRS_Pos   (5U)\r
-#define   SCU_RESET_PRCLR1_DACRS_Msk   (0x00000001U  << SCU_RESET_PRCLR1_DACRS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR1_MMCIRS_Pos          (6U)\r
-#define   SCU_RESET_PRCLR1_MMCIRS_Msk          (0x00000001U  << SCU_RESET_PRCLR1_MMCIRS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR1_USIC1RS_Pos         (7U)\r
-#define   SCU_RESET_PRCLR1_USIC1RS_Msk         (0x00000001U  << SCU_RESET_PRCLR1_USIC1RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR1_USIC2RS_Pos         (8U)\r
-#define   SCU_RESET_PRCLR1_USIC2RS_Msk         (0x00000001U  << SCU_RESET_PRCLR1_USIC2RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR1_PPORTSRS_Pos        (9U)\r
-#define   SCU_RESET_PRCLR1_PPORTSRS_Msk        (0x00000001U  << SCU_RESET_PRCLR1_PPORTSRS_Pos)\r
-\r
-/* SCU_RESET_PRSTAT2  =  RCU Peripheral 2 Reset Status*/\r
-#define   SCU_RESET_PRSTAT2_WDTRS_Pos          (1U)\r
-#define   SCU_RESET_PRSTAT2_WDTRS_Msk          (0x00000001U  << SCU_RESET_PRSTAT2_WDTRS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT2_ETH0RS_Pos         (2U)\r
-#define   SCU_RESET_PRSTAT2_ETH0RS_Msk         (0x00000001U  << SCU_RESET_PRSTAT2_ETH0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT2_DMA0RS_Pos         (4U)\r
-#define   SCU_RESET_PRSTAT2_DMA0RS_Msk         (0x00000001U  << SCU_RESET_PRSTAT2_DMA0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT2_DMA1RS_Pos         (5U)\r
-#define   SCU_RESET_PRSTAT2_DMA1RS_Msk         (0x00000001U  << SCU_RESET_PRSTAT2_DMA1RS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT2_FCERS_Pos          (6U)\r
-#define   SCU_RESET_PRSTAT2_FCERS_Msk          (0x00000001U  << SCU_RESET_PRSTAT2_FCERS_Pos)\r
-\r
-#define   SCU_RESET_PRSTAT2_USBRS_Pos          (7U)\r
-#define   SCU_RESET_PRSTAT2_USBRS_Msk          (0x00000001U  << SCU_RESET_PRSTAT2_USBRS_Pos)\r
-\r
-/* SCU_RESET_PRSET2  =  RCU Peripheral 2 Reset Set*/\r
-#define   SCU_RESET_PRSET2_WDTRS_Pos   (1U)\r
-#define   SCU_RESET_PRSET2_WDTRS_Msk   (0x00000001U  << SCU_RESET_PRSET2_WDTRS_Pos)\r
-\r
-#define   SCU_RESET_PRSET2_ETH0RS_Pos          (2U)\r
-#define   SCU_RESET_PRSET2_ETH0RS_Msk          (0x00000001U  << SCU_RESET_PRSET2_ETH0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET2_DMA0RS_Pos          (4U)\r
-#define   SCU_RESET_PRSET2_DMA0RS_Msk          (0x00000001U  << SCU_RESET_PRSET2_DMA0RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET2_DMA1RS_Pos          (5U)\r
-#define   SCU_RESET_PRSET2_DMA1RS_Msk          (0x00000001U  << SCU_RESET_PRSET2_DMA1RS_Pos)\r
-\r
-#define   SCU_RESET_PRSET2_FCERS_Pos   (6U)\r
-#define   SCU_RESET_PRSET2_FCERS_Msk   (0x00000001U  << SCU_RESET_PRSET2_FCERS_Pos)\r
-\r
-#define   SCU_RESET_PRSET2_USBRS_Pos   (7U)\r
-#define   SCU_RESET_PRSET2_USBRS_Msk   (0x00000001U  << SCU_RESET_PRSET2_USBRS_Pos)\r
-\r
-/* SCU_RESET_PRCLR2  =  RCU Peripheral 2 Reset Clear*/\r
-#define   SCU_RESET_PRCLR2_WDTRS_Pos   (1U)\r
-#define   SCU_RESET_PRCLR2_WDTRS_Msk   (0x00000001U  << SCU_RESET_PRCLR2_WDTRS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR2_ETH0RS_Pos          (2U)\r
-#define   SCU_RESET_PRCLR2_ETH0RS_Msk          (0x00000001U  << SCU_RESET_PRCLR2_ETH0RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR2_DMA0RS_Pos          (4U)\r
-#define   SCU_RESET_PRCLR2_DMA0RS_Msk          (0x00000001U  << SCU_RESET_PRCLR2_DMA0RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR2_DMA1RS_Pos          (5U)\r
-#define   SCU_RESET_PRCLR2_DMA1RS_Msk          (0x00000001U  << SCU_RESET_PRCLR2_DMA1RS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR2_FCERS_Pos   (6U)\r
-#define   SCU_RESET_PRCLR2_FCERS_Msk   (0x00000001U  << SCU_RESET_PRCLR2_FCERS_Pos)\r
-\r
-#define   SCU_RESET_PRCLR2_USBRS_Pos   (7U)\r
-#define   SCU_RESET_PRCLR2_USBRS_Msk   (0x00000001U  << SCU_RESET_PRCLR2_USBRS_Pos)\r
-\r
-/* SCU_RESET_PRSTAT3  =  RCU Peripheral 3 Reset Status*/\r
-#define   SCU_RESET_PRSTAT3_EBURS_Pos          (2U)\r
-#define   SCU_RESET_PRSTAT3_EBURS_Msk          (0x00000001U  << SCU_RESET_PRSTAT3_EBURS_Pos)\r
-\r
-/* SCU_RESET_PRSET3  =  RCU Peripheral 3 Reset Set*/\r
-#define   SCU_RESET_PRSET3_EBURS_Pos   (2U)\r
-#define   SCU_RESET_PRSET3_EBURS_Msk   (0x00000001U  << SCU_RESET_PRSET3_EBURS_Pos)\r
-\r
-/* SCU_RESET_PRCLR3  =  RCU Peripheral 3 Reset Clear*/\r
-#define   SCU_RESET_PRCLR3_EBURS_Pos   (2U)\r
-#define   SCU_RESET_PRCLR3_EBURS_Msk   (0x00000001U  << SCU_RESET_PRCLR3_EBURS_Pos)\r
-\r
-\r
-\r
-/***   SDMMC Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* SDMMC_BLOCK_SIZE  =  Block Size Register*/\r
-#define   SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Pos        (15U)\r
-#define   SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Msk        (0x00000001U  << SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Pos)\r
-\r
-#define   SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Pos   (0U)\r
-#define   SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Msk   (0x00000FFFU  << SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Pos)\r
-\r
-/* SDMMC_BLOCK_COUNT  =  Block Count Register*/\r
-#define   SDMMC_BLOCK_COUNT_BLOCK_COUNT_Pos    (0U)\r
-#define   SDMMC_BLOCK_COUNT_BLOCK_COUNT_Msk    (0x0000FFFFU  << SDMMC_BLOCK_COUNT_BLOCK_COUNT_Pos)\r
-\r
-/* SDMMC_ARGUMENT1  =  Argument1 Register*/\r
-#define   SDMMC_ARGUMENT1_ARGUMENT1_Pos        (0U)\r
-#define   SDMMC_ARGUMENT1_ARGUMENT1_Msk        (0xFFFFFFFFU  << SDMMC_ARGUMENT1_ARGUMENT1_Pos)\r
-\r
-/* SDMMC_TRANSFER_MODE  =  Transfer Mode Register*/\r
-#define   SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Pos         (6U)\r
-#define   SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Msk         (0x00000001U  << SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Pos)\r
-\r
-#define   SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Pos   (5U)\r
-#define   SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Msk   (0x00000001U  << SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Pos)\r
-\r
-#define   SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos        (4U)\r
-#define   SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Msk        (0x00000001U  << SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos)\r
-\r
-#define   SDMMC_TRANSFER_MODE_ACMD_EN_Pos      (2U)\r
-#define   SDMMC_TRANSFER_MODE_ACMD_EN_Msk      (0x00000003U  << SDMMC_TRANSFER_MODE_ACMD_EN_Pos)\r
-\r
-#define   SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Pos       (1U)\r
-#define   SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Msk       (0x00000001U  << SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Pos)\r
-\r
-/* SDMMC_COMMAND  =  Command Register*/\r
-#define   SDMMC_COMMAND_CMD_IND_Pos    (8U)\r
-#define   SDMMC_COMMAND_CMD_IND_Msk    (0x0000003FU  << SDMMC_COMMAND_CMD_IND_Pos)\r
-\r
-#define   SDMMC_COMMAND_CMD_TYPE_Pos   (6U)\r
-#define   SDMMC_COMMAND_CMD_TYPE_Msk   (0x00000003U  << SDMMC_COMMAND_CMD_TYPE_Pos)\r
-\r
-#define   SDMMC_COMMAND_DATA_PRESENT_SELECT_Pos        (5U)\r
-#define   SDMMC_COMMAND_DATA_PRESENT_SELECT_Msk        (0x00000001U  << SDMMC_COMMAND_DATA_PRESENT_SELECT_Pos)\r
-\r
-#define   SDMMC_COMMAND_CMD_IND_CHECK_EN_Pos   (4U)\r
-#define   SDMMC_COMMAND_CMD_IND_CHECK_EN_Msk   (0x00000001U  << SDMMC_COMMAND_CMD_IND_CHECK_EN_Pos)\r
-\r
-#define   SDMMC_COMMAND_CMD_CRC_CHECK_EN_Pos   (3U)\r
-#define   SDMMC_COMMAND_CMD_CRC_CHECK_EN_Msk   (0x00000001U  << SDMMC_COMMAND_CMD_CRC_CHECK_EN_Pos)\r
-\r
-#define   SDMMC_COMMAND_RESP_TYPE_SELECT_Pos   (0U)\r
-#define   SDMMC_COMMAND_RESP_TYPE_SELECT_Msk   (0x00000003U  << SDMMC_COMMAND_RESP_TYPE_SELECT_Pos)\r
-\r
-/* SDMMC_RESPONSE0  =  Response x Register*/\r
-#define   SDMMC_RESPONSE0_RESPONSE1_Pos        (16U)\r
-#define   SDMMC_RESPONSE0_RESPONSE1_Msk        (0x0000FFFFU  << SDMMC_RESPONSE0_RESPONSE1_Pos)\r
-\r
-#define   SDMMC_RESPONSE0_RESPONSE0_Pos        (0U)\r
-#define   SDMMC_RESPONSE0_RESPONSE0_Msk        (0x0000FFFFU  << SDMMC_RESPONSE0_RESPONSE0_Pos)\r
-\r
-/* SDMMC_RESPONSE2  =  Response 2 Register*/\r
-#define   SDMMC_RESPONSE2_RESPONSE3_Pos        (16U)\r
-#define   SDMMC_RESPONSE2_RESPONSE3_Msk        (0x0000FFFFU  << SDMMC_RESPONSE2_RESPONSE3_Pos)\r
-\r
-#define   SDMMC_RESPONSE2_RESPONSE2_Pos        (0U)\r
-#define   SDMMC_RESPONSE2_RESPONSE2_Msk        (0x0000FFFFU  << SDMMC_RESPONSE2_RESPONSE2_Pos)\r
-\r
-/* SDMMC_RESPONSE4  =  Response 4 Register*/\r
-#define   SDMMC_RESPONSE4_RESPONSE5_Pos        (16U)\r
-#define   SDMMC_RESPONSE4_RESPONSE5_Msk        (0x0000FFFFU  << SDMMC_RESPONSE4_RESPONSE5_Pos)\r
-\r
-#define   SDMMC_RESPONSE4_RESPONSE4_Pos        (0U)\r
-#define   SDMMC_RESPONSE4_RESPONSE4_Msk        (0x0000FFFFU  << SDMMC_RESPONSE4_RESPONSE4_Pos)\r
-\r
-/* SDMMC_RESPONSE6  =  Response 6 Register*/\r
-#define   SDMMC_RESPONSE6_RESPONSE7_Pos        (16U)\r
-#define   SDMMC_RESPONSE6_RESPONSE7_Msk        (0x0000FFFFU  << SDMMC_RESPONSE6_RESPONSE7_Pos)\r
-\r
-#define   SDMMC_RESPONSE6_RESPONSE6_Pos        (0U)\r
-#define   SDMMC_RESPONSE6_RESPONSE6_Msk        (0x0000FFFFU  << SDMMC_RESPONSE6_RESPONSE6_Pos)\r
-\r
-/* SDMMC_DATA_BUFFER  =  Data Buffer Register*/\r
-#define   SDMMC_DATA_BUFFER_DATA_BUFFER_Pos    (0U)\r
-#define   SDMMC_DATA_BUFFER_DATA_BUFFER_Msk    (0xFFFFFFFFU  << SDMMC_DATA_BUFFER_DATA_BUFFER_Pos)\r
-\r
-/* SDMMC_PRESENT_STATE  =  Present State Register*/\r
-#define   SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Pos    (25U)\r
-#define   SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Msk    (0x0000000FU  << SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Pos       (24U)\r
-#define   SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Msk       (0x00000001U  << SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos    (20U)\r
-#define   SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Msk    (0x0000000FU  << SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Pos      (19U)\r
-#define   SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Msk      (0x00000001U  << SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Pos        (18U)\r
-#define   SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Msk        (0x00000001U  << SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Pos    (17U)\r
-#define   SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Msk    (0x00000001U  << SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_CARD_INSERTED_Pos        (16U)\r
-#define   SDMMC_PRESENT_STATE_CARD_INSERTED_Msk        (0x00000001U  << SDMMC_PRESENT_STATE_CARD_INSERTED_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Pos   (11U)\r
-#define   SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Msk   (0x00000001U  << SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Pos          (10U)\r
-#define   SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Msk          (0x00000001U  << SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Pos         (9U)\r
-#define   SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Msk         (0x00000001U  << SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Pos        (8U)\r
-#define   SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Msk        (0x00000001U  << SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Pos      (2U)\r
-#define   SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Msk      (0x00000001U  << SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Pos          (1U)\r
-#define   SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Msk          (0x00000001U  << SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Pos)\r
-\r
-#define   SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Pos          (0U)\r
-#define   SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Msk          (0x00000001U  << SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Pos)\r
-\r
-/* SDMMC_HOST_CTRL  =  Host Control Register*/\r
-#define   SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos   (7U)\r
-#define   SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Msk   (0x00000001U  << SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos)\r
-\r
-#define   SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos   (6U)\r
-#define   SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Msk   (0x00000001U  << SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos)\r
-\r
-#define   SDMMC_HOST_CTRL_HIGH_SPEED_EN_Pos    (2U)\r
-#define   SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk    (0x00000001U  << SDMMC_HOST_CTRL_HIGH_SPEED_EN_Pos)\r
-\r
-#define   SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos    (1U)\r
-#define   SDMMC_HOST_CTRL_DATA_TX_WIDTH_Msk    (0x00000001U  << SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos)\r
-\r
-#define   SDMMC_HOST_CTRL_LED_CTRL_Pos         (0U)\r
-#define   SDMMC_HOST_CTRL_LED_CTRL_Msk         (0x00000001U  << SDMMC_HOST_CTRL_LED_CTRL_Pos)\r
-\r
-/* SDMMC_POWER_CTRL  =  Power Control Register*/\r
-#define   SDMMC_POWER_CTRL_HARDWARE_RESET_Pos          (4U)\r
-#define   SDMMC_POWER_CTRL_HARDWARE_RESET_Msk          (0x00000001U  << SDMMC_POWER_CTRL_HARDWARE_RESET_Pos)\r
-\r
-#define   SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos      (1U)\r
-#define   SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Msk      (0x00000007U  << SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos)\r
-\r
-#define   SDMMC_POWER_CTRL_SD_BUS_POWER_Pos    (0U)\r
-#define   SDMMC_POWER_CTRL_SD_BUS_POWER_Msk    (0x00000001U  << SDMMC_POWER_CTRL_SD_BUS_POWER_Pos)\r
-\r
-/* SDMMC_BLOCK_GAP_CTRL  =  Block Gap Control Register*/\r
-#define   SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Pos    (4U)\r
-#define   SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Msk    (0x00000001U  << SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Pos)\r
-\r
-#define   SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Pos    (3U)\r
-#define   SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk    (0x00000001U  << SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Pos)\r
-\r
-#define   SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Pos      (2U)\r
-#define   SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Msk      (0x00000001U  << SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Pos)\r
-\r
-#define   SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos        (1U)\r
-#define   SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Msk        (0x00000001U  << SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos)\r
-\r
-#define   SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Pos   (0U)\r
-#define   SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Msk   (0x00000001U  << SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Pos)\r
-\r
-/* SDMMC_WAKEUPORT_CTRL  =  Wake-up Control Register*/\r
-#define   SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Pos    (2U)\r
-#define   SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Msk    (0x00000001U  << SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Pos)\r
-\r
-#define   SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Pos    (1U)\r
-#define   SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Msk    (0x00000001U  << SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Pos)\r
-\r
-#define   SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Pos    (0U)\r
-#define   SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Msk    (0x00000001U  << SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Pos)\r
-\r
-/* SDMMC_CLOCK_CTRL  =  Clock Control Register*/\r
-#define   SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos          (8U)\r
-#define   SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Msk          (0x000000FFU  << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos)\r
-\r
-#define   SDMMC_CLOCK_CTRL_SDCLOCK_EN_Pos      (2U)\r
-#define   SDMMC_CLOCK_CTRL_SDCLOCK_EN_Msk      (0x00000001U  << SDMMC_CLOCK_CTRL_SDCLOCK_EN_Pos)\r
-\r
-#define   SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Pos   (1U)\r
-#define   SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Msk   (0x00000001U  << SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Pos)\r
-\r
-#define   SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Pos       (0U)\r
-#define   SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Msk       (0x00000001U  << SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Pos)\r
-\r
-/* SDMMC_TIMEOUT_CTRL  =  Timeout Control Register*/\r
-#define   SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos   (0U)\r
-#define   SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Msk   (0x0000000FU  << SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos)\r
-\r
-/* SDMMC_SW_RESET  =  Software Reset Register*/\r
-#define   SDMMC_SW_RESET_SW_RST_DAT_LINE_Pos   (2U)\r
-#define   SDMMC_SW_RESET_SW_RST_DAT_LINE_Msk   (0x00000001U  << SDMMC_SW_RESET_SW_RST_DAT_LINE_Pos)\r
-\r
-#define   SDMMC_SW_RESET_SW_RST_CMD_LINE_Pos   (1U)\r
-#define   SDMMC_SW_RESET_SW_RST_CMD_LINE_Msk   (0x00000001U  << SDMMC_SW_RESET_SW_RST_CMD_LINE_Pos)\r
-\r
-#define   SDMMC_SW_RESET_SW_RST_ALL_Pos        (0U)\r
-#define   SDMMC_SW_RESET_SW_RST_ALL_Msk        (0x00000001U  << SDMMC_SW_RESET_SW_RST_ALL_Pos)\r
-\r
-/* SDMMC_INT_STATUS_NORM  =  Normal Interrupt Status Register*/\r
-#define   SDMMC_INT_STATUS_NORM_ERR_INT_Pos    (15U)\r
-#define   SDMMC_INT_STATUS_NORM_ERR_INT_Msk    (0x00000001U  << SDMMC_INT_STATUS_NORM_ERR_INT_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_NORM_CARD_INT_Pos   (8U)\r
-#define   SDMMC_INT_STATUS_NORM_CARD_INT_Msk   (0x00000001U  << SDMMC_INT_STATUS_NORM_CARD_INT_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Pos       (7U)\r
-#define   SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Msk       (0x00000001U  << SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_NORM_CARD_INS_Pos   (6U)\r
-#define   SDMMC_INT_STATUS_NORM_CARD_INS_Msk   (0x00000001U  << SDMMC_INT_STATUS_NORM_CARD_INS_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Pos    (5U)\r
-#define   SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Msk    (0x00000001U  << SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Pos   (4U)\r
-#define   SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Msk   (0x00000001U  << SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Pos    (2U)\r
-#define   SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Msk    (0x00000001U  << SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_NORM_TX_COMPLETE_Pos        (1U)\r
-#define   SDMMC_INT_STATUS_NORM_TX_COMPLETE_Msk        (0x00000001U  << SDMMC_INT_STATUS_NORM_TX_COMPLETE_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Pos       (0U)\r
-#define   SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Msk       (0x00000001U  << SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Pos)\r
-\r
-/* SDMMC_INT_STATUS_ERR  =  Error Interrupt Status Register*/\r
-#define   SDMMC_INT_STATUS_ERR_CEATA_ERR_Pos   (13U)\r
-#define   SDMMC_INT_STATUS_ERR_CEATA_ERR_Msk   (0x00000001U  << SDMMC_INT_STATUS_ERR_CEATA_ERR_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_ERR_ACMD_ERR_Pos    (8U)\r
-#define   SDMMC_INT_STATUS_ERR_ACMD_ERR_Msk    (0x00000001U  << SDMMC_INT_STATUS_ERR_ACMD_ERR_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Pos   (7U)\r
-#define   SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Msk   (0x00000001U  << SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Pos    (6U)\r
-#define   SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Msk    (0x00000001U  << SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Pos        (5U)\r
-#define   SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Msk        (0x00000001U  << SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Pos    (4U)\r
-#define   SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Msk    (0x00000001U  << SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Pos         (3U)\r
-#define   SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Msk         (0x00000001U  << SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Pos     (2U)\r
-#define   SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Msk     (0x00000001U  << SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Pos         (1U)\r
-#define   SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Msk         (0x00000001U  << SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Pos)\r
-\r
-#define   SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Pos     (0U)\r
-#define   SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Msk     (0x00000001U  << SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Pos)\r
-\r
-/* SDMMC_EN_INT_STATUS_NORM  =  Normal Interrupt Status Enable Register*/\r
-#define   SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Pos      (15U)\r
-#define   SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Msk      (0x00000001U  << SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Pos     (8U)\r
-#define   SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Msk     (0x00000001U  << SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Pos         (7U)\r
-#define   SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Msk         (0x00000001U  << SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Pos     (6U)\r
-#define   SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Msk     (0x00000001U  << SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Pos      (5U)\r
-#define   SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Msk      (0x00000001U  << SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Pos     (4U)\r
-#define   SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Msk     (0x00000001U  << SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Pos      (2U)\r
-#define   SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Msk      (0x00000001U  << SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Pos          (1U)\r
-#define   SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Msk          (0x00000001U  << SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Pos         (0U)\r
-#define   SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Msk         (0x00000001U  << SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Pos)\r
-\r
-/* SDMMC_EN_INT_STATUS_ERR  =  Error Interrupt Status Enable Register*/\r
-#define   SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Pos     (13U)\r
-#define   SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Msk     (0x00000001U  << SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Pos       (12U)\r
-#define   SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Msk       (0x00000001U  << SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Pos      (8U)\r
-#define   SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Msk      (0x00000001U  << SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Pos     (7U)\r
-#define   SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Msk     (0x00000001U  << SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Pos      (6U)\r
-#define   SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Msk      (0x00000001U  << SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Pos          (5U)\r
-#define   SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Msk          (0x00000001U  << SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Pos      (4U)\r
-#define   SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Msk      (0x00000001U  << SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Pos   (3U)\r
-#define   SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Msk   (0x00000001U  << SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Pos       (2U)\r
-#define   SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Msk       (0x00000001U  << SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Pos   (1U)\r
-#define   SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Msk   (0x00000001U  << SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Pos       (0U)\r
-#define   SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Msk       (0x00000001U  << SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Pos)\r
-\r
-/* SDMMC_EN_INT_SIGNAL_NORM  =  Normal Interrupt Signal Enable Register*/\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Pos      (15U)\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Msk      (0x00000001U  << SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Pos     (8U)\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Msk     (0x00000001U  << SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Pos         (7U)\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Msk         (0x00000001U  << SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Pos     (6U)\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Msk     (0x00000001U  << SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Pos      (5U)\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Msk      (0x00000001U  << SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Pos     (4U)\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Msk     (0x00000001U  << SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Pos      (2U)\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Msk      (0x00000001U  << SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Pos          (1U)\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Msk          (0x00000001U  << SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Pos         (0U)\r
-#define   SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Msk         (0x00000001U  << SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Pos)\r
-\r
-/* SDMMC_EN_INT_SIGNAL_ERR  =  Error Interrupt Signal Enable Register*/\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Pos     (13U)\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Msk     (0x00000001U  << SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Pos       (12U)\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Msk       (0x00000001U  << SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Pos      (8U)\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Msk      (0x00000001U  << SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Pos     (7U)\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Msk     (0x00000001U  << SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Pos      (6U)\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Msk      (0x00000001U  << SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Pos          (5U)\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Msk          (0x00000001U  << SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Pos      (4U)\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Msk      (0x00000001U  << SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Pos   (3U)\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Msk   (0x00000001U  << SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Pos       (2U)\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Msk       (0x00000001U  << SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Pos   (1U)\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Msk   (0x00000001U  << SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Pos)\r
-\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Pos       (0U)\r
-#define   SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Msk       (0x00000001U  << SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Pos)\r
-\r
-/* SDMMC_ACMD_ERR_STATUS  =  Auto CMD Error Status Register*/\r
-#define   SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Pos       (7U)\r
-#define   SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Msk       (0x00000001U  << SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Pos)\r
-\r
-#define   SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Pos       (4U)\r
-#define   SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Msk       (0x00000001U  << SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Pos)\r
-\r
-#define   SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Pos   (3U)\r
-#define   SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Msk   (0x00000001U  << SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Pos)\r
-\r
-#define   SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Pos       (2U)\r
-#define   SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Msk       (0x00000001U  << SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Pos)\r
-\r
-#define   SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Pos   (1U)\r
-#define   SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Msk   (0x00000001U  << SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Pos)\r
-\r
-#define   SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Pos        (0U)\r
-#define   SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Msk        (0x00000001U  << SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Pos)\r
-\r
-/* SDMMC_FORCE_EVENT_ACMD_ERR_STATUS  =  Force Event Register for Auto CMD Error Status*/\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Pos   (7U)\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Msk   (0x00000001U  << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Pos        (4U)\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Msk        (0x00000001U  << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Pos    (3U)\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Msk    (0x00000001U  << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Pos        (2U)\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Msk        (0x00000001U  << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Pos    (1U)\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Msk    (0x00000001U  << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Pos       (0U)\r
-#define   SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Msk       (0x00000001U  << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Pos)\r
-\r
-/* SDMMC_FORCE_EVENT_ERR_STATUS  =  Force Event Register for Error Interrupt Status*/\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Pos        (13U)\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Msk        (0x00000001U  << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Pos      (12U)\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Msk      (0x00000001U  << SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Pos       (8U)\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Msk       (0x00000001U  << SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Pos        (7U)\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Msk        (0x00000001U  << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Pos         (6U)\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Msk         (0x00000001U  << SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Pos     (5U)\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Msk     (0x00000001U  << SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Pos         (4U)\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Msk         (0x00000001U  << SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Pos      (3U)\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Msk      (0x00000001U  << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Pos          (2U)\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Msk          (0x00000001U  << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Pos      (1U)\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Msk      (0x00000001U  << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Pos)\r
-\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Pos          (0U)\r
-#define   SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Msk          (0x00000001U  << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Pos)\r
-\r
-/* SDMMC_DEBUG_SEL  =  Debug Selection Register*/\r
-#define   SDMMC_DEBUG_SEL_DEBUG_SEL_Pos        (0U)\r
-#define   SDMMC_DEBUG_SEL_DEBUG_SEL_Msk        (0x00000001U  << SDMMC_DEBUG_SEL_DEBUG_SEL_Pos)\r
-\r
-/* SDMMC_SPI  =  SPI Interrupt Support Register*/\r
-#define   SDMMC_SPI_SPI_INT_SUPPORT_Pos        (0U)\r
-#define   SDMMC_SPI_SPI_INT_SUPPORT_Msk        (0x000000FFU  << SDMMC_SPI_SPI_INT_SUPPORT_Pos)\r
-\r
-/* SDMMC_SLOT_INT_STATUS  =  Slot Interrupt Status Register*/\r
-#define   SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Pos    (0U)\r
-#define   SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Msk    (0x000000FFU  << SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Pos)\r
-\r
-\r
-\r
-/***   TPIU Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-// -------------------------------------  TPIU_TPIU_SSPSR  ----------------------------------------\r
-#define TPIU_TPIU_SSPSR_SWIDTH_Pos                            0                                                         /*!< TPIU TPIU_SSPSR: SWIDTH Position    */\r
-#define TPIU_TPIU_SSPSR_SWIDTH_Msk                            (0xffffffffUL << TPIU_TPIU_SSPSR_SWIDTH_Pos)              /*!< TPIU TPIU_SSPSR: SWIDTH Mask        */\r
-\r
-// -------------------------------------  TPIU_TPIU_CSPSR  ----------------------------------------\r
-#define TPIU_TPIU_CSPSR_CWIDTH_Pos                            0                                                         /*!< TPIU TPIU_CSPSR: CWIDTH Position    */\r
-#define TPIU_TPIU_CSPSR_CWIDTH_Msk                            (0xffffffffUL << TPIU_TPIU_CSPSR_CWIDTH_Pos)              /*!< TPIU TPIU_CSPSR: CWIDTH Mask        */\r
-\r
-// -------------------------------------  TPIU_TPIU_ACPR  -----------------------------------------\r
-#define TPIU_TPIU_ACPR_PRESCALER_Pos                          0                                                         /*!< TPIU TPIU_ACPR: PRESCALER Position  */\r
-#define TPIU_TPIU_ACPR_PRESCALER_Msk                          (0x00001fffUL << TPIU_TPIU_ACPR_PRESCALER_Pos)            /*!< TPIU TPIU_ACPR: PRESCALER Mask      */\r
-#define TPIU_TPIU_ACPR_Reserved_Pos                           13                                                        /*!< TPIU TPIU_ACPR: Reserved Position   */\r
-#define TPIU_TPIU_ACPR_Reserved_Msk                           (0x0007ffffUL << TPIU_TPIU_ACPR_Reserved_Pos)             /*!< TPIU TPIU_ACPR: Reserved Mask       */\r
-\r
-// -------------------------------------  TPIU_TPIU_SPPR  -----------------------------------------\r
-#define TPIU_TPIU_SPPR_TXMODE_Pos                             0                                                         /*!< TPIU TPIU_SPPR: TXMODE Position     */\r
-#define TPIU_TPIU_SPPR_TXMODE_Msk                             (0x03UL << TPIU_TPIU_SPPR_TXMODE_Pos)                     /*!< TPIU TPIU_SPPR: TXMODE Mask         */\r
-#define TPIU_TPIU_SPPR_Reserved_Pos                           2                                                         /*!< TPIU TPIU_SPPR: Reserved Position   */\r
-#define TPIU_TPIU_SPPR_Reserved_Msk                           (0x3fffffffUL << TPIU_TPIU_SPPR_Reserved_Pos)             /*!< TPIU TPIU_SPPR: Reserved Mask       */\r
-\r
-// -------------------------------------  TPIU_TPIU_FFSR  -----------------------------------------\r
-#define TPIU_TPIU_FFSR_FlInProg_Pos                           0                                                         /*!< TPIU TPIU_FFSR: FlInProg Position   */\r
-#define TPIU_TPIU_FFSR_FlInProg_Msk                           (0x01UL << TPIU_TPIU_FFSR_FlInProg_Pos)                   /*!< TPIU TPIU_FFSR: FlInProg Mask       */\r
-#define TPIU_TPIU_FFSR_FtStopped_Pos                          1                                                         /*!< TPIU TPIU_FFSR: FtStopped Position  */\r
-#define TPIU_TPIU_FFSR_FtStopped_Msk                          (0x01UL << TPIU_TPIU_FFSR_FtStopped_Pos)                  /*!< TPIU TPIU_FFSR: FtStopped Mask      */\r
-#define TPIU_TPIU_FFSR_TCPresent_Pos                          2                                                         /*!< TPIU TPIU_FFSR: TCPresent Position  */\r
-#define TPIU_TPIU_FFSR_TCPresent_Msk                          (0x01UL << TPIU_TPIU_FFSR_TCPresent_Pos)                  /*!< TPIU TPIU_FFSR: TCPresent Mask      */\r
-#define TPIU_TPIU_FFSR_FtNonStop_Pos                          3                                                         /*!< TPIU TPIU_FFSR: FtNonStop Position  */\r
-#define TPIU_TPIU_FFSR_FtNonStop_Msk                          (0x01UL << TPIU_TPIU_FFSR_FtNonStop_Pos)                  /*!< TPIU TPIU_FFSR: FtNonStop Mask      */\r
-#define TPIU_TPIU_FFSR_Reserved_Pos                           4                                                         /*!< TPIU TPIU_FFSR: Reserved Position   */\r
-#define TPIU_TPIU_FFSR_Reserved_Msk                           (0x0fffffffUL << TPIU_TPIU_FFSR_Reserved_Pos)             /*!< TPIU TPIU_FFSR: Reserved Mask       */\r
-\r
-// -------------------------------------  TPIU_TPIU_FFCR  -----------------------------------------\r
-#define TPIU_TPIU_FFCR_Reserved_Pos                           0                                                         /*!< TPIU TPIU_FFCR: Reserved Position   */\r
-#define TPIU_TPIU_FFCR_Reserved_Msk                           (0x01UL << TPIU_TPIU_FFCR_Reserved_Pos)                   /*!< TPIU TPIU_FFCR: Reserved Mask       */\r
-#define TPIU_TPIU_FFCR_EnFCont_Pos                            1                                                         /*!< TPIU TPIU_FFCR: EnFCont Position    */\r
-#define TPIU_TPIU_FFCR_EnFCont_Msk                            (0x01UL << TPIU_TPIU_FFCR_EnFCont_Pos)                    /*!< TPIU TPIU_FFCR: EnFCont Mask        */\r
-#define TPIU_TPIU_FFCR_Reserved1_Pos                          2                                                         /*!< TPIU TPIU_FFCR: Reserved1 Position  */\r
-#define TPIU_TPIU_FFCR_Reserved1_Msk                          (0x3fUL << TPIU_TPIU_FFCR_Reserved1_Pos)                  /*!< TPIU TPIU_FFCR: Reserved1 Mask      */\r
-#define TPIU_TPIU_FFCR_TrigIn_Pos                             8                                                         /*!< TPIU TPIU_FFCR: TrigIn Position     */\r
-#define TPIU_TPIU_FFCR_TrigIn_Msk                             (0x01UL << TPIU_TPIU_FFCR_TrigIn_Pos)                     /*!< TPIU TPIU_FFCR: TrigIn Mask         */\r
-#define TPIU_TPIU_FFCR_Reserved2_Pos                          9                                                         /*!< TPIU TPIU_FFCR: Reserved2 Position  */\r
-#define TPIU_TPIU_FFCR_Reserved2_Msk                          (0x007fffffUL << TPIU_TPIU_FFCR_Reserved2_Pos)            /*!< TPIU TPIU_FFCR: Reserved2 Mask      */\r
-\r
-// -------------------------------------  TPIU_TPIU_FSCR  -----------------------------------------\r
-#define TPIU_TPIU_FSCR_Reserved_Pos                           0                                                         /*!< TPIU TPIU_FSCR: Reserved Position   */\r
-#define TPIU_TPIU_FSCR_Reserved_Msk                           (0xffffffffUL << TPIU_TPIU_FSCR_Reserved_Pos)             /*!< TPIU TPIU_FSCR: Reserved Mask       */\r
-\r
-// --------------------------------------  TPIU_TRIGGER  ------------------------------------------\r
-#define TPIU_TRIGGER_TRIGGER_InputValue_Pos                   0                                                         /*!< TPIU TRIGGER: TRIGGER_InputValue Position */\r
-#define TPIU_TRIGGER_TRIGGER_InputValue_Msk                   (0x01UL << TPIU_TRIGGER_TRIGGER_InputValue_Pos)           /*!< TPIU TRIGGER: TRIGGER_InputValue Mask */\r
-#define TPIU_TRIGGER_Reserved_Pos                             1                                                         /*!< TPIU TRIGGER: Reserved Position     */\r
-#define TPIU_TRIGGER_Reserved_Msk                             (0x7fffffffUL << TPIU_TRIGGER_Reserved_Pos)               /*!< TPIU TRIGGER: Reserved Mask         */\r
-\r
-// -------------------------------------  TPIU_FIFO_Data0  ----------------------------------------\r
-#define TPIU_FIFO_Data0_ETM_Data_0_Pos                        0                                                         /*!< TPIU FIFO_Data0: ETM_Data_0 Position */\r
-#define TPIU_FIFO_Data0_ETM_Data_0_Msk                        (0x000000ffUL << TPIU_FIFO_Data0_ETM_Data_0_Pos)          /*!< TPIU FIFO_Data0: ETM_Data_0 Mask    */\r
-#define TPIU_FIFO_Data0_ETM_Data_1_Pos                        8                                                         /*!< TPIU FIFO_Data0: ETM_Data_1 Position */\r
-#define TPIU_FIFO_Data0_ETM_Data_1_Msk                        (0x000000ffUL << TPIU_FIFO_Data0_ETM_Data_1_Pos)          /*!< TPIU FIFO_Data0: ETM_Data_1 Mask    */\r
-#define TPIU_FIFO_Data0_ETM_Data_2_Pos                        16                                                        /*!< TPIU FIFO_Data0: ETM_Data_2 Position */\r
-#define TPIU_FIFO_Data0_ETM_Data_2_Msk                        (0x000000ffUL << TPIU_FIFO_Data0_ETM_Data_2_Pos)          /*!< TPIU FIFO_Data0: ETM_Data_2 Mask    */\r
-#define TPIU_FIFO_Data0_ETM_ByteCount_Pos                     24                                                        /*!< TPIU FIFO_Data0: ETM_ByteCount Position */\r
-#define TPIU_FIFO_Data0_ETM_ByteCount_Msk                     (0x03UL << TPIU_FIFO_Data0_ETM_ByteCount_Pos)             /*!< TPIU FIFO_Data0: ETM_ByteCount Mask */\r
-#define TPIU_FIFO_Data0_ETM_ATVALID_Input_Pos                 26                                                        /*!< TPIU FIFO_Data0: ETM_ATVALID_Input Position */\r
-#define TPIU_FIFO_Data0_ETM_ATVALID_Input_Msk                 (0x01UL << TPIU_FIFO_Data0_ETM_ATVALID_Input_Pos)         /*!< TPIU FIFO_Data0: ETM_ATVALID_Input Mask */\r
-#define TPIU_FIFO_Data0_ITM_ByteCount_Pos                     27                                                        /*!< TPIU FIFO_Data0: ITM_ByteCount Position */\r
-#define TPIU_FIFO_Data0_ITM_ByteCount_Msk                     (0x03UL << TPIU_FIFO_Data0_ITM_ByteCount_Pos)             /*!< TPIU FIFO_Data0: ITM_ByteCount Mask */\r
-#define TPIU_FIFO_Data0_ITM_ATVALID_Input_Pos                 29                                                        /*!< TPIU FIFO_Data0: ITM_ATVALID_Input Position */\r
-#define TPIU_FIFO_Data0_ITM_ATVALID_Input_Msk                 (0x01UL << TPIU_FIFO_Data0_ITM_ATVALID_Input_Pos)         /*!< TPIU FIFO_Data0: ITM_ATVALID_Input Mask */\r
-#define TPIU_FIFO_Data0_Reserved_Pos                          30                                                        /*!< TPIU FIFO_Data0: Reserved Position  */\r
-#define TPIU_FIFO_Data0_Reserved_Msk                          (0x03UL << TPIU_FIFO_Data0_Reserved_Pos)                  /*!< TPIU FIFO_Data0: Reserved Mask      */\r
-\r
-// -------------------------------------  TPIU_ITATBCTR2  -----------------------------------------\r
-#define TPIU_ITATBCTR2_ATREADY1_ATREADY2_Pos                  0                                                         /*!< TPIU ITATBCTR2: ATREADY1_ATREADY2 Position */\r
-#define TPIU_ITATBCTR2_ATREADY1_ATREADY2_Msk                  (0x01UL << TPIU_ITATBCTR2_ATREADY1_ATREADY2_Pos)          /*!< TPIU ITATBCTR2: ATREADY1_ATREADY2 Mask */\r
-#define TPIU_ITATBCTR2_Reserved_Pos                           1                                                         /*!< TPIU ITATBCTR2: Reserved Position   */\r
-#define TPIU_ITATBCTR2_Reserved_Msk                           (0x7fffffffUL << TPIU_ITATBCTR2_Reserved_Pos)             /*!< TPIU ITATBCTR2: Reserved Mask       */\r
-\r
-// -------------------------------------  TPIU_ITATBCTR0  -----------------------------------------\r
-#define TPIU_ITATBCTR0_ATVALID1_ATVALID2_Pos                  0                                                         /*!< TPIU ITATBCTR0: ATVALID1_ATVALID2 Position */\r
-#define TPIU_ITATBCTR0_ATVALID1_ATVALID2_Msk                  (0x01UL << TPIU_ITATBCTR0_ATVALID1_ATVALID2_Pos)          /*!< TPIU ITATBCTR0: ATVALID1_ATVALID2 Mask */\r
-#define TPIU_ITATBCTR0_Reserved_Pos                           1                                                         /*!< TPIU ITATBCTR0: Reserved Position   */\r
-#define TPIU_ITATBCTR0_Reserved_Msk                           (0x7fffffffUL << TPIU_ITATBCTR0_Reserved_Pos)             /*!< TPIU ITATBCTR0: Reserved Mask       */\r
-\r
-// -------------------------------------  TPIU_FIFO_Data1  ----------------------------------------\r
-#define TPIU_FIFO_Data1_ITM_Data_0_Pos                        0                                                         /*!< TPIU FIFO_Data1: ITM_Data_0 Position */\r
-#define TPIU_FIFO_Data1_ITM_Data_0_Msk                        (0x000000ffUL << TPIU_FIFO_Data1_ITM_Data_0_Pos)          /*!< TPIU FIFO_Data1: ITM_Data_0 Mask    */\r
-#define TPIU_FIFO_Data1_ITM_Data_1_Pos                        8                                                         /*!< TPIU FIFO_Data1: ITM_Data_1 Position */\r
-#define TPIU_FIFO_Data1_ITM_Data_1_Msk                        (0x000000ffUL << TPIU_FIFO_Data1_ITM_Data_1_Pos)          /*!< TPIU FIFO_Data1: ITM_Data_1 Mask    */\r
-#define TPIU_FIFO_Data1_ITM_Data_2_Pos                        16                                                        /*!< TPIU FIFO_Data1: ITM_Data_2 Position */\r
-#define TPIU_FIFO_Data1_ITM_Data_2_Msk                        (0x000000ffUL << TPIU_FIFO_Data1_ITM_Data_2_Pos)          /*!< TPIU FIFO_Data1: ITM_Data_2 Mask    */\r
-#define TPIU_FIFO_Data1_ETM_ByteCount_Pos                     24                                                        /*!< TPIU FIFO_Data1: ETM_ByteCount Position */\r
-#define TPIU_FIFO_Data1_ETM_ByteCount_Msk                     (0x03UL << TPIU_FIFO_Data1_ETM_ByteCount_Pos)             /*!< TPIU FIFO_Data1: ETM_ByteCount Mask */\r
-#define TPIU_FIFO_Data1_ETM_ATVALID_Input_Pos                 26                                                        /*!< TPIU FIFO_Data1: ETM_ATVALID_Input Position */\r
-#define TPIU_FIFO_Data1_ETM_ATVALID_Input_Msk                 (0x01UL << TPIU_FIFO_Data1_ETM_ATVALID_Input_Pos)         /*!< TPIU FIFO_Data1: ETM_ATVALID_Input Mask */\r
-#define TPIU_FIFO_Data1_ITM_ByteCount_Pos                     27                                                        /*!< TPIU FIFO_Data1: ITM_ByteCount Position */\r
-#define TPIU_FIFO_Data1_ITM_ByteCount_Msk                     (0x03UL << TPIU_FIFO_Data1_ITM_ByteCount_Pos)             /*!< TPIU FIFO_Data1: ITM_ByteCount Mask */\r
-#define TPIU_FIFO_Data1_ITM_ATVALID_Input_Pos                 29                                                        /*!< TPIU FIFO_Data1: ITM_ATVALID_Input Position */\r
-#define TPIU_FIFO_Data1_ITM_ATVALID_Input_Msk                 (0x01UL << TPIU_FIFO_Data1_ITM_ATVALID_Input_Pos)         /*!< TPIU FIFO_Data1: ITM_ATVALID_Input Mask */\r
-#define TPIU_FIFO_Data1_Reserved_Pos                          30                                                        /*!< TPIU FIFO_Data1: Reserved Position  */\r
-#define TPIU_FIFO_Data1_Reserved_Msk                          (0x03UL << TPIU_FIFO_Data1_Reserved_Pos)                  /*!< TPIU FIFO_Data1: Reserved Mask      */\r
-\r
-// ---------------------------------------  TPIU_ITCTRL  ------------------------------------------\r
-#define TPIU_ITCTRL_Mode_Pos                                  0                                                         /*!< TPIU ITCTRL: Mode Position          */\r
-#define TPIU_ITCTRL_Mode_Msk                                  (0x03UL << TPIU_ITCTRL_Mode_Pos)                          /*!< TPIU ITCTRL: Mode Mask              */\r
-#define TPIU_ITCTRL_Reserved_Pos                              2                                                         /*!< TPIU ITCTRL: Reserved Position      */\r
-#define TPIU_ITCTRL_Reserved_Msk                              (0x3fffffffUL << TPIU_ITCTRL_Reserved_Pos)                /*!< TPIU ITCTRL: Reserved Mask          */\r
-\r
-// --------------------------------------  TPIU_CLAIMSET  -----------------------------------------\r
-#define TPIU_CLAIMSET_ClaimTagSet_Pos                         0                                                         /*!< TPIU CLAIMSET: ClaimTagSet Position */\r
-#define TPIU_CLAIMSET_ClaimTagSet_Msk                         (0xffffffffUL << TPIU_CLAIMSET_ClaimTagSet_Pos)           /*!< TPIU CLAIMSET: ClaimTagSet Mask     */\r
-\r
-// --------------------------------------  TPIU_CLAIMCLR  -----------------------------------------\r
-#define TPIU_CLAIMCLR_ClaimTagClear_Pos                       0                                                         /*!< TPIU CLAIMCLR: ClaimTagClear Position */\r
-#define TPIU_CLAIMCLR_ClaimTagClear_Msk                       (0xffffffffUL << TPIU_CLAIMCLR_ClaimTagClear_Pos)         /*!< TPIU CLAIMCLR: ClaimTagClear Mask   */\r
-\r
-// ---------------------------------------  TPIU_DEVID  -------------------------------------------\r
-#define TPIU_DEVID_NumberOfTraceInputs_Pos                    0                                                         /*!< TPIU DEVID: NumberOfTraceInputs Position */\r
-#define TPIU_DEVID_NumberOfTraceInputs_Msk                    (0x1fUL << TPIU_DEVID_NumberOfTraceInputs_Pos)            /*!< TPIU DEVID: NumberOfTraceInputs Mask */\r
-#define TPIU_DEVID_AsynchronousTRACECLKIN_Pos                 5                                                         /*!< TPIU DEVID: AsynchronousTRACECLKIN Position */\r
-#define TPIU_DEVID_AsynchronousTRACECLKIN_Msk                 (0x01UL << TPIU_DEVID_AsynchronousTRACECLKIN_Pos)         /*!< TPIU DEVID: AsynchronousTRACECLKIN Mask */\r
-#define TPIU_DEVID_MinimumBufferSize_Pos                      6                                                         /*!< TPIU DEVID: MinimumBufferSize Position */\r
-#define TPIU_DEVID_MinimumBufferSize_Msk                      (0x07UL << TPIU_DEVID_MinimumBufferSize_Pos)              /*!< TPIU DEVID: MinimumBufferSize Mask  */\r
-#define TPIU_DEVID_ParallelTracePortMode_Pos                  9                                                         /*!< TPIU DEVID: ParallelTracePortMode Position */\r
-#define TPIU_DEVID_ParallelTracePortMode_Msk                  (0x01UL << TPIU_DEVID_ParallelTracePortMode_Pos)          /*!< TPIU DEVID: ParallelTracePortMode Mask */\r
-#define TPIU_DEVID_AsynchronousSerialWireOutput_Manchester_Pos10                                                        /*!< TPIU DEVID: AsynchronousSerialWireOutput_Manchester Position */\r
-#define TPIU_DEVID_AsynchronousSerialWireOutput_Manchester_Msk (0x01UL << TPIU_DEVID_AsynchronousSerialWireOutput_Manchester_Pos)/*!< TPIU DEVID: AsynchronousSerialWireOutput_Manchester Mask */\r
-#define TPIU_DEVID_AsynchronousSerialWireOutput_NRZ_Pos       11                                                        /*!< TPIU DEVID: AsynchronousSerialWireOutput_NRZ Position */\r
-#define TPIU_DEVID_AsynchronousSerialWireOutput_NRZ_Msk       (0x01UL << TPIU_DEVID_AsynchronousSerialWireOutput_NRZ_Pos)/*!< TPIU DEVID: AsynchronousSerialWireOutput_NRZ Mask */\r
-#define TPIU_DEVID_Reserved_Pos                               12                                                        /*!< TPIU DEVID: Reserved Position       */\r
-#define TPIU_DEVID_Reserved_Msk                               (0x000fffffUL << TPIU_DEVID_Reserved_Pos)                 /*!< TPIU DEVID: Reserved Mask           */\r
-\r
-// --------------------------------------  TPIU_DEVTYPE  ------------------------------------------\r
-#define TPIU_DEVTYPE_MajorType_Pos                            0                                                         /*!< TPIU DEVTYPE: MajorType Position    */\r
-#define TPIU_DEVTYPE_MajorType_Msk                            (0x0fUL << TPIU_DEVTYPE_MajorType_Pos)                    /*!< TPIU DEVTYPE: MajorType Mask        */\r
-#define TPIU_DEVTYPE_SubType_Pos                              4                                                         /*!< TPIU DEVTYPE: SubType Position      */\r
-#define TPIU_DEVTYPE_SubType_Msk                              (0x0fUL << TPIU_DEVTYPE_SubType_Pos)                      /*!< TPIU DEVTYPE: SubType Mask          */\r
-#define TPIU_DEVTYPE_Reserved_Pos                             8                                                         /*!< TPIU DEVTYPE: Reserved Position     */\r
-#define TPIU_DEVTYPE_Reserved_Msk                             (0x00ffffffUL << TPIU_DEVTYPE_Reserved_Pos)               /*!< TPIU DEVTYPE: Reserved Mask         */\r
-\r
-// --------------------------------------  TPIU_TPIUPID4  -----------------------------------------\r
-#define TPIU_TPIUPID4_PID4_Pos                                0                                                         /*!< TPIU TPIUPID4: PID4 Position        */\r
-#define TPIU_TPIUPID4_PID4_Msk                                (0xffffffffUL << TPIU_TPIUPID4_PID4_Pos)                  /*!< TPIU TPIUPID4: PID4 Mask            */\r
-\r
-// --------------------------------------  TPIU_TPIUPID5  -----------------------------------------\r
-#define TPIU_TPIUPID5_PID5_Pos                                0                                                         /*!< TPIU TPIUPID5: PID5 Position        */\r
-#define TPIU_TPIUPID5_PID5_Msk                                (0xffffffffUL << TPIU_TPIUPID5_PID5_Pos)                  /*!< TPIU TPIUPID5: PID5 Mask            */\r
-\r
-// --------------------------------------  TPIU_TPIUPID6  -----------------------------------------\r
-#define TPIU_TPIUPID6_PID6_Pos                                0                                                         /*!< TPIU TPIUPID6: PID6 Position        */\r
-#define TPIU_TPIUPID6_PID6_Msk                                (0xffffffffUL << TPIU_TPIUPID6_PID6_Pos)                  /*!< TPIU TPIUPID6: PID6 Mask            */\r
-\r
-// --------------------------------------  TPIU_TPIUPID7  -----------------------------------------\r
-#define TPIU_TPIUPID7_PID7_Pos                                0                                                         /*!< TPIU TPIUPID7: PID7 Position        */\r
-#define TPIU_TPIUPID7_PID7_Msk                                (0xffffffffUL << TPIU_TPIUPID7_PID7_Pos)                  /*!< TPIU TPIUPID7: PID7 Mask            */\r
-\r
-// --------------------------------------  TPIU_TPIUPID0  -----------------------------------------\r
-#define TPIU_TPIUPID0_PID0_Pos                                0                                                         /*!< TPIU TPIUPID0: PID0 Position        */\r
-#define TPIU_TPIUPID0_PID0_Msk                                (0xffffffffUL << TPIU_TPIUPID0_PID0_Pos)                  /*!< TPIU TPIUPID0: PID0 Mask            */\r
-\r
-// --------------------------------------  TPIU_TPIUPID1  -----------------------------------------\r
-#define TPIU_TPIUPID1_PID1_Pos                                0                                                         /*!< TPIU TPIUPID1: PID1 Position        */\r
-#define TPIU_TPIUPID1_PID1_Msk                                (0xffffffffUL << TPIU_TPIUPID1_PID1_Pos)                  /*!< TPIU TPIUPID1: PID1 Mask            */\r
-\r
-// --------------------------------------  TPIU_TPIUPID2  -----------------------------------------\r
-#define TPIU_TPIUPID2_PID2_Pos                                0                                                         /*!< TPIU TPIUPID2: PID2 Position        */\r
-#define TPIU_TPIUPID2_PID2_Msk                                (0xffffffffUL << TPIU_TPIUPID2_PID2_Pos)                  /*!< TPIU TPIUPID2: PID2 Mask            */\r
-\r
-// --------------------------------------  TPIU_TPIUPID3  -----------------------------------------\r
-#define TPIU_TPIUPID3_PID3_Pos                                0                                                         /*!< TPIU TPIUPID3: PID3 Position        */\r
-#define TPIU_TPIUPID3_PID3_Msk                                (0xffffffffUL << TPIU_TPIUPID3_PID3_Pos)                  /*!< TPIU TPIUPID3: PID3 Mask            */\r
-\r
-// --------------------------------------  TPIU_TPIUCID0  -----------------------------------------\r
-#define TPIU_TPIUCID0_CID0_Pos                                0                                                         /*!< TPIU TPIUCID0: CID0 Position        */\r
-#define TPIU_TPIUCID0_CID0_Msk                                (0xffffffffUL << TPIU_TPIUCID0_CID0_Pos)                  /*!< TPIU TPIUCID0: CID0 Mask            */\r
-\r
-// --------------------------------------  TPIU_TPIUCID1  -----------------------------------------\r
-#define TPIU_TPIUCID1_CID1_Pos                                0                                                         /*!< TPIU TPIUCID1: CID1 Position        */\r
-#define TPIU_TPIUCID1_CID1_Msk                                (0xffffffffUL << TPIU_TPIUCID1_CID1_Pos)                  /*!< TPIU TPIUCID1: CID1 Mask            */\r
-\r
-// --------------------------------------  TPIU_TPIUCID2  -----------------------------------------\r
-#define TPIU_TPIUCID2_CID2_Pos                                0                                                         /*!< TPIU TPIUCID2: CID2 Position        */\r
-#define TPIU_TPIUCID2_CID2_Msk                                (0xffffffffUL << TPIU_TPIUCID2_CID2_Pos)                  /*!< TPIU TPIUCID2: CID2 Mask            */\r
-\r
-// --------------------------------------  TPIU_TPIUCID3  -----------------------------------------\r
-#define TPIU_TPIUCID3_CID3_Pos                                0                                                         /*!< TPIU TPIUCID3: CID3 Position        */\r
-#define TPIU_TPIUCID3_CID3_Msk                                (0xffffffffUL << TPIU_TPIUCID3_CID3_Pos)                  /*!< TPIU TPIUCID3: CID3 Mask            */\r
-\r
-\r
-/***   USB0 Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* USB_GOTGCTL  =  Control and Status Register*/\r
-#define   USB_GOTGCTL_SesReqScs_Pos    (0U)\r
-#define   USB_GOTGCTL_SesReqScs_Msk    (0x00000001U  << USB_GOTGCTL_SesReqScs_Pos)\r
-\r
-#define   USB_GOTGCTL_SesReq_Pos       (1U)\r
-#define   USB_GOTGCTL_SesReq_Msk       (0x00000001U  << USB_GOTGCTL_SesReq_Pos)\r
-\r
-#define   USB_GOTGCTL_VbvalidOvEn_Pos          (2U)\r
-#define   USB_GOTGCTL_VbvalidOvEn_Msk          (0x00000001U  << USB_GOTGCTL_VbvalidOvEn_Pos)\r
-\r
-#define   USB_GOTGCTL_VbvalidOvVal_Pos         (3U)\r
-#define   USB_GOTGCTL_VbvalidOvVal_Msk         (0x00000001U  << USB_GOTGCTL_VbvalidOvVal_Pos)\r
-\r
-#define   USB_GOTGCTL_AvalidOvEn_Pos   (4U)\r
-#define   USB_GOTGCTL_AvalidOvEn_Msk   (0x00000001U  << USB_GOTGCTL_AvalidOvEn_Pos)\r
-\r
-#define   USB_GOTGCTL_AvalidOvVal_Pos          (5U)\r
-#define   USB_GOTGCTL_AvalidOvVal_Msk          (0x00000001U  << USB_GOTGCTL_AvalidOvVal_Pos)\r
-\r
-#define   USB_GOTGCTL_BvalidOvEn_Pos   (6U)\r
-#define   USB_GOTGCTL_BvalidOvEn_Msk   (0x00000001U  << USB_GOTGCTL_BvalidOvEn_Pos)\r
-\r
-#define   USB_GOTGCTL_BvalidOvVal_Pos          (7U)\r
-#define   USB_GOTGCTL_BvalidOvVal_Msk          (0x00000001U  << USB_GOTGCTL_BvalidOvVal_Pos)\r
-\r
-#define   USB_GOTGCTL_HstNegScs_Pos    (8U)\r
-#define   USB_GOTGCTL_HstNegScs_Msk    (0x00000001U  << USB_GOTGCTL_HstNegScs_Pos)\r
-\r
-#define   USB_GOTGCTL_HNPReq_Pos       (9U)\r
-#define   USB_GOTGCTL_HNPReq_Msk       (0x00000001U  << USB_GOTGCTL_HNPReq_Pos)\r
-\r
-#define   USB_GOTGCTL_HstSetHNPEn_Pos          (10U)\r
-#define   USB_GOTGCTL_HstSetHNPEn_Msk          (0x00000001U  << USB_GOTGCTL_HstSetHNPEn_Pos)\r
-\r
-#define   USB_GOTGCTL_DevHNPEn_Pos     (11U)\r
-#define   USB_GOTGCTL_DevHNPEn_Msk     (0x00000001U  << USB_GOTGCTL_DevHNPEn_Pos)\r
-\r
-#define   USB_GOTGCTL_ConlDSts_Pos     (16U)\r
-#define   USB_GOTGCTL_ConlDSts_Msk     (0x00000001U  << USB_GOTGCTL_ConlDSts_Pos)\r
-\r
-#define   USB_GOTGCTL_DbncTime_Pos     (17U)\r
-#define   USB_GOTGCTL_DbncTime_Msk     (0x00000001U  << USB_GOTGCTL_DbncTime_Pos)\r
-\r
-#define   USB_GOTGCTL_ASesVId_Pos      (18U)\r
-#define   USB_GOTGCTL_ASesVId_Msk      (0x00000001U  << USB_GOTGCTL_ASesVId_Pos)\r
-\r
-#define   USB_GOTGCTL_BSesVld_Pos      (19U)\r
-#define   USB_GOTGCTL_BSesVld_Msk      (0x00000001U  << USB_GOTGCTL_BSesVld_Pos)\r
-\r
-#define   USB_GOTGCTL_OTGVer_Pos       (20U)\r
-#define   USB_GOTGCTL_OTGVer_Msk       (0x00000001U  << USB_GOTGCTL_OTGVer_Pos)\r
-\r
-/* USB_GOTGINT  =  OTG Interrupt Register*/\r
-#define   USB_GOTGINT_DbnceDone_Pos    (19U)\r
-#define   USB_GOTGINT_DbnceDone_Msk    (0x00000001U  << USB_GOTGINT_DbnceDone_Pos)\r
-\r
-#define   USB_GOTGINT_ADevTOUTChg_Pos          (18U)\r
-#define   USB_GOTGINT_ADevTOUTChg_Msk          (0x00000001U  << USB_GOTGINT_ADevTOUTChg_Pos)\r
-\r
-#define   USB_GOTGINT_HstNegDet_Pos    (17U)\r
-#define   USB_GOTGINT_HstNegDet_Msk    (0x00000001U  << USB_GOTGINT_HstNegDet_Pos)\r
-\r
-#define   USB_GOTGINT_HstNegSucStsChng_Pos     (9U)\r
-#define   USB_GOTGINT_HstNegSucStsChng_Msk     (0x00000001U  << USB_GOTGINT_HstNegSucStsChng_Pos)\r
-\r
-#define   USB_GOTGINT_SesReqSucStsChng_Pos     (8U)\r
-#define   USB_GOTGINT_SesReqSucStsChng_Msk     (0x00000001U  << USB_GOTGINT_SesReqSucStsChng_Pos)\r
-\r
-#define   USB_GOTGINT_SesEndDet_Pos    (2U)\r
-#define   USB_GOTGINT_SesEndDet_Msk    (0x00000001U  << USB_GOTGINT_SesEndDet_Pos)\r
-\r
-/* USB_GAHBCFG  =  AHB Configuration Register*/\r
-#define   USB_GAHBCFG_NotiAllDmaWrit_Pos       (22U)\r
-#define   USB_GAHBCFG_NotiAllDmaWrit_Msk       (0x00000001U  << USB_GAHBCFG_NotiAllDmaWrit_Pos)\r
-\r
-#define   USB_GAHBCFG_RemMemSupp_Pos   (21U)\r
-#define   USB_GAHBCFG_RemMemSupp_Msk   (0x00000001U  << USB_GAHBCFG_RemMemSupp_Pos)\r
-\r
-#define   USB_GAHBCFG_PTxFEmpLvl_Pos   (8U)\r
-#define   USB_GAHBCFG_PTxFEmpLvl_Msk   (0x00000001U  << USB_GAHBCFG_PTxFEmpLvl_Pos)\r
-\r
-#define   USB_GAHBCFG_NPTxFEmpLvl_Pos          (7U)\r
-#define   USB_GAHBCFG_NPTxFEmpLvl_Msk          (0x00000001U  << USB_GAHBCFG_NPTxFEmpLvl_Pos)\r
-\r
-#define   USB_GAHBCFG_DMAEn_Pos        (5U)\r
-#define   USB_GAHBCFG_DMAEn_Msk        (0x00000001U  << USB_GAHBCFG_DMAEn_Pos)\r
-\r
-#define   USB_GAHBCFG_HBstLen_Pos      (1U)\r
-#define   USB_GAHBCFG_HBstLen_Msk      (0x0000000FU  << USB_GAHBCFG_HBstLen_Pos)\r
-\r
-#define   USB_GAHBCFG_GlblIntrMsk_Pos          (0U)\r
-#define   USB_GAHBCFG_GlblIntrMsk_Msk          (0x00000001U  << USB_GAHBCFG_GlblIntrMsk_Pos)\r
-\r
-/* USB_GUSBCFG  =  USB Configuration Register*/\r
-#define   USB_GUSBCFG_CTP_Pos          (31U)\r
-#define   USB_GUSBCFG_CTP_Msk          (0x00000001U  << USB_GUSBCFG_CTP_Pos)\r
-\r
-#define   USB_GUSBCFG_ForceDevMode_Pos         (30U)\r
-#define   USB_GUSBCFG_ForceDevMode_Msk         (0x00000001U  << USB_GUSBCFG_ForceDevMode_Pos)\r
-\r
-#define   USB_GUSBCFG_ForceHstMode_Pos         (29U)\r
-#define   USB_GUSBCFG_ForceHstMode_Msk         (0x00000001U  << USB_GUSBCFG_ForceHstMode_Pos)\r
-\r
-#define   USB_GUSBCFG_TxEndDela_Pos    (28U)\r
-#define   USB_GUSBCFG_TxEndDela_Msk    (0x00000001U  << USB_GUSBCFG_TxEndDela_Pos)\r
-\r
-#define   USB_GUSBCFG_OtgI2CSel_Pos    (16U)\r
-#define   USB_GUSBCFG_OtgI2CSel_Msk    (0x00000001U  << USB_GUSBCFG_OtgI2CSel_Pos)\r
-\r
-#define   USB_GUSBCFG_USBTrdTim_Pos    (10U)\r
-#define   USB_GUSBCFG_USBTrdTim_Msk    (0x0000000FU  << USB_GUSBCFG_USBTrdTim_Pos)\r
-\r
-#define   USB_GUSBCFG_HNPCap_Pos       (9U)\r
-#define   USB_GUSBCFG_HNPCap_Msk       (0x00000001U  << USB_GUSBCFG_HNPCap_Pos)\r
-\r
-#define   USB_GUSBCFG_SRPCap_Pos       (8U)\r
-#define   USB_GUSBCFG_SRPCap_Msk       (0x00000001U  << USB_GUSBCFG_SRPCap_Pos)\r
-\r
-#define   USB_GUSBCFG_PHYSel_Pos       (6U)\r
-#define   USB_GUSBCFG_PHYSel_Msk       (0x00000001U  << USB_GUSBCFG_PHYSel_Pos)\r
-\r
-#define   USB_GUSBCFG_FSIntf_Pos       (5U)\r
-#define   USB_GUSBCFG_FSIntf_Msk       (0x00000001U  << USB_GUSBCFG_FSIntf_Pos)\r
-\r
-#define   USB_GUSBCFG_PHYIf_Pos        (3U)\r
-#define   USB_GUSBCFG_PHYIf_Msk        (0x00000001U  << USB_GUSBCFG_PHYIf_Pos)\r
-\r
-#define   USB_GUSBCFG_TOutCal_Pos      (0U)\r
-#define   USB_GUSBCFG_TOutCal_Msk      (0x00000007U  << USB_GUSBCFG_TOutCal_Pos)\r
-\r
-/* USB_GRSTCTL  =  Reset Register*/\r
-#define   USB_GRSTCTL_AHBIdle_Pos      (31U)\r
-#define   USB_GRSTCTL_AHBIdle_Msk      (0x00000001U  << USB_GRSTCTL_AHBIdle_Pos)\r
-\r
-#define   USB_GRSTCTL_DMAReq_Pos       (30U)\r
-#define   USB_GRSTCTL_DMAReq_Msk       (0x00000001U  << USB_GRSTCTL_DMAReq_Pos)\r
-\r
-#define   USB_GRSTCTL_TxFNum_Pos       (6U)\r
-#define   USB_GRSTCTL_TxFNum_Msk       (0x0000001FU  << USB_GRSTCTL_TxFNum_Pos)\r
-\r
-#define   USB_GRSTCTL_TxFFlsh_Pos      (5U)\r
-#define   USB_GRSTCTL_TxFFlsh_Msk      (0x00000001U  << USB_GRSTCTL_TxFFlsh_Pos)\r
-\r
-#define   USB_GRSTCTL_RxFFlsh_Pos      (4U)\r
-#define   USB_GRSTCTL_RxFFlsh_Msk      (0x00000001U  << USB_GRSTCTL_RxFFlsh_Pos)\r
-\r
-#define   USB_GRSTCTL_FrmCntrRst_Pos   (2U)\r
-#define   USB_GRSTCTL_FrmCntrRst_Msk   (0x00000001U  << USB_GRSTCTL_FrmCntrRst_Pos)\r
-\r
-#define   USB_GRSTCTL_CSftRst_Pos      (0U)\r
-#define   USB_GRSTCTL_CSftRst_Msk      (0x00000001U  << USB_GRSTCTL_CSftRst_Pos)\r
-\r
-/* USB_GINTSTS_HOSTMODE  =  Interrupt Register [Host Mode]*/\r
-#define   USB_GINTSTS_HOSTMODE_WkUpInt_Pos     (31U)\r
-#define   USB_GINTSTS_HOSTMODE_WkUpInt_Msk     (0x00000001U  << USB_GINTSTS_HOSTMODE_WkUpInt_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_SessReqInt_Pos          (30U)\r
-#define   USB_GINTSTS_HOSTMODE_SessReqInt_Msk          (0x00000001U  << USB_GINTSTS_HOSTMODE_SessReqInt_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_DisconnInt_Pos          (29U)\r
-#define   USB_GINTSTS_HOSTMODE_DisconnInt_Msk          (0x00000001U  << USB_GINTSTS_HOSTMODE_DisconnInt_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos        (28U)\r
-#define   USB_GINTSTS_HOSTMODE_ConIDStsChng_Msk        (0x00000001U  << USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_PTxFEmp_Pos     (26U)\r
-#define   USB_GINTSTS_HOSTMODE_PTxFEmp_Msk     (0x00000001U  << USB_GINTSTS_HOSTMODE_PTxFEmp_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_HChInt_Pos      (25U)\r
-#define   USB_GINTSTS_HOSTMODE_HChInt_Msk      (0x00000001U  << USB_GINTSTS_HOSTMODE_HChInt_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_PrtInt_Pos      (24U)\r
-#define   USB_GINTSTS_HOSTMODE_PrtInt_Msk      (0x00000001U  << USB_GINTSTS_HOSTMODE_PrtInt_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_incomplP_Pos    (21U)\r
-#define   USB_GINTSTS_HOSTMODE_incomplP_Msk    (0x00000001U  << USB_GINTSTS_HOSTMODE_incomplP_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_RxFLvl_Pos      (4U)\r
-#define   USB_GINTSTS_HOSTMODE_RxFLvl_Msk      (0x00000001U  << USB_GINTSTS_HOSTMODE_RxFLvl_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_Sof_Pos         (3U)\r
-#define   USB_GINTSTS_HOSTMODE_Sof_Msk         (0x00000001U  << USB_GINTSTS_HOSTMODE_Sof_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_OTGInt_Pos      (2U)\r
-#define   USB_GINTSTS_HOSTMODE_OTGInt_Msk      (0x00000001U  << USB_GINTSTS_HOSTMODE_OTGInt_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_ModeMis_Pos     (1U)\r
-#define   USB_GINTSTS_HOSTMODE_ModeMis_Msk     (0x00000001U  << USB_GINTSTS_HOSTMODE_ModeMis_Pos)\r
-\r
-#define   USB_GINTSTS_HOSTMODE_CurMod_Pos      (0U)\r
-#define   USB_GINTSTS_HOSTMODE_CurMod_Msk      (0x00000001U  << USB_GINTSTS_HOSTMODE_CurMod_Pos)\r
-\r
-/* USB_GINTSTS_DEVICEMODE  =  Interrupt Register [Device Mode]*/\r
-#define   USB_GINTSTS_DEVICEMODE_WkUpInt_Pos   (31U)\r
-#define   USB_GINTSTS_DEVICEMODE_WkUpInt_Msk   (0x00000001U  << USB_GINTSTS_DEVICEMODE_WkUpInt_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_SessReqInt_Pos        (30U)\r
-#define   USB_GINTSTS_DEVICEMODE_SessReqInt_Msk        (0x00000001U  << USB_GINTSTS_DEVICEMODE_SessReqInt_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos      (28U)\r
-#define   USB_GINTSTS_DEVICEMODE_ConIDStsChng_Msk      (0x00000001U  << USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_ResetDet_Pos          (23U)\r
-#define   USB_GINTSTS_DEVICEMODE_ResetDet_Msk          (0x00000001U  << USB_GINTSTS_DEVICEMODE_ResetDet_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_FetSusp_Pos   (22U)\r
-#define   USB_GINTSTS_DEVICEMODE_FetSusp_Msk   (0x00000001U  << USB_GINTSTS_DEVICEMODE_FetSusp_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos      (21U)\r
-#define   USB_GINTSTS_DEVICEMODE_incomplSOOUT_Msk      (0x00000001U  << USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_incompISOIN_Pos       (20U)\r
-#define   USB_GINTSTS_DEVICEMODE_incompISOIN_Msk       (0x00000001U  << USB_GINTSTS_DEVICEMODE_incompISOIN_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_OEPInt_Pos    (19U)\r
-#define   USB_GINTSTS_DEVICEMODE_OEPInt_Msk    (0x00000001U  << USB_GINTSTS_DEVICEMODE_OEPInt_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_IEPInt_Pos    (18U)\r
-#define   USB_GINTSTS_DEVICEMODE_IEPInt_Msk    (0x00000001U  << USB_GINTSTS_DEVICEMODE_IEPInt_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_EOPF_Pos      (15U)\r
-#define   USB_GINTSTS_DEVICEMODE_EOPF_Msk      (0x00000001U  << USB_GINTSTS_DEVICEMODE_EOPF_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos        (14U)\r
-#define   USB_GINTSTS_DEVICEMODE_ISOOutDrop_Msk        (0x00000001U  << USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_EnumDone_Pos          (13U)\r
-#define   USB_GINTSTS_DEVICEMODE_EnumDone_Msk          (0x00000001U  << USB_GINTSTS_DEVICEMODE_EnumDone_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_USBRst_Pos    (12U)\r
-#define   USB_GINTSTS_DEVICEMODE_USBRst_Msk    (0x00000001U  << USB_GINTSTS_DEVICEMODE_USBRst_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_USBSusp_Pos   (11U)\r
-#define   USB_GINTSTS_DEVICEMODE_USBSusp_Msk   (0x00000001U  << USB_GINTSTS_DEVICEMODE_USBSusp_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_ErlySusp_Pos          (10U)\r
-#define   USB_GINTSTS_DEVICEMODE_ErlySusp_Msk          (0x00000001U  << USB_GINTSTS_DEVICEMODE_ErlySusp_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos        (7U)\r
-#define   USB_GINTSTS_DEVICEMODE_GOUTNakEff_Msk        (0x00000001U  << USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_GINNakEff_Pos         (6U)\r
-#define   USB_GINTSTS_DEVICEMODE_GINNakEff_Msk         (0x00000001U  << USB_GINTSTS_DEVICEMODE_GINNakEff_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_RxFLvl_Pos    (4U)\r
-#define   USB_GINTSTS_DEVICEMODE_RxFLvl_Msk    (0x00000001U  << USB_GINTSTS_DEVICEMODE_RxFLvl_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_Sof_Pos       (3U)\r
-#define   USB_GINTSTS_DEVICEMODE_Sof_Msk       (0x00000001U  << USB_GINTSTS_DEVICEMODE_Sof_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_OTGInt_Pos    (2U)\r
-#define   USB_GINTSTS_DEVICEMODE_OTGInt_Msk    (0x00000001U  << USB_GINTSTS_DEVICEMODE_OTGInt_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_ModeMis_Pos   (1U)\r
-#define   USB_GINTSTS_DEVICEMODE_ModeMis_Msk   (0x00000001U  << USB_GINTSTS_DEVICEMODE_ModeMis_Pos)\r
-\r
-#define   USB_GINTSTS_DEVICEMODE_CurMod_Pos    (0U)\r
-#define   USB_GINTSTS_DEVICEMODE_CurMod_Msk    (0x00000001U  << USB_GINTSTS_DEVICEMODE_CurMod_Pos)\r
-\r
-/* USB_GINTMSK_HOSTMODE  =  Interrupt Mask Register [Host Mode]*/\r
-#define   USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos          (31U)\r
-#define   USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk          (0x00000001U  << USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos       (30U)\r
-#define   USB_GINTMSK_HOSTMODE_SessReqIntMsk_Msk       (0x00000001U  << USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos       (29U)\r
-#define   USB_GINTMSK_HOSTMODE_DisconnIntMsk_Msk       (0x00000001U  << USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos     (28U)\r
-#define   USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Msk     (0x00000001U  << USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos)\r
-\r
-#define   USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos          (26U)\r
-#define   USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Msk          (0x00000001U  << USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos)\r
-\r
-#define   USB_GINTMSK_HOSTMODE_HChIntMsk_Pos   (25U)\r
-#define   USB_GINTMSK_HOSTMODE_HChIntMsk_Msk   (0x00000001U  << USB_GINTMSK_HOSTMODE_HChIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos   (24U)\r
-#define   USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk   (0x00000001U  << USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_HOSTMODE_incomplPMsk_Pos         (21U)\r
-#define   USB_GINTMSK_HOSTMODE_incomplPMsk_Msk         (0x00000001U  << USB_GINTMSK_HOSTMODE_incomplPMsk_Pos)\r
-\r
-#define   USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos   (4U)\r
-#define   USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk   (0x00000001U  << USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos)\r
-\r
-#define   USB_GINTMSK_HOSTMODE_SofMsk_Pos      (3U)\r
-#define   USB_GINTMSK_HOSTMODE_SofMsk_Msk      (0x00000001U  << USB_GINTMSK_HOSTMODE_SofMsk_Pos)\r
-\r
-#define   USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos   (2U)\r
-#define   USB_GINTMSK_HOSTMODE_OTGIntMsk_Msk   (0x00000001U  << USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos          (1U)\r
-#define   USB_GINTMSK_HOSTMODE_ModeMisMsk_Msk          (0x00000001U  << USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos)\r
-\r
-/* USB_GINTMSK_DEVICEMODE  =  Interrupt Mask Register [Device Mode]*/\r
-#define   USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos        (31U)\r
-#define   USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Msk        (0x00000001U  << USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos     (30U)\r
-#define   USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Msk     (0x00000001U  << USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Pos     (29U)\r
-#define   USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Msk     (0x00000001U  << USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos   (28U)\r
-#define   USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Msk   (0x00000001U  << USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_ResetDetMsk_Pos       (23U)\r
-#define   USB_GINTMSK_DEVICEMODE_ResetDetMsk_Msk       (0x00000001U  << USB_GINTMSK_DEVICEMODE_ResetDetMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_FetSuspMsk_Pos        (22U)\r
-#define   USB_GINTMSK_DEVICEMODE_FetSuspMsk_Msk        (0x00000001U  << USB_GINTMSK_DEVICEMODE_FetSuspMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos   (21U)\r
-#define   USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Msk   (0x00000001U  << USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos    (20U)\r
-#define   USB_GINTMSK_DEVICEMODE_incompISOINMsk_Msk    (0x00000001U  << USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos         (19U)\r
-#define   USB_GINTMSK_DEVICEMODE_OEPIntMsk_Msk         (0x00000001U  << USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos         (18U)\r
-#define   USB_GINTMSK_DEVICEMODE_IEPIntMsk_Msk         (0x00000001U  << USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos   (15U)\r
-#define   USB_GINTMSK_DEVICEMODE_EOPFMsk_Msk   (0x00000001U  << USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos     (14U)\r
-#define   USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Msk     (0x00000001U  << USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos       (13U)\r
-#define   USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Msk       (0x00000001U  << USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos         (12U)\r
-#define   USB_GINTMSK_DEVICEMODE_USBRstMsk_Msk         (0x00000001U  << USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos        (11U)\r
-#define   USB_GINTMSK_DEVICEMODE_USBSuspMsk_Msk        (0x00000001U  << USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos       (10U)\r
-#define   USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Msk       (0x00000001U  << USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos     (7U)\r
-#define   USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Msk     (0x00000001U  << USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos      (6U)\r
-#define   USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Msk      (0x00000001U  << USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos         (4U)\r
-#define   USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Msk         (0x00000001U  << USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_SofMsk_Pos    (3U)\r
-#define   USB_GINTMSK_DEVICEMODE_SofMsk_Msk    (0x00000001U  << USB_GINTMSK_DEVICEMODE_SofMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos         (2U)\r
-#define   USB_GINTMSK_DEVICEMODE_OTGIntMsk_Msk         (0x00000001U  << USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos)\r
-\r
-#define   USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos        (1U)\r
-#define   USB_GINTMSK_DEVICEMODE_ModeMisMsk_Msk        (0x00000001U  << USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos)\r
-\r
-/* USB_GRXSTSR_HOSTMODE  =  Receive Status Debug Read Register [Host Mode]*/\r
-#define   USB_GRXSTSR_HOSTMODE_PktSts_Pos      (17U)\r
-#define   USB_GRXSTSR_HOSTMODE_PktSts_Msk      (0x0000000FU  << USB_GRXSTSR_HOSTMODE_PktSts_Pos)\r
-\r
-#define   USB_GRXSTSR_HOSTMODE_DPID_Pos        (15U)\r
-#define   USB_GRXSTSR_HOSTMODE_DPID_Msk        (0x00000003U  << USB_GRXSTSR_HOSTMODE_DPID_Pos)\r
-\r
-#define   USB_GRXSTSR_HOSTMODE_BCnt_Pos        (4U)\r
-#define   USB_GRXSTSR_HOSTMODE_BCnt_Msk        (0x000007FFU  << USB_GRXSTSR_HOSTMODE_BCnt_Pos)\r
-\r
-#define   USB_GRXSTSR_HOSTMODE_ChNum_Pos       (0U)\r
-#define   USB_GRXSTSR_HOSTMODE_ChNum_Msk       (0x0000000FU  << USB_GRXSTSR_HOSTMODE_ChNum_Pos)\r
-\r
-/* USB_GRXSTSR_DEVICEMODE  =  Receive Status Debug Read Register [Device Mode]*/\r
-#define   USB_GRXSTSR_DEVICEMODE_FN_Pos        (21U)\r
-#define   USB_GRXSTSR_DEVICEMODE_FN_Msk        (0x0000000FU  << USB_GRXSTSR_DEVICEMODE_FN_Pos)\r
-\r
-#define   USB_GRXSTSR_DEVICEMODE_PktSts_Pos    (17U)\r
-#define   USB_GRXSTSR_DEVICEMODE_PktSts_Msk    (0x0000000FU  << USB_GRXSTSR_DEVICEMODE_PktSts_Pos)\r
-\r
-#define   USB_GRXSTSR_DEVICEMODE_DPID_Pos      (15U)\r
-#define   USB_GRXSTSR_DEVICEMODE_DPID_Msk      (0x00000003U  << USB_GRXSTSR_DEVICEMODE_DPID_Pos)\r
-\r
-#define   USB_GRXSTSR_DEVICEMODE_BCnt_Pos      (4U)\r
-#define   USB_GRXSTSR_DEVICEMODE_BCnt_Msk      (0x000007FFU  << USB_GRXSTSR_DEVICEMODE_BCnt_Pos)\r
-\r
-#define   USB_GRXSTSR_DEVICEMODE_EPNum_Pos     (0U)\r
-#define   USB_GRXSTSR_DEVICEMODE_EPNum_Msk     (0x0000000FU  << USB_GRXSTSR_DEVICEMODE_EPNum_Pos)\r
-\r
-/* USB_GRXSTSP_HOSTMODE  =  Receive Status Read and Pop Register [Host Mode]*/\r
-#define   USB_GRXSTSP_HOSTMODE_PktSts_Pos      (17U)\r
-#define   USB_GRXSTSP_HOSTMODE_PktSts_Msk      (0x0000000FU  << USB_GRXSTSP_HOSTMODE_PktSts_Pos)\r
-\r
-#define   USB_GRXSTSP_HOSTMODE_DPID_Pos        (15U)\r
-#define   USB_GRXSTSP_HOSTMODE_DPID_Msk        (0x00000003U  << USB_GRXSTSP_HOSTMODE_DPID_Pos)\r
-\r
-#define   USB_GRXSTSP_HOSTMODE_BCnt_Pos        (4U)\r
-#define   USB_GRXSTSP_HOSTMODE_BCnt_Msk        (0x000007FFU  << USB_GRXSTSP_HOSTMODE_BCnt_Pos)\r
-\r
-#define   USB_GRXSTSP_HOSTMODE_ChNum_Pos       (0U)\r
-#define   USB_GRXSTSP_HOSTMODE_ChNum_Msk       (0x0000000FU  << USB_GRXSTSP_HOSTMODE_ChNum_Pos)\r
-\r
-/* USB_GRXSTSP_DEVICEMODE  =  Receive Status Read and Pop Register [Device Mode]*/\r
-#define   USB_GRXSTSP_DEVICEMODE_FN_Pos        (21U)\r
-#define   USB_GRXSTSP_DEVICEMODE_FN_Msk        (0x0000000FU  << USB_GRXSTSP_DEVICEMODE_FN_Pos)\r
-\r
-#define   USB_GRXSTSP_DEVICEMODE_PktSts_Pos    (17U)\r
-#define   USB_GRXSTSP_DEVICEMODE_PktSts_Msk    (0x0000000FU  << USB_GRXSTSP_DEVICEMODE_PktSts_Pos)\r
-\r
-#define   USB_GRXSTSP_DEVICEMODE_DPID_Pos      (15U)\r
-#define   USB_GRXSTSP_DEVICEMODE_DPID_Msk      (0x00000003U  << USB_GRXSTSP_DEVICEMODE_DPID_Pos)\r
-\r
-#define   USB_GRXSTSP_DEVICEMODE_BCnt_Pos      (4U)\r
-#define   USB_GRXSTSP_DEVICEMODE_BCnt_Msk      (0x000007FFU  << USB_GRXSTSP_DEVICEMODE_BCnt_Pos)\r
-\r
-#define   USB_GRXSTSP_DEVICEMODE_EPNum_Pos     (0U)\r
-#define   USB_GRXSTSP_DEVICEMODE_EPNum_Msk     (0x0000000FU  << USB_GRXSTSP_DEVICEMODE_EPNum_Pos)\r
-\r
-/* USB_GRXFSIZ  =  Receive FIFO Size Register*/\r
-#define   USB_GRXFSIZ_RxFDep_Pos       (0U)\r
-#define   USB_GRXFSIZ_RxFDep_Msk       (0x0000FFFFU  << USB_GRXFSIZ_RxFDep_Pos)\r
-\r
-/* USB_GNPTXFSIZ_HOSTMODE  =  Non-Periodic Transmit FIFO Size Register [Host Mode]*/\r
-#define   USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos          (16U)\r
-#define   USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Msk          (0x0000FFFFU  << USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos)\r
-\r
-#define   USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos       (0U)\r
-#define   USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Msk       (0x0000FFFFU  << USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos)\r
-\r
-/* USB_GNPTXFSIZ_DEVICEMODE  =  Non-Periodic Transmit FIFO Size Register [Device Mode]*/\r
-#define   USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos     (16U)\r
-#define   USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Msk     (0x0000FFFFU  << USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos)\r
-\r
-/* USB_GNPTXSTS  =  Non-Periodic Transmit FIFO/Queue Status Register*/\r
-#define   USB_GNPTXSTS_NPTxQTop_Pos    (24U)\r
-#define   USB_GNPTXSTS_NPTxQTop_Msk    (0x0000007FU  << USB_GNPTXSTS_NPTxQTop_Pos)\r
-\r
-#define   USB_GNPTXSTS_NPTxQSpcAvail_Pos       (16U)\r
-#define   USB_GNPTXSTS_NPTxQSpcAvail_Msk       (0x000000FFU  << USB_GNPTXSTS_NPTxQSpcAvail_Pos)\r
-\r
-#define   USB_GNPTXSTS_NPTxFSpcAvail_Pos       (0U)\r
-#define   USB_GNPTXSTS_NPTxFSpcAvail_Msk       (0x0000FFFFU  << USB_GNPTXSTS_NPTxFSpcAvail_Pos)\r
-\r
-/* USB_GUID  =  User ID Register*/\r
-#define   USB_GUID_UserID_Pos          (0U)\r
-#define   USB_GUID_UserID_Msk          (0xFFFFFFFFU  << USB_GUID_UserID_Pos)\r
-\r
-/* USB_GDFIFOCFG  =  Global DFIFO Software Config Register*/\r
-#define   USB_GDFIFOCFG_EPInfoBaseAddr_Pos     (16U)\r
-#define   USB_GDFIFOCFG_EPInfoBaseAddr_Msk     (0x0000FFFFU  << USB_GDFIFOCFG_EPInfoBaseAddr_Pos)\r
-\r
-#define   USB_GDFIFOCFG_GDFIFOCfg_Pos          (0U)\r
-#define   USB_GDFIFOCFG_GDFIFOCfg_Msk          (0x0000FFFFU  << USB_GDFIFOCFG_GDFIFOCfg_Pos)\r
-\r
-/* USB_HPTXFSIZ  =  Host Periodic Transmit FIFO Size Register*/\r
-#define   USB_HPTXFSIZ_PTxFSize_Pos    (16U)\r
-#define   USB_HPTXFSIZ_PTxFSize_Msk    (0x0000FFFFU  << USB_HPTXFSIZ_PTxFSize_Pos)\r
-\r
-#define   USB_HPTXFSIZ_PTxFStAddr_Pos          (0U)\r
-#define   USB_HPTXFSIZ_PTxFStAddr_Msk          (0x0000FFFFU  << USB_HPTXFSIZ_PTxFStAddr_Pos)\r
-\r
-/* USB_DIEPTXF1  =  Device IN Endpoint Transmit FIFO Size Register*/\r
-#define   USB_DIEPTXF1_INEPnTxFDep_Pos         (16U)\r
-#define   USB_DIEPTXF1_INEPnTxFDep_Msk         (0x0000FFFFU  << USB_DIEPTXF1_INEPnTxFDep_Pos)\r
-\r
-#define   USB_DIEPTXF1_INEPnTxFStAddr_Pos      (0U)\r
-#define   USB_DIEPTXF1_INEPnTxFStAddr_Msk      (0x0000FFFFU  << USB_DIEPTXF1_INEPnTxFStAddr_Pos)\r
-\r
-/* USB_DIEPTXF2  =  Device IN Endpoint Transmit FIFO Size Register*/\r
-#define   USB_DIEPTXF2_INEPnTxFDep_Pos         (16U)\r
-#define   USB_DIEPTXF2_INEPnTxFDep_Msk         (0x0000FFFFU  << USB_DIEPTXF2_INEPnTxFDep_Pos)\r
-\r
-#define   USB_DIEPTXF2_INEPnTxFStAddr_Pos      (0U)\r
-#define   USB_DIEPTXF2_INEPnTxFStAddr_Msk      (0x0000FFFFU  << USB_DIEPTXF2_INEPnTxFStAddr_Pos)\r
-\r
-/* USB_DIEPTXF3  =  Device IN Endpoint Transmit FIFO Size Register*/\r
-#define   USB_DIEPTXF3_INEPnTxFDep_Pos         (16U)\r
-#define   USB_DIEPTXF3_INEPnTxFDep_Msk         (0x0000FFFFU  << USB_DIEPTXF3_INEPnTxFDep_Pos)\r
-\r
-#define   USB_DIEPTXF3_INEPnTxFStAddr_Pos      (0U)\r
-#define   USB_DIEPTXF3_INEPnTxFStAddr_Msk      (0x0000FFFFU  << USB_DIEPTXF3_INEPnTxFStAddr_Pos)\r
-\r
-/* USB_DIEPTXF4  =  Device IN Endpoint Transmit FIFO Size Register*/\r
-#define   USB_DIEPTXF4_INEPnTxFDep_Pos         (16U)\r
-#define   USB_DIEPTXF4_INEPnTxFDep_Msk         (0x0000FFFFU  << USB_DIEPTXF4_INEPnTxFDep_Pos)\r
-\r
-#define   USB_DIEPTXF4_INEPnTxFStAddr_Pos      (0U)\r
-#define   USB_DIEPTXF4_INEPnTxFStAddr_Msk      (0x0000FFFFU  << USB_DIEPTXF4_INEPnTxFStAddr_Pos)\r
-\r
-/* USB_DIEPTXF5  =  Device IN Endpoint Transmit FIFO Size Register*/\r
-#define   USB_DIEPTXF5_INEPnTxFDep_Pos         (16U)\r
-#define   USB_DIEPTXF5_INEPnTxFDep_Msk         (0x0000FFFFU  << USB_DIEPTXF5_INEPnTxFDep_Pos)\r
-\r
-#define   USB_DIEPTXF5_INEPnTxFStAddr_Pos      (0U)\r
-#define   USB_DIEPTXF5_INEPnTxFStAddr_Msk      (0x0000FFFFU  << USB_DIEPTXF5_INEPnTxFStAddr_Pos)\r
-\r
-/* USB_DIEPTXF6  =  Device IN Endpoint Transmit FIFO Size Register*/\r
-#define   USB_DIEPTXF6_INEPnTxFDep_Pos         (16U)\r
-#define   USB_DIEPTXF6_INEPnTxFDep_Msk         (0x0000FFFFU  << USB_DIEPTXF6_INEPnTxFDep_Pos)\r
-\r
-#define   USB_DIEPTXF6_INEPnTxFStAddr_Pos      (0U)\r
-#define   USB_DIEPTXF6_INEPnTxFStAddr_Msk      (0x0000FFFFU  << USB_DIEPTXF6_INEPnTxFStAddr_Pos)\r
-\r
-/* USB_CH_HCFG  =  Host Configuration Register*/\r
-#define   USB_CH_HCFG_PerSchedEna_Pos          (26U)\r
-#define   USB_CH_HCFG_PerSchedEna_Msk          (0x00000001U  << USB_CH_HCFG_PerSchedEna_Pos)\r
-\r
-#define   USB_CH_HCFG_FrListEn_Pos     (24U)\r
-#define   USB_CH_HCFG_FrListEn_Msk     (0x00000003U  << USB_CH_HCFG_FrListEn_Pos)\r
-\r
-#define   USB_CH_HCFG_DescDMA_Pos      (23U)\r
-#define   USB_CH_HCFG_DescDMA_Msk      (0x00000001U  << USB_CH_HCFG_DescDMA_Pos)\r
-\r
-#define   USB_CH_HCFG_ResValid_Pos     (8U)\r
-#define   USB_CH_HCFG_ResValid_Msk     (0x000000FFU  << USB_CH_HCFG_ResValid_Pos)\r
-\r
-#define   USB_CH_HCFG_Ena32KHzS_Pos    (7U)\r
-#define   USB_CH_HCFG_Ena32KHzS_Msk    (0x00000001U  << USB_CH_HCFG_Ena32KHzS_Pos)\r
-\r
-#define   USB_CH_HCFG_FSLSSupp_Pos     (2U)\r
-#define   USB_CH_HCFG_FSLSSupp_Msk     (0x00000001U  << USB_CH_HCFG_FSLSSupp_Pos)\r
-\r
-#define   USB_CH_HCFG_FSLSPclkSel_Pos          (0U)\r
-#define   USB_CH_HCFG_FSLSPclkSel_Msk          (0x00000003U  << USB_CH_HCFG_FSLSPclkSel_Pos)\r
-\r
-/* USB_HFIR  =  Host Frame Interval Register*/\r
-#define   USB_HFIR_FrInt_Pos   (0U)\r
-#define   USB_HFIR_FrInt_Msk   (0x0000FFFFU  << USB_HFIR_FrInt_Pos)\r
-\r
-/* USB_HFNUM  =  Host Frame Number/Frame Time Remaining Register*/\r
-#define   USB_HFNUM_FrRem_Pos          (16U)\r
-#define   USB_HFNUM_FrRem_Msk          (0x0000FFFFU  << USB_HFNUM_FrRem_Pos)\r
-\r
-#define   USB_HFNUM_FrNum_Pos          (0U)\r
-#define   USB_HFNUM_FrNum_Msk          (0x0000FFFFU  << USB_HFNUM_FrNum_Pos)\r
-\r
-/* USB_HPTXSTS  =  Host Periodic Transmit FIFO/ Queue Status Register*/\r
-#define   USB_HPTXSTS_PTxQTop_Pos      (24U)\r
-#define   USB_HPTXSTS_PTxQTop_Msk      (0x000000FFU  << USB_HPTXSTS_PTxQTop_Pos)\r
-\r
-#define   USB_HPTXSTS_PTxQSpcAvail_Pos         (16U)\r
-#define   USB_HPTXSTS_PTxQSpcAvail_Msk         (0x000000FFU  << USB_HPTXSTS_PTxQSpcAvail_Pos)\r
-\r
-#define   USB_HPTXSTS_PTxFSpcAvail_Pos         (0U)\r
-#define   USB_HPTXSTS_PTxFSpcAvail_Msk         (0x0000FFFFU  << USB_HPTXSTS_PTxFSpcAvail_Pos)\r
-\r
-/* USB_HAINT  =  Host All Channels Interrupt Register*/\r
-#define   USB_HAINT_HAINT_Pos          (0U)\r
-#define   USB_HAINT_HAINT_Msk          (0x00003FFFU  << USB_HAINT_HAINT_Pos)\r
-\r
-/* USB_HAINTMSK  =  Host All Channels Interrupt Mask Register*/\r
-#define   USB_HAINTMSK_HAINTMsk_Pos    (0U)\r
-#define   USB_HAINTMSK_HAINTMsk_Msk    (0x00003FFFU  << USB_HAINTMSK_HAINTMsk_Pos)\r
-\r
-/* USB_HFLBADDR  =  Host Frame List Base Address Register*/\r
-#define   USB_HFLBADDR_Starting_Address_Pos    (0U)\r
-#define   USB_HFLBADDR_Starting_Address_Msk    (0xFFFFFFFFU  << USB_HFLBADDR_Starting_Address_Pos)\r
-\r
-/* USB_HPRT  =  Host Port Control and Status Register*/\r
-#define   USB_HPRT_PrtSpd_Pos          (17U)\r
-#define   USB_HPRT_PrtSpd_Msk          (0x00000003U  << USB_HPRT_PrtSpd_Pos)\r
-\r
-#define   USB_HPRT_PrtPwr_Pos          (12U)\r
-#define   USB_HPRT_PrtPwr_Msk          (0x00000001U  << USB_HPRT_PrtPwr_Pos)\r
-\r
-#define   USB_HPRT_PrtLnSts_Pos        (10U)\r
-#define   USB_HPRT_PrtLnSts_Msk        (0x00000003U  << USB_HPRT_PrtLnSts_Pos)\r
-\r
-#define   USB_HPRT_PrtRst_Pos          (8U)\r
-#define   USB_HPRT_PrtRst_Msk          (0x00000001U  << USB_HPRT_PrtRst_Pos)\r
-\r
-#define   USB_HPRT_PrtSusp_Pos         (7U)\r
-#define   USB_HPRT_PrtSusp_Msk         (0x00000001U  << USB_HPRT_PrtSusp_Pos)\r
-\r
-#define   USB_HPRT_PrtRes_Pos          (6U)\r
-#define   USB_HPRT_PrtRes_Msk          (0x00000001U  << USB_HPRT_PrtRes_Pos)\r
-\r
-#define   USB_HPRT_PrtOvrCurrChng_Pos          (5U)\r
-#define   USB_HPRT_PrtOvrCurrChng_Msk          (0x00000001U  << USB_HPRT_PrtOvrCurrChng_Pos)\r
-\r
-#define   USB_HPRT_PrtOvrCurrAct_Pos   (4U)\r
-#define   USB_HPRT_PrtOvrCurrAct_Msk   (0x00000001U  << USB_HPRT_PrtOvrCurrAct_Pos)\r
-\r
-#define   USB_HPRT_PrtEnChng_Pos       (3U)\r
-#define   USB_HPRT_PrtEnChng_Msk       (0x00000001U  << USB_HPRT_PrtEnChng_Pos)\r
-\r
-#define   USB_HPRT_PrtEna_Pos          (2U)\r
-#define   USB_HPRT_PrtEna_Msk          (0x00000001U  << USB_HPRT_PrtEna_Pos)\r
-\r
-#define   USB_HPRT_PrtConnDet_Pos      (1U)\r
-#define   USB_HPRT_PrtConnDet_Msk      (0x00000001U  << USB_HPRT_PrtConnDet_Pos)\r
-\r
-#define   USB_HPRT_PrtConnSts_Pos      (0U)\r
-#define   USB_HPRT_PrtConnSts_Msk      (0x00000001U  << USB_HPRT_PrtConnSts_Pos)\r
-\r
-/* USB_DCFG  =  Device Configuration Register*/\r
-#define   USB_DCFG_ResValid_Pos        (26U)\r
-#define   USB_DCFG_ResValid_Msk        (0x0000003FU  << USB_DCFG_ResValid_Pos)\r
-\r
-#define   USB_DCFG_PerSchIntvl_Pos     (24U)\r
-#define   USB_DCFG_PerSchIntvl_Msk     (0x00000003U  << USB_DCFG_PerSchIntvl_Pos)\r
-\r
-#define   USB_DCFG_DescDMA_Pos         (23U)\r
-#define   USB_DCFG_DescDMA_Msk         (0x00000001U  << USB_DCFG_DescDMA_Pos)\r
-\r
-#define   USB_DCFG_EPMisCnt_Pos        (18U)\r
-#define   USB_DCFG_EPMisCnt_Msk        (0x0000001FU  << USB_DCFG_EPMisCnt_Pos)\r
-\r
-#define   USB_DCFG_PerFrInt_Pos        (11U)\r
-#define   USB_DCFG_PerFrInt_Msk        (0x00000003U  << USB_DCFG_PerFrInt_Pos)\r
-\r
-#define   USB_DCFG_DevAddr_Pos         (4U)\r
-#define   USB_DCFG_DevAddr_Msk         (0x0000007FU  << USB_DCFG_DevAddr_Pos)\r
-\r
-#define   USB_DCFG_Ena32KHzS_Pos       (3U)\r
-#define   USB_DCFG_Ena32KHzS_Msk       (0x00000001U  << USB_DCFG_Ena32KHzS_Pos)\r
-\r
-#define   USB_DCFG_NZStsOUTHShk_Pos    (2U)\r
-#define   USB_DCFG_NZStsOUTHShk_Msk    (0x00000001U  << USB_DCFG_NZStsOUTHShk_Pos)\r
-\r
-#define   USB_DCFG_DevSpd_Pos          (0U)\r
-#define   USB_DCFG_DevSpd_Msk          (0x00000003U  << USB_DCFG_DevSpd_Pos)\r
-\r
-/* USB_DCTL  =  Device Control Register*/\r
-#define   USB_DCTL_NakOnBble_Pos       (16U)\r
-#define   USB_DCTL_NakOnBble_Msk       (0x00000001U  << USB_DCTL_NakOnBble_Pos)\r
-\r
-#define   USB_DCTL_IgnrFrmNum_Pos      (15U)\r
-#define   USB_DCTL_IgnrFrmNum_Msk      (0x00000001U  << USB_DCTL_IgnrFrmNum_Pos)\r
-\r
-#define   USB_DCTL_GMC_Pos     (13U)\r
-#define   USB_DCTL_GMC_Msk     (0x00000003U  << USB_DCTL_GMC_Pos)\r
-\r
-#define   USB_DCTL_PWROnPrgDone_Pos    (11U)\r
-#define   USB_DCTL_PWROnPrgDone_Msk    (0x00000001U  << USB_DCTL_PWROnPrgDone_Pos)\r
-\r
-#define   USB_DCTL_CGOUTNak_Pos        (10U)\r
-#define   USB_DCTL_CGOUTNak_Msk        (0x00000001U  << USB_DCTL_CGOUTNak_Pos)\r
-\r
-#define   USB_DCTL_SGOUTNak_Pos        (9U)\r
-#define   USB_DCTL_SGOUTNak_Msk        (0x00000001U  << USB_DCTL_SGOUTNak_Pos)\r
-\r
-#define   USB_DCTL_CGNPInNak_Pos       (8U)\r
-#define   USB_DCTL_CGNPInNak_Msk       (0x00000001U  << USB_DCTL_CGNPInNak_Pos)\r
-\r
-#define   USB_DCTL_SGNPInNak_Pos       (7U)\r
-#define   USB_DCTL_SGNPInNak_Msk       (0x00000001U  << USB_DCTL_SGNPInNak_Pos)\r
-\r
-#define   USB_DCTL_GOUTNakSts_Pos      (3U)\r
-#define   USB_DCTL_GOUTNakSts_Msk      (0x00000001U  << USB_DCTL_GOUTNakSts_Pos)\r
-\r
-#define   USB_DCTL_GNPINNakSts_Pos     (2U)\r
-#define   USB_DCTL_GNPINNakSts_Msk     (0x00000001U  << USB_DCTL_GNPINNakSts_Pos)\r
-\r
-#define   USB_DCTL_SftDiscon_Pos       (1U)\r
-#define   USB_DCTL_SftDiscon_Msk       (0x00000001U  << USB_DCTL_SftDiscon_Pos)\r
-\r
-#define   USB_DCTL_RmtWkUpSig_Pos      (0U)\r
-#define   USB_DCTL_RmtWkUpSig_Msk      (0x00000001U  << USB_DCTL_RmtWkUpSig_Pos)\r
-\r
-/* USB_DSTS  =  Device Status Register*/\r
-#define   USB_DSTS_SOFFN_Pos   (8U)\r
-#define   USB_DSTS_SOFFN_Msk   (0x00003FFFU  << USB_DSTS_SOFFN_Pos)\r
-\r
-#define   USB_DSTS_ErrticErr_Pos       (3U)\r
-#define   USB_DSTS_ErrticErr_Msk       (0x00000001U  << USB_DSTS_ErrticErr_Pos)\r
-\r
-#define   USB_DSTS_EnumSpd_Pos         (1U)\r
-#define   USB_DSTS_EnumSpd_Msk         (0x00000003U  << USB_DSTS_EnumSpd_Pos)\r
-\r
-#define   USB_DSTS_SuspSts_Pos         (0U)\r
-#define   USB_DSTS_SuspSts_Msk         (0x00000001U  << USB_DSTS_SuspSts_Pos)\r
-\r
-/* USB_DIEPMSK  =  Device IN Endpoint Common Interrupt Mask Register*/\r
-#define   USB_DIEPMSK_NAKMsk_Pos       (13U)\r
-#define   USB_DIEPMSK_NAKMsk_Msk       (0x00000001U  << USB_DIEPMSK_NAKMsk_Pos)\r
-\r
-#define   USB_DIEPMSK_BNAInIntrMsk_Pos         (9U)\r
-#define   USB_DIEPMSK_BNAInIntrMsk_Msk         (0x00000001U  << USB_DIEPMSK_BNAInIntrMsk_Pos)\r
-\r
-#define   USB_DIEPMSK_TxfifoUndrnMsk_Pos       (8U)\r
-#define   USB_DIEPMSK_TxfifoUndrnMsk_Msk       (0x00000001U  << USB_DIEPMSK_TxfifoUndrnMsk_Pos)\r
-\r
-#define   USB_DIEPMSK_INEPNakEffMsk_Pos        (6U)\r
-#define   USB_DIEPMSK_INEPNakEffMsk_Msk        (0x00000001U  << USB_DIEPMSK_INEPNakEffMsk_Pos)\r
-\r
-#define   USB_DIEPMSK_INTknEPMisMsk_Pos        (5U)\r
-#define   USB_DIEPMSK_INTknEPMisMsk_Msk        (0x00000001U  << USB_DIEPMSK_INTknEPMisMsk_Pos)\r
-\r
-#define   USB_DIEPMSK_INTknTXFEmpMsk_Pos       (4U)\r
-#define   USB_DIEPMSK_INTknTXFEmpMsk_Msk       (0x00000001U  << USB_DIEPMSK_INTknTXFEmpMsk_Pos)\r
-\r
-#define   USB_DIEPMSK_TimeOUTMsk_Pos   (3U)\r
-#define   USB_DIEPMSK_TimeOUTMsk_Msk   (0x00000001U  << USB_DIEPMSK_TimeOUTMsk_Pos)\r
-\r
-#define   USB_DIEPMSK_AHBErrMsk_Pos    (2U)\r
-#define   USB_DIEPMSK_AHBErrMsk_Msk    (0x00000001U  << USB_DIEPMSK_AHBErrMsk_Pos)\r
-\r
-#define   USB_DIEPMSK_EPDisbldMsk_Pos          (1U)\r
-#define   USB_DIEPMSK_EPDisbldMsk_Msk          (0x00000001U  << USB_DIEPMSK_EPDisbldMsk_Pos)\r
-\r
-#define   USB_DIEPMSK_XferComplMsk_Pos         (0U)\r
-#define   USB_DIEPMSK_XferComplMsk_Msk         (0x00000001U  << USB_DIEPMSK_XferComplMsk_Pos)\r
-\r
-/* USB_DOEPMSK  =  Device OUT Endpoint Common Interrupt Mask Register*/\r
-#define   USB_DOEPMSK_NYETMsk_Pos      (14U)\r
-#define   USB_DOEPMSK_NYETMsk_Msk      (0x00000001U  << USB_DOEPMSK_NYETMsk_Pos)\r
-\r
-#define   USB_DOEPMSK_NAKMsk_Pos       (13U)\r
-#define   USB_DOEPMSK_NAKMsk_Msk       (0x00000001U  << USB_DOEPMSK_NAKMsk_Pos)\r
-\r
-#define   USB_DOEPMSK_BbleErrMsk_Pos   (12U)\r
-#define   USB_DOEPMSK_BbleErrMsk_Msk   (0x00000001U  << USB_DOEPMSK_BbleErrMsk_Pos)\r
-\r
-#define   USB_DOEPMSK_BnaOutIntrMsk_Pos        (9U)\r
-#define   USB_DOEPMSK_BnaOutIntrMsk_Msk        (0x00000001U  << USB_DOEPMSK_BnaOutIntrMsk_Pos)\r
-\r
-#define   USB_DOEPMSK_OutPktErrMsk_Pos         (8U)\r
-#define   USB_DOEPMSK_OutPktErrMsk_Msk         (0x00000001U  << USB_DOEPMSK_OutPktErrMsk_Pos)\r
-\r
-#define   USB_DOEPMSK_Back2BackSETup_Pos       (6U)\r
-#define   USB_DOEPMSK_Back2BackSETup_Msk       (0x00000001U  << USB_DOEPMSK_Back2BackSETup_Pos)\r
-\r
-#define   USB_DOEPMSK_OUTTknEPdisMsk_Pos       (4U)\r
-#define   USB_DOEPMSK_OUTTknEPdisMsk_Msk       (0x00000001U  << USB_DOEPMSK_OUTTknEPdisMsk_Pos)\r
-\r
-#define   USB_DOEPMSK_SetUPMsk_Pos     (3U)\r
-#define   USB_DOEPMSK_SetUPMsk_Msk     (0x00000001U  << USB_DOEPMSK_SetUPMsk_Pos)\r
-\r
-#define   USB_DOEPMSK_AHBErrMsk_Pos    (2U)\r
-#define   USB_DOEPMSK_AHBErrMsk_Msk    (0x00000001U  << USB_DOEPMSK_AHBErrMsk_Pos)\r
-\r
-#define   USB_DOEPMSK_EPDisbldMsk_Pos          (1U)\r
-#define   USB_DOEPMSK_EPDisbldMsk_Msk          (0x00000001U  << USB_DOEPMSK_EPDisbldMsk_Pos)\r
-\r
-#define   USB_DOEPMSK_XferComplMsk_Pos         (0U)\r
-#define   USB_DOEPMSK_XferComplMsk_Msk         (0x00000001U  << USB_DOEPMSK_XferComplMsk_Pos)\r
-\r
-/* USB_DAINT  =  Device All Endpoints Interrupt Register*/\r
-#define   USB_DAINT_OutEPInt_Pos       (16U)\r
-#define   USB_DAINT_OutEPInt_Msk       (0x0000FFFFU  << USB_DAINT_OutEPInt_Pos)\r
-\r
-#define   USB_DAINT_InEpInt_Pos        (0U)\r
-#define   USB_DAINT_InEpInt_Msk        (0x0000FFFFU  << USB_DAINT_InEpInt_Pos)\r
-\r
-/* USB_DAINTMSK  =  Device All Endpoints Interrupt Mask Register*/\r
-#define   USB_DAINTMSK_OutEpMsk_Pos    (16U)\r
-#define   USB_DAINTMSK_OutEpMsk_Msk    (0x0000FFFFU  << USB_DAINTMSK_OutEpMsk_Pos)\r
-\r
-#define   USB_DAINTMSK_InEpMsk_Pos     (0U)\r
-#define   USB_DAINTMSK_InEpMsk_Msk     (0x0000FFFFU  << USB_DAINTMSK_InEpMsk_Pos)\r
-\r
-/* USB_DVBUSDIS  =  Device VBUS Discharge Time Register*/\r
-#define   USB_DVBUSDIS_DVBUSDis_Pos    (0U)\r
-#define   USB_DVBUSDIS_DVBUSDis_Msk    (0x0000FFFFU  << USB_DVBUSDIS_DVBUSDis_Pos)\r
-\r
-/* USB_DVBUSPULSE  =  Device VBUS Pulsing Time Register*/\r
-#define   USB_DVBUSPULSE_DVBUSPulse_Pos        (0U)\r
-#define   USB_DVBUSPULSE_DVBUSPulse_Msk        (0x00000FFFU  << USB_DVBUSPULSE_DVBUSPulse_Pos)\r
-\r
-/* USB_DIEPEMPMSK  =  Device IN Endpoint FIFO Empty Interrupt Mask Register*/\r
-#define   USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos     (0U)\r
-#define   USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk     (0x0000FFFFU  << USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos)\r
-\r
-/* USB_PCGCCTL  =  Power and Clock Gating Control Register*/\r
-#define   USB_PCGCCTL_ResetAfterSusp_Pos       (8U)\r
-#define   USB_PCGCCTL_ResetAfterSusp_Msk       (0x00000001U  << USB_PCGCCTL_ResetAfterSusp_Pos)\r
-\r
-#define   USB_PCGCCTL_L1_Suspended_Pos         (7U)\r
-#define   USB_PCGCCTL_L1_Suspended_Msk         (0x00000001U  << USB_PCGCCTL_L1_Suspended_Pos)\r
-\r
-#define   USB_PCGCCTL_PhySleep_Pos     (6U)\r
-#define   USB_PCGCCTL_PhySleep_Msk     (0x00000001U  << USB_PCGCCTL_PhySleep_Pos)\r
-\r
-#define   USB_PCGCCTL_Enbl_L1Gating_Pos        (5U)\r
-#define   USB_PCGCCTL_Enbl_L1Gating_Msk        (0x00000001U  << USB_PCGCCTL_Enbl_L1Gating_Pos)\r
-\r
-#define   USB_PCGCCTL_RstPdwnModule_Pos        (3U)\r
-#define   USB_PCGCCTL_RstPdwnModule_Msk        (0x00000001U  << USB_PCGCCTL_RstPdwnModule_Pos)\r
-\r
-#define   USB_PCGCCTL_PwrClmp_Pos      (2U)\r
-#define   USB_PCGCCTL_PwrClmp_Msk      (0x00000001U  << USB_PCGCCTL_PwrClmp_Pos)\r
-\r
-#define   USB_PCGCCTL_GateHclk_Pos     (1U)\r
-#define   USB_PCGCCTL_GateHclk_Msk     (0x00000001U  << USB_PCGCCTL_GateHclk_Pos)\r
-\r
-#define   USB_PCGCCTL_StopPclk_Pos     (0U)\r
-#define   USB_PCGCCTL_StopPclk_Msk     (0x00000001U  << USB_PCGCCTL_StopPclk_Pos)\r
-\r
-/* USB_EP_DIEPCTL0  =  Device Control IN Endpoint x Control Register*/\r
-#define   USB_EP_DIEPCTL0_EPEna_Pos    (31U)\r
-#define   USB_EP_DIEPCTL0_EPEna_Msk    (0x00000001U  << USB_EP_DIEPCTL0_EPEna_Pos)\r
-\r
-#define   USB_EP_DIEPCTL0_EPDis_Pos    (30U)\r
-#define   USB_EP_DIEPCTL0_EPDis_Msk    (0x00000001U  << USB_EP_DIEPCTL0_EPDis_Pos)\r
-\r
-#define   USB_EP_DIEPCTL0_SNAK_Pos     (27U)\r
-#define   USB_EP_DIEPCTL0_SNAK_Msk     (0x00000001U  << USB_EP_DIEPCTL0_SNAK_Pos)\r
-\r
-#define   USB_EP_DIEPCTL0_CNAK_Pos     (26U)\r
-#define   USB_EP_DIEPCTL0_CNAK_Msk     (0x00000001U  << USB_EP_DIEPCTL0_CNAK_Pos)\r
-\r
-#define   USB_EP_DIEPCTL0_TxFNum_Pos   (22U)\r
-#define   USB_EP_DIEPCTL0_TxFNum_Msk   (0x0000000FU  << USB_EP_DIEPCTL0_TxFNum_Pos)\r
-\r
-#define   USB_EP_DIEPCTL0_Stall_Pos    (21U)\r
-#define   USB_EP_DIEPCTL0_Stall_Msk    (0x00000001U  << USB_EP_DIEPCTL0_Stall_Pos)\r
-\r
-#define   USB_EP_DIEPCTL0_EPType_Pos   (18U)\r
-#define   USB_EP_DIEPCTL0_EPType_Msk   (0x00000003U  << USB_EP_DIEPCTL0_EPType_Pos)\r
-\r
-#define   USB_EP_DIEPCTL0_NAKSts_Pos   (17U)\r
-#define   USB_EP_DIEPCTL0_NAKSts_Msk   (0x00000001U  << USB_EP_DIEPCTL0_NAKSts_Pos)\r
-\r
-#define   USB_EP_DIEPCTL0_USBActEP_Pos         (15U)\r
-#define   USB_EP_DIEPCTL0_USBActEP_Msk         (0x00000001U  << USB_EP_DIEPCTL0_USBActEP_Pos)\r
-\r
-#define   USB_EP_DIEPCTL0_NextEp_Pos   (11U)\r
-#define   USB_EP_DIEPCTL0_NextEp_Msk   (0x0000000FU  << USB_EP_DIEPCTL0_NextEp_Pos)\r
-\r
-#define   USB_EP_DIEPCTL0_MPS_Pos      (0U)\r
-#define   USB_EP_DIEPCTL0_MPS_Msk      (0x00000003U  << USB_EP_DIEPCTL0_MPS_Pos)\r
-\r
-/* USB_EP_DIEPINT0  =  Device Endpoint-0 Interrupt Register*/\r
-#define   USB_EP_DIEPINT0_NYETIntrpt_Pos       (14U)\r
-#define   USB_EP_DIEPINT0_NYETIntrpt_Msk       (0x00000001U  << USB_EP_DIEPINT0_NYETIntrpt_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_NAKIntrpt_Pos        (13U)\r
-#define   USB_EP_DIEPINT0_NAKIntrpt_Msk        (0x00000001U  << USB_EP_DIEPINT0_NAKIntrpt_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_BbleErrIntrpt_Pos    (12U)\r
-#define   USB_EP_DIEPINT0_BbleErrIntrpt_Msk    (0x00000001U  << USB_EP_DIEPINT0_BbleErrIntrpt_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_PktDrpSts_Pos        (11U)\r
-#define   USB_EP_DIEPINT0_PktDrpSts_Msk        (0x00000001U  << USB_EP_DIEPINT0_PktDrpSts_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_BNAIntr_Pos          (9U)\r
-#define   USB_EP_DIEPINT0_BNAIntr_Msk          (0x00000001U  << USB_EP_DIEPINT0_BNAIntr_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_TxfifoUndrn_Pos      (8U)\r
-#define   USB_EP_DIEPINT0_TxfifoUndrn_Msk      (0x00000001U  << USB_EP_DIEPINT0_TxfifoUndrn_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_TxFEmp_Pos   (7U)\r
-#define   USB_EP_DIEPINT0_TxFEmp_Msk   (0x00000001U  << USB_EP_DIEPINT0_TxFEmp_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_INEPNakEff_Pos       (6U)\r
-#define   USB_EP_DIEPINT0_INEPNakEff_Msk       (0x00000001U  << USB_EP_DIEPINT0_INEPNakEff_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_INTknEPMis_Pos       (5U)\r
-#define   USB_EP_DIEPINT0_INTknEPMis_Msk       (0x00000001U  << USB_EP_DIEPINT0_INTknEPMis_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_INTknTXFEmp_Pos      (4U)\r
-#define   USB_EP_DIEPINT0_INTknTXFEmp_Msk      (0x00000001U  << USB_EP_DIEPINT0_INTknTXFEmp_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_TimeOUT_Pos          (3U)\r
-#define   USB_EP_DIEPINT0_TimeOUT_Msk          (0x00000001U  << USB_EP_DIEPINT0_TimeOUT_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_AHBErr_Pos   (2U)\r
-#define   USB_EP_DIEPINT0_AHBErr_Msk   (0x00000001U  << USB_EP_DIEPINT0_AHBErr_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_EPDisbld_Pos         (1U)\r
-#define   USB_EP_DIEPINT0_EPDisbld_Msk         (0x00000001U  << USB_EP_DIEPINT0_EPDisbld_Pos)\r
-\r
-#define   USB_EP_DIEPINT0_XferCompl_Pos        (0U)\r
-#define   USB_EP_DIEPINT0_XferCompl_Msk        (0x00000001U  << USB_EP_DIEPINT0_XferCompl_Pos)\r
-\r
-/* USB_EP_DIEPTSIZ0  =  Device IN Endpoint x Transfer Size Register*/\r
-#define   USB_EP_DIEPTSIZ0_PktCnt_Pos          (19U)\r
-#define   USB_EP_DIEPTSIZ0_PktCnt_Msk          (0x00000003U  << USB_EP_DIEPTSIZ0_PktCnt_Pos)\r
-\r
-#define   USB_EP_DIEPTSIZ0_XferSize_Pos        (0U)\r
-#define   USB_EP_DIEPTSIZ0_XferSize_Msk        (0x0000007FU  << USB_EP_DIEPTSIZ0_XferSize_Pos)\r
-\r
-/* USB_EP_DIEPDMA0  =  Device Endpoint-0 DMA Address Register*/\r
-#define   USB_EP_DIEPDMA0_DMAAddr_Pos          (0U)\r
-#define   USB_EP_DIEPDMA0_DMAAddr_Msk          (0xFFFFFFFFU  << USB_EP_DIEPDMA0_DMAAddr_Pos)\r
-\r
-/* USB_EP_DTXFSTS0  =  Device IN Endpoint Transmit FIFO Status Register*/\r
-#define   USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos          (0U)\r
-#define   USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk          (0x0000FFFFU  << USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos)\r
-\r
-/* USB_EP_DIEPDMAB0  =  Device Endpoint-0 DMA Buffer Address Register*/\r
-#define   USB_EP_DIEPDMAB0_DMABufferAddr_Pos   (0U)\r
-#define   USB_EP_DIEPDMAB0_DMABufferAddr_Msk   (0xFFFFFFFFU  << USB_EP_DIEPDMAB0_DMABufferAddr_Pos)\r
-\r
-/* USB_EP_DOEPCTL0  =  Device Control OUT Endpoint x Control Register*/\r
-#define   USB_EP_DOEPCTL0_EPEna_Pos    (31U)\r
-#define   USB_EP_DOEPCTL0_EPEna_Msk    (0x00000001U  << USB_EP_DOEPCTL0_EPEna_Pos)\r
-\r
-#define   USB_EP_DOEPCTL0_EPDis_Pos    (30U)\r
-#define   USB_EP_DOEPCTL0_EPDis_Msk    (0x00000001U  << USB_EP_DOEPCTL0_EPDis_Pos)\r
-\r
-#define   USB_EP_DOEPCTL0_SNAK_Pos     (27U)\r
-#define   USB_EP_DOEPCTL0_SNAK_Msk     (0x00000001U  << USB_EP_DOEPCTL0_SNAK_Pos)\r
-\r
-#define   USB_EP_DOEPCTL0_CNAK_Pos     (26U)\r
-#define   USB_EP_DOEPCTL0_CNAK_Msk     (0x00000001U  << USB_EP_DOEPCTL0_CNAK_Pos)\r
-\r
-#define   USB_EP_DOEPCTL0_Stall_Pos    (21U)\r
-#define   USB_EP_DOEPCTL0_Stall_Msk    (0x00000001U  << USB_EP_DOEPCTL0_Stall_Pos)\r
-\r
-#define   USB_EP_DOEPCTL0_Snp_Pos      (20U)\r
-#define   USB_EP_DOEPCTL0_Snp_Msk      (0x00000001U  << USB_EP_DOEPCTL0_Snp_Pos)\r
-\r
-#define   USB_EP_DOEPCTL0_EPType_Pos   (18U)\r
-#define   USB_EP_DOEPCTL0_EPType_Msk   (0x00000003U  << USB_EP_DOEPCTL0_EPType_Pos)\r
-\r
-#define   USB_EP_DOEPCTL0_NAKSts_Pos   (17U)\r
-#define   USB_EP_DOEPCTL0_NAKSts_Msk   (0x00000001U  << USB_EP_DOEPCTL0_NAKSts_Pos)\r
-\r
-#define   USB_EP_DOEPCTL0_USBActEP_Pos         (15U)\r
-#define   USB_EP_DOEPCTL0_USBActEP_Msk         (0x00000001U  << USB_EP_DOEPCTL0_USBActEP_Pos)\r
-\r
-#define   USB_EP_DOEPCTL0_MPS_Pos      (0U)\r
-#define   USB_EP_DOEPCTL0_MPS_Msk      (0x00000003U  << USB_EP_DOEPCTL0_MPS_Pos)\r
-\r
-/* USB_EP_DOEPINT0  =  Device Endpoint-0 Interrupt Register*/\r
-#define   USB_EP_DOEPINT0_NYETIntrpt_Pos       (14U)\r
-#define   USB_EP_DOEPINT0_NYETIntrpt_Msk       (0x00000001U  << USB_EP_DOEPINT0_NYETIntrpt_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_NAKIntrpt_Pos        (13U)\r
-#define   USB_EP_DOEPINT0_NAKIntrpt_Msk        (0x00000001U  << USB_EP_DOEPINT0_NAKIntrpt_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_BbleErrIntrpt_Pos    (12U)\r
-#define   USB_EP_DOEPINT0_BbleErrIntrpt_Msk    (0x00000001U  << USB_EP_DOEPINT0_BbleErrIntrpt_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_PktDrpSts_Pos        (11U)\r
-#define   USB_EP_DOEPINT0_PktDrpSts_Msk        (0x00000001U  << USB_EP_DOEPINT0_PktDrpSts_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_BNAIntr_Pos          (9U)\r
-#define   USB_EP_DOEPINT0_BNAIntr_Msk          (0x00000001U  << USB_EP_DOEPINT0_BNAIntr_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_OutPktErr_Pos        (8U)\r
-#define   USB_EP_DOEPINT0_OutPktErr_Msk        (0x00000001U  << USB_EP_DOEPINT0_OutPktErr_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_Back2BackSETup_Pos   (6U)\r
-#define   USB_EP_DOEPINT0_Back2BackSETup_Msk   (0x00000001U  << USB_EP_DOEPINT0_Back2BackSETup_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_StsPhseRcvd_Pos      (5U)\r
-#define   USB_EP_DOEPINT0_StsPhseRcvd_Msk      (0x00000001U  << USB_EP_DOEPINT0_StsPhseRcvd_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_OUTTknEPdis_Pos      (4U)\r
-#define   USB_EP_DOEPINT0_OUTTknEPdis_Msk      (0x00000001U  << USB_EP_DOEPINT0_OUTTknEPdis_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_SetUp_Pos    (3U)\r
-#define   USB_EP_DOEPINT0_SetUp_Msk    (0x00000001U  << USB_EP_DOEPINT0_SetUp_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_AHBErr_Pos   (2U)\r
-#define   USB_EP_DOEPINT0_AHBErr_Msk   (0x00000001U  << USB_EP_DOEPINT0_AHBErr_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_EPDisbld_Pos         (1U)\r
-#define   USB_EP_DOEPINT0_EPDisbld_Msk         (0x00000001U  << USB_EP_DOEPINT0_EPDisbld_Pos)\r
-\r
-#define   USB_EP_DOEPINT0_XferCompl_Pos        (0U)\r
-#define   USB_EP_DOEPINT0_XferCompl_Msk        (0x00000001U  << USB_EP_DOEPINT0_XferCompl_Pos)\r
-\r
-/* USB_EP_DOEPTSIZ0  =  Device OUT Endpoint x Transfer Size Register*/\r
-#define   USB_EP_DOEPTSIZ0_SUPCnt_Pos          (29U)\r
-#define   USB_EP_DOEPTSIZ0_SUPCnt_Msk          (0x00000003U  << USB_EP_DOEPTSIZ0_SUPCnt_Pos)\r
-\r
-#define   USB_EP_DOEPTSIZ0_PktCnt_Pos          (19U)\r
-#define   USB_EP_DOEPTSIZ0_PktCnt_Msk          (0x00000003U  << USB_EP_DOEPTSIZ0_PktCnt_Pos)\r
-\r
-#define   USB_EP_DOEPTSIZ0_XferSize_Pos        (0U)\r
-#define   USB_EP_DOEPTSIZ0_XferSize_Msk        (0x0000007FU  << USB_EP_DOEPTSIZ0_XferSize_Pos)\r
-\r
-/* USB_EP_DOEPDMA0  =  Device Endpoint-0 DMA Address Register*/\r
-#define   USB_EP_DOEPDMA0_DMAAddr_Pos          (0U)\r
-#define   USB_EP_DOEPDMA0_DMAAddr_Msk          (0xFFFFFFFFU  << USB_EP_DOEPDMA0_DMAAddr_Pos)\r
-\r
-/* USB_EP_DOEPDMAB0  =  Device Endpoint-0 DMA Buffer Address Register*/\r
-#define   USB_EP_DOEPDMAB0_DMABufferAddr_Pos   (0U)\r
-#define   USB_EP_DOEPDMAB0_DMABufferAddr_Msk   (0xFFFFFFFFU  << USB_EP_DOEPDMAB0_DMABufferAddr_Pos)\r
-\r
-/* USB_EP_DIEPCTL_INTBULK  =  Device Endpoint-1 Control Register [Interrupt/Bulk Endpoint]*/\r
-#define   USB_EP_DIEPCTL_INTBULK_EPEna_Pos     (31U)\r
-#define   USB_EP_DIEPCTL_INTBULK_EPEna_Msk     (0x00000001U  << USB_EP_DIEPCTL_INTBULK_EPEna_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_EPDis_Pos     (30U)\r
-#define   USB_EP_DIEPCTL_INTBULK_EPDis_Msk     (0x00000001U  << USB_EP_DIEPCTL_INTBULK_EPDis_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos          (29U)\r
-#define   USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk          (0x00000001U  << USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos          (28U)\r
-#define   USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk          (0x00000001U  << USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_SNAK_Pos      (27U)\r
-#define   USB_EP_DIEPCTL_INTBULK_SNAK_Msk      (0x00000001U  << USB_EP_DIEPCTL_INTBULK_SNAK_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_CNAK_Pos      (26U)\r
-#define   USB_EP_DIEPCTL_INTBULK_CNAK_Msk      (0x00000001U  << USB_EP_DIEPCTL_INTBULK_CNAK_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_TxFNum_Pos    (22U)\r
-#define   USB_EP_DIEPCTL_INTBULK_TxFNum_Msk    (0x0000000FU  << USB_EP_DIEPCTL_INTBULK_TxFNum_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_Stall_Pos     (21U)\r
-#define   USB_EP_DIEPCTL_INTBULK_Stall_Msk     (0x00000001U  << USB_EP_DIEPCTL_INTBULK_Stall_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_Snp_Pos       (20U)\r
-#define   USB_EP_DIEPCTL_INTBULK_Snp_Msk       (0x00000001U  << USB_EP_DIEPCTL_INTBULK_Snp_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_EPType_Pos    (18U)\r
-#define   USB_EP_DIEPCTL_INTBULK_EPType_Msk    (0x00000003U  << USB_EP_DIEPCTL_INTBULK_EPType_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_NAKSts_Pos    (17U)\r
-#define   USB_EP_DIEPCTL_INTBULK_NAKSts_Msk    (0x00000001U  << USB_EP_DIEPCTL_INTBULK_NAKSts_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_DPID_Pos      (16U)\r
-#define   USB_EP_DIEPCTL_INTBULK_DPID_Msk      (0x00000001U  << USB_EP_DIEPCTL_INTBULK_DPID_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_USBActEP_Pos          (15U)\r
-#define   USB_EP_DIEPCTL_INTBULK_USBActEP_Msk          (0x00000001U  << USB_EP_DIEPCTL_INTBULK_USBActEP_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_NextEp_Pos    (11U)\r
-#define   USB_EP_DIEPCTL_INTBULK_NextEp_Msk    (0x0000000FU  << USB_EP_DIEPCTL_INTBULK_NextEp_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_INTBULK_MPS_Pos       (0U)\r
-#define   USB_EP_DIEPCTL_INTBULK_MPS_Msk       (0x000007FFU  << USB_EP_DIEPCTL_INTBULK_MPS_Pos)\r
-\r
-/* USB_EP_DIEPCTL_ISOCONT  =  Device Endpoint-1 Control Register [Isochronous/Control Endpoint]*/\r
-#define   USB_EP_DIEPCTL_ISOCONT_EPEna_Pos     (31U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_EPEna_Msk     (0x00000001U  << USB_EP_DIEPCTL_ISOCONT_EPEna_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_EPDis_Pos     (30U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_EPDis_Msk     (0x00000001U  << USB_EP_DIEPCTL_ISOCONT_EPDis_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos          (29U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk          (0x00000001U  << USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos         (28U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk         (0x00000001U  << USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_SNAK_Pos      (27U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_SNAK_Msk      (0x00000001U  << USB_EP_DIEPCTL_ISOCONT_SNAK_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_CNAK_Pos      (26U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_CNAK_Msk      (0x00000001U  << USB_EP_DIEPCTL_ISOCONT_CNAK_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos    (22U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk    (0x0000000FU  << USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_Stall_Pos     (21U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_Stall_Msk     (0x00000001U  << USB_EP_DIEPCTL_ISOCONT_Stall_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_Snp_Pos       (20U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_Snp_Msk       (0x00000001U  << USB_EP_DIEPCTL_ISOCONT_Snp_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_EPType_Pos    (18U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_EPType_Msk    (0x00000003U  << USB_EP_DIEPCTL_ISOCONT_EPType_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos    (17U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk    (0x00000001U  << USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos          (16U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk          (0x00000001U  << USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos          (15U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk          (0x00000001U  << USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_NextEp_Pos    (11U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_NextEp_Msk    (0x0000000FU  << USB_EP_DIEPCTL_ISOCONT_NextEp_Pos)\r
-\r
-#define   USB_EP_DIEPCTL_ISOCONT_MPS_Pos       (0U)\r
-#define   USB_EP_DIEPCTL_ISOCONT_MPS_Msk       (0x000007FFU  << USB_EP_DIEPCTL_ISOCONT_MPS_Pos)\r
-\r
-/* USB_EP_DIEPINTx  =  Device Endpoint-1 Interrupt Register*/\r
-#define   USB_EP_DIEPINT_NYETIntrpt_Pos        (14U)\r
-#define   USB_EP_DIEPINT_NYETIntrpt_Msk        (0x00000001U  << USB_EP_DIEPINT_NYETIntrpt_Pos)\r
-\r
-#define   USB_EP_DIEPINT_NAKIntrpt_Pos         (13U)\r
-#define   USB_EP_DIEPINT_NAKIntrpt_Msk         (0x00000001U  << USB_EP_DIEPINT_NAKIntrpt_Pos)\r
-\r
-#define   USB_EP_DIEPINT_BbleErrIntrpt_Pos     (12U)\r
-#define   USB_EP_DIEPINT_BbleErrIntrpt_Msk     (0x00000001U  << USB_EP_DIEPINT_BbleErrIntrpt_Pos)\r
-\r
-#define   USB_EP_DIEPINT_PktDrpSts_Pos         (11U)\r
-#define   USB_EP_DIEPINT_PktDrpSts_Msk         (0x00000001U  << USB_EP_DIEPINT_PktDrpSts_Pos)\r
-\r
-#define   USB_EP_DIEPINT_BNAIntr_Pos   (9U)\r
-#define   USB_EP_DIEPINT_BNAIntr_Msk   (0x00000001U  << USB_EP_DIEPINT_BNAIntr_Pos)\r
-\r
-#define   USB_EP_DIEPINT_TxfifoUndrn_Pos       (8U)\r
-#define   USB_EP_DIEPINT_TxfifoUndrn_Msk       (0x00000001U  << USB_EP_DIEPINT_TxfifoUndrn_Pos)\r
-\r
-#define   USB_EP_DIEPINT_TxFEmp_Pos    (7U)\r
-#define   USB_EP_DIEPINT_TxFEmp_Msk    (0x00000001U  << USB_EP_DIEPINT_TxFEmp_Pos)\r
-\r
-#define   USB_EP_DIEPINT_INEPNakEff_Pos        (6U)\r
-#define   USB_EP_DIEPINT_INEPNakEff_Msk        (0x00000001U  << USB_EP_DIEPINT_INEPNakEff_Pos)\r
-\r
-#define   USB_EP_DIEPINT_INTknEPMis_Pos        (5U)\r
-#define   USB_EP_DIEPINT_INTknEPMis_Msk        (0x00000001U  << USB_EP_DIEPINT_INTknEPMis_Pos)\r
-\r
-#define   USB_EP_DIEPINT_INTknTXFEmp_Pos       (4U)\r
-#define   USB_EP_DIEPINT_INTknTXFEmp_Msk       (0x00000001U  << USB_EP_DIEPINT_INTknTXFEmp_Pos)\r
-\r
-#define   USB_EP_DIEPINT_TimeOUT_Pos   (3U)\r
-#define   USB_EP_DIEPINT_TimeOUT_Msk   (0x00000001U  << USB_EP_DIEPINT_TimeOUT_Pos)\r
-\r
-#define   USB_EP_DIEPINT_AHBErr_Pos    (2U)\r
-#define   USB_EP_DIEPINT_AHBErr_Msk    (0x00000001U  << USB_EP_DIEPINT_AHBErr_Pos)\r
-\r
-#define   USB_EP_DIEPINT_EPDisbld_Pos          (1U)\r
-#define   USB_EP_DIEPINT_EPDisbld_Msk          (0x00000001U  << USB_EP_DIEPINT_EPDisbld_Pos)\r
-\r
-#define   USB_EP_DIEPINT_XferCompl_Pos         (0U)\r
-#define   USB_EP_DIEPINT_XferCompl_Msk         (0x00000001U  << USB_EP_DIEPINT_XferCompl_Pos)\r
-\r
-/* USB_EP_DIEPTSIZx  =  Device Endpoint-1 Transfer Size Register*/\r
-#define   USB_EP_DIEPTSIZ_PktCnt_Pos   (19U)\r
-#define   USB_EP_DIEPTSIZ_PktCnt_Msk   (0x000003FFU  << USB_EP_DIEPTSIZ_PktCnt_Pos)\r
-\r
-#define   USB_EP_DIEPTSIZ_XferSize_Pos         (0U)\r
-#define   USB_EP_DIEPTSIZ_XferSize_Msk         (0x0007FFFFU  << USB_EP_DIEPTSIZ_XferSize_Pos)\r
-\r
-/* USB_EP_DIEPDMAx  =  Device Endpoint-1 DMA Address Register*/\r
-#define   USB_EP_DIEPDMA_DMAAddr_Pos   (0U)\r
-#define   USB_EP_DIEPDMA_DMAAddr_Msk   (0xFFFFFFFFU  << USB_EP_DIEPDMA_DMAAddr_Pos)\r
-\r
-/* USB_EP_DTXFSTSx  =  Device IN Endpoint Transmit FIFO Status Register*/\r
-#define   USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos   (0U)\r
-#define   USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk   (0x0000FFFFU  << USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos)\r
-\r
-/* USB_EP_DIEPDMABx  =  Device Endpoint-1 DMA Buffer Address Register*/\r
-#define   USB_EP_DIEPDMAB_DMABufferAddr_Pos    (0U)\r
-#define   USB_EP_DIEPDMAB_DMABufferAddr_Msk    (0xFFFFFFFFU  << USB_EP_DIEPDMAB_DMABufferAddr_Pos)\r
-\r
-/* USB_EP_DOEPCTL_INTBULK  =  Device Endpoint-1 Control Register [Interrupt/Bulk Endpoint]*/\r
-#define   USB_EP_DOEPCTL_INTBULK_EPEna_Pos     (31U)\r
-#define   USB_EP_DOEPCTL_INTBULK_EPEna_Msk     (0x00000001U  << USB_EP_DOEPCTL_INTBULK_EPEna_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_EPDis_Pos     (30U)\r
-#define   USB_EP_DOEPCTL_INTBULK_EPDis_Msk     (0x00000001U  << USB_EP_DOEPCTL_INTBULK_EPDis_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos          (29U)\r
-#define   USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk          (0x00000001U  << USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos          (28U)\r
-#define   USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk          (0x00000001U  << USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_SNAK_Pos      (27U)\r
-#define   USB_EP_DOEPCTL_INTBULK_SNAK_Msk      (0x00000001U  << USB_EP_DOEPCTL_INTBULK_SNAK_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_CNAK_Pos      (26U)\r
-#define   USB_EP_DOEPCTL_INTBULK_CNAK_Msk      (0x00000001U  << USB_EP_DOEPCTL_INTBULK_CNAK_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_TxFNum_Pos    (22U)\r
-#define   USB_EP_DOEPCTL_INTBULK_TxFNum_Msk    (0x0000000FU  << USB_EP_DOEPCTL_INTBULK_TxFNum_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_Stall_Pos     (21U)\r
-#define   USB_EP_DOEPCTL_INTBULK_Stall_Msk     (0x00000001U  << USB_EP_DOEPCTL_INTBULK_Stall_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_Snp_Pos       (20U)\r
-#define   USB_EP_DOEPCTL_INTBULK_Snp_Msk       (0x00000001U  << USB_EP_DOEPCTL_INTBULK_Snp_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_EPType_Pos    (18U)\r
-#define   USB_EP_DOEPCTL_INTBULK_EPType_Msk    (0x00000003U  << USB_EP_DOEPCTL_INTBULK_EPType_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_NAKSts_Pos    (17U)\r
-#define   USB_EP_DOEPCTL_INTBULK_NAKSts_Msk    (0x00000001U  << USB_EP_DOEPCTL_INTBULK_NAKSts_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_DPID_Pos      (16U)\r
-#define   USB_EP_DOEPCTL_INTBULK_DPID_Msk      (0x00000001U  << USB_EP_DOEPCTL_INTBULK_DPID_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_USBActEP_Pos          (15U)\r
-#define   USB_EP_DOEPCTL_INTBULK_USBActEP_Msk          (0x00000001U  << USB_EP_DOEPCTL_INTBULK_USBActEP_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_NextEp_Pos    (11U)\r
-#define   USB_EP_DOEPCTL_INTBULK_NextEp_Msk    (0x0000000FU  << USB_EP_DOEPCTL_INTBULK_NextEp_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_INTBULK_MPS_Pos       (0U)\r
-#define   USB_EP_DOEPCTL_INTBULK_MPS_Msk       (0x000007FFU  << USB_EP_DOEPCTL_INTBULK_MPS_Pos)\r
-\r
-/* USB_EP_DOEPCTL_ISOCONT  =  Device Endpoint-1 Control Register [Isochronous/Control Endpoint]*/\r
-#define   USB_EP_DOEPCTL_ISOCONT_EPEna_Pos     (31U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_EPEna_Msk     (0x00000001U  << USB_EP_DOEPCTL_ISOCONT_EPEna_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_EPDis_Pos     (30U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_EPDis_Msk     (0x00000001U  << USB_EP_DOEPCTL_ISOCONT_EPDis_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos          (29U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk          (0x00000001U  << USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos         (28U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk         (0x00000001U  << USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_SNAK_Pos      (27U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_SNAK_Msk      (0x00000001U  << USB_EP_DOEPCTL_ISOCONT_SNAK_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_CNAK_Pos      (26U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_CNAK_Msk      (0x00000001U  << USB_EP_DOEPCTL_ISOCONT_CNAK_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos    (22U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk    (0x0000000FU  << USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_Stall_Pos     (21U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_Stall_Msk     (0x00000001U  << USB_EP_DOEPCTL_ISOCONT_Stall_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_Snp_Pos       (20U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_Snp_Msk       (0x00000001U  << USB_EP_DOEPCTL_ISOCONT_Snp_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_EPType_Pos    (18U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_EPType_Msk    (0x00000003U  << USB_EP_DOEPCTL_ISOCONT_EPType_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos    (17U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk    (0x00000001U  << USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos          (16U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk          (0x00000001U  << USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos          (15U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk          (0x00000001U  << USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_NextEp_Pos    (11U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_NextEp_Msk    (0x0000000FU  << USB_EP_DOEPCTL_ISOCONT_NextEp_Pos)\r
-\r
-#define   USB_EP_DOEPCTL_ISOCONT_MPS_Pos       (0U)\r
-#define   USB_EP_DOEPCTL_ISOCONT_MPS_Msk       (0x000007FFU  << USB_EP_DOEPCTL_ISOCONT_MPS_Pos)\r
-\r
-/* USB_EP_DOEPINTx  =  Device Endpoint-1 Interrupt Register*/\r
-#define   USB_EP_DOEPINT_NYETIntrpt_Pos        (14U)\r
-#define   USB_EP_DOEPINT_NYETIntrpt_Msk        (0x00000001U  << USB_EP_DOEPINT_NYETIntrpt_Pos)\r
-\r
-#define   USB_EP_DOEPINT_NAKIntrpt_Pos         (13U)\r
-#define   USB_EP_DOEPINT_NAKIntrpt_Msk         (0x00000001U  << USB_EP_DOEPINT_NAKIntrpt_Pos)\r
-\r
-#define   USB_EP_DOEPINT_BbleErrIntrpt_Pos     (12U)\r
-#define   USB_EP_DOEPINT_BbleErrIntrpt_Msk     (0x00000001U  << USB_EP_DOEPINT_BbleErrIntrpt_Pos)\r
-\r
-#define   USB_EP_DOEPINT_PktDrpSts_Pos         (11U)\r
-#define   USB_EP_DOEPINT_PktDrpSts_Msk         (0x00000001U  << USB_EP_DOEPINT_PktDrpSts_Pos)\r
-\r
-#define   USB_EP_DOEPINT_BNAIntr_Pos   (9U)\r
-#define   USB_EP_DOEPINT_BNAIntr_Msk   (0x00000001U  << USB_EP_DOEPINT_BNAIntr_Pos)\r
-\r
-#define   USB_EP_DOEPINT_OutPktErr_Pos         (8U)\r
-#define   USB_EP_DOEPINT_OutPktErr_Msk         (0x00000001U  << USB_EP_DOEPINT_OutPktErr_Pos)\r
-\r
-#define   USB_EP_DOEPINT_Back2BackSETup_Pos    (6U)\r
-#define   USB_EP_DOEPINT_Back2BackSETup_Msk    (0x00000001U  << USB_EP_DOEPINT_Back2BackSETup_Pos)\r
-\r
-#define   USB_EP_DOEPINT_StsPhseRcvd_Pos       (5U)\r
-#define   USB_EP_DOEPINT_StsPhseRcvd_Msk       (0x00000001U  << USB_EP_DOEPINT_StsPhseRcvd_Pos)\r
-\r
-#define   USB_EP_DOEPINT_OUTTknEPdis_Pos       (4U)\r
-#define   USB_EP_DOEPINT_OUTTknEPdis_Msk       (0x00000001U  << USB_EP_DOEPINT_OUTTknEPdis_Pos)\r
-\r
-#define   USB_EP_DOEPINT_SetUp_Pos     (3U)\r
-#define   USB_EP_DOEPINT_SetUp_Msk     (0x00000001U  << USB_EP_DOEPINT_SetUp_Pos)\r
-\r
-#define   USB_EP_DOEPINT_AHBErr_Pos    (2U)\r
-#define   USB_EP_DOEPINT_AHBErr_Msk    (0x00000001U  << USB_EP_DOEPINT_AHBErr_Pos)\r
-\r
-#define   USB_EP_DOEPINT_EPDisbld_Pos          (1U)\r
-#define   USB_EP_DOEPINT_EPDisbld_Msk          (0x00000001U  << USB_EP_DOEPINT_EPDisbld_Pos)\r
-\r
-#define   USB_EP_DOEPINT_XferCompl_Pos         (0U)\r
-#define   USB_EP_DOEPINT_XferCompl_Msk         (0x00000001U  << USB_EP_DOEPINT_XferCompl_Pos)\r
-\r
-/* USB_EP_DOEPTSIZ_ISO  =  Device Endpoint-1 Transfer Size Register [Isochronous OUT Endpoint]*/\r
-#define   USB_EP_DOEPTSIZ_ISO_RxDPID_Pos       (29U)\r
-#define   USB_EP_DOEPTSIZ_ISO_RxDPID_Msk       (0x00000003U  << USB_EP_DOEPTSIZ_ISO_RxDPID_Pos)\r
-\r
-#define   USB_EP_DOEPTSIZ_ISO_PktCnt_Pos       (19U)\r
-#define   USB_EP_DOEPTSIZ_ISO_PktCnt_Msk       (0x000003FFU  << USB_EP_DOEPTSIZ_ISO_PktCnt_Pos)\r
-\r
-#define   USB_EP_DOEPTSIZ_ISO_XferSize_Pos     (0U)\r
-#define   USB_EP_DOEPTSIZ_ISO_XferSize_Msk     (0x0007FFFFU  << USB_EP_DOEPTSIZ_ISO_XferSize_Pos)\r
-\r
-/* USB_EP_DOEPTSIZ_CONTROL  =  Device Endpoint-1 Transfer Size Register [Control OUT Endpoint]*/\r
-#define   USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos   (29U)\r
-#define   USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk   (0x00000003U  << USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos)\r
-\r
-#define   USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos   (19U)\r
-#define   USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk   (0x000003FFU  << USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos)\r
-\r
-#define   USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos         (0U)\r
-#define   USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk         (0x0007FFFFU  << USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos)\r
-\r
-/* USB_EP_DOEPDMAx  =  Device Endpoint-1 DMA Address Register*/\r
-#define   USB_EP_DOEPDMA_DMAAddr_Pos   (0U)\r
-#define   USB_EP_DOEPDMA_DMAAddr_Msk   (0xFFFFFFFFU  << USB_EP_DOEPDMA_DMAAddr_Pos)\r
-\r
-/* USB_EP_DOEPDMABx  =  Device Endpoint-1 DMA Buffer Address Register*/\r
-#define   USB_EP_DOEPDMAB_DMABufferAddr_Pos    (0U)\r
-#define   USB_EP_DOEPDMAB_DMABufferAddr_Msk    (0xFFFFFFFFU  << USB_EP_DOEPDMAB_DMABufferAddr_Pos)\r
-\r
-/* USB_CH_HCCHARx  =  Host Channel-0 Characteristics Register*/\r
-#define   USB_CH_HCCHAR_ChEna_Pos      (31U)\r
-#define   USB_CH_HCCHAR_ChEna_Msk      (0x00000001U  << USB_CH_HCCHAR_ChEna_Pos)\r
-\r
-#define   USB_CH_HCCHAR_ChDis_Pos      (30U)\r
-#define   USB_CH_HCCHAR_ChDis_Msk      (0x00000001U  << USB_CH_HCCHAR_ChDis_Pos)\r
-\r
-#define   USB_CH_HCCHAR_OddFrm_Pos     (29U)\r
-#define   USB_CH_HCCHAR_OddFrm_Msk     (0x00000001U  << USB_CH_HCCHAR_OddFrm_Pos)\r
-\r
-#define   USB_CH_HCCHAR_DevAddr_Pos    (22U)\r
-#define   USB_CH_HCCHAR_DevAddr_Msk    (0x0000007FU  << USB_CH_HCCHAR_DevAddr_Pos)\r
-\r
-#define   USB_CH_HCCHAR_MC_EC_Pos      (20U)\r
-#define   USB_CH_HCCHAR_MC_EC_Msk      (0x00000003U  << USB_CH_HCCHAR_MC_EC_Pos)\r
-\r
-#define   USB_CH_HCCHAR_EPType_Pos     (18U)\r
-#define   USB_CH_HCCHAR_EPType_Msk     (0x00000003U  << USB_CH_HCCHAR_EPType_Pos)\r
-\r
-#define   USB_CH_HCCHAR_LSpdDev_Pos    (17U)\r
-#define   USB_CH_HCCHAR_LSpdDev_Msk    (0x00000001U  << USB_CH_HCCHAR_LSpdDev_Pos)\r
-\r
-#define   USB_CH_HCCHAR_EPDir_Pos      (15U)\r
-#define   USB_CH_HCCHAR_EPDir_Msk      (0x00000001U  << USB_CH_HCCHAR_EPDir_Pos)\r
-\r
-#define   USB_CH_HCCHAR_EPNum_Pos      (11U)\r
-#define   USB_CH_HCCHAR_EPNum_Msk      (0x0000000FU  << USB_CH_HCCHAR_EPNum_Pos)\r
-\r
-#define   USB_CH_HCCHAR_MPS_Pos        (0U)\r
-#define   USB_CH_HCCHAR_MPS_Msk        (0x000007FFU  << USB_CH_HCCHAR_MPS_Pos)\r
-\r
-/* USB_CH_HCINTx  =  Host Channel-0 Interrupt Register*/\r
-#define   USB_CH_HCINT_DESC_LST_ROLLIntr_Pos   (13U)\r
-#define   USB_CH_HCINT_DESC_LST_ROLLIntr_Msk   (0x00000001U  << USB_CH_HCINT_DESC_LST_ROLLIntr_Pos)\r
-\r
-#define   USB_CH_HCINT_XCS_XACT_ERR_Pos        (12U)\r
-#define   USB_CH_HCINT_XCS_XACT_ERR_Msk        (0x00000001U  << USB_CH_HCINT_XCS_XACT_ERR_Pos)\r
-\r
-#define   USB_CH_HCINT_BNAIntr_Pos     (11U)\r
-#define   USB_CH_HCINT_BNAIntr_Msk     (0x00000001U  << USB_CH_HCINT_BNAIntr_Pos)\r
-\r
-#define   USB_CH_HCINT_DataTglErr_Pos          (10U)\r
-#define   USB_CH_HCINT_DataTglErr_Msk          (0x00000001U  << USB_CH_HCINT_DataTglErr_Pos)\r
-\r
-#define   USB_CH_HCINT_FrmOvrun_Pos    (9U)\r
-#define   USB_CH_HCINT_FrmOvrun_Msk    (0x00000001U  << USB_CH_HCINT_FrmOvrun_Pos)\r
-\r
-#define   USB_CH_HCINT_BblErr_Pos      (8U)\r
-#define   USB_CH_HCINT_BblErr_Msk      (0x00000001U  << USB_CH_HCINT_BblErr_Pos)\r
-\r
-#define   USB_CH_HCINT_XactErr_Pos     (7U)\r
-#define   USB_CH_HCINT_XactErr_Msk     (0x00000001U  << USB_CH_HCINT_XactErr_Pos)\r
-\r
-#define   USB_CH_HCINT_NYET_Pos        (6U)\r
-#define   USB_CH_HCINT_NYET_Msk        (0x00000001U  << USB_CH_HCINT_NYET_Pos)\r
-\r
-#define   USB_CH_HCINT_ACK_Pos         (5U)\r
-#define   USB_CH_HCINT_ACK_Msk         (0x00000001U  << USB_CH_HCINT_ACK_Pos)\r
-\r
-#define   USB_CH_HCINT_NAK_Pos         (4U)\r
-#define   USB_CH_HCINT_NAK_Msk         (0x00000001U  << USB_CH_HCINT_NAK_Pos)\r
-\r
-#define   USB_CH_HCINT_STALL_Pos       (3U)\r
-#define   USB_CH_HCINT_STALL_Msk       (0x00000001U  << USB_CH_HCINT_STALL_Pos)\r
-\r
-#define   USB_CH_HCINT_AHBErr_Pos      (2U)\r
-#define   USB_CH_HCINT_AHBErr_Msk      (0x00000001U  << USB_CH_HCINT_AHBErr_Pos)\r
-\r
-#define   USB_CH_HCINT_ChHltd_Pos      (1U)\r
-#define   USB_CH_HCINT_ChHltd_Msk      (0x00000001U  << USB_CH_HCINT_ChHltd_Pos)\r
-\r
-#define   USB_CH_HCINT_XferCompl_Pos   (0U)\r
-#define   USB_CH_HCINT_XferCompl_Msk   (0x00000001U  << USB_CH_HCINT_XferCompl_Pos)\r
-\r
-/* USB_CH_HCINTMSKx  =  Host Channel-0 Interrupt Mask Register*/\r
-#define   USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos     (13U)\r
-#define   USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Msk     (0x00000001U  << USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_BNAIntrMsk_Pos       (11U)\r
-#define   USB_CH_HCINTMSK_BNAIntrMsk_Msk       (0x00000001U  << USB_CH_HCINTMSK_BNAIntrMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_DataTglErrMsk_Pos    (10U)\r
-#define   USB_CH_HCINTMSK_DataTglErrMsk_Msk    (0x00000001U  << USB_CH_HCINTMSK_DataTglErrMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_FrmOvrunMsk_Pos      (9U)\r
-#define   USB_CH_HCINTMSK_FrmOvrunMsk_Msk      (0x00000001U  << USB_CH_HCINTMSK_FrmOvrunMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_BblErrMsk_Pos        (8U)\r
-#define   USB_CH_HCINTMSK_BblErrMsk_Msk        (0x00000001U  << USB_CH_HCINTMSK_BblErrMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_XactErrMsk_Pos       (7U)\r
-#define   USB_CH_HCINTMSK_XactErrMsk_Msk       (0x00000001U  << USB_CH_HCINTMSK_XactErrMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_NyetMsk_Pos          (6U)\r
-#define   USB_CH_HCINTMSK_NyetMsk_Msk          (0x00000001U  << USB_CH_HCINTMSK_NyetMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_AckMsk_Pos   (5U)\r
-#define   USB_CH_HCINTMSK_AckMsk_Msk   (0x00000001U  << USB_CH_HCINTMSK_AckMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_NakMsk_Pos   (4U)\r
-#define   USB_CH_HCINTMSK_NakMsk_Msk   (0x00000001U  << USB_CH_HCINTMSK_NakMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_StallMsk_Pos         (3U)\r
-#define   USB_CH_HCINTMSK_StallMsk_Msk         (0x00000001U  << USB_CH_HCINTMSK_StallMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_AHBErrMsk_Pos        (2U)\r
-#define   USB_CH_HCINTMSK_AHBErrMsk_Msk        (0x00000001U  << USB_CH_HCINTMSK_AHBErrMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_ChHltdMsk_Pos        (1U)\r
-#define   USB_CH_HCINTMSK_ChHltdMsk_Msk        (0x00000001U  << USB_CH_HCINTMSK_ChHltdMsk_Pos)\r
-\r
-#define   USB_CH_HCINTMSK_XferComplMsk_Pos     (0U)\r
-#define   USB_CH_HCINTMSK_XferComplMsk_Msk     (0x00000001U  << USB_CH_HCINTMSK_XferComplMsk_Pos)\r
-\r
-/* USB_CH_HCTSIZ_SCATGATHER  =  Host Channel-0 Transfer Size Register [Scatter/Gather DMA Mode]*/\r
-#define   USB_CH_HCTSIZ_SCATGATHER_DoPng_Pos   (31U)\r
-#define   USB_CH_HCTSIZ_SCATGATHER_DoPng_Msk   (0x00000001U  << USB_CH_HCTSIZ_SCATGATHER_DoPng_Pos)\r
-\r
-#define   USB_CH_HCTSIZ_SCATGATHER_Pid_Pos     (29U)\r
-#define   USB_CH_HCTSIZ_SCATGATHER_Pid_Msk     (0x00000003U  << USB_CH_HCTSIZ_SCATGATHER_Pid_Pos)\r
-\r
-#define   USB_CH_HCTSIZ_SCATGATHER_NTD_Pos     (8U)\r
-#define   USB_CH_HCTSIZ_SCATGATHER_NTD_Msk     (0x000000FFU  << USB_CH_HCTSIZ_SCATGATHER_NTD_Pos)\r
-\r
-#define   USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos      (0U)\r
-#define   USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Msk      (0x000000FFU  << USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos)\r
-\r
-/* USB_CH_HCTSIZ_BUFFERMODE  =  Host Channel-0 Transfer Size Register [Buffer DMA Mode]*/\r
-#define   USB_CH_HCTSIZ_BUFFERMODE_DoPng_Pos   (31U)\r
-#define   USB_CH_HCTSIZ_BUFFERMODE_DoPng_Msk   (0x00000001U  << USB_CH_HCTSIZ_BUFFERMODE_DoPng_Pos)\r
-\r
-#define   USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos     (29U)\r
-#define   USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk     (0x00000003U  << USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos)\r
-\r
-#define   USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos          (19U)\r
-#define   USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk          (0x000003FFU  << USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos)\r
-\r
-#define   USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos        (0U)\r
-#define   USB_CH_HCTSIZ_BUFFERMODE_XferSize_Msk        (0x0007FFFFU  << USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos)\r
-\r
-/* USB_CH_HCDMA_SCATGATHER  =  Host Channel-0 DMA Address Register [Scatter/Gather DMA Mode]*/\r
-#define   USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos          (9U)\r
-#define   USB_CH_HCDMA_SCATGATHER_DMAAddr_Msk          (0x007FFFFFU  << USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos)\r
-\r
-#define   USB_CH_HCDMA_SCATGATHER_CTD_Pos      (3U)\r
-#define   USB_CH_HCDMA_SCATGATHER_CTD_Msk      (0x0000003FU  << USB_CH_HCDMA_SCATGATHER_CTD_Pos)\r
-\r
-/* USB_CH_HCDMA_BUFFERMODE  =  Host Channel-0 DMA Address Register [Buffer DMA Mode]*/\r
-#define   USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos          (0U)\r
-#define   USB_CH_HCDMA_BUFFERMODE_DMAAddr_Msk          (0xFFFFFFFFU  << USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos)\r
-\r
-/* USB_CH_HCDMABx  =  Host Channel-0 DMA Buffer Address Register*/\r
-#define   USB_CH_HCDMAB_Buffer_Address_Pos     (0U)\r
-#define   USB_CH_HCDMAB_Buffer_Address_Msk     (0xFFFFFFFFU  << USB_CH_HCDMAB_Buffer_Address_Pos)\r
-\r
-\r
-\r
-/***   USICx Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* USIC_ID  =  Module Identification Register*/\r
-#define   USIC_ID_MOD_REV_Pos          (0U)\r
-#define   USIC_ID_MOD_REV_Msk          (0x000000FFU  << USIC_ID_MOD_REV_Pos)\r
-\r
-#define   USIC_ID_MOD_TYPE_Pos         (8U)\r
-#define   USIC_ID_MOD_TYPE_Msk         (0x000000FFU  << USIC_ID_MOD_TYPE_Pos)\r
-\r
-#define   USIC_ID_MOD_NUMBER_Pos       (16U)\r
-#define   USIC_ID_MOD_NUMBER_Msk       (0x0000FFFFU  << USIC_ID_MOD_NUMBER_Pos)\r
-\r
-/* USIC_CH_CCFG  =  Channel Configuration Register*/\r
-#define   USIC_CH_CCFG_SSC_Pos         (0U)\r
-#define   USIC_CH_CCFG_SSC_Msk         (0x00000001U  << USIC_CH_CCFG_SSC_Pos)\r
-\r
-#define   USIC_CH_CCFG_ASC_Pos         (1U)\r
-#define   USIC_CH_CCFG_ASC_Msk         (0x00000001U  << USIC_CH_CCFG_ASC_Pos)\r
-\r
-#define   USIC_CH_CCFG_IIC_Pos         (2U)\r
-#define   USIC_CH_CCFG_IIC_Msk         (0x00000001U  << USIC_CH_CCFG_IIC_Pos)\r
-\r
-#define   USIC_CH_CCFG_IIS_Pos         (3U)\r
-#define   USIC_CH_CCFG_IIS_Msk         (0x00000001U  << USIC_CH_CCFG_IIS_Pos)\r
-\r
-#define   USIC_CH_CCFG_RB_Pos          (6U)\r
-#define   USIC_CH_CCFG_RB_Msk          (0x00000001U  << USIC_CH_CCFG_RB_Pos)\r
-\r
-#define   USIC_CH_CCFG_TB_Pos          (7U)\r
-#define   USIC_CH_CCFG_TB_Msk          (0x00000001U  << USIC_CH_CCFG_TB_Pos)\r
-\r
-/* USIC_CH_KSCFG  =  Kernel State Configuration Register*/\r
-#define   USIC_CH_KSCFG_MODEN_Pos      (0U)\r
-#define   USIC_CH_KSCFG_MODEN_Msk      (0x00000001U  << USIC_CH_KSCFG_MODEN_Pos)\r
-\r
-#define   USIC_CH_KSCFG_BPMODEN_Pos    (1U)\r
-#define   USIC_CH_KSCFG_BPMODEN_Msk    (0x00000001U  << USIC_CH_KSCFG_BPMODEN_Pos)\r
-\r
-#define   USIC_CH_KSCFG_NOMCFG_Pos     (4U)\r
-#define   USIC_CH_KSCFG_NOMCFG_Msk     (0x00000003U  << USIC_CH_KSCFG_NOMCFG_Pos)\r
-\r
-#define   USIC_CH_KSCFG_BPNOM_Pos      (7U)\r
-#define   USIC_CH_KSCFG_BPNOM_Msk      (0x00000001U  << USIC_CH_KSCFG_BPNOM_Pos)\r
-\r
-#define   USIC_CH_KSCFG_SUMCFG_Pos     (8U)\r
-#define   USIC_CH_KSCFG_SUMCFG_Msk     (0x00000003U  << USIC_CH_KSCFG_SUMCFG_Pos)\r
-\r
-#define   USIC_CH_KSCFG_BPSUM_Pos      (11U)\r
-#define   USIC_CH_KSCFG_BPSUM_Msk      (0x00000001U  << USIC_CH_KSCFG_BPSUM_Pos)\r
-\r
-/* USIC_CH_FDR  =  Fractional Divider Register*/\r
-#define   USIC_CH_FDR_STEP_Pos         (0U)\r
-#define   USIC_CH_FDR_STEP_Msk         (0x000003FFU  << USIC_CH_FDR_STEP_Pos)\r
-\r
-#define   USIC_CH_FDR_DM_Pos   (14U)\r
-#define   USIC_CH_FDR_DM_Msk   (0x00000003U  << USIC_CH_FDR_DM_Pos)\r
-\r
-#define   USIC_CH_FDR_RESULT_Pos       (16U)\r
-#define   USIC_CH_FDR_RESULT_Msk       (0x000003FFU  << USIC_CH_FDR_RESULT_Pos)\r
-\r
-/* USIC_CH_BRG  =  Baud Rate Generator Register*/\r
-#define   USIC_CH_BRG_CLKSEL_Pos       (0U)\r
-#define   USIC_CH_BRG_CLKSEL_Msk       (0x00000003U  << USIC_CH_BRG_CLKSEL_Pos)\r
-\r
-#define   USIC_CH_BRG_TMEN_Pos         (3U)\r
-#define   USIC_CH_BRG_TMEN_Msk         (0x00000001U  << USIC_CH_BRG_TMEN_Pos)\r
-\r
-#define   USIC_CH_BRG_PPPEN_Pos        (4U)\r
-#define   USIC_CH_BRG_PPPEN_Msk        (0x00000001U  << USIC_CH_BRG_PPPEN_Pos)\r
-\r
-#define   USIC_CH_BRG_CTQSEL_Pos       (6U)\r
-#define   USIC_CH_BRG_CTQSEL_Msk       (0x00000003U  << USIC_CH_BRG_CTQSEL_Pos)\r
-\r
-#define   USIC_CH_BRG_PCTQ_Pos         (8U)\r
-#define   USIC_CH_BRG_PCTQ_Msk         (0x00000003U  << USIC_CH_BRG_PCTQ_Pos)\r
-\r
-#define   USIC_CH_BRG_DCTQ_Pos         (10U)\r
-#define   USIC_CH_BRG_DCTQ_Msk         (0x0000001FU  << USIC_CH_BRG_DCTQ_Pos)\r
-\r
-#define   USIC_CH_BRG_PDIV_Pos         (16U)\r
-#define   USIC_CH_BRG_PDIV_Msk         (0x000003FFU  << USIC_CH_BRG_PDIV_Pos)\r
-\r
-#define   USIC_CH_BRG_MCLKCFG_Pos      (29U)\r
-#define   USIC_CH_BRG_MCLKCFG_Msk      (0x00000001U  << USIC_CH_BRG_MCLKCFG_Pos)\r
-\r
-#define   USIC_CH_BRG_SCLKCFG_Pos      (30U)\r
-#define   USIC_CH_BRG_SCLKCFG_Msk      (0x00000003U  << USIC_CH_BRG_SCLKCFG_Pos)\r
-\r
-/* USIC_CH_INPR  =  Interrupt Node Pointer Register*/\r
-#define   USIC_CH_INPR_TSINP_Pos       (0U)\r
-#define   USIC_CH_INPR_TSINP_Msk       (0x00000007U  << USIC_CH_INPR_TSINP_Pos)\r
-\r
-#define   USIC_CH_INPR_TBINP_Pos       (4U)\r
-#define   USIC_CH_INPR_TBINP_Msk       (0x00000007U  << USIC_CH_INPR_TBINP_Pos)\r
-\r
-#define   USIC_CH_INPR_RINP_Pos        (8U)\r
-#define   USIC_CH_INPR_RINP_Msk        (0x00000007U  << USIC_CH_INPR_RINP_Pos)\r
-\r
-#define   USIC_CH_INPR_AINP_Pos        (12U)\r
-#define   USIC_CH_INPR_AINP_Msk        (0x00000007U  << USIC_CH_INPR_AINP_Pos)\r
-\r
-#define   USIC_CH_INPR_PINP_Pos        (16U)\r
-#define   USIC_CH_INPR_PINP_Msk        (0x00000007U  << USIC_CH_INPR_PINP_Pos)\r
-\r
-/* USIC_CH_DX0CR  =  Input Control Register 0*/\r
-#define   USIC_CH_DX0CR_DSEL_Pos       (0U)\r
-#define   USIC_CH_DX0CR_DSEL_Msk       (0x00000007U  << USIC_CH_DX0CR_DSEL_Pos)\r
-\r
-#define   USIC_CH_DX0CR_INSW_Pos       (4U)\r
-#define   USIC_CH_DX0CR_INSW_Msk       (0x00000001U  << USIC_CH_DX0CR_INSW_Pos)\r
-\r
-#define   USIC_CH_DX0CR_DFEN_Pos       (5U)\r
-#define   USIC_CH_DX0CR_DFEN_Msk       (0x00000001U  << USIC_CH_DX0CR_DFEN_Pos)\r
-\r
-#define   USIC_CH_DX0CR_DSEN_Pos       (6U)\r
-#define   USIC_CH_DX0CR_DSEN_Msk       (0x00000001U  << USIC_CH_DX0CR_DSEN_Pos)\r
-\r
-#define   USIC_CH_DX0CR_DPOL_Pos       (8U)\r
-#define   USIC_CH_DX0CR_DPOL_Msk       (0x00000001U  << USIC_CH_DX0CR_DPOL_Pos)\r
-\r
-#define   USIC_CH_DX0CR_SFSEL_Pos      (9U)\r
-#define   USIC_CH_DX0CR_SFSEL_Msk      (0x00000001U  << USIC_CH_DX0CR_SFSEL_Pos)\r
-\r
-#define   USIC_CH_DX0CR_CM_Pos         (10U)\r
-#define   USIC_CH_DX0CR_CM_Msk         (0x00000003U  << USIC_CH_DX0CR_CM_Pos)\r
-\r
-#define   USIC_CH_DX0CR_DXS_Pos        (15U)\r
-#define   USIC_CH_DX0CR_DXS_Msk        (0x00000001U  << USIC_CH_DX0CR_DXS_Pos)\r
-\r
-/* USIC_CH_DX1CR  =  Input Control Register 1*/\r
-#define   USIC_CH_DX1CR_DSEL_Pos       (0U)\r
-#define   USIC_CH_DX1CR_DSEL_Msk       (0x00000007U  << USIC_CH_DX1CR_DSEL_Pos)\r
-\r
-#define   USIC_CH_DX1CR_DCEN_Pos       (3U)\r
-#define   USIC_CH_DX1CR_DCEN_Msk       (0x00000001U  << USIC_CH_DX1CR_DCEN_Pos)\r
-\r
-#define   USIC_CH_DX1CR_INSW_Pos       (4U)\r
-#define   USIC_CH_DX1CR_INSW_Msk       (0x00000001U  << USIC_CH_DX1CR_INSW_Pos)\r
-\r
-#define   USIC_CH_DX1CR_DFEN_Pos       (5U)\r
-#define   USIC_CH_DX1CR_DFEN_Msk       (0x00000001U  << USIC_CH_DX1CR_DFEN_Pos)\r
-\r
-#define   USIC_CH_DX1CR_DSEN_Pos       (6U)\r
-#define   USIC_CH_DX1CR_DSEN_Msk       (0x00000001U  << USIC_CH_DX1CR_DSEN_Pos)\r
-\r
-#define   USIC_CH_DX1CR_DPOL_Pos       (8U)\r
-#define   USIC_CH_DX1CR_DPOL_Msk       (0x00000001U  << USIC_CH_DX1CR_DPOL_Pos)\r
-\r
-#define   USIC_CH_DX1CR_SFSEL_Pos      (9U)\r
-#define   USIC_CH_DX1CR_SFSEL_Msk      (0x00000001U  << USIC_CH_DX1CR_SFSEL_Pos)\r
-\r
-#define   USIC_CH_DX1CR_CM_Pos         (10U)\r
-#define   USIC_CH_DX1CR_CM_Msk         (0x00000003U  << USIC_CH_DX1CR_CM_Pos)\r
-\r
-#define   USIC_CH_DX1CR_DXS_Pos        (15U)\r
-#define   USIC_CH_DX1CR_DXS_Msk        (0x00000001U  << USIC_CH_DX1CR_DXS_Pos)\r
-\r
-/* USIC_CH_DX2CR  =  Input Control Register 2*/\r
-#define   USIC_CH_DX2CR_DSEL_Pos       (0U)\r
-#define   USIC_CH_DX2CR_DSEL_Msk       (0x00000007U  << USIC_CH_DX2CR_DSEL_Pos)\r
-\r
-#define   USIC_CH_DX2CR_INSW_Pos       (4U)\r
-#define   USIC_CH_DX2CR_INSW_Msk       (0x00000001U  << USIC_CH_DX2CR_INSW_Pos)\r
-\r
-#define   USIC_CH_DX2CR_DFEN_Pos       (5U)\r
-#define   USIC_CH_DX2CR_DFEN_Msk       (0x00000001U  << USIC_CH_DX2CR_DFEN_Pos)\r
-\r
-#define   USIC_CH_DX2CR_DSEN_Pos       (6U)\r
-#define   USIC_CH_DX2CR_DSEN_Msk       (0x00000001U  << USIC_CH_DX2CR_DSEN_Pos)\r
-\r
-#define   USIC_CH_DX2CR_DPOL_Pos       (8U)\r
-#define   USIC_CH_DX2CR_DPOL_Msk       (0x00000001U  << USIC_CH_DX2CR_DPOL_Pos)\r
-\r
-#define   USIC_CH_DX2CR_SFSEL_Pos      (9U)\r
-#define   USIC_CH_DX2CR_SFSEL_Msk      (0x00000001U  << USIC_CH_DX2CR_SFSEL_Pos)\r
-\r
-#define   USIC_CH_DX2CR_CM_Pos         (10U)\r
-#define   USIC_CH_DX2CR_CM_Msk         (0x00000003U  << USIC_CH_DX2CR_CM_Pos)\r
-\r
-#define   USIC_CH_DX2CR_DXS_Pos        (15U)\r
-#define   USIC_CH_DX2CR_DXS_Msk        (0x00000001U  << USIC_CH_DX2CR_DXS_Pos)\r
-\r
-/* USIC_CH_DX3CR  =  Input Control Register 3*/\r
-#define   USIC_CH_DX3CR_DSEL_Pos       (0U)\r
-#define   USIC_CH_DX3CR_DSEL_Msk       (0x00000007U  << USIC_CH_DX3CR_DSEL_Pos)\r
-\r
-#define   USIC_CH_DX3CR_INSW_Pos       (4U)\r
-#define   USIC_CH_DX3CR_INSW_Msk       (0x00000001U  << USIC_CH_DX3CR_INSW_Pos)\r
-\r
-#define   USIC_CH_DX3CR_DFEN_Pos       (5U)\r
-#define   USIC_CH_DX3CR_DFEN_Msk       (0x00000001U  << USIC_CH_DX3CR_DFEN_Pos)\r
-\r
-#define   USIC_CH_DX3CR_DSEN_Pos       (6U)\r
-#define   USIC_CH_DX3CR_DSEN_Msk       (0x00000001U  << USIC_CH_DX3CR_DSEN_Pos)\r
-\r
-#define   USIC_CH_DX3CR_DPOL_Pos       (8U)\r
-#define   USIC_CH_DX3CR_DPOL_Msk       (0x00000001U  << USIC_CH_DX3CR_DPOL_Pos)\r
-\r
-#define   USIC_CH_DX3CR_SFSEL_Pos      (9U)\r
-#define   USIC_CH_DX3CR_SFSEL_Msk      (0x00000001U  << USIC_CH_DX3CR_SFSEL_Pos)\r
-\r
-#define   USIC_CH_DX3CR_CM_Pos         (10U)\r
-#define   USIC_CH_DX3CR_CM_Msk         (0x00000003U  << USIC_CH_DX3CR_CM_Pos)\r
-\r
-#define   USIC_CH_DX3CR_DXS_Pos        (15U)\r
-#define   USIC_CH_DX3CR_DXS_Msk        (0x00000001U  << USIC_CH_DX3CR_DXS_Pos)\r
-\r
-/* USIC_CH_DX4CR  =  Input Control Register 4*/\r
-#define   USIC_CH_DX4CR_DSEL_Pos       (0U)\r
-#define   USIC_CH_DX4CR_DSEL_Msk       (0x00000007U  << USIC_CH_DX4CR_DSEL_Pos)\r
-\r
-#define   USIC_CH_DX4CR_INSW_Pos       (4U)\r
-#define   USIC_CH_DX4CR_INSW_Msk       (0x00000001U  << USIC_CH_DX4CR_INSW_Pos)\r
-\r
-#define   USIC_CH_DX4CR_DFEN_Pos       (5U)\r
-#define   USIC_CH_DX4CR_DFEN_Msk       (0x00000001U  << USIC_CH_DX4CR_DFEN_Pos)\r
-\r
-#define   USIC_CH_DX4CR_DSEN_Pos       (6U)\r
-#define   USIC_CH_DX4CR_DSEN_Msk       (0x00000001U  << USIC_CH_DX4CR_DSEN_Pos)\r
-\r
-#define   USIC_CH_DX4CR_DPOL_Pos       (8U)\r
-#define   USIC_CH_DX4CR_DPOL_Msk       (0x00000001U  << USIC_CH_DX4CR_DPOL_Pos)\r
-\r
-#define   USIC_CH_DX4CR_SFSEL_Pos      (9U)\r
-#define   USIC_CH_DX4CR_SFSEL_Msk      (0x00000001U  << USIC_CH_DX4CR_SFSEL_Pos)\r
-\r
-#define   USIC_CH_DX4CR_CM_Pos         (10U)\r
-#define   USIC_CH_DX4CR_CM_Msk         (0x00000003U  << USIC_CH_DX4CR_CM_Pos)\r
-\r
-#define   USIC_CH_DX4CR_DXS_Pos        (15U)\r
-#define   USIC_CH_DX4CR_DXS_Msk        (0x00000001U  << USIC_CH_DX4CR_DXS_Pos)\r
-\r
-/* USIC_CH_DX5CR  =  Input Control Register 5*/\r
-#define   USIC_CH_DX5CR_DSEL_Pos       (0U)\r
-#define   USIC_CH_DX5CR_DSEL_Msk       (0x00000007U  << USIC_CH_DX5CR_DSEL_Pos)\r
-\r
-#define   USIC_CH_DX5CR_INSW_Pos       (4U)\r
-#define   USIC_CH_DX5CR_INSW_Msk       (0x00000001U  << USIC_CH_DX5CR_INSW_Pos)\r
-\r
-#define   USIC_CH_DX5CR_DFEN_Pos       (5U)\r
-#define   USIC_CH_DX5CR_DFEN_Msk       (0x00000001U  << USIC_CH_DX5CR_DFEN_Pos)\r
-\r
-#define   USIC_CH_DX5CR_DSEN_Pos       (6U)\r
-#define   USIC_CH_DX5CR_DSEN_Msk       (0x00000001U  << USIC_CH_DX5CR_DSEN_Pos)\r
-\r
-#define   USIC_CH_DX5CR_DPOL_Pos       (8U)\r
-#define   USIC_CH_DX5CR_DPOL_Msk       (0x00000001U  << USIC_CH_DX5CR_DPOL_Pos)\r
-\r
-#define   USIC_CH_DX5CR_SFSEL_Pos      (9U)\r
-#define   USIC_CH_DX5CR_SFSEL_Msk      (0x00000001U  << USIC_CH_DX5CR_SFSEL_Pos)\r
-\r
-#define   USIC_CH_DX5CR_CM_Pos         (10U)\r
-#define   USIC_CH_DX5CR_CM_Msk         (0x00000003U  << USIC_CH_DX5CR_CM_Pos)\r
-\r
-#define   USIC_CH_DX5CR_DXS_Pos        (15U)\r
-#define   USIC_CH_DX5CR_DXS_Msk        (0x00000001U  << USIC_CH_DX5CR_DXS_Pos)\r
-\r
-/* USIC_CH_SCTR  =  Shift Control Register*/\r
-#define   USIC_CH_SCTR_SDIR_Pos        (0U)\r
-#define   USIC_CH_SCTR_SDIR_Msk        (0x00000001U  << USIC_CH_SCTR_SDIR_Pos)\r
-\r
-#define   USIC_CH_SCTR_PDL_Pos         (1U)\r
-#define   USIC_CH_SCTR_PDL_Msk         (0x00000001U  << USIC_CH_SCTR_PDL_Pos)\r
-\r
-#define   USIC_CH_SCTR_DSM_Pos         (2U)\r
-#define   USIC_CH_SCTR_DSM_Msk         (0x00000003U  << USIC_CH_SCTR_DSM_Pos)\r
-\r
-#define   USIC_CH_SCTR_HPCDIR_Pos      (4U)\r
-#define   USIC_CH_SCTR_HPCDIR_Msk      (0x00000001U  << USIC_CH_SCTR_HPCDIR_Pos)\r
-\r
-#define   USIC_CH_SCTR_DOCFG_Pos       (6U)\r
-#define   USIC_CH_SCTR_DOCFG_Msk       (0x00000003U  << USIC_CH_SCTR_DOCFG_Pos)\r
-\r
-#define   USIC_CH_SCTR_TRM_Pos         (8U)\r
-#define   USIC_CH_SCTR_TRM_Msk         (0x00000003U  << USIC_CH_SCTR_TRM_Pos)\r
-\r
-#define   USIC_CH_SCTR_FLE_Pos         (16U)\r
-#define   USIC_CH_SCTR_FLE_Msk         (0x0000003FU  << USIC_CH_SCTR_FLE_Pos)\r
-\r
-#define   USIC_CH_SCTR_WLE_Pos         (24U)\r
-#define   USIC_CH_SCTR_WLE_Msk         (0x0000000FU  << USIC_CH_SCTR_WLE_Pos)\r
-\r
-/* USIC_CH_TCSR  =  Transmit Control/Status Register*/\r
-#define   USIC_CH_TCSR_WLEMD_Pos       (0U)\r
-#define   USIC_CH_TCSR_WLEMD_Msk       (0x00000001U  << USIC_CH_TCSR_WLEMD_Pos)\r
-\r
-#define   USIC_CH_TCSR_SELMD_Pos       (1U)\r
-#define   USIC_CH_TCSR_SELMD_Msk       (0x00000001U  << USIC_CH_TCSR_SELMD_Pos)\r
-\r
-#define   USIC_CH_TCSR_FLEMD_Pos       (2U)\r
-#define   USIC_CH_TCSR_FLEMD_Msk       (0x00000001U  << USIC_CH_TCSR_FLEMD_Pos)\r
-\r
-#define   USIC_CH_TCSR_WAMD_Pos        (3U)\r
-#define   USIC_CH_TCSR_WAMD_Msk        (0x00000001U  << USIC_CH_TCSR_WAMD_Pos)\r
-\r
-#define   USIC_CH_TCSR_HPCMD_Pos       (4U)\r
-#define   USIC_CH_TCSR_HPCMD_Msk       (0x00000001U  << USIC_CH_TCSR_HPCMD_Pos)\r
-\r
-#define   USIC_CH_TCSR_SOF_Pos         (5U)\r
-#define   USIC_CH_TCSR_SOF_Msk         (0x00000001U  << USIC_CH_TCSR_SOF_Pos)\r
-\r
-#define   USIC_CH_TCSR_EOF_Pos         (6U)\r
-#define   USIC_CH_TCSR_EOF_Msk         (0x00000001U  << USIC_CH_TCSR_EOF_Pos)\r
-\r
-#define   USIC_CH_TCSR_TDV_Pos         (7U)\r
-#define   USIC_CH_TCSR_TDV_Msk         (0x00000001U  << USIC_CH_TCSR_TDV_Pos)\r
-\r
-#define   USIC_CH_TCSR_TDSSM_Pos       (8U)\r
-#define   USIC_CH_TCSR_TDSSM_Msk       (0x00000001U  << USIC_CH_TCSR_TDSSM_Pos)\r
-\r
-#define   USIC_CH_TCSR_TDEN_Pos        (10U)\r
-#define   USIC_CH_TCSR_TDEN_Msk        (0x00000003U  << USIC_CH_TCSR_TDEN_Pos)\r
-\r
-#define   USIC_CH_TCSR_TDVTR_Pos       (12U)\r
-#define   USIC_CH_TCSR_TDVTR_Msk       (0x00000001U  << USIC_CH_TCSR_TDVTR_Pos)\r
-\r
-#define   USIC_CH_TCSR_WA_Pos          (13U)\r
-#define   USIC_CH_TCSR_WA_Msk          (0x00000001U  << USIC_CH_TCSR_WA_Pos)\r
-\r
-#define   USIC_CH_TCSR_TSOF_Pos        (24U)\r
-#define   USIC_CH_TCSR_TSOF_Msk        (0x00000001U  << USIC_CH_TCSR_TSOF_Pos)\r
-\r
-#define   USIC_CH_TCSR_TV_Pos          (26U)\r
-#define   USIC_CH_TCSR_TV_Msk          (0x00000001U  << USIC_CH_TCSR_TV_Pos)\r
-\r
-#define   USIC_CH_TCSR_TVC_Pos         (27U)\r
-#define   USIC_CH_TCSR_TVC_Msk         (0x00000001U  << USIC_CH_TCSR_TVC_Pos)\r
-\r
-#define   USIC_CH_TCSR_TE_Pos          (28U)\r
-#define   USIC_CH_TCSR_TE_Msk          (0x00000001U  << USIC_CH_TCSR_TE_Pos)\r
-\r
-/* USIC_CH_PCR  =  Protocol Control Register*/\r
-#define   USIC_CH_PCR_CTR0_Pos         (0U)\r
-#define   USIC_CH_PCR_CTR0_Msk         (0x00000001U  << USIC_CH_PCR_CTR0_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR1_Pos         (1U)\r
-#define   USIC_CH_PCR_CTR1_Msk         (0x00000001U  << USIC_CH_PCR_CTR1_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR2_Pos         (2U)\r
-#define   USIC_CH_PCR_CTR2_Msk         (0x00000001U  << USIC_CH_PCR_CTR2_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR3_Pos         (3U)\r
-#define   USIC_CH_PCR_CTR3_Msk         (0x00000001U  << USIC_CH_PCR_CTR3_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR4_Pos         (4U)\r
-#define   USIC_CH_PCR_CTR4_Msk         (0x00000001U  << USIC_CH_PCR_CTR4_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR5_Pos         (5U)\r
-#define   USIC_CH_PCR_CTR5_Msk         (0x00000001U  << USIC_CH_PCR_CTR5_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR6_Pos         (6U)\r
-#define   USIC_CH_PCR_CTR6_Msk         (0x00000001U  << USIC_CH_PCR_CTR6_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR7_Pos         (7U)\r
-#define   USIC_CH_PCR_CTR7_Msk         (0x00000001U  << USIC_CH_PCR_CTR7_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR8_Pos         (8U)\r
-#define   USIC_CH_PCR_CTR8_Msk         (0x00000001U  << USIC_CH_PCR_CTR8_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR9_Pos         (9U)\r
-#define   USIC_CH_PCR_CTR9_Msk         (0x00000001U  << USIC_CH_PCR_CTR9_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR10_Pos        (10U)\r
-#define   USIC_CH_PCR_CTR10_Msk        (0x00000001U  << USIC_CH_PCR_CTR10_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR11_Pos        (11U)\r
-#define   USIC_CH_PCR_CTR11_Msk        (0x00000001U  << USIC_CH_PCR_CTR11_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR12_Pos        (12U)\r
-#define   USIC_CH_PCR_CTR12_Msk        (0x00000001U  << USIC_CH_PCR_CTR12_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR13_Pos        (13U)\r
-#define   USIC_CH_PCR_CTR13_Msk        (0x00000001U  << USIC_CH_PCR_CTR13_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR14_Pos        (14U)\r
-#define   USIC_CH_PCR_CTR14_Msk        (0x00000001U  << USIC_CH_PCR_CTR14_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR15_Pos        (15U)\r
-#define   USIC_CH_PCR_CTR15_Msk        (0x00000001U  << USIC_CH_PCR_CTR15_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR16_Pos        (16U)\r
-#define   USIC_CH_PCR_CTR16_Msk        (0x00000001U  << USIC_CH_PCR_CTR16_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR17_Pos        (17U)\r
-#define   USIC_CH_PCR_CTR17_Msk        (0x00000001U  << USIC_CH_PCR_CTR17_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR18_Pos        (18U)\r
-#define   USIC_CH_PCR_CTR18_Msk        (0x00000001U  << USIC_CH_PCR_CTR18_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR19_Pos        (19U)\r
-#define   USIC_CH_PCR_CTR19_Msk        (0x00000001U  << USIC_CH_PCR_CTR19_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR20_Pos        (20U)\r
-#define   USIC_CH_PCR_CTR20_Msk        (0x00000001U  << USIC_CH_PCR_CTR20_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR21_Pos        (21U)\r
-#define   USIC_CH_PCR_CTR21_Msk        (0x00000001U  << USIC_CH_PCR_CTR21_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR22_Pos        (22U)\r
-#define   USIC_CH_PCR_CTR22_Msk        (0x00000001U  << USIC_CH_PCR_CTR22_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR23_Pos        (23U)\r
-#define   USIC_CH_PCR_CTR23_Msk        (0x00000001U  << USIC_CH_PCR_CTR23_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR24_Pos        (24U)\r
-#define   USIC_CH_PCR_CTR24_Msk        (0x00000001U  << USIC_CH_PCR_CTR24_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR25_Pos        (25U)\r
-#define   USIC_CH_PCR_CTR25_Msk        (0x00000001U  << USIC_CH_PCR_CTR25_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR26_Pos        (26U)\r
-#define   USIC_CH_PCR_CTR26_Msk        (0x00000001U  << USIC_CH_PCR_CTR26_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR27_Pos        (27U)\r
-#define   USIC_CH_PCR_CTR27_Msk        (0x00000001U  << USIC_CH_PCR_CTR27_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR28_Pos        (28U)\r
-#define   USIC_CH_PCR_CTR28_Msk        (0x00000001U  << USIC_CH_PCR_CTR28_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR29_Pos        (29U)\r
-#define   USIC_CH_PCR_CTR29_Msk        (0x00000001U  << USIC_CH_PCR_CTR29_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR30_Pos        (30U)\r
-#define   USIC_CH_PCR_CTR30_Msk        (0x00000001U  << USIC_CH_PCR_CTR30_Pos)\r
-\r
-#define   USIC_CH_PCR_CTR31_Pos        (31U)\r
-#define   USIC_CH_PCR_CTR31_Msk        (0x00000001U  << USIC_CH_PCR_CTR31_Pos)\r
-\r
-/* USIC_CH_PCR_ASCMode  =  Protocol Control Register [ASC Mode]*/\r
-#define   USIC_CH_PCR_ASCMode_SMD_Pos          (0U)\r
-#define   USIC_CH_PCR_ASCMode_SMD_Msk          (0x00000001U  << USIC_CH_PCR_ASCMode_SMD_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_STPB_Pos         (1U)\r
-#define   USIC_CH_PCR_ASCMode_STPB_Msk         (0x00000001U  << USIC_CH_PCR_ASCMode_STPB_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_IDM_Pos          (2U)\r
-#define   USIC_CH_PCR_ASCMode_IDM_Msk          (0x00000001U  << USIC_CH_PCR_ASCMode_IDM_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_SBIEN_Pos        (3U)\r
-#define   USIC_CH_PCR_ASCMode_SBIEN_Msk        (0x00000001U  << USIC_CH_PCR_ASCMode_SBIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_CDEN_Pos         (4U)\r
-#define   USIC_CH_PCR_ASCMode_CDEN_Msk         (0x00000001U  << USIC_CH_PCR_ASCMode_CDEN_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_RNIEN_Pos        (5U)\r
-#define   USIC_CH_PCR_ASCMode_RNIEN_Msk        (0x00000001U  << USIC_CH_PCR_ASCMode_RNIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_FEIEN_Pos        (6U)\r
-#define   USIC_CH_PCR_ASCMode_FEIEN_Msk        (0x00000001U  << USIC_CH_PCR_ASCMode_FEIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_FFIEN_Pos        (7U)\r
-#define   USIC_CH_PCR_ASCMode_FFIEN_Msk        (0x00000001U  << USIC_CH_PCR_ASCMode_FFIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_SP_Pos   (8U)\r
-#define   USIC_CH_PCR_ASCMode_SP_Msk   (0x0000001FU  << USIC_CH_PCR_ASCMode_SP_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_PL_Pos   (13U)\r
-#define   USIC_CH_PCR_ASCMode_PL_Msk   (0x00000007U  << USIC_CH_PCR_ASCMode_PL_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_RSTEN_Pos        (16U)\r
-#define   USIC_CH_PCR_ASCMode_RSTEN_Msk        (0x00000001U  << USIC_CH_PCR_ASCMode_RSTEN_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_TSTEN_Pos        (17U)\r
-#define   USIC_CH_PCR_ASCMode_TSTEN_Msk        (0x00000001U  << USIC_CH_PCR_ASCMode_TSTEN_Pos)\r
-\r
-#define   USIC_CH_PCR_ASCMode_MCLK_Pos         (31U)\r
-#define   USIC_CH_PCR_ASCMode_MCLK_Msk         (0x00000001U  << USIC_CH_PCR_ASCMode_MCLK_Pos)\r
-\r
-/* USIC_CH_PCR_SSCMode  =  Protocol Control Register [SSC Mode]*/\r
-#define   USIC_CH_PCR_SSCMode_MSLSEN_Pos       (0U)\r
-#define   USIC_CH_PCR_SSCMode_MSLSEN_Msk       (0x00000001U  << USIC_CH_PCR_SSCMode_MSLSEN_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_SELCTR_Pos       (1U)\r
-#define   USIC_CH_PCR_SSCMode_SELCTR_Msk       (0x00000001U  << USIC_CH_PCR_SSCMode_SELCTR_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_SELINV_Pos       (2U)\r
-#define   USIC_CH_PCR_SSCMode_SELINV_Msk       (0x00000001U  << USIC_CH_PCR_SSCMode_SELINV_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_FEM_Pos          (3U)\r
-#define   USIC_CH_PCR_SSCMode_FEM_Msk          (0x00000001U  << USIC_CH_PCR_SSCMode_FEM_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_CTQSEL1_Pos      (4U)\r
-#define   USIC_CH_PCR_SSCMode_CTQSEL1_Msk      (0x00000003U  << USIC_CH_PCR_SSCMode_CTQSEL1_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_PCTQ1_Pos        (6U)\r
-#define   USIC_CH_PCR_SSCMode_PCTQ1_Msk        (0x00000003U  << USIC_CH_PCR_SSCMode_PCTQ1_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_DCTQ1_Pos        (8U)\r
-#define   USIC_CH_PCR_SSCMode_DCTQ1_Msk        (0x0000001FU  << USIC_CH_PCR_SSCMode_DCTQ1_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_PARIEN_Pos       (13U)\r
-#define   USIC_CH_PCR_SSCMode_PARIEN_Msk       (0x00000001U  << USIC_CH_PCR_SSCMode_PARIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_MSLSIEN_Pos      (14U)\r
-#define   USIC_CH_PCR_SSCMode_MSLSIEN_Msk      (0x00000001U  << USIC_CH_PCR_SSCMode_MSLSIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_DX2TIEN_Pos      (15U)\r
-#define   USIC_CH_PCR_SSCMode_DX2TIEN_Msk      (0x00000001U  << USIC_CH_PCR_SSCMode_DX2TIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_SELO_Pos         (16U)\r
-#define   USIC_CH_PCR_SSCMode_SELO_Msk         (0x000000FFU  << USIC_CH_PCR_SSCMode_SELO_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_TIWEN_Pos        (24U)\r
-#define   USIC_CH_PCR_SSCMode_TIWEN_Msk        (0x00000001U  << USIC_CH_PCR_SSCMode_TIWEN_Pos)\r
-\r
-#define   USIC_CH_PCR_SSCMode_MCLK_Pos         (31U)\r
-#define   USIC_CH_PCR_SSCMode_MCLK_Msk         (0x00000001U  << USIC_CH_PCR_SSCMode_MCLK_Pos)\r
-\r
-/* USIC_CH_PCR_IISMode  =  Protocol Control Register [IIS Mode]*/\r
-#define   USIC_CH_PCR_IISMode_WAGEN_Pos        (0U)\r
-#define   USIC_CH_PCR_IISMode_WAGEN_Msk        (0x00000001U  << USIC_CH_PCR_IISMode_WAGEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IISMode_DTEN_Pos         (1U)\r
-#define   USIC_CH_PCR_IISMode_DTEN_Msk         (0x00000001U  << USIC_CH_PCR_IISMode_DTEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IISMode_SELINV_Pos       (2U)\r
-#define   USIC_CH_PCR_IISMode_SELINV_Msk       (0x00000001U  << USIC_CH_PCR_IISMode_SELINV_Pos)\r
-\r
-#define   USIC_CH_PCR_IISMode_WAFEIEN_Pos      (4U)\r
-#define   USIC_CH_PCR_IISMode_WAFEIEN_Msk      (0x00000001U  << USIC_CH_PCR_IISMode_WAFEIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IISMode_WAREIEN_Pos      (5U)\r
-#define   USIC_CH_PCR_IISMode_WAREIEN_Msk      (0x00000001U  << USIC_CH_PCR_IISMode_WAREIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IISMode_ENDIEN_Pos       (6U)\r
-#define   USIC_CH_PCR_IISMode_ENDIEN_Msk       (0x00000001U  << USIC_CH_PCR_IISMode_ENDIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IISMode_DX2TIEN_Pos      (15U)\r
-#define   USIC_CH_PCR_IISMode_DX2TIEN_Msk      (0x00000001U  << USIC_CH_PCR_IISMode_DX2TIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IISMode_TDEL_Pos         (16U)\r
-#define   USIC_CH_PCR_IISMode_TDEL_Msk         (0x0000003FU  << USIC_CH_PCR_IISMode_TDEL_Pos)\r
-\r
-#define   USIC_CH_PCR_IISMode_MCLK_Pos         (31U)\r
-#define   USIC_CH_PCR_IISMode_MCLK_Msk         (0x00000001U  << USIC_CH_PCR_IISMode_MCLK_Pos)\r
-\r
-/* USIC_CH_PCR_IICMode  =  Protocol Control Register [IIC Mode]*/\r
-#define   USIC_CH_PCR_IICMode_SLAD_Pos         (0U)\r
-#define   USIC_CH_PCR_IICMode_SLAD_Msk         (0x0000FFFFU  << USIC_CH_PCR_IICMode_SLAD_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_ACK00_Pos        (16U)\r
-#define   USIC_CH_PCR_IICMode_ACK00_Msk        (0x00000001U  << USIC_CH_PCR_IICMode_ACK00_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_STIM_Pos         (17U)\r
-#define   USIC_CH_PCR_IICMode_STIM_Msk         (0x00000001U  << USIC_CH_PCR_IICMode_STIM_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_SCRIEN_Pos       (18U)\r
-#define   USIC_CH_PCR_IICMode_SCRIEN_Msk       (0x00000001U  << USIC_CH_PCR_IICMode_SCRIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_RSCRIEN_Pos      (19U)\r
-#define   USIC_CH_PCR_IICMode_RSCRIEN_Msk      (0x00000001U  << USIC_CH_PCR_IICMode_RSCRIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_PCRIEN_Pos       (20U)\r
-#define   USIC_CH_PCR_IICMode_PCRIEN_Msk       (0x00000001U  << USIC_CH_PCR_IICMode_PCRIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_NACKIEN_Pos      (21U)\r
-#define   USIC_CH_PCR_IICMode_NACKIEN_Msk      (0x00000001U  << USIC_CH_PCR_IICMode_NACKIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_ARLIEN_Pos       (22U)\r
-#define   USIC_CH_PCR_IICMode_ARLIEN_Msk       (0x00000001U  << USIC_CH_PCR_IICMode_ARLIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_SRRIEN_Pos       (23U)\r
-#define   USIC_CH_PCR_IICMode_SRRIEN_Msk       (0x00000001U  << USIC_CH_PCR_IICMode_SRRIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_ERRIEN_Pos       (24U)\r
-#define   USIC_CH_PCR_IICMode_ERRIEN_Msk       (0x00000001U  << USIC_CH_PCR_IICMode_ERRIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_SACKDIS_Pos      (25U)\r
-#define   USIC_CH_PCR_IICMode_SACKDIS_Msk      (0x00000001U  << USIC_CH_PCR_IICMode_SACKDIS_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_HDEL_Pos         (26U)\r
-#define   USIC_CH_PCR_IICMode_HDEL_Msk         (0x0000000FU  << USIC_CH_PCR_IICMode_HDEL_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_ACKIEN_Pos       (30U)\r
-#define   USIC_CH_PCR_IICMode_ACKIEN_Msk       (0x00000001U  << USIC_CH_PCR_IICMode_ACKIEN_Pos)\r
-\r
-#define   USIC_CH_PCR_IICMode_MCLK_Pos         (31U)\r
-#define   USIC_CH_PCR_IICMode_MCLK_Msk         (0x00000001U  << USIC_CH_PCR_IICMode_MCLK_Pos)\r
-\r
-/* USIC_CH_CCR  =  Channel Control Register*/\r
-#define   USIC_CH_CCR_MODE_Pos         (0U)\r
-#define   USIC_CH_CCR_MODE_Msk         (0x0000000FU  << USIC_CH_CCR_MODE_Pos)\r
-\r
-#define   USIC_CH_CCR_HPCEN_Pos        (6U)\r
-#define   USIC_CH_CCR_HPCEN_Msk        (0x00000003U  << USIC_CH_CCR_HPCEN_Pos)\r
-\r
-#define   USIC_CH_CCR_PM_Pos   (8U)\r
-#define   USIC_CH_CCR_PM_Msk   (0x00000003U  << USIC_CH_CCR_PM_Pos)\r
-\r
-#define   USIC_CH_CCR_RSIEN_Pos        (10U)\r
-#define   USIC_CH_CCR_RSIEN_Msk        (0x00000001U  << USIC_CH_CCR_RSIEN_Pos)\r
-\r
-#define   USIC_CH_CCR_DLIEN_Pos        (11U)\r
-#define   USIC_CH_CCR_DLIEN_Msk        (0x00000001U  << USIC_CH_CCR_DLIEN_Pos)\r
-\r
-#define   USIC_CH_CCR_TSIEN_Pos        (12U)\r
-#define   USIC_CH_CCR_TSIEN_Msk        (0x00000001U  << USIC_CH_CCR_TSIEN_Pos)\r
-\r
-#define   USIC_CH_CCR_TBIEN_Pos        (13U)\r
-#define   USIC_CH_CCR_TBIEN_Msk        (0x00000001U  << USIC_CH_CCR_TBIEN_Pos)\r
-\r
-#define   USIC_CH_CCR_RIEN_Pos         (14U)\r
-#define   USIC_CH_CCR_RIEN_Msk         (0x00000001U  << USIC_CH_CCR_RIEN_Pos)\r
-\r
-#define   USIC_CH_CCR_AIEN_Pos         (15U)\r
-#define   USIC_CH_CCR_AIEN_Msk         (0x00000001U  << USIC_CH_CCR_AIEN_Pos)\r
-\r
-#define   USIC_CH_CCR_BRGIEN_Pos       (16U)\r
-#define   USIC_CH_CCR_BRGIEN_Msk       (0x00000001U  << USIC_CH_CCR_BRGIEN_Pos)\r
-\r
-/* USIC_CH_CMTR  =  Capture Mode Timer Register*/\r
-#define   USIC_CH_CMTR_CTV_Pos         (0U)\r
-#define   USIC_CH_CMTR_CTV_Msk         (0x000003FFU  << USIC_CH_CMTR_CTV_Pos)\r
-\r
-/* USIC_CH_PSR  =  Protocol Status Register*/\r
-#define   USIC_CH_PSR_ST0_Pos          (0U)\r
-#define   USIC_CH_PSR_ST0_Msk          (0x00000001U  << USIC_CH_PSR_ST0_Pos)\r
-\r
-#define   USIC_CH_PSR_ST1_Pos          (1U)\r
-#define   USIC_CH_PSR_ST1_Msk          (0x00000001U  << USIC_CH_PSR_ST1_Pos)\r
-\r
-#define   USIC_CH_PSR_ST2_Pos          (2U)\r
-#define   USIC_CH_PSR_ST2_Msk          (0x00000001U  << USIC_CH_PSR_ST2_Pos)\r
-\r
-#define   USIC_CH_PSR_ST3_Pos          (3U)\r
-#define   USIC_CH_PSR_ST3_Msk          (0x00000001U  << USIC_CH_PSR_ST3_Pos)\r
-\r
-#define   USIC_CH_PSR_ST4_Pos          (4U)\r
-#define   USIC_CH_PSR_ST4_Msk          (0x00000001U  << USIC_CH_PSR_ST4_Pos)\r
-\r
-#define   USIC_CH_PSR_ST5_Pos          (5U)\r
-#define   USIC_CH_PSR_ST5_Msk          (0x00000001U  << USIC_CH_PSR_ST5_Pos)\r
-\r
-#define   USIC_CH_PSR_ST6_Pos          (6U)\r
-#define   USIC_CH_PSR_ST6_Msk          (0x00000001U  << USIC_CH_PSR_ST6_Pos)\r
-\r
-#define   USIC_CH_PSR_ST7_Pos          (7U)\r
-#define   USIC_CH_PSR_ST7_Msk          (0x00000001U  << USIC_CH_PSR_ST7_Pos)\r
-\r
-#define   USIC_CH_PSR_ST8_Pos          (8U)\r
-#define   USIC_CH_PSR_ST8_Msk          (0x00000001U  << USIC_CH_PSR_ST8_Pos)\r
-\r
-#define   USIC_CH_PSR_ST9_Pos          (9U)\r
-#define   USIC_CH_PSR_ST9_Msk          (0x00000001U  << USIC_CH_PSR_ST9_Pos)\r
-\r
-#define   USIC_CH_PSR_RSIF_Pos         (10U)\r
-#define   USIC_CH_PSR_RSIF_Msk         (0x00000001U  << USIC_CH_PSR_RSIF_Pos)\r
-\r
-#define   USIC_CH_PSR_DLIF_Pos         (11U)\r
-#define   USIC_CH_PSR_DLIF_Msk         (0x00000001U  << USIC_CH_PSR_DLIF_Pos)\r
-\r
-#define   USIC_CH_PSR_TSIF_Pos         (12U)\r
-#define   USIC_CH_PSR_TSIF_Msk         (0x00000001U  << USIC_CH_PSR_TSIF_Pos)\r
-\r
-#define   USIC_CH_PSR_TBIF_Pos         (13U)\r
-#define   USIC_CH_PSR_TBIF_Msk         (0x00000001U  << USIC_CH_PSR_TBIF_Pos)\r
-\r
-#define   USIC_CH_PSR_RIF_Pos          (14U)\r
-#define   USIC_CH_PSR_RIF_Msk          (0x00000001U  << USIC_CH_PSR_RIF_Pos)\r
-\r
-#define   USIC_CH_PSR_AIF_Pos          (15U)\r
-#define   USIC_CH_PSR_AIF_Msk          (0x00000001U  << USIC_CH_PSR_AIF_Pos)\r
-\r
-#define   USIC_CH_PSR_BRGIF_Pos        (16U)\r
-#define   USIC_CH_PSR_BRGIF_Msk        (0x00000001U  << USIC_CH_PSR_BRGIF_Pos)\r
-\r
-/* USIC_CH_PSR_ASCMode  =  Protocol Status Register [ASC Mode]*/\r
-#define   USIC_CH_PSR_ASCMode_TXIDLE_Pos       (0U)\r
-#define   USIC_CH_PSR_ASCMode_TXIDLE_Msk       (0x00000001U  << USIC_CH_PSR_ASCMode_TXIDLE_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_RXIDLE_Pos       (1U)\r
-#define   USIC_CH_PSR_ASCMode_RXIDLE_Msk       (0x00000001U  << USIC_CH_PSR_ASCMode_RXIDLE_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_SBD_Pos          (2U)\r
-#define   USIC_CH_PSR_ASCMode_SBD_Msk          (0x00000001U  << USIC_CH_PSR_ASCMode_SBD_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_COL_Pos          (3U)\r
-#define   USIC_CH_PSR_ASCMode_COL_Msk          (0x00000001U  << USIC_CH_PSR_ASCMode_COL_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_RNS_Pos          (4U)\r
-#define   USIC_CH_PSR_ASCMode_RNS_Msk          (0x00000001U  << USIC_CH_PSR_ASCMode_RNS_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_FER0_Pos         (5U)\r
-#define   USIC_CH_PSR_ASCMode_FER0_Msk         (0x00000001U  << USIC_CH_PSR_ASCMode_FER0_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_FER1_Pos         (6U)\r
-#define   USIC_CH_PSR_ASCMode_FER1_Msk         (0x00000001U  << USIC_CH_PSR_ASCMode_FER1_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_RFF_Pos          (7U)\r
-#define   USIC_CH_PSR_ASCMode_RFF_Msk          (0x00000001U  << USIC_CH_PSR_ASCMode_RFF_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_TFF_Pos          (8U)\r
-#define   USIC_CH_PSR_ASCMode_TFF_Msk          (0x00000001U  << USIC_CH_PSR_ASCMode_TFF_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_BUSY_Pos         (9U)\r
-#define   USIC_CH_PSR_ASCMode_BUSY_Msk         (0x00000001U  << USIC_CH_PSR_ASCMode_BUSY_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_RSIF_Pos         (10U)\r
-#define   USIC_CH_PSR_ASCMode_RSIF_Msk         (0x00000001U  << USIC_CH_PSR_ASCMode_RSIF_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_DLIF_Pos         (11U)\r
-#define   USIC_CH_PSR_ASCMode_DLIF_Msk         (0x00000001U  << USIC_CH_PSR_ASCMode_DLIF_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_TSIF_Pos         (12U)\r
-#define   USIC_CH_PSR_ASCMode_TSIF_Msk         (0x00000001U  << USIC_CH_PSR_ASCMode_TSIF_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_TBIF_Pos         (13U)\r
-#define   USIC_CH_PSR_ASCMode_TBIF_Msk         (0x00000001U  << USIC_CH_PSR_ASCMode_TBIF_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_RIF_Pos          (14U)\r
-#define   USIC_CH_PSR_ASCMode_RIF_Msk          (0x00000001U  << USIC_CH_PSR_ASCMode_RIF_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_AIF_Pos          (15U)\r
-#define   USIC_CH_PSR_ASCMode_AIF_Msk          (0x00000001U  << USIC_CH_PSR_ASCMode_AIF_Pos)\r
-\r
-#define   USIC_CH_PSR_ASCMode_BRGIF_Pos        (16U)\r
-#define   USIC_CH_PSR_ASCMode_BRGIF_Msk        (0x00000001U  << USIC_CH_PSR_ASCMode_BRGIF_Pos)\r
-\r
-/* USIC_CH_PSR_SSCMode  =  Protocol Status Register [SSC Mode]*/\r
-#define   USIC_CH_PSR_SSCMode_MSLS_Pos         (0U)\r
-#define   USIC_CH_PSR_SSCMode_MSLS_Msk         (0x00000001U  << USIC_CH_PSR_SSCMode_MSLS_Pos)\r
-\r
-#define   USIC_CH_PSR_SSCMode_DX2S_Pos         (1U)\r
-#define   USIC_CH_PSR_SSCMode_DX2S_Msk         (0x00000001U  << USIC_CH_PSR_SSCMode_DX2S_Pos)\r
-\r
-#define   USIC_CH_PSR_SSCMode_MSLSEV_Pos       (2U)\r
-#define   USIC_CH_PSR_SSCMode_MSLSEV_Msk       (0x00000001U  << USIC_CH_PSR_SSCMode_MSLSEV_Pos)\r
-\r
-#define   USIC_CH_PSR_SSCMode_DX2TEV_Pos       (3U)\r
-#define   USIC_CH_PSR_SSCMode_DX2TEV_Msk       (0x00000001U  << USIC_CH_PSR_SSCMode_DX2TEV_Pos)\r
-\r
-#define   USIC_CH_PSR_SSCMode_PARERR_Pos       (4U)\r
-#define   USIC_CH_PSR_SSCMode_PARERR_Msk       (0x00000001U  << USIC_CH_PSR_SSCMode_PARERR_Pos)\r
-\r
-#define   USIC_CH_PSR_SSCMode_RSIF_Pos         (10U)\r
-#define   USIC_CH_PSR_SSCMode_RSIF_Msk         (0x00000001U  << USIC_CH_PSR_SSCMode_RSIF_Pos)\r
-\r
-#define   USIC_CH_PSR_SSCMode_DLIF_Pos         (11U)\r
-#define   USIC_CH_PSR_SSCMode_DLIF_Msk         (0x00000001U  << USIC_CH_PSR_SSCMode_DLIF_Pos)\r
-\r
-#define   USIC_CH_PSR_SSCMode_TSIF_Pos         (12U)\r
-#define   USIC_CH_PSR_SSCMode_TSIF_Msk         (0x00000001U  << USIC_CH_PSR_SSCMode_TSIF_Pos)\r
-\r
-#define   USIC_CH_PSR_SSCMode_TBIF_Pos         (13U)\r
-#define   USIC_CH_PSR_SSCMode_TBIF_Msk         (0x00000001U  << USIC_CH_PSR_SSCMode_TBIF_Pos)\r
-\r
-#define   USIC_CH_PSR_SSCMode_RIF_Pos          (14U)\r
-#define   USIC_CH_PSR_SSCMode_RIF_Msk          (0x00000001U  << USIC_CH_PSR_SSCMode_RIF_Pos)\r
-\r
-#define   USIC_CH_PSR_SSCMode_AIF_Pos          (15U)\r
-#define   USIC_CH_PSR_SSCMode_AIF_Msk          (0x00000001U  << USIC_CH_PSR_SSCMode_AIF_Pos)\r
-\r
-#define   USIC_CH_PSR_SSCMode_BRGIF_Pos        (16U)\r
-#define   USIC_CH_PSR_SSCMode_BRGIF_Msk        (0x00000001U  << USIC_CH_PSR_SSCMode_BRGIF_Pos)\r
-\r
-/* USIC_CH_PSR_IISMode  =  Protocol Status Register [IIS Mode]*/\r
-#define   USIC_CH_PSR_IISMode_WA_Pos   (0U)\r
-#define   USIC_CH_PSR_IISMode_WA_Msk   (0x00000001U  << USIC_CH_PSR_IISMode_WA_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_DX2S_Pos         (1U)\r
-#define   USIC_CH_PSR_IISMode_DX2S_Msk         (0x00000001U  << USIC_CH_PSR_IISMode_DX2S_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_DX2TEV_Pos       (3U)\r
-#define   USIC_CH_PSR_IISMode_DX2TEV_Msk       (0x00000001U  << USIC_CH_PSR_IISMode_DX2TEV_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_WAFE_Pos         (4U)\r
-#define   USIC_CH_PSR_IISMode_WAFE_Msk         (0x00000001U  << USIC_CH_PSR_IISMode_WAFE_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_WARE_Pos         (5U)\r
-#define   USIC_CH_PSR_IISMode_WARE_Msk         (0x00000001U  << USIC_CH_PSR_IISMode_WARE_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_END_Pos          (6U)\r
-#define   USIC_CH_PSR_IISMode_END_Msk          (0x00000001U  << USIC_CH_PSR_IISMode_END_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_RSIF_Pos         (10U)\r
-#define   USIC_CH_PSR_IISMode_RSIF_Msk         (0x00000001U  << USIC_CH_PSR_IISMode_RSIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_DLIF_Pos         (11U)\r
-#define   USIC_CH_PSR_IISMode_DLIF_Msk         (0x00000001U  << USIC_CH_PSR_IISMode_DLIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_TSIF_Pos         (12U)\r
-#define   USIC_CH_PSR_IISMode_TSIF_Msk         (0x00000001U  << USIC_CH_PSR_IISMode_TSIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_TBIF_Pos         (13U)\r
-#define   USIC_CH_PSR_IISMode_TBIF_Msk         (0x00000001U  << USIC_CH_PSR_IISMode_TBIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_RIF_Pos          (14U)\r
-#define   USIC_CH_PSR_IISMode_RIF_Msk          (0x00000001U  << USIC_CH_PSR_IISMode_RIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_AIF_Pos          (15U)\r
-#define   USIC_CH_PSR_IISMode_AIF_Msk          (0x00000001U  << USIC_CH_PSR_IISMode_AIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IISMode_BRGIF_Pos        (16U)\r
-#define   USIC_CH_PSR_IISMode_BRGIF_Msk        (0x00000001U  << USIC_CH_PSR_IISMode_BRGIF_Pos)\r
-\r
-/* USIC_CH_PSR_IICMode  =  Protocol Status Register [IIC Mode]*/\r
-#define   USIC_CH_PSR_IICMode_SLSEL_Pos        (0U)\r
-#define   USIC_CH_PSR_IICMode_SLSEL_Msk        (0x00000001U  << USIC_CH_PSR_IICMode_SLSEL_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_WTDF_Pos         (1U)\r
-#define   USIC_CH_PSR_IICMode_WTDF_Msk         (0x00000001U  << USIC_CH_PSR_IICMode_WTDF_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_SCR_Pos          (2U)\r
-#define   USIC_CH_PSR_IICMode_SCR_Msk          (0x00000001U  << USIC_CH_PSR_IICMode_SCR_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_RSCR_Pos         (3U)\r
-#define   USIC_CH_PSR_IICMode_RSCR_Msk         (0x00000001U  << USIC_CH_PSR_IICMode_RSCR_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_PCR_Pos          (4U)\r
-#define   USIC_CH_PSR_IICMode_PCR_Msk          (0x00000001U  << USIC_CH_PSR_IICMode_PCR_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_NACK_Pos         (5U)\r
-#define   USIC_CH_PSR_IICMode_NACK_Msk         (0x00000001U  << USIC_CH_PSR_IICMode_NACK_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_ARL_Pos          (6U)\r
-#define   USIC_CH_PSR_IICMode_ARL_Msk          (0x00000001U  << USIC_CH_PSR_IICMode_ARL_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_SRR_Pos          (7U)\r
-#define   USIC_CH_PSR_IICMode_SRR_Msk          (0x00000001U  << USIC_CH_PSR_IICMode_SRR_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_ERR_Pos          (8U)\r
-#define   USIC_CH_PSR_IICMode_ERR_Msk          (0x00000001U  << USIC_CH_PSR_IICMode_ERR_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_ACK_Pos          (9U)\r
-#define   USIC_CH_PSR_IICMode_ACK_Msk          (0x00000001U  << USIC_CH_PSR_IICMode_ACK_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_RSIF_Pos         (10U)\r
-#define   USIC_CH_PSR_IICMode_RSIF_Msk         (0x00000001U  << USIC_CH_PSR_IICMode_RSIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_DLIF_Pos         (11U)\r
-#define   USIC_CH_PSR_IICMode_DLIF_Msk         (0x00000001U  << USIC_CH_PSR_IICMode_DLIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_TSIF_Pos         (12U)\r
-#define   USIC_CH_PSR_IICMode_TSIF_Msk         (0x00000001U  << USIC_CH_PSR_IICMode_TSIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_TBIF_Pos         (13U)\r
-#define   USIC_CH_PSR_IICMode_TBIF_Msk         (0x00000001U  << USIC_CH_PSR_IICMode_TBIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_RIF_Pos          (14U)\r
-#define   USIC_CH_PSR_IICMode_RIF_Msk          (0x00000001U  << USIC_CH_PSR_IICMode_RIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_AIF_Pos          (15U)\r
-#define   USIC_CH_PSR_IICMode_AIF_Msk          (0x00000001U  << USIC_CH_PSR_IICMode_AIF_Pos)\r
-\r
-#define   USIC_CH_PSR_IICMode_BRGIF_Pos        (16U)\r
-#define   USIC_CH_PSR_IICMode_BRGIF_Msk        (0x00000001U  << USIC_CH_PSR_IICMode_BRGIF_Pos)\r
-\r
-/* USIC_CH_PSCR  =  Protocol Status Clear Register*/\r
-#define   USIC_CH_PSCR_CST0_Pos        (0U)\r
-#define   USIC_CH_PSCR_CST0_Msk        (0x00000001U  << USIC_CH_PSCR_CST0_Pos)\r
-\r
-#define   USIC_CH_PSCR_CST1_Pos        (1U)\r
-#define   USIC_CH_PSCR_CST1_Msk        (0x00000001U  << USIC_CH_PSCR_CST1_Pos)\r
-\r
-#define   USIC_CH_PSCR_CST2_Pos        (2U)\r
-#define   USIC_CH_PSCR_CST2_Msk        (0x00000001U  << USIC_CH_PSCR_CST2_Pos)\r
-\r
-#define   USIC_CH_PSCR_CST3_Pos        (3U)\r
-#define   USIC_CH_PSCR_CST3_Msk        (0x00000001U  << USIC_CH_PSCR_CST3_Pos)\r
-\r
-#define   USIC_CH_PSCR_CST4_Pos        (4U)\r
-#define   USIC_CH_PSCR_CST4_Msk        (0x00000001U  << USIC_CH_PSCR_CST4_Pos)\r
-\r
-#define   USIC_CH_PSCR_CST5_Pos        (5U)\r
-#define   USIC_CH_PSCR_CST5_Msk        (0x00000001U  << USIC_CH_PSCR_CST5_Pos)\r
-\r
-#define   USIC_CH_PSCR_CST6_Pos        (6U)\r
-#define   USIC_CH_PSCR_CST6_Msk        (0x00000001U  << USIC_CH_PSCR_CST6_Pos)\r
-\r
-#define   USIC_CH_PSCR_CST7_Pos        (7U)\r
-#define   USIC_CH_PSCR_CST7_Msk        (0x00000001U  << USIC_CH_PSCR_CST7_Pos)\r
-\r
-#define   USIC_CH_PSCR_CST8_Pos        (8U)\r
-#define   USIC_CH_PSCR_CST8_Msk        (0x00000001U  << USIC_CH_PSCR_CST8_Pos)\r
-\r
-#define   USIC_CH_PSCR_CST9_Pos        (9U)\r
-#define   USIC_CH_PSCR_CST9_Msk        (0x00000001U  << USIC_CH_PSCR_CST9_Pos)\r
-\r
-#define   USIC_CH_PSCR_CRSIF_Pos       (10U)\r
-#define   USIC_CH_PSCR_CRSIF_Msk       (0x00000001U  << USIC_CH_PSCR_CRSIF_Pos)\r
-\r
-#define   USIC_CH_PSCR_CDLIF_Pos       (11U)\r
-#define   USIC_CH_PSCR_CDLIF_Msk       (0x00000001U  << USIC_CH_PSCR_CDLIF_Pos)\r
-\r
-#define   USIC_CH_PSCR_CTSIF_Pos       (12U)\r
-#define   USIC_CH_PSCR_CTSIF_Msk       (0x00000001U  << USIC_CH_PSCR_CTSIF_Pos)\r
-\r
-#define   USIC_CH_PSCR_CTBIF_Pos       (13U)\r
-#define   USIC_CH_PSCR_CTBIF_Msk       (0x00000001U  << USIC_CH_PSCR_CTBIF_Pos)\r
-\r
-#define   USIC_CH_PSCR_CRIF_Pos        (14U)\r
-#define   USIC_CH_PSCR_CRIF_Msk        (0x00000001U  << USIC_CH_PSCR_CRIF_Pos)\r
-\r
-#define   USIC_CH_PSCR_CAIF_Pos        (15U)\r
-#define   USIC_CH_PSCR_CAIF_Msk        (0x00000001U  << USIC_CH_PSCR_CAIF_Pos)\r
-\r
-#define   USIC_CH_PSCR_CBRGIF_Pos      (16U)\r
-#define   USIC_CH_PSCR_CBRGIF_Msk      (0x00000001U  << USIC_CH_PSCR_CBRGIF_Pos)\r
-\r
-/* USIC_CH_RBUFSR  =  Receiver Buffer Status Register*/\r
-#define   USIC_CH_RBUFSR_WLEN_Pos      (0U)\r
-#define   USIC_CH_RBUFSR_WLEN_Msk      (0x0000000FU  << USIC_CH_RBUFSR_WLEN_Pos)\r
-\r
-#define   USIC_CH_RBUFSR_SOF_Pos       (6U)\r
-#define   USIC_CH_RBUFSR_SOF_Msk       (0x00000001U  << USIC_CH_RBUFSR_SOF_Pos)\r
-\r
-#define   USIC_CH_RBUFSR_PAR_Pos       (8U)\r
-#define   USIC_CH_RBUFSR_PAR_Msk       (0x00000001U  << USIC_CH_RBUFSR_PAR_Pos)\r
-\r
-#define   USIC_CH_RBUFSR_PERR_Pos      (9U)\r
-#define   USIC_CH_RBUFSR_PERR_Msk      (0x00000001U  << USIC_CH_RBUFSR_PERR_Pos)\r
-\r
-#define   USIC_CH_RBUFSR_RDV0_Pos      (13U)\r
-#define   USIC_CH_RBUFSR_RDV0_Msk      (0x00000001U  << USIC_CH_RBUFSR_RDV0_Pos)\r
-\r
-#define   USIC_CH_RBUFSR_RDV1_Pos      (14U)\r
-#define   USIC_CH_RBUFSR_RDV1_Msk      (0x00000001U  << USIC_CH_RBUFSR_RDV1_Pos)\r
-\r
-#define   USIC_CH_RBUFSR_DS_Pos        (15U)\r
-#define   USIC_CH_RBUFSR_DS_Msk        (0x00000001U  << USIC_CH_RBUFSR_DS_Pos)\r
-\r
-/* USIC_CH_RBUF  =  Receiver Buffer Register*/\r
-#define   USIC_CH_RBUF_DSR_Pos         (0U)\r
-#define   USIC_CH_RBUF_DSR_Msk         (0x0000FFFFU  << USIC_CH_RBUF_DSR_Pos)\r
-\r
-/* USIC_CH_RBUFD  =  Receiver Buffer Register for Debugger*/\r
-#define   USIC_CH_RBUFD_DSR_Pos        (0U)\r
-#define   USIC_CH_RBUFD_DSR_Msk        (0x0000FFFFU  << USIC_CH_RBUFD_DSR_Pos)\r
-\r
-/* USIC_CH_RBUF0  =  Receiver Buffer Register 0*/\r
-#define   USIC_CH_RBUF0_DSR0_Pos       (0U)\r
-#define   USIC_CH_RBUF0_DSR0_Msk       (0x0000FFFFU  << USIC_CH_RBUF0_DSR0_Pos)\r
-\r
-/* USIC_CH_RBUF1  =  Receiver Buffer Register 1*/\r
-#define   USIC_CH_RBUF1_DSR1_Pos       (0U)\r
-#define   USIC_CH_RBUF1_DSR1_Msk       (0x0000FFFFU  << USIC_CH_RBUF1_DSR1_Pos)\r
-\r
-/* USIC_CH_RBUF01SR  =  Receiver Buffer 01 Status Register*/\r
-#define   USIC_CH_RBUF01SR_WLEN0_Pos   (0U)\r
-#define   USIC_CH_RBUF01SR_WLEN0_Msk   (0x0000000FU  << USIC_CH_RBUF01SR_WLEN0_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_SOF0_Pos    (6U)\r
-#define   USIC_CH_RBUF01SR_SOF0_Msk    (0x00000001U  << USIC_CH_RBUF01SR_SOF0_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_PAR0_Pos    (8U)\r
-#define   USIC_CH_RBUF01SR_PAR0_Msk    (0x00000001U  << USIC_CH_RBUF01SR_PAR0_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_PERR0_Pos   (9U)\r
-#define   USIC_CH_RBUF01SR_PERR0_Msk   (0x00000001U  << USIC_CH_RBUF01SR_PERR0_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_RDV00_Pos   (13U)\r
-#define   USIC_CH_RBUF01SR_RDV00_Msk   (0x00000001U  << USIC_CH_RBUF01SR_RDV00_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_RDV01_Pos   (14U)\r
-#define   USIC_CH_RBUF01SR_RDV01_Msk   (0x00000001U  << USIC_CH_RBUF01SR_RDV01_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_DS0_Pos     (15U)\r
-#define   USIC_CH_RBUF01SR_DS0_Msk     (0x00000001U  << USIC_CH_RBUF01SR_DS0_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_WLEN1_Pos   (16U)\r
-#define   USIC_CH_RBUF01SR_WLEN1_Msk   (0x0000000FU  << USIC_CH_RBUF01SR_WLEN1_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_SOF1_Pos    (22U)\r
-#define   USIC_CH_RBUF01SR_SOF1_Msk    (0x00000001U  << USIC_CH_RBUF01SR_SOF1_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_PAR1_Pos    (24U)\r
-#define   USIC_CH_RBUF01SR_PAR1_Msk    (0x00000001U  << USIC_CH_RBUF01SR_PAR1_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_PERR1_Pos   (25U)\r
-#define   USIC_CH_RBUF01SR_PERR1_Msk   (0x00000001U  << USIC_CH_RBUF01SR_PERR1_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_RDV10_Pos   (29U)\r
-#define   USIC_CH_RBUF01SR_RDV10_Msk   (0x00000001U  << USIC_CH_RBUF01SR_RDV10_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_RDV11_Pos   (30U)\r
-#define   USIC_CH_RBUF01SR_RDV11_Msk   (0x00000001U  << USIC_CH_RBUF01SR_RDV11_Pos)\r
-\r
-#define   USIC_CH_RBUF01SR_DS1_Pos     (31U)\r
-#define   USIC_CH_RBUF01SR_DS1_Msk     (0x00000001U  << USIC_CH_RBUF01SR_DS1_Pos)\r
-\r
-/* USIC_CH_FMR  =  Flag Modification Register*/\r
-#define   USIC_CH_FMR_MTDV_Pos         (0U)\r
-#define   USIC_CH_FMR_MTDV_Msk         (0x00000003U  << USIC_CH_FMR_MTDV_Pos)\r
-\r
-#define   USIC_CH_FMR_ATVC_Pos         (4U)\r
-#define   USIC_CH_FMR_ATVC_Msk         (0x00000001U  << USIC_CH_FMR_ATVC_Pos)\r
-\r
-#define   USIC_CH_FMR_CRDV0_Pos        (14U)\r
-#define   USIC_CH_FMR_CRDV0_Msk        (0x00000001U  << USIC_CH_FMR_CRDV0_Pos)\r
-\r
-#define   USIC_CH_FMR_CRDV1_Pos        (15U)\r
-#define   USIC_CH_FMR_CRDV1_Msk        (0x00000001U  << USIC_CH_FMR_CRDV1_Pos)\r
-\r
-#define   USIC_CH_FMR_SIO0_Pos         (16U)\r
-#define   USIC_CH_FMR_SIO0_Msk         (0x00000001U  << USIC_CH_FMR_SIO0_Pos)\r
-\r
-#define   USIC_CH_FMR_SIO1_Pos         (17U)\r
-#define   USIC_CH_FMR_SIO1_Msk         (0x00000001U  << USIC_CH_FMR_SIO1_Pos)\r
-\r
-#define   USIC_CH_FMR_SIO2_Pos         (18U)\r
-#define   USIC_CH_FMR_SIO2_Msk         (0x00000001U  << USIC_CH_FMR_SIO2_Pos)\r
-\r
-#define   USIC_CH_FMR_SIO3_Pos         (19U)\r
-#define   USIC_CH_FMR_SIO3_Msk         (0x00000001U  << USIC_CH_FMR_SIO3_Pos)\r
-\r
-#define   USIC_CH_FMR_SIO4_Pos         (20U)\r
-#define   USIC_CH_FMR_SIO4_Msk         (0x00000001U  << USIC_CH_FMR_SIO4_Pos)\r
-\r
-#define   USIC_CH_FMR_SIO5_Pos         (21U)\r
-#define   USIC_CH_FMR_SIO5_Msk         (0x00000001U  << USIC_CH_FMR_SIO5_Pos)\r
-\r
-/* USIC_CH_TBUFxx  =  Transmit Buffer Input Location 00*/\r
-#define   USIC_CH_TBUF_TDATA_Pos       (0U)\r
-#define   USIC_CH_TBUF_TDATA_Msk       (0x0000FFFFU  << USIC_CH_TBUF_TDATA_Pos)\r
-\r
-/* USIC_CH_BYP  =  Bypass Data Register*/\r
-#define   USIC_CH_BYP_BDATA_Pos        (0U)\r
-#define   USIC_CH_BYP_BDATA_Msk        (0x0000FFFFU  << USIC_CH_BYP_BDATA_Pos)\r
-\r
-/* USIC_CH_BYPCR  =  Bypass Control Register*/\r
-#define   USIC_CH_BYPCR_BWLE_Pos       (0U)\r
-#define   USIC_CH_BYPCR_BWLE_Msk       (0x0000000FU  << USIC_CH_BYPCR_BWLE_Pos)\r
-\r
-#define   USIC_CH_BYPCR_BDSSM_Pos      (8U)\r
-#define   USIC_CH_BYPCR_BDSSM_Msk      (0x00000001U  << USIC_CH_BYPCR_BDSSM_Pos)\r
-\r
-#define   USIC_CH_BYPCR_BDEN_Pos       (10U)\r
-#define   USIC_CH_BYPCR_BDEN_Msk       (0x00000003U  << USIC_CH_BYPCR_BDEN_Pos)\r
-\r
-#define   USIC_CH_BYPCR_BDVTR_Pos      (12U)\r
-#define   USIC_CH_BYPCR_BDVTR_Msk      (0x00000001U  << USIC_CH_BYPCR_BDVTR_Pos)\r
-\r
-#define   USIC_CH_BYPCR_BPRIO_Pos      (13U)\r
-#define   USIC_CH_BYPCR_BPRIO_Msk      (0x00000001U  << USIC_CH_BYPCR_BPRIO_Pos)\r
-\r
-#define   USIC_CH_BYPCR_BDV_Pos        (15U)\r
-#define   USIC_CH_BYPCR_BDV_Msk        (0x00000001U  << USIC_CH_BYPCR_BDV_Pos)\r
-\r
-#define   USIC_CH_BYPCR_BSELO_Pos      (16U)\r
-#define   USIC_CH_BYPCR_BSELO_Msk      (0x0000001FU  << USIC_CH_BYPCR_BSELO_Pos)\r
-\r
-#define   USIC_CH_BYPCR_BHPC_Pos       (21U)\r
-#define   USIC_CH_BYPCR_BHPC_Msk       (0x00000007U  << USIC_CH_BYPCR_BHPC_Pos)\r
-\r
-/* USIC_CH_TBCTR  =  Transmitter Buffer Control Register*/\r
-#define   USIC_CH_TBCTR_DPTR_Pos       (0U)\r
-#define   USIC_CH_TBCTR_DPTR_Msk       (0x0000003FU  << USIC_CH_TBCTR_DPTR_Pos)\r
-\r
-#define   USIC_CH_TBCTR_LIMIT_Pos      (8U)\r
-#define   USIC_CH_TBCTR_LIMIT_Msk      (0x0000003FU  << USIC_CH_TBCTR_LIMIT_Pos)\r
-\r
-#define   USIC_CH_TBCTR_STBTM_Pos      (14U)\r
-#define   USIC_CH_TBCTR_STBTM_Msk      (0x00000001U  << USIC_CH_TBCTR_STBTM_Pos)\r
-\r
-#define   USIC_CH_TBCTR_STBTEN_Pos     (15U)\r
-#define   USIC_CH_TBCTR_STBTEN_Msk     (0x00000001U  << USIC_CH_TBCTR_STBTEN_Pos)\r
-\r
-#define   USIC_CH_TBCTR_STBINP_Pos     (16U)\r
-#define   USIC_CH_TBCTR_STBINP_Msk     (0x00000007U  << USIC_CH_TBCTR_STBINP_Pos)\r
-\r
-#define   USIC_CH_TBCTR_ATBINP_Pos     (19U)\r
-#define   USIC_CH_TBCTR_ATBINP_Msk     (0x00000007U  << USIC_CH_TBCTR_ATBINP_Pos)\r
-\r
-#define   USIC_CH_TBCTR_SIZE_Pos       (24U)\r
-#define   USIC_CH_TBCTR_SIZE_Msk       (0x00000007U  << USIC_CH_TBCTR_SIZE_Pos)\r
-\r
-#define   USIC_CH_TBCTR_LOF_Pos        (28U)\r
-#define   USIC_CH_TBCTR_LOF_Msk        (0x00000001U  << USIC_CH_TBCTR_LOF_Pos)\r
-\r
-#define   USIC_CH_TBCTR_STBIEN_Pos     (30U)\r
-#define   USIC_CH_TBCTR_STBIEN_Msk     (0x00000001U  << USIC_CH_TBCTR_STBIEN_Pos)\r
-\r
-#define   USIC_CH_TBCTR_TBERIEN_Pos    (31U)\r
-#define   USIC_CH_TBCTR_TBERIEN_Msk    (0x00000001U  << USIC_CH_TBCTR_TBERIEN_Pos)\r
-\r
-/* USIC_CH_RBCTR  =  Receiver Buffer Control Register*/\r
-#define   USIC_CH_RBCTR_DPTR_Pos       (0U)\r
-#define   USIC_CH_RBCTR_DPTR_Msk       (0x0000003FU  << USIC_CH_RBCTR_DPTR_Pos)\r
-\r
-#define   USIC_CH_RBCTR_LIMIT_Pos      (8U)\r
-#define   USIC_CH_RBCTR_LIMIT_Msk      (0x0000003FU  << USIC_CH_RBCTR_LIMIT_Pos)\r
-\r
-#define   USIC_CH_RBCTR_SRBTM_Pos      (14U)\r
-#define   USIC_CH_RBCTR_SRBTM_Msk      (0x00000001U  << USIC_CH_RBCTR_SRBTM_Pos)\r
-\r
-#define   USIC_CH_RBCTR_SRBTEN_Pos     (15U)\r
-#define   USIC_CH_RBCTR_SRBTEN_Msk     (0x00000001U  << USIC_CH_RBCTR_SRBTEN_Pos)\r
-\r
-#define   USIC_CH_RBCTR_SRBINP_Pos     (16U)\r
-#define   USIC_CH_RBCTR_SRBINP_Msk     (0x00000007U  << USIC_CH_RBCTR_SRBINP_Pos)\r
-\r
-#define   USIC_CH_RBCTR_ARBINP_Pos     (19U)\r
-#define   USIC_CH_RBCTR_ARBINP_Msk     (0x00000007U  << USIC_CH_RBCTR_ARBINP_Pos)\r
-\r
-#define   USIC_CH_RBCTR_RCIM_Pos       (22U)\r
-#define   USIC_CH_RBCTR_RCIM_Msk       (0x00000003U  << USIC_CH_RBCTR_RCIM_Pos)\r
-\r
-#define   USIC_CH_RBCTR_SIZE_Pos       (24U)\r
-#define   USIC_CH_RBCTR_SIZE_Msk       (0x00000007U  << USIC_CH_RBCTR_SIZE_Pos)\r
-\r
-#define   USIC_CH_RBCTR_RNM_Pos        (27U)\r
-#define   USIC_CH_RBCTR_RNM_Msk        (0x00000001U  << USIC_CH_RBCTR_RNM_Pos)\r
-\r
-#define   USIC_CH_RBCTR_LOF_Pos        (28U)\r
-#define   USIC_CH_RBCTR_LOF_Msk        (0x00000001U  << USIC_CH_RBCTR_LOF_Pos)\r
-\r
-#define   USIC_CH_RBCTR_ARBIEN_Pos     (29U)\r
-#define   USIC_CH_RBCTR_ARBIEN_Msk     (0x00000001U  << USIC_CH_RBCTR_ARBIEN_Pos)\r
-\r
-#define   USIC_CH_RBCTR_SRBIEN_Pos     (30U)\r
-#define   USIC_CH_RBCTR_SRBIEN_Msk     (0x00000001U  << USIC_CH_RBCTR_SRBIEN_Pos)\r
-\r
-#define   USIC_CH_RBCTR_RBERIEN_Pos    (31U)\r
-#define   USIC_CH_RBCTR_RBERIEN_Msk    (0x00000001U  << USIC_CH_RBCTR_RBERIEN_Pos)\r
-\r
-/* USIC_CH_TRBPTR  =  Transmit/Receive Buffer Pointer Register*/\r
-#define   USIC_CH_TRBPTR_TDIPTR_Pos    (0U)\r
-#define   USIC_CH_TRBPTR_TDIPTR_Msk    (0x0000003FU  << USIC_CH_TRBPTR_TDIPTR_Pos)\r
-\r
-#define   USIC_CH_TRBPTR_TDOPTR_Pos    (8U)\r
-#define   USIC_CH_TRBPTR_TDOPTR_Msk    (0x0000003FU  << USIC_CH_TRBPTR_TDOPTR_Pos)\r
-\r
-#define   USIC_CH_TRBPTR_RDIPTR_Pos    (16U)\r
-#define   USIC_CH_TRBPTR_RDIPTR_Msk    (0x0000003FU  << USIC_CH_TRBPTR_RDIPTR_Pos)\r
-\r
-#define   USIC_CH_TRBPTR_RDOPTR_Pos    (24U)\r
-#define   USIC_CH_TRBPTR_RDOPTR_Msk    (0x0000003FU  << USIC_CH_TRBPTR_RDOPTR_Pos)\r
-\r
-/* USIC_CH_TRBSR  =  Transmit/Receive Buffer Status Register*/\r
-#define   USIC_CH_TRBSR_SRBI_Pos       (0U)\r
-#define   USIC_CH_TRBSR_SRBI_Msk       (0x00000001U  << USIC_CH_TRBSR_SRBI_Pos)\r
-\r
-#define   USIC_CH_TRBSR_RBERI_Pos      (1U)\r
-#define   USIC_CH_TRBSR_RBERI_Msk      (0x00000001U  << USIC_CH_TRBSR_RBERI_Pos)\r
-\r
-#define   USIC_CH_TRBSR_ARBI_Pos       (2U)\r
-#define   USIC_CH_TRBSR_ARBI_Msk       (0x00000001U  << USIC_CH_TRBSR_ARBI_Pos)\r
-\r
-#define   USIC_CH_TRBSR_REMPTY_Pos     (3U)\r
-#define   USIC_CH_TRBSR_REMPTY_Msk     (0x00000001U  << USIC_CH_TRBSR_REMPTY_Pos)\r
-\r
-#define   USIC_CH_TRBSR_RFULL_Pos      (4U)\r
-#define   USIC_CH_TRBSR_RFULL_Msk      (0x00000001U  << USIC_CH_TRBSR_RFULL_Pos)\r
-\r
-#define   USIC_CH_TRBSR_RBUS_Pos       (5U)\r
-#define   USIC_CH_TRBSR_RBUS_Msk       (0x00000001U  << USIC_CH_TRBSR_RBUS_Pos)\r
-\r
-#define   USIC_CH_TRBSR_SRBT_Pos       (6U)\r
-#define   USIC_CH_TRBSR_SRBT_Msk       (0x00000001U  << USIC_CH_TRBSR_SRBT_Pos)\r
-\r
-#define   USIC_CH_TRBSR_STBI_Pos       (8U)\r
-#define   USIC_CH_TRBSR_STBI_Msk       (0x00000001U  << USIC_CH_TRBSR_STBI_Pos)\r
-\r
-#define   USIC_CH_TRBSR_TBERI_Pos      (9U)\r
-#define   USIC_CH_TRBSR_TBERI_Msk      (0x00000001U  << USIC_CH_TRBSR_TBERI_Pos)\r
-\r
-#define   USIC_CH_TRBSR_TEMPTY_Pos     (11U)\r
-#define   USIC_CH_TRBSR_TEMPTY_Msk     (0x00000001U  << USIC_CH_TRBSR_TEMPTY_Pos)\r
-\r
-#define   USIC_CH_TRBSR_TFULL_Pos      (12U)\r
-#define   USIC_CH_TRBSR_TFULL_Msk      (0x00000001U  << USIC_CH_TRBSR_TFULL_Pos)\r
-\r
-#define   USIC_CH_TRBSR_TBUS_Pos       (13U)\r
-#define   USIC_CH_TRBSR_TBUS_Msk       (0x00000001U  << USIC_CH_TRBSR_TBUS_Pos)\r
-\r
-#define   USIC_CH_TRBSR_STBT_Pos       (14U)\r
-#define   USIC_CH_TRBSR_STBT_Msk       (0x00000001U  << USIC_CH_TRBSR_STBT_Pos)\r
-\r
-#define   USIC_CH_TRBSR_RBFLVL_Pos     (16U)\r
-#define   USIC_CH_TRBSR_RBFLVL_Msk     (0x0000007FU  << USIC_CH_TRBSR_RBFLVL_Pos)\r
-\r
-#define   USIC_CH_TRBSR_TBFLVL_Pos     (24U)\r
-#define   USIC_CH_TRBSR_TBFLVL_Msk     (0x0000007FU  << USIC_CH_TRBSR_TBFLVL_Pos)\r
-\r
-/* USIC_CH_TRBSCR  =  Transmit/Receive Buffer Status Clear Register*/\r
-#define   USIC_CH_TRBSCR_CSRBI_Pos     (0U)\r
-#define   USIC_CH_TRBSCR_CSRBI_Msk     (0x00000001U  << USIC_CH_TRBSCR_CSRBI_Pos)\r
-\r
-#define   USIC_CH_TRBSCR_CRBERI_Pos    (1U)\r
-#define   USIC_CH_TRBSCR_CRBERI_Msk    (0x00000001U  << USIC_CH_TRBSCR_CRBERI_Pos)\r
-\r
-#define   USIC_CH_TRBSCR_CARBI_Pos     (2U)\r
-#define   USIC_CH_TRBSCR_CARBI_Msk     (0x00000001U  << USIC_CH_TRBSCR_CARBI_Pos)\r
-\r
-#define   USIC_CH_TRBSCR_CSTBI_Pos     (8U)\r
-#define   USIC_CH_TRBSCR_CSTBI_Msk     (0x00000001U  << USIC_CH_TRBSCR_CSTBI_Pos)\r
-\r
-#define   USIC_CH_TRBSCR_CTBERI_Pos    (9U)\r
-#define   USIC_CH_TRBSCR_CTBERI_Msk    (0x00000001U  << USIC_CH_TRBSCR_CTBERI_Pos)\r
-\r
-#define   USIC_CH_TRBSCR_CBDV_Pos      (10U)\r
-#define   USIC_CH_TRBSCR_CBDV_Msk      (0x00000001U  << USIC_CH_TRBSCR_CBDV_Pos)\r
-\r
-#define   USIC_CH_TRBSCR_FLUSHRB_Pos   (14U)\r
-#define   USIC_CH_TRBSCR_FLUSHRB_Msk   (0x00000001U  << USIC_CH_TRBSCR_FLUSHRB_Pos)\r
-\r
-#define   USIC_CH_TRBSCR_FLUSHTB_Pos   (15U)\r
-#define   USIC_CH_TRBSCR_FLUSHTB_Msk   (0x00000001U  << USIC_CH_TRBSCR_FLUSHTB_Pos)\r
-\r
-/* USIC_CH_OUTR  =  Receiver Buffer Output Register*/\r
-#define   USIC_CH_OUTR_DSR_Pos         (0U)\r
-#define   USIC_CH_OUTR_DSR_Msk         (0x0000FFFFU  << USIC_CH_OUTR_DSR_Pos)\r
-\r
-#define   USIC_CH_OUTR_RCI_Pos         (16U)\r
-#define   USIC_CH_OUTR_RCI_Msk         (0x0000001FU  << USIC_CH_OUTR_RCI_Pos)\r
-\r
-/* USIC_CH_OUTDR  =  Receiver Buffer Output Register L for Debugger*/\r
-#define   USIC_CH_OUTDR_DSR_Pos        (0U)\r
-#define   USIC_CH_OUTDR_DSR_Msk        (0x0000FFFFU  << USIC_CH_OUTDR_DSR_Pos)\r
-\r
-#define   USIC_CH_OUTDR_RCI_Pos        (16U)\r
-#define   USIC_CH_OUTDR_RCI_Msk        (0x0000001FU  << USIC_CH_OUTDR_RCI_Pos)\r
-\r
-/* USIC_CH_INxx  =  Transmit FIFO Buffer Input Location 00*/\r
-#define   USIC_CH_IN_TDATA_Pos         (0U)\r
-#define   USIC_CH_IN_TDATA_Msk         (0x0000FFFFU  << USIC_CH_IN_TDATA_Pos)\r
-\r
-\r
-\r
-/***   VADC Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* VADC_G_ARBCFG  =  Arbitration Configuration Register, Group 0*/\r
-#define   VADC_G_ARBCFG_ANONC_Pos      (0U)\r
-#define   VADC_G_ARBCFG_ANONC_Msk      (0x00000003U  << VADC_G_ARBCFG_ANONC_Pos)\r
-\r
-#define   VADC_G_ARBCFG_ARBRND_Pos     (4U)\r
-#define   VADC_G_ARBCFG_ARBRND_Msk     (0x00000003U  << VADC_G_ARBCFG_ARBRND_Pos)\r
-\r
-#define   VADC_G_ARBCFG_ARBM_Pos       (7U)\r
-#define   VADC_G_ARBCFG_ARBM_Msk       (0x00000001U  << VADC_G_ARBCFG_ARBM_Pos)\r
-\r
-#define   VADC_G_ARBCFG_ANONS_Pos      (16U)\r
-#define   VADC_G_ARBCFG_ANONS_Msk      (0x00000003U  << VADC_G_ARBCFG_ANONS_Pos)\r
-\r
-#define   VADC_G_ARBCFG_CAL_Pos        (28U)\r
-#define   VADC_G_ARBCFG_CAL_Msk        (0x00000001U  << VADC_G_ARBCFG_CAL_Pos)\r
-\r
-#define   VADC_G_ARBCFG_BUSY_Pos       (30U)\r
-#define   VADC_G_ARBCFG_BUSY_Msk       (0x00000001U  << VADC_G_ARBCFG_BUSY_Pos)\r
-\r
-#define   VADC_G_ARBCFG_SAMPLE_Pos     (31U)\r
-#define   VADC_G_ARBCFG_SAMPLE_Msk     (0x00000001U  << VADC_G_ARBCFG_SAMPLE_Pos)\r
-\r
-/* VADC_G_ARBPR  =  Arbitration Priority Register, Group 0*/\r
-#define   VADC_G_ARBPR_PRIO0_Pos       (0U)\r
-#define   VADC_G_ARBPR_PRIO0_Msk       (0x00000003U  << VADC_G_ARBPR_PRIO0_Pos)\r
-\r
-#define   VADC_G_ARBPR_PRIO1_Pos       (4U)\r
-#define   VADC_G_ARBPR_PRIO1_Msk       (0x00000003U  << VADC_G_ARBPR_PRIO1_Pos)\r
-\r
-#define   VADC_G_ARBPR_PRIO2_Pos       (8U)\r
-#define   VADC_G_ARBPR_PRIO2_Msk       (0x00000003U  << VADC_G_ARBPR_PRIO2_Pos)\r
-\r
-#define   VADC_G_ARBPR_CSM0_Pos        (3U)\r
-#define   VADC_G_ARBPR_CSM0_Msk        (0x00000001U  << VADC_G_ARBPR_CSM0_Pos)\r
-\r
-#define   VADC_G_ARBPR_CSM1_Pos        (7U)\r
-#define   VADC_G_ARBPR_CSM1_Msk        (0x00000001U  << VADC_G_ARBPR_CSM1_Pos)\r
-\r
-#define   VADC_G_ARBPR_CSM2_Pos        (11U)\r
-#define   VADC_G_ARBPR_CSM2_Msk        (0x00000001U  << VADC_G_ARBPR_CSM2_Pos)\r
-\r
-#define   VADC_G_ARBPR_ASEN0_Pos       (24U)\r
-#define   VADC_G_ARBPR_ASEN0_Msk       (0x00000001U  << VADC_G_ARBPR_ASEN0_Pos)\r
-\r
-#define   VADC_G_ARBPR_ASEN1_Pos       (25U)\r
-#define   VADC_G_ARBPR_ASEN1_Msk       (0x00000001U  << VADC_G_ARBPR_ASEN1_Pos)\r
-\r
-#define   VADC_G_ARBPR_ASEN2_Pos       (26U)\r
-#define   VADC_G_ARBPR_ASEN2_Msk       (0x00000001U  << VADC_G_ARBPR_ASEN2_Pos)\r
-\r
-/* VADC_G_CHASS  =  Channel Assignment Register, Group 0*/\r
-#define   VADC_G_CHASS_ASSCH0_Pos      (0U)\r
-#define   VADC_G_CHASS_ASSCH0_Msk      (0x00000001U  << VADC_G_CHASS_ASSCH0_Pos)\r
-\r
-#define   VADC_G_CHASS_ASSCH1_Pos      (1U)\r
-#define   VADC_G_CHASS_ASSCH1_Msk      (0x00000001U  << VADC_G_CHASS_ASSCH1_Pos)\r
-\r
-#define   VADC_G_CHASS_ASSCH2_Pos      (2U)\r
-#define   VADC_G_CHASS_ASSCH2_Msk      (0x00000001U  << VADC_G_CHASS_ASSCH2_Pos)\r
-\r
-#define   VADC_G_CHASS_ASSCH3_Pos      (3U)\r
-#define   VADC_G_CHASS_ASSCH3_Msk      (0x00000001U  << VADC_G_CHASS_ASSCH3_Pos)\r
-\r
-#define   VADC_G_CHASS_ASSCH4_Pos      (4U)\r
-#define   VADC_G_CHASS_ASSCH4_Msk      (0x00000001U  << VADC_G_CHASS_ASSCH4_Pos)\r
-\r
-#define   VADC_G_CHASS_ASSCH5_Pos      (5U)\r
-#define   VADC_G_CHASS_ASSCH5_Msk      (0x00000001U  << VADC_G_CHASS_ASSCH5_Pos)\r
-\r
-#define   VADC_G_CHASS_ASSCH6_Pos      (6U)\r
-#define   VADC_G_CHASS_ASSCH6_Msk      (0x00000001U  << VADC_G_CHASS_ASSCH6_Pos)\r
-\r
-#define   VADC_G_CHASS_ASSCH7_Pos      (7U)\r
-#define   VADC_G_CHASS_ASSCH7_Msk      (0x00000001U  << VADC_G_CHASS_ASSCH7_Pos)\r
-\r
-/* VADC_G_ICLASS0  =  Input Class Register 0, Group 0*/\r
-#define   VADC_G_ICLASS_STCS_Pos       (0U)\r
-#define   VADC_G_ICLASS_STCS_Msk       (0x0000001FU  << VADC_G_ICLASS_STCS_Pos)\r
-\r
-#define   VADC_G_ICLASS_CMS_Pos        (8U)\r
-#define   VADC_G_ICLASS_CMS_Msk        (0x00000007U  << VADC_G_ICLASS_CMS_Pos)\r
-\r
-#define   VADC_G_ICLASS_STCE_Pos       (16U)\r
-#define   VADC_G_ICLASS_STCE_Msk       (0x0000001FU  << VADC_G_ICLASS_STCE_Pos)\r
-\r
-#define   VADC_G_ICLASS_CME_Pos        (24U)\r
-#define   VADC_G_ICLASS_CME_Msk        (0x00000007U  << VADC_G_ICLASS_CME_Pos)\r
-\r
-/* VADC_G_ALIAS  =  Alias Register, Group 0*/\r
-#define   VADC_G_ALIAS_ALIAS0_Pos      (0U)\r
-#define   VADC_G_ALIAS_ALIAS0_Msk      (0x0000001FU  << VADC_G_ALIAS_ALIAS0_Pos)\r
-\r
-#define   VADC_G_ALIAS_ALIAS1_Pos      (8U)\r
-#define   VADC_G_ALIAS_ALIAS1_Msk      (0x0000001FU  << VADC_G_ALIAS_ALIAS1_Pos)\r
-\r
-/* VADC_G_BOUND  =  Boundary Select Register, Group 0*/\r
-#define   VADC_G_BOUND_BOUNDARY0_Pos   (0U)\r
-#define   VADC_G_BOUND_BOUNDARY0_Msk   (0x00000FFFU  << VADC_G_BOUND_BOUNDARY0_Pos)\r
-\r
-#define   VADC_G_BOUND_BOUNDARY1_Pos   (16U)\r
-#define   VADC_G_BOUND_BOUNDARY1_Msk   (0x00000FFFU  << VADC_G_BOUND_BOUNDARY1_Pos)\r
-\r
-/* VADC_G_SYNCTR  =  Synchronization Control Register, Group 0*/\r
-#define   VADC_G_SYNCTR_STSEL_Pos      (0U)\r
-#define   VADC_G_SYNCTR_STSEL_Msk      (0x00000003U  << VADC_G_SYNCTR_STSEL_Pos)\r
-\r
-#define   VADC_G_SYNCTR_EVALR1_Pos     (4U)\r
-#define   VADC_G_SYNCTR_EVALR1_Msk     (0x00000001U  << VADC_G_SYNCTR_EVALR1_Pos)\r
-\r
-#define   VADC_G_SYNCTR_EVALR2_Pos     (5U)\r
-#define   VADC_G_SYNCTR_EVALR2_Msk     (0x00000001U  << VADC_G_SYNCTR_EVALR2_Pos)\r
-\r
-#define   VADC_G_SYNCTR_EVALR3_Pos     (6U)\r
-#define   VADC_G_SYNCTR_EVALR3_Msk     (0x00000001U  << VADC_G_SYNCTR_EVALR3_Pos)\r
-\r
-/* VADC_G_BFL  =  Boundary Flag Register, Group 0*/\r
-#define   VADC_G_BFL_BFL0_Pos          (0U)\r
-#define   VADC_G_BFL_BFL0_Msk          (0x00000001U  << VADC_G_BFL_BFL0_Pos)\r
-\r
-#define   VADC_G_BFL_BFL1_Pos          (1U)\r
-#define   VADC_G_BFL_BFL1_Msk          (0x00000001U  << VADC_G_BFL_BFL1_Pos)\r
-\r
-#define   VADC_G_BFL_BFL2_Pos          (2U)\r
-#define   VADC_G_BFL_BFL2_Msk          (0x00000001U  << VADC_G_BFL_BFL2_Pos)\r
-\r
-#define   VADC_G_BFL_BFL3_Pos          (3U)\r
-#define   VADC_G_BFL_BFL3_Msk          (0x00000001U  << VADC_G_BFL_BFL3_Pos)\r
-\r
-#define   VADC_G_BFL_BFA0_Pos          (8U)\r
-#define   VADC_G_BFL_BFA0_Msk          (0x00000001U  << VADC_G_BFL_BFA0_Pos)\r
-\r
-#define   VADC_G_BFL_BFA1_Pos          (9U)\r
-#define   VADC_G_BFL_BFA1_Msk          (0x00000001U  << VADC_G_BFL_BFA1_Pos)\r
-\r
-#define   VADC_G_BFL_BFA2_Pos          (10U)\r
-#define   VADC_G_BFL_BFA2_Msk          (0x00000001U  << VADC_G_BFL_BFA2_Pos)\r
-\r
-#define   VADC_G_BFL_BFA3_Pos          (11U)\r
-#define   VADC_G_BFL_BFA3_Msk          (0x00000001U  << VADC_G_BFL_BFA3_Pos)\r
-\r
-#define   VADC_G_BFL_BFI0_Pos          (16U)\r
-#define   VADC_G_BFL_BFI0_Msk          (0x00000001U  << VADC_G_BFL_BFI0_Pos)\r
-\r
-#define   VADC_G_BFL_BFI1_Pos          (17U)\r
-#define   VADC_G_BFL_BFI1_Msk          (0x00000001U  << VADC_G_BFL_BFI1_Pos)\r
-\r
-#define   VADC_G_BFL_BFI2_Pos          (18U)\r
-#define   VADC_G_BFL_BFI2_Msk          (0x00000001U  << VADC_G_BFL_BFI2_Pos)\r
-\r
-#define   VADC_G_BFL_BFI3_Pos          (19U)\r
-#define   VADC_G_BFL_BFI3_Msk          (0x00000001U  << VADC_G_BFL_BFI3_Pos)\r
-\r
-\r
-/* VADC_G_QCTRL0  =  Queue x Source Control Register, Group 0*/\r
-#define   VADC_G_QCTRL0_SRCRESREG_Pos          (0U)\r
-#define   VADC_G_QCTRL0_SRCRESREG_Msk          (0x0000000FU  << VADC_G_QCTRL0_SRCRESREG_Pos)\r
-\r
-#define   VADC_G_QCTRL0_XTSEL_Pos      (8U)\r
-#define   VADC_G_QCTRL0_XTSEL_Msk      (0x0000000FU  << VADC_G_QCTRL0_XTSEL_Pos)\r
-\r
-#define   VADC_G_QCTRL0_XTLVL_Pos      (12U)\r
-#define   VADC_G_QCTRL0_XTLVL_Msk      (0x00000001U  << VADC_G_QCTRL0_XTLVL_Pos)\r
-\r
-#define   VADC_G_QCTRL0_XTMODE_Pos     (13U)\r
-#define   VADC_G_QCTRL0_XTMODE_Msk     (0x00000003U  << VADC_G_QCTRL0_XTMODE_Pos)\r
-\r
-#define   VADC_G_QCTRL0_XTWC_Pos       (15U)\r
-#define   VADC_G_QCTRL0_XTWC_Msk       (0x00000001U  << VADC_G_QCTRL0_XTWC_Pos)\r
-\r
-#define   VADC_G_QCTRL0_GTSEL_Pos      (16U)\r
-#define   VADC_G_QCTRL0_GTSEL_Msk      (0x0000000FU  << VADC_G_QCTRL0_GTSEL_Pos)\r
-\r
-#define   VADC_G_QCTRL0_GTLVL_Pos      (20U)\r
-#define   VADC_G_QCTRL0_GTLVL_Msk      (0x00000001U  << VADC_G_QCTRL0_GTLVL_Pos)\r
-\r
-#define   VADC_G_QCTRL0_GTWC_Pos       (23U)\r
-#define   VADC_G_QCTRL0_GTWC_Msk       (0x00000001U  << VADC_G_QCTRL0_GTWC_Pos)\r
-\r
-#define   VADC_G_QCTRL0_TMEN_Pos       (28U)\r
-#define   VADC_G_QCTRL0_TMEN_Msk       (0x00000001U  << VADC_G_QCTRL0_TMEN_Pos)\r
-\r
-#define   VADC_G_QCTRL0_TMWC_Pos       (31U)\r
-#define   VADC_G_QCTRL0_TMWC_Msk       (0x00000001U  << VADC_G_QCTRL0_TMWC_Pos)\r
-\r
-/* VADC_G_QMR0  =  Queue x Mode Register, Group 0*/\r
-#define   VADC_G_QMR0_ENGT_Pos         (0U)\r
-#define   VADC_G_QMR0_ENGT_Msk         (0x00000003U  << VADC_G_QMR0_ENGT_Pos)\r
-\r
-#define   VADC_G_QMR0_ENTR_Pos         (2U)\r
-#define   VADC_G_QMR0_ENTR_Msk         (0x00000001U  << VADC_G_QMR0_ENTR_Pos)\r
-\r
-#define   VADC_G_QMR0_CLRV_Pos         (8U)\r
-#define   VADC_G_QMR0_CLRV_Msk         (0x00000001U  << VADC_G_QMR0_CLRV_Pos)\r
-\r
-#define   VADC_G_QMR0_TREV_Pos         (9U)\r
-#define   VADC_G_QMR0_TREV_Msk         (0x00000001U  << VADC_G_QMR0_TREV_Pos)\r
-\r
-#define   VADC_G_QMR0_FLUSH_Pos        (10U)\r
-#define   VADC_G_QMR0_FLUSH_Msk        (0x00000001U  << VADC_G_QMR0_FLUSH_Pos)\r
-\r
-#define   VADC_G_QMR0_CEV_Pos          (11U)\r
-#define   VADC_G_QMR0_CEV_Msk          (0x00000001U  << VADC_G_QMR0_CEV_Pos)\r
-\r
-#define   VADC_G_QMR0_RPTDIS_Pos       (16U)\r
-#define   VADC_G_QMR0_RPTDIS_Msk       (0x00000001U  << VADC_G_QMR0_RPTDIS_Pos)\r
-\r
-/* VADC_G_QSR0  =  Queue x Status Register, Group 0*/\r
-#define   VADC_G_QSR0_FILL_Pos         (0U)\r
-#define   VADC_G_QSR0_FILL_Msk         (0x0000000FU  << VADC_G_QSR0_FILL_Pos)\r
-\r
-#define   VADC_G_QSR0_EMPTY_Pos        (5U)\r
-#define   VADC_G_QSR0_EMPTY_Msk        (0x00000001U  << VADC_G_QSR0_EMPTY_Pos)\r
-\r
-#define   VADC_G_QSR0_REQGT_Pos        (7U)\r
-#define   VADC_G_QSR0_REQGT_Msk        (0x00000001U  << VADC_G_QSR0_REQGT_Pos)\r
-\r
-#define   VADC_G_QSR0_EV_Pos   (8U)\r
-#define   VADC_G_QSR0_EV_Msk   (0x00000001U  << VADC_G_QSR0_EV_Pos)\r
-\r
-/* VADC_G_Q0R0  =  Queue x Register 0, Group 0*/\r
-#define   VADC_G_Q0R0_REQCHNR_Pos      (0U)\r
-#define   VADC_G_Q0R0_REQCHNR_Msk      (0x0000001FU  << VADC_G_Q0R0_REQCHNR_Pos)\r
-\r
-#define   VADC_G_Q0R0_RF_Pos   (5U)\r
-#define   VADC_G_Q0R0_RF_Msk   (0x00000001U  << VADC_G_Q0R0_RF_Pos)\r
-\r
-#define   VADC_G_Q0R0_ENSI_Pos         (6U)\r
-#define   VADC_G_Q0R0_ENSI_Msk         (0x00000001U  << VADC_G_Q0R0_ENSI_Pos)\r
-\r
-#define   VADC_G_Q0R0_EXTR_Pos         (7U)\r
-#define   VADC_G_Q0R0_EXTR_Msk         (0x00000001U  << VADC_G_Q0R0_EXTR_Pos)\r
-\r
-#define   VADC_G_Q0R0_V_Pos    (8U)\r
-#define   VADC_G_Q0R0_V_Msk    (0x00000001U  << VADC_G_Q0R0_V_Pos)\r
-\r
-/* VADC_G_QBUR0  =  Queue x Backup Register, Group 0*/\r
-#define   VADC_G_QBUR0_REQCHNR_Pos     (0U)\r
-#define   VADC_G_QBUR0_REQCHNR_Msk     (0x0000001FU  << VADC_G_QBUR0_REQCHNR_Pos)\r
-\r
-#define   VADC_G_QBUR0_RF_Pos          (5U)\r
-#define   VADC_G_QBUR0_RF_Msk          (0x00000001U  << VADC_G_QBUR0_RF_Pos)\r
-\r
-#define   VADC_G_QBUR0_ENSI_Pos        (6U)\r
-#define   VADC_G_QBUR0_ENSI_Msk        (0x00000001U  << VADC_G_QBUR0_ENSI_Pos)\r
-\r
-#define   VADC_G_QBUR0_EXTR_Pos        (7U)\r
-#define   VADC_G_QBUR0_EXTR_Msk        (0x00000001U  << VADC_G_QBUR0_EXTR_Pos)\r
-\r
-#define   VADC_G_QBUR0_V_Pos   (8U)\r
-#define   VADC_G_QBUR0_V_Msk   (0x00000001U  << VADC_G_QBUR0_V_Pos)\r
-\r
-#define   VADC_G_QBUR0_r_Pos   (9U)\r
-#define   VADC_G_QBUR0_r_Msk   (0x007FFFFFU  << VADC_G_QBUR0_r_Pos)\r
-\r
-/* VADC_G_QINR0  =  Queue x Input Register, Group 0*/\r
-#define   VADC_G_QINR0_REQCHNR_Pos     (0U)\r
-#define   VADC_G_QINR0_REQCHNR_Msk     (0x0000001FU  << VADC_G_QINR0_REQCHNR_Pos)\r
-\r
-#define   VADC_G_QINR0_RF_Pos          (5U)\r
-#define   VADC_G_QINR0_RF_Msk          (0x00000001U  << VADC_G_QINR0_RF_Pos)\r
-\r
-#define   VADC_G_QINR0_ENSI_Pos        (6U)\r
-#define   VADC_G_QINR0_ENSI_Msk        (0x00000001U  << VADC_G_QINR0_ENSI_Pos)\r
-\r
-#define   VADC_G_QINR0_EXTR_Pos        (7U)\r
-#define   VADC_G_QINR0_EXTR_Msk        (0x00000001U  << VADC_G_QINR0_EXTR_Pos)\r
-\r
-/* VADC_G_ASCTRL  =  Autoscan Source Control Register, Group 0*/\r
-#define   VADC_G_ASCTRL_SRCRESREG_Pos          (0U)\r
-#define   VADC_G_ASCTRL_SRCRESREG_Msk          (0x0000000FU  << VADC_G_ASCTRL_SRCRESREG_Pos)\r
-\r
-#define   VADC_G_ASCTRL_XTSEL_Pos      (8U)\r
-#define   VADC_G_ASCTRL_XTSEL_Msk      (0x0000000FU  << VADC_G_ASCTRL_XTSEL_Pos)\r
-\r
-#define   VADC_G_ASCTRL_XTLVL_Pos      (12U)\r
-#define   VADC_G_ASCTRL_XTLVL_Msk      (0x00000001U  << VADC_G_ASCTRL_XTLVL_Pos)\r
-\r
-#define   VADC_G_ASCTRL_XTMODE_Pos     (13U)\r
-#define   VADC_G_ASCTRL_XTMODE_Msk     (0x00000003U  << VADC_G_ASCTRL_XTMODE_Pos)\r
-\r
-#define   VADC_G_ASCTRL_XTWC_Pos       (15U)\r
-#define   VADC_G_ASCTRL_XTWC_Msk       (0x00000001U  << VADC_G_ASCTRL_XTWC_Pos)\r
-\r
-#define   VADC_G_ASCTRL_GTSEL_Pos      (16U)\r
-#define   VADC_G_ASCTRL_GTSEL_Msk      (0x0000000FU  << VADC_G_ASCTRL_GTSEL_Pos)\r
-\r
-#define   VADC_G_ASCTRL_GTLVL_Pos      (20U)\r
-#define   VADC_G_ASCTRL_GTLVL_Msk      (0x00000001U  << VADC_G_ASCTRL_GTLVL_Pos)\r
-\r
-#define   VADC_G_ASCTRL_GTWC_Pos       (23U)\r
-#define   VADC_G_ASCTRL_GTWC_Msk       (0x00000001U  << VADC_G_ASCTRL_GTWC_Pos)\r
-\r
-#define   VADC_G_ASCTRL_TMEN_Pos       (28U)\r
-#define   VADC_G_ASCTRL_TMEN_Msk       (0x00000001U  << VADC_G_ASCTRL_TMEN_Pos)\r
-\r
-#define   VADC_G_ASCTRL_TMWC_Pos       (31U)\r
-#define   VADC_G_ASCTRL_TMWC_Msk       (0x00000001U  << VADC_G_ASCTRL_TMWC_Pos)\r
-\r
-/* VADC_G_ASMR  =  Autoscan Source Mode Register, Group 0*/\r
-#define   VADC_G_ASMR_ENGT_Pos         (0U)\r
-#define   VADC_G_ASMR_ENGT_Msk         (0x00000003U  << VADC_G_ASMR_ENGT_Pos)\r
-\r
-#define   VADC_G_ASMR_ENTR_Pos         (2U)\r
-#define   VADC_G_ASMR_ENTR_Msk         (0x00000001U  << VADC_G_ASMR_ENTR_Pos)\r
-\r
-#define   VADC_G_ASMR_ENSI_Pos         (3U)\r
-#define   VADC_G_ASMR_ENSI_Msk         (0x00000001U  << VADC_G_ASMR_ENSI_Pos)\r
-\r
-#define   VADC_G_ASMR_SCAN_Pos         (4U)\r
-#define   VADC_G_ASMR_SCAN_Msk         (0x00000001U  << VADC_G_ASMR_SCAN_Pos)\r
-\r
-#define   VADC_G_ASMR_LDM_Pos          (5U)\r
-#define   VADC_G_ASMR_LDM_Msk          (0x00000001U  << VADC_G_ASMR_LDM_Pos)\r
-\r
-#define   VADC_G_ASMR_REQGT_Pos        (7U)\r
-#define   VADC_G_ASMR_REQGT_Msk        (0x00000001U  << VADC_G_ASMR_REQGT_Pos)\r
-\r
-#define   VADC_G_ASMR_CLRPND_Pos       (8U)\r
-#define   VADC_G_ASMR_CLRPND_Msk       (0x00000001U  << VADC_G_ASMR_CLRPND_Pos)\r
-\r
-#define   VADC_G_ASMR_LDEV_Pos         (9U)\r
-#define   VADC_G_ASMR_LDEV_Msk         (0x00000001U  << VADC_G_ASMR_LDEV_Pos)\r
-\r
-#define   VADC_G_ASMR_RPTDIS_Pos       (16U)\r
-#define   VADC_G_ASMR_RPTDIS_Msk       (0x00000001U  << VADC_G_ASMR_RPTDIS_Pos)\r
-\r
-/* VADC_G_ASSEL  =  Autoscan Source Channel Select Register, Group 0*/\r
-#define   VADC_G_ASSEL_CHSEL_Pos       (0U)\r
-#define   VADC_G_ASSEL_CHSEL_Msk       (0xFFFFFFFFU  << VADC_G_ASSEL_CHSEL_Pos)\r
-\r
-/* VADC_G_ASPND  =  Autoscan Source Pending Register, Group 0*/\r
-#define   VADC_G_ASPND_CHPND_Pos       (0U)\r
-#define   VADC_G_ASPND_CHPND_Msk       (0xFFFFFFFFU  << VADC_G_ASPND_CHPND_Pos)\r
-\r
-/* VADC_G_CEFLAG  =  Channel Event Flag Register, Group 0*/\r
-#define   VADC_G_CEFLAG_CEV0_Pos       (0U)\r
-#define   VADC_G_CEFLAG_CEV0_Msk       (0x00000001U  << VADC_G_CEFLAG_CEV0_Pos)\r
-\r
-#define   VADC_G_CEFLAG_CEV1_Pos       (1U)\r
-#define   VADC_G_CEFLAG_CEV1_Msk       (0x00000001U  << VADC_G_CEFLAG_CEV1_Pos)\r
-\r
-#define   VADC_G_CEFLAG_CEV2_Pos       (2U)\r
-#define   VADC_G_CEFLAG_CEV2_Msk       (0x00000001U  << VADC_G_CEFLAG_CEV2_Pos)\r
-\r
-#define   VADC_G_CEFLAG_CEV3_Pos       (3U)\r
-#define   VADC_G_CEFLAG_CEV3_Msk       (0x00000001U  << VADC_G_CEFLAG_CEV3_Pos)\r
-\r
-#define   VADC_G_CEFLAG_CEV4_Pos       (4U)\r
-#define   VADC_G_CEFLAG_CEV4_Msk       (0x00000001U  << VADC_G_CEFLAG_CEV4_Pos)\r
-\r
-#define   VADC_G_CEFLAG_CEV5_Pos       (5U)\r
-#define   VADC_G_CEFLAG_CEV5_Msk       (0x00000001U  << VADC_G_CEFLAG_CEV5_Pos)\r
-\r
-#define   VADC_G_CEFLAG_CEV6_Pos       (6U)\r
-#define   VADC_G_CEFLAG_CEV6_Msk       (0x00000001U  << VADC_G_CEFLAG_CEV6_Pos)\r
-\r
-#define   VADC_G_CEFLAG_CEV7_Pos       (7U)\r
-#define   VADC_G_CEFLAG_CEV7_Msk       (0x00000001U  << VADC_G_CEFLAG_CEV7_Pos)\r
-\r
-/* VADC_G_REFLAG  =  Result Event Flag Register, Group 0*/\r
-#define   VADC_G_REFLAG_REV0_Pos       (0U)\r
-#define   VADC_G_REFLAG_REV0_Msk       (0x00000001U  << VADC_G_REFLAG_REV0_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV1_Pos       (1U)\r
-#define   VADC_G_REFLAG_REV1_Msk       (0x00000001U  << VADC_G_REFLAG_REV1_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV2_Pos       (2U)\r
-#define   VADC_G_REFLAG_REV2_Msk       (0x00000001U  << VADC_G_REFLAG_REV2_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV3_Pos       (3U)\r
-#define   VADC_G_REFLAG_REV3_Msk       (0x00000001U  << VADC_G_REFLAG_REV3_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV4_Pos       (4U)\r
-#define   VADC_G_REFLAG_REV4_Msk       (0x00000001U  << VADC_G_REFLAG_REV4_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV5_Pos       (5U)\r
-#define   VADC_G_REFLAG_REV5_Msk       (0x00000001U  << VADC_G_REFLAG_REV5_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV6_Pos       (6U)\r
-#define   VADC_G_REFLAG_REV6_Msk       (0x00000001U  << VADC_G_REFLAG_REV6_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV7_Pos       (7U)\r
-#define   VADC_G_REFLAG_REV7_Msk       (0x00000001U  << VADC_G_REFLAG_REV7_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV8_Pos       (8U)\r
-#define   VADC_G_REFLAG_REV8_Msk       (0x00000001U  << VADC_G_REFLAG_REV8_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV9_Pos       (9U)\r
-#define   VADC_G_REFLAG_REV9_Msk       (0x00000001U  << VADC_G_REFLAG_REV9_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV10_Pos      (10U)\r
-#define   VADC_G_REFLAG_REV10_Msk      (0x00000001U  << VADC_G_REFLAG_REV10_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV11_Pos      (11U)\r
-#define   VADC_G_REFLAG_REV11_Msk      (0x00000001U  << VADC_G_REFLAG_REV11_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV12_Pos      (12U)\r
-#define   VADC_G_REFLAG_REV12_Msk      (0x00000001U  << VADC_G_REFLAG_REV12_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV13_Pos      (13U)\r
-#define   VADC_G_REFLAG_REV13_Msk      (0x00000001U  << VADC_G_REFLAG_REV13_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV14_Pos      (14U)\r
-#define   VADC_G_REFLAG_REV14_Msk      (0x00000001U  << VADC_G_REFLAG_REV14_Pos)\r
-\r
-#define   VADC_G_REFLAG_REV15_Pos      (15U)\r
-#define   VADC_G_REFLAG_REV15_Msk      (0x00000001U  << VADC_G_REFLAG_REV15_Pos)\r
-\r
-/* VADC_G_SEFLAG  =  Source Event Flag Register, Group 0*/\r
-#define   VADC_G_SEFLAG_SEV0_Pos       (0U)\r
-#define   VADC_G_SEFLAG_SEV0_Msk       (0x00000001U  << VADC_G_SEFLAG_SEV0_Pos)\r
-\r
-#define   VADC_G_SEFLAG_SEV1_Pos       (1U)\r
-#define   VADC_G_SEFLAG_SEV1_Msk       (0x00000001U  << VADC_G_SEFLAG_SEV1_Pos)\r
-\r
-/* VADC_G_CEFCLR  =  Channel Event Flag Clear Register, Group 0*/\r
-#define   VADC_G_CEFCLR_CEV0_Pos       (0U)\r
-#define   VADC_G_CEFCLR_CEV0_Msk       (0x00000001U  << VADC_G_CEFCLR_CEV0_Pos)\r
-\r
-#define   VADC_G_CEFCLR_CEV1_Pos       (1U)\r
-#define   VADC_G_CEFCLR_CEV1_Msk       (0x00000001U  << VADC_G_CEFCLR_CEV1_Pos)\r
-\r
-#define   VADC_G_CEFCLR_CEV2_Pos       (2U)\r
-#define   VADC_G_CEFCLR_CEV2_Msk       (0x00000001U  << VADC_G_CEFCLR_CEV2_Pos)\r
-\r
-#define   VADC_G_CEFCLR_CEV3_Pos       (3U)\r
-#define   VADC_G_CEFCLR_CEV3_Msk       (0x00000001U  << VADC_G_CEFCLR_CEV3_Pos)\r
-\r
-#define   VADC_G_CEFCLR_CEV4_Pos       (4U)\r
-#define   VADC_G_CEFCLR_CEV4_Msk       (0x00000001U  << VADC_G_CEFCLR_CEV4_Pos)\r
-\r
-#define   VADC_G_CEFCLR_CEV5_Pos       (5U)\r
-#define   VADC_G_CEFCLR_CEV5_Msk       (0x00000001U  << VADC_G_CEFCLR_CEV5_Pos)\r
-\r
-#define   VADC_G_CEFCLR_CEV6_Pos       (6U)\r
-#define   VADC_G_CEFCLR_CEV6_Msk       (0x00000001U  << VADC_G_CEFCLR_CEV6_Pos)\r
-\r
-#define   VADC_G_CEFCLR_CEV7_Pos       (7U)\r
-#define   VADC_G_CEFCLR_CEV7_Msk       (0x00000001U  << VADC_G_CEFCLR_CEV7_Pos)\r
-\r
-/* VADC_G_REFCLR  =  Result Event Flag Clear Register, Group 0*/\r
-#define   VADC_G_REFCLR_REV0_Pos       (0U)\r
-#define   VADC_G_REFCLR_REV0_Msk       (0x00000001U  << VADC_G_REFCLR_REV0_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV1_Pos       (1U)\r
-#define   VADC_G_REFCLR_REV1_Msk       (0x00000001U  << VADC_G_REFCLR_REV1_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV2_Pos       (2U)\r
-#define   VADC_G_REFCLR_REV2_Msk       (0x00000001U  << VADC_G_REFCLR_REV2_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV3_Pos       (3U)\r
-#define   VADC_G_REFCLR_REV3_Msk       (0x00000001U  << VADC_G_REFCLR_REV3_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV4_Pos       (4U)\r
-#define   VADC_G_REFCLR_REV4_Msk       (0x00000001U  << VADC_G_REFCLR_REV4_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV5_Pos       (5U)\r
-#define   VADC_G_REFCLR_REV5_Msk       (0x00000001U  << VADC_G_REFCLR_REV5_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV6_Pos       (6U)\r
-#define   VADC_G_REFCLR_REV6_Msk       (0x00000001U  << VADC_G_REFCLR_REV6_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV7_Pos       (7U)\r
-#define   VADC_G_REFCLR_REV7_Msk       (0x00000001U  << VADC_G_REFCLR_REV7_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV8_Pos       (8U)\r
-#define   VADC_G_REFCLR_REV8_Msk       (0x00000001U  << VADC_G_REFCLR_REV8_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV9_Pos       (9U)\r
-#define   VADC_G_REFCLR_REV9_Msk       (0x00000001U  << VADC_G_REFCLR_REV9_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV10_Pos      (10U)\r
-#define   VADC_G_REFCLR_REV10_Msk      (0x00000001U  << VADC_G_REFCLR_REV10_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV11_Pos      (11U)\r
-#define   VADC_G_REFCLR_REV11_Msk      (0x00000001U  << VADC_G_REFCLR_REV11_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV12_Pos      (12U)\r
-#define   VADC_G_REFCLR_REV12_Msk      (0x00000001U  << VADC_G_REFCLR_REV12_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV13_Pos      (13U)\r
-#define   VADC_G_REFCLR_REV13_Msk      (0x00000001U  << VADC_G_REFCLR_REV13_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV14_Pos      (14U)\r
-#define   VADC_G_REFCLR_REV14_Msk      (0x00000001U  << VADC_G_REFCLR_REV14_Pos)\r
-\r
-#define   VADC_G_REFCLR_REV15_Pos      (15U)\r
-#define   VADC_G_REFCLR_REV15_Msk      (0x00000001U  << VADC_G_REFCLR_REV15_Pos)\r
-\r
-/* VADC_G_SEFCLR  =  Source Event Flag Clear Register, Group 0*/\r
-#define   VADC_G_SEFCLR_SEV0_Pos       (0U)\r
-#define   VADC_G_SEFCLR_SEV0_Msk       (0x00000001U  << VADC_G_SEFCLR_SEV0_Pos)\r
-\r
-#define   VADC_G_SEFCLR_SEV1_Pos       (1U)\r
-#define   VADC_G_SEFCLR_SEV1_Msk       (0x00000001U  << VADC_G_SEFCLR_SEV1_Pos)\r
-\r
-/* VADC_G_CEVNP0  =  Channel Event Node Pointer Register 0, Group 0*/\r
-#define   VADC_G_CEVNP0_CEV0NP_Pos     (0U)\r
-#define   VADC_G_CEVNP0_CEV0NP_Msk     (0x0000000FU  << VADC_G_CEVNP0_CEV0NP_Pos)\r
-\r
-#define   VADC_G_CEVNP0_CEV1NP_Pos     (4U)\r
-#define   VADC_G_CEVNP0_CEV1NP_Msk     (0x0000000FU  << VADC_G_CEVNP0_CEV1NP_Pos)\r
-\r
-#define   VADC_G_CEVNP0_CEV2NP_Pos     (8U)\r
-#define   VADC_G_CEVNP0_CEV2NP_Msk     (0x0000000FU  << VADC_G_CEVNP0_CEV2NP_Pos)\r
-\r
-#define   VADC_G_CEVNP0_CEV3NP_Pos     (12U)\r
-#define   VADC_G_CEVNP0_CEV3NP_Msk     (0x0000000FU  << VADC_G_CEVNP0_CEV3NP_Pos)\r
-\r
-#define   VADC_G_CEVNP0_CEV4NP_Pos     (16U)\r
-#define   VADC_G_CEVNP0_CEV4NP_Msk     (0x0000000FU  << VADC_G_CEVNP0_CEV4NP_Pos)\r
-\r
-#define   VADC_G_CEVNP0_CEV5NP_Pos     (20U)\r
-#define   VADC_G_CEVNP0_CEV5NP_Msk     (0x0000000FU  << VADC_G_CEVNP0_CEV5NP_Pos)\r
-\r
-#define   VADC_G_CEVNP0_CEV6NP_Pos     (24U)\r
-#define   VADC_G_CEVNP0_CEV6NP_Msk     (0x0000000FU  << VADC_G_CEVNP0_CEV6NP_Pos)\r
-\r
-#define   VADC_G_CEVNP0_CEV7NP_Pos     (28U)\r
-#define   VADC_G_CEVNP0_CEV7NP_Msk     (0x0000000FU  << VADC_G_CEVNP0_CEV7NP_Pos)\r
-\r
-/* VADC_G_REVNP0  =  Result Event Node Pointer Register 0, Group 0*/\r
-#define   VADC_G_REVNP0_REV0NP_Pos     (0U)\r
-#define   VADC_G_REVNP0_REV0NP_Msk     (0x0000000FU  << VADC_G_REVNP0_REV0NP_Pos)\r
-\r
-#define   VADC_G_REVNP0_REV1NP_Pos     (4U)\r
-#define   VADC_G_REVNP0_REV1NP_Msk     (0x0000000FU  << VADC_G_REVNP0_REV1NP_Pos)\r
-\r
-#define   VADC_G_REVNP0_REV2NP_Pos     (8U)\r
-#define   VADC_G_REVNP0_REV2NP_Msk     (0x0000000FU  << VADC_G_REVNP0_REV2NP_Pos)\r
-\r
-#define   VADC_G_REVNP0_REV3NP_Pos     (12U)\r
-#define   VADC_G_REVNP0_REV3NP_Msk     (0x0000000FU  << VADC_G_REVNP0_REV3NP_Pos)\r
-\r
-#define   VADC_G_REVNP0_REV4NP_Pos     (16U)\r
-#define   VADC_G_REVNP0_REV4NP_Msk     (0x0000000FU  << VADC_G_REVNP0_REV4NP_Pos)\r
-\r
-#define   VADC_G_REVNP0_REV5NP_Pos     (20U)\r
-#define   VADC_G_REVNP0_REV5NP_Msk     (0x0000000FU  << VADC_G_REVNP0_REV5NP_Pos)\r
-\r
-#define   VADC_G_REVNP0_REV6NP_Pos     (24U)\r
-#define   VADC_G_REVNP0_REV6NP_Msk     (0x0000000FU  << VADC_G_REVNP0_REV6NP_Pos)\r
-\r
-#define   VADC_G_REVNP0_REV7NP_Pos     (28U)\r
-#define   VADC_G_REVNP0_REV7NP_Msk     (0x0000000FU  << VADC_G_REVNP0_REV7NP_Pos)\r
-\r
-/* VADC_G_REVNP1  =  Result Event Node Pointer Register 1, Group 0*/\r
-#define   VADC_G_REVNP1_REV8NP_Pos     (0U)\r
-#define   VADC_G_REVNP1_REV8NP_Msk     (0x0000000FU  << VADC_G_REVNP1_REV8NP_Pos)\r
-\r
-#define   VADC_G_REVNP1_REV9NP_Pos     (4U)\r
-#define   VADC_G_REVNP1_REV9NP_Msk     (0x0000000FU  << VADC_G_REVNP1_REV9NP_Pos)\r
-\r
-#define   VADC_G_REVNP1_REV10NP_Pos    (8U)\r
-#define   VADC_G_REVNP1_REV10NP_Msk    (0x0000000FU  << VADC_G_REVNP1_REV10NP_Pos)\r
-\r
-#define   VADC_G_REVNP1_REV11NP_Pos    (12U)\r
-#define   VADC_G_REVNP1_REV11NP_Msk    (0x0000000FU  << VADC_G_REVNP1_REV11NP_Pos)\r
-\r
-#define   VADC_G_REVNP1_REV12NP_Pos    (16U)\r
-#define   VADC_G_REVNP1_REV12NP_Msk    (0x0000000FU  << VADC_G_REVNP1_REV12NP_Pos)\r
-\r
-#define   VADC_G_REVNP1_REV13NP_Pos    (20U)\r
-#define   VADC_G_REVNP1_REV13NP_Msk    (0x0000000FU  << VADC_G_REVNP1_REV13NP_Pos)\r
-\r
-#define   VADC_G_REVNP1_REV14NP_Pos    (24U)\r
-#define   VADC_G_REVNP1_REV14NP_Msk    (0x0000000FU  << VADC_G_REVNP1_REV14NP_Pos)\r
-\r
-#define   VADC_G_REVNP1_REV15NP_Pos    (28U)\r
-#define   VADC_G_REVNP1_REV15NP_Msk    (0x0000000FU  << VADC_G_REVNP1_REV15NP_Pos)\r
-\r
-/* VADC_G_SEVNP  =  Source Event Node Pointer Register, Group 0*/\r
-#define   VADC_G_SEVNP_SEV0NP_Pos      (0U)\r
-#define   VADC_G_SEVNP_SEV0NP_Msk      (0x0000000FU  << VADC_G_SEVNP_SEV0NP_Pos)\r
-\r
-#define   VADC_G_SEVNP_SEV1NP_Pos      (4U)\r
-#define   VADC_G_SEVNP_SEV1NP_Msk      (0x0000000FU  << VADC_G_SEVNP_SEV1NP_Pos)\r
-\r
-/* VADC_G_SRACT  =  Service Request Software Activation Trigger, Group 0*/\r
-#define   VADC_G_SRACT_AGSR0_Pos       (0U)\r
-#define   VADC_G_SRACT_AGSR0_Msk       (0x00000001U  << VADC_G_SRACT_AGSR0_Pos)\r
-\r
-#define   VADC_G_SRACT_AGSR1_Pos       (1U)\r
-#define   VADC_G_SRACT_AGSR1_Msk       (0x00000001U  << VADC_G_SRACT_AGSR1_Pos)\r
-\r
-#define   VADC_G_SRACT_AGSR2_Pos       (2U)\r
-#define   VADC_G_SRACT_AGSR2_Msk       (0x00000001U  << VADC_G_SRACT_AGSR2_Pos)\r
-\r
-#define   VADC_G_SRACT_AGSR3_Pos       (3U)\r
-#define   VADC_G_SRACT_AGSR3_Msk       (0x00000001U  << VADC_G_SRACT_AGSR3_Pos)\r
-\r
-#define   VADC_G_SRACT_ASSR0_Pos       (8U)\r
-#define   VADC_G_SRACT_ASSR0_Msk       (0x00000001U  << VADC_G_SRACT_ASSR0_Pos)\r
-\r
-#define   VADC_G_SRACT_ASSR1_Pos       (9U)\r
-#define   VADC_G_SRACT_ASSR1_Msk       (0x00000001U  << VADC_G_SRACT_ASSR1_Pos)\r
-\r
-#define   VADC_G_SRACT_ASSR2_Pos       (10U)\r
-#define   VADC_G_SRACT_ASSR2_Msk       (0x00000001U  << VADC_G_SRACT_ASSR2_Pos)\r
-\r
-#define   VADC_G_SRACT_ASSR3_Pos       (11U)\r
-#define   VADC_G_SRACT_ASSR3_Msk       (0x00000001U  << VADC_G_SRACT_ASSR3_Pos)\r
-\r
-/* VADC_G_EMUXCTR  =  E0ternal Multiplexer Control Register, Group x*/\r
-#define   VADC_G_EMUXCTR_EMUXSET_Pos   (0U)\r
-#define   VADC_G_EMUXCTR_EMUXSET_Msk   (0x00000007U  << VADC_G_EMUXCTR_EMUXSET_Pos)\r
-\r
-#define   VADC_G_EMUXCTR_EMUXACT_Pos   (8U)\r
-#define   VADC_G_EMUXCTR_EMUXACT_Msk   (0x00000007U  << VADC_G_EMUXCTR_EMUXACT_Pos)\r
-\r
-#define   VADC_G_EMUXCTR_EMUXCH_Pos    (16U)\r
-#define   VADC_G_EMUXCTR_EMUXCH_Msk    (0x000003FFU  << VADC_G_EMUXCTR_EMUXCH_Pos)\r
-\r
-#define   VADC_G_EMUXCTR_EMUXMODE_Pos          (26U)\r
-#define   VADC_G_EMUXCTR_EMUXMODE_Msk          (0x00000003U  << VADC_G_EMUXCTR_EMUXMODE_Pos)\r
-\r
-#define   VADC_G_EMUXCTR_EMXCOD_Pos    (28U)\r
-#define   VADC_G_EMUXCTR_EMXCOD_Msk    (0x00000001U  << VADC_G_EMUXCTR_EMXCOD_Pos)\r
-\r
-#define   VADC_G_EMUXCTR_EMXST_Pos     (29U)\r
-#define   VADC_G_EMUXCTR_EMXST_Msk     (0x00000001U  << VADC_G_EMUXCTR_EMXST_Pos)\r
-\r
-#define   VADC_G_EMUXCTR_EMXCSS_Pos    (30U)\r
-#define   VADC_G_EMUXCTR_EMXCSS_Msk    (0x00000001U  << VADC_G_EMUXCTR_EMXCSS_Pos)\r
-\r
-#define   VADC_G_EMUXCTR_EMXWC_Pos     (31U)\r
-#define   VADC_G_EMUXCTR_EMXWC_Msk     (0x00000001U  << VADC_G_EMUXCTR_EMXWC_Pos)\r
-\r
-/* VADC_G_VFR  =  Valid Flag Register, Group 0*/\r
-#define   VADC_G_VFR_VF0_Pos   (0U)\r
-#define   VADC_G_VFR_VF0_Msk   (0x00000001U  << VADC_G_VFR_VF0_Pos)\r
-\r
-#define   VADC_G_VFR_VF1_Pos   (1U)\r
-#define   VADC_G_VFR_VF1_Msk   (0x00000001U  << VADC_G_VFR_VF1_Pos)\r
-\r
-#define   VADC_G_VFR_VF2_Pos   (2U)\r
-#define   VADC_G_VFR_VF2_Msk   (0x00000001U  << VADC_G_VFR_VF2_Pos)\r
-\r
-#define   VADC_G_VFR_VF3_Pos   (3U)\r
-#define   VADC_G_VFR_VF3_Msk   (0x00000001U  << VADC_G_VFR_VF3_Pos)\r
-\r
-#define   VADC_G_VFR_VF4_Pos   (4U)\r
-#define   VADC_G_VFR_VF4_Msk   (0x00000001U  << VADC_G_VFR_VF4_Pos)\r
-\r
-#define   VADC_G_VFR_VF5_Pos   (5U)\r
-#define   VADC_G_VFR_VF5_Msk   (0x00000001U  << VADC_G_VFR_VF5_Pos)\r
-\r
-#define   VADC_G_VFR_VF6_Pos   (6U)\r
-#define   VADC_G_VFR_VF6_Msk   (0x00000001U  << VADC_G_VFR_VF6_Pos)\r
-\r
-#define   VADC_G_VFR_VF7_Pos   (7U)\r
-#define   VADC_G_VFR_VF7_Msk   (0x00000001U  << VADC_G_VFR_VF7_Pos)\r
-\r
-#define   VADC_G_VFR_VF8_Pos   (8U)\r
-#define   VADC_G_VFR_VF8_Msk   (0x00000001U  << VADC_G_VFR_VF8_Pos)\r
-\r
-#define   VADC_G_VFR_VF9_Pos   (9U)\r
-#define   VADC_G_VFR_VF9_Msk   (0x00000001U  << VADC_G_VFR_VF9_Pos)\r
-\r
-#define   VADC_G_VFR_VF10_Pos          (10U)\r
-#define   VADC_G_VFR_VF10_Msk          (0x00000001U  << VADC_G_VFR_VF10_Pos)\r
-\r
-#define   VADC_G_VFR_VF11_Pos          (11U)\r
-#define   VADC_G_VFR_VF11_Msk          (0x00000001U  << VADC_G_VFR_VF11_Pos)\r
-\r
-#define   VADC_G_VFR_VF12_Pos          (12U)\r
-#define   VADC_G_VFR_VF12_Msk          (0x00000001U  << VADC_G_VFR_VF12_Pos)\r
-\r
-#define   VADC_G_VFR_VF13_Pos          (13U)\r
-#define   VADC_G_VFR_VF13_Msk          (0x00000001U  << VADC_G_VFR_VF13_Pos)\r
-\r
-#define   VADC_G_VFR_VF14_Pos          (14U)\r
-#define   VADC_G_VFR_VF14_Msk          (0x00000001U  << VADC_G_VFR_VF14_Pos)\r
-\r
-#define   VADC_G_VFR_VF15_Pos          (15U)\r
-#define   VADC_G_VFR_VF15_Msk          (0x00000001U  << VADC_G_VFR_VF15_Pos)\r
-\r
-/* VADC_G_CHCTRy  =  Group 0, Channel x Ctrl. Reg.*/\r
-#define   VADC_G_CHCTR_ICLSEL_Pos      (0U)\r
-#define   VADC_G_CHCTR_ICLSEL_Msk      (0x00000003U  << VADC_G_CHCTR_ICLSEL_Pos)\r
-\r
-#define   VADC_G_CHCTR_BNDSELL_Pos     (4U)\r
-#define   VADC_G_CHCTR_BNDSELL_Msk     (0x00000003U  << VADC_G_CHCTR_BNDSELL_Pos)\r
-\r
-#define   VADC_G_CHCTR_BNDSELU_Pos     (6U)\r
-#define   VADC_G_CHCTR_BNDSELU_Msk     (0x00000003U  << VADC_G_CHCTR_BNDSELU_Pos)\r
-\r
-#define   VADC_G_CHCTR_CHEVMODE_Pos    (8U)\r
-#define   VADC_G_CHCTR_CHEVMODE_Msk    (0x00000003U  << VADC_G_CHCTR_CHEVMODE_Pos)\r
-\r
-#define   VADC_G_CHCTR_SYNC_Pos        (10U)\r
-#define   VADC_G_CHCTR_SYNC_Msk        (0x00000001U  << VADC_G_CHCTR_SYNC_Pos)\r
-\r
-#define   VADC_G_CHCTR_REFSEL_Pos      (11U)\r
-#define   VADC_G_CHCTR_REFSEL_Msk      (0x00000001U  << VADC_G_CHCTR_REFSEL_Pos)\r
-\r
-#define   VADC_G_CHCTR_BNDSELX_Pos     (12U)\r
-#define   VADC_G_CHCTR_BNDSELX_Msk     (0x0000000FU  << VADC_G_CHCTR_BNDSELX_Pos)\r
-\r
-#define   VADC_G_CHCTR_RESREG_Pos      (16U)\r
-#define   VADC_G_CHCTR_RESREG_Msk      (0x0000000FU  << VADC_G_CHCTR_RESREG_Pos)\r
-\r
-#define   VADC_G_CHCTR_RESTBS_Pos      (20U)\r
-#define   VADC_G_CHCTR_RESTBS_Msk      (0x00000001U  << VADC_G_CHCTR_RESTBS_Pos)\r
-\r
-#define   VADC_G_CHCTR_RESPOS_Pos      (21U)\r
-#define   VADC_G_CHCTR_RESPOS_Msk      (0x00000001U  << VADC_G_CHCTR_RESPOS_Pos)\r
-\r
-#define   VADC_G_CHCTR_BWDCH_Pos       (28U)\r
-#define   VADC_G_CHCTR_BWDCH_Msk       (0x00000003U  << VADC_G_CHCTR_BWDCH_Pos)\r
-\r
-#define   VADC_G_CHCTR_BWDEN_Pos       (30U)\r
-#define   VADC_G_CHCTR_BWDEN_Msk       (0x00000001U  << VADC_G_CHCTR_BWDEN_Pos)\r
-\r
-/* VADC_G_RCRy  =  Group x Result Control Reg. 0*/\r
-#define   VADC_G_RCR_DRCTR_Pos         (16U)\r
-#define   VADC_G_RCR_DRCTR_Msk         (0x0000000FU  << VADC_G_RCR_DRCTR_Pos)\r
-\r
-#define   VADC_G_RCR_DMM_Pos   (20U)\r
-#define   VADC_G_RCR_DMM_Msk   (0x00000003U  << VADC_G_RCR_DMM_Pos)\r
-\r
-#define   VADC_G_RCR_WFR_Pos   (24U)\r
-#define   VADC_G_RCR_WFR_Msk   (0x00000001U  << VADC_G_RCR_WFR_Pos)\r
-\r
-#define   VADC_G_RCR_FEN_Pos   (25U)\r
-#define   VADC_G_RCR_FEN_Msk   (0x00000003U  << VADC_G_RCR_FEN_Pos)\r
-\r
-#define   VADC_G_RCR_SRGEN_Pos         (31U)\r
-#define   VADC_G_RCR_SRGEN_Msk         (0x00000001U  << VADC_G_RCR_SRGEN_Pos)\r
-\r
-/* VADC_G_RESy  =  Group x Result Register 0*/\r
-#define   VADC_G_RES_RESULT_Pos        (0U)\r
-#define   VADC_G_RES_RESULT_Msk        (0x0000FFFFU  << VADC_G_RES_RESULT_Pos)\r
-\r
-#define   VADC_G_RES_DRC_Pos   (16U)\r
-#define   VADC_G_RES_DRC_Msk   (0x0000000FU  << VADC_G_RES_DRC_Pos)\r
-\r
-#define   VADC_G_RES_CHNR_Pos          (20U)\r
-#define   VADC_G_RES_CHNR_Msk          (0x0000001FU  << VADC_G_RES_CHNR_Pos)\r
-\r
-#define   VADC_G_RES_EMUX_Pos          (25U)\r
-#define   VADC_G_RES_EMUX_Msk          (0x00000007U  << VADC_G_RES_EMUX_Pos)\r
-\r
-#define   VADC_G_RES_CRS_Pos   (28U)\r
-#define   VADC_G_RES_CRS_Msk   (0x00000003U  << VADC_G_RES_CRS_Pos)\r
-\r
-#define   VADC_G_RES_FCR_Pos   (30U)\r
-#define   VADC_G_RES_FCR_Msk   (0x00000001U  << VADC_G_RES_FCR_Pos)\r
-\r
-#define   VADC_G_RES_VF_Pos    (31U)\r
-#define   VADC_G_RES_VF_Msk    (0x00000001U  << VADC_G_RES_VF_Pos)\r
-\r
-/* VADC_G_RESDy  =  Group x Result Reg. 0, Debug*/\r
-#define   VADC_G_RESD_RESULT_Pos       (0U)\r
-#define   VADC_G_RESD_RESULT_Msk       (0x0000FFFFU  << VADC_G_RESD_RESULT_Pos)\r
-\r
-#define   VADC_G_RESD_DRC_Pos          (16U)\r
-#define   VADC_G_RESD_DRC_Msk          (0x0000000FU  << VADC_G_RESD_DRC_Pos)\r
-\r
-#define   VADC_G_RESD_CHNR_Pos         (20U)\r
-#define   VADC_G_RESD_CHNR_Msk         (0x0000001FU  << VADC_G_RESD_CHNR_Pos)\r
-\r
-#define   VADC_G_RESD_EMUX_Pos         (25U)\r
-#define   VADC_G_RESD_EMUX_Msk         (0x00000007U  << VADC_G_RESD_EMUX_Pos)\r
-\r
-#define   VADC_G_RESD_CRS_Pos          (28U)\r
-#define   VADC_G_RESD_CRS_Msk          (0x00000003U  << VADC_G_RESD_CRS_Pos)\r
-\r
-#define   VADC_G_RESD_FCR_Pos          (30U)\r
-#define   VADC_G_RESD_FCR_Msk          (0x00000001U  << VADC_G_RESD_FCR_Pos)\r
-\r
-#define   VADC_G_RESD_VF_Pos   (31U)\r
-#define   VADC_G_RESD_VF_Msk   (0x00000001U  << VADC_G_RESD_VF_Pos)\r
-\r
-/* VADC_CLC  =  Clock Control Register*/\r
-#define   VADC_CLC_DISR_Pos    (0U)\r
-#define   VADC_CLC_DISR_Msk    (0x00000001U  << VADC_CLC_DISR_Pos)\r
-\r
-#define   VADC_CLC_DISS_Pos    (1U)\r
-#define   VADC_CLC_DISS_Msk    (0x00000001U  << VADC_CLC_DISS_Pos)\r
-\r
-#define   VADC_CLC_EDIS_Pos    (3U)\r
-#define   VADC_CLC_EDIS_Msk    (0x00000001U  << VADC_CLC_EDIS_Pos)\r
-\r
-/* VADC_ID  =  Module Identification Register*/\r
-#define   VADC_ID_MOD_REV_Pos          (0U)\r
-#define   VADC_ID_MOD_REV_Msk          (0x000000FFU  << VADC_ID_MOD_REV_Pos)\r
-\r
-#define   VADC_ID_MOD_TYPE_Pos         (8U)\r
-#define   VADC_ID_MOD_TYPE_Msk         (0x000000FFU  << VADC_ID_MOD_TYPE_Pos)\r
-\r
-#define   VADC_ID_MOD_NUMBER_Pos       (16U)\r
-#define   VADC_ID_MOD_NUMBER_Msk       (0x0000FFFFU  << VADC_ID_MOD_NUMBER_Pos)\r
-\r
-/* VADC_OCS  =  OCDS Control and Status Register*/\r
-#define   VADC_OCS_TGS_Pos     (0U)\r
-#define   VADC_OCS_TGS_Msk     (0x00000003U  << VADC_OCS_TGS_Pos)\r
-\r
-#define   VADC_OCS_TGB_Pos     (2U)\r
-#define   VADC_OCS_TGB_Msk     (0x00000001U  << VADC_OCS_TGB_Pos)\r
-\r
-#define   VADC_OCS_TG_P_Pos    (3U)\r
-#define   VADC_OCS_TG_P_Msk    (0x00000001U  << VADC_OCS_TG_P_Pos)\r
-\r
-#define   VADC_OCS_SUS_Pos     (24U)\r
-#define   VADC_OCS_SUS_Msk     (0x0000000FU  << VADC_OCS_SUS_Pos)\r
-\r
-#define   VADC_OCS_SUS_P_Pos   (28U)\r
-#define   VADC_OCS_SUS_P_Msk   (0x00000001U  << VADC_OCS_SUS_P_Pos)\r
-\r
-#define   VADC_OCS_SUSSTA_Pos          (29U)\r
-#define   VADC_OCS_SUSSTA_Msk          (0x00000001U  << VADC_OCS_SUSSTA_Pos)\r
-\r
-/* VADC_GLOBCFG  =  Global Configuration Register*/\r
-#define   VADC_GLOBCFG_DIVA_Pos        (0U)\r
-#define   VADC_GLOBCFG_DIVA_Msk        (0x0000001FU  << VADC_GLOBCFG_DIVA_Pos)\r
-\r
-#define   VADC_GLOBCFG_DCMSB_Pos       (7U)\r
-#define   VADC_GLOBCFG_DCMSB_Msk       (0x00000001U  << VADC_GLOBCFG_DCMSB_Pos)\r
-\r
-#define   VADC_GLOBCFG_DIVD_Pos        (8U)\r
-#define   VADC_GLOBCFG_DIVD_Msk        (0x00000003U  << VADC_GLOBCFG_DIVD_Pos)\r
-\r
-#define   VADC_GLOBCFG_DIVWC_Pos       (15U)\r
-#define   VADC_GLOBCFG_DIVWC_Msk       (0x00000001U  << VADC_GLOBCFG_DIVWC_Pos)\r
-\r
-#define   VADC_GLOBCFG_DPCAL0_Pos      (16U)\r
-#define   VADC_GLOBCFG_DPCAL0_Msk      (0x00000001U  << VADC_GLOBCFG_DPCAL0_Pos)\r
-\r
-#define   VADC_GLOBCFG_DPCAL1_Pos      (17U)\r
-#define   VADC_GLOBCFG_DPCAL1_Msk      (0x00000001U  << VADC_GLOBCFG_DPCAL1_Pos)\r
-\r
-#define   VADC_GLOBCFG_DPCAL2_Pos      (18U)\r
-#define   VADC_GLOBCFG_DPCAL2_Msk      (0x00000001U  << VADC_GLOBCFG_DPCAL2_Pos)\r
-\r
-#define   VADC_GLOBCFG_DPCAL3_Pos      (19U)\r
-#define   VADC_GLOBCFG_DPCAL3_Msk      (0x00000001U  << VADC_GLOBCFG_DPCAL3_Pos)\r
-\r
-#define   VADC_GLOBCFG_SUCAL_Pos       (31U)\r
-#define   VADC_GLOBCFG_SUCAL_Msk       (0x00000001U  << VADC_GLOBCFG_SUCAL_Pos)\r
-\r
-/* VADC_GLOBICLASSy  =  Input Class Register 0, Global*/\r
-#define   VADC_GLOBICLASS_STCS_Pos     (0U)\r
-#define   VADC_GLOBICLASS_STCS_Msk     (0x0000001FU  << VADC_GLOBICLASS_STCS_Pos)\r
-\r
-#define   VADC_GLOBICLASS_CMS_Pos      (8U)\r
-#define   VADC_GLOBICLASS_CMS_Msk      (0x00000007U  << VADC_GLOBICLASS_CMS_Pos)\r
-\r
-#define   VADC_GLOBICLASS_STCE_Pos     (16U)\r
-#define   VADC_GLOBICLASS_STCE_Msk     (0x0000001FU  << VADC_GLOBICLASS_STCE_Pos)\r
-\r
-#define   VADC_GLOBICLASS_CME_Pos      (24U)\r
-#define   VADC_GLOBICLASS_CME_Msk      (0x00000007U  << VADC_GLOBICLASS_CME_Pos)\r
-\r
-/* VADC_GLOBBOUND  =  Global Boundary Select Register*/\r
-#define   VADC_GLOBBOUND_BOUNDARY0_Pos         (0U)\r
-#define   VADC_GLOBBOUND_BOUNDARY0_Msk         (0x00000FFFU  << VADC_GLOBBOUND_BOUNDARY0_Pos)\r
-\r
-#define   VADC_GLOBBOUND_BOUNDARY1_Pos         (16U)\r
-#define   VADC_GLOBBOUND_BOUNDARY1_Msk         (0x00000FFFU  << VADC_GLOBBOUND_BOUNDARY1_Pos)\r
-\r
-/* VADC_GLOBEFLAG  =  Global Event Flag Register*/\r
-#define   VADC_GLOBEFLAG_SEVGLB_Pos    (0U)\r
-#define   VADC_GLOBEFLAG_SEVGLB_Msk    (0x00000001U  << VADC_GLOBEFLAG_SEVGLB_Pos)\r
-\r
-#define   VADC_GLOBEFLAG_REVGLB_Pos    (8U)\r
-#define   VADC_GLOBEFLAG_REVGLB_Msk    (0x00000001U  << VADC_GLOBEFLAG_REVGLB_Pos)\r
-\r
-#define   VADC_GLOBEFLAG_SEVGLBCLR_Pos         (16U)\r
-#define   VADC_GLOBEFLAG_SEVGLBCLR_Msk         (0x00000001U  << VADC_GLOBEFLAG_SEVGLBCLR_Pos)\r
-\r
-#define   VADC_GLOBEFLAG_REVGLBCLR_Pos         (24U)\r
-#define   VADC_GLOBEFLAG_REVGLBCLR_Msk         (0x00000001U  << VADC_GLOBEFLAG_REVGLBCLR_Pos)\r
-\r
-/* VADC_GLOBEVNP  =  Global Event Node Pointer Register*/\r
-#define   VADC_GLOBEVNP_SEV0NP_Pos     (0U)\r
-#define   VADC_GLOBEVNP_SEV0NP_Msk     (0x0000000FU  << VADC_GLOBEVNP_SEV0NP_Pos)\r
-\r
-#define   VADC_GLOBEVNP_REV0NP_Pos     (16U)\r
-#define   VADC_GLOBEVNP_REV0NP_Msk     (0x0000000FU  << VADC_GLOBEVNP_REV0NP_Pos)\r
-\r
-/* VADC_GLOBTF  =  Global Test Functions Register*/\r
-#define   VADC_GLOBTF_CDCH_Pos         (0U)\r
-#define   VADC_GLOBTF_CDCH_Msk         (0x0000000FU  << VADC_GLOBTF_CDCH_Pos)\r
-\r
-#define   VADC_GLOBTF_CDGR_Pos         (4U)\r
-#define   VADC_GLOBTF_CDGR_Msk         (0x0000000FU  << VADC_GLOBTF_CDGR_Pos)\r
-\r
-#define   VADC_GLOBTF_CDEN_Pos         (8U)\r
-#define   VADC_GLOBTF_CDEN_Msk         (0x00000001U  << VADC_GLOBTF_CDEN_Pos)\r
-\r
-#define   VADC_GLOBTF_CDSEL_Pos        (9U)\r
-#define   VADC_GLOBTF_CDSEL_Msk        (0x00000003U  << VADC_GLOBTF_CDSEL_Pos)\r
-\r
-#define   VADC_GLOBTF_CDWC_Pos         (15U)\r
-#define   VADC_GLOBTF_CDWC_Msk         (0x00000001U  << VADC_GLOBTF_CDWC_Pos)\r
-\r
-#define   VADC_GLOBTF_PDD_Pos          (16U)\r
-#define   VADC_GLOBTF_PDD_Msk          (0x00000001U  << VADC_GLOBTF_PDD_Pos)\r
-\r
-#define   VADC_GLOBTF_MDPD_Pos         (17U)\r
-#define   VADC_GLOBTF_MDPD_Msk         (0x00000001U  << VADC_GLOBTF_MDPD_Pos)\r
-\r
-#define   VADC_GLOBTF_MDPU_Pos         (18U)\r
-#define   VADC_GLOBTF_MDPU_Msk         (0x00000001U  << VADC_GLOBTF_MDPU_Pos)\r
-\r
-#define   VADC_GLOBTF_MDWC_Pos         (23U)\r
-#define   VADC_GLOBTF_MDWC_Msk         (0x00000001U  << VADC_GLOBTF_MDWC_Pos)\r
-\r
-#define   VADC_GLOBTF_TRSW_Pos         (24U)\r
-#define   VADC_GLOBTF_TRSW_Msk         (0x00000001U  << VADC_GLOBTF_TRSW_Pos)\r
-\r
-#define   VADC_GLOBTF_TREV_Pos         (25U)\r
-#define   VADC_GLOBTF_TREV_Msk         (0x00000001U  << VADC_GLOBTF_TREV_Pos)\r
-\r
-#define   VADC_GLOBTF_SRGMODE_Pos      (29U)\r
-#define   VADC_GLOBTF_SRGMODE_Msk      (0x00000003U  << VADC_GLOBTF_SRGMODE_Pos)\r
-\r
-#define   VADC_GLOBTF_SRGWC_Pos        (31U)\r
-#define   VADC_GLOBTF_SRGWC_Msk        (0x00000001U  << VADC_GLOBTF_SRGWC_Pos)\r
-\r
-/* VADC_BRSSELy  =  Background Request Source Channel Select Register, Group 0*/\r
-#define   VADC_BRSSEL_CHSELG_Pos       (0U)\r
-#define   VADC_BRSSEL_CHSELG_Msk       (0xFFFFFFFFU  << VADC_BRSSEL_CHSELG_Pos)\r
-\r
-/* VADC_BRSPNDy  =  Background Request Source Pending Register, Group 0*/\r
-#define   VADC_BRSPND_CHPNDG_Pos       (0U)\r
-#define   VADC_BRSPND_CHPNDG_Msk       (0xFFFFFFFFU  << VADC_BRSPND_CHPNDG_Pos)\r
-\r
-/* VADC_BRSCTRL  =  Background Request Source Control Register*/\r
-#define   VADC_BRSCTRL_SRCRESREG_Pos   (0U)\r
-#define   VADC_BRSCTRL_SRCRESREG_Msk   (0x0000000FU  << VADC_BRSCTRL_SRCRESREG_Pos)\r
-\r
-#define   VADC_BRSCTRL_XTSEL_Pos       (8U)\r
-#define   VADC_BRSCTRL_XTSEL_Msk       (0x0000000FU  << VADC_BRSCTRL_XTSEL_Pos)\r
-\r
-#define   VADC_BRSCTRL_XTLVL_Pos       (12U)\r
-#define   VADC_BRSCTRL_XTLVL_Msk       (0x00000001U  << VADC_BRSCTRL_XTLVL_Pos)\r
-\r
-#define   VADC_BRSCTRL_XTMODE_Pos      (13U)\r
-#define   VADC_BRSCTRL_XTMODE_Msk      (0x00000003U  << VADC_BRSCTRL_XTMODE_Pos)\r
-\r
-#define   VADC_BRSCTRL_XTWC_Pos        (15U)\r
-#define   VADC_BRSCTRL_XTWC_Msk        (0x00000001U  << VADC_BRSCTRL_XTWC_Pos)\r
-\r
-#define   VADC_BRSCTRL_GTSEL_Pos       (16U)\r
-#define   VADC_BRSCTRL_GTSEL_Msk       (0x0000000FU  << VADC_BRSCTRL_GTSEL_Pos)\r
-\r
-#define   VADC_BRSCTRL_GTLVL_Pos       (20U)\r
-#define   VADC_BRSCTRL_GTLVL_Msk       (0x00000001U  << VADC_BRSCTRL_GTLVL_Pos)\r
-\r
-#define   VADC_BRSCTRL_GTWC_Pos        (23U)\r
-#define   VADC_BRSCTRL_GTWC_Msk        (0x00000001U  << VADC_BRSCTRL_GTWC_Pos)\r
-\r
-/* VADC_BRSMR  =  Background Request Source Mode Register*/\r
-#define   VADC_BRSMR_ENGT_Pos          (0U)\r
-#define   VADC_BRSMR_ENGT_Msk          (0x00000003U  << VADC_BRSMR_ENGT_Pos)\r
-\r
-#define   VADC_BRSMR_ENTR_Pos          (2U)\r
-#define   VADC_BRSMR_ENTR_Msk          (0x00000001U  << VADC_BRSMR_ENTR_Pos)\r
-\r
-#define   VADC_BRSMR_ENSI_Pos          (3U)\r
-#define   VADC_BRSMR_ENSI_Msk          (0x00000001U  << VADC_BRSMR_ENSI_Pos)\r
-\r
-#define   VADC_BRSMR_SCAN_Pos          (4U)\r
-#define   VADC_BRSMR_SCAN_Msk          (0x00000001U  << VADC_BRSMR_SCAN_Pos)\r
-\r
-#define   VADC_BRSMR_LDM_Pos   (5U)\r
-#define   VADC_BRSMR_LDM_Msk   (0x00000001U  << VADC_BRSMR_LDM_Pos)\r
-\r
-#define   VADC_BRSMR_REQGT_Pos         (7U)\r
-#define   VADC_BRSMR_REQGT_Msk         (0x00000001U  << VADC_BRSMR_REQGT_Pos)\r
-\r
-#define   VADC_BRSMR_CLRPND_Pos        (8U)\r
-#define   VADC_BRSMR_CLRPND_Msk        (0x00000001U  << VADC_BRSMR_CLRPND_Pos)\r
-\r
-#define   VADC_BRSMR_LDEV_Pos          (9U)\r
-#define   VADC_BRSMR_LDEV_Msk          (0x00000001U  << VADC_BRSMR_LDEV_Pos)\r
-\r
-#define   VADC_BRSMR_RPTDIS_Pos        (16U)\r
-#define   VADC_BRSMR_RPTDIS_Msk        (0x00000001U  << VADC_BRSMR_RPTDIS_Pos)\r
-\r
-/* VADC_GLOBRCR  =  Global Result Control Register*/\r
-#define   VADC_GLOBRCR_DRCTR_Pos       (16U)\r
-#define   VADC_GLOBRCR_DRCTR_Msk       (0x0000000FU  << VADC_GLOBRCR_DRCTR_Pos)\r
-\r
-#define   VADC_GLOBRCR_WFR_Pos         (24U)\r
-#define   VADC_GLOBRCR_WFR_Msk         (0x00000001U  << VADC_GLOBRCR_WFR_Pos)\r
-\r
-#define   VADC_GLOBRCR_SRGEN_Pos       (31U)\r
-#define   VADC_GLOBRCR_SRGEN_Msk       (0x00000001U  << VADC_GLOBRCR_SRGEN_Pos)\r
-\r
-/* VADC_GLOBRES  =  Global Result Register*/\r
-#define   VADC_GLOBRES_RESULT_Pos      (0U)\r
-#define   VADC_GLOBRES_RESULT_Msk      (0x0000FFFFU  << VADC_GLOBRES_RESULT_Pos)\r
-\r
-#define   VADC_GLOBRES_GNR_Pos         (16U)\r
-#define   VADC_GLOBRES_GNR_Msk         (0x0000000FU  << VADC_GLOBRES_GNR_Pos)\r
-\r
-#define   VADC_GLOBRES_CHNR_Pos        (20U)\r
-#define   VADC_GLOBRES_CHNR_Msk        (0x0000001FU  << VADC_GLOBRES_CHNR_Pos)\r
-\r
-#define   VADC_GLOBRES_EMUX_Pos        (25U)\r
-#define   VADC_GLOBRES_EMUX_Msk        (0x00000007U  << VADC_GLOBRES_EMUX_Pos)\r
-\r
-#define   VADC_GLOBRES_CRS_Pos         (28U)\r
-#define   VADC_GLOBRES_CRS_Msk         (0x00000003U  << VADC_GLOBRES_CRS_Pos)\r
-\r
-#define   VADC_GLOBRES_FCR_Pos         (30U)\r
-#define   VADC_GLOBRES_FCR_Msk         (0x00000001U  << VADC_GLOBRES_FCR_Pos)\r
-\r
-#define   VADC_GLOBRES_VF_Pos          (31U)\r
-#define   VADC_GLOBRES_VF_Msk          (0x00000001U  << VADC_GLOBRES_VF_Pos)\r
-\r
-/* VADC_GLOBRESD  =  Global Result Register, Debug*/\r
-#define   VADC_GLOBRESD_RESULT_Pos     (0U)\r
-#define   VADC_GLOBRESD_RESULT_Msk     (0x0000FFFFU  << VADC_GLOBRESD_RESULT_Pos)\r
-\r
-#define   VADC_GLOBRESD_GNR_Pos        (16U)\r
-#define   VADC_GLOBRESD_GNR_Msk        (0x0000000FU  << VADC_GLOBRESD_GNR_Pos)\r
-\r
-#define   VADC_GLOBRESD_CHNR_Pos       (20U)\r
-#define   VADC_GLOBRESD_CHNR_Msk       (0x0000001FU  << VADC_GLOBRESD_CHNR_Pos)\r
-\r
-#define   VADC_GLOBRESD_EMUX_Pos       (25U)\r
-#define   VADC_GLOBRESD_EMUX_Msk       (0x00000007U  << VADC_GLOBRESD_EMUX_Pos)\r
-\r
-#define   VADC_GLOBRESD_CRS_Pos        (28U)\r
-#define   VADC_GLOBRESD_CRS_Msk        (0x00000003U  << VADC_GLOBRESD_CRS_Pos)\r
-\r
-#define   VADC_GLOBRESD_FCR_Pos        (30U)\r
-#define   VADC_GLOBRESD_FCR_Msk        (0x00000001U  << VADC_GLOBRESD_FCR_Pos)\r
-\r
-#define   VADC_GLOBRESD_VF_Pos         (31U)\r
-#define   VADC_GLOBRESD_VF_Msk         (0x00000001U  << VADC_GLOBRESD_VF_Pos)\r
-\r
-/* VADC_EMUXSEL  =  External Multiplexer Select Register*/\r
-#define   VADC_EMUXSEL_EMUXGRP0_Pos    (0U)\r
-#define   VADC_EMUXSEL_EMUXGRP0_Msk    (0x0000000FU  << VADC_EMUXSEL_EMUXGRP0_Pos)\r
-\r
-#define   VADC_EMUXSEL_EMUXGRP1_Pos    (4U)\r
-#define   VADC_EMUXSEL_EMUXGRP1_Msk    (0x0000000FU  << VADC_EMUXSEL_EMUXGRP1_Pos)\r
-\r
-\r
-\r
-/***   WDT Bit Fileds *******************/\r
-/***************************************************************************/\r
-\r
-\r
-/* WDT_ID  =  WDT ID Register*/\r
-#define   WDT_ID_ID_Pos        (0U)\r
-#define   WDT_ID_ID_Msk        (0xFFFFFFFFU  << WDT_ID_ID_Pos)\r
-\r
-/* WDT_CTR  =  WDT Control Register*/\r
-#define   WDT_CTR_ENB_Pos      (0U)\r
-#define   WDT_CTR_ENB_Msk      (0x00000001U  << WDT_CTR_ENB_Pos)\r
-\r
-#define   WDT_CTR_PRE_Pos      (1U)\r
-#define   WDT_CTR_PRE_Msk      (0x00000001U  << WDT_CTR_PRE_Pos)\r
-\r
-#define   WDT_CTR_DSP_Pos      (4U)\r
-#define   WDT_CTR_DSP_Msk      (0x00000001U  << WDT_CTR_DSP_Pos)\r
-\r
-#define   WDT_CTR_SPW_Pos      (8U)\r
-#define   WDT_CTR_SPW_Msk      (0x000000FFU  << WDT_CTR_SPW_Pos)\r
-\r
-/* WDT_SRV  =  WDT Service Register*/\r
-#define   WDT_SRV_SRV_Pos      (0U)\r
-#define   WDT_SRV_SRV_Msk      (0xFFFFFFFFU  << WDT_SRV_SRV_Pos)\r
-\r
-/* WDT_TIM  =  WDT Timer Register*/\r
-#define   WDT_TIM_TIM_Pos      (0U)\r
-#define   WDT_TIM_TIM_Msk      (0xFFFFFFFFU  << WDT_TIM_TIM_Pos)\r
-\r
-/* WDT_WLB  =  WDT Window Lower Bound Register*/\r
-#define   WDT_WLB_WLB_Pos      (0U)\r
-#define   WDT_WLB_WLB_Msk      (0xFFFFFFFFU  << WDT_WLB_WLB_Pos)\r
-\r
-/* WDT_WUB  =  WDT Window Upper Bound Register*/\r
-#define   WDT_WUB_WUB_Pos      (0U)\r
-#define   WDT_WUB_WUB_Msk      (0xFFFFFFFFU  << WDT_WUB_WUB_Pos)\r
-\r
-/* WDT_WDTSTS  =  WDT Status Register*/\r
-#define   WDT_WDTSTS_ALMS_Pos          (0U)\r
-#define   WDT_WDTSTS_ALMS_Msk          (0x00000001U  << WDT_WDTSTS_ALMS_Pos)\r
-\r
-/* WDT_WDTCLR  =  WDT Clear Register*/\r
-#define   WDT_WDTCLR_ALMC_Pos          (0U)\r
-#define   WDT_WDTCLR_ALMC_Msk          (0x00000001U  << WDT_WDTCLR_ALMC_Pos)\r
-\r
-/********************************************\r
-** End of section using anonymous unions   **\r
-*********************************************/\r
-\r
-#if defined(__CC_ARM)\r
-  #pragma pop\r
-#elif defined(__ICCARM__)\r
-  /* leave anonymous unions enabled */\r
-#elif defined(__GNUC__)\r
-  /* anonymous unions are enabled by default */\r
-#elif defined(__TMS470__)\r
-  /* anonymous unions are enabled by default */\r
-#elif defined(__TASKING__)\r
-  #pragma warning restore\r
-#else\r
-   #warning Not supported compiler type\r
-#endif\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif  // ifndef __XMC4500_H__\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/startup/iar/vector_table_M_forXMC4500.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/startup/iar/vector_table_M_forXMC4500.s
deleted file mode 100644 (file)
index 7562398..0000000
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/startup/iar/vector_table_M_forXMC4500.s
+++ /dev/null
@@ -1,445 +0,0 @@
-;*************************************************\r
-;*\r
-;* Part one of the system initialization code, contains low-level\r
-;* initialization, plain thumb variant.\r
-;*\r
-;* Copyright 2008 IAR Systems. All rights reserved.\r
-;*\r
-;* $Revision: 50748 $\r
-;*\r
-;*************************************************\r
-\r
-;\r
-; The modules in this file are included in the libraries, and may be replaced\r
-; by any user-defined modules that define the PUBLIC symbol _program_start or\r
-; a user defined start symbol.\r
-; To override the cstartup defined in the library, simply add your modified\r
-; version to the workbench project.\r
-;\r
-; The vector table is normally located at address 0.\r
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
-; The name "__vector_table" has special meaning for C-SPY:\r
-; it is where the SP start value is found, and the NVIC vector\r
-; table register (VTOR) is initialized to this address if != 0.\r
-;\r
-; Cortex-M version with interrupt handler for XMC4500 from Infineon\r
-;\r
-\r
-        MODULE  ?vector_table\r
-\r
-        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE\r
-        PRESERVE8\r
-\r
-\r
-        ;; Forward declaration of sections.\r
-        SECTION CSTACK:DATA:NOROOT(3)\r
-\r
-        SECTION .intvec:CODE:NOROOT(2)\r
-\r
-        EXTERN  __iar_program_start\r
-        PUBLIC  __vector_table\r
-\r
-        DATA\r
-\r
-__iar_init$$done:               ; The vector table is not needed\r
-                                ; until after copy initialization is done\r
-\r
-__vector_table\r
-        DCD     sfe(CSTACK)\r
-        DCD     Reset_Handler\r
-\r
-        DCD     NMI_Handler\r
-        DCD     HardFault_Handler\r
-        DCD     MemManage_Handler\r
-        DCD     BusFault_Handler\r
-        DCD     UsageFault_Handler\r
-        DCD     0\r
-        DCD     0\r
-        DCD     0\r
-        DCD     0\r
-        DCD     SVC_Handler\r
-        DCD     DebugMon_Handler\r
-        DCD     0\r
-        DCD     PendSV_Handler\r
-        DCD     SysTick_Handler\r
-\r
-    ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals\r
-           DCD   SCU_0_IRQHandler            ; Handler name for SR SCU_0\r
-           DCD   ERU0_0_IRQHandler           ; Handler name for SR ERU0_0\r
-           DCD   ERU0_1_IRQHandler           ; Handler name for SR ERU0_1\r
-           DCD   ERU0_2_IRQHandler           ; Handler name for SR ERU0_2\r
-           DCD   ERU0_3_IRQHandler           ; Handler name for SR ERU0_3\r
-           DCD   ERU1_0_IRQHandler           ; Handler name for SR ERU1_0\r
-           DCD   ERU1_1_IRQHandler           ; Handler name for SR ERU1_1\r
-           DCD   ERU1_2_IRQHandler           ; Handler name for SR ERU1_2\r
-           DCD   ERU1_3_IRQHandler           ; Handler name for SR ERU1_3\r
-           DCD   0                           ; Not Available\r
-           DCD   0                           ; Not Available\r
-           DCD   0                           ; Not Available\r
-           DCD   PMU0_0_IRQHandler           ; Handler name for SR PMU0_0\r
-           DCD   0                           ; Not Available\r
-           DCD   VADC0_C0_0_IRQHandler       ; Handler name for SR VADC0_C0_0\r
-           DCD   VADC0_C0_1_IRQHandler       ; Handler name for SR VADC0_C0_1\r
-           DCD   VADC0_C0_2_IRQHandler       ; Handler name for SR VADC0_C0_1\r
-           DCD   VADC0_C0_3_IRQHandler       ; Handler name for SR VADC0_C0_3\r
-           DCD   VADC0_G0_0_IRQHandler       ; Handler name for SR VADC0_G0_0\r
-           DCD   VADC0_G0_1_IRQHandler       ; Handler name for SR VADC0_G0_1\r
-           DCD   VADC0_G0_2_IRQHandler       ; Handler name for SR VADC0_G0_2\r
-           DCD   VADC0_G0_3_IRQHandler       ; Handler name for SR VADC0_G0_3\r
-           DCD   VADC0_G1_0_IRQHandler       ; Handler name for SR VADC0_G1_0\r
-           DCD   VADC0_G1_1_IRQHandler       ; Handler name for SR VADC0_G1_1\r
-           DCD   VADC0_G1_2_IRQHandler       ; Handler name for SR VADC0_G1_2\r
-           DCD   VADC0_G1_3_IRQHandler       ; Handler name for SR VADC0_G1_3\r
-           DCD   VADC0_G2_0_IRQHandler       ; Handler name for SR VADC0_G2_0\r
-           DCD   VADC0_G2_1_IRQHandler       ; Handler name for SR VADC0_G2_1\r
-           DCD   VADC0_G2_2_IRQHandler       ; Handler name for SR VADC0_G2_2\r
-           DCD   VADC0_G2_3_IRQHandler       ; Handler name for SR VADC0_G2_3\r
-           DCD   VADC0_G3_0_IRQHandler       ; Handler name for SR VADC0_G3_0\r
-           DCD   VADC0_G3_1_IRQHandler       ; Handler name for SR VADC0_G3_1\r
-           DCD   VADC0_G3_2_IRQHandler       ; Handler name for SR VADC0_G3_2\r
-           DCD   VADC0_G3_3_IRQHandler       ; Handler name for SR VADC0_G3_3\r
-           DCD   DSD0_0_IRQHandler           ; Handler name for SR DSD0_0\r
-           DCD   DSD0_1_IRQHandler           ; Handler name for SR DSD0_1\r
-           DCD   DSD0_2_IRQHandler           ; Handler name for SR DSD0_2\r
-           DCD   DSD0_3_IRQHandler           ; Handler name for SR DSD0_3\r
-           DCD   DSD0_4_IRQHandler           ; Handler name for SR DSD0_4\r
-           DCD   DSD0_5_IRQHandler           ; Handler name for SR DSD0_5\r
-           DCD   DSD0_6_IRQHandler           ; Handler name for SR DSD0_6\r
-           DCD   DSD0_7_IRQHandler           ; Handler name for SR DSD0_7\r
-           DCD   DAC0_0_IRQHandler           ; Handler name for SR DAC0_0\r
-           DCD   DAC0_1_IRQHandler           ; Handler name for SR DAC0_0\r
-           DCD   CCU40_0_IRQHandler          ; Handler name for SR CCU40_0\r
-           DCD   CCU40_1_IRQHandler          ; Handler name for SR CCU40_1\r
-           DCD   CCU40_2_IRQHandler          ; Handler name for SR CCU40_2\r
-           DCD   CCU40_3_IRQHandler          ; Handler name for SR CCU40_3\r
-           DCD   CCU41_0_IRQHandler          ; Handler name for SR CCU41_0\r
-           DCD   CCU41_1_IRQHandler          ; Handler name for SR CCU41_1\r
-           DCD   CCU41_2_IRQHandler          ; Handler name for SR CCU41_2\r
-           DCD   CCU41_3_IRQHandler          ; Handler name for SR CCU41_3\r
-           DCD   CCU42_0_IRQHandler          ; Handler name for SR CCU42_0\r
-           DCD   CCU42_1_IRQHandler          ; Handler name for SR CCU42_1\r
-           DCD   CCU42_2_IRQHandler          ; Handler name for SR CCU42_2\r
-           DCD   CCU42_3_IRQHandler          ; Handler name for SR CCU42_3\r
-           DCD   CCU43_0_IRQHandler          ; Handler name for SR CCU43_0\r
-           DCD   CCU43_1_IRQHandler          ; Handler name for SR CCU43_1\r
-           DCD   CCU43_2_IRQHandler          ; Handler name for SR CCU43_2\r
-           DCD   CCU43_3_IRQHandler          ; Handler name for SR CCU43_3\r
-           DCD   CCU80_0_IRQHandler          ; Handler name for SR CCU80_0\r
-           DCD   CCU80_1_IRQHandler          ; Handler name for SR CCU80_1\r
-           DCD   CCU80_2_IRQHandler          ; Handler name for SR CCU80_2\r
-           DCD   CCU80_3_IRQHandler          ; Handler name for SR CCU80_3\r
-           DCD   CCU81_0_IRQHandler          ; Handler name for SR CCU81_0\r
-           DCD   CCU81_1_IRQHandler          ; Handler name for SR CCU81_1\r
-           DCD   CCU81_2_IRQHandler          ; Handler name for SR CCU81_2\r
-           DCD   CCU81_3_IRQHandler          ; Handler name for SR CCU81_3\r
-           DCD   POSIF0_0_IRQHandler         ; Handler name for SR POSIF0_0\r
-           DCD   POSIF0_1_IRQHandler         ; Handler name for SR POSIF0_1\r
-           DCD   POSIF1_0_IRQHandler         ; Handler name for SR POSIF1_0\r
-           DCD   POSIF1_1_IRQHandler         ; Handler name for SR POSIF1_1\r
-           DCD   0                           ; Not Available\r
-           DCD   0                           ; Not Available\r
-           DCD   0                           ; Not Available\r
-           DCD   0                           ; Not Available\r
-           DCD   CAN0_0_IRQHandler           ; Handler name for SR CAN0_0\r
-           DCD   CAN0_1_IRQHandler           ; Handler name for SR CAN0_1\r
-           DCD   CAN0_2_IRQHandler           ; Handler name for SR CAN0_2\r
-           DCD   CAN0_3_IRQHandler           ; Handler name for SR CAN0_3\r
-           DCD   CAN0_4_IRQHandler           ; Handler name for SR CAN0_4\r
-           DCD   CAN0_5_IRQHandler           ; Handler name for SR CAN0_5\r
-           DCD   CAN0_6_IRQHandler           ; Handler name for SR CAN0_6\r
-           DCD   CAN0_7_IRQHandler           ; Handler name for SR CAN0_7\r
-           DCD   USIC0_0_IRQHandler          ; Handler name for SR USIC0_0\r
-           DCD   USIC0_1_IRQHandler          ; Handler name for SR USIC0_1\r
-           DCD   USIC0_2_IRQHandler          ; Handler name for SR USIC0_2\r
-           DCD   USIC0_3_IRQHandler          ; Handler name for SR USIC0_3\r
-           DCD   USIC0_4_IRQHandler          ; Handler name for SR USIC0_4\r
-           DCD   USIC0_5_IRQHandler          ; Handler name for SR USIC0_5\r
-           DCD   USIC1_0_IRQHandler          ; Handler name for SR USIC1_0\r
-           DCD   USIC1_1_IRQHandler          ; Handler name for SR USIC1_1\r
-           DCD   USIC1_2_IRQHandler          ; Handler name for SR USIC1_2\r
-           DCD   USIC1_3_IRQHandler          ; Handler name for SR USIC1_3\r
-           DCD   USIC1_4_IRQHandler          ; Handler name for SR USIC1_4\r
-           DCD   USIC1_5_IRQHandler          ; Handler name for SR USIC1_5\r
-           DCD   USIC2_0_IRQHandler          ; Handler name for SR USIC2_0\r
-           DCD   USIC2_1_IRQHandler          ; Handler name for SR USIC2_1\r
-           DCD   USIC2_2_IRQHandler          ; Handler name for SR USIC2_2\r
-           DCD   USIC2_3_IRQHandler          ; Handler name for SR USIC2_3\r
-           DCD   USIC2_4_IRQHandler          ; Handler name for SR USIC2_4\r
-           DCD   USIC2_5_IRQHandler          ; Handler name for SR USIC2_5\r
-           DCD   LEDTS0_0_IRQHandler         ; Handler name for SR LEDTS0_0\r
-           DCD   0                           ; Not Available\r
-           DCD   FCE0_0_IRQHandler           ; Handler name for SR FCE0_0\r
-           DCD   GPDMA0_0_IRQHandler         ; Handler name for SR GPDMA0_0\r
-           DCD   SDMMC0_0_IRQHandler         ; Handler name for SR SDMMC0_0\r
-           DCD   USB0_0_IRQHandler           ; Handler name for SR USB0_0\r
-           DCD   ETH0_0_IRQHandler           ; Handler name for SR ETH0_0\r
-           DCD   0                           ; Not Available\r
-           DCD   GPDMA1_0_IRQHandler         ; Handler name for SR GPDMA1_0\r
-           DCD   0                           ; Not Available\r
-\r
-\r
-\r
-\r
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-;;\r
-;; Default interrupt handlers.\r
-;;\r
-\r
-        PUBWEAK NMI_Handler\r
-        PUBWEAK HardFault_Handler\r
-        PUBWEAK MemManage_Handler\r
-        PUBWEAK BusFault_Handler\r
-        PUBWEAK UsageFault_Handler\r
-        PUBWEAK SVC_Handler\r
-        PUBWEAK DebugMon_Handler\r
-        PUBWEAK PendSV_Handler\r
-        PUBWEAK SysTick_Handler\r
-;; XMC4500 interrupt handlers\r
-      PUBWEAK   SCU_0_IRQHandler\r
-           PUBWEAK   ERU0_0_IRQHandler\r
-           PUBWEAK   ERU0_1_IRQHandler\r
-           PUBWEAK   ERU0_2_IRQHandler\r
-           PUBWEAK   ERU0_3_IRQHandler\r
-           PUBWEAK   ERU1_0_IRQHandler\r
-           PUBWEAK   ERU1_1_IRQHandler\r
-           PUBWEAK   ERU1_2_IRQHandler\r
-           PUBWEAK   ERU1_3_IRQHandler\r
-           PUBWEAK   PMU0_0_IRQHandler\r
-           PUBWEAK   PMU0_1_IRQHandler\r
-           PUBWEAK   VADC0_C0_0_IRQHandler\r
-           PUBWEAK   VADC0_C0_1_IRQHandler\r
-           PUBWEAK   VADC0_C0_2_IRQHandler\r
-           PUBWEAK   VADC0_C0_3_IRQHandler\r
-           PUBWEAK   VADC0_G0_0_IRQHandler\r
-           PUBWEAK   VADC0_G0_1_IRQHandler\r
-           PUBWEAK   VADC0_G0_2_IRQHandler\r
-           PUBWEAK   VADC0_G0_3_IRQHandler\r
-           PUBWEAK   VADC0_G1_0_IRQHandler\r
-           PUBWEAK   VADC0_G1_1_IRQHandler\r
-           PUBWEAK   VADC0_G1_2_IRQHandler\r
-           PUBWEAK   VADC0_G1_3_IRQHandler\r
-           PUBWEAK   VADC0_G2_0_IRQHandler\r
-           PUBWEAK   VADC0_G2_1_IRQHandler\r
-           PUBWEAK   VADC0_G2_2_IRQHandler\r
-           PUBWEAK   VADC0_G2_3_IRQHandler\r
-           PUBWEAK   VADC0_G3_0_IRQHandler\r
-           PUBWEAK   VADC0_G3_1_IRQHandler\r
-           PUBWEAK   VADC0_G3_2_IRQHandler\r
-           PUBWEAK   VADC0_G3_3_IRQHandler\r
-           PUBWEAK   DSD0_0_IRQHandler\r
-           PUBWEAK   DSD0_1_IRQHandler\r
-           PUBWEAK   DSD0_2_IRQHandler\r
-           PUBWEAK   DSD0_3_IRQHandler\r
-           PUBWEAK   DSD0_4_IRQHandler\r
-           PUBWEAK   DSD0_5_IRQHandler\r
-           PUBWEAK   DSD0_6_IRQHandler\r
-           PUBWEAK   DSD0_7_IRQHandler\r
-           PUBWEAK   DAC0_0_IRQHandler\r
-           PUBWEAK   DAC0_1_IRQHandler\r
-           PUBWEAK   CCU40_0_IRQHandler\r
-           PUBWEAK   CCU40_1_IRQHandler\r
-           PUBWEAK   CCU40_2_IRQHandler\r
-           PUBWEAK   CCU40_3_IRQHandler\r
-           PUBWEAK   CCU41_0_IRQHandler\r
-           PUBWEAK   CCU41_1_IRQHandler\r
-           PUBWEAK   CCU41_2_IRQHandler\r
-           PUBWEAK   CCU41_3_IRQHandler\r
-           PUBWEAK   CCU42_0_IRQHandler\r
-           PUBWEAK   CCU42_1_IRQHandler\r
-           PUBWEAK   CCU42_2_IRQHandler\r
-           PUBWEAK   CCU42_3_IRQHandler\r
-           PUBWEAK   CCU43_0_IRQHandler\r
-           PUBWEAK   CCU43_1_IRQHandler\r
-           PUBWEAK   CCU43_2_IRQHandler\r
-           PUBWEAK   CCU43_3_IRQHandler\r
-           PUBWEAK   CCU80_0_IRQHandler\r
-           PUBWEAK   CCU80_1_IRQHandler\r
-           PUBWEAK   CCU80_2_IRQHandler\r
-           PUBWEAK   CCU80_3_IRQHandler\r
-           PUBWEAK   CCU81_0_IRQHandler\r
-           PUBWEAK   CCU81_1_IRQHandler\r
-           PUBWEAK   CCU81_2_IRQHandler\r
-           PUBWEAK   CCU81_3_IRQHandler\r
-           PUBWEAK   POSIF0_0_IRQHandler\r
-           PUBWEAK   POSIF0_1_IRQHandler\r
-           PUBWEAK   POSIF1_0_IRQHandler\r
-           PUBWEAK   POSIF1_1_IRQHandler\r
-           PUBWEAK   CAN0_0_IRQHandler\r
-           PUBWEAK   CAN0_1_IRQHandler\r
-           PUBWEAK   CAN0_2_IRQHandler\r
-           PUBWEAK   CAN0_3_IRQHandler\r
-           PUBWEAK   CAN0_4_IRQHandler\r
-           PUBWEAK   CAN0_5_IRQHandler\r
-           PUBWEAK   CAN0_6_IRQHandler\r
-           PUBWEAK   CAN0_7_IRQHandler\r
-           PUBWEAK   USIC0_0_IRQHandler\r
-           PUBWEAK   USIC0_1_IRQHandler\r
-           PUBWEAK   USIC0_2_IRQHandler\r
-           PUBWEAK   USIC0_3_IRQHandler\r
-           PUBWEAK   USIC0_4_IRQHandler\r
-           PUBWEAK   USIC0_5_IRQHandler\r
-           PUBWEAK   USIC1_0_IRQHandler\r
-           PUBWEAK   USIC1_1_IRQHandler\r
-           PUBWEAK   USIC1_2_IRQHandler\r
-           PUBWEAK   USIC1_3_IRQHandler\r
-           PUBWEAK   USIC1_4_IRQHandler\r
-           PUBWEAK   USIC1_5_IRQHandler\r
-           PUBWEAK   USIC2_0_IRQHandler\r
-           PUBWEAK   USIC2_1_IRQHandler\r
-           PUBWEAK   USIC2_2_IRQHandler\r
-           PUBWEAK   USIC2_3_IRQHandler\r
-           PUBWEAK   USIC2_4_IRQHandler\r
-           PUBWEAK   USIC2_5_IRQHandler\r
-           PUBWEAK   LEDTS0_0_IRQHandler\r
-           PUBWEAK   FCE0_0_IRQHandler\r
-           PUBWEAK   GPDMA0_0_IRQHandler\r
-           PUBWEAK   SDMMC0_0_IRQHandler\r
-           PUBWEAK   USB0_0_IRQHandler\r
-           PUBWEAK   ETH0_0_IRQHandler\r
-           PUBWEAK   GPDMA1_0_IRQHandler\r
-\r
-        SECTION .text:CODE:REORDER(2)\r
-        THUMB\r
-\r
-NMI_Handler\r
-HardFault_Handler\r
-MemManage_Handler\r
-BusFault_Handler\r
-UsageFault_Handler\r
-SVC_Handler\r
-DebugMon_Handler\r
-PendSV_Handler\r
-SysTick_Handler\r
-\r
-SCU_0_IRQHandler\r
-ERU0_0_IRQHandler\r
-ERU0_1_IRQHandler\r
-ERU0_2_IRQHandler\r
-ERU0_3_IRQHandler\r
-ERU1_0_IRQHandler\r
-ERU1_1_IRQHandler\r
-ERU1_2_IRQHandler\r
-ERU1_3_IRQHandler\r
-PMU0_0_IRQHandler\r
-PMU0_1_IRQHandler\r
-VADC0_C0_0_IRQHandler\r
-VADC0_C0_1_IRQHandler\r
-VADC0_C0_2_IRQHandler\r
-VADC0_C0_3_IRQHandler\r
-VADC0_G0_0_IRQHandler\r
-VADC0_G0_1_IRQHandler\r
-VADC0_G0_2_IRQHandler\r
-VADC0_G0_3_IRQHandler\r
-VADC0_G1_0_IRQHandler\r
-VADC0_G1_1_IRQHandler\r
-VADC0_G1_2_IRQHandler\r
-VADC0_G1_3_IRQHandler\r
-VADC0_G2_0_IRQHandler\r
-VADC0_G2_1_IRQHandler\r
-VADC0_G2_2_IRQHandler\r
-VADC0_G2_3_IRQHandler\r
-VADC0_G3_0_IRQHandler\r
-VADC0_G3_1_IRQHandler\r
-VADC0_G3_2_IRQHandler\r
-VADC0_G3_3_IRQHandler\r
-DSD0_0_IRQHandler\r
-DSD0_1_IRQHandler\r
-DSD0_2_IRQHandler\r
-DSD0_3_IRQHandler\r
-DSD0_4_IRQHandler\r
-DSD0_5_IRQHandler\r
-DSD0_6_IRQHandler\r
-DSD0_7_IRQHandler\r
-DAC0_0_IRQHandler\r
-DAC0_1_IRQHandler\r
-CCU40_0_IRQHandler\r
-CCU40_1_IRQHandler\r
-CCU40_2_IRQHandler\r
-CCU40_3_IRQHandler\r
-CCU41_0_IRQHandler\r
-CCU41_1_IRQHandler\r
-CCU41_2_IRQHandler\r
-CCU41_3_IRQHandler\r
-CCU42_0_IRQHandler\r
-CCU42_1_IRQHandler\r
-CCU42_2_IRQHandler\r
-CCU42_3_IRQHandler\r
-CCU43_0_IRQHandler\r
-CCU43_1_IRQHandler\r
-CCU43_2_IRQHandler\r
-CCU43_3_IRQHandler\r
-CCU80_0_IRQHandler\r
-CCU80_1_IRQHandler\r
-CCU80_2_IRQHandler\r
-CCU80_3_IRQHandler\r
-CCU81_0_IRQHandler\r
-CCU81_1_IRQHandler\r
-CCU81_2_IRQHandler\r
-CCU81_3_IRQHandler\r
-POSIF0_0_IRQHandler\r
-POSIF0_1_IRQHandler\r
-POSIF1_0_IRQHandler\r
-POSIF1_1_IRQHandler\r
-CAN0_0_IRQHandler\r
-CAN0_1_IRQHandler\r
-CAN0_2_IRQHandler\r
-CAN0_3_IRQHandler\r
-CAN0_4_IRQHandler\r
-CAN0_5_IRQHandler\r
-CAN0_6_IRQHandler\r
-CAN0_7_IRQHandler\r
-USIC0_0_IRQHandler\r
-USIC0_1_IRQHandler\r
-USIC0_2_IRQHandler\r
-USIC0_3_IRQHandler\r
-USIC0_4_IRQHandler\r
-USIC0_5_IRQHandler\r
-USIC1_0_IRQHandler\r
-USIC1_1_IRQHandler\r
-USIC1_2_IRQHandler\r
-USIC1_3_IRQHandler\r
-USIC1_4_IRQHandler\r
-USIC1_5_IRQHandler\r
-USIC2_0_IRQHandler\r
-USIC2_1_IRQHandler\r
-USIC2_2_IRQHandler\r
-USIC2_3_IRQHandler\r
-USIC2_4_IRQHandler\r
-USIC2_5_IRQHandler\r
-LEDTS0_0_IRQHandler\r
-FCE0_0_IRQHandler\r
-GPDMA0_0_IRQHandler\r
-SDMMC0_0_IRQHandler\r
-USB0_0_IRQHandler\r
-ETH0_0_IRQHandler\r
-GPDMA1_0_IRQHandler\r
-\r
-Default_Handler\r
-        NOCALL Default_Handler\r
-        B Default_Handler\r
-\r
-PREF_PCON       EQU 0x58004000\r
-SCU_GCU_PEEN    EQU 0x5000413C\r
-SCU_GCU_PEFLAG  EQU 0x50004150\r
-\r
-        SECTION .text:CODE:REORDER(2)\r
-        THUMB\r
-Reset_Handler:\r
-        ; A11 workaround for branch prediction and parity\r
-        LDR R0,=PREF_PCON        /* switch off branch prediction required in A11 step to use cached memory*/\r
-        LDR R1,[R0]\r
-        ORR R1,R1,#0x00010000\r
-        STR R1,[R0]\r
-\r
-        /* Clear existing parity errors if any required in A11 step */\r
-        LDR R0,=SCU_GCU_PEFLAG\r
-        MOV R1,#0xFFFFFFFF\r
-        STR R1,[R0]\r
-\r
-        /* Disable parity  required in A11 step*/\r
-        LDR R0,=SCU_GCU_PEEN\r
-        MOV R1,#0\r
-        STR R1,[R0]\r
-        B __iar_program_start\r
-        \r
-        END\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/system_XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/system_XMC4500.h
deleted file mode 100644 (file)
index 6149d30..0000000
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/system_XMC4500.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/**************************************************************************//**\r
- * @file     system_XMC4500.h\r
- * @brief    Header file for the XMC4500-Series systeminit\r
- *           \r
- * @version  V1.4\r
- * @date     31. Januar 2012\r
- *\r
- * @note\r
- * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.\r
-\r
- *\r
- * @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon\92s microcontrollers.  \r
- * This file can be freely distributed within development tools that are supporting such microcontrollers. \r
-\r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- *\r
- ******************************************************************************/\r
-\r
-\r
-#ifndef __SYSTEM_XMC4500_H\r
-#define __SYSTEM_XMC4500_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-#include <stdint.h>\r
-\r
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\r
-\r
-/**\r
- * Initialize the system\r
- *\r
- * @param  none\r
- * @return none\r
- *\r
- * @brief  Setup the microcontroller system.\r
- *         Initialize the System.\r
- */\r
-extern void SystemInit (void);\r
-\r
-\r
-/**\r
- * Update SystemCoreClock variable\r
- *\r
- * @param  none\r
- * @return none\r
- *\r
- * @brief  Updates the SystemCoreClock with current core Clock\r
- *         retrieved from cpu registers.\r
- */\r
-extern void SystemCoreClockUpdate (void);\r
-\r
-\r
-/* clock definitions, do not modify! */\r
-#define SCU_CLOCK_CRYSTAL              1\r
-\r
-                               \r
-                               \r
-/*                             \r
- * mandatory clock parameters **************************************************                               \r
- */                            \r
-/* source for clock generation                         \r
- * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)                               \r
- *                                     \r
- **************************************************************************************/                               \r
-                               \r
-#define        SCU_PLL_CLOCK_INPUT     SCU_CLOCK_CRYSTAL\r
-#define CLOCK_OSC_HP   24000000                         \r
-#define        CLOCK_CRYSTAL_FREQUENCY 12000000                \r
-#define        SYSTEM_FREQUENCY        120000000               \r
-                               \r
-/* OSC_HP setup parameters */                          \r
-#define        OSC_HP_MODE     0               \r
-#define OSCHPWDGDIV 2\r
-                               \r
-/* MAIN PLL setup parameters */                                \r
-                               \r
-                               \r
-#define        PLL_K1DIV       1               \r
-#define        PLL_K2DIV       3               \r
-#define        PLL_PDIV        1               \r
-#define        PLL_NDIV        79\r
-               \r
-                               \r
-                               \r
-#define        PLL_K2DIV_STEP_1        19      //PLL output is 24Mhz   \r
-#define        PLL_K2DIV_STEP_2        7       //PLL output to 60Mhz   \r
-#define        PLL_K2DIV_STEP_3        4       //PLL output to 96Mhz   \r
-                               \r
-                               \r
-               \r
-#define        USBPLL_PDIV     1               \r
-#define        USBPLL_NDIV     15              \r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4200.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4200.c
new file mode 100644 (file)
index 0000000..d2385b4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4200.c
@@ -0,0 +1,708 @@
+/**************************************************************************//**\r
+ * @file     system_XMC4200.c\r
+ * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ *           for the Infineon XMC4000 Device Series\r
+ * @version  V3.0.1 Alpha\r
+ * @date     26. September 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <system_XMC4200.h>\r
+#include <XMC4200.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL                      1\r
+#define SCU_CLOCK_BACK_UP_FACTORY                      2\r
+#define SCU_CLOCK_BACK_UP_AUTOMATIC            3\r
+\r
+\r
+#define HIB_CLOCK_FOSI                                 1                                \r
+#define HIB_CLOCK_OSCULP                               2\r
+\r
+\r
+\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+\r
+\r
+/*--------------------- Watchdog Configuration -------------------------------\r
+//\r
+// <e> Watchdog Configuration\r
+//     <o1.0> Disable Watchdog\r
+//\r
+// </e>\r
+*/\r
+#define WDT_SETUP               1\r
+#define WDTENB_nVal             0x00000001\r
+\r
+/*--------------------- CLOCK Configuration -------------------------------\r
+//\r
+// <e> Main Clock Configuration\r
+//     <o1.0..1> CPU clock divider\r
+//                     <0=> fCPU = fSYS \r
+//                     <1=> fCPU = fSYS / 2\r
+//     <o2.0..1>  Peripheral Bus clock divider\r
+//                     <0=> fPB        = fCPU\r
+//                     <1=> fPB        = fCPU / 2\r
+//     <o3.0..1>  CCU Bus clock divider\r
+//                     <0=> fCCU = fCPU\r
+//                     <1=> fCCU = fCPU / 2\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCK_SETUP               1\r
+#define        SCU_CPUCLKCR_DIV                0x00000000\r
+#define        SCU_PBCLKCR_DIV             0x00000000\r
+#define        SCU_CCUCLKCR_DIV                0x00000000\r
+/* not avalible in config wizzard*/\r
+/*                             \r
+* mandatory clock parameters **************************************************                                \r
+*                              \r
+* source for clock generation                          \r
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)                                \r
+*                              \r
+**************************************************************************************/                                \r
+// Selection of imput lock for PLL     \r
+/*************************************************************************************/\r
+#define        SCU_PLL_CLOCK_INPUT     SCU_CLOCK_CRYSTAL\r
+//#define      SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_FACTORY\r
+//#define      SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_AUTOMATIC\r
+\r
+/*************************************************************************************/\r
+// Standby clock selection for Backup clock source trimming\r
+/*************************************************************************************/\r
+#define        SCU_STANDBY_CLOCK  HIB_CLOCK_OSCULP\r
+//#define      SCU_STANDBY_CLOCK  HIB_CLOCK_FOSI\r
+\r
+/*************************************************************************************/\r
+// Global clock parameters\r
+/*************************************************************************************/\r
+#define CLOCK_FSYS                                                     80000000\r
+#define        CLOCK_CRYSTAL_FREQUENCY 12000000                \r
+#define        CLOCK_BACK_UP                                           24000000                \r
+                               \r
+/*************************************************************************************/\r
+/* OSC_HP setup parameters */                          \r
+/*************************************************************************************/\r
+#define        SCU_OSC_HP_MODE 0xF0\r
+#define        SCU_OSCHPWDGDIV 2               \r
+                               \r
+/*************************************************************************************/\r
+/* MAIN PLL setup parameters */                                \r
+/*************************************************************************************/\r
+//Divider settings for external crystal @ 12 MHz \r
+/*************************************************************************************/\r
+#define        SCU_PLL_K1DIV   1\r
+#define        SCU_PLL_K1DIV   1               \r
+#define        SCU_PLL_K2DIV   5               \r
+#define        SCU_PLL_PDIV    1               \r
+#define        SCU_PLL_NDIV    79              \r
+                               \r
+/*************************************************************************************/\r
+//Divider settings for use of backup clock source trimmed\r
+/*************************************************************************************/\r
+//#define      SCU_PLL_K1DIV   1               \r
+//#define      SCU_PLL_K2DIV   5               \r
+//#define      SCU_PLL_PDIV    3               \r
+//#define      SCU_PLL_NDIV    79              \r
+/*************************************************************************************/\r
+       \r
+\r
+/*--------------------- USB CLOCK Configuration ---------------------------\r
+//\r
+// <e> USB Clock Configuration\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_USB_CLOCK_SETUP              0\r
+/* not avalible in config wizzard*/\r
+#define        SCU_USBPLL_PDIV 0               \r
+#define        SCU_USBPLL_NDIV 31              \r
+#define        SCU_USBDIV      3               \r
+\r
+/*--------------------- Flash Wait State Configuration -------------------------------\r
+//\r
+// <e> Flash Wait State Configuration\r
+//     <o1.0..3>   Flash Wait State\r
+//                     <0=> 3 WS\r
+//                     <1=> 4 WS\r
+//                     <2=> 5 WS     \r
+//                                                                              <3=> 6 WS\r
+// </e>\r
+// \r
+*/\r
+\r
+#define PMU_FLASH             1\r
+#define        PMU_FLASH_WS                                    0x00000000\r
+\r
+\r
+/*--------------------- CLOCKOUT Configuration -------------------------------\r
+//\r
+// <e> Clock OUT Configuration\r
+//     <o1.0..1>   Clockout Source Selection\r
+//                     <0=> System Clock\r
+//                     <2=> Divided value of USB PLL output\r
+//                     <3=> Divided value of PLL Clock\r
+//     <o2.0..4>   Clockout divider <1-10><#-1>\r
+//     <o3.0..1>   Clockout Pin Selection\r
+//                     <0=> P1.15\r
+//                     <1=> P0.8\r
+//                     \r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCKOUT_SETUP               0\r
+#define        SCU_CLOCKOUT_SOURCE             0x00000000\r
+#define        SCU_CLOCKOUT_DIV                0x00000009\r
+#define        SCU_CLOCKOUT_PIN                0x00000001\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+#if SCU_CLOCK_SETUP\r
+uint32_t SystemCoreClock = CLOCK_FSYS;\r
+#else\r
+uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+  static functions declarations\r
+ *----------------------------------------------------------------------------*/\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void);\r
+#endif\r
+\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void);\r
+#endif\r
+\r
+\r
+/**\r
+  * @brief  Setup the microcontroller system.\r
+  *         Initialize the PLL and update the \r
+  *         SystemCoreClock variable.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemInit(void)\r
+{\r
+int temp;\r
+       \r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */\r
+               (3UL << 11*2)  );               /* set CP11 Full Access */\r
+#endif\r
+       \r
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
+       \r
+/* Setup the WDT */\r
+#if WDT_SETUP\r
+\r
+WDT->CTR &= ~WDTENB_nVal; \r
+\r
+#endif\r
+\r
+\r
+/* Setup the Flash Wait State */\r
+#if PMU_FLASH\r
+temp = FLASH0->FCON; \r
+temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
+temp |= PMU_FLASH_WS+3;\r
+FLASH0->FCON = temp;\r
+#endif\r
+\r
+       \r
+/* Setup the clockout */\r
+#if SCU_CLOCKOUT_SETUP\r
+\r
+SCU_CLK->EXTCLKCR      |= SCU_CLOCKOUT_SOURCE;\r
+/*set PLL div for clkout */\r
+SCU_CLK->EXTCLKCR      |= SCU_CLOCKOUT_DIV<<16;\r
+\r
+if (SCU_CLOCKOUT_PIN) {\r
+                                               PORT0->IOCR8 = 0x00000088;   /*P0.8 --> ALT1 select +  HWSEL */\r
+                                           PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+                                           PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk);  /*set to strong driver */\r
+                                               }\r
+else {\r
+               PORT1->IOCR12 = 0x88000000;                    /*P1.15--> ALT1 select */\r
+           PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk);  /*set to strong driver */\r
+               }\r
+\r
+#endif\r
+\r
+\r
+/* Setup the System clock */ \r
+#if SCU_CLOCK_SETUP\r
+SystemClockSetup();\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/* Setup the USB PL */ \r
+#if SCU_USB_CLOCK_SETUP\r
+USBClockSetup();\r
+#endif\r
+\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Update SystemCoreClock according to Clock Register Values\r
+  * @note   -  \r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+unsigned int PDIV;\r
+unsigned int NDIV;\r
+unsigned int K2DIV;\r
+unsigned int long VCO;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+if (SCU_CLK->SYSCLKCR ==  0x00010000)\r
+{\r
+       if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
+               /* check if PLL is locked */\r
+               /* read back divider settings */\r
+                PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
+                NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
+                K2DIV  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
+\r
+               if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
+               /* the selected clock is the Backup clock fofi */\r
+               VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
+               SystemCoreClock = VCO/K2DIV;\r
+               /* in case the sysclock div is used */\r
+               SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+               \r
+               }\r
+               else\r
+               {\r
+               /* the selected clock is the PLL external oscillator */         \r
+               VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
+               SystemCoreClock = VCO/K2DIV;\r
+               /* in case the sysclock div is used */\r
+               SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+               } \r
+       \r
+       \r
+       }\r
+}\r
+else\r
+{\r
+SystemCoreClock = CLOCK_BACK_UP;\r
+}\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+  * @brief  -\r
+  * @note   -  \r
+  * @param  None\r
+  * @retval None\r
+  */\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void)\r
+{\r
+int temp;\r
+unsigned int long VCO;\r
+int stepping_K2DIV;    \r
+\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+        \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+/* enable PLL first */\r
+  SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+\r
+} \r
+\r
+/* Enable OSC_HP if not already on*/\r
+  if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
+  {\r
+       /********************************************************************************************************************/\r
+       /*   Use external crystal for PLL clock input                                                                            */\r
+       /********************************************************************************************************************/\r
+\r
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+          SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
+          /* setup OSC WDG devider */\r
+          SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);         \r
+          /* select external OSC as PLL input */\r
+          SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+          /* restart OSC Watchdog */\r
+          SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
+\r
+       /* Timeout for wait loop ~150ms */\r
+          /********************************/\r
+          SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
+          do \r
+          {\r
+       ;/* wait for ~150ms  */\r
+          }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+          return(0);/* Return Error */\r
+\r
+    }\r
+  }\r
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
+       {\r
+       /********************************************************************************************************************/\r
+       /*   Use factory trimming Back-up clock for PLL clock input                                                                            */\r
+       /********************************************************************************************************************/\r
+               /* PLL Back up clock selected */\r
+               SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+                       \r
+       }\r
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
+  {\r
+       /********************************************************************************************************************/\r
+       /*   Use automatic trimming Back-up clock for PLL clock input                                                                            */\r
+       /********************************************************************************************************************/\r
+       /* check for HIB Domain enabled  */\r
+       if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
+               SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
+\r
+   /* check for HIB Domain is not in reset state  */\r
+       if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
+           SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
+\r
+                       /* PLL Back up clock selected */\r
+               SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+       \r
+               if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
+                       {\r
+                       /****************************************************************************************************************/\r
+                       /*   Use fOSI as source of the standby clock                                                                             */\r
+                       /****************************************************************************************************************/\r
+                       SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+                       \r
+                       SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+                       for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+                       SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+                       }\r
+               else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
+                       {\r
+                       /****************************************************************************************************************/\r
+                       /*   Use fULP as source of the standby clock                                                                            */\r
+                       /****************************************************************************************************************/\r
+                       /*check OSCUL if running correct*/\r
+                       if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
+                               {\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
+\r
+                                       SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
+                                       /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
+                                       /* select OSCUL clock for RTC*/\r
+                                       SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+                                       /*enable OSCULP WDG Alarm Enable*/\r
+                                       SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+                                       /*wait now for clock is stable */\r
+                                       do\r
+                                       {\r
+                                       SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+                                       for(temp=0;temp<=0xFFFF;temp++);\r
+                                       }\r
+                                       while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); \r
+\r
+                                       SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+                               }       \r
+                       // now OSCULP is running and can be used                 \r
+                       SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+                       \r
+                       SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+                       /*TRIAL for delay loop*/\r
+                       for(temp=0;temp<=0xFFFF;temp++);\r
+                       \r
+                       SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+                       /*TRIAL for delay loop*/\r
+                       for(temp=0;temp<=0xFFFF;temp++);\r
+                       \r
+                       }\r
+  }\r
+\r
+       /********************************************************************************************************************/\r
+       /*   Setup and look the main PLL                                                                                    */\r
+       /********************************************************************************************************************/\r
+\r
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
+       /* Systen is still running from internal clock */\r
+                  /* select FOFI as system clock */\r
+                  if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
+\r
+\r
+                        /*calulation for stepping*/\r
+                        if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+                        if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+                                       VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+        \r
+                        stepping_K2DIV = (VCO/24000000)-1;     \r
+                        /* Go to bypass the Main PLL */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+                  /* disconnect OSC_HP to PLL */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+                  /* Setup devider settings for main PLL */\r
+                  SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                  /* we may have to set OSCDISCDIS */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+                  /* connect OSC_HP to PLL */\r
+                  SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+                  /* restart PLL Lock detection */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+                  /* wait for PLL Lock */\r
+                  /* setup time out loop */\r
+              /* Timeout for wait loo ~150ms */\r
+                  /********************************/\r
+                  SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+                  SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+                  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                                  SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
+                  \r
+                  while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
+              SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+\r
+                  if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
+                               {\r
+                               /* Go back to the Main PLL */\r
+                               SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+                               }\r
+                               else return(0);\r
+                \r
+       \r
+          /*********************************************************\r
+          here we need to setup the system clock divider\r
+          *********************************************************/\r
+       \r
+               SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+               SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;     \r
+               SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+       \r
+\r
+               /* Switch system clock to PLL */\r
+          SCU_CLK->SYSCLKCR |=  0x00010000; \r
+                               \r
+          /* we may have to reset OSCDISCDIS */\r
+          SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+                               \r
+                                                                                                                                 \r
+                /*********************************************************/\r
+                /* Delay for next K2 step ~50µs */\r
+                /*********************************************************/\r
+                SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+                SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+                SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                                                                                SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
+       \r
+                while (SysTick->VAL >= 100);                                                              /* wait for ~50µs  */\r
+                SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+                /*********************************************************/\r
+\r
+          /*********************************************************\r
+          here the ramp up of the system clock starts FSys < 60MHz\r
+          *********************************************************/\r
+               if (CLOCK_FSYS > 60000000){\r
+                        /*calulation for stepping*/\r
+                        if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+                        if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+                                       VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+        \r
+                        stepping_K2DIV = (VCO/60000000)-1;     \r
+\r
+                        /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                }\r
+                else\r
+                {\r
+                               /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                   SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
+                         return(1);\r
+                }\r
+\r
+                /*********************************************************/\r
+                /* Delay for next K2 step ~50µs */\r
+                /*********************************************************/\r
+          SysTick->LOAD  = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
+       \r
+          while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          /********************************/\r
+       \r
+   /*********************************************************\r
+          here the ramp up of the system clock starts FSys < 90MHz\r
+          *********************************************************/\r
+               if (CLOCK_FSYS > 90000000){\r
+                        /*calulation for stepping*/\r
+                        if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+                        if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+                                       VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+                        stepping_K2DIV = (VCO/90000000)-1;                     \r
+\r
+                        /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                }\r
+                else\r
+                {\r
+                               /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+             SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
+                               return(1);\r
+                }\r
+       \r
+                /*********************************************************/\r
+                /* Delay for next K2 step ~50µs */\r
+                /*********************************************************/\r
+          SysTick->LOAD  = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
+       \r
+          while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          /********************************/\r
+       \r
+          /* Setup devider settings for main PLL */\r
+          SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+       \r
+          SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
+       }\r
+ }/* end this weak function enables DAVE3 clock App usage */   \r
+   return(1);\r
+\r
+}\r
+#endif\r
+\r
+/**\r
+  * @brief  -\r
+  * @note   -  \r
+  * @param  None\r
+  * @retval None\r
+  */\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void)\r
+{\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+       \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
+       /* enable PLL first */\r
+  SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+}\r
+\r
+/* check and if not already running enable OSC_HP */\r
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+                /* check if Main PLL is switched on for OSC WD*/\r
+                if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+                       /* enable PLL first */\r
+                       SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+                }\r
+          SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
+          /* setup OSC WDG devider */\r
+          SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);         \r
+          /* restart OSC Watchdog */\r
+          SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
+       \r
+       /* Timeout for wait loop ~150ms */\r
+          /********************************/\r
+          SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
+          do \r
+          {\r
+       ;/* wait for ~150ms  */\r
+          }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+          return(0);/* Return Error */\r
+       \r
+  }\r
+\r
+\r
+/* Setup USB PLL */\r
+   /* Go to bypass the Main PLL */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
+   /* disconnect OSC_FI to PLL */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+   /* Setup devider settings for main PLL */\r
+   SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
+   /* Setup USBDIV settings USB clock */\r
+   SCU_CLK->USBCLKCR = SCU_USBDIV;\r
+   /* we may have to set OSCDISCDIS */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
+   /* connect OSC_FI to PLL */\r
+   SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+   /* restart PLL Lock detection */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
+   /* wait for PLL Lock */\r
+   while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
+   \r
+ }/* end this weak function enables DAVE3 clock App usage */   \r
+   return(1);\r
+\r
+}\r
+#endif\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4400.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4400.c
new file mode 100644 (file)
index 0000000..70162d9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4400.c
@@ -0,0 +1,707 @@
+/**************************************************************************//**\r
+ * @file     system_XMC4400.c\r
+ * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ *           for the Infineon XMC4500 Device Series\r
+ * @version  V3.0.1 Alpha\r
+ * @date     17. September 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <system_XMC4400.h>\r
+#include <XMC4400.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL                      1\r
+#define SCU_CLOCK_BACK_UP_FACTORY                      2\r
+#define SCU_CLOCK_BACK_UP_AUTOMATIC            3\r
+\r
+\r
+#define HIB_CLOCK_FOSI                                 1                                \r
+#define HIB_CLOCK_OSCULP                               2\r
+\r
+\r
+\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+\r
+\r
+/*--------------------- Watchdog Configuration -------------------------------\r
+//\r
+// <e> Watchdog Configuration\r
+//     <o1.0> Disable Watchdog\r
+//\r
+// </e>\r
+*/\r
+#define WDT_SETUP               1\r
+#define WDTENB_nVal             0x00000001\r
+\r
+/*--------------------- CLOCK Configuration -------------------------------\r
+//\r
+// <e> Main Clock Configuration\r
+//     <o1.0..1> CPU clock divider\r
+//                     <0=> fCPU = fSYS \r
+//                     <1=> fCPU = fSYS / 2\r
+//     <o2.0..1>  Peripheral Bus clock divider\r
+//                     <0=> fPB        = fCPU\r
+//                     <1=> fPB        = fCPU / 2\r
+//     <o3.0..1>  CCU Bus clock divider\r
+//                     <0=> fCCU = fCPU\r
+//                     <1=> fCCU = fCPU / 2\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCK_SETUP               1\r
+#define        SCU_CPUCLKCR_DIV                0x00000000\r
+#define        SCU_PBCLKCR_DIV             0x00000000\r
+#define        SCU_CCUCLKCR_DIV                0x00000000\r
+/* not avalible in config wizzard*/\r
+/*                             \r
+* mandatory clock parameters **************************************************                                \r
+*                              \r
+* source for clock generation                          \r
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)                                \r
+*                              \r
+**************************************************************************************/                                \r
+// Selection of imput lock for PLL     \r
+/*************************************************************************************/\r
+#define        SCU_PLL_CLOCK_INPUT     SCU_CLOCK_CRYSTAL\r
+//#define      SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_FACTORY\r
+//#define      SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_AUTOMATIC\r
+\r
+/*************************************************************************************/\r
+// Standby clock selection for Backup clock source trimming\r
+/*************************************************************************************/\r
+#define        SCU_STANDBY_CLOCK  HIB_CLOCK_OSCULP\r
+//#define      SCU_STANDBY_CLOCK  HIB_CLOCK_FOSI\r
+\r
+/*************************************************************************************/\r
+// Global clock parameters\r
+/*************************************************************************************/\r
+#define CLOCK_FSYS                                                     120000000\r
+#define        CLOCK_CRYSTAL_FREQUENCY 12000000                \r
+#define        CLOCK_BACK_UP                                           24000000                \r
+                               \r
+/*************************************************************************************/\r
+/* OSC_HP setup parameters */                          \r
+/*************************************************************************************/\r
+#define        SCU_OSC_HP_MODE 0xF0\r
+#define        SCU_OSCHPWDGDIV 2               \r
+                               \r
+/*************************************************************************************/\r
+/* MAIN PLL setup parameters */                                \r
+/*************************************************************************************/\r
+//Divider settings for external crystal @ 12 MHz \r
+/*************************************************************************************/\r
+#define        SCU_PLL_K1DIV   1\r
+#define        SCU_PLL_K2DIV   3\r
+#define        SCU_PLL_PDIV    1\r
+#define        SCU_PLL_NDIV    79\r
+                               \r
+/*************************************************************************************/\r
+//Divider settings for use of backup clock source trimmed\r
+/*************************************************************************************/\r
+//#define      SCU_PLL_K1DIV   1               \r
+//#define      SCU_PLL_K2DIV   3               \r
+//#define      SCU_PLL_PDIV    3               \r
+//#define      SCU_PLL_NDIV    79              \r
+/*************************************************************************************/\r
+       \r
+\r
+/*--------------------- USB CLOCK Configuration ---------------------------\r
+//\r
+// <e> USB Clock Configuration\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_USB_CLOCK_SETUP              0\r
+/* not avalible in config wizzard*/\r
+#define        SCU_USBPLL_PDIV 0               \r
+#define        SCU_USBPLL_NDIV 31              \r
+#define        SCU_USBDIV      3               \r
+\r
+/*--------------------- Flash Wait State Configuration -------------------------------\r
+//\r
+// <e> Flash Wait State Configuration\r
+//     <o1.0..3>   Flash Wait State\r
+//                     <0=> 3 WS\r
+//                     <1=> 4 WS\r
+//                     <2=> 5 WS     \r
+//                                                                              <3=> 6 WS\r
+// </e>\r
+// \r
+*/\r
+\r
+#define PMU_FLASH             1\r
+#define        PMU_FLASH_WS                                    0x00000000\r
+\r
+\r
+/*--------------------- CLOCKOUT Configuration -------------------------------\r
+//\r
+// <e> Clock OUT Configuration\r
+//     <o1.0..1>   Clockout Source Selection\r
+//                     <0=> System Clock\r
+//                     <2=> Divided value of USB PLL output\r
+//                     <3=> Divided value of PLL Clock\r
+//     <o2.0..4>   Clockout divider <1-10><#-1>\r
+//     <o3.0..1>   Clockout Pin Selection\r
+//                     <0=> P1.15\r
+//                     <1=> P0.8\r
+//                     \r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCKOUT_SETUP               0\r
+#define        SCU_CLOCKOUT_SOURCE             0x00000000\r
+#define        SCU_CLOCKOUT_DIV                0x00000009\r
+#define        SCU_CLOCKOUT_PIN                0x00000001\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+#if SCU_CLOCK_SETUP\r
+uint32_t SystemCoreClock = CLOCK_FSYS;\r
+#else\r
+uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+  static functions declarations\r
+ *----------------------------------------------------------------------------*/\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void);\r
+#endif\r
+\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void);\r
+#endif\r
+\r
+\r
+/**\r
+  * @brief  Setup the microcontroller system.\r
+  *         Initialize the PLL and update the \r
+  *         SystemCoreClock variable.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemInit(void)\r
+{\r
+int temp;\r
+       \r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */\r
+               (3UL << 11*2)  );               /* set CP11 Full Access */\r
+#endif\r
+       \r
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
+       \r
+/* Setup the WDT */\r
+#if WDT_SETUP\r
+\r
+WDT->CTR &= ~WDTENB_nVal; \r
+\r
+#endif\r
+\r
+\r
+/* Setup the Flash Wait State */\r
+#if PMU_FLASH\r
+temp = FLASH0->FCON; \r
+temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
+temp |= PMU_FLASH_WS+3;\r
+FLASH0->FCON = temp;\r
+#endif\r
+\r
+       \r
+/* Setup the clockout */\r
+#if SCU_CLOCKOUT_SETUP\r
+\r
+SCU_CLK->EXTCLKCR      |= SCU_CLOCKOUT_SOURCE;\r
+/*set PLL div for clkout */\r
+SCU_CLK->EXTCLKCR      |= SCU_CLOCKOUT_DIV<<16;\r
+\r
+if (SCU_CLOCKOUT_PIN) {\r
+                                               PORT0->IOCR8 = 0x00000088;   /*P0.8 --> ALT1 select +  HWSEL */\r
+                                           PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+                                           PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk);  /*set to strong driver */\r
+                                               }\r
+else {\r
+               PORT1->IOCR12 = 0x88000000;                    /*P1.15--> ALT1 select */\r
+           PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk);  /*set to strong driver */\r
+               }\r
+\r
+#endif\r
+\r
+\r
+/* Setup the System clock */ \r
+#if SCU_CLOCK_SETUP\r
+SystemClockSetup();\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/* Setup the USB PL */ \r
+#if SCU_USB_CLOCK_SETUP\r
+USBClockSetup();\r
+#endif\r
+\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Update SystemCoreClock according to Clock Register Values\r
+  * @note   -  \r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+unsigned int PDIV;\r
+unsigned int NDIV;\r
+unsigned int K2DIV;\r
+unsigned int long VCO;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+if (SCU_CLK->SYSCLKCR ==  0x00010000)\r
+{\r
+       if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
+               /* check if PLL is locked */\r
+               /* read back divider settings */\r
+                PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
+                NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
+                K2DIV  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
+\r
+               if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
+               /* the selected clock is the Backup clock fofi */\r
+               VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
+               SystemCoreClock = VCO/K2DIV;\r
+               /* in case the sysclock div is used */\r
+               SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+               \r
+               }\r
+               else\r
+               {\r
+               /* the selected clock is the PLL external oscillator */         \r
+               VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
+               SystemCoreClock = VCO/K2DIV;\r
+               /* in case the sysclock div is used */\r
+               SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+               } \r
+       \r
+       \r
+       }\r
+}\r
+else\r
+{\r
+SystemCoreClock = CLOCK_BACK_UP;\r
+}\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+  * @brief  -\r
+  * @note   -  \r
+  * @param  None\r
+  * @retval None\r
+  */\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void)\r
+{\r
+int temp;\r
+unsigned int long VCO;\r
+int stepping_K2DIV;    \r
+\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+        \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+/* enable PLL first */\r
+  SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+\r
+} \r
+\r
+/* Enable OSC_HP if not already on*/\r
+  if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
+  {\r
+       /********************************************************************************************************************/\r
+       /*   Use external crystal for PLL clock input                                                                            */\r
+       /********************************************************************************************************************/\r
+\r
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+          SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
+          /* setup OSC WDG devider */\r
+          SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);         \r
+          /* select external OSC as PLL input */\r
+          SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+          /* restart OSC Watchdog */\r
+          SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
+\r
+       /* Timeout for wait loop ~150ms */\r
+          /********************************/\r
+          SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
+          do \r
+          {\r
+       ;/* wait for ~150ms  */\r
+          }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+          return(0);/* Return Error */\r
+\r
+    }\r
+  }\r
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
+       {\r
+       /********************************************************************************************************************/\r
+       /*   Use factory trimming Back-up clock for PLL clock input                                                                            */\r
+       /********************************************************************************************************************/\r
+               /* PLL Back up clock selected */\r
+               SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+                       \r
+       }\r
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
+  {\r
+       /********************************************************************************************************************/\r
+       /*   Use automatic trimming Back-up clock for PLL clock input                                                                            */\r
+       /********************************************************************************************************************/\r
+       /* check for HIB Domain enabled  */\r
+       if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
+               SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
+\r
+   /* check for HIB Domain is not in reset state  */\r
+       if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
+           SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
+\r
+                       /* PLL Back up clock selected */\r
+               SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+       \r
+               if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
+                       {\r
+                       /****************************************************************************************************************/\r
+                       /*   Use fOSI as source of the standby clock                                                                             */\r
+                       /****************************************************************************************************************/\r
+                       SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+                       \r
+                       SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+                       for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+                       SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+                       }\r
+               else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
+                       {\r
+                       /****************************************************************************************************************/\r
+                       /*   Use fULP as source of the standby clock                                                                            */\r
+                       /****************************************************************************************************************/\r
+                       /*check OSCUL if running correct*/\r
+                       if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
+                               {\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
+\r
+                                       SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
+                                       /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
+                                       /* select OSCUL clock for RTC*/\r
+                                       SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+                                       /*enable OSCULP WDG Alarm Enable*/\r
+                                       SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+                                       /*wait now for clock is stable */\r
+                                       do\r
+                                       {\r
+                                       SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+                                       for(temp=0;temp<=0xFFFF;temp++);\r
+                                       }\r
+                                       while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); \r
+\r
+                                       SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+                               }       \r
+                       // now OSCULP is running and can be used                 \r
+                       SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+                       \r
+                       SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+                       /*TRIAL for delay loop*/\r
+                       for(temp=0;temp<=0xFFFF;temp++);\r
+                       \r
+                       SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+                       /*TRIAL for delay loop*/\r
+                       for(temp=0;temp<=0xFFFF;temp++);\r
+                       \r
+                       }\r
+  }\r
+\r
+       /********************************************************************************************************************/\r
+       /*   Setup and look the main PLL                                                                                    */\r
+       /********************************************************************************************************************/\r
+\r
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
+       /* Systen is still running from internal clock */\r
+                  /* select FOFI as system clock */\r
+                  if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
+\r
+\r
+                        /*calulation for stepping*/\r
+                        if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+                        if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+                                       VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+        \r
+                        stepping_K2DIV = (VCO/24000000)-1;     \r
+                        /* Go to bypass the Main PLL */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+                  /* disconnect OSC_HP to PLL */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+                  /* Setup devider settings for main PLL */\r
+                  SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                  /* we may have to set OSCDISCDIS */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+                  /* connect OSC_HP to PLL */\r
+                  SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+                  /* restart PLL Lock detection */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+                  /* wait for PLL Lock */\r
+                  /* setup time out loop */\r
+              /* Timeout for wait loo ~150ms */\r
+                  /********************************/\r
+                  SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+                  SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+                  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                                  SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
+                  \r
+                  while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
+              SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+\r
+                  if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
+                               {\r
+                               /* Go back to the Main PLL */\r
+                               SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+                               }\r
+                               else return(0);\r
+                \r
+       \r
+          /*********************************************************\r
+          here we need to setup the system clock divider\r
+          *********************************************************/\r
+       \r
+               SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+               SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;     \r
+               SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+       \r
+\r
+               /* Switch system clock to PLL */\r
+          SCU_CLK->SYSCLKCR |=  0x00010000; \r
+                               \r
+          /* we may have to reset OSCDISCDIS */\r
+          SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+                               \r
+                                                                                                                                 \r
+                /*********************************************************/\r
+                /* Delay for next K2 step ~50µs */\r
+                /*********************************************************/\r
+                SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+                SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+                SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                                                                                SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
+       \r
+                while (SysTick->VAL >= 100);                                                              /* wait for ~50µs  */\r
+                SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+                /*********************************************************/\r
+\r
+          /*********************************************************\r
+          here the ramp up of the system clock starts FSys < 60MHz\r
+          *********************************************************/\r
+               if (CLOCK_FSYS > 60000000){\r
+                        /*calulation for stepping*/\r
+                        if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+                        if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+                                       VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+        \r
+                        stepping_K2DIV = (VCO/60000000)-1;     \r
+\r
+                        /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                }\r
+                else\r
+                {\r
+                               /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                   SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
+                         return(1);\r
+                }\r
+\r
+                /*********************************************************/\r
+                /* Delay for next K2 step ~50µs */\r
+                /*********************************************************/\r
+          SysTick->LOAD  = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
+       \r
+          while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          /********************************/\r
+       \r
+   /*********************************************************\r
+          here the ramp up of the system clock starts FSys < 90MHz\r
+          *********************************************************/\r
+               if (CLOCK_FSYS > 90000000){\r
+                        /*calulation for stepping*/\r
+                        if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+                        if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+                                       VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+                        stepping_K2DIV = (VCO/90000000)-1;                     \r
+\r
+                        /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                }\r
+                else\r
+                {\r
+                               /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+             SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
+                               return(1);\r
+                }\r
+       \r
+                /*********************************************************/\r
+                /* Delay for next K2 step ~50µs */\r
+                /*********************************************************/\r
+          SysTick->LOAD  = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
+       \r
+          while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          /********************************/\r
+       \r
+          /* Setup devider settings for main PLL */\r
+          SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+       \r
+          SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
+       }\r
+ }/* end this weak function enables DAVE3 clock App usage */   \r
+   return(1);\r
+\r
+}\r
+#endif\r
+\r
+/**\r
+  * @brief  -\r
+  * @note   -  \r
+  * @param  None\r
+  * @retval None\r
+  */\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void)\r
+{\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+       \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
+       /* enable PLL first */\r
+  SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+}\r
+\r
+/* check and if not already running enable OSC_HP */\r
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+                /* check if Main PLL is switched on for OSC WD*/\r
+                if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+                       /* enable PLL first */\r
+                       SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+                }\r
+          SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
+          /* setup OSC WDG devider */\r
+          SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);         \r
+          /* restart OSC Watchdog */\r
+          SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
+       \r
+       /* Timeout for wait loop ~150ms */\r
+          /********************************/\r
+          SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
+          do \r
+          {\r
+       ;/* wait for ~150ms  */\r
+          }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+          return(0);/* Return Error */\r
+       \r
+  }\r
+\r
+\r
+/* Setup USB PLL */\r
+   /* Go to bypass the Main PLL */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
+   /* disconnect OSC_FI to PLL */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+   /* Setup devider settings for main PLL */\r
+   SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
+   /* Setup USBDIV settings USB clock */\r
+   SCU_CLK->USBCLKCR = SCU_USBDIV;\r
+   /* we may have to set OSCDISCDIS */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
+   /* connect OSC_FI to PLL */\r
+   SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+   /* restart PLL Lock detection */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
+   /* wait for PLL Lock */\r
+   while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
+   \r
+ }/* end this weak function enables DAVE3 clock App usage */   \r
+   return(1);\r
+\r
+}\r
+#endif\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4200.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4200.h
new file mode 100644 (file)
index 0000000..3984b45
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4200.h
@@ -0,0 +1,13138 @@
+\r
+/****************************************************************************************************//**\r
+ * @file     XMC4200.h\r
+ *\r
+ * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for\r
+ *           XMC4200 from Infineon.\r
+ *\r
+ * @version  V1.1.0 (Reference Manual v1.1)\r
+ * @date     10. January 2013\r
+ *\r
+ * @note     Generated with SVDConv V2.78b \r
+ *           from CMSIS SVD File 'XMC4200_Processed_SVD.xml' Version 1.1.0 (Reference Manual v1.1),\r
+ *******************************************************************************************************/\r
+\r
+\r
+\r
+/** @addtogroup Infineon\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup XMC4200\r
+  * @{\r
+  */\r
+\r
+#ifndef XMC4200_H\r
+#define XMC4200_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/* -------------------------  Interrupt Number Definition  ------------------------ */\r
+\r
+typedef enum {\r
+/* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */\r
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */\r
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */\r
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */\r
+  MemoryManagement_IRQn         = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation\r
+                                                         and No Match                                                          */\r
+  BusFault_IRQn                 = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory\r
+                                                         related Fault                                                         */\r
+  UsageFault_IRQn               = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */\r
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */\r
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */\r
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */\r
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */\r
+/* ---------------------  XMC4200 Specific Interrupt Numbers  --------------------- */\r
+  SCU_0_IRQn                    =   0,              /*!<   0  SCU_0                                                            */\r
+  ERU0_0_IRQn                   =   1,              /*!<   1  ERU0_0                                                           */\r
+  ERU0_1_IRQn                   =   2,              /*!<   2  ERU0_1                                                           */\r
+  ERU0_2_IRQn                   =   3,              /*!<   3  ERU0_2                                                           */\r
+  ERU0_3_IRQn                   =   4,              /*!<   4  ERU0_3                                                           */\r
+  ERU1_0_IRQn                   =   5,              /*!<   5  ERU1_0                                                           */\r
+  ERU1_1_IRQn                   =   6,              /*!<   6  ERU1_1                                                           */\r
+  ERU1_2_IRQn                   =   7,              /*!<   7  ERU1_2                                                           */\r
+  ERU1_3_IRQn                   =   8,              /*!<   8  ERU1_3                                                           */\r
+  PMU0_0_IRQn                   =  12,              /*!<  12  PMU0_0                                                           */\r
+  VADC0_C0_0_IRQn               =  14,              /*!<  14  VADC0_C0_0                                                       */\r
+  VADC0_C0_1_IRQn               =  15,              /*!<  15  VADC0_C0_1                                                       */\r
+  VADC0_C0_2_IRQn               =  16,              /*!<  16  VADC0_C0_2                                                       */\r
+  VADC0_C0_3_IRQn               =  17,              /*!<  17  VADC0_C0_3                                                       */\r
+  VADC0_G0_0_IRQn               =  18,              /*!<  18  VADC0_G0_0                                                       */\r
+  VADC0_G0_1_IRQn               =  19,              /*!<  19  VADC0_G0_1                                                       */\r
+  VADC0_G0_2_IRQn               =  20,              /*!<  20  VADC0_G0_2                                                       */\r
+  VADC0_G0_3_IRQn               =  21,              /*!<  21  VADC0_G0_3                                                       */\r
+  VADC0_G1_0_IRQn               =  22,              /*!<  22  VADC0_G1_0                                                       */\r
+  VADC0_G1_1_IRQn               =  23,              /*!<  23  VADC0_G1_1                                                       */\r
+  VADC0_G1_2_IRQn               =  24,              /*!<  24  VADC0_G1_2                                                       */\r
+  VADC0_G1_3_IRQn               =  25,              /*!<  25  VADC0_G1_3                                                       */\r
+  DAC0_0_IRQn                   =  42,              /*!<  42  DAC0_0                                                           */\r
+  DAC0_1_IRQn                   =  43,              /*!<  43  DAC0_1                                                           */\r
+  CCU40_0_IRQn                  =  44,              /*!<  44  CCU40_0                                                          */\r
+  CCU40_1_IRQn                  =  45,              /*!<  45  CCU40_1                                                          */\r
+  CCU40_2_IRQn                  =  46,              /*!<  46  CCU40_2                                                          */\r
+  CCU40_3_IRQn                  =  47,              /*!<  47  CCU40_3                                                          */\r
+  CCU41_0_IRQn                  =  48,              /*!<  48  CCU41_0                                                          */\r
+  CCU41_1_IRQn                  =  49,              /*!<  49  CCU41_1                                                          */\r
+  CCU41_2_IRQn                  =  50,              /*!<  50  CCU41_2                                                          */\r
+  CCU41_3_IRQn                  =  51,              /*!<  51  CCU41_3                                                          */\r
+  CCU80_0_IRQn                  =  60,              /*!<  60  CCU80_0                                                          */\r
+  CCU80_1_IRQn                  =  61,              /*!<  61  CCU80_1                                                          */\r
+  CCU80_2_IRQn                  =  62,              /*!<  62  CCU80_2                                                          */\r
+  CCU80_3_IRQn                  =  63,              /*!<  63  CCU80_3                                                          */\r
+  POSIF0_0_IRQn                 =  68,              /*!<  68  POSIF0_0                                                         */\r
+  POSIF0_1_IRQn                 =  69,              /*!<  69  POSIF0_1                                                         */\r
+  HRPWM_0_IRQn                  =  72,              /*!<  72  HRPWM_0                                                          */\r
+  HRPWM_1_IRQn                  =  73,              /*!<  73  HRPWM_1                                                         */\r
+  HRPWM_2_IRQn                  =  74,              /*!<  74  HRPWM_0                                                          */\r
+  HRPWM_3_IRQn                  =  75,              /*!<  75  HRPWM_1                                                         */\r
+  CAN0_0_IRQn                   =  76,              /*!<  76  CAN0_0                                                           */\r
+  CAN0_1_IRQn                   =  77,              /*!<  77  CAN0_1                                                           */\r
+  CAN0_2_IRQn                   =  78,              /*!<  78  CAN0_2                                                           */\r
+  CAN0_3_IRQn                   =  79,              /*!<  79  CAN0_3                                                           */\r
+  CAN0_4_IRQn                   =  80,              /*!<  80  CAN0_4                                                           */\r
+  CAN0_5_IRQn                   =  81,              /*!<  81  CAN0_5                                                           */\r
+  CAN0_6_IRQn                   =  82,              /*!<  82  CAN0_6                                                           */\r
+  CAN0_7_IRQn                   =  83,              /*!<  83  CAN0_7                                                           */\r
+  USIC0_0_IRQn                  =  84,              /*!<  84  USIC0_0                                                          */\r
+  USIC0_1_IRQn                  =  85,              /*!<  85  USIC0_1                                                          */\r
+  USIC0_2_IRQn                  =  86,              /*!<  86  USIC0_2                                                          */\r
+  USIC0_3_IRQn                  =  87,              /*!<  87  USIC0_3                                                          */\r
+  USIC0_4_IRQn                  =  88,              /*!<  88  USIC0_4                                                          */\r
+  USIC0_5_IRQn                  =  89,              /*!<  89  USIC0_5                                                          */\r
+  USIC1_0_IRQn                  =  90,              /*!<  90  USIC1_0                                                          */\r
+  USIC1_1_IRQn                  =  91,              /*!<  91  USIC1_1                                                          */\r
+  USIC1_2_IRQn                  =  92,              /*!<  92  USIC1_2                                                          */\r
+  USIC1_3_IRQn                  =  93,              /*!<  93  USIC1_3                                                          */\r
+  USIC1_4_IRQn                  =  94,              /*!<  94  USIC1_4                                                          */\r
+  USIC1_5_IRQn                  =  95,              /*!<  95  USIC1_5                                                          */\r
+  LEDTS0_0_IRQn                 = 102,              /*!< 102  LEDTS0_0                                                         */\r
+  FCE0_0_IRQn                   = 104,              /*!< 104  FCE0_0                                                           */\r
+  GPDMA0_0_IRQn                 = 105,              /*!< 105  GPDMA0_0                                                         */\r
+  USB0_0_IRQn                   = 107,              /*!< 107  USB0_0                                                           */\r
+} IRQn_Type;\r
+\r
+\r
+/** @addtogroup Configuration_of_CMSIS\r
+  * @{\r
+  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      Processor and Core Peripheral Section     ================ */\r
+/* ================================================================================ */\r
+\r
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */\r
+#define __CM4_REV                 0x0200            /*!< Cortex-M4 Core Revision                                               */\r
+#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */\r
+#define __NVIC_PRIO_BITS               6            /*!< Number of Bits used for Priority Levels                               */\r
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */\r
+#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */\r
+/** @} */ /* End of group Configuration_of_CMSIS */\r
+\r
+#include <core_cm4.h>                               /*!< Cortex-M4 processor and core peripherals                              */\r
+#include "system_XMC4200.h"                         /*!< XMC4200 System                                                        */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       Device Specific Peripheral Section       ================ */\r
+/* ================================================================================ */\r
+/* Macro to modify desired bitfields of a register */\r
+#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \\r
+                                                        ((uint32_t)mask)) | \\r
+                                          (reg & ((uint32_t)~((uint32_t)mask)))\r
+\r
+/* Macro to modify desired bitfields of a register */\r
+#define WR_REG_SIZE(reg, mask, pos, val, size) {  \\r
+uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \\r
+uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \\r
+uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \\r
+uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \\r
+reg = (uint##size##_t) (VAL2 | VAL4);\\r
+}\r
+\r
+/** Macro to read bitfields from a register */\r
+#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)\r
+\r
+/** Macro to read bitfields from a register */\r
+#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \\r
+                                                      (uint32_t)mask) >> pos) )\r
+\r
+/** Macro to set a bit in register */\r
+#define SET_BIT(reg, pos)     (reg |= ((uint32_t)1<<pos))\r
+\r
+/** Macro to clear a bit in register */\r
+#define CLR_BIT(reg, pos)     (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) )\r
+/*\r
+* ==========================================================================\r
+* ---------- Interrupt Handler Definition ----------------------------------\r
+* ==========================================================================\r
+*/\r
+#define IRQ_Hdlr_0   SCU_0_IRQHandler\r
+#define IRQ_Hdlr_1   ERU0_0_IRQHandler\r
+#define IRQ_Hdlr_2   ERU0_1_IRQHandler\r
+#define IRQ_Hdlr_3   ERU0_2_IRQHandler\r
+#define IRQ_Hdlr_4   ERU0_3_IRQHandler\r
+#define IRQ_Hdlr_5   ERU1_0_IRQHandler\r
+#define IRQ_Hdlr_6   ERU1_1_IRQHandler\r
+#define IRQ_Hdlr_7   ERU1_2_IRQHandler\r
+#define IRQ_Hdlr_8   ERU1_3_IRQHandler\r
+#define IRQ_Hdlr_12  PMU0_0_IRQHandler\r
+#define IRQ_Hdlr_14  VADC0_C0_0_IRQHandler\r
+#define IRQ_Hdlr_15  VADC0_C0_1_IRQHandler\r
+#define IRQ_Hdlr_16  VADC0_C0_2_IRQHandler\r
+#define IRQ_Hdlr_17  VADC0_C0_3_IRQHandler\r
+#define IRQ_Hdlr_18  VADC0_G0_0_IRQHandler\r
+#define IRQ_Hdlr_19  VADC0_G0_1_IRQHandler\r
+#define IRQ_Hdlr_20  VADC0_G0_2_IRQHandler\r
+#define IRQ_Hdlr_21  VADC0_G0_3_IRQHandler\r
+#define IRQ_Hdlr_22  VADC0_G1_0_IRQHandler\r
+#define IRQ_Hdlr_23  VADC0_G1_1_IRQHandler\r
+#define IRQ_Hdlr_24  VADC0_G1_2_IRQHandler\r
+#define IRQ_Hdlr_25  VADC0_G1_3_IRQHandler\r
+#define IRQ_Hdlr_42  DAC0_0_IRQHandler\r
+#define IRQ_Hdlr_43  DAC0_1_IRQHandler\r
+#define IRQ_Hdlr_44  CCU40_0_IRQHandler\r
+#define IRQ_Hdlr_45  CCU40_1_IRQHandler\r
+#define IRQ_Hdlr_46  CCU40_2_IRQHandler\r
+#define IRQ_Hdlr_47  CCU40_3_IRQHandler\r
+#define IRQ_Hdlr_48  CCU41_0_IRQHandler\r
+#define IRQ_Hdlr_49  CCU41_1_IRQHandler\r
+#define IRQ_Hdlr_50  CCU41_2_IRQHandler\r
+#define IRQ_Hdlr_51  CCU41_3_IRQHandler\r
+#define IRQ_Hdlr_60  CCU80_0_IRQHandler\r
+#define IRQ_Hdlr_61  CCU80_1_IRQHandler\r
+#define IRQ_Hdlr_62  CCU80_2_IRQHandler\r
+#define IRQ_Hdlr_63  CCU80_3_IRQHandler\r
+#define IRQ_Hdlr_68  POSIF0_0_IRQHandler\r
+#define IRQ_Hdlr_69  POSIF0_1_IRQHandler\r
+#define IRQ_Hdlr_72  HRPWM_0_IRQHandler\r
+#define IRQ_Hdlr_73  HRPWM_1_IRQHandler\r
+#define IRQ_Hdlr_74  HRPWM_2_IRQHandler\r
+#define IRQ_Hdlr_75  HRPWM_3_IRQHandler\r
+#define IRQ_Hdlr_76  CAN0_0_IRQHandler\r
+#define IRQ_Hdlr_77  CAN0_1_IRQHandler\r
+#define IRQ_Hdlr_78  CAN0_2_IRQHandler\r
+#define IRQ_Hdlr_79  CAN0_3_IRQHandler\r
+#define IRQ_Hdlr_80  CAN0_4_IRQHandler\r
+#define IRQ_Hdlr_81  CAN0_5_IRQHandler\r
+#define IRQ_Hdlr_82  CAN0_6_IRQHandler\r
+#define IRQ_Hdlr_83  CAN0_7_IRQHandler\r
+#define IRQ_Hdlr_84  USIC0_0_IRQHandler\r
+#define IRQ_Hdlr_85  USIC0_1_IRQHandler\r
+#define IRQ_Hdlr_86  USIC0_2_IRQHandler\r
+#define IRQ_Hdlr_87  USIC0_3_IRQHandler\r
+#define IRQ_Hdlr_88  USIC0_4_IRQHandler\r
+#define IRQ_Hdlr_89  USIC0_5_IRQHandler\r
+#define IRQ_Hdlr_90  USIC1_0_IRQHandler\r
+#define IRQ_Hdlr_91  USIC1_1_IRQHandler\r
+#define IRQ_Hdlr_92  USIC1_2_IRQHandler\r
+#define IRQ_Hdlr_93  USIC1_3_IRQHandler\r
+#define IRQ_Hdlr_94  USIC1_4_IRQHandler\r
+#define IRQ_Hdlr_95  USIC1_5_IRQHandler\r
+#define IRQ_Hdlr_102 LEDTS0_0_IRQHandler\r
+#define IRQ_Hdlr_104 FCE0_0_IRQHandler\r
+#define IRQ_Hdlr_105 GPDMA0_0_IRQHandler\r
+#define IRQ_Hdlr_107 USB0_0_IRQHandler\r
+\r
+/*\r
+* ==========================================================================\r
+* ---------- Interrupt Handler retrieval macro -----------------------------\r
+* ==========================================================================\r
+*/\r
+#define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N\r
+\r
+\r
+/** @addtogroup Device_Peripheral_Registers\r
+  * @{\r
+  */\r
+\r
+\r
+/* -------------------  Start of section using anonymous unions  ------------------ */\r
+#if defined(__CC_ARM)\r
+  #pragma push\r
+  #pragma anon_unions\r
+#elif defined(__ICCARM__)\r
+  #pragma language=extended\r
+#elif defined(__GNUC__)\r
+  /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+/* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+  #pragma warning 586\r
+#else\r
+  #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       PPB                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Cortex-M4 Private Peripheral Block (PPB)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0xE000E000) PPB Structure                                          */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  ACTLR;                             /*!< (@ 0xE000E008) Auxiliary Control Register                             */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  SYST_CSR;                          /*!< (@ 0xE000E010) SysTick Control and Status Register                    */\r
+  __IO uint32_t  SYST_RVR;                          /*!< (@ 0xE000E014) SysTick Reload Value Register                          */\r
+  __IO uint32_t  SYST_CVR;                          /*!< (@ 0xE000E018) SysTick Current Value Register                         */\r
+  __IO uint32_t  SYST_CALIB;                        /*!< (@ 0xE000E01C) SysTick Calibration Value Register r                   */\r
+  __I  uint32_t  RESERVED2[56];\r
+  __IO uint32_t  NVIC_ISER0;                        /*!< (@ 0xE000E100) Interrupt Set-enable Register 0                        */\r
+  __IO uint32_t  NVIC_ISER1;                        /*!< (@ 0xE000E104) Interrupt Set-enable Register 1                        */\r
+  __IO uint32_t  NVIC_ISER2;                        /*!< (@ 0xE000E108) Interrupt Set-enable Register 2                        */\r
+  __IO uint32_t  NVIC_ISER3;                        /*!< (@ 0xE000E10C) Interrupt Set-enable Register 3                        */\r
+  __I  uint32_t  RESERVED3[28];\r
+  __IO uint32_t  NVIC_ICER0;                        /*!< (@ 0xE000E180) Interrupt Clear-enable Register 0                      */\r
+  __IO uint32_t  NVIC_ICER1;                        /*!< (@ 0xE000E184) Interrupt Clear-enable Register 1                      */\r
+  __IO uint32_t  NVIC_ICER2;                        /*!< (@ 0xE000E188) Interrupt Clear-enable Register 2                      */\r
+  __IO uint32_t  NVIC_ICER3;                        /*!< (@ 0xE000E18C) Interrupt Clear-enable Register 3                      */\r
+  __I  uint32_t  RESERVED4[28];\r
+  __IO uint32_t  NVIC_ISPR0;                        /*!< (@ 0xE000E200) Interrupt Set-pending Register 0                       */\r
+  __IO uint32_t  NVIC_ISPR1;                        /*!< (@ 0xE000E204) Interrupt Set-pending Register 1                       */\r
+  __IO uint32_t  NVIC_ISPR2;                        /*!< (@ 0xE000E208) Interrupt Set-pending Register 2                       */\r
+  __IO uint32_t  NVIC_ISPR3;                        /*!< (@ 0xE000E20C) Interrupt Set-pending Register 3                       */\r
+  __I  uint32_t  RESERVED5[28];\r
+  __IO uint32_t  NVIC_ICPR0;                        /*!< (@ 0xE000E280) Interrupt Clear-pending Register 0                     */\r
+  __IO uint32_t  NVIC_ICPR1;                        /*!< (@ 0xE000E284) Interrupt Clear-pending Register 1                     */\r
+  __IO uint32_t  NVIC_ICPR2;                        /*!< (@ 0xE000E288) Interrupt Clear-pending Register 2                     */\r
+  __IO uint32_t  NVIC_ICPR3;                        /*!< (@ 0xE000E28C) Interrupt Clear-pending Register 3                     */\r
+  __I  uint32_t  RESERVED6[28];\r
+  __IO uint32_t  NVIC_IABR0;                        /*!< (@ 0xE000E300) Interrupt Active Bit Register 0                        */\r
+  __IO uint32_t  NVIC_IABR1;                        /*!< (@ 0xE000E304) Interrupt Active Bit Register 1                        */\r
+  __IO uint32_t  NVIC_IABR2;                        /*!< (@ 0xE000E308) Interrupt Active Bit Register 2                        */\r
+  __IO uint32_t  NVIC_IABR3;                        /*!< (@ 0xE000E30C) Interrupt Active Bit Register 3                        */\r
+  __I  uint32_t  RESERVED7[60];\r
+  __IO uint32_t  NVIC_IPR0;                         /*!< (@ 0xE000E400) Interrupt Priority Register 0                          */\r
+  __IO uint32_t  NVIC_IPR1;                         /*!< (@ 0xE000E404) Interrupt Priority Register 1                          */\r
+  __IO uint32_t  NVIC_IPR2;                         /*!< (@ 0xE000E408) Interrupt Priority Register 2                          */\r
+  __IO uint32_t  NVIC_IPR3;                         /*!< (@ 0xE000E40C) Interrupt Priority Register 3                          */\r
+  __IO uint32_t  NVIC_IPR4;                         /*!< (@ 0xE000E410) Interrupt Priority Register 4                          */\r
+  __IO uint32_t  NVIC_IPR5;                         /*!< (@ 0xE000E414) Interrupt Priority Register 5                          */\r
+  __IO uint32_t  NVIC_IPR6;                         /*!< (@ 0xE000E418) Interrupt Priority Register 6                          */\r
+  __IO uint32_t  NVIC_IPR7;                         /*!< (@ 0xE000E41C) Interrupt Priority Register 7                          */\r
+  __IO uint32_t  NVIC_IPR8;                         /*!< (@ 0xE000E420) Interrupt Priority Register 8                          */\r
+  __IO uint32_t  NVIC_IPR9;                         /*!< (@ 0xE000E424) Interrupt Priority Register 9                          */\r
+  __IO uint32_t  NVIC_IPR10;                        /*!< (@ 0xE000E428) Interrupt Priority Register 10                         */\r
+  __IO uint32_t  NVIC_IPR11;                        /*!< (@ 0xE000E42C) Interrupt Priority Register 11                         */\r
+  __IO uint32_t  NVIC_IPR12;                        /*!< (@ 0xE000E430) Interrupt Priority Register 12                         */\r
+  __IO uint32_t  NVIC_IPR13;                        /*!< (@ 0xE000E434) Interrupt Priority Register 13                         */\r
+  __IO uint32_t  NVIC_IPR14;                        /*!< (@ 0xE000E438) Interrupt Priority Register 14                         */\r
+  __IO uint32_t  NVIC_IPR15;                        /*!< (@ 0xE000E43C) Interrupt Priority Register 15                         */\r
+  __IO uint32_t  NVIC_IPR16;                        /*!< (@ 0xE000E440) Interrupt Priority Register 16                         */\r
+  __IO uint32_t  NVIC_IPR17;                        /*!< (@ 0xE000E444) Interrupt Priority Register 17                         */\r
+  __IO uint32_t  NVIC_IPR18;                        /*!< (@ 0xE000E448) Interrupt Priority Register 18                         */\r
+  __IO uint32_t  NVIC_IPR19;                        /*!< (@ 0xE000E44C) Interrupt Priority Register 19                         */\r
+  __IO uint32_t  NVIC_IPR20;                        /*!< (@ 0xE000E450) Interrupt Priority Register 20                         */\r
+  __IO uint32_t  NVIC_IPR21;                        /*!< (@ 0xE000E454) Interrupt Priority Register 21                         */\r
+  __IO uint32_t  NVIC_IPR22;                        /*!< (@ 0xE000E458) Interrupt Priority Register 22                         */\r
+  __IO uint32_t  NVIC_IPR23;                        /*!< (@ 0xE000E45C) Interrupt Priority Register 23                         */\r
+  __IO uint32_t  NVIC_IPR24;                        /*!< (@ 0xE000E460) Interrupt Priority Register 24                         */\r
+  __IO uint32_t  NVIC_IPR25;                        /*!< (@ 0xE000E464) Interrupt Priority Register 25                         */\r
+  __IO uint32_t  NVIC_IPR26;                        /*!< (@ 0xE000E468) Interrupt Priority Register 26                         */\r
+  __IO uint32_t  NVIC_IPR27;                        /*!< (@ 0xE000E46C) Interrupt Priority Register 27                         */\r
+  __I  uint32_t  RESERVED8[548];\r
+  __I  uint32_t  CPUID;                             /*!< (@ 0xE000ED00) CPUID Base Register                                    */\r
+  __IO uint32_t  ICSR;                              /*!< (@ 0xE000ED04) Interrupt Control and State Register                   */\r
+  __IO uint32_t  VTOR;                              /*!< (@ 0xE000ED08) Vector Table Offset Register                           */\r
+  __IO uint32_t  AIRCR;                             /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register       */\r
+  __IO uint32_t  SCR;                               /*!< (@ 0xE000ED10) System Control Register                                */\r
+  __IO uint32_t  CCR;                               /*!< (@ 0xE000ED14) Configuration and Control Register                     */\r
+  __IO uint32_t  SHPR1;                             /*!< (@ 0xE000ED18) System Handler Priority Register 1                     */\r
+  __IO uint32_t  SHPR2;                             /*!< (@ 0xE000ED1C) System Handler Priority Register 2                     */\r
+  __IO uint32_t  SHPR3;                             /*!< (@ 0xE000ED20) System Handler Priority Register 3                     */\r
+  __IO uint32_t  SHCSR;                             /*!< (@ 0xE000ED24) System Handler Control and State Register              */\r
+  __IO uint32_t  CFSR;                              /*!< (@ 0xE000ED28) Configurable Fault Status Register                     */\r
+  __IO uint32_t  HFSR;                              /*!< (@ 0xE000ED2C) HardFault Status Register                              */\r
+  __I  uint32_t  RESERVED9;\r
+  __IO uint32_t  MMFAR;                             /*!< (@ 0xE000ED34) MemManage Fault Address Register                       */\r
+  __IO uint32_t  BFAR;                              /*!< (@ 0xE000ED38) BusFault Address Register                              */\r
+  __IO uint32_t  AFSR;                              /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register                        */\r
+  __I  uint32_t  RESERVED10[18];\r
+  __IO uint32_t  CPACR;                             /*!< (@ 0xE000ED88) Coprocessor Access Control Register                    */\r
+  __I  uint32_t  RESERVED11;\r
+  __I  uint32_t  MPU_TYPE;                          /*!< (@ 0xE000ED90) MPU Type Register                                      */\r
+  __IO uint32_t  MPU_CTRL;                          /*!< (@ 0xE000ED94) MPU Control Register                                   */\r
+  __IO uint32_t  MPU_RNR;                           /*!< (@ 0xE000ED98) MPU Region Number Register                             */\r
+  __IO uint32_t  MPU_RBAR;                          /*!< (@ 0xE000ED9C) MPU Region Base Address Register                       */\r
+  __IO uint32_t  MPU_RASR;                          /*!< (@ 0xE000EDA0) MPU Region Attribute and Size Register                 */\r
+  __IO uint32_t  MPU_RBAR_A1;                       /*!< (@ 0xE000EDA4) MPU Region Base Address Register A1                    */\r
+  __IO uint32_t  MPU_RASR_A1;                       /*!< (@ 0xE000EDA8) MPU Region Attribute and Size Register A1              */\r
+  __IO uint32_t  MPU_RBAR_A2;                       /*!< (@ 0xE000EDAC) MPU Region Base Address Register A2                    */\r
+  __IO uint32_t  MPU_RASR_A2;                       /*!< (@ 0xE000EDB0) MPU Region Attribute and Size Register A2              */\r
+  __IO uint32_t  MPU_RBAR_A3;                       /*!< (@ 0xE000EDB4) MPU Region Base Address Register A3                    */\r
+  __IO uint32_t  MPU_RASR_A3;                       /*!< (@ 0xE000EDB8) MPU Region Attribute and Size Register A3              */\r
+  __I  uint32_t  RESERVED12[81];\r
+  __O  uint32_t  STIR;                              /*!< (@ 0xE000EF00) Software Trigger Interrupt Register                    */\r
+  __I  uint32_t  RESERVED13[12];\r
+  __IO uint32_t  FPCCR;                             /*!< (@ 0xE000EF34) Floating-point Context Control Register                */\r
+  __IO uint32_t  FPCAR;                             /*!< (@ 0xE000EF38) Floating-point Context Address Register                */\r
+  __IO uint32_t  FPDSCR;                            /*!< (@ 0xE000EF3C) Floating-point Default Status Control Register         */\r
+} PPB_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       DLR                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief DMA Line Router (DLR)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004900) DLR Structure                                          */\r
+  __I  uint32_t  OVRSTAT;                           /*!< (@ 0x50004900) Overrun Status                                         */\r
+  __O  uint32_t  OVRCLR;                            /*!< (@ 0x50004904) Overrun Clear                                          */\r
+  __IO uint32_t  SRSEL0;                            /*!< (@ 0x50004908) Service Request Selection 0                            */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  LNEN;                              /*!< (@ 0x50004910) Line Enable                                            */\r
+} DLR_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   ERU [ERU0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Event Request Unit 0 (ERU)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004800) ERU Structure                                          */\r
+  __IO uint32_t  EXISEL;                            /*!< (@ 0x50004800) Event Input Select                                     */\r
+  __I  uint32_t  RESERVED0[3];\r
+  __IO uint32_t  EXICON[4];                         /*!< (@ 0x50004810) Event Input Control                                    */\r
+  __IO uint32_t  EXOCON[4];                         /*!< (@ 0x50004820) Event Output Trigger Control                           */\r
+} ERU_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     GPDMA0                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief General Purpose DMA Unit 0 (GPDMA0)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x500142C0) GPDMA0 Structure                                       */\r
+  __IO uint32_t  RAWTFR;                            /*!< (@ 0x500142C0) Raw IntTfr Status                                      */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  RAWBLOCK;                          /*!< (@ 0x500142C8) Raw IntBlock Status                                    */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  RAWSRCTRAN;                        /*!< (@ 0x500142D0) Raw IntSrcTran Status                                  */\r
+  __I  uint32_t  RESERVED2;\r
+  __IO uint32_t  RAWDSTTRAN;                        /*!< (@ 0x500142D8) Raw IntBlock Status                                    */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  RAWERR;                            /*!< (@ 0x500142E0) Raw IntErr Status                                      */\r
+  __I  uint32_t  RESERVED4;\r
+  __I  uint32_t  STATUSTFR;                         /*!< (@ 0x500142E8) IntTfr Status                                          */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  STATUSBLOCK;                       /*!< (@ 0x500142F0) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED6;\r
+  __I  uint32_t  STATUSSRCTRAN;                     /*!< (@ 0x500142F8) IntSrcTran Status                                      */\r
+  __I  uint32_t  RESERVED7;\r
+  __I  uint32_t  STATUSDSTTRAN;                     /*!< (@ 0x50014300) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED8;\r
+  __I  uint32_t  STATUSERR;                         /*!< (@ 0x50014308) IntErr Status                                          */\r
+  __I  uint32_t  RESERVED9;\r
+  __IO uint32_t  MASKTFR;                           /*!< (@ 0x50014310) Mask for Raw IntTfr Status                             */\r
+  __I  uint32_t  RESERVED10;\r
+  __IO uint32_t  MASKBLOCK;                         /*!< (@ 0x50014318) Mask for Raw IntBlock Status                           */\r
+  __I  uint32_t  RESERVED11;\r
+  __IO uint32_t  MASKSRCTRAN;                       /*!< (@ 0x50014320) Mask for Raw IntSrcTran Status                         */\r
+  __I  uint32_t  RESERVED12;\r
+  __IO uint32_t  MASKDSTTRAN;                       /*!< (@ 0x50014328) Mask for Raw IntBlock Status                           */\r
+  __I  uint32_t  RESERVED13;\r
+  __IO uint32_t  MASKERR;                           /*!< (@ 0x50014330) Mask for Raw IntErr Status                             */\r
+  __I  uint32_t  RESERVED14;\r
+  __O  uint32_t  CLEARTFR;                          /*!< (@ 0x50014338) IntTfr Status                                          */\r
+  __I  uint32_t  RESERVED15;\r
+  __O  uint32_t  CLEARBLOCK;                        /*!< (@ 0x50014340) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED16;\r
+  __O  uint32_t  CLEARSRCTRAN;                      /*!< (@ 0x50014348) IntSrcTran Status                                      */\r
+  __I  uint32_t  RESERVED17;\r
+  __O  uint32_t  CLEARDSTTRAN;                      /*!< (@ 0x50014350) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED18;\r
+  __O  uint32_t  CLEARERR;                          /*!< (@ 0x50014358) IntErr Status                                          */\r
+  __I  uint32_t  RESERVED19;\r
+  __I  uint32_t  STATUSINT;                         /*!< (@ 0x50014360) Combined Interrupt Status Register                     */\r
+  __I  uint32_t  RESERVED20;\r
+  __IO uint32_t  REQSRCREG;                         /*!< (@ 0x50014368) Source Software Transaction Request Register           */\r
+  __I  uint32_t  RESERVED21;\r
+  __IO uint32_t  REQDSTREG;                         /*!< (@ 0x50014370) Destination Software Transaction Request Register      */\r
+  __I  uint32_t  RESERVED22;\r
+  __IO uint32_t  SGLREQSRCREG;                      /*!< (@ 0x50014378) Single Source Transaction Request Register             */\r
+  __I  uint32_t  RESERVED23;\r
+  __IO uint32_t  SGLREQDSTREG;                      /*!< (@ 0x50014380) Single Destination Transaction Request Register        */\r
+  __I  uint32_t  RESERVED24;\r
+  __IO uint32_t  LSTSRCREG;                         /*!< (@ 0x50014388) Last Source Transaction Request Register               */\r
+  __I  uint32_t  RESERVED25;\r
+  __IO uint32_t  LSTDSTREG;                         /*!< (@ 0x50014390) Last Destination Transaction Request Register          */\r
+  __I  uint32_t  RESERVED26;\r
+  __IO uint32_t  DMACFGREG;                         /*!< (@ 0x50014398) GPDMA Configuration Register                           */\r
+  __I  uint32_t  RESERVED27;\r
+  __IO uint32_t  CHENREG;                           /*!< (@ 0x500143A0) GPDMA Channel Enable Register                          */\r
+  __I  uint32_t  RESERVED28;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x500143A8) GPDMA0 ID Register                                     */\r
+  __I  uint32_t  RESERVED29[19];\r
+  __I  uint32_t  TYPE;                              /*!< (@ 0x500143F8) GPDMA Component Type                                   */\r
+  __I  uint32_t  VERSION;                           /*!< (@ 0x500143FC) DMA Component Version                                  */\r
+} GPDMA0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================            GPDMA0_CH0_1 [GPDMA0_CH0]           ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief General Purpose DMA Unit 0 (GPDMA0_CH0_1)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50014000) GPDMA0_CH0_1 Structure                                 */\r
+  __IO uint32_t  SAR;                               /*!< (@ 0x50014000) Source Address Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DAR;                               /*!< (@ 0x50014008) Destination Address Register                           */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  LLP;                               /*!< (@ 0x50014010) Linked List Pointer Register                           */\r
+  __I  uint32_t  RESERVED2;\r
+  __IO uint32_t  CTLL;                              /*!< (@ 0x50014018) Control Register Low                                   */\r
+  __IO uint32_t  CTLH;                              /*!< (@ 0x5001401C) Control Register High                                  */\r
+  __IO uint32_t  SSTAT;                             /*!< (@ 0x50014020) Source Status Register                                 */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  DSTAT;                             /*!< (@ 0x50014028) Destination Status Register                            */\r
+  __I  uint32_t  RESERVED4;\r
+  __IO uint32_t  SSTATAR;                           /*!< (@ 0x50014030) Source Status Address Register                         */\r
+  __I  uint32_t  RESERVED5;\r
+  __IO uint32_t  DSTATAR;                           /*!< (@ 0x50014038) Destination Status Address Register                    */\r
+  __I  uint32_t  RESERVED6;\r
+  __IO uint32_t  CFGL;                              /*!< (@ 0x50014040) Configuration Register Low                             */\r
+  __IO uint32_t  CFGH;                              /*!< (@ 0x50014044) Configuration Register High                            */\r
+  __IO uint32_t  SGR;                               /*!< (@ 0x50014048) Source Gather Register                                 */\r
+  __I  uint32_t  RESERVED7;\r
+  __IO uint32_t  DSR;                               /*!< (@ 0x50014050) Destination Scatter Register                           */\r
+} GPDMA0_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================            GPDMA0_CH2_7 [GPDMA0_CH2]           ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief General Purpose DMA Unit 0 (GPDMA0_CH2_7)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x500140B0) GPDMA0_CH2_7 Structure                                 */\r
+  __IO uint32_t  SAR;                               /*!< (@ 0x500140B0) Source Address Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DAR;                               /*!< (@ 0x500140B8) Destination Address Register                           */\r
+  __I  uint32_t  RESERVED1[3];\r
+  __IO uint32_t  CTLL;                              /*!< (@ 0x500140C8) Control Register Low                                   */\r
+  __IO uint32_t  CTLH;                              /*!< (@ 0x500140CC) Control Register High                                  */\r
+  __I  uint32_t  RESERVED2[8];\r
+  __IO uint32_t  CFGL;                              /*!< (@ 0x500140F0) Configuration Register Low                             */\r
+  __IO uint32_t  CFGH;                              /*!< (@ 0x500140F4) Configuration Register High                            */\r
+} GPDMA0_CH2_7_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       FCE                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Flexible CRC Engine (FCE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50020000) FCE Structure                                          */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x50020000) Clock Control Register                                 */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50020008) Module Identification Register                         */\r
+} FCE_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                FCE_KE [FCE_KE0]                ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Flexible CRC Engine (FCE_KE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50020020) FCE_KE Structure                                       */\r
+  __IO uint32_t  IR;                                /*!< (@ 0x50020020) Input Register                                         */\r
+  __I  uint32_t  RES;                               /*!< (@ 0x50020024) CRC Result Register                                    */\r
+  __IO uint32_t  CFG;                               /*!< (@ 0x50020028) CRC Configuration Register                             */\r
+  __IO uint32_t  STS;                               /*!< (@ 0x5002002C) CRC Status Register                                    */\r
+  __IO uint32_t  LENGTH;                            /*!< (@ 0x50020030) CRC Length Register                                    */\r
+  __IO uint32_t  CHECK;                             /*!< (@ 0x50020034) CRC Check Register                                     */\r
+  __IO uint32_t  CRC;                               /*!< (@ 0x50020038) CRC Register                                           */\r
+  __IO uint32_t  CTR;                               /*!< (@ 0x5002003C) CRC Test Register                                      */\r
+} FCE_KE_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   PBA [PBA0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Peripheral Bridge AHB 0 (PBA)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40000000) PBA Structure                                          */\r
+  __IO uint32_t  STS;                               /*!< (@ 0x40000000) Peripheral Bridge Status Register                      */\r
+  __I  uint32_t  WADDR;                             /*!< (@ 0x40000004) PBA Write Error Address Register                       */\r
+} PBA_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                 FLASH [FLASH0]                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Flash Memory Controller (FLASH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x58001000) FLASH Structure                                        */\r
+  __I  uint32_t  RESERVED0[1026];\r
+  __I  uint32_t  ID;                                /*!< (@ 0x58002008) Flash Module Identification Register                   */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  FSR;                               /*!< (@ 0x58002010) Flash Status Register                                  */\r
+  __IO uint32_t  FCON;                              /*!< (@ 0x58002014) Flash Configuration Register                           */\r
+  __IO uint32_t  MARP;                              /*!< (@ 0x58002018) Margin Control Register PFLASH                         */\r
+  __I  uint32_t  RESERVED2;\r
+  __I  uint32_t  PROCON0;                           /*!< (@ 0x58002020) Flash Protection Configuration Register User\r
+                                                         0                                                                     */\r
+  __I  uint32_t  PROCON1;                           /*!< (@ 0x58002024) Flash Protection Configuration Register User\r
+                                                         1                                                                     */\r
+  __I  uint32_t  PROCON2;                           /*!< (@ 0x58002028) Flash Protection Configuration Register User\r
+                                                         2                                                                     */\r
+} FLASH0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PREF                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Prefetch Unit (PREF)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x58004000) PREF Structure                                         */\r
+  __IO uint32_t  PCON;                              /*!< (@ 0x58004000) Prefetch Configuration Register                        */\r
+} PREF_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   PMU [PMU0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Program Management Unit (PMU)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x58000508) PMU Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x58000508) PMU0 Identification Register                           */\r
+} PMU0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       WDT                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Watch Dog Timer (WDT)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50008000) WDT Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50008000) WDT ID Register                                        */\r
+  __IO uint32_t  CTR;                               /*!< (@ 0x50008004) WDT Control Register                                   */\r
+  __O  uint32_t  SRV;                               /*!< (@ 0x50008008) WDT Service Register                                   */\r
+  __I  uint32_t  TIM;                               /*!< (@ 0x5000800C) WDT Timer Register                                     */\r
+  __IO uint32_t  WLB;                               /*!< (@ 0x50008010) WDT Window Lower Bound Register                        */\r
+  __IO uint32_t  WUB;                               /*!< (@ 0x50008014) WDT Window Upper Bound Register                        */\r
+  __I  uint32_t  WDTSTS;                            /*!< (@ 0x50008018) WDT Status Register                                    */\r
+  __O  uint32_t  WDTCLR;                            /*!< (@ 0x5000801C) WDT Clear Register                                     */\r
+} WDT_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       RTC                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Real Time Clock (RTC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004A00) RTC Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50004A00) RTC ID Register                                        */\r
+  __IO uint32_t  CTR;                               /*!< (@ 0x50004A04) RTC Control Register                                   */\r
+  __I  uint32_t  RAWSTAT;                           /*!< (@ 0x50004A08) RTC Raw Service Request Register                       */\r
+  __I  uint32_t  STSSR;                             /*!< (@ 0x50004A0C) RTC Service Request Status Register                    */\r
+  __IO uint32_t  MSKSR;                             /*!< (@ 0x50004A10) RTC Service Request Mask Register                      */\r
+  __O  uint32_t  CLRSR;                             /*!< (@ 0x50004A14) RTC Clear Service Request Register                     */\r
+  __IO uint32_t  ATIM0;                             /*!< (@ 0x50004A18) RTC Alarm Time Register 0                              */\r
+  __IO uint32_t  ATIM1;                             /*!< (@ 0x50004A1C) RTC Alarm Time Register 1                              */\r
+  __IO uint32_t  TIM0;                              /*!< (@ 0x50004A20) RTC Time Register 0                                    */\r
+  __IO uint32_t  TIM1;                              /*!< (@ 0x50004A24) RTC Time Register 1                                    */\r
+} RTC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     SCU_CLK                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_CLK)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004600) SCU_CLK Structure                                      */\r
+  __I  uint32_t  CLKSTAT;                           /*!< (@ 0x50004600) Clock Status Register                                  */\r
+  __O  uint32_t  CLKSET;                            /*!< (@ 0x50004604) CLK Set Register                                       */\r
+  __O  uint32_t  CLKCLR;                            /*!< (@ 0x50004608) CLK Clear Register                                     */\r
+  __IO uint32_t  SYSCLKCR;                          /*!< (@ 0x5000460C) System Clock Control Register                          */\r
+  __IO uint32_t  CPUCLKCR;                          /*!< (@ 0x50004610) CPU Clock Control Register                             */\r
+  __IO uint32_t  PBCLKCR;                           /*!< (@ 0x50004614) Peripheral Bus Clock Control Register                  */\r
+  __IO uint32_t  USBCLKCR;                          /*!< (@ 0x50004618) USB Clock Control Register                             */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  CCUCLKCR;                          /*!< (@ 0x50004620) CCU Clock Control Register                             */\r
+  __IO uint32_t  WDTCLKCR;                          /*!< (@ 0x50004624) WDT Clock Control Register                             */\r
+  __IO uint32_t  EXTCLKCR;                          /*!< (@ 0x50004628) External Clock Control                                 */\r
+  __IO uint32_t  MLINKCLKCR;                        /*!< (@ 0x5000462C) Multi-Link Clock Control                               */\r
+  __IO uint32_t  SLEEPCR;                           /*!< (@ 0x50004630) Sleep Control Register                                 */\r
+  __IO uint32_t  DSLEEPCR;                          /*!< (@ 0x50004634) Deep Sleep Control Register                            */\r
+  __I  uint32_t  RESERVED1[2];\r
+  __I  uint32_t  CGATSTAT0;                         /*!< (@ 0x50004640) Peripheral 0 Clock Gating Status                       */\r
+  __O  uint32_t  CGATSET0;                          /*!< (@ 0x50004644) Peripheral 0 Clock Gating Set                          */\r
+  __O  uint32_t  CGATCLR0;                          /*!< (@ 0x50004648) Peripheral 0 Clock Gating Clear                        */\r
+  __I  uint32_t  CGATSTAT1;                         /*!< (@ 0x5000464C) Peripheral 1 Clock Gating Status                       */\r
+  __O  uint32_t  CGATSET1;                          /*!< (@ 0x50004650) Peripheral 1 Clock Gating Set                          */\r
+  __O  uint32_t  CGATCLR1;                          /*!< (@ 0x50004654) Peripheral 1 Clock Gating Clear                        */\r
+  __I  uint32_t  CGATSTAT2;                         /*!< (@ 0x50004658) Peripheral 2 Clock Gating Status                       */\r
+  __O  uint32_t  CGATSET2;                          /*!< (@ 0x5000465C) Peripheral 2 Clock Gating Set                          */\r
+  __O  uint32_t  CGATCLR2;                          /*!< (@ 0x50004660) Peripheral 2 Clock Gating Clear                        */\r
+} SCU_CLK_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     SCU_OSC                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_OSC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004700) SCU_OSC Structure                                      */\r
+  __I  uint32_t  OSCHPSTAT;                         /*!< (@ 0x50004700) OSC_HP Status Register                                 */\r
+  __IO uint32_t  OSCHPCTRL;                         /*!< (@ 0x50004704) OSC_HP Control Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  CLKCALCONST;                       /*!< (@ 0x5000470C) Clock Calibration Constant Register                    */\r
+} SCU_OSC_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     SCU_PLL                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_PLL)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004710) SCU_PLL Structure                                      */\r
+  __I  uint32_t  PLLSTAT;                           /*!< (@ 0x50004710) PLL Status Register                                    */\r
+  __IO uint32_t  PLLCON0;                           /*!< (@ 0x50004714) PLL Configuration 0 Register                           */\r
+  __IO uint32_t  PLLCON1;                           /*!< (@ 0x50004718) PLL Configuration 1 Register                           */\r
+  __IO uint32_t  PLLCON2;                           /*!< (@ 0x5000471C) PLL Configuration 2 Register                           */\r
+  __I  uint32_t  USBPLLSTAT;                        /*!< (@ 0x50004720) USB PLL Status Register                                */\r
+  __IO uint32_t  USBPLLCON;                         /*!< (@ 0x50004724) USB PLL Configuration Register                         */\r
+  __I  uint32_t  RESERVED0[4];\r
+  __I  uint32_t  CLKMXSTAT;                         /*!< (@ 0x50004738) Clock Multiplexing Status Register                     */\r
+} SCU_PLL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   SCU_GENERAL                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_GENERAL)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004000) SCU_GENERAL Structure                                  */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50004000) SCU Module ID Register                                 */\r
+  __I  uint32_t  IDCHIP;                            /*!< (@ 0x50004004) Chip ID Register                                       */\r
+  __I  uint32_t  IDMANUF;                           /*!< (@ 0x50004008) Manufactory ID Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  STCON;                             /*!< (@ 0x50004010) Startup Configuration Register                         */\r
+  __I  uint32_t  RESERVED1[6];\r
+  __IO uint32_t  GPR[2];                            /*!< (@ 0x5000402C) General Purpose Register 0                             */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  CCUCON;                            /*!< (@ 0x5000404C) CCU Control Register                                   */\r
+  __I  uint32_t  RESERVED3[15];\r
+  __IO uint32_t  DTSCON;                            /*!< (@ 0x5000408C) Die Temperature Sensor Control Register                */\r
+  __I  uint32_t  DTSSTAT;                           /*!< (@ 0x50004090) Die Temperature Sensor Status Register                 */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  GORCEN[2];                         /*!< (@ 0x500040A0) Out of Range Comparator Enable Register 0              */\r
+  __IO uint32_t  DTEMPLIM;                          /*!< (@ 0x500040A8) Die Temperature Sensor Limit Register                  */\r
+  __I  uint32_t  DTEMPALARM;                        /*!< (@ 0x500040AC) Die Temperature Sensor Alarm Register                  */\r
+  __I  uint32_t  RESERVED5[5];\r
+  __I  uint32_t  MIRRSTS;                           /*!< (@ 0x500040C4) Mirror Write Status Register                           */\r
+  __IO uint32_t  RMACR;                             /*!< (@ 0x500040C8) Retention Memory Access Control Register               */\r
+  __IO uint32_t  RMDATA;                            /*!< (@ 0x500040CC) Retention Memory Access Data Register                  */\r
+  __I  uint32_t  MIRRALLSTAT;                       /*!< (@ 0x500040D0) Mirror All Status                                      */\r
+  __O  uint32_t  MIRRALLREQ;                        /*!< (@ 0x500040D4) Mirror All Request                                     */\r
+} SCU_GENERAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  SCU_INTERRUPT                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_INTERRUPT)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004074) SCU_INTERRUPT Structure                                */\r
+  __I  uint32_t  SRSTAT;                            /*!< (@ 0x50004074) SCU Service Request Status                             */\r
+  __I  uint32_t  SRRAW;                             /*!< (@ 0x50004078) SCU Raw Service Request Status                         */\r
+  __IO uint32_t  SRMSK;                             /*!< (@ 0x5000407C) SCU Service Request Mask                               */\r
+  __O  uint32_t  SRCLR;                             /*!< (@ 0x50004080) SCU Service Request Clear                              */\r
+  __O  uint32_t  SRSET;                             /*!< (@ 0x50004084) SCU Service Request Set                                */\r
+  __IO uint32_t  NMIREQEN;                          /*!< (@ 0x50004088) SCU Service Request Mask                               */\r
+} SCU_INTERRUPT_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   SCU_PARITY                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_PARITY)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x5000413C) SCU_PARITY Structure                                   */\r
+  __IO uint32_t  PEEN;                              /*!< (@ 0x5000413C) Parity Error Enable Register                           */\r
+  __IO uint32_t  MCHKCON;                           /*!< (@ 0x50004140) Memory Checking Control Register                       */\r
+  __IO uint32_t  PETE;                              /*!< (@ 0x50004144) Parity Error Trap Enable Register                      */\r
+  __IO uint32_t  PERSTEN;                           /*!< (@ 0x50004148) Parity Error Reset Enable Register                     */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  PEFLAG;                            /*!< (@ 0x50004150) Parity Error Flag Register                             */\r
+  __IO uint32_t  PMTPR;                             /*!< (@ 0x50004154) Parity Memory Test Pattern Register                    */\r
+  __IO uint32_t  PMTSR;                             /*!< (@ 0x50004158) Parity Memory Test Select Register                     */\r
+} SCU_PARITY_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    SCU_TRAP                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_TRAP)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004160) SCU_TRAP Structure                                     */\r
+  __I  uint32_t  TRAPSTAT;                          /*!< (@ 0x50004160) Trap Status Register                                   */\r
+  __I  uint32_t  TRAPRAW;                           /*!< (@ 0x50004164) Trap Raw Status Register                               */\r
+  __IO uint32_t  TRAPDIS;                           /*!< (@ 0x50004168) Trap Disable Register                                  */\r
+  __O  uint32_t  TRAPCLR;                           /*!< (@ 0x5000416C) Trap Clear Register                                    */\r
+  __O  uint32_t  TRAPSET;                           /*!< (@ 0x50004170) Trap Set Register                                      */\r
+} SCU_TRAP_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  SCU_HIBERNATE                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_HIBERNATE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004300) SCU_HIBERNATE Structure                                */\r
+  __I  uint32_t  HDSTAT;                            /*!< (@ 0x50004300) Hibernate Domain Status Register                       */\r
+  __O  uint32_t  HDCLR;                             /*!< (@ 0x50004304) Hibernate Domain Status Clear Register                 */\r
+  __O  uint32_t  HDSET;                             /*!< (@ 0x50004308) Hibernate Domain Status Set Register                   */\r
+  __IO uint32_t  HDCR;                              /*!< (@ 0x5000430C) Hibernate Domain Control Register                      */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  OSCSICTRL;                         /*!< (@ 0x50004314) fOSI Control Register                                  */\r
+  __I  uint32_t  OSCULSTAT;                         /*!< (@ 0x50004318) OSC_ULP Status Register                                */\r
+  __IO uint32_t  OSCULCTRL;                         /*!< (@ 0x5000431C) OSC_ULP Control Register                               */\r
+  __IO uint32_t  LPACCONF;                          /*!< (@ 0x50004320) Analog Wake-up Configuration Register                  */\r
+  __IO uint32_t  LPACTH0;                           /*!< (@ 0x50004324) LPAC Threshold Register 0                              */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  LPACST;                            /*!< (@ 0x5000432C) Hibernate Analog Control State Register                */\r
+  __O  uint32_t  LPACCLR;                           /*!< (@ 0x50004330) LPAC Control Clear Register                            */\r
+  __O  uint32_t  LPACSET;                           /*!< (@ 0x50004334) LPAC Control Set Register                              */\r
+  __I  uint32_t  HINTST;                            /*!< (@ 0x50004338) Hibernate Internal Control State Register              */\r
+  __O  uint32_t  HINTCLR;                           /*!< (@ 0x5000433C) Hibernate Internal Control Clear Register              */\r
+  __O  uint32_t  HINTSET;                           /*!< (@ 0x50004340) Hibernate Internal Control Set Register                */\r
+} SCU_HIBERNATE_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    SCU_POWER                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_POWER)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004200) SCU_POWER Structure                                    */\r
+  __I  uint32_t  PWRSTAT;                           /*!< (@ 0x50004200) PCU Status Register                                    */\r
+  __O  uint32_t  PWRSET;                            /*!< (@ 0x50004204) PCU Set Control Register                               */\r
+  __O  uint32_t  PWRCLR;                            /*!< (@ 0x50004208) PCU Clear Control Register                             */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  EVRSTAT;                           /*!< (@ 0x50004210) EVR Status Register                                    */\r
+  __I  uint32_t  EVRVADCSTAT;                       /*!< (@ 0x50004214) EVR VADC Status Register                               */\r
+  __I  uint32_t  RESERVED1[5];\r
+  __IO uint32_t  PWRMON;                            /*!< (@ 0x5000422C) Power Monitor Control                                  */\r
+} SCU_POWER_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    SCU_RESET                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_RESET)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004400) SCU_RESET Structure                                    */\r
+  __I  uint32_t  RSTSTAT;                           /*!< (@ 0x50004400) RCU Reset Status                                       */\r
+  __O  uint32_t  RSTSET;                            /*!< (@ 0x50004404) RCU Reset Set Register                                 */\r
+  __O  uint32_t  RSTCLR;                            /*!< (@ 0x50004408) RCU Reset Clear Register                               */\r
+  __I  uint32_t  PRSTAT0;                           /*!< (@ 0x5000440C) RCU Peripheral 0 Reset Status                          */\r
+  __O  uint32_t  PRSET0;                            /*!< (@ 0x50004410) RCU Peripheral 0 Reset Set                             */\r
+  __O  uint32_t  PRCLR0;                            /*!< (@ 0x50004414) RCU Peripheral 0 Reset Clear                           */\r
+  __I  uint32_t  PRSTAT1;                           /*!< (@ 0x50004418) RCU Peripheral 1 Reset Status                          */\r
+  __O  uint32_t  PRSET1;                            /*!< (@ 0x5000441C) RCU Peripheral 1 Reset Set                             */\r
+  __O  uint32_t  PRCLR1;                            /*!< (@ 0x50004420) RCU Peripheral 1 Reset Clear                           */\r
+  __I  uint32_t  PRSTAT2;                           /*!< (@ 0x50004424) RCU Peripheral 2 Reset Status                          */\r
+  __O  uint32_t  PRSET2;                            /*!< (@ 0x50004428) RCU Peripheral 2 Reset Set                             */\r
+  __O  uint32_t  PRCLR2;                            /*!< (@ 0x5000442C) RCU Peripheral 2 Reset Clear                           */\r
+} SCU_RESET_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                 LEDTS [LEDTS0]                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief LED and Touch Sense Unit 0 (LEDTS)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48010000) LEDTS Structure                                        */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x48010000) Module Identification Register                         */\r
+  __IO uint32_t  GLOBCTL;                           /*!< (@ 0x48010004) Global Control Register                                */\r
+  __IO uint32_t  FNCTL;                             /*!< (@ 0x48010008) Function Control Register                              */\r
+  __O  uint32_t  EVFR;                              /*!< (@ 0x4801000C) Event Flag Register                                    */\r
+  __IO uint32_t  TSVAL;                             /*!< (@ 0x48010010) Touch-sense TS-Counter Value                           */\r
+  __IO uint32_t  LINE0;                             /*!< (@ 0x48010014) Line Pattern Register 0                                */\r
+  __IO uint32_t  LINE1;                             /*!< (@ 0x48010018) Line Pattern Register 1                                */\r
+  __IO uint32_t  LDCMP0;                            /*!< (@ 0x4801001C) LED Compare Register 0                                 */\r
+  __IO uint32_t  LDCMP1;                            /*!< (@ 0x48010020) LED Compare Register 1                                 */\r
+  __IO uint32_t  TSCMP0;                            /*!< (@ 0x48010024) Touch-sense Compare Register 0                         */\r
+  __IO uint32_t  TSCMP1;                            /*!< (@ 0x48010028) Touch-sense Compare Register 1                         */\r
+} LEDTS0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   USB [USB0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Bus (USB)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50040000) USB Structure                                          */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  GAHBCFG;                           /*!< (@ 0x50040008) AHB Configuration Register                             */\r
+  __IO uint32_t  GUSBCFG;                           /*!< (@ 0x5004000C) USB Configuration Register                             */\r
+  __IO uint32_t  GRSTCTL;                           /*!< (@ 0x50040010) Reset Register                                         */\r
+  __IO uint32_t  GINTSTS;                           /*!< (@ 0x50040014) Interrupt Register                                     */\r
+  __IO uint32_t  GINTMSK;                           /*!< (@ 0x50040018) Interrupt Mask Register                                */\r
+  __I  uint32_t  GRXSTSR;                           /*!< (@ 0x5004001C) Receive Status Debug Read Register                     */\r
+  __I  uint32_t  GRXSTSP;                           /*!< (@ 0x50040020) Receive Status Read and Pop Register                   */\r
+  __IO uint32_t  GRXFSIZ;                           /*!< (@ 0x50040024) Receive FIFO Size Register                             */\r
+  __IO uint32_t  GNPTXFSIZ;                         /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register               */\r
+  __I  uint32_t  RESERVED1[4];\r
+  __IO uint32_t  GUID;                              /*!< (@ 0x5004003C) USB Module Identification Register                     */\r
+  __I  uint32_t  RESERVED2[7];\r
+  __IO uint32_t  GDFIFOCFG;                         /*!< (@ 0x5004005C) Global DFIFO Software Config Register                  */\r
+  __I  uint32_t  RESERVED3[41];\r
+  __IO uint32_t  DIEPTXF1;                          /*!< (@ 0x50040104) Device IN Endpoint 1 Transmit FIFO Size Register       */\r
+  __IO uint32_t  DIEPTXF2;                          /*!< (@ 0x50040108) Device IN Endpoint 2 Transmit FIFO Size Register       */\r
+  __IO uint32_t  DIEPTXF3;                          /*!< (@ 0x5004010C) Device IN Endpoint 3 Transmit FIFO Size Register       */\r
+  __IO uint32_t  DIEPTXF4;                          /*!< (@ 0x50040110) Device IN Endpoint 4 Transmit FIFO Size Register       */\r
+  __IO uint32_t  DIEPTXF5;                          /*!< (@ 0x50040114) Device IN Endpoint 5 Transmit FIFO Size Register       */\r
+  __IO uint32_t  DIEPTXF6;                          /*!< (@ 0x50040118) Device IN Endpoint 6 Transmit FIFO Size Register       */\r
+  __I  uint32_t  RESERVED4[441];\r
+  __IO uint32_t  DCFG;                              /*!< (@ 0x50040800) Device Configuration Register                          */\r
+  __IO uint32_t  DCTL;                              /*!< (@ 0x50040804) Device Control Register                                */\r
+  __I  uint32_t  DSTS;                              /*!< (@ 0x50040808) Device Status Register                                 */\r
+  __I  uint32_t  RESERVED5;\r
+  __IO uint32_t  DIEPMSK;                           /*!< (@ 0x50040810) Device IN Endpoint Common Interrupt Mask Register      */\r
+  __IO uint32_t  DOEPMSK;                           /*!< (@ 0x50040814) Device OUT Endpoint Common Interrupt Mask Register     */\r
+  __I  uint32_t  DAINT;                             /*!< (@ 0x50040818) Device All Endpoints Interrupt Register                */\r
+  __IO uint32_t  DAINTMSK;                          /*!< (@ 0x5004081C) Device All Endpoints Interrupt Mask Register           */\r
+  __I  uint32_t  RESERVED6[2];\r
+  __IO uint32_t  DVBUSDIS;                          /*!< (@ 0x50040828) Device VBUS Discharge Time Register                    */\r
+  __IO uint32_t  DVBUSPULSE;                        /*!< (@ 0x5004082C) Device VBUS Pulsing Time Register                      */\r
+  __I  uint32_t  RESERVED7;\r
+  __IO uint32_t  DIEPEMPMSK;                        /*!< (@ 0x50040834) Device IN Endpoint FIFO Empty Interrupt Mask\r
+                                                         Register                                                              */\r
+  __I  uint32_t  RESERVED8[370];\r
+  __IO uint32_t  PCGCCTL;                           /*!< (@ 0x50040E00) Power and Clock Gating Control Register                */\r
+} USB0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    USB0_EP0                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Bus (USB0_EP0)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50040900) USB0_EP0 Structure                                     */\r
+  __IO uint32_t  DIEPCTL0;                          /*!< (@ 0x50040900) Device Control IN Endpoint Control Register            */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DIEPINT0;                          /*!< (@ 0x50040908) Device Endpoint Interrupt Register                     */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  DIEPTSIZ0;                         /*!< (@ 0x50040910) Device IN Endpoint Transfer Size Register              */\r
+  __IO uint32_t  DIEPDMA0;                          /*!< (@ 0x50040914) Device Endpoint DMA Address Register                   */\r
+  __I  uint32_t  DTXFSTS0;                          /*!< (@ 0x50040918) Device IN Endpoint Transmit FIFO Status Register       */\r
+  __I  uint32_t  DIEPDMAB0;                         /*!< (@ 0x5004091C) Device Endpoint DMA Buffer Address Register            */\r
+  __I  uint32_t  RESERVED2[120];\r
+  __IO uint32_t  DOEPCTL0;                          /*!< (@ 0x50040B00) Device Control OUT Endpoint Control Register           */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  DOEPINT0;                          /*!< (@ 0x50040B08) Device Endpoint Interrupt Register                     */\r
+  __I  uint32_t  RESERVED4;\r
+  __IO uint32_t  DOEPTSIZ0;                         /*!< (@ 0x50040B10) Device OUT Endpoint Transfer Size Register             */\r
+  __IO uint32_t  DOEPDMA0;                          /*!< (@ 0x50040B14) Device Endpoint DMA Address Register                   */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  DOEPDMAB0;                         /*!< (@ 0x50040B1C) Device Endpoint DMA Buffer Address Register            */\r
+} USB0_EP0_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                USB_EP [USB0_EP1]               ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Bus (USB_EP)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50040920) USB_EP Structure                                       */\r
+  \r
+  union {\r
+    __IO uint32_t  DIEPCTL_INTBULK;                 /*!< (@ 0x50040920) Device Endpoint Control Register [INTBULK]             */\r
+    __IO uint32_t  DIEPCTL_ISOCONT;                 /*!< (@ 0x50040920) Device Endpoint Control Register [ISOCONT]             */\r
+  };\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DIEPINT;                           /*!< (@ 0x50040928) Device Endpoint Interrupt Register                     */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  DIEPTSIZ;                          /*!< (@ 0x50040930) Device Endpoint Transfer Size Register                 */\r
+  __IO uint32_t  DIEPDMA;                           /*!< (@ 0x50040934) Device Endpoint DMA Address Register                   */\r
+  __I  uint32_t  DTXFSTS;                           /*!< (@ 0x50040938) Device IN Endpoint Transmit FIFO Status Register       */\r
+  __I  uint32_t  DIEPDMAB;                          /*!< (@ 0x5004093C) Device Endpoint DMA Buffer Address Register            */\r
+  __I  uint32_t  RESERVED2[120];\r
+  \r
+  union {\r
+    __IO uint32_t  DOEPCTL_INTBULK;                 /*!< (@ 0x50040B20) Device Endpoint Control Register [INTBULK]             */\r
+    __IO uint32_t  DOEPCTL_ISOCONT;                 /*!< (@ 0x50040B20) Device Endpoint Control Register [ISOCONT]             */\r
+  };\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  DOEPINT;                           /*!< (@ 0x50040B28) Device Endpoint Interrupt Register                     */\r
+  __I  uint32_t  RESERVED4;\r
+  \r
+  union {\r
+    __IO uint32_t  DOEPTSIZ_CONTROL;                /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [CONT]          */\r
+    __IO uint32_t  DOEPTSIZ_ISO;                    /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [ISO]           */\r
+  };\r
+  __IO uint32_t  DOEPDMA;                           /*!< (@ 0x50040B34) Device Endpoint DMA Address Register                   */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  DOEPDMAB;                          /*!< (@ 0x50040B3C) Device Endpoint DMA Buffer Address Register            */\r
+} USB0_EP_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  USIC [USIC0]                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Interface Controller 0 (USIC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40030008) USIC Structure                                         */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x40030008) Module Identification Register                         */\r
+} USIC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================               USIC_CH [USIC0_CH0]              ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Interface Controller 0 (USIC_CH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40030000) USIC_CH Structure                                      */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  CCFG;                              /*!< (@ 0x40030004) Channel Configuration Register                         */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  KSCFG;                             /*!< (@ 0x4003000C) Kernel State Configuration Register                    */\r
+  __IO uint32_t  FDR;                               /*!< (@ 0x40030010) Fractional Divider Register                            */\r
+  __IO uint32_t  BRG;                               /*!< (@ 0x40030014) Baud Rate Generator Register                           */\r
+  __IO uint32_t  INPR;                              /*!< (@ 0x40030018) Interrupt Node Pointer Register                        */\r
+  __IO uint32_t  DX0CR;                             /*!< (@ 0x4003001C) Input Control Register 0                               */\r
+  __IO uint32_t  DX1CR;                             /*!< (@ 0x40030020) Input Control Register 1                               */\r
+  __IO uint32_t  DX2CR;                             /*!< (@ 0x40030024) Input Control Register 2                               */\r
+  __IO uint32_t  DX3CR;                             /*!< (@ 0x40030028) Input Control Register 3                               */\r
+  __IO uint32_t  DX4CR;                             /*!< (@ 0x4003002C) Input Control Register 4                               */\r
+  __IO uint32_t  DX5CR;                             /*!< (@ 0x40030030) Input Control Register 5                               */\r
+  __IO uint32_t  SCTR;                              /*!< (@ 0x40030034) Shift Control Register                                 */\r
+  __IO uint32_t  TCSR;                              /*!< (@ 0x40030038) Transmit Control/Status Register                       */\r
+  \r
+  union {\r
+    __IO uint32_t  PCR_IICMode;                     /*!< (@ 0x4003003C) Protocol Control Register [IIC Mode]                   */\r
+    __IO uint32_t  PCR_IISMode;                     /*!< (@ 0x4003003C) Protocol Control Register [IIS Mode]                   */\r
+    __IO uint32_t  PCR_SSCMode;                     /*!< (@ 0x4003003C) Protocol Control Register [SSC Mode]                   */\r
+    __IO uint32_t  PCR;                             /*!< (@ 0x4003003C) Protocol Control Register                              */\r
+    __IO uint32_t  PCR_ASCMode;                     /*!< (@ 0x4003003C) Protocol Control Register [ASC Mode]                   */\r
+  };\r
+  __IO uint32_t  CCR;                               /*!< (@ 0x40030040) Channel Control Register                               */\r
+  __IO uint32_t  CMTR;                              /*!< (@ 0x40030044) Capture Mode Timer Register                            */\r
+  \r
+  union {\r
+    __IO uint32_t  PSR_IICMode;                     /*!< (@ 0x40030048) Protocol Status Register [IIC Mode]                    */\r
+    __IO uint32_t  PSR_IISMode;                     /*!< (@ 0x40030048) Protocol Status Register [IIS Mode]                    */\r
+    __IO uint32_t  PSR_SSCMode;                     /*!< (@ 0x40030048) Protocol Status Register [SSC Mode]                    */\r
+    __IO uint32_t  PSR;                             /*!< (@ 0x40030048) Protocol Status Register                               */\r
+    __IO uint32_t  PSR_ASCMode;                     /*!< (@ 0x40030048) Protocol Status Register [ASC Mode]                    */\r
+  };\r
+  __O  uint32_t  PSCR;                              /*!< (@ 0x4003004C) Protocol Status Clear Register                         */\r
+  __I  uint32_t  RBUFSR;                            /*!< (@ 0x40030050) Receiver Buffer Status Register                        */\r
+  __I  uint32_t  RBUF;                              /*!< (@ 0x40030054) Receiver Buffer Register                               */\r
+  __I  uint32_t  RBUFD;                             /*!< (@ 0x40030058) Receiver Buffer Register for Debugger                  */\r
+  __I  uint32_t  RBUF0;                             /*!< (@ 0x4003005C) Receiver Buffer Register 0                             */\r
+  __I  uint32_t  RBUF1;                             /*!< (@ 0x40030060) Receiver Buffer Register 1                             */\r
+  __I  uint32_t  RBUF01SR;                          /*!< (@ 0x40030064) Receiver Buffer 01 Status Register                     */\r
+  __O  uint32_t  FMR;                               /*!< (@ 0x40030068) Flag Modification Register                             */\r
+  __I  uint32_t  RESERVED2[5];\r
+  __IO uint32_t  TBUF[32];                          /*!< (@ 0x40030080) Transmit Buffer                                        */\r
+  __IO uint32_t  BYP;                               /*!< (@ 0x40030100) Bypass Data Register                                   */\r
+  __IO uint32_t  BYPCR;                             /*!< (@ 0x40030104) Bypass Control Register                                */\r
+  __IO uint32_t  TBCTR;                             /*!< (@ 0x40030108) Transmitter Buffer Control Register                    */\r
+  __IO uint32_t  RBCTR;                             /*!< (@ 0x4003010C) Receiver Buffer Control Register                       */\r
+  __I  uint32_t  TRBPTR;                            /*!< (@ 0x40030110) Transmit/Receive Buffer Pointer Register               */\r
+  __IO uint32_t  TRBSR;                             /*!< (@ 0x40030114) Transmit/Receive Buffer Status Register                */\r
+  __O  uint32_t  TRBSCR;                            /*!< (@ 0x40030118) Transmit/Receive Buffer Status Clear Register          */\r
+  __I  uint32_t  OUTR;                              /*!< (@ 0x4003011C) Receiver Buffer Output Register                        */\r
+  __I  uint32_t  OUTDR;                             /*!< (@ 0x40030120) Receiver Buffer Output Register L for Debugger         */\r
+  __I  uint32_t  RESERVED3[23];\r
+  __O  uint32_t  IN[32];                            /*!< (@ 0x40030180) Transmit FIFO Buffer                                   */\r
+} USIC_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       CAN                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Controller Area Networks (CAN)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48014000) CAN Structure                                          */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x48014000) CAN Clock Control Register                             */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x48014008) Module Identification Register                         */\r
+  __IO uint32_t  FDR;                               /*!< (@ 0x4801400C) CAN Fractional Divider Register                        */\r
+  __I  uint32_t  RESERVED1[60];\r
+  __I  uint32_t  LIST[8];                           /*!< (@ 0x48014100) List Register                                          */\r
+  __I  uint32_t  RESERVED2[8];\r
+  __IO uint32_t  MSPND[8];                          /*!< (@ 0x48014140) Message Pending Register                               */\r
+  __I  uint32_t  RESERVED3[8];\r
+  __I  uint32_t  MSID[8];                           /*!< (@ 0x48014180) Message Index Register                                 */\r
+  __I  uint32_t  RESERVED4[8];\r
+  __IO uint32_t  MSIMASK;                           /*!< (@ 0x480141C0) Message Index Mask Register                            */\r
+  __IO uint32_t  PANCTR;                            /*!< (@ 0x480141C4) Panel Control Register                                 */\r
+  __IO uint32_t  MCR;                               /*!< (@ 0x480141C8) Module Control Register                                */\r
+  __O  uint32_t  MITR;                              /*!< (@ 0x480141CC) Module Interrupt Trigger Register                      */\r
+} CAN_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              CAN_NODE [CAN_NODE0]              ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Controller Area Networks (CAN_NODE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48014200) CAN_NODE Structure                                     */\r
+  __IO uint32_t  NCR;                               /*!< (@ 0x48014200) Node Control Register                                  */\r
+  __IO uint32_t  NSR;                               /*!< (@ 0x48014204) Node Status Register                                   */\r
+  __IO uint32_t  NIPR;                              /*!< (@ 0x48014208) Node Interrupt Pointer Register                        */\r
+  __IO uint32_t  NPCR;                              /*!< (@ 0x4801420C) Node Port Control Register                             */\r
+  __IO uint32_t  NBTR;                              /*!< (@ 0x48014210) Node Bit Timing Register                               */\r
+  __IO uint32_t  NECNT;                             /*!< (@ 0x48014214) Node Error Counter Register                            */\r
+  __IO uint32_t  NFCR;                              /*!< (@ 0x48014218) Node Frame Counter Register                            */\r
+} CAN_NODE_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                CAN_MO [CAN_MO0]                ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Controller Area Networks (CAN_MO)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48015000) CAN_MO Structure                                       */\r
+  __IO uint32_t  MOFCR;                             /*!< (@ 0x48015000) Message Object Function Control Register               */\r
+  __IO uint32_t  MOFGPR;                            /*!< (@ 0x48015004) Message Object FIFO/Gateway Pointer Register           */\r
+  __IO uint32_t  MOIPR;                             /*!< (@ 0x48015008) Message Object Interrupt Pointer Register              */\r
+  __IO uint32_t  MOAMR;                             /*!< (@ 0x4801500C) Message Object Acceptance Mask Register                */\r
+  __IO uint32_t  MODATAL;                           /*!< (@ 0x48015010) Message Object Data Register Low                       */\r
+  __IO uint32_t  MODATAH;                           /*!< (@ 0x48015014) Message Object Data Register High                      */\r
+  __IO uint32_t  MOAR;                              /*!< (@ 0x48015018) Message Object Arbitration Register                    */\r
+  \r
+  union {\r
+    __I  uint32_t  MOSTAT;                          /*!< (@ 0x4801501C) Message Object Status Register                         */\r
+    __O  uint32_t  MOCTR;                           /*!< (@ 0x4801501C) Message Object Control Register                        */\r
+  };\r
+} CAN_MO_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      VADC                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Analog to Digital Converter (VADC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40004000) VADC Structure                                         */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x40004000) Clock Control Register                                 */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x40004008) Module Identification Register                         */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __IO uint32_t  OCS;                               /*!< (@ 0x40004028) OCDS Control and Status Register                       */\r
+  __I  uint32_t  RESERVED2[21];\r
+  __IO uint32_t  GLOBCFG;                           /*!< (@ 0x40004080) Global Configuration Register                          */\r
+  __I  uint32_t  RESERVED3[7];\r
+  __IO uint32_t  GLOBICLASS[2];                     /*!< (@ 0x400040A0) Input Class Register, Global                           */\r
+  __I  uint32_t  RESERVED4[4];\r
+  __IO uint32_t  GLOBBOUND;                         /*!< (@ 0x400040B8) Global Boundary Select Register                        */\r
+  __I  uint32_t  RESERVED5[9];\r
+  __IO uint32_t  GLOBEFLAG;                         /*!< (@ 0x400040E0) Global Event Flag Register                             */\r
+  __I  uint32_t  RESERVED6[23];\r
+  __IO uint32_t  GLOBEVNP;                          /*!< (@ 0x40004140) Global Event Node Pointer Register                     */\r
+  __I  uint32_t  RESERVED7[7];\r
+  __IO uint32_t  GLOBTF;                            /*!< (@ 0x40004160) Global Test Functions Register                         */\r
+  __I  uint32_t  RESERVED8[7];\r
+  __IO uint32_t  BRSSEL[4];                         /*!< (@ 0x40004180) Background Request Source Channel Select Register      */\r
+  __I  uint32_t  RESERVED9[12];\r
+  __IO uint32_t  BRSPND[4];                         /*!< (@ 0x400041C0) Background Request Source Pending Register             */\r
+  __I  uint32_t  RESERVED10[12];\r
+  __IO uint32_t  BRSCTRL;                           /*!< (@ 0x40004200) Background Request Source Control Register             */\r
+  __IO uint32_t  BRSMR;                             /*!< (@ 0x40004204) Background Request Source Mode Register                */\r
+  __I  uint32_t  RESERVED11[30];\r
+  __IO uint32_t  GLOBRCR;                           /*!< (@ 0x40004280) Global Result Control Register                         */\r
+  __I  uint32_t  RESERVED12[31];\r
+  __IO uint32_t  GLOBRES;                           /*!< (@ 0x40004300) Global Result Register                                 */\r
+  __I  uint32_t  RESERVED13[31];\r
+  __IO uint32_t  GLOBRESD;                          /*!< (@ 0x40004380) Global Result Register, Debug                          */\r
+  __I  uint32_t  RESERVED14[27];\r
+  __IO uint32_t  EMUXSEL;                           /*!< (@ 0x400043F0) External Multiplexer Select Register                   */\r
+} VADC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                VADC_G [VADC_G0]                ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Analog to Digital Converter (VADC_G)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40004400) VADC_G Structure                                       */\r
+  __I  uint32_t  RESERVED0[32];\r
+  __IO uint32_t  ARBCFG;                            /*!< (@ 0x40004480) Arbitration Configuration Register                     */\r
+  __IO uint32_t  ARBPR;                             /*!< (@ 0x40004484) Arbitration Priority Register                          */\r
+  __IO uint32_t  CHASS;                             /*!< (@ 0x40004488) Channel Assignment Register                            */\r
+  __I  uint32_t  RESERVED1[5];\r
+  __IO uint32_t  ICLASS[2];                         /*!< (@ 0x400044A0) Input Class Register                                   */\r
+  __I  uint32_t  RESERVED2[2];\r
+  __IO uint32_t  ALIAS;                             /*!< (@ 0x400044B0) Alias Register                                         */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  BOUND;                             /*!< (@ 0x400044B8) Boundary Select Register                               */\r
+  __I  uint32_t  RESERVED4;\r
+  __IO uint32_t  SYNCTR;                            /*!< (@ 0x400044C0) Synchronization Control Register                       */\r
+  __I  uint32_t  RESERVED5;\r
+  __IO uint32_t  BFL;                               /*!< (@ 0x400044C8) Boundary Flag Register                                 */\r
+  __I  uint32_t  RESERVED6[13];\r
+  __IO uint32_t  QCTRL0;                            /*!< (@ 0x40004500) Queue 0 Source Control Register                        */\r
+  __IO uint32_t  QMR0;                              /*!< (@ 0x40004504) Queue 0 Mode Register                                  */\r
+  __I  uint32_t  QSR0;                              /*!< (@ 0x40004508) Queue 0 Status Register                                */\r
+  __I  uint32_t  Q0R0;                              /*!< (@ 0x4000450C) Queue 0 Register 0                                     */\r
+  \r
+  union {\r
+    __I  uint32_t  QBUR0;                           /*!< (@ 0x40004510) Queue 0 Backup Register                                */\r
+    __O  uint32_t  QINR0;                           /*!< (@ 0x40004510) Queue 0 Input Register                                 */\r
+  };\r
+  __I  uint32_t  RESERVED7[3];\r
+  __IO uint32_t  ASCTRL;                            /*!< (@ 0x40004520) Autoscan Source Control Register                       */\r
+  __IO uint32_t  ASMR;                              /*!< (@ 0x40004524) Autoscan Source Mode Register                          */\r
+  __IO uint32_t  ASSEL;                             /*!< (@ 0x40004528) Autoscan Source Channel Select Register                */\r
+  __IO uint32_t  ASPND;                             /*!< (@ 0x4000452C) Autoscan Source Pending Register                       */\r
+  __I  uint32_t  RESERVED8[20];\r
+  __IO uint32_t  CEFLAG;                            /*!< (@ 0x40004580) Channel Event Flag Register                            */\r
+  __IO uint32_t  REFLAG;                            /*!< (@ 0x40004584) Result Event Flag Register                             */\r
+  __IO uint32_t  SEFLAG;                            /*!< (@ 0x40004588) Source Event Flag Register                             */\r
+  __I  uint32_t  RESERVED9;\r
+  __O  uint32_t  CEFCLR;                            /*!< (@ 0x40004590) Channel Event Flag Clear Register                      */\r
+  __O  uint32_t  REFCLR;                            /*!< (@ 0x40004594) Result Event Flag Clear Register                       */\r
+  __O  uint32_t  SEFCLR;                            /*!< (@ 0x40004598) Source Event Flag Clear Register                       */\r
+  __I  uint32_t  RESERVED10;\r
+  __IO uint32_t  CEVNP0;                            /*!< (@ 0x400045A0) Channel Event Node Pointer Register 0                  */\r
+  __I  uint32_t  RESERVED11[3];\r
+  __IO uint32_t  REVNP0;                            /*!< (@ 0x400045B0) Result Event Node Pointer Register 0                   */\r
+  __IO uint32_t  REVNP1;                            /*!< (@ 0x400045B4) Result Event Node Pointer Register 1                   */\r
+  __I  uint32_t  RESERVED12[2];\r
+  __IO uint32_t  SEVNP;                             /*!< (@ 0x400045C0) Source Event Node Pointer Register                     */\r
+  __I  uint32_t  RESERVED13;\r
+  __O  uint32_t  SRACT;                             /*!< (@ 0x400045C8) Service Request Software Activation Trigger            */\r
+  __I  uint32_t  RESERVED14[9];\r
+  __IO uint32_t  EMUXCTR;                           /*!< (@ 0x400045F0) External Multiplexer Control Register                  */\r
+  __I  uint32_t  RESERVED15;\r
+  __IO uint32_t  VFR;                               /*!< (@ 0x400045F8) Valid Flag Register                                    */\r
+  __I  uint32_t  RESERVED16;\r
+  __IO uint32_t  CHCTR[8];                          /*!< (@ 0x40004600) Channel Ctrl. Reg.                                     */\r
+  __I  uint32_t  RESERVED17[24];\r
+  __IO uint32_t  RCR[16];                           /*!< (@ 0x40004680) Result Control Register                                */\r
+  __I  uint32_t  RESERVED18[16];\r
+  __IO uint32_t  RES[16];                           /*!< (@ 0x40004700) Result Register                                        */\r
+  __I  uint32_t  RESERVED19[16];\r
+  __I  uint32_t  RESD[16];                          /*!< (@ 0x40004780) Result Register, Debug                                 */\r
+} VADC_G_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       DAC                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Digital to Analog Converter (DAC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48018000) DAC Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x48018000) Module Identification Register                         */\r
+  __IO uint32_t  DAC0CFG0;                          /*!< (@ 0x48018004) DAC0 Configuration Register 0                          */\r
+  __IO uint32_t  DAC0CFG1;                          /*!< (@ 0x48018008) DAC0 Configuration Register 1                          */\r
+  __IO uint32_t  DAC1CFG0;                          /*!< (@ 0x4801800C) DAC1 Configuration Register 0                          */\r
+  __IO uint32_t  DAC1CFG1;                          /*!< (@ 0x48018010) DAC1 Configuration Register 1                          */\r
+  __IO uint32_t  DAC0DATA;                          /*!< (@ 0x48018014) DAC0 Data Register                                     */\r
+  __IO uint32_t  DAC1DATA;                          /*!< (@ 0x48018018) DAC1 Data Register                                     */\r
+  __IO uint32_t  DAC01DATA;                         /*!< (@ 0x4801801C) DAC01 Data Register                                    */\r
+  __IO uint32_t  DAC0PATL;                          /*!< (@ 0x48018020) DAC0 Lower Pattern Register                            */\r
+  __IO uint32_t  DAC0PATH;                          /*!< (@ 0x48018024) DAC0 Higher Pattern Register                           */\r
+  __IO uint32_t  DAC1PATL;                          /*!< (@ 0x48018028) DAC1 Lower Pattern Register                            */\r
+  __IO uint32_t  DAC1PATH;                          /*!< (@ 0x4801802C) DAC1 Higher Pattern Register                           */\r
+} DAC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  CCU4 [CCU40]                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 4 - Unit 0 (CCU4)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x4000C000) CCU4 Structure                                         */\r
+  __IO uint32_t  GCTRL;                             /*!< (@ 0x4000C000) Global Control Register                                */\r
+  __I  uint32_t  GSTAT;                             /*!< (@ 0x4000C004) Global Status Register                                 */\r
+  __O  uint32_t  GIDLS;                             /*!< (@ 0x4000C008) Global Idle Set                                        */\r
+  __O  uint32_t  GIDLC;                             /*!< (@ 0x4000C00C) Global Idle Clear                                      */\r
+  __O  uint32_t  GCSS;                              /*!< (@ 0x4000C010) Global Channel Set                                     */\r
+  __O  uint32_t  GCSC;                              /*!< (@ 0x4000C014) Global Channel Clear                                   */\r
+  __I  uint32_t  GCST;                              /*!< (@ 0x4000C018) Global Channel Status                                  */\r
+  __I  uint32_t  RESERVED0[13];\r
+  __I  uint32_t  ECRD;                              /*!< (@ 0x4000C050) Extended Capture Mode Read                             */\r
+  __I  uint32_t  RESERVED1[11];\r
+  __I  uint32_t  MIDR;                              /*!< (@ 0x4000C080) Module Identification                                  */\r
+} CCU4_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              CCU4_CC4 [CCU40_CC40]             ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x4000C100) CCU4_CC4 Structure                                     */\r
+  __IO uint32_t  INS;                               /*!< (@ 0x4000C100) Input Selector Configuration                           */\r
+  __IO uint32_t  CMC;                               /*!< (@ 0x4000C104) Connection Matrix Control                              */\r
+  __I  uint32_t  TCST;                              /*!< (@ 0x4000C108) Slice Timer Status                                     */\r
+  __O  uint32_t  TCSET;                             /*!< (@ 0x4000C10C) Slice Timer Run Set                                    */\r
+  __O  uint32_t  TCCLR;                             /*!< (@ 0x4000C110) Slice Timer Clear                                      */\r
+  __IO uint32_t  TC;                                /*!< (@ 0x4000C114) Slice Timer Control                                    */\r
+  __IO uint32_t  PSL;                               /*!< (@ 0x4000C118) Passive Level Config                                   */\r
+  __I  uint32_t  DIT;                               /*!< (@ 0x4000C11C) Dither Config                                          */\r
+  __IO uint32_t  DITS;                              /*!< (@ 0x4000C120) Dither Shadow Register                                 */\r
+  __IO uint32_t  PSC;                               /*!< (@ 0x4000C124) Prescaler Control                                      */\r
+  __IO uint32_t  FPC;                               /*!< (@ 0x4000C128) Floating Prescaler Control                             */\r
+  __IO uint32_t  FPCS;                              /*!< (@ 0x4000C12C) Floating Prescaler Shadow                              */\r
+  __I  uint32_t  PR;                                /*!< (@ 0x4000C130) Timer Period Value                                     */\r
+  __IO uint32_t  PRS;                               /*!< (@ 0x4000C134) Timer Shadow Period Value                              */\r
+  __I  uint32_t  CR;                                /*!< (@ 0x4000C138) Timer Compare Value                                    */\r
+  __IO uint32_t  CRS;                               /*!< (@ 0x4000C13C) Timer Shadow Compare Value                             */\r
+  __I  uint32_t  RESERVED0[12];\r
+  __IO uint32_t  TIMER;                             /*!< (@ 0x4000C170) Timer Value                                            */\r
+  __I  uint32_t  CV[4];                             /*!< (@ 0x4000C174) Capture Register 0                                     */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __I  uint32_t  INTS;                              /*!< (@ 0x4000C1A0) Interrupt Status                                       */\r
+  __IO uint32_t  INTE;                              /*!< (@ 0x4000C1A4) Interrupt Enable Control                               */\r
+  __IO uint32_t  SRS;                               /*!< (@ 0x4000C1A8) Service Request Selector                               */\r
+  __O  uint32_t  SWS;                               /*!< (@ 0x4000C1AC) Interrupt Status Set                                   */\r
+  __O  uint32_t  SWR;                               /*!< (@ 0x4000C1B0) Interrupt Status Clear                                 */\r
+} CCU4_CC4_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  CCU8 [CCU80]                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 8 - Unit 0 (CCU8)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40020000) CCU8 Structure                                         */\r
+  __IO uint32_t  GCTRL;                             /*!< (@ 0x40020000) Global Control Register                                */\r
+  __I  uint32_t  GSTAT;                             /*!< (@ 0x40020004) Global Status Register                                 */\r
+  __O  uint32_t  GIDLS;                             /*!< (@ 0x40020008) Global Idle Set                                        */\r
+  __O  uint32_t  GIDLC;                             /*!< (@ 0x4002000C) Global Idle Clear                                      */\r
+  __O  uint32_t  GCSS;                              /*!< (@ 0x40020010) Global Channel Set                                     */\r
+  __O  uint32_t  GCSC;                              /*!< (@ 0x40020014) Global Channel Clear                                   */\r
+  __I  uint32_t  GCST;                              /*!< (@ 0x40020018) Global Channel status                                  */\r
+  __IO uint32_t  GPCHK;                             /*!< (@ 0x4002001C) Parity Checker Configuration                           */\r
+  __I  uint32_t  RESERVED0[12];\r
+  __I  uint32_t  ECRD;                              /*!< (@ 0x40020050) Extended Capture Mode Read                             */\r
+  __I  uint32_t  RESERVED1[11];\r
+  __I  uint32_t  MIDR;                              /*!< (@ 0x40020080) Module Identification                                  */\r
+} CCU8_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              CCU8_CC8 [CCU80_CC80]             ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 8 - Unit 0 (CCU8_CC8)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40020100) CCU8_CC8 Structure                                     */\r
+  __IO uint32_t  INS;                               /*!< (@ 0x40020100) Input Selector Configuration                           */\r
+  __IO uint32_t  CMC;                               /*!< (@ 0x40020104) Connection Matrix Control                              */\r
+  __I  uint32_t  TCST;                              /*!< (@ 0x40020108) Slice Timer Status                                     */\r
+  __O  uint32_t  TCSET;                             /*!< (@ 0x4002010C) Slice Timer Run Set                                    */\r
+  __O  uint32_t  TCCLR;                             /*!< (@ 0x40020110) Slice Timer Clear                                      */\r
+  __IO uint32_t  TC;                                /*!< (@ 0x40020114) Slice Timer Control                                    */\r
+  __IO uint32_t  PSL;                               /*!< (@ 0x40020118) Passive Level Config                                   */\r
+  __I  uint32_t  DIT;                               /*!< (@ 0x4002011C) Dither Config                                          */\r
+  __IO uint32_t  DITS;                              /*!< (@ 0x40020120) Dither Shadow Register                                 */\r
+  __IO uint32_t  PSC;                               /*!< (@ 0x40020124) Prescaler Control                                      */\r
+  __IO uint32_t  FPC;                               /*!< (@ 0x40020128) Floating Prescaler Control                             */\r
+  __IO uint32_t  FPCS;                              /*!< (@ 0x4002012C) Floating Prescaler Shadow                              */\r
+  __I  uint32_t  PR;                                /*!< (@ 0x40020130) Timer Period Value                                     */\r
+  __IO uint32_t  PRS;                               /*!< (@ 0x40020134) Timer Shadow Period Value                              */\r
+  __I  uint32_t  CR1;                               /*!< (@ 0x40020138) Channel 1 Compare Value                                */\r
+  __IO uint32_t  CR1S;                              /*!< (@ 0x4002013C) Channel 1 Compare Shadow Value                         */\r
+  __I  uint32_t  CR2;                               /*!< (@ 0x40020140) Channel 2 Compare Value                                */\r
+  __IO uint32_t  CR2S;                              /*!< (@ 0x40020144) Channel 2 Compare Shadow Value                         */\r
+  __IO uint32_t  CHC;                               /*!< (@ 0x40020148) Channel Control                                        */\r
+  __IO uint32_t  DTC;                               /*!< (@ 0x4002014C) Dead Time Control                                      */\r
+  __IO uint32_t  DC1R;                              /*!< (@ 0x40020150) Channel 1 Dead Time Values                             */\r
+  __IO uint32_t  DC2R;                              /*!< (@ 0x40020154) Channel 2 Dead Time Values                             */\r
+  __I  uint32_t  RESERVED0[6];\r
+  __IO uint32_t  TIMER;                             /*!< (@ 0x40020170) Timer Value                                            */\r
+  __I  uint32_t  CV[4];                             /*!< (@ 0x40020174) Capture Register 0                                     */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __I  uint32_t  INTS;                              /*!< (@ 0x400201A0) Interrupt Status                                       */\r
+  __IO uint32_t  INTE;                              /*!< (@ 0x400201A4) Interrupt Enable Control                               */\r
+  __IO uint32_t  SRS;                               /*!< (@ 0x400201A8) Service Request Selector                               */\r
+  __O  uint32_t  SWS;                               /*!< (@ 0x400201AC) Interrupt Status Set                                   */\r
+  __O  uint32_t  SWR;                               /*!< (@ 0x400201B0) Interrupt Status Clear                                 */\r
+  __IO uint32_t  STC;                               /*!< (@ 0x400201B4) Shadow transfer control                                */\r
+} CCU8_CC8_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     HRPWM0                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief High Resolution PWM Unit (HRPWM0)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40020900) HRPWM0 Structure                                       */\r
+  __IO uint32_t  HRBSC;                             /*!< (@ 0x40020900) Bias and suspend configuration                         */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  MIDR;                              /*!< (@ 0x40020908) Module identification register                         */\r
+  __I  uint32_t  RESERVED1[2];\r
+  __IO uint32_t  GLBANA;                            /*!< (@ 0x40020914) Global Analog Configuration                            */\r
+  __I  uint32_t  RESERVED2[2];\r
+  __IO uint32_t  CSGCFG;                            /*!< (@ 0x40020920) Global CSG configuration                               */\r
+  __O  uint32_t  CSGSETG;                           /*!< (@ 0x40020924) Global CSG run bit set                                 */\r
+  __O  uint32_t  CSGCLRG;                           /*!< (@ 0x40020928) Global CSG run bit clear                               */\r
+  __I  uint32_t  CSGSTATG;                          /*!< (@ 0x4002092C) Global CSG run bit status                              */\r
+  __O  uint32_t  CSGFCG;                            /*!< (@ 0x40020930) Global CSG slope/prescaler control                     */\r
+  __I  uint32_t  CSGFSG;                            /*!< (@ 0x40020934) Global CSG slope/prescaler status                      */\r
+  __O  uint32_t  CSGTRG;                            /*!< (@ 0x40020938) Global CSG shadow/switch trigger                       */\r
+  __O  uint32_t  CSGTRC;                            /*!< (@ 0x4002093C) Global CSG shadow trigger clear                        */\r
+  __I  uint32_t  CSGTRSG;                           /*!< (@ 0x40020940) Global CSG shadow/switch status                        */\r
+  __I  uint32_t  RESERVED3[7];\r
+  __IO uint32_t  HRCCFG;                            /*!< (@ 0x40020960) Global HRC configuration                               */\r
+  __O  uint32_t  HRCSTRG;                           /*!< (@ 0x40020964) Global HRC shadow trigger set                          */\r
+  __O  uint32_t  HRCCTRG;                           /*!< (@ 0x40020968) Global HRC shadow trigger clear                        */\r
+  __I  uint32_t  HRCSTSG;                           /*!< (@ 0x4002096C) Global HRC shadow transfer status                      */\r
+  __I  uint32_t  HRGHRS;                            /*!< (@ 0x40020970) High Resolution Generation Status                      */\r
+} HRPWM0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================            HRPWM0_CSG [HRPWM0_CSG0]            ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief High Resolution PWM Unit (HRPWM0_CSG)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40020A00) HRPWM0_CSG Structure                                   */\r
+  __IO uint32_t  DCI;                               /*!< (@ 0x40020A00) External input selection                               */\r
+  __IO uint32_t  IES;                               /*!< (@ 0x40020A04) External input selection                               */\r
+  __IO uint32_t  SC;                                /*!< (@ 0x40020A08) Slope generation control                               */\r
+  __I  uint32_t  PC;                                /*!< (@ 0x40020A0C) Pulse swallow configuration                            */\r
+  __I  uint32_t  DSV1;                              /*!< (@ 0x40020A10) DAC reference value 1                                  */\r
+  __IO uint32_t  DSV2;                              /*!< (@ 0x40020A14) DAC reference value 1                                  */\r
+  __IO uint32_t  SDSV1;                             /*!< (@ 0x40020A18) Shadow reference value 1                               */\r
+  __IO uint32_t  SPC;                               /*!< (@ 0x40020A1C) Shadow Pulse swallow value                             */\r
+  __IO uint32_t  CC;                                /*!< (@ 0x40020A20) Comparator configuration                               */\r
+  __IO uint32_t  PLC;                               /*!< (@ 0x40020A24) Passive level configuration                            */\r
+  __IO uint32_t  BLV;                               /*!< (@ 0x40020A28) Comparator blanking value                              */\r
+  __IO uint32_t  SRE;                               /*!< (@ 0x40020A2C) Service request enable                                 */\r
+  __IO uint32_t  SRS;                               /*!< (@ 0x40020A30) Service request line selector                          */\r
+  __O  uint32_t  SWS;                               /*!< (@ 0x40020A34) Service request SW set                                 */\r
+  __O  uint32_t  SWC;                               /*!< (@ 0x40020A38) Service request SW clear                               */\r
+  __I  uint32_t  ISTAT;                             /*!< (@ 0x40020A3C) Service request status                                 */\r
+} HRPWM0_CSG_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================            HRPWM0_HRC [HRPWM0_HRC0]            ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief High Resolution PWM Unit (HRPWM0_HRC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40021300) HRPWM0_HRC Structure                                   */\r
+  __IO uint32_t  GC;                                /*!< (@ 0x40021300) HRC mode configuration                                 */\r
+  __IO uint32_t  PL;                                /*!< (@ 0x40021304) HRC output passive level                               */\r
+  __IO uint32_t  GSEL;                              /*!< (@ 0x40021308) HRC global control selection                           */\r
+  __IO uint32_t  TSEL;                              /*!< (@ 0x4002130C) HRC timer selection                                    */\r
+  __I  uint32_t  SC;                                /*!< (@ 0x40021310) HRC current source for shadow                          */\r
+  __I  uint32_t  DCR;                               /*!< (@ 0x40021314) HRC dead time rising value                             */\r
+  __I  uint32_t  DCF;                               /*!< (@ 0x40021318) HRC dead time falling value                            */\r
+  __I  uint32_t  CR1;                               /*!< (@ 0x4002131C) HRC rising edge value                                  */\r
+  __I  uint32_t  CR2;                               /*!< (@ 0x40021320) HRC falling edge value                                 */\r
+  __IO uint32_t  SSC;                               /*!< (@ 0x40021324) HRC next source for shadow                             */\r
+  __IO uint32_t  SDCR;                              /*!< (@ 0x40021328) HRC shadow dead time rising                            */\r
+  __IO uint32_t  SDCF;                              /*!< (@ 0x4002132C) HRC shadow dead time falling                           */\r
+  __IO uint32_t  SCR1;                              /*!< (@ 0x40021330) HRC shadow rising edge value                           */\r
+  __IO uint32_t  SCR2;                              /*!< (@ 0x40021334) HRC shadow falling edge value                          */\r
+} HRPWM0_HRC_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                 POSIF [POSIF0]                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Position Interface 0 (POSIF)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40028000) POSIF Structure                                        */\r
+  __IO uint32_t  PCONF;                             /*!< (@ 0x40028000) Service Request Processing configuration               */\r
+  __IO uint32_t  PSUS;                              /*!< (@ 0x40028004) Service Request Processing Suspend Config              */\r
+  __O  uint32_t  PRUNS;                             /*!< (@ 0x40028008) Service Request Processing Run Bit Set                 */\r
+  __O  uint32_t  PRUNC;                             /*!< (@ 0x4002800C) Service Request Processing Run Bit Clear               */\r
+  __I  uint32_t  PRUN;                              /*!< (@ 0x40028010) Service Request Processing Run Bit Status              */\r
+  __I  uint32_t  RESERVED0[3];\r
+  __I  uint32_t  MIDR;                              /*!< (@ 0x40028020) Module Identification register                         */\r
+  __I  uint32_t  RESERVED1[3];\r
+  __I  uint32_t  HALP;                              /*!< (@ 0x40028030) Hall Sensor Patterns                                   */\r
+  __IO uint32_t  HALPS;                             /*!< (@ 0x40028034) Hall Sensor Shadow Patterns                            */\r
+  __I  uint32_t  RESERVED2[2];\r
+  __I  uint32_t  MCM;                               /*!< (@ 0x40028040) Multi-Channel Pattern                                  */\r
+  __IO uint32_t  MCSM;                              /*!< (@ 0x40028044) Multi-Channel Shadow Pattern                           */\r
+  __O  uint32_t  MCMS;                              /*!< (@ 0x40028048) Multi-Channel Pattern Control set                      */\r
+  __O  uint32_t  MCMC;                              /*!< (@ 0x4002804C) Multi-Channel Pattern Control clear                    */\r
+  __I  uint32_t  MCMF;                              /*!< (@ 0x40028050) Multi-Channel Pattern Control flag                     */\r
+  __I  uint32_t  RESERVED3[3];\r
+  __IO uint32_t  QDC;                               /*!< (@ 0x40028060) Quadrature Decoder Control                             */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __I  uint32_t  PFLG;                              /*!< (@ 0x40028070) Service Request Processing Interrupt Flags             */\r
+  __IO uint32_t  PFLGE;                             /*!< (@ 0x40028074) Service Request Processing Interrupt Enable            */\r
+  __O  uint32_t  SPFLG;                             /*!< (@ 0x40028078) Service Request Processing Interrupt Set               */\r
+  __O  uint32_t  RPFLG;                             /*!< (@ 0x4002807C) Service Request Processing Interrupt Clear             */\r
+  __I  uint32_t  RESERVED5[32];\r
+  __I  uint32_t  PDBG;                              /*!< (@ 0x40028100) POSIF Debug register                                   */\r
+} POSIF_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT0                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 0 (PORT0)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028000) PORT0 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028000) Port 0 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028004) Port 0 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028010) Port 0 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028014) Port 0 Input/Output Control Register 4                 */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028018) Port 0 Input/Output Control Register 8                 */\r
+  __I  uint32_t  RESERVED1[2];\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028024) Port 0 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028040) Port 0 Pad Driver Mode 0 Register                      */\r
+  __IO uint32_t  PDR1;                              /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Register                      */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028060) Port 0 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028070) Port 0 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028074) Port 0 Pin Hardware Select Register                    */\r
+} PORT0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT1                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 1 (PORT1)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028100) PORT1 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028100) Port 1 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028104) Port 1 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028110) Port 1 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028114) Port 1 Input/Output Control Register 4                 */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028118) Port 1 Input/Output Control Register 8                 */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x4802811C) Port 1 Input/Output Control Register 12                */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028124) Port 1 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028140) Port 1 Pad Driver Mode 0 Register                      */\r
+  __IO uint32_t  PDR1;                              /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Register                      */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028160) Port 1 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028170) Port 1 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028174) Port 1 Pin Hardware Select Register                    */\r
+} PORT1_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT2                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 2 (PORT2)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028200) PORT2 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028200) Port 2 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028204) Port 2 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028210) Port 2 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028214) Port 2 Input/Output Control Register 4                 */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028218) Port 2 Input/Output Control Register 8                 */\r
+  __I  uint32_t  RESERVED1[2];\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028224) Port 2 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028240) Port 2 Pad Driver Mode 0 Register                      */\r
+  __IO uint32_t  PDR1;                              /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Register                      */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028260) Port 2 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028270) Port 2 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028274) Port 2 Pin Hardware Select Register                    */\r
+} PORT2_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT3                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 3 (PORT3)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028300) PORT3 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028300) Port 3 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028304) Port 3 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028310) Port 3 Input/Output Control Register 0                 */\r
+  __I  uint32_t  RESERVED1[4];\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028324) Port 3 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028340) Port 3 Pad Driver Mode 0 Register                      */\r
+  __I  uint32_t  RESERVED3[7];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028360) Port 3 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028370) Port 3 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028374) Port 3 Pin Hardware Select Register                    */\r
+} PORT3_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     PORT14                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 14 (PORT14)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028E00) PORT14 Structure                                       */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028E00) Port 14 Output Register                                */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028E04) Port 14 Output Modification Register                   */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028E10) Port 14 Input/Output Control Register 0                */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028E14) Port 14 Input/Output Control Register 4                */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028E18) Port 14 Input/Output Control Register 8                */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x48028E1C) Port 14 Input/Output Control Register 12               */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028E24) Port 14 Input Register                                 */\r
+  __I  uint32_t  RESERVED2[14];\r
+  __IO uint32_t  PDISC;                             /*!< (@ 0x48028E60) Port 14 Pin Function Decision Control Register         */\r
+  __I  uint32_t  RESERVED3[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028E70) Port 14 Pin Power Save Register                        */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028E74) Port 14 Pin Hardware Select Register                   */\r
+} PORT14_Type;\r
+\r
+\r
+/* --------------------  End of section using anonymous unions  ------------------- */\r
+#if defined(__CC_ARM)\r
+  #pragma pop\r
+#elif defined(__ICCARM__)\r
+  /* leave anonymous unions enabled */\r
+#elif defined(__GNUC__)\r
+  /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+  /* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+  #pragma warning restore\r
+#else\r
+  #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'PPB' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PPB_ACTLR  --------------------------------- */\r
+#define PPB_ACTLR_DISMCYCINT_Pos              0                                                       /*!< PPB ACTLR: DISMCYCINT Position          */\r
+#define PPB_ACTLR_DISMCYCINT_Msk              (0x01UL << PPB_ACTLR_DISMCYCINT_Pos)                    /*!< PPB ACTLR: DISMCYCINT Mask              */\r
+#define PPB_ACTLR_DISDEFWBUF_Pos              1                                                       /*!< PPB ACTLR: DISDEFWBUF Position          */\r
+#define PPB_ACTLR_DISDEFWBUF_Msk              (0x01UL << PPB_ACTLR_DISDEFWBUF_Pos)                    /*!< PPB ACTLR: DISDEFWBUF Mask              */\r
+#define PPB_ACTLR_DISFOLD_Pos                 2                                                       /*!< PPB ACTLR: DISFOLD Position             */\r
+#define PPB_ACTLR_DISFOLD_Msk                 (0x01UL << PPB_ACTLR_DISFOLD_Pos)                       /*!< PPB ACTLR: DISFOLD Mask                 */\r
+#define PPB_ACTLR_DISFPCA_Pos                 8                                                       /*!< PPB ACTLR: DISFPCA Position             */\r
+#define PPB_ACTLR_DISFPCA_Msk                 (0x01UL << PPB_ACTLR_DISFPCA_Pos)                       /*!< PPB ACTLR: DISFPCA Mask                 */\r
+#define PPB_ACTLR_DISOOFP_Pos                 9                                                       /*!< PPB ACTLR: DISOOFP Position             */\r
+#define PPB_ACTLR_DISOOFP_Msk                 (0x01UL << PPB_ACTLR_DISOOFP_Pos)                       /*!< PPB ACTLR: DISOOFP Mask                 */\r
+\r
+/* --------------------------------  PPB_SYST_CSR  -------------------------------- */\r
+#define PPB_SYST_CSR_ENABLE_Pos               0                                                       /*!< PPB SYST_CSR: ENABLE Position           */\r
+#define PPB_SYST_CSR_ENABLE_Msk               (0x01UL << PPB_SYST_CSR_ENABLE_Pos)                     /*!< PPB SYST_CSR: ENABLE Mask               */\r
+#define PPB_SYST_CSR_TICKINT_Pos              1                                                       /*!< PPB SYST_CSR: TICKINT Position          */\r
+#define PPB_SYST_CSR_TICKINT_Msk              (0x01UL << PPB_SYST_CSR_TICKINT_Pos)                    /*!< PPB SYST_CSR: TICKINT Mask              */\r
+#define PPB_SYST_CSR_CLKSOURCE_Pos            2                                                       /*!< PPB SYST_CSR: CLKSOURCE Position        */\r
+#define PPB_SYST_CSR_CLKSOURCE_Msk            (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos)                  /*!< PPB SYST_CSR: CLKSOURCE Mask            */\r
+#define PPB_SYST_CSR_COUNTFLAG_Pos            16                                                      /*!< PPB SYST_CSR: COUNTFLAG Position        */\r
+#define PPB_SYST_CSR_COUNTFLAG_Msk            (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos)                  /*!< PPB SYST_CSR: COUNTFLAG Mask            */\r
+\r
+/* --------------------------------  PPB_SYST_RVR  -------------------------------- */\r
+#define PPB_SYST_RVR_RELOAD_Pos               0                                                       /*!< PPB SYST_RVR: RELOAD Position           */\r
+#define PPB_SYST_RVR_RELOAD_Msk               (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos)               /*!< PPB SYST_RVR: RELOAD Mask               */\r
+\r
+/* --------------------------------  PPB_SYST_CVR  -------------------------------- */\r
+#define PPB_SYST_CVR_CURRENT_Pos              0                                                       /*!< PPB SYST_CVR: CURRENT Position          */\r
+#define PPB_SYST_CVR_CURRENT_Msk              (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos)              /*!< PPB SYST_CVR: CURRENT Mask              */\r
+\r
+/* -------------------------------  PPB_SYST_CALIB  ------------------------------- */\r
+#define PPB_SYST_CALIB_TENMS_Pos              0                                                       /*!< PPB SYST_CALIB: TENMS Position          */\r
+#define PPB_SYST_CALIB_TENMS_Msk              (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos)              /*!< PPB SYST_CALIB: TENMS Mask              */\r
+#define PPB_SYST_CALIB_SKEW_Pos               30                                                      /*!< PPB SYST_CALIB: SKEW Position           */\r
+#define PPB_SYST_CALIB_SKEW_Msk               (0x01UL << PPB_SYST_CALIB_SKEW_Pos)                     /*!< PPB SYST_CALIB: SKEW Mask               */\r
+#define PPB_SYST_CALIB_NOREF_Pos              31                                                      /*!< PPB SYST_CALIB: NOREF Position          */\r
+#define PPB_SYST_CALIB_NOREF_Msk              (0x01UL << PPB_SYST_CALIB_NOREF_Pos)                    /*!< PPB SYST_CALIB: NOREF Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER0  ------------------------------- */\r
+#define PPB_NVIC_ISER0_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER0: SETENA Position         */\r
+#define PPB_NVIC_ISER0_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER0_SETENA_Pos)             /*!< PPB NVIC_ISER0: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER1  ------------------------------- */\r
+#define PPB_NVIC_ISER1_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER1: SETENA Position         */\r
+#define PPB_NVIC_ISER1_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER1_SETENA_Pos)             /*!< PPB NVIC_ISER1: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER2  ------------------------------- */\r
+#define PPB_NVIC_ISER2_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER2: SETENA Position         */\r
+#define PPB_NVIC_ISER2_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER2_SETENA_Pos)             /*!< PPB NVIC_ISER2: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER3  ------------------------------- */\r
+#define PPB_NVIC_ISER3_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER3: SETENA Position         */\r
+#define PPB_NVIC_ISER3_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER3_SETENA_Pos)             /*!< PPB NVIC_ISER3: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER0  ------------------------------- */\r
+#define PPB_NVIC_ICER0_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER0: CLRENA Position         */\r
+#define PPB_NVIC_ICER0_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER0_CLRENA_Pos)             /*!< PPB NVIC_ICER0: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER1  ------------------------------- */\r
+#define PPB_NVIC_ICER1_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER1: CLRENA Position         */\r
+#define PPB_NVIC_ICER1_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER1_CLRENA_Pos)             /*!< PPB NVIC_ICER1: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER2  ------------------------------- */\r
+#define PPB_NVIC_ICER2_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER2: CLRENA Position         */\r
+#define PPB_NVIC_ICER2_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER2_CLRENA_Pos)             /*!< PPB NVIC_ICER2: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER3  ------------------------------- */\r
+#define PPB_NVIC_ICER3_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER3: CLRENA Position         */\r
+#define PPB_NVIC_ICER3_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER3_CLRENA_Pos)             /*!< PPB NVIC_ICER3: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR0  ------------------------------- */\r
+#define PPB_NVIC_ISPR0_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR0: SETPEND Position        */\r
+#define PPB_NVIC_ISPR0_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR0_SETPEND_Pos)            /*!< PPB NVIC_ISPR0: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR1  ------------------------------- */\r
+#define PPB_NVIC_ISPR1_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR1: SETPEND Position        */\r
+#define PPB_NVIC_ISPR1_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR1_SETPEND_Pos)            /*!< PPB NVIC_ISPR1: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR2  ------------------------------- */\r
+#define PPB_NVIC_ISPR2_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR2: SETPEND Position        */\r
+#define PPB_NVIC_ISPR2_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR2_SETPEND_Pos)            /*!< PPB NVIC_ISPR2: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR3  ------------------------------- */\r
+#define PPB_NVIC_ISPR3_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR3: SETPEND Position        */\r
+#define PPB_NVIC_ISPR3_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR3_SETPEND_Pos)            /*!< PPB NVIC_ISPR3: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR0  ------------------------------- */\r
+#define PPB_NVIC_ICPR0_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR0: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR0_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR0_CLRPEND_Pos)            /*!< PPB NVIC_ICPR0: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR1  ------------------------------- */\r
+#define PPB_NVIC_ICPR1_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR1: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR1_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR1_CLRPEND_Pos)            /*!< PPB NVIC_ICPR1: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR2  ------------------------------- */\r
+#define PPB_NVIC_ICPR2_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR2: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR2_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR2_CLRPEND_Pos)            /*!< PPB NVIC_ICPR2: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR3  ------------------------------- */\r
+#define PPB_NVIC_ICPR3_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR3: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR3_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR3_CLRPEND_Pos)            /*!< PPB NVIC_ICPR3: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR0  ------------------------------- */\r
+#define PPB_NVIC_IABR0_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR0: ACTIVE Position         */\r
+#define PPB_NVIC_IABR0_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR0_ACTIVE_Pos)             /*!< PPB NVIC_IABR0: ACTIVE Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR1  ------------------------------- */\r
+#define PPB_NVIC_IABR1_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR1: ACTIVE Position         */\r
+#define PPB_NVIC_IABR1_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR1_ACTIVE_Pos)             /*!< PPB NVIC_IABR1: ACTIVE Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR2  ------------------------------- */\r
+#define PPB_NVIC_IABR2_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR2: ACTIVE Position         */\r
+#define PPB_NVIC_IABR2_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR2_ACTIVE_Pos)             /*!< PPB NVIC_IABR2: ACTIVE Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR3  ------------------------------- */\r
+#define PPB_NVIC_IABR3_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR3: ACTIVE Position         */\r
+#define PPB_NVIC_IABR3_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR3_ACTIVE_Pos)             /*!< PPB NVIC_IABR3: ACTIVE Mask             */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR0  ------------------------------- */\r
+#define PPB_NVIC_IPR0_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR0: PRI_0 Position           */\r
+#define PPB_NVIC_IPR0_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos)               /*!< PPB NVIC_IPR0: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR0_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR0: PRI_1 Position           */\r
+#define PPB_NVIC_IPR0_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos)               /*!< PPB NVIC_IPR0: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR0_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR0: PRI_2 Position           */\r
+#define PPB_NVIC_IPR0_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos)               /*!< PPB NVIC_IPR0: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR0_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR0: PRI_3 Position           */\r
+#define PPB_NVIC_IPR0_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos)               /*!< PPB NVIC_IPR0: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR1  ------------------------------- */\r
+#define PPB_NVIC_IPR1_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR1: PRI_0 Position           */\r
+#define PPB_NVIC_IPR1_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos)               /*!< PPB NVIC_IPR1: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR1_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR1: PRI_1 Position           */\r
+#define PPB_NVIC_IPR1_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos)               /*!< PPB NVIC_IPR1: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR1_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR1: PRI_2 Position           */\r
+#define PPB_NVIC_IPR1_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos)               /*!< PPB NVIC_IPR1: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR1_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR1: PRI_3 Position           */\r
+#define PPB_NVIC_IPR1_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos)               /*!< PPB NVIC_IPR1: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR2  ------------------------------- */\r
+#define PPB_NVIC_IPR2_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR2: PRI_0 Position           */\r
+#define PPB_NVIC_IPR2_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos)               /*!< PPB NVIC_IPR2: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR2_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR2: PRI_1 Position           */\r
+#define PPB_NVIC_IPR2_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos)               /*!< PPB NVIC_IPR2: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR2_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR2: PRI_2 Position           */\r
+#define PPB_NVIC_IPR2_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos)               /*!< PPB NVIC_IPR2: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR2_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR2: PRI_3 Position           */\r
+#define PPB_NVIC_IPR2_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos)               /*!< PPB NVIC_IPR2: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR3  ------------------------------- */\r
+#define PPB_NVIC_IPR3_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR3: PRI_0 Position           */\r
+#define PPB_NVIC_IPR3_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos)               /*!< PPB NVIC_IPR3: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR3_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR3: PRI_1 Position           */\r
+#define PPB_NVIC_IPR3_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos)               /*!< PPB NVIC_IPR3: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR3_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR3: PRI_2 Position           */\r
+#define PPB_NVIC_IPR3_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos)               /*!< PPB NVIC_IPR3: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR3_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR3: PRI_3 Position           */\r
+#define PPB_NVIC_IPR3_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos)               /*!< PPB NVIC_IPR3: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR4  ------------------------------- */\r
+#define PPB_NVIC_IPR4_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR4: PRI_0 Position           */\r
+#define PPB_NVIC_IPR4_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos)               /*!< PPB NVIC_IPR4: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR4_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR4: PRI_1 Position           */\r
+#define PPB_NVIC_IPR4_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos)               /*!< PPB NVIC_IPR4: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR4_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR4: PRI_2 Position           */\r
+#define PPB_NVIC_IPR4_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos)               /*!< PPB NVIC_IPR4: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR4_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR4: PRI_3 Position           */\r
+#define PPB_NVIC_IPR4_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos)               /*!< PPB NVIC_IPR4: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR5  ------------------------------- */\r
+#define PPB_NVIC_IPR5_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR5: PRI_0 Position           */\r
+#define PPB_NVIC_IPR5_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos)               /*!< PPB NVIC_IPR5: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR5_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR5: PRI_1 Position           */\r
+#define PPB_NVIC_IPR5_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos)               /*!< PPB NVIC_IPR5: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR5_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR5: PRI_2 Position           */\r
+#define PPB_NVIC_IPR5_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos)               /*!< PPB NVIC_IPR5: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR5_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR5: PRI_3 Position           */\r
+#define PPB_NVIC_IPR5_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos)               /*!< PPB NVIC_IPR5: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR6  ------------------------------- */\r
+#define PPB_NVIC_IPR6_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR6: PRI_0 Position           */\r
+#define PPB_NVIC_IPR6_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos)               /*!< PPB NVIC_IPR6: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR6_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR6: PRI_1 Position           */\r
+#define PPB_NVIC_IPR6_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos)               /*!< PPB NVIC_IPR6: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR6_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR6: PRI_2 Position           */\r
+#define PPB_NVIC_IPR6_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos)               /*!< PPB NVIC_IPR6: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR6_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR6: PRI_3 Position           */\r
+#define PPB_NVIC_IPR6_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos)               /*!< PPB NVIC_IPR6: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR7  ------------------------------- */\r
+#define PPB_NVIC_IPR7_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR7: PRI_0 Position           */\r
+#define PPB_NVIC_IPR7_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos)               /*!< PPB NVIC_IPR7: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR7_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR7: PRI_1 Position           */\r
+#define PPB_NVIC_IPR7_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos)               /*!< PPB NVIC_IPR7: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR7_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR7: PRI_2 Position           */\r
+#define PPB_NVIC_IPR7_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos)               /*!< PPB NVIC_IPR7: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR7_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR7: PRI_3 Position           */\r
+#define PPB_NVIC_IPR7_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos)               /*!< PPB NVIC_IPR7: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR8  ------------------------------- */\r
+#define PPB_NVIC_IPR8_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR8: PRI_0 Position           */\r
+#define PPB_NVIC_IPR8_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_0_Pos)               /*!< PPB NVIC_IPR8: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR8_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR8: PRI_1 Position           */\r
+#define PPB_NVIC_IPR8_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_1_Pos)               /*!< PPB NVIC_IPR8: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR8_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR8: PRI_2 Position           */\r
+#define PPB_NVIC_IPR8_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_2_Pos)               /*!< PPB NVIC_IPR8: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR8_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR8: PRI_3 Position           */\r
+#define PPB_NVIC_IPR8_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_3_Pos)               /*!< PPB NVIC_IPR8: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR9  ------------------------------- */\r
+#define PPB_NVIC_IPR9_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR9: PRI_0 Position           */\r
+#define PPB_NVIC_IPR9_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_0_Pos)               /*!< PPB NVIC_IPR9: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR9_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR9: PRI_1 Position           */\r
+#define PPB_NVIC_IPR9_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_1_Pos)               /*!< PPB NVIC_IPR9: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR9_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR9: PRI_2 Position           */\r
+#define PPB_NVIC_IPR9_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_2_Pos)               /*!< PPB NVIC_IPR9: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR9_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR9: PRI_3 Position           */\r
+#define PPB_NVIC_IPR9_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_3_Pos)               /*!< PPB NVIC_IPR9: PRI_3 Mask               */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR10  ------------------------------- */\r
+#define PPB_NVIC_IPR10_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR10: PRI_0 Position          */\r
+#define PPB_NVIC_IPR10_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_0_Pos)              /*!< PPB NVIC_IPR10: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR10_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR10: PRI_1 Position          */\r
+#define PPB_NVIC_IPR10_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_1_Pos)              /*!< PPB NVIC_IPR10: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR10_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR10: PRI_2 Position          */\r
+#define PPB_NVIC_IPR10_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_2_Pos)              /*!< PPB NVIC_IPR10: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR10_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR10: PRI_3 Position          */\r
+#define PPB_NVIC_IPR10_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_3_Pos)              /*!< PPB NVIC_IPR10: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR11  ------------------------------- */\r
+#define PPB_NVIC_IPR11_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR11: PRI_0 Position          */\r
+#define PPB_NVIC_IPR11_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_0_Pos)              /*!< PPB NVIC_IPR11: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR11_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR11: PRI_1 Position          */\r
+#define PPB_NVIC_IPR11_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_1_Pos)              /*!< PPB NVIC_IPR11: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR11_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR11: PRI_2 Position          */\r
+#define PPB_NVIC_IPR11_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_2_Pos)              /*!< PPB NVIC_IPR11: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR11_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR11: PRI_3 Position          */\r
+#define PPB_NVIC_IPR11_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_3_Pos)              /*!< PPB NVIC_IPR11: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR12  ------------------------------- */\r
+#define PPB_NVIC_IPR12_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR12: PRI_0 Position          */\r
+#define PPB_NVIC_IPR12_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_0_Pos)              /*!< PPB NVIC_IPR12: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR12_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR12: PRI_1 Position          */\r
+#define PPB_NVIC_IPR12_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_1_Pos)              /*!< PPB NVIC_IPR12: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR12_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR12: PRI_2 Position          */\r
+#define PPB_NVIC_IPR12_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_2_Pos)              /*!< PPB NVIC_IPR12: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR12_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR12: PRI_3 Position          */\r
+#define PPB_NVIC_IPR12_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_3_Pos)              /*!< PPB NVIC_IPR12: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR13  ------------------------------- */\r
+#define PPB_NVIC_IPR13_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR13: PRI_0 Position          */\r
+#define PPB_NVIC_IPR13_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_0_Pos)              /*!< PPB NVIC_IPR13: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR13_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR13: PRI_1 Position          */\r
+#define PPB_NVIC_IPR13_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_1_Pos)              /*!< PPB NVIC_IPR13: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR13_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR13: PRI_2 Position          */\r
+#define PPB_NVIC_IPR13_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_2_Pos)              /*!< PPB NVIC_IPR13: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR13_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR13: PRI_3 Position          */\r
+#define PPB_NVIC_IPR13_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_3_Pos)              /*!< PPB NVIC_IPR13: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR14  ------------------------------- */\r
+#define PPB_NVIC_IPR14_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR14: PRI_0 Position          */\r
+#define PPB_NVIC_IPR14_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_0_Pos)              /*!< PPB NVIC_IPR14: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR14_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR14: PRI_1 Position          */\r
+#define PPB_NVIC_IPR14_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_1_Pos)              /*!< PPB NVIC_IPR14: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR14_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR14: PRI_2 Position          */\r
+#define PPB_NVIC_IPR14_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_2_Pos)              /*!< PPB NVIC_IPR14: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR14_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR14: PRI_3 Position          */\r
+#define PPB_NVIC_IPR14_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_3_Pos)              /*!< PPB NVIC_IPR14: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR15  ------------------------------- */\r
+#define PPB_NVIC_IPR15_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR15: PRI_0 Position          */\r
+#define PPB_NVIC_IPR15_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_0_Pos)              /*!< PPB NVIC_IPR15: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR15_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR15: PRI_1 Position          */\r
+#define PPB_NVIC_IPR15_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_1_Pos)              /*!< PPB NVIC_IPR15: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR15_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR15: PRI_2 Position          */\r
+#define PPB_NVIC_IPR15_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_2_Pos)              /*!< PPB NVIC_IPR15: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR15_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR15: PRI_3 Position          */\r
+#define PPB_NVIC_IPR15_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_3_Pos)              /*!< PPB NVIC_IPR15: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR16  ------------------------------- */\r
+#define PPB_NVIC_IPR16_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR16: PRI_0 Position          */\r
+#define PPB_NVIC_IPR16_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_0_Pos)              /*!< PPB NVIC_IPR16: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR16_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR16: PRI_1 Position          */\r
+#define PPB_NVIC_IPR16_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_1_Pos)              /*!< PPB NVIC_IPR16: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR16_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR16: PRI_2 Position          */\r
+#define PPB_NVIC_IPR16_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_2_Pos)              /*!< PPB NVIC_IPR16: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR16_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR16: PRI_3 Position          */\r
+#define PPB_NVIC_IPR16_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_3_Pos)              /*!< PPB NVIC_IPR16: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR17  ------------------------------- */\r
+#define PPB_NVIC_IPR17_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR17: PRI_0 Position          */\r
+#define PPB_NVIC_IPR17_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_0_Pos)              /*!< PPB NVIC_IPR17: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR17_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR17: PRI_1 Position          */\r
+#define PPB_NVIC_IPR17_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_1_Pos)              /*!< PPB NVIC_IPR17: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR17_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR17: PRI_2 Position          */\r
+#define PPB_NVIC_IPR17_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_2_Pos)              /*!< PPB NVIC_IPR17: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR17_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR17: PRI_3 Position          */\r
+#define PPB_NVIC_IPR17_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_3_Pos)              /*!< PPB NVIC_IPR17: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR18  ------------------------------- */\r
+#define PPB_NVIC_IPR18_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR18: PRI_0 Position          */\r
+#define PPB_NVIC_IPR18_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_0_Pos)              /*!< PPB NVIC_IPR18: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR18_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR18: PRI_1 Position          */\r
+#define PPB_NVIC_IPR18_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_1_Pos)              /*!< PPB NVIC_IPR18: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR18_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR18: PRI_2 Position          */\r
+#define PPB_NVIC_IPR18_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_2_Pos)              /*!< PPB NVIC_IPR18: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR18_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR18: PRI_3 Position          */\r
+#define PPB_NVIC_IPR18_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_3_Pos)              /*!< PPB NVIC_IPR18: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR19  ------------------------------- */\r
+#define PPB_NVIC_IPR19_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR19: PRI_0 Position          */\r
+#define PPB_NVIC_IPR19_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_0_Pos)              /*!< PPB NVIC_IPR19: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR19_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR19: PRI_1 Position          */\r
+#define PPB_NVIC_IPR19_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_1_Pos)              /*!< PPB NVIC_IPR19: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR19_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR19: PRI_2 Position          */\r
+#define PPB_NVIC_IPR19_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_2_Pos)              /*!< PPB NVIC_IPR19: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR19_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR19: PRI_3 Position          */\r
+#define PPB_NVIC_IPR19_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_3_Pos)              /*!< PPB NVIC_IPR19: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR20  ------------------------------- */\r
+#define PPB_NVIC_IPR20_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR20: PRI_0 Position          */\r
+#define PPB_NVIC_IPR20_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_0_Pos)              /*!< PPB NVIC_IPR20: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR20_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR20: PRI_1 Position          */\r
+#define PPB_NVIC_IPR20_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_1_Pos)              /*!< PPB NVIC_IPR20: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR20_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR20: PRI_2 Position          */\r
+#define PPB_NVIC_IPR20_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_2_Pos)              /*!< PPB NVIC_IPR20: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR20_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR20: PRI_3 Position          */\r
+#define PPB_NVIC_IPR20_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_3_Pos)              /*!< PPB NVIC_IPR20: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR21  ------------------------------- */\r
+#define PPB_NVIC_IPR21_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR21: PRI_0 Position          */\r
+#define PPB_NVIC_IPR21_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_0_Pos)              /*!< PPB NVIC_IPR21: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR21_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR21: PRI_1 Position          */\r
+#define PPB_NVIC_IPR21_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_1_Pos)              /*!< PPB NVIC_IPR21: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR21_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR21: PRI_2 Position          */\r
+#define PPB_NVIC_IPR21_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_2_Pos)              /*!< PPB NVIC_IPR21: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR21_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR21: PRI_3 Position          */\r
+#define PPB_NVIC_IPR21_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_3_Pos)              /*!< PPB NVIC_IPR21: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR22  ------------------------------- */\r
+#define PPB_NVIC_IPR22_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR22: PRI_0 Position          */\r
+#define PPB_NVIC_IPR22_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_0_Pos)              /*!< PPB NVIC_IPR22: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR22_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR22: PRI_1 Position          */\r
+#define PPB_NVIC_IPR22_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_1_Pos)              /*!< PPB NVIC_IPR22: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR22_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR22: PRI_2 Position          */\r
+#define PPB_NVIC_IPR22_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_2_Pos)              /*!< PPB NVIC_IPR22: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR22_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR22: PRI_3 Position          */\r
+#define PPB_NVIC_IPR22_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_3_Pos)              /*!< PPB NVIC_IPR22: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR23  ------------------------------- */\r
+#define PPB_NVIC_IPR23_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR23: PRI_0 Position          */\r
+#define PPB_NVIC_IPR23_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_0_Pos)              /*!< PPB NVIC_IPR23: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR23_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR23: PRI_1 Position          */\r
+#define PPB_NVIC_IPR23_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_1_Pos)              /*!< PPB NVIC_IPR23: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR23_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR23: PRI_2 Position          */\r
+#define PPB_NVIC_IPR23_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_2_Pos)              /*!< PPB NVIC_IPR23: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR23_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR23: PRI_3 Position          */\r
+#define PPB_NVIC_IPR23_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_3_Pos)              /*!< PPB NVIC_IPR23: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR24  ------------------------------- */\r
+#define PPB_NVIC_IPR24_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR24: PRI_0 Position          */\r
+#define PPB_NVIC_IPR24_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_0_Pos)              /*!< PPB NVIC_IPR24: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR24_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR24: PRI_1 Position          */\r
+#define PPB_NVIC_IPR24_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_1_Pos)              /*!< PPB NVIC_IPR24: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR24_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR24: PRI_2 Position          */\r
+#define PPB_NVIC_IPR24_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_2_Pos)              /*!< PPB NVIC_IPR24: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR24_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR24: PRI_3 Position          */\r
+#define PPB_NVIC_IPR24_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_3_Pos)              /*!< PPB NVIC_IPR24: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR25  ------------------------------- */\r
+#define PPB_NVIC_IPR25_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR25: PRI_0 Position          */\r
+#define PPB_NVIC_IPR25_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_0_Pos)              /*!< PPB NVIC_IPR25: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR25_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR25: PRI_1 Position          */\r
+#define PPB_NVIC_IPR25_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_1_Pos)              /*!< PPB NVIC_IPR25: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR25_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR25: PRI_2 Position          */\r
+#define PPB_NVIC_IPR25_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_2_Pos)              /*!< PPB NVIC_IPR25: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR25_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR25: PRI_3 Position          */\r
+#define PPB_NVIC_IPR25_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_3_Pos)              /*!< PPB NVIC_IPR25: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR26  ------------------------------- */\r
+#define PPB_NVIC_IPR26_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR26: PRI_0 Position          */\r
+#define PPB_NVIC_IPR26_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_0_Pos)              /*!< PPB NVIC_IPR26: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR26_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR26: PRI_1 Position          */\r
+#define PPB_NVIC_IPR26_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_1_Pos)              /*!< PPB NVIC_IPR26: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR26_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR26: PRI_2 Position          */\r
+#define PPB_NVIC_IPR26_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_2_Pos)              /*!< PPB NVIC_IPR26: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR26_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR26: PRI_3 Position          */\r
+#define PPB_NVIC_IPR26_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_3_Pos)              /*!< PPB NVIC_IPR26: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR27  ------------------------------- */\r
+#define PPB_NVIC_IPR27_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR27: PRI_0 Position          */\r
+#define PPB_NVIC_IPR27_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_0_Pos)              /*!< PPB NVIC_IPR27: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR27_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR27: PRI_1 Position          */\r
+#define PPB_NVIC_IPR27_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_1_Pos)              /*!< PPB NVIC_IPR27: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR27_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR27: PRI_2 Position          */\r
+#define PPB_NVIC_IPR27_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_2_Pos)              /*!< PPB NVIC_IPR27: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR27_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR27: PRI_3 Position          */\r
+#define PPB_NVIC_IPR27_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_3_Pos)              /*!< PPB NVIC_IPR27: PRI_3 Mask              */\r
+\r
+/* ----------------------------------  PPB_CPUID  --------------------------------- */\r
+#define PPB_CPUID_Revision_Pos                0                                                       /*!< PPB CPUID: Revision Position            */\r
+#define PPB_CPUID_Revision_Msk                (0x0fUL << PPB_CPUID_Revision_Pos)                      /*!< PPB CPUID: Revision Mask                */\r
+#define PPB_CPUID_PartNo_Pos                  4                                                       /*!< PPB CPUID: PartNo Position              */\r
+#define PPB_CPUID_PartNo_Msk                  (0x00000fffUL << PPB_CPUID_PartNo_Pos)                  /*!< PPB CPUID: PartNo Mask                  */\r
+#define PPB_CPUID_Constant_Pos                16                                                      /*!< PPB CPUID: Constant Position            */\r
+#define PPB_CPUID_Constant_Msk                (0x0fUL << PPB_CPUID_Constant_Pos)                      /*!< PPB CPUID: Constant Mask                */\r
+#define PPB_CPUID_Variant_Pos                 20                                                      /*!< PPB CPUID: Variant Position             */\r
+#define PPB_CPUID_Variant_Msk                 (0x0fUL << PPB_CPUID_Variant_Pos)                       /*!< PPB CPUID: Variant Mask                 */\r
+#define PPB_CPUID_Implementer_Pos             24                                                      /*!< PPB CPUID: Implementer Position         */\r
+#define PPB_CPUID_Implementer_Msk             (0x000000ffUL << PPB_CPUID_Implementer_Pos)             /*!< PPB CPUID: Implementer Mask             */\r
+\r
+/* ----------------------------------  PPB_ICSR  ---------------------------------- */\r
+#define PPB_ICSR_VECTACTIVE_Pos               0                                                       /*!< PPB ICSR: VECTACTIVE Position           */\r
+#define PPB_ICSR_VECTACTIVE_Msk               (0x000001ffUL << PPB_ICSR_VECTACTIVE_Pos)               /*!< PPB ICSR: VECTACTIVE Mask               */\r
+#define PPB_ICSR_RETTOBASE_Pos                11                                                      /*!< PPB ICSR: RETTOBASE Position            */\r
+#define PPB_ICSR_RETTOBASE_Msk                (0x01UL << PPB_ICSR_RETTOBASE_Pos)                      /*!< PPB ICSR: RETTOBASE Mask                */\r
+#define PPB_ICSR_VECTPENDING_Pos              12                                                      /*!< PPB ICSR: VECTPENDING Position          */\r
+#define PPB_ICSR_VECTPENDING_Msk              (0x3fUL << PPB_ICSR_VECTPENDING_Pos)                    /*!< PPB ICSR: VECTPENDING Mask              */\r
+#define PPB_ICSR_ISRPENDING_Pos               22                                                      /*!< PPB ICSR: ISRPENDING Position           */\r
+#define PPB_ICSR_ISRPENDING_Msk               (0x01UL << PPB_ICSR_ISRPENDING_Pos)                     /*!< PPB ICSR: ISRPENDING Mask               */\r
+#define PPB_ICSR_Res_Pos                      23                                                      /*!< PPB ICSR: Res Position                  */\r
+#define PPB_ICSR_Res_Msk                      (0x01UL << PPB_ICSR_Res_Pos)                            /*!< PPB ICSR: Res Mask                      */\r
+#define PPB_ICSR_PENDSTCLR_Pos                25                                                      /*!< PPB ICSR: PENDSTCLR Position            */\r
+#define PPB_ICSR_PENDSTCLR_Msk                (0x01UL << PPB_ICSR_PENDSTCLR_Pos)                      /*!< PPB ICSR: PENDSTCLR Mask                */\r
+#define PPB_ICSR_PENDSTSET_Pos                26                                                      /*!< PPB ICSR: PENDSTSET Position            */\r
+#define PPB_ICSR_PENDSTSET_Msk                (0x01UL << PPB_ICSR_PENDSTSET_Pos)                      /*!< PPB ICSR: PENDSTSET Mask                */\r
+#define PPB_ICSR_PENDSVCLR_Pos                27                                                      /*!< PPB ICSR: PENDSVCLR Position            */\r
+#define PPB_ICSR_PENDSVCLR_Msk                (0x01UL << PPB_ICSR_PENDSVCLR_Pos)                      /*!< PPB ICSR: PENDSVCLR Mask                */\r
+#define PPB_ICSR_PENDSVSET_Pos                28                                                      /*!< PPB ICSR: PENDSVSET Position            */\r
+#define PPB_ICSR_PENDSVSET_Msk                (0x01UL << PPB_ICSR_PENDSVSET_Pos)                      /*!< PPB ICSR: PENDSVSET Mask                */\r
+#define PPB_ICSR_NMIPENDSET_Pos               31                                                      /*!< PPB ICSR: NMIPENDSET Position           */\r
+#define PPB_ICSR_NMIPENDSET_Msk               (0x01UL << PPB_ICSR_NMIPENDSET_Pos)                     /*!< PPB ICSR: NMIPENDSET Mask               */\r
+\r
+/* ----------------------------------  PPB_VTOR  ---------------------------------- */\r
+#define PPB_VTOR_TBLOFF_Pos                   10                                                      /*!< PPB VTOR: TBLOFF Position               */\r
+#define PPB_VTOR_TBLOFF_Msk                   (0x003fffffUL << PPB_VTOR_TBLOFF_Pos)                   /*!< PPB VTOR: TBLOFF Mask                   */\r
+\r
+/* ----------------------------------  PPB_AIRCR  --------------------------------- */\r
+#define PPB_AIRCR_VECTRESET_Pos               0                                                       /*!< PPB AIRCR: VECTRESET Position           */\r
+#define PPB_AIRCR_VECTRESET_Msk               (0x01UL << PPB_AIRCR_VECTRESET_Pos)                     /*!< PPB AIRCR: VECTRESET Mask               */\r
+#define PPB_AIRCR_VECTCLRACTIVE_Pos           1                                                       /*!< PPB AIRCR: VECTCLRACTIVE Position       */\r
+#define PPB_AIRCR_VECTCLRACTIVE_Msk           (0x01UL << PPB_AIRCR_VECTCLRACTIVE_Pos)                 /*!< PPB AIRCR: VECTCLRACTIVE Mask           */\r
+#define PPB_AIRCR_SYSRESETREQ_Pos             2                                                       /*!< PPB AIRCR: SYSRESETREQ Position         */\r
+#define PPB_AIRCR_SYSRESETREQ_Msk             (0x01UL << PPB_AIRCR_SYSRESETREQ_Pos)                   /*!< PPB AIRCR: SYSRESETREQ Mask             */\r
+#define PPB_AIRCR_PRIGROUP_Pos                8                                                       /*!< PPB AIRCR: PRIGROUP Position            */\r
+#define PPB_AIRCR_PRIGROUP_Msk                (0x07UL << PPB_AIRCR_PRIGROUP_Pos)                      /*!< PPB AIRCR: PRIGROUP Mask                */\r
+#define PPB_AIRCR_ENDIANNESS_Pos              15                                                      /*!< PPB AIRCR: ENDIANNESS Position          */\r
+#define PPB_AIRCR_ENDIANNESS_Msk              (0x01UL << PPB_AIRCR_ENDIANNESS_Pos)                    /*!< PPB AIRCR: ENDIANNESS Mask              */\r
+#define PPB_AIRCR_VECTKEY_Pos                 16                                                      /*!< PPB AIRCR: VECTKEY Position             */\r
+#define PPB_AIRCR_VECTKEY_Msk                 (0x0000ffffUL << PPB_AIRCR_VECTKEY_Pos)                 /*!< PPB AIRCR: VECTKEY Mask                 */\r
+\r
+/* -----------------------------------  PPB_SCR  ---------------------------------- */\r
+#define PPB_SCR_SLEEPONEXIT_Pos               1                                                       /*!< PPB SCR: SLEEPONEXIT Position           */\r
+#define PPB_SCR_SLEEPONEXIT_Msk               (0x01UL << PPB_SCR_SLEEPONEXIT_Pos)                     /*!< PPB SCR: SLEEPONEXIT Mask               */\r
+#define PPB_SCR_SLEEPDEEP_Pos                 2                                                       /*!< PPB SCR: SLEEPDEEP Position             */\r
+#define PPB_SCR_SLEEPDEEP_Msk                 (0x01UL << PPB_SCR_SLEEPDEEP_Pos)                       /*!< PPB SCR: SLEEPDEEP Mask                 */\r
+#define PPB_SCR_SEVONPEND_Pos                 4                                                       /*!< PPB SCR: SEVONPEND Position             */\r
+#define PPB_SCR_SEVONPEND_Msk                 (0x01UL << PPB_SCR_SEVONPEND_Pos)                       /*!< PPB SCR: SEVONPEND Mask                 */\r
+\r
+/* -----------------------------------  PPB_CCR  ---------------------------------- */\r
+#define PPB_CCR_NONBASETHRDENA_Pos            0                                                       /*!< PPB CCR: NONBASETHRDENA Position        */\r
+#define PPB_CCR_NONBASETHRDENA_Msk            (0x01UL << PPB_CCR_NONBASETHRDENA_Pos)                  /*!< PPB CCR: NONBASETHRDENA Mask            */\r
+#define PPB_CCR_USERSETMPEND_Pos              1                                                       /*!< PPB CCR: USERSETMPEND Position          */\r
+#define PPB_CCR_USERSETMPEND_Msk              (0x01UL << PPB_CCR_USERSETMPEND_Pos)                    /*!< PPB CCR: USERSETMPEND Mask              */\r
+#define PPB_CCR_UNALIGN_TRP_Pos               3                                                       /*!< PPB CCR: UNALIGN_TRP Position           */\r
+#define PPB_CCR_UNALIGN_TRP_Msk               (0x01UL << PPB_CCR_UNALIGN_TRP_Pos)                     /*!< PPB CCR: UNALIGN_TRP Mask               */\r
+#define PPB_CCR_DIV_0_TRP_Pos                 4                                                       /*!< PPB CCR: DIV_0_TRP Position             */\r
+#define PPB_CCR_DIV_0_TRP_Msk                 (0x01UL << PPB_CCR_DIV_0_TRP_Pos)                       /*!< PPB CCR: DIV_0_TRP Mask                 */\r
+#define PPB_CCR_BFHFNMIGN_Pos                 8                                                       /*!< PPB CCR: BFHFNMIGN Position             */\r
+#define PPB_CCR_BFHFNMIGN_Msk                 (0x01UL << PPB_CCR_BFHFNMIGN_Pos)                       /*!< PPB CCR: BFHFNMIGN Mask                 */\r
+#define PPB_CCR_STKALIGN_Pos                  9                                                       /*!< PPB CCR: STKALIGN Position              */\r
+#define PPB_CCR_STKALIGN_Msk                  (0x01UL << PPB_CCR_STKALIGN_Pos)                        /*!< PPB CCR: STKALIGN Mask                  */\r
+\r
+/* ----------------------------------  PPB_SHPR1  --------------------------------- */\r
+#define PPB_SHPR1_PRI_4_Pos                   0                                                       /*!< PPB SHPR1: PRI_4 Position               */\r
+#define PPB_SHPR1_PRI_4_Msk                   (0x000000ffUL << PPB_SHPR1_PRI_4_Pos)                   /*!< PPB SHPR1: PRI_4 Mask                   */\r
+#define PPB_SHPR1_PRI_5_Pos                   8                                                       /*!< PPB SHPR1: PRI_5 Position               */\r
+#define PPB_SHPR1_PRI_5_Msk                   (0x000000ffUL << PPB_SHPR1_PRI_5_Pos)                   /*!< PPB SHPR1: PRI_5 Mask                   */\r
+#define PPB_SHPR1_PRI_6_Pos                   16                                                      /*!< PPB SHPR1: PRI_6 Position               */\r
+#define PPB_SHPR1_PRI_6_Msk                   (0x000000ffUL << PPB_SHPR1_PRI_6_Pos)                   /*!< PPB SHPR1: PRI_6 Mask                   */\r
+\r
+/* ----------------------------------  PPB_SHPR2  --------------------------------- */\r
+#define PPB_SHPR2_PRI_11_Pos                  24                                                      /*!< PPB SHPR2: PRI_11 Position              */\r
+#define PPB_SHPR2_PRI_11_Msk                  (0x000000ffUL << PPB_SHPR2_PRI_11_Pos)                  /*!< PPB SHPR2: PRI_11 Mask                  */\r
+\r
+/* ----------------------------------  PPB_SHPR3  --------------------------------- */\r
+#define PPB_SHPR3_PRI_14_Pos                  16                                                      /*!< PPB SHPR3: PRI_14 Position              */\r
+#define PPB_SHPR3_PRI_14_Msk                  (0x000000ffUL << PPB_SHPR3_PRI_14_Pos)                  /*!< PPB SHPR3: PRI_14 Mask                  */\r
+#define PPB_SHPR3_PRI_15_Pos                  24                                                      /*!< PPB SHPR3: PRI_15 Position              */\r
+#define PPB_SHPR3_PRI_15_Msk                  (0x000000ffUL << PPB_SHPR3_PRI_15_Pos)                  /*!< PPB SHPR3: PRI_15 Mask                  */\r
+\r
+/* ----------------------------------  PPB_SHCSR  --------------------------------- */\r
+#define PPB_SHCSR_MEMFAULTACT_Pos             0                                                       /*!< PPB SHCSR: MEMFAULTACT Position         */\r
+#define PPB_SHCSR_MEMFAULTACT_Msk             (0x01UL << PPB_SHCSR_MEMFAULTACT_Pos)                   /*!< PPB SHCSR: MEMFAULTACT Mask             */\r
+#define PPB_SHCSR_BUSFAULTACT_Pos             1                                                       /*!< PPB SHCSR: BUSFAULTACT Position         */\r
+#define PPB_SHCSR_BUSFAULTACT_Msk             (0x01UL << PPB_SHCSR_BUSFAULTACT_Pos)                   /*!< PPB SHCSR: BUSFAULTACT Mask             */\r
+#define PPB_SHCSR_USGFAULTACT_Pos             3                                                       /*!< PPB SHCSR: USGFAULTACT Position         */\r
+#define PPB_SHCSR_USGFAULTACT_Msk             (0x01UL << PPB_SHCSR_USGFAULTACT_Pos)                   /*!< PPB SHCSR: USGFAULTACT Mask             */\r
+#define PPB_SHCSR_SVCALLACT_Pos               7                                                       /*!< PPB SHCSR: SVCALLACT Position           */\r
+#define PPB_SHCSR_SVCALLACT_Msk               (0x01UL << PPB_SHCSR_SVCALLACT_Pos)                     /*!< PPB SHCSR: SVCALLACT Mask               */\r
+#define PPB_SHCSR_MONITORACT_Pos              8                                                       /*!< PPB SHCSR: MONITORACT Position          */\r
+#define PPB_SHCSR_MONITORACT_Msk              (0x01UL << PPB_SHCSR_MONITORACT_Pos)                    /*!< PPB SHCSR: MONITORACT Mask              */\r
+#define PPB_SHCSR_PENDSVACT_Pos               10                                                      /*!< PPB SHCSR: PENDSVACT Position           */\r
+#define PPB_SHCSR_PENDSVACT_Msk               (0x01UL << PPB_SHCSR_PENDSVACT_Pos)                     /*!< PPB SHCSR: PENDSVACT Mask               */\r
+#define PPB_SHCSR_SYSTICKACT_Pos              11                                                      /*!< PPB SHCSR: SYSTICKACT Position          */\r
+#define PPB_SHCSR_SYSTICKACT_Msk              (0x01UL << PPB_SHCSR_SYSTICKACT_Pos)                    /*!< PPB SHCSR: SYSTICKACT Mask              */\r
+#define PPB_SHCSR_USGFAULTPENDED_Pos          12                                                      /*!< PPB SHCSR: USGFAULTPENDED Position      */\r
+#define PPB_SHCSR_USGFAULTPENDED_Msk          (0x01UL << PPB_SHCSR_USGFAULTPENDED_Pos)                /*!< PPB SHCSR: USGFAULTPENDED Mask          */\r
+#define PPB_SHCSR_MEMFAULTPENDED_Pos          13                                                      /*!< PPB SHCSR: MEMFAULTPENDED Position      */\r
+#define PPB_SHCSR_MEMFAULTPENDED_Msk          (0x01UL << PPB_SHCSR_MEMFAULTPENDED_Pos)                /*!< PPB SHCSR: MEMFAULTPENDED Mask          */\r
+#define PPB_SHCSR_BUSFAULTPENDED_Pos          14                                                      /*!< PPB SHCSR: BUSFAULTPENDED Position      */\r
+#define PPB_SHCSR_BUSFAULTPENDED_Msk          (0x01UL << PPB_SHCSR_BUSFAULTPENDED_Pos)                /*!< PPB SHCSR: BUSFAULTPENDED Mask          */\r
+#define PPB_SHCSR_SVCALLPENDED_Pos            15                                                      /*!< PPB SHCSR: SVCALLPENDED Position        */\r
+#define PPB_SHCSR_SVCALLPENDED_Msk            (0x01UL << PPB_SHCSR_SVCALLPENDED_Pos)                  /*!< PPB SHCSR: SVCALLPENDED Mask            */\r
+#define PPB_SHCSR_MEMFAULTENA_Pos             16                                                      /*!< PPB SHCSR: MEMFAULTENA Position         */\r
+#define PPB_SHCSR_MEMFAULTENA_Msk             (0x01UL << PPB_SHCSR_MEMFAULTENA_Pos)                   /*!< PPB SHCSR: MEMFAULTENA Mask             */\r
+#define PPB_SHCSR_BUSFAULTENA_Pos             17                                                      /*!< PPB SHCSR: BUSFAULTENA Position         */\r
+#define PPB_SHCSR_BUSFAULTENA_Msk             (0x01UL << PPB_SHCSR_BUSFAULTENA_Pos)                   /*!< PPB SHCSR: BUSFAULTENA Mask             */\r
+#define PPB_SHCSR_USGFAULTENA_Pos             18                                                      /*!< PPB SHCSR: USGFAULTENA Position         */\r
+#define PPB_SHCSR_USGFAULTENA_Msk             (0x01UL << PPB_SHCSR_USGFAULTENA_Pos)                   /*!< PPB SHCSR: USGFAULTENA Mask             */\r
+\r
+/* ----------------------------------  PPB_CFSR  ---------------------------------- */\r
+#define PPB_CFSR_IACCVIOL_Pos                 0                                                       /*!< PPB CFSR: IACCVIOL Position             */\r
+#define PPB_CFSR_IACCVIOL_Msk                 (0x01UL << PPB_CFSR_IACCVIOL_Pos)                       /*!< PPB CFSR: IACCVIOL Mask                 */\r
+#define PPB_CFSR_DACCVIOL_Pos                 1                                                       /*!< PPB CFSR: DACCVIOL Position             */\r
+#define PPB_CFSR_DACCVIOL_Msk                 (0x01UL << PPB_CFSR_DACCVIOL_Pos)                       /*!< PPB CFSR: DACCVIOL Mask                 */\r
+#define PPB_CFSR_MUNSTKERR_Pos                3                                                       /*!< PPB CFSR: MUNSTKERR Position            */\r
+#define PPB_CFSR_MUNSTKERR_Msk                (0x01UL << PPB_CFSR_MUNSTKERR_Pos)                      /*!< PPB CFSR: MUNSTKERR Mask                */\r
+#define PPB_CFSR_MSTKERR_Pos                  4                                                       /*!< PPB CFSR: MSTKERR Position              */\r
+#define PPB_CFSR_MSTKERR_Msk                  (0x01UL << PPB_CFSR_MSTKERR_Pos)                        /*!< PPB CFSR: MSTKERR Mask                  */\r
+#define PPB_CFSR_MLSPERR_Pos                  5                                                       /*!< PPB CFSR: MLSPERR Position              */\r
+#define PPB_CFSR_MLSPERR_Msk                  (0x01UL << PPB_CFSR_MLSPERR_Pos)                        /*!< PPB CFSR: MLSPERR Mask                  */\r
+#define PPB_CFSR_MMARVALID_Pos                7                                                       /*!< PPB CFSR: MMARVALID Position            */\r
+#define PPB_CFSR_MMARVALID_Msk                (0x01UL << PPB_CFSR_MMARVALID_Pos)                      /*!< PPB CFSR: MMARVALID Mask                */\r
+#define PPB_CFSR_IBUSERR_Pos                  8                                                       /*!< PPB CFSR: IBUSERR Position              */\r
+#define PPB_CFSR_IBUSERR_Msk                  (0x01UL << PPB_CFSR_IBUSERR_Pos)                        /*!< PPB CFSR: IBUSERR Mask                  */\r
+#define PPB_CFSR_PRECISERR_Pos                9                                                       /*!< PPB CFSR: PRECISERR Position            */\r
+#define PPB_CFSR_PRECISERR_Msk                (0x01UL << PPB_CFSR_PRECISERR_Pos)                      /*!< PPB CFSR: PRECISERR Mask                */\r
+#define PPB_CFSR_IMPRECISERR_Pos              10                                                      /*!< PPB CFSR: IMPRECISERR Position          */\r
+#define PPB_CFSR_IMPRECISERR_Msk              (0x01UL << PPB_CFSR_IMPRECISERR_Pos)                    /*!< PPB CFSR: IMPRECISERR Mask              */\r
+#define PPB_CFSR_UNSTKERR_Pos                 11                                                      /*!< PPB CFSR: UNSTKERR Position             */\r
+#define PPB_CFSR_UNSTKERR_Msk                 (0x01UL << PPB_CFSR_UNSTKERR_Pos)                       /*!< PPB CFSR: UNSTKERR Mask                 */\r
+#define PPB_CFSR_STKERR_Pos                   12                                                      /*!< PPB CFSR: STKERR Position               */\r
+#define PPB_CFSR_STKERR_Msk                   (0x01UL << PPB_CFSR_STKERR_Pos)                         /*!< PPB CFSR: STKERR Mask                   */\r
+#define PPB_CFSR_LSPERR_Pos                   13                                                      /*!< PPB CFSR: LSPERR Position               */\r
+#define PPB_CFSR_LSPERR_Msk                   (0x01UL << PPB_CFSR_LSPERR_Pos)                         /*!< PPB CFSR: LSPERR Mask                   */\r
+#define PPB_CFSR_BFARVALID_Pos                15                                                      /*!< PPB CFSR: BFARVALID Position            */\r
+#define PPB_CFSR_BFARVALID_Msk                (0x01UL << PPB_CFSR_BFARVALID_Pos)                      /*!< PPB CFSR: BFARVALID Mask                */\r
+#define PPB_CFSR_UNDEFINSTR_Pos               16                                                      /*!< PPB CFSR: UNDEFINSTR Position           */\r
+#define PPB_CFSR_UNDEFINSTR_Msk               (0x01UL << PPB_CFSR_UNDEFINSTR_Pos)                     /*!< PPB CFSR: UNDEFINSTR Mask               */\r
+#define PPB_CFSR_INVSTATE_Pos                 17                                                      /*!< PPB CFSR: INVSTATE Position             */\r
+#define PPB_CFSR_INVSTATE_Msk                 (0x01UL << PPB_CFSR_INVSTATE_Pos)                       /*!< PPB CFSR: INVSTATE Mask                 */\r
+#define PPB_CFSR_INVPC_Pos                    18                                                      /*!< PPB CFSR: INVPC Position                */\r
+#define PPB_CFSR_INVPC_Msk                    (0x01UL << PPB_CFSR_INVPC_Pos)                          /*!< PPB CFSR: INVPC Mask                    */\r
+#define PPB_CFSR_NOCP_Pos                     19                                                      /*!< PPB CFSR: NOCP Position                 */\r
+#define PPB_CFSR_NOCP_Msk                     (0x01UL << PPB_CFSR_NOCP_Pos)                           /*!< PPB CFSR: NOCP Mask                     */\r
+#define PPB_CFSR_UNALIGNED_Pos                24                                                      /*!< PPB CFSR: UNALIGNED Position            */\r
+#define PPB_CFSR_UNALIGNED_Msk                (0x01UL << PPB_CFSR_UNALIGNED_Pos)                      /*!< PPB CFSR: UNALIGNED Mask                */\r
+#define PPB_CFSR_DIVBYZERO_Pos                25                                                      /*!< PPB CFSR: DIVBYZERO Position            */\r
+#define PPB_CFSR_DIVBYZERO_Msk                (0x01UL << PPB_CFSR_DIVBYZERO_Pos)                      /*!< PPB CFSR: DIVBYZERO Mask                */\r
+\r
+/* ----------------------------------  PPB_HFSR  ---------------------------------- */\r
+#define PPB_HFSR_VECTTBL_Pos                  1                                                       /*!< PPB HFSR: VECTTBL Position              */\r
+#define PPB_HFSR_VECTTBL_Msk                  (0x01UL << PPB_HFSR_VECTTBL_Pos)                        /*!< PPB HFSR: VECTTBL Mask                  */\r
+#define PPB_HFSR_FORCED_Pos                   30                                                      /*!< PPB HFSR: FORCED Position               */\r
+#define PPB_HFSR_FORCED_Msk                   (0x01UL << PPB_HFSR_FORCED_Pos)                         /*!< PPB HFSR: FORCED Mask                   */\r
+#define PPB_HFSR_DEBUGEVT_Pos                 31                                                      /*!< PPB HFSR: DEBUGEVT Position             */\r
+#define PPB_HFSR_DEBUGEVT_Msk                 (0x01UL << PPB_HFSR_DEBUGEVT_Pos)                       /*!< PPB HFSR: DEBUGEVT Mask                 */\r
+\r
+/* ----------------------------------  PPB_MMFAR  --------------------------------- */\r
+#define PPB_MMFAR_ADDRESS_Pos                 0                                                       /*!< PPB MMFAR: ADDRESS Position             */\r
+#define PPB_MMFAR_ADDRESS_Msk                 (0xffffffffUL << PPB_MMFAR_ADDRESS_Pos)                 /*!< PPB MMFAR: ADDRESS Mask                 */\r
+\r
+/* ----------------------------------  PPB_BFAR  ---------------------------------- */\r
+#define PPB_BFAR_ADDRESS_Pos                  0                                                       /*!< PPB BFAR: ADDRESS Position              */\r
+#define PPB_BFAR_ADDRESS_Msk                  (0xffffffffUL << PPB_BFAR_ADDRESS_Pos)                  /*!< PPB BFAR: ADDRESS Mask                  */\r
+\r
+/* ----------------------------------  PPB_AFSR  ---------------------------------- */\r
+#define PPB_AFSR_VALUE_Pos                    0                                                       /*!< PPB AFSR: VALUE Position                */\r
+#define PPB_AFSR_VALUE_Msk                    (0xffffffffUL << PPB_AFSR_VALUE_Pos)                    /*!< PPB AFSR: VALUE Mask                    */\r
+\r
+/* ----------------------------------  PPB_CPACR  --------------------------------- */\r
+#define PPB_CPACR_CP10_Pos                    20                                                      /*!< PPB CPACR: CP10 Position                */\r
+#define PPB_CPACR_CP10_Msk                    (0x03UL << PPB_CPACR_CP10_Pos)                          /*!< PPB CPACR: CP10 Mask                    */\r
+#define PPB_CPACR_CP11_Pos                    22                                                      /*!< PPB CPACR: CP11 Position                */\r
+#define PPB_CPACR_CP11_Msk                    (0x03UL << PPB_CPACR_CP11_Pos)                          /*!< PPB CPACR: CP11 Mask                    */\r
+\r
+/* --------------------------------  PPB_MPU_TYPE  -------------------------------- */\r
+#define PPB_MPU_TYPE_SEPARATE_Pos             0                                                       /*!< PPB MPU_TYPE: SEPARATE Position         */\r
+#define PPB_MPU_TYPE_SEPARATE_Msk             (0x01UL << PPB_MPU_TYPE_SEPARATE_Pos)                   /*!< PPB MPU_TYPE: SEPARATE Mask             */\r
+#define PPB_MPU_TYPE_DREGION_Pos              8                                                       /*!< PPB MPU_TYPE: DREGION Position          */\r
+#define PPB_MPU_TYPE_DREGION_Msk              (0x000000ffUL << PPB_MPU_TYPE_DREGION_Pos)              /*!< PPB MPU_TYPE: DREGION Mask              */\r
+#define PPB_MPU_TYPE_IREGION_Pos              16                                                      /*!< PPB MPU_TYPE: IREGION Position          */\r
+#define PPB_MPU_TYPE_IREGION_Msk              (0x000000ffUL << PPB_MPU_TYPE_IREGION_Pos)              /*!< PPB MPU_TYPE: IREGION Mask              */\r
+\r
+/* --------------------------------  PPB_MPU_CTRL  -------------------------------- */\r
+#define PPB_MPU_CTRL_ENABLE_Pos               0                                                       /*!< PPB MPU_CTRL: ENABLE Position           */\r
+#define PPB_MPU_CTRL_ENABLE_Msk               (0x01UL << PPB_MPU_CTRL_ENABLE_Pos)                     /*!< PPB MPU_CTRL: ENABLE Mask               */\r
+#define PPB_MPU_CTRL_HFNMIENA_Pos             1                                                       /*!< PPB MPU_CTRL: HFNMIENA Position         */\r
+#define PPB_MPU_CTRL_HFNMIENA_Msk             (0x01UL << PPB_MPU_CTRL_HFNMIENA_Pos)                   /*!< PPB MPU_CTRL: HFNMIENA Mask             */\r
+#define PPB_MPU_CTRL_PRIVDEFENA_Pos           2                                                       /*!< PPB MPU_CTRL: PRIVDEFENA Position       */\r
+#define PPB_MPU_CTRL_PRIVDEFENA_Msk           (0x01UL << PPB_MPU_CTRL_PRIVDEFENA_Pos)                 /*!< PPB MPU_CTRL: PRIVDEFENA Mask           */\r
+\r
+/* ---------------------------------  PPB_MPU_RNR  -------------------------------- */\r
+#define PPB_MPU_RNR_REGION_Pos                0                                                       /*!< PPB MPU_RNR: REGION Position            */\r
+#define PPB_MPU_RNR_REGION_Msk                (0x000000ffUL << PPB_MPU_RNR_REGION_Pos)                /*!< PPB MPU_RNR: REGION Mask                */\r
+\r
+/* --------------------------------  PPB_MPU_RBAR  -------------------------------- */\r
+#define PPB_MPU_RBAR_REGION_Pos               0                                                       /*!< PPB MPU_RBAR: REGION Position           */\r
+#define PPB_MPU_RBAR_REGION_Msk               (0x0fUL << PPB_MPU_RBAR_REGION_Pos)                     /*!< PPB MPU_RBAR: REGION Mask               */\r
+#define PPB_MPU_RBAR_VALID_Pos                4                                                       /*!< PPB MPU_RBAR: VALID Position            */\r
+#define PPB_MPU_RBAR_VALID_Msk                (0x01UL << PPB_MPU_RBAR_VALID_Pos)                      /*!< PPB MPU_RBAR: VALID Mask                */\r
+#define PPB_MPU_RBAR_ADDR_Pos                 9                                                       /*!< PPB MPU_RBAR: ADDR Position             */\r
+#define PPB_MPU_RBAR_ADDR_Msk                 (0x007fffffUL << PPB_MPU_RBAR_ADDR_Pos)                 /*!< PPB MPU_RBAR: ADDR Mask                 */\r
+\r
+/* --------------------------------  PPB_MPU_RASR  -------------------------------- */\r
+#define PPB_MPU_RASR_ENABLE_Pos               0                                                       /*!< PPB MPU_RASR: ENABLE Position           */\r
+#define PPB_MPU_RASR_ENABLE_Msk               (0x01UL << PPB_MPU_RASR_ENABLE_Pos)                     /*!< PPB MPU_RASR: ENABLE Mask               */\r
+#define PPB_MPU_RASR_SIZE_Pos                 1                                                       /*!< PPB MPU_RASR: SIZE Position             */\r
+#define PPB_MPU_RASR_SIZE_Msk                 (0x1fUL << PPB_MPU_RASR_SIZE_Pos)                       /*!< PPB MPU_RASR: SIZE Mask                 */\r
+#define PPB_MPU_RASR_SRD_Pos                  8                                                       /*!< PPB MPU_RASR: SRD Position              */\r
+#define PPB_MPU_RASR_SRD_Msk                  (0x000000ffUL << PPB_MPU_RASR_SRD_Pos)                  /*!< PPB MPU_RASR: SRD Mask                  */\r
+#define PPB_MPU_RASR_B_Pos                    16                                                      /*!< PPB MPU_RASR: B Position                */\r
+#define PPB_MPU_RASR_B_Msk                    (0x01UL << PPB_MPU_RASR_B_Pos)                          /*!< PPB MPU_RASR: B Mask                    */\r
+#define PPB_MPU_RASR_C_Pos                    17                                                      /*!< PPB MPU_RASR: C Position                */\r
+#define PPB_MPU_RASR_C_Msk                    (0x01UL << PPB_MPU_RASR_C_Pos)                          /*!< PPB MPU_RASR: C Mask                    */\r
+#define PPB_MPU_RASR_S_Pos                    18                                                      /*!< PPB MPU_RASR: S Position                */\r
+#define PPB_MPU_RASR_S_Msk                    (0x01UL << PPB_MPU_RASR_S_Pos)                          /*!< PPB MPU_RASR: S Mask                    */\r
+#define PPB_MPU_RASR_TEX_Pos                  19                                                      /*!< PPB MPU_RASR: TEX Position              */\r
+#define PPB_MPU_RASR_TEX_Msk                  (0x07UL << PPB_MPU_RASR_TEX_Pos)                        /*!< PPB MPU_RASR: TEX Mask                  */\r
+#define PPB_MPU_RASR_AP_Pos                   24                                                      /*!< PPB MPU_RASR: AP Position               */\r
+#define PPB_MPU_RASR_AP_Msk                   (0x07UL << PPB_MPU_RASR_AP_Pos)                         /*!< PPB MPU_RASR: AP Mask                   */\r
+#define PPB_MPU_RASR_XN_Pos                   28                                                      /*!< PPB MPU_RASR: XN Position               */\r
+#define PPB_MPU_RASR_XN_Msk                   (0x01UL << PPB_MPU_RASR_XN_Pos)                         /*!< PPB MPU_RASR: XN Mask                   */\r
+\r
+/* -------------------------------  PPB_MPU_RBAR_A1  ------------------------------ */\r
+#define PPB_MPU_RBAR_A1_REGION_Pos            0                                                       /*!< PPB MPU_RBAR_A1: REGION Position        */\r
+#define PPB_MPU_RBAR_A1_REGION_Msk            (0x0fUL << PPB_MPU_RBAR_A1_REGION_Pos)                  /*!< PPB MPU_RBAR_A1: REGION Mask            */\r
+#define PPB_MPU_RBAR_A1_VALID_Pos             4                                                       /*!< PPB MPU_RBAR_A1: VALID Position         */\r
+#define PPB_MPU_RBAR_A1_VALID_Msk             (0x01UL << PPB_MPU_RBAR_A1_VALID_Pos)                   /*!< PPB MPU_RBAR_A1: VALID Mask             */\r
+#define PPB_MPU_RBAR_A1_ADDR_Pos              9                                                       /*!< PPB MPU_RBAR_A1: ADDR Position          */\r
+#define PPB_MPU_RBAR_A1_ADDR_Msk              (0x007fffffUL << PPB_MPU_RBAR_A1_ADDR_Pos)              /*!< PPB MPU_RBAR_A1: ADDR Mask              */\r
+\r
+/* -------------------------------  PPB_MPU_RASR_A1  ------------------------------ */\r
+#define PPB_MPU_RASR_A1_ENABLE_Pos            0                                                       /*!< PPB MPU_RASR_A1: ENABLE Position        */\r
+#define PPB_MPU_RASR_A1_ENABLE_Msk            (0x01UL << PPB_MPU_RASR_A1_ENABLE_Pos)                  /*!< PPB MPU_RASR_A1: ENABLE Mask            */\r
+#define PPB_MPU_RASR_A1_SIZE_Pos              1                                                       /*!< PPB MPU_RASR_A1: SIZE Position          */\r
+#define PPB_MPU_RASR_A1_SIZE_Msk              (0x1fUL << PPB_MPU_RASR_A1_SIZE_Pos)                    /*!< PPB MPU_RASR_A1: SIZE Mask              */\r
+#define PPB_MPU_RASR_A1_SRD_Pos               8                                                       /*!< PPB MPU_RASR_A1: SRD Position           */\r
+#define PPB_MPU_RASR_A1_SRD_Msk               (0x000000ffUL << PPB_MPU_RASR_A1_SRD_Pos)               /*!< PPB MPU_RASR_A1: SRD Mask               */\r
+#define PPB_MPU_RASR_A1_B_Pos                 16                                                      /*!< PPB MPU_RASR_A1: B Position             */\r
+#define PPB_MPU_RASR_A1_B_Msk                 (0x01UL << PPB_MPU_RASR_A1_B_Pos)                       /*!< PPB MPU_RASR_A1: B Mask                 */\r
+#define PPB_MPU_RASR_A1_C_Pos                 17                                                      /*!< PPB MPU_RASR_A1: C Position             */\r
+#define PPB_MPU_RASR_A1_C_Msk                 (0x01UL << PPB_MPU_RASR_A1_C_Pos)                       /*!< PPB MPU_RASR_A1: C Mask                 */\r
+#define PPB_MPU_RASR_A1_S_Pos                 18                                                      /*!< PPB MPU_RASR_A1: S Position             */\r
+#define PPB_MPU_RASR_A1_S_Msk                 (0x01UL << PPB_MPU_RASR_A1_S_Pos)                       /*!< PPB MPU_RASR_A1: S Mask                 */\r
+#define PPB_MPU_RASR_A1_TEX_Pos               19                                                      /*!< PPB MPU_RASR_A1: TEX Position           */\r
+#define PPB_MPU_RASR_A1_TEX_Msk               (0x07UL << PPB_MPU_RASR_A1_TEX_Pos)                     /*!< PPB MPU_RASR_A1: TEX Mask               */\r
+#define PPB_MPU_RASR_A1_AP_Pos                24                                                      /*!< PPB MPU_RASR_A1: AP Position            */\r
+#define PPB_MPU_RASR_A1_AP_Msk                (0x07UL << PPB_MPU_RASR_A1_AP_Pos)                      /*!< PPB MPU_RASR_A1: AP Mask                */\r
+#define PPB_MPU_RASR_A1_XN_Pos                28                                                      /*!< PPB MPU_RASR_A1: XN Position            */\r
+#define PPB_MPU_RASR_A1_XN_Msk                (0x01UL << PPB_MPU_RASR_A1_XN_Pos)                      /*!< PPB MPU_RASR_A1: XN Mask                */\r
+\r
+/* -------------------------------  PPB_MPU_RBAR_A2  ------------------------------ */\r
+#define PPB_MPU_RBAR_A2_REGION_Pos            0                                                       /*!< PPB MPU_RBAR_A2: REGION Position        */\r
+#define PPB_MPU_RBAR_A2_REGION_Msk            (0x0fUL << PPB_MPU_RBAR_A2_REGION_Pos)                  /*!< PPB MPU_RBAR_A2: REGION Mask            */\r
+#define PPB_MPU_RBAR_A2_VALID_Pos             4                                                       /*!< PPB MPU_RBAR_A2: VALID Position         */\r
+#define PPB_MPU_RBAR_A2_VALID_Msk             (0x01UL << PPB_MPU_RBAR_A2_VALID_Pos)                   /*!< PPB MPU_RBAR_A2: VALID Mask             */\r
+#define PPB_MPU_RBAR_A2_ADDR_Pos              9                                                       /*!< PPB MPU_RBAR_A2: ADDR Position          */\r
+#define PPB_MPU_RBAR_A2_ADDR_Msk              (0x007fffffUL << PPB_MPU_RBAR_A2_ADDR_Pos)              /*!< PPB MPU_RBAR_A2: ADDR Mask              */\r
+\r
+/* -------------------------------  PPB_MPU_RASR_A2  ------------------------------ */\r
+#define PPB_MPU_RASR_A2_ENABLE_Pos            0                                                       /*!< PPB MPU_RASR_A2: ENABLE Position        */\r
+#define PPB_MPU_RASR_A2_ENABLE_Msk            (0x01UL << PPB_MPU_RASR_A2_ENABLE_Pos)                  /*!< PPB MPU_RASR_A2: ENABLE Mask            */\r
+#define PPB_MPU_RASR_A2_SIZE_Pos              1                                                       /*!< PPB MPU_RASR_A2: SIZE Position          */\r
+#define PPB_MPU_RASR_A2_SIZE_Msk              (0x1fUL << PPB_MPU_RASR_A2_SIZE_Pos)                    /*!< PPB MPU_RASR_A2: SIZE Mask              */\r
+#define PPB_MPU_RASR_A2_SRD_Pos               8                                                       /*!< PPB MPU_RASR_A2: SRD Position           */\r
+#define PPB_MPU_RASR_A2_SRD_Msk               (0x000000ffUL << PPB_MPU_RASR_A2_SRD_Pos)               /*!< PPB MPU_RASR_A2: SRD Mask               */\r
+#define PPB_MPU_RASR_A2_B_Pos                 16                                                      /*!< PPB MPU_RASR_A2: B Position             */\r
+#define PPB_MPU_RASR_A2_B_Msk                 (0x01UL << PPB_MPU_RASR_A2_B_Pos)                       /*!< PPB MPU_RASR_A2: B Mask                 */\r
+#define PPB_MPU_RASR_A2_C_Pos                 17                                                      /*!< PPB MPU_RASR_A2: C Position             */\r
+#define PPB_MPU_RASR_A2_C_Msk                 (0x01UL << PPB_MPU_RASR_A2_C_Pos)                       /*!< PPB MPU_RASR_A2: C Mask                 */\r
+#define PPB_MPU_RASR_A2_S_Pos                 18                                                      /*!< PPB MPU_RASR_A2: S Position             */\r
+#define PPB_MPU_RASR_A2_S_Msk                 (0x01UL << PPB_MPU_RASR_A2_S_Pos)                       /*!< PPB MPU_RASR_A2: S Mask                 */\r
+#define PPB_MPU_RASR_A2_TEX_Pos               19                                                      /*!< PPB MPU_RASR_A2: TEX Position           */\r
+#define PPB_MPU_RASR_A2_TEX_Msk               (0x07UL << PPB_MPU_RASR_A2_TEX_Pos)                     /*!< PPB MPU_RASR_A2: TEX Mask               */\r
+#define PPB_MPU_RASR_A2_AP_Pos                24                                                      /*!< PPB MPU_RASR_A2: AP Position            */\r
+#define PPB_MPU_RASR_A2_AP_Msk                (0x07UL << PPB_MPU_RASR_A2_AP_Pos)                      /*!< PPB MPU_RASR_A2: AP Mask                */\r
+#define PPB_MPU_RASR_A2_XN_Pos                28                                                      /*!< PPB MPU_RASR_A2: XN Position            */\r
+#define PPB_MPU_RASR_A2_XN_Msk                (0x01UL << PPB_MPU_RASR_A2_XN_Pos)                      /*!< PPB MPU_RASR_A2: XN Mask                */\r
+\r
+/* -------------------------------  PPB_MPU_RBAR_A3  ------------------------------ */\r
+#define PPB_MPU_RBAR_A3_REGION_Pos            0                                                       /*!< PPB MPU_RBAR_A3: REGION Position        */\r
+#define PPB_MPU_RBAR_A3_REGION_Msk            (0x0fUL << PPB_MPU_RBAR_A3_REGION_Pos)                  /*!< PPB MPU_RBAR_A3: REGION Mask            */\r
+#define PPB_MPU_RBAR_A3_VALID_Pos             4                                                       /*!< PPB MPU_RBAR_A3: VALID Position         */\r
+#define PPB_MPU_RBAR_A3_VALID_Msk             (0x01UL << PPB_MPU_RBAR_A3_VALID_Pos)                   /*!< PPB MPU_RBAR_A3: VALID Mask             */\r
+#define PPB_MPU_RBAR_A3_ADDR_Pos              9                                                       /*!< PPB MPU_RBAR_A3: ADDR Position          */\r
+#define PPB_MPU_RBAR_A3_ADDR_Msk              (0x007fffffUL << PPB_MPU_RBAR_A3_ADDR_Pos)              /*!< PPB MPU_RBAR_A3: ADDR Mask              */\r
+\r
+/* -------------------------------  PPB_MPU_RASR_A3  ------------------------------ */\r
+#define PPB_MPU_RASR_A3_ENABLE_Pos            0                                                       /*!< PPB MPU_RASR_A3: ENABLE Position        */\r
+#define PPB_MPU_RASR_A3_ENABLE_Msk            (0x01UL << PPB_MPU_RASR_A3_ENABLE_Pos)                  /*!< PPB MPU_RASR_A3: ENABLE Mask            */\r
+#define PPB_MPU_RASR_A3_SIZE_Pos              1                                                       /*!< PPB MPU_RASR_A3: SIZE Position          */\r
+#define PPB_MPU_RASR_A3_SIZE_Msk              (0x1fUL << PPB_MPU_RASR_A3_SIZE_Pos)                    /*!< PPB MPU_RASR_A3: SIZE Mask              */\r
+#define PPB_MPU_RASR_A3_SRD_Pos               8                                                       /*!< PPB MPU_RASR_A3: SRD Position           */\r
+#define PPB_MPU_RASR_A3_SRD_Msk               (0x000000ffUL << PPB_MPU_RASR_A3_SRD_Pos)               /*!< PPB MPU_RASR_A3: SRD Mask               */\r
+#define PPB_MPU_RASR_A3_B_Pos                 16                                                      /*!< PPB MPU_RASR_A3: B Position             */\r
+#define PPB_MPU_RASR_A3_B_Msk                 (0x01UL << PPB_MPU_RASR_A3_B_Pos)                       /*!< PPB MPU_RASR_A3: B Mask                 */\r
+#define PPB_MPU_RASR_A3_C_Pos                 17                                                      /*!< PPB MPU_RASR_A3: C Position             */\r
+#define PPB_MPU_RASR_A3_C_Msk                 (0x01UL << PPB_MPU_RASR_A3_C_Pos)                       /*!< PPB MPU_RASR_A3: C Mask                 */\r
+#define PPB_MPU_RASR_A3_S_Pos                 18                                                      /*!< PPB MPU_RASR_A3: S Position             */\r
+#define PPB_MPU_RASR_A3_S_Msk                 (0x01UL << PPB_MPU_RASR_A3_S_Pos)                       /*!< PPB MPU_RASR_A3: S Mask                 */\r
+#define PPB_MPU_RASR_A3_TEX_Pos               19                                                      /*!< PPB MPU_RASR_A3: TEX Position           */\r
+#define PPB_MPU_RASR_A3_TEX_Msk               (0x07UL << PPB_MPU_RASR_A3_TEX_Pos)                     /*!< PPB MPU_RASR_A3: TEX Mask               */\r
+#define PPB_MPU_RASR_A3_AP_Pos                24                                                      /*!< PPB MPU_RASR_A3: AP Position            */\r
+#define PPB_MPU_RASR_A3_AP_Msk                (0x07UL << PPB_MPU_RASR_A3_AP_Pos)                      /*!< PPB MPU_RASR_A3: AP Mask                */\r
+#define PPB_MPU_RASR_A3_XN_Pos                28                                                      /*!< PPB MPU_RASR_A3: XN Position            */\r
+#define PPB_MPU_RASR_A3_XN_Msk                (0x01UL << PPB_MPU_RASR_A3_XN_Pos)                      /*!< PPB MPU_RASR_A3: XN Mask                */\r
+\r
+/* ----------------------------------  PPB_STIR  ---------------------------------- */\r
+#define PPB_STIR_INTID_Pos                    0                                                       /*!< PPB STIR: INTID Position                */\r
+#define PPB_STIR_INTID_Msk                    (0x000001ffUL << PPB_STIR_INTID_Pos)                    /*!< PPB STIR: INTID Mask                    */\r
+\r
+/* ----------------------------------  PPB_FPCCR  --------------------------------- */\r
+#define PPB_FPCCR_LSPACT_Pos                  0                                                       /*!< PPB FPCCR: LSPACT Position              */\r
+#define PPB_FPCCR_LSPACT_Msk                  (0x01UL << PPB_FPCCR_LSPACT_Pos)                        /*!< PPB FPCCR: LSPACT Mask                  */\r
+#define PPB_FPCCR_USER_Pos                    1                                                       /*!< PPB FPCCR: USER Position                */\r
+#define PPB_FPCCR_USER_Msk                    (0x01UL << PPB_FPCCR_USER_Pos)                          /*!< PPB FPCCR: USER Mask                    */\r
+#define PPB_FPCCR_THREAD_Pos                  3                                                       /*!< PPB FPCCR: THREAD Position              */\r
+#define PPB_FPCCR_THREAD_Msk                  (0x01UL << PPB_FPCCR_THREAD_Pos)                        /*!< PPB FPCCR: THREAD Mask                  */\r
+#define PPB_FPCCR_HFRDY_Pos                   4                                                       /*!< PPB FPCCR: HFRDY Position               */\r
+#define PPB_FPCCR_HFRDY_Msk                   (0x01UL << PPB_FPCCR_HFRDY_Pos)                         /*!< PPB FPCCR: HFRDY Mask                   */\r
+#define PPB_FPCCR_MMRDY_Pos                   5                                                       /*!< PPB FPCCR: MMRDY Position               */\r
+#define PPB_FPCCR_MMRDY_Msk                   (0x01UL << PPB_FPCCR_MMRDY_Pos)                         /*!< PPB FPCCR: MMRDY Mask                   */\r
+#define PPB_FPCCR_BFRDY_Pos                   6                                                       /*!< PPB FPCCR: BFRDY Position               */\r
+#define PPB_FPCCR_BFRDY_Msk                   (0x01UL << PPB_FPCCR_BFRDY_Pos)                         /*!< PPB FPCCR: BFRDY Mask                   */\r
+#define PPB_FPCCR_MONRDY_Pos                  8                                                       /*!< PPB FPCCR: MONRDY Position              */\r
+#define PPB_FPCCR_MONRDY_Msk                  (0x01UL << PPB_FPCCR_MONRDY_Pos)                        /*!< PPB FPCCR: MONRDY Mask                  */\r
+#define PPB_FPCCR_LSPEN_Pos                   30                                                      /*!< PPB FPCCR: LSPEN Position               */\r
+#define PPB_FPCCR_LSPEN_Msk                   (0x01UL << PPB_FPCCR_LSPEN_Pos)                         /*!< PPB FPCCR: LSPEN Mask                   */\r
+#define PPB_FPCCR_ASPEN_Pos                   31                                                      /*!< PPB FPCCR: ASPEN Position               */\r
+#define PPB_FPCCR_ASPEN_Msk                   (0x01UL << PPB_FPCCR_ASPEN_Pos)                         /*!< PPB FPCCR: ASPEN Mask                   */\r
+\r
+/* ----------------------------------  PPB_FPCAR  --------------------------------- */\r
+#define PPB_FPCAR_ADDRESS_Pos                 3                                                       /*!< PPB FPCAR: ADDRESS Position             */\r
+#define PPB_FPCAR_ADDRESS_Msk                 (0x1fffffffUL << PPB_FPCAR_ADDRESS_Pos)                 /*!< PPB FPCAR: ADDRESS Mask                 */\r
+\r
+/* ---------------------------------  PPB_FPDSCR  --------------------------------- */\r
+#define PPB_FPDSCR_RMode_Pos                  22                                                      /*!< PPB FPDSCR: RMode Position              */\r
+#define PPB_FPDSCR_RMode_Msk                  (0x03UL << PPB_FPDSCR_RMode_Pos)                        /*!< PPB FPDSCR: RMode Mask                  */\r
+#define PPB_FPDSCR_FZ_Pos                     24                                                      /*!< PPB FPDSCR: FZ Position                 */\r
+#define PPB_FPDSCR_FZ_Msk                     (0x01UL << PPB_FPDSCR_FZ_Pos)                           /*!< PPB FPDSCR: FZ Mask                     */\r
+#define PPB_FPDSCR_DN_Pos                     25                                                      /*!< PPB FPDSCR: DN Position                 */\r
+#define PPB_FPDSCR_DN_Msk                     (0x01UL << PPB_FPDSCR_DN_Pos)                           /*!< PPB FPDSCR: DN Mask                     */\r
+#define PPB_FPDSCR_AHP_Pos                    26                                                      /*!< PPB FPDSCR: AHP Position                */\r
+#define PPB_FPDSCR_AHP_Msk                    (0x01UL << PPB_FPDSCR_AHP_Pos)                          /*!< PPB FPDSCR: AHP Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'DLR' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  DLR_OVRSTAT  -------------------------------- */\r
+#define DLR_OVRSTAT_LN0_Pos                   0                                                       /*!< DLR OVRSTAT: LN0 Position               */\r
+#define DLR_OVRSTAT_LN0_Msk                   (0x01UL << DLR_OVRSTAT_LN0_Pos)                         /*!< DLR OVRSTAT: LN0 Mask                   */\r
+#define DLR_OVRSTAT_LN1_Pos                   1                                                       /*!< DLR OVRSTAT: LN1 Position               */\r
+#define DLR_OVRSTAT_LN1_Msk                   (0x01UL << DLR_OVRSTAT_LN1_Pos)                         /*!< DLR OVRSTAT: LN1 Mask                   */\r
+#define DLR_OVRSTAT_LN2_Pos                   2                                                       /*!< DLR OVRSTAT: LN2 Position               */\r
+#define DLR_OVRSTAT_LN2_Msk                   (0x01UL << DLR_OVRSTAT_LN2_Pos)                         /*!< DLR OVRSTAT: LN2 Mask                   */\r
+#define DLR_OVRSTAT_LN3_Pos                   3                                                       /*!< DLR OVRSTAT: LN3 Position               */\r
+#define DLR_OVRSTAT_LN3_Msk                   (0x01UL << DLR_OVRSTAT_LN3_Pos)                         /*!< DLR OVRSTAT: LN3 Mask                   */\r
+#define DLR_OVRSTAT_LN4_Pos                   4                                                       /*!< DLR OVRSTAT: LN4 Position               */\r
+#define DLR_OVRSTAT_LN4_Msk                   (0x01UL << DLR_OVRSTAT_LN4_Pos)                         /*!< DLR OVRSTAT: LN4 Mask                   */\r
+#define DLR_OVRSTAT_LN5_Pos                   5                                                       /*!< DLR OVRSTAT: LN5 Position               */\r
+#define DLR_OVRSTAT_LN5_Msk                   (0x01UL << DLR_OVRSTAT_LN5_Pos)                         /*!< DLR OVRSTAT: LN5 Mask                   */\r
+#define DLR_OVRSTAT_LN6_Pos                   6                                                       /*!< DLR OVRSTAT: LN6 Position               */\r
+#define DLR_OVRSTAT_LN6_Msk                   (0x01UL << DLR_OVRSTAT_LN6_Pos)                         /*!< DLR OVRSTAT: LN6 Mask                   */\r
+#define DLR_OVRSTAT_LN7_Pos                   7                                                       /*!< DLR OVRSTAT: LN7 Position               */\r
+#define DLR_OVRSTAT_LN7_Msk                   (0x01UL << DLR_OVRSTAT_LN7_Pos)                         /*!< DLR OVRSTAT: LN7 Mask                   */\r
+\r
+/* ---------------------------------  DLR_OVRCLR  --------------------------------- */\r
+#define DLR_OVRCLR_LN0_Pos                    0                                                       /*!< DLR OVRCLR: LN0 Position                */\r
+#define DLR_OVRCLR_LN0_Msk                    (0x01UL << DLR_OVRCLR_LN0_Pos)                          /*!< DLR OVRCLR: LN0 Mask                    */\r
+#define DLR_OVRCLR_LN1_Pos                    1                                                       /*!< DLR OVRCLR: LN1 Position                */\r
+#define DLR_OVRCLR_LN1_Msk                    (0x01UL << DLR_OVRCLR_LN1_Pos)                          /*!< DLR OVRCLR: LN1 Mask                    */\r
+#define DLR_OVRCLR_LN2_Pos                    2                                                       /*!< DLR OVRCLR: LN2 Position                */\r
+#define DLR_OVRCLR_LN2_Msk                    (0x01UL << DLR_OVRCLR_LN2_Pos)                          /*!< DLR OVRCLR: LN2 Mask                    */\r
+#define DLR_OVRCLR_LN3_Pos                    3                                                       /*!< DLR OVRCLR: LN3 Position                */\r
+#define DLR_OVRCLR_LN3_Msk                    (0x01UL << DLR_OVRCLR_LN3_Pos)                          /*!< DLR OVRCLR: LN3 Mask                    */\r
+#define DLR_OVRCLR_LN4_Pos                    4                                                       /*!< DLR OVRCLR: LN4 Position                */\r
+#define DLR_OVRCLR_LN4_Msk                    (0x01UL << DLR_OVRCLR_LN4_Pos)                          /*!< DLR OVRCLR: LN4 Mask                    */\r
+#define DLR_OVRCLR_LN5_Pos                    5                                                       /*!< DLR OVRCLR: LN5 Position                */\r
+#define DLR_OVRCLR_LN5_Msk                    (0x01UL << DLR_OVRCLR_LN5_Pos)                          /*!< DLR OVRCLR: LN5 Mask                    */\r
+#define DLR_OVRCLR_LN6_Pos                    6                                                       /*!< DLR OVRCLR: LN6 Position                */\r
+#define DLR_OVRCLR_LN6_Msk                    (0x01UL << DLR_OVRCLR_LN6_Pos)                          /*!< DLR OVRCLR: LN6 Mask                    */\r
+#define DLR_OVRCLR_LN7_Pos                    7                                                       /*!< DLR OVRCLR: LN7 Position                */\r
+#define DLR_OVRCLR_LN7_Msk                    (0x01UL << DLR_OVRCLR_LN7_Pos)                          /*!< DLR OVRCLR: LN7 Mask                    */\r
+\r
+/* ---------------------------------  DLR_SRSEL0  --------------------------------- */\r
+#define DLR_SRSEL0_RS0_Pos                    0                                                       /*!< DLR SRSEL0: RS0 Position                */\r
+#define DLR_SRSEL0_RS0_Msk                    (0x0fUL << DLR_SRSEL0_RS0_Pos)                          /*!< DLR SRSEL0: RS0 Mask                    */\r
+#define DLR_SRSEL0_RS1_Pos                    4                                                       /*!< DLR SRSEL0: RS1 Position                */\r
+#define DLR_SRSEL0_RS1_Msk                    (0x0fUL << DLR_SRSEL0_RS1_Pos)                          /*!< DLR SRSEL0: RS1 Mask                    */\r
+#define DLR_SRSEL0_RS2_Pos                    8                                                       /*!< DLR SRSEL0: RS2 Position                */\r
+#define DLR_SRSEL0_RS2_Msk                    (0x0fUL << DLR_SRSEL0_RS2_Pos)                          /*!< DLR SRSEL0: RS2 Mask                    */\r
+#define DLR_SRSEL0_RS3_Pos                    12                                                      /*!< DLR SRSEL0: RS3 Position                */\r
+#define DLR_SRSEL0_RS3_Msk                    (0x0fUL << DLR_SRSEL0_RS3_Pos)                          /*!< DLR SRSEL0: RS3 Mask                    */\r
+#define DLR_SRSEL0_RS4_Pos                    16                                                      /*!< DLR SRSEL0: RS4 Position                */\r
+#define DLR_SRSEL0_RS4_Msk                    (0x0fUL << DLR_SRSEL0_RS4_Pos)                          /*!< DLR SRSEL0: RS4 Mask                    */\r
+#define DLR_SRSEL0_RS5_Pos                    20                                                      /*!< DLR SRSEL0: RS5 Position                */\r
+#define DLR_SRSEL0_RS5_Msk                    (0x0fUL << DLR_SRSEL0_RS5_Pos)                          /*!< DLR SRSEL0: RS5 Mask                    */\r
+#define DLR_SRSEL0_RS6_Pos                    24                                                      /*!< DLR SRSEL0: RS6 Position                */\r
+#define DLR_SRSEL0_RS6_Msk                    (0x0fUL << DLR_SRSEL0_RS6_Pos)                          /*!< DLR SRSEL0: RS6 Mask                    */\r
+#define DLR_SRSEL0_RS7_Pos                    28                                                      /*!< DLR SRSEL0: RS7 Position                */\r
+#define DLR_SRSEL0_RS7_Msk                    (0x0fUL << DLR_SRSEL0_RS7_Pos)                          /*!< DLR SRSEL0: RS7 Mask                    */\r
+\r
+/* ----------------------------------  DLR_LNEN  ---------------------------------- */\r
+#define DLR_LNEN_LN0_Pos                      0                                                       /*!< DLR LNEN: LN0 Position                  */\r
+#define DLR_LNEN_LN0_Msk                      (0x01UL << DLR_LNEN_LN0_Pos)                            /*!< DLR LNEN: LN0 Mask                      */\r
+#define DLR_LNEN_LN1_Pos                      1                                                       /*!< DLR LNEN: LN1 Position                  */\r
+#define DLR_LNEN_LN1_Msk                      (0x01UL << DLR_LNEN_LN1_Pos)                            /*!< DLR LNEN: LN1 Mask                      */\r
+#define DLR_LNEN_LN2_Pos                      2                                                       /*!< DLR LNEN: LN2 Position                  */\r
+#define DLR_LNEN_LN2_Msk                      (0x01UL << DLR_LNEN_LN2_Pos)                            /*!< DLR LNEN: LN2 Mask                      */\r
+#define DLR_LNEN_LN3_Pos                      3                                                       /*!< DLR LNEN: LN3 Position                  */\r
+#define DLR_LNEN_LN3_Msk                      (0x01UL << DLR_LNEN_LN3_Pos)                            /*!< DLR LNEN: LN3 Mask                      */\r
+#define DLR_LNEN_LN4_Pos                      4                                                       /*!< DLR LNEN: LN4 Position                  */\r
+#define DLR_LNEN_LN4_Msk                      (0x01UL << DLR_LNEN_LN4_Pos)                            /*!< DLR LNEN: LN4 Mask                      */\r
+#define DLR_LNEN_LN5_Pos                      5                                                       /*!< DLR LNEN: LN5 Position                  */\r
+#define DLR_LNEN_LN5_Msk                      (0x01UL << DLR_LNEN_LN5_Pos)                            /*!< DLR LNEN: LN5 Mask                      */\r
+#define DLR_LNEN_LN6_Pos                      6                                                       /*!< DLR LNEN: LN6 Position                  */\r
+#define DLR_LNEN_LN6_Msk                      (0x01UL << DLR_LNEN_LN6_Pos)                            /*!< DLR LNEN: LN6 Mask                      */\r
+#define DLR_LNEN_LN7_Pos                      7                                                       /*!< DLR LNEN: LN7 Position                  */\r
+#define DLR_LNEN_LN7_Msk                      (0x01UL << DLR_LNEN_LN7_Pos)                            /*!< DLR LNEN: LN7 Mask                      */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'ERU' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  ERU_EXISEL  --------------------------------- */\r
+#define ERU_EXISEL_EXS0A_Pos                  0                                                       /*!< ERU EXISEL: EXS0A Position              */\r
+#define ERU_EXISEL_EXS0A_Msk                  (0x03UL << ERU_EXISEL_EXS0A_Pos)                        /*!< ERU EXISEL: EXS0A Mask                  */\r
+#define ERU_EXISEL_EXS0B_Pos                  2                                                       /*!< ERU EXISEL: EXS0B Position              */\r
+#define ERU_EXISEL_EXS0B_Msk                  (0x03UL << ERU_EXISEL_EXS0B_Pos)                        /*!< ERU EXISEL: EXS0B Mask                  */\r
+#define ERU_EXISEL_EXS1A_Pos                  4                                                       /*!< ERU EXISEL: EXS1A Position              */\r
+#define ERU_EXISEL_EXS1A_Msk                  (0x03UL << ERU_EXISEL_EXS1A_Pos)                        /*!< ERU EXISEL: EXS1A Mask                  */\r
+#define ERU_EXISEL_EXS1B_Pos                  6                                                       /*!< ERU EXISEL: EXS1B Position              */\r
+#define ERU_EXISEL_EXS1B_Msk                  (0x03UL << ERU_EXISEL_EXS1B_Pos)                        /*!< ERU EXISEL: EXS1B Mask                  */\r
+#define ERU_EXISEL_EXS2A_Pos                  8                                                       /*!< ERU EXISEL: EXS2A Position              */\r
+#define ERU_EXISEL_EXS2A_Msk                  (0x03UL << ERU_EXISEL_EXS2A_Pos)                        /*!< ERU EXISEL: EXS2A Mask                  */\r
+#define ERU_EXISEL_EXS2B_Pos                  10                                                      /*!< ERU EXISEL: EXS2B Position              */\r
+#define ERU_EXISEL_EXS2B_Msk                  (0x03UL << ERU_EXISEL_EXS2B_Pos)                        /*!< ERU EXISEL: EXS2B Mask                  */\r
+#define ERU_EXISEL_EXS3A_Pos                  12                                                      /*!< ERU EXISEL: EXS3A Position              */\r
+#define ERU_EXISEL_EXS3A_Msk                  (0x03UL << ERU_EXISEL_EXS3A_Pos)                        /*!< ERU EXISEL: EXS3A Mask                  */\r
+#define ERU_EXISEL_EXS3B_Pos                  14                                                      /*!< ERU EXISEL: EXS3B Position              */\r
+#define ERU_EXISEL_EXS3B_Msk                  (0x03UL << ERU_EXISEL_EXS3B_Pos)                        /*!< ERU EXISEL: EXS3B Mask                  */\r
+\r
+/* ---------------------------------  ERU_EXICON  --------------------------------- */\r
+#define ERU_EXICON_PE_Pos                     0                                                       /*!< ERU EXICON: PE Position                 */\r
+#define ERU_EXICON_PE_Msk                     (0x01UL << ERU_EXICON_PE_Pos)                           /*!< ERU EXICON: PE Mask                     */\r
+#define ERU_EXICON_LD_Pos                     1                                                       /*!< ERU EXICON: LD Position                 */\r
+#define ERU_EXICON_LD_Msk                     (0x01UL << ERU_EXICON_LD_Pos)                           /*!< ERU EXICON: LD Mask                     */\r
+#define ERU_EXICON_RE_Pos                     2                                                       /*!< ERU EXICON: RE Position                 */\r
+#define ERU_EXICON_RE_Msk                     (0x01UL << ERU_EXICON_RE_Pos)                           /*!< ERU EXICON: RE Mask                     */\r
+#define ERU_EXICON_FE_Pos                     3                                                       /*!< ERU EXICON: FE Position                 */\r
+#define ERU_EXICON_FE_Msk                     (0x01UL << ERU_EXICON_FE_Pos)                           /*!< ERU EXICON: FE Mask                     */\r
+#define ERU_EXICON_OCS_Pos                    4                                                       /*!< ERU EXICON: OCS Position                */\r
+#define ERU_EXICON_OCS_Msk                    (0x07UL << ERU_EXICON_OCS_Pos)                          /*!< ERU EXICON: OCS Mask                    */\r
+#define ERU_EXICON_FL_Pos                     7                                                       /*!< ERU EXICON: FL Position                 */\r
+#define ERU_EXICON_FL_Msk                     (0x01UL << ERU_EXICON_FL_Pos)                           /*!< ERU EXICON: FL Mask                     */\r
+#define ERU_EXICON_SS_Pos                     8                                                       /*!< ERU EXICON: SS Position                 */\r
+#define ERU_EXICON_SS_Msk                     (0x03UL << ERU_EXICON_SS_Pos)                           /*!< ERU EXICON: SS Mask                     */\r
+#define ERU_EXICON_NA_Pos                     10                                                      /*!< ERU EXICON: NA Position                 */\r
+#define ERU_EXICON_NA_Msk                     (0x01UL << ERU_EXICON_NA_Pos)                           /*!< ERU EXICON: NA Mask                     */\r
+#define ERU_EXICON_NB_Pos                     11                                                      /*!< ERU EXICON: NB Position                 */\r
+#define ERU_EXICON_NB_Msk                     (0x01UL << ERU_EXICON_NB_Pos)                           /*!< ERU EXICON: NB Mask                     */\r
+\r
+/* ---------------------------------  ERU_EXOCON  --------------------------------- */\r
+#define ERU_EXOCON_ISS_Pos                    0                                                       /*!< ERU EXOCON: ISS Position                */\r
+#define ERU_EXOCON_ISS_Msk                    (0x03UL << ERU_EXOCON_ISS_Pos)                          /*!< ERU EXOCON: ISS Mask                    */\r
+#define ERU_EXOCON_GEEN_Pos                   2                                                       /*!< ERU EXOCON: GEEN Position               */\r
+#define ERU_EXOCON_GEEN_Msk                   (0x01UL << ERU_EXOCON_GEEN_Pos)                         /*!< ERU EXOCON: GEEN Mask                   */\r
+#define ERU_EXOCON_PDR_Pos                    3                                                       /*!< ERU EXOCON: PDR Position                */\r
+#define ERU_EXOCON_PDR_Msk                    (0x01UL << ERU_EXOCON_PDR_Pos)                          /*!< ERU EXOCON: PDR Mask                    */\r
+#define ERU_EXOCON_GP_Pos                     4                                                       /*!< ERU EXOCON: GP Position                 */\r
+#define ERU_EXOCON_GP_Msk                     (0x03UL << ERU_EXOCON_GP_Pos)                           /*!< ERU EXOCON: GP Mask                     */\r
+#define ERU_EXOCON_IPEN0_Pos                  12                                                      /*!< ERU EXOCON: IPEN0 Position              */\r
+#define ERU_EXOCON_IPEN0_Msk                  (0x01UL << ERU_EXOCON_IPEN0_Pos)                        /*!< ERU EXOCON: IPEN0 Mask                  */\r
+#define ERU_EXOCON_IPEN1_Pos                  13                                                      /*!< ERU EXOCON: IPEN1 Position              */\r
+#define ERU_EXOCON_IPEN1_Msk                  (0x01UL << ERU_EXOCON_IPEN1_Pos)                        /*!< ERU EXOCON: IPEN1 Mask                  */\r
+#define ERU_EXOCON_IPEN2_Pos                  14                                                      /*!< ERU EXOCON: IPEN2 Position              */\r
+#define ERU_EXOCON_IPEN2_Msk                  (0x01UL << ERU_EXOCON_IPEN2_Pos)                        /*!< ERU EXOCON: IPEN2 Mask                  */\r
+#define ERU_EXOCON_IPEN3_Pos                  15                                                      /*!< ERU EXOCON: IPEN3 Position              */\r
+#define ERU_EXOCON_IPEN3_Msk                  (0x01UL << ERU_EXOCON_IPEN3_Pos)                        /*!< ERU EXOCON: IPEN3 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'GPDMA0' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  GPDMA0_RAWTFR  ------------------------------- */\r
+#define GPDMA0_RAWTFR_CH0_Pos                 0                                                       /*!< GPDMA0 RAWTFR: CH0 Position             */\r
+#define GPDMA0_RAWTFR_CH0_Msk                 (0x01UL << GPDMA0_RAWTFR_CH0_Pos)                       /*!< GPDMA0 RAWTFR: CH0 Mask                 */\r
+#define GPDMA0_RAWTFR_CH1_Pos                 1                                                       /*!< GPDMA0 RAWTFR: CH1 Position             */\r
+#define GPDMA0_RAWTFR_CH1_Msk                 (0x01UL << GPDMA0_RAWTFR_CH1_Pos)                       /*!< GPDMA0 RAWTFR: CH1 Mask                 */\r
+#define GPDMA0_RAWTFR_CH2_Pos                 2                                                       /*!< GPDMA0 RAWTFR: CH2 Position             */\r
+#define GPDMA0_RAWTFR_CH2_Msk                 (0x01UL << GPDMA0_RAWTFR_CH2_Pos)                       /*!< GPDMA0 RAWTFR: CH2 Mask                 */\r
+#define GPDMA0_RAWTFR_CH3_Pos                 3                                                       /*!< GPDMA0 RAWTFR: CH3 Position             */\r
+#define GPDMA0_RAWTFR_CH3_Msk                 (0x01UL << GPDMA0_RAWTFR_CH3_Pos)                       /*!< GPDMA0 RAWTFR: CH3 Mask                 */\r
+#define GPDMA0_RAWTFR_CH4_Pos                 4                                                       /*!< GPDMA0 RAWTFR: CH4 Position             */\r
+#define GPDMA0_RAWTFR_CH4_Msk                 (0x01UL << GPDMA0_RAWTFR_CH4_Pos)                       /*!< GPDMA0 RAWTFR: CH4 Mask                 */\r
+#define GPDMA0_RAWTFR_CH5_Pos                 5                                                       /*!< GPDMA0 RAWTFR: CH5 Position             */\r
+#define GPDMA0_RAWTFR_CH5_Msk                 (0x01UL << GPDMA0_RAWTFR_CH5_Pos)                       /*!< GPDMA0 RAWTFR: CH5 Mask                 */\r
+#define GPDMA0_RAWTFR_CH6_Pos                 6                                                       /*!< GPDMA0 RAWTFR: CH6 Position             */\r
+#define GPDMA0_RAWTFR_CH6_Msk                 (0x01UL << GPDMA0_RAWTFR_CH6_Pos)                       /*!< GPDMA0 RAWTFR: CH6 Mask                 */\r
+#define GPDMA0_RAWTFR_CH7_Pos                 7                                                       /*!< GPDMA0 RAWTFR: CH7 Position             */\r
+#define GPDMA0_RAWTFR_CH7_Msk                 (0x01UL << GPDMA0_RAWTFR_CH7_Pos)                       /*!< GPDMA0 RAWTFR: CH7 Mask                 */\r
+\r
+/* -------------------------------  GPDMA0_RAWBLOCK  ------------------------------ */\r
+#define GPDMA0_RAWBLOCK_CH0_Pos               0                                                       /*!< GPDMA0 RAWBLOCK: CH0 Position           */\r
+#define GPDMA0_RAWBLOCK_CH0_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH0_Pos)                     /*!< GPDMA0 RAWBLOCK: CH0 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH1_Pos               1                                                       /*!< GPDMA0 RAWBLOCK: CH1 Position           */\r
+#define GPDMA0_RAWBLOCK_CH1_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH1_Pos)                     /*!< GPDMA0 RAWBLOCK: CH1 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH2_Pos               2                                                       /*!< GPDMA0 RAWBLOCK: CH2 Position           */\r
+#define GPDMA0_RAWBLOCK_CH2_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH2_Pos)                     /*!< GPDMA0 RAWBLOCK: CH2 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH3_Pos               3                                                       /*!< GPDMA0 RAWBLOCK: CH3 Position           */\r
+#define GPDMA0_RAWBLOCK_CH3_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH3_Pos)                     /*!< GPDMA0 RAWBLOCK: CH3 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH4_Pos               4                                                       /*!< GPDMA0 RAWBLOCK: CH4 Position           */\r
+#define GPDMA0_RAWBLOCK_CH4_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH4_Pos)                     /*!< GPDMA0 RAWBLOCK: CH4 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH5_Pos               5                                                       /*!< GPDMA0 RAWBLOCK: CH5 Position           */\r
+#define GPDMA0_RAWBLOCK_CH5_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH5_Pos)                     /*!< GPDMA0 RAWBLOCK: CH5 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH6_Pos               6                                                       /*!< GPDMA0 RAWBLOCK: CH6 Position           */\r
+#define GPDMA0_RAWBLOCK_CH6_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH6_Pos)                     /*!< GPDMA0 RAWBLOCK: CH6 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH7_Pos               7                                                       /*!< GPDMA0 RAWBLOCK: CH7 Position           */\r
+#define GPDMA0_RAWBLOCK_CH7_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH7_Pos)                     /*!< GPDMA0 RAWBLOCK: CH7 Mask               */\r
+\r
+/* ------------------------------  GPDMA0_RAWSRCTRAN  ----------------------------- */\r
+#define GPDMA0_RAWSRCTRAN_CH0_Pos             0                                                       /*!< GPDMA0 RAWSRCTRAN: CH0 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH0_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH0_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH0 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH1_Pos             1                                                       /*!< GPDMA0 RAWSRCTRAN: CH1 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH1_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH1_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH1 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH2_Pos             2                                                       /*!< GPDMA0 RAWSRCTRAN: CH2 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH2_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH2_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH2 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH3_Pos             3                                                       /*!< GPDMA0 RAWSRCTRAN: CH3 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH3_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH3_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH3 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH4_Pos             4                                                       /*!< GPDMA0 RAWSRCTRAN: CH4 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH4_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH4_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH4 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH5_Pos             5                                                       /*!< GPDMA0 RAWSRCTRAN: CH5 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH5_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH5_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH5 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH6_Pos             6                                                       /*!< GPDMA0 RAWSRCTRAN: CH6 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH6_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH6_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH6 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH7_Pos             7                                                       /*!< GPDMA0 RAWSRCTRAN: CH7 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH7_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH7_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH7 Mask             */\r
+\r
+/* ------------------------------  GPDMA0_RAWDSTTRAN  ----------------------------- */\r
+#define GPDMA0_RAWDSTTRAN_CH0_Pos             0                                                       /*!< GPDMA0 RAWDSTTRAN: CH0 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH0_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH0_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH0 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH1_Pos             1                                                       /*!< GPDMA0 RAWDSTTRAN: CH1 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH1_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH1_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH1 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH2_Pos             2                                                       /*!< GPDMA0 RAWDSTTRAN: CH2 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH2_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH2_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH2 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH3_Pos             3                                                       /*!< GPDMA0 RAWDSTTRAN: CH3 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH3_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH3_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH3 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH4_Pos             4                                                       /*!< GPDMA0 RAWDSTTRAN: CH4 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH4_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH4_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH4 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH5_Pos             5                                                       /*!< GPDMA0 RAWDSTTRAN: CH5 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH5_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH5_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH5 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH6_Pos             6                                                       /*!< GPDMA0 RAWDSTTRAN: CH6 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH6_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH6_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH6 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH7_Pos             7                                                       /*!< GPDMA0 RAWDSTTRAN: CH7 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH7_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH7_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH7 Mask             */\r
+\r
+/* --------------------------------  GPDMA0_RAWERR  ------------------------------- */\r
+#define GPDMA0_RAWERR_CH0_Pos                 0                                                       /*!< GPDMA0 RAWERR: CH0 Position             */\r
+#define GPDMA0_RAWERR_CH0_Msk                 (0x01UL << GPDMA0_RAWERR_CH0_Pos)                       /*!< GPDMA0 RAWERR: CH0 Mask                 */\r
+#define GPDMA0_RAWERR_CH1_Pos                 1                                                       /*!< GPDMA0 RAWERR: CH1 Position             */\r
+#define GPDMA0_RAWERR_CH1_Msk                 (0x01UL << GPDMA0_RAWERR_CH1_Pos)                       /*!< GPDMA0 RAWERR: CH1 Mask                 */\r
+#define GPDMA0_RAWERR_CH2_Pos                 2                                                       /*!< GPDMA0 RAWERR: CH2 Position             */\r
+#define GPDMA0_RAWERR_CH2_Msk                 (0x01UL << GPDMA0_RAWERR_CH2_Pos)                       /*!< GPDMA0 RAWERR: CH2 Mask                 */\r
+#define GPDMA0_RAWERR_CH3_Pos                 3                                                       /*!< GPDMA0 RAWERR: CH3 Position             */\r
+#define GPDMA0_RAWERR_CH3_Msk                 (0x01UL << GPDMA0_RAWERR_CH3_Pos)                       /*!< GPDMA0 RAWERR: CH3 Mask                 */\r
+#define GPDMA0_RAWERR_CH4_Pos                 4                                                       /*!< GPDMA0 RAWERR: CH4 Position             */\r
+#define GPDMA0_RAWERR_CH4_Msk                 (0x01UL << GPDMA0_RAWERR_CH4_Pos)                       /*!< GPDMA0 RAWERR: CH4 Mask                 */\r
+#define GPDMA0_RAWERR_CH5_Pos                 5                                                       /*!< GPDMA0 RAWERR: CH5 Position             */\r
+#define GPDMA0_RAWERR_CH5_Msk                 (0x01UL << GPDMA0_RAWERR_CH5_Pos)                       /*!< GPDMA0 RAWERR: CH5 Mask                 */\r
+#define GPDMA0_RAWERR_CH6_Pos                 6                                                       /*!< GPDMA0 RAWERR: CH6 Position             */\r
+#define GPDMA0_RAWERR_CH6_Msk                 (0x01UL << GPDMA0_RAWERR_CH6_Pos)                       /*!< GPDMA0 RAWERR: CH6 Mask                 */\r
+#define GPDMA0_RAWERR_CH7_Pos                 7                                                       /*!< GPDMA0 RAWERR: CH7 Position             */\r
+#define GPDMA0_RAWERR_CH7_Msk                 (0x01UL << GPDMA0_RAWERR_CH7_Pos)                       /*!< GPDMA0 RAWERR: CH7 Mask                 */\r
+\r
+/* ------------------------------  GPDMA0_STATUSTFR  ------------------------------ */\r
+#define GPDMA0_STATUSTFR_CH0_Pos              0                                                       /*!< GPDMA0 STATUSTFR: CH0 Position          */\r
+#define GPDMA0_STATUSTFR_CH0_Msk              (0x01UL << GPDMA0_STATUSTFR_CH0_Pos)                    /*!< GPDMA0 STATUSTFR: CH0 Mask              */\r
+#define GPDMA0_STATUSTFR_CH1_Pos              1                                                       /*!< GPDMA0 STATUSTFR: CH1 Position          */\r
+#define GPDMA0_STATUSTFR_CH1_Msk              (0x01UL << GPDMA0_STATUSTFR_CH1_Pos)                    /*!< GPDMA0 STATUSTFR: CH1 Mask              */\r
+#define GPDMA0_STATUSTFR_CH2_Pos              2                                                       /*!< GPDMA0 STATUSTFR: CH2 Position          */\r
+#define GPDMA0_STATUSTFR_CH2_Msk              (0x01UL << GPDMA0_STATUSTFR_CH2_Pos)                    /*!< GPDMA0 STATUSTFR: CH2 Mask              */\r
+#define GPDMA0_STATUSTFR_CH3_Pos              3                                                       /*!< GPDMA0 STATUSTFR: CH3 Position          */\r
+#define GPDMA0_STATUSTFR_CH3_Msk              (0x01UL << GPDMA0_STATUSTFR_CH3_Pos)                    /*!< GPDMA0 STATUSTFR: CH3 Mask              */\r
+#define GPDMA0_STATUSTFR_CH4_Pos              4                                                       /*!< GPDMA0 STATUSTFR: CH4 Position          */\r
+#define GPDMA0_STATUSTFR_CH4_Msk              (0x01UL << GPDMA0_STATUSTFR_CH4_Pos)                    /*!< GPDMA0 STATUSTFR: CH4 Mask              */\r
+#define GPDMA0_STATUSTFR_CH5_Pos              5                                                       /*!< GPDMA0 STATUSTFR: CH5 Position          */\r
+#define GPDMA0_STATUSTFR_CH5_Msk              (0x01UL << GPDMA0_STATUSTFR_CH5_Pos)                    /*!< GPDMA0 STATUSTFR: CH5 Mask              */\r
+#define GPDMA0_STATUSTFR_CH6_Pos              6                                                       /*!< GPDMA0 STATUSTFR: CH6 Position          */\r
+#define GPDMA0_STATUSTFR_CH6_Msk              (0x01UL << GPDMA0_STATUSTFR_CH6_Pos)                    /*!< GPDMA0 STATUSTFR: CH6 Mask              */\r
+#define GPDMA0_STATUSTFR_CH7_Pos              7                                                       /*!< GPDMA0 STATUSTFR: CH7 Position          */\r
+#define GPDMA0_STATUSTFR_CH7_Msk              (0x01UL << GPDMA0_STATUSTFR_CH7_Pos)                    /*!< GPDMA0 STATUSTFR: CH7 Mask              */\r
+\r
+/* -----------------------------  GPDMA0_STATUSBLOCK  ----------------------------- */\r
+#define GPDMA0_STATUSBLOCK_CH0_Pos            0                                                       /*!< GPDMA0 STATUSBLOCK: CH0 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH0_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH0_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH0 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH1_Pos            1                                                       /*!< GPDMA0 STATUSBLOCK: CH1 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH1_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH1_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH1 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH2_Pos            2                                                       /*!< GPDMA0 STATUSBLOCK: CH2 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH2_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH2_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH2 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH3_Pos            3                                                       /*!< GPDMA0 STATUSBLOCK: CH3 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH3_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH3_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH3 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH4_Pos            4                                                       /*!< GPDMA0 STATUSBLOCK: CH4 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH4_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH4_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH4 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH5_Pos            5                                                       /*!< GPDMA0 STATUSBLOCK: CH5 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH5_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH5_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH5 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH6_Pos            6                                                       /*!< GPDMA0 STATUSBLOCK: CH6 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH6_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH6_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH6 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH7_Pos            7                                                       /*!< GPDMA0 STATUSBLOCK: CH7 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH7_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH7_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH7 Mask            */\r
+\r
+/* ----------------------------  GPDMA0_STATUSSRCTRAN  ---------------------------- */\r
+#define GPDMA0_STATUSSRCTRAN_CH0_Pos          0                                                       /*!< GPDMA0 STATUSSRCTRAN: CH0 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH0_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH0_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH0 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH1_Pos          1                                                       /*!< GPDMA0 STATUSSRCTRAN: CH1 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH1_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH1_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH1 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH2_Pos          2                                                       /*!< GPDMA0 STATUSSRCTRAN: CH2 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH2_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH2_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH2 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH3_Pos          3                                                       /*!< GPDMA0 STATUSSRCTRAN: CH3 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH3_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH3_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH3 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH4_Pos          4                                                       /*!< GPDMA0 STATUSSRCTRAN: CH4 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH4_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH4_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH4 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH5_Pos          5                                                       /*!< GPDMA0 STATUSSRCTRAN: CH5 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH5_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH5_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH5 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH6_Pos          6                                                       /*!< GPDMA0 STATUSSRCTRAN: CH6 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH6_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH6_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH6 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH7_Pos          7                                                       /*!< GPDMA0 STATUSSRCTRAN: CH7 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH7_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH7_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH7 Mask          */\r
+\r
+/* ----------------------------  GPDMA0_STATUSDSTTRAN  ---------------------------- */\r
+#define GPDMA0_STATUSDSTTRAN_CH0_Pos          0                                                       /*!< GPDMA0 STATUSDSTTRAN: CH0 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH0_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH0_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH0 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH1_Pos          1                                                       /*!< GPDMA0 STATUSDSTTRAN: CH1 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH1_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH1_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH1 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH2_Pos          2                                                       /*!< GPDMA0 STATUSDSTTRAN: CH2 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH2_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH2_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH2 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH3_Pos          3                                                       /*!< GPDMA0 STATUSDSTTRAN: CH3 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH3_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH3_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH3 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH4_Pos          4                                                       /*!< GPDMA0 STATUSDSTTRAN: CH4 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH4_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH4_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH4 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH5_Pos          5                                                       /*!< GPDMA0 STATUSDSTTRAN: CH5 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH5_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH5_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH5 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH6_Pos          6                                                       /*!< GPDMA0 STATUSDSTTRAN: CH6 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH6_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH6_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH6 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH7_Pos          7                                                       /*!< GPDMA0 STATUSDSTTRAN: CH7 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH7_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH7_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH7 Mask          */\r
+\r
+/* ------------------------------  GPDMA0_STATUSERR  ------------------------------ */\r
+#define GPDMA0_STATUSERR_CH0_Pos              0                                                       /*!< GPDMA0 STATUSERR: CH0 Position          */\r
+#define GPDMA0_STATUSERR_CH0_Msk              (0x01UL << GPDMA0_STATUSERR_CH0_Pos)                    /*!< GPDMA0 STATUSERR: CH0 Mask              */\r
+#define GPDMA0_STATUSERR_CH1_Pos              1                                                       /*!< GPDMA0 STATUSERR: CH1 Position          */\r
+#define GPDMA0_STATUSERR_CH1_Msk              (0x01UL << GPDMA0_STATUSERR_CH1_Pos)                    /*!< GPDMA0 STATUSERR: CH1 Mask              */\r
+#define GPDMA0_STATUSERR_CH2_Pos              2                                                       /*!< GPDMA0 STATUSERR: CH2 Position          */\r
+#define GPDMA0_STATUSERR_CH2_Msk              (0x01UL << GPDMA0_STATUSERR_CH2_Pos)                    /*!< GPDMA0 STATUSERR: CH2 Mask              */\r
+#define GPDMA0_STATUSERR_CH3_Pos              3                                                       /*!< GPDMA0 STATUSERR: CH3 Position          */\r
+#define GPDMA0_STATUSERR_CH3_Msk              (0x01UL << GPDMA0_STATUSERR_CH3_Pos)                    /*!< GPDMA0 STATUSERR: CH3 Mask              */\r
+#define GPDMA0_STATUSERR_CH4_Pos              4                                                       /*!< GPDMA0 STATUSERR: CH4 Position          */\r
+#define GPDMA0_STATUSERR_CH4_Msk              (0x01UL << GPDMA0_STATUSERR_CH4_Pos)                    /*!< GPDMA0 STATUSERR: CH4 Mask              */\r
+#define GPDMA0_STATUSERR_CH5_Pos              5                                                       /*!< GPDMA0 STATUSERR: CH5 Position          */\r
+#define GPDMA0_STATUSERR_CH5_Msk              (0x01UL << GPDMA0_STATUSERR_CH5_Pos)                    /*!< GPDMA0 STATUSERR: CH5 Mask              */\r
+#define GPDMA0_STATUSERR_CH6_Pos              6                                                       /*!< GPDMA0 STATUSERR: CH6 Position          */\r
+#define GPDMA0_STATUSERR_CH6_Msk              (0x01UL << GPDMA0_STATUSERR_CH6_Pos)                    /*!< GPDMA0 STATUSERR: CH6 Mask              */\r
+#define GPDMA0_STATUSERR_CH7_Pos              7                                                       /*!< GPDMA0 STATUSERR: CH7 Position          */\r
+#define GPDMA0_STATUSERR_CH7_Msk              (0x01UL << GPDMA0_STATUSERR_CH7_Pos)                    /*!< GPDMA0 STATUSERR: CH7 Mask              */\r
+\r
+/* -------------------------------  GPDMA0_MASKTFR  ------------------------------- */\r
+#define GPDMA0_MASKTFR_CH0_Pos                0                                                       /*!< GPDMA0 MASKTFR: CH0 Position            */\r
+#define GPDMA0_MASKTFR_CH0_Msk                (0x01UL << GPDMA0_MASKTFR_CH0_Pos)                      /*!< GPDMA0 MASKTFR: CH0 Mask                */\r
+#define GPDMA0_MASKTFR_CH1_Pos                1                                                       /*!< GPDMA0 MASKTFR: CH1 Position            */\r
+#define GPDMA0_MASKTFR_CH1_Msk                (0x01UL << GPDMA0_MASKTFR_CH1_Pos)                      /*!< GPDMA0 MASKTFR: CH1 Mask                */\r
+#define GPDMA0_MASKTFR_CH2_Pos                2                                                       /*!< GPDMA0 MASKTFR: CH2 Position            */\r
+#define GPDMA0_MASKTFR_CH2_Msk                (0x01UL << GPDMA0_MASKTFR_CH2_Pos)                      /*!< GPDMA0 MASKTFR: CH2 Mask                */\r
+#define GPDMA0_MASKTFR_CH3_Pos                3                                                       /*!< GPDMA0 MASKTFR: CH3 Position            */\r
+#define GPDMA0_MASKTFR_CH3_Msk                (0x01UL << GPDMA0_MASKTFR_CH3_Pos)                      /*!< GPDMA0 MASKTFR: CH3 Mask                */\r
+#define GPDMA0_MASKTFR_CH4_Pos                4                                                       /*!< GPDMA0 MASKTFR: CH4 Position            */\r
+#define GPDMA0_MASKTFR_CH4_Msk                (0x01UL << GPDMA0_MASKTFR_CH4_Pos)                      /*!< GPDMA0 MASKTFR: CH4 Mask                */\r
+#define GPDMA0_MASKTFR_CH5_Pos                5                                                       /*!< GPDMA0 MASKTFR: CH5 Position            */\r
+#define GPDMA0_MASKTFR_CH5_Msk                (0x01UL << GPDMA0_MASKTFR_CH5_Pos)                      /*!< GPDMA0 MASKTFR: CH5 Mask                */\r
+#define GPDMA0_MASKTFR_CH6_Pos                6                                                       /*!< GPDMA0 MASKTFR: CH6 Position            */\r
+#define GPDMA0_MASKTFR_CH6_Msk                (0x01UL << GPDMA0_MASKTFR_CH6_Pos)                      /*!< GPDMA0 MASKTFR: CH6 Mask                */\r
+#define GPDMA0_MASKTFR_CH7_Pos                7                                                       /*!< GPDMA0 MASKTFR: CH7 Position            */\r
+#define GPDMA0_MASKTFR_CH7_Msk                (0x01UL << GPDMA0_MASKTFR_CH7_Pos)                      /*!< GPDMA0 MASKTFR: CH7 Mask                */\r
+#define GPDMA0_MASKTFR_WE_CH0_Pos             8                                                       /*!< GPDMA0 MASKTFR: WE_CH0 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH0_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH0_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH0 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH1_Pos             9                                                       /*!< GPDMA0 MASKTFR: WE_CH1 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH1_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH1_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH1 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH2_Pos             10                                                      /*!< GPDMA0 MASKTFR: WE_CH2 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH2_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH2_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH2 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH3_Pos             11                                                      /*!< GPDMA0 MASKTFR: WE_CH3 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH3_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH3_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH3 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH4_Pos             12                                                      /*!< GPDMA0 MASKTFR: WE_CH4 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH4_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH4_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH4 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH5_Pos             13                                                      /*!< GPDMA0 MASKTFR: WE_CH5 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH5_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH5_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH5 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH6_Pos             14                                                      /*!< GPDMA0 MASKTFR: WE_CH6 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH6_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH6_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH6 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH7_Pos             15                                                      /*!< GPDMA0 MASKTFR: WE_CH7 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH7_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH7_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH7 Mask             */\r
+\r
+/* ------------------------------  GPDMA0_MASKBLOCK  ------------------------------ */\r
+#define GPDMA0_MASKBLOCK_CH0_Pos              0                                                       /*!< GPDMA0 MASKBLOCK: CH0 Position          */\r
+#define GPDMA0_MASKBLOCK_CH0_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH0_Pos)                    /*!< GPDMA0 MASKBLOCK: CH0 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH1_Pos              1                                                       /*!< GPDMA0 MASKBLOCK: CH1 Position          */\r
+#define GPDMA0_MASKBLOCK_CH1_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH1_Pos)                    /*!< GPDMA0 MASKBLOCK: CH1 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH2_Pos              2                                                       /*!< GPDMA0 MASKBLOCK: CH2 Position          */\r
+#define GPDMA0_MASKBLOCK_CH2_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH2_Pos)                    /*!< GPDMA0 MASKBLOCK: CH2 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH3_Pos              3                                                       /*!< GPDMA0 MASKBLOCK: CH3 Position          */\r
+#define GPDMA0_MASKBLOCK_CH3_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH3_Pos)                    /*!< GPDMA0 MASKBLOCK: CH3 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH4_Pos              4                                                       /*!< GPDMA0 MASKBLOCK: CH4 Position          */\r
+#define GPDMA0_MASKBLOCK_CH4_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH4_Pos)                    /*!< GPDMA0 MASKBLOCK: CH4 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH5_Pos              5                                                       /*!< GPDMA0 MASKBLOCK: CH5 Position          */\r
+#define GPDMA0_MASKBLOCK_CH5_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH5_Pos)                    /*!< GPDMA0 MASKBLOCK: CH5 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH6_Pos              6                                                       /*!< GPDMA0 MASKBLOCK: CH6 Position          */\r
+#define GPDMA0_MASKBLOCK_CH6_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH6_Pos)                    /*!< GPDMA0 MASKBLOCK: CH6 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH7_Pos              7                                                       /*!< GPDMA0 MASKBLOCK: CH7 Position          */\r
+#define GPDMA0_MASKBLOCK_CH7_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH7_Pos)                    /*!< GPDMA0 MASKBLOCK: CH7 Mask              */\r
+#define GPDMA0_MASKBLOCK_WE_CH0_Pos           8                                                       /*!< GPDMA0 MASKBLOCK: WE_CH0 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH0_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH0_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH0 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH1_Pos           9                                                       /*!< GPDMA0 MASKBLOCK: WE_CH1 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH1_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH1_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH1 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH2_Pos           10                                                      /*!< GPDMA0 MASKBLOCK: WE_CH2 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH2_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH2_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH2 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH3_Pos           11                                                      /*!< GPDMA0 MASKBLOCK: WE_CH3 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH3_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH3_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH3 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH4_Pos           12                                                      /*!< GPDMA0 MASKBLOCK: WE_CH4 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH4_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH4_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH4 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH5_Pos           13                                                      /*!< GPDMA0 MASKBLOCK: WE_CH5 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH5_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH5_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH5 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH6_Pos           14                                                      /*!< GPDMA0 MASKBLOCK: WE_CH6 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH6_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH6_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH6 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH7_Pos           15                                                      /*!< GPDMA0 MASKBLOCK: WE_CH7 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH7_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH7_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH7 Mask           */\r
+\r
+/* -----------------------------  GPDMA0_MASKSRCTRAN  ----------------------------- */\r
+#define GPDMA0_MASKSRCTRAN_CH0_Pos            0                                                       /*!< GPDMA0 MASKSRCTRAN: CH0 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH0_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH0_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH0 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH1_Pos            1                                                       /*!< GPDMA0 MASKSRCTRAN: CH1 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH1_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH1_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH1 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH2_Pos            2                                                       /*!< GPDMA0 MASKSRCTRAN: CH2 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH2_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH2_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH2 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH3_Pos            3                                                       /*!< GPDMA0 MASKSRCTRAN: CH3 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH3_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH3_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH3 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH4_Pos            4                                                       /*!< GPDMA0 MASKSRCTRAN: CH4 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH4_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH4_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH4 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH5_Pos            5                                                       /*!< GPDMA0 MASKSRCTRAN: CH5 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH5_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH5_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH5 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH6_Pos            6                                                       /*!< GPDMA0 MASKSRCTRAN: CH6 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH6_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH6_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH6 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH7_Pos            7                                                       /*!< GPDMA0 MASKSRCTRAN: CH7 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH7_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH7_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH7 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH0_Pos         8                                                       /*!< GPDMA0 MASKSRCTRAN: WE_CH0 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH0_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH0_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH0 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH1_Pos         9                                                       /*!< GPDMA0 MASKSRCTRAN: WE_CH1 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH1_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH1_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH1 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH2_Pos         10                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH2 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH2_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH2_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH2 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH3_Pos         11                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH3 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH3_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH3_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH3 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH4_Pos         12                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH4 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH4_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH4_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH4 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH5_Pos         13                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH5 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH5_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH5_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH5 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH6_Pos         14                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH6 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH6_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH6_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH6 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH7_Pos         15                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH7 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH7_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH7_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH7 Mask         */\r
+\r
+/* -----------------------------  GPDMA0_MASKDSTTRAN  ----------------------------- */\r
+#define GPDMA0_MASKDSTTRAN_CH0_Pos            0                                                       /*!< GPDMA0 MASKDSTTRAN: CH0 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH0_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH0_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH0 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH1_Pos            1                                                       /*!< GPDMA0 MASKDSTTRAN: CH1 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH1_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH1_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH1 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH2_Pos            2                                                       /*!< GPDMA0 MASKDSTTRAN: CH2 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH2_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH2_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH2 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH3_Pos            3                                                       /*!< GPDMA0 MASKDSTTRAN: CH3 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH3_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH3_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH3 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH4_Pos            4                                                       /*!< GPDMA0 MASKDSTTRAN: CH4 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH4_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH4_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH4 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH5_Pos            5                                                       /*!< GPDMA0 MASKDSTTRAN: CH5 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH5_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH5_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH5 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH6_Pos            6                                                       /*!< GPDMA0 MASKDSTTRAN: CH6 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH6_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH6_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH6 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH7_Pos            7                                                       /*!< GPDMA0 MASKDSTTRAN: CH7 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH7_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH7_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH7 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH0_Pos         8                                                       /*!< GPDMA0 MASKDSTTRAN: WE_CH0 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH0_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH0_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH0 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH1_Pos         9                                                       /*!< GPDMA0 MASKDSTTRAN: WE_CH1 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH1_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH1_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH1 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH2_Pos         10                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH2 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH2_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH2_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH2 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH3_Pos         11                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH3 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH3_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH3_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH3 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH4_Pos         12                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH4 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH4_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH4_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH4 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH5_Pos         13                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH5 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH5_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH5_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH5 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH6_Pos         14                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH6 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH6_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH6_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH6 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH7_Pos         15                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH7 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH7_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH7_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH7 Mask         */\r
+\r
+/* -------------------------------  GPDMA0_MASKERR  ------------------------------- */\r
+#define GPDMA0_MASKERR_CH0_Pos                0                                                       /*!< GPDMA0 MASKERR: CH0 Position            */\r
+#define GPDMA0_MASKERR_CH0_Msk                (0x01UL << GPDMA0_MASKERR_CH0_Pos)                      /*!< GPDMA0 MASKERR: CH0 Mask                */\r
+#define GPDMA0_MASKERR_CH1_Pos                1                                                       /*!< GPDMA0 MASKERR: CH1 Position            */\r
+#define GPDMA0_MASKERR_CH1_Msk                (0x01UL << GPDMA0_MASKERR_CH1_Pos)                      /*!< GPDMA0 MASKERR: CH1 Mask                */\r
+#define GPDMA0_MASKERR_CH2_Pos                2                                                       /*!< GPDMA0 MASKERR: CH2 Position            */\r
+#define GPDMA0_MASKERR_CH2_Msk                (0x01UL << GPDMA0_MASKERR_CH2_Pos)                      /*!< GPDMA0 MASKERR: CH2 Mask                */\r
+#define GPDMA0_MASKERR_CH3_Pos                3                                                       /*!< GPDMA0 MASKERR: CH3 Position            */\r
+#define GPDMA0_MASKERR_CH3_Msk                (0x01UL << GPDMA0_MASKERR_CH3_Pos)                      /*!< GPDMA0 MASKERR: CH3 Mask                */\r
+#define GPDMA0_MASKERR_CH4_Pos                4                                                       /*!< GPDMA0 MASKERR: CH4 Position            */\r
+#define GPDMA0_MASKERR_CH4_Msk                (0x01UL << GPDMA0_MASKERR_CH4_Pos)                      /*!< GPDMA0 MASKERR: CH4 Mask                */\r
+#define GPDMA0_MASKERR_CH5_Pos                5                                                       /*!< GPDMA0 MASKERR: CH5 Position            */\r
+#define GPDMA0_MASKERR_CH5_Msk                (0x01UL << GPDMA0_MASKERR_CH5_Pos)                      /*!< GPDMA0 MASKERR: CH5 Mask                */\r
+#define GPDMA0_MASKERR_CH6_Pos                6                                                       /*!< GPDMA0 MASKERR: CH6 Position            */\r
+#define GPDMA0_MASKERR_CH6_Msk                (0x01UL << GPDMA0_MASKERR_CH6_Pos)                      /*!< GPDMA0 MASKERR: CH6 Mask                */\r
+#define GPDMA0_MASKERR_CH7_Pos                7                                                       /*!< GPDMA0 MASKERR: CH7 Position            */\r
+#define GPDMA0_MASKERR_CH7_Msk                (0x01UL << GPDMA0_MASKERR_CH7_Pos)                      /*!< GPDMA0 MASKERR: CH7 Mask                */\r
+#define GPDMA0_MASKERR_WE_CH0_Pos             8                                                       /*!< GPDMA0 MASKERR: WE_CH0 Position         */\r
+#define GPDMA0_MASKERR_WE_CH0_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH0_Pos)                   /*!< GPDMA0 MASKERR: WE_CH0 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH1_Pos             9                                                       /*!< GPDMA0 MASKERR: WE_CH1 Position         */\r
+#define GPDMA0_MASKERR_WE_CH1_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH1_Pos)                   /*!< GPDMA0 MASKERR: WE_CH1 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH2_Pos             10                                                      /*!< GPDMA0 MASKERR: WE_CH2 Position         */\r
+#define GPDMA0_MASKERR_WE_CH2_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH2_Pos)                   /*!< GPDMA0 MASKERR: WE_CH2 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH3_Pos             11                                                      /*!< GPDMA0 MASKERR: WE_CH3 Position         */\r
+#define GPDMA0_MASKERR_WE_CH3_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH3_Pos)                   /*!< GPDMA0 MASKERR: WE_CH3 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH4_Pos             12                                                      /*!< GPDMA0 MASKERR: WE_CH4 Position         */\r
+#define GPDMA0_MASKERR_WE_CH4_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH4_Pos)                   /*!< GPDMA0 MASKERR: WE_CH4 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH5_Pos             13                                                      /*!< GPDMA0 MASKERR: WE_CH5 Position         */\r
+#define GPDMA0_MASKERR_WE_CH5_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH5_Pos)                   /*!< GPDMA0 MASKERR: WE_CH5 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH6_Pos             14                                                      /*!< GPDMA0 MASKERR: WE_CH6 Position         */\r
+#define GPDMA0_MASKERR_WE_CH6_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH6_Pos)                   /*!< GPDMA0 MASKERR: WE_CH6 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH7_Pos             15                                                      /*!< GPDMA0 MASKERR: WE_CH7 Position         */\r
+#define GPDMA0_MASKERR_WE_CH7_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH7_Pos)                   /*!< GPDMA0 MASKERR: WE_CH7 Mask             */\r
+\r
+/* -------------------------------  GPDMA0_CLEARTFR  ------------------------------ */\r
+#define GPDMA0_CLEARTFR_CH0_Pos               0                                                       /*!< GPDMA0 CLEARTFR: CH0 Position           */\r
+#define GPDMA0_CLEARTFR_CH0_Msk               (0x01UL << GPDMA0_CLEARTFR_CH0_Pos)                     /*!< GPDMA0 CLEARTFR: CH0 Mask               */\r
+#define GPDMA0_CLEARTFR_CH1_Pos               1                                                       /*!< GPDMA0 CLEARTFR: CH1 Position           */\r
+#define GPDMA0_CLEARTFR_CH1_Msk               (0x01UL << GPDMA0_CLEARTFR_CH1_Pos)                     /*!< GPDMA0 CLEARTFR: CH1 Mask               */\r
+#define GPDMA0_CLEARTFR_CH2_Pos               2                                                       /*!< GPDMA0 CLEARTFR: CH2 Position           */\r
+#define GPDMA0_CLEARTFR_CH2_Msk               (0x01UL << GPDMA0_CLEARTFR_CH2_Pos)                     /*!< GPDMA0 CLEARTFR: CH2 Mask               */\r
+#define GPDMA0_CLEARTFR_CH3_Pos               3                                                       /*!< GPDMA0 CLEARTFR: CH3 Position           */\r
+#define GPDMA0_CLEARTFR_CH3_Msk               (0x01UL << GPDMA0_CLEARTFR_CH3_Pos)                     /*!< GPDMA0 CLEARTFR: CH3 Mask               */\r
+#define GPDMA0_CLEARTFR_CH4_Pos               4                                                       /*!< GPDMA0 CLEARTFR: CH4 Position           */\r
+#define GPDMA0_CLEARTFR_CH4_Msk               (0x01UL << GPDMA0_CLEARTFR_CH4_Pos)                     /*!< GPDMA0 CLEARTFR: CH4 Mask               */\r
+#define GPDMA0_CLEARTFR_CH5_Pos               5                                                       /*!< GPDMA0 CLEARTFR: CH5 Position           */\r
+#define GPDMA0_CLEARTFR_CH5_Msk               (0x01UL << GPDMA0_CLEARTFR_CH5_Pos)                     /*!< GPDMA0 CLEARTFR: CH5 Mask               */\r
+#define GPDMA0_CLEARTFR_CH6_Pos               6                                                       /*!< GPDMA0 CLEARTFR: CH6 Position           */\r
+#define GPDMA0_CLEARTFR_CH6_Msk               (0x01UL << GPDMA0_CLEARTFR_CH6_Pos)                     /*!< GPDMA0 CLEARTFR: CH6 Mask               */\r
+#define GPDMA0_CLEARTFR_CH7_Pos               7                                                       /*!< GPDMA0 CLEARTFR: CH7 Position           */\r
+#define GPDMA0_CLEARTFR_CH7_Msk               (0x01UL << GPDMA0_CLEARTFR_CH7_Pos)                     /*!< GPDMA0 CLEARTFR: CH7 Mask               */\r
+\r
+/* ------------------------------  GPDMA0_CLEARBLOCK  ----------------------------- */\r
+#define GPDMA0_CLEARBLOCK_CH0_Pos             0                                                       /*!< GPDMA0 CLEARBLOCK: CH0 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH0_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH0_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH0 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH1_Pos             1                                                       /*!< GPDMA0 CLEARBLOCK: CH1 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH1_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH1_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH1 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH2_Pos             2                                                       /*!< GPDMA0 CLEARBLOCK: CH2 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH2_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH2_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH2 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH3_Pos             3                                                       /*!< GPDMA0 CLEARBLOCK: CH3 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH3_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH3_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH3 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH4_Pos             4                                                       /*!< GPDMA0 CLEARBLOCK: CH4 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH4_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH4_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH4 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH5_Pos             5                                                       /*!< GPDMA0 CLEARBLOCK: CH5 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH5_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH5_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH5 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH6_Pos             6                                                       /*!< GPDMA0 CLEARBLOCK: CH6 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH6_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH6_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH6 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH7_Pos             7                                                       /*!< GPDMA0 CLEARBLOCK: CH7 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH7_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH7_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH7 Mask             */\r
+\r
+/* -----------------------------  GPDMA0_CLEARSRCTRAN  ---------------------------- */\r
+#define GPDMA0_CLEARSRCTRAN_CH0_Pos           0                                                       /*!< GPDMA0 CLEARSRCTRAN: CH0 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH0_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH0_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH0 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH1_Pos           1                                                       /*!< GPDMA0 CLEARSRCTRAN: CH1 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH1_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH1_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH1 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH2_Pos           2                                                       /*!< GPDMA0 CLEARSRCTRAN: CH2 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH2_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH2_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH2 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH3_Pos           3                                                       /*!< GPDMA0 CLEARSRCTRAN: CH3 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH3_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH3_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH3 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH4_Pos           4                                                       /*!< GPDMA0 CLEARSRCTRAN: CH4 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH4_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH4_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH4 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH5_Pos           5                                                       /*!< GPDMA0 CLEARSRCTRAN: CH5 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH5_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH5_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH5 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH6_Pos           6                                                       /*!< GPDMA0 CLEARSRCTRAN: CH6 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH6_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH6_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH6 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH7_Pos           7                                                       /*!< GPDMA0 CLEARSRCTRAN: CH7 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH7_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH7_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH7 Mask           */\r
+\r
+/* -----------------------------  GPDMA0_CLEARDSTTRAN  ---------------------------- */\r
+#define GPDMA0_CLEARDSTTRAN_CH0_Pos           0                                                       /*!< GPDMA0 CLEARDSTTRAN: CH0 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH0_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH0_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH0 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH1_Pos           1                                                       /*!< GPDMA0 CLEARDSTTRAN: CH1 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH1_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH1_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH1 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH2_Pos           2                                                       /*!< GPDMA0 CLEARDSTTRAN: CH2 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH2_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH2_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH2 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH3_Pos           3                                                       /*!< GPDMA0 CLEARDSTTRAN: CH3 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH3_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH3_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH3 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH4_Pos           4                                                       /*!< GPDMA0 CLEARDSTTRAN: CH4 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH4_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH4_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH4 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH5_Pos           5                                                       /*!< GPDMA0 CLEARDSTTRAN: CH5 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH5_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH5_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH5 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH6_Pos           6                                                       /*!< GPDMA0 CLEARDSTTRAN: CH6 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH6_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH6_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH6 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH7_Pos           7                                                       /*!< GPDMA0 CLEARDSTTRAN: CH7 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH7_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH7_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH7 Mask           */\r
+\r
+/* -------------------------------  GPDMA0_CLEARERR  ------------------------------ */\r
+#define GPDMA0_CLEARERR_CH0_Pos               0                                                       /*!< GPDMA0 CLEARERR: CH0 Position           */\r
+#define GPDMA0_CLEARERR_CH0_Msk               (0x01UL << GPDMA0_CLEARERR_CH0_Pos)                     /*!< GPDMA0 CLEARERR: CH0 Mask               */\r
+#define GPDMA0_CLEARERR_CH1_Pos               1                                                       /*!< GPDMA0 CLEARERR: CH1 Position           */\r
+#define GPDMA0_CLEARERR_CH1_Msk               (0x01UL << GPDMA0_CLEARERR_CH1_Pos)                     /*!< GPDMA0 CLEARERR: CH1 Mask               */\r
+#define GPDMA0_CLEARERR_CH2_Pos               2                                                       /*!< GPDMA0 CLEARERR: CH2 Position           */\r
+#define GPDMA0_CLEARERR_CH2_Msk               (0x01UL << GPDMA0_CLEARERR_CH2_Pos)                     /*!< GPDMA0 CLEARERR: CH2 Mask               */\r
+#define GPDMA0_CLEARERR_CH3_Pos               3                                                       /*!< GPDMA0 CLEARERR: CH3 Position           */\r
+#define GPDMA0_CLEARERR_CH3_Msk               (0x01UL << GPDMA0_CLEARERR_CH3_Pos)                     /*!< GPDMA0 CLEARERR: CH3 Mask               */\r
+#define GPDMA0_CLEARERR_CH4_Pos               4                                                       /*!< GPDMA0 CLEARERR: CH4 Position           */\r
+#define GPDMA0_CLEARERR_CH4_Msk               (0x01UL << GPDMA0_CLEARERR_CH4_Pos)                     /*!< GPDMA0 CLEARERR: CH4 Mask               */\r
+#define GPDMA0_CLEARERR_CH5_Pos               5                                                       /*!< GPDMA0 CLEARERR: CH5 Position           */\r
+#define GPDMA0_CLEARERR_CH5_Msk               (0x01UL << GPDMA0_CLEARERR_CH5_Pos)                     /*!< GPDMA0 CLEARERR: CH5 Mask               */\r
+#define GPDMA0_CLEARERR_CH6_Pos               6                                                       /*!< GPDMA0 CLEARERR: CH6 Position           */\r
+#define GPDMA0_CLEARERR_CH6_Msk               (0x01UL << GPDMA0_CLEARERR_CH6_Pos)                     /*!< GPDMA0 CLEARERR: CH6 Mask               */\r
+#define GPDMA0_CLEARERR_CH7_Pos               7                                                       /*!< GPDMA0 CLEARERR: CH7 Position           */\r
+#define GPDMA0_CLEARERR_CH7_Msk               (0x01UL << GPDMA0_CLEARERR_CH7_Pos)                     /*!< GPDMA0 CLEARERR: CH7 Mask               */\r
+\r
+/* ------------------------------  GPDMA0_STATUSINT  ------------------------------ */\r
+#define GPDMA0_STATUSINT_TFR_Pos              0                                                       /*!< GPDMA0 STATUSINT: TFR Position          */\r
+#define GPDMA0_STATUSINT_TFR_Msk              (0x01UL << GPDMA0_STATUSINT_TFR_Pos)                    /*!< GPDMA0 STATUSINT: TFR Mask              */\r
+#define GPDMA0_STATUSINT_BLOCK_Pos            1                                                       /*!< GPDMA0 STATUSINT: BLOCK Position        */\r
+#define GPDMA0_STATUSINT_BLOCK_Msk            (0x01UL << GPDMA0_STATUSINT_BLOCK_Pos)                  /*!< GPDMA0 STATUSINT: BLOCK Mask            */\r
+#define GPDMA0_STATUSINT_SRCT_Pos             2                                                       /*!< GPDMA0 STATUSINT: SRCT Position         */\r
+#define GPDMA0_STATUSINT_SRCT_Msk             (0x01UL << GPDMA0_STATUSINT_SRCT_Pos)                   /*!< GPDMA0 STATUSINT: SRCT Mask             */\r
+#define GPDMA0_STATUSINT_DSTT_Pos             3                                                       /*!< GPDMA0 STATUSINT: DSTT Position         */\r
+#define GPDMA0_STATUSINT_DSTT_Msk             (0x01UL << GPDMA0_STATUSINT_DSTT_Pos)                   /*!< GPDMA0 STATUSINT: DSTT Mask             */\r
+#define GPDMA0_STATUSINT_ERR_Pos              4                                                       /*!< GPDMA0 STATUSINT: ERR Position          */\r
+#define GPDMA0_STATUSINT_ERR_Msk              (0x01UL << GPDMA0_STATUSINT_ERR_Pos)                    /*!< GPDMA0 STATUSINT: ERR Mask              */\r
+\r
+/* ------------------------------  GPDMA0_REQSRCREG  ------------------------------ */\r
+#define GPDMA0_REQSRCREG_CH0_Pos              0                                                       /*!< GPDMA0 REQSRCREG: CH0 Position          */\r
+#define GPDMA0_REQSRCREG_CH0_Msk              (0x01UL << GPDMA0_REQSRCREG_CH0_Pos)                    /*!< GPDMA0 REQSRCREG: CH0 Mask              */\r
+#define GPDMA0_REQSRCREG_CH1_Pos              1                                                       /*!< GPDMA0 REQSRCREG: CH1 Position          */\r
+#define GPDMA0_REQSRCREG_CH1_Msk              (0x01UL << GPDMA0_REQSRCREG_CH1_Pos)                    /*!< GPDMA0 REQSRCREG: CH1 Mask              */\r
+#define GPDMA0_REQSRCREG_CH2_Pos              2                                                       /*!< GPDMA0 REQSRCREG: CH2 Position          */\r
+#define GPDMA0_REQSRCREG_CH2_Msk              (0x01UL << GPDMA0_REQSRCREG_CH2_Pos)                    /*!< GPDMA0 REQSRCREG: CH2 Mask              */\r
+#define GPDMA0_REQSRCREG_CH3_Pos              3                                                       /*!< GPDMA0 REQSRCREG: CH3 Position          */\r
+#define GPDMA0_REQSRCREG_CH3_Msk              (0x01UL << GPDMA0_REQSRCREG_CH3_Pos)                    /*!< GPDMA0 REQSRCREG: CH3 Mask              */\r
+#define GPDMA0_REQSRCREG_CH4_Pos              4                                                       /*!< GPDMA0 REQSRCREG: CH4 Position          */\r
+#define GPDMA0_REQSRCREG_CH4_Msk              (0x01UL << GPDMA0_REQSRCREG_CH4_Pos)                    /*!< GPDMA0 REQSRCREG: CH4 Mask              */\r
+#define GPDMA0_REQSRCREG_CH5_Pos              5                                                       /*!< GPDMA0 REQSRCREG: CH5 Position          */\r
+#define GPDMA0_REQSRCREG_CH5_Msk              (0x01UL << GPDMA0_REQSRCREG_CH5_Pos)                    /*!< GPDMA0 REQSRCREG: CH5 Mask              */\r
+#define GPDMA0_REQSRCREG_CH6_Pos              6                                                       /*!< GPDMA0 REQSRCREG: CH6 Position          */\r
+#define GPDMA0_REQSRCREG_CH6_Msk              (0x01UL << GPDMA0_REQSRCREG_CH6_Pos)                    /*!< GPDMA0 REQSRCREG: CH6 Mask              */\r
+#define GPDMA0_REQSRCREG_CH7_Pos              7                                                       /*!< GPDMA0 REQSRCREG: CH7 Position          */\r
+#define GPDMA0_REQSRCREG_CH7_Msk              (0x01UL << GPDMA0_REQSRCREG_CH7_Pos)                    /*!< GPDMA0 REQSRCREG: CH7 Mask              */\r
+#define GPDMA0_REQSRCREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 REQSRCREG: WE_CH0 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH0_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH0_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH0 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 REQSRCREG: WE_CH1 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH1_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH1_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH1 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 REQSRCREG: WE_CH2 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH2_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH2_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH2 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 REQSRCREG: WE_CH3 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH3_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH3_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH3 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 REQSRCREG: WE_CH4 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH4_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH4_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH4 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 REQSRCREG: WE_CH5 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH5_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH5_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH5 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 REQSRCREG: WE_CH6 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH6_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH6_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH6 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 REQSRCREG: WE_CH7 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH7_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH7_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH7 Mask           */\r
+\r
+/* ------------------------------  GPDMA0_REQDSTREG  ------------------------------ */\r
+#define GPDMA0_REQDSTREG_CH0_Pos              0                                                       /*!< GPDMA0 REQDSTREG: CH0 Position          */\r
+#define GPDMA0_REQDSTREG_CH0_Msk              (0x01UL << GPDMA0_REQDSTREG_CH0_Pos)                    /*!< GPDMA0 REQDSTREG: CH0 Mask              */\r
+#define GPDMA0_REQDSTREG_CH1_Pos              1                                                       /*!< GPDMA0 REQDSTREG: CH1 Position          */\r
+#define GPDMA0_REQDSTREG_CH1_Msk              (0x01UL << GPDMA0_REQDSTREG_CH1_Pos)                    /*!< GPDMA0 REQDSTREG: CH1 Mask              */\r
+#define GPDMA0_REQDSTREG_CH2_Pos              2                                                       /*!< GPDMA0 REQDSTREG: CH2 Position          */\r
+#define GPDMA0_REQDSTREG_CH2_Msk              (0x01UL << GPDMA0_REQDSTREG_CH2_Pos)                    /*!< GPDMA0 REQDSTREG: CH2 Mask              */\r
+#define GPDMA0_REQDSTREG_CH3_Pos              3                                                       /*!< GPDMA0 REQDSTREG: CH3 Position          */\r
+#define GPDMA0_REQDSTREG_CH3_Msk              (0x01UL << GPDMA0_REQDSTREG_CH3_Pos)                    /*!< GPDMA0 REQDSTREG: CH3 Mask              */\r
+#define GPDMA0_REQDSTREG_CH4_Pos              4                                                       /*!< GPDMA0 REQDSTREG: CH4 Position          */\r
+#define GPDMA0_REQDSTREG_CH4_Msk              (0x01UL << GPDMA0_REQDSTREG_CH4_Pos)                    /*!< GPDMA0 REQDSTREG: CH4 Mask              */\r
+#define GPDMA0_REQDSTREG_CH5_Pos              5                                                       /*!< GPDMA0 REQDSTREG: CH5 Position          */\r
+#define GPDMA0_REQDSTREG_CH5_Msk              (0x01UL << GPDMA0_REQDSTREG_CH5_Pos)                    /*!< GPDMA0 REQDSTREG: CH5 Mask              */\r
+#define GPDMA0_REQDSTREG_CH6_Pos              6                                                       /*!< GPDMA0 REQDSTREG: CH6 Position          */\r
+#define GPDMA0_REQDSTREG_CH6_Msk              (0x01UL << GPDMA0_REQDSTREG_CH6_Pos)                    /*!< GPDMA0 REQDSTREG: CH6 Mask              */\r
+#define GPDMA0_REQDSTREG_CH7_Pos              7                                                       /*!< GPDMA0 REQDSTREG: CH7 Position          */\r
+#define GPDMA0_REQDSTREG_CH7_Msk              (0x01UL << GPDMA0_REQDSTREG_CH7_Pos)                    /*!< GPDMA0 REQDSTREG: CH7 Mask              */\r
+#define GPDMA0_REQDSTREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 REQDSTREG: WE_CH0 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH0_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH0_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH0 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 REQDSTREG: WE_CH1 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH1_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH1_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH1 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 REQDSTREG: WE_CH2 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH2_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH2_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH2 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 REQDSTREG: WE_CH3 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH3_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH3_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH3 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 REQDSTREG: WE_CH4 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH4_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH4_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH4 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 REQDSTREG: WE_CH5 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH5_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH5_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH5 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 REQDSTREG: WE_CH6 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH6_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH6_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH6 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 REQDSTREG: WE_CH7 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH7_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH7_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH7 Mask           */\r
+\r
+/* -----------------------------  GPDMA0_SGLREQSRCREG  ---------------------------- */\r
+#define GPDMA0_SGLREQSRCREG_CH0_Pos           0                                                       /*!< GPDMA0 SGLREQSRCREG: CH0 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH0_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH0_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH0 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH1_Pos           1                                                       /*!< GPDMA0 SGLREQSRCREG: CH1 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH1_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH1_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH1 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH2_Pos           2                                                       /*!< GPDMA0 SGLREQSRCREG: CH2 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH2_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH2_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH2 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH3_Pos           3                                                       /*!< GPDMA0 SGLREQSRCREG: CH3 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH3_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH3_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH3 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH4_Pos           4                                                       /*!< GPDMA0 SGLREQSRCREG: CH4 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH4_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH4_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH4 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH5_Pos           5                                                       /*!< GPDMA0 SGLREQSRCREG: CH5 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH5_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH5_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH5 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH6_Pos           6                                                       /*!< GPDMA0 SGLREQSRCREG: CH6 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH6_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH6_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH6 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH7_Pos           7                                                       /*!< GPDMA0 SGLREQSRCREG: CH7 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH7_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH7_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH7 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH0_Pos        8                                                       /*!< GPDMA0 SGLREQSRCREG: WE_CH0 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH0_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH0_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH0 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH1_Pos        9                                                       /*!< GPDMA0 SGLREQSRCREG: WE_CH1 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH1_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH1_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH1 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH2_Pos        10                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH2 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH2_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH2_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH2 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH3_Pos        11                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH3 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH3_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH3_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH3 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH4_Pos        12                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH4 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH4_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH4_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH4 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH5_Pos        13                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH5 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH5_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH5_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH5 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH6_Pos        14                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH6 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH6_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH6_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH6 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH7_Pos        15                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH7 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH7_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH7_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH7 Mask        */\r
+\r
+/* -----------------------------  GPDMA0_SGLREQDSTREG  ---------------------------- */\r
+#define GPDMA0_SGLREQDSTREG_CH0_Pos           0                                                       /*!< GPDMA0 SGLREQDSTREG: CH0 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH0_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH0_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH0 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH1_Pos           1                                                       /*!< GPDMA0 SGLREQDSTREG: CH1 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH1_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH1_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH1 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH2_Pos           2                                                       /*!< GPDMA0 SGLREQDSTREG: CH2 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH2_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH2_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH2 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH3_Pos           3                                                       /*!< GPDMA0 SGLREQDSTREG: CH3 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH3_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH3_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH3 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH4_Pos           4                                                       /*!< GPDMA0 SGLREQDSTREG: CH4 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH4_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH4_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH4 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH5_Pos           5                                                       /*!< GPDMA0 SGLREQDSTREG: CH5 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH5_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH5_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH5 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH6_Pos           6                                                       /*!< GPDMA0 SGLREQDSTREG: CH6 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH6_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH6_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH6 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH7_Pos           7                                                       /*!< GPDMA0 SGLREQDSTREG: CH7 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH7_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH7_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH7 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH0_Pos        8                                                       /*!< GPDMA0 SGLREQDSTREG: WE_CH0 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH0_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH0_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH0 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH1_Pos        9                                                       /*!< GPDMA0 SGLREQDSTREG: WE_CH1 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH1_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH1_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH1 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH2_Pos        10                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH2 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH2_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH2_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH2 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH3_Pos        11                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH3 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH3_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH3_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH3 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH4_Pos        12                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH4 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH4_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH4_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH4 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH5_Pos        13                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH5 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH5_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH5_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH5 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH6_Pos        14                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH6 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH6_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH6_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH6 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH7_Pos        15                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH7 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH7_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH7_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH7 Mask        */\r
+\r
+/* ------------------------------  GPDMA0_LSTSRCREG  ------------------------------ */\r
+#define GPDMA0_LSTSRCREG_CH0_Pos              0                                                       /*!< GPDMA0 LSTSRCREG: CH0 Position          */\r
+#define GPDMA0_LSTSRCREG_CH0_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH0_Pos)                    /*!< GPDMA0 LSTSRCREG: CH0 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH1_Pos              1                                                       /*!< GPDMA0 LSTSRCREG: CH1 Position          */\r
+#define GPDMA0_LSTSRCREG_CH1_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH1_Pos)                    /*!< GPDMA0 LSTSRCREG: CH1 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH2_Pos              2                                                       /*!< GPDMA0 LSTSRCREG: CH2 Position          */\r
+#define GPDMA0_LSTSRCREG_CH2_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH2_Pos)                    /*!< GPDMA0 LSTSRCREG: CH2 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH3_Pos              3                                                       /*!< GPDMA0 LSTSRCREG: CH3 Position          */\r
+#define GPDMA0_LSTSRCREG_CH3_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH3_Pos)                    /*!< GPDMA0 LSTSRCREG: CH3 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH4_Pos              4                                                       /*!< GPDMA0 LSTSRCREG: CH4 Position          */\r
+#define GPDMA0_LSTSRCREG_CH4_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH4_Pos)                    /*!< GPDMA0 LSTSRCREG: CH4 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH5_Pos              5                                                       /*!< GPDMA0 LSTSRCREG: CH5 Position          */\r
+#define GPDMA0_LSTSRCREG_CH5_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH5_Pos)                    /*!< GPDMA0 LSTSRCREG: CH5 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH6_Pos              6                                                       /*!< GPDMA0 LSTSRCREG: CH6 Position          */\r
+#define GPDMA0_LSTSRCREG_CH6_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH6_Pos)                    /*!< GPDMA0 LSTSRCREG: CH6 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH7_Pos              7                                                       /*!< GPDMA0 LSTSRCREG: CH7 Position          */\r
+#define GPDMA0_LSTSRCREG_CH7_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH7_Pos)                    /*!< GPDMA0 LSTSRCREG: CH7 Mask              */\r
+#define GPDMA0_LSTSRCREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 LSTSRCREG: WE_CH0 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH0_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH0_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH0 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 LSTSRCREG: WE_CH1 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH1_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH1_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH1 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 LSTSRCREG: WE_CH2 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH2_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH2_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH2 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 LSTSRCREG: WE_CH3 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH3_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH3_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH3 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 LSTSRCREG: WE_CH4 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH4_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH4_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH4 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 LSTSRCREG: WE_CH5 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH5_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH5_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH5 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 LSTSRCREG: WE_CH6 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH6_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH6_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH6 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 LSTSRCREG: WE_CH7 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH7_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH7_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH7 Mask           */\r
+\r
+/* ------------------------------  GPDMA0_LSTDSTREG  ------------------------------ */\r
+#define GPDMA0_LSTDSTREG_CH0_Pos              0                                                       /*!< GPDMA0 LSTDSTREG: CH0 Position          */\r
+#define GPDMA0_LSTDSTREG_CH0_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH0_Pos)                    /*!< GPDMA0 LSTDSTREG: CH0 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH1_Pos              1                                                       /*!< GPDMA0 LSTDSTREG: CH1 Position          */\r
+#define GPDMA0_LSTDSTREG_CH1_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH1_Pos)                    /*!< GPDMA0 LSTDSTREG: CH1 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH2_Pos              2                                                       /*!< GPDMA0 LSTDSTREG: CH2 Position          */\r
+#define GPDMA0_LSTDSTREG_CH2_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH2_Pos)                    /*!< GPDMA0 LSTDSTREG: CH2 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH3_Pos              3                                                       /*!< GPDMA0 LSTDSTREG: CH3 Position          */\r
+#define GPDMA0_LSTDSTREG_CH3_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH3_Pos)                    /*!< GPDMA0 LSTDSTREG: CH3 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH4_Pos              4                                                       /*!< GPDMA0 LSTDSTREG: CH4 Position          */\r
+#define GPDMA0_LSTDSTREG_CH4_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH4_Pos)                    /*!< GPDMA0 LSTDSTREG: CH4 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH5_Pos              5                                                       /*!< GPDMA0 LSTDSTREG: CH5 Position          */\r
+#define GPDMA0_LSTDSTREG_CH5_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH5_Pos)                    /*!< GPDMA0 LSTDSTREG: CH5 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH6_Pos              6                                                       /*!< GPDMA0 LSTDSTREG: CH6 Position          */\r
+#define GPDMA0_LSTDSTREG_CH6_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH6_Pos)                    /*!< GPDMA0 LSTDSTREG: CH6 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH7_Pos              7                                                       /*!< GPDMA0 LSTDSTREG: CH7 Position          */\r
+#define GPDMA0_LSTDSTREG_CH7_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH7_Pos)                    /*!< GPDMA0 LSTDSTREG: CH7 Mask              */\r
+#define GPDMA0_LSTDSTREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 LSTDSTREG: WE_CH0 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH0_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH0_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH0 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 LSTDSTREG: WE_CH1 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH1_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH1_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH1 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 LSTDSTREG: WE_CH2 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH2_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH2_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH2 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 LSTDSTREG: WE_CH3 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH3_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH3_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH3 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 LSTDSTREG: WE_CH4 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH4_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH4_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH4 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 LSTDSTREG: WE_CH5 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH5_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH5_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH5 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 LSTDSTREG: WE_CH6 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH6_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH6_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH6 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 LSTDSTREG: WE_CH7 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH7_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH7_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH7 Mask           */\r
+\r
+/* ------------------------------  GPDMA0_DMACFGREG  ------------------------------ */\r
+#define GPDMA0_DMACFGREG_DMA_EN_Pos           0                                                       /*!< GPDMA0 DMACFGREG: DMA_EN Position       */\r
+#define GPDMA0_DMACFGREG_DMA_EN_Msk           (0x01UL << GPDMA0_DMACFGREG_DMA_EN_Pos)                 /*!< GPDMA0 DMACFGREG: DMA_EN Mask           */\r
+\r
+/* -------------------------------  GPDMA0_CHENREG  ------------------------------- */\r
+#define GPDMA0_CHENREG_CH_Pos                 0                                                       /*!< GPDMA0 CHENREG: CH Position             */\r
+#define GPDMA0_CHENREG_CH_Msk                 (0x000000ffUL << GPDMA0_CHENREG_CH_Pos)                 /*!< GPDMA0 CHENREG: CH Mask                 */\r
+#define GPDMA0_CHENREG_WE_CH_Pos              8                                                       /*!< GPDMA0 CHENREG: WE_CH Position          */\r
+#define GPDMA0_CHENREG_WE_CH_Msk              (0x000000ffUL << GPDMA0_CHENREG_WE_CH_Pos)              /*!< GPDMA0 CHENREG: WE_CH Mask              */\r
+\r
+/* ----------------------------------  GPDMA0_ID  --------------------------------- */\r
+#define GPDMA0_ID_VALUE_Pos                   0                                                       /*!< GPDMA0 ID: VALUE Position               */\r
+#define GPDMA0_ID_VALUE_Msk                   (0xffffffffUL << GPDMA0_ID_VALUE_Pos)                   /*!< GPDMA0 ID: VALUE Mask                   */\r
+\r
+/* ---------------------------------  GPDMA0_TYPE  -------------------------------- */\r
+#define GPDMA0_TYPE_VALUE_Pos                 0                                                       /*!< GPDMA0 TYPE: VALUE Position             */\r
+#define GPDMA0_TYPE_VALUE_Msk                 (0xffffffffUL << GPDMA0_TYPE_VALUE_Pos)                 /*!< GPDMA0 TYPE: VALUE Mask                 */\r
+\r
+/* -------------------------------  GPDMA0_VERSION  ------------------------------- */\r
+#define GPDMA0_VERSION_VALUE_Pos              0                                                       /*!< GPDMA0 VERSION: VALUE Position          */\r
+#define GPDMA0_VERSION_VALUE_Msk              (0xffffffffUL << GPDMA0_VERSION_VALUE_Pos)              /*!< GPDMA0 VERSION: VALUE Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      Group 'GPDMA0_CH0_1' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  GPDMA0_CH_SAR  ------------------------------ */\r
+#define GPDMA0_CH_SAR_SAR_Pos              0                                                       /*!< GPDMA0_CH0_1 SAR: SAR Position          */\r
+#define GPDMA0_CH_SAR_SAR_Msk              (0xffffffffUL << GPDMA0_CH_SAR_SAR_Pos)              /*!< GPDMA0_CH0_1 SAR: SAR Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_DAR  ------------------------------ */\r
+#define GPDMA0_CH_DAR_DAR_Pos              0                                                       /*!< GPDMA0_CH0_1 DAR: DAR Position          */\r
+#define GPDMA0_CH_DAR_DAR_Msk              (0xffffffffUL << GPDMA0_CH_DAR_DAR_Pos)              /*!< GPDMA0_CH0_1 DAR: DAR Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_LLP  ------------------------------ */\r
+#define GPDMA0_CH_LLP_LOC_Pos              2                                                       /*!< GPDMA0_CH0_1 LLP: LOC Position          */\r
+#define GPDMA0_CH_LLP_LOC_Msk              (0x3fffffffUL << GPDMA0_CH_LLP_LOC_Pos)              /*!< GPDMA0_CH0_1 LLP: LOC Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_CTLL  ----------------------------- */\r
+#define GPDMA0_CH_CTLL_INT_EN_Pos          0                                                       /*!< GPDMA0_CH0_1 CTLL: INT_EN Position      */\r
+#define GPDMA0_CH_CTLL_INT_EN_Msk          (0x01UL << GPDMA0_CH_CTLL_INT_EN_Pos)                /*!< GPDMA0_CH0_1 CTLL: INT_EN Mask          */\r
+#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos    1                                                       /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH Position */\r
+#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk    (0x07UL << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos)          /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH Mask    */\r
+#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos    4                                                       /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH Position */\r
+#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk    (0x07UL << GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos)          /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH Mask    */\r
+#define GPDMA0_CH_CTLL_DINC_Pos            7                                                       /*!< GPDMA0_CH0_1 CTLL: DINC Position        */\r
+#define GPDMA0_CH_CTLL_DINC_Msk            (0x03UL << GPDMA0_CH_CTLL_DINC_Pos)                  /*!< GPDMA0_CH0_1 CTLL: DINC Mask            */\r
+#define GPDMA0_CH_CTLL_SINC_Pos            9                                                       /*!< GPDMA0_CH0_1 CTLL: SINC Position        */\r
+#define GPDMA0_CH_CTLL_SINC_Msk            (0x03UL << GPDMA0_CH_CTLL_SINC_Pos)                  /*!< GPDMA0_CH0_1 CTLL: SINC Mask            */\r
+#define GPDMA0_CH_CTLL_DEST_MSIZE_Pos      11                                                      /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE Position  */\r
+#define GPDMA0_CH_CTLL_DEST_MSIZE_Msk      (0x07UL << GPDMA0_CH_CTLL_DEST_MSIZE_Pos)            /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE Mask      */\r
+#define GPDMA0_CH_CTLL_SRC_MSIZE_Pos       14                                                      /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE Position   */\r
+#define GPDMA0_CH_CTLL_SRC_MSIZE_Msk       (0x07UL << GPDMA0_CH_CTLL_SRC_MSIZE_Pos)             /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE Mask       */\r
+#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos   17                                                      /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN Position */\r
+#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk   (0x01UL << GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos)         /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN Mask   */\r
+#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos  18                                                      /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN Position */\r
+#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk  (0x01UL << GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos)        /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN Mask  */\r
+#define GPDMA0_CH_CTLL_TT_FC_Pos           20                                                      /*!< GPDMA0_CH0_1 CTLL: TT_FC Position       */\r
+#define GPDMA0_CH_CTLL_TT_FC_Msk           (0x07UL << GPDMA0_CH_CTLL_TT_FC_Pos)                 /*!< GPDMA0_CH0_1 CTLL: TT_FC Mask           */\r
+#define GPDMA0_CH_CTLL_LLP_DST_EN_Pos      27                                                      /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN Position  */\r
+#define GPDMA0_CH_CTLL_LLP_DST_EN_Msk      (0x01UL << GPDMA0_CH_CTLL_LLP_DST_EN_Pos)            /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN Mask      */\r
+#define GPDMA0_CH_CTLL_LLP_SRC_EN_Pos      28                                                      /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN Position  */\r
+#define GPDMA0_CH_CTLL_LLP_SRC_EN_Msk      (0x01UL << GPDMA0_CH_CTLL_LLP_SRC_EN_Pos)            /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN Mask      */\r
+\r
+/* ------------------------------  GPDMA0_CH_CTLH  ----------------------------- */\r
+#define GPDMA0_CH_CTLH_BLOCK_TS_Pos        0                                                       /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS Position    */\r
+#define GPDMA0_CH_CTLH_BLOCK_TS_Msk        (0x00000fffUL << GPDMA0_CH_CTLH_BLOCK_TS_Pos)        /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS Mask        */\r
+#define GPDMA0_CH_CTLH_DONE_Pos            12                                                      /*!< GPDMA0_CH0_1 CTLH: DONE Position        */\r
+#define GPDMA0_CH_CTLH_DONE_Msk            (0x01UL << GPDMA0_CH_CTLH_DONE_Pos)                  /*!< GPDMA0_CH0_1 CTLH: DONE Mask            */\r
+\r
+/* -----------------------------  GPDMA0_CH_SSTAT  ----------------------------- */\r
+#define GPDMA0_CH_SSTAT_SSTAT_Pos          0                                                       /*!< GPDMA0_CH0_1 SSTAT: SSTAT Position      */\r
+#define GPDMA0_CH_SSTAT_SSTAT_Msk          (0xffffffffUL << GPDMA0_CH_SSTAT_SSTAT_Pos)          /*!< GPDMA0_CH0_1 SSTAT: SSTAT Mask          */\r
+\r
+/* -----------------------------  GPDMA0_CH_DSTAT  ----------------------------- */\r
+#define GPDMA0_CH_DSTAT_DSTAT_Pos          0                                                       /*!< GPDMA0_CH0_1 DSTAT: DSTAT Position      */\r
+#define GPDMA0_CH_DSTAT_DSTAT_Msk          (0xffffffffUL << GPDMA0_CH_DSTAT_DSTAT_Pos)          /*!< GPDMA0_CH0_1 DSTAT: DSTAT Mask          */\r
+\r
+/* ----------------------------  GPDMA0_CH_SSTATAR  ---------------------------- */\r
+#define GPDMA0_CH_SSTATAR_SSTATAR_Pos      0                                                       /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR Position  */\r
+#define GPDMA0_CH_SSTATAR_SSTATAR_Msk      (0xffffffffUL << GPDMA0_CH_SSTATAR_SSTATAR_Pos)      /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR Mask      */\r
+\r
+/* ----------------------------  GPDMA0_CH_DSTATAR  ---------------------------- */\r
+#define GPDMA0_CH_DSTATAR_DSTATAR_Pos      0                                                       /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR Position  */\r
+#define GPDMA0_CH_DSTATAR_DSTATAR_Msk      (0xffffffffUL << GPDMA0_CH_DSTATAR_DSTATAR_Pos)      /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR Mask      */\r
+\r
+/* ------------------------------  GPDMA0_CH_CFGL  ----------------------------- */\r
+#define GPDMA0_CH_CFGL_CH_PRIOR_Pos        5                                                       /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR Position    */\r
+#define GPDMA0_CH_CFGL_CH_PRIOR_Msk        (0x07UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos)              /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR Mask        */\r
+#define GPDMA0_CH_CFGL_CH_SUSP_Pos         8                                                       /*!< GPDMA0_CH0_1 CFGL: CH_SUSP Position     */\r
+#define GPDMA0_CH_CFGL_CH_SUSP_Msk         (0x01UL << GPDMA0_CH_CFGL_CH_SUSP_Pos)               /*!< GPDMA0_CH0_1 CFGL: CH_SUSP Mask         */\r
+#define GPDMA0_CH_CFGL_FIFO_EMPTY_Pos      9                                                       /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY Position  */\r
+#define GPDMA0_CH_CFGL_FIFO_EMPTY_Msk      (0x01UL << GPDMA0_CH_CFGL_FIFO_EMPTY_Pos)            /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY Mask      */\r
+#define GPDMA0_CH_CFGL_HS_SEL_DST_Pos      10                                                      /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST Position  */\r
+#define GPDMA0_CH_CFGL_HS_SEL_DST_Msk      (0x01UL << GPDMA0_CH_CFGL_HS_SEL_DST_Pos)            /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST Mask      */\r
+#define GPDMA0_CH_CFGL_HS_SEL_SRC_Pos      11                                                      /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC Position  */\r
+#define GPDMA0_CH_CFGL_HS_SEL_SRC_Msk      (0x01UL << GPDMA0_CH_CFGL_HS_SEL_SRC_Pos)            /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC Mask      */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_L_Pos       12                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L Position   */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_L_Msk       (0x03UL << GPDMA0_CH_CFGL_LOCK_CH_L_Pos)             /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L Mask       */\r
+#define GPDMA0_CH_CFGL_LOCK_B_L_Pos        14                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L Position    */\r
+#define GPDMA0_CH_CFGL_LOCK_B_L_Msk        (0x03UL << GPDMA0_CH_CFGL_LOCK_B_L_Pos)              /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L Mask        */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_Pos         16                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_CH Position     */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_Msk         (0x01UL << GPDMA0_CH_CFGL_LOCK_CH_Pos)               /*!< GPDMA0_CH0_1 CFGL: LOCK_CH Mask         */\r
+#define GPDMA0_CH_CFGL_LOCK_B_Pos          17                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_B Position      */\r
+#define GPDMA0_CH_CFGL_LOCK_B_Msk          (0x01UL << GPDMA0_CH_CFGL_LOCK_B_Pos)                /*!< GPDMA0_CH0_1 CFGL: LOCK_B Mask          */\r
+#define GPDMA0_CH_CFGL_DST_HS_POL_Pos      18                                                      /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL Position  */\r
+#define GPDMA0_CH_CFGL_DST_HS_POL_Msk      (0x01UL << GPDMA0_CH_CFGL_DST_HS_POL_Pos)            /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL Mask      */\r
+#define GPDMA0_CH_CFGL_SRC_HS_POL_Pos      19                                                      /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL Position  */\r
+#define GPDMA0_CH_CFGL_SRC_HS_POL_Msk      (0x01UL << GPDMA0_CH_CFGL_SRC_HS_POL_Pos)            /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL Mask      */\r
+#define GPDMA0_CH_CFGL_MAX_ABRST_Pos       20                                                      /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST Position   */\r
+#define GPDMA0_CH_CFGL_MAX_ABRST_Msk       (0x000003ffUL << GPDMA0_CH_CFGL_MAX_ABRST_Pos)       /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST Mask       */\r
+#define GPDMA0_CH_CFGL_RELOAD_SRC_Pos      30                                                      /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC Position  */\r
+#define GPDMA0_CH_CFGL_RELOAD_SRC_Msk      (0x01UL << GPDMA0_CH_CFGL_RELOAD_SRC_Pos)            /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC Mask      */\r
+#define GPDMA0_CH_CFGL_RELOAD_DST_Pos      31                                                      /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST Position  */\r
+#define GPDMA0_CH_CFGL_RELOAD_DST_Msk      (0x01UL << GPDMA0_CH_CFGL_RELOAD_DST_Pos)            /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST Mask      */\r
+\r
+/* ------------------------------  GPDMA0_CH_CFGH  ----------------------------- */\r
+#define GPDMA0_CH_CFGH_FCMODE_Pos          0                                                       /*!< GPDMA0_CH0_1 CFGH: FCMODE Position      */\r
+#define GPDMA0_CH_CFGH_FCMODE_Msk          (0x01UL << GPDMA0_CH_CFGH_FCMODE_Pos)                /*!< GPDMA0_CH0_1 CFGH: FCMODE Mask          */\r
+#define GPDMA0_CH_CFGH_FIFO_MODE_Pos       1                                                       /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE Position   */\r
+#define GPDMA0_CH_CFGH_FIFO_MODE_Msk       (0x01UL << GPDMA0_CH_CFGH_FIFO_MODE_Pos)             /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE Mask       */\r
+#define GPDMA0_CH_CFGH_PROTCTL_Pos         2                                                       /*!< GPDMA0_CH0_1 CFGH: PROTCTL Position     */\r
+#define GPDMA0_CH_CFGH_PROTCTL_Msk         (0x07UL << GPDMA0_CH_CFGH_PROTCTL_Pos)               /*!< GPDMA0_CH0_1 CFGH: PROTCTL Mask         */\r
+#define GPDMA0_CH_CFGH_DS_UPD_EN_Pos       5                                                       /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN Position   */\r
+#define GPDMA0_CH_CFGH_DS_UPD_EN_Msk       (0x01UL << GPDMA0_CH_CFGH_DS_UPD_EN_Pos)             /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN Mask       */\r
+#define GPDMA0_CH_CFGH_SS_UPD_EN_Pos       6                                                       /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN Position   */\r
+#define GPDMA0_CH_CFGH_SS_UPD_EN_Msk       (0x01UL << GPDMA0_CH_CFGH_SS_UPD_EN_Pos)             /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN Mask       */\r
+#define GPDMA0_CH_CFGH_SRC_PER_Pos         7                                                       /*!< GPDMA0_CH0_1 CFGH: SRC_PER Position     */\r
+#define GPDMA0_CH_CFGH_SRC_PER_Msk         (0x0fUL << GPDMA0_CH_CFGH_SRC_PER_Pos)               /*!< GPDMA0_CH0_1 CFGH: SRC_PER Mask         */\r
+#define GPDMA0_CH_CFGH_DEST_PER_Pos        11                                                      /*!< GPDMA0_CH0_1 CFGH: DEST_PER Position    */\r
+#define GPDMA0_CH_CFGH_DEST_PER_Msk        (0x0fUL << GPDMA0_CH_CFGH_DEST_PER_Pos)              /*!< GPDMA0_CH0_1 CFGH: DEST_PER Mask        */\r
+\r
+/* ------------------------------  GPDMA0_CH_SGR  ------------------------------ */\r
+#define GPDMA0_CH_SGR_SGI_Pos              0                                                       /*!< GPDMA0_CH0_1 SGR: SGI Position          */\r
+#define GPDMA0_CH_SGR_SGI_Msk              (0x000fffffUL << GPDMA0_CH_SGR_SGI_Pos)              /*!< GPDMA0_CH0_1 SGR: SGI Mask              */\r
+#define GPDMA0_CH_SGR_SGC_Pos              20                                                      /*!< GPDMA0_CH0_1 SGR: SGC Position          */\r
+#define GPDMA0_CH_SGR_SGC_Msk              (0x00000fffUL << GPDMA0_CH_SGR_SGC_Pos)              /*!< GPDMA0_CH0_1 SGR: SGC Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_DSR  ------------------------------ */\r
+#define GPDMA0_CH_DSR_DSI_Pos              0                                                       /*!< GPDMA0_CH0_1 DSR: DSI Position          */\r
+#define GPDMA0_CH_DSR_DSI_Msk              (0x000fffffUL << GPDMA0_CH_DSR_DSI_Pos)              /*!< GPDMA0_CH0_1 DSR: DSI Mask              */\r
+#define GPDMA0_CH_DSR_DSC_Pos              20                                                      /*!< GPDMA0_CH0_1 DSR: DSC Position          */\r
+#define GPDMA0_CH_DSR_DSC_Msk              (0x00000fffUL << GPDMA0_CH_DSR_DSC_Pos)              /*!< GPDMA0_CH0_1 DSR: DSC Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'FCE' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  FCE_CLC  ---------------------------------- */\r
+#define FCE_CLC_DISR_Pos                      0                                                       /*!< FCE CLC: DISR Position                  */\r
+#define FCE_CLC_DISR_Msk                      (0x01UL << FCE_CLC_DISR_Pos)                            /*!< FCE CLC: DISR Mask                      */\r
+#define FCE_CLC_DISS_Pos                      1                                                       /*!< FCE CLC: DISS Position                  */\r
+#define FCE_CLC_DISS_Msk                      (0x01UL << FCE_CLC_DISS_Pos)                            /*!< FCE CLC: DISS Mask                      */\r
+\r
+/* -----------------------------------  FCE_ID  ----------------------------------- */\r
+#define FCE_ID_MOD_REV_Pos                    0                                                       /*!< FCE ID: MOD_REV Position                */\r
+#define FCE_ID_MOD_REV_Msk                    (0x000000ffUL << FCE_ID_MOD_REV_Pos)                    /*!< FCE ID: MOD_REV Mask                    */\r
+#define FCE_ID_MOD_TYPE_Pos                   8                                                       /*!< FCE ID: MOD_TYPE Position               */\r
+#define FCE_ID_MOD_TYPE_Msk                   (0x000000ffUL << FCE_ID_MOD_TYPE_Pos)                   /*!< FCE ID: MOD_TYPE Mask                   */\r
+#define FCE_ID_MOD_NUMBER_Pos                 16                                                      /*!< FCE ID: MOD_NUMBER Position             */\r
+#define FCE_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << FCE_ID_MOD_NUMBER_Pos)                 /*!< FCE ID: MOD_NUMBER Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'FCE_KE' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  FCE_KE_IR  --------------------------------- */\r
+#define FCE_KE_IR_IR_Pos                      0                                                       /*!< FCE_KE IR: IR Position                  */\r
+#define FCE_KE_IR_IR_Msk                      (0xffffffffUL << FCE_KE_IR_IR_Pos)                      /*!< FCE_KE IR: IR Mask                      */\r
+\r
+/* ---------------------------------  FCE_KE_RES  --------------------------------- */\r
+#define FCE_KE_RES_RES_Pos                    0                                                       /*!< FCE_KE RES: RES Position                */\r
+#define FCE_KE_RES_RES_Msk                    (0xffffffffUL << FCE_KE_RES_RES_Pos)                    /*!< FCE_KE RES: RES Mask                    */\r
+\r
+/* ---------------------------------  FCE_KE_CFG  --------------------------------- */\r
+#define FCE_KE_CFG_CMI_Pos                    0                                                       /*!< FCE_KE CFG: CMI Position                */\r
+#define FCE_KE_CFG_CMI_Msk                    (0x01UL << FCE_KE_CFG_CMI_Pos)                          /*!< FCE_KE CFG: CMI Mask                    */\r
+#define FCE_KE_CFG_CEI_Pos                    1                                                       /*!< FCE_KE CFG: CEI Position                */\r
+#define FCE_KE_CFG_CEI_Msk                    (0x01UL << FCE_KE_CFG_CEI_Pos)                          /*!< FCE_KE CFG: CEI Mask                    */\r
+#define FCE_KE_CFG_LEI_Pos                    2                                                       /*!< FCE_KE CFG: LEI Position                */\r
+#define FCE_KE_CFG_LEI_Msk                    (0x01UL << FCE_KE_CFG_LEI_Pos)                          /*!< FCE_KE CFG: LEI Mask                    */\r
+#define FCE_KE_CFG_BEI_Pos                    3                                                       /*!< FCE_KE CFG: BEI Position                */\r
+#define FCE_KE_CFG_BEI_Msk                    (0x01UL << FCE_KE_CFG_BEI_Pos)                          /*!< FCE_KE CFG: BEI Mask                    */\r
+#define FCE_KE_CFG_CCE_Pos                    4                                                       /*!< FCE_KE CFG: CCE Position                */\r
+#define FCE_KE_CFG_CCE_Msk                    (0x01UL << FCE_KE_CFG_CCE_Pos)                          /*!< FCE_KE CFG: CCE Mask                    */\r
+#define FCE_KE_CFG_ALR_Pos                    5                                                       /*!< FCE_KE CFG: ALR Position                */\r
+#define FCE_KE_CFG_ALR_Msk                    (0x01UL << FCE_KE_CFG_ALR_Pos)                          /*!< FCE_KE CFG: ALR Mask                    */\r
+#define FCE_KE_CFG_REFIN_Pos                  8                                                       /*!< FCE_KE CFG: REFIN Position              */\r
+#define FCE_KE_CFG_REFIN_Msk                  (0x01UL << FCE_KE_CFG_REFIN_Pos)                        /*!< FCE_KE CFG: REFIN Mask                  */\r
+#define FCE_KE_CFG_REFOUT_Pos                 9                                                       /*!< FCE_KE CFG: REFOUT Position             */\r
+#define FCE_KE_CFG_REFOUT_Msk                 (0x01UL << FCE_KE_CFG_REFOUT_Pos)                       /*!< FCE_KE CFG: REFOUT Mask                 */\r
+#define FCE_KE_CFG_XSEL_Pos                   10                                                      /*!< FCE_KE CFG: XSEL Position               */\r
+#define FCE_KE_CFG_XSEL_Msk                   (0x01UL << FCE_KE_CFG_XSEL_Pos)                         /*!< FCE_KE CFG: XSEL Mask                   */\r
+\r
+/* ---------------------------------  FCE_KE_STS  --------------------------------- */\r
+#define FCE_KE_STS_CMF_Pos                    0                                                       /*!< FCE_KE STS: CMF Position                */\r
+#define FCE_KE_STS_CMF_Msk                    (0x01UL << FCE_KE_STS_CMF_Pos)                          /*!< FCE_KE STS: CMF Mask                    */\r
+#define FCE_KE_STS_CEF_Pos                    1                                                       /*!< FCE_KE STS: CEF Position                */\r
+#define FCE_KE_STS_CEF_Msk                    (0x01UL << FCE_KE_STS_CEF_Pos)                          /*!< FCE_KE STS: CEF Mask                    */\r
+#define FCE_KE_STS_LEF_Pos                    2                                                       /*!< FCE_KE STS: LEF Position                */\r
+#define FCE_KE_STS_LEF_Msk                    (0x01UL << FCE_KE_STS_LEF_Pos)                          /*!< FCE_KE STS: LEF Mask                    */\r
+#define FCE_KE_STS_BEF_Pos                    3                                                       /*!< FCE_KE STS: BEF Position                */\r
+#define FCE_KE_STS_BEF_Msk                    (0x01UL << FCE_KE_STS_BEF_Pos)                          /*!< FCE_KE STS: BEF Mask                    */\r
+\r
+/* --------------------------------  FCE_KE_LENGTH  ------------------------------- */\r
+#define FCE_KE_LENGTH_LENGTH_Pos              0                                                       /*!< FCE_KE LENGTH: LENGTH Position          */\r
+#define FCE_KE_LENGTH_LENGTH_Msk              (0x0000ffffUL << FCE_KE_LENGTH_LENGTH_Pos)              /*!< FCE_KE LENGTH: LENGTH Mask              */\r
+\r
+/* --------------------------------  FCE_KE_CHECK  -------------------------------- */\r
+#define FCE_KE_CHECK_CHECK_Pos                0                                                       /*!< FCE_KE CHECK: CHECK Position            */\r
+#define FCE_KE_CHECK_CHECK_Msk                (0xffffffffUL << FCE_KE_CHECK_CHECK_Pos)                /*!< FCE_KE CHECK: CHECK Mask                */\r
+\r
+/* ---------------------------------  FCE_KE_CRC  --------------------------------- */\r
+#define FCE_KE_CRC_CRC_Pos                    0                                                       /*!< FCE_KE CRC: CRC Position                */\r
+#define FCE_KE_CRC_CRC_Msk                    (0xffffffffUL << FCE_KE_CRC_CRC_Pos)                    /*!< FCE_KE CRC: CRC Mask                    */\r
+\r
+/* ---------------------------------  FCE_KE_CTR  --------------------------------- */\r
+#define FCE_KE_CTR_FCM_Pos                    0                                                       /*!< FCE_KE CTR: FCM Position                */\r
+#define FCE_KE_CTR_FCM_Msk                    (0x01UL << FCE_KE_CTR_FCM_Pos)                          /*!< FCE_KE CTR: FCM Mask                    */\r
+#define FCE_KE_CTR_FRM_CFG_Pos                1                                                       /*!< FCE_KE CTR: FRM_CFG Position            */\r
+#define FCE_KE_CTR_FRM_CFG_Msk                (0x01UL << FCE_KE_CTR_FRM_CFG_Pos)                      /*!< FCE_KE CTR: FRM_CFG Mask                */\r
+#define FCE_KE_CTR_FRM_CHECK_Pos              2                                                       /*!< FCE_KE CTR: FRM_CHECK Position          */\r
+#define FCE_KE_CTR_FRM_CHECK_Msk              (0x01UL << FCE_KE_CTR_FRM_CHECK_Pos)                    /*!< FCE_KE CTR: FRM_CHECK Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'PBA' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  PBA_STS  ---------------------------------- */\r
+#define PBA_STS_WERR_Pos                      0                                                       /*!< PBA STS: WERR Position                  */\r
+#define PBA_STS_WERR_Msk                      (0x01UL << PBA_STS_WERR_Pos)                            /*!< PBA STS: WERR Mask                      */\r
+\r
+/* ----------------------------------  PBA_WADDR  --------------------------------- */\r
+#define PBA_WADDR_WADDR_Pos                   0                                                       /*!< PBA WADDR: WADDR Position               */\r
+#define PBA_WADDR_WADDR_Msk                   (0xffffffffUL << PBA_WADDR_WADDR_Pos)                   /*!< PBA WADDR: WADDR Mask                   */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'FLASH' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  FLASH_ID  ---------------------------------- */\r
+#define FLASH_ID_MOD_REV_Pos                  0                                                       /*!< FLASH ID: MOD_REV Position              */\r
+#define FLASH_ID_MOD_REV_Msk                  (0x000000ffUL << FLASH_ID_MOD_REV_Pos)                  /*!< FLASH ID: MOD_REV Mask                  */\r
+#define FLASH_ID_MOD_TYPE_Pos                 8                                                       /*!< FLASH ID: MOD_TYPE Position             */\r
+#define FLASH_ID_MOD_TYPE_Msk                 (0x000000ffUL << FLASH_ID_MOD_TYPE_Pos)                 /*!< FLASH ID: MOD_TYPE Mask                 */\r
+#define FLASH_ID_MOD_NUMBER_Pos               16                                                      /*!< FLASH ID: MOD_NUMBER Position           */\r
+#define FLASH_ID_MOD_NUMBER_Msk               (0x0000ffffUL << FLASH_ID_MOD_NUMBER_Pos)               /*!< FLASH ID: MOD_NUMBER Mask               */\r
+\r
+/* ----------------------------------  FLASH_FSR  --------------------------------- */\r
+#define FLASH_FSR_PBUSY_Pos                   0                                                       /*!< FLASH FSR: PBUSY Position               */\r
+#define FLASH_FSR_PBUSY_Msk                   (0x01UL << FLASH_FSR_PBUSY_Pos)                         /*!< FLASH FSR: PBUSY Mask                   */\r
+#define FLASH_FSR_FABUSY_Pos                  1                                                       /*!< FLASH FSR: FABUSY Position              */\r
+#define FLASH_FSR_FABUSY_Msk                  (0x01UL << FLASH_FSR_FABUSY_Pos)                        /*!< FLASH FSR: FABUSY Mask                  */\r
+#define FLASH_FSR_PROG_Pos                    4                                                       /*!< FLASH FSR: PROG Position                */\r
+#define FLASH_FSR_PROG_Msk                    (0x01UL << FLASH_FSR_PROG_Pos)                          /*!< FLASH FSR: PROG Mask                    */\r
+#define FLASH_FSR_ERASE_Pos                   5                                                       /*!< FLASH FSR: ERASE Position               */\r
+#define FLASH_FSR_ERASE_Msk                   (0x01UL << FLASH_FSR_ERASE_Pos)                         /*!< FLASH FSR: ERASE Mask                   */\r
+#define FLASH_FSR_PFPAGE_Pos                  6                                                       /*!< FLASH FSR: PFPAGE Position              */\r
+#define FLASH_FSR_PFPAGE_Msk                  (0x01UL << FLASH_FSR_PFPAGE_Pos)                        /*!< FLASH FSR: PFPAGE Mask                  */\r
+#define FLASH_FSR_PFOPER_Pos                  8                                                       /*!< FLASH FSR: PFOPER Position              */\r
+#define FLASH_FSR_PFOPER_Msk                  (0x01UL << FLASH_FSR_PFOPER_Pos)                        /*!< FLASH FSR: PFOPER Mask                  */\r
+#define FLASH_FSR_SQER_Pos                    10                                                      /*!< FLASH FSR: SQER Position                */\r
+#define FLASH_FSR_SQER_Msk                    (0x01UL << FLASH_FSR_SQER_Pos)                          /*!< FLASH FSR: SQER Mask                    */\r
+#define FLASH_FSR_PROER_Pos                   11                                                      /*!< FLASH FSR: PROER Position               */\r
+#define FLASH_FSR_PROER_Msk                   (0x01UL << FLASH_FSR_PROER_Pos)                         /*!< FLASH FSR: PROER Mask                   */\r
+#define FLASH_FSR_PFSBER_Pos                  12                                                      /*!< FLASH FSR: PFSBER Position              */\r
+#define FLASH_FSR_PFSBER_Msk                  (0x01UL << FLASH_FSR_PFSBER_Pos)                        /*!< FLASH FSR: PFSBER Mask                  */\r
+#define FLASH_FSR_PFDBER_Pos                  14                                                      /*!< FLASH FSR: PFDBER Position              */\r
+#define FLASH_FSR_PFDBER_Msk                  (0x01UL << FLASH_FSR_PFDBER_Pos)                        /*!< FLASH FSR: PFDBER Mask                  */\r
+#define FLASH_FSR_PROIN_Pos                   16                                                      /*!< FLASH FSR: PROIN Position               */\r
+#define FLASH_FSR_PROIN_Msk                   (0x01UL << FLASH_FSR_PROIN_Pos)                         /*!< FLASH FSR: PROIN Mask                   */\r
+#define FLASH_FSR_RPROIN_Pos                  18                                                      /*!< FLASH FSR: RPROIN Position              */\r
+#define FLASH_FSR_RPROIN_Msk                  (0x01UL << FLASH_FSR_RPROIN_Pos)                        /*!< FLASH FSR: RPROIN Mask                  */\r
+#define FLASH_FSR_RPRODIS_Pos                 19                                                      /*!< FLASH FSR: RPRODIS Position             */\r
+#define FLASH_FSR_RPRODIS_Msk                 (0x01UL << FLASH_FSR_RPRODIS_Pos)                       /*!< FLASH FSR: RPRODIS Mask                 */\r
+#define FLASH_FSR_WPROIN0_Pos                 21                                                      /*!< FLASH FSR: WPROIN0 Position             */\r
+#define FLASH_FSR_WPROIN0_Msk                 (0x01UL << FLASH_FSR_WPROIN0_Pos)                       /*!< FLASH FSR: WPROIN0 Mask                 */\r
+#define FLASH_FSR_WPROIN1_Pos                 22                                                      /*!< FLASH FSR: WPROIN1 Position             */\r
+#define FLASH_FSR_WPROIN1_Msk                 (0x01UL << FLASH_FSR_WPROIN1_Pos)                       /*!< FLASH FSR: WPROIN1 Mask                 */\r
+#define FLASH_FSR_WPROIN2_Pos                 23                                                      /*!< FLASH FSR: WPROIN2 Position             */\r
+#define FLASH_FSR_WPROIN2_Msk                 (0x01UL << FLASH_FSR_WPROIN2_Pos)                       /*!< FLASH FSR: WPROIN2 Mask                 */\r
+#define FLASH_FSR_WPRODIS0_Pos                25                                                      /*!< FLASH FSR: WPRODIS0 Position            */\r
+#define FLASH_FSR_WPRODIS0_Msk                (0x01UL << FLASH_FSR_WPRODIS0_Pos)                      /*!< FLASH FSR: WPRODIS0 Mask                */\r
+#define FLASH_FSR_WPRODIS1_Pos                26                                                      /*!< FLASH FSR: WPRODIS1 Position            */\r
+#define FLASH_FSR_WPRODIS1_Msk                (0x01UL << FLASH_FSR_WPRODIS1_Pos)                      /*!< FLASH FSR: WPRODIS1 Mask                */\r
+#define FLASH_FSR_SLM_Pos                     28                                                      /*!< FLASH FSR: SLM Position                 */\r
+#define FLASH_FSR_SLM_Msk                     (0x01UL << FLASH_FSR_SLM_Pos)                           /*!< FLASH FSR: SLM Mask                     */\r
+#define FLASH_FSR_X_Pos                       30                                                      /*!< FLASH FSR: X Position                   */\r
+#define FLASH_FSR_X_Msk                       (0x01UL << FLASH_FSR_X_Pos)                             /*!< FLASH FSR: X Mask                       */\r
+#define FLASH_FSR_VER_Pos                     31                                                      /*!< FLASH FSR: VER Position                 */\r
+#define FLASH_FSR_VER_Msk                     (0x01UL << FLASH_FSR_VER_Pos)                           /*!< FLASH FSR: VER Mask                     */\r
+\r
+/* ---------------------------------  FLASH_FCON  --------------------------------- */\r
+#define FLASH_FCON_WSPFLASH_Pos               0                                                       /*!< FLASH FCON: WSPFLASH Position           */\r
+#define FLASH_FCON_WSPFLASH_Msk               (0x0fUL << FLASH_FCON_WSPFLASH_Pos)                     /*!< FLASH FCON: WSPFLASH Mask               */\r
+#define FLASH_FCON_WSECPF_Pos                 4                                                       /*!< FLASH FCON: WSECPF Position             */\r
+#define FLASH_FCON_WSECPF_Msk                 (0x01UL << FLASH_FCON_WSECPF_Pos)                       /*!< FLASH FCON: WSECPF Mask                 */\r
+#define FLASH_FCON_IDLE_Pos                   13                                                      /*!< FLASH FCON: IDLE Position               */\r
+#define FLASH_FCON_IDLE_Msk                   (0x01UL << FLASH_FCON_IDLE_Pos)                         /*!< FLASH FCON: IDLE Mask                   */\r
+#define FLASH_FCON_ESLDIS_Pos                 14                                                      /*!< FLASH FCON: ESLDIS Position             */\r
+#define FLASH_FCON_ESLDIS_Msk                 (0x01UL << FLASH_FCON_ESLDIS_Pos)                       /*!< FLASH FCON: ESLDIS Mask                 */\r
+#define FLASH_FCON_SLEEP_Pos                  15                                                      /*!< FLASH FCON: SLEEP Position              */\r
+#define FLASH_FCON_SLEEP_Msk                  (0x01UL << FLASH_FCON_SLEEP_Pos)                        /*!< FLASH FCON: SLEEP Mask                  */\r
+#define FLASH_FCON_RPA_Pos                    16                                                      /*!< FLASH FCON: RPA Position                */\r
+#define FLASH_FCON_RPA_Msk                    (0x01UL << FLASH_FCON_RPA_Pos)                          /*!< FLASH FCON: RPA Mask                    */\r
+#define FLASH_FCON_DCF_Pos                    17                                                      /*!< FLASH FCON: DCF Position                */\r
+#define FLASH_FCON_DCF_Msk                    (0x01UL << FLASH_FCON_DCF_Pos)                          /*!< FLASH FCON: DCF Mask                    */\r
+#define FLASH_FCON_DDF_Pos                    18                                                      /*!< FLASH FCON: DDF Position                */\r
+#define FLASH_FCON_DDF_Msk                    (0x01UL << FLASH_FCON_DDF_Pos)                          /*!< FLASH FCON: DDF Mask                    */\r
+#define FLASH_FCON_VOPERM_Pos                 24                                                      /*!< FLASH FCON: VOPERM Position             */\r
+#define FLASH_FCON_VOPERM_Msk                 (0x01UL << FLASH_FCON_VOPERM_Pos)                       /*!< FLASH FCON: VOPERM Mask                 */\r
+#define FLASH_FCON_SQERM_Pos                  25                                                      /*!< FLASH FCON: SQERM Position              */\r
+#define FLASH_FCON_SQERM_Msk                  (0x01UL << FLASH_FCON_SQERM_Pos)                        /*!< FLASH FCON: SQERM Mask                  */\r
+#define FLASH_FCON_PROERM_Pos                 26                                                      /*!< FLASH FCON: PROERM Position             */\r
+#define FLASH_FCON_PROERM_Msk                 (0x01UL << FLASH_FCON_PROERM_Pos)                       /*!< FLASH FCON: PROERM Mask                 */\r
+#define FLASH_FCON_PFSBERM_Pos                27                                                      /*!< FLASH FCON: PFSBERM Position            */\r
+#define FLASH_FCON_PFSBERM_Msk                (0x01UL << FLASH_FCON_PFSBERM_Pos)                      /*!< FLASH FCON: PFSBERM Mask                */\r
+#define FLASH_FCON_PFDBERM_Pos                29                                                      /*!< FLASH FCON: PFDBERM Position            */\r
+#define FLASH_FCON_PFDBERM_Msk                (0x01UL << FLASH_FCON_PFDBERM_Pos)                      /*!< FLASH FCON: PFDBERM Mask                */\r
+#define FLASH_FCON_EOBM_Pos                   31                                                      /*!< FLASH FCON: EOBM Position               */\r
+#define FLASH_FCON_EOBM_Msk                   (0x01UL << FLASH_FCON_EOBM_Pos)                         /*!< FLASH FCON: EOBM Mask                   */\r
+\r
+/* ---------------------------------  FLASH_MARP  --------------------------------- */\r
+#define FLASH_MARP_MARGIN_Pos                 0                                                       /*!< FLASH MARP: MARGIN Position             */\r
+#define FLASH_MARP_MARGIN_Msk                 (0x0fUL << FLASH_MARP_MARGIN_Pos)                       /*!< FLASH MARP: MARGIN Mask                 */\r
+#define FLASH_MARP_TRAPDIS_Pos                15                                                      /*!< FLASH MARP: TRAPDIS Position            */\r
+#define FLASH_MARP_TRAPDIS_Msk                (0x01UL << FLASH_MARP_TRAPDIS_Pos)                      /*!< FLASH MARP: TRAPDIS Mask                */\r
+\r
+/* --------------------------------  FLASH_PROCON0  ------------------------------- */\r
+#define FLASH_PROCON0_S0L_Pos                 0                                                       /*!< FLASH PROCON0: S0L Position             */\r
+#define FLASH_PROCON0_S0L_Msk                 (0x01UL << FLASH_PROCON0_S0L_Pos)                       /*!< FLASH PROCON0: S0L Mask                 */\r
+#define FLASH_PROCON0_S1L_Pos                 1                                                       /*!< FLASH PROCON0: S1L Position             */\r
+#define FLASH_PROCON0_S1L_Msk                 (0x01UL << FLASH_PROCON0_S1L_Pos)                       /*!< FLASH PROCON0: S1L Mask                 */\r
+#define FLASH_PROCON0_S2L_Pos                 2                                                       /*!< FLASH PROCON0: S2L Position             */\r
+#define FLASH_PROCON0_S2L_Msk                 (0x01UL << FLASH_PROCON0_S2L_Pos)                       /*!< FLASH PROCON0: S2L Mask                 */\r
+#define FLASH_PROCON0_S3L_Pos                 3                                                       /*!< FLASH PROCON0: S3L Position             */\r
+#define FLASH_PROCON0_S3L_Msk                 (0x01UL << FLASH_PROCON0_S3L_Pos)                       /*!< FLASH PROCON0: S3L Mask                 */\r
+#define FLASH_PROCON0_S4L_Pos                 4                                                       /*!< FLASH PROCON0: S4L Position             */\r
+#define FLASH_PROCON0_S4L_Msk                 (0x01UL << FLASH_PROCON0_S4L_Pos)                       /*!< FLASH PROCON0: S4L Mask                 */\r
+#define FLASH_PROCON0_S5L_Pos                 5                                                       /*!< FLASH PROCON0: S5L Position             */\r
+#define FLASH_PROCON0_S5L_Msk                 (0x01UL << FLASH_PROCON0_S5L_Pos)                       /*!< FLASH PROCON0: S5L Mask                 */\r
+#define FLASH_PROCON0_S6L_Pos                 6                                                       /*!< FLASH PROCON0: S6L Position             */\r
+#define FLASH_PROCON0_S6L_Msk                 (0x01UL << FLASH_PROCON0_S6L_Pos)                       /*!< FLASH PROCON0: S6L Mask                 */\r
+#define FLASH_PROCON0_S7L_Pos                 7                                                       /*!< FLASH PROCON0: S7L Position             */\r
+#define FLASH_PROCON0_S7L_Msk                 (0x01UL << FLASH_PROCON0_S7L_Pos)                       /*!< FLASH PROCON0: S7L Mask                 */\r
+#define FLASH_PROCON0_S8L_Pos                 8                                                       /*!< FLASH PROCON0: S8L Position             */\r
+#define FLASH_PROCON0_S8L_Msk                 (0x01UL << FLASH_PROCON0_S8L_Pos)                       /*!< FLASH PROCON0: S8L Mask                 */\r
+#define FLASH_PROCON0_RPRO_Pos                15                                                      /*!< FLASH PROCON0: RPRO Position            */\r
+#define FLASH_PROCON0_RPRO_Msk                (0x01UL << FLASH_PROCON0_RPRO_Pos)                      /*!< FLASH PROCON0: RPRO Mask                */\r
+\r
+/* --------------------------------  FLASH_PROCON1  ------------------------------- */\r
+#define FLASH_PROCON1_S0L_Pos                 0                                                       /*!< FLASH PROCON1: S0L Position             */\r
+#define FLASH_PROCON1_S0L_Msk                 (0x01UL << FLASH_PROCON1_S0L_Pos)                       /*!< FLASH PROCON1: S0L Mask                 */\r
+#define FLASH_PROCON1_S1L_Pos                 1                                                       /*!< FLASH PROCON1: S1L Position             */\r
+#define FLASH_PROCON1_S1L_Msk                 (0x01UL << FLASH_PROCON1_S1L_Pos)                       /*!< FLASH PROCON1: S1L Mask                 */\r
+#define FLASH_PROCON1_S2L_Pos                 2                                                       /*!< FLASH PROCON1: S2L Position             */\r
+#define FLASH_PROCON1_S2L_Msk                 (0x01UL << FLASH_PROCON1_S2L_Pos)                       /*!< FLASH PROCON1: S2L Mask                 */\r
+#define FLASH_PROCON1_S3L_Pos                 3                                                       /*!< FLASH PROCON1: S3L Position             */\r
+#define FLASH_PROCON1_S3L_Msk                 (0x01UL << FLASH_PROCON1_S3L_Pos)                       /*!< FLASH PROCON1: S3L Mask                 */\r
+#define FLASH_PROCON1_S4L_Pos                 4                                                       /*!< FLASH PROCON1: S4L Position             */\r
+#define FLASH_PROCON1_S4L_Msk                 (0x01UL << FLASH_PROCON1_S4L_Pos)                       /*!< FLASH PROCON1: S4L Mask                 */\r
+#define FLASH_PROCON1_S5L_Pos                 5                                                       /*!< FLASH PROCON1: S5L Position             */\r
+#define FLASH_PROCON1_S5L_Msk                 (0x01UL << FLASH_PROCON1_S5L_Pos)                       /*!< FLASH PROCON1: S5L Mask                 */\r
+#define FLASH_PROCON1_S6L_Pos                 6                                                       /*!< FLASH PROCON1: S6L Position             */\r
+#define FLASH_PROCON1_S6L_Msk                 (0x01UL << FLASH_PROCON1_S6L_Pos)                       /*!< FLASH PROCON1: S6L Mask                 */\r
+#define FLASH_PROCON1_S7L_Pos                 7                                                       /*!< FLASH PROCON1: S7L Position             */\r
+#define FLASH_PROCON1_S7L_Msk                 (0x01UL << FLASH_PROCON1_S7L_Pos)                       /*!< FLASH PROCON1: S7L Mask                 */\r
+#define FLASH_PROCON1_S8L_Pos                 8                                                       /*!< FLASH PROCON1: S8L Position             */\r
+#define FLASH_PROCON1_S8L_Msk                 (0x01UL << FLASH_PROCON1_S8L_Pos)                       /*!< FLASH PROCON1: S8L Mask                 */\r
+\r
+/* --------------------------------  FLASH_PROCON2  ------------------------------- */\r
+#define FLASH_PROCON2_S0ROM_Pos               0                                                       /*!< FLASH PROCON2: S0ROM Position           */\r
+#define FLASH_PROCON2_S0ROM_Msk               (0x01UL << FLASH_PROCON2_S0ROM_Pos)                     /*!< FLASH PROCON2: S0ROM Mask               */\r
+#define FLASH_PROCON2_S1ROM_Pos               1                                                       /*!< FLASH PROCON2: S1ROM Position           */\r
+#define FLASH_PROCON2_S1ROM_Msk               (0x01UL << FLASH_PROCON2_S1ROM_Pos)                     /*!< FLASH PROCON2: S1ROM Mask               */\r
+#define FLASH_PROCON2_S2ROM_Pos               2                                                       /*!< FLASH PROCON2: S2ROM Position           */\r
+#define FLASH_PROCON2_S2ROM_Msk               (0x01UL << FLASH_PROCON2_S2ROM_Pos)                     /*!< FLASH PROCON2: S2ROM Mask               */\r
+#define FLASH_PROCON2_S3ROM_Pos               3                                                       /*!< FLASH PROCON2: S3ROM Position           */\r
+#define FLASH_PROCON2_S3ROM_Msk               (0x01UL << FLASH_PROCON2_S3ROM_Pos)                     /*!< FLASH PROCON2: S3ROM Mask               */\r
+#define FLASH_PROCON2_S4ROM_Pos               4                                                       /*!< FLASH PROCON2: S4ROM Position           */\r
+#define FLASH_PROCON2_S4ROM_Msk               (0x01UL << FLASH_PROCON2_S4ROM_Pos)                     /*!< FLASH PROCON2: S4ROM Mask               */\r
+#define FLASH_PROCON2_S5ROM_Pos               5                                                       /*!< FLASH PROCON2: S5ROM Position           */\r
+#define FLASH_PROCON2_S5ROM_Msk               (0x01UL << FLASH_PROCON2_S5ROM_Pos)                     /*!< FLASH PROCON2: S5ROM Mask               */\r
+#define FLASH_PROCON2_S6ROM_Pos               6                                                       /*!< FLASH PROCON2: S6ROM Position           */\r
+#define FLASH_PROCON2_S6ROM_Msk               (0x01UL << FLASH_PROCON2_S6ROM_Pos)                     /*!< FLASH PROCON2: S6ROM Mask               */\r
+#define FLASH_PROCON2_S7ROM_Pos               7                                                       /*!< FLASH PROCON2: S7ROM Position           */\r
+#define FLASH_PROCON2_S7ROM_Msk               (0x01UL << FLASH_PROCON2_S7ROM_Pos)                     /*!< FLASH PROCON2: S7ROM Mask               */\r
+#define FLASH_PROCON2_S8ROM_Pos               8                                                       /*!< FLASH PROCON2: S8ROM Position           */\r
+#define FLASH_PROCON2_S8ROM_Msk               (0x01UL << FLASH_PROCON2_S8ROM_Pos)                     /*!< FLASH PROCON2: S8ROM Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'PREF' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PREF_PCON  --------------------------------- */\r
+#define PREF_PCON_IBYP_Pos                    0                                                       /*!< PREF PCON: IBYP Position                */\r
+#define PREF_PCON_IBYP_Msk                    (0x01UL << PREF_PCON_IBYP_Pos)                          /*!< PREF PCON: IBYP Mask                    */\r
+#define PREF_PCON_IINV_Pos                    1                                                       /*!< PREF PCON: IINV Position                */\r
+#define PREF_PCON_IINV_Msk                    (0x01UL << PREF_PCON_IINV_Pos)                          /*!< PREF PCON: IINV Mask                    */\r
+#define PREF_PCON_DBYP_Pos                    4                                                       /*!< PREF PCON: DBYP Position                */\r
+#define PREF_PCON_DBYP_Msk                    (0x01UL << PREF_PCON_DBYP_Pos)                          /*!< PREF PCON: DBYP Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'PMU' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  PMU_ID  ----------------------------------- */\r
+#define PMU_ID_MOD_REV_Pos                    0                                                       /*!< PMU ID: MOD_REV Position                */\r
+#define PMU_ID_MOD_REV_Msk                    (0x000000ffUL << PMU_ID_MOD_REV_Pos)                    /*!< PMU ID: MOD_REV Mask                    */\r
+#define PMU_ID_MOD_TYPE_Pos                   8                                                       /*!< PMU ID: MOD_TYPE Position               */\r
+#define PMU_ID_MOD_TYPE_Msk                   (0x000000ffUL << PMU_ID_MOD_TYPE_Pos)                   /*!< PMU ID: MOD_TYPE Mask                   */\r
+#define PMU_ID_MOD_NUMBER_Pos                 16                                                      /*!< PMU ID: MOD_NUMBER Position             */\r
+#define PMU_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << PMU_ID_MOD_NUMBER_Pos)                 /*!< PMU ID: MOD_NUMBER Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'WDT' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  WDT_ID  ----------------------------------- */\r
+#define WDT_ID_MOD_REV_Pos                    0                                                       /*!< WDT ID: MOD_REV Position                */\r
+#define WDT_ID_MOD_REV_Msk                    (0x000000ffUL << WDT_ID_MOD_REV_Pos)                    /*!< WDT ID: MOD_REV Mask                    */\r
+#define WDT_ID_MOD_TYPE_Pos                   8                                                       /*!< WDT ID: MOD_TYPE Position               */\r
+#define WDT_ID_MOD_TYPE_Msk                   (0x000000ffUL << WDT_ID_MOD_TYPE_Pos)                   /*!< WDT ID: MOD_TYPE Mask                   */\r
+#define WDT_ID_MOD_NUMBER_Pos                 16                                                      /*!< WDT ID: MOD_NUMBER Position             */\r
+#define WDT_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << WDT_ID_MOD_NUMBER_Pos)                 /*!< WDT ID: MOD_NUMBER Mask                 */\r
+\r
+/* -----------------------------------  WDT_CTR  ---------------------------------- */\r
+#define WDT_CTR_ENB_Pos                       0                                                       /*!< WDT CTR: ENB Position                   */\r
+#define WDT_CTR_ENB_Msk                       (0x01UL << WDT_CTR_ENB_Pos)                             /*!< WDT CTR: ENB Mask                       */\r
+#define WDT_CTR_PRE_Pos                       1                                                       /*!< WDT CTR: PRE Position                   */\r
+#define WDT_CTR_PRE_Msk                       (0x01UL << WDT_CTR_PRE_Pos)                             /*!< WDT CTR: PRE Mask                       */\r
+#define WDT_CTR_DSP_Pos                       4                                                       /*!< WDT CTR: DSP Position                   */\r
+#define WDT_CTR_DSP_Msk                       (0x01UL << WDT_CTR_DSP_Pos)                             /*!< WDT CTR: DSP Mask                       */\r
+#define WDT_CTR_SPW_Pos                       8                                                       /*!< WDT CTR: SPW Position                   */\r
+#define WDT_CTR_SPW_Msk                       (0x000000ffUL << WDT_CTR_SPW_Pos)                       /*!< WDT CTR: SPW Mask                       */\r
+\r
+/* -----------------------------------  WDT_SRV  ---------------------------------- */\r
+#define WDT_SRV_SRV_Pos                       0                                                       /*!< WDT SRV: SRV Position                   */\r
+#define WDT_SRV_SRV_Msk                       (0xffffffffUL << WDT_SRV_SRV_Pos)                       /*!< WDT SRV: SRV Mask                       */\r
+\r
+/* -----------------------------------  WDT_TIM  ---------------------------------- */\r
+#define WDT_TIM_TIM_Pos                       0                                                       /*!< WDT TIM: TIM Position                   */\r
+#define WDT_TIM_TIM_Msk                       (0xffffffffUL << WDT_TIM_TIM_Pos)                       /*!< WDT TIM: TIM Mask                       */\r
+\r
+/* -----------------------------------  WDT_WLB  ---------------------------------- */\r
+#define WDT_WLB_WLB_Pos                       0                                                       /*!< WDT WLB: WLB Position                   */\r
+#define WDT_WLB_WLB_Msk                       (0xffffffffUL << WDT_WLB_WLB_Pos)                       /*!< WDT WLB: WLB Mask                       */\r
+\r
+/* -----------------------------------  WDT_WUB  ---------------------------------- */\r
+#define WDT_WUB_WUB_Pos                       0                                                       /*!< WDT WUB: WUB Position                   */\r
+#define WDT_WUB_WUB_Msk                       (0xffffffffUL << WDT_WUB_WUB_Pos)                       /*!< WDT WUB: WUB Mask                       */\r
+\r
+/* ---------------------------------  WDT_WDTSTS  --------------------------------- */\r
+#define WDT_WDTSTS_ALMS_Pos                   0                                                       /*!< WDT WDTSTS: ALMS Position               */\r
+#define WDT_WDTSTS_ALMS_Msk                   (0x01UL << WDT_WDTSTS_ALMS_Pos)                         /*!< WDT WDTSTS: ALMS Mask                   */\r
+\r
+/* ---------------------------------  WDT_WDTCLR  --------------------------------- */\r
+#define WDT_WDTCLR_ALMC_Pos                   0                                                       /*!< WDT WDTCLR: ALMC Position               */\r
+#define WDT_WDTCLR_ALMC_Msk                   (0x01UL << WDT_WDTCLR_ALMC_Pos)                         /*!< WDT WDTCLR: ALMC Mask                   */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'RTC' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  RTC_ID  ----------------------------------- */\r
+#define RTC_ID_MOD_REV_Pos                    0                                                       /*!< RTC ID: MOD_REV Position                */\r
+#define RTC_ID_MOD_REV_Msk                    (0x000000ffUL << RTC_ID_MOD_REV_Pos)                    /*!< RTC ID: MOD_REV Mask                    */\r
+#define RTC_ID_MOD_TYPE_Pos                   8                                                       /*!< RTC ID: MOD_TYPE Position               */\r
+#define RTC_ID_MOD_TYPE_Msk                   (0x000000ffUL << RTC_ID_MOD_TYPE_Pos)                   /*!< RTC ID: MOD_TYPE Mask                   */\r
+#define RTC_ID_MOD_NUMBER_Pos                 16                                                      /*!< RTC ID: MOD_NUMBER Position             */\r
+#define RTC_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << RTC_ID_MOD_NUMBER_Pos)                 /*!< RTC ID: MOD_NUMBER Mask                 */\r
+\r
+/* -----------------------------------  RTC_CTR  ---------------------------------- */\r
+#define RTC_CTR_ENB_Pos                       0                                                       /*!< RTC CTR: ENB Position                   */\r
+#define RTC_CTR_ENB_Msk                       (0x01UL << RTC_CTR_ENB_Pos)                             /*!< RTC CTR: ENB Mask                       */\r
+#define RTC_CTR_TAE_Pos                       2                                                       /*!< RTC CTR: TAE Position                   */\r
+#define RTC_CTR_TAE_Msk                       (0x01UL << RTC_CTR_TAE_Pos)                             /*!< RTC CTR: TAE Mask                       */\r
+#define RTC_CTR_ESEC_Pos                      8                                                       /*!< RTC CTR: ESEC Position                  */\r
+#define RTC_CTR_ESEC_Msk                      (0x01UL << RTC_CTR_ESEC_Pos)                            /*!< RTC CTR: ESEC Mask                      */\r
+#define RTC_CTR_EMIC_Pos                      9                                                       /*!< RTC CTR: EMIC Position                  */\r
+#define RTC_CTR_EMIC_Msk                      (0x01UL << RTC_CTR_EMIC_Pos)                            /*!< RTC CTR: EMIC Mask                      */\r
+#define RTC_CTR_EHOC_Pos                      10                                                      /*!< RTC CTR: EHOC Position                  */\r
+#define RTC_CTR_EHOC_Msk                      (0x01UL << RTC_CTR_EHOC_Pos)                            /*!< RTC CTR: EHOC Mask                      */\r
+#define RTC_CTR_EDAC_Pos                      11                                                      /*!< RTC CTR: EDAC Position                  */\r
+#define RTC_CTR_EDAC_Msk                      (0x01UL << RTC_CTR_EDAC_Pos)                            /*!< RTC CTR: EDAC Mask                      */\r
+#define RTC_CTR_EMOC_Pos                      13                                                      /*!< RTC CTR: EMOC Position                  */\r
+#define RTC_CTR_EMOC_Msk                      (0x01UL << RTC_CTR_EMOC_Pos)                            /*!< RTC CTR: EMOC Mask                      */\r
+#define RTC_CTR_EYEC_Pos                      14                                                      /*!< RTC CTR: EYEC Position                  */\r
+#define RTC_CTR_EYEC_Msk                      (0x01UL << RTC_CTR_EYEC_Pos)                            /*!< RTC CTR: EYEC Mask                      */\r
+#define RTC_CTR_DIV_Pos                       16                                                      /*!< RTC CTR: DIV Position                   */\r
+#define RTC_CTR_DIV_Msk                       (0x0000ffffUL << RTC_CTR_DIV_Pos)                       /*!< RTC CTR: DIV Mask                       */\r
+\r
+/* ---------------------------------  RTC_RAWSTAT  -------------------------------- */\r
+#define RTC_RAWSTAT_RPSE_Pos                  0                                                       /*!< RTC RAWSTAT: RPSE Position              */\r
+#define RTC_RAWSTAT_RPSE_Msk                  (0x01UL << RTC_RAWSTAT_RPSE_Pos)                        /*!< RTC RAWSTAT: RPSE Mask                  */\r
+#define RTC_RAWSTAT_RPMI_Pos                  1                                                       /*!< RTC RAWSTAT: RPMI Position              */\r
+#define RTC_RAWSTAT_RPMI_Msk                  (0x01UL << RTC_RAWSTAT_RPMI_Pos)                        /*!< RTC RAWSTAT: RPMI Mask                  */\r
+#define RTC_RAWSTAT_RPHO_Pos                  2                                                       /*!< RTC RAWSTAT: RPHO Position              */\r
+#define RTC_RAWSTAT_RPHO_Msk                  (0x01UL << RTC_RAWSTAT_RPHO_Pos)                        /*!< RTC RAWSTAT: RPHO Mask                  */\r
+#define RTC_RAWSTAT_RPDA_Pos                  3                                                       /*!< RTC RAWSTAT: RPDA Position              */\r
+#define RTC_RAWSTAT_RPDA_Msk                  (0x01UL << RTC_RAWSTAT_RPDA_Pos)                        /*!< RTC RAWSTAT: RPDA Mask                  */\r
+#define RTC_RAWSTAT_RPMO_Pos                  5                                                       /*!< RTC RAWSTAT: RPMO Position              */\r
+#define RTC_RAWSTAT_RPMO_Msk                  (0x01UL << RTC_RAWSTAT_RPMO_Pos)                        /*!< RTC RAWSTAT: RPMO Mask                  */\r
+#define RTC_RAWSTAT_RPYE_Pos                  6                                                       /*!< RTC RAWSTAT: RPYE Position              */\r
+#define RTC_RAWSTAT_RPYE_Msk                  (0x01UL << RTC_RAWSTAT_RPYE_Pos)                        /*!< RTC RAWSTAT: RPYE Mask                  */\r
+#define RTC_RAWSTAT_RAI_Pos                   8                                                       /*!< RTC RAWSTAT: RAI Position               */\r
+#define RTC_RAWSTAT_RAI_Msk                   (0x01UL << RTC_RAWSTAT_RAI_Pos)                         /*!< RTC RAWSTAT: RAI Mask                   */\r
+\r
+/* ----------------------------------  RTC_STSSR  --------------------------------- */\r
+#define RTC_STSSR_SPSE_Pos                    0                                                       /*!< RTC STSSR: SPSE Position                */\r
+#define RTC_STSSR_SPSE_Msk                    (0x01UL << RTC_STSSR_SPSE_Pos)                          /*!< RTC STSSR: SPSE Mask                    */\r
+#define RTC_STSSR_SPMI_Pos                    1                                                       /*!< RTC STSSR: SPMI Position                */\r
+#define RTC_STSSR_SPMI_Msk                    (0x01UL << RTC_STSSR_SPMI_Pos)                          /*!< RTC STSSR: SPMI Mask                    */\r
+#define RTC_STSSR_SPHO_Pos                    2                                                       /*!< RTC STSSR: SPHO Position                */\r
+#define RTC_STSSR_SPHO_Msk                    (0x01UL << RTC_STSSR_SPHO_Pos)                          /*!< RTC STSSR: SPHO Mask                    */\r
+#define RTC_STSSR_SPDA_Pos                    3                                                       /*!< RTC STSSR: SPDA Position                */\r
+#define RTC_STSSR_SPDA_Msk                    (0x01UL << RTC_STSSR_SPDA_Pos)                          /*!< RTC STSSR: SPDA Mask                    */\r
+#define RTC_STSSR_SPMO_Pos                    5                                                       /*!< RTC STSSR: SPMO Position                */\r
+#define RTC_STSSR_SPMO_Msk                    (0x01UL << RTC_STSSR_SPMO_Pos)                          /*!< RTC STSSR: SPMO Mask                    */\r
+#define RTC_STSSR_SPYE_Pos                    6                                                       /*!< RTC STSSR: SPYE Position                */\r
+#define RTC_STSSR_SPYE_Msk                    (0x01UL << RTC_STSSR_SPYE_Pos)                          /*!< RTC STSSR: SPYE Mask                    */\r
+#define RTC_STSSR_SAI_Pos                     8                                                       /*!< RTC STSSR: SAI Position                 */\r
+#define RTC_STSSR_SAI_Msk                     (0x01UL << RTC_STSSR_SAI_Pos)                           /*!< RTC STSSR: SAI Mask                     */\r
+\r
+/* ----------------------------------  RTC_MSKSR  --------------------------------- */\r
+#define RTC_MSKSR_MPSE_Pos                    0                                                       /*!< RTC MSKSR: MPSE Position                */\r
+#define RTC_MSKSR_MPSE_Msk                    (0x01UL << RTC_MSKSR_MPSE_Pos)                          /*!< RTC MSKSR: MPSE Mask                    */\r
+#define RTC_MSKSR_MPMI_Pos                    1                                                       /*!< RTC MSKSR: MPMI Position                */\r
+#define RTC_MSKSR_MPMI_Msk                    (0x01UL << RTC_MSKSR_MPMI_Pos)                          /*!< RTC MSKSR: MPMI Mask                    */\r
+#define RTC_MSKSR_MPHO_Pos                    2                                                       /*!< RTC MSKSR: MPHO Position                */\r
+#define RTC_MSKSR_MPHO_Msk                    (0x01UL << RTC_MSKSR_MPHO_Pos)                          /*!< RTC MSKSR: MPHO Mask                    */\r
+#define RTC_MSKSR_MPDA_Pos                    3                                                       /*!< RTC MSKSR: MPDA Position                */\r
+#define RTC_MSKSR_MPDA_Msk                    (0x01UL << RTC_MSKSR_MPDA_Pos)                          /*!< RTC MSKSR: MPDA Mask                    */\r
+#define RTC_MSKSR_MPMO_Pos                    5                                                       /*!< RTC MSKSR: MPMO Position                */\r
+#define RTC_MSKSR_MPMO_Msk                    (0x01UL << RTC_MSKSR_MPMO_Pos)                          /*!< RTC MSKSR: MPMO Mask                    */\r
+#define RTC_MSKSR_MPYE_Pos                    6                                                       /*!< RTC MSKSR: MPYE Position                */\r
+#define RTC_MSKSR_MPYE_Msk                    (0x01UL << RTC_MSKSR_MPYE_Pos)                          /*!< RTC MSKSR: MPYE Mask                    */\r
+#define RTC_MSKSR_MAI_Pos                     8                                                       /*!< RTC MSKSR: MAI Position                 */\r
+#define RTC_MSKSR_MAI_Msk                     (0x01UL << RTC_MSKSR_MAI_Pos)                           /*!< RTC MSKSR: MAI Mask                     */\r
+\r
+/* ----------------------------------  RTC_CLRSR  --------------------------------- */\r
+#define RTC_CLRSR_RPSE_Pos                    0                                                       /*!< RTC CLRSR: RPSE Position                */\r
+#define RTC_CLRSR_RPSE_Msk                    (0x01UL << RTC_CLRSR_RPSE_Pos)                          /*!< RTC CLRSR: RPSE Mask                    */\r
+#define RTC_CLRSR_RPMI_Pos                    1                                                       /*!< RTC CLRSR: RPMI Position                */\r
+#define RTC_CLRSR_RPMI_Msk                    (0x01UL << RTC_CLRSR_RPMI_Pos)                          /*!< RTC CLRSR: RPMI Mask                    */\r
+#define RTC_CLRSR_RPHO_Pos                    2                                                       /*!< RTC CLRSR: RPHO Position                */\r
+#define RTC_CLRSR_RPHO_Msk                    (0x01UL << RTC_CLRSR_RPHO_Pos)                          /*!< RTC CLRSR: RPHO Mask                    */\r
+#define RTC_CLRSR_RPDA_Pos                    3                                                       /*!< RTC CLRSR: RPDA Position                */\r
+#define RTC_CLRSR_RPDA_Msk                    (0x01UL << RTC_CLRSR_RPDA_Pos)                          /*!< RTC CLRSR: RPDA Mask                    */\r
+#define RTC_CLRSR_RPMO_Pos                    5                                                       /*!< RTC CLRSR: RPMO Position                */\r
+#define RTC_CLRSR_RPMO_Msk                    (0x01UL << RTC_CLRSR_RPMO_Pos)                          /*!< RTC CLRSR: RPMO Mask                    */\r
+#define RTC_CLRSR_RPYE_Pos                    6                                                       /*!< RTC CLRSR: RPYE Position                */\r
+#define RTC_CLRSR_RPYE_Msk                    (0x01UL << RTC_CLRSR_RPYE_Pos)                          /*!< RTC CLRSR: RPYE Mask                    */\r
+#define RTC_CLRSR_RAI_Pos                     8                                                       /*!< RTC CLRSR: RAI Position                 */\r
+#define RTC_CLRSR_RAI_Msk                     (0x01UL << RTC_CLRSR_RAI_Pos)                           /*!< RTC CLRSR: RAI Mask                     */\r
+\r
+/* ----------------------------------  RTC_ATIM0  --------------------------------- */\r
+#define RTC_ATIM0_ASE_Pos                     0                                                       /*!< RTC ATIM0: ASE Position                 */\r
+#define RTC_ATIM0_ASE_Msk                     (0x3fUL << RTC_ATIM0_ASE_Pos)                           /*!< RTC ATIM0: ASE Mask                     */\r
+#define RTC_ATIM0_AMI_Pos                     8                                                       /*!< RTC ATIM0: AMI Position                 */\r
+#define RTC_ATIM0_AMI_Msk                     (0x3fUL << RTC_ATIM0_AMI_Pos)                           /*!< RTC ATIM0: AMI Mask                     */\r
+#define RTC_ATIM0_AHO_Pos                     16                                                      /*!< RTC ATIM0: AHO Position                 */\r
+#define RTC_ATIM0_AHO_Msk                     (0x1fUL << RTC_ATIM0_AHO_Pos)                           /*!< RTC ATIM0: AHO Mask                     */\r
+#define RTC_ATIM0_ADA_Pos                     24                                                      /*!< RTC ATIM0: ADA Position                 */\r
+#define RTC_ATIM0_ADA_Msk                     (0x1fUL << RTC_ATIM0_ADA_Pos)                           /*!< RTC ATIM0: ADA Mask                     */\r
+\r
+/* ----------------------------------  RTC_ATIM1  --------------------------------- */\r
+#define RTC_ATIM1_AMO_Pos                     8                                                       /*!< RTC ATIM1: AMO Position                 */\r
+#define RTC_ATIM1_AMO_Msk                     (0x0fUL << RTC_ATIM1_AMO_Pos)                           /*!< RTC ATIM1: AMO Mask                     */\r
+#define RTC_ATIM1_AYE_Pos                     16                                                      /*!< RTC ATIM1: AYE Position                 */\r
+#define RTC_ATIM1_AYE_Msk                     (0x0000ffffUL << RTC_ATIM1_AYE_Pos)                     /*!< RTC ATIM1: AYE Mask                     */\r
+\r
+/* ----------------------------------  RTC_TIM0  ---------------------------------- */\r
+#define RTC_TIM0_SE_Pos                       0                                                       /*!< RTC TIM0: SE Position                   */\r
+#define RTC_TIM0_SE_Msk                       (0x3fUL << RTC_TIM0_SE_Pos)                             /*!< RTC TIM0: SE Mask                       */\r
+#define RTC_TIM0_MI_Pos                       8                                                       /*!< RTC TIM0: MI Position                   */\r
+#define RTC_TIM0_MI_Msk                       (0x3fUL << RTC_TIM0_MI_Pos)                             /*!< RTC TIM0: MI Mask                       */\r
+#define RTC_TIM0_HO_Pos                       16                                                      /*!< RTC TIM0: HO Position                   */\r
+#define RTC_TIM0_HO_Msk                       (0x1fUL << RTC_TIM0_HO_Pos)                             /*!< RTC TIM0: HO Mask                       */\r
+#define RTC_TIM0_DA_Pos                       24                                                      /*!< RTC TIM0: DA Position                   */\r
+#define RTC_TIM0_DA_Msk                       (0x1fUL << RTC_TIM0_DA_Pos)                             /*!< RTC TIM0: DA Mask                       */\r
+\r
+/* ----------------------------------  RTC_TIM1  ---------------------------------- */\r
+#define RTC_TIM1_DAWE_Pos                     0                                                       /*!< RTC TIM1: DAWE Position                 */\r
+#define RTC_TIM1_DAWE_Msk                     (0x07UL << RTC_TIM1_DAWE_Pos)                           /*!< RTC TIM1: DAWE Mask                     */\r
+#define RTC_TIM1_MO_Pos                       8                                                       /*!< RTC TIM1: MO Position                   */\r
+#define RTC_TIM1_MO_Msk                       (0x0fUL << RTC_TIM1_MO_Pos)                             /*!< RTC TIM1: MO Mask                       */\r
+#define RTC_TIM1_YE_Pos                       16                                                      /*!< RTC TIM1: YE Position                   */\r
+#define RTC_TIM1_YE_Msk                       (0x0000ffffUL << RTC_TIM1_YE_Pos)                       /*!< RTC TIM1: YE Mask                       */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_CLK' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_CLK_CLKSTAT  ------------------------------ */\r
+#define SCU_CLK_CLKSTAT_USBCST_Pos            0                                                       /*!< SCU_CLK CLKSTAT: USBCST Position        */\r
+#define SCU_CLK_CLKSTAT_USBCST_Msk            (0x01UL << SCU_CLK_CLKSTAT_USBCST_Pos)                  /*!< SCU_CLK CLKSTAT: USBCST Mask            */\r
+#define SCU_CLK_CLKSTAT_CCUCST_Pos            4                                                       /*!< SCU_CLK CLKSTAT: CCUCST Position        */\r
+#define SCU_CLK_CLKSTAT_CCUCST_Msk            (0x01UL << SCU_CLK_CLKSTAT_CCUCST_Pos)                  /*!< SCU_CLK CLKSTAT: CCUCST Mask            */\r
+#define SCU_CLK_CLKSTAT_WDTCST_Pos            5                                                       /*!< SCU_CLK CLKSTAT: WDTCST Position        */\r
+#define SCU_CLK_CLKSTAT_WDTCST_Msk            (0x01UL << SCU_CLK_CLKSTAT_WDTCST_Pos)                  /*!< SCU_CLK CLKSTAT: WDTCST Mask            */\r
+\r
+/* -------------------------------  SCU_CLK_CLKSET  ------------------------------- */\r
+#define SCU_CLK_CLKSET_USBCEN_Pos             0                                                       /*!< SCU_CLK CLKSET: USBCEN Position         */\r
+#define SCU_CLK_CLKSET_USBCEN_Msk             (0x01UL << SCU_CLK_CLKSET_USBCEN_Pos)                   /*!< SCU_CLK CLKSET: USBCEN Mask             */\r
+#define SCU_CLK_CLKSET_CCUCEN_Pos             4                                                       /*!< SCU_CLK CLKSET: CCUCEN Position         */\r
+#define SCU_CLK_CLKSET_CCUCEN_Msk             (0x01UL << SCU_CLK_CLKSET_CCUCEN_Pos)                   /*!< SCU_CLK CLKSET: CCUCEN Mask             */\r
+#define SCU_CLK_CLKSET_WDTCEN_Pos             5                                                       /*!< SCU_CLK CLKSET: WDTCEN Position         */\r
+#define SCU_CLK_CLKSET_WDTCEN_Msk             (0x01UL << SCU_CLK_CLKSET_WDTCEN_Pos)                   /*!< SCU_CLK CLKSET: WDTCEN Mask             */\r
+\r
+/* -------------------------------  SCU_CLK_CLKCLR  ------------------------------- */\r
+#define SCU_CLK_CLKCLR_USBCDI_Pos             0                                                       /*!< SCU_CLK CLKCLR: USBCDI Position         */\r
+#define SCU_CLK_CLKCLR_USBCDI_Msk             (0x01UL << SCU_CLK_CLKCLR_USBCDI_Pos)                   /*!< SCU_CLK CLKCLR: USBCDI Mask             */\r
+#define SCU_CLK_CLKCLR_CCUCDI_Pos             4                                                       /*!< SCU_CLK CLKCLR: CCUCDI Position         */\r
+#define SCU_CLK_CLKCLR_CCUCDI_Msk             (0x01UL << SCU_CLK_CLKCLR_CCUCDI_Pos)                   /*!< SCU_CLK CLKCLR: CCUCDI Mask             */\r
+#define SCU_CLK_CLKCLR_WDTCDI_Pos             5                                                       /*!< SCU_CLK CLKCLR: WDTCDI Position         */\r
+#define SCU_CLK_CLKCLR_WDTCDI_Msk             (0x01UL << SCU_CLK_CLKCLR_WDTCDI_Pos)                   /*!< SCU_CLK CLKCLR: WDTCDI Mask             */\r
+\r
+/* ------------------------------  SCU_CLK_SYSCLKCR  ------------------------------ */\r
+#define SCU_CLK_SYSCLKCR_SYSDIV_Pos           0                                                       /*!< SCU_CLK SYSCLKCR: SYSDIV Position       */\r
+#define SCU_CLK_SYSCLKCR_SYSDIV_Msk           (0x000000ffUL << SCU_CLK_SYSCLKCR_SYSDIV_Pos)           /*!< SCU_CLK SYSCLKCR: SYSDIV Mask           */\r
+#define SCU_CLK_SYSCLKCR_SYSSEL_Pos           16                                                      /*!< SCU_CLK SYSCLKCR: SYSSEL Position       */\r
+#define SCU_CLK_SYSCLKCR_SYSSEL_Msk           (0x01UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos)                 /*!< SCU_CLK SYSCLKCR: SYSSEL Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CPUCLKCR  ------------------------------ */\r
+#define SCU_CLK_CPUCLKCR_CPUDIV_Pos           0                                                       /*!< SCU_CLK CPUCLKCR: CPUDIV Position       */\r
+#define SCU_CLK_CPUCLKCR_CPUDIV_Msk           (0x01UL << SCU_CLK_CPUCLKCR_CPUDIV_Pos)                 /*!< SCU_CLK CPUCLKCR: CPUDIV Mask           */\r
+\r
+/* -------------------------------  SCU_CLK_PBCLKCR  ------------------------------ */\r
+#define SCU_CLK_PBCLKCR_PBDIV_Pos             0                                                       /*!< SCU_CLK PBCLKCR: PBDIV Position         */\r
+#define SCU_CLK_PBCLKCR_PBDIV_Msk             (0x01UL << SCU_CLK_PBCLKCR_PBDIV_Pos)                   /*!< SCU_CLK PBCLKCR: PBDIV Mask             */\r
+\r
+/* ------------------------------  SCU_CLK_USBCLKCR  ------------------------------ */\r
+#define SCU_CLK_USBCLKCR_USBDIV_Pos           0                                                       /*!< SCU_CLK USBCLKCR: USBDIV Position       */\r
+#define SCU_CLK_USBCLKCR_USBDIV_Msk           (0x07UL << SCU_CLK_USBCLKCR_USBDIV_Pos)                 /*!< SCU_CLK USBCLKCR: USBDIV Mask           */\r
+#define SCU_CLK_USBCLKCR_USBSEL_Pos           16                                                      /*!< SCU_CLK USBCLKCR: USBSEL Position       */\r
+#define SCU_CLK_USBCLKCR_USBSEL_Msk           (0x01UL << SCU_CLK_USBCLKCR_USBSEL_Pos)                 /*!< SCU_CLK USBCLKCR: USBSEL Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CCUCLKCR  ------------------------------ */\r
+#define SCU_CLK_CCUCLKCR_CCUDIV_Pos           0                                                       /*!< SCU_CLK CCUCLKCR: CCUDIV Position       */\r
+#define SCU_CLK_CCUCLKCR_CCUDIV_Msk           (0x01UL << SCU_CLK_CCUCLKCR_CCUDIV_Pos)                 /*!< SCU_CLK CCUCLKCR: CCUDIV Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_WDTCLKCR  ------------------------------ */\r
+#define SCU_CLK_WDTCLKCR_WDTDIV_Pos           0                                                       /*!< SCU_CLK WDTCLKCR: WDTDIV Position       */\r
+#define SCU_CLK_WDTCLKCR_WDTDIV_Msk           (0x000000ffUL << SCU_CLK_WDTCLKCR_WDTDIV_Pos)           /*!< SCU_CLK WDTCLKCR: WDTDIV Mask           */\r
+#define SCU_CLK_WDTCLKCR_WDTSEL_Pos           16                                                      /*!< SCU_CLK WDTCLKCR: WDTSEL Position       */\r
+#define SCU_CLK_WDTCLKCR_WDTSEL_Msk           (0x03UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos)                 /*!< SCU_CLK WDTCLKCR: WDTSEL Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_EXTCLKCR  ------------------------------ */\r
+#define SCU_CLK_EXTCLKCR_ECKSEL_Pos           0                                                       /*!< SCU_CLK EXTCLKCR: ECKSEL Position       */\r
+#define SCU_CLK_EXTCLKCR_ECKSEL_Msk           (0x07UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos)                 /*!< SCU_CLK EXTCLKCR: ECKSEL Mask           */\r
+#define SCU_CLK_EXTCLKCR_ECKDIV_Pos           16                                                      /*!< SCU_CLK EXTCLKCR: ECKDIV Position       */\r
+#define SCU_CLK_EXTCLKCR_ECKDIV_Msk           (0x000001ffUL << SCU_CLK_EXTCLKCR_ECKDIV_Pos)           /*!< SCU_CLK EXTCLKCR: ECKDIV Mask           */\r
+\r
+/* -----------------------------  SCU_CLK_MLINKCLKCR  ----------------------------- */\r
+#define SCU_CLK_MLINKCLKCR_SYSDIV_Pos         0                                                       /*!< SCU_CLK MLINKCLKCR: SYSDIV Position     */\r
+#define SCU_CLK_MLINKCLKCR_SYSDIV_Msk         (0x000000ffUL << SCU_CLK_MLINKCLKCR_SYSDIV_Pos)         /*!< SCU_CLK MLINKCLKCR: SYSDIV Mask         */\r
+#define SCU_CLK_MLINKCLKCR_SYSSEL_Pos         8                                                       /*!< SCU_CLK MLINKCLKCR: SYSSEL Position     */\r
+#define SCU_CLK_MLINKCLKCR_SYSSEL_Msk         (0x01UL << SCU_CLK_MLINKCLKCR_SYSSEL_Pos)               /*!< SCU_CLK MLINKCLKCR: SYSSEL Mask         */\r
+#define SCU_CLK_MLINKCLKCR_CPUDIV_Pos         10                                                      /*!< SCU_CLK MLINKCLKCR: CPUDIV Position     */\r
+#define SCU_CLK_MLINKCLKCR_CPUDIV_Msk         (0x01UL << SCU_CLK_MLINKCLKCR_CPUDIV_Pos)               /*!< SCU_CLK MLINKCLKCR: CPUDIV Mask         */\r
+#define SCU_CLK_MLINKCLKCR_PBDIV_Pos          12                                                      /*!< SCU_CLK MLINKCLKCR: PBDIV Position      */\r
+#define SCU_CLK_MLINKCLKCR_PBDIV_Msk          (0x01UL << SCU_CLK_MLINKCLKCR_PBDIV_Pos)                /*!< SCU_CLK MLINKCLKCR: PBDIV Mask          */\r
+#define SCU_CLK_MLINKCLKCR_CCUDIV_Pos         14                                                      /*!< SCU_CLK MLINKCLKCR: CCUDIV Position     */\r
+#define SCU_CLK_MLINKCLKCR_CCUDIV_Msk         (0x01UL << SCU_CLK_MLINKCLKCR_CCUDIV_Pos)               /*!< SCU_CLK MLINKCLKCR: CCUDIV Mask         */\r
+#define SCU_CLK_MLINKCLKCR_WDTDIV_Pos         16                                                      /*!< SCU_CLK MLINKCLKCR: WDTDIV Position     */\r
+#define SCU_CLK_MLINKCLKCR_WDTDIV_Msk         (0x000000ffUL << SCU_CLK_MLINKCLKCR_WDTDIV_Pos)         /*!< SCU_CLK MLINKCLKCR: WDTDIV Mask         */\r
+#define SCU_CLK_MLINKCLKCR_WDTSEL_Pos         24                                                      /*!< SCU_CLK MLINKCLKCR: WDTSEL Position     */\r
+#define SCU_CLK_MLINKCLKCR_WDTSEL_Msk         (0x03UL << SCU_CLK_MLINKCLKCR_WDTSEL_Pos)               /*!< SCU_CLK MLINKCLKCR: WDTSEL Mask         */\r
+\r
+/* -------------------------------  SCU_CLK_SLEEPCR  ------------------------------ */\r
+#define SCU_CLK_SLEEPCR_SYSSEL_Pos            0                                                       /*!< SCU_CLK SLEEPCR: SYSSEL Position        */\r
+#define SCU_CLK_SLEEPCR_SYSSEL_Msk            (0x01UL << SCU_CLK_SLEEPCR_SYSSEL_Pos)                  /*!< SCU_CLK SLEEPCR: SYSSEL Mask            */\r
+#define SCU_CLK_SLEEPCR_USBCR_Pos             16                                                      /*!< SCU_CLK SLEEPCR: USBCR Position         */\r
+#define SCU_CLK_SLEEPCR_USBCR_Msk             (0x01UL << SCU_CLK_SLEEPCR_USBCR_Pos)                   /*!< SCU_CLK SLEEPCR: USBCR Mask             */\r
+#define SCU_CLK_SLEEPCR_CCUCR_Pos             20                                                      /*!< SCU_CLK SLEEPCR: CCUCR Position         */\r
+#define SCU_CLK_SLEEPCR_CCUCR_Msk             (0x01UL << SCU_CLK_SLEEPCR_CCUCR_Pos)                   /*!< SCU_CLK SLEEPCR: CCUCR Mask             */\r
+#define SCU_CLK_SLEEPCR_WDTCR_Pos             21                                                      /*!< SCU_CLK SLEEPCR: WDTCR Position         */\r
+#define SCU_CLK_SLEEPCR_WDTCR_Msk             (0x01UL << SCU_CLK_SLEEPCR_WDTCR_Pos)                   /*!< SCU_CLK SLEEPCR: WDTCR Mask             */\r
+\r
+/* ------------------------------  SCU_CLK_DSLEEPCR  ------------------------------ */\r
+#define SCU_CLK_DSLEEPCR_SYSSEL_Pos           0                                                       /*!< SCU_CLK DSLEEPCR: SYSSEL Position       */\r
+#define SCU_CLK_DSLEEPCR_SYSSEL_Msk           (0x01UL << SCU_CLK_DSLEEPCR_SYSSEL_Pos)                 /*!< SCU_CLK DSLEEPCR: SYSSEL Mask           */\r
+#define SCU_CLK_DSLEEPCR_FPDN_Pos             11                                                      /*!< SCU_CLK DSLEEPCR: FPDN Position         */\r
+#define SCU_CLK_DSLEEPCR_FPDN_Msk             (0x01UL << SCU_CLK_DSLEEPCR_FPDN_Pos)                   /*!< SCU_CLK DSLEEPCR: FPDN Mask             */\r
+#define SCU_CLK_DSLEEPCR_PLLPDN_Pos           12                                                      /*!< SCU_CLK DSLEEPCR: PLLPDN Position       */\r
+#define SCU_CLK_DSLEEPCR_PLLPDN_Msk           (0x01UL << SCU_CLK_DSLEEPCR_PLLPDN_Pos)                 /*!< SCU_CLK DSLEEPCR: PLLPDN Mask           */\r
+#define SCU_CLK_DSLEEPCR_VCOPDN_Pos           13                                                      /*!< SCU_CLK DSLEEPCR: VCOPDN Position       */\r
+#define SCU_CLK_DSLEEPCR_VCOPDN_Msk           (0x01UL << SCU_CLK_DSLEEPCR_VCOPDN_Pos)                 /*!< SCU_CLK DSLEEPCR: VCOPDN Mask           */\r
+#define SCU_CLK_DSLEEPCR_USBCR_Pos            16                                                      /*!< SCU_CLK DSLEEPCR: USBCR Position        */\r
+#define SCU_CLK_DSLEEPCR_USBCR_Msk            (0x01UL << SCU_CLK_DSLEEPCR_USBCR_Pos)                  /*!< SCU_CLK DSLEEPCR: USBCR Mask            */\r
+#define SCU_CLK_DSLEEPCR_CCUCR_Pos            20                                                      /*!< SCU_CLK DSLEEPCR: CCUCR Position        */\r
+#define SCU_CLK_DSLEEPCR_CCUCR_Msk            (0x01UL << SCU_CLK_DSLEEPCR_CCUCR_Pos)                  /*!< SCU_CLK DSLEEPCR: CCUCR Mask            */\r
+#define SCU_CLK_DSLEEPCR_WDTCR_Pos            21                                                      /*!< SCU_CLK DSLEEPCR: WDTCR Position        */\r
+#define SCU_CLK_DSLEEPCR_WDTCR_Msk            (0x01UL << SCU_CLK_DSLEEPCR_WDTCR_Pos)                  /*!< SCU_CLK DSLEEPCR: WDTCR Mask            */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSTAT0  ----------------------------- */\r
+#define SCU_CLK_CGATSTAT0_VADC_Pos            0                                                       /*!< SCU_CLK CGATSTAT0: VADC Position        */\r
+#define SCU_CLK_CGATSTAT0_VADC_Msk            (0x01UL << SCU_CLK_CGATSTAT0_VADC_Pos)                  /*!< SCU_CLK CGATSTAT0: VADC Mask            */\r
+#define SCU_CLK_CGATSTAT0_CCU40_Pos           2                                                       /*!< SCU_CLK CGATSTAT0: CCU40 Position       */\r
+#define SCU_CLK_CGATSTAT0_CCU40_Msk           (0x01UL << SCU_CLK_CGATSTAT0_CCU40_Pos)                 /*!< SCU_CLK CGATSTAT0: CCU40 Mask           */\r
+#define SCU_CLK_CGATSTAT0_CCU41_Pos           3                                                       /*!< SCU_CLK CGATSTAT0: CCU41 Position       */\r
+#define SCU_CLK_CGATSTAT0_CCU41_Msk           (0x01UL << SCU_CLK_CGATSTAT0_CCU41_Pos)                 /*!< SCU_CLK CGATSTAT0: CCU41 Mask           */\r
+#define SCU_CLK_CGATSTAT0_CCU80_Pos           7                                                       /*!< SCU_CLK CGATSTAT0: CCU80 Position       */\r
+#define SCU_CLK_CGATSTAT0_CCU80_Msk           (0x01UL << SCU_CLK_CGATSTAT0_CCU80_Pos)                 /*!< SCU_CLK CGATSTAT0: CCU80 Mask           */\r
+#define SCU_CLK_CGATSTAT0_POSIF0_Pos          9                                                       /*!< SCU_CLK CGATSTAT0: POSIF0 Position      */\r
+#define SCU_CLK_CGATSTAT0_POSIF0_Msk          (0x01UL << SCU_CLK_CGATSTAT0_POSIF0_Pos)                /*!< SCU_CLK CGATSTAT0: POSIF0 Mask          */\r
+#define SCU_CLK_CGATSTAT0_USIC0_Pos           11                                                      /*!< SCU_CLK CGATSTAT0: USIC0 Position       */\r
+#define SCU_CLK_CGATSTAT0_USIC0_Msk           (0x01UL << SCU_CLK_CGATSTAT0_USIC0_Pos)                 /*!< SCU_CLK CGATSTAT0: USIC0 Mask           */\r
+#define SCU_CLK_CGATSTAT0_ERU1_Pos            16                                                      /*!< SCU_CLK CGATSTAT0: ERU1 Position        */\r
+#define SCU_CLK_CGATSTAT0_ERU1_Msk            (0x01UL << SCU_CLK_CGATSTAT0_ERU1_Pos)                  /*!< SCU_CLK CGATSTAT0: ERU1 Mask            */\r
+#define SCU_CLK_CGATSTAT0_HRPWM0_Pos          23                                                      /*!< SCU_CLK CGATSTAT0: HRPWM0 Position      */\r
+#define SCU_CLK_CGATSTAT0_HRPWM0_Msk          (0x01UL << SCU_CLK_CGATSTAT0_HRPWM0_Pos)                /*!< SCU_CLK CGATSTAT0: HRPWM0 Mask          */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSET0  ------------------------------ */\r
+#define SCU_CLK_CGATSET0_VADC_Pos             0                                                       /*!< SCU_CLK CGATSET0: VADC Position         */\r
+#define SCU_CLK_CGATSET0_VADC_Msk             (0x01UL << SCU_CLK_CGATSET0_VADC_Pos)                   /*!< SCU_CLK CGATSET0: VADC Mask             */\r
+#define SCU_CLK_CGATSET0_CCU40_Pos            2                                                       /*!< SCU_CLK CGATSET0: CCU40 Position        */\r
+#define SCU_CLK_CGATSET0_CCU40_Msk            (0x01UL << SCU_CLK_CGATSET0_CCU40_Pos)                  /*!< SCU_CLK CGATSET0: CCU40 Mask            */\r
+#define SCU_CLK_CGATSET0_CCU41_Pos            3                                                       /*!< SCU_CLK CGATSET0: CCU41 Position        */\r
+#define SCU_CLK_CGATSET0_CCU41_Msk            (0x01UL << SCU_CLK_CGATSET0_CCU41_Pos)                  /*!< SCU_CLK CGATSET0: CCU41 Mask            */\r
+#define SCU_CLK_CGATSET0_CCU80_Pos            7                                                       /*!< SCU_CLK CGATSET0: CCU80 Position        */\r
+#define SCU_CLK_CGATSET0_CCU80_Msk            (0x01UL << SCU_CLK_CGATSET0_CCU80_Pos)                  /*!< SCU_CLK CGATSET0: CCU80 Mask            */\r
+#define SCU_CLK_CGATSET0_POSIF0_Pos           9                                                       /*!< SCU_CLK CGATSET0: POSIF0 Position       */\r
+#define SCU_CLK_CGATSET0_POSIF0_Msk           (0x01UL << SCU_CLK_CGATSET0_POSIF0_Pos)                 /*!< SCU_CLK CGATSET0: POSIF0 Mask           */\r
+#define SCU_CLK_CGATSET0_USIC0_Pos            11                                                      /*!< SCU_CLK CGATSET0: USIC0 Position        */\r
+#define SCU_CLK_CGATSET0_USIC0_Msk            (0x01UL << SCU_CLK_CGATSET0_USIC0_Pos)                  /*!< SCU_CLK CGATSET0: USIC0 Mask            */\r
+#define SCU_CLK_CGATSET0_ERU1_Pos             16                                                      /*!< SCU_CLK CGATSET0: ERU1 Position         */\r
+#define SCU_CLK_CGATSET0_ERU1_Msk             (0x01UL << SCU_CLK_CGATSET0_ERU1_Pos)                   /*!< SCU_CLK CGATSET0: ERU1 Mask             */\r
+#define SCU_CLK_CGATSET0_HRPWM0_Pos           23                                                      /*!< SCU_CLK CGATSET0: HRPWM0 Position       */\r
+#define SCU_CLK_CGATSET0_HRPWM0_Msk           (0x01UL << SCU_CLK_CGATSET0_HRPWM0_Pos)                 /*!< SCU_CLK CGATSET0: HRPWM0 Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CGATCLR0  ------------------------------ */\r
+#define SCU_CLK_CGATCLR0_VADC_Pos             0                                                       /*!< SCU_CLK CGATCLR0: VADC Position         */\r
+#define SCU_CLK_CGATCLR0_VADC_Msk             (0x01UL << SCU_CLK_CGATCLR0_VADC_Pos)                   /*!< SCU_CLK CGATCLR0: VADC Mask             */\r
+#define SCU_CLK_CGATCLR0_CCU40_Pos            2                                                       /*!< SCU_CLK CGATCLR0: CCU40 Position        */\r
+#define SCU_CLK_CGATCLR0_CCU40_Msk            (0x01UL << SCU_CLK_CGATCLR0_CCU40_Pos)                  /*!< SCU_CLK CGATCLR0: CCU40 Mask            */\r
+#define SCU_CLK_CGATCLR0_CCU41_Pos            3                                                       /*!< SCU_CLK CGATCLR0: CCU41 Position        */\r
+#define SCU_CLK_CGATCLR0_CCU41_Msk            (0x01UL << SCU_CLK_CGATCLR0_CCU41_Pos)                  /*!< SCU_CLK CGATCLR0: CCU41 Mask            */\r
+#define SCU_CLK_CGATCLR0_CCU80_Pos            7                                                       /*!< SCU_CLK CGATCLR0: CCU80 Position        */\r
+#define SCU_CLK_CGATCLR0_CCU80_Msk            (0x01UL << SCU_CLK_CGATCLR0_CCU80_Pos)                  /*!< SCU_CLK CGATCLR0: CCU80 Mask            */\r
+#define SCU_CLK_CGATCLR0_POSIF0_Pos           9                                                       /*!< SCU_CLK CGATCLR0: POSIF0 Position       */\r
+#define SCU_CLK_CGATCLR0_POSIF0_Msk           (0x01UL << SCU_CLK_CGATCLR0_POSIF0_Pos)                 /*!< SCU_CLK CGATCLR0: POSIF0 Mask           */\r
+#define SCU_CLK_CGATCLR0_USIC0_Pos            11                                                      /*!< SCU_CLK CGATCLR0: USIC0 Position        */\r
+#define SCU_CLK_CGATCLR0_USIC0_Msk            (0x01UL << SCU_CLK_CGATCLR0_USIC0_Pos)                  /*!< SCU_CLK CGATCLR0: USIC0 Mask            */\r
+#define SCU_CLK_CGATCLR0_ERU1_Pos             16                                                      /*!< SCU_CLK CGATCLR0: ERU1 Position         */\r
+#define SCU_CLK_CGATCLR0_ERU1_Msk             (0x01UL << SCU_CLK_CGATCLR0_ERU1_Pos)                   /*!< SCU_CLK CGATCLR0: ERU1 Mask             */\r
+#define SCU_CLK_CGATCLR0_HRPWM0_Pos           23                                                      /*!< SCU_CLK CGATCLR0: HRPWM0 Position       */\r
+#define SCU_CLK_CGATCLR0_HRPWM0_Msk           (0x01UL << SCU_CLK_CGATCLR0_HRPWM0_Pos)                 /*!< SCU_CLK CGATCLR0: HRPWM0 Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSTAT1  ----------------------------- */\r
+#define SCU_CLK_CGATSTAT1_LEDTSCU0_Pos        3                                                       /*!< SCU_CLK CGATSTAT1: LEDTSCU0 Position    */\r
+#define SCU_CLK_CGATSTAT1_LEDTSCU0_Msk        (0x01UL << SCU_CLK_CGATSTAT1_LEDTSCU0_Pos)              /*!< SCU_CLK CGATSTAT1: LEDTSCU0 Mask        */\r
+#define SCU_CLK_CGATSTAT1_MCAN0_Pos           4                                                       /*!< SCU_CLK CGATSTAT1: MCAN0 Position       */\r
+#define SCU_CLK_CGATSTAT1_MCAN0_Msk           (0x01UL << SCU_CLK_CGATSTAT1_MCAN0_Pos)                 /*!< SCU_CLK CGATSTAT1: MCAN0 Mask           */\r
+#define SCU_CLK_CGATSTAT1_DAC_Pos             5                                                       /*!< SCU_CLK CGATSTAT1: DAC Position         */\r
+#define SCU_CLK_CGATSTAT1_DAC_Msk             (0x01UL << SCU_CLK_CGATSTAT1_DAC_Pos)                   /*!< SCU_CLK CGATSTAT1: DAC Mask             */\r
+#define SCU_CLK_CGATSTAT1_USIC1_Pos           7                                                       /*!< SCU_CLK CGATSTAT1: USIC1 Position       */\r
+#define SCU_CLK_CGATSTAT1_USIC1_Msk           (0x01UL << SCU_CLK_CGATSTAT1_USIC1_Pos)                 /*!< SCU_CLK CGATSTAT1: USIC1 Mask           */\r
+#define SCU_CLK_CGATSTAT1_PPORTS_Pos          9                                                       /*!< SCU_CLK CGATSTAT1: PPORTS Position      */\r
+#define SCU_CLK_CGATSTAT1_PPORTS_Msk          (0x01UL << SCU_CLK_CGATSTAT1_PPORTS_Pos)                /*!< SCU_CLK CGATSTAT1: PPORTS Mask          */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSET1  ------------------------------ */\r
+#define SCU_CLK_CGATSET1_LEDTSCU0_Pos         3                                                       /*!< SCU_CLK CGATSET1: LEDTSCU0 Position     */\r
+#define SCU_CLK_CGATSET1_LEDTSCU0_Msk         (0x01UL << SCU_CLK_CGATSET1_LEDTSCU0_Pos)               /*!< SCU_CLK CGATSET1: LEDTSCU0 Mask         */\r
+#define SCU_CLK_CGATSET1_MCAN0_Pos            4                                                       /*!< SCU_CLK CGATSET1: MCAN0 Position        */\r
+#define SCU_CLK_CGATSET1_MCAN0_Msk            (0x01UL << SCU_CLK_CGATSET1_MCAN0_Pos)                  /*!< SCU_CLK CGATSET1: MCAN0 Mask            */\r
+#define SCU_CLK_CGATSET1_DAC_Pos              5                                                       /*!< SCU_CLK CGATSET1: DAC Position          */\r
+#define SCU_CLK_CGATSET1_DAC_Msk              (0x01UL << SCU_CLK_CGATSET1_DAC_Pos)                    /*!< SCU_CLK CGATSET1: DAC Mask              */\r
+#define SCU_CLK_CGATSET1_USIC1_Pos            7                                                       /*!< SCU_CLK CGATSET1: USIC1 Position        */\r
+#define SCU_CLK_CGATSET1_USIC1_Msk            (0x01UL << SCU_CLK_CGATSET1_USIC1_Pos)                  /*!< SCU_CLK CGATSET1: USIC1 Mask            */\r
+#define SCU_CLK_CGATSET1_PPORTS_Pos           9                                                       /*!< SCU_CLK CGATSET1: PPORTS Position       */\r
+#define SCU_CLK_CGATSET1_PPORTS_Msk           (0x01UL << SCU_CLK_CGATSET1_PPORTS_Pos)                 /*!< SCU_CLK CGATSET1: PPORTS Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CGATCLR1  ------------------------------ */\r
+#define SCU_CLK_CGATCLR1_LEDTSCU0_Pos         3                                                       /*!< SCU_CLK CGATCLR1: LEDTSCU0 Position     */\r
+#define SCU_CLK_CGATCLR1_LEDTSCU0_Msk         (0x01UL << SCU_CLK_CGATCLR1_LEDTSCU0_Pos)               /*!< SCU_CLK CGATCLR1: LEDTSCU0 Mask         */\r
+#define SCU_CLK_CGATCLR1_MCAN0_Pos            4                                                       /*!< SCU_CLK CGATCLR1: MCAN0 Position        */\r
+#define SCU_CLK_CGATCLR1_MCAN0_Msk            (0x01UL << SCU_CLK_CGATCLR1_MCAN0_Pos)                  /*!< SCU_CLK CGATCLR1: MCAN0 Mask            */\r
+#define SCU_CLK_CGATCLR1_DAC_Pos              5                                                       /*!< SCU_CLK CGATCLR1: DAC Position          */\r
+#define SCU_CLK_CGATCLR1_DAC_Msk              (0x01UL << SCU_CLK_CGATCLR1_DAC_Pos)                    /*!< SCU_CLK CGATCLR1: DAC Mask              */\r
+#define SCU_CLK_CGATCLR1_USIC1_Pos            7                                                       /*!< SCU_CLK CGATCLR1: USIC1 Position        */\r
+#define SCU_CLK_CGATCLR1_USIC1_Msk            (0x01UL << SCU_CLK_CGATCLR1_USIC1_Pos)                  /*!< SCU_CLK CGATCLR1: USIC1 Mask            */\r
+#define SCU_CLK_CGATCLR1_PPORTS_Pos           9                                                       /*!< SCU_CLK CGATCLR1: PPORTS Position       */\r
+#define SCU_CLK_CGATCLR1_PPORTS_Msk           (0x01UL << SCU_CLK_CGATCLR1_PPORTS_Pos)                 /*!< SCU_CLK CGATCLR1: PPORTS Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSTAT2  ----------------------------- */\r
+#define SCU_CLK_CGATSTAT2_WDT_Pos             1                                                       /*!< SCU_CLK CGATSTAT2: WDT Position         */\r
+#define SCU_CLK_CGATSTAT2_WDT_Msk             (0x01UL << SCU_CLK_CGATSTAT2_WDT_Pos)                   /*!< SCU_CLK CGATSTAT2: WDT Mask             */\r
+#define SCU_CLK_CGATSTAT2_DMA0_Pos            4                                                       /*!< SCU_CLK CGATSTAT2: DMA0 Position        */\r
+#define SCU_CLK_CGATSTAT2_DMA0_Msk            (0x01UL << SCU_CLK_CGATSTAT2_DMA0_Pos)                  /*!< SCU_CLK CGATSTAT2: DMA0 Mask            */\r
+#define SCU_CLK_CGATSTAT2_FCE_Pos             6                                                       /*!< SCU_CLK CGATSTAT2: FCE Position         */\r
+#define SCU_CLK_CGATSTAT2_FCE_Msk             (0x01UL << SCU_CLK_CGATSTAT2_FCE_Pos)                   /*!< SCU_CLK CGATSTAT2: FCE Mask             */\r
+#define SCU_CLK_CGATSTAT2_USB_Pos             7                                                       /*!< SCU_CLK CGATSTAT2: USB Position         */\r
+#define SCU_CLK_CGATSTAT2_USB_Msk             (0x01UL << SCU_CLK_CGATSTAT2_USB_Pos)                   /*!< SCU_CLK CGATSTAT2: USB Mask             */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSET2  ------------------------------ */\r
+#define SCU_CLK_CGATSET2_WDT_Pos              1                                                       /*!< SCU_CLK CGATSET2: WDT Position          */\r
+#define SCU_CLK_CGATSET2_WDT_Msk              (0x01UL << SCU_CLK_CGATSET2_WDT_Pos)                    /*!< SCU_CLK CGATSET2: WDT Mask              */\r
+#define SCU_CLK_CGATSET2_DMA0_Pos             4                                                       /*!< SCU_CLK CGATSET2: DMA0 Position         */\r
+#define SCU_CLK_CGATSET2_DMA0_Msk             (0x01UL << SCU_CLK_CGATSET2_DMA0_Pos)                   /*!< SCU_CLK CGATSET2: DMA0 Mask             */\r
+#define SCU_CLK_CGATSET2_FCE_Pos              6                                                       /*!< SCU_CLK CGATSET2: FCE Position          */\r
+#define SCU_CLK_CGATSET2_FCE_Msk              (0x01UL << SCU_CLK_CGATSET2_FCE_Pos)                    /*!< SCU_CLK CGATSET2: FCE Mask              */\r
+#define SCU_CLK_CGATSET2_USB_Pos              7                                                       /*!< SCU_CLK CGATSET2: USB Position          */\r
+#define SCU_CLK_CGATSET2_USB_Msk              (0x01UL << SCU_CLK_CGATSET2_USB_Pos)                    /*!< SCU_CLK CGATSET2: USB Mask              */\r
+\r
+/* ------------------------------  SCU_CLK_CGATCLR2  ------------------------------ */\r
+#define SCU_CLK_CGATCLR2_WDT_Pos              1                                                       /*!< SCU_CLK CGATCLR2: WDT Position          */\r
+#define SCU_CLK_CGATCLR2_WDT_Msk              (0x01UL << SCU_CLK_CGATCLR2_WDT_Pos)                    /*!< SCU_CLK CGATCLR2: WDT Mask              */\r
+#define SCU_CLK_CGATCLR2_DMA0_Pos             4                                                       /*!< SCU_CLK CGATCLR2: DMA0 Position         */\r
+#define SCU_CLK_CGATCLR2_DMA0_Msk             (0x01UL << SCU_CLK_CGATCLR2_DMA0_Pos)                   /*!< SCU_CLK CGATCLR2: DMA0 Mask             */\r
+#define SCU_CLK_CGATCLR2_FCE_Pos              6                                                       /*!< SCU_CLK CGATCLR2: FCE Position          */\r
+#define SCU_CLK_CGATCLR2_FCE_Msk              (0x01UL << SCU_CLK_CGATCLR2_FCE_Pos)                    /*!< SCU_CLK CGATCLR2: FCE Mask              */\r
+#define SCU_CLK_CGATCLR2_USB_Pos              7                                                       /*!< SCU_CLK CGATCLR2: USB Position          */\r
+#define SCU_CLK_CGATCLR2_USB_Msk              (0x01UL << SCU_CLK_CGATCLR2_USB_Pos)                    /*!< SCU_CLK CGATCLR2: USB Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_OSC' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_OSC_OSCHPSTAT  ----------------------------- */\r
+#define SCU_OSC_OSCHPSTAT_X1D_Pos             0                                                       /*!< SCU_OSC OSCHPSTAT: X1D Position         */\r
+#define SCU_OSC_OSCHPSTAT_X1D_Msk             (0x01UL << SCU_OSC_OSCHPSTAT_X1D_Pos)                   /*!< SCU_OSC OSCHPSTAT: X1D Mask             */\r
+\r
+/* ------------------------------  SCU_OSC_OSCHPCTRL  ----------------------------- */\r
+#define SCU_OSC_OSCHPCTRL_X1DEN_Pos           0                                                       /*!< SCU_OSC OSCHPCTRL: X1DEN Position       */\r
+#define SCU_OSC_OSCHPCTRL_X1DEN_Msk           (0x01UL << SCU_OSC_OSCHPCTRL_X1DEN_Pos)                 /*!< SCU_OSC OSCHPCTRL: X1DEN Mask           */\r
+#define SCU_OSC_OSCHPCTRL_SHBY_Pos            1                                                       /*!< SCU_OSC OSCHPCTRL: SHBY Position        */\r
+#define SCU_OSC_OSCHPCTRL_SHBY_Msk            (0x01UL << SCU_OSC_OSCHPCTRL_SHBY_Pos)                  /*!< SCU_OSC OSCHPCTRL: SHBY Mask            */\r
+#define SCU_OSC_OSCHPCTRL_MODE_Pos            4                                                       /*!< SCU_OSC OSCHPCTRL: MODE Position        */\r
+#define SCU_OSC_OSCHPCTRL_MODE_Msk            (0x03UL << SCU_OSC_OSCHPCTRL_MODE_Pos)                  /*!< SCU_OSC OSCHPCTRL: MODE Mask            */\r
+#define SCU_OSC_OSCHPCTRL_OSCVAL_Pos          16                                                      /*!< SCU_OSC OSCHPCTRL: OSCVAL Position      */\r
+#define SCU_OSC_OSCHPCTRL_OSCVAL_Msk          (0x1fUL << SCU_OSC_OSCHPCTRL_OSCVAL_Pos)                /*!< SCU_OSC OSCHPCTRL: OSCVAL Mask          */\r
+\r
+/* -----------------------------  SCU_OSC_CLKCALCONST  ---------------------------- */\r
+#define SCU_OSC_CLKCALCONST_CALIBCONST_Pos    0                                                       /*!< SCU_OSC CLKCALCONST: CALIBCONST Position */\r
+#define SCU_OSC_CLKCALCONST_CALIBCONST_Msk    (0x0fUL << SCU_OSC_CLKCALCONST_CALIBCONST_Pos)          /*!< SCU_OSC CLKCALCONST: CALIBCONST Mask    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_PLL' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_PLL_PLLSTAT  ------------------------------ */\r
+#define SCU_PLL_PLLSTAT_VCOBYST_Pos           0                                                       /*!< SCU_PLL PLLSTAT: VCOBYST Position       */\r
+#define SCU_PLL_PLLSTAT_VCOBYST_Msk           (0x01UL << SCU_PLL_PLLSTAT_VCOBYST_Pos)                 /*!< SCU_PLL PLLSTAT: VCOBYST Mask           */\r
+#define SCU_PLL_PLLSTAT_PWDSTAT_Pos           1                                                       /*!< SCU_PLL PLLSTAT: PWDSTAT Position       */\r
+#define SCU_PLL_PLLSTAT_PWDSTAT_Msk           (0x01UL << SCU_PLL_PLLSTAT_PWDSTAT_Pos)                 /*!< SCU_PLL PLLSTAT: PWDSTAT Mask           */\r
+#define SCU_PLL_PLLSTAT_VCOLOCK_Pos           2                                                       /*!< SCU_PLL PLLSTAT: VCOLOCK Position       */\r
+#define SCU_PLL_PLLSTAT_VCOLOCK_Msk           (0x01UL << SCU_PLL_PLLSTAT_VCOLOCK_Pos)                 /*!< SCU_PLL PLLSTAT: VCOLOCK Mask           */\r
+#define SCU_PLL_PLLSTAT_K1RDY_Pos             4                                                       /*!< SCU_PLL PLLSTAT: K1RDY Position         */\r
+#define SCU_PLL_PLLSTAT_K1RDY_Msk             (0x01UL << SCU_PLL_PLLSTAT_K1RDY_Pos)                   /*!< SCU_PLL PLLSTAT: K1RDY Mask             */\r
+#define SCU_PLL_PLLSTAT_K2RDY_Pos             5                                                       /*!< SCU_PLL PLLSTAT: K2RDY Position         */\r
+#define SCU_PLL_PLLSTAT_K2RDY_Msk             (0x01UL << SCU_PLL_PLLSTAT_K2RDY_Pos)                   /*!< SCU_PLL PLLSTAT: K2RDY Mask             */\r
+#define SCU_PLL_PLLSTAT_BY_Pos                6                                                       /*!< SCU_PLL PLLSTAT: BY Position            */\r
+#define SCU_PLL_PLLSTAT_BY_Msk                (0x01UL << SCU_PLL_PLLSTAT_BY_Pos)                      /*!< SCU_PLL PLLSTAT: BY Mask                */\r
+#define SCU_PLL_PLLSTAT_PLLLV_Pos             7                                                       /*!< SCU_PLL PLLSTAT: PLLLV Position         */\r
+#define SCU_PLL_PLLSTAT_PLLLV_Msk             (0x01UL << SCU_PLL_PLLSTAT_PLLLV_Pos)                   /*!< SCU_PLL PLLSTAT: PLLLV Mask             */\r
+#define SCU_PLL_PLLSTAT_PLLHV_Pos             8                                                       /*!< SCU_PLL PLLSTAT: PLLHV Position         */\r
+#define SCU_PLL_PLLSTAT_PLLHV_Msk             (0x01UL << SCU_PLL_PLLSTAT_PLLHV_Pos)                   /*!< SCU_PLL PLLSTAT: PLLHV Mask             */\r
+#define SCU_PLL_PLLSTAT_PLLSP_Pos             9                                                       /*!< SCU_PLL PLLSTAT: PLLSP Position         */\r
+#define SCU_PLL_PLLSTAT_PLLSP_Msk             (0x01UL << SCU_PLL_PLLSTAT_PLLSP_Pos)                   /*!< SCU_PLL PLLSTAT: PLLSP Mask             */\r
+\r
+/* -------------------------------  SCU_PLL_PLLCON0  ------------------------------ */\r
+#define SCU_PLL_PLLCON0_VCOBYP_Pos            0                                                       /*!< SCU_PLL PLLCON0: VCOBYP Position        */\r
+#define SCU_PLL_PLLCON0_VCOBYP_Msk            (0x01UL << SCU_PLL_PLLCON0_VCOBYP_Pos)                  /*!< SCU_PLL PLLCON0: VCOBYP Mask            */\r
+#define SCU_PLL_PLLCON0_VCOPWD_Pos            1                                                       /*!< SCU_PLL PLLCON0: VCOPWD Position        */\r
+#define SCU_PLL_PLLCON0_VCOPWD_Msk            (0x01UL << SCU_PLL_PLLCON0_VCOPWD_Pos)                  /*!< SCU_PLL PLLCON0: VCOPWD Mask            */\r
+#define SCU_PLL_PLLCON0_VCOTR_Pos             2                                                       /*!< SCU_PLL PLLCON0: VCOTR Position         */\r
+#define SCU_PLL_PLLCON0_VCOTR_Msk             (0x01UL << SCU_PLL_PLLCON0_VCOTR_Pos)                   /*!< SCU_PLL PLLCON0: VCOTR Mask             */\r
+#define SCU_PLL_PLLCON0_FINDIS_Pos            4                                                       /*!< SCU_PLL PLLCON0: FINDIS Position        */\r
+#define SCU_PLL_PLLCON0_FINDIS_Msk            (0x01UL << SCU_PLL_PLLCON0_FINDIS_Pos)                  /*!< SCU_PLL PLLCON0: FINDIS Mask            */\r
+#define SCU_PLL_PLLCON0_OSCDISCDIS_Pos        6                                                       /*!< SCU_PLL PLLCON0: OSCDISCDIS Position    */\r
+#define SCU_PLL_PLLCON0_OSCDISCDIS_Msk        (0x01UL << SCU_PLL_PLLCON0_OSCDISCDIS_Pos)              /*!< SCU_PLL PLLCON0: OSCDISCDIS Mask        */\r
+#define SCU_PLL_PLLCON0_PLLPWD_Pos            16                                                      /*!< SCU_PLL PLLCON0: PLLPWD Position        */\r
+#define SCU_PLL_PLLCON0_PLLPWD_Msk            (0x01UL << SCU_PLL_PLLCON0_PLLPWD_Pos)                  /*!< SCU_PLL PLLCON0: PLLPWD Mask            */\r
+#define SCU_PLL_PLLCON0_OSCRES_Pos            17                                                      /*!< SCU_PLL PLLCON0: OSCRES Position        */\r
+#define SCU_PLL_PLLCON0_OSCRES_Msk            (0x01UL << SCU_PLL_PLLCON0_OSCRES_Pos)                  /*!< SCU_PLL PLLCON0: OSCRES Mask            */\r
+#define SCU_PLL_PLLCON0_RESLD_Pos             18                                                      /*!< SCU_PLL PLLCON0: RESLD Position         */\r
+#define SCU_PLL_PLLCON0_RESLD_Msk             (0x01UL << SCU_PLL_PLLCON0_RESLD_Pos)                   /*!< SCU_PLL PLLCON0: RESLD Mask             */\r
+#define SCU_PLL_PLLCON0_AOTREN_Pos            19                                                      /*!< SCU_PLL PLLCON0: AOTREN Position        */\r
+#define SCU_PLL_PLLCON0_AOTREN_Msk            (0x01UL << SCU_PLL_PLLCON0_AOTREN_Pos)                  /*!< SCU_PLL PLLCON0: AOTREN Mask            */\r
+#define SCU_PLL_PLLCON0_FOTR_Pos              20                                                      /*!< SCU_PLL PLLCON0: FOTR Position          */\r
+#define SCU_PLL_PLLCON0_FOTR_Msk              (0x01UL << SCU_PLL_PLLCON0_FOTR_Pos)                    /*!< SCU_PLL PLLCON0: FOTR Mask              */\r
+\r
+/* -------------------------------  SCU_PLL_PLLCON1  ------------------------------ */\r
+#define SCU_PLL_PLLCON1_K1DIV_Pos             0                                                       /*!< SCU_PLL PLLCON1: K1DIV Position         */\r
+#define SCU_PLL_PLLCON1_K1DIV_Msk             (0x7fUL << SCU_PLL_PLLCON1_K1DIV_Pos)                   /*!< SCU_PLL PLLCON1: K1DIV Mask             */\r
+#define SCU_PLL_PLLCON1_NDIV_Pos              8                                                       /*!< SCU_PLL PLLCON1: NDIV Position          */\r
+#define SCU_PLL_PLLCON1_NDIV_Msk              (0x7fUL << SCU_PLL_PLLCON1_NDIV_Pos)                    /*!< SCU_PLL PLLCON1: NDIV Mask              */\r
+#define SCU_PLL_PLLCON1_K2DIV_Pos             16                                                      /*!< SCU_PLL PLLCON1: K2DIV Position         */\r
+#define SCU_PLL_PLLCON1_K2DIV_Msk             (0x7fUL << SCU_PLL_PLLCON1_K2DIV_Pos)                   /*!< SCU_PLL PLLCON1: K2DIV Mask             */\r
+#define SCU_PLL_PLLCON1_PDIV_Pos              24                                                      /*!< SCU_PLL PLLCON1: PDIV Position          */\r
+#define SCU_PLL_PLLCON1_PDIV_Msk              (0x0fUL << SCU_PLL_PLLCON1_PDIV_Pos)                    /*!< SCU_PLL PLLCON1: PDIV Mask              */\r
+\r
+/* -------------------------------  SCU_PLL_PLLCON2  ------------------------------ */\r
+#define SCU_PLL_PLLCON2_PINSEL_Pos            0                                                       /*!< SCU_PLL PLLCON2: PINSEL Position        */\r
+#define SCU_PLL_PLLCON2_PINSEL_Msk            (0x01UL << SCU_PLL_PLLCON2_PINSEL_Pos)                  /*!< SCU_PLL PLLCON2: PINSEL Mask            */\r
+#define SCU_PLL_PLLCON2_K1INSEL_Pos           8                                                       /*!< SCU_PLL PLLCON2: K1INSEL Position       */\r
+#define SCU_PLL_PLLCON2_K1INSEL_Msk           (0x01UL << SCU_PLL_PLLCON2_K1INSEL_Pos)                 /*!< SCU_PLL PLLCON2: K1INSEL Mask           */\r
+\r
+/* -----------------------------  SCU_PLL_USBPLLSTAT  ----------------------------- */\r
+#define SCU_PLL_USBPLLSTAT_VCOBYST_Pos        0                                                       /*!< SCU_PLL USBPLLSTAT: VCOBYST Position    */\r
+#define SCU_PLL_USBPLLSTAT_VCOBYST_Msk        (0x01UL << SCU_PLL_USBPLLSTAT_VCOBYST_Pos)              /*!< SCU_PLL USBPLLSTAT: VCOBYST Mask        */\r
+#define SCU_PLL_USBPLLSTAT_PWDSTAT_Pos        1                                                       /*!< SCU_PLL USBPLLSTAT: PWDSTAT Position    */\r
+#define SCU_PLL_USBPLLSTAT_PWDSTAT_Msk        (0x01UL << SCU_PLL_USBPLLSTAT_PWDSTAT_Pos)              /*!< SCU_PLL USBPLLSTAT: PWDSTAT Mask        */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCK_Pos        2                                                       /*!< SCU_PLL USBPLLSTAT: VCOLOCK Position    */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCK_Msk        (0x01UL << SCU_PLL_USBPLLSTAT_VCOLOCK_Pos)              /*!< SCU_PLL USBPLLSTAT: VCOLOCK Mask        */\r
+#define SCU_PLL_USBPLLSTAT_BY_Pos             6                                                       /*!< SCU_PLL USBPLLSTAT: BY Position         */\r
+#define SCU_PLL_USBPLLSTAT_BY_Msk             (0x01UL << SCU_PLL_USBPLLSTAT_BY_Pos)                   /*!< SCU_PLL USBPLLSTAT: BY Mask             */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos      7                                                       /*!< SCU_PLL USBPLLSTAT: VCOLOCKED Position  */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk      (0x01UL << SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos)            /*!< SCU_PLL USBPLLSTAT: VCOLOCKED Mask      */\r
+\r
+/* ------------------------------  SCU_PLL_USBPLLCON  ----------------------------- */\r
+#define SCU_PLL_USBPLLCON_VCOBYP_Pos          0                                                       /*!< SCU_PLL USBPLLCON: VCOBYP Position      */\r
+#define SCU_PLL_USBPLLCON_VCOBYP_Msk          (0x01UL << SCU_PLL_USBPLLCON_VCOBYP_Pos)                /*!< SCU_PLL USBPLLCON: VCOBYP Mask          */\r
+#define SCU_PLL_USBPLLCON_VCOPWD_Pos          1                                                       /*!< SCU_PLL USBPLLCON: VCOPWD Position      */\r
+#define SCU_PLL_USBPLLCON_VCOPWD_Msk          (0x01UL << SCU_PLL_USBPLLCON_VCOPWD_Pos)                /*!< SCU_PLL USBPLLCON: VCOPWD Mask          */\r
+#define SCU_PLL_USBPLLCON_VCOTR_Pos           2                                                       /*!< SCU_PLL USBPLLCON: VCOTR Position       */\r
+#define SCU_PLL_USBPLLCON_VCOTR_Msk           (0x01UL << SCU_PLL_USBPLLCON_VCOTR_Pos)                 /*!< SCU_PLL USBPLLCON: VCOTR Mask           */\r
+#define SCU_PLL_USBPLLCON_FINDIS_Pos          4                                                       /*!< SCU_PLL USBPLLCON: FINDIS Position      */\r
+#define SCU_PLL_USBPLLCON_FINDIS_Msk          (0x01UL << SCU_PLL_USBPLLCON_FINDIS_Pos)                /*!< SCU_PLL USBPLLCON: FINDIS Mask          */\r
+#define SCU_PLL_USBPLLCON_OSCDISCDIS_Pos      6                                                       /*!< SCU_PLL USBPLLCON: OSCDISCDIS Position  */\r
+#define SCU_PLL_USBPLLCON_OSCDISCDIS_Msk      (0x01UL << SCU_PLL_USBPLLCON_OSCDISCDIS_Pos)            /*!< SCU_PLL USBPLLCON: OSCDISCDIS Mask      */\r
+#define SCU_PLL_USBPLLCON_NDIV_Pos            8                                                       /*!< SCU_PLL USBPLLCON: NDIV Position        */\r
+#define SCU_PLL_USBPLLCON_NDIV_Msk            (0x7fUL << SCU_PLL_USBPLLCON_NDIV_Pos)                  /*!< SCU_PLL USBPLLCON: NDIV Mask            */\r
+#define SCU_PLL_USBPLLCON_PLLPWD_Pos          16                                                      /*!< SCU_PLL USBPLLCON: PLLPWD Position      */\r
+#define SCU_PLL_USBPLLCON_PLLPWD_Msk          (0x01UL << SCU_PLL_USBPLLCON_PLLPWD_Pos)                /*!< SCU_PLL USBPLLCON: PLLPWD Mask          */\r
+#define SCU_PLL_USBPLLCON_RESLD_Pos           18                                                      /*!< SCU_PLL USBPLLCON: RESLD Position       */\r
+#define SCU_PLL_USBPLLCON_RESLD_Msk           (0x01UL << SCU_PLL_USBPLLCON_RESLD_Pos)                 /*!< SCU_PLL USBPLLCON: RESLD Mask           */\r
+#define SCU_PLL_USBPLLCON_PDIV_Pos            24                                                      /*!< SCU_PLL USBPLLCON: PDIV Position        */\r
+#define SCU_PLL_USBPLLCON_PDIV_Msk            (0x0fUL << SCU_PLL_USBPLLCON_PDIV_Pos)                  /*!< SCU_PLL USBPLLCON: PDIV Mask            */\r
+\r
+/* ------------------------------  SCU_PLL_CLKMXSTAT  ----------------------------- */\r
+#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos       0                                                       /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX Position   */\r
+#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk       (0x03UL << SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos)             /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX Mask       */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'SCU_GENERAL' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_GENERAL_ID  ------------------------------- */\r
+#define SCU_GENERAL_ID_MOD_REV_Pos            0                                                       /*!< SCU_GENERAL ID: MOD_REV Position        */\r
+#define SCU_GENERAL_ID_MOD_REV_Msk            (0x000000ffUL << SCU_GENERAL_ID_MOD_REV_Pos)            /*!< SCU_GENERAL ID: MOD_REV Mask            */\r
+#define SCU_GENERAL_ID_MOD_TYPE_Pos           8                                                       /*!< SCU_GENERAL ID: MOD_TYPE Position       */\r
+#define SCU_GENERAL_ID_MOD_TYPE_Msk           (0x000000ffUL << SCU_GENERAL_ID_MOD_TYPE_Pos)           /*!< SCU_GENERAL ID: MOD_TYPE Mask           */\r
+#define SCU_GENERAL_ID_MOD_NUMBER_Pos         16                                                      /*!< SCU_GENERAL ID: MOD_NUMBER Position     */\r
+#define SCU_GENERAL_ID_MOD_NUMBER_Msk         (0x0000ffffUL << SCU_GENERAL_ID_MOD_NUMBER_Pos)         /*!< SCU_GENERAL ID: MOD_NUMBER Mask         */\r
+\r
+/* -----------------------------  SCU_GENERAL_IDCHIP  ----------------------------- */\r
+#define SCU_GENERAL_IDCHIP_IDCHIP_Pos         0                                                       /*!< SCU_GENERAL IDCHIP: IDCHIP Position     */\r
+#define SCU_GENERAL_IDCHIP_IDCHIP_Msk         (0xffffffffUL << SCU_GENERAL_IDCHIP_IDCHIP_Pos)         /*!< SCU_GENERAL IDCHIP: IDCHIP Mask         */\r
+\r
+/* -----------------------------  SCU_GENERAL_IDMANUF  ---------------------------- */\r
+#define SCU_GENERAL_IDMANUF_DEPT_Pos          0                                                       /*!< SCU_GENERAL IDMANUF: DEPT Position      */\r
+#define SCU_GENERAL_IDMANUF_DEPT_Msk          (0x1fUL << SCU_GENERAL_IDMANUF_DEPT_Pos)                /*!< SCU_GENERAL IDMANUF: DEPT Mask          */\r
+#define SCU_GENERAL_IDMANUF_MANUF_Pos         5                                                       /*!< SCU_GENERAL IDMANUF: MANUF Position     */\r
+#define SCU_GENERAL_IDMANUF_MANUF_Msk         (0x000007ffUL << SCU_GENERAL_IDMANUF_MANUF_Pos)         /*!< SCU_GENERAL IDMANUF: MANUF Mask         */\r
+\r
+/* ------------------------------  SCU_GENERAL_STCON  ----------------------------- */\r
+#define SCU_GENERAL_STCON_HWCON_Pos           0                                                       /*!< SCU_GENERAL STCON: HWCON Position       */\r
+#define SCU_GENERAL_STCON_HWCON_Msk           (0x03UL << SCU_GENERAL_STCON_HWCON_Pos)                 /*!< SCU_GENERAL STCON: HWCON Mask           */\r
+#define SCU_GENERAL_STCON_SWCON_Pos           8                                                       /*!< SCU_GENERAL STCON: SWCON Position       */\r
+#define SCU_GENERAL_STCON_SWCON_Msk           (0x0fUL << SCU_GENERAL_STCON_SWCON_Pos)                 /*!< SCU_GENERAL STCON: SWCON Mask           */\r
+\r
+/* -------------------------------  SCU_GENERAL_GPR  ------------------------------ */\r
+#define SCU_GENERAL_GPR_DAT_Pos               0                                                       /*!< SCU_GENERAL GPR: DAT Position           */\r
+#define SCU_GENERAL_GPR_DAT_Msk               (0xffffffffUL << SCU_GENERAL_GPR_DAT_Pos)               /*!< SCU_GENERAL GPR: DAT Mask               */\r
+\r
+/* -----------------------------  SCU_GENERAL_CCUCON  ----------------------------- */\r
+#define SCU_GENERAL_CCUCON_GSC40_Pos          0                                                       /*!< SCU_GENERAL CCUCON: GSC40 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC40_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC40_Pos)                /*!< SCU_GENERAL CCUCON: GSC40 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC41_Pos          1                                                       /*!< SCU_GENERAL CCUCON: GSC41 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC41_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC41_Pos)                /*!< SCU_GENERAL CCUCON: GSC41 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC80_Pos          8                                                       /*!< SCU_GENERAL CCUCON: GSC80 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC80_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC80_Pos)                /*!< SCU_GENERAL CCUCON: GSC80 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSHR0_Pos          24                                                      /*!< SCU_GENERAL CCUCON: GSHR0 Position      */\r
+#define SCU_GENERAL_CCUCON_GSHR0_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSHR0_Pos)                /*!< SCU_GENERAL CCUCON: GSHR0 Mask          */\r
+\r
+/* -----------------------------  SCU_GENERAL_DTSCON  ----------------------------- */\r
+#define SCU_GENERAL_DTSCON_PWD_Pos            0                                                       /*!< SCU_GENERAL DTSCON: PWD Position        */\r
+#define SCU_GENERAL_DTSCON_PWD_Msk            (0x01UL << SCU_GENERAL_DTSCON_PWD_Pos)                  /*!< SCU_GENERAL DTSCON: PWD Mask            */\r
+#define SCU_GENERAL_DTSCON_START_Pos          1                                                       /*!< SCU_GENERAL DTSCON: START Position      */\r
+#define SCU_GENERAL_DTSCON_START_Msk          (0x01UL << SCU_GENERAL_DTSCON_START_Pos)                /*!< SCU_GENERAL DTSCON: START Mask          */\r
+#define SCU_GENERAL_DTSCON_OFFSET_Pos         4                                                       /*!< SCU_GENERAL DTSCON: OFFSET Position     */\r
+#define SCU_GENERAL_DTSCON_OFFSET_Msk         (0x7fUL << SCU_GENERAL_DTSCON_OFFSET_Pos)               /*!< SCU_GENERAL DTSCON: OFFSET Mask         */\r
+#define SCU_GENERAL_DTSCON_GAIN_Pos           11                                                      /*!< SCU_GENERAL DTSCON: GAIN Position       */\r
+#define SCU_GENERAL_DTSCON_GAIN_Msk           (0x3fUL << SCU_GENERAL_DTSCON_GAIN_Pos)                 /*!< SCU_GENERAL DTSCON: GAIN Mask           */\r
+#define SCU_GENERAL_DTSCON_REFTRIM_Pos        17                                                      /*!< SCU_GENERAL DTSCON: REFTRIM Position    */\r
+#define SCU_GENERAL_DTSCON_REFTRIM_Msk        (0x07UL << SCU_GENERAL_DTSCON_REFTRIM_Pos)              /*!< SCU_GENERAL DTSCON: REFTRIM Mask        */\r
+#define SCU_GENERAL_DTSCON_BGTRIM_Pos         20                                                      /*!< SCU_GENERAL DTSCON: BGTRIM Position     */\r
+#define SCU_GENERAL_DTSCON_BGTRIM_Msk         (0x0fUL << SCU_GENERAL_DTSCON_BGTRIM_Pos)               /*!< SCU_GENERAL DTSCON: BGTRIM Mask         */\r
+\r
+/* -----------------------------  SCU_GENERAL_DTSSTAT  ---------------------------- */\r
+#define SCU_GENERAL_DTSSTAT_RESULT_Pos        0                                                       /*!< SCU_GENERAL DTSSTAT: RESULT Position    */\r
+#define SCU_GENERAL_DTSSTAT_RESULT_Msk        (0x000003ffUL << SCU_GENERAL_DTSSTAT_RESULT_Pos)        /*!< SCU_GENERAL DTSSTAT: RESULT Mask        */\r
+#define SCU_GENERAL_DTSSTAT_RDY_Pos           14                                                      /*!< SCU_GENERAL DTSSTAT: RDY Position       */\r
+#define SCU_GENERAL_DTSSTAT_RDY_Msk           (0x01UL << SCU_GENERAL_DTSSTAT_RDY_Pos)                 /*!< SCU_GENERAL DTSSTAT: RDY Mask           */\r
+#define SCU_GENERAL_DTSSTAT_BUSY_Pos          15                                                      /*!< SCU_GENERAL DTSSTAT: BUSY Position      */\r
+#define SCU_GENERAL_DTSSTAT_BUSY_Msk          (0x01UL << SCU_GENERAL_DTSSTAT_BUSY_Pos)                /*!< SCU_GENERAL DTSSTAT: BUSY Mask          */\r
+\r
+/* -----------------------------  SCU_GENERAL_GORCEN  ----------------------------- */\r
+#define SCU_GENERAL_GORCEN_ENORC6_Pos         6                                                       /*!< SCU_GENERAL GORCEN: ENORC6 Position     */\r
+#define SCU_GENERAL_GORCEN_ENORC6_Msk         (0x01UL << SCU_GENERAL_GORCEN_ENORC6_Pos)               /*!< SCU_GENERAL GORCEN: ENORC6 Mask         */\r
+#define SCU_GENERAL_GORCEN_ENORC7_Pos         7                                                       /*!< SCU_GENERAL GORCEN: ENORC7 Position     */\r
+#define SCU_GENERAL_GORCEN_ENORC7_Msk         (0x01UL << SCU_GENERAL_GORCEN_ENORC7_Pos)               /*!< SCU_GENERAL GORCEN: ENORC7 Mask         */\r
+\r
+/* ----------------------------  SCU_GENERAL_DTEMPLIM  ---------------------------- */\r
+#define SCU_GENERAL_DTEMPLIM_LOWER_Pos        0                                                       /*!< SCU_GENERAL DTEMPLIM: LOWER Position    */\r
+#define SCU_GENERAL_DTEMPLIM_LOWER_Msk        (0x000003ffUL << SCU_GENERAL_DTEMPLIM_LOWER_Pos)        /*!< SCU_GENERAL DTEMPLIM: LOWER Mask        */\r
+#define SCU_GENERAL_DTEMPLIM_UPPER_Pos        16                                                      /*!< SCU_GENERAL DTEMPLIM: UPPER Position    */\r
+#define SCU_GENERAL_DTEMPLIM_UPPER_Msk        (0x000003ffUL << SCU_GENERAL_DTEMPLIM_UPPER_Pos)        /*!< SCU_GENERAL DTEMPLIM: UPPER Mask        */\r
+\r
+/* ---------------------------  SCU_GENERAL_DTEMPALARM  --------------------------- */\r
+#define SCU_GENERAL_DTEMPALARM_UNDERFL_Pos    0                                                       /*!< SCU_GENERAL DTEMPALARM: UNDERFL Position */\r
+#define SCU_GENERAL_DTEMPALARM_UNDERFL_Msk    (0x01UL << SCU_GENERAL_DTEMPALARM_UNDERFL_Pos)          /*!< SCU_GENERAL DTEMPALARM: UNDERFL Mask    */\r
+#define SCU_GENERAL_DTEMPALARM_OVERFL_Pos     16                                                      /*!< SCU_GENERAL DTEMPALARM: OVERFL Position */\r
+#define SCU_GENERAL_DTEMPALARM_OVERFL_Msk     (0x01UL << SCU_GENERAL_DTEMPALARM_OVERFL_Pos)           /*!< SCU_GENERAL DTEMPALARM: OVERFL Mask     */\r
+\r
+/* -----------------------------  SCU_GENERAL_MIRRSTS  ---------------------------- */\r
+#define SCU_GENERAL_MIRRSTS_HDCLR_Pos         1                                                       /*!< SCU_GENERAL MIRRSTS: HDCLR Position     */\r
+#define SCU_GENERAL_MIRRSTS_HDCLR_Msk         (0x01UL << SCU_GENERAL_MIRRSTS_HDCLR_Pos)               /*!< SCU_GENERAL MIRRSTS: HDCLR Mask         */\r
+#define SCU_GENERAL_MIRRSTS_HDSET_Pos         2                                                       /*!< SCU_GENERAL MIRRSTS: HDSET Position     */\r
+#define SCU_GENERAL_MIRRSTS_HDSET_Msk         (0x01UL << SCU_GENERAL_MIRRSTS_HDSET_Pos)               /*!< SCU_GENERAL MIRRSTS: HDSET Mask         */\r
+#define SCU_GENERAL_MIRRSTS_HDCR_Pos          3                                                       /*!< SCU_GENERAL MIRRSTS: HDCR Position      */\r
+#define SCU_GENERAL_MIRRSTS_HDCR_Msk          (0x01UL << SCU_GENERAL_MIRRSTS_HDCR_Pos)                /*!< SCU_GENERAL MIRRSTS: HDCR Mask          */\r
+#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos     5                                                       /*!< SCU_GENERAL MIRRSTS: OSCSICTRL Position */\r
+#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos)           /*!< SCU_GENERAL MIRRSTS: OSCSICTRL Mask     */\r
+#define SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos     6                                                       /*!< SCU_GENERAL MIRRSTS: OSCULSTAT Position */\r
+#define SCU_GENERAL_MIRRSTS_OSCULSTAT_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos)           /*!< SCU_GENERAL MIRRSTS: OSCULSTAT Mask     */\r
+#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos     7                                                       /*!< SCU_GENERAL MIRRSTS: OSCULCTRL Position */\r
+#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos)           /*!< SCU_GENERAL MIRRSTS: OSCULCTRL Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos       8                                                       /*!< SCU_GENERAL MIRRSTS: RTC_CTR Position   */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CTR_Pos)             /*!< SCU_GENERAL MIRRSTS: RTC_CTR Mask       */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos     9                                                       /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos     10                                                      /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos      11                                                      /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Position  */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk      (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos)            /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Mask      */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos      12                                                      /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Position  */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk      (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos)            /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Mask      */\r
+#define SCU_GENERAL_MIRRSTS_RMX_Pos           13                                                      /*!< SCU_GENERAL MIRRSTS: RMX Position       */\r
+#define SCU_GENERAL_MIRRSTS_RMX_Msk           (0x01UL << SCU_GENERAL_MIRRSTS_RMX_Pos)                 /*!< SCU_GENERAL MIRRSTS: RMX Mask           */\r
+#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos     14                                                      /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos     15                                                      /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR Mask     */\r
+#define SCU_GENERAL_MIRRSTS_LPACCONF_Pos      16                                                      /*!< SCU_GENERAL MIRRSTS: LPACCONF Position  */\r
+#define SCU_GENERAL_MIRRSTS_LPACCONF_Msk      (0x01UL << SCU_GENERAL_MIRRSTS_LPACCONF_Pos)            /*!< SCU_GENERAL MIRRSTS: LPACCONF Mask      */\r
+#define SCU_GENERAL_MIRRSTS_LPACTH0_Pos       17                                                      /*!< SCU_GENERAL MIRRSTS: LPACTH0 Position   */\r
+#define SCU_GENERAL_MIRRSTS_LPACTH0_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_LPACTH0_Pos)             /*!< SCU_GENERAL MIRRSTS: LPACTH0 Mask       */\r
+#define SCU_GENERAL_MIRRSTS_LPACCLR_Pos       20                                                      /*!< SCU_GENERAL MIRRSTS: LPACCLR Position   */\r
+#define SCU_GENERAL_MIRRSTS_LPACCLR_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_LPACCLR_Pos)             /*!< SCU_GENERAL MIRRSTS: LPACCLR Mask       */\r
+#define SCU_GENERAL_MIRRSTS_LPACSET_Pos       21                                                      /*!< SCU_GENERAL MIRRSTS: LPACSET Position   */\r
+#define SCU_GENERAL_MIRRSTS_LPACSET_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_LPACSET_Pos)             /*!< SCU_GENERAL MIRRSTS: LPACSET Mask       */\r
+#define SCU_GENERAL_MIRRSTS_HINTCLR_Pos       23                                                      /*!< SCU_GENERAL MIRRSTS: HINTCLR Position   */\r
+#define SCU_GENERAL_MIRRSTS_HINTCLR_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_HINTCLR_Pos)             /*!< SCU_GENERAL MIRRSTS: HINTCLR Mask       */\r
+#define SCU_GENERAL_MIRRSTS_HINTSET_Pos       24                                                      /*!< SCU_GENERAL MIRRSTS: HINTSET Position   */\r
+#define SCU_GENERAL_MIRRSTS_HINTSET_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_HINTSET_Pos)             /*!< SCU_GENERAL MIRRSTS: HINTSET Mask       */\r
+\r
+/* ------------------------------  SCU_GENERAL_RMACR  ----------------------------- */\r
+#define SCU_GENERAL_RMACR_RDWR_Pos            0                                                       /*!< SCU_GENERAL RMACR: RDWR Position        */\r
+#define SCU_GENERAL_RMACR_RDWR_Msk            (0x01UL << SCU_GENERAL_RMACR_RDWR_Pos)                  /*!< SCU_GENERAL RMACR: RDWR Mask            */\r
+#define SCU_GENERAL_RMACR_ADDR_Pos            16                                                      /*!< SCU_GENERAL RMACR: ADDR Position        */\r
+#define SCU_GENERAL_RMACR_ADDR_Msk            (0x0fUL << SCU_GENERAL_RMACR_ADDR_Pos)                  /*!< SCU_GENERAL RMACR: ADDR Mask            */\r
+\r
+/* -----------------------------  SCU_GENERAL_RMDATA  ----------------------------- */\r
+#define SCU_GENERAL_RMDATA_DATA_Pos           0                                                       /*!< SCU_GENERAL RMDATA: DATA Position       */\r
+#define SCU_GENERAL_RMDATA_DATA_Msk           (0xffffffffUL << SCU_GENERAL_RMDATA_DATA_Pos)           /*!< SCU_GENERAL RMDATA: DATA Mask           */\r
+\r
+/* ---------------------------  SCU_GENERAL_MIRRALLSTAT  -------------------------- */\r
+#define SCU_GENERAL_MIRRALLSTAT_BUSY_Pos      0                                                       /*!< SCU_GENERAL MIRRALLSTAT: BUSY Position  */\r
+#define SCU_GENERAL_MIRRALLSTAT_BUSY_Msk      (0x01UL << SCU_GENERAL_MIRRALLSTAT_BUSY_Pos)            /*!< SCU_GENERAL MIRRALLSTAT: BUSY Mask      */\r
+\r
+/* ---------------------------  SCU_GENERAL_MIRRALLREQ  --------------------------- */\r
+#define SCU_GENERAL_MIRRALLREQ_REQ_Pos        0                                                       /*!< SCU_GENERAL MIRRALLREQ: REQ Position    */\r
+#define SCU_GENERAL_MIRRALLREQ_REQ_Msk        (0x01UL << SCU_GENERAL_MIRRALLREQ_REQ_Pos)              /*!< SCU_GENERAL MIRRALLREQ: REQ Mask        */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================     struct 'SCU_INTERRUPT' Position & Mask     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------  SCU_INTERRUPT_SRSTAT  ---------------------------- */\r
+#define SCU_INTERRUPT_SRSTAT_PRWARN_Pos       0                                                       /*!< SCU_INTERRUPT SRSTAT: PRWARN Position   */\r
+#define SCU_INTERRUPT_SRSTAT_PRWARN_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_PRWARN_Pos)             /*!< SCU_INTERRUPT SRSTAT: PRWARN Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_PI_Pos           1                                                       /*!< SCU_INTERRUPT SRSTAT: PI Position       */\r
+#define SCU_INTERRUPT_SRSTAT_PI_Msk           (0x01UL << SCU_INTERRUPT_SRSTAT_PI_Pos)                 /*!< SCU_INTERRUPT SRSTAT: PI Mask           */\r
+#define SCU_INTERRUPT_SRSTAT_AI_Pos           2                                                       /*!< SCU_INTERRUPT SRSTAT: AI Position       */\r
+#define SCU_INTERRUPT_SRSTAT_AI_Msk           (0x01UL << SCU_INTERRUPT_SRSTAT_AI_Pos)                 /*!< SCU_INTERRUPT SRSTAT: AI Mask           */\r
+#define SCU_INTERRUPT_SRSTAT_DLROVR_Pos       3                                                       /*!< SCU_INTERRUPT SRSTAT: DLROVR Position   */\r
+#define SCU_INTERRUPT_SRSTAT_DLROVR_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_DLROVR_Pos)             /*!< SCU_INTERRUPT SRSTAT: DLROVR Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_LPACCR_Pos       6                                                       /*!< SCU_INTERRUPT SRSTAT: LPACCR Position   */\r
+#define SCU_INTERRUPT_SRSTAT_LPACCR_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_LPACCR_Pos)             /*!< SCU_INTERRUPT SRSTAT: LPACCR Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_LPACTH0_Pos      7                                                       /*!< SCU_INTERRUPT SRSTAT: LPACTH0 Position  */\r
+#define SCU_INTERRUPT_SRSTAT_LPACTH0_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_LPACTH0_Pos)            /*!< SCU_INTERRUPT SRSTAT: LPACTH0 Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_LPACST_Pos       9                                                       /*!< SCU_INTERRUPT SRSTAT: LPACST Position   */\r
+#define SCU_INTERRUPT_SRSTAT_LPACST_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_LPACST_Pos)             /*!< SCU_INTERRUPT SRSTAT: LPACST Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_LPACCLR_Pos      10                                                      /*!< SCU_INTERRUPT SRSTAT: LPACCLR Position  */\r
+#define SCU_INTERRUPT_SRSTAT_LPACCLR_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_LPACCLR_Pos)            /*!< SCU_INTERRUPT SRSTAT: LPACCLR Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_LPACSET_Pos      11                                                      /*!< SCU_INTERRUPT SRSTAT: LPACSET Position  */\r
+#define SCU_INTERRUPT_SRSTAT_LPACSET_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_LPACSET_Pos)            /*!< SCU_INTERRUPT SRSTAT: LPACSET Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_HINTST_Pos       12                                                      /*!< SCU_INTERRUPT SRSTAT: HINTST Position   */\r
+#define SCU_INTERRUPT_SRSTAT_HINTST_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_HINTST_Pos)             /*!< SCU_INTERRUPT SRSTAT: HINTST Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_HINTCLR_Pos      13                                                      /*!< SCU_INTERRUPT SRSTAT: HINTCLR Position  */\r
+#define SCU_INTERRUPT_SRSTAT_HINTCLR_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_HINTCLR_Pos)            /*!< SCU_INTERRUPT SRSTAT: HINTCLR Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_HINTSET_Pos      14                                                      /*!< SCU_INTERRUPT SRSTAT: HINTSET Position  */\r
+#define SCU_INTERRUPT_SRSTAT_HINTSET_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_HINTSET_Pos)            /*!< SCU_INTERRUPT SRSTAT: HINTSET Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_HDSTAT_Pos       16                                                      /*!< SCU_INTERRUPT SRSTAT: HDSTAT Position   */\r
+#define SCU_INTERRUPT_SRSTAT_HDSTAT_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_HDSTAT_Pos)             /*!< SCU_INTERRUPT SRSTAT: HDSTAT Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_HDCLR_Pos        17                                                      /*!< SCU_INTERRUPT SRSTAT: HDCLR Position    */\r
+#define SCU_INTERRUPT_SRSTAT_HDCLR_Msk        (0x01UL << SCU_INTERRUPT_SRSTAT_HDCLR_Pos)              /*!< SCU_INTERRUPT SRSTAT: HDCLR Mask        */\r
+#define SCU_INTERRUPT_SRSTAT_HDSET_Pos        18                                                      /*!< SCU_INTERRUPT SRSTAT: HDSET Position    */\r
+#define SCU_INTERRUPT_SRSTAT_HDSET_Msk        (0x01UL << SCU_INTERRUPT_SRSTAT_HDSET_Pos)              /*!< SCU_INTERRUPT SRSTAT: HDSET Mask        */\r
+#define SCU_INTERRUPT_SRSTAT_HDCR_Pos         19                                                      /*!< SCU_INTERRUPT SRSTAT: HDCR Position     */\r
+#define SCU_INTERRUPT_SRSTAT_HDCR_Msk         (0x01UL << SCU_INTERRUPT_SRSTAT_HDCR_Pos)               /*!< SCU_INTERRUPT SRSTAT: HDCR Mask         */\r
+#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos    21                                                      /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos)          /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos    22                                                      /*!< SCU_INTERRUPT SRSTAT: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos)          /*!< SCU_INTERRUPT SRSTAT: OSCULSTAT Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos    23                                                      /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos)          /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos      24                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_CTR Position  */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos)            /*!< SCU_INTERRUPT SRSTAT: RTC_CTR Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos    25                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos)          /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos    26                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos)          /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos     27                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk     (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos)           /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 Mask     */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos     28                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk     (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos)           /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 Mask     */\r
+#define SCU_INTERRUPT_SRSTAT_RMX_Pos          29                                                      /*!< SCU_INTERRUPT SRSTAT: RMX Position      */\r
+#define SCU_INTERRUPT_SRSTAT_RMX_Msk          (0x01UL << SCU_INTERRUPT_SRSTAT_RMX_Pos)                /*!< SCU_INTERRUPT SRSTAT: RMX Mask          */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRRAW  ---------------------------- */\r
+#define SCU_INTERRUPT_SRRAW_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRRAW: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRRAW_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_PRWARN_Pos)              /*!< SCU_INTERRUPT SRRAW: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRRAW_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRRAW: PI Position        */\r
+#define SCU_INTERRUPT_SRRAW_PI_Msk            (0x01UL << SCU_INTERRUPT_SRRAW_PI_Pos)                  /*!< SCU_INTERRUPT SRRAW: PI Mask            */\r
+#define SCU_INTERRUPT_SRRAW_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRRAW: AI Position        */\r
+#define SCU_INTERRUPT_SRRAW_AI_Msk            (0x01UL << SCU_INTERRUPT_SRRAW_AI_Pos)                  /*!< SCU_INTERRUPT SRRAW: AI Mask            */\r
+#define SCU_INTERRUPT_SRRAW_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRRAW: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRRAW_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_DLROVR_Pos)              /*!< SCU_INTERRUPT SRRAW: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRRAW_LPACCR_Pos        6                                                       /*!< SCU_INTERRUPT SRRAW: LPACCR Position    */\r
+#define SCU_INTERRUPT_SRRAW_LPACCR_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_LPACCR_Pos)              /*!< SCU_INTERRUPT SRRAW: LPACCR Mask        */\r
+#define SCU_INTERRUPT_SRRAW_LPACTH0_Pos       7                                                       /*!< SCU_INTERRUPT SRRAW: LPACTH0 Position   */\r
+#define SCU_INTERRUPT_SRRAW_LPACTH0_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_LPACTH0_Pos)             /*!< SCU_INTERRUPT SRRAW: LPACTH0 Mask       */\r
+#define SCU_INTERRUPT_SRRAW_LPACST_Pos        9                                                       /*!< SCU_INTERRUPT SRRAW: LPACST Position    */\r
+#define SCU_INTERRUPT_SRRAW_LPACST_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_LPACST_Pos)              /*!< SCU_INTERRUPT SRRAW: LPACST Mask        */\r
+#define SCU_INTERRUPT_SRRAW_LPACCLR_Pos       10                                                      /*!< SCU_INTERRUPT SRRAW: LPACCLR Position   */\r
+#define SCU_INTERRUPT_SRRAW_LPACCLR_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_LPACCLR_Pos)             /*!< SCU_INTERRUPT SRRAW: LPACCLR Mask       */\r
+#define SCU_INTERRUPT_SRRAW_LPACSET_Pos       11                                                      /*!< SCU_INTERRUPT SRRAW: LPACSET Position   */\r
+#define SCU_INTERRUPT_SRRAW_LPACSET_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_LPACSET_Pos)             /*!< SCU_INTERRUPT SRRAW: LPACSET Mask       */\r
+#define SCU_INTERRUPT_SRRAW_HINTST_Pos        12                                                      /*!< SCU_INTERRUPT SRRAW: HINTST Position    */\r
+#define SCU_INTERRUPT_SRRAW_HINTST_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_HINTST_Pos)              /*!< SCU_INTERRUPT SRRAW: HINTST Mask        */\r
+#define SCU_INTERRUPT_SRRAW_HINTCLR_Pos       13                                                      /*!< SCU_INTERRUPT SRRAW: HINTCLR Position   */\r
+#define SCU_INTERRUPT_SRRAW_HINTCLR_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_HINTCLR_Pos)             /*!< SCU_INTERRUPT SRRAW: HINTCLR Mask       */\r
+#define SCU_INTERRUPT_SRRAW_HINTSET_Pos       14                                                      /*!< SCU_INTERRUPT SRRAW: HINTSET Position   */\r
+#define SCU_INTERRUPT_SRRAW_HINTSET_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_HINTSET_Pos)             /*!< SCU_INTERRUPT SRRAW: HINTSET Mask       */\r
+#define SCU_INTERRUPT_SRRAW_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRRAW: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRRAW_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRRAW: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRRAW_HDCLR_Pos         17                                                      /*!< SCU_INTERRUPT SRRAW: HDCLR Position     */\r
+#define SCU_INTERRUPT_SRRAW_HDCLR_Msk         (0x01UL << SCU_INTERRUPT_SRRAW_HDCLR_Pos)               /*!< SCU_INTERRUPT SRRAW: HDCLR Mask         */\r
+#define SCU_INTERRUPT_SRRAW_HDSET_Pos         18                                                      /*!< SCU_INTERRUPT SRRAW: HDSET Position     */\r
+#define SCU_INTERRUPT_SRRAW_HDSET_Msk         (0x01UL << SCU_INTERRUPT_SRRAW_HDSET_Pos)               /*!< SCU_INTERRUPT SRRAW: HDSET Mask         */\r
+#define SCU_INTERRUPT_SRRAW_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRRAW: HDCR Position      */\r
+#define SCU_INTERRUPT_SRRAW_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRRAW_HDCR_Pos)                /*!< SCU_INTERRUPT SRRAW: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRRAW: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRRAW: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRRAW: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRRAW_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRRAW: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRRAW: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRRAW: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRRAW: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRRAW: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRRAW_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRRAW: RMX Position       */\r
+#define SCU_INTERRUPT_SRRAW_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRRAW_RMX_Pos)                 /*!< SCU_INTERRUPT SRRAW: RMX Mask           */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRMSK  ---------------------------- */\r
+#define SCU_INTERRUPT_SRMSK_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRMSK: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRMSK_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_PRWARN_Pos)              /*!< SCU_INTERRUPT SRMSK: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRMSK_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRMSK: PI Position        */\r
+#define SCU_INTERRUPT_SRMSK_PI_Msk            (0x01UL << SCU_INTERRUPT_SRMSK_PI_Pos)                  /*!< SCU_INTERRUPT SRMSK: PI Mask            */\r
+#define SCU_INTERRUPT_SRMSK_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRMSK: AI Position        */\r
+#define SCU_INTERRUPT_SRMSK_AI_Msk            (0x01UL << SCU_INTERRUPT_SRMSK_AI_Pos)                  /*!< SCU_INTERRUPT SRMSK: AI Mask            */\r
+#define SCU_INTERRUPT_SRMSK_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRMSK: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRMSK_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_DLROVR_Pos)              /*!< SCU_INTERRUPT SRMSK: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRMSK_LPACCR_Pos        6                                                       /*!< SCU_INTERRUPT SRMSK: LPACCR Position    */\r
+#define SCU_INTERRUPT_SRMSK_LPACCR_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_LPACCR_Pos)              /*!< SCU_INTERRUPT SRMSK: LPACCR Mask        */\r
+#define SCU_INTERRUPT_SRMSK_LPACTH0_Pos       7                                                       /*!< SCU_INTERRUPT SRMSK: LPACTH0 Position   */\r
+#define SCU_INTERRUPT_SRMSK_LPACTH0_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_LPACTH0_Pos)             /*!< SCU_INTERRUPT SRMSK: LPACTH0 Mask       */\r
+#define SCU_INTERRUPT_SRMSK_LPACST_Pos        9                                                       /*!< SCU_INTERRUPT SRMSK: LPACST Position    */\r
+#define SCU_INTERRUPT_SRMSK_LPACST_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_LPACST_Pos)              /*!< SCU_INTERRUPT SRMSK: LPACST Mask        */\r
+#define SCU_INTERRUPT_SRMSK_LPACCLR_Pos       10                                                      /*!< SCU_INTERRUPT SRMSK: LPACCLR Position   */\r
+#define SCU_INTERRUPT_SRMSK_LPACCLR_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_LPACCLR_Pos)             /*!< SCU_INTERRUPT SRMSK: LPACCLR Mask       */\r
+#define SCU_INTERRUPT_SRMSK_LPACSET_Pos       11                                                      /*!< SCU_INTERRUPT SRMSK: LPACSET Position   */\r
+#define SCU_INTERRUPT_SRMSK_LPACSET_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_LPACSET_Pos)             /*!< SCU_INTERRUPT SRMSK: LPACSET Mask       */\r
+#define SCU_INTERRUPT_SRMSK_HINTST_Pos        12                                                      /*!< SCU_INTERRUPT SRMSK: HINTST Position    */\r
+#define SCU_INTERRUPT_SRMSK_HINTST_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_HINTST_Pos)              /*!< SCU_INTERRUPT SRMSK: HINTST Mask        */\r
+#define SCU_INTERRUPT_SRMSK_HINTCLR_Pos       13                                                      /*!< SCU_INTERRUPT SRMSK: HINTCLR Position   */\r
+#define SCU_INTERRUPT_SRMSK_HINTCLR_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_HINTCLR_Pos)             /*!< SCU_INTERRUPT SRMSK: HINTCLR Mask       */\r
+#define SCU_INTERRUPT_SRMSK_HINTSET_Pos       14                                                      /*!< SCU_INTERRUPT SRMSK: HINTSET Position   */\r
+#define SCU_INTERRUPT_SRMSK_HINTSET_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_HINTSET_Pos)             /*!< SCU_INTERRUPT SRMSK: HINTSET Mask       */\r
+#define SCU_INTERRUPT_SRMSK_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRMSK: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRMSK_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRMSK: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRMSK_HDCLR_Pos         17                                                      /*!< SCU_INTERRUPT SRMSK: HDCLR Position     */\r
+#define SCU_INTERRUPT_SRMSK_HDCLR_Msk         (0x01UL << SCU_INTERRUPT_SRMSK_HDCLR_Pos)               /*!< SCU_INTERRUPT SRMSK: HDCLR Mask         */\r
+#define SCU_INTERRUPT_SRMSK_HDSET_Pos         18                                                      /*!< SCU_INTERRUPT SRMSK: HDSET Position     */\r
+#define SCU_INTERRUPT_SRMSK_HDSET_Msk         (0x01UL << SCU_INTERRUPT_SRMSK_HDSET_Pos)               /*!< SCU_INTERRUPT SRMSK: HDSET Mask         */\r
+#define SCU_INTERRUPT_SRMSK_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRMSK: HDCR Position      */\r
+#define SCU_INTERRUPT_SRMSK_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRMSK_HDCR_Pos)                /*!< SCU_INTERRUPT SRMSK: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRMSK: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRMSK: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRMSK: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRMSK_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRMSK: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRMSK: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRMSK: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRMSK: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRMSK: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRMSK_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRMSK: RMX Position       */\r
+#define SCU_INTERRUPT_SRMSK_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRMSK_RMX_Pos)                 /*!< SCU_INTERRUPT SRMSK: RMX Mask           */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRCLR  ---------------------------- */\r
+#define SCU_INTERRUPT_SRCLR_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRCLR: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRCLR_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_PRWARN_Pos)              /*!< SCU_INTERRUPT SRCLR: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRCLR_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRCLR: PI Position        */\r
+#define SCU_INTERRUPT_SRCLR_PI_Msk            (0x01UL << SCU_INTERRUPT_SRCLR_PI_Pos)                  /*!< SCU_INTERRUPT SRCLR: PI Mask            */\r
+#define SCU_INTERRUPT_SRCLR_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRCLR: AI Position        */\r
+#define SCU_INTERRUPT_SRCLR_AI_Msk            (0x01UL << SCU_INTERRUPT_SRCLR_AI_Pos)                  /*!< SCU_INTERRUPT SRCLR: AI Mask            */\r
+#define SCU_INTERRUPT_SRCLR_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRCLR: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRCLR_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_DLROVR_Pos)              /*!< SCU_INTERRUPT SRCLR: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRCLR_LPACCR_Pos        6                                                       /*!< SCU_INTERRUPT SRCLR: LPACCR Position    */\r
+#define SCU_INTERRUPT_SRCLR_LPACCR_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_LPACCR_Pos)              /*!< SCU_INTERRUPT SRCLR: LPACCR Mask        */\r
+#define SCU_INTERRUPT_SRCLR_LPACTH0_Pos       7                                                       /*!< SCU_INTERRUPT SRCLR: LPACTH0 Position   */\r
+#define SCU_INTERRUPT_SRCLR_LPACTH0_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_LPACTH0_Pos)             /*!< SCU_INTERRUPT SRCLR: LPACTH0 Mask       */\r
+#define SCU_INTERRUPT_SRCLR_LPACST_Pos        9                                                       /*!< SCU_INTERRUPT SRCLR: LPACST Position    */\r
+#define SCU_INTERRUPT_SRCLR_LPACST_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_LPACST_Pos)              /*!< SCU_INTERRUPT SRCLR: LPACST Mask        */\r
+#define SCU_INTERRUPT_SRCLR_LPACCLR_Pos       10                                                      /*!< SCU_INTERRUPT SRCLR: LPACCLR Position   */\r
+#define SCU_INTERRUPT_SRCLR_LPACCLR_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_LPACCLR_Pos)             /*!< SCU_INTERRUPT SRCLR: LPACCLR Mask       */\r
+#define SCU_INTERRUPT_SRCLR_LPACSET_Pos       11                                                      /*!< SCU_INTERRUPT SRCLR: LPACSET Position   */\r
+#define SCU_INTERRUPT_SRCLR_LPACSET_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_LPACSET_Pos)             /*!< SCU_INTERRUPT SRCLR: LPACSET Mask       */\r
+#define SCU_INTERRUPT_SRCLR_HINTST_Pos        12                                                      /*!< SCU_INTERRUPT SRCLR: HINTST Position    */\r
+#define SCU_INTERRUPT_SRCLR_HINTST_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_HINTST_Pos)              /*!< SCU_INTERRUPT SRCLR: HINTST Mask        */\r
+#define SCU_INTERRUPT_SRCLR_HINTCLR_Pos       13                                                      /*!< SCU_INTERRUPT SRCLR: HINTCLR Position   */\r
+#define SCU_INTERRUPT_SRCLR_HINTCLR_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_HINTCLR_Pos)             /*!< SCU_INTERRUPT SRCLR: HINTCLR Mask       */\r
+#define SCU_INTERRUPT_SRCLR_HINTSET_Pos       14                                                      /*!< SCU_INTERRUPT SRCLR: HINTSET Position   */\r
+#define SCU_INTERRUPT_SRCLR_HINTSET_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_HINTSET_Pos)             /*!< SCU_INTERRUPT SRCLR: HINTSET Mask       */\r
+#define SCU_INTERRUPT_SRCLR_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRCLR: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRCLR_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRCLR: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRCLR_HDCLR_Pos         17                                                      /*!< SCU_INTERRUPT SRCLR: HDCLR Position     */\r
+#define SCU_INTERRUPT_SRCLR_HDCLR_Msk         (0x01UL << SCU_INTERRUPT_SRCLR_HDCLR_Pos)               /*!< SCU_INTERRUPT SRCLR: HDCLR Mask         */\r
+#define SCU_INTERRUPT_SRCLR_HDSET_Pos         18                                                      /*!< SCU_INTERRUPT SRCLR: HDSET Position     */\r
+#define SCU_INTERRUPT_SRCLR_HDSET_Msk         (0x01UL << SCU_INTERRUPT_SRCLR_HDSET_Pos)               /*!< SCU_INTERRUPT SRCLR: HDSET Mask         */\r
+#define SCU_INTERRUPT_SRCLR_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRCLR: HDCR Position      */\r
+#define SCU_INTERRUPT_SRCLR_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRCLR_HDCR_Pos)                /*!< SCU_INTERRUPT SRCLR: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRCLR: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRCLR: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRCLR: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRCLR_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRCLR: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRCLR: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRCLR: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRCLR: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRCLR: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRCLR_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRCLR: RMX Position       */\r
+#define SCU_INTERRUPT_SRCLR_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRCLR_RMX_Pos)                 /*!< SCU_INTERRUPT SRCLR: RMX Mask           */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRSET  ---------------------------- */\r
+#define SCU_INTERRUPT_SRSET_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRSET: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRSET_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRSET_PRWARN_Pos)              /*!< SCU_INTERRUPT SRSET: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRSET_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRSET: PI Position        */\r
+#define SCU_INTERRUPT_SRSET_PI_Msk            (0x01UL << SCU_INTERRUPT_SRSET_PI_Pos)                  /*!< SCU_INTERRUPT SRSET: PI Mask            */\r
+#define SCU_INTERRUPT_SRSET_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRSET: AI Position        */\r
+#define SCU_INTERRUPT_SRSET_AI_Msk            (0x01UL << SCU_INTERRUPT_SRSET_AI_Pos)                  /*!< SCU_INTERRUPT SRSET: AI Mask            */\r
+#define SCU_INTERRUPT_SRSET_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRSET: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRSET_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRSET_DLROVR_Pos)              /*!< SCU_INTERRUPT SRSET: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRSET_LPACCR_Pos        6                                                       /*!< SCU_INTERRUPT SRSET: LPACCR Position    */\r
+#define SCU_INTERRUPT_SRSET_LPACCR_Msk        (0x01UL << SCU_INTERRUPT_SRSET_LPACCR_Pos)              /*!< SCU_INTERRUPT SRSET: LPACCR Mask        */\r
+#define SCU_INTERRUPT_SRSET_LPACTH0_Pos       7                                                       /*!< SCU_INTERRUPT SRSET: LPACTH0 Position   */\r
+#define SCU_INTERRUPT_SRSET_LPACTH0_Msk       (0x01UL << SCU_INTERRUPT_SRSET_LPACTH0_Pos)             /*!< SCU_INTERRUPT SRSET: LPACTH0 Mask       */\r
+#define SCU_INTERRUPT_SRSET_LPACST_Pos        9                                                       /*!< SCU_INTERRUPT SRSET: LPACST Position    */\r
+#define SCU_INTERRUPT_SRSET_LPACST_Msk        (0x01UL << SCU_INTERRUPT_SRSET_LPACST_Pos)              /*!< SCU_INTERRUPT SRSET: LPACST Mask        */\r
+#define SCU_INTERRUPT_SRSET_LPACCLR_Pos       10                                                      /*!< SCU_INTERRUPT SRSET: LPACCLR Position   */\r
+#define SCU_INTERRUPT_SRSET_LPACCLR_Msk       (0x01UL << SCU_INTERRUPT_SRSET_LPACCLR_Pos)             /*!< SCU_INTERRUPT SRSET: LPACCLR Mask       */\r
+#define SCU_INTERRUPT_SRSET_LPACSET_Pos       11                                                      /*!< SCU_INTERRUPT SRSET: LPACSET Position   */\r
+#define SCU_INTERRUPT_SRSET_LPACSET_Msk       (0x01UL << SCU_INTERRUPT_SRSET_LPACSET_Pos)             /*!< SCU_INTERRUPT SRSET: LPACSET Mask       */\r
+#define SCU_INTERRUPT_SRSET_HINTST_Pos        12                                                      /*!< SCU_INTERRUPT SRSET: HINTST Position    */\r
+#define SCU_INTERRUPT_SRSET_HINTST_Msk        (0x01UL << SCU_INTERRUPT_SRSET_HINTST_Pos)              /*!< SCU_INTERRUPT SRSET: HINTST Mask        */\r
+#define SCU_INTERRUPT_SRSET_HINTCLR_Pos       13                                                      /*!< SCU_INTERRUPT SRSET: HINTCLR Position   */\r
+#define SCU_INTERRUPT_SRSET_HINTCLR_Msk       (0x01UL << SCU_INTERRUPT_SRSET_HINTCLR_Pos)             /*!< SCU_INTERRUPT SRSET: HINTCLR Mask       */\r
+#define SCU_INTERRUPT_SRSET_HINTSET_Pos       14                                                      /*!< SCU_INTERRUPT SRSET: HINTSET Position   */\r
+#define SCU_INTERRUPT_SRSET_HINTSET_Msk       (0x01UL << SCU_INTERRUPT_SRSET_HINTSET_Pos)             /*!< SCU_INTERRUPT SRSET: HINTSET Mask       */\r
+#define SCU_INTERRUPT_SRSET_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRSET: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRSET_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRSET_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRSET: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRSET_HDCRCLR_Pos       17                                                      /*!< SCU_INTERRUPT SRSET: HDCRCLR Position   */\r
+#define SCU_INTERRUPT_SRSET_HDCRCLR_Msk       (0x01UL << SCU_INTERRUPT_SRSET_HDCRCLR_Pos)             /*!< SCU_INTERRUPT SRSET: HDCRCLR Mask       */\r
+#define SCU_INTERRUPT_SRSET_HDCRSET_Pos       18                                                      /*!< SCU_INTERRUPT SRSET: HDCRSET Position   */\r
+#define SCU_INTERRUPT_SRSET_HDCRSET_Msk       (0x01UL << SCU_INTERRUPT_SRSET_HDCRSET_Pos)             /*!< SCU_INTERRUPT SRSET: HDCRSET Mask       */\r
+#define SCU_INTERRUPT_SRSET_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRSET: HDCR Position      */\r
+#define SCU_INTERRUPT_SRSET_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRSET_HDCR_Pos)                /*!< SCU_INTERRUPT SRSET: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRSET_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRSET: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRSET_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRSET_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRSET: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRSET_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRSET: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRSET_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRSET_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRSET: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRSET_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRSET: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRSET_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRSET_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRSET: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRSET_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRSET: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRSET_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRSET_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRSET: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRSET_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRSET: RMX Position       */\r
+#define SCU_INTERRUPT_SRSET_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRSET_RMX_Pos)                 /*!< SCU_INTERRUPT SRSET: RMX Mask           */\r
+\r
+/* ---------------------------  SCU_INTERRUPT_NMIREQEN  --------------------------- */\r
+#define SCU_INTERRUPT_NMIREQEN_PRWARN_Pos     0                                                       /*!< SCU_INTERRUPT NMIREQEN: PRWARN Position */\r
+#define SCU_INTERRUPT_NMIREQEN_PRWARN_Msk     (0x01UL << SCU_INTERRUPT_NMIREQEN_PRWARN_Pos)           /*!< SCU_INTERRUPT NMIREQEN: PRWARN Mask     */\r
+#define SCU_INTERRUPT_NMIREQEN_PI_Pos         1                                                       /*!< SCU_INTERRUPT NMIREQEN: PI Position     */\r
+#define SCU_INTERRUPT_NMIREQEN_PI_Msk         (0x01UL << SCU_INTERRUPT_NMIREQEN_PI_Pos)               /*!< SCU_INTERRUPT NMIREQEN: PI Mask         */\r
+#define SCU_INTERRUPT_NMIREQEN_AI_Pos         2                                                       /*!< SCU_INTERRUPT NMIREQEN: AI Position     */\r
+#define SCU_INTERRUPT_NMIREQEN_AI_Msk         (0x01UL << SCU_INTERRUPT_NMIREQEN_AI_Pos)               /*!< SCU_INTERRUPT NMIREQEN: AI Mask         */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU00_Pos      16                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU00 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU00_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU00_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU00 Mask      */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU01_Pos      17                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU01 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU01_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU01_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU01 Mask      */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU02_Pos      18                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU02 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU02_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU02_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU02 Mask      */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU03_Pos      19                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU03 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU03_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU03_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU03 Mask      */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       struct 'SCU_PARITY' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_PARITY_PEEN  ------------------------------ */\r
+#define SCU_PARITY_PEEN_PEENPS_Pos            0                                                       /*!< SCU_PARITY PEEN: PEENPS Position        */\r
+#define SCU_PARITY_PEEN_PEENPS_Msk            (0x01UL << SCU_PARITY_PEEN_PEENPS_Pos)                  /*!< SCU_PARITY PEEN: PEENPS Mask            */\r
+#define SCU_PARITY_PEEN_PEENDS1_Pos           1                                                       /*!< SCU_PARITY PEEN: PEENDS1 Position       */\r
+#define SCU_PARITY_PEEN_PEENDS1_Msk           (0x01UL << SCU_PARITY_PEEN_PEENDS1_Pos)                 /*!< SCU_PARITY PEEN: PEENDS1 Mask           */\r
+#define SCU_PARITY_PEEN_PEENU0_Pos            8                                                       /*!< SCU_PARITY PEEN: PEENU0 Position        */\r
+#define SCU_PARITY_PEEN_PEENU0_Msk            (0x01UL << SCU_PARITY_PEEN_PEENU0_Pos)                  /*!< SCU_PARITY PEEN: PEENU0 Mask            */\r
+#define SCU_PARITY_PEEN_PEENU1_Pos            9                                                       /*!< SCU_PARITY PEEN: PEENU1 Position        */\r
+#define SCU_PARITY_PEEN_PEENU1_Msk            (0x01UL << SCU_PARITY_PEEN_PEENU1_Pos)                  /*!< SCU_PARITY PEEN: PEENU1 Mask            */\r
+#define SCU_PARITY_PEEN_PEENMC_Pos            12                                                      /*!< SCU_PARITY PEEN: PEENMC Position        */\r
+#define SCU_PARITY_PEEN_PEENMC_Msk            (0x01UL << SCU_PARITY_PEEN_PEENMC_Pos)                  /*!< SCU_PARITY PEEN: PEENMC Mask            */\r
+#define SCU_PARITY_PEEN_PEENPPRF_Pos          13                                                      /*!< SCU_PARITY PEEN: PEENPPRF Position      */\r
+#define SCU_PARITY_PEEN_PEENPPRF_Msk          (0x01UL << SCU_PARITY_PEEN_PEENPPRF_Pos)                /*!< SCU_PARITY PEEN: PEENPPRF Mask          */\r
+#define SCU_PARITY_PEEN_PEENUSB_Pos           16                                                      /*!< SCU_PARITY PEEN: PEENUSB Position       */\r
+#define SCU_PARITY_PEEN_PEENUSB_Msk           (0x01UL << SCU_PARITY_PEEN_PEENUSB_Pos)                 /*!< SCU_PARITY PEEN: PEENUSB Mask           */\r
+\r
+/* -----------------------------  SCU_PARITY_MCHKCON  ----------------------------- */\r
+#define SCU_PARITY_MCHKCON_SELPS_Pos          0                                                       /*!< SCU_PARITY MCHKCON: SELPS Position      */\r
+#define SCU_PARITY_MCHKCON_SELPS_Msk          (0x01UL << SCU_PARITY_MCHKCON_SELPS_Pos)                /*!< SCU_PARITY MCHKCON: SELPS Mask          */\r
+#define SCU_PARITY_MCHKCON_SELDS1_Pos         1                                                       /*!< SCU_PARITY MCHKCON: SELDS1 Position     */\r
+#define SCU_PARITY_MCHKCON_SELDS1_Msk         (0x01UL << SCU_PARITY_MCHKCON_SELDS1_Pos)               /*!< SCU_PARITY MCHKCON: SELDS1 Mask         */\r
+#define SCU_PARITY_MCHKCON_USIC0DRA_Pos       8                                                       /*!< SCU_PARITY MCHKCON: USIC0DRA Position   */\r
+#define SCU_PARITY_MCHKCON_USIC0DRA_Msk       (0x01UL << SCU_PARITY_MCHKCON_USIC0DRA_Pos)             /*!< SCU_PARITY MCHKCON: USIC0DRA Mask       */\r
+#define SCU_PARITY_MCHKCON_USIC1DRA_Pos       9                                                       /*!< SCU_PARITY MCHKCON: USIC1DRA Position   */\r
+#define SCU_PARITY_MCHKCON_USIC1DRA_Msk       (0x01UL << SCU_PARITY_MCHKCON_USIC1DRA_Pos)             /*!< SCU_PARITY MCHKCON: USIC1DRA Mask       */\r
+#define SCU_PARITY_MCHKCON_MCANDRA_Pos        12                                                      /*!< SCU_PARITY MCHKCON: MCANDRA Position    */\r
+#define SCU_PARITY_MCHKCON_MCANDRA_Msk        (0x01UL << SCU_PARITY_MCHKCON_MCANDRA_Pos)              /*!< SCU_PARITY MCHKCON: MCANDRA Mask        */\r
+#define SCU_PARITY_MCHKCON_PPRFDRA_Pos        13                                                      /*!< SCU_PARITY MCHKCON: PPRFDRA Position    */\r
+#define SCU_PARITY_MCHKCON_PPRFDRA_Msk        (0x01UL << SCU_PARITY_MCHKCON_PPRFDRA_Pos)              /*!< SCU_PARITY MCHKCON: PPRFDRA Mask        */\r
+#define SCU_PARITY_MCHKCON_SELUSB_Pos         16                                                      /*!< SCU_PARITY MCHKCON: SELUSB Position     */\r
+#define SCU_PARITY_MCHKCON_SELUSB_Msk         (0x01UL << SCU_PARITY_MCHKCON_SELUSB_Pos)               /*!< SCU_PARITY MCHKCON: SELUSB Mask         */\r
+\r
+/* -------------------------------  SCU_PARITY_PETE  ------------------------------ */\r
+#define SCU_PARITY_PETE_PETEPS_Pos            0                                                       /*!< SCU_PARITY PETE: PETEPS Position        */\r
+#define SCU_PARITY_PETE_PETEPS_Msk            (0x01UL << SCU_PARITY_PETE_PETEPS_Pos)                  /*!< SCU_PARITY PETE: PETEPS Mask            */\r
+#define SCU_PARITY_PETE_PETEDS1_Pos           1                                                       /*!< SCU_PARITY PETE: PETEDS1 Position       */\r
+#define SCU_PARITY_PETE_PETEDS1_Msk           (0x01UL << SCU_PARITY_PETE_PETEDS1_Pos)                 /*!< SCU_PARITY PETE: PETEDS1 Mask           */\r
+#define SCU_PARITY_PETE_PETEU0_Pos            8                                                       /*!< SCU_PARITY PETE: PETEU0 Position        */\r
+#define SCU_PARITY_PETE_PETEU0_Msk            (0x01UL << SCU_PARITY_PETE_PETEU0_Pos)                  /*!< SCU_PARITY PETE: PETEU0 Mask            */\r
+#define SCU_PARITY_PETE_PETEU1_Pos            9                                                       /*!< SCU_PARITY PETE: PETEU1 Position        */\r
+#define SCU_PARITY_PETE_PETEU1_Msk            (0x01UL << SCU_PARITY_PETE_PETEU1_Pos)                  /*!< SCU_PARITY PETE: PETEU1 Mask            */\r
+#define SCU_PARITY_PETE_PETEMC_Pos            12                                                      /*!< SCU_PARITY PETE: PETEMC Position        */\r
+#define SCU_PARITY_PETE_PETEMC_Msk            (0x01UL << SCU_PARITY_PETE_PETEMC_Pos)                  /*!< SCU_PARITY PETE: PETEMC Mask            */\r
+#define SCU_PARITY_PETE_PETEPPRF_Pos          13                                                      /*!< SCU_PARITY PETE: PETEPPRF Position      */\r
+#define SCU_PARITY_PETE_PETEPPRF_Msk          (0x01UL << SCU_PARITY_PETE_PETEPPRF_Pos)                /*!< SCU_PARITY PETE: PETEPPRF Mask          */\r
+#define SCU_PARITY_PETE_PETEUSB_Pos           16                                                      /*!< SCU_PARITY PETE: PETEUSB Position       */\r
+#define SCU_PARITY_PETE_PETEUSB_Msk           (0x01UL << SCU_PARITY_PETE_PETEUSB_Pos)                 /*!< SCU_PARITY PETE: PETEUSB Mask           */\r
+\r
+/* -----------------------------  SCU_PARITY_PERSTEN  ----------------------------- */\r
+#define SCU_PARITY_PERSTEN_RSEN_Pos           0                                                       /*!< SCU_PARITY PERSTEN: RSEN Position       */\r
+#define SCU_PARITY_PERSTEN_RSEN_Msk           (0x01UL << SCU_PARITY_PERSTEN_RSEN_Pos)                 /*!< SCU_PARITY PERSTEN: RSEN Mask           */\r
+\r
+/* ------------------------------  SCU_PARITY_PEFLAG  ----------------------------- */\r
+#define SCU_PARITY_PEFLAG_PEFPS_Pos           0                                                       /*!< SCU_PARITY PEFLAG: PEFPS Position       */\r
+#define SCU_PARITY_PEFLAG_PEFPS_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFPS_Pos)                 /*!< SCU_PARITY PEFLAG: PEFPS Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFDS1_Pos          1                                                       /*!< SCU_PARITY PEFLAG: PEFDS1 Position      */\r
+#define SCU_PARITY_PEFLAG_PEFDS1_Msk          (0x01UL << SCU_PARITY_PEFLAG_PEFDS1_Pos)                /*!< SCU_PARITY PEFLAG: PEFDS1 Mask          */\r
+#define SCU_PARITY_PEFLAG_PEFU0_Pos           8                                                       /*!< SCU_PARITY PEFLAG: PEFU0 Position       */\r
+#define SCU_PARITY_PEFLAG_PEFU0_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFU0_Pos)                 /*!< SCU_PARITY PEFLAG: PEFU0 Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFU1_Pos           9                                                       /*!< SCU_PARITY PEFLAG: PEFU1 Position       */\r
+#define SCU_PARITY_PEFLAG_PEFU1_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFU1_Pos)                 /*!< SCU_PARITY PEFLAG: PEFU1 Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFMC_Pos           12                                                      /*!< SCU_PARITY PEFLAG: PEFMC Position       */\r
+#define SCU_PARITY_PEFLAG_PEFMC_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFMC_Pos)                 /*!< SCU_PARITY PEFLAG: PEFMC Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFPPRF_Pos         13                                                      /*!< SCU_PARITY PEFLAG: PEFPPRF Position     */\r
+#define SCU_PARITY_PEFLAG_PEFPPRF_Msk         (0x01UL << SCU_PARITY_PEFLAG_PEFPPRF_Pos)               /*!< SCU_PARITY PEFLAG: PEFPPRF Mask         */\r
+#define SCU_PARITY_PEFLAG_PEUSB_Pos           16                                                      /*!< SCU_PARITY PEFLAG: PEUSB Position       */\r
+#define SCU_PARITY_PEFLAG_PEUSB_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEUSB_Pos)                 /*!< SCU_PARITY PEFLAG: PEUSB Mask           */\r
+\r
+/* ------------------------------  SCU_PARITY_PMTPR  ------------------------------ */\r
+#define SCU_PARITY_PMTPR_PWR_Pos              0                                                       /*!< SCU_PARITY PMTPR: PWR Position          */\r
+#define SCU_PARITY_PMTPR_PWR_Msk              (0x000000ffUL << SCU_PARITY_PMTPR_PWR_Pos)              /*!< SCU_PARITY PMTPR: PWR Mask              */\r
+#define SCU_PARITY_PMTPR_PRD_Pos              8                                                       /*!< SCU_PARITY PMTPR: PRD Position          */\r
+#define SCU_PARITY_PMTPR_PRD_Msk              (0x000000ffUL << SCU_PARITY_PMTPR_PRD_Pos)              /*!< SCU_PARITY PMTPR: PRD Mask              */\r
+\r
+/* ------------------------------  SCU_PARITY_PMTSR  ------------------------------ */\r
+#define SCU_PARITY_PMTSR_MTENPS_Pos           0                                                       /*!< SCU_PARITY PMTSR: MTENPS Position       */\r
+#define SCU_PARITY_PMTSR_MTENPS_Msk           (0x01UL << SCU_PARITY_PMTSR_MTENPS_Pos)                 /*!< SCU_PARITY PMTSR: MTENPS Mask           */\r
+#define SCU_PARITY_PMTSR_MTENDS1_Pos          1                                                       /*!< SCU_PARITY PMTSR: MTENDS1 Position      */\r
+#define SCU_PARITY_PMTSR_MTENDS1_Msk          (0x01UL << SCU_PARITY_PMTSR_MTENDS1_Pos)                /*!< SCU_PARITY PMTSR: MTENDS1 Mask          */\r
+#define SCU_PARITY_PMTSR_MTEU0_Pos            8                                                       /*!< SCU_PARITY PMTSR: MTEU0 Position        */\r
+#define SCU_PARITY_PMTSR_MTEU0_Msk            (0x01UL << SCU_PARITY_PMTSR_MTEU0_Pos)                  /*!< SCU_PARITY PMTSR: MTEU0 Mask            */\r
+#define SCU_PARITY_PMTSR_MTEU1_Pos            9                                                       /*!< SCU_PARITY PMTSR: MTEU1 Position        */\r
+#define SCU_PARITY_PMTSR_MTEU1_Msk            (0x01UL << SCU_PARITY_PMTSR_MTEU1_Pos)                  /*!< SCU_PARITY PMTSR: MTEU1 Mask            */\r
+#define SCU_PARITY_PMTSR_MTEMC_Pos            12                                                      /*!< SCU_PARITY PMTSR: MTEMC Position        */\r
+#define SCU_PARITY_PMTSR_MTEMC_Msk            (0x01UL << SCU_PARITY_PMTSR_MTEMC_Pos)                  /*!< SCU_PARITY PMTSR: MTEMC Mask            */\r
+#define SCU_PARITY_PMTSR_MTEPPRF_Pos          13                                                      /*!< SCU_PARITY PMTSR: MTEPPRF Position      */\r
+#define SCU_PARITY_PMTSR_MTEPPRF_Msk          (0x01UL << SCU_PARITY_PMTSR_MTEPPRF_Pos)                /*!< SCU_PARITY PMTSR: MTEPPRF Mask          */\r
+#define SCU_PARITY_PMTSR_MTUSB_Pos            16                                                      /*!< SCU_PARITY PMTSR: MTUSB Position        */\r
+#define SCU_PARITY_PMTSR_MTUSB_Msk            (0x01UL << SCU_PARITY_PMTSR_MTUSB_Pos)                  /*!< SCU_PARITY PMTSR: MTUSB Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_TRAP' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPSTAT  ----------------------------- */\r
+#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos        0                                                       /*!< SCU_TRAP TRAPSTAT: SOSCWDGT Position    */\r
+#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk        (0x01UL << SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos)              /*!< SCU_TRAP TRAPSTAT: SOSCWDGT Mask        */\r
+#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos        2                                                       /*!< SCU_TRAP TRAPSTAT: SVCOLCKT Position    */\r
+#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk        (0x01UL << SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos)              /*!< SCU_TRAP TRAPSTAT: SVCOLCKT Mask        */\r
+#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos        3                                                       /*!< SCU_TRAP TRAPSTAT: UVCOLCKT Position    */\r
+#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk        (0x01UL << SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos)              /*!< SCU_TRAP TRAPSTAT: UVCOLCKT Mask        */\r
+#define SCU_TRAP_TRAPSTAT_PET_Pos             4                                                       /*!< SCU_TRAP TRAPSTAT: PET Position         */\r
+#define SCU_TRAP_TRAPSTAT_PET_Msk             (0x01UL << SCU_TRAP_TRAPSTAT_PET_Pos)                   /*!< SCU_TRAP TRAPSTAT: PET Mask             */\r
+#define SCU_TRAP_TRAPSTAT_BRWNT_Pos           5                                                       /*!< SCU_TRAP TRAPSTAT: BRWNT Position       */\r
+#define SCU_TRAP_TRAPSTAT_BRWNT_Msk           (0x01UL << SCU_TRAP_TRAPSTAT_BRWNT_Pos)                 /*!< SCU_TRAP TRAPSTAT: BRWNT Mask           */\r
+#define SCU_TRAP_TRAPSTAT_ULPWDGT_Pos         6                                                       /*!< SCU_TRAP TRAPSTAT: ULPWDGT Position     */\r
+#define SCU_TRAP_TRAPSTAT_ULPWDGT_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_ULPWDGT_Pos)               /*!< SCU_TRAP TRAPSTAT: ULPWDGT Mask         */\r
+#define SCU_TRAP_TRAPSTAT_BWERR0T_Pos         7                                                       /*!< SCU_TRAP TRAPSTAT: BWERR0T Position     */\r
+#define SCU_TRAP_TRAPSTAT_BWERR0T_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_BWERR0T_Pos)               /*!< SCU_TRAP TRAPSTAT: BWERR0T Mask         */\r
+#define SCU_TRAP_TRAPSTAT_BWERR1T_Pos         8                                                       /*!< SCU_TRAP TRAPSTAT: BWERR1T Position     */\r
+#define SCU_TRAP_TRAPSTAT_BWERR1T_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_BWERR1T_Pos)               /*!< SCU_TRAP TRAPSTAT: BWERR1T Mask         */\r
+#define SCU_TRAP_TRAPSTAT_TEMPHIT_Pos         12                                                      /*!< SCU_TRAP TRAPSTAT: TEMPHIT Position     */\r
+#define SCU_TRAP_TRAPSTAT_TEMPHIT_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_TEMPHIT_Pos)               /*!< SCU_TRAP TRAPSTAT: TEMPHIT Mask         */\r
+#define SCU_TRAP_TRAPSTAT_TEMPLOT_Pos         13                                                      /*!< SCU_TRAP TRAPSTAT: TEMPLOT Position     */\r
+#define SCU_TRAP_TRAPSTAT_TEMPLOT_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_TEMPLOT_Pos)               /*!< SCU_TRAP TRAPSTAT: TEMPLOT Mask         */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPRAW  ------------------------------ */\r
+#define SCU_TRAP_TRAPRAW_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPRAW: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPRAW_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPRAW_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPRAW: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPRAW_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPRAW: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPRAW_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPRAW_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPRAW: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPRAW_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPRAW: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPRAW_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPRAW_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPRAW: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPRAW_PET_Pos              4                                                       /*!< SCU_TRAP TRAPRAW: PET Position          */\r
+#define SCU_TRAP_TRAPRAW_PET_Msk              (0x01UL << SCU_TRAP_TRAPRAW_PET_Pos)                    /*!< SCU_TRAP TRAPRAW: PET Mask              */\r
+#define SCU_TRAP_TRAPRAW_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPRAW: BRWNT Position        */\r
+#define SCU_TRAP_TRAPRAW_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPRAW_BRWNT_Pos)                  /*!< SCU_TRAP TRAPRAW: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPRAW_ULPWDGT_Pos          6                                                       /*!< SCU_TRAP TRAPRAW: ULPWDGT Position      */\r
+#define SCU_TRAP_TRAPRAW_ULPWDGT_Msk          (0x01UL << SCU_TRAP_TRAPRAW_ULPWDGT_Pos)                /*!< SCU_TRAP TRAPRAW: ULPWDGT Mask          */\r
+#define SCU_TRAP_TRAPRAW_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPRAW: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPRAW_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPRAW_BWERR0T_Pos)                /*!< SCU_TRAP TRAPRAW: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPRAW_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPRAW: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPRAW_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPRAW_BWERR1T_Pos)                /*!< SCU_TRAP TRAPRAW: BWERR1T Mask          */\r
+#define SCU_TRAP_TRAPRAW_TEMPHIT_Pos          12                                                      /*!< SCU_TRAP TRAPRAW: TEMPHIT Position      */\r
+#define SCU_TRAP_TRAPRAW_TEMPHIT_Msk          (0x01UL << SCU_TRAP_TRAPRAW_TEMPHIT_Pos)                /*!< SCU_TRAP TRAPRAW: TEMPHIT Mask          */\r
+#define SCU_TRAP_TRAPRAW_TEMPLOT_Pos          13                                                      /*!< SCU_TRAP TRAPRAW: TEMPLOT Position      */\r
+#define SCU_TRAP_TRAPRAW_TEMPLOT_Msk          (0x01UL << SCU_TRAP_TRAPRAW_TEMPLOT_Pos)                /*!< SCU_TRAP TRAPRAW: TEMPLOT Mask          */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPDIS  ------------------------------ */\r
+#define SCU_TRAP_TRAPDIS_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPDIS: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPDIS_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPDIS_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPDIS: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPDIS_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPDIS: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPDIS_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPDIS_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPDIS: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPDIS_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPDIS: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPDIS_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPDIS_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPDIS: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPDIS_PET_Pos              4                                                       /*!< SCU_TRAP TRAPDIS: PET Position          */\r
+#define SCU_TRAP_TRAPDIS_PET_Msk              (0x01UL << SCU_TRAP_TRAPDIS_PET_Pos)                    /*!< SCU_TRAP TRAPDIS: PET Mask              */\r
+#define SCU_TRAP_TRAPDIS_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPDIS: BRWNT Position        */\r
+#define SCU_TRAP_TRAPDIS_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPDIS_BRWNT_Pos)                  /*!< SCU_TRAP TRAPDIS: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPDIS_ULPWDGT_Pos          6                                                       /*!< SCU_TRAP TRAPDIS: ULPWDGT Position      */\r
+#define SCU_TRAP_TRAPDIS_ULPWDGT_Msk          (0x01UL << SCU_TRAP_TRAPDIS_ULPWDGT_Pos)                /*!< SCU_TRAP TRAPDIS: ULPWDGT Mask          */\r
+#define SCU_TRAP_TRAPDIS_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPDIS: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPDIS_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPDIS_BWERR0T_Pos)                /*!< SCU_TRAP TRAPDIS: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPDIS_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPDIS: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPDIS_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPDIS_BWERR1T_Pos)                /*!< SCU_TRAP TRAPDIS: BWERR1T Mask          */\r
+#define SCU_TRAP_TRAPDIS_TEMPHIT_Pos          12                                                      /*!< SCU_TRAP TRAPDIS: TEMPHIT Position      */\r
+#define SCU_TRAP_TRAPDIS_TEMPHIT_Msk          (0x01UL << SCU_TRAP_TRAPDIS_TEMPHIT_Pos)                /*!< SCU_TRAP TRAPDIS: TEMPHIT Mask          */\r
+#define SCU_TRAP_TRAPDIS_TEMPLOT_Pos          13                                                      /*!< SCU_TRAP TRAPDIS: TEMPLOT Position      */\r
+#define SCU_TRAP_TRAPDIS_TEMPLOT_Msk          (0x01UL << SCU_TRAP_TRAPDIS_TEMPLOT_Pos)                /*!< SCU_TRAP TRAPDIS: TEMPLOT Mask          */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPCLR  ------------------------------ */\r
+#define SCU_TRAP_TRAPCLR_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPCLR: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPCLR_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPCLR_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPCLR: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPCLR_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPCLR: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPCLR_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPCLR_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPCLR: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPCLR_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPCLR: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPCLR_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPCLR_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPCLR: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPCLR_PET_Pos              4                                                       /*!< SCU_TRAP TRAPCLR: PET Position          */\r
+#define SCU_TRAP_TRAPCLR_PET_Msk              (0x01UL << SCU_TRAP_TRAPCLR_PET_Pos)                    /*!< SCU_TRAP TRAPCLR: PET Mask              */\r
+#define SCU_TRAP_TRAPCLR_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPCLR: BRWNT Position        */\r
+#define SCU_TRAP_TRAPCLR_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPCLR_BRWNT_Pos)                  /*!< SCU_TRAP TRAPCLR: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPCLR_ULPWDGT_Pos          6                                                       /*!< SCU_TRAP TRAPCLR: ULPWDGT Position      */\r
+#define SCU_TRAP_TRAPCLR_ULPWDGT_Msk          (0x01UL << SCU_TRAP_TRAPCLR_ULPWDGT_Pos)                /*!< SCU_TRAP TRAPCLR: ULPWDGT Mask          */\r
+#define SCU_TRAP_TRAPCLR_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPCLR: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPCLR_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPCLR_BWERR0T_Pos)                /*!< SCU_TRAP TRAPCLR: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPCLR_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPCLR: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPCLR_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPCLR_BWERR1T_Pos)                /*!< SCU_TRAP TRAPCLR: BWERR1T Mask          */\r
+#define SCU_TRAP_TRAPCLR_TEMPHIT_Pos          12                                                      /*!< SCU_TRAP TRAPCLR: TEMPHIT Position      */\r
+#define SCU_TRAP_TRAPCLR_TEMPHIT_Msk          (0x01UL << SCU_TRAP_TRAPCLR_TEMPHIT_Pos)                /*!< SCU_TRAP TRAPCLR: TEMPHIT Mask          */\r
+#define SCU_TRAP_TRAPCLR_TEMPLOT_Pos          13                                                      /*!< SCU_TRAP TRAPCLR: TEMPLOT Position      */\r
+#define SCU_TRAP_TRAPCLR_TEMPLOT_Msk          (0x01UL << SCU_TRAP_TRAPCLR_TEMPLOT_Pos)                /*!< SCU_TRAP TRAPCLR: TEMPLOT Mask          */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPSET  ------------------------------ */\r
+#define SCU_TRAP_TRAPSET_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPSET: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPSET_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPSET_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPSET: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPSET_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPSET: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPSET_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPSET_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPSET: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPSET_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPSET: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPSET_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPSET_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPSET: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPSET_PET_Pos              4                                                       /*!< SCU_TRAP TRAPSET: PET Position          */\r
+#define SCU_TRAP_TRAPSET_PET_Msk              (0x01UL << SCU_TRAP_TRAPSET_PET_Pos)                    /*!< SCU_TRAP TRAPSET: PET Mask              */\r
+#define SCU_TRAP_TRAPSET_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPSET: BRWNT Position        */\r
+#define SCU_TRAP_TRAPSET_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPSET_BRWNT_Pos)                  /*!< SCU_TRAP TRAPSET: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPSET_ULPWDT_Pos           6                                                       /*!< SCU_TRAP TRAPSET: ULPWDT Position       */\r
+#define SCU_TRAP_TRAPSET_ULPWDT_Msk           (0x01UL << SCU_TRAP_TRAPSET_ULPWDT_Pos)                 /*!< SCU_TRAP TRAPSET: ULPWDT Mask           */\r
+#define SCU_TRAP_TRAPSET_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPSET: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPSET_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPSET_BWERR0T_Pos)                /*!< SCU_TRAP TRAPSET: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPSET_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPSET: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPSET_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPSET_BWERR1T_Pos)                /*!< SCU_TRAP TRAPSET: BWERR1T Mask          */\r
+#define SCU_TRAP_TRAPSET_TEMPHIT_Pos          12                                                      /*!< SCU_TRAP TRAPSET: TEMPHIT Position      */\r
+#define SCU_TRAP_TRAPSET_TEMPHIT_Msk          (0x01UL << SCU_TRAP_TRAPSET_TEMPHIT_Pos)                /*!< SCU_TRAP TRAPSET: TEMPHIT Mask          */\r
+#define SCU_TRAP_TRAPSET_TEMPLOT_Pos          13                                                      /*!< SCU_TRAP TRAPSET: TEMPLOT Position      */\r
+#define SCU_TRAP_TRAPSET_TEMPLOT_Msk          (0x01UL << SCU_TRAP_TRAPSET_TEMPLOT_Pos)                /*!< SCU_TRAP TRAPSET: TEMPLOT Mask          */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================     struct 'SCU_HIBERNATE' Position & Mask     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------  SCU_HIBERNATE_HDSTAT  ---------------------------- */\r
+#define SCU_HIBERNATE_HDSTAT_EPEV_Pos         0                                                       /*!< SCU_HIBERNATE HDSTAT: EPEV Position     */\r
+#define SCU_HIBERNATE_HDSTAT_EPEV_Msk         (0x01UL << SCU_HIBERNATE_HDSTAT_EPEV_Pos)               /*!< SCU_HIBERNATE HDSTAT: EPEV Mask         */\r
+#define SCU_HIBERNATE_HDSTAT_ENEV_Pos         1                                                       /*!< SCU_HIBERNATE HDSTAT: ENEV Position     */\r
+#define SCU_HIBERNATE_HDSTAT_ENEV_Msk         (0x01UL << SCU_HIBERNATE_HDSTAT_ENEV_Pos)               /*!< SCU_HIBERNATE HDSTAT: ENEV Mask         */\r
+#define SCU_HIBERNATE_HDSTAT_RTCEV_Pos        2                                                       /*!< SCU_HIBERNATE HDSTAT: RTCEV Position    */\r
+#define SCU_HIBERNATE_HDSTAT_RTCEV_Msk        (0x01UL << SCU_HIBERNATE_HDSTAT_RTCEV_Pos)              /*!< SCU_HIBERNATE HDSTAT: RTCEV Mask        */\r
+#define SCU_HIBERNATE_HDSTAT_ULPWDG_Pos       3                                                       /*!< SCU_HIBERNATE HDSTAT: ULPWDG Position   */\r
+#define SCU_HIBERNATE_HDSTAT_ULPWDG_Msk       (0x01UL << SCU_HIBERNATE_HDSTAT_ULPWDG_Pos)             /*!< SCU_HIBERNATE HDSTAT: ULPWDG Mask       */\r
+#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos      4                                                       /*!< SCU_HIBERNATE HDSTAT: HIBNOUT Position  */\r
+#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk      (0x01UL << SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos)            /*!< SCU_HIBERNATE HDSTAT: HIBNOUT Mask      */\r
+#define SCU_HIBERNATE_HDSTAT_VBATPEV_Pos      8                                                       /*!< SCU_HIBERNATE HDSTAT: VBATPEV Position  */\r
+#define SCU_HIBERNATE_HDSTAT_VBATPEV_Msk      (0x01UL << SCU_HIBERNATE_HDSTAT_VBATPEV_Pos)            /*!< SCU_HIBERNATE HDSTAT: VBATPEV Mask      */\r
+#define SCU_HIBERNATE_HDSTAT_VBATNEV_Pos      9                                                       /*!< SCU_HIBERNATE HDSTAT: VBATNEV Position  */\r
+#define SCU_HIBERNATE_HDSTAT_VBATNEV_Msk      (0x01UL << SCU_HIBERNATE_HDSTAT_VBATNEV_Pos)            /*!< SCU_HIBERNATE HDSTAT: VBATNEV Mask      */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos   10                                                      /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV Position */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Msk   (0x01UL << SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos)         /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV Mask   */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos   11                                                      /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV Position */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Msk   (0x01UL << SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos)         /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV Mask   */\r
+\r
+/* -----------------------------  SCU_HIBERNATE_HDCLR  ---------------------------- */\r
+#define SCU_HIBERNATE_HDCLR_EPEV_Pos          0                                                       /*!< SCU_HIBERNATE HDCLR: EPEV Position      */\r
+#define SCU_HIBERNATE_HDCLR_EPEV_Msk          (0x01UL << SCU_HIBERNATE_HDCLR_EPEV_Pos)                /*!< SCU_HIBERNATE HDCLR: EPEV Mask          */\r
+#define SCU_HIBERNATE_HDCLR_ENEV_Pos          1                                                       /*!< SCU_HIBERNATE HDCLR: ENEV Position      */\r
+#define SCU_HIBERNATE_HDCLR_ENEV_Msk          (0x01UL << SCU_HIBERNATE_HDCLR_ENEV_Pos)                /*!< SCU_HIBERNATE HDCLR: ENEV Mask          */\r
+#define SCU_HIBERNATE_HDCLR_RTCEV_Pos         2                                                       /*!< SCU_HIBERNATE HDCLR: RTCEV Position     */\r
+#define SCU_HIBERNATE_HDCLR_RTCEV_Msk         (0x01UL << SCU_HIBERNATE_HDCLR_RTCEV_Pos)               /*!< SCU_HIBERNATE HDCLR: RTCEV Mask         */\r
+#define SCU_HIBERNATE_HDCLR_ULPWDG_Pos        3                                                       /*!< SCU_HIBERNATE HDCLR: ULPWDG Position    */\r
+#define SCU_HIBERNATE_HDCLR_ULPWDG_Msk        (0x01UL << SCU_HIBERNATE_HDCLR_ULPWDG_Pos)              /*!< SCU_HIBERNATE HDCLR: ULPWDG Mask        */\r
+#define SCU_HIBERNATE_HDCLR_VBATPEV_Pos       8                                                       /*!< SCU_HIBERNATE HDCLR: VBATPEV Position   */\r
+#define SCU_HIBERNATE_HDCLR_VBATPEV_Msk       (0x01UL << SCU_HIBERNATE_HDCLR_VBATPEV_Pos)             /*!< SCU_HIBERNATE HDCLR: VBATPEV Mask       */\r
+#define SCU_HIBERNATE_HDCLR_VBATNEV_Pos       9                                                       /*!< SCU_HIBERNATE HDCLR: VBATNEV Position   */\r
+#define SCU_HIBERNATE_HDCLR_VBATNEV_Msk       (0x01UL << SCU_HIBERNATE_HDCLR_VBATNEV_Pos)             /*!< SCU_HIBERNATE HDCLR: VBATNEV Mask       */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Pos    10                                                      /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV Position */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Msk    (0x01UL << SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Pos)          /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV Mask    */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Pos    11                                                      /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV Position */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Msk    (0x01UL << SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Pos)          /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV Mask    */\r
+\r
+/* -----------------------------  SCU_HIBERNATE_HDSET  ---------------------------- */\r
+#define SCU_HIBERNATE_HDSET_EPEV_Pos          0                                                       /*!< SCU_HIBERNATE HDSET: EPEV Position      */\r
+#define SCU_HIBERNATE_HDSET_EPEV_Msk          (0x01UL << SCU_HIBERNATE_HDSET_EPEV_Pos)                /*!< SCU_HIBERNATE HDSET: EPEV Mask          */\r
+#define SCU_HIBERNATE_HDSET_ENEV_Pos          1                                                       /*!< SCU_HIBERNATE HDSET: ENEV Position      */\r
+#define SCU_HIBERNATE_HDSET_ENEV_Msk          (0x01UL << SCU_HIBERNATE_HDSET_ENEV_Pos)                /*!< SCU_HIBERNATE HDSET: ENEV Mask          */\r
+#define SCU_HIBERNATE_HDSET_RTCEV_Pos         2                                                       /*!< SCU_HIBERNATE HDSET: RTCEV Position     */\r
+#define SCU_HIBERNATE_HDSET_RTCEV_Msk         (0x01UL << SCU_HIBERNATE_HDSET_RTCEV_Pos)               /*!< SCU_HIBERNATE HDSET: RTCEV Mask         */\r
+#define SCU_HIBERNATE_HDSET_ULPWDG_Pos        3                                                       /*!< SCU_HIBERNATE HDSET: ULPWDG Position    */\r
+#define SCU_HIBERNATE_HDSET_ULPWDG_Msk        (0x01UL << SCU_HIBERNATE_HDSET_ULPWDG_Pos)              /*!< SCU_HIBERNATE HDSET: ULPWDG Mask        */\r
+#define SCU_HIBERNATE_HDSET_VBATPEV_Pos       8                                                       /*!< SCU_HIBERNATE HDSET: VBATPEV Position   */\r
+#define SCU_HIBERNATE_HDSET_VBATPEV_Msk       (0x01UL << SCU_HIBERNATE_HDSET_VBATPEV_Pos)             /*!< SCU_HIBERNATE HDSET: VBATPEV Mask       */\r
+#define SCU_HIBERNATE_HDSET_VBATNEV_Pos       9                                                       /*!< SCU_HIBERNATE HDSET: VBATNEV Position   */\r
+#define SCU_HIBERNATE_HDSET_VBATNEV_Msk       (0x01UL << SCU_HIBERNATE_HDSET_VBATNEV_Pos)             /*!< SCU_HIBERNATE HDSET: VBATNEV Mask       */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Pos    10                                                      /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV Position */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Msk    (0x01UL << SCU_HIBERNATE_HDSET_AHIBIO0PEV_Pos)          /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV Mask    */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Pos    11                                                      /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV Position */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Msk    (0x01UL << SCU_HIBERNATE_HDSET_AHIBIO0NEV_Pos)          /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV Mask    */\r
+\r
+/* -----------------------------  SCU_HIBERNATE_HDCR  ----------------------------- */\r
+#define SCU_HIBERNATE_HDCR_WKPEP_Pos          0                                                       /*!< SCU_HIBERNATE HDCR: WKPEP Position      */\r
+#define SCU_HIBERNATE_HDCR_WKPEP_Msk          (0x01UL << SCU_HIBERNATE_HDCR_WKPEP_Pos)                /*!< SCU_HIBERNATE HDCR: WKPEP Mask          */\r
+#define SCU_HIBERNATE_HDCR_WKPEN_Pos          1                                                       /*!< SCU_HIBERNATE HDCR: WKPEN Position      */\r
+#define SCU_HIBERNATE_HDCR_WKPEN_Msk          (0x01UL << SCU_HIBERNATE_HDCR_WKPEN_Pos)                /*!< SCU_HIBERNATE HDCR: WKPEN Mask          */\r
+#define SCU_HIBERNATE_HDCR_RTCE_Pos           2                                                       /*!< SCU_HIBERNATE HDCR: RTCE Position       */\r
+#define SCU_HIBERNATE_HDCR_RTCE_Msk           (0x01UL << SCU_HIBERNATE_HDCR_RTCE_Pos)                 /*!< SCU_HIBERNATE HDCR: RTCE Mask           */\r
+#define SCU_HIBERNATE_HDCR_ULPWDGEN_Pos       3                                                       /*!< SCU_HIBERNATE HDCR: ULPWDGEN Position   */\r
+#define SCU_HIBERNATE_HDCR_ULPWDGEN_Msk       (0x01UL << SCU_HIBERNATE_HDCR_ULPWDGEN_Pos)             /*!< SCU_HIBERNATE HDCR: ULPWDGEN Mask       */\r
+#define SCU_HIBERNATE_HDCR_HIB_Pos            4                                                       /*!< SCU_HIBERNATE HDCR: HIB Position        */\r
+#define SCU_HIBERNATE_HDCR_HIB_Msk            (0x01UL << SCU_HIBERNATE_HDCR_HIB_Pos)                  /*!< SCU_HIBERNATE HDCR: HIB Mask            */\r
+#define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Pos    5                                                       /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL Position */\r
+#define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk    (0x01UL << SCU_HIBERNATE_HDCR_XTALGPI1SEL_Pos)          /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL Mask    */\r
+#define SCU_HIBERNATE_HDCR_RCS_Pos            6                                                       /*!< SCU_HIBERNATE HDCR: RCS Position        */\r
+#define SCU_HIBERNATE_HDCR_RCS_Msk            (0x01UL << SCU_HIBERNATE_HDCR_RCS_Pos)                  /*!< SCU_HIBERNATE HDCR: RCS Mask            */\r
+#define SCU_HIBERNATE_HDCR_STDBYSEL_Pos       7                                                       /*!< SCU_HIBERNATE HDCR: STDBYSEL Position   */\r
+#define SCU_HIBERNATE_HDCR_STDBYSEL_Msk       (0x01UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos)             /*!< SCU_HIBERNATE HDCR: STDBYSEL Mask       */\r
+#define SCU_HIBERNATE_HDCR_WKUPSEL_Pos        8                                                       /*!< SCU_HIBERNATE HDCR: WKUPSEL Position    */\r
+#define SCU_HIBERNATE_HDCR_WKUPSEL_Msk        (0x01UL << SCU_HIBERNATE_HDCR_WKUPSEL_Pos)              /*!< SCU_HIBERNATE HDCR: WKUPSEL Mask        */\r
+#define SCU_HIBERNATE_HDCR_GPI0SEL_Pos        10                                                      /*!< SCU_HIBERNATE HDCR: GPI0SEL Position    */\r
+#define SCU_HIBERNATE_HDCR_GPI0SEL_Msk        (0x01UL << SCU_HIBERNATE_HDCR_GPI0SEL_Pos)              /*!< SCU_HIBERNATE HDCR: GPI0SEL Mask        */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0POL_Pos      12                                                      /*!< SCU_HIBERNATE HDCR: HIBIO0POL Position  */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0POL_Msk      (0x01UL << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos)            /*!< SCU_HIBERNATE HDCR: HIBIO0POL Mask      */\r
+#define SCU_HIBERNATE_HDCR_ADIG0SEL_Pos       14                                                      /*!< SCU_HIBERNATE HDCR: ADIG0SEL Position   */\r
+#define SCU_HIBERNATE_HDCR_ADIG0SEL_Msk       (0x01UL << SCU_HIBERNATE_HDCR_ADIG0SEL_Pos)             /*!< SCU_HIBERNATE HDCR: ADIG0SEL Mask       */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos      16                                                      /*!< SCU_HIBERNATE HDCR: HIBIO0SEL Position  */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk      (0x0fUL << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos)            /*!< SCU_HIBERNATE HDCR: HIBIO0SEL Mask      */\r
+#define SCU_HIBERNATE_HDCR_VBATLO_Pos         24                                                      /*!< SCU_HIBERNATE HDCR: VBATLO Position     */\r
+#define SCU_HIBERNATE_HDCR_VBATLO_Msk         (0x01UL << SCU_HIBERNATE_HDCR_VBATLO_Pos)               /*!< SCU_HIBERNATE HDCR: VBATLO Mask         */\r
+#define SCU_HIBERNATE_HDCR_VBATHI_Pos         25                                                      /*!< SCU_HIBERNATE HDCR: VBATHI Position     */\r
+#define SCU_HIBERNATE_HDCR_VBATHI_Msk         (0x01UL << SCU_HIBERNATE_HDCR_VBATHI_Pos)               /*!< SCU_HIBERNATE HDCR: VBATHI Mask         */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos      26                                                      /*!< SCU_HIBERNATE HDCR: AHIBIO0LO Position  */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO0LO_Msk      (0x01UL << SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos)            /*!< SCU_HIBERNATE HDCR: AHIBIO0LO Mask      */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos      27                                                      /*!< SCU_HIBERNATE HDCR: AHIBIO0HI Position  */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO0HI_Msk      (0x01UL << SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos)            /*!< SCU_HIBERNATE HDCR: AHIBIO0HI Mask      */\r
+\r
+/* ---------------------------  SCU_HIBERNATE_OSCSICTRL  -------------------------- */\r
+#define SCU_HIBERNATE_OSCSICTRL_PWD_Pos       0                                                       /*!< SCU_HIBERNATE OSCSICTRL: PWD Position   */\r
+#define SCU_HIBERNATE_OSCSICTRL_PWD_Msk       (0x01UL << SCU_HIBERNATE_OSCSICTRL_PWD_Pos)             /*!< SCU_HIBERNATE OSCSICTRL: PWD Mask       */\r
+\r
+/* ---------------------------  SCU_HIBERNATE_OSCULSTAT  -------------------------- */\r
+#define SCU_HIBERNATE_OSCULSTAT_X1D_Pos       0                                                       /*!< SCU_HIBERNATE OSCULSTAT: X1D Position   */\r
+#define SCU_HIBERNATE_OSCULSTAT_X1D_Msk       (0x01UL << SCU_HIBERNATE_OSCULSTAT_X1D_Pos)             /*!< SCU_HIBERNATE OSCULSTAT: X1D Mask       */\r
+\r
+/* ---------------------------  SCU_HIBERNATE_OSCULCTRL  -------------------------- */\r
+#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos     0                                                       /*!< SCU_HIBERNATE OSCULCTRL: X1DEN Position */\r
+#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk     (0x01UL << SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos)           /*!< SCU_HIBERNATE OSCULCTRL: X1DEN Mask     */\r
+#define SCU_HIBERNATE_OSCULCTRL_MODE_Pos      4                                                       /*!< SCU_HIBERNATE OSCULCTRL: MODE Position  */\r
+#define SCU_HIBERNATE_OSCULCTRL_MODE_Msk      (0x03UL << SCU_HIBERNATE_OSCULCTRL_MODE_Pos)            /*!< SCU_HIBERNATE OSCULCTRL: MODE Mask      */\r
+\r
+/* ---------------------------  SCU_HIBERNATE_LPACCONF  --------------------------- */\r
+#define SCU_HIBERNATE_LPACCONF_CMPEN_Pos      0                                                       /*!< SCU_HIBERNATE LPACCONF: CMPEN Position  */\r
+#define SCU_HIBERNATE_LPACCONF_CMPEN_Msk      (0x07UL << SCU_HIBERNATE_LPACCONF_CMPEN_Pos)            /*!< SCU_HIBERNATE LPACCONF: CMPEN Mask      */\r
+#define SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos    4                                                       /*!< SCU_HIBERNATE LPACCONF: TRIGSEL Position */\r
+#define SCU_HIBERNATE_LPACCONF_TRIGSEL_Msk    (0x07UL << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos)          /*!< SCU_HIBERNATE LPACCONF: TRIGSEL Mask    */\r
+#define SCU_HIBERNATE_LPACCONF_CONVDEL_Pos    12                                                      /*!< SCU_HIBERNATE LPACCONF: CONVDEL Position */\r
+#define SCU_HIBERNATE_LPACCONF_CONVDEL_Msk    (0x01UL << SCU_HIBERNATE_LPACCONF_CONVDEL_Pos)          /*!< SCU_HIBERNATE LPACCONF: CONVDEL Mask    */\r
+#define SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos  16                                                      /*!< SCU_HIBERNATE LPACCONF: INTERVCNT Position */\r
+#define SCU_HIBERNATE_LPACCONF_INTERVCNT_Msk  (0x00000fffUL << SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos)  /*!< SCU_HIBERNATE LPACCONF: INTERVCNT Mask  */\r
+#define SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos  28                                                      /*!< SCU_HIBERNATE LPACCONF: SETTLECNT Position */\r
+#define SCU_HIBERNATE_LPACCONF_SETTLECNT_Msk  (0x0fUL << SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos)        /*!< SCU_HIBERNATE LPACCONF: SETTLECNT Mask  */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_LPACTH0  --------------------------- */\r
+#define SCU_HIBERNATE_LPACTH0_VBATLO_Pos      0                                                       /*!< SCU_HIBERNATE LPACTH0: VBATLO Position  */\r
+#define SCU_HIBERNATE_LPACTH0_VBATLO_Msk      (0x3fUL << SCU_HIBERNATE_LPACTH0_VBATLO_Pos)            /*!< SCU_HIBERNATE LPACTH0: VBATLO Mask      */\r
+#define SCU_HIBERNATE_LPACTH0_VBATHI_Pos      8                                                       /*!< SCU_HIBERNATE LPACTH0: VBATHI Position  */\r
+#define SCU_HIBERNATE_LPACTH0_VBATHI_Msk      (0x3fUL << SCU_HIBERNATE_LPACTH0_VBATHI_Pos)            /*!< SCU_HIBERNATE LPACTH0: VBATHI Mask      */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_LPACST  ---------------------------- */\r
+#define SCU_HIBERNATE_LPACST_VBATSCMP_Pos     0                                                       /*!< SCU_HIBERNATE LPACST: VBATSCMP Position */\r
+#define SCU_HIBERNATE_LPACST_VBATSCMP_Msk     (0x01UL << SCU_HIBERNATE_LPACST_VBATSCMP_Pos)           /*!< SCU_HIBERNATE LPACST: VBATSCMP Mask     */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Pos  1                                                       /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP Position */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Msk  (0x01UL << SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Pos)        /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP Mask  */\r
+#define SCU_HIBERNATE_LPACST_VBATVAL_Pos      16                                                      /*!< SCU_HIBERNATE LPACST: VBATVAL Position  */\r
+#define SCU_HIBERNATE_LPACST_VBATVAL_Msk      (0x01UL << SCU_HIBERNATE_LPACST_VBATVAL_Pos)            /*!< SCU_HIBERNATE LPACST: VBATVAL Mask      */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Pos   17                                                      /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL Position */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Msk   (0x01UL << SCU_HIBERNATE_LPACST_AHIBIO0VAL_Pos)         /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL Mask   */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_LPACCLR  --------------------------- */\r
+#define SCU_HIBERNATE_LPACCLR_VBATSCMP_Pos    0                                                       /*!< SCU_HIBERNATE LPACCLR: VBATSCMP Position */\r
+#define SCU_HIBERNATE_LPACCLR_VBATSCMP_Msk    (0x01UL << SCU_HIBERNATE_LPACCLR_VBATSCMP_Pos)          /*!< SCU_HIBERNATE LPACCLR: VBATSCMP Mask    */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Pos 1                                                       /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP Position */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Pos)       /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP Mask */\r
+#define SCU_HIBERNATE_LPACCLR_VBATVAL_Pos     16                                                      /*!< SCU_HIBERNATE LPACCLR: VBATVAL Position */\r
+#define SCU_HIBERNATE_LPACCLR_VBATVAL_Msk     (0x01UL << SCU_HIBERNATE_LPACCLR_VBATVAL_Pos)           /*!< SCU_HIBERNATE LPACCLR: VBATVAL Mask     */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Pos  17                                                      /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL Position */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Msk  (0x01UL << SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Pos)        /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL Mask  */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_LPACSET  --------------------------- */\r
+#define SCU_HIBERNATE_LPACSET_VBATSCMP_Pos    0                                                       /*!< SCU_HIBERNATE LPACSET: VBATSCMP Position */\r
+#define SCU_HIBERNATE_LPACSET_VBATSCMP_Msk    (0x01UL << SCU_HIBERNATE_LPACSET_VBATSCMP_Pos)          /*!< SCU_HIBERNATE LPACSET: VBATSCMP Mask    */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Pos 1                                                       /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP Position */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Pos)       /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP Mask */\r
+#define SCU_HIBERNATE_LPACSET_VBATVAL_Pos     16                                                      /*!< SCU_HIBERNATE LPACSET: VBATVAL Position */\r
+#define SCU_HIBERNATE_LPACSET_VBATVAL_Msk     (0x01UL << SCU_HIBERNATE_LPACSET_VBATVAL_Pos)           /*!< SCU_HIBERNATE LPACSET: VBATVAL Mask     */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Pos  17                                                      /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL Position */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Msk  (0x01UL << SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Pos)        /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL Mask  */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_HINTST  ---------------------------- */\r
+#define SCU_HIBERNATE_HINTST_HIBNINT_Pos      0                                                       /*!< SCU_HIBERNATE HINTST: HIBNINT Position  */\r
+#define SCU_HIBERNATE_HINTST_HIBNINT_Msk      (0x01UL << SCU_HIBERNATE_HINTST_HIBNINT_Pos)            /*!< SCU_HIBERNATE HINTST: HIBNINT Mask      */\r
+#define SCU_HIBERNATE_HINTST_FLASHOFF_Pos     2                                                       /*!< SCU_HIBERNATE HINTST: FLASHOFF Position */\r
+#define SCU_HIBERNATE_HINTST_FLASHOFF_Msk     (0x01UL << SCU_HIBERNATE_HINTST_FLASHOFF_Pos)           /*!< SCU_HIBERNATE HINTST: FLASHOFF Mask     */\r
+#define SCU_HIBERNATE_HINTST_FLASHPD_Pos      3                                                       /*!< SCU_HIBERNATE HINTST: FLASHPD Position  */\r
+#define SCU_HIBERNATE_HINTST_FLASHPD_Msk      (0x01UL << SCU_HIBERNATE_HINTST_FLASHPD_Pos)            /*!< SCU_HIBERNATE HINTST: FLASHPD Mask      */\r
+#define SCU_HIBERNATE_HINTST_POFFD_Pos        4                                                       /*!< SCU_HIBERNATE HINTST: POFFD Position    */\r
+#define SCU_HIBERNATE_HINTST_POFFD_Msk        (0x01UL << SCU_HIBERNATE_HINTST_POFFD_Pos)              /*!< SCU_HIBERNATE HINTST: POFFD Mask        */\r
+#define SCU_HIBERNATE_HINTST_PPODEL_Pos       16                                                      /*!< SCU_HIBERNATE HINTST: PPODEL Position   */\r
+#define SCU_HIBERNATE_HINTST_PPODEL_Msk       (0x03UL << SCU_HIBERNATE_HINTST_PPODEL_Pos)             /*!< SCU_HIBERNATE HINTST: PPODEL Mask       */\r
+#define SCU_HIBERNATE_HINTST_POFFH_Pos        20                                                      /*!< SCU_HIBERNATE HINTST: POFFH Position    */\r
+#define SCU_HIBERNATE_HINTST_POFFH_Msk        (0x01UL << SCU_HIBERNATE_HINTST_POFFH_Pos)              /*!< SCU_HIBERNATE HINTST: POFFH Mask        */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_HINTCLR  --------------------------- */\r
+#define SCU_HIBERNATE_HINTCLR_HIBNINT_Pos     0                                                       /*!< SCU_HIBERNATE HINTCLR: HIBNINT Position */\r
+#define SCU_HIBERNATE_HINTCLR_HIBNINT_Msk     (0x01UL << SCU_HIBERNATE_HINTCLR_HIBNINT_Pos)           /*!< SCU_HIBERNATE HINTCLR: HIBNINT Mask     */\r
+#define SCU_HIBERNATE_HINTCLR_FLASHOFF_Pos    2                                                       /*!< SCU_HIBERNATE HINTCLR: FLASHOFF Position */\r
+#define SCU_HIBERNATE_HINTCLR_FLASHOFF_Msk    (0x01UL << SCU_HIBERNATE_HINTCLR_FLASHOFF_Pos)          /*!< SCU_HIBERNATE HINTCLR: FLASHOFF Mask    */\r
+#define SCU_HIBERNATE_HINTCLR_FLASHPD_Pos     3                                                       /*!< SCU_HIBERNATE HINTCLR: FLASHPD Position */\r
+#define SCU_HIBERNATE_HINTCLR_FLASHPD_Msk     (0x01UL << SCU_HIBERNATE_HINTCLR_FLASHPD_Pos)           /*!< SCU_HIBERNATE HINTCLR: FLASHPD Mask     */\r
+#define SCU_HIBERNATE_HINTCLR_POFFD_Pos       4                                                       /*!< SCU_HIBERNATE HINTCLR: POFFD Position   */\r
+#define SCU_HIBERNATE_HINTCLR_POFFD_Msk       (0x01UL << SCU_HIBERNATE_HINTCLR_POFFD_Pos)             /*!< SCU_HIBERNATE HINTCLR: POFFD Mask       */\r
+#define SCU_HIBERNATE_HINTCLR_PPODEL_Pos      16                                                      /*!< SCU_HIBERNATE HINTCLR: PPODEL Position  */\r
+#define SCU_HIBERNATE_HINTCLR_PPODEL_Msk      (0x03UL << SCU_HIBERNATE_HINTCLR_PPODEL_Pos)            /*!< SCU_HIBERNATE HINTCLR: PPODEL Mask      */\r
+#define SCU_HIBERNATE_HINTCLR_POFFH_Pos       20                                                      /*!< SCU_HIBERNATE HINTCLR: POFFH Position   */\r
+#define SCU_HIBERNATE_HINTCLR_POFFH_Msk       (0x01UL << SCU_HIBERNATE_HINTCLR_POFFH_Pos)             /*!< SCU_HIBERNATE HINTCLR: POFFH Mask       */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_HINTSET  --------------------------- */\r
+#define SCU_HIBERNATE_HINTSET_HIBNINT_Pos     0                                                       /*!< SCU_HIBERNATE HINTSET: HIBNINT Position */\r
+#define SCU_HIBERNATE_HINTSET_HIBNINT_Msk     (0x01UL << SCU_HIBERNATE_HINTSET_HIBNINT_Pos)           /*!< SCU_HIBERNATE HINTSET: HIBNINT Mask     */\r
+#define SCU_HIBERNATE_HINTSET_VCOREOFF_Pos    1                                                       /*!< SCU_HIBERNATE HINTSET: VCOREOFF Position */\r
+#define SCU_HIBERNATE_HINTSET_VCOREOFF_Msk    (0x01UL << SCU_HIBERNATE_HINTSET_VCOREOFF_Pos)          /*!< SCU_HIBERNATE HINTSET: VCOREOFF Mask    */\r
+#define SCU_HIBERNATE_HINTSET_FLASHOFF_Pos    2                                                       /*!< SCU_HIBERNATE HINTSET: FLASHOFF Position */\r
+#define SCU_HIBERNATE_HINTSET_FLASHOFF_Msk    (0x01UL << SCU_HIBERNATE_HINTSET_FLASHOFF_Pos)          /*!< SCU_HIBERNATE HINTSET: FLASHOFF Mask    */\r
+#define SCU_HIBERNATE_HINTSET_FLASHPD_Pos     3                                                       /*!< SCU_HIBERNATE HINTSET: FLASHPD Position */\r
+#define SCU_HIBERNATE_HINTSET_FLASHPD_Msk     (0x01UL << SCU_HIBERNATE_HINTSET_FLASHPD_Pos)           /*!< SCU_HIBERNATE HINTSET: FLASHPD Mask     */\r
+#define SCU_HIBERNATE_HINTSET_POFFD_Pos       4                                                       /*!< SCU_HIBERNATE HINTSET: POFFD Position   */\r
+#define SCU_HIBERNATE_HINTSET_POFFD_Msk       (0x01UL << SCU_HIBERNATE_HINTSET_POFFD_Pos)             /*!< SCU_HIBERNATE HINTSET: POFFD Mask       */\r
+#define SCU_HIBERNATE_HINTSET_PPODEL_Pos      16                                                      /*!< SCU_HIBERNATE HINTSET: PPODEL Position  */\r
+#define SCU_HIBERNATE_HINTSET_PPODEL_Msk      (0x03UL << SCU_HIBERNATE_HINTSET_PPODEL_Pos)            /*!< SCU_HIBERNATE HINTSET: PPODEL Mask      */\r
+#define SCU_HIBERNATE_HINTSET_POFFH_Pos       20                                                      /*!< SCU_HIBERNATE HINTSET: POFFH Position   */\r
+#define SCU_HIBERNATE_HINTSET_POFFH_Msk       (0x01UL << SCU_HIBERNATE_HINTSET_POFFH_Pos)             /*!< SCU_HIBERNATE HINTSET: POFFH Mask       */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       struct 'SCU_POWER' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_POWER_PWRSTAT  ----------------------------- */\r
+#define SCU_POWER_PWRSTAT_HIBEN_Pos           0                                                       /*!< SCU_POWER PWRSTAT: HIBEN Position       */\r
+#define SCU_POWER_PWRSTAT_HIBEN_Msk           (0x01UL << SCU_POWER_PWRSTAT_HIBEN_Pos)                 /*!< SCU_POWER PWRSTAT: HIBEN Mask           */\r
+#define SCU_POWER_PWRSTAT_USBPHYPDQ_Pos       16                                                      /*!< SCU_POWER PWRSTAT: USBPHYPDQ Position   */\r
+#define SCU_POWER_PWRSTAT_USBPHYPDQ_Msk       (0x01UL << SCU_POWER_PWRSTAT_USBPHYPDQ_Pos)             /*!< SCU_POWER PWRSTAT: USBPHYPDQ Mask       */\r
+#define SCU_POWER_PWRSTAT_USBPUWQ_Pos         18                                                      /*!< SCU_POWER PWRSTAT: USBPUWQ Position     */\r
+#define SCU_POWER_PWRSTAT_USBPUWQ_Msk         (0x01UL << SCU_POWER_PWRSTAT_USBPUWQ_Pos)               /*!< SCU_POWER PWRSTAT: USBPUWQ Mask         */\r
+\r
+/* ------------------------------  SCU_POWER_PWRSET  ------------------------------ */\r
+#define SCU_POWER_PWRSET_HIB_Pos              0                                                       /*!< SCU_POWER PWRSET: HIB Position          */\r
+#define SCU_POWER_PWRSET_HIB_Msk              (0x01UL << SCU_POWER_PWRSET_HIB_Pos)                    /*!< SCU_POWER PWRSET: HIB Mask              */\r
+#define SCU_POWER_PWRSET_USBPHYPDQ_Pos        16                                                      /*!< SCU_POWER PWRSET: USBPHYPDQ Position    */\r
+#define SCU_POWER_PWRSET_USBPHYPDQ_Msk        (0x01UL << SCU_POWER_PWRSET_USBPHYPDQ_Pos)              /*!< SCU_POWER PWRSET: USBPHYPDQ Mask        */\r
+#define SCU_POWER_PWRSET_USBPUWQ_Pos          18                                                      /*!< SCU_POWER PWRSET: USBPUWQ Position      */\r
+#define SCU_POWER_PWRSET_USBPUWQ_Msk          (0x01UL << SCU_POWER_PWRSET_USBPUWQ_Pos)                /*!< SCU_POWER PWRSET: USBPUWQ Mask          */\r
+\r
+/* ------------------------------  SCU_POWER_PWRCLR  ------------------------------ */\r
+#define SCU_POWER_PWRCLR_HIB_Pos              0                                                       /*!< SCU_POWER PWRCLR: HIB Position          */\r
+#define SCU_POWER_PWRCLR_HIB_Msk              (0x01UL << SCU_POWER_PWRCLR_HIB_Pos)                    /*!< SCU_POWER PWRCLR: HIB Mask              */\r
+#define SCU_POWER_PWRCLR_USBPHYPDQ_Pos        16                                                      /*!< SCU_POWER PWRCLR: USBPHYPDQ Position    */\r
+#define SCU_POWER_PWRCLR_USBPHYPDQ_Msk        (0x01UL << SCU_POWER_PWRCLR_USBPHYPDQ_Pos)              /*!< SCU_POWER PWRCLR: USBPHYPDQ Mask        */\r
+#define SCU_POWER_PWRCLR_USBPUWQ_Pos          18                                                      /*!< SCU_POWER PWRCLR: USBPUWQ Position      */\r
+#define SCU_POWER_PWRCLR_USBPUWQ_Msk          (0x01UL << SCU_POWER_PWRCLR_USBPUWQ_Pos)                /*!< SCU_POWER PWRCLR: USBPUWQ Mask          */\r
+\r
+/* ------------------------------  SCU_POWER_EVRSTAT  ----------------------------- */\r
+#define SCU_POWER_EVRSTAT_OV13_Pos            1                                                       /*!< SCU_POWER EVRSTAT: OV13 Position        */\r
+#define SCU_POWER_EVRSTAT_OV13_Msk            (0x01UL << SCU_POWER_EVRSTAT_OV13_Pos)                  /*!< SCU_POWER EVRSTAT: OV13 Mask            */\r
+\r
+/* ----------------------------  SCU_POWER_EVRVADCSTAT  --------------------------- */\r
+#define SCU_POWER_EVRVADCSTAT_VADC13V_Pos     0                                                       /*!< SCU_POWER EVRVADCSTAT: VADC13V Position */\r
+#define SCU_POWER_EVRVADCSTAT_VADC13V_Msk     (0x000000ffUL << SCU_POWER_EVRVADCSTAT_VADC13V_Pos)     /*!< SCU_POWER EVRVADCSTAT: VADC13V Mask     */\r
+#define SCU_POWER_EVRVADCSTAT_VADC33V_Pos     8                                                       /*!< SCU_POWER EVRVADCSTAT: VADC33V Position */\r
+#define SCU_POWER_EVRVADCSTAT_VADC33V_Msk     (0x000000ffUL << SCU_POWER_EVRVADCSTAT_VADC33V_Pos)     /*!< SCU_POWER EVRVADCSTAT: VADC33V Mask     */\r
+\r
+/* ------------------------------  SCU_POWER_PWRMON  ------------------------------ */\r
+#define SCU_POWER_PWRMON_THRS_Pos             0                                                       /*!< SCU_POWER PWRMON: THRS Position         */\r
+#define SCU_POWER_PWRMON_THRS_Msk             (0x000000ffUL << SCU_POWER_PWRMON_THRS_Pos)             /*!< SCU_POWER PWRMON: THRS Mask             */\r
+#define SCU_POWER_PWRMON_INTV_Pos             8                                                       /*!< SCU_POWER PWRMON: INTV Position         */\r
+#define SCU_POWER_PWRMON_INTV_Msk             (0x000000ffUL << SCU_POWER_PWRMON_INTV_Pos)             /*!< SCU_POWER PWRMON: INTV Mask             */\r
+#define SCU_POWER_PWRMON_ENB_Pos              16                                                      /*!< SCU_POWER PWRMON: ENB Position          */\r
+#define SCU_POWER_PWRMON_ENB_Msk              (0x01UL << SCU_POWER_PWRMON_ENB_Pos)                    /*!< SCU_POWER PWRMON: ENB Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       struct 'SCU_RESET' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_RESET_RSTSTAT  ----------------------------- */\r
+#define SCU_RESET_RSTSTAT_RSTSTAT_Pos         0                                                       /*!< SCU_RESET RSTSTAT: RSTSTAT Position     */\r
+#define SCU_RESET_RSTSTAT_RSTSTAT_Msk         (0x000000ffUL << SCU_RESET_RSTSTAT_RSTSTAT_Pos)         /*!< SCU_RESET RSTSTAT: RSTSTAT Mask         */\r
+#define SCU_RESET_RSTSTAT_HIBWK_Pos           8                                                       /*!< SCU_RESET RSTSTAT: HIBWK Position       */\r
+#define SCU_RESET_RSTSTAT_HIBWK_Msk           (0x01UL << SCU_RESET_RSTSTAT_HIBWK_Pos)                 /*!< SCU_RESET RSTSTAT: HIBWK Mask           */\r
+#define SCU_RESET_RSTSTAT_HIBRS_Pos           9                                                       /*!< SCU_RESET RSTSTAT: HIBRS Position       */\r
+#define SCU_RESET_RSTSTAT_HIBRS_Msk           (0x01UL << SCU_RESET_RSTSTAT_HIBRS_Pos)                 /*!< SCU_RESET RSTSTAT: HIBRS Mask           */\r
+#define SCU_RESET_RSTSTAT_LCKEN_Pos           10                                                      /*!< SCU_RESET RSTSTAT: LCKEN Position       */\r
+#define SCU_RESET_RSTSTAT_LCKEN_Msk           (0x01UL << SCU_RESET_RSTSTAT_LCKEN_Pos)                 /*!< SCU_RESET RSTSTAT: LCKEN Mask           */\r
+\r
+/* ------------------------------  SCU_RESET_RSTSET  ------------------------------ */\r
+#define SCU_RESET_RSTSET_HIBWK_Pos            8                                                       /*!< SCU_RESET RSTSET: HIBWK Position        */\r
+#define SCU_RESET_RSTSET_HIBWK_Msk            (0x01UL << SCU_RESET_RSTSET_HIBWK_Pos)                  /*!< SCU_RESET RSTSET: HIBWK Mask            */\r
+#define SCU_RESET_RSTSET_HIBRS_Pos            9                                                       /*!< SCU_RESET RSTSET: HIBRS Position        */\r
+#define SCU_RESET_RSTSET_HIBRS_Msk            (0x01UL << SCU_RESET_RSTSET_HIBRS_Pos)                  /*!< SCU_RESET RSTSET: HIBRS Mask            */\r
+#define SCU_RESET_RSTSET_LCKEN_Pos            10                                                      /*!< SCU_RESET RSTSET: LCKEN Position        */\r
+#define SCU_RESET_RSTSET_LCKEN_Msk            (0x01UL << SCU_RESET_RSTSET_LCKEN_Pos)                  /*!< SCU_RESET RSTSET: LCKEN Mask            */\r
+\r
+/* ------------------------------  SCU_RESET_RSTCLR  ------------------------------ */\r
+#define SCU_RESET_RSTCLR_RSCLR_Pos            0                                                       /*!< SCU_RESET RSTCLR: RSCLR Position        */\r
+#define SCU_RESET_RSTCLR_RSCLR_Msk            (0x01UL << SCU_RESET_RSTCLR_RSCLR_Pos)                  /*!< SCU_RESET RSTCLR: RSCLR Mask            */\r
+#define SCU_RESET_RSTCLR_HIBWK_Pos            8                                                       /*!< SCU_RESET RSTCLR: HIBWK Position        */\r
+#define SCU_RESET_RSTCLR_HIBWK_Msk            (0x01UL << SCU_RESET_RSTCLR_HIBWK_Pos)                  /*!< SCU_RESET RSTCLR: HIBWK Mask            */\r
+#define SCU_RESET_RSTCLR_HIBRS_Pos            9                                                       /*!< SCU_RESET RSTCLR: HIBRS Position        */\r
+#define SCU_RESET_RSTCLR_HIBRS_Msk            (0x01UL << SCU_RESET_RSTCLR_HIBRS_Pos)                  /*!< SCU_RESET RSTCLR: HIBRS Mask            */\r
+#define SCU_RESET_RSTCLR_LCKEN_Pos            10                                                      /*!< SCU_RESET RSTCLR: LCKEN Position        */\r
+#define SCU_RESET_RSTCLR_LCKEN_Msk            (0x01UL << SCU_RESET_RSTCLR_LCKEN_Pos)                  /*!< SCU_RESET RSTCLR: LCKEN Mask            */\r
+\r
+/* ------------------------------  SCU_RESET_PRSTAT0  ----------------------------- */\r
+#define SCU_RESET_PRSTAT0_VADCRS_Pos          0                                                       /*!< SCU_RESET PRSTAT0: VADCRS Position      */\r
+#define SCU_RESET_PRSTAT0_VADCRS_Msk          (0x01UL << SCU_RESET_PRSTAT0_VADCRS_Pos)                /*!< SCU_RESET PRSTAT0: VADCRS Mask          */\r
+#define SCU_RESET_PRSTAT0_CCU40RS_Pos         2                                                       /*!< SCU_RESET PRSTAT0: CCU40RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU40RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU40RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU40RS Mask         */\r
+#define SCU_RESET_PRSTAT0_CCU41RS_Pos         3                                                       /*!< SCU_RESET PRSTAT0: CCU41RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU41RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU41RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU41RS Mask         */\r
+#define SCU_RESET_PRSTAT0_CCU80RS_Pos         7                                                       /*!< SCU_RESET PRSTAT0: CCU80RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU80RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU80RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU80RS Mask         */\r
+#define SCU_RESET_PRSTAT0_POSIF0RS_Pos        9                                                       /*!< SCU_RESET PRSTAT0: POSIF0RS Position    */\r
+#define SCU_RESET_PRSTAT0_POSIF0RS_Msk        (0x01UL << SCU_RESET_PRSTAT0_POSIF0RS_Pos)              /*!< SCU_RESET PRSTAT0: POSIF0RS Mask        */\r
+#define SCU_RESET_PRSTAT0_USIC0RS_Pos         11                                                      /*!< SCU_RESET PRSTAT0: USIC0RS Position     */\r
+#define SCU_RESET_PRSTAT0_USIC0RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_USIC0RS_Pos)               /*!< SCU_RESET PRSTAT0: USIC0RS Mask         */\r
+#define SCU_RESET_PRSTAT0_ERU1RS_Pos          16                                                      /*!< SCU_RESET PRSTAT0: ERU1RS Position      */\r
+#define SCU_RESET_PRSTAT0_ERU1RS_Msk          (0x01UL << SCU_RESET_PRSTAT0_ERU1RS_Pos)                /*!< SCU_RESET PRSTAT0: ERU1RS Mask          */\r
+#define SCU_RESET_PRSTAT0_HRPWM0RS_Pos        23                                                      /*!< SCU_RESET PRSTAT0: HRPWM0RS Position    */\r
+#define SCU_RESET_PRSTAT0_HRPWM0RS_Msk        (0x01UL << SCU_RESET_PRSTAT0_HRPWM0RS_Pos)              /*!< SCU_RESET PRSTAT0: HRPWM0RS Mask        */\r
+\r
+/* ------------------------------  SCU_RESET_PRSET0  ------------------------------ */\r
+#define SCU_RESET_PRSET0_VADCRS_Pos           0                                                       /*!< SCU_RESET PRSET0: VADCRS Position       */\r
+#define SCU_RESET_PRSET0_VADCRS_Msk           (0x01UL << SCU_RESET_PRSET0_VADCRS_Pos)                 /*!< SCU_RESET PRSET0: VADCRS Mask           */\r
+#define SCU_RESET_PRSET0_CCU40RS_Pos          2                                                       /*!< SCU_RESET PRSET0: CCU40RS Position      */\r
+#define SCU_RESET_PRSET0_CCU40RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU40RS_Pos)                /*!< SCU_RESET PRSET0: CCU40RS Mask          */\r
+#define SCU_RESET_PRSET0_CCU41RS_Pos          3                                                       /*!< SCU_RESET PRSET0: CCU41RS Position      */\r
+#define SCU_RESET_PRSET0_CCU41RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU41RS_Pos)                /*!< SCU_RESET PRSET0: CCU41RS Mask          */\r
+#define SCU_RESET_PRSET0_CCU80RS_Pos          7                                                       /*!< SCU_RESET PRSET0: CCU80RS Position      */\r
+#define SCU_RESET_PRSET0_CCU80RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU80RS_Pos)                /*!< SCU_RESET PRSET0: CCU80RS Mask          */\r
+#define SCU_RESET_PRSET0_POSIF0RS_Pos         9                                                       /*!< SCU_RESET PRSET0: POSIF0RS Position     */\r
+#define SCU_RESET_PRSET0_POSIF0RS_Msk         (0x01UL << SCU_RESET_PRSET0_POSIF0RS_Pos)               /*!< SCU_RESET PRSET0: POSIF0RS Mask         */\r
+#define SCU_RESET_PRSET0_USIC0RS_Pos          11                                                      /*!< SCU_RESET PRSET0: USIC0RS Position      */\r
+#define SCU_RESET_PRSET0_USIC0RS_Msk          (0x01UL << SCU_RESET_PRSET0_USIC0RS_Pos)                /*!< SCU_RESET PRSET0: USIC0RS Mask          */\r
+#define SCU_RESET_PRSET0_ERU1RS_Pos           16                                                      /*!< SCU_RESET PRSET0: ERU1RS Position       */\r
+#define SCU_RESET_PRSET0_ERU1RS_Msk           (0x01UL << SCU_RESET_PRSET0_ERU1RS_Pos)                 /*!< SCU_RESET PRSET0: ERU1RS Mask           */\r
+#define SCU_RESET_PRSET0_HRPWM0RS_Pos         23                                                      /*!< SCU_RESET PRSET0: HRPWM0RS Position     */\r
+#define SCU_RESET_PRSET0_HRPWM0RS_Msk         (0x01UL << SCU_RESET_PRSET0_HRPWM0RS_Pos)               /*!< SCU_RESET PRSET0: HRPWM0RS Mask         */\r
+\r
+/* ------------------------------  SCU_RESET_PRCLR0  ------------------------------ */\r
+#define SCU_RESET_PRCLR0_VADCRS_Pos           0                                                       /*!< SCU_RESET PRCLR0: VADCRS Position       */\r
+#define SCU_RESET_PRCLR0_VADCRS_Msk           (0x01UL << SCU_RESET_PRCLR0_VADCRS_Pos)                 /*!< SCU_RESET PRCLR0: VADCRS Mask           */\r
+#define SCU_RESET_PRCLR0_CCU40RS_Pos          2                                                       /*!< SCU_RESET PRCLR0: CCU40RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU40RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU40RS_Pos)                /*!< SCU_RESET PRCLR0: CCU40RS Mask          */\r
+#define SCU_RESET_PRCLR0_CCU41RS_Pos          3                                                       /*!< SCU_RESET PRCLR0: CCU41RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU41RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU41RS_Pos)                /*!< SCU_RESET PRCLR0: CCU41RS Mask          */\r
+#define SCU_RESET_PRCLR0_CCU80RS_Pos          7                                                       /*!< SCU_RESET PRCLR0: CCU80RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU80RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU80RS_Pos)                /*!< SCU_RESET PRCLR0: CCU80RS Mask          */\r
+#define SCU_RESET_PRCLR0_POSIF0RS_Pos         9                                                       /*!< SCU_RESET PRCLR0: POSIF0RS Position     */\r
+#define SCU_RESET_PRCLR0_POSIF0RS_Msk         (0x01UL << SCU_RESET_PRCLR0_POSIF0RS_Pos)               /*!< SCU_RESET PRCLR0: POSIF0RS Mask         */\r
+#define SCU_RESET_PRCLR0_USIC0RS_Pos          11                                                      /*!< SCU_RESET PRCLR0: USIC0RS Position      */\r
+#define SCU_RESET_PRCLR0_USIC0RS_Msk          (0x01UL << SCU_RESET_PRCLR0_USIC0RS_Pos)                /*!< SCU_RESET PRCLR0: USIC0RS Mask          */\r
+#define SCU_RESET_PRCLR0_ERU1RS_Pos           16                                                      /*!< SCU_RESET PRCLR0: ERU1RS Position       */\r
+#define SCU_RESET_PRCLR0_ERU1RS_Msk           (0x01UL << SCU_RESET_PRCLR0_ERU1RS_Pos)                 /*!< SCU_RESET PRCLR0: ERU1RS Mask           */\r
+#define SCU_RESET_PRCLR0_HRPWM0RS_Pos         23                                                      /*!< SCU_RESET PRCLR0: HRPWM0RS Position     */\r
+#define SCU_RESET_PRCLR0_HRPWM0RS_Msk         (0x01UL << SCU_RESET_PRCLR0_HRPWM0RS_Pos)               /*!< SCU_RESET PRCLR0: HRPWM0RS Mask         */\r
+\r
+/* ------------------------------  SCU_RESET_PRSTAT1  ----------------------------- */\r
+#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos      3                                                       /*!< SCU_RESET PRSTAT1: LEDTSCU0RS Position  */\r
+#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk      (0x01UL << SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos)            /*!< SCU_RESET PRSTAT1: LEDTSCU0RS Mask      */\r
+#define SCU_RESET_PRSTAT1_MCAN0RS_Pos         4                                                       /*!< SCU_RESET PRSTAT1: MCAN0RS Position     */\r
+#define SCU_RESET_PRSTAT1_MCAN0RS_Msk         (0x01UL << SCU_RESET_PRSTAT1_MCAN0RS_Pos)               /*!< SCU_RESET PRSTAT1: MCAN0RS Mask         */\r
+#define SCU_RESET_PRSTAT1_DACRS_Pos           5                                                       /*!< SCU_RESET PRSTAT1: DACRS Position       */\r
+#define SCU_RESET_PRSTAT1_DACRS_Msk           (0x01UL << SCU_RESET_PRSTAT1_DACRS_Pos)                 /*!< SCU_RESET PRSTAT1: DACRS Mask           */\r
+#define SCU_RESET_PRSTAT1_USIC1RS_Pos         7                                                       /*!< SCU_RESET PRSTAT1: USIC1RS Position     */\r
+#define SCU_RESET_PRSTAT1_USIC1RS_Msk         (0x01UL << SCU_RESET_PRSTAT1_USIC1RS_Pos)               /*!< SCU_RESET PRSTAT1: USIC1RS Mask         */\r
+#define SCU_RESET_PRSTAT1_PPORTSRS_Pos        9                                                       /*!< SCU_RESET PRSTAT1: PPORTSRS Position    */\r
+#define SCU_RESET_PRSTAT1_PPORTSRS_Msk        (0x01UL << SCU_RESET_PRSTAT1_PPORTSRS_Pos)              /*!< SCU_RESET PRSTAT1: PPORTSRS Mask        */\r
+\r
+/* ------------------------------  SCU_RESET_PRSET1  ------------------------------ */\r
+#define SCU_RESET_PRSET1_LEDTSCU0RS_Pos       3                                                       /*!< SCU_RESET PRSET1: LEDTSCU0RS Position   */\r
+#define SCU_RESET_PRSET1_LEDTSCU0RS_Msk       (0x01UL << SCU_RESET_PRSET1_LEDTSCU0RS_Pos)             /*!< SCU_RESET PRSET1: LEDTSCU0RS Mask       */\r
+#define SCU_RESET_PRSET1_MCAN0RS_Pos          4                                                       /*!< SCU_RESET PRSET1: MCAN0RS Position      */\r
+#define SCU_RESET_PRSET1_MCAN0RS_Msk          (0x01UL << SCU_RESET_PRSET1_MCAN0RS_Pos)                /*!< SCU_RESET PRSET1: MCAN0RS Mask          */\r
+#define SCU_RESET_PRSET1_DACRS_Pos            5                                                       /*!< SCU_RESET PRSET1: DACRS Position        */\r
+#define SCU_RESET_PRSET1_DACRS_Msk            (0x01UL << SCU_RESET_PRSET1_DACRS_Pos)                  /*!< SCU_RESET PRSET1: DACRS Mask            */\r
+#define SCU_RESET_PRSET1_USIC1RS_Pos          7                                                       /*!< SCU_RESET PRSET1: USIC1RS Position      */\r
+#define SCU_RESET_PRSET1_USIC1RS_Msk          (0x01UL << SCU_RESET_PRSET1_USIC1RS_Pos)                /*!< SCU_RESET PRSET1: USIC1RS Mask          */\r
+#define SCU_RESET_PRSET1_PPORTSRS_Pos         9                                                       /*!< SCU_RESET PRSET1: PPORTSRS Position     */\r
+#define SCU_RESET_PRSET1_PPORTSRS_Msk         (0x01UL << SCU_RESET_PRSET1_PPORTSRS_Pos)               /*!< SCU_RESET PRSET1: PPORTSRS Mask         */\r
+\r
+/* ------------------------------  SCU_RESET_PRCLR1  ------------------------------ */\r
+#define SCU_RESET_PRCLR1_LEDTSCU0RS_Pos       3                                                       /*!< SCU_RESET PRCLR1: LEDTSCU0RS Position   */\r
+#define SCU_RESET_PRCLR1_LEDTSCU0RS_Msk       (0x01UL << SCU_RESET_PRCLR1_LEDTSCU0RS_Pos)             /*!< SCU_RESET PRCLR1: LEDTSCU0RS Mask       */\r
+#define SCU_RESET_PRCLR1_MCAN0RS_Pos          4                                                       /*!< SCU_RESET PRCLR1: MCAN0RS Position      */\r
+#define SCU_RESET_PRCLR1_MCAN0RS_Msk          (0x01UL << SCU_RESET_PRCLR1_MCAN0RS_Pos)                /*!< SCU_RESET PRCLR1: MCAN0RS Mask          */\r
+#define SCU_RESET_PRCLR1_DACRS_Pos            5                                                       /*!< SCU_RESET PRCLR1: DACRS Position        */\r
+#define SCU_RESET_PRCLR1_DACRS_Msk            (0x01UL << SCU_RESET_PRCLR1_DACRS_Pos)                  /*!< SCU_RESET PRCLR1: DACRS Mask            */\r
+#define SCU_RESET_PRCLR1_USIC1RS_Pos          7                                                       /*!< SCU_RESET PRCLR1: USIC1RS Position      */\r
+#define SCU_RESET_PRCLR1_USIC1RS_Msk          (0x01UL << SCU_RESET_PRCLR1_USIC1RS_Pos)                /*!< SCU_RESET PRCLR1: USIC1RS Mask          */\r
+#define SCU_RESET_PRCLR1_PPORTSRS_Pos         9                                                       /*!< SCU_RESET PRCLR1: PPORTSRS Position     */\r
+#define SCU_RESET_PRCLR1_PPORTSRS_Msk         (0x01UL << SCU_RESET_PRCLR1_PPORTSRS_Pos)               /*!< SCU_RESET PRCLR1: PPORTSRS Mask         */\r
+\r
+/* ------------------------------  SCU_RESET_PRSTAT2  ----------------------------- */\r
+#define SCU_RESET_PRSTAT2_WDTRS_Pos           1                                                       /*!< SCU_RESET PRSTAT2: WDTRS Position       */\r
+#define SCU_RESET_PRSTAT2_WDTRS_Msk           (0x01UL << SCU_RESET_PRSTAT2_WDTRS_Pos)                 /*!< SCU_RESET PRSTAT2: WDTRS Mask           */\r
+#define SCU_RESET_PRSTAT2_DMA0RS_Pos          4                                                       /*!< SCU_RESET PRSTAT2: DMA0RS Position      */\r
+#define SCU_RESET_PRSTAT2_DMA0RS_Msk          (0x01UL << SCU_RESET_PRSTAT2_DMA0RS_Pos)                /*!< SCU_RESET PRSTAT2: DMA0RS Mask          */\r
+#define SCU_RESET_PRSTAT2_FCERS_Pos           6                                                       /*!< SCU_RESET PRSTAT2: FCERS Position       */\r
+#define SCU_RESET_PRSTAT2_FCERS_Msk           (0x01UL << SCU_RESET_PRSTAT2_FCERS_Pos)                 /*!< SCU_RESET PRSTAT2: FCERS Mask           */\r
+#define SCU_RESET_PRSTAT2_USBRS_Pos           7                                                       /*!< SCU_RESET PRSTAT2: USBRS Position       */\r
+#define SCU_RESET_PRSTAT2_USBRS_Msk           (0x01UL << SCU_RESET_PRSTAT2_USBRS_Pos)                 /*!< SCU_RESET PRSTAT2: USBRS Mask           */\r
+\r
+/* ------------------------------  SCU_RESET_PRSET2  ------------------------------ */\r
+#define SCU_RESET_PRSET2_WDTRS_Pos            1                                                       /*!< SCU_RESET PRSET2: WDTRS Position        */\r
+#define SCU_RESET_PRSET2_WDTRS_Msk            (0x01UL << SCU_RESET_PRSET2_WDTRS_Pos)                  /*!< SCU_RESET PRSET2: WDTRS Mask            */\r
+#define SCU_RESET_PRSET2_DMA0RS_Pos           4                                                       /*!< SCU_RESET PRSET2: DMA0RS Position       */\r
+#define SCU_RESET_PRSET2_DMA0RS_Msk           (0x01UL << SCU_RESET_PRSET2_DMA0RS_Pos)                 /*!< SCU_RESET PRSET2: DMA0RS Mask           */\r
+#define SCU_RESET_PRSET2_FCERS_Pos            6                                                       /*!< SCU_RESET PRSET2: FCERS Position        */\r
+#define SCU_RESET_PRSET2_FCERS_Msk            (0x01UL << SCU_RESET_PRSET2_FCERS_Pos)                  /*!< SCU_RESET PRSET2: FCERS Mask            */\r
+#define SCU_RESET_PRSET2_USBRS_Pos            7                                                       /*!< SCU_RESET PRSET2: USBRS Position        */\r
+#define SCU_RESET_PRSET2_USBRS_Msk            (0x01UL << SCU_RESET_PRSET2_USBRS_Pos)                  /*!< SCU_RESET PRSET2: USBRS Mask            */\r
+\r
+/* ------------------------------  SCU_RESET_PRCLR2  ------------------------------ */\r
+#define SCU_RESET_PRCLR2_WDTRS_Pos            1                                                       /*!< SCU_RESET PRCLR2: WDTRS Position        */\r
+#define SCU_RESET_PRCLR2_WDTRS_Msk            (0x01UL << SCU_RESET_PRCLR2_WDTRS_Pos)                  /*!< SCU_RESET PRCLR2: WDTRS Mask            */\r
+#define SCU_RESET_PRCLR2_DMA0RS_Pos           4                                                       /*!< SCU_RESET PRCLR2: DMA0RS Position       */\r
+#define SCU_RESET_PRCLR2_DMA0RS_Msk           (0x01UL << SCU_RESET_PRCLR2_DMA0RS_Pos)                 /*!< SCU_RESET PRCLR2: DMA0RS Mask           */\r
+#define SCU_RESET_PRCLR2_FCERS_Pos            6                                                       /*!< SCU_RESET PRCLR2: FCERS Position        */\r
+#define SCU_RESET_PRCLR2_FCERS_Msk            (0x01UL << SCU_RESET_PRCLR2_FCERS_Pos)                  /*!< SCU_RESET PRCLR2: FCERS Mask            */\r
+#define SCU_RESET_PRCLR2_USBRS_Pos            7                                                       /*!< SCU_RESET PRCLR2: USBRS Position        */\r
+#define SCU_RESET_PRCLR2_USBRS_Msk            (0x01UL << SCU_RESET_PRCLR2_USBRS_Pos)                  /*!< SCU_RESET PRCLR2: USBRS Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'LEDTS' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  LEDTS_ID  ---------------------------------- */\r
+#define LEDTS_ID_MOD_REV_Pos                  0                                                       /*!< LEDTS ID: MOD_REV Position              */\r
+#define LEDTS_ID_MOD_REV_Msk                  (0x000000ffUL << LEDTS_ID_MOD_REV_Pos)                  /*!< LEDTS ID: MOD_REV Mask                  */\r
+#define LEDTS_ID_MOD_TYPE_Pos                 8                                                       /*!< LEDTS ID: MOD_TYPE Position             */\r
+#define LEDTS_ID_MOD_TYPE_Msk                 (0x000000ffUL << LEDTS_ID_MOD_TYPE_Pos)                 /*!< LEDTS ID: MOD_TYPE Mask                 */\r
+#define LEDTS_ID_MOD_NUMBER_Pos               16                                                      /*!< LEDTS ID: MOD_NUMBER Position           */\r
+#define LEDTS_ID_MOD_NUMBER_Msk               (0x0000ffffUL << LEDTS_ID_MOD_NUMBER_Pos)               /*!< LEDTS ID: MOD_NUMBER Mask               */\r
+\r
+/* --------------------------------  LEDTS_GLOBCTL  ------------------------------- */\r
+#define LEDTS_GLOBCTL_TS_EN_Pos               0                                                       /*!< LEDTS GLOBCTL: TS_EN Position           */\r
+#define LEDTS_GLOBCTL_TS_EN_Msk               (0x01UL << LEDTS_GLOBCTL_TS_EN_Pos)                     /*!< LEDTS GLOBCTL: TS_EN Mask               */\r
+#define LEDTS_GLOBCTL_LD_EN_Pos               1                                                       /*!< LEDTS GLOBCTL: LD_EN Position           */\r
+#define LEDTS_GLOBCTL_LD_EN_Msk               (0x01UL << LEDTS_GLOBCTL_LD_EN_Pos)                     /*!< LEDTS GLOBCTL: LD_EN Mask               */\r
+#define LEDTS_GLOBCTL_CMTR_Pos                2                                                       /*!< LEDTS GLOBCTL: CMTR Position            */\r
+#define LEDTS_GLOBCTL_CMTR_Msk                (0x01UL << LEDTS_GLOBCTL_CMTR_Pos)                      /*!< LEDTS GLOBCTL: CMTR Mask                */\r
+#define LEDTS_GLOBCTL_ENSYNC_Pos              3                                                       /*!< LEDTS GLOBCTL: ENSYNC Position          */\r
+#define LEDTS_GLOBCTL_ENSYNC_Msk              (0x01UL << LEDTS_GLOBCTL_ENSYNC_Pos)                    /*!< LEDTS GLOBCTL: ENSYNC Mask              */\r
+#define LEDTS_GLOBCTL_SUSCFG_Pos              8                                                       /*!< LEDTS GLOBCTL: SUSCFG Position          */\r
+#define LEDTS_GLOBCTL_SUSCFG_Msk              (0x01UL << LEDTS_GLOBCTL_SUSCFG_Pos)                    /*!< LEDTS GLOBCTL: SUSCFG Mask              */\r
+#define LEDTS_GLOBCTL_MASKVAL_Pos             9                                                       /*!< LEDTS GLOBCTL: MASKVAL Position         */\r
+#define LEDTS_GLOBCTL_MASKVAL_Msk             (0x07UL << LEDTS_GLOBCTL_MASKVAL_Pos)                   /*!< LEDTS GLOBCTL: MASKVAL Mask             */\r
+#define LEDTS_GLOBCTL_FENVAL_Pos              12                                                      /*!< LEDTS GLOBCTL: FENVAL Position          */\r
+#define LEDTS_GLOBCTL_FENVAL_Msk              (0x01UL << LEDTS_GLOBCTL_FENVAL_Pos)                    /*!< LEDTS GLOBCTL: FENVAL Mask              */\r
+#define LEDTS_GLOBCTL_ITS_EN_Pos              13                                                      /*!< LEDTS GLOBCTL: ITS_EN Position          */\r
+#define LEDTS_GLOBCTL_ITS_EN_Msk              (0x01UL << LEDTS_GLOBCTL_ITS_EN_Pos)                    /*!< LEDTS GLOBCTL: ITS_EN Mask              */\r
+#define LEDTS_GLOBCTL_ITF_EN_Pos              14                                                      /*!< LEDTS GLOBCTL: ITF_EN Position          */\r
+#define LEDTS_GLOBCTL_ITF_EN_Msk              (0x01UL << LEDTS_GLOBCTL_ITF_EN_Pos)                    /*!< LEDTS GLOBCTL: ITF_EN Mask              */\r
+#define LEDTS_GLOBCTL_ITP_EN_Pos              15                                                      /*!< LEDTS GLOBCTL: ITP_EN Position          */\r
+#define LEDTS_GLOBCTL_ITP_EN_Msk              (0x01UL << LEDTS_GLOBCTL_ITP_EN_Pos)                    /*!< LEDTS GLOBCTL: ITP_EN Mask              */\r
+#define LEDTS_GLOBCTL_CLK_PS_Pos              16                                                      /*!< LEDTS GLOBCTL: CLK_PS Position          */\r
+#define LEDTS_GLOBCTL_CLK_PS_Msk              (0x0000ffffUL << LEDTS_GLOBCTL_CLK_PS_Pos)              /*!< LEDTS GLOBCTL: CLK_PS Mask              */\r
+\r
+/* ---------------------------------  LEDTS_FNCTL  -------------------------------- */\r
+#define LEDTS_FNCTL_PADT_Pos                  0                                                       /*!< LEDTS FNCTL: PADT Position              */\r
+#define LEDTS_FNCTL_PADT_Msk                  (0x07UL << LEDTS_FNCTL_PADT_Pos)                        /*!< LEDTS FNCTL: PADT Mask                  */\r
+#define LEDTS_FNCTL_PADTSW_Pos                3                                                       /*!< LEDTS FNCTL: PADTSW Position            */\r
+#define LEDTS_FNCTL_PADTSW_Msk                (0x01UL << LEDTS_FNCTL_PADTSW_Pos)                      /*!< LEDTS FNCTL: PADTSW Mask                */\r
+#define LEDTS_FNCTL_EPULL_Pos                 4                                                       /*!< LEDTS FNCTL: EPULL Position             */\r
+#define LEDTS_FNCTL_EPULL_Msk                 (0x01UL << LEDTS_FNCTL_EPULL_Pos)                       /*!< LEDTS FNCTL: EPULL Mask                 */\r
+#define LEDTS_FNCTL_FNCOL_Pos                 5                                                       /*!< LEDTS FNCTL: FNCOL Position             */\r
+#define LEDTS_FNCTL_FNCOL_Msk                 (0x07UL << LEDTS_FNCTL_FNCOL_Pos)                       /*!< LEDTS FNCTL: FNCOL Mask                 */\r
+#define LEDTS_FNCTL_ACCCNT_Pos                16                                                      /*!< LEDTS FNCTL: ACCCNT Position            */\r
+#define LEDTS_FNCTL_ACCCNT_Msk                (0x0fUL << LEDTS_FNCTL_ACCCNT_Pos)                      /*!< LEDTS FNCTL: ACCCNT Mask                */\r
+#define LEDTS_FNCTL_TSCCMP_Pos                20                                                      /*!< LEDTS FNCTL: TSCCMP Position            */\r
+#define LEDTS_FNCTL_TSCCMP_Msk                (0x01UL << LEDTS_FNCTL_TSCCMP_Pos)                      /*!< LEDTS FNCTL: TSCCMP Mask                */\r
+#define LEDTS_FNCTL_TSOEXT_Pos                21                                                      /*!< LEDTS FNCTL: TSOEXT Position            */\r
+#define LEDTS_FNCTL_TSOEXT_Msk                (0x03UL << LEDTS_FNCTL_TSOEXT_Pos)                      /*!< LEDTS FNCTL: TSOEXT Mask                */\r
+#define LEDTS_FNCTL_TSCTRR_Pos                23                                                      /*!< LEDTS FNCTL: TSCTRR Position            */\r
+#define LEDTS_FNCTL_TSCTRR_Msk                (0x01UL << LEDTS_FNCTL_TSCTRR_Pos)                      /*!< LEDTS FNCTL: TSCTRR Mask                */\r
+#define LEDTS_FNCTL_TSCTRSAT_Pos              24                                                      /*!< LEDTS FNCTL: TSCTRSAT Position          */\r
+#define LEDTS_FNCTL_TSCTRSAT_Msk              (0x01UL << LEDTS_FNCTL_TSCTRSAT_Pos)                    /*!< LEDTS FNCTL: TSCTRSAT Mask              */\r
+#define LEDTS_FNCTL_NR_TSIN_Pos               25                                                      /*!< LEDTS FNCTL: NR_TSIN Position           */\r
+#define LEDTS_FNCTL_NR_TSIN_Msk               (0x07UL << LEDTS_FNCTL_NR_TSIN_Pos)                     /*!< LEDTS FNCTL: NR_TSIN Mask               */\r
+#define LEDTS_FNCTL_COLLEV_Pos                28                                                      /*!< LEDTS FNCTL: COLLEV Position            */\r
+#define LEDTS_FNCTL_COLLEV_Msk                (0x01UL << LEDTS_FNCTL_COLLEV_Pos)                      /*!< LEDTS FNCTL: COLLEV Mask                */\r
+#define LEDTS_FNCTL_NR_LEDCOL_Pos             29                                                      /*!< LEDTS FNCTL: NR_LEDCOL Position         */\r
+#define LEDTS_FNCTL_NR_LEDCOL_Msk             (0x07UL << LEDTS_FNCTL_NR_LEDCOL_Pos)                   /*!< LEDTS FNCTL: NR_LEDCOL Mask             */\r
+\r
+/* ---------------------------------  LEDTS_EVFR  --------------------------------- */\r
+#define LEDTS_EVFR_TSF_Pos                    0                                                       /*!< LEDTS EVFR: TSF Position                */\r
+#define LEDTS_EVFR_TSF_Msk                    (0x01UL << LEDTS_EVFR_TSF_Pos)                          /*!< LEDTS EVFR: TSF Mask                    */\r
+#define LEDTS_EVFR_TFF_Pos                    1                                                       /*!< LEDTS EVFR: TFF Position                */\r
+#define LEDTS_EVFR_TFF_Msk                    (0x01UL << LEDTS_EVFR_TFF_Pos)                          /*!< LEDTS EVFR: TFF Mask                    */\r
+#define LEDTS_EVFR_TPF_Pos                    2                                                       /*!< LEDTS EVFR: TPF Position                */\r
+#define LEDTS_EVFR_TPF_Msk                    (0x01UL << LEDTS_EVFR_TPF_Pos)                          /*!< LEDTS EVFR: TPF Mask                    */\r
+#define LEDTS_EVFR_TSCTROVF_Pos               3                                                       /*!< LEDTS EVFR: TSCTROVF Position           */\r
+#define LEDTS_EVFR_TSCTROVF_Msk               (0x01UL << LEDTS_EVFR_TSCTROVF_Pos)                     /*!< LEDTS EVFR: TSCTROVF Mask               */\r
+#define LEDTS_EVFR_CTSF_Pos                   16                                                      /*!< LEDTS EVFR: CTSF Position               */\r
+#define LEDTS_EVFR_CTSF_Msk                   (0x01UL << LEDTS_EVFR_CTSF_Pos)                         /*!< LEDTS EVFR: CTSF Mask                   */\r
+#define LEDTS_EVFR_CTFF_Pos                   17                                                      /*!< LEDTS EVFR: CTFF Position               */\r
+#define LEDTS_EVFR_CTFF_Msk                   (0x01UL << LEDTS_EVFR_CTFF_Pos)                         /*!< LEDTS EVFR: CTFF Mask                   */\r
+#define LEDTS_EVFR_CTPF_Pos                   18                                                      /*!< LEDTS EVFR: CTPF Position               */\r
+#define LEDTS_EVFR_CTPF_Msk                   (0x01UL << LEDTS_EVFR_CTPF_Pos)                         /*!< LEDTS EVFR: CTPF Mask                   */\r
+\r
+/* ---------------------------------  LEDTS_TSVAL  -------------------------------- */\r
+#define LEDTS_TSVAL_TSCTRVALR_Pos             0                                                       /*!< LEDTS TSVAL: TSCTRVALR Position         */\r
+#define LEDTS_TSVAL_TSCTRVALR_Msk             (0x0000ffffUL << LEDTS_TSVAL_TSCTRVALR_Pos)             /*!< LEDTS TSVAL: TSCTRVALR Mask             */\r
+#define LEDTS_TSVAL_TSCTRVAL_Pos              16                                                      /*!< LEDTS TSVAL: TSCTRVAL Position          */\r
+#define LEDTS_TSVAL_TSCTRVAL_Msk              (0x0000ffffUL << LEDTS_TSVAL_TSCTRVAL_Pos)              /*!< LEDTS TSVAL: TSCTRVAL Mask              */\r
+\r
+/* ---------------------------------  LEDTS_LINE0  -------------------------------- */\r
+#define LEDTS_LINE0_LINE_0_Pos                0                                                       /*!< LEDTS LINE0: LINE_0 Position            */\r
+#define LEDTS_LINE0_LINE_0_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_0_Pos)                /*!< LEDTS LINE0: LINE_0 Mask                */\r
+#define LEDTS_LINE0_LINE_1_Pos                8                                                       /*!< LEDTS LINE0: LINE_1 Position            */\r
+#define LEDTS_LINE0_LINE_1_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_1_Pos)                /*!< LEDTS LINE0: LINE_1 Mask                */\r
+#define LEDTS_LINE0_LINE_2_Pos                16                                                      /*!< LEDTS LINE0: LINE_2 Position            */\r
+#define LEDTS_LINE0_LINE_2_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_2_Pos)                /*!< LEDTS LINE0: LINE_2 Mask                */\r
+#define LEDTS_LINE0_LINE_3_Pos                24                                                      /*!< LEDTS LINE0: LINE_3 Position            */\r
+#define LEDTS_LINE0_LINE_3_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_3_Pos)                /*!< LEDTS LINE0: LINE_3 Mask                */\r
+\r
+/* ---------------------------------  LEDTS_LINE1  -------------------------------- */\r
+#define LEDTS_LINE1_LINE_4_Pos                0                                                       /*!< LEDTS LINE1: LINE_4 Position            */\r
+#define LEDTS_LINE1_LINE_4_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_4_Pos)                /*!< LEDTS LINE1: LINE_4 Mask                */\r
+#define LEDTS_LINE1_LINE_5_Pos                8                                                       /*!< LEDTS LINE1: LINE_5 Position            */\r
+#define LEDTS_LINE1_LINE_5_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_5_Pos)                /*!< LEDTS LINE1: LINE_5 Mask                */\r
+#define LEDTS_LINE1_LINE_6_Pos                16                                                      /*!< LEDTS LINE1: LINE_6 Position            */\r
+#define LEDTS_LINE1_LINE_6_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_6_Pos)                /*!< LEDTS LINE1: LINE_6 Mask                */\r
+#define LEDTS_LINE1_LINE_A_Pos                24                                                      /*!< LEDTS LINE1: LINE_A Position            */\r
+#define LEDTS_LINE1_LINE_A_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_A_Pos)                /*!< LEDTS LINE1: LINE_A Mask                */\r
+\r
+/* --------------------------------  LEDTS_LDCMP0  -------------------------------- */\r
+#define LEDTS_LDCMP0_CMP_LD0_Pos              0                                                       /*!< LEDTS LDCMP0: CMP_LD0 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD0_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD0_Pos)              /*!< LEDTS LDCMP0: CMP_LD0 Mask              */\r
+#define LEDTS_LDCMP0_CMP_LD1_Pos              8                                                       /*!< LEDTS LDCMP0: CMP_LD1 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD1_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD1_Pos)              /*!< LEDTS LDCMP0: CMP_LD1 Mask              */\r
+#define LEDTS_LDCMP0_CMP_LD2_Pos              16                                                      /*!< LEDTS LDCMP0: CMP_LD2 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD2_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD2_Pos)              /*!< LEDTS LDCMP0: CMP_LD2 Mask              */\r
+#define LEDTS_LDCMP0_CMP_LD3_Pos              24                                                      /*!< LEDTS LDCMP0: CMP_LD3 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD3_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD3_Pos)              /*!< LEDTS LDCMP0: CMP_LD3 Mask              */\r
+\r
+/* --------------------------------  LEDTS_LDCMP1  -------------------------------- */\r
+#define LEDTS_LDCMP1_CMP_LD4_Pos              0                                                       /*!< LEDTS LDCMP1: CMP_LD4 Position          */\r
+#define LEDTS_LDCMP1_CMP_LD4_Msk              (0x000000ffUL << LEDTS_LDCMP1_CMP_LD4_Pos)              /*!< LEDTS LDCMP1: CMP_LD4 Mask              */\r
+#define LEDTS_LDCMP1_CMP_LD5_Pos              8                                                       /*!< LEDTS LDCMP1: CMP_LD5 Position          */\r
+#define LEDTS_LDCMP1_CMP_LD5_Msk              (0x000000ffUL << LEDTS_LDCMP1_CMP_LD5_Pos)              /*!< LEDTS LDCMP1: CMP_LD5 Mask              */\r
+#define LEDTS_LDCMP1_CMP_LD6_Pos              16                                                      /*!< LEDTS LDCMP1: CMP_LD6 Position          */\r
+#define LEDTS_LDCMP1_CMP_LD6_Msk              (0x000000ffUL << LEDTS_LDCMP1_CMP_LD6_Pos)              /*!< LEDTS LDCMP1: CMP_LD6 Mask              */\r
+#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos        24                                                      /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Position    */\r
+#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk        (0x000000ffUL << LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos)        /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Mask        */\r
+\r
+/* --------------------------------  LEDTS_TSCMP0  -------------------------------- */\r
+#define LEDTS_TSCMP0_CMP_TS0_Pos              0                                                       /*!< LEDTS TSCMP0: CMP_TS0 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS0_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS0_Pos)              /*!< LEDTS TSCMP0: CMP_TS0 Mask              */\r
+#define LEDTS_TSCMP0_CMP_TS1_Pos              8                                                       /*!< LEDTS TSCMP0: CMP_TS1 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS1_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS1_Pos)              /*!< LEDTS TSCMP0: CMP_TS1 Mask              */\r
+#define LEDTS_TSCMP0_CMP_TS2_Pos              16                                                      /*!< LEDTS TSCMP0: CMP_TS2 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS2_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS2_Pos)              /*!< LEDTS TSCMP0: CMP_TS2 Mask              */\r
+#define LEDTS_TSCMP0_CMP_TS3_Pos              24                                                      /*!< LEDTS TSCMP0: CMP_TS3 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS3_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS3_Pos)              /*!< LEDTS TSCMP0: CMP_TS3 Mask              */\r
+\r
+/* --------------------------------  LEDTS_TSCMP1  -------------------------------- */\r
+#define LEDTS_TSCMP1_CMP_TS4_Pos              0                                                       /*!< LEDTS TSCMP1: CMP_TS4 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS4_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS4_Pos)              /*!< LEDTS TSCMP1: CMP_TS4 Mask              */\r
+#define LEDTS_TSCMP1_CMP_TS5_Pos              8                                                       /*!< LEDTS TSCMP1: CMP_TS5 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS5_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS5_Pos)              /*!< LEDTS TSCMP1: CMP_TS5 Mask              */\r
+#define LEDTS_TSCMP1_CMP_TS6_Pos              16                                                      /*!< LEDTS TSCMP1: CMP_TS6 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS6_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS6_Pos)              /*!< LEDTS TSCMP1: CMP_TS6 Mask              */\r
+#define LEDTS_TSCMP1_CMP_TS7_Pos              24                                                      /*!< LEDTS TSCMP1: CMP_TS7 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS7_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS7_Pos)              /*!< LEDTS TSCMP1: CMP_TS7 Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'USB' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  USB_GAHBCFG  -------------------------------- */\r
+#define USB_GAHBCFG_GlblIntrMsk_Pos           0                                                       /*!< USB GAHBCFG: GlblIntrMsk Position       */\r
+#define USB_GAHBCFG_GlblIntrMsk_Msk           (0x01UL << USB_GAHBCFG_GlblIntrMsk_Pos)                 /*!< USB GAHBCFG: GlblIntrMsk Mask           */\r
+#define USB_GAHBCFG_HBstLen_Pos               1                                                       /*!< USB GAHBCFG: HBstLen Position           */\r
+#define USB_GAHBCFG_HBstLen_Msk               (0x0fUL << USB_GAHBCFG_HBstLen_Pos)                     /*!< USB GAHBCFG: HBstLen Mask               */\r
+#define USB_GAHBCFG_DMAEn_Pos                 5                                                       /*!< USB GAHBCFG: DMAEn Position             */\r
+#define USB_GAHBCFG_DMAEn_Msk                 (0x01UL << USB_GAHBCFG_DMAEn_Pos)                       /*!< USB GAHBCFG: DMAEn Mask                 */\r
+#define USB_GAHBCFG_NPTxFEmpLvl_Pos           7                                                       /*!< USB GAHBCFG: NPTxFEmpLvl Position       */\r
+#define USB_GAHBCFG_NPTxFEmpLvl_Msk           (0x01UL << USB_GAHBCFG_NPTxFEmpLvl_Pos)                 /*!< USB GAHBCFG: NPTxFEmpLvl Mask           */\r
+#define USB_GAHBCFG_AHBSingle_Pos             23                                                      /*!< USB GAHBCFG: AHBSingle Position         */\r
+#define USB_GAHBCFG_AHBSingle_Msk             (0x01UL << USB_GAHBCFG_AHBSingle_Pos)                   /*!< USB GAHBCFG: AHBSingle Mask             */\r
+\r
+/* ---------------------------------  USB_GUSBCFG  -------------------------------- */\r
+#define USB_GUSBCFG_TOutCal_Pos               0                                                       /*!< USB GUSBCFG: TOutCal Position           */\r
+#define USB_GUSBCFG_TOutCal_Msk               (0x07UL << USB_GUSBCFG_TOutCal_Pos)                     /*!< USB GUSBCFG: TOutCal Mask               */\r
+#define USB_GUSBCFG_PHYSel_Pos                6                                                       /*!< USB GUSBCFG: PHYSel Position            */\r
+#define USB_GUSBCFG_PHYSel_Msk                (0x01UL << USB_GUSBCFG_PHYSel_Pos)                      /*!< USB GUSBCFG: PHYSel Mask                */\r
+#define USB_GUSBCFG_USBTrdTim_Pos             10                                                      /*!< USB GUSBCFG: USBTrdTim Position         */\r
+#define USB_GUSBCFG_USBTrdTim_Msk             (0x0fUL << USB_GUSBCFG_USBTrdTim_Pos)                   /*!< USB GUSBCFG: USBTrdTim Mask             */\r
+#define USB_GUSBCFG_TxEndDelay_Pos            28                                                      /*!< USB GUSBCFG: TxEndDelay Position        */\r
+#define USB_GUSBCFG_TxEndDelay_Msk            (0x01UL << USB_GUSBCFG_TxEndDelay_Pos)                  /*!< USB GUSBCFG: TxEndDelay Mask            */\r
+#define USB_GUSBCFG_ForceDevMode_Pos          30                                                      /*!< USB GUSBCFG: ForceDevMode Position      */\r
+#define USB_GUSBCFG_ForceDevMode_Msk          (0x01UL << USB_GUSBCFG_ForceDevMode_Pos)                /*!< USB GUSBCFG: ForceDevMode Mask          */\r
+#define USB_GUSBCFG_CTP_Pos                   31                                                      /*!< USB GUSBCFG: CTP Position               */\r
+#define USB_GUSBCFG_CTP_Msk                   (0x01UL << USB_GUSBCFG_CTP_Pos)                         /*!< USB GUSBCFG: CTP Mask                   */\r
+\r
+/* ---------------------------------  USB_GRSTCTL  -------------------------------- */\r
+#define USB_GRSTCTL_CSftRst_Pos               0                                                       /*!< USB GRSTCTL: CSftRst Position           */\r
+#define USB_GRSTCTL_CSftRst_Msk               (0x01UL << USB_GRSTCTL_CSftRst_Pos)                     /*!< USB GRSTCTL: CSftRst Mask               */\r
+#define USB_GRSTCTL_RxFFlsh_Pos               4                                                       /*!< USB GRSTCTL: RxFFlsh Position           */\r
+#define USB_GRSTCTL_RxFFlsh_Msk               (0x01UL << USB_GRSTCTL_RxFFlsh_Pos)                     /*!< USB GRSTCTL: RxFFlsh Mask               */\r
+#define USB_GRSTCTL_TxFFlsh_Pos               5                                                       /*!< USB GRSTCTL: TxFFlsh Position           */\r
+#define USB_GRSTCTL_TxFFlsh_Msk               (0x01UL << USB_GRSTCTL_TxFFlsh_Pos)                     /*!< USB GRSTCTL: TxFFlsh Mask               */\r
+#define USB_GRSTCTL_TxFNum_Pos                6                                                       /*!< USB GRSTCTL: TxFNum Position            */\r
+#define USB_GRSTCTL_TxFNum_Msk                (0x1fUL << USB_GRSTCTL_TxFNum_Pos)                      /*!< USB GRSTCTL: TxFNum Mask                */\r
+#define USB_GRSTCTL_DMAReq_Pos                30                                                      /*!< USB GRSTCTL: DMAReq Position            */\r
+#define USB_GRSTCTL_DMAReq_Msk                (0x01UL << USB_GRSTCTL_DMAReq_Pos)                      /*!< USB GRSTCTL: DMAReq Mask                */\r
+#define USB_GRSTCTL_AHBIdle_Pos               31                                                      /*!< USB GRSTCTL: AHBIdle Position           */\r
+#define USB_GRSTCTL_AHBIdle_Msk               (0x01UL << USB_GRSTCTL_AHBIdle_Pos)                     /*!< USB GRSTCTL: AHBIdle Mask               */\r
+\r
+/* ---------------------------------  USB_GINTSTS  -------------------------------- */\r
+#define USB_GINTSTS_CurMod_Pos                0                                                       /*!< USB GINTSTS: CurMod Position            */\r
+#define USB_GINTSTS_CurMod_Msk                (0x01UL << USB_GINTSTS_CurMod_Pos)                      /*!< USB GINTSTS: CurMod Mask                */\r
+#define USB_GINTSTS_Sof_Pos                   3                                                       /*!< USB GINTSTS: Sof Position               */\r
+#define USB_GINTSTS_Sof_Msk                   (0x01UL << USB_GINTSTS_Sof_Pos)                         /*!< USB GINTSTS: Sof Mask                   */\r
+#define USB_GINTSTS_RxFLvl_Pos                4                                                       /*!< USB GINTSTS: RxFLvl Position            */\r
+#define USB_GINTSTS_RxFLvl_Msk                (0x01UL << USB_GINTSTS_RxFLvl_Pos)                      /*!< USB GINTSTS: RxFLvl Mask                */\r
+#define USB_GINTSTS_GINNakEff_Pos             6                                                       /*!< USB GINTSTS: GINNakEff Position         */\r
+#define USB_GINTSTS_GINNakEff_Msk             (0x01UL << USB_GINTSTS_GINNakEff_Pos)                   /*!< USB GINTSTS: GINNakEff Mask             */\r
+#define USB_GINTSTS_GOUTNakEff_Pos            7                                                       /*!< USB GINTSTS: GOUTNakEff Position        */\r
+#define USB_GINTSTS_GOUTNakEff_Msk            (0x01UL << USB_GINTSTS_GOUTNakEff_Pos)                  /*!< USB GINTSTS: GOUTNakEff Mask            */\r
+#define USB_GINTSTS_ErlySusp_Pos              10                                                      /*!< USB GINTSTS: ErlySusp Position          */\r
+#define USB_GINTSTS_ErlySusp_Msk              (0x01UL << USB_GINTSTS_ErlySusp_Pos)                    /*!< USB GINTSTS: ErlySusp Mask              */\r
+#define USB_GINTSTS_USBSusp_Pos               11                                                      /*!< USB GINTSTS: USBSusp Position           */\r
+#define USB_GINTSTS_USBSusp_Msk               (0x01UL << USB_GINTSTS_USBSusp_Pos)                     /*!< USB GINTSTS: USBSusp Mask               */\r
+#define USB_GINTSTS_USBRst_Pos                12                                                      /*!< USB GINTSTS: USBRst Position            */\r
+#define USB_GINTSTS_USBRst_Msk                (0x01UL << USB_GINTSTS_USBRst_Pos)                      /*!< USB GINTSTS: USBRst Mask                */\r
+#define USB_GINTSTS_EnumDone_Pos              13                                                      /*!< USB GINTSTS: EnumDone Position          */\r
+#define USB_GINTSTS_EnumDone_Msk              (0x01UL << USB_GINTSTS_EnumDone_Pos)                    /*!< USB GINTSTS: EnumDone Mask              */\r
+#define USB_GINTSTS_ISOOutDrop_Pos            14                                                      /*!< USB GINTSTS: ISOOutDrop Position        */\r
+#define USB_GINTSTS_ISOOutDrop_Msk            (0x01UL << USB_GINTSTS_ISOOutDrop_Pos)                  /*!< USB GINTSTS: ISOOutDrop Mask            */\r
+#define USB_GINTSTS_EOPF_Pos                  15                                                      /*!< USB GINTSTS: EOPF Position              */\r
+#define USB_GINTSTS_EOPF_Msk                  (0x01UL << USB_GINTSTS_EOPF_Pos)                        /*!< USB GINTSTS: EOPF Mask                  */\r
+#define USB_GINTSTS_IEPInt_Pos                18                                                      /*!< USB GINTSTS: IEPInt Position            */\r
+#define USB_GINTSTS_IEPInt_Msk                (0x01UL << USB_GINTSTS_IEPInt_Pos)                      /*!< USB GINTSTS: IEPInt Mask                */\r
+#define USB_GINTSTS_OEPInt_Pos                19                                                      /*!< USB GINTSTS: OEPInt Position            */\r
+#define USB_GINTSTS_OEPInt_Msk                (0x01UL << USB_GINTSTS_OEPInt_Pos)                      /*!< USB GINTSTS: OEPInt Mask                */\r
+#define USB_GINTSTS_incompISOIN_Pos           20                                                      /*!< USB GINTSTS: incompISOIN Position       */\r
+#define USB_GINTSTS_incompISOIN_Msk           (0x01UL << USB_GINTSTS_incompISOIN_Pos)                 /*!< USB GINTSTS: incompISOIN Mask           */\r
+#define USB_GINTSTS_incomplSOOUT_Pos          21                                                      /*!< USB GINTSTS: incomplSOOUT Position      */\r
+#define USB_GINTSTS_incomplSOOUT_Msk          (0x01UL << USB_GINTSTS_incomplSOOUT_Pos)                /*!< USB GINTSTS: incomplSOOUT Mask          */\r
+#define USB_GINTSTS_WkUpInt_Pos               31                                                      /*!< USB GINTSTS: WkUpInt Position           */\r
+#define USB_GINTSTS_WkUpInt_Msk               (0x01UL << USB_GINTSTS_WkUpInt_Pos)                     /*!< USB GINTSTS: WkUpInt Mask               */\r
+\r
+/* ---------------------------------  USB_GINTMSK  -------------------------------- */\r
+#define USB_GINTMSK_SofMsk_Pos                3                                                       /*!< USB GINTMSK: SofMsk Position            */\r
+#define USB_GINTMSK_SofMsk_Msk                (0x01UL << USB_GINTMSK_SofMsk_Pos)                      /*!< USB GINTMSK: SofMsk Mask                */\r
+#define USB_GINTMSK_RxFLvlMsk_Pos             4                                                       /*!< USB GINTMSK: RxFLvlMsk Position         */\r
+#define USB_GINTMSK_RxFLvlMsk_Msk             (0x01UL << USB_GINTMSK_RxFLvlMsk_Pos)                   /*!< USB GINTMSK: RxFLvlMsk Mask             */\r
+#define USB_GINTMSK_GINNakEffMsk_Pos          6                                                       /*!< USB GINTMSK: GINNakEffMsk Position      */\r
+#define USB_GINTMSK_GINNakEffMsk_Msk          (0x01UL << USB_GINTMSK_GINNakEffMsk_Pos)                /*!< USB GINTMSK: GINNakEffMsk Mask          */\r
+#define USB_GINTMSK_GOUTNakEffMsk_Pos         7                                                       /*!< USB GINTMSK: GOUTNakEffMsk Position     */\r
+#define USB_GINTMSK_GOUTNakEffMsk_Msk         (0x01UL << USB_GINTMSK_GOUTNakEffMsk_Pos)               /*!< USB GINTMSK: GOUTNakEffMsk Mask         */\r
+#define USB_GINTMSK_ErlySuspMsk_Pos           10                                                      /*!< USB GINTMSK: ErlySuspMsk Position       */\r
+#define USB_GINTMSK_ErlySuspMsk_Msk           (0x01UL << USB_GINTMSK_ErlySuspMsk_Pos)                 /*!< USB GINTMSK: ErlySuspMsk Mask           */\r
+#define USB_GINTMSK_USBSuspMsk_Pos            11                                                      /*!< USB GINTMSK: USBSuspMsk Position        */\r
+#define USB_GINTMSK_USBSuspMsk_Msk            (0x01UL << USB_GINTMSK_USBSuspMsk_Pos)                  /*!< USB GINTMSK: USBSuspMsk Mask            */\r
+#define USB_GINTMSK_USBRstMsk_Pos             12                                                      /*!< USB GINTMSK: USBRstMsk Position         */\r
+#define USB_GINTMSK_USBRstMsk_Msk             (0x01UL << USB_GINTMSK_USBRstMsk_Pos)                   /*!< USB GINTMSK: USBRstMsk Mask             */\r
+#define USB_GINTMSK_EnumDoneMsk_Pos           13                                                      /*!< USB GINTMSK: EnumDoneMsk Position       */\r
+#define USB_GINTMSK_EnumDoneMsk_Msk           (0x01UL << USB_GINTMSK_EnumDoneMsk_Pos)                 /*!< USB GINTMSK: EnumDoneMsk Mask           */\r
+#define USB_GINTMSK_ISOOutDropMsk_Pos         14                                                      /*!< USB GINTMSK: ISOOutDropMsk Position     */\r
+#define USB_GINTMSK_ISOOutDropMsk_Msk         (0x01UL << USB_GINTMSK_ISOOutDropMsk_Pos)               /*!< USB GINTMSK: ISOOutDropMsk Mask         */\r
+#define USB_GINTMSK_EOPFMsk_Pos               15                                                      /*!< USB GINTMSK: EOPFMsk Position           */\r
+#define USB_GINTMSK_EOPFMsk_Msk               (0x01UL << USB_GINTMSK_EOPFMsk_Pos)                     /*!< USB GINTMSK: EOPFMsk Mask               */\r
+#define USB_GINTMSK_IEPIntMsk_Pos             18                                                      /*!< USB GINTMSK: IEPIntMsk Position         */\r
+#define USB_GINTMSK_IEPIntMsk_Msk             (0x01UL << USB_GINTMSK_IEPIntMsk_Pos)                   /*!< USB GINTMSK: IEPIntMsk Mask             */\r
+#define USB_GINTMSK_OEPIntMsk_Pos             19                                                      /*!< USB GINTMSK: OEPIntMsk Position         */\r
+#define USB_GINTMSK_OEPIntMsk_Msk             (0x01UL << USB_GINTMSK_OEPIntMsk_Pos)                   /*!< USB GINTMSK: OEPIntMsk Mask             */\r
+#define USB_GINTMSK_incompISOINMsk_Pos        20                                                      /*!< USB GINTMSK: incompISOINMsk Position    */\r
+#define USB_GINTMSK_incompISOINMsk_Msk        (0x01UL << USB_GINTMSK_incompISOINMsk_Pos)              /*!< USB GINTMSK: incompISOINMsk Mask        */\r
+#define USB_GINTMSK_incomplSOOUTMsk_Pos       21                                                      /*!< USB GINTMSK: incomplSOOUTMsk Position   */\r
+#define USB_GINTMSK_incomplSOOUTMsk_Msk       (0x01UL << USB_GINTMSK_incomplSOOUTMsk_Pos)             /*!< USB GINTMSK: incomplSOOUTMsk Mask       */\r
+#define USB_GINTMSK_WkUpIntMsk_Pos            31                                                      /*!< USB GINTMSK: WkUpIntMsk Position        */\r
+#define USB_GINTMSK_WkUpIntMsk_Msk            (0x01UL << USB_GINTMSK_WkUpIntMsk_Pos)                  /*!< USB GINTMSK: WkUpIntMsk Mask            */\r
+\r
+/* ---------------------------------  USB_GRXSTSR  -------------------------------- */\r
+#define USB_GRXSTSR_EPNum_Pos                 0                                                       /*!< USB GRXSTSR: EPNum Position             */\r
+#define USB_GRXSTSR_EPNum_Msk                 (0x0fUL << USB_GRXSTSR_EPNum_Pos)                       /*!< USB GRXSTSR: EPNum Mask                 */\r
+#define USB_GRXSTSR_BCnt_Pos                  4                                                       /*!< USB GRXSTSR: BCnt Position              */\r
+#define USB_GRXSTSR_BCnt_Msk                  (0x000007ffUL << USB_GRXSTSR_BCnt_Pos)                  /*!< USB GRXSTSR: BCnt Mask                  */\r
+#define USB_GRXSTSR_DPID_Pos                  15                                                      /*!< USB GRXSTSR: DPID Position              */\r
+#define USB_GRXSTSR_DPID_Msk                  (0x03UL << USB_GRXSTSR_DPID_Pos)                        /*!< USB GRXSTSR: DPID Mask                  */\r
+#define USB_GRXSTSR_PktSts_Pos                17                                                      /*!< USB GRXSTSR: PktSts Position            */\r
+#define USB_GRXSTSR_PktSts_Msk                (0x0fUL << USB_GRXSTSR_PktSts_Pos)                      /*!< USB GRXSTSR: PktSts Mask                */\r
+#define USB_GRXSTSR_FN_Pos                    21                                                      /*!< USB GRXSTSR: FN Position                */\r
+#define USB_GRXSTSR_FN_Msk                    (0x0fUL << USB_GRXSTSR_FN_Pos)                          /*!< USB GRXSTSR: FN Mask                    */\r
+\r
+/* ---------------------------------  USB_GRXSTSP  -------------------------------- */\r
+#define USB_GRXSTSP_EPNum_Pos                 0                                                       /*!< USB GRXSTSP: EPNum Position             */\r
+#define USB_GRXSTSP_EPNum_Msk                 (0x0fUL << USB_GRXSTSP_EPNum_Pos)                       /*!< USB GRXSTSP: EPNum Mask                 */\r
+#define USB_GRXSTSP_BCnt_Pos                  4                                                       /*!< USB GRXSTSP: BCnt Position              */\r
+#define USB_GRXSTSP_BCnt_Msk                  (0x000007ffUL << USB_GRXSTSP_BCnt_Pos)                  /*!< USB GRXSTSP: BCnt Mask                  */\r
+#define USB_GRXSTSP_DPID_Pos                  15                                                      /*!< USB GRXSTSP: DPID Position              */\r
+#define USB_GRXSTSP_DPID_Msk                  (0x03UL << USB_GRXSTSP_DPID_Pos)                        /*!< USB GRXSTSP: DPID Mask                  */\r
+#define USB_GRXSTSP_PktSts_Pos                17                                                      /*!< USB GRXSTSP: PktSts Position            */\r
+#define USB_GRXSTSP_PktSts_Msk                (0x0fUL << USB_GRXSTSP_PktSts_Pos)                      /*!< USB GRXSTSP: PktSts Mask                */\r
+#define USB_GRXSTSP_FN_Pos                    21                                                      /*!< USB GRXSTSP: FN Position                */\r
+#define USB_GRXSTSP_FN_Msk                    (0x0fUL << USB_GRXSTSP_FN_Pos)                          /*!< USB GRXSTSP: FN Mask                    */\r
+\r
+/* ---------------------------------  USB_GRXFSIZ  -------------------------------- */\r
+#define USB_GRXFSIZ_RxFDep_Pos                0                                                       /*!< USB GRXFSIZ: RxFDep Position            */\r
+#define USB_GRXFSIZ_RxFDep_Msk                (0x0000ffffUL << USB_GRXFSIZ_RxFDep_Pos)                /*!< USB GRXFSIZ: RxFDep Mask                */\r
+\r
+/* --------------------------------  USB_GNPTXFSIZ  ------------------------------- */\r
+#define USB_GNPTXFSIZ_INEPTxF0StAddr_Pos      0                                                       /*!< USB GNPTXFSIZ: INEPTxF0StAddr Position  */\r
+#define USB_GNPTXFSIZ_INEPTxF0StAddr_Msk      (0x0000ffffUL << USB_GNPTXFSIZ_INEPTxF0StAddr_Pos)      /*!< USB GNPTXFSIZ: INEPTxF0StAddr Mask      */\r
+#define USB_GNPTXFSIZ_INEPTxF0Dep_Pos         16                                                      /*!< USB GNPTXFSIZ: INEPTxF0Dep Position     */\r
+#define USB_GNPTXFSIZ_INEPTxF0Dep_Msk         (0x0000ffffUL << USB_GNPTXFSIZ_INEPTxF0Dep_Pos)         /*!< USB GNPTXFSIZ: INEPTxF0Dep Mask         */\r
+\r
+/* ----------------------------------  USB_GUID  ---------------------------------- */\r
+#define USB_GUID_MOD_REV_Pos                  0                                                       /*!< USB GUID: MOD_REV Position              */\r
+#define USB_GUID_MOD_REV_Msk                  (0x000000ffUL << USB_GUID_MOD_REV_Pos)                  /*!< USB GUID: MOD_REV Mask                  */\r
+#define USB_GUID_MOD_TYPE_Pos                 8                                                       /*!< USB GUID: MOD_TYPE Position             */\r
+#define USB_GUID_MOD_TYPE_Msk                 (0x000000ffUL << USB_GUID_MOD_TYPE_Pos)                 /*!< USB GUID: MOD_TYPE Mask                 */\r
+#define USB_GUID_MOD_NUMBER_Pos               16                                                      /*!< USB GUID: MOD_NUMBER Position           */\r
+#define USB_GUID_MOD_NUMBER_Msk               (0x0000ffffUL << USB_GUID_MOD_NUMBER_Pos)               /*!< USB GUID: MOD_NUMBER Mask               */\r
+\r
+/* --------------------------------  USB_GDFIFOCFG  ------------------------------- */\r
+#define USB_GDFIFOCFG_GDFIFOCfg_Pos           0                                                       /*!< USB GDFIFOCFG: GDFIFOCfg Position       */\r
+#define USB_GDFIFOCFG_GDFIFOCfg_Msk           (0x0000ffffUL << USB_GDFIFOCFG_GDFIFOCfg_Pos)           /*!< USB GDFIFOCFG: GDFIFOCfg Mask           */\r
+#define USB_GDFIFOCFG_EPInfoBaseAddr_Pos      16                                                      /*!< USB GDFIFOCFG: EPInfoBaseAddr Position  */\r
+#define USB_GDFIFOCFG_EPInfoBaseAddr_Msk      (0x0000ffffUL << USB_GDFIFOCFG_EPInfoBaseAddr_Pos)      /*!< USB GDFIFOCFG: EPInfoBaseAddr Mask      */\r
+\r
+/* --------------------------------  USB_DIEPTXF1  -------------------------------- */\r
+#define USB_DIEPTXF1_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF1: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF1_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF1_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF1: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF1_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF1: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF1_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF1_INEPnTxFDep_Pos)          /*!< USB DIEPTXF1: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF2  -------------------------------- */\r
+#define USB_DIEPTXF2_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF2: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF2_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF2_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF2: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF2_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF2: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF2_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF2_INEPnTxFDep_Pos)          /*!< USB DIEPTXF2: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF3  -------------------------------- */\r
+#define USB_DIEPTXF3_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF3: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF3_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF3_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF3: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF3_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF3: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF3_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF3_INEPnTxFDep_Pos)          /*!< USB DIEPTXF3: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF4  -------------------------------- */\r
+#define USB_DIEPTXF4_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF4: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF4_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF4_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF4: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF4_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF4: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF4_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF4_INEPnTxFDep_Pos)          /*!< USB DIEPTXF4: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF5  -------------------------------- */\r
+#define USB_DIEPTXF5_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF5: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF5_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF5_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF5: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF5_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF5: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF5_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF5_INEPnTxFDep_Pos)          /*!< USB DIEPTXF5: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF6  -------------------------------- */\r
+#define USB_DIEPTXF6_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF6: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF6_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF6_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF6: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF6_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF6: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF6_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF6_INEPnTxFDep_Pos)          /*!< USB DIEPTXF6: INEPnTxFDep Mask          */\r
+\r
+/* ----------------------------------  USB_DCFG  ---------------------------------- */\r
+#define USB_DCFG_DevSpd_Pos                   0                                                       /*!< USB DCFG: DevSpd Position               */\r
+#define USB_DCFG_DevSpd_Msk                   (0x03UL << USB_DCFG_DevSpd_Pos)                         /*!< USB DCFG: DevSpd Mask                   */\r
+#define USB_DCFG_NZStsOUTHShk_Pos             2                                                       /*!< USB DCFG: NZStsOUTHShk Position         */\r
+#define USB_DCFG_NZStsOUTHShk_Msk             (0x01UL << USB_DCFG_NZStsOUTHShk_Pos)                   /*!< USB DCFG: NZStsOUTHShk Mask             */\r
+#define USB_DCFG_DevAddr_Pos                  4                                                       /*!< USB DCFG: DevAddr Position              */\r
+#define USB_DCFG_DevAddr_Msk                  (0x7fUL << USB_DCFG_DevAddr_Pos)                        /*!< USB DCFG: DevAddr Mask                  */\r
+#define USB_DCFG_PerFrInt_Pos                 11                                                      /*!< USB DCFG: PerFrInt Position             */\r
+#define USB_DCFG_PerFrInt_Msk                 (0x03UL << USB_DCFG_PerFrInt_Pos)                       /*!< USB DCFG: PerFrInt Mask                 */\r
+#define USB_DCFG_DescDMA_Pos                  23                                                      /*!< USB DCFG: DescDMA Position              */\r
+#define USB_DCFG_DescDMA_Msk                  (0x01UL << USB_DCFG_DescDMA_Pos)                        /*!< USB DCFG: DescDMA Mask                  */\r
+#define USB_DCFG_PerSchIntvl_Pos              24                                                      /*!< USB DCFG: PerSchIntvl Position          */\r
+#define USB_DCFG_PerSchIntvl_Msk              (0x03UL << USB_DCFG_PerSchIntvl_Pos)                    /*!< USB DCFG: PerSchIntvl Mask              */\r
+\r
+/* ----------------------------------  USB_DCTL  ---------------------------------- */\r
+#define USB_DCTL_RmtWkUpSig_Pos               0                                                       /*!< USB DCTL: RmtWkUpSig Position           */\r
+#define USB_DCTL_RmtWkUpSig_Msk               (0x01UL << USB_DCTL_RmtWkUpSig_Pos)                     /*!< USB DCTL: RmtWkUpSig Mask               */\r
+#define USB_DCTL_SftDiscon_Pos                1                                                       /*!< USB DCTL: SftDiscon Position            */\r
+#define USB_DCTL_SftDiscon_Msk                (0x01UL << USB_DCTL_SftDiscon_Pos)                      /*!< USB DCTL: SftDiscon Mask                */\r
+#define USB_DCTL_GNPINNakSts_Pos              2                                                       /*!< USB DCTL: GNPINNakSts Position          */\r
+#define USB_DCTL_GNPINNakSts_Msk              (0x01UL << USB_DCTL_GNPINNakSts_Pos)                    /*!< USB DCTL: GNPINNakSts Mask              */\r
+#define USB_DCTL_GOUTNakSts_Pos               3                                                       /*!< USB DCTL: GOUTNakSts Position           */\r
+#define USB_DCTL_GOUTNakSts_Msk               (0x01UL << USB_DCTL_GOUTNakSts_Pos)                     /*!< USB DCTL: GOUTNakSts Mask               */\r
+#define USB_DCTL_SGNPInNak_Pos                7                                                       /*!< USB DCTL: SGNPInNak Position            */\r
+#define USB_DCTL_SGNPInNak_Msk                (0x01UL << USB_DCTL_SGNPInNak_Pos)                      /*!< USB DCTL: SGNPInNak Mask                */\r
+#define USB_DCTL_CGNPInNak_Pos                8                                                       /*!< USB DCTL: CGNPInNak Position            */\r
+#define USB_DCTL_CGNPInNak_Msk                (0x01UL << USB_DCTL_CGNPInNak_Pos)                      /*!< USB DCTL: CGNPInNak Mask                */\r
+#define USB_DCTL_SGOUTNak_Pos                 9                                                       /*!< USB DCTL: SGOUTNak Position             */\r
+#define USB_DCTL_SGOUTNak_Msk                 (0x01UL << USB_DCTL_SGOUTNak_Pos)                       /*!< USB DCTL: SGOUTNak Mask                 */\r
+#define USB_DCTL_CGOUTNak_Pos                 10                                                      /*!< USB DCTL: CGOUTNak Position             */\r
+#define USB_DCTL_CGOUTNak_Msk                 (0x01UL << USB_DCTL_CGOUTNak_Pos)                       /*!< USB DCTL: CGOUTNak Mask                 */\r
+#define USB_DCTL_GMC_Pos                      13                                                      /*!< USB DCTL: GMC Position                  */\r
+#define USB_DCTL_GMC_Msk                      (0x03UL << USB_DCTL_GMC_Pos)                            /*!< USB DCTL: GMC Mask                      */\r
+#define USB_DCTL_IgnrFrmNum_Pos               15                                                      /*!< USB DCTL: IgnrFrmNum Position           */\r
+#define USB_DCTL_IgnrFrmNum_Msk               (0x01UL << USB_DCTL_IgnrFrmNum_Pos)                     /*!< USB DCTL: IgnrFrmNum Mask               */\r
+#define USB_DCTL_NakOnBble_Pos                16                                                      /*!< USB DCTL: NakOnBble Position            */\r
+#define USB_DCTL_NakOnBble_Msk                (0x01UL << USB_DCTL_NakOnBble_Pos)                      /*!< USB DCTL: NakOnBble Mask                */\r
+#define USB_DCTL_EnContOnBNA_Pos              17                                                      /*!< USB DCTL: EnContOnBNA Position          */\r
+#define USB_DCTL_EnContOnBNA_Msk              (0x01UL << USB_DCTL_EnContOnBNA_Pos)                    /*!< USB DCTL: EnContOnBNA Mask              */\r
+\r
+/* ----------------------------------  USB_DSTS  ---------------------------------- */\r
+#define USB_DSTS_SuspSts_Pos                  0                                                       /*!< USB DSTS: SuspSts Position              */\r
+#define USB_DSTS_SuspSts_Msk                  (0x01UL << USB_DSTS_SuspSts_Pos)                        /*!< USB DSTS: SuspSts Mask                  */\r
+#define USB_DSTS_EnumSpd_Pos                  1                                                       /*!< USB DSTS: EnumSpd Position              */\r
+#define USB_DSTS_EnumSpd_Msk                  (0x03UL << USB_DSTS_EnumSpd_Pos)                        /*!< USB DSTS: EnumSpd Mask                  */\r
+#define USB_DSTS_ErrticErr_Pos                3                                                       /*!< USB DSTS: ErrticErr Position            */\r
+#define USB_DSTS_ErrticErr_Msk                (0x01UL << USB_DSTS_ErrticErr_Pos)                      /*!< USB DSTS: ErrticErr Mask                */\r
+#define USB_DSTS_SOFFN_Pos                    8                                                       /*!< USB DSTS: SOFFN Position                */\r
+#define USB_DSTS_SOFFN_Msk                    (0x00003fffUL << USB_DSTS_SOFFN_Pos)                    /*!< USB DSTS: SOFFN Mask                    */\r
+\r
+/* ---------------------------------  USB_DIEPMSK  -------------------------------- */\r
+#define USB_DIEPMSK_XferComplMsk_Pos          0                                                       /*!< USB DIEPMSK: XferComplMsk Position      */\r
+#define USB_DIEPMSK_XferComplMsk_Msk          (0x01UL << USB_DIEPMSK_XferComplMsk_Pos)                /*!< USB DIEPMSK: XferComplMsk Mask          */\r
+#define USB_DIEPMSK_EPDisbldMsk_Pos           1                                                       /*!< USB DIEPMSK: EPDisbldMsk Position       */\r
+#define USB_DIEPMSK_EPDisbldMsk_Msk           (0x01UL << USB_DIEPMSK_EPDisbldMsk_Pos)                 /*!< USB DIEPMSK: EPDisbldMsk Mask           */\r
+#define USB_DIEPMSK_AHBErrMsk_Pos             2                                                       /*!< USB DIEPMSK: AHBErrMsk Position         */\r
+#define USB_DIEPMSK_AHBErrMsk_Msk             (0x01UL << USB_DIEPMSK_AHBErrMsk_Pos)                   /*!< USB DIEPMSK: AHBErrMsk Mask             */\r
+#define USB_DIEPMSK_TimeOUTMsk_Pos            3                                                       /*!< USB DIEPMSK: TimeOUTMsk Position        */\r
+#define USB_DIEPMSK_TimeOUTMsk_Msk            (0x01UL << USB_DIEPMSK_TimeOUTMsk_Pos)                  /*!< USB DIEPMSK: TimeOUTMsk Mask            */\r
+#define USB_DIEPMSK_INTknTXFEmpMsk_Pos        4                                                       /*!< USB DIEPMSK: INTknTXFEmpMsk Position    */\r
+#define USB_DIEPMSK_INTknTXFEmpMsk_Msk        (0x01UL << USB_DIEPMSK_INTknTXFEmpMsk_Pos)              /*!< USB DIEPMSK: INTknTXFEmpMsk Mask        */\r
+#define USB_DIEPMSK_INEPNakEffMsk_Pos         6                                                       /*!< USB DIEPMSK: INEPNakEffMsk Position     */\r
+#define USB_DIEPMSK_INEPNakEffMsk_Msk         (0x01UL << USB_DIEPMSK_INEPNakEffMsk_Pos)               /*!< USB DIEPMSK: INEPNakEffMsk Mask         */\r
+#define USB_DIEPMSK_TxfifoUndrnMsk_Pos        8                                                       /*!< USB DIEPMSK: TxfifoUndrnMsk Position    */\r
+#define USB_DIEPMSK_TxfifoUndrnMsk_Msk        (0x01UL << USB_DIEPMSK_TxfifoUndrnMsk_Pos)              /*!< USB DIEPMSK: TxfifoUndrnMsk Mask        */\r
+#define USB_DIEPMSK_BNAInIntrMsk_Pos          9                                                       /*!< USB DIEPMSK: BNAInIntrMsk Position      */\r
+#define USB_DIEPMSK_BNAInIntrMsk_Msk          (0x01UL << USB_DIEPMSK_BNAInIntrMsk_Pos)                /*!< USB DIEPMSK: BNAInIntrMsk Mask          */\r
+#define USB_DIEPMSK_NAKMsk_Pos                13                                                      /*!< USB DIEPMSK: NAKMsk Position            */\r
+#define USB_DIEPMSK_NAKMsk_Msk                (0x01UL << USB_DIEPMSK_NAKMsk_Pos)                      /*!< USB DIEPMSK: NAKMsk Mask                */\r
+\r
+/* ---------------------------------  USB_DOEPMSK  -------------------------------- */\r
+#define USB_DOEPMSK_XferComplMsk_Pos          0                                                       /*!< USB DOEPMSK: XferComplMsk Position      */\r
+#define USB_DOEPMSK_XferComplMsk_Msk          (0x01UL << USB_DOEPMSK_XferComplMsk_Pos)                /*!< USB DOEPMSK: XferComplMsk Mask          */\r
+#define USB_DOEPMSK_EPDisbldMsk_Pos           1                                                       /*!< USB DOEPMSK: EPDisbldMsk Position       */\r
+#define USB_DOEPMSK_EPDisbldMsk_Msk           (0x01UL << USB_DOEPMSK_EPDisbldMsk_Pos)                 /*!< USB DOEPMSK: EPDisbldMsk Mask           */\r
+#define USB_DOEPMSK_AHBErrMsk_Pos             2                                                       /*!< USB DOEPMSK: AHBErrMsk Position         */\r
+#define USB_DOEPMSK_AHBErrMsk_Msk             (0x01UL << USB_DOEPMSK_AHBErrMsk_Pos)                   /*!< USB DOEPMSK: AHBErrMsk Mask             */\r
+#define USB_DOEPMSK_SetUPMsk_Pos              3                                                       /*!< USB DOEPMSK: SetUPMsk Position          */\r
+#define USB_DOEPMSK_SetUPMsk_Msk              (0x01UL << USB_DOEPMSK_SetUPMsk_Pos)                    /*!< USB DOEPMSK: SetUPMsk Mask              */\r
+#define USB_DOEPMSK_OUTTknEPdisMsk_Pos        4                                                       /*!< USB DOEPMSK: OUTTknEPdisMsk Position    */\r
+#define USB_DOEPMSK_OUTTknEPdisMsk_Msk        (0x01UL << USB_DOEPMSK_OUTTknEPdisMsk_Pos)              /*!< USB DOEPMSK: OUTTknEPdisMsk Mask        */\r
+#define USB_DOEPMSK_Back2BackSETup_Pos        6                                                       /*!< USB DOEPMSK: Back2BackSETup Position    */\r
+#define USB_DOEPMSK_Back2BackSETup_Msk        (0x01UL << USB_DOEPMSK_Back2BackSETup_Pos)              /*!< USB DOEPMSK: Back2BackSETup Mask        */\r
+#define USB_DOEPMSK_OutPktErrMsk_Pos          8                                                       /*!< USB DOEPMSK: OutPktErrMsk Position      */\r
+#define USB_DOEPMSK_OutPktErrMsk_Msk          (0x01UL << USB_DOEPMSK_OutPktErrMsk_Pos)                /*!< USB DOEPMSK: OutPktErrMsk Mask          */\r
+#define USB_DOEPMSK_BnaOutIntrMsk_Pos         9                                                       /*!< USB DOEPMSK: BnaOutIntrMsk Position     */\r
+#define USB_DOEPMSK_BnaOutIntrMsk_Msk         (0x01UL << USB_DOEPMSK_BnaOutIntrMsk_Pos)               /*!< USB DOEPMSK: BnaOutIntrMsk Mask         */\r
+#define USB_DOEPMSK_BbleErrMsk_Pos            12                                                      /*!< USB DOEPMSK: BbleErrMsk Position        */\r
+#define USB_DOEPMSK_BbleErrMsk_Msk            (0x01UL << USB_DOEPMSK_BbleErrMsk_Pos)                  /*!< USB DOEPMSK: BbleErrMsk Mask            */\r
+#define USB_DOEPMSK_NAKMsk_Pos                13                                                      /*!< USB DOEPMSK: NAKMsk Position            */\r
+#define USB_DOEPMSK_NAKMsk_Msk                (0x01UL << USB_DOEPMSK_NAKMsk_Pos)                      /*!< USB DOEPMSK: NAKMsk Mask                */\r
+#define USB_DOEPMSK_NYETMsk_Pos               14                                                      /*!< USB DOEPMSK: NYETMsk Position           */\r
+#define USB_DOEPMSK_NYETMsk_Msk               (0x01UL << USB_DOEPMSK_NYETMsk_Pos)                     /*!< USB DOEPMSK: NYETMsk Mask               */\r
+\r
+/* ----------------------------------  USB_DAINT  --------------------------------- */\r
+#define USB_DAINT_InEpInt_Pos                 0                                                       /*!< USB DAINT: InEpInt Position             */\r
+#define USB_DAINT_InEpInt_Msk                 (0x0000ffffUL << USB_DAINT_InEpInt_Pos)                 /*!< USB DAINT: InEpInt Mask                 */\r
+#define USB_DAINT_OutEPInt_Pos                16                                                      /*!< USB DAINT: OutEPInt Position            */\r
+#define USB_DAINT_OutEPInt_Msk                (0x0000ffffUL << USB_DAINT_OutEPInt_Pos)                /*!< USB DAINT: OutEPInt Mask                */\r
+\r
+/* --------------------------------  USB_DAINTMSK  -------------------------------- */\r
+#define USB_DAINTMSK_InEpMsk_Pos              0                                                       /*!< USB DAINTMSK: InEpMsk Position          */\r
+#define USB_DAINTMSK_InEpMsk_Msk              (0x0000ffffUL << USB_DAINTMSK_InEpMsk_Pos)              /*!< USB DAINTMSK: InEpMsk Mask              */\r
+#define USB_DAINTMSK_OutEpMsk_Pos             16                                                      /*!< USB DAINTMSK: OutEpMsk Position         */\r
+#define USB_DAINTMSK_OutEpMsk_Msk             (0x0000ffffUL << USB_DAINTMSK_OutEpMsk_Pos)             /*!< USB DAINTMSK: OutEpMsk Mask             */\r
+\r
+/* --------------------------------  USB_DVBUSDIS  -------------------------------- */\r
+#define USB_DVBUSDIS_DVBUSDis_Pos             0                                                       /*!< USB DVBUSDIS: DVBUSDis Position         */\r
+#define USB_DVBUSDIS_DVBUSDis_Msk             (0x0000ffffUL << USB_DVBUSDIS_DVBUSDis_Pos)             /*!< USB DVBUSDIS: DVBUSDis Mask             */\r
+\r
+/* -------------------------------  USB_DVBUSPULSE  ------------------------------- */\r
+#define USB_DVBUSPULSE_DVBUSPulse_Pos         0                                                       /*!< USB DVBUSPULSE: DVBUSPulse Position     */\r
+#define USB_DVBUSPULSE_DVBUSPulse_Msk         (0x00000fffUL << USB_DVBUSPULSE_DVBUSPulse_Pos)         /*!< USB DVBUSPULSE: DVBUSPulse Mask         */\r
+\r
+/* -------------------------------  USB_DIEPEMPMSK  ------------------------------- */\r
+#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos      0                                                       /*!< USB DIEPEMPMSK: InEpTxfEmpMsk Position  */\r
+#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk      (0x0000ffffUL << USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos)      /*!< USB DIEPEMPMSK: InEpTxfEmpMsk Mask      */\r
+\r
+/* ---------------------------------  USB_PCGCCTL  -------------------------------- */\r
+#define USB_PCGCCTL_StopPclk_Pos              0                                                       /*!< USB PCGCCTL: StopPclk Position          */\r
+#define USB_PCGCCTL_StopPclk_Msk              (0x01UL << USB_PCGCCTL_StopPclk_Pos)                    /*!< USB PCGCCTL: StopPclk Mask              */\r
+#define USB_PCGCCTL_GateHclk_Pos              1                                                       /*!< USB PCGCCTL: GateHclk Position          */\r
+#define USB_PCGCCTL_GateHclk_Msk              (0x01UL << USB_PCGCCTL_GateHclk_Pos)                    /*!< USB PCGCCTL: GateHclk Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'USB0_EP0' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  USB_EP_DIEPCTL0  ----------------------------- */\r
+#define USB_EP_DIEPCTL0_MPS_Pos             0                                                       /*!< USB0_EP0 DIEPCTL0: MPS Position         */\r
+#define USB_EP_DIEPCTL0_MPS_Msk             (0x03UL << USB_EP_DIEPCTL0_MPS_Pos)                   /*!< USB0_EP0 DIEPCTL0: MPS Mask             */\r
+#define USB_EP_DIEPCTL0_USBActEP_Pos        15                                                      /*!< USB0_EP0 DIEPCTL0: USBActEP Position    */\r
+#define USB_EP_DIEPCTL0_USBActEP_Msk        (0x01UL << USB_EP_DIEPCTL0_USBActEP_Pos)              /*!< USB0_EP0 DIEPCTL0: USBActEP Mask        */\r
+#define USB_EP_DIEPCTL0_NAKSts_Pos          17                                                      /*!< USB0_EP0 DIEPCTL0: NAKSts Position      */\r
+#define USB_EP_DIEPCTL0_NAKSts_Msk          (0x01UL << USB_EP_DIEPCTL0_NAKSts_Pos)                /*!< USB0_EP0 DIEPCTL0: NAKSts Mask          */\r
+#define USB_EP_DIEPCTL0_EPType_Pos          18                                                      /*!< USB0_EP0 DIEPCTL0: EPType Position      */\r
+#define USB_EP_DIEPCTL0_EPType_Msk          (0x03UL << USB_EP_DIEPCTL0_EPType_Pos)                /*!< USB0_EP0 DIEPCTL0: EPType Mask          */\r
+#define USB_EP_DIEPCTL0_Stall_Pos           21                                                      /*!< USB0_EP0 DIEPCTL0: Stall Position       */\r
+#define USB_EP_DIEPCTL0_Stall_Msk           (0x01UL << USB_EP_DIEPCTL0_Stall_Pos)                 /*!< USB0_EP0 DIEPCTL0: Stall Mask           */\r
+#define USB_EP_DIEPCTL0_TxFNum_Pos          22                                                      /*!< USB0_EP0 DIEPCTL0: TxFNum Position      */\r
+#define USB_EP_DIEPCTL0_TxFNum_Msk          (0x0fUL << USB_EP_DIEPCTL0_TxFNum_Pos)                /*!< USB0_EP0 DIEPCTL0: TxFNum Mask          */\r
+#define USB_EP_DIEPCTL0_CNAK_Pos            26                                                      /*!< USB0_EP0 DIEPCTL0: CNAK Position        */\r
+#define USB_EP_DIEPCTL0_CNAK_Msk            (0x01UL << USB_EP_DIEPCTL0_CNAK_Pos)                  /*!< USB0_EP0 DIEPCTL0: CNAK Mask            */\r
+#define USB_EP_DIEPCTL0_SNAK_Pos            27                                                      /*!< USB0_EP0 DIEPCTL0: SNAK Position        */\r
+#define USB_EP_DIEPCTL0_SNAK_Msk            (0x01UL << USB_EP_DIEPCTL0_SNAK_Pos)                  /*!< USB0_EP0 DIEPCTL0: SNAK Mask            */\r
+#define USB_EP_DIEPCTL0_EPDis_Pos           30                                                      /*!< USB0_EP0 DIEPCTL0: EPDis Position       */\r
+#define USB_EP_DIEPCTL0_EPDis_Msk           (0x01UL << USB_EP_DIEPCTL0_EPDis_Pos)                 /*!< USB0_EP0 DIEPCTL0: EPDis Mask           */\r
+#define USB_EP_DIEPCTL0_EPEna_Pos           31                                                      /*!< USB0_EP0 DIEPCTL0: EPEna Position       */\r
+#define USB_EP_DIEPCTL0_EPEna_Msk           (0x01UL << USB_EP_DIEPCTL0_EPEna_Pos)                 /*!< USB0_EP0 DIEPCTL0: EPEna Mask           */\r
+\r
+/* ------------------------------  USB_EP_DIEPINT0  ----------------------------- */\r
+#define USB_EP_DIEPINT0_XferCompl_Pos       0                                                       /*!< USB0_EP0 DIEPINT0: XferCompl Position   */\r
+#define USB_EP_DIEPINT0_XferCompl_Msk       (0x01UL << USB_EP_DIEPINT0_XferCompl_Pos)             /*!< USB0_EP0 DIEPINT0: XferCompl Mask       */\r
+#define USB_EP_DIEPINT0_EPDisbld_Pos        1                                                       /*!< USB0_EP0 DIEPINT0: EPDisbld Position    */\r
+#define USB_EP_DIEPINT0_EPDisbld_Msk        (0x01UL << USB_EP_DIEPINT0_EPDisbld_Pos)              /*!< USB0_EP0 DIEPINT0: EPDisbld Mask        */\r
+#define USB_EP_DIEPINT0_AHBErr_Pos          2                                                       /*!< USB0_EP0 DIEPINT0: AHBErr Position      */\r
+#define USB_EP_DIEPINT0_AHBErr_Msk          (0x01UL << USB_EP_DIEPINT0_AHBErr_Pos)                /*!< USB0_EP0 DIEPINT0: AHBErr Mask          */\r
+#define USB_EP_DIEPINT0_TimeOUT_Pos         3                                                       /*!< USB0_EP0 DIEPINT0: TimeOUT Position     */\r
+#define USB_EP_DIEPINT0_TimeOUT_Msk         (0x01UL << USB_EP_DIEPINT0_TimeOUT_Pos)               /*!< USB0_EP0 DIEPINT0: TimeOUT Mask         */\r
+#define USB_EP_DIEPINT0_INTknTXFEmp_Pos     4                                                       /*!< USB0_EP0 DIEPINT0: INTknTXFEmp Position */\r
+#define USB_EP_DIEPINT0_INTknTXFEmp_Msk     (0x01UL << USB_EP_DIEPINT0_INTknTXFEmp_Pos)           /*!< USB0_EP0 DIEPINT0: INTknTXFEmp Mask     */\r
+#define USB_EP_DIEPINT0_INEPNakEff_Pos      6                                                       /*!< USB0_EP0 DIEPINT0: INEPNakEff Position  */\r
+#define USB_EP_DIEPINT0_INEPNakEff_Msk      (0x01UL << USB_EP_DIEPINT0_INEPNakEff_Pos)            /*!< USB0_EP0 DIEPINT0: INEPNakEff Mask      */\r
+#define USB_EP_DIEPINT0_TxFEmp_Pos          7                                                       /*!< USB0_EP0 DIEPINT0: TxFEmp Position      */\r
+#define USB_EP_DIEPINT0_TxFEmp_Msk          (0x01UL << USB_EP_DIEPINT0_TxFEmp_Pos)                /*!< USB0_EP0 DIEPINT0: TxFEmp Mask          */\r
+#define USB_EP_DIEPINT0_BNAIntr_Pos         9                                                       /*!< USB0_EP0 DIEPINT0: BNAIntr Position     */\r
+#define USB_EP_DIEPINT0_BNAIntr_Msk         (0x01UL << USB_EP_DIEPINT0_BNAIntr_Pos)               /*!< USB0_EP0 DIEPINT0: BNAIntr Mask         */\r
+\r
+/* -----------------------------  USB_EP_DIEPTSIZ0  ----------------------------- */\r
+#define USB_EP_DIEPTSIZ0_XferSize_Pos       0                                                       /*!< USB0_EP0 DIEPTSIZ0: XferSize Position   */\r
+#define USB_EP_DIEPTSIZ0_XferSize_Msk       (0x7fUL << USB_EP_DIEPTSIZ0_XferSize_Pos)             /*!< USB0_EP0 DIEPTSIZ0: XferSize Mask       */\r
+#define USB_EP_DIEPTSIZ0_PktCnt_Pos         19                                                      /*!< USB0_EP0 DIEPTSIZ0: PktCnt Position     */\r
+#define USB_EP_DIEPTSIZ0_PktCnt_Msk         (0x03UL << USB_EP_DIEPTSIZ0_PktCnt_Pos)               /*!< USB0_EP0 DIEPTSIZ0: PktCnt Mask         */\r
+\r
+/* ------------------------------  USB_EP_DIEPDMA0  ----------------------------- */\r
+#define USB_EP_DIEPDMA0_DMAAddr_Pos         0                                                       /*!< USB0_EP0 DIEPDMA0: DMAAddr Position     */\r
+#define USB_EP_DIEPDMA0_DMAAddr_Msk         (0xffffffffUL << USB_EP_DIEPDMA0_DMAAddr_Pos)         /*!< USB0_EP0 DIEPDMA0: DMAAddr Mask         */\r
+\r
+/* ------------------------------  USB_EP_DTXFSTS0  ----------------------------- */\r
+#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos 0                                                       /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail Position */\r
+#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk (0x0000ffffUL << USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail Mask */\r
+\r
+/* -----------------------------  USB_EP_DIEPDMAB0  ----------------------------- */\r
+#define USB_EP_DIEPDMAB0_DMABufferAddr_Pos  0                                                       /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr Position */\r
+#define USB_EP_DIEPDMAB0_DMABufferAddr_Msk  (0xffffffffUL << USB_EP_DIEPDMAB0_DMABufferAddr_Pos)  /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr Mask  */\r
+\r
+/* ------------------------------  USB_EP_DOEPCTL0  ----------------------------- */\r
+#define USB_EP_DOEPCTL0_MPS_Pos             0                                                       /*!< USB0_EP0 DOEPCTL0: MPS Position         */\r
+#define USB_EP_DOEPCTL0_MPS_Msk             (0x03UL << USB_EP_DOEPCTL0_MPS_Pos)                   /*!< USB0_EP0 DOEPCTL0: MPS Mask             */\r
+#define USB_EP_DOEPCTL0_USBActEP_Pos        15                                                      /*!< USB0_EP0 DOEPCTL0: USBActEP Position    */\r
+#define USB_EP_DOEPCTL0_USBActEP_Msk        (0x01UL << USB_EP_DOEPCTL0_USBActEP_Pos)              /*!< USB0_EP0 DOEPCTL0: USBActEP Mask        */\r
+#define USB_EP_DOEPCTL0_NAKSts_Pos          17                                                      /*!< USB0_EP0 DOEPCTL0: NAKSts Position      */\r
+#define USB_EP_DOEPCTL0_NAKSts_Msk          (0x01UL << USB_EP_DOEPCTL0_NAKSts_Pos)                /*!< USB0_EP0 DOEPCTL0: NAKSts Mask          */\r
+#define USB_EP_DOEPCTL0_EPType_Pos          18                                                      /*!< USB0_EP0 DOEPCTL0: EPType Position      */\r
+#define USB_EP_DOEPCTL0_EPType_Msk          (0x03UL << USB_EP_DOEPCTL0_EPType_Pos)                /*!< USB0_EP0 DOEPCTL0: EPType Mask          */\r
+#define USB_EP_DOEPCTL0_Snp_Pos             20                                                      /*!< USB0_EP0 DOEPCTL0: Snp Position         */\r
+#define USB_EP_DOEPCTL0_Snp_Msk             (0x01UL << USB_EP_DOEPCTL0_Snp_Pos)                   /*!< USB0_EP0 DOEPCTL0: Snp Mask             */\r
+#define USB_EP_DOEPCTL0_Stall_Pos           21                                                      /*!< USB0_EP0 DOEPCTL0: Stall Position       */\r
+#define USB_EP_DOEPCTL0_Stall_Msk           (0x01UL << USB_EP_DOEPCTL0_Stall_Pos)                 /*!< USB0_EP0 DOEPCTL0: Stall Mask           */\r
+#define USB_EP_DOEPCTL0_CNAK_Pos            26                                                      /*!< USB0_EP0 DOEPCTL0: CNAK Position        */\r
+#define USB_EP_DOEPCTL0_CNAK_Msk            (0x01UL << USB_EP_DOEPCTL0_CNAK_Pos)                  /*!< USB0_EP0 DOEPCTL0: CNAK Mask            */\r
+#define USB_EP_DOEPCTL0_SNAK_Pos            27                                                      /*!< USB0_EP0 DOEPCTL0: SNAK Position        */\r
+#define USB_EP_DOEPCTL0_SNAK_Msk            (0x01UL << USB_EP_DOEPCTL0_SNAK_Pos)                  /*!< USB0_EP0 DOEPCTL0: SNAK Mask            */\r
+#define USB_EP_DOEPCTL0_EPDis_Pos           30                                                      /*!< USB0_EP0 DOEPCTL0: EPDis Position       */\r
+#define USB_EP_DOEPCTL0_EPDis_Msk           (0x01UL << USB_EP_DOEPCTL0_EPDis_Pos)                 /*!< USB0_EP0 DOEPCTL0: EPDis Mask           */\r
+#define USB_EP_DOEPCTL0_EPEna_Pos           31                                                      /*!< USB0_EP0 DOEPCTL0: EPEna Position       */\r
+#define USB_EP_DOEPCTL0_EPEna_Msk           (0x01UL << USB_EP_DOEPCTL0_EPEna_Pos)                 /*!< USB0_EP0 DOEPCTL0: EPEna Mask           */\r
+\r
+/* ------------------------------  USB_EP_DOEPINT0  ----------------------------- */\r
+#define USB_EP_DOEPINT0_XferCompl_Pos       0                                                       /*!< USB0_EP0 DOEPINT0: XferCompl Position   */\r
+#define USB_EP_DOEPINT0_XferCompl_Msk       (0x01UL << USB_EP_DOEPINT0_XferCompl_Pos)             /*!< USB0_EP0 DOEPINT0: XferCompl Mask       */\r
+#define USB_EP_DOEPINT0_EPDisbld_Pos        1                                                       /*!< USB0_EP0 DOEPINT0: EPDisbld Position    */\r
+#define USB_EP_DOEPINT0_EPDisbld_Msk        (0x01UL << USB_EP_DOEPINT0_EPDisbld_Pos)              /*!< USB0_EP0 DOEPINT0: EPDisbld Mask        */\r
+#define USB_EP_DOEPINT0_AHBErr_Pos          2                                                       /*!< USB0_EP0 DOEPINT0: AHBErr Position      */\r
+#define USB_EP_DOEPINT0_AHBErr_Msk          (0x01UL << USB_EP_DOEPINT0_AHBErr_Pos)                /*!< USB0_EP0 DOEPINT0: AHBErr Mask          */\r
+#define USB_EP_DOEPINT0_SetUp_Pos           3                                                       /*!< USB0_EP0 DOEPINT0: SetUp Position       */\r
+#define USB_EP_DOEPINT0_SetUp_Msk           (0x01UL << USB_EP_DOEPINT0_SetUp_Pos)                 /*!< USB0_EP0 DOEPINT0: SetUp Mask           */\r
+#define USB_EP_DOEPINT0_OUTTknEPdis_Pos     4                                                       /*!< USB0_EP0 DOEPINT0: OUTTknEPdis Position */\r
+#define USB_EP_DOEPINT0_OUTTknEPdis_Msk     (0x01UL << USB_EP_DOEPINT0_OUTTknEPdis_Pos)           /*!< USB0_EP0 DOEPINT0: OUTTknEPdis Mask     */\r
+#define USB_EP_DOEPINT0_StsPhseRcvd_Pos     5                                                       /*!< USB0_EP0 DOEPINT0: StsPhseRcvd Position */\r
+#define USB_EP_DOEPINT0_StsPhseRcvd_Msk     (0x01UL << USB_EP_DOEPINT0_StsPhseRcvd_Pos)           /*!< USB0_EP0 DOEPINT0: StsPhseRcvd Mask     */\r
+#define USB_EP_DOEPINT0_Back2BackSETup_Pos  6                                                       /*!< USB0_EP0 DOEPINT0: Back2BackSETup Position */\r
+#define USB_EP_DOEPINT0_Back2BackSETup_Msk  (0x01UL << USB_EP_DOEPINT0_Back2BackSETup_Pos)        /*!< USB0_EP0 DOEPINT0: Back2BackSETup Mask  */\r
+#define USB_EP_DOEPINT0_BNAIntr_Pos         9                                                       /*!< USB0_EP0 DOEPINT0: BNAIntr Position     */\r
+#define USB_EP_DOEPINT0_BNAIntr_Msk         (0x01UL << USB_EP_DOEPINT0_BNAIntr_Pos)               /*!< USB0_EP0 DOEPINT0: BNAIntr Mask         */\r
+#define USB_EP_DOEPINT0_PktDrpSts_Pos       11                                                      /*!< USB0_EP0 DOEPINT0: PktDrpSts Position   */\r
+#define USB_EP_DOEPINT0_PktDrpSts_Msk       (0x01UL << USB_EP_DOEPINT0_PktDrpSts_Pos)             /*!< USB0_EP0 DOEPINT0: PktDrpSts Mask       */\r
+#define USB_EP_DOEPINT0_BbleErrIntrpt_Pos   12                                                      /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt Position */\r
+#define USB_EP_DOEPINT0_BbleErrIntrpt_Msk   (0x01UL << USB_EP_DOEPINT0_BbleErrIntrpt_Pos)         /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt Mask   */\r
+#define USB_EP_DOEPINT0_NAKIntrpt_Pos       13                                                      /*!< USB0_EP0 DOEPINT0: NAKIntrpt Position   */\r
+#define USB_EP_DOEPINT0_NAKIntrpt_Msk       (0x01UL << USB_EP_DOEPINT0_NAKIntrpt_Pos)             /*!< USB0_EP0 DOEPINT0: NAKIntrpt Mask       */\r
+#define USB_EP_DOEPINT0_NYETIntrpt_Pos      14                                                      /*!< USB0_EP0 DOEPINT0: NYETIntrpt Position  */\r
+#define USB_EP_DOEPINT0_NYETIntrpt_Msk      (0x01UL << USB_EP_DOEPINT0_NYETIntrpt_Pos)            /*!< USB0_EP0 DOEPINT0: NYETIntrpt Mask      */\r
+\r
+/* -----------------------------  USB_EP_DOEPTSIZ0  ----------------------------- */\r
+#define USB_EP_DOEPTSIZ0_XferSize_Pos       0                                                       /*!< USB0_EP0 DOEPTSIZ0: XferSize Position   */\r
+#define USB_EP_DOEPTSIZ0_XferSize_Msk       (0x7fUL << USB_EP_DOEPTSIZ0_XferSize_Pos)             /*!< USB0_EP0 DOEPTSIZ0: XferSize Mask       */\r
+#define USB_EP_DOEPTSIZ0_PktCnt_Pos         19                                                      /*!< USB0_EP0 DOEPTSIZ0: PktCnt Position     */\r
+#define USB_EP_DOEPTSIZ0_PktCnt_Msk         (0x03UL << USB_EP_DOEPTSIZ0_PktCnt_Pos)               /*!< USB0_EP0 DOEPTSIZ0: PktCnt Mask         */\r
+#define USB_EP_DOEPTSIZ0_SUPCnt_Pos         29                                                      /*!< USB0_EP0 DOEPTSIZ0: SUPCnt Position     */\r
+#define USB_EP_DOEPTSIZ0_SUPCnt_Msk         (0x03UL << USB_EP_DOEPTSIZ0_SUPCnt_Pos)               /*!< USB0_EP0 DOEPTSIZ0: SUPCnt Mask         */\r
+\r
+/* ------------------------------  USB_EP_DOEPDMA0  ----------------------------- */\r
+#define USB_EP_DOEPDMA0_DMAAddr_Pos         0                                                       /*!< USB0_EP0 DOEPDMA0: DMAAddr Position     */\r
+#define USB_EP_DOEPDMA0_DMAAddr_Msk         (0xffffffffUL << USB_EP_DOEPDMA0_DMAAddr_Pos)         /*!< USB0_EP0 DOEPDMA0: DMAAddr Mask         */\r
+\r
+/* -----------------------------  USB_EP_DOEPDMAB0  ----------------------------- */\r
+#define USB_EP_DOEPDMAB0_DMABufferAddr_Pos  0                                                       /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr Position */\r
+#define USB_EP_DOEPDMAB0_DMABufferAddr_Msk  (0xffffffffUL << USB_EP_DOEPDMAB0_DMABufferAddr_Pos)  /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr Mask  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'USB_EP' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------  USB_EP_DIEPCTL_ISOCONT  --------------------------- */\r
+#define USB_EP_DIEPCTL_ISOCONT_MPS_Pos        0                                                       /*!< USB_EP DIEPCTL_ISOCONT: MPS Position    */\r
+#define USB_EP_DIEPCTL_ISOCONT_MPS_Msk        (0x000007ffUL << USB_EP_DIEPCTL_ISOCONT_MPS_Pos)        /*!< USB_EP DIEPCTL_ISOCONT: MPS Mask        */\r
+#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos   15                                                      /*!< USB_EP DIEPCTL_ISOCONT: USBActEP Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk   (0x01UL << USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos)         /*!< USB_EP DIEPCTL_ISOCONT: USBActEP Mask   */\r
+#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos   16                                                      /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk   (0x01UL << USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos)         /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum Mask   */\r
+#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos     17                                                      /*!< USB_EP DIEPCTL_ISOCONT: NAKSts Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk     (0x01UL << USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos)           /*!< USB_EP DIEPCTL_ISOCONT: NAKSts Mask     */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPType_Pos     18                                                      /*!< USB_EP DIEPCTL_ISOCONT: EPType Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPType_Msk     (0x03UL << USB_EP_DIEPCTL_ISOCONT_EPType_Pos)           /*!< USB_EP DIEPCTL_ISOCONT: EPType Mask     */\r
+#define USB_EP_DIEPCTL_ISOCONT_Snp_Pos        20                                                      /*!< USB_EP DIEPCTL_ISOCONT: Snp Position    */\r
+#define USB_EP_DIEPCTL_ISOCONT_Snp_Msk        (0x01UL << USB_EP_DIEPCTL_ISOCONT_Snp_Pos)              /*!< USB_EP DIEPCTL_ISOCONT: Snp Mask        */\r
+#define USB_EP_DIEPCTL_ISOCONT_Stall_Pos      21                                                      /*!< USB_EP DIEPCTL_ISOCONT: Stall Position  */\r
+#define USB_EP_DIEPCTL_ISOCONT_Stall_Msk      (0x01UL << USB_EP_DIEPCTL_ISOCONT_Stall_Pos)            /*!< USB_EP DIEPCTL_ISOCONT: Stall Mask      */\r
+#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos     22                                                      /*!< USB_EP DIEPCTL_ISOCONT: TxFNum Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk     (0x0fUL << USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos)           /*!< USB_EP DIEPCTL_ISOCONT: TxFNum Mask     */\r
+#define USB_EP_DIEPCTL_ISOCONT_CNAK_Pos       26                                                      /*!< USB_EP DIEPCTL_ISOCONT: CNAK Position   */\r
+#define USB_EP_DIEPCTL_ISOCONT_CNAK_Msk       (0x01UL << USB_EP_DIEPCTL_ISOCONT_CNAK_Pos)             /*!< USB_EP DIEPCTL_ISOCONT: CNAK Mask       */\r
+#define USB_EP_DIEPCTL_ISOCONT_SNAK_Pos       27                                                      /*!< USB_EP DIEPCTL_ISOCONT: SNAK Position   */\r
+#define USB_EP_DIEPCTL_ISOCONT_SNAK_Msk       (0x01UL << USB_EP_DIEPCTL_ISOCONT_SNAK_Pos)             /*!< USB_EP DIEPCTL_ISOCONT: SNAK Mask       */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos  28                                                      /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk  (0x01UL << USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos)        /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr Mask  */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos   29                                                      /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk   (0x01UL << USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos)         /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr Mask   */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPDis_Pos      30                                                      /*!< USB_EP DIEPCTL_ISOCONT: EPDis Position  */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPDis_Msk      (0x01UL << USB_EP_DIEPCTL_ISOCONT_EPDis_Pos)            /*!< USB_EP DIEPCTL_ISOCONT: EPDis Mask      */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPEna_Pos      31                                                      /*!< USB_EP DIEPCTL_ISOCONT: EPEna Position  */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPEna_Msk      (0x01UL << USB_EP_DIEPCTL_ISOCONT_EPEna_Pos)            /*!< USB_EP DIEPCTL_ISOCONT: EPEna Mask      */\r
+\r
+/* ---------------------------  USB_EP_DIEPCTL_INTBULK  --------------------------- */\r
+#define USB_EP_DIEPCTL_INTBULK_MPS_Pos        0                                                       /*!< USB_EP DIEPCTL_INTBULK: MPS Position    */\r
+#define USB_EP_DIEPCTL_INTBULK_MPS_Msk        (0x000007ffUL << USB_EP_DIEPCTL_INTBULK_MPS_Pos)        /*!< USB_EP DIEPCTL_INTBULK: MPS Mask        */\r
+#define USB_EP_DIEPCTL_INTBULK_USBActEP_Pos   15                                                      /*!< USB_EP DIEPCTL_INTBULK: USBActEP Position */\r
+#define USB_EP_DIEPCTL_INTBULK_USBActEP_Msk   (0x01UL << USB_EP_DIEPCTL_INTBULK_USBActEP_Pos)         /*!< USB_EP DIEPCTL_INTBULK: USBActEP Mask   */\r
+#define USB_EP_DIEPCTL_INTBULK_DPID_Pos       16                                                      /*!< USB_EP DIEPCTL_INTBULK: DPID Position   */\r
+#define USB_EP_DIEPCTL_INTBULK_DPID_Msk       (0x01UL << USB_EP_DIEPCTL_INTBULK_DPID_Pos)             /*!< USB_EP DIEPCTL_INTBULK: DPID Mask       */\r
+#define USB_EP_DIEPCTL_INTBULK_NAKSts_Pos     17                                                      /*!< USB_EP DIEPCTL_INTBULK: NAKSts Position */\r
+#define USB_EP_DIEPCTL_INTBULK_NAKSts_Msk     (0x01UL << USB_EP_DIEPCTL_INTBULK_NAKSts_Pos)           /*!< USB_EP DIEPCTL_INTBULK: NAKSts Mask     */\r
+#define USB_EP_DIEPCTL_INTBULK_EPType_Pos     18                                                      /*!< USB_EP DIEPCTL_INTBULK: EPType Position */\r
+#define USB_EP_DIEPCTL_INTBULK_EPType_Msk     (0x03UL << USB_EP_DIEPCTL_INTBULK_EPType_Pos)           /*!< USB_EP DIEPCTL_INTBULK: EPType Mask     */\r
+#define USB_EP_DIEPCTL_INTBULK_Snp_Pos        20                                                      /*!< USB_EP DIEPCTL_INTBULK: Snp Position    */\r
+#define USB_EP_DIEPCTL_INTBULK_Snp_Msk        (0x01UL << USB_EP_DIEPCTL_INTBULK_Snp_Pos)              /*!< USB_EP DIEPCTL_INTBULK: Snp Mask        */\r
+#define USB_EP_DIEPCTL_INTBULK_Stall_Pos      21                                                      /*!< USB_EP DIEPCTL_INTBULK: Stall Position  */\r
+#define USB_EP_DIEPCTL_INTBULK_Stall_Msk      (0x01UL << USB_EP_DIEPCTL_INTBULK_Stall_Pos)            /*!< USB_EP DIEPCTL_INTBULK: Stall Mask      */\r
+#define USB_EP_DIEPCTL_INTBULK_TxFNum_Pos     22                                                      /*!< USB_EP DIEPCTL_INTBULK: TxFNum Position */\r
+#define USB_EP_DIEPCTL_INTBULK_TxFNum_Msk     (0x0fUL << USB_EP_DIEPCTL_INTBULK_TxFNum_Pos)           /*!< USB_EP DIEPCTL_INTBULK: TxFNum Mask     */\r
+#define USB_EP_DIEPCTL_INTBULK_CNAK_Pos       26                                                      /*!< USB_EP DIEPCTL_INTBULK: CNAK Position   */\r
+#define USB_EP_DIEPCTL_INTBULK_CNAK_Msk       (0x01UL << USB_EP_DIEPCTL_INTBULK_CNAK_Pos)             /*!< USB_EP DIEPCTL_INTBULK: CNAK Mask       */\r
+#define USB_EP_DIEPCTL_INTBULK_SNAK_Pos       27                                                      /*!< USB_EP DIEPCTL_INTBULK: SNAK Position   */\r
+#define USB_EP_DIEPCTL_INTBULK_SNAK_Msk       (0x01UL << USB_EP_DIEPCTL_INTBULK_SNAK_Pos)             /*!< USB_EP DIEPCTL_INTBULK: SNAK Mask       */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos   28                                                      /*!< USB_EP DIEPCTL_INTBULK: SetD0PID Position */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk   (0x01UL << USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos)         /*!< USB_EP DIEPCTL_INTBULK: SetD0PID Mask   */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos   29                                                      /*!< USB_EP DIEPCTL_INTBULK: SetD1PID Position */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk   (0x01UL << USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos)         /*!< USB_EP DIEPCTL_INTBULK: SetD1PID Mask   */\r
+#define USB_EP_DIEPCTL_INTBULK_EPDis_Pos      30                                                      /*!< USB_EP DIEPCTL_INTBULK: EPDis Position  */\r
+#define USB_EP_DIEPCTL_INTBULK_EPDis_Msk      (0x01UL << USB_EP_DIEPCTL_INTBULK_EPDis_Pos)            /*!< USB_EP DIEPCTL_INTBULK: EPDis Mask      */\r
+#define USB_EP_DIEPCTL_INTBULK_EPEna_Pos      31                                                      /*!< USB_EP DIEPCTL_INTBULK: EPEna Position  */\r
+#define USB_EP_DIEPCTL_INTBULK_EPEna_Msk      (0x01UL << USB_EP_DIEPCTL_INTBULK_EPEna_Pos)            /*!< USB_EP DIEPCTL_INTBULK: EPEna Mask      */\r
+\r
+/* -------------------------------  USB_EP_DIEPINT  ------------------------------- */\r
+#define USB_EP_DIEPINT_XferCompl_Pos          0                                                       /*!< USB_EP DIEPINT: XferCompl Position      */\r
+#define USB_EP_DIEPINT_XferCompl_Msk          (0x01UL << USB_EP_DIEPINT_XferCompl_Pos)                /*!< USB_EP DIEPINT: XferCompl Mask          */\r
+#define USB_EP_DIEPINT_EPDisbld_Pos           1                                                       /*!< USB_EP DIEPINT: EPDisbld Position       */\r
+#define USB_EP_DIEPINT_EPDisbld_Msk           (0x01UL << USB_EP_DIEPINT_EPDisbld_Pos)                 /*!< USB_EP DIEPINT: EPDisbld Mask           */\r
+#define USB_EP_DIEPINT_AHBErr_Pos             2                                                       /*!< USB_EP DIEPINT: AHBErr Position         */\r
+#define USB_EP_DIEPINT_AHBErr_Msk             (0x01UL << USB_EP_DIEPINT_AHBErr_Pos)                   /*!< USB_EP DIEPINT: AHBErr Mask             */\r
+#define USB_EP_DIEPINT_TimeOUT_Pos            3                                                       /*!< USB_EP DIEPINT: TimeOUT Position        */\r
+#define USB_EP_DIEPINT_TimeOUT_Msk            (0x01UL << USB_EP_DIEPINT_TimeOUT_Pos)                  /*!< USB_EP DIEPINT: TimeOUT Mask            */\r
+#define USB_EP_DIEPINT_INTknTXFEmp_Pos        4                                                       /*!< USB_EP DIEPINT: INTknTXFEmp Position    */\r
+#define USB_EP_DIEPINT_INTknTXFEmp_Msk        (0x01UL << USB_EP_DIEPINT_INTknTXFEmp_Pos)              /*!< USB_EP DIEPINT: INTknTXFEmp Mask        */\r
+#define USB_EP_DIEPINT_INEPNakEff_Pos         6                                                       /*!< USB_EP DIEPINT: INEPNakEff Position     */\r
+#define USB_EP_DIEPINT_INEPNakEff_Msk         (0x01UL << USB_EP_DIEPINT_INEPNakEff_Pos)               /*!< USB_EP DIEPINT: INEPNakEff Mask         */\r
+#define USB_EP_DIEPINT_TxFEmp_Pos             7                                                       /*!< USB_EP DIEPINT: TxFEmp Position         */\r
+#define USB_EP_DIEPINT_TxFEmp_Msk             (0x01UL << USB_EP_DIEPINT_TxFEmp_Pos)                   /*!< USB_EP DIEPINT: TxFEmp Mask             */\r
+#define USB_EP_DIEPINT_BNAIntr_Pos            9                                                       /*!< USB_EP DIEPINT: BNAIntr Position        */\r
+#define USB_EP_DIEPINT_BNAIntr_Msk            (0x01UL << USB_EP_DIEPINT_BNAIntr_Pos)                  /*!< USB_EP DIEPINT: BNAIntr Mask            */\r
+\r
+/* -------------------------------  USB_EP_DIEPTSIZ  ------------------------------ */\r
+#define USB_EP_DIEPTSIZ_XferSize_Pos          0                                                       /*!< USB_EP DIEPTSIZ: XferSize Position      */\r
+#define USB_EP_DIEPTSIZ_XferSize_Msk          (0x0007ffffUL << USB_EP_DIEPTSIZ_XferSize_Pos)          /*!< USB_EP DIEPTSIZ: XferSize Mask          */\r
+#define USB_EP_DIEPTSIZ_PktCnt_Pos            19                                                      /*!< USB_EP DIEPTSIZ: PktCnt Position        */\r
+#define USB_EP_DIEPTSIZ_PktCnt_Msk            (0x000003ffUL << USB_EP_DIEPTSIZ_PktCnt_Pos)            /*!< USB_EP DIEPTSIZ: PktCnt Mask            */\r
+\r
+/* -------------------------------  USB_EP_DIEPDMA  ------------------------------- */\r
+#define USB_EP_DIEPDMA_DMAAddr_Pos            0                                                       /*!< USB_EP DIEPDMA: DMAAddr Position        */\r
+#define USB_EP_DIEPDMA_DMAAddr_Msk            (0xffffffffUL << USB_EP_DIEPDMA_DMAAddr_Pos)            /*!< USB_EP DIEPDMA: DMAAddr Mask            */\r
+\r
+/* -------------------------------  USB_EP_DTXFSTS  ------------------------------- */\r
+#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos    0                                                       /*!< USB_EP DTXFSTS: INEPTxFSpcAvail Position */\r
+#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk    (0x0000ffffUL << USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos)    /*!< USB_EP DTXFSTS: INEPTxFSpcAvail Mask    */\r
+\r
+/* -------------------------------  USB_EP_DIEPDMAB  ------------------------------ */\r
+#define USB_EP_DIEPDMAB_DMABufferAddr_Pos     0                                                       /*!< USB_EP DIEPDMAB: DMABufferAddr Position */\r
+#define USB_EP_DIEPDMAB_DMABufferAddr_Msk     (0xffffffffUL << USB_EP_DIEPDMAB_DMABufferAddr_Pos)     /*!< USB_EP DIEPDMAB: DMABufferAddr Mask     */\r
+\r
+/* ---------------------------  USB_EP_DOEPCTL_ISOCONT  --------------------------- */\r
+#define USB_EP_DOEPCTL_ISOCONT_MPS_Pos        0                                                       /*!< USB_EP DOEPCTL_ISOCONT: MPS Position    */\r
+#define USB_EP_DOEPCTL_ISOCONT_MPS_Msk        (0x000007ffUL << USB_EP_DOEPCTL_ISOCONT_MPS_Pos)        /*!< USB_EP DOEPCTL_ISOCONT: MPS Mask        */\r
+#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos   15                                                      /*!< USB_EP DOEPCTL_ISOCONT: USBActEP Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk   (0x01UL << USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos)         /*!< USB_EP DOEPCTL_ISOCONT: USBActEP Mask   */\r
+#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos   16                                                      /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk   (0x01UL << USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos)         /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum Mask   */\r
+#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos     17                                                      /*!< USB_EP DOEPCTL_ISOCONT: NAKSts Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk     (0x01UL << USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos)           /*!< USB_EP DOEPCTL_ISOCONT: NAKSts Mask     */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPType_Pos     18                                                      /*!< USB_EP DOEPCTL_ISOCONT: EPType Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPType_Msk     (0x03UL << USB_EP_DOEPCTL_ISOCONT_EPType_Pos)           /*!< USB_EP DOEPCTL_ISOCONT: EPType Mask     */\r
+#define USB_EP_DOEPCTL_ISOCONT_Snp_Pos        20                                                      /*!< USB_EP DOEPCTL_ISOCONT: Snp Position    */\r
+#define USB_EP_DOEPCTL_ISOCONT_Snp_Msk        (0x01UL << USB_EP_DOEPCTL_ISOCONT_Snp_Pos)              /*!< USB_EP DOEPCTL_ISOCONT: Snp Mask        */\r
+#define USB_EP_DOEPCTL_ISOCONT_Stall_Pos      21                                                      /*!< USB_EP DOEPCTL_ISOCONT: Stall Position  */\r
+#define USB_EP_DOEPCTL_ISOCONT_Stall_Msk      (0x01UL << USB_EP_DOEPCTL_ISOCONT_Stall_Pos)            /*!< USB_EP DOEPCTL_ISOCONT: Stall Mask      */\r
+#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos     22                                                      /*!< USB_EP DOEPCTL_ISOCONT: TxFNum Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk     (0x0fUL << USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos)           /*!< USB_EP DOEPCTL_ISOCONT: TxFNum Mask     */\r
+#define USB_EP_DOEPCTL_ISOCONT_CNAK_Pos       26                                                      /*!< USB_EP DOEPCTL_ISOCONT: CNAK Position   */\r
+#define USB_EP_DOEPCTL_ISOCONT_CNAK_Msk       (0x01UL << USB_EP_DOEPCTL_ISOCONT_CNAK_Pos)             /*!< USB_EP DOEPCTL_ISOCONT: CNAK Mask       */\r
+#define USB_EP_DOEPCTL_ISOCONT_SNAK_Pos       27                                                      /*!< USB_EP DOEPCTL_ISOCONT: SNAK Position   */\r
+#define USB_EP_DOEPCTL_ISOCONT_SNAK_Msk       (0x01UL << USB_EP_DOEPCTL_ISOCONT_SNAK_Pos)             /*!< USB_EP DOEPCTL_ISOCONT: SNAK Mask       */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos  28                                                      /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk  (0x01UL << USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos)        /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr Mask  */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos   29                                                      /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk   (0x01UL << USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos)         /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr Mask   */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPDis_Pos      30                                                      /*!< USB_EP DOEPCTL_ISOCONT: EPDis Position  */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPDis_Msk      (0x01UL << USB_EP_DOEPCTL_ISOCONT_EPDis_Pos)            /*!< USB_EP DOEPCTL_ISOCONT: EPDis Mask      */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPEna_Pos      31                                                      /*!< USB_EP DOEPCTL_ISOCONT: EPEna Position  */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPEna_Msk      (0x01UL << USB_EP_DOEPCTL_ISOCONT_EPEna_Pos)            /*!< USB_EP DOEPCTL_ISOCONT: EPEna Mask      */\r
+\r
+/* ---------------------------  USB_EP_DOEPCTL_INTBULK  --------------------------- */\r
+#define USB_EP_DOEPCTL_INTBULK_MPS_Pos        0                                                       /*!< USB_EP DOEPCTL_INTBULK: MPS Position    */\r
+#define USB_EP_DOEPCTL_INTBULK_MPS_Msk        (0x000007ffUL << USB_EP_DOEPCTL_INTBULK_MPS_Pos)        /*!< USB_EP DOEPCTL_INTBULK: MPS Mask        */\r
+#define USB_EP_DOEPCTL_INTBULK_USBActEP_Pos   15                                                      /*!< USB_EP DOEPCTL_INTBULK: USBActEP Position */\r
+#define USB_EP_DOEPCTL_INTBULK_USBActEP_Msk   (0x01UL << USB_EP_DOEPCTL_INTBULK_USBActEP_Pos)         /*!< USB_EP DOEPCTL_INTBULK: USBActEP Mask   */\r
+#define USB_EP_DOEPCTL_INTBULK_DPID_Pos       16                                                      /*!< USB_EP DOEPCTL_INTBULK: DPID Position   */\r
+#define USB_EP_DOEPCTL_INTBULK_DPID_Msk       (0x01UL << USB_EP_DOEPCTL_INTBULK_DPID_Pos)             /*!< USB_EP DOEPCTL_INTBULK: DPID Mask       */\r
+#define USB_EP_DOEPCTL_INTBULK_NAKSts_Pos     17                                                      /*!< USB_EP DOEPCTL_INTBULK: NAKSts Position */\r
+#define USB_EP_DOEPCTL_INTBULK_NAKSts_Msk     (0x01UL << USB_EP_DOEPCTL_INTBULK_NAKSts_Pos)           /*!< USB_EP DOEPCTL_INTBULK: NAKSts Mask     */\r
+#define USB_EP_DOEPCTL_INTBULK_EPType_Pos     18                                                      /*!< USB_EP DOEPCTL_INTBULK: EPType Position */\r
+#define USB_EP_DOEPCTL_INTBULK_EPType_Msk     (0x03UL << USB_EP_DOEPCTL_INTBULK_EPType_Pos)           /*!< USB_EP DOEPCTL_INTBULK: EPType Mask     */\r
+#define USB_EP_DOEPCTL_INTBULK_Snp_Pos        20                                                      /*!< USB_EP DOEPCTL_INTBULK: Snp Position    */\r
+#define USB_EP_DOEPCTL_INTBULK_Snp_Msk        (0x01UL << USB_EP_DOEPCTL_INTBULK_Snp_Pos)              /*!< USB_EP DOEPCTL_INTBULK: Snp Mask        */\r
+#define USB_EP_DOEPCTL_INTBULK_Stall_Pos      21                                                      /*!< USB_EP DOEPCTL_INTBULK: Stall Position  */\r
+#define USB_EP_DOEPCTL_INTBULK_Stall_Msk      (0x01UL << USB_EP_DOEPCTL_INTBULK_Stall_Pos)            /*!< USB_EP DOEPCTL_INTBULK: Stall Mask      */\r
+#define USB_EP_DOEPCTL_INTBULK_TxFNum_Pos     22                                                      /*!< USB_EP DOEPCTL_INTBULK: TxFNum Position */\r
+#define USB_EP_DOEPCTL_INTBULK_TxFNum_Msk     (0x0fUL << USB_EP_DOEPCTL_INTBULK_TxFNum_Pos)           /*!< USB_EP DOEPCTL_INTBULK: TxFNum Mask     */\r
+#define USB_EP_DOEPCTL_INTBULK_CNAK_Pos       26                                                      /*!< USB_EP DOEPCTL_INTBULK: CNAK Position   */\r
+#define USB_EP_DOEPCTL_INTBULK_CNAK_Msk       (0x01UL << USB_EP_DOEPCTL_INTBULK_CNAK_Pos)             /*!< USB_EP DOEPCTL_INTBULK: CNAK Mask       */\r
+#define USB_EP_DOEPCTL_INTBULK_SNAK_Pos       27                                                      /*!< USB_EP DOEPCTL_INTBULK: SNAK Position   */\r
+#define USB_EP_DOEPCTL_INTBULK_SNAK_Msk       (0x01UL << USB_EP_DOEPCTL_INTBULK_SNAK_Pos)             /*!< USB_EP DOEPCTL_INTBULK: SNAK Mask       */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos   28                                                      /*!< USB_EP DOEPCTL_INTBULK: SetD0PID Position */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk   (0x01UL << USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos)         /*!< USB_EP DOEPCTL_INTBULK: SetD0PID Mask   */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos   29                                                      /*!< USB_EP DOEPCTL_INTBULK: SetD1PID Position */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk   (0x01UL << USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos)         /*!< USB_EP DOEPCTL_INTBULK: SetD1PID Mask   */\r
+#define USB_EP_DOEPCTL_INTBULK_EPDis_Pos      30                                                      /*!< USB_EP DOEPCTL_INTBULK: EPDis Position  */\r
+#define USB_EP_DOEPCTL_INTBULK_EPDis_Msk      (0x01UL << USB_EP_DOEPCTL_INTBULK_EPDis_Pos)            /*!< USB_EP DOEPCTL_INTBULK: EPDis Mask      */\r
+#define USB_EP_DOEPCTL_INTBULK_EPEna_Pos      31                                                      /*!< USB_EP DOEPCTL_INTBULK: EPEna Position  */\r
+#define USB_EP_DOEPCTL_INTBULK_EPEna_Msk      (0x01UL << USB_EP_DOEPCTL_INTBULK_EPEna_Pos)            /*!< USB_EP DOEPCTL_INTBULK: EPEna Mask      */\r
+\r
+/* -------------------------------  USB_EP_DOEPINT  ------------------------------- */\r
+#define USB_EP_DOEPINT_XferCompl_Pos          0                                                       /*!< USB_EP DOEPINT: XferCompl Position      */\r
+#define USB_EP_DOEPINT_XferCompl_Msk          (0x01UL << USB_EP_DOEPINT_XferCompl_Pos)                /*!< USB_EP DOEPINT: XferCompl Mask          */\r
+#define USB_EP_DOEPINT_EPDisbld_Pos           1                                                       /*!< USB_EP DOEPINT: EPDisbld Position       */\r
+#define USB_EP_DOEPINT_EPDisbld_Msk           (0x01UL << USB_EP_DOEPINT_EPDisbld_Pos)                 /*!< USB_EP DOEPINT: EPDisbld Mask           */\r
+#define USB_EP_DOEPINT_AHBErr_Pos             2                                                       /*!< USB_EP DOEPINT: AHBErr Position         */\r
+#define USB_EP_DOEPINT_AHBErr_Msk             (0x01UL << USB_EP_DOEPINT_AHBErr_Pos)                   /*!< USB_EP DOEPINT: AHBErr Mask             */\r
+#define USB_EP_DOEPINT_SetUp_Pos              3                                                       /*!< USB_EP DOEPINT: SetUp Position          */\r
+#define USB_EP_DOEPINT_SetUp_Msk              (0x01UL << USB_EP_DOEPINT_SetUp_Pos)                    /*!< USB_EP DOEPINT: SetUp Mask              */\r
+#define USB_EP_DOEPINT_OUTTknEPdis_Pos        4                                                       /*!< USB_EP DOEPINT: OUTTknEPdis Position    */\r
+#define USB_EP_DOEPINT_OUTTknEPdis_Msk        (0x01UL << USB_EP_DOEPINT_OUTTknEPdis_Pos)              /*!< USB_EP DOEPINT: OUTTknEPdis Mask        */\r
+#define USB_EP_DOEPINT_StsPhseRcvd_Pos        5                                                       /*!< USB_EP DOEPINT: StsPhseRcvd Position    */\r
+#define USB_EP_DOEPINT_StsPhseRcvd_Msk        (0x01UL << USB_EP_DOEPINT_StsPhseRcvd_Pos)              /*!< USB_EP DOEPINT: StsPhseRcvd Mask        */\r
+#define USB_EP_DOEPINT_Back2BackSETup_Pos     6                                                       /*!< USB_EP DOEPINT: Back2BackSETup Position */\r
+#define USB_EP_DOEPINT_Back2BackSETup_Msk     (0x01UL << USB_EP_DOEPINT_Back2BackSETup_Pos)           /*!< USB_EP DOEPINT: Back2BackSETup Mask     */\r
+#define USB_EP_DOEPINT_BNAIntr_Pos            9                                                       /*!< USB_EP DOEPINT: BNAIntr Position        */\r
+#define USB_EP_DOEPINT_BNAIntr_Msk            (0x01UL << USB_EP_DOEPINT_BNAIntr_Pos)                  /*!< USB_EP DOEPINT: BNAIntr Mask            */\r
+#define USB_EP_DOEPINT_PktDrpSts_Pos          11                                                      /*!< USB_EP DOEPINT: PktDrpSts Position      */\r
+#define USB_EP_DOEPINT_PktDrpSts_Msk          (0x01UL << USB_EP_DOEPINT_PktDrpSts_Pos)                /*!< USB_EP DOEPINT: PktDrpSts Mask          */\r
+#define USB_EP_DOEPINT_BbleErrIntrpt_Pos      12                                                      /*!< USB_EP DOEPINT: BbleErrIntrpt Position  */\r
+#define USB_EP_DOEPINT_BbleErrIntrpt_Msk      (0x01UL << USB_EP_DOEPINT_BbleErrIntrpt_Pos)            /*!< USB_EP DOEPINT: BbleErrIntrpt Mask      */\r
+#define USB_EP_DOEPINT_NAKIntrpt_Pos          13                                                      /*!< USB_EP DOEPINT: NAKIntrpt Position      */\r
+#define USB_EP_DOEPINT_NAKIntrpt_Msk          (0x01UL << USB_EP_DOEPINT_NAKIntrpt_Pos)                /*!< USB_EP DOEPINT: NAKIntrpt Mask          */\r
+#define USB_EP_DOEPINT_NYETIntrpt_Pos         14                                                      /*!< USB_EP DOEPINT: NYETIntrpt Position     */\r
+#define USB_EP_DOEPINT_NYETIntrpt_Msk         (0x01UL << USB_EP_DOEPINT_NYETIntrpt_Pos)               /*!< USB_EP DOEPINT: NYETIntrpt Mask         */\r
+\r
+/* -----------------------------  USB_EP_DOEPTSIZ_ISO  ---------------------------- */\r
+#define USB_EP_DOEPTSIZ_ISO_XferSize_Pos      0                                                       /*!< USB_EP DOEPTSIZ_ISO: XferSize Position  */\r
+#define USB_EP_DOEPTSIZ_ISO_XferSize_Msk      (0x0007ffffUL << USB_EP_DOEPTSIZ_ISO_XferSize_Pos)      /*!< USB_EP DOEPTSIZ_ISO: XferSize Mask      */\r
+#define USB_EP_DOEPTSIZ_ISO_PktCnt_Pos        19                                                      /*!< USB_EP DOEPTSIZ_ISO: PktCnt Position    */\r
+#define USB_EP_DOEPTSIZ_ISO_PktCnt_Msk        (0x000003ffUL << USB_EP_DOEPTSIZ_ISO_PktCnt_Pos)        /*!< USB_EP DOEPTSIZ_ISO: PktCnt Mask        */\r
+#define USB_EP_DOEPTSIZ_ISO_RxDPID_Pos        29                                                      /*!< USB_EP DOEPTSIZ_ISO: RxDPID Position    */\r
+#define USB_EP_DOEPTSIZ_ISO_RxDPID_Msk        (0x03UL << USB_EP_DOEPTSIZ_ISO_RxDPID_Pos)              /*!< USB_EP DOEPTSIZ_ISO: RxDPID Mask        */\r
+\r
+/* ---------------------------  USB_EP_DOEPTSIZ_CONTROL  -------------------------- */\r
+#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos  0                                                       /*!< USB_EP DOEPTSIZ_CONTROL: XferSize Position */\r
+#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk  (0x0007ffffUL << USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos)  /*!< USB_EP DOEPTSIZ_CONTROL: XferSize Mask  */\r
+#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos    19                                                      /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt Position */\r
+#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk    (0x000003ffUL << USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos)    /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt Mask    */\r
+#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos    29                                                      /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt Position */\r
+#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk    (0x03UL << USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos)          /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt Mask    */\r
+\r
+/* -------------------------------  USB_EP_DOEPDMA  ------------------------------- */\r
+#define USB_EP_DOEPDMA_DMAAddr_Pos            0                                                       /*!< USB_EP DOEPDMA: DMAAddr Position        */\r
+#define USB_EP_DOEPDMA_DMAAddr_Msk            (0xffffffffUL << USB_EP_DOEPDMA_DMAAddr_Pos)            /*!< USB_EP DOEPDMA: DMAAddr Mask            */\r
+\r
+/* -------------------------------  USB_EP_DOEPDMAB  ------------------------------ */\r
+#define USB_EP_DOEPDMAB_DMABufferAddr_Pos     0                                                       /*!< USB_EP DOEPDMAB: DMABufferAddr Position */\r
+#define USB_EP_DOEPDMAB_DMABufferAddr_Msk     (0xffffffffUL << USB_EP_DOEPDMAB_DMABufferAddr_Pos)     /*!< USB_EP DOEPDMAB: DMABufferAddr Mask     */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'USIC' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  USIC_ID  ---------------------------------- */\r
+#define USIC_ID_MOD_REV_Pos                   0                                                       /*!< USIC ID: MOD_REV Position               */\r
+#define USIC_ID_MOD_REV_Msk                   (0x000000ffUL << USIC_ID_MOD_REV_Pos)                   /*!< USIC ID: MOD_REV Mask                   */\r
+#define USIC_ID_MOD_TYPE_Pos                  8                                                       /*!< USIC ID: MOD_TYPE Position              */\r
+#define USIC_ID_MOD_TYPE_Msk                  (0x000000ffUL << USIC_ID_MOD_TYPE_Pos)                  /*!< USIC ID: MOD_TYPE Mask                  */\r
+#define USIC_ID_MOD_NUMBER_Pos                16                                                      /*!< USIC ID: MOD_NUMBER Position            */\r
+#define USIC_ID_MOD_NUMBER_Msk                (0x0000ffffUL << USIC_ID_MOD_NUMBER_Pos)                /*!< USIC ID: MOD_NUMBER Mask                */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'USIC_CH' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  USIC_CH_CCFG  -------------------------------- */\r
+#define USIC_CH_CCFG_SSC_Pos                  0                                                       /*!< USIC_CH CCFG: SSC Position              */\r
+#define USIC_CH_CCFG_SSC_Msk                  (0x01UL << USIC_CH_CCFG_SSC_Pos)                        /*!< USIC_CH CCFG: SSC Mask                  */\r
+#define USIC_CH_CCFG_ASC_Pos                  1                                                       /*!< USIC_CH CCFG: ASC Position              */\r
+#define USIC_CH_CCFG_ASC_Msk                  (0x01UL << USIC_CH_CCFG_ASC_Pos)                        /*!< USIC_CH CCFG: ASC Mask                  */\r
+#define USIC_CH_CCFG_IIC_Pos                  2                                                       /*!< USIC_CH CCFG: IIC Position              */\r
+#define USIC_CH_CCFG_IIC_Msk                  (0x01UL << USIC_CH_CCFG_IIC_Pos)                        /*!< USIC_CH CCFG: IIC Mask                  */\r
+#define USIC_CH_CCFG_IIS_Pos                  3                                                       /*!< USIC_CH CCFG: IIS Position              */\r
+#define USIC_CH_CCFG_IIS_Msk                  (0x01UL << USIC_CH_CCFG_IIS_Pos)                        /*!< USIC_CH CCFG: IIS Mask                  */\r
+#define USIC_CH_CCFG_RB_Pos                   6                                                       /*!< USIC_CH CCFG: RB Position               */\r
+#define USIC_CH_CCFG_RB_Msk                   (0x01UL << USIC_CH_CCFG_RB_Pos)                         /*!< USIC_CH CCFG: RB Mask                   */\r
+#define USIC_CH_CCFG_TB_Pos                   7                                                       /*!< USIC_CH CCFG: TB Position               */\r
+#define USIC_CH_CCFG_TB_Msk                   (0x01UL << USIC_CH_CCFG_TB_Pos)                         /*!< USIC_CH CCFG: TB Mask                   */\r
+\r
+/* --------------------------------  USIC_CH_KSCFG  ------------------------------- */\r
+#define USIC_CH_KSCFG_MODEN_Pos               0                                                       /*!< USIC_CH KSCFG: MODEN Position           */\r
+#define USIC_CH_KSCFG_MODEN_Msk               (0x01UL << USIC_CH_KSCFG_MODEN_Pos)                     /*!< USIC_CH KSCFG: MODEN Mask               */\r
+#define USIC_CH_KSCFG_BPMODEN_Pos             1                                                       /*!< USIC_CH KSCFG: BPMODEN Position         */\r
+#define USIC_CH_KSCFG_BPMODEN_Msk             (0x01UL << USIC_CH_KSCFG_BPMODEN_Pos)                   /*!< USIC_CH KSCFG: BPMODEN Mask             */\r
+#define USIC_CH_KSCFG_NOMCFG_Pos              4                                                       /*!< USIC_CH KSCFG: NOMCFG Position          */\r
+#define USIC_CH_KSCFG_NOMCFG_Msk              (0x03UL << USIC_CH_KSCFG_NOMCFG_Pos)                    /*!< USIC_CH KSCFG: NOMCFG Mask              */\r
+#define USIC_CH_KSCFG_BPNOM_Pos               7                                                       /*!< USIC_CH KSCFG: BPNOM Position           */\r
+#define USIC_CH_KSCFG_BPNOM_Msk               (0x01UL << USIC_CH_KSCFG_BPNOM_Pos)                     /*!< USIC_CH KSCFG: BPNOM Mask               */\r
+#define USIC_CH_KSCFG_SUMCFG_Pos              8                                                       /*!< USIC_CH KSCFG: SUMCFG Position          */\r
+#define USIC_CH_KSCFG_SUMCFG_Msk              (0x03UL << USIC_CH_KSCFG_SUMCFG_Pos)                    /*!< USIC_CH KSCFG: SUMCFG Mask              */\r
+#define USIC_CH_KSCFG_BPSUM_Pos               11                                                      /*!< USIC_CH KSCFG: BPSUM Position           */\r
+#define USIC_CH_KSCFG_BPSUM_Msk               (0x01UL << USIC_CH_KSCFG_BPSUM_Pos)                     /*!< USIC_CH KSCFG: BPSUM Mask               */\r
+\r
+/* ---------------------------------  USIC_CH_FDR  -------------------------------- */\r
+#define USIC_CH_FDR_STEP_Pos                  0                                                       /*!< USIC_CH FDR: STEP Position              */\r
+#define USIC_CH_FDR_STEP_Msk                  (0x000003ffUL << USIC_CH_FDR_STEP_Pos)                  /*!< USIC_CH FDR: STEP Mask                  */\r
+#define USIC_CH_FDR_DM_Pos                    14                                                      /*!< USIC_CH FDR: DM Position                */\r
+#define USIC_CH_FDR_DM_Msk                    (0x03UL << USIC_CH_FDR_DM_Pos)                          /*!< USIC_CH FDR: DM Mask                    */\r
+#define USIC_CH_FDR_RESULT_Pos                16                                                      /*!< USIC_CH FDR: RESULT Position            */\r
+#define USIC_CH_FDR_RESULT_Msk                (0x000003ffUL << USIC_CH_FDR_RESULT_Pos)                /*!< USIC_CH FDR: RESULT Mask                */\r
+\r
+/* ---------------------------------  USIC_CH_BRG  -------------------------------- */\r
+#define USIC_CH_BRG_CLKSEL_Pos                0                                                       /*!< USIC_CH BRG: CLKSEL Position            */\r
+#define USIC_CH_BRG_CLKSEL_Msk                (0x03UL << USIC_CH_BRG_CLKSEL_Pos)                      /*!< USIC_CH BRG: CLKSEL Mask                */\r
+#define USIC_CH_BRG_TMEN_Pos                  3                                                       /*!< USIC_CH BRG: TMEN Position              */\r
+#define USIC_CH_BRG_TMEN_Msk                  (0x01UL << USIC_CH_BRG_TMEN_Pos)                        /*!< USIC_CH BRG: TMEN Mask                  */\r
+#define USIC_CH_BRG_PPPEN_Pos                 4                                                       /*!< USIC_CH BRG: PPPEN Position             */\r
+#define USIC_CH_BRG_PPPEN_Msk                 (0x01UL << USIC_CH_BRG_PPPEN_Pos)                       /*!< USIC_CH BRG: PPPEN Mask                 */\r
+#define USIC_CH_BRG_CTQSEL_Pos                6                                                       /*!< USIC_CH BRG: CTQSEL Position            */\r
+#define USIC_CH_BRG_CTQSEL_Msk                (0x03UL << USIC_CH_BRG_CTQSEL_Pos)                      /*!< USIC_CH BRG: CTQSEL Mask                */\r
+#define USIC_CH_BRG_PCTQ_Pos                  8                                                       /*!< USIC_CH BRG: PCTQ Position              */\r
+#define USIC_CH_BRG_PCTQ_Msk                  (0x03UL << USIC_CH_BRG_PCTQ_Pos)                        /*!< USIC_CH BRG: PCTQ Mask                  */\r
+#define USIC_CH_BRG_DCTQ_Pos                  10                                                      /*!< USIC_CH BRG: DCTQ Position              */\r
+#define USIC_CH_BRG_DCTQ_Msk                  (0x1fUL << USIC_CH_BRG_DCTQ_Pos)                        /*!< USIC_CH BRG: DCTQ Mask                  */\r
+#define USIC_CH_BRG_PDIV_Pos                  16                                                      /*!< USIC_CH BRG: PDIV Position              */\r
+#define USIC_CH_BRG_PDIV_Msk                  (0x000003ffUL << USIC_CH_BRG_PDIV_Pos)                  /*!< USIC_CH BRG: PDIV Mask                  */\r
+#define USIC_CH_BRG_SCLKOSEL_Pos              28                                                      /*!< USIC_CH BRG: SCLKOSEL Position          */\r
+#define USIC_CH_BRG_SCLKOSEL_Msk              (0x01UL << USIC_CH_BRG_SCLKOSEL_Pos)                    /*!< USIC_CH BRG: SCLKOSEL Mask              */\r
+#define USIC_CH_BRG_MCLKCFG_Pos               29                                                      /*!< USIC_CH BRG: MCLKCFG Position           */\r
+#define USIC_CH_BRG_MCLKCFG_Msk               (0x01UL << USIC_CH_BRG_MCLKCFG_Pos)                     /*!< USIC_CH BRG: MCLKCFG Mask               */\r
+#define USIC_CH_BRG_SCLKCFG_Pos               30                                                      /*!< USIC_CH BRG: SCLKCFG Position           */\r
+#define USIC_CH_BRG_SCLKCFG_Msk               (0x03UL << USIC_CH_BRG_SCLKCFG_Pos)                     /*!< USIC_CH BRG: SCLKCFG Mask               */\r
+\r
+/* --------------------------------  USIC_CH_INPR  -------------------------------- */\r
+#define USIC_CH_INPR_TSINP_Pos                0                                                       /*!< USIC_CH INPR: TSINP Position            */\r
+#define USIC_CH_INPR_TSINP_Msk                (0x07UL << USIC_CH_INPR_TSINP_Pos)                      /*!< USIC_CH INPR: TSINP Mask                */\r
+#define USIC_CH_INPR_TBINP_Pos                4                                                       /*!< USIC_CH INPR: TBINP Position            */\r
+#define USIC_CH_INPR_TBINP_Msk                (0x07UL << USIC_CH_INPR_TBINP_Pos)                      /*!< USIC_CH INPR: TBINP Mask                */\r
+#define USIC_CH_INPR_RINP_Pos                 8                                                       /*!< USIC_CH INPR: RINP Position             */\r
+#define USIC_CH_INPR_RINP_Msk                 (0x07UL << USIC_CH_INPR_RINP_Pos)                       /*!< USIC_CH INPR: RINP Mask                 */\r
+#define USIC_CH_INPR_AINP_Pos                 12                                                      /*!< USIC_CH INPR: AINP Position             */\r
+#define USIC_CH_INPR_AINP_Msk                 (0x07UL << USIC_CH_INPR_AINP_Pos)                       /*!< USIC_CH INPR: AINP Mask                 */\r
+#define USIC_CH_INPR_PINP_Pos                 16                                                      /*!< USIC_CH INPR: PINP Position             */\r
+#define USIC_CH_INPR_PINP_Msk                 (0x07UL << USIC_CH_INPR_PINP_Pos)                       /*!< USIC_CH INPR: PINP Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX0CR  ------------------------------- */\r
+#define USIC_CH_DX0CR_DSEL_Pos                0                                                       /*!< USIC_CH DX0CR: DSEL Position            */\r
+#define USIC_CH_DX0CR_DSEL_Msk                (0x07UL << USIC_CH_DX0CR_DSEL_Pos)                      /*!< USIC_CH DX0CR: DSEL Mask                */\r
+#define USIC_CH_DX0CR_INSW_Pos                4                                                       /*!< USIC_CH DX0CR: INSW Position            */\r
+#define USIC_CH_DX0CR_INSW_Msk                (0x01UL << USIC_CH_DX0CR_INSW_Pos)                      /*!< USIC_CH DX0CR: INSW Mask                */\r
+#define USIC_CH_DX0CR_DFEN_Pos                5                                                       /*!< USIC_CH DX0CR: DFEN Position            */\r
+#define USIC_CH_DX0CR_DFEN_Msk                (0x01UL << USIC_CH_DX0CR_DFEN_Pos)                      /*!< USIC_CH DX0CR: DFEN Mask                */\r
+#define USIC_CH_DX0CR_DSEN_Pos                6                                                       /*!< USIC_CH DX0CR: DSEN Position            */\r
+#define USIC_CH_DX0CR_DSEN_Msk                (0x01UL << USIC_CH_DX0CR_DSEN_Pos)                      /*!< USIC_CH DX0CR: DSEN Mask                */\r
+#define USIC_CH_DX0CR_DPOL_Pos                8                                                       /*!< USIC_CH DX0CR: DPOL Position            */\r
+#define USIC_CH_DX0CR_DPOL_Msk                (0x01UL << USIC_CH_DX0CR_DPOL_Pos)                      /*!< USIC_CH DX0CR: DPOL Mask                */\r
+#define USIC_CH_DX0CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX0CR: SFSEL Position           */\r
+#define USIC_CH_DX0CR_SFSEL_Msk               (0x01UL << USIC_CH_DX0CR_SFSEL_Pos)                     /*!< USIC_CH DX0CR: SFSEL Mask               */\r
+#define USIC_CH_DX0CR_CM_Pos                  10                                                      /*!< USIC_CH DX0CR: CM Position              */\r
+#define USIC_CH_DX0CR_CM_Msk                  (0x03UL << USIC_CH_DX0CR_CM_Pos)                        /*!< USIC_CH DX0CR: CM Mask                  */\r
+#define USIC_CH_DX0CR_DXS_Pos                 15                                                      /*!< USIC_CH DX0CR: DXS Position             */\r
+#define USIC_CH_DX0CR_DXS_Msk                 (0x01UL << USIC_CH_DX0CR_DXS_Pos)                       /*!< USIC_CH DX0CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX1CR  ------------------------------- */\r
+#define USIC_CH_DX1CR_DSEL_Pos                0                                                       /*!< USIC_CH DX1CR: DSEL Position            */\r
+#define USIC_CH_DX1CR_DSEL_Msk                (0x07UL << USIC_CH_DX1CR_DSEL_Pos)                      /*!< USIC_CH DX1CR: DSEL Mask                */\r
+#define USIC_CH_DX1CR_DCEN_Pos                3                                                       /*!< USIC_CH DX1CR: DCEN Position            */\r
+#define USIC_CH_DX1CR_DCEN_Msk                (0x01UL << USIC_CH_DX1CR_DCEN_Pos)                      /*!< USIC_CH DX1CR: DCEN Mask                */\r
+#define USIC_CH_DX1CR_INSW_Pos                4                                                       /*!< USIC_CH DX1CR: INSW Position            */\r
+#define USIC_CH_DX1CR_INSW_Msk                (0x01UL << USIC_CH_DX1CR_INSW_Pos)                      /*!< USIC_CH DX1CR: INSW Mask                */\r
+#define USIC_CH_DX1CR_DFEN_Pos                5                                                       /*!< USIC_CH DX1CR: DFEN Position            */\r
+#define USIC_CH_DX1CR_DFEN_Msk                (0x01UL << USIC_CH_DX1CR_DFEN_Pos)                      /*!< USIC_CH DX1CR: DFEN Mask                */\r
+#define USIC_CH_DX1CR_DSEN_Pos                6                                                       /*!< USIC_CH DX1CR: DSEN Position            */\r
+#define USIC_CH_DX1CR_DSEN_Msk                (0x01UL << USIC_CH_DX1CR_DSEN_Pos)                      /*!< USIC_CH DX1CR: DSEN Mask                */\r
+#define USIC_CH_DX1CR_DPOL_Pos                8                                                       /*!< USIC_CH DX1CR: DPOL Position            */\r
+#define USIC_CH_DX1CR_DPOL_Msk                (0x01UL << USIC_CH_DX1CR_DPOL_Pos)                      /*!< USIC_CH DX1CR: DPOL Mask                */\r
+#define USIC_CH_DX1CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX1CR: SFSEL Position           */\r
+#define USIC_CH_DX1CR_SFSEL_Msk               (0x01UL << USIC_CH_DX1CR_SFSEL_Pos)                     /*!< USIC_CH DX1CR: SFSEL Mask               */\r
+#define USIC_CH_DX1CR_CM_Pos                  10                                                      /*!< USIC_CH DX1CR: CM Position              */\r
+#define USIC_CH_DX1CR_CM_Msk                  (0x03UL << USIC_CH_DX1CR_CM_Pos)                        /*!< USIC_CH DX1CR: CM Mask                  */\r
+#define USIC_CH_DX1CR_DXS_Pos                 15                                                      /*!< USIC_CH DX1CR: DXS Position             */\r
+#define USIC_CH_DX1CR_DXS_Msk                 (0x01UL << USIC_CH_DX1CR_DXS_Pos)                       /*!< USIC_CH DX1CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX2CR  ------------------------------- */\r
+#define USIC_CH_DX2CR_DSEL_Pos                0                                                       /*!< USIC_CH DX2CR: DSEL Position            */\r
+#define USIC_CH_DX2CR_DSEL_Msk                (0x07UL << USIC_CH_DX2CR_DSEL_Pos)                      /*!< USIC_CH DX2CR: DSEL Mask                */\r
+#define USIC_CH_DX2CR_INSW_Pos                4                                                       /*!< USIC_CH DX2CR: INSW Position            */\r
+#define USIC_CH_DX2CR_INSW_Msk                (0x01UL << USIC_CH_DX2CR_INSW_Pos)                      /*!< USIC_CH DX2CR: INSW Mask                */\r
+#define USIC_CH_DX2CR_DFEN_Pos                5                                                       /*!< USIC_CH DX2CR: DFEN Position            */\r
+#define USIC_CH_DX2CR_DFEN_Msk                (0x01UL << USIC_CH_DX2CR_DFEN_Pos)                      /*!< USIC_CH DX2CR: DFEN Mask                */\r
+#define USIC_CH_DX2CR_DSEN_Pos                6                                                       /*!< USIC_CH DX2CR: DSEN Position            */\r
+#define USIC_CH_DX2CR_DSEN_Msk                (0x01UL << USIC_CH_DX2CR_DSEN_Pos)                      /*!< USIC_CH DX2CR: DSEN Mask                */\r
+#define USIC_CH_DX2CR_DPOL_Pos                8                                                       /*!< USIC_CH DX2CR: DPOL Position            */\r
+#define USIC_CH_DX2CR_DPOL_Msk                (0x01UL << USIC_CH_DX2CR_DPOL_Pos)                      /*!< USIC_CH DX2CR: DPOL Mask                */\r
+#define USIC_CH_DX2CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX2CR: SFSEL Position           */\r
+#define USIC_CH_DX2CR_SFSEL_Msk               (0x01UL << USIC_CH_DX2CR_SFSEL_Pos)                     /*!< USIC_CH DX2CR: SFSEL Mask               */\r
+#define USIC_CH_DX2CR_CM_Pos                  10                                                      /*!< USIC_CH DX2CR: CM Position              */\r
+#define USIC_CH_DX2CR_CM_Msk                  (0x03UL << USIC_CH_DX2CR_CM_Pos)                        /*!< USIC_CH DX2CR: CM Mask                  */\r
+#define USIC_CH_DX2CR_DXS_Pos                 15                                                      /*!< USIC_CH DX2CR: DXS Position             */\r
+#define USIC_CH_DX2CR_DXS_Msk                 (0x01UL << USIC_CH_DX2CR_DXS_Pos)                       /*!< USIC_CH DX2CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX3CR  ------------------------------- */\r
+#define USIC_CH_DX3CR_DSEL_Pos                0                                                       /*!< USIC_CH DX3CR: DSEL Position            */\r
+#define USIC_CH_DX3CR_DSEL_Msk                (0x07UL << USIC_CH_DX3CR_DSEL_Pos)                      /*!< USIC_CH DX3CR: DSEL Mask                */\r
+#define USIC_CH_DX3CR_INSW_Pos                4                                                       /*!< USIC_CH DX3CR: INSW Position            */\r
+#define USIC_CH_DX3CR_INSW_Msk                (0x01UL << USIC_CH_DX3CR_INSW_Pos)                      /*!< USIC_CH DX3CR: INSW Mask                */\r
+#define USIC_CH_DX3CR_DFEN_Pos                5                                                       /*!< USIC_CH DX3CR: DFEN Position            */\r
+#define USIC_CH_DX3CR_DFEN_Msk                (0x01UL << USIC_CH_DX3CR_DFEN_Pos)                      /*!< USIC_CH DX3CR: DFEN Mask                */\r
+#define USIC_CH_DX3CR_DSEN_Pos                6                                                       /*!< USIC_CH DX3CR: DSEN Position            */\r
+#define USIC_CH_DX3CR_DSEN_Msk                (0x01UL << USIC_CH_DX3CR_DSEN_Pos)                      /*!< USIC_CH DX3CR: DSEN Mask                */\r
+#define USIC_CH_DX3CR_DPOL_Pos                8                                                       /*!< USIC_CH DX3CR: DPOL Position            */\r
+#define USIC_CH_DX3CR_DPOL_Msk                (0x01UL << USIC_CH_DX3CR_DPOL_Pos)                      /*!< USIC_CH DX3CR: DPOL Mask                */\r
+#define USIC_CH_DX3CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX3CR: SFSEL Position           */\r
+#define USIC_CH_DX3CR_SFSEL_Msk               (0x01UL << USIC_CH_DX3CR_SFSEL_Pos)                     /*!< USIC_CH DX3CR: SFSEL Mask               */\r
+#define USIC_CH_DX3CR_CM_Pos                  10                                                      /*!< USIC_CH DX3CR: CM Position              */\r
+#define USIC_CH_DX3CR_CM_Msk                  (0x03UL << USIC_CH_DX3CR_CM_Pos)                        /*!< USIC_CH DX3CR: CM Mask                  */\r
+#define USIC_CH_DX3CR_DXS_Pos                 15                                                      /*!< USIC_CH DX3CR: DXS Position             */\r
+#define USIC_CH_DX3CR_DXS_Msk                 (0x01UL << USIC_CH_DX3CR_DXS_Pos)                       /*!< USIC_CH DX3CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX4CR  ------------------------------- */\r
+#define USIC_CH_DX4CR_DSEL_Pos                0                                                       /*!< USIC_CH DX4CR: DSEL Position            */\r
+#define USIC_CH_DX4CR_DSEL_Msk                (0x07UL << USIC_CH_DX4CR_DSEL_Pos)                      /*!< USIC_CH DX4CR: DSEL Mask                */\r
+#define USIC_CH_DX4CR_INSW_Pos                4                                                       /*!< USIC_CH DX4CR: INSW Position            */\r
+#define USIC_CH_DX4CR_INSW_Msk                (0x01UL << USIC_CH_DX4CR_INSW_Pos)                      /*!< USIC_CH DX4CR: INSW Mask                */\r
+#define USIC_CH_DX4CR_DFEN_Pos                5                                                       /*!< USIC_CH DX4CR: DFEN Position            */\r
+#define USIC_CH_DX4CR_DFEN_Msk                (0x01UL << USIC_CH_DX4CR_DFEN_Pos)                      /*!< USIC_CH DX4CR: DFEN Mask                */\r
+#define USIC_CH_DX4CR_DSEN_Pos                6                                                       /*!< USIC_CH DX4CR: DSEN Position            */\r
+#define USIC_CH_DX4CR_DSEN_Msk                (0x01UL << USIC_CH_DX4CR_DSEN_Pos)                      /*!< USIC_CH DX4CR: DSEN Mask                */\r
+#define USIC_CH_DX4CR_DPOL_Pos                8                                                       /*!< USIC_CH DX4CR: DPOL Position            */\r
+#define USIC_CH_DX4CR_DPOL_Msk                (0x01UL << USIC_CH_DX4CR_DPOL_Pos)                      /*!< USIC_CH DX4CR: DPOL Mask                */\r
+#define USIC_CH_DX4CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX4CR: SFSEL Position           */\r
+#define USIC_CH_DX4CR_SFSEL_Msk               (0x01UL << USIC_CH_DX4CR_SFSEL_Pos)                     /*!< USIC_CH DX4CR: SFSEL Mask               */\r
+#define USIC_CH_DX4CR_CM_Pos                  10                                                      /*!< USIC_CH DX4CR: CM Position              */\r
+#define USIC_CH_DX4CR_CM_Msk                  (0x03UL << USIC_CH_DX4CR_CM_Pos)                        /*!< USIC_CH DX4CR: CM Mask                  */\r
+#define USIC_CH_DX4CR_DXS_Pos                 15                                                      /*!< USIC_CH DX4CR: DXS Position             */\r
+#define USIC_CH_DX4CR_DXS_Msk                 (0x01UL << USIC_CH_DX4CR_DXS_Pos)                       /*!< USIC_CH DX4CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX5CR  ------------------------------- */\r
+#define USIC_CH_DX5CR_DSEL_Pos                0                                                       /*!< USIC_CH DX5CR: DSEL Position            */\r
+#define USIC_CH_DX5CR_DSEL_Msk                (0x07UL << USIC_CH_DX5CR_DSEL_Pos)                      /*!< USIC_CH DX5CR: DSEL Mask                */\r
+#define USIC_CH_DX5CR_INSW_Pos                4                                                       /*!< USIC_CH DX5CR: INSW Position            */\r
+#define USIC_CH_DX5CR_INSW_Msk                (0x01UL << USIC_CH_DX5CR_INSW_Pos)                      /*!< USIC_CH DX5CR: INSW Mask                */\r
+#define USIC_CH_DX5CR_DFEN_Pos                5                                                       /*!< USIC_CH DX5CR: DFEN Position            */\r
+#define USIC_CH_DX5CR_DFEN_Msk                (0x01UL << USIC_CH_DX5CR_DFEN_Pos)                      /*!< USIC_CH DX5CR: DFEN Mask                */\r
+#define USIC_CH_DX5CR_DSEN_Pos                6                                                       /*!< USIC_CH DX5CR: DSEN Position            */\r
+#define USIC_CH_DX5CR_DSEN_Msk                (0x01UL << USIC_CH_DX5CR_DSEN_Pos)                      /*!< USIC_CH DX5CR: DSEN Mask                */\r
+#define USIC_CH_DX5CR_DPOL_Pos                8                                                       /*!< USIC_CH DX5CR: DPOL Position            */\r
+#define USIC_CH_DX5CR_DPOL_Msk                (0x01UL << USIC_CH_DX5CR_DPOL_Pos)                      /*!< USIC_CH DX5CR: DPOL Mask                */\r
+#define USIC_CH_DX5CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX5CR: SFSEL Position           */\r
+#define USIC_CH_DX5CR_SFSEL_Msk               (0x01UL << USIC_CH_DX5CR_SFSEL_Pos)                     /*!< USIC_CH DX5CR: SFSEL Mask               */\r
+#define USIC_CH_DX5CR_CM_Pos                  10                                                      /*!< USIC_CH DX5CR: CM Position              */\r
+#define USIC_CH_DX5CR_CM_Msk                  (0x03UL << USIC_CH_DX5CR_CM_Pos)                        /*!< USIC_CH DX5CR: CM Mask                  */\r
+#define USIC_CH_DX5CR_DXS_Pos                 15                                                      /*!< USIC_CH DX5CR: DXS Position             */\r
+#define USIC_CH_DX5CR_DXS_Msk                 (0x01UL << USIC_CH_DX5CR_DXS_Pos)                       /*!< USIC_CH DX5CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_SCTR  -------------------------------- */\r
+#define USIC_CH_SCTR_SDIR_Pos                 0                                                       /*!< USIC_CH SCTR: SDIR Position             */\r
+#define USIC_CH_SCTR_SDIR_Msk                 (0x01UL << USIC_CH_SCTR_SDIR_Pos)                       /*!< USIC_CH SCTR: SDIR Mask                 */\r
+#define USIC_CH_SCTR_PDL_Pos                  1                                                       /*!< USIC_CH SCTR: PDL Position              */\r
+#define USIC_CH_SCTR_PDL_Msk                  (0x01UL << USIC_CH_SCTR_PDL_Pos)                        /*!< USIC_CH SCTR: PDL Mask                  */\r
+#define USIC_CH_SCTR_DSM_Pos                  2                                                       /*!< USIC_CH SCTR: DSM Position              */\r
+#define USIC_CH_SCTR_DSM_Msk                  (0x03UL << USIC_CH_SCTR_DSM_Pos)                        /*!< USIC_CH SCTR: DSM Mask                  */\r
+#define USIC_CH_SCTR_HPCDIR_Pos               4                                                       /*!< USIC_CH SCTR: HPCDIR Position           */\r
+#define USIC_CH_SCTR_HPCDIR_Msk               (0x01UL << USIC_CH_SCTR_HPCDIR_Pos)                     /*!< USIC_CH SCTR: HPCDIR Mask               */\r
+#define USIC_CH_SCTR_DOCFG_Pos                6                                                       /*!< USIC_CH SCTR: DOCFG Position            */\r
+#define USIC_CH_SCTR_DOCFG_Msk                (0x03UL << USIC_CH_SCTR_DOCFG_Pos)                      /*!< USIC_CH SCTR: DOCFG Mask                */\r
+#define USIC_CH_SCTR_TRM_Pos                  8                                                       /*!< USIC_CH SCTR: TRM Position              */\r
+#define USIC_CH_SCTR_TRM_Msk                  (0x03UL << USIC_CH_SCTR_TRM_Pos)                        /*!< USIC_CH SCTR: TRM Mask                  */\r
+#define USIC_CH_SCTR_FLE_Pos                  16                                                      /*!< USIC_CH SCTR: FLE Position              */\r
+#define USIC_CH_SCTR_FLE_Msk                  (0x3fUL << USIC_CH_SCTR_FLE_Pos)                        /*!< USIC_CH SCTR: FLE Mask                  */\r
+#define USIC_CH_SCTR_WLE_Pos                  24                                                      /*!< USIC_CH SCTR: WLE Position              */\r
+#define USIC_CH_SCTR_WLE_Msk                  (0x0fUL << USIC_CH_SCTR_WLE_Pos)                        /*!< USIC_CH SCTR: WLE Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_TCSR  -------------------------------- */\r
+#define USIC_CH_TCSR_WLEMD_Pos                0                                                       /*!< USIC_CH TCSR: WLEMD Position            */\r
+#define USIC_CH_TCSR_WLEMD_Msk                (0x01UL << USIC_CH_TCSR_WLEMD_Pos)                      /*!< USIC_CH TCSR: WLEMD Mask                */\r
+#define USIC_CH_TCSR_SELMD_Pos                1                                                       /*!< USIC_CH TCSR: SELMD Position            */\r
+#define USIC_CH_TCSR_SELMD_Msk                (0x01UL << USIC_CH_TCSR_SELMD_Pos)                      /*!< USIC_CH TCSR: SELMD Mask                */\r
+#define USIC_CH_TCSR_FLEMD_Pos                2                                                       /*!< USIC_CH TCSR: FLEMD Position            */\r
+#define USIC_CH_TCSR_FLEMD_Msk                (0x01UL << USIC_CH_TCSR_FLEMD_Pos)                      /*!< USIC_CH TCSR: FLEMD Mask                */\r
+#define USIC_CH_TCSR_WAMD_Pos                 3                                                       /*!< USIC_CH TCSR: WAMD Position             */\r
+#define USIC_CH_TCSR_WAMD_Msk                 (0x01UL << USIC_CH_TCSR_WAMD_Pos)                       /*!< USIC_CH TCSR: WAMD Mask                 */\r
+#define USIC_CH_TCSR_HPCMD_Pos                4                                                       /*!< USIC_CH TCSR: HPCMD Position            */\r
+#define USIC_CH_TCSR_HPCMD_Msk                (0x01UL << USIC_CH_TCSR_HPCMD_Pos)                      /*!< USIC_CH TCSR: HPCMD Mask                */\r
+#define USIC_CH_TCSR_SOF_Pos                  5                                                       /*!< USIC_CH TCSR: SOF Position              */\r
+#define USIC_CH_TCSR_SOF_Msk                  (0x01UL << USIC_CH_TCSR_SOF_Pos)                        /*!< USIC_CH TCSR: SOF Mask                  */\r
+#define USIC_CH_TCSR_EOF_Pos                  6                                                       /*!< USIC_CH TCSR: EOF Position              */\r
+#define USIC_CH_TCSR_EOF_Msk                  (0x01UL << USIC_CH_TCSR_EOF_Pos)                        /*!< USIC_CH TCSR: EOF Mask                  */\r
+#define USIC_CH_TCSR_TDV_Pos                  7                                                       /*!< USIC_CH TCSR: TDV Position              */\r
+#define USIC_CH_TCSR_TDV_Msk                  (0x01UL << USIC_CH_TCSR_TDV_Pos)                        /*!< USIC_CH TCSR: TDV Mask                  */\r
+#define USIC_CH_TCSR_TDSSM_Pos                8                                                       /*!< USIC_CH TCSR: TDSSM Position            */\r
+#define USIC_CH_TCSR_TDSSM_Msk                (0x01UL << USIC_CH_TCSR_TDSSM_Pos)                      /*!< USIC_CH TCSR: TDSSM Mask                */\r
+#define USIC_CH_TCSR_TDEN_Pos                 10                                                      /*!< USIC_CH TCSR: TDEN Position             */\r
+#define USIC_CH_TCSR_TDEN_Msk                 (0x03UL << USIC_CH_TCSR_TDEN_Pos)                       /*!< USIC_CH TCSR: TDEN Mask                 */\r
+#define USIC_CH_TCSR_TDVTR_Pos                12                                                      /*!< USIC_CH TCSR: TDVTR Position            */\r
+#define USIC_CH_TCSR_TDVTR_Msk                (0x01UL << USIC_CH_TCSR_TDVTR_Pos)                      /*!< USIC_CH TCSR: TDVTR Mask                */\r
+#define USIC_CH_TCSR_WA_Pos                   13                                                      /*!< USIC_CH TCSR: WA Position               */\r
+#define USIC_CH_TCSR_WA_Msk                   (0x01UL << USIC_CH_TCSR_WA_Pos)                         /*!< USIC_CH TCSR: WA Mask                   */\r
+#define USIC_CH_TCSR_TSOF_Pos                 24                                                      /*!< USIC_CH TCSR: TSOF Position             */\r
+#define USIC_CH_TCSR_TSOF_Msk                 (0x01UL << USIC_CH_TCSR_TSOF_Pos)                       /*!< USIC_CH TCSR: TSOF Mask                 */\r
+#define USIC_CH_TCSR_TV_Pos                   26                                                      /*!< USIC_CH TCSR: TV Position               */\r
+#define USIC_CH_TCSR_TV_Msk                   (0x01UL << USIC_CH_TCSR_TV_Pos)                         /*!< USIC_CH TCSR: TV Mask                   */\r
+#define USIC_CH_TCSR_TVC_Pos                  27                                                      /*!< USIC_CH TCSR: TVC Position              */\r
+#define USIC_CH_TCSR_TVC_Msk                  (0x01UL << USIC_CH_TCSR_TVC_Pos)                        /*!< USIC_CH TCSR: TVC Mask                  */\r
+#define USIC_CH_TCSR_TE_Pos                   28                                                      /*!< USIC_CH TCSR: TE Position               */\r
+#define USIC_CH_TCSR_TE_Msk                   (0x01UL << USIC_CH_TCSR_TE_Pos)                         /*!< USIC_CH TCSR: TE Mask                   */\r
+\r
+/* ---------------------------------  USIC_CH_PCR  -------------------------------- */\r
+#define USIC_CH_PCR_CTR0_Pos                  0                                                       /*!< USIC_CH PCR: CTR0 Position              */\r
+#define USIC_CH_PCR_CTR0_Msk                  (0x01UL << USIC_CH_PCR_CTR0_Pos)                        /*!< USIC_CH PCR: CTR0 Mask                  */\r
+#define USIC_CH_PCR_CTR1_Pos                  1                                                       /*!< USIC_CH PCR: CTR1 Position              */\r
+#define USIC_CH_PCR_CTR1_Msk                  (0x01UL << USIC_CH_PCR_CTR1_Pos)                        /*!< USIC_CH PCR: CTR1 Mask                  */\r
+#define USIC_CH_PCR_CTR2_Pos                  2                                                       /*!< USIC_CH PCR: CTR2 Position              */\r
+#define USIC_CH_PCR_CTR2_Msk                  (0x01UL << USIC_CH_PCR_CTR2_Pos)                        /*!< USIC_CH PCR: CTR2 Mask                  */\r
+#define USIC_CH_PCR_CTR3_Pos                  3                                                       /*!< USIC_CH PCR: CTR3 Position              */\r
+#define USIC_CH_PCR_CTR3_Msk                  (0x01UL << USIC_CH_PCR_CTR3_Pos)                        /*!< USIC_CH PCR: CTR3 Mask                  */\r
+#define USIC_CH_PCR_CTR4_Pos                  4                                                       /*!< USIC_CH PCR: CTR4 Position              */\r
+#define USIC_CH_PCR_CTR4_Msk                  (0x01UL << USIC_CH_PCR_CTR4_Pos)                        /*!< USIC_CH PCR: CTR4 Mask                  */\r
+#define USIC_CH_PCR_CTR5_Pos                  5                                                       /*!< USIC_CH PCR: CTR5 Position              */\r
+#define USIC_CH_PCR_CTR5_Msk                  (0x01UL << USIC_CH_PCR_CTR5_Pos)                        /*!< USIC_CH PCR: CTR5 Mask                  */\r
+#define USIC_CH_PCR_CTR6_Pos                  6                                                       /*!< USIC_CH PCR: CTR6 Position              */\r
+#define USIC_CH_PCR_CTR6_Msk                  (0x01UL << USIC_CH_PCR_CTR6_Pos)                        /*!< USIC_CH PCR: CTR6 Mask                  */\r
+#define USIC_CH_PCR_CTR7_Pos                  7                                                       /*!< USIC_CH PCR: CTR7 Position              */\r
+#define USIC_CH_PCR_CTR7_Msk                  (0x01UL << USIC_CH_PCR_CTR7_Pos)                        /*!< USIC_CH PCR: CTR7 Mask                  */\r
+#define USIC_CH_PCR_CTR8_Pos                  8                                                       /*!< USIC_CH PCR: CTR8 Position              */\r
+#define USIC_CH_PCR_CTR8_Msk                  (0x01UL << USIC_CH_PCR_CTR8_Pos)                        /*!< USIC_CH PCR: CTR8 Mask                  */\r
+#define USIC_CH_PCR_CTR9_Pos                  9                                                       /*!< USIC_CH PCR: CTR9 Position              */\r
+#define USIC_CH_PCR_CTR9_Msk                  (0x01UL << USIC_CH_PCR_CTR9_Pos)                        /*!< USIC_CH PCR: CTR9 Mask                  */\r
+#define USIC_CH_PCR_CTR10_Pos                 10                                                      /*!< USIC_CH PCR: CTR10 Position             */\r
+#define USIC_CH_PCR_CTR10_Msk                 (0x01UL << USIC_CH_PCR_CTR10_Pos)                       /*!< USIC_CH PCR: CTR10 Mask                 */\r
+#define USIC_CH_PCR_CTR11_Pos                 11                                                      /*!< USIC_CH PCR: CTR11 Position             */\r
+#define USIC_CH_PCR_CTR11_Msk                 (0x01UL << USIC_CH_PCR_CTR11_Pos)                       /*!< USIC_CH PCR: CTR11 Mask                 */\r
+#define USIC_CH_PCR_CTR12_Pos                 12                                                      /*!< USIC_CH PCR: CTR12 Position             */\r
+#define USIC_CH_PCR_CTR12_Msk                 (0x01UL << USIC_CH_PCR_CTR12_Pos)                       /*!< USIC_CH PCR: CTR12 Mask                 */\r
+#define USIC_CH_PCR_CTR13_Pos                 13                                                      /*!< USIC_CH PCR: CTR13 Position             */\r
+#define USIC_CH_PCR_CTR13_Msk                 (0x01UL << USIC_CH_PCR_CTR13_Pos)                       /*!< USIC_CH PCR: CTR13 Mask                 */\r
+#define USIC_CH_PCR_CTR14_Pos                 14                                                      /*!< USIC_CH PCR: CTR14 Position             */\r
+#define USIC_CH_PCR_CTR14_Msk                 (0x01UL << USIC_CH_PCR_CTR14_Pos)                       /*!< USIC_CH PCR: CTR14 Mask                 */\r
+#define USIC_CH_PCR_CTR15_Pos                 15                                                      /*!< USIC_CH PCR: CTR15 Position             */\r
+#define USIC_CH_PCR_CTR15_Msk                 (0x01UL << USIC_CH_PCR_CTR15_Pos)                       /*!< USIC_CH PCR: CTR15 Mask                 */\r
+#define USIC_CH_PCR_CTR16_Pos                 16                                                      /*!< USIC_CH PCR: CTR16 Position             */\r
+#define USIC_CH_PCR_CTR16_Msk                 (0x01UL << USIC_CH_PCR_CTR16_Pos)                       /*!< USIC_CH PCR: CTR16 Mask                 */\r
+#define USIC_CH_PCR_CTR17_Pos                 17                                                      /*!< USIC_CH PCR: CTR17 Position             */\r
+#define USIC_CH_PCR_CTR17_Msk                 (0x01UL << USIC_CH_PCR_CTR17_Pos)                       /*!< USIC_CH PCR: CTR17 Mask                 */\r
+#define USIC_CH_PCR_CTR18_Pos                 18                                                      /*!< USIC_CH PCR: CTR18 Position             */\r
+#define USIC_CH_PCR_CTR18_Msk                 (0x01UL << USIC_CH_PCR_CTR18_Pos)                       /*!< USIC_CH PCR: CTR18 Mask                 */\r
+#define USIC_CH_PCR_CTR19_Pos                 19                                                      /*!< USIC_CH PCR: CTR19 Position             */\r
+#define USIC_CH_PCR_CTR19_Msk                 (0x01UL << USIC_CH_PCR_CTR19_Pos)                       /*!< USIC_CH PCR: CTR19 Mask                 */\r
+#define USIC_CH_PCR_CTR20_Pos                 20                                                      /*!< USIC_CH PCR: CTR20 Position             */\r
+#define USIC_CH_PCR_CTR20_Msk                 (0x01UL << USIC_CH_PCR_CTR20_Pos)                       /*!< USIC_CH PCR: CTR20 Mask                 */\r
+#define USIC_CH_PCR_CTR21_Pos                 21                                                      /*!< USIC_CH PCR: CTR21 Position             */\r
+#define USIC_CH_PCR_CTR21_Msk                 (0x01UL << USIC_CH_PCR_CTR21_Pos)                       /*!< USIC_CH PCR: CTR21 Mask                 */\r
+#define USIC_CH_PCR_CTR22_Pos                 22                                                      /*!< USIC_CH PCR: CTR22 Position             */\r
+#define USIC_CH_PCR_CTR22_Msk                 (0x01UL << USIC_CH_PCR_CTR22_Pos)                       /*!< USIC_CH PCR: CTR22 Mask                 */\r
+#define USIC_CH_PCR_CTR23_Pos                 23                                                      /*!< USIC_CH PCR: CTR23 Position             */\r
+#define USIC_CH_PCR_CTR23_Msk                 (0x01UL << USIC_CH_PCR_CTR23_Pos)                       /*!< USIC_CH PCR: CTR23 Mask                 */\r
+#define USIC_CH_PCR_CTR24_Pos                 24                                                      /*!< USIC_CH PCR: CTR24 Position             */\r
+#define USIC_CH_PCR_CTR24_Msk                 (0x01UL << USIC_CH_PCR_CTR24_Pos)                       /*!< USIC_CH PCR: CTR24 Mask                 */\r
+#define USIC_CH_PCR_CTR25_Pos                 25                                                      /*!< USIC_CH PCR: CTR25 Position             */\r
+#define USIC_CH_PCR_CTR25_Msk                 (0x01UL << USIC_CH_PCR_CTR25_Pos)                       /*!< USIC_CH PCR: CTR25 Mask                 */\r
+#define USIC_CH_PCR_CTR26_Pos                 26                                                      /*!< USIC_CH PCR: CTR26 Position             */\r
+#define USIC_CH_PCR_CTR26_Msk                 (0x01UL << USIC_CH_PCR_CTR26_Pos)                       /*!< USIC_CH PCR: CTR26 Mask                 */\r
+#define USIC_CH_PCR_CTR27_Pos                 27                                                      /*!< USIC_CH PCR: CTR27 Position             */\r
+#define USIC_CH_PCR_CTR27_Msk                 (0x01UL << USIC_CH_PCR_CTR27_Pos)                       /*!< USIC_CH PCR: CTR27 Mask                 */\r
+#define USIC_CH_PCR_CTR28_Pos                 28                                                      /*!< USIC_CH PCR: CTR28 Position             */\r
+#define USIC_CH_PCR_CTR28_Msk                 (0x01UL << USIC_CH_PCR_CTR28_Pos)                       /*!< USIC_CH PCR: CTR28 Mask                 */\r
+#define USIC_CH_PCR_CTR29_Pos                 29                                                      /*!< USIC_CH PCR: CTR29 Position             */\r
+#define USIC_CH_PCR_CTR29_Msk                 (0x01UL << USIC_CH_PCR_CTR29_Pos)                       /*!< USIC_CH PCR: CTR29 Mask                 */\r
+#define USIC_CH_PCR_CTR30_Pos                 30                                                      /*!< USIC_CH PCR: CTR30 Position             */\r
+#define USIC_CH_PCR_CTR30_Msk                 (0x01UL << USIC_CH_PCR_CTR30_Pos)                       /*!< USIC_CH PCR: CTR30 Mask                 */\r
+#define USIC_CH_PCR_CTR31_Pos                 31                                                      /*!< USIC_CH PCR: CTR31 Position             */\r
+#define USIC_CH_PCR_CTR31_Msk                 (0x01UL << USIC_CH_PCR_CTR31_Pos)                       /*!< USIC_CH PCR: CTR31 Mask                 */\r
+\r
+/* -----------------------------  USIC_CH_PCR_ASCMode  ---------------------------- */\r
+#define USIC_CH_PCR_ASCMode_SMD_Pos           0                                                       /*!< USIC_CH PCR_ASCMode: SMD Position       */\r
+#define USIC_CH_PCR_ASCMode_SMD_Msk           (0x01UL << USIC_CH_PCR_ASCMode_SMD_Pos)                 /*!< USIC_CH PCR_ASCMode: SMD Mask           */\r
+#define USIC_CH_PCR_ASCMode_STPB_Pos          1                                                       /*!< USIC_CH PCR_ASCMode: STPB Position      */\r
+#define USIC_CH_PCR_ASCMode_STPB_Msk          (0x01UL << USIC_CH_PCR_ASCMode_STPB_Pos)                /*!< USIC_CH PCR_ASCMode: STPB Mask          */\r
+#define USIC_CH_PCR_ASCMode_IDM_Pos           2                                                       /*!< USIC_CH PCR_ASCMode: IDM Position       */\r
+#define USIC_CH_PCR_ASCMode_IDM_Msk           (0x01UL << USIC_CH_PCR_ASCMode_IDM_Pos)                 /*!< USIC_CH PCR_ASCMode: IDM Mask           */\r
+#define USIC_CH_PCR_ASCMode_SBIEN_Pos         3                                                       /*!< USIC_CH PCR_ASCMode: SBIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_SBIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_SBIEN_Pos)               /*!< USIC_CH PCR_ASCMode: SBIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_CDEN_Pos          4                                                       /*!< USIC_CH PCR_ASCMode: CDEN Position      */\r
+#define USIC_CH_PCR_ASCMode_CDEN_Msk          (0x01UL << USIC_CH_PCR_ASCMode_CDEN_Pos)                /*!< USIC_CH PCR_ASCMode: CDEN Mask          */\r
+#define USIC_CH_PCR_ASCMode_RNIEN_Pos         5                                                       /*!< USIC_CH PCR_ASCMode: RNIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_RNIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_RNIEN_Pos)               /*!< USIC_CH PCR_ASCMode: RNIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_FEIEN_Pos         6                                                       /*!< USIC_CH PCR_ASCMode: FEIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_FEIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_FEIEN_Pos)               /*!< USIC_CH PCR_ASCMode: FEIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_FFIEN_Pos         7                                                       /*!< USIC_CH PCR_ASCMode: FFIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_FFIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_FFIEN_Pos)               /*!< USIC_CH PCR_ASCMode: FFIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_SP_Pos            8                                                       /*!< USIC_CH PCR_ASCMode: SP Position        */\r
+#define USIC_CH_PCR_ASCMode_SP_Msk            (0x1fUL << USIC_CH_PCR_ASCMode_SP_Pos)                  /*!< USIC_CH PCR_ASCMode: SP Mask            */\r
+#define USIC_CH_PCR_ASCMode_PL_Pos            13                                                      /*!< USIC_CH PCR_ASCMode: PL Position        */\r
+#define USIC_CH_PCR_ASCMode_PL_Msk            (0x07UL << USIC_CH_PCR_ASCMode_PL_Pos)                  /*!< USIC_CH PCR_ASCMode: PL Mask            */\r
+#define USIC_CH_PCR_ASCMode_RSTEN_Pos         16                                                      /*!< USIC_CH PCR_ASCMode: RSTEN Position     */\r
+#define USIC_CH_PCR_ASCMode_RSTEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_RSTEN_Pos)               /*!< USIC_CH PCR_ASCMode: RSTEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_TSTEN_Pos         17                                                      /*!< USIC_CH PCR_ASCMode: TSTEN Position     */\r
+#define USIC_CH_PCR_ASCMode_TSTEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_TSTEN_Pos)               /*!< USIC_CH PCR_ASCMode: TSTEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_ASCMode: MCLK Position      */\r
+#define USIC_CH_PCR_ASCMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_ASCMode_MCLK_Pos)                /*!< USIC_CH PCR_ASCMode: MCLK Mask          */\r
+\r
+/* -----------------------------  USIC_CH_PCR_SSCMode  ---------------------------- */\r
+#define USIC_CH_PCR_SSCMode_MSLSEN_Pos        0                                                       /*!< USIC_CH PCR_SSCMode: MSLSEN Position    */\r
+#define USIC_CH_PCR_SSCMode_MSLSEN_Msk        (0x01UL << USIC_CH_PCR_SSCMode_MSLSEN_Pos)              /*!< USIC_CH PCR_SSCMode: MSLSEN Mask        */\r
+#define USIC_CH_PCR_SSCMode_SELCTR_Pos        1                                                       /*!< USIC_CH PCR_SSCMode: SELCTR Position    */\r
+#define USIC_CH_PCR_SSCMode_SELCTR_Msk        (0x01UL << USIC_CH_PCR_SSCMode_SELCTR_Pos)              /*!< USIC_CH PCR_SSCMode: SELCTR Mask        */\r
+#define USIC_CH_PCR_SSCMode_SELINV_Pos        2                                                       /*!< USIC_CH PCR_SSCMode: SELINV Position    */\r
+#define USIC_CH_PCR_SSCMode_SELINV_Msk        (0x01UL << USIC_CH_PCR_SSCMode_SELINV_Pos)              /*!< USIC_CH PCR_SSCMode: SELINV Mask        */\r
+#define USIC_CH_PCR_SSCMode_FEM_Pos           3                                                       /*!< USIC_CH PCR_SSCMode: FEM Position       */\r
+#define USIC_CH_PCR_SSCMode_FEM_Msk           (0x01UL << USIC_CH_PCR_SSCMode_FEM_Pos)                 /*!< USIC_CH PCR_SSCMode: FEM Mask           */\r
+#define USIC_CH_PCR_SSCMode_CTQSEL1_Pos       4                                                       /*!< USIC_CH PCR_SSCMode: CTQSEL1 Position   */\r
+#define USIC_CH_PCR_SSCMode_CTQSEL1_Msk       (0x03UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos)             /*!< USIC_CH PCR_SSCMode: CTQSEL1 Mask       */\r
+#define USIC_CH_PCR_SSCMode_PCTQ1_Pos         6                                                       /*!< USIC_CH PCR_SSCMode: PCTQ1 Position     */\r
+#define USIC_CH_PCR_SSCMode_PCTQ1_Msk         (0x03UL << USIC_CH_PCR_SSCMode_PCTQ1_Pos)               /*!< USIC_CH PCR_SSCMode: PCTQ1 Mask         */\r
+#define USIC_CH_PCR_SSCMode_DCTQ1_Pos         8                                                       /*!< USIC_CH PCR_SSCMode: DCTQ1 Position     */\r
+#define USIC_CH_PCR_SSCMode_DCTQ1_Msk         (0x1fUL << USIC_CH_PCR_SSCMode_DCTQ1_Pos)               /*!< USIC_CH PCR_SSCMode: DCTQ1 Mask         */\r
+#define USIC_CH_PCR_SSCMode_PARIEN_Pos        13                                                      /*!< USIC_CH PCR_SSCMode: PARIEN Position    */\r
+#define USIC_CH_PCR_SSCMode_PARIEN_Msk        (0x01UL << USIC_CH_PCR_SSCMode_PARIEN_Pos)              /*!< USIC_CH PCR_SSCMode: PARIEN Mask        */\r
+#define USIC_CH_PCR_SSCMode_MSLSIEN_Pos       14                                                      /*!< USIC_CH PCR_SSCMode: MSLSIEN Position   */\r
+#define USIC_CH_PCR_SSCMode_MSLSIEN_Msk       (0x01UL << USIC_CH_PCR_SSCMode_MSLSIEN_Pos)             /*!< USIC_CH PCR_SSCMode: MSLSIEN Mask       */\r
+#define USIC_CH_PCR_SSCMode_DX2TIEN_Pos       15                                                      /*!< USIC_CH PCR_SSCMode: DX2TIEN Position   */\r
+#define USIC_CH_PCR_SSCMode_DX2TIEN_Msk       (0x01UL << USIC_CH_PCR_SSCMode_DX2TIEN_Pos)             /*!< USIC_CH PCR_SSCMode: DX2TIEN Mask       */\r
+#define USIC_CH_PCR_SSCMode_SELO_Pos          16                                                      /*!< USIC_CH PCR_SSCMode: SELO Position      */\r
+#define USIC_CH_PCR_SSCMode_SELO_Msk          (0x000000ffUL << USIC_CH_PCR_SSCMode_SELO_Pos)          /*!< USIC_CH PCR_SSCMode: SELO Mask          */\r
+#define USIC_CH_PCR_SSCMode_TIWEN_Pos         24                                                      /*!< USIC_CH PCR_SSCMode: TIWEN Position     */\r
+#define USIC_CH_PCR_SSCMode_TIWEN_Msk         (0x01UL << USIC_CH_PCR_SSCMode_TIWEN_Pos)               /*!< USIC_CH PCR_SSCMode: TIWEN Mask         */\r
+#define USIC_CH_PCR_SSCMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_SSCMode: MCLK Position      */\r
+#define USIC_CH_PCR_SSCMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_SSCMode_MCLK_Pos)                /*!< USIC_CH PCR_SSCMode: MCLK Mask          */\r
+\r
+/* -----------------------------  USIC_CH_PCR_IICMode  ---------------------------- */\r
+#define USIC_CH_PCR_IICMode_SLAD_Pos          0                                                       /*!< USIC_CH PCR_IICMode: SLAD Position      */\r
+#define USIC_CH_PCR_IICMode_SLAD_Msk          (0x0000ffffUL << USIC_CH_PCR_IICMode_SLAD_Pos)          /*!< USIC_CH PCR_IICMode: SLAD Mask          */\r
+#define USIC_CH_PCR_IICMode_ACK00_Pos         16                                                      /*!< USIC_CH PCR_IICMode: ACK00 Position     */\r
+#define USIC_CH_PCR_IICMode_ACK00_Msk         (0x01UL << USIC_CH_PCR_IICMode_ACK00_Pos)               /*!< USIC_CH PCR_IICMode: ACK00 Mask         */\r
+#define USIC_CH_PCR_IICMode_STIM_Pos          17                                                      /*!< USIC_CH PCR_IICMode: STIM Position      */\r
+#define USIC_CH_PCR_IICMode_STIM_Msk          (0x01UL << USIC_CH_PCR_IICMode_STIM_Pos)                /*!< USIC_CH PCR_IICMode: STIM Mask          */\r
+#define USIC_CH_PCR_IICMode_SCRIEN_Pos        18                                                      /*!< USIC_CH PCR_IICMode: SCRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_SCRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_SCRIEN_Pos)              /*!< USIC_CH PCR_IICMode: SCRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_RSCRIEN_Pos       19                                                      /*!< USIC_CH PCR_IICMode: RSCRIEN Position   */\r
+#define USIC_CH_PCR_IICMode_RSCRIEN_Msk       (0x01UL << USIC_CH_PCR_IICMode_RSCRIEN_Pos)             /*!< USIC_CH PCR_IICMode: RSCRIEN Mask       */\r
+#define USIC_CH_PCR_IICMode_PCRIEN_Pos        20                                                      /*!< USIC_CH PCR_IICMode: PCRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_PCRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_PCRIEN_Pos)              /*!< USIC_CH PCR_IICMode: PCRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_NACKIEN_Pos       21                                                      /*!< USIC_CH PCR_IICMode: NACKIEN Position   */\r
+#define USIC_CH_PCR_IICMode_NACKIEN_Msk       (0x01UL << USIC_CH_PCR_IICMode_NACKIEN_Pos)             /*!< USIC_CH PCR_IICMode: NACKIEN Mask       */\r
+#define USIC_CH_PCR_IICMode_ARLIEN_Pos        22                                                      /*!< USIC_CH PCR_IICMode: ARLIEN Position    */\r
+#define USIC_CH_PCR_IICMode_ARLIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_ARLIEN_Pos)              /*!< USIC_CH PCR_IICMode: ARLIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_SRRIEN_Pos        23                                                      /*!< USIC_CH PCR_IICMode: SRRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_SRRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_SRRIEN_Pos)              /*!< USIC_CH PCR_IICMode: SRRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_ERRIEN_Pos        24                                                      /*!< USIC_CH PCR_IICMode: ERRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_ERRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_ERRIEN_Pos)              /*!< USIC_CH PCR_IICMode: ERRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_SACKDIS_Pos       25                                                      /*!< USIC_CH PCR_IICMode: SACKDIS Position   */\r
+#define USIC_CH_PCR_IICMode_SACKDIS_Msk       (0x01UL << USIC_CH_PCR_IICMode_SACKDIS_Pos)             /*!< USIC_CH PCR_IICMode: SACKDIS Mask       */\r
+#define USIC_CH_PCR_IICMode_HDEL_Pos          26                                                      /*!< USIC_CH PCR_IICMode: HDEL Position      */\r
+#define USIC_CH_PCR_IICMode_HDEL_Msk          (0x0fUL << USIC_CH_PCR_IICMode_HDEL_Pos)                /*!< USIC_CH PCR_IICMode: HDEL Mask          */\r
+#define USIC_CH_PCR_IICMode_ACKIEN_Pos        30                                                      /*!< USIC_CH PCR_IICMode: ACKIEN Position    */\r
+#define USIC_CH_PCR_IICMode_ACKIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_ACKIEN_Pos)              /*!< USIC_CH PCR_IICMode: ACKIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_IICMode: MCLK Position      */\r
+#define USIC_CH_PCR_IICMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_IICMode_MCLK_Pos)                /*!< USIC_CH PCR_IICMode: MCLK Mask          */\r
+\r
+/* -----------------------------  USIC_CH_PCR_IISMode  ---------------------------- */\r
+#define USIC_CH_PCR_IISMode_WAGEN_Pos         0                                                       /*!< USIC_CH PCR_IISMode: WAGEN Position     */\r
+#define USIC_CH_PCR_IISMode_WAGEN_Msk         (0x01UL << USIC_CH_PCR_IISMode_WAGEN_Pos)               /*!< USIC_CH PCR_IISMode: WAGEN Mask         */\r
+#define USIC_CH_PCR_IISMode_DTEN_Pos          1                                                       /*!< USIC_CH PCR_IISMode: DTEN Position      */\r
+#define USIC_CH_PCR_IISMode_DTEN_Msk          (0x01UL << USIC_CH_PCR_IISMode_DTEN_Pos)                /*!< USIC_CH PCR_IISMode: DTEN Mask          */\r
+#define USIC_CH_PCR_IISMode_SELINV_Pos        2                                                       /*!< USIC_CH PCR_IISMode: SELINV Position    */\r
+#define USIC_CH_PCR_IISMode_SELINV_Msk        (0x01UL << USIC_CH_PCR_IISMode_SELINV_Pos)              /*!< USIC_CH PCR_IISMode: SELINV Mask        */\r
+#define USIC_CH_PCR_IISMode_WAFEIEN_Pos       4                                                       /*!< USIC_CH PCR_IISMode: WAFEIEN Position   */\r
+#define USIC_CH_PCR_IISMode_WAFEIEN_Msk       (0x01UL << USIC_CH_PCR_IISMode_WAFEIEN_Pos)             /*!< USIC_CH PCR_IISMode: WAFEIEN Mask       */\r
+#define USIC_CH_PCR_IISMode_WAREIEN_Pos       5                                                       /*!< USIC_CH PCR_IISMode: WAREIEN Position   */\r
+#define USIC_CH_PCR_IISMode_WAREIEN_Msk       (0x01UL << USIC_CH_PCR_IISMode_WAREIEN_Pos)             /*!< USIC_CH PCR_IISMode: WAREIEN Mask       */\r
+#define USIC_CH_PCR_IISMode_ENDIEN_Pos        6                                                       /*!< USIC_CH PCR_IISMode: ENDIEN Position    */\r
+#define USIC_CH_PCR_IISMode_ENDIEN_Msk        (0x01UL << USIC_CH_PCR_IISMode_ENDIEN_Pos)              /*!< USIC_CH PCR_IISMode: ENDIEN Mask        */\r
+#define USIC_CH_PCR_IISMode_DX2TIEN_Pos       15                                                      /*!< USIC_CH PCR_IISMode: DX2TIEN Position   */\r
+#define USIC_CH_PCR_IISMode_DX2TIEN_Msk       (0x01UL << USIC_CH_PCR_IISMode_DX2TIEN_Pos)             /*!< USIC_CH PCR_IISMode: DX2TIEN Mask       */\r
+#define USIC_CH_PCR_IISMode_TDEL_Pos          16                                                      /*!< USIC_CH PCR_IISMode: TDEL Position      */\r
+#define USIC_CH_PCR_IISMode_TDEL_Msk          (0x3fUL << USIC_CH_PCR_IISMode_TDEL_Pos)                /*!< USIC_CH PCR_IISMode: TDEL Mask          */\r
+#define USIC_CH_PCR_IISMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_IISMode: MCLK Position      */\r
+#define USIC_CH_PCR_IISMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_IISMode_MCLK_Pos)                /*!< USIC_CH PCR_IISMode: MCLK Mask          */\r
+\r
+/* ---------------------------------  USIC_CH_CCR  -------------------------------- */\r
+#define USIC_CH_CCR_MODE_Pos                  0                                                       /*!< USIC_CH CCR: MODE Position              */\r
+#define USIC_CH_CCR_MODE_Msk                  (0x0fUL << USIC_CH_CCR_MODE_Pos)                        /*!< USIC_CH CCR: MODE Mask                  */\r
+#define USIC_CH_CCR_HPCEN_Pos                 6                                                       /*!< USIC_CH CCR: HPCEN Position             */\r
+#define USIC_CH_CCR_HPCEN_Msk                 (0x03UL << USIC_CH_CCR_HPCEN_Pos)                       /*!< USIC_CH CCR: HPCEN Mask                 */\r
+#define USIC_CH_CCR_PM_Pos                    8                                                       /*!< USIC_CH CCR: PM Position                */\r
+#define USIC_CH_CCR_PM_Msk                    (0x03UL << USIC_CH_CCR_PM_Pos)                          /*!< USIC_CH CCR: PM Mask                    */\r
+#define USIC_CH_CCR_RSIEN_Pos                 10                                                      /*!< USIC_CH CCR: RSIEN Position             */\r
+#define USIC_CH_CCR_RSIEN_Msk                 (0x01UL << USIC_CH_CCR_RSIEN_Pos)                       /*!< USIC_CH CCR: RSIEN Mask                 */\r
+#define USIC_CH_CCR_DLIEN_Pos                 11                                                      /*!< USIC_CH CCR: DLIEN Position             */\r
+#define USIC_CH_CCR_DLIEN_Msk                 (0x01UL << USIC_CH_CCR_DLIEN_Pos)                       /*!< USIC_CH CCR: DLIEN Mask                 */\r
+#define USIC_CH_CCR_TSIEN_Pos                 12                                                      /*!< USIC_CH CCR: TSIEN Position             */\r
+#define USIC_CH_CCR_TSIEN_Msk                 (0x01UL << USIC_CH_CCR_TSIEN_Pos)                       /*!< USIC_CH CCR: TSIEN Mask                 */\r
+#define USIC_CH_CCR_TBIEN_Pos                 13                                                      /*!< USIC_CH CCR: TBIEN Position             */\r
+#define USIC_CH_CCR_TBIEN_Msk                 (0x01UL << USIC_CH_CCR_TBIEN_Pos)                       /*!< USIC_CH CCR: TBIEN Mask                 */\r
+#define USIC_CH_CCR_RIEN_Pos                  14                                                      /*!< USIC_CH CCR: RIEN Position              */\r
+#define USIC_CH_CCR_RIEN_Msk                  (0x01UL << USIC_CH_CCR_RIEN_Pos)                        /*!< USIC_CH CCR: RIEN Mask                  */\r
+#define USIC_CH_CCR_AIEN_Pos                  15                                                      /*!< USIC_CH CCR: AIEN Position              */\r
+#define USIC_CH_CCR_AIEN_Msk                  (0x01UL << USIC_CH_CCR_AIEN_Pos)                        /*!< USIC_CH CCR: AIEN Mask                  */\r
+#define USIC_CH_CCR_BRGIEN_Pos                16                                                      /*!< USIC_CH CCR: BRGIEN Position            */\r
+#define USIC_CH_CCR_BRGIEN_Msk                (0x01UL << USIC_CH_CCR_BRGIEN_Pos)                      /*!< USIC_CH CCR: BRGIEN Mask                */\r
+\r
+/* --------------------------------  USIC_CH_CMTR  -------------------------------- */\r
+#define USIC_CH_CMTR_CTV_Pos                  0                                                       /*!< USIC_CH CMTR: CTV Position              */\r
+#define USIC_CH_CMTR_CTV_Msk                  (0x000003ffUL << USIC_CH_CMTR_CTV_Pos)                  /*!< USIC_CH CMTR: CTV Mask                  */\r
+\r
+/* ---------------------------------  USIC_CH_PSR  -------------------------------- */\r
+#define USIC_CH_PSR_ST0_Pos                   0                                                       /*!< USIC_CH PSR: ST0 Position               */\r
+#define USIC_CH_PSR_ST0_Msk                   (0x01UL << USIC_CH_PSR_ST0_Pos)                         /*!< USIC_CH PSR: ST0 Mask                   */\r
+#define USIC_CH_PSR_ST1_Pos                   1                                                       /*!< USIC_CH PSR: ST1 Position               */\r
+#define USIC_CH_PSR_ST1_Msk                   (0x01UL << USIC_CH_PSR_ST1_Pos)                         /*!< USIC_CH PSR: ST1 Mask                   */\r
+#define USIC_CH_PSR_ST2_Pos                   2                                                       /*!< USIC_CH PSR: ST2 Position               */\r
+#define USIC_CH_PSR_ST2_Msk                   (0x01UL << USIC_CH_PSR_ST2_Pos)                         /*!< USIC_CH PSR: ST2 Mask                   */\r
+#define USIC_CH_PSR_ST3_Pos                   3                                                       /*!< USIC_CH PSR: ST3 Position               */\r
+#define USIC_CH_PSR_ST3_Msk                   (0x01UL << USIC_CH_PSR_ST3_Pos)                         /*!< USIC_CH PSR: ST3 Mask                   */\r
+#define USIC_CH_PSR_ST4_Pos                   4                                                       /*!< USIC_CH PSR: ST4 Position               */\r
+#define USIC_CH_PSR_ST4_Msk                   (0x01UL << USIC_CH_PSR_ST4_Pos)                         /*!< USIC_CH PSR: ST4 Mask                   */\r
+#define USIC_CH_PSR_ST5_Pos                   5                                                       /*!< USIC_CH PSR: ST5 Position               */\r
+#define USIC_CH_PSR_ST5_Msk                   (0x01UL << USIC_CH_PSR_ST5_Pos)                         /*!< USIC_CH PSR: ST5 Mask                   */\r
+#define USIC_CH_PSR_ST6_Pos                   6                                                       /*!< USIC_CH PSR: ST6 Position               */\r
+#define USIC_CH_PSR_ST6_Msk                   (0x01UL << USIC_CH_PSR_ST6_Pos)                         /*!< USIC_CH PSR: ST6 Mask                   */\r
+#define USIC_CH_PSR_ST7_Pos                   7                                                       /*!< USIC_CH PSR: ST7 Position               */\r
+#define USIC_CH_PSR_ST7_Msk                   (0x01UL << USIC_CH_PSR_ST7_Pos)                         /*!< USIC_CH PSR: ST7 Mask                   */\r
+#define USIC_CH_PSR_ST8_Pos                   8                                                       /*!< USIC_CH PSR: ST8 Position               */\r
+#define USIC_CH_PSR_ST8_Msk                   (0x01UL << USIC_CH_PSR_ST8_Pos)                         /*!< USIC_CH PSR: ST8 Mask                   */\r
+#define USIC_CH_PSR_ST9_Pos                   9                                                       /*!< USIC_CH PSR: ST9 Position               */\r
+#define USIC_CH_PSR_ST9_Msk                   (0x01UL << USIC_CH_PSR_ST9_Pos)                         /*!< USIC_CH PSR: ST9 Mask                   */\r
+#define USIC_CH_PSR_RSIF_Pos                  10                                                      /*!< USIC_CH PSR: RSIF Position              */\r
+#define USIC_CH_PSR_RSIF_Msk                  (0x01UL << USIC_CH_PSR_RSIF_Pos)                        /*!< USIC_CH PSR: RSIF Mask                  */\r
+#define USIC_CH_PSR_DLIF_Pos                  11                                                      /*!< USIC_CH PSR: DLIF Position              */\r
+#define USIC_CH_PSR_DLIF_Msk                  (0x01UL << USIC_CH_PSR_DLIF_Pos)                        /*!< USIC_CH PSR: DLIF Mask                  */\r
+#define USIC_CH_PSR_TSIF_Pos                  12                                                      /*!< USIC_CH PSR: TSIF Position              */\r
+#define USIC_CH_PSR_TSIF_Msk                  (0x01UL << USIC_CH_PSR_TSIF_Pos)                        /*!< USIC_CH PSR: TSIF Mask                  */\r
+#define USIC_CH_PSR_TBIF_Pos                  13                                                      /*!< USIC_CH PSR: TBIF Position              */\r
+#define USIC_CH_PSR_TBIF_Msk                  (0x01UL << USIC_CH_PSR_TBIF_Pos)                        /*!< USIC_CH PSR: TBIF Mask                  */\r
+#define USIC_CH_PSR_RIF_Pos                   14                                                      /*!< USIC_CH PSR: RIF Position               */\r
+#define USIC_CH_PSR_RIF_Msk                   (0x01UL << USIC_CH_PSR_RIF_Pos)                         /*!< USIC_CH PSR: RIF Mask                   */\r
+#define USIC_CH_PSR_AIF_Pos                   15                                                      /*!< USIC_CH PSR: AIF Position               */\r
+#define USIC_CH_PSR_AIF_Msk                   (0x01UL << USIC_CH_PSR_AIF_Pos)                         /*!< USIC_CH PSR: AIF Mask                   */\r
+#define USIC_CH_PSR_BRGIF_Pos                 16                                                      /*!< USIC_CH PSR: BRGIF Position             */\r
+#define USIC_CH_PSR_BRGIF_Msk                 (0x01UL << USIC_CH_PSR_BRGIF_Pos)                       /*!< USIC_CH PSR: BRGIF Mask                 */\r
+\r
+/* -----------------------------  USIC_CH_PSR_ASCMode  ---------------------------- */\r
+#define USIC_CH_PSR_ASCMode_TXIDLE_Pos        0                                                       /*!< USIC_CH PSR_ASCMode: TXIDLE Position    */\r
+#define USIC_CH_PSR_ASCMode_TXIDLE_Msk        (0x01UL << USIC_CH_PSR_ASCMode_TXIDLE_Pos)              /*!< USIC_CH PSR_ASCMode: TXIDLE Mask        */\r
+#define USIC_CH_PSR_ASCMode_RXIDLE_Pos        1                                                       /*!< USIC_CH PSR_ASCMode: RXIDLE Position    */\r
+#define USIC_CH_PSR_ASCMode_RXIDLE_Msk        (0x01UL << USIC_CH_PSR_ASCMode_RXIDLE_Pos)              /*!< USIC_CH PSR_ASCMode: RXIDLE Mask        */\r
+#define USIC_CH_PSR_ASCMode_SBD_Pos           2                                                       /*!< USIC_CH PSR_ASCMode: SBD Position       */\r
+#define USIC_CH_PSR_ASCMode_SBD_Msk           (0x01UL << USIC_CH_PSR_ASCMode_SBD_Pos)                 /*!< USIC_CH PSR_ASCMode: SBD Mask           */\r
+#define USIC_CH_PSR_ASCMode_COL_Pos           3                                                       /*!< USIC_CH PSR_ASCMode: COL Position       */\r
+#define USIC_CH_PSR_ASCMode_COL_Msk           (0x01UL << USIC_CH_PSR_ASCMode_COL_Pos)                 /*!< USIC_CH PSR_ASCMode: COL Mask           */\r
+#define USIC_CH_PSR_ASCMode_RNS_Pos           4                                                       /*!< USIC_CH PSR_ASCMode: RNS Position       */\r
+#define USIC_CH_PSR_ASCMode_RNS_Msk           (0x01UL << USIC_CH_PSR_ASCMode_RNS_Pos)                 /*!< USIC_CH PSR_ASCMode: RNS Mask           */\r
+#define USIC_CH_PSR_ASCMode_FER0_Pos          5                                                       /*!< USIC_CH PSR_ASCMode: FER0 Position      */\r
+#define USIC_CH_PSR_ASCMode_FER0_Msk          (0x01UL << USIC_CH_PSR_ASCMode_FER0_Pos)                /*!< USIC_CH PSR_ASCMode: FER0 Mask          */\r
+#define USIC_CH_PSR_ASCMode_FER1_Pos          6                                                       /*!< USIC_CH PSR_ASCMode: FER1 Position      */\r
+#define USIC_CH_PSR_ASCMode_FER1_Msk          (0x01UL << USIC_CH_PSR_ASCMode_FER1_Pos)                /*!< USIC_CH PSR_ASCMode: FER1 Mask          */\r
+#define USIC_CH_PSR_ASCMode_RFF_Pos           7                                                       /*!< USIC_CH PSR_ASCMode: RFF Position       */\r
+#define USIC_CH_PSR_ASCMode_RFF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_RFF_Pos)                 /*!< USIC_CH PSR_ASCMode: RFF Mask           */\r
+#define USIC_CH_PSR_ASCMode_TFF_Pos           8                                                       /*!< USIC_CH PSR_ASCMode: TFF Position       */\r
+#define USIC_CH_PSR_ASCMode_TFF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_TFF_Pos)                 /*!< USIC_CH PSR_ASCMode: TFF Mask           */\r
+#define USIC_CH_PSR_ASCMode_BUSY_Pos          9                                                       /*!< USIC_CH PSR_ASCMode: BUSY Position      */\r
+#define USIC_CH_PSR_ASCMode_BUSY_Msk          (0x01UL << USIC_CH_PSR_ASCMode_BUSY_Pos)                /*!< USIC_CH PSR_ASCMode: BUSY Mask          */\r
+#define USIC_CH_PSR_ASCMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_ASCMode: RSIF Position      */\r
+#define USIC_CH_PSR_ASCMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_RSIF_Pos)                /*!< USIC_CH PSR_ASCMode: RSIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_ASCMode: DLIF Position      */\r
+#define USIC_CH_PSR_ASCMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_DLIF_Pos)                /*!< USIC_CH PSR_ASCMode: DLIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_ASCMode: TSIF Position      */\r
+#define USIC_CH_PSR_ASCMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_TSIF_Pos)                /*!< USIC_CH PSR_ASCMode: TSIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_ASCMode: TBIF Position      */\r
+#define USIC_CH_PSR_ASCMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_TBIF_Pos)                /*!< USIC_CH PSR_ASCMode: TBIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_ASCMode: RIF Position       */\r
+#define USIC_CH_PSR_ASCMode_RIF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_RIF_Pos)                 /*!< USIC_CH PSR_ASCMode: RIF Mask           */\r
+#define USIC_CH_PSR_ASCMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_ASCMode: AIF Position       */\r
+#define USIC_CH_PSR_ASCMode_AIF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_AIF_Pos)                 /*!< USIC_CH PSR_ASCMode: AIF Mask           */\r
+#define USIC_CH_PSR_ASCMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_ASCMode: BRGIF Position     */\r
+#define USIC_CH_PSR_ASCMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_ASCMode_BRGIF_Pos)               /*!< USIC_CH PSR_ASCMode: BRGIF Mask         */\r
+\r
+/* -----------------------------  USIC_CH_PSR_SSCMode  ---------------------------- */\r
+#define USIC_CH_PSR_SSCMode_MSLS_Pos          0                                                       /*!< USIC_CH PSR_SSCMode: MSLS Position      */\r
+#define USIC_CH_PSR_SSCMode_MSLS_Msk          (0x01UL << USIC_CH_PSR_SSCMode_MSLS_Pos)                /*!< USIC_CH PSR_SSCMode: MSLS Mask          */\r
+#define USIC_CH_PSR_SSCMode_DX2S_Pos          1                                                       /*!< USIC_CH PSR_SSCMode: DX2S Position      */\r
+#define USIC_CH_PSR_SSCMode_DX2S_Msk          (0x01UL << USIC_CH_PSR_SSCMode_DX2S_Pos)                /*!< USIC_CH PSR_SSCMode: DX2S Mask          */\r
+#define USIC_CH_PSR_SSCMode_MSLSEV_Pos        2                                                       /*!< USIC_CH PSR_SSCMode: MSLSEV Position    */\r
+#define USIC_CH_PSR_SSCMode_MSLSEV_Msk        (0x01UL << USIC_CH_PSR_SSCMode_MSLSEV_Pos)              /*!< USIC_CH PSR_SSCMode: MSLSEV Mask        */\r
+#define USIC_CH_PSR_SSCMode_DX2TEV_Pos        3                                                       /*!< USIC_CH PSR_SSCMode: DX2TEV Position    */\r
+#define USIC_CH_PSR_SSCMode_DX2TEV_Msk        (0x01UL << USIC_CH_PSR_SSCMode_DX2TEV_Pos)              /*!< USIC_CH PSR_SSCMode: DX2TEV Mask        */\r
+#define USIC_CH_PSR_SSCMode_PARERR_Pos        4                                                       /*!< USIC_CH PSR_SSCMode: PARERR Position    */\r
+#define USIC_CH_PSR_SSCMode_PARERR_Msk        (0x01UL << USIC_CH_PSR_SSCMode_PARERR_Pos)              /*!< USIC_CH PSR_SSCMode: PARERR Mask        */\r
+#define USIC_CH_PSR_SSCMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_SSCMode: RSIF Position      */\r
+#define USIC_CH_PSR_SSCMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_RSIF_Pos)                /*!< USIC_CH PSR_SSCMode: RSIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_SSCMode: DLIF Position      */\r
+#define USIC_CH_PSR_SSCMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_DLIF_Pos)                /*!< USIC_CH PSR_SSCMode: DLIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_SSCMode: TSIF Position      */\r
+#define USIC_CH_PSR_SSCMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_TSIF_Pos)                /*!< USIC_CH PSR_SSCMode: TSIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_SSCMode: TBIF Position      */\r
+#define USIC_CH_PSR_SSCMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_TBIF_Pos)                /*!< USIC_CH PSR_SSCMode: TBIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_SSCMode: RIF Position       */\r
+#define USIC_CH_PSR_SSCMode_RIF_Msk           (0x01UL << USIC_CH_PSR_SSCMode_RIF_Pos)                 /*!< USIC_CH PSR_SSCMode: RIF Mask           */\r
+#define USIC_CH_PSR_SSCMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_SSCMode: AIF Position       */\r
+#define USIC_CH_PSR_SSCMode_AIF_Msk           (0x01UL << USIC_CH_PSR_SSCMode_AIF_Pos)                 /*!< USIC_CH PSR_SSCMode: AIF Mask           */\r
+#define USIC_CH_PSR_SSCMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_SSCMode: BRGIF Position     */\r
+#define USIC_CH_PSR_SSCMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_SSCMode_BRGIF_Pos)               /*!< USIC_CH PSR_SSCMode: BRGIF Mask         */\r
+\r
+/* -----------------------------  USIC_CH_PSR_IICMode  ---------------------------- */\r
+#define USIC_CH_PSR_IICMode_SLSEL_Pos         0                                                       /*!< USIC_CH PSR_IICMode: SLSEL Position     */\r
+#define USIC_CH_PSR_IICMode_SLSEL_Msk         (0x01UL << USIC_CH_PSR_IICMode_SLSEL_Pos)               /*!< USIC_CH PSR_IICMode: SLSEL Mask         */\r
+#define USIC_CH_PSR_IICMode_WTDF_Pos          1                                                       /*!< USIC_CH PSR_IICMode: WTDF Position      */\r
+#define USIC_CH_PSR_IICMode_WTDF_Msk          (0x01UL << USIC_CH_PSR_IICMode_WTDF_Pos)                /*!< USIC_CH PSR_IICMode: WTDF Mask          */\r
+#define USIC_CH_PSR_IICMode_SCR_Pos           2                                                       /*!< USIC_CH PSR_IICMode: SCR Position       */\r
+#define USIC_CH_PSR_IICMode_SCR_Msk           (0x01UL << USIC_CH_PSR_IICMode_SCR_Pos)                 /*!< USIC_CH PSR_IICMode: SCR Mask           */\r
+#define USIC_CH_PSR_IICMode_RSCR_Pos          3                                                       /*!< USIC_CH PSR_IICMode: RSCR Position      */\r
+#define USIC_CH_PSR_IICMode_RSCR_Msk          (0x01UL << USIC_CH_PSR_IICMode_RSCR_Pos)                /*!< USIC_CH PSR_IICMode: RSCR Mask          */\r
+#define USIC_CH_PSR_IICMode_PCR_Pos           4                                                       /*!< USIC_CH PSR_IICMode: PCR Position       */\r
+#define USIC_CH_PSR_IICMode_PCR_Msk           (0x01UL << USIC_CH_PSR_IICMode_PCR_Pos)                 /*!< USIC_CH PSR_IICMode: PCR Mask           */\r
+#define USIC_CH_PSR_IICMode_NACK_Pos          5                                                       /*!< USIC_CH PSR_IICMode: NACK Position      */\r
+#define USIC_CH_PSR_IICMode_NACK_Msk          (0x01UL << USIC_CH_PSR_IICMode_NACK_Pos)                /*!< USIC_CH PSR_IICMode: NACK Mask          */\r
+#define USIC_CH_PSR_IICMode_ARL_Pos           6                                                       /*!< USIC_CH PSR_IICMode: ARL Position       */\r
+#define USIC_CH_PSR_IICMode_ARL_Msk           (0x01UL << USIC_CH_PSR_IICMode_ARL_Pos)                 /*!< USIC_CH PSR_IICMode: ARL Mask           */\r
+#define USIC_CH_PSR_IICMode_SRR_Pos           7                                                       /*!< USIC_CH PSR_IICMode: SRR Position       */\r
+#define USIC_CH_PSR_IICMode_SRR_Msk           (0x01UL << USIC_CH_PSR_IICMode_SRR_Pos)                 /*!< USIC_CH PSR_IICMode: SRR Mask           */\r
+#define USIC_CH_PSR_IICMode_ERR_Pos           8                                                       /*!< USIC_CH PSR_IICMode: ERR Position       */\r
+#define USIC_CH_PSR_IICMode_ERR_Msk           (0x01UL << USIC_CH_PSR_IICMode_ERR_Pos)                 /*!< USIC_CH PSR_IICMode: ERR Mask           */\r
+#define USIC_CH_PSR_IICMode_ACK_Pos           9                                                       /*!< USIC_CH PSR_IICMode: ACK Position       */\r
+#define USIC_CH_PSR_IICMode_ACK_Msk           (0x01UL << USIC_CH_PSR_IICMode_ACK_Pos)                 /*!< USIC_CH PSR_IICMode: ACK Mask           */\r
+#define USIC_CH_PSR_IICMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_IICMode: RSIF Position      */\r
+#define USIC_CH_PSR_IICMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_RSIF_Pos)                /*!< USIC_CH PSR_IICMode: RSIF Mask          */\r
+#define USIC_CH_PSR_IICMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_IICMode: DLIF Position      */\r
+#define USIC_CH_PSR_IICMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_DLIF_Pos)                /*!< USIC_CH PSR_IICMode: DLIF Mask          */\r
+#define USIC_CH_PSR_IICMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_IICMode: TSIF Position      */\r
+#define USIC_CH_PSR_IICMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_TSIF_Pos)                /*!< USIC_CH PSR_IICMode: TSIF Mask          */\r
+#define USIC_CH_PSR_IICMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_IICMode: TBIF Position      */\r
+#define USIC_CH_PSR_IICMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_TBIF_Pos)                /*!< USIC_CH PSR_IICMode: TBIF Mask          */\r
+#define USIC_CH_PSR_IICMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_IICMode: RIF Position       */\r
+#define USIC_CH_PSR_IICMode_RIF_Msk           (0x01UL << USIC_CH_PSR_IICMode_RIF_Pos)                 /*!< USIC_CH PSR_IICMode: RIF Mask           */\r
+#define USIC_CH_PSR_IICMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_IICMode: AIF Position       */\r
+#define USIC_CH_PSR_IICMode_AIF_Msk           (0x01UL << USIC_CH_PSR_IICMode_AIF_Pos)                 /*!< USIC_CH PSR_IICMode: AIF Mask           */\r
+#define USIC_CH_PSR_IICMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_IICMode: BRGIF Position     */\r
+#define USIC_CH_PSR_IICMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_IICMode_BRGIF_Pos)               /*!< USIC_CH PSR_IICMode: BRGIF Mask         */\r
+\r
+/* -----------------------------  USIC_CH_PSR_IISMode  ---------------------------- */\r
+#define USIC_CH_PSR_IISMode_WA_Pos            0                                                       /*!< USIC_CH PSR_IISMode: WA Position        */\r
+#define USIC_CH_PSR_IISMode_WA_Msk            (0x01UL << USIC_CH_PSR_IISMode_WA_Pos)                  /*!< USIC_CH PSR_IISMode: WA Mask            */\r
+#define USIC_CH_PSR_IISMode_DX2S_Pos          1                                                       /*!< USIC_CH PSR_IISMode: DX2S Position      */\r
+#define USIC_CH_PSR_IISMode_DX2S_Msk          (0x01UL << USIC_CH_PSR_IISMode_DX2S_Pos)                /*!< USIC_CH PSR_IISMode: DX2S Mask          */\r
+#define USIC_CH_PSR_IISMode_DX2TEV_Pos        3                                                       /*!< USIC_CH PSR_IISMode: DX2TEV Position    */\r
+#define USIC_CH_PSR_IISMode_DX2TEV_Msk        (0x01UL << USIC_CH_PSR_IISMode_DX2TEV_Pos)              /*!< USIC_CH PSR_IISMode: DX2TEV Mask        */\r
+#define USIC_CH_PSR_IISMode_WAFE_Pos          4                                                       /*!< USIC_CH PSR_IISMode: WAFE Position      */\r
+#define USIC_CH_PSR_IISMode_WAFE_Msk          (0x01UL << USIC_CH_PSR_IISMode_WAFE_Pos)                /*!< USIC_CH PSR_IISMode: WAFE Mask          */\r
+#define USIC_CH_PSR_IISMode_WARE_Pos          5                                                       /*!< USIC_CH PSR_IISMode: WARE Position      */\r
+#define USIC_CH_PSR_IISMode_WARE_Msk          (0x01UL << USIC_CH_PSR_IISMode_WARE_Pos)                /*!< USIC_CH PSR_IISMode: WARE Mask          */\r
+#define USIC_CH_PSR_IISMode_END_Pos           6                                                       /*!< USIC_CH PSR_IISMode: END Position       */\r
+#define USIC_CH_PSR_IISMode_END_Msk           (0x01UL << USIC_CH_PSR_IISMode_END_Pos)                 /*!< USIC_CH PSR_IISMode: END Mask           */\r
+#define USIC_CH_PSR_IISMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_IISMode: RSIF Position      */\r
+#define USIC_CH_PSR_IISMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_RSIF_Pos)                /*!< USIC_CH PSR_IISMode: RSIF Mask          */\r
+#define USIC_CH_PSR_IISMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_IISMode: DLIF Position      */\r
+#define USIC_CH_PSR_IISMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_DLIF_Pos)                /*!< USIC_CH PSR_IISMode: DLIF Mask          */\r
+#define USIC_CH_PSR_IISMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_IISMode: TSIF Position      */\r
+#define USIC_CH_PSR_IISMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_TSIF_Pos)                /*!< USIC_CH PSR_IISMode: TSIF Mask          */\r
+#define USIC_CH_PSR_IISMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_IISMode: TBIF Position      */\r
+#define USIC_CH_PSR_IISMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_TBIF_Pos)                /*!< USIC_CH PSR_IISMode: TBIF Mask          */\r
+#define USIC_CH_PSR_IISMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_IISMode: RIF Position       */\r
+#define USIC_CH_PSR_IISMode_RIF_Msk           (0x01UL << USIC_CH_PSR_IISMode_RIF_Pos)                 /*!< USIC_CH PSR_IISMode: RIF Mask           */\r
+#define USIC_CH_PSR_IISMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_IISMode: AIF Position       */\r
+#define USIC_CH_PSR_IISMode_AIF_Msk           (0x01UL << USIC_CH_PSR_IISMode_AIF_Pos)                 /*!< USIC_CH PSR_IISMode: AIF Mask           */\r
+#define USIC_CH_PSR_IISMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_IISMode: BRGIF Position     */\r
+#define USIC_CH_PSR_IISMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_IISMode_BRGIF_Pos)               /*!< USIC_CH PSR_IISMode: BRGIF Mask         */\r
+\r
+/* --------------------------------  USIC_CH_PSCR  -------------------------------- */\r
+#define USIC_CH_PSCR_CST0_Pos                 0                                                       /*!< USIC_CH PSCR: CST0 Position             */\r
+#define USIC_CH_PSCR_CST0_Msk                 (0x01UL << USIC_CH_PSCR_CST0_Pos)                       /*!< USIC_CH PSCR: CST0 Mask                 */\r
+#define USIC_CH_PSCR_CST1_Pos                 1                                                       /*!< USIC_CH PSCR: CST1 Position             */\r
+#define USIC_CH_PSCR_CST1_Msk                 (0x01UL << USIC_CH_PSCR_CST1_Pos)                       /*!< USIC_CH PSCR: CST1 Mask                 */\r
+#define USIC_CH_PSCR_CST2_Pos                 2                                                       /*!< USIC_CH PSCR: CST2 Position             */\r
+#define USIC_CH_PSCR_CST2_Msk                 (0x01UL << USIC_CH_PSCR_CST2_Pos)                       /*!< USIC_CH PSCR: CST2 Mask                 */\r
+#define USIC_CH_PSCR_CST3_Pos                 3                                                       /*!< USIC_CH PSCR: CST3 Position             */\r
+#define USIC_CH_PSCR_CST3_Msk                 (0x01UL << USIC_CH_PSCR_CST3_Pos)                       /*!< USIC_CH PSCR: CST3 Mask                 */\r
+#define USIC_CH_PSCR_CST4_Pos                 4                                                       /*!< USIC_CH PSCR: CST4 Position             */\r
+#define USIC_CH_PSCR_CST4_Msk                 (0x01UL << USIC_CH_PSCR_CST4_Pos)                       /*!< USIC_CH PSCR: CST4 Mask                 */\r
+#define USIC_CH_PSCR_CST5_Pos                 5                                                       /*!< USIC_CH PSCR: CST5 Position             */\r
+#define USIC_CH_PSCR_CST5_Msk                 (0x01UL << USIC_CH_PSCR_CST5_Pos)                       /*!< USIC_CH PSCR: CST5 Mask                 */\r
+#define USIC_CH_PSCR_CST6_Pos                 6                                                       /*!< USIC_CH PSCR: CST6 Position             */\r
+#define USIC_CH_PSCR_CST6_Msk                 (0x01UL << USIC_CH_PSCR_CST6_Pos)                       /*!< USIC_CH PSCR: CST6 Mask                 */\r
+#define USIC_CH_PSCR_CST7_Pos                 7                                                       /*!< USIC_CH PSCR: CST7 Position             */\r
+#define USIC_CH_PSCR_CST7_Msk                 (0x01UL << USIC_CH_PSCR_CST7_Pos)                       /*!< USIC_CH PSCR: CST7 Mask                 */\r
+#define USIC_CH_PSCR_CST8_Pos                 8                                                       /*!< USIC_CH PSCR: CST8 Position             */\r
+#define USIC_CH_PSCR_CST8_Msk                 (0x01UL << USIC_CH_PSCR_CST8_Pos)                       /*!< USIC_CH PSCR: CST8 Mask                 */\r
+#define USIC_CH_PSCR_CST9_Pos                 9                                                       /*!< USIC_CH PSCR: CST9 Position             */\r
+#define USIC_CH_PSCR_CST9_Msk                 (0x01UL << USIC_CH_PSCR_CST9_Pos)                       /*!< USIC_CH PSCR: CST9 Mask                 */\r
+#define USIC_CH_PSCR_CRSIF_Pos                10                                                      /*!< USIC_CH PSCR: CRSIF Position            */\r
+#define USIC_CH_PSCR_CRSIF_Msk                (0x01UL << USIC_CH_PSCR_CRSIF_Pos)                      /*!< USIC_CH PSCR: CRSIF Mask                */\r
+#define USIC_CH_PSCR_CDLIF_Pos                11                                                      /*!< USIC_CH PSCR: CDLIF Position            */\r
+#define USIC_CH_PSCR_CDLIF_Msk                (0x01UL << USIC_CH_PSCR_CDLIF_Pos)                      /*!< USIC_CH PSCR: CDLIF Mask                */\r
+#define USIC_CH_PSCR_CTSIF_Pos                12                                                      /*!< USIC_CH PSCR: CTSIF Position            */\r
+#define USIC_CH_PSCR_CTSIF_Msk                (0x01UL << USIC_CH_PSCR_CTSIF_Pos)                      /*!< USIC_CH PSCR: CTSIF Mask                */\r
+#define USIC_CH_PSCR_CTBIF_Pos                13                                                      /*!< USIC_CH PSCR: CTBIF Position            */\r
+#define USIC_CH_PSCR_CTBIF_Msk                (0x01UL << USIC_CH_PSCR_CTBIF_Pos)                      /*!< USIC_CH PSCR: CTBIF Mask                */\r
+#define USIC_CH_PSCR_CRIF_Pos                 14                                                      /*!< USIC_CH PSCR: CRIF Position             */\r
+#define USIC_CH_PSCR_CRIF_Msk                 (0x01UL << USIC_CH_PSCR_CRIF_Pos)                       /*!< USIC_CH PSCR: CRIF Mask                 */\r
+#define USIC_CH_PSCR_CAIF_Pos                 15                                                      /*!< USIC_CH PSCR: CAIF Position             */\r
+#define USIC_CH_PSCR_CAIF_Msk                 (0x01UL << USIC_CH_PSCR_CAIF_Pos)                       /*!< USIC_CH PSCR: CAIF Mask                 */\r
+#define USIC_CH_PSCR_CBRGIF_Pos               16                                                      /*!< USIC_CH PSCR: CBRGIF Position           */\r
+#define USIC_CH_PSCR_CBRGIF_Msk               (0x01UL << USIC_CH_PSCR_CBRGIF_Pos)                     /*!< USIC_CH PSCR: CBRGIF Mask               */\r
+\r
+/* -------------------------------  USIC_CH_RBUFSR  ------------------------------- */\r
+#define USIC_CH_RBUFSR_WLEN_Pos               0                                                       /*!< USIC_CH RBUFSR: WLEN Position           */\r
+#define USIC_CH_RBUFSR_WLEN_Msk               (0x0fUL << USIC_CH_RBUFSR_WLEN_Pos)                     /*!< USIC_CH RBUFSR: WLEN Mask               */\r
+#define USIC_CH_RBUFSR_SOF_Pos                6                                                       /*!< USIC_CH RBUFSR: SOF Position            */\r
+#define USIC_CH_RBUFSR_SOF_Msk                (0x01UL << USIC_CH_RBUFSR_SOF_Pos)                      /*!< USIC_CH RBUFSR: SOF Mask                */\r
+#define USIC_CH_RBUFSR_PAR_Pos                8                                                       /*!< USIC_CH RBUFSR: PAR Position            */\r
+#define USIC_CH_RBUFSR_PAR_Msk                (0x01UL << USIC_CH_RBUFSR_PAR_Pos)                      /*!< USIC_CH RBUFSR: PAR Mask                */\r
+#define USIC_CH_RBUFSR_PERR_Pos               9                                                       /*!< USIC_CH RBUFSR: PERR Position           */\r
+#define USIC_CH_RBUFSR_PERR_Msk               (0x01UL << USIC_CH_RBUFSR_PERR_Pos)                     /*!< USIC_CH RBUFSR: PERR Mask               */\r
+#define USIC_CH_RBUFSR_RDV0_Pos               13                                                      /*!< USIC_CH RBUFSR: RDV0 Position           */\r
+#define USIC_CH_RBUFSR_RDV0_Msk               (0x01UL << USIC_CH_RBUFSR_RDV0_Pos)                     /*!< USIC_CH RBUFSR: RDV0 Mask               */\r
+#define USIC_CH_RBUFSR_RDV1_Pos               14                                                      /*!< USIC_CH RBUFSR: RDV1 Position           */\r
+#define USIC_CH_RBUFSR_RDV1_Msk               (0x01UL << USIC_CH_RBUFSR_RDV1_Pos)                     /*!< USIC_CH RBUFSR: RDV1 Mask               */\r
+#define USIC_CH_RBUFSR_DS_Pos                 15                                                      /*!< USIC_CH RBUFSR: DS Position             */\r
+#define USIC_CH_RBUFSR_DS_Msk                 (0x01UL << USIC_CH_RBUFSR_DS_Pos)                       /*!< USIC_CH RBUFSR: DS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_RBUF  -------------------------------- */\r
+#define USIC_CH_RBUF_DSR_Pos                  0                                                       /*!< USIC_CH RBUF: DSR Position              */\r
+#define USIC_CH_RBUF_DSR_Msk                  (0x0000ffffUL << USIC_CH_RBUF_DSR_Pos)                  /*!< USIC_CH RBUF: DSR Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_RBUFD  ------------------------------- */\r
+#define USIC_CH_RBUFD_DSR_Pos                 0                                                       /*!< USIC_CH RBUFD: DSR Position             */\r
+#define USIC_CH_RBUFD_DSR_Msk                 (0x0000ffffUL << USIC_CH_RBUFD_DSR_Pos)                 /*!< USIC_CH RBUFD: DSR Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_RBUF0  ------------------------------- */\r
+#define USIC_CH_RBUF0_DSR0_Pos                0                                                       /*!< USIC_CH RBUF0: DSR0 Position            */\r
+#define USIC_CH_RBUF0_DSR0_Msk                (0x0000ffffUL << USIC_CH_RBUF0_DSR0_Pos)                /*!< USIC_CH RBUF0: DSR0 Mask                */\r
+\r
+/* --------------------------------  USIC_CH_RBUF1  ------------------------------- */\r
+#define USIC_CH_RBUF1_DSR1_Pos                0                                                       /*!< USIC_CH RBUF1: DSR1 Position            */\r
+#define USIC_CH_RBUF1_DSR1_Msk                (0x0000ffffUL << USIC_CH_RBUF1_DSR1_Pos)                /*!< USIC_CH RBUF1: DSR1 Mask                */\r
+\r
+/* ------------------------------  USIC_CH_RBUF01SR  ------------------------------ */\r
+#define USIC_CH_RBUF01SR_WLEN0_Pos            0                                                       /*!< USIC_CH RBUF01SR: WLEN0 Position        */\r
+#define USIC_CH_RBUF01SR_WLEN0_Msk            (0x0fUL << USIC_CH_RBUF01SR_WLEN0_Pos)                  /*!< USIC_CH RBUF01SR: WLEN0 Mask            */\r
+#define USIC_CH_RBUF01SR_SOF0_Pos             6                                                       /*!< USIC_CH RBUF01SR: SOF0 Position         */\r
+#define USIC_CH_RBUF01SR_SOF0_Msk             (0x01UL << USIC_CH_RBUF01SR_SOF0_Pos)                   /*!< USIC_CH RBUF01SR: SOF0 Mask             */\r
+#define USIC_CH_RBUF01SR_PAR0_Pos             8                                                       /*!< USIC_CH RBUF01SR: PAR0 Position         */\r
+#define USIC_CH_RBUF01SR_PAR0_Msk             (0x01UL << USIC_CH_RBUF01SR_PAR0_Pos)                   /*!< USIC_CH RBUF01SR: PAR0 Mask             */\r
+#define USIC_CH_RBUF01SR_PERR0_Pos            9                                                       /*!< USIC_CH RBUF01SR: PERR0 Position        */\r
+#define USIC_CH_RBUF01SR_PERR0_Msk            (0x01UL << USIC_CH_RBUF01SR_PERR0_Pos)                  /*!< USIC_CH RBUF01SR: PERR0 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV00_Pos            13                                                      /*!< USIC_CH RBUF01SR: RDV00 Position        */\r
+#define USIC_CH_RBUF01SR_RDV00_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV00_Pos)                  /*!< USIC_CH RBUF01SR: RDV00 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV01_Pos            14                                                      /*!< USIC_CH RBUF01SR: RDV01 Position        */\r
+#define USIC_CH_RBUF01SR_RDV01_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV01_Pos)                  /*!< USIC_CH RBUF01SR: RDV01 Mask            */\r
+#define USIC_CH_RBUF01SR_DS0_Pos              15                                                      /*!< USIC_CH RBUF01SR: DS0 Position          */\r
+#define USIC_CH_RBUF01SR_DS0_Msk              (0x01UL << USIC_CH_RBUF01SR_DS0_Pos)                    /*!< USIC_CH RBUF01SR: DS0 Mask              */\r
+#define USIC_CH_RBUF01SR_WLEN1_Pos            16                                                      /*!< USIC_CH RBUF01SR: WLEN1 Position        */\r
+#define USIC_CH_RBUF01SR_WLEN1_Msk            (0x0fUL << USIC_CH_RBUF01SR_WLEN1_Pos)                  /*!< USIC_CH RBUF01SR: WLEN1 Mask            */\r
+#define USIC_CH_RBUF01SR_SOF1_Pos             22                                                      /*!< USIC_CH RBUF01SR: SOF1 Position         */\r
+#define USIC_CH_RBUF01SR_SOF1_Msk             (0x01UL << USIC_CH_RBUF01SR_SOF1_Pos)                   /*!< USIC_CH RBUF01SR: SOF1 Mask             */\r
+#define USIC_CH_RBUF01SR_PAR1_Pos             24                                                      /*!< USIC_CH RBUF01SR: PAR1 Position         */\r
+#define USIC_CH_RBUF01SR_PAR1_Msk             (0x01UL << USIC_CH_RBUF01SR_PAR1_Pos)                   /*!< USIC_CH RBUF01SR: PAR1 Mask             */\r
+#define USIC_CH_RBUF01SR_PERR1_Pos            25                                                      /*!< USIC_CH RBUF01SR: PERR1 Position        */\r
+#define USIC_CH_RBUF01SR_PERR1_Msk            (0x01UL << USIC_CH_RBUF01SR_PERR1_Pos)                  /*!< USIC_CH RBUF01SR: PERR1 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV10_Pos            29                                                      /*!< USIC_CH RBUF01SR: RDV10 Position        */\r
+#define USIC_CH_RBUF01SR_RDV10_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV10_Pos)                  /*!< USIC_CH RBUF01SR: RDV10 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV11_Pos            30                                                      /*!< USIC_CH RBUF01SR: RDV11 Position        */\r
+#define USIC_CH_RBUF01SR_RDV11_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV11_Pos)                  /*!< USIC_CH RBUF01SR: RDV11 Mask            */\r
+#define USIC_CH_RBUF01SR_DS1_Pos              31                                                      /*!< USIC_CH RBUF01SR: DS1 Position          */\r
+#define USIC_CH_RBUF01SR_DS1_Msk              (0x01UL << USIC_CH_RBUF01SR_DS1_Pos)                    /*!< USIC_CH RBUF01SR: DS1 Mask              */\r
+\r
+/* ---------------------------------  USIC_CH_FMR  -------------------------------- */\r
+#define USIC_CH_FMR_MTDV_Pos                  0                                                       /*!< USIC_CH FMR: MTDV Position              */\r
+#define USIC_CH_FMR_MTDV_Msk                  (0x03UL << USIC_CH_FMR_MTDV_Pos)                        /*!< USIC_CH FMR: MTDV Mask                  */\r
+#define USIC_CH_FMR_ATVC_Pos                  4                                                       /*!< USIC_CH FMR: ATVC Position              */\r
+#define USIC_CH_FMR_ATVC_Msk                  (0x01UL << USIC_CH_FMR_ATVC_Pos)                        /*!< USIC_CH FMR: ATVC Mask                  */\r
+#define USIC_CH_FMR_CRDV0_Pos                 14                                                      /*!< USIC_CH FMR: CRDV0 Position             */\r
+#define USIC_CH_FMR_CRDV0_Msk                 (0x01UL << USIC_CH_FMR_CRDV0_Pos)                       /*!< USIC_CH FMR: CRDV0 Mask                 */\r
+#define USIC_CH_FMR_CRDV1_Pos                 15                                                      /*!< USIC_CH FMR: CRDV1 Position             */\r
+#define USIC_CH_FMR_CRDV1_Msk                 (0x01UL << USIC_CH_FMR_CRDV1_Pos)                       /*!< USIC_CH FMR: CRDV1 Mask                 */\r
+#define USIC_CH_FMR_SIO0_Pos                  16                                                      /*!< USIC_CH FMR: SIO0 Position              */\r
+#define USIC_CH_FMR_SIO0_Msk                  (0x01UL << USIC_CH_FMR_SIO0_Pos)                        /*!< USIC_CH FMR: SIO0 Mask                  */\r
+#define USIC_CH_FMR_SIO1_Pos                  17                                                      /*!< USIC_CH FMR: SIO1 Position              */\r
+#define USIC_CH_FMR_SIO1_Msk                  (0x01UL << USIC_CH_FMR_SIO1_Pos)                        /*!< USIC_CH FMR: SIO1 Mask                  */\r
+#define USIC_CH_FMR_SIO2_Pos                  18                                                      /*!< USIC_CH FMR: SIO2 Position              */\r
+#define USIC_CH_FMR_SIO2_Msk                  (0x01UL << USIC_CH_FMR_SIO2_Pos)                        /*!< USIC_CH FMR: SIO2 Mask                  */\r
+#define USIC_CH_FMR_SIO3_Pos                  19                                                      /*!< USIC_CH FMR: SIO3 Position              */\r
+#define USIC_CH_FMR_SIO3_Msk                  (0x01UL << USIC_CH_FMR_SIO3_Pos)                        /*!< USIC_CH FMR: SIO3 Mask                  */\r
+#define USIC_CH_FMR_SIO4_Pos                  20                                                      /*!< USIC_CH FMR: SIO4 Position              */\r
+#define USIC_CH_FMR_SIO4_Msk                  (0x01UL << USIC_CH_FMR_SIO4_Pos)                        /*!< USIC_CH FMR: SIO4 Mask                  */\r
+#define USIC_CH_FMR_SIO5_Pos                  21                                                      /*!< USIC_CH FMR: SIO5 Position              */\r
+#define USIC_CH_FMR_SIO5_Msk                  (0x01UL << USIC_CH_FMR_SIO5_Pos)                        /*!< USIC_CH FMR: SIO5 Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_TBUF  -------------------------------- */\r
+#define USIC_CH_TBUF_TDATA_Pos                0                                                       /*!< USIC_CH TBUF: TDATA Position            */\r
+#define USIC_CH_TBUF_TDATA_Msk                (0x0000ffffUL << USIC_CH_TBUF_TDATA_Pos)                /*!< USIC_CH TBUF: TDATA Mask                */\r
+\r
+/* ---------------------------------  USIC_CH_BYP  -------------------------------- */\r
+#define USIC_CH_BYP_BDATA_Pos                 0                                                       /*!< USIC_CH BYP: BDATA Position             */\r
+#define USIC_CH_BYP_BDATA_Msk                 (0x0000ffffUL << USIC_CH_BYP_BDATA_Pos)                 /*!< USIC_CH BYP: BDATA Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_BYPCR  ------------------------------- */\r
+#define USIC_CH_BYPCR_BWLE_Pos                0                                                       /*!< USIC_CH BYPCR: BWLE Position            */\r
+#define USIC_CH_BYPCR_BWLE_Msk                (0x0fUL << USIC_CH_BYPCR_BWLE_Pos)                      /*!< USIC_CH BYPCR: BWLE Mask                */\r
+#define USIC_CH_BYPCR_BDSSM_Pos               8                                                       /*!< USIC_CH BYPCR: BDSSM Position           */\r
+#define USIC_CH_BYPCR_BDSSM_Msk               (0x01UL << USIC_CH_BYPCR_BDSSM_Pos)                     /*!< USIC_CH BYPCR: BDSSM Mask               */\r
+#define USIC_CH_BYPCR_BDEN_Pos                10                                                      /*!< USIC_CH BYPCR: BDEN Position            */\r
+#define USIC_CH_BYPCR_BDEN_Msk                (0x03UL << USIC_CH_BYPCR_BDEN_Pos)                      /*!< USIC_CH BYPCR: BDEN Mask                */\r
+#define USIC_CH_BYPCR_BDVTR_Pos               12                                                      /*!< USIC_CH BYPCR: BDVTR Position           */\r
+#define USIC_CH_BYPCR_BDVTR_Msk               (0x01UL << USIC_CH_BYPCR_BDVTR_Pos)                     /*!< USIC_CH BYPCR: BDVTR Mask               */\r
+#define USIC_CH_BYPCR_BPRIO_Pos               13                                                      /*!< USIC_CH BYPCR: BPRIO Position           */\r
+#define USIC_CH_BYPCR_BPRIO_Msk               (0x01UL << USIC_CH_BYPCR_BPRIO_Pos)                     /*!< USIC_CH BYPCR: BPRIO Mask               */\r
+#define USIC_CH_BYPCR_BDV_Pos                 15                                                      /*!< USIC_CH BYPCR: BDV Position             */\r
+#define USIC_CH_BYPCR_BDV_Msk                 (0x01UL << USIC_CH_BYPCR_BDV_Pos)                       /*!< USIC_CH BYPCR: BDV Mask                 */\r
+#define USIC_CH_BYPCR_BSELO_Pos               16                                                      /*!< USIC_CH BYPCR: BSELO Position           */\r
+#define USIC_CH_BYPCR_BSELO_Msk               (0x1fUL << USIC_CH_BYPCR_BSELO_Pos)                     /*!< USIC_CH BYPCR: BSELO Mask               */\r
+#define USIC_CH_BYPCR_BHPC_Pos                21                                                      /*!< USIC_CH BYPCR: BHPC Position            */\r
+#define USIC_CH_BYPCR_BHPC_Msk                (0x07UL << USIC_CH_BYPCR_BHPC_Pos)                      /*!< USIC_CH BYPCR: BHPC Mask                */\r
+\r
+/* --------------------------------  USIC_CH_TBCTR  ------------------------------- */\r
+#define USIC_CH_TBCTR_DPTR_Pos                0                                                       /*!< USIC_CH TBCTR: DPTR Position            */\r
+#define USIC_CH_TBCTR_DPTR_Msk                (0x3fUL << USIC_CH_TBCTR_DPTR_Pos)                      /*!< USIC_CH TBCTR: DPTR Mask                */\r
+#define USIC_CH_TBCTR_LIMIT_Pos               8                                                       /*!< USIC_CH TBCTR: LIMIT Position           */\r
+#define USIC_CH_TBCTR_LIMIT_Msk               (0x3fUL << USIC_CH_TBCTR_LIMIT_Pos)                     /*!< USIC_CH TBCTR: LIMIT Mask               */\r
+#define USIC_CH_TBCTR_STBTM_Pos               14                                                      /*!< USIC_CH TBCTR: STBTM Position           */\r
+#define USIC_CH_TBCTR_STBTM_Msk               (0x01UL << USIC_CH_TBCTR_STBTM_Pos)                     /*!< USIC_CH TBCTR: STBTM Mask               */\r
+#define USIC_CH_TBCTR_STBTEN_Pos              15                                                      /*!< USIC_CH TBCTR: STBTEN Position          */\r
+#define USIC_CH_TBCTR_STBTEN_Msk              (0x01UL << USIC_CH_TBCTR_STBTEN_Pos)                    /*!< USIC_CH TBCTR: STBTEN Mask              */\r
+#define USIC_CH_TBCTR_STBINP_Pos              16                                                      /*!< USIC_CH TBCTR: STBINP Position          */\r
+#define USIC_CH_TBCTR_STBINP_Msk              (0x07UL << USIC_CH_TBCTR_STBINP_Pos)                    /*!< USIC_CH TBCTR: STBINP Mask              */\r
+#define USIC_CH_TBCTR_ATBINP_Pos              19                                                      /*!< USIC_CH TBCTR: ATBINP Position          */\r
+#define USIC_CH_TBCTR_ATBINP_Msk              (0x07UL << USIC_CH_TBCTR_ATBINP_Pos)                    /*!< USIC_CH TBCTR: ATBINP Mask              */\r
+#define USIC_CH_TBCTR_SIZE_Pos                24                                                      /*!< USIC_CH TBCTR: SIZE Position            */\r
+#define USIC_CH_TBCTR_SIZE_Msk                (0x07UL << USIC_CH_TBCTR_SIZE_Pos)                      /*!< USIC_CH TBCTR: SIZE Mask                */\r
+#define USIC_CH_TBCTR_LOF_Pos                 28                                                      /*!< USIC_CH TBCTR: LOF Position             */\r
+#define USIC_CH_TBCTR_LOF_Msk                 (0x01UL << USIC_CH_TBCTR_LOF_Pos)                       /*!< USIC_CH TBCTR: LOF Mask                 */\r
+#define USIC_CH_TBCTR_STBIEN_Pos              30                                                      /*!< USIC_CH TBCTR: STBIEN Position          */\r
+#define USIC_CH_TBCTR_STBIEN_Msk              (0x01UL << USIC_CH_TBCTR_STBIEN_Pos)                    /*!< USIC_CH TBCTR: STBIEN Mask              */\r
+#define USIC_CH_TBCTR_TBERIEN_Pos             31                                                      /*!< USIC_CH TBCTR: TBERIEN Position         */\r
+#define USIC_CH_TBCTR_TBERIEN_Msk             (0x01UL << USIC_CH_TBCTR_TBERIEN_Pos)                   /*!< USIC_CH TBCTR: TBERIEN Mask             */\r
+\r
+/* --------------------------------  USIC_CH_RBCTR  ------------------------------- */\r
+#define USIC_CH_RBCTR_DPTR_Pos                0                                                       /*!< USIC_CH RBCTR: DPTR Position            */\r
+#define USIC_CH_RBCTR_DPTR_Msk                (0x3fUL << USIC_CH_RBCTR_DPTR_Pos)                      /*!< USIC_CH RBCTR: DPTR Mask                */\r
+#define USIC_CH_RBCTR_LIMIT_Pos               8                                                       /*!< USIC_CH RBCTR: LIMIT Position           */\r
+#define USIC_CH_RBCTR_LIMIT_Msk               (0x3fUL << USIC_CH_RBCTR_LIMIT_Pos)                     /*!< USIC_CH RBCTR: LIMIT Mask               */\r
+#define USIC_CH_RBCTR_SRBTM_Pos               14                                                      /*!< USIC_CH RBCTR: SRBTM Position           */\r
+#define USIC_CH_RBCTR_SRBTM_Msk               (0x01UL << USIC_CH_RBCTR_SRBTM_Pos)                     /*!< USIC_CH RBCTR: SRBTM Mask               */\r
+#define USIC_CH_RBCTR_SRBTEN_Pos              15                                                      /*!< USIC_CH RBCTR: SRBTEN Position          */\r
+#define USIC_CH_RBCTR_SRBTEN_Msk              (0x01UL << USIC_CH_RBCTR_SRBTEN_Pos)                    /*!< USIC_CH RBCTR: SRBTEN Mask              */\r
+#define USIC_CH_RBCTR_SRBINP_Pos              16                                                      /*!< USIC_CH RBCTR: SRBINP Position          */\r
+#define USIC_CH_RBCTR_SRBINP_Msk              (0x07UL << USIC_CH_RBCTR_SRBINP_Pos)                    /*!< USIC_CH RBCTR: SRBINP Mask              */\r
+#define USIC_CH_RBCTR_ARBINP_Pos              19                                                      /*!< USIC_CH RBCTR: ARBINP Position          */\r
+#define USIC_CH_RBCTR_ARBINP_Msk              (0x07UL << USIC_CH_RBCTR_ARBINP_Pos)                    /*!< USIC_CH RBCTR: ARBINP Mask              */\r
+#define USIC_CH_RBCTR_RCIM_Pos                22                                                      /*!< USIC_CH RBCTR: RCIM Position            */\r
+#define USIC_CH_RBCTR_RCIM_Msk                (0x03UL << USIC_CH_RBCTR_RCIM_Pos)                      /*!< USIC_CH RBCTR: RCIM Mask                */\r
+#define USIC_CH_RBCTR_SIZE_Pos                24                                                      /*!< USIC_CH RBCTR: SIZE Position            */\r
+#define USIC_CH_RBCTR_SIZE_Msk                (0x07UL << USIC_CH_RBCTR_SIZE_Pos)                      /*!< USIC_CH RBCTR: SIZE Mask                */\r
+#define USIC_CH_RBCTR_RNM_Pos                 27                                                      /*!< USIC_CH RBCTR: RNM Position             */\r
+#define USIC_CH_RBCTR_RNM_Msk                 (0x01UL << USIC_CH_RBCTR_RNM_Pos)                       /*!< USIC_CH RBCTR: RNM Mask                 */\r
+#define USIC_CH_RBCTR_LOF_Pos                 28                                                      /*!< USIC_CH RBCTR: LOF Position             */\r
+#define USIC_CH_RBCTR_LOF_Msk                 (0x01UL << USIC_CH_RBCTR_LOF_Pos)                       /*!< USIC_CH RBCTR: LOF Mask                 */\r
+#define USIC_CH_RBCTR_ARBIEN_Pos              29                                                      /*!< USIC_CH RBCTR: ARBIEN Position          */\r
+#define USIC_CH_RBCTR_ARBIEN_Msk              (0x01UL << USIC_CH_RBCTR_ARBIEN_Pos)                    /*!< USIC_CH RBCTR: ARBIEN Mask              */\r
+#define USIC_CH_RBCTR_SRBIEN_Pos              30                                                      /*!< USIC_CH RBCTR: SRBIEN Position          */\r
+#define USIC_CH_RBCTR_SRBIEN_Msk              (0x01UL << USIC_CH_RBCTR_SRBIEN_Pos)                    /*!< USIC_CH RBCTR: SRBIEN Mask              */\r
+#define USIC_CH_RBCTR_RBERIEN_Pos             31                                                      /*!< USIC_CH RBCTR: RBERIEN Position         */\r
+#define USIC_CH_RBCTR_RBERIEN_Msk             (0x01UL << USIC_CH_RBCTR_RBERIEN_Pos)                   /*!< USIC_CH RBCTR: RBERIEN Mask             */\r
+\r
+/* -------------------------------  USIC_CH_TRBPTR  ------------------------------- */\r
+#define USIC_CH_TRBPTR_TDIPTR_Pos             0                                                       /*!< USIC_CH TRBPTR: TDIPTR Position         */\r
+#define USIC_CH_TRBPTR_TDIPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_TDIPTR_Pos)                   /*!< USIC_CH TRBPTR: TDIPTR Mask             */\r
+#define USIC_CH_TRBPTR_TDOPTR_Pos             8                                                       /*!< USIC_CH TRBPTR: TDOPTR Position         */\r
+#define USIC_CH_TRBPTR_TDOPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_TDOPTR_Pos)                   /*!< USIC_CH TRBPTR: TDOPTR Mask             */\r
+#define USIC_CH_TRBPTR_RDIPTR_Pos             16                                                      /*!< USIC_CH TRBPTR: RDIPTR Position         */\r
+#define USIC_CH_TRBPTR_RDIPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_RDIPTR_Pos)                   /*!< USIC_CH TRBPTR: RDIPTR Mask             */\r
+#define USIC_CH_TRBPTR_RDOPTR_Pos             24                                                      /*!< USIC_CH TRBPTR: RDOPTR Position         */\r
+#define USIC_CH_TRBPTR_RDOPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_RDOPTR_Pos)                   /*!< USIC_CH TRBPTR: RDOPTR Mask             */\r
+\r
+/* --------------------------------  USIC_CH_TRBSR  ------------------------------- */\r
+#define USIC_CH_TRBSR_SRBI_Pos                0                                                       /*!< USIC_CH TRBSR: SRBI Position            */\r
+#define USIC_CH_TRBSR_SRBI_Msk                (0x01UL << USIC_CH_TRBSR_SRBI_Pos)                      /*!< USIC_CH TRBSR: SRBI Mask                */\r
+#define USIC_CH_TRBSR_RBERI_Pos               1                                                       /*!< USIC_CH TRBSR: RBERI Position           */\r
+#define USIC_CH_TRBSR_RBERI_Msk               (0x01UL << USIC_CH_TRBSR_RBERI_Pos)                     /*!< USIC_CH TRBSR: RBERI Mask               */\r
+#define USIC_CH_TRBSR_ARBI_Pos                2                                                       /*!< USIC_CH TRBSR: ARBI Position            */\r
+#define USIC_CH_TRBSR_ARBI_Msk                (0x01UL << USIC_CH_TRBSR_ARBI_Pos)                      /*!< USIC_CH TRBSR: ARBI Mask                */\r
+#define USIC_CH_TRBSR_REMPTY_Pos              3                                                       /*!< USIC_CH TRBSR: REMPTY Position          */\r
+#define USIC_CH_TRBSR_REMPTY_Msk              (0x01UL << USIC_CH_TRBSR_REMPTY_Pos)                    /*!< USIC_CH TRBSR: REMPTY Mask              */\r
+#define USIC_CH_TRBSR_RFULL_Pos               4                                                       /*!< USIC_CH TRBSR: RFULL Position           */\r
+#define USIC_CH_TRBSR_RFULL_Msk               (0x01UL << USIC_CH_TRBSR_RFULL_Pos)                     /*!< USIC_CH TRBSR: RFULL Mask               */\r
+#define USIC_CH_TRBSR_RBUS_Pos                5                                                       /*!< USIC_CH TRBSR: RBUS Position            */\r
+#define USIC_CH_TRBSR_RBUS_Msk                (0x01UL << USIC_CH_TRBSR_RBUS_Pos)                      /*!< USIC_CH TRBSR: RBUS Mask                */\r
+#define USIC_CH_TRBSR_SRBT_Pos                6                                                       /*!< USIC_CH TRBSR: SRBT Position            */\r
+#define USIC_CH_TRBSR_SRBT_Msk                (0x01UL << USIC_CH_TRBSR_SRBT_Pos)                      /*!< USIC_CH TRBSR: SRBT Mask                */\r
+#define USIC_CH_TRBSR_STBI_Pos                8                                                       /*!< USIC_CH TRBSR: STBI Position            */\r
+#define USIC_CH_TRBSR_STBI_Msk                (0x01UL << USIC_CH_TRBSR_STBI_Pos)                      /*!< USIC_CH TRBSR: STBI Mask                */\r
+#define USIC_CH_TRBSR_TBERI_Pos               9                                                       /*!< USIC_CH TRBSR: TBERI Position           */\r
+#define USIC_CH_TRBSR_TBERI_Msk               (0x01UL << USIC_CH_TRBSR_TBERI_Pos)                     /*!< USIC_CH TRBSR: TBERI Mask               */\r
+#define USIC_CH_TRBSR_TEMPTY_Pos              11                                                      /*!< USIC_CH TRBSR: TEMPTY Position          */\r
+#define USIC_CH_TRBSR_TEMPTY_Msk              (0x01UL << USIC_CH_TRBSR_TEMPTY_Pos)                    /*!< USIC_CH TRBSR: TEMPTY Mask              */\r
+#define USIC_CH_TRBSR_TFULL_Pos               12                                                      /*!< USIC_CH TRBSR: TFULL Position           */\r
+#define USIC_CH_TRBSR_TFULL_Msk               (0x01UL << USIC_CH_TRBSR_TFULL_Pos)                     /*!< USIC_CH TRBSR: TFULL Mask               */\r
+#define USIC_CH_TRBSR_TBUS_Pos                13                                                      /*!< USIC_CH TRBSR: TBUS Position            */\r
+#define USIC_CH_TRBSR_TBUS_Msk                (0x01UL << USIC_CH_TRBSR_TBUS_Pos)                      /*!< USIC_CH TRBSR: TBUS Mask                */\r
+#define USIC_CH_TRBSR_STBT_Pos                14                                                      /*!< USIC_CH TRBSR: STBT Position            */\r
+#define USIC_CH_TRBSR_STBT_Msk                (0x01UL << USIC_CH_TRBSR_STBT_Pos)                      /*!< USIC_CH TRBSR: STBT Mask                */\r
+#define USIC_CH_TRBSR_RBFLVL_Pos              16                                                      /*!< USIC_CH TRBSR: RBFLVL Position          */\r
+#define USIC_CH_TRBSR_RBFLVL_Msk              (0x7fUL << USIC_CH_TRBSR_RBFLVL_Pos)                    /*!< USIC_CH TRBSR: RBFLVL Mask              */\r
+#define USIC_CH_TRBSR_TBFLVL_Pos              24                                                      /*!< USIC_CH TRBSR: TBFLVL Position          */\r
+#define USIC_CH_TRBSR_TBFLVL_Msk              (0x7fUL << USIC_CH_TRBSR_TBFLVL_Pos)                    /*!< USIC_CH TRBSR: TBFLVL Mask              */\r
+\r
+/* -------------------------------  USIC_CH_TRBSCR  ------------------------------- */\r
+#define USIC_CH_TRBSCR_CSRBI_Pos              0                                                       /*!< USIC_CH TRBSCR: CSRBI Position          */\r
+#define USIC_CH_TRBSCR_CSRBI_Msk              (0x01UL << USIC_CH_TRBSCR_CSRBI_Pos)                    /*!< USIC_CH TRBSCR: CSRBI Mask              */\r
+#define USIC_CH_TRBSCR_CRBERI_Pos             1                                                       /*!< USIC_CH TRBSCR: CRBERI Position         */\r
+#define USIC_CH_TRBSCR_CRBERI_Msk             (0x01UL << USIC_CH_TRBSCR_CRBERI_Pos)                   /*!< USIC_CH TRBSCR: CRBERI Mask             */\r
+#define USIC_CH_TRBSCR_CARBI_Pos              2                                                       /*!< USIC_CH TRBSCR: CARBI Position          */\r
+#define USIC_CH_TRBSCR_CARBI_Msk              (0x01UL << USIC_CH_TRBSCR_CARBI_Pos)                    /*!< USIC_CH TRBSCR: CARBI Mask              */\r
+#define USIC_CH_TRBSCR_CSTBI_Pos              8                                                       /*!< USIC_CH TRBSCR: CSTBI Position          */\r
+#define USIC_CH_TRBSCR_CSTBI_Msk              (0x01UL << USIC_CH_TRBSCR_CSTBI_Pos)                    /*!< USIC_CH TRBSCR: CSTBI Mask              */\r
+#define USIC_CH_TRBSCR_CTBERI_Pos             9                                                       /*!< USIC_CH TRBSCR: CTBERI Position         */\r
+#define USIC_CH_TRBSCR_CTBERI_Msk             (0x01UL << USIC_CH_TRBSCR_CTBERI_Pos)                   /*!< USIC_CH TRBSCR: CTBERI Mask             */\r
+#define USIC_CH_TRBSCR_CBDV_Pos               10                                                      /*!< USIC_CH TRBSCR: CBDV Position           */\r
+#define USIC_CH_TRBSCR_CBDV_Msk               (0x01UL << USIC_CH_TRBSCR_CBDV_Pos)                     /*!< USIC_CH TRBSCR: CBDV Mask               */\r
+#define USIC_CH_TRBSCR_FLUSHRB_Pos            14                                                      /*!< USIC_CH TRBSCR: FLUSHRB Position        */\r
+#define USIC_CH_TRBSCR_FLUSHRB_Msk            (0x01UL << USIC_CH_TRBSCR_FLUSHRB_Pos)                  /*!< USIC_CH TRBSCR: FLUSHRB Mask            */\r
+#define USIC_CH_TRBSCR_FLUSHTB_Pos            15                                                      /*!< USIC_CH TRBSCR: FLUSHTB Position        */\r
+#define USIC_CH_TRBSCR_FLUSHTB_Msk            (0x01UL << USIC_CH_TRBSCR_FLUSHTB_Pos)                  /*!< USIC_CH TRBSCR: FLUSHTB Mask            */\r
+\r
+/* --------------------------------  USIC_CH_OUTR  -------------------------------- */\r
+#define USIC_CH_OUTR_DSR_Pos                  0                                                       /*!< USIC_CH OUTR: DSR Position              */\r
+#define USIC_CH_OUTR_DSR_Msk                  (0x0000ffffUL << USIC_CH_OUTR_DSR_Pos)                  /*!< USIC_CH OUTR: DSR Mask                  */\r
+#define USIC_CH_OUTR_RCI_Pos                  16                                                      /*!< USIC_CH OUTR: RCI Position              */\r
+#define USIC_CH_OUTR_RCI_Msk                  (0x1fUL << USIC_CH_OUTR_RCI_Pos)                        /*!< USIC_CH OUTR: RCI Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_OUTDR  ------------------------------- */\r
+#define USIC_CH_OUTDR_DSR_Pos                 0                                                       /*!< USIC_CH OUTDR: DSR Position             */\r
+#define USIC_CH_OUTDR_DSR_Msk                 (0x0000ffffUL << USIC_CH_OUTDR_DSR_Pos)                 /*!< USIC_CH OUTDR: DSR Mask                 */\r
+#define USIC_CH_OUTDR_RCI_Pos                 16                                                      /*!< USIC_CH OUTDR: RCI Position             */\r
+#define USIC_CH_OUTDR_RCI_Msk                 (0x1fUL << USIC_CH_OUTDR_RCI_Pos)                       /*!< USIC_CH OUTDR: RCI Mask                 */\r
+\r
+/* ---------------------------------  USIC_CH_IN  --------------------------------- */\r
+#define USIC_CH_IN_TDATA_Pos                  0                                                       /*!< USIC_CH IN: TDATA Position              */\r
+#define USIC_CH_IN_TDATA_Msk                  (0x0000ffffUL << USIC_CH_IN_TDATA_Pos)                  /*!< USIC_CH IN: TDATA Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'CAN' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  CAN_CLC  ---------------------------------- */\r
+#define CAN_CLC_DISR_Pos                      0                                                       /*!< CAN CLC: DISR Position                  */\r
+#define CAN_CLC_DISR_Msk                      (0x01UL << CAN_CLC_DISR_Pos)                            /*!< CAN CLC: DISR Mask                      */\r
+#define CAN_CLC_DISS_Pos                      1                                                       /*!< CAN CLC: DISS Position                  */\r
+#define CAN_CLC_DISS_Msk                      (0x01UL << CAN_CLC_DISS_Pos)                            /*!< CAN CLC: DISS Mask                      */\r
+#define CAN_CLC_EDIS_Pos                      3                                                       /*!< CAN CLC: EDIS Position                  */\r
+#define CAN_CLC_EDIS_Msk                      (0x01UL << CAN_CLC_EDIS_Pos)                            /*!< CAN CLC: EDIS Mask                      */\r
+#define CAN_CLC_SBWE_Pos                      4                                                       /*!< CAN CLC: SBWE Position                  */\r
+#define CAN_CLC_SBWE_Msk                      (0x01UL << CAN_CLC_SBWE_Pos)                            /*!< CAN CLC: SBWE Mask                      */\r
+\r
+/* -----------------------------------  CAN_ID  ----------------------------------- */\r
+#define CAN_ID_MOD_REV_Pos                    0                                                       /*!< CAN ID: MOD_REV Position                */\r
+#define CAN_ID_MOD_REV_Msk                    (0x000000ffUL << CAN_ID_MOD_REV_Pos)                    /*!< CAN ID: MOD_REV Mask                    */\r
+#define CAN_ID_MOD_TYPE_Pos                   8                                                       /*!< CAN ID: MOD_TYPE Position               */\r
+#define CAN_ID_MOD_TYPE_Msk                   (0x000000ffUL << CAN_ID_MOD_TYPE_Pos)                   /*!< CAN ID: MOD_TYPE Mask                   */\r
+#define CAN_ID_MOD_NUMBER_Pos                 16                                                      /*!< CAN ID: MOD_NUMBER Position             */\r
+#define CAN_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << CAN_ID_MOD_NUMBER_Pos)                 /*!< CAN ID: MOD_NUMBER Mask                 */\r
+\r
+/* -----------------------------------  CAN_FDR  ---------------------------------- */\r
+#define CAN_FDR_STEP_Pos                      0                                                       /*!< CAN FDR: STEP Position                  */\r
+#define CAN_FDR_STEP_Msk                      (0x000003ffUL << CAN_FDR_STEP_Pos)                      /*!< CAN FDR: STEP Mask                      */\r
+#define CAN_FDR_SM_Pos                        11                                                      /*!< CAN FDR: SM Position                    */\r
+#define CAN_FDR_SM_Msk                        (0x01UL << CAN_FDR_SM_Pos)                              /*!< CAN FDR: SM Mask                        */\r
+#define CAN_FDR_SC_Pos                        12                                                      /*!< CAN FDR: SC Position                    */\r
+#define CAN_FDR_SC_Msk                        (0x03UL << CAN_FDR_SC_Pos)                              /*!< CAN FDR: SC Mask                        */\r
+#define CAN_FDR_DM_Pos                        14                                                      /*!< CAN FDR: DM Position                    */\r
+#define CAN_FDR_DM_Msk                        (0x03UL << CAN_FDR_DM_Pos)                              /*!< CAN FDR: DM Mask                        */\r
+#define CAN_FDR_RESULT_Pos                    16                                                      /*!< CAN FDR: RESULT Position                */\r
+#define CAN_FDR_RESULT_Msk                    (0x000003ffUL << CAN_FDR_RESULT_Pos)                    /*!< CAN FDR: RESULT Mask                    */\r
+#define CAN_FDR_SUSACK_Pos                    28                                                      /*!< CAN FDR: SUSACK Position                */\r
+#define CAN_FDR_SUSACK_Msk                    (0x01UL << CAN_FDR_SUSACK_Pos)                          /*!< CAN FDR: SUSACK Mask                    */\r
+#define CAN_FDR_SUSREQ_Pos                    29                                                      /*!< CAN FDR: SUSREQ Position                */\r
+#define CAN_FDR_SUSREQ_Msk                    (0x01UL << CAN_FDR_SUSREQ_Pos)                          /*!< CAN FDR: SUSREQ Mask                    */\r
+#define CAN_FDR_ENHW_Pos                      30                                                      /*!< CAN FDR: ENHW Position                  */\r
+#define CAN_FDR_ENHW_Msk                      (0x01UL << CAN_FDR_ENHW_Pos)                            /*!< CAN FDR: ENHW Mask                      */\r
+#define CAN_FDR_DISCLK_Pos                    31                                                      /*!< CAN FDR: DISCLK Position                */\r
+#define CAN_FDR_DISCLK_Msk                    (0x01UL << CAN_FDR_DISCLK_Pos)                          /*!< CAN FDR: DISCLK Mask                    */\r
+\r
+/* ----------------------------------  CAN_LIST  ---------------------------------- */\r
+#define CAN_LIST_BEGIN_Pos                    0                                                       /*!< CAN LIST: BEGIN Position                */\r
+#define CAN_LIST_BEGIN_Msk                    (0x000000ffUL << CAN_LIST_BEGIN_Pos)                    /*!< CAN LIST: BEGIN Mask                    */\r
+#define CAN_LIST_END_Pos                      8                                                       /*!< CAN LIST: END Position                  */\r
+#define CAN_LIST_END_Msk                      (0x000000ffUL << CAN_LIST_END_Pos)                      /*!< CAN LIST: END Mask                      */\r
+#define CAN_LIST_SIZE_Pos                     16                                                      /*!< CAN LIST: SIZE Position                 */\r
+#define CAN_LIST_SIZE_Msk                     (0x000000ffUL << CAN_LIST_SIZE_Pos)                     /*!< CAN LIST: SIZE Mask                     */\r
+#define CAN_LIST_EMPTY_Pos                    24                                                      /*!< CAN LIST: EMPTY Position                */\r
+#define CAN_LIST_EMPTY_Msk                    (0x01UL << CAN_LIST_EMPTY_Pos)                          /*!< CAN LIST: EMPTY Mask                    */\r
+\r
+/* ----------------------------------  CAN_MSPND  --------------------------------- */\r
+#define CAN_MSPND_PND_Pos                     0                                                       /*!< CAN MSPND: PND Position                 */\r
+#define CAN_MSPND_PND_Msk                     (0xffffffffUL << CAN_MSPND_PND_Pos)                     /*!< CAN MSPND: PND Mask                     */\r
+\r
+/* ----------------------------------  CAN_MSID  ---------------------------------- */\r
+#define CAN_MSID_INDEX_Pos                    0                                                       /*!< CAN MSID: INDEX Position                */\r
+#define CAN_MSID_INDEX_Msk                    (0x3fUL << CAN_MSID_INDEX_Pos)                          /*!< CAN MSID: INDEX Mask                    */\r
+\r
+/* ---------------------------------  CAN_MSIMASK  -------------------------------- */\r
+#define CAN_MSIMASK_IM_Pos                    0                                                       /*!< CAN MSIMASK: IM Position                */\r
+#define CAN_MSIMASK_IM_Msk                    (0xffffffffUL << CAN_MSIMASK_IM_Pos)                    /*!< CAN MSIMASK: IM Mask                    */\r
+\r
+/* ---------------------------------  CAN_PANCTR  --------------------------------- */\r
+#define CAN_PANCTR_PANCMD_Pos                 0                                                       /*!< CAN PANCTR: PANCMD Position             */\r
+#define CAN_PANCTR_PANCMD_Msk                 (0x000000ffUL << CAN_PANCTR_PANCMD_Pos)                 /*!< CAN PANCTR: PANCMD Mask                 */\r
+#define CAN_PANCTR_BUSY_Pos                   8                                                       /*!< CAN PANCTR: BUSY Position               */\r
+#define CAN_PANCTR_BUSY_Msk                   (0x01UL << CAN_PANCTR_BUSY_Pos)                         /*!< CAN PANCTR: BUSY Mask                   */\r
+#define CAN_PANCTR_RBUSY_Pos                  9                                                       /*!< CAN PANCTR: RBUSY Position              */\r
+#define CAN_PANCTR_RBUSY_Msk                  (0x01UL << CAN_PANCTR_RBUSY_Pos)                        /*!< CAN PANCTR: RBUSY Mask                  */\r
+#define CAN_PANCTR_PANAR1_Pos                 16                                                      /*!< CAN PANCTR: PANAR1 Position             */\r
+#define CAN_PANCTR_PANAR1_Msk                 (0x000000ffUL << CAN_PANCTR_PANAR1_Pos)                 /*!< CAN PANCTR: PANAR1 Mask                 */\r
+#define CAN_PANCTR_PANAR2_Pos                 24                                                      /*!< CAN PANCTR: PANAR2 Position             */\r
+#define CAN_PANCTR_PANAR2_Msk                 (0x000000ffUL << CAN_PANCTR_PANAR2_Pos)                 /*!< CAN PANCTR: PANAR2 Mask                 */\r
+\r
+/* -----------------------------------  CAN_MCR  ---------------------------------- */\r
+#define CAN_MCR_MPSEL_Pos                     12                                                      /*!< CAN MCR: MPSEL Position                 */\r
+#define CAN_MCR_MPSEL_Msk                     (0x0fUL << CAN_MCR_MPSEL_Pos)                           /*!< CAN MCR: MPSEL Mask                     */\r
+\r
+/* ----------------------------------  CAN_MITR  ---------------------------------- */\r
+#define CAN_MITR_IT_Pos                       0                                                       /*!< CAN MITR: IT Position                   */\r
+#define CAN_MITR_IT_Msk                       (0x000000ffUL << CAN_MITR_IT_Pos)                       /*!< CAN MITR: IT Mask                       */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        Group 'CAN_NODE' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CAN_NODE_NCR  -------------------------------- */\r
+#define CAN_NODE_NCR_INIT_Pos                 0                                                       /*!< CAN_NODE NCR: INIT Position             */\r
+#define CAN_NODE_NCR_INIT_Msk                 (0x01UL << CAN_NODE_NCR_INIT_Pos)                       /*!< CAN_NODE NCR: INIT Mask                 */\r
+#define CAN_NODE_NCR_TRIE_Pos                 1                                                       /*!< CAN_NODE NCR: TRIE Position             */\r
+#define CAN_NODE_NCR_TRIE_Msk                 (0x01UL << CAN_NODE_NCR_TRIE_Pos)                       /*!< CAN_NODE NCR: TRIE Mask                 */\r
+#define CAN_NODE_NCR_LECIE_Pos                2                                                       /*!< CAN_NODE NCR: LECIE Position            */\r
+#define CAN_NODE_NCR_LECIE_Msk                (0x01UL << CAN_NODE_NCR_LECIE_Pos)                      /*!< CAN_NODE NCR: LECIE Mask                */\r
+#define CAN_NODE_NCR_ALIE_Pos                 3                                                       /*!< CAN_NODE NCR: ALIE Position             */\r
+#define CAN_NODE_NCR_ALIE_Msk                 (0x01UL << CAN_NODE_NCR_ALIE_Pos)                       /*!< CAN_NODE NCR: ALIE Mask                 */\r
+#define CAN_NODE_NCR_CANDIS_Pos               4                                                       /*!< CAN_NODE NCR: CANDIS Position           */\r
+#define CAN_NODE_NCR_CANDIS_Msk               (0x01UL << CAN_NODE_NCR_CANDIS_Pos)                     /*!< CAN_NODE NCR: CANDIS Mask               */\r
+#define CAN_NODE_NCR_CCE_Pos                  6                                                       /*!< CAN_NODE NCR: CCE Position              */\r
+#define CAN_NODE_NCR_CCE_Msk                  (0x01UL << CAN_NODE_NCR_CCE_Pos)                        /*!< CAN_NODE NCR: CCE Mask                  */\r
+#define CAN_NODE_NCR_CALM_Pos                 7                                                       /*!< CAN_NODE NCR: CALM Position             */\r
+#define CAN_NODE_NCR_CALM_Msk                 (0x01UL << CAN_NODE_NCR_CALM_Pos)                       /*!< CAN_NODE NCR: CALM Mask                 */\r
+#define CAN_NODE_NCR_SUSEN_Pos                8                                                       /*!< CAN_NODE NCR: SUSEN Position            */\r
+#define CAN_NODE_NCR_SUSEN_Msk                (0x01UL << CAN_NODE_NCR_SUSEN_Pos)                      /*!< CAN_NODE NCR: SUSEN Mask                */\r
+\r
+/* --------------------------------  CAN_NODE_NSR  -------------------------------- */\r
+#define CAN_NODE_NSR_LEC_Pos                  0                                                       /*!< CAN_NODE NSR: LEC Position              */\r
+#define CAN_NODE_NSR_LEC_Msk                  (0x07UL << CAN_NODE_NSR_LEC_Pos)                        /*!< CAN_NODE NSR: LEC Mask                  */\r
+#define CAN_NODE_NSR_TXOK_Pos                 3                                                       /*!< CAN_NODE NSR: TXOK Position             */\r
+#define CAN_NODE_NSR_TXOK_Msk                 (0x01UL << CAN_NODE_NSR_TXOK_Pos)                       /*!< CAN_NODE NSR: TXOK Mask                 */\r
+#define CAN_NODE_NSR_RXOK_Pos                 4                                                       /*!< CAN_NODE NSR: RXOK Position             */\r
+#define CAN_NODE_NSR_RXOK_Msk                 (0x01UL << CAN_NODE_NSR_RXOK_Pos)                       /*!< CAN_NODE NSR: RXOK Mask                 */\r
+#define CAN_NODE_NSR_ALERT_Pos                5                                                       /*!< CAN_NODE NSR: ALERT Position            */\r
+#define CAN_NODE_NSR_ALERT_Msk                (0x01UL << CAN_NODE_NSR_ALERT_Pos)                      /*!< CAN_NODE NSR: ALERT Mask                */\r
+#define CAN_NODE_NSR_EWRN_Pos                 6                                                       /*!< CAN_NODE NSR: EWRN Position             */\r
+#define CAN_NODE_NSR_EWRN_Msk                 (0x01UL << CAN_NODE_NSR_EWRN_Pos)                       /*!< CAN_NODE NSR: EWRN Mask                 */\r
+#define CAN_NODE_NSR_BOFF_Pos                 7                                                       /*!< CAN_NODE NSR: BOFF Position             */\r
+#define CAN_NODE_NSR_BOFF_Msk                 (0x01UL << CAN_NODE_NSR_BOFF_Pos)                       /*!< CAN_NODE NSR: BOFF Mask                 */\r
+#define CAN_NODE_NSR_LLE_Pos                  8                                                       /*!< CAN_NODE NSR: LLE Position              */\r
+#define CAN_NODE_NSR_LLE_Msk                  (0x01UL << CAN_NODE_NSR_LLE_Pos)                        /*!< CAN_NODE NSR: LLE Mask                  */\r
+#define CAN_NODE_NSR_LOE_Pos                  9                                                       /*!< CAN_NODE NSR: LOE Position              */\r
+#define CAN_NODE_NSR_LOE_Msk                  (0x01UL << CAN_NODE_NSR_LOE_Pos)                        /*!< CAN_NODE NSR: LOE Mask                  */\r
+#define CAN_NODE_NSR_SUSACK_Pos               10                                                      /*!< CAN_NODE NSR: SUSACK Position           */\r
+#define CAN_NODE_NSR_SUSACK_Msk               (0x01UL << CAN_NODE_NSR_SUSACK_Pos)                     /*!< CAN_NODE NSR: SUSACK Mask               */\r
+\r
+/* --------------------------------  CAN_NODE_NIPR  ------------------------------- */\r
+#define CAN_NODE_NIPR_ALINP_Pos               0                                                       /*!< CAN_NODE NIPR: ALINP Position           */\r
+#define CAN_NODE_NIPR_ALINP_Msk               (0x07UL << CAN_NODE_NIPR_ALINP_Pos)                     /*!< CAN_NODE NIPR: ALINP Mask               */\r
+#define CAN_NODE_NIPR_LECINP_Pos              4                                                       /*!< CAN_NODE NIPR: LECINP Position          */\r
+#define CAN_NODE_NIPR_LECINP_Msk              (0x07UL << CAN_NODE_NIPR_LECINP_Pos)                    /*!< CAN_NODE NIPR: LECINP Mask              */\r
+#define CAN_NODE_NIPR_TRINP_Pos               8                                                       /*!< CAN_NODE NIPR: TRINP Position           */\r
+#define CAN_NODE_NIPR_TRINP_Msk               (0x07UL << CAN_NODE_NIPR_TRINP_Pos)                     /*!< CAN_NODE NIPR: TRINP Mask               */\r
+#define CAN_NODE_NIPR_CFCINP_Pos              12                                                      /*!< CAN_NODE NIPR: CFCINP Position          */\r
+#define CAN_NODE_NIPR_CFCINP_Msk              (0x07UL << CAN_NODE_NIPR_CFCINP_Pos)                    /*!< CAN_NODE NIPR: CFCINP Mask              */\r
+\r
+/* --------------------------------  CAN_NODE_NPCR  ------------------------------- */\r
+#define CAN_NODE_NPCR_RXSEL_Pos               0                                                       /*!< CAN_NODE NPCR: RXSEL Position           */\r
+#define CAN_NODE_NPCR_RXSEL_Msk               (0x07UL << CAN_NODE_NPCR_RXSEL_Pos)                     /*!< CAN_NODE NPCR: RXSEL Mask               */\r
+#define CAN_NODE_NPCR_LBM_Pos                 8                                                       /*!< CAN_NODE NPCR: LBM Position             */\r
+#define CAN_NODE_NPCR_LBM_Msk                 (0x01UL << CAN_NODE_NPCR_LBM_Pos)                       /*!< CAN_NODE NPCR: LBM Mask                 */\r
+\r
+/* --------------------------------  CAN_NODE_NBTR  ------------------------------- */\r
+#define CAN_NODE_NBTR_BRP_Pos                 0                                                       /*!< CAN_NODE NBTR: BRP Position             */\r
+#define CAN_NODE_NBTR_BRP_Msk                 (0x3fUL << CAN_NODE_NBTR_BRP_Pos)                       /*!< CAN_NODE NBTR: BRP Mask                 */\r
+#define CAN_NODE_NBTR_SJW_Pos                 6                                                       /*!< CAN_NODE NBTR: SJW Position             */\r
+#define CAN_NODE_NBTR_SJW_Msk                 (0x03UL << CAN_NODE_NBTR_SJW_Pos)                       /*!< CAN_NODE NBTR: SJW Mask                 */\r
+#define CAN_NODE_NBTR_TSEG1_Pos               8                                                       /*!< CAN_NODE NBTR: TSEG1 Position           */\r
+#define CAN_NODE_NBTR_TSEG1_Msk               (0x0fUL << CAN_NODE_NBTR_TSEG1_Pos)                     /*!< CAN_NODE NBTR: TSEG1 Mask               */\r
+#define CAN_NODE_NBTR_TSEG2_Pos               12                                                      /*!< CAN_NODE NBTR: TSEG2 Position           */\r
+#define CAN_NODE_NBTR_TSEG2_Msk               (0x07UL << CAN_NODE_NBTR_TSEG2_Pos)                     /*!< CAN_NODE NBTR: TSEG2 Mask               */\r
+#define CAN_NODE_NBTR_DIV8_Pos                15                                                      /*!< CAN_NODE NBTR: DIV8 Position            */\r
+#define CAN_NODE_NBTR_DIV8_Msk                (0x01UL << CAN_NODE_NBTR_DIV8_Pos)                      /*!< CAN_NODE NBTR: DIV8 Mask                */\r
+\r
+/* -------------------------------  CAN_NODE_NECNT  ------------------------------- */\r
+#define CAN_NODE_NECNT_REC_Pos                0                                                       /*!< CAN_NODE NECNT: REC Position            */\r
+#define CAN_NODE_NECNT_REC_Msk                (0x000000ffUL << CAN_NODE_NECNT_REC_Pos)                /*!< CAN_NODE NECNT: REC Mask                */\r
+#define CAN_NODE_NECNT_TEC_Pos                8                                                       /*!< CAN_NODE NECNT: TEC Position            */\r
+#define CAN_NODE_NECNT_TEC_Msk                (0x000000ffUL << CAN_NODE_NECNT_TEC_Pos)                /*!< CAN_NODE NECNT: TEC Mask                */\r
+#define CAN_NODE_NECNT_EWRNLVL_Pos            16                                                      /*!< CAN_NODE NECNT: EWRNLVL Position        */\r
+#define CAN_NODE_NECNT_EWRNLVL_Msk            (0x000000ffUL << CAN_NODE_NECNT_EWRNLVL_Pos)            /*!< CAN_NODE NECNT: EWRNLVL Mask            */\r
+#define CAN_NODE_NECNT_LETD_Pos               24                                                      /*!< CAN_NODE NECNT: LETD Position           */\r
+#define CAN_NODE_NECNT_LETD_Msk               (0x01UL << CAN_NODE_NECNT_LETD_Pos)                     /*!< CAN_NODE NECNT: LETD Mask               */\r
+#define CAN_NODE_NECNT_LEINC_Pos              25                                                      /*!< CAN_NODE NECNT: LEINC Position          */\r
+#define CAN_NODE_NECNT_LEINC_Msk              (0x01UL << CAN_NODE_NECNT_LEINC_Pos)                    /*!< CAN_NODE NECNT: LEINC Mask              */\r
+\r
+/* --------------------------------  CAN_NODE_NFCR  ------------------------------- */\r
+#define CAN_NODE_NFCR_CFC_Pos                 0                                                       /*!< CAN_NODE NFCR: CFC Position             */\r
+#define CAN_NODE_NFCR_CFC_Msk                 (0x0000ffffUL << CAN_NODE_NFCR_CFC_Pos)                 /*!< CAN_NODE NFCR: CFC Mask                 */\r
+#define CAN_NODE_NFCR_CFSEL_Pos               16                                                      /*!< CAN_NODE NFCR: CFSEL Position           */\r
+#define CAN_NODE_NFCR_CFSEL_Msk               (0x07UL << CAN_NODE_NFCR_CFSEL_Pos)                     /*!< CAN_NODE NFCR: CFSEL Mask               */\r
+#define CAN_NODE_NFCR_CFMOD_Pos               19                                                      /*!< CAN_NODE NFCR: CFMOD Position           */\r
+#define CAN_NODE_NFCR_CFMOD_Msk               (0x03UL << CAN_NODE_NFCR_CFMOD_Pos)                     /*!< CAN_NODE NFCR: CFMOD Mask               */\r
+#define CAN_NODE_NFCR_CFCIE_Pos               22                                                      /*!< CAN_NODE NFCR: CFCIE Position           */\r
+#define CAN_NODE_NFCR_CFCIE_Msk               (0x01UL << CAN_NODE_NFCR_CFCIE_Pos)                     /*!< CAN_NODE NFCR: CFCIE Mask               */\r
+#define CAN_NODE_NFCR_CFCOV_Pos               23                                                      /*!< CAN_NODE NFCR: CFCOV Position           */\r
+#define CAN_NODE_NFCR_CFCOV_Msk               (0x01UL << CAN_NODE_NFCR_CFCOV_Pos)                     /*!< CAN_NODE NFCR: CFCOV Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'CAN_MO' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CAN_MO_MOFCR  -------------------------------- */\r
+#define CAN_MO_MOFCR_MMC_Pos                  0                                                       /*!< CAN_MO MOFCR: MMC Position              */\r
+#define CAN_MO_MOFCR_MMC_Msk                  (0x0fUL << CAN_MO_MOFCR_MMC_Pos)                        /*!< CAN_MO MOFCR: MMC Mask                  */\r
+#define CAN_MO_MOFCR_GDFS_Pos                 8                                                       /*!< CAN_MO MOFCR: GDFS Position             */\r
+#define CAN_MO_MOFCR_GDFS_Msk                 (0x01UL << CAN_MO_MOFCR_GDFS_Pos)                       /*!< CAN_MO MOFCR: GDFS Mask                 */\r
+#define CAN_MO_MOFCR_IDC_Pos                  9                                                       /*!< CAN_MO MOFCR: IDC Position              */\r
+#define CAN_MO_MOFCR_IDC_Msk                  (0x01UL << CAN_MO_MOFCR_IDC_Pos)                        /*!< CAN_MO MOFCR: IDC Mask                  */\r
+#define CAN_MO_MOFCR_DLCC_Pos                 10                                                      /*!< CAN_MO MOFCR: DLCC Position             */\r
+#define CAN_MO_MOFCR_DLCC_Msk                 (0x01UL << CAN_MO_MOFCR_DLCC_Pos)                       /*!< CAN_MO MOFCR: DLCC Mask                 */\r
+#define CAN_MO_MOFCR_DATC_Pos                 11                                                      /*!< CAN_MO MOFCR: DATC Position             */\r
+#define CAN_MO_MOFCR_DATC_Msk                 (0x01UL << CAN_MO_MOFCR_DATC_Pos)                       /*!< CAN_MO MOFCR: DATC Mask                 */\r
+#define CAN_MO_MOFCR_RXIE_Pos                 16                                                      /*!< CAN_MO MOFCR: RXIE Position             */\r
+#define CAN_MO_MOFCR_RXIE_Msk                 (0x01UL << CAN_MO_MOFCR_RXIE_Pos)                       /*!< CAN_MO MOFCR: RXIE Mask                 */\r
+#define CAN_MO_MOFCR_TXIE_Pos                 17                                                      /*!< CAN_MO MOFCR: TXIE Position             */\r
+#define CAN_MO_MOFCR_TXIE_Msk                 (0x01UL << CAN_MO_MOFCR_TXIE_Pos)                       /*!< CAN_MO MOFCR: TXIE Mask                 */\r
+#define CAN_MO_MOFCR_OVIE_Pos                 18                                                      /*!< CAN_MO MOFCR: OVIE Position             */\r
+#define CAN_MO_MOFCR_OVIE_Msk                 (0x01UL << CAN_MO_MOFCR_OVIE_Pos)                       /*!< CAN_MO MOFCR: OVIE Mask                 */\r
+#define CAN_MO_MOFCR_FRREN_Pos                20                                                      /*!< CAN_MO MOFCR: FRREN Position            */\r
+#define CAN_MO_MOFCR_FRREN_Msk                (0x01UL << CAN_MO_MOFCR_FRREN_Pos)                      /*!< CAN_MO MOFCR: FRREN Mask                */\r
+#define CAN_MO_MOFCR_RMM_Pos                  21                                                      /*!< CAN_MO MOFCR: RMM Position              */\r
+#define CAN_MO_MOFCR_RMM_Msk                  (0x01UL << CAN_MO_MOFCR_RMM_Pos)                        /*!< CAN_MO MOFCR: RMM Mask                  */\r
+#define CAN_MO_MOFCR_SDT_Pos                  22                                                      /*!< CAN_MO MOFCR: SDT Position              */\r
+#define CAN_MO_MOFCR_SDT_Msk                  (0x01UL << CAN_MO_MOFCR_SDT_Pos)                        /*!< CAN_MO MOFCR: SDT Mask                  */\r
+#define CAN_MO_MOFCR_STT_Pos                  23                                                      /*!< CAN_MO MOFCR: STT Position              */\r
+#define CAN_MO_MOFCR_STT_Msk                  (0x01UL << CAN_MO_MOFCR_STT_Pos)                        /*!< CAN_MO MOFCR: STT Mask                  */\r
+#define CAN_MO_MOFCR_DLC_Pos                  24                                                      /*!< CAN_MO MOFCR: DLC Position              */\r
+#define CAN_MO_MOFCR_DLC_Msk                  (0x0fUL << CAN_MO_MOFCR_DLC_Pos)                        /*!< CAN_MO MOFCR: DLC Mask                  */\r
+\r
+/* --------------------------------  CAN_MO_MOFGPR  ------------------------------- */\r
+#define CAN_MO_MOFGPR_BOT_Pos                 0                                                       /*!< CAN_MO MOFGPR: BOT Position             */\r
+#define CAN_MO_MOFGPR_BOT_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_BOT_Pos)                 /*!< CAN_MO MOFGPR: BOT Mask                 */\r
+#define CAN_MO_MOFGPR_TOP_Pos                 8                                                       /*!< CAN_MO MOFGPR: TOP Position             */\r
+#define CAN_MO_MOFGPR_TOP_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_TOP_Pos)                 /*!< CAN_MO MOFGPR: TOP Mask                 */\r
+#define CAN_MO_MOFGPR_CUR_Pos                 16                                                      /*!< CAN_MO MOFGPR: CUR Position             */\r
+#define CAN_MO_MOFGPR_CUR_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_CUR_Pos)                 /*!< CAN_MO MOFGPR: CUR Mask                 */\r
+#define CAN_MO_MOFGPR_SEL_Pos                 24                                                      /*!< CAN_MO MOFGPR: SEL Position             */\r
+#define CAN_MO_MOFGPR_SEL_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_SEL_Pos)                 /*!< CAN_MO MOFGPR: SEL Mask                 */\r
+\r
+/* --------------------------------  CAN_MO_MOIPR  -------------------------------- */\r
+#define CAN_MO_MOIPR_RXINP_Pos                0                                                       /*!< CAN_MO MOIPR: RXINP Position            */\r
+#define CAN_MO_MOIPR_RXINP_Msk                (0x07UL << CAN_MO_MOIPR_RXINP_Pos)                      /*!< CAN_MO MOIPR: RXINP Mask                */\r
+#define CAN_MO_MOIPR_TXINP_Pos                4                                                       /*!< CAN_MO MOIPR: TXINP Position            */\r
+#define CAN_MO_MOIPR_TXINP_Msk                (0x07UL << CAN_MO_MOIPR_TXINP_Pos)                      /*!< CAN_MO MOIPR: TXINP Mask                */\r
+#define CAN_MO_MOIPR_MPN_Pos                  8                                                       /*!< CAN_MO MOIPR: MPN Position              */\r
+#define CAN_MO_MOIPR_MPN_Msk                  (0x000000ffUL << CAN_MO_MOIPR_MPN_Pos)                  /*!< CAN_MO MOIPR: MPN Mask                  */\r
+#define CAN_MO_MOIPR_CFCVAL_Pos               16                                                      /*!< CAN_MO MOIPR: CFCVAL Position           */\r
+#define CAN_MO_MOIPR_CFCVAL_Msk               (0x0000ffffUL << CAN_MO_MOIPR_CFCVAL_Pos)               /*!< CAN_MO MOIPR: CFCVAL Mask               */\r
+\r
+/* --------------------------------  CAN_MO_MOAMR  -------------------------------- */\r
+#define CAN_MO_MOAMR_AM_Pos                   0                                                       /*!< CAN_MO MOAMR: AM Position               */\r
+#define CAN_MO_MOAMR_AM_Msk                   (0x1fffffffUL << CAN_MO_MOAMR_AM_Pos)                   /*!< CAN_MO MOAMR: AM Mask                   */\r
+#define CAN_MO_MOAMR_MIDE_Pos                 29                                                      /*!< CAN_MO MOAMR: MIDE Position             */\r
+#define CAN_MO_MOAMR_MIDE_Msk                 (0x01UL << CAN_MO_MOAMR_MIDE_Pos)                       /*!< CAN_MO MOAMR: MIDE Mask                 */\r
+\r
+/* -------------------------------  CAN_MO_MODATAL  ------------------------------- */\r
+#define CAN_MO_MODATAL_DB0_Pos                0                                                       /*!< CAN_MO MODATAL: DB0 Position            */\r
+#define CAN_MO_MODATAL_DB0_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB0_Pos)                /*!< CAN_MO MODATAL: DB0 Mask                */\r
+#define CAN_MO_MODATAL_DB1_Pos                8                                                       /*!< CAN_MO MODATAL: DB1 Position            */\r
+#define CAN_MO_MODATAL_DB1_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB1_Pos)                /*!< CAN_MO MODATAL: DB1 Mask                */\r
+#define CAN_MO_MODATAL_DB2_Pos                16                                                      /*!< CAN_MO MODATAL: DB2 Position            */\r
+#define CAN_MO_MODATAL_DB2_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB2_Pos)                /*!< CAN_MO MODATAL: DB2 Mask                */\r
+#define CAN_MO_MODATAL_DB3_Pos                24                                                      /*!< CAN_MO MODATAL: DB3 Position            */\r
+#define CAN_MO_MODATAL_DB3_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB3_Pos)                /*!< CAN_MO MODATAL: DB3 Mask                */\r
+\r
+/* -------------------------------  CAN_MO_MODATAH  ------------------------------- */\r
+#define CAN_MO_MODATAH_DB4_Pos                0                                                       /*!< CAN_MO MODATAH: DB4 Position            */\r
+#define CAN_MO_MODATAH_DB4_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB4_Pos)                /*!< CAN_MO MODATAH: DB4 Mask                */\r
+#define CAN_MO_MODATAH_DB5_Pos                8                                                       /*!< CAN_MO MODATAH: DB5 Position            */\r
+#define CAN_MO_MODATAH_DB5_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB5_Pos)                /*!< CAN_MO MODATAH: DB5 Mask                */\r
+#define CAN_MO_MODATAH_DB6_Pos                16                                                      /*!< CAN_MO MODATAH: DB6 Position            */\r
+#define CAN_MO_MODATAH_DB6_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB6_Pos)                /*!< CAN_MO MODATAH: DB6 Mask                */\r
+#define CAN_MO_MODATAH_DB7_Pos                24                                                      /*!< CAN_MO MODATAH: DB7 Position            */\r
+#define CAN_MO_MODATAH_DB7_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB7_Pos)                /*!< CAN_MO MODATAH: DB7 Mask                */\r
+\r
+/* ---------------------------------  CAN_MO_MOAR  -------------------------------- */\r
+#define CAN_MO_MOAR_ID_Pos                    0                                                       /*!< CAN_MO MOAR: ID Position                */\r
+#define CAN_MO_MOAR_ID_Msk                    (0x1fffffffUL << CAN_MO_MOAR_ID_Pos)                    /*!< CAN_MO MOAR: ID Mask                    */\r
+#define CAN_MO_MOAR_IDE_Pos                   29                                                      /*!< CAN_MO MOAR: IDE Position               */\r
+#define CAN_MO_MOAR_IDE_Msk                   (0x01UL << CAN_MO_MOAR_IDE_Pos)                         /*!< CAN_MO MOAR: IDE Mask                   */\r
+#define CAN_MO_MOAR_PRI_Pos                   30                                                      /*!< CAN_MO MOAR: PRI Position               */\r
+#define CAN_MO_MOAR_PRI_Msk                   (0x03UL << CAN_MO_MOAR_PRI_Pos)                         /*!< CAN_MO MOAR: PRI Mask                   */\r
+\r
+/* --------------------------------  CAN_MO_MOCTR  -------------------------------- */\r
+#define CAN_MO_MOCTR_RESRXPND_Pos             0                                                       /*!< CAN_MO MOCTR: RESRXPND Position         */\r
+#define CAN_MO_MOCTR_RESRXPND_Msk             (0x01UL << CAN_MO_MOCTR_RESRXPND_Pos)                   /*!< CAN_MO MOCTR: RESRXPND Mask             */\r
+#define CAN_MO_MOCTR_RESTXPND_Pos             1                                                       /*!< CAN_MO MOCTR: RESTXPND Position         */\r
+#define CAN_MO_MOCTR_RESTXPND_Msk             (0x01UL << CAN_MO_MOCTR_RESTXPND_Pos)                   /*!< CAN_MO MOCTR: RESTXPND Mask             */\r
+#define CAN_MO_MOCTR_RESRXUPD_Pos             2                                                       /*!< CAN_MO MOCTR: RESRXUPD Position         */\r
+#define CAN_MO_MOCTR_RESRXUPD_Msk             (0x01UL << CAN_MO_MOCTR_RESRXUPD_Pos)                   /*!< CAN_MO MOCTR: RESRXUPD Mask             */\r
+#define CAN_MO_MOCTR_RESNEWDAT_Pos            3                                                       /*!< CAN_MO MOCTR: RESNEWDAT Position        */\r
+#define CAN_MO_MOCTR_RESNEWDAT_Msk            (0x01UL << CAN_MO_MOCTR_RESNEWDAT_Pos)                  /*!< CAN_MO MOCTR: RESNEWDAT Mask            */\r
+#define CAN_MO_MOCTR_RESMSGLST_Pos            4                                                       /*!< CAN_MO MOCTR: RESMSGLST Position        */\r
+#define CAN_MO_MOCTR_RESMSGLST_Msk            (0x01UL << CAN_MO_MOCTR_RESMSGLST_Pos)                  /*!< CAN_MO MOCTR: RESMSGLST Mask            */\r
+#define CAN_MO_MOCTR_RESMSGVAL_Pos            5                                                       /*!< CAN_MO MOCTR: RESMSGVAL Position        */\r
+#define CAN_MO_MOCTR_RESMSGVAL_Msk            (0x01UL << CAN_MO_MOCTR_RESMSGVAL_Pos)                  /*!< CAN_MO MOCTR: RESMSGVAL Mask            */\r
+#define CAN_MO_MOCTR_RESRTSEL_Pos             6                                                       /*!< CAN_MO MOCTR: RESRTSEL Position         */\r
+#define CAN_MO_MOCTR_RESRTSEL_Msk             (0x01UL << CAN_MO_MOCTR_RESRTSEL_Pos)                   /*!< CAN_MO MOCTR: RESRTSEL Mask             */\r
+#define CAN_MO_MOCTR_RESRXEN_Pos              7                                                       /*!< CAN_MO MOCTR: RESRXEN Position          */\r
+#define CAN_MO_MOCTR_RESRXEN_Msk              (0x01UL << CAN_MO_MOCTR_RESRXEN_Pos)                    /*!< CAN_MO MOCTR: RESRXEN Mask              */\r
+#define CAN_MO_MOCTR_RESTXRQ_Pos              8                                                       /*!< CAN_MO MOCTR: RESTXRQ Position          */\r
+#define CAN_MO_MOCTR_RESTXRQ_Msk              (0x01UL << CAN_MO_MOCTR_RESTXRQ_Pos)                    /*!< CAN_MO MOCTR: RESTXRQ Mask              */\r
+#define CAN_MO_MOCTR_RESTXEN0_Pos             9                                                       /*!< CAN_MO MOCTR: RESTXEN0 Position         */\r
+#define CAN_MO_MOCTR_RESTXEN0_Msk             (0x01UL << CAN_MO_MOCTR_RESTXEN0_Pos)                   /*!< CAN_MO MOCTR: RESTXEN0 Mask             */\r
+#define CAN_MO_MOCTR_RESTXEN1_Pos             10                                                      /*!< CAN_MO MOCTR: RESTXEN1 Position         */\r
+#define CAN_MO_MOCTR_RESTXEN1_Msk             (0x01UL << CAN_MO_MOCTR_RESTXEN1_Pos)                   /*!< CAN_MO MOCTR: RESTXEN1 Mask             */\r
+#define CAN_MO_MOCTR_RESDIR_Pos               11                                                      /*!< CAN_MO MOCTR: RESDIR Position           */\r
+#define CAN_MO_MOCTR_RESDIR_Msk               (0x01UL << CAN_MO_MOCTR_RESDIR_Pos)                     /*!< CAN_MO MOCTR: RESDIR Mask               */\r
+#define CAN_MO_MOCTR_SETRXPND_Pos             16                                                      /*!< CAN_MO MOCTR: SETRXPND Position         */\r
+#define CAN_MO_MOCTR_SETRXPND_Msk             (0x01UL << CAN_MO_MOCTR_SETRXPND_Pos)                   /*!< CAN_MO MOCTR: SETRXPND Mask             */\r
+#define CAN_MO_MOCTR_SETTXPND_Pos             17                                                      /*!< CAN_MO MOCTR: SETTXPND Position         */\r
+#define CAN_MO_MOCTR_SETTXPND_Msk             (0x01UL << CAN_MO_MOCTR_SETTXPND_Pos)                   /*!< CAN_MO MOCTR: SETTXPND Mask             */\r
+#define CAN_MO_MOCTR_SETRXUPD_Pos             18                                                      /*!< CAN_MO MOCTR: SETRXUPD Position         */\r
+#define CAN_MO_MOCTR_SETRXUPD_Msk             (0x01UL << CAN_MO_MOCTR_SETRXUPD_Pos)                   /*!< CAN_MO MOCTR: SETRXUPD Mask             */\r
+#define CAN_MO_MOCTR_SETNEWDAT_Pos            19                                                      /*!< CAN_MO MOCTR: SETNEWDAT Position        */\r
+#define CAN_MO_MOCTR_SETNEWDAT_Msk            (0x01UL << CAN_MO_MOCTR_SETNEWDAT_Pos)                  /*!< CAN_MO MOCTR: SETNEWDAT Mask            */\r
+#define CAN_MO_MOCTR_SETMSGLST_Pos            20                                                      /*!< CAN_MO MOCTR: SETMSGLST Position        */\r
+#define CAN_MO_MOCTR_SETMSGLST_Msk            (0x01UL << CAN_MO_MOCTR_SETMSGLST_Pos)                  /*!< CAN_MO MOCTR: SETMSGLST Mask            */\r
+#define CAN_MO_MOCTR_SETMSGVAL_Pos            21                                                      /*!< CAN_MO MOCTR: SETMSGVAL Position        */\r
+#define CAN_MO_MOCTR_SETMSGVAL_Msk            (0x01UL << CAN_MO_MOCTR_SETMSGVAL_Pos)                  /*!< CAN_MO MOCTR: SETMSGVAL Mask            */\r
+#define CAN_MO_MOCTR_SETRTSEL_Pos             22                                                      /*!< CAN_MO MOCTR: SETRTSEL Position         */\r
+#define CAN_MO_MOCTR_SETRTSEL_Msk             (0x01UL << CAN_MO_MOCTR_SETRTSEL_Pos)                   /*!< CAN_MO MOCTR: SETRTSEL Mask             */\r
+#define CAN_MO_MOCTR_SETRXEN_Pos              23                                                      /*!< CAN_MO MOCTR: SETRXEN Position          */\r
+#define CAN_MO_MOCTR_SETRXEN_Msk              (0x01UL << CAN_MO_MOCTR_SETRXEN_Pos)                    /*!< CAN_MO MOCTR: SETRXEN Mask              */\r
+#define CAN_MO_MOCTR_SETTXRQ_Pos              24                                                      /*!< CAN_MO MOCTR: SETTXRQ Position          */\r
+#define CAN_MO_MOCTR_SETTXRQ_Msk              (0x01UL << CAN_MO_MOCTR_SETTXRQ_Pos)                    /*!< CAN_MO MOCTR: SETTXRQ Mask              */\r
+#define CAN_MO_MOCTR_SETTXEN0_Pos             25                                                      /*!< CAN_MO MOCTR: SETTXEN0 Position         */\r
+#define CAN_MO_MOCTR_SETTXEN0_Msk             (0x01UL << CAN_MO_MOCTR_SETTXEN0_Pos)                   /*!< CAN_MO MOCTR: SETTXEN0 Mask             */\r
+#define CAN_MO_MOCTR_SETTXEN1_Pos             26                                                      /*!< CAN_MO MOCTR: SETTXEN1 Position         */\r
+#define CAN_MO_MOCTR_SETTXEN1_Msk             (0x01UL << CAN_MO_MOCTR_SETTXEN1_Pos)                   /*!< CAN_MO MOCTR: SETTXEN1 Mask             */\r
+#define CAN_MO_MOCTR_SETDIR_Pos               27                                                      /*!< CAN_MO MOCTR: SETDIR Position           */\r
+#define CAN_MO_MOCTR_SETDIR_Msk               (0x01UL << CAN_MO_MOCTR_SETDIR_Pos)                     /*!< CAN_MO MOCTR: SETDIR Mask               */\r
+\r
+/* --------------------------------  CAN_MO_MOSTAT  ------------------------------- */\r
+#define CAN_MO_MOSTAT_RXPND_Pos               0                                                       /*!< CAN_MO MOSTAT: RXPND Position           */\r
+#define CAN_MO_MOSTAT_RXPND_Msk               (0x01UL << CAN_MO_MOSTAT_RXPND_Pos)                     /*!< CAN_MO MOSTAT: RXPND Mask               */\r
+#define CAN_MO_MOSTAT_TXPND_Pos               1                                                       /*!< CAN_MO MOSTAT: TXPND Position           */\r
+#define CAN_MO_MOSTAT_TXPND_Msk               (0x01UL << CAN_MO_MOSTAT_TXPND_Pos)                     /*!< CAN_MO MOSTAT: TXPND Mask               */\r
+#define CAN_MO_MOSTAT_RXUPD_Pos               2                                                       /*!< CAN_MO MOSTAT: RXUPD Position           */\r
+#define CAN_MO_MOSTAT_RXUPD_Msk               (0x01UL << CAN_MO_MOSTAT_RXUPD_Pos)                     /*!< CAN_MO MOSTAT: RXUPD Mask               */\r
+#define CAN_MO_MOSTAT_NEWDAT_Pos              3                                                       /*!< CAN_MO MOSTAT: NEWDAT Position          */\r
+#define CAN_MO_MOSTAT_NEWDAT_Msk              (0x01UL << CAN_MO_MOSTAT_NEWDAT_Pos)                    /*!< CAN_MO MOSTAT: NEWDAT Mask              */\r
+#define CAN_MO_MOSTAT_MSGLST_Pos              4                                                       /*!< CAN_MO MOSTAT: MSGLST Position          */\r
+#define CAN_MO_MOSTAT_MSGLST_Msk              (0x01UL << CAN_MO_MOSTAT_MSGLST_Pos)                    /*!< CAN_MO MOSTAT: MSGLST Mask              */\r
+#define CAN_MO_MOSTAT_MSGVAL_Pos              5                                                       /*!< CAN_MO MOSTAT: MSGVAL Position          */\r
+#define CAN_MO_MOSTAT_MSGVAL_Msk              (0x01UL << CAN_MO_MOSTAT_MSGVAL_Pos)                    /*!< CAN_MO MOSTAT: MSGVAL Mask              */\r
+#define CAN_MO_MOSTAT_RTSEL_Pos               6                                                       /*!< CAN_MO MOSTAT: RTSEL Position           */\r
+#define CAN_MO_MOSTAT_RTSEL_Msk               (0x01UL << CAN_MO_MOSTAT_RTSEL_Pos)                     /*!< CAN_MO MOSTAT: RTSEL Mask               */\r
+#define CAN_MO_MOSTAT_RXEN_Pos                7                                                       /*!< CAN_MO MOSTAT: RXEN Position            */\r
+#define CAN_MO_MOSTAT_RXEN_Msk                (0x01UL << CAN_MO_MOSTAT_RXEN_Pos)                      /*!< CAN_MO MOSTAT: RXEN Mask                */\r
+#define CAN_MO_MOSTAT_TXRQ_Pos                8                                                       /*!< CAN_MO MOSTAT: TXRQ Position            */\r
+#define CAN_MO_MOSTAT_TXRQ_Msk                (0x01UL << CAN_MO_MOSTAT_TXRQ_Pos)                      /*!< CAN_MO MOSTAT: TXRQ Mask                */\r
+#define CAN_MO_MOSTAT_TXEN0_Pos               9                                                       /*!< CAN_MO MOSTAT: TXEN0 Position           */\r
+#define CAN_MO_MOSTAT_TXEN0_Msk               (0x01UL << CAN_MO_MOSTAT_TXEN0_Pos)                     /*!< CAN_MO MOSTAT: TXEN0 Mask               */\r
+#define CAN_MO_MOSTAT_TXEN1_Pos               10                                                      /*!< CAN_MO MOSTAT: TXEN1 Position           */\r
+#define CAN_MO_MOSTAT_TXEN1_Msk               (0x01UL << CAN_MO_MOSTAT_TXEN1_Pos)                     /*!< CAN_MO MOSTAT: TXEN1 Mask               */\r
+#define CAN_MO_MOSTAT_DIR_Pos                 11                                                      /*!< CAN_MO MOSTAT: DIR Position             */\r
+#define CAN_MO_MOSTAT_DIR_Msk                 (0x01UL << CAN_MO_MOSTAT_DIR_Pos)                       /*!< CAN_MO MOSTAT: DIR Mask                 */\r
+#define CAN_MO_MOSTAT_LIST_Pos                12                                                      /*!< CAN_MO MOSTAT: LIST Position            */\r
+#define CAN_MO_MOSTAT_LIST_Msk                (0x0fUL << CAN_MO_MOSTAT_LIST_Pos)                      /*!< CAN_MO MOSTAT: LIST Mask                */\r
+#define CAN_MO_MOSTAT_PPREV_Pos               16                                                      /*!< CAN_MO MOSTAT: PPREV Position           */\r
+#define CAN_MO_MOSTAT_PPREV_Msk               (0x000000ffUL << CAN_MO_MOSTAT_PPREV_Pos)               /*!< CAN_MO MOSTAT: PPREV Mask               */\r
+#define CAN_MO_MOSTAT_PNEXT_Pos               24                                                      /*!< CAN_MO MOSTAT: PNEXT Position           */\r
+#define CAN_MO_MOSTAT_PNEXT_Msk               (0x000000ffUL << CAN_MO_MOSTAT_PNEXT_Pos)               /*!< CAN_MO MOSTAT: PNEXT Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'VADC' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  VADC_CLC  ---------------------------------- */\r
+#define VADC_CLC_DISR_Pos                     0                                                       /*!< VADC CLC: DISR Position                 */\r
+#define VADC_CLC_DISR_Msk                     (0x01UL << VADC_CLC_DISR_Pos)                           /*!< VADC CLC: DISR Mask                     */\r
+#define VADC_CLC_DISS_Pos                     1                                                       /*!< VADC CLC: DISS Position                 */\r
+#define VADC_CLC_DISS_Msk                     (0x01UL << VADC_CLC_DISS_Pos)                           /*!< VADC CLC: DISS Mask                     */\r
+#define VADC_CLC_EDIS_Pos                     3                                                       /*!< VADC CLC: EDIS Position                 */\r
+#define VADC_CLC_EDIS_Msk                     (0x01UL << VADC_CLC_EDIS_Pos)                           /*!< VADC CLC: EDIS Mask                     */\r
+\r
+/* -----------------------------------  VADC_ID  ---------------------------------- */\r
+#define VADC_ID_MOD_REV_Pos                   0                                                       /*!< VADC ID: MOD_REV Position               */\r
+#define VADC_ID_MOD_REV_Msk                   (0x000000ffUL << VADC_ID_MOD_REV_Pos)                   /*!< VADC ID: MOD_REV Mask                   */\r
+#define VADC_ID_MOD_TYPE_Pos                  8                                                       /*!< VADC ID: MOD_TYPE Position              */\r
+#define VADC_ID_MOD_TYPE_Msk                  (0x000000ffUL << VADC_ID_MOD_TYPE_Pos)                  /*!< VADC ID: MOD_TYPE Mask                  */\r
+#define VADC_ID_MOD_NUMBER_Pos                16                                                      /*!< VADC ID: MOD_NUMBER Position            */\r
+#define VADC_ID_MOD_NUMBER_Msk                (0x0000ffffUL << VADC_ID_MOD_NUMBER_Pos)                /*!< VADC ID: MOD_NUMBER Mask                */\r
+\r
+/* ----------------------------------  VADC_OCS  ---------------------------------- */\r
+#define VADC_OCS_TGS_Pos                      0                                                       /*!< VADC OCS: TGS Position                  */\r
+#define VADC_OCS_TGS_Msk                      (0x03UL << VADC_OCS_TGS_Pos)                            /*!< VADC OCS: TGS Mask                      */\r
+#define VADC_OCS_TGB_Pos                      2                                                       /*!< VADC OCS: TGB Position                  */\r
+#define VADC_OCS_TGB_Msk                      (0x01UL << VADC_OCS_TGB_Pos)                            /*!< VADC OCS: TGB Mask                      */\r
+#define VADC_OCS_TG_P_Pos                     3                                                       /*!< VADC OCS: TG_P Position                 */\r
+#define VADC_OCS_TG_P_Msk                     (0x01UL << VADC_OCS_TG_P_Pos)                           /*!< VADC OCS: TG_P Mask                     */\r
+#define VADC_OCS_SUS_Pos                      24                                                      /*!< VADC OCS: SUS Position                  */\r
+#define VADC_OCS_SUS_Msk                      (0x0fUL << VADC_OCS_SUS_Pos)                            /*!< VADC OCS: SUS Mask                      */\r
+#define VADC_OCS_SUS_P_Pos                    28                                                      /*!< VADC OCS: SUS_P Position                */\r
+#define VADC_OCS_SUS_P_Msk                    (0x01UL << VADC_OCS_SUS_P_Pos)                          /*!< VADC OCS: SUS_P Mask                    */\r
+#define VADC_OCS_SUSSTA_Pos                   29                                                      /*!< VADC OCS: SUSSTA Position               */\r
+#define VADC_OCS_SUSSTA_Msk                   (0x01UL << VADC_OCS_SUSSTA_Pos)                         /*!< VADC OCS: SUSSTA Mask                   */\r
+\r
+/* --------------------------------  VADC_GLOBCFG  -------------------------------- */\r
+#define VADC_GLOBCFG_DIVA_Pos                 0                                                       /*!< VADC GLOBCFG: DIVA Position             */\r
+#define VADC_GLOBCFG_DIVA_Msk                 (0x1fUL << VADC_GLOBCFG_DIVA_Pos)                       /*!< VADC GLOBCFG: DIVA Mask                 */\r
+#define VADC_GLOBCFG_DCMSB_Pos                7                                                       /*!< VADC GLOBCFG: DCMSB Position            */\r
+#define VADC_GLOBCFG_DCMSB_Msk                (0x01UL << VADC_GLOBCFG_DCMSB_Pos)                      /*!< VADC GLOBCFG: DCMSB Mask                */\r
+#define VADC_GLOBCFG_DIVD_Pos                 8                                                       /*!< VADC GLOBCFG: DIVD Position             */\r
+#define VADC_GLOBCFG_DIVD_Msk                 (0x03UL << VADC_GLOBCFG_DIVD_Pos)                       /*!< VADC GLOBCFG: DIVD Mask                 */\r
+#define VADC_GLOBCFG_DIVWC_Pos                15                                                      /*!< VADC GLOBCFG: DIVWC Position            */\r
+#define VADC_GLOBCFG_DIVWC_Msk                (0x01UL << VADC_GLOBCFG_DIVWC_Pos)                      /*!< VADC GLOBCFG: DIVWC Mask                */\r
+#define VADC_GLOBCFG_DPCAL0_Pos               16                                                      /*!< VADC GLOBCFG: DPCAL0 Position           */\r
+#define VADC_GLOBCFG_DPCAL0_Msk               (0x01UL << VADC_GLOBCFG_DPCAL0_Pos)                     /*!< VADC GLOBCFG: DPCAL0 Mask               */\r
+#define VADC_GLOBCFG_DPCAL1_Pos               17                                                      /*!< VADC GLOBCFG: DPCAL1 Position           */\r
+#define VADC_GLOBCFG_DPCAL1_Msk               (0x01UL << VADC_GLOBCFG_DPCAL1_Pos)                     /*!< VADC GLOBCFG: DPCAL1 Mask               */\r
+#define VADC_GLOBCFG_DPCAL2_Pos               18                                                      /*!< VADC GLOBCFG: DPCAL2 Position           */\r
+#define VADC_GLOBCFG_DPCAL2_Msk               (0x01UL << VADC_GLOBCFG_DPCAL2_Pos)                     /*!< VADC GLOBCFG: DPCAL2 Mask               */\r
+#define VADC_GLOBCFG_DPCAL3_Pos               19                                                      /*!< VADC GLOBCFG: DPCAL3 Position           */\r
+#define VADC_GLOBCFG_DPCAL3_Msk               (0x01UL << VADC_GLOBCFG_DPCAL3_Pos)                     /*!< VADC GLOBCFG: DPCAL3 Mask               */\r
+#define VADC_GLOBCFG_SUCAL_Pos                31                                                      /*!< VADC GLOBCFG: SUCAL Position            */\r
+#define VADC_GLOBCFG_SUCAL_Msk                (0x01UL << VADC_GLOBCFG_SUCAL_Pos)                      /*!< VADC GLOBCFG: SUCAL Mask                */\r
+\r
+/* -------------------------------  VADC_GLOBICLASS  ------------------------------ */\r
+#define VADC_GLOBICLASS_STCS_Pos              0                                                       /*!< VADC GLOBICLASS: STCS Position          */\r
+#define VADC_GLOBICLASS_STCS_Msk              (0x1fUL << VADC_GLOBICLASS_STCS_Pos)                    /*!< VADC GLOBICLASS: STCS Mask              */\r
+#define VADC_GLOBICLASS_CMS_Pos               8                                                       /*!< VADC GLOBICLASS: CMS Position           */\r
+#define VADC_GLOBICLASS_CMS_Msk               (0x07UL << VADC_GLOBICLASS_CMS_Pos)                     /*!< VADC GLOBICLASS: CMS Mask               */\r
+#define VADC_GLOBICLASS_STCE_Pos              16                                                      /*!< VADC GLOBICLASS: STCE Position          */\r
+#define VADC_GLOBICLASS_STCE_Msk              (0x1fUL << VADC_GLOBICLASS_STCE_Pos)                    /*!< VADC GLOBICLASS: STCE Mask              */\r
+#define VADC_GLOBICLASS_CME_Pos               24                                                      /*!< VADC GLOBICLASS: CME Position           */\r
+#define VADC_GLOBICLASS_CME_Msk               (0x07UL << VADC_GLOBICLASS_CME_Pos)                     /*!< VADC GLOBICLASS: CME Mask               */\r
+\r
+/* -------------------------------  VADC_GLOBBOUND  ------------------------------- */\r
+#define VADC_GLOBBOUND_BOUNDARY0_Pos          0                                                       /*!< VADC GLOBBOUND: BOUNDARY0 Position      */\r
+#define VADC_GLOBBOUND_BOUNDARY0_Msk          (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY0_Pos)          /*!< VADC GLOBBOUND: BOUNDARY0 Mask          */\r
+#define VADC_GLOBBOUND_BOUNDARY1_Pos          16                                                      /*!< VADC GLOBBOUND: BOUNDARY1 Position      */\r
+#define VADC_GLOBBOUND_BOUNDARY1_Msk          (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY1_Pos)          /*!< VADC GLOBBOUND: BOUNDARY1 Mask          */\r
+\r
+/* -------------------------------  VADC_GLOBEFLAG  ------------------------------- */\r
+#define VADC_GLOBEFLAG_SEVGLB_Pos             0                                                       /*!< VADC GLOBEFLAG: SEVGLB Position         */\r
+#define VADC_GLOBEFLAG_SEVGLB_Msk             (0x01UL << VADC_GLOBEFLAG_SEVGLB_Pos)                   /*!< VADC GLOBEFLAG: SEVGLB Mask             */\r
+#define VADC_GLOBEFLAG_REVGLB_Pos             8                                                       /*!< VADC GLOBEFLAG: REVGLB Position         */\r
+#define VADC_GLOBEFLAG_REVGLB_Msk             (0x01UL << VADC_GLOBEFLAG_REVGLB_Pos)                   /*!< VADC GLOBEFLAG: REVGLB Mask             */\r
+#define VADC_GLOBEFLAG_SEVGLBCLR_Pos          16                                                      /*!< VADC GLOBEFLAG: SEVGLBCLR Position      */\r
+#define VADC_GLOBEFLAG_SEVGLBCLR_Msk          (0x01UL << VADC_GLOBEFLAG_SEVGLBCLR_Pos)                /*!< VADC GLOBEFLAG: SEVGLBCLR Mask          */\r
+#define VADC_GLOBEFLAG_REVGLBCLR_Pos          24                                                      /*!< VADC GLOBEFLAG: REVGLBCLR Position      */\r
+#define VADC_GLOBEFLAG_REVGLBCLR_Msk          (0x01UL << VADC_GLOBEFLAG_REVGLBCLR_Pos)                /*!< VADC GLOBEFLAG: REVGLBCLR Mask          */\r
+\r
+/* --------------------------------  VADC_GLOBEVNP  ------------------------------- */\r
+#define VADC_GLOBEVNP_SEV0NP_Pos              0                                                       /*!< VADC GLOBEVNP: SEV0NP Position          */\r
+#define VADC_GLOBEVNP_SEV0NP_Msk              (0x0fUL << VADC_GLOBEVNP_SEV0NP_Pos)                    /*!< VADC GLOBEVNP: SEV0NP Mask              */\r
+#define VADC_GLOBEVNP_REV0NP_Pos              16                                                      /*!< VADC GLOBEVNP: REV0NP Position          */\r
+#define VADC_GLOBEVNP_REV0NP_Msk              (0x0fUL << VADC_GLOBEVNP_REV0NP_Pos)                    /*!< VADC GLOBEVNP: REV0NP Mask              */\r
+\r
+/* ---------------------------------  VADC_GLOBTF  -------------------------------- */\r
+#define VADC_GLOBTF_CDGR_Pos                  4                                                       /*!< VADC GLOBTF: CDGR Position              */\r
+#define VADC_GLOBTF_CDGR_Msk                  (0x0fUL << VADC_GLOBTF_CDGR_Pos)                        /*!< VADC GLOBTF: CDGR Mask                  */\r
+#define VADC_GLOBTF_CDEN_Pos                  8                                                       /*!< VADC GLOBTF: CDEN Position              */\r
+#define VADC_GLOBTF_CDEN_Msk                  (0x01UL << VADC_GLOBTF_CDEN_Pos)                        /*!< VADC GLOBTF: CDEN Mask                  */\r
+#define VADC_GLOBTF_CDSEL_Pos                 9                                                       /*!< VADC GLOBTF: CDSEL Position             */\r
+#define VADC_GLOBTF_CDSEL_Msk                 (0x03UL << VADC_GLOBTF_CDSEL_Pos)                       /*!< VADC GLOBTF: CDSEL Mask                 */\r
+#define VADC_GLOBTF_CDWC_Pos                  15                                                      /*!< VADC GLOBTF: CDWC Position              */\r
+#define VADC_GLOBTF_CDWC_Msk                  (0x01UL << VADC_GLOBTF_CDWC_Pos)                        /*!< VADC GLOBTF: CDWC Mask                  */\r
+#define VADC_GLOBTF_PDD_Pos                   16                                                      /*!< VADC GLOBTF: PDD Position               */\r
+#define VADC_GLOBTF_PDD_Msk                   (0x01UL << VADC_GLOBTF_PDD_Pos)                         /*!< VADC GLOBTF: PDD Mask                   */\r
+#define VADC_GLOBTF_MDWC_Pos                  23                                                      /*!< VADC GLOBTF: MDWC Position              */\r
+#define VADC_GLOBTF_MDWC_Msk                  (0x01UL << VADC_GLOBTF_MDWC_Pos)                        /*!< VADC GLOBTF: MDWC Mask                  */\r
+\r
+/* ---------------------------------  VADC_BRSSEL  -------------------------------- */\r
+#define VADC_BRSSEL_CHSELG0_Pos               0                                                       /*!< VADC BRSSEL: CHSELG0 Position           */\r
+#define VADC_BRSSEL_CHSELG0_Msk               (0x01UL << VADC_BRSSEL_CHSELG0_Pos)                     /*!< VADC BRSSEL: CHSELG0 Mask               */\r
+#define VADC_BRSSEL_CHSELG1_Pos               1                                                       /*!< VADC BRSSEL: CHSELG1 Position           */\r
+#define VADC_BRSSEL_CHSELG1_Msk               (0x01UL << VADC_BRSSEL_CHSELG1_Pos)                     /*!< VADC BRSSEL: CHSELG1 Mask               */\r
+#define VADC_BRSSEL_CHSELG2_Pos               2                                                       /*!< VADC BRSSEL: CHSELG2 Position           */\r
+#define VADC_BRSSEL_CHSELG2_Msk               (0x01UL << VADC_BRSSEL_CHSELG2_Pos)                     /*!< VADC BRSSEL: CHSELG2 Mask               */\r
+#define VADC_BRSSEL_CHSELG3_Pos               3                                                       /*!< VADC BRSSEL: CHSELG3 Position           */\r
+#define VADC_BRSSEL_CHSELG3_Msk               (0x01UL << VADC_BRSSEL_CHSELG3_Pos)                     /*!< VADC BRSSEL: CHSELG3 Mask               */\r
+#define VADC_BRSSEL_CHSELG4_Pos               4                                                       /*!< VADC BRSSEL: CHSELG4 Position           */\r
+#define VADC_BRSSEL_CHSELG4_Msk               (0x01UL << VADC_BRSSEL_CHSELG4_Pos)                     /*!< VADC BRSSEL: CHSELG4 Mask               */\r
+#define VADC_BRSSEL_CHSELG5_Pos               5                                                       /*!< VADC BRSSEL: CHSELG5 Position           */\r
+#define VADC_BRSSEL_CHSELG5_Msk               (0x01UL << VADC_BRSSEL_CHSELG5_Pos)                     /*!< VADC BRSSEL: CHSELG5 Mask               */\r
+#define VADC_BRSSEL_CHSELG6_Pos               6                                                       /*!< VADC BRSSEL: CHSELG6 Position           */\r
+#define VADC_BRSSEL_CHSELG6_Msk               (0x01UL << VADC_BRSSEL_CHSELG6_Pos)                     /*!< VADC BRSSEL: CHSELG6 Mask               */\r
+#define VADC_BRSSEL_CHSELG7_Pos               7                                                       /*!< VADC BRSSEL: CHSELG7 Position           */\r
+#define VADC_BRSSEL_CHSELG7_Msk               (0x01UL << VADC_BRSSEL_CHSELG7_Pos)                     /*!< VADC BRSSEL: CHSELG7 Mask               */\r
+\r
+/* ---------------------------------  VADC_BRSPND  -------------------------------- */\r
+#define VADC_BRSPND_CHPNDG0_Pos               0                                                       /*!< VADC BRSPND: CHPNDG0 Position           */\r
+#define VADC_BRSPND_CHPNDG0_Msk               (0x01UL << VADC_BRSPND_CHPNDG0_Pos)                     /*!< VADC BRSPND: CHPNDG0 Mask               */\r
+#define VADC_BRSPND_CHPNDG1_Pos               1                                                       /*!< VADC BRSPND: CHPNDG1 Position           */\r
+#define VADC_BRSPND_CHPNDG1_Msk               (0x01UL << VADC_BRSPND_CHPNDG1_Pos)                     /*!< VADC BRSPND: CHPNDG1 Mask               */\r
+#define VADC_BRSPND_CHPNDG2_Pos               2                                                       /*!< VADC BRSPND: CHPNDG2 Position           */\r
+#define VADC_BRSPND_CHPNDG2_Msk               (0x01UL << VADC_BRSPND_CHPNDG2_Pos)                     /*!< VADC BRSPND: CHPNDG2 Mask               */\r
+#define VADC_BRSPND_CHPNDG3_Pos               3                                                       /*!< VADC BRSPND: CHPNDG3 Position           */\r
+#define VADC_BRSPND_CHPNDG3_Msk               (0x01UL << VADC_BRSPND_CHPNDG3_Pos)                     /*!< VADC BRSPND: CHPNDG3 Mask               */\r
+#define VADC_BRSPND_CHPNDG4_Pos               4                                                       /*!< VADC BRSPND: CHPNDG4 Position           */\r
+#define VADC_BRSPND_CHPNDG4_Msk               (0x01UL << VADC_BRSPND_CHPNDG4_Pos)                     /*!< VADC BRSPND: CHPNDG4 Mask               */\r
+#define VADC_BRSPND_CHPNDG5_Pos               5                                                       /*!< VADC BRSPND: CHPNDG5 Position           */\r
+#define VADC_BRSPND_CHPNDG5_Msk               (0x01UL << VADC_BRSPND_CHPNDG5_Pos)                     /*!< VADC BRSPND: CHPNDG5 Mask               */\r
+#define VADC_BRSPND_CHPNDG6_Pos               6                                                       /*!< VADC BRSPND: CHPNDG6 Position           */\r
+#define VADC_BRSPND_CHPNDG6_Msk               (0x01UL << VADC_BRSPND_CHPNDG6_Pos)                     /*!< VADC BRSPND: CHPNDG6 Mask               */\r
+#define VADC_BRSPND_CHPNDG7_Pos               7                                                       /*!< VADC BRSPND: CHPNDG7 Position           */\r
+#define VADC_BRSPND_CHPNDG7_Msk               (0x01UL << VADC_BRSPND_CHPNDG7_Pos)                     /*!< VADC BRSPND: CHPNDG7 Mask               */\r
+\r
+/* --------------------------------  VADC_BRSCTRL  -------------------------------- */\r
+#define VADC_BRSCTRL_XTSEL_Pos                8                                                       /*!< VADC BRSCTRL: XTSEL Position            */\r
+#define VADC_BRSCTRL_XTSEL_Msk                (0x0fUL << VADC_BRSCTRL_XTSEL_Pos)                      /*!< VADC BRSCTRL: XTSEL Mask                */\r
+#define VADC_BRSCTRL_XTLVL_Pos                12                                                      /*!< VADC BRSCTRL: XTLVL Position            */\r
+#define VADC_BRSCTRL_XTLVL_Msk                (0x01UL << VADC_BRSCTRL_XTLVL_Pos)                      /*!< VADC BRSCTRL: XTLVL Mask                */\r
+#define VADC_BRSCTRL_XTMODE_Pos               13                                                      /*!< VADC BRSCTRL: XTMODE Position           */\r
+#define VADC_BRSCTRL_XTMODE_Msk               (0x03UL << VADC_BRSCTRL_XTMODE_Pos)                     /*!< VADC BRSCTRL: XTMODE Mask               */\r
+#define VADC_BRSCTRL_XTWC_Pos                 15                                                      /*!< VADC BRSCTRL: XTWC Position             */\r
+#define VADC_BRSCTRL_XTWC_Msk                 (0x01UL << VADC_BRSCTRL_XTWC_Pos)                       /*!< VADC BRSCTRL: XTWC Mask                 */\r
+#define VADC_BRSCTRL_GTSEL_Pos                16                                                      /*!< VADC BRSCTRL: GTSEL Position            */\r
+#define VADC_BRSCTRL_GTSEL_Msk                (0x0fUL << VADC_BRSCTRL_GTSEL_Pos)                      /*!< VADC BRSCTRL: GTSEL Mask                */\r
+#define VADC_BRSCTRL_GTLVL_Pos                20                                                      /*!< VADC BRSCTRL: GTLVL Position            */\r
+#define VADC_BRSCTRL_GTLVL_Msk                (0x01UL << VADC_BRSCTRL_GTLVL_Pos)                      /*!< VADC BRSCTRL: GTLVL Mask                */\r
+#define VADC_BRSCTRL_GTWC_Pos                 23                                                      /*!< VADC BRSCTRL: GTWC Position             */\r
+#define VADC_BRSCTRL_GTWC_Msk                 (0x01UL << VADC_BRSCTRL_GTWC_Pos)                       /*!< VADC BRSCTRL: GTWC Mask                 */\r
+\r
+/* ---------------------------------  VADC_BRSMR  --------------------------------- */\r
+#define VADC_BRSMR_ENGT_Pos                   0                                                       /*!< VADC BRSMR: ENGT Position               */\r
+#define VADC_BRSMR_ENGT_Msk                   (0x03UL << VADC_BRSMR_ENGT_Pos)                         /*!< VADC BRSMR: ENGT Mask                   */\r
+#define VADC_BRSMR_ENTR_Pos                   2                                                       /*!< VADC BRSMR: ENTR Position               */\r
+#define VADC_BRSMR_ENTR_Msk                   (0x01UL << VADC_BRSMR_ENTR_Pos)                         /*!< VADC BRSMR: ENTR Mask                   */\r
+#define VADC_BRSMR_ENSI_Pos                   3                                                       /*!< VADC BRSMR: ENSI Position               */\r
+#define VADC_BRSMR_ENSI_Msk                   (0x01UL << VADC_BRSMR_ENSI_Pos)                         /*!< VADC BRSMR: ENSI Mask                   */\r
+#define VADC_BRSMR_SCAN_Pos                   4                                                       /*!< VADC BRSMR: SCAN Position               */\r
+#define VADC_BRSMR_SCAN_Msk                   (0x01UL << VADC_BRSMR_SCAN_Pos)                         /*!< VADC BRSMR: SCAN Mask                   */\r
+#define VADC_BRSMR_LDM_Pos                    5                                                       /*!< VADC BRSMR: LDM Position                */\r
+#define VADC_BRSMR_LDM_Msk                    (0x01UL << VADC_BRSMR_LDM_Pos)                          /*!< VADC BRSMR: LDM Mask                    */\r
+#define VADC_BRSMR_REQGT_Pos                  7                                                       /*!< VADC BRSMR: REQGT Position              */\r
+#define VADC_BRSMR_REQGT_Msk                  (0x01UL << VADC_BRSMR_REQGT_Pos)                        /*!< VADC BRSMR: REQGT Mask                  */\r
+#define VADC_BRSMR_CLRPND_Pos                 8                                                       /*!< VADC BRSMR: CLRPND Position             */\r
+#define VADC_BRSMR_CLRPND_Msk                 (0x01UL << VADC_BRSMR_CLRPND_Pos)                       /*!< VADC BRSMR: CLRPND Mask                 */\r
+#define VADC_BRSMR_LDEV_Pos                   9                                                       /*!< VADC BRSMR: LDEV Position               */\r
+#define VADC_BRSMR_LDEV_Msk                   (0x01UL << VADC_BRSMR_LDEV_Pos)                         /*!< VADC BRSMR: LDEV Mask                   */\r
+#define VADC_BRSMR_RPTDIS_Pos                 16                                                      /*!< VADC BRSMR: RPTDIS Position             */\r
+#define VADC_BRSMR_RPTDIS_Msk                 (0x01UL << VADC_BRSMR_RPTDIS_Pos)                       /*!< VADC BRSMR: RPTDIS Mask                 */\r
+\r
+/* --------------------------------  VADC_GLOBRCR  -------------------------------- */\r
+#define VADC_GLOBRCR_DRCTR_Pos                16                                                      /*!< VADC GLOBRCR: DRCTR Position            */\r
+#define VADC_GLOBRCR_DRCTR_Msk                (0x0fUL << VADC_GLOBRCR_DRCTR_Pos)                      /*!< VADC GLOBRCR: DRCTR Mask                */\r
+#define VADC_GLOBRCR_WFR_Pos                  24                                                      /*!< VADC GLOBRCR: WFR Position              */\r
+#define VADC_GLOBRCR_WFR_Msk                  (0x01UL << VADC_GLOBRCR_WFR_Pos)                        /*!< VADC GLOBRCR: WFR Mask                  */\r
+#define VADC_GLOBRCR_SRGEN_Pos                31                                                      /*!< VADC GLOBRCR: SRGEN Position            */\r
+#define VADC_GLOBRCR_SRGEN_Msk                (0x01UL << VADC_GLOBRCR_SRGEN_Pos)                      /*!< VADC GLOBRCR: SRGEN Mask                */\r
+\r
+/* --------------------------------  VADC_GLOBRES  -------------------------------- */\r
+#define VADC_GLOBRES_RESULT_Pos               0                                                       /*!< VADC GLOBRES: RESULT Position           */\r
+#define VADC_GLOBRES_RESULT_Msk               (0x0000ffffUL << VADC_GLOBRES_RESULT_Pos)               /*!< VADC GLOBRES: RESULT Mask               */\r
+#define VADC_GLOBRES_GNR_Pos                  16                                                      /*!< VADC GLOBRES: GNR Position              */\r
+#define VADC_GLOBRES_GNR_Msk                  (0x0fUL << VADC_GLOBRES_GNR_Pos)                        /*!< VADC GLOBRES: GNR Mask                  */\r
+#define VADC_GLOBRES_CHNR_Pos                 20                                                      /*!< VADC GLOBRES: CHNR Position             */\r
+#define VADC_GLOBRES_CHNR_Msk                 (0x1fUL << VADC_GLOBRES_CHNR_Pos)                       /*!< VADC GLOBRES: CHNR Mask                 */\r
+#define VADC_GLOBRES_EMUX_Pos                 25                                                      /*!< VADC GLOBRES: EMUX Position             */\r
+#define VADC_GLOBRES_EMUX_Msk                 (0x07UL << VADC_GLOBRES_EMUX_Pos)                       /*!< VADC GLOBRES: EMUX Mask                 */\r
+#define VADC_GLOBRES_CRS_Pos                  28                                                      /*!< VADC GLOBRES: CRS Position              */\r
+#define VADC_GLOBRES_CRS_Msk                  (0x03UL << VADC_GLOBRES_CRS_Pos)                        /*!< VADC GLOBRES: CRS Mask                  */\r
+#define VADC_GLOBRES_FCR_Pos                  30                                                      /*!< VADC GLOBRES: FCR Position              */\r
+#define VADC_GLOBRES_FCR_Msk                  (0x01UL << VADC_GLOBRES_FCR_Pos)                        /*!< VADC GLOBRES: FCR Mask                  */\r
+#define VADC_GLOBRES_VF_Pos                   31                                                      /*!< VADC GLOBRES: VF Position               */\r
+#define VADC_GLOBRES_VF_Msk                   (0x01UL << VADC_GLOBRES_VF_Pos)                         /*!< VADC GLOBRES: VF Mask                   */\r
+\r
+/* --------------------------------  VADC_GLOBRESD  ------------------------------- */\r
+#define VADC_GLOBRESD_RESULT_Pos              0                                                       /*!< VADC GLOBRESD: RESULT Position          */\r
+#define VADC_GLOBRESD_RESULT_Msk              (0x0000ffffUL << VADC_GLOBRESD_RESULT_Pos)              /*!< VADC GLOBRESD: RESULT Mask              */\r
+#define VADC_GLOBRESD_GNR_Pos                 16                                                      /*!< VADC GLOBRESD: GNR Position             */\r
+#define VADC_GLOBRESD_GNR_Msk                 (0x0fUL << VADC_GLOBRESD_GNR_Pos)                       /*!< VADC GLOBRESD: GNR Mask                 */\r
+#define VADC_GLOBRESD_CHNR_Pos                20                                                      /*!< VADC GLOBRESD: CHNR Position            */\r
+#define VADC_GLOBRESD_CHNR_Msk                (0x1fUL << VADC_GLOBRESD_CHNR_Pos)                      /*!< VADC GLOBRESD: CHNR Mask                */\r
+#define VADC_GLOBRESD_EMUX_Pos                25                                                      /*!< VADC GLOBRESD: EMUX Position            */\r
+#define VADC_GLOBRESD_EMUX_Msk                (0x07UL << VADC_GLOBRESD_EMUX_Pos)                      /*!< VADC GLOBRESD: EMUX Mask                */\r
+#define VADC_GLOBRESD_CRS_Pos                 28                                                      /*!< VADC GLOBRESD: CRS Position             */\r
+#define VADC_GLOBRESD_CRS_Msk                 (0x03UL << VADC_GLOBRESD_CRS_Pos)                       /*!< VADC GLOBRESD: CRS Mask                 */\r
+#define VADC_GLOBRESD_FCR_Pos                 30                                                      /*!< VADC GLOBRESD: FCR Position             */\r
+#define VADC_GLOBRESD_FCR_Msk                 (0x01UL << VADC_GLOBRESD_FCR_Pos)                       /*!< VADC GLOBRESD: FCR Mask                 */\r
+#define VADC_GLOBRESD_VF_Pos                  31                                                      /*!< VADC GLOBRESD: VF Position              */\r
+#define VADC_GLOBRESD_VF_Msk                  (0x01UL << VADC_GLOBRESD_VF_Pos)                        /*!< VADC GLOBRESD: VF Mask                  */\r
+\r
+/* --------------------------------  VADC_EMUXSEL  -------------------------------- */\r
+#define VADC_EMUXSEL_EMUXGRP0_Pos             0                                                       /*!< VADC EMUXSEL: EMUXGRP0 Position         */\r
+#define VADC_EMUXSEL_EMUXGRP0_Msk             (0x0fUL << VADC_EMUXSEL_EMUXGRP0_Pos)                   /*!< VADC EMUXSEL: EMUXGRP0 Mask             */\r
+#define VADC_EMUXSEL_EMUXGRP1_Pos             4                                                       /*!< VADC EMUXSEL: EMUXGRP1 Position         */\r
+#define VADC_EMUXSEL_EMUXGRP1_Msk             (0x0fUL << VADC_EMUXSEL_EMUXGRP1_Pos)                   /*!< VADC EMUXSEL: EMUXGRP1 Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'VADC_G' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  VADC_G_ARBCFG  ------------------------------- */\r
+#define VADC_G_ARBCFG_ANONC_Pos               0                                                       /*!< VADC_G ARBCFG: ANONC Position           */\r
+#define VADC_G_ARBCFG_ANONC_Msk               (0x03UL << VADC_G_ARBCFG_ANONC_Pos)                     /*!< VADC_G ARBCFG: ANONC Mask               */\r
+#define VADC_G_ARBCFG_ARBRND_Pos              4                                                       /*!< VADC_G ARBCFG: ARBRND Position          */\r
+#define VADC_G_ARBCFG_ARBRND_Msk              (0x03UL << VADC_G_ARBCFG_ARBRND_Pos)                    /*!< VADC_G ARBCFG: ARBRND Mask              */\r
+#define VADC_G_ARBCFG_ARBM_Pos                7                                                       /*!< VADC_G ARBCFG: ARBM Position            */\r
+#define VADC_G_ARBCFG_ARBM_Msk                (0x01UL << VADC_G_ARBCFG_ARBM_Pos)                      /*!< VADC_G ARBCFG: ARBM Mask                */\r
+#define VADC_G_ARBCFG_ANONS_Pos               16                                                      /*!< VADC_G ARBCFG: ANONS Position           */\r
+#define VADC_G_ARBCFG_ANONS_Msk               (0x03UL << VADC_G_ARBCFG_ANONS_Pos)                     /*!< VADC_G ARBCFG: ANONS Mask               */\r
+#define VADC_G_ARBCFG_CAL_Pos                 28                                                      /*!< VADC_G ARBCFG: CAL Position             */\r
+#define VADC_G_ARBCFG_CAL_Msk                 (0x01UL << VADC_G_ARBCFG_CAL_Pos)                       /*!< VADC_G ARBCFG: CAL Mask                 */\r
+#define VADC_G_ARBCFG_BUSY_Pos                30                                                      /*!< VADC_G ARBCFG: BUSY Position            */\r
+#define VADC_G_ARBCFG_BUSY_Msk                (0x01UL << VADC_G_ARBCFG_BUSY_Pos)                      /*!< VADC_G ARBCFG: BUSY Mask                */\r
+#define VADC_G_ARBCFG_SAMPLE_Pos              31                                                      /*!< VADC_G ARBCFG: SAMPLE Position          */\r
+#define VADC_G_ARBCFG_SAMPLE_Msk              (0x01UL << VADC_G_ARBCFG_SAMPLE_Pos)                    /*!< VADC_G ARBCFG: SAMPLE Mask              */\r
+\r
+/* --------------------------------  VADC_G_ARBPR  -------------------------------- */\r
+#define VADC_G_ARBPR_PRIO0_Pos                0                                                       /*!< VADC_G ARBPR: PRIO0 Position            */\r
+#define VADC_G_ARBPR_PRIO0_Msk                (0x03UL << VADC_G_ARBPR_PRIO0_Pos)                      /*!< VADC_G ARBPR: PRIO0 Mask                */\r
+#define VADC_G_ARBPR_CSM0_Pos                 3                                                       /*!< VADC_G ARBPR: CSM0 Position             */\r
+#define VADC_G_ARBPR_CSM0_Msk                 (0x01UL << VADC_G_ARBPR_CSM0_Pos)                       /*!< VADC_G ARBPR: CSM0 Mask                 */\r
+#define VADC_G_ARBPR_PRIO1_Pos                4                                                       /*!< VADC_G ARBPR: PRIO1 Position            */\r
+#define VADC_G_ARBPR_PRIO1_Msk                (0x03UL << VADC_G_ARBPR_PRIO1_Pos)                      /*!< VADC_G ARBPR: PRIO1 Mask                */\r
+#define VADC_G_ARBPR_CSM1_Pos                 7                                                       /*!< VADC_G ARBPR: CSM1 Position             */\r
+#define VADC_G_ARBPR_CSM1_Msk                 (0x01UL << VADC_G_ARBPR_CSM1_Pos)                       /*!< VADC_G ARBPR: CSM1 Mask                 */\r
+#define VADC_G_ARBPR_PRIO2_Pos                8                                                       /*!< VADC_G ARBPR: PRIO2 Position            */\r
+#define VADC_G_ARBPR_PRIO2_Msk                (0x03UL << VADC_G_ARBPR_PRIO2_Pos)                      /*!< VADC_G ARBPR: PRIO2 Mask                */\r
+#define VADC_G_ARBPR_CSM2_Pos                 11                                                      /*!< VADC_G ARBPR: CSM2 Position             */\r
+#define VADC_G_ARBPR_CSM2_Msk                 (0x01UL << VADC_G_ARBPR_CSM2_Pos)                       /*!< VADC_G ARBPR: CSM2 Mask                 */\r
+#define VADC_G_ARBPR_ASEN0_Pos                24                                                      /*!< VADC_G ARBPR: ASEN0 Position            */\r
+#define VADC_G_ARBPR_ASEN0_Msk                (0x01UL << VADC_G_ARBPR_ASEN0_Pos)                      /*!< VADC_G ARBPR: ASEN0 Mask                */\r
+#define VADC_G_ARBPR_ASEN1_Pos                25                                                      /*!< VADC_G ARBPR: ASEN1 Position            */\r
+#define VADC_G_ARBPR_ASEN1_Msk                (0x01UL << VADC_G_ARBPR_ASEN1_Pos)                      /*!< VADC_G ARBPR: ASEN1 Mask                */\r
+#define VADC_G_ARBPR_ASEN2_Pos                26                                                      /*!< VADC_G ARBPR: ASEN2 Position            */\r
+#define VADC_G_ARBPR_ASEN2_Msk                (0x01UL << VADC_G_ARBPR_ASEN2_Pos)                      /*!< VADC_G ARBPR: ASEN2 Mask                */\r
+\r
+/* --------------------------------  VADC_G_CHASS  -------------------------------- */\r
+#define VADC_G_CHASS_ASSCH0_Pos               0                                                       /*!< VADC_G CHASS: ASSCH0 Position           */\r
+#define VADC_G_CHASS_ASSCH0_Msk               (0x01UL << VADC_G_CHASS_ASSCH0_Pos)                     /*!< VADC_G CHASS: ASSCH0 Mask               */\r
+#define VADC_G_CHASS_ASSCH1_Pos               1                                                       /*!< VADC_G CHASS: ASSCH1 Position           */\r
+#define VADC_G_CHASS_ASSCH1_Msk               (0x01UL << VADC_G_CHASS_ASSCH1_Pos)                     /*!< VADC_G CHASS: ASSCH1 Mask               */\r
+#define VADC_G_CHASS_ASSCH2_Pos               2                                                       /*!< VADC_G CHASS: ASSCH2 Position           */\r
+#define VADC_G_CHASS_ASSCH2_Msk               (0x01UL << VADC_G_CHASS_ASSCH2_Pos)                     /*!< VADC_G CHASS: ASSCH2 Mask               */\r
+#define VADC_G_CHASS_ASSCH3_Pos               3                                                       /*!< VADC_G CHASS: ASSCH3 Position           */\r
+#define VADC_G_CHASS_ASSCH3_Msk               (0x01UL << VADC_G_CHASS_ASSCH3_Pos)                     /*!< VADC_G CHASS: ASSCH3 Mask               */\r
+#define VADC_G_CHASS_ASSCH4_Pos               4                                                       /*!< VADC_G CHASS: ASSCH4 Position           */\r
+#define VADC_G_CHASS_ASSCH4_Msk               (0x01UL << VADC_G_CHASS_ASSCH4_Pos)                     /*!< VADC_G CHASS: ASSCH4 Mask               */\r
+#define VADC_G_CHASS_ASSCH5_Pos               5                                                       /*!< VADC_G CHASS: ASSCH5 Position           */\r
+#define VADC_G_CHASS_ASSCH5_Msk               (0x01UL << VADC_G_CHASS_ASSCH5_Pos)                     /*!< VADC_G CHASS: ASSCH5 Mask               */\r
+#define VADC_G_CHASS_ASSCH6_Pos               6                                                       /*!< VADC_G CHASS: ASSCH6 Position           */\r
+#define VADC_G_CHASS_ASSCH6_Msk               (0x01UL << VADC_G_CHASS_ASSCH6_Pos)                     /*!< VADC_G CHASS: ASSCH6 Mask               */\r
+#define VADC_G_CHASS_ASSCH7_Pos               7                                                       /*!< VADC_G CHASS: ASSCH7 Position           */\r
+#define VADC_G_CHASS_ASSCH7_Msk               (0x01UL << VADC_G_CHASS_ASSCH7_Pos)                     /*!< VADC_G CHASS: ASSCH7 Mask               */\r
+\r
+/* --------------------------------  VADC_G_ICLASS  ------------------------------- */\r
+#define VADC_G_ICLASS_STCS_Pos                0                                                       /*!< VADC_G ICLASS: STCS Position            */\r
+#define VADC_G_ICLASS_STCS_Msk                (0x1fUL << VADC_G_ICLASS_STCS_Pos)                      /*!< VADC_G ICLASS: STCS Mask                */\r
+#define VADC_G_ICLASS_CMS_Pos                 8                                                       /*!< VADC_G ICLASS: CMS Position             */\r
+#define VADC_G_ICLASS_CMS_Msk                 (0x07UL << VADC_G_ICLASS_CMS_Pos)                       /*!< VADC_G ICLASS: CMS Mask                 */\r
+#define VADC_G_ICLASS_STCE_Pos                16                                                      /*!< VADC_G ICLASS: STCE Position            */\r
+#define VADC_G_ICLASS_STCE_Msk                (0x1fUL << VADC_G_ICLASS_STCE_Pos)                      /*!< VADC_G ICLASS: STCE Mask                */\r
+#define VADC_G_ICLASS_CME_Pos                 24                                                      /*!< VADC_G ICLASS: CME Position             */\r
+#define VADC_G_ICLASS_CME_Msk                 (0x07UL << VADC_G_ICLASS_CME_Pos)                       /*!< VADC_G ICLASS: CME Mask                 */\r
+\r
+/* --------------------------------  VADC_G_ALIAS  -------------------------------- */\r
+#define VADC_G_ALIAS_ALIAS0_Pos               0                                                       /*!< VADC_G ALIAS: ALIAS0 Position           */\r
+#define VADC_G_ALIAS_ALIAS0_Msk               (0x1fUL << VADC_G_ALIAS_ALIAS0_Pos)                     /*!< VADC_G ALIAS: ALIAS0 Mask               */\r
+#define VADC_G_ALIAS_ALIAS1_Pos               8                                                       /*!< VADC_G ALIAS: ALIAS1 Position           */\r
+#define VADC_G_ALIAS_ALIAS1_Msk               (0x1fUL << VADC_G_ALIAS_ALIAS1_Pos)                     /*!< VADC_G ALIAS: ALIAS1 Mask               */\r
+\r
+/* --------------------------------  VADC_G_BOUND  -------------------------------- */\r
+#define VADC_G_BOUND_BOUNDARY0_Pos            0                                                       /*!< VADC_G BOUND: BOUNDARY0 Position        */\r
+#define VADC_G_BOUND_BOUNDARY0_Msk            (0x00000fffUL << VADC_G_BOUND_BOUNDARY0_Pos)            /*!< VADC_G BOUND: BOUNDARY0 Mask            */\r
+#define VADC_G_BOUND_BOUNDARY1_Pos            16                                                      /*!< VADC_G BOUND: BOUNDARY1 Position        */\r
+#define VADC_G_BOUND_BOUNDARY1_Msk            (0x00000fffUL << VADC_G_BOUND_BOUNDARY1_Pos)            /*!< VADC_G BOUND: BOUNDARY1 Mask            */\r
+\r
+/* --------------------------------  VADC_G_SYNCTR  ------------------------------- */\r
+#define VADC_G_SYNCTR_STSEL_Pos               0                                                       /*!< VADC_G SYNCTR: STSEL Position           */\r
+#define VADC_G_SYNCTR_STSEL_Msk               (0x03UL << VADC_G_SYNCTR_STSEL_Pos)                     /*!< VADC_G SYNCTR: STSEL Mask               */\r
+#define VADC_G_SYNCTR_EVALR1_Pos              4                                                       /*!< VADC_G SYNCTR: EVALR1 Position          */\r
+#define VADC_G_SYNCTR_EVALR1_Msk              (0x01UL << VADC_G_SYNCTR_EVALR1_Pos)                    /*!< VADC_G SYNCTR: EVALR1 Mask              */\r
+#define VADC_G_SYNCTR_EVALR2_Pos              5                                                       /*!< VADC_G SYNCTR: EVALR2 Position          */\r
+#define VADC_G_SYNCTR_EVALR2_Msk              (0x01UL << VADC_G_SYNCTR_EVALR2_Pos)                    /*!< VADC_G SYNCTR: EVALR2 Mask              */\r
+#define VADC_G_SYNCTR_EVALR3_Pos              6                                                       /*!< VADC_G SYNCTR: EVALR3 Position          */\r
+#define VADC_G_SYNCTR_EVALR3_Msk              (0x01UL << VADC_G_SYNCTR_EVALR3_Pos)                    /*!< VADC_G SYNCTR: EVALR3 Mask              */\r
+\r
+/* ---------------------------------  VADC_G_BFL  --------------------------------- */\r
+#define VADC_G_BFL_BFL0_Pos                   0                                                       /*!< VADC_G BFL: BFL0 Position               */\r
+#define VADC_G_BFL_BFL0_Msk                   (0x01UL << VADC_G_BFL_BFL0_Pos)                         /*!< VADC_G BFL: BFL0 Mask                   */\r
+#define VADC_G_BFL_BFL1_Pos                   1                                                       /*!< VADC_G BFL: BFL1 Position               */\r
+#define VADC_G_BFL_BFL1_Msk                   (0x01UL << VADC_G_BFL_BFL1_Pos)                         /*!< VADC_G BFL: BFL1 Mask                   */\r
+#define VADC_G_BFL_BFL2_Pos                   2                                                       /*!< VADC_G BFL: BFL2 Position               */\r
+#define VADC_G_BFL_BFL2_Msk                   (0x01UL << VADC_G_BFL_BFL2_Pos)                         /*!< VADC_G BFL: BFL2 Mask                   */\r
+#define VADC_G_BFL_BFL3_Pos                   3                                                       /*!< VADC_G BFL: BFL3 Position               */\r
+#define VADC_G_BFL_BFL3_Msk                   (0x01UL << VADC_G_BFL_BFL3_Pos)                         /*!< VADC_G BFL: BFL3 Mask                   */\r
+#define VADC_G_BFL_BFE0_Pos                   16                                                      /*!< VADC_G BFL: BFE0 Position               */\r
+#define VADC_G_BFL_BFE0_Msk                   (0x01UL << VADC_G_BFL_BFE0_Pos)                         /*!< VADC_G BFL: BFE0 Mask                   */\r
+#define VADC_G_BFL_BFE1_Pos                   17                                                      /*!< VADC_G BFL: BFE1 Position               */\r
+#define VADC_G_BFL_BFE1_Msk                   (0x01UL << VADC_G_BFL_BFE1_Pos)                         /*!< VADC_G BFL: BFE1 Mask                   */\r
+#define VADC_G_BFL_BFE2_Pos                   18                                                      /*!< VADC_G BFL: BFE2 Position               */\r
+#define VADC_G_BFL_BFE2_Msk                   (0x01UL << VADC_G_BFL_BFE2_Pos)                         /*!< VADC_G BFL: BFE2 Mask                   */\r
+#define VADC_G_BFL_BFE3_Pos                   19                                                      /*!< VADC_G BFL: BFE3 Position               */\r
+#define VADC_G_BFL_BFE3_Msk                   (0x01UL << VADC_G_BFL_BFE3_Pos)                         /*!< VADC_G BFL: BFE3 Mask                   */\r
+\r
+/* --------------------------------  VADC_G_QCTRL0  ------------------------------- */\r
+#define VADC_G_QCTRL0_XTSEL_Pos               8                                                       /*!< VADC_G QCTRL0: XTSEL Position           */\r
+#define VADC_G_QCTRL0_XTSEL_Msk               (0x0fUL << VADC_G_QCTRL0_XTSEL_Pos)                     /*!< VADC_G QCTRL0: XTSEL Mask               */\r
+#define VADC_G_QCTRL0_XTLVL_Pos               12                                                      /*!< VADC_G QCTRL0: XTLVL Position           */\r
+#define VADC_G_QCTRL0_XTLVL_Msk               (0x01UL << VADC_G_QCTRL0_XTLVL_Pos)                     /*!< VADC_G QCTRL0: XTLVL Mask               */\r
+#define VADC_G_QCTRL0_XTMODE_Pos              13                                                      /*!< VADC_G QCTRL0: XTMODE Position          */\r
+#define VADC_G_QCTRL0_XTMODE_Msk              (0x03UL << VADC_G_QCTRL0_XTMODE_Pos)                    /*!< VADC_G QCTRL0: XTMODE Mask              */\r
+#define VADC_G_QCTRL0_XTWC_Pos                15                                                      /*!< VADC_G QCTRL0: XTWC Position            */\r
+#define VADC_G_QCTRL0_XTWC_Msk                (0x01UL << VADC_G_QCTRL0_XTWC_Pos)                      /*!< VADC_G QCTRL0: XTWC Mask                */\r
+#define VADC_G_QCTRL0_GTSEL_Pos               16                                                      /*!< VADC_G QCTRL0: GTSEL Position           */\r
+#define VADC_G_QCTRL0_GTSEL_Msk               (0x0fUL << VADC_G_QCTRL0_GTSEL_Pos)                     /*!< VADC_G QCTRL0: GTSEL Mask               */\r
+#define VADC_G_QCTRL0_GTLVL_Pos               20                                                      /*!< VADC_G QCTRL0: GTLVL Position           */\r
+#define VADC_G_QCTRL0_GTLVL_Msk               (0x01UL << VADC_G_QCTRL0_GTLVL_Pos)                     /*!< VADC_G QCTRL0: GTLVL Mask               */\r
+#define VADC_G_QCTRL0_GTWC_Pos                23                                                      /*!< VADC_G QCTRL0: GTWC Position            */\r
+#define VADC_G_QCTRL0_GTWC_Msk                (0x01UL << VADC_G_QCTRL0_GTWC_Pos)                      /*!< VADC_G QCTRL0: GTWC Mask                */\r
+#define VADC_G_QCTRL0_TMEN_Pos                28                                                      /*!< VADC_G QCTRL0: TMEN Position            */\r
+#define VADC_G_QCTRL0_TMEN_Msk                (0x01UL << VADC_G_QCTRL0_TMEN_Pos)                      /*!< VADC_G QCTRL0: TMEN Mask                */\r
+#define VADC_G_QCTRL0_TMWC_Pos                31                                                      /*!< VADC_G QCTRL0: TMWC Position            */\r
+#define VADC_G_QCTRL0_TMWC_Msk                (0x01UL << VADC_G_QCTRL0_TMWC_Pos)                      /*!< VADC_G QCTRL0: TMWC Mask                */\r
+\r
+/* ---------------------------------  VADC_G_QMR0  -------------------------------- */\r
+#define VADC_G_QMR0_ENGT_Pos                  0                                                       /*!< VADC_G QMR0: ENGT Position              */\r
+#define VADC_G_QMR0_ENGT_Msk                  (0x03UL << VADC_G_QMR0_ENGT_Pos)                        /*!< VADC_G QMR0: ENGT Mask                  */\r
+#define VADC_G_QMR0_ENTR_Pos                  2                                                       /*!< VADC_G QMR0: ENTR Position              */\r
+#define VADC_G_QMR0_ENTR_Msk                  (0x01UL << VADC_G_QMR0_ENTR_Pos)                        /*!< VADC_G QMR0: ENTR Mask                  */\r
+#define VADC_G_QMR0_CLRV_Pos                  8                                                       /*!< VADC_G QMR0: CLRV Position              */\r
+#define VADC_G_QMR0_CLRV_Msk                  (0x01UL << VADC_G_QMR0_CLRV_Pos)                        /*!< VADC_G QMR0: CLRV Mask                  */\r
+#define VADC_G_QMR0_TREV_Pos                  9                                                       /*!< VADC_G QMR0: TREV Position              */\r
+#define VADC_G_QMR0_TREV_Msk                  (0x01UL << VADC_G_QMR0_TREV_Pos)                        /*!< VADC_G QMR0: TREV Mask                  */\r
+#define VADC_G_QMR0_FLUSH_Pos                 10                                                      /*!< VADC_G QMR0: FLUSH Position             */\r
+#define VADC_G_QMR0_FLUSH_Msk                 (0x01UL << VADC_G_QMR0_FLUSH_Pos)                       /*!< VADC_G QMR0: FLUSH Mask                 */\r
+#define VADC_G_QMR0_CEV_Pos                   11                                                      /*!< VADC_G QMR0: CEV Position               */\r
+#define VADC_G_QMR0_CEV_Msk                   (0x01UL << VADC_G_QMR0_CEV_Pos)                         /*!< VADC_G QMR0: CEV Mask                   */\r
+#define VADC_G_QMR0_RPTDIS_Pos                16                                                      /*!< VADC_G QMR0: RPTDIS Position            */\r
+#define VADC_G_QMR0_RPTDIS_Msk                (0x01UL << VADC_G_QMR0_RPTDIS_Pos)                      /*!< VADC_G QMR0: RPTDIS Mask                */\r
+\r
+/* ---------------------------------  VADC_G_QSR0  -------------------------------- */\r
+#define VADC_G_QSR0_FILL_Pos                  0                                                       /*!< VADC_G QSR0: FILL Position              */\r
+#define VADC_G_QSR0_FILL_Msk                  (0x0fUL << VADC_G_QSR0_FILL_Pos)                        /*!< VADC_G QSR0: FILL Mask                  */\r
+#define VADC_G_QSR0_EMPTY_Pos                 5                                                       /*!< VADC_G QSR0: EMPTY Position             */\r
+#define VADC_G_QSR0_EMPTY_Msk                 (0x01UL << VADC_G_QSR0_EMPTY_Pos)                       /*!< VADC_G QSR0: EMPTY Mask                 */\r
+#define VADC_G_QSR0_REQGT_Pos                 7                                                       /*!< VADC_G QSR0: REQGT Position             */\r
+#define VADC_G_QSR0_REQGT_Msk                 (0x01UL << VADC_G_QSR0_REQGT_Pos)                       /*!< VADC_G QSR0: REQGT Mask                 */\r
+#define VADC_G_QSR0_EV_Pos                    8                                                       /*!< VADC_G QSR0: EV Position                */\r
+#define VADC_G_QSR0_EV_Msk                    (0x01UL << VADC_G_QSR0_EV_Pos)                          /*!< VADC_G QSR0: EV Mask                    */\r
+\r
+/* ---------------------------------  VADC_G_Q0R0  -------------------------------- */\r
+#define VADC_G_Q0R0_REQCHNR_Pos               0                                                       /*!< VADC_G Q0R0: REQCHNR Position           */\r
+#define VADC_G_Q0R0_REQCHNR_Msk               (0x1fUL << VADC_G_Q0R0_REQCHNR_Pos)                     /*!< VADC_G Q0R0: REQCHNR Mask               */\r
+#define VADC_G_Q0R0_RF_Pos                    5                                                       /*!< VADC_G Q0R0: RF Position                */\r
+#define VADC_G_Q0R0_RF_Msk                    (0x01UL << VADC_G_Q0R0_RF_Pos)                          /*!< VADC_G Q0R0: RF Mask                    */\r
+#define VADC_G_Q0R0_ENSI_Pos                  6                                                       /*!< VADC_G Q0R0: ENSI Position              */\r
+#define VADC_G_Q0R0_ENSI_Msk                  (0x01UL << VADC_G_Q0R0_ENSI_Pos)                        /*!< VADC_G Q0R0: ENSI Mask                  */\r
+#define VADC_G_Q0R0_EXTR_Pos                  7                                                       /*!< VADC_G Q0R0: EXTR Position              */\r
+#define VADC_G_Q0R0_EXTR_Msk                  (0x01UL << VADC_G_Q0R0_EXTR_Pos)                        /*!< VADC_G Q0R0: EXTR Mask                  */\r
+#define VADC_G_Q0R0_V_Pos                     8                                                       /*!< VADC_G Q0R0: V Position                 */\r
+#define VADC_G_Q0R0_V_Msk                     (0x01UL << VADC_G_Q0R0_V_Pos)                           /*!< VADC_G Q0R0: V Mask                     */\r
+\r
+/* --------------------------------  VADC_G_QINR0  -------------------------------- */\r
+#define VADC_G_QINR0_REQCHNR_Pos              0                                                       /*!< VADC_G QINR0: REQCHNR Position          */\r
+#define VADC_G_QINR0_REQCHNR_Msk              (0x1fUL << VADC_G_QINR0_REQCHNR_Pos)                    /*!< VADC_G QINR0: REQCHNR Mask              */\r
+#define VADC_G_QINR0_RF_Pos                   5                                                       /*!< VADC_G QINR0: RF Position               */\r
+#define VADC_G_QINR0_RF_Msk                   (0x01UL << VADC_G_QINR0_RF_Pos)                         /*!< VADC_G QINR0: RF Mask                   */\r
+#define VADC_G_QINR0_ENSI_Pos                 6                                                       /*!< VADC_G QINR0: ENSI Position             */\r
+#define VADC_G_QINR0_ENSI_Msk                 (0x01UL << VADC_G_QINR0_ENSI_Pos)                       /*!< VADC_G QINR0: ENSI Mask                 */\r
+#define VADC_G_QINR0_EXTR_Pos                 7                                                       /*!< VADC_G QINR0: EXTR Position             */\r
+#define VADC_G_QINR0_EXTR_Msk                 (0x01UL << VADC_G_QINR0_EXTR_Pos)                       /*!< VADC_G QINR0: EXTR Mask                 */\r
+\r
+/* --------------------------------  VADC_G_QBUR0  -------------------------------- */\r
+#define VADC_G_QBUR0_REQCHNR_Pos              0                                                       /*!< VADC_G QBUR0: REQCHNR Position          */\r
+#define VADC_G_QBUR0_REQCHNR_Msk              (0x1fUL << VADC_G_QBUR0_REQCHNR_Pos)                    /*!< VADC_G QBUR0: REQCHNR Mask              */\r
+#define VADC_G_QBUR0_RF_Pos                   5                                                       /*!< VADC_G QBUR0: RF Position               */\r
+#define VADC_G_QBUR0_RF_Msk                   (0x01UL << VADC_G_QBUR0_RF_Pos)                         /*!< VADC_G QBUR0: RF Mask                   */\r
+#define VADC_G_QBUR0_ENSI_Pos                 6                                                       /*!< VADC_G QBUR0: ENSI Position             */\r
+#define VADC_G_QBUR0_ENSI_Msk                 (0x01UL << VADC_G_QBUR0_ENSI_Pos)                       /*!< VADC_G QBUR0: ENSI Mask                 */\r
+#define VADC_G_QBUR0_EXTR_Pos                 7                                                       /*!< VADC_G QBUR0: EXTR Position             */\r
+#define VADC_G_QBUR0_EXTR_Msk                 (0x01UL << VADC_G_QBUR0_EXTR_Pos)                       /*!< VADC_G QBUR0: EXTR Mask                 */\r
+#define VADC_G_QBUR0_V_Pos                    8                                                       /*!< VADC_G QBUR0: V Position                */\r
+#define VADC_G_QBUR0_V_Msk                    (0x01UL << VADC_G_QBUR0_V_Pos)                          /*!< VADC_G QBUR0: V Mask                    */\r
+\r
+/* --------------------------------  VADC_G_ASCTRL  ------------------------------- */\r
+#define VADC_G_ASCTRL_XTSEL_Pos               8                                                       /*!< VADC_G ASCTRL: XTSEL Position           */\r
+#define VADC_G_ASCTRL_XTSEL_Msk               (0x0fUL << VADC_G_ASCTRL_XTSEL_Pos)                     /*!< VADC_G ASCTRL: XTSEL Mask               */\r
+#define VADC_G_ASCTRL_XTLVL_Pos               12                                                      /*!< VADC_G ASCTRL: XTLVL Position           */\r
+#define VADC_G_ASCTRL_XTLVL_Msk               (0x01UL << VADC_G_ASCTRL_XTLVL_Pos)                     /*!< VADC_G ASCTRL: XTLVL Mask               */\r
+#define VADC_G_ASCTRL_XTMODE_Pos              13                                                      /*!< VADC_G ASCTRL: XTMODE Position          */\r
+#define VADC_G_ASCTRL_XTMODE_Msk              (0x03UL << VADC_G_ASCTRL_XTMODE_Pos)                    /*!< VADC_G ASCTRL: XTMODE Mask              */\r
+#define VADC_G_ASCTRL_XTWC_Pos                15                                                      /*!< VADC_G ASCTRL: XTWC Position            */\r
+#define VADC_G_ASCTRL_XTWC_Msk                (0x01UL << VADC_G_ASCTRL_XTWC_Pos)                      /*!< VADC_G ASCTRL: XTWC Mask                */\r
+#define VADC_G_ASCTRL_GTSEL_Pos               16                                                      /*!< VADC_G ASCTRL: GTSEL Position           */\r
+#define VADC_G_ASCTRL_GTSEL_Msk               (0x0fUL << VADC_G_ASCTRL_GTSEL_Pos)                     /*!< VADC_G ASCTRL: GTSEL Mask               */\r
+#define VADC_G_ASCTRL_GTLVL_Pos               20                                                      /*!< VADC_G ASCTRL: GTLVL Position           */\r
+#define VADC_G_ASCTRL_GTLVL_Msk               (0x01UL << VADC_G_ASCTRL_GTLVL_Pos)                     /*!< VADC_G ASCTRL: GTLVL Mask               */\r
+#define VADC_G_ASCTRL_GTWC_Pos                23                                                      /*!< VADC_G ASCTRL: GTWC Position            */\r
+#define VADC_G_ASCTRL_GTWC_Msk                (0x01UL << VADC_G_ASCTRL_GTWC_Pos)                      /*!< VADC_G ASCTRL: GTWC Mask                */\r
+#define VADC_G_ASCTRL_TMEN_Pos                28                                                      /*!< VADC_G ASCTRL: TMEN Position            */\r
+#define VADC_G_ASCTRL_TMEN_Msk                (0x01UL << VADC_G_ASCTRL_TMEN_Pos)                      /*!< VADC_G ASCTRL: TMEN Mask                */\r
+#define VADC_G_ASCTRL_TMWC_Pos                31                                                      /*!< VADC_G ASCTRL: TMWC Position            */\r
+#define VADC_G_ASCTRL_TMWC_Msk                (0x01UL << VADC_G_ASCTRL_TMWC_Pos)                      /*!< VADC_G ASCTRL: TMWC Mask                */\r
+\r
+/* ---------------------------------  VADC_G_ASMR  -------------------------------- */\r
+#define VADC_G_ASMR_ENGT_Pos                  0                                                       /*!< VADC_G ASMR: ENGT Position              */\r
+#define VADC_G_ASMR_ENGT_Msk                  (0x03UL << VADC_G_ASMR_ENGT_Pos)                        /*!< VADC_G ASMR: ENGT Mask                  */\r
+#define VADC_G_ASMR_ENTR_Pos                  2                                                       /*!< VADC_G ASMR: ENTR Position              */\r
+#define VADC_G_ASMR_ENTR_Msk                  (0x01UL << VADC_G_ASMR_ENTR_Pos)                        /*!< VADC_G ASMR: ENTR Mask                  */\r
+#define VADC_G_ASMR_ENSI_Pos                  3                                                       /*!< VADC_G ASMR: ENSI Position              */\r
+#define VADC_G_ASMR_ENSI_Msk                  (0x01UL << VADC_G_ASMR_ENSI_Pos)                        /*!< VADC_G ASMR: ENSI Mask                  */\r
+#define VADC_G_ASMR_SCAN_Pos                  4                                                       /*!< VADC_G ASMR: SCAN Position              */\r
+#define VADC_G_ASMR_SCAN_Msk                  (0x01UL << VADC_G_ASMR_SCAN_Pos)                        /*!< VADC_G ASMR: SCAN Mask                  */\r
+#define VADC_G_ASMR_LDM_Pos                   5                                                       /*!< VADC_G ASMR: LDM Position               */\r
+#define VADC_G_ASMR_LDM_Msk                   (0x01UL << VADC_G_ASMR_LDM_Pos)                         /*!< VADC_G ASMR: LDM Mask                   */\r
+#define VADC_G_ASMR_REQGT_Pos                 7                                                       /*!< VADC_G ASMR: REQGT Position             */\r
+#define VADC_G_ASMR_REQGT_Msk                 (0x01UL << VADC_G_ASMR_REQGT_Pos)                       /*!< VADC_G ASMR: REQGT Mask                 */\r
+#define VADC_G_ASMR_CLRPND_Pos                8                                                       /*!< VADC_G ASMR: CLRPND Position            */\r
+#define VADC_G_ASMR_CLRPND_Msk                (0x01UL << VADC_G_ASMR_CLRPND_Pos)                      /*!< VADC_G ASMR: CLRPND Mask                */\r
+#define VADC_G_ASMR_LDEV_Pos                  9                                                       /*!< VADC_G ASMR: LDEV Position              */\r
+#define VADC_G_ASMR_LDEV_Msk                  (0x01UL << VADC_G_ASMR_LDEV_Pos)                        /*!< VADC_G ASMR: LDEV Mask                  */\r
+#define VADC_G_ASMR_RPTDIS_Pos                16                                                      /*!< VADC_G ASMR: RPTDIS Position            */\r
+#define VADC_G_ASMR_RPTDIS_Msk                (0x01UL << VADC_G_ASMR_RPTDIS_Pos)                      /*!< VADC_G ASMR: RPTDIS Mask                */\r
+\r
+/* --------------------------------  VADC_G_ASSEL  -------------------------------- */\r
+#define VADC_G_ASSEL_CHSEL0_Pos               0                                                       /*!< VADC_G ASSEL: CHSEL0 Position           */\r
+#define VADC_G_ASSEL_CHSEL0_Msk               (0x01UL << VADC_G_ASSEL_CHSEL0_Pos)                     /*!< VADC_G ASSEL: CHSEL0 Mask               */\r
+#define VADC_G_ASSEL_CHSEL1_Pos               1                                                       /*!< VADC_G ASSEL: CHSEL1 Position           */\r
+#define VADC_G_ASSEL_CHSEL1_Msk               (0x01UL << VADC_G_ASSEL_CHSEL1_Pos)                     /*!< VADC_G ASSEL: CHSEL1 Mask               */\r
+#define VADC_G_ASSEL_CHSEL2_Pos               2                                                       /*!< VADC_G ASSEL: CHSEL2 Position           */\r
+#define VADC_G_ASSEL_CHSEL2_Msk               (0x01UL << VADC_G_ASSEL_CHSEL2_Pos)                     /*!< VADC_G ASSEL: CHSEL2 Mask               */\r
+#define VADC_G_ASSEL_CHSEL3_Pos               3                                                       /*!< VADC_G ASSEL: CHSEL3 Position           */\r
+#define VADC_G_ASSEL_CHSEL3_Msk               (0x01UL << VADC_G_ASSEL_CHSEL3_Pos)                     /*!< VADC_G ASSEL: CHSEL3 Mask               */\r
+#define VADC_G_ASSEL_CHSEL4_Pos               4                                                       /*!< VADC_G ASSEL: CHSEL4 Position           */\r
+#define VADC_G_ASSEL_CHSEL4_Msk               (0x01UL << VADC_G_ASSEL_CHSEL4_Pos)                     /*!< VADC_G ASSEL: CHSEL4 Mask               */\r
+#define VADC_G_ASSEL_CHSEL5_Pos               5                                                       /*!< VADC_G ASSEL: CHSEL5 Position           */\r
+#define VADC_G_ASSEL_CHSEL5_Msk               (0x01UL << VADC_G_ASSEL_CHSEL5_Pos)                     /*!< VADC_G ASSEL: CHSEL5 Mask               */\r
+#define VADC_G_ASSEL_CHSEL6_Pos               6                                                       /*!< VADC_G ASSEL: CHSEL6 Position           */\r
+#define VADC_G_ASSEL_CHSEL6_Msk               (0x01UL << VADC_G_ASSEL_CHSEL6_Pos)                     /*!< VADC_G ASSEL: CHSEL6 Mask               */\r
+#define VADC_G_ASSEL_CHSEL7_Pos               7                                                       /*!< VADC_G ASSEL: CHSEL7 Position           */\r
+#define VADC_G_ASSEL_CHSEL7_Msk               (0x01UL << VADC_G_ASSEL_CHSEL7_Pos)                     /*!< VADC_G ASSEL: CHSEL7 Mask               */\r
+\r
+/* --------------------------------  VADC_G_ASPND  -------------------------------- */\r
+#define VADC_G_ASPND_CHPND0_Pos               0                                                       /*!< VADC_G ASPND: CHPND0 Position           */\r
+#define VADC_G_ASPND_CHPND0_Msk               (0x01UL << VADC_G_ASPND_CHPND0_Pos)                     /*!< VADC_G ASPND: CHPND0 Mask               */\r
+#define VADC_G_ASPND_CHPND1_Pos               1                                                       /*!< VADC_G ASPND: CHPND1 Position           */\r
+#define VADC_G_ASPND_CHPND1_Msk               (0x01UL << VADC_G_ASPND_CHPND1_Pos)                     /*!< VADC_G ASPND: CHPND1 Mask               */\r
+#define VADC_G_ASPND_CHPND2_Pos               2                                                       /*!< VADC_G ASPND: CHPND2 Position           */\r
+#define VADC_G_ASPND_CHPND2_Msk               (0x01UL << VADC_G_ASPND_CHPND2_Pos)                     /*!< VADC_G ASPND: CHPND2 Mask               */\r
+#define VADC_G_ASPND_CHPND3_Pos               3                                                       /*!< VADC_G ASPND: CHPND3 Position           */\r
+#define VADC_G_ASPND_CHPND3_Msk               (0x01UL << VADC_G_ASPND_CHPND3_Pos)                     /*!< VADC_G ASPND: CHPND3 Mask               */\r
+#define VADC_G_ASPND_CHPND4_Pos               4                                                       /*!< VADC_G ASPND: CHPND4 Position           */\r
+#define VADC_G_ASPND_CHPND4_Msk               (0x01UL << VADC_G_ASPND_CHPND4_Pos)                     /*!< VADC_G ASPND: CHPND4 Mask               */\r
+#define VADC_G_ASPND_CHPND5_Pos               5                                                       /*!< VADC_G ASPND: CHPND5 Position           */\r
+#define VADC_G_ASPND_CHPND5_Msk               (0x01UL << VADC_G_ASPND_CHPND5_Pos)                     /*!< VADC_G ASPND: CHPND5 Mask               */\r
+#define VADC_G_ASPND_CHPND6_Pos               6                                                       /*!< VADC_G ASPND: CHPND6 Position           */\r
+#define VADC_G_ASPND_CHPND6_Msk               (0x01UL << VADC_G_ASPND_CHPND6_Pos)                     /*!< VADC_G ASPND: CHPND6 Mask               */\r
+#define VADC_G_ASPND_CHPND7_Pos               7                                                       /*!< VADC_G ASPND: CHPND7 Position           */\r
+#define VADC_G_ASPND_CHPND7_Msk               (0x01UL << VADC_G_ASPND_CHPND7_Pos)                     /*!< VADC_G ASPND: CHPND7 Mask               */\r
+\r
+/* --------------------------------  VADC_G_CEFLAG  ------------------------------- */\r
+#define VADC_G_CEFLAG_CEV0_Pos                0                                                       /*!< VADC_G CEFLAG: CEV0 Position            */\r
+#define VADC_G_CEFLAG_CEV0_Msk                (0x01UL << VADC_G_CEFLAG_CEV0_Pos)                      /*!< VADC_G CEFLAG: CEV0 Mask                */\r
+#define VADC_G_CEFLAG_CEV1_Pos                1                                                       /*!< VADC_G CEFLAG: CEV1 Position            */\r
+#define VADC_G_CEFLAG_CEV1_Msk                (0x01UL << VADC_G_CEFLAG_CEV1_Pos)                      /*!< VADC_G CEFLAG: CEV1 Mask                */\r
+#define VADC_G_CEFLAG_CEV2_Pos                2                                                       /*!< VADC_G CEFLAG: CEV2 Position            */\r
+#define VADC_G_CEFLAG_CEV2_Msk                (0x01UL << VADC_G_CEFLAG_CEV2_Pos)                      /*!< VADC_G CEFLAG: CEV2 Mask                */\r
+#define VADC_G_CEFLAG_CEV3_Pos                3                                                       /*!< VADC_G CEFLAG: CEV3 Position            */\r
+#define VADC_G_CEFLAG_CEV3_Msk                (0x01UL << VADC_G_CEFLAG_CEV3_Pos)                      /*!< VADC_G CEFLAG: CEV3 Mask                */\r
+#define VADC_G_CEFLAG_CEV4_Pos                4                                                       /*!< VADC_G CEFLAG: CEV4 Position            */\r
+#define VADC_G_CEFLAG_CEV4_Msk                (0x01UL << VADC_G_CEFLAG_CEV4_Pos)                      /*!< VADC_G CEFLAG: CEV4 Mask                */\r
+#define VADC_G_CEFLAG_CEV5_Pos                5                                                       /*!< VADC_G CEFLAG: CEV5 Position            */\r
+#define VADC_G_CEFLAG_CEV5_Msk                (0x01UL << VADC_G_CEFLAG_CEV5_Pos)                      /*!< VADC_G CEFLAG: CEV5 Mask                */\r
+#define VADC_G_CEFLAG_CEV6_Pos                6                                                       /*!< VADC_G CEFLAG: CEV6 Position            */\r
+#define VADC_G_CEFLAG_CEV6_Msk                (0x01UL << VADC_G_CEFLAG_CEV6_Pos)                      /*!< VADC_G CEFLAG: CEV6 Mask                */\r
+#define VADC_G_CEFLAG_CEV7_Pos                7                                                       /*!< VADC_G CEFLAG: CEV7 Position            */\r
+#define VADC_G_CEFLAG_CEV7_Msk                (0x01UL << VADC_G_CEFLAG_CEV7_Pos)                      /*!< VADC_G CEFLAG: CEV7 Mask                */\r
+\r
+/* --------------------------------  VADC_G_REFLAG  ------------------------------- */\r
+#define VADC_G_REFLAG_REV0_Pos                0                                                       /*!< VADC_G REFLAG: REV0 Position            */\r
+#define VADC_G_REFLAG_REV0_Msk                (0x01UL << VADC_G_REFLAG_REV0_Pos)                      /*!< VADC_G REFLAG: REV0 Mask                */\r
+#define VADC_G_REFLAG_REV1_Pos                1                                                       /*!< VADC_G REFLAG: REV1 Position            */\r
+#define VADC_G_REFLAG_REV1_Msk                (0x01UL << VADC_G_REFLAG_REV1_Pos)                      /*!< VADC_G REFLAG: REV1 Mask                */\r
+#define VADC_G_REFLAG_REV2_Pos                2                                                       /*!< VADC_G REFLAG: REV2 Position            */\r
+#define VADC_G_REFLAG_REV2_Msk                (0x01UL << VADC_G_REFLAG_REV2_Pos)                      /*!< VADC_G REFLAG: REV2 Mask                */\r
+#define VADC_G_REFLAG_REV3_Pos                3                                                       /*!< VADC_G REFLAG: REV3 Position            */\r
+#define VADC_G_REFLAG_REV3_Msk                (0x01UL << VADC_G_REFLAG_REV3_Pos)                      /*!< VADC_G REFLAG: REV3 Mask                */\r
+#define VADC_G_REFLAG_REV4_Pos                4                                                       /*!< VADC_G REFLAG: REV4 Position            */\r
+#define VADC_G_REFLAG_REV4_Msk                (0x01UL << VADC_G_REFLAG_REV4_Pos)                      /*!< VADC_G REFLAG: REV4 Mask                */\r
+#define VADC_G_REFLAG_REV5_Pos                5                                                       /*!< VADC_G REFLAG: REV5 Position            */\r
+#define VADC_G_REFLAG_REV5_Msk                (0x01UL << VADC_G_REFLAG_REV5_Pos)                      /*!< VADC_G REFLAG: REV5 Mask                */\r
+#define VADC_G_REFLAG_REV6_Pos                6                                                       /*!< VADC_G REFLAG: REV6 Position            */\r
+#define VADC_G_REFLAG_REV6_Msk                (0x01UL << VADC_G_REFLAG_REV6_Pos)                      /*!< VADC_G REFLAG: REV6 Mask                */\r
+#define VADC_G_REFLAG_REV7_Pos                7                                                       /*!< VADC_G REFLAG: REV7 Position            */\r
+#define VADC_G_REFLAG_REV7_Msk                (0x01UL << VADC_G_REFLAG_REV7_Pos)                      /*!< VADC_G REFLAG: REV7 Mask                */\r
+#define VADC_G_REFLAG_REV8_Pos                8                                                       /*!< VADC_G REFLAG: REV8 Position            */\r
+#define VADC_G_REFLAG_REV8_Msk                (0x01UL << VADC_G_REFLAG_REV8_Pos)                      /*!< VADC_G REFLAG: REV8 Mask                */\r
+#define VADC_G_REFLAG_REV9_Pos                9                                                       /*!< VADC_G REFLAG: REV9 Position            */\r
+#define VADC_G_REFLAG_REV9_Msk                (0x01UL << VADC_G_REFLAG_REV9_Pos)                      /*!< VADC_G REFLAG: REV9 Mask                */\r
+#define VADC_G_REFLAG_REV10_Pos               10                                                      /*!< VADC_G REFLAG: REV10 Position           */\r
+#define VADC_G_REFLAG_REV10_Msk               (0x01UL << VADC_G_REFLAG_REV10_Pos)                     /*!< VADC_G REFLAG: REV10 Mask               */\r
+#define VADC_G_REFLAG_REV11_Pos               11                                                      /*!< VADC_G REFLAG: REV11 Position           */\r
+#define VADC_G_REFLAG_REV11_Msk               (0x01UL << VADC_G_REFLAG_REV11_Pos)                     /*!< VADC_G REFLAG: REV11 Mask               */\r
+#define VADC_G_REFLAG_REV12_Pos               12                                                      /*!< VADC_G REFLAG: REV12 Position           */\r
+#define VADC_G_REFLAG_REV12_Msk               (0x01UL << VADC_G_REFLAG_REV12_Pos)                     /*!< VADC_G REFLAG: REV12 Mask               */\r
+#define VADC_G_REFLAG_REV13_Pos               13                                                      /*!< VADC_G REFLAG: REV13 Position           */\r
+#define VADC_G_REFLAG_REV13_Msk               (0x01UL << VADC_G_REFLAG_REV13_Pos)                     /*!< VADC_G REFLAG: REV13 Mask               */\r
+#define VADC_G_REFLAG_REV14_Pos               14                                                      /*!< VADC_G REFLAG: REV14 Position           */\r
+#define VADC_G_REFLAG_REV14_Msk               (0x01UL << VADC_G_REFLAG_REV14_Pos)                     /*!< VADC_G REFLAG: REV14 Mask               */\r
+#define VADC_G_REFLAG_REV15_Pos               15                                                      /*!< VADC_G REFLAG: REV15 Position           */\r
+#define VADC_G_REFLAG_REV15_Msk               (0x01UL << VADC_G_REFLAG_REV15_Pos)                     /*!< VADC_G REFLAG: REV15 Mask               */\r
+\r
+/* --------------------------------  VADC_G_SEFLAG  ------------------------------- */\r
+#define VADC_G_SEFLAG_SEV0_Pos                0                                                       /*!< VADC_G SEFLAG: SEV0 Position            */\r
+#define VADC_G_SEFLAG_SEV0_Msk                (0x01UL << VADC_G_SEFLAG_SEV0_Pos)                      /*!< VADC_G SEFLAG: SEV0 Mask                */\r
+#define VADC_G_SEFLAG_SEV1_Pos                1                                                       /*!< VADC_G SEFLAG: SEV1 Position            */\r
+#define VADC_G_SEFLAG_SEV1_Msk                (0x01UL << VADC_G_SEFLAG_SEV1_Pos)                      /*!< VADC_G SEFLAG: SEV1 Mask                */\r
+\r
+/* --------------------------------  VADC_G_CEFCLR  ------------------------------- */\r
+#define VADC_G_CEFCLR_CEV0_Pos                0                                                       /*!< VADC_G CEFCLR: CEV0 Position            */\r
+#define VADC_G_CEFCLR_CEV0_Msk                (0x01UL << VADC_G_CEFCLR_CEV0_Pos)                      /*!< VADC_G CEFCLR: CEV0 Mask                */\r
+#define VADC_G_CEFCLR_CEV1_Pos                1                                                       /*!< VADC_G CEFCLR: CEV1 Position            */\r
+#define VADC_G_CEFCLR_CEV1_Msk                (0x01UL << VADC_G_CEFCLR_CEV1_Pos)                      /*!< VADC_G CEFCLR: CEV1 Mask                */\r
+#define VADC_G_CEFCLR_CEV2_Pos                2                                                       /*!< VADC_G CEFCLR: CEV2 Position            */\r
+#define VADC_G_CEFCLR_CEV2_Msk                (0x01UL << VADC_G_CEFCLR_CEV2_Pos)                      /*!< VADC_G CEFCLR: CEV2 Mask                */\r
+#define VADC_G_CEFCLR_CEV3_Pos                3                                                       /*!< VADC_G CEFCLR: CEV3 Position            */\r
+#define VADC_G_CEFCLR_CEV3_Msk                (0x01UL << VADC_G_CEFCLR_CEV3_Pos)                      /*!< VADC_G CEFCLR: CEV3 Mask                */\r
+#define VADC_G_CEFCLR_CEV4_Pos                4                                                       /*!< VADC_G CEFCLR: CEV4 Position            */\r
+#define VADC_G_CEFCLR_CEV4_Msk                (0x01UL << VADC_G_CEFCLR_CEV4_Pos)                      /*!< VADC_G CEFCLR: CEV4 Mask                */\r
+#define VADC_G_CEFCLR_CEV5_Pos                5                                                       /*!< VADC_G CEFCLR: CEV5 Position            */\r
+#define VADC_G_CEFCLR_CEV5_Msk                (0x01UL << VADC_G_CEFCLR_CEV5_Pos)                      /*!< VADC_G CEFCLR: CEV5 Mask                */\r
+#define VADC_G_CEFCLR_CEV6_Pos                6                                                       /*!< VADC_G CEFCLR: CEV6 Position            */\r
+#define VADC_G_CEFCLR_CEV6_Msk                (0x01UL << VADC_G_CEFCLR_CEV6_Pos)                      /*!< VADC_G CEFCLR: CEV6 Mask                */\r
+#define VADC_G_CEFCLR_CEV7_Pos                7                                                       /*!< VADC_G CEFCLR: CEV7 Position            */\r
+#define VADC_G_CEFCLR_CEV7_Msk                (0x01UL << VADC_G_CEFCLR_CEV7_Pos)                      /*!< VADC_G CEFCLR: CEV7 Mask                */\r
+\r
+/* --------------------------------  VADC_G_REFCLR  ------------------------------- */\r
+#define VADC_G_REFCLR_REV0_Pos                0                                                       /*!< VADC_G REFCLR: REV0 Position            */\r
+#define VADC_G_REFCLR_REV0_Msk                (0x01UL << VADC_G_REFCLR_REV0_Pos)                      /*!< VADC_G REFCLR: REV0 Mask                */\r
+#define VADC_G_REFCLR_REV1_Pos                1                                                       /*!< VADC_G REFCLR: REV1 Position            */\r
+#define VADC_G_REFCLR_REV1_Msk                (0x01UL << VADC_G_REFCLR_REV1_Pos)                      /*!< VADC_G REFCLR: REV1 Mask                */\r
+#define VADC_G_REFCLR_REV2_Pos                2                                                       /*!< VADC_G REFCLR: REV2 Position            */\r
+#define VADC_G_REFCLR_REV2_Msk                (0x01UL << VADC_G_REFCLR_REV2_Pos)                      /*!< VADC_G REFCLR: REV2 Mask                */\r
+#define VADC_G_REFCLR_REV3_Pos                3                                                       /*!< VADC_G REFCLR: REV3 Position            */\r
+#define VADC_G_REFCLR_REV3_Msk                (0x01UL << VADC_G_REFCLR_REV3_Pos)                      /*!< VADC_G REFCLR: REV3 Mask                */\r
+#define VADC_G_REFCLR_REV4_Pos                4                                                       /*!< VADC_G REFCLR: REV4 Position            */\r
+#define VADC_G_REFCLR_REV4_Msk                (0x01UL << VADC_G_REFCLR_REV4_Pos)                      /*!< VADC_G REFCLR: REV4 Mask                */\r
+#define VADC_G_REFCLR_REV5_Pos                5                                                       /*!< VADC_G REFCLR: REV5 Position            */\r
+#define VADC_G_REFCLR_REV5_Msk                (0x01UL << VADC_G_REFCLR_REV5_Pos)                      /*!< VADC_G REFCLR: REV5 Mask                */\r
+#define VADC_G_REFCLR_REV6_Pos                6                                                       /*!< VADC_G REFCLR: REV6 Position            */\r
+#define VADC_G_REFCLR_REV6_Msk                (0x01UL << VADC_G_REFCLR_REV6_Pos)                      /*!< VADC_G REFCLR: REV6 Mask                */\r
+#define VADC_G_REFCLR_REV7_Pos                7                                                       /*!< VADC_G REFCLR: REV7 Position            */\r
+#define VADC_G_REFCLR_REV7_Msk                (0x01UL << VADC_G_REFCLR_REV7_Pos)                      /*!< VADC_G REFCLR: REV7 Mask                */\r
+#define VADC_G_REFCLR_REV8_Pos                8                                                       /*!< VADC_G REFCLR: REV8 Position            */\r
+#define VADC_G_REFCLR_REV8_Msk                (0x01UL << VADC_G_REFCLR_REV8_Pos)                      /*!< VADC_G REFCLR: REV8 Mask                */\r
+#define VADC_G_REFCLR_REV9_Pos                9                                                       /*!< VADC_G REFCLR: REV9 Position            */\r
+#define VADC_G_REFCLR_REV9_Msk                (0x01UL << VADC_G_REFCLR_REV9_Pos)                      /*!< VADC_G REFCLR: REV9 Mask                */\r
+#define VADC_G_REFCLR_REV10_Pos               10                                                      /*!< VADC_G REFCLR: REV10 Position           */\r
+#define VADC_G_REFCLR_REV10_Msk               (0x01UL << VADC_G_REFCLR_REV10_Pos)                     /*!< VADC_G REFCLR: REV10 Mask               */\r
+#define VADC_G_REFCLR_REV11_Pos               11                                                      /*!< VADC_G REFCLR: REV11 Position           */\r
+#define VADC_G_REFCLR_REV11_Msk               (0x01UL << VADC_G_REFCLR_REV11_Pos)                     /*!< VADC_G REFCLR: REV11 Mask               */\r
+#define VADC_G_REFCLR_REV12_Pos               12                                                      /*!< VADC_G REFCLR: REV12 Position           */\r
+#define VADC_G_REFCLR_REV12_Msk               (0x01UL << VADC_G_REFCLR_REV12_Pos)                     /*!< VADC_G REFCLR: REV12 Mask               */\r
+#define VADC_G_REFCLR_REV13_Pos               13                                                      /*!< VADC_G REFCLR: REV13 Position           */\r
+#define VADC_G_REFCLR_REV13_Msk               (0x01UL << VADC_G_REFCLR_REV13_Pos)                     /*!< VADC_G REFCLR: REV13 Mask               */\r
+#define VADC_G_REFCLR_REV14_Pos               14                                                      /*!< VADC_G REFCLR: REV14 Position           */\r
+#define VADC_G_REFCLR_REV14_Msk               (0x01UL << VADC_G_REFCLR_REV14_Pos)                     /*!< VADC_G REFCLR: REV14 Mask               */\r
+#define VADC_G_REFCLR_REV15_Pos               15                                                      /*!< VADC_G REFCLR: REV15 Position           */\r
+#define VADC_G_REFCLR_REV15_Msk               (0x01UL << VADC_G_REFCLR_REV15_Pos)                     /*!< VADC_G REFCLR: REV15 Mask               */\r
+\r
+/* --------------------------------  VADC_G_SEFCLR  ------------------------------- */\r
+#define VADC_G_SEFCLR_SEV0_Pos                0                                                       /*!< VADC_G SEFCLR: SEV0 Position            */\r
+#define VADC_G_SEFCLR_SEV0_Msk                (0x01UL << VADC_G_SEFCLR_SEV0_Pos)                      /*!< VADC_G SEFCLR: SEV0 Mask                */\r
+#define VADC_G_SEFCLR_SEV1_Pos                1                                                       /*!< VADC_G SEFCLR: SEV1 Position            */\r
+#define VADC_G_SEFCLR_SEV1_Msk                (0x01UL << VADC_G_SEFCLR_SEV1_Pos)                      /*!< VADC_G SEFCLR: SEV1 Mask                */\r
+\r
+/* --------------------------------  VADC_G_CEVNP0  ------------------------------- */\r
+#define VADC_G_CEVNP0_CEV0NP_Pos              0                                                       /*!< VADC_G CEVNP0: CEV0NP Position          */\r
+#define VADC_G_CEVNP0_CEV0NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV0NP_Pos)                    /*!< VADC_G CEVNP0: CEV0NP Mask              */\r
+#define VADC_G_CEVNP0_CEV1NP_Pos              4                                                       /*!< VADC_G CEVNP0: CEV1NP Position          */\r
+#define VADC_G_CEVNP0_CEV1NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV1NP_Pos)                    /*!< VADC_G CEVNP0: CEV1NP Mask              */\r
+#define VADC_G_CEVNP0_CEV2NP_Pos              8                                                       /*!< VADC_G CEVNP0: CEV2NP Position          */\r
+#define VADC_G_CEVNP0_CEV2NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV2NP_Pos)                    /*!< VADC_G CEVNP0: CEV2NP Mask              */\r
+#define VADC_G_CEVNP0_CEV3NP_Pos              12                                                      /*!< VADC_G CEVNP0: CEV3NP Position          */\r
+#define VADC_G_CEVNP0_CEV3NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV3NP_Pos)                    /*!< VADC_G CEVNP0: CEV3NP Mask              */\r
+#define VADC_G_CEVNP0_CEV4NP_Pos              16                                                      /*!< VADC_G CEVNP0: CEV4NP Position          */\r
+#define VADC_G_CEVNP0_CEV4NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV4NP_Pos)                    /*!< VADC_G CEVNP0: CEV4NP Mask              */\r
+#define VADC_G_CEVNP0_CEV5NP_Pos              20                                                      /*!< VADC_G CEVNP0: CEV5NP Position          */\r
+#define VADC_G_CEVNP0_CEV5NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV5NP_Pos)                    /*!< VADC_G CEVNP0: CEV5NP Mask              */\r
+#define VADC_G_CEVNP0_CEV6NP_Pos              24                                                      /*!< VADC_G CEVNP0: CEV6NP Position          */\r
+#define VADC_G_CEVNP0_CEV6NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV6NP_Pos)                    /*!< VADC_G CEVNP0: CEV6NP Mask              */\r
+#define VADC_G_CEVNP0_CEV7NP_Pos              28                                                      /*!< VADC_G CEVNP0: CEV7NP Position          */\r
+#define VADC_G_CEVNP0_CEV7NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV7NP_Pos)                    /*!< VADC_G CEVNP0: CEV7NP Mask              */\r
+\r
+/* --------------------------------  VADC_G_REVNP0  ------------------------------- */\r
+#define VADC_G_REVNP0_REV0NP_Pos              0                                                       /*!< VADC_G REVNP0: REV0NP Position          */\r
+#define VADC_G_REVNP0_REV0NP_Msk              (0x0fUL << VADC_G_REVNP0_REV0NP_Pos)                    /*!< VADC_G REVNP0: REV0NP Mask              */\r
+#define VADC_G_REVNP0_REV1NP_Pos              4                                                       /*!< VADC_G REVNP0: REV1NP Position          */\r
+#define VADC_G_REVNP0_REV1NP_Msk              (0x0fUL << VADC_G_REVNP0_REV1NP_Pos)                    /*!< VADC_G REVNP0: REV1NP Mask              */\r
+#define VADC_G_REVNP0_REV2NP_Pos              8                                                       /*!< VADC_G REVNP0: REV2NP Position          */\r
+#define VADC_G_REVNP0_REV2NP_Msk              (0x0fUL << VADC_G_REVNP0_REV2NP_Pos)                    /*!< VADC_G REVNP0: REV2NP Mask              */\r
+#define VADC_G_REVNP0_REV3NP_Pos              12                                                      /*!< VADC_G REVNP0: REV3NP Position          */\r
+#define VADC_G_REVNP0_REV3NP_Msk              (0x0fUL << VADC_G_REVNP0_REV3NP_Pos)                    /*!< VADC_G REVNP0: REV3NP Mask              */\r
+#define VADC_G_REVNP0_REV4NP_Pos              16                                                      /*!< VADC_G REVNP0: REV4NP Position          */\r
+#define VADC_G_REVNP0_REV4NP_Msk              (0x0fUL << VADC_G_REVNP0_REV4NP_Pos)                    /*!< VADC_G REVNP0: REV4NP Mask              */\r
+#define VADC_G_REVNP0_REV5NP_Pos              20                                                      /*!< VADC_G REVNP0: REV5NP Position          */\r
+#define VADC_G_REVNP0_REV5NP_Msk              (0x0fUL << VADC_G_REVNP0_REV5NP_Pos)                    /*!< VADC_G REVNP0: REV5NP Mask              */\r
+#define VADC_G_REVNP0_REV6NP_Pos              24                                                      /*!< VADC_G REVNP0: REV6NP Position          */\r
+#define VADC_G_REVNP0_REV6NP_Msk              (0x0fUL << VADC_G_REVNP0_REV6NP_Pos)                    /*!< VADC_G REVNP0: REV6NP Mask              */\r
+#define VADC_G_REVNP0_REV7NP_Pos              28                                                      /*!< VADC_G REVNP0: REV7NP Position          */\r
+#define VADC_G_REVNP0_REV7NP_Msk              (0x0fUL << VADC_G_REVNP0_REV7NP_Pos)                    /*!< VADC_G REVNP0: REV7NP Mask              */\r
+\r
+/* --------------------------------  VADC_G_REVNP1  ------------------------------- */\r
+#define VADC_G_REVNP1_REV8NP_Pos              0                                                       /*!< VADC_G REVNP1: REV8NP Position          */\r
+#define VADC_G_REVNP1_REV8NP_Msk              (0x0fUL << VADC_G_REVNP1_REV8NP_Pos)                    /*!< VADC_G REVNP1: REV8NP Mask              */\r
+#define VADC_G_REVNP1_REV9NP_Pos              4                                                       /*!< VADC_G REVNP1: REV9NP Position          */\r
+#define VADC_G_REVNP1_REV9NP_Msk              (0x0fUL << VADC_G_REVNP1_REV9NP_Pos)                    /*!< VADC_G REVNP1: REV9NP Mask              */\r
+#define VADC_G_REVNP1_REV10NP_Pos             8                                                       /*!< VADC_G REVNP1: REV10NP Position         */\r
+#define VADC_G_REVNP1_REV10NP_Msk             (0x0fUL << VADC_G_REVNP1_REV10NP_Pos)                   /*!< VADC_G REVNP1: REV10NP Mask             */\r
+#define VADC_G_REVNP1_REV11NP_Pos             12                                                      /*!< VADC_G REVNP1: REV11NP Position         */\r
+#define VADC_G_REVNP1_REV11NP_Msk             (0x0fUL << VADC_G_REVNP1_REV11NP_Pos)                   /*!< VADC_G REVNP1: REV11NP Mask             */\r
+#define VADC_G_REVNP1_REV12NP_Pos             16                                                      /*!< VADC_G REVNP1: REV12NP Position         */\r
+#define VADC_G_REVNP1_REV12NP_Msk             (0x0fUL << VADC_G_REVNP1_REV12NP_Pos)                   /*!< VADC_G REVNP1: REV12NP Mask             */\r
+#define VADC_G_REVNP1_REV13NP_Pos             20                                                      /*!< VADC_G REVNP1: REV13NP Position         */\r
+#define VADC_G_REVNP1_REV13NP_Msk             (0x0fUL << VADC_G_REVNP1_REV13NP_Pos)                   /*!< VADC_G REVNP1: REV13NP Mask             */\r
+#define VADC_G_REVNP1_REV14NP_Pos             24                                                      /*!< VADC_G REVNP1: REV14NP Position         */\r
+#define VADC_G_REVNP1_REV14NP_Msk             (0x0fUL << VADC_G_REVNP1_REV14NP_Pos)                   /*!< VADC_G REVNP1: REV14NP Mask             */\r
+#define VADC_G_REVNP1_REV15NP_Pos             28                                                      /*!< VADC_G REVNP1: REV15NP Position         */\r
+#define VADC_G_REVNP1_REV15NP_Msk             (0x0fUL << VADC_G_REVNP1_REV15NP_Pos)                   /*!< VADC_G REVNP1: REV15NP Mask             */\r
+\r
+/* --------------------------------  VADC_G_SEVNP  -------------------------------- */\r
+#define VADC_G_SEVNP_SEV0NP_Pos               0                                                       /*!< VADC_G SEVNP: SEV0NP Position           */\r
+#define VADC_G_SEVNP_SEV0NP_Msk               (0x0fUL << VADC_G_SEVNP_SEV0NP_Pos)                     /*!< VADC_G SEVNP: SEV0NP Mask               */\r
+#define VADC_G_SEVNP_SEV1NP_Pos               4                                                       /*!< VADC_G SEVNP: SEV1NP Position           */\r
+#define VADC_G_SEVNP_SEV1NP_Msk               (0x0fUL << VADC_G_SEVNP_SEV1NP_Pos)                     /*!< VADC_G SEVNP: SEV1NP Mask               */\r
+\r
+/* --------------------------------  VADC_G_SRACT  -------------------------------- */\r
+#define VADC_G_SRACT_AGSR0_Pos                0                                                       /*!< VADC_G SRACT: AGSR0 Position            */\r
+#define VADC_G_SRACT_AGSR0_Msk                (0x01UL << VADC_G_SRACT_AGSR0_Pos)                      /*!< VADC_G SRACT: AGSR0 Mask                */\r
+#define VADC_G_SRACT_AGSR1_Pos                1                                                       /*!< VADC_G SRACT: AGSR1 Position            */\r
+#define VADC_G_SRACT_AGSR1_Msk                (0x01UL << VADC_G_SRACT_AGSR1_Pos)                      /*!< VADC_G SRACT: AGSR1 Mask                */\r
+#define VADC_G_SRACT_AGSR2_Pos                2                                                       /*!< VADC_G SRACT: AGSR2 Position            */\r
+#define VADC_G_SRACT_AGSR2_Msk                (0x01UL << VADC_G_SRACT_AGSR2_Pos)                      /*!< VADC_G SRACT: AGSR2 Mask                */\r
+#define VADC_G_SRACT_AGSR3_Pos                3                                                       /*!< VADC_G SRACT: AGSR3 Position            */\r
+#define VADC_G_SRACT_AGSR3_Msk                (0x01UL << VADC_G_SRACT_AGSR3_Pos)                      /*!< VADC_G SRACT: AGSR3 Mask                */\r
+#define VADC_G_SRACT_ASSR0_Pos                8                                                       /*!< VADC_G SRACT: ASSR0 Position            */\r
+#define VADC_G_SRACT_ASSR0_Msk                (0x01UL << VADC_G_SRACT_ASSR0_Pos)                      /*!< VADC_G SRACT: ASSR0 Mask                */\r
+#define VADC_G_SRACT_ASSR1_Pos                9                                                       /*!< VADC_G SRACT: ASSR1 Position            */\r
+#define VADC_G_SRACT_ASSR1_Msk                (0x01UL << VADC_G_SRACT_ASSR1_Pos)                      /*!< VADC_G SRACT: ASSR1 Mask                */\r
+#define VADC_G_SRACT_ASSR2_Pos                10                                                      /*!< VADC_G SRACT: ASSR2 Position            */\r
+#define VADC_G_SRACT_ASSR2_Msk                (0x01UL << VADC_G_SRACT_ASSR2_Pos)                      /*!< VADC_G SRACT: ASSR2 Mask                */\r
+#define VADC_G_SRACT_ASSR3_Pos                11                                                      /*!< VADC_G SRACT: ASSR3 Position            */\r
+#define VADC_G_SRACT_ASSR3_Msk                (0x01UL << VADC_G_SRACT_ASSR3_Pos)                      /*!< VADC_G SRACT: ASSR3 Mask                */\r
+\r
+/* -------------------------------  VADC_G_EMUXCTR  ------------------------------- */\r
+#define VADC_G_EMUXCTR_EMUXSET_Pos            0                                                       /*!< VADC_G EMUXCTR: EMUXSET Position        */\r
+#define VADC_G_EMUXCTR_EMUXSET_Msk            (0x07UL << VADC_G_EMUXCTR_EMUXSET_Pos)                  /*!< VADC_G EMUXCTR: EMUXSET Mask            */\r
+#define VADC_G_EMUXCTR_EMUXACT_Pos            8                                                       /*!< VADC_G EMUXCTR: EMUXACT Position        */\r
+#define VADC_G_EMUXCTR_EMUXACT_Msk            (0x07UL << VADC_G_EMUXCTR_EMUXACT_Pos)                  /*!< VADC_G EMUXCTR: EMUXACT Mask            */\r
+#define VADC_G_EMUXCTR_EMUXCH_Pos             16                                                      /*!< VADC_G EMUXCTR: EMUXCH Position         */\r
+#define VADC_G_EMUXCTR_EMUXCH_Msk             (0x000003ffUL << VADC_G_EMUXCTR_EMUXCH_Pos)             /*!< VADC_G EMUXCTR: EMUXCH Mask             */\r
+#define VADC_G_EMUXCTR_EMUXMODE_Pos           26                                                      /*!< VADC_G EMUXCTR: EMUXMODE Position       */\r
+#define VADC_G_EMUXCTR_EMUXMODE_Msk           (0x03UL << VADC_G_EMUXCTR_EMUXMODE_Pos)                 /*!< VADC_G EMUXCTR: EMUXMODE Mask           */\r
+#define VADC_G_EMUXCTR_EMXCOD_Pos             28                                                      /*!< VADC_G EMUXCTR: EMXCOD Position         */\r
+#define VADC_G_EMUXCTR_EMXCOD_Msk             (0x01UL << VADC_G_EMUXCTR_EMXCOD_Pos)                   /*!< VADC_G EMUXCTR: EMXCOD Mask             */\r
+#define VADC_G_EMUXCTR_EMXST_Pos              29                                                      /*!< VADC_G EMUXCTR: EMXST Position          */\r
+#define VADC_G_EMUXCTR_EMXST_Msk              (0x01UL << VADC_G_EMUXCTR_EMXST_Pos)                    /*!< VADC_G EMUXCTR: EMXST Mask              */\r
+#define VADC_G_EMUXCTR_EMXCSS_Pos             30                                                      /*!< VADC_G EMUXCTR: EMXCSS Position         */\r
+#define VADC_G_EMUXCTR_EMXCSS_Msk             (0x01UL << VADC_G_EMUXCTR_EMXCSS_Pos)                   /*!< VADC_G EMUXCTR: EMXCSS Mask             */\r
+#define VADC_G_EMUXCTR_EMXWC_Pos              31                                                      /*!< VADC_G EMUXCTR: EMXWC Position          */\r
+#define VADC_G_EMUXCTR_EMXWC_Msk              (0x01UL << VADC_G_EMUXCTR_EMXWC_Pos)                    /*!< VADC_G EMUXCTR: EMXWC Mask              */\r
+\r
+/* ---------------------------------  VADC_G_VFR  --------------------------------- */\r
+#define VADC_G_VFR_VF0_Pos                    0                                                       /*!< VADC_G VFR: VF0 Position                */\r
+#define VADC_G_VFR_VF0_Msk                    (0x01UL << VADC_G_VFR_VF0_Pos)                          /*!< VADC_G VFR: VF0 Mask                    */\r
+#define VADC_G_VFR_VF1_Pos                    1                                                       /*!< VADC_G VFR: VF1 Position                */\r
+#define VADC_G_VFR_VF1_Msk                    (0x01UL << VADC_G_VFR_VF1_Pos)                          /*!< VADC_G VFR: VF1 Mask                    */\r
+#define VADC_G_VFR_VF2_Pos                    2                                                       /*!< VADC_G VFR: VF2 Position                */\r
+#define VADC_G_VFR_VF2_Msk                    (0x01UL << VADC_G_VFR_VF2_Pos)                          /*!< VADC_G VFR: VF2 Mask                    */\r
+#define VADC_G_VFR_VF3_Pos                    3                                                       /*!< VADC_G VFR: VF3 Position                */\r
+#define VADC_G_VFR_VF3_Msk                    (0x01UL << VADC_G_VFR_VF3_Pos)                          /*!< VADC_G VFR: VF3 Mask                    */\r
+#define VADC_G_VFR_VF4_Pos                    4                                                       /*!< VADC_G VFR: VF4 Position                */\r
+#define VADC_G_VFR_VF4_Msk                    (0x01UL << VADC_G_VFR_VF4_Pos)                          /*!< VADC_G VFR: VF4 Mask                    */\r
+#define VADC_G_VFR_VF5_Pos                    5                                                       /*!< VADC_G VFR: VF5 Position                */\r
+#define VADC_G_VFR_VF5_Msk                    (0x01UL << VADC_G_VFR_VF5_Pos)                          /*!< VADC_G VFR: VF5 Mask                    */\r
+#define VADC_G_VFR_VF6_Pos                    6                                                       /*!< VADC_G VFR: VF6 Position                */\r
+#define VADC_G_VFR_VF6_Msk                    (0x01UL << VADC_G_VFR_VF6_Pos)                          /*!< VADC_G VFR: VF6 Mask                    */\r
+#define VADC_G_VFR_VF7_Pos                    7                                                       /*!< VADC_G VFR: VF7 Position                */\r
+#define VADC_G_VFR_VF7_Msk                    (0x01UL << VADC_G_VFR_VF7_Pos)                          /*!< VADC_G VFR: VF7 Mask                    */\r
+#define VADC_G_VFR_VF8_Pos                    8                                                       /*!< VADC_G VFR: VF8 Position                */\r
+#define VADC_G_VFR_VF8_Msk                    (0x01UL << VADC_G_VFR_VF8_Pos)                          /*!< VADC_G VFR: VF8 Mask                    */\r
+#define VADC_G_VFR_VF9_Pos                    9                                                       /*!< VADC_G VFR: VF9 Position                */\r
+#define VADC_G_VFR_VF9_Msk                    (0x01UL << VADC_G_VFR_VF9_Pos)                          /*!< VADC_G VFR: VF9 Mask                    */\r
+#define VADC_G_VFR_VF10_Pos                   10                                                      /*!< VADC_G VFR: VF10 Position               */\r
+#define VADC_G_VFR_VF10_Msk                   (0x01UL << VADC_G_VFR_VF10_Pos)                         /*!< VADC_G VFR: VF10 Mask                   */\r
+#define VADC_G_VFR_VF11_Pos                   11                                                      /*!< VADC_G VFR: VF11 Position               */\r
+#define VADC_G_VFR_VF11_Msk                   (0x01UL << VADC_G_VFR_VF11_Pos)                         /*!< VADC_G VFR: VF11 Mask                   */\r
+#define VADC_G_VFR_VF12_Pos                   12                                                      /*!< VADC_G VFR: VF12 Position               */\r
+#define VADC_G_VFR_VF12_Msk                   (0x01UL << VADC_G_VFR_VF12_Pos)                         /*!< VADC_G VFR: VF12 Mask                   */\r
+#define VADC_G_VFR_VF13_Pos                   13                                                      /*!< VADC_G VFR: VF13 Position               */\r
+#define VADC_G_VFR_VF13_Msk                   (0x01UL << VADC_G_VFR_VF13_Pos)                         /*!< VADC_G VFR: VF13 Mask                   */\r
+#define VADC_G_VFR_VF14_Pos                   14                                                      /*!< VADC_G VFR: VF14 Position               */\r
+#define VADC_G_VFR_VF14_Msk                   (0x01UL << VADC_G_VFR_VF14_Pos)                         /*!< VADC_G VFR: VF14 Mask                   */\r
+#define VADC_G_VFR_VF15_Pos                   15                                                      /*!< VADC_G VFR: VF15 Position               */\r
+#define VADC_G_VFR_VF15_Msk                   (0x01UL << VADC_G_VFR_VF15_Pos)                         /*!< VADC_G VFR: VF15 Mask                   */\r
+\r
+/* --------------------------------  VADC_G_CHCTR  -------------------------------- */\r
+#define VADC_G_CHCTR_ICLSEL_Pos               0                                                       /*!< VADC_G CHCTR: ICLSEL Position           */\r
+#define VADC_G_CHCTR_ICLSEL_Msk               (0x03UL << VADC_G_CHCTR_ICLSEL_Pos)                     /*!< VADC_G CHCTR: ICLSEL Mask               */\r
+#define VADC_G_CHCTR_BNDSELL_Pos              4                                                       /*!< VADC_G CHCTR: BNDSELL Position          */\r
+#define VADC_G_CHCTR_BNDSELL_Msk              (0x03UL << VADC_G_CHCTR_BNDSELL_Pos)                    /*!< VADC_G CHCTR: BNDSELL Mask              */\r
+#define VADC_G_CHCTR_BNDSELU_Pos              6                                                       /*!< VADC_G CHCTR: BNDSELU Position          */\r
+#define VADC_G_CHCTR_BNDSELU_Msk              (0x03UL << VADC_G_CHCTR_BNDSELU_Pos)                    /*!< VADC_G CHCTR: BNDSELU Mask              */\r
+#define VADC_G_CHCTR_CHEVMODE_Pos             8                                                       /*!< VADC_G CHCTR: CHEVMODE Position         */\r
+#define VADC_G_CHCTR_CHEVMODE_Msk             (0x03UL << VADC_G_CHCTR_CHEVMODE_Pos)                   /*!< VADC_G CHCTR: CHEVMODE Mask             */\r
+#define VADC_G_CHCTR_SYNC_Pos                 10                                                      /*!< VADC_G CHCTR: SYNC Position             */\r
+#define VADC_G_CHCTR_SYNC_Msk                 (0x01UL << VADC_G_CHCTR_SYNC_Pos)                       /*!< VADC_G CHCTR: SYNC Mask                 */\r
+#define VADC_G_CHCTR_REFSEL_Pos               11                                                      /*!< VADC_G CHCTR: REFSEL Position           */\r
+#define VADC_G_CHCTR_REFSEL_Msk               (0x01UL << VADC_G_CHCTR_REFSEL_Pos)                     /*!< VADC_G CHCTR: REFSEL Mask               */\r
+#define VADC_G_CHCTR_RESREG_Pos               16                                                      /*!< VADC_G CHCTR: RESREG Position           */\r
+#define VADC_G_CHCTR_RESREG_Msk               (0x0fUL << VADC_G_CHCTR_RESREG_Pos)                     /*!< VADC_G CHCTR: RESREG Mask               */\r
+#define VADC_G_CHCTR_RESTBS_Pos               20                                                      /*!< VADC_G CHCTR: RESTBS Position           */\r
+#define VADC_G_CHCTR_RESTBS_Msk               (0x01UL << VADC_G_CHCTR_RESTBS_Pos)                     /*!< VADC_G CHCTR: RESTBS Mask               */\r
+#define VADC_G_CHCTR_RESPOS_Pos               21                                                      /*!< VADC_G CHCTR: RESPOS Position           */\r
+#define VADC_G_CHCTR_RESPOS_Msk               (0x01UL << VADC_G_CHCTR_RESPOS_Pos)                     /*!< VADC_G CHCTR: RESPOS Mask               */\r
+#define VADC_G_CHCTR_BWDCH_Pos                28                                                      /*!< VADC_G CHCTR: BWDCH Position            */\r
+#define VADC_G_CHCTR_BWDCH_Msk                (0x03UL << VADC_G_CHCTR_BWDCH_Pos)                      /*!< VADC_G CHCTR: BWDCH Mask                */\r
+#define VADC_G_CHCTR_BWDEN_Pos                30                                                      /*!< VADC_G CHCTR: BWDEN Position            */\r
+#define VADC_G_CHCTR_BWDEN_Msk                (0x01UL << VADC_G_CHCTR_BWDEN_Pos)                      /*!< VADC_G CHCTR: BWDEN Mask                */\r
+\r
+/* ---------------------------------  VADC_G_RCR  --------------------------------- */\r
+#define VADC_G_RCR_DRCTR_Pos                  16                                                      /*!< VADC_G RCR: DRCTR Position              */\r
+#define VADC_G_RCR_DRCTR_Msk                  (0x0fUL << VADC_G_RCR_DRCTR_Pos)                        /*!< VADC_G RCR: DRCTR Mask                  */\r
+#define VADC_G_RCR_DMM_Pos                    20                                                      /*!< VADC_G RCR: DMM Position                */\r
+#define VADC_G_RCR_DMM_Msk                    (0x03UL << VADC_G_RCR_DMM_Pos)                          /*!< VADC_G RCR: DMM Mask                    */\r
+#define VADC_G_RCR_WFR_Pos                    24                                                      /*!< VADC_G RCR: WFR Position                */\r
+#define VADC_G_RCR_WFR_Msk                    (0x01UL << VADC_G_RCR_WFR_Pos)                          /*!< VADC_G RCR: WFR Mask                    */\r
+#define VADC_G_RCR_FEN_Pos                    25                                                      /*!< VADC_G RCR: FEN Position                */\r
+#define VADC_G_RCR_FEN_Msk                    (0x03UL << VADC_G_RCR_FEN_Pos)                          /*!< VADC_G RCR: FEN Mask                    */\r
+#define VADC_G_RCR_SRGEN_Pos                  31                                                      /*!< VADC_G RCR: SRGEN Position              */\r
+#define VADC_G_RCR_SRGEN_Msk                  (0x01UL << VADC_G_RCR_SRGEN_Pos)                        /*!< VADC_G RCR: SRGEN Mask                  */\r
+\r
+/* ---------------------------------  VADC_G_RES  --------------------------------- */\r
+#define VADC_G_RES_RESULT_Pos                 0                                                       /*!< VADC_G RES: RESULT Position             */\r
+#define VADC_G_RES_RESULT_Msk                 (0x0000ffffUL << VADC_G_RES_RESULT_Pos)                 /*!< VADC_G RES: RESULT Mask                 */\r
+#define VADC_G_RES_DRC_Pos                    16                                                      /*!< VADC_G RES: DRC Position                */\r
+#define VADC_G_RES_DRC_Msk                    (0x0fUL << VADC_G_RES_DRC_Pos)                          /*!< VADC_G RES: DRC Mask                    */\r
+#define VADC_G_RES_CHNR_Pos                   20                                                      /*!< VADC_G RES: CHNR Position               */\r
+#define VADC_G_RES_CHNR_Msk                   (0x1fUL << VADC_G_RES_CHNR_Pos)                         /*!< VADC_G RES: CHNR Mask                   */\r
+#define VADC_G_RES_EMUX_Pos                   25                                                      /*!< VADC_G RES: EMUX Position               */\r
+#define VADC_G_RES_EMUX_Msk                   (0x07UL << VADC_G_RES_EMUX_Pos)                         /*!< VADC_G RES: EMUX Mask                   */\r
+#define VADC_G_RES_CRS_Pos                    28                                                      /*!< VADC_G RES: CRS Position                */\r
+#define VADC_G_RES_CRS_Msk                    (0x03UL << VADC_G_RES_CRS_Pos)                          /*!< VADC_G RES: CRS Mask                    */\r
+#define VADC_G_RES_FCR_Pos                    30                                                      /*!< VADC_G RES: FCR Position                */\r
+#define VADC_G_RES_FCR_Msk                    (0x01UL << VADC_G_RES_FCR_Pos)                          /*!< VADC_G RES: FCR Mask                    */\r
+#define VADC_G_RES_VF_Pos                     31                                                      /*!< VADC_G RES: VF Position                 */\r
+#define VADC_G_RES_VF_Msk                     (0x01UL << VADC_G_RES_VF_Pos)                           /*!< VADC_G RES: VF Mask                     */\r
+\r
+/* ---------------------------------  VADC_G_RESD  -------------------------------- */\r
+#define VADC_G_RESD_RESULT_Pos                0                                                       /*!< VADC_G RESD: RESULT Position            */\r
+#define VADC_G_RESD_RESULT_Msk                (0x0000ffffUL << VADC_G_RESD_RESULT_Pos)                /*!< VADC_G RESD: RESULT Mask                */\r
+#define VADC_G_RESD_DRC_Pos                   16                                                      /*!< VADC_G RESD: DRC Position               */\r
+#define VADC_G_RESD_DRC_Msk                   (0x0fUL << VADC_G_RESD_DRC_Pos)                         /*!< VADC_G RESD: DRC Mask                   */\r
+#define VADC_G_RESD_CHNR_Pos                  20                                                      /*!< VADC_G RESD: CHNR Position              */\r
+#define VADC_G_RESD_CHNR_Msk                  (0x1fUL << VADC_G_RESD_CHNR_Pos)                        /*!< VADC_G RESD: CHNR Mask                  */\r
+#define VADC_G_RESD_EMUX_Pos                  25                                                      /*!< VADC_G RESD: EMUX Position              */\r
+#define VADC_G_RESD_EMUX_Msk                  (0x07UL << VADC_G_RESD_EMUX_Pos)                        /*!< VADC_G RESD: EMUX Mask                  */\r
+#define VADC_G_RESD_CRS_Pos                   28                                                      /*!< VADC_G RESD: CRS Position               */\r
+#define VADC_G_RESD_CRS_Msk                   (0x03UL << VADC_G_RESD_CRS_Pos)                         /*!< VADC_G RESD: CRS Mask                   */\r
+#define VADC_G_RESD_FCR_Pos                   30                                                      /*!< VADC_G RESD: FCR Position               */\r
+#define VADC_G_RESD_FCR_Msk                   (0x01UL << VADC_G_RESD_FCR_Pos)                         /*!< VADC_G RESD: FCR Mask                   */\r
+#define VADC_G_RESD_VF_Pos                    31                                                      /*!< VADC_G RESD: VF Position                */\r
+#define VADC_G_RESD_VF_Msk                    (0x01UL << VADC_G_RESD_VF_Pos)                          /*!< VADC_G RESD: VF Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'DAC' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  DAC_ID  ----------------------------------- */\r
+#define DAC_ID_MODR_Pos                       0                                                       /*!< DAC ID: MODR Position                   */\r
+#define DAC_ID_MODR_Msk                       (0x000000ffUL << DAC_ID_MODR_Pos)                       /*!< DAC ID: MODR Mask                       */\r
+#define DAC_ID_MODT_Pos                       8                                                       /*!< DAC ID: MODT Position                   */\r
+#define DAC_ID_MODT_Msk                       (0x000000ffUL << DAC_ID_MODT_Pos)                       /*!< DAC ID: MODT Mask                       */\r
+#define DAC_ID_MODN_Pos                       16                                                      /*!< DAC ID: MODN Position                   */\r
+#define DAC_ID_MODN_Msk                       (0x0000ffffUL << DAC_ID_MODN_Pos)                       /*!< DAC ID: MODN Mask                       */\r
+\r
+/* --------------------------------  DAC_DAC0CFG0  -------------------------------- */\r
+#define DAC_DAC0CFG0_FREQ_Pos                 0                                                       /*!< DAC DAC0CFG0: FREQ Position             */\r
+#define DAC_DAC0CFG0_FREQ_Msk                 (0x000fffffUL << DAC_DAC0CFG0_FREQ_Pos)                 /*!< DAC DAC0CFG0: FREQ Mask                 */\r
+#define DAC_DAC0CFG0_MODE_Pos                 20                                                      /*!< DAC DAC0CFG0: MODE Position             */\r
+#define DAC_DAC0CFG0_MODE_Msk                 (0x07UL << DAC_DAC0CFG0_MODE_Pos)                       /*!< DAC DAC0CFG0: MODE Mask                 */\r
+#define DAC_DAC0CFG0_SIGN_Pos                 23                                                      /*!< DAC DAC0CFG0: SIGN Position             */\r
+#define DAC_DAC0CFG0_SIGN_Msk                 (0x01UL << DAC_DAC0CFG0_SIGN_Pos)                       /*!< DAC DAC0CFG0: SIGN Mask                 */\r
+#define DAC_DAC0CFG0_FIFOIND_Pos              24                                                      /*!< DAC DAC0CFG0: FIFOIND Position          */\r
+#define DAC_DAC0CFG0_FIFOIND_Msk              (0x03UL << DAC_DAC0CFG0_FIFOIND_Pos)                    /*!< DAC DAC0CFG0: FIFOIND Mask              */\r
+#define DAC_DAC0CFG0_FIFOEMP_Pos              26                                                      /*!< DAC DAC0CFG0: FIFOEMP Position          */\r
+#define DAC_DAC0CFG0_FIFOEMP_Msk              (0x01UL << DAC_DAC0CFG0_FIFOEMP_Pos)                    /*!< DAC DAC0CFG0: FIFOEMP Mask              */\r
+#define DAC_DAC0CFG0_FIFOFUL_Pos              27                                                      /*!< DAC DAC0CFG0: FIFOFUL Position          */\r
+#define DAC_DAC0CFG0_FIFOFUL_Msk              (0x01UL << DAC_DAC0CFG0_FIFOFUL_Pos)                    /*!< DAC DAC0CFG0: FIFOFUL Mask              */\r
+#define DAC_DAC0CFG0_NEGATE_Pos               28                                                      /*!< DAC DAC0CFG0: NEGATE Position           */\r
+#define DAC_DAC0CFG0_NEGATE_Msk               (0x01UL << DAC_DAC0CFG0_NEGATE_Pos)                     /*!< DAC DAC0CFG0: NEGATE Mask               */\r
+#define DAC_DAC0CFG0_SIGNEN_Pos               29                                                      /*!< DAC DAC0CFG0: SIGNEN Position           */\r
+#define DAC_DAC0CFG0_SIGNEN_Msk               (0x01UL << DAC_DAC0CFG0_SIGNEN_Pos)                     /*!< DAC DAC0CFG0: SIGNEN Mask               */\r
+#define DAC_DAC0CFG0_SREN_Pos                 30                                                      /*!< DAC DAC0CFG0: SREN Position             */\r
+#define DAC_DAC0CFG0_SREN_Msk                 (0x01UL << DAC_DAC0CFG0_SREN_Pos)                       /*!< DAC DAC0CFG0: SREN Mask                 */\r
+#define DAC_DAC0CFG0_RUN_Pos                  31                                                      /*!< DAC DAC0CFG0: RUN Position              */\r
+#define DAC_DAC0CFG0_RUN_Msk                  (0x01UL << DAC_DAC0CFG0_RUN_Pos)                        /*!< DAC DAC0CFG0: RUN Mask                  */\r
+\r
+/* --------------------------------  DAC_DAC0CFG1  -------------------------------- */\r
+#define DAC_DAC0CFG1_SCALE_Pos                0                                                       /*!< DAC DAC0CFG1: SCALE Position            */\r
+#define DAC_DAC0CFG1_SCALE_Msk                (0x07UL << DAC_DAC0CFG1_SCALE_Pos)                      /*!< DAC DAC0CFG1: SCALE Mask                */\r
+#define DAC_DAC0CFG1_MULDIV_Pos               3                                                       /*!< DAC DAC0CFG1: MULDIV Position           */\r
+#define DAC_DAC0CFG1_MULDIV_Msk               (0x01UL << DAC_DAC0CFG1_MULDIV_Pos)                     /*!< DAC DAC0CFG1: MULDIV Mask               */\r
+#define DAC_DAC0CFG1_OFFS_Pos                 4                                                       /*!< DAC DAC0CFG1: OFFS Position             */\r
+#define DAC_DAC0CFG1_OFFS_Msk                 (0x000000ffUL << DAC_DAC0CFG1_OFFS_Pos)                 /*!< DAC DAC0CFG1: OFFS Mask                 */\r
+#define DAC_DAC0CFG1_TRIGSEL_Pos              12                                                      /*!< DAC DAC0CFG1: TRIGSEL Position          */\r
+#define DAC_DAC0CFG1_TRIGSEL_Msk              (0x07UL << DAC_DAC0CFG1_TRIGSEL_Pos)                    /*!< DAC DAC0CFG1: TRIGSEL Mask              */\r
+#define DAC_DAC0CFG1_DATMOD_Pos               15                                                      /*!< DAC DAC0CFG1: DATMOD Position           */\r
+#define DAC_DAC0CFG1_DATMOD_Msk               (0x01UL << DAC_DAC0CFG1_DATMOD_Pos)                     /*!< DAC DAC0CFG1: DATMOD Mask               */\r
+#define DAC_DAC0CFG1_SWTRIG_Pos               16                                                      /*!< DAC DAC0CFG1: SWTRIG Position           */\r
+#define DAC_DAC0CFG1_SWTRIG_Msk               (0x01UL << DAC_DAC0CFG1_SWTRIG_Pos)                     /*!< DAC DAC0CFG1: SWTRIG Mask               */\r
+#define DAC_DAC0CFG1_TRIGMOD_Pos              17                                                      /*!< DAC DAC0CFG1: TRIGMOD Position          */\r
+#define DAC_DAC0CFG1_TRIGMOD_Msk              (0x03UL << DAC_DAC0CFG1_TRIGMOD_Pos)                    /*!< DAC DAC0CFG1: TRIGMOD Mask              */\r
+#define DAC_DAC0CFG1_ANACFG_Pos               19                                                      /*!< DAC DAC0CFG1: ANACFG Position           */\r
+#define DAC_DAC0CFG1_ANACFG_Msk               (0x1fUL << DAC_DAC0CFG1_ANACFG_Pos)                     /*!< DAC DAC0CFG1: ANACFG Mask               */\r
+#define DAC_DAC0CFG1_ANAEN_Pos                24                                                      /*!< DAC DAC0CFG1: ANAEN Position            */\r
+#define DAC_DAC0CFG1_ANAEN_Msk                (0x01UL << DAC_DAC0CFG1_ANAEN_Pos)                      /*!< DAC DAC0CFG1: ANAEN Mask                */\r
+#define DAC_DAC0CFG1_REFCFGL_Pos              28                                                      /*!< DAC DAC0CFG1: REFCFGL Position          */\r
+#define DAC_DAC0CFG1_REFCFGL_Msk              (0x0fUL << DAC_DAC0CFG1_REFCFGL_Pos)                    /*!< DAC DAC0CFG1: REFCFGL Mask              */\r
+\r
+/* --------------------------------  DAC_DAC1CFG0  -------------------------------- */\r
+#define DAC_DAC1CFG0_FREQ_Pos                 0                                                       /*!< DAC DAC1CFG0: FREQ Position             */\r
+#define DAC_DAC1CFG0_FREQ_Msk                 (0x000fffffUL << DAC_DAC1CFG0_FREQ_Pos)                 /*!< DAC DAC1CFG0: FREQ Mask                 */\r
+#define DAC_DAC1CFG0_MODE_Pos                 20                                                      /*!< DAC DAC1CFG0: MODE Position             */\r
+#define DAC_DAC1CFG0_MODE_Msk                 (0x07UL << DAC_DAC1CFG0_MODE_Pos)                       /*!< DAC DAC1CFG0: MODE Mask                 */\r
+#define DAC_DAC1CFG0_SIGN_Pos                 23                                                      /*!< DAC DAC1CFG0: SIGN Position             */\r
+#define DAC_DAC1CFG0_SIGN_Msk                 (0x01UL << DAC_DAC1CFG0_SIGN_Pos)                       /*!< DAC DAC1CFG0: SIGN Mask                 */\r
+#define DAC_DAC1CFG0_FIFOIND_Pos              24                                                      /*!< DAC DAC1CFG0: FIFOIND Position          */\r
+#define DAC_DAC1CFG0_FIFOIND_Msk              (0x03UL << DAC_DAC1CFG0_FIFOIND_Pos)                    /*!< DAC DAC1CFG0: FIFOIND Mask              */\r
+#define DAC_DAC1CFG0_FIFOEMP_Pos              26                                                      /*!< DAC DAC1CFG0: FIFOEMP Position          */\r
+#define DAC_DAC1CFG0_FIFOEMP_Msk              (0x01UL << DAC_DAC1CFG0_FIFOEMP_Pos)                    /*!< DAC DAC1CFG0: FIFOEMP Mask              */\r
+#define DAC_DAC1CFG0_FIFOFUL_Pos              27                                                      /*!< DAC DAC1CFG0: FIFOFUL Position          */\r
+#define DAC_DAC1CFG0_FIFOFUL_Msk              (0x01UL << DAC_DAC1CFG0_FIFOFUL_Pos)                    /*!< DAC DAC1CFG0: FIFOFUL Mask              */\r
+#define DAC_DAC1CFG0_NEGATE_Pos               28                                                      /*!< DAC DAC1CFG0: NEGATE Position           */\r
+#define DAC_DAC1CFG0_NEGATE_Msk               (0x01UL << DAC_DAC1CFG0_NEGATE_Pos)                     /*!< DAC DAC1CFG0: NEGATE Mask               */\r
+#define DAC_DAC1CFG0_SIGNEN_Pos               29                                                      /*!< DAC DAC1CFG0: SIGNEN Position           */\r
+#define DAC_DAC1CFG0_SIGNEN_Msk               (0x01UL << DAC_DAC1CFG0_SIGNEN_Pos)                     /*!< DAC DAC1CFG0: SIGNEN Mask               */\r
+#define DAC_DAC1CFG0_SREN_Pos                 30                                                      /*!< DAC DAC1CFG0: SREN Position             */\r
+#define DAC_DAC1CFG0_SREN_Msk                 (0x01UL << DAC_DAC1CFG0_SREN_Pos)                       /*!< DAC DAC1CFG0: SREN Mask                 */\r
+#define DAC_DAC1CFG0_RUN_Pos                  31                                                      /*!< DAC DAC1CFG0: RUN Position              */\r
+#define DAC_DAC1CFG0_RUN_Msk                  (0x01UL << DAC_DAC1CFG0_RUN_Pos)                        /*!< DAC DAC1CFG0: RUN Mask                  */\r
+\r
+/* --------------------------------  DAC_DAC1CFG1  -------------------------------- */\r
+#define DAC_DAC1CFG1_SCALE_Pos                0                                                       /*!< DAC DAC1CFG1: SCALE Position            */\r
+#define DAC_DAC1CFG1_SCALE_Msk                (0x07UL << DAC_DAC1CFG1_SCALE_Pos)                      /*!< DAC DAC1CFG1: SCALE Mask                */\r
+#define DAC_DAC1CFG1_MULDIV_Pos               3                                                       /*!< DAC DAC1CFG1: MULDIV Position           */\r
+#define DAC_DAC1CFG1_MULDIV_Msk               (0x01UL << DAC_DAC1CFG1_MULDIV_Pos)                     /*!< DAC DAC1CFG1: MULDIV Mask               */\r
+#define DAC_DAC1CFG1_OFFS_Pos                 4                                                       /*!< DAC DAC1CFG1: OFFS Position             */\r
+#define DAC_DAC1CFG1_OFFS_Msk                 (0x000000ffUL << DAC_DAC1CFG1_OFFS_Pos)                 /*!< DAC DAC1CFG1: OFFS Mask                 */\r
+#define DAC_DAC1CFG1_TRIGSEL_Pos              12                                                      /*!< DAC DAC1CFG1: TRIGSEL Position          */\r
+#define DAC_DAC1CFG1_TRIGSEL_Msk              (0x07UL << DAC_DAC1CFG1_TRIGSEL_Pos)                    /*!< DAC DAC1CFG1: TRIGSEL Mask              */\r
+#define DAC_DAC1CFG1_SWTRIG_Pos               16                                                      /*!< DAC DAC1CFG1: SWTRIG Position           */\r
+#define DAC_DAC1CFG1_SWTRIG_Msk               (0x01UL << DAC_DAC1CFG1_SWTRIG_Pos)                     /*!< DAC DAC1CFG1: SWTRIG Mask               */\r
+#define DAC_DAC1CFG1_TRIGMOD_Pos              17                                                      /*!< DAC DAC1CFG1: TRIGMOD Position          */\r
+#define DAC_DAC1CFG1_TRIGMOD_Msk              (0x03UL << DAC_DAC1CFG1_TRIGMOD_Pos)                    /*!< DAC DAC1CFG1: TRIGMOD Mask              */\r
+#define DAC_DAC1CFG1_ANACFG_Pos               19                                                      /*!< DAC DAC1CFG1: ANACFG Position           */\r
+#define DAC_DAC1CFG1_ANACFG_Msk               (0x1fUL << DAC_DAC1CFG1_ANACFG_Pos)                     /*!< DAC DAC1CFG1: ANACFG Mask               */\r
+#define DAC_DAC1CFG1_ANAEN_Pos                24                                                      /*!< DAC DAC1CFG1: ANAEN Position            */\r
+#define DAC_DAC1CFG1_ANAEN_Msk                (0x01UL << DAC_DAC1CFG1_ANAEN_Pos)                      /*!< DAC DAC1CFG1: ANAEN Mask                */\r
+#define DAC_DAC1CFG1_REFCFGH_Pos              28                                                      /*!< DAC DAC1CFG1: REFCFGH Position          */\r
+#define DAC_DAC1CFG1_REFCFGH_Msk              (0x0fUL << DAC_DAC1CFG1_REFCFGH_Pos)                    /*!< DAC DAC1CFG1: REFCFGH Mask              */\r
+\r
+/* --------------------------------  DAC_DAC0DATA  -------------------------------- */\r
+#define DAC_DAC0DATA_DATA0_Pos                0                                                       /*!< DAC DAC0DATA: DATA0 Position            */\r
+#define DAC_DAC0DATA_DATA0_Msk                (0x00000fffUL << DAC_DAC0DATA_DATA0_Pos)                /*!< DAC DAC0DATA: DATA0 Mask                */\r
+\r
+/* --------------------------------  DAC_DAC1DATA  -------------------------------- */\r
+#define DAC_DAC1DATA_DATA1_Pos                0                                                       /*!< DAC DAC1DATA: DATA1 Position            */\r
+#define DAC_DAC1DATA_DATA1_Msk                (0x00000fffUL << DAC_DAC1DATA_DATA1_Pos)                /*!< DAC DAC1DATA: DATA1 Mask                */\r
+\r
+/* --------------------------------  DAC_DAC01DATA  ------------------------------- */\r
+#define DAC_DAC01DATA_DATA0_Pos               0                                                       /*!< DAC DAC01DATA: DATA0 Position           */\r
+#define DAC_DAC01DATA_DATA0_Msk               (0x00000fffUL << DAC_DAC01DATA_DATA0_Pos)               /*!< DAC DAC01DATA: DATA0 Mask               */\r
+#define DAC_DAC01DATA_DATA1_Pos               16                                                      /*!< DAC DAC01DATA: DATA1 Position           */\r
+#define DAC_DAC01DATA_DATA1_Msk               (0x00000fffUL << DAC_DAC01DATA_DATA1_Pos)               /*!< DAC DAC01DATA: DATA1 Mask               */\r
+\r
+/* --------------------------------  DAC_DAC0PATL  -------------------------------- */\r
+#define DAC_DAC0PATL_PAT0_Pos                 0                                                       /*!< DAC DAC0PATL: PAT0 Position             */\r
+#define DAC_DAC0PATL_PAT0_Msk                 (0x1fUL << DAC_DAC0PATL_PAT0_Pos)                       /*!< DAC DAC0PATL: PAT0 Mask                 */\r
+#define DAC_DAC0PATL_PAT1_Pos                 5                                                       /*!< DAC DAC0PATL: PAT1 Position             */\r
+#define DAC_DAC0PATL_PAT1_Msk                 (0x1fUL << DAC_DAC0PATL_PAT1_Pos)                       /*!< DAC DAC0PATL: PAT1 Mask                 */\r
+#define DAC_DAC0PATL_PAT2_Pos                 10                                                      /*!< DAC DAC0PATL: PAT2 Position             */\r
+#define DAC_DAC0PATL_PAT2_Msk                 (0x1fUL << DAC_DAC0PATL_PAT2_Pos)                       /*!< DAC DAC0PATL: PAT2 Mask                 */\r
+#define DAC_DAC0PATL_PAT3_Pos                 15                                                      /*!< DAC DAC0PATL: PAT3 Position             */\r
+#define DAC_DAC0PATL_PAT3_Msk                 (0x1fUL << DAC_DAC0PATL_PAT3_Pos)                       /*!< DAC DAC0PATL: PAT3 Mask                 */\r
+#define DAC_DAC0PATL_PAT4_Pos                 20                                                      /*!< DAC DAC0PATL: PAT4 Position             */\r
+#define DAC_DAC0PATL_PAT4_Msk                 (0x1fUL << DAC_DAC0PATL_PAT4_Pos)                       /*!< DAC DAC0PATL: PAT4 Mask                 */\r
+#define DAC_DAC0PATL_PAT5_Pos                 25                                                      /*!< DAC DAC0PATL: PAT5 Position             */\r
+#define DAC_DAC0PATL_PAT5_Msk                 (0x1fUL << DAC_DAC0PATL_PAT5_Pos)                       /*!< DAC DAC0PATL: PAT5 Mask                 */\r
+\r
+/* --------------------------------  DAC_DAC0PATH  -------------------------------- */\r
+#define DAC_DAC0PATH_PAT6_Pos                 0                                                       /*!< DAC DAC0PATH: PAT6 Position             */\r
+#define DAC_DAC0PATH_PAT6_Msk                 (0x1fUL << DAC_DAC0PATH_PAT6_Pos)                       /*!< DAC DAC0PATH: PAT6 Mask                 */\r
+#define DAC_DAC0PATH_PAT7_Pos                 5                                                       /*!< DAC DAC0PATH: PAT7 Position             */\r
+#define DAC_DAC0PATH_PAT7_Msk                 (0x1fUL << DAC_DAC0PATH_PAT7_Pos)                       /*!< DAC DAC0PATH: PAT7 Mask                 */\r
+#define DAC_DAC0PATH_PAT8_Pos                 10                                                      /*!< DAC DAC0PATH: PAT8 Position             */\r
+#define DAC_DAC0PATH_PAT8_Msk                 (0x1fUL << DAC_DAC0PATH_PAT8_Pos)                       /*!< DAC DAC0PATH: PAT8 Mask                 */\r
+\r
+/* --------------------------------  DAC_DAC1PATL  -------------------------------- */\r
+#define DAC_DAC1PATL_PAT0_Pos                 0                                                       /*!< DAC DAC1PATL: PAT0 Position             */\r
+#define DAC_DAC1PATL_PAT0_Msk                 (0x1fUL << DAC_DAC1PATL_PAT0_Pos)                       /*!< DAC DAC1PATL: PAT0 Mask                 */\r
+#define DAC_DAC1PATL_PAT1_Pos                 5                                                       /*!< DAC DAC1PATL: PAT1 Position             */\r
+#define DAC_DAC1PATL_PAT1_Msk                 (0x1fUL << DAC_DAC1PATL_PAT1_Pos)                       /*!< DAC DAC1PATL: PAT1 Mask                 */\r
+#define DAC_DAC1PATL_PAT2_Pos                 10                                                      /*!< DAC DAC1PATL: PAT2 Position             */\r
+#define DAC_DAC1PATL_PAT2_Msk                 (0x1fUL << DAC_DAC1PATL_PAT2_Pos)                       /*!< DAC DAC1PATL: PAT2 Mask                 */\r
+#define DAC_DAC1PATL_PAT3_Pos                 15                                                      /*!< DAC DAC1PATL: PAT3 Position             */\r
+#define DAC_DAC1PATL_PAT3_Msk                 (0x1fUL << DAC_DAC1PATL_PAT3_Pos)                       /*!< DAC DAC1PATL: PAT3 Mask                 */\r
+#define DAC_DAC1PATL_PAT4_Pos                 20                                                      /*!< DAC DAC1PATL: PAT4 Position             */\r
+#define DAC_DAC1PATL_PAT4_Msk                 (0x1fUL << DAC_DAC1PATL_PAT4_Pos)                       /*!< DAC DAC1PATL: PAT4 Mask                 */\r
+#define DAC_DAC1PATL_PAT5_Pos                 25                                                      /*!< DAC DAC1PATL: PAT5 Position             */\r
+#define DAC_DAC1PATL_PAT5_Msk                 (0x1fUL << DAC_DAC1PATL_PAT5_Pos)                       /*!< DAC DAC1PATL: PAT5 Mask                 */\r
+\r
+/* --------------------------------  DAC_DAC1PATH  -------------------------------- */\r
+#define DAC_DAC1PATH_PAT6_Pos                 0                                                       /*!< DAC DAC1PATH: PAT6 Position             */\r
+#define DAC_DAC1PATH_PAT6_Msk                 (0x1fUL << DAC_DAC1PATH_PAT6_Pos)                       /*!< DAC DAC1PATH: PAT6 Mask                 */\r
+#define DAC_DAC1PATH_PAT7_Pos                 5                                                       /*!< DAC DAC1PATH: PAT7 Position             */\r
+#define DAC_DAC1PATH_PAT7_Msk                 (0x1fUL << DAC_DAC1PATH_PAT7_Pos)                       /*!< DAC DAC1PATH: PAT7 Mask                 */\r
+#define DAC_DAC1PATH_PAT8_Pos                 10                                                      /*!< DAC DAC1PATH: PAT8 Position             */\r
+#define DAC_DAC1PATH_PAT8_Msk                 (0x1fUL << DAC_DAC1PATH_PAT8_Pos)                       /*!< DAC DAC1PATH: PAT8 Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'CCU4' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  CCU4_GCTRL  --------------------------------- */\r
+#define CCU4_GCTRL_PRBC_Pos                   0                                                       /*!< CCU4 GCTRL: PRBC Position               */\r
+#define CCU4_GCTRL_PRBC_Msk                   (0x07UL << CCU4_GCTRL_PRBC_Pos)                         /*!< CCU4 GCTRL: PRBC Mask                   */\r
+#define CCU4_GCTRL_PCIS_Pos                   4                                                       /*!< CCU4 GCTRL: PCIS Position               */\r
+#define CCU4_GCTRL_PCIS_Msk                   (0x03UL << CCU4_GCTRL_PCIS_Pos)                         /*!< CCU4 GCTRL: PCIS Mask                   */\r
+#define CCU4_GCTRL_SUSCFG_Pos                 8                                                       /*!< CCU4 GCTRL: SUSCFG Position             */\r
+#define CCU4_GCTRL_SUSCFG_Msk                 (0x03UL << CCU4_GCTRL_SUSCFG_Pos)                       /*!< CCU4 GCTRL: SUSCFG Mask                 */\r
+#define CCU4_GCTRL_MSE0_Pos                   10                                                      /*!< CCU4 GCTRL: MSE0 Position               */\r
+#define CCU4_GCTRL_MSE0_Msk                   (0x01UL << CCU4_GCTRL_MSE0_Pos)                         /*!< CCU4 GCTRL: MSE0 Mask                   */\r
+#define CCU4_GCTRL_MSE1_Pos                   11                                                      /*!< CCU4 GCTRL: MSE1 Position               */\r
+#define CCU4_GCTRL_MSE1_Msk                   (0x01UL << CCU4_GCTRL_MSE1_Pos)                         /*!< CCU4 GCTRL: MSE1 Mask                   */\r
+#define CCU4_GCTRL_MSE2_Pos                   12                                                      /*!< CCU4 GCTRL: MSE2 Position               */\r
+#define CCU4_GCTRL_MSE2_Msk                   (0x01UL << CCU4_GCTRL_MSE2_Pos)                         /*!< CCU4 GCTRL: MSE2 Mask                   */\r
+#define CCU4_GCTRL_MSE3_Pos                   13                                                      /*!< CCU4 GCTRL: MSE3 Position               */\r
+#define CCU4_GCTRL_MSE3_Msk                   (0x01UL << CCU4_GCTRL_MSE3_Pos)                         /*!< CCU4 GCTRL: MSE3 Mask                   */\r
+#define CCU4_GCTRL_MSDE_Pos                   14                                                      /*!< CCU4 GCTRL: MSDE Position               */\r
+#define CCU4_GCTRL_MSDE_Msk                   (0x03UL << CCU4_GCTRL_MSDE_Pos)                         /*!< CCU4 GCTRL: MSDE Mask                   */\r
+\r
+/* ---------------------------------  CCU4_GSTAT  --------------------------------- */\r
+#define CCU4_GSTAT_S0I_Pos                    0                                                       /*!< CCU4 GSTAT: S0I Position                */\r
+#define CCU4_GSTAT_S0I_Msk                    (0x01UL << CCU4_GSTAT_S0I_Pos)                          /*!< CCU4 GSTAT: S0I Mask                    */\r
+#define CCU4_GSTAT_S1I_Pos                    1                                                       /*!< CCU4 GSTAT: S1I Position                */\r
+#define CCU4_GSTAT_S1I_Msk                    (0x01UL << CCU4_GSTAT_S1I_Pos)                          /*!< CCU4 GSTAT: S1I Mask                    */\r
+#define CCU4_GSTAT_S2I_Pos                    2                                                       /*!< CCU4 GSTAT: S2I Position                */\r
+#define CCU4_GSTAT_S2I_Msk                    (0x01UL << CCU4_GSTAT_S2I_Pos)                          /*!< CCU4 GSTAT: S2I Mask                    */\r
+#define CCU4_GSTAT_S3I_Pos                    3                                                       /*!< CCU4 GSTAT: S3I Position                */\r
+#define CCU4_GSTAT_S3I_Msk                    (0x01UL << CCU4_GSTAT_S3I_Pos)                          /*!< CCU4 GSTAT: S3I Mask                    */\r
+#define CCU4_GSTAT_PRB_Pos                    8                                                       /*!< CCU4 GSTAT: PRB Position                */\r
+#define CCU4_GSTAT_PRB_Msk                    (0x01UL << CCU4_GSTAT_PRB_Pos)                          /*!< CCU4 GSTAT: PRB Mask                    */\r
+\r
+/* ---------------------------------  CCU4_GIDLS  --------------------------------- */\r
+#define CCU4_GIDLS_SS0I_Pos                   0                                                       /*!< CCU4 GIDLS: SS0I Position               */\r
+#define CCU4_GIDLS_SS0I_Msk                   (0x01UL << CCU4_GIDLS_SS0I_Pos)                         /*!< CCU4 GIDLS: SS0I Mask                   */\r
+#define CCU4_GIDLS_SS1I_Pos                   1                                                       /*!< CCU4 GIDLS: SS1I Position               */\r
+#define CCU4_GIDLS_SS1I_Msk                   (0x01UL << CCU4_GIDLS_SS1I_Pos)                         /*!< CCU4 GIDLS: SS1I Mask                   */\r
+#define CCU4_GIDLS_SS2I_Pos                   2                                                       /*!< CCU4 GIDLS: SS2I Position               */\r
+#define CCU4_GIDLS_SS2I_Msk                   (0x01UL << CCU4_GIDLS_SS2I_Pos)                         /*!< CCU4 GIDLS: SS2I Mask                   */\r
+#define CCU4_GIDLS_SS3I_Pos                   3                                                       /*!< CCU4 GIDLS: SS3I Position               */\r
+#define CCU4_GIDLS_SS3I_Msk                   (0x01UL << CCU4_GIDLS_SS3I_Pos)                         /*!< CCU4 GIDLS: SS3I Mask                   */\r
+#define CCU4_GIDLS_CPRB_Pos                   8                                                       /*!< CCU4 GIDLS: CPRB Position               */\r
+#define CCU4_GIDLS_CPRB_Msk                   (0x01UL << CCU4_GIDLS_CPRB_Pos)                         /*!< CCU4 GIDLS: CPRB Mask                   */\r
+#define CCU4_GIDLS_PSIC_Pos                   9                                                       /*!< CCU4 GIDLS: PSIC Position               */\r
+#define CCU4_GIDLS_PSIC_Msk                   (0x01UL << CCU4_GIDLS_PSIC_Pos)                         /*!< CCU4 GIDLS: PSIC Mask                   */\r
+\r
+/* ---------------------------------  CCU4_GIDLC  --------------------------------- */\r
+#define CCU4_GIDLC_CS0I_Pos                   0                                                       /*!< CCU4 GIDLC: CS0I Position               */\r
+#define CCU4_GIDLC_CS0I_Msk                   (0x01UL << CCU4_GIDLC_CS0I_Pos)                         /*!< CCU4 GIDLC: CS0I Mask                   */\r
+#define CCU4_GIDLC_CS1I_Pos                   1                                                       /*!< CCU4 GIDLC: CS1I Position               */\r
+#define CCU4_GIDLC_CS1I_Msk                   (0x01UL << CCU4_GIDLC_CS1I_Pos)                         /*!< CCU4 GIDLC: CS1I Mask                   */\r
+#define CCU4_GIDLC_CS2I_Pos                   2                                                       /*!< CCU4 GIDLC: CS2I Position               */\r
+#define CCU4_GIDLC_CS2I_Msk                   (0x01UL << CCU4_GIDLC_CS2I_Pos)                         /*!< CCU4 GIDLC: CS2I Mask                   */\r
+#define CCU4_GIDLC_CS3I_Pos                   3                                                       /*!< CCU4 GIDLC: CS3I Position               */\r
+#define CCU4_GIDLC_CS3I_Msk                   (0x01UL << CCU4_GIDLC_CS3I_Pos)                         /*!< CCU4 GIDLC: CS3I Mask                   */\r
+#define CCU4_GIDLC_SPRB_Pos                   8                                                       /*!< CCU4 GIDLC: SPRB Position               */\r
+#define CCU4_GIDLC_SPRB_Msk                   (0x01UL << CCU4_GIDLC_SPRB_Pos)                         /*!< CCU4 GIDLC: SPRB Mask                   */\r
+\r
+/* ----------------------------------  CCU4_GCSS  --------------------------------- */\r
+#define CCU4_GCSS_S0SE_Pos                    0                                                       /*!< CCU4 GCSS: S0SE Position                */\r
+#define CCU4_GCSS_S0SE_Msk                    (0x01UL << CCU4_GCSS_S0SE_Pos)                          /*!< CCU4 GCSS: S0SE Mask                    */\r
+#define CCU4_GCSS_S0DSE_Pos                   1                                                       /*!< CCU4 GCSS: S0DSE Position               */\r
+#define CCU4_GCSS_S0DSE_Msk                   (0x01UL << CCU4_GCSS_S0DSE_Pos)                         /*!< CCU4 GCSS: S0DSE Mask                   */\r
+#define CCU4_GCSS_S0PSE_Pos                   2                                                       /*!< CCU4 GCSS: S0PSE Position               */\r
+#define CCU4_GCSS_S0PSE_Msk                   (0x01UL << CCU4_GCSS_S0PSE_Pos)                         /*!< CCU4 GCSS: S0PSE Mask                   */\r
+#define CCU4_GCSS_S1SE_Pos                    4                                                       /*!< CCU4 GCSS: S1SE Position                */\r
+#define CCU4_GCSS_S1SE_Msk                    (0x01UL << CCU4_GCSS_S1SE_Pos)                          /*!< CCU4 GCSS: S1SE Mask                    */\r
+#define CCU4_GCSS_S1DSE_Pos                   5                                                       /*!< CCU4 GCSS: S1DSE Position               */\r
+#define CCU4_GCSS_S1DSE_Msk                   (0x01UL << CCU4_GCSS_S1DSE_Pos)                         /*!< CCU4 GCSS: S1DSE Mask                   */\r
+#define CCU4_GCSS_S1PSE_Pos                   6                                                       /*!< CCU4 GCSS: S1PSE Position               */\r
+#define CCU4_GCSS_S1PSE_Msk                   (0x01UL << CCU4_GCSS_S1PSE_Pos)                         /*!< CCU4 GCSS: S1PSE Mask                   */\r
+#define CCU4_GCSS_S2SE_Pos                    8                                                       /*!< CCU4 GCSS: S2SE Position                */\r
+#define CCU4_GCSS_S2SE_Msk                    (0x01UL << CCU4_GCSS_S2SE_Pos)                          /*!< CCU4 GCSS: S2SE Mask                    */\r
+#define CCU4_GCSS_S2DSE_Pos                   9                                                       /*!< CCU4 GCSS: S2DSE Position               */\r
+#define CCU4_GCSS_S2DSE_Msk                   (0x01UL << CCU4_GCSS_S2DSE_Pos)                         /*!< CCU4 GCSS: S2DSE Mask                   */\r
+#define CCU4_GCSS_S2PSE_Pos                   10                                                      /*!< CCU4 GCSS: S2PSE Position               */\r
+#define CCU4_GCSS_S2PSE_Msk                   (0x01UL << CCU4_GCSS_S2PSE_Pos)                         /*!< CCU4 GCSS: S2PSE Mask                   */\r
+#define CCU4_GCSS_S3SE_Pos                    12                                                      /*!< CCU4 GCSS: S3SE Position                */\r
+#define CCU4_GCSS_S3SE_Msk                    (0x01UL << CCU4_GCSS_S3SE_Pos)                          /*!< CCU4 GCSS: S3SE Mask                    */\r
+#define CCU4_GCSS_S3DSE_Pos                   13                                                      /*!< CCU4 GCSS: S3DSE Position               */\r
+#define CCU4_GCSS_S3DSE_Msk                   (0x01UL << CCU4_GCSS_S3DSE_Pos)                         /*!< CCU4 GCSS: S3DSE Mask                   */\r
+#define CCU4_GCSS_S3PSE_Pos                   14                                                      /*!< CCU4 GCSS: S3PSE Position               */\r
+#define CCU4_GCSS_S3PSE_Msk                   (0x01UL << CCU4_GCSS_S3PSE_Pos)                         /*!< CCU4 GCSS: S3PSE Mask                   */\r
+#define CCU4_GCSS_S0STS_Pos                   16                                                      /*!< CCU4 GCSS: S0STS Position               */\r
+#define CCU4_GCSS_S0STS_Msk                   (0x01UL << CCU4_GCSS_S0STS_Pos)                         /*!< CCU4 GCSS: S0STS Mask                   */\r
+#define CCU4_GCSS_S1STS_Pos                   17                                                      /*!< CCU4 GCSS: S1STS Position               */\r
+#define CCU4_GCSS_S1STS_Msk                   (0x01UL << CCU4_GCSS_S1STS_Pos)                         /*!< CCU4 GCSS: S1STS Mask                   */\r
+#define CCU4_GCSS_S2STS_Pos                   18                                                      /*!< CCU4 GCSS: S2STS Position               */\r
+#define CCU4_GCSS_S2STS_Msk                   (0x01UL << CCU4_GCSS_S2STS_Pos)                         /*!< CCU4 GCSS: S2STS Mask                   */\r
+#define CCU4_GCSS_S3STS_Pos                   19                                                      /*!< CCU4 GCSS: S3STS Position               */\r
+#define CCU4_GCSS_S3STS_Msk                   (0x01UL << CCU4_GCSS_S3STS_Pos)                         /*!< CCU4 GCSS: S3STS Mask                   */\r
+\r
+/* ----------------------------------  CCU4_GCSC  --------------------------------- */\r
+#define CCU4_GCSC_S0SC_Pos                    0                                                       /*!< CCU4 GCSC: S0SC Position                */\r
+#define CCU4_GCSC_S0SC_Msk                    (0x01UL << CCU4_GCSC_S0SC_Pos)                          /*!< CCU4 GCSC: S0SC Mask                    */\r
+#define CCU4_GCSC_S0DSC_Pos                   1                                                       /*!< CCU4 GCSC: S0DSC Position               */\r
+#define CCU4_GCSC_S0DSC_Msk                   (0x01UL << CCU4_GCSC_S0DSC_Pos)                         /*!< CCU4 GCSC: S0DSC Mask                   */\r
+#define CCU4_GCSC_S0PSC_Pos                   2                                                       /*!< CCU4 GCSC: S0PSC Position               */\r
+#define CCU4_GCSC_S0PSC_Msk                   (0x01UL << CCU4_GCSC_S0PSC_Pos)                         /*!< CCU4 GCSC: S0PSC Mask                   */\r
+#define CCU4_GCSC_S1SC_Pos                    4                                                       /*!< CCU4 GCSC: S1SC Position                */\r
+#define CCU4_GCSC_S1SC_Msk                    (0x01UL << CCU4_GCSC_S1SC_Pos)                          /*!< CCU4 GCSC: S1SC Mask                    */\r
+#define CCU4_GCSC_S1DSC_Pos                   5                                                       /*!< CCU4 GCSC: S1DSC Position               */\r
+#define CCU4_GCSC_S1DSC_Msk                   (0x01UL << CCU4_GCSC_S1DSC_Pos)                         /*!< CCU4 GCSC: S1DSC Mask                   */\r
+#define CCU4_GCSC_S1PSC_Pos                   6                                                       /*!< CCU4 GCSC: S1PSC Position               */\r
+#define CCU4_GCSC_S1PSC_Msk                   (0x01UL << CCU4_GCSC_S1PSC_Pos)                         /*!< CCU4 GCSC: S1PSC Mask                   */\r
+#define CCU4_GCSC_S2SC_Pos                    8                                                       /*!< CCU4 GCSC: S2SC Position                */\r
+#define CCU4_GCSC_S2SC_Msk                    (0x01UL << CCU4_GCSC_S2SC_Pos)                          /*!< CCU4 GCSC: S2SC Mask                    */\r
+#define CCU4_GCSC_S2DSC_Pos                   9                                                       /*!< CCU4 GCSC: S2DSC Position               */\r
+#define CCU4_GCSC_S2DSC_Msk                   (0x01UL << CCU4_GCSC_S2DSC_Pos)                         /*!< CCU4 GCSC: S2DSC Mask                   */\r
+#define CCU4_GCSC_S2PSC_Pos                   10                                                      /*!< CCU4 GCSC: S2PSC Position               */\r
+#define CCU4_GCSC_S2PSC_Msk                   (0x01UL << CCU4_GCSC_S2PSC_Pos)                         /*!< CCU4 GCSC: S2PSC Mask                   */\r
+#define CCU4_GCSC_S3SC_Pos                    12                                                      /*!< CCU4 GCSC: S3SC Position                */\r
+#define CCU4_GCSC_S3SC_Msk                    (0x01UL << CCU4_GCSC_S3SC_Pos)                          /*!< CCU4 GCSC: S3SC Mask                    */\r
+#define CCU4_GCSC_S3DSC_Pos                   13                                                      /*!< CCU4 GCSC: S3DSC Position               */\r
+#define CCU4_GCSC_S3DSC_Msk                   (0x01UL << CCU4_GCSC_S3DSC_Pos)                         /*!< CCU4 GCSC: S3DSC Mask                   */\r
+#define CCU4_GCSC_S3PSC_Pos                   14                                                      /*!< CCU4 GCSC: S3PSC Position               */\r
+#define CCU4_GCSC_S3PSC_Msk                   (0x01UL << CCU4_GCSC_S3PSC_Pos)                         /*!< CCU4 GCSC: S3PSC Mask                   */\r
+#define CCU4_GCSC_S0STC_Pos                   16                                                      /*!< CCU4 GCSC: S0STC Position               */\r
+#define CCU4_GCSC_S0STC_Msk                   (0x01UL << CCU4_GCSC_S0STC_Pos)                         /*!< CCU4 GCSC: S0STC Mask                   */\r
+#define CCU4_GCSC_S1STC_Pos                   17                                                      /*!< CCU4 GCSC: S1STC Position               */\r
+#define CCU4_GCSC_S1STC_Msk                   (0x01UL << CCU4_GCSC_S1STC_Pos)                         /*!< CCU4 GCSC: S1STC Mask                   */\r
+#define CCU4_GCSC_S2STC_Pos                   18                                                      /*!< CCU4 GCSC: S2STC Position               */\r
+#define CCU4_GCSC_S2STC_Msk                   (0x01UL << CCU4_GCSC_S2STC_Pos)                         /*!< CCU4 GCSC: S2STC Mask                   */\r
+#define CCU4_GCSC_S3STC_Pos                   19                                                      /*!< CCU4 GCSC: S3STC Position               */\r
+#define CCU4_GCSC_S3STC_Msk                   (0x01UL << CCU4_GCSC_S3STC_Pos)                         /*!< CCU4 GCSC: S3STC Mask                   */\r
+\r
+/* ----------------------------------  CCU4_GCST  --------------------------------- */\r
+#define CCU4_GCST_S0SS_Pos                    0                                                       /*!< CCU4 GCST: S0SS Position                */\r
+#define CCU4_GCST_S0SS_Msk                    (0x01UL << CCU4_GCST_S0SS_Pos)                          /*!< CCU4 GCST: S0SS Mask                    */\r
+#define CCU4_GCST_S0DSS_Pos                   1                                                       /*!< CCU4 GCST: S0DSS Position               */\r
+#define CCU4_GCST_S0DSS_Msk                   (0x01UL << CCU4_GCST_S0DSS_Pos)                         /*!< CCU4 GCST: S0DSS Mask                   */\r
+#define CCU4_GCST_S0PSS_Pos                   2                                                       /*!< CCU4 GCST: S0PSS Position               */\r
+#define CCU4_GCST_S0PSS_Msk                   (0x01UL << CCU4_GCST_S0PSS_Pos)                         /*!< CCU4 GCST: S0PSS Mask                   */\r
+#define CCU4_GCST_S1SS_Pos                    4                                                       /*!< CCU4 GCST: S1SS Position                */\r
+#define CCU4_GCST_S1SS_Msk                    (0x01UL << CCU4_GCST_S1SS_Pos)                          /*!< CCU4 GCST: S1SS Mask                    */\r
+#define CCU4_GCST_S1DSS_Pos                   5                                                       /*!< CCU4 GCST: S1DSS Position               */\r
+#define CCU4_GCST_S1DSS_Msk                   (0x01UL << CCU4_GCST_S1DSS_Pos)                         /*!< CCU4 GCST: S1DSS Mask                   */\r
+#define CCU4_GCST_S1PSS_Pos                   6                                                       /*!< CCU4 GCST: S1PSS Position               */\r
+#define CCU4_GCST_S1PSS_Msk                   (0x01UL << CCU4_GCST_S1PSS_Pos)                         /*!< CCU4 GCST: S1PSS Mask                   */\r
+#define CCU4_GCST_S2SS_Pos                    8                                                       /*!< CCU4 GCST: S2SS Position                */\r
+#define CCU4_GCST_S2SS_Msk                    (0x01UL << CCU4_GCST_S2SS_Pos)                          /*!< CCU4 GCST: S2SS Mask                    */\r
+#define CCU4_GCST_S2DSS_Pos                   9                                                       /*!< CCU4 GCST: S2DSS Position               */\r
+#define CCU4_GCST_S2DSS_Msk                   (0x01UL << CCU4_GCST_S2DSS_Pos)                         /*!< CCU4 GCST: S2DSS Mask                   */\r
+#define CCU4_GCST_S2PSS_Pos                   10                                                      /*!< CCU4 GCST: S2PSS Position               */\r
+#define CCU4_GCST_S2PSS_Msk                   (0x01UL << CCU4_GCST_S2PSS_Pos)                         /*!< CCU4 GCST: S2PSS Mask                   */\r
+#define CCU4_GCST_S3SS_Pos                    12                                                      /*!< CCU4 GCST: S3SS Position                */\r
+#define CCU4_GCST_S3SS_Msk                    (0x01UL << CCU4_GCST_S3SS_Pos)                          /*!< CCU4 GCST: S3SS Mask                    */\r
+#define CCU4_GCST_S3DSS_Pos                   13                                                      /*!< CCU4 GCST: S3DSS Position               */\r
+#define CCU4_GCST_S3DSS_Msk                   (0x01UL << CCU4_GCST_S3DSS_Pos)                         /*!< CCU4 GCST: S3DSS Mask                   */\r
+#define CCU4_GCST_S3PSS_Pos                   14                                                      /*!< CCU4 GCST: S3PSS Position               */\r
+#define CCU4_GCST_S3PSS_Msk                   (0x01UL << CCU4_GCST_S3PSS_Pos)                         /*!< CCU4 GCST: S3PSS Mask                   */\r
+#define CCU4_GCST_CC40ST_Pos                  16                                                      /*!< CCU4 GCST: CC40ST Position              */\r
+#define CCU4_GCST_CC40ST_Msk                  (0x01UL << CCU4_GCST_CC40ST_Pos)                        /*!< CCU4 GCST: CC40ST Mask                  */\r
+#define CCU4_GCST_CC41ST_Pos                  17                                                      /*!< CCU4 GCST: CC41ST Position              */\r
+#define CCU4_GCST_CC41ST_Msk                  (0x01UL << CCU4_GCST_CC41ST_Pos)                        /*!< CCU4 GCST: CC41ST Mask                  */\r
+#define CCU4_GCST_CC42ST_Pos                  18                                                      /*!< CCU4 GCST: CC42ST Position              */\r
+#define CCU4_GCST_CC42ST_Msk                  (0x01UL << CCU4_GCST_CC42ST_Pos)                        /*!< CCU4 GCST: CC42ST Mask                  */\r
+#define CCU4_GCST_CC43ST_Pos                  19                                                      /*!< CCU4 GCST: CC43ST Position              */\r
+#define CCU4_GCST_CC43ST_Msk                  (0x01UL << CCU4_GCST_CC43ST_Pos)                        /*!< CCU4 GCST: CC43ST Mask                  */\r
+\r
+/* ----------------------------------  CCU4_ECRD  --------------------------------- */\r
+#define CCU4_ECRD_CAPV_Pos                    0                                                       /*!< CCU4 ECRD: CAPV Position                */\r
+#define CCU4_ECRD_CAPV_Msk                    (0x0000ffffUL << CCU4_ECRD_CAPV_Pos)                    /*!< CCU4 ECRD: CAPV Mask                    */\r
+#define CCU4_ECRD_FPCV_Pos                    16                                                      /*!< CCU4 ECRD: FPCV Position                */\r
+#define CCU4_ECRD_FPCV_Msk                    (0x0fUL << CCU4_ECRD_FPCV_Pos)                          /*!< CCU4 ECRD: FPCV Mask                    */\r
+#define CCU4_ECRD_SPTR_Pos                    20                                                      /*!< CCU4 ECRD: SPTR Position                */\r
+#define CCU4_ECRD_SPTR_Msk                    (0x03UL << CCU4_ECRD_SPTR_Pos)                          /*!< CCU4 ECRD: SPTR Mask                    */\r
+#define CCU4_ECRD_VPTR_Pos                    22                                                      /*!< CCU4 ECRD: VPTR Position                */\r
+#define CCU4_ECRD_VPTR_Msk                    (0x03UL << CCU4_ECRD_VPTR_Pos)                          /*!< CCU4 ECRD: VPTR Mask                    */\r
+#define CCU4_ECRD_FFL_Pos                     24                                                      /*!< CCU4 ECRD: FFL Position                 */\r
+#define CCU4_ECRD_FFL_Msk                     (0x01UL << CCU4_ECRD_FFL_Pos)                           /*!< CCU4 ECRD: FFL Mask                     */\r
+\r
+/* ----------------------------------  CCU4_MIDR  --------------------------------- */\r
+#define CCU4_MIDR_MODR_Pos                    0                                                       /*!< CCU4 MIDR: MODR Position                */\r
+#define CCU4_MIDR_MODR_Msk                    (0x000000ffUL << CCU4_MIDR_MODR_Pos)                    /*!< CCU4 MIDR: MODR Mask                    */\r
+#define CCU4_MIDR_MODT_Pos                    8                                                       /*!< CCU4 MIDR: MODT Position                */\r
+#define CCU4_MIDR_MODT_Msk                    (0x000000ffUL << CCU4_MIDR_MODT_Pos)                    /*!< CCU4 MIDR: MODT Mask                    */\r
+#define CCU4_MIDR_MODN_Pos                    16                                                      /*!< CCU4 MIDR: MODN Position                */\r
+#define CCU4_MIDR_MODN_Msk                    (0x0000ffffUL << CCU4_MIDR_MODN_Pos)                    /*!< CCU4 MIDR: MODN Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        Group 'CCU4_CC4' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CCU4_CC4_INS  -------------------------------- */\r
+#define CCU4_CC4_INS_EV0IS_Pos                0                                                       /*!< CCU4_CC4 INS: EV0IS Position            */\r
+#define CCU4_CC4_INS_EV0IS_Msk                (0x0fUL << CCU4_CC4_INS_EV0IS_Pos)                      /*!< CCU4_CC4 INS: EV0IS Mask                */\r
+#define CCU4_CC4_INS_EV1IS_Pos                4                                                       /*!< CCU4_CC4 INS: EV1IS Position            */\r
+#define CCU4_CC4_INS_EV1IS_Msk                (0x0fUL << CCU4_CC4_INS_EV1IS_Pos)                      /*!< CCU4_CC4 INS: EV1IS Mask                */\r
+#define CCU4_CC4_INS_EV2IS_Pos                8                                                       /*!< CCU4_CC4 INS: EV2IS Position            */\r
+#define CCU4_CC4_INS_EV2IS_Msk                (0x0fUL << CCU4_CC4_INS_EV2IS_Pos)                      /*!< CCU4_CC4 INS: EV2IS Mask                */\r
+#define CCU4_CC4_INS_EV0EM_Pos                16                                                      /*!< CCU4_CC4 INS: EV0EM Position            */\r
+#define CCU4_CC4_INS_EV0EM_Msk                (0x03UL << CCU4_CC4_INS_EV0EM_Pos)                      /*!< CCU4_CC4 INS: EV0EM Mask                */\r
+#define CCU4_CC4_INS_EV1EM_Pos                18                                                      /*!< CCU4_CC4 INS: EV1EM Position            */\r
+#define CCU4_CC4_INS_EV1EM_Msk                (0x03UL << CCU4_CC4_INS_EV1EM_Pos)                      /*!< CCU4_CC4 INS: EV1EM Mask                */\r
+#define CCU4_CC4_INS_EV2EM_Pos                20                                                      /*!< CCU4_CC4 INS: EV2EM Position            */\r
+#define CCU4_CC4_INS_EV2EM_Msk                (0x03UL << CCU4_CC4_INS_EV2EM_Pos)                      /*!< CCU4_CC4 INS: EV2EM Mask                */\r
+#define CCU4_CC4_INS_EV0LM_Pos                22                                                      /*!< CCU4_CC4 INS: EV0LM Position            */\r
+#define CCU4_CC4_INS_EV0LM_Msk                (0x01UL << CCU4_CC4_INS_EV0LM_Pos)                      /*!< CCU4_CC4 INS: EV0LM Mask                */\r
+#define CCU4_CC4_INS_EV1LM_Pos                23                                                      /*!< CCU4_CC4 INS: EV1LM Position            */\r
+#define CCU4_CC4_INS_EV1LM_Msk                (0x01UL << CCU4_CC4_INS_EV1LM_Pos)                      /*!< CCU4_CC4 INS: EV1LM Mask                */\r
+#define CCU4_CC4_INS_EV2LM_Pos                24                                                      /*!< CCU4_CC4 INS: EV2LM Position            */\r
+#define CCU4_CC4_INS_EV2LM_Msk                (0x01UL << CCU4_CC4_INS_EV2LM_Pos)                      /*!< CCU4_CC4 INS: EV2LM Mask                */\r
+#define CCU4_CC4_INS_LPF0M_Pos                25                                                      /*!< CCU4_CC4 INS: LPF0M Position            */\r
+#define CCU4_CC4_INS_LPF0M_Msk                (0x03UL << CCU4_CC4_INS_LPF0M_Pos)                      /*!< CCU4_CC4 INS: LPF0M Mask                */\r
+#define CCU4_CC4_INS_LPF1M_Pos                27                                                      /*!< CCU4_CC4 INS: LPF1M Position            */\r
+#define CCU4_CC4_INS_LPF1M_Msk                (0x03UL << CCU4_CC4_INS_LPF1M_Pos)                      /*!< CCU4_CC4 INS: LPF1M Mask                */\r
+#define CCU4_CC4_INS_LPF2M_Pos                29                                                      /*!< CCU4_CC4 INS: LPF2M Position            */\r
+#define CCU4_CC4_INS_LPF2M_Msk                (0x03UL << CCU4_CC4_INS_LPF2M_Pos)                      /*!< CCU4_CC4 INS: LPF2M Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_CMC  -------------------------------- */\r
+#define CCU4_CC4_CMC_STRTS_Pos                0                                                       /*!< CCU4_CC4 CMC: STRTS Position            */\r
+#define CCU4_CC4_CMC_STRTS_Msk                (0x03UL << CCU4_CC4_CMC_STRTS_Pos)                      /*!< CCU4_CC4 CMC: STRTS Mask                */\r
+#define CCU4_CC4_CMC_ENDS_Pos                 2                                                       /*!< CCU4_CC4 CMC: ENDS Position             */\r
+#define CCU4_CC4_CMC_ENDS_Msk                 (0x03UL << CCU4_CC4_CMC_ENDS_Pos)                       /*!< CCU4_CC4 CMC: ENDS Mask                 */\r
+#define CCU4_CC4_CMC_CAP0S_Pos                4                                                       /*!< CCU4_CC4 CMC: CAP0S Position            */\r
+#define CCU4_CC4_CMC_CAP0S_Msk                (0x03UL << CCU4_CC4_CMC_CAP0S_Pos)                      /*!< CCU4_CC4 CMC: CAP0S Mask                */\r
+#define CCU4_CC4_CMC_CAP1S_Pos                6                                                       /*!< CCU4_CC4 CMC: CAP1S Position            */\r
+#define CCU4_CC4_CMC_CAP1S_Msk                (0x03UL << CCU4_CC4_CMC_CAP1S_Pos)                      /*!< CCU4_CC4 CMC: CAP1S Mask                */\r
+#define CCU4_CC4_CMC_GATES_Pos                8                                                       /*!< CCU4_CC4 CMC: GATES Position            */\r
+#define CCU4_CC4_CMC_GATES_Msk                (0x03UL << CCU4_CC4_CMC_GATES_Pos)                      /*!< CCU4_CC4 CMC: GATES Mask                */\r
+#define CCU4_CC4_CMC_UDS_Pos                  10                                                      /*!< CCU4_CC4 CMC: UDS Position              */\r
+#define CCU4_CC4_CMC_UDS_Msk                  (0x03UL << CCU4_CC4_CMC_UDS_Pos)                        /*!< CCU4_CC4 CMC: UDS Mask                  */\r
+#define CCU4_CC4_CMC_LDS_Pos                  12                                                      /*!< CCU4_CC4 CMC: LDS Position              */\r
+#define CCU4_CC4_CMC_LDS_Msk                  (0x03UL << CCU4_CC4_CMC_LDS_Pos)                        /*!< CCU4_CC4 CMC: LDS Mask                  */\r
+#define CCU4_CC4_CMC_CNTS_Pos                 14                                                      /*!< CCU4_CC4 CMC: CNTS Position             */\r
+#define CCU4_CC4_CMC_CNTS_Msk                 (0x03UL << CCU4_CC4_CMC_CNTS_Pos)                       /*!< CCU4_CC4 CMC: CNTS Mask                 */\r
+#define CCU4_CC4_CMC_OFS_Pos                  16                                                      /*!< CCU4_CC4 CMC: OFS Position              */\r
+#define CCU4_CC4_CMC_OFS_Msk                  (0x01UL << CCU4_CC4_CMC_OFS_Pos)                        /*!< CCU4_CC4 CMC: OFS Mask                  */\r
+#define CCU4_CC4_CMC_TS_Pos                   17                                                      /*!< CCU4_CC4 CMC: TS Position               */\r
+#define CCU4_CC4_CMC_TS_Msk                   (0x01UL << CCU4_CC4_CMC_TS_Pos)                         /*!< CCU4_CC4 CMC: TS Mask                   */\r
+#define CCU4_CC4_CMC_MOS_Pos                  18                                                      /*!< CCU4_CC4 CMC: MOS Position              */\r
+#define CCU4_CC4_CMC_MOS_Msk                  (0x03UL << CCU4_CC4_CMC_MOS_Pos)                        /*!< CCU4_CC4 CMC: MOS Mask                  */\r
+#define CCU4_CC4_CMC_TCE_Pos                  20                                                      /*!< CCU4_CC4 CMC: TCE Position              */\r
+#define CCU4_CC4_CMC_TCE_Msk                  (0x01UL << CCU4_CC4_CMC_TCE_Pos)                        /*!< CCU4_CC4 CMC: TCE Mask                  */\r
+\r
+/* --------------------------------  CCU4_CC4_TCST  ------------------------------- */\r
+#define CCU4_CC4_TCST_TRB_Pos                 0                                                       /*!< CCU4_CC4 TCST: TRB Position             */\r
+#define CCU4_CC4_TCST_TRB_Msk                 (0x01UL << CCU4_CC4_TCST_TRB_Pos)                       /*!< CCU4_CC4 TCST: TRB Mask                 */\r
+#define CCU4_CC4_TCST_CDIR_Pos                1                                                       /*!< CCU4_CC4 TCST: CDIR Position            */\r
+#define CCU4_CC4_TCST_CDIR_Msk                (0x01UL << CCU4_CC4_TCST_CDIR_Pos)                      /*!< CCU4_CC4 TCST: CDIR Mask                */\r
+\r
+/* -------------------------------  CCU4_CC4_TCSET  ------------------------------- */\r
+#define CCU4_CC4_TCSET_TRBS_Pos               0                                                       /*!< CCU4_CC4 TCSET: TRBS Position           */\r
+#define CCU4_CC4_TCSET_TRBS_Msk               (0x01UL << CCU4_CC4_TCSET_TRBS_Pos)                     /*!< CCU4_CC4 TCSET: TRBS Mask               */\r
+\r
+/* -------------------------------  CCU4_CC4_TCCLR  ------------------------------- */\r
+#define CCU4_CC4_TCCLR_TRBC_Pos               0                                                       /*!< CCU4_CC4 TCCLR: TRBC Position           */\r
+#define CCU4_CC4_TCCLR_TRBC_Msk               (0x01UL << CCU4_CC4_TCCLR_TRBC_Pos)                     /*!< CCU4_CC4 TCCLR: TRBC Mask               */\r
+#define CCU4_CC4_TCCLR_TCC_Pos                1                                                       /*!< CCU4_CC4 TCCLR: TCC Position            */\r
+#define CCU4_CC4_TCCLR_TCC_Msk                (0x01UL << CCU4_CC4_TCCLR_TCC_Pos)                      /*!< CCU4_CC4 TCCLR: TCC Mask                */\r
+#define CCU4_CC4_TCCLR_DITC_Pos               2                                                       /*!< CCU4_CC4 TCCLR: DITC Position           */\r
+#define CCU4_CC4_TCCLR_DITC_Msk               (0x01UL << CCU4_CC4_TCCLR_DITC_Pos)                     /*!< CCU4_CC4 TCCLR: DITC Mask               */\r
+\r
+/* ---------------------------------  CCU4_CC4_TC  -------------------------------- */\r
+#define CCU4_CC4_TC_TCM_Pos                   0                                                       /*!< CCU4_CC4 TC: TCM Position               */\r
+#define CCU4_CC4_TC_TCM_Msk                   (0x01UL << CCU4_CC4_TC_TCM_Pos)                         /*!< CCU4_CC4 TC: TCM Mask                   */\r
+#define CCU4_CC4_TC_TSSM_Pos                  1                                                       /*!< CCU4_CC4 TC: TSSM Position              */\r
+#define CCU4_CC4_TC_TSSM_Msk                  (0x01UL << CCU4_CC4_TC_TSSM_Pos)                        /*!< CCU4_CC4 TC: TSSM Mask                  */\r
+#define CCU4_CC4_TC_CLST_Pos                  2                                                       /*!< CCU4_CC4 TC: CLST Position              */\r
+#define CCU4_CC4_TC_CLST_Msk                  (0x01UL << CCU4_CC4_TC_CLST_Pos)                        /*!< CCU4_CC4 TC: CLST Mask                  */\r
+#define CCU4_CC4_TC_CMOD_Pos                  3                                                       /*!< CCU4_CC4 TC: CMOD Position              */\r
+#define CCU4_CC4_TC_CMOD_Msk                  (0x01UL << CCU4_CC4_TC_CMOD_Pos)                        /*!< CCU4_CC4 TC: CMOD Mask                  */\r
+#define CCU4_CC4_TC_ECM_Pos                   4                                                       /*!< CCU4_CC4 TC: ECM Position               */\r
+#define CCU4_CC4_TC_ECM_Msk                   (0x01UL << CCU4_CC4_TC_ECM_Pos)                         /*!< CCU4_CC4 TC: ECM Mask                   */\r
+#define CCU4_CC4_TC_CAPC_Pos                  5                                                       /*!< CCU4_CC4 TC: CAPC Position              */\r
+#define CCU4_CC4_TC_CAPC_Msk                  (0x03UL << CCU4_CC4_TC_CAPC_Pos)                        /*!< CCU4_CC4 TC: CAPC Mask                  */\r
+#define CCU4_CC4_TC_ENDM_Pos                  8                                                       /*!< CCU4_CC4 TC: ENDM Position              */\r
+#define CCU4_CC4_TC_ENDM_Msk                  (0x03UL << CCU4_CC4_TC_ENDM_Pos)                        /*!< CCU4_CC4 TC: ENDM Mask                  */\r
+#define CCU4_CC4_TC_STRM_Pos                  10                                                      /*!< CCU4_CC4 TC: STRM Position              */\r
+#define CCU4_CC4_TC_STRM_Msk                  (0x01UL << CCU4_CC4_TC_STRM_Pos)                        /*!< CCU4_CC4 TC: STRM Mask                  */\r
+#define CCU4_CC4_TC_SCE_Pos                   11                                                      /*!< CCU4_CC4 TC: SCE Position               */\r
+#define CCU4_CC4_TC_SCE_Msk                   (0x01UL << CCU4_CC4_TC_SCE_Pos)                         /*!< CCU4_CC4 TC: SCE Mask                   */\r
+#define CCU4_CC4_TC_CCS_Pos                   12                                                      /*!< CCU4_CC4 TC: CCS Position               */\r
+#define CCU4_CC4_TC_CCS_Msk                   (0x01UL << CCU4_CC4_TC_CCS_Pos)                         /*!< CCU4_CC4 TC: CCS Mask                   */\r
+#define CCU4_CC4_TC_DITHE_Pos                 13                                                      /*!< CCU4_CC4 TC: DITHE Position             */\r
+#define CCU4_CC4_TC_DITHE_Msk                 (0x03UL << CCU4_CC4_TC_DITHE_Pos)                       /*!< CCU4_CC4 TC: DITHE Mask                 */\r
+#define CCU4_CC4_TC_DIM_Pos                   15                                                      /*!< CCU4_CC4 TC: DIM Position               */\r
+#define CCU4_CC4_TC_DIM_Msk                   (0x01UL << CCU4_CC4_TC_DIM_Pos)                         /*!< CCU4_CC4 TC: DIM Mask                   */\r
+#define CCU4_CC4_TC_FPE_Pos                   16                                                      /*!< CCU4_CC4 TC: FPE Position               */\r
+#define CCU4_CC4_TC_FPE_Msk                   (0x01UL << CCU4_CC4_TC_FPE_Pos)                         /*!< CCU4_CC4 TC: FPE Mask                   */\r
+#define CCU4_CC4_TC_TRAPE_Pos                 17                                                      /*!< CCU4_CC4 TC: TRAPE Position             */\r
+#define CCU4_CC4_TC_TRAPE_Msk                 (0x01UL << CCU4_CC4_TC_TRAPE_Pos)                       /*!< CCU4_CC4 TC: TRAPE Mask                 */\r
+#define CCU4_CC4_TC_TRPSE_Pos                 21                                                      /*!< CCU4_CC4 TC: TRPSE Position             */\r
+#define CCU4_CC4_TC_TRPSE_Msk                 (0x01UL << CCU4_CC4_TC_TRPSE_Pos)                       /*!< CCU4_CC4 TC: TRPSE Mask                 */\r
+#define CCU4_CC4_TC_TRPSW_Pos                 22                                                      /*!< CCU4_CC4 TC: TRPSW Position             */\r
+#define CCU4_CC4_TC_TRPSW_Msk                 (0x01UL << CCU4_CC4_TC_TRPSW_Pos)                       /*!< CCU4_CC4 TC: TRPSW Mask                 */\r
+#define CCU4_CC4_TC_EMS_Pos                   23                                                      /*!< CCU4_CC4 TC: EMS Position               */\r
+#define CCU4_CC4_TC_EMS_Msk                   (0x01UL << CCU4_CC4_TC_EMS_Pos)                         /*!< CCU4_CC4 TC: EMS Mask                   */\r
+#define CCU4_CC4_TC_EMT_Pos                   24                                                      /*!< CCU4_CC4 TC: EMT Position               */\r
+#define CCU4_CC4_TC_EMT_Msk                   (0x01UL << CCU4_CC4_TC_EMT_Pos)                         /*!< CCU4_CC4 TC: EMT Mask                   */\r
+#define CCU4_CC4_TC_MCME_Pos                  25                                                      /*!< CCU4_CC4 TC: MCME Position              */\r
+#define CCU4_CC4_TC_MCME_Msk                  (0x01UL << CCU4_CC4_TC_MCME_Pos)                        /*!< CCU4_CC4 TC: MCME Mask                  */\r
+\r
+/* --------------------------------  CCU4_CC4_PSL  -------------------------------- */\r
+#define CCU4_CC4_PSL_PSL_Pos                  0                                                       /*!< CCU4_CC4 PSL: PSL Position              */\r
+#define CCU4_CC4_PSL_PSL_Msk                  (0x01UL << CCU4_CC4_PSL_PSL_Pos)                        /*!< CCU4_CC4 PSL: PSL Mask                  */\r
+\r
+/* --------------------------------  CCU4_CC4_DIT  -------------------------------- */\r
+#define CCU4_CC4_DIT_DCV_Pos                  0                                                       /*!< CCU4_CC4 DIT: DCV Position              */\r
+#define CCU4_CC4_DIT_DCV_Msk                  (0x0fUL << CCU4_CC4_DIT_DCV_Pos)                        /*!< CCU4_CC4 DIT: DCV Mask                  */\r
+#define CCU4_CC4_DIT_DCNT_Pos                 8                                                       /*!< CCU4_CC4 DIT: DCNT Position             */\r
+#define CCU4_CC4_DIT_DCNT_Msk                 (0x0fUL << CCU4_CC4_DIT_DCNT_Pos)                       /*!< CCU4_CC4 DIT: DCNT Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_DITS  ------------------------------- */\r
+#define CCU4_CC4_DITS_DCVS_Pos                0                                                       /*!< CCU4_CC4 DITS: DCVS Position            */\r
+#define CCU4_CC4_DITS_DCVS_Msk                (0x0fUL << CCU4_CC4_DITS_DCVS_Pos)                      /*!< CCU4_CC4 DITS: DCVS Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_PSC  -------------------------------- */\r
+#define CCU4_CC4_PSC_PSIV_Pos                 0                                                       /*!< CCU4_CC4 PSC: PSIV Position             */\r
+#define CCU4_CC4_PSC_PSIV_Msk                 (0x0fUL << CCU4_CC4_PSC_PSIV_Pos)                       /*!< CCU4_CC4 PSC: PSIV Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_FPC  -------------------------------- */\r
+#define CCU4_CC4_FPC_PCMP_Pos                 0                                                       /*!< CCU4_CC4 FPC: PCMP Position             */\r
+#define CCU4_CC4_FPC_PCMP_Msk                 (0x0fUL << CCU4_CC4_FPC_PCMP_Pos)                       /*!< CCU4_CC4 FPC: PCMP Mask                 */\r
+#define CCU4_CC4_FPC_PVAL_Pos                 8                                                       /*!< CCU4_CC4 FPC: PVAL Position             */\r
+#define CCU4_CC4_FPC_PVAL_Msk                 (0x0fUL << CCU4_CC4_FPC_PVAL_Pos)                       /*!< CCU4_CC4 FPC: PVAL Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_FPCS  ------------------------------- */\r
+#define CCU4_CC4_FPCS_PCMP_Pos                0                                                       /*!< CCU4_CC4 FPCS: PCMP Position            */\r
+#define CCU4_CC4_FPCS_PCMP_Msk                (0x0fUL << CCU4_CC4_FPCS_PCMP_Pos)                      /*!< CCU4_CC4 FPCS: PCMP Mask                */\r
+\r
+/* ---------------------------------  CCU4_CC4_PR  -------------------------------- */\r
+#define CCU4_CC4_PR_PR_Pos                    0                                                       /*!< CCU4_CC4 PR: PR Position                */\r
+#define CCU4_CC4_PR_PR_Msk                    (0x0000ffffUL << CCU4_CC4_PR_PR_Pos)                    /*!< CCU4_CC4 PR: PR Mask                    */\r
+\r
+/* --------------------------------  CCU4_CC4_PRS  -------------------------------- */\r
+#define CCU4_CC4_PRS_PRS_Pos                  0                                                       /*!< CCU4_CC4 PRS: PRS Position              */\r
+#define CCU4_CC4_PRS_PRS_Msk                  (0x0000ffffUL << CCU4_CC4_PRS_PRS_Pos)                  /*!< CCU4_CC4 PRS: PRS Mask                  */\r
+\r
+/* ---------------------------------  CCU4_CC4_CR  -------------------------------- */\r
+#define CCU4_CC4_CR_CR_Pos                    0                                                       /*!< CCU4_CC4 CR: CR Position                */\r
+#define CCU4_CC4_CR_CR_Msk                    (0x0000ffffUL << CCU4_CC4_CR_CR_Pos)                    /*!< CCU4_CC4 CR: CR Mask                    */\r
+\r
+/* --------------------------------  CCU4_CC4_CRS  -------------------------------- */\r
+#define CCU4_CC4_CRS_CRS_Pos                  0                                                       /*!< CCU4_CC4 CRS: CRS Position              */\r
+#define CCU4_CC4_CRS_CRS_Msk                  (0x0000ffffUL << CCU4_CC4_CRS_CRS_Pos)                  /*!< CCU4_CC4 CRS: CRS Mask                  */\r
+\r
+/* -------------------------------  CCU4_CC4_TIMER  ------------------------------- */\r
+#define CCU4_CC4_TIMER_TVAL_Pos               0                                                       /*!< CCU4_CC4 TIMER: TVAL Position           */\r
+#define CCU4_CC4_TIMER_TVAL_Msk               (0x0000ffffUL << CCU4_CC4_TIMER_TVAL_Pos)               /*!< CCU4_CC4 TIMER: TVAL Mask               */\r
+\r
+/* ---------------------------------  CCU4_CC4_CV  -------------------------------- */\r
+#define CCU4_CC4_CV_CAPTV_Pos                 0                                                       /*!< CCU4_CC4 CV: CAPTV Position             */\r
+#define CCU4_CC4_CV_CAPTV_Msk                 (0x0000ffffUL << CCU4_CC4_CV_CAPTV_Pos)                 /*!< CCU4_CC4 CV: CAPTV Mask                 */\r
+#define CCU4_CC4_CV_FPCV_Pos                  16                                                      /*!< CCU4_CC4 CV: FPCV Position              */\r
+#define CCU4_CC4_CV_FPCV_Msk                  (0x0fUL << CCU4_CC4_CV_FPCV_Pos)                        /*!< CCU4_CC4 CV: FPCV Mask                  */\r
+#define CCU4_CC4_CV_FFL_Pos                   20                                                      /*!< CCU4_CC4 CV: FFL Position               */\r
+#define CCU4_CC4_CV_FFL_Msk                   (0x01UL << CCU4_CC4_CV_FFL_Pos)                         /*!< CCU4_CC4 CV: FFL Mask                   */\r
+\r
+/* --------------------------------  CCU4_CC4_INTS  ------------------------------- */\r
+#define CCU4_CC4_INTS_PMUS_Pos                0                                                       /*!< CCU4_CC4 INTS: PMUS Position            */\r
+#define CCU4_CC4_INTS_PMUS_Msk                (0x01UL << CCU4_CC4_INTS_PMUS_Pos)                      /*!< CCU4_CC4 INTS: PMUS Mask                */\r
+#define CCU4_CC4_INTS_OMDS_Pos                1                                                       /*!< CCU4_CC4 INTS: OMDS Position            */\r
+#define CCU4_CC4_INTS_OMDS_Msk                (0x01UL << CCU4_CC4_INTS_OMDS_Pos)                      /*!< CCU4_CC4 INTS: OMDS Mask                */\r
+#define CCU4_CC4_INTS_CMUS_Pos                2                                                       /*!< CCU4_CC4 INTS: CMUS Position            */\r
+#define CCU4_CC4_INTS_CMUS_Msk                (0x01UL << CCU4_CC4_INTS_CMUS_Pos)                      /*!< CCU4_CC4 INTS: CMUS Mask                */\r
+#define CCU4_CC4_INTS_CMDS_Pos                3                                                       /*!< CCU4_CC4 INTS: CMDS Position            */\r
+#define CCU4_CC4_INTS_CMDS_Msk                (0x01UL << CCU4_CC4_INTS_CMDS_Pos)                      /*!< CCU4_CC4 INTS: CMDS Mask                */\r
+#define CCU4_CC4_INTS_E0AS_Pos                8                                                       /*!< CCU4_CC4 INTS: E0AS Position            */\r
+#define CCU4_CC4_INTS_E0AS_Msk                (0x01UL << CCU4_CC4_INTS_E0AS_Pos)                      /*!< CCU4_CC4 INTS: E0AS Mask                */\r
+#define CCU4_CC4_INTS_E1AS_Pos                9                                                       /*!< CCU4_CC4 INTS: E1AS Position            */\r
+#define CCU4_CC4_INTS_E1AS_Msk                (0x01UL << CCU4_CC4_INTS_E1AS_Pos)                      /*!< CCU4_CC4 INTS: E1AS Mask                */\r
+#define CCU4_CC4_INTS_E2AS_Pos                10                                                      /*!< CCU4_CC4 INTS: E2AS Position            */\r
+#define CCU4_CC4_INTS_E2AS_Msk                (0x01UL << CCU4_CC4_INTS_E2AS_Pos)                      /*!< CCU4_CC4 INTS: E2AS Mask                */\r
+#define CCU4_CC4_INTS_TRPF_Pos                11                                                      /*!< CCU4_CC4 INTS: TRPF Position            */\r
+#define CCU4_CC4_INTS_TRPF_Msk                (0x01UL << CCU4_CC4_INTS_TRPF_Pos)                      /*!< CCU4_CC4 INTS: TRPF Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_INTE  ------------------------------- */\r
+#define CCU4_CC4_INTE_PME_Pos                 0                                                       /*!< CCU4_CC4 INTE: PME Position             */\r
+#define CCU4_CC4_INTE_PME_Msk                 (0x01UL << CCU4_CC4_INTE_PME_Pos)                       /*!< CCU4_CC4 INTE: PME Mask                 */\r
+#define CCU4_CC4_INTE_OME_Pos                 1                                                       /*!< CCU4_CC4 INTE: OME Position             */\r
+#define CCU4_CC4_INTE_OME_Msk                 (0x01UL << CCU4_CC4_INTE_OME_Pos)                       /*!< CCU4_CC4 INTE: OME Mask                 */\r
+#define CCU4_CC4_INTE_CMUE_Pos                2                                                       /*!< CCU4_CC4 INTE: CMUE Position            */\r
+#define CCU4_CC4_INTE_CMUE_Msk                (0x01UL << CCU4_CC4_INTE_CMUE_Pos)                      /*!< CCU4_CC4 INTE: CMUE Mask                */\r
+#define CCU4_CC4_INTE_CMDE_Pos                3                                                       /*!< CCU4_CC4 INTE: CMDE Position            */\r
+#define CCU4_CC4_INTE_CMDE_Msk                (0x01UL << CCU4_CC4_INTE_CMDE_Pos)                      /*!< CCU4_CC4 INTE: CMDE Mask                */\r
+#define CCU4_CC4_INTE_E0AE_Pos                8                                                       /*!< CCU4_CC4 INTE: E0AE Position            */\r
+#define CCU4_CC4_INTE_E0AE_Msk                (0x01UL << CCU4_CC4_INTE_E0AE_Pos)                      /*!< CCU4_CC4 INTE: E0AE Mask                */\r
+#define CCU4_CC4_INTE_E1AE_Pos                9                                                       /*!< CCU4_CC4 INTE: E1AE Position            */\r
+#define CCU4_CC4_INTE_E1AE_Msk                (0x01UL << CCU4_CC4_INTE_E1AE_Pos)                      /*!< CCU4_CC4 INTE: E1AE Mask                */\r
+#define CCU4_CC4_INTE_E2AE_Pos                10                                                      /*!< CCU4_CC4 INTE: E2AE Position            */\r
+#define CCU4_CC4_INTE_E2AE_Msk                (0x01UL << CCU4_CC4_INTE_E2AE_Pos)                      /*!< CCU4_CC4 INTE: E2AE Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_SRS  -------------------------------- */\r
+#define CCU4_CC4_SRS_POSR_Pos                 0                                                       /*!< CCU4_CC4 SRS: POSR Position             */\r
+#define CCU4_CC4_SRS_POSR_Msk                 (0x03UL << CCU4_CC4_SRS_POSR_Pos)                       /*!< CCU4_CC4 SRS: POSR Mask                 */\r
+#define CCU4_CC4_SRS_CMSR_Pos                 2                                                       /*!< CCU4_CC4 SRS: CMSR Position             */\r
+#define CCU4_CC4_SRS_CMSR_Msk                 (0x03UL << CCU4_CC4_SRS_CMSR_Pos)                       /*!< CCU4_CC4 SRS: CMSR Mask                 */\r
+#define CCU4_CC4_SRS_E0SR_Pos                 8                                                       /*!< CCU4_CC4 SRS: E0SR Position             */\r
+#define CCU4_CC4_SRS_E0SR_Msk                 (0x03UL << CCU4_CC4_SRS_E0SR_Pos)                       /*!< CCU4_CC4 SRS: E0SR Mask                 */\r
+#define CCU4_CC4_SRS_E1SR_Pos                 10                                                      /*!< CCU4_CC4 SRS: E1SR Position             */\r
+#define CCU4_CC4_SRS_E1SR_Msk                 (0x03UL << CCU4_CC4_SRS_E1SR_Pos)                       /*!< CCU4_CC4 SRS: E1SR Mask                 */\r
+#define CCU4_CC4_SRS_E2SR_Pos                 12                                                      /*!< CCU4_CC4 SRS: E2SR Position             */\r
+#define CCU4_CC4_SRS_E2SR_Msk                 (0x03UL << CCU4_CC4_SRS_E2SR_Pos)                       /*!< CCU4_CC4 SRS: E2SR Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_SWS  -------------------------------- */\r
+#define CCU4_CC4_SWS_SPM_Pos                  0                                                       /*!< CCU4_CC4 SWS: SPM Position              */\r
+#define CCU4_CC4_SWS_SPM_Msk                  (0x01UL << CCU4_CC4_SWS_SPM_Pos)                        /*!< CCU4_CC4 SWS: SPM Mask                  */\r
+#define CCU4_CC4_SWS_SOM_Pos                  1                                                       /*!< CCU4_CC4 SWS: SOM Position              */\r
+#define CCU4_CC4_SWS_SOM_Msk                  (0x01UL << CCU4_CC4_SWS_SOM_Pos)                        /*!< CCU4_CC4 SWS: SOM Mask                  */\r
+#define CCU4_CC4_SWS_SCMU_Pos                 2                                                       /*!< CCU4_CC4 SWS: SCMU Position             */\r
+#define CCU4_CC4_SWS_SCMU_Msk                 (0x01UL << CCU4_CC4_SWS_SCMU_Pos)                       /*!< CCU4_CC4 SWS: SCMU Mask                 */\r
+#define CCU4_CC4_SWS_SCMD_Pos                 3                                                       /*!< CCU4_CC4 SWS: SCMD Position             */\r
+#define CCU4_CC4_SWS_SCMD_Msk                 (0x01UL << CCU4_CC4_SWS_SCMD_Pos)                       /*!< CCU4_CC4 SWS: SCMD Mask                 */\r
+#define CCU4_CC4_SWS_SE0A_Pos                 8                                                       /*!< CCU4_CC4 SWS: SE0A Position             */\r
+#define CCU4_CC4_SWS_SE0A_Msk                 (0x01UL << CCU4_CC4_SWS_SE0A_Pos)                       /*!< CCU4_CC4 SWS: SE0A Mask                 */\r
+#define CCU4_CC4_SWS_SE1A_Pos                 9                                                       /*!< CCU4_CC4 SWS: SE1A Position             */\r
+#define CCU4_CC4_SWS_SE1A_Msk                 (0x01UL << CCU4_CC4_SWS_SE1A_Pos)                       /*!< CCU4_CC4 SWS: SE1A Mask                 */\r
+#define CCU4_CC4_SWS_SE2A_Pos                 10                                                      /*!< CCU4_CC4 SWS: SE2A Position             */\r
+#define CCU4_CC4_SWS_SE2A_Msk                 (0x01UL << CCU4_CC4_SWS_SE2A_Pos)                       /*!< CCU4_CC4 SWS: SE2A Mask                 */\r
+#define CCU4_CC4_SWS_STRPF_Pos                11                                                      /*!< CCU4_CC4 SWS: STRPF Position            */\r
+#define CCU4_CC4_SWS_STRPF_Msk                (0x01UL << CCU4_CC4_SWS_STRPF_Pos)                      /*!< CCU4_CC4 SWS: STRPF Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_SWR  -------------------------------- */\r
+#define CCU4_CC4_SWR_RPM_Pos                  0                                                       /*!< CCU4_CC4 SWR: RPM Position              */\r
+#define CCU4_CC4_SWR_RPM_Msk                  (0x01UL << CCU4_CC4_SWR_RPM_Pos)                        /*!< CCU4_CC4 SWR: RPM Mask                  */\r
+#define CCU4_CC4_SWR_ROM_Pos                  1                                                       /*!< CCU4_CC4 SWR: ROM Position              */\r
+#define CCU4_CC4_SWR_ROM_Msk                  (0x01UL << CCU4_CC4_SWR_ROM_Pos)                        /*!< CCU4_CC4 SWR: ROM Mask                  */\r
+#define CCU4_CC4_SWR_RCMU_Pos                 2                                                       /*!< CCU4_CC4 SWR: RCMU Position             */\r
+#define CCU4_CC4_SWR_RCMU_Msk                 (0x01UL << CCU4_CC4_SWR_RCMU_Pos)                       /*!< CCU4_CC4 SWR: RCMU Mask                 */\r
+#define CCU4_CC4_SWR_RCMD_Pos                 3                                                       /*!< CCU4_CC4 SWR: RCMD Position             */\r
+#define CCU4_CC4_SWR_RCMD_Msk                 (0x01UL << CCU4_CC4_SWR_RCMD_Pos)                       /*!< CCU4_CC4 SWR: RCMD Mask                 */\r
+#define CCU4_CC4_SWR_RE0A_Pos                 8                                                       /*!< CCU4_CC4 SWR: RE0A Position             */\r
+#define CCU4_CC4_SWR_RE0A_Msk                 (0x01UL << CCU4_CC4_SWR_RE0A_Pos)                       /*!< CCU4_CC4 SWR: RE0A Mask                 */\r
+#define CCU4_CC4_SWR_RE1A_Pos                 9                                                       /*!< CCU4_CC4 SWR: RE1A Position             */\r
+#define CCU4_CC4_SWR_RE1A_Msk                 (0x01UL << CCU4_CC4_SWR_RE1A_Pos)                       /*!< CCU4_CC4 SWR: RE1A Mask                 */\r
+#define CCU4_CC4_SWR_RE2A_Pos                 10                                                      /*!< CCU4_CC4 SWR: RE2A Position             */\r
+#define CCU4_CC4_SWR_RE2A_Msk                 (0x01UL << CCU4_CC4_SWR_RE2A_Pos)                       /*!< CCU4_CC4 SWR: RE2A Mask                 */\r
+#define CCU4_CC4_SWR_RTRPF_Pos                11                                                      /*!< CCU4_CC4 SWR: RTRPF Position            */\r
+#define CCU4_CC4_SWR_RTRPF_Msk                (0x01UL << CCU4_CC4_SWR_RTRPF_Pos)                      /*!< CCU4_CC4 SWR: RTRPF Mask                */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'CCU8' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  CCU8_GCTRL  --------------------------------- */\r
+#define CCU8_GCTRL_PRBC_Pos                   0                                                       /*!< CCU8 GCTRL: PRBC Position               */\r
+#define CCU8_GCTRL_PRBC_Msk                   (0x07UL << CCU8_GCTRL_PRBC_Pos)                         /*!< CCU8 GCTRL: PRBC Mask                   */\r
+#define CCU8_GCTRL_PCIS_Pos                   4                                                       /*!< CCU8 GCTRL: PCIS Position               */\r
+#define CCU8_GCTRL_PCIS_Msk                   (0x03UL << CCU8_GCTRL_PCIS_Pos)                         /*!< CCU8 GCTRL: PCIS Mask                   */\r
+#define CCU8_GCTRL_SUSCFG_Pos                 8                                                       /*!< CCU8 GCTRL: SUSCFG Position             */\r
+#define CCU8_GCTRL_SUSCFG_Msk                 (0x03UL << CCU8_GCTRL_SUSCFG_Pos)                       /*!< CCU8 GCTRL: SUSCFG Mask                 */\r
+#define CCU8_GCTRL_MSE0_Pos                   10                                                      /*!< CCU8 GCTRL: MSE0 Position               */\r
+#define CCU8_GCTRL_MSE0_Msk                   (0x01UL << CCU8_GCTRL_MSE0_Pos)                         /*!< CCU8 GCTRL: MSE0 Mask                   */\r
+#define CCU8_GCTRL_MSE1_Pos                   11                                                      /*!< CCU8 GCTRL: MSE1 Position               */\r
+#define CCU8_GCTRL_MSE1_Msk                   (0x01UL << CCU8_GCTRL_MSE1_Pos)                         /*!< CCU8 GCTRL: MSE1 Mask                   */\r
+#define CCU8_GCTRL_MSE2_Pos                   12                                                      /*!< CCU8 GCTRL: MSE2 Position               */\r
+#define CCU8_GCTRL_MSE2_Msk                   (0x01UL << CCU8_GCTRL_MSE2_Pos)                         /*!< CCU8 GCTRL: MSE2 Mask                   */\r
+#define CCU8_GCTRL_MSE3_Pos                   13                                                      /*!< CCU8 GCTRL: MSE3 Position               */\r
+#define CCU8_GCTRL_MSE3_Msk                   (0x01UL << CCU8_GCTRL_MSE3_Pos)                         /*!< CCU8 GCTRL: MSE3 Mask                   */\r
+#define CCU8_GCTRL_MSDE_Pos                   14                                                      /*!< CCU8 GCTRL: MSDE Position               */\r
+#define CCU8_GCTRL_MSDE_Msk                   (0x03UL << CCU8_GCTRL_MSDE_Pos)                         /*!< CCU8 GCTRL: MSDE Mask                   */\r
+\r
+/* ---------------------------------  CCU8_GSTAT  --------------------------------- */\r
+#define CCU8_GSTAT_S0I_Pos                    0                                                       /*!< CCU8 GSTAT: S0I Position                */\r
+#define CCU8_GSTAT_S0I_Msk                    (0x01UL << CCU8_GSTAT_S0I_Pos)                          /*!< CCU8 GSTAT: S0I Mask                    */\r
+#define CCU8_GSTAT_S1I_Pos                    1                                                       /*!< CCU8 GSTAT: S1I Position                */\r
+#define CCU8_GSTAT_S1I_Msk                    (0x01UL << CCU8_GSTAT_S1I_Pos)                          /*!< CCU8 GSTAT: S1I Mask                    */\r
+#define CCU8_GSTAT_S2I_Pos                    2                                                       /*!< CCU8 GSTAT: S2I Position                */\r
+#define CCU8_GSTAT_S2I_Msk                    (0x01UL << CCU8_GSTAT_S2I_Pos)                          /*!< CCU8 GSTAT: S2I Mask                    */\r
+#define CCU8_GSTAT_S3I_Pos                    3                                                       /*!< CCU8 GSTAT: S3I Position                */\r
+#define CCU8_GSTAT_S3I_Msk                    (0x01UL << CCU8_GSTAT_S3I_Pos)                          /*!< CCU8 GSTAT: S3I Mask                    */\r
+#define CCU8_GSTAT_PRB_Pos                    8                                                       /*!< CCU8 GSTAT: PRB Position                */\r
+#define CCU8_GSTAT_PRB_Msk                    (0x01UL << CCU8_GSTAT_PRB_Pos)                          /*!< CCU8 GSTAT: PRB Mask                    */\r
+#define CCU8_GSTAT_PCRB_Pos                   10                                                      /*!< CCU8 GSTAT: PCRB Position               */\r
+#define CCU8_GSTAT_PCRB_Msk                   (0x01UL << CCU8_GSTAT_PCRB_Pos)                         /*!< CCU8 GSTAT: PCRB Mask                   */\r
+\r
+/* ---------------------------------  CCU8_GIDLS  --------------------------------- */\r
+#define CCU8_GIDLS_SS0I_Pos                   0                                                       /*!< CCU8 GIDLS: SS0I Position               */\r
+#define CCU8_GIDLS_SS0I_Msk                   (0x01UL << CCU8_GIDLS_SS0I_Pos)                         /*!< CCU8 GIDLS: SS0I Mask                   */\r
+#define CCU8_GIDLS_SS1I_Pos                   1                                                       /*!< CCU8 GIDLS: SS1I Position               */\r
+#define CCU8_GIDLS_SS1I_Msk                   (0x01UL << CCU8_GIDLS_SS1I_Pos)                         /*!< CCU8 GIDLS: SS1I Mask                   */\r
+#define CCU8_GIDLS_SS2I_Pos                   2                                                       /*!< CCU8 GIDLS: SS2I Position               */\r
+#define CCU8_GIDLS_SS2I_Msk                   (0x01UL << CCU8_GIDLS_SS2I_Pos)                         /*!< CCU8 GIDLS: SS2I Mask                   */\r
+#define CCU8_GIDLS_SS3I_Pos                   3                                                       /*!< CCU8 GIDLS: SS3I Position               */\r
+#define CCU8_GIDLS_SS3I_Msk                   (0x01UL << CCU8_GIDLS_SS3I_Pos)                         /*!< CCU8 GIDLS: SS3I Mask                   */\r
+#define CCU8_GIDLS_CPRB_Pos                   8                                                       /*!< CCU8 GIDLS: CPRB Position               */\r
+#define CCU8_GIDLS_CPRB_Msk                   (0x01UL << CCU8_GIDLS_CPRB_Pos)                         /*!< CCU8 GIDLS: CPRB Mask                   */\r
+#define CCU8_GIDLS_PSIC_Pos                   9                                                       /*!< CCU8 GIDLS: PSIC Position               */\r
+#define CCU8_GIDLS_PSIC_Msk                   (0x01UL << CCU8_GIDLS_PSIC_Pos)                         /*!< CCU8 GIDLS: PSIC Mask                   */\r
+#define CCU8_GIDLS_CPCH_Pos                   10                                                      /*!< CCU8 GIDLS: CPCH Position               */\r
+#define CCU8_GIDLS_CPCH_Msk                   (0x01UL << CCU8_GIDLS_CPCH_Pos)                         /*!< CCU8 GIDLS: CPCH Mask                   */\r
+\r
+/* ---------------------------------  CCU8_GIDLC  --------------------------------- */\r
+#define CCU8_GIDLC_CS0I_Pos                   0                                                       /*!< CCU8 GIDLC: CS0I Position               */\r
+#define CCU8_GIDLC_CS0I_Msk                   (0x01UL << CCU8_GIDLC_CS0I_Pos)                         /*!< CCU8 GIDLC: CS0I Mask                   */\r
+#define CCU8_GIDLC_CS1I_Pos                   1                                                       /*!< CCU8 GIDLC: CS1I Position               */\r
+#define CCU8_GIDLC_CS1I_Msk                   (0x01UL << CCU8_GIDLC_CS1I_Pos)                         /*!< CCU8 GIDLC: CS1I Mask                   */\r
+#define CCU8_GIDLC_CS2I_Pos                   2                                                       /*!< CCU8 GIDLC: CS2I Position               */\r
+#define CCU8_GIDLC_CS2I_Msk                   (0x01UL << CCU8_GIDLC_CS2I_Pos)                         /*!< CCU8 GIDLC: CS2I Mask                   */\r
+#define CCU8_GIDLC_CS3I_Pos                   3                                                       /*!< CCU8 GIDLC: CS3I Position               */\r
+#define CCU8_GIDLC_CS3I_Msk                   (0x01UL << CCU8_GIDLC_CS3I_Pos)                         /*!< CCU8 GIDLC: CS3I Mask                   */\r
+#define CCU8_GIDLC_SPRB_Pos                   8                                                       /*!< CCU8 GIDLC: SPRB Position               */\r
+#define CCU8_GIDLC_SPRB_Msk                   (0x01UL << CCU8_GIDLC_SPRB_Pos)                         /*!< CCU8 GIDLC: SPRB Mask                   */\r
+#define CCU8_GIDLC_SPCH_Pos                   10                                                      /*!< CCU8 GIDLC: SPCH Position               */\r
+#define CCU8_GIDLC_SPCH_Msk                   (0x01UL << CCU8_GIDLC_SPCH_Pos)                         /*!< CCU8 GIDLC: SPCH Mask                   */\r
+\r
+/* ----------------------------------  CCU8_GCSS  --------------------------------- */\r
+#define CCU8_GCSS_S0SE_Pos                    0                                                       /*!< CCU8 GCSS: S0SE Position                */\r
+#define CCU8_GCSS_S0SE_Msk                    (0x01UL << CCU8_GCSS_S0SE_Pos)                          /*!< CCU8 GCSS: S0SE Mask                    */\r
+#define CCU8_GCSS_S0DSE_Pos                   1                                                       /*!< CCU8 GCSS: S0DSE Position               */\r
+#define CCU8_GCSS_S0DSE_Msk                   (0x01UL << CCU8_GCSS_S0DSE_Pos)                         /*!< CCU8 GCSS: S0DSE Mask                   */\r
+#define CCU8_GCSS_S0PSE_Pos                   2                                                       /*!< CCU8 GCSS: S0PSE Position               */\r
+#define CCU8_GCSS_S0PSE_Msk                   (0x01UL << CCU8_GCSS_S0PSE_Pos)                         /*!< CCU8 GCSS: S0PSE Mask                   */\r
+#define CCU8_GCSS_S1SE_Pos                    4                                                       /*!< CCU8 GCSS: S1SE Position                */\r
+#define CCU8_GCSS_S1SE_Msk                    (0x01UL << CCU8_GCSS_S1SE_Pos)                          /*!< CCU8 GCSS: S1SE Mask                    */\r
+#define CCU8_GCSS_S1DSE_Pos                   5                                                       /*!< CCU8 GCSS: S1DSE Position               */\r
+#define CCU8_GCSS_S1DSE_Msk                   (0x01UL << CCU8_GCSS_S1DSE_Pos)                         /*!< CCU8 GCSS: S1DSE Mask                   */\r
+#define CCU8_GCSS_S1PSE_Pos                   6                                                       /*!< CCU8 GCSS: S1PSE Position               */\r
+#define CCU8_GCSS_S1PSE_Msk                   (0x01UL << CCU8_GCSS_S1PSE_Pos)                         /*!< CCU8 GCSS: S1PSE Mask                   */\r
+#define CCU8_GCSS_S2SE_Pos                    8                                                       /*!< CCU8 GCSS: S2SE Position                */\r
+#define CCU8_GCSS_S2SE_Msk                    (0x01UL << CCU8_GCSS_S2SE_Pos)                          /*!< CCU8 GCSS: S2SE Mask                    */\r
+#define CCU8_GCSS_S2DSE_Pos                   9                                                       /*!< CCU8 GCSS: S2DSE Position               */\r
+#define CCU8_GCSS_S2DSE_Msk                   (0x01UL << CCU8_GCSS_S2DSE_Pos)                         /*!< CCU8 GCSS: S2DSE Mask                   */\r
+#define CCU8_GCSS_S2PSE_Pos                   10                                                      /*!< CCU8 GCSS: S2PSE Position               */\r
+#define CCU8_GCSS_S2PSE_Msk                   (0x01UL << CCU8_GCSS_S2PSE_Pos)                         /*!< CCU8 GCSS: S2PSE Mask                   */\r
+#define CCU8_GCSS_S3SE_Pos                    12                                                      /*!< CCU8 GCSS: S3SE Position                */\r
+#define CCU8_GCSS_S3SE_Msk                    (0x01UL << CCU8_GCSS_S3SE_Pos)                          /*!< CCU8 GCSS: S3SE Mask                    */\r
+#define CCU8_GCSS_S3DSE_Pos                   13                                                      /*!< CCU8 GCSS: S3DSE Position               */\r
+#define CCU8_GCSS_S3DSE_Msk                   (0x01UL << CCU8_GCSS_S3DSE_Pos)                         /*!< CCU8 GCSS: S3DSE Mask                   */\r
+#define CCU8_GCSS_S3PSE_Pos                   14                                                      /*!< CCU8 GCSS: S3PSE Position               */\r
+#define CCU8_GCSS_S3PSE_Msk                   (0x01UL << CCU8_GCSS_S3PSE_Pos)                         /*!< CCU8 GCSS: S3PSE Mask                   */\r
+#define CCU8_GCSS_S0ST1S_Pos                  16                                                      /*!< CCU8 GCSS: S0ST1S Position              */\r
+#define CCU8_GCSS_S0ST1S_Msk                  (0x01UL << CCU8_GCSS_S0ST1S_Pos)                        /*!< CCU8 GCSS: S0ST1S Mask                  */\r
+#define CCU8_GCSS_S1ST1S_Pos                  17                                                      /*!< CCU8 GCSS: S1ST1S Position              */\r
+#define CCU8_GCSS_S1ST1S_Msk                  (0x01UL << CCU8_GCSS_S1ST1S_Pos)                        /*!< CCU8 GCSS: S1ST1S Mask                  */\r
+#define CCU8_GCSS_S2ST1S_Pos                  18                                                      /*!< CCU8 GCSS: S2ST1S Position              */\r
+#define CCU8_GCSS_S2ST1S_Msk                  (0x01UL << CCU8_GCSS_S2ST1S_Pos)                        /*!< CCU8 GCSS: S2ST1S Mask                  */\r
+#define CCU8_GCSS_S3ST1S_Pos                  19                                                      /*!< CCU8 GCSS: S3ST1S Position              */\r
+#define CCU8_GCSS_S3ST1S_Msk                  (0x01UL << CCU8_GCSS_S3ST1S_Pos)                        /*!< CCU8 GCSS: S3ST1S Mask                  */\r
+#define CCU8_GCSS_S0ST2S_Pos                  20                                                      /*!< CCU8 GCSS: S0ST2S Position              */\r
+#define CCU8_GCSS_S0ST2S_Msk                  (0x01UL << CCU8_GCSS_S0ST2S_Pos)                        /*!< CCU8 GCSS: S0ST2S Mask                  */\r
+#define CCU8_GCSS_S1ST2S_Pos                  21                                                      /*!< CCU8 GCSS: S1ST2S Position              */\r
+#define CCU8_GCSS_S1ST2S_Msk                  (0x01UL << CCU8_GCSS_S1ST2S_Pos)                        /*!< CCU8 GCSS: S1ST2S Mask                  */\r
+#define CCU8_GCSS_S2ST2S_Pos                  22                                                      /*!< CCU8 GCSS: S2ST2S Position              */\r
+#define CCU8_GCSS_S2ST2S_Msk                  (0x01UL << CCU8_GCSS_S2ST2S_Pos)                        /*!< CCU8 GCSS: S2ST2S Mask                  */\r
+#define CCU8_GCSS_S3ST2S_Pos                  23                                                      /*!< CCU8 GCSS: S3ST2S Position              */\r
+#define CCU8_GCSS_S3ST2S_Msk                  (0x01UL << CCU8_GCSS_S3ST2S_Pos)                        /*!< CCU8 GCSS: S3ST2S Mask                  */\r
+\r
+/* ----------------------------------  CCU8_GCSC  --------------------------------- */\r
+#define CCU8_GCSC_S0SC_Pos                    0                                                       /*!< CCU8 GCSC: S0SC Position                */\r
+#define CCU8_GCSC_S0SC_Msk                    (0x01UL << CCU8_GCSC_S0SC_Pos)                          /*!< CCU8 GCSC: S0SC Mask                    */\r
+#define CCU8_GCSC_S0DSC_Pos                   1                                                       /*!< CCU8 GCSC: S0DSC Position               */\r
+#define CCU8_GCSC_S0DSC_Msk                   (0x01UL << CCU8_GCSC_S0DSC_Pos)                         /*!< CCU8 GCSC: S0DSC Mask                   */\r
+#define CCU8_GCSC_S0PSC_Pos                   2                                                       /*!< CCU8 GCSC: S0PSC Position               */\r
+#define CCU8_GCSC_S0PSC_Msk                   (0x01UL << CCU8_GCSC_S0PSC_Pos)                         /*!< CCU8 GCSC: S0PSC Mask                   */\r
+#define CCU8_GCSC_S1SC_Pos                    4                                                       /*!< CCU8 GCSC: S1SC Position                */\r
+#define CCU8_GCSC_S1SC_Msk                    (0x01UL << CCU8_GCSC_S1SC_Pos)                          /*!< CCU8 GCSC: S1SC Mask                    */\r
+#define CCU8_GCSC_S1DSC_Pos                   5                                                       /*!< CCU8 GCSC: S1DSC Position               */\r
+#define CCU8_GCSC_S1DSC_Msk                   (0x01UL << CCU8_GCSC_S1DSC_Pos)                         /*!< CCU8 GCSC: S1DSC Mask                   */\r
+#define CCU8_GCSC_S1PSC_Pos                   6                                                       /*!< CCU8 GCSC: S1PSC Position               */\r
+#define CCU8_GCSC_S1PSC_Msk                   (0x01UL << CCU8_GCSC_S1PSC_Pos)                         /*!< CCU8 GCSC: S1PSC Mask                   */\r
+#define CCU8_GCSC_S2SC_Pos                    8                                                       /*!< CCU8 GCSC: S2SC Position                */\r
+#define CCU8_GCSC_S2SC_Msk                    (0x01UL << CCU8_GCSC_S2SC_Pos)                          /*!< CCU8 GCSC: S2SC Mask                    */\r
+#define CCU8_GCSC_S2DSC_Pos                   9                                                       /*!< CCU8 GCSC: S2DSC Position               */\r
+#define CCU8_GCSC_S2DSC_Msk                   (0x01UL << CCU8_GCSC_S2DSC_Pos)                         /*!< CCU8 GCSC: S2DSC Mask                   */\r
+#define CCU8_GCSC_S2PSC_Pos                   10                                                      /*!< CCU8 GCSC: S2PSC Position               */\r
+#define CCU8_GCSC_S2PSC_Msk                   (0x01UL << CCU8_GCSC_S2PSC_Pos)                         /*!< CCU8 GCSC: S2PSC Mask                   */\r
+#define CCU8_GCSC_S3SC_Pos                    12                                                      /*!< CCU8 GCSC: S3SC Position                */\r
+#define CCU8_GCSC_S3SC_Msk                    (0x01UL << CCU8_GCSC_S3SC_Pos)                          /*!< CCU8 GCSC: S3SC Mask                    */\r
+#define CCU8_GCSC_S3DSC_Pos                   13                                                      /*!< CCU8 GCSC: S3DSC Position               */\r
+#define CCU8_GCSC_S3DSC_Msk                   (0x01UL << CCU8_GCSC_S3DSC_Pos)                         /*!< CCU8 GCSC: S3DSC Mask                   */\r
+#define CCU8_GCSC_S3PSC_Pos                   14                                                      /*!< CCU8 GCSC: S3PSC Position               */\r
+#define CCU8_GCSC_S3PSC_Msk                   (0x01UL << CCU8_GCSC_S3PSC_Pos)                         /*!< CCU8 GCSC: S3PSC Mask                   */\r
+#define CCU8_GCSC_S0ST1C_Pos                  16                                                      /*!< CCU8 GCSC: S0ST1C Position              */\r
+#define CCU8_GCSC_S0ST1C_Msk                  (0x01UL << CCU8_GCSC_S0ST1C_Pos)                        /*!< CCU8 GCSC: S0ST1C Mask                  */\r
+#define CCU8_GCSC_S1ST1C_Pos                  17                                                      /*!< CCU8 GCSC: S1ST1C Position              */\r
+#define CCU8_GCSC_S1ST1C_Msk                  (0x01UL << CCU8_GCSC_S1ST1C_Pos)                        /*!< CCU8 GCSC: S1ST1C Mask                  */\r
+#define CCU8_GCSC_S2ST1C_Pos                  18                                                      /*!< CCU8 GCSC: S2ST1C Position              */\r
+#define CCU8_GCSC_S2ST1C_Msk                  (0x01UL << CCU8_GCSC_S2ST1C_Pos)                        /*!< CCU8 GCSC: S2ST1C Mask                  */\r
+#define CCU8_GCSC_S3ST1C_Pos                  19                                                      /*!< CCU8 GCSC: S3ST1C Position              */\r
+#define CCU8_GCSC_S3ST1C_Msk                  (0x01UL << CCU8_GCSC_S3ST1C_Pos)                        /*!< CCU8 GCSC: S3ST1C Mask                  */\r
+#define CCU8_GCSC_S0ST2C_Pos                  20                                                      /*!< CCU8 GCSC: S0ST2C Position              */\r
+#define CCU8_GCSC_S0ST2C_Msk                  (0x01UL << CCU8_GCSC_S0ST2C_Pos)                        /*!< CCU8 GCSC: S0ST2C Mask                  */\r
+#define CCU8_GCSC_S1ST2C_Pos                  21                                                      /*!< CCU8 GCSC: S1ST2C Position              */\r
+#define CCU8_GCSC_S1ST2C_Msk                  (0x01UL << CCU8_GCSC_S1ST2C_Pos)                        /*!< CCU8 GCSC: S1ST2C Mask                  */\r
+#define CCU8_GCSC_S2ST2C_Pos                  22                                                      /*!< CCU8 GCSC: S2ST2C Position              */\r
+#define CCU8_GCSC_S2ST2C_Msk                  (0x01UL << CCU8_GCSC_S2ST2C_Pos)                        /*!< CCU8 GCSC: S2ST2C Mask                  */\r
+#define CCU8_GCSC_S3ST2C_Pos                  23                                                      /*!< CCU8 GCSC: S3ST2C Position              */\r
+#define CCU8_GCSC_S3ST2C_Msk                  (0x01UL << CCU8_GCSC_S3ST2C_Pos)                        /*!< CCU8 GCSC: S3ST2C Mask                  */\r
+\r
+/* ----------------------------------  CCU8_GCST  --------------------------------- */\r
+#define CCU8_GCST_S0SS_Pos                    0                                                       /*!< CCU8 GCST: S0SS Position                */\r
+#define CCU8_GCST_S0SS_Msk                    (0x01UL << CCU8_GCST_S0SS_Pos)                          /*!< CCU8 GCST: S0SS Mask                    */\r
+#define CCU8_GCST_S0DSS_Pos                   1                                                       /*!< CCU8 GCST: S0DSS Position               */\r
+#define CCU8_GCST_S0DSS_Msk                   (0x01UL << CCU8_GCST_S0DSS_Pos)                         /*!< CCU8 GCST: S0DSS Mask                   */\r
+#define CCU8_GCST_S0PSS_Pos                   2                                                       /*!< CCU8 GCST: S0PSS Position               */\r
+#define CCU8_GCST_S0PSS_Msk                   (0x01UL << CCU8_GCST_S0PSS_Pos)                         /*!< CCU8 GCST: S0PSS Mask                   */\r
+#define CCU8_GCST_S1SS_Pos                    4                                                       /*!< CCU8 GCST: S1SS Position                */\r
+#define CCU8_GCST_S1SS_Msk                    (0x01UL << CCU8_GCST_S1SS_Pos)                          /*!< CCU8 GCST: S1SS Mask                    */\r
+#define CCU8_GCST_S1DSS_Pos                   5                                                       /*!< CCU8 GCST: S1DSS Position               */\r
+#define CCU8_GCST_S1DSS_Msk                   (0x01UL << CCU8_GCST_S1DSS_Pos)                         /*!< CCU8 GCST: S1DSS Mask                   */\r
+#define CCU8_GCST_S1PSS_Pos                   6                                                       /*!< CCU8 GCST: S1PSS Position               */\r
+#define CCU8_GCST_S1PSS_Msk                   (0x01UL << CCU8_GCST_S1PSS_Pos)                         /*!< CCU8 GCST: S1PSS Mask                   */\r
+#define CCU8_GCST_S2SS_Pos                    8                                                       /*!< CCU8 GCST: S2SS Position                */\r
+#define CCU8_GCST_S2SS_Msk                    (0x01UL << CCU8_GCST_S2SS_Pos)                          /*!< CCU8 GCST: S2SS Mask                    */\r
+#define CCU8_GCST_S2DSS_Pos                   9                                                       /*!< CCU8 GCST: S2DSS Position               */\r
+#define CCU8_GCST_S2DSS_Msk                   (0x01UL << CCU8_GCST_S2DSS_Pos)                         /*!< CCU8 GCST: S2DSS Mask                   */\r
+#define CCU8_GCST_S2PSS_Pos                   10                                                      /*!< CCU8 GCST: S2PSS Position               */\r
+#define CCU8_GCST_S2PSS_Msk                   (0x01UL << CCU8_GCST_S2PSS_Pos)                         /*!< CCU8 GCST: S2PSS Mask                   */\r
+#define CCU8_GCST_S3SS_Pos                    12                                                      /*!< CCU8 GCST: S3SS Position                */\r
+#define CCU8_GCST_S3SS_Msk                    (0x01UL << CCU8_GCST_S3SS_Pos)                          /*!< CCU8 GCST: S3SS Mask                    */\r
+#define CCU8_GCST_S3DSS_Pos                   13                                                      /*!< CCU8 GCST: S3DSS Position               */\r
+#define CCU8_GCST_S3DSS_Msk                   (0x01UL << CCU8_GCST_S3DSS_Pos)                         /*!< CCU8 GCST: S3DSS Mask                   */\r
+#define CCU8_GCST_S3PSS_Pos                   14                                                      /*!< CCU8 GCST: S3PSS Position               */\r
+#define CCU8_GCST_S3PSS_Msk                   (0x01UL << CCU8_GCST_S3PSS_Pos)                         /*!< CCU8 GCST: S3PSS Mask                   */\r
+#define CCU8_GCST_CC80ST1_Pos                 16                                                      /*!< CCU8 GCST: CC80ST1 Position             */\r
+#define CCU8_GCST_CC80ST1_Msk                 (0x01UL << CCU8_GCST_CC80ST1_Pos)                       /*!< CCU8 GCST: CC80ST1 Mask                 */\r
+#define CCU8_GCST_CC81ST1_Pos                 17                                                      /*!< CCU8 GCST: CC81ST1 Position             */\r
+#define CCU8_GCST_CC81ST1_Msk                 (0x01UL << CCU8_GCST_CC81ST1_Pos)                       /*!< CCU8 GCST: CC81ST1 Mask                 */\r
+#define CCU8_GCST_CC82ST1_Pos                 18                                                      /*!< CCU8 GCST: CC82ST1 Position             */\r
+#define CCU8_GCST_CC82ST1_Msk                 (0x01UL << CCU8_GCST_CC82ST1_Pos)                       /*!< CCU8 GCST: CC82ST1 Mask                 */\r
+#define CCU8_GCST_CC83ST1_Pos                 19                                                      /*!< CCU8 GCST: CC83ST1 Position             */\r
+#define CCU8_GCST_CC83ST1_Msk                 (0x01UL << CCU8_GCST_CC83ST1_Pos)                       /*!< CCU8 GCST: CC83ST1 Mask                 */\r
+#define CCU8_GCST_CC80ST2_Pos                 20                                                      /*!< CCU8 GCST: CC80ST2 Position             */\r
+#define CCU8_GCST_CC80ST2_Msk                 (0x01UL << CCU8_GCST_CC80ST2_Pos)                       /*!< CCU8 GCST: CC80ST2 Mask                 */\r
+#define CCU8_GCST_CC81ST2_Pos                 21                                                      /*!< CCU8 GCST: CC81ST2 Position             */\r
+#define CCU8_GCST_CC81ST2_Msk                 (0x01UL << CCU8_GCST_CC81ST2_Pos)                       /*!< CCU8 GCST: CC81ST2 Mask                 */\r
+#define CCU8_GCST_CC82ST2_Pos                 22                                                      /*!< CCU8 GCST: CC82ST2 Position             */\r
+#define CCU8_GCST_CC82ST2_Msk                 (0x01UL << CCU8_GCST_CC82ST2_Pos)                       /*!< CCU8 GCST: CC82ST2 Mask                 */\r
+#define CCU8_GCST_CC83ST2_Pos                 23                                                      /*!< CCU8 GCST: CC83ST2 Position             */\r
+#define CCU8_GCST_CC83ST2_Msk                 (0x01UL << CCU8_GCST_CC83ST2_Pos)                       /*!< CCU8 GCST: CC83ST2 Mask                 */\r
+\r
+/* ---------------------------------  CCU8_GPCHK  --------------------------------- */\r
+#define CCU8_GPCHK_PASE_Pos                   0                                                       /*!< CCU8 GPCHK: PASE Position               */\r
+#define CCU8_GPCHK_PASE_Msk                   (0x01UL << CCU8_GPCHK_PASE_Pos)                         /*!< CCU8 GPCHK: PASE Mask                   */\r
+#define CCU8_GPCHK_PACS_Pos                   1                                                       /*!< CCU8 GPCHK: PACS Position               */\r
+#define CCU8_GPCHK_PACS_Msk                   (0x03UL << CCU8_GPCHK_PACS_Pos)                         /*!< CCU8 GPCHK: PACS Mask                   */\r
+#define CCU8_GPCHK_PISEL_Pos                  3                                                       /*!< CCU8 GPCHK: PISEL Position              */\r
+#define CCU8_GPCHK_PISEL_Msk                  (0x03UL << CCU8_GPCHK_PISEL_Pos)                        /*!< CCU8 GPCHK: PISEL Mask                  */\r
+#define CCU8_GPCHK_PCDS_Pos                   5                                                       /*!< CCU8 GPCHK: PCDS Position               */\r
+#define CCU8_GPCHK_PCDS_Msk                   (0x03UL << CCU8_GPCHK_PCDS_Pos)                         /*!< CCU8 GPCHK: PCDS Mask                   */\r
+#define CCU8_GPCHK_PCTS_Pos                   7                                                       /*!< CCU8 GPCHK: PCTS Position               */\r
+#define CCU8_GPCHK_PCTS_Msk                   (0x01UL << CCU8_GPCHK_PCTS_Pos)                         /*!< CCU8 GPCHK: PCTS Mask                   */\r
+#define CCU8_GPCHK_PCST_Pos                   15                                                      /*!< CCU8 GPCHK: PCST Position               */\r
+#define CCU8_GPCHK_PCST_Msk                   (0x01UL << CCU8_GPCHK_PCST_Pos)                         /*!< CCU8 GPCHK: PCST Mask                   */\r
+#define CCU8_GPCHK_PCSEL0_Pos                 16                                                      /*!< CCU8 GPCHK: PCSEL0 Position             */\r
+#define CCU8_GPCHK_PCSEL0_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL0_Pos)                       /*!< CCU8 GPCHK: PCSEL0 Mask                 */\r
+#define CCU8_GPCHK_PCSEL1_Pos                 20                                                      /*!< CCU8 GPCHK: PCSEL1 Position             */\r
+#define CCU8_GPCHK_PCSEL1_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL1_Pos)                       /*!< CCU8 GPCHK: PCSEL1 Mask                 */\r
+#define CCU8_GPCHK_PCSEL2_Pos                 24                                                      /*!< CCU8 GPCHK: PCSEL2 Position             */\r
+#define CCU8_GPCHK_PCSEL2_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL2_Pos)                       /*!< CCU8 GPCHK: PCSEL2 Mask                 */\r
+#define CCU8_GPCHK_PCSEL3_Pos                 28                                                      /*!< CCU8 GPCHK: PCSEL3 Position             */\r
+#define CCU8_GPCHK_PCSEL3_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL3_Pos)                       /*!< CCU8 GPCHK: PCSEL3 Mask                 */\r
+\r
+/* ----------------------------------  CCU8_ECRD  --------------------------------- */\r
+#define CCU8_ECRD_CAPV_Pos                    0                                                       /*!< CCU8 ECRD: CAPV Position                */\r
+#define CCU8_ECRD_CAPV_Msk                    (0x0000ffffUL << CCU8_ECRD_CAPV_Pos)                    /*!< CCU8 ECRD: CAPV Mask                    */\r
+#define CCU8_ECRD_FPCV_Pos                    16                                                      /*!< CCU8 ECRD: FPCV Position                */\r
+#define CCU8_ECRD_FPCV_Msk                    (0x0fUL << CCU8_ECRD_FPCV_Pos)                          /*!< CCU8 ECRD: FPCV Mask                    */\r
+#define CCU8_ECRD_SPTR_Pos                    20                                                      /*!< CCU8 ECRD: SPTR Position                */\r
+#define CCU8_ECRD_SPTR_Msk                    (0x03UL << CCU8_ECRD_SPTR_Pos)                          /*!< CCU8 ECRD: SPTR Mask                    */\r
+#define CCU8_ECRD_VPTR_Pos                    22                                                      /*!< CCU8 ECRD: VPTR Position                */\r
+#define CCU8_ECRD_VPTR_Msk                    (0x03UL << CCU8_ECRD_VPTR_Pos)                          /*!< CCU8 ECRD: VPTR Mask                    */\r
+#define CCU8_ECRD_FFL_Pos                     24                                                      /*!< CCU8 ECRD: FFL Position                 */\r
+#define CCU8_ECRD_FFL_Msk                     (0x01UL << CCU8_ECRD_FFL_Pos)                           /*!< CCU8 ECRD: FFL Mask                     */\r
+\r
+/* ----------------------------------  CCU8_MIDR  --------------------------------- */\r
+#define CCU8_MIDR_MODR_Pos                    0                                                       /*!< CCU8 MIDR: MODR Position                */\r
+#define CCU8_MIDR_MODR_Msk                    (0x000000ffUL << CCU8_MIDR_MODR_Pos)                    /*!< CCU8 MIDR: MODR Mask                    */\r
+#define CCU8_MIDR_MODT_Pos                    8                                                       /*!< CCU8 MIDR: MODT Position                */\r
+#define CCU8_MIDR_MODT_Msk                    (0x000000ffUL << CCU8_MIDR_MODT_Pos)                    /*!< CCU8 MIDR: MODT Mask                    */\r
+#define CCU8_MIDR_MODN_Pos                    16                                                      /*!< CCU8 MIDR: MODN Position                */\r
+#define CCU8_MIDR_MODN_Msk                    (0x0000ffffUL << CCU8_MIDR_MODN_Pos)                    /*!< CCU8 MIDR: MODN Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        Group 'CCU8_CC8' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CCU8_CC8_INS  -------------------------------- */\r
+#define CCU8_CC8_INS_EV0IS_Pos                0                                                       /*!< CCU8_CC8 INS: EV0IS Position            */\r
+#define CCU8_CC8_INS_EV0IS_Msk                (0x0fUL << CCU8_CC8_INS_EV0IS_Pos)                      /*!< CCU8_CC8 INS: EV0IS Mask                */\r
+#define CCU8_CC8_INS_EV1IS_Pos                4                                                       /*!< CCU8_CC8 INS: EV1IS Position            */\r
+#define CCU8_CC8_INS_EV1IS_Msk                (0x0fUL << CCU8_CC8_INS_EV1IS_Pos)                      /*!< CCU8_CC8 INS: EV1IS Mask                */\r
+#define CCU8_CC8_INS_EV2IS_Pos                8                                                       /*!< CCU8_CC8 INS: EV2IS Position            */\r
+#define CCU8_CC8_INS_EV2IS_Msk                (0x0fUL << CCU8_CC8_INS_EV2IS_Pos)                      /*!< CCU8_CC8 INS: EV2IS Mask                */\r
+#define CCU8_CC8_INS_EV0EM_Pos                16                                                      /*!< CCU8_CC8 INS: EV0EM Position            */\r
+#define CCU8_CC8_INS_EV0EM_Msk                (0x03UL << CCU8_CC8_INS_EV0EM_Pos)                      /*!< CCU8_CC8 INS: EV0EM Mask                */\r
+#define CCU8_CC8_INS_EV1EM_Pos                18                                                      /*!< CCU8_CC8 INS: EV1EM Position            */\r
+#define CCU8_CC8_INS_EV1EM_Msk                (0x03UL << CCU8_CC8_INS_EV1EM_Pos)                      /*!< CCU8_CC8 INS: EV1EM Mask                */\r
+#define CCU8_CC8_INS_EV2EM_Pos                20                                                      /*!< CCU8_CC8 INS: EV2EM Position            */\r
+#define CCU8_CC8_INS_EV2EM_Msk                (0x03UL << CCU8_CC8_INS_EV2EM_Pos)                      /*!< CCU8_CC8 INS: EV2EM Mask                */\r
+#define CCU8_CC8_INS_EV0LM_Pos                22                                                      /*!< CCU8_CC8 INS: EV0LM Position            */\r
+#define CCU8_CC8_INS_EV0LM_Msk                (0x01UL << CCU8_CC8_INS_EV0LM_Pos)                      /*!< CCU8_CC8 INS: EV0LM Mask                */\r
+#define CCU8_CC8_INS_EV1LM_Pos                23                                                      /*!< CCU8_CC8 INS: EV1LM Position            */\r
+#define CCU8_CC8_INS_EV1LM_Msk                (0x01UL << CCU8_CC8_INS_EV1LM_Pos)                      /*!< CCU8_CC8 INS: EV1LM Mask                */\r
+#define CCU8_CC8_INS_EV2LM_Pos                24                                                      /*!< CCU8_CC8 INS: EV2LM Position            */\r
+#define CCU8_CC8_INS_EV2LM_Msk                (0x01UL << CCU8_CC8_INS_EV2LM_Pos)                      /*!< CCU8_CC8 INS: EV2LM Mask                */\r
+#define CCU8_CC8_INS_LPF0M_Pos                25                                                      /*!< CCU8_CC8 INS: LPF0M Position            */\r
+#define CCU8_CC8_INS_LPF0M_Msk                (0x03UL << CCU8_CC8_INS_LPF0M_Pos)                      /*!< CCU8_CC8 INS: LPF0M Mask                */\r
+#define CCU8_CC8_INS_LPF1M_Pos                27                                                      /*!< CCU8_CC8 INS: LPF1M Position            */\r
+#define CCU8_CC8_INS_LPF1M_Msk                (0x03UL << CCU8_CC8_INS_LPF1M_Pos)                      /*!< CCU8_CC8 INS: LPF1M Mask                */\r
+#define CCU8_CC8_INS_LPF2M_Pos                29                                                      /*!< CCU8_CC8 INS: LPF2M Position            */\r
+#define CCU8_CC8_INS_LPF2M_Msk                (0x03UL << CCU8_CC8_INS_LPF2M_Pos)                      /*!< CCU8_CC8 INS: LPF2M Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_CMC  -------------------------------- */\r
+#define CCU8_CC8_CMC_STRTS_Pos                0                                                       /*!< CCU8_CC8 CMC: STRTS Position            */\r
+#define CCU8_CC8_CMC_STRTS_Msk                (0x03UL << CCU8_CC8_CMC_STRTS_Pos)                      /*!< CCU8_CC8 CMC: STRTS Mask                */\r
+#define CCU8_CC8_CMC_ENDS_Pos                 2                                                       /*!< CCU8_CC8 CMC: ENDS Position             */\r
+#define CCU8_CC8_CMC_ENDS_Msk                 (0x03UL << CCU8_CC8_CMC_ENDS_Pos)                       /*!< CCU8_CC8 CMC: ENDS Mask                 */\r
+#define CCU8_CC8_CMC_CAP0S_Pos                4                                                       /*!< CCU8_CC8 CMC: CAP0S Position            */\r
+#define CCU8_CC8_CMC_CAP0S_Msk                (0x03UL << CCU8_CC8_CMC_CAP0S_Pos)                      /*!< CCU8_CC8 CMC: CAP0S Mask                */\r
+#define CCU8_CC8_CMC_CAP1S_Pos                6                                                       /*!< CCU8_CC8 CMC: CAP1S Position            */\r
+#define CCU8_CC8_CMC_CAP1S_Msk                (0x03UL << CCU8_CC8_CMC_CAP1S_Pos)                      /*!< CCU8_CC8 CMC: CAP1S Mask                */\r
+#define CCU8_CC8_CMC_GATES_Pos                8                                                       /*!< CCU8_CC8 CMC: GATES Position            */\r
+#define CCU8_CC8_CMC_GATES_Msk                (0x03UL << CCU8_CC8_CMC_GATES_Pos)                      /*!< CCU8_CC8 CMC: GATES Mask                */\r
+#define CCU8_CC8_CMC_UDS_Pos                  10                                                      /*!< CCU8_CC8 CMC: UDS Position              */\r
+#define CCU8_CC8_CMC_UDS_Msk                  (0x03UL << CCU8_CC8_CMC_UDS_Pos)                        /*!< CCU8_CC8 CMC: UDS Mask                  */\r
+#define CCU8_CC8_CMC_LDS_Pos                  12                                                      /*!< CCU8_CC8 CMC: LDS Position              */\r
+#define CCU8_CC8_CMC_LDS_Msk                  (0x03UL << CCU8_CC8_CMC_LDS_Pos)                        /*!< CCU8_CC8 CMC: LDS Mask                  */\r
+#define CCU8_CC8_CMC_CNTS_Pos                 14                                                      /*!< CCU8_CC8 CMC: CNTS Position             */\r
+#define CCU8_CC8_CMC_CNTS_Msk                 (0x03UL << CCU8_CC8_CMC_CNTS_Pos)                       /*!< CCU8_CC8 CMC: CNTS Mask                 */\r
+#define CCU8_CC8_CMC_OFS_Pos                  16                                                      /*!< CCU8_CC8 CMC: OFS Position              */\r
+#define CCU8_CC8_CMC_OFS_Msk                  (0x01UL << CCU8_CC8_CMC_OFS_Pos)                        /*!< CCU8_CC8 CMC: OFS Mask                  */\r
+#define CCU8_CC8_CMC_TS_Pos                   17                                                      /*!< CCU8_CC8 CMC: TS Position               */\r
+#define CCU8_CC8_CMC_TS_Msk                   (0x01UL << CCU8_CC8_CMC_TS_Pos)                         /*!< CCU8_CC8 CMC: TS Mask                   */\r
+#define CCU8_CC8_CMC_MOS_Pos                  18                                                      /*!< CCU8_CC8 CMC: MOS Position              */\r
+#define CCU8_CC8_CMC_MOS_Msk                  (0x03UL << CCU8_CC8_CMC_MOS_Pos)                        /*!< CCU8_CC8 CMC: MOS Mask                  */\r
+#define CCU8_CC8_CMC_TCE_Pos                  20                                                      /*!< CCU8_CC8 CMC: TCE Position              */\r
+#define CCU8_CC8_CMC_TCE_Msk                  (0x01UL << CCU8_CC8_CMC_TCE_Pos)                        /*!< CCU8_CC8 CMC: TCE Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_TCST  ------------------------------- */\r
+#define CCU8_CC8_TCST_TRB_Pos                 0                                                       /*!< CCU8_CC8 TCST: TRB Position             */\r
+#define CCU8_CC8_TCST_TRB_Msk                 (0x01UL << CCU8_CC8_TCST_TRB_Pos)                       /*!< CCU8_CC8 TCST: TRB Mask                 */\r
+#define CCU8_CC8_TCST_CDIR_Pos                1                                                       /*!< CCU8_CC8 TCST: CDIR Position            */\r
+#define CCU8_CC8_TCST_CDIR_Msk                (0x01UL << CCU8_CC8_TCST_CDIR_Pos)                      /*!< CCU8_CC8 TCST: CDIR Mask                */\r
+#define CCU8_CC8_TCST_DTR1_Pos                3                                                       /*!< CCU8_CC8 TCST: DTR1 Position            */\r
+#define CCU8_CC8_TCST_DTR1_Msk                (0x01UL << CCU8_CC8_TCST_DTR1_Pos)                      /*!< CCU8_CC8 TCST: DTR1 Mask                */\r
+#define CCU8_CC8_TCST_DTR2_Pos                4                                                       /*!< CCU8_CC8 TCST: DTR2 Position            */\r
+#define CCU8_CC8_TCST_DTR2_Msk                (0x01UL << CCU8_CC8_TCST_DTR2_Pos)                      /*!< CCU8_CC8 TCST: DTR2 Mask                */\r
+\r
+/* -------------------------------  CCU8_CC8_TCSET  ------------------------------- */\r
+#define CCU8_CC8_TCSET_TRBS_Pos               0                                                       /*!< CCU8_CC8 TCSET: TRBS Position           */\r
+#define CCU8_CC8_TCSET_TRBS_Msk               (0x01UL << CCU8_CC8_TCSET_TRBS_Pos)                     /*!< CCU8_CC8 TCSET: TRBS Mask               */\r
+\r
+/* -------------------------------  CCU8_CC8_TCCLR  ------------------------------- */\r
+#define CCU8_CC8_TCCLR_TRBC_Pos               0                                                       /*!< CCU8_CC8 TCCLR: TRBC Position           */\r
+#define CCU8_CC8_TCCLR_TRBC_Msk               (0x01UL << CCU8_CC8_TCCLR_TRBC_Pos)                     /*!< CCU8_CC8 TCCLR: TRBC Mask               */\r
+#define CCU8_CC8_TCCLR_TCC_Pos                1                                                       /*!< CCU8_CC8 TCCLR: TCC Position            */\r
+#define CCU8_CC8_TCCLR_TCC_Msk                (0x01UL << CCU8_CC8_TCCLR_TCC_Pos)                      /*!< CCU8_CC8 TCCLR: TCC Mask                */\r
+#define CCU8_CC8_TCCLR_DITC_Pos               2                                                       /*!< CCU8_CC8 TCCLR: DITC Position           */\r
+#define CCU8_CC8_TCCLR_DITC_Msk               (0x01UL << CCU8_CC8_TCCLR_DITC_Pos)                     /*!< CCU8_CC8 TCCLR: DITC Mask               */\r
+#define CCU8_CC8_TCCLR_DTC1C_Pos              3                                                       /*!< CCU8_CC8 TCCLR: DTC1C Position          */\r
+#define CCU8_CC8_TCCLR_DTC1C_Msk              (0x01UL << CCU8_CC8_TCCLR_DTC1C_Pos)                    /*!< CCU8_CC8 TCCLR: DTC1C Mask              */\r
+#define CCU8_CC8_TCCLR_DTC2C_Pos              4                                                       /*!< CCU8_CC8 TCCLR: DTC2C Position          */\r
+#define CCU8_CC8_TCCLR_DTC2C_Msk              (0x01UL << CCU8_CC8_TCCLR_DTC2C_Pos)                    /*!< CCU8_CC8 TCCLR: DTC2C Mask              */\r
+\r
+/* ---------------------------------  CCU8_CC8_TC  -------------------------------- */\r
+#define CCU8_CC8_TC_TCM_Pos                   0                                                       /*!< CCU8_CC8 TC: TCM Position               */\r
+#define CCU8_CC8_TC_TCM_Msk                   (0x01UL << CCU8_CC8_TC_TCM_Pos)                         /*!< CCU8_CC8 TC: TCM Mask                   */\r
+#define CCU8_CC8_TC_TSSM_Pos                  1                                                       /*!< CCU8_CC8 TC: TSSM Position              */\r
+#define CCU8_CC8_TC_TSSM_Msk                  (0x01UL << CCU8_CC8_TC_TSSM_Pos)                        /*!< CCU8_CC8 TC: TSSM Mask                  */\r
+#define CCU8_CC8_TC_CLST_Pos                  2                                                       /*!< CCU8_CC8 TC: CLST Position              */\r
+#define CCU8_CC8_TC_CLST_Msk                  (0x01UL << CCU8_CC8_TC_CLST_Pos)                        /*!< CCU8_CC8 TC: CLST Mask                  */\r
+#define CCU8_CC8_TC_CMOD_Pos                  3                                                       /*!< CCU8_CC8 TC: CMOD Position              */\r
+#define CCU8_CC8_TC_CMOD_Msk                  (0x01UL << CCU8_CC8_TC_CMOD_Pos)                        /*!< CCU8_CC8 TC: CMOD Mask                  */\r
+#define CCU8_CC8_TC_ECM_Pos                   4                                                       /*!< CCU8_CC8 TC: ECM Position               */\r
+#define CCU8_CC8_TC_ECM_Msk                   (0x01UL << CCU8_CC8_TC_ECM_Pos)                         /*!< CCU8_CC8 TC: ECM Mask                   */\r
+#define CCU8_CC8_TC_CAPC_Pos                  5                                                       /*!< CCU8_CC8 TC: CAPC Position              */\r
+#define CCU8_CC8_TC_CAPC_Msk                  (0x03UL << CCU8_CC8_TC_CAPC_Pos)                        /*!< CCU8_CC8 TC: CAPC Mask                  */\r
+#define CCU8_CC8_TC_TLS_Pos                   7                                                       /*!< CCU8_CC8 TC: TLS Position               */\r
+#define CCU8_CC8_TC_TLS_Msk                   (0x01UL << CCU8_CC8_TC_TLS_Pos)                         /*!< CCU8_CC8 TC: TLS Mask                   */\r
+#define CCU8_CC8_TC_ENDM_Pos                  8                                                       /*!< CCU8_CC8 TC: ENDM Position              */\r
+#define CCU8_CC8_TC_ENDM_Msk                  (0x03UL << CCU8_CC8_TC_ENDM_Pos)                        /*!< CCU8_CC8 TC: ENDM Mask                  */\r
+#define CCU8_CC8_TC_STRM_Pos                  10                                                      /*!< CCU8_CC8 TC: STRM Position              */\r
+#define CCU8_CC8_TC_STRM_Msk                  (0x01UL << CCU8_CC8_TC_STRM_Pos)                        /*!< CCU8_CC8 TC: STRM Mask                  */\r
+#define CCU8_CC8_TC_SCE_Pos                   11                                                      /*!< CCU8_CC8 TC: SCE Position               */\r
+#define CCU8_CC8_TC_SCE_Msk                   (0x01UL << CCU8_CC8_TC_SCE_Pos)                         /*!< CCU8_CC8 TC: SCE Mask                   */\r
+#define CCU8_CC8_TC_CCS_Pos                   12                                                      /*!< CCU8_CC8 TC: CCS Position               */\r
+#define CCU8_CC8_TC_CCS_Msk                   (0x01UL << CCU8_CC8_TC_CCS_Pos)                         /*!< CCU8_CC8 TC: CCS Mask                   */\r
+#define CCU8_CC8_TC_DITHE_Pos                 13                                                      /*!< CCU8_CC8 TC: DITHE Position             */\r
+#define CCU8_CC8_TC_DITHE_Msk                 (0x03UL << CCU8_CC8_TC_DITHE_Pos)                       /*!< CCU8_CC8 TC: DITHE Mask                 */\r
+#define CCU8_CC8_TC_DIM_Pos                   15                                                      /*!< CCU8_CC8 TC: DIM Position               */\r
+#define CCU8_CC8_TC_DIM_Msk                   (0x01UL << CCU8_CC8_TC_DIM_Pos)                         /*!< CCU8_CC8 TC: DIM Mask                   */\r
+#define CCU8_CC8_TC_FPE_Pos                   16                                                      /*!< CCU8_CC8 TC: FPE Position               */\r
+#define CCU8_CC8_TC_FPE_Msk                   (0x01UL << CCU8_CC8_TC_FPE_Pos)                         /*!< CCU8_CC8 TC: FPE Mask                   */\r
+#define CCU8_CC8_TC_TRAPE0_Pos                17                                                      /*!< CCU8_CC8 TC: TRAPE0 Position            */\r
+#define CCU8_CC8_TC_TRAPE0_Msk                (0x01UL << CCU8_CC8_TC_TRAPE0_Pos)                      /*!< CCU8_CC8 TC: TRAPE0 Mask                */\r
+#define CCU8_CC8_TC_TRAPE1_Pos                18                                                      /*!< CCU8_CC8 TC: TRAPE1 Position            */\r
+#define CCU8_CC8_TC_TRAPE1_Msk                (0x01UL << CCU8_CC8_TC_TRAPE1_Pos)                      /*!< CCU8_CC8 TC: TRAPE1 Mask                */\r
+#define CCU8_CC8_TC_TRAPE2_Pos                19                                                      /*!< CCU8_CC8 TC: TRAPE2 Position            */\r
+#define CCU8_CC8_TC_TRAPE2_Msk                (0x01UL << CCU8_CC8_TC_TRAPE2_Pos)                      /*!< CCU8_CC8 TC: TRAPE2 Mask                */\r
+#define CCU8_CC8_TC_TRAPE3_Pos                20                                                      /*!< CCU8_CC8 TC: TRAPE3 Position            */\r
+#define CCU8_CC8_TC_TRAPE3_Msk                (0x01UL << CCU8_CC8_TC_TRAPE3_Pos)                      /*!< CCU8_CC8 TC: TRAPE3 Mask                */\r
+#define CCU8_CC8_TC_TRPSE_Pos                 21                                                      /*!< CCU8_CC8 TC: TRPSE Position             */\r
+#define CCU8_CC8_TC_TRPSE_Msk                 (0x01UL << CCU8_CC8_TC_TRPSE_Pos)                       /*!< CCU8_CC8 TC: TRPSE Mask                 */\r
+#define CCU8_CC8_TC_TRPSW_Pos                 22                                                      /*!< CCU8_CC8 TC: TRPSW Position             */\r
+#define CCU8_CC8_TC_TRPSW_Msk                 (0x01UL << CCU8_CC8_TC_TRPSW_Pos)                       /*!< CCU8_CC8 TC: TRPSW Mask                 */\r
+#define CCU8_CC8_TC_EMS_Pos                   23                                                      /*!< CCU8_CC8 TC: EMS Position               */\r
+#define CCU8_CC8_TC_EMS_Msk                   (0x01UL << CCU8_CC8_TC_EMS_Pos)                         /*!< CCU8_CC8 TC: EMS Mask                   */\r
+#define CCU8_CC8_TC_EMT_Pos                   24                                                      /*!< CCU8_CC8 TC: EMT Position               */\r
+#define CCU8_CC8_TC_EMT_Msk                   (0x01UL << CCU8_CC8_TC_EMT_Pos)                         /*!< CCU8_CC8 TC: EMT Mask                   */\r
+#define CCU8_CC8_TC_MCME1_Pos                 25                                                      /*!< CCU8_CC8 TC: MCME1 Position             */\r
+#define CCU8_CC8_TC_MCME1_Msk                 (0x01UL << CCU8_CC8_TC_MCME1_Pos)                       /*!< CCU8_CC8 TC: MCME1 Mask                 */\r
+#define CCU8_CC8_TC_MCME2_Pos                 26                                                      /*!< CCU8_CC8 TC: MCME2 Position             */\r
+#define CCU8_CC8_TC_MCME2_Msk                 (0x01UL << CCU8_CC8_TC_MCME2_Pos)                       /*!< CCU8_CC8 TC: MCME2 Mask                 */\r
+#define CCU8_CC8_TC_EME_Pos                   27                                                      /*!< CCU8_CC8 TC: EME Position               */\r
+#define CCU8_CC8_TC_EME_Msk                   (0x03UL << CCU8_CC8_TC_EME_Pos)                         /*!< CCU8_CC8 TC: EME Mask                   */\r
+#define CCU8_CC8_TC_STOS_Pos                  29                                                      /*!< CCU8_CC8 TC: STOS Position              */\r
+#define CCU8_CC8_TC_STOS_Msk                  (0x03UL << CCU8_CC8_TC_STOS_Pos)                        /*!< CCU8_CC8 TC: STOS Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_PSL  -------------------------------- */\r
+#define CCU8_CC8_PSL_PSL11_Pos                0                                                       /*!< CCU8_CC8 PSL: PSL11 Position            */\r
+#define CCU8_CC8_PSL_PSL11_Msk                (0x01UL << CCU8_CC8_PSL_PSL11_Pos)                      /*!< CCU8_CC8 PSL: PSL11 Mask                */\r
+#define CCU8_CC8_PSL_PSL12_Pos                1                                                       /*!< CCU8_CC8 PSL: PSL12 Position            */\r
+#define CCU8_CC8_PSL_PSL12_Msk                (0x01UL << CCU8_CC8_PSL_PSL12_Pos)                      /*!< CCU8_CC8 PSL: PSL12 Mask                */\r
+#define CCU8_CC8_PSL_PSL21_Pos                2                                                       /*!< CCU8_CC8 PSL: PSL21 Position            */\r
+#define CCU8_CC8_PSL_PSL21_Msk                (0x01UL << CCU8_CC8_PSL_PSL21_Pos)                      /*!< CCU8_CC8 PSL: PSL21 Mask                */\r
+#define CCU8_CC8_PSL_PSL22_Pos                3                                                       /*!< CCU8_CC8 PSL: PSL22 Position            */\r
+#define CCU8_CC8_PSL_PSL22_Msk                (0x01UL << CCU8_CC8_PSL_PSL22_Pos)                      /*!< CCU8_CC8 PSL: PSL22 Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_DIT  -------------------------------- */\r
+#define CCU8_CC8_DIT_DCV_Pos                  0                                                       /*!< CCU8_CC8 DIT: DCV Position              */\r
+#define CCU8_CC8_DIT_DCV_Msk                  (0x0fUL << CCU8_CC8_DIT_DCV_Pos)                        /*!< CCU8_CC8 DIT: DCV Mask                  */\r
+#define CCU8_CC8_DIT_DCNT_Pos                 8                                                       /*!< CCU8_CC8 DIT: DCNT Position             */\r
+#define CCU8_CC8_DIT_DCNT_Msk                 (0x0fUL << CCU8_CC8_DIT_DCNT_Pos)                       /*!< CCU8_CC8 DIT: DCNT Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_DITS  ------------------------------- */\r
+#define CCU8_CC8_DITS_DCVS_Pos                0                                                       /*!< CCU8_CC8 DITS: DCVS Position            */\r
+#define CCU8_CC8_DITS_DCVS_Msk                (0x0fUL << CCU8_CC8_DITS_DCVS_Pos)                      /*!< CCU8_CC8 DITS: DCVS Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_PSC  -------------------------------- */\r
+#define CCU8_CC8_PSC_PSIV_Pos                 0                                                       /*!< CCU8_CC8 PSC: PSIV Position             */\r
+#define CCU8_CC8_PSC_PSIV_Msk                 (0x0fUL << CCU8_CC8_PSC_PSIV_Pos)                       /*!< CCU8_CC8 PSC: PSIV Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_FPC  -------------------------------- */\r
+#define CCU8_CC8_FPC_PCMP_Pos                 0                                                       /*!< CCU8_CC8 FPC: PCMP Position             */\r
+#define CCU8_CC8_FPC_PCMP_Msk                 (0x0fUL << CCU8_CC8_FPC_PCMP_Pos)                       /*!< CCU8_CC8 FPC: PCMP Mask                 */\r
+#define CCU8_CC8_FPC_PVAL_Pos                 8                                                       /*!< CCU8_CC8 FPC: PVAL Position             */\r
+#define CCU8_CC8_FPC_PVAL_Msk                 (0x0fUL << CCU8_CC8_FPC_PVAL_Pos)                       /*!< CCU8_CC8 FPC: PVAL Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_FPCS  ------------------------------- */\r
+#define CCU8_CC8_FPCS_PCMP_Pos                0                                                       /*!< CCU8_CC8 FPCS: PCMP Position            */\r
+#define CCU8_CC8_FPCS_PCMP_Msk                (0x0fUL << CCU8_CC8_FPCS_PCMP_Pos)                      /*!< CCU8_CC8 FPCS: PCMP Mask                */\r
+\r
+/* ---------------------------------  CCU8_CC8_PR  -------------------------------- */\r
+#define CCU8_CC8_PR_PR_Pos                    0                                                       /*!< CCU8_CC8 PR: PR Position                */\r
+#define CCU8_CC8_PR_PR_Msk                    (0x0000ffffUL << CCU8_CC8_PR_PR_Pos)                    /*!< CCU8_CC8 PR: PR Mask                    */\r
+\r
+/* --------------------------------  CCU8_CC8_PRS  -------------------------------- */\r
+#define CCU8_CC8_PRS_PRS_Pos                  0                                                       /*!< CCU8_CC8 PRS: PRS Position              */\r
+#define CCU8_CC8_PRS_PRS_Msk                  (0x0000ffffUL << CCU8_CC8_PRS_PRS_Pos)                  /*!< CCU8_CC8 PRS: PRS Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_CR1  -------------------------------- */\r
+#define CCU8_CC8_CR1_CR1_Pos                  0                                                       /*!< CCU8_CC8 CR1: CR1 Position              */\r
+#define CCU8_CC8_CR1_CR1_Msk                  (0x0000ffffUL << CCU8_CC8_CR1_CR1_Pos)                  /*!< CCU8_CC8 CR1: CR1 Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_CR1S  ------------------------------- */\r
+#define CCU8_CC8_CR1S_CR1S_Pos                0                                                       /*!< CCU8_CC8 CR1S: CR1S Position            */\r
+#define CCU8_CC8_CR1S_CR1S_Msk                (0x0000ffffUL << CCU8_CC8_CR1S_CR1S_Pos)                /*!< CCU8_CC8 CR1S: CR1S Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_CR2  -------------------------------- */\r
+#define CCU8_CC8_CR2_CR2_Pos                  0                                                       /*!< CCU8_CC8 CR2: CR2 Position              */\r
+#define CCU8_CC8_CR2_CR2_Msk                  (0x0000ffffUL << CCU8_CC8_CR2_CR2_Pos)                  /*!< CCU8_CC8 CR2: CR2 Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_CR2S  ------------------------------- */\r
+#define CCU8_CC8_CR2S_CR2S_Pos                0                                                       /*!< CCU8_CC8 CR2S: CR2S Position            */\r
+#define CCU8_CC8_CR2S_CR2S_Msk                (0x0000ffffUL << CCU8_CC8_CR2S_CR2S_Pos)                /*!< CCU8_CC8 CR2S: CR2S Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_CHC  -------------------------------- */\r
+#define CCU8_CC8_CHC_ASE_Pos                  0                                                       /*!< CCU8_CC8 CHC: ASE Position              */\r
+#define CCU8_CC8_CHC_ASE_Msk                  (0x01UL << CCU8_CC8_CHC_ASE_Pos)                        /*!< CCU8_CC8 CHC: ASE Mask                  */\r
+#define CCU8_CC8_CHC_OCS1_Pos                 1                                                       /*!< CCU8_CC8 CHC: OCS1 Position             */\r
+#define CCU8_CC8_CHC_OCS1_Msk                 (0x01UL << CCU8_CC8_CHC_OCS1_Pos)                       /*!< CCU8_CC8 CHC: OCS1 Mask                 */\r
+#define CCU8_CC8_CHC_OCS2_Pos                 2                                                       /*!< CCU8_CC8 CHC: OCS2 Position             */\r
+#define CCU8_CC8_CHC_OCS2_Msk                 (0x01UL << CCU8_CC8_CHC_OCS2_Pos)                       /*!< CCU8_CC8 CHC: OCS2 Mask                 */\r
+#define CCU8_CC8_CHC_OCS3_Pos                 3                                                       /*!< CCU8_CC8 CHC: OCS3 Position             */\r
+#define CCU8_CC8_CHC_OCS3_Msk                 (0x01UL << CCU8_CC8_CHC_OCS3_Pos)                       /*!< CCU8_CC8 CHC: OCS3 Mask                 */\r
+#define CCU8_CC8_CHC_OCS4_Pos                 4                                                       /*!< CCU8_CC8 CHC: OCS4 Position             */\r
+#define CCU8_CC8_CHC_OCS4_Msk                 (0x01UL << CCU8_CC8_CHC_OCS4_Pos)                       /*!< CCU8_CC8 CHC: OCS4 Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_DTC  -------------------------------- */\r
+#define CCU8_CC8_DTC_DTE1_Pos                 0                                                       /*!< CCU8_CC8 DTC: DTE1 Position             */\r
+#define CCU8_CC8_DTC_DTE1_Msk                 (0x01UL << CCU8_CC8_DTC_DTE1_Pos)                       /*!< CCU8_CC8 DTC: DTE1 Mask                 */\r
+#define CCU8_CC8_DTC_DTE2_Pos                 1                                                       /*!< CCU8_CC8 DTC: DTE2 Position             */\r
+#define CCU8_CC8_DTC_DTE2_Msk                 (0x01UL << CCU8_CC8_DTC_DTE2_Pos)                       /*!< CCU8_CC8 DTC: DTE2 Mask                 */\r
+#define CCU8_CC8_DTC_DCEN1_Pos                2                                                       /*!< CCU8_CC8 DTC: DCEN1 Position            */\r
+#define CCU8_CC8_DTC_DCEN1_Msk                (0x01UL << CCU8_CC8_DTC_DCEN1_Pos)                      /*!< CCU8_CC8 DTC: DCEN1 Mask                */\r
+#define CCU8_CC8_DTC_DCEN2_Pos                3                                                       /*!< CCU8_CC8 DTC: DCEN2 Position            */\r
+#define CCU8_CC8_DTC_DCEN2_Msk                (0x01UL << CCU8_CC8_DTC_DCEN2_Pos)                      /*!< CCU8_CC8 DTC: DCEN2 Mask                */\r
+#define CCU8_CC8_DTC_DCEN3_Pos                4                                                       /*!< CCU8_CC8 DTC: DCEN3 Position            */\r
+#define CCU8_CC8_DTC_DCEN3_Msk                (0x01UL << CCU8_CC8_DTC_DCEN3_Pos)                      /*!< CCU8_CC8 DTC: DCEN3 Mask                */\r
+#define CCU8_CC8_DTC_DCEN4_Pos                5                                                       /*!< CCU8_CC8 DTC: DCEN4 Position            */\r
+#define CCU8_CC8_DTC_DCEN4_Msk                (0x01UL << CCU8_CC8_DTC_DCEN4_Pos)                      /*!< CCU8_CC8 DTC: DCEN4 Mask                */\r
+#define CCU8_CC8_DTC_DTCC_Pos                 6                                                       /*!< CCU8_CC8 DTC: DTCC Position             */\r
+#define CCU8_CC8_DTC_DTCC_Msk                 (0x03UL << CCU8_CC8_DTC_DTCC_Pos)                       /*!< CCU8_CC8 DTC: DTCC Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_DC1R  ------------------------------- */\r
+#define CCU8_CC8_DC1R_DT1R_Pos                0                                                       /*!< CCU8_CC8 DC1R: DT1R Position            */\r
+#define CCU8_CC8_DC1R_DT1R_Msk                (0x000000ffUL << CCU8_CC8_DC1R_DT1R_Pos)                /*!< CCU8_CC8 DC1R: DT1R Mask                */\r
+#define CCU8_CC8_DC1R_DT1F_Pos                8                                                       /*!< CCU8_CC8 DC1R: DT1F Position            */\r
+#define CCU8_CC8_DC1R_DT1F_Msk                (0x000000ffUL << CCU8_CC8_DC1R_DT1F_Pos)                /*!< CCU8_CC8 DC1R: DT1F Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_DC2R  ------------------------------- */\r
+#define CCU8_CC8_DC2R_DT2R_Pos                0                                                       /*!< CCU8_CC8 DC2R: DT2R Position            */\r
+#define CCU8_CC8_DC2R_DT2R_Msk                (0x000000ffUL << CCU8_CC8_DC2R_DT2R_Pos)                /*!< CCU8_CC8 DC2R: DT2R Mask                */\r
+#define CCU8_CC8_DC2R_DT2F_Pos                8                                                       /*!< CCU8_CC8 DC2R: DT2F Position            */\r
+#define CCU8_CC8_DC2R_DT2F_Msk                (0x000000ffUL << CCU8_CC8_DC2R_DT2F_Pos)                /*!< CCU8_CC8 DC2R: DT2F Mask                */\r
+\r
+/* -------------------------------  CCU8_CC8_TIMER  ------------------------------- */\r
+#define CCU8_CC8_TIMER_TVAL_Pos               0                                                       /*!< CCU8_CC8 TIMER: TVAL Position           */\r
+#define CCU8_CC8_TIMER_TVAL_Msk               (0x0000ffffUL << CCU8_CC8_TIMER_TVAL_Pos)               /*!< CCU8_CC8 TIMER: TVAL Mask               */\r
+\r
+/* ---------------------------------  CCU8_CC8_CV  -------------------------------- */\r
+#define CCU8_CC8_CV_CAPTV_Pos                 0                                                       /*!< CCU8_CC8 CV: CAPTV Position             */\r
+#define CCU8_CC8_CV_CAPTV_Msk                 (0x0000ffffUL << CCU8_CC8_CV_CAPTV_Pos)                 /*!< CCU8_CC8 CV: CAPTV Mask                 */\r
+#define CCU8_CC8_CV_FPCV_Pos                  16                                                      /*!< CCU8_CC8 CV: FPCV Position              */\r
+#define CCU8_CC8_CV_FPCV_Msk                  (0x0fUL << CCU8_CC8_CV_FPCV_Pos)                        /*!< CCU8_CC8 CV: FPCV Mask                  */\r
+#define CCU8_CC8_CV_FFL_Pos                   20                                                      /*!< CCU8_CC8 CV: FFL Position               */\r
+#define CCU8_CC8_CV_FFL_Msk                   (0x01UL << CCU8_CC8_CV_FFL_Pos)                         /*!< CCU8_CC8 CV: FFL Mask                   */\r
+\r
+/* --------------------------------  CCU8_CC8_INTS  ------------------------------- */\r
+#define CCU8_CC8_INTS_PMUS_Pos                0                                                       /*!< CCU8_CC8 INTS: PMUS Position            */\r
+#define CCU8_CC8_INTS_PMUS_Msk                (0x01UL << CCU8_CC8_INTS_PMUS_Pos)                      /*!< CCU8_CC8 INTS: PMUS Mask                */\r
+#define CCU8_CC8_INTS_OMDS_Pos                1                                                       /*!< CCU8_CC8 INTS: OMDS Position            */\r
+#define CCU8_CC8_INTS_OMDS_Msk                (0x01UL << CCU8_CC8_INTS_OMDS_Pos)                      /*!< CCU8_CC8 INTS: OMDS Mask                */\r
+#define CCU8_CC8_INTS_CMU1S_Pos               2                                                       /*!< CCU8_CC8 INTS: CMU1S Position           */\r
+#define CCU8_CC8_INTS_CMU1S_Msk               (0x01UL << CCU8_CC8_INTS_CMU1S_Pos)                     /*!< CCU8_CC8 INTS: CMU1S Mask               */\r
+#define CCU8_CC8_INTS_CMD1S_Pos               3                                                       /*!< CCU8_CC8 INTS: CMD1S Position           */\r
+#define CCU8_CC8_INTS_CMD1S_Msk               (0x01UL << CCU8_CC8_INTS_CMD1S_Pos)                     /*!< CCU8_CC8 INTS: CMD1S Mask               */\r
+#define CCU8_CC8_INTS_CMU2S_Pos               4                                                       /*!< CCU8_CC8 INTS: CMU2S Position           */\r
+#define CCU8_CC8_INTS_CMU2S_Msk               (0x01UL << CCU8_CC8_INTS_CMU2S_Pos)                     /*!< CCU8_CC8 INTS: CMU2S Mask               */\r
+#define CCU8_CC8_INTS_CMD2S_Pos               5                                                       /*!< CCU8_CC8 INTS: CMD2S Position           */\r
+#define CCU8_CC8_INTS_CMD2S_Msk               (0x01UL << CCU8_CC8_INTS_CMD2S_Pos)                     /*!< CCU8_CC8 INTS: CMD2S Mask               */\r
+#define CCU8_CC8_INTS_E0AS_Pos                8                                                       /*!< CCU8_CC8 INTS: E0AS Position            */\r
+#define CCU8_CC8_INTS_E0AS_Msk                (0x01UL << CCU8_CC8_INTS_E0AS_Pos)                      /*!< CCU8_CC8 INTS: E0AS Mask                */\r
+#define CCU8_CC8_INTS_E1AS_Pos                9                                                       /*!< CCU8_CC8 INTS: E1AS Position            */\r
+#define CCU8_CC8_INTS_E1AS_Msk                (0x01UL << CCU8_CC8_INTS_E1AS_Pos)                      /*!< CCU8_CC8 INTS: E1AS Mask                */\r
+#define CCU8_CC8_INTS_E2AS_Pos                10                                                      /*!< CCU8_CC8 INTS: E2AS Position            */\r
+#define CCU8_CC8_INTS_E2AS_Msk                (0x01UL << CCU8_CC8_INTS_E2AS_Pos)                      /*!< CCU8_CC8 INTS: E2AS Mask                */\r
+#define CCU8_CC8_INTS_TRPF_Pos                11                                                      /*!< CCU8_CC8 INTS: TRPF Position            */\r
+#define CCU8_CC8_INTS_TRPF_Msk                (0x01UL << CCU8_CC8_INTS_TRPF_Pos)                      /*!< CCU8_CC8 INTS: TRPF Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_INTE  ------------------------------- */\r
+#define CCU8_CC8_INTE_PME_Pos                 0                                                       /*!< CCU8_CC8 INTE: PME Position             */\r
+#define CCU8_CC8_INTE_PME_Msk                 (0x01UL << CCU8_CC8_INTE_PME_Pos)                       /*!< CCU8_CC8 INTE: PME Mask                 */\r
+#define CCU8_CC8_INTE_OME_Pos                 1                                                       /*!< CCU8_CC8 INTE: OME Position             */\r
+#define CCU8_CC8_INTE_OME_Msk                 (0x01UL << CCU8_CC8_INTE_OME_Pos)                       /*!< CCU8_CC8 INTE: OME Mask                 */\r
+#define CCU8_CC8_INTE_CMU1E_Pos               2                                                       /*!< CCU8_CC8 INTE: CMU1E Position           */\r
+#define CCU8_CC8_INTE_CMU1E_Msk               (0x01UL << CCU8_CC8_INTE_CMU1E_Pos)                     /*!< CCU8_CC8 INTE: CMU1E Mask               */\r
+#define CCU8_CC8_INTE_CMD1E_Pos               3                                                       /*!< CCU8_CC8 INTE: CMD1E Position           */\r
+#define CCU8_CC8_INTE_CMD1E_Msk               (0x01UL << CCU8_CC8_INTE_CMD1E_Pos)                     /*!< CCU8_CC8 INTE: CMD1E Mask               */\r
+#define CCU8_CC8_INTE_CMU2E_Pos               4                                                       /*!< CCU8_CC8 INTE: CMU2E Position           */\r
+#define CCU8_CC8_INTE_CMU2E_Msk               (0x01UL << CCU8_CC8_INTE_CMU2E_Pos)                     /*!< CCU8_CC8 INTE: CMU2E Mask               */\r
+#define CCU8_CC8_INTE_CMD2E_Pos               5                                                       /*!< CCU8_CC8 INTE: CMD2E Position           */\r
+#define CCU8_CC8_INTE_CMD2E_Msk               (0x01UL << CCU8_CC8_INTE_CMD2E_Pos)                     /*!< CCU8_CC8 INTE: CMD2E Mask               */\r
+#define CCU8_CC8_INTE_E0AE_Pos                8                                                       /*!< CCU8_CC8 INTE: E0AE Position            */\r
+#define CCU8_CC8_INTE_E0AE_Msk                (0x01UL << CCU8_CC8_INTE_E0AE_Pos)                      /*!< CCU8_CC8 INTE: E0AE Mask                */\r
+#define CCU8_CC8_INTE_E1AE_Pos                9                                                       /*!< CCU8_CC8 INTE: E1AE Position            */\r
+#define CCU8_CC8_INTE_E1AE_Msk                (0x01UL << CCU8_CC8_INTE_E1AE_Pos)                      /*!< CCU8_CC8 INTE: E1AE Mask                */\r
+#define CCU8_CC8_INTE_E2AE_Pos                10                                                      /*!< CCU8_CC8 INTE: E2AE Position            */\r
+#define CCU8_CC8_INTE_E2AE_Msk                (0x01UL << CCU8_CC8_INTE_E2AE_Pos)                      /*!< CCU8_CC8 INTE: E2AE Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_SRS  -------------------------------- */\r
+#define CCU8_CC8_SRS_POSR_Pos                 0                                                       /*!< CCU8_CC8 SRS: POSR Position             */\r
+#define CCU8_CC8_SRS_POSR_Msk                 (0x03UL << CCU8_CC8_SRS_POSR_Pos)                       /*!< CCU8_CC8 SRS: POSR Mask                 */\r
+#define CCU8_CC8_SRS_CM1SR_Pos                2                                                       /*!< CCU8_CC8 SRS: CM1SR Position            */\r
+#define CCU8_CC8_SRS_CM1SR_Msk                (0x03UL << CCU8_CC8_SRS_CM1SR_Pos)                      /*!< CCU8_CC8 SRS: CM1SR Mask                */\r
+#define CCU8_CC8_SRS_CM2SR_Pos                4                                                       /*!< CCU8_CC8 SRS: CM2SR Position            */\r
+#define CCU8_CC8_SRS_CM2SR_Msk                (0x03UL << CCU8_CC8_SRS_CM2SR_Pos)                      /*!< CCU8_CC8 SRS: CM2SR Mask                */\r
+#define CCU8_CC8_SRS_E0SR_Pos                 8                                                       /*!< CCU8_CC8 SRS: E0SR Position             */\r
+#define CCU8_CC8_SRS_E0SR_Msk                 (0x03UL << CCU8_CC8_SRS_E0SR_Pos)                       /*!< CCU8_CC8 SRS: E0SR Mask                 */\r
+#define CCU8_CC8_SRS_E1SR_Pos                 10                                                      /*!< CCU8_CC8 SRS: E1SR Position             */\r
+#define CCU8_CC8_SRS_E1SR_Msk                 (0x03UL << CCU8_CC8_SRS_E1SR_Pos)                       /*!< CCU8_CC8 SRS: E1SR Mask                 */\r
+#define CCU8_CC8_SRS_E2SR_Pos                 12                                                      /*!< CCU8_CC8 SRS: E2SR Position             */\r
+#define CCU8_CC8_SRS_E2SR_Msk                 (0x03UL << CCU8_CC8_SRS_E2SR_Pos)                       /*!< CCU8_CC8 SRS: E2SR Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_SWS  -------------------------------- */\r
+#define CCU8_CC8_SWS_SPM_Pos                  0                                                       /*!< CCU8_CC8 SWS: SPM Position              */\r
+#define CCU8_CC8_SWS_SPM_Msk                  (0x01UL << CCU8_CC8_SWS_SPM_Pos)                        /*!< CCU8_CC8 SWS: SPM Mask                  */\r
+#define CCU8_CC8_SWS_SOM_Pos                  1                                                       /*!< CCU8_CC8 SWS: SOM Position              */\r
+#define CCU8_CC8_SWS_SOM_Msk                  (0x01UL << CCU8_CC8_SWS_SOM_Pos)                        /*!< CCU8_CC8 SWS: SOM Mask                  */\r
+#define CCU8_CC8_SWS_SCM1U_Pos                2                                                       /*!< CCU8_CC8 SWS: SCM1U Position            */\r
+#define CCU8_CC8_SWS_SCM1U_Msk                (0x01UL << CCU8_CC8_SWS_SCM1U_Pos)                      /*!< CCU8_CC8 SWS: SCM1U Mask                */\r
+#define CCU8_CC8_SWS_SCM1D_Pos                3                                                       /*!< CCU8_CC8 SWS: SCM1D Position            */\r
+#define CCU8_CC8_SWS_SCM1D_Msk                (0x01UL << CCU8_CC8_SWS_SCM1D_Pos)                      /*!< CCU8_CC8 SWS: SCM1D Mask                */\r
+#define CCU8_CC8_SWS_SCM2U_Pos                4                                                       /*!< CCU8_CC8 SWS: SCM2U Position            */\r
+#define CCU8_CC8_SWS_SCM2U_Msk                (0x01UL << CCU8_CC8_SWS_SCM2U_Pos)                      /*!< CCU8_CC8 SWS: SCM2U Mask                */\r
+#define CCU8_CC8_SWS_SCM2D_Pos                5                                                       /*!< CCU8_CC8 SWS: SCM2D Position            */\r
+#define CCU8_CC8_SWS_SCM2D_Msk                (0x01UL << CCU8_CC8_SWS_SCM2D_Pos)                      /*!< CCU8_CC8 SWS: SCM2D Mask                */\r
+#define CCU8_CC8_SWS_SE0A_Pos                 8                                                       /*!< CCU8_CC8 SWS: SE0A Position             */\r
+#define CCU8_CC8_SWS_SE0A_Msk                 (0x01UL << CCU8_CC8_SWS_SE0A_Pos)                       /*!< CCU8_CC8 SWS: SE0A Mask                 */\r
+#define CCU8_CC8_SWS_SE1A_Pos                 9                                                       /*!< CCU8_CC8 SWS: SE1A Position             */\r
+#define CCU8_CC8_SWS_SE1A_Msk                 (0x01UL << CCU8_CC8_SWS_SE1A_Pos)                       /*!< CCU8_CC8 SWS: SE1A Mask                 */\r
+#define CCU8_CC8_SWS_SE2A_Pos                 10                                                      /*!< CCU8_CC8 SWS: SE2A Position             */\r
+#define CCU8_CC8_SWS_SE2A_Msk                 (0x01UL << CCU8_CC8_SWS_SE2A_Pos)                       /*!< CCU8_CC8 SWS: SE2A Mask                 */\r
+#define CCU8_CC8_SWS_STRPF_Pos                11                                                      /*!< CCU8_CC8 SWS: STRPF Position            */\r
+#define CCU8_CC8_SWS_STRPF_Msk                (0x01UL << CCU8_CC8_SWS_STRPF_Pos)                      /*!< CCU8_CC8 SWS: STRPF Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_SWR  -------------------------------- */\r
+#define CCU8_CC8_SWR_RPM_Pos                  0                                                       /*!< CCU8_CC8 SWR: RPM Position              */\r
+#define CCU8_CC8_SWR_RPM_Msk                  (0x01UL << CCU8_CC8_SWR_RPM_Pos)                        /*!< CCU8_CC8 SWR: RPM Mask                  */\r
+#define CCU8_CC8_SWR_ROM_Pos                  1                                                       /*!< CCU8_CC8 SWR: ROM Position              */\r
+#define CCU8_CC8_SWR_ROM_Msk                  (0x01UL << CCU8_CC8_SWR_ROM_Pos)                        /*!< CCU8_CC8 SWR: ROM Mask                  */\r
+#define CCU8_CC8_SWR_RCM1U_Pos                2                                                       /*!< CCU8_CC8 SWR: RCM1U Position            */\r
+#define CCU8_CC8_SWR_RCM1U_Msk                (0x01UL << CCU8_CC8_SWR_RCM1U_Pos)                      /*!< CCU8_CC8 SWR: RCM1U Mask                */\r
+#define CCU8_CC8_SWR_RCM1D_Pos                3                                                       /*!< CCU8_CC8 SWR: RCM1D Position            */\r
+#define CCU8_CC8_SWR_RCM1D_Msk                (0x01UL << CCU8_CC8_SWR_RCM1D_Pos)                      /*!< CCU8_CC8 SWR: RCM1D Mask                */\r
+#define CCU8_CC8_SWR_RCM2U_Pos                4                                                       /*!< CCU8_CC8 SWR: RCM2U Position            */\r
+#define CCU8_CC8_SWR_RCM2U_Msk                (0x01UL << CCU8_CC8_SWR_RCM2U_Pos)                      /*!< CCU8_CC8 SWR: RCM2U Mask                */\r
+#define CCU8_CC8_SWR_RCM2D_Pos                5                                                       /*!< CCU8_CC8 SWR: RCM2D Position            */\r
+#define CCU8_CC8_SWR_RCM2D_Msk                (0x01UL << CCU8_CC8_SWR_RCM2D_Pos)                      /*!< CCU8_CC8 SWR: RCM2D Mask                */\r
+#define CCU8_CC8_SWR_RE0A_Pos                 8                                                       /*!< CCU8_CC8 SWR: RE0A Position             */\r
+#define CCU8_CC8_SWR_RE0A_Msk                 (0x01UL << CCU8_CC8_SWR_RE0A_Pos)                       /*!< CCU8_CC8 SWR: RE0A Mask                 */\r
+#define CCU8_CC8_SWR_RE1A_Pos                 9                                                       /*!< CCU8_CC8 SWR: RE1A Position             */\r
+#define CCU8_CC8_SWR_RE1A_Msk                 (0x01UL << CCU8_CC8_SWR_RE1A_Pos)                       /*!< CCU8_CC8 SWR: RE1A Mask                 */\r
+#define CCU8_CC8_SWR_RE2A_Pos                 10                                                      /*!< CCU8_CC8 SWR: RE2A Position             */\r
+#define CCU8_CC8_SWR_RE2A_Msk                 (0x01UL << CCU8_CC8_SWR_RE2A_Pos)                       /*!< CCU8_CC8 SWR: RE2A Mask                 */\r
+#define CCU8_CC8_SWR_RTRPF_Pos                11                                                      /*!< CCU8_CC8 SWR: RTRPF Position            */\r
+#define CCU8_CC8_SWR_RTRPF_Msk                (0x01UL << CCU8_CC8_SWR_RTRPF_Pos)                      /*!< CCU8_CC8 SWR: RTRPF Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_STC  -------------------------------- */\r
+#define CCU8_CC8_STC_CSE_Pos                  0                                                       /*!< CCU8_CC8 STC: CSE Position              */\r
+#define CCU8_CC8_STC_CSE_Msk                  (0x01UL << CCU8_CC8_STC_CSE_Pos)                        /*!< CCU8_CC8 STC: CSE Mask                  */\r
+#define CCU8_CC8_STC_STM_Pos                  1                                                       /*!< CCU8_CC8 STC: STM Position              */\r
+#define CCU8_CC8_STC_STM_Msk                  (0x03UL << CCU8_CC8_STC_STM_Pos)                        /*!< CCU8_CC8 STC: STM Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'HRPWM0' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  HRPWM0_HRBSC  -------------------------------- */\r
+#define HRPWM0_HRBSC_SUSCFG_Pos               0                                                       /*!< HRPWM0 HRBSC: SUSCFG Position           */\r
+#define HRPWM0_HRBSC_SUSCFG_Msk               (0x07UL << HRPWM0_HRBSC_SUSCFG_Pos)                     /*!< HRPWM0 HRBSC: SUSCFG Mask               */\r
+#define HRPWM0_HRBSC_HRBE_Pos                 8                                                       /*!< HRPWM0 HRBSC: HRBE Position             */\r
+#define HRPWM0_HRBSC_HRBE_Msk                 (0x01UL << HRPWM0_HRBSC_HRBE_Pos)                       /*!< HRPWM0 HRBSC: HRBE Mask                 */\r
+\r
+/* ---------------------------------  HRPWM0_MIDR  -------------------------------- */\r
+#define HRPWM0_MIDR_MODR_Pos                  0                                                       /*!< HRPWM0 MIDR: MODR Position              */\r
+#define HRPWM0_MIDR_MODR_Msk                  (0x000000ffUL << HRPWM0_MIDR_MODR_Pos)                  /*!< HRPWM0 MIDR: MODR Mask                  */\r
+#define HRPWM0_MIDR_MODT_Pos                  8                                                       /*!< HRPWM0 MIDR: MODT Position              */\r
+#define HRPWM0_MIDR_MODT_Msk                  (0x000000ffUL << HRPWM0_MIDR_MODT_Pos)                  /*!< HRPWM0 MIDR: MODT Mask                  */\r
+#define HRPWM0_MIDR_MODN_Pos                  16                                                      /*!< HRPWM0 MIDR: MODN Position              */\r
+#define HRPWM0_MIDR_MODN_Msk                  (0x0000ffffUL << HRPWM0_MIDR_MODN_Pos)                  /*!< HRPWM0 MIDR: MODN Mask                  */\r
+\r
+/* --------------------------------  HRPWM0_GLBANA  ------------------------------- */\r
+#define HRPWM0_GLBANA_SLDLY_Pos               0                                                       /*!< HRPWM0 GLBANA: SLDLY Position           */\r
+#define HRPWM0_GLBANA_SLDLY_Msk               (0x03UL << HRPWM0_GLBANA_SLDLY_Pos)                     /*!< HRPWM0 GLBANA: SLDLY Mask               */\r
+#define HRPWM0_GLBANA_FUP_Pos                 2                                                       /*!< HRPWM0 GLBANA: FUP Position             */\r
+#define HRPWM0_GLBANA_FUP_Msk                 (0x01UL << HRPWM0_GLBANA_FUP_Pos)                       /*!< HRPWM0 GLBANA: FUP Mask                 */\r
+#define HRPWM0_GLBANA_FDN_Pos                 3                                                       /*!< HRPWM0 GLBANA: FDN Position             */\r
+#define HRPWM0_GLBANA_FDN_Msk                 (0x01UL << HRPWM0_GLBANA_FDN_Pos)                       /*!< HRPWM0 GLBANA: FDN Mask                 */\r
+#define HRPWM0_GLBANA_SLCP_Pos                6                                                       /*!< HRPWM0 GLBANA: SLCP Position            */\r
+#define HRPWM0_GLBANA_SLCP_Msk                (0x07UL << HRPWM0_GLBANA_SLCP_Pos)                      /*!< HRPWM0 GLBANA: SLCP Mask                */\r
+#define HRPWM0_GLBANA_SLIBLDO_Pos             9                                                       /*!< HRPWM0 GLBANA: SLIBLDO Position         */\r
+#define HRPWM0_GLBANA_SLIBLDO_Msk             (0x03UL << HRPWM0_GLBANA_SLIBLDO_Pos)                   /*!< HRPWM0 GLBANA: SLIBLDO Mask             */\r
+#define HRPWM0_GLBANA_SLIBLF_Pos              11                                                      /*!< HRPWM0 GLBANA: SLIBLF Position          */\r
+#define HRPWM0_GLBANA_SLIBLF_Msk              (0x03UL << HRPWM0_GLBANA_SLIBLF_Pos)                    /*!< HRPWM0 GLBANA: SLIBLF Mask              */\r
+#define HRPWM0_GLBANA_SLVREF_Pos              13                                                      /*!< HRPWM0 GLBANA: SLVREF Position          */\r
+#define HRPWM0_GLBANA_SLVREF_Msk              (0x07UL << HRPWM0_GLBANA_SLVREF_Pos)                    /*!< HRPWM0 GLBANA: SLVREF Mask              */\r
+#define HRPWM0_GLBANA_TRIBIAS_Pos             16                                                      /*!< HRPWM0 GLBANA: TRIBIAS Position         */\r
+#define HRPWM0_GLBANA_TRIBIAS_Msk             (0x03UL << HRPWM0_GLBANA_TRIBIAS_Pos)                   /*!< HRPWM0 GLBANA: TRIBIAS Mask             */\r
+#define HRPWM0_GLBANA_GHREN_Pos               18                                                      /*!< HRPWM0 GLBANA: GHREN Position           */\r
+#define HRPWM0_GLBANA_GHREN_Msk               (0x01UL << HRPWM0_GLBANA_GHREN_Pos)                     /*!< HRPWM0 GLBANA: GHREN Mask               */\r
+\r
+/* --------------------------------  HRPWM0_CSGCFG  ------------------------------- */\r
+#define HRPWM0_CSGCFG_C0PM_Pos                0                                                       /*!< HRPWM0 CSGCFG: C0PM Position            */\r
+#define HRPWM0_CSGCFG_C0PM_Msk                (0x03UL << HRPWM0_CSGCFG_C0PM_Pos)                      /*!< HRPWM0 CSGCFG: C0PM Mask                */\r
+#define HRPWM0_CSGCFG_C1PM_Pos                2                                                       /*!< HRPWM0 CSGCFG: C1PM Position            */\r
+#define HRPWM0_CSGCFG_C1PM_Msk                (0x03UL << HRPWM0_CSGCFG_C1PM_Pos)                      /*!< HRPWM0 CSGCFG: C1PM Mask                */\r
+#define HRPWM0_CSGCFG_C2PM_Pos                4                                                       /*!< HRPWM0 CSGCFG: C2PM Position            */\r
+#define HRPWM0_CSGCFG_C2PM_Msk                (0x03UL << HRPWM0_CSGCFG_C2PM_Pos)                      /*!< HRPWM0 CSGCFG: C2PM Mask                */\r
+#define HRPWM0_CSGCFG_C0CD_Pos                16                                                      /*!< HRPWM0 CSGCFG: C0CD Position            */\r
+#define HRPWM0_CSGCFG_C0CD_Msk                (0x01UL << HRPWM0_CSGCFG_C0CD_Pos)                      /*!< HRPWM0 CSGCFG: C0CD Mask                */\r
+#define HRPWM0_CSGCFG_C1CD_Pos                17                                                      /*!< HRPWM0 CSGCFG: C1CD Position            */\r
+#define HRPWM0_CSGCFG_C1CD_Msk                (0x01UL << HRPWM0_CSGCFG_C1CD_Pos)                      /*!< HRPWM0 CSGCFG: C1CD Mask                */\r
+#define HRPWM0_CSGCFG_C2CD_Pos                18                                                      /*!< HRPWM0 CSGCFG: C2CD Position            */\r
+#define HRPWM0_CSGCFG_C2CD_Msk                (0x01UL << HRPWM0_CSGCFG_C2CD_Pos)                      /*!< HRPWM0 CSGCFG: C2CD Mask                */\r
+\r
+/* -------------------------------  HRPWM0_CSGSETG  ------------------------------- */\r
+#define HRPWM0_CSGSETG_SD0R_Pos               0                                                       /*!< HRPWM0 CSGSETG: SD0R Position           */\r
+#define HRPWM0_CSGSETG_SD0R_Msk               (0x01UL << HRPWM0_CSGSETG_SD0R_Pos)                     /*!< HRPWM0 CSGSETG: SD0R Mask               */\r
+#define HRPWM0_CSGSETG_SC0R_Pos               1                                                       /*!< HRPWM0 CSGSETG: SC0R Position           */\r
+#define HRPWM0_CSGSETG_SC0R_Msk               (0x01UL << HRPWM0_CSGSETG_SC0R_Pos)                     /*!< HRPWM0 CSGSETG: SC0R Mask               */\r
+#define HRPWM0_CSGSETG_SC0P_Pos               2                                                       /*!< HRPWM0 CSGSETG: SC0P Position           */\r
+#define HRPWM0_CSGSETG_SC0P_Msk               (0x01UL << HRPWM0_CSGSETG_SC0P_Pos)                     /*!< HRPWM0 CSGSETG: SC0P Mask               */\r
+#define HRPWM0_CSGSETG_SD1R_Pos               4                                                       /*!< HRPWM0 CSGSETG: SD1R Position           */\r
+#define HRPWM0_CSGSETG_SD1R_Msk               (0x01UL << HRPWM0_CSGSETG_SD1R_Pos)                     /*!< HRPWM0 CSGSETG: SD1R Mask               */\r
+#define HRPWM0_CSGSETG_SC1R_Pos               5                                                       /*!< HRPWM0 CSGSETG: SC1R Position           */\r
+#define HRPWM0_CSGSETG_SC1R_Msk               (0x01UL << HRPWM0_CSGSETG_SC1R_Pos)                     /*!< HRPWM0 CSGSETG: SC1R Mask               */\r
+#define HRPWM0_CSGSETG_SC1P_Pos               6                                                       /*!< HRPWM0 CSGSETG: SC1P Position           */\r
+#define HRPWM0_CSGSETG_SC1P_Msk               (0x01UL << HRPWM0_CSGSETG_SC1P_Pos)                     /*!< HRPWM0 CSGSETG: SC1P Mask               */\r
+#define HRPWM0_CSGSETG_SD2R_Pos               8                                                       /*!< HRPWM0 CSGSETG: SD2R Position           */\r
+#define HRPWM0_CSGSETG_SD2R_Msk               (0x01UL << HRPWM0_CSGSETG_SD2R_Pos)                     /*!< HRPWM0 CSGSETG: SD2R Mask               */\r
+#define HRPWM0_CSGSETG_SC2R_Pos               9                                                       /*!< HRPWM0 CSGSETG: SC2R Position           */\r
+#define HRPWM0_CSGSETG_SC2R_Msk               (0x01UL << HRPWM0_CSGSETG_SC2R_Pos)                     /*!< HRPWM0 CSGSETG: SC2R Mask               */\r
+#define HRPWM0_CSGSETG_SC2P_Pos               10                                                      /*!< HRPWM0 CSGSETG: SC2P Position           */\r
+#define HRPWM0_CSGSETG_SC2P_Msk               (0x01UL << HRPWM0_CSGSETG_SC2P_Pos)                     /*!< HRPWM0 CSGSETG: SC2P Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSGCLRG  ------------------------------- */\r
+#define HRPWM0_CSGCLRG_CD0R_Pos               0                                                       /*!< HRPWM0 CSGCLRG: CD0R Position           */\r
+#define HRPWM0_CSGCLRG_CD0R_Msk               (0x01UL << HRPWM0_CSGCLRG_CD0R_Pos)                     /*!< HRPWM0 CSGCLRG: CD0R Mask               */\r
+#define HRPWM0_CSGCLRG_CC0R_Pos               1                                                       /*!< HRPWM0 CSGCLRG: CC0R Position           */\r
+#define HRPWM0_CSGCLRG_CC0R_Msk               (0x01UL << HRPWM0_CSGCLRG_CC0R_Pos)                     /*!< HRPWM0 CSGCLRG: CC0R Mask               */\r
+#define HRPWM0_CSGCLRG_CC0P_Pos               2                                                       /*!< HRPWM0 CSGCLRG: CC0P Position           */\r
+#define HRPWM0_CSGCLRG_CC0P_Msk               (0x01UL << HRPWM0_CSGCLRG_CC0P_Pos)                     /*!< HRPWM0 CSGCLRG: CC0P Mask               */\r
+#define HRPWM0_CSGCLRG_CD1R_Pos               4                                                       /*!< HRPWM0 CSGCLRG: CD1R Position           */\r
+#define HRPWM0_CSGCLRG_CD1R_Msk               (0x01UL << HRPWM0_CSGCLRG_CD1R_Pos)                     /*!< HRPWM0 CSGCLRG: CD1R Mask               */\r
+#define HRPWM0_CSGCLRG_CC1R_Pos               5                                                       /*!< HRPWM0 CSGCLRG: CC1R Position           */\r
+#define HRPWM0_CSGCLRG_CC1R_Msk               (0x01UL << HRPWM0_CSGCLRG_CC1R_Pos)                     /*!< HRPWM0 CSGCLRG: CC1R Mask               */\r
+#define HRPWM0_CSGCLRG_CC1P_Pos               6                                                       /*!< HRPWM0 CSGCLRG: CC1P Position           */\r
+#define HRPWM0_CSGCLRG_CC1P_Msk               (0x01UL << HRPWM0_CSGCLRG_CC1P_Pos)                     /*!< HRPWM0 CSGCLRG: CC1P Mask               */\r
+#define HRPWM0_CSGCLRG_CD2R_Pos               8                                                       /*!< HRPWM0 CSGCLRG: CD2R Position           */\r
+#define HRPWM0_CSGCLRG_CD2R_Msk               (0x01UL << HRPWM0_CSGCLRG_CD2R_Pos)                     /*!< HRPWM0 CSGCLRG: CD2R Mask               */\r
+#define HRPWM0_CSGCLRG_CC2R_Pos               9                                                       /*!< HRPWM0 CSGCLRG: CC2R Position           */\r
+#define HRPWM0_CSGCLRG_CC2R_Msk               (0x01UL << HRPWM0_CSGCLRG_CC2R_Pos)                     /*!< HRPWM0 CSGCLRG: CC2R Mask               */\r
+#define HRPWM0_CSGCLRG_CC2P_Pos               10                                                      /*!< HRPWM0 CSGCLRG: CC2P Position           */\r
+#define HRPWM0_CSGCLRG_CC2P_Msk               (0x01UL << HRPWM0_CSGCLRG_CC2P_Pos)                     /*!< HRPWM0 CSGCLRG: CC2P Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSGSTATG  ------------------------------ */\r
+#define HRPWM0_CSGSTATG_D0RB_Pos              0                                                       /*!< HRPWM0 CSGSTATG: D0RB Position          */\r
+#define HRPWM0_CSGSTATG_D0RB_Msk              (0x01UL << HRPWM0_CSGSTATG_D0RB_Pos)                    /*!< HRPWM0 CSGSTATG: D0RB Mask              */\r
+#define HRPWM0_CSGSTATG_C0RB_Pos              1                                                       /*!< HRPWM0 CSGSTATG: C0RB Position          */\r
+#define HRPWM0_CSGSTATG_C0RB_Msk              (0x01UL << HRPWM0_CSGSTATG_C0RB_Pos)                    /*!< HRPWM0 CSGSTATG: C0RB Mask              */\r
+#define HRPWM0_CSGSTATG_PSLS0_Pos             2                                                       /*!< HRPWM0 CSGSTATG: PSLS0 Position         */\r
+#define HRPWM0_CSGSTATG_PSLS0_Msk             (0x01UL << HRPWM0_CSGSTATG_PSLS0_Pos)                   /*!< HRPWM0 CSGSTATG: PSLS0 Mask             */\r
+#define HRPWM0_CSGSTATG_D1RB_Pos              4                                                       /*!< HRPWM0 CSGSTATG: D1RB Position          */\r
+#define HRPWM0_CSGSTATG_D1RB_Msk              (0x01UL << HRPWM0_CSGSTATG_D1RB_Pos)                    /*!< HRPWM0 CSGSTATG: D1RB Mask              */\r
+#define HRPWM0_CSGSTATG_C1RB_Pos              5                                                       /*!< HRPWM0 CSGSTATG: C1RB Position          */\r
+#define HRPWM0_CSGSTATG_C1RB_Msk              (0x01UL << HRPWM0_CSGSTATG_C1RB_Pos)                    /*!< HRPWM0 CSGSTATG: C1RB Mask              */\r
+#define HRPWM0_CSGSTATG_PSLS1_Pos             6                                                       /*!< HRPWM0 CSGSTATG: PSLS1 Position         */\r
+#define HRPWM0_CSGSTATG_PSLS1_Msk             (0x01UL << HRPWM0_CSGSTATG_PSLS1_Pos)                   /*!< HRPWM0 CSGSTATG: PSLS1 Mask             */\r
+#define HRPWM0_CSGSTATG_D2RB_Pos              8                                                       /*!< HRPWM0 CSGSTATG: D2RB Position          */\r
+#define HRPWM0_CSGSTATG_D2RB_Msk              (0x01UL << HRPWM0_CSGSTATG_D2RB_Pos)                    /*!< HRPWM0 CSGSTATG: D2RB Mask              */\r
+#define HRPWM0_CSGSTATG_C2RB_Pos              9                                                       /*!< HRPWM0 CSGSTATG: C2RB Position          */\r
+#define HRPWM0_CSGSTATG_C2RB_Msk              (0x01UL << HRPWM0_CSGSTATG_C2RB_Pos)                    /*!< HRPWM0 CSGSTATG: C2RB Mask              */\r
+#define HRPWM0_CSGSTATG_PSLS2_Pos             10                                                      /*!< HRPWM0 CSGSTATG: PSLS2 Position         */\r
+#define HRPWM0_CSGSTATG_PSLS2_Msk             (0x01UL << HRPWM0_CSGSTATG_PSLS2_Pos)                   /*!< HRPWM0 CSGSTATG: PSLS2 Mask             */\r
+\r
+/* --------------------------------  HRPWM0_CSGFCG  ------------------------------- */\r
+#define HRPWM0_CSGFCG_S0STR_Pos               0                                                       /*!< HRPWM0 CSGFCG: S0STR Position           */\r
+#define HRPWM0_CSGFCG_S0STR_Msk               (0x01UL << HRPWM0_CSGFCG_S0STR_Pos)                     /*!< HRPWM0 CSGFCG: S0STR Mask               */\r
+#define HRPWM0_CSGFCG_S0STP_Pos               1                                                       /*!< HRPWM0 CSGFCG: S0STP Position           */\r
+#define HRPWM0_CSGFCG_S0STP_Msk               (0x01UL << HRPWM0_CSGFCG_S0STP_Pos)                     /*!< HRPWM0 CSGFCG: S0STP Mask               */\r
+#define HRPWM0_CSGFCG_PS0STR_Pos              2                                                       /*!< HRPWM0 CSGFCG: PS0STR Position          */\r
+#define HRPWM0_CSGFCG_PS0STR_Msk              (0x01UL << HRPWM0_CSGFCG_PS0STR_Pos)                    /*!< HRPWM0 CSGFCG: PS0STR Mask              */\r
+#define HRPWM0_CSGFCG_PS0STP_Pos              3                                                       /*!< HRPWM0 CSGFCG: PS0STP Position          */\r
+#define HRPWM0_CSGFCG_PS0STP_Msk              (0x01UL << HRPWM0_CSGFCG_PS0STP_Pos)                    /*!< HRPWM0 CSGFCG: PS0STP Mask              */\r
+#define HRPWM0_CSGFCG_PS0CLR_Pos              4                                                       /*!< HRPWM0 CSGFCG: PS0CLR Position          */\r
+#define HRPWM0_CSGFCG_PS0CLR_Msk              (0x01UL << HRPWM0_CSGFCG_PS0CLR_Pos)                    /*!< HRPWM0 CSGFCG: PS0CLR Mask              */\r
+#define HRPWM0_CSGFCG_S1STR_Pos               8                                                       /*!< HRPWM0 CSGFCG: S1STR Position           */\r
+#define HRPWM0_CSGFCG_S1STR_Msk               (0x01UL << HRPWM0_CSGFCG_S1STR_Pos)                     /*!< HRPWM0 CSGFCG: S1STR Mask               */\r
+#define HRPWM0_CSGFCG_S1STP_Pos               9                                                       /*!< HRPWM0 CSGFCG: S1STP Position           */\r
+#define HRPWM0_CSGFCG_S1STP_Msk               (0x01UL << HRPWM0_CSGFCG_S1STP_Pos)                     /*!< HRPWM0 CSGFCG: S1STP Mask               */\r
+#define HRPWM0_CSGFCG_PS1STR_Pos              10                                                      /*!< HRPWM0 CSGFCG: PS1STR Position          */\r
+#define HRPWM0_CSGFCG_PS1STR_Msk              (0x01UL << HRPWM0_CSGFCG_PS1STR_Pos)                    /*!< HRPWM0 CSGFCG: PS1STR Mask              */\r
+#define HRPWM0_CSGFCG_PS1STP_Pos              11                                                      /*!< HRPWM0 CSGFCG: PS1STP Position          */\r
+#define HRPWM0_CSGFCG_PS1STP_Msk              (0x01UL << HRPWM0_CSGFCG_PS1STP_Pos)                    /*!< HRPWM0 CSGFCG: PS1STP Mask              */\r
+#define HRPWM0_CSGFCG_PS1CLR_Pos              12                                                      /*!< HRPWM0 CSGFCG: PS1CLR Position          */\r
+#define HRPWM0_CSGFCG_PS1CLR_Msk              (0x01UL << HRPWM0_CSGFCG_PS1CLR_Pos)                    /*!< HRPWM0 CSGFCG: PS1CLR Mask              */\r
+#define HRPWM0_CSGFCG_S2STR_Pos               16                                                      /*!< HRPWM0 CSGFCG: S2STR Position           */\r
+#define HRPWM0_CSGFCG_S2STR_Msk               (0x01UL << HRPWM0_CSGFCG_S2STR_Pos)                     /*!< HRPWM0 CSGFCG: S2STR Mask               */\r
+#define HRPWM0_CSGFCG_S2STP_Pos               17                                                      /*!< HRPWM0 CSGFCG: S2STP Position           */\r
+#define HRPWM0_CSGFCG_S2STP_Msk               (0x01UL << HRPWM0_CSGFCG_S2STP_Pos)                     /*!< HRPWM0 CSGFCG: S2STP Mask               */\r
+#define HRPWM0_CSGFCG_PS2STR_Pos              18                                                      /*!< HRPWM0 CSGFCG: PS2STR Position          */\r
+#define HRPWM0_CSGFCG_PS2STR_Msk              (0x01UL << HRPWM0_CSGFCG_PS2STR_Pos)                    /*!< HRPWM0 CSGFCG: PS2STR Mask              */\r
+#define HRPWM0_CSGFCG_PS2STP_Pos              19                                                      /*!< HRPWM0 CSGFCG: PS2STP Position          */\r
+#define HRPWM0_CSGFCG_PS2STP_Msk              (0x01UL << HRPWM0_CSGFCG_PS2STP_Pos)                    /*!< HRPWM0 CSGFCG: PS2STP Mask              */\r
+#define HRPWM0_CSGFCG_PS2CLR_Pos              20                                                      /*!< HRPWM0 CSGFCG: PS2CLR Position          */\r
+#define HRPWM0_CSGFCG_PS2CLR_Msk              (0x01UL << HRPWM0_CSGFCG_PS2CLR_Pos)                    /*!< HRPWM0 CSGFCG: PS2CLR Mask              */\r
+\r
+/* --------------------------------  HRPWM0_CSGFSG  ------------------------------- */\r
+#define HRPWM0_CSGFSG_S0RB_Pos                0                                                       /*!< HRPWM0 CSGFSG: S0RB Position            */\r
+#define HRPWM0_CSGFSG_S0RB_Msk                (0x01UL << HRPWM0_CSGFSG_S0RB_Pos)                      /*!< HRPWM0 CSGFSG: S0RB Mask                */\r
+#define HRPWM0_CSGFSG_P0RB_Pos                1                                                       /*!< HRPWM0 CSGFSG: P0RB Position            */\r
+#define HRPWM0_CSGFSG_P0RB_Msk                (0x01UL << HRPWM0_CSGFSG_P0RB_Pos)                      /*!< HRPWM0 CSGFSG: P0RB Mask                */\r
+#define HRPWM0_CSGFSG_S1RB_Pos                8                                                       /*!< HRPWM0 CSGFSG: S1RB Position            */\r
+#define HRPWM0_CSGFSG_S1RB_Msk                (0x01UL << HRPWM0_CSGFSG_S1RB_Pos)                      /*!< HRPWM0 CSGFSG: S1RB Mask                */\r
+#define HRPWM0_CSGFSG_P1RB_Pos                9                                                       /*!< HRPWM0 CSGFSG: P1RB Position            */\r
+#define HRPWM0_CSGFSG_P1RB_Msk                (0x01UL << HRPWM0_CSGFSG_P1RB_Pos)                      /*!< HRPWM0 CSGFSG: P1RB Mask                */\r
+#define HRPWM0_CSGFSG_S2RB_Pos                16                                                      /*!< HRPWM0 CSGFSG: S2RB Position            */\r
+#define HRPWM0_CSGFSG_S2RB_Msk                (0x01UL << HRPWM0_CSGFSG_S2RB_Pos)                      /*!< HRPWM0 CSGFSG: S2RB Mask                */\r
+#define HRPWM0_CSGFSG_P2RB_Pos                17                                                      /*!< HRPWM0 CSGFSG: P2RB Position            */\r
+#define HRPWM0_CSGFSG_P2RB_Msk                (0x01UL << HRPWM0_CSGFSG_P2RB_Pos)                      /*!< HRPWM0 CSGFSG: P2RB Mask                */\r
+\r
+/* --------------------------------  HRPWM0_CSGTRG  ------------------------------- */\r
+#define HRPWM0_CSGTRG_D0SES_Pos               0                                                       /*!< HRPWM0 CSGTRG: D0SES Position           */\r
+#define HRPWM0_CSGTRG_D0SES_Msk               (0x01UL << HRPWM0_CSGTRG_D0SES_Pos)                     /*!< HRPWM0 CSGTRG: D0SES Mask               */\r
+#define HRPWM0_CSGTRG_D0SVS_Pos               1                                                       /*!< HRPWM0 CSGTRG: D0SVS Position           */\r
+#define HRPWM0_CSGTRG_D0SVS_Msk               (0x01UL << HRPWM0_CSGTRG_D0SVS_Pos)                     /*!< HRPWM0 CSGTRG: D0SVS Mask               */\r
+#define HRPWM0_CSGTRG_D1SES_Pos               4                                                       /*!< HRPWM0 CSGTRG: D1SES Position           */\r
+#define HRPWM0_CSGTRG_D1SES_Msk               (0x01UL << HRPWM0_CSGTRG_D1SES_Pos)                     /*!< HRPWM0 CSGTRG: D1SES Mask               */\r
+#define HRPWM0_CSGTRG_D1SVS_Pos               5                                                       /*!< HRPWM0 CSGTRG: D1SVS Position           */\r
+#define HRPWM0_CSGTRG_D1SVS_Msk               (0x01UL << HRPWM0_CSGTRG_D1SVS_Pos)                     /*!< HRPWM0 CSGTRG: D1SVS Mask               */\r
+#define HRPWM0_CSGTRG_D2SES_Pos               8                                                       /*!< HRPWM0 CSGTRG: D2SES Position           */\r
+#define HRPWM0_CSGTRG_D2SES_Msk               (0x01UL << HRPWM0_CSGTRG_D2SES_Pos)                     /*!< HRPWM0 CSGTRG: D2SES Mask               */\r
+#define HRPWM0_CSGTRG_D2SVS_Pos               9                                                       /*!< HRPWM0 CSGTRG: D2SVS Position           */\r
+#define HRPWM0_CSGTRG_D2SVS_Msk               (0x01UL << HRPWM0_CSGTRG_D2SVS_Pos)                     /*!< HRPWM0 CSGTRG: D2SVS Mask               */\r
+\r
+/* --------------------------------  HRPWM0_CSGTRC  ------------------------------- */\r
+#define HRPWM0_CSGTRC_D0SEC_Pos               0                                                       /*!< HRPWM0 CSGTRC: D0SEC Position           */\r
+#define HRPWM0_CSGTRC_D0SEC_Msk               (0x01UL << HRPWM0_CSGTRC_D0SEC_Pos)                     /*!< HRPWM0 CSGTRC: D0SEC Mask               */\r
+#define HRPWM0_CSGTRC_D1SEC_Pos               4                                                       /*!< HRPWM0 CSGTRC: D1SEC Position           */\r
+#define HRPWM0_CSGTRC_D1SEC_Msk               (0x01UL << HRPWM0_CSGTRC_D1SEC_Pos)                     /*!< HRPWM0 CSGTRC: D1SEC Mask               */\r
+#define HRPWM0_CSGTRC_D2SEC_Pos               8                                                       /*!< HRPWM0 CSGTRC: D2SEC Position           */\r
+#define HRPWM0_CSGTRC_D2SEC_Msk               (0x01UL << HRPWM0_CSGTRC_D2SEC_Pos)                     /*!< HRPWM0 CSGTRC: D2SEC Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSGTRSG  ------------------------------- */\r
+#define HRPWM0_CSGTRSG_D0STE_Pos              0                                                       /*!< HRPWM0 CSGTRSG: D0STE Position          */\r
+#define HRPWM0_CSGTRSG_D0STE_Msk              (0x01UL << HRPWM0_CSGTRSG_D0STE_Pos)                    /*!< HRPWM0 CSGTRSG: D0STE Mask              */\r
+#define HRPWM0_CSGTRSG_SW0ST_Pos              1                                                       /*!< HRPWM0 CSGTRSG: SW0ST Position          */\r
+#define HRPWM0_CSGTRSG_SW0ST_Msk              (0x01UL << HRPWM0_CSGTRSG_SW0ST_Pos)                    /*!< HRPWM0 CSGTRSG: SW0ST Mask              */\r
+#define HRPWM0_CSGTRSG_D1STE_Pos              4                                                       /*!< HRPWM0 CSGTRSG: D1STE Position          */\r
+#define HRPWM0_CSGTRSG_D1STE_Msk              (0x01UL << HRPWM0_CSGTRSG_D1STE_Pos)                    /*!< HRPWM0 CSGTRSG: D1STE Mask              */\r
+#define HRPWM0_CSGTRSG_SW1ST_Pos              5                                                       /*!< HRPWM0 CSGTRSG: SW1ST Position          */\r
+#define HRPWM0_CSGTRSG_SW1ST_Msk              (0x01UL << HRPWM0_CSGTRSG_SW1ST_Pos)                    /*!< HRPWM0 CSGTRSG: SW1ST Mask              */\r
+#define HRPWM0_CSGTRSG_D2STE_Pos              8                                                       /*!< HRPWM0 CSGTRSG: D2STE Position          */\r
+#define HRPWM0_CSGTRSG_D2STE_Msk              (0x01UL << HRPWM0_CSGTRSG_D2STE_Pos)                    /*!< HRPWM0 CSGTRSG: D2STE Mask              */\r
+#define HRPWM0_CSGTRSG_SW2ST_Pos              9                                                       /*!< HRPWM0 CSGTRSG: SW2ST Position          */\r
+#define HRPWM0_CSGTRSG_SW2ST_Msk              (0x01UL << HRPWM0_CSGTRSG_SW2ST_Pos)                    /*!< HRPWM0 CSGTRSG: SW2ST Mask              */\r
+\r
+/* --------------------------------  HRPWM0_HRCCFG  ------------------------------- */\r
+#define HRPWM0_HRCCFG_HRCPM_Pos               0                                                       /*!< HRPWM0 HRCCFG: HRCPM Position           */\r
+#define HRPWM0_HRCCFG_HRCPM_Msk               (0x01UL << HRPWM0_HRCCFG_HRCPM_Pos)                     /*!< HRPWM0 HRCCFG: HRCPM Mask               */\r
+#define HRPWM0_HRCCFG_HRC0E_Pos               4                                                       /*!< HRPWM0 HRCCFG: HRC0E Position           */\r
+#define HRPWM0_HRCCFG_HRC0E_Msk               (0x01UL << HRPWM0_HRCCFG_HRC0E_Pos)                     /*!< HRPWM0 HRCCFG: HRC0E Mask               */\r
+#define HRPWM0_HRCCFG_HRC1E_Pos               5                                                       /*!< HRPWM0 HRCCFG: HRC1E Position           */\r
+#define HRPWM0_HRCCFG_HRC1E_Msk               (0x01UL << HRPWM0_HRCCFG_HRC1E_Pos)                     /*!< HRPWM0 HRCCFG: HRC1E Mask               */\r
+#define HRPWM0_HRCCFG_HRC2E_Pos               6                                                       /*!< HRPWM0 HRCCFG: HRC2E Position           */\r
+#define HRPWM0_HRCCFG_HRC2E_Msk               (0x01UL << HRPWM0_HRCCFG_HRC2E_Pos)                     /*!< HRPWM0 HRCCFG: HRC2E Mask               */\r
+#define HRPWM0_HRCCFG_HRC3E_Pos               7                                                       /*!< HRPWM0 HRCCFG: HRC3E Position           */\r
+#define HRPWM0_HRCCFG_HRC3E_Msk               (0x01UL << HRPWM0_HRCCFG_HRC3E_Pos)                     /*!< HRPWM0 HRCCFG: HRC3E Mask               */\r
+#define HRPWM0_HRCCFG_CLKC_Pos                16                                                      /*!< HRPWM0 HRCCFG: CLKC Position            */\r
+#define HRPWM0_HRCCFG_CLKC_Msk                (0x07UL << HRPWM0_HRCCFG_CLKC_Pos)                      /*!< HRPWM0 HRCCFG: CLKC Mask                */\r
+#define HRPWM0_HRCCFG_LRC0E_Pos               20                                                      /*!< HRPWM0 HRCCFG: LRC0E Position           */\r
+#define HRPWM0_HRCCFG_LRC0E_Msk               (0x01UL << HRPWM0_HRCCFG_LRC0E_Pos)                     /*!< HRPWM0 HRCCFG: LRC0E Mask               */\r
+#define HRPWM0_HRCCFG_LRC1E_Pos               21                                                      /*!< HRPWM0 HRCCFG: LRC1E Position           */\r
+#define HRPWM0_HRCCFG_LRC1E_Msk               (0x01UL << HRPWM0_HRCCFG_LRC1E_Pos)                     /*!< HRPWM0 HRCCFG: LRC1E Mask               */\r
+#define HRPWM0_HRCCFG_LRC2E_Pos               22                                                      /*!< HRPWM0 HRCCFG: LRC2E Position           */\r
+#define HRPWM0_HRCCFG_LRC2E_Msk               (0x01UL << HRPWM0_HRCCFG_LRC2E_Pos)                     /*!< HRPWM0 HRCCFG: LRC2E Mask               */\r
+#define HRPWM0_HRCCFG_LRC3E_Pos               23                                                      /*!< HRPWM0 HRCCFG: LRC3E Position           */\r
+#define HRPWM0_HRCCFG_LRC3E_Msk               (0x01UL << HRPWM0_HRCCFG_LRC3E_Pos)                     /*!< HRPWM0 HRCCFG: LRC3E Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRCSTRG  ------------------------------- */\r
+#define HRPWM0_HRCSTRG_H0ES_Pos               0                                                       /*!< HRPWM0 HRCSTRG: H0ES Position           */\r
+#define HRPWM0_HRCSTRG_H0ES_Msk               (0x01UL << HRPWM0_HRCSTRG_H0ES_Pos)                     /*!< HRPWM0 HRCSTRG: H0ES Mask               */\r
+#define HRPWM0_HRCSTRG_H0DES_Pos              1                                                       /*!< HRPWM0 HRCSTRG: H0DES Position          */\r
+#define HRPWM0_HRCSTRG_H0DES_Msk              (0x01UL << HRPWM0_HRCSTRG_H0DES_Pos)                    /*!< HRPWM0 HRCSTRG: H0DES Mask              */\r
+#define HRPWM0_HRCSTRG_H1ES_Pos               4                                                       /*!< HRPWM0 HRCSTRG: H1ES Position           */\r
+#define HRPWM0_HRCSTRG_H1ES_Msk               (0x01UL << HRPWM0_HRCSTRG_H1ES_Pos)                     /*!< HRPWM0 HRCSTRG: H1ES Mask               */\r
+#define HRPWM0_HRCSTRG_H1DES_Pos              5                                                       /*!< HRPWM0 HRCSTRG: H1DES Position          */\r
+#define HRPWM0_HRCSTRG_H1DES_Msk              (0x01UL << HRPWM0_HRCSTRG_H1DES_Pos)                    /*!< HRPWM0 HRCSTRG: H1DES Mask              */\r
+#define HRPWM0_HRCSTRG_H2ES_Pos               8                                                       /*!< HRPWM0 HRCSTRG: H2ES Position           */\r
+#define HRPWM0_HRCSTRG_H2ES_Msk               (0x01UL << HRPWM0_HRCSTRG_H2ES_Pos)                     /*!< HRPWM0 HRCSTRG: H2ES Mask               */\r
+#define HRPWM0_HRCSTRG_H2DES_Pos              9                                                       /*!< HRPWM0 HRCSTRG: H2DES Position          */\r
+#define HRPWM0_HRCSTRG_H2DES_Msk              (0x01UL << HRPWM0_HRCSTRG_H2DES_Pos)                    /*!< HRPWM0 HRCSTRG: H2DES Mask              */\r
+#define HRPWM0_HRCSTRG_H3ES_Pos               12                                                      /*!< HRPWM0 HRCSTRG: H3ES Position           */\r
+#define HRPWM0_HRCSTRG_H3ES_Msk               (0x01UL << HRPWM0_HRCSTRG_H3ES_Pos)                     /*!< HRPWM0 HRCSTRG: H3ES Mask               */\r
+#define HRPWM0_HRCSTRG_H3DES_Pos              13                                                      /*!< HRPWM0 HRCSTRG: H3DES Position          */\r
+#define HRPWM0_HRCSTRG_H3DES_Msk              (0x01UL << HRPWM0_HRCSTRG_H3DES_Pos)                    /*!< HRPWM0 HRCSTRG: H3DES Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRCCTRG  ------------------------------- */\r
+#define HRPWM0_HRCCTRG_H0EC_Pos               0                                                       /*!< HRPWM0 HRCCTRG: H0EC Position           */\r
+#define HRPWM0_HRCCTRG_H0EC_Msk               (0x01UL << HRPWM0_HRCCTRG_H0EC_Pos)                     /*!< HRPWM0 HRCCTRG: H0EC Mask               */\r
+#define HRPWM0_HRCCTRG_H0DEC_Pos              1                                                       /*!< HRPWM0 HRCCTRG: H0DEC Position          */\r
+#define HRPWM0_HRCCTRG_H0DEC_Msk              (0x01UL << HRPWM0_HRCCTRG_H0DEC_Pos)                    /*!< HRPWM0 HRCCTRG: H0DEC Mask              */\r
+#define HRPWM0_HRCCTRG_H1EC_Pos               4                                                       /*!< HRPWM0 HRCCTRG: H1EC Position           */\r
+#define HRPWM0_HRCCTRG_H1EC_Msk               (0x01UL << HRPWM0_HRCCTRG_H1EC_Pos)                     /*!< HRPWM0 HRCCTRG: H1EC Mask               */\r
+#define HRPWM0_HRCCTRG_H1DEC_Pos              5                                                       /*!< HRPWM0 HRCCTRG: H1DEC Position          */\r
+#define HRPWM0_HRCCTRG_H1DEC_Msk              (0x01UL << HRPWM0_HRCCTRG_H1DEC_Pos)                    /*!< HRPWM0 HRCCTRG: H1DEC Mask              */\r
+#define HRPWM0_HRCCTRG_H2CEC_Pos              8                                                       /*!< HRPWM0 HRCCTRG: H2CEC Position          */\r
+#define HRPWM0_HRCCTRG_H2CEC_Msk              (0x01UL << HRPWM0_HRCCTRG_H2CEC_Pos)                    /*!< HRPWM0 HRCCTRG: H2CEC Mask              */\r
+#define HRPWM0_HRCCTRG_H2DEC_Pos              9                                                       /*!< HRPWM0 HRCCTRG: H2DEC Position          */\r
+#define HRPWM0_HRCCTRG_H2DEC_Msk              (0x01UL << HRPWM0_HRCCTRG_H2DEC_Pos)                    /*!< HRPWM0 HRCCTRG: H2DEC Mask              */\r
+#define HRPWM0_HRCCTRG_H3EC_Pos               12                                                      /*!< HRPWM0 HRCCTRG: H3EC Position           */\r
+#define HRPWM0_HRCCTRG_H3EC_Msk               (0x01UL << HRPWM0_HRCCTRG_H3EC_Pos)                     /*!< HRPWM0 HRCCTRG: H3EC Mask               */\r
+#define HRPWM0_HRCCTRG_H3DEC_Pos              13                                                      /*!< HRPWM0 HRCCTRG: H3DEC Position          */\r
+#define HRPWM0_HRCCTRG_H3DEC_Msk              (0x01UL << HRPWM0_HRCCTRG_H3DEC_Pos)                    /*!< HRPWM0 HRCCTRG: H3DEC Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRCSTSG  ------------------------------- */\r
+#define HRPWM0_HRCSTSG_H0STE_Pos              0                                                       /*!< HRPWM0 HRCSTSG: H0STE Position          */\r
+#define HRPWM0_HRCSTSG_H0STE_Msk              (0x01UL << HRPWM0_HRCSTSG_H0STE_Pos)                    /*!< HRPWM0 HRCSTSG: H0STE Mask              */\r
+#define HRPWM0_HRCSTSG_H0DSTE_Pos             1                                                       /*!< HRPWM0 HRCSTSG: H0DSTE Position         */\r
+#define HRPWM0_HRCSTSG_H0DSTE_Msk             (0x01UL << HRPWM0_HRCSTSG_H0DSTE_Pos)                   /*!< HRPWM0 HRCSTSG: H0DSTE Mask             */\r
+#define HRPWM0_HRCSTSG_H1STE_Pos              4                                                       /*!< HRPWM0 HRCSTSG: H1STE Position          */\r
+#define HRPWM0_HRCSTSG_H1STE_Msk              (0x01UL << HRPWM0_HRCSTSG_H1STE_Pos)                    /*!< HRPWM0 HRCSTSG: H1STE Mask              */\r
+#define HRPWM0_HRCSTSG_H1DSTE_Pos             5                                                       /*!< HRPWM0 HRCSTSG: H1DSTE Position         */\r
+#define HRPWM0_HRCSTSG_H1DSTE_Msk             (0x01UL << HRPWM0_HRCSTSG_H1DSTE_Pos)                   /*!< HRPWM0 HRCSTSG: H1DSTE Mask             */\r
+#define HRPWM0_HRCSTSG_H2STE_Pos              8                                                       /*!< HRPWM0 HRCSTSG: H2STE Position          */\r
+#define HRPWM0_HRCSTSG_H2STE_Msk              (0x01UL << HRPWM0_HRCSTSG_H2STE_Pos)                    /*!< HRPWM0 HRCSTSG: H2STE Mask              */\r
+#define HRPWM0_HRCSTSG_H2DSTE_Pos             9                                                       /*!< HRPWM0 HRCSTSG: H2DSTE Position         */\r
+#define HRPWM0_HRCSTSG_H2DSTE_Msk             (0x01UL << HRPWM0_HRCSTSG_H2DSTE_Pos)                   /*!< HRPWM0 HRCSTSG: H2DSTE Mask             */\r
+#define HRPWM0_HRCSTSG_H3STE_Pos              12                                                      /*!< HRPWM0 HRCSTSG: H3STE Position          */\r
+#define HRPWM0_HRCSTSG_H3STE_Msk              (0x01UL << HRPWM0_HRCSTSG_H3STE_Pos)                    /*!< HRPWM0 HRCSTSG: H3STE Mask              */\r
+#define HRPWM0_HRCSTSG_H3DSTE_Pos             13                                                      /*!< HRPWM0 HRCSTSG: H3DSTE Position         */\r
+#define HRPWM0_HRCSTSG_H3DSTE_Msk             (0x01UL << HRPWM0_HRCSTSG_H3DSTE_Pos)                   /*!< HRPWM0 HRCSTSG: H3DSTE Mask             */\r
+\r
+/* --------------------------------  HRPWM0_HRGHRS  ------------------------------- */\r
+#define HRPWM0_HRGHRS_HRGR_Pos                0                                                       /*!< HRPWM0 HRGHRS: HRGR Position            */\r
+#define HRPWM0_HRGHRS_HRGR_Msk                (0x01UL << HRPWM0_HRGHRS_HRGR_Pos)                      /*!< HRPWM0 HRGHRS: HRGR Mask                */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       Group 'HRPWM0_CSG' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_CSG_DCI  ------------------------------- */\r
+#define HRPWM0_CSG_DCI_SVIS_Pos               0                                                       /*!< HRPWM0_CSG DCI: SVIS Position           */\r
+#define HRPWM0_CSG_DCI_SVIS_Msk               (0x0fUL << HRPWM0_CSG_DCI_SVIS_Pos)                     /*!< HRPWM0_CSG DCI: SVIS Mask               */\r
+#define HRPWM0_CSG_DCI_STRIS_Pos              4                                                       /*!< HRPWM0_CSG DCI: STRIS Position          */\r
+#define HRPWM0_CSG_DCI_STRIS_Msk              (0x0fUL << HRPWM0_CSG_DCI_STRIS_Pos)                    /*!< HRPWM0_CSG DCI: STRIS Mask              */\r
+#define HRPWM0_CSG_DCI_STPIS_Pos              8                                                       /*!< HRPWM0_CSG DCI: STPIS Position          */\r
+#define HRPWM0_CSG_DCI_STPIS_Msk              (0x0fUL << HRPWM0_CSG_DCI_STPIS_Pos)                    /*!< HRPWM0_CSG DCI: STPIS Mask              */\r
+#define HRPWM0_CSG_DCI_TRGIS_Pos              12                                                      /*!< HRPWM0_CSG DCI: TRGIS Position          */\r
+#define HRPWM0_CSG_DCI_TRGIS_Msk              (0x0fUL << HRPWM0_CSG_DCI_TRGIS_Pos)                    /*!< HRPWM0_CSG DCI: TRGIS Mask              */\r
+#define HRPWM0_CSG_DCI_STIS_Pos               16                                                      /*!< HRPWM0_CSG DCI: STIS Position           */\r
+#define HRPWM0_CSG_DCI_STIS_Msk               (0x0fUL << HRPWM0_CSG_DCI_STIS_Pos)                     /*!< HRPWM0_CSG DCI: STIS Mask               */\r
+#define HRPWM0_CSG_DCI_SCS_Pos                20                                                      /*!< HRPWM0_CSG DCI: SCS Position            */\r
+#define HRPWM0_CSG_DCI_SCS_Msk                (0x03UL << HRPWM0_CSG_DCI_SCS_Pos)                      /*!< HRPWM0_CSG DCI: SCS Mask                */\r
+\r
+/* -------------------------------  HRPWM0_CSG_IES  ------------------------------- */\r
+#define HRPWM0_CSG_IES_SVLS_Pos               0                                                       /*!< HRPWM0_CSG IES: SVLS Position           */\r
+#define HRPWM0_CSG_IES_SVLS_Msk               (0x03UL << HRPWM0_CSG_IES_SVLS_Pos)                     /*!< HRPWM0_CSG IES: SVLS Mask               */\r
+#define HRPWM0_CSG_IES_STRES_Pos              2                                                       /*!< HRPWM0_CSG IES: STRES Position          */\r
+#define HRPWM0_CSG_IES_STRES_Msk              (0x03UL << HRPWM0_CSG_IES_STRES_Pos)                    /*!< HRPWM0_CSG IES: STRES Mask              */\r
+#define HRPWM0_CSG_IES_STPES_Pos              4                                                       /*!< HRPWM0_CSG IES: STPES Position          */\r
+#define HRPWM0_CSG_IES_STPES_Msk              (0x03UL << HRPWM0_CSG_IES_STPES_Pos)                    /*!< HRPWM0_CSG IES: STPES Mask              */\r
+#define HRPWM0_CSG_IES_TRGES_Pos              6                                                       /*!< HRPWM0_CSG IES: TRGES Position          */\r
+#define HRPWM0_CSG_IES_TRGES_Msk              (0x03UL << HRPWM0_CSG_IES_TRGES_Pos)                    /*!< HRPWM0_CSG IES: TRGES Mask              */\r
+#define HRPWM0_CSG_IES_STES_Pos               8                                                       /*!< HRPWM0_CSG IES: STES Position           */\r
+#define HRPWM0_CSG_IES_STES_Msk               (0x03UL << HRPWM0_CSG_IES_STES_Pos)                     /*!< HRPWM0_CSG IES: STES Mask               */\r
+\r
+/* --------------------------------  HRPWM0_CSG_SC  ------------------------------- */\r
+#define HRPWM0_CSG_SC_PSRM_Pos                0                                                       /*!< HRPWM0_CSG SC: PSRM Position            */\r
+#define HRPWM0_CSG_SC_PSRM_Msk                (0x03UL << HRPWM0_CSG_SC_PSRM_Pos)                      /*!< HRPWM0_CSG SC: PSRM Mask                */\r
+#define HRPWM0_CSG_SC_PSTM_Pos                2                                                       /*!< HRPWM0_CSG SC: PSTM Position            */\r
+#define HRPWM0_CSG_SC_PSTM_Msk                (0x03UL << HRPWM0_CSG_SC_PSTM_Pos)                      /*!< HRPWM0_CSG SC: PSTM Mask                */\r
+#define HRPWM0_CSG_SC_FPD_Pos                 4                                                       /*!< HRPWM0_CSG SC: FPD Position             */\r
+#define HRPWM0_CSG_SC_FPD_Msk                 (0x01UL << HRPWM0_CSG_SC_FPD_Pos)                       /*!< HRPWM0_CSG SC: FPD Mask                 */\r
+#define HRPWM0_CSG_SC_PSV_Pos                 5                                                       /*!< HRPWM0_CSG SC: PSV Position             */\r
+#define HRPWM0_CSG_SC_PSV_Msk                 (0x03UL << HRPWM0_CSG_SC_PSV_Pos)                       /*!< HRPWM0_CSG SC: PSV Mask                 */\r
+#define HRPWM0_CSG_SC_SCM_Pos                 8                                                       /*!< HRPWM0_CSG SC: SCM Position             */\r
+#define HRPWM0_CSG_SC_SCM_Msk                 (0x03UL << HRPWM0_CSG_SC_SCM_Pos)                       /*!< HRPWM0_CSG SC: SCM Mask                 */\r
+#define HRPWM0_CSG_SC_SSRM_Pos                10                                                      /*!< HRPWM0_CSG SC: SSRM Position            */\r
+#define HRPWM0_CSG_SC_SSRM_Msk                (0x03UL << HRPWM0_CSG_SC_SSRM_Pos)                      /*!< HRPWM0_CSG SC: SSRM Mask                */\r
+#define HRPWM0_CSG_SC_SSTM_Pos                12                                                      /*!< HRPWM0_CSG SC: SSTM Position            */\r
+#define HRPWM0_CSG_SC_SSTM_Msk                (0x03UL << HRPWM0_CSG_SC_SSTM_Pos)                      /*!< HRPWM0_CSG SC: SSTM Mask                */\r
+#define HRPWM0_CSG_SC_SVSC_Pos                14                                                      /*!< HRPWM0_CSG SC: SVSC Position            */\r
+#define HRPWM0_CSG_SC_SVSC_Msk                (0x03UL << HRPWM0_CSG_SC_SVSC_Pos)                      /*!< HRPWM0_CSG SC: SVSC Mask                */\r
+#define HRPWM0_CSG_SC_SWSM_Pos                16                                                      /*!< HRPWM0_CSG SC: SWSM Position            */\r
+#define HRPWM0_CSG_SC_SWSM_Msk                (0x03UL << HRPWM0_CSG_SC_SWSM_Pos)                      /*!< HRPWM0_CSG SC: SWSM Mask                */\r
+#define HRPWM0_CSG_SC_GCFG_Pos                18                                                      /*!< HRPWM0_CSG SC: GCFG Position            */\r
+#define HRPWM0_CSG_SC_GCFG_Msk                (0x03UL << HRPWM0_CSG_SC_GCFG_Pos)                      /*!< HRPWM0_CSG SC: GCFG Mask                */\r
+#define HRPWM0_CSG_SC_IST_Pos                 20                                                      /*!< HRPWM0_CSG SC: IST Position             */\r
+#define HRPWM0_CSG_SC_IST_Msk                 (0x01UL << HRPWM0_CSG_SC_IST_Pos)                       /*!< HRPWM0_CSG SC: IST Mask                 */\r
+#define HRPWM0_CSG_SC_PSE_Pos                 21                                                      /*!< HRPWM0_CSG SC: PSE Position             */\r
+#define HRPWM0_CSG_SC_PSE_Msk                 (0x01UL << HRPWM0_CSG_SC_PSE_Pos)                       /*!< HRPWM0_CSG SC: PSE Mask                 */\r
+#define HRPWM0_CSG_SC_PSWM_Pos                24                                                      /*!< HRPWM0_CSG SC: PSWM Position            */\r
+#define HRPWM0_CSG_SC_PSWM_Msk                (0x03UL << HRPWM0_CSG_SC_PSWM_Pos)                      /*!< HRPWM0_CSG SC: PSWM Mask                */\r
+\r
+/* --------------------------------  HRPWM0_CSG_PC  ------------------------------- */\r
+#define HRPWM0_CSG_PC_PSWV_Pos                0                                                       /*!< HRPWM0_CSG PC: PSWV Position            */\r
+#define HRPWM0_CSG_PC_PSWV_Msk                (0x3fUL << HRPWM0_CSG_PC_PSWV_Pos)                      /*!< HRPWM0_CSG PC: PSWV Mask                */\r
+\r
+/* -------------------------------  HRPWM0_CSG_DSV1  ------------------------------ */\r
+#define HRPWM0_CSG_DSV1_DSV1_Pos              0                                                       /*!< HRPWM0_CSG DSV1: DSV1 Position          */\r
+#define HRPWM0_CSG_DSV1_DSV1_Msk              (0x000003ffUL << HRPWM0_CSG_DSV1_DSV1_Pos)              /*!< HRPWM0_CSG DSV1: DSV1 Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG_DSV2  ------------------------------ */\r
+#define HRPWM0_CSG_DSV2_DSV2_Pos              0                                                       /*!< HRPWM0_CSG DSV2: DSV2 Position          */\r
+#define HRPWM0_CSG_DSV2_DSV2_Msk              (0x000003ffUL << HRPWM0_CSG_DSV2_DSV2_Pos)              /*!< HRPWM0_CSG DSV2: DSV2 Mask              */\r
+\r
+/* ------------------------------  HRPWM0_CSG_SDSV1  ------------------------------ */\r
+#define HRPWM0_CSG_SDSV1_SDSV1_Pos            0                                                       /*!< HRPWM0_CSG SDSV1: SDSV1 Position        */\r
+#define HRPWM0_CSG_SDSV1_SDSV1_Msk            (0x000003ffUL << HRPWM0_CSG_SDSV1_SDSV1_Pos)            /*!< HRPWM0_CSG SDSV1: SDSV1 Mask            */\r
+\r
+/* -------------------------------  HRPWM0_CSG_SPC  ------------------------------- */\r
+#define HRPWM0_CSG_SPC_SPSWV_Pos              0                                                       /*!< HRPWM0_CSG SPC: SPSWV Position          */\r
+#define HRPWM0_CSG_SPC_SPSWV_Msk              (0x3fUL << HRPWM0_CSG_SPC_SPSWV_Pos)                    /*!< HRPWM0_CSG SPC: SPSWV Mask              */\r
+\r
+/* --------------------------------  HRPWM0_CSG_CC  ------------------------------- */\r
+#define HRPWM0_CSG_CC_IBS_Pos                 0                                                       /*!< HRPWM0_CSG CC: IBS Position             */\r
+#define HRPWM0_CSG_CC_IBS_Msk                 (0x0fUL << HRPWM0_CSG_CC_IBS_Pos)                       /*!< HRPWM0_CSG CC: IBS Mask                 */\r
+#define HRPWM0_CSG_CC_IMCS_Pos                8                                                       /*!< HRPWM0_CSG CC: IMCS Position            */\r
+#define HRPWM0_CSG_CC_IMCS_Msk                (0x01UL << HRPWM0_CSG_CC_IMCS_Pos)                      /*!< HRPWM0_CSG CC: IMCS Mask                */\r
+#define HRPWM0_CSG_CC_IMCC_Pos                9                                                       /*!< HRPWM0_CSG CC: IMCC Position            */\r
+#define HRPWM0_CSG_CC_IMCC_Msk                (0x03UL << HRPWM0_CSG_CC_IMCC_Pos)                      /*!< HRPWM0_CSG CC: IMCC Mask                */\r
+#define HRPWM0_CSG_CC_ESE_Pos                 11                                                      /*!< HRPWM0_CSG CC: ESE Position             */\r
+#define HRPWM0_CSG_CC_ESE_Msk                 (0x01UL << HRPWM0_CSG_CC_ESE_Pos)                       /*!< HRPWM0_CSG CC: ESE Mask                 */\r
+#define HRPWM0_CSG_CC_OIE_Pos                 12                                                      /*!< HRPWM0_CSG CC: OIE Position             */\r
+#define HRPWM0_CSG_CC_OIE_Msk                 (0x01UL << HRPWM0_CSG_CC_OIE_Pos)                       /*!< HRPWM0_CSG CC: OIE Mask                 */\r
+#define HRPWM0_CSG_CC_OSE_Pos                 13                                                      /*!< HRPWM0_CSG CC: OSE Position             */\r
+#define HRPWM0_CSG_CC_OSE_Msk                 (0x01UL << HRPWM0_CSG_CC_OSE_Pos)                       /*!< HRPWM0_CSG CC: OSE Mask                 */\r
+#define HRPWM0_CSG_CC_BLMC_Pos                14                                                      /*!< HRPWM0_CSG CC: BLMC Position            */\r
+#define HRPWM0_CSG_CC_BLMC_Msk                (0x03UL << HRPWM0_CSG_CC_BLMC_Pos)                      /*!< HRPWM0_CSG CC: BLMC Mask                */\r
+#define HRPWM0_CSG_CC_EBE_Pos                 16                                                      /*!< HRPWM0_CSG CC: EBE Position             */\r
+#define HRPWM0_CSG_CC_EBE_Msk                 (0x01UL << HRPWM0_CSG_CC_EBE_Pos)                       /*!< HRPWM0_CSG CC: EBE Mask                 */\r
+#define HRPWM0_CSG_CC_COFE_Pos                17                                                      /*!< HRPWM0_CSG CC: COFE Position            */\r
+#define HRPWM0_CSG_CC_COFE_Msk                (0x01UL << HRPWM0_CSG_CC_COFE_Pos)                      /*!< HRPWM0_CSG CC: COFE Mask                */\r
+#define HRPWM0_CSG_CC_COFM_Pos                18                                                      /*!< HRPWM0_CSG CC: COFM Position            */\r
+#define HRPWM0_CSG_CC_COFM_Msk                (0x0fUL << HRPWM0_CSG_CC_COFM_Pos)                      /*!< HRPWM0_CSG CC: COFM Mask                */\r
+#define HRPWM0_CSG_CC_COFC_Pos                24                                                      /*!< HRPWM0_CSG CC: COFC Position            */\r
+#define HRPWM0_CSG_CC_COFC_Msk                (0x03UL << HRPWM0_CSG_CC_COFC_Pos)                      /*!< HRPWM0_CSG CC: COFC Mask                */\r
+\r
+/* -------------------------------  HRPWM0_CSG_PLC  ------------------------------- */\r
+#define HRPWM0_CSG_PLC_IPLS_Pos               0                                                       /*!< HRPWM0_CSG PLC: IPLS Position           */\r
+#define HRPWM0_CSG_PLC_IPLS_Msk               (0x0fUL << HRPWM0_CSG_PLC_IPLS_Pos)                     /*!< HRPWM0_CSG PLC: IPLS Mask               */\r
+#define HRPWM0_CSG_PLC_PLCL_Pos               8                                                       /*!< HRPWM0_CSG PLC: PLCL Position           */\r
+#define HRPWM0_CSG_PLC_PLCL_Msk               (0x03UL << HRPWM0_CSG_PLC_PLCL_Pos)                     /*!< HRPWM0_CSG PLC: PLCL Mask               */\r
+#define HRPWM0_CSG_PLC_PSL_Pos                10                                                      /*!< HRPWM0_CSG PLC: PSL Position            */\r
+#define HRPWM0_CSG_PLC_PSL_Msk                (0x01UL << HRPWM0_CSG_PLC_PSL_Pos)                      /*!< HRPWM0_CSG PLC: PSL Mask                */\r
+#define HRPWM0_CSG_PLC_PLSW_Pos               11                                                      /*!< HRPWM0_CSG PLC: PLSW Position           */\r
+#define HRPWM0_CSG_PLC_PLSW_Msk               (0x01UL << HRPWM0_CSG_PLC_PLSW_Pos)                     /*!< HRPWM0_CSG PLC: PLSW Mask               */\r
+#define HRPWM0_CSG_PLC_PLEC_Pos               12                                                      /*!< HRPWM0_CSG PLC: PLEC Position           */\r
+#define HRPWM0_CSG_PLC_PLEC_Msk               (0x03UL << HRPWM0_CSG_PLC_PLEC_Pos)                     /*!< HRPWM0_CSG PLC: PLEC Mask               */\r
+#define HRPWM0_CSG_PLC_PLXC_Pos               14                                                      /*!< HRPWM0_CSG PLC: PLXC Position           */\r
+#define HRPWM0_CSG_PLC_PLXC_Msk               (0x03UL << HRPWM0_CSG_PLC_PLXC_Pos)                     /*!< HRPWM0_CSG PLC: PLXC Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG_BLV  ------------------------------- */\r
+#define HRPWM0_CSG_BLV_BLV_Pos                0                                                       /*!< HRPWM0_CSG BLV: BLV Position            */\r
+#define HRPWM0_CSG_BLV_BLV_Msk                (0x000000ffUL << HRPWM0_CSG_BLV_BLV_Pos)                /*!< HRPWM0_CSG BLV: BLV Mask                */\r
+\r
+/* -------------------------------  HRPWM0_CSG_SRE  ------------------------------- */\r
+#define HRPWM0_CSG_SRE_VLS1E_Pos              0                                                       /*!< HRPWM0_CSG SRE: VLS1E Position          */\r
+#define HRPWM0_CSG_SRE_VLS1E_Msk              (0x01UL << HRPWM0_CSG_SRE_VLS1E_Pos)                    /*!< HRPWM0_CSG SRE: VLS1E Mask              */\r
+#define HRPWM0_CSG_SRE_VLS2E_Pos              1                                                       /*!< HRPWM0_CSG SRE: VLS2E Position          */\r
+#define HRPWM0_CSG_SRE_VLS2E_Msk              (0x01UL << HRPWM0_CSG_SRE_VLS2E_Pos)                    /*!< HRPWM0_CSG SRE: VLS2E Mask              */\r
+#define HRPWM0_CSG_SRE_TRGSE_Pos              2                                                       /*!< HRPWM0_CSG SRE: TRGSE Position          */\r
+#define HRPWM0_CSG_SRE_TRGSE_Msk              (0x01UL << HRPWM0_CSG_SRE_TRGSE_Pos)                    /*!< HRPWM0_CSG SRE: TRGSE Mask              */\r
+#define HRPWM0_CSG_SRE_STRSE_Pos              3                                                       /*!< HRPWM0_CSG SRE: STRSE Position          */\r
+#define HRPWM0_CSG_SRE_STRSE_Msk              (0x01UL << HRPWM0_CSG_SRE_STRSE_Pos)                    /*!< HRPWM0_CSG SRE: STRSE Mask              */\r
+#define HRPWM0_CSG_SRE_STPSE_Pos              4                                                       /*!< HRPWM0_CSG SRE: STPSE Position          */\r
+#define HRPWM0_CSG_SRE_STPSE_Msk              (0x01UL << HRPWM0_CSG_SRE_STPSE_Pos)                    /*!< HRPWM0_CSG SRE: STPSE Mask              */\r
+#define HRPWM0_CSG_SRE_STDE_Pos               5                                                       /*!< HRPWM0_CSG SRE: STDE Position           */\r
+#define HRPWM0_CSG_SRE_STDE_Msk               (0x01UL << HRPWM0_CSG_SRE_STDE_Pos)                     /*!< HRPWM0_CSG SRE: STDE Mask               */\r
+#define HRPWM0_CSG_SRE_CRSE_Pos               6                                                       /*!< HRPWM0_CSG SRE: CRSE Position           */\r
+#define HRPWM0_CSG_SRE_CRSE_Msk               (0x01UL << HRPWM0_CSG_SRE_CRSE_Pos)                     /*!< HRPWM0_CSG SRE: CRSE Mask               */\r
+#define HRPWM0_CSG_SRE_CFSE_Pos               7                                                       /*!< HRPWM0_CSG SRE: CFSE Position           */\r
+#define HRPWM0_CSG_SRE_CFSE_Msk               (0x01UL << HRPWM0_CSG_SRE_CFSE_Pos)                     /*!< HRPWM0_CSG SRE: CFSE Mask               */\r
+#define HRPWM0_CSG_SRE_CSEE_Pos               8                                                       /*!< HRPWM0_CSG SRE: CSEE Position           */\r
+#define HRPWM0_CSG_SRE_CSEE_Msk               (0x01UL << HRPWM0_CSG_SRE_CSEE_Pos)                     /*!< HRPWM0_CSG SRE: CSEE Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG_SRS  ------------------------------- */\r
+#define HRPWM0_CSG_SRS_VLS1S_Pos              0                                                       /*!< HRPWM0_CSG SRS: VLS1S Position          */\r
+#define HRPWM0_CSG_SRS_VLS1S_Msk              (0x03UL << HRPWM0_CSG_SRS_VLS1S_Pos)                    /*!< HRPWM0_CSG SRS: VLS1S Mask              */\r
+#define HRPWM0_CSG_SRS_VLS2S_Pos              2                                                       /*!< HRPWM0_CSG SRS: VLS2S Position          */\r
+#define HRPWM0_CSG_SRS_VLS2S_Msk              (0x03UL << HRPWM0_CSG_SRS_VLS2S_Pos)                    /*!< HRPWM0_CSG SRS: VLS2S Mask              */\r
+#define HRPWM0_CSG_SRS_TRLS_Pos               4                                                       /*!< HRPWM0_CSG SRS: TRLS Position           */\r
+#define HRPWM0_CSG_SRS_TRLS_Msk               (0x03UL << HRPWM0_CSG_SRS_TRLS_Pos)                     /*!< HRPWM0_CSG SRS: TRLS Mask               */\r
+#define HRPWM0_CSG_SRS_SSLS_Pos               6                                                       /*!< HRPWM0_CSG SRS: SSLS Position           */\r
+#define HRPWM0_CSG_SRS_SSLS_Msk               (0x03UL << HRPWM0_CSG_SRS_SSLS_Pos)                     /*!< HRPWM0_CSG SRS: SSLS Mask               */\r
+#define HRPWM0_CSG_SRS_STLS_Pos               8                                                       /*!< HRPWM0_CSG SRS: STLS Position           */\r
+#define HRPWM0_CSG_SRS_STLS_Msk               (0x03UL << HRPWM0_CSG_SRS_STLS_Pos)                     /*!< HRPWM0_CSG SRS: STLS Mask               */\r
+#define HRPWM0_CSG_SRS_CRFLS_Pos              10                                                      /*!< HRPWM0_CSG SRS: CRFLS Position          */\r
+#define HRPWM0_CSG_SRS_CRFLS_Msk              (0x03UL << HRPWM0_CSG_SRS_CRFLS_Pos)                    /*!< HRPWM0_CSG SRS: CRFLS Mask              */\r
+#define HRPWM0_CSG_SRS_CSLS_Pos               12                                                      /*!< HRPWM0_CSG SRS: CSLS Position           */\r
+#define HRPWM0_CSG_SRS_CSLS_Msk               (0x03UL << HRPWM0_CSG_SRS_CSLS_Pos)                     /*!< HRPWM0_CSG SRS: CSLS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG_SWS  ------------------------------- */\r
+#define HRPWM0_CSG_SWS_SVLS1_Pos              0                                                       /*!< HRPWM0_CSG SWS: SVLS1 Position          */\r
+#define HRPWM0_CSG_SWS_SVLS1_Msk              (0x01UL << HRPWM0_CSG_SWS_SVLS1_Pos)                    /*!< HRPWM0_CSG SWS: SVLS1 Mask              */\r
+#define HRPWM0_CSG_SWS_SVLS2_Pos              1                                                       /*!< HRPWM0_CSG SWS: SVLS2 Position          */\r
+#define HRPWM0_CSG_SWS_SVLS2_Msk              (0x01UL << HRPWM0_CSG_SWS_SVLS2_Pos)                    /*!< HRPWM0_CSG SWS: SVLS2 Mask              */\r
+#define HRPWM0_CSG_SWS_STRGS_Pos              2                                                       /*!< HRPWM0_CSG SWS: STRGS Position          */\r
+#define HRPWM0_CSG_SWS_STRGS_Msk              (0x01UL << HRPWM0_CSG_SWS_STRGS_Pos)                    /*!< HRPWM0_CSG SWS: STRGS Mask              */\r
+#define HRPWM0_CSG_SWS_SSTRS_Pos              3                                                       /*!< HRPWM0_CSG SWS: SSTRS Position          */\r
+#define HRPWM0_CSG_SWS_SSTRS_Msk              (0x01UL << HRPWM0_CSG_SWS_SSTRS_Pos)                    /*!< HRPWM0_CSG SWS: SSTRS Mask              */\r
+#define HRPWM0_CSG_SWS_SSTPS_Pos              4                                                       /*!< HRPWM0_CSG SWS: SSTPS Position          */\r
+#define HRPWM0_CSG_SWS_SSTPS_Msk              (0x01UL << HRPWM0_CSG_SWS_SSTPS_Pos)                    /*!< HRPWM0_CSG SWS: SSTPS Mask              */\r
+#define HRPWM0_CSG_SWS_SSTD_Pos               5                                                       /*!< HRPWM0_CSG SWS: SSTD Position           */\r
+#define HRPWM0_CSG_SWS_SSTD_Msk               (0x01UL << HRPWM0_CSG_SWS_SSTD_Pos)                     /*!< HRPWM0_CSG SWS: SSTD Mask               */\r
+#define HRPWM0_CSG_SWS_SCRS_Pos               6                                                       /*!< HRPWM0_CSG SWS: SCRS Position           */\r
+#define HRPWM0_CSG_SWS_SCRS_Msk               (0x01UL << HRPWM0_CSG_SWS_SCRS_Pos)                     /*!< HRPWM0_CSG SWS: SCRS Mask               */\r
+#define HRPWM0_CSG_SWS_SCFS_Pos               7                                                       /*!< HRPWM0_CSG SWS: SCFS Position           */\r
+#define HRPWM0_CSG_SWS_SCFS_Msk               (0x01UL << HRPWM0_CSG_SWS_SCFS_Pos)                     /*!< HRPWM0_CSG SWS: SCFS Mask               */\r
+#define HRPWM0_CSG_SWS_SCSS_Pos               8                                                       /*!< HRPWM0_CSG SWS: SCSS Position           */\r
+#define HRPWM0_CSG_SWS_SCSS_Msk               (0x01UL << HRPWM0_CSG_SWS_SCSS_Pos)                     /*!< HRPWM0_CSG SWS: SCSS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG_SWC  ------------------------------- */\r
+#define HRPWM0_CSG_SWC_CVLS1_Pos              0                                                       /*!< HRPWM0_CSG SWC: CVLS1 Position          */\r
+#define HRPWM0_CSG_SWC_CVLS1_Msk              (0x01UL << HRPWM0_CSG_SWC_CVLS1_Pos)                    /*!< HRPWM0_CSG SWC: CVLS1 Mask              */\r
+#define HRPWM0_CSG_SWC_CVLS2_Pos              1                                                       /*!< HRPWM0_CSG SWC: CVLS2 Position          */\r
+#define HRPWM0_CSG_SWC_CVLS2_Msk              (0x01UL << HRPWM0_CSG_SWC_CVLS2_Pos)                    /*!< HRPWM0_CSG SWC: CVLS2 Mask              */\r
+#define HRPWM0_CSG_SWC_CTRGS_Pos              2                                                       /*!< HRPWM0_CSG SWC: CTRGS Position          */\r
+#define HRPWM0_CSG_SWC_CTRGS_Msk              (0x01UL << HRPWM0_CSG_SWC_CTRGS_Pos)                    /*!< HRPWM0_CSG SWC: CTRGS Mask              */\r
+#define HRPWM0_CSG_SWC_CSTRS_Pos              3                                                       /*!< HRPWM0_CSG SWC: CSTRS Position          */\r
+#define HRPWM0_CSG_SWC_CSTRS_Msk              (0x01UL << HRPWM0_CSG_SWC_CSTRS_Pos)                    /*!< HRPWM0_CSG SWC: CSTRS Mask              */\r
+#define HRPWM0_CSG_SWC_CSTPS_Pos              4                                                       /*!< HRPWM0_CSG SWC: CSTPS Position          */\r
+#define HRPWM0_CSG_SWC_CSTPS_Msk              (0x01UL << HRPWM0_CSG_SWC_CSTPS_Pos)                    /*!< HRPWM0_CSG SWC: CSTPS Mask              */\r
+#define HRPWM0_CSG_SWC_CSTD_Pos               5                                                       /*!< HRPWM0_CSG SWC: CSTD Position           */\r
+#define HRPWM0_CSG_SWC_CSTD_Msk               (0x01UL << HRPWM0_CSG_SWC_CSTD_Pos)                     /*!< HRPWM0_CSG SWC: CSTD Mask               */\r
+#define HRPWM0_CSG_SWC_CCRS_Pos               6                                                       /*!< HRPWM0_CSG SWC: CCRS Position           */\r
+#define HRPWM0_CSG_SWC_CCRS_Msk               (0x01UL << HRPWM0_CSG_SWC_CCRS_Pos)                     /*!< HRPWM0_CSG SWC: CCRS Mask               */\r
+#define HRPWM0_CSG_SWC_CCFS_Pos               7                                                       /*!< HRPWM0_CSG SWC: CCFS Position           */\r
+#define HRPWM0_CSG_SWC_CCFS_Msk               (0x01UL << HRPWM0_CSG_SWC_CCFS_Pos)                     /*!< HRPWM0_CSG SWC: CCFS Mask               */\r
+#define HRPWM0_CSG_SWC_CCSS_Pos               8                                                       /*!< HRPWM0_CSG SWC: CCSS Position           */\r
+#define HRPWM0_CSG_SWC_CCSS_Msk               (0x01UL << HRPWM0_CSG_SWC_CCSS_Pos)                     /*!< HRPWM0_CSG SWC: CCSS Mask               */\r
+\r
+/* ------------------------------  HRPWM0_CSG_ISTAT  ------------------------------ */\r
+#define HRPWM0_CSG_ISTAT_VLS1S_Pos            0                                                       /*!< HRPWM0_CSG ISTAT: VLS1S Position        */\r
+#define HRPWM0_CSG_ISTAT_VLS1S_Msk            (0x01UL << HRPWM0_CSG_ISTAT_VLS1S_Pos)                  /*!< HRPWM0_CSG ISTAT: VLS1S Mask            */\r
+#define HRPWM0_CSG_ISTAT_VLS2S_Pos            1                                                       /*!< HRPWM0_CSG ISTAT: VLS2S Position        */\r
+#define HRPWM0_CSG_ISTAT_VLS2S_Msk            (0x01UL << HRPWM0_CSG_ISTAT_VLS2S_Pos)                  /*!< HRPWM0_CSG ISTAT: VLS2S Mask            */\r
+#define HRPWM0_CSG_ISTAT_TRGSS_Pos            2                                                       /*!< HRPWM0_CSG ISTAT: TRGSS Position        */\r
+#define HRPWM0_CSG_ISTAT_TRGSS_Msk            (0x01UL << HRPWM0_CSG_ISTAT_TRGSS_Pos)                  /*!< HRPWM0_CSG ISTAT: TRGSS Mask            */\r
+#define HRPWM0_CSG_ISTAT_STRSS_Pos            3                                                       /*!< HRPWM0_CSG ISTAT: STRSS Position        */\r
+#define HRPWM0_CSG_ISTAT_STRSS_Msk            (0x01UL << HRPWM0_CSG_ISTAT_STRSS_Pos)                  /*!< HRPWM0_CSG ISTAT: STRSS Mask            */\r
+#define HRPWM0_CSG_ISTAT_STPSS_Pos            4                                                       /*!< HRPWM0_CSG ISTAT: STPSS Position        */\r
+#define HRPWM0_CSG_ISTAT_STPSS_Msk            (0x01UL << HRPWM0_CSG_ISTAT_STPSS_Pos)                  /*!< HRPWM0_CSG ISTAT: STPSS Mask            */\r
+#define HRPWM0_CSG_ISTAT_STDS_Pos             5                                                       /*!< HRPWM0_CSG ISTAT: STDS Position         */\r
+#define HRPWM0_CSG_ISTAT_STDS_Msk             (0x01UL << HRPWM0_CSG_ISTAT_STDS_Pos)                   /*!< HRPWM0_CSG ISTAT: STDS Mask             */\r
+#define HRPWM0_CSG_ISTAT_CRSS_Pos             6                                                       /*!< HRPWM0_CSG ISTAT: CRSS Position         */\r
+#define HRPWM0_CSG_ISTAT_CRSS_Msk             (0x01UL << HRPWM0_CSG_ISTAT_CRSS_Pos)                   /*!< HRPWM0_CSG ISTAT: CRSS Mask             */\r
+#define HRPWM0_CSG_ISTAT_CFSS_Pos             7                                                       /*!< HRPWM0_CSG ISTAT: CFSS Position         */\r
+#define HRPWM0_CSG_ISTAT_CFSS_Msk             (0x01UL << HRPWM0_CSG_ISTAT_CFSS_Pos)                   /*!< HRPWM0_CSG ISTAT: CFSS Mask             */\r
+#define HRPWM0_CSG_ISTAT_CSES_Pos             8                                                       /*!< HRPWM0_CSG ISTAT: CSES Position         */\r
+#define HRPWM0_CSG_ISTAT_CSES_Msk             (0x01UL << HRPWM0_CSG_ISTAT_CSES_Pos)                   /*!< HRPWM0_CSG ISTAT: CSES Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_CSG0' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_CSG0_DCI  ------------------------------ */\r
+#define HRPWM0_CSG0_DCI_SVIS_Pos              0                                                       /*!< HRPWM0_CSG0 DCI: SVIS Position          */\r
+#define HRPWM0_CSG0_DCI_SVIS_Msk              (0x0fUL << HRPWM0_CSG0_DCI_SVIS_Pos)                    /*!< HRPWM0_CSG0 DCI: SVIS Mask              */\r
+#define HRPWM0_CSG0_DCI_STRIS_Pos             4                                                       /*!< HRPWM0_CSG0 DCI: STRIS Position         */\r
+#define HRPWM0_CSG0_DCI_STRIS_Msk             (0x0fUL << HRPWM0_CSG0_DCI_STRIS_Pos)                   /*!< HRPWM0_CSG0 DCI: STRIS Mask             */\r
+#define HRPWM0_CSG0_DCI_STPIS_Pos             8                                                       /*!< HRPWM0_CSG0 DCI: STPIS Position         */\r
+#define HRPWM0_CSG0_DCI_STPIS_Msk             (0x0fUL << HRPWM0_CSG0_DCI_STPIS_Pos)                   /*!< HRPWM0_CSG0 DCI: STPIS Mask             */\r
+#define HRPWM0_CSG0_DCI_TRGIS_Pos             12                                                      /*!< HRPWM0_CSG0 DCI: TRGIS Position         */\r
+#define HRPWM0_CSG0_DCI_TRGIS_Msk             (0x0fUL << HRPWM0_CSG0_DCI_TRGIS_Pos)                   /*!< HRPWM0_CSG0 DCI: TRGIS Mask             */\r
+#define HRPWM0_CSG0_DCI_STIS_Pos              16                                                      /*!< HRPWM0_CSG0 DCI: STIS Position          */\r
+#define HRPWM0_CSG0_DCI_STIS_Msk              (0x0fUL << HRPWM0_CSG0_DCI_STIS_Pos)                    /*!< HRPWM0_CSG0 DCI: STIS Mask              */\r
+#define HRPWM0_CSG0_DCI_SCS_Pos               20                                                      /*!< HRPWM0_CSG0 DCI: SCS Position           */\r
+#define HRPWM0_CSG0_DCI_SCS_Msk               (0x03UL << HRPWM0_CSG0_DCI_SCS_Pos)                     /*!< HRPWM0_CSG0 DCI: SCS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_IES  ------------------------------ */\r
+#define HRPWM0_CSG0_IES_SVLS_Pos              0                                                       /*!< HRPWM0_CSG0 IES: SVLS Position          */\r
+#define HRPWM0_CSG0_IES_SVLS_Msk              (0x03UL << HRPWM0_CSG0_IES_SVLS_Pos)                    /*!< HRPWM0_CSG0 IES: SVLS Mask              */\r
+#define HRPWM0_CSG0_IES_STRES_Pos             2                                                       /*!< HRPWM0_CSG0 IES: STRES Position         */\r
+#define HRPWM0_CSG0_IES_STRES_Msk             (0x03UL << HRPWM0_CSG0_IES_STRES_Pos)                   /*!< HRPWM0_CSG0 IES: STRES Mask             */\r
+#define HRPWM0_CSG0_IES_STPES_Pos             4                                                       /*!< HRPWM0_CSG0 IES: STPES Position         */\r
+#define HRPWM0_CSG0_IES_STPES_Msk             (0x03UL << HRPWM0_CSG0_IES_STPES_Pos)                   /*!< HRPWM0_CSG0 IES: STPES Mask             */\r
+#define HRPWM0_CSG0_IES_TRGES_Pos             6                                                       /*!< HRPWM0_CSG0 IES: TRGES Position         */\r
+#define HRPWM0_CSG0_IES_TRGES_Msk             (0x03UL << HRPWM0_CSG0_IES_TRGES_Pos)                   /*!< HRPWM0_CSG0 IES: TRGES Mask             */\r
+#define HRPWM0_CSG0_IES_STES_Pos              8                                                       /*!< HRPWM0_CSG0 IES: STES Position          */\r
+#define HRPWM0_CSG0_IES_STES_Msk              (0x03UL << HRPWM0_CSG0_IES_STES_Pos)                    /*!< HRPWM0_CSG0 IES: STES Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SC  ------------------------------- */\r
+#define HRPWM0_CSG0_SC_PSRM_Pos               0                                                       /*!< HRPWM0_CSG0 SC: PSRM Position           */\r
+#define HRPWM0_CSG0_SC_PSRM_Msk               (0x03UL << HRPWM0_CSG0_SC_PSRM_Pos)                     /*!< HRPWM0_CSG0 SC: PSRM Mask               */\r
+#define HRPWM0_CSG0_SC_PSTM_Pos               2                                                       /*!< HRPWM0_CSG0 SC: PSTM Position           */\r
+#define HRPWM0_CSG0_SC_PSTM_Msk               (0x03UL << HRPWM0_CSG0_SC_PSTM_Pos)                     /*!< HRPWM0_CSG0 SC: PSTM Mask               */\r
+#define HRPWM0_CSG0_SC_FPD_Pos                4                                                       /*!< HRPWM0_CSG0 SC: FPD Position            */\r
+#define HRPWM0_CSG0_SC_FPD_Msk                (0x01UL << HRPWM0_CSG0_SC_FPD_Pos)                      /*!< HRPWM0_CSG0 SC: FPD Mask                */\r
+#define HRPWM0_CSG0_SC_PSV_Pos                5                                                       /*!< HRPWM0_CSG0 SC: PSV Position            */\r
+#define HRPWM0_CSG0_SC_PSV_Msk                (0x03UL << HRPWM0_CSG0_SC_PSV_Pos)                      /*!< HRPWM0_CSG0 SC: PSV Mask                */\r
+#define HRPWM0_CSG0_SC_SCM_Pos                8                                                       /*!< HRPWM0_CSG0 SC: SCM Position            */\r
+#define HRPWM0_CSG0_SC_SCM_Msk                (0x03UL << HRPWM0_CSG0_SC_SCM_Pos)                      /*!< HRPWM0_CSG0 SC: SCM Mask                */\r
+#define HRPWM0_CSG0_SC_SSRM_Pos               10                                                      /*!< HRPWM0_CSG0 SC: SSRM Position           */\r
+#define HRPWM0_CSG0_SC_SSRM_Msk               (0x03UL << HRPWM0_CSG0_SC_SSRM_Pos)                     /*!< HRPWM0_CSG0 SC: SSRM Mask               */\r
+#define HRPWM0_CSG0_SC_SSTM_Pos               12                                                      /*!< HRPWM0_CSG0 SC: SSTM Position           */\r
+#define HRPWM0_CSG0_SC_SSTM_Msk               (0x03UL << HRPWM0_CSG0_SC_SSTM_Pos)                     /*!< HRPWM0_CSG0 SC: SSTM Mask               */\r
+#define HRPWM0_CSG0_SC_SVSC_Pos               14                                                      /*!< HRPWM0_CSG0 SC: SVSC Position           */\r
+#define HRPWM0_CSG0_SC_SVSC_Msk               (0x03UL << HRPWM0_CSG0_SC_SVSC_Pos)                     /*!< HRPWM0_CSG0 SC: SVSC Mask               */\r
+#define HRPWM0_CSG0_SC_SWSM_Pos               16                                                      /*!< HRPWM0_CSG0 SC: SWSM Position           */\r
+#define HRPWM0_CSG0_SC_SWSM_Msk               (0x03UL << HRPWM0_CSG0_SC_SWSM_Pos)                     /*!< HRPWM0_CSG0 SC: SWSM Mask               */\r
+#define HRPWM0_CSG0_SC_GCFG_Pos               18                                                      /*!< HRPWM0_CSG0 SC: GCFG Position           */\r
+#define HRPWM0_CSG0_SC_GCFG_Msk               (0x03UL << HRPWM0_CSG0_SC_GCFG_Pos)                     /*!< HRPWM0_CSG0 SC: GCFG Mask               */\r
+#define HRPWM0_CSG0_SC_IST_Pos                20                                                      /*!< HRPWM0_CSG0 SC: IST Position            */\r
+#define HRPWM0_CSG0_SC_IST_Msk                (0x01UL << HRPWM0_CSG0_SC_IST_Pos)                      /*!< HRPWM0_CSG0 SC: IST Mask                */\r
+#define HRPWM0_CSG0_SC_PSE_Pos                21                                                      /*!< HRPWM0_CSG0 SC: PSE Position            */\r
+#define HRPWM0_CSG0_SC_PSE_Msk                (0x01UL << HRPWM0_CSG0_SC_PSE_Pos)                      /*!< HRPWM0_CSG0 SC: PSE Mask                */\r
+#define HRPWM0_CSG0_SC_PSWM_Pos               24                                                      /*!< HRPWM0_CSG0 SC: PSWM Position           */\r
+#define HRPWM0_CSG0_SC_PSWM_Msk               (0x03UL << HRPWM0_CSG0_SC_PSWM_Pos)                     /*!< HRPWM0_CSG0 SC: PSWM Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_PC  ------------------------------- */\r
+#define HRPWM0_CSG0_PC_PSWV_Pos               0                                                       /*!< HRPWM0_CSG0 PC: PSWV Position           */\r
+#define HRPWM0_CSG0_PC_PSWV_Msk               (0x3fUL << HRPWM0_CSG0_PC_PSWV_Pos)                     /*!< HRPWM0_CSG0 PC: PSWV Mask               */\r
+\r
+/* ------------------------------  HRPWM0_CSG0_DSV1  ------------------------------ */\r
+#define HRPWM0_CSG0_DSV1_DSV1_Pos             0                                                       /*!< HRPWM0_CSG0 DSV1: DSV1 Position         */\r
+#define HRPWM0_CSG0_DSV1_DSV1_Msk             (0x000003ffUL << HRPWM0_CSG0_DSV1_DSV1_Pos)             /*!< HRPWM0_CSG0 DSV1: DSV1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG0_DSV2  ------------------------------ */\r
+#define HRPWM0_CSG0_DSV2_DSV2_Pos             0                                                       /*!< HRPWM0_CSG0 DSV2: DSV2 Position         */\r
+#define HRPWM0_CSG0_DSV2_DSV2_Msk             (0x000003ffUL << HRPWM0_CSG0_DSV2_DSV2_Pos)             /*!< HRPWM0_CSG0 DSV2: DSV2 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG0_SDSV1  ----------------------------- */\r
+#define HRPWM0_CSG0_SDSV1_SDSV1_Pos           0                                                       /*!< HRPWM0_CSG0 SDSV1: SDSV1 Position       */\r
+#define HRPWM0_CSG0_SDSV1_SDSV1_Msk           (0x000003ffUL << HRPWM0_CSG0_SDSV1_SDSV1_Pos)           /*!< HRPWM0_CSG0 SDSV1: SDSV1 Mask           */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SPC  ------------------------------ */\r
+#define HRPWM0_CSG0_SPC_SPSWV_Pos             0                                                       /*!< HRPWM0_CSG0 SPC: SPSWV Position         */\r
+#define HRPWM0_CSG0_SPC_SPSWV_Msk             (0x3fUL << HRPWM0_CSG0_SPC_SPSWV_Pos)                   /*!< HRPWM0_CSG0 SPC: SPSWV Mask             */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_CC  ------------------------------- */\r
+#define HRPWM0_CSG0_CC_IBS_Pos                0                                                       /*!< HRPWM0_CSG0 CC: IBS Position            */\r
+#define HRPWM0_CSG0_CC_IBS_Msk                (0x0fUL << HRPWM0_CSG0_CC_IBS_Pos)                      /*!< HRPWM0_CSG0 CC: IBS Mask                */\r
+#define HRPWM0_CSG0_CC_IMCS_Pos               8                                                       /*!< HRPWM0_CSG0 CC: IMCS Position           */\r
+#define HRPWM0_CSG0_CC_IMCS_Msk               (0x01UL << HRPWM0_CSG0_CC_IMCS_Pos)                     /*!< HRPWM0_CSG0 CC: IMCS Mask               */\r
+#define HRPWM0_CSG0_CC_IMCC_Pos               9                                                       /*!< HRPWM0_CSG0 CC: IMCC Position           */\r
+#define HRPWM0_CSG0_CC_IMCC_Msk               (0x03UL << HRPWM0_CSG0_CC_IMCC_Pos)                     /*!< HRPWM0_CSG0 CC: IMCC Mask               */\r
+#define HRPWM0_CSG0_CC_ESE_Pos                11                                                      /*!< HRPWM0_CSG0 CC: ESE Position            */\r
+#define HRPWM0_CSG0_CC_ESE_Msk                (0x01UL << HRPWM0_CSG0_CC_ESE_Pos)                      /*!< HRPWM0_CSG0 CC: ESE Mask                */\r
+#define HRPWM0_CSG0_CC_OIE_Pos                12                                                      /*!< HRPWM0_CSG0 CC: OIE Position            */\r
+#define HRPWM0_CSG0_CC_OIE_Msk                (0x01UL << HRPWM0_CSG0_CC_OIE_Pos)                      /*!< HRPWM0_CSG0 CC: OIE Mask                */\r
+#define HRPWM0_CSG0_CC_OSE_Pos                13                                                      /*!< HRPWM0_CSG0 CC: OSE Position            */\r
+#define HRPWM0_CSG0_CC_OSE_Msk                (0x01UL << HRPWM0_CSG0_CC_OSE_Pos)                      /*!< HRPWM0_CSG0 CC: OSE Mask                */\r
+#define HRPWM0_CSG0_CC_BLMC_Pos               14                                                      /*!< HRPWM0_CSG0 CC: BLMC Position           */\r
+#define HRPWM0_CSG0_CC_BLMC_Msk               (0x03UL << HRPWM0_CSG0_CC_BLMC_Pos)                     /*!< HRPWM0_CSG0 CC: BLMC Mask               */\r
+#define HRPWM0_CSG0_CC_EBE_Pos                16                                                      /*!< HRPWM0_CSG0 CC: EBE Position            */\r
+#define HRPWM0_CSG0_CC_EBE_Msk                (0x01UL << HRPWM0_CSG0_CC_EBE_Pos)                      /*!< HRPWM0_CSG0 CC: EBE Mask                */\r
+#define HRPWM0_CSG0_CC_COFE_Pos               17                                                      /*!< HRPWM0_CSG0 CC: COFE Position           */\r
+#define HRPWM0_CSG0_CC_COFE_Msk               (0x01UL << HRPWM0_CSG0_CC_COFE_Pos)                     /*!< HRPWM0_CSG0 CC: COFE Mask               */\r
+#define HRPWM0_CSG0_CC_COFM_Pos               18                                                      /*!< HRPWM0_CSG0 CC: COFM Position           */\r
+#define HRPWM0_CSG0_CC_COFM_Msk               (0x0fUL << HRPWM0_CSG0_CC_COFM_Pos)                     /*!< HRPWM0_CSG0 CC: COFM Mask               */\r
+#define HRPWM0_CSG0_CC_COFC_Pos               24                                                      /*!< HRPWM0_CSG0 CC: COFC Position           */\r
+#define HRPWM0_CSG0_CC_COFC_Msk               (0x03UL << HRPWM0_CSG0_CC_COFC_Pos)                     /*!< HRPWM0_CSG0 CC: COFC Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_PLC  ------------------------------ */\r
+#define HRPWM0_CSG0_PLC_IPLS_Pos              0                                                       /*!< HRPWM0_CSG0 PLC: IPLS Position          */\r
+#define HRPWM0_CSG0_PLC_IPLS_Msk              (0x0fUL << HRPWM0_CSG0_PLC_IPLS_Pos)                    /*!< HRPWM0_CSG0 PLC: IPLS Mask              */\r
+#define HRPWM0_CSG0_PLC_PLCL_Pos              8                                                       /*!< HRPWM0_CSG0 PLC: PLCL Position          */\r
+#define HRPWM0_CSG0_PLC_PLCL_Msk              (0x03UL << HRPWM0_CSG0_PLC_PLCL_Pos)                    /*!< HRPWM0_CSG0 PLC: PLCL Mask              */\r
+#define HRPWM0_CSG0_PLC_PSL_Pos               10                                                      /*!< HRPWM0_CSG0 PLC: PSL Position           */\r
+#define HRPWM0_CSG0_PLC_PSL_Msk               (0x01UL << HRPWM0_CSG0_PLC_PSL_Pos)                     /*!< HRPWM0_CSG0 PLC: PSL Mask               */\r
+#define HRPWM0_CSG0_PLC_PLSW_Pos              11                                                      /*!< HRPWM0_CSG0 PLC: PLSW Position          */\r
+#define HRPWM0_CSG0_PLC_PLSW_Msk              (0x01UL << HRPWM0_CSG0_PLC_PLSW_Pos)                    /*!< HRPWM0_CSG0 PLC: PLSW Mask              */\r
+#define HRPWM0_CSG0_PLC_PLEC_Pos              12                                                      /*!< HRPWM0_CSG0 PLC: PLEC Position          */\r
+#define HRPWM0_CSG0_PLC_PLEC_Msk              (0x03UL << HRPWM0_CSG0_PLC_PLEC_Pos)                    /*!< HRPWM0_CSG0 PLC: PLEC Mask              */\r
+#define HRPWM0_CSG0_PLC_PLXC_Pos              14                                                      /*!< HRPWM0_CSG0 PLC: PLXC Position          */\r
+#define HRPWM0_CSG0_PLC_PLXC_Msk              (0x03UL << HRPWM0_CSG0_PLC_PLXC_Pos)                    /*!< HRPWM0_CSG0 PLC: PLXC Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_BLV  ------------------------------ */\r
+#define HRPWM0_CSG0_BLV_BLV_Pos               0                                                       /*!< HRPWM0_CSG0 BLV: BLV Position           */\r
+#define HRPWM0_CSG0_BLV_BLV_Msk               (0x000000ffUL << HRPWM0_CSG0_BLV_BLV_Pos)               /*!< HRPWM0_CSG0 BLV: BLV Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SRE  ------------------------------ */\r
+#define HRPWM0_CSG0_SRE_VLS1E_Pos             0                                                       /*!< HRPWM0_CSG0 SRE: VLS1E Position         */\r
+#define HRPWM0_CSG0_SRE_VLS1E_Msk             (0x01UL << HRPWM0_CSG0_SRE_VLS1E_Pos)                   /*!< HRPWM0_CSG0 SRE: VLS1E Mask             */\r
+#define HRPWM0_CSG0_SRE_VLS2E_Pos             1                                                       /*!< HRPWM0_CSG0 SRE: VLS2E Position         */\r
+#define HRPWM0_CSG0_SRE_VLS2E_Msk             (0x01UL << HRPWM0_CSG0_SRE_VLS2E_Pos)                   /*!< HRPWM0_CSG0 SRE: VLS2E Mask             */\r
+#define HRPWM0_CSG0_SRE_TRGSE_Pos             2                                                       /*!< HRPWM0_CSG0 SRE: TRGSE Position         */\r
+#define HRPWM0_CSG0_SRE_TRGSE_Msk             (0x01UL << HRPWM0_CSG0_SRE_TRGSE_Pos)                   /*!< HRPWM0_CSG0 SRE: TRGSE Mask             */\r
+#define HRPWM0_CSG0_SRE_STRSE_Pos             3                                                       /*!< HRPWM0_CSG0 SRE: STRSE Position         */\r
+#define HRPWM0_CSG0_SRE_STRSE_Msk             (0x01UL << HRPWM0_CSG0_SRE_STRSE_Pos)                   /*!< HRPWM0_CSG0 SRE: STRSE Mask             */\r
+#define HRPWM0_CSG0_SRE_STPSE_Pos             4                                                       /*!< HRPWM0_CSG0 SRE: STPSE Position         */\r
+#define HRPWM0_CSG0_SRE_STPSE_Msk             (0x01UL << HRPWM0_CSG0_SRE_STPSE_Pos)                   /*!< HRPWM0_CSG0 SRE: STPSE Mask             */\r
+#define HRPWM0_CSG0_SRE_STDE_Pos              5                                                       /*!< HRPWM0_CSG0 SRE: STDE Position          */\r
+#define HRPWM0_CSG0_SRE_STDE_Msk              (0x01UL << HRPWM0_CSG0_SRE_STDE_Pos)                    /*!< HRPWM0_CSG0 SRE: STDE Mask              */\r
+#define HRPWM0_CSG0_SRE_CRSE_Pos              6                                                       /*!< HRPWM0_CSG0 SRE: CRSE Position          */\r
+#define HRPWM0_CSG0_SRE_CRSE_Msk              (0x01UL << HRPWM0_CSG0_SRE_CRSE_Pos)                    /*!< HRPWM0_CSG0 SRE: CRSE Mask              */\r
+#define HRPWM0_CSG0_SRE_CFSE_Pos              7                                                       /*!< HRPWM0_CSG0 SRE: CFSE Position          */\r
+#define HRPWM0_CSG0_SRE_CFSE_Msk              (0x01UL << HRPWM0_CSG0_SRE_CFSE_Pos)                    /*!< HRPWM0_CSG0 SRE: CFSE Mask              */\r
+#define HRPWM0_CSG0_SRE_CSEE_Pos              8                                                       /*!< HRPWM0_CSG0 SRE: CSEE Position          */\r
+#define HRPWM0_CSG0_SRE_CSEE_Msk              (0x01UL << HRPWM0_CSG0_SRE_CSEE_Pos)                    /*!< HRPWM0_CSG0 SRE: CSEE Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SRS  ------------------------------ */\r
+#define HRPWM0_CSG0_SRS_VLS1S_Pos             0                                                       /*!< HRPWM0_CSG0 SRS: VLS1S Position         */\r
+#define HRPWM0_CSG0_SRS_VLS1S_Msk             (0x03UL << HRPWM0_CSG0_SRS_VLS1S_Pos)                   /*!< HRPWM0_CSG0 SRS: VLS1S Mask             */\r
+#define HRPWM0_CSG0_SRS_VLS2S_Pos             2                                                       /*!< HRPWM0_CSG0 SRS: VLS2S Position         */\r
+#define HRPWM0_CSG0_SRS_VLS2S_Msk             (0x03UL << HRPWM0_CSG0_SRS_VLS2S_Pos)                   /*!< HRPWM0_CSG0 SRS: VLS2S Mask             */\r
+#define HRPWM0_CSG0_SRS_TRLS_Pos              4                                                       /*!< HRPWM0_CSG0 SRS: TRLS Position          */\r
+#define HRPWM0_CSG0_SRS_TRLS_Msk              (0x03UL << HRPWM0_CSG0_SRS_TRLS_Pos)                    /*!< HRPWM0_CSG0 SRS: TRLS Mask              */\r
+#define HRPWM0_CSG0_SRS_SSLS_Pos              6                                                       /*!< HRPWM0_CSG0 SRS: SSLS Position          */\r
+#define HRPWM0_CSG0_SRS_SSLS_Msk              (0x03UL << HRPWM0_CSG0_SRS_SSLS_Pos)                    /*!< HRPWM0_CSG0 SRS: SSLS Mask              */\r
+#define HRPWM0_CSG0_SRS_STLS_Pos              8                                                       /*!< HRPWM0_CSG0 SRS: STLS Position          */\r
+#define HRPWM0_CSG0_SRS_STLS_Msk              (0x03UL << HRPWM0_CSG0_SRS_STLS_Pos)                    /*!< HRPWM0_CSG0 SRS: STLS Mask              */\r
+#define HRPWM0_CSG0_SRS_CRFLS_Pos             10                                                      /*!< HRPWM0_CSG0 SRS: CRFLS Position         */\r
+#define HRPWM0_CSG0_SRS_CRFLS_Msk             (0x03UL << HRPWM0_CSG0_SRS_CRFLS_Pos)                   /*!< HRPWM0_CSG0 SRS: CRFLS Mask             */\r
+#define HRPWM0_CSG0_SRS_CSLS_Pos              12                                                      /*!< HRPWM0_CSG0 SRS: CSLS Position          */\r
+#define HRPWM0_CSG0_SRS_CSLS_Msk              (0x03UL << HRPWM0_CSG0_SRS_CSLS_Pos)                    /*!< HRPWM0_CSG0 SRS: CSLS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SWS  ------------------------------ */\r
+#define HRPWM0_CSG0_SWS_SVLS1_Pos             0                                                       /*!< HRPWM0_CSG0 SWS: SVLS1 Position         */\r
+#define HRPWM0_CSG0_SWS_SVLS1_Msk             (0x01UL << HRPWM0_CSG0_SWS_SVLS1_Pos)                   /*!< HRPWM0_CSG0 SWS: SVLS1 Mask             */\r
+#define HRPWM0_CSG0_SWS_SVLS2_Pos             1                                                       /*!< HRPWM0_CSG0 SWS: SVLS2 Position         */\r
+#define HRPWM0_CSG0_SWS_SVLS2_Msk             (0x01UL << HRPWM0_CSG0_SWS_SVLS2_Pos)                   /*!< HRPWM0_CSG0 SWS: SVLS2 Mask             */\r
+#define HRPWM0_CSG0_SWS_STRGS_Pos             2                                                       /*!< HRPWM0_CSG0 SWS: STRGS Position         */\r
+#define HRPWM0_CSG0_SWS_STRGS_Msk             (0x01UL << HRPWM0_CSG0_SWS_STRGS_Pos)                   /*!< HRPWM0_CSG0 SWS: STRGS Mask             */\r
+#define HRPWM0_CSG0_SWS_SSTRS_Pos             3                                                       /*!< HRPWM0_CSG0 SWS: SSTRS Position         */\r
+#define HRPWM0_CSG0_SWS_SSTRS_Msk             (0x01UL << HRPWM0_CSG0_SWS_SSTRS_Pos)                   /*!< HRPWM0_CSG0 SWS: SSTRS Mask             */\r
+#define HRPWM0_CSG0_SWS_SSTPS_Pos             4                                                       /*!< HRPWM0_CSG0 SWS: SSTPS Position         */\r
+#define HRPWM0_CSG0_SWS_SSTPS_Msk             (0x01UL << HRPWM0_CSG0_SWS_SSTPS_Pos)                   /*!< HRPWM0_CSG0 SWS: SSTPS Mask             */\r
+#define HRPWM0_CSG0_SWS_SSTD_Pos              5                                                       /*!< HRPWM0_CSG0 SWS: SSTD Position          */\r
+#define HRPWM0_CSG0_SWS_SSTD_Msk              (0x01UL << HRPWM0_CSG0_SWS_SSTD_Pos)                    /*!< HRPWM0_CSG0 SWS: SSTD Mask              */\r
+#define HRPWM0_CSG0_SWS_SCRS_Pos              6                                                       /*!< HRPWM0_CSG0 SWS: SCRS Position          */\r
+#define HRPWM0_CSG0_SWS_SCRS_Msk              (0x01UL << HRPWM0_CSG0_SWS_SCRS_Pos)                    /*!< HRPWM0_CSG0 SWS: SCRS Mask              */\r
+#define HRPWM0_CSG0_SWS_SCFS_Pos              7                                                       /*!< HRPWM0_CSG0 SWS: SCFS Position          */\r
+#define HRPWM0_CSG0_SWS_SCFS_Msk              (0x01UL << HRPWM0_CSG0_SWS_SCFS_Pos)                    /*!< HRPWM0_CSG0 SWS: SCFS Mask              */\r
+#define HRPWM0_CSG0_SWS_SCSS_Pos              8                                                       /*!< HRPWM0_CSG0 SWS: SCSS Position          */\r
+#define HRPWM0_CSG0_SWS_SCSS_Msk              (0x01UL << HRPWM0_CSG0_SWS_SCSS_Pos)                    /*!< HRPWM0_CSG0 SWS: SCSS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SWC  ------------------------------ */\r
+#define HRPWM0_CSG0_SWC_CVLS1_Pos             0                                                       /*!< HRPWM0_CSG0 SWC: CVLS1 Position         */\r
+#define HRPWM0_CSG0_SWC_CVLS1_Msk             (0x01UL << HRPWM0_CSG0_SWC_CVLS1_Pos)                   /*!< HRPWM0_CSG0 SWC: CVLS1 Mask             */\r
+#define HRPWM0_CSG0_SWC_CVLS2_Pos             1                                                       /*!< HRPWM0_CSG0 SWC: CVLS2 Position         */\r
+#define HRPWM0_CSG0_SWC_CVLS2_Msk             (0x01UL << HRPWM0_CSG0_SWC_CVLS2_Pos)                   /*!< HRPWM0_CSG0 SWC: CVLS2 Mask             */\r
+#define HRPWM0_CSG0_SWC_CTRGS_Pos             2                                                       /*!< HRPWM0_CSG0 SWC: CTRGS Position         */\r
+#define HRPWM0_CSG0_SWC_CTRGS_Msk             (0x01UL << HRPWM0_CSG0_SWC_CTRGS_Pos)                   /*!< HRPWM0_CSG0 SWC: CTRGS Mask             */\r
+#define HRPWM0_CSG0_SWC_CSTRS_Pos             3                                                       /*!< HRPWM0_CSG0 SWC: CSTRS Position         */\r
+#define HRPWM0_CSG0_SWC_CSTRS_Msk             (0x01UL << HRPWM0_CSG0_SWC_CSTRS_Pos)                   /*!< HRPWM0_CSG0 SWC: CSTRS Mask             */\r
+#define HRPWM0_CSG0_SWC_CSTPS_Pos             4                                                       /*!< HRPWM0_CSG0 SWC: CSTPS Position         */\r
+#define HRPWM0_CSG0_SWC_CSTPS_Msk             (0x01UL << HRPWM0_CSG0_SWC_CSTPS_Pos)                   /*!< HRPWM0_CSG0 SWC: CSTPS Mask             */\r
+#define HRPWM0_CSG0_SWC_CSTD_Pos              5                                                       /*!< HRPWM0_CSG0 SWC: CSTD Position          */\r
+#define HRPWM0_CSG0_SWC_CSTD_Msk              (0x01UL << HRPWM0_CSG0_SWC_CSTD_Pos)                    /*!< HRPWM0_CSG0 SWC: CSTD Mask              */\r
+#define HRPWM0_CSG0_SWC_CCRS_Pos              6                                                       /*!< HRPWM0_CSG0 SWC: CCRS Position          */\r
+#define HRPWM0_CSG0_SWC_CCRS_Msk              (0x01UL << HRPWM0_CSG0_SWC_CCRS_Pos)                    /*!< HRPWM0_CSG0 SWC: CCRS Mask              */\r
+#define HRPWM0_CSG0_SWC_CCFS_Pos              7                                                       /*!< HRPWM0_CSG0 SWC: CCFS Position          */\r
+#define HRPWM0_CSG0_SWC_CCFS_Msk              (0x01UL << HRPWM0_CSG0_SWC_CCFS_Pos)                    /*!< HRPWM0_CSG0 SWC: CCFS Mask              */\r
+#define HRPWM0_CSG0_SWC_CCSS_Pos              8                                                       /*!< HRPWM0_CSG0 SWC: CCSS Position          */\r
+#define HRPWM0_CSG0_SWC_CCSS_Msk              (0x01UL << HRPWM0_CSG0_SWC_CCSS_Pos)                    /*!< HRPWM0_CSG0 SWC: CCSS Mask              */\r
+\r
+/* ------------------------------  HRPWM0_CSG0_ISTAT  ----------------------------- */\r
+#define HRPWM0_CSG0_ISTAT_VLS1S_Pos           0                                                       /*!< HRPWM0_CSG0 ISTAT: VLS1S Position       */\r
+#define HRPWM0_CSG0_ISTAT_VLS1S_Msk           (0x01UL << HRPWM0_CSG0_ISTAT_VLS1S_Pos)                 /*!< HRPWM0_CSG0 ISTAT: VLS1S Mask           */\r
+#define HRPWM0_CSG0_ISTAT_VLS2S_Pos           1                                                       /*!< HRPWM0_CSG0 ISTAT: VLS2S Position       */\r
+#define HRPWM0_CSG0_ISTAT_VLS2S_Msk           (0x01UL << HRPWM0_CSG0_ISTAT_VLS2S_Pos)                 /*!< HRPWM0_CSG0 ISTAT: VLS2S Mask           */\r
+#define HRPWM0_CSG0_ISTAT_TRGSS_Pos           2                                                       /*!< HRPWM0_CSG0 ISTAT: TRGSS Position       */\r
+#define HRPWM0_CSG0_ISTAT_TRGSS_Msk           (0x01UL << HRPWM0_CSG0_ISTAT_TRGSS_Pos)                 /*!< HRPWM0_CSG0 ISTAT: TRGSS Mask           */\r
+#define HRPWM0_CSG0_ISTAT_STRSS_Pos           3                                                       /*!< HRPWM0_CSG0 ISTAT: STRSS Position       */\r
+#define HRPWM0_CSG0_ISTAT_STRSS_Msk           (0x01UL << HRPWM0_CSG0_ISTAT_STRSS_Pos)                 /*!< HRPWM0_CSG0 ISTAT: STRSS Mask           */\r
+#define HRPWM0_CSG0_ISTAT_STPSS_Pos           4                                                       /*!< HRPWM0_CSG0 ISTAT: STPSS Position       */\r
+#define HRPWM0_CSG0_ISTAT_STPSS_Msk           (0x01UL << HRPWM0_CSG0_ISTAT_STPSS_Pos)                 /*!< HRPWM0_CSG0 ISTAT: STPSS Mask           */\r
+#define HRPWM0_CSG0_ISTAT_STDS_Pos            5                                                       /*!< HRPWM0_CSG0 ISTAT: STDS Position        */\r
+#define HRPWM0_CSG0_ISTAT_STDS_Msk            (0x01UL << HRPWM0_CSG0_ISTAT_STDS_Pos)                  /*!< HRPWM0_CSG0 ISTAT: STDS Mask            */\r
+#define HRPWM0_CSG0_ISTAT_CRSS_Pos            6                                                       /*!< HRPWM0_CSG0 ISTAT: CRSS Position        */\r
+#define HRPWM0_CSG0_ISTAT_CRSS_Msk            (0x01UL << HRPWM0_CSG0_ISTAT_CRSS_Pos)                  /*!< HRPWM0_CSG0 ISTAT: CRSS Mask            */\r
+#define HRPWM0_CSG0_ISTAT_CFSS_Pos            7                                                       /*!< HRPWM0_CSG0 ISTAT: CFSS Position        */\r
+#define HRPWM0_CSG0_ISTAT_CFSS_Msk            (0x01UL << HRPWM0_CSG0_ISTAT_CFSS_Pos)                  /*!< HRPWM0_CSG0 ISTAT: CFSS Mask            */\r
+#define HRPWM0_CSG0_ISTAT_CSES_Pos            8                                                       /*!< HRPWM0_CSG0 ISTAT: CSES Position        */\r
+#define HRPWM0_CSG0_ISTAT_CSES_Msk            (0x01UL << HRPWM0_CSG0_ISTAT_CSES_Pos)                  /*!< HRPWM0_CSG0 ISTAT: CSES Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_CSG1' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_CSG1_DCI  ------------------------------ */\r
+#define HRPWM0_CSG1_DCI_SVIS_Pos              0                                                       /*!< HRPWM0_CSG1 DCI: SVIS Position          */\r
+#define HRPWM0_CSG1_DCI_SVIS_Msk              (0x0fUL << HRPWM0_CSG1_DCI_SVIS_Pos)                    /*!< HRPWM0_CSG1 DCI: SVIS Mask              */\r
+#define HRPWM0_CSG1_DCI_STRIS_Pos             4                                                       /*!< HRPWM0_CSG1 DCI: STRIS Position         */\r
+#define HRPWM0_CSG1_DCI_STRIS_Msk             (0x0fUL << HRPWM0_CSG1_DCI_STRIS_Pos)                   /*!< HRPWM0_CSG1 DCI: STRIS Mask             */\r
+#define HRPWM0_CSG1_DCI_STPIS_Pos             8                                                       /*!< HRPWM0_CSG1 DCI: STPIS Position         */\r
+#define HRPWM0_CSG1_DCI_STPIS_Msk             (0x0fUL << HRPWM0_CSG1_DCI_STPIS_Pos)                   /*!< HRPWM0_CSG1 DCI: STPIS Mask             */\r
+#define HRPWM0_CSG1_DCI_TRGIS_Pos             12                                                      /*!< HRPWM0_CSG1 DCI: TRGIS Position         */\r
+#define HRPWM0_CSG1_DCI_TRGIS_Msk             (0x0fUL << HRPWM0_CSG1_DCI_TRGIS_Pos)                   /*!< HRPWM0_CSG1 DCI: TRGIS Mask             */\r
+#define HRPWM0_CSG1_DCI_STIS_Pos              16                                                      /*!< HRPWM0_CSG1 DCI: STIS Position          */\r
+#define HRPWM0_CSG1_DCI_STIS_Msk              (0x0fUL << HRPWM0_CSG1_DCI_STIS_Pos)                    /*!< HRPWM0_CSG1 DCI: STIS Mask              */\r
+#define HRPWM0_CSG1_DCI_SCS_Pos               20                                                      /*!< HRPWM0_CSG1 DCI: SCS Position           */\r
+#define HRPWM0_CSG1_DCI_SCS_Msk               (0x03UL << HRPWM0_CSG1_DCI_SCS_Pos)                     /*!< HRPWM0_CSG1 DCI: SCS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_IES  ------------------------------ */\r
+#define HRPWM0_CSG1_IES_SVLS_Pos              0                                                       /*!< HRPWM0_CSG1 IES: SVLS Position          */\r
+#define HRPWM0_CSG1_IES_SVLS_Msk              (0x03UL << HRPWM0_CSG1_IES_SVLS_Pos)                    /*!< HRPWM0_CSG1 IES: SVLS Mask              */\r
+#define HRPWM0_CSG1_IES_STRES_Pos             2                                                       /*!< HRPWM0_CSG1 IES: STRES Position         */\r
+#define HRPWM0_CSG1_IES_STRES_Msk             (0x03UL << HRPWM0_CSG1_IES_STRES_Pos)                   /*!< HRPWM0_CSG1 IES: STRES Mask             */\r
+#define HRPWM0_CSG1_IES_STPES_Pos             4                                                       /*!< HRPWM0_CSG1 IES: STPES Position         */\r
+#define HRPWM0_CSG1_IES_STPES_Msk             (0x03UL << HRPWM0_CSG1_IES_STPES_Pos)                   /*!< HRPWM0_CSG1 IES: STPES Mask             */\r
+#define HRPWM0_CSG1_IES_TRGES_Pos             6                                                       /*!< HRPWM0_CSG1 IES: TRGES Position         */\r
+#define HRPWM0_CSG1_IES_TRGES_Msk             (0x03UL << HRPWM0_CSG1_IES_TRGES_Pos)                   /*!< HRPWM0_CSG1 IES: TRGES Mask             */\r
+#define HRPWM0_CSG1_IES_STES_Pos              8                                                       /*!< HRPWM0_CSG1 IES: STES Position          */\r
+#define HRPWM0_CSG1_IES_STES_Msk              (0x03UL << HRPWM0_CSG1_IES_STES_Pos)                    /*!< HRPWM0_CSG1 IES: STES Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SC  ------------------------------- */\r
+#define HRPWM0_CSG1_SC_PSRM_Pos               0                                                       /*!< HRPWM0_CSG1 SC: PSRM Position           */\r
+#define HRPWM0_CSG1_SC_PSRM_Msk               (0x03UL << HRPWM0_CSG1_SC_PSRM_Pos)                     /*!< HRPWM0_CSG1 SC: PSRM Mask               */\r
+#define HRPWM0_CSG1_SC_PSTM_Pos               2                                                       /*!< HRPWM0_CSG1 SC: PSTM Position           */\r
+#define HRPWM0_CSG1_SC_PSTM_Msk               (0x03UL << HRPWM0_CSG1_SC_PSTM_Pos)                     /*!< HRPWM0_CSG1 SC: PSTM Mask               */\r
+#define HRPWM0_CSG1_SC_FPD_Pos                4                                                       /*!< HRPWM0_CSG1 SC: FPD Position            */\r
+#define HRPWM0_CSG1_SC_FPD_Msk                (0x01UL << HRPWM0_CSG1_SC_FPD_Pos)                      /*!< HRPWM0_CSG1 SC: FPD Mask                */\r
+#define HRPWM0_CSG1_SC_PSV_Pos                5                                                       /*!< HRPWM0_CSG1 SC: PSV Position            */\r
+#define HRPWM0_CSG1_SC_PSV_Msk                (0x03UL << HRPWM0_CSG1_SC_PSV_Pos)                      /*!< HRPWM0_CSG1 SC: PSV Mask                */\r
+#define HRPWM0_CSG1_SC_SCM_Pos                8                                                       /*!< HRPWM0_CSG1 SC: SCM Position            */\r
+#define HRPWM0_CSG1_SC_SCM_Msk                (0x03UL << HRPWM0_CSG1_SC_SCM_Pos)                      /*!< HRPWM0_CSG1 SC: SCM Mask                */\r
+#define HRPWM0_CSG1_SC_SSRM_Pos               10                                                      /*!< HRPWM0_CSG1 SC: SSRM Position           */\r
+#define HRPWM0_CSG1_SC_SSRM_Msk               (0x03UL << HRPWM0_CSG1_SC_SSRM_Pos)                     /*!< HRPWM0_CSG1 SC: SSRM Mask               */\r
+#define HRPWM0_CSG1_SC_SSTM_Pos               12                                                      /*!< HRPWM0_CSG1 SC: SSTM Position           */\r
+#define HRPWM0_CSG1_SC_SSTM_Msk               (0x03UL << HRPWM0_CSG1_SC_SSTM_Pos)                     /*!< HRPWM0_CSG1 SC: SSTM Mask               */\r
+#define HRPWM0_CSG1_SC_SVSC_Pos               14                                                      /*!< HRPWM0_CSG1 SC: SVSC Position           */\r
+#define HRPWM0_CSG1_SC_SVSC_Msk               (0x03UL << HRPWM0_CSG1_SC_SVSC_Pos)                     /*!< HRPWM0_CSG1 SC: SVSC Mask               */\r
+#define HRPWM0_CSG1_SC_SWSM_Pos               16                                                      /*!< HRPWM0_CSG1 SC: SWSM Position           */\r
+#define HRPWM0_CSG1_SC_SWSM_Msk               (0x03UL << HRPWM0_CSG1_SC_SWSM_Pos)                     /*!< HRPWM0_CSG1 SC: SWSM Mask               */\r
+#define HRPWM0_CSG1_SC_GCFG_Pos               18                                                      /*!< HRPWM0_CSG1 SC: GCFG Position           */\r
+#define HRPWM0_CSG1_SC_GCFG_Msk               (0x03UL << HRPWM0_CSG1_SC_GCFG_Pos)                     /*!< HRPWM0_CSG1 SC: GCFG Mask               */\r
+#define HRPWM0_CSG1_SC_IST_Pos                20                                                      /*!< HRPWM0_CSG1 SC: IST Position            */\r
+#define HRPWM0_CSG1_SC_IST_Msk                (0x01UL << HRPWM0_CSG1_SC_IST_Pos)                      /*!< HRPWM0_CSG1 SC: IST Mask                */\r
+#define HRPWM0_CSG1_SC_PSE_Pos                21                                                      /*!< HRPWM0_CSG1 SC: PSE Position            */\r
+#define HRPWM0_CSG1_SC_PSE_Msk                (0x01UL << HRPWM0_CSG1_SC_PSE_Pos)                      /*!< HRPWM0_CSG1 SC: PSE Mask                */\r
+#define HRPWM0_CSG1_SC_PSWM_Pos               24                                                      /*!< HRPWM0_CSG1 SC: PSWM Position           */\r
+#define HRPWM0_CSG1_SC_PSWM_Msk               (0x03UL << HRPWM0_CSG1_SC_PSWM_Pos)                     /*!< HRPWM0_CSG1 SC: PSWM Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_PC  ------------------------------- */\r
+#define HRPWM0_CSG1_PC_PSWV_Pos               0                                                       /*!< HRPWM0_CSG1 PC: PSWV Position           */\r
+#define HRPWM0_CSG1_PC_PSWV_Msk               (0x3fUL << HRPWM0_CSG1_PC_PSWV_Pos)                     /*!< HRPWM0_CSG1 PC: PSWV Mask               */\r
+\r
+/* ------------------------------  HRPWM0_CSG1_DSV1  ------------------------------ */\r
+#define HRPWM0_CSG1_DSV1_DSV1_Pos             0                                                       /*!< HRPWM0_CSG1 DSV1: DSV1 Position         */\r
+#define HRPWM0_CSG1_DSV1_DSV1_Msk             (0x000003ffUL << HRPWM0_CSG1_DSV1_DSV1_Pos)             /*!< HRPWM0_CSG1 DSV1: DSV1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG1_DSV2  ------------------------------ */\r
+#define HRPWM0_CSG1_DSV2_DSV2_Pos             0                                                       /*!< HRPWM0_CSG1 DSV2: DSV2 Position         */\r
+#define HRPWM0_CSG1_DSV2_DSV2_Msk             (0x000003ffUL << HRPWM0_CSG1_DSV2_DSV2_Pos)             /*!< HRPWM0_CSG1 DSV2: DSV2 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG1_SDSV1  ----------------------------- */\r
+#define HRPWM0_CSG1_SDSV1_SDSV1_Pos           0                                                       /*!< HRPWM0_CSG1 SDSV1: SDSV1 Position       */\r
+#define HRPWM0_CSG1_SDSV1_SDSV1_Msk           (0x000003ffUL << HRPWM0_CSG1_SDSV1_SDSV1_Pos)           /*!< HRPWM0_CSG1 SDSV1: SDSV1 Mask           */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SPC  ------------------------------ */\r
+#define HRPWM0_CSG1_SPC_SPSWV_Pos             0                                                       /*!< HRPWM0_CSG1 SPC: SPSWV Position         */\r
+#define HRPWM0_CSG1_SPC_SPSWV_Msk             (0x3fUL << HRPWM0_CSG1_SPC_SPSWV_Pos)                   /*!< HRPWM0_CSG1 SPC: SPSWV Mask             */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_CC  ------------------------------- */\r
+#define HRPWM0_CSG1_CC_IBS_Pos                0                                                       /*!< HRPWM0_CSG1 CC: IBS Position            */\r
+#define HRPWM0_CSG1_CC_IBS_Msk                (0x0fUL << HRPWM0_CSG1_CC_IBS_Pos)                      /*!< HRPWM0_CSG1 CC: IBS Mask                */\r
+#define HRPWM0_CSG1_CC_IMCS_Pos               8                                                       /*!< HRPWM0_CSG1 CC: IMCS Position           */\r
+#define HRPWM0_CSG1_CC_IMCS_Msk               (0x01UL << HRPWM0_CSG1_CC_IMCS_Pos)                     /*!< HRPWM0_CSG1 CC: IMCS Mask               */\r
+#define HRPWM0_CSG1_CC_IMCC_Pos               9                                                       /*!< HRPWM0_CSG1 CC: IMCC Position           */\r
+#define HRPWM0_CSG1_CC_IMCC_Msk               (0x03UL << HRPWM0_CSG1_CC_IMCC_Pos)                     /*!< HRPWM0_CSG1 CC: IMCC Mask               */\r
+#define HRPWM0_CSG1_CC_ESE_Pos                11                                                      /*!< HRPWM0_CSG1 CC: ESE Position            */\r
+#define HRPWM0_CSG1_CC_ESE_Msk                (0x01UL << HRPWM0_CSG1_CC_ESE_Pos)                      /*!< HRPWM0_CSG1 CC: ESE Mask                */\r
+#define HRPWM0_CSG1_CC_OIE_Pos                12                                                      /*!< HRPWM0_CSG1 CC: OIE Position            */\r
+#define HRPWM0_CSG1_CC_OIE_Msk                (0x01UL << HRPWM0_CSG1_CC_OIE_Pos)                      /*!< HRPWM0_CSG1 CC: OIE Mask                */\r
+#define HRPWM0_CSG1_CC_OSE_Pos                13                                                      /*!< HRPWM0_CSG1 CC: OSE Position            */\r
+#define HRPWM0_CSG1_CC_OSE_Msk                (0x01UL << HRPWM0_CSG1_CC_OSE_Pos)                      /*!< HRPWM0_CSG1 CC: OSE Mask                */\r
+#define HRPWM0_CSG1_CC_BLMC_Pos               14                                                      /*!< HRPWM0_CSG1 CC: BLMC Position           */\r
+#define HRPWM0_CSG1_CC_BLMC_Msk               (0x03UL << HRPWM0_CSG1_CC_BLMC_Pos)                     /*!< HRPWM0_CSG1 CC: BLMC Mask               */\r
+#define HRPWM0_CSG1_CC_EBE_Pos                16                                                      /*!< HRPWM0_CSG1 CC: EBE Position            */\r
+#define HRPWM0_CSG1_CC_EBE_Msk                (0x01UL << HRPWM0_CSG1_CC_EBE_Pos)                      /*!< HRPWM0_CSG1 CC: EBE Mask                */\r
+#define HRPWM0_CSG1_CC_COFE_Pos               17                                                      /*!< HRPWM0_CSG1 CC: COFE Position           */\r
+#define HRPWM0_CSG1_CC_COFE_Msk               (0x01UL << HRPWM0_CSG1_CC_COFE_Pos)                     /*!< HRPWM0_CSG1 CC: COFE Mask               */\r
+#define HRPWM0_CSG1_CC_COFM_Pos               18                                                      /*!< HRPWM0_CSG1 CC: COFM Position           */\r
+#define HRPWM0_CSG1_CC_COFM_Msk               (0x0fUL << HRPWM0_CSG1_CC_COFM_Pos)                     /*!< HRPWM0_CSG1 CC: COFM Mask               */\r
+#define HRPWM0_CSG1_CC_COFC_Pos               24                                                      /*!< HRPWM0_CSG1 CC: COFC Position           */\r
+#define HRPWM0_CSG1_CC_COFC_Msk               (0x03UL << HRPWM0_CSG1_CC_COFC_Pos)                     /*!< HRPWM0_CSG1 CC: COFC Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_PLC  ------------------------------ */\r
+#define HRPWM0_CSG1_PLC_IPLS_Pos              0                                                       /*!< HRPWM0_CSG1 PLC: IPLS Position          */\r
+#define HRPWM0_CSG1_PLC_IPLS_Msk              (0x0fUL << HRPWM0_CSG1_PLC_IPLS_Pos)                    /*!< HRPWM0_CSG1 PLC: IPLS Mask              */\r
+#define HRPWM0_CSG1_PLC_PLCL_Pos              8                                                       /*!< HRPWM0_CSG1 PLC: PLCL Position          */\r
+#define HRPWM0_CSG1_PLC_PLCL_Msk              (0x03UL << HRPWM0_CSG1_PLC_PLCL_Pos)                    /*!< HRPWM0_CSG1 PLC: PLCL Mask              */\r
+#define HRPWM0_CSG1_PLC_PSL_Pos               10                                                      /*!< HRPWM0_CSG1 PLC: PSL Position           */\r
+#define HRPWM0_CSG1_PLC_PSL_Msk               (0x01UL << HRPWM0_CSG1_PLC_PSL_Pos)                     /*!< HRPWM0_CSG1 PLC: PSL Mask               */\r
+#define HRPWM0_CSG1_PLC_PLSW_Pos              11                                                      /*!< HRPWM0_CSG1 PLC: PLSW Position          */\r
+#define HRPWM0_CSG1_PLC_PLSW_Msk              (0x01UL << HRPWM0_CSG1_PLC_PLSW_Pos)                    /*!< HRPWM0_CSG1 PLC: PLSW Mask              */\r
+#define HRPWM0_CSG1_PLC_PLEC_Pos              12                                                      /*!< HRPWM0_CSG1 PLC: PLEC Position          */\r
+#define HRPWM0_CSG1_PLC_PLEC_Msk              (0x03UL << HRPWM0_CSG1_PLC_PLEC_Pos)                    /*!< HRPWM0_CSG1 PLC: PLEC Mask              */\r
+#define HRPWM0_CSG1_PLC_PLXC_Pos              14                                                      /*!< HRPWM0_CSG1 PLC: PLXC Position          */\r
+#define HRPWM0_CSG1_PLC_PLXC_Msk              (0x03UL << HRPWM0_CSG1_PLC_PLXC_Pos)                    /*!< HRPWM0_CSG1 PLC: PLXC Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_BLV  ------------------------------ */\r
+#define HRPWM0_CSG1_BLV_BLV_Pos               0                                                       /*!< HRPWM0_CSG1 BLV: BLV Position           */\r
+#define HRPWM0_CSG1_BLV_BLV_Msk               (0x000000ffUL << HRPWM0_CSG1_BLV_BLV_Pos)               /*!< HRPWM0_CSG1 BLV: BLV Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SRE  ------------------------------ */\r
+#define HRPWM0_CSG1_SRE_VLS1E_Pos             0                                                       /*!< HRPWM0_CSG1 SRE: VLS1E Position         */\r
+#define HRPWM0_CSG1_SRE_VLS1E_Msk             (0x01UL << HRPWM0_CSG1_SRE_VLS1E_Pos)                   /*!< HRPWM0_CSG1 SRE: VLS1E Mask             */\r
+#define HRPWM0_CSG1_SRE_VLS2E_Pos             1                                                       /*!< HRPWM0_CSG1 SRE: VLS2E Position         */\r
+#define HRPWM0_CSG1_SRE_VLS2E_Msk             (0x01UL << HRPWM0_CSG1_SRE_VLS2E_Pos)                   /*!< HRPWM0_CSG1 SRE: VLS2E Mask             */\r
+#define HRPWM0_CSG1_SRE_TRGSE_Pos             2                                                       /*!< HRPWM0_CSG1 SRE: TRGSE Position         */\r
+#define HRPWM0_CSG1_SRE_TRGSE_Msk             (0x01UL << HRPWM0_CSG1_SRE_TRGSE_Pos)                   /*!< HRPWM0_CSG1 SRE: TRGSE Mask             */\r
+#define HRPWM0_CSG1_SRE_STRSE_Pos             3                                                       /*!< HRPWM0_CSG1 SRE: STRSE Position         */\r
+#define HRPWM0_CSG1_SRE_STRSE_Msk             (0x01UL << HRPWM0_CSG1_SRE_STRSE_Pos)                   /*!< HRPWM0_CSG1 SRE: STRSE Mask             */\r
+#define HRPWM0_CSG1_SRE_STPSE_Pos             4                                                       /*!< HRPWM0_CSG1 SRE: STPSE Position         */\r
+#define HRPWM0_CSG1_SRE_STPSE_Msk             (0x01UL << HRPWM0_CSG1_SRE_STPSE_Pos)                   /*!< HRPWM0_CSG1 SRE: STPSE Mask             */\r
+#define HRPWM0_CSG1_SRE_STDE_Pos              5                                                       /*!< HRPWM0_CSG1 SRE: STDE Position          */\r
+#define HRPWM0_CSG1_SRE_STDE_Msk              (0x01UL << HRPWM0_CSG1_SRE_STDE_Pos)                    /*!< HRPWM0_CSG1 SRE: STDE Mask              */\r
+#define HRPWM0_CSG1_SRE_CRSE_Pos              6                                                       /*!< HRPWM0_CSG1 SRE: CRSE Position          */\r
+#define HRPWM0_CSG1_SRE_CRSE_Msk              (0x01UL << HRPWM0_CSG1_SRE_CRSE_Pos)                    /*!< HRPWM0_CSG1 SRE: CRSE Mask              */\r
+#define HRPWM0_CSG1_SRE_CFSE_Pos              7                                                       /*!< HRPWM0_CSG1 SRE: CFSE Position          */\r
+#define HRPWM0_CSG1_SRE_CFSE_Msk              (0x01UL << HRPWM0_CSG1_SRE_CFSE_Pos)                    /*!< HRPWM0_CSG1 SRE: CFSE Mask              */\r
+#define HRPWM0_CSG1_SRE_CSEE_Pos              8                                                       /*!< HRPWM0_CSG1 SRE: CSEE Position          */\r
+#define HRPWM0_CSG1_SRE_CSEE_Msk              (0x01UL << HRPWM0_CSG1_SRE_CSEE_Pos)                    /*!< HRPWM0_CSG1 SRE: CSEE Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SRS  ------------------------------ */\r
+#define HRPWM0_CSG1_SRS_VLS1S_Pos             0                                                       /*!< HRPWM0_CSG1 SRS: VLS1S Position         */\r
+#define HRPWM0_CSG1_SRS_VLS1S_Msk             (0x03UL << HRPWM0_CSG1_SRS_VLS1S_Pos)                   /*!< HRPWM0_CSG1 SRS: VLS1S Mask             */\r
+#define HRPWM0_CSG1_SRS_VLS2S_Pos             2                                                       /*!< HRPWM0_CSG1 SRS: VLS2S Position         */\r
+#define HRPWM0_CSG1_SRS_VLS2S_Msk             (0x03UL << HRPWM0_CSG1_SRS_VLS2S_Pos)                   /*!< HRPWM0_CSG1 SRS: VLS2S Mask             */\r
+#define HRPWM0_CSG1_SRS_TRLS_Pos              4                                                       /*!< HRPWM0_CSG1 SRS: TRLS Position          */\r
+#define HRPWM0_CSG1_SRS_TRLS_Msk              (0x03UL << HRPWM0_CSG1_SRS_TRLS_Pos)                    /*!< HRPWM0_CSG1 SRS: TRLS Mask              */\r
+#define HRPWM0_CSG1_SRS_SSLS_Pos              6                                                       /*!< HRPWM0_CSG1 SRS: SSLS Position          */\r
+#define HRPWM0_CSG1_SRS_SSLS_Msk              (0x03UL << HRPWM0_CSG1_SRS_SSLS_Pos)                    /*!< HRPWM0_CSG1 SRS: SSLS Mask              */\r
+#define HRPWM0_CSG1_SRS_STLS_Pos              8                                                       /*!< HRPWM0_CSG1 SRS: STLS Position          */\r
+#define HRPWM0_CSG1_SRS_STLS_Msk              (0x03UL << HRPWM0_CSG1_SRS_STLS_Pos)                    /*!< HRPWM0_CSG1 SRS: STLS Mask              */\r
+#define HRPWM0_CSG1_SRS_CRFLS_Pos             10                                                      /*!< HRPWM0_CSG1 SRS: CRFLS Position         */\r
+#define HRPWM0_CSG1_SRS_CRFLS_Msk             (0x03UL << HRPWM0_CSG1_SRS_CRFLS_Pos)                   /*!< HRPWM0_CSG1 SRS: CRFLS Mask             */\r
+#define HRPWM0_CSG1_SRS_CSLS_Pos              12                                                      /*!< HRPWM0_CSG1 SRS: CSLS Position          */\r
+#define HRPWM0_CSG1_SRS_CSLS_Msk              (0x03UL << HRPWM0_CSG1_SRS_CSLS_Pos)                    /*!< HRPWM0_CSG1 SRS: CSLS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SWS  ------------------------------ */\r
+#define HRPWM0_CSG1_SWS_SVLS1_Pos             0                                                       /*!< HRPWM0_CSG1 SWS: SVLS1 Position         */\r
+#define HRPWM0_CSG1_SWS_SVLS1_Msk             (0x01UL << HRPWM0_CSG1_SWS_SVLS1_Pos)                   /*!< HRPWM0_CSG1 SWS: SVLS1 Mask             */\r
+#define HRPWM0_CSG1_SWS_SVLS2_Pos             1                                                       /*!< HRPWM0_CSG1 SWS: SVLS2 Position         */\r
+#define HRPWM0_CSG1_SWS_SVLS2_Msk             (0x01UL << HRPWM0_CSG1_SWS_SVLS2_Pos)                   /*!< HRPWM0_CSG1 SWS: SVLS2 Mask             */\r
+#define HRPWM0_CSG1_SWS_STRGS_Pos             2                                                       /*!< HRPWM0_CSG1 SWS: STRGS Position         */\r
+#define HRPWM0_CSG1_SWS_STRGS_Msk             (0x01UL << HRPWM0_CSG1_SWS_STRGS_Pos)                   /*!< HRPWM0_CSG1 SWS: STRGS Mask             */\r
+#define HRPWM0_CSG1_SWS_SSTRS_Pos             3                                                       /*!< HRPWM0_CSG1 SWS: SSTRS Position         */\r
+#define HRPWM0_CSG1_SWS_SSTRS_Msk             (0x01UL << HRPWM0_CSG1_SWS_SSTRS_Pos)                   /*!< HRPWM0_CSG1 SWS: SSTRS Mask             */\r
+#define HRPWM0_CSG1_SWS_SSTPS_Pos             4                                                       /*!< HRPWM0_CSG1 SWS: SSTPS Position         */\r
+#define HRPWM0_CSG1_SWS_SSTPS_Msk             (0x01UL << HRPWM0_CSG1_SWS_SSTPS_Pos)                   /*!< HRPWM0_CSG1 SWS: SSTPS Mask             */\r
+#define HRPWM0_CSG1_SWS_SSTD_Pos              5                                                       /*!< HRPWM0_CSG1 SWS: SSTD Position          */\r
+#define HRPWM0_CSG1_SWS_SSTD_Msk              (0x01UL << HRPWM0_CSG1_SWS_SSTD_Pos)                    /*!< HRPWM0_CSG1 SWS: SSTD Mask              */\r
+#define HRPWM0_CSG1_SWS_SCRS_Pos              6                                                       /*!< HRPWM0_CSG1 SWS: SCRS Position          */\r
+#define HRPWM0_CSG1_SWS_SCRS_Msk              (0x01UL << HRPWM0_CSG1_SWS_SCRS_Pos)                    /*!< HRPWM0_CSG1 SWS: SCRS Mask              */\r
+#define HRPWM0_CSG1_SWS_SCFS_Pos              7                                                       /*!< HRPWM0_CSG1 SWS: SCFS Position          */\r
+#define HRPWM0_CSG1_SWS_SCFS_Msk              (0x01UL << HRPWM0_CSG1_SWS_SCFS_Pos)                    /*!< HRPWM0_CSG1 SWS: SCFS Mask              */\r
+#define HRPWM0_CSG1_SWS_SCSS_Pos              8                                                       /*!< HRPWM0_CSG1 SWS: SCSS Position          */\r
+#define HRPWM0_CSG1_SWS_SCSS_Msk              (0x01UL << HRPWM0_CSG1_SWS_SCSS_Pos)                    /*!< HRPWM0_CSG1 SWS: SCSS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SWC  ------------------------------ */\r
+#define HRPWM0_CSG1_SWC_CVLS1_Pos             0                                                       /*!< HRPWM0_CSG1 SWC: CVLS1 Position         */\r
+#define HRPWM0_CSG1_SWC_CVLS1_Msk             (0x01UL << HRPWM0_CSG1_SWC_CVLS1_Pos)                   /*!< HRPWM0_CSG1 SWC: CVLS1 Mask             */\r
+#define HRPWM0_CSG1_SWC_CVLS2_Pos             1                                                       /*!< HRPWM0_CSG1 SWC: CVLS2 Position         */\r
+#define HRPWM0_CSG1_SWC_CVLS2_Msk             (0x01UL << HRPWM0_CSG1_SWC_CVLS2_Pos)                   /*!< HRPWM0_CSG1 SWC: CVLS2 Mask             */\r
+#define HRPWM0_CSG1_SWC_CTRGS_Pos             2                                                       /*!< HRPWM0_CSG1 SWC: CTRGS Position         */\r
+#define HRPWM0_CSG1_SWC_CTRGS_Msk             (0x01UL << HRPWM0_CSG1_SWC_CTRGS_Pos)                   /*!< HRPWM0_CSG1 SWC: CTRGS Mask             */\r
+#define HRPWM0_CSG1_SWC_CSTRS_Pos             3                                                       /*!< HRPWM0_CSG1 SWC: CSTRS Position         */\r
+#define HRPWM0_CSG1_SWC_CSTRS_Msk             (0x01UL << HRPWM0_CSG1_SWC_CSTRS_Pos)                   /*!< HRPWM0_CSG1 SWC: CSTRS Mask             */\r
+#define HRPWM0_CSG1_SWC_CSTPS_Pos             4                                                       /*!< HRPWM0_CSG1 SWC: CSTPS Position         */\r
+#define HRPWM0_CSG1_SWC_CSTPS_Msk             (0x01UL << HRPWM0_CSG1_SWC_CSTPS_Pos)                   /*!< HRPWM0_CSG1 SWC: CSTPS Mask             */\r
+#define HRPWM0_CSG1_SWC_CSTD_Pos              5                                                       /*!< HRPWM0_CSG1 SWC: CSTD Position          */\r
+#define HRPWM0_CSG1_SWC_CSTD_Msk              (0x01UL << HRPWM0_CSG1_SWC_CSTD_Pos)                    /*!< HRPWM0_CSG1 SWC: CSTD Mask              */\r
+#define HRPWM0_CSG1_SWC_CCRS_Pos              6                                                       /*!< HRPWM0_CSG1 SWC: CCRS Position          */\r
+#define HRPWM0_CSG1_SWC_CCRS_Msk              (0x01UL << HRPWM0_CSG1_SWC_CCRS_Pos)                    /*!< HRPWM0_CSG1 SWC: CCRS Mask              */\r
+#define HRPWM0_CSG1_SWC_CCFS_Pos              7                                                       /*!< HRPWM0_CSG1 SWC: CCFS Position          */\r
+#define HRPWM0_CSG1_SWC_CCFS_Msk              (0x01UL << HRPWM0_CSG1_SWC_CCFS_Pos)                    /*!< HRPWM0_CSG1 SWC: CCFS Mask              */\r
+#define HRPWM0_CSG1_SWC_CCSS_Pos              8                                                       /*!< HRPWM0_CSG1 SWC: CCSS Position          */\r
+#define HRPWM0_CSG1_SWC_CCSS_Msk              (0x01UL << HRPWM0_CSG1_SWC_CCSS_Pos)                    /*!< HRPWM0_CSG1 SWC: CCSS Mask              */\r
+\r
+/* ------------------------------  HRPWM0_CSG1_ISTAT  ----------------------------- */\r
+#define HRPWM0_CSG1_ISTAT_VLS1S_Pos           0                                                       /*!< HRPWM0_CSG1 ISTAT: VLS1S Position       */\r
+#define HRPWM0_CSG1_ISTAT_VLS1S_Msk           (0x01UL << HRPWM0_CSG1_ISTAT_VLS1S_Pos)                 /*!< HRPWM0_CSG1 ISTAT: VLS1S Mask           */\r
+#define HRPWM0_CSG1_ISTAT_VLS2S_Pos           1                                                       /*!< HRPWM0_CSG1 ISTAT: VLS2S Position       */\r
+#define HRPWM0_CSG1_ISTAT_VLS2S_Msk           (0x01UL << HRPWM0_CSG1_ISTAT_VLS2S_Pos)                 /*!< HRPWM0_CSG1 ISTAT: VLS2S Mask           */\r
+#define HRPWM0_CSG1_ISTAT_TRGSS_Pos           2                                                       /*!< HRPWM0_CSG1 ISTAT: TRGSS Position       */\r
+#define HRPWM0_CSG1_ISTAT_TRGSS_Msk           (0x01UL << HRPWM0_CSG1_ISTAT_TRGSS_Pos)                 /*!< HRPWM0_CSG1 ISTAT: TRGSS Mask           */\r
+#define HRPWM0_CSG1_ISTAT_STRSS_Pos           3                                                       /*!< HRPWM0_CSG1 ISTAT: STRSS Position       */\r
+#define HRPWM0_CSG1_ISTAT_STRSS_Msk           (0x01UL << HRPWM0_CSG1_ISTAT_STRSS_Pos)                 /*!< HRPWM0_CSG1 ISTAT: STRSS Mask           */\r
+#define HRPWM0_CSG1_ISTAT_STPSS_Pos           4                                                       /*!< HRPWM0_CSG1 ISTAT: STPSS Position       */\r
+#define HRPWM0_CSG1_ISTAT_STPSS_Msk           (0x01UL << HRPWM0_CSG1_ISTAT_STPSS_Pos)                 /*!< HRPWM0_CSG1 ISTAT: STPSS Mask           */\r
+#define HRPWM0_CSG1_ISTAT_STDS_Pos            5                                                       /*!< HRPWM0_CSG1 ISTAT: STDS Position        */\r
+#define HRPWM0_CSG1_ISTAT_STDS_Msk            (0x01UL << HRPWM0_CSG1_ISTAT_STDS_Pos)                  /*!< HRPWM0_CSG1 ISTAT: STDS Mask            */\r
+#define HRPWM0_CSG1_ISTAT_CRSS_Pos            6                                                       /*!< HRPWM0_CSG1 ISTAT: CRSS Position        */\r
+#define HRPWM0_CSG1_ISTAT_CRSS_Msk            (0x01UL << HRPWM0_CSG1_ISTAT_CRSS_Pos)                  /*!< HRPWM0_CSG1 ISTAT: CRSS Mask            */\r
+#define HRPWM0_CSG1_ISTAT_CFSS_Pos            7                                                       /*!< HRPWM0_CSG1 ISTAT: CFSS Position        */\r
+#define HRPWM0_CSG1_ISTAT_CFSS_Msk            (0x01UL << HRPWM0_CSG1_ISTAT_CFSS_Pos)                  /*!< HRPWM0_CSG1 ISTAT: CFSS Mask            */\r
+#define HRPWM0_CSG1_ISTAT_CSES_Pos            8                                                       /*!< HRPWM0_CSG1 ISTAT: CSES Position        */\r
+#define HRPWM0_CSG1_ISTAT_CSES_Msk            (0x01UL << HRPWM0_CSG1_ISTAT_CSES_Pos)                  /*!< HRPWM0_CSG1 ISTAT: CSES Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_CSG2' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_CSG2_DCI  ------------------------------ */\r
+#define HRPWM0_CSG2_DCI_SVIS_Pos              0                                                       /*!< HRPWM0_CSG2 DCI: SVIS Position          */\r
+#define HRPWM0_CSG2_DCI_SVIS_Msk              (0x0fUL << HRPWM0_CSG2_DCI_SVIS_Pos)                    /*!< HRPWM0_CSG2 DCI: SVIS Mask              */\r
+#define HRPWM0_CSG2_DCI_STRIS_Pos             4                                                       /*!< HRPWM0_CSG2 DCI: STRIS Position         */\r
+#define HRPWM0_CSG2_DCI_STRIS_Msk             (0x0fUL << HRPWM0_CSG2_DCI_STRIS_Pos)                   /*!< HRPWM0_CSG2 DCI: STRIS Mask             */\r
+#define HRPWM0_CSG2_DCI_STPIS_Pos             8                                                       /*!< HRPWM0_CSG2 DCI: STPIS Position         */\r
+#define HRPWM0_CSG2_DCI_STPIS_Msk             (0x0fUL << HRPWM0_CSG2_DCI_STPIS_Pos)                   /*!< HRPWM0_CSG2 DCI: STPIS Mask             */\r
+#define HRPWM0_CSG2_DCI_TRGIS_Pos             12                                                      /*!< HRPWM0_CSG2 DCI: TRGIS Position         */\r
+#define HRPWM0_CSG2_DCI_TRGIS_Msk             (0x0fUL << HRPWM0_CSG2_DCI_TRGIS_Pos)                   /*!< HRPWM0_CSG2 DCI: TRGIS Mask             */\r
+#define HRPWM0_CSG2_DCI_STIS_Pos              16                                                      /*!< HRPWM0_CSG2 DCI: STIS Position          */\r
+#define HRPWM0_CSG2_DCI_STIS_Msk              (0x0fUL << HRPWM0_CSG2_DCI_STIS_Pos)                    /*!< HRPWM0_CSG2 DCI: STIS Mask              */\r
+#define HRPWM0_CSG2_DCI_SCS_Pos               20                                                      /*!< HRPWM0_CSG2 DCI: SCS Position           */\r
+#define HRPWM0_CSG2_DCI_SCS_Msk               (0x03UL << HRPWM0_CSG2_DCI_SCS_Pos)                     /*!< HRPWM0_CSG2 DCI: SCS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_IES  ------------------------------ */\r
+#define HRPWM0_CSG2_IES_SVLS_Pos              0                                                       /*!< HRPWM0_CSG2 IES: SVLS Position          */\r
+#define HRPWM0_CSG2_IES_SVLS_Msk              (0x03UL << HRPWM0_CSG2_IES_SVLS_Pos)                    /*!< HRPWM0_CSG2 IES: SVLS Mask              */\r
+#define HRPWM0_CSG2_IES_STRES_Pos             2                                                       /*!< HRPWM0_CSG2 IES: STRES Position         */\r
+#define HRPWM0_CSG2_IES_STRES_Msk             (0x03UL << HRPWM0_CSG2_IES_STRES_Pos)                   /*!< HRPWM0_CSG2 IES: STRES Mask             */\r
+#define HRPWM0_CSG2_IES_STPES_Pos             4                                                       /*!< HRPWM0_CSG2 IES: STPES Position         */\r
+#define HRPWM0_CSG2_IES_STPES_Msk             (0x03UL << HRPWM0_CSG2_IES_STPES_Pos)                   /*!< HRPWM0_CSG2 IES: STPES Mask             */\r
+#define HRPWM0_CSG2_IES_TRGES_Pos             6                                                       /*!< HRPWM0_CSG2 IES: TRGES Position         */\r
+#define HRPWM0_CSG2_IES_TRGES_Msk             (0x03UL << HRPWM0_CSG2_IES_TRGES_Pos)                   /*!< HRPWM0_CSG2 IES: TRGES Mask             */\r
+#define HRPWM0_CSG2_IES_STES_Pos              8                                                       /*!< HRPWM0_CSG2 IES: STES Position          */\r
+#define HRPWM0_CSG2_IES_STES_Msk              (0x03UL << HRPWM0_CSG2_IES_STES_Pos)                    /*!< HRPWM0_CSG2 IES: STES Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SC  ------------------------------- */\r
+#define HRPWM0_CSG2_SC_PSRM_Pos               0                                                       /*!< HRPWM0_CSG2 SC: PSRM Position           */\r
+#define HRPWM0_CSG2_SC_PSRM_Msk               (0x03UL << HRPWM0_CSG2_SC_PSRM_Pos)                     /*!< HRPWM0_CSG2 SC: PSRM Mask               */\r
+#define HRPWM0_CSG2_SC_PSTM_Pos               2                                                       /*!< HRPWM0_CSG2 SC: PSTM Position           */\r
+#define HRPWM0_CSG2_SC_PSTM_Msk               (0x03UL << HRPWM0_CSG2_SC_PSTM_Pos)                     /*!< HRPWM0_CSG2 SC: PSTM Mask               */\r
+#define HRPWM0_CSG2_SC_FPD_Pos                4                                                       /*!< HRPWM0_CSG2 SC: FPD Position            */\r
+#define HRPWM0_CSG2_SC_FPD_Msk                (0x01UL << HRPWM0_CSG2_SC_FPD_Pos)                      /*!< HRPWM0_CSG2 SC: FPD Mask                */\r
+#define HRPWM0_CSG2_SC_PSV_Pos                5                                                       /*!< HRPWM0_CSG2 SC: PSV Position            */\r
+#define HRPWM0_CSG2_SC_PSV_Msk                (0x03UL << HRPWM0_CSG2_SC_PSV_Pos)                      /*!< HRPWM0_CSG2 SC: PSV Mask                */\r
+#define HRPWM0_CSG2_SC_SCM_Pos                8                                                       /*!< HRPWM0_CSG2 SC: SCM Position            */\r
+#define HRPWM0_CSG2_SC_SCM_Msk                (0x03UL << HRPWM0_CSG2_SC_SCM_Pos)                      /*!< HRPWM0_CSG2 SC: SCM Mask                */\r
+#define HRPWM0_CSG2_SC_SSRM_Pos               10                                                      /*!< HRPWM0_CSG2 SC: SSRM Position           */\r
+#define HRPWM0_CSG2_SC_SSRM_Msk               (0x03UL << HRPWM0_CSG2_SC_SSRM_Pos)                     /*!< HRPWM0_CSG2 SC: SSRM Mask               */\r
+#define HRPWM0_CSG2_SC_SSTM_Pos               12                                                      /*!< HRPWM0_CSG2 SC: SSTM Position           */\r
+#define HRPWM0_CSG2_SC_SSTM_Msk               (0x03UL << HRPWM0_CSG2_SC_SSTM_Pos)                     /*!< HRPWM0_CSG2 SC: SSTM Mask               */\r
+#define HRPWM0_CSG2_SC_SVSC_Pos               14                                                      /*!< HRPWM0_CSG2 SC: SVSC Position           */\r
+#define HRPWM0_CSG2_SC_SVSC_Msk               (0x03UL << HRPWM0_CSG2_SC_SVSC_Pos)                     /*!< HRPWM0_CSG2 SC: SVSC Mask               */\r
+#define HRPWM0_CSG2_SC_SWSM_Pos               16                                                      /*!< HRPWM0_CSG2 SC: SWSM Position           */\r
+#define HRPWM0_CSG2_SC_SWSM_Msk               (0x03UL << HRPWM0_CSG2_SC_SWSM_Pos)                     /*!< HRPWM0_CSG2 SC: SWSM Mask               */\r
+#define HRPWM0_CSG2_SC_GCFG_Pos               18                                                      /*!< HRPWM0_CSG2 SC: GCFG Position           */\r
+#define HRPWM0_CSG2_SC_GCFG_Msk               (0x03UL << HRPWM0_CSG2_SC_GCFG_Pos)                     /*!< HRPWM0_CSG2 SC: GCFG Mask               */\r
+#define HRPWM0_CSG2_SC_IST_Pos                20                                                      /*!< HRPWM0_CSG2 SC: IST Position            */\r
+#define HRPWM0_CSG2_SC_IST_Msk                (0x01UL << HRPWM0_CSG2_SC_IST_Pos)                      /*!< HRPWM0_CSG2 SC: IST Mask                */\r
+#define HRPWM0_CSG2_SC_PSE_Pos                21                                                      /*!< HRPWM0_CSG2 SC: PSE Position            */\r
+#define HRPWM0_CSG2_SC_PSE_Msk                (0x01UL << HRPWM0_CSG2_SC_PSE_Pos)                      /*!< HRPWM0_CSG2 SC: PSE Mask                */\r
+#define HRPWM0_CSG2_SC_PSWM_Pos               24                                                      /*!< HRPWM0_CSG2 SC: PSWM Position           */\r
+#define HRPWM0_CSG2_SC_PSWM_Msk               (0x03UL << HRPWM0_CSG2_SC_PSWM_Pos)                     /*!< HRPWM0_CSG2 SC: PSWM Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_PC  ------------------------------- */\r
+#define HRPWM0_CSG2_PC_PSWV_Pos               0                                                       /*!< HRPWM0_CSG2 PC: PSWV Position           */\r
+#define HRPWM0_CSG2_PC_PSWV_Msk               (0x3fUL << HRPWM0_CSG2_PC_PSWV_Pos)                     /*!< HRPWM0_CSG2 PC: PSWV Mask               */\r
+\r
+/* ------------------------------  HRPWM0_CSG2_DSV1  ------------------------------ */\r
+#define HRPWM0_CSG2_DSV1_DSV1_Pos             0                                                       /*!< HRPWM0_CSG2 DSV1: DSV1 Position         */\r
+#define HRPWM0_CSG2_DSV1_DSV1_Msk             (0x000003ffUL << HRPWM0_CSG2_DSV1_DSV1_Pos)             /*!< HRPWM0_CSG2 DSV1: DSV1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG2_DSV2  ------------------------------ */\r
+#define HRPWM0_CSG2_DSV2_DSV2_Pos             0                                                       /*!< HRPWM0_CSG2 DSV2: DSV2 Position         */\r
+#define HRPWM0_CSG2_DSV2_DSV2_Msk             (0x000003ffUL << HRPWM0_CSG2_DSV2_DSV2_Pos)             /*!< HRPWM0_CSG2 DSV2: DSV2 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG2_SDSV1  ----------------------------- */\r
+#define HRPWM0_CSG2_SDSV1_SDSV1_Pos           0                                                       /*!< HRPWM0_CSG2 SDSV1: SDSV1 Position       */\r
+#define HRPWM0_CSG2_SDSV1_SDSV1_Msk           (0x000003ffUL << HRPWM0_CSG2_SDSV1_SDSV1_Pos)           /*!< HRPWM0_CSG2 SDSV1: SDSV1 Mask           */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SPC  ------------------------------ */\r
+#define HRPWM0_CSG2_SPC_SPSWV_Pos             0                                                       /*!< HRPWM0_CSG2 SPC: SPSWV Position         */\r
+#define HRPWM0_CSG2_SPC_SPSWV_Msk             (0x3fUL << HRPWM0_CSG2_SPC_SPSWV_Pos)                   /*!< HRPWM0_CSG2 SPC: SPSWV Mask             */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_CC  ------------------------------- */\r
+#define HRPWM0_CSG2_CC_IBS_Pos                0                                                       /*!< HRPWM0_CSG2 CC: IBS Position            */\r
+#define HRPWM0_CSG2_CC_IBS_Msk                (0x0fUL << HRPWM0_CSG2_CC_IBS_Pos)                      /*!< HRPWM0_CSG2 CC: IBS Mask                */\r
+#define HRPWM0_CSG2_CC_IMCS_Pos               8                                                       /*!< HRPWM0_CSG2 CC: IMCS Position           */\r
+#define HRPWM0_CSG2_CC_IMCS_Msk               (0x01UL << HRPWM0_CSG2_CC_IMCS_Pos)                     /*!< HRPWM0_CSG2 CC: IMCS Mask               */\r
+#define HRPWM0_CSG2_CC_IMCC_Pos               9                                                       /*!< HRPWM0_CSG2 CC: IMCC Position           */\r
+#define HRPWM0_CSG2_CC_IMCC_Msk               (0x03UL << HRPWM0_CSG2_CC_IMCC_Pos)                     /*!< HRPWM0_CSG2 CC: IMCC Mask               */\r
+#define HRPWM0_CSG2_CC_ESE_Pos                11                                                      /*!< HRPWM0_CSG2 CC: ESE Position            */\r
+#define HRPWM0_CSG2_CC_ESE_Msk                (0x01UL << HRPWM0_CSG2_CC_ESE_Pos)                      /*!< HRPWM0_CSG2 CC: ESE Mask                */\r
+#define HRPWM0_CSG2_CC_OIE_Pos                12                                                      /*!< HRPWM0_CSG2 CC: OIE Position            */\r
+#define HRPWM0_CSG2_CC_OIE_Msk                (0x01UL << HRPWM0_CSG2_CC_OIE_Pos)                      /*!< HRPWM0_CSG2 CC: OIE Mask                */\r
+#define HRPWM0_CSG2_CC_OSE_Pos                13                                                      /*!< HRPWM0_CSG2 CC: OSE Position            */\r
+#define HRPWM0_CSG2_CC_OSE_Msk                (0x01UL << HRPWM0_CSG2_CC_OSE_Pos)                      /*!< HRPWM0_CSG2 CC: OSE Mask                */\r
+#define HRPWM0_CSG2_CC_BLMC_Pos               14                                                      /*!< HRPWM0_CSG2 CC: BLMC Position           */\r
+#define HRPWM0_CSG2_CC_BLMC_Msk               (0x03UL << HRPWM0_CSG2_CC_BLMC_Pos)                     /*!< HRPWM0_CSG2 CC: BLMC Mask               */\r
+#define HRPWM0_CSG2_CC_EBE_Pos                16                                                      /*!< HRPWM0_CSG2 CC: EBE Position            */\r
+#define HRPWM0_CSG2_CC_EBE_Msk                (0x01UL << HRPWM0_CSG2_CC_EBE_Pos)                      /*!< HRPWM0_CSG2 CC: EBE Mask                */\r
+#define HRPWM0_CSG2_CC_COFE_Pos               17                                                      /*!< HRPWM0_CSG2 CC: COFE Position           */\r
+#define HRPWM0_CSG2_CC_COFE_Msk               (0x01UL << HRPWM0_CSG2_CC_COFE_Pos)                     /*!< HRPWM0_CSG2 CC: COFE Mask               */\r
+#define HRPWM0_CSG2_CC_COFM_Pos               18                                                      /*!< HRPWM0_CSG2 CC: COFM Position           */\r
+#define HRPWM0_CSG2_CC_COFM_Msk               (0x0fUL << HRPWM0_CSG2_CC_COFM_Pos)                     /*!< HRPWM0_CSG2 CC: COFM Mask               */\r
+#define HRPWM0_CSG2_CC_COFC_Pos               24                                                      /*!< HRPWM0_CSG2 CC: COFC Position           */\r
+#define HRPWM0_CSG2_CC_COFC_Msk               (0x03UL << HRPWM0_CSG2_CC_COFC_Pos)                     /*!< HRPWM0_CSG2 CC: COFC Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_PLC  ------------------------------ */\r
+#define HRPWM0_CSG2_PLC_IPLS_Pos              0                                                       /*!< HRPWM0_CSG2 PLC: IPLS Position          */\r
+#define HRPWM0_CSG2_PLC_IPLS_Msk              (0x0fUL << HRPWM0_CSG2_PLC_IPLS_Pos)                    /*!< HRPWM0_CSG2 PLC: IPLS Mask              */\r
+#define HRPWM0_CSG2_PLC_PLCL_Pos              8                                                       /*!< HRPWM0_CSG2 PLC: PLCL Position          */\r
+#define HRPWM0_CSG2_PLC_PLCL_Msk              (0x03UL << HRPWM0_CSG2_PLC_PLCL_Pos)                    /*!< HRPWM0_CSG2 PLC: PLCL Mask              */\r
+#define HRPWM0_CSG2_PLC_PSL_Pos               10                                                      /*!< HRPWM0_CSG2 PLC: PSL Position           */\r
+#define HRPWM0_CSG2_PLC_PSL_Msk               (0x01UL << HRPWM0_CSG2_PLC_PSL_Pos)                     /*!< HRPWM0_CSG2 PLC: PSL Mask               */\r
+#define HRPWM0_CSG2_PLC_PLSW_Pos              11                                                      /*!< HRPWM0_CSG2 PLC: PLSW Position          */\r
+#define HRPWM0_CSG2_PLC_PLSW_Msk              (0x01UL << HRPWM0_CSG2_PLC_PLSW_Pos)                    /*!< HRPWM0_CSG2 PLC: PLSW Mask              */\r
+#define HRPWM0_CSG2_PLC_PLEC_Pos              12                                                      /*!< HRPWM0_CSG2 PLC: PLEC Position          */\r
+#define HRPWM0_CSG2_PLC_PLEC_Msk              (0x03UL << HRPWM0_CSG2_PLC_PLEC_Pos)                    /*!< HRPWM0_CSG2 PLC: PLEC Mask              */\r
+#define HRPWM0_CSG2_PLC_PLXC_Pos              14                                                      /*!< HRPWM0_CSG2 PLC: PLXC Position          */\r
+#define HRPWM0_CSG2_PLC_PLXC_Msk              (0x03UL << HRPWM0_CSG2_PLC_PLXC_Pos)                    /*!< HRPWM0_CSG2 PLC: PLXC Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_BLV  ------------------------------ */\r
+#define HRPWM0_CSG2_BLV_BLV_Pos               0                                                       /*!< HRPWM0_CSG2 BLV: BLV Position           */\r
+#define HRPWM0_CSG2_BLV_BLV_Msk               (0x000000ffUL << HRPWM0_CSG2_BLV_BLV_Pos)               /*!< HRPWM0_CSG2 BLV: BLV Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SRE  ------------------------------ */\r
+#define HRPWM0_CSG2_SRE_VLS1E_Pos             0                                                       /*!< HRPWM0_CSG2 SRE: VLS1E Position         */\r
+#define HRPWM0_CSG2_SRE_VLS1E_Msk             (0x01UL << HRPWM0_CSG2_SRE_VLS1E_Pos)                   /*!< HRPWM0_CSG2 SRE: VLS1E Mask             */\r
+#define HRPWM0_CSG2_SRE_VLS2E_Pos             1                                                       /*!< HRPWM0_CSG2 SRE: VLS2E Position         */\r
+#define HRPWM0_CSG2_SRE_VLS2E_Msk             (0x01UL << HRPWM0_CSG2_SRE_VLS2E_Pos)                   /*!< HRPWM0_CSG2 SRE: VLS2E Mask             */\r
+#define HRPWM0_CSG2_SRE_TRGSE_Pos             2                                                       /*!< HRPWM0_CSG2 SRE: TRGSE Position         */\r
+#define HRPWM0_CSG2_SRE_TRGSE_Msk             (0x01UL << HRPWM0_CSG2_SRE_TRGSE_Pos)                   /*!< HRPWM0_CSG2 SRE: TRGSE Mask             */\r
+#define HRPWM0_CSG2_SRE_STRSE_Pos             3                                                       /*!< HRPWM0_CSG2 SRE: STRSE Position         */\r
+#define HRPWM0_CSG2_SRE_STRSE_Msk             (0x01UL << HRPWM0_CSG2_SRE_STRSE_Pos)                   /*!< HRPWM0_CSG2 SRE: STRSE Mask             */\r
+#define HRPWM0_CSG2_SRE_STPSE_Pos             4                                                       /*!< HRPWM0_CSG2 SRE: STPSE Position         */\r
+#define HRPWM0_CSG2_SRE_STPSE_Msk             (0x01UL << HRPWM0_CSG2_SRE_STPSE_Pos)                   /*!< HRPWM0_CSG2 SRE: STPSE Mask             */\r
+#define HRPWM0_CSG2_SRE_STDE_Pos              5                                                       /*!< HRPWM0_CSG2 SRE: STDE Position          */\r
+#define HRPWM0_CSG2_SRE_STDE_Msk              (0x01UL << HRPWM0_CSG2_SRE_STDE_Pos)                    /*!< HRPWM0_CSG2 SRE: STDE Mask              */\r
+#define HRPWM0_CSG2_SRE_CRSE_Pos              6                                                       /*!< HRPWM0_CSG2 SRE: CRSE Position          */\r
+#define HRPWM0_CSG2_SRE_CRSE_Msk              (0x01UL << HRPWM0_CSG2_SRE_CRSE_Pos)                    /*!< HRPWM0_CSG2 SRE: CRSE Mask              */\r
+#define HRPWM0_CSG2_SRE_CFSE_Pos              7                                                       /*!< HRPWM0_CSG2 SRE: CFSE Position          */\r
+#define HRPWM0_CSG2_SRE_CFSE_Msk              (0x01UL << HRPWM0_CSG2_SRE_CFSE_Pos)                    /*!< HRPWM0_CSG2 SRE: CFSE Mask              */\r
+#define HRPWM0_CSG2_SRE_CSEE_Pos              8                                                       /*!< HRPWM0_CSG2 SRE: CSEE Position          */\r
+#define HRPWM0_CSG2_SRE_CSEE_Msk              (0x01UL << HRPWM0_CSG2_SRE_CSEE_Pos)                    /*!< HRPWM0_CSG2 SRE: CSEE Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SRS  ------------------------------ */\r
+#define HRPWM0_CSG2_SRS_VLS1S_Pos             0                                                       /*!< HRPWM0_CSG2 SRS: VLS1S Position         */\r
+#define HRPWM0_CSG2_SRS_VLS1S_Msk             (0x03UL << HRPWM0_CSG2_SRS_VLS1S_Pos)                   /*!< HRPWM0_CSG2 SRS: VLS1S Mask             */\r
+#define HRPWM0_CSG2_SRS_VLS2S_Pos             2                                                       /*!< HRPWM0_CSG2 SRS: VLS2S Position         */\r
+#define HRPWM0_CSG2_SRS_VLS2S_Msk             (0x03UL << HRPWM0_CSG2_SRS_VLS2S_Pos)                   /*!< HRPWM0_CSG2 SRS: VLS2S Mask             */\r
+#define HRPWM0_CSG2_SRS_TRLS_Pos              4                                                       /*!< HRPWM0_CSG2 SRS: TRLS Position          */\r
+#define HRPWM0_CSG2_SRS_TRLS_Msk              (0x03UL << HRPWM0_CSG2_SRS_TRLS_Pos)                    /*!< HRPWM0_CSG2 SRS: TRLS Mask              */\r
+#define HRPWM0_CSG2_SRS_SSLS_Pos              6                                                       /*!< HRPWM0_CSG2 SRS: SSLS Position          */\r
+#define HRPWM0_CSG2_SRS_SSLS_Msk              (0x03UL << HRPWM0_CSG2_SRS_SSLS_Pos)                    /*!< HRPWM0_CSG2 SRS: SSLS Mask              */\r
+#define HRPWM0_CSG2_SRS_STLS_Pos              8                                                       /*!< HRPWM0_CSG2 SRS: STLS Position          */\r
+#define HRPWM0_CSG2_SRS_STLS_Msk              (0x03UL << HRPWM0_CSG2_SRS_STLS_Pos)                    /*!< HRPWM0_CSG2 SRS: STLS Mask              */\r
+#define HRPWM0_CSG2_SRS_CRFLS_Pos             10                                                      /*!< HRPWM0_CSG2 SRS: CRFLS Position         */\r
+#define HRPWM0_CSG2_SRS_CRFLS_Msk             (0x03UL << HRPWM0_CSG2_SRS_CRFLS_Pos)                   /*!< HRPWM0_CSG2 SRS: CRFLS Mask             */\r
+#define HRPWM0_CSG2_SRS_CSLS_Pos              12                                                      /*!< HRPWM0_CSG2 SRS: CSLS Position          */\r
+#define HRPWM0_CSG2_SRS_CSLS_Msk              (0x03UL << HRPWM0_CSG2_SRS_CSLS_Pos)                    /*!< HRPWM0_CSG2 SRS: CSLS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SWS  ------------------------------ */\r
+#define HRPWM0_CSG2_SWS_SVLS1_Pos             0                                                       /*!< HRPWM0_CSG2 SWS: SVLS1 Position         */\r
+#define HRPWM0_CSG2_SWS_SVLS1_Msk             (0x01UL << HRPWM0_CSG2_SWS_SVLS1_Pos)                   /*!< HRPWM0_CSG2 SWS: SVLS1 Mask             */\r
+#define HRPWM0_CSG2_SWS_SVLS2_Pos             1                                                       /*!< HRPWM0_CSG2 SWS: SVLS2 Position         */\r
+#define HRPWM0_CSG2_SWS_SVLS2_Msk             (0x01UL << HRPWM0_CSG2_SWS_SVLS2_Pos)                   /*!< HRPWM0_CSG2 SWS: SVLS2 Mask             */\r
+#define HRPWM0_CSG2_SWS_STRGS_Pos             2                                                       /*!< HRPWM0_CSG2 SWS: STRGS Position         */\r
+#define HRPWM0_CSG2_SWS_STRGS_Msk             (0x01UL << HRPWM0_CSG2_SWS_STRGS_Pos)                   /*!< HRPWM0_CSG2 SWS: STRGS Mask             */\r
+#define HRPWM0_CSG2_SWS_SSTRS_Pos             3                                                       /*!< HRPWM0_CSG2 SWS: SSTRS Position         */\r
+#define HRPWM0_CSG2_SWS_SSTRS_Msk             (0x01UL << HRPWM0_CSG2_SWS_SSTRS_Pos)                   /*!< HRPWM0_CSG2 SWS: SSTRS Mask             */\r
+#define HRPWM0_CSG2_SWS_SSTPS_Pos             4                                                       /*!< HRPWM0_CSG2 SWS: SSTPS Position         */\r
+#define HRPWM0_CSG2_SWS_SSTPS_Msk             (0x01UL << HRPWM0_CSG2_SWS_SSTPS_Pos)                   /*!< HRPWM0_CSG2 SWS: SSTPS Mask             */\r
+#define HRPWM0_CSG2_SWS_SSTD_Pos              5                                                       /*!< HRPWM0_CSG2 SWS: SSTD Position          */\r
+#define HRPWM0_CSG2_SWS_SSTD_Msk              (0x01UL << HRPWM0_CSG2_SWS_SSTD_Pos)                    /*!< HRPWM0_CSG2 SWS: SSTD Mask              */\r
+#define HRPWM0_CSG2_SWS_SCRS_Pos              6                                                       /*!< HRPWM0_CSG2 SWS: SCRS Position          */\r
+#define HRPWM0_CSG2_SWS_SCRS_Msk              (0x01UL << HRPWM0_CSG2_SWS_SCRS_Pos)                    /*!< HRPWM0_CSG2 SWS: SCRS Mask              */\r
+#define HRPWM0_CSG2_SWS_SCFS_Pos              7                                                       /*!< HRPWM0_CSG2 SWS: SCFS Position          */\r
+#define HRPWM0_CSG2_SWS_SCFS_Msk              (0x01UL << HRPWM0_CSG2_SWS_SCFS_Pos)                    /*!< HRPWM0_CSG2 SWS: SCFS Mask              */\r
+#define HRPWM0_CSG2_SWS_SCSS_Pos              8                                                       /*!< HRPWM0_CSG2 SWS: SCSS Position          */\r
+#define HRPWM0_CSG2_SWS_SCSS_Msk              (0x01UL << HRPWM0_CSG2_SWS_SCSS_Pos)                    /*!< HRPWM0_CSG2 SWS: SCSS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SWC  ------------------------------ */\r
+#define HRPWM0_CSG2_SWC_CVLS1_Pos             0                                                       /*!< HRPWM0_CSG2 SWC: CVLS1 Position         */\r
+#define HRPWM0_CSG2_SWC_CVLS1_Msk             (0x01UL << HRPWM0_CSG2_SWC_CVLS1_Pos)                   /*!< HRPWM0_CSG2 SWC: CVLS1 Mask             */\r
+#define HRPWM0_CSG2_SWC_CVLS2_Pos             1                                                       /*!< HRPWM0_CSG2 SWC: CVLS2 Position         */\r
+#define HRPWM0_CSG2_SWC_CVLS2_Msk             (0x01UL << HRPWM0_CSG2_SWC_CVLS2_Pos)                   /*!< HRPWM0_CSG2 SWC: CVLS2 Mask             */\r
+#define HRPWM0_CSG2_SWC_CTRGS_Pos             2                                                       /*!< HRPWM0_CSG2 SWC: CTRGS Position         */\r
+#define HRPWM0_CSG2_SWC_CTRGS_Msk             (0x01UL << HRPWM0_CSG2_SWC_CTRGS_Pos)                   /*!< HRPWM0_CSG2 SWC: CTRGS Mask             */\r
+#define HRPWM0_CSG2_SWC_CSTRS_Pos             3                                                       /*!< HRPWM0_CSG2 SWC: CSTRS Position         */\r
+#define HRPWM0_CSG2_SWC_CSTRS_Msk             (0x01UL << HRPWM0_CSG2_SWC_CSTRS_Pos)                   /*!< HRPWM0_CSG2 SWC: CSTRS Mask             */\r
+#define HRPWM0_CSG2_SWC_CSTPS_Pos             4                                                       /*!< HRPWM0_CSG2 SWC: CSTPS Position         */\r
+#define HRPWM0_CSG2_SWC_CSTPS_Msk             (0x01UL << HRPWM0_CSG2_SWC_CSTPS_Pos)                   /*!< HRPWM0_CSG2 SWC: CSTPS Mask             */\r
+#define HRPWM0_CSG2_SWC_CSTD_Pos              5                                                       /*!< HRPWM0_CSG2 SWC: CSTD Position          */\r
+#define HRPWM0_CSG2_SWC_CSTD_Msk              (0x01UL << HRPWM0_CSG2_SWC_CSTD_Pos)                    /*!< HRPWM0_CSG2 SWC: CSTD Mask              */\r
+#define HRPWM0_CSG2_SWC_CCRS_Pos              6                                                       /*!< HRPWM0_CSG2 SWC: CCRS Position          */\r
+#define HRPWM0_CSG2_SWC_CCRS_Msk              (0x01UL << HRPWM0_CSG2_SWC_CCRS_Pos)                    /*!< HRPWM0_CSG2 SWC: CCRS Mask              */\r
+#define HRPWM0_CSG2_SWC_CCFS_Pos              7                                                       /*!< HRPWM0_CSG2 SWC: CCFS Position          */\r
+#define HRPWM0_CSG2_SWC_CCFS_Msk              (0x01UL << HRPWM0_CSG2_SWC_CCFS_Pos)                    /*!< HRPWM0_CSG2 SWC: CCFS Mask              */\r
+#define HRPWM0_CSG2_SWC_CCSS_Pos              8                                                       /*!< HRPWM0_CSG2 SWC: CCSS Position          */\r
+#define HRPWM0_CSG2_SWC_CCSS_Msk              (0x01UL << HRPWM0_CSG2_SWC_CCSS_Pos)                    /*!< HRPWM0_CSG2 SWC: CCSS Mask              */\r
+\r
+/* ------------------------------  HRPWM0_CSG2_ISTAT  ----------------------------- */\r
+#define HRPWM0_CSG2_ISTAT_VLS1S_Pos           0                                                       /*!< HRPWM0_CSG2 ISTAT: VLS1S Position       */\r
+#define HRPWM0_CSG2_ISTAT_VLS1S_Msk           (0x01UL << HRPWM0_CSG2_ISTAT_VLS1S_Pos)                 /*!< HRPWM0_CSG2 ISTAT: VLS1S Mask           */\r
+#define HRPWM0_CSG2_ISTAT_VLS2S_Pos           1                                                       /*!< HRPWM0_CSG2 ISTAT: VLS2S Position       */\r
+#define HRPWM0_CSG2_ISTAT_VLS2S_Msk           (0x01UL << HRPWM0_CSG2_ISTAT_VLS2S_Pos)                 /*!< HRPWM0_CSG2 ISTAT: VLS2S Mask           */\r
+#define HRPWM0_CSG2_ISTAT_TRGSS_Pos           2                                                       /*!< HRPWM0_CSG2 ISTAT: TRGSS Position       */\r
+#define HRPWM0_CSG2_ISTAT_TRGSS_Msk           (0x01UL << HRPWM0_CSG2_ISTAT_TRGSS_Pos)                 /*!< HRPWM0_CSG2 ISTAT: TRGSS Mask           */\r
+#define HRPWM0_CSG2_ISTAT_STRSS_Pos           3                                                       /*!< HRPWM0_CSG2 ISTAT: STRSS Position       */\r
+#define HRPWM0_CSG2_ISTAT_STRSS_Msk           (0x01UL << HRPWM0_CSG2_ISTAT_STRSS_Pos)                 /*!< HRPWM0_CSG2 ISTAT: STRSS Mask           */\r
+#define HRPWM0_CSG2_ISTAT_STPSS_Pos           4                                                       /*!< HRPWM0_CSG2 ISTAT: STPSS Position       */\r
+#define HRPWM0_CSG2_ISTAT_STPSS_Msk           (0x01UL << HRPWM0_CSG2_ISTAT_STPSS_Pos)                 /*!< HRPWM0_CSG2 ISTAT: STPSS Mask           */\r
+#define HRPWM0_CSG2_ISTAT_STDS_Pos            5                                                       /*!< HRPWM0_CSG2 ISTAT: STDS Position        */\r
+#define HRPWM0_CSG2_ISTAT_STDS_Msk            (0x01UL << HRPWM0_CSG2_ISTAT_STDS_Pos)                  /*!< HRPWM0_CSG2 ISTAT: STDS Mask            */\r
+#define HRPWM0_CSG2_ISTAT_CRSS_Pos            6                                                       /*!< HRPWM0_CSG2 ISTAT: CRSS Position        */\r
+#define HRPWM0_CSG2_ISTAT_CRSS_Msk            (0x01UL << HRPWM0_CSG2_ISTAT_CRSS_Pos)                  /*!< HRPWM0_CSG2 ISTAT: CRSS Mask            */\r
+#define HRPWM0_CSG2_ISTAT_CFSS_Pos            7                                                       /*!< HRPWM0_CSG2 ISTAT: CFSS Position        */\r
+#define HRPWM0_CSG2_ISTAT_CFSS_Msk            (0x01UL << HRPWM0_CSG2_ISTAT_CFSS_Pos)                  /*!< HRPWM0_CSG2 ISTAT: CFSS Mask            */\r
+#define HRPWM0_CSG2_ISTAT_CSES_Pos            8                                                       /*!< HRPWM0_CSG2 ISTAT: CSES Position        */\r
+#define HRPWM0_CSG2_ISTAT_CSES_Msk            (0x01UL << HRPWM0_CSG2_ISTAT_CSES_Pos)                  /*!< HRPWM0_CSG2 ISTAT: CSES Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       Group 'HRPWM0_HRC' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  HRPWM0_HRC_GC  ------------------------------- */\r
+#define HRPWM0_HRC_GC_HRM0_Pos                0                                                       /*!< HRPWM0_HRC GC: HRM0 Position            */\r
+#define HRPWM0_HRC_GC_HRM0_Msk                (0x03UL << HRPWM0_HRC_GC_HRM0_Pos)                      /*!< HRPWM0_HRC GC: HRM0 Mask                */\r
+#define HRPWM0_HRC_GC_HRM1_Pos                2                                                       /*!< HRPWM0_HRC GC: HRM1 Position            */\r
+#define HRPWM0_HRC_GC_HRM1_Msk                (0x03UL << HRPWM0_HRC_GC_HRM1_Pos)                      /*!< HRPWM0_HRC GC: HRM1 Mask                */\r
+#define HRPWM0_HRC_GC_DTE_Pos                 8                                                       /*!< HRPWM0_HRC GC: DTE Position             */\r
+#define HRPWM0_HRC_GC_DTE_Msk                 (0x01UL << HRPWM0_HRC_GC_DTE_Pos)                       /*!< HRPWM0_HRC GC: DTE Mask                 */\r
+#define HRPWM0_HRC_GC_TR0E_Pos                9                                                       /*!< HRPWM0_HRC GC: TR0E Position            */\r
+#define HRPWM0_HRC_GC_TR0E_Msk                (0x01UL << HRPWM0_HRC_GC_TR0E_Pos)                      /*!< HRPWM0_HRC GC: TR0E Mask                */\r
+#define HRPWM0_HRC_GC_TR1E_Pos                10                                                      /*!< HRPWM0_HRC GC: TR1E Position            */\r
+#define HRPWM0_HRC_GC_TR1E_Msk                (0x01UL << HRPWM0_HRC_GC_TR1E_Pos)                      /*!< HRPWM0_HRC GC: TR1E Mask                */\r
+#define HRPWM0_HRC_GC_STC_Pos                 11                                                      /*!< HRPWM0_HRC GC: STC Position             */\r
+#define HRPWM0_HRC_GC_STC_Msk                 (0x01UL << HRPWM0_HRC_GC_STC_Pos)                       /*!< HRPWM0_HRC GC: STC Mask                 */\r
+#define HRPWM0_HRC_GC_DSTC_Pos                12                                                      /*!< HRPWM0_HRC GC: DSTC Position            */\r
+#define HRPWM0_HRC_GC_DSTC_Msk                (0x01UL << HRPWM0_HRC_GC_DSTC_Pos)                      /*!< HRPWM0_HRC GC: DSTC Mask                */\r
+#define HRPWM0_HRC_GC_OCS0_Pos                13                                                      /*!< HRPWM0_HRC GC: OCS0 Position            */\r
+#define HRPWM0_HRC_GC_OCS0_Msk                (0x01UL << HRPWM0_HRC_GC_OCS0_Pos)                      /*!< HRPWM0_HRC GC: OCS0 Mask                */\r
+#define HRPWM0_HRC_GC_OCS1_Pos                14                                                      /*!< HRPWM0_HRC GC: OCS1 Position            */\r
+#define HRPWM0_HRC_GC_OCS1_Msk                (0x01UL << HRPWM0_HRC_GC_OCS1_Pos)                      /*!< HRPWM0_HRC GC: OCS1 Mask                */\r
+#define HRPWM0_HRC_GC_DTUS_Pos                16                                                      /*!< HRPWM0_HRC GC: DTUS Position            */\r
+#define HRPWM0_HRC_GC_DTUS_Msk                (0x01UL << HRPWM0_HRC_GC_DTUS_Pos)                      /*!< HRPWM0_HRC GC: DTUS Mask                */\r
+\r
+/* --------------------------------  HRPWM0_HRC_PL  ------------------------------- */\r
+#define HRPWM0_HRC_PL_PSL0_Pos                0                                                       /*!< HRPWM0_HRC PL: PSL0 Position            */\r
+#define HRPWM0_HRC_PL_PSL0_Msk                (0x01UL << HRPWM0_HRC_PL_PSL0_Pos)                      /*!< HRPWM0_HRC PL: PSL0 Mask                */\r
+#define HRPWM0_HRC_PL_PSL1_Pos                1                                                       /*!< HRPWM0_HRC PL: PSL1 Position            */\r
+#define HRPWM0_HRC_PL_PSL1_Msk                (0x01UL << HRPWM0_HRC_PL_PSL1_Pos)                      /*!< HRPWM0_HRC PL: PSL1 Mask                */\r
+\r
+/* -------------------------------  HRPWM0_HRC_GSEL  ------------------------------ */\r
+#define HRPWM0_HRC_GSEL_C0SS_Pos              0                                                       /*!< HRPWM0_HRC GSEL: C0SS Position          */\r
+#define HRPWM0_HRC_GSEL_C0SS_Msk              (0x07UL << HRPWM0_HRC_GSEL_C0SS_Pos)                    /*!< HRPWM0_HRC GSEL: C0SS Mask              */\r
+#define HRPWM0_HRC_GSEL_C0CS_Pos              3                                                       /*!< HRPWM0_HRC GSEL: C0CS Position          */\r
+#define HRPWM0_HRC_GSEL_C0CS_Msk              (0x07UL << HRPWM0_HRC_GSEL_C0CS_Pos)                    /*!< HRPWM0_HRC GSEL: C0CS Mask              */\r
+#define HRPWM0_HRC_GSEL_S0M_Pos               6                                                       /*!< HRPWM0_HRC GSEL: S0M Position           */\r
+#define HRPWM0_HRC_GSEL_S0M_Msk               (0x03UL << HRPWM0_HRC_GSEL_S0M_Pos)                     /*!< HRPWM0_HRC GSEL: S0M Mask               */\r
+#define HRPWM0_HRC_GSEL_C0M_Pos               8                                                       /*!< HRPWM0_HRC GSEL: C0M Position           */\r
+#define HRPWM0_HRC_GSEL_C0M_Msk               (0x03UL << HRPWM0_HRC_GSEL_C0M_Pos)                     /*!< HRPWM0_HRC GSEL: C0M Mask               */\r
+#define HRPWM0_HRC_GSEL_S0ES_Pos              10                                                      /*!< HRPWM0_HRC GSEL: S0ES Position          */\r
+#define HRPWM0_HRC_GSEL_S0ES_Msk              (0x03UL << HRPWM0_HRC_GSEL_S0ES_Pos)                    /*!< HRPWM0_HRC GSEL: S0ES Mask              */\r
+#define HRPWM0_HRC_GSEL_C0ES_Pos              12                                                      /*!< HRPWM0_HRC GSEL: C0ES Position          */\r
+#define HRPWM0_HRC_GSEL_C0ES_Msk              (0x03UL << HRPWM0_HRC_GSEL_C0ES_Pos)                    /*!< HRPWM0_HRC GSEL: C0ES Mask              */\r
+#define HRPWM0_HRC_GSEL_C1SS_Pos              16                                                      /*!< HRPWM0_HRC GSEL: C1SS Position          */\r
+#define HRPWM0_HRC_GSEL_C1SS_Msk              (0x07UL << HRPWM0_HRC_GSEL_C1SS_Pos)                    /*!< HRPWM0_HRC GSEL: C1SS Mask              */\r
+#define HRPWM0_HRC_GSEL_C1CS_Pos              19                                                      /*!< HRPWM0_HRC GSEL: C1CS Position          */\r
+#define HRPWM0_HRC_GSEL_C1CS_Msk              (0x07UL << HRPWM0_HRC_GSEL_C1CS_Pos)                    /*!< HRPWM0_HRC GSEL: C1CS Mask              */\r
+#define HRPWM0_HRC_GSEL_S1M_Pos               22                                                      /*!< HRPWM0_HRC GSEL: S1M Position           */\r
+#define HRPWM0_HRC_GSEL_S1M_Msk               (0x03UL << HRPWM0_HRC_GSEL_S1M_Pos)                     /*!< HRPWM0_HRC GSEL: S1M Mask               */\r
+#define HRPWM0_HRC_GSEL_C1M_Pos               24                                                      /*!< HRPWM0_HRC GSEL: C1M Position           */\r
+#define HRPWM0_HRC_GSEL_C1M_Msk               (0x03UL << HRPWM0_HRC_GSEL_C1M_Pos)                     /*!< HRPWM0_HRC GSEL: C1M Mask               */\r
+#define HRPWM0_HRC_GSEL_S1ES_Pos              26                                                      /*!< HRPWM0_HRC GSEL: S1ES Position          */\r
+#define HRPWM0_HRC_GSEL_S1ES_Msk              (0x03UL << HRPWM0_HRC_GSEL_S1ES_Pos)                    /*!< HRPWM0_HRC GSEL: S1ES Mask              */\r
+#define HRPWM0_HRC_GSEL_C1ES_Pos              28                                                      /*!< HRPWM0_HRC GSEL: C1ES Position          */\r
+#define HRPWM0_HRC_GSEL_C1ES_Msk              (0x03UL << HRPWM0_HRC_GSEL_C1ES_Pos)                    /*!< HRPWM0_HRC GSEL: C1ES Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC_TSEL  ------------------------------ */\r
+#define HRPWM0_HRC_TSEL_TSEL0_Pos             0                                                       /*!< HRPWM0_HRC TSEL: TSEL0 Position         */\r
+#define HRPWM0_HRC_TSEL_TSEL0_Msk             (0x07UL << HRPWM0_HRC_TSEL_TSEL0_Pos)                   /*!< HRPWM0_HRC TSEL: TSEL0 Mask             */\r
+#define HRPWM0_HRC_TSEL_TSEL1_Pos             3                                                       /*!< HRPWM0_HRC TSEL: TSEL1 Position         */\r
+#define HRPWM0_HRC_TSEL_TSEL1_Msk             (0x07UL << HRPWM0_HRC_TSEL_TSEL1_Pos)                   /*!< HRPWM0_HRC TSEL: TSEL1 Mask             */\r
+#define HRPWM0_HRC_TSEL_TS0E_Pos              16                                                      /*!< HRPWM0_HRC TSEL: TS0E Position          */\r
+#define HRPWM0_HRC_TSEL_TS0E_Msk              (0x01UL << HRPWM0_HRC_TSEL_TS0E_Pos)                    /*!< HRPWM0_HRC TSEL: TS0E Mask              */\r
+#define HRPWM0_HRC_TSEL_TS1E_Pos              17                                                      /*!< HRPWM0_HRC TSEL: TS1E Position          */\r
+#define HRPWM0_HRC_TSEL_TS1E_Msk              (0x01UL << HRPWM0_HRC_TSEL_TS1E_Pos)                    /*!< HRPWM0_HRC TSEL: TS1E Mask              */\r
+\r
+/* --------------------------------  HRPWM0_HRC_SC  ------------------------------- */\r
+#define HRPWM0_HRC_SC_ST_Pos                  0                                                       /*!< HRPWM0_HRC SC: ST Position              */\r
+#define HRPWM0_HRC_SC_ST_Msk                  (0x01UL << HRPWM0_HRC_SC_ST_Pos)                        /*!< HRPWM0_HRC SC: ST Mask                  */\r
+\r
+/* -------------------------------  HRPWM0_HRC_DCR  ------------------------------- */\r
+#define HRPWM0_HRC_DCR_DTRV_Pos               0                                                       /*!< HRPWM0_HRC DCR: DTRV Position           */\r
+#define HRPWM0_HRC_DCR_DTRV_Msk               (0x0000ffffUL << HRPWM0_HRC_DCR_DTRV_Pos)               /*!< HRPWM0_HRC DCR: DTRV Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC_DCF  ------------------------------- */\r
+#define HRPWM0_HRC_DCF_DTFV_Pos               0                                                       /*!< HRPWM0_HRC DCF: DTFV Position           */\r
+#define HRPWM0_HRC_DCF_DTFV_Msk               (0x0000ffffUL << HRPWM0_HRC_DCF_DTFV_Pos)               /*!< HRPWM0_HRC DCF: DTFV Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC_CR1  ------------------------------- */\r
+#define HRPWM0_HRC_CR1_CR1_Pos                0                                                       /*!< HRPWM0_HRC CR1: CR1 Position            */\r
+#define HRPWM0_HRC_CR1_CR1_Msk                (0x000000ffUL << HRPWM0_HRC_CR1_CR1_Pos)                /*!< HRPWM0_HRC CR1: CR1 Mask                */\r
+\r
+/* -------------------------------  HRPWM0_HRC_CR2  ------------------------------- */\r
+#define HRPWM0_HRC_CR2_CR2_Pos                0                                                       /*!< HRPWM0_HRC CR2: CR2 Position            */\r
+#define HRPWM0_HRC_CR2_CR2_Msk                (0x000000ffUL << HRPWM0_HRC_CR2_CR2_Pos)                /*!< HRPWM0_HRC CR2: CR2 Mask                */\r
+\r
+/* -------------------------------  HRPWM0_HRC_SSC  ------------------------------- */\r
+#define HRPWM0_HRC_SSC_SST_Pos                0                                                       /*!< HRPWM0_HRC SSC: SST Position            */\r
+#define HRPWM0_HRC_SSC_SST_Msk                (0x01UL << HRPWM0_HRC_SSC_SST_Pos)                      /*!< HRPWM0_HRC SSC: SST Mask                */\r
+\r
+/* -------------------------------  HRPWM0_HRC_SDCR  ------------------------------ */\r
+#define HRPWM0_HRC_SDCR_SDTRV_Pos             0                                                       /*!< HRPWM0_HRC SDCR: SDTRV Position         */\r
+#define HRPWM0_HRC_SDCR_SDTRV_Msk             (0x0000ffffUL << HRPWM0_HRC_SDCR_SDTRV_Pos)             /*!< HRPWM0_HRC SDCR: SDTRV Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC_SDCF  ------------------------------ */\r
+#define HRPWM0_HRC_SDCF_SDTFV_Pos             0                                                       /*!< HRPWM0_HRC SDCF: SDTFV Position         */\r
+#define HRPWM0_HRC_SDCF_SDTFV_Msk             (0x0000ffffUL << HRPWM0_HRC_SDCF_SDTFV_Pos)             /*!< HRPWM0_HRC SDCF: SDTFV Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC_SCR1  ------------------------------ */\r
+#define HRPWM0_HRC_SCR1_SCR1_Pos              0                                                       /*!< HRPWM0_HRC SCR1: SCR1 Position          */\r
+#define HRPWM0_HRC_SCR1_SCR1_Msk              (0x000000ffUL << HRPWM0_HRC_SCR1_SCR1_Pos)              /*!< HRPWM0_HRC SCR1: SCR1 Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC_SCR2  ------------------------------ */\r
+#define HRPWM0_HRC_SCR2_SCR2_Pos              0                                                       /*!< HRPWM0_HRC SCR2: SCR2 Position          */\r
+#define HRPWM0_HRC_SCR2_SCR2_Msk              (0x000000ffUL << HRPWM0_HRC_SCR2_SCR2_Pos)              /*!< HRPWM0_HRC SCR2: SCR2 Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_HRC0' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_HRC0_GC  ------------------------------- */\r
+#define HRPWM0_HRC0_GC_HRM0_Pos               0                                                       /*!< HRPWM0_HRC0 GC: HRM0 Position           */\r
+#define HRPWM0_HRC0_GC_HRM0_Msk               (0x03UL << HRPWM0_HRC0_GC_HRM0_Pos)                     /*!< HRPWM0_HRC0 GC: HRM0 Mask               */\r
+#define HRPWM0_HRC0_GC_HRM1_Pos               2                                                       /*!< HRPWM0_HRC0 GC: HRM1 Position           */\r
+#define HRPWM0_HRC0_GC_HRM1_Msk               (0x03UL << HRPWM0_HRC0_GC_HRM1_Pos)                     /*!< HRPWM0_HRC0 GC: HRM1 Mask               */\r
+#define HRPWM0_HRC0_GC_DTE_Pos                8                                                       /*!< HRPWM0_HRC0 GC: DTE Position            */\r
+#define HRPWM0_HRC0_GC_DTE_Msk                (0x01UL << HRPWM0_HRC0_GC_DTE_Pos)                      /*!< HRPWM0_HRC0 GC: DTE Mask                */\r
+#define HRPWM0_HRC0_GC_TR0E_Pos               9                                                       /*!< HRPWM0_HRC0 GC: TR0E Position           */\r
+#define HRPWM0_HRC0_GC_TR0E_Msk               (0x01UL << HRPWM0_HRC0_GC_TR0E_Pos)                     /*!< HRPWM0_HRC0 GC: TR0E Mask               */\r
+#define HRPWM0_HRC0_GC_TR1E_Pos               10                                                      /*!< HRPWM0_HRC0 GC: TR1E Position           */\r
+#define HRPWM0_HRC0_GC_TR1E_Msk               (0x01UL << HRPWM0_HRC0_GC_TR1E_Pos)                     /*!< HRPWM0_HRC0 GC: TR1E Mask               */\r
+#define HRPWM0_HRC0_GC_STC_Pos                11                                                      /*!< HRPWM0_HRC0 GC: STC Position            */\r
+#define HRPWM0_HRC0_GC_STC_Msk                (0x01UL << HRPWM0_HRC0_GC_STC_Pos)                      /*!< HRPWM0_HRC0 GC: STC Mask                */\r
+#define HRPWM0_HRC0_GC_DSTC_Pos               12                                                      /*!< HRPWM0_HRC0 GC: DSTC Position           */\r
+#define HRPWM0_HRC0_GC_DSTC_Msk               (0x01UL << HRPWM0_HRC0_GC_DSTC_Pos)                     /*!< HRPWM0_HRC0 GC: DSTC Mask               */\r
+#define HRPWM0_HRC0_GC_OCS0_Pos               13                                                      /*!< HRPWM0_HRC0 GC: OCS0 Position           */\r
+#define HRPWM0_HRC0_GC_OCS0_Msk               (0x01UL << HRPWM0_HRC0_GC_OCS0_Pos)                     /*!< HRPWM0_HRC0 GC: OCS0 Mask               */\r
+#define HRPWM0_HRC0_GC_OCS1_Pos               14                                                      /*!< HRPWM0_HRC0 GC: OCS1 Position           */\r
+#define HRPWM0_HRC0_GC_OCS1_Msk               (0x01UL << HRPWM0_HRC0_GC_OCS1_Pos)                     /*!< HRPWM0_HRC0 GC: OCS1 Mask               */\r
+#define HRPWM0_HRC0_GC_DTUS_Pos               16                                                      /*!< HRPWM0_HRC0 GC: DTUS Position           */\r
+#define HRPWM0_HRC0_GC_DTUS_Msk               (0x01UL << HRPWM0_HRC0_GC_DTUS_Pos)                     /*!< HRPWM0_HRC0 GC: DTUS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_PL  ------------------------------- */\r
+#define HRPWM0_HRC0_PL_PSL0_Pos               0                                                       /*!< HRPWM0_HRC0 PL: PSL0 Position           */\r
+#define HRPWM0_HRC0_PL_PSL0_Msk               (0x01UL << HRPWM0_HRC0_PL_PSL0_Pos)                     /*!< HRPWM0_HRC0 PL: PSL0 Mask               */\r
+#define HRPWM0_HRC0_PL_PSL1_Pos               1                                                       /*!< HRPWM0_HRC0 PL: PSL1 Position           */\r
+#define HRPWM0_HRC0_PL_PSL1_Msk               (0x01UL << HRPWM0_HRC0_PL_PSL1_Pos)                     /*!< HRPWM0_HRC0 PL: PSL1 Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_GSEL  ------------------------------ */\r
+#define HRPWM0_HRC0_GSEL_C0SS_Pos             0                                                       /*!< HRPWM0_HRC0 GSEL: C0SS Position         */\r
+#define HRPWM0_HRC0_GSEL_C0SS_Msk             (0x07UL << HRPWM0_HRC0_GSEL_C0SS_Pos)                   /*!< HRPWM0_HRC0 GSEL: C0SS Mask             */\r
+#define HRPWM0_HRC0_GSEL_C0CS_Pos             3                                                       /*!< HRPWM0_HRC0 GSEL: C0CS Position         */\r
+#define HRPWM0_HRC0_GSEL_C0CS_Msk             (0x07UL << HRPWM0_HRC0_GSEL_C0CS_Pos)                   /*!< HRPWM0_HRC0 GSEL: C0CS Mask             */\r
+#define HRPWM0_HRC0_GSEL_S0M_Pos              6                                                       /*!< HRPWM0_HRC0 GSEL: S0M Position          */\r
+#define HRPWM0_HRC0_GSEL_S0M_Msk              (0x03UL << HRPWM0_HRC0_GSEL_S0M_Pos)                    /*!< HRPWM0_HRC0 GSEL: S0M Mask              */\r
+#define HRPWM0_HRC0_GSEL_C0M_Pos              8                                                       /*!< HRPWM0_HRC0 GSEL: C0M Position          */\r
+#define HRPWM0_HRC0_GSEL_C0M_Msk              (0x03UL << HRPWM0_HRC0_GSEL_C0M_Pos)                    /*!< HRPWM0_HRC0 GSEL: C0M Mask              */\r
+#define HRPWM0_HRC0_GSEL_S0ES_Pos             10                                                      /*!< HRPWM0_HRC0 GSEL: S0ES Position         */\r
+#define HRPWM0_HRC0_GSEL_S0ES_Msk             (0x03UL << HRPWM0_HRC0_GSEL_S0ES_Pos)                   /*!< HRPWM0_HRC0 GSEL: S0ES Mask             */\r
+#define HRPWM0_HRC0_GSEL_C0ES_Pos             12                                                      /*!< HRPWM0_HRC0 GSEL: C0ES Position         */\r
+#define HRPWM0_HRC0_GSEL_C0ES_Msk             (0x03UL << HRPWM0_HRC0_GSEL_C0ES_Pos)                   /*!< HRPWM0_HRC0 GSEL: C0ES Mask             */\r
+#define HRPWM0_HRC0_GSEL_C1SS_Pos             16                                                      /*!< HRPWM0_HRC0 GSEL: C1SS Position         */\r
+#define HRPWM0_HRC0_GSEL_C1SS_Msk             (0x07UL << HRPWM0_HRC0_GSEL_C1SS_Pos)                   /*!< HRPWM0_HRC0 GSEL: C1SS Mask             */\r
+#define HRPWM0_HRC0_GSEL_C1CS_Pos             19                                                      /*!< HRPWM0_HRC0 GSEL: C1CS Position         */\r
+#define HRPWM0_HRC0_GSEL_C1CS_Msk             (0x07UL << HRPWM0_HRC0_GSEL_C1CS_Pos)                   /*!< HRPWM0_HRC0 GSEL: C1CS Mask             */\r
+#define HRPWM0_HRC0_GSEL_S1M_Pos              22                                                      /*!< HRPWM0_HRC0 GSEL: S1M Position          */\r
+#define HRPWM0_HRC0_GSEL_S1M_Msk              (0x03UL << HRPWM0_HRC0_GSEL_S1M_Pos)                    /*!< HRPWM0_HRC0 GSEL: S1M Mask              */\r
+#define HRPWM0_HRC0_GSEL_C1M_Pos              24                                                      /*!< HRPWM0_HRC0 GSEL: C1M Position          */\r
+#define HRPWM0_HRC0_GSEL_C1M_Msk              (0x03UL << HRPWM0_HRC0_GSEL_C1M_Pos)                    /*!< HRPWM0_HRC0 GSEL: C1M Mask              */\r
+#define HRPWM0_HRC0_GSEL_S1ES_Pos             26                                                      /*!< HRPWM0_HRC0 GSEL: S1ES Position         */\r
+#define HRPWM0_HRC0_GSEL_S1ES_Msk             (0x03UL << HRPWM0_HRC0_GSEL_S1ES_Pos)                   /*!< HRPWM0_HRC0 GSEL: S1ES Mask             */\r
+#define HRPWM0_HRC0_GSEL_C1ES_Pos             28                                                      /*!< HRPWM0_HRC0 GSEL: C1ES Position         */\r
+#define HRPWM0_HRC0_GSEL_C1ES_Msk             (0x03UL << HRPWM0_HRC0_GSEL_C1ES_Pos)                   /*!< HRPWM0_HRC0 GSEL: C1ES Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_TSEL  ------------------------------ */\r
+#define HRPWM0_HRC0_TSEL_TSEL0_Pos            0                                                       /*!< HRPWM0_HRC0 TSEL: TSEL0 Position        */\r
+#define HRPWM0_HRC0_TSEL_TSEL0_Msk            (0x07UL << HRPWM0_HRC0_TSEL_TSEL0_Pos)                  /*!< HRPWM0_HRC0 TSEL: TSEL0 Mask            */\r
+#define HRPWM0_HRC0_TSEL_TSEL1_Pos            3                                                       /*!< HRPWM0_HRC0 TSEL: TSEL1 Position        */\r
+#define HRPWM0_HRC0_TSEL_TSEL1_Msk            (0x07UL << HRPWM0_HRC0_TSEL_TSEL1_Pos)                  /*!< HRPWM0_HRC0 TSEL: TSEL1 Mask            */\r
+#define HRPWM0_HRC0_TSEL_TS0E_Pos             16                                                      /*!< HRPWM0_HRC0 TSEL: TS0E Position         */\r
+#define HRPWM0_HRC0_TSEL_TS0E_Msk             (0x01UL << HRPWM0_HRC0_TSEL_TS0E_Pos)                   /*!< HRPWM0_HRC0 TSEL: TS0E Mask             */\r
+#define HRPWM0_HRC0_TSEL_TS1E_Pos             17                                                      /*!< HRPWM0_HRC0 TSEL: TS1E Position         */\r
+#define HRPWM0_HRC0_TSEL_TS1E_Msk             (0x01UL << HRPWM0_HRC0_TSEL_TS1E_Pos)                   /*!< HRPWM0_HRC0 TSEL: TS1E Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_SC  ------------------------------- */\r
+#define HRPWM0_HRC0_SC_ST_Pos                 0                                                       /*!< HRPWM0_HRC0 SC: ST Position             */\r
+#define HRPWM0_HRC0_SC_ST_Msk                 (0x01UL << HRPWM0_HRC0_SC_ST_Pos)                       /*!< HRPWM0_HRC0 SC: ST Mask                 */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_DCR  ------------------------------ */\r
+#define HRPWM0_HRC0_DCR_DTRV_Pos              0                                                       /*!< HRPWM0_HRC0 DCR: DTRV Position          */\r
+#define HRPWM0_HRC0_DCR_DTRV_Msk              (0x0000ffffUL << HRPWM0_HRC0_DCR_DTRV_Pos)              /*!< HRPWM0_HRC0 DCR: DTRV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_DCF  ------------------------------ */\r
+#define HRPWM0_HRC0_DCF_DTFV_Pos              0                                                       /*!< HRPWM0_HRC0 DCF: DTFV Position          */\r
+#define HRPWM0_HRC0_DCF_DTFV_Msk              (0x0000ffffUL << HRPWM0_HRC0_DCF_DTFV_Pos)              /*!< HRPWM0_HRC0 DCF: DTFV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_CR1  ------------------------------ */\r
+#define HRPWM0_HRC0_CR1_CR1_Pos               0                                                       /*!< HRPWM0_HRC0 CR1: CR1 Position           */\r
+#define HRPWM0_HRC0_CR1_CR1_Msk               (0x000000ffUL << HRPWM0_HRC0_CR1_CR1_Pos)               /*!< HRPWM0_HRC0 CR1: CR1 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_CR2  ------------------------------ */\r
+#define HRPWM0_HRC0_CR2_CR2_Pos               0                                                       /*!< HRPWM0_HRC0 CR2: CR2 Position           */\r
+#define HRPWM0_HRC0_CR2_CR2_Msk               (0x000000ffUL << HRPWM0_HRC0_CR2_CR2_Pos)               /*!< HRPWM0_HRC0 CR2: CR2 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_SSC  ------------------------------ */\r
+#define HRPWM0_HRC0_SSC_SST_Pos               0                                                       /*!< HRPWM0_HRC0 SSC: SST Position           */\r
+#define HRPWM0_HRC0_SSC_SST_Msk               (0x01UL << HRPWM0_HRC0_SSC_SST_Pos)                     /*!< HRPWM0_HRC0 SSC: SST Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_SDCR  ------------------------------ */\r
+#define HRPWM0_HRC0_SDCR_SDTRV_Pos            0                                                       /*!< HRPWM0_HRC0 SDCR: SDTRV Position        */\r
+#define HRPWM0_HRC0_SDCR_SDTRV_Msk            (0x0000ffffUL << HRPWM0_HRC0_SDCR_SDTRV_Pos)            /*!< HRPWM0_HRC0 SDCR: SDTRV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_SDCF  ------------------------------ */\r
+#define HRPWM0_HRC0_SDCF_SDTFV_Pos            0                                                       /*!< HRPWM0_HRC0 SDCF: SDTFV Position        */\r
+#define HRPWM0_HRC0_SDCF_SDTFV_Msk            (0x0000ffffUL << HRPWM0_HRC0_SDCF_SDTFV_Pos)            /*!< HRPWM0_HRC0 SDCF: SDTFV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_SCR1  ------------------------------ */\r
+#define HRPWM0_HRC0_SCR1_SCR1_Pos             0                                                       /*!< HRPWM0_HRC0 SCR1: SCR1 Position         */\r
+#define HRPWM0_HRC0_SCR1_SCR1_Msk             (0x000000ffUL << HRPWM0_HRC0_SCR1_SCR1_Pos)             /*!< HRPWM0_HRC0 SCR1: SCR1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_SCR2  ------------------------------ */\r
+#define HRPWM0_HRC0_SCR2_SCR2_Pos             0                                                       /*!< HRPWM0_HRC0 SCR2: SCR2 Position         */\r
+#define HRPWM0_HRC0_SCR2_SCR2_Msk             (0x000000ffUL << HRPWM0_HRC0_SCR2_SCR2_Pos)             /*!< HRPWM0_HRC0 SCR2: SCR2 Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_HRC1' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_HRC1_GC  ------------------------------- */\r
+#define HRPWM0_HRC1_GC_HRM0_Pos               0                                                       /*!< HRPWM0_HRC1 GC: HRM0 Position           */\r
+#define HRPWM0_HRC1_GC_HRM0_Msk               (0x03UL << HRPWM0_HRC1_GC_HRM0_Pos)                     /*!< HRPWM0_HRC1 GC: HRM0 Mask               */\r
+#define HRPWM0_HRC1_GC_HRM1_Pos               2                                                       /*!< HRPWM0_HRC1 GC: HRM1 Position           */\r
+#define HRPWM0_HRC1_GC_HRM1_Msk               (0x03UL << HRPWM0_HRC1_GC_HRM1_Pos)                     /*!< HRPWM0_HRC1 GC: HRM1 Mask               */\r
+#define HRPWM0_HRC1_GC_DTE_Pos                8                                                       /*!< HRPWM0_HRC1 GC: DTE Position            */\r
+#define HRPWM0_HRC1_GC_DTE_Msk                (0x01UL << HRPWM0_HRC1_GC_DTE_Pos)                      /*!< HRPWM0_HRC1 GC: DTE Mask                */\r
+#define HRPWM0_HRC1_GC_TR0E_Pos               9                                                       /*!< HRPWM0_HRC1 GC: TR0E Position           */\r
+#define HRPWM0_HRC1_GC_TR0E_Msk               (0x01UL << HRPWM0_HRC1_GC_TR0E_Pos)                     /*!< HRPWM0_HRC1 GC: TR0E Mask               */\r
+#define HRPWM0_HRC1_GC_TR1E_Pos               10                                                      /*!< HRPWM0_HRC1 GC: TR1E Position           */\r
+#define HRPWM0_HRC1_GC_TR1E_Msk               (0x01UL << HRPWM0_HRC1_GC_TR1E_Pos)                     /*!< HRPWM0_HRC1 GC: TR1E Mask               */\r
+#define HRPWM0_HRC1_GC_STC_Pos                11                                                      /*!< HRPWM0_HRC1 GC: STC Position            */\r
+#define HRPWM0_HRC1_GC_STC_Msk                (0x01UL << HRPWM0_HRC1_GC_STC_Pos)                      /*!< HRPWM0_HRC1 GC: STC Mask                */\r
+#define HRPWM0_HRC1_GC_DSTC_Pos               12                                                      /*!< HRPWM0_HRC1 GC: DSTC Position           */\r
+#define HRPWM0_HRC1_GC_DSTC_Msk               (0x01UL << HRPWM0_HRC1_GC_DSTC_Pos)                     /*!< HRPWM0_HRC1 GC: DSTC Mask               */\r
+#define HRPWM0_HRC1_GC_OCS0_Pos               13                                                      /*!< HRPWM0_HRC1 GC: OCS0 Position           */\r
+#define HRPWM0_HRC1_GC_OCS0_Msk               (0x01UL << HRPWM0_HRC1_GC_OCS0_Pos)                     /*!< HRPWM0_HRC1 GC: OCS0 Mask               */\r
+#define HRPWM0_HRC1_GC_OCS1_Pos               14                                                      /*!< HRPWM0_HRC1 GC: OCS1 Position           */\r
+#define HRPWM0_HRC1_GC_OCS1_Msk               (0x01UL << HRPWM0_HRC1_GC_OCS1_Pos)                     /*!< HRPWM0_HRC1 GC: OCS1 Mask               */\r
+#define HRPWM0_HRC1_GC_DTUS_Pos               16                                                      /*!< HRPWM0_HRC1 GC: DTUS Position           */\r
+#define HRPWM0_HRC1_GC_DTUS_Msk               (0x01UL << HRPWM0_HRC1_GC_DTUS_Pos)                     /*!< HRPWM0_HRC1 GC: DTUS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_PL  ------------------------------- */\r
+#define HRPWM0_HRC1_PL_PSL0_Pos               0                                                       /*!< HRPWM0_HRC1 PL: PSL0 Position           */\r
+#define HRPWM0_HRC1_PL_PSL0_Msk               (0x01UL << HRPWM0_HRC1_PL_PSL0_Pos)                     /*!< HRPWM0_HRC1 PL: PSL0 Mask               */\r
+#define HRPWM0_HRC1_PL_PSL1_Pos               1                                                       /*!< HRPWM0_HRC1 PL: PSL1 Position           */\r
+#define HRPWM0_HRC1_PL_PSL1_Msk               (0x01UL << HRPWM0_HRC1_PL_PSL1_Pos)                     /*!< HRPWM0_HRC1 PL: PSL1 Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_GSEL  ------------------------------ */\r
+#define HRPWM0_HRC1_GSEL_C0SS_Pos             0                                                       /*!< HRPWM0_HRC1 GSEL: C0SS Position         */\r
+#define HRPWM0_HRC1_GSEL_C0SS_Msk             (0x07UL << HRPWM0_HRC1_GSEL_C0SS_Pos)                   /*!< HRPWM0_HRC1 GSEL: C0SS Mask             */\r
+#define HRPWM0_HRC1_GSEL_C0CS_Pos             3                                                       /*!< HRPWM0_HRC1 GSEL: C0CS Position         */\r
+#define HRPWM0_HRC1_GSEL_C0CS_Msk             (0x07UL << HRPWM0_HRC1_GSEL_C0CS_Pos)                   /*!< HRPWM0_HRC1 GSEL: C0CS Mask             */\r
+#define HRPWM0_HRC1_GSEL_S0M_Pos              6                                                       /*!< HRPWM0_HRC1 GSEL: S0M Position          */\r
+#define HRPWM0_HRC1_GSEL_S0M_Msk              (0x03UL << HRPWM0_HRC1_GSEL_S0M_Pos)                    /*!< HRPWM0_HRC1 GSEL: S0M Mask              */\r
+#define HRPWM0_HRC1_GSEL_C0M_Pos              8                                                       /*!< HRPWM0_HRC1 GSEL: C0M Position          */\r
+#define HRPWM0_HRC1_GSEL_C0M_Msk              (0x03UL << HRPWM0_HRC1_GSEL_C0M_Pos)                    /*!< HRPWM0_HRC1 GSEL: C0M Mask              */\r
+#define HRPWM0_HRC1_GSEL_S0ES_Pos             10                                                      /*!< HRPWM0_HRC1 GSEL: S0ES Position         */\r
+#define HRPWM0_HRC1_GSEL_S0ES_Msk             (0x03UL << HRPWM0_HRC1_GSEL_S0ES_Pos)                   /*!< HRPWM0_HRC1 GSEL: S0ES Mask             */\r
+#define HRPWM0_HRC1_GSEL_C0ES_Pos             12                                                      /*!< HRPWM0_HRC1 GSEL: C0ES Position         */\r
+#define HRPWM0_HRC1_GSEL_C0ES_Msk             (0x03UL << HRPWM0_HRC1_GSEL_C0ES_Pos)                   /*!< HRPWM0_HRC1 GSEL: C0ES Mask             */\r
+#define HRPWM0_HRC1_GSEL_C1SS_Pos             16                                                      /*!< HRPWM0_HRC1 GSEL: C1SS Position         */\r
+#define HRPWM0_HRC1_GSEL_C1SS_Msk             (0x07UL << HRPWM0_HRC1_GSEL_C1SS_Pos)                   /*!< HRPWM0_HRC1 GSEL: C1SS Mask             */\r
+#define HRPWM0_HRC1_GSEL_C1CS_Pos             19                                                      /*!< HRPWM0_HRC1 GSEL: C1CS Position         */\r
+#define HRPWM0_HRC1_GSEL_C1CS_Msk             (0x07UL << HRPWM0_HRC1_GSEL_C1CS_Pos)                   /*!< HRPWM0_HRC1 GSEL: C1CS Mask             */\r
+#define HRPWM0_HRC1_GSEL_S1M_Pos              22                                                      /*!< HRPWM0_HRC1 GSEL: S1M Position          */\r
+#define HRPWM0_HRC1_GSEL_S1M_Msk              (0x03UL << HRPWM0_HRC1_GSEL_S1M_Pos)                    /*!< HRPWM0_HRC1 GSEL: S1M Mask              */\r
+#define HRPWM0_HRC1_GSEL_C1M_Pos              24                                                      /*!< HRPWM0_HRC1 GSEL: C1M Position          */\r
+#define HRPWM0_HRC1_GSEL_C1M_Msk              (0x03UL << HRPWM0_HRC1_GSEL_C1M_Pos)                    /*!< HRPWM0_HRC1 GSEL: C1M Mask              */\r
+#define HRPWM0_HRC1_GSEL_S1ES_Pos             26                                                      /*!< HRPWM0_HRC1 GSEL: S1ES Position         */\r
+#define HRPWM0_HRC1_GSEL_S1ES_Msk             (0x03UL << HRPWM0_HRC1_GSEL_S1ES_Pos)                   /*!< HRPWM0_HRC1 GSEL: S1ES Mask             */\r
+#define HRPWM0_HRC1_GSEL_C1ES_Pos             28                                                      /*!< HRPWM0_HRC1 GSEL: C1ES Position         */\r
+#define HRPWM0_HRC1_GSEL_C1ES_Msk             (0x03UL << HRPWM0_HRC1_GSEL_C1ES_Pos)                   /*!< HRPWM0_HRC1 GSEL: C1ES Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_TSEL  ------------------------------ */\r
+#define HRPWM0_HRC1_TSEL_TSEL0_Pos            0                                                       /*!< HRPWM0_HRC1 TSEL: TSEL0 Position        */\r
+#define HRPWM0_HRC1_TSEL_TSEL0_Msk            (0x07UL << HRPWM0_HRC1_TSEL_TSEL0_Pos)                  /*!< HRPWM0_HRC1 TSEL: TSEL0 Mask            */\r
+#define HRPWM0_HRC1_TSEL_TSEL1_Pos            3                                                       /*!< HRPWM0_HRC1 TSEL: TSEL1 Position        */\r
+#define HRPWM0_HRC1_TSEL_TSEL1_Msk            (0x07UL << HRPWM0_HRC1_TSEL_TSEL1_Pos)                  /*!< HRPWM0_HRC1 TSEL: TSEL1 Mask            */\r
+#define HRPWM0_HRC1_TSEL_TS0E_Pos             16                                                      /*!< HRPWM0_HRC1 TSEL: TS0E Position         */\r
+#define HRPWM0_HRC1_TSEL_TS0E_Msk             (0x01UL << HRPWM0_HRC1_TSEL_TS0E_Pos)                   /*!< HRPWM0_HRC1 TSEL: TS0E Mask             */\r
+#define HRPWM0_HRC1_TSEL_TS1E_Pos             17                                                      /*!< HRPWM0_HRC1 TSEL: TS1E Position         */\r
+#define HRPWM0_HRC1_TSEL_TS1E_Msk             (0x01UL << HRPWM0_HRC1_TSEL_TS1E_Pos)                   /*!< HRPWM0_HRC1 TSEL: TS1E Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_SC  ------------------------------- */\r
+#define HRPWM0_HRC1_SC_ST_Pos                 0                                                       /*!< HRPWM0_HRC1 SC: ST Position             */\r
+#define HRPWM0_HRC1_SC_ST_Msk                 (0x01UL << HRPWM0_HRC1_SC_ST_Pos)                       /*!< HRPWM0_HRC1 SC: ST Mask                 */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_DCR  ------------------------------ */\r
+#define HRPWM0_HRC1_DCR_DTRV_Pos              0                                                       /*!< HRPWM0_HRC1 DCR: DTRV Position          */\r
+#define HRPWM0_HRC1_DCR_DTRV_Msk              (0x0000ffffUL << HRPWM0_HRC1_DCR_DTRV_Pos)              /*!< HRPWM0_HRC1 DCR: DTRV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_DCF  ------------------------------ */\r
+#define HRPWM0_HRC1_DCF_DTFV_Pos              0                                                       /*!< HRPWM0_HRC1 DCF: DTFV Position          */\r
+#define HRPWM0_HRC1_DCF_DTFV_Msk              (0x0000ffffUL << HRPWM0_HRC1_DCF_DTFV_Pos)              /*!< HRPWM0_HRC1 DCF: DTFV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_CR1  ------------------------------ */\r
+#define HRPWM0_HRC1_CR1_CR1_Pos               0                                                       /*!< HRPWM0_HRC1 CR1: CR1 Position           */\r
+#define HRPWM0_HRC1_CR1_CR1_Msk               (0x000000ffUL << HRPWM0_HRC1_CR1_CR1_Pos)               /*!< HRPWM0_HRC1 CR1: CR1 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_CR2  ------------------------------ */\r
+#define HRPWM0_HRC1_CR2_CR2_Pos               0                                                       /*!< HRPWM0_HRC1 CR2: CR2 Position           */\r
+#define HRPWM0_HRC1_CR2_CR2_Msk               (0x000000ffUL << HRPWM0_HRC1_CR2_CR2_Pos)               /*!< HRPWM0_HRC1 CR2: CR2 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_SSC  ------------------------------ */\r
+#define HRPWM0_HRC1_SSC_SST_Pos               0                                                       /*!< HRPWM0_HRC1 SSC: SST Position           */\r
+#define HRPWM0_HRC1_SSC_SST_Msk               (0x01UL << HRPWM0_HRC1_SSC_SST_Pos)                     /*!< HRPWM0_HRC1 SSC: SST Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_SDCR  ------------------------------ */\r
+#define HRPWM0_HRC1_SDCR_SDTRV_Pos            0                                                       /*!< HRPWM0_HRC1 SDCR: SDTRV Position        */\r
+#define HRPWM0_HRC1_SDCR_SDTRV_Msk            (0x0000ffffUL << HRPWM0_HRC1_SDCR_SDTRV_Pos)            /*!< HRPWM0_HRC1 SDCR: SDTRV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_SDCF  ------------------------------ */\r
+#define HRPWM0_HRC1_SDCF_SDTFV_Pos            0                                                       /*!< HRPWM0_HRC1 SDCF: SDTFV Position        */\r
+#define HRPWM0_HRC1_SDCF_SDTFV_Msk            (0x0000ffffUL << HRPWM0_HRC1_SDCF_SDTFV_Pos)            /*!< HRPWM0_HRC1 SDCF: SDTFV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_SCR1  ------------------------------ */\r
+#define HRPWM0_HRC1_SCR1_SCR1_Pos             0                                                       /*!< HRPWM0_HRC1 SCR1: SCR1 Position         */\r
+#define HRPWM0_HRC1_SCR1_SCR1_Msk             (0x000000ffUL << HRPWM0_HRC1_SCR1_SCR1_Pos)             /*!< HRPWM0_HRC1 SCR1: SCR1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_SCR2  ------------------------------ */\r
+#define HRPWM0_HRC1_SCR2_SCR2_Pos             0                                                       /*!< HRPWM0_HRC1 SCR2: SCR2 Position         */\r
+#define HRPWM0_HRC1_SCR2_SCR2_Msk             (0x000000ffUL << HRPWM0_HRC1_SCR2_SCR2_Pos)             /*!< HRPWM0_HRC1 SCR2: SCR2 Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_HRC2' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_HRC2_GC  ------------------------------- */\r
+#define HRPWM0_HRC2_GC_HRM0_Pos               0                                                       /*!< HRPWM0_HRC2 GC: HRM0 Position           */\r
+#define HRPWM0_HRC2_GC_HRM0_Msk               (0x03UL << HRPWM0_HRC2_GC_HRM0_Pos)                     /*!< HRPWM0_HRC2 GC: HRM0 Mask               */\r
+#define HRPWM0_HRC2_GC_HRM1_Pos               2                                                       /*!< HRPWM0_HRC2 GC: HRM1 Position           */\r
+#define HRPWM0_HRC2_GC_HRM1_Msk               (0x03UL << HRPWM0_HRC2_GC_HRM1_Pos)                     /*!< HRPWM0_HRC2 GC: HRM1 Mask               */\r
+#define HRPWM0_HRC2_GC_DTE_Pos                8                                                       /*!< HRPWM0_HRC2 GC: DTE Position            */\r
+#define HRPWM0_HRC2_GC_DTE_Msk                (0x01UL << HRPWM0_HRC2_GC_DTE_Pos)                      /*!< HRPWM0_HRC2 GC: DTE Mask                */\r
+#define HRPWM0_HRC2_GC_TR0E_Pos               9                                                       /*!< HRPWM0_HRC2 GC: TR0E Position           */\r
+#define HRPWM0_HRC2_GC_TR0E_Msk               (0x01UL << HRPWM0_HRC2_GC_TR0E_Pos)                     /*!< HRPWM0_HRC2 GC: TR0E Mask               */\r
+#define HRPWM0_HRC2_GC_TR1E_Pos               10                                                      /*!< HRPWM0_HRC2 GC: TR1E Position           */\r
+#define HRPWM0_HRC2_GC_TR1E_Msk               (0x01UL << HRPWM0_HRC2_GC_TR1E_Pos)                     /*!< HRPWM0_HRC2 GC: TR1E Mask               */\r
+#define HRPWM0_HRC2_GC_STC_Pos                11                                                      /*!< HRPWM0_HRC2 GC: STC Position            */\r
+#define HRPWM0_HRC2_GC_STC_Msk                (0x01UL << HRPWM0_HRC2_GC_STC_Pos)                      /*!< HRPWM0_HRC2 GC: STC Mask                */\r
+#define HRPWM0_HRC2_GC_DSTC_Pos               12                                                      /*!< HRPWM0_HRC2 GC: DSTC Position           */\r
+#define HRPWM0_HRC2_GC_DSTC_Msk               (0x01UL << HRPWM0_HRC2_GC_DSTC_Pos)                     /*!< HRPWM0_HRC2 GC: DSTC Mask               */\r
+#define HRPWM0_HRC2_GC_OCS0_Pos               13                                                      /*!< HRPWM0_HRC2 GC: OCS0 Position           */\r
+#define HRPWM0_HRC2_GC_OCS0_Msk               (0x01UL << HRPWM0_HRC2_GC_OCS0_Pos)                     /*!< HRPWM0_HRC2 GC: OCS0 Mask               */\r
+#define HRPWM0_HRC2_GC_OCS1_Pos               14                                                      /*!< HRPWM0_HRC2 GC: OCS1 Position           */\r
+#define HRPWM0_HRC2_GC_OCS1_Msk               (0x01UL << HRPWM0_HRC2_GC_OCS1_Pos)                     /*!< HRPWM0_HRC2 GC: OCS1 Mask               */\r
+#define HRPWM0_HRC2_GC_DTUS_Pos               16                                                      /*!< HRPWM0_HRC2 GC: DTUS Position           */\r
+#define HRPWM0_HRC2_GC_DTUS_Msk               (0x01UL << HRPWM0_HRC2_GC_DTUS_Pos)                     /*!< HRPWM0_HRC2 GC: DTUS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_PL  ------------------------------- */\r
+#define HRPWM0_HRC2_PL_PSL0_Pos               0                                                       /*!< HRPWM0_HRC2 PL: PSL0 Position           */\r
+#define HRPWM0_HRC2_PL_PSL0_Msk               (0x01UL << HRPWM0_HRC2_PL_PSL0_Pos)                     /*!< HRPWM0_HRC2 PL: PSL0 Mask               */\r
+#define HRPWM0_HRC2_PL_PSL1_Pos               1                                                       /*!< HRPWM0_HRC2 PL: PSL1 Position           */\r
+#define HRPWM0_HRC2_PL_PSL1_Msk               (0x01UL << HRPWM0_HRC2_PL_PSL1_Pos)                     /*!< HRPWM0_HRC2 PL: PSL1 Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_GSEL  ------------------------------ */\r
+#define HRPWM0_HRC2_GSEL_C0SS_Pos             0                                                       /*!< HRPWM0_HRC2 GSEL: C0SS Position         */\r
+#define HRPWM0_HRC2_GSEL_C0SS_Msk             (0x07UL << HRPWM0_HRC2_GSEL_C0SS_Pos)                   /*!< HRPWM0_HRC2 GSEL: C0SS Mask             */\r
+#define HRPWM0_HRC2_GSEL_C0CS_Pos             3                                                       /*!< HRPWM0_HRC2 GSEL: C0CS Position         */\r
+#define HRPWM0_HRC2_GSEL_C0CS_Msk             (0x07UL << HRPWM0_HRC2_GSEL_C0CS_Pos)                   /*!< HRPWM0_HRC2 GSEL: C0CS Mask             */\r
+#define HRPWM0_HRC2_GSEL_S0M_Pos              6                                                       /*!< HRPWM0_HRC2 GSEL: S0M Position          */\r
+#define HRPWM0_HRC2_GSEL_S0M_Msk              (0x03UL << HRPWM0_HRC2_GSEL_S0M_Pos)                    /*!< HRPWM0_HRC2 GSEL: S0M Mask              */\r
+#define HRPWM0_HRC2_GSEL_C0M_Pos              8                                                       /*!< HRPWM0_HRC2 GSEL: C0M Position          */\r
+#define HRPWM0_HRC2_GSEL_C0M_Msk              (0x03UL << HRPWM0_HRC2_GSEL_C0M_Pos)                    /*!< HRPWM0_HRC2 GSEL: C0M Mask              */\r
+#define HRPWM0_HRC2_GSEL_S0ES_Pos             10                                                      /*!< HRPWM0_HRC2 GSEL: S0ES Position         */\r
+#define HRPWM0_HRC2_GSEL_S0ES_Msk             (0x03UL << HRPWM0_HRC2_GSEL_S0ES_Pos)                   /*!< HRPWM0_HRC2 GSEL: S0ES Mask             */\r
+#define HRPWM0_HRC2_GSEL_C0ES_Pos             12                                                      /*!< HRPWM0_HRC2 GSEL: C0ES Position         */\r
+#define HRPWM0_HRC2_GSEL_C0ES_Msk             (0x03UL << HRPWM0_HRC2_GSEL_C0ES_Pos)                   /*!< HRPWM0_HRC2 GSEL: C0ES Mask             */\r
+#define HRPWM0_HRC2_GSEL_C1SS_Pos             16                                                      /*!< HRPWM0_HRC2 GSEL: C1SS Position         */\r
+#define HRPWM0_HRC2_GSEL_C1SS_Msk             (0x07UL << HRPWM0_HRC2_GSEL_C1SS_Pos)                   /*!< HRPWM0_HRC2 GSEL: C1SS Mask             */\r
+#define HRPWM0_HRC2_GSEL_C1CS_Pos             19                                                      /*!< HRPWM0_HRC2 GSEL: C1CS Position         */\r
+#define HRPWM0_HRC2_GSEL_C1CS_Msk             (0x07UL << HRPWM0_HRC2_GSEL_C1CS_Pos)                   /*!< HRPWM0_HRC2 GSEL: C1CS Mask             */\r
+#define HRPWM0_HRC2_GSEL_S1M_Pos              22                                                      /*!< HRPWM0_HRC2 GSEL: S1M Position          */\r
+#define HRPWM0_HRC2_GSEL_S1M_Msk              (0x03UL << HRPWM0_HRC2_GSEL_S1M_Pos)                    /*!< HRPWM0_HRC2 GSEL: S1M Mask              */\r
+#define HRPWM0_HRC2_GSEL_C1M_Pos              24                                                      /*!< HRPWM0_HRC2 GSEL: C1M Position          */\r
+#define HRPWM0_HRC2_GSEL_C1M_Msk              (0x03UL << HRPWM0_HRC2_GSEL_C1M_Pos)                    /*!< HRPWM0_HRC2 GSEL: C1M Mask              */\r
+#define HRPWM0_HRC2_GSEL_S1ES_Pos             26                                                      /*!< HRPWM0_HRC2 GSEL: S1ES Position         */\r
+#define HRPWM0_HRC2_GSEL_S1ES_Msk             (0x03UL << HRPWM0_HRC2_GSEL_S1ES_Pos)                   /*!< HRPWM0_HRC2 GSEL: S1ES Mask             */\r
+#define HRPWM0_HRC2_GSEL_C1ES_Pos             28                                                      /*!< HRPWM0_HRC2 GSEL: C1ES Position         */\r
+#define HRPWM0_HRC2_GSEL_C1ES_Msk             (0x03UL << HRPWM0_HRC2_GSEL_C1ES_Pos)                   /*!< HRPWM0_HRC2 GSEL: C1ES Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_TSEL  ------------------------------ */\r
+#define HRPWM0_HRC2_TSEL_TSEL0_Pos            0                                                       /*!< HRPWM0_HRC2 TSEL: TSEL0 Position        */\r
+#define HRPWM0_HRC2_TSEL_TSEL0_Msk            (0x07UL << HRPWM0_HRC2_TSEL_TSEL0_Pos)                  /*!< HRPWM0_HRC2 TSEL: TSEL0 Mask            */\r
+#define HRPWM0_HRC2_TSEL_TSEL1_Pos            3                                                       /*!< HRPWM0_HRC2 TSEL: TSEL1 Position        */\r
+#define HRPWM0_HRC2_TSEL_TSEL1_Msk            (0x07UL << HRPWM0_HRC2_TSEL_TSEL1_Pos)                  /*!< HRPWM0_HRC2 TSEL: TSEL1 Mask            */\r
+#define HRPWM0_HRC2_TSEL_TS0E_Pos             16                                                      /*!< HRPWM0_HRC2 TSEL: TS0E Position         */\r
+#define HRPWM0_HRC2_TSEL_TS0E_Msk             (0x01UL << HRPWM0_HRC2_TSEL_TS0E_Pos)                   /*!< HRPWM0_HRC2 TSEL: TS0E Mask             */\r
+#define HRPWM0_HRC2_TSEL_TS1E_Pos             17                                                      /*!< HRPWM0_HRC2 TSEL: TS1E Position         */\r
+#define HRPWM0_HRC2_TSEL_TS1E_Msk             (0x01UL << HRPWM0_HRC2_TSEL_TS1E_Pos)                   /*!< HRPWM0_HRC2 TSEL: TS1E Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_SC  ------------------------------- */\r
+#define HRPWM0_HRC2_SC_ST_Pos                 0                                                       /*!< HRPWM0_HRC2 SC: ST Position             */\r
+#define HRPWM0_HRC2_SC_ST_Msk                 (0x01UL << HRPWM0_HRC2_SC_ST_Pos)                       /*!< HRPWM0_HRC2 SC: ST Mask                 */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_DCR  ------------------------------ */\r
+#define HRPWM0_HRC2_DCR_DTRV_Pos              0                                                       /*!< HRPWM0_HRC2 DCR: DTRV Position          */\r
+#define HRPWM0_HRC2_DCR_DTRV_Msk              (0x0000ffffUL << HRPWM0_HRC2_DCR_DTRV_Pos)              /*!< HRPWM0_HRC2 DCR: DTRV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_DCF  ------------------------------ */\r
+#define HRPWM0_HRC2_DCF_DTFV_Pos              0                                                       /*!< HRPWM0_HRC2 DCF: DTFV Position          */\r
+#define HRPWM0_HRC2_DCF_DTFV_Msk              (0x0000ffffUL << HRPWM0_HRC2_DCF_DTFV_Pos)              /*!< HRPWM0_HRC2 DCF: DTFV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_CR1  ------------------------------ */\r
+#define HRPWM0_HRC2_CR1_CR1_Pos               0                                                       /*!< HRPWM0_HRC2 CR1: CR1 Position           */\r
+#define HRPWM0_HRC2_CR1_CR1_Msk               (0x000000ffUL << HRPWM0_HRC2_CR1_CR1_Pos)               /*!< HRPWM0_HRC2 CR1: CR1 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_CR2  ------------------------------ */\r
+#define HRPWM0_HRC2_CR2_CR2_Pos               0                                                       /*!< HRPWM0_HRC2 CR2: CR2 Position           */\r
+#define HRPWM0_HRC2_CR2_CR2_Msk               (0x000000ffUL << HRPWM0_HRC2_CR2_CR2_Pos)               /*!< HRPWM0_HRC2 CR2: CR2 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_SSC  ------------------------------ */\r
+#define HRPWM0_HRC2_SSC_SST_Pos               0                                                       /*!< HRPWM0_HRC2 SSC: SST Position           */\r
+#define HRPWM0_HRC2_SSC_SST_Msk               (0x01UL << HRPWM0_HRC2_SSC_SST_Pos)                     /*!< HRPWM0_HRC2 SSC: SST Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_SDCR  ------------------------------ */\r
+#define HRPWM0_HRC2_SDCR_SDTRV_Pos            0                                                       /*!< HRPWM0_HRC2 SDCR: SDTRV Position        */\r
+#define HRPWM0_HRC2_SDCR_SDTRV_Msk            (0x0000ffffUL << HRPWM0_HRC2_SDCR_SDTRV_Pos)            /*!< HRPWM0_HRC2 SDCR: SDTRV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_SDCF  ------------------------------ */\r
+#define HRPWM0_HRC2_SDCF_SDTFV_Pos            0                                                       /*!< HRPWM0_HRC2 SDCF: SDTFV Position        */\r
+#define HRPWM0_HRC2_SDCF_SDTFV_Msk            (0x0000ffffUL << HRPWM0_HRC2_SDCF_SDTFV_Pos)            /*!< HRPWM0_HRC2 SDCF: SDTFV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_SCR1  ------------------------------ */\r
+#define HRPWM0_HRC2_SCR1_SCR1_Pos             0                                                       /*!< HRPWM0_HRC2 SCR1: SCR1 Position         */\r
+#define HRPWM0_HRC2_SCR1_SCR1_Msk             (0x000000ffUL << HRPWM0_HRC2_SCR1_SCR1_Pos)             /*!< HRPWM0_HRC2 SCR1: SCR1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_SCR2  ------------------------------ */\r
+#define HRPWM0_HRC2_SCR2_SCR2_Pos             0                                                       /*!< HRPWM0_HRC2 SCR2: SCR2 Position         */\r
+#define HRPWM0_HRC2_SCR2_SCR2_Msk             (0x000000ffUL << HRPWM0_HRC2_SCR2_SCR2_Pos)             /*!< HRPWM0_HRC2 SCR2: SCR2 Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_HRC3' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_HRC3_GC  ------------------------------- */\r
+#define HRPWM0_HRC3_GC_HRM0_Pos               0                                                       /*!< HRPWM0_HRC3 GC: HRM0 Position           */\r
+#define HRPWM0_HRC3_GC_HRM0_Msk               (0x03UL << HRPWM0_HRC3_GC_HRM0_Pos)                     /*!< HRPWM0_HRC3 GC: HRM0 Mask               */\r
+#define HRPWM0_HRC3_GC_HRM1_Pos               2                                                       /*!< HRPWM0_HRC3 GC: HRM1 Position           */\r
+#define HRPWM0_HRC3_GC_HRM1_Msk               (0x03UL << HRPWM0_HRC3_GC_HRM1_Pos)                     /*!< HRPWM0_HRC3 GC: HRM1 Mask               */\r
+#define HRPWM0_HRC3_GC_DTE_Pos                8                                                       /*!< HRPWM0_HRC3 GC: DTE Position            */\r
+#define HRPWM0_HRC3_GC_DTE_Msk                (0x01UL << HRPWM0_HRC3_GC_DTE_Pos)                      /*!< HRPWM0_HRC3 GC: DTE Mask                */\r
+#define HRPWM0_HRC3_GC_TR0E_Pos               9                                                       /*!< HRPWM0_HRC3 GC: TR0E Position           */\r
+#define HRPWM0_HRC3_GC_TR0E_Msk               (0x01UL << HRPWM0_HRC3_GC_TR0E_Pos)                     /*!< HRPWM0_HRC3 GC: TR0E Mask               */\r
+#define HRPWM0_HRC3_GC_TR1E_Pos               10                                                      /*!< HRPWM0_HRC3 GC: TR1E Position           */\r
+#define HRPWM0_HRC3_GC_TR1E_Msk               (0x01UL << HRPWM0_HRC3_GC_TR1E_Pos)                     /*!< HRPWM0_HRC3 GC: TR1E Mask               */\r
+#define HRPWM0_HRC3_GC_STC_Pos                11                                                      /*!< HRPWM0_HRC3 GC: STC Position            */\r
+#define HRPWM0_HRC3_GC_STC_Msk                (0x01UL << HRPWM0_HRC3_GC_STC_Pos)                      /*!< HRPWM0_HRC3 GC: STC Mask                */\r
+#define HRPWM0_HRC3_GC_DSTC_Pos               12                                                      /*!< HRPWM0_HRC3 GC: DSTC Position           */\r
+#define HRPWM0_HRC3_GC_DSTC_Msk               (0x01UL << HRPWM0_HRC3_GC_DSTC_Pos)                     /*!< HRPWM0_HRC3 GC: DSTC Mask               */\r
+#define HRPWM0_HRC3_GC_OCS0_Pos               13                                                      /*!< HRPWM0_HRC3 GC: OCS0 Position           */\r
+#define HRPWM0_HRC3_GC_OCS0_Msk               (0x01UL << HRPWM0_HRC3_GC_OCS0_Pos)                     /*!< HRPWM0_HRC3 GC: OCS0 Mask               */\r
+#define HRPWM0_HRC3_GC_OCS1_Pos               14                                                      /*!< HRPWM0_HRC3 GC: OCS1 Position           */\r
+#define HRPWM0_HRC3_GC_OCS1_Msk               (0x01UL << HRPWM0_HRC3_GC_OCS1_Pos)                     /*!< HRPWM0_HRC3 GC: OCS1 Mask               */\r
+#define HRPWM0_HRC3_GC_DTUS_Pos               16                                                      /*!< HRPWM0_HRC3 GC: DTUS Position           */\r
+#define HRPWM0_HRC3_GC_DTUS_Msk               (0x01UL << HRPWM0_HRC3_GC_DTUS_Pos)                     /*!< HRPWM0_HRC3 GC: DTUS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_PL  ------------------------------- */\r
+#define HRPWM0_HRC3_PL_PSL0_Pos               0                                                       /*!< HRPWM0_HRC3 PL: PSL0 Position           */\r
+#define HRPWM0_HRC3_PL_PSL0_Msk               (0x01UL << HRPWM0_HRC3_PL_PSL0_Pos)                     /*!< HRPWM0_HRC3 PL: PSL0 Mask               */\r
+#define HRPWM0_HRC3_PL_PSL1_Pos               1                                                       /*!< HRPWM0_HRC3 PL: PSL1 Position           */\r
+#define HRPWM0_HRC3_PL_PSL1_Msk               (0x01UL << HRPWM0_HRC3_PL_PSL1_Pos)                     /*!< HRPWM0_HRC3 PL: PSL1 Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_GSEL  ------------------------------ */\r
+#define HRPWM0_HRC3_GSEL_C0SS_Pos             0                                                       /*!< HRPWM0_HRC3 GSEL: C0SS Position         */\r
+#define HRPWM0_HRC3_GSEL_C0SS_Msk             (0x07UL << HRPWM0_HRC3_GSEL_C0SS_Pos)                   /*!< HRPWM0_HRC3 GSEL: C0SS Mask             */\r
+#define HRPWM0_HRC3_GSEL_C0CS_Pos             3                                                       /*!< HRPWM0_HRC3 GSEL: C0CS Position         */\r
+#define HRPWM0_HRC3_GSEL_C0CS_Msk             (0x07UL << HRPWM0_HRC3_GSEL_C0CS_Pos)                   /*!< HRPWM0_HRC3 GSEL: C0CS Mask             */\r
+#define HRPWM0_HRC3_GSEL_S0M_Pos              6                                                       /*!< HRPWM0_HRC3 GSEL: S0M Position          */\r
+#define HRPWM0_HRC3_GSEL_S0M_Msk              (0x03UL << HRPWM0_HRC3_GSEL_S0M_Pos)                    /*!< HRPWM0_HRC3 GSEL: S0M Mask              */\r
+#define HRPWM0_HRC3_GSEL_C0M_Pos              8                                                       /*!< HRPWM0_HRC3 GSEL: C0M Position          */\r
+#define HRPWM0_HRC3_GSEL_C0M_Msk              (0x03UL << HRPWM0_HRC3_GSEL_C0M_Pos)                    /*!< HRPWM0_HRC3 GSEL: C0M Mask              */\r
+#define HRPWM0_HRC3_GSEL_S0ES_Pos             10                                                      /*!< HRPWM0_HRC3 GSEL: S0ES Position         */\r
+#define HRPWM0_HRC3_GSEL_S0ES_Msk             (0x03UL << HRPWM0_HRC3_GSEL_S0ES_Pos)                   /*!< HRPWM0_HRC3 GSEL: S0ES Mask             */\r
+#define HRPWM0_HRC3_GSEL_C0ES_Pos             12                                                      /*!< HRPWM0_HRC3 GSEL: C0ES Position         */\r
+#define HRPWM0_HRC3_GSEL_C0ES_Msk             (0x03UL << HRPWM0_HRC3_GSEL_C0ES_Pos)                   /*!< HRPWM0_HRC3 GSEL: C0ES Mask             */\r
+#define HRPWM0_HRC3_GSEL_C1SS_Pos             16                                                      /*!< HRPWM0_HRC3 GSEL: C1SS Position         */\r
+#define HRPWM0_HRC3_GSEL_C1SS_Msk             (0x07UL << HRPWM0_HRC3_GSEL_C1SS_Pos)                   /*!< HRPWM0_HRC3 GSEL: C1SS Mask             */\r
+#define HRPWM0_HRC3_GSEL_C1CS_Pos             19                                                      /*!< HRPWM0_HRC3 GSEL: C1CS Position         */\r
+#define HRPWM0_HRC3_GSEL_C1CS_Msk             (0x07UL << HRPWM0_HRC3_GSEL_C1CS_Pos)                   /*!< HRPWM0_HRC3 GSEL: C1CS Mask             */\r
+#define HRPWM0_HRC3_GSEL_S1M_Pos              22                                                      /*!< HRPWM0_HRC3 GSEL: S1M Position          */\r
+#define HRPWM0_HRC3_GSEL_S1M_Msk              (0x03UL << HRPWM0_HRC3_GSEL_S1M_Pos)                    /*!< HRPWM0_HRC3 GSEL: S1M Mask              */\r
+#define HRPWM0_HRC3_GSEL_C1M_Pos              24                                                      /*!< HRPWM0_HRC3 GSEL: C1M Position          */\r
+#define HRPWM0_HRC3_GSEL_C1M_Msk              (0x03UL << HRPWM0_HRC3_GSEL_C1M_Pos)                    /*!< HRPWM0_HRC3 GSEL: C1M Mask              */\r
+#define HRPWM0_HRC3_GSEL_S1ES_Pos             26                                                      /*!< HRPWM0_HRC3 GSEL: S1ES Position         */\r
+#define HRPWM0_HRC3_GSEL_S1ES_Msk             (0x03UL << HRPWM0_HRC3_GSEL_S1ES_Pos)                   /*!< HRPWM0_HRC3 GSEL: S1ES Mask             */\r
+#define HRPWM0_HRC3_GSEL_C1ES_Pos             28                                                      /*!< HRPWM0_HRC3 GSEL: C1ES Position         */\r
+#define HRPWM0_HRC3_GSEL_C1ES_Msk             (0x03UL << HRPWM0_HRC3_GSEL_C1ES_Pos)                   /*!< HRPWM0_HRC3 GSEL: C1ES Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_TSEL  ------------------------------ */\r
+#define HRPWM0_HRC3_TSEL_TSEL0_Pos            0                                                       /*!< HRPWM0_HRC3 TSEL: TSEL0 Position        */\r
+#define HRPWM0_HRC3_TSEL_TSEL0_Msk            (0x07UL << HRPWM0_HRC3_TSEL_TSEL0_Pos)                  /*!< HRPWM0_HRC3 TSEL: TSEL0 Mask            */\r
+#define HRPWM0_HRC3_TSEL_TSEL1_Pos            3                                                       /*!< HRPWM0_HRC3 TSEL: TSEL1 Position        */\r
+#define HRPWM0_HRC3_TSEL_TSEL1_Msk            (0x07UL << HRPWM0_HRC3_TSEL_TSEL1_Pos)                  /*!< HRPWM0_HRC3 TSEL: TSEL1 Mask            */\r
+#define HRPWM0_HRC3_TSEL_TS0E_Pos             16                                                      /*!< HRPWM0_HRC3 TSEL: TS0E Position         */\r
+#define HRPWM0_HRC3_TSEL_TS0E_Msk             (0x01UL << HRPWM0_HRC3_TSEL_TS0E_Pos)                   /*!< HRPWM0_HRC3 TSEL: TS0E Mask             */\r
+#define HRPWM0_HRC3_TSEL_TS1E_Pos             17                                                      /*!< HRPWM0_HRC3 TSEL: TS1E Position         */\r
+#define HRPWM0_HRC3_TSEL_TS1E_Msk             (0x01UL << HRPWM0_HRC3_TSEL_TS1E_Pos)                   /*!< HRPWM0_HRC3 TSEL: TS1E Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_SC  ------------------------------- */\r
+#define HRPWM0_HRC3_SC_ST_Pos                 0                                                       /*!< HRPWM0_HRC3 SC: ST Position             */\r
+#define HRPWM0_HRC3_SC_ST_Msk                 (0x01UL << HRPWM0_HRC3_SC_ST_Pos)                       /*!< HRPWM0_HRC3 SC: ST Mask                 */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_DCR  ------------------------------ */\r
+#define HRPWM0_HRC3_DCR_DTRV_Pos              0                                                       /*!< HRPWM0_HRC3 DCR: DTRV Position          */\r
+#define HRPWM0_HRC3_DCR_DTRV_Msk              (0x0000ffffUL << HRPWM0_HRC3_DCR_DTRV_Pos)              /*!< HRPWM0_HRC3 DCR: DTRV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_DCF  ------------------------------ */\r
+#define HRPWM0_HRC3_DCF_DTFV_Pos              0                                                       /*!< HRPWM0_HRC3 DCF: DTFV Position          */\r
+#define HRPWM0_HRC3_DCF_DTFV_Msk              (0x0000ffffUL << HRPWM0_HRC3_DCF_DTFV_Pos)              /*!< HRPWM0_HRC3 DCF: DTFV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_CR1  ------------------------------ */\r
+#define HRPWM0_HRC3_CR1_CR1_Pos               0                                                       /*!< HRPWM0_HRC3 CR1: CR1 Position           */\r
+#define HRPWM0_HRC3_CR1_CR1_Msk               (0x000000ffUL << HRPWM0_HRC3_CR1_CR1_Pos)               /*!< HRPWM0_HRC3 CR1: CR1 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_CR2  ------------------------------ */\r
+#define HRPWM0_HRC3_CR2_CR2_Pos               0                                                       /*!< HRPWM0_HRC3 CR2: CR2 Position           */\r
+#define HRPWM0_HRC3_CR2_CR2_Msk               (0x000000ffUL << HRPWM0_HRC3_CR2_CR2_Pos)               /*!< HRPWM0_HRC3 CR2: CR2 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_SSC  ------------------------------ */\r
+#define HRPWM0_HRC3_SSC_SST_Pos               0                                                       /*!< HRPWM0_HRC3 SSC: SST Position           */\r
+#define HRPWM0_HRC3_SSC_SST_Msk               (0x01UL << HRPWM0_HRC3_SSC_SST_Pos)                     /*!< HRPWM0_HRC3 SSC: SST Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_SDCR  ------------------------------ */\r
+#define HRPWM0_HRC3_SDCR_SDTRV_Pos            0                                                       /*!< HRPWM0_HRC3 SDCR: SDTRV Position        */\r
+#define HRPWM0_HRC3_SDCR_SDTRV_Msk            (0x0000ffffUL << HRPWM0_HRC3_SDCR_SDTRV_Pos)            /*!< HRPWM0_HRC3 SDCR: SDTRV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_SDCF  ------------------------------ */\r
+#define HRPWM0_HRC3_SDCF_SDTFV_Pos            0                                                       /*!< HRPWM0_HRC3 SDCF: SDTFV Position        */\r
+#define HRPWM0_HRC3_SDCF_SDTFV_Msk            (0x0000ffffUL << HRPWM0_HRC3_SDCF_SDTFV_Pos)            /*!< HRPWM0_HRC3 SDCF: SDTFV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_SCR1  ------------------------------ */\r
+#define HRPWM0_HRC3_SCR1_SCR1_Pos             0                                                       /*!< HRPWM0_HRC3 SCR1: SCR1 Position         */\r
+#define HRPWM0_HRC3_SCR1_SCR1_Msk             (0x000000ffUL << HRPWM0_HRC3_SCR1_SCR1_Pos)             /*!< HRPWM0_HRC3 SCR1: SCR1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_SCR2  ------------------------------ */\r
+#define HRPWM0_HRC3_SCR2_SCR2_Pos             0                                                       /*!< HRPWM0_HRC3 SCR2: SCR2 Position         */\r
+#define HRPWM0_HRC3_SCR2_SCR2_Msk             (0x000000ffUL << HRPWM0_HRC3_SCR2_SCR2_Pos)             /*!< HRPWM0_HRC3 SCR2: SCR2 Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'POSIF' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  POSIF_PCONF  -------------------------------- */\r
+#define POSIF_PCONF_FSEL_Pos                  0                                                       /*!< POSIF PCONF: FSEL Position              */\r
+#define POSIF_PCONF_FSEL_Msk                  (0x03UL << POSIF_PCONF_FSEL_Pos)                        /*!< POSIF PCONF: FSEL Mask                  */\r
+#define POSIF_PCONF_QDCM_Pos                  2                                                       /*!< POSIF PCONF: QDCM Position              */\r
+#define POSIF_PCONF_QDCM_Msk                  (0x01UL << POSIF_PCONF_QDCM_Pos)                        /*!< POSIF PCONF: QDCM Mask                  */\r
+#define POSIF_PCONF_HIDG_Pos                  4                                                       /*!< POSIF PCONF: HIDG Position              */\r
+#define POSIF_PCONF_HIDG_Msk                  (0x01UL << POSIF_PCONF_HIDG_Pos)                        /*!< POSIF PCONF: HIDG Mask                  */\r
+#define POSIF_PCONF_MCUE_Pos                  5                                                       /*!< POSIF PCONF: MCUE Position              */\r
+#define POSIF_PCONF_MCUE_Msk                  (0x01UL << POSIF_PCONF_MCUE_Pos)                        /*!< POSIF PCONF: MCUE Mask                  */\r
+#define POSIF_PCONF_INSEL0_Pos                8                                                       /*!< POSIF PCONF: INSEL0 Position            */\r
+#define POSIF_PCONF_INSEL0_Msk                (0x03UL << POSIF_PCONF_INSEL0_Pos)                      /*!< POSIF PCONF: INSEL0 Mask                */\r
+#define POSIF_PCONF_INSEL1_Pos                10                                                      /*!< POSIF PCONF: INSEL1 Position            */\r
+#define POSIF_PCONF_INSEL1_Msk                (0x03UL << POSIF_PCONF_INSEL1_Pos)                      /*!< POSIF PCONF: INSEL1 Mask                */\r
+#define POSIF_PCONF_INSEL2_Pos                12                                                      /*!< POSIF PCONF: INSEL2 Position            */\r
+#define POSIF_PCONF_INSEL2_Msk                (0x03UL << POSIF_PCONF_INSEL2_Pos)                      /*!< POSIF PCONF: INSEL2 Mask                */\r
+#define POSIF_PCONF_DSEL_Pos                  16                                                      /*!< POSIF PCONF: DSEL Position              */\r
+#define POSIF_PCONF_DSEL_Msk                  (0x01UL << POSIF_PCONF_DSEL_Pos)                        /*!< POSIF PCONF: DSEL Mask                  */\r
+#define POSIF_PCONF_SPES_Pos                  17                                                      /*!< POSIF PCONF: SPES Position              */\r
+#define POSIF_PCONF_SPES_Msk                  (0x01UL << POSIF_PCONF_SPES_Pos)                        /*!< POSIF PCONF: SPES Mask                  */\r
+#define POSIF_PCONF_MSETS_Pos                 18                                                      /*!< POSIF PCONF: MSETS Position             */\r
+#define POSIF_PCONF_MSETS_Msk                 (0x07UL << POSIF_PCONF_MSETS_Pos)                       /*!< POSIF PCONF: MSETS Mask                 */\r
+#define POSIF_PCONF_MSES_Pos                  21                                                      /*!< POSIF PCONF: MSES Position              */\r
+#define POSIF_PCONF_MSES_Msk                  (0x01UL << POSIF_PCONF_MSES_Pos)                        /*!< POSIF PCONF: MSES Mask                  */\r
+#define POSIF_PCONF_MSYNS_Pos                 22                                                      /*!< POSIF PCONF: MSYNS Position             */\r
+#define POSIF_PCONF_MSYNS_Msk                 (0x03UL << POSIF_PCONF_MSYNS_Pos)                       /*!< POSIF PCONF: MSYNS Mask                 */\r
+#define POSIF_PCONF_EWIS_Pos                  24                                                      /*!< POSIF PCONF: EWIS Position              */\r
+#define POSIF_PCONF_EWIS_Msk                  (0x03UL << POSIF_PCONF_EWIS_Pos)                        /*!< POSIF PCONF: EWIS Mask                  */\r
+#define POSIF_PCONF_EWIE_Pos                  26                                                      /*!< POSIF PCONF: EWIE Position              */\r
+#define POSIF_PCONF_EWIE_Msk                  (0x01UL << POSIF_PCONF_EWIE_Pos)                        /*!< POSIF PCONF: EWIE Mask                  */\r
+#define POSIF_PCONF_EWIL_Pos                  27                                                      /*!< POSIF PCONF: EWIL Position              */\r
+#define POSIF_PCONF_EWIL_Msk                  (0x01UL << POSIF_PCONF_EWIL_Pos)                        /*!< POSIF PCONF: EWIL Mask                  */\r
+#define POSIF_PCONF_LPC_Pos                   28                                                      /*!< POSIF PCONF: LPC Position               */\r
+#define POSIF_PCONF_LPC_Msk                   (0x07UL << POSIF_PCONF_LPC_Pos)                         /*!< POSIF PCONF: LPC Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PSUS  --------------------------------- */\r
+#define POSIF_PSUS_QSUS_Pos                   0                                                       /*!< POSIF PSUS: QSUS Position               */\r
+#define POSIF_PSUS_QSUS_Msk                   (0x03UL << POSIF_PSUS_QSUS_Pos)                         /*!< POSIF PSUS: QSUS Mask                   */\r
+#define POSIF_PSUS_MSUS_Pos                   2                                                       /*!< POSIF PSUS: MSUS Position               */\r
+#define POSIF_PSUS_MSUS_Msk                   (0x03UL << POSIF_PSUS_MSUS_Pos)                         /*!< POSIF PSUS: MSUS Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PRUNS  -------------------------------- */\r
+#define POSIF_PRUNS_SRB_Pos                   0                                                       /*!< POSIF PRUNS: SRB Position               */\r
+#define POSIF_PRUNS_SRB_Msk                   (0x01UL << POSIF_PRUNS_SRB_Pos)                         /*!< POSIF PRUNS: SRB Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PRUNC  -------------------------------- */\r
+#define POSIF_PRUNC_CRB_Pos                   0                                                       /*!< POSIF PRUNC: CRB Position               */\r
+#define POSIF_PRUNC_CRB_Msk                   (0x01UL << POSIF_PRUNC_CRB_Pos)                         /*!< POSIF PRUNC: CRB Mask                   */\r
+#define POSIF_PRUNC_CSM_Pos                   1                                                       /*!< POSIF PRUNC: CSM Position               */\r
+#define POSIF_PRUNC_CSM_Msk                   (0x01UL << POSIF_PRUNC_CSM_Pos)                         /*!< POSIF PRUNC: CSM Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PRUN  --------------------------------- */\r
+#define POSIF_PRUN_RB_Pos                     0                                                       /*!< POSIF PRUN: RB Position                 */\r
+#define POSIF_PRUN_RB_Msk                     (0x01UL << POSIF_PRUN_RB_Pos)                           /*!< POSIF PRUN: RB Mask                     */\r
+\r
+/* ---------------------------------  POSIF_MIDR  --------------------------------- */\r
+#define POSIF_MIDR_MODR_Pos                   0                                                       /*!< POSIF MIDR: MODR Position               */\r
+#define POSIF_MIDR_MODR_Msk                   (0x000000ffUL << POSIF_MIDR_MODR_Pos)                   /*!< POSIF MIDR: MODR Mask                   */\r
+#define POSIF_MIDR_MODT_Pos                   8                                                       /*!< POSIF MIDR: MODT Position               */\r
+#define POSIF_MIDR_MODT_Msk                   (0x000000ffUL << POSIF_MIDR_MODT_Pos)                   /*!< POSIF MIDR: MODT Mask                   */\r
+#define POSIF_MIDR_MODN_Pos                   16                                                      /*!< POSIF MIDR: MODN Position               */\r
+#define POSIF_MIDR_MODN_Msk                   (0x0000ffffUL << POSIF_MIDR_MODN_Pos)                   /*!< POSIF MIDR: MODN Mask                   */\r
+\r
+/* ---------------------------------  POSIF_HALP  --------------------------------- */\r
+#define POSIF_HALP_HCP_Pos                    0                                                       /*!< POSIF HALP: HCP Position                */\r
+#define POSIF_HALP_HCP_Msk                    (0x07UL << POSIF_HALP_HCP_Pos)                          /*!< POSIF HALP: HCP Mask                    */\r
+#define POSIF_HALP_HEP_Pos                    3                                                       /*!< POSIF HALP: HEP Position                */\r
+#define POSIF_HALP_HEP_Msk                    (0x07UL << POSIF_HALP_HEP_Pos)                          /*!< POSIF HALP: HEP Mask                    */\r
+\r
+/* ---------------------------------  POSIF_HALPS  -------------------------------- */\r
+#define POSIF_HALPS_HCPS_Pos                  0                                                       /*!< POSIF HALPS: HCPS Position              */\r
+#define POSIF_HALPS_HCPS_Msk                  (0x07UL << POSIF_HALPS_HCPS_Pos)                        /*!< POSIF HALPS: HCPS Mask                  */\r
+#define POSIF_HALPS_HEPS_Pos                  3                                                       /*!< POSIF HALPS: HEPS Position              */\r
+#define POSIF_HALPS_HEPS_Msk                  (0x07UL << POSIF_HALPS_HEPS_Pos)                        /*!< POSIF HALPS: HEPS Mask                  */\r
+\r
+/* ----------------------------------  POSIF_MCM  --------------------------------- */\r
+#define POSIF_MCM_MCMP_Pos                    0                                                       /*!< POSIF MCM: MCMP Position                */\r
+#define POSIF_MCM_MCMP_Msk                    (0x0000ffffUL << POSIF_MCM_MCMP_Pos)                    /*!< POSIF MCM: MCMP Mask                    */\r
+\r
+/* ---------------------------------  POSIF_MCSM  --------------------------------- */\r
+#define POSIF_MCSM_MCMPS_Pos                  0                                                       /*!< POSIF MCSM: MCMPS Position              */\r
+#define POSIF_MCSM_MCMPS_Msk                  (0x0000ffffUL << POSIF_MCSM_MCMPS_Pos)                  /*!< POSIF MCSM: MCMPS Mask                  */\r
+\r
+/* ---------------------------------  POSIF_MCMS  --------------------------------- */\r
+#define POSIF_MCMS_MNPS_Pos                   0                                                       /*!< POSIF MCMS: MNPS Position               */\r
+#define POSIF_MCMS_MNPS_Msk                   (0x01UL << POSIF_MCMS_MNPS_Pos)                         /*!< POSIF MCMS: MNPS Mask                   */\r
+#define POSIF_MCMS_STHR_Pos                   1                                                       /*!< POSIF MCMS: STHR Position               */\r
+#define POSIF_MCMS_STHR_Msk                   (0x01UL << POSIF_MCMS_STHR_Pos)                         /*!< POSIF MCMS: STHR Mask                   */\r
+#define POSIF_MCMS_STMR_Pos                   2                                                       /*!< POSIF MCMS: STMR Position               */\r
+#define POSIF_MCMS_STMR_Msk                   (0x01UL << POSIF_MCMS_STMR_Pos)                         /*!< POSIF MCMS: STMR Mask                   */\r
+\r
+/* ---------------------------------  POSIF_MCMC  --------------------------------- */\r
+#define POSIF_MCMC_MNPC_Pos                   0                                                       /*!< POSIF MCMC: MNPC Position               */\r
+#define POSIF_MCMC_MNPC_Msk                   (0x01UL << POSIF_MCMC_MNPC_Pos)                         /*!< POSIF MCMC: MNPC Mask                   */\r
+#define POSIF_MCMC_MPC_Pos                    1                                                       /*!< POSIF MCMC: MPC Position                */\r
+#define POSIF_MCMC_MPC_Msk                    (0x01UL << POSIF_MCMC_MPC_Pos)                          /*!< POSIF MCMC: MPC Mask                    */\r
+\r
+/* ---------------------------------  POSIF_MCMF  --------------------------------- */\r
+#define POSIF_MCMF_MSS_Pos                    0                                                       /*!< POSIF MCMF: MSS Position                */\r
+#define POSIF_MCMF_MSS_Msk                    (0x01UL << POSIF_MCMF_MSS_Pos)                          /*!< POSIF MCMF: MSS Mask                    */\r
+\r
+/* ----------------------------------  POSIF_QDC  --------------------------------- */\r
+#define POSIF_QDC_PALS_Pos                    0                                                       /*!< POSIF QDC: PALS Position                */\r
+#define POSIF_QDC_PALS_Msk                    (0x01UL << POSIF_QDC_PALS_Pos)                          /*!< POSIF QDC: PALS Mask                    */\r
+#define POSIF_QDC_PBLS_Pos                    1                                                       /*!< POSIF QDC: PBLS Position                */\r
+#define POSIF_QDC_PBLS_Msk                    (0x01UL << POSIF_QDC_PBLS_Pos)                          /*!< POSIF QDC: PBLS Mask                    */\r
+#define POSIF_QDC_PHS_Pos                     2                                                       /*!< POSIF QDC: PHS Position                 */\r
+#define POSIF_QDC_PHS_Msk                     (0x01UL << POSIF_QDC_PHS_Pos)                           /*!< POSIF QDC: PHS Mask                     */\r
+#define POSIF_QDC_ICM_Pos                     4                                                       /*!< POSIF QDC: ICM Position                 */\r
+#define POSIF_QDC_ICM_Msk                     (0x03UL << POSIF_QDC_ICM_Pos)                           /*!< POSIF QDC: ICM Mask                     */\r
+#define POSIF_QDC_DVAL_Pos                    8                                                       /*!< POSIF QDC: DVAL Position                */\r
+#define POSIF_QDC_DVAL_Msk                    (0x01UL << POSIF_QDC_DVAL_Pos)                          /*!< POSIF QDC: DVAL Mask                    */\r
+\r
+/* ---------------------------------  POSIF_PFLG  --------------------------------- */\r
+#define POSIF_PFLG_CHES_Pos                   0                                                       /*!< POSIF PFLG: CHES Position               */\r
+#define POSIF_PFLG_CHES_Msk                   (0x01UL << POSIF_PFLG_CHES_Pos)                         /*!< POSIF PFLG: CHES Mask                   */\r
+#define POSIF_PFLG_WHES_Pos                   1                                                       /*!< POSIF PFLG: WHES Position               */\r
+#define POSIF_PFLG_WHES_Msk                   (0x01UL << POSIF_PFLG_WHES_Pos)                         /*!< POSIF PFLG: WHES Mask                   */\r
+#define POSIF_PFLG_HIES_Pos                   2                                                       /*!< POSIF PFLG: HIES Position               */\r
+#define POSIF_PFLG_HIES_Msk                   (0x01UL << POSIF_PFLG_HIES_Pos)                         /*!< POSIF PFLG: HIES Mask                   */\r
+#define POSIF_PFLG_MSTS_Pos                   4                                                       /*!< POSIF PFLG: MSTS Position               */\r
+#define POSIF_PFLG_MSTS_Msk                   (0x01UL << POSIF_PFLG_MSTS_Pos)                         /*!< POSIF PFLG: MSTS Mask                   */\r
+#define POSIF_PFLG_INDXS_Pos                  8                                                       /*!< POSIF PFLG: INDXS Position              */\r
+#define POSIF_PFLG_INDXS_Msk                  (0x01UL << POSIF_PFLG_INDXS_Pos)                        /*!< POSIF PFLG: INDXS Mask                  */\r
+#define POSIF_PFLG_ERRS_Pos                   9                                                       /*!< POSIF PFLG: ERRS Position               */\r
+#define POSIF_PFLG_ERRS_Msk                   (0x01UL << POSIF_PFLG_ERRS_Pos)                         /*!< POSIF PFLG: ERRS Mask                   */\r
+#define POSIF_PFLG_CNTS_Pos                   10                                                      /*!< POSIF PFLG: CNTS Position               */\r
+#define POSIF_PFLG_CNTS_Msk                   (0x01UL << POSIF_PFLG_CNTS_Pos)                         /*!< POSIF PFLG: CNTS Mask                   */\r
+#define POSIF_PFLG_DIRS_Pos                   11                                                      /*!< POSIF PFLG: DIRS Position               */\r
+#define POSIF_PFLG_DIRS_Msk                   (0x01UL << POSIF_PFLG_DIRS_Pos)                         /*!< POSIF PFLG: DIRS Mask                   */\r
+#define POSIF_PFLG_PCLKS_Pos                  12                                                      /*!< POSIF PFLG: PCLKS Position              */\r
+#define POSIF_PFLG_PCLKS_Msk                  (0x01UL << POSIF_PFLG_PCLKS_Pos)                        /*!< POSIF PFLG: PCLKS Mask                  */\r
+\r
+/* ---------------------------------  POSIF_PFLGE  -------------------------------- */\r
+#define POSIF_PFLGE_ECHE_Pos                  0                                                       /*!< POSIF PFLGE: ECHE Position              */\r
+#define POSIF_PFLGE_ECHE_Msk                  (0x01UL << POSIF_PFLGE_ECHE_Pos)                        /*!< POSIF PFLGE: ECHE Mask                  */\r
+#define POSIF_PFLGE_EWHE_Pos                  1                                                       /*!< POSIF PFLGE: EWHE Position              */\r
+#define POSIF_PFLGE_EWHE_Msk                  (0x01UL << POSIF_PFLGE_EWHE_Pos)                        /*!< POSIF PFLGE: EWHE Mask                  */\r
+#define POSIF_PFLGE_EHIE_Pos                  2                                                       /*!< POSIF PFLGE: EHIE Position              */\r
+#define POSIF_PFLGE_EHIE_Msk                  (0x01UL << POSIF_PFLGE_EHIE_Pos)                        /*!< POSIF PFLGE: EHIE Mask                  */\r
+#define POSIF_PFLGE_EMST_Pos                  4                                                       /*!< POSIF PFLGE: EMST Position              */\r
+#define POSIF_PFLGE_EMST_Msk                  (0x01UL << POSIF_PFLGE_EMST_Pos)                        /*!< POSIF PFLGE: EMST Mask                  */\r
+#define POSIF_PFLGE_EINDX_Pos                 8                                                       /*!< POSIF PFLGE: EINDX Position             */\r
+#define POSIF_PFLGE_EINDX_Msk                 (0x01UL << POSIF_PFLGE_EINDX_Pos)                       /*!< POSIF PFLGE: EINDX Mask                 */\r
+#define POSIF_PFLGE_EERR_Pos                  9                                                       /*!< POSIF PFLGE: EERR Position              */\r
+#define POSIF_PFLGE_EERR_Msk                  (0x01UL << POSIF_PFLGE_EERR_Pos)                        /*!< POSIF PFLGE: EERR Mask                  */\r
+#define POSIF_PFLGE_ECNT_Pos                  10                                                      /*!< POSIF PFLGE: ECNT Position              */\r
+#define POSIF_PFLGE_ECNT_Msk                  (0x01UL << POSIF_PFLGE_ECNT_Pos)                        /*!< POSIF PFLGE: ECNT Mask                  */\r
+#define POSIF_PFLGE_EDIR_Pos                  11                                                      /*!< POSIF PFLGE: EDIR Position              */\r
+#define POSIF_PFLGE_EDIR_Msk                  (0x01UL << POSIF_PFLGE_EDIR_Pos)                        /*!< POSIF PFLGE: EDIR Mask                  */\r
+#define POSIF_PFLGE_EPCLK_Pos                 12                                                      /*!< POSIF PFLGE: EPCLK Position             */\r
+#define POSIF_PFLGE_EPCLK_Msk                 (0x01UL << POSIF_PFLGE_EPCLK_Pos)                       /*!< POSIF PFLGE: EPCLK Mask                 */\r
+#define POSIF_PFLGE_CHESEL_Pos                16                                                      /*!< POSIF PFLGE: CHESEL Position            */\r
+#define POSIF_PFLGE_CHESEL_Msk                (0x01UL << POSIF_PFLGE_CHESEL_Pos)                      /*!< POSIF PFLGE: CHESEL Mask                */\r
+#define POSIF_PFLGE_WHESEL_Pos                17                                                      /*!< POSIF PFLGE: WHESEL Position            */\r
+#define POSIF_PFLGE_WHESEL_Msk                (0x01UL << POSIF_PFLGE_WHESEL_Pos)                      /*!< POSIF PFLGE: WHESEL Mask                */\r
+#define POSIF_PFLGE_HIESEL_Pos                18                                                      /*!< POSIF PFLGE: HIESEL Position            */\r
+#define POSIF_PFLGE_HIESEL_Msk                (0x01UL << POSIF_PFLGE_HIESEL_Pos)                      /*!< POSIF PFLGE: HIESEL Mask                */\r
+#define POSIF_PFLGE_MSTSEL_Pos                20                                                      /*!< POSIF PFLGE: MSTSEL Position            */\r
+#define POSIF_PFLGE_MSTSEL_Msk                (0x01UL << POSIF_PFLGE_MSTSEL_Pos)                      /*!< POSIF PFLGE: MSTSEL Mask                */\r
+#define POSIF_PFLGE_INDSEL_Pos                24                                                      /*!< POSIF PFLGE: INDSEL Position            */\r
+#define POSIF_PFLGE_INDSEL_Msk                (0x01UL << POSIF_PFLGE_INDSEL_Pos)                      /*!< POSIF PFLGE: INDSEL Mask                */\r
+#define POSIF_PFLGE_ERRSEL_Pos                25                                                      /*!< POSIF PFLGE: ERRSEL Position            */\r
+#define POSIF_PFLGE_ERRSEL_Msk                (0x01UL << POSIF_PFLGE_ERRSEL_Pos)                      /*!< POSIF PFLGE: ERRSEL Mask                */\r
+#define POSIF_PFLGE_CNTSEL_Pos                26                                                      /*!< POSIF PFLGE: CNTSEL Position            */\r
+#define POSIF_PFLGE_CNTSEL_Msk                (0x01UL << POSIF_PFLGE_CNTSEL_Pos)                      /*!< POSIF PFLGE: CNTSEL Mask                */\r
+#define POSIF_PFLGE_DIRSEL_Pos                27                                                      /*!< POSIF PFLGE: DIRSEL Position            */\r
+#define POSIF_PFLGE_DIRSEL_Msk                (0x01UL << POSIF_PFLGE_DIRSEL_Pos)                      /*!< POSIF PFLGE: DIRSEL Mask                */\r
+#define POSIF_PFLGE_PCLSEL_Pos                28                                                      /*!< POSIF PFLGE: PCLSEL Position            */\r
+#define POSIF_PFLGE_PCLSEL_Msk                (0x01UL << POSIF_PFLGE_PCLSEL_Pos)                      /*!< POSIF PFLGE: PCLSEL Mask                */\r
+\r
+/* ---------------------------------  POSIF_SPFLG  -------------------------------- */\r
+#define POSIF_SPFLG_SCHE_Pos                  0                                                       /*!< POSIF SPFLG: SCHE Position              */\r
+#define POSIF_SPFLG_SCHE_Msk                  (0x01UL << POSIF_SPFLG_SCHE_Pos)                        /*!< POSIF SPFLG: SCHE Mask                  */\r
+#define POSIF_SPFLG_SWHE_Pos                  1                                                       /*!< POSIF SPFLG: SWHE Position              */\r
+#define POSIF_SPFLG_SWHE_Msk                  (0x01UL << POSIF_SPFLG_SWHE_Pos)                        /*!< POSIF SPFLG: SWHE Mask                  */\r
+#define POSIF_SPFLG_SHIE_Pos                  2                                                       /*!< POSIF SPFLG: SHIE Position              */\r
+#define POSIF_SPFLG_SHIE_Msk                  (0x01UL << POSIF_SPFLG_SHIE_Pos)                        /*!< POSIF SPFLG: SHIE Mask                  */\r
+#define POSIF_SPFLG_SMST_Pos                  4                                                       /*!< POSIF SPFLG: SMST Position              */\r
+#define POSIF_SPFLG_SMST_Msk                  (0x01UL << POSIF_SPFLG_SMST_Pos)                        /*!< POSIF SPFLG: SMST Mask                  */\r
+#define POSIF_SPFLG_SINDX_Pos                 8                                                       /*!< POSIF SPFLG: SINDX Position             */\r
+#define POSIF_SPFLG_SINDX_Msk                 (0x01UL << POSIF_SPFLG_SINDX_Pos)                       /*!< POSIF SPFLG: SINDX Mask                 */\r
+#define POSIF_SPFLG_SERR_Pos                  9                                                       /*!< POSIF SPFLG: SERR Position              */\r
+#define POSIF_SPFLG_SERR_Msk                  (0x01UL << POSIF_SPFLG_SERR_Pos)                        /*!< POSIF SPFLG: SERR Mask                  */\r
+#define POSIF_SPFLG_SCNT_Pos                  10                                                      /*!< POSIF SPFLG: SCNT Position              */\r
+#define POSIF_SPFLG_SCNT_Msk                  (0x01UL << POSIF_SPFLG_SCNT_Pos)                        /*!< POSIF SPFLG: SCNT Mask                  */\r
+#define POSIF_SPFLG_SDIR_Pos                  11                                                      /*!< POSIF SPFLG: SDIR Position              */\r
+#define POSIF_SPFLG_SDIR_Msk                  (0x01UL << POSIF_SPFLG_SDIR_Pos)                        /*!< POSIF SPFLG: SDIR Mask                  */\r
+#define POSIF_SPFLG_SPCLK_Pos                 12                                                      /*!< POSIF SPFLG: SPCLK Position             */\r
+#define POSIF_SPFLG_SPCLK_Msk                 (0x01UL << POSIF_SPFLG_SPCLK_Pos)                       /*!< POSIF SPFLG: SPCLK Mask                 */\r
+\r
+/* ---------------------------------  POSIF_RPFLG  -------------------------------- */\r
+#define POSIF_RPFLG_RCHE_Pos                  0                                                       /*!< POSIF RPFLG: RCHE Position              */\r
+#define POSIF_RPFLG_RCHE_Msk                  (0x01UL << POSIF_RPFLG_RCHE_Pos)                        /*!< POSIF RPFLG: RCHE Mask                  */\r
+#define POSIF_RPFLG_RWHE_Pos                  1                                                       /*!< POSIF RPFLG: RWHE Position              */\r
+#define POSIF_RPFLG_RWHE_Msk                  (0x01UL << POSIF_RPFLG_RWHE_Pos)                        /*!< POSIF RPFLG: RWHE Mask                  */\r
+#define POSIF_RPFLG_RHIE_Pos                  2                                                       /*!< POSIF RPFLG: RHIE Position              */\r
+#define POSIF_RPFLG_RHIE_Msk                  (0x01UL << POSIF_RPFLG_RHIE_Pos)                        /*!< POSIF RPFLG: RHIE Mask                  */\r
+#define POSIF_RPFLG_RMST_Pos                  4                                                       /*!< POSIF RPFLG: RMST Position              */\r
+#define POSIF_RPFLG_RMST_Msk                  (0x01UL << POSIF_RPFLG_RMST_Pos)                        /*!< POSIF RPFLG: RMST Mask                  */\r
+#define POSIF_RPFLG_RINDX_Pos                 8                                                       /*!< POSIF RPFLG: RINDX Position             */\r
+#define POSIF_RPFLG_RINDX_Msk                 (0x01UL << POSIF_RPFLG_RINDX_Pos)                       /*!< POSIF RPFLG: RINDX Mask                 */\r
+#define POSIF_RPFLG_RERR_Pos                  9                                                       /*!< POSIF RPFLG: RERR Position              */\r
+#define POSIF_RPFLG_RERR_Msk                  (0x01UL << POSIF_RPFLG_RERR_Pos)                        /*!< POSIF RPFLG: RERR Mask                  */\r
+#define POSIF_RPFLG_RCNT_Pos                  10                                                      /*!< POSIF RPFLG: RCNT Position              */\r
+#define POSIF_RPFLG_RCNT_Msk                  (0x01UL << POSIF_RPFLG_RCNT_Pos)                        /*!< POSIF RPFLG: RCNT Mask                  */\r
+#define POSIF_RPFLG_RDIR_Pos                  11                                                      /*!< POSIF RPFLG: RDIR Position              */\r
+#define POSIF_RPFLG_RDIR_Msk                  (0x01UL << POSIF_RPFLG_RDIR_Pos)                        /*!< POSIF RPFLG: RDIR Mask                  */\r
+#define POSIF_RPFLG_RPCLK_Pos                 12                                                      /*!< POSIF RPFLG: RPCLK Position             */\r
+#define POSIF_RPFLG_RPCLK_Msk                 (0x01UL << POSIF_RPFLG_RPCLK_Pos)                       /*!< POSIF RPFLG: RPCLK Mask                 */\r
+\r
+/* ---------------------------------  POSIF_PDBG  --------------------------------- */\r
+#define POSIF_PDBG_QCSV_Pos                   0                                                       /*!< POSIF PDBG: QCSV Position               */\r
+#define POSIF_PDBG_QCSV_Msk                   (0x03UL << POSIF_PDBG_QCSV_Pos)                         /*!< POSIF PDBG: QCSV Mask                   */\r
+#define POSIF_PDBG_QPSV_Pos                   2                                                       /*!< POSIF PDBG: QPSV Position               */\r
+#define POSIF_PDBG_QPSV_Msk                   (0x03UL << POSIF_PDBG_QPSV_Pos)                         /*!< POSIF PDBG: QPSV Mask                   */\r
+#define POSIF_PDBG_IVAL_Pos                   4                                                       /*!< POSIF PDBG: IVAL Position               */\r
+#define POSIF_PDBG_IVAL_Msk                   (0x01UL << POSIF_PDBG_IVAL_Pos)                         /*!< POSIF PDBG: IVAL Mask                   */\r
+#define POSIF_PDBG_HSP_Pos                    5                                                       /*!< POSIF PDBG: HSP Position                */\r
+#define POSIF_PDBG_HSP_Msk                    (0x07UL << POSIF_PDBG_HSP_Pos)                          /*!< POSIF PDBG: HSP Mask                    */\r
+#define POSIF_PDBG_LPP0_Pos                   8                                                       /*!< POSIF PDBG: LPP0 Position               */\r
+#define POSIF_PDBG_LPP0_Msk                   (0x3fUL << POSIF_PDBG_LPP0_Pos)                         /*!< POSIF PDBG: LPP0 Mask                   */\r
+#define POSIF_PDBG_LPP1_Pos                   16                                                      /*!< POSIF PDBG: LPP1 Position               */\r
+#define POSIF_PDBG_LPP1_Msk                   (0x3fUL << POSIF_PDBG_LPP1_Pos)                         /*!< POSIF PDBG: LPP1 Mask                   */\r
+#define POSIF_PDBG_LPP2_Pos                   22                                                      /*!< POSIF PDBG: LPP2 Position               */\r
+#define POSIF_PDBG_LPP2_Msk                   (0x3fUL << POSIF_PDBG_LPP2_Pos)                         /*!< POSIF PDBG: LPP2 Mask                   */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT0' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT0_OUT  --------------------------------- */\r
+#define PORT0_OUT_P0_Pos                      0                                                       /*!< PORT0 OUT: P0 Position                  */\r
+#define PORT0_OUT_P0_Msk                      (0x01UL << PORT0_OUT_P0_Pos)                            /*!< PORT0 OUT: P0 Mask                      */\r
+#define PORT0_OUT_P1_Pos                      1                                                       /*!< PORT0 OUT: P1 Position                  */\r
+#define PORT0_OUT_P1_Msk                      (0x01UL << PORT0_OUT_P1_Pos)                            /*!< PORT0 OUT: P1 Mask                      */\r
+#define PORT0_OUT_P2_Pos                      2                                                       /*!< PORT0 OUT: P2 Position                  */\r
+#define PORT0_OUT_P2_Msk                      (0x01UL << PORT0_OUT_P2_Pos)                            /*!< PORT0 OUT: P2 Mask                      */\r
+#define PORT0_OUT_P3_Pos                      3                                                       /*!< PORT0 OUT: P3 Position                  */\r
+#define PORT0_OUT_P3_Msk                      (0x01UL << PORT0_OUT_P3_Pos)                            /*!< PORT0 OUT: P3 Mask                      */\r
+#define PORT0_OUT_P4_Pos                      4                                                       /*!< PORT0 OUT: P4 Position                  */\r
+#define PORT0_OUT_P4_Msk                      (0x01UL << PORT0_OUT_P4_Pos)                            /*!< PORT0 OUT: P4 Mask                      */\r
+#define PORT0_OUT_P5_Pos                      5                                                       /*!< PORT0 OUT: P5 Position                  */\r
+#define PORT0_OUT_P5_Msk                      (0x01UL << PORT0_OUT_P5_Pos)                            /*!< PORT0 OUT: P5 Mask                      */\r
+#define PORT0_OUT_P6_Pos                      6                                                       /*!< PORT0 OUT: P6 Position                  */\r
+#define PORT0_OUT_P6_Msk                      (0x01UL << PORT0_OUT_P6_Pos)                            /*!< PORT0 OUT: P6 Mask                      */\r
+#define PORT0_OUT_P7_Pos                      7                                                       /*!< PORT0 OUT: P7 Position                  */\r
+#define PORT0_OUT_P7_Msk                      (0x01UL << PORT0_OUT_P7_Pos)                            /*!< PORT0 OUT: P7 Mask                      */\r
+#define PORT0_OUT_P8_Pos                      8                                                       /*!< PORT0 OUT: P8 Position                  */\r
+#define PORT0_OUT_P8_Msk                      (0x01UL << PORT0_OUT_P8_Pos)                            /*!< PORT0 OUT: P8 Mask                      */\r
+#define PORT0_OUT_P9_Pos                      9                                                       /*!< PORT0 OUT: P9 Position                  */\r
+#define PORT0_OUT_P9_Msk                      (0x01UL << PORT0_OUT_P9_Pos)                            /*!< PORT0 OUT: P9 Mask                      */\r
+#define PORT0_OUT_P10_Pos                     10                                                      /*!< PORT0 OUT: P10 Position                 */\r
+#define PORT0_OUT_P10_Msk                     (0x01UL << PORT0_OUT_P10_Pos)                           /*!< PORT0 OUT: P10 Mask                     */\r
+#define PORT0_OUT_P11_Pos                     11                                                      /*!< PORT0 OUT: P11 Position                 */\r
+#define PORT0_OUT_P11_Msk                     (0x01UL << PORT0_OUT_P11_Pos)                           /*!< PORT0 OUT: P11 Mask                     */\r
+#define PORT0_OUT_P12_Pos                     12                                                      /*!< PORT0 OUT: P12 Position                 */\r
+#define PORT0_OUT_P12_Msk                     (0x01UL << PORT0_OUT_P12_Pos)                           /*!< PORT0 OUT: P12 Mask                     */\r
+#define PORT0_OUT_P13_Pos                     13                                                      /*!< PORT0 OUT: P13 Position                 */\r
+#define PORT0_OUT_P13_Msk                     (0x01UL << PORT0_OUT_P13_Pos)                           /*!< PORT0 OUT: P13 Mask                     */\r
+#define PORT0_OUT_P14_Pos                     14                                                      /*!< PORT0 OUT: P14 Position                 */\r
+#define PORT0_OUT_P14_Msk                     (0x01UL << PORT0_OUT_P14_Pos)                           /*!< PORT0 OUT: P14 Mask                     */\r
+#define PORT0_OUT_P15_Pos                     15                                                      /*!< PORT0 OUT: P15 Position                 */\r
+#define PORT0_OUT_P15_Msk                     (0x01UL << PORT0_OUT_P15_Pos)                           /*!< PORT0 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT0_OMR  --------------------------------- */\r
+#define PORT0_OMR_PS0_Pos                     0                                                       /*!< PORT0 OMR: PS0 Position                 */\r
+#define PORT0_OMR_PS0_Msk                     (0x01UL << PORT0_OMR_PS0_Pos)                           /*!< PORT0 OMR: PS0 Mask                     */\r
+#define PORT0_OMR_PS1_Pos                     1                                                       /*!< PORT0 OMR: PS1 Position                 */\r
+#define PORT0_OMR_PS1_Msk                     (0x01UL << PORT0_OMR_PS1_Pos)                           /*!< PORT0 OMR: PS1 Mask                     */\r
+#define PORT0_OMR_PS2_Pos                     2                                                       /*!< PORT0 OMR: PS2 Position                 */\r
+#define PORT0_OMR_PS2_Msk                     (0x01UL << PORT0_OMR_PS2_Pos)                           /*!< PORT0 OMR: PS2 Mask                     */\r
+#define PORT0_OMR_PS3_Pos                     3                                                       /*!< PORT0 OMR: PS3 Position                 */\r
+#define PORT0_OMR_PS3_Msk                     (0x01UL << PORT0_OMR_PS3_Pos)                           /*!< PORT0 OMR: PS3 Mask                     */\r
+#define PORT0_OMR_PS4_Pos                     4                                                       /*!< PORT0 OMR: PS4 Position                 */\r
+#define PORT0_OMR_PS4_Msk                     (0x01UL << PORT0_OMR_PS4_Pos)                           /*!< PORT0 OMR: PS4 Mask                     */\r
+#define PORT0_OMR_PS5_Pos                     5                                                       /*!< PORT0 OMR: PS5 Position                 */\r
+#define PORT0_OMR_PS5_Msk                     (0x01UL << PORT0_OMR_PS5_Pos)                           /*!< PORT0 OMR: PS5 Mask                     */\r
+#define PORT0_OMR_PS6_Pos                     6                                                       /*!< PORT0 OMR: PS6 Position                 */\r
+#define PORT0_OMR_PS6_Msk                     (0x01UL << PORT0_OMR_PS6_Pos)                           /*!< PORT0 OMR: PS6 Mask                     */\r
+#define PORT0_OMR_PS7_Pos                     7                                                       /*!< PORT0 OMR: PS7 Position                 */\r
+#define PORT0_OMR_PS7_Msk                     (0x01UL << PORT0_OMR_PS7_Pos)                           /*!< PORT0 OMR: PS7 Mask                     */\r
+#define PORT0_OMR_PS8_Pos                     8                                                       /*!< PORT0 OMR: PS8 Position                 */\r
+#define PORT0_OMR_PS8_Msk                     (0x01UL << PORT0_OMR_PS8_Pos)                           /*!< PORT0 OMR: PS8 Mask                     */\r
+#define PORT0_OMR_PS9_Pos                     9                                                       /*!< PORT0 OMR: PS9 Position                 */\r
+#define PORT0_OMR_PS9_Msk                     (0x01UL << PORT0_OMR_PS9_Pos)                           /*!< PORT0 OMR: PS9 Mask                     */\r
+#define PORT0_OMR_PS10_Pos                    10                                                      /*!< PORT0 OMR: PS10 Position                */\r
+#define PORT0_OMR_PS10_Msk                    (0x01UL << PORT0_OMR_PS10_Pos)                          /*!< PORT0 OMR: PS10 Mask                    */\r
+#define PORT0_OMR_PS11_Pos                    11                                                      /*!< PORT0 OMR: PS11 Position                */\r
+#define PORT0_OMR_PS11_Msk                    (0x01UL << PORT0_OMR_PS11_Pos)                          /*!< PORT0 OMR: PS11 Mask                    */\r
+#define PORT0_OMR_PS12_Pos                    12                                                      /*!< PORT0 OMR: PS12 Position                */\r
+#define PORT0_OMR_PS12_Msk                    (0x01UL << PORT0_OMR_PS12_Pos)                          /*!< PORT0 OMR: PS12 Mask                    */\r
+#define PORT0_OMR_PS13_Pos                    13                                                      /*!< PORT0 OMR: PS13 Position                */\r
+#define PORT0_OMR_PS13_Msk                    (0x01UL << PORT0_OMR_PS13_Pos)                          /*!< PORT0 OMR: PS13 Mask                    */\r
+#define PORT0_OMR_PS14_Pos                    14                                                      /*!< PORT0 OMR: PS14 Position                */\r
+#define PORT0_OMR_PS14_Msk                    (0x01UL << PORT0_OMR_PS14_Pos)                          /*!< PORT0 OMR: PS14 Mask                    */\r
+#define PORT0_OMR_PS15_Pos                    15                                                      /*!< PORT0 OMR: PS15 Position                */\r
+#define PORT0_OMR_PS15_Msk                    (0x01UL << PORT0_OMR_PS15_Pos)                          /*!< PORT0 OMR: PS15 Mask                    */\r
+#define PORT0_OMR_PR0_Pos                     16                                                      /*!< PORT0 OMR: PR0 Position                 */\r
+#define PORT0_OMR_PR0_Msk                     (0x01UL << PORT0_OMR_PR0_Pos)                           /*!< PORT0 OMR: PR0 Mask                     */\r
+#define PORT0_OMR_PR1_Pos                     17                                                      /*!< PORT0 OMR: PR1 Position                 */\r
+#define PORT0_OMR_PR1_Msk                     (0x01UL << PORT0_OMR_PR1_Pos)                           /*!< PORT0 OMR: PR1 Mask                     */\r
+#define PORT0_OMR_PR2_Pos                     18                                                      /*!< PORT0 OMR: PR2 Position                 */\r
+#define PORT0_OMR_PR2_Msk                     (0x01UL << PORT0_OMR_PR2_Pos)                           /*!< PORT0 OMR: PR2 Mask                     */\r
+#define PORT0_OMR_PR3_Pos                     19                                                      /*!< PORT0 OMR: PR3 Position                 */\r
+#define PORT0_OMR_PR3_Msk                     (0x01UL << PORT0_OMR_PR3_Pos)                           /*!< PORT0 OMR: PR3 Mask                     */\r
+#define PORT0_OMR_PR4_Pos                     20                                                      /*!< PORT0 OMR: PR4 Position                 */\r
+#define PORT0_OMR_PR4_Msk                     (0x01UL << PORT0_OMR_PR4_Pos)                           /*!< PORT0 OMR: PR4 Mask                     */\r
+#define PORT0_OMR_PR5_Pos                     21                                                      /*!< PORT0 OMR: PR5 Position                 */\r
+#define PORT0_OMR_PR5_Msk                     (0x01UL << PORT0_OMR_PR5_Pos)                           /*!< PORT0 OMR: PR5 Mask                     */\r
+#define PORT0_OMR_PR6_Pos                     22                                                      /*!< PORT0 OMR: PR6 Position                 */\r
+#define PORT0_OMR_PR6_Msk                     (0x01UL << PORT0_OMR_PR6_Pos)                           /*!< PORT0 OMR: PR6 Mask                     */\r
+#define PORT0_OMR_PR7_Pos                     23                                                      /*!< PORT0 OMR: PR7 Position                 */\r
+#define PORT0_OMR_PR7_Msk                     (0x01UL << PORT0_OMR_PR7_Pos)                           /*!< PORT0 OMR: PR7 Mask                     */\r
+#define PORT0_OMR_PR8_Pos                     24                                                      /*!< PORT0 OMR: PR8 Position                 */\r
+#define PORT0_OMR_PR8_Msk                     (0x01UL << PORT0_OMR_PR8_Pos)                           /*!< PORT0 OMR: PR8 Mask                     */\r
+#define PORT0_OMR_PR9_Pos                     25                                                      /*!< PORT0 OMR: PR9 Position                 */\r
+#define PORT0_OMR_PR9_Msk                     (0x01UL << PORT0_OMR_PR9_Pos)                           /*!< PORT0 OMR: PR9 Mask                     */\r
+#define PORT0_OMR_PR10_Pos                    26                                                      /*!< PORT0 OMR: PR10 Position                */\r
+#define PORT0_OMR_PR10_Msk                    (0x01UL << PORT0_OMR_PR10_Pos)                          /*!< PORT0 OMR: PR10 Mask                    */\r
+#define PORT0_OMR_PR11_Pos                    27                                                      /*!< PORT0 OMR: PR11 Position                */\r
+#define PORT0_OMR_PR11_Msk                    (0x01UL << PORT0_OMR_PR11_Pos)                          /*!< PORT0 OMR: PR11 Mask                    */\r
+#define PORT0_OMR_PR12_Pos                    28                                                      /*!< PORT0 OMR: PR12 Position                */\r
+#define PORT0_OMR_PR12_Msk                    (0x01UL << PORT0_OMR_PR12_Pos)                          /*!< PORT0 OMR: PR12 Mask                    */\r
+#define PORT0_OMR_PR13_Pos                    29                                                      /*!< PORT0 OMR: PR13 Position                */\r
+#define PORT0_OMR_PR13_Msk                    (0x01UL << PORT0_OMR_PR13_Pos)                          /*!< PORT0 OMR: PR13 Mask                    */\r
+#define PORT0_OMR_PR14_Pos                    30                                                      /*!< PORT0 OMR: PR14 Position                */\r
+#define PORT0_OMR_PR14_Msk                    (0x01UL << PORT0_OMR_PR14_Pos)                          /*!< PORT0 OMR: PR14 Mask                    */\r
+#define PORT0_OMR_PR15_Pos                    31                                                      /*!< PORT0 OMR: PR15 Position                */\r
+#define PORT0_OMR_PR15_Msk                    (0x01UL << PORT0_OMR_PR15_Pos)                          /*!< PORT0 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT0_IOCR0  -------------------------------- */\r
+#define PORT0_IOCR0_PC0_Pos                   3                                                       /*!< PORT0 IOCR0: PC0 Position               */\r
+#define PORT0_IOCR0_PC0_Msk                   (0x1fUL << PORT0_IOCR0_PC0_Pos)                         /*!< PORT0 IOCR0: PC0 Mask                   */\r
+#define PORT0_IOCR0_PC1_Pos                   11                                                      /*!< PORT0 IOCR0: PC1 Position               */\r
+#define PORT0_IOCR0_PC1_Msk                   (0x1fUL << PORT0_IOCR0_PC1_Pos)                         /*!< PORT0 IOCR0: PC1 Mask                   */\r
+#define PORT0_IOCR0_PC2_Pos                   19                                                      /*!< PORT0 IOCR0: PC2 Position               */\r
+#define PORT0_IOCR0_PC2_Msk                   (0x1fUL << PORT0_IOCR0_PC2_Pos)                         /*!< PORT0 IOCR0: PC2 Mask                   */\r
+#define PORT0_IOCR0_PC3_Pos                   27                                                      /*!< PORT0 IOCR0: PC3 Position               */\r
+#define PORT0_IOCR0_PC3_Msk                   (0x1fUL << PORT0_IOCR0_PC3_Pos)                         /*!< PORT0 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_IOCR4  -------------------------------- */\r
+#define PORT0_IOCR4_PC4_Pos                   3                                                       /*!< PORT0 IOCR4: PC4 Position               */\r
+#define PORT0_IOCR4_PC4_Msk                   (0x1fUL << PORT0_IOCR4_PC4_Pos)                         /*!< PORT0 IOCR4: PC4 Mask                   */\r
+#define PORT0_IOCR4_PC5_Pos                   11                                                      /*!< PORT0 IOCR4: PC5 Position               */\r
+#define PORT0_IOCR4_PC5_Msk                   (0x1fUL << PORT0_IOCR4_PC5_Pos)                         /*!< PORT0 IOCR4: PC5 Mask                   */\r
+#define PORT0_IOCR4_PC6_Pos                   19                                                      /*!< PORT0 IOCR4: PC6 Position               */\r
+#define PORT0_IOCR4_PC6_Msk                   (0x1fUL << PORT0_IOCR4_PC6_Pos)                         /*!< PORT0 IOCR4: PC6 Mask                   */\r
+#define PORT0_IOCR4_PC7_Pos                   27                                                      /*!< PORT0 IOCR4: PC7 Position               */\r
+#define PORT0_IOCR4_PC7_Msk                   (0x1fUL << PORT0_IOCR4_PC7_Pos)                         /*!< PORT0 IOCR4: PC7 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_IOCR8  -------------------------------- */\r
+#define PORT0_IOCR8_PC8_Pos                   3                                                       /*!< PORT0 IOCR8: PC8 Position               */\r
+#define PORT0_IOCR8_PC8_Msk                   (0x1fUL << PORT0_IOCR8_PC8_Pos)                         /*!< PORT0 IOCR8: PC8 Mask                   */\r
+#define PORT0_IOCR8_PC9_Pos                   11                                                      /*!< PORT0 IOCR8: PC9 Position               */\r
+#define PORT0_IOCR8_PC9_Msk                   (0x1fUL << PORT0_IOCR8_PC9_Pos)                         /*!< PORT0 IOCR8: PC9 Mask                   */\r
+#define PORT0_IOCR8_PC10_Pos                  19                                                      /*!< PORT0 IOCR8: PC10 Position              */\r
+#define PORT0_IOCR8_PC10_Msk                  (0x1fUL << PORT0_IOCR8_PC10_Pos)                        /*!< PORT0 IOCR8: PC10 Mask                  */\r
+#define PORT0_IOCR8_PC11_Pos                  27                                                      /*!< PORT0 IOCR8: PC11 Position              */\r
+#define PORT0_IOCR8_PC11_Msk                  (0x1fUL << PORT0_IOCR8_PC11_Pos)                        /*!< PORT0 IOCR8: PC11 Mask                  */\r
+\r
+/* ----------------------------------  PORT0_IN  ---------------------------------- */\r
+#define PORT0_IN_P0_Pos                       0                                                       /*!< PORT0 IN: P0 Position                   */\r
+#define PORT0_IN_P0_Msk                       (0x01UL << PORT0_IN_P0_Pos)                             /*!< PORT0 IN: P0 Mask                       */\r
+#define PORT0_IN_P1_Pos                       1                                                       /*!< PORT0 IN: P1 Position                   */\r
+#define PORT0_IN_P1_Msk                       (0x01UL << PORT0_IN_P1_Pos)                             /*!< PORT0 IN: P1 Mask                       */\r
+#define PORT0_IN_P2_Pos                       2                                                       /*!< PORT0 IN: P2 Position                   */\r
+#define PORT0_IN_P2_Msk                       (0x01UL << PORT0_IN_P2_Pos)                             /*!< PORT0 IN: P2 Mask                       */\r
+#define PORT0_IN_P3_Pos                       3                                                       /*!< PORT0 IN: P3 Position                   */\r
+#define PORT0_IN_P3_Msk                       (0x01UL << PORT0_IN_P3_Pos)                             /*!< PORT0 IN: P3 Mask                       */\r
+#define PORT0_IN_P4_Pos                       4                                                       /*!< PORT0 IN: P4 Position                   */\r
+#define PORT0_IN_P4_Msk                       (0x01UL << PORT0_IN_P4_Pos)                             /*!< PORT0 IN: P4 Mask                       */\r
+#define PORT0_IN_P5_Pos                       5                                                       /*!< PORT0 IN: P5 Position                   */\r
+#define PORT0_IN_P5_Msk                       (0x01UL << PORT0_IN_P5_Pos)                             /*!< PORT0 IN: P5 Mask                       */\r
+#define PORT0_IN_P6_Pos                       6                                                       /*!< PORT0 IN: P6 Position                   */\r
+#define PORT0_IN_P6_Msk                       (0x01UL << PORT0_IN_P6_Pos)                             /*!< PORT0 IN: P6 Mask                       */\r
+#define PORT0_IN_P7_Pos                       7                                                       /*!< PORT0 IN: P7 Position                   */\r
+#define PORT0_IN_P7_Msk                       (0x01UL << PORT0_IN_P7_Pos)                             /*!< PORT0 IN: P7 Mask                       */\r
+#define PORT0_IN_P8_Pos                       8                                                       /*!< PORT0 IN: P8 Position                   */\r
+#define PORT0_IN_P8_Msk                       (0x01UL << PORT0_IN_P8_Pos)                             /*!< PORT0 IN: P8 Mask                       */\r
+#define PORT0_IN_P9_Pos                       9                                                       /*!< PORT0 IN: P9 Position                   */\r
+#define PORT0_IN_P9_Msk                       (0x01UL << PORT0_IN_P9_Pos)                             /*!< PORT0 IN: P9 Mask                       */\r
+#define PORT0_IN_P10_Pos                      10                                                      /*!< PORT0 IN: P10 Position                  */\r
+#define PORT0_IN_P10_Msk                      (0x01UL << PORT0_IN_P10_Pos)                            /*!< PORT0 IN: P10 Mask                      */\r
+#define PORT0_IN_P11_Pos                      11                                                      /*!< PORT0 IN: P11 Position                  */\r
+#define PORT0_IN_P11_Msk                      (0x01UL << PORT0_IN_P11_Pos)                            /*!< PORT0 IN: P11 Mask                      */\r
+#define PORT0_IN_P12_Pos                      12                                                      /*!< PORT0 IN: P12 Position                  */\r
+#define PORT0_IN_P12_Msk                      (0x01UL << PORT0_IN_P12_Pos)                            /*!< PORT0 IN: P12 Mask                      */\r
+#define PORT0_IN_P13_Pos                      13                                                      /*!< PORT0 IN: P13 Position                  */\r
+#define PORT0_IN_P13_Msk                      (0x01UL << PORT0_IN_P13_Pos)                            /*!< PORT0 IN: P13 Mask                      */\r
+#define PORT0_IN_P14_Pos                      14                                                      /*!< PORT0 IN: P14 Position                  */\r
+#define PORT0_IN_P14_Msk                      (0x01UL << PORT0_IN_P14_Pos)                            /*!< PORT0 IN: P14 Mask                      */\r
+#define PORT0_IN_P15_Pos                      15                                                      /*!< PORT0 IN: P15 Position                  */\r
+#define PORT0_IN_P15_Msk                      (0x01UL << PORT0_IN_P15_Pos)                            /*!< PORT0 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT0_PDR0  --------------------------------- */\r
+#define PORT0_PDR0_PD0_Pos                    0                                                       /*!< PORT0 PDR0: PD0 Position                */\r
+#define PORT0_PDR0_PD0_Msk                    (0x07UL << PORT0_PDR0_PD0_Pos)                          /*!< PORT0 PDR0: PD0 Mask                    */\r
+#define PORT0_PDR0_PD1_Pos                    4                                                       /*!< PORT0 PDR0: PD1 Position                */\r
+#define PORT0_PDR0_PD1_Msk                    (0x07UL << PORT0_PDR0_PD1_Pos)                          /*!< PORT0 PDR0: PD1 Mask                    */\r
+#define PORT0_PDR0_PD2_Pos                    8                                                       /*!< PORT0 PDR0: PD2 Position                */\r
+#define PORT0_PDR0_PD2_Msk                    (0x07UL << PORT0_PDR0_PD2_Pos)                          /*!< PORT0 PDR0: PD2 Mask                    */\r
+#define PORT0_PDR0_PD3_Pos                    12                                                      /*!< PORT0 PDR0: PD3 Position                */\r
+#define PORT0_PDR0_PD3_Msk                    (0x07UL << PORT0_PDR0_PD3_Pos)                          /*!< PORT0 PDR0: PD3 Mask                    */\r
+#define PORT0_PDR0_PD4_Pos                    16                                                      /*!< PORT0 PDR0: PD4 Position                */\r
+#define PORT0_PDR0_PD4_Msk                    (0x07UL << PORT0_PDR0_PD4_Pos)                          /*!< PORT0 PDR0: PD4 Mask                    */\r
+#define PORT0_PDR0_PD5_Pos                    20                                                      /*!< PORT0 PDR0: PD5 Position                */\r
+#define PORT0_PDR0_PD5_Msk                    (0x07UL << PORT0_PDR0_PD5_Pos)                          /*!< PORT0 PDR0: PD5 Mask                    */\r
+#define PORT0_PDR0_PD6_Pos                    24                                                      /*!< PORT0 PDR0: PD6 Position                */\r
+#define PORT0_PDR0_PD6_Msk                    (0x07UL << PORT0_PDR0_PD6_Pos)                          /*!< PORT0 PDR0: PD6 Mask                    */\r
+#define PORT0_PDR0_PD7_Pos                    28                                                      /*!< PORT0 PDR0: PD7 Position                */\r
+#define PORT0_PDR0_PD7_Msk                    (0x07UL << PORT0_PDR0_PD7_Pos)                          /*!< PORT0 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT0_PDR1  --------------------------------- */\r
+#define PORT0_PDR1_PD8_Pos                    0                                                       /*!< PORT0 PDR1: PD8 Position                */\r
+#define PORT0_PDR1_PD8_Msk                    (0x07UL << PORT0_PDR1_PD8_Pos)                          /*!< PORT0 PDR1: PD8 Mask                    */\r
+#define PORT0_PDR1_PD9_Pos                    4                                                       /*!< PORT0 PDR1: PD9 Position                */\r
+#define PORT0_PDR1_PD9_Msk                    (0x07UL << PORT0_PDR1_PD9_Pos)                          /*!< PORT0 PDR1: PD9 Mask                    */\r
+#define PORT0_PDR1_PD10_Pos                   8                                                       /*!< PORT0 PDR1: PD10 Position               */\r
+#define PORT0_PDR1_PD10_Msk                   (0x07UL << PORT0_PDR1_PD10_Pos)                         /*!< PORT0 PDR1: PD10 Mask                   */\r
+#define PORT0_PDR1_PD11_Pos                   12                                                      /*!< PORT0 PDR1: PD11 Position               */\r
+#define PORT0_PDR1_PD11_Msk                   (0x07UL << PORT0_PDR1_PD11_Pos)                         /*!< PORT0 PDR1: PD11 Mask                   */\r
+#define PORT0_PDR1_PD12_Pos                   16                                                      /*!< PORT0 PDR1: PD12 Position               */\r
+#define PORT0_PDR1_PD12_Msk                   (0x07UL << PORT0_PDR1_PD12_Pos)                         /*!< PORT0 PDR1: PD12 Mask                   */\r
+#define PORT0_PDR1_PD13_Pos                   20                                                      /*!< PORT0 PDR1: PD13 Position               */\r
+#define PORT0_PDR1_PD13_Msk                   (0x07UL << PORT0_PDR1_PD13_Pos)                         /*!< PORT0 PDR1: PD13 Mask                   */\r
+#define PORT0_PDR1_PD14_Pos                   24                                                      /*!< PORT0 PDR1: PD14 Position               */\r
+#define PORT0_PDR1_PD14_Msk                   (0x07UL << PORT0_PDR1_PD14_Pos)                         /*!< PORT0 PDR1: PD14 Mask                   */\r
+#define PORT0_PDR1_PD15_Pos                   28                                                      /*!< PORT0 PDR1: PD15 Position               */\r
+#define PORT0_PDR1_PD15_Msk                   (0x07UL << PORT0_PDR1_PD15_Pos)                         /*!< PORT0 PDR1: PD15 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_PDISC  -------------------------------- */\r
+#define PORT0_PDISC_PDIS0_Pos                 0                                                       /*!< PORT0 PDISC: PDIS0 Position             */\r
+#define PORT0_PDISC_PDIS0_Msk                 (0x01UL << PORT0_PDISC_PDIS0_Pos)                       /*!< PORT0 PDISC: PDIS0 Mask                 */\r
+#define PORT0_PDISC_PDIS1_Pos                 1                                                       /*!< PORT0 PDISC: PDIS1 Position             */\r
+#define PORT0_PDISC_PDIS1_Msk                 (0x01UL << PORT0_PDISC_PDIS1_Pos)                       /*!< PORT0 PDISC: PDIS1 Mask                 */\r
+#define PORT0_PDISC_PDIS2_Pos                 2                                                       /*!< PORT0 PDISC: PDIS2 Position             */\r
+#define PORT0_PDISC_PDIS2_Msk                 (0x01UL << PORT0_PDISC_PDIS2_Pos)                       /*!< PORT0 PDISC: PDIS2 Mask                 */\r
+#define PORT0_PDISC_PDIS3_Pos                 3                                                       /*!< PORT0 PDISC: PDIS3 Position             */\r
+#define PORT0_PDISC_PDIS3_Msk                 (0x01UL << PORT0_PDISC_PDIS3_Pos)                       /*!< PORT0 PDISC: PDIS3 Mask                 */\r
+#define PORT0_PDISC_PDIS4_Pos                 4                                                       /*!< PORT0 PDISC: PDIS4 Position             */\r
+#define PORT0_PDISC_PDIS4_Msk                 (0x01UL << PORT0_PDISC_PDIS4_Pos)                       /*!< PORT0 PDISC: PDIS4 Mask                 */\r
+#define PORT0_PDISC_PDIS5_Pos                 5                                                       /*!< PORT0 PDISC: PDIS5 Position             */\r
+#define PORT0_PDISC_PDIS5_Msk                 (0x01UL << PORT0_PDISC_PDIS5_Pos)                       /*!< PORT0 PDISC: PDIS5 Mask                 */\r
+#define PORT0_PDISC_PDIS6_Pos                 6                                                       /*!< PORT0 PDISC: PDIS6 Position             */\r
+#define PORT0_PDISC_PDIS6_Msk                 (0x01UL << PORT0_PDISC_PDIS6_Pos)                       /*!< PORT0 PDISC: PDIS6 Mask                 */\r
+#define PORT0_PDISC_PDIS7_Pos                 7                                                       /*!< PORT0 PDISC: PDIS7 Position             */\r
+#define PORT0_PDISC_PDIS7_Msk                 (0x01UL << PORT0_PDISC_PDIS7_Pos)                       /*!< PORT0 PDISC: PDIS7 Mask                 */\r
+#define PORT0_PDISC_PDIS8_Pos                 8                                                       /*!< PORT0 PDISC: PDIS8 Position             */\r
+#define PORT0_PDISC_PDIS8_Msk                 (0x01UL << PORT0_PDISC_PDIS8_Pos)                       /*!< PORT0 PDISC: PDIS8 Mask                 */\r
+#define PORT0_PDISC_PDIS9_Pos                 9                                                       /*!< PORT0 PDISC: PDIS9 Position             */\r
+#define PORT0_PDISC_PDIS9_Msk                 (0x01UL << PORT0_PDISC_PDIS9_Pos)                       /*!< PORT0 PDISC: PDIS9 Mask                 */\r
+#define PORT0_PDISC_PDIS10_Pos                10                                                      /*!< PORT0 PDISC: PDIS10 Position            */\r
+#define PORT0_PDISC_PDIS10_Msk                (0x01UL << PORT0_PDISC_PDIS10_Pos)                      /*!< PORT0 PDISC: PDIS10 Mask                */\r
+#define PORT0_PDISC_PDIS11_Pos                11                                                      /*!< PORT0 PDISC: PDIS11 Position            */\r
+#define PORT0_PDISC_PDIS11_Msk                (0x01UL << PORT0_PDISC_PDIS11_Pos)                      /*!< PORT0 PDISC: PDIS11 Mask                */\r
+#define PORT0_PDISC_PDIS12_Pos                12                                                      /*!< PORT0 PDISC: PDIS12 Position            */\r
+#define PORT0_PDISC_PDIS12_Msk                (0x01UL << PORT0_PDISC_PDIS12_Pos)                      /*!< PORT0 PDISC: PDIS12 Mask                */\r
+#define PORT0_PDISC_PDIS13_Pos                13                                                      /*!< PORT0 PDISC: PDIS13 Position            */\r
+#define PORT0_PDISC_PDIS13_Msk                (0x01UL << PORT0_PDISC_PDIS13_Pos)                      /*!< PORT0 PDISC: PDIS13 Mask                */\r
+#define PORT0_PDISC_PDIS14_Pos                14                                                      /*!< PORT0 PDISC: PDIS14 Position            */\r
+#define PORT0_PDISC_PDIS14_Msk                (0x01UL << PORT0_PDISC_PDIS14_Pos)                      /*!< PORT0 PDISC: PDIS14 Mask                */\r
+#define PORT0_PDISC_PDIS15_Pos                15                                                      /*!< PORT0 PDISC: PDIS15 Position            */\r
+#define PORT0_PDISC_PDIS15_Msk                (0x01UL << PORT0_PDISC_PDIS15_Pos)                      /*!< PORT0 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT0_PPS  --------------------------------- */\r
+#define PORT0_PPS_PPS0_Pos                    0                                                       /*!< PORT0 PPS: PPS0 Position                */\r
+#define PORT0_PPS_PPS0_Msk                    (0x01UL << PORT0_PPS_PPS0_Pos)                          /*!< PORT0 PPS: PPS0 Mask                    */\r
+#define PORT0_PPS_PPS1_Pos                    1                                                       /*!< PORT0 PPS: PPS1 Position                */\r
+#define PORT0_PPS_PPS1_Msk                    (0x01UL << PORT0_PPS_PPS1_Pos)                          /*!< PORT0 PPS: PPS1 Mask                    */\r
+#define PORT0_PPS_PPS2_Pos                    2                                                       /*!< PORT0 PPS: PPS2 Position                */\r
+#define PORT0_PPS_PPS2_Msk                    (0x01UL << PORT0_PPS_PPS2_Pos)                          /*!< PORT0 PPS: PPS2 Mask                    */\r
+#define PORT0_PPS_PPS3_Pos                    3                                                       /*!< PORT0 PPS: PPS3 Position                */\r
+#define PORT0_PPS_PPS3_Msk                    (0x01UL << PORT0_PPS_PPS3_Pos)                          /*!< PORT0 PPS: PPS3 Mask                    */\r
+#define PORT0_PPS_PPS4_Pos                    4                                                       /*!< PORT0 PPS: PPS4 Position                */\r
+#define PORT0_PPS_PPS4_Msk                    (0x01UL << PORT0_PPS_PPS4_Pos)                          /*!< PORT0 PPS: PPS4 Mask                    */\r
+#define PORT0_PPS_PPS5_Pos                    5                                                       /*!< PORT0 PPS: PPS5 Position                */\r
+#define PORT0_PPS_PPS5_Msk                    (0x01UL << PORT0_PPS_PPS5_Pos)                          /*!< PORT0 PPS: PPS5 Mask                    */\r
+#define PORT0_PPS_PPS6_Pos                    6                                                       /*!< PORT0 PPS: PPS6 Position                */\r
+#define PORT0_PPS_PPS6_Msk                    (0x01UL << PORT0_PPS_PPS6_Pos)                          /*!< PORT0 PPS: PPS6 Mask                    */\r
+#define PORT0_PPS_PPS7_Pos                    7                                                       /*!< PORT0 PPS: PPS7 Position                */\r
+#define PORT0_PPS_PPS7_Msk                    (0x01UL << PORT0_PPS_PPS7_Pos)                          /*!< PORT0 PPS: PPS7 Mask                    */\r
+#define PORT0_PPS_PPS8_Pos                    8                                                       /*!< PORT0 PPS: PPS8 Position                */\r
+#define PORT0_PPS_PPS8_Msk                    (0x01UL << PORT0_PPS_PPS8_Pos)                          /*!< PORT0 PPS: PPS8 Mask                    */\r
+#define PORT0_PPS_PPS9_Pos                    9                                                       /*!< PORT0 PPS: PPS9 Position                */\r
+#define PORT0_PPS_PPS9_Msk                    (0x01UL << PORT0_PPS_PPS9_Pos)                          /*!< PORT0 PPS: PPS9 Mask                    */\r
+#define PORT0_PPS_PPS10_Pos                   10                                                      /*!< PORT0 PPS: PPS10 Position               */\r
+#define PORT0_PPS_PPS10_Msk                   (0x01UL << PORT0_PPS_PPS10_Pos)                         /*!< PORT0 PPS: PPS10 Mask                   */\r
+#define PORT0_PPS_PPS11_Pos                   11                                                      /*!< PORT0 PPS: PPS11 Position               */\r
+#define PORT0_PPS_PPS11_Msk                   (0x01UL << PORT0_PPS_PPS11_Pos)                         /*!< PORT0 PPS: PPS11 Mask                   */\r
+#define PORT0_PPS_PPS12_Pos                   12                                                      /*!< PORT0 PPS: PPS12 Position               */\r
+#define PORT0_PPS_PPS12_Msk                   (0x01UL << PORT0_PPS_PPS12_Pos)                         /*!< PORT0 PPS: PPS12 Mask                   */\r
+#define PORT0_PPS_PPS13_Pos                   13                                                      /*!< PORT0 PPS: PPS13 Position               */\r
+#define PORT0_PPS_PPS13_Msk                   (0x01UL << PORT0_PPS_PPS13_Pos)                         /*!< PORT0 PPS: PPS13 Mask                   */\r
+#define PORT0_PPS_PPS14_Pos                   14                                                      /*!< PORT0 PPS: PPS14 Position               */\r
+#define PORT0_PPS_PPS14_Msk                   (0x01UL << PORT0_PPS_PPS14_Pos)                         /*!< PORT0 PPS: PPS14 Mask                   */\r
+#define PORT0_PPS_PPS15_Pos                   15                                                      /*!< PORT0 PPS: PPS15 Position               */\r
+#define PORT0_PPS_PPS15_Msk                   (0x01UL << PORT0_PPS_PPS15_Pos)                         /*!< PORT0 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_HWSEL  -------------------------------- */\r
+#define PORT0_HWSEL_HW0_Pos                   0                                                       /*!< PORT0 HWSEL: HW0 Position               */\r
+#define PORT0_HWSEL_HW0_Msk                   (0x03UL << PORT0_HWSEL_HW0_Pos)                         /*!< PORT0 HWSEL: HW0 Mask                   */\r
+#define PORT0_HWSEL_HW1_Pos                   2                                                       /*!< PORT0 HWSEL: HW1 Position               */\r
+#define PORT0_HWSEL_HW1_Msk                   (0x03UL << PORT0_HWSEL_HW1_Pos)                         /*!< PORT0 HWSEL: HW1 Mask                   */\r
+#define PORT0_HWSEL_HW2_Pos                   4                                                       /*!< PORT0 HWSEL: HW2 Position               */\r
+#define PORT0_HWSEL_HW2_Msk                   (0x03UL << PORT0_HWSEL_HW2_Pos)                         /*!< PORT0 HWSEL: HW2 Mask                   */\r
+#define PORT0_HWSEL_HW3_Pos                   6                                                       /*!< PORT0 HWSEL: HW3 Position               */\r
+#define PORT0_HWSEL_HW3_Msk                   (0x03UL << PORT0_HWSEL_HW3_Pos)                         /*!< PORT0 HWSEL: HW3 Mask                   */\r
+#define PORT0_HWSEL_HW4_Pos                   8                                                       /*!< PORT0 HWSEL: HW4 Position               */\r
+#define PORT0_HWSEL_HW4_Msk                   (0x03UL << PORT0_HWSEL_HW4_Pos)                         /*!< PORT0 HWSEL: HW4 Mask                   */\r
+#define PORT0_HWSEL_HW5_Pos                   10                                                      /*!< PORT0 HWSEL: HW5 Position               */\r
+#define PORT0_HWSEL_HW5_Msk                   (0x03UL << PORT0_HWSEL_HW5_Pos)                         /*!< PORT0 HWSEL: HW5 Mask                   */\r
+#define PORT0_HWSEL_HW6_Pos                   12                                                      /*!< PORT0 HWSEL: HW6 Position               */\r
+#define PORT0_HWSEL_HW6_Msk                   (0x03UL << PORT0_HWSEL_HW6_Pos)                         /*!< PORT0 HWSEL: HW6 Mask                   */\r
+#define PORT0_HWSEL_HW7_Pos                   14                                                      /*!< PORT0 HWSEL: HW7 Position               */\r
+#define PORT0_HWSEL_HW7_Msk                   (0x03UL << PORT0_HWSEL_HW7_Pos)                         /*!< PORT0 HWSEL: HW7 Mask                   */\r
+#define PORT0_HWSEL_HW8_Pos                   16                                                      /*!< PORT0 HWSEL: HW8 Position               */\r
+#define PORT0_HWSEL_HW8_Msk                   (0x03UL << PORT0_HWSEL_HW8_Pos)                         /*!< PORT0 HWSEL: HW8 Mask                   */\r
+#define PORT0_HWSEL_HW9_Pos                   18                                                      /*!< PORT0 HWSEL: HW9 Position               */\r
+#define PORT0_HWSEL_HW9_Msk                   (0x03UL << PORT0_HWSEL_HW9_Pos)                         /*!< PORT0 HWSEL: HW9 Mask                   */\r
+#define PORT0_HWSEL_HW10_Pos                  20                                                      /*!< PORT0 HWSEL: HW10 Position              */\r
+#define PORT0_HWSEL_HW10_Msk                  (0x03UL << PORT0_HWSEL_HW10_Pos)                        /*!< PORT0 HWSEL: HW10 Mask                  */\r
+#define PORT0_HWSEL_HW11_Pos                  22                                                      /*!< PORT0 HWSEL: HW11 Position              */\r
+#define PORT0_HWSEL_HW11_Msk                  (0x03UL << PORT0_HWSEL_HW11_Pos)                        /*!< PORT0 HWSEL: HW11 Mask                  */\r
+#define PORT0_HWSEL_HW12_Pos                  24                                                      /*!< PORT0 HWSEL: HW12 Position              */\r
+#define PORT0_HWSEL_HW12_Msk                  (0x03UL << PORT0_HWSEL_HW12_Pos)                        /*!< PORT0 HWSEL: HW12 Mask                  */\r
+#define PORT0_HWSEL_HW13_Pos                  26                                                      /*!< PORT0 HWSEL: HW13 Position              */\r
+#define PORT0_HWSEL_HW13_Msk                  (0x03UL << PORT0_HWSEL_HW13_Pos)                        /*!< PORT0 HWSEL: HW13 Mask                  */\r
+#define PORT0_HWSEL_HW14_Pos                  28                                                      /*!< PORT0 HWSEL: HW14 Position              */\r
+#define PORT0_HWSEL_HW14_Msk                  (0x03UL << PORT0_HWSEL_HW14_Pos)                        /*!< PORT0 HWSEL: HW14 Mask                  */\r
+#define PORT0_HWSEL_HW15_Pos                  30                                                      /*!< PORT0 HWSEL: HW15 Position              */\r
+#define PORT0_HWSEL_HW15_Msk                  (0x03UL << PORT0_HWSEL_HW15_Pos)                        /*!< PORT0 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT1' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT1_OUT  --------------------------------- */\r
+#define PORT1_OUT_P0_Pos                      0                                                       /*!< PORT1 OUT: P0 Position                  */\r
+#define PORT1_OUT_P0_Msk                      (0x01UL << PORT1_OUT_P0_Pos)                            /*!< PORT1 OUT: P0 Mask                      */\r
+#define PORT1_OUT_P1_Pos                      1                                                       /*!< PORT1 OUT: P1 Position                  */\r
+#define PORT1_OUT_P1_Msk                      (0x01UL << PORT1_OUT_P1_Pos)                            /*!< PORT1 OUT: P1 Mask                      */\r
+#define PORT1_OUT_P2_Pos                      2                                                       /*!< PORT1 OUT: P2 Position                  */\r
+#define PORT1_OUT_P2_Msk                      (0x01UL << PORT1_OUT_P2_Pos)                            /*!< PORT1 OUT: P2 Mask                      */\r
+#define PORT1_OUT_P3_Pos                      3                                                       /*!< PORT1 OUT: P3 Position                  */\r
+#define PORT1_OUT_P3_Msk                      (0x01UL << PORT1_OUT_P3_Pos)                            /*!< PORT1 OUT: P3 Mask                      */\r
+#define PORT1_OUT_P4_Pos                      4                                                       /*!< PORT1 OUT: P4 Position                  */\r
+#define PORT1_OUT_P4_Msk                      (0x01UL << PORT1_OUT_P4_Pos)                            /*!< PORT1 OUT: P4 Mask                      */\r
+#define PORT1_OUT_P5_Pos                      5                                                       /*!< PORT1 OUT: P5 Position                  */\r
+#define PORT1_OUT_P5_Msk                      (0x01UL << PORT1_OUT_P5_Pos)                            /*!< PORT1 OUT: P5 Mask                      */\r
+#define PORT1_OUT_P6_Pos                      6                                                       /*!< PORT1 OUT: P6 Position                  */\r
+#define PORT1_OUT_P6_Msk                      (0x01UL << PORT1_OUT_P6_Pos)                            /*!< PORT1 OUT: P6 Mask                      */\r
+#define PORT1_OUT_P7_Pos                      7                                                       /*!< PORT1 OUT: P7 Position                  */\r
+#define PORT1_OUT_P7_Msk                      (0x01UL << PORT1_OUT_P7_Pos)                            /*!< PORT1 OUT: P7 Mask                      */\r
+#define PORT1_OUT_P8_Pos                      8                                                       /*!< PORT1 OUT: P8 Position                  */\r
+#define PORT1_OUT_P8_Msk                      (0x01UL << PORT1_OUT_P8_Pos)                            /*!< PORT1 OUT: P8 Mask                      */\r
+#define PORT1_OUT_P9_Pos                      9                                                       /*!< PORT1 OUT: P9 Position                  */\r
+#define PORT1_OUT_P9_Msk                      (0x01UL << PORT1_OUT_P9_Pos)                            /*!< PORT1 OUT: P9 Mask                      */\r
+#define PORT1_OUT_P10_Pos                     10                                                      /*!< PORT1 OUT: P10 Position                 */\r
+#define PORT1_OUT_P10_Msk                     (0x01UL << PORT1_OUT_P10_Pos)                           /*!< PORT1 OUT: P10 Mask                     */\r
+#define PORT1_OUT_P11_Pos                     11                                                      /*!< PORT1 OUT: P11 Position                 */\r
+#define PORT1_OUT_P11_Msk                     (0x01UL << PORT1_OUT_P11_Pos)                           /*!< PORT1 OUT: P11 Mask                     */\r
+#define PORT1_OUT_P12_Pos                     12                                                      /*!< PORT1 OUT: P12 Position                 */\r
+#define PORT1_OUT_P12_Msk                     (0x01UL << PORT1_OUT_P12_Pos)                           /*!< PORT1 OUT: P12 Mask                     */\r
+#define PORT1_OUT_P13_Pos                     13                                                      /*!< PORT1 OUT: P13 Position                 */\r
+#define PORT1_OUT_P13_Msk                     (0x01UL << PORT1_OUT_P13_Pos)                           /*!< PORT1 OUT: P13 Mask                     */\r
+#define PORT1_OUT_P14_Pos                     14                                                      /*!< PORT1 OUT: P14 Position                 */\r
+#define PORT1_OUT_P14_Msk                     (0x01UL << PORT1_OUT_P14_Pos)                           /*!< PORT1 OUT: P14 Mask                     */\r
+#define PORT1_OUT_P15_Pos                     15                                                      /*!< PORT1 OUT: P15 Position                 */\r
+#define PORT1_OUT_P15_Msk                     (0x01UL << PORT1_OUT_P15_Pos)                           /*!< PORT1 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT1_OMR  --------------------------------- */\r
+#define PORT1_OMR_PS0_Pos                     0                                                       /*!< PORT1 OMR: PS0 Position                 */\r
+#define PORT1_OMR_PS0_Msk                     (0x01UL << PORT1_OMR_PS0_Pos)                           /*!< PORT1 OMR: PS0 Mask                     */\r
+#define PORT1_OMR_PS1_Pos                     1                                                       /*!< PORT1 OMR: PS1 Position                 */\r
+#define PORT1_OMR_PS1_Msk                     (0x01UL << PORT1_OMR_PS1_Pos)                           /*!< PORT1 OMR: PS1 Mask                     */\r
+#define PORT1_OMR_PS2_Pos                     2                                                       /*!< PORT1 OMR: PS2 Position                 */\r
+#define PORT1_OMR_PS2_Msk                     (0x01UL << PORT1_OMR_PS2_Pos)                           /*!< PORT1 OMR: PS2 Mask                     */\r
+#define PORT1_OMR_PS3_Pos                     3                                                       /*!< PORT1 OMR: PS3 Position                 */\r
+#define PORT1_OMR_PS3_Msk                     (0x01UL << PORT1_OMR_PS3_Pos)                           /*!< PORT1 OMR: PS3 Mask                     */\r
+#define PORT1_OMR_PS4_Pos                     4                                                       /*!< PORT1 OMR: PS4 Position                 */\r
+#define PORT1_OMR_PS4_Msk                     (0x01UL << PORT1_OMR_PS4_Pos)                           /*!< PORT1 OMR: PS4 Mask                     */\r
+#define PORT1_OMR_PS5_Pos                     5                                                       /*!< PORT1 OMR: PS5 Position                 */\r
+#define PORT1_OMR_PS5_Msk                     (0x01UL << PORT1_OMR_PS5_Pos)                           /*!< PORT1 OMR: PS5 Mask                     */\r
+#define PORT1_OMR_PS6_Pos                     6                                                       /*!< PORT1 OMR: PS6 Position                 */\r
+#define PORT1_OMR_PS6_Msk                     (0x01UL << PORT1_OMR_PS6_Pos)                           /*!< PORT1 OMR: PS6 Mask                     */\r
+#define PORT1_OMR_PS7_Pos                     7                                                       /*!< PORT1 OMR: PS7 Position                 */\r
+#define PORT1_OMR_PS7_Msk                     (0x01UL << PORT1_OMR_PS7_Pos)                           /*!< PORT1 OMR: PS7 Mask                     */\r
+#define PORT1_OMR_PS8_Pos                     8                                                       /*!< PORT1 OMR: PS8 Position                 */\r
+#define PORT1_OMR_PS8_Msk                     (0x01UL << PORT1_OMR_PS8_Pos)                           /*!< PORT1 OMR: PS8 Mask                     */\r
+#define PORT1_OMR_PS9_Pos                     9                                                       /*!< PORT1 OMR: PS9 Position                 */\r
+#define PORT1_OMR_PS9_Msk                     (0x01UL << PORT1_OMR_PS9_Pos)                           /*!< PORT1 OMR: PS9 Mask                     */\r
+#define PORT1_OMR_PS10_Pos                    10                                                      /*!< PORT1 OMR: PS10 Position                */\r
+#define PORT1_OMR_PS10_Msk                    (0x01UL << PORT1_OMR_PS10_Pos)                          /*!< PORT1 OMR: PS10 Mask                    */\r
+#define PORT1_OMR_PS11_Pos                    11                                                      /*!< PORT1 OMR: PS11 Position                */\r
+#define PORT1_OMR_PS11_Msk                    (0x01UL << PORT1_OMR_PS11_Pos)                          /*!< PORT1 OMR: PS11 Mask                    */\r
+#define PORT1_OMR_PS12_Pos                    12                                                      /*!< PORT1 OMR: PS12 Position                */\r
+#define PORT1_OMR_PS12_Msk                    (0x01UL << PORT1_OMR_PS12_Pos)                          /*!< PORT1 OMR: PS12 Mask                    */\r
+#define PORT1_OMR_PS13_Pos                    13                                                      /*!< PORT1 OMR: PS13 Position                */\r
+#define PORT1_OMR_PS13_Msk                    (0x01UL << PORT1_OMR_PS13_Pos)                          /*!< PORT1 OMR: PS13 Mask                    */\r
+#define PORT1_OMR_PS14_Pos                    14                                                      /*!< PORT1 OMR: PS14 Position                */\r
+#define PORT1_OMR_PS14_Msk                    (0x01UL << PORT1_OMR_PS14_Pos)                          /*!< PORT1 OMR: PS14 Mask                    */\r
+#define PORT1_OMR_PS15_Pos                    15                                                      /*!< PORT1 OMR: PS15 Position                */\r
+#define PORT1_OMR_PS15_Msk                    (0x01UL << PORT1_OMR_PS15_Pos)                          /*!< PORT1 OMR: PS15 Mask                    */\r
+#define PORT1_OMR_PR0_Pos                     16                                                      /*!< PORT1 OMR: PR0 Position                 */\r
+#define PORT1_OMR_PR0_Msk                     (0x01UL << PORT1_OMR_PR0_Pos)                           /*!< PORT1 OMR: PR0 Mask                     */\r
+#define PORT1_OMR_PR1_Pos                     17                                                      /*!< PORT1 OMR: PR1 Position                 */\r
+#define PORT1_OMR_PR1_Msk                     (0x01UL << PORT1_OMR_PR1_Pos)                           /*!< PORT1 OMR: PR1 Mask                     */\r
+#define PORT1_OMR_PR2_Pos                     18                                                      /*!< PORT1 OMR: PR2 Position                 */\r
+#define PORT1_OMR_PR2_Msk                     (0x01UL << PORT1_OMR_PR2_Pos)                           /*!< PORT1 OMR: PR2 Mask                     */\r
+#define PORT1_OMR_PR3_Pos                     19                                                      /*!< PORT1 OMR: PR3 Position                 */\r
+#define PORT1_OMR_PR3_Msk                     (0x01UL << PORT1_OMR_PR3_Pos)                           /*!< PORT1 OMR: PR3 Mask                     */\r
+#define PORT1_OMR_PR4_Pos                     20                                                      /*!< PORT1 OMR: PR4 Position                 */\r
+#define PORT1_OMR_PR4_Msk                     (0x01UL << PORT1_OMR_PR4_Pos)                           /*!< PORT1 OMR: PR4 Mask                     */\r
+#define PORT1_OMR_PR5_Pos                     21                                                      /*!< PORT1 OMR: PR5 Position                 */\r
+#define PORT1_OMR_PR5_Msk                     (0x01UL << PORT1_OMR_PR5_Pos)                           /*!< PORT1 OMR: PR5 Mask                     */\r
+#define PORT1_OMR_PR6_Pos                     22                                                      /*!< PORT1 OMR: PR6 Position                 */\r
+#define PORT1_OMR_PR6_Msk                     (0x01UL << PORT1_OMR_PR6_Pos)                           /*!< PORT1 OMR: PR6 Mask                     */\r
+#define PORT1_OMR_PR7_Pos                     23                                                      /*!< PORT1 OMR: PR7 Position                 */\r
+#define PORT1_OMR_PR7_Msk                     (0x01UL << PORT1_OMR_PR7_Pos)                           /*!< PORT1 OMR: PR7 Mask                     */\r
+#define PORT1_OMR_PR8_Pos                     24                                                      /*!< PORT1 OMR: PR8 Position                 */\r
+#define PORT1_OMR_PR8_Msk                     (0x01UL << PORT1_OMR_PR8_Pos)                           /*!< PORT1 OMR: PR8 Mask                     */\r
+#define PORT1_OMR_PR9_Pos                     25                                                      /*!< PORT1 OMR: PR9 Position                 */\r
+#define PORT1_OMR_PR9_Msk                     (0x01UL << PORT1_OMR_PR9_Pos)                           /*!< PORT1 OMR: PR9 Mask                     */\r
+#define PORT1_OMR_PR10_Pos                    26                                                      /*!< PORT1 OMR: PR10 Position                */\r
+#define PORT1_OMR_PR10_Msk                    (0x01UL << PORT1_OMR_PR10_Pos)                          /*!< PORT1 OMR: PR10 Mask                    */\r
+#define PORT1_OMR_PR11_Pos                    27                                                      /*!< PORT1 OMR: PR11 Position                */\r
+#define PORT1_OMR_PR11_Msk                    (0x01UL << PORT1_OMR_PR11_Pos)                          /*!< PORT1 OMR: PR11 Mask                    */\r
+#define PORT1_OMR_PR12_Pos                    28                                                      /*!< PORT1 OMR: PR12 Position                */\r
+#define PORT1_OMR_PR12_Msk                    (0x01UL << PORT1_OMR_PR12_Pos)                          /*!< PORT1 OMR: PR12 Mask                    */\r
+#define PORT1_OMR_PR13_Pos                    29                                                      /*!< PORT1 OMR: PR13 Position                */\r
+#define PORT1_OMR_PR13_Msk                    (0x01UL << PORT1_OMR_PR13_Pos)                          /*!< PORT1 OMR: PR13 Mask                    */\r
+#define PORT1_OMR_PR14_Pos                    30                                                      /*!< PORT1 OMR: PR14 Position                */\r
+#define PORT1_OMR_PR14_Msk                    (0x01UL << PORT1_OMR_PR14_Pos)                          /*!< PORT1 OMR: PR14 Mask                    */\r
+#define PORT1_OMR_PR15_Pos                    31                                                      /*!< PORT1 OMR: PR15 Position                */\r
+#define PORT1_OMR_PR15_Msk                    (0x01UL << PORT1_OMR_PR15_Pos)                          /*!< PORT1 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT1_IOCR0  -------------------------------- */\r
+#define PORT1_IOCR0_PC0_Pos                   3                                                       /*!< PORT1 IOCR0: PC0 Position               */\r
+#define PORT1_IOCR0_PC0_Msk                   (0x1fUL << PORT1_IOCR0_PC0_Pos)                         /*!< PORT1 IOCR0: PC0 Mask                   */\r
+#define PORT1_IOCR0_PC1_Pos                   11                                                      /*!< PORT1 IOCR0: PC1 Position               */\r
+#define PORT1_IOCR0_PC1_Msk                   (0x1fUL << PORT1_IOCR0_PC1_Pos)                         /*!< PORT1 IOCR0: PC1 Mask                   */\r
+#define PORT1_IOCR0_PC2_Pos                   19                                                      /*!< PORT1 IOCR0: PC2 Position               */\r
+#define PORT1_IOCR0_PC2_Msk                   (0x1fUL << PORT1_IOCR0_PC2_Pos)                         /*!< PORT1 IOCR0: PC2 Mask                   */\r
+#define PORT1_IOCR0_PC3_Pos                   27                                                      /*!< PORT1 IOCR0: PC3 Position               */\r
+#define PORT1_IOCR0_PC3_Msk                   (0x1fUL << PORT1_IOCR0_PC3_Pos)                         /*!< PORT1 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_IOCR4  -------------------------------- */\r
+#define PORT1_IOCR4_PC4_Pos                   3                                                       /*!< PORT1 IOCR4: PC4 Position               */\r
+#define PORT1_IOCR4_PC4_Msk                   (0x1fUL << PORT1_IOCR4_PC4_Pos)                         /*!< PORT1 IOCR4: PC4 Mask                   */\r
+#define PORT1_IOCR4_PC5_Pos                   11                                                      /*!< PORT1 IOCR4: PC5 Position               */\r
+#define PORT1_IOCR4_PC5_Msk                   (0x1fUL << PORT1_IOCR4_PC5_Pos)                         /*!< PORT1 IOCR4: PC5 Mask                   */\r
+#define PORT1_IOCR4_PC6_Pos                   19                                                      /*!< PORT1 IOCR4: PC6 Position               */\r
+#define PORT1_IOCR4_PC6_Msk                   (0x1fUL << PORT1_IOCR4_PC6_Pos)                         /*!< PORT1 IOCR4: PC6 Mask                   */\r
+#define PORT1_IOCR4_PC7_Pos                   27                                                      /*!< PORT1 IOCR4: PC7 Position               */\r
+#define PORT1_IOCR4_PC7_Msk                   (0x1fUL << PORT1_IOCR4_PC7_Pos)                         /*!< PORT1 IOCR4: PC7 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_IOCR8  -------------------------------- */\r
+#define PORT1_IOCR8_PC8_Pos                   3                                                       /*!< PORT1 IOCR8: PC8 Position               */\r
+#define PORT1_IOCR8_PC8_Msk                   (0x1fUL << PORT1_IOCR8_PC8_Pos)                         /*!< PORT1 IOCR8: PC8 Mask                   */\r
+#define PORT1_IOCR8_PC9_Pos                   11                                                      /*!< PORT1 IOCR8: PC9 Position               */\r
+#define PORT1_IOCR8_PC9_Msk                   (0x1fUL << PORT1_IOCR8_PC9_Pos)                         /*!< PORT1 IOCR8: PC9 Mask                   */\r
+#define PORT1_IOCR8_PC10_Pos                  19                                                      /*!< PORT1 IOCR8: PC10 Position              */\r
+#define PORT1_IOCR8_PC10_Msk                  (0x1fUL << PORT1_IOCR8_PC10_Pos)                        /*!< PORT1 IOCR8: PC10 Mask                  */\r
+#define PORT1_IOCR8_PC11_Pos                  27                                                      /*!< PORT1 IOCR8: PC11 Position              */\r
+#define PORT1_IOCR8_PC11_Msk                  (0x1fUL << PORT1_IOCR8_PC11_Pos)                        /*!< PORT1 IOCR8: PC11 Mask                  */\r
+\r
+/* --------------------------------  PORT1_IOCR12  -------------------------------- */\r
+#define PORT1_IOCR12_PC12_Pos                 3                                                       /*!< PORT1 IOCR12: PC12 Position             */\r
+#define PORT1_IOCR12_PC12_Msk                 (0x1fUL << PORT1_IOCR12_PC12_Pos)                       /*!< PORT1 IOCR12: PC12 Mask                 */\r
+#define PORT1_IOCR12_PC13_Pos                 11                                                      /*!< PORT1 IOCR12: PC13 Position             */\r
+#define PORT1_IOCR12_PC13_Msk                 (0x1fUL << PORT1_IOCR12_PC13_Pos)                       /*!< PORT1 IOCR12: PC13 Mask                 */\r
+#define PORT1_IOCR12_PC14_Pos                 19                                                      /*!< PORT1 IOCR12: PC14 Position             */\r
+#define PORT1_IOCR12_PC14_Msk                 (0x1fUL << PORT1_IOCR12_PC14_Pos)                       /*!< PORT1 IOCR12: PC14 Mask                 */\r
+#define PORT1_IOCR12_PC15_Pos                 27                                                      /*!< PORT1 IOCR12: PC15 Position             */\r
+#define PORT1_IOCR12_PC15_Msk                 (0x1fUL << PORT1_IOCR12_PC15_Pos)                       /*!< PORT1 IOCR12: PC15 Mask                 */\r
+\r
+/* ----------------------------------  PORT1_IN  ---------------------------------- */\r
+#define PORT1_IN_P0_Pos                       0                                                       /*!< PORT1 IN: P0 Position                   */\r
+#define PORT1_IN_P0_Msk                       (0x01UL << PORT1_IN_P0_Pos)                             /*!< PORT1 IN: P0 Mask                       */\r
+#define PORT1_IN_P1_Pos                       1                                                       /*!< PORT1 IN: P1 Position                   */\r
+#define PORT1_IN_P1_Msk                       (0x01UL << PORT1_IN_P1_Pos)                             /*!< PORT1 IN: P1 Mask                       */\r
+#define PORT1_IN_P2_Pos                       2                                                       /*!< PORT1 IN: P2 Position                   */\r
+#define PORT1_IN_P2_Msk                       (0x01UL << PORT1_IN_P2_Pos)                             /*!< PORT1 IN: P2 Mask                       */\r
+#define PORT1_IN_P3_Pos                       3                                                       /*!< PORT1 IN: P3 Position                   */\r
+#define PORT1_IN_P3_Msk                       (0x01UL << PORT1_IN_P3_Pos)                             /*!< PORT1 IN: P3 Mask                       */\r
+#define PORT1_IN_P4_Pos                       4                                                       /*!< PORT1 IN: P4 Position                   */\r
+#define PORT1_IN_P4_Msk                       (0x01UL << PORT1_IN_P4_Pos)                             /*!< PORT1 IN: P4 Mask                       */\r
+#define PORT1_IN_P5_Pos                       5                                                       /*!< PORT1 IN: P5 Position                   */\r
+#define PORT1_IN_P5_Msk                       (0x01UL << PORT1_IN_P5_Pos)                             /*!< PORT1 IN: P5 Mask                       */\r
+#define PORT1_IN_P6_Pos                       6                                                       /*!< PORT1 IN: P6 Position                   */\r
+#define PORT1_IN_P6_Msk                       (0x01UL << PORT1_IN_P6_Pos)                             /*!< PORT1 IN: P6 Mask                       */\r
+#define PORT1_IN_P7_Pos                       7                                                       /*!< PORT1 IN: P7 Position                   */\r
+#define PORT1_IN_P7_Msk                       (0x01UL << PORT1_IN_P7_Pos)                             /*!< PORT1 IN: P7 Mask                       */\r
+#define PORT1_IN_P8_Pos                       8                                                       /*!< PORT1 IN: P8 Position                   */\r
+#define PORT1_IN_P8_Msk                       (0x01UL << PORT1_IN_P8_Pos)                             /*!< PORT1 IN: P8 Mask                       */\r
+#define PORT1_IN_P9_Pos                       9                                                       /*!< PORT1 IN: P9 Position                   */\r
+#define PORT1_IN_P9_Msk                       (0x01UL << PORT1_IN_P9_Pos)                             /*!< PORT1 IN: P9 Mask                       */\r
+#define PORT1_IN_P10_Pos                      10                                                      /*!< PORT1 IN: P10 Position                  */\r
+#define PORT1_IN_P10_Msk                      (0x01UL << PORT1_IN_P10_Pos)                            /*!< PORT1 IN: P10 Mask                      */\r
+#define PORT1_IN_P11_Pos                      11                                                      /*!< PORT1 IN: P11 Position                  */\r
+#define PORT1_IN_P11_Msk                      (0x01UL << PORT1_IN_P11_Pos)                            /*!< PORT1 IN: P11 Mask                      */\r
+#define PORT1_IN_P12_Pos                      12                                                      /*!< PORT1 IN: P12 Position                  */\r
+#define PORT1_IN_P12_Msk                      (0x01UL << PORT1_IN_P12_Pos)                            /*!< PORT1 IN: P12 Mask                      */\r
+#define PORT1_IN_P13_Pos                      13                                                      /*!< PORT1 IN: P13 Position                  */\r
+#define PORT1_IN_P13_Msk                      (0x01UL << PORT1_IN_P13_Pos)                            /*!< PORT1 IN: P13 Mask                      */\r
+#define PORT1_IN_P14_Pos                      14                                                      /*!< PORT1 IN: P14 Position                  */\r
+#define PORT1_IN_P14_Msk                      (0x01UL << PORT1_IN_P14_Pos)                            /*!< PORT1 IN: P14 Mask                      */\r
+#define PORT1_IN_P15_Pos                      15                                                      /*!< PORT1 IN: P15 Position                  */\r
+#define PORT1_IN_P15_Msk                      (0x01UL << PORT1_IN_P15_Pos)                            /*!< PORT1 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT1_PDR0  --------------------------------- */\r
+#define PORT1_PDR0_PD0_Pos                    0                                                       /*!< PORT1 PDR0: PD0 Position                */\r
+#define PORT1_PDR0_PD0_Msk                    (0x07UL << PORT1_PDR0_PD0_Pos)                          /*!< PORT1 PDR0: PD0 Mask                    */\r
+#define PORT1_PDR0_PD1_Pos                    4                                                       /*!< PORT1 PDR0: PD1 Position                */\r
+#define PORT1_PDR0_PD1_Msk                    (0x07UL << PORT1_PDR0_PD1_Pos)                          /*!< PORT1 PDR0: PD1 Mask                    */\r
+#define PORT1_PDR0_PD2_Pos                    8                                                       /*!< PORT1 PDR0: PD2 Position                */\r
+#define PORT1_PDR0_PD2_Msk                    (0x07UL << PORT1_PDR0_PD2_Pos)                          /*!< PORT1 PDR0: PD2 Mask                    */\r
+#define PORT1_PDR0_PD3_Pos                    12                                                      /*!< PORT1 PDR0: PD3 Position                */\r
+#define PORT1_PDR0_PD3_Msk                    (0x07UL << PORT1_PDR0_PD3_Pos)                          /*!< PORT1 PDR0: PD3 Mask                    */\r
+#define PORT1_PDR0_PD4_Pos                    16                                                      /*!< PORT1 PDR0: PD4 Position                */\r
+#define PORT1_PDR0_PD4_Msk                    (0x07UL << PORT1_PDR0_PD4_Pos)                          /*!< PORT1 PDR0: PD4 Mask                    */\r
+#define PORT1_PDR0_PD5_Pos                    20                                                      /*!< PORT1 PDR0: PD5 Position                */\r
+#define PORT1_PDR0_PD5_Msk                    (0x07UL << PORT1_PDR0_PD5_Pos)                          /*!< PORT1 PDR0: PD5 Mask                    */\r
+#define PORT1_PDR0_PD6_Pos                    24                                                      /*!< PORT1 PDR0: PD6 Position                */\r
+#define PORT1_PDR0_PD6_Msk                    (0x07UL << PORT1_PDR0_PD6_Pos)                          /*!< PORT1 PDR0: PD6 Mask                    */\r
+#define PORT1_PDR0_PD7_Pos                    28                                                      /*!< PORT1 PDR0: PD7 Position                */\r
+#define PORT1_PDR0_PD7_Msk                    (0x07UL << PORT1_PDR0_PD7_Pos)                          /*!< PORT1 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT1_PDR1  --------------------------------- */\r
+#define PORT1_PDR1_PD8_Pos                    0                                                       /*!< PORT1 PDR1: PD8 Position                */\r
+#define PORT1_PDR1_PD8_Msk                    (0x07UL << PORT1_PDR1_PD8_Pos)                          /*!< PORT1 PDR1: PD8 Mask                    */\r
+#define PORT1_PDR1_PD9_Pos                    4                                                       /*!< PORT1 PDR1: PD9 Position                */\r
+#define PORT1_PDR1_PD9_Msk                    (0x07UL << PORT1_PDR1_PD9_Pos)                          /*!< PORT1 PDR1: PD9 Mask                    */\r
+#define PORT1_PDR1_PD10_Pos                   8                                                       /*!< PORT1 PDR1: PD10 Position               */\r
+#define PORT1_PDR1_PD10_Msk                   (0x07UL << PORT1_PDR1_PD10_Pos)                         /*!< PORT1 PDR1: PD10 Mask                   */\r
+#define PORT1_PDR1_PD11_Pos                   12                                                      /*!< PORT1 PDR1: PD11 Position               */\r
+#define PORT1_PDR1_PD11_Msk                   (0x07UL << PORT1_PDR1_PD11_Pos)                         /*!< PORT1 PDR1: PD11 Mask                   */\r
+#define PORT1_PDR1_PD12_Pos                   16                                                      /*!< PORT1 PDR1: PD12 Position               */\r
+#define PORT1_PDR1_PD12_Msk                   (0x07UL << PORT1_PDR1_PD12_Pos)                         /*!< PORT1 PDR1: PD12 Mask                   */\r
+#define PORT1_PDR1_PD13_Pos                   20                                                      /*!< PORT1 PDR1: PD13 Position               */\r
+#define PORT1_PDR1_PD13_Msk                   (0x07UL << PORT1_PDR1_PD13_Pos)                         /*!< PORT1 PDR1: PD13 Mask                   */\r
+#define PORT1_PDR1_PD14_Pos                   24                                                      /*!< PORT1 PDR1: PD14 Position               */\r
+#define PORT1_PDR1_PD14_Msk                   (0x07UL << PORT1_PDR1_PD14_Pos)                         /*!< PORT1 PDR1: PD14 Mask                   */\r
+#define PORT1_PDR1_PD15_Pos                   28                                                      /*!< PORT1 PDR1: PD15 Position               */\r
+#define PORT1_PDR1_PD15_Msk                   (0x07UL << PORT1_PDR1_PD15_Pos)                         /*!< PORT1 PDR1: PD15 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_PDISC  -------------------------------- */\r
+#define PORT1_PDISC_PDIS0_Pos                 0                                                       /*!< PORT1 PDISC: PDIS0 Position             */\r
+#define PORT1_PDISC_PDIS0_Msk                 (0x01UL << PORT1_PDISC_PDIS0_Pos)                       /*!< PORT1 PDISC: PDIS0 Mask                 */\r
+#define PORT1_PDISC_PDIS1_Pos                 1                                                       /*!< PORT1 PDISC: PDIS1 Position             */\r
+#define PORT1_PDISC_PDIS1_Msk                 (0x01UL << PORT1_PDISC_PDIS1_Pos)                       /*!< PORT1 PDISC: PDIS1 Mask                 */\r
+#define PORT1_PDISC_PDIS2_Pos                 2                                                       /*!< PORT1 PDISC: PDIS2 Position             */\r
+#define PORT1_PDISC_PDIS2_Msk                 (0x01UL << PORT1_PDISC_PDIS2_Pos)                       /*!< PORT1 PDISC: PDIS2 Mask                 */\r
+#define PORT1_PDISC_PDIS3_Pos                 3                                                       /*!< PORT1 PDISC: PDIS3 Position             */\r
+#define PORT1_PDISC_PDIS3_Msk                 (0x01UL << PORT1_PDISC_PDIS3_Pos)                       /*!< PORT1 PDISC: PDIS3 Mask                 */\r
+#define PORT1_PDISC_PDIS4_Pos                 4                                                       /*!< PORT1 PDISC: PDIS4 Position             */\r
+#define PORT1_PDISC_PDIS4_Msk                 (0x01UL << PORT1_PDISC_PDIS4_Pos)                       /*!< PORT1 PDISC: PDIS4 Mask                 */\r
+#define PORT1_PDISC_PDIS5_Pos                 5                                                       /*!< PORT1 PDISC: PDIS5 Position             */\r
+#define PORT1_PDISC_PDIS5_Msk                 (0x01UL << PORT1_PDISC_PDIS5_Pos)                       /*!< PORT1 PDISC: PDIS5 Mask                 */\r
+#define PORT1_PDISC_PDIS6_Pos                 6                                                       /*!< PORT1 PDISC: PDIS6 Position             */\r
+#define PORT1_PDISC_PDIS6_Msk                 (0x01UL << PORT1_PDISC_PDIS6_Pos)                       /*!< PORT1 PDISC: PDIS6 Mask                 */\r
+#define PORT1_PDISC_PDIS7_Pos                 7                                                       /*!< PORT1 PDISC: PDIS7 Position             */\r
+#define PORT1_PDISC_PDIS7_Msk                 (0x01UL << PORT1_PDISC_PDIS7_Pos)                       /*!< PORT1 PDISC: PDIS7 Mask                 */\r
+#define PORT1_PDISC_PDIS8_Pos                 8                                                       /*!< PORT1 PDISC: PDIS8 Position             */\r
+#define PORT1_PDISC_PDIS8_Msk                 (0x01UL << PORT1_PDISC_PDIS8_Pos)                       /*!< PORT1 PDISC: PDIS8 Mask                 */\r
+#define PORT1_PDISC_PDIS9_Pos                 9                                                       /*!< PORT1 PDISC: PDIS9 Position             */\r
+#define PORT1_PDISC_PDIS9_Msk                 (0x01UL << PORT1_PDISC_PDIS9_Pos)                       /*!< PORT1 PDISC: PDIS9 Mask                 */\r
+#define PORT1_PDISC_PDIS10_Pos                10                                                      /*!< PORT1 PDISC: PDIS10 Position            */\r
+#define PORT1_PDISC_PDIS10_Msk                (0x01UL << PORT1_PDISC_PDIS10_Pos)                      /*!< PORT1 PDISC: PDIS10 Mask                */\r
+#define PORT1_PDISC_PDIS11_Pos                11                                                      /*!< PORT1 PDISC: PDIS11 Position            */\r
+#define PORT1_PDISC_PDIS11_Msk                (0x01UL << PORT1_PDISC_PDIS11_Pos)                      /*!< PORT1 PDISC: PDIS11 Mask                */\r
+#define PORT1_PDISC_PDIS12_Pos                12                                                      /*!< PORT1 PDISC: PDIS12 Position            */\r
+#define PORT1_PDISC_PDIS12_Msk                (0x01UL << PORT1_PDISC_PDIS12_Pos)                      /*!< PORT1 PDISC: PDIS12 Mask                */\r
+#define PORT1_PDISC_PDIS13_Pos                13                                                      /*!< PORT1 PDISC: PDIS13 Position            */\r
+#define PORT1_PDISC_PDIS13_Msk                (0x01UL << PORT1_PDISC_PDIS13_Pos)                      /*!< PORT1 PDISC: PDIS13 Mask                */\r
+#define PORT1_PDISC_PDIS14_Pos                14                                                      /*!< PORT1 PDISC: PDIS14 Position            */\r
+#define PORT1_PDISC_PDIS14_Msk                (0x01UL << PORT1_PDISC_PDIS14_Pos)                      /*!< PORT1 PDISC: PDIS14 Mask                */\r
+#define PORT1_PDISC_PDIS15_Pos                15                                                      /*!< PORT1 PDISC: PDIS15 Position            */\r
+#define PORT1_PDISC_PDIS15_Msk                (0x01UL << PORT1_PDISC_PDIS15_Pos)                      /*!< PORT1 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT1_PPS  --------------------------------- */\r
+#define PORT1_PPS_PPS0_Pos                    0                                                       /*!< PORT1 PPS: PPS0 Position                */\r
+#define PORT1_PPS_PPS0_Msk                    (0x01UL << PORT1_PPS_PPS0_Pos)                          /*!< PORT1 PPS: PPS0 Mask                    */\r
+#define PORT1_PPS_PPS1_Pos                    1                                                       /*!< PORT1 PPS: PPS1 Position                */\r
+#define PORT1_PPS_PPS1_Msk                    (0x01UL << PORT1_PPS_PPS1_Pos)                          /*!< PORT1 PPS: PPS1 Mask                    */\r
+#define PORT1_PPS_PPS2_Pos                    2                                                       /*!< PORT1 PPS: PPS2 Position                */\r
+#define PORT1_PPS_PPS2_Msk                    (0x01UL << PORT1_PPS_PPS2_Pos)                          /*!< PORT1 PPS: PPS2 Mask                    */\r
+#define PORT1_PPS_PPS3_Pos                    3                                                       /*!< PORT1 PPS: PPS3 Position                */\r
+#define PORT1_PPS_PPS3_Msk                    (0x01UL << PORT1_PPS_PPS3_Pos)                          /*!< PORT1 PPS: PPS3 Mask                    */\r
+#define PORT1_PPS_PPS4_Pos                    4                                                       /*!< PORT1 PPS: PPS4 Position                */\r
+#define PORT1_PPS_PPS4_Msk                    (0x01UL << PORT1_PPS_PPS4_Pos)                          /*!< PORT1 PPS: PPS4 Mask                    */\r
+#define PORT1_PPS_PPS5_Pos                    5                                                       /*!< PORT1 PPS: PPS5 Position                */\r
+#define PORT1_PPS_PPS5_Msk                    (0x01UL << PORT1_PPS_PPS5_Pos)                          /*!< PORT1 PPS: PPS5 Mask                    */\r
+#define PORT1_PPS_PPS6_Pos                    6                                                       /*!< PORT1 PPS: PPS6 Position                */\r
+#define PORT1_PPS_PPS6_Msk                    (0x01UL << PORT1_PPS_PPS6_Pos)                          /*!< PORT1 PPS: PPS6 Mask                    */\r
+#define PORT1_PPS_PPS7_Pos                    7                                                       /*!< PORT1 PPS: PPS7 Position                */\r
+#define PORT1_PPS_PPS7_Msk                    (0x01UL << PORT1_PPS_PPS7_Pos)                          /*!< PORT1 PPS: PPS7 Mask                    */\r
+#define PORT1_PPS_PPS8_Pos                    8                                                       /*!< PORT1 PPS: PPS8 Position                */\r
+#define PORT1_PPS_PPS8_Msk                    (0x01UL << PORT1_PPS_PPS8_Pos)                          /*!< PORT1 PPS: PPS8 Mask                    */\r
+#define PORT1_PPS_PPS9_Pos                    9                                                       /*!< PORT1 PPS: PPS9 Position                */\r
+#define PORT1_PPS_PPS9_Msk                    (0x01UL << PORT1_PPS_PPS9_Pos)                          /*!< PORT1 PPS: PPS9 Mask                    */\r
+#define PORT1_PPS_PPS10_Pos                   10                                                      /*!< PORT1 PPS: PPS10 Position               */\r
+#define PORT1_PPS_PPS10_Msk                   (0x01UL << PORT1_PPS_PPS10_Pos)                         /*!< PORT1 PPS: PPS10 Mask                   */\r
+#define PORT1_PPS_PPS11_Pos                   11                                                      /*!< PORT1 PPS: PPS11 Position               */\r
+#define PORT1_PPS_PPS11_Msk                   (0x01UL << PORT1_PPS_PPS11_Pos)                         /*!< PORT1 PPS: PPS11 Mask                   */\r
+#define PORT1_PPS_PPS12_Pos                   12                                                      /*!< PORT1 PPS: PPS12 Position               */\r
+#define PORT1_PPS_PPS12_Msk                   (0x01UL << PORT1_PPS_PPS12_Pos)                         /*!< PORT1 PPS: PPS12 Mask                   */\r
+#define PORT1_PPS_PPS13_Pos                   13                                                      /*!< PORT1 PPS: PPS13 Position               */\r
+#define PORT1_PPS_PPS13_Msk                   (0x01UL << PORT1_PPS_PPS13_Pos)                         /*!< PORT1 PPS: PPS13 Mask                   */\r
+#define PORT1_PPS_PPS14_Pos                   14                                                      /*!< PORT1 PPS: PPS14 Position               */\r
+#define PORT1_PPS_PPS14_Msk                   (0x01UL << PORT1_PPS_PPS14_Pos)                         /*!< PORT1 PPS: PPS14 Mask                   */\r
+#define PORT1_PPS_PPS15_Pos                   15                                                      /*!< PORT1 PPS: PPS15 Position               */\r
+#define PORT1_PPS_PPS15_Msk                   (0x01UL << PORT1_PPS_PPS15_Pos)                         /*!< PORT1 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_HWSEL  -------------------------------- */\r
+#define PORT1_HWSEL_HW0_Pos                   0                                                       /*!< PORT1 HWSEL: HW0 Position               */\r
+#define PORT1_HWSEL_HW0_Msk                   (0x03UL << PORT1_HWSEL_HW0_Pos)                         /*!< PORT1 HWSEL: HW0 Mask                   */\r
+#define PORT1_HWSEL_HW1_Pos                   2                                                       /*!< PORT1 HWSEL: HW1 Position               */\r
+#define PORT1_HWSEL_HW1_Msk                   (0x03UL << PORT1_HWSEL_HW1_Pos)                         /*!< PORT1 HWSEL: HW1 Mask                   */\r
+#define PORT1_HWSEL_HW2_Pos                   4                                                       /*!< PORT1 HWSEL: HW2 Position               */\r
+#define PORT1_HWSEL_HW2_Msk                   (0x03UL << PORT1_HWSEL_HW2_Pos)                         /*!< PORT1 HWSEL: HW2 Mask                   */\r
+#define PORT1_HWSEL_HW3_Pos                   6                                                       /*!< PORT1 HWSEL: HW3 Position               */\r
+#define PORT1_HWSEL_HW3_Msk                   (0x03UL << PORT1_HWSEL_HW3_Pos)                         /*!< PORT1 HWSEL: HW3 Mask                   */\r
+#define PORT1_HWSEL_HW4_Pos                   8                                                       /*!< PORT1 HWSEL: HW4 Position               */\r
+#define PORT1_HWSEL_HW4_Msk                   (0x03UL << PORT1_HWSEL_HW4_Pos)                         /*!< PORT1 HWSEL: HW4 Mask                   */\r
+#define PORT1_HWSEL_HW5_Pos                   10                                                      /*!< PORT1 HWSEL: HW5 Position               */\r
+#define PORT1_HWSEL_HW5_Msk                   (0x03UL << PORT1_HWSEL_HW5_Pos)                         /*!< PORT1 HWSEL: HW5 Mask                   */\r
+#define PORT1_HWSEL_HW6_Pos                   12                                                      /*!< PORT1 HWSEL: HW6 Position               */\r
+#define PORT1_HWSEL_HW6_Msk                   (0x03UL << PORT1_HWSEL_HW6_Pos)                         /*!< PORT1 HWSEL: HW6 Mask                   */\r
+#define PORT1_HWSEL_HW7_Pos                   14                                                      /*!< PORT1 HWSEL: HW7 Position               */\r
+#define PORT1_HWSEL_HW7_Msk                   (0x03UL << PORT1_HWSEL_HW7_Pos)                         /*!< PORT1 HWSEL: HW7 Mask                   */\r
+#define PORT1_HWSEL_HW8_Pos                   16                                                      /*!< PORT1 HWSEL: HW8 Position               */\r
+#define PORT1_HWSEL_HW8_Msk                   (0x03UL << PORT1_HWSEL_HW8_Pos)                         /*!< PORT1 HWSEL: HW8 Mask                   */\r
+#define PORT1_HWSEL_HW9_Pos                   18                                                      /*!< PORT1 HWSEL: HW9 Position               */\r
+#define PORT1_HWSEL_HW9_Msk                   (0x03UL << PORT1_HWSEL_HW9_Pos)                         /*!< PORT1 HWSEL: HW9 Mask                   */\r
+#define PORT1_HWSEL_HW10_Pos                  20                                                      /*!< PORT1 HWSEL: HW10 Position              */\r
+#define PORT1_HWSEL_HW10_Msk                  (0x03UL << PORT1_HWSEL_HW10_Pos)                        /*!< PORT1 HWSEL: HW10 Mask                  */\r
+#define PORT1_HWSEL_HW11_Pos                  22                                                      /*!< PORT1 HWSEL: HW11 Position              */\r
+#define PORT1_HWSEL_HW11_Msk                  (0x03UL << PORT1_HWSEL_HW11_Pos)                        /*!< PORT1 HWSEL: HW11 Mask                  */\r
+#define PORT1_HWSEL_HW12_Pos                  24                                                      /*!< PORT1 HWSEL: HW12 Position              */\r
+#define PORT1_HWSEL_HW12_Msk                  (0x03UL << PORT1_HWSEL_HW12_Pos)                        /*!< PORT1 HWSEL: HW12 Mask                  */\r
+#define PORT1_HWSEL_HW13_Pos                  26                                                      /*!< PORT1 HWSEL: HW13 Position              */\r
+#define PORT1_HWSEL_HW13_Msk                  (0x03UL << PORT1_HWSEL_HW13_Pos)                        /*!< PORT1 HWSEL: HW13 Mask                  */\r
+#define PORT1_HWSEL_HW14_Pos                  28                                                      /*!< PORT1 HWSEL: HW14 Position              */\r
+#define PORT1_HWSEL_HW14_Msk                  (0x03UL << PORT1_HWSEL_HW14_Pos)                        /*!< PORT1 HWSEL: HW14 Mask                  */\r
+#define PORT1_HWSEL_HW15_Pos                  30                                                      /*!< PORT1 HWSEL: HW15 Position              */\r
+#define PORT1_HWSEL_HW15_Msk                  (0x03UL << PORT1_HWSEL_HW15_Pos)                        /*!< PORT1 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT2' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT2_OUT  --------------------------------- */\r
+#define PORT2_OUT_P0_Pos                      0                                                       /*!< PORT2 OUT: P0 Position                  */\r
+#define PORT2_OUT_P0_Msk                      (0x01UL << PORT2_OUT_P0_Pos)                            /*!< PORT2 OUT: P0 Mask                      */\r
+#define PORT2_OUT_P1_Pos                      1                                                       /*!< PORT2 OUT: P1 Position                  */\r
+#define PORT2_OUT_P1_Msk                      (0x01UL << PORT2_OUT_P1_Pos)                            /*!< PORT2 OUT: P1 Mask                      */\r
+#define PORT2_OUT_P2_Pos                      2                                                       /*!< PORT2 OUT: P2 Position                  */\r
+#define PORT2_OUT_P2_Msk                      (0x01UL << PORT2_OUT_P2_Pos)                            /*!< PORT2 OUT: P2 Mask                      */\r
+#define PORT2_OUT_P3_Pos                      3                                                       /*!< PORT2 OUT: P3 Position                  */\r
+#define PORT2_OUT_P3_Msk                      (0x01UL << PORT2_OUT_P3_Pos)                            /*!< PORT2 OUT: P3 Mask                      */\r
+#define PORT2_OUT_P4_Pos                      4                                                       /*!< PORT2 OUT: P4 Position                  */\r
+#define PORT2_OUT_P4_Msk                      (0x01UL << PORT2_OUT_P4_Pos)                            /*!< PORT2 OUT: P4 Mask                      */\r
+#define PORT2_OUT_P5_Pos                      5                                                       /*!< PORT2 OUT: P5 Position                  */\r
+#define PORT2_OUT_P5_Msk                      (0x01UL << PORT2_OUT_P5_Pos)                            /*!< PORT2 OUT: P5 Mask                      */\r
+#define PORT2_OUT_P6_Pos                      6                                                       /*!< PORT2 OUT: P6 Position                  */\r
+#define PORT2_OUT_P6_Msk                      (0x01UL << PORT2_OUT_P6_Pos)                            /*!< PORT2 OUT: P6 Mask                      */\r
+#define PORT2_OUT_P7_Pos                      7                                                       /*!< PORT2 OUT: P7 Position                  */\r
+#define PORT2_OUT_P7_Msk                      (0x01UL << PORT2_OUT_P7_Pos)                            /*!< PORT2 OUT: P7 Mask                      */\r
+#define PORT2_OUT_P8_Pos                      8                                                       /*!< PORT2 OUT: P8 Position                  */\r
+#define PORT2_OUT_P8_Msk                      (0x01UL << PORT2_OUT_P8_Pos)                            /*!< PORT2 OUT: P8 Mask                      */\r
+#define PORT2_OUT_P9_Pos                      9                                                       /*!< PORT2 OUT: P9 Position                  */\r
+#define PORT2_OUT_P9_Msk                      (0x01UL << PORT2_OUT_P9_Pos)                            /*!< PORT2 OUT: P9 Mask                      */\r
+#define PORT2_OUT_P10_Pos                     10                                                      /*!< PORT2 OUT: P10 Position                 */\r
+#define PORT2_OUT_P10_Msk                     (0x01UL << PORT2_OUT_P10_Pos)                           /*!< PORT2 OUT: P10 Mask                     */\r
+#define PORT2_OUT_P11_Pos                     11                                                      /*!< PORT2 OUT: P11 Position                 */\r
+#define PORT2_OUT_P11_Msk                     (0x01UL << PORT2_OUT_P11_Pos)                           /*!< PORT2 OUT: P11 Mask                     */\r
+#define PORT2_OUT_P12_Pos                     12                                                      /*!< PORT2 OUT: P12 Position                 */\r
+#define PORT2_OUT_P12_Msk                     (0x01UL << PORT2_OUT_P12_Pos)                           /*!< PORT2 OUT: P12 Mask                     */\r
+#define PORT2_OUT_P13_Pos                     13                                                      /*!< PORT2 OUT: P13 Position                 */\r
+#define PORT2_OUT_P13_Msk                     (0x01UL << PORT2_OUT_P13_Pos)                           /*!< PORT2 OUT: P13 Mask                     */\r
+#define PORT2_OUT_P14_Pos                     14                                                      /*!< PORT2 OUT: P14 Position                 */\r
+#define PORT2_OUT_P14_Msk                     (0x01UL << PORT2_OUT_P14_Pos)                           /*!< PORT2 OUT: P14 Mask                     */\r
+#define PORT2_OUT_P15_Pos                     15                                                      /*!< PORT2 OUT: P15 Position                 */\r
+#define PORT2_OUT_P15_Msk                     (0x01UL << PORT2_OUT_P15_Pos)                           /*!< PORT2 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT2_OMR  --------------------------------- */\r
+#define PORT2_OMR_PS0_Pos                     0                                                       /*!< PORT2 OMR: PS0 Position                 */\r
+#define PORT2_OMR_PS0_Msk                     (0x01UL << PORT2_OMR_PS0_Pos)                           /*!< PORT2 OMR: PS0 Mask                     */\r
+#define PORT2_OMR_PS1_Pos                     1                                                       /*!< PORT2 OMR: PS1 Position                 */\r
+#define PORT2_OMR_PS1_Msk                     (0x01UL << PORT2_OMR_PS1_Pos)                           /*!< PORT2 OMR: PS1 Mask                     */\r
+#define PORT2_OMR_PS2_Pos                     2                                                       /*!< PORT2 OMR: PS2 Position                 */\r
+#define PORT2_OMR_PS2_Msk                     (0x01UL << PORT2_OMR_PS2_Pos)                           /*!< PORT2 OMR: PS2 Mask                     */\r
+#define PORT2_OMR_PS3_Pos                     3                                                       /*!< PORT2 OMR: PS3 Position                 */\r
+#define PORT2_OMR_PS3_Msk                     (0x01UL << PORT2_OMR_PS3_Pos)                           /*!< PORT2 OMR: PS3 Mask                     */\r
+#define PORT2_OMR_PS4_Pos                     4                                                       /*!< PORT2 OMR: PS4 Position                 */\r
+#define PORT2_OMR_PS4_Msk                     (0x01UL << PORT2_OMR_PS4_Pos)                           /*!< PORT2 OMR: PS4 Mask                     */\r
+#define PORT2_OMR_PS5_Pos                     5                                                       /*!< PORT2 OMR: PS5 Position                 */\r
+#define PORT2_OMR_PS5_Msk                     (0x01UL << PORT2_OMR_PS5_Pos)                           /*!< PORT2 OMR: PS5 Mask                     */\r
+#define PORT2_OMR_PS6_Pos                     6                                                       /*!< PORT2 OMR: PS6 Position                 */\r
+#define PORT2_OMR_PS6_Msk                     (0x01UL << PORT2_OMR_PS6_Pos)                           /*!< PORT2 OMR: PS6 Mask                     */\r
+#define PORT2_OMR_PS7_Pos                     7                                                       /*!< PORT2 OMR: PS7 Position                 */\r
+#define PORT2_OMR_PS7_Msk                     (0x01UL << PORT2_OMR_PS7_Pos)                           /*!< PORT2 OMR: PS7 Mask                     */\r
+#define PORT2_OMR_PS8_Pos                     8                                                       /*!< PORT2 OMR: PS8 Position                 */\r
+#define PORT2_OMR_PS8_Msk                     (0x01UL << PORT2_OMR_PS8_Pos)                           /*!< PORT2 OMR: PS8 Mask                     */\r
+#define PORT2_OMR_PS9_Pos                     9                                                       /*!< PORT2 OMR: PS9 Position                 */\r
+#define PORT2_OMR_PS9_Msk                     (0x01UL << PORT2_OMR_PS9_Pos)                           /*!< PORT2 OMR: PS9 Mask                     */\r
+#define PORT2_OMR_PS10_Pos                    10                                                      /*!< PORT2 OMR: PS10 Position                */\r
+#define PORT2_OMR_PS10_Msk                    (0x01UL << PORT2_OMR_PS10_Pos)                          /*!< PORT2 OMR: PS10 Mask                    */\r
+#define PORT2_OMR_PS11_Pos                    11                                                      /*!< PORT2 OMR: PS11 Position                */\r
+#define PORT2_OMR_PS11_Msk                    (0x01UL << PORT2_OMR_PS11_Pos)                          /*!< PORT2 OMR: PS11 Mask                    */\r
+#define PORT2_OMR_PS12_Pos                    12                                                      /*!< PORT2 OMR: PS12 Position                */\r
+#define PORT2_OMR_PS12_Msk                    (0x01UL << PORT2_OMR_PS12_Pos)                          /*!< PORT2 OMR: PS12 Mask                    */\r
+#define PORT2_OMR_PS13_Pos                    13                                                      /*!< PORT2 OMR: PS13 Position                */\r
+#define PORT2_OMR_PS13_Msk                    (0x01UL << PORT2_OMR_PS13_Pos)                          /*!< PORT2 OMR: PS13 Mask                    */\r
+#define PORT2_OMR_PS14_Pos                    14                                                      /*!< PORT2 OMR: PS14 Position                */\r
+#define PORT2_OMR_PS14_Msk                    (0x01UL << PORT2_OMR_PS14_Pos)                          /*!< PORT2 OMR: PS14 Mask                    */\r
+#define PORT2_OMR_PS15_Pos                    15                                                      /*!< PORT2 OMR: PS15 Position                */\r
+#define PORT2_OMR_PS15_Msk                    (0x01UL << PORT2_OMR_PS15_Pos)                          /*!< PORT2 OMR: PS15 Mask                    */\r
+#define PORT2_OMR_PR0_Pos                     16                                                      /*!< PORT2 OMR: PR0 Position                 */\r
+#define PORT2_OMR_PR0_Msk                     (0x01UL << PORT2_OMR_PR0_Pos)                           /*!< PORT2 OMR: PR0 Mask                     */\r
+#define PORT2_OMR_PR1_Pos                     17                                                      /*!< PORT2 OMR: PR1 Position                 */\r
+#define PORT2_OMR_PR1_Msk                     (0x01UL << PORT2_OMR_PR1_Pos)                           /*!< PORT2 OMR: PR1 Mask                     */\r
+#define PORT2_OMR_PR2_Pos                     18                                                      /*!< PORT2 OMR: PR2 Position                 */\r
+#define PORT2_OMR_PR2_Msk                     (0x01UL << PORT2_OMR_PR2_Pos)                           /*!< PORT2 OMR: PR2 Mask                     */\r
+#define PORT2_OMR_PR3_Pos                     19                                                      /*!< PORT2 OMR: PR3 Position                 */\r
+#define PORT2_OMR_PR3_Msk                     (0x01UL << PORT2_OMR_PR3_Pos)                           /*!< PORT2 OMR: PR3 Mask                     */\r
+#define PORT2_OMR_PR4_Pos                     20                                                      /*!< PORT2 OMR: PR4 Position                 */\r
+#define PORT2_OMR_PR4_Msk                     (0x01UL << PORT2_OMR_PR4_Pos)                           /*!< PORT2 OMR: PR4 Mask                     */\r
+#define PORT2_OMR_PR5_Pos                     21                                                      /*!< PORT2 OMR: PR5 Position                 */\r
+#define PORT2_OMR_PR5_Msk                     (0x01UL << PORT2_OMR_PR5_Pos)                           /*!< PORT2 OMR: PR5 Mask                     */\r
+#define PORT2_OMR_PR6_Pos                     22                                                      /*!< PORT2 OMR: PR6 Position                 */\r
+#define PORT2_OMR_PR6_Msk                     (0x01UL << PORT2_OMR_PR6_Pos)                           /*!< PORT2 OMR: PR6 Mask                     */\r
+#define PORT2_OMR_PR7_Pos                     23                                                      /*!< PORT2 OMR: PR7 Position                 */\r
+#define PORT2_OMR_PR7_Msk                     (0x01UL << PORT2_OMR_PR7_Pos)                           /*!< PORT2 OMR: PR7 Mask                     */\r
+#define PORT2_OMR_PR8_Pos                     24                                                      /*!< PORT2 OMR: PR8 Position                 */\r
+#define PORT2_OMR_PR8_Msk                     (0x01UL << PORT2_OMR_PR8_Pos)                           /*!< PORT2 OMR: PR8 Mask                     */\r
+#define PORT2_OMR_PR9_Pos                     25                                                      /*!< PORT2 OMR: PR9 Position                 */\r
+#define PORT2_OMR_PR9_Msk                     (0x01UL << PORT2_OMR_PR9_Pos)                           /*!< PORT2 OMR: PR9 Mask                     */\r
+#define PORT2_OMR_PR10_Pos                    26                                                      /*!< PORT2 OMR: PR10 Position                */\r
+#define PORT2_OMR_PR10_Msk                    (0x01UL << PORT2_OMR_PR10_Pos)                          /*!< PORT2 OMR: PR10 Mask                    */\r
+#define PORT2_OMR_PR11_Pos                    27                                                      /*!< PORT2 OMR: PR11 Position                */\r
+#define PORT2_OMR_PR11_Msk                    (0x01UL << PORT2_OMR_PR11_Pos)                          /*!< PORT2 OMR: PR11 Mask                    */\r
+#define PORT2_OMR_PR12_Pos                    28                                                      /*!< PORT2 OMR: PR12 Position                */\r
+#define PORT2_OMR_PR12_Msk                    (0x01UL << PORT2_OMR_PR12_Pos)                          /*!< PORT2 OMR: PR12 Mask                    */\r
+#define PORT2_OMR_PR13_Pos                    29                                                      /*!< PORT2 OMR: PR13 Position                */\r
+#define PORT2_OMR_PR13_Msk                    (0x01UL << PORT2_OMR_PR13_Pos)                          /*!< PORT2 OMR: PR13 Mask                    */\r
+#define PORT2_OMR_PR14_Pos                    30                                                      /*!< PORT2 OMR: PR14 Position                */\r
+#define PORT2_OMR_PR14_Msk                    (0x01UL << PORT2_OMR_PR14_Pos)                          /*!< PORT2 OMR: PR14 Mask                    */\r
+#define PORT2_OMR_PR15_Pos                    31                                                      /*!< PORT2 OMR: PR15 Position                */\r
+#define PORT2_OMR_PR15_Msk                    (0x01UL << PORT2_OMR_PR15_Pos)                          /*!< PORT2 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT2_IOCR0  -------------------------------- */\r
+#define PORT2_IOCR0_PC0_Pos                   3                                                       /*!< PORT2 IOCR0: PC0 Position               */\r
+#define PORT2_IOCR0_PC0_Msk                   (0x1fUL << PORT2_IOCR0_PC0_Pos)                         /*!< PORT2 IOCR0: PC0 Mask                   */\r
+#define PORT2_IOCR0_PC1_Pos                   11                                                      /*!< PORT2 IOCR0: PC1 Position               */\r
+#define PORT2_IOCR0_PC1_Msk                   (0x1fUL << PORT2_IOCR0_PC1_Pos)                         /*!< PORT2 IOCR0: PC1 Mask                   */\r
+#define PORT2_IOCR0_PC2_Pos                   19                                                      /*!< PORT2 IOCR0: PC2 Position               */\r
+#define PORT2_IOCR0_PC2_Msk                   (0x1fUL << PORT2_IOCR0_PC2_Pos)                         /*!< PORT2 IOCR0: PC2 Mask                   */\r
+#define PORT2_IOCR0_PC3_Pos                   27                                                      /*!< PORT2 IOCR0: PC3 Position               */\r
+#define PORT2_IOCR0_PC3_Msk                   (0x1fUL << PORT2_IOCR0_PC3_Pos)                         /*!< PORT2 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_IOCR4  -------------------------------- */\r
+#define PORT2_IOCR4_PC4_Pos                   3                                                       /*!< PORT2 IOCR4: PC4 Position               */\r
+#define PORT2_IOCR4_PC4_Msk                   (0x1fUL << PORT2_IOCR4_PC4_Pos)                         /*!< PORT2 IOCR4: PC4 Mask                   */\r
+#define PORT2_IOCR4_PC5_Pos                   11                                                      /*!< PORT2 IOCR4: PC5 Position               */\r
+#define PORT2_IOCR4_PC5_Msk                   (0x1fUL << PORT2_IOCR4_PC5_Pos)                         /*!< PORT2 IOCR4: PC5 Mask                   */\r
+#define PORT2_IOCR4_PC6_Pos                   19                                                      /*!< PORT2 IOCR4: PC6 Position               */\r
+#define PORT2_IOCR4_PC6_Msk                   (0x1fUL << PORT2_IOCR4_PC6_Pos)                         /*!< PORT2 IOCR4: PC6 Mask                   */\r
+#define PORT2_IOCR4_PC7_Pos                   27                                                      /*!< PORT2 IOCR4: PC7 Position               */\r
+#define PORT2_IOCR4_PC7_Msk                   (0x1fUL << PORT2_IOCR4_PC7_Pos)                         /*!< PORT2 IOCR4: PC7 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_IOCR8  -------------------------------- */\r
+#define PORT2_IOCR8_PC8_Pos                   3                                                       /*!< PORT2 IOCR8: PC8 Position               */\r
+#define PORT2_IOCR8_PC8_Msk                   (0x1fUL << PORT2_IOCR8_PC8_Pos)                         /*!< PORT2 IOCR8: PC8 Mask                   */\r
+#define PORT2_IOCR8_PC9_Pos                   11                                                      /*!< PORT2 IOCR8: PC9 Position               */\r
+#define PORT2_IOCR8_PC9_Msk                   (0x1fUL << PORT2_IOCR8_PC9_Pos)                         /*!< PORT2 IOCR8: PC9 Mask                   */\r
+#define PORT2_IOCR8_PC10_Pos                  19                                                      /*!< PORT2 IOCR8: PC10 Position              */\r
+#define PORT2_IOCR8_PC10_Msk                  (0x1fUL << PORT2_IOCR8_PC10_Pos)                        /*!< PORT2 IOCR8: PC10 Mask                  */\r
+#define PORT2_IOCR8_PC11_Pos                  27                                                      /*!< PORT2 IOCR8: PC11 Position              */\r
+#define PORT2_IOCR8_PC11_Msk                  (0x1fUL << PORT2_IOCR8_PC11_Pos)                        /*!< PORT2 IOCR8: PC11 Mask                  */\r
+\r
+/* ----------------------------------  PORT2_IN  ---------------------------------- */\r
+#define PORT2_IN_P0_Pos                       0                                                       /*!< PORT2 IN: P0 Position                   */\r
+#define PORT2_IN_P0_Msk                       (0x01UL << PORT2_IN_P0_Pos)                             /*!< PORT2 IN: P0 Mask                       */\r
+#define PORT2_IN_P1_Pos                       1                                                       /*!< PORT2 IN: P1 Position                   */\r
+#define PORT2_IN_P1_Msk                       (0x01UL << PORT2_IN_P1_Pos)                             /*!< PORT2 IN: P1 Mask                       */\r
+#define PORT2_IN_P2_Pos                       2                                                       /*!< PORT2 IN: P2 Position                   */\r
+#define PORT2_IN_P2_Msk                       (0x01UL << PORT2_IN_P2_Pos)                             /*!< PORT2 IN: P2 Mask                       */\r
+#define PORT2_IN_P3_Pos                       3                                                       /*!< PORT2 IN: P3 Position                   */\r
+#define PORT2_IN_P3_Msk                       (0x01UL << PORT2_IN_P3_Pos)                             /*!< PORT2 IN: P3 Mask                       */\r
+#define PORT2_IN_P4_Pos                       4                                                       /*!< PORT2 IN: P4 Position                   */\r
+#define PORT2_IN_P4_Msk                       (0x01UL << PORT2_IN_P4_Pos)                             /*!< PORT2 IN: P4 Mask                       */\r
+#define PORT2_IN_P5_Pos                       5                                                       /*!< PORT2 IN: P5 Position                   */\r
+#define PORT2_IN_P5_Msk                       (0x01UL << PORT2_IN_P5_Pos)                             /*!< PORT2 IN: P5 Mask                       */\r
+#define PORT2_IN_P6_Pos                       6                                                       /*!< PORT2 IN: P6 Position                   */\r
+#define PORT2_IN_P6_Msk                       (0x01UL << PORT2_IN_P6_Pos)                             /*!< PORT2 IN: P6 Mask                       */\r
+#define PORT2_IN_P7_Pos                       7                                                       /*!< PORT2 IN: P7 Position                   */\r
+#define PORT2_IN_P7_Msk                       (0x01UL << PORT2_IN_P7_Pos)                             /*!< PORT2 IN: P7 Mask                       */\r
+#define PORT2_IN_P8_Pos                       8                                                       /*!< PORT2 IN: P8 Position                   */\r
+#define PORT2_IN_P8_Msk                       (0x01UL << PORT2_IN_P8_Pos)                             /*!< PORT2 IN: P8 Mask                       */\r
+#define PORT2_IN_P9_Pos                       9                                                       /*!< PORT2 IN: P9 Position                   */\r
+#define PORT2_IN_P9_Msk                       (0x01UL << PORT2_IN_P9_Pos)                             /*!< PORT2 IN: P9 Mask                       */\r
+#define PORT2_IN_P10_Pos                      10                                                      /*!< PORT2 IN: P10 Position                  */\r
+#define PORT2_IN_P10_Msk                      (0x01UL << PORT2_IN_P10_Pos)                            /*!< PORT2 IN: P10 Mask                      */\r
+#define PORT2_IN_P11_Pos                      11                                                      /*!< PORT2 IN: P11 Position                  */\r
+#define PORT2_IN_P11_Msk                      (0x01UL << PORT2_IN_P11_Pos)                            /*!< PORT2 IN: P11 Mask                      */\r
+#define PORT2_IN_P12_Pos                      12                                                      /*!< PORT2 IN: P12 Position                  */\r
+#define PORT2_IN_P12_Msk                      (0x01UL << PORT2_IN_P12_Pos)                            /*!< PORT2 IN: P12 Mask                      */\r
+#define PORT2_IN_P13_Pos                      13                                                      /*!< PORT2 IN: P13 Position                  */\r
+#define PORT2_IN_P13_Msk                      (0x01UL << PORT2_IN_P13_Pos)                            /*!< PORT2 IN: P13 Mask                      */\r
+#define PORT2_IN_P14_Pos                      14                                                      /*!< PORT2 IN: P14 Position                  */\r
+#define PORT2_IN_P14_Msk                      (0x01UL << PORT2_IN_P14_Pos)                            /*!< PORT2 IN: P14 Mask                      */\r
+#define PORT2_IN_P15_Pos                      15                                                      /*!< PORT2 IN: P15 Position                  */\r
+#define PORT2_IN_P15_Msk                      (0x01UL << PORT2_IN_P15_Pos)                            /*!< PORT2 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT2_PDR0  --------------------------------- */\r
+#define PORT2_PDR0_PD0_Pos                    0                                                       /*!< PORT2 PDR0: PD0 Position                */\r
+#define PORT2_PDR0_PD0_Msk                    (0x07UL << PORT2_PDR0_PD0_Pos)                          /*!< PORT2 PDR0: PD0 Mask                    */\r
+#define PORT2_PDR0_PD1_Pos                    4                                                       /*!< PORT2 PDR0: PD1 Position                */\r
+#define PORT2_PDR0_PD1_Msk                    (0x07UL << PORT2_PDR0_PD1_Pos)                          /*!< PORT2 PDR0: PD1 Mask                    */\r
+#define PORT2_PDR0_PD2_Pos                    8                                                       /*!< PORT2 PDR0: PD2 Position                */\r
+#define PORT2_PDR0_PD2_Msk                    (0x07UL << PORT2_PDR0_PD2_Pos)                          /*!< PORT2 PDR0: PD2 Mask                    */\r
+#define PORT2_PDR0_PD3_Pos                    12                                                      /*!< PORT2 PDR0: PD3 Position                */\r
+#define PORT2_PDR0_PD3_Msk                    (0x07UL << PORT2_PDR0_PD3_Pos)                          /*!< PORT2 PDR0: PD3 Mask                    */\r
+#define PORT2_PDR0_PD4_Pos                    16                                                      /*!< PORT2 PDR0: PD4 Position                */\r
+#define PORT2_PDR0_PD4_Msk                    (0x07UL << PORT2_PDR0_PD4_Pos)                          /*!< PORT2 PDR0: PD4 Mask                    */\r
+#define PORT2_PDR0_PD5_Pos                    20                                                      /*!< PORT2 PDR0: PD5 Position                */\r
+#define PORT2_PDR0_PD5_Msk                    (0x07UL << PORT2_PDR0_PD5_Pos)                          /*!< PORT2 PDR0: PD5 Mask                    */\r
+#define PORT2_PDR0_PD6_Pos                    24                                                      /*!< PORT2 PDR0: PD6 Position                */\r
+#define PORT2_PDR0_PD6_Msk                    (0x07UL << PORT2_PDR0_PD6_Pos)                          /*!< PORT2 PDR0: PD6 Mask                    */\r
+#define PORT2_PDR0_PD7_Pos                    28                                                      /*!< PORT2 PDR0: PD7 Position                */\r
+#define PORT2_PDR0_PD7_Msk                    (0x07UL << PORT2_PDR0_PD7_Pos)                          /*!< PORT2 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT2_PDR1  --------------------------------- */\r
+#define PORT2_PDR1_PD8_Pos                    0                                                       /*!< PORT2 PDR1: PD8 Position                */\r
+#define PORT2_PDR1_PD8_Msk                    (0x07UL << PORT2_PDR1_PD8_Pos)                          /*!< PORT2 PDR1: PD8 Mask                    */\r
+#define PORT2_PDR1_PD9_Pos                    4                                                       /*!< PORT2 PDR1: PD9 Position                */\r
+#define PORT2_PDR1_PD9_Msk                    (0x07UL << PORT2_PDR1_PD9_Pos)                          /*!< PORT2 PDR1: PD9 Mask                    */\r
+#define PORT2_PDR1_PD10_Pos                   8                                                       /*!< PORT2 PDR1: PD10 Position               */\r
+#define PORT2_PDR1_PD10_Msk                   (0x07UL << PORT2_PDR1_PD10_Pos)                         /*!< PORT2 PDR1: PD10 Mask                   */\r
+#define PORT2_PDR1_PD11_Pos                   12                                                      /*!< PORT2 PDR1: PD11 Position               */\r
+#define PORT2_PDR1_PD11_Msk                   (0x07UL << PORT2_PDR1_PD11_Pos)                         /*!< PORT2 PDR1: PD11 Mask                   */\r
+#define PORT2_PDR1_PD12_Pos                   16                                                      /*!< PORT2 PDR1: PD12 Position               */\r
+#define PORT2_PDR1_PD12_Msk                   (0x07UL << PORT2_PDR1_PD12_Pos)                         /*!< PORT2 PDR1: PD12 Mask                   */\r
+#define PORT2_PDR1_PD13_Pos                   20                                                      /*!< PORT2 PDR1: PD13 Position               */\r
+#define PORT2_PDR1_PD13_Msk                   (0x07UL << PORT2_PDR1_PD13_Pos)                         /*!< PORT2 PDR1: PD13 Mask                   */\r
+#define PORT2_PDR1_PD14_Pos                   24                                                      /*!< PORT2 PDR1: PD14 Position               */\r
+#define PORT2_PDR1_PD14_Msk                   (0x07UL << PORT2_PDR1_PD14_Pos)                         /*!< PORT2 PDR1: PD14 Mask                   */\r
+#define PORT2_PDR1_PD15_Pos                   28                                                      /*!< PORT2 PDR1: PD15 Position               */\r
+#define PORT2_PDR1_PD15_Msk                   (0x07UL << PORT2_PDR1_PD15_Pos)                         /*!< PORT2 PDR1: PD15 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_PDISC  -------------------------------- */\r
+#define PORT2_PDISC_PDIS0_Pos                 0                                                       /*!< PORT2 PDISC: PDIS0 Position             */\r
+#define PORT2_PDISC_PDIS0_Msk                 (0x01UL << PORT2_PDISC_PDIS0_Pos)                       /*!< PORT2 PDISC: PDIS0 Mask                 */\r
+#define PORT2_PDISC_PDIS1_Pos                 1                                                       /*!< PORT2 PDISC: PDIS1 Position             */\r
+#define PORT2_PDISC_PDIS1_Msk                 (0x01UL << PORT2_PDISC_PDIS1_Pos)                       /*!< PORT2 PDISC: PDIS1 Mask                 */\r
+#define PORT2_PDISC_PDIS2_Pos                 2                                                       /*!< PORT2 PDISC: PDIS2 Position             */\r
+#define PORT2_PDISC_PDIS2_Msk                 (0x01UL << PORT2_PDISC_PDIS2_Pos)                       /*!< PORT2 PDISC: PDIS2 Mask                 */\r
+#define PORT2_PDISC_PDIS3_Pos                 3                                                       /*!< PORT2 PDISC: PDIS3 Position             */\r
+#define PORT2_PDISC_PDIS3_Msk                 (0x01UL << PORT2_PDISC_PDIS3_Pos)                       /*!< PORT2 PDISC: PDIS3 Mask                 */\r
+#define PORT2_PDISC_PDIS4_Pos                 4                                                       /*!< PORT2 PDISC: PDIS4 Position             */\r
+#define PORT2_PDISC_PDIS4_Msk                 (0x01UL << PORT2_PDISC_PDIS4_Pos)                       /*!< PORT2 PDISC: PDIS4 Mask                 */\r
+#define PORT2_PDISC_PDIS5_Pos                 5                                                       /*!< PORT2 PDISC: PDIS5 Position             */\r
+#define PORT2_PDISC_PDIS5_Msk                 (0x01UL << PORT2_PDISC_PDIS5_Pos)                       /*!< PORT2 PDISC: PDIS5 Mask                 */\r
+#define PORT2_PDISC_PDIS6_Pos                 6                                                       /*!< PORT2 PDISC: PDIS6 Position             */\r
+#define PORT2_PDISC_PDIS6_Msk                 (0x01UL << PORT2_PDISC_PDIS6_Pos)                       /*!< PORT2 PDISC: PDIS6 Mask                 */\r
+#define PORT2_PDISC_PDIS7_Pos                 7                                                       /*!< PORT2 PDISC: PDIS7 Position             */\r
+#define PORT2_PDISC_PDIS7_Msk                 (0x01UL << PORT2_PDISC_PDIS7_Pos)                       /*!< PORT2 PDISC: PDIS7 Mask                 */\r
+#define PORT2_PDISC_PDIS8_Pos                 8                                                       /*!< PORT2 PDISC: PDIS8 Position             */\r
+#define PORT2_PDISC_PDIS8_Msk                 (0x01UL << PORT2_PDISC_PDIS8_Pos)                       /*!< PORT2 PDISC: PDIS8 Mask                 */\r
+#define PORT2_PDISC_PDIS9_Pos                 9                                                       /*!< PORT2 PDISC: PDIS9 Position             */\r
+#define PORT2_PDISC_PDIS9_Msk                 (0x01UL << PORT2_PDISC_PDIS9_Pos)                       /*!< PORT2 PDISC: PDIS9 Mask                 */\r
+#define PORT2_PDISC_PDIS10_Pos                10                                                      /*!< PORT2 PDISC: PDIS10 Position            */\r
+#define PORT2_PDISC_PDIS10_Msk                (0x01UL << PORT2_PDISC_PDIS10_Pos)                      /*!< PORT2 PDISC: PDIS10 Mask                */\r
+#define PORT2_PDISC_PDIS11_Pos                11                                                      /*!< PORT2 PDISC: PDIS11 Position            */\r
+#define PORT2_PDISC_PDIS11_Msk                (0x01UL << PORT2_PDISC_PDIS11_Pos)                      /*!< PORT2 PDISC: PDIS11 Mask                */\r
+#define PORT2_PDISC_PDIS12_Pos                12                                                      /*!< PORT2 PDISC: PDIS12 Position            */\r
+#define PORT2_PDISC_PDIS12_Msk                (0x01UL << PORT2_PDISC_PDIS12_Pos)                      /*!< PORT2 PDISC: PDIS12 Mask                */\r
+#define PORT2_PDISC_PDIS13_Pos                13                                                      /*!< PORT2 PDISC: PDIS13 Position            */\r
+#define PORT2_PDISC_PDIS13_Msk                (0x01UL << PORT2_PDISC_PDIS13_Pos)                      /*!< PORT2 PDISC: PDIS13 Mask                */\r
+#define PORT2_PDISC_PDIS14_Pos                14                                                      /*!< PORT2 PDISC: PDIS14 Position            */\r
+#define PORT2_PDISC_PDIS14_Msk                (0x01UL << PORT2_PDISC_PDIS14_Pos)                      /*!< PORT2 PDISC: PDIS14 Mask                */\r
+#define PORT2_PDISC_PDIS15_Pos                15                                                      /*!< PORT2 PDISC: PDIS15 Position            */\r
+#define PORT2_PDISC_PDIS15_Msk                (0x01UL << PORT2_PDISC_PDIS15_Pos)                      /*!< PORT2 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT2_PPS  --------------------------------- */\r
+#define PORT2_PPS_PPS0_Pos                    0                                                       /*!< PORT2 PPS: PPS0 Position                */\r
+#define PORT2_PPS_PPS0_Msk                    (0x01UL << PORT2_PPS_PPS0_Pos)                          /*!< PORT2 PPS: PPS0 Mask                    */\r
+#define PORT2_PPS_PPS1_Pos                    1                                                       /*!< PORT2 PPS: PPS1 Position                */\r
+#define PORT2_PPS_PPS1_Msk                    (0x01UL << PORT2_PPS_PPS1_Pos)                          /*!< PORT2 PPS: PPS1 Mask                    */\r
+#define PORT2_PPS_PPS2_Pos                    2                                                       /*!< PORT2 PPS: PPS2 Position                */\r
+#define PORT2_PPS_PPS2_Msk                    (0x01UL << PORT2_PPS_PPS2_Pos)                          /*!< PORT2 PPS: PPS2 Mask                    */\r
+#define PORT2_PPS_PPS3_Pos                    3                                                       /*!< PORT2 PPS: PPS3 Position                */\r
+#define PORT2_PPS_PPS3_Msk                    (0x01UL << PORT2_PPS_PPS3_Pos)                          /*!< PORT2 PPS: PPS3 Mask                    */\r
+#define PORT2_PPS_PPS4_Pos                    4                                                       /*!< PORT2 PPS: PPS4 Position                */\r
+#define PORT2_PPS_PPS4_Msk                    (0x01UL << PORT2_PPS_PPS4_Pos)                          /*!< PORT2 PPS: PPS4 Mask                    */\r
+#define PORT2_PPS_PPS5_Pos                    5                                                       /*!< PORT2 PPS: PPS5 Position                */\r
+#define PORT2_PPS_PPS5_Msk                    (0x01UL << PORT2_PPS_PPS5_Pos)                          /*!< PORT2 PPS: PPS5 Mask                    */\r
+#define PORT2_PPS_PPS6_Pos                    6                                                       /*!< PORT2 PPS: PPS6 Position                */\r
+#define PORT2_PPS_PPS6_Msk                    (0x01UL << PORT2_PPS_PPS6_Pos)                          /*!< PORT2 PPS: PPS6 Mask                    */\r
+#define PORT2_PPS_PPS7_Pos                    7                                                       /*!< PORT2 PPS: PPS7 Position                */\r
+#define PORT2_PPS_PPS7_Msk                    (0x01UL << PORT2_PPS_PPS7_Pos)                          /*!< PORT2 PPS: PPS7 Mask                    */\r
+#define PORT2_PPS_PPS8_Pos                    8                                                       /*!< PORT2 PPS: PPS8 Position                */\r
+#define PORT2_PPS_PPS8_Msk                    (0x01UL << PORT2_PPS_PPS8_Pos)                          /*!< PORT2 PPS: PPS8 Mask                    */\r
+#define PORT2_PPS_PPS9_Pos                    9                                                       /*!< PORT2 PPS: PPS9 Position                */\r
+#define PORT2_PPS_PPS9_Msk                    (0x01UL << PORT2_PPS_PPS9_Pos)                          /*!< PORT2 PPS: PPS9 Mask                    */\r
+#define PORT2_PPS_PPS10_Pos                   10                                                      /*!< PORT2 PPS: PPS10 Position               */\r
+#define PORT2_PPS_PPS10_Msk                   (0x01UL << PORT2_PPS_PPS10_Pos)                         /*!< PORT2 PPS: PPS10 Mask                   */\r
+#define PORT2_PPS_PPS11_Pos                   11                                                      /*!< PORT2 PPS: PPS11 Position               */\r
+#define PORT2_PPS_PPS11_Msk                   (0x01UL << PORT2_PPS_PPS11_Pos)                         /*!< PORT2 PPS: PPS11 Mask                   */\r
+#define PORT2_PPS_PPS12_Pos                   12                                                      /*!< PORT2 PPS: PPS12 Position               */\r
+#define PORT2_PPS_PPS12_Msk                   (0x01UL << PORT2_PPS_PPS12_Pos)                         /*!< PORT2 PPS: PPS12 Mask                   */\r
+#define PORT2_PPS_PPS13_Pos                   13                                                      /*!< PORT2 PPS: PPS13 Position               */\r
+#define PORT2_PPS_PPS13_Msk                   (0x01UL << PORT2_PPS_PPS13_Pos)                         /*!< PORT2 PPS: PPS13 Mask                   */\r
+#define PORT2_PPS_PPS14_Pos                   14                                                      /*!< PORT2 PPS: PPS14 Position               */\r
+#define PORT2_PPS_PPS14_Msk                   (0x01UL << PORT2_PPS_PPS14_Pos)                         /*!< PORT2 PPS: PPS14 Mask                   */\r
+#define PORT2_PPS_PPS15_Pos                   15                                                      /*!< PORT2 PPS: PPS15 Position               */\r
+#define PORT2_PPS_PPS15_Msk                   (0x01UL << PORT2_PPS_PPS15_Pos)                         /*!< PORT2 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_HWSEL  -------------------------------- */\r
+#define PORT2_HWSEL_HW0_Pos                   0                                                       /*!< PORT2 HWSEL: HW0 Position               */\r
+#define PORT2_HWSEL_HW0_Msk                   (0x03UL << PORT2_HWSEL_HW0_Pos)                         /*!< PORT2 HWSEL: HW0 Mask                   */\r
+#define PORT2_HWSEL_HW1_Pos                   2                                                       /*!< PORT2 HWSEL: HW1 Position               */\r
+#define PORT2_HWSEL_HW1_Msk                   (0x03UL << PORT2_HWSEL_HW1_Pos)                         /*!< PORT2 HWSEL: HW1 Mask                   */\r
+#define PORT2_HWSEL_HW2_Pos                   4                                                       /*!< PORT2 HWSEL: HW2 Position               */\r
+#define PORT2_HWSEL_HW2_Msk                   (0x03UL << PORT2_HWSEL_HW2_Pos)                         /*!< PORT2 HWSEL: HW2 Mask                   */\r
+#define PORT2_HWSEL_HW3_Pos                   6                                                       /*!< PORT2 HWSEL: HW3 Position               */\r
+#define PORT2_HWSEL_HW3_Msk                   (0x03UL << PORT2_HWSEL_HW3_Pos)                         /*!< PORT2 HWSEL: HW3 Mask                   */\r
+#define PORT2_HWSEL_HW4_Pos                   8                                                       /*!< PORT2 HWSEL: HW4 Position               */\r
+#define PORT2_HWSEL_HW4_Msk                   (0x03UL << PORT2_HWSEL_HW4_Pos)                         /*!< PORT2 HWSEL: HW4 Mask                   */\r
+#define PORT2_HWSEL_HW5_Pos                   10                                                      /*!< PORT2 HWSEL: HW5 Position               */\r
+#define PORT2_HWSEL_HW5_Msk                   (0x03UL << PORT2_HWSEL_HW5_Pos)                         /*!< PORT2 HWSEL: HW5 Mask                   */\r
+#define PORT2_HWSEL_HW6_Pos                   12                                                      /*!< PORT2 HWSEL: HW6 Position               */\r
+#define PORT2_HWSEL_HW6_Msk                   (0x03UL << PORT2_HWSEL_HW6_Pos)                         /*!< PORT2 HWSEL: HW6 Mask                   */\r
+#define PORT2_HWSEL_HW7_Pos                   14                                                      /*!< PORT2 HWSEL: HW7 Position               */\r
+#define PORT2_HWSEL_HW7_Msk                   (0x03UL << PORT2_HWSEL_HW7_Pos)                         /*!< PORT2 HWSEL: HW7 Mask                   */\r
+#define PORT2_HWSEL_HW8_Pos                   16                                                      /*!< PORT2 HWSEL: HW8 Position               */\r
+#define PORT2_HWSEL_HW8_Msk                   (0x03UL << PORT2_HWSEL_HW8_Pos)                         /*!< PORT2 HWSEL: HW8 Mask                   */\r
+#define PORT2_HWSEL_HW9_Pos                   18                                                      /*!< PORT2 HWSEL: HW9 Position               */\r
+#define PORT2_HWSEL_HW9_Msk                   (0x03UL << PORT2_HWSEL_HW9_Pos)                         /*!< PORT2 HWSEL: HW9 Mask                   */\r
+#define PORT2_HWSEL_HW10_Pos                  20                                                      /*!< PORT2 HWSEL: HW10 Position              */\r
+#define PORT2_HWSEL_HW10_Msk                  (0x03UL << PORT2_HWSEL_HW10_Pos)                        /*!< PORT2 HWSEL: HW10 Mask                  */\r
+#define PORT2_HWSEL_HW11_Pos                  22                                                      /*!< PORT2 HWSEL: HW11 Position              */\r
+#define PORT2_HWSEL_HW11_Msk                  (0x03UL << PORT2_HWSEL_HW11_Pos)                        /*!< PORT2 HWSEL: HW11 Mask                  */\r
+#define PORT2_HWSEL_HW12_Pos                  24                                                      /*!< PORT2 HWSEL: HW12 Position              */\r
+#define PORT2_HWSEL_HW12_Msk                  (0x03UL << PORT2_HWSEL_HW12_Pos)                        /*!< PORT2 HWSEL: HW12 Mask                  */\r
+#define PORT2_HWSEL_HW13_Pos                  26                                                      /*!< PORT2 HWSEL: HW13 Position              */\r
+#define PORT2_HWSEL_HW13_Msk                  (0x03UL << PORT2_HWSEL_HW13_Pos)                        /*!< PORT2 HWSEL: HW13 Mask                  */\r
+#define PORT2_HWSEL_HW14_Pos                  28                                                      /*!< PORT2 HWSEL: HW14 Position              */\r
+#define PORT2_HWSEL_HW14_Msk                  (0x03UL << PORT2_HWSEL_HW14_Pos)                        /*!< PORT2 HWSEL: HW14 Mask                  */\r
+#define PORT2_HWSEL_HW15_Pos                  30                                                      /*!< PORT2 HWSEL: HW15 Position              */\r
+#define PORT2_HWSEL_HW15_Msk                  (0x03UL << PORT2_HWSEL_HW15_Pos)                        /*!< PORT2 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT3' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT3_OUT  --------------------------------- */\r
+#define PORT3_OUT_P0_Pos                      0                                                       /*!< PORT3 OUT: P0 Position                  */\r
+#define PORT3_OUT_P0_Msk                      (0x01UL << PORT3_OUT_P0_Pos)                            /*!< PORT3 OUT: P0 Mask                      */\r
+#define PORT3_OUT_P1_Pos                      1                                                       /*!< PORT3 OUT: P1 Position                  */\r
+#define PORT3_OUT_P1_Msk                      (0x01UL << PORT3_OUT_P1_Pos)                            /*!< PORT3 OUT: P1 Mask                      */\r
+#define PORT3_OUT_P2_Pos                      2                                                       /*!< PORT3 OUT: P2 Position                  */\r
+#define PORT3_OUT_P2_Msk                      (0x01UL << PORT3_OUT_P2_Pos)                            /*!< PORT3 OUT: P2 Mask                      */\r
+#define PORT3_OUT_P3_Pos                      3                                                       /*!< PORT3 OUT: P3 Position                  */\r
+#define PORT3_OUT_P3_Msk                      (0x01UL << PORT3_OUT_P3_Pos)                            /*!< PORT3 OUT: P3 Mask                      */\r
+#define PORT3_OUT_P4_Pos                      4                                                       /*!< PORT3 OUT: P4 Position                  */\r
+#define PORT3_OUT_P4_Msk                      (0x01UL << PORT3_OUT_P4_Pos)                            /*!< PORT3 OUT: P4 Mask                      */\r
+#define PORT3_OUT_P5_Pos                      5                                                       /*!< PORT3 OUT: P5 Position                  */\r
+#define PORT3_OUT_P5_Msk                      (0x01UL << PORT3_OUT_P5_Pos)                            /*!< PORT3 OUT: P5 Mask                      */\r
+#define PORT3_OUT_P6_Pos                      6                                                       /*!< PORT3 OUT: P6 Position                  */\r
+#define PORT3_OUT_P6_Msk                      (0x01UL << PORT3_OUT_P6_Pos)                            /*!< PORT3 OUT: P6 Mask                      */\r
+#define PORT3_OUT_P7_Pos                      7                                                       /*!< PORT3 OUT: P7 Position                  */\r
+#define PORT3_OUT_P7_Msk                      (0x01UL << PORT3_OUT_P7_Pos)                            /*!< PORT3 OUT: P7 Mask                      */\r
+#define PORT3_OUT_P8_Pos                      8                                                       /*!< PORT3 OUT: P8 Position                  */\r
+#define PORT3_OUT_P8_Msk                      (0x01UL << PORT3_OUT_P8_Pos)                            /*!< PORT3 OUT: P8 Mask                      */\r
+#define PORT3_OUT_P9_Pos                      9                                                       /*!< PORT3 OUT: P9 Position                  */\r
+#define PORT3_OUT_P9_Msk                      (0x01UL << PORT3_OUT_P9_Pos)                            /*!< PORT3 OUT: P9 Mask                      */\r
+#define PORT3_OUT_P10_Pos                     10                                                      /*!< PORT3 OUT: P10 Position                 */\r
+#define PORT3_OUT_P10_Msk                     (0x01UL << PORT3_OUT_P10_Pos)                           /*!< PORT3 OUT: P10 Mask                     */\r
+#define PORT3_OUT_P11_Pos                     11                                                      /*!< PORT3 OUT: P11 Position                 */\r
+#define PORT3_OUT_P11_Msk                     (0x01UL << PORT3_OUT_P11_Pos)                           /*!< PORT3 OUT: P11 Mask                     */\r
+#define PORT3_OUT_P12_Pos                     12                                                      /*!< PORT3 OUT: P12 Position                 */\r
+#define PORT3_OUT_P12_Msk                     (0x01UL << PORT3_OUT_P12_Pos)                           /*!< PORT3 OUT: P12 Mask                     */\r
+#define PORT3_OUT_P13_Pos                     13                                                      /*!< PORT3 OUT: P13 Position                 */\r
+#define PORT3_OUT_P13_Msk                     (0x01UL << PORT3_OUT_P13_Pos)                           /*!< PORT3 OUT: P13 Mask                     */\r
+#define PORT3_OUT_P14_Pos                     14                                                      /*!< PORT3 OUT: P14 Position                 */\r
+#define PORT3_OUT_P14_Msk                     (0x01UL << PORT3_OUT_P14_Pos)                           /*!< PORT3 OUT: P14 Mask                     */\r
+#define PORT3_OUT_P15_Pos                     15                                                      /*!< PORT3 OUT: P15 Position                 */\r
+#define PORT3_OUT_P15_Msk                     (0x01UL << PORT3_OUT_P15_Pos)                           /*!< PORT3 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT3_OMR  --------------------------------- */\r
+#define PORT3_OMR_PS0_Pos                     0                                                       /*!< PORT3 OMR: PS0 Position                 */\r
+#define PORT3_OMR_PS0_Msk                     (0x01UL << PORT3_OMR_PS0_Pos)                           /*!< PORT3 OMR: PS0 Mask                     */\r
+#define PORT3_OMR_PS1_Pos                     1                                                       /*!< PORT3 OMR: PS1 Position                 */\r
+#define PORT3_OMR_PS1_Msk                     (0x01UL << PORT3_OMR_PS1_Pos)                           /*!< PORT3 OMR: PS1 Mask                     */\r
+#define PORT3_OMR_PS2_Pos                     2                                                       /*!< PORT3 OMR: PS2 Position                 */\r
+#define PORT3_OMR_PS2_Msk                     (0x01UL << PORT3_OMR_PS2_Pos)                           /*!< PORT3 OMR: PS2 Mask                     */\r
+#define PORT3_OMR_PS3_Pos                     3                                                       /*!< PORT3 OMR: PS3 Position                 */\r
+#define PORT3_OMR_PS3_Msk                     (0x01UL << PORT3_OMR_PS3_Pos)                           /*!< PORT3 OMR: PS3 Mask                     */\r
+#define PORT3_OMR_PS4_Pos                     4                                                       /*!< PORT3 OMR: PS4 Position                 */\r
+#define PORT3_OMR_PS4_Msk                     (0x01UL << PORT3_OMR_PS4_Pos)                           /*!< PORT3 OMR: PS4 Mask                     */\r
+#define PORT3_OMR_PS5_Pos                     5                                                       /*!< PORT3 OMR: PS5 Position                 */\r
+#define PORT3_OMR_PS5_Msk                     (0x01UL << PORT3_OMR_PS5_Pos)                           /*!< PORT3 OMR: PS5 Mask                     */\r
+#define PORT3_OMR_PS6_Pos                     6                                                       /*!< PORT3 OMR: PS6 Position                 */\r
+#define PORT3_OMR_PS6_Msk                     (0x01UL << PORT3_OMR_PS6_Pos)                           /*!< PORT3 OMR: PS6 Mask                     */\r
+#define PORT3_OMR_PS7_Pos                     7                                                       /*!< PORT3 OMR: PS7 Position                 */\r
+#define PORT3_OMR_PS7_Msk                     (0x01UL << PORT3_OMR_PS7_Pos)                           /*!< PORT3 OMR: PS7 Mask                     */\r
+#define PORT3_OMR_PS8_Pos                     8                                                       /*!< PORT3 OMR: PS8 Position                 */\r
+#define PORT3_OMR_PS8_Msk                     (0x01UL << PORT3_OMR_PS8_Pos)                           /*!< PORT3 OMR: PS8 Mask                     */\r
+#define PORT3_OMR_PS9_Pos                     9                                                       /*!< PORT3 OMR: PS9 Position                 */\r
+#define PORT3_OMR_PS9_Msk                     (0x01UL << PORT3_OMR_PS9_Pos)                           /*!< PORT3 OMR: PS9 Mask                     */\r
+#define PORT3_OMR_PS10_Pos                    10                                                      /*!< PORT3 OMR: PS10 Position                */\r
+#define PORT3_OMR_PS10_Msk                    (0x01UL << PORT3_OMR_PS10_Pos)                          /*!< PORT3 OMR: PS10 Mask                    */\r
+#define PORT3_OMR_PS11_Pos                    11                                                      /*!< PORT3 OMR: PS11 Position                */\r
+#define PORT3_OMR_PS11_Msk                    (0x01UL << PORT3_OMR_PS11_Pos)                          /*!< PORT3 OMR: PS11 Mask                    */\r
+#define PORT3_OMR_PS12_Pos                    12                                                      /*!< PORT3 OMR: PS12 Position                */\r
+#define PORT3_OMR_PS12_Msk                    (0x01UL << PORT3_OMR_PS12_Pos)                          /*!< PORT3 OMR: PS12 Mask                    */\r
+#define PORT3_OMR_PS13_Pos                    13                                                      /*!< PORT3 OMR: PS13 Position                */\r
+#define PORT3_OMR_PS13_Msk                    (0x01UL << PORT3_OMR_PS13_Pos)                          /*!< PORT3 OMR: PS13 Mask                    */\r
+#define PORT3_OMR_PS14_Pos                    14                                                      /*!< PORT3 OMR: PS14 Position                */\r
+#define PORT3_OMR_PS14_Msk                    (0x01UL << PORT3_OMR_PS14_Pos)                          /*!< PORT3 OMR: PS14 Mask                    */\r
+#define PORT3_OMR_PS15_Pos                    15                                                      /*!< PORT3 OMR: PS15 Position                */\r
+#define PORT3_OMR_PS15_Msk                    (0x01UL << PORT3_OMR_PS15_Pos)                          /*!< PORT3 OMR: PS15 Mask                    */\r
+#define PORT3_OMR_PR0_Pos                     16                                                      /*!< PORT3 OMR: PR0 Position                 */\r
+#define PORT3_OMR_PR0_Msk                     (0x01UL << PORT3_OMR_PR0_Pos)                           /*!< PORT3 OMR: PR0 Mask                     */\r
+#define PORT3_OMR_PR1_Pos                     17                                                      /*!< PORT3 OMR: PR1 Position                 */\r
+#define PORT3_OMR_PR1_Msk                     (0x01UL << PORT3_OMR_PR1_Pos)                           /*!< PORT3 OMR: PR1 Mask                     */\r
+#define PORT3_OMR_PR2_Pos                     18                                                      /*!< PORT3 OMR: PR2 Position                 */\r
+#define PORT3_OMR_PR2_Msk                     (0x01UL << PORT3_OMR_PR2_Pos)                           /*!< PORT3 OMR: PR2 Mask                     */\r
+#define PORT3_OMR_PR3_Pos                     19                                                      /*!< PORT3 OMR: PR3 Position                 */\r
+#define PORT3_OMR_PR3_Msk                     (0x01UL << PORT3_OMR_PR3_Pos)                           /*!< PORT3 OMR: PR3 Mask                     */\r
+#define PORT3_OMR_PR4_Pos                     20                                                      /*!< PORT3 OMR: PR4 Position                 */\r
+#define PORT3_OMR_PR4_Msk                     (0x01UL << PORT3_OMR_PR4_Pos)                           /*!< PORT3 OMR: PR4 Mask                     */\r
+#define PORT3_OMR_PR5_Pos                     21                                                      /*!< PORT3 OMR: PR5 Position                 */\r
+#define PORT3_OMR_PR5_Msk                     (0x01UL << PORT3_OMR_PR5_Pos)                           /*!< PORT3 OMR: PR5 Mask                     */\r
+#define PORT3_OMR_PR6_Pos                     22                                                      /*!< PORT3 OMR: PR6 Position                 */\r
+#define PORT3_OMR_PR6_Msk                     (0x01UL << PORT3_OMR_PR6_Pos)                           /*!< PORT3 OMR: PR6 Mask                     */\r
+#define PORT3_OMR_PR7_Pos                     23                                                      /*!< PORT3 OMR: PR7 Position                 */\r
+#define PORT3_OMR_PR7_Msk                     (0x01UL << PORT3_OMR_PR7_Pos)                           /*!< PORT3 OMR: PR7 Mask                     */\r
+#define PORT3_OMR_PR8_Pos                     24                                                      /*!< PORT3 OMR: PR8 Position                 */\r
+#define PORT3_OMR_PR8_Msk                     (0x01UL << PORT3_OMR_PR8_Pos)                           /*!< PORT3 OMR: PR8 Mask                     */\r
+#define PORT3_OMR_PR9_Pos                     25                                                      /*!< PORT3 OMR: PR9 Position                 */\r
+#define PORT3_OMR_PR9_Msk                     (0x01UL << PORT3_OMR_PR9_Pos)                           /*!< PORT3 OMR: PR9 Mask                     */\r
+#define PORT3_OMR_PR10_Pos                    26                                                      /*!< PORT3 OMR: PR10 Position                */\r
+#define PORT3_OMR_PR10_Msk                    (0x01UL << PORT3_OMR_PR10_Pos)                          /*!< PORT3 OMR: PR10 Mask                    */\r
+#define PORT3_OMR_PR11_Pos                    27                                                      /*!< PORT3 OMR: PR11 Position                */\r
+#define PORT3_OMR_PR11_Msk                    (0x01UL << PORT3_OMR_PR11_Pos)                          /*!< PORT3 OMR: PR11 Mask                    */\r
+#define PORT3_OMR_PR12_Pos                    28                                                      /*!< PORT3 OMR: PR12 Position                */\r
+#define PORT3_OMR_PR12_Msk                    (0x01UL << PORT3_OMR_PR12_Pos)                          /*!< PORT3 OMR: PR12 Mask                    */\r
+#define PORT3_OMR_PR13_Pos                    29                                                      /*!< PORT3 OMR: PR13 Position                */\r
+#define PORT3_OMR_PR13_Msk                    (0x01UL << PORT3_OMR_PR13_Pos)                          /*!< PORT3 OMR: PR13 Mask                    */\r
+#define PORT3_OMR_PR14_Pos                    30                                                      /*!< PORT3 OMR: PR14 Position                */\r
+#define PORT3_OMR_PR14_Msk                    (0x01UL << PORT3_OMR_PR14_Pos)                          /*!< PORT3 OMR: PR14 Mask                    */\r
+#define PORT3_OMR_PR15_Pos                    31                                                      /*!< PORT3 OMR: PR15 Position                */\r
+#define PORT3_OMR_PR15_Msk                    (0x01UL << PORT3_OMR_PR15_Pos)                          /*!< PORT3 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT3_IOCR0  -------------------------------- */\r
+#define PORT3_IOCR0_PC0_Pos                   3                                                       /*!< PORT3 IOCR0: PC0 Position               */\r
+#define PORT3_IOCR0_PC0_Msk                   (0x1fUL << PORT3_IOCR0_PC0_Pos)                         /*!< PORT3 IOCR0: PC0 Mask                   */\r
+#define PORT3_IOCR0_PC1_Pos                   11                                                      /*!< PORT3 IOCR0: PC1 Position               */\r
+#define PORT3_IOCR0_PC1_Msk                   (0x1fUL << PORT3_IOCR0_PC1_Pos)                         /*!< PORT3 IOCR0: PC1 Mask                   */\r
+#define PORT3_IOCR0_PC2_Pos                   19                                                      /*!< PORT3 IOCR0: PC2 Position               */\r
+#define PORT3_IOCR0_PC2_Msk                   (0x1fUL << PORT3_IOCR0_PC2_Pos)                         /*!< PORT3 IOCR0: PC2 Mask                   */\r
+#define PORT3_IOCR0_PC3_Pos                   27                                                      /*!< PORT3 IOCR0: PC3 Position               */\r
+#define PORT3_IOCR0_PC3_Msk                   (0x1fUL << PORT3_IOCR0_PC3_Pos)                         /*!< PORT3 IOCR0: PC3 Mask                   */\r
+\r
+/* ----------------------------------  PORT3_IN  ---------------------------------- */\r
+#define PORT3_IN_P0_Pos                       0                                                       /*!< PORT3 IN: P0 Position                   */\r
+#define PORT3_IN_P0_Msk                       (0x01UL << PORT3_IN_P0_Pos)                             /*!< PORT3 IN: P0 Mask                       */\r
+#define PORT3_IN_P1_Pos                       1                                                       /*!< PORT3 IN: P1 Position                   */\r
+#define PORT3_IN_P1_Msk                       (0x01UL << PORT3_IN_P1_Pos)                             /*!< PORT3 IN: P1 Mask                       */\r
+#define PORT3_IN_P2_Pos                       2                                                       /*!< PORT3 IN: P2 Position                   */\r
+#define PORT3_IN_P2_Msk                       (0x01UL << PORT3_IN_P2_Pos)                             /*!< PORT3 IN: P2 Mask                       */\r
+#define PORT3_IN_P3_Pos                       3                                                       /*!< PORT3 IN: P3 Position                   */\r
+#define PORT3_IN_P3_Msk                       (0x01UL << PORT3_IN_P3_Pos)                             /*!< PORT3 IN: P3 Mask                       */\r
+#define PORT3_IN_P4_Pos                       4                                                       /*!< PORT3 IN: P4 Position                   */\r
+#define PORT3_IN_P4_Msk                       (0x01UL << PORT3_IN_P4_Pos)                             /*!< PORT3 IN: P4 Mask                       */\r
+#define PORT3_IN_P5_Pos                       5                                                       /*!< PORT3 IN: P5 Position                   */\r
+#define PORT3_IN_P5_Msk                       (0x01UL << PORT3_IN_P5_Pos)                             /*!< PORT3 IN: P5 Mask                       */\r
+#define PORT3_IN_P6_Pos                       6                                                       /*!< PORT3 IN: P6 Position                   */\r
+#define PORT3_IN_P6_Msk                       (0x01UL << PORT3_IN_P6_Pos)                             /*!< PORT3 IN: P6 Mask                       */\r
+#define PORT3_IN_P7_Pos                       7                                                       /*!< PORT3 IN: P7 Position                   */\r
+#define PORT3_IN_P7_Msk                       (0x01UL << PORT3_IN_P7_Pos)                             /*!< PORT3 IN: P7 Mask                       */\r
+#define PORT3_IN_P8_Pos                       8                                                       /*!< PORT3 IN: P8 Position                   */\r
+#define PORT3_IN_P8_Msk                       (0x01UL << PORT3_IN_P8_Pos)                             /*!< PORT3 IN: P8 Mask                       */\r
+#define PORT3_IN_P9_Pos                       9                                                       /*!< PORT3 IN: P9 Position                   */\r
+#define PORT3_IN_P9_Msk                       (0x01UL << PORT3_IN_P9_Pos)                             /*!< PORT3 IN: P9 Mask                       */\r
+#define PORT3_IN_P10_Pos                      10                                                      /*!< PORT3 IN: P10 Position                  */\r
+#define PORT3_IN_P10_Msk                      (0x01UL << PORT3_IN_P10_Pos)                            /*!< PORT3 IN: P10 Mask                      */\r
+#define PORT3_IN_P11_Pos                      11                                                      /*!< PORT3 IN: P11 Position                  */\r
+#define PORT3_IN_P11_Msk                      (0x01UL << PORT3_IN_P11_Pos)                            /*!< PORT3 IN: P11 Mask                      */\r
+#define PORT3_IN_P12_Pos                      12                                                      /*!< PORT3 IN: P12 Position                  */\r
+#define PORT3_IN_P12_Msk                      (0x01UL << PORT3_IN_P12_Pos)                            /*!< PORT3 IN: P12 Mask                      */\r
+#define PORT3_IN_P13_Pos                      13                                                      /*!< PORT3 IN: P13 Position                  */\r
+#define PORT3_IN_P13_Msk                      (0x01UL << PORT3_IN_P13_Pos)                            /*!< PORT3 IN: P13 Mask                      */\r
+#define PORT3_IN_P14_Pos                      14                                                      /*!< PORT3 IN: P14 Position                  */\r
+#define PORT3_IN_P14_Msk                      (0x01UL << PORT3_IN_P14_Pos)                            /*!< PORT3 IN: P14 Mask                      */\r
+#define PORT3_IN_P15_Pos                      15                                                      /*!< PORT3 IN: P15 Position                  */\r
+#define PORT3_IN_P15_Msk                      (0x01UL << PORT3_IN_P15_Pos)                            /*!< PORT3 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT3_PDR0  --------------------------------- */\r
+#define PORT3_PDR0_PD0_Pos                    0                                                       /*!< PORT3 PDR0: PD0 Position                */\r
+#define PORT3_PDR0_PD0_Msk                    (0x07UL << PORT3_PDR0_PD0_Pos)                          /*!< PORT3 PDR0: PD0 Mask                    */\r
+#define PORT3_PDR0_PD1_Pos                    4                                                       /*!< PORT3 PDR0: PD1 Position                */\r
+#define PORT3_PDR0_PD1_Msk                    (0x07UL << PORT3_PDR0_PD1_Pos)                          /*!< PORT3 PDR0: PD1 Mask                    */\r
+#define PORT3_PDR0_PD2_Pos                    8                                                       /*!< PORT3 PDR0: PD2 Position                */\r
+#define PORT3_PDR0_PD2_Msk                    (0x07UL << PORT3_PDR0_PD2_Pos)                          /*!< PORT3 PDR0: PD2 Mask                    */\r
+#define PORT3_PDR0_PD3_Pos                    12                                                      /*!< PORT3 PDR0: PD3 Position                */\r
+#define PORT3_PDR0_PD3_Msk                    (0x07UL << PORT3_PDR0_PD3_Pos)                          /*!< PORT3 PDR0: PD3 Mask                    */\r
+#define PORT3_PDR0_PD4_Pos                    16                                                      /*!< PORT3 PDR0: PD4 Position                */\r
+#define PORT3_PDR0_PD4_Msk                    (0x07UL << PORT3_PDR0_PD4_Pos)                          /*!< PORT3 PDR0: PD4 Mask                    */\r
+#define PORT3_PDR0_PD5_Pos                    20                                                      /*!< PORT3 PDR0: PD5 Position                */\r
+#define PORT3_PDR0_PD5_Msk                    (0x07UL << PORT3_PDR0_PD5_Pos)                          /*!< PORT3 PDR0: PD5 Mask                    */\r
+#define PORT3_PDR0_PD6_Pos                    24                                                      /*!< PORT3 PDR0: PD6 Position                */\r
+#define PORT3_PDR0_PD6_Msk                    (0x07UL << PORT3_PDR0_PD6_Pos)                          /*!< PORT3 PDR0: PD6 Mask                    */\r
+#define PORT3_PDR0_PD7_Pos                    28                                                      /*!< PORT3 PDR0: PD7 Position                */\r
+#define PORT3_PDR0_PD7_Msk                    (0x07UL << PORT3_PDR0_PD7_Pos)                          /*!< PORT3 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT3_PDISC  -------------------------------- */\r
+#define PORT3_PDISC_PDIS0_Pos                 0                                                       /*!< PORT3 PDISC: PDIS0 Position             */\r
+#define PORT3_PDISC_PDIS0_Msk                 (0x01UL << PORT3_PDISC_PDIS0_Pos)                       /*!< PORT3 PDISC: PDIS0 Mask                 */\r
+#define PORT3_PDISC_PDIS1_Pos                 1                                                       /*!< PORT3 PDISC: PDIS1 Position             */\r
+#define PORT3_PDISC_PDIS1_Msk                 (0x01UL << PORT3_PDISC_PDIS1_Pos)                       /*!< PORT3 PDISC: PDIS1 Mask                 */\r
+#define PORT3_PDISC_PDIS2_Pos                 2                                                       /*!< PORT3 PDISC: PDIS2 Position             */\r
+#define PORT3_PDISC_PDIS2_Msk                 (0x01UL << PORT3_PDISC_PDIS2_Pos)                       /*!< PORT3 PDISC: PDIS2 Mask                 */\r
+#define PORT3_PDISC_PDIS3_Pos                 3                                                       /*!< PORT3 PDISC: PDIS3 Position             */\r
+#define PORT3_PDISC_PDIS3_Msk                 (0x01UL << PORT3_PDISC_PDIS3_Pos)                       /*!< PORT3 PDISC: PDIS3 Mask                 */\r
+#define PORT3_PDISC_PDIS4_Pos                 4                                                       /*!< PORT3 PDISC: PDIS4 Position             */\r
+#define PORT3_PDISC_PDIS4_Msk                 (0x01UL << PORT3_PDISC_PDIS4_Pos)                       /*!< PORT3 PDISC: PDIS4 Mask                 */\r
+#define PORT3_PDISC_PDIS5_Pos                 5                                                       /*!< PORT3 PDISC: PDIS5 Position             */\r
+#define PORT3_PDISC_PDIS5_Msk                 (0x01UL << PORT3_PDISC_PDIS5_Pos)                       /*!< PORT3 PDISC: PDIS5 Mask                 */\r
+#define PORT3_PDISC_PDIS6_Pos                 6                                                       /*!< PORT3 PDISC: PDIS6 Position             */\r
+#define PORT3_PDISC_PDIS6_Msk                 (0x01UL << PORT3_PDISC_PDIS6_Pos)                       /*!< PORT3 PDISC: PDIS6 Mask                 */\r
+#define PORT3_PDISC_PDIS7_Pos                 7                                                       /*!< PORT3 PDISC: PDIS7 Position             */\r
+#define PORT3_PDISC_PDIS7_Msk                 (0x01UL << PORT3_PDISC_PDIS7_Pos)                       /*!< PORT3 PDISC: PDIS7 Mask                 */\r
+#define PORT3_PDISC_PDIS8_Pos                 8                                                       /*!< PORT3 PDISC: PDIS8 Position             */\r
+#define PORT3_PDISC_PDIS8_Msk                 (0x01UL << PORT3_PDISC_PDIS8_Pos)                       /*!< PORT3 PDISC: PDIS8 Mask                 */\r
+#define PORT3_PDISC_PDIS9_Pos                 9                                                       /*!< PORT3 PDISC: PDIS9 Position             */\r
+#define PORT3_PDISC_PDIS9_Msk                 (0x01UL << PORT3_PDISC_PDIS9_Pos)                       /*!< PORT3 PDISC: PDIS9 Mask                 */\r
+#define PORT3_PDISC_PDIS10_Pos                10                                                      /*!< PORT3 PDISC: PDIS10 Position            */\r
+#define PORT3_PDISC_PDIS10_Msk                (0x01UL << PORT3_PDISC_PDIS10_Pos)                      /*!< PORT3 PDISC: PDIS10 Mask                */\r
+#define PORT3_PDISC_PDIS11_Pos                11                                                      /*!< PORT3 PDISC: PDIS11 Position            */\r
+#define PORT3_PDISC_PDIS11_Msk                (0x01UL << PORT3_PDISC_PDIS11_Pos)                      /*!< PORT3 PDISC: PDIS11 Mask                */\r
+#define PORT3_PDISC_PDIS12_Pos                12                                                      /*!< PORT3 PDISC: PDIS12 Position            */\r
+#define PORT3_PDISC_PDIS12_Msk                (0x01UL << PORT3_PDISC_PDIS12_Pos)                      /*!< PORT3 PDISC: PDIS12 Mask                */\r
+#define PORT3_PDISC_PDIS13_Pos                13                                                      /*!< PORT3 PDISC: PDIS13 Position            */\r
+#define PORT3_PDISC_PDIS13_Msk                (0x01UL << PORT3_PDISC_PDIS13_Pos)                      /*!< PORT3 PDISC: PDIS13 Mask                */\r
+#define PORT3_PDISC_PDIS14_Pos                14                                                      /*!< PORT3 PDISC: PDIS14 Position            */\r
+#define PORT3_PDISC_PDIS14_Msk                (0x01UL << PORT3_PDISC_PDIS14_Pos)                      /*!< PORT3 PDISC: PDIS14 Mask                */\r
+#define PORT3_PDISC_PDIS15_Pos                15                                                      /*!< PORT3 PDISC: PDIS15 Position            */\r
+#define PORT3_PDISC_PDIS15_Msk                (0x01UL << PORT3_PDISC_PDIS15_Pos)                      /*!< PORT3 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT3_PPS  --------------------------------- */\r
+#define PORT3_PPS_PPS0_Pos                    0                                                       /*!< PORT3 PPS: PPS0 Position                */\r
+#define PORT3_PPS_PPS0_Msk                    (0x01UL << PORT3_PPS_PPS0_Pos)                          /*!< PORT3 PPS: PPS0 Mask                    */\r
+#define PORT3_PPS_PPS1_Pos                    1                                                       /*!< PORT3 PPS: PPS1 Position                */\r
+#define PORT3_PPS_PPS1_Msk                    (0x01UL << PORT3_PPS_PPS1_Pos)                          /*!< PORT3 PPS: PPS1 Mask                    */\r
+#define PORT3_PPS_PPS2_Pos                    2                                                       /*!< PORT3 PPS: PPS2 Position                */\r
+#define PORT3_PPS_PPS2_Msk                    (0x01UL << PORT3_PPS_PPS2_Pos)                          /*!< PORT3 PPS: PPS2 Mask                    */\r
+#define PORT3_PPS_PPS3_Pos                    3                                                       /*!< PORT3 PPS: PPS3 Position                */\r
+#define PORT3_PPS_PPS3_Msk                    (0x01UL << PORT3_PPS_PPS3_Pos)                          /*!< PORT3 PPS: PPS3 Mask                    */\r
+#define PORT3_PPS_PPS4_Pos                    4                                                       /*!< PORT3 PPS: PPS4 Position                */\r
+#define PORT3_PPS_PPS4_Msk                    (0x01UL << PORT3_PPS_PPS4_Pos)                          /*!< PORT3 PPS: PPS4 Mask                    */\r
+#define PORT3_PPS_PPS5_Pos                    5                                                       /*!< PORT3 PPS: PPS5 Position                */\r
+#define PORT3_PPS_PPS5_Msk                    (0x01UL << PORT3_PPS_PPS5_Pos)                          /*!< PORT3 PPS: PPS5 Mask                    */\r
+#define PORT3_PPS_PPS6_Pos                    6                                                       /*!< PORT3 PPS: PPS6 Position                */\r
+#define PORT3_PPS_PPS6_Msk                    (0x01UL << PORT3_PPS_PPS6_Pos)                          /*!< PORT3 PPS: PPS6 Mask                    */\r
+#define PORT3_PPS_PPS7_Pos                    7                                                       /*!< PORT3 PPS: PPS7 Position                */\r
+#define PORT3_PPS_PPS7_Msk                    (0x01UL << PORT3_PPS_PPS7_Pos)                          /*!< PORT3 PPS: PPS7 Mask                    */\r
+#define PORT3_PPS_PPS8_Pos                    8                                                       /*!< PORT3 PPS: PPS8 Position                */\r
+#define PORT3_PPS_PPS8_Msk                    (0x01UL << PORT3_PPS_PPS8_Pos)                          /*!< PORT3 PPS: PPS8 Mask                    */\r
+#define PORT3_PPS_PPS9_Pos                    9                                                       /*!< PORT3 PPS: PPS9 Position                */\r
+#define PORT3_PPS_PPS9_Msk                    (0x01UL << PORT3_PPS_PPS9_Pos)                          /*!< PORT3 PPS: PPS9 Mask                    */\r
+#define PORT3_PPS_PPS10_Pos                   10                                                      /*!< PORT3 PPS: PPS10 Position               */\r
+#define PORT3_PPS_PPS10_Msk                   (0x01UL << PORT3_PPS_PPS10_Pos)                         /*!< PORT3 PPS: PPS10 Mask                   */\r
+#define PORT3_PPS_PPS11_Pos                   11                                                      /*!< PORT3 PPS: PPS11 Position               */\r
+#define PORT3_PPS_PPS11_Msk                   (0x01UL << PORT3_PPS_PPS11_Pos)                         /*!< PORT3 PPS: PPS11 Mask                   */\r
+#define PORT3_PPS_PPS12_Pos                   12                                                      /*!< PORT3 PPS: PPS12 Position               */\r
+#define PORT3_PPS_PPS12_Msk                   (0x01UL << PORT3_PPS_PPS12_Pos)                         /*!< PORT3 PPS: PPS12 Mask                   */\r
+#define PORT3_PPS_PPS13_Pos                   13                                                      /*!< PORT3 PPS: PPS13 Position               */\r
+#define PORT3_PPS_PPS13_Msk                   (0x01UL << PORT3_PPS_PPS13_Pos)                         /*!< PORT3 PPS: PPS13 Mask                   */\r
+#define PORT3_PPS_PPS14_Pos                   14                                                      /*!< PORT3 PPS: PPS14 Position               */\r
+#define PORT3_PPS_PPS14_Msk                   (0x01UL << PORT3_PPS_PPS14_Pos)                         /*!< PORT3 PPS: PPS14 Mask                   */\r
+#define PORT3_PPS_PPS15_Pos                   15                                                      /*!< PORT3 PPS: PPS15 Position               */\r
+#define PORT3_PPS_PPS15_Msk                   (0x01UL << PORT3_PPS_PPS15_Pos)                         /*!< PORT3 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT3_HWSEL  -------------------------------- */\r
+#define PORT3_HWSEL_HW0_Pos                   0                                                       /*!< PORT3 HWSEL: HW0 Position               */\r
+#define PORT3_HWSEL_HW0_Msk                   (0x03UL << PORT3_HWSEL_HW0_Pos)                         /*!< PORT3 HWSEL: HW0 Mask                   */\r
+#define PORT3_HWSEL_HW1_Pos                   2                                                       /*!< PORT3 HWSEL: HW1 Position               */\r
+#define PORT3_HWSEL_HW1_Msk                   (0x03UL << PORT3_HWSEL_HW1_Pos)                         /*!< PORT3 HWSEL: HW1 Mask                   */\r
+#define PORT3_HWSEL_HW2_Pos                   4                                                       /*!< PORT3 HWSEL: HW2 Position               */\r
+#define PORT3_HWSEL_HW2_Msk                   (0x03UL << PORT3_HWSEL_HW2_Pos)                         /*!< PORT3 HWSEL: HW2 Mask                   */\r
+#define PORT3_HWSEL_HW3_Pos                   6                                                       /*!< PORT3 HWSEL: HW3 Position               */\r
+#define PORT3_HWSEL_HW3_Msk                   (0x03UL << PORT3_HWSEL_HW3_Pos)                         /*!< PORT3 HWSEL: HW3 Mask                   */\r
+#define PORT3_HWSEL_HW4_Pos                   8                                                       /*!< PORT3 HWSEL: HW4 Position               */\r
+#define PORT3_HWSEL_HW4_Msk                   (0x03UL << PORT3_HWSEL_HW4_Pos)                         /*!< PORT3 HWSEL: HW4 Mask                   */\r
+#define PORT3_HWSEL_HW5_Pos                   10                                                      /*!< PORT3 HWSEL: HW5 Position               */\r
+#define PORT3_HWSEL_HW5_Msk                   (0x03UL << PORT3_HWSEL_HW5_Pos)                         /*!< PORT3 HWSEL: HW5 Mask                   */\r
+#define PORT3_HWSEL_HW6_Pos                   12                                                      /*!< PORT3 HWSEL: HW6 Position               */\r
+#define PORT3_HWSEL_HW6_Msk                   (0x03UL << PORT3_HWSEL_HW6_Pos)                         /*!< PORT3 HWSEL: HW6 Mask                   */\r
+#define PORT3_HWSEL_HW7_Pos                   14                                                      /*!< PORT3 HWSEL: HW7 Position               */\r
+#define PORT3_HWSEL_HW7_Msk                   (0x03UL << PORT3_HWSEL_HW7_Pos)                         /*!< PORT3 HWSEL: HW7 Mask                   */\r
+#define PORT3_HWSEL_HW8_Pos                   16                                                      /*!< PORT3 HWSEL: HW8 Position               */\r
+#define PORT3_HWSEL_HW8_Msk                   (0x03UL << PORT3_HWSEL_HW8_Pos)                         /*!< PORT3 HWSEL: HW8 Mask                   */\r
+#define PORT3_HWSEL_HW9_Pos                   18                                                      /*!< PORT3 HWSEL: HW9 Position               */\r
+#define PORT3_HWSEL_HW9_Msk                   (0x03UL << PORT3_HWSEL_HW9_Pos)                         /*!< PORT3 HWSEL: HW9 Mask                   */\r
+#define PORT3_HWSEL_HW10_Pos                  20                                                      /*!< PORT3 HWSEL: HW10 Position              */\r
+#define PORT3_HWSEL_HW10_Msk                  (0x03UL << PORT3_HWSEL_HW10_Pos)                        /*!< PORT3 HWSEL: HW10 Mask                  */\r
+#define PORT3_HWSEL_HW11_Pos                  22                                                      /*!< PORT3 HWSEL: HW11 Position              */\r
+#define PORT3_HWSEL_HW11_Msk                  (0x03UL << PORT3_HWSEL_HW11_Pos)                        /*!< PORT3 HWSEL: HW11 Mask                  */\r
+#define PORT3_HWSEL_HW12_Pos                  24                                                      /*!< PORT3 HWSEL: HW12 Position              */\r
+#define PORT3_HWSEL_HW12_Msk                  (0x03UL << PORT3_HWSEL_HW12_Pos)                        /*!< PORT3 HWSEL: HW12 Mask                  */\r
+#define PORT3_HWSEL_HW13_Pos                  26                                                      /*!< PORT3 HWSEL: HW13 Position              */\r
+#define PORT3_HWSEL_HW13_Msk                  (0x03UL << PORT3_HWSEL_HW13_Pos)                        /*!< PORT3 HWSEL: HW13 Mask                  */\r
+#define PORT3_HWSEL_HW14_Pos                  28                                                      /*!< PORT3 HWSEL: HW14 Position              */\r
+#define PORT3_HWSEL_HW14_Msk                  (0x03UL << PORT3_HWSEL_HW14_Pos)                        /*!< PORT3 HWSEL: HW14 Mask                  */\r
+#define PORT3_HWSEL_HW15_Pos                  30                                                      /*!< PORT3 HWSEL: HW15 Position              */\r
+#define PORT3_HWSEL_HW15_Msk                  (0x03UL << PORT3_HWSEL_HW15_Pos)                        /*!< PORT3 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT14' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  PORT14_OUT  --------------------------------- */\r
+#define PORT14_OUT_P0_Pos                     0                                                       /*!< PORT14 OUT: P0 Position                 */\r
+#define PORT14_OUT_P0_Msk                     (0x01UL << PORT14_OUT_P0_Pos)                           /*!< PORT14 OUT: P0 Mask                     */\r
+#define PORT14_OUT_P1_Pos                     1                                                       /*!< PORT14 OUT: P1 Position                 */\r
+#define PORT14_OUT_P1_Msk                     (0x01UL << PORT14_OUT_P1_Pos)                           /*!< PORT14 OUT: P1 Mask                     */\r
+#define PORT14_OUT_P2_Pos                     2                                                       /*!< PORT14 OUT: P2 Position                 */\r
+#define PORT14_OUT_P2_Msk                     (0x01UL << PORT14_OUT_P2_Pos)                           /*!< PORT14 OUT: P2 Mask                     */\r
+#define PORT14_OUT_P3_Pos                     3                                                       /*!< PORT14 OUT: P3 Position                 */\r
+#define PORT14_OUT_P3_Msk                     (0x01UL << PORT14_OUT_P3_Pos)                           /*!< PORT14 OUT: P3 Mask                     */\r
+#define PORT14_OUT_P4_Pos                     4                                                       /*!< PORT14 OUT: P4 Position                 */\r
+#define PORT14_OUT_P4_Msk                     (0x01UL << PORT14_OUT_P4_Pos)                           /*!< PORT14 OUT: P4 Mask                     */\r
+#define PORT14_OUT_P5_Pos                     5                                                       /*!< PORT14 OUT: P5 Position                 */\r
+#define PORT14_OUT_P5_Msk                     (0x01UL << PORT14_OUT_P5_Pos)                           /*!< PORT14 OUT: P5 Mask                     */\r
+#define PORT14_OUT_P6_Pos                     6                                                       /*!< PORT14 OUT: P6 Position                 */\r
+#define PORT14_OUT_P6_Msk                     (0x01UL << PORT14_OUT_P6_Pos)                           /*!< PORT14 OUT: P6 Mask                     */\r
+#define PORT14_OUT_P7_Pos                     7                                                       /*!< PORT14 OUT: P7 Position                 */\r
+#define PORT14_OUT_P7_Msk                     (0x01UL << PORT14_OUT_P7_Pos)                           /*!< PORT14 OUT: P7 Mask                     */\r
+#define PORT14_OUT_P8_Pos                     8                                                       /*!< PORT14 OUT: P8 Position                 */\r
+#define PORT14_OUT_P8_Msk                     (0x01UL << PORT14_OUT_P8_Pos)                           /*!< PORT14 OUT: P8 Mask                     */\r
+#define PORT14_OUT_P9_Pos                     9                                                       /*!< PORT14 OUT: P9 Position                 */\r
+#define PORT14_OUT_P9_Msk                     (0x01UL << PORT14_OUT_P9_Pos)                           /*!< PORT14 OUT: P9 Mask                     */\r
+#define PORT14_OUT_P10_Pos                    10                                                      /*!< PORT14 OUT: P10 Position                */\r
+#define PORT14_OUT_P10_Msk                    (0x01UL << PORT14_OUT_P10_Pos)                          /*!< PORT14 OUT: P10 Mask                    */\r
+#define PORT14_OUT_P11_Pos                    11                                                      /*!< PORT14 OUT: P11 Position                */\r
+#define PORT14_OUT_P11_Msk                    (0x01UL << PORT14_OUT_P11_Pos)                          /*!< PORT14 OUT: P11 Mask                    */\r
+#define PORT14_OUT_P12_Pos                    12                                                      /*!< PORT14 OUT: P12 Position                */\r
+#define PORT14_OUT_P12_Msk                    (0x01UL << PORT14_OUT_P12_Pos)                          /*!< PORT14 OUT: P12 Mask                    */\r
+#define PORT14_OUT_P13_Pos                    13                                                      /*!< PORT14 OUT: P13 Position                */\r
+#define PORT14_OUT_P13_Msk                    (0x01UL << PORT14_OUT_P13_Pos)                          /*!< PORT14 OUT: P13 Mask                    */\r
+#define PORT14_OUT_P14_Pos                    14                                                      /*!< PORT14 OUT: P14 Position                */\r
+#define PORT14_OUT_P14_Msk                    (0x01UL << PORT14_OUT_P14_Pos)                          /*!< PORT14 OUT: P14 Mask                    */\r
+#define PORT14_OUT_P15_Pos                    15                                                      /*!< PORT14 OUT: P15 Position                */\r
+#define PORT14_OUT_P15_Msk                    (0x01UL << PORT14_OUT_P15_Pos)                          /*!< PORT14 OUT: P15 Mask                    */\r
+\r
+/* ---------------------------------  PORT14_OMR  --------------------------------- */\r
+#define PORT14_OMR_PS0_Pos                    0                                                       /*!< PORT14 OMR: PS0 Position                */\r
+#define PORT14_OMR_PS0_Msk                    (0x01UL << PORT14_OMR_PS0_Pos)                          /*!< PORT14 OMR: PS0 Mask                    */\r
+#define PORT14_OMR_PS1_Pos                    1                                                       /*!< PORT14 OMR: PS1 Position                */\r
+#define PORT14_OMR_PS1_Msk                    (0x01UL << PORT14_OMR_PS1_Pos)                          /*!< PORT14 OMR: PS1 Mask                    */\r
+#define PORT14_OMR_PS2_Pos                    2                                                       /*!< PORT14 OMR: PS2 Position                */\r
+#define PORT14_OMR_PS2_Msk                    (0x01UL << PORT14_OMR_PS2_Pos)                          /*!< PORT14 OMR: PS2 Mask                    */\r
+#define PORT14_OMR_PS3_Pos                    3                                                       /*!< PORT14 OMR: PS3 Position                */\r
+#define PORT14_OMR_PS3_Msk                    (0x01UL << PORT14_OMR_PS3_Pos)                          /*!< PORT14 OMR: PS3 Mask                    */\r
+#define PORT14_OMR_PS4_Pos                    4                                                       /*!< PORT14 OMR: PS4 Position                */\r
+#define PORT14_OMR_PS4_Msk                    (0x01UL << PORT14_OMR_PS4_Pos)                          /*!< PORT14 OMR: PS4 Mask                    */\r
+#define PORT14_OMR_PS5_Pos                    5                                                       /*!< PORT14 OMR: PS5 Position                */\r
+#define PORT14_OMR_PS5_Msk                    (0x01UL << PORT14_OMR_PS5_Pos)                          /*!< PORT14 OMR: PS5 Mask                    */\r
+#define PORT14_OMR_PS6_Pos                    6                                                       /*!< PORT14 OMR: PS6 Position                */\r
+#define PORT14_OMR_PS6_Msk                    (0x01UL << PORT14_OMR_PS6_Pos)                          /*!< PORT14 OMR: PS6 Mask                    */\r
+#define PORT14_OMR_PS7_Pos                    7                                                       /*!< PORT14 OMR: PS7 Position                */\r
+#define PORT14_OMR_PS7_Msk                    (0x01UL << PORT14_OMR_PS7_Pos)                          /*!< PORT14 OMR: PS7 Mask                    */\r
+#define PORT14_OMR_PS8_Pos                    8                                                       /*!< PORT14 OMR: PS8 Position                */\r
+#define PORT14_OMR_PS8_Msk                    (0x01UL << PORT14_OMR_PS8_Pos)                          /*!< PORT14 OMR: PS8 Mask                    */\r
+#define PORT14_OMR_PS9_Pos                    9                                                       /*!< PORT14 OMR: PS9 Position                */\r
+#define PORT14_OMR_PS9_Msk                    (0x01UL << PORT14_OMR_PS9_Pos)                          /*!< PORT14 OMR: PS9 Mask                    */\r
+#define PORT14_OMR_PS10_Pos                   10                                                      /*!< PORT14 OMR: PS10 Position               */\r
+#define PORT14_OMR_PS10_Msk                   (0x01UL << PORT14_OMR_PS10_Pos)                         /*!< PORT14 OMR: PS10 Mask                   */\r
+#define PORT14_OMR_PS11_Pos                   11                                                      /*!< PORT14 OMR: PS11 Position               */\r
+#define PORT14_OMR_PS11_Msk                   (0x01UL << PORT14_OMR_PS11_Pos)                         /*!< PORT14 OMR: PS11 Mask                   */\r
+#define PORT14_OMR_PS12_Pos                   12                                                      /*!< PORT14 OMR: PS12 Position               */\r
+#define PORT14_OMR_PS12_Msk                   (0x01UL << PORT14_OMR_PS12_Pos)                         /*!< PORT14 OMR: PS12 Mask                   */\r
+#define PORT14_OMR_PS13_Pos                   13                                                      /*!< PORT14 OMR: PS13 Position               */\r
+#define PORT14_OMR_PS13_Msk                   (0x01UL << PORT14_OMR_PS13_Pos)                         /*!< PORT14 OMR: PS13 Mask                   */\r
+#define PORT14_OMR_PS14_Pos                   14                                                      /*!< PORT14 OMR: PS14 Position               */\r
+#define PORT14_OMR_PS14_Msk                   (0x01UL << PORT14_OMR_PS14_Pos)                         /*!< PORT14 OMR: PS14 Mask                   */\r
+#define PORT14_OMR_PS15_Pos                   15                                                      /*!< PORT14 OMR: PS15 Position               */\r
+#define PORT14_OMR_PS15_Msk                   (0x01UL << PORT14_OMR_PS15_Pos)                         /*!< PORT14 OMR: PS15 Mask                   */\r
+#define PORT14_OMR_PR0_Pos                    16                                                      /*!< PORT14 OMR: PR0 Position                */\r
+#define PORT14_OMR_PR0_Msk                    (0x01UL << PORT14_OMR_PR0_Pos)                          /*!< PORT14 OMR: PR0 Mask                    */\r
+#define PORT14_OMR_PR1_Pos                    17                                                      /*!< PORT14 OMR: PR1 Position                */\r
+#define PORT14_OMR_PR1_Msk                    (0x01UL << PORT14_OMR_PR1_Pos)                          /*!< PORT14 OMR: PR1 Mask                    */\r
+#define PORT14_OMR_PR2_Pos                    18                                                      /*!< PORT14 OMR: PR2 Position                */\r
+#define PORT14_OMR_PR2_Msk                    (0x01UL << PORT14_OMR_PR2_Pos)                          /*!< PORT14 OMR: PR2 Mask                    */\r
+#define PORT14_OMR_PR3_Pos                    19                                                      /*!< PORT14 OMR: PR3 Position                */\r
+#define PORT14_OMR_PR3_Msk                    (0x01UL << PORT14_OMR_PR3_Pos)                          /*!< PORT14 OMR: PR3 Mask                    */\r
+#define PORT14_OMR_PR4_Pos                    20                                                      /*!< PORT14 OMR: PR4 Position                */\r
+#define PORT14_OMR_PR4_Msk                    (0x01UL << PORT14_OMR_PR4_Pos)                          /*!< PORT14 OMR: PR4 Mask                    */\r
+#define PORT14_OMR_PR5_Pos                    21                                                      /*!< PORT14 OMR: PR5 Position                */\r
+#define PORT14_OMR_PR5_Msk                    (0x01UL << PORT14_OMR_PR5_Pos)                          /*!< PORT14 OMR: PR5 Mask                    */\r
+#define PORT14_OMR_PR6_Pos                    22                                                      /*!< PORT14 OMR: PR6 Position                */\r
+#define PORT14_OMR_PR6_Msk                    (0x01UL << PORT14_OMR_PR6_Pos)                          /*!< PORT14 OMR: PR6 Mask                    */\r
+#define PORT14_OMR_PR7_Pos                    23                                                      /*!< PORT14 OMR: PR7 Position                */\r
+#define PORT14_OMR_PR7_Msk                    (0x01UL << PORT14_OMR_PR7_Pos)                          /*!< PORT14 OMR: PR7 Mask                    */\r
+#define PORT14_OMR_PR8_Pos                    24                                                      /*!< PORT14 OMR: PR8 Position                */\r
+#define PORT14_OMR_PR8_Msk                    (0x01UL << PORT14_OMR_PR8_Pos)                          /*!< PORT14 OMR: PR8 Mask                    */\r
+#define PORT14_OMR_PR9_Pos                    25                                                      /*!< PORT14 OMR: PR9 Position                */\r
+#define PORT14_OMR_PR9_Msk                    (0x01UL << PORT14_OMR_PR9_Pos)                          /*!< PORT14 OMR: PR9 Mask                    */\r
+#define PORT14_OMR_PR10_Pos                   26                                                      /*!< PORT14 OMR: PR10 Position               */\r
+#define PORT14_OMR_PR10_Msk                   (0x01UL << PORT14_OMR_PR10_Pos)                         /*!< PORT14 OMR: PR10 Mask                   */\r
+#define PORT14_OMR_PR11_Pos                   27                                                      /*!< PORT14 OMR: PR11 Position               */\r
+#define PORT14_OMR_PR11_Msk                   (0x01UL << PORT14_OMR_PR11_Pos)                         /*!< PORT14 OMR: PR11 Mask                   */\r
+#define PORT14_OMR_PR12_Pos                   28                                                      /*!< PORT14 OMR: PR12 Position               */\r
+#define PORT14_OMR_PR12_Msk                   (0x01UL << PORT14_OMR_PR12_Pos)                         /*!< PORT14 OMR: PR12 Mask                   */\r
+#define PORT14_OMR_PR13_Pos                   29                                                      /*!< PORT14 OMR: PR13 Position               */\r
+#define PORT14_OMR_PR13_Msk                   (0x01UL << PORT14_OMR_PR13_Pos)                         /*!< PORT14 OMR: PR13 Mask                   */\r
+#define PORT14_OMR_PR14_Pos                   30                                                      /*!< PORT14 OMR: PR14 Position               */\r
+#define PORT14_OMR_PR14_Msk                   (0x01UL << PORT14_OMR_PR14_Pos)                         /*!< PORT14 OMR: PR14 Mask                   */\r
+#define PORT14_OMR_PR15_Pos                   31                                                      /*!< PORT14 OMR: PR15 Position               */\r
+#define PORT14_OMR_PR15_Msk                   (0x01UL << PORT14_OMR_PR15_Pos)                         /*!< PORT14 OMR: PR15 Mask                   */\r
+\r
+/* --------------------------------  PORT14_IOCR0  -------------------------------- */\r
+#define PORT14_IOCR0_PC0_Pos                  3                                                       /*!< PORT14 IOCR0: PC0 Position              */\r
+#define PORT14_IOCR0_PC0_Msk                  (0x1fUL << PORT14_IOCR0_PC0_Pos)                        /*!< PORT14 IOCR0: PC0 Mask                  */\r
+#define PORT14_IOCR0_PC1_Pos                  11                                                      /*!< PORT14 IOCR0: PC1 Position              */\r
+#define PORT14_IOCR0_PC1_Msk                  (0x1fUL << PORT14_IOCR0_PC1_Pos)                        /*!< PORT14 IOCR0: PC1 Mask                  */\r
+#define PORT14_IOCR0_PC2_Pos                  19                                                      /*!< PORT14 IOCR0: PC2 Position              */\r
+#define PORT14_IOCR0_PC2_Msk                  (0x1fUL << PORT14_IOCR0_PC2_Pos)                        /*!< PORT14 IOCR0: PC2 Mask                  */\r
+#define PORT14_IOCR0_PC3_Pos                  27                                                      /*!< PORT14 IOCR0: PC3 Position              */\r
+#define PORT14_IOCR0_PC3_Msk                  (0x1fUL << PORT14_IOCR0_PC3_Pos)                        /*!< PORT14 IOCR0: PC3 Mask                  */\r
+\r
+/* --------------------------------  PORT14_IOCR4  -------------------------------- */\r
+#define PORT14_IOCR4_PC4_Pos                  3                                                       /*!< PORT14 IOCR4: PC4 Position              */\r
+#define PORT14_IOCR4_PC4_Msk                  (0x1fUL << PORT14_IOCR4_PC4_Pos)                        /*!< PORT14 IOCR4: PC4 Mask                  */\r
+#define PORT14_IOCR4_PC5_Pos                  11                                                      /*!< PORT14 IOCR4: PC5 Position              */\r
+#define PORT14_IOCR4_PC5_Msk                  (0x1fUL << PORT14_IOCR4_PC5_Pos)                        /*!< PORT14 IOCR4: PC5 Mask                  */\r
+#define PORT14_IOCR4_PC6_Pos                  19                                                      /*!< PORT14 IOCR4: PC6 Position              */\r
+#define PORT14_IOCR4_PC6_Msk                  (0x1fUL << PORT14_IOCR4_PC6_Pos)                        /*!< PORT14 IOCR4: PC6 Mask                  */\r
+#define PORT14_IOCR4_PC7_Pos                  27                                                      /*!< PORT14 IOCR4: PC7 Position              */\r
+#define PORT14_IOCR4_PC7_Msk                  (0x1fUL << PORT14_IOCR4_PC7_Pos)                        /*!< PORT14 IOCR4: PC7 Mask                  */\r
+\r
+/* --------------------------------  PORT14_IOCR8  -------------------------------- */\r
+#define PORT14_IOCR8_PC8_Pos                  3                                                       /*!< PORT14 IOCR8: PC8 Position              */\r
+#define PORT14_IOCR8_PC8_Msk                  (0x1fUL << PORT14_IOCR8_PC8_Pos)                        /*!< PORT14 IOCR8: PC8 Mask                  */\r
+#define PORT14_IOCR8_PC9_Pos                  11                                                      /*!< PORT14 IOCR8: PC9 Position              */\r
+#define PORT14_IOCR8_PC9_Msk                  (0x1fUL << PORT14_IOCR8_PC9_Pos)                        /*!< PORT14 IOCR8: PC9 Mask                  */\r
+#define PORT14_IOCR8_PC10_Pos                 19                                                      /*!< PORT14 IOCR8: PC10 Position             */\r
+#define PORT14_IOCR8_PC10_Msk                 (0x1fUL << PORT14_IOCR8_PC10_Pos)                       /*!< PORT14 IOCR8: PC10 Mask                 */\r
+#define PORT14_IOCR8_PC11_Pos                 27                                                      /*!< PORT14 IOCR8: PC11 Position             */\r
+#define PORT14_IOCR8_PC11_Msk                 (0x1fUL << PORT14_IOCR8_PC11_Pos)                       /*!< PORT14 IOCR8: PC11 Mask                 */\r
+\r
+/* --------------------------------  PORT14_IOCR12  ------------------------------- */\r
+#define PORT14_IOCR12_PC12_Pos                3                                                       /*!< PORT14 IOCR12: PC12 Position            */\r
+#define PORT14_IOCR12_PC12_Msk                (0x1fUL << PORT14_IOCR12_PC12_Pos)                      /*!< PORT14 IOCR12: PC12 Mask                */\r
+#define PORT14_IOCR12_PC13_Pos                11                                                      /*!< PORT14 IOCR12: PC13 Position            */\r
+#define PORT14_IOCR12_PC13_Msk                (0x1fUL << PORT14_IOCR12_PC13_Pos)                      /*!< PORT14 IOCR12: PC13 Mask                */\r
+#define PORT14_IOCR12_PC14_Pos                19                                                      /*!< PORT14 IOCR12: PC14 Position            */\r
+#define PORT14_IOCR12_PC14_Msk                (0x1fUL << PORT14_IOCR12_PC14_Pos)                      /*!< PORT14 IOCR12: PC14 Mask                */\r
+#define PORT14_IOCR12_PC15_Pos                27                                                      /*!< PORT14 IOCR12: PC15 Position            */\r
+#define PORT14_IOCR12_PC15_Msk                (0x1fUL << PORT14_IOCR12_PC15_Pos)                      /*!< PORT14 IOCR12: PC15 Mask                */\r
+\r
+/* ----------------------------------  PORT14_IN  --------------------------------- */\r
+#define PORT14_IN_P0_Pos                      0                                                       /*!< PORT14 IN: P0 Position                  */\r
+#define PORT14_IN_P0_Msk                      (0x01UL << PORT14_IN_P0_Pos)                            /*!< PORT14 IN: P0 Mask                      */\r
+#define PORT14_IN_P1_Pos                      1                                                       /*!< PORT14 IN: P1 Position                  */\r
+#define PORT14_IN_P1_Msk                      (0x01UL << PORT14_IN_P1_Pos)                            /*!< PORT14 IN: P1 Mask                      */\r
+#define PORT14_IN_P2_Pos                      2                                                       /*!< PORT14 IN: P2 Position                  */\r
+#define PORT14_IN_P2_Msk                      (0x01UL << PORT14_IN_P2_Pos)                            /*!< PORT14 IN: P2 Mask                      */\r
+#define PORT14_IN_P3_Pos                      3                                                       /*!< PORT14 IN: P3 Position                  */\r
+#define PORT14_IN_P3_Msk                      (0x01UL << PORT14_IN_P3_Pos)                            /*!< PORT14 IN: P3 Mask                      */\r
+#define PORT14_IN_P4_Pos                      4                                                       /*!< PORT14 IN: P4 Position                  */\r
+#define PORT14_IN_P4_Msk                      (0x01UL << PORT14_IN_P4_Pos)                            /*!< PORT14 IN: P4 Mask                      */\r
+#define PORT14_IN_P5_Pos                      5                                                       /*!< PORT14 IN: P5 Position                  */\r
+#define PORT14_IN_P5_Msk                      (0x01UL << PORT14_IN_P5_Pos)                            /*!< PORT14 IN: P5 Mask                      */\r
+#define PORT14_IN_P6_Pos                      6                                                       /*!< PORT14 IN: P6 Position                  */\r
+#define PORT14_IN_P6_Msk                      (0x01UL << PORT14_IN_P6_Pos)                            /*!< PORT14 IN: P6 Mask                      */\r
+#define PORT14_IN_P7_Pos                      7                                                       /*!< PORT14 IN: P7 Position                  */\r
+#define PORT14_IN_P7_Msk                      (0x01UL << PORT14_IN_P7_Pos)                            /*!< PORT14 IN: P7 Mask                      */\r
+#define PORT14_IN_P8_Pos                      8                                                       /*!< PORT14 IN: P8 Position                  */\r
+#define PORT14_IN_P8_Msk                      (0x01UL << PORT14_IN_P8_Pos)                            /*!< PORT14 IN: P8 Mask                      */\r
+#define PORT14_IN_P9_Pos                      9                                                       /*!< PORT14 IN: P9 Position                  */\r
+#define PORT14_IN_P9_Msk                      (0x01UL << PORT14_IN_P9_Pos)                            /*!< PORT14 IN: P9 Mask                      */\r
+#define PORT14_IN_P10_Pos                     10                                                      /*!< PORT14 IN: P10 Position                 */\r
+#define PORT14_IN_P10_Msk                     (0x01UL << PORT14_IN_P10_Pos)                           /*!< PORT14 IN: P10 Mask                     */\r
+#define PORT14_IN_P11_Pos                     11                                                      /*!< PORT14 IN: P11 Position                 */\r
+#define PORT14_IN_P11_Msk                     (0x01UL << PORT14_IN_P11_Pos)                           /*!< PORT14 IN: P11 Mask                     */\r
+#define PORT14_IN_P12_Pos                     12                                                      /*!< PORT14 IN: P12 Position                 */\r
+#define PORT14_IN_P12_Msk                     (0x01UL << PORT14_IN_P12_Pos)                           /*!< PORT14 IN: P12 Mask                     */\r
+#define PORT14_IN_P13_Pos                     13                                                      /*!< PORT14 IN: P13 Position                 */\r
+#define PORT14_IN_P13_Msk                     (0x01UL << PORT14_IN_P13_Pos)                           /*!< PORT14 IN: P13 Mask                     */\r
+#define PORT14_IN_P14_Pos                     14                                                      /*!< PORT14 IN: P14 Position                 */\r
+#define PORT14_IN_P14_Msk                     (0x01UL << PORT14_IN_P14_Pos)                           /*!< PORT14 IN: P14 Mask                     */\r
+#define PORT14_IN_P15_Pos                     15                                                      /*!< PORT14 IN: P15 Position                 */\r
+#define PORT14_IN_P15_Msk                     (0x01UL << PORT14_IN_P15_Pos)                           /*!< PORT14 IN: P15 Mask                     */\r
+\r
+/* --------------------------------  PORT14_PDISC  -------------------------------- */\r
+#define PORT14_PDISC_PDIS0_Pos                0                                                       /*!< PORT14 PDISC: PDIS0 Position            */\r
+#define PORT14_PDISC_PDIS0_Msk                (0x01UL << PORT14_PDISC_PDIS0_Pos)                      /*!< PORT14 PDISC: PDIS0 Mask                */\r
+#define PORT14_PDISC_PDIS1_Pos                1                                                       /*!< PORT14 PDISC: PDIS1 Position            */\r
+#define PORT14_PDISC_PDIS1_Msk                (0x01UL << PORT14_PDISC_PDIS1_Pos)                      /*!< PORT14 PDISC: PDIS1 Mask                */\r
+#define PORT14_PDISC_PDIS2_Pos                2                                                       /*!< PORT14 PDISC: PDIS2 Position            */\r
+#define PORT14_PDISC_PDIS2_Msk                (0x01UL << PORT14_PDISC_PDIS2_Pos)                      /*!< PORT14 PDISC: PDIS2 Mask                */\r
+#define PORT14_PDISC_PDIS3_Pos                3                                                       /*!< PORT14 PDISC: PDIS3 Position            */\r
+#define PORT14_PDISC_PDIS3_Msk                (0x01UL << PORT14_PDISC_PDIS3_Pos)                      /*!< PORT14 PDISC: PDIS3 Mask                */\r
+#define PORT14_PDISC_PDIS4_Pos                4                                                       /*!< PORT14 PDISC: PDIS4 Position            */\r
+#define PORT14_PDISC_PDIS4_Msk                (0x01UL << PORT14_PDISC_PDIS4_Pos)                      /*!< PORT14 PDISC: PDIS4 Mask                */\r
+#define PORT14_PDISC_PDIS5_Pos                5                                                       /*!< PORT14 PDISC: PDIS5 Position            */\r
+#define PORT14_PDISC_PDIS5_Msk                (0x01UL << PORT14_PDISC_PDIS5_Pos)                      /*!< PORT14 PDISC: PDIS5 Mask                */\r
+#define PORT14_PDISC_PDIS6_Pos                6                                                       /*!< PORT14 PDISC: PDIS6 Position            */\r
+#define PORT14_PDISC_PDIS6_Msk                (0x01UL << PORT14_PDISC_PDIS6_Pos)                      /*!< PORT14 PDISC: PDIS6 Mask                */\r
+#define PORT14_PDISC_PDIS7_Pos                7                                                       /*!< PORT14 PDISC: PDIS7 Position            */\r
+#define PORT14_PDISC_PDIS7_Msk                (0x01UL << PORT14_PDISC_PDIS7_Pos)                      /*!< PORT14 PDISC: PDIS7 Mask                */\r
+#define PORT14_PDISC_PDIS8_Pos                8                                                       /*!< PORT14 PDISC: PDIS8 Position            */\r
+#define PORT14_PDISC_PDIS8_Msk                (0x01UL << PORT14_PDISC_PDIS8_Pos)                      /*!< PORT14 PDISC: PDIS8 Mask                */\r
+#define PORT14_PDISC_PDIS9_Pos                9                                                       /*!< PORT14 PDISC: PDIS9 Position            */\r
+#define PORT14_PDISC_PDIS9_Msk                (0x01UL << PORT14_PDISC_PDIS9_Pos)                      /*!< PORT14 PDISC: PDIS9 Mask                */\r
+#define PORT14_PDISC_PDIS10_Pos               10                                                      /*!< PORT14 PDISC: PDIS10 Position           */\r
+#define PORT14_PDISC_PDIS10_Msk               (0x01UL << PORT14_PDISC_PDIS10_Pos)                     /*!< PORT14 PDISC: PDIS10 Mask               */\r
+#define PORT14_PDISC_PDIS11_Pos               11                                                      /*!< PORT14 PDISC: PDIS11 Position           */\r
+#define PORT14_PDISC_PDIS11_Msk               (0x01UL << PORT14_PDISC_PDIS11_Pos)                     /*!< PORT14 PDISC: PDIS11 Mask               */\r
+#define PORT14_PDISC_PDIS12_Pos               12                                                      /*!< PORT14 PDISC: PDIS12 Position           */\r
+#define PORT14_PDISC_PDIS12_Msk               (0x01UL << PORT14_PDISC_PDIS12_Pos)                     /*!< PORT14 PDISC: PDIS12 Mask               */\r
+#define PORT14_PDISC_PDIS13_Pos               13                                                      /*!< PORT14 PDISC: PDIS13 Position           */\r
+#define PORT14_PDISC_PDIS13_Msk               (0x01UL << PORT14_PDISC_PDIS13_Pos)                     /*!< PORT14 PDISC: PDIS13 Mask               */\r
+#define PORT14_PDISC_PDIS14_Pos               14                                                      /*!< PORT14 PDISC: PDIS14 Position           */\r
+#define PORT14_PDISC_PDIS14_Msk               (0x01UL << PORT14_PDISC_PDIS14_Pos)                     /*!< PORT14 PDISC: PDIS14 Mask               */\r
+#define PORT14_PDISC_PDIS15_Pos               15                                                      /*!< PORT14 PDISC: PDIS15 Position           */\r
+#define PORT14_PDISC_PDIS15_Msk               (0x01UL << PORT14_PDISC_PDIS15_Pos)                     /*!< PORT14 PDISC: PDIS15 Mask               */\r
+\r
+/* ---------------------------------  PORT14_PPS  --------------------------------- */\r
+#define PORT14_PPS_PPS0_Pos                   0                                                       /*!< PORT14 PPS: PPS0 Position               */\r
+#define PORT14_PPS_PPS0_Msk                   (0x01UL << PORT14_PPS_PPS0_Pos)                         /*!< PORT14 PPS: PPS0 Mask                   */\r
+#define PORT14_PPS_PPS1_Pos                   1                                                       /*!< PORT14 PPS: PPS1 Position               */\r
+#define PORT14_PPS_PPS1_Msk                   (0x01UL << PORT14_PPS_PPS1_Pos)                         /*!< PORT14 PPS: PPS1 Mask                   */\r
+#define PORT14_PPS_PPS2_Pos                   2                                                       /*!< PORT14 PPS: PPS2 Position               */\r
+#define PORT14_PPS_PPS2_Msk                   (0x01UL << PORT14_PPS_PPS2_Pos)                         /*!< PORT14 PPS: PPS2 Mask                   */\r
+#define PORT14_PPS_PPS3_Pos                   3                                                       /*!< PORT14 PPS: PPS3 Position               */\r
+#define PORT14_PPS_PPS3_Msk                   (0x01UL << PORT14_PPS_PPS3_Pos)                         /*!< PORT14 PPS: PPS3 Mask                   */\r
+#define PORT14_PPS_PPS4_Pos                   4                                                       /*!< PORT14 PPS: PPS4 Position               */\r
+#define PORT14_PPS_PPS4_Msk                   (0x01UL << PORT14_PPS_PPS4_Pos)                         /*!< PORT14 PPS: PPS4 Mask                   */\r
+#define PORT14_PPS_PPS5_Pos                   5                                                       /*!< PORT14 PPS: PPS5 Position               */\r
+#define PORT14_PPS_PPS5_Msk                   (0x01UL << PORT14_PPS_PPS5_Pos)                         /*!< PORT14 PPS: PPS5 Mask                   */\r
+#define PORT14_PPS_PPS6_Pos                   6                                                       /*!< PORT14 PPS: PPS6 Position               */\r
+#define PORT14_PPS_PPS6_Msk                   (0x01UL << PORT14_PPS_PPS6_Pos)                         /*!< PORT14 PPS: PPS6 Mask                   */\r
+#define PORT14_PPS_PPS7_Pos                   7                                                       /*!< PORT14 PPS: PPS7 Position               */\r
+#define PORT14_PPS_PPS7_Msk                   (0x01UL << PORT14_PPS_PPS7_Pos)                         /*!< PORT14 PPS: PPS7 Mask                   */\r
+#define PORT14_PPS_PPS8_Pos                   8                                                       /*!< PORT14 PPS: PPS8 Position               */\r
+#define PORT14_PPS_PPS8_Msk                   (0x01UL << PORT14_PPS_PPS8_Pos)                         /*!< PORT14 PPS: PPS8 Mask                   */\r
+#define PORT14_PPS_PPS9_Pos                   9                                                       /*!< PORT14 PPS: PPS9 Position               */\r
+#define PORT14_PPS_PPS9_Msk                   (0x01UL << PORT14_PPS_PPS9_Pos)                         /*!< PORT14 PPS: PPS9 Mask                   */\r
+#define PORT14_PPS_PPS10_Pos                  10                                                      /*!< PORT14 PPS: PPS10 Position              */\r
+#define PORT14_PPS_PPS10_Msk                  (0x01UL << PORT14_PPS_PPS10_Pos)                        /*!< PORT14 PPS: PPS10 Mask                  */\r
+#define PORT14_PPS_PPS11_Pos                  11                                                      /*!< PORT14 PPS: PPS11 Position              */\r
+#define PORT14_PPS_PPS11_Msk                  (0x01UL << PORT14_PPS_PPS11_Pos)                        /*!< PORT14 PPS: PPS11 Mask                  */\r
+#define PORT14_PPS_PPS12_Pos                  12                                                      /*!< PORT14 PPS: PPS12 Position              */\r
+#define PORT14_PPS_PPS12_Msk                  (0x01UL << PORT14_PPS_PPS12_Pos)                        /*!< PORT14 PPS: PPS12 Mask                  */\r
+#define PORT14_PPS_PPS13_Pos                  13                                                      /*!< PORT14 PPS: PPS13 Position              */\r
+#define PORT14_PPS_PPS13_Msk                  (0x01UL << PORT14_PPS_PPS13_Pos)                        /*!< PORT14 PPS: PPS13 Mask                  */\r
+#define PORT14_PPS_PPS14_Pos                  14                                                      /*!< PORT14 PPS: PPS14 Position              */\r
+#define PORT14_PPS_PPS14_Msk                  (0x01UL << PORT14_PPS_PPS14_Pos)                        /*!< PORT14 PPS: PPS14 Mask                  */\r
+#define PORT14_PPS_PPS15_Pos                  15                                                      /*!< PORT14 PPS: PPS15 Position              */\r
+#define PORT14_PPS_PPS15_Msk                  (0x01UL << PORT14_PPS_PPS15_Pos)                        /*!< PORT14 PPS: PPS15 Mask                  */\r
+\r
+/* --------------------------------  PORT14_HWSEL  -------------------------------- */\r
+#define PORT14_HWSEL_HW0_Pos                  0                                                       /*!< PORT14 HWSEL: HW0 Position              */\r
+#define PORT14_HWSEL_HW0_Msk                  (0x03UL << PORT14_HWSEL_HW0_Pos)                        /*!< PORT14 HWSEL: HW0 Mask                  */\r
+#define PORT14_HWSEL_HW1_Pos                  2                                                       /*!< PORT14 HWSEL: HW1 Position              */\r
+#define PORT14_HWSEL_HW1_Msk                  (0x03UL << PORT14_HWSEL_HW1_Pos)                        /*!< PORT14 HWSEL: HW1 Mask                  */\r
+#define PORT14_HWSEL_HW2_Pos                  4                                                       /*!< PORT14 HWSEL: HW2 Position              */\r
+#define PORT14_HWSEL_HW2_Msk                  (0x03UL << PORT14_HWSEL_HW2_Pos)                        /*!< PORT14 HWSEL: HW2 Mask                  */\r
+#define PORT14_HWSEL_HW3_Pos                  6                                                       /*!< PORT14 HWSEL: HW3 Position              */\r
+#define PORT14_HWSEL_HW3_Msk                  (0x03UL << PORT14_HWSEL_HW3_Pos)                        /*!< PORT14 HWSEL: HW3 Mask                  */\r
+#define PORT14_HWSEL_HW4_Pos                  8                                                       /*!< PORT14 HWSEL: HW4 Position              */\r
+#define PORT14_HWSEL_HW4_Msk                  (0x03UL << PORT14_HWSEL_HW4_Pos)                        /*!< PORT14 HWSEL: HW4 Mask                  */\r
+#define PORT14_HWSEL_HW5_Pos                  10                                                      /*!< PORT14 HWSEL: HW5 Position              */\r
+#define PORT14_HWSEL_HW5_Msk                  (0x03UL << PORT14_HWSEL_HW5_Pos)                        /*!< PORT14 HWSEL: HW5 Mask                  */\r
+#define PORT14_HWSEL_HW6_Pos                  12                                                      /*!< PORT14 HWSEL: HW6 Position              */\r
+#define PORT14_HWSEL_HW6_Msk                  (0x03UL << PORT14_HWSEL_HW6_Pos)                        /*!< PORT14 HWSEL: HW6 Mask                  */\r
+#define PORT14_HWSEL_HW7_Pos                  14                                                      /*!< PORT14 HWSEL: HW7 Position              */\r
+#define PORT14_HWSEL_HW7_Msk                  (0x03UL << PORT14_HWSEL_HW7_Pos)                        /*!< PORT14 HWSEL: HW7 Mask                  */\r
+#define PORT14_HWSEL_HW8_Pos                  16                                                      /*!< PORT14 HWSEL: HW8 Position              */\r
+#define PORT14_HWSEL_HW8_Msk                  (0x03UL << PORT14_HWSEL_HW8_Pos)                        /*!< PORT14 HWSEL: HW8 Mask                  */\r
+#define PORT14_HWSEL_HW9_Pos                  18                                                      /*!< PORT14 HWSEL: HW9 Position              */\r
+#define PORT14_HWSEL_HW9_Msk                  (0x03UL << PORT14_HWSEL_HW9_Pos)                        /*!< PORT14 HWSEL: HW9 Mask                  */\r
+#define PORT14_HWSEL_HW10_Pos                 20                                                      /*!< PORT14 HWSEL: HW10 Position             */\r
+#define PORT14_HWSEL_HW10_Msk                 (0x03UL << PORT14_HWSEL_HW10_Pos)                       /*!< PORT14 HWSEL: HW10 Mask                 */\r
+#define PORT14_HWSEL_HW11_Pos                 22                                                      /*!< PORT14 HWSEL: HW11 Position             */\r
+#define PORT14_HWSEL_HW11_Msk                 (0x03UL << PORT14_HWSEL_HW11_Pos)                       /*!< PORT14 HWSEL: HW11 Mask                 */\r
+#define PORT14_HWSEL_HW12_Pos                 24                                                      /*!< PORT14 HWSEL: HW12 Position             */\r
+#define PORT14_HWSEL_HW12_Msk                 (0x03UL << PORT14_HWSEL_HW12_Pos)                       /*!< PORT14 HWSEL: HW12 Mask                 */\r
+#define PORT14_HWSEL_HW13_Pos                 26                                                      /*!< PORT14 HWSEL: HW13 Position             */\r
+#define PORT14_HWSEL_HW13_Msk                 (0x03UL << PORT14_HWSEL_HW13_Pos)                       /*!< PORT14 HWSEL: HW13 Mask                 */\r
+#define PORT14_HWSEL_HW14_Pos                 28                                                      /*!< PORT14 HWSEL: HW14 Position             */\r
+#define PORT14_HWSEL_HW14_Msk                 (0x03UL << PORT14_HWSEL_HW14_Pos)                       /*!< PORT14 HWSEL: HW14 Mask                 */\r
+#define PORT14_HWSEL_HW15_Pos                 30                                                      /*!< PORT14 HWSEL: HW15 Position             */\r
+#define PORT14_HWSEL_HW15_Msk                 (0x03UL << PORT14_HWSEL_HW15_Pos)                       /*!< PORT14 HWSEL: HW15 Mask                 */\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              Peripheral memory map             ================ */\r
+/* ================================================================================ */\r
+\r
+#define PPB_BASE                        0xE000E000UL\r
+#define DLR_BASE                        0x50004900UL\r
+#define ERU0_BASE                       0x50004800UL\r
+#define ERU1_BASE                       0x40044000UL\r
+#define GPDMA0_BASE                     0x500142C0UL\r
+#define GPDMA0_CH0_BASE                 0x50014000UL\r
+#define GPDMA0_CH1_BASE                 0x50014058UL\r
+#define GPDMA0_CH2_BASE                 0x500140B0UL\r
+#define GPDMA0_CH3_BASE                 0x50014108UL\r
+#define GPDMA0_CH4_BASE                 0x50014160UL\r
+#define GPDMA0_CH5_BASE                 0x500141B8UL\r
+#define GPDMA0_CH6_BASE                 0x50014210UL\r
+#define GPDMA0_CH7_BASE                 0x50014268UL\r
+#define FCE_BASE                        0x50020000UL\r
+#define FCE_KE0_BASE                    0x50020020UL\r
+#define FCE_KE1_BASE                    0x50020040UL\r
+#define FCE_KE2_BASE                    0x50020060UL\r
+#define FCE_KE3_BASE                    0x50020080UL\r
+#define PBA0_BASE                       0x40000000UL\r
+#define PBA1_BASE                       0x48000000UL\r
+#define FLASH0_BASE                     0x58001000UL\r
+#define PREF_BASE                       0x58004000UL\r
+#define PMU0_BASE                       0x58000508UL\r
+#define WDT_BASE                        0x50008000UL\r
+#define RTC_BASE                        0x50004A00UL\r
+#define SCU_CLK_BASE                    0x50004600UL\r
+#define SCU_OSC_BASE                    0x50004700UL\r
+#define SCU_PLL_BASE                    0x50004710UL\r
+#define SCU_GENERAL_BASE                0x50004000UL\r
+#define SCU_INTERRUPT_BASE              0x50004074UL\r
+#define SCU_PARITY_BASE                 0x5000413CUL\r
+#define SCU_TRAP_BASE                   0x50004160UL\r
+#define SCU_HIBERNATE_BASE              0x50004300UL\r
+#define SCU_POWER_BASE                  0x50004200UL\r
+#define SCU_RESET_BASE                  0x50004400UL\r
+#define LEDTS0_BASE                     0x48010000UL\r
+#define USB0_BASE                       0x50040000UL\r
+#define USB_EP_BASE                   0x50040900UL\r
+#define USB0_EP1_BASE                   0x50040920UL\r
+#define USB0_EP2_BASE                   0x50040940UL\r
+#define USB0_EP3_BASE                   0x50040960UL\r
+#define USB0_EP4_BASE                   0x50040980UL\r
+#define USB0_EP5_BASE                   0x500409A0UL\r
+#define USB0_EP6_BASE                   0x500409C0UL\r
+#define USIC0_BASE                      0x40030008UL\r
+#define USIC1_BASE                      0x48020008UL\r
+#define USIC0_CH0_BASE                  0x40030000UL\r
+#define USIC0_CH1_BASE                  0x40030200UL\r
+#define USIC1_CH0_BASE                  0x48020000UL\r
+#define USIC1_CH1_BASE                  0x48020200UL\r
+#define CAN_BASE                        0x48014000UL\r
+#define CAN_NODE0_BASE                  0x48014200UL\r
+#define CAN_NODE1_BASE                  0x48014300UL\r
+#define CAN_MO0_BASE                    0x48015000UL\r
+#define CAN_MO1_BASE                    0x48015020UL\r
+#define CAN_MO2_BASE                    0x48015040UL\r
+#define CAN_MO3_BASE                    0x48015060UL\r
+#define CAN_MO4_BASE                    0x48015080UL\r
+#define CAN_MO5_BASE                    0x480150A0UL\r
+#define CAN_MO6_BASE                    0x480150C0UL\r
+#define CAN_MO7_BASE                    0x480150E0UL\r
+#define CAN_MO8_BASE                    0x48015100UL\r
+#define CAN_MO9_BASE                    0x48015120UL\r
+#define CAN_MO10_BASE                   0x48015140UL\r
+#define CAN_MO11_BASE                   0x48015160UL\r
+#define CAN_MO12_BASE                   0x48015180UL\r
+#define CAN_MO13_BASE                   0x480151A0UL\r
+#define CAN_MO14_BASE                   0x480151C0UL\r
+#define CAN_MO15_BASE                   0x480151E0UL\r
+#define CAN_MO16_BASE                   0x48015200UL\r
+#define CAN_MO17_BASE                   0x48015220UL\r
+#define CAN_MO18_BASE                   0x48015240UL\r
+#define CAN_MO19_BASE                   0x48015260UL\r
+#define CAN_MO20_BASE                   0x48015280UL\r
+#define CAN_MO21_BASE                   0x480152A0UL\r
+#define CAN_MO22_BASE                   0x480152C0UL\r
+#define CAN_MO23_BASE                   0x480152E0UL\r
+#define CAN_MO24_BASE                   0x48015300UL\r
+#define CAN_MO25_BASE                   0x48015320UL\r
+#define CAN_MO26_BASE                   0x48015340UL\r
+#define CAN_MO27_BASE                   0x48015360UL\r
+#define CAN_MO28_BASE                   0x48015380UL\r
+#define CAN_MO29_BASE                   0x480153A0UL\r
+#define CAN_MO30_BASE                   0x480153C0UL\r
+#define CAN_MO31_BASE                   0x480153E0UL\r
+#define CAN_MO32_BASE                   0x48015400UL\r
+#define CAN_MO33_BASE                   0x48015420UL\r
+#define CAN_MO34_BASE                   0x48015440UL\r
+#define CAN_MO35_BASE                   0x48015460UL\r
+#define CAN_MO36_BASE                   0x48015480UL\r
+#define CAN_MO37_BASE                   0x480154A0UL\r
+#define CAN_MO38_BASE                   0x480154C0UL\r
+#define CAN_MO39_BASE                   0x480154E0UL\r
+#define CAN_MO40_BASE                   0x48015500UL\r
+#define CAN_MO41_BASE                   0x48015520UL\r
+#define CAN_MO42_BASE                   0x48015540UL\r
+#define CAN_MO43_BASE                   0x48015560UL\r
+#define CAN_MO44_BASE                   0x48015580UL\r
+#define CAN_MO45_BASE                   0x480155A0UL\r
+#define CAN_MO46_BASE                   0x480155C0UL\r
+#define CAN_MO47_BASE                   0x480155E0UL\r
+#define CAN_MO48_BASE                   0x48015600UL\r
+#define CAN_MO49_BASE                   0x48015620UL\r
+#define CAN_MO50_BASE                   0x48015640UL\r
+#define CAN_MO51_BASE                   0x48015660UL\r
+#define CAN_MO52_BASE                   0x48015680UL\r
+#define CAN_MO53_BASE                   0x480156A0UL\r
+#define CAN_MO54_BASE                   0x480156C0UL\r
+#define CAN_MO55_BASE                   0x480156E0UL\r
+#define CAN_MO56_BASE                   0x48015700UL\r
+#define CAN_MO57_BASE                   0x48015720UL\r
+#define CAN_MO58_BASE                   0x48015740UL\r
+#define CAN_MO59_BASE                   0x48015760UL\r
+#define CAN_MO60_BASE                   0x48015780UL\r
+#define CAN_MO61_BASE                   0x480157A0UL\r
+#define CAN_MO62_BASE                   0x480157C0UL\r
+#define CAN_MO63_BASE                   0x480157E0UL\r
+#define VADC_BASE                       0x40004000UL\r
+#define VADC_G0_BASE                    0x40004400UL\r
+#define VADC_G1_BASE                    0x40004800UL\r
+#define DAC_BASE                        0x48018000UL\r
+#define CCU40_BASE                      0x4000C000UL\r
+#define CCU41_BASE                      0x40010000UL\r
+#define CCU40_CC40_BASE                 0x4000C100UL\r
+#define CCU40_CC41_BASE                 0x4000C200UL\r
+#define CCU40_CC42_BASE                 0x4000C300UL\r
+#define CCU40_CC43_BASE                 0x4000C400UL\r
+#define CCU41_CC40_BASE                 0x40010100UL\r
+#define CCU41_CC41_BASE                 0x40010200UL\r
+#define CCU41_CC42_BASE                 0x40010300UL\r
+#define CCU41_CC43_BASE                 0x40010400UL\r
+#define CCU80_BASE                      0x40020000UL\r
+#define CCU80_CC80_BASE                 0x40020100UL\r
+#define CCU80_CC81_BASE                 0x40020200UL\r
+#define CCU80_CC82_BASE                 0x40020300UL\r
+#define CCU80_CC83_BASE                 0x40020400UL\r
+#define HRPWM0_BASE                     0x40020900UL\r
+#define HRPWM0_CSG0_BASE                0x40020A00UL\r
+#define HRPWM0_CSG1_BASE                0x40020B00UL\r
+#define HRPWM0_CSG2_BASE                0x40020C00UL\r
+#define HRPWM0_HRC0_BASE                0x40021300UL\r
+#define HRPWM0_HRC1_BASE                0x40021400UL\r
+#define HRPWM0_HRC2_BASE                0x40021500UL\r
+#define HRPWM0_HRC3_BASE                0x40021600UL\r
+#define POSIF0_BASE                     0x40028000UL\r
+#define PORT0_BASE                      0x48028000UL\r
+#define PORT1_BASE                      0x48028100UL\r
+#define PORT2_BASE                      0x48028200UL\r
+#define PORT3_BASE                      0x48028300UL\r
+#define PORT14_BASE                     0x48028E00UL\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================             Peripheral declaration             ================ */\r
+/* ================================================================================ */\r
+\r
+#define PPB                             ((PPB_Type                *) PPB_BASE)\r
+#define DLR                             ((DLR_GLOBAL_TypeDef                *) DLR_BASE)\r
+#define ERU0                            ((ERU_GLOBAL_TypeDef                *) ERU0_BASE)\r
+#define ERU1                            ((ERU_GLOBAL_TypeDef                *) ERU1_BASE)\r
+#define GPDMA0                          ((GPDMA0_GLOBAL_TypeDef             *) GPDMA0_BASE)\r
+#define GPDMA0_CH0                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH0_BASE)\r
+#define GPDMA0_CH1                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH1_BASE)\r
+#define GPDMA0_CH2                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH2_BASE)\r
+#define GPDMA0_CH3                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH3_BASE)\r
+#define GPDMA0_CH4                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH4_BASE)\r
+#define GPDMA0_CH5                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH5_BASE)\r
+#define GPDMA0_CH6                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH6_BASE)\r
+#define GPDMA0_CH7                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH7_BASE)\r
+#define FCE                             ((FCE_GLOBAL_TypeDef                *) FCE_BASE)\r
+#define FCE_KE0                         ((FCE_KE_TypeDef             *) FCE_KE0_BASE)\r
+#define FCE_KE1                         ((FCE_KE_TypeDef             *) FCE_KE1_BASE)\r
+#define FCE_KE2                         ((FCE_KE_TypeDef             *) FCE_KE2_BASE)\r
+#define FCE_KE3                         ((FCE_KE_TypeDef             *) FCE_KE3_BASE)\r
+#define PBA0                            ((PBA_GLOBAL_TypeDef                *) PBA0_BASE)\r
+#define PBA1                            ((PBA_GLOBAL_TypeDef                *) PBA1_BASE)\r
+#define FLASH0                          ((FLASH0_GLOBAL_TypeDef              *) FLASH0_BASE)\r
+#define PREF                            ((PREF_GLOBAL_TypeDef               *) PREF_BASE)\r
+#define PMU0                            ((PMU0_GLOBAL_TypeDef                *) PMU0_BASE)\r
+#define WDT                             ((WDT_GLOBAL_TypeDef                *) WDT_BASE)\r
+#define RTC                             ((RTC_GLOBAL_TypeDef                *) RTC_BASE)\r
+#define SCU_CLK                         ((SCU_CLK_TypeDef            *) SCU_CLK_BASE)\r
+#define SCU_OSC                         ((SCU_OSC_TypeDef            *) SCU_OSC_BASE)\r
+#define SCU_PLL                         ((SCU_PLL_TypeDef            *) SCU_PLL_BASE)\r
+#define SCU_GENERAL                     ((SCU_GENERAL_TypeDef        *) SCU_GENERAL_BASE)\r
+#define SCU_INTERRUPT                   ((SCU_INTERRUPT_TypeDef      *) SCU_INTERRUPT_BASE)\r
+#define SCU_PARITY                      ((SCU_PARITY_TypeDef         *) SCU_PARITY_BASE)\r
+#define SCU_TRAP                        ((SCU_TRAP_TypeDef           *) SCU_TRAP_BASE)\r
+#define SCU_HIBERNATE                   ((SCU_HIBERNATE_TypeDef      *) SCU_HIBERNATE_BASE)\r
+#define SCU_POWER                       ((SCU_POWER_TypeDef          *) SCU_POWER_BASE)\r
+#define SCU_RESET                       ((SCU_RESET_TypeDef          *) SCU_RESET_BASE)\r
+#define LEDTS0                          ((LEDTS0_GLOBAL_TypeDef              *) LEDTS0_BASE)\r
+#define USB0                            ((USB0_GLOBAL_TypeDef                *) USB0_BASE)\r
+#define USB0_EP0                        ((USB0_EP0_TypeDef           *) USB_EP_BASE)\r
+#define USB0_EP1                        ((USB0_EP_TypeDef             *) USB0_EP1_BASE)\r
+#define USB0_EP2                        ((USB0_EP_TypeDef             *) USB0_EP2_BASE)\r
+#define USB0_EP3                        ((USB0_EP_TypeDef             *) USB0_EP3_BASE)\r
+#define USB0_EP4                        ((USB0_EP_TypeDef             *) USB0_EP4_BASE)\r
+#define USB0_EP5                        ((USB0_EP_TypeDef             *) USB0_EP5_BASE)\r
+#define USB0_EP6                        ((USB0_EP_TypeDef             *) USB0_EP6_BASE)\r
+#define USIC0                           ((USIC_GLOBAL_TypeDef               *) USIC0_BASE)\r
+#define USIC1                           ((USIC_GLOBAL_TypeDef               *) USIC1_BASE)\r
+#define USIC0_CH0                       ((USIC_CH_TypeDef            *) USIC0_CH0_BASE)\r
+#define USIC0_CH1                       ((USIC_CH_TypeDef            *) USIC0_CH1_BASE)\r
+#define USIC1_CH0                       ((USIC_CH_TypeDef            *) USIC1_CH0_BASE)\r
+#define USIC1_CH1                       ((USIC_CH_TypeDef            *) USIC1_CH1_BASE)\r
+#define CAN                             ((CAN_GLOBAL_TypeDef                *) CAN_BASE)\r
+#define CAN_NODE0                       ((CAN_NODE_TypeDef           *) CAN_NODE0_BASE)\r
+#define CAN_NODE1                       ((CAN_NODE_TypeDef           *) CAN_NODE1_BASE)\r
+#define CAN_MO0                         ((CAN_MO_TypeDef             *) CAN_MO0_BASE)\r
+#define CAN_MO1                         ((CAN_MO_TypeDef             *) CAN_MO1_BASE)\r
+#define CAN_MO2                         ((CAN_MO_TypeDef             *) CAN_MO2_BASE)\r
+#define CAN_MO3                         ((CAN_MO_TypeDef             *) CAN_MO3_BASE)\r
+#define CAN_MO4                         ((CAN_MO_TypeDef             *) CAN_MO4_BASE)\r
+#define CAN_MO5                         ((CAN_MO_TypeDef             *) CAN_MO5_BASE)\r
+#define CAN_MO6                         ((CAN_MO_TypeDef             *) CAN_MO6_BASE)\r
+#define CAN_MO7                         ((CAN_MO_TypeDef             *) CAN_MO7_BASE)\r
+#define CAN_MO8                         ((CAN_MO_TypeDef             *) CAN_MO8_BASE)\r
+#define CAN_MO9                         ((CAN_MO_TypeDef             *) CAN_MO9_BASE)\r
+#define CAN_MO10                        ((CAN_MO_TypeDef             *) CAN_MO10_BASE)\r
+#define CAN_MO11                        ((CAN_MO_TypeDef             *) CAN_MO11_BASE)\r
+#define CAN_MO12                        ((CAN_MO_TypeDef             *) CAN_MO12_BASE)\r
+#define CAN_MO13                        ((CAN_MO_TypeDef             *) CAN_MO13_BASE)\r
+#define CAN_MO14                        ((CAN_MO_TypeDef             *) CAN_MO14_BASE)\r
+#define CAN_MO15                        ((CAN_MO_TypeDef             *) CAN_MO15_BASE)\r
+#define CAN_MO16                        ((CAN_MO_TypeDef             *) CAN_MO16_BASE)\r
+#define CAN_MO17                        ((CAN_MO_TypeDef             *) CAN_MO17_BASE)\r
+#define CAN_MO18                        ((CAN_MO_TypeDef             *) CAN_MO18_BASE)\r
+#define CAN_MO19                        ((CAN_MO_TypeDef             *) CAN_MO19_BASE)\r
+#define CAN_MO20                        ((CAN_MO_TypeDef             *) CAN_MO20_BASE)\r
+#define CAN_MO21                        ((CAN_MO_TypeDef             *) CAN_MO21_BASE)\r
+#define CAN_MO22                        ((CAN_MO_TypeDef             *) CAN_MO22_BASE)\r
+#define CAN_MO23                        ((CAN_MO_TypeDef             *) CAN_MO23_BASE)\r
+#define CAN_MO24                        ((CAN_MO_TypeDef             *) CAN_MO24_BASE)\r
+#define CAN_MO25                        ((CAN_MO_TypeDef             *) CAN_MO25_BASE)\r
+#define CAN_MO26                        ((CAN_MO_TypeDef             *) CAN_MO26_BASE)\r
+#define CAN_MO27                        ((CAN_MO_TypeDef             *) CAN_MO27_BASE)\r
+#define CAN_MO28                        ((CAN_MO_TypeDef             *) CAN_MO28_BASE)\r
+#define CAN_MO29                        ((CAN_MO_TypeDef             *) CAN_MO29_BASE)\r
+#define CAN_MO30                        ((CAN_MO_TypeDef             *) CAN_MO30_BASE)\r
+#define CAN_MO31                        ((CAN_MO_TypeDef             *) CAN_MO31_BASE)\r
+#define CAN_MO32                        ((CAN_MO_TypeDef             *) CAN_MO32_BASE)\r
+#define CAN_MO33                        ((CAN_MO_TypeDef             *) CAN_MO33_BASE)\r
+#define CAN_MO34                        ((CAN_MO_TypeDef             *) CAN_MO34_BASE)\r
+#define CAN_MO35                        ((CAN_MO_TypeDef             *) CAN_MO35_BASE)\r
+#define CAN_MO36                        ((CAN_MO_TypeDef             *) CAN_MO36_BASE)\r
+#define CAN_MO37                        ((CAN_MO_TypeDef             *) CAN_MO37_BASE)\r
+#define CAN_MO38                        ((CAN_MO_TypeDef             *) CAN_MO38_BASE)\r
+#define CAN_MO39                        ((CAN_MO_TypeDef             *) CAN_MO39_BASE)\r
+#define CAN_MO40                        ((CAN_MO_TypeDef             *) CAN_MO40_BASE)\r
+#define CAN_MO41                        ((CAN_MO_TypeDef             *) CAN_MO41_BASE)\r
+#define CAN_MO42                        ((CAN_MO_TypeDef             *) CAN_MO42_BASE)\r
+#define CAN_MO43                        ((CAN_MO_TypeDef             *) CAN_MO43_BASE)\r
+#define CAN_MO44                        ((CAN_MO_TypeDef             *) CAN_MO44_BASE)\r
+#define CAN_MO45                        ((CAN_MO_TypeDef             *) CAN_MO45_BASE)\r
+#define CAN_MO46                        ((CAN_MO_TypeDef             *) CAN_MO46_BASE)\r
+#define CAN_MO47                        ((CAN_MO_TypeDef             *) CAN_MO47_BASE)\r
+#define CAN_MO48                        ((CAN_MO_TypeDef             *) CAN_MO48_BASE)\r
+#define CAN_MO49                        ((CAN_MO_TypeDef             *) CAN_MO49_BASE)\r
+#define CAN_MO50                        ((CAN_MO_TypeDef             *) CAN_MO50_BASE)\r
+#define CAN_MO51                        ((CAN_MO_TypeDef             *) CAN_MO51_BASE)\r
+#define CAN_MO52                        ((CAN_MO_TypeDef             *) CAN_MO52_BASE)\r
+#define CAN_MO53                        ((CAN_MO_TypeDef             *) CAN_MO53_BASE)\r
+#define CAN_MO54                        ((CAN_MO_TypeDef             *) CAN_MO54_BASE)\r
+#define CAN_MO55                        ((CAN_MO_TypeDef             *) CAN_MO55_BASE)\r
+#define CAN_MO56                        ((CAN_MO_TypeDef             *) CAN_MO56_BASE)\r
+#define CAN_MO57                        ((CAN_MO_TypeDef             *) CAN_MO57_BASE)\r
+#define CAN_MO58                        ((CAN_MO_TypeDef             *) CAN_MO58_BASE)\r
+#define CAN_MO59                        ((CAN_MO_TypeDef             *) CAN_MO59_BASE)\r
+#define CAN_MO60                        ((CAN_MO_TypeDef             *) CAN_MO60_BASE)\r
+#define CAN_MO61                        ((CAN_MO_TypeDef             *) CAN_MO61_BASE)\r
+#define CAN_MO62                        ((CAN_MO_TypeDef             *) CAN_MO62_BASE)\r
+#define CAN_MO63                        ((CAN_MO_TypeDef             *) CAN_MO63_BASE)\r
+#define VADC                            ((VADC_GLOBAL_TypeDef               *) VADC_BASE)\r
+#define VADC_G0                         ((VADC_G_TypeDef             *) VADC_G0_BASE)\r
+#define VADC_G1                         ((VADC_G_TypeDef             *) VADC_G1_BASE)\r
+#define DAC                             ((DAC_GLOBAL_TypeDef                *) DAC_BASE)\r
+#define CCU40                           ((CCU4_GLOBAL_TypeDef               *) CCU40_BASE)\r
+#define CCU41                           ((CCU4_GLOBAL_TypeDef               *) CCU41_BASE)\r
+#define CCU40_CC40                      ((CCU4_CC4_TypeDef           *) CCU40_CC40_BASE)\r
+#define CCU40_CC41                      ((CCU4_CC4_TypeDef           *) CCU40_CC41_BASE)\r
+#define CCU40_CC42                      ((CCU4_CC4_TypeDef           *) CCU40_CC42_BASE)\r
+#define CCU40_CC43                      ((CCU4_CC4_TypeDef           *) CCU40_CC43_BASE)\r
+#define CCU41_CC40                      ((CCU4_CC4_TypeDef           *) CCU41_CC40_BASE)\r
+#define CCU41_CC41                      ((CCU4_CC4_TypeDef           *) CCU41_CC41_BASE)\r
+#define CCU41_CC42                      ((CCU4_CC4_TypeDef           *) CCU41_CC42_BASE)\r
+#define CCU41_CC43                      ((CCU4_CC4_TypeDef           *) CCU41_CC43_BASE)\r
+#define CCU80                           ((CCU8_GLOBAL_TypeDef               *) CCU80_BASE)\r
+#define CCU80_CC80                      ((CCU8_CC8_TypeDef           *) CCU80_CC80_BASE)\r
+#define CCU80_CC81                      ((CCU8_CC8_TypeDef           *) CCU80_CC81_BASE)\r
+#define CCU80_CC82                      ((CCU8_CC8_TypeDef           *) CCU80_CC82_BASE)\r
+#define CCU80_CC83                      ((CCU8_CC8_TypeDef           *) CCU80_CC83_BASE)\r
+#define HRPWM0                          ((HRPWM0_Type             *) HRPWM0_BASE)\r
+#define HRPWM0_CSG0                     ((HRPWM0_CSG_Type         *) HRPWM0_CSG0_BASE)\r
+#define HRPWM0_CSG1                     ((HRPWM0_CSG_Type         *) HRPWM0_CSG1_BASE)\r
+#define HRPWM0_CSG2                     ((HRPWM0_CSG_Type         *) HRPWM0_CSG2_BASE)\r
+#define HRPWM0_HRC0                     ((HRPWM0_HRC_Type         *) HRPWM0_HRC0_BASE)\r
+#define HRPWM0_HRC1                     ((HRPWM0_HRC_Type         *) HRPWM0_HRC1_BASE)\r
+#define HRPWM0_HRC2                     ((HRPWM0_HRC_Type         *) HRPWM0_HRC2_BASE)\r
+#define HRPWM0_HRC3                     ((HRPWM0_HRC_Type         *) HRPWM0_HRC3_BASE)\r
+#define POSIF0                          ((POSIF_GLOBAL_TypeDef              *) POSIF0_BASE)\r
+#define PORT0                           ((PORT0_Type              *) PORT0_BASE)\r
+#define PORT1                           ((PORT1_Type              *) PORT1_BASE)\r
+#define PORT2                           ((PORT2_Type              *) PORT2_BASE)\r
+#define PORT3                           ((PORT3_Type              *) PORT3_BASE)\r
+#define PORT14                          ((PORT14_Type             *) PORT14_BASE)\r
+\r
+\r
+/** @} */ /* End of group Device_Peripheral_Registers */\r
+/** @} */ /* End of group XMC4200 */\r
+/** @} */ /* End of group Infineon */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif  /* XMC4200_H */\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4400.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4400.h
new file mode 100644 (file)
index 0000000..e4b68c6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4400.h
@@ -0,0 +1,16784 @@
+\r
+/****************************************************************************************************//**\r
+ * @file     XMC4400.h\r
+ *\r
+ * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for\r
+ *           XMC4400 from Infineon.\r
+ *\r
+ * @version  V1.1.0 (Reference Manual v1.1)\r
+ * @date     13. December 2012\r
+ *\r
+ * @note     Generated with SVDConv V2.78b \r
+ *           from CMSIS SVD File 'XMC4400_Processed_SVD.xml' Version 1.1.0 (Reference Manual v1.1),\r
+ *******************************************************************************************************/\r
+\r
+\r
+\r
+/** @addtogroup Infineon\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup XMC4400\r
+  * @{\r
+  */\r
+\r
+#ifndef XMC4400_H\r
+#define XMC4400_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/* -------------------------  Interrupt Number Definition  ------------------------ */\r
+\r
+typedef enum {\r
+/* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */\r
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */\r
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */\r
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */\r
+  MemoryManagement_IRQn         = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation\r
+                                                         and No Match                                                          */\r
+  BusFault_IRQn                 = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory\r
+                                                         related Fault                                                         */\r
+  UsageFault_IRQn               = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */\r
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */\r
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */\r
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */\r
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */\r
+/* ---------------------  XMC4400 Specific Interrupt Numbers  --------------------- */\r
+  SCU_0_IRQn                    =   0,              /*!<   0  SCU_0                                                            */\r
+  ERU0_0_IRQn                   =   1,              /*!<   1  ERU0_0                                                           */\r
+  ERU0_1_IRQn                   =   2,              /*!<   2  ERU0_1                                                           */\r
+  ERU0_2_IRQn                   =   3,              /*!<   3  ERU0_2                                                           */\r
+  ERU0_3_IRQn                   =   4,              /*!<   4  ERU0_3                                                           */\r
+  ERU1_0_IRQn                   =   5,              /*!<   5  ERU1_0                                                           */\r
+  ERU1_1_IRQn                   =   6,              /*!<   6  ERU1_1                                                           */\r
+  ERU1_2_IRQn                   =   7,              /*!<   7  ERU1_2                                                           */\r
+  ERU1_3_IRQn                   =   8,              /*!<   8  ERU1_3                                                           */\r
+  PMU0_0_IRQn                   =  12,              /*!<  12  PMU0_0                                                           */\r
+  VADC0_C0_0_IRQn               =  14,              /*!<  14  VADC0_C0_0                                                       */\r
+  VADC0_C0_1_IRQn               =  15,              /*!<  15  VADC0_C0_1                                                       */\r
+  VADC0_C0_2_IRQn               =  16,              /*!<  16  VADC0_C0_2                                                       */\r
+  VADC0_C0_3_IRQn               =  17,              /*!<  17  VADC0_C0_3                                                       */\r
+  VADC0_G0_0_IRQn               =  18,              /*!<  18  VADC0_G0_0                                                       */\r
+  VADC0_G0_1_IRQn               =  19,              /*!<  19  VADC0_G0_1                                                       */\r
+  VADC0_G0_2_IRQn               =  20,              /*!<  20  VADC0_G0_2                                                       */\r
+  VADC0_G0_3_IRQn               =  21,              /*!<  21  VADC0_G0_3                                                       */\r
+  VADC0_G1_0_IRQn               =  22,              /*!<  22  VADC0_G1_0                                                       */\r
+  VADC0_G1_1_IRQn               =  23,              /*!<  23  VADC0_G1_1                                                       */\r
+  VADC0_G1_2_IRQn               =  24,              /*!<  24  VADC0_G1_2                                                       */\r
+  VADC0_G1_3_IRQn               =  25,              /*!<  25  VADC0_G1_3                                                       */\r
+  VADC0_G2_0_IRQn               =  26,              /*!<  26  VADC0_G2_0                                                       */\r
+  VADC0_G2_1_IRQn               =  27,              /*!<  27  VADC0_G2_1                                                       */\r
+  VADC0_G2_2_IRQn               =  28,              /*!<  28  VADC0_G2_2                                                       */\r
+  VADC0_G2_3_IRQn               =  29,              /*!<  29  VADC0_G2_3                                                       */\r
+  VADC0_G3_0_IRQn               =  30,              /*!<  30  VADC0_G3_0                                                       */\r
+  VADC0_G3_1_IRQn               =  31,              /*!<  31  VADC0_G3_1                                                       */\r
+  VADC0_G3_2_IRQn               =  32,              /*!<  32  VADC0_G3_2                                                       */\r
+  VADC0_G3_3_IRQn               =  33,              /*!<  33  VADC0_G3_3                                                       */\r
+  DSD0_M_0_IRQn                 =  34,              /*!<  34  DSD0_M_0                                                         */\r
+  DSD0_M_1_IRQn                 =  35,              /*!<  35  DSD0_M_1                                                         */\r
+  DSD0_M_2_IRQn                 =  36,              /*!<  36  DSD0_M_2                                                         */\r
+  DSD0_M_3_IRQn                 =  37,              /*!<  37  DSD0_M_3                                                         */\r
+  DSD0_A_4_IRQn                 =  38,              /*!<  38  DSD0_A_4                                                         */\r
+  DSD0_A_5_IRQn                 =  39,              /*!<  39  DSD0_A_5                                                         */\r
+  DSD0_A_6_IRQn                 =  40,              /*!<  40  DSD0_A_6                                                         */\r
+  DSD0_A_7_IRQn                 =  41,              /*!<  41  DSD0_A_7                                                         */\r
+  DAC0_0_IRQn                   =  42,              /*!<  42  DAC0_0                                                           */\r
+  DAC0_1_IRQn                   =  43,              /*!<  43  DAC0_1                                                           */\r
+  CCU40_0_IRQn                  =  44,              /*!<  44  CCU40_0                                                          */\r
+  CCU40_1_IRQn                  =  45,              /*!<  45  CCU40_1                                                          */\r
+  CCU40_2_IRQn                  =  46,              /*!<  46  CCU40_2                                                          */\r
+  CCU40_3_IRQn                  =  47,              /*!<  47  CCU40_3                                                          */\r
+  CCU41_0_IRQn                  =  48,              /*!<  48  CCU41_0                                                          */\r
+  CCU41_1_IRQn                  =  49,              /*!<  49  CCU41_1                                                          */\r
+  CCU41_2_IRQn                  =  50,              /*!<  50  CCU41_2                                                          */\r
+  CCU41_3_IRQn                  =  51,              /*!<  51  CCU41_3                                                          */\r
+  CCU42_0_IRQn                  =  52,              /*!<  52  CCU42_0                                                          */\r
+  CCU42_1_IRQn                  =  53,              /*!<  53  CCU42_1                                                          */\r
+  CCU42_2_IRQn                  =  54,              /*!<  54  CCU42_2                                                          */\r
+  CCU42_3_IRQn                  =  55,              /*!<  55  CCU42_3                                                          */\r
+  CCU43_0_IRQn                  =  56,              /*!<  56  CCU43_0                                                          */\r
+  CCU43_1_IRQn                  =  57,              /*!<  57  CCU43_1                                                          */\r
+  CCU43_2_IRQn                  =  58,              /*!<  58  CCU43_2                                                          */\r
+  CCU43_3_IRQn                  =  59,              /*!<  59  CCU43_3                                                          */\r
+  CCU80_0_IRQn                  =  60,              /*!<  60  CCU80_0                                                          */\r
+  CCU80_1_IRQn                  =  61,              /*!<  61  CCU80_1                                                          */\r
+  CCU80_2_IRQn                  =  62,              /*!<  62  CCU80_2                                                          */\r
+  CCU80_3_IRQn                  =  63,              /*!<  63  CCU80_3                                                          */\r
+  CCU81_0_IRQn                  =  64,              /*!<  64  CCU81_0                                                          */\r
+  CCU81_1_IRQn                  =  65,              /*!<  65  CCU81_1                                                          */\r
+  CCU81_2_IRQn                  =  66,              /*!<  66  CCU81_2                                                          */\r
+  CCU81_3_IRQn                  =  67,              /*!<  67  CCU81_3                                                          */\r
+  POSIF0_0_IRQn                 =  68,              /*!<  68  POSIF0_0                                                         */\r
+  POSIF0_1_IRQn                 =  69,              /*!<  69  POSIF0_1                                                         */\r
+  POSIF1_0_IRQn                 =  70,              /*!<  70  POSIF1_0                                                         */\r
+  POSIF1_1_IRQn                 =  71,              /*!<  71  POSIF1_1                                                         */\r
+  HRPWM_0_IRQn                  =  72,              /*!<  72  HRPWM_0                                                          */\r
+  HRPWM_1_IRQn                  =  73,              /*!<  73  HRPWM_1                                                          */ \r
+  HRPWM_2_IRQn                  =  74,              /*!<  72  HRPWM_2                                                          */\r
+  HRPWM_3_IRQn                  =  75,              /*!<  73  HRPWM_3                                                          */ \r
+  CAN0_0_IRQn                   =  76,              /*!<  76  CAN0_0                                                           */\r
+  CAN0_1_IRQn                   =  77,              /*!<  77  CAN0_1                                                           */\r
+  CAN0_2_IRQn                   =  78,              /*!<  78  CAN0_2                                                           */\r
+  CAN0_3_IRQn                   =  79,              /*!<  79  CAN0_3                                                           */\r
+  CAN0_4_IRQn                   =  80,              /*!<  80  CAN0_4                                                           */\r
+  CAN0_5_IRQn                   =  81,              /*!<  81  CAN0_5                                                           */\r
+  CAN0_6_IRQn                   =  82,              /*!<  82  CAN0_6                                                           */\r
+  CAN0_7_IRQn                   =  83,              /*!<  83  CAN0_7                                                           */\r
+  USIC0_0_IRQn                  =  84,              /*!<  84  USIC0_0                                                          */\r
+  USIC0_1_IRQn                  =  85,              /*!<  85  USIC0_1                                                          */\r
+  USIC0_2_IRQn                  =  86,              /*!<  86  USIC0_2                                                          */\r
+  USIC0_3_IRQn                  =  87,              /*!<  87  USIC0_3                                                          */\r
+  USIC0_4_IRQn                  =  88,              /*!<  88  USIC0_4                                                          */\r
+  USIC0_5_IRQn                  =  89,              /*!<  89  USIC0_5                                                          */\r
+  USIC1_0_IRQn                  =  90,              /*!<  90  USIC1_0                                                          */\r
+  USIC1_1_IRQn                  =  91,              /*!<  91  USIC1_1                                                          */\r
+  USIC1_2_IRQn                  =  92,              /*!<  92  USIC1_2                                                          */\r
+  USIC1_3_IRQn                  =  93,              /*!<  93  USIC1_3                                                          */\r
+  USIC1_4_IRQn                  =  94,              /*!<  94  USIC1_4                                                          */\r
+  USIC1_5_IRQn                  =  95,              /*!<  95  USIC1_5                                                          */\r
+  LEDTS0_0_IRQn                 = 102,              /*!< 102  LEDTS0_0                                                         */\r
+  FCE0_0_IRQn                   = 104,              /*!< 104  FCE0_0                                                           */\r
+  GPDMA0_0_IRQn                 = 105,              /*!< 105  GPDMA0_0                                                         */\r
+  USB0_0_IRQn                   = 107,              /*!< 107  USB0_0                                                           */\r
+  ETH0_0_IRQn                   = 108,              /*!< 108  ETH0_0                                                           */\r
+} IRQn_Type;\r
+\r
+\r
+/** @addtogroup Configuration_of_CMSIS\r
+  * @{\r
+  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      Processor and Core Peripheral Section     ================ */\r
+/* ================================================================================ */\r
+\r
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */\r
+#define __CM4_REV                 0x0200            /*!< Cortex-M4 Core Revision                                               */\r
+#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */\r
+#define __NVIC_PRIO_BITS               6            /*!< Number of Bits used for Priority Levels                               */\r
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */\r
+#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */\r
+/** @} */ /* End of group Configuration_of_CMSIS */\r
+\r
+#include <core_cm4.h>                               /*!< Cortex-M4 processor and core peripherals                              */\r
+#include "system_XMC4400.h"                         /*!< XMC4400 System                                                        */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       Device Specific Peripheral Section       ================ */\r
+/* ================================================================================ */\r
+/* Macro to modify desired bitfields of a register */\r
+#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \\r
+                                                        ((uint32_t)mask)) | \\r
+                                          (reg & ((uint32_t)~((uint32_t)mask)))\r
+\r
+/* Macro to modify desired bitfields of a register */\r
+#define WR_REG_SIZE(reg, mask, pos, val, size) {  \\r
+uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \\r
+uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \\r
+uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \\r
+uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \\r
+reg = (uint##size##_t) (VAL2 | VAL4);\\r
+}\r
+\r
+/** Macro to read bitfields from a register */\r
+#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)\r
+\r
+/** Macro to read bitfields from a register */\r
+#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \\r
+                                                      (uint32_t)mask) >> pos) )\r
+\r
+/** Macro to set a bit in register */\r
+#define SET_BIT(reg, pos)     (reg |= ((uint32_t)1<<pos))\r
+\r
+/** Macro to clear a bit in register */\r
+#define CLR_BIT(reg, pos)     (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) )\r
+/*\r
+* ==========================================================================\r
+* ---------- Interrupt Handler Definition ----------------------------------\r
+* ==========================================================================\r
+*/\r
+#define IRQ_Hdlr_0   SCU_0_IRQHandler\r
+#define IRQ_Hdlr_1   ERU0_0_IRQHandler\r
+#define IRQ_Hdlr_2   ERU0_1_IRQHandler\r
+#define IRQ_Hdlr_3   ERU0_2_IRQHandler\r
+#define IRQ_Hdlr_4   ERU0_3_IRQHandler\r
+#define IRQ_Hdlr_5   ERU1_0_IRQHandler\r
+#define IRQ_Hdlr_6   ERU1_1_IRQHandler\r
+#define IRQ_Hdlr_7   ERU1_2_IRQHandler\r
+#define IRQ_Hdlr_8   ERU1_3_IRQHandler\r
+#define IRQ_Hdlr_12  PMU0_0_IRQHandler\r
+#define IRQ_Hdlr_14  VADC0_C0_0_IRQHandler\r
+#define IRQ_Hdlr_15  VADC0_C0_1_IRQHandler\r
+#define IRQ_Hdlr_16  VADC0_C0_2_IRQHandler\r
+#define IRQ_Hdlr_17  VADC0_C0_3_IRQHandler\r
+#define IRQ_Hdlr_18  VADC0_G0_0_IRQHandler\r
+#define IRQ_Hdlr_19  VADC0_G0_1_IRQHandler\r
+#define IRQ_Hdlr_20  VADC0_G0_2_IRQHandler\r
+#define IRQ_Hdlr_21  VADC0_G0_3_IRQHandler\r
+#define IRQ_Hdlr_22  VADC0_G1_0_IRQHandler\r
+#define IRQ_Hdlr_23  VADC0_G1_1_IRQHandler\r
+#define IRQ_Hdlr_24  VADC0_G1_2_IRQHandler\r
+#define IRQ_Hdlr_25  VADC0_G1_3_IRQHandler\r
+#define IRQ_Hdlr_26  VADC0_G2_0_IRQHandler\r
+#define IRQ_Hdlr_27  VADC0_G2_1_IRQHandler\r
+#define IRQ_Hdlr_28  VADC0_G2_2_IRQHandler\r
+#define IRQ_Hdlr_29  VADC0_G2_3_IRQHandler\r
+#define IRQ_Hdlr_30  VADC0_G3_0_IRQHandler\r
+#define IRQ_Hdlr_31  VADC0_G3_1_IRQHandler\r
+#define IRQ_Hdlr_32  VADC0_G3_2_IRQHandler\r
+#define IRQ_Hdlr_33  VADC0_G3_3_IRQHandler\r
+#define IRQ_Hdlr_34  DSD0_0_IRQHandler\r
+#define IRQ_Hdlr_35  DSD0_1_IRQHandler\r
+#define IRQ_Hdlr_36  DSD0_2_IRQHandler\r
+#define IRQ_Hdlr_37  DSD0_3_IRQHandler\r
+#define IRQ_Hdlr_38  DSD0_4_IRQHandler\r
+#define IRQ_Hdlr_39  DSD0_5_IRQHandler\r
+#define IRQ_Hdlr_40  DSD0_6_IRQHandler\r
+#define IRQ_Hdlr_41  DSD0_7_IRQHandler\r
+#define IRQ_Hdlr_42  DAC0_0_IRQHandler\r
+#define IRQ_Hdlr_43  DAC0_1_IRQHandler\r
+#define IRQ_Hdlr_44  CCU40_0_IRQHandler\r
+#define IRQ_Hdlr_45  CCU40_1_IRQHandler\r
+#define IRQ_Hdlr_46  CCU40_2_IRQHandler\r
+#define IRQ_Hdlr_47  CCU40_3_IRQHandler\r
+#define IRQ_Hdlr_48  CCU41_0_IRQHandler\r
+#define IRQ_Hdlr_49  CCU41_1_IRQHandler\r
+#define IRQ_Hdlr_50  CCU41_2_IRQHandler\r
+#define IRQ_Hdlr_51  CCU41_3_IRQHandler\r
+#define IRQ_Hdlr_52  CCU42_0_IRQHandler\r
+#define IRQ_Hdlr_53  CCU42_1_IRQHandler\r
+#define IRQ_Hdlr_54  CCU42_2_IRQHandler\r
+#define IRQ_Hdlr_55  CCU42_3_IRQHandler\r
+#define IRQ_Hdlr_56  CCU43_0_IRQHandler\r
+#define IRQ_Hdlr_57  CCU43_1_IRQHandler\r
+#define IRQ_Hdlr_58  CCU43_2_IRQHandler\r
+#define IRQ_Hdlr_59  CCU43_3_IRQHandler\r
+#define IRQ_Hdlr_60  CCU80_0_IRQHandler\r
+#define IRQ_Hdlr_61  CCU80_1_IRQHandler\r
+#define IRQ_Hdlr_62  CCU80_2_IRQHandler\r
+#define IRQ_Hdlr_63  CCU80_3_IRQHandler\r
+#define IRQ_Hdlr_64  CCU81_0_IRQHandler\r
+#define IRQ_Hdlr_65  CCU81_1_IRQHandler\r
+#define IRQ_Hdlr_66  CCU81_2_IRQHandler\r
+#define IRQ_Hdlr_67  CCU81_3_IRQHandler\r
+#define IRQ_Hdlr_68  POSIF0_0_IRQHandler\r
+#define IRQ_Hdlr_69  POSIF0_1_IRQHandler\r
+#define IRQ_Hdlr_70  POSIF1_0_IRQHandler\r
+#define IRQ_Hdlr_71  POSIF1_1_IRQHandler\r
+#define IRQ_Hdlr_72  HRPWM_0_IRQHandler\r
+#define IRQ_Hdlr_73  HRPWM_1_IRQHandler\r
+#define IRQ_Hdlr_74  HRPWM_2_IRQHandler\r
+#define IRQ_Hdlr_75  HRPWM_3_IRQHandler\r
+#define IRQ_Hdlr_76  CAN0_0_IRQHandler\r
+#define IRQ_Hdlr_77  CAN0_1_IRQHandler\r
+#define IRQ_Hdlr_78  CAN0_2_IRQHandler\r
+#define IRQ_Hdlr_79  CAN0_3_IRQHandler\r
+#define IRQ_Hdlr_80  CAN0_4_IRQHandler\r
+#define IRQ_Hdlr_81  CAN0_5_IRQHandler\r
+#define IRQ_Hdlr_82  CAN0_6_IRQHandler\r
+#define IRQ_Hdlr_83  CAN0_7_IRQHandler\r
+#define IRQ_Hdlr_84  USIC0_0_IRQHandler\r
+#define IRQ_Hdlr_85  USIC0_1_IRQHandler\r
+#define IRQ_Hdlr_86  USIC0_2_IRQHandler\r
+#define IRQ_Hdlr_87  USIC0_3_IRQHandler\r
+#define IRQ_Hdlr_88  USIC0_4_IRQHandler\r
+#define IRQ_Hdlr_89  USIC0_5_IRQHandler\r
+#define IRQ_Hdlr_90  USIC1_0_IRQHandler\r
+#define IRQ_Hdlr_91  USIC1_1_IRQHandler\r
+#define IRQ_Hdlr_92  USIC1_2_IRQHandler\r
+#define IRQ_Hdlr_93  USIC1_3_IRQHandler\r
+#define IRQ_Hdlr_94  USIC1_4_IRQHandler\r
+#define IRQ_Hdlr_95  USIC1_5_IRQHandler\r
+#define IRQ_Hdlr_101 USIC2_5_IRQHandler\r
+#define IRQ_Hdlr_102 LEDTS0_0_IRQHandler\r
+#define IRQ_Hdlr_104 FCE0_0_IRQHandler\r
+#define IRQ_Hdlr_105 GPDMA0_0_IRQHandler\r
+#define IRQ_Hdlr_107 USB0_0_IRQHandler\r
+#define IRQ_Hdlr_108 ETH0_0_IRQHandler\r
+\r
+/*\r
+* ==========================================================================\r
+* ---------- Interrupt Handler retrieval macro -----------------------------\r
+* ==========================================================================\r
+*/\r
+#define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N\r
+\r
+/** @addtogroup Device_Peripheral_Registers\r
+  * @{\r
+  */\r
+\r
+\r
+/* -------------------  Start of section using anonymous unions  ------------------ */\r
+#if defined(__CC_ARM)\r
+  #pragma push\r
+  #pragma anon_unions\r
+#elif defined(__ICCARM__)\r
+  #pragma language=extended\r
+#elif defined(__GNUC__)\r
+  /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+/* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+  #pragma warning 586\r
+#else\r
+  #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       PPB                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Cortex-M4 Private Peripheral Block (PPB)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0xE000E000) PPB Structure                                          */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  ACTLR;                             /*!< (@ 0xE000E008) Auxiliary Control Register                             */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  SYST_CSR;                          /*!< (@ 0xE000E010) SysTick Control and Status Register                    */\r
+  __IO uint32_t  SYST_RVR;                          /*!< (@ 0xE000E014) SysTick Reload Value Register                          */\r
+  __IO uint32_t  SYST_CVR;                          /*!< (@ 0xE000E018) SysTick Current Value Register                         */\r
+  __IO uint32_t  SYST_CALIB;                        /*!< (@ 0xE000E01C) SysTick Calibration Value Register r                   */\r
+  __I  uint32_t  RESERVED2[56];\r
+  __IO uint32_t  NVIC_ISER0;                        /*!< (@ 0xE000E100) Interrupt Set-enable Register 0                        */\r
+  __IO uint32_t  NVIC_ISER1;                        /*!< (@ 0xE000E104) Interrupt Set-enable Register 1                        */\r
+  __IO uint32_t  NVIC_ISER2;                        /*!< (@ 0xE000E108) Interrupt Set-enable Register 2                        */\r
+  __IO uint32_t  NVIC_ISER3;                        /*!< (@ 0xE000E10C) Interrupt Set-enable Register 3                        */\r
+  __I  uint32_t  RESERVED3[28];\r
+  __IO uint32_t  NVIC_ICER0;                        /*!< (@ 0xE000E180) Interrupt Clear-enable Register 0                      */\r
+  __IO uint32_t  NVIC_ICER1;                        /*!< (@ 0xE000E184) Interrupt Clear-enable Register 1                      */\r
+  __IO uint32_t  NVIC_ICER2;                        /*!< (@ 0xE000E188) Interrupt Clear-enable Register 2                      */\r
+  __IO uint32_t  NVIC_ICER3;                        /*!< (@ 0xE000E18C) Interrupt Clear-enable Register 3                      */\r
+  __I  uint32_t  RESERVED4[28];\r
+  __IO uint32_t  NVIC_ISPR0;                        /*!< (@ 0xE000E200) Interrupt Set-pending Register 0                       */\r
+  __IO uint32_t  NVIC_ISPR1;                        /*!< (@ 0xE000E204) Interrupt Set-pending Register 1                       */\r
+  __IO uint32_t  NVIC_ISPR2;                        /*!< (@ 0xE000E208) Interrupt Set-pending Register 2                       */\r
+  __IO uint32_t  NVIC_ISPR3;                        /*!< (@ 0xE000E20C) Interrupt Set-pending Register 3                       */\r
+  __I  uint32_t  RESERVED5[28];\r
+  __IO uint32_t  NVIC_ICPR0;                        /*!< (@ 0xE000E280) Interrupt Clear-pending Register 0                     */\r
+  __IO uint32_t  NVIC_ICPR1;                        /*!< (@ 0xE000E284) Interrupt Clear-pending Register 1                     */\r
+  __IO uint32_t  NVIC_ICPR2;                        /*!< (@ 0xE000E288) Interrupt Clear-pending Register 2                     */\r
+  __IO uint32_t  NVIC_ICPR3;                        /*!< (@ 0xE000E28C) Interrupt Clear-pending Register 3                     */\r
+  __I  uint32_t  RESERVED6[28];\r
+  __IO uint32_t  NVIC_IABR0;                        /*!< (@ 0xE000E300) Interrupt Active Bit Register 0                        */\r
+  __IO uint32_t  NVIC_IABR1;                        /*!< (@ 0xE000E304) Interrupt Active Bit Register 1                        */\r
+  __IO uint32_t  NVIC_IABR2;                        /*!< (@ 0xE000E308) Interrupt Active Bit Register 2                        */\r
+  __IO uint32_t  NVIC_IABR3;                        /*!< (@ 0xE000E30C) Interrupt Active Bit Register 3                        */\r
+  __I  uint32_t  RESERVED7[60];\r
+  __IO uint32_t  NVIC_IPR0;                         /*!< (@ 0xE000E400) Interrupt Priority Register 0                          */\r
+  __IO uint32_t  NVIC_IPR1;                         /*!< (@ 0xE000E404) Interrupt Priority Register 1                          */\r
+  __IO uint32_t  NVIC_IPR2;                         /*!< (@ 0xE000E408) Interrupt Priority Register 2                          */\r
+  __IO uint32_t  NVIC_IPR3;                         /*!< (@ 0xE000E40C) Interrupt Priority Register 3                          */\r
+  __IO uint32_t  NVIC_IPR4;                         /*!< (@ 0xE000E410) Interrupt Priority Register 4                          */\r
+  __IO uint32_t  NVIC_IPR5;                         /*!< (@ 0xE000E414) Interrupt Priority Register 5                          */\r
+  __IO uint32_t  NVIC_IPR6;                         /*!< (@ 0xE000E418) Interrupt Priority Register 6                          */\r
+  __IO uint32_t  NVIC_IPR7;                         /*!< (@ 0xE000E41C) Interrupt Priority Register 7                          */\r
+  __IO uint32_t  NVIC_IPR8;                         /*!< (@ 0xE000E420) Interrupt Priority Register 8                          */\r
+  __IO uint32_t  NVIC_IPR9;                         /*!< (@ 0xE000E424) Interrupt Priority Register 9                          */\r
+  __IO uint32_t  NVIC_IPR10;                        /*!< (@ 0xE000E428) Interrupt Priority Register 10                         */\r
+  __IO uint32_t  NVIC_IPR11;                        /*!< (@ 0xE000E42C) Interrupt Priority Register 11                         */\r
+  __IO uint32_t  NVIC_IPR12;                        /*!< (@ 0xE000E430) Interrupt Priority Register 12                         */\r
+  __IO uint32_t  NVIC_IPR13;                        /*!< (@ 0xE000E434) Interrupt Priority Register 13                         */\r
+  __IO uint32_t  NVIC_IPR14;                        /*!< (@ 0xE000E438) Interrupt Priority Register 14                         */\r
+  __IO uint32_t  NVIC_IPR15;                        /*!< (@ 0xE000E43C) Interrupt Priority Register 15                         */\r
+  __IO uint32_t  NVIC_IPR16;                        /*!< (@ 0xE000E440) Interrupt Priority Register 16                         */\r
+  __IO uint32_t  NVIC_IPR17;                        /*!< (@ 0xE000E444) Interrupt Priority Register 17                         */\r
+  __IO uint32_t  NVIC_IPR18;                        /*!< (@ 0xE000E448) Interrupt Priority Register 18                         */\r
+  __IO uint32_t  NVIC_IPR19;                        /*!< (@ 0xE000E44C) Interrupt Priority Register 19                         */\r
+  __IO uint32_t  NVIC_IPR20;                        /*!< (@ 0xE000E450) Interrupt Priority Register 20                         */\r
+  __IO uint32_t  NVIC_IPR21;                        /*!< (@ 0xE000E454) Interrupt Priority Register 21                         */\r
+  __IO uint32_t  NVIC_IPR22;                        /*!< (@ 0xE000E458) Interrupt Priority Register 22                         */\r
+  __IO uint32_t  NVIC_IPR23;                        /*!< (@ 0xE000E45C) Interrupt Priority Register 23                         */\r
+  __IO uint32_t  NVIC_IPR24;                        /*!< (@ 0xE000E460) Interrupt Priority Register 24                         */\r
+  __IO uint32_t  NVIC_IPR25;                        /*!< (@ 0xE000E464) Interrupt Priority Register 25                         */\r
+  __IO uint32_t  NVIC_IPR26;                        /*!< (@ 0xE000E468) Interrupt Priority Register 26                         */\r
+  __IO uint32_t  NVIC_IPR27;                        /*!< (@ 0xE000E46C) Interrupt Priority Register 27                         */\r
+  __I  uint32_t  RESERVED8[548];\r
+  __I  uint32_t  CPUID;                             /*!< (@ 0xE000ED00) CPUID Base Register                                    */\r
+  __IO uint32_t  ICSR;                              /*!< (@ 0xE000ED04) Interrupt Control and State Register                   */\r
+  __IO uint32_t  VTOR;                              /*!< (@ 0xE000ED08) Vector Table Offset Register                           */\r
+  __IO uint32_t  AIRCR;                             /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register       */\r
+  __IO uint32_t  SCR;                               /*!< (@ 0xE000ED10) System Control Register                                */\r
+  __IO uint32_t  CCR;                               /*!< (@ 0xE000ED14) Configuration and Control Register                     */\r
+  __IO uint32_t  SHPR1;                             /*!< (@ 0xE000ED18) System Handler Priority Register 1                     */\r
+  __IO uint32_t  SHPR2;                             /*!< (@ 0xE000ED1C) System Handler Priority Register 2                     */\r
+  __IO uint32_t  SHPR3;                             /*!< (@ 0xE000ED20) System Handler Priority Register 3                     */\r
+  __IO uint32_t  SHCSR;                             /*!< (@ 0xE000ED24) System Handler Control and State Register              */\r
+  __IO uint32_t  CFSR;                              /*!< (@ 0xE000ED28) Configurable Fault Status Register                     */\r
+  __IO uint32_t  HFSR;                              /*!< (@ 0xE000ED2C) HardFault Status Register                              */\r
+  __I  uint32_t  RESERVED9;\r
+  __IO uint32_t  MMFAR;                             /*!< (@ 0xE000ED34) MemManage Fault Address Register                       */\r
+  __IO uint32_t  BFAR;                              /*!< (@ 0xE000ED38) BusFault Address Register                              */\r
+  __IO uint32_t  AFSR;                              /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register                        */\r
+  __I  uint32_t  RESERVED10[18];\r
+  __IO uint32_t  CPACR;                             /*!< (@ 0xE000ED88) Coprocessor Access Control Register                    */\r
+  __I  uint32_t  RESERVED11;\r
+  __I  uint32_t  MPU_TYPE;                          /*!< (@ 0xE000ED90) MPU Type Register                                      */\r
+  __IO uint32_t  MPU_CTRL;                          /*!< (@ 0xE000ED94) MPU Control Register                                   */\r
+  __IO uint32_t  MPU_RNR;                           /*!< (@ 0xE000ED98) MPU Region Number Register                             */\r
+  __IO uint32_t  MPU_RBAR;                          /*!< (@ 0xE000ED9C) MPU Region Base Address Register                       */\r
+  __IO uint32_t  MPU_RASR;                          /*!< (@ 0xE000EDA0) MPU Region Attribute and Size Register                 */\r
+  __IO uint32_t  MPU_RBAR_A1;                       /*!< (@ 0xE000EDA4) MPU Region Base Address Register A1                    */\r
+  __IO uint32_t  MPU_RASR_A1;                       /*!< (@ 0xE000EDA8) MPU Region Attribute and Size Register A1              */\r
+  __IO uint32_t  MPU_RBAR_A2;                       /*!< (@ 0xE000EDAC) MPU Region Base Address Register A2                    */\r
+  __IO uint32_t  MPU_RASR_A2;                       /*!< (@ 0xE000EDB0) MPU Region Attribute and Size Register A2              */\r
+  __IO uint32_t  MPU_RBAR_A3;                       /*!< (@ 0xE000EDB4) MPU Region Base Address Register A3                    */\r
+  __IO uint32_t  MPU_RASR_A3;                       /*!< (@ 0xE000EDB8) MPU Region Attribute and Size Register A3              */\r
+  __I  uint32_t  RESERVED12[81];\r
+  __O  uint32_t  STIR;                              /*!< (@ 0xE000EF00) Software Trigger Interrupt Register                    */\r
+  __I  uint32_t  RESERVED13[12];\r
+  __IO uint32_t  FPCCR;                             /*!< (@ 0xE000EF34) Floating-point Context Control Register                */\r
+  __IO uint32_t  FPCAR;                             /*!< (@ 0xE000EF38) Floating-point Context Address Register                */\r
+  __IO uint32_t  FPDSCR;                            /*!< (@ 0xE000EF3C) Floating-point Default Status Control Register         */\r
+} PPB_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       DLR                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief DMA Line Router (DLR)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004900) DLR Structure                                          */\r
+  __I  uint32_t  OVRSTAT;                           /*!< (@ 0x50004900) Overrun Status                                         */\r
+  __O  uint32_t  OVRCLR;                            /*!< (@ 0x50004904) Overrun Clear                                          */\r
+  __IO uint32_t  SRSEL0;                            /*!< (@ 0x50004908) Service Request Selection 0                            */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  LNEN;                              /*!< (@ 0x50004910) Line Enable                                            */\r
+} DLR_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   ERU [ERU0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Event Request Unit 0 (ERU)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004800) ERU Structure                                          */\r
+  __IO uint32_t  EXISEL;                            /*!< (@ 0x50004800) Event Input Select                                     */\r
+  __I  uint32_t  RESERVED0[3];\r
+  __IO uint32_t  EXICON[4];                         /*!< (@ 0x50004810) Event Input Control                                    */\r
+  __IO uint32_t  EXOCON[4];                         /*!< (@ 0x50004820) Event Output Trigger Control                           */\r
+} ERU_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     GPDMA0                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief General Purpose DMA Unit 0 (GPDMA0)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x500142C0) GPDMA0 Structure                                       */\r
+  __IO uint32_t  RAWTFR;                            /*!< (@ 0x500142C0) Raw IntTfr Status                                      */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  RAWBLOCK;                          /*!< (@ 0x500142C8) Raw IntBlock Status                                    */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  RAWSRCTRAN;                        /*!< (@ 0x500142D0) Raw IntSrcTran Status                                  */\r
+  __I  uint32_t  RESERVED2;\r
+  __IO uint32_t  RAWDSTTRAN;                        /*!< (@ 0x500142D8) Raw IntBlock Status                                    */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  RAWERR;                            /*!< (@ 0x500142E0) Raw IntErr Status                                      */\r
+  __I  uint32_t  RESERVED4;\r
+  __I  uint32_t  STATUSTFR;                         /*!< (@ 0x500142E8) IntTfr Status                                          */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  STATUSBLOCK;                       /*!< (@ 0x500142F0) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED6;\r
+  __I  uint32_t  STATUSSRCTRAN;                     /*!< (@ 0x500142F8) IntSrcTran Status                                      */\r
+  __I  uint32_t  RESERVED7;\r
+  __I  uint32_t  STATUSDSTTRAN;                     /*!< (@ 0x50014300) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED8;\r
+  __I  uint32_t  STATUSERR;                         /*!< (@ 0x50014308) IntErr Status                                          */\r
+  __I  uint32_t  RESERVED9;\r
+  __IO uint32_t  MASKTFR;                           /*!< (@ 0x50014310) Mask for Raw IntTfr Status                             */\r
+  __I  uint32_t  RESERVED10;\r
+  __IO uint32_t  MASKBLOCK;                         /*!< (@ 0x50014318) Mask for Raw IntBlock Status                           */\r
+  __I  uint32_t  RESERVED11;\r
+  __IO uint32_t  MASKSRCTRAN;                       /*!< (@ 0x50014320) Mask for Raw IntSrcTran Status                         */\r
+  __I  uint32_t  RESERVED12;\r
+  __IO uint32_t  MASKDSTTRAN;                       /*!< (@ 0x50014328) Mask for Raw IntBlock Status                           */\r
+  __I  uint32_t  RESERVED13;\r
+  __IO uint32_t  MASKERR;                           /*!< (@ 0x50014330) Mask for Raw IntErr Status                             */\r
+  __I  uint32_t  RESERVED14;\r
+  __O  uint32_t  CLEARTFR;                          /*!< (@ 0x50014338) IntTfr Status                                          */\r
+  __I  uint32_t  RESERVED15;\r
+  __O  uint32_t  CLEARBLOCK;                        /*!< (@ 0x50014340) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED16;\r
+  __O  uint32_t  CLEARSRCTRAN;                      /*!< (@ 0x50014348) IntSrcTran Status                                      */\r
+  __I  uint32_t  RESERVED17;\r
+  __O  uint32_t  CLEARDSTTRAN;                      /*!< (@ 0x50014350) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED18;\r
+  __O  uint32_t  CLEARERR;                          /*!< (@ 0x50014358) IntErr Status                                          */\r
+  __I  uint32_t  RESERVED19;\r
+  __I  uint32_t  STATUSINT;                         /*!< (@ 0x50014360) Combined Interrupt Status Register                     */\r
+  __I  uint32_t  RESERVED20;\r
+  __IO uint32_t  REQSRCREG;                         /*!< (@ 0x50014368) Source Software Transaction Request Register           */\r
+  __I  uint32_t  RESERVED21;\r
+  __IO uint32_t  REQDSTREG;                         /*!< (@ 0x50014370) Destination Software Transaction Request Register      */\r
+  __I  uint32_t  RESERVED22;\r
+  __IO uint32_t  SGLREQSRCREG;                      /*!< (@ 0x50014378) Single Source Transaction Request Register             */\r
+  __I  uint32_t  RESERVED23;\r
+  __IO uint32_t  SGLREQDSTREG;                      /*!< (@ 0x50014380) Single Destination Transaction Request Register        */\r
+  __I  uint32_t  RESERVED24;\r
+  __IO uint32_t  LSTSRCREG;                         /*!< (@ 0x50014388) Last Source Transaction Request Register               */\r
+  __I  uint32_t  RESERVED25;\r
+  __IO uint32_t  LSTDSTREG;                         /*!< (@ 0x50014390) Last Destination Transaction Request Register          */\r
+  __I  uint32_t  RESERVED26;\r
+  __IO uint32_t  DMACFGREG;                         /*!< (@ 0x50014398) GPDMA Configuration Register                           */\r
+  __I  uint32_t  RESERVED27;\r
+  __IO uint32_t  CHENREG;                           /*!< (@ 0x500143A0) GPDMA Channel Enable Register                          */\r
+  __I  uint32_t  RESERVED28;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x500143A8) GPDMA0 ID Register                                     */\r
+  __I  uint32_t  RESERVED29[19];\r
+  __I  uint32_t  TYPE;                              /*!< (@ 0x500143F8) GPDMA Component Type                                   */\r
+  __I  uint32_t  VERSION;                           /*!< (@ 0x500143FC) DMA Component Version                                  */\r
+} GPDMA0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================            GPDMA0_CH0_1 [GPDMA0_CH0]           ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief General Purpose DMA Unit 0 (GPDMA0_CH0_1)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50014000) GPDMA0_CH0_1 Structure                                 */\r
+  __IO uint32_t  SAR;                               /*!< (@ 0x50014000) Source Address Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DAR;                               /*!< (@ 0x50014008) Destination Address Register                           */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  LLP;                               /*!< (@ 0x50014010) Linked List Pointer Register                           */\r
+  __I  uint32_t  RESERVED2;\r
+  __IO uint32_t  CTLL;                              /*!< (@ 0x50014018) Control Register Low                                   */\r
+  __IO uint32_t  CTLH;                              /*!< (@ 0x5001401C) Control Register High                                  */\r
+  __IO uint32_t  SSTAT;                             /*!< (@ 0x50014020) Source Status Register                                 */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  DSTAT;                             /*!< (@ 0x50014028) Destination Status Register                            */\r
+  __I  uint32_t  RESERVED4;\r
+  __IO uint32_t  SSTATAR;                           /*!< (@ 0x50014030) Source Status Address Register                         */\r
+  __I  uint32_t  RESERVED5;\r
+  __IO uint32_t  DSTATAR;                           /*!< (@ 0x50014038) Destination Status Address Register                    */\r
+  __I  uint32_t  RESERVED6;\r
+  __IO uint32_t  CFGL;                              /*!< (@ 0x50014040) Configuration Register Low                             */\r
+  __IO uint32_t  CFGH;                              /*!< (@ 0x50014044) Configuration Register High                            */\r
+  __IO uint32_t  SGR;                               /*!< (@ 0x50014048) Source Gather Register                                 */\r
+  __I  uint32_t  RESERVED7;\r
+  __IO uint32_t  DSR;                               /*!< (@ 0x50014050) Destination Scatter Register                           */\r
+} GPDMA0_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================            GPDMA0_CH2_7 [GPDMA0_CH2]           ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief General Purpose DMA Unit 0 (GPDMA0_CH2_7)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x500140B0) GPDMA0_CH2_7 Structure                                 */\r
+  __IO uint32_t  SAR;                               /*!< (@ 0x500140B0) Source Address Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DAR;                               /*!< (@ 0x500140B8) Destination Address Register                           */\r
+  __I  uint32_t  RESERVED1[3];\r
+  __IO uint32_t  CTLL;                              /*!< (@ 0x500140C8) Control Register Low                                   */\r
+  __IO uint32_t  CTLH;                              /*!< (@ 0x500140CC) Control Register High                                  */\r
+  __I  uint32_t  RESERVED2[8];\r
+  __IO uint32_t  CFGL;                              /*!< (@ 0x500140F0) Configuration Register Low                             */\r
+  __IO uint32_t  CFGH;                              /*!< (@ 0x500140F4) Configuration Register High                            */\r
+} GPDMA0_CH2_7_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       FCE                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Flexible CRC Engine (FCE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50020000) FCE Structure                                          */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x50020000) Clock Control Register                                 */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50020008) Module Identification Register                         */\r
+} FCE_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                FCE_KE [FCE_KE0]                ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Flexible CRC Engine (FCE_KE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50020020) FCE_KE Structure                                       */\r
+  __IO uint32_t  IR;                                /*!< (@ 0x50020020) Input Register                                         */\r
+  __I  uint32_t  RES;                               /*!< (@ 0x50020024) CRC Result Register                                    */\r
+  __IO uint32_t  CFG;                               /*!< (@ 0x50020028) CRC Configuration Register                             */\r
+  __IO uint32_t  STS;                               /*!< (@ 0x5002002C) CRC Status Register                                    */\r
+  __IO uint32_t  LENGTH;                            /*!< (@ 0x50020030) CRC Length Register                                    */\r
+  __IO uint32_t  CHECK;                             /*!< (@ 0x50020034) CRC Check Register                                     */\r
+  __IO uint32_t  CRC;                               /*!< (@ 0x50020038) CRC Register                                           */\r
+  __IO uint32_t  CTR;                               /*!< (@ 0x5002003C) CRC Test Register                                      */\r
+} FCE_KE_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   PBA [PBA0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Peripheral Bridge AHB 0 (PBA)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40000000) PBA Structure                                          */\r
+  __IO uint32_t  STS;                               /*!< (@ 0x40000000) Peripheral Bridge Status Register                      */\r
+  __I  uint32_t  WADDR;                             /*!< (@ 0x40000004) PBA Write Error Address Register                       */\r
+} PBA_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                 FLASH [FLASH0]                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Flash Memory Controller (FLASH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x58001000) FLASH Structure                                        */\r
+  __I  uint32_t  RESERVED0[1026];\r
+  __I  uint32_t  ID;                                /*!< (@ 0x58002008) Flash Module Identification Register                   */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  FSR;                               /*!< (@ 0x58002010) Flash Status Register                                  */\r
+  __IO uint32_t  FCON;                              /*!< (@ 0x58002014) Flash Configuration Register                           */\r
+  __IO uint32_t  MARP;                              /*!< (@ 0x58002018) Margin Control Register PFLASH                         */\r
+  __I  uint32_t  RESERVED2;\r
+  __I  uint32_t  PROCON0;                           /*!< (@ 0x58002020) Flash Protection Configuration Register User\r
+                                                         0                                                                     */\r
+  __I  uint32_t  PROCON1;                           /*!< (@ 0x58002024) Flash Protection Configuration Register User\r
+                                                         1                                                                     */\r
+  __I  uint32_t  PROCON2;                           /*!< (@ 0x58002028) Flash Protection Configuration Register User\r
+                                                         2                                                                     */\r
+} FLASH0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PREF                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Prefetch Unit (PREF)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x58004000) PREF Structure                                         */\r
+  __IO uint32_t  PCON;                              /*!< (@ 0x58004000) Prefetch Configuration Register                        */\r
+} PREF_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   PMU [PMU0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Program Management Unit (PMU)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x58000508) PMU Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x58000508) PMU0 Identification Register                           */\r
+} PMU0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       WDT                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Watch Dog Timer (WDT)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50008000) WDT Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50008000) WDT ID Register                                        */\r
+  __IO uint32_t  CTR;                               /*!< (@ 0x50008004) WDT Control Register                                   */\r
+  __O  uint32_t  SRV;                               /*!< (@ 0x50008008) WDT Service Register                                   */\r
+  __I  uint32_t  TIM;                               /*!< (@ 0x5000800C) WDT Timer Register                                     */\r
+  __IO uint32_t  WLB;                               /*!< (@ 0x50008010) WDT Window Lower Bound Register                        */\r
+  __IO uint32_t  WUB;                               /*!< (@ 0x50008014) WDT Window Upper Bound Register                        */\r
+  __I  uint32_t  WDTSTS;                            /*!< (@ 0x50008018) WDT Status Register                                    */\r
+  __O  uint32_t  WDTCLR;                            /*!< (@ 0x5000801C) WDT Clear Register                                     */\r
+} WDT_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       RTC                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Real Time Clock (RTC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004A00) RTC Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50004A00) RTC ID Register                                        */\r
+  __IO uint32_t  CTR;                               /*!< (@ 0x50004A04) RTC Control Register                                   */\r
+  __I  uint32_t  RAWSTAT;                           /*!< (@ 0x50004A08) RTC Raw Service Request Register                       */\r
+  __I  uint32_t  STSSR;                             /*!< (@ 0x50004A0C) RTC Service Request Status Register                    */\r
+  __IO uint32_t  MSKSR;                             /*!< (@ 0x50004A10) RTC Service Request Mask Register                      */\r
+  __O  uint32_t  CLRSR;                             /*!< (@ 0x50004A14) RTC Clear Service Request Register                     */\r
+  __IO uint32_t  ATIM0;                             /*!< (@ 0x50004A18) RTC Alarm Time Register 0                              */\r
+  __IO uint32_t  ATIM1;                             /*!< (@ 0x50004A1C) RTC Alarm Time Register 1                              */\r
+  __IO uint32_t  TIM0;                              /*!< (@ 0x50004A20) RTC Time Register 0                                    */\r
+  __IO uint32_t  TIM1;                              /*!< (@ 0x50004A24) RTC Time Register 1                                    */\r
+} RTC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     SCU_CLK                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_CLK)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004600) SCU_CLK Structure                                      */\r
+  __I  uint32_t  CLKSTAT;                           /*!< (@ 0x50004600) Clock Status Register                                  */\r
+  __O  uint32_t  CLKSET;                            /*!< (@ 0x50004604) CLK Set Register                                       */\r
+  __O  uint32_t  CLKCLR;                            /*!< (@ 0x50004608) CLK Clear Register                                     */\r
+  __IO uint32_t  SYSCLKCR;                          /*!< (@ 0x5000460C) System Clock Control Register                          */\r
+  __IO uint32_t  CPUCLKCR;                          /*!< (@ 0x50004610) CPU Clock Control Register                             */\r
+  __IO uint32_t  PBCLKCR;                           /*!< (@ 0x50004614) Peripheral Bus Clock Control Register                  */\r
+  __IO uint32_t  USBCLKCR;                          /*!< (@ 0x50004618) USB Clock Control Register                             */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  CCUCLKCR;                          /*!< (@ 0x50004620) CCU Clock Control Register                             */\r
+  __IO uint32_t  WDTCLKCR;                          /*!< (@ 0x50004624) WDT Clock Control Register                             */\r
+  __IO uint32_t  EXTCLKCR;                          /*!< (@ 0x50004628) External Clock Control                                 */\r
+  __IO uint32_t  MLINKCLKCR;                        /*!< (@ 0x5000462C) Multi-Link Clock Control                               */\r
+  __IO uint32_t  SLEEPCR;                           /*!< (@ 0x50004630) Sleep Control Register                                 */\r
+  __IO uint32_t  DSLEEPCR;                          /*!< (@ 0x50004634) Deep Sleep Control Register                            */\r
+  __I  uint32_t  RESERVED1[2];\r
+  __I  uint32_t  CGATSTAT0;                         /*!< (@ 0x50004640) Peripheral 0 Clock Gating Status                       */\r
+  __O  uint32_t  CGATSET0;                          /*!< (@ 0x50004644) Peripheral 0 Clock Gating Set                          */\r
+  __O  uint32_t  CGATCLR0;                          /*!< (@ 0x50004648) Peripheral 0 Clock Gating Clear                        */\r
+  __I  uint32_t  CGATSTAT1;                         /*!< (@ 0x5000464C) Peripheral 1 Clock Gating Status                       */\r
+  __O  uint32_t  CGATSET1;                          /*!< (@ 0x50004650) Peripheral 1 Clock Gating Set                          */\r
+  __O  uint32_t  CGATCLR1;                          /*!< (@ 0x50004654) Peripheral 1 Clock Gating Clear                        */\r
+  __I  uint32_t  CGATSTAT2;                         /*!< (@ 0x50004658) Peripheral 2 Clock Gating Status                       */\r
+  __O  uint32_t  CGATSET2;                          /*!< (@ 0x5000465C) Peripheral 2 Clock Gating Set                          */\r
+  __O  uint32_t  CGATCLR2;                          /*!< (@ 0x50004660) Peripheral 2 Clock Gating Clear                        */\r
+} SCU_CLK_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     SCU_OSC                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_OSC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004700) SCU_OSC Structure                                      */\r
+  __I  uint32_t  OSCHPSTAT;                         /*!< (@ 0x50004700) OSC_HP Status Register                                 */\r
+  __IO uint32_t  OSCHPCTRL;                         /*!< (@ 0x50004704) OSC_HP Control Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  CLKCALCONST;                       /*!< (@ 0x5000470C) Clock Calibration Constant Register                    */\r
+} SCU_OSC_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     SCU_PLL                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_PLL)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004710) SCU_PLL Structure                                      */\r
+  __I  uint32_t  PLLSTAT;                           /*!< (@ 0x50004710) PLL Status Register                                    */\r
+  __IO uint32_t  PLLCON0;                           /*!< (@ 0x50004714) PLL Configuration 0 Register                           */\r
+  __IO uint32_t  PLLCON1;                           /*!< (@ 0x50004718) PLL Configuration 1 Register                           */\r
+  __IO uint32_t  PLLCON2;                           /*!< (@ 0x5000471C) PLL Configuration 2 Register                           */\r
+  __I  uint32_t  USBPLLSTAT;                        /*!< (@ 0x50004720) USB PLL Status Register                                */\r
+  __IO uint32_t  USBPLLCON;                         /*!< (@ 0x50004724) USB PLL Configuration Register                         */\r
+  __I  uint32_t  RESERVED0[4];\r
+  __I  uint32_t  CLKMXSTAT;                         /*!< (@ 0x50004738) Clock Multiplexing Status Register                     */\r
+} SCU_PLL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   SCU_GENERAL                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_GENERAL)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004000) SCU_GENERAL Structure                                  */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50004000) SCU Module ID Register                                 */\r
+  __I  uint32_t  IDCHIP;                            /*!< (@ 0x50004004) Chip ID Register                                       */\r
+  __I  uint32_t  IDMANUF;                           /*!< (@ 0x50004008) Manufactory ID Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  STCON;                             /*!< (@ 0x50004010) Startup Configuration Register                         */\r
+  __I  uint32_t  RESERVED1[6];\r
+  __IO uint32_t  GPR[2];                            /*!< (@ 0x5000402C) General Purpose Register 0                             */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  CCUCON;                            /*!< (@ 0x5000404C) CCU Control Register                                   */\r
+  __I  uint32_t  RESERVED3[15];\r
+  __IO uint32_t  DTSCON;                            /*!< (@ 0x5000408C) Die Temperature Sensor Control Register                */\r
+  __I  uint32_t  DTSSTAT;                           /*!< (@ 0x50004090) Die Temperature Sensor Status Register                 */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  GORCEN[2];                         /*!< (@ 0x500040A0) Out of Range Comparator Enable Register 0              */\r
+  __IO uint32_t  DTEMPLIM;                          /*!< (@ 0x500040A8) Die Temperature Sensor Limit Register                  */\r
+  __I  uint32_t  DTEMPALARM;                        /*!< (@ 0x500040AC) Die Temperature Sensor Alarm Register                  */\r
+  __I  uint32_t  RESERVED5[5];\r
+  __I  uint32_t  MIRRSTS;                           /*!< (@ 0x500040C4) Mirror Write Status Register                           */\r
+  __IO uint32_t  RMACR;                             /*!< (@ 0x500040C8) Retention Memory Access Control Register               */\r
+  __IO uint32_t  RMDATA;                            /*!< (@ 0x500040CC) Retention Memory Access Data Register                  */\r
+  __I  uint32_t  MIRRALLSTAT;                       /*!< (@ 0x500040D0) Mirror All Status                                      */\r
+  __O  uint32_t  MIRRALLREQ;                        /*!< (@ 0x500040D4) Mirror All Request                                     */\r
+} SCU_GENERAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  SCU_INTERRUPT                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_INTERRUPT)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004074) SCU_INTERRUPT Structure                                */\r
+  __I  uint32_t  SRSTAT;                            /*!< (@ 0x50004074) SCU Service Request Status                             */\r
+  __I  uint32_t  SRRAW;                             /*!< (@ 0x50004078) SCU Raw Service Request Status                         */\r
+  __IO uint32_t  SRMSK;                             /*!< (@ 0x5000407C) SCU Service Request Mask                               */\r
+  __O  uint32_t  SRCLR;                             /*!< (@ 0x50004080) SCU Service Request Clear                              */\r
+  __O  uint32_t  SRSET;                             /*!< (@ 0x50004084) SCU Service Request Set                                */\r
+  __IO uint32_t  NMIREQEN;                          /*!< (@ 0x50004088) SCU Service Request Mask                               */\r
+} SCU_INTERRUPT_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   SCU_PARITY                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_PARITY)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x5000413C) SCU_PARITY Structure                                   */\r
+  __IO uint32_t  PEEN;                              /*!< (@ 0x5000413C) Parity Error Enable Register                           */\r
+  __IO uint32_t  MCHKCON;                           /*!< (@ 0x50004140) Memory Checking Control Register                       */\r
+  __IO uint32_t  PETE;                              /*!< (@ 0x50004144) Parity Error Trap Enable Register                      */\r
+  __IO uint32_t  PERSTEN;                           /*!< (@ 0x50004148) Parity Error Reset Enable Register                     */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  PEFLAG;                            /*!< (@ 0x50004150) Parity Error Flag Register                             */\r
+  __IO uint32_t  PMTPR;                             /*!< (@ 0x50004154) Parity Memory Test Pattern Register                    */\r
+  __IO uint32_t  PMTSR;                             /*!< (@ 0x50004158) Parity Memory Test Select Register                     */\r
+} SCU_PARITY_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    SCU_TRAP                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_TRAP)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004160) SCU_TRAP Structure                                     */\r
+  __I  uint32_t  TRAPSTAT;                          /*!< (@ 0x50004160) Trap Status Register                                   */\r
+  __I  uint32_t  TRAPRAW;                           /*!< (@ 0x50004164) Trap Raw Status Register                               */\r
+  __IO uint32_t  TRAPDIS;                           /*!< (@ 0x50004168) Trap Disable Register                                  */\r
+  __O  uint32_t  TRAPCLR;                           /*!< (@ 0x5000416C) Trap Clear Register                                    */\r
+  __O  uint32_t  TRAPSET;                           /*!< (@ 0x50004170) Trap Set Register                                      */\r
+} SCU_TRAP_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  SCU_HIBERNATE                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_HIBERNATE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004300) SCU_HIBERNATE Structure                                */\r
+  __I  uint32_t  HDSTAT;                            /*!< (@ 0x50004300) Hibernate Domain Status Register                       */\r
+  __O  uint32_t  HDCLR;                             /*!< (@ 0x50004304) Hibernate Domain Status Clear Register                 */\r
+  __O  uint32_t  HDSET;                             /*!< (@ 0x50004308) Hibernate Domain Status Set Register                   */\r
+  __IO uint32_t  HDCR;                              /*!< (@ 0x5000430C) Hibernate Domain Control Register                      */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  OSCSICTRL;                         /*!< (@ 0x50004314) fOSI Control Register                                  */\r
+  __I  uint32_t  OSCULSTAT;                         /*!< (@ 0x50004318) OSC_ULP Status Register                                */\r
+  __IO uint32_t  OSCULCTRL;                         /*!< (@ 0x5000431C) OSC_ULP Control Register                               */\r
+  __IO uint32_t  LPACCONF;                          /*!< (@ 0x50004320) Analog Wake-up Configuration Register                  */\r
+  __IO uint32_t  LPACTH0;                           /*!< (@ 0x50004324) LPAC Threshold Register 0                              */\r
+  __IO uint32_t  LPACTH1;                           /*!< (@ 0x50004328) LPAC Threshold Register 1                              */\r
+  __I  uint32_t  LPACST;                            /*!< (@ 0x5000432C) Hibernate Analog Control State Register                */\r
+  __O  uint32_t  LPACCLR;                           /*!< (@ 0x50004330) LPAC Control Clear Register                            */\r
+  __O  uint32_t  LPACSET;                           /*!< (@ 0x50004334) LPAC Control Set Register                              */\r
+  __I  uint32_t  HINTST;                            /*!< (@ 0x50004338) Hibernate Internal Control State Register              */\r
+  __O  uint32_t  HINTCLR;                           /*!< (@ 0x5000433C) Hibernate Internal Control Clear Register              */\r
+  __O  uint32_t  HINTSET;                           /*!< (@ 0x50004340) Hibernate Internal Control Set Register                */\r
+} SCU_HIBERNATE_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    SCU_POWER                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_POWER)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004200) SCU_POWER Structure                                    */\r
+  __I  uint32_t  PWRSTAT;                           /*!< (@ 0x50004200) PCU Status Register                                    */\r
+  __O  uint32_t  PWRSET;                            /*!< (@ 0x50004204) PCU Set Control Register                               */\r
+  __O  uint32_t  PWRCLR;                            /*!< (@ 0x50004208) PCU Clear Control Register                             */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  EVRSTAT;                           /*!< (@ 0x50004210) EVR Status Register                                    */\r
+  __I  uint32_t  EVRVADCSTAT;                       /*!< (@ 0x50004214) EVR VADC Status Register                               */\r
+  __I  uint32_t  RESERVED1[5];\r
+  __IO uint32_t  PWRMON;                            /*!< (@ 0x5000422C) Power Monitor Control                                  */\r
+} SCU_POWER_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    SCU_RESET                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_RESET)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004400) SCU_RESET Structure                                    */\r
+  __I  uint32_t  RSTSTAT;                           /*!< (@ 0x50004400) RCU Reset Status                                       */\r
+  __O  uint32_t  RSTSET;                            /*!< (@ 0x50004404) RCU Reset Set Register                                 */\r
+  __O  uint32_t  RSTCLR;                            /*!< (@ 0x50004408) RCU Reset Clear Register                               */\r
+  __I  uint32_t  PRSTAT0;                           /*!< (@ 0x5000440C) RCU Peripheral 0 Reset Status                          */\r
+  __O  uint32_t  PRSET0;                            /*!< (@ 0x50004410) RCU Peripheral 0 Reset Set                             */\r
+  __O  uint32_t  PRCLR0;                            /*!< (@ 0x50004414) RCU Peripheral 0 Reset Clear                           */\r
+  __I  uint32_t  PRSTAT1;                           /*!< (@ 0x50004418) RCU Peripheral 1 Reset Status                          */\r
+  __O  uint32_t  PRSET1;                            /*!< (@ 0x5000441C) RCU Peripheral 1 Reset Set                             */\r
+  __O  uint32_t  PRCLR1;                            /*!< (@ 0x50004420) RCU Peripheral 1 Reset Clear                           */\r
+  __I  uint32_t  PRSTAT2;                           /*!< (@ 0x50004424) RCU Peripheral 2 Reset Status                          */\r
+  __O  uint32_t  PRSET2;                            /*!< (@ 0x50004428) RCU Peripheral 2 Reset Set                             */\r
+  __O  uint32_t  PRCLR2;                            /*!< (@ 0x5000442C) RCU Peripheral 2 Reset Clear                           */\r
+} SCU_RESET_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                 LEDTS [LEDTS0]                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief LED and Touch Sense Unit 0 (LEDTS)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48010000) LEDTS Structure                                        */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x48010000) Module Identification Register                         */\r
+  __IO uint32_t  GLOBCTL;                           /*!< (@ 0x48010004) Global Control Register                                */\r
+  __IO uint32_t  FNCTL;                             /*!< (@ 0x48010008) Function Control Register                              */\r
+  __O  uint32_t  EVFR;                              /*!< (@ 0x4801000C) Event Flag Register                                    */\r
+  __IO uint32_t  TSVAL;                             /*!< (@ 0x48010010) Touch-sense TS-Counter Value                           */\r
+  __IO uint32_t  LINE0;                             /*!< (@ 0x48010014) Line Pattern Register 0                                */\r
+  __IO uint32_t  LINE1;                             /*!< (@ 0x48010018) Line Pattern Register 1                                */\r
+  __IO uint32_t  LDCMP0;                            /*!< (@ 0x4801001C) LED Compare Register 0                                 */\r
+  __IO uint32_t  LDCMP1;                            /*!< (@ 0x48010020) LED Compare Register 1                                 */\r
+  __IO uint32_t  TSCMP0;                            /*!< (@ 0x48010024) Touch-sense Compare Register 0                         */\r
+  __IO uint32_t  TSCMP1;                            /*!< (@ 0x48010028) Touch-sense Compare Register 1                         */\r
+} LEDTS0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    ETH0_CON                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Ethernet Control Register (ETH0_CON)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004040) ETH0_CON Structure                                     */\r
+  __IO uint32_t  CON;                          /*!< (@ 0x50004040) Ethernet 0 Port Control Register                       */\r
+} ETH0_CON_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   ETH [ETH0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Ethernet Unit 0 (ETH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x5000C000) ETH Structure                                          */\r
+  __IO uint32_t  MAC_CONFIGURATION;                 /*!< (@ 0x5000C000) MAC Configuration Register                             */\r
+  __IO uint32_t  MAC_FRAME_FILTER;                  /*!< (@ 0x5000C004) MAC Frame Filter                                       */\r
+  __IO uint32_t  HASH_TABLE_HIGH;                   /*!< (@ 0x5000C008) Hash Table High Register                               */\r
+  __IO uint32_t  HASH_TABLE_LOW;                    /*!< (@ 0x5000C00C) Hash Table Low Register                                */\r
+  __IO uint32_t  GMII_ADDRESS;                      /*!< (@ 0x5000C010) MII Address Register                                   */\r
+  __IO uint32_t  GMII_DATA;                         /*!< (@ 0x5000C014) MII Data Register                                      */\r
+  __IO uint32_t  FLOW_CONTROL;                      /*!< (@ 0x5000C018) Flow Control Register                                  */\r
+  __IO uint32_t  VLAN_TAG;                          /*!< (@ 0x5000C01C) VLAN Tag Register                                      */\r
+  __I  uint32_t  VERSION;                           /*!< (@ 0x5000C020) Version Register                                       */\r
+  __I  uint32_t  DEBUG;                             /*!< (@ 0x5000C024) Debug Register                                         */\r
+  __IO uint32_t  REMOTE_WAKE_UP_FRAME_FILTER;       /*!< (@ 0x5000C028) Remote Wake Up Frame Filter Register                   */\r
+  __IO uint32_t  PMT_CONTROL_STATUS;                /*!< (@ 0x5000C02C) PMT Control and Status Register                        */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __I  uint32_t  INTERRUPT_STATUS;                  /*!< (@ 0x5000C038) Interrupt Register                                     */\r
+  __IO uint32_t  INTERRUPT_MASK;                    /*!< (@ 0x5000C03C) Interrupt Mask Register                                */\r
+  __IO uint32_t  MAC_ADDRESS0_HIGH;                 /*!< (@ 0x5000C040) MAC Address0 High Register                             */\r
+  __IO uint32_t  MAC_ADDRESS0_LOW;                  /*!< (@ 0x5000C044) MAC Address0 Low Register                              */\r
+  __IO uint32_t  MAC_ADDRESS1_HIGH;                 /*!< (@ 0x5000C048) MAC Address1 High Register                             */\r
+  __IO uint32_t  MAC_ADDRESS1_LOW;                  /*!< (@ 0x5000C04C) MAC Address1 Low Register                              */\r
+  __IO uint32_t  MAC_ADDRESS2_HIGH;                 /*!< (@ 0x5000C050) MAC Address2 High Register                             */\r
+  __IO uint32_t  MAC_ADDRESS2_LOW;                  /*!< (@ 0x5000C054) MAC Address2 Low Register                              */\r
+  __IO uint32_t  MAC_ADDRESS3_HIGH;                 /*!< (@ 0x5000C058) MAC Address3 High Register                             */\r
+  __IO uint32_t  MAC_ADDRESS3_LOW;                  /*!< (@ 0x5000C05C) MAC Address3 Low Register                              */\r
+  __I  uint32_t  RESERVED1[40];\r
+  __IO uint32_t  MMC_CONTROL;                       /*!< (@ 0x5000C100) MMC Control Register                                   */\r
+  __I  uint32_t  MMC_RECEIVE_INTERRUPT;             /*!< (@ 0x5000C104) MMC Receive Interrupt Register                         */\r
+  __I  uint32_t  MMC_TRANSMIT_INTERRUPT;            /*!< (@ 0x5000C108) MMC Transmit Interrupt Register                        */\r
+  __IO uint32_t  MMC_RECEIVE_INTERRUPT_MASK;        /*!< (@ 0x5000C10C) MMC Reveive Interrupt Mask Register                    */\r
+  __IO uint32_t  MMC_TRANSMIT_INTERRUPT_MASK;       /*!< (@ 0x5000C110) MMC Transmit Interrupt Mask Register                   */\r
+  __I  uint32_t  TX_OCTET_COUNT_GOOD_BAD;           /*!< (@ 0x5000C114) Transmit Octet Count for Good and Bad Frames\r
+                                                         Register                                                              */\r
+  __I  uint32_t  TX_FRAME_COUNT_GOOD_BAD;           /*!< (@ 0x5000C118) Transmit Frame Count for Goodand Bad Frames Register   */\r
+  __I  uint32_t  TX_BROADCAST_FRAMES_GOOD;          /*!< (@ 0x5000C11C) Transmit Frame Count for Good Broadcast Frames         */\r
+  __I  uint32_t  TX_MULTICAST_FRAMES_GOOD;          /*!< (@ 0x5000C120) Transmit Frame Count for Good Multicast Frames         */\r
+  __I  uint32_t  TX_64OCTETS_FRAMES_GOOD_BAD;       /*!< (@ 0x5000C124) Transmit Octet Count for Good and Bad 64 Byte\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_65TO127OCTETS_FRAMES_GOOD_BAD;  /*!< (@ 0x5000C128) Transmit Octet Count for Good and Bad 65 to 127\r
+                                                         Bytes Frames                                                          */\r
+  __I  uint32_t  TX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C12C) Transmit Octet Count for Good and Bad 128 to\r
+                                                         255 Bytes Frames                                                      */\r
+  __I  uint32_t  TX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C130) Transmit Octet Count for Good and Bad 256 to\r
+                                                         511 Bytes Frames                                                      */\r
+  __I  uint32_t  TX_512TO1023OCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C134) Transmit Octet Count for Good and Bad 512 to\r
+                                                         1023 Bytes Frames                                                     */\r
+  __I  uint32_t  TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C138) Transmit Octet Count for Good and Bad 1024 to\r
+                                                         Maxsize Bytes Frames                                                  */\r
+  __I  uint32_t  TX_UNICAST_FRAMES_GOOD_BAD;        /*!< (@ 0x5000C13C) Transmit Frame Count for Good and Bad Unicast\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_MULTICAST_FRAMES_GOOD_BAD;      /*!< (@ 0x5000C140) Transmit Frame Count for Good and Bad Multicast\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_BROADCAST_FRAMES_GOOD_BAD;      /*!< (@ 0x5000C144) Transmit Frame Count for Good and Bad Broadcast\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_UNDERFLOW_ERROR_FRAMES;         /*!< (@ 0x5000C148) Transmit Frame Count for Underflow Error Frames        */\r
+  __I  uint32_t  TX_SINGLE_COLLISION_GOOD_FRAMES;   /*!< (@ 0x5000C14C) Transmit Frame Count for Frames Transmitted after\r
+                                                         Single Collision                                                      */\r
+  __I  uint32_t  TX_MULTIPLE_COLLISION_GOOD_FRAMES; /*!< (@ 0x5000C150) Transmit Frame Count for Frames Transmitted after\r
+                                                         Multiple Collision                                                    */\r
+  __I  uint32_t  TX_DEFERRED_FRAMES;                /*!< (@ 0x5000C154) Tx Deferred Frames Register                            */\r
+  __I  uint32_t  TX_LATE_COLLISION_FRAMES;          /*!< (@ 0x5000C158) Transmit Frame Count for Late Collision Error\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_EXCESSIVE_COLLISION_FRAMES;     /*!< (@ 0x5000C15C) Transmit Frame Count for Excessive Collision\r
+                                                         Error Frames                                                          */\r
+  __I  uint32_t  TX_CARRIER_ERROR_FRAMES;           /*!< (@ 0x5000C160) Transmit Frame Count for Carrier Sense Error\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_OCTET_COUNT_GOOD;               /*!< (@ 0x5000C164) Tx Octet Count Good Register                           */\r
+  __I  uint32_t  TX_FRAME_COUNT_GOOD;               /*!< (@ 0x5000C168) Tx Frame Count Good Register                           */\r
+  __I  uint32_t  TX_EXCESSIVE_DEFERRAL_ERROR;       /*!< (@ 0x5000C16C) Transmit Frame Count for Excessive Deferral Error\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_PAUSE_FRAMES;                   /*!< (@ 0x5000C170) Transmit Frame Count for Good PAUSE Frames             */\r
+  __I  uint32_t  TX_VLAN_FRAMES_GOOD;               /*!< (@ 0x5000C174) Transmit Frame Count for Good VLAN Frames              */\r
+  __I  uint32_t  TX_OSIZE_FRAMES_GOOD;              /*!< (@ 0x5000C178) Transmit Frame Count for Good Oversize Frames          */\r
+  __I  uint32_t  RESERVED2;\r
+  __I  uint32_t  RX_FRAMES_COUNT_GOOD_BAD;          /*!< (@ 0x5000C180) Receive Frame Count for Good and Bad Frames            */\r
+  __I  uint32_t  RX_OCTET_COUNT_GOOD_BAD;           /*!< (@ 0x5000C184) Receive Octet Count for Good and Bad Frames            */\r
+  __I  uint32_t  RX_OCTET_COUNT_GOOD;               /*!< (@ 0x5000C188) Rx Octet Count Good Register                           */\r
+  __I  uint32_t  RX_BROADCAST_FRAMES_GOOD;          /*!< (@ 0x5000C18C) Receive Frame Count for Good Broadcast Frames          */\r
+  __I  uint32_t  RX_MULTICAST_FRAMES_GOOD;          /*!< (@ 0x5000C190) Receive Frame Count for Good Multicast Frames          */\r
+  __I  uint32_t  RX_CRC_ERROR_FRAMES;               /*!< (@ 0x5000C194) Receive Frame Count for CRC Error Frames               */\r
+  __I  uint32_t  RX_ALIGNMENT_ERROR_FRAMES;         /*!< (@ 0x5000C198) Receive Frame Count for Alignment Error Frames         */\r
+  __I  uint32_t  RX_RUNT_ERROR_FRAMES;              /*!< (@ 0x5000C19C) Receive Frame Count for Runt Error Frames              */\r
+  __I  uint32_t  RX_JABBER_ERROR_FRAMES;            /*!< (@ 0x5000C1A0) Receive Frame Count for Jabber Error Frames            */\r
+  __I  uint32_t  RX_UNDERSIZE_FRAMES_GOOD;          /*!< (@ 0x5000C1A4) Receive Frame Count for Undersize Frames               */\r
+  __I  uint32_t  RX_OVERSIZE_FRAMES_GOOD;           /*!< (@ 0x5000C1A8) Rx Oversize Frames Good Register                       */\r
+  __I  uint32_t  RX_64OCTETS_FRAMES_GOOD_BAD;       /*!< (@ 0x5000C1AC) Receive Frame Count for Good and Bad 64 Byte\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  RX_65TO127OCTETS_FRAMES_GOOD_BAD;  /*!< (@ 0x5000C1B0) Receive Frame Count for Good and Bad 65 to 127\r
+                                                         Bytes Frames                                                          */\r
+  __I  uint32_t  RX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B4) Receive Frame Count for Good and Bad 128 to 255\r
+                                                         Bytes Frames                                                          */\r
+  __I  uint32_t  RX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B8) Receive Frame Count for Good and Bad 256 to 511\r
+                                                         Bytes Frames                                                          */\r
+  __I  uint32_t  RX_512TO1023OCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C1BC) Receive Frame Count for Good and Bad 512 to 1,023\r
+                                                         Bytes Frames                                                          */\r
+  __I  uint32_t  RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C1C0) Receive Frame Count for Good and Bad 1,024 to\r
+                                                         Maxsize Bytes Frames                                                  */\r
+  __I  uint32_t  RX_UNICAST_FRAMES_GOOD;            /*!< (@ 0x5000C1C4) Receive Frame Count for Good Unicast Frames            */\r
+  __I  uint32_t  RX_LENGTH_ERROR_FRAMES;            /*!< (@ 0x5000C1C8) Receive Frame Count for Length Error Frames            */\r
+  __I  uint32_t  RX_OUT_OF_RANGE_TYPE_FRAMES;       /*!< (@ 0x5000C1CC) Receive Frame Count for Out of Range Frames            */\r
+  __I  uint32_t  RX_PAUSE_FRAMES;                   /*!< (@ 0x5000C1D0) Receive Frame Count for PAUSE Frames                   */\r
+  __I  uint32_t  RX_FIFO_OVERFLOW_FRAMES;           /*!< (@ 0x5000C1D4) Receive Frame Count for FIFO Overflow Frames           */\r
+  __I  uint32_t  RX_VLAN_FRAMES_GOOD_BAD;           /*!< (@ 0x5000C1D8) Receive Frame Count for Good and Bad VLAN Frames       */\r
+  __I  uint32_t  RX_WATCHDOG_ERROR_FRAMES;          /*!< (@ 0x5000C1DC) Receive Frame Count for Watchdog Error Frames          */\r
+  __I  uint32_t  RX_RECEIVE_ERROR_FRAMES;           /*!< (@ 0x5000C1E0) Receive Frame Count for Receive Error Frames           */\r
+  __I  uint32_t  RX_CONTROL_FRAMES_GOOD;            /*!< (@ 0x5000C1E4) Receive Frame Count for Good Control Frames Frames     */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __IO uint32_t  MMC_IPC_RECEIVE_INTERRUPT_MASK;    /*!< (@ 0x5000C200) MMC Receive Checksum Offload Interrupt Mask Register   */\r
+  __I  uint32_t  RESERVED4;\r
+  __I  uint32_t  MMC_IPC_RECEIVE_INTERRUPT;         /*!< (@ 0x5000C208) MMC Receive Checksum Offload Interrupt Register        */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  RXIPV4_GOOD_FRAMES;                /*!< (@ 0x5000C210) RxIPv4 Good Frames Register                            */\r
+  __I  uint32_t  RXIPV4_HEADER_ERROR_FRAMES;        /*!< (@ 0x5000C214) Receive IPV4 Header Error Frame Counter Register       */\r
+  __I  uint32_t  RXIPV4_NO_PAYLOAD_FRAMES;          /*!< (@ 0x5000C218) Receive IPV4 No Payload Frame Counter Register         */\r
+  __I  uint32_t  RXIPV4_FRAGMENTED_FRAMES;          /*!< (@ 0x5000C21C) Receive IPV4 Fragmented Frame Counter Register         */\r
+  __I  uint32_t  RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES;/*!< (@ 0x5000C220) Receive IPV4 UDP Checksum Disabled Frame Counter\r
+                                                         Register                                                              */\r
+  __I  uint32_t  RXIPV6_GOOD_FRAMES;                /*!< (@ 0x5000C224) RxIPv6 Good Frames Register                            */\r
+  __I  uint32_t  RXIPV6_HEADER_ERROR_FRAMES;        /*!< (@ 0x5000C228) Receive IPV6 Header Error Frame Counter Register       */\r
+  __I  uint32_t  RXIPV6_NO_PAYLOAD_FRAMES;          /*!< (@ 0x5000C22C) Receive IPV6 No Payload Frame Counter Register         */\r
+  __I  uint32_t  RXUDP_GOOD_FRAMES;                 /*!< (@ 0x5000C230) RxUDP Good Frames Register                             */\r
+  __I  uint32_t  RXUDP_ERROR_FRAMES;                /*!< (@ 0x5000C234) RxUDP Error Frames Register                            */\r
+  __I  uint32_t  RXTCP_GOOD_FRAMES;                 /*!< (@ 0x5000C238) RxTCP Good Frames Register                             */\r
+  __I  uint32_t  RXTCP_ERROR_FRAMES;                /*!< (@ 0x5000C23C) RxTCP Error Frames Register                            */\r
+  __I  uint32_t  RXICMP_GOOD_FRAMES;                /*!< (@ 0x5000C240) RxICMP Good Frames Register                            */\r
+  __I  uint32_t  RXICMP_ERROR_FRAMES;               /*!< (@ 0x5000C244) RxICMP Error Frames Register                           */\r
+  __I  uint32_t  RESERVED6[2];\r
+  __I  uint32_t  RXIPV4_GOOD_OCTETS;                /*!< (@ 0x5000C250) RxIPv4 Good Octets Register                            */\r
+  __I  uint32_t  RXIPV4_HEADER_ERROR_OCTETS;        /*!< (@ 0x5000C254) Receive IPV4 Header Error Octet Counter Register       */\r
+  __I  uint32_t  RXIPV4_NO_PAYLOAD_OCTETS;          /*!< (@ 0x5000C258) Receive IPV4 No Payload Octet Counter Register         */\r
+  __I  uint32_t  RXIPV4_FRAGMENTED_OCTETS;          /*!< (@ 0x5000C25C) Receive IPV4 Fragmented Octet Counter Register         */\r
+  __I  uint32_t  RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS;/*!< (@ 0x5000C260) Receive IPV4 Fragmented Octet Counter Register         */\r
+  __I  uint32_t  RXIPV6_GOOD_OCTETS;                /*!< (@ 0x5000C264) RxIPv6 Good Octets Register                            */\r
+  __I  uint32_t  RXIPV6_HEADER_ERROR_OCTETS;        /*!< (@ 0x5000C268) Receive IPV6 Header Error Octet Counter Register       */\r
+  __I  uint32_t  RXIPV6_NO_PAYLOAD_OCTETS;          /*!< (@ 0x5000C26C) Receive IPV6 No Payload Octet Counter Register         */\r
+  __I  uint32_t  RXUDP_GOOD_OCTETS;                 /*!< (@ 0x5000C270) Receive UDP Good Octets Register                       */\r
+  __I  uint32_t  RXUDP_ERROR_OCTETS;                /*!< (@ 0x5000C274) Receive UDP Error Octets Register                      */\r
+  __I  uint32_t  RXTCP_GOOD_OCTETS;                 /*!< (@ 0x5000C278) Receive TCP Good Octets Register                       */\r
+  __I  uint32_t  RXTCP_ERROR_OCTETS;                /*!< (@ 0x5000C27C) Receive TCP Error Octets Register                      */\r
+  __I  uint32_t  RXICMP_GOOD_OCTETS;                /*!< (@ 0x5000C280) Receive ICMP Good Octets Register                      */\r
+  __I  uint32_t  RXICMP_ERROR_OCTETS;               /*!< (@ 0x5000C284) Receive ICMP Error Octets Register                     */\r
+  __I  uint32_t  RESERVED7[286];\r
+  __IO uint32_t  TIMESTAMP_CONTROL;                 /*!< (@ 0x5000C700) Timestamp Control Register                             */\r
+  __IO uint32_t  SUB_SECOND_INCREMENT;              /*!< (@ 0x5000C704) Sub-Second Increment Register                          */\r
+  __I  uint32_t  SYSTEM_TIME_SECONDS;               /*!< (@ 0x5000C708) System Time - Seconds Register                         */\r
+  __I  uint32_t  SYSTEM_TIME_NANOSECONDS;           /*!< (@ 0x5000C70C) System Time Nanoseconds Register                       */\r
+  __IO uint32_t  SYSTEM_TIME_SECONDS_UPDATE;        /*!< (@ 0x5000C710) System Time - Seconds Update Register                  */\r
+  __IO uint32_t  SYSTEM_TIME_NANOSECONDS_UPDATE;    /*!< (@ 0x5000C714) System Time Nanoseconds Update Register                */\r
+  __IO uint32_t  TIMESTAMP_ADDEND;                  /*!< (@ 0x5000C718) Timestamp Addend Register                              */\r
+  __IO uint32_t  TARGET_TIME_SECONDS;               /*!< (@ 0x5000C71C) Target Time Seconds Register                           */\r
+  __IO uint32_t  TARGET_TIME_NANOSECONDS;           /*!< (@ 0x5000C720) Target Time Nanoseconds Register                       */\r
+  __IO uint32_t  SYSTEM_TIME_HIGHER_WORD_SECONDS;   /*!< (@ 0x5000C724) System Time - Higher Word Seconds Register             */\r
+  __I  uint32_t  TIMESTAMP_STATUS;                  /*!< (@ 0x5000C728) Timestamp Status Register                              */\r
+  __IO uint32_t  PPS_CONTROL;                       /*!< (@ 0x5000C72C) PPS Control Register                                   */\r
+  __I  uint32_t  RESERVED8[564];\r
+  __IO uint32_t  BUS_MODE;                          /*!< (@ 0x5000D000) Bus Mode Register                                      */\r
+  __IO uint32_t  TRANSMIT_POLL_DEMAND;              /*!< (@ 0x5000D004) Transmit Poll Demand Register                          */\r
+  __IO uint32_t  RECEIVE_POLL_DEMAND;               /*!< (@ 0x5000D008) Receive Poll Demand Register                           */\r
+  __IO uint32_t  RECEIVE_DESCRIPTOR_LIST_ADDRESS;   /*!< (@ 0x5000D00C) Receive Descriptor Address Register                    */\r
+  __IO uint32_t  TRANSMIT_DESCRIPTOR_LIST_ADDRESS;  /*!< (@ 0x5000D010) Transmit descripter Address Register                   */\r
+  __IO uint32_t  STATUS;                            /*!< (@ 0x5000D014) Status Register                                        */\r
+  __IO uint32_t  OPERATION_MODE;                    /*!< (@ 0x5000D018) Operation Mode Register                                */\r
+  __IO uint32_t  INTERRUPT_ENABLE;                  /*!< (@ 0x5000D01C) Interrupt Enable Register                              */\r
+  __I  uint32_t  MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER;/*!< (@ 0x5000D020) Missed Frame and Buffer Overflow Counter Register */\r
+  __IO uint32_t  RECEIVE_INTERRUPT_WATCHDOG_TIMER;  /*!< (@ 0x5000D024) Receive Interrupt Watchdog Timer Register              */\r
+  __I  uint32_t  RESERVED9;\r
+  __I  uint32_t  AHB_STATUS;                        /*!< (@ 0x5000D02C) AHB Status Register                                    */\r
+  __I  uint32_t  RESERVED10[6];\r
+  __I  uint32_t  CURRENT_HOST_TRANSMIT_DESCRIPTOR;  /*!< (@ 0x5000D048) Current Host Transmit Descriptor Register              */\r
+  __I  uint32_t  CURRENT_HOST_RECEIVE_DESCRIPTOR;   /*!< (@ 0x5000D04C) Current Host Receive Descriptor Register               */\r
+  __I  uint32_t  CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS;/*!< (@ 0x5000D050) Current Host Transmit Buffer Address Register        */\r
+  __I  uint32_t  CURRENT_HOST_RECEIVE_BUFFER_ADDRESS;/*!< (@ 0x5000D054) Current Host Receive Buffer Address Register          */\r
+  __IO uint32_t  HW_FEATURE;                        /*!< (@ 0x5000D058) HW Feature Register                                    */\r
+} ETH_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   USB [USB0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Bus (USB)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50040000) USB Structure                                          */\r
+  __IO uint32_t  GOTGCTL;                           /*!< (@ 0x50040000) Control and Status Register                            */\r
+  __IO uint32_t  GOTGINT;                           /*!< (@ 0x50040004) OTG Interrupt Register                                 */\r
+  __IO uint32_t  GAHBCFG;                           /*!< (@ 0x50040008) AHB Configuration Register                             */\r
+  __IO uint32_t  GUSBCFG;                           /*!< (@ 0x5004000C) USB Configuration Register                             */\r
+  __IO uint32_t  GRSTCTL;                           /*!< (@ 0x50040010) Reset Register                                         */\r
+  \r
+  union {\r
+    __IO uint32_t  GINTSTS_DEVICEMODE;              /*!< (@ 0x50040014) Interrupt Register [DEVICEMODE]                        */\r
+    __IO uint32_t  GINTSTS_HOSTMODE;                /*!< (@ 0x50040014) Interrupt Register [HOSTMODE]                          */\r
+  };\r
+  \r
+  union {\r
+    __IO uint32_t  GINTMSK_DEVICEMODE;              /*!< (@ 0x50040018) Interrupt Mask Register [DEVICEMODE]                   */\r
+    __IO uint32_t  GINTMSK_HOSTMODE;                /*!< (@ 0x50040018) Interrupt Mask Register [HOSTMODE]                     */\r
+  };\r
+  \r
+  union {\r
+    __I  uint32_t  GRXSTSR_DEVICEMODE;              /*!< (@ 0x5004001C) Receive Status Debug Read Register [DEVICEMODE]        */\r
+    __I  uint32_t  GRXSTSR_HOSTMODE;                /*!< (@ 0x5004001C) Receive Status Debug Read Register [HOSTMODE]          */\r
+  };\r
+  \r
+  union {\r
+    __I  uint32_t  GRXSTSP_HOSTMODE;                /*!< (@ 0x50040020) Receive Status Read and Pop Register [HOSTMODE]        */\r
+    __I  uint32_t  GRXSTSP_DEVICEMODE;              /*!< (@ 0x50040020) Receive Status Read and Pop Register [DEVICEMODE]      */\r
+  };\r
+  __IO uint32_t  GRXFSIZ;                           /*!< (@ 0x50040024) Receive FIFO Size Register                             */\r
+  \r
+  union {\r
+    __IO uint32_t  GNPTXFSIZ_DEVICEMODE;            /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register [DEVICEMODE]  */\r
+    __IO uint32_t  GNPTXFSIZ_HOSTMODE;              /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register [HOSTMODE]    */\r
+  };\r
+  __I  uint32_t  GNPTXSTS;                          /*!< (@ 0x5004002C) Non-Periodic Transmit FIFO/Queue Status Register       */\r
+  __I  uint32_t  RESERVED0[3];\r
+  __IO uint32_t  GUID;                              /*!< (@ 0x5004003C) USB Module Identification Register                     */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __IO uint32_t  GDFIFOCFG;                         /*!< (@ 0x5004005C) Global DFIFO Software Config Register                  */\r
+  __I  uint32_t  RESERVED2[40];\r
+  __IO uint32_t  HPTXFSIZ;                          /*!< (@ 0x50040100) Host Periodic Transmit FIFO Size Register              */\r
+  __IO uint32_t  DIEPTXF1;                          /*!< (@ 0x50040104) Device IN Endpoint Transmit FIFO Size Register         */\r
+  __IO uint32_t  DIEPTXF2;                          /*!< (@ 0x50040108) Device IN Endpoint Transmit FIFO Size Register         */\r
+  __IO uint32_t  DIEPTXF3;                          /*!< (@ 0x5004010C) Device IN Endpoint Transmit FIFO Size Register         */\r
+  __IO uint32_t  DIEPTXF4;                          /*!< (@ 0x50040110) Device IN Endpoint Transmit FIFO Size Register         */\r
+  __IO uint32_t  DIEPTXF5;                          /*!< (@ 0x50040114) Device IN Endpoint Transmit FIFO Size Register         */\r
+  __IO uint32_t  DIEPTXF6;                          /*!< (@ 0x50040118) Device IN Endpoint Transmit FIFO Size Register         */\r
+  __I  uint32_t  RESERVED3[185];\r
+  __IO uint32_t  HCFG;                              /*!< (@ 0x50040400) Host Configuration Register                            */\r
+  __IO uint32_t  HFIR;                              /*!< (@ 0x50040404) Host Frame Interval Register                           */\r
+  __IO uint32_t  HFNUM;                             /*!< (@ 0x50040408) Host Frame Number/Frame Time Remaining Register        */\r
+  __I  uint32_t  RESERVED4;\r
+  __IO uint32_t  HPTXSTS;                           /*!< (@ 0x50040410) Host Periodic Transmit FIFO/ Queue Status Register     */\r
+  __I  uint32_t  HAINT;                             /*!< (@ 0x50040414) Host All Channels Interrupt Register                   */\r
+  __IO uint32_t  HAINTMSK;                          /*!< (@ 0x50040418) Host All Channels Interrupt Mask Register              */\r
+  __IO uint32_t  HFLBADDR;                          /*!< (@ 0x5004041C) Host Frame List Base Address Register                  */\r
+  __I  uint32_t  RESERVED5[8];\r
+  __IO uint32_t  HPRT;                              /*!< (@ 0x50040440) Host Port Control and Status Register                  */\r
+  __I  uint32_t  RESERVED6[239];\r
+  __IO uint32_t  DCFG;                              /*!< (@ 0x50040800) Device Configuration Register                          */\r
+  __IO uint32_t  DCTL;                              /*!< (@ 0x50040804) Device Control Register                                */\r
+  __I  uint32_t  DSTS;                              /*!< (@ 0x50040808) Device Status Register                                 */\r
+  __I  uint32_t  RESERVED7;\r
+  __IO uint32_t  DIEPMSK;                           /*!< (@ 0x50040810) Device IN Endpoint Common Interrupt Mask Register      */\r
+  __IO uint32_t  DOEPMSK;                           /*!< (@ 0x50040814) Device OUT Endpoint Common Interrupt Mask Register     */\r
+  __I  uint32_t  DAINT;                             /*!< (@ 0x50040818) Device All Endpoints Interrupt Register                */\r
+  __IO uint32_t  DAINTMSK;                          /*!< (@ 0x5004081C) Device All Endpoints Interrupt Mask Register           */\r
+  __I  uint32_t  RESERVED8[2];\r
+  __IO uint32_t  DVBUSDIS;                          /*!< (@ 0x50040828) Device VBUS Discharge Time Register                    */\r
+  __IO uint32_t  DVBUSPULSE;                        /*!< (@ 0x5004082C) Device VBUS Pulsing Time Register                      */\r
+  __I  uint32_t  RESERVED9;\r
+  __IO uint32_t  DIEPEMPMSK;                        /*!< (@ 0x50040834) Device IN Endpoint FIFO Empty Interrupt Mask\r
+                                                         Register                                                              */\r
+  __I  uint32_t  RESERVED10[370];\r
+  __IO uint32_t  PCGCCTL;                           /*!< (@ 0x50040E00) Power and Clock Gating Control Register                */\r
+} USB0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    USB0_EP0                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Bus (USB0_EP0)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50040900) USB0_EP0 Structure                                     */\r
+  __IO uint32_t  DIEPCTL0;                          /*!< (@ 0x50040900) Device Control IN Endpoint Control Register            */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DIEPINT0;                          /*!< (@ 0x50040908) Device Endpoint Interrupt Register                     */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  DIEPTSIZ0;                         /*!< (@ 0x50040910) Device IN Endpoint Transfer Size Register              */\r
+  __IO uint32_t  DIEPDMA0;                          /*!< (@ 0x50040914) Device Endpoint DMA Address Register                   */\r
+  __I  uint32_t  DTXFSTS0;                          /*!< (@ 0x50040918) Device IN Endpoint Transmit FIFO Status Register       */\r
+  __I  uint32_t  DIEPDMAB0;                         /*!< (@ 0x5004091C) Device Endpoint DMA Buffer Address Register            */\r
+  __I  uint32_t  RESERVED2[120];\r
+  __IO uint32_t  DOEPCTL0;                          /*!< (@ 0x50040B00) Device Control OUT Endpoint Control Register           */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  DOEPINT0;                          /*!< (@ 0x50040B08) Device Endpoint Interrupt Register                     */\r
+  __I  uint32_t  RESERVED4;\r
+  __IO uint32_t  DOEPTSIZ0;                         /*!< (@ 0x50040B10) Device OUT Endpoint Transfer Size Register             */\r
+  __IO uint32_t  DOEPDMA0;                          /*!< (@ 0x50040B14) Device Endpoint DMA Address Register                   */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  DOEPDMAB0;                         /*!< (@ 0x50040B1C) Device Endpoint DMA Buffer Address Register            */\r
+} USB0_EP0_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                USB_EP [USB0_EP1]               ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Bus (USB_EP)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50040920) USB_EP Structure                                       */\r
+  \r
+  union {\r
+    __IO uint32_t  DIEPCTL_INTBULK;                 /*!< (@ 0x50040920) Device Endpoint Control Register [INTBULK]             */\r
+    __IO uint32_t  DIEPCTL_ISOCONT;                 /*!< (@ 0x50040920) Device Endpoint Control Register [ISOCONT]             */\r
+  };\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DIEPINT;                           /*!< (@ 0x50040928) Device Endpoint Interrupt Register                     */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  DIEPTSIZ;                          /*!< (@ 0x50040930) Device Endpoint Transfer Size Register                 */\r
+  __IO uint32_t  DIEPDMA;                           /*!< (@ 0x50040934) Device Endpoint DMA Address Register                   */\r
+  __I  uint32_t  DTXFSTS;                           /*!< (@ 0x50040938) Device IN Endpoint Transmit FIFO Status Register       */\r
+  __I  uint32_t  DIEPDMAB;                          /*!< (@ 0x5004093C) Device Endpoint DMA Buffer Address Register            */\r
+  __I  uint32_t  RESERVED2[120];\r
+  \r
+  union {\r
+    __IO uint32_t  DOEPCTL_INTBULK;                 /*!< (@ 0x50040B20) Device Endpoint Control Register [INTBULK]             */\r
+    __IO uint32_t  DOEPCTL_ISOCONT;                 /*!< (@ 0x50040B20) Device Endpoint Control Register [ISOCONT]             */\r
+  };\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  DOEPINT;                           /*!< (@ 0x50040B28) Device Endpoint Interrupt Register                     */\r
+  __I  uint32_t  RESERVED4;\r
+  \r
+  union {\r
+    __IO uint32_t  DOEPTSIZ_CONTROL;                /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [CONT]          */\r
+    __IO uint32_t  DOEPTSIZ_ISO;                    /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [ISO]           */\r
+  };\r
+  __IO uint32_t  DOEPDMA;                           /*!< (@ 0x50040B34) Device Endpoint DMA Address Register                   */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  DOEPDMAB;                          /*!< (@ 0x50040B3C) Device Endpoint DMA Buffer Address Register            */\r
+} USB0_EP_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                USB_CH [USB0_CH0]               ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Bus (USB_CH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50040500) USB_CH Structure                                       */\r
+  __IO uint32_t  HCCHAR;                            /*!< (@ 0x50040500) Host Channel Characteristics Register                  */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  HCINT;                             /*!< (@ 0x50040508) Host Channel Interrupt Register                        */\r
+  __IO uint32_t  HCINTMSK;                          /*!< (@ 0x5004050C) Host Channel Interrupt Mask Register                   */\r
+  \r
+  union {\r
+    __IO uint32_t  HCTSIZ_SCATGATHER;               /*!< (@ 0x50040510) Host Channel Transfer Size Register [SCATGATHER]       */\r
+    __IO uint32_t  HCTSIZ_BUFFERMODE;               /*!< (@ 0x50040510) Host Channel Transfer Size Register [BUFFERMODE]       */\r
+  };\r
+  \r
+  union {\r
+    __IO uint32_t  HCDMA_SCATGATHER;                /*!< (@ 0x50040514) Host Channel DMA Address Register [SCATGATHER]         */\r
+    __IO uint32_t  HCDMA_BUFFERMODE;                /*!< (@ 0x50040514) Host Channel DMA Address Register [BUFFERMODE]         */\r
+  };\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  HCDMAB;                            /*!< (@ 0x5004051C) Host Channel DMA Buffer Address Register               */\r
+} USB0_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  USIC [USIC0]                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Interface Controller 0 (USIC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40030008) USIC Structure                                         */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x40030008) Module Identification Register                         */\r
+} USIC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================               USIC_CH [USIC0_CH0]              ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Interface Controller 0 (USIC_CH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40030000) USIC_CH Structure                                      */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  CCFG;                              /*!< (@ 0x40030004) Channel Configuration Register                         */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  KSCFG;                             /*!< (@ 0x4003000C) Kernel State Configuration Register                    */\r
+  __IO uint32_t  FDR;                               /*!< (@ 0x40030010) Fractional Divider Register                            */\r
+  __IO uint32_t  BRG;                               /*!< (@ 0x40030014) Baud Rate Generator Register                           */\r
+  __IO uint32_t  INPR;                              /*!< (@ 0x40030018) Interrupt Node Pointer Register                        */\r
+  __IO uint32_t  DX0CR;                             /*!< (@ 0x4003001C) Input Control Register 0                               */\r
+  __IO uint32_t  DX1CR;                             /*!< (@ 0x40030020) Input Control Register 1                               */\r
+  __IO uint32_t  DX2CR;                             /*!< (@ 0x40030024) Input Control Register 2                               */\r
+  __IO uint32_t  DX3CR;                             /*!< (@ 0x40030028) Input Control Register 3                               */\r
+  __IO uint32_t  DX4CR;                             /*!< (@ 0x4003002C) Input Control Register 4                               */\r
+  __IO uint32_t  DX5CR;                             /*!< (@ 0x40030030) Input Control Register 5                               */\r
+  __IO uint32_t  SCTR;                              /*!< (@ 0x40030034) Shift Control Register                                 */\r
+  __IO uint32_t  TCSR;                              /*!< (@ 0x40030038) Transmit Control/Status Register                       */\r
+  \r
+  union {\r
+    __IO uint32_t  PCR_IICMode;                     /*!< (@ 0x4003003C) Protocol Control Register [IIC Mode]                   */\r
+    __IO uint32_t  PCR_IISMode;                     /*!< (@ 0x4003003C) Protocol Control Register [IIS Mode]                   */\r
+    __IO uint32_t  PCR_SSCMode;                     /*!< (@ 0x4003003C) Protocol Control Register [SSC Mode]                   */\r
+    __IO uint32_t  PCR;                             /*!< (@ 0x4003003C) Protocol Control Register                              */\r
+    __IO uint32_t  PCR_ASCMode;                     /*!< (@ 0x4003003C) Protocol Control Register [ASC Mode]                   */\r
+  };\r
+  __IO uint32_t  CCR;                               /*!< (@ 0x40030040) Channel Control Register                               */\r
+  __IO uint32_t  CMTR;                              /*!< (@ 0x40030044) Capture Mode Timer Register                            */\r
+  \r
+  union {\r
+    __IO uint32_t  PSR_IICMode;                     /*!< (@ 0x40030048) Protocol Status Register [IIC Mode]                    */\r
+    __IO uint32_t  PSR_IISMode;                     /*!< (@ 0x40030048) Protocol Status Register [IIS Mode]                    */\r
+    __IO uint32_t  PSR_SSCMode;                     /*!< (@ 0x40030048) Protocol Status Register [SSC Mode]                    */\r
+    __IO uint32_t  PSR;                             /*!< (@ 0x40030048) Protocol Status Register                               */\r
+    __IO uint32_t  PSR_ASCMode;                     /*!< (@ 0x40030048) Protocol Status Register [ASC Mode]                    */\r
+  };\r
+  __O  uint32_t  PSCR;                              /*!< (@ 0x4003004C) Protocol Status Clear Register                         */\r
+  __I  uint32_t  RBUFSR;                            /*!< (@ 0x40030050) Receiver Buffer Status Register                        */\r
+  __I  uint32_t  RBUF;                              /*!< (@ 0x40030054) Receiver Buffer Register                               */\r
+  __I  uint32_t  RBUFD;                             /*!< (@ 0x40030058) Receiver Buffer Register for Debugger                  */\r
+  __I  uint32_t  RBUF0;                             /*!< (@ 0x4003005C) Receiver Buffer Register 0                             */\r
+  __I  uint32_t  RBUF1;                             /*!< (@ 0x40030060) Receiver Buffer Register 1                             */\r
+  __I  uint32_t  RBUF01SR;                          /*!< (@ 0x40030064) Receiver Buffer 01 Status Register                     */\r
+  __O  uint32_t  FMR;                               /*!< (@ 0x40030068) Flag Modification Register                             */\r
+  __I  uint32_t  RESERVED2[5];\r
+  __IO uint32_t  TBUF[32];                          /*!< (@ 0x40030080) Transmit Buffer                                        */\r
+  __IO uint32_t  BYP;                               /*!< (@ 0x40030100) Bypass Data Register                                   */\r
+  __IO uint32_t  BYPCR;                             /*!< (@ 0x40030104) Bypass Control Register                                */\r
+  __IO uint32_t  TBCTR;                             /*!< (@ 0x40030108) Transmitter Buffer Control Register                    */\r
+  __IO uint32_t  RBCTR;                             /*!< (@ 0x4003010C) Receiver Buffer Control Register                       */\r
+  __I  uint32_t  TRBPTR;                            /*!< (@ 0x40030110) Transmit/Receive Buffer Pointer Register               */\r
+  __IO uint32_t  TRBSR;                             /*!< (@ 0x40030114) Transmit/Receive Buffer Status Register                */\r
+  __O  uint32_t  TRBSCR;                            /*!< (@ 0x40030118) Transmit/Receive Buffer Status Clear Register          */\r
+  __I  uint32_t  OUTR;                              /*!< (@ 0x4003011C) Receiver Buffer Output Register                        */\r
+  __I  uint32_t  OUTDR;                             /*!< (@ 0x40030120) Receiver Buffer Output Register L for Debugger         */\r
+  __I  uint32_t  RESERVED3[23];\r
+  __O  uint32_t  IN[32];                            /*!< (@ 0x40030180) Transmit FIFO Buffer                                   */\r
+} USIC_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       CAN                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Controller Area Networks (CAN)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48014000) CAN Structure                                          */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x48014000) CAN Clock Control Register                             */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x48014008) Module Identification Register                         */\r
+  __IO uint32_t  FDR;                               /*!< (@ 0x4801400C) CAN Fractional Divider Register                        */\r
+  __I  uint32_t  RESERVED1[60];\r
+  __I  uint32_t  LIST[8];                           /*!< (@ 0x48014100) List Register                                          */\r
+  __I  uint32_t  RESERVED2[8];\r
+  __IO uint32_t  MSPND[8];                          /*!< (@ 0x48014140) Message Pending Register                               */\r
+  __I  uint32_t  RESERVED3[8];\r
+  __I  uint32_t  MSID[8];                           /*!< (@ 0x48014180) Message Index Register                                 */\r
+  __I  uint32_t  RESERVED4[8];\r
+  __IO uint32_t  MSIMASK;                           /*!< (@ 0x480141C0) Message Index Mask Register                            */\r
+  __IO uint32_t  PANCTR;                            /*!< (@ 0x480141C4) Panel Control Register                                 */\r
+  __IO uint32_t  MCR;                               /*!< (@ 0x480141C8) Module Control Register                                */\r
+  __O  uint32_t  MITR;                              /*!< (@ 0x480141CC) Module Interrupt Trigger Register                      */\r
+} CAN_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              CAN_NODE [CAN_NODE0]              ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Controller Area Networks (CAN_NODE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48014200) CAN_NODE Structure                                     */\r
+  __IO uint32_t  NCR;                               /*!< (@ 0x48014200) Node Control Register                                  */\r
+  __IO uint32_t  NSR;                               /*!< (@ 0x48014204) Node Status Register                                   */\r
+  __IO uint32_t  NIPR;                              /*!< (@ 0x48014208) Node Interrupt Pointer Register                        */\r
+  __IO uint32_t  NPCR;                              /*!< (@ 0x4801420C) Node Port Control Register                             */\r
+  __IO uint32_t  NBTR;                              /*!< (@ 0x48014210) Node Bit Timing Register                               */\r
+  __IO uint32_t  NECNT;                             /*!< (@ 0x48014214) Node Error Counter Register                            */\r
+  __IO uint32_t  NFCR;                              /*!< (@ 0x48014218) Node Frame Counter Register                            */\r
+} CAN_NODE_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                CAN_MO [CAN_MO0]                ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Controller Area Networks (CAN_MO)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48015000) CAN_MO Structure                                       */\r
+  __IO uint32_t  MOFCR;                             /*!< (@ 0x48015000) Message Object Function Control Register               */\r
+  __IO uint32_t  MOFGPR;                            /*!< (@ 0x48015004) Message Object FIFO/Gateway Pointer Register           */\r
+  __IO uint32_t  MOIPR;                             /*!< (@ 0x48015008) Message Object Interrupt Pointer Register              */\r
+  __IO uint32_t  MOAMR;                             /*!< (@ 0x4801500C) Message Object Acceptance Mask Register                */\r
+  __IO uint32_t  MODATAL;                           /*!< (@ 0x48015010) Message Object Data Register Low                       */\r
+  __IO uint32_t  MODATAH;                           /*!< (@ 0x48015014) Message Object Data Register High                      */\r
+  __IO uint32_t  MOAR;                              /*!< (@ 0x48015018) Message Object Arbitration Register                    */\r
+  \r
+  union {\r
+    __I  uint32_t  MOSTAT;                          /*!< (@ 0x4801501C) Message Object Status Register                         */\r
+    __O  uint32_t  MOCTR;                           /*!< (@ 0x4801501C) Message Object Control Register                        */\r
+  };\r
+} CAN_MO_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      VADC                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Analog to Digital Converter (VADC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40004000) VADC Structure                                         */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x40004000) Clock Control Register                                 */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x40004008) Module Identification Register                         */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __IO uint32_t  OCS;                               /*!< (@ 0x40004028) OCDS Control and Status Register                       */\r
+  __I  uint32_t  RESERVED2[21];\r
+  __IO uint32_t  GLOBCFG;                           /*!< (@ 0x40004080) Global Configuration Register                          */\r
+  __I  uint32_t  RESERVED3[7];\r
+  __IO uint32_t  GLOBICLASS[2];                     /*!< (@ 0x400040A0) Input Class Register, Global                           */\r
+  __I  uint32_t  RESERVED4[4];\r
+  __IO uint32_t  GLOBBOUND;                         /*!< (@ 0x400040B8) Global Boundary Select Register                        */\r
+  __I  uint32_t  RESERVED5[9];\r
+  __IO uint32_t  GLOBEFLAG;                         /*!< (@ 0x400040E0) Global Event Flag Register                             */\r
+  __I  uint32_t  RESERVED6[23];\r
+  __IO uint32_t  GLOBEVNP;                          /*!< (@ 0x40004140) Global Event Node Pointer Register                     */\r
+  __I  uint32_t  RESERVED7[7];\r
+  __IO uint32_t  GLOBTF;                            /*!< (@ 0x40004160) Global Test Functions Register                         */\r
+  __I  uint32_t  RESERVED8[7];\r
+  __IO uint32_t  BRSSEL[4];                         /*!< (@ 0x40004180) Background Request Source Channel Select Register      */\r
+  __I  uint32_t  RESERVED9[12];\r
+  __IO uint32_t  BRSPND[4];                         /*!< (@ 0x400041C0) Background Request Source Pending Register             */\r
+  __I  uint32_t  RESERVED10[12];\r
+  __IO uint32_t  BRSCTRL;                           /*!< (@ 0x40004200) Background Request Source Control Register             */\r
+  __IO uint32_t  BRSMR;                             /*!< (@ 0x40004204) Background Request Source Mode Register                */\r
+  __I  uint32_t  RESERVED11[30];\r
+  __IO uint32_t  GLOBRCR;                           /*!< (@ 0x40004280) Global Result Control Register                         */\r
+  __I  uint32_t  RESERVED12[31];\r
+  __IO uint32_t  GLOBRES;                           /*!< (@ 0x40004300) Global Result Register                                 */\r
+  __I  uint32_t  RESERVED13[31];\r
+  __IO uint32_t  GLOBRESD;                          /*!< (@ 0x40004380) Global Result Register, Debug                          */\r
+  __I  uint32_t  RESERVED14[27];\r
+  __IO uint32_t  EMUXSEL;                           /*!< (@ 0x400043F0) External Multiplexer Select Register                   */\r
+} VADC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                VADC_G [VADC_G0]                ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Analog to Digital Converter (VADC_G)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40004400) VADC_G Structure                                       */\r
+  __I  uint32_t  RESERVED0[32];\r
+  __IO uint32_t  ARBCFG;                            /*!< (@ 0x40004480) Arbitration Configuration Register                     */\r
+  __IO uint32_t  ARBPR;                             /*!< (@ 0x40004484) Arbitration Priority Register                          */\r
+  __IO uint32_t  CHASS;                             /*!< (@ 0x40004488) Channel Assignment Register                            */\r
+  __I  uint32_t  RESERVED1[5];\r
+  __IO uint32_t  ICLASS[2];                         /*!< (@ 0x400044A0) Input Class Register                                   */\r
+  __I  uint32_t  RESERVED2[2];\r
+  __IO uint32_t  ALIAS;                             /*!< (@ 0x400044B0) Alias Register                                         */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  BOUND;                             /*!< (@ 0x400044B8) Boundary Select Register                               */\r
+  __I  uint32_t  RESERVED4;\r
+  __IO uint32_t  SYNCTR;                            /*!< (@ 0x400044C0) Synchronization Control Register                       */\r
+  __I  uint32_t  RESERVED5;\r
+  __IO uint32_t  BFL;                               /*!< (@ 0x400044C8) Boundary Flag Register                                 */\r
+  __I  uint32_t  RESERVED6[13];\r
+  __IO uint32_t  QCTRL0;                            /*!< (@ 0x40004500) Queue 0 Source Control Register                        */\r
+  __IO uint32_t  QMR0;                              /*!< (@ 0x40004504) Queue 0 Mode Register                                  */\r
+  __I  uint32_t  QSR0;                              /*!< (@ 0x40004508) Queue 0 Status Register                                */\r
+  __I  uint32_t  Q0R0;                              /*!< (@ 0x4000450C) Queue 0 Register 0                                     */\r
+  \r
+  union {\r
+    __I  uint32_t  QBUR0;                           /*!< (@ 0x40004510) Queue 0 Backup Register                                */\r
+    __O  uint32_t  QINR0;                           /*!< (@ 0x40004510) Queue 0 Input Register                                 */\r
+  };\r
+  __I  uint32_t  RESERVED7[3];\r
+  __IO uint32_t  ASCTRL;                            /*!< (@ 0x40004520) Autoscan Source Control Register                       */\r
+  __IO uint32_t  ASMR;                              /*!< (@ 0x40004524) Autoscan Source Mode Register                          */\r
+  __IO uint32_t  ASSEL;                             /*!< (@ 0x40004528) Autoscan Source Channel Select Register                */\r
+  __IO uint32_t  ASPND;                             /*!< (@ 0x4000452C) Autoscan Source Pending Register                       */\r
+  __I  uint32_t  RESERVED8[20];\r
+  __IO uint32_t  CEFLAG;                            /*!< (@ 0x40004580) Channel Event Flag Register                            */\r
+  __IO uint32_t  REFLAG;                            /*!< (@ 0x40004584) Result Event Flag Register                             */\r
+  __IO uint32_t  SEFLAG;                            /*!< (@ 0x40004588) Source Event Flag Register                             */\r
+  __I  uint32_t  RESERVED9;\r
+  __O  uint32_t  CEFCLR;                            /*!< (@ 0x40004590) Channel Event Flag Clear Register                      */\r
+  __O  uint32_t  REFCLR;                            /*!< (@ 0x40004594) Result Event Flag Clear Register                       */\r
+  __O  uint32_t  SEFCLR;                            /*!< (@ 0x40004598) Source Event Flag Clear Register                       */\r
+  __I  uint32_t  RESERVED10;\r
+  __IO uint32_t  CEVNP0;                            /*!< (@ 0x400045A0) Channel Event Node Pointer Register 0                  */\r
+  __I  uint32_t  RESERVED11[3];\r
+  __IO uint32_t  REVNP0;                            /*!< (@ 0x400045B0) Result Event Node Pointer Register 0                   */\r
+  __IO uint32_t  REVNP1;                            /*!< (@ 0x400045B4) Result Event Node Pointer Register 1                   */\r
+  __I  uint32_t  RESERVED12[2];\r
+  __IO uint32_t  SEVNP;                             /*!< (@ 0x400045C0) Source Event Node Pointer Register                     */\r
+  __I  uint32_t  RESERVED13;\r
+  __O  uint32_t  SRACT;                             /*!< (@ 0x400045C8) Service Request Software Activation Trigger            */\r
+  __I  uint32_t  RESERVED14[9];\r
+  __IO uint32_t  EMUXCTR;                           /*!< (@ 0x400045F0) E0ternal Multiplexer Control Register                  */\r
+  __I  uint32_t  RESERVED15;\r
+  __IO uint32_t  VFR;                               /*!< (@ 0x400045F8) Valid Flag Register                                    */\r
+  __I  uint32_t  RESERVED16;\r
+  __IO uint32_t  CHCTR[8];                          /*!< (@ 0x40004600) Channel Ctrl. Reg.                                     */\r
+  __I  uint32_t  RESERVED17[24];\r
+  __IO uint32_t  RCR[16];                           /*!< (@ 0x40004680) Result Control Register                                */\r
+  __I  uint32_t  RESERVED18[16];\r
+  __IO uint32_t  RES[16];                           /*!< (@ 0x40004700) Result Register                                        */\r
+  __I  uint32_t  RESERVED19[16];\r
+  __I  uint32_t  RESD[16];                          /*!< (@ 0x40004780) Result Register, Debug                                 */\r
+} VADC_G_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       DSD                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Delta Sigma Demodulator (DSD)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40008000) DSD Structure                                          */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x40008000) Clock Control Register                                 */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x40008008) Module Identification Register                         */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __IO uint32_t  OCS;                               /*!< (@ 0x40008028) OCDS Control and Status Register                       */\r
+  __I  uint32_t  RESERVED2[21];\r
+  __IO uint32_t  GLOBCFG;                           /*!< (@ 0x40008080) Global Configuration Register                          */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  GLOBRC;                            /*!< (@ 0x40008088) Global Run Control Register                            */\r
+  __I  uint32_t  RESERVED4[5];\r
+  __IO uint32_t  CGCFG;                             /*!< (@ 0x400080A0) Carrier Generator Configuration Register               */\r
+  __I  uint32_t  RESERVED5[15];\r
+  __IO uint32_t  EVFLAG;                            /*!< (@ 0x400080E0) Event Flag Register                                    */\r
+  __O  uint32_t  EVFLAGCLR;                         /*!< (@ 0x400080E4) Event Flag Clear Register                              */\r
+} DSD_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                DSD_CH [DSD_CH0]                ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Delta Sigma Demodulator (DSD_CH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40008100) DSD_CH Structure                                       */\r
+  __IO uint32_t  MODCFG;                            /*!< (@ 0x40008100) Modulator Configuration Register                       */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DICFG;                             /*!< (@ 0x40008108) Demodulator Input Configuration Register               */\r
+  __I  uint32_t  RESERVED1[2];\r
+  __IO uint32_t  FCFGC;                             /*!< (@ 0x40008114) Filter Configuration Register, Main CIC Filter         */\r
+  __IO uint32_t  FCFGA;                             /*!< (@ 0x40008118) Filter Configuration Register, Auxiliary Filter        */\r
+  __I  uint32_t  RESERVED2;\r
+  __IO uint32_t  IWCTR;                             /*!< (@ 0x40008120) Integration Window Control Register                    */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  BOUNDSEL;                          /*!< (@ 0x40008128) Boundary Select Register                               */\r
+  __I  uint32_t  RESERVED4;\r
+  __I  uint32_t  RESM;                              /*!< (@ 0x40008130) Result Register, Main Filter                           */\r
+  __I  uint32_t  RESERVED5;\r
+  __IO uint32_t  OFFM;                              /*!< (@ 0x40008138) Offset Register, Main Filter                           */\r
+  __I  uint32_t  RESERVED6;\r
+  __I  uint32_t  RESA;                              /*!< (@ 0x40008140) Result Register, Auxiliary Filter                      */\r
+  __I  uint32_t  RESERVED7[3];\r
+  __I  uint32_t  TSTMP;                             /*!< (@ 0x40008150) Time-Stamp Register                                    */\r
+  __I  uint32_t  RESERVED8[19];\r
+  __IO uint32_t  CGSYNC;                            /*!< (@ 0x400081A0) Carrier Generator Synchronization Register             */\r
+  __I  uint32_t  RESERVED9;\r
+  __IO uint32_t  RECTCFG;                           /*!< (@ 0x400081A8) Rectification Configuration Register                   */\r
+} DSD_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       DAC                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Digital to Analog Converter (DAC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48018000) DAC Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x48018000) Module Identification Register                         */\r
+  __IO uint32_t  DAC0CFG0;                          /*!< (@ 0x48018004) DAC0 Configuration Register 0                          */\r
+  __IO uint32_t  DAC0CFG1;                          /*!< (@ 0x48018008) DAC0 Configuration Register 1                          */\r
+  __IO uint32_t  DAC1CFG0;                          /*!< (@ 0x4801800C) DAC1 Configuration Register 0                          */\r
+  __IO uint32_t  DAC1CFG1;                          /*!< (@ 0x48018010) DAC1 Configuration Register 1                          */\r
+  __IO uint32_t  DAC0DATA;                          /*!< (@ 0x48018014) DAC0 Data Register                                     */\r
+  __IO uint32_t  DAC1DATA;                          /*!< (@ 0x48018018) DAC1 Data Register                                     */\r
+  __IO uint32_t  DAC01DATA;                         /*!< (@ 0x4801801C) DAC01 Data Register                                    */\r
+  __IO uint32_t  DAC0PATL;                          /*!< (@ 0x48018020) DAC0 Lower Pattern Register                            */\r
+  __IO uint32_t  DAC0PATH;                          /*!< (@ 0x48018024) DAC0 Higher Pattern Register                           */\r
+  __IO uint32_t  DAC1PATL;                          /*!< (@ 0x48018028) DAC1 Lower Pattern Register                            */\r
+  __IO uint32_t  DAC1PATH;                          /*!< (@ 0x4801802C) DAC1 Higher Pattern Register                           */\r
+} DAC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  CCU4 [CCU40]                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 4 - Unit 0 (CCU4)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x4000C000) CCU4 Structure                                         */\r
+  __IO uint32_t  GCTRL;                             /*!< (@ 0x4000C000) Global Control Register                                */\r
+  __I  uint32_t  GSTAT;                             /*!< (@ 0x4000C004) Global Status Register                                 */\r
+  __O  uint32_t  GIDLS;                             /*!< (@ 0x4000C008) Global Idle Set                                        */\r
+  __O  uint32_t  GIDLC;                             /*!< (@ 0x4000C00C) Global Idle Clear                                      */\r
+  __O  uint32_t  GCSS;                              /*!< (@ 0x4000C010) Global Channel Set                                     */\r
+  __O  uint32_t  GCSC;                              /*!< (@ 0x4000C014) Global Channel Clear                                   */\r
+  __I  uint32_t  GCST;                              /*!< (@ 0x4000C018) Global Channel Status                                  */\r
+  __I  uint32_t  RESERVED0[13];\r
+  __I  uint32_t  ECRD;                              /*!< (@ 0x4000C050) Extended Capture Mode Read                             */\r
+  __I  uint32_t  RESERVED1[11];\r
+  __I  uint32_t  MIDR;                              /*!< (@ 0x4000C080) Module Identification                                  */\r
+} CCU4_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              CCU4_CC4 [CCU40_CC40]             ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x4000C100) CCU4_CC4 Structure                                     */\r
+  __IO uint32_t  INS;                               /*!< (@ 0x4000C100) Input Selector Configuration                           */\r
+  __IO uint32_t  CMC;                               /*!< (@ 0x4000C104) Connection Matrix Control                              */\r
+  __I  uint32_t  TCST;                              /*!< (@ 0x4000C108) Slice Timer Status                                     */\r
+  __O  uint32_t  TCSET;                             /*!< (@ 0x4000C10C) Slice Timer Run Set                                    */\r
+  __O  uint32_t  TCCLR;                             /*!< (@ 0x4000C110) Slice Timer Clear                                      */\r
+  __IO uint32_t  TC;                                /*!< (@ 0x4000C114) Slice Timer Control                                    */\r
+  __IO uint32_t  PSL;                               /*!< (@ 0x4000C118) Passive Level Config                                   */\r
+  __I  uint32_t  DIT;                               /*!< (@ 0x4000C11C) Dither Config                                          */\r
+  __IO uint32_t  DITS;                              /*!< (@ 0x4000C120) Dither Shadow Register                                 */\r
+  __IO uint32_t  PSC;                               /*!< (@ 0x4000C124) Prescaler Control                                      */\r
+  __IO uint32_t  FPC;                               /*!< (@ 0x4000C128) Floating Prescaler Control                             */\r
+  __IO uint32_t  FPCS;                              /*!< (@ 0x4000C12C) Floating Prescaler Shadow                              */\r
+  __I  uint32_t  PR;                                /*!< (@ 0x4000C130) Timer Period Value                                     */\r
+  __IO uint32_t  PRS;                               /*!< (@ 0x4000C134) Timer Shadow Period Value                              */\r
+  __I  uint32_t  CR;                                /*!< (@ 0x4000C138) Timer Compare Value                                    */\r
+  __IO uint32_t  CRS;                               /*!< (@ 0x4000C13C) Timer Shadow Compare Value                             */\r
+  __I  uint32_t  RESERVED0[12];\r
+  __IO uint32_t  TIMER;                             /*!< (@ 0x4000C170) Timer Value                                            */\r
+  __I  uint32_t  CV[4];                             /*!< (@ 0x4000C174) Capture Register 0                                     */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __I  uint32_t  INTS;                              /*!< (@ 0x4000C1A0) Interrupt Status                                       */\r
+  __IO uint32_t  INTE;                              /*!< (@ 0x4000C1A4) Interrupt Enable Control                               */\r
+  __IO uint32_t  SRS;                               /*!< (@ 0x4000C1A8) Service Request Selector                               */\r
+  __O  uint32_t  SWS;                               /*!< (@ 0x4000C1AC) Interrupt Status Set                                   */\r
+  __O  uint32_t  SWR;                               /*!< (@ 0x4000C1B0) Interrupt Status Clear                                 */\r
+} CCU4_CC4_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  CCU8 [CCU80]                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 8 - Unit 0 (CCU8)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40020000) CCU8 Structure                                         */\r
+  __IO uint32_t  GCTRL;                             /*!< (@ 0x40020000) Global Control Register                                */\r
+  __I  uint32_t  GSTAT;                             /*!< (@ 0x40020004) Global Status Register                                 */\r
+  __O  uint32_t  GIDLS;                             /*!< (@ 0x40020008) Global Idle Set                                        */\r
+  __O  uint32_t  GIDLC;                             /*!< (@ 0x4002000C) Global Idle Clear                                      */\r
+  __O  uint32_t  GCSS;                              /*!< (@ 0x40020010) Global Channel Set                                     */\r
+  __O  uint32_t  GCSC;                              /*!< (@ 0x40020014) Global Channel Clear                                   */\r
+  __I  uint32_t  GCST;                              /*!< (@ 0x40020018) Global Channel status                                  */\r
+  __IO uint32_t  GPCHK;                             /*!< (@ 0x4002001C) Parity Checker Configuration                           */\r
+  __I  uint32_t  RESERVED0[12];\r
+  __I  uint32_t  ECRD;                              /*!< (@ 0x40020050) Extended Capture Mode Read                             */\r
+  __I  uint32_t  RESERVED1[11];\r
+  __I  uint32_t  MIDR;                              /*!< (@ 0x40020080) Module Identification                                  */\r
+} CCU8_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              CCU8_CC8 [CCU80_CC80]             ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 8 - Unit 0 (CCU8_CC8)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40020100) CCU8_CC8 Structure                                     */\r
+  __IO uint32_t  INS;                               /*!< (@ 0x40020100) Input Selector Configuration                           */\r
+  __IO uint32_t  CMC;                               /*!< (@ 0x40020104) Connection Matrix Control                              */\r
+  __I  uint32_t  TCST;                              /*!< (@ 0x40020108) Slice Timer Status                                     */\r
+  __O  uint32_t  TCSET;                             /*!< (@ 0x4002010C) Slice Timer Run Set                                    */\r
+  __O  uint32_t  TCCLR;                             /*!< (@ 0x40020110) Slice Timer Clear                                      */\r
+  __IO uint32_t  TC;                                /*!< (@ 0x40020114) Slice Timer Control                                    */\r
+  __IO uint32_t  PSL;                               /*!< (@ 0x40020118) Passive Level Config                                   */\r
+  __I  uint32_t  DIT;                               /*!< (@ 0x4002011C) Dither Config                                          */\r
+  __IO uint32_t  DITS;                              /*!< (@ 0x40020120) Dither Shadow Register                                 */\r
+  __IO uint32_t  PSC;                               /*!< (@ 0x40020124) Prescaler Control                                      */\r
+  __IO uint32_t  FPC;                               /*!< (@ 0x40020128) Floating Prescaler Control                             */\r
+  __IO uint32_t  FPCS;                              /*!< (@ 0x4002012C) Floating Prescaler Shadow                              */\r
+  __I  uint32_t  PR;                                /*!< (@ 0x40020130) Timer Period Value                                     */\r
+  __IO uint32_t  PRS;                               /*!< (@ 0x40020134) Timer Shadow Period Value                              */\r
+  __I  uint32_t  CR1;                               /*!< (@ 0x40020138) Channel 1 Compare Value                                */\r
+  __IO uint32_t  CR1S;                              /*!< (@ 0x4002013C) Channel 1 Compare Shadow Value                         */\r
+  __I  uint32_t  CR2;                               /*!< (@ 0x40020140) Channel 2 Compare Value                                */\r
+  __IO uint32_t  CR2S;                              /*!< (@ 0x40020144) Channel 2 Compare Shadow Value                         */\r
+  __IO uint32_t  CHC;                               /*!< (@ 0x40020148) Channel Control                                        */\r
+  __IO uint32_t  DTC;                               /*!< (@ 0x4002014C) Dead Time Control                                      */\r
+  __IO uint32_t  DC1R;                              /*!< (@ 0x40020150) Channel 1 Dead Time Values                             */\r
+  __IO uint32_t  DC2R;                              /*!< (@ 0x40020154) Channel 2 Dead Time Values                             */\r
+  __I  uint32_t  RESERVED0[6];\r
+  __IO uint32_t  TIMER;                             /*!< (@ 0x40020170) Timer Value                                            */\r
+  __I  uint32_t  CV[4];                             /*!< (@ 0x40020174) Capture Register 0                                     */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __I  uint32_t  INTS;                              /*!< (@ 0x400201A0) Interrupt Status                                       */\r
+  __IO uint32_t  INTE;                              /*!< (@ 0x400201A4) Interrupt Enable Control                               */\r
+  __IO uint32_t  SRS;                               /*!< (@ 0x400201A8) Service Request Selector                               */\r
+  __O  uint32_t  SWS;                               /*!< (@ 0x400201AC) Interrupt Status Set                                   */\r
+  __O  uint32_t  SWR;                               /*!< (@ 0x400201B0) Interrupt Status Clear                                 */\r
+} CCU8_CC8_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     HRPWM0                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief High Resolution PWM Unit (HRPWM0)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40020900) HRPWM0 Structure                                       */\r
+  __IO uint32_t  HRBSC;                             /*!< (@ 0x40020900) Bias and suspend configuration                         */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  MIDR;                              /*!< (@ 0x40020908) Module identification register                         */\r
+  __I  uint32_t  RESERVED1[2];\r
+  __IO uint32_t  GLBANA;                            /*!< (@ 0x40020914) Global Analog Configuration                            */\r
+  __I  uint32_t  RESERVED2[2];\r
+  __IO uint32_t  CSGCFG;                            /*!< (@ 0x40020920) Global CSG configuration                               */\r
+  __O  uint32_t  CSGSETG;                           /*!< (@ 0x40020924) Global CSG run bit set                                 */\r
+  __O  uint32_t  CSGCLRG;                           /*!< (@ 0x40020928) Global CSG run bit clear                               */\r
+  __I  uint32_t  CSGSTATG;                          /*!< (@ 0x4002092C) Global CSG run bit status                              */\r
+  __O  uint32_t  CSGFCG;                            /*!< (@ 0x40020930) Global CSG slope/prescaler control                     */\r
+  __I  uint32_t  CSGFSG;                            /*!< (@ 0x40020934) Global CSG slope/prescaler status                      */\r
+  __O  uint32_t  CSGTRG;                            /*!< (@ 0x40020938) Global CSG shadow/switch trigger                       */\r
+  __O  uint32_t  CSGTRC;                            /*!< (@ 0x4002093C) Global CSG shadow trigger clear                        */\r
+  __I  uint32_t  CSGTRSG;                           /*!< (@ 0x40020940) Global CSG shadow/switch status                        */\r
+  __I  uint32_t  RESERVED3[7];\r
+  __IO uint32_t  HRCCFG;                            /*!< (@ 0x40020960) Global HRC configuration                               */\r
+  __O  uint32_t  HRCSTRG;                           /*!< (@ 0x40020964) Global HRC shadow trigger set                          */\r
+  __O  uint32_t  HRCCTRG;                           /*!< (@ 0x40020968) Global HRC shadow trigger clear                        */\r
+  __I  uint32_t  HRCSTSG;                           /*!< (@ 0x4002096C) Global HRC shadow transfer status                      */\r
+  __I  uint32_t  HRGHRS;                            /*!< (@ 0x40020970) High Resolution Generation Status                      */\r
+} HRPWM0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================            HRPWM0_CSG [HRPWM0_CSG0]            ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief High Resolution PWM Unit (HRPWM0_CSG)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40020A00) HRPWM0_CSG Structure                                   */\r
+  __IO uint32_t  DCI;                               /*!< (@ 0x40020A00) External input selection                               */\r
+  __IO uint32_t  IES;                               /*!< (@ 0x40020A04) External input selection                               */\r
+  __IO uint32_t  SC;                                /*!< (@ 0x40020A08) Slope generation control                               */\r
+  __I  uint32_t  PC;                                /*!< (@ 0x40020A0C) Pulse swallow configuration                            */\r
+  __I  uint32_t  DSV1;                              /*!< (@ 0x40020A10) DAC reference value 1                                  */\r
+  __IO uint32_t  DSV2;                              /*!< (@ 0x40020A14) DAC reference value 1                                  */\r
+  __IO uint32_t  SDSV1;                             /*!< (@ 0x40020A18) Shadow reference value 1                               */\r
+  __IO uint32_t  SPC;                               /*!< (@ 0x40020A1C) Shadow Pulse swallow value                             */\r
+  __IO uint32_t  CC;                                /*!< (@ 0x40020A20) Comparator configuration                               */\r
+  __IO uint32_t  PLC;                               /*!< (@ 0x40020A24) Passive level configuration                            */\r
+  __IO uint32_t  BLV;                               /*!< (@ 0x40020A28) Comparator blanking value                              */\r
+  __IO uint32_t  SRE;                               /*!< (@ 0x40020A2C) Service request enable                                 */\r
+  __IO uint32_t  SRS;                               /*!< (@ 0x40020A30) Service request line selector                          */\r
+  __O  uint32_t  SWS;                               /*!< (@ 0x40020A34) Service request SW set                                 */\r
+  __O  uint32_t  SWC;                               /*!< (@ 0x40020A38) Service request SW clear                               */\r
+  __I  uint32_t  ISTAT;                             /*!< (@ 0x40020A3C) Service request status                                 */\r
+} HRPWM0_CSG_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================            HRPWM0_HRC [HRPWM0_HRC0]            ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief High Resolution PWM Unit (HRPWM0_HRC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40021300) HRPWM0_HRC Structure                                   */\r
+  __IO uint32_t  GC;                                /*!< (@ 0x40021300) HRC mode configuration                                 */\r
+  __IO uint32_t  PL;                                /*!< (@ 0x40021304) HRC output passive level                               */\r
+  __IO uint32_t  GSEL;                              /*!< (@ 0x40021308) HRC global control selection                           */\r
+  __IO uint32_t  TSEL;                              /*!< (@ 0x4002130C) HRC timer selection                                    */\r
+  __I  uint32_t  SC;                                /*!< (@ 0x40021310) HRC current source for shadow                          */\r
+  __I  uint32_t  DCR;                               /*!< (@ 0x40021314) HRC dead time rising value                             */\r
+  __I  uint32_t  DCF;                               /*!< (@ 0x40021318) HRC dead time falling value                            */\r
+  __I  uint32_t  CR1;                               /*!< (@ 0x4002131C) HRC rising edge value                                  */\r
+  __I  uint32_t  CR2;                               /*!< (@ 0x40021320) HRC falling edge value                                 */\r
+  __IO uint32_t  SSC;                               /*!< (@ 0x40021324) HRC next source for shadow                             */\r
+  __IO uint32_t  SDCR;                              /*!< (@ 0x40021328) HRC shadow dead time rising                            */\r
+  __IO uint32_t  SDCF;                              /*!< (@ 0x4002132C) HRC shadow dead time falling                           */\r
+  __IO uint32_t  SCR1;                              /*!< (@ 0x40021330) HRC shadow rising edge value                           */\r
+  __IO uint32_t  SCR2;                              /*!< (@ 0x40021334) HRC shadow falling edge value                          */\r
+} HRPWM0_HRC_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                 POSIF [POSIF0]                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Position Interface 0 (POSIF)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40028000) POSIF Structure                                        */\r
+  __IO uint32_t  PCONF;                             /*!< (@ 0x40028000) Service Request Processing configuration               */\r
+  __IO uint32_t  PSUS;                              /*!< (@ 0x40028004) Service Request Processing Suspend Config              */\r
+  __O  uint32_t  PRUNS;                             /*!< (@ 0x40028008) Service Request Processing Run Bit Set                 */\r
+  __O  uint32_t  PRUNC;                             /*!< (@ 0x4002800C) Service Request Processing Run Bit Clear               */\r
+  __I  uint32_t  PRUN;                              /*!< (@ 0x40028010) Service Request Processing Run Bit Status              */\r
+  __I  uint32_t  RESERVED0[3];\r
+  __I  uint32_t  MIDR;                              /*!< (@ 0x40028020) Module Identification register                         */\r
+  __I  uint32_t  RESERVED1[3];\r
+  __I  uint32_t  HALP;                              /*!< (@ 0x40028030) Hall Sensor Patterns                                   */\r
+  __IO uint32_t  HALPS;                             /*!< (@ 0x40028034) Hall Sensor Shadow Patterns                            */\r
+  __I  uint32_t  RESERVED2[2];\r
+  __I  uint32_t  MCM;                               /*!< (@ 0x40028040) Multi-Channel Pattern                                  */\r
+  __IO uint32_t  MCSM;                              /*!< (@ 0x40028044) Multi-Channel Shadow Pattern                           */\r
+  __O  uint32_t  MCMS;                              /*!< (@ 0x40028048) Multi-Channel Pattern Control set                      */\r
+  __O  uint32_t  MCMC;                              /*!< (@ 0x4002804C) Multi-Channel Pattern Control clear                    */\r
+  __I  uint32_t  MCMF;                              /*!< (@ 0x40028050) Multi-Channel Pattern Control flag                     */\r
+  __I  uint32_t  RESERVED3[3];\r
+  __IO uint32_t  QDC;                               /*!< (@ 0x40028060) Quadrature Decoder Control                             */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __I  uint32_t  PFLG;                              /*!< (@ 0x40028070) Service Request Processing Interrupt Flags             */\r
+  __IO uint32_t  PFLGE;                             /*!< (@ 0x40028074) Service Request Processing Interrupt Enable            */\r
+  __O  uint32_t  SPFLG;                             /*!< (@ 0x40028078) Service Request Processing Interrupt Set               */\r
+  __O  uint32_t  RPFLG;                             /*!< (@ 0x4002807C) Service Request Processing Interrupt Clear             */\r
+  __I  uint32_t  RESERVED5[32];\r
+  __I  uint32_t  PDBG;                              /*!< (@ 0x40028100) POSIF Debug register                                   */\r
+} POSIF_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT0                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 0 (PORT0)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028000) PORT0 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028000) Port 0 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028004) Port 0 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028010) Port 0 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028014) Port 0 Input/Output Control Register 4                 */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028018) Port 0 Input/Output Control Register 8                 */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x4802801C) Port 0 Input/Output Control Register 12                */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028024) Port 0 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028040) Port 0 Pad Driver Mode 0 Register                      */\r
+  __IO uint32_t  PDR1;                              /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Register                      */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028060) Port 0 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028070) Port 0 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028074) Port 0 Pin Hardware Select Register                    */\r
+} PORT0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT1                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 1 (PORT1)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028100) PORT1 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028100) Port 1 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028104) Port 1 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028110) Port 1 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028114) Port 1 Input/Output Control Register 4                 */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028118) Port 1 Input/Output Control Register 8                 */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x4802811C) Port 1 Input/Output Control Register 12                */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028124) Port 1 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028140) Port 1 Pad Driver Mode 0 Register                      */\r
+  __IO uint32_t  PDR1;                              /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Register                      */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028160) Port 1 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028170) Port 1 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028174) Port 1 Pin Hardware Select Register                    */\r
+} PORT1_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT2                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 2 (PORT2)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028200) PORT2 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028200) Port 2 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028204) Port 2 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028210) Port 2 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028214) Port 2 Input/Output Control Register 4                 */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028218) Port 2 Input/Output Control Register 8                 */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x4802821C) Port 2 Input/Output Control Register 12                */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028224) Port 2 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028240) Port 2 Pad Driver Mode 0 Register                      */\r
+  __IO uint32_t  PDR1;                              /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Register                      */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028260) Port 2 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028270) Port 2 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028274) Port 2 Pin Hardware Select Register                    */\r
+} PORT2_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT3                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 3 (PORT3)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028300) PORT3 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028300) Port 3 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028304) Port 3 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028310) Port 3 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028314) Port 3 Input/Output Control Register 4                 */\r
+  __I  uint32_t  RESERVED1[3];\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028324) Port 3 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028340) Port 3 Pad Driver Mode 0 Register                      */\r
+  __I  uint32_t  RESERVED3[7];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028360) Port 3 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028370) Port 3 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028374) Port 3 Pin Hardware Select Register                    */\r
+} PORT3_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT4                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 4 (PORT4)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028400) PORT4 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028400) Port 4 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028404) Port 4 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028410) Port 4 Input/Output Control Register 0                 */\r
+  __I  uint32_t  RESERVED1[4];\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028424) Port 4 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028440) Port 4 Pad Driver Mode 0 Register                      */\r
+  __I  uint32_t  RESERVED3[7];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028460) Port 4 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028470) Port 4 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028474) Port 4 Pin Hardware Select Register                    */\r
+} PORT4_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT5                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 5 (PORT5)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028500) PORT5 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028500) Port 5 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028504) Port 5 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028510) Port 5 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028514) Port 5 Input/Output Control Register 4                 */\r
+  __I  uint32_t  RESERVED1[3];\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028524) Port 5 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028540) Port 5 Pad Driver Mode 0 Register                      */\r
+  __I  uint32_t  RESERVED3[7];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028560) Port 5 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028570) Port 5 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028574) Port 5 Pin Hardware Select Register                    */\r
+} PORT5_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     PORT14                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 14 (PORT14)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028E00) PORT14 Structure                                       */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028E00) Port 14 Output Register                                */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028E04) Port 14 Output Modification Register                   */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028E10) Port 14 Input/Output Control Register 0                */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028E14) Port 14 Input/Output Control Register 4                */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028E18) Port 14 Input/Output Control Register 8                */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x48028E1C) Port 14 Input/Output Control Register 12               */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028E24) Port 14 Input Register                                 */\r
+  __I  uint32_t  RESERVED2[14];\r
+  __IO uint32_t  PDISC;                             /*!< (@ 0x48028E60) Port 14 Pin Function Decision Control Register         */\r
+  __I  uint32_t  RESERVED3[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028E70) Port 14 Pin Power Save Register                        */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028E74) Port 14 Pin Hardware Select Register                   */\r
+} PORT14_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     PORT15                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 15 (PORT15)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028F00) PORT15 Structure                                       */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028F00) Port 15 Output Register                                */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028F04) Port 15 Output Modification Register                   */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028F10) Port 15 Input/Output Control Register 0                */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028F14) Port 15 Input/Output Control Register 4                */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028F18) Port 15 Input/Output Control Register 8                */\r
+  __I  uint32_t  RESERVED1[2];\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028F24) Port 15 Input Register                                 */\r
+  __I  uint32_t  RESERVED2[14];\r
+  __IO uint32_t  PDISC;                             /*!< (@ 0x48028F60) Port 15 Pin Function Decision Control Register         */\r
+  __I  uint32_t  RESERVED3[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028F70) Port 15 Pin Power Save Register                        */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028F74) Port 15 Pin Hardware Select Register                   */\r
+} PORT15_Type;\r
+\r
+\r
+/* --------------------  End of section using anonymous unions  ------------------- */\r
+#if defined(__CC_ARM)\r
+  #pragma pop\r
+#elif defined(__ICCARM__)\r
+  /* leave anonymous unions enabled */\r
+#elif defined(__GNUC__)\r
+  /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+  /* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+  #pragma warning restore\r
+#else\r
+  #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'PPB' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PPB_ACTLR  --------------------------------- */\r
+#define PPB_ACTLR_DISMCYCINT_Pos              0                                                       /*!< PPB ACTLR: DISMCYCINT Position          */\r
+#define PPB_ACTLR_DISMCYCINT_Msk              (0x01UL << PPB_ACTLR_DISMCYCINT_Pos)                    /*!< PPB ACTLR: DISMCYCINT Mask              */\r
+#define PPB_ACTLR_DISDEFWBUF_Pos              1                                                       /*!< PPB ACTLR: DISDEFWBUF Position          */\r
+#define PPB_ACTLR_DISDEFWBUF_Msk              (0x01UL << PPB_ACTLR_DISDEFWBUF_Pos)                    /*!< PPB ACTLR: DISDEFWBUF Mask              */\r
+#define PPB_ACTLR_DISFOLD_Pos                 2                                                       /*!< PPB ACTLR: DISFOLD Position             */\r
+#define PPB_ACTLR_DISFOLD_Msk                 (0x01UL << PPB_ACTLR_DISFOLD_Pos)                       /*!< PPB ACTLR: DISFOLD Mask                 */\r
+#define PPB_ACTLR_DISFPCA_Pos                 8                                                       /*!< PPB ACTLR: DISFPCA Position             */\r
+#define PPB_ACTLR_DISFPCA_Msk                 (0x01UL << PPB_ACTLR_DISFPCA_Pos)                       /*!< PPB ACTLR: DISFPCA Mask                 */\r
+#define PPB_ACTLR_DISOOFP_Pos                 9                                                       /*!< PPB ACTLR: DISOOFP Position             */\r
+#define PPB_ACTLR_DISOOFP_Msk                 (0x01UL << PPB_ACTLR_DISOOFP_Pos)                       /*!< PPB ACTLR: DISOOFP Mask                 */\r
+\r
+/* --------------------------------  PPB_SYST_CSR  -------------------------------- */\r
+#define PPB_SYST_CSR_ENABLE_Pos               0                                                       /*!< PPB SYST_CSR: ENABLE Position           */\r
+#define PPB_SYST_CSR_ENABLE_Msk               (0x01UL << PPB_SYST_CSR_ENABLE_Pos)                     /*!< PPB SYST_CSR: ENABLE Mask               */\r
+#define PPB_SYST_CSR_TICKINT_Pos              1                                                       /*!< PPB SYST_CSR: TICKINT Position          */\r
+#define PPB_SYST_CSR_TICKINT_Msk              (0x01UL << PPB_SYST_CSR_TICKINT_Pos)                    /*!< PPB SYST_CSR: TICKINT Mask              */\r
+#define PPB_SYST_CSR_CLKSOURCE_Pos            2                                                       /*!< PPB SYST_CSR: CLKSOURCE Position        */\r
+#define PPB_SYST_CSR_CLKSOURCE_Msk            (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos)                  /*!< PPB SYST_CSR: CLKSOURCE Mask            */\r
+#define PPB_SYST_CSR_COUNTFLAG_Pos            16                                                      /*!< PPB SYST_CSR: COUNTFLAG Position        */\r
+#define PPB_SYST_CSR_COUNTFLAG_Msk            (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos)                  /*!< PPB SYST_CSR: COUNTFLAG Mask            */\r
+\r
+/* --------------------------------  PPB_SYST_RVR  -------------------------------- */\r
+#define PPB_SYST_RVR_RELOAD_Pos               0                                                       /*!< PPB SYST_RVR: RELOAD Position           */\r
+#define PPB_SYST_RVR_RELOAD_Msk               (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos)               /*!< PPB SYST_RVR: RELOAD Mask               */\r
+\r
+/* --------------------------------  PPB_SYST_CVR  -------------------------------- */\r
+#define PPB_SYST_CVR_CURRENT_Pos              0                                                       /*!< PPB SYST_CVR: CURRENT Position          */\r
+#define PPB_SYST_CVR_CURRENT_Msk              (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos)              /*!< PPB SYST_CVR: CURRENT Mask              */\r
+\r
+/* -------------------------------  PPB_SYST_CALIB  ------------------------------- */\r
+#define PPB_SYST_CALIB_TENMS_Pos              0                                                       /*!< PPB SYST_CALIB: TENMS Position          */\r
+#define PPB_SYST_CALIB_TENMS_Msk              (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos)              /*!< PPB SYST_CALIB: TENMS Mask              */\r
+#define PPB_SYST_CALIB_SKEW_Pos               30                                                      /*!< PPB SYST_CALIB: SKEW Position           */\r
+#define PPB_SYST_CALIB_SKEW_Msk               (0x01UL << PPB_SYST_CALIB_SKEW_Pos)                     /*!< PPB SYST_CALIB: SKEW Mask               */\r
+#define PPB_SYST_CALIB_NOREF_Pos              31                                                      /*!< PPB SYST_CALIB: NOREF Position          */\r
+#define PPB_SYST_CALIB_NOREF_Msk              (0x01UL << PPB_SYST_CALIB_NOREF_Pos)                    /*!< PPB SYST_CALIB: NOREF Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER0  ------------------------------- */\r
+#define PPB_NVIC_ISER0_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER0: SETENA Position         */\r
+#define PPB_NVIC_ISER0_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER0_SETENA_Pos)             /*!< PPB NVIC_ISER0: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER1  ------------------------------- */\r
+#define PPB_NVIC_ISER1_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER1: SETENA Position         */\r
+#define PPB_NVIC_ISER1_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER1_SETENA_Pos)             /*!< PPB NVIC_ISER1: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER2  ------------------------------- */\r
+#define PPB_NVIC_ISER2_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER2: SETENA Position         */\r
+#define PPB_NVIC_ISER2_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER2_SETENA_Pos)             /*!< PPB NVIC_ISER2: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER3  ------------------------------- */\r
+#define PPB_NVIC_ISER3_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER3: SETENA Position         */\r
+#define PPB_NVIC_ISER3_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER3_SETENA_Pos)             /*!< PPB NVIC_ISER3: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER0  ------------------------------- */\r
+#define PPB_NVIC_ICER0_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER0: CLRENA Position         */\r
+#define PPB_NVIC_ICER0_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER0_CLRENA_Pos)             /*!< PPB NVIC_ICER0: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER1  ------------------------------- */\r
+#define PPB_NVIC_ICER1_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER1: CLRENA Position         */\r
+#define PPB_NVIC_ICER1_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER1_CLRENA_Pos)             /*!< PPB NVIC_ICER1: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER2  ------------------------------- */\r
+#define PPB_NVIC_ICER2_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER2: CLRENA Position         */\r
+#define PPB_NVIC_ICER2_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER2_CLRENA_Pos)             /*!< PPB NVIC_ICER2: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER3  ------------------------------- */\r
+#define PPB_NVIC_ICER3_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER3: CLRENA Position         */\r
+#define PPB_NVIC_ICER3_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER3_CLRENA_Pos)             /*!< PPB NVIC_ICER3: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR0  ------------------------------- */\r
+#define PPB_NVIC_ISPR0_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR0: SETPEND Position        */\r
+#define PPB_NVIC_ISPR0_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR0_SETPEND_Pos)            /*!< PPB NVIC_ISPR0: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR1  ------------------------------- */\r
+#define PPB_NVIC_ISPR1_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR1: SETPEND Position        */\r
+#define PPB_NVIC_ISPR1_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR1_SETPEND_Pos)            /*!< PPB NVIC_ISPR1: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR2  ------------------------------- */\r
+#define PPB_NVIC_ISPR2_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR2: SETPEND Position        */\r
+#define PPB_NVIC_ISPR2_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR2_SETPEND_Pos)            /*!< PPB NVIC_ISPR2: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR3  ------------------------------- */\r
+#define PPB_NVIC_ISPR3_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR3: SETPEND Position        */\r
+#define PPB_NVIC_ISPR3_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR3_SETPEND_Pos)            /*!< PPB NVIC_ISPR3: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR0  ------------------------------- */\r
+#define PPB_NVIC_ICPR0_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR0: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR0_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR0_CLRPEND_Pos)            /*!< PPB NVIC_ICPR0: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR1  ------------------------------- */\r
+#define PPB_NVIC_ICPR1_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR1: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR1_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR1_CLRPEND_Pos)            /*!< PPB NVIC_ICPR1: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR2  ------------------------------- */\r
+#define PPB_NVIC_ICPR2_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR2: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR2_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR2_CLRPEND_Pos)            /*!< PPB NVIC_ICPR2: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR3  ------------------------------- */\r
+#define PPB_NVIC_ICPR3_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR3: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR3_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR3_CLRPEND_Pos)            /*!< PPB NVIC_ICPR3: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR0  ------------------------------- */\r
+#define PPB_NVIC_IABR0_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR0: ACTIVE Position         */\r
+#define PPB_NVIC_IABR0_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR0_ACTIVE_Pos)             /*!< PPB NVIC_IABR0: ACTIVE Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR1  ------------------------------- */\r
+#define PPB_NVIC_IABR1_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR1: ACTIVE Position         */\r
+#define PPB_NVIC_IABR1_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR1_ACTIVE_Pos)             /*!< PPB NVIC_IABR1: ACTIVE Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR2  ------------------------------- */\r
+#define PPB_NVIC_IABR2_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR2: ACTIVE Position         */\r
+#define PPB_NVIC_IABR2_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR2_ACTIVE_Pos)             /*!< PPB NVIC_IABR2: ACTIVE Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR3  ------------------------------- */\r
+#define PPB_NVIC_IABR3_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR3: ACTIVE Position         */\r
+#define PPB_NVIC_IABR3_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR3_ACTIVE_Pos)             /*!< PPB NVIC_IABR3: ACTIVE Mask             */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR0  ------------------------------- */\r
+#define PPB_NVIC_IPR0_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR0: PRI_0 Position           */\r
+#define PPB_NVIC_IPR0_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos)               /*!< PPB NVIC_IPR0: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR0_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR0: PRI_1 Position           */\r
+#define PPB_NVIC_IPR0_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos)               /*!< PPB NVIC_IPR0: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR0_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR0: PRI_2 Position           */\r
+#define PPB_NVIC_IPR0_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos)               /*!< PPB NVIC_IPR0: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR0_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR0: PRI_3 Position           */\r
+#define PPB_NVIC_IPR0_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos)               /*!< PPB NVIC_IPR0: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR1  ------------------------------- */\r
+#define PPB_NVIC_IPR1_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR1: PRI_0 Position           */\r
+#define PPB_NVIC_IPR1_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos)               /*!< PPB NVIC_IPR1: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR1_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR1: PRI_1 Position           */\r
+#define PPB_NVIC_IPR1_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos)               /*!< PPB NVIC_IPR1: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR1_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR1: PRI_2 Position           */\r
+#define PPB_NVIC_IPR1_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos)               /*!< PPB NVIC_IPR1: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR1_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR1: PRI_3 Position           */\r
+#define PPB_NVIC_IPR1_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos)               /*!< PPB NVIC_IPR1: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR2  ------------------------------- */\r
+#define PPB_NVIC_IPR2_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR2: PRI_0 Position           */\r
+#define PPB_NVIC_IPR2_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos)               /*!< PPB NVIC_IPR2: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR2_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR2: PRI_1 Position           */\r
+#define PPB_NVIC_IPR2_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos)               /*!< PPB NVIC_IPR2: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR2_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR2: PRI_2 Position           */\r
+#define PPB_NVIC_IPR2_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos)               /*!< PPB NVIC_IPR2: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR2_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR2: PRI_3 Position           */\r
+#define PPB_NVIC_IPR2_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos)               /*!< PPB NVIC_IPR2: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR3  ------------------------------- */\r
+#define PPB_NVIC_IPR3_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR3: PRI_0 Position           */\r
+#define PPB_NVIC_IPR3_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos)               /*!< PPB NVIC_IPR3: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR3_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR3: PRI_1 Position           */\r
+#define PPB_NVIC_IPR3_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos)               /*!< PPB NVIC_IPR3: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR3_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR3: PRI_2 Position           */\r
+#define PPB_NVIC_IPR3_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos)               /*!< PPB NVIC_IPR3: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR3_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR3: PRI_3 Position           */\r
+#define PPB_NVIC_IPR3_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos)               /*!< PPB NVIC_IPR3: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR4  ------------------------------- */\r
+#define PPB_NVIC_IPR4_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR4: PRI_0 Position           */\r
+#define PPB_NVIC_IPR4_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos)               /*!< PPB NVIC_IPR4: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR4_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR4: PRI_1 Position           */\r
+#define PPB_NVIC_IPR4_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos)               /*!< PPB NVIC_IPR4: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR4_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR4: PRI_2 Position           */\r
+#define PPB_NVIC_IPR4_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos)               /*!< PPB NVIC_IPR4: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR4_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR4: PRI_3 Position           */\r
+#define PPB_NVIC_IPR4_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos)               /*!< PPB NVIC_IPR4: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR5  ------------------------------- */\r
+#define PPB_NVIC_IPR5_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR5: PRI_0 Position           */\r
+#define PPB_NVIC_IPR5_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos)               /*!< PPB NVIC_IPR5: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR5_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR5: PRI_1 Position           */\r
+#define PPB_NVIC_IPR5_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos)               /*!< PPB NVIC_IPR5: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR5_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR5: PRI_2 Position           */\r
+#define PPB_NVIC_IPR5_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos)               /*!< PPB NVIC_IPR5: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR5_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR5: PRI_3 Position           */\r
+#define PPB_NVIC_IPR5_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos)               /*!< PPB NVIC_IPR5: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR6  ------------------------------- */\r
+#define PPB_NVIC_IPR6_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR6: PRI_0 Position           */\r
+#define PPB_NVIC_IPR6_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos)               /*!< PPB NVIC_IPR6: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR6_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR6: PRI_1 Position           */\r
+#define PPB_NVIC_IPR6_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos)               /*!< PPB NVIC_IPR6: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR6_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR6: PRI_2 Position           */\r
+#define PPB_NVIC_IPR6_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos)               /*!< PPB NVIC_IPR6: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR6_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR6: PRI_3 Position           */\r
+#define PPB_NVIC_IPR6_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos)               /*!< PPB NVIC_IPR6: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR7  ------------------------------- */\r
+#define PPB_NVIC_IPR7_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR7: PRI_0 Position           */\r
+#define PPB_NVIC_IPR7_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos)               /*!< PPB NVIC_IPR7: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR7_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR7: PRI_1 Position           */\r
+#define PPB_NVIC_IPR7_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos)               /*!< PPB NVIC_IPR7: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR7_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR7: PRI_2 Position           */\r
+#define PPB_NVIC_IPR7_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos)               /*!< PPB NVIC_IPR7: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR7_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR7: PRI_3 Position           */\r
+#define PPB_NVIC_IPR7_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos)               /*!< PPB NVIC_IPR7: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR8  ------------------------------- */\r
+#define PPB_NVIC_IPR8_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR8: PRI_0 Position           */\r
+#define PPB_NVIC_IPR8_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_0_Pos)               /*!< PPB NVIC_IPR8: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR8_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR8: PRI_1 Position           */\r
+#define PPB_NVIC_IPR8_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_1_Pos)               /*!< PPB NVIC_IPR8: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR8_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR8: PRI_2 Position           */\r
+#define PPB_NVIC_IPR8_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_2_Pos)               /*!< PPB NVIC_IPR8: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR8_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR8: PRI_3 Position           */\r
+#define PPB_NVIC_IPR8_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_3_Pos)               /*!< PPB NVIC_IPR8: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR9  ------------------------------- */\r
+#define PPB_NVIC_IPR9_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR9: PRI_0 Position           */\r
+#define PPB_NVIC_IPR9_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_0_Pos)               /*!< PPB NVIC_IPR9: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR9_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR9: PRI_1 Position           */\r
+#define PPB_NVIC_IPR9_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_1_Pos)               /*!< PPB NVIC_IPR9: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR9_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR9: PRI_2 Position           */\r
+#define PPB_NVIC_IPR9_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_2_Pos)               /*!< PPB NVIC_IPR9: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR9_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR9: PRI_3 Position           */\r
+#define PPB_NVIC_IPR9_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_3_Pos)               /*!< PPB NVIC_IPR9: PRI_3 Mask               */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR10  ------------------------------- */\r
+#define PPB_NVIC_IPR10_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR10: PRI_0 Position          */\r
+#define PPB_NVIC_IPR10_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_0_Pos)              /*!< PPB NVIC_IPR10: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR10_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR10: PRI_1 Position          */\r
+#define PPB_NVIC_IPR10_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_1_Pos)              /*!< PPB NVIC_IPR10: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR10_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR10: PRI_2 Position          */\r
+#define PPB_NVIC_IPR10_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_2_Pos)              /*!< PPB NVIC_IPR10: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR10_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR10: PRI_3 Position          */\r
+#define PPB_NVIC_IPR10_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_3_Pos)              /*!< PPB NVIC_IPR10: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR11  ------------------------------- */\r
+#define PPB_NVIC_IPR11_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR11: PRI_0 Position          */\r
+#define PPB_NVIC_IPR11_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_0_Pos)              /*!< PPB NVIC_IPR11: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR11_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR11: PRI_1 Position          */\r
+#define PPB_NVIC_IPR11_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_1_Pos)              /*!< PPB NVIC_IPR11: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR11_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR11: PRI_2 Position          */\r
+#define PPB_NVIC_IPR11_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_2_Pos)              /*!< PPB NVIC_IPR11: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR11_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR11: PRI_3 Position          */\r
+#define PPB_NVIC_IPR11_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_3_Pos)              /*!< PPB NVIC_IPR11: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR12  ------------------------------- */\r
+#define PPB_NVIC_IPR12_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR12: PRI_0 Position          */\r
+#define PPB_NVIC_IPR12_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_0_Pos)              /*!< PPB NVIC_IPR12: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR12_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR12: PRI_1 Position          */\r
+#define PPB_NVIC_IPR12_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_1_Pos)              /*!< PPB NVIC_IPR12: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR12_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR12: PRI_2 Position          */\r
+#define PPB_NVIC_IPR12_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_2_Pos)              /*!< PPB NVIC_IPR12: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR12_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR12: PRI_3 Position          */\r
+#define PPB_NVIC_IPR12_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_3_Pos)              /*!< PPB NVIC_IPR12: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR13  ------------------------------- */\r
+#define PPB_NVIC_IPR13_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR13: PRI_0 Position          */\r
+#define PPB_NVIC_IPR13_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_0_Pos)              /*!< PPB NVIC_IPR13: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR13_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR13: PRI_1 Position          */\r
+#define PPB_NVIC_IPR13_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_1_Pos)              /*!< PPB NVIC_IPR13: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR13_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR13: PRI_2 Position          */\r
+#define PPB_NVIC_IPR13_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_2_Pos)              /*!< PPB NVIC_IPR13: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR13_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR13: PRI_3 Position          */\r
+#define PPB_NVIC_IPR13_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_3_Pos)              /*!< PPB NVIC_IPR13: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR14  ------------------------------- */\r
+#define PPB_NVIC_IPR14_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR14: PRI_0 Position          */\r
+#define PPB_NVIC_IPR14_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_0_Pos)              /*!< PPB NVIC_IPR14: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR14_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR14: PRI_1 Position          */\r
+#define PPB_NVIC_IPR14_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_1_Pos)              /*!< PPB NVIC_IPR14: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR14_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR14: PRI_2 Position          */\r
+#define PPB_NVIC_IPR14_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_2_Pos)              /*!< PPB NVIC_IPR14: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR14_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR14: PRI_3 Position          */\r
+#define PPB_NVIC_IPR14_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_3_Pos)              /*!< PPB NVIC_IPR14: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR15  ------------------------------- */\r
+#define PPB_NVIC_IPR15_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR15: PRI_0 Position          */\r
+#define PPB_NVIC_IPR15_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_0_Pos)              /*!< PPB NVIC_IPR15: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR15_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR15: PRI_1 Position          */\r
+#define PPB_NVIC_IPR15_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_1_Pos)              /*!< PPB NVIC_IPR15: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR15_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR15: PRI_2 Position          */\r
+#define PPB_NVIC_IPR15_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_2_Pos)              /*!< PPB NVIC_IPR15: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR15_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR15: PRI_3 Position          */\r
+#define PPB_NVIC_IPR15_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_3_Pos)              /*!< PPB NVIC_IPR15: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR16  ------------------------------- */\r
+#define PPB_NVIC_IPR16_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR16: PRI_0 Position          */\r
+#define PPB_NVIC_IPR16_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_0_Pos)              /*!< PPB NVIC_IPR16: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR16_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR16: PRI_1 Position          */\r
+#define PPB_NVIC_IPR16_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_1_Pos)              /*!< PPB NVIC_IPR16: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR16_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR16: PRI_2 Position          */\r
+#define PPB_NVIC_IPR16_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_2_Pos)              /*!< PPB NVIC_IPR16: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR16_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR16: PRI_3 Position          */\r
+#define PPB_NVIC_IPR16_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_3_Pos)              /*!< PPB NVIC_IPR16: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR17  ------------------------------- */\r
+#define PPB_NVIC_IPR17_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR17: PRI_0 Position          */\r
+#define PPB_NVIC_IPR17_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_0_Pos)              /*!< PPB NVIC_IPR17: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR17_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR17: PRI_1 Position          */\r
+#define PPB_NVIC_IPR17_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_1_Pos)              /*!< PPB NVIC_IPR17: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR17_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR17: PRI_2 Position          */\r
+#define PPB_NVIC_IPR17_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_2_Pos)              /*!< PPB NVIC_IPR17: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR17_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR17: PRI_3 Position          */\r
+#define PPB_NVIC_IPR17_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_3_Pos)              /*!< PPB NVIC_IPR17: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR18  ------------------------------- */\r
+#define PPB_NVIC_IPR18_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR18: PRI_0 Position          */\r
+#define PPB_NVIC_IPR18_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_0_Pos)              /*!< PPB NVIC_IPR18: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR18_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR18: PRI_1 Position          */\r
+#define PPB_NVIC_IPR18_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_1_Pos)              /*!< PPB NVIC_IPR18: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR18_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR18: PRI_2 Position          */\r
+#define PPB_NVIC_IPR18_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_2_Pos)              /*!< PPB NVIC_IPR18: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR18_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR18: PRI_3 Position          */\r
+#define PPB_NVIC_IPR18_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_3_Pos)              /*!< PPB NVIC_IPR18: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR19  ------------------------------- */\r
+#define PPB_NVIC_IPR19_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR19: PRI_0 Position          */\r
+#define PPB_NVIC_IPR19_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_0_Pos)              /*!< PPB NVIC_IPR19: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR19_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR19: PRI_1 Position          */\r
+#define PPB_NVIC_IPR19_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_1_Pos)              /*!< PPB NVIC_IPR19: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR19_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR19: PRI_2 Position          */\r
+#define PPB_NVIC_IPR19_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_2_Pos)              /*!< PPB NVIC_IPR19: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR19_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR19: PRI_3 Position          */\r
+#define PPB_NVIC_IPR19_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_3_Pos)              /*!< PPB NVIC_IPR19: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR20  ------------------------------- */\r
+#define PPB_NVIC_IPR20_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR20: PRI_0 Position          */\r
+#define PPB_NVIC_IPR20_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_0_Pos)              /*!< PPB NVIC_IPR20: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR20_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR20: PRI_1 Position          */\r
+#define PPB_NVIC_IPR20_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_1_Pos)              /*!< PPB NVIC_IPR20: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR20_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR20: PRI_2 Position          */\r
+#define PPB_NVIC_IPR20_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_2_Pos)              /*!< PPB NVIC_IPR20: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR20_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR20: PRI_3 Position          */\r
+#define PPB_NVIC_IPR20_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_3_Pos)              /*!< PPB NVIC_IPR20: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR21  ------------------------------- */\r
+#define PPB_NVIC_IPR21_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR21: PRI_0 Position          */\r
+#define PPB_NVIC_IPR21_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_0_Pos)              /*!< PPB NVIC_IPR21: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR21_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR21: PRI_1 Position          */\r
+#define PPB_NVIC_IPR21_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_1_Pos)              /*!< PPB NVIC_IPR21: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR21_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR21: PRI_2 Position          */\r
+#define PPB_NVIC_IPR21_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_2_Pos)              /*!< PPB NVIC_IPR21: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR21_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR21: PRI_3 Position          */\r
+#define PPB_NVIC_IPR21_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_3_Pos)              /*!< PPB NVIC_IPR21: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR22  ------------------------------- */\r
+#define PPB_NVIC_IPR22_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR22: PRI_0 Position          */\r
+#define PPB_NVIC_IPR22_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_0_Pos)              /*!< PPB NVIC_IPR22: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR22_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR22: PRI_1 Position          */\r
+#define PPB_NVIC_IPR22_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_1_Pos)              /*!< PPB NVIC_IPR22: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR22_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR22: PRI_2 Position          */\r
+#define PPB_NVIC_IPR22_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_2_Pos)              /*!< PPB NVIC_IPR22: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR22_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR22: PRI_3 Position          */\r
+#define PPB_NVIC_IPR22_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_3_Pos)              /*!< PPB NVIC_IPR22: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR23  ------------------------------- */\r
+#define PPB_NVIC_IPR23_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR23: PRI_0 Position          */\r
+#define PPB_NVIC_IPR23_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_0_Pos)              /*!< PPB NVIC_IPR23: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR23_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR23: PRI_1 Position          */\r
+#define PPB_NVIC_IPR23_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_1_Pos)              /*!< PPB NVIC_IPR23: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR23_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR23: PRI_2 Position          */\r
+#define PPB_NVIC_IPR23_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_2_Pos)              /*!< PPB NVIC_IPR23: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR23_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR23: PRI_3 Position          */\r
+#define PPB_NVIC_IPR23_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_3_Pos)              /*!< PPB NVIC_IPR23: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR24  ------------------------------- */\r
+#define PPB_NVIC_IPR24_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR24: PRI_0 Position          */\r
+#define PPB_NVIC_IPR24_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_0_Pos)              /*!< PPB NVIC_IPR24: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR24_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR24: PRI_1 Position          */\r
+#define PPB_NVIC_IPR24_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_1_Pos)              /*!< PPB NVIC_IPR24: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR24_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR24: PRI_2 Position          */\r
+#define PPB_NVIC_IPR24_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_2_Pos)              /*!< PPB NVIC_IPR24: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR24_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR24: PRI_3 Position          */\r
+#define PPB_NVIC_IPR24_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_3_Pos)              /*!< PPB NVIC_IPR24: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR25  ------------------------------- */\r
+#define PPB_NVIC_IPR25_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR25: PRI_0 Position          */\r
+#define PPB_NVIC_IPR25_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_0_Pos)              /*!< PPB NVIC_IPR25: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR25_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR25: PRI_1 Position          */\r
+#define PPB_NVIC_IPR25_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_1_Pos)              /*!< PPB NVIC_IPR25: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR25_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR25: PRI_2 Position          */\r
+#define PPB_NVIC_IPR25_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_2_Pos)              /*!< PPB NVIC_IPR25: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR25_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR25: PRI_3 Position          */\r
+#define PPB_NVIC_IPR25_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_3_Pos)              /*!< PPB NVIC_IPR25: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR26  ------------------------------- */\r
+#define PPB_NVIC_IPR26_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR26: PRI_0 Position          */\r
+#define PPB_NVIC_IPR26_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_0_Pos)              /*!< PPB NVIC_IPR26: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR26_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR26: PRI_1 Position          */\r
+#define PPB_NVIC_IPR26_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_1_Pos)              /*!< PPB NVIC_IPR26: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR26_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR26: PRI_2 Position          */\r
+#define PPB_NVIC_IPR26_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_2_Pos)              /*!< PPB NVIC_IPR26: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR26_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR26: PRI_3 Position          */\r
+#define PPB_NVIC_IPR26_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_3_Pos)              /*!< PPB NVIC_IPR26: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR27  ------------------------------- */\r
+#define PPB_NVIC_IPR27_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR27: PRI_0 Position          */\r
+#define PPB_NVIC_IPR27_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_0_Pos)              /*!< PPB NVIC_IPR27: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR27_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR27: PRI_1 Position          */\r
+#define PPB_NVIC_IPR27_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_1_Pos)              /*!< PPB NVIC_IPR27: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR27_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR27: PRI_2 Position          */\r
+#define PPB_NVIC_IPR27_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_2_Pos)              /*!< PPB NVIC_IPR27: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR27_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR27: PRI_3 Position          */\r
+#define PPB_NVIC_IPR27_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_3_Pos)              /*!< PPB NVIC_IPR27: PRI_3 Mask              */\r
+\r
+/* ----------------------------------  PPB_CPUID  --------------------------------- */\r
+#define PPB_CPUID_Revision_Pos                0                                                       /*!< PPB CPUID: Revision Position            */\r
+#define PPB_CPUID_Revision_Msk                (0x0fUL << PPB_CPUID_Revision_Pos)                      /*!< PPB CPUID: Revision Mask                */\r
+#define PPB_CPUID_PartNo_Pos                  4                                                       /*!< PPB CPUID: PartNo Position              */\r
+#define PPB_CPUID_PartNo_Msk                  (0x00000fffUL << PPB_CPUID_PartNo_Pos)                  /*!< PPB CPUID: PartNo Mask                  */\r
+#define PPB_CPUID_Constant_Pos                16                                                      /*!< PPB CPUID: Constant Position            */\r
+#define PPB_CPUID_Constant_Msk                (0x0fUL << PPB_CPUID_Constant_Pos)                      /*!< PPB CPUID: Constant Mask                */\r
+#define PPB_CPUID_Variant_Pos                 20                                                      /*!< PPB CPUID: Variant Position             */\r
+#define PPB_CPUID_Variant_Msk                 (0x0fUL << PPB_CPUID_Variant_Pos)                       /*!< PPB CPUID: Variant Mask                 */\r
+#define PPB_CPUID_Implementer_Pos             24                                                      /*!< PPB CPUID: Implementer Position         */\r
+#define PPB_CPUID_Implementer_Msk             (0x000000ffUL << PPB_CPUID_Implementer_Pos)             /*!< PPB CPUID: Implementer Mask             */\r
+\r
+/* ----------------------------------  PPB_ICSR  ---------------------------------- */\r
+#define PPB_ICSR_VECTACTIVE_Pos               0                                                       /*!< PPB ICSR: VECTACTIVE Position           */\r
+#define PPB_ICSR_VECTACTIVE_Msk               (0x000001ffUL << PPB_ICSR_VECTACTIVE_Pos)               /*!< PPB ICSR: VECTACTIVE Mask               */\r
+#define PPB_ICSR_RETTOBASE_Pos                11                                                      /*!< PPB ICSR: RETTOBASE Position            */\r
+#define PPB_ICSR_RETTOBASE_Msk                (0x01UL << PPB_ICSR_RETTOBASE_Pos)                      /*!< PPB ICSR: RETTOBASE Mask                */\r
+#define PPB_ICSR_VECTPENDING_Pos              12                                                      /*!< PPB ICSR: VECTPENDING Position          */\r
+#define PPB_ICSR_VECTPENDING_Msk              (0x3fUL << PPB_ICSR_VECTPENDING_Pos)                    /*!< PPB ICSR: VECTPENDING Mask              */\r
+#define PPB_ICSR_ISRPENDING_Pos               22                                                      /*!< PPB ICSR: ISRPENDING Position           */\r
+#define PPB_ICSR_ISRPENDING_Msk               (0x01UL << PPB_ICSR_ISRPENDING_Pos)                     /*!< PPB ICSR: ISRPENDING Mask               */\r
+#define PPB_ICSR_Res_Pos                      23                                                      /*!< PPB ICSR: Res Position                  */\r
+#define PPB_ICSR_Res_Msk                      (0x01UL << PPB_ICSR_Res_Pos)                            /*!< PPB ICSR: Res Mask                      */\r
+#define PPB_ICSR_PENDSTCLR_Pos                25                                                      /*!< PPB ICSR: PENDSTCLR Position            */\r
+#define PPB_ICSR_PENDSTCLR_Msk                (0x01UL << PPB_ICSR_PENDSTCLR_Pos)                      /*!< PPB ICSR: PENDSTCLR Mask                */\r
+#define PPB_ICSR_PENDSTSET_Pos                26                                                      /*!< PPB ICSR: PENDSTSET Position            */\r
+#define PPB_ICSR_PENDSTSET_Msk                (0x01UL << PPB_ICSR_PENDSTSET_Pos)                      /*!< PPB ICSR: PENDSTSET Mask                */\r
+#define PPB_ICSR_PENDSVCLR_Pos                27                                                      /*!< PPB ICSR: PENDSVCLR Position            */\r
+#define PPB_ICSR_PENDSVCLR_Msk                (0x01UL << PPB_ICSR_PENDSVCLR_Pos)                      /*!< PPB ICSR: PENDSVCLR Mask                */\r
+#define PPB_ICSR_PENDSVSET_Pos                28                                                      /*!< PPB ICSR: PENDSVSET Position            */\r
+#define PPB_ICSR_PENDSVSET_Msk                (0x01UL << PPB_ICSR_PENDSVSET_Pos)                      /*!< PPB ICSR: PENDSVSET Mask                */\r
+#define PPB_ICSR_NMIPENDSET_Pos               31                                                      /*!< PPB ICSR: NMIPENDSET Position           */\r
+#define PPB_ICSR_NMIPENDSET_Msk               (0x01UL << PPB_ICSR_NMIPENDSET_Pos)                     /*!< PPB ICSR: NMIPENDSET Mask               */\r
+\r
+/* ----------------------------------  PPB_VTOR  ---------------------------------- */\r
+#define PPB_VTOR_TBLOFF_Pos                   10                                                      /*!< PPB VTOR: TBLOFF Position               */\r
+#define PPB_VTOR_TBLOFF_Msk                   (0x003fffffUL << PPB_VTOR_TBLOFF_Pos)                   /*!< PPB VTOR: TBLOFF Mask                   */\r
+\r
+/* ----------------------------------  PPB_AIRCR  --------------------------------- */\r
+#define PPB_AIRCR_VECTRESET_Pos               0                                                       /*!< PPB AIRCR: VECTRESET Position           */\r
+#define PPB_AIRCR_VECTRESET_Msk               (0x01UL << PPB_AIRCR_VECTRESET_Pos)                     /*!< PPB AIRCR: VECTRESET Mask               */\r
+#define PPB_AIRCR_VECTCLRACTIVE_Pos           1                                                       /*!< PPB AIRCR: VECTCLRACTIVE Position       */\r
+#define PPB_AIRCR_VECTCLRACTIVE_Msk           (0x01UL << PPB_AIRCR_VECTCLRACTIVE_Pos)                 /*!< PPB AIRCR: VECTCLRACTIVE Mask           */\r
+#define PPB_AIRCR_SYSRESETREQ_Pos             2                                                       /*!< PPB AIRCR: SYSRESETREQ Position         */\r
+#define PPB_AIRCR_SYSRESETREQ_Msk             (0x01UL << PPB_AIRCR_SYSRESETREQ_Pos)                   /*!< PPB AIRCR: SYSRESETREQ Mask             */\r
+#define PPB_AIRCR_PRIGROUP_Pos                8                                                       /*!< PPB AIRCR: PRIGROUP Position            */\r
+#define PPB_AIRCR_PRIGROUP_Msk                (0x07UL << PPB_AIRCR_PRIGROUP_Pos)                      /*!< PPB AIRCR: PRIGROUP Mask                */\r
+#define PPB_AIRCR_ENDIANNESS_Pos              15                                                      /*!< PPB AIRCR: ENDIANNESS Position          */\r
+#define PPB_AIRCR_ENDIANNESS_Msk              (0x01UL << PPB_AIRCR_ENDIANNESS_Pos)                    /*!< PPB AIRCR: ENDIANNESS Mask              */\r
+#define PPB_AIRCR_VECTKEY_Pos                 16                                                      /*!< PPB AIRCR: VECTKEY Position             */\r
+#define PPB_AIRCR_VECTKEY_Msk                 (0x0000ffffUL << PPB_AIRCR_VECTKEY_Pos)                 /*!< PPB AIRCR: VECTKEY Mask                 */\r
+\r
+/* -----------------------------------  PPB_SCR  ---------------------------------- */\r
+#define PPB_SCR_SLEEPONEXIT_Pos               1                                                       /*!< PPB SCR: SLEEPONEXIT Position           */\r
+#define PPB_SCR_SLEEPONEXIT_Msk               (0x01UL << PPB_SCR_SLEEPONEXIT_Pos)                     /*!< PPB SCR: SLEEPONEXIT Mask               */\r
+#define PPB_SCR_SLEEPDEEP_Pos                 2                                                       /*!< PPB SCR: SLEEPDEEP Position             */\r
+#define PPB_SCR_SLEEPDEEP_Msk                 (0x01UL << PPB_SCR_SLEEPDEEP_Pos)                       /*!< PPB SCR: SLEEPDEEP Mask                 */\r
+#define PPB_SCR_SEVONPEND_Pos                 4                                                       /*!< PPB SCR: SEVONPEND Position             */\r
+#define PPB_SCR_SEVONPEND_Msk                 (0x01UL << PPB_SCR_SEVONPEND_Pos)                       /*!< PPB SCR: SEVONPEND Mask                 */\r
+\r
+/* -----------------------------------  PPB_CCR  ---------------------------------- */\r
+#define PPB_CCR_NONBASETHRDENA_Pos            0                                                       /*!< PPB CCR: NONBASETHRDENA Position        */\r
+#define PPB_CCR_NONBASETHRDENA_Msk            (0x01UL << PPB_CCR_NONBASETHRDENA_Pos)                  /*!< PPB CCR: NONBASETHRDENA Mask            */\r
+#define PPB_CCR_USERSETMPEND_Pos              1                                                       /*!< PPB CCR: USERSETMPEND Position          */\r
+#define PPB_CCR_USERSETMPEND_Msk              (0x01UL << PPB_CCR_USERSETMPEND_Pos)                    /*!< PPB CCR: USERSETMPEND Mask              */\r
+#define PPB_CCR_UNALIGN_TRP_Pos               3                                                       /*!< PPB CCR: UNALIGN_TRP Position           */\r
+#define PPB_CCR_UNALIGN_TRP_Msk               (0x01UL << PPB_CCR_UNALIGN_TRP_Pos)                     /*!< PPB CCR: UNALIGN_TRP Mask               */\r
+#define PPB_CCR_DIV_0_TRP_Pos                 4                                                       /*!< PPB CCR: DIV_0_TRP Position             */\r
+#define PPB_CCR_DIV_0_TRP_Msk                 (0x01UL << PPB_CCR_DIV_0_TRP_Pos)                       /*!< PPB CCR: DIV_0_TRP Mask                 */\r
+#define PPB_CCR_BFHFNMIGN_Pos                 8                                                       /*!< PPB CCR: BFHFNMIGN Position             */\r
+#define PPB_CCR_BFHFNMIGN_Msk                 (0x01UL << PPB_CCR_BFHFNMIGN_Pos)                       /*!< PPB CCR: BFHFNMIGN Mask                 */\r
+#define PPB_CCR_STKALIGN_Pos                  9                                                       /*!< PPB CCR: STKALIGN Position              */\r
+#define PPB_CCR_STKALIGN_Msk                  (0x01UL << PPB_CCR_STKALIGN_Pos)                        /*!< PPB CCR: STKALIGN Mask                  */\r
+\r
+/* ----------------------------------  PPB_SHPR1  --------------------------------- */\r
+#define PPB_SHPR1_PRI_4_Pos                   0                                                       /*!< PPB SHPR1: PRI_4 Position               */\r
+#define PPB_SHPR1_PRI_4_Msk                   (0x000000ffUL << PPB_SHPR1_PRI_4_Pos)                   /*!< PPB SHPR1: PRI_4 Mask                   */\r
+#define PPB_SHPR1_PRI_5_Pos                   8                                                       /*!< PPB SHPR1: PRI_5 Position               */\r
+#define PPB_SHPR1_PRI_5_Msk                   (0x000000ffUL << PPB_SHPR1_PRI_5_Pos)                   /*!< PPB SHPR1: PRI_5 Mask                   */\r
+#define PPB_SHPR1_PRI_6_Pos                   16                                                      /*!< PPB SHPR1: PRI_6 Position               */\r
+#define PPB_SHPR1_PRI_6_Msk                   (0x000000ffUL << PPB_SHPR1_PRI_6_Pos)                   /*!< PPB SHPR1: PRI_6 Mask                   */\r
+\r
+/* ----------------------------------  PPB_SHPR2  --------------------------------- */\r
+#define PPB_SHPR2_PRI_11_Pos                  24                                                      /*!< PPB SHPR2: PRI_11 Position              */\r
+#define PPB_SHPR2_PRI_11_Msk                  (0x000000ffUL << PPB_SHPR2_PRI_11_Pos)                  /*!< PPB SHPR2: PRI_11 Mask                  */\r
+\r
+/* ----------------------------------  PPB_SHPR3  --------------------------------- */\r
+#define PPB_SHPR3_PRI_14_Pos                  16                                                      /*!< PPB SHPR3: PRI_14 Position              */\r
+#define PPB_SHPR3_PRI_14_Msk                  (0x000000ffUL << PPB_SHPR3_PRI_14_Pos)                  /*!< PPB SHPR3: PRI_14 Mask                  */\r
+#define PPB_SHPR3_PRI_15_Pos                  24                                                      /*!< PPB SHPR3: PRI_15 Position              */\r
+#define PPB_SHPR3_PRI_15_Msk                  (0x000000ffUL << PPB_SHPR3_PRI_15_Pos)                  /*!< PPB SHPR3: PRI_15 Mask                  */\r
+\r
+/* ----------------------------------  PPB_SHCSR  --------------------------------- */\r
+#define PPB_SHCSR_MEMFAULTACT_Pos             0                                                       /*!< PPB SHCSR: MEMFAULTACT Position         */\r
+#define PPB_SHCSR_MEMFAULTACT_Msk             (0x01UL << PPB_SHCSR_MEMFAULTACT_Pos)                   /*!< PPB SHCSR: MEMFAULTACT Mask             */\r
+#define PPB_SHCSR_BUSFAULTACT_Pos             1                                                       /*!< PPB SHCSR: BUSFAULTACT Position         */\r
+#define PPB_SHCSR_BUSFAULTACT_Msk             (0x01UL << PPB_SHCSR_BUSFAULTACT_Pos)                   /*!< PPB SHCSR: BUSFAULTACT Mask             */\r
+#define PPB_SHCSR_USGFAULTACT_Pos             3                                                       /*!< PPB SHCSR: USGFAULTACT Position         */\r
+#define PPB_SHCSR_USGFAULTACT_Msk             (0x01UL << PPB_SHCSR_USGFAULTACT_Pos)                   /*!< PPB SHCSR: USGFAULTACT Mask             */\r
+#define PPB_SHCSR_SVCALLACT_Pos               7                                                       /*!< PPB SHCSR: SVCALLACT Position           */\r
+#define PPB_SHCSR_SVCALLACT_Msk               (0x01UL << PPB_SHCSR_SVCALLACT_Pos)                     /*!< PPB SHCSR: SVCALLACT Mask               */\r
+#define PPB_SHCSR_MONITORACT_Pos              8                                                       /*!< PPB SHCSR: MONITORACT Position          */\r
+#define PPB_SHCSR_MONITORACT_Msk              (0x01UL << PPB_SHCSR_MONITORACT_Pos)                    /*!< PPB SHCSR: MONITORACT Mask              */\r
+#define PPB_SHCSR_PENDSVACT_Pos               10                                                      /*!< PPB SHCSR: PENDSVACT Position           */\r
+#define PPB_SHCSR_PENDSVACT_Msk               (0x01UL << PPB_SHCSR_PENDSVACT_Pos)                     /*!< PPB SHCSR: PENDSVACT Mask               */\r
+#define PPB_SHCSR_SYSTICKACT_Pos              11                                                      /*!< PPB SHCSR: SYSTICKACT Position          */\r
+#define PPB_SHCSR_SYSTICKACT_Msk              (0x01UL << PPB_SHCSR_SYSTICKACT_Pos)                    /*!< PPB SHCSR: SYSTICKACT Mask              */\r
+#define PPB_SHCSR_USGFAULTPENDED_Pos          12                                                      /*!< PPB SHCSR: USGFAULTPENDED Position      */\r
+#define PPB_SHCSR_USGFAULTPENDED_Msk          (0x01UL << PPB_SHCSR_USGFAULTPENDED_Pos)                /*!< PPB SHCSR: USGFAULTPENDED Mask          */\r
+#define PPB_SHCSR_MEMFAULTPENDED_Pos          13                                                      /*!< PPB SHCSR: MEMFAULTPENDED Position      */\r
+#define PPB_SHCSR_MEMFAULTPENDED_Msk          (0x01UL << PPB_SHCSR_MEMFAULTPENDED_Pos)                /*!< PPB SHCSR: MEMFAULTPENDED Mask          */\r
+#define PPB_SHCSR_BUSFAULTPENDED_Pos          14                                                      /*!< PPB SHCSR: BUSFAULTPENDED Position      */\r
+#define PPB_SHCSR_BUSFAULTPENDED_Msk          (0x01UL << PPB_SHCSR_BUSFAULTPENDED_Pos)                /*!< PPB SHCSR: BUSFAULTPENDED Mask          */\r
+#define PPB_SHCSR_SVCALLPENDED_Pos            15                                                      /*!< PPB SHCSR: SVCALLPENDED Position        */\r
+#define PPB_SHCSR_SVCALLPENDED_Msk            (0x01UL << PPB_SHCSR_SVCALLPENDED_Pos)                  /*!< PPB SHCSR: SVCALLPENDED Mask            */\r
+#define PPB_SHCSR_MEMFAULTENA_Pos             16                                                      /*!< PPB SHCSR: MEMFAULTENA Position         */\r
+#define PPB_SHCSR_MEMFAULTENA_Msk             (0x01UL << PPB_SHCSR_MEMFAULTENA_Pos)                   /*!< PPB SHCSR: MEMFAULTENA Mask             */\r
+#define PPB_SHCSR_BUSFAULTENA_Pos             17                                                      /*!< PPB SHCSR: BUSFAULTENA Position         */\r
+#define PPB_SHCSR_BUSFAULTENA_Msk             (0x01UL << PPB_SHCSR_BUSFAULTENA_Pos)                   /*!< PPB SHCSR: BUSFAULTENA Mask             */\r
+#define PPB_SHCSR_USGFAULTENA_Pos             18                                                      /*!< PPB SHCSR: USGFAULTENA Position         */\r
+#define PPB_SHCSR_USGFAULTENA_Msk             (0x01UL << PPB_SHCSR_USGFAULTENA_Pos)                   /*!< PPB SHCSR: USGFAULTENA Mask             */\r
+\r
+/* ----------------------------------  PPB_CFSR  ---------------------------------- */\r
+#define PPB_CFSR_IACCVIOL_Pos                 0                                                       /*!< PPB CFSR: IACCVIOL Position             */\r
+#define PPB_CFSR_IACCVIOL_Msk                 (0x01UL << PPB_CFSR_IACCVIOL_Pos)                       /*!< PPB CFSR: IACCVIOL Mask                 */\r
+#define PPB_CFSR_DACCVIOL_Pos                 1                                                       /*!< PPB CFSR: DACCVIOL Position             */\r
+#define PPB_CFSR_DACCVIOL_Msk                 (0x01UL << PPB_CFSR_DACCVIOL_Pos)                       /*!< PPB CFSR: DACCVIOL Mask                 */\r
+#define PPB_CFSR_MUNSTKERR_Pos                3                                                       /*!< PPB CFSR: MUNSTKERR Position            */\r
+#define PPB_CFSR_MUNSTKERR_Msk                (0x01UL << PPB_CFSR_MUNSTKERR_Pos)                      /*!< PPB CFSR: MUNSTKERR Mask                */\r
+#define PPB_CFSR_MSTKERR_Pos                  4                                                       /*!< PPB CFSR: MSTKERR Position              */\r
+#define PPB_CFSR_MSTKERR_Msk                  (0x01UL << PPB_CFSR_MSTKERR_Pos)                        /*!< PPB CFSR: MSTKERR Mask                  */\r
+#define PPB_CFSR_MLSPERR_Pos                  5                                                       /*!< PPB CFSR: MLSPERR Position              */\r
+#define PPB_CFSR_MLSPERR_Msk                  (0x01UL << PPB_CFSR_MLSPERR_Pos)                        /*!< PPB CFSR: MLSPERR Mask                  */\r
+#define PPB_CFSR_MMARVALID_Pos                7                                                       /*!< PPB CFSR: MMARVALID Position            */\r
+#define PPB_CFSR_MMARVALID_Msk                (0x01UL << PPB_CFSR_MMARVALID_Pos)                      /*!< PPB CFSR: MMARVALID Mask                */\r
+#define PPB_CFSR_IBUSERR_Pos                  8                                                       /*!< PPB CFSR: IBUSERR Position              */\r
+#define PPB_CFSR_IBUSERR_Msk                  (0x01UL << PPB_CFSR_IBUSERR_Pos)                        /*!< PPB CFSR: IBUSERR Mask                  */\r
+#define PPB_CFSR_PRECISERR_Pos                9                                                       /*!< PPB CFSR: PRECISERR Position            */\r
+#define PPB_CFSR_PRECISERR_Msk                (0x01UL << PPB_CFSR_PRECISERR_Pos)                      /*!< PPB CFSR: PRECISERR Mask                */\r
+#define PPB_CFSR_IMPRECISERR_Pos              10                                                      /*!< PPB CFSR: IMPRECISERR Position          */\r
+#define PPB_CFSR_IMPRECISERR_Msk              (0x01UL << PPB_CFSR_IMPRECISERR_Pos)                    /*!< PPB CFSR: IMPRECISERR Mask              */\r
+#define PPB_CFSR_UNSTKERR_Pos                 11                                                      /*!< PPB CFSR: UNSTKERR Position             */\r
+#define PPB_CFSR_UNSTKERR_Msk                 (0x01UL << PPB_CFSR_UNSTKERR_Pos)                       /*!< PPB CFSR: UNSTKERR Mask                 */\r
+#define PPB_CFSR_STKERR_Pos                   12                                                      /*!< PPB CFSR: STKERR Position               */\r
+#define PPB_CFSR_STKERR_Msk                   (0x01UL << PPB_CFSR_STKERR_Pos)                         /*!< PPB CFSR: STKERR Mask                   */\r
+#define PPB_CFSR_LSPERR_Pos                   13                                                      /*!< PPB CFSR: LSPERR Position               */\r
+#define PPB_CFSR_LSPERR_Msk                   (0x01UL << PPB_CFSR_LSPERR_Pos)                         /*!< PPB CFSR: LSPERR Mask                   */\r
+#define PPB_CFSR_BFARVALID_Pos                15                                                      /*!< PPB CFSR: BFARVALID Position            */\r
+#define PPB_CFSR_BFARVALID_Msk                (0x01UL << PPB_CFSR_BFARVALID_Pos)                      /*!< PPB CFSR: BFARVALID Mask                */\r
+#define PPB_CFSR_UNDEFINSTR_Pos               16                                                      /*!< PPB CFSR: UNDEFINSTR Position           */\r
+#define PPB_CFSR_UNDEFINSTR_Msk               (0x01UL << PPB_CFSR_UNDEFINSTR_Pos)                     /*!< PPB CFSR: UNDEFINSTR Mask               */\r
+#define PPB_CFSR_INVSTATE_Pos                 17                                                      /*!< PPB CFSR: INVSTATE Position             */\r
+#define PPB_CFSR_INVSTATE_Msk                 (0x01UL << PPB_CFSR_INVSTATE_Pos)                       /*!< PPB CFSR: INVSTATE Mask                 */\r
+#define PPB_CFSR_INVPC_Pos                    18                                                      /*!< PPB CFSR: INVPC Position                */\r
+#define PPB_CFSR_INVPC_Msk                    (0x01UL << PPB_CFSR_INVPC_Pos)                          /*!< PPB CFSR: INVPC Mask                    */\r
+#define PPB_CFSR_NOCP_Pos                     19                                                      /*!< PPB CFSR: NOCP Position                 */\r
+#define PPB_CFSR_NOCP_Msk                     (0x01UL << PPB_CFSR_NOCP_Pos)                           /*!< PPB CFSR: NOCP Mask                     */\r
+#define PPB_CFSR_UNALIGNED_Pos                24                                                      /*!< PPB CFSR: UNALIGNED Position            */\r
+#define PPB_CFSR_UNALIGNED_Msk                (0x01UL << PPB_CFSR_UNALIGNED_Pos)                      /*!< PPB CFSR: UNALIGNED Mask                */\r
+#define PPB_CFSR_DIVBYZERO_Pos                25                                                      /*!< PPB CFSR: DIVBYZERO Position            */\r
+#define PPB_CFSR_DIVBYZERO_Msk                (0x01UL << PPB_CFSR_DIVBYZERO_Pos)                      /*!< PPB CFSR: DIVBYZERO Mask                */\r
+\r
+/* ----------------------------------  PPB_HFSR  ---------------------------------- */\r
+#define PPB_HFSR_VECTTBL_Pos                  1                                                       /*!< PPB HFSR: VECTTBL Position              */\r
+#define PPB_HFSR_VECTTBL_Msk                  (0x01UL << PPB_HFSR_VECTTBL_Pos)                        /*!< PPB HFSR: VECTTBL Mask                  */\r
+#define PPB_HFSR_FORCED_Pos                   30                                                      /*!< PPB HFSR: FORCED Position               */\r
+#define PPB_HFSR_FORCED_Msk                   (0x01UL << PPB_HFSR_FORCED_Pos)                         /*!< PPB HFSR: FORCED Mask                   */\r
+#define PPB_HFSR_DEBUGEVT_Pos                 31                                                      /*!< PPB HFSR: DEBUGEVT Position             */\r
+#define PPB_HFSR_DEBUGEVT_Msk                 (0x01UL << PPB_HFSR_DEBUGEVT_Pos)                       /*!< PPB HFSR: DEBUGEVT Mask                 */\r
+\r
+/* ----------------------------------  PPB_MMFAR  --------------------------------- */\r
+#define PPB_MMFAR_ADDRESS_Pos                 0                                                       /*!< PPB MMFAR: ADDRESS Position             */\r
+#define PPB_MMFAR_ADDRESS_Msk                 (0xffffffffUL << PPB_MMFAR_ADDRESS_Pos)                 /*!< PPB MMFAR: ADDRESS Mask                 */\r
+\r
+/* ----------------------------------  PPB_BFAR  ---------------------------------- */\r
+#define PPB_BFAR_ADDRESS_Pos                  0                                                       /*!< PPB BFAR: ADDRESS Position              */\r
+#define PPB_BFAR_ADDRESS_Msk                  (0xffffffffUL << PPB_BFAR_ADDRESS_Pos)                  /*!< PPB BFAR: ADDRESS Mask                  */\r
+\r
+/* ----------------------------------  PPB_AFSR  ---------------------------------- */\r
+#define PPB_AFSR_VALUE_Pos                    0                                                       /*!< PPB AFSR: VALUE Position                */\r
+#define PPB_AFSR_VALUE_Msk                    (0xffffffffUL << PPB_AFSR_VALUE_Pos)                    /*!< PPB AFSR: VALUE Mask                    */\r
+\r
+/* ----------------------------------  PPB_CPACR  --------------------------------- */\r
+#define PPB_CPACR_CP10_Pos                    20                                                      /*!< PPB CPACR: CP10 Position                */\r
+#define PPB_CPACR_CP10_Msk                    (0x03UL << PPB_CPACR_CP10_Pos)                          /*!< PPB CPACR: CP10 Mask                    */\r
+#define PPB_CPACR_CP11_Pos                    22                                                      /*!< PPB CPACR: CP11 Position                */\r
+#define PPB_CPACR_CP11_Msk                    (0x03UL << PPB_CPACR_CP11_Pos)                          /*!< PPB CPACR: CP11 Mask                    */\r
+\r
+/* --------------------------------  PPB_MPU_TYPE  -------------------------------- */\r
+#define PPB_MPU_TYPE_SEPARATE_Pos             0                                                       /*!< PPB MPU_TYPE: SEPARATE Position         */\r
+#define PPB_MPU_TYPE_SEPARATE_Msk             (0x01UL << PPB_MPU_TYPE_SEPARATE_Pos)                   /*!< PPB MPU_TYPE: SEPARATE Mask             */\r
+#define PPB_MPU_TYPE_DREGION_Pos              8                                                       /*!< PPB MPU_TYPE: DREGION Position          */\r
+#define PPB_MPU_TYPE_DREGION_Msk              (0x000000ffUL << PPB_MPU_TYPE_DREGION_Pos)              /*!< PPB MPU_TYPE: DREGION Mask              */\r
+#define PPB_MPU_TYPE_IREGION_Pos              16                                                      /*!< PPB MPU_TYPE: IREGION Position          */\r
+#define PPB_MPU_TYPE_IREGION_Msk              (0x000000ffUL << PPB_MPU_TYPE_IREGION_Pos)              /*!< PPB MPU_TYPE: IREGION Mask              */\r
+\r
+/* --------------------------------  PPB_MPU_CTRL  -------------------------------- */\r
+#define PPB_MPU_CTRL_ENABLE_Pos               0                                                       /*!< PPB MPU_CTRL: ENABLE Position           */\r
+#define PPB_MPU_CTRL_ENABLE_Msk               (0x01UL << PPB_MPU_CTRL_ENABLE_Pos)                     /*!< PPB MPU_CTRL: ENABLE Mask               */\r
+#define PPB_MPU_CTRL_HFNMIENA_Pos             1                                                       /*!< PPB MPU_CTRL: HFNMIENA Position         */\r
+#define PPB_MPU_CTRL_HFNMIENA_Msk             (0x01UL << PPB_MPU_CTRL_HFNMIENA_Pos)                   /*!< PPB MPU_CTRL: HFNMIENA Mask             */\r
+#define PPB_MPU_CTRL_PRIVDEFENA_Pos           2                                                       /*!< PPB MPU_CTRL: PRIVDEFENA Position       */\r
+#define PPB_MPU_CTRL_PRIVDEFENA_Msk           (0x01UL << PPB_MPU_CTRL_PRIVDEFENA_Pos)                 /*!< PPB MPU_CTRL: PRIVDEFENA Mask           */\r
+\r
+/* ---------------------------------  PPB_MPU_RNR  -------------------------------- */\r
+#define PPB_MPU_RNR_REGION_Pos                0                                                       /*!< PPB MPU_RNR: REGION Position            */\r
+#define PPB_MPU_RNR_REGION_Msk                (0x000000ffUL << PPB_MPU_RNR_REGION_Pos)                /*!< PPB MPU_RNR: REGION Mask                */\r
+\r
+/* --------------------------------  PPB_MPU_RBAR  -------------------------------- */\r
+#define PPB_MPU_RBAR_REGION_Pos               0                                                       /*!< PPB MPU_RBAR: REGION Position           */\r
+#define PPB_MPU_RBAR_REGION_Msk               (0x0fUL << PPB_MPU_RBAR_REGION_Pos)                     /*!< PPB MPU_RBAR: REGION Mask               */\r
+#define PPB_MPU_RBAR_VALID_Pos                4                                                       /*!< PPB MPU_RBAR: VALID Position            */\r
+#define PPB_MPU_RBAR_VALID_Msk                (0x01UL << PPB_MPU_RBAR_VALID_Pos)                      /*!< PPB MPU_RBAR: VALID Mask                */\r
+#define PPB_MPU_RBAR_ADDR_Pos                 9                                                       /*!< PPB MPU_RBAR: ADDR Position             */\r
+#define PPB_MPU_RBAR_ADDR_Msk                 (0x007fffffUL << PPB_MPU_RBAR_ADDR_Pos)                 /*!< PPB MPU_RBAR: ADDR Mask                 */\r
+\r
+/* --------------------------------  PPB_MPU_RASR  -------------------------------- */\r
+#define PPB_MPU_RASR_ENABLE_Pos               0                                                       /*!< PPB MPU_RASR: ENABLE Position           */\r
+#define PPB_MPU_RASR_ENABLE_Msk               (0x01UL << PPB_MPU_RASR_ENABLE_Pos)                     /*!< PPB MPU_RASR: ENABLE Mask               */\r
+#define PPB_MPU_RASR_SIZE_Pos                 1                                                       /*!< PPB MPU_RASR: SIZE Position             */\r
+#define PPB_MPU_RASR_SIZE_Msk                 (0x1fUL << PPB_MPU_RASR_SIZE_Pos)                       /*!< PPB MPU_RASR: SIZE Mask                 */\r
+#define PPB_MPU_RASR_SRD_Pos                  8                                                       /*!< PPB MPU_RASR: SRD Position              */\r
+#define PPB_MPU_RASR_SRD_Msk                  (0x000000ffUL << PPB_MPU_RASR_SRD_Pos)                  /*!< PPB MPU_RASR: SRD Mask                  */\r
+#define PPB_MPU_RASR_B_Pos                    16                                                      /*!< PPB MPU_RASR: B Position                */\r
+#define PPB_MPU_RASR_B_Msk                    (0x01UL << PPB_MPU_RASR_B_Pos)                          /*!< PPB MPU_RASR: B Mask                    */\r
+#define PPB_MPU_RASR_C_Pos                    17                                                      /*!< PPB MPU_RASR: C Position                */\r
+#define PPB_MPU_RASR_C_Msk                    (0x01UL << PPB_MPU_RASR_C_Pos)                          /*!< PPB MPU_RASR: C Mask                    */\r
+#define PPB_MPU_RASR_S_Pos                    18                                                      /*!< PPB MPU_RASR: S Position                */\r
+#define PPB_MPU_RASR_S_Msk                    (0x01UL << PPB_MPU_RASR_S_Pos)                          /*!< PPB MPU_RASR: S Mask                    */\r
+#define PPB_MPU_RASR_TEX_Pos                  19                                                      /*!< PPB MPU_RASR: TEX Position              */\r
+#define PPB_MPU_RASR_TEX_Msk                  (0x07UL << PPB_MPU_RASR_TEX_Pos)                        /*!< PPB MPU_RASR: TEX Mask                  */\r
+#define PPB_MPU_RASR_AP_Pos                   24                                                      /*!< PPB MPU_RASR: AP Position               */\r
+#define PPB_MPU_RASR_AP_Msk                   (0x07UL << PPB_MPU_RASR_AP_Pos)                         /*!< PPB MPU_RASR: AP Mask                   */\r
+#define PPB_MPU_RASR_XN_Pos                   28                                                      /*!< PPB MPU_RASR: XN Position               */\r
+#define PPB_MPU_RASR_XN_Msk                   (0x01UL << PPB_MPU_RASR_XN_Pos)                         /*!< PPB MPU_RASR: XN Mask                   */\r
+\r
+/* -------------------------------  PPB_MPU_RBAR_A1  ------------------------------ */\r
+#define PPB_MPU_RBAR_A1_REGION_Pos            0                                                       /*!< PPB MPU_RBAR_A1: REGION Position        */\r
+#define PPB_MPU_RBAR_A1_REGION_Msk            (0x0fUL << PPB_MPU_RBAR_A1_REGION_Pos)                  /*!< PPB MPU_RBAR_A1: REGION Mask            */\r
+#define PPB_MPU_RBAR_A1_VALID_Pos             4                                                       /*!< PPB MPU_RBAR_A1: VALID Position         */\r
+#define PPB_MPU_RBAR_A1_VALID_Msk             (0x01UL << PPB_MPU_RBAR_A1_VALID_Pos)                   /*!< PPB MPU_RBAR_A1: VALID Mask             */\r
+#define PPB_MPU_RBAR_A1_ADDR_Pos              9                                                       /*!< PPB MPU_RBAR_A1: ADDR Position          */\r
+#define PPB_MPU_RBAR_A1_ADDR_Msk              (0x007fffffUL << PPB_MPU_RBAR_A1_ADDR_Pos)              /*!< PPB MPU_RBAR_A1: ADDR Mask              */\r
+\r
+/* -------------------------------  PPB_MPU_RASR_A1  ------------------------------ */\r
+#define PPB_MPU_RASR_A1_ENABLE_Pos            0                                                       /*!< PPB MPU_RASR_A1: ENABLE Position        */\r
+#define PPB_MPU_RASR_A1_ENABLE_Msk            (0x01UL << PPB_MPU_RASR_A1_ENABLE_Pos)                  /*!< PPB MPU_RASR_A1: ENABLE Mask            */\r
+#define PPB_MPU_RASR_A1_SIZE_Pos              1                                                       /*!< PPB MPU_RASR_A1: SIZE Position          */\r
+#define PPB_MPU_RASR_A1_SIZE_Msk              (0x1fUL << PPB_MPU_RASR_A1_SIZE_Pos)                    /*!< PPB MPU_RASR_A1: SIZE Mask              */\r
+#define PPB_MPU_RASR_A1_SRD_Pos               8                                                       /*!< PPB MPU_RASR_A1: SRD Position           */\r
+#define PPB_MPU_RASR_A1_SRD_Msk               (0x000000ffUL << PPB_MPU_RASR_A1_SRD_Pos)               /*!< PPB MPU_RASR_A1: SRD Mask               */\r
+#define PPB_MPU_RASR_A1_B_Pos                 16                                                      /*!< PPB MPU_RASR_A1: B Position             */\r
+#define PPB_MPU_RASR_A1_B_Msk                 (0x01UL << PPB_MPU_RASR_A1_B_Pos)                       /*!< PPB MPU_RASR_A1: B Mask                 */\r
+#define PPB_MPU_RASR_A1_C_Pos                 17                                                      /*!< PPB MPU_RASR_A1: C Position             */\r
+#define PPB_MPU_RASR_A1_C_Msk                 (0x01UL << PPB_MPU_RASR_A1_C_Pos)                       /*!< PPB MPU_RASR_A1: C Mask                 */\r
+#define PPB_MPU_RASR_A1_S_Pos                 18                                                      /*!< PPB MPU_RASR_A1: S Position             */\r
+#define PPB_MPU_RASR_A1_S_Msk                 (0x01UL << PPB_MPU_RASR_A1_S_Pos)                       /*!< PPB MPU_RASR_A1: S Mask                 */\r
+#define PPB_MPU_RASR_A1_TEX_Pos               19                                                      /*!< PPB MPU_RASR_A1: TEX Position           */\r
+#define PPB_MPU_RASR_A1_TEX_Msk               (0x07UL << PPB_MPU_RASR_A1_TEX_Pos)                     /*!< PPB MPU_RASR_A1: TEX Mask               */\r
+#define PPB_MPU_RASR_A1_AP_Pos                24                                                      /*!< PPB MPU_RASR_A1: AP Position            */\r
+#define PPB_MPU_RASR_A1_AP_Msk                (0x07UL << PPB_MPU_RASR_A1_AP_Pos)                      /*!< PPB MPU_RASR_A1: AP Mask                */\r
+#define PPB_MPU_RASR_A1_XN_Pos                28                                                      /*!< PPB MPU_RASR_A1: XN Position            */\r
+#define PPB_MPU_RASR_A1_XN_Msk                (0x01UL << PPB_MPU_RASR_A1_XN_Pos)                      /*!< PPB MPU_RASR_A1: XN Mask                */\r
+\r
+/* -------------------------------  PPB_MPU_RBAR_A2  ------------------------------ */\r
+#define PPB_MPU_RBAR_A2_REGION_Pos            0                                                       /*!< PPB MPU_RBAR_A2: REGION Position        */\r
+#define PPB_MPU_RBAR_A2_REGION_Msk            (0x0fUL << PPB_MPU_RBAR_A2_REGION_Pos)                  /*!< PPB MPU_RBAR_A2: REGION Mask            */\r
+#define PPB_MPU_RBAR_A2_VALID_Pos             4                                                       /*!< PPB MPU_RBAR_A2: VALID Position         */\r
+#define PPB_MPU_RBAR_A2_VALID_Msk             (0x01UL << PPB_MPU_RBAR_A2_VALID_Pos)                   /*!< PPB MPU_RBAR_A2: VALID Mask             */\r
+#define PPB_MPU_RBAR_A2_ADDR_Pos              9                                                       /*!< PPB MPU_RBAR_A2: ADDR Position          */\r
+#define PPB_MPU_RBAR_A2_ADDR_Msk              (0x007fffffUL << PPB_MPU_RBAR_A2_ADDR_Pos)              /*!< PPB MPU_RBAR_A2: ADDR Mask              */\r
+\r
+/* -------------------------------  PPB_MPU_RASR_A2  ------------------------------ */\r
+#define PPB_MPU_RASR_A2_ENABLE_Pos            0                                                       /*!< PPB MPU_RASR_A2: ENABLE Position        */\r
+#define PPB_MPU_RASR_A2_ENABLE_Msk            (0x01UL << PPB_MPU_RASR_A2_ENABLE_Pos)                  /*!< PPB MPU_RASR_A2: ENABLE Mask            */\r
+#define PPB_MPU_RASR_A2_SIZE_Pos              1                                                       /*!< PPB MPU_RASR_A2: SIZE Position          */\r
+#define PPB_MPU_RASR_A2_SIZE_Msk              (0x1fUL << PPB_MPU_RASR_A2_SIZE_Pos)                    /*!< PPB MPU_RASR_A2: SIZE Mask              */\r
+#define PPB_MPU_RASR_A2_SRD_Pos               8                                                       /*!< PPB MPU_RASR_A2: SRD Position           */\r
+#define PPB_MPU_RASR_A2_SRD_Msk               (0x000000ffUL << PPB_MPU_RASR_A2_SRD_Pos)               /*!< PPB MPU_RASR_A2: SRD Mask               */\r
+#define PPB_MPU_RASR_A2_B_Pos                 16                                                      /*!< PPB MPU_RASR_A2: B Position             */\r
+#define PPB_MPU_RASR_A2_B_Msk                 (0x01UL << PPB_MPU_RASR_A2_B_Pos)                       /*!< PPB MPU_RASR_A2: B Mask                 */\r
+#define PPB_MPU_RASR_A2_C_Pos                 17                                                      /*!< PPB MPU_RASR_A2: C Position             */\r
+#define PPB_MPU_RASR_A2_C_Msk                 (0x01UL << PPB_MPU_RASR_A2_C_Pos)                       /*!< PPB MPU_RASR_A2: C Mask                 */\r
+#define PPB_MPU_RASR_A2_S_Pos                 18                                                      /*!< PPB MPU_RASR_A2: S Position             */\r
+#define PPB_MPU_RASR_A2_S_Msk                 (0x01UL << PPB_MPU_RASR_A2_S_Pos)                       /*!< PPB MPU_RASR_A2: S Mask                 */\r
+#define PPB_MPU_RASR_A2_TEX_Pos               19                                                      /*!< PPB MPU_RASR_A2: TEX Position           */\r
+#define PPB_MPU_RASR_A2_TEX_Msk               (0x07UL << PPB_MPU_RASR_A2_TEX_Pos)                     /*!< PPB MPU_RASR_A2: TEX Mask               */\r
+#define PPB_MPU_RASR_A2_AP_Pos                24                                                      /*!< PPB MPU_RASR_A2: AP Position            */\r
+#define PPB_MPU_RASR_A2_AP_Msk                (0x07UL << PPB_MPU_RASR_A2_AP_Pos)                      /*!< PPB MPU_RASR_A2: AP Mask                */\r
+#define PPB_MPU_RASR_A2_XN_Pos                28                                                      /*!< PPB MPU_RASR_A2: XN Position            */\r
+#define PPB_MPU_RASR_A2_XN_Msk                (0x01UL << PPB_MPU_RASR_A2_XN_Pos)                      /*!< PPB MPU_RASR_A2: XN Mask                */\r
+\r
+/* -------------------------------  PPB_MPU_RBAR_A3  ------------------------------ */\r
+#define PPB_MPU_RBAR_A3_REGION_Pos            0                                                       /*!< PPB MPU_RBAR_A3: REGION Position        */\r
+#define PPB_MPU_RBAR_A3_REGION_Msk            (0x0fUL << PPB_MPU_RBAR_A3_REGION_Pos)                  /*!< PPB MPU_RBAR_A3: REGION Mask            */\r
+#define PPB_MPU_RBAR_A3_VALID_Pos             4                                                       /*!< PPB MPU_RBAR_A3: VALID Position         */\r
+#define PPB_MPU_RBAR_A3_VALID_Msk             (0x01UL << PPB_MPU_RBAR_A3_VALID_Pos)                   /*!< PPB MPU_RBAR_A3: VALID Mask             */\r
+#define PPB_MPU_RBAR_A3_ADDR_Pos              9                                                       /*!< PPB MPU_RBAR_A3: ADDR Position          */\r
+#define PPB_MPU_RBAR_A3_ADDR_Msk              (0x007fffffUL << PPB_MPU_RBAR_A3_ADDR_Pos)              /*!< PPB MPU_RBAR_A3: ADDR Mask              */\r
+\r
+/* -------------------------------  PPB_MPU_RASR_A3  ------------------------------ */\r
+#define PPB_MPU_RASR_A3_ENABLE_Pos            0                                                       /*!< PPB MPU_RASR_A3: ENABLE Position        */\r
+#define PPB_MPU_RASR_A3_ENABLE_Msk            (0x01UL << PPB_MPU_RASR_A3_ENABLE_Pos)                  /*!< PPB MPU_RASR_A3: ENABLE Mask            */\r
+#define PPB_MPU_RASR_A3_SIZE_Pos              1                                                       /*!< PPB MPU_RASR_A3: SIZE Position          */\r
+#define PPB_MPU_RASR_A3_SIZE_Msk              (0x1fUL << PPB_MPU_RASR_A3_SIZE_Pos)                    /*!< PPB MPU_RASR_A3: SIZE Mask              */\r
+#define PPB_MPU_RASR_A3_SRD_Pos               8                                                       /*!< PPB MPU_RASR_A3: SRD Position           */\r
+#define PPB_MPU_RASR_A3_SRD_Msk               (0x000000ffUL << PPB_MPU_RASR_A3_SRD_Pos)               /*!< PPB MPU_RASR_A3: SRD Mask               */\r
+#define PPB_MPU_RASR_A3_B_Pos                 16                                                      /*!< PPB MPU_RASR_A3: B Position             */\r
+#define PPB_MPU_RASR_A3_B_Msk                 (0x01UL << PPB_MPU_RASR_A3_B_Pos)                       /*!< PPB MPU_RASR_A3: B Mask                 */\r
+#define PPB_MPU_RASR_A3_C_Pos                 17                                                      /*!< PPB MPU_RASR_A3: C Position             */\r
+#define PPB_MPU_RASR_A3_C_Msk                 (0x01UL << PPB_MPU_RASR_A3_C_Pos)                       /*!< PPB MPU_RASR_A3: C Mask                 */\r
+#define PPB_MPU_RASR_A3_S_Pos                 18                                                      /*!< PPB MPU_RASR_A3: S Position             */\r
+#define PPB_MPU_RASR_A3_S_Msk                 (0x01UL << PPB_MPU_RASR_A3_S_Pos)                       /*!< PPB MPU_RASR_A3: S Mask                 */\r
+#define PPB_MPU_RASR_A3_TEX_Pos               19                                                      /*!< PPB MPU_RASR_A3: TEX Position           */\r
+#define PPB_MPU_RASR_A3_TEX_Msk               (0x07UL << PPB_MPU_RASR_A3_TEX_Pos)                     /*!< PPB MPU_RASR_A3: TEX Mask               */\r
+#define PPB_MPU_RASR_A3_AP_Pos                24                                                      /*!< PPB MPU_RASR_A3: AP Position            */\r
+#define PPB_MPU_RASR_A3_AP_Msk                (0x07UL << PPB_MPU_RASR_A3_AP_Pos)                      /*!< PPB MPU_RASR_A3: AP Mask                */\r
+#define PPB_MPU_RASR_A3_XN_Pos                28                                                      /*!< PPB MPU_RASR_A3: XN Position            */\r
+#define PPB_MPU_RASR_A3_XN_Msk                (0x01UL << PPB_MPU_RASR_A3_XN_Pos)                      /*!< PPB MPU_RASR_A3: XN Mask                */\r
+\r
+/* ----------------------------------  PPB_STIR  ---------------------------------- */\r
+#define PPB_STIR_INTID_Pos                    0                                                       /*!< PPB STIR: INTID Position                */\r
+#define PPB_STIR_INTID_Msk                    (0x000001ffUL << PPB_STIR_INTID_Pos)                    /*!< PPB STIR: INTID Mask                    */\r
+\r
+/* ----------------------------------  PPB_FPCCR  --------------------------------- */\r
+#define PPB_FPCCR_LSPACT_Pos                  0                                                       /*!< PPB FPCCR: LSPACT Position              */\r
+#define PPB_FPCCR_LSPACT_Msk                  (0x01UL << PPB_FPCCR_LSPACT_Pos)                        /*!< PPB FPCCR: LSPACT Mask                  */\r
+#define PPB_FPCCR_USER_Pos                    1                                                       /*!< PPB FPCCR: USER Position                */\r
+#define PPB_FPCCR_USER_Msk                    (0x01UL << PPB_FPCCR_USER_Pos)                          /*!< PPB FPCCR: USER Mask                    */\r
+#define PPB_FPCCR_THREAD_Pos                  3                                                       /*!< PPB FPCCR: THREAD Position              */\r
+#define PPB_FPCCR_THREAD_Msk                  (0x01UL << PPB_FPCCR_THREAD_Pos)                        /*!< PPB FPCCR: THREAD Mask                  */\r
+#define PPB_FPCCR_HFRDY_Pos                   4                                                       /*!< PPB FPCCR: HFRDY Position               */\r
+#define PPB_FPCCR_HFRDY_Msk                   (0x01UL << PPB_FPCCR_HFRDY_Pos)                         /*!< PPB FPCCR: HFRDY Mask                   */\r
+#define PPB_FPCCR_MMRDY_Pos                   5                                                       /*!< PPB FPCCR: MMRDY Position               */\r
+#define PPB_FPCCR_MMRDY_Msk                   (0x01UL << PPB_FPCCR_MMRDY_Pos)                         /*!< PPB FPCCR: MMRDY Mask                   */\r
+#define PPB_FPCCR_BFRDY_Pos                   6                                                       /*!< PPB FPCCR: BFRDY Position               */\r
+#define PPB_FPCCR_BFRDY_Msk                   (0x01UL << PPB_FPCCR_BFRDY_Pos)                         /*!< PPB FPCCR: BFRDY Mask                   */\r
+#define PPB_FPCCR_MONRDY_Pos                  8                                                       /*!< PPB FPCCR: MONRDY Position              */\r
+#define PPB_FPCCR_MONRDY_Msk                  (0x01UL << PPB_FPCCR_MONRDY_Pos)                        /*!< PPB FPCCR: MONRDY Mask                  */\r
+#define PPB_FPCCR_LSPEN_Pos                   30                                                      /*!< PPB FPCCR: LSPEN Position               */\r
+#define PPB_FPCCR_LSPEN_Msk                   (0x01UL << PPB_FPCCR_LSPEN_Pos)                         /*!< PPB FPCCR: LSPEN Mask                   */\r
+#define PPB_FPCCR_ASPEN_Pos                   31                                                      /*!< PPB FPCCR: ASPEN Position               */\r
+#define PPB_FPCCR_ASPEN_Msk                   (0x01UL << PPB_FPCCR_ASPEN_Pos)                         /*!< PPB FPCCR: ASPEN Mask                   */\r
+\r
+/* ----------------------------------  PPB_FPCAR  --------------------------------- */\r
+#define PPB_FPCAR_ADDRESS_Pos                 3                                                       /*!< PPB FPCAR: ADDRESS Position             */\r
+#define PPB_FPCAR_ADDRESS_Msk                 (0x1fffffffUL << PPB_FPCAR_ADDRESS_Pos)                 /*!< PPB FPCAR: ADDRESS Mask                 */\r
+\r
+/* ---------------------------------  PPB_FPDSCR  --------------------------------- */\r
+#define PPB_FPDSCR_RMode_Pos                  22                                                      /*!< PPB FPDSCR: RMode Position              */\r
+#define PPB_FPDSCR_RMode_Msk                  (0x03UL << PPB_FPDSCR_RMode_Pos)                        /*!< PPB FPDSCR: RMode Mask                  */\r
+#define PPB_FPDSCR_FZ_Pos                     24                                                      /*!< PPB FPDSCR: FZ Position                 */\r
+#define PPB_FPDSCR_FZ_Msk                     (0x01UL << PPB_FPDSCR_FZ_Pos)                           /*!< PPB FPDSCR: FZ Mask                     */\r
+#define PPB_FPDSCR_DN_Pos                     25                                                      /*!< PPB FPDSCR: DN Position                 */\r
+#define PPB_FPDSCR_DN_Msk                     (0x01UL << PPB_FPDSCR_DN_Pos)                           /*!< PPB FPDSCR: DN Mask                     */\r
+#define PPB_FPDSCR_AHP_Pos                    26                                                      /*!< PPB FPDSCR: AHP Position                */\r
+#define PPB_FPDSCR_AHP_Msk                    (0x01UL << PPB_FPDSCR_AHP_Pos)                          /*!< PPB FPDSCR: AHP Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'DLR' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  DLR_OVRSTAT  -------------------------------- */\r
+#define DLR_OVRSTAT_LN0_Pos                   0                                                       /*!< DLR OVRSTAT: LN0 Position               */\r
+#define DLR_OVRSTAT_LN0_Msk                   (0x01UL << DLR_OVRSTAT_LN0_Pos)                         /*!< DLR OVRSTAT: LN0 Mask                   */\r
+#define DLR_OVRSTAT_LN1_Pos                   1                                                       /*!< DLR OVRSTAT: LN1 Position               */\r
+#define DLR_OVRSTAT_LN1_Msk                   (0x01UL << DLR_OVRSTAT_LN1_Pos)                         /*!< DLR OVRSTAT: LN1 Mask                   */\r
+#define DLR_OVRSTAT_LN2_Pos                   2                                                       /*!< DLR OVRSTAT: LN2 Position               */\r
+#define DLR_OVRSTAT_LN2_Msk                   (0x01UL << DLR_OVRSTAT_LN2_Pos)                         /*!< DLR OVRSTAT: LN2 Mask                   */\r
+#define DLR_OVRSTAT_LN3_Pos                   3                                                       /*!< DLR OVRSTAT: LN3 Position               */\r
+#define DLR_OVRSTAT_LN3_Msk                   (0x01UL << DLR_OVRSTAT_LN3_Pos)                         /*!< DLR OVRSTAT: LN3 Mask                   */\r
+#define DLR_OVRSTAT_LN4_Pos                   4                                                       /*!< DLR OVRSTAT: LN4 Position               */\r
+#define DLR_OVRSTAT_LN4_Msk                   (0x01UL << DLR_OVRSTAT_LN4_Pos)                         /*!< DLR OVRSTAT: LN4 Mask                   */\r
+#define DLR_OVRSTAT_LN5_Pos                   5                                                       /*!< DLR OVRSTAT: LN5 Position               */\r
+#define DLR_OVRSTAT_LN5_Msk                   (0x01UL << DLR_OVRSTAT_LN5_Pos)                         /*!< DLR OVRSTAT: LN5 Mask                   */\r
+#define DLR_OVRSTAT_LN6_Pos                   6                                                       /*!< DLR OVRSTAT: LN6 Position               */\r
+#define DLR_OVRSTAT_LN6_Msk                   (0x01UL << DLR_OVRSTAT_LN6_Pos)                         /*!< DLR OVRSTAT: LN6 Mask                   */\r
+#define DLR_OVRSTAT_LN7_Pos                   7                                                       /*!< DLR OVRSTAT: LN7 Position               */\r
+#define DLR_OVRSTAT_LN7_Msk                   (0x01UL << DLR_OVRSTAT_LN7_Pos)                         /*!< DLR OVRSTAT: LN7 Mask                   */\r
+\r
+/* ---------------------------------  DLR_OVRCLR  --------------------------------- */\r
+#define DLR_OVRCLR_LN0_Pos                    0                                                       /*!< DLR OVRCLR: LN0 Position                */\r
+#define DLR_OVRCLR_LN0_Msk                    (0x01UL << DLR_OVRCLR_LN0_Pos)                          /*!< DLR OVRCLR: LN0 Mask                    */\r
+#define DLR_OVRCLR_LN1_Pos                    1                                                       /*!< DLR OVRCLR: LN1 Position                */\r
+#define DLR_OVRCLR_LN1_Msk                    (0x01UL << DLR_OVRCLR_LN1_Pos)                          /*!< DLR OVRCLR: LN1 Mask                    */\r
+#define DLR_OVRCLR_LN2_Pos                    2                                                       /*!< DLR OVRCLR: LN2 Position                */\r
+#define DLR_OVRCLR_LN2_Msk                    (0x01UL << DLR_OVRCLR_LN2_Pos)                          /*!< DLR OVRCLR: LN2 Mask                    */\r
+#define DLR_OVRCLR_LN3_Pos                    3                                                       /*!< DLR OVRCLR: LN3 Position                */\r
+#define DLR_OVRCLR_LN3_Msk                    (0x01UL << DLR_OVRCLR_LN3_Pos)                          /*!< DLR OVRCLR: LN3 Mask                    */\r
+#define DLR_OVRCLR_LN4_Pos                    4                                                       /*!< DLR OVRCLR: LN4 Position                */\r
+#define DLR_OVRCLR_LN4_Msk                    (0x01UL << DLR_OVRCLR_LN4_Pos)                          /*!< DLR OVRCLR: LN4 Mask                    */\r
+#define DLR_OVRCLR_LN5_Pos                    5                                                       /*!< DLR OVRCLR: LN5 Position                */\r
+#define DLR_OVRCLR_LN5_Msk                    (0x01UL << DLR_OVRCLR_LN5_Pos)                          /*!< DLR OVRCLR: LN5 Mask                    */\r
+#define DLR_OVRCLR_LN6_Pos                    6                                                       /*!< DLR OVRCLR: LN6 Position                */\r
+#define DLR_OVRCLR_LN6_Msk                    (0x01UL << DLR_OVRCLR_LN6_Pos)                          /*!< DLR OVRCLR: LN6 Mask                    */\r
+#define DLR_OVRCLR_LN7_Pos                    7                                                       /*!< DLR OVRCLR: LN7 Position                */\r
+#define DLR_OVRCLR_LN7_Msk                    (0x01UL << DLR_OVRCLR_LN7_Pos)                          /*!< DLR OVRCLR: LN7 Mask                    */\r
+\r
+/* ---------------------------------  DLR_SRSEL0  --------------------------------- */\r
+#define DLR_SRSEL0_RS0_Pos                    0                                                       /*!< DLR SRSEL0: RS0 Position                */\r
+#define DLR_SRSEL0_RS0_Msk                    (0x0fUL << DLR_SRSEL0_RS0_Pos)                          /*!< DLR SRSEL0: RS0 Mask                    */\r
+#define DLR_SRSEL0_RS1_Pos                    4                                                       /*!< DLR SRSEL0: RS1 Position                */\r
+#define DLR_SRSEL0_RS1_Msk                    (0x0fUL << DLR_SRSEL0_RS1_Pos)                          /*!< DLR SRSEL0: RS1 Mask                    */\r
+#define DLR_SRSEL0_RS2_Pos                    8                                                       /*!< DLR SRSEL0: RS2 Position                */\r
+#define DLR_SRSEL0_RS2_Msk                    (0x0fUL << DLR_SRSEL0_RS2_Pos)                          /*!< DLR SRSEL0: RS2 Mask                    */\r
+#define DLR_SRSEL0_RS3_Pos                    12                                                      /*!< DLR SRSEL0: RS3 Position                */\r
+#define DLR_SRSEL0_RS3_Msk                    (0x0fUL << DLR_SRSEL0_RS3_Pos)                          /*!< DLR SRSEL0: RS3 Mask                    */\r
+#define DLR_SRSEL0_RS4_Pos                    16                                                      /*!< DLR SRSEL0: RS4 Position                */\r
+#define DLR_SRSEL0_RS4_Msk                    (0x0fUL << DLR_SRSEL0_RS4_Pos)                          /*!< DLR SRSEL0: RS4 Mask                    */\r
+#define DLR_SRSEL0_RS5_Pos                    20                                                      /*!< DLR SRSEL0: RS5 Position                */\r
+#define DLR_SRSEL0_RS5_Msk                    (0x0fUL << DLR_SRSEL0_RS5_Pos)                          /*!< DLR SRSEL0: RS5 Mask                    */\r
+#define DLR_SRSEL0_RS6_Pos                    24                                                      /*!< DLR SRSEL0: RS6 Position                */\r
+#define DLR_SRSEL0_RS6_Msk                    (0x0fUL << DLR_SRSEL0_RS6_Pos)                          /*!< DLR SRSEL0: RS6 Mask                    */\r
+#define DLR_SRSEL0_RS7_Pos                    28                                                      /*!< DLR SRSEL0: RS7 Position                */\r
+#define DLR_SRSEL0_RS7_Msk                    (0x0fUL << DLR_SRSEL0_RS7_Pos)                          /*!< DLR SRSEL0: RS7 Mask                    */\r
+\r
+/* ----------------------------------  DLR_LNEN  ---------------------------------- */\r
+#define DLR_LNEN_LN0_Pos                      0                                                       /*!< DLR LNEN: LN0 Position                  */\r
+#define DLR_LNEN_LN0_Msk                      (0x01UL << DLR_LNEN_LN0_Pos)                            /*!< DLR LNEN: LN0 Mask                      */\r
+#define DLR_LNEN_LN1_Pos                      1                                                       /*!< DLR LNEN: LN1 Position                  */\r
+#define DLR_LNEN_LN1_Msk                      (0x01UL << DLR_LNEN_LN1_Pos)                            /*!< DLR LNEN: LN1 Mask                      */\r
+#define DLR_LNEN_LN2_Pos                      2                                                       /*!< DLR LNEN: LN2 Position                  */\r
+#define DLR_LNEN_LN2_Msk                      (0x01UL << DLR_LNEN_LN2_Pos)                            /*!< DLR LNEN: LN2 Mask                      */\r
+#define DLR_LNEN_LN3_Pos                      3                                                       /*!< DLR LNEN: LN3 Position                  */\r
+#define DLR_LNEN_LN3_Msk                      (0x01UL << DLR_LNEN_LN3_Pos)                            /*!< DLR LNEN: LN3 Mask                      */\r
+#define DLR_LNEN_LN4_Pos                      4                                                       /*!< DLR LNEN: LN4 Position                  */\r
+#define DLR_LNEN_LN4_Msk                      (0x01UL << DLR_LNEN_LN4_Pos)                            /*!< DLR LNEN: LN4 Mask                      */\r
+#define DLR_LNEN_LN5_Pos                      5                                                       /*!< DLR LNEN: LN5 Position                  */\r
+#define DLR_LNEN_LN5_Msk                      (0x01UL << DLR_LNEN_LN5_Pos)                            /*!< DLR LNEN: LN5 Mask                      */\r
+#define DLR_LNEN_LN6_Pos                      6                                                       /*!< DLR LNEN: LN6 Position                  */\r
+#define DLR_LNEN_LN6_Msk                      (0x01UL << DLR_LNEN_LN6_Pos)                            /*!< DLR LNEN: LN6 Mask                      */\r
+#define DLR_LNEN_LN7_Pos                      7                                                       /*!< DLR LNEN: LN7 Position                  */\r
+#define DLR_LNEN_LN7_Msk                      (0x01UL << DLR_LNEN_LN7_Pos)                            /*!< DLR LNEN: LN7 Mask                      */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'ERU' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  ERU_EXISEL  --------------------------------- */\r
+#define ERU_EXISEL_EXS0A_Pos                  0                                                       /*!< ERU EXISEL: EXS0A Position              */\r
+#define ERU_EXISEL_EXS0A_Msk                  (0x03UL << ERU_EXISEL_EXS0A_Pos)                        /*!< ERU EXISEL: EXS0A Mask                  */\r
+#define ERU_EXISEL_EXS0B_Pos                  2                                                       /*!< ERU EXISEL: EXS0B Position              */\r
+#define ERU_EXISEL_EXS0B_Msk                  (0x03UL << ERU_EXISEL_EXS0B_Pos)                        /*!< ERU EXISEL: EXS0B Mask                  */\r
+#define ERU_EXISEL_EXS1A_Pos                  4                                                       /*!< ERU EXISEL: EXS1A Position              */\r
+#define ERU_EXISEL_EXS1A_Msk                  (0x03UL << ERU_EXISEL_EXS1A_Pos)                        /*!< ERU EXISEL: EXS1A Mask                  */\r
+#define ERU_EXISEL_EXS1B_Pos                  6                                                       /*!< ERU EXISEL: EXS1B Position              */\r
+#define ERU_EXISEL_EXS1B_Msk                  (0x03UL << ERU_EXISEL_EXS1B_Pos)                        /*!< ERU EXISEL: EXS1B Mask                  */\r
+#define ERU_EXISEL_EXS2A_Pos                  8                                                       /*!< ERU EXISEL: EXS2A Position              */\r
+#define ERU_EXISEL_EXS2A_Msk                  (0x03UL << ERU_EXISEL_EXS2A_Pos)                        /*!< ERU EXISEL: EXS2A Mask                  */\r
+#define ERU_EXISEL_EXS2B_Pos                  10                                                      /*!< ERU EXISEL: EXS2B Position              */\r
+#define ERU_EXISEL_EXS2B_Msk                  (0x03UL << ERU_EXISEL_EXS2B_Pos)                        /*!< ERU EXISEL: EXS2B Mask                  */\r
+#define ERU_EXISEL_EXS3A_Pos                  12                                                      /*!< ERU EXISEL: EXS3A Position              */\r
+#define ERU_EXISEL_EXS3A_Msk                  (0x03UL << ERU_EXISEL_EXS3A_Pos)                        /*!< ERU EXISEL: EXS3A Mask                  */\r
+#define ERU_EXISEL_EXS3B_Pos                  14                                                      /*!< ERU EXISEL: EXS3B Position              */\r
+#define ERU_EXISEL_EXS3B_Msk                  (0x03UL << ERU_EXISEL_EXS3B_Pos)                        /*!< ERU EXISEL: EXS3B Mask                  */\r
+\r
+/* ---------------------------------  ERU_EXICON  --------------------------------- */\r
+#define ERU_EXICON_PE_Pos                     0                                                       /*!< ERU EXICON: PE Position                 */\r
+#define ERU_EXICON_PE_Msk                     (0x01UL << ERU_EXICON_PE_Pos)                           /*!< ERU EXICON: PE Mask                     */\r
+#define ERU_EXICON_LD_Pos                     1                                                       /*!< ERU EXICON: LD Position                 */\r
+#define ERU_EXICON_LD_Msk                     (0x01UL << ERU_EXICON_LD_Pos)                           /*!< ERU EXICON: LD Mask                     */\r
+#define ERU_EXICON_RE_Pos                     2                                                       /*!< ERU EXICON: RE Position                 */\r
+#define ERU_EXICON_RE_Msk                     (0x01UL << ERU_EXICON_RE_Pos)                           /*!< ERU EXICON: RE Mask                     */\r
+#define ERU_EXICON_FE_Pos                     3                                                       /*!< ERU EXICON: FE Position                 */\r
+#define ERU_EXICON_FE_Msk                     (0x01UL << ERU_EXICON_FE_Pos)                           /*!< ERU EXICON: FE Mask                     */\r
+#define ERU_EXICON_OCS_Pos                    4                                                       /*!< ERU EXICON: OCS Position                */\r
+#define ERU_EXICON_OCS_Msk                    (0x07UL << ERU_EXICON_OCS_Pos)                          /*!< ERU EXICON: OCS Mask                    */\r
+#define ERU_EXICON_FL_Pos                     7                                                       /*!< ERU EXICON: FL Position                 */\r
+#define ERU_EXICON_FL_Msk                     (0x01UL << ERU_EXICON_FL_Pos)                           /*!< ERU EXICON: FL Mask                     */\r
+#define ERU_EXICON_SS_Pos                     8                                                       /*!< ERU EXICON: SS Position                 */\r
+#define ERU_EXICON_SS_Msk                     (0x03UL << ERU_EXICON_SS_Pos)                           /*!< ERU EXICON: SS Mask                     */\r
+#define ERU_EXICON_NA_Pos                     10                                                      /*!< ERU EXICON: NA Position                 */\r
+#define ERU_EXICON_NA_Msk                     (0x01UL << ERU_EXICON_NA_Pos)                           /*!< ERU EXICON: NA Mask                     */\r
+#define ERU_EXICON_NB_Pos                     11                                                      /*!< ERU EXICON: NB Position                 */\r
+#define ERU_EXICON_NB_Msk                     (0x01UL << ERU_EXICON_NB_Pos)                           /*!< ERU EXICON: NB Mask                     */\r
+\r
+/* ---------------------------------  ERU_EXOCON  --------------------------------- */\r
+#define ERU_EXOCON_ISS_Pos                    0                                                       /*!< ERU EXOCON: ISS Position                */\r
+#define ERU_EXOCON_ISS_Msk                    (0x03UL << ERU_EXOCON_ISS_Pos)                          /*!< ERU EXOCON: ISS Mask                    */\r
+#define ERU_EXOCON_GEEN_Pos                   2                                                       /*!< ERU EXOCON: GEEN Position               */\r
+#define ERU_EXOCON_GEEN_Msk                   (0x01UL << ERU_EXOCON_GEEN_Pos)                         /*!< ERU EXOCON: GEEN Mask                   */\r
+#define ERU_EXOCON_PDR_Pos                    3                                                       /*!< ERU EXOCON: PDR Position                */\r
+#define ERU_EXOCON_PDR_Msk                    (0x01UL << ERU_EXOCON_PDR_Pos)                          /*!< ERU EXOCON: PDR Mask                    */\r
+#define ERU_EXOCON_GP_Pos                     4                                                       /*!< ERU EXOCON: GP Position                 */\r
+#define ERU_EXOCON_GP_Msk                     (0x03UL << ERU_EXOCON_GP_Pos)                           /*!< ERU EXOCON: GP Mask                     */\r
+#define ERU_EXOCON_IPEN0_Pos                  12                                                      /*!< ERU EXOCON: IPEN0 Position              */\r
+#define ERU_EXOCON_IPEN0_Msk                  (0x01UL << ERU_EXOCON_IPEN0_Pos)                        /*!< ERU EXOCON: IPEN0 Mask                  */\r
+#define ERU_EXOCON_IPEN1_Pos                  13                                                      /*!< ERU EXOCON: IPEN1 Position              */\r
+#define ERU_EXOCON_IPEN1_Msk                  (0x01UL << ERU_EXOCON_IPEN1_Pos)                        /*!< ERU EXOCON: IPEN1 Mask                  */\r
+#define ERU_EXOCON_IPEN2_Pos                  14                                                      /*!< ERU EXOCON: IPEN2 Position              */\r
+#define ERU_EXOCON_IPEN2_Msk                  (0x01UL << ERU_EXOCON_IPEN2_Pos)                        /*!< ERU EXOCON: IPEN2 Mask                  */\r
+#define ERU_EXOCON_IPEN3_Pos                  15                                                      /*!< ERU EXOCON: IPEN3 Position              */\r
+#define ERU_EXOCON_IPEN3_Msk                  (0x01UL << ERU_EXOCON_IPEN3_Pos)                        /*!< ERU EXOCON: IPEN3 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'GPDMA0' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  GPDMA0_RAWTFR  ------------------------------- */\r
+#define GPDMA0_RAWTFR_CH0_Pos                 0                                                       /*!< GPDMA0 RAWTFR: CH0 Position             */\r
+#define GPDMA0_RAWTFR_CH0_Msk                 (0x01UL << GPDMA0_RAWTFR_CH0_Pos)                       /*!< GPDMA0 RAWTFR: CH0 Mask                 */\r
+#define GPDMA0_RAWTFR_CH1_Pos                 1                                                       /*!< GPDMA0 RAWTFR: CH1 Position             */\r
+#define GPDMA0_RAWTFR_CH1_Msk                 (0x01UL << GPDMA0_RAWTFR_CH1_Pos)                       /*!< GPDMA0 RAWTFR: CH1 Mask                 */\r
+#define GPDMA0_RAWTFR_CH2_Pos                 2                                                       /*!< GPDMA0 RAWTFR: CH2 Position             */\r
+#define GPDMA0_RAWTFR_CH2_Msk                 (0x01UL << GPDMA0_RAWTFR_CH2_Pos)                       /*!< GPDMA0 RAWTFR: CH2 Mask                 */\r
+#define GPDMA0_RAWTFR_CH3_Pos                 3                                                       /*!< GPDMA0 RAWTFR: CH3 Position             */\r
+#define GPDMA0_RAWTFR_CH3_Msk                 (0x01UL << GPDMA0_RAWTFR_CH3_Pos)                       /*!< GPDMA0 RAWTFR: CH3 Mask                 */\r
+#define GPDMA0_RAWTFR_CH4_Pos                 4                                                       /*!< GPDMA0 RAWTFR: CH4 Position             */\r
+#define GPDMA0_RAWTFR_CH4_Msk                 (0x01UL << GPDMA0_RAWTFR_CH4_Pos)                       /*!< GPDMA0 RAWTFR: CH4 Mask                 */\r
+#define GPDMA0_RAWTFR_CH5_Pos                 5                                                       /*!< GPDMA0 RAWTFR: CH5 Position             */\r
+#define GPDMA0_RAWTFR_CH5_Msk                 (0x01UL << GPDMA0_RAWTFR_CH5_Pos)                       /*!< GPDMA0 RAWTFR: CH5 Mask                 */\r
+#define GPDMA0_RAWTFR_CH6_Pos                 6                                                       /*!< GPDMA0 RAWTFR: CH6 Position             */\r
+#define GPDMA0_RAWTFR_CH6_Msk                 (0x01UL << GPDMA0_RAWTFR_CH6_Pos)                       /*!< GPDMA0 RAWTFR: CH6 Mask                 */\r
+#define GPDMA0_RAWTFR_CH7_Pos                 7                                                       /*!< GPDMA0 RAWTFR: CH7 Position             */\r
+#define GPDMA0_RAWTFR_CH7_Msk                 (0x01UL << GPDMA0_RAWTFR_CH7_Pos)                       /*!< GPDMA0 RAWTFR: CH7 Mask                 */\r
+\r
+/* -------------------------------  GPDMA0_RAWBLOCK  ------------------------------ */\r
+#define GPDMA0_RAWBLOCK_CH0_Pos               0                                                       /*!< GPDMA0 RAWBLOCK: CH0 Position           */\r
+#define GPDMA0_RAWBLOCK_CH0_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH0_Pos)                     /*!< GPDMA0 RAWBLOCK: CH0 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH1_Pos               1                                                       /*!< GPDMA0 RAWBLOCK: CH1 Position           */\r
+#define GPDMA0_RAWBLOCK_CH1_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH1_Pos)                     /*!< GPDMA0 RAWBLOCK: CH1 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH2_Pos               2                                                       /*!< GPDMA0 RAWBLOCK: CH2 Position           */\r
+#define GPDMA0_RAWBLOCK_CH2_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH2_Pos)                     /*!< GPDMA0 RAWBLOCK: CH2 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH3_Pos               3                                                       /*!< GPDMA0 RAWBLOCK: CH3 Position           */\r
+#define GPDMA0_RAWBLOCK_CH3_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH3_Pos)                     /*!< GPDMA0 RAWBLOCK: CH3 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH4_Pos               4                                                       /*!< GPDMA0 RAWBLOCK: CH4 Position           */\r
+#define GPDMA0_RAWBLOCK_CH4_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH4_Pos)                     /*!< GPDMA0 RAWBLOCK: CH4 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH5_Pos               5                                                       /*!< GPDMA0 RAWBLOCK: CH5 Position           */\r
+#define GPDMA0_RAWBLOCK_CH5_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH5_Pos)                     /*!< GPDMA0 RAWBLOCK: CH5 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH6_Pos               6                                                       /*!< GPDMA0 RAWBLOCK: CH6 Position           */\r
+#define GPDMA0_RAWBLOCK_CH6_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH6_Pos)                     /*!< GPDMA0 RAWBLOCK: CH6 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH7_Pos               7                                                       /*!< GPDMA0 RAWBLOCK: CH7 Position           */\r
+#define GPDMA0_RAWBLOCK_CH7_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH7_Pos)                     /*!< GPDMA0 RAWBLOCK: CH7 Mask               */\r
+\r
+/* ------------------------------  GPDMA0_RAWSRCTRAN  ----------------------------- */\r
+#define GPDMA0_RAWSRCTRAN_CH0_Pos             0                                                       /*!< GPDMA0 RAWSRCTRAN: CH0 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH0_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH0_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH0 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH1_Pos             1                                                       /*!< GPDMA0 RAWSRCTRAN: CH1 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH1_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH1_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH1 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH2_Pos             2                                                       /*!< GPDMA0 RAWSRCTRAN: CH2 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH2_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH2_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH2 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH3_Pos             3                                                       /*!< GPDMA0 RAWSRCTRAN: CH3 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH3_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH3_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH3 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH4_Pos             4                                                       /*!< GPDMA0 RAWSRCTRAN: CH4 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH4_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH4_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH4 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH5_Pos             5                                                       /*!< GPDMA0 RAWSRCTRAN: CH5 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH5_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH5_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH5 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH6_Pos             6                                                       /*!< GPDMA0 RAWSRCTRAN: CH6 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH6_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH6_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH6 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH7_Pos             7                                                       /*!< GPDMA0 RAWSRCTRAN: CH7 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH7_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH7_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH7 Mask             */\r
+\r
+/* ------------------------------  GPDMA0_RAWDSTTRAN  ----------------------------- */\r
+#define GPDMA0_RAWDSTTRAN_CH0_Pos             0                                                       /*!< GPDMA0 RAWDSTTRAN: CH0 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH0_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH0_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH0 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH1_Pos             1                                                       /*!< GPDMA0 RAWDSTTRAN: CH1 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH1_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH1_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH1 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH2_Pos             2                                                       /*!< GPDMA0 RAWDSTTRAN: CH2 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH2_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH2_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH2 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH3_Pos             3                                                       /*!< GPDMA0 RAWDSTTRAN: CH3 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH3_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH3_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH3 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH4_Pos             4                                                       /*!< GPDMA0 RAWDSTTRAN: CH4 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH4_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH4_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH4 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH5_Pos             5                                                       /*!< GPDMA0 RAWDSTTRAN: CH5 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH5_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH5_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH5 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH6_Pos             6                                                       /*!< GPDMA0 RAWDSTTRAN: CH6 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH6_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH6_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH6 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH7_Pos             7                                                       /*!< GPDMA0 RAWDSTTRAN: CH7 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH7_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH7_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH7 Mask             */\r
+\r
+/* --------------------------------  GPDMA0_RAWERR  ------------------------------- */\r
+#define GPDMA0_RAWERR_CH0_Pos                 0                                                       /*!< GPDMA0 RAWERR: CH0 Position             */\r
+#define GPDMA0_RAWERR_CH0_Msk                 (0x01UL << GPDMA0_RAWERR_CH0_Pos)                       /*!< GPDMA0 RAWERR: CH0 Mask                 */\r
+#define GPDMA0_RAWERR_CH1_Pos                 1                                                       /*!< GPDMA0 RAWERR: CH1 Position             */\r
+#define GPDMA0_RAWERR_CH1_Msk                 (0x01UL << GPDMA0_RAWERR_CH1_Pos)                       /*!< GPDMA0 RAWERR: CH1 Mask                 */\r
+#define GPDMA0_RAWERR_CH2_Pos                 2                                                       /*!< GPDMA0 RAWERR: CH2 Position             */\r
+#define GPDMA0_RAWERR_CH2_Msk                 (0x01UL << GPDMA0_RAWERR_CH2_Pos)                       /*!< GPDMA0 RAWERR: CH2 Mask                 */\r
+#define GPDMA0_RAWERR_CH3_Pos                 3                                                       /*!< GPDMA0 RAWERR: CH3 Position             */\r
+#define GPDMA0_RAWERR_CH3_Msk                 (0x01UL << GPDMA0_RAWERR_CH3_Pos)                       /*!< GPDMA0 RAWERR: CH3 Mask                 */\r
+#define GPDMA0_RAWERR_CH4_Pos                 4                                                       /*!< GPDMA0 RAWERR: CH4 Position             */\r
+#define GPDMA0_RAWERR_CH4_Msk                 (0x01UL << GPDMA0_RAWERR_CH4_Pos)                       /*!< GPDMA0 RAWERR: CH4 Mask                 */\r
+#define GPDMA0_RAWERR_CH5_Pos                 5                                                       /*!< GPDMA0 RAWERR: CH5 Position             */\r
+#define GPDMA0_RAWERR_CH5_Msk                 (0x01UL << GPDMA0_RAWERR_CH5_Pos)                       /*!< GPDMA0 RAWERR: CH5 Mask                 */\r
+#define GPDMA0_RAWERR_CH6_Pos                 6                                                       /*!< GPDMA0 RAWERR: CH6 Position             */\r
+#define GPDMA0_RAWERR_CH6_Msk                 (0x01UL << GPDMA0_RAWERR_CH6_Pos)                       /*!< GPDMA0 RAWERR: CH6 Mask                 */\r
+#define GPDMA0_RAWERR_CH7_Pos                 7                                                       /*!< GPDMA0 RAWERR: CH7 Position             */\r
+#define GPDMA0_RAWERR_CH7_Msk                 (0x01UL << GPDMA0_RAWERR_CH7_Pos)                       /*!< GPDMA0 RAWERR: CH7 Mask                 */\r
+\r
+/* ------------------------------  GPDMA0_STATUSTFR  ------------------------------ */\r
+#define GPDMA0_STATUSTFR_CH0_Pos              0                                                       /*!< GPDMA0 STATUSTFR: CH0 Position          */\r
+#define GPDMA0_STATUSTFR_CH0_Msk              (0x01UL << GPDMA0_STATUSTFR_CH0_Pos)                    /*!< GPDMA0 STATUSTFR: CH0 Mask              */\r
+#define GPDMA0_STATUSTFR_CH1_Pos              1                                                       /*!< GPDMA0 STATUSTFR: CH1 Position          */\r
+#define GPDMA0_STATUSTFR_CH1_Msk              (0x01UL << GPDMA0_STATUSTFR_CH1_Pos)                    /*!< GPDMA0 STATUSTFR: CH1 Mask              */\r
+#define GPDMA0_STATUSTFR_CH2_Pos              2                                                       /*!< GPDMA0 STATUSTFR: CH2 Position          */\r
+#define GPDMA0_STATUSTFR_CH2_Msk              (0x01UL << GPDMA0_STATUSTFR_CH2_Pos)                    /*!< GPDMA0 STATUSTFR: CH2 Mask              */\r
+#define GPDMA0_STATUSTFR_CH3_Pos              3                                                       /*!< GPDMA0 STATUSTFR: CH3 Position          */\r
+#define GPDMA0_STATUSTFR_CH3_Msk              (0x01UL << GPDMA0_STATUSTFR_CH3_Pos)                    /*!< GPDMA0 STATUSTFR: CH3 Mask              */\r
+#define GPDMA0_STATUSTFR_CH4_Pos              4                                                       /*!< GPDMA0 STATUSTFR: CH4 Position          */\r
+#define GPDMA0_STATUSTFR_CH4_Msk              (0x01UL << GPDMA0_STATUSTFR_CH4_Pos)                    /*!< GPDMA0 STATUSTFR: CH4 Mask              */\r
+#define GPDMA0_STATUSTFR_CH5_Pos              5                                                       /*!< GPDMA0 STATUSTFR: CH5 Position          */\r
+#define GPDMA0_STATUSTFR_CH5_Msk              (0x01UL << GPDMA0_STATUSTFR_CH5_Pos)                    /*!< GPDMA0 STATUSTFR: CH5 Mask              */\r
+#define GPDMA0_STATUSTFR_CH6_Pos              6                                                       /*!< GPDMA0 STATUSTFR: CH6 Position          */\r
+#define GPDMA0_STATUSTFR_CH6_Msk              (0x01UL << GPDMA0_STATUSTFR_CH6_Pos)                    /*!< GPDMA0 STATUSTFR: CH6 Mask              */\r
+#define GPDMA0_STATUSTFR_CH7_Pos              7                                                       /*!< GPDMA0 STATUSTFR: CH7 Position          */\r
+#define GPDMA0_STATUSTFR_CH7_Msk              (0x01UL << GPDMA0_STATUSTFR_CH7_Pos)                    /*!< GPDMA0 STATUSTFR: CH7 Mask              */\r
+\r
+/* -----------------------------  GPDMA0_STATUSBLOCK  ----------------------------- */\r
+#define GPDMA0_STATUSBLOCK_CH0_Pos            0                                                       /*!< GPDMA0 STATUSBLOCK: CH0 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH0_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH0_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH0 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH1_Pos            1                                                       /*!< GPDMA0 STATUSBLOCK: CH1 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH1_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH1_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH1 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH2_Pos            2                                                       /*!< GPDMA0 STATUSBLOCK: CH2 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH2_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH2_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH2 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH3_Pos            3                                                       /*!< GPDMA0 STATUSBLOCK: CH3 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH3_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH3_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH3 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH4_Pos            4                                                       /*!< GPDMA0 STATUSBLOCK: CH4 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH4_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH4_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH4 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH5_Pos            5                                                       /*!< GPDMA0 STATUSBLOCK: CH5 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH5_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH5_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH5 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH6_Pos            6                                                       /*!< GPDMA0 STATUSBLOCK: CH6 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH6_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH6_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH6 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH7_Pos            7                                                       /*!< GPDMA0 STATUSBLOCK: CH7 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH7_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH7_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH7 Mask            */\r
+\r
+/* ----------------------------  GPDMA0_STATUSSRCTRAN  ---------------------------- */\r
+#define GPDMA0_STATUSSRCTRAN_CH0_Pos          0                                                       /*!< GPDMA0 STATUSSRCTRAN: CH0 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH0_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH0_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH0 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH1_Pos          1                                                       /*!< GPDMA0 STATUSSRCTRAN: CH1 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH1_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH1_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH1 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH2_Pos          2                                                       /*!< GPDMA0 STATUSSRCTRAN: CH2 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH2_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH2_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH2 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH3_Pos          3                                                       /*!< GPDMA0 STATUSSRCTRAN: CH3 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH3_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH3_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH3 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH4_Pos          4                                                       /*!< GPDMA0 STATUSSRCTRAN: CH4 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH4_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH4_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH4 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH5_Pos          5                                                       /*!< GPDMA0 STATUSSRCTRAN: CH5 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH5_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH5_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH5 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH6_Pos          6                                                       /*!< GPDMA0 STATUSSRCTRAN: CH6 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH6_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH6_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH6 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH7_Pos          7                                                       /*!< GPDMA0 STATUSSRCTRAN: CH7 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH7_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH7_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH7 Mask          */\r
+\r
+/* ----------------------------  GPDMA0_STATUSDSTTRAN  ---------------------------- */\r
+#define GPDMA0_STATUSDSTTRAN_CH0_Pos          0                                                       /*!< GPDMA0 STATUSDSTTRAN: CH0 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH0_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH0_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH0 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH1_Pos          1                                                       /*!< GPDMA0 STATUSDSTTRAN: CH1 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH1_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH1_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH1 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH2_Pos          2                                                       /*!< GPDMA0 STATUSDSTTRAN: CH2 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH2_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH2_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH2 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH3_Pos          3                                                       /*!< GPDMA0 STATUSDSTTRAN: CH3 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH3_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH3_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH3 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH4_Pos          4                                                       /*!< GPDMA0 STATUSDSTTRAN: CH4 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH4_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH4_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH4 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH5_Pos          5                                                       /*!< GPDMA0 STATUSDSTTRAN: CH5 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH5_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH5_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH5 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH6_Pos          6                                                       /*!< GPDMA0 STATUSDSTTRAN: CH6 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH6_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH6_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH6 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH7_Pos          7                                                       /*!< GPDMA0 STATUSDSTTRAN: CH7 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH7_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH7_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH7 Mask          */\r
+\r
+/* ------------------------------  GPDMA0_STATUSERR  ------------------------------ */\r
+#define GPDMA0_STATUSERR_CH0_Pos              0                                                       /*!< GPDMA0 STATUSERR: CH0 Position          */\r
+#define GPDMA0_STATUSERR_CH0_Msk              (0x01UL << GPDMA0_STATUSERR_CH0_Pos)                    /*!< GPDMA0 STATUSERR: CH0 Mask              */\r
+#define GPDMA0_STATUSERR_CH1_Pos              1                                                       /*!< GPDMA0 STATUSERR: CH1 Position          */\r
+#define GPDMA0_STATUSERR_CH1_Msk              (0x01UL << GPDMA0_STATUSERR_CH1_Pos)                    /*!< GPDMA0 STATUSERR: CH1 Mask              */\r
+#define GPDMA0_STATUSERR_CH2_Pos              2                                                       /*!< GPDMA0 STATUSERR: CH2 Position          */\r
+#define GPDMA0_STATUSERR_CH2_Msk              (0x01UL << GPDMA0_STATUSERR_CH2_Pos)                    /*!< GPDMA0 STATUSERR: CH2 Mask              */\r
+#define GPDMA0_STATUSERR_CH3_Pos              3                                                       /*!< GPDMA0 STATUSERR: CH3 Position          */\r
+#define GPDMA0_STATUSERR_CH3_Msk              (0x01UL << GPDMA0_STATUSERR_CH3_Pos)                    /*!< GPDMA0 STATUSERR: CH3 Mask              */\r
+#define GPDMA0_STATUSERR_CH4_Pos              4                                                       /*!< GPDMA0 STATUSERR: CH4 Position          */\r
+#define GPDMA0_STATUSERR_CH4_Msk              (0x01UL << GPDMA0_STATUSERR_CH4_Pos)                    /*!< GPDMA0 STATUSERR: CH4 Mask              */\r
+#define GPDMA0_STATUSERR_CH5_Pos              5                                                       /*!< GPDMA0 STATUSERR: CH5 Position          */\r
+#define GPDMA0_STATUSERR_CH5_Msk              (0x01UL << GPDMA0_STATUSERR_CH5_Pos)                    /*!< GPDMA0 STATUSERR: CH5 Mask              */\r
+#define GPDMA0_STATUSERR_CH6_Pos              6                                                       /*!< GPDMA0 STATUSERR: CH6 Position          */\r
+#define GPDMA0_STATUSERR_CH6_Msk              (0x01UL << GPDMA0_STATUSERR_CH6_Pos)                    /*!< GPDMA0 STATUSERR: CH6 Mask              */\r
+#define GPDMA0_STATUSERR_CH7_Pos              7                                                       /*!< GPDMA0 STATUSERR: CH7 Position          */\r
+#define GPDMA0_STATUSERR_CH7_Msk              (0x01UL << GPDMA0_STATUSERR_CH7_Pos)                    /*!< GPDMA0 STATUSERR: CH7 Mask              */\r
+\r
+/* -------------------------------  GPDMA0_MASKTFR  ------------------------------- */\r
+#define GPDMA0_MASKTFR_CH0_Pos                0                                                       /*!< GPDMA0 MASKTFR: CH0 Position            */\r
+#define GPDMA0_MASKTFR_CH0_Msk                (0x01UL << GPDMA0_MASKTFR_CH0_Pos)                      /*!< GPDMA0 MASKTFR: CH0 Mask                */\r
+#define GPDMA0_MASKTFR_CH1_Pos                1                                                       /*!< GPDMA0 MASKTFR: CH1 Position            */\r
+#define GPDMA0_MASKTFR_CH1_Msk                (0x01UL << GPDMA0_MASKTFR_CH1_Pos)                      /*!< GPDMA0 MASKTFR: CH1 Mask                */\r
+#define GPDMA0_MASKTFR_CH2_Pos                2                                                       /*!< GPDMA0 MASKTFR: CH2 Position            */\r
+#define GPDMA0_MASKTFR_CH2_Msk                (0x01UL << GPDMA0_MASKTFR_CH2_Pos)                      /*!< GPDMA0 MASKTFR: CH2 Mask                */\r
+#define GPDMA0_MASKTFR_CH3_Pos                3                                                       /*!< GPDMA0 MASKTFR: CH3 Position            */\r
+#define GPDMA0_MASKTFR_CH3_Msk                (0x01UL << GPDMA0_MASKTFR_CH3_Pos)                      /*!< GPDMA0 MASKTFR: CH3 Mask                */\r
+#define GPDMA0_MASKTFR_CH4_Pos                4                                                       /*!< GPDMA0 MASKTFR: CH4 Position            */\r
+#define GPDMA0_MASKTFR_CH4_Msk                (0x01UL << GPDMA0_MASKTFR_CH4_Pos)                      /*!< GPDMA0 MASKTFR: CH4 Mask                */\r
+#define GPDMA0_MASKTFR_CH5_Pos                5                                                       /*!< GPDMA0 MASKTFR: CH5 Position            */\r
+#define GPDMA0_MASKTFR_CH5_Msk                (0x01UL << GPDMA0_MASKTFR_CH5_Pos)                      /*!< GPDMA0 MASKTFR: CH5 Mask                */\r
+#define GPDMA0_MASKTFR_CH6_Pos                6                                                       /*!< GPDMA0 MASKTFR: CH6 Position            */\r
+#define GPDMA0_MASKTFR_CH6_Msk                (0x01UL << GPDMA0_MASKTFR_CH6_Pos)                      /*!< GPDMA0 MASKTFR: CH6 Mask                */\r
+#define GPDMA0_MASKTFR_CH7_Pos                7                                                       /*!< GPDMA0 MASKTFR: CH7 Position            */\r
+#define GPDMA0_MASKTFR_CH7_Msk                (0x01UL << GPDMA0_MASKTFR_CH7_Pos)                      /*!< GPDMA0 MASKTFR: CH7 Mask                */\r
+#define GPDMA0_MASKTFR_WE_CH0_Pos             8                                                       /*!< GPDMA0 MASKTFR: WE_CH0 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH0_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH0_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH0 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH1_Pos             9                                                       /*!< GPDMA0 MASKTFR: WE_CH1 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH1_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH1_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH1 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH2_Pos             10                                                      /*!< GPDMA0 MASKTFR: WE_CH2 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH2_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH2_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH2 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH3_Pos             11                                                      /*!< GPDMA0 MASKTFR: WE_CH3 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH3_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH3_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH3 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH4_Pos             12                                                      /*!< GPDMA0 MASKTFR: WE_CH4 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH4_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH4_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH4 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH5_Pos             13                                                      /*!< GPDMA0 MASKTFR: WE_CH5 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH5_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH5_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH5 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH6_Pos             14                                                      /*!< GPDMA0 MASKTFR: WE_CH6 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH6_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH6_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH6 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH7_Pos             15                                                      /*!< GPDMA0 MASKTFR: WE_CH7 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH7_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH7_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH7 Mask             */\r
+\r
+/* ------------------------------  GPDMA0_MASKBLOCK  ------------------------------ */\r
+#define GPDMA0_MASKBLOCK_CH0_Pos              0                                                       /*!< GPDMA0 MASKBLOCK: CH0 Position          */\r
+#define GPDMA0_MASKBLOCK_CH0_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH0_Pos)                    /*!< GPDMA0 MASKBLOCK: CH0 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH1_Pos              1                                                       /*!< GPDMA0 MASKBLOCK: CH1 Position          */\r
+#define GPDMA0_MASKBLOCK_CH1_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH1_Pos)                    /*!< GPDMA0 MASKBLOCK: CH1 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH2_Pos              2                                                       /*!< GPDMA0 MASKBLOCK: CH2 Position          */\r
+#define GPDMA0_MASKBLOCK_CH2_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH2_Pos)                    /*!< GPDMA0 MASKBLOCK: CH2 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH3_Pos              3                                                       /*!< GPDMA0 MASKBLOCK: CH3 Position          */\r
+#define GPDMA0_MASKBLOCK_CH3_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH3_Pos)                    /*!< GPDMA0 MASKBLOCK: CH3 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH4_Pos              4                                                       /*!< GPDMA0 MASKBLOCK: CH4 Position          */\r
+#define GPDMA0_MASKBLOCK_CH4_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH4_Pos)                    /*!< GPDMA0 MASKBLOCK: CH4 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH5_Pos              5                                                       /*!< GPDMA0 MASKBLOCK: CH5 Position          */\r
+#define GPDMA0_MASKBLOCK_CH5_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH5_Pos)                    /*!< GPDMA0 MASKBLOCK: CH5 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH6_Pos              6                                                       /*!< GPDMA0 MASKBLOCK: CH6 Position          */\r
+#define GPDMA0_MASKBLOCK_CH6_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH6_Pos)                    /*!< GPDMA0 MASKBLOCK: CH6 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH7_Pos              7                                                       /*!< GPDMA0 MASKBLOCK: CH7 Position          */\r
+#define GPDMA0_MASKBLOCK_CH7_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH7_Pos)                    /*!< GPDMA0 MASKBLOCK: CH7 Mask              */\r
+#define GPDMA0_MASKBLOCK_WE_CH0_Pos           8                                                       /*!< GPDMA0 MASKBLOCK: WE_CH0 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH0_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH0_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH0 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH1_Pos           9                                                       /*!< GPDMA0 MASKBLOCK: WE_CH1 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH1_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH1_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH1 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH2_Pos           10                                                      /*!< GPDMA0 MASKBLOCK: WE_CH2 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH2_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH2_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH2 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH3_Pos           11                                                      /*!< GPDMA0 MASKBLOCK: WE_CH3 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH3_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH3_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH3 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH4_Pos           12                                                      /*!< GPDMA0 MASKBLOCK: WE_CH4 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH4_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH4_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH4 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH5_Pos           13                                                      /*!< GPDMA0 MASKBLOCK: WE_CH5 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH5_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH5_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH5 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH6_Pos           14                                                      /*!< GPDMA0 MASKBLOCK: WE_CH6 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH6_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH6_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH6 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH7_Pos           15                                                      /*!< GPDMA0 MASKBLOCK: WE_CH7 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH7_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH7_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH7 Mask           */\r
+\r
+/* -----------------------------  GPDMA0_MASKSRCTRAN  ----------------------------- */\r
+#define GPDMA0_MASKSRCTRAN_CH0_Pos            0                                                       /*!< GPDMA0 MASKSRCTRAN: CH0 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH0_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH0_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH0 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH1_Pos            1                                                       /*!< GPDMA0 MASKSRCTRAN: CH1 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH1_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH1_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH1 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH2_Pos            2                                                       /*!< GPDMA0 MASKSRCTRAN: CH2 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH2_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH2_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH2 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH3_Pos            3                                                       /*!< GPDMA0 MASKSRCTRAN: CH3 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH3_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH3_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH3 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH4_Pos            4                                                       /*!< GPDMA0 MASKSRCTRAN: CH4 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH4_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH4_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH4 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH5_Pos            5                                                       /*!< GPDMA0 MASKSRCTRAN: CH5 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH5_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH5_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH5 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH6_Pos            6                                                       /*!< GPDMA0 MASKSRCTRAN: CH6 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH6_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH6_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH6 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH7_Pos            7                                                       /*!< GPDMA0 MASKSRCTRAN: CH7 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH7_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH7_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH7 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH0_Pos         8                                                       /*!< GPDMA0 MASKSRCTRAN: WE_CH0 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH0_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH0_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH0 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH1_Pos         9                                                       /*!< GPDMA0 MASKSRCTRAN: WE_CH1 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH1_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH1_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH1 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH2_Pos         10                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH2 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH2_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH2_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH2 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH3_Pos         11                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH3 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH3_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH3_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH3 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH4_Pos         12                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH4 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH4_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH4_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH4 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH5_Pos         13                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH5 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH5_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH5_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH5 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH6_Pos         14                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH6 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH6_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH6_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH6 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH7_Pos         15                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH7 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH7_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH7_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH7 Mask         */\r
+\r
+/* -----------------------------  GPDMA0_MASKDSTTRAN  ----------------------------- */\r
+#define GPDMA0_MASKDSTTRAN_CH0_Pos            0                                                       /*!< GPDMA0 MASKDSTTRAN: CH0 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH0_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH0_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH0 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH1_Pos            1                                                       /*!< GPDMA0 MASKDSTTRAN: CH1 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH1_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH1_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH1 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH2_Pos            2                                                       /*!< GPDMA0 MASKDSTTRAN: CH2 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH2_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH2_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH2 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH3_Pos            3                                                       /*!< GPDMA0 MASKDSTTRAN: CH3 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH3_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH3_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH3 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH4_Pos            4                                                       /*!< GPDMA0 MASKDSTTRAN: CH4 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH4_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH4_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH4 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH5_Pos            5                                                       /*!< GPDMA0 MASKDSTTRAN: CH5 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH5_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH5_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH5 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH6_Pos            6                                                       /*!< GPDMA0 MASKDSTTRAN: CH6 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH6_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH6_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH6 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH7_Pos            7                                                       /*!< GPDMA0 MASKDSTTRAN: CH7 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH7_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH7_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH7 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH0_Pos         8                                                       /*!< GPDMA0 MASKDSTTRAN: WE_CH0 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH0_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH0_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH0 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH1_Pos         9                                                       /*!< GPDMA0 MASKDSTTRAN: WE_CH1 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH1_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH1_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH1 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH2_Pos         10                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH2 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH2_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH2_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH2 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH3_Pos         11                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH3 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH3_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH3_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH3 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH4_Pos         12                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH4 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH4_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH4_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH4 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH5_Pos         13                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH5 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH5_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH5_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH5 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH6_Pos         14                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH6 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH6_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH6_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH6 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH7_Pos         15                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH7 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH7_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH7_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH7 Mask         */\r
+\r
+/* -------------------------------  GPDMA0_MASKERR  ------------------------------- */\r
+#define GPDMA0_MASKERR_CH0_Pos                0                                                       /*!< GPDMA0 MASKERR: CH0 Position            */\r
+#define GPDMA0_MASKERR_CH0_Msk                (0x01UL << GPDMA0_MASKERR_CH0_Pos)                      /*!< GPDMA0 MASKERR: CH0 Mask                */\r
+#define GPDMA0_MASKERR_CH1_Pos                1                                                       /*!< GPDMA0 MASKERR: CH1 Position            */\r
+#define GPDMA0_MASKERR_CH1_Msk                (0x01UL << GPDMA0_MASKERR_CH1_Pos)                      /*!< GPDMA0 MASKERR: CH1 Mask                */\r
+#define GPDMA0_MASKERR_CH2_Pos                2                                                       /*!< GPDMA0 MASKERR: CH2 Position            */\r
+#define GPDMA0_MASKERR_CH2_Msk                (0x01UL << GPDMA0_MASKERR_CH2_Pos)                      /*!< GPDMA0 MASKERR: CH2 Mask                */\r
+#define GPDMA0_MASKERR_CH3_Pos                3                                                       /*!< GPDMA0 MASKERR: CH3 Position            */\r
+#define GPDMA0_MASKERR_CH3_Msk                (0x01UL << GPDMA0_MASKERR_CH3_Pos)                      /*!< GPDMA0 MASKERR: CH3 Mask                */\r
+#define GPDMA0_MASKERR_CH4_Pos                4                                                       /*!< GPDMA0 MASKERR: CH4 Position            */\r
+#define GPDMA0_MASKERR_CH4_Msk                (0x01UL << GPDMA0_MASKERR_CH4_Pos)                      /*!< GPDMA0 MASKERR: CH4 Mask                */\r
+#define GPDMA0_MASKERR_CH5_Pos                5                                                       /*!< GPDMA0 MASKERR: CH5 Position            */\r
+#define GPDMA0_MASKERR_CH5_Msk                (0x01UL << GPDMA0_MASKERR_CH5_Pos)                      /*!< GPDMA0 MASKERR: CH5 Mask                */\r
+#define GPDMA0_MASKERR_CH6_Pos                6                                                       /*!< GPDMA0 MASKERR: CH6 Position            */\r
+#define GPDMA0_MASKERR_CH6_Msk                (0x01UL << GPDMA0_MASKERR_CH6_Pos)                      /*!< GPDMA0 MASKERR: CH6 Mask                */\r
+#define GPDMA0_MASKERR_CH7_Pos                7                                                       /*!< GPDMA0 MASKERR: CH7 Position            */\r
+#define GPDMA0_MASKERR_CH7_Msk                (0x01UL << GPDMA0_MASKERR_CH7_Pos)                      /*!< GPDMA0 MASKERR: CH7 Mask                */\r
+#define GPDMA0_MASKERR_WE_CH0_Pos             8                                                       /*!< GPDMA0 MASKERR: WE_CH0 Position         */\r
+#define GPDMA0_MASKERR_WE_CH0_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH0_Pos)                   /*!< GPDMA0 MASKERR: WE_CH0 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH1_Pos             9                                                       /*!< GPDMA0 MASKERR: WE_CH1 Position         */\r
+#define GPDMA0_MASKERR_WE_CH1_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH1_Pos)                   /*!< GPDMA0 MASKERR: WE_CH1 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH2_Pos             10                                                      /*!< GPDMA0 MASKERR: WE_CH2 Position         */\r
+#define GPDMA0_MASKERR_WE_CH2_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH2_Pos)                   /*!< GPDMA0 MASKERR: WE_CH2 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH3_Pos             11                                                      /*!< GPDMA0 MASKERR: WE_CH3 Position         */\r
+#define GPDMA0_MASKERR_WE_CH3_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH3_Pos)                   /*!< GPDMA0 MASKERR: WE_CH3 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH4_Pos             12                                                      /*!< GPDMA0 MASKERR: WE_CH4 Position         */\r
+#define GPDMA0_MASKERR_WE_CH4_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH4_Pos)                   /*!< GPDMA0 MASKERR: WE_CH4 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH5_Pos             13                                                      /*!< GPDMA0 MASKERR: WE_CH5 Position         */\r
+#define GPDMA0_MASKERR_WE_CH5_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH5_Pos)                   /*!< GPDMA0 MASKERR: WE_CH5 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH6_Pos             14                                                      /*!< GPDMA0 MASKERR: WE_CH6 Position         */\r
+#define GPDMA0_MASKERR_WE_CH6_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH6_Pos)                   /*!< GPDMA0 MASKERR: WE_CH6 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH7_Pos             15                                                      /*!< GPDMA0 MASKERR: WE_CH7 Position         */\r
+#define GPDMA0_MASKERR_WE_CH7_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH7_Pos)                   /*!< GPDMA0 MASKERR: WE_CH7 Mask             */\r
+\r
+/* -------------------------------  GPDMA0_CLEARTFR  ------------------------------ */\r
+#define GPDMA0_CLEARTFR_CH0_Pos               0                                                       /*!< GPDMA0 CLEARTFR: CH0 Position           */\r
+#define GPDMA0_CLEARTFR_CH0_Msk               (0x01UL << GPDMA0_CLEARTFR_CH0_Pos)                     /*!< GPDMA0 CLEARTFR: CH0 Mask               */\r
+#define GPDMA0_CLEARTFR_CH1_Pos               1                                                       /*!< GPDMA0 CLEARTFR: CH1 Position           */\r
+#define GPDMA0_CLEARTFR_CH1_Msk               (0x01UL << GPDMA0_CLEARTFR_CH1_Pos)                     /*!< GPDMA0 CLEARTFR: CH1 Mask               */\r
+#define GPDMA0_CLEARTFR_CH2_Pos               2                                                       /*!< GPDMA0 CLEARTFR: CH2 Position           */\r
+#define GPDMA0_CLEARTFR_CH2_Msk               (0x01UL << GPDMA0_CLEARTFR_CH2_Pos)                     /*!< GPDMA0 CLEARTFR: CH2 Mask               */\r
+#define GPDMA0_CLEARTFR_CH3_Pos               3                                                       /*!< GPDMA0 CLEARTFR: CH3 Position           */\r
+#define GPDMA0_CLEARTFR_CH3_Msk               (0x01UL << GPDMA0_CLEARTFR_CH3_Pos)                     /*!< GPDMA0 CLEARTFR: CH3 Mask               */\r
+#define GPDMA0_CLEARTFR_CH4_Pos               4                                                       /*!< GPDMA0 CLEARTFR: CH4 Position           */\r
+#define GPDMA0_CLEARTFR_CH4_Msk               (0x01UL << GPDMA0_CLEARTFR_CH4_Pos)                     /*!< GPDMA0 CLEARTFR: CH4 Mask               */\r
+#define GPDMA0_CLEARTFR_CH5_Pos               5                                                       /*!< GPDMA0 CLEARTFR: CH5 Position           */\r
+#define GPDMA0_CLEARTFR_CH5_Msk               (0x01UL << GPDMA0_CLEARTFR_CH5_Pos)                     /*!< GPDMA0 CLEARTFR: CH5 Mask               */\r
+#define GPDMA0_CLEARTFR_CH6_Pos               6                                                       /*!< GPDMA0 CLEARTFR: CH6 Position           */\r
+#define GPDMA0_CLEARTFR_CH6_Msk               (0x01UL << GPDMA0_CLEARTFR_CH6_Pos)                     /*!< GPDMA0 CLEARTFR: CH6 Mask               */\r
+#define GPDMA0_CLEARTFR_CH7_Pos               7                                                       /*!< GPDMA0 CLEARTFR: CH7 Position           */\r
+#define GPDMA0_CLEARTFR_CH7_Msk               (0x01UL << GPDMA0_CLEARTFR_CH7_Pos)                     /*!< GPDMA0 CLEARTFR: CH7 Mask               */\r
+\r
+/* ------------------------------  GPDMA0_CLEARBLOCK  ----------------------------- */\r
+#define GPDMA0_CLEARBLOCK_CH0_Pos             0                                                       /*!< GPDMA0 CLEARBLOCK: CH0 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH0_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH0_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH0 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH1_Pos             1                                                       /*!< GPDMA0 CLEARBLOCK: CH1 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH1_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH1_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH1 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH2_Pos             2                                                       /*!< GPDMA0 CLEARBLOCK: CH2 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH2_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH2_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH2 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH3_Pos             3                                                       /*!< GPDMA0 CLEARBLOCK: CH3 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH3_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH3_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH3 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH4_Pos             4                                                       /*!< GPDMA0 CLEARBLOCK: CH4 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH4_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH4_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH4 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH5_Pos             5                                                       /*!< GPDMA0 CLEARBLOCK: CH5 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH5_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH5_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH5 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH6_Pos             6                                                       /*!< GPDMA0 CLEARBLOCK: CH6 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH6_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH6_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH6 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH7_Pos             7                                                       /*!< GPDMA0 CLEARBLOCK: CH7 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH7_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH7_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH7 Mask             */\r
+\r
+/* -----------------------------  GPDMA0_CLEARSRCTRAN  ---------------------------- */\r
+#define GPDMA0_CLEARSRCTRAN_CH0_Pos           0                                                       /*!< GPDMA0 CLEARSRCTRAN: CH0 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH0_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH0_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH0 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH1_Pos           1                                                       /*!< GPDMA0 CLEARSRCTRAN: CH1 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH1_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH1_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH1 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH2_Pos           2                                                       /*!< GPDMA0 CLEARSRCTRAN: CH2 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH2_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH2_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH2 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH3_Pos           3                                                       /*!< GPDMA0 CLEARSRCTRAN: CH3 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH3_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH3_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH3 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH4_Pos           4                                                       /*!< GPDMA0 CLEARSRCTRAN: CH4 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH4_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH4_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH4 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH5_Pos           5                                                       /*!< GPDMA0 CLEARSRCTRAN: CH5 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH5_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH5_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH5 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH6_Pos           6                                                       /*!< GPDMA0 CLEARSRCTRAN: CH6 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH6_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH6_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH6 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH7_Pos           7                                                       /*!< GPDMA0 CLEARSRCTRAN: CH7 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH7_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH7_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH7 Mask           */\r
+\r
+/* -----------------------------  GPDMA0_CLEARDSTTRAN  ---------------------------- */\r
+#define GPDMA0_CLEARDSTTRAN_CH0_Pos           0                                                       /*!< GPDMA0 CLEARDSTTRAN: CH0 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH0_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH0_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH0 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH1_Pos           1                                                       /*!< GPDMA0 CLEARDSTTRAN: CH1 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH1_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH1_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH1 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH2_Pos           2                                                       /*!< GPDMA0 CLEARDSTTRAN: CH2 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH2_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH2_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH2 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH3_Pos           3                                                       /*!< GPDMA0 CLEARDSTTRAN: CH3 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH3_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH3_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH3 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH4_Pos           4                                                       /*!< GPDMA0 CLEARDSTTRAN: CH4 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH4_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH4_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH4 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH5_Pos           5                                                       /*!< GPDMA0 CLEARDSTTRAN: CH5 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH5_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH5_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH5 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH6_Pos           6                                                       /*!< GPDMA0 CLEARDSTTRAN: CH6 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH6_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH6_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH6 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH7_Pos           7                                                       /*!< GPDMA0 CLEARDSTTRAN: CH7 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH7_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH7_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH7 Mask           */\r
+\r
+/* -------------------------------  GPDMA0_CLEARERR  ------------------------------ */\r
+#define GPDMA0_CLEARERR_CH0_Pos               0                                                       /*!< GPDMA0 CLEARERR: CH0 Position           */\r
+#define GPDMA0_CLEARERR_CH0_Msk               (0x01UL << GPDMA0_CLEARERR_CH0_Pos)                     /*!< GPDMA0 CLEARERR: CH0 Mask               */\r
+#define GPDMA0_CLEARERR_CH1_Pos               1                                                       /*!< GPDMA0 CLEARERR: CH1 Position           */\r
+#define GPDMA0_CLEARERR_CH1_Msk               (0x01UL << GPDMA0_CLEARERR_CH1_Pos)                     /*!< GPDMA0 CLEARERR: CH1 Mask               */\r
+#define GPDMA0_CLEARERR_CH2_Pos               2                                                       /*!< GPDMA0 CLEARERR: CH2 Position           */\r
+#define GPDMA0_CLEARERR_CH2_Msk               (0x01UL << GPDMA0_CLEARERR_CH2_Pos)                     /*!< GPDMA0 CLEARERR: CH2 Mask               */\r
+#define GPDMA0_CLEARERR_CH3_Pos               3                                                       /*!< GPDMA0 CLEARERR: CH3 Position           */\r
+#define GPDMA0_CLEARERR_CH3_Msk               (0x01UL << GPDMA0_CLEARERR_CH3_Pos)                     /*!< GPDMA0 CLEARERR: CH3 Mask               */\r
+#define GPDMA0_CLEARERR_CH4_Pos               4                                                       /*!< GPDMA0 CLEARERR: CH4 Position           */\r
+#define GPDMA0_CLEARERR_CH4_Msk               (0x01UL << GPDMA0_CLEARERR_CH4_Pos)                     /*!< GPDMA0 CLEARERR: CH4 Mask               */\r
+#define GPDMA0_CLEARERR_CH5_Pos               5                                                       /*!< GPDMA0 CLEARERR: CH5 Position           */\r
+#define GPDMA0_CLEARERR_CH5_Msk               (0x01UL << GPDMA0_CLEARERR_CH5_Pos)                     /*!< GPDMA0 CLEARERR: CH5 Mask               */\r
+#define GPDMA0_CLEARERR_CH6_Pos               6                                                       /*!< GPDMA0 CLEARERR: CH6 Position           */\r
+#define GPDMA0_CLEARERR_CH6_Msk               (0x01UL << GPDMA0_CLEARERR_CH6_Pos)                     /*!< GPDMA0 CLEARERR: CH6 Mask               */\r
+#define GPDMA0_CLEARERR_CH7_Pos               7                                                       /*!< GPDMA0 CLEARERR: CH7 Position           */\r
+#define GPDMA0_CLEARERR_CH7_Msk               (0x01UL << GPDMA0_CLEARERR_CH7_Pos)                     /*!< GPDMA0 CLEARERR: CH7 Mask               */\r
+\r
+/* ------------------------------  GPDMA0_STATUSINT  ------------------------------ */\r
+#define GPDMA0_STATUSINT_TFR_Pos              0                                                       /*!< GPDMA0 STATUSINT: TFR Position          */\r
+#define GPDMA0_STATUSINT_TFR_Msk              (0x01UL << GPDMA0_STATUSINT_TFR_Pos)                    /*!< GPDMA0 STATUSINT: TFR Mask              */\r
+#define GPDMA0_STATUSINT_BLOCK_Pos            1                                                       /*!< GPDMA0 STATUSINT: BLOCK Position        */\r
+#define GPDMA0_STATUSINT_BLOCK_Msk            (0x01UL << GPDMA0_STATUSINT_BLOCK_Pos)                  /*!< GPDMA0 STATUSINT: BLOCK Mask            */\r
+#define GPDMA0_STATUSINT_SRCT_Pos             2                                                       /*!< GPDMA0 STATUSINT: SRCT Position         */\r
+#define GPDMA0_STATUSINT_SRCT_Msk             (0x01UL << GPDMA0_STATUSINT_SRCT_Pos)                   /*!< GPDMA0 STATUSINT: SRCT Mask             */\r
+#define GPDMA0_STATUSINT_DSTT_Pos             3                                                       /*!< GPDMA0 STATUSINT: DSTT Position         */\r
+#define GPDMA0_STATUSINT_DSTT_Msk             (0x01UL << GPDMA0_STATUSINT_DSTT_Pos)                   /*!< GPDMA0 STATUSINT: DSTT Mask             */\r
+#define GPDMA0_STATUSINT_ERR_Pos              4                                                       /*!< GPDMA0 STATUSINT: ERR Position          */\r
+#define GPDMA0_STATUSINT_ERR_Msk              (0x01UL << GPDMA0_STATUSINT_ERR_Pos)                    /*!< GPDMA0 STATUSINT: ERR Mask              */\r
+\r
+/* ------------------------------  GPDMA0_REQSRCREG  ------------------------------ */\r
+#define GPDMA0_REQSRCREG_CH0_Pos              0                                                       /*!< GPDMA0 REQSRCREG: CH0 Position          */\r
+#define GPDMA0_REQSRCREG_CH0_Msk              (0x01UL << GPDMA0_REQSRCREG_CH0_Pos)                    /*!< GPDMA0 REQSRCREG: CH0 Mask              */\r
+#define GPDMA0_REQSRCREG_CH1_Pos              1                                                       /*!< GPDMA0 REQSRCREG: CH1 Position          */\r
+#define GPDMA0_REQSRCREG_CH1_Msk              (0x01UL << GPDMA0_REQSRCREG_CH1_Pos)                    /*!< GPDMA0 REQSRCREG: CH1 Mask              */\r
+#define GPDMA0_REQSRCREG_CH2_Pos              2                                                       /*!< GPDMA0 REQSRCREG: CH2 Position          */\r
+#define GPDMA0_REQSRCREG_CH2_Msk              (0x01UL << GPDMA0_REQSRCREG_CH2_Pos)                    /*!< GPDMA0 REQSRCREG: CH2 Mask              */\r
+#define GPDMA0_REQSRCREG_CH3_Pos              3                                                       /*!< GPDMA0 REQSRCREG: CH3 Position          */\r
+#define GPDMA0_REQSRCREG_CH3_Msk              (0x01UL << GPDMA0_REQSRCREG_CH3_Pos)                    /*!< GPDMA0 REQSRCREG: CH3 Mask              */\r
+#define GPDMA0_REQSRCREG_CH4_Pos              4                                                       /*!< GPDMA0 REQSRCREG: CH4 Position          */\r
+#define GPDMA0_REQSRCREG_CH4_Msk              (0x01UL << GPDMA0_REQSRCREG_CH4_Pos)                    /*!< GPDMA0 REQSRCREG: CH4 Mask              */\r
+#define GPDMA0_REQSRCREG_CH5_Pos              5                                                       /*!< GPDMA0 REQSRCREG: CH5 Position          */\r
+#define GPDMA0_REQSRCREG_CH5_Msk              (0x01UL << GPDMA0_REQSRCREG_CH5_Pos)                    /*!< GPDMA0 REQSRCREG: CH5 Mask              */\r
+#define GPDMA0_REQSRCREG_CH6_Pos              6                                                       /*!< GPDMA0 REQSRCREG: CH6 Position          */\r
+#define GPDMA0_REQSRCREG_CH6_Msk              (0x01UL << GPDMA0_REQSRCREG_CH6_Pos)                    /*!< GPDMA0 REQSRCREG: CH6 Mask              */\r
+#define GPDMA0_REQSRCREG_CH7_Pos              7                                                       /*!< GPDMA0 REQSRCREG: CH7 Position          */\r
+#define GPDMA0_REQSRCREG_CH7_Msk              (0x01UL << GPDMA0_REQSRCREG_CH7_Pos)                    /*!< GPDMA0 REQSRCREG: CH7 Mask              */\r
+#define GPDMA0_REQSRCREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 REQSRCREG: WE_CH0 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH0_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH0_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH0 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 REQSRCREG: WE_CH1 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH1_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH1_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH1 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 REQSRCREG: WE_CH2 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH2_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH2_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH2 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 REQSRCREG: WE_CH3 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH3_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH3_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH3 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 REQSRCREG: WE_CH4 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH4_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH4_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH4 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 REQSRCREG: WE_CH5 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH5_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH5_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH5 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 REQSRCREG: WE_CH6 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH6_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH6_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH6 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 REQSRCREG: WE_CH7 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH7_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH7_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH7 Mask           */\r
+\r
+/* ------------------------------  GPDMA0_REQDSTREG  ------------------------------ */\r
+#define GPDMA0_REQDSTREG_CH0_Pos              0                                                       /*!< GPDMA0 REQDSTREG: CH0 Position          */\r
+#define GPDMA0_REQDSTREG_CH0_Msk              (0x01UL << GPDMA0_REQDSTREG_CH0_Pos)                    /*!< GPDMA0 REQDSTREG: CH0 Mask              */\r
+#define GPDMA0_REQDSTREG_CH1_Pos              1                                                       /*!< GPDMA0 REQDSTREG: CH1 Position          */\r
+#define GPDMA0_REQDSTREG_CH1_Msk              (0x01UL << GPDMA0_REQDSTREG_CH1_Pos)                    /*!< GPDMA0 REQDSTREG: CH1 Mask              */\r
+#define GPDMA0_REQDSTREG_CH2_Pos              2                                                       /*!< GPDMA0 REQDSTREG: CH2 Position          */\r
+#define GPDMA0_REQDSTREG_CH2_Msk              (0x01UL << GPDMA0_REQDSTREG_CH2_Pos)                    /*!< GPDMA0 REQDSTREG: CH2 Mask              */\r
+#define GPDMA0_REQDSTREG_CH3_Pos              3                                                       /*!< GPDMA0 REQDSTREG: CH3 Position          */\r
+#define GPDMA0_REQDSTREG_CH3_Msk              (0x01UL << GPDMA0_REQDSTREG_CH3_Pos)                    /*!< GPDMA0 REQDSTREG: CH3 Mask              */\r
+#define GPDMA0_REQDSTREG_CH4_Pos              4                                                       /*!< GPDMA0 REQDSTREG: CH4 Position          */\r
+#define GPDMA0_REQDSTREG_CH4_Msk              (0x01UL << GPDMA0_REQDSTREG_CH4_Pos)                    /*!< GPDMA0 REQDSTREG: CH4 Mask              */\r
+#define GPDMA0_REQDSTREG_CH5_Pos              5                                                       /*!< GPDMA0 REQDSTREG: CH5 Position          */\r
+#define GPDMA0_REQDSTREG_CH5_Msk              (0x01UL << GPDMA0_REQDSTREG_CH5_Pos)                    /*!< GPDMA0 REQDSTREG: CH5 Mask              */\r
+#define GPDMA0_REQDSTREG_CH6_Pos              6                                                       /*!< GPDMA0 REQDSTREG: CH6 Position          */\r
+#define GPDMA0_REQDSTREG_CH6_Msk              (0x01UL << GPDMA0_REQDSTREG_CH6_Pos)                    /*!< GPDMA0 REQDSTREG: CH6 Mask              */\r
+#define GPDMA0_REQDSTREG_CH7_Pos              7                                                       /*!< GPDMA0 REQDSTREG: CH7 Position          */\r
+#define GPDMA0_REQDSTREG_CH7_Msk              (0x01UL << GPDMA0_REQDSTREG_CH7_Pos)                    /*!< GPDMA0 REQDSTREG: CH7 Mask              */\r
+#define GPDMA0_REQDSTREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 REQDSTREG: WE_CH0 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH0_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH0_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH0 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 REQDSTREG: WE_CH1 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH1_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH1_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH1 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 REQDSTREG: WE_CH2 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH2_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH2_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH2 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 REQDSTREG: WE_CH3 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH3_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH3_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH3 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 REQDSTREG: WE_CH4 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH4_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH4_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH4 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 REQDSTREG: WE_CH5 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH5_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH5_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH5 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 REQDSTREG: WE_CH6 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH6_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH6_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH6 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 REQDSTREG: WE_CH7 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH7_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH7_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH7 Mask           */\r
+\r
+/* -----------------------------  GPDMA0_SGLREQSRCREG  ---------------------------- */\r
+#define GPDMA0_SGLREQSRCREG_CH0_Pos           0                                                       /*!< GPDMA0 SGLREQSRCREG: CH0 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH0_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH0_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH0 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH1_Pos           1                                                       /*!< GPDMA0 SGLREQSRCREG: CH1 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH1_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH1_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH1 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH2_Pos           2                                                       /*!< GPDMA0 SGLREQSRCREG: CH2 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH2_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH2_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH2 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH3_Pos           3                                                       /*!< GPDMA0 SGLREQSRCREG: CH3 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH3_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH3_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH3 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH4_Pos           4                                                       /*!< GPDMA0 SGLREQSRCREG: CH4 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH4_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH4_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH4 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH5_Pos           5                                                       /*!< GPDMA0 SGLREQSRCREG: CH5 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH5_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH5_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH5 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH6_Pos           6                                                       /*!< GPDMA0 SGLREQSRCREG: CH6 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH6_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH6_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH6 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH7_Pos           7                                                       /*!< GPDMA0 SGLREQSRCREG: CH7 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH7_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH7_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH7 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH0_Pos        8                                                       /*!< GPDMA0 SGLREQSRCREG: WE_CH0 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH0_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH0_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH0 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH1_Pos        9                                                       /*!< GPDMA0 SGLREQSRCREG: WE_CH1 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH1_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH1_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH1 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH2_Pos        10                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH2 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH2_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH2_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH2 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH3_Pos        11                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH3 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH3_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH3_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH3 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH4_Pos        12                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH4 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH4_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH4_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH4 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH5_Pos        13                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH5 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH5_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH5_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH5 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH6_Pos        14                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH6 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH6_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH6_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH6 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH7_Pos        15                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH7 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH7_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH7_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH7 Mask        */\r
+\r
+/* -----------------------------  GPDMA0_SGLREQDSTREG  ---------------------------- */\r
+#define GPDMA0_SGLREQDSTREG_CH0_Pos           0                                                       /*!< GPDMA0 SGLREQDSTREG: CH0 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH0_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH0_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH0 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH1_Pos           1                                                       /*!< GPDMA0 SGLREQDSTREG: CH1 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH1_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH1_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH1 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH2_Pos           2                                                       /*!< GPDMA0 SGLREQDSTREG: CH2 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH2_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH2_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH2 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH3_Pos           3                                                       /*!< GPDMA0 SGLREQDSTREG: CH3 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH3_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH3_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH3 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH4_Pos           4                                                       /*!< GPDMA0 SGLREQDSTREG: CH4 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH4_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH4_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH4 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH5_Pos           5                                                       /*!< GPDMA0 SGLREQDSTREG: CH5 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH5_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH5_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH5 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH6_Pos           6                                                       /*!< GPDMA0 SGLREQDSTREG: CH6 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH6_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH6_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH6 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH7_Pos           7                                                       /*!< GPDMA0 SGLREQDSTREG: CH7 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH7_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH7_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH7 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH0_Pos        8                                                       /*!< GPDMA0 SGLREQDSTREG: WE_CH0 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH0_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH0_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH0 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH1_Pos        9                                                       /*!< GPDMA0 SGLREQDSTREG: WE_CH1 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH1_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH1_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH1 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH2_Pos        10                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH2 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH2_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH2_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH2 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH3_Pos        11                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH3 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH3_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH3_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH3 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH4_Pos        12                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH4 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH4_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH4_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH4 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH5_Pos        13                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH5 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH5_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH5_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH5 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH6_Pos        14                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH6 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH6_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH6_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH6 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH7_Pos        15                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH7 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH7_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH7_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH7 Mask        */\r
+\r
+/* ------------------------------  GPDMA0_LSTSRCREG  ------------------------------ */\r
+#define GPDMA0_LSTSRCREG_CH0_Pos              0                                                       /*!< GPDMA0 LSTSRCREG: CH0 Position          */\r
+#define GPDMA0_LSTSRCREG_CH0_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH0_Pos)                    /*!< GPDMA0 LSTSRCREG: CH0 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH1_Pos              1                                                       /*!< GPDMA0 LSTSRCREG: CH1 Position          */\r
+#define GPDMA0_LSTSRCREG_CH1_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH1_Pos)                    /*!< GPDMA0 LSTSRCREG: CH1 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH2_Pos              2                                                       /*!< GPDMA0 LSTSRCREG: CH2 Position          */\r
+#define GPDMA0_LSTSRCREG_CH2_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH2_Pos)                    /*!< GPDMA0 LSTSRCREG: CH2 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH3_Pos              3                                                       /*!< GPDMA0 LSTSRCREG: CH3 Position          */\r
+#define GPDMA0_LSTSRCREG_CH3_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH3_Pos)                    /*!< GPDMA0 LSTSRCREG: CH3 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH4_Pos              4                                                       /*!< GPDMA0 LSTSRCREG: CH4 Position          */\r
+#define GPDMA0_LSTSRCREG_CH4_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH4_Pos)                    /*!< GPDMA0 LSTSRCREG: CH4 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH5_Pos              5                                                       /*!< GPDMA0 LSTSRCREG: CH5 Position          */\r
+#define GPDMA0_LSTSRCREG_CH5_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH5_Pos)                    /*!< GPDMA0 LSTSRCREG: CH5 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH6_Pos              6                                                       /*!< GPDMA0 LSTSRCREG: CH6 Position          */\r
+#define GPDMA0_LSTSRCREG_CH6_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH6_Pos)                    /*!< GPDMA0 LSTSRCREG: CH6 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH7_Pos              7                                                       /*!< GPDMA0 LSTSRCREG: CH7 Position          */\r
+#define GPDMA0_LSTSRCREG_CH7_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH7_Pos)                    /*!< GPDMA0 LSTSRCREG: CH7 Mask              */\r
+#define GPDMA0_LSTSRCREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 LSTSRCREG: WE_CH0 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH0_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH0_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH0 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 LSTSRCREG: WE_CH1 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH1_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH1_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH1 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 LSTSRCREG: WE_CH2 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH2_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH2_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH2 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 LSTSRCREG: WE_CH3 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH3_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH3_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH3 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 LSTSRCREG: WE_CH4 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH4_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH4_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH4 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 LSTSRCREG: WE_CH5 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH5_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH5_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH5 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 LSTSRCREG: WE_CH6 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH6_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH6_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH6 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 LSTSRCREG: WE_CH7 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH7_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH7_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH7 Mask           */\r
+\r
+/* ------------------------------  GPDMA0_LSTDSTREG  ------------------------------ */\r
+#define GPDMA0_LSTDSTREG_CH0_Pos              0                                                       /*!< GPDMA0 LSTDSTREG: CH0 Position          */\r
+#define GPDMA0_LSTDSTREG_CH0_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH0_Pos)                    /*!< GPDMA0 LSTDSTREG: CH0 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH1_Pos              1                                                       /*!< GPDMA0 LSTDSTREG: CH1 Position          */\r
+#define GPDMA0_LSTDSTREG_CH1_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH1_Pos)                    /*!< GPDMA0 LSTDSTREG: CH1 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH2_Pos              2                                                       /*!< GPDMA0 LSTDSTREG: CH2 Position          */\r
+#define GPDMA0_LSTDSTREG_CH2_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH2_Pos)                    /*!< GPDMA0 LSTDSTREG: CH2 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH3_Pos              3                                                       /*!< GPDMA0 LSTDSTREG: CH3 Position          */\r
+#define GPDMA0_LSTDSTREG_CH3_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH3_Pos)                    /*!< GPDMA0 LSTDSTREG: CH3 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH4_Pos              4                                                       /*!< GPDMA0 LSTDSTREG: CH4 Position          */\r
+#define GPDMA0_LSTDSTREG_CH4_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH4_Pos)                    /*!< GPDMA0 LSTDSTREG: CH4 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH5_Pos              5                                                       /*!< GPDMA0 LSTDSTREG: CH5 Position          */\r
+#define GPDMA0_LSTDSTREG_CH5_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH5_Pos)                    /*!< GPDMA0 LSTDSTREG: CH5 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH6_Pos              6                                                       /*!< GPDMA0 LSTDSTREG: CH6 Position          */\r
+#define GPDMA0_LSTDSTREG_CH6_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH6_Pos)                    /*!< GPDMA0 LSTDSTREG: CH6 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH7_Pos              7                                                       /*!< GPDMA0 LSTDSTREG: CH7 Position          */\r
+#define GPDMA0_LSTDSTREG_CH7_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH7_Pos)                    /*!< GPDMA0 LSTDSTREG: CH7 Mask              */\r
+#define GPDMA0_LSTDSTREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 LSTDSTREG: WE_CH0 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH0_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH0_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH0 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 LSTDSTREG: WE_CH1 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH1_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH1_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH1 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 LSTDSTREG: WE_CH2 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH2_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH2_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH2 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 LSTDSTREG: WE_CH3 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH3_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH3_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH3 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 LSTDSTREG: WE_CH4 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH4_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH4_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH4 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 LSTDSTREG: WE_CH5 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH5_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH5_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH5 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 LSTDSTREG: WE_CH6 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH6_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH6_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH6 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 LSTDSTREG: WE_CH7 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH7_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH7_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH7 Mask           */\r
+\r
+/* ------------------------------  GPDMA0_DMACFGREG  ------------------------------ */\r
+#define GPDMA0_DMACFGREG_DMA_EN_Pos           0                                                       /*!< GPDMA0 DMACFGREG: DMA_EN Position       */\r
+#define GPDMA0_DMACFGREG_DMA_EN_Msk           (0x01UL << GPDMA0_DMACFGREG_DMA_EN_Pos)                 /*!< GPDMA0 DMACFGREG: DMA_EN Mask           */\r
+\r
+/* -------------------------------  GPDMA0_CHENREG  ------------------------------- */\r
+#define GPDMA0_CHENREG_CH_Pos                 0                                                       /*!< GPDMA0 CHENREG: CH Position             */\r
+#define GPDMA0_CHENREG_CH_Msk                 (0x000000ffUL << GPDMA0_CHENREG_CH_Pos)                 /*!< GPDMA0 CHENREG: CH Mask                 */\r
+#define GPDMA0_CHENREG_WE_CH_Pos              8                                                       /*!< GPDMA0 CHENREG: WE_CH Position          */\r
+#define GPDMA0_CHENREG_WE_CH_Msk              (0x000000ffUL << GPDMA0_CHENREG_WE_CH_Pos)              /*!< GPDMA0 CHENREG: WE_CH Mask              */\r
+\r
+/* ----------------------------------  GPDMA0_ID  --------------------------------- */\r
+#define GPDMA0_ID_VALUE_Pos                   0                                                       /*!< GPDMA0 ID: VALUE Position               */\r
+#define GPDMA0_ID_VALUE_Msk                   (0xffffffffUL << GPDMA0_ID_VALUE_Pos)                   /*!< GPDMA0 ID: VALUE Mask                   */\r
+\r
+/* ---------------------------------  GPDMA0_TYPE  -------------------------------- */\r
+#define GPDMA0_TYPE_VALUE_Pos                 0                                                       /*!< GPDMA0 TYPE: VALUE Position             */\r
+#define GPDMA0_TYPE_VALUE_Msk                 (0xffffffffUL << GPDMA0_TYPE_VALUE_Pos)                 /*!< GPDMA0 TYPE: VALUE Mask                 */\r
+\r
+/* -------------------------------  GPDMA0_VERSION  ------------------------------- */\r
+#define GPDMA0_VERSION_VALUE_Pos              0                                                       /*!< GPDMA0 VERSION: VALUE Position          */\r
+#define GPDMA0_VERSION_VALUE_Msk              (0xffffffffUL << GPDMA0_VERSION_VALUE_Pos)              /*!< GPDMA0 VERSION: VALUE Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      Group 'GPDMA0_CH0_1' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  GPDMA0_CH_SAR  ------------------------------ */\r
+#define GPDMA0_CH_SAR_SAR_Pos              0                                                       /*!< GPDMA0_CH0_1 SAR: SAR Position          */\r
+#define GPDMA0_CH_SAR_SAR_Msk              (0xffffffffUL << GPDMA0_CH_SAR_SAR_Pos)              /*!< GPDMA0_CH0_1 SAR: SAR Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_DAR  ------------------------------ */\r
+#define GPDMA0_CH_DAR_DAR_Pos              0                                                       /*!< GPDMA0_CH0_1 DAR: DAR Position          */\r
+#define GPDMA0_CH_DAR_DAR_Msk              (0xffffffffUL << GPDMA0_CH_DAR_DAR_Pos)              /*!< GPDMA0_CH0_1 DAR: DAR Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_LLP  ------------------------------ */\r
+#define GPDMA0_CH_LLP_LOC_Pos              2                                                       /*!< GPDMA0_CH0_1 LLP: LOC Position          */\r
+#define GPDMA0_CH_LLP_LOC_Msk              (0x3fffffffUL << GPDMA0_CH_LLP_LOC_Pos)              /*!< GPDMA0_CH0_1 LLP: LOC Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_CTLL  ----------------------------- */\r
+#define GPDMA0_CH_CTLL_INT_EN_Pos          0                                                       /*!< GPDMA0_CH0_1 CTLL: INT_EN Position      */\r
+#define GPDMA0_CH_CTLL_INT_EN_Msk          (0x01UL << GPDMA0_CH_CTLL_INT_EN_Pos)                /*!< GPDMA0_CH0_1 CTLL: INT_EN Mask          */\r
+#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos    1                                                       /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH Position */\r
+#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk    (0x07UL << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos)          /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH Mask    */\r
+#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos    4                                                       /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH Position */\r
+#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk    (0x07UL << GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos)          /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH Mask    */\r
+#define GPDMA0_CH_CTLL_DINC_Pos            7                                                       /*!< GPDMA0_CH0_1 CTLL: DINC Position        */\r
+#define GPDMA0_CH_CTLL_DINC_Msk            (0x03UL << GPDMA0_CH_CTLL_DINC_Pos)                  /*!< GPDMA0_CH0_1 CTLL: DINC Mask            */\r
+#define GPDMA0_CH_CTLL_SINC_Pos            9                                                       /*!< GPDMA0_CH0_1 CTLL: SINC Position        */\r
+#define GPDMA0_CH_CTLL_SINC_Msk            (0x03UL << GPDMA0_CH_CTLL_SINC_Pos)                  /*!< GPDMA0_CH0_1 CTLL: SINC Mask            */\r
+#define GPDMA0_CH_CTLL_DEST_MSIZE_Pos      11                                                      /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE Position  */\r
+#define GPDMA0_CH_CTLL_DEST_MSIZE_Msk      (0x07UL << GPDMA0_CH_CTLL_DEST_MSIZE_Pos)            /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE Mask      */\r
+#define GPDMA0_CH_CTLL_SRC_MSIZE_Pos       14                                                      /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE Position   */\r
+#define GPDMA0_CH_CTLL_SRC_MSIZE_Msk       (0x07UL << GPDMA0_CH_CTLL_SRC_MSIZE_Pos)             /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE Mask       */\r
+#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos   17                                                      /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN Position */\r
+#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk   (0x01UL << GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos)         /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN Mask   */\r
+#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos  18                                                      /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN Position */\r
+#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk  (0x01UL << GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos)        /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN Mask  */\r
+#define GPDMA0_CH_CTLL_TT_FC_Pos           20                                                      /*!< GPDMA0_CH0_1 CTLL: TT_FC Position       */\r
+#define GPDMA0_CH_CTLL_TT_FC_Msk           (0x07UL << GPDMA0_CH_CTLL_TT_FC_Pos)                 /*!< GPDMA0_CH0_1 CTLL: TT_FC Mask           */\r
+#define GPDMA0_CH_CTLL_LLP_DST_EN_Pos      27                                                      /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN Position  */\r
+#define GPDMA0_CH_CTLL_LLP_DST_EN_Msk      (0x01UL << GPDMA0_CH_CTLL_LLP_DST_EN_Pos)            /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN Mask      */\r
+#define GPDMA0_CH_CTLL_LLP_SRC_EN_Pos      28                                                      /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN Position  */\r
+#define GPDMA0_CH_CTLL_LLP_SRC_EN_Msk      (0x01UL << GPDMA0_CH_CTLL_LLP_SRC_EN_Pos)            /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN Mask      */\r
+\r
+/* ------------------------------  GPDMA0_CH_CTLH  ----------------------------- */\r
+#define GPDMA0_CH_CTLH_BLOCK_TS_Pos        0                                                       /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS Position    */\r
+#define GPDMA0_CH_CTLH_BLOCK_TS_Msk        (0x00000fffUL << GPDMA0_CH_CTLH_BLOCK_TS_Pos)        /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS Mask        */\r
+#define GPDMA0_CH_CTLH_DONE_Pos            12                                                      /*!< GPDMA0_CH0_1 CTLH: DONE Position        */\r
+#define GPDMA0_CH_CTLH_DONE_Msk            (0x01UL << GPDMA0_CH_CTLH_DONE_Pos)                  /*!< GPDMA0_CH0_1 CTLH: DONE Mask            */\r
+\r
+/* -----------------------------  GPDMA0_CH_SSTAT  ----------------------------- */\r
+#define GPDMA0_CH_SSTAT_SSTAT_Pos          0                                                       /*!< GPDMA0_CH0_1 SSTAT: SSTAT Position      */\r
+#define GPDMA0_CH_SSTAT_SSTAT_Msk          (0xffffffffUL << GPDMA0_CH_SSTAT_SSTAT_Pos)          /*!< GPDMA0_CH0_1 SSTAT: SSTAT Mask          */\r
+\r
+/* -----------------------------  GPDMA0_CH_DSTAT  ----------------------------- */\r
+#define GPDMA0_CH_DSTAT_DSTAT_Pos          0                                                       /*!< GPDMA0_CH0_1 DSTAT: DSTAT Position      */\r
+#define GPDMA0_CH_DSTAT_DSTAT_Msk          (0xffffffffUL << GPDMA0_CH_DSTAT_DSTAT_Pos)          /*!< GPDMA0_CH0_1 DSTAT: DSTAT Mask          */\r
+\r
+/* ----------------------------  GPDMA0_CH_SSTATAR  ---------------------------- */\r
+#define GPDMA0_CH_SSTATAR_SSTATAR_Pos      0                                                       /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR Position  */\r
+#define GPDMA0_CH_SSTATAR_SSTATAR_Msk      (0xffffffffUL << GPDMA0_CH_SSTATAR_SSTATAR_Pos)      /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR Mask      */\r
+\r
+/* ----------------------------  GPDMA0_CH_DSTATAR  ---------------------------- */\r
+#define GPDMA0_CH_DSTATAR_DSTATAR_Pos      0                                                       /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR Position  */\r
+#define GPDMA0_CH_DSTATAR_DSTATAR_Msk      (0xffffffffUL << GPDMA0_CH_DSTATAR_DSTATAR_Pos)      /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR Mask      */\r
+\r
+/* ------------------------------  GPDMA0_CH_CFGL  ----------------------------- */\r
+#define GPDMA0_CH_CFGL_CH_PRIOR_Pos        5                                                       /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR Position    */\r
+#define GPDMA0_CH_CFGL_CH_PRIOR_Msk        (0x07UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos)              /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR Mask        */\r
+#define GPDMA0_CH_CFGL_CH_SUSP_Pos         8                                                       /*!< GPDMA0_CH0_1 CFGL: CH_SUSP Position     */\r
+#define GPDMA0_CH_CFGL_CH_SUSP_Msk         (0x01UL << GPDMA0_CH_CFGL_CH_SUSP_Pos)               /*!< GPDMA0_CH0_1 CFGL: CH_SUSP Mask         */\r
+#define GPDMA0_CH_CFGL_FIFO_EMPTY_Pos      9                                                       /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY Position  */\r
+#define GPDMA0_CH_CFGL_FIFO_EMPTY_Msk      (0x01UL << GPDMA0_CH_CFGL_FIFO_EMPTY_Pos)            /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY Mask      */\r
+#define GPDMA0_CH_CFGL_HS_SEL_DST_Pos      10                                                      /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST Position  */\r
+#define GPDMA0_CH_CFGL_HS_SEL_DST_Msk      (0x01UL << GPDMA0_CH_CFGL_HS_SEL_DST_Pos)            /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST Mask      */\r
+#define GPDMA0_CH_CFGL_HS_SEL_SRC_Pos      11                                                      /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC Position  */\r
+#define GPDMA0_CH_CFGL_HS_SEL_SRC_Msk      (0x01UL << GPDMA0_CH_CFGL_HS_SEL_SRC_Pos)            /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC Mask      */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_L_Pos       12                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L Position   */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_L_Msk       (0x03UL << GPDMA0_CH_CFGL_LOCK_CH_L_Pos)             /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L Mask       */\r
+#define GPDMA0_CH_CFGL_LOCK_B_L_Pos        14                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L Position    */\r
+#define GPDMA0_CH_CFGL_LOCK_B_L_Msk        (0x03UL << GPDMA0_CH_CFGL_LOCK_B_L_Pos)              /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L Mask        */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_Pos         16                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_CH Position     */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_Msk         (0x01UL << GPDMA0_CH_CFGL_LOCK_CH_Pos)               /*!< GPDMA0_CH0_1 CFGL: LOCK_CH Mask         */\r
+#define GPDMA0_CH_CFGL_LOCK_B_Pos          17                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_B Position      */\r
+#define GPDMA0_CH_CFGL_LOCK_B_Msk          (0x01UL << GPDMA0_CH_CFGL_LOCK_B_Pos)                /*!< GPDMA0_CH0_1 CFGL: LOCK_B Mask          */\r
+#define GPDMA0_CH_CFGL_DST_HS_POL_Pos      18                                                      /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL Position  */\r
+#define GPDMA0_CH_CFGL_DST_HS_POL_Msk      (0x01UL << GPDMA0_CH_CFGL_DST_HS_POL_Pos)            /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL Mask      */\r
+#define GPDMA0_CH_CFGL_SRC_HS_POL_Pos      19                                                      /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL Position  */\r
+#define GPDMA0_CH_CFGL_SRC_HS_POL_Msk      (0x01UL << GPDMA0_CH_CFGL_SRC_HS_POL_Pos)            /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL Mask      */\r
+#define GPDMA0_CH_CFGL_MAX_ABRST_Pos       20                                                      /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST Position   */\r
+#define GPDMA0_CH_CFGL_MAX_ABRST_Msk       (0x000003ffUL << GPDMA0_CH_CFGL_MAX_ABRST_Pos)       /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST Mask       */\r
+#define GPDMA0_CH_CFGL_RELOAD_SRC_Pos      30                                                      /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC Position  */\r
+#define GPDMA0_CH_CFGL_RELOAD_SRC_Msk      (0x01UL << GPDMA0_CH_CFGL_RELOAD_SRC_Pos)            /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC Mask      */\r
+#define GPDMA0_CH_CFGL_RELOAD_DST_Pos      31                                                      /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST Position  */\r
+#define GPDMA0_CH_CFGL_RELOAD_DST_Msk      (0x01UL << GPDMA0_CH_CFGL_RELOAD_DST_Pos)            /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST Mask      */\r
+\r
+/* ------------------------------  GPDMA0_CH_CFGH  ----------------------------- */\r
+#define GPDMA0_CH_CFGH_FCMODE_Pos          0                                                       /*!< GPDMA0_CH0_1 CFGH: FCMODE Position      */\r
+#define GPDMA0_CH_CFGH_FCMODE_Msk          (0x01UL << GPDMA0_CH_CFGH_FCMODE_Pos)                /*!< GPDMA0_CH0_1 CFGH: FCMODE Mask          */\r
+#define GPDMA0_CH_CFGH_FIFO_MODE_Pos       1                                                       /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE Position   */\r
+#define GPDMA0_CH_CFGH_FIFO_MODE_Msk       (0x01UL << GPDMA0_CH_CFGH_FIFO_MODE_Pos)             /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE Mask       */\r
+#define GPDMA0_CH_CFGH_PROTCTL_Pos         2                                                       /*!< GPDMA0_CH0_1 CFGH: PROTCTL Position     */\r
+#define GPDMA0_CH_CFGH_PROTCTL_Msk         (0x07UL << GPDMA0_CH_CFGH_PROTCTL_Pos)               /*!< GPDMA0_CH0_1 CFGH: PROTCTL Mask         */\r
+#define GPDMA0_CH_CFGH_DS_UPD_EN_Pos       5                                                       /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN Position   */\r
+#define GPDMA0_CH_CFGH_DS_UPD_EN_Msk       (0x01UL << GPDMA0_CH_CFGH_DS_UPD_EN_Pos)             /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN Mask       */\r
+#define GPDMA0_CH_CFGH_SS_UPD_EN_Pos       6                                                       /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN Position   */\r
+#define GPDMA0_CH_CFGH_SS_UPD_EN_Msk       (0x01UL << GPDMA0_CH_CFGH_SS_UPD_EN_Pos)             /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN Mask       */\r
+#define GPDMA0_CH_CFGH_SRC_PER_Pos         7                                                       /*!< GPDMA0_CH0_1 CFGH: SRC_PER Position     */\r
+#define GPDMA0_CH_CFGH_SRC_PER_Msk         (0x0fUL << GPDMA0_CH_CFGH_SRC_PER_Pos)               /*!< GPDMA0_CH0_1 CFGH: SRC_PER Mask         */\r
+#define GPDMA0_CH_CFGH_DEST_PER_Pos        11                                                      /*!< GPDMA0_CH0_1 CFGH: DEST_PER Position    */\r
+#define GPDMA0_CH_CFGH_DEST_PER_Msk        (0x0fUL << GPDMA0_CH_CFGH_DEST_PER_Pos)              /*!< GPDMA0_CH0_1 CFGH: DEST_PER Mask        */\r
+\r
+/* ------------------------------  GPDMA0_CH_SGR  ------------------------------ */\r
+#define GPDMA0_CH_SGR_SGI_Pos              0                                                       /*!< GPDMA0_CH0_1 SGR: SGI Position          */\r
+#define GPDMA0_CH_SGR_SGI_Msk              (0x000fffffUL << GPDMA0_CH_SGR_SGI_Pos)              /*!< GPDMA0_CH0_1 SGR: SGI Mask              */\r
+#define GPDMA0_CH_SGR_SGC_Pos              20                                                      /*!< GPDMA0_CH0_1 SGR: SGC Position          */\r
+#define GPDMA0_CH_SGR_SGC_Msk              (0x00000fffUL << GPDMA0_CH_SGR_SGC_Pos)              /*!< GPDMA0_CH0_1 SGR: SGC Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_DSR  ------------------------------ */\r
+#define GPDMA0_CH_DSR_DSI_Pos              0                                                       /*!< GPDMA0_CH0_1 DSR: DSI Position          */\r
+#define GPDMA0_CH_DSR_DSI_Msk              (0x000fffffUL << GPDMA0_CH_DSR_DSI_Pos)              /*!< GPDMA0_CH0_1 DSR: DSI Mask              */\r
+#define GPDMA0_CH_DSR_DSC_Pos              20                                                      /*!< GPDMA0_CH0_1 DSR: DSC Position          */\r
+#define GPDMA0_CH_DSR_DSC_Msk              (0x00000fffUL << GPDMA0_CH_DSR_DSC_Pos)              /*!< GPDMA0_CH0_1 DSR: DSC Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'FCE' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  FCE_CLC  ---------------------------------- */\r
+#define FCE_CLC_DISR_Pos                      0                                                       /*!< FCE CLC: DISR Position                  */\r
+#define FCE_CLC_DISR_Msk                      (0x01UL << FCE_CLC_DISR_Pos)                            /*!< FCE CLC: DISR Mask                      */\r
+#define FCE_CLC_DISS_Pos                      1                                                       /*!< FCE CLC: DISS Position                  */\r
+#define FCE_CLC_DISS_Msk                      (0x01UL << FCE_CLC_DISS_Pos)                            /*!< FCE CLC: DISS Mask                      */\r
+\r
+/* -----------------------------------  FCE_ID  ----------------------------------- */\r
+#define FCE_ID_MOD_REV_Pos                    0                                                       /*!< FCE ID: MOD_REV Position                */\r
+#define FCE_ID_MOD_REV_Msk                    (0x000000ffUL << FCE_ID_MOD_REV_Pos)                    /*!< FCE ID: MOD_REV Mask                    */\r
+#define FCE_ID_MOD_TYPE_Pos                   8                                                       /*!< FCE ID: MOD_TYPE Position               */\r
+#define FCE_ID_MOD_TYPE_Msk                   (0x000000ffUL << FCE_ID_MOD_TYPE_Pos)                   /*!< FCE ID: MOD_TYPE Mask                   */\r
+#define FCE_ID_MOD_NUMBER_Pos                 16                                                      /*!< FCE ID: MOD_NUMBER Position             */\r
+#define FCE_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << FCE_ID_MOD_NUMBER_Pos)                 /*!< FCE ID: MOD_NUMBER Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'FCE_KE' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  FCE_KE_IR  --------------------------------- */\r
+#define FCE_KE_IR_IR_Pos                      0                                                       /*!< FCE_KE IR: IR Position                  */\r
+#define FCE_KE_IR_IR_Msk                      (0xffffffffUL << FCE_KE_IR_IR_Pos)                      /*!< FCE_KE IR: IR Mask                      */\r
+\r
+/* ---------------------------------  FCE_KE_RES  --------------------------------- */\r
+#define FCE_KE_RES_RES_Pos                    0                                                       /*!< FCE_KE RES: RES Position                */\r
+#define FCE_KE_RES_RES_Msk                    (0xffffffffUL << FCE_KE_RES_RES_Pos)                    /*!< FCE_KE RES: RES Mask                    */\r
+\r
+/* ---------------------------------  FCE_KE_CFG  --------------------------------- */\r
+#define FCE_KE_CFG_CMI_Pos                    0                                                       /*!< FCE_KE CFG: CMI Position                */\r
+#define FCE_KE_CFG_CMI_Msk                    (0x01UL << FCE_KE_CFG_CMI_Pos)                          /*!< FCE_KE CFG: CMI Mask                    */\r
+#define FCE_KE_CFG_CEI_Pos                    1                                                       /*!< FCE_KE CFG: CEI Position                */\r
+#define FCE_KE_CFG_CEI_Msk                    (0x01UL << FCE_KE_CFG_CEI_Pos)                          /*!< FCE_KE CFG: CEI Mask                    */\r
+#define FCE_KE_CFG_LEI_Pos                    2                                                       /*!< FCE_KE CFG: LEI Position                */\r
+#define FCE_KE_CFG_LEI_Msk                    (0x01UL << FCE_KE_CFG_LEI_Pos)                          /*!< FCE_KE CFG: LEI Mask                    */\r
+#define FCE_KE_CFG_BEI_Pos                    3                                                       /*!< FCE_KE CFG: BEI Position                */\r
+#define FCE_KE_CFG_BEI_Msk                    (0x01UL << FCE_KE_CFG_BEI_Pos)                          /*!< FCE_KE CFG: BEI Mask                    */\r
+#define FCE_KE_CFG_CCE_Pos                    4                                                       /*!< FCE_KE CFG: CCE Position                */\r
+#define FCE_KE_CFG_CCE_Msk                    (0x01UL << FCE_KE_CFG_CCE_Pos)                          /*!< FCE_KE CFG: CCE Mask                    */\r
+#define FCE_KE_CFG_ALR_Pos                    5                                                       /*!< FCE_KE CFG: ALR Position                */\r
+#define FCE_KE_CFG_ALR_Msk                    (0x01UL << FCE_KE_CFG_ALR_Pos)                          /*!< FCE_KE CFG: ALR Mask                    */\r
+#define FCE_KE_CFG_REFIN_Pos                  8                                                       /*!< FCE_KE CFG: REFIN Position              */\r
+#define FCE_KE_CFG_REFIN_Msk                  (0x01UL << FCE_KE_CFG_REFIN_Pos)                        /*!< FCE_KE CFG: REFIN Mask                  */\r
+#define FCE_KE_CFG_REFOUT_Pos                 9                                                       /*!< FCE_KE CFG: REFOUT Position             */\r
+#define FCE_KE_CFG_REFOUT_Msk                 (0x01UL << FCE_KE_CFG_REFOUT_Pos)                       /*!< FCE_KE CFG: REFOUT Mask                 */\r
+#define FCE_KE_CFG_XSEL_Pos                   10                                                      /*!< FCE_KE CFG: XSEL Position               */\r
+#define FCE_KE_CFG_XSEL_Msk                   (0x01UL << FCE_KE_CFG_XSEL_Pos)                         /*!< FCE_KE CFG: XSEL Mask                   */\r
+\r
+/* ---------------------------------  FCE_KE_STS  --------------------------------- */\r
+#define FCE_KE_STS_CMF_Pos                    0                                                       /*!< FCE_KE STS: CMF Position                */\r
+#define FCE_KE_STS_CMF_Msk                    (0x01UL << FCE_KE_STS_CMF_Pos)                          /*!< FCE_KE STS: CMF Mask                    */\r
+#define FCE_KE_STS_CEF_Pos                    1                                                       /*!< FCE_KE STS: CEF Position                */\r
+#define FCE_KE_STS_CEF_Msk                    (0x01UL << FCE_KE_STS_CEF_Pos)                          /*!< FCE_KE STS: CEF Mask                    */\r
+#define FCE_KE_STS_LEF_Pos                    2                                                       /*!< FCE_KE STS: LEF Position                */\r
+#define FCE_KE_STS_LEF_Msk                    (0x01UL << FCE_KE_STS_LEF_Pos)                          /*!< FCE_KE STS: LEF Mask                    */\r
+#define FCE_KE_STS_BEF_Pos                    3                                                       /*!< FCE_KE STS: BEF Position                */\r
+#define FCE_KE_STS_BEF_Msk                    (0x01UL << FCE_KE_STS_BEF_Pos)                          /*!< FCE_KE STS: BEF Mask                    */\r
+\r
+/* --------------------------------  FCE_KE_LENGTH  ------------------------------- */\r
+#define FCE_KE_LENGTH_LENGTH_Pos              0                                                       /*!< FCE_KE LENGTH: LENGTH Position          */\r
+#define FCE_KE_LENGTH_LENGTH_Msk              (0x0000ffffUL << FCE_KE_LENGTH_LENGTH_Pos)              /*!< FCE_KE LENGTH: LENGTH Mask              */\r
+\r
+/* --------------------------------  FCE_KE_CHECK  -------------------------------- */\r
+#define FCE_KE_CHECK_CHECK_Pos                0                                                       /*!< FCE_KE CHECK: CHECK Position            */\r
+#define FCE_KE_CHECK_CHECK_Msk                (0xffffffffUL << FCE_KE_CHECK_CHECK_Pos)                /*!< FCE_KE CHECK: CHECK Mask                */\r
+\r
+/* ---------------------------------  FCE_KE_CRC  --------------------------------- */\r
+#define FCE_KE_CRC_CRC_Pos                    0                                                       /*!< FCE_KE CRC: CRC Position                */\r
+#define FCE_KE_CRC_CRC_Msk                    (0xffffffffUL << FCE_KE_CRC_CRC_Pos)                    /*!< FCE_KE CRC: CRC Mask                    */\r
+\r
+/* ---------------------------------  FCE_KE_CTR  --------------------------------- */\r
+#define FCE_KE_CTR_FCM_Pos                    0                                                       /*!< FCE_KE CTR: FCM Position                */\r
+#define FCE_KE_CTR_FCM_Msk                    (0x01UL << FCE_KE_CTR_FCM_Pos)                          /*!< FCE_KE CTR: FCM Mask                    */\r
+#define FCE_KE_CTR_FRM_CFG_Pos                1                                                       /*!< FCE_KE CTR: FRM_CFG Position            */\r
+#define FCE_KE_CTR_FRM_CFG_Msk                (0x01UL << FCE_KE_CTR_FRM_CFG_Pos)                      /*!< FCE_KE CTR: FRM_CFG Mask                */\r
+#define FCE_KE_CTR_FRM_CHECK_Pos              2                                                       /*!< FCE_KE CTR: FRM_CHECK Position          */\r
+#define FCE_KE_CTR_FRM_CHECK_Msk              (0x01UL << FCE_KE_CTR_FRM_CHECK_Pos)                    /*!< FCE_KE CTR: FRM_CHECK Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'PBA' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  PBA_STS  ---------------------------------- */\r
+#define PBA_STS_WERR_Pos                      0                                                       /*!< PBA STS: WERR Position                  */\r
+#define PBA_STS_WERR_Msk                      (0x01UL << PBA_STS_WERR_Pos)                            /*!< PBA STS: WERR Mask                      */\r
+\r
+/* ----------------------------------  PBA_WADDR  --------------------------------- */\r
+#define PBA_WADDR_WADDR_Pos                   0                                                       /*!< PBA WADDR: WADDR Position               */\r
+#define PBA_WADDR_WADDR_Msk                   (0xffffffffUL << PBA_WADDR_WADDR_Pos)                   /*!< PBA WADDR: WADDR Mask                   */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'FLASH' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  FLASH_ID  ---------------------------------- */\r
+#define FLASH_ID_MOD_REV_Pos                  0                                                       /*!< FLASH ID: MOD_REV Position              */\r
+#define FLASH_ID_MOD_REV_Msk                  (0x000000ffUL << FLASH_ID_MOD_REV_Pos)                  /*!< FLASH ID: MOD_REV Mask                  */\r
+#define FLASH_ID_MOD_TYPE_Pos                 8                                                       /*!< FLASH ID: MOD_TYPE Position             */\r
+#define FLASH_ID_MOD_TYPE_Msk                 (0x000000ffUL << FLASH_ID_MOD_TYPE_Pos)                 /*!< FLASH ID: MOD_TYPE Mask                 */\r
+#define FLASH_ID_MOD_NUMBER_Pos               16                                                      /*!< FLASH ID: MOD_NUMBER Position           */\r
+#define FLASH_ID_MOD_NUMBER_Msk               (0x0000ffffUL << FLASH_ID_MOD_NUMBER_Pos)               /*!< FLASH ID: MOD_NUMBER Mask               */\r
+\r
+/* ----------------------------------  FLASH_FSR  --------------------------------- */\r
+#define FLASH_FSR_PBUSY_Pos                   0                                                       /*!< FLASH FSR: PBUSY Position               */\r
+#define FLASH_FSR_PBUSY_Msk                   (0x01UL << FLASH_FSR_PBUSY_Pos)                         /*!< FLASH FSR: PBUSY Mask                   */\r
+#define FLASH_FSR_FABUSY_Pos                  1                                                       /*!< FLASH FSR: FABUSY Position              */\r
+#define FLASH_FSR_FABUSY_Msk                  (0x01UL << FLASH_FSR_FABUSY_Pos)                        /*!< FLASH FSR: FABUSY Mask                  */\r
+#define FLASH_FSR_PROG_Pos                    4                                                       /*!< FLASH FSR: PROG Position                */\r
+#define FLASH_FSR_PROG_Msk                    (0x01UL << FLASH_FSR_PROG_Pos)                          /*!< FLASH FSR: PROG Mask                    */\r
+#define FLASH_FSR_ERASE_Pos                   5                                                       /*!< FLASH FSR: ERASE Position               */\r
+#define FLASH_FSR_ERASE_Msk                   (0x01UL << FLASH_FSR_ERASE_Pos)                         /*!< FLASH FSR: ERASE Mask                   */\r
+#define FLASH_FSR_PFPAGE_Pos                  6                                                       /*!< FLASH FSR: PFPAGE Position              */\r
+#define FLASH_FSR_PFPAGE_Msk                  (0x01UL << FLASH_FSR_PFPAGE_Pos)                        /*!< FLASH FSR: PFPAGE Mask                  */\r
+#define FLASH_FSR_PFOPER_Pos                  8                                                       /*!< FLASH FSR: PFOPER Position              */\r
+#define FLASH_FSR_PFOPER_Msk                  (0x01UL << FLASH_FSR_PFOPER_Pos)                        /*!< FLASH FSR: PFOPER Mask                  */\r
+#define FLASH_FSR_SQER_Pos                    10                                                      /*!< FLASH FSR: SQER Position                */\r
+#define FLASH_FSR_SQER_Msk                    (0x01UL << FLASH_FSR_SQER_Pos)                          /*!< FLASH FSR: SQER Mask                    */\r
+#define FLASH_FSR_PROER_Pos                   11                                                      /*!< FLASH FSR: PROER Position               */\r
+#define FLASH_FSR_PROER_Msk                   (0x01UL << FLASH_FSR_PROER_Pos)                         /*!< FLASH FSR: PROER Mask                   */\r
+#define FLASH_FSR_PFSBER_Pos                  12                                                      /*!< FLASH FSR: PFSBER Position              */\r
+#define FLASH_FSR_PFSBER_Msk                  (0x01UL << FLASH_FSR_PFSBER_Pos)                        /*!< FLASH FSR: PFSBER Mask                  */\r
+#define FLASH_FSR_PFDBER_Pos                  14                                                      /*!< FLASH FSR: PFDBER Position              */\r
+#define FLASH_FSR_PFDBER_Msk                  (0x01UL << FLASH_FSR_PFDBER_Pos)                        /*!< FLASH FSR: PFDBER Mask                  */\r
+#define FLASH_FSR_PROIN_Pos                   16                                                      /*!< FLASH FSR: PROIN Position               */\r
+#define FLASH_FSR_PROIN_Msk                   (0x01UL << FLASH_FSR_PROIN_Pos)                         /*!< FLASH FSR: PROIN Mask                   */\r
+#define FLASH_FSR_RPROIN_Pos                  18                                                      /*!< FLASH FSR: RPROIN Position              */\r
+#define FLASH_FSR_RPROIN_Msk                  (0x01UL << FLASH_FSR_RPROIN_Pos)                        /*!< FLASH FSR: RPROIN Mask                  */\r
+#define FLASH_FSR_RPRODIS_Pos                 19                                                      /*!< FLASH FSR: RPRODIS Position             */\r
+#define FLASH_FSR_RPRODIS_Msk                 (0x01UL << FLASH_FSR_RPRODIS_Pos)                       /*!< FLASH FSR: RPRODIS Mask                 */\r
+#define FLASH_FSR_WPROIN0_Pos                 21                                                      /*!< FLASH FSR: WPROIN0 Position             */\r
+#define FLASH_FSR_WPROIN0_Msk                 (0x01UL << FLASH_FSR_WPROIN0_Pos)                       /*!< FLASH FSR: WPROIN0 Mask                 */\r
+#define FLASH_FSR_WPROIN1_Pos                 22                                                      /*!< FLASH FSR: WPROIN1 Position             */\r
+#define FLASH_FSR_WPROIN1_Msk                 (0x01UL << FLASH_FSR_WPROIN1_Pos)                       /*!< FLASH FSR: WPROIN1 Mask                 */\r
+#define FLASH_FSR_WPROIN2_Pos                 23                                                      /*!< FLASH FSR: WPROIN2 Position             */\r
+#define FLASH_FSR_WPROIN2_Msk                 (0x01UL << FLASH_FSR_WPROIN2_Pos)                       /*!< FLASH FSR: WPROIN2 Mask                 */\r
+#define FLASH_FSR_WPRODIS0_Pos                25                                                      /*!< FLASH FSR: WPRODIS0 Position            */\r
+#define FLASH_FSR_WPRODIS0_Msk                (0x01UL << FLASH_FSR_WPRODIS0_Pos)                      /*!< FLASH FSR: WPRODIS0 Mask                */\r
+#define FLASH_FSR_WPRODIS1_Pos                26                                                      /*!< FLASH FSR: WPRODIS1 Position            */\r
+#define FLASH_FSR_WPRODIS1_Msk                (0x01UL << FLASH_FSR_WPRODIS1_Pos)                      /*!< FLASH FSR: WPRODIS1 Mask                */\r
+#define FLASH_FSR_SLM_Pos                     28                                                      /*!< FLASH FSR: SLM Position                 */\r
+#define FLASH_FSR_SLM_Msk                     (0x01UL << FLASH_FSR_SLM_Pos)                           /*!< FLASH FSR: SLM Mask                     */\r
+#define FLASH_FSR_X_Pos                       30                                                      /*!< FLASH FSR: X Position                   */\r
+#define FLASH_FSR_X_Msk                       (0x01UL << FLASH_FSR_X_Pos)                             /*!< FLASH FSR: X Mask                       */\r
+#define FLASH_FSR_VER_Pos                     31                                                      /*!< FLASH FSR: VER Position                 */\r
+#define FLASH_FSR_VER_Msk                     (0x01UL << FLASH_FSR_VER_Pos)                           /*!< FLASH FSR: VER Mask                     */\r
+\r
+/* ---------------------------------  FLASH_FCON  --------------------------------- */\r
+#define FLASH_FCON_WSPFLASH_Pos               0                                                       /*!< FLASH FCON: WSPFLASH Position           */\r
+#define FLASH_FCON_WSPFLASH_Msk               (0x0fUL << FLASH_FCON_WSPFLASH_Pos)                     /*!< FLASH FCON: WSPFLASH Mask               */\r
+#define FLASH_FCON_WSECPF_Pos                 4                                                       /*!< FLASH FCON: WSECPF Position             */\r
+#define FLASH_FCON_WSECPF_Msk                 (0x01UL << FLASH_FCON_WSECPF_Pos)                       /*!< FLASH FCON: WSECPF Mask                 */\r
+#define FLASH_FCON_IDLE_Pos                   13                                                      /*!< FLASH FCON: IDLE Position               */\r
+#define FLASH_FCON_IDLE_Msk                   (0x01UL << FLASH_FCON_IDLE_Pos)                         /*!< FLASH FCON: IDLE Mask                   */\r
+#define FLASH_FCON_ESLDIS_Pos                 14                                                      /*!< FLASH FCON: ESLDIS Position             */\r
+#define FLASH_FCON_ESLDIS_Msk                 (0x01UL << FLASH_FCON_ESLDIS_Pos)                       /*!< FLASH FCON: ESLDIS Mask                 */\r
+#define FLASH_FCON_SLEEP_Pos                  15                                                      /*!< FLASH FCON: SLEEP Position              */\r
+#define FLASH_FCON_SLEEP_Msk                  (0x01UL << FLASH_FCON_SLEEP_Pos)                        /*!< FLASH FCON: SLEEP Mask                  */\r
+#define FLASH_FCON_RPA_Pos                    16                                                      /*!< FLASH FCON: RPA Position                */\r
+#define FLASH_FCON_RPA_Msk                    (0x01UL << FLASH_FCON_RPA_Pos)                          /*!< FLASH FCON: RPA Mask                    */\r
+#define FLASH_FCON_DCF_Pos                    17                                                      /*!< FLASH FCON: DCF Position                */\r
+#define FLASH_FCON_DCF_Msk                    (0x01UL << FLASH_FCON_DCF_Pos)                          /*!< FLASH FCON: DCF Mask                    */\r
+#define FLASH_FCON_DDF_Pos                    18                                                      /*!< FLASH FCON: DDF Position                */\r
+#define FLASH_FCON_DDF_Msk                    (0x01UL << FLASH_FCON_DDF_Pos)                          /*!< FLASH FCON: DDF Mask                    */\r
+#define FLASH_FCON_VOPERM_Pos                 24                                                      /*!< FLASH FCON: VOPERM Position             */\r
+#define FLASH_FCON_VOPERM_Msk                 (0x01UL << FLASH_FCON_VOPERM_Pos)                       /*!< FLASH FCON: VOPERM Mask                 */\r
+#define FLASH_FCON_SQERM_Pos                  25                                                      /*!< FLASH FCON: SQERM Position              */\r
+#define FLASH_FCON_SQERM_Msk                  (0x01UL << FLASH_FCON_SQERM_Pos)                        /*!< FLASH FCON: SQERM Mask                  */\r
+#define FLASH_FCON_PROERM_Pos                 26                                                      /*!< FLASH FCON: PROERM Position             */\r
+#define FLASH_FCON_PROERM_Msk                 (0x01UL << FLASH_FCON_PROERM_Pos)                       /*!< FLASH FCON: PROERM Mask                 */\r
+#define FLASH_FCON_PFSBERM_Pos                27                                                      /*!< FLASH FCON: PFSBERM Position            */\r
+#define FLASH_FCON_PFSBERM_Msk                (0x01UL << FLASH_FCON_PFSBERM_Pos)                      /*!< FLASH FCON: PFSBERM Mask                */\r
+#define FLASH_FCON_PFDBERM_Pos                29                                                      /*!< FLASH FCON: PFDBERM Position            */\r
+#define FLASH_FCON_PFDBERM_Msk                (0x01UL << FLASH_FCON_PFDBERM_Pos)                      /*!< FLASH FCON: PFDBERM Mask                */\r
+#define FLASH_FCON_EOBM_Pos                   31                                                      /*!< FLASH FCON: EOBM Position               */\r
+#define FLASH_FCON_EOBM_Msk                   (0x01UL << FLASH_FCON_EOBM_Pos)                         /*!< FLASH FCON: EOBM Mask                   */\r
+\r
+/* ---------------------------------  FLASH_MARP  --------------------------------- */\r
+#define FLASH_MARP_MARGIN_Pos                 0                                                       /*!< FLASH MARP: MARGIN Position             */\r
+#define FLASH_MARP_MARGIN_Msk                 (0x0fUL << FLASH_MARP_MARGIN_Pos)                       /*!< FLASH MARP: MARGIN Mask                 */\r
+#define FLASH_MARP_TRAPDIS_Pos                15                                                      /*!< FLASH MARP: TRAPDIS Position            */\r
+#define FLASH_MARP_TRAPDIS_Msk                (0x01UL << FLASH_MARP_TRAPDIS_Pos)                      /*!< FLASH MARP: TRAPDIS Mask                */\r
+\r
+/* --------------------------------  FLASH_PROCON0  ------------------------------- */\r
+#define FLASH_PROCON0_S0L_Pos                 0                                                       /*!< FLASH PROCON0: S0L Position             */\r
+#define FLASH_PROCON0_S0L_Msk                 (0x01UL << FLASH_PROCON0_S0L_Pos)                       /*!< FLASH PROCON0: S0L Mask                 */\r
+#define FLASH_PROCON0_S1L_Pos                 1                                                       /*!< FLASH PROCON0: S1L Position             */\r
+#define FLASH_PROCON0_S1L_Msk                 (0x01UL << FLASH_PROCON0_S1L_Pos)                       /*!< FLASH PROCON0: S1L Mask                 */\r
+#define FLASH_PROCON0_S2L_Pos                 2                                                       /*!< FLASH PROCON0: S2L Position             */\r
+#define FLASH_PROCON0_S2L_Msk                 (0x01UL << FLASH_PROCON0_S2L_Pos)                       /*!< FLASH PROCON0: S2L Mask                 */\r
+#define FLASH_PROCON0_S3L_Pos                 3                                                       /*!< FLASH PROCON0: S3L Position             */\r
+#define FLASH_PROCON0_S3L_Msk                 (0x01UL << FLASH_PROCON0_S3L_Pos)                       /*!< FLASH PROCON0: S3L Mask                 */\r
+#define FLASH_PROCON0_S4L_Pos                 4                                                       /*!< FLASH PROCON0: S4L Position             */\r
+#define FLASH_PROCON0_S4L_Msk                 (0x01UL << FLASH_PROCON0_S4L_Pos)                       /*!< FLASH PROCON0: S4L Mask                 */\r
+#define FLASH_PROCON0_S5L_Pos                 5                                                       /*!< FLASH PROCON0: S5L Position             */\r
+#define FLASH_PROCON0_S5L_Msk                 (0x01UL << FLASH_PROCON0_S5L_Pos)                       /*!< FLASH PROCON0: S5L Mask                 */\r
+#define FLASH_PROCON0_S6L_Pos                 6                                                       /*!< FLASH PROCON0: S6L Position             */\r
+#define FLASH_PROCON0_S6L_Msk                 (0x01UL << FLASH_PROCON0_S6L_Pos)                       /*!< FLASH PROCON0: S6L Mask                 */\r
+#define FLASH_PROCON0_S7L_Pos                 7                                                       /*!< FLASH PROCON0: S7L Position             */\r
+#define FLASH_PROCON0_S7L_Msk                 (0x01UL << FLASH_PROCON0_S7L_Pos)                       /*!< FLASH PROCON0: S7L Mask                 */\r
+#define FLASH_PROCON0_S8L_Pos                 8                                                       /*!< FLASH PROCON0: S8L Position             */\r
+#define FLASH_PROCON0_S8L_Msk                 (0x01UL << FLASH_PROCON0_S8L_Pos)                       /*!< FLASH PROCON0: S8L Mask                 */\r
+#define FLASH_PROCON0_S9L_Pos                 9                                                       /*!< FLASH PROCON0: S9L Position             */\r
+#define FLASH_PROCON0_S9L_Msk                 (0x01UL << FLASH_PROCON0_S9L_Pos)                       /*!< FLASH PROCON0: S9L Mask                 */\r
+#define FLASH_PROCON0_RPRO_Pos                15                                                      /*!< FLASH PROCON0: RPRO Position            */\r
+#define FLASH_PROCON0_RPRO_Msk                (0x01UL << FLASH_PROCON0_RPRO_Pos)                      /*!< FLASH PROCON0: RPRO Mask                */\r
+\r
+/* --------------------------------  FLASH_PROCON1  ------------------------------- */\r
+#define FLASH_PROCON1_S0L_Pos                 0                                                       /*!< FLASH PROCON1: S0L Position             */\r
+#define FLASH_PROCON1_S0L_Msk                 (0x01UL << FLASH_PROCON1_S0L_Pos)                       /*!< FLASH PROCON1: S0L Mask                 */\r
+#define FLASH_PROCON1_S1L_Pos                 1                                                       /*!< FLASH PROCON1: S1L Position             */\r
+#define FLASH_PROCON1_S1L_Msk                 (0x01UL << FLASH_PROCON1_S1L_Pos)                       /*!< FLASH PROCON1: S1L Mask                 */\r
+#define FLASH_PROCON1_S2L_Pos                 2                                                       /*!< FLASH PROCON1: S2L Position             */\r
+#define FLASH_PROCON1_S2L_Msk                 (0x01UL << FLASH_PROCON1_S2L_Pos)                       /*!< FLASH PROCON1: S2L Mask                 */\r
+#define FLASH_PROCON1_S3L_Pos                 3                                                       /*!< FLASH PROCON1: S3L Position             */\r
+#define FLASH_PROCON1_S3L_Msk                 (0x01UL << FLASH_PROCON1_S3L_Pos)                       /*!< FLASH PROCON1: S3L Mask                 */\r
+#define FLASH_PROCON1_S4L_Pos                 4                                                       /*!< FLASH PROCON1: S4L Position             */\r
+#define FLASH_PROCON1_S4L_Msk                 (0x01UL << FLASH_PROCON1_S4L_Pos)                       /*!< FLASH PROCON1: S4L Mask                 */\r
+#define FLASH_PROCON1_S5L_Pos                 5                                                       /*!< FLASH PROCON1: S5L Position             */\r
+#define FLASH_PROCON1_S5L_Msk                 (0x01UL << FLASH_PROCON1_S5L_Pos)                       /*!< FLASH PROCON1: S5L Mask                 */\r
+#define FLASH_PROCON1_S6L_Pos                 6                                                       /*!< FLASH PROCON1: S6L Position             */\r
+#define FLASH_PROCON1_S6L_Msk                 (0x01UL << FLASH_PROCON1_S6L_Pos)                       /*!< FLASH PROCON1: S6L Mask                 */\r
+#define FLASH_PROCON1_S7L_Pos                 7                                                       /*!< FLASH PROCON1: S7L Position             */\r
+#define FLASH_PROCON1_S7L_Msk                 (0x01UL << FLASH_PROCON1_S7L_Pos)                       /*!< FLASH PROCON1: S7L Mask                 */\r
+#define FLASH_PROCON1_S8L_Pos                 8                                                       /*!< FLASH PROCON1: S8L Position             */\r
+#define FLASH_PROCON1_S8L_Msk                 (0x01UL << FLASH_PROCON1_S8L_Pos)                       /*!< FLASH PROCON1: S8L Mask                 */\r
+#define FLASH_PROCON1_S9L_Pos                 9                                                       /*!< FLASH PROCON1: S9L Position             */\r
+#define FLASH_PROCON1_S9L_Msk                 (0x01UL << FLASH_PROCON1_S9L_Pos)                       /*!< FLASH PROCON1: S9L Mask                 */\r
+\r
+/* --------------------------------  FLASH_PROCON2  ------------------------------- */\r
+#define FLASH_PROCON2_S0ROM_Pos               0                                                       /*!< FLASH PROCON2: S0ROM Position           */\r
+#define FLASH_PROCON2_S0ROM_Msk               (0x01UL << FLASH_PROCON2_S0ROM_Pos)                     /*!< FLASH PROCON2: S0ROM Mask               */\r
+#define FLASH_PROCON2_S1ROM_Pos               1                                                       /*!< FLASH PROCON2: S1ROM Position           */\r
+#define FLASH_PROCON2_S1ROM_Msk               (0x01UL << FLASH_PROCON2_S1ROM_Pos)                     /*!< FLASH PROCON2: S1ROM Mask               */\r
+#define FLASH_PROCON2_S2ROM_Pos               2                                                       /*!< FLASH PROCON2: S2ROM Position           */\r
+#define FLASH_PROCON2_S2ROM_Msk               (0x01UL << FLASH_PROCON2_S2ROM_Pos)                     /*!< FLASH PROCON2: S2ROM Mask               */\r
+#define FLASH_PROCON2_S3ROM_Pos               3                                                       /*!< FLASH PROCON2: S3ROM Position           */\r
+#define FLASH_PROCON2_S3ROM_Msk               (0x01UL << FLASH_PROCON2_S3ROM_Pos)                     /*!< FLASH PROCON2: S3ROM Mask               */\r
+#define FLASH_PROCON2_S4ROM_Pos               4                                                       /*!< FLASH PROCON2: S4ROM Position           */\r
+#define FLASH_PROCON2_S4ROM_Msk               (0x01UL << FLASH_PROCON2_S4ROM_Pos)                     /*!< FLASH PROCON2: S4ROM Mask               */\r
+#define FLASH_PROCON2_S5ROM_Pos               5                                                       /*!< FLASH PROCON2: S5ROM Position           */\r
+#define FLASH_PROCON2_S5ROM_Msk               (0x01UL << FLASH_PROCON2_S5ROM_Pos)                     /*!< FLASH PROCON2: S5ROM Mask               */\r
+#define FLASH_PROCON2_S6ROM_Pos               6                                                       /*!< FLASH PROCON2: S6ROM Position           */\r
+#define FLASH_PROCON2_S6ROM_Msk               (0x01UL << FLASH_PROCON2_S6ROM_Pos)                     /*!< FLASH PROCON2: S6ROM Mask               */\r
+#define FLASH_PROCON2_S7ROM_Pos               7                                                       /*!< FLASH PROCON2: S7ROM Position           */\r
+#define FLASH_PROCON2_S7ROM_Msk               (0x01UL << FLASH_PROCON2_S7ROM_Pos)                     /*!< FLASH PROCON2: S7ROM Mask               */\r
+#define FLASH_PROCON2_S8ROM_Pos               8                                                       /*!< FLASH PROCON2: S8ROM Position           */\r
+#define FLASH_PROCON2_S8ROM_Msk               (0x01UL << FLASH_PROCON2_S8ROM_Pos)                     /*!< FLASH PROCON2: S8ROM Mask               */\r
+#define FLASH_PROCON2_S9ROM_Pos               9                                                       /*!< FLASH PROCON2: S9ROM Position           */\r
+#define FLASH_PROCON2_S9ROM_Msk               (0x01UL << FLASH_PROCON2_S9ROM_Pos)                     /*!< FLASH PROCON2: S9ROM Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'PREF' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PREF_PCON  --------------------------------- */\r
+#define PREF_PCON_IBYP_Pos                    0                                                       /*!< PREF PCON: IBYP Position                */\r
+#define PREF_PCON_IBYP_Msk                    (0x01UL << PREF_PCON_IBYP_Pos)                          /*!< PREF PCON: IBYP Mask                    */\r
+#define PREF_PCON_IINV_Pos                    1                                                       /*!< PREF PCON: IINV Position                */\r
+#define PREF_PCON_IINV_Msk                    (0x01UL << PREF_PCON_IINV_Pos)                          /*!< PREF PCON: IINV Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'PMU' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  PMU_ID  ----------------------------------- */\r
+#define PMU_ID_MOD_REV_Pos                    0                                                       /*!< PMU ID: MOD_REV Position                */\r
+#define PMU_ID_MOD_REV_Msk                    (0x000000ffUL << PMU_ID_MOD_REV_Pos)                    /*!< PMU ID: MOD_REV Mask                    */\r
+#define PMU_ID_MOD_TYPE_Pos                   8                                                       /*!< PMU ID: MOD_TYPE Position               */\r
+#define PMU_ID_MOD_TYPE_Msk                   (0x000000ffUL << PMU_ID_MOD_TYPE_Pos)                   /*!< PMU ID: MOD_TYPE Mask                   */\r
+#define PMU_ID_MOD_NUMBER_Pos                 16                                                      /*!< PMU ID: MOD_NUMBER Position             */\r
+#define PMU_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << PMU_ID_MOD_NUMBER_Pos)                 /*!< PMU ID: MOD_NUMBER Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'WDT' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  WDT_ID  ----------------------------------- */\r
+#define WDT_ID_MOD_REV_Pos                    0                                                       /*!< WDT ID: MOD_REV Position                */\r
+#define WDT_ID_MOD_REV_Msk                    (0x000000ffUL << WDT_ID_MOD_REV_Pos)                    /*!< WDT ID: MOD_REV Mask                    */\r
+#define WDT_ID_MOD_TYPE_Pos                   8                                                       /*!< WDT ID: MOD_TYPE Position               */\r
+#define WDT_ID_MOD_TYPE_Msk                   (0x000000ffUL << WDT_ID_MOD_TYPE_Pos)                   /*!< WDT ID: MOD_TYPE Mask                   */\r
+#define WDT_ID_MOD_NUMBER_Pos                 16                                                      /*!< WDT ID: MOD_NUMBER Position             */\r
+#define WDT_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << WDT_ID_MOD_NUMBER_Pos)                 /*!< WDT ID: MOD_NUMBER Mask                 */\r
+\r
+/* -----------------------------------  WDT_CTR  ---------------------------------- */\r
+#define WDT_CTR_ENB_Pos                       0                                                       /*!< WDT CTR: ENB Position                   */\r
+#define WDT_CTR_ENB_Msk                       (0x01UL << WDT_CTR_ENB_Pos)                             /*!< WDT CTR: ENB Mask                       */\r
+#define WDT_CTR_PRE_Pos                       1                                                       /*!< WDT CTR: PRE Position                   */\r
+#define WDT_CTR_PRE_Msk                       (0x01UL << WDT_CTR_PRE_Pos)                             /*!< WDT CTR: PRE Mask                       */\r
+#define WDT_CTR_DSP_Pos                       4                                                       /*!< WDT CTR: DSP Position                   */\r
+#define WDT_CTR_DSP_Msk                       (0x01UL << WDT_CTR_DSP_Pos)                             /*!< WDT CTR: DSP Mask                       */\r
+#define WDT_CTR_SPW_Pos                       8                                                       /*!< WDT CTR: SPW Position                   */\r
+#define WDT_CTR_SPW_Msk                       (0x000000ffUL << WDT_CTR_SPW_Pos)                       /*!< WDT CTR: SPW Mask                       */\r
+\r
+/* -----------------------------------  WDT_SRV  ---------------------------------- */\r
+#define WDT_SRV_SRV_Pos                       0                                                       /*!< WDT SRV: SRV Position                   */\r
+#define WDT_SRV_SRV_Msk                       (0xffffffffUL << WDT_SRV_SRV_Pos)                       /*!< WDT SRV: SRV Mask                       */\r
+\r
+/* -----------------------------------  WDT_TIM  ---------------------------------- */\r
+#define WDT_TIM_TIM_Pos                       0                                                       /*!< WDT TIM: TIM Position                   */\r
+#define WDT_TIM_TIM_Msk                       (0xffffffffUL << WDT_TIM_TIM_Pos)                       /*!< WDT TIM: TIM Mask                       */\r
+\r
+/* -----------------------------------  WDT_WLB  ---------------------------------- */\r
+#define WDT_WLB_WLB_Pos                       0                                                       /*!< WDT WLB: WLB Position                   */\r
+#define WDT_WLB_WLB_Msk                       (0xffffffffUL << WDT_WLB_WLB_Pos)                       /*!< WDT WLB: WLB Mask                       */\r
+\r
+/* -----------------------------------  WDT_WUB  ---------------------------------- */\r
+#define WDT_WUB_WUB_Pos                       0                                                       /*!< WDT WUB: WUB Position                   */\r
+#define WDT_WUB_WUB_Msk                       (0xffffffffUL << WDT_WUB_WUB_Pos)                       /*!< WDT WUB: WUB Mask                       */\r
+\r
+/* ---------------------------------  WDT_WDTSTS  --------------------------------- */\r
+#define WDT_WDTSTS_ALMS_Pos                   0                                                       /*!< WDT WDTSTS: ALMS Position               */\r
+#define WDT_WDTSTS_ALMS_Msk                   (0x01UL << WDT_WDTSTS_ALMS_Pos)                         /*!< WDT WDTSTS: ALMS Mask                   */\r
+\r
+/* ---------------------------------  WDT_WDTCLR  --------------------------------- */\r
+#define WDT_WDTCLR_ALMC_Pos                   0                                                       /*!< WDT WDTCLR: ALMC Position               */\r
+#define WDT_WDTCLR_ALMC_Msk                   (0x01UL << WDT_WDTCLR_ALMC_Pos)                         /*!< WDT WDTCLR: ALMC Mask                   */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'RTC' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  RTC_ID  ----------------------------------- */\r
+#define RTC_ID_MOD_REV_Pos                    0                                                       /*!< RTC ID: MOD_REV Position                */\r
+#define RTC_ID_MOD_REV_Msk                    (0x000000ffUL << RTC_ID_MOD_REV_Pos)                    /*!< RTC ID: MOD_REV Mask                    */\r
+#define RTC_ID_MOD_TYPE_Pos                   8                                                       /*!< RTC ID: MOD_TYPE Position               */\r
+#define RTC_ID_MOD_TYPE_Msk                   (0x000000ffUL << RTC_ID_MOD_TYPE_Pos)                   /*!< RTC ID: MOD_TYPE Mask                   */\r
+#define RTC_ID_MOD_NUMBER_Pos                 16                                                      /*!< RTC ID: MOD_NUMBER Position             */\r
+#define RTC_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << RTC_ID_MOD_NUMBER_Pos)                 /*!< RTC ID: MOD_NUMBER Mask                 */\r
+\r
+/* -----------------------------------  RTC_CTR  ---------------------------------- */\r
+#define RTC_CTR_ENB_Pos                       0                                                       /*!< RTC CTR: ENB Position                   */\r
+#define RTC_CTR_ENB_Msk                       (0x01UL << RTC_CTR_ENB_Pos)                             /*!< RTC CTR: ENB Mask                       */\r
+#define RTC_CTR_TAE_Pos                       2                                                       /*!< RTC CTR: TAE Position                   */\r
+#define RTC_CTR_TAE_Msk                       (0x01UL << RTC_CTR_TAE_Pos)                             /*!< RTC CTR: TAE Mask                       */\r
+#define RTC_CTR_ESEC_Pos                      8                                                       /*!< RTC CTR: ESEC Position                  */\r
+#define RTC_CTR_ESEC_Msk                      (0x01UL << RTC_CTR_ESEC_Pos)                            /*!< RTC CTR: ESEC Mask                      */\r
+#define RTC_CTR_EMIC_Pos                      9                                                       /*!< RTC CTR: EMIC Position                  */\r
+#define RTC_CTR_EMIC_Msk                      (0x01UL << RTC_CTR_EMIC_Pos)                            /*!< RTC CTR: EMIC Mask                      */\r
+#define RTC_CTR_EHOC_Pos                      10                                                      /*!< RTC CTR: EHOC Position                  */\r
+#define RTC_CTR_EHOC_Msk                      (0x01UL << RTC_CTR_EHOC_Pos)                            /*!< RTC CTR: EHOC Mask                      */\r
+#define RTC_CTR_EDAC_Pos                      11                                                      /*!< RTC CTR: EDAC Position                  */\r
+#define RTC_CTR_EDAC_Msk                      (0x01UL << RTC_CTR_EDAC_Pos)                            /*!< RTC CTR: EDAC Mask                      */\r
+#define RTC_CTR_EMOC_Pos                      13                                                      /*!< RTC CTR: EMOC Position                  */\r
+#define RTC_CTR_EMOC_Msk                      (0x01UL << RTC_CTR_EMOC_Pos)                            /*!< RTC CTR: EMOC Mask                      */\r
+#define RTC_CTR_EYEC_Pos                      14                                                      /*!< RTC CTR: EYEC Position                  */\r
+#define RTC_CTR_EYEC_Msk                      (0x01UL << RTC_CTR_EYEC_Pos)                            /*!< RTC CTR: EYEC Mask                      */\r
+#define RTC_CTR_DIV_Pos                       16                                                      /*!< RTC CTR: DIV Position                   */\r
+#define RTC_CTR_DIV_Msk                       (0x0000ffffUL << RTC_CTR_DIV_Pos)                       /*!< RTC CTR: DIV Mask                       */\r
+\r
+/* ---------------------------------  RTC_RAWSTAT  -------------------------------- */\r
+#define RTC_RAWSTAT_RPSE_Pos                  0                                                       /*!< RTC RAWSTAT: RPSE Position              */\r
+#define RTC_RAWSTAT_RPSE_Msk                  (0x01UL << RTC_RAWSTAT_RPSE_Pos)                        /*!< RTC RAWSTAT: RPSE Mask                  */\r
+#define RTC_RAWSTAT_RPMI_Pos                  1                                                       /*!< RTC RAWSTAT: RPMI Position              */\r
+#define RTC_RAWSTAT_RPMI_Msk                  (0x01UL << RTC_RAWSTAT_RPMI_Pos)                        /*!< RTC RAWSTAT: RPMI Mask                  */\r
+#define RTC_RAWSTAT_RPHO_Pos                  2                                                       /*!< RTC RAWSTAT: RPHO Position              */\r
+#define RTC_RAWSTAT_RPHO_Msk                  (0x01UL << RTC_RAWSTAT_RPHO_Pos)                        /*!< RTC RAWSTAT: RPHO Mask                  */\r
+#define RTC_RAWSTAT_RPDA_Pos                  3                                                       /*!< RTC RAWSTAT: RPDA Position              */\r
+#define RTC_RAWSTAT_RPDA_Msk                  (0x01UL << RTC_RAWSTAT_RPDA_Pos)                        /*!< RTC RAWSTAT: RPDA Mask                  */\r
+#define RTC_RAWSTAT_RPMO_Pos                  5                                                       /*!< RTC RAWSTAT: RPMO Position              */\r
+#define RTC_RAWSTAT_RPMO_Msk                  (0x01UL << RTC_RAWSTAT_RPMO_Pos)                        /*!< RTC RAWSTAT: RPMO Mask                  */\r
+#define RTC_RAWSTAT_RPYE_Pos                  6                                                       /*!< RTC RAWSTAT: RPYE Position              */\r
+#define RTC_RAWSTAT_RPYE_Msk                  (0x01UL << RTC_RAWSTAT_RPYE_Pos)                        /*!< RTC RAWSTAT: RPYE Mask                  */\r
+#define RTC_RAWSTAT_RAI_Pos                   8                                                       /*!< RTC RAWSTAT: RAI Position               */\r
+#define RTC_RAWSTAT_RAI_Msk                   (0x01UL << RTC_RAWSTAT_RAI_Pos)                         /*!< RTC RAWSTAT: RAI Mask                   */\r
+\r
+/* ----------------------------------  RTC_STSSR  --------------------------------- */\r
+#define RTC_STSSR_SPSE_Pos                    0                                                       /*!< RTC STSSR: SPSE Position                */\r
+#define RTC_STSSR_SPSE_Msk                    (0x01UL << RTC_STSSR_SPSE_Pos)                          /*!< RTC STSSR: SPSE Mask                    */\r
+#define RTC_STSSR_SPMI_Pos                    1                                                       /*!< RTC STSSR: SPMI Position                */\r
+#define RTC_STSSR_SPMI_Msk                    (0x01UL << RTC_STSSR_SPMI_Pos)                          /*!< RTC STSSR: SPMI Mask                    */\r
+#define RTC_STSSR_SPHO_Pos                    2                                                       /*!< RTC STSSR: SPHO Position                */\r
+#define RTC_STSSR_SPHO_Msk                    (0x01UL << RTC_STSSR_SPHO_Pos)                          /*!< RTC STSSR: SPHO Mask                    */\r
+#define RTC_STSSR_SPDA_Pos                    3                                                       /*!< RTC STSSR: SPDA Position                */\r
+#define RTC_STSSR_SPDA_Msk                    (0x01UL << RTC_STSSR_SPDA_Pos)                          /*!< RTC STSSR: SPDA Mask                    */\r
+#define RTC_STSSR_SPMO_Pos                    5                                                       /*!< RTC STSSR: SPMO Position                */\r
+#define RTC_STSSR_SPMO_Msk                    (0x01UL << RTC_STSSR_SPMO_Pos)                          /*!< RTC STSSR: SPMO Mask                    */\r
+#define RTC_STSSR_SPYE_Pos                    6                                                       /*!< RTC STSSR: SPYE Position                */\r
+#define RTC_STSSR_SPYE_Msk                    (0x01UL << RTC_STSSR_SPYE_Pos)                          /*!< RTC STSSR: SPYE Mask                    */\r
+#define RTC_STSSR_SAI_Pos                     8                                                       /*!< RTC STSSR: SAI Position                 */\r
+#define RTC_STSSR_SAI_Msk                     (0x01UL << RTC_STSSR_SAI_Pos)                           /*!< RTC STSSR: SAI Mask                     */\r
+\r
+/* ----------------------------------  RTC_MSKSR  --------------------------------- */\r
+#define RTC_MSKSR_MPSE_Pos                    0                                                       /*!< RTC MSKSR: MPSE Position                */\r
+#define RTC_MSKSR_MPSE_Msk                    (0x01UL << RTC_MSKSR_MPSE_Pos)                          /*!< RTC MSKSR: MPSE Mask                    */\r
+#define RTC_MSKSR_MPMI_Pos                    1                                                       /*!< RTC MSKSR: MPMI Position                */\r
+#define RTC_MSKSR_MPMI_Msk                    (0x01UL << RTC_MSKSR_MPMI_Pos)                          /*!< RTC MSKSR: MPMI Mask                    */\r
+#define RTC_MSKSR_MPHO_Pos                    2                                                       /*!< RTC MSKSR: MPHO Position                */\r
+#define RTC_MSKSR_MPHO_Msk                    (0x01UL << RTC_MSKSR_MPHO_Pos)                          /*!< RTC MSKSR: MPHO Mask                    */\r
+#define RTC_MSKSR_MPDA_Pos                    3                                                       /*!< RTC MSKSR: MPDA Position                */\r
+#define RTC_MSKSR_MPDA_Msk                    (0x01UL << RTC_MSKSR_MPDA_Pos)                          /*!< RTC MSKSR: MPDA Mask                    */\r
+#define RTC_MSKSR_MPMO_Pos                    5                                                       /*!< RTC MSKSR: MPMO Position                */\r
+#define RTC_MSKSR_MPMO_Msk                    (0x01UL << RTC_MSKSR_MPMO_Pos)                          /*!< RTC MSKSR: MPMO Mask                    */\r
+#define RTC_MSKSR_MPYE_Pos                    6                                                       /*!< RTC MSKSR: MPYE Position                */\r
+#define RTC_MSKSR_MPYE_Msk                    (0x01UL << RTC_MSKSR_MPYE_Pos)                          /*!< RTC MSKSR: MPYE Mask                    */\r
+#define RTC_MSKSR_MAI_Pos                     8                                                       /*!< RTC MSKSR: MAI Position                 */\r
+#define RTC_MSKSR_MAI_Msk                     (0x01UL << RTC_MSKSR_MAI_Pos)                           /*!< RTC MSKSR: MAI Mask                     */\r
+\r
+/* ----------------------------------  RTC_CLRSR  --------------------------------- */\r
+#define RTC_CLRSR_RPSE_Pos                    0                                                       /*!< RTC CLRSR: RPSE Position                */\r
+#define RTC_CLRSR_RPSE_Msk                    (0x01UL << RTC_CLRSR_RPSE_Pos)                          /*!< RTC CLRSR: RPSE Mask                    */\r
+#define RTC_CLRSR_RPMI_Pos                    1                                                       /*!< RTC CLRSR: RPMI Position                */\r
+#define RTC_CLRSR_RPMI_Msk                    (0x01UL << RTC_CLRSR_RPMI_Pos)                          /*!< RTC CLRSR: RPMI Mask                    */\r
+#define RTC_CLRSR_RPHO_Pos                    2                                                       /*!< RTC CLRSR: RPHO Position                */\r
+#define RTC_CLRSR_RPHO_Msk                    (0x01UL << RTC_CLRSR_RPHO_Pos)                          /*!< RTC CLRSR: RPHO Mask                    */\r
+#define RTC_CLRSR_RPDA_Pos                    3                                                       /*!< RTC CLRSR: RPDA Position                */\r
+#define RTC_CLRSR_RPDA_Msk                    (0x01UL << RTC_CLRSR_RPDA_Pos)                          /*!< RTC CLRSR: RPDA Mask                    */\r
+#define RTC_CLRSR_RPMO_Pos                    5                                                       /*!< RTC CLRSR: RPMO Position                */\r
+#define RTC_CLRSR_RPMO_Msk                    (0x01UL << RTC_CLRSR_RPMO_Pos)                          /*!< RTC CLRSR: RPMO Mask                    */\r
+#define RTC_CLRSR_RPYE_Pos                    6                                                       /*!< RTC CLRSR: RPYE Position                */\r
+#define RTC_CLRSR_RPYE_Msk                    (0x01UL << RTC_CLRSR_RPYE_Pos)                          /*!< RTC CLRSR: RPYE Mask                    */\r
+#define RTC_CLRSR_RAI_Pos                     8                                                       /*!< RTC CLRSR: RAI Position                 */\r
+#define RTC_CLRSR_RAI_Msk                     (0x01UL << RTC_CLRSR_RAI_Pos)                           /*!< RTC CLRSR: RAI Mask                     */\r
+\r
+/* ----------------------------------  RTC_ATIM0  --------------------------------- */\r
+#define RTC_ATIM0_ASE_Pos                     0                                                       /*!< RTC ATIM0: ASE Position                 */\r
+#define RTC_ATIM0_ASE_Msk                     (0x3fUL << RTC_ATIM0_ASE_Pos)                           /*!< RTC ATIM0: ASE Mask                     */\r
+#define RTC_ATIM0_AMI_Pos                     8                                                       /*!< RTC ATIM0: AMI Position                 */\r
+#define RTC_ATIM0_AMI_Msk                     (0x3fUL << RTC_ATIM0_AMI_Pos)                           /*!< RTC ATIM0: AMI Mask                     */\r
+#define RTC_ATIM0_AHO_Pos                     16                                                      /*!< RTC ATIM0: AHO Position                 */\r
+#define RTC_ATIM0_AHO_Msk                     (0x1fUL << RTC_ATIM0_AHO_Pos)                           /*!< RTC ATIM0: AHO Mask                     */\r
+#define RTC_ATIM0_ADA_Pos                     24                                                      /*!< RTC ATIM0: ADA Position                 */\r
+#define RTC_ATIM0_ADA_Msk                     (0x1fUL << RTC_ATIM0_ADA_Pos)                           /*!< RTC ATIM0: ADA Mask                     */\r
+\r
+/* ----------------------------------  RTC_ATIM1  --------------------------------- */\r
+#define RTC_ATIM1_AMO_Pos                     8                                                       /*!< RTC ATIM1: AMO Position                 */\r
+#define RTC_ATIM1_AMO_Msk                     (0x0fUL << RTC_ATIM1_AMO_Pos)                           /*!< RTC ATIM1: AMO Mask                     */\r
+#define RTC_ATIM1_AYE_Pos                     16                                                      /*!< RTC ATIM1: AYE Position                 */\r
+#define RTC_ATIM1_AYE_Msk                     (0x0000ffffUL << RTC_ATIM1_AYE_Pos)                     /*!< RTC ATIM1: AYE Mask                     */\r
+\r
+/* ----------------------------------  RTC_TIM0  ---------------------------------- */\r
+#define RTC_TIM0_SE_Pos                       0                                                       /*!< RTC TIM0: SE Position                   */\r
+#define RTC_TIM0_SE_Msk                       (0x3fUL << RTC_TIM0_SE_Pos)                             /*!< RTC TIM0: SE Mask                       */\r
+#define RTC_TIM0_MI_Pos                       8                                                       /*!< RTC TIM0: MI Position                   */\r
+#define RTC_TIM0_MI_Msk                       (0x3fUL << RTC_TIM0_MI_Pos)                             /*!< RTC TIM0: MI Mask                       */\r
+#define RTC_TIM0_HO_Pos                       16                                                      /*!< RTC TIM0: HO Position                   */\r
+#define RTC_TIM0_HO_Msk                       (0x1fUL << RTC_TIM0_HO_Pos)                             /*!< RTC TIM0: HO Mask                       */\r
+#define RTC_TIM0_DA_Pos                       24                                                      /*!< RTC TIM0: DA Position                   */\r
+#define RTC_TIM0_DA_Msk                       (0x1fUL << RTC_TIM0_DA_Pos)                             /*!< RTC TIM0: DA Mask                       */\r
+\r
+/* ----------------------------------  RTC_TIM1  ---------------------------------- */\r
+#define RTC_TIM1_DAWE_Pos                     0                                                       /*!< RTC TIM1: DAWE Position                 */\r
+#define RTC_TIM1_DAWE_Msk                     (0x07UL << RTC_TIM1_DAWE_Pos)                           /*!< RTC TIM1: DAWE Mask                     */\r
+#define RTC_TIM1_MO_Pos                       8                                                       /*!< RTC TIM1: MO Position                   */\r
+#define RTC_TIM1_MO_Msk                       (0x0fUL << RTC_TIM1_MO_Pos)                             /*!< RTC TIM1: MO Mask                       */\r
+#define RTC_TIM1_YE_Pos                       16                                                      /*!< RTC TIM1: YE Position                   */\r
+#define RTC_TIM1_YE_Msk                       (0x0000ffffUL << RTC_TIM1_YE_Pos)                       /*!< RTC TIM1: YE Mask                       */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_CLK' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_CLK_CLKSTAT  ------------------------------ */\r
+#define SCU_CLK_CLKSTAT_USBCST_Pos            0                                                       /*!< SCU_CLK CLKSTAT: USBCST Position        */\r
+#define SCU_CLK_CLKSTAT_USBCST_Msk            (0x01UL << SCU_CLK_CLKSTAT_USBCST_Pos)                  /*!< SCU_CLK CLKSTAT: USBCST Mask            */\r
+#define SCU_CLK_CLKSTAT_ETH0CST_Pos           2                                                       /*!< SCU_CLK CLKSTAT: ETH0CST Position       */\r
+#define SCU_CLK_CLKSTAT_ETH0CST_Msk           (0x01UL << SCU_CLK_CLKSTAT_ETH0CST_Pos)                 /*!< SCU_CLK CLKSTAT: ETH0CST Mask           */\r
+#define SCU_CLK_CLKSTAT_CCUCST_Pos            4                                                       /*!< SCU_CLK CLKSTAT: CCUCST Position        */\r
+#define SCU_CLK_CLKSTAT_CCUCST_Msk            (0x01UL << SCU_CLK_CLKSTAT_CCUCST_Pos)                  /*!< SCU_CLK CLKSTAT: CCUCST Mask            */\r
+#define SCU_CLK_CLKSTAT_WDTCST_Pos            5                                                       /*!< SCU_CLK CLKSTAT: WDTCST Position        */\r
+#define SCU_CLK_CLKSTAT_WDTCST_Msk            (0x01UL << SCU_CLK_CLKSTAT_WDTCST_Pos)                  /*!< SCU_CLK CLKSTAT: WDTCST Mask            */\r
+\r
+/* -------------------------------  SCU_CLK_CLKSET  ------------------------------- */\r
+#define SCU_CLK_CLKSET_USBCEN_Pos             0                                                       /*!< SCU_CLK CLKSET: USBCEN Position         */\r
+#define SCU_CLK_CLKSET_USBCEN_Msk             (0x01UL << SCU_CLK_CLKSET_USBCEN_Pos)                   /*!< SCU_CLK CLKSET: USBCEN Mask             */\r
+#define SCU_CLK_CLKSET_ETH0CEN_Pos            2                                                       /*!< SCU_CLK CLKSET: ETH0CEN Position        */\r
+#define SCU_CLK_CLKSET_ETH0CEN_Msk            (0x01UL << SCU_CLK_CLKSET_ETH0CEN_Pos)                  /*!< SCU_CLK CLKSET: ETH0CEN Mask            */\r
+#define SCU_CLK_CLKSET_CCUCEN_Pos             4                                                       /*!< SCU_CLK CLKSET: CCUCEN Position         */\r
+#define SCU_CLK_CLKSET_CCUCEN_Msk             (0x01UL << SCU_CLK_CLKSET_CCUCEN_Pos)                   /*!< SCU_CLK CLKSET: CCUCEN Mask             */\r
+#define SCU_CLK_CLKSET_WDTCEN_Pos             5                                                       /*!< SCU_CLK CLKSET: WDTCEN Position         */\r
+#define SCU_CLK_CLKSET_WDTCEN_Msk             (0x01UL << SCU_CLK_CLKSET_WDTCEN_Pos)                   /*!< SCU_CLK CLKSET: WDTCEN Mask             */\r
+\r
+/* -------------------------------  SCU_CLK_CLKCLR  ------------------------------- */\r
+#define SCU_CLK_CLKCLR_USBCDI_Pos             0                                                       /*!< SCU_CLK CLKCLR: USBCDI Position         */\r
+#define SCU_CLK_CLKCLR_USBCDI_Msk             (0x01UL << SCU_CLK_CLKCLR_USBCDI_Pos)                   /*!< SCU_CLK CLKCLR: USBCDI Mask             */\r
+#define SCU_CLK_CLKCLR_ETH0CDI_Pos            2                                                       /*!< SCU_CLK CLKCLR: ETH0CDI Position        */\r
+#define SCU_CLK_CLKCLR_ETH0CDI_Msk            (0x01UL << SCU_CLK_CLKCLR_ETH0CDI_Pos)                  /*!< SCU_CLK CLKCLR: ETH0CDI Mask            */\r
+#define SCU_CLK_CLKCLR_CCUCDI_Pos             4                                                       /*!< SCU_CLK CLKCLR: CCUCDI Position         */\r
+#define SCU_CLK_CLKCLR_CCUCDI_Msk             (0x01UL << SCU_CLK_CLKCLR_CCUCDI_Pos)                   /*!< SCU_CLK CLKCLR: CCUCDI Mask             */\r
+#define SCU_CLK_CLKCLR_WDTCDI_Pos             5                                                       /*!< SCU_CLK CLKCLR: WDTCDI Position         */\r
+#define SCU_CLK_CLKCLR_WDTCDI_Msk             (0x01UL << SCU_CLK_CLKCLR_WDTCDI_Pos)                   /*!< SCU_CLK CLKCLR: WDTCDI Mask             */\r
+\r
+/* ------------------------------  SCU_CLK_SYSCLKCR  ------------------------------ */\r
+#define SCU_CLK_SYSCLKCR_SYSDIV_Pos           0                                                       /*!< SCU_CLK SYSCLKCR: SYSDIV Position       */\r
+#define SCU_CLK_SYSCLKCR_SYSDIV_Msk           (0x000000ffUL << SCU_CLK_SYSCLKCR_SYSDIV_Pos)           /*!< SCU_CLK SYSCLKCR: SYSDIV Mask           */\r
+#define SCU_CLK_SYSCLKCR_SYSSEL_Pos           16                                                      /*!< SCU_CLK SYSCLKCR: SYSSEL Position       */\r
+#define SCU_CLK_SYSCLKCR_SYSSEL_Msk           (0x01UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos)                 /*!< SCU_CLK SYSCLKCR: SYSSEL Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CPUCLKCR  ------------------------------ */\r
+#define SCU_CLK_CPUCLKCR_CPUDIV_Pos           0                                                       /*!< SCU_CLK CPUCLKCR: CPUDIV Position       */\r
+#define SCU_CLK_CPUCLKCR_CPUDIV_Msk           (0x01UL << SCU_CLK_CPUCLKCR_CPUDIV_Pos)                 /*!< SCU_CLK CPUCLKCR: CPUDIV Mask           */\r
+\r
+/* -------------------------------  SCU_CLK_PBCLKCR  ------------------------------ */\r
+#define SCU_CLK_PBCLKCR_PBDIV_Pos             0                                                       /*!< SCU_CLK PBCLKCR: PBDIV Position         */\r
+#define SCU_CLK_PBCLKCR_PBDIV_Msk             (0x01UL << SCU_CLK_PBCLKCR_PBDIV_Pos)                   /*!< SCU_CLK PBCLKCR: PBDIV Mask             */\r
+\r
+/* ------------------------------  SCU_CLK_USBCLKCR  ------------------------------ */\r
+#define SCU_CLK_USBCLKCR_USBDIV_Pos           0                                                       /*!< SCU_CLK USBCLKCR: USBDIV Position       */\r
+#define SCU_CLK_USBCLKCR_USBDIV_Msk           (0x07UL << SCU_CLK_USBCLKCR_USBDIV_Pos)                 /*!< SCU_CLK USBCLKCR: USBDIV Mask           */\r
+#define SCU_CLK_USBCLKCR_USBSEL_Pos           16                                                      /*!< SCU_CLK USBCLKCR: USBSEL Position       */\r
+#define SCU_CLK_USBCLKCR_USBSEL_Msk           (0x01UL << SCU_CLK_USBCLKCR_USBSEL_Pos)                 /*!< SCU_CLK USBCLKCR: USBSEL Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CCUCLKCR  ------------------------------ */\r
+#define SCU_CLK_CCUCLKCR_CCUDIV_Pos           0                                                       /*!< SCU_CLK CCUCLKCR: CCUDIV Position       */\r
+#define SCU_CLK_CCUCLKCR_CCUDIV_Msk           (0x01UL << SCU_CLK_CCUCLKCR_CCUDIV_Pos)                 /*!< SCU_CLK CCUCLKCR: CCUDIV Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_WDTCLKCR  ------------------------------ */\r
+#define SCU_CLK_WDTCLKCR_WDTDIV_Pos           0                                                       /*!< SCU_CLK WDTCLKCR: WDTDIV Position       */\r
+#define SCU_CLK_WDTCLKCR_WDTDIV_Msk           (0x000000ffUL << SCU_CLK_WDTCLKCR_WDTDIV_Pos)           /*!< SCU_CLK WDTCLKCR: WDTDIV Mask           */\r
+#define SCU_CLK_WDTCLKCR_WDTSEL_Pos           16                                                      /*!< SCU_CLK WDTCLKCR: WDTSEL Position       */\r
+#define SCU_CLK_WDTCLKCR_WDTSEL_Msk           (0x03UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos)                 /*!< SCU_CLK WDTCLKCR: WDTSEL Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_EXTCLKCR  ------------------------------ */\r
+#define SCU_CLK_EXTCLKCR_ECKSEL_Pos           0                                                       /*!< SCU_CLK EXTCLKCR: ECKSEL Position       */\r
+#define SCU_CLK_EXTCLKCR_ECKSEL_Msk           (0x07UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos)                 /*!< SCU_CLK EXTCLKCR: ECKSEL Mask           */\r
+#define SCU_CLK_EXTCLKCR_ECKDIV_Pos           16                                                      /*!< SCU_CLK EXTCLKCR: ECKDIV Position       */\r
+#define SCU_CLK_EXTCLKCR_ECKDIV_Msk           (0x000001ffUL << SCU_CLK_EXTCLKCR_ECKDIV_Pos)           /*!< SCU_CLK EXTCLKCR: ECKDIV Mask           */\r
+\r
+/* -----------------------------  SCU_CLK_MLINKCLKCR  ----------------------------- */\r
+#define SCU_CLK_MLINKCLKCR_SYSDIV_Pos         0                                                       /*!< SCU_CLK MLINKCLKCR: SYSDIV Position     */\r
+#define SCU_CLK_MLINKCLKCR_SYSDIV_Msk         (0x000000ffUL << SCU_CLK_MLINKCLKCR_SYSDIV_Pos)         /*!< SCU_CLK MLINKCLKCR: SYSDIV Mask         */\r
+#define SCU_CLK_MLINKCLKCR_SYSSEL_Pos         8                                                       /*!< SCU_CLK MLINKCLKCR: SYSSEL Position     */\r
+#define SCU_CLK_MLINKCLKCR_SYSSEL_Msk         (0x01UL << SCU_CLK_MLINKCLKCR_SYSSEL_Pos)               /*!< SCU_CLK MLINKCLKCR: SYSSEL Mask         */\r
+#define SCU_CLK_MLINKCLKCR_CPUDIV_Pos         10                                                      /*!< SCU_CLK MLINKCLKCR: CPUDIV Position     */\r
+#define SCU_CLK_MLINKCLKCR_CPUDIV_Msk         (0x01UL << SCU_CLK_MLINKCLKCR_CPUDIV_Pos)               /*!< SCU_CLK MLINKCLKCR: CPUDIV Mask         */\r
+#define SCU_CLK_MLINKCLKCR_PBDIV_Pos          12                                                      /*!< SCU_CLK MLINKCLKCR: PBDIV Position      */\r
+#define SCU_CLK_MLINKCLKCR_PBDIV_Msk          (0x01UL << SCU_CLK_MLINKCLKCR_PBDIV_Pos)                /*!< SCU_CLK MLINKCLKCR: PBDIV Mask          */\r
+#define SCU_CLK_MLINKCLKCR_CCUDIV_Pos         14                                                      /*!< SCU_CLK MLINKCLKCR: CCUDIV Position     */\r
+#define SCU_CLK_MLINKCLKCR_CCUDIV_Msk         (0x01UL << SCU_CLK_MLINKCLKCR_CCUDIV_Pos)               /*!< SCU_CLK MLINKCLKCR: CCUDIV Mask         */\r
+#define SCU_CLK_MLINKCLKCR_WDTDIV_Pos         16                                                      /*!< SCU_CLK MLINKCLKCR: WDTDIV Position     */\r
+#define SCU_CLK_MLINKCLKCR_WDTDIV_Msk         (0x000000ffUL << SCU_CLK_MLINKCLKCR_WDTDIV_Pos)         /*!< SCU_CLK MLINKCLKCR: WDTDIV Mask         */\r
+#define SCU_CLK_MLINKCLKCR_WDTSEL_Pos         24                                                      /*!< SCU_CLK MLINKCLKCR: WDTSEL Position     */\r
+#define SCU_CLK_MLINKCLKCR_WDTSEL_Msk         (0x03UL << SCU_CLK_MLINKCLKCR_WDTSEL_Pos)               /*!< SCU_CLK MLINKCLKCR: WDTSEL Mask         */\r
+\r
+/* -------------------------------  SCU_CLK_SLEEPCR  ------------------------------ */\r
+#define SCU_CLK_SLEEPCR_SYSSEL_Pos            0                                                       /*!< SCU_CLK SLEEPCR: SYSSEL Position        */\r
+#define SCU_CLK_SLEEPCR_SYSSEL_Msk            (0x01UL << SCU_CLK_SLEEPCR_SYSSEL_Pos)                  /*!< SCU_CLK SLEEPCR: SYSSEL Mask            */\r
+#define SCU_CLK_SLEEPCR_USBCR_Pos             16                                                      /*!< SCU_CLK SLEEPCR: USBCR Position         */\r
+#define SCU_CLK_SLEEPCR_USBCR_Msk             (0x01UL << SCU_CLK_SLEEPCR_USBCR_Pos)                   /*!< SCU_CLK SLEEPCR: USBCR Mask             */\r
+#define SCU_CLK_SLEEPCR_ETH0CR_Pos            18                                                      /*!< SCU_CLK SLEEPCR: ETH0CR Position        */\r
+#define SCU_CLK_SLEEPCR_ETH0CR_Msk            (0x01UL << SCU_CLK_SLEEPCR_ETH0CR_Pos)                  /*!< SCU_CLK SLEEPCR: ETH0CR Mask            */\r
+#define SCU_CLK_SLEEPCR_CCUCR_Pos             20                                                      /*!< SCU_CLK SLEEPCR: CCUCR Position         */\r
+#define SCU_CLK_SLEEPCR_CCUCR_Msk             (0x01UL << SCU_CLK_SLEEPCR_CCUCR_Pos)                   /*!< SCU_CLK SLEEPCR: CCUCR Mask             */\r
+#define SCU_CLK_SLEEPCR_WDTCR_Pos             21                                                      /*!< SCU_CLK SLEEPCR: WDTCR Position         */\r
+#define SCU_CLK_SLEEPCR_WDTCR_Msk             (0x01UL << SCU_CLK_SLEEPCR_WDTCR_Pos)                   /*!< SCU_CLK SLEEPCR: WDTCR Mask             */\r
+\r
+/* ------------------------------  SCU_CLK_DSLEEPCR  ------------------------------ */\r
+#define SCU_CLK_DSLEEPCR_SYSSEL_Pos           0                                                       /*!< SCU_CLK DSLEEPCR: SYSSEL Position       */\r
+#define SCU_CLK_DSLEEPCR_SYSSEL_Msk           (0x01UL << SCU_CLK_DSLEEPCR_SYSSEL_Pos)                 /*!< SCU_CLK DSLEEPCR: SYSSEL Mask           */\r
+#define SCU_CLK_DSLEEPCR_FPDN_Pos             11                                                      /*!< SCU_CLK DSLEEPCR: FPDN Position         */\r
+#define SCU_CLK_DSLEEPCR_FPDN_Msk             (0x01UL << SCU_CLK_DSLEEPCR_FPDN_Pos)                   /*!< SCU_CLK DSLEEPCR: FPDN Mask             */\r
+#define SCU_CLK_DSLEEPCR_PLLPDN_Pos           12                                                      /*!< SCU_CLK DSLEEPCR: PLLPDN Position       */\r
+#define SCU_CLK_DSLEEPCR_PLLPDN_Msk           (0x01UL << SCU_CLK_DSLEEPCR_PLLPDN_Pos)                 /*!< SCU_CLK DSLEEPCR: PLLPDN Mask           */\r
+#define SCU_CLK_DSLEEPCR_VCOPDN_Pos           13                                                      /*!< SCU_CLK DSLEEPCR: VCOPDN Position       */\r
+#define SCU_CLK_DSLEEPCR_VCOPDN_Msk           (0x01UL << SCU_CLK_DSLEEPCR_VCOPDN_Pos)                 /*!< SCU_CLK DSLEEPCR: VCOPDN Mask           */\r
+#define SCU_CLK_DSLEEPCR_USBCR_Pos            16                                                      /*!< SCU_CLK DSLEEPCR: USBCR Position        */\r
+#define SCU_CLK_DSLEEPCR_USBCR_Msk            (0x01UL << SCU_CLK_DSLEEPCR_USBCR_Pos)                  /*!< SCU_CLK DSLEEPCR: USBCR Mask            */\r
+#define SCU_CLK_DSLEEPCR_ETH0CR_Pos           18                                                      /*!< SCU_CLK DSLEEPCR: ETH0CR Position       */\r
+#define SCU_CLK_DSLEEPCR_ETH0CR_Msk           (0x01UL << SCU_CLK_DSLEEPCR_ETH0CR_Pos)                 /*!< SCU_CLK DSLEEPCR: ETH0CR Mask           */\r
+#define SCU_CLK_DSLEEPCR_CCUCR_Pos            20                                                      /*!< SCU_CLK DSLEEPCR: CCUCR Position        */\r
+#define SCU_CLK_DSLEEPCR_CCUCR_Msk            (0x01UL << SCU_CLK_DSLEEPCR_CCUCR_Pos)                  /*!< SCU_CLK DSLEEPCR: CCUCR Mask            */\r
+#define SCU_CLK_DSLEEPCR_WDTCR_Pos            21                                                      /*!< SCU_CLK DSLEEPCR: WDTCR Position        */\r
+#define SCU_CLK_DSLEEPCR_WDTCR_Msk            (0x01UL << SCU_CLK_DSLEEPCR_WDTCR_Pos)                  /*!< SCU_CLK DSLEEPCR: WDTCR Mask            */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSTAT0  ----------------------------- */\r
+#define SCU_CLK_CGATSTAT0_VADC_Pos            0                                                       /*!< SCU_CLK CGATSTAT0: VADC Position        */\r
+#define SCU_CLK_CGATSTAT0_VADC_Msk            (0x01UL << SCU_CLK_CGATSTAT0_VADC_Pos)                  /*!< SCU_CLK CGATSTAT0: VADC Mask            */\r
+#define SCU_CLK_CGATSTAT0_DSD_Pos             1                                                       /*!< SCU_CLK CGATSTAT0: DSD Position         */\r
+#define SCU_CLK_CGATSTAT0_DSD_Msk             (0x01UL << SCU_CLK_CGATSTAT0_DSD_Pos)                   /*!< SCU_CLK CGATSTAT0: DSD Mask             */\r
+#define SCU_CLK_CGATSTAT0_CCU40_Pos           2                                                       /*!< SCU_CLK CGATSTAT0: CCU40 Position       */\r
+#define SCU_CLK_CGATSTAT0_CCU40_Msk           (0x01UL << SCU_CLK_CGATSTAT0_CCU40_Pos)                 /*!< SCU_CLK CGATSTAT0: CCU40 Mask           */\r
+#define SCU_CLK_CGATSTAT0_CCU41_Pos           3                                                       /*!< SCU_CLK CGATSTAT0: CCU41 Position       */\r
+#define SCU_CLK_CGATSTAT0_CCU41_Msk           (0x01UL << SCU_CLK_CGATSTAT0_CCU41_Pos)                 /*!< SCU_CLK CGATSTAT0: CCU41 Mask           */\r
+#define SCU_CLK_CGATSTAT0_CCU42_Pos           4                                                       /*!< SCU_CLK CGATSTAT0: CCU42 Position       */\r
+#define SCU_CLK_CGATSTAT0_CCU42_Msk           (0x01UL << SCU_CLK_CGATSTAT0_CCU42_Pos)                 /*!< SCU_CLK CGATSTAT0: CCU42 Mask           */\r
+#define SCU_CLK_CGATSTAT0_CCU80_Pos           7                                                       /*!< SCU_CLK CGATSTAT0: CCU80 Position       */\r
+#define SCU_CLK_CGATSTAT0_CCU80_Msk           (0x01UL << SCU_CLK_CGATSTAT0_CCU80_Pos)                 /*!< SCU_CLK CGATSTAT0: CCU80 Mask           */\r
+#define SCU_CLK_CGATSTAT0_CCU81_Pos           8                                                       /*!< SCU_CLK CGATSTAT0: CCU81 Position       */\r
+#define SCU_CLK_CGATSTAT0_CCU81_Msk           (0x01UL << SCU_CLK_CGATSTAT0_CCU81_Pos)                 /*!< SCU_CLK CGATSTAT0: CCU81 Mask           */\r
+#define SCU_CLK_CGATSTAT0_POSIF0_Pos          9                                                       /*!< SCU_CLK CGATSTAT0: POSIF0 Position      */\r
+#define SCU_CLK_CGATSTAT0_POSIF0_Msk          (0x01UL << SCU_CLK_CGATSTAT0_POSIF0_Pos)                /*!< SCU_CLK CGATSTAT0: POSIF0 Mask          */\r
+#define SCU_CLK_CGATSTAT0_POSIF1_Pos          10                                                      /*!< SCU_CLK CGATSTAT0: POSIF1 Position      */\r
+#define SCU_CLK_CGATSTAT0_POSIF1_Msk          (0x01UL << SCU_CLK_CGATSTAT0_POSIF1_Pos)                /*!< SCU_CLK CGATSTAT0: POSIF1 Mask          */\r
+#define SCU_CLK_CGATSTAT0_USIC0_Pos           11                                                      /*!< SCU_CLK CGATSTAT0: USIC0 Position       */\r
+#define SCU_CLK_CGATSTAT0_USIC0_Msk           (0x01UL << SCU_CLK_CGATSTAT0_USIC0_Pos)                 /*!< SCU_CLK CGATSTAT0: USIC0 Mask           */\r
+#define SCU_CLK_CGATSTAT0_ERU1_Pos            16                                                      /*!< SCU_CLK CGATSTAT0: ERU1 Position        */\r
+#define SCU_CLK_CGATSTAT0_ERU1_Msk            (0x01UL << SCU_CLK_CGATSTAT0_ERU1_Pos)                  /*!< SCU_CLK CGATSTAT0: ERU1 Mask            */\r
+#define SCU_CLK_CGATSTAT0_HRPWM0_Pos          23                                                      /*!< SCU_CLK CGATSTAT0: HRPWM0 Position      */\r
+#define SCU_CLK_CGATSTAT0_HRPWM0_Msk          (0x01UL << SCU_CLK_CGATSTAT0_HRPWM0_Pos)                /*!< SCU_CLK CGATSTAT0: HRPWM0 Mask          */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSET0  ------------------------------ */\r
+#define SCU_CLK_CGATSET0_VADC_Pos             0                                                       /*!< SCU_CLK CGATSET0: VADC Position         */\r
+#define SCU_CLK_CGATSET0_VADC_Msk             (0x01UL << SCU_CLK_CGATSET0_VADC_Pos)                   /*!< SCU_CLK CGATSET0: VADC Mask             */\r
+#define SCU_CLK_CGATSET0_DSD_Pos              1                                                       /*!< SCU_CLK CGATSET0: DSD Position          */\r
+#define SCU_CLK_CGATSET0_DSD_Msk              (0x01UL << SCU_CLK_CGATSET0_DSD_Pos)                    /*!< SCU_CLK CGATSET0: DSD Mask              */\r
+#define SCU_CLK_CGATSET0_CCU40_Pos            2                                                       /*!< SCU_CLK CGATSET0: CCU40 Position        */\r
+#define SCU_CLK_CGATSET0_CCU40_Msk            (0x01UL << SCU_CLK_CGATSET0_CCU40_Pos)                  /*!< SCU_CLK CGATSET0: CCU40 Mask            */\r
+#define SCU_CLK_CGATSET0_CCU41_Pos            3                                                       /*!< SCU_CLK CGATSET0: CCU41 Position        */\r
+#define SCU_CLK_CGATSET0_CCU41_Msk            (0x01UL << SCU_CLK_CGATSET0_CCU41_Pos)                  /*!< SCU_CLK CGATSET0: CCU41 Mask            */\r
+#define SCU_CLK_CGATSET0_CCU42_Pos            4                                                       /*!< SCU_CLK CGATSET0: CCU42 Position        */\r
+#define SCU_CLK_CGATSET0_CCU42_Msk            (0x01UL << SCU_CLK_CGATSET0_CCU42_Pos)                  /*!< SCU_CLK CGATSET0: CCU42 Mask            */\r
+#define SCU_CLK_CGATSET0_CCU80_Pos            7                                                       /*!< SCU_CLK CGATSET0: CCU80 Position        */\r
+#define SCU_CLK_CGATSET0_CCU80_Msk            (0x01UL << SCU_CLK_CGATSET0_CCU80_Pos)                  /*!< SCU_CLK CGATSET0: CCU80 Mask            */\r
+#define SCU_CLK_CGATSET0_CCU81_Pos            8                                                       /*!< SCU_CLK CGATSET0: CCU81 Position        */\r
+#define SCU_CLK_CGATSET0_CCU81_Msk            (0x01UL << SCU_CLK_CGATSET0_CCU81_Pos)                  /*!< SCU_CLK CGATSET0: CCU81 Mask            */\r
+#define SCU_CLK_CGATSET0_POSIF0_Pos           9                                                       /*!< SCU_CLK CGATSET0: POSIF0 Position       */\r
+#define SCU_CLK_CGATSET0_POSIF0_Msk           (0x01UL << SCU_CLK_CGATSET0_POSIF0_Pos)                 /*!< SCU_CLK CGATSET0: POSIF0 Mask           */\r
+#define SCU_CLK_CGATSET0_POSIF1_Pos           10                                                      /*!< SCU_CLK CGATSET0: POSIF1 Position       */\r
+#define SCU_CLK_CGATSET0_POSIF1_Msk           (0x01UL << SCU_CLK_CGATSET0_POSIF1_Pos)                 /*!< SCU_CLK CGATSET0: POSIF1 Mask           */\r
+#define SCU_CLK_CGATSET0_USIC0_Pos            11                                                      /*!< SCU_CLK CGATSET0: USIC0 Position        */\r
+#define SCU_CLK_CGATSET0_USIC0_Msk            (0x01UL << SCU_CLK_CGATSET0_USIC0_Pos)                  /*!< SCU_CLK CGATSET0: USIC0 Mask            */\r
+#define SCU_CLK_CGATSET0_ERU1_Pos             16                                                      /*!< SCU_CLK CGATSET0: ERU1 Position         */\r
+#define SCU_CLK_CGATSET0_ERU1_Msk             (0x01UL << SCU_CLK_CGATSET0_ERU1_Pos)                   /*!< SCU_CLK CGATSET0: ERU1 Mask             */\r
+#define SCU_CLK_CGATSET0_HRPWM0_Pos           23                                                      /*!< SCU_CLK CGATSET0: HRPWM0 Position       */\r
+#define SCU_CLK_CGATSET0_HRPWM0_Msk           (0x01UL << SCU_CLK_CGATSET0_HRPWM0_Pos)                 /*!< SCU_CLK CGATSET0: HRPWM0 Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CGATCLR0  ------------------------------ */\r
+#define SCU_CLK_CGATCLR0_VADC_Pos             0                                                       /*!< SCU_CLK CGATCLR0: VADC Position         */\r
+#define SCU_CLK_CGATCLR0_VADC_Msk             (0x01UL << SCU_CLK_CGATCLR0_VADC_Pos)                   /*!< SCU_CLK CGATCLR0: VADC Mask             */\r
+#define SCU_CLK_CGATCLR0_DSD_Pos              1                                                       /*!< SCU_CLK CGATCLR0: DSD Position          */\r
+#define SCU_CLK_CGATCLR0_DSD_Msk              (0x01UL << SCU_CLK_CGATCLR0_DSD_Pos)                    /*!< SCU_CLK CGATCLR0: DSD Mask              */\r
+#define SCU_CLK_CGATCLR0_CCU40_Pos            2                                                       /*!< SCU_CLK CGATCLR0: CCU40 Position        */\r
+#define SCU_CLK_CGATCLR0_CCU40_Msk            (0x01UL << SCU_CLK_CGATCLR0_CCU40_Pos)                  /*!< SCU_CLK CGATCLR0: CCU40 Mask            */\r
+#define SCU_CLK_CGATCLR0_CCU41_Pos            3                                                       /*!< SCU_CLK CGATCLR0: CCU41 Position        */\r
+#define SCU_CLK_CGATCLR0_CCU41_Msk            (0x01UL << SCU_CLK_CGATCLR0_CCU41_Pos)                  /*!< SCU_CLK CGATCLR0: CCU41 Mask            */\r
+#define SCU_CLK_CGATCLR0_CCU42_Pos            4                                                       /*!< SCU_CLK CGATCLR0: CCU42 Position        */\r
+#define SCU_CLK_CGATCLR0_CCU42_Msk            (0x01UL << SCU_CLK_CGATCLR0_CCU42_Pos)                  /*!< SCU_CLK CGATCLR0: CCU42 Mask            */\r
+#define SCU_CLK_CGATCLR0_CCU80_Pos            7                                                       /*!< SCU_CLK CGATCLR0: CCU80 Position        */\r
+#define SCU_CLK_CGATCLR0_CCU80_Msk            (0x01UL << SCU_CLK_CGATCLR0_CCU80_Pos)                  /*!< SCU_CLK CGATCLR0: CCU80 Mask            */\r
+#define SCU_CLK_CGATCLR0_CCU81_Pos            8                                                       /*!< SCU_CLK CGATCLR0: CCU81 Position        */\r
+#define SCU_CLK_CGATCLR0_CCU81_Msk            (0x01UL << SCU_CLK_CGATCLR0_CCU81_Pos)                  /*!< SCU_CLK CGATCLR0: CCU81 Mask            */\r
+#define SCU_CLK_CGATCLR0_POSIF0_Pos           9                                                       /*!< SCU_CLK CGATCLR0: POSIF0 Position       */\r
+#define SCU_CLK_CGATCLR0_POSIF0_Msk           (0x01UL << SCU_CLK_CGATCLR0_POSIF0_Pos)                 /*!< SCU_CLK CGATCLR0: POSIF0 Mask           */\r
+#define SCU_CLK_CGATCLR0_POSIF1_Pos           10                                                      /*!< SCU_CLK CGATCLR0: POSIF1 Position       */\r
+#define SCU_CLK_CGATCLR0_POSIF1_Msk           (0x01UL << SCU_CLK_CGATCLR0_POSIF1_Pos)                 /*!< SCU_CLK CGATCLR0: POSIF1 Mask           */\r
+#define SCU_CLK_CGATCLR0_USIC0_Pos            11                                                      /*!< SCU_CLK CGATCLR0: USIC0 Position        */\r
+#define SCU_CLK_CGATCLR0_USIC0_Msk            (0x01UL << SCU_CLK_CGATCLR0_USIC0_Pos)                  /*!< SCU_CLK CGATCLR0: USIC0 Mask            */\r
+#define SCU_CLK_CGATCLR0_ERU1_Pos             16                                                      /*!< SCU_CLK CGATCLR0: ERU1 Position         */\r
+#define SCU_CLK_CGATCLR0_ERU1_Msk             (0x01UL << SCU_CLK_CGATCLR0_ERU1_Pos)                   /*!< SCU_CLK CGATCLR0: ERU1 Mask             */\r
+#define SCU_CLK_CGATCLR0_HRPWM0_Pos           23                                                      /*!< SCU_CLK CGATCLR0: HRPWM0 Position       */\r
+#define SCU_CLK_CGATCLR0_HRPWM0_Msk           (0x01UL << SCU_CLK_CGATCLR0_HRPWM0_Pos)                 /*!< SCU_CLK CGATCLR0: HRPWM0 Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSTAT1  ----------------------------- */\r
+#define SCU_CLK_CGATSTAT1_CCU43_Pos           0                                                       /*!< SCU_CLK CGATSTAT1: CCU43 Position       */\r
+#define SCU_CLK_CGATSTAT1_CCU43_Msk           (0x01UL << SCU_CLK_CGATSTAT1_CCU43_Pos)                 /*!< SCU_CLK CGATSTAT1: CCU43 Mask           */\r
+#define SCU_CLK_CGATSTAT1_LEDTSCU0_Pos        3                                                       /*!< SCU_CLK CGATSTAT1: LEDTSCU0 Position    */\r
+#define SCU_CLK_CGATSTAT1_LEDTSCU0_Msk        (0x01UL << SCU_CLK_CGATSTAT1_LEDTSCU0_Pos)              /*!< SCU_CLK CGATSTAT1: LEDTSCU0 Mask        */\r
+#define SCU_CLK_CGATSTAT1_MCAN0_Pos           4                                                       /*!< SCU_CLK CGATSTAT1: MCAN0 Position       */\r
+#define SCU_CLK_CGATSTAT1_MCAN0_Msk           (0x01UL << SCU_CLK_CGATSTAT1_MCAN0_Pos)                 /*!< SCU_CLK CGATSTAT1: MCAN0 Mask           */\r
+#define SCU_CLK_CGATSTAT1_DAC_Pos             5                                                       /*!< SCU_CLK CGATSTAT1: DAC Position         */\r
+#define SCU_CLK_CGATSTAT1_DAC_Msk             (0x01UL << SCU_CLK_CGATSTAT1_DAC_Pos)                   /*!< SCU_CLK CGATSTAT1: DAC Mask             */\r
+#define SCU_CLK_CGATSTAT1_USIC1_Pos           7                                                       /*!< SCU_CLK CGATSTAT1: USIC1 Position       */\r
+#define SCU_CLK_CGATSTAT1_USIC1_Msk           (0x01UL << SCU_CLK_CGATSTAT1_USIC1_Pos)                 /*!< SCU_CLK CGATSTAT1: USIC1 Mask           */\r
+#define SCU_CLK_CGATSTAT1_PPORTS_Pos          9                                                       /*!< SCU_CLK CGATSTAT1: PPORTS Position      */\r
+#define SCU_CLK_CGATSTAT1_PPORTS_Msk          (0x01UL << SCU_CLK_CGATSTAT1_PPORTS_Pos)                /*!< SCU_CLK CGATSTAT1: PPORTS Mask          */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSET1  ------------------------------ */\r
+#define SCU_CLK_CGATSET1_CCU43_Pos            0                                                       /*!< SCU_CLK CGATSET1: CCU43 Position        */\r
+#define SCU_CLK_CGATSET1_CCU43_Msk            (0x01UL << SCU_CLK_CGATSET1_CCU43_Pos)                  /*!< SCU_CLK CGATSET1: CCU43 Mask            */\r
+#define SCU_CLK_CGATSET1_LEDTSCU0_Pos         3                                                       /*!< SCU_CLK CGATSET1: LEDTSCU0 Position     */\r
+#define SCU_CLK_CGATSET1_LEDTSCU0_Msk         (0x01UL << SCU_CLK_CGATSET1_LEDTSCU0_Pos)               /*!< SCU_CLK CGATSET1: LEDTSCU0 Mask         */\r
+#define SCU_CLK_CGATSET1_MCAN0_Pos            4                                                       /*!< SCU_CLK CGATSET1: MCAN0 Position        */\r
+#define SCU_CLK_CGATSET1_MCAN0_Msk            (0x01UL << SCU_CLK_CGATSET1_MCAN0_Pos)                  /*!< SCU_CLK CGATSET1: MCAN0 Mask            */\r
+#define SCU_CLK_CGATSET1_DAC_Pos              5                                                       /*!< SCU_CLK CGATSET1: DAC Position          */\r
+#define SCU_CLK_CGATSET1_DAC_Msk              (0x01UL << SCU_CLK_CGATSET1_DAC_Pos)                    /*!< SCU_CLK CGATSET1: DAC Mask              */\r
+#define SCU_CLK_CGATSET1_USIC1_Pos            7                                                       /*!< SCU_CLK CGATSET1: USIC1 Position        */\r
+#define SCU_CLK_CGATSET1_USIC1_Msk            (0x01UL << SCU_CLK_CGATSET1_USIC1_Pos)                  /*!< SCU_CLK CGATSET1: USIC1 Mask            */\r
+#define SCU_CLK_CGATSET1_PPORTS_Pos           9                                                       /*!< SCU_CLK CGATSET1: PPORTS Position       */\r
+#define SCU_CLK_CGATSET1_PPORTS_Msk           (0x01UL << SCU_CLK_CGATSET1_PPORTS_Pos)                 /*!< SCU_CLK CGATSET1: PPORTS Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CGATCLR1  ------------------------------ */\r
+#define SCU_CLK_CGATCLR1_CCU43_Pos            0                                                       /*!< SCU_CLK CGATCLR1: CCU43 Position        */\r
+#define SCU_CLK_CGATCLR1_CCU43_Msk            (0x01UL << SCU_CLK_CGATCLR1_CCU43_Pos)                  /*!< SCU_CLK CGATCLR1: CCU43 Mask            */\r
+#define SCU_CLK_CGATCLR1_LEDTSCU0_Pos         3                                                       /*!< SCU_CLK CGATCLR1: LEDTSCU0 Position     */\r
+#define SCU_CLK_CGATCLR1_LEDTSCU0_Msk         (0x01UL << SCU_CLK_CGATCLR1_LEDTSCU0_Pos)               /*!< SCU_CLK CGATCLR1: LEDTSCU0 Mask         */\r
+#define SCU_CLK_CGATCLR1_MCAN0_Pos            4                                                       /*!< SCU_CLK CGATCLR1: MCAN0 Position        */\r
+#define SCU_CLK_CGATCLR1_MCAN0_Msk            (0x01UL << SCU_CLK_CGATCLR1_MCAN0_Pos)                  /*!< SCU_CLK CGATCLR1: MCAN0 Mask            */\r
+#define SCU_CLK_CGATCLR1_DAC_Pos              5                                                       /*!< SCU_CLK CGATCLR1: DAC Position          */\r
+#define SCU_CLK_CGATCLR1_DAC_Msk              (0x01UL << SCU_CLK_CGATCLR1_DAC_Pos)                    /*!< SCU_CLK CGATCLR1: DAC Mask              */\r
+#define SCU_CLK_CGATCLR1_USIC1_Pos            7                                                       /*!< SCU_CLK CGATCLR1: USIC1 Position        */\r
+#define SCU_CLK_CGATCLR1_USIC1_Msk            (0x01UL << SCU_CLK_CGATCLR1_USIC1_Pos)                  /*!< SCU_CLK CGATCLR1: USIC1 Mask            */\r
+#define SCU_CLK_CGATCLR1_PPORTS_Pos           9                                                       /*!< SCU_CLK CGATCLR1: PPORTS Position       */\r
+#define SCU_CLK_CGATCLR1_PPORTS_Msk           (0x01UL << SCU_CLK_CGATCLR1_PPORTS_Pos)                 /*!< SCU_CLK CGATCLR1: PPORTS Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSTAT2  ----------------------------- */\r
+#define SCU_CLK_CGATSTAT2_WDT_Pos             1                                                       /*!< SCU_CLK CGATSTAT2: WDT Position         */\r
+#define SCU_CLK_CGATSTAT2_WDT_Msk             (0x01UL << SCU_CLK_CGATSTAT2_WDT_Pos)                   /*!< SCU_CLK CGATSTAT2: WDT Mask             */\r
+#define SCU_CLK_CGATSTAT2_ETH0_Pos            2                                                       /*!< SCU_CLK CGATSTAT2: ETH0 Position        */\r
+#define SCU_CLK_CGATSTAT2_ETH0_Msk            (0x01UL << SCU_CLK_CGATSTAT2_ETH0_Pos)                  /*!< SCU_CLK CGATSTAT2: ETH0 Mask            */\r
+#define SCU_CLK_CGATSTAT2_DMA0_Pos            4                                                       /*!< SCU_CLK CGATSTAT2: DMA0 Position        */\r
+#define SCU_CLK_CGATSTAT2_DMA0_Msk            (0x01UL << SCU_CLK_CGATSTAT2_DMA0_Pos)                  /*!< SCU_CLK CGATSTAT2: DMA0 Mask            */\r
+#define SCU_CLK_CGATSTAT2_FCE_Pos             6                                                       /*!< SCU_CLK CGATSTAT2: FCE Position         */\r
+#define SCU_CLK_CGATSTAT2_FCE_Msk             (0x01UL << SCU_CLK_CGATSTAT2_FCE_Pos)                   /*!< SCU_CLK CGATSTAT2: FCE Mask             */\r
+#define SCU_CLK_CGATSTAT2_USB_Pos             7                                                       /*!< SCU_CLK CGATSTAT2: USB Position         */\r
+#define SCU_CLK_CGATSTAT2_USB_Msk             (0x01UL << SCU_CLK_CGATSTAT2_USB_Pos)                   /*!< SCU_CLK CGATSTAT2: USB Mask             */\r
+\r
+/* ------------------------------  SCU_CLK_CGATSET2  ------------------------------ */\r
+#define SCU_CLK_CGATSET2_WDT_Pos              1                                                       /*!< SCU_CLK CGATSET2: WDT Position          */\r
+#define SCU_CLK_CGATSET2_WDT_Msk              (0x01UL << SCU_CLK_CGATSET2_WDT_Pos)                    /*!< SCU_CLK CGATSET2: WDT Mask              */\r
+#define SCU_CLK_CGATSET2_ETH0_Pos             2                                                       /*!< SCU_CLK CGATSET2: ETH0 Position         */\r
+#define SCU_CLK_CGATSET2_ETH0_Msk             (0x01UL << SCU_CLK_CGATSET2_ETH0_Pos)                   /*!< SCU_CLK CGATSET2: ETH0 Mask             */\r
+#define SCU_CLK_CGATSET2_DMA0_Pos             4                                                       /*!< SCU_CLK CGATSET2: DMA0 Position         */\r
+#define SCU_CLK_CGATSET2_DMA0_Msk             (0x01UL << SCU_CLK_CGATSET2_DMA0_Pos)                   /*!< SCU_CLK CGATSET2: DMA0 Mask             */\r
+#define SCU_CLK_CGATSET2_FCE_Pos              6                                                       /*!< SCU_CLK CGATSET2: FCE Position          */\r
+#define SCU_CLK_CGATSET2_FCE_Msk              (0x01UL << SCU_CLK_CGATSET2_FCE_Pos)                    /*!< SCU_CLK CGATSET2: FCE Mask              */\r
+#define SCU_CLK_CGATSET2_USB_Pos              7                                                       /*!< SCU_CLK CGATSET2: USB Position          */\r
+#define SCU_CLK_CGATSET2_USB_Msk              (0x01UL << SCU_CLK_CGATSET2_USB_Pos)                    /*!< SCU_CLK CGATSET2: USB Mask              */\r
+\r
+/* ------------------------------  SCU_CLK_CGATCLR2  ------------------------------ */\r
+#define SCU_CLK_CGATCLR2_WDT_Pos              1                                                       /*!< SCU_CLK CGATCLR2: WDT Position          */\r
+#define SCU_CLK_CGATCLR2_WDT_Msk              (0x01UL << SCU_CLK_CGATCLR2_WDT_Pos)                    /*!< SCU_CLK CGATCLR2: WDT Mask              */\r
+#define SCU_CLK_CGATCLR2_ETH0_Pos             2                                                       /*!< SCU_CLK CGATCLR2: ETH0 Position         */\r
+#define SCU_CLK_CGATCLR2_ETH0_Msk             (0x01UL << SCU_CLK_CGATCLR2_ETH0_Pos)                   /*!< SCU_CLK CGATCLR2: ETH0 Mask             */\r
+#define SCU_CLK_CGATCLR2_DMA0_Pos             4                                                       /*!< SCU_CLK CGATCLR2: DMA0 Position         */\r
+#define SCU_CLK_CGATCLR2_DMA0_Msk             (0x01UL << SCU_CLK_CGATCLR2_DMA0_Pos)                   /*!< SCU_CLK CGATCLR2: DMA0 Mask             */\r
+#define SCU_CLK_CGATCLR2_FCE_Pos              6                                                       /*!< SCU_CLK CGATCLR2: FCE Position          */\r
+#define SCU_CLK_CGATCLR2_FCE_Msk              (0x01UL << SCU_CLK_CGATCLR2_FCE_Pos)                    /*!< SCU_CLK CGATCLR2: FCE Mask              */\r
+#define SCU_CLK_CGATCLR2_USB_Pos              7                                                       /*!< SCU_CLK CGATCLR2: USB Position          */\r
+#define SCU_CLK_CGATCLR2_USB_Msk              (0x01UL << SCU_CLK_CGATCLR2_USB_Pos)                    /*!< SCU_CLK CGATCLR2: USB Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_OSC' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_OSC_OSCHPSTAT  ----------------------------- */\r
+#define SCU_OSC_OSCHPSTAT_X1D_Pos             0                                                       /*!< SCU_OSC OSCHPSTAT: X1D Position         */\r
+#define SCU_OSC_OSCHPSTAT_X1D_Msk             (0x01UL << SCU_OSC_OSCHPSTAT_X1D_Pos)                   /*!< SCU_OSC OSCHPSTAT: X1D Mask             */\r
+\r
+/* ------------------------------  SCU_OSC_OSCHPCTRL  ----------------------------- */\r
+#define SCU_OSC_OSCHPCTRL_X1DEN_Pos           0                                                       /*!< SCU_OSC OSCHPCTRL: X1DEN Position       */\r
+#define SCU_OSC_OSCHPCTRL_X1DEN_Msk           (0x01UL << SCU_OSC_OSCHPCTRL_X1DEN_Pos)                 /*!< SCU_OSC OSCHPCTRL: X1DEN Mask           */\r
+#define SCU_OSC_OSCHPCTRL_SHBY_Pos            1                                                       /*!< SCU_OSC OSCHPCTRL: SHBY Position        */\r
+#define SCU_OSC_OSCHPCTRL_SHBY_Msk            (0x01UL << SCU_OSC_OSCHPCTRL_SHBY_Pos)                  /*!< SCU_OSC OSCHPCTRL: SHBY Mask            */\r
+#define SCU_OSC_OSCHPCTRL_MODE_Pos            4                                                       /*!< SCU_OSC OSCHPCTRL: MODE Position        */\r
+#define SCU_OSC_OSCHPCTRL_MODE_Msk            (0x03UL << SCU_OSC_OSCHPCTRL_MODE_Pos)                  /*!< SCU_OSC OSCHPCTRL: MODE Mask            */\r
+#define SCU_OSC_OSCHPCTRL_OSCVAL_Pos          16                                                      /*!< SCU_OSC OSCHPCTRL: OSCVAL Position      */\r
+#define SCU_OSC_OSCHPCTRL_OSCVAL_Msk          (0x1fUL << SCU_OSC_OSCHPCTRL_OSCVAL_Pos)                /*!< SCU_OSC OSCHPCTRL: OSCVAL Mask          */\r
+\r
+/* -----------------------------  SCU_OSC_CLKCALCONST  ---------------------------- */\r
+#define SCU_OSC_CLKCALCONST_CALIBCONST_Pos    0                                                       /*!< SCU_OSC CLKCALCONST: CALIBCONST Position */\r
+#define SCU_OSC_CLKCALCONST_CALIBCONST_Msk    (0x0fUL << SCU_OSC_CLKCALCONST_CALIBCONST_Pos)          /*!< SCU_OSC CLKCALCONST: CALIBCONST Mask    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_PLL' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_PLL_PLLSTAT  ------------------------------ */\r
+#define SCU_PLL_PLLSTAT_VCOBYST_Pos           0                                                       /*!< SCU_PLL PLLSTAT: VCOBYST Position       */\r
+#define SCU_PLL_PLLSTAT_VCOBYST_Msk           (0x01UL << SCU_PLL_PLLSTAT_VCOBYST_Pos)                 /*!< SCU_PLL PLLSTAT: VCOBYST Mask           */\r
+#define SCU_PLL_PLLSTAT_PWDSTAT_Pos           1                                                       /*!< SCU_PLL PLLSTAT: PWDSTAT Position       */\r
+#define SCU_PLL_PLLSTAT_PWDSTAT_Msk           (0x01UL << SCU_PLL_PLLSTAT_PWDSTAT_Pos)                 /*!< SCU_PLL PLLSTAT: PWDSTAT Mask           */\r
+#define SCU_PLL_PLLSTAT_VCOLOCK_Pos           2                                                       /*!< SCU_PLL PLLSTAT: VCOLOCK Position       */\r
+#define SCU_PLL_PLLSTAT_VCOLOCK_Msk           (0x01UL << SCU_PLL_PLLSTAT_VCOLOCK_Pos)                 /*!< SCU_PLL PLLSTAT: VCOLOCK Mask           */\r
+#define SCU_PLL_PLLSTAT_K1RDY_Pos             4                                                       /*!< SCU_PLL PLLSTAT: K1RDY Position         */\r
+#define SCU_PLL_PLLSTAT_K1RDY_Msk             (0x01UL << SCU_PLL_PLLSTAT_K1RDY_Pos)                   /*!< SCU_PLL PLLSTAT: K1RDY Mask             */\r
+#define SCU_PLL_PLLSTAT_K2RDY_Pos             5                                                       /*!< SCU_PLL PLLSTAT: K2RDY Position         */\r
+#define SCU_PLL_PLLSTAT_K2RDY_Msk             (0x01UL << SCU_PLL_PLLSTAT_K2RDY_Pos)                   /*!< SCU_PLL PLLSTAT: K2RDY Mask             */\r
+#define SCU_PLL_PLLSTAT_BY_Pos                6                                                       /*!< SCU_PLL PLLSTAT: BY Position            */\r
+#define SCU_PLL_PLLSTAT_BY_Msk                (0x01UL << SCU_PLL_PLLSTAT_BY_Pos)                      /*!< SCU_PLL PLLSTAT: BY Mask                */\r
+#define SCU_PLL_PLLSTAT_PLLLV_Pos             7                                                       /*!< SCU_PLL PLLSTAT: PLLLV Position         */\r
+#define SCU_PLL_PLLSTAT_PLLLV_Msk             (0x01UL << SCU_PLL_PLLSTAT_PLLLV_Pos)                   /*!< SCU_PLL PLLSTAT: PLLLV Mask             */\r
+#define SCU_PLL_PLLSTAT_PLLHV_Pos             8                                                       /*!< SCU_PLL PLLSTAT: PLLHV Position         */\r
+#define SCU_PLL_PLLSTAT_PLLHV_Msk             (0x01UL << SCU_PLL_PLLSTAT_PLLHV_Pos)                   /*!< SCU_PLL PLLSTAT: PLLHV Mask             */\r
+#define SCU_PLL_PLLSTAT_PLLSP_Pos             9                                                       /*!< SCU_PLL PLLSTAT: PLLSP Position         */\r
+#define SCU_PLL_PLLSTAT_PLLSP_Msk             (0x01UL << SCU_PLL_PLLSTAT_PLLSP_Pos)                   /*!< SCU_PLL PLLSTAT: PLLSP Mask             */\r
+\r
+/* -------------------------------  SCU_PLL_PLLCON0  ------------------------------ */\r
+#define SCU_PLL_PLLCON0_VCOBYP_Pos            0                                                       /*!< SCU_PLL PLLCON0: VCOBYP Position        */\r
+#define SCU_PLL_PLLCON0_VCOBYP_Msk            (0x01UL << SCU_PLL_PLLCON0_VCOBYP_Pos)                  /*!< SCU_PLL PLLCON0: VCOBYP Mask            */\r
+#define SCU_PLL_PLLCON0_VCOPWD_Pos            1                                                       /*!< SCU_PLL PLLCON0: VCOPWD Position        */\r
+#define SCU_PLL_PLLCON0_VCOPWD_Msk            (0x01UL << SCU_PLL_PLLCON0_VCOPWD_Pos)                  /*!< SCU_PLL PLLCON0: VCOPWD Mask            */\r
+#define SCU_PLL_PLLCON0_VCOTR_Pos             2                                                       /*!< SCU_PLL PLLCON0: VCOTR Position         */\r
+#define SCU_PLL_PLLCON0_VCOTR_Msk             (0x01UL << SCU_PLL_PLLCON0_VCOTR_Pos)                   /*!< SCU_PLL PLLCON0: VCOTR Mask             */\r
+#define SCU_PLL_PLLCON0_FINDIS_Pos            4                                                       /*!< SCU_PLL PLLCON0: FINDIS Position        */\r
+#define SCU_PLL_PLLCON0_FINDIS_Msk            (0x01UL << SCU_PLL_PLLCON0_FINDIS_Pos)                  /*!< SCU_PLL PLLCON0: FINDIS Mask            */\r
+#define SCU_PLL_PLLCON0_OSCDISCDIS_Pos        6                                                       /*!< SCU_PLL PLLCON0: OSCDISCDIS Position    */\r
+#define SCU_PLL_PLLCON0_OSCDISCDIS_Msk        (0x01UL << SCU_PLL_PLLCON0_OSCDISCDIS_Pos)              /*!< SCU_PLL PLLCON0: OSCDISCDIS Mask        */\r
+#define SCU_PLL_PLLCON0_PLLPWD_Pos            16                                                      /*!< SCU_PLL PLLCON0: PLLPWD Position        */\r
+#define SCU_PLL_PLLCON0_PLLPWD_Msk            (0x01UL << SCU_PLL_PLLCON0_PLLPWD_Pos)                  /*!< SCU_PLL PLLCON0: PLLPWD Mask            */\r
+#define SCU_PLL_PLLCON0_OSCRES_Pos            17                                                      /*!< SCU_PLL PLLCON0: OSCRES Position        */\r
+#define SCU_PLL_PLLCON0_OSCRES_Msk            (0x01UL << SCU_PLL_PLLCON0_OSCRES_Pos)                  /*!< SCU_PLL PLLCON0: OSCRES Mask            */\r
+#define SCU_PLL_PLLCON0_RESLD_Pos             18                                                      /*!< SCU_PLL PLLCON0: RESLD Position         */\r
+#define SCU_PLL_PLLCON0_RESLD_Msk             (0x01UL << SCU_PLL_PLLCON0_RESLD_Pos)                   /*!< SCU_PLL PLLCON0: RESLD Mask             */\r
+#define SCU_PLL_PLLCON0_AOTREN_Pos            19                                                      /*!< SCU_PLL PLLCON0: AOTREN Position        */\r
+#define SCU_PLL_PLLCON0_AOTREN_Msk            (0x01UL << SCU_PLL_PLLCON0_AOTREN_Pos)                  /*!< SCU_PLL PLLCON0: AOTREN Mask            */\r
+#define SCU_PLL_PLLCON0_FOTR_Pos              20                                                      /*!< SCU_PLL PLLCON0: FOTR Position          */\r
+#define SCU_PLL_PLLCON0_FOTR_Msk              (0x01UL << SCU_PLL_PLLCON0_FOTR_Pos)                    /*!< SCU_PLL PLLCON0: FOTR Mask              */\r
+\r
+/* -------------------------------  SCU_PLL_PLLCON1  ------------------------------ */\r
+#define SCU_PLL_PLLCON1_K1DIV_Pos             0                                                       /*!< SCU_PLL PLLCON1: K1DIV Position         */\r
+#define SCU_PLL_PLLCON1_K1DIV_Msk             (0x7fUL << SCU_PLL_PLLCON1_K1DIV_Pos)                   /*!< SCU_PLL PLLCON1: K1DIV Mask             */\r
+#define SCU_PLL_PLLCON1_NDIV_Pos              8                                                       /*!< SCU_PLL PLLCON1: NDIV Position          */\r
+#define SCU_PLL_PLLCON1_NDIV_Msk              (0x7fUL << SCU_PLL_PLLCON1_NDIV_Pos)                    /*!< SCU_PLL PLLCON1: NDIV Mask              */\r
+#define SCU_PLL_PLLCON1_K2DIV_Pos             16                                                      /*!< SCU_PLL PLLCON1: K2DIV Position         */\r
+#define SCU_PLL_PLLCON1_K2DIV_Msk             (0x7fUL << SCU_PLL_PLLCON1_K2DIV_Pos)                   /*!< SCU_PLL PLLCON1: K2DIV Mask             */\r
+#define SCU_PLL_PLLCON1_PDIV_Pos              24                                                      /*!< SCU_PLL PLLCON1: PDIV Position          */\r
+#define SCU_PLL_PLLCON1_PDIV_Msk              (0x0fUL << SCU_PLL_PLLCON1_PDIV_Pos)                    /*!< SCU_PLL PLLCON1: PDIV Mask              */\r
+\r
+/* -------------------------------  SCU_PLL_PLLCON2  ------------------------------ */\r
+#define SCU_PLL_PLLCON2_PINSEL_Pos            0                                                       /*!< SCU_PLL PLLCON2: PINSEL Position        */\r
+#define SCU_PLL_PLLCON2_PINSEL_Msk            (0x01UL << SCU_PLL_PLLCON2_PINSEL_Pos)                  /*!< SCU_PLL PLLCON2: PINSEL Mask            */\r
+#define SCU_PLL_PLLCON2_K1INSEL_Pos           8                                                       /*!< SCU_PLL PLLCON2: K1INSEL Position       */\r
+#define SCU_PLL_PLLCON2_K1INSEL_Msk           (0x01UL << SCU_PLL_PLLCON2_K1INSEL_Pos)                 /*!< SCU_PLL PLLCON2: K1INSEL Mask           */\r
+\r
+/* -----------------------------  SCU_PLL_USBPLLSTAT  ----------------------------- */\r
+#define SCU_PLL_USBPLLSTAT_VCOBYST_Pos        0                                                       /*!< SCU_PLL USBPLLSTAT: VCOBYST Position    */\r
+#define SCU_PLL_USBPLLSTAT_VCOBYST_Msk        (0x01UL << SCU_PLL_USBPLLSTAT_VCOBYST_Pos)              /*!< SCU_PLL USBPLLSTAT: VCOBYST Mask        */\r
+#define SCU_PLL_USBPLLSTAT_PWDSTAT_Pos        1                                                       /*!< SCU_PLL USBPLLSTAT: PWDSTAT Position    */\r
+#define SCU_PLL_USBPLLSTAT_PWDSTAT_Msk        (0x01UL << SCU_PLL_USBPLLSTAT_PWDSTAT_Pos)              /*!< SCU_PLL USBPLLSTAT: PWDSTAT Mask        */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCK_Pos        2                                                       /*!< SCU_PLL USBPLLSTAT: VCOLOCK Position    */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCK_Msk        (0x01UL << SCU_PLL_USBPLLSTAT_VCOLOCK_Pos)              /*!< SCU_PLL USBPLLSTAT: VCOLOCK Mask        */\r
+#define SCU_PLL_USBPLLSTAT_BY_Pos             6                                                       /*!< SCU_PLL USBPLLSTAT: BY Position         */\r
+#define SCU_PLL_USBPLLSTAT_BY_Msk             (0x01UL << SCU_PLL_USBPLLSTAT_BY_Pos)                   /*!< SCU_PLL USBPLLSTAT: BY Mask             */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos      7                                                       /*!< SCU_PLL USBPLLSTAT: VCOLOCKED Position  */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk      (0x01UL << SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos)            /*!< SCU_PLL USBPLLSTAT: VCOLOCKED Mask      */\r
+\r
+/* ------------------------------  SCU_PLL_USBPLLCON  ----------------------------- */\r
+#define SCU_PLL_USBPLLCON_VCOBYP_Pos          0                                                       /*!< SCU_PLL USBPLLCON: VCOBYP Position      */\r
+#define SCU_PLL_USBPLLCON_VCOBYP_Msk          (0x01UL << SCU_PLL_USBPLLCON_VCOBYP_Pos)                /*!< SCU_PLL USBPLLCON: VCOBYP Mask          */\r
+#define SCU_PLL_USBPLLCON_VCOPWD_Pos          1                                                       /*!< SCU_PLL USBPLLCON: VCOPWD Position      */\r
+#define SCU_PLL_USBPLLCON_VCOPWD_Msk          (0x01UL << SCU_PLL_USBPLLCON_VCOPWD_Pos)                /*!< SCU_PLL USBPLLCON: VCOPWD Mask          */\r
+#define SCU_PLL_USBPLLCON_VCOTR_Pos           2                                                       /*!< SCU_PLL USBPLLCON: VCOTR Position       */\r
+#define SCU_PLL_USBPLLCON_VCOTR_Msk           (0x01UL << SCU_PLL_USBPLLCON_VCOTR_Pos)                 /*!< SCU_PLL USBPLLCON: VCOTR Mask           */\r
+#define SCU_PLL_USBPLLCON_FINDIS_Pos          4                                                       /*!< SCU_PLL USBPLLCON: FINDIS Position      */\r
+#define SCU_PLL_USBPLLCON_FINDIS_Msk          (0x01UL << SCU_PLL_USBPLLCON_FINDIS_Pos)                /*!< SCU_PLL USBPLLCON: FINDIS Mask          */\r
+#define SCU_PLL_USBPLLCON_OSCDISCDIS_Pos      6                                                       /*!< SCU_PLL USBPLLCON: OSCDISCDIS Position  */\r
+#define SCU_PLL_USBPLLCON_OSCDISCDIS_Msk      (0x01UL << SCU_PLL_USBPLLCON_OSCDISCDIS_Pos)            /*!< SCU_PLL USBPLLCON: OSCDISCDIS Mask      */\r
+#define SCU_PLL_USBPLLCON_NDIV_Pos            8                                                       /*!< SCU_PLL USBPLLCON: NDIV Position        */\r
+#define SCU_PLL_USBPLLCON_NDIV_Msk            (0x7fUL << SCU_PLL_USBPLLCON_NDIV_Pos)                  /*!< SCU_PLL USBPLLCON: NDIV Mask            */\r
+#define SCU_PLL_USBPLLCON_PLLPWD_Pos          16                                                      /*!< SCU_PLL USBPLLCON: PLLPWD Position      */\r
+#define SCU_PLL_USBPLLCON_PLLPWD_Msk          (0x01UL << SCU_PLL_USBPLLCON_PLLPWD_Pos)                /*!< SCU_PLL USBPLLCON: PLLPWD Mask          */\r
+#define SCU_PLL_USBPLLCON_RESLD_Pos           18                                                      /*!< SCU_PLL USBPLLCON: RESLD Position       */\r
+#define SCU_PLL_USBPLLCON_RESLD_Msk           (0x01UL << SCU_PLL_USBPLLCON_RESLD_Pos)                 /*!< SCU_PLL USBPLLCON: RESLD Mask           */\r
+#define SCU_PLL_USBPLLCON_PDIV_Pos            24                                                      /*!< SCU_PLL USBPLLCON: PDIV Position        */\r
+#define SCU_PLL_USBPLLCON_PDIV_Msk            (0x0fUL << SCU_PLL_USBPLLCON_PDIV_Pos)                  /*!< SCU_PLL USBPLLCON: PDIV Mask            */\r
+\r
+/* ------------------------------  SCU_PLL_CLKMXSTAT  ----------------------------- */\r
+#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos       0                                                       /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX Position   */\r
+#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk       (0x03UL << SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos)             /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX Mask       */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'SCU_GENERAL' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_GENERAL_ID  ------------------------------- */\r
+#define SCU_GENERAL_ID_MOD_REV_Pos            0                                                       /*!< SCU_GENERAL ID: MOD_REV Position        */\r
+#define SCU_GENERAL_ID_MOD_REV_Msk            (0x000000ffUL << SCU_GENERAL_ID_MOD_REV_Pos)            /*!< SCU_GENERAL ID: MOD_REV Mask            */\r
+#define SCU_GENERAL_ID_MOD_TYPE_Pos           8                                                       /*!< SCU_GENERAL ID: MOD_TYPE Position       */\r
+#define SCU_GENERAL_ID_MOD_TYPE_Msk           (0x000000ffUL << SCU_GENERAL_ID_MOD_TYPE_Pos)           /*!< SCU_GENERAL ID: MOD_TYPE Mask           */\r
+#define SCU_GENERAL_ID_MOD_NUMBER_Pos         16                                                      /*!< SCU_GENERAL ID: MOD_NUMBER Position     */\r
+#define SCU_GENERAL_ID_MOD_NUMBER_Msk         (0x0000ffffUL << SCU_GENERAL_ID_MOD_NUMBER_Pos)         /*!< SCU_GENERAL ID: MOD_NUMBER Mask         */\r
+\r
+/* -----------------------------  SCU_GENERAL_IDCHIP  ----------------------------- */\r
+#define SCU_GENERAL_IDCHIP_IDCHIP_Pos         0                                                       /*!< SCU_GENERAL IDCHIP: IDCHIP Position     */\r
+#define SCU_GENERAL_IDCHIP_IDCHIP_Msk         (0xffffffffUL << SCU_GENERAL_IDCHIP_IDCHIP_Pos)         /*!< SCU_GENERAL IDCHIP: IDCHIP Mask         */\r
+\r
+/* -----------------------------  SCU_GENERAL_IDMANUF  ---------------------------- */\r
+#define SCU_GENERAL_IDMANUF_DEPT_Pos          0                                                       /*!< SCU_GENERAL IDMANUF: DEPT Position      */\r
+#define SCU_GENERAL_IDMANUF_DEPT_Msk          (0x1fUL << SCU_GENERAL_IDMANUF_DEPT_Pos)                /*!< SCU_GENERAL IDMANUF: DEPT Mask          */\r
+#define SCU_GENERAL_IDMANUF_MANUF_Pos         5                                                       /*!< SCU_GENERAL IDMANUF: MANUF Position     */\r
+#define SCU_GENERAL_IDMANUF_MANUF_Msk         (0x000007ffUL << SCU_GENERAL_IDMANUF_MANUF_Pos)         /*!< SCU_GENERAL IDMANUF: MANUF Mask         */\r
+\r
+/* ------------------------------  SCU_GENERAL_STCON  ----------------------------- */\r
+#define SCU_GENERAL_STCON_HWCON_Pos           0                                                       /*!< SCU_GENERAL STCON: HWCON Position       */\r
+#define SCU_GENERAL_STCON_HWCON_Msk           (0x03UL << SCU_GENERAL_STCON_HWCON_Pos)                 /*!< SCU_GENERAL STCON: HWCON Mask           */\r
+#define SCU_GENERAL_STCON_SWCON_Pos           8                                                       /*!< SCU_GENERAL STCON: SWCON Position       */\r
+#define SCU_GENERAL_STCON_SWCON_Msk           (0x0fUL << SCU_GENERAL_STCON_SWCON_Pos)                 /*!< SCU_GENERAL STCON: SWCON Mask           */\r
+\r
+/* -------------------------------  SCU_GENERAL_GPR  ------------------------------ */\r
+#define SCU_GENERAL_GPR_DAT_Pos               0                                                       /*!< SCU_GENERAL GPR: DAT Position           */\r
+#define SCU_GENERAL_GPR_DAT_Msk               (0xffffffffUL << SCU_GENERAL_GPR_DAT_Pos)               /*!< SCU_GENERAL GPR: DAT Mask               */\r
+\r
+/* -----------------------------  SCU_GENERAL_CCUCON  ----------------------------- */\r
+#define SCU_GENERAL_CCUCON_GSC40_Pos          0                                                       /*!< SCU_GENERAL CCUCON: GSC40 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC40_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC40_Pos)                /*!< SCU_GENERAL CCUCON: GSC40 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC41_Pos          1                                                       /*!< SCU_GENERAL CCUCON: GSC41 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC41_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC41_Pos)                /*!< SCU_GENERAL CCUCON: GSC41 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC42_Pos          2                                                       /*!< SCU_GENERAL CCUCON: GSC42 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC42_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC42_Pos)                /*!< SCU_GENERAL CCUCON: GSC42 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC43_Pos          3                                                       /*!< SCU_GENERAL CCUCON: GSC43 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC43_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC43_Pos)                /*!< SCU_GENERAL CCUCON: GSC43 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC80_Pos          8                                                       /*!< SCU_GENERAL CCUCON: GSC80 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC80_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC80_Pos)                /*!< SCU_GENERAL CCUCON: GSC80 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC81_Pos          9                                                       /*!< SCU_GENERAL CCUCON: GSC81 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC81_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC81_Pos)                /*!< SCU_GENERAL CCUCON: GSC81 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSHR0_Pos          24                                                      /*!< SCU_GENERAL CCUCON: GSHR0 Position      */\r
+#define SCU_GENERAL_CCUCON_GSHR0_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSHR0_Pos)                /*!< SCU_GENERAL CCUCON: GSHR0 Mask          */\r
+\r
+/* -----------------------------  SCU_GENERAL_DTSCON  ----------------------------- */\r
+#define SCU_GENERAL_DTSCON_PWD_Pos            0                                                       /*!< SCU_GENERAL DTSCON: PWD Position        */\r
+#define SCU_GENERAL_DTSCON_PWD_Msk            (0x01UL << SCU_GENERAL_DTSCON_PWD_Pos)                  /*!< SCU_GENERAL DTSCON: PWD Mask            */\r
+#define SCU_GENERAL_DTSCON_START_Pos          1                                                       /*!< SCU_GENERAL DTSCON: START Position      */\r
+#define SCU_GENERAL_DTSCON_START_Msk          (0x01UL << SCU_GENERAL_DTSCON_START_Pos)                /*!< SCU_GENERAL DTSCON: START Mask          */\r
+#define SCU_GENERAL_DTSCON_OFFSET_Pos         4                                                       /*!< SCU_GENERAL DTSCON: OFFSET Position     */\r
+#define SCU_GENERAL_DTSCON_OFFSET_Msk         (0x7fUL << SCU_GENERAL_DTSCON_OFFSET_Pos)               /*!< SCU_GENERAL DTSCON: OFFSET Mask         */\r
+#define SCU_GENERAL_DTSCON_GAIN_Pos           11                                                      /*!< SCU_GENERAL DTSCON: GAIN Position       */\r
+#define SCU_GENERAL_DTSCON_GAIN_Msk           (0x3fUL << SCU_GENERAL_DTSCON_GAIN_Pos)                 /*!< SCU_GENERAL DTSCON: GAIN Mask           */\r
+#define SCU_GENERAL_DTSCON_REFTRIM_Pos        17                                                      /*!< SCU_GENERAL DTSCON: REFTRIM Position    */\r
+#define SCU_GENERAL_DTSCON_REFTRIM_Msk        (0x07UL << SCU_GENERAL_DTSCON_REFTRIM_Pos)              /*!< SCU_GENERAL DTSCON: REFTRIM Mask        */\r
+#define SCU_GENERAL_DTSCON_BGTRIM_Pos         20                                                      /*!< SCU_GENERAL DTSCON: BGTRIM Position     */\r
+#define SCU_GENERAL_DTSCON_BGTRIM_Msk         (0x0fUL << SCU_GENERAL_DTSCON_BGTRIM_Pos)               /*!< SCU_GENERAL DTSCON: BGTRIM Mask         */\r
+\r
+/* -----------------------------  SCU_GENERAL_DTSSTAT  ---------------------------- */\r
+#define SCU_GENERAL_DTSSTAT_RESULT_Pos        0                                                       /*!< SCU_GENERAL DTSSTAT: RESULT Position    */\r
+#define SCU_GENERAL_DTSSTAT_RESULT_Msk        (0x000003ffUL << SCU_GENERAL_DTSSTAT_RESULT_Pos)        /*!< SCU_GENERAL DTSSTAT: RESULT Mask        */\r
+#define SCU_GENERAL_DTSSTAT_RDY_Pos           14                                                      /*!< SCU_GENERAL DTSSTAT: RDY Position       */\r
+#define SCU_GENERAL_DTSSTAT_RDY_Msk           (0x01UL << SCU_GENERAL_DTSSTAT_RDY_Pos)                 /*!< SCU_GENERAL DTSSTAT: RDY Mask           */\r
+#define SCU_GENERAL_DTSSTAT_BUSY_Pos          15                                                      /*!< SCU_GENERAL DTSSTAT: BUSY Position      */\r
+#define SCU_GENERAL_DTSSTAT_BUSY_Msk          (0x01UL << SCU_GENERAL_DTSSTAT_BUSY_Pos)                /*!< SCU_GENERAL DTSSTAT: BUSY Mask          */\r
+\r
+/* -----------------------------  SCU_GENERAL_GORCEN  ----------------------------- */\r
+#define SCU_GENERAL_GORCEN_ENORC6_Pos         6                                                       /*!< SCU_GENERAL GORCEN: ENORC6 Position     */\r
+#define SCU_GENERAL_GORCEN_ENORC6_Msk         (0x01UL << SCU_GENERAL_GORCEN_ENORC6_Pos)               /*!< SCU_GENERAL GORCEN: ENORC6 Mask         */\r
+#define SCU_GENERAL_GORCEN_ENORC7_Pos         7                                                       /*!< SCU_GENERAL GORCEN: ENORC7 Position     */\r
+#define SCU_GENERAL_GORCEN_ENORC7_Msk         (0x01UL << SCU_GENERAL_GORCEN_ENORC7_Pos)               /*!< SCU_GENERAL GORCEN: ENORC7 Mask         */\r
+\r
+/* ----------------------------  SCU_GENERAL_DTEMPLIM  ---------------------------- */\r
+#define SCU_GENERAL_DTEMPLIM_LOWER_Pos        0                                                       /*!< SCU_GENERAL DTEMPLIM: LOWER Position    */\r
+#define SCU_GENERAL_DTEMPLIM_LOWER_Msk        (0x000003ffUL << SCU_GENERAL_DTEMPLIM_LOWER_Pos)        /*!< SCU_GENERAL DTEMPLIM: LOWER Mask        */\r
+#define SCU_GENERAL_DTEMPLIM_UPPER_Pos        16                                                      /*!< SCU_GENERAL DTEMPLIM: UPPER Position    */\r
+#define SCU_GENERAL_DTEMPLIM_UPPER_Msk        (0x000003ffUL << SCU_GENERAL_DTEMPLIM_UPPER_Pos)        /*!< SCU_GENERAL DTEMPLIM: UPPER Mask        */\r
+\r
+/* ---------------------------  SCU_GENERAL_DTEMPALARM  --------------------------- */\r
+#define SCU_GENERAL_DTEMPALARM_UNDERFL_Pos    0                                                       /*!< SCU_GENERAL DTEMPALARM: UNDERFL Position */\r
+#define SCU_GENERAL_DTEMPALARM_UNDERFL_Msk    (0x01UL << SCU_GENERAL_DTEMPALARM_UNDERFL_Pos)          /*!< SCU_GENERAL DTEMPALARM: UNDERFL Mask    */\r
+#define SCU_GENERAL_DTEMPALARM_OVERFL_Pos     16                                                      /*!< SCU_GENERAL DTEMPALARM: OVERFL Position */\r
+#define SCU_GENERAL_DTEMPALARM_OVERFL_Msk     (0x01UL << SCU_GENERAL_DTEMPALARM_OVERFL_Pos)           /*!< SCU_GENERAL DTEMPALARM: OVERFL Mask     */\r
+\r
+/* -----------------------------  SCU_GENERAL_MIRRSTS  ---------------------------- */\r
+#define SCU_GENERAL_MIRRSTS_HDCLR_Pos         1                                                       /*!< SCU_GENERAL MIRRSTS: HDCLR Position     */\r
+#define SCU_GENERAL_MIRRSTS_HDCLR_Msk         (0x01UL << SCU_GENERAL_MIRRSTS_HDCLR_Pos)               /*!< SCU_GENERAL MIRRSTS: HDCLR Mask         */\r
+#define SCU_GENERAL_MIRRSTS_HDSET_Pos         2                                                       /*!< SCU_GENERAL MIRRSTS: HDSET Position     */\r
+#define SCU_GENERAL_MIRRSTS_HDSET_Msk         (0x01UL << SCU_GENERAL_MIRRSTS_HDSET_Pos)               /*!< SCU_GENERAL MIRRSTS: HDSET Mask         */\r
+#define SCU_GENERAL_MIRRSTS_HDCR_Pos          3                                                       /*!< SCU_GENERAL MIRRSTS: HDCR Position      */\r
+#define SCU_GENERAL_MIRRSTS_HDCR_Msk          (0x01UL << SCU_GENERAL_MIRRSTS_HDCR_Pos)                /*!< SCU_GENERAL MIRRSTS: HDCR Mask          */\r
+#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos     5                                                       /*!< SCU_GENERAL MIRRSTS: OSCSICTRL Position */\r
+#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos)           /*!< SCU_GENERAL MIRRSTS: OSCSICTRL Mask     */\r
+#define SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos     6                                                       /*!< SCU_GENERAL MIRRSTS: OSCULSTAT Position */\r
+#define SCU_GENERAL_MIRRSTS_OSCULSTAT_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos)           /*!< SCU_GENERAL MIRRSTS: OSCULSTAT Mask     */\r
+#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos     7                                                       /*!< SCU_GENERAL MIRRSTS: OSCULCTRL Position */\r
+#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos)           /*!< SCU_GENERAL MIRRSTS: OSCULCTRL Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos       8                                                       /*!< SCU_GENERAL MIRRSTS: RTC_CTR Position   */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CTR_Pos)             /*!< SCU_GENERAL MIRRSTS: RTC_CTR Mask       */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos     9                                                       /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos     10                                                      /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos      11                                                      /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Position  */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk      (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos)            /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Mask      */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos      12                                                      /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Position  */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk      (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos)            /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Mask      */\r
+#define SCU_GENERAL_MIRRSTS_RMX_Pos           13                                                      /*!< SCU_GENERAL MIRRSTS: RMX Position       */\r
+#define SCU_GENERAL_MIRRSTS_RMX_Msk           (0x01UL << SCU_GENERAL_MIRRSTS_RMX_Pos)                 /*!< SCU_GENERAL MIRRSTS: RMX Mask           */\r
+#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos     14                                                      /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos     15                                                      /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR Mask     */\r
+#define SCU_GENERAL_MIRRSTS_LPACCONF_Pos      16                                                      /*!< SCU_GENERAL MIRRSTS: LPACCONF Position  */\r
+#define SCU_GENERAL_MIRRSTS_LPACCONF_Msk      (0x01UL << SCU_GENERAL_MIRRSTS_LPACCONF_Pos)            /*!< SCU_GENERAL MIRRSTS: LPACCONF Mask      */\r
+#define SCU_GENERAL_MIRRSTS_LPACTH0_Pos       17                                                      /*!< SCU_GENERAL MIRRSTS: LPACTH0 Position   */\r
+#define SCU_GENERAL_MIRRSTS_LPACTH0_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_LPACTH0_Pos)             /*!< SCU_GENERAL MIRRSTS: LPACTH0 Mask       */\r
+#define SCU_GENERAL_MIRRSTS_LPACTH1_Pos       18                                                      /*!< SCU_GENERAL MIRRSTS: LPACTH1 Position   */\r
+#define SCU_GENERAL_MIRRSTS_LPACTH1_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_LPACTH1_Pos)             /*!< SCU_GENERAL MIRRSTS: LPACTH1 Mask       */\r
+#define SCU_GENERAL_MIRRSTS_LPACCLR_Pos       20                                                      /*!< SCU_GENERAL MIRRSTS: LPACCLR Position   */\r
+#define SCU_GENERAL_MIRRSTS_LPACCLR_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_LPACCLR_Pos)             /*!< SCU_GENERAL MIRRSTS: LPACCLR Mask       */\r
+#define SCU_GENERAL_MIRRSTS_LPACSET_Pos       21                                                      /*!< SCU_GENERAL MIRRSTS: LPACSET Position   */\r
+#define SCU_GENERAL_MIRRSTS_LPACSET_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_LPACSET_Pos)             /*!< SCU_GENERAL MIRRSTS: LPACSET Mask       */\r
+#define SCU_GENERAL_MIRRSTS_HINTCLR_Pos       23                                                      /*!< SCU_GENERAL MIRRSTS: HINTCLR Position   */\r
+#define SCU_GENERAL_MIRRSTS_HINTCLR_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_HINTCLR_Pos)             /*!< SCU_GENERAL MIRRSTS: HINTCLR Mask       */\r
+#define SCU_GENERAL_MIRRSTS_HINTSET_Pos       24                                                      /*!< SCU_GENERAL MIRRSTS: HINTSET Position   */\r
+#define SCU_GENERAL_MIRRSTS_HINTSET_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_HINTSET_Pos)             /*!< SCU_GENERAL MIRRSTS: HINTSET Mask       */\r
+\r
+/* ------------------------------  SCU_GENERAL_RMACR  ----------------------------- */\r
+#define SCU_GENERAL_RMACR_RDWR_Pos            0                                                       /*!< SCU_GENERAL RMACR: RDWR Position        */\r
+#define SCU_GENERAL_RMACR_RDWR_Msk            (0x01UL << SCU_GENERAL_RMACR_RDWR_Pos)                  /*!< SCU_GENERAL RMACR: RDWR Mask            */\r
+#define SCU_GENERAL_RMACR_ADDR_Pos            16                                                      /*!< SCU_GENERAL RMACR: ADDR Position        */\r
+#define SCU_GENERAL_RMACR_ADDR_Msk            (0x0fUL << SCU_GENERAL_RMACR_ADDR_Pos)                  /*!< SCU_GENERAL RMACR: ADDR Mask            */\r
+\r
+/* -----------------------------  SCU_GENERAL_RMDATA  ----------------------------- */\r
+#define SCU_GENERAL_RMDATA_DATA_Pos           0                                                       /*!< SCU_GENERAL RMDATA: DATA Position       */\r
+#define SCU_GENERAL_RMDATA_DATA_Msk           (0xffffffffUL << SCU_GENERAL_RMDATA_DATA_Pos)           /*!< SCU_GENERAL RMDATA: DATA Mask           */\r
+\r
+/* ---------------------------  SCU_GENERAL_MIRRALLSTAT  -------------------------- */\r
+#define SCU_GENERAL_MIRRALLSTAT_BUSY_Pos      0                                                       /*!< SCU_GENERAL MIRRALLSTAT: BUSY Position  */\r
+#define SCU_GENERAL_MIRRALLSTAT_BUSY_Msk      (0x01UL << SCU_GENERAL_MIRRALLSTAT_BUSY_Pos)            /*!< SCU_GENERAL MIRRALLSTAT: BUSY Mask      */\r
+\r
+/* ---------------------------  SCU_GENERAL_MIRRALLREQ  --------------------------- */\r
+#define SCU_GENERAL_MIRRALLREQ_REQ_Pos        0                                                       /*!< SCU_GENERAL MIRRALLREQ: REQ Position    */\r
+#define SCU_GENERAL_MIRRALLREQ_REQ_Msk        (0x01UL << SCU_GENERAL_MIRRALLREQ_REQ_Pos)              /*!< SCU_GENERAL MIRRALLREQ: REQ Mask        */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================     struct 'SCU_INTERRUPT' Position & Mask     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------  SCU_INTERRUPT_SRSTAT  ---------------------------- */\r
+#define SCU_INTERRUPT_SRSTAT_PRWARN_Pos       0                                                       /*!< SCU_INTERRUPT SRSTAT: PRWARN Position   */\r
+#define SCU_INTERRUPT_SRSTAT_PRWARN_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_PRWARN_Pos)             /*!< SCU_INTERRUPT SRSTAT: PRWARN Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_PI_Pos           1                                                       /*!< SCU_INTERRUPT SRSTAT: PI Position       */\r
+#define SCU_INTERRUPT_SRSTAT_PI_Msk           (0x01UL << SCU_INTERRUPT_SRSTAT_PI_Pos)                 /*!< SCU_INTERRUPT SRSTAT: PI Mask           */\r
+#define SCU_INTERRUPT_SRSTAT_AI_Pos           2                                                       /*!< SCU_INTERRUPT SRSTAT: AI Position       */\r
+#define SCU_INTERRUPT_SRSTAT_AI_Msk           (0x01UL << SCU_INTERRUPT_SRSTAT_AI_Pos)                 /*!< SCU_INTERRUPT SRSTAT: AI Mask           */\r
+#define SCU_INTERRUPT_SRSTAT_DLROVR_Pos       3                                                       /*!< SCU_INTERRUPT SRSTAT: DLROVR Position   */\r
+#define SCU_INTERRUPT_SRSTAT_DLROVR_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_DLROVR_Pos)             /*!< SCU_INTERRUPT SRSTAT: DLROVR Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_LPACCR_Pos       6                                                       /*!< SCU_INTERRUPT SRSTAT: LPACCR Position   */\r
+#define SCU_INTERRUPT_SRSTAT_LPACCR_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_LPACCR_Pos)             /*!< SCU_INTERRUPT SRSTAT: LPACCR Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_LPACTH0_Pos      7                                                       /*!< SCU_INTERRUPT SRSTAT: LPACTH0 Position  */\r
+#define SCU_INTERRUPT_SRSTAT_LPACTH0_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_LPACTH0_Pos)            /*!< SCU_INTERRUPT SRSTAT: LPACTH0 Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_LPACTH1_Pos      8                                                       /*!< SCU_INTERRUPT SRSTAT: LPACTH1 Position  */\r
+#define SCU_INTERRUPT_SRSTAT_LPACTH1_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_LPACTH1_Pos)            /*!< SCU_INTERRUPT SRSTAT: LPACTH1 Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_LPACST_Pos       9                                                       /*!< SCU_INTERRUPT SRSTAT: LPACST Position   */\r
+#define SCU_INTERRUPT_SRSTAT_LPACST_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_LPACST_Pos)             /*!< SCU_INTERRUPT SRSTAT: LPACST Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_LPACCLR_Pos      10                                                      /*!< SCU_INTERRUPT SRSTAT: LPACCLR Position  */\r
+#define SCU_INTERRUPT_SRSTAT_LPACCLR_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_LPACCLR_Pos)            /*!< SCU_INTERRUPT SRSTAT: LPACCLR Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_LPACSET_Pos      11                                                      /*!< SCU_INTERRUPT SRSTAT: LPACSET Position  */\r
+#define SCU_INTERRUPT_SRSTAT_LPACSET_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_LPACSET_Pos)            /*!< SCU_INTERRUPT SRSTAT: LPACSET Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_HINTST_Pos       12                                                      /*!< SCU_INTERRUPT SRSTAT: HINTST Position   */\r
+#define SCU_INTERRUPT_SRSTAT_HINTST_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_HINTST_Pos)             /*!< SCU_INTERRUPT SRSTAT: HINTST Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_HINTCLR_Pos      13                                                      /*!< SCU_INTERRUPT SRSTAT: HINTCLR Position  */\r
+#define SCU_INTERRUPT_SRSTAT_HINTCLR_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_HINTCLR_Pos)            /*!< SCU_INTERRUPT SRSTAT: HINTCLR Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_HINTSET_Pos      14                                                      /*!< SCU_INTERRUPT SRSTAT: HINTSET Position  */\r
+#define SCU_INTERRUPT_SRSTAT_HINTSET_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_HINTSET_Pos)            /*!< SCU_INTERRUPT SRSTAT: HINTSET Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_HDSTAT_Pos       16                                                      /*!< SCU_INTERRUPT SRSTAT: HDSTAT Position   */\r
+#define SCU_INTERRUPT_SRSTAT_HDSTAT_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_HDSTAT_Pos)             /*!< SCU_INTERRUPT SRSTAT: HDSTAT Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_HDCLR_Pos        17                                                      /*!< SCU_INTERRUPT SRSTAT: HDCLR Position    */\r
+#define SCU_INTERRUPT_SRSTAT_HDCLR_Msk        (0x01UL << SCU_INTERRUPT_SRSTAT_HDCLR_Pos)              /*!< SCU_INTERRUPT SRSTAT: HDCLR Mask        */\r
+#define SCU_INTERRUPT_SRSTAT_HDSET_Pos        18                                                      /*!< SCU_INTERRUPT SRSTAT: HDSET Position    */\r
+#define SCU_INTERRUPT_SRSTAT_HDSET_Msk        (0x01UL << SCU_INTERRUPT_SRSTAT_HDSET_Pos)              /*!< SCU_INTERRUPT SRSTAT: HDSET Mask        */\r
+#define SCU_INTERRUPT_SRSTAT_HDCR_Pos         19                                                      /*!< SCU_INTERRUPT SRSTAT: HDCR Position     */\r
+#define SCU_INTERRUPT_SRSTAT_HDCR_Msk         (0x01UL << SCU_INTERRUPT_SRSTAT_HDCR_Pos)               /*!< SCU_INTERRUPT SRSTAT: HDCR Mask         */\r
+#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos    21                                                      /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos)          /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos    22                                                      /*!< SCU_INTERRUPT SRSTAT: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos)          /*!< SCU_INTERRUPT SRSTAT: OSCULSTAT Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos    23                                                      /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos)          /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos      24                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_CTR Position  */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos)            /*!< SCU_INTERRUPT SRSTAT: RTC_CTR Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos    25                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos)          /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos    26                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos)          /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos     27                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk     (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos)           /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 Mask     */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos     28                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk     (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos)           /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 Mask     */\r
+#define SCU_INTERRUPT_SRSTAT_RMX_Pos          29                                                      /*!< SCU_INTERRUPT SRSTAT: RMX Position      */\r
+#define SCU_INTERRUPT_SRSTAT_RMX_Msk          (0x01UL << SCU_INTERRUPT_SRSTAT_RMX_Pos)                /*!< SCU_INTERRUPT SRSTAT: RMX Mask          */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRRAW  ---------------------------- */\r
+#define SCU_INTERRUPT_SRRAW_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRRAW: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRRAW_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_PRWARN_Pos)              /*!< SCU_INTERRUPT SRRAW: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRRAW_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRRAW: PI Position        */\r
+#define SCU_INTERRUPT_SRRAW_PI_Msk            (0x01UL << SCU_INTERRUPT_SRRAW_PI_Pos)                  /*!< SCU_INTERRUPT SRRAW: PI Mask            */\r
+#define SCU_INTERRUPT_SRRAW_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRRAW: AI Position        */\r
+#define SCU_INTERRUPT_SRRAW_AI_Msk            (0x01UL << SCU_INTERRUPT_SRRAW_AI_Pos)                  /*!< SCU_INTERRUPT SRRAW: AI Mask            */\r
+#define SCU_INTERRUPT_SRRAW_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRRAW: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRRAW_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_DLROVR_Pos)              /*!< SCU_INTERRUPT SRRAW: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRRAW_LPACCR_Pos        6                                                       /*!< SCU_INTERRUPT SRRAW: LPACCR Position    */\r
+#define SCU_INTERRUPT_SRRAW_LPACCR_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_LPACCR_Pos)              /*!< SCU_INTERRUPT SRRAW: LPACCR Mask        */\r
+#define SCU_INTERRUPT_SRRAW_LPACTH0_Pos       7                                                       /*!< SCU_INTERRUPT SRRAW: LPACTH0 Position   */\r
+#define SCU_INTERRUPT_SRRAW_LPACTH0_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_LPACTH0_Pos)             /*!< SCU_INTERRUPT SRRAW: LPACTH0 Mask       */\r
+#define SCU_INTERRUPT_SRRAW_LPACTH1_Pos       8                                                       /*!< SCU_INTERRUPT SRRAW: LPACTH1 Position   */\r
+#define SCU_INTERRUPT_SRRAW_LPACTH1_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_LPACTH1_Pos)             /*!< SCU_INTERRUPT SRRAW: LPACTH1 Mask       */\r
+#define SCU_INTERRUPT_SRRAW_LPACST_Pos        9                                                       /*!< SCU_INTERRUPT SRRAW: LPACST Position    */\r
+#define SCU_INTERRUPT_SRRAW_LPACST_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_LPACST_Pos)              /*!< SCU_INTERRUPT SRRAW: LPACST Mask        */\r
+#define SCU_INTERRUPT_SRRAW_LPACCLR_Pos       10                                                      /*!< SCU_INTERRUPT SRRAW: LPACCLR Position   */\r
+#define SCU_INTERRUPT_SRRAW_LPACCLR_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_LPACCLR_Pos)             /*!< SCU_INTERRUPT SRRAW: LPACCLR Mask       */\r
+#define SCU_INTERRUPT_SRRAW_LPACSET_Pos       11                                                      /*!< SCU_INTERRUPT SRRAW: LPACSET Position   */\r
+#define SCU_INTERRUPT_SRRAW_LPACSET_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_LPACSET_Pos)             /*!< SCU_INTERRUPT SRRAW: LPACSET Mask       */\r
+#define SCU_INTERRUPT_SRRAW_HINTST_Pos        12                                                      /*!< SCU_INTERRUPT SRRAW: HINTST Position    */\r
+#define SCU_INTERRUPT_SRRAW_HINTST_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_HINTST_Pos)              /*!< SCU_INTERRUPT SRRAW: HINTST Mask        */\r
+#define SCU_INTERRUPT_SRRAW_HINTCLR_Pos       13                                                      /*!< SCU_INTERRUPT SRRAW: HINTCLR Position   */\r
+#define SCU_INTERRUPT_SRRAW_HINTCLR_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_HINTCLR_Pos)             /*!< SCU_INTERRUPT SRRAW: HINTCLR Mask       */\r
+#define SCU_INTERRUPT_SRRAW_HINTSET_Pos       14                                                      /*!< SCU_INTERRUPT SRRAW: HINTSET Position   */\r
+#define SCU_INTERRUPT_SRRAW_HINTSET_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_HINTSET_Pos)             /*!< SCU_INTERRUPT SRRAW: HINTSET Mask       */\r
+#define SCU_INTERRUPT_SRRAW_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRRAW: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRRAW_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRRAW: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRRAW_HDCLR_Pos         17                                                      /*!< SCU_INTERRUPT SRRAW: HDCLR Position     */\r
+#define SCU_INTERRUPT_SRRAW_HDCLR_Msk         (0x01UL << SCU_INTERRUPT_SRRAW_HDCLR_Pos)               /*!< SCU_INTERRUPT SRRAW: HDCLR Mask         */\r
+#define SCU_INTERRUPT_SRRAW_HDSET_Pos         18                                                      /*!< SCU_INTERRUPT SRRAW: HDSET Position     */\r
+#define SCU_INTERRUPT_SRRAW_HDSET_Msk         (0x01UL << SCU_INTERRUPT_SRRAW_HDSET_Pos)               /*!< SCU_INTERRUPT SRRAW: HDSET Mask         */\r
+#define SCU_INTERRUPT_SRRAW_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRRAW: HDCR Position      */\r
+#define SCU_INTERRUPT_SRRAW_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRRAW_HDCR_Pos)                /*!< SCU_INTERRUPT SRRAW: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRRAW: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRRAW: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRRAW: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRRAW_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRRAW: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRRAW: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRRAW: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRRAW: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRRAW: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRRAW_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRRAW: RMX Position       */\r
+#define SCU_INTERRUPT_SRRAW_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRRAW_RMX_Pos)                 /*!< SCU_INTERRUPT SRRAW: RMX Mask           */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRMSK  ---------------------------- */\r
+#define SCU_INTERRUPT_SRMSK_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRMSK: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRMSK_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_PRWARN_Pos)              /*!< SCU_INTERRUPT SRMSK: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRMSK_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRMSK: PI Position        */\r
+#define SCU_INTERRUPT_SRMSK_PI_Msk            (0x01UL << SCU_INTERRUPT_SRMSK_PI_Pos)                  /*!< SCU_INTERRUPT SRMSK: PI Mask            */\r
+#define SCU_INTERRUPT_SRMSK_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRMSK: AI Position        */\r
+#define SCU_INTERRUPT_SRMSK_AI_Msk            (0x01UL << SCU_INTERRUPT_SRMSK_AI_Pos)                  /*!< SCU_INTERRUPT SRMSK: AI Mask            */\r
+#define SCU_INTERRUPT_SRMSK_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRMSK: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRMSK_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_DLROVR_Pos)              /*!< SCU_INTERRUPT SRMSK: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRMSK_LPACCR_Pos        6                                                       /*!< SCU_INTERRUPT SRMSK: LPACCR Position    */\r
+#define SCU_INTERRUPT_SRMSK_LPACCR_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_LPACCR_Pos)              /*!< SCU_INTERRUPT SRMSK: LPACCR Mask        */\r
+#define SCU_INTERRUPT_SRMSK_LPACTH0_Pos       7                                                       /*!< SCU_INTERRUPT SRMSK: LPACTH0 Position   */\r
+#define SCU_INTERRUPT_SRMSK_LPACTH0_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_LPACTH0_Pos)             /*!< SCU_INTERRUPT SRMSK: LPACTH0 Mask       */\r
+#define SCU_INTERRUPT_SRMSK_LPACTH1_Pos       8                                                       /*!< SCU_INTERRUPT SRMSK: LPACTH1 Position   */\r
+#define SCU_INTERRUPT_SRMSK_LPACTH1_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_LPACTH1_Pos)             /*!< SCU_INTERRUPT SRMSK: LPACTH1 Mask       */\r
+#define SCU_INTERRUPT_SRMSK_LPACST_Pos        9                                                       /*!< SCU_INTERRUPT SRMSK: LPACST Position    */\r
+#define SCU_INTERRUPT_SRMSK_LPACST_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_LPACST_Pos)              /*!< SCU_INTERRUPT SRMSK: LPACST Mask        */\r
+#define SCU_INTERRUPT_SRMSK_LPACCLR_Pos       10                                                      /*!< SCU_INTERRUPT SRMSK: LPACCLR Position   */\r
+#define SCU_INTERRUPT_SRMSK_LPACCLR_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_LPACCLR_Pos)             /*!< SCU_INTERRUPT SRMSK: LPACCLR Mask       */\r
+#define SCU_INTERRUPT_SRMSK_LPACSET_Pos       11                                                      /*!< SCU_INTERRUPT SRMSK: LPACSET Position   */\r
+#define SCU_INTERRUPT_SRMSK_LPACSET_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_LPACSET_Pos)             /*!< SCU_INTERRUPT SRMSK: LPACSET Mask       */\r
+#define SCU_INTERRUPT_SRMSK_HINTST_Pos        12                                                      /*!< SCU_INTERRUPT SRMSK: HINTST Position    */\r
+#define SCU_INTERRUPT_SRMSK_HINTST_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_HINTST_Pos)              /*!< SCU_INTERRUPT SRMSK: HINTST Mask        */\r
+#define SCU_INTERRUPT_SRMSK_HINTCLR_Pos       13                                                      /*!< SCU_INTERRUPT SRMSK: HINTCLR Position   */\r
+#define SCU_INTERRUPT_SRMSK_HINTCLR_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_HINTCLR_Pos)             /*!< SCU_INTERRUPT SRMSK: HINTCLR Mask       */\r
+#define SCU_INTERRUPT_SRMSK_HINTSET_Pos       14                                                      /*!< SCU_INTERRUPT SRMSK: HINTSET Position   */\r
+#define SCU_INTERRUPT_SRMSK_HINTSET_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_HINTSET_Pos)             /*!< SCU_INTERRUPT SRMSK: HINTSET Mask       */\r
+#define SCU_INTERRUPT_SRMSK_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRMSK: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRMSK_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRMSK: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRMSK_HDCLR_Pos         17                                                      /*!< SCU_INTERRUPT SRMSK: HDCLR Position     */\r
+#define SCU_INTERRUPT_SRMSK_HDCLR_Msk         (0x01UL << SCU_INTERRUPT_SRMSK_HDCLR_Pos)               /*!< SCU_INTERRUPT SRMSK: HDCLR Mask         */\r
+#define SCU_INTERRUPT_SRMSK_HDSET_Pos         18                                                      /*!< SCU_INTERRUPT SRMSK: HDSET Position     */\r
+#define SCU_INTERRUPT_SRMSK_HDSET_Msk         (0x01UL << SCU_INTERRUPT_SRMSK_HDSET_Pos)               /*!< SCU_INTERRUPT SRMSK: HDSET Mask         */\r
+#define SCU_INTERRUPT_SRMSK_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRMSK: HDCR Position      */\r
+#define SCU_INTERRUPT_SRMSK_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRMSK_HDCR_Pos)                /*!< SCU_INTERRUPT SRMSK: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRMSK: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRMSK: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRMSK: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRMSK_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRMSK: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRMSK: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRMSK: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRMSK: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRMSK: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRMSK_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRMSK: RMX Position       */\r
+#define SCU_INTERRUPT_SRMSK_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRMSK_RMX_Pos)                 /*!< SCU_INTERRUPT SRMSK: RMX Mask           */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRCLR  ---------------------------- */\r
+#define SCU_INTERRUPT_SRCLR_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRCLR: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRCLR_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_PRWARN_Pos)              /*!< SCU_INTERRUPT SRCLR: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRCLR_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRCLR: PI Position        */\r
+#define SCU_INTERRUPT_SRCLR_PI_Msk            (0x01UL << SCU_INTERRUPT_SRCLR_PI_Pos)                  /*!< SCU_INTERRUPT SRCLR: PI Mask            */\r
+#define SCU_INTERRUPT_SRCLR_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRCLR: AI Position        */\r
+#define SCU_INTERRUPT_SRCLR_AI_Msk            (0x01UL << SCU_INTERRUPT_SRCLR_AI_Pos)                  /*!< SCU_INTERRUPT SRCLR: AI Mask            */\r
+#define SCU_INTERRUPT_SRCLR_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRCLR: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRCLR_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_DLROVR_Pos)              /*!< SCU_INTERRUPT SRCLR: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRCLR_LPACCR_Pos        6                                                       /*!< SCU_INTERRUPT SRCLR: LPACCR Position    */\r
+#define SCU_INTERRUPT_SRCLR_LPACCR_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_LPACCR_Pos)              /*!< SCU_INTERRUPT SRCLR: LPACCR Mask        */\r
+#define SCU_INTERRUPT_SRCLR_LPACTH0_Pos       7                                                       /*!< SCU_INTERRUPT SRCLR: LPACTH0 Position   */\r
+#define SCU_INTERRUPT_SRCLR_LPACTH0_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_LPACTH0_Pos)             /*!< SCU_INTERRUPT SRCLR: LPACTH0 Mask       */\r
+#define SCU_INTERRUPT_SRCLR_LPACTH1_Pos       8                                                       /*!< SCU_INTERRUPT SRCLR: LPACTH1 Position   */\r
+#define SCU_INTERRUPT_SRCLR_LPACTH1_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_LPACTH1_Pos)             /*!< SCU_INTERRUPT SRCLR: LPACTH1 Mask       */\r
+#define SCU_INTERRUPT_SRCLR_LPACST_Pos        9                                                       /*!< SCU_INTERRUPT SRCLR: LPACST Position    */\r
+#define SCU_INTERRUPT_SRCLR_LPACST_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_LPACST_Pos)              /*!< SCU_INTERRUPT SRCLR: LPACST Mask        */\r
+#define SCU_INTERRUPT_SRCLR_LPACCLR_Pos       10                                                      /*!< SCU_INTERRUPT SRCLR: LPACCLR Position   */\r
+#define SCU_INTERRUPT_SRCLR_LPACCLR_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_LPACCLR_Pos)             /*!< SCU_INTERRUPT SRCLR: LPACCLR Mask       */\r
+#define SCU_INTERRUPT_SRCLR_LPACSET_Pos       11                                                      /*!< SCU_INTERRUPT SRCLR: LPACSET Position   */\r
+#define SCU_INTERRUPT_SRCLR_LPACSET_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_LPACSET_Pos)             /*!< SCU_INTERRUPT SRCLR: LPACSET Mask       */\r
+#define SCU_INTERRUPT_SRCLR_HINTST_Pos        12                                                      /*!< SCU_INTERRUPT SRCLR: HINTST Position    */\r
+#define SCU_INTERRUPT_SRCLR_HINTST_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_HINTST_Pos)              /*!< SCU_INTERRUPT SRCLR: HINTST Mask        */\r
+#define SCU_INTERRUPT_SRCLR_HINTCLR_Pos       13                                                      /*!< SCU_INTERRUPT SRCLR: HINTCLR Position   */\r
+#define SCU_INTERRUPT_SRCLR_HINTCLR_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_HINTCLR_Pos)             /*!< SCU_INTERRUPT SRCLR: HINTCLR Mask       */\r
+#define SCU_INTERRUPT_SRCLR_HINTSET_Pos       14                                                      /*!< SCU_INTERRUPT SRCLR: HINTSET Position   */\r
+#define SCU_INTERRUPT_SRCLR_HINTSET_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_HINTSET_Pos)             /*!< SCU_INTERRUPT SRCLR: HINTSET Mask       */\r
+#define SCU_INTERRUPT_SRCLR_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRCLR: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRCLR_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRCLR: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRCLR_HDCLR_Pos         17                                                      /*!< SCU_INTERRUPT SRCLR: HDCLR Position     */\r
+#define SCU_INTERRUPT_SRCLR_HDCLR_Msk         (0x01UL << SCU_INTERRUPT_SRCLR_HDCLR_Pos)               /*!< SCU_INTERRUPT SRCLR: HDCLR Mask         */\r
+#define SCU_INTERRUPT_SRCLR_HDSET_Pos         18                                                      /*!< SCU_INTERRUPT SRCLR: HDSET Position     */\r
+#define SCU_INTERRUPT_SRCLR_HDSET_Msk         (0x01UL << SCU_INTERRUPT_SRCLR_HDSET_Pos)               /*!< SCU_INTERRUPT SRCLR: HDSET Mask         */\r
+#define SCU_INTERRUPT_SRCLR_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRCLR: HDCR Position      */\r
+#define SCU_INTERRUPT_SRCLR_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRCLR_HDCR_Pos)                /*!< SCU_INTERRUPT SRCLR: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRCLR: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRCLR: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRCLR: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRCLR_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRCLR: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRCLR: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRCLR: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRCLR: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRCLR: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRCLR_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRCLR: RMX Position       */\r
+#define SCU_INTERRUPT_SRCLR_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRCLR_RMX_Pos)                 /*!< SCU_INTERRUPT SRCLR: RMX Mask           */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRSET  ---------------------------- */\r
+#define SCU_INTERRUPT_SRSET_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRSET: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRSET_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRSET_PRWARN_Pos)              /*!< SCU_INTERRUPT SRSET: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRSET_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRSET: PI Position        */\r
+#define SCU_INTERRUPT_SRSET_PI_Msk            (0x01UL << SCU_INTERRUPT_SRSET_PI_Pos)                  /*!< SCU_INTERRUPT SRSET: PI Mask            */\r
+#define SCU_INTERRUPT_SRSET_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRSET: AI Position        */\r
+#define SCU_INTERRUPT_SRSET_AI_Msk            (0x01UL << SCU_INTERRUPT_SRSET_AI_Pos)                  /*!< SCU_INTERRUPT SRSET: AI Mask            */\r
+#define SCU_INTERRUPT_SRSET_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRSET: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRSET_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRSET_DLROVR_Pos)              /*!< SCU_INTERRUPT SRSET: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRSET_LPACCR_Pos        6                                                       /*!< SCU_INTERRUPT SRSET: LPACCR Position    */\r
+#define SCU_INTERRUPT_SRSET_LPACCR_Msk        (0x01UL << SCU_INTERRUPT_SRSET_LPACCR_Pos)              /*!< SCU_INTERRUPT SRSET: LPACCR Mask        */\r
+#define SCU_INTERRUPT_SRSET_LPACTH0_Pos       7                                                       /*!< SCU_INTERRUPT SRSET: LPACTH0 Position   */\r
+#define SCU_INTERRUPT_SRSET_LPACTH0_Msk       (0x01UL << SCU_INTERRUPT_SRSET_LPACTH0_Pos)             /*!< SCU_INTERRUPT SRSET: LPACTH0 Mask       */\r
+#define SCU_INTERRUPT_SRSET_LPACTH1_Pos       8                                                       /*!< SCU_INTERRUPT SRSET: LPACTH1 Position   */\r
+#define SCU_INTERRUPT_SRSET_LPACTH1_Msk       (0x01UL << SCU_INTERRUPT_SRSET_LPACTH1_Pos)             /*!< SCU_INTERRUPT SRSET: LPACTH1 Mask       */\r
+#define SCU_INTERRUPT_SRSET_LPACST_Pos        9                                                       /*!< SCU_INTERRUPT SRSET: LPACST Position    */\r
+#define SCU_INTERRUPT_SRSET_LPACST_Msk        (0x01UL << SCU_INTERRUPT_SRSET_LPACST_Pos)              /*!< SCU_INTERRUPT SRSET: LPACST Mask        */\r
+#define SCU_INTERRUPT_SRSET_LPACCLR_Pos       10                                                      /*!< SCU_INTERRUPT SRSET: LPACCLR Position   */\r
+#define SCU_INTERRUPT_SRSET_LPACCLR_Msk       (0x01UL << SCU_INTERRUPT_SRSET_LPACCLR_Pos)             /*!< SCU_INTERRUPT SRSET: LPACCLR Mask       */\r
+#define SCU_INTERRUPT_SRSET_LPACSET_Pos       11                                                      /*!< SCU_INTERRUPT SRSET: LPACSET Position   */\r
+#define SCU_INTERRUPT_SRSET_LPACSET_Msk       (0x01UL << SCU_INTERRUPT_SRSET_LPACSET_Pos)             /*!< SCU_INTERRUPT SRSET: LPACSET Mask       */\r
+#define SCU_INTERRUPT_SRSET_HINTST_Pos        12                                                      /*!< SCU_INTERRUPT SRSET: HINTST Position    */\r
+#define SCU_INTERRUPT_SRSET_HINTST_Msk        (0x01UL << SCU_INTERRUPT_SRSET_HINTST_Pos)              /*!< SCU_INTERRUPT SRSET: HINTST Mask        */\r
+#define SCU_INTERRUPT_SRSET_HINTCLR_Pos       13                                                      /*!< SCU_INTERRUPT SRSET: HINTCLR Position   */\r
+#define SCU_INTERRUPT_SRSET_HINTCLR_Msk       (0x01UL << SCU_INTERRUPT_SRSET_HINTCLR_Pos)             /*!< SCU_INTERRUPT SRSET: HINTCLR Mask       */\r
+#define SCU_INTERRUPT_SRSET_HINTSET_Pos       14                                                      /*!< SCU_INTERRUPT SRSET: HINTSET Position   */\r
+#define SCU_INTERRUPT_SRSET_HINTSET_Msk       (0x01UL << SCU_INTERRUPT_SRSET_HINTSET_Pos)             /*!< SCU_INTERRUPT SRSET: HINTSET Mask       */\r
+#define SCU_INTERRUPT_SRSET_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRSET: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRSET_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRSET_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRSET: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRSET_HDCRCLR_Pos       17                                                      /*!< SCU_INTERRUPT SRSET: HDCRCLR Position   */\r
+#define SCU_INTERRUPT_SRSET_HDCRCLR_Msk       (0x01UL << SCU_INTERRUPT_SRSET_HDCRCLR_Pos)             /*!< SCU_INTERRUPT SRSET: HDCRCLR Mask       */\r
+#define SCU_INTERRUPT_SRSET_HDCRSET_Pos       18                                                      /*!< SCU_INTERRUPT SRSET: HDCRSET Position   */\r
+#define SCU_INTERRUPT_SRSET_HDCRSET_Msk       (0x01UL << SCU_INTERRUPT_SRSET_HDCRSET_Pos)             /*!< SCU_INTERRUPT SRSET: HDCRSET Mask       */\r
+#define SCU_INTERRUPT_SRSET_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRSET: HDCR Position      */\r
+#define SCU_INTERRUPT_SRSET_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRSET_HDCR_Pos)                /*!< SCU_INTERRUPT SRSET: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRSET_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRSET: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRSET_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRSET_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRSET: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRSET_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRSET: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRSET_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRSET_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRSET: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRSET_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRSET: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRSET_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRSET_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRSET: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRSET_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRSET: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRSET_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRSET_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRSET: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRSET_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRSET: RMX Position       */\r
+#define SCU_INTERRUPT_SRSET_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRSET_RMX_Pos)                 /*!< SCU_INTERRUPT SRSET: RMX Mask           */\r
+\r
+/* ---------------------------  SCU_INTERRUPT_NMIREQEN  --------------------------- */\r
+#define SCU_INTERRUPT_NMIREQEN_PRWARN_Pos     0                                                       /*!< SCU_INTERRUPT NMIREQEN: PRWARN Position */\r
+#define SCU_INTERRUPT_NMIREQEN_PRWARN_Msk     (0x01UL << SCU_INTERRUPT_NMIREQEN_PRWARN_Pos)           /*!< SCU_INTERRUPT NMIREQEN: PRWARN Mask     */\r
+#define SCU_INTERRUPT_NMIREQEN_PI_Pos         1                                                       /*!< SCU_INTERRUPT NMIREQEN: PI Position     */\r
+#define SCU_INTERRUPT_NMIREQEN_PI_Msk         (0x01UL << SCU_INTERRUPT_NMIREQEN_PI_Pos)               /*!< SCU_INTERRUPT NMIREQEN: PI Mask         */\r
+#define SCU_INTERRUPT_NMIREQEN_AI_Pos         2                                                       /*!< SCU_INTERRUPT NMIREQEN: AI Position     */\r
+#define SCU_INTERRUPT_NMIREQEN_AI_Msk         (0x01UL << SCU_INTERRUPT_NMIREQEN_AI_Pos)               /*!< SCU_INTERRUPT NMIREQEN: AI Mask         */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU00_Pos      16                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU00 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU00_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU00_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU00 Mask      */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU01_Pos      17                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU01 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU01_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU01_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU01 Mask      */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU02_Pos      18                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU02 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU02_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU02_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU02 Mask      */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU03_Pos      19                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU03 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU03_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU03_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU03 Mask      */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       struct 'SCU_PARITY' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_PARITY_PEEN  ------------------------------ */\r
+#define SCU_PARITY_PEEN_PEENPS_Pos            0                                                       /*!< SCU_PARITY PEEN: PEENPS Position        */\r
+#define SCU_PARITY_PEEN_PEENPS_Msk            (0x01UL << SCU_PARITY_PEEN_PEENPS_Pos)                  /*!< SCU_PARITY PEEN: PEENPS Mask            */\r
+#define SCU_PARITY_PEEN_PEENDS1_Pos           1                                                       /*!< SCU_PARITY PEEN: PEENDS1 Position       */\r
+#define SCU_PARITY_PEEN_PEENDS1_Msk           (0x01UL << SCU_PARITY_PEEN_PEENDS1_Pos)                 /*!< SCU_PARITY PEEN: PEENDS1 Mask           */\r
+#define SCU_PARITY_PEEN_PEENDS2_Pos           2                                                       /*!< SCU_PARITY PEEN: PEENDS2 Position       */\r
+#define SCU_PARITY_PEEN_PEENDS2_Msk           (0x01UL << SCU_PARITY_PEEN_PEENDS2_Pos)                 /*!< SCU_PARITY PEEN: PEENDS2 Mask           */\r
+#define SCU_PARITY_PEEN_PEENU0_Pos            8                                                       /*!< SCU_PARITY PEEN: PEENU0 Position        */\r
+#define SCU_PARITY_PEEN_PEENU0_Msk            (0x01UL << SCU_PARITY_PEEN_PEENU0_Pos)                  /*!< SCU_PARITY PEEN: PEENU0 Mask            */\r
+#define SCU_PARITY_PEEN_PEENU1_Pos            9                                                       /*!< SCU_PARITY PEEN: PEENU1 Position        */\r
+#define SCU_PARITY_PEEN_PEENU1_Msk            (0x01UL << SCU_PARITY_PEEN_PEENU1_Pos)                  /*!< SCU_PARITY PEEN: PEENU1 Mask            */\r
+#define SCU_PARITY_PEEN_PEENMC_Pos            12                                                      /*!< SCU_PARITY PEEN: PEENMC Position        */\r
+#define SCU_PARITY_PEEN_PEENMC_Msk            (0x01UL << SCU_PARITY_PEEN_PEENMC_Pos)                  /*!< SCU_PARITY PEEN: PEENMC Mask            */\r
+#define SCU_PARITY_PEEN_PEENPPRF_Pos          13                                                      /*!< SCU_PARITY PEEN: PEENPPRF Position      */\r
+#define SCU_PARITY_PEEN_PEENPPRF_Msk          (0x01UL << SCU_PARITY_PEEN_PEENPPRF_Pos)                /*!< SCU_PARITY PEEN: PEENPPRF Mask          */\r
+#define SCU_PARITY_PEEN_PEENUSB_Pos           16                                                      /*!< SCU_PARITY PEEN: PEENUSB Position       */\r
+#define SCU_PARITY_PEEN_PEENUSB_Msk           (0x01UL << SCU_PARITY_PEEN_PEENUSB_Pos)                 /*!< SCU_PARITY PEEN: PEENUSB Mask           */\r
+#define SCU_PARITY_PEEN_PEENETH0TX_Pos        17                                                      /*!< SCU_PARITY PEEN: PEENETH0TX Position    */\r
+#define SCU_PARITY_PEEN_PEENETH0TX_Msk        (0x01UL << SCU_PARITY_PEEN_PEENETH0TX_Pos)              /*!< SCU_PARITY PEEN: PEENETH0TX Mask        */\r
+#define SCU_PARITY_PEEN_PEENETH0RX_Pos        18                                                      /*!< SCU_PARITY PEEN: PEENETH0RX Position    */\r
+#define SCU_PARITY_PEEN_PEENETH0RX_Msk        (0x01UL << SCU_PARITY_PEEN_PEENETH0RX_Pos)              /*!< SCU_PARITY PEEN: PEENETH0RX Mask        */\r
+\r
+/* -----------------------------  SCU_PARITY_MCHKCON  ----------------------------- */\r
+#define SCU_PARITY_MCHKCON_SELPS_Pos          0                                                       /*!< SCU_PARITY MCHKCON: SELPS Position      */\r
+#define SCU_PARITY_MCHKCON_SELPS_Msk          (0x01UL << SCU_PARITY_MCHKCON_SELPS_Pos)                /*!< SCU_PARITY MCHKCON: SELPS Mask          */\r
+#define SCU_PARITY_MCHKCON_SELDS1_Pos         1                                                       /*!< SCU_PARITY MCHKCON: SELDS1 Position     */\r
+#define SCU_PARITY_MCHKCON_SELDS1_Msk         (0x01UL << SCU_PARITY_MCHKCON_SELDS1_Pos)               /*!< SCU_PARITY MCHKCON: SELDS1 Mask         */\r
+#define SCU_PARITY_MCHKCON_SELDS2_Pos         2                                                       /*!< SCU_PARITY MCHKCON: SELDS2 Position     */\r
+#define SCU_PARITY_MCHKCON_SELDS2_Msk         (0x01UL << SCU_PARITY_MCHKCON_SELDS2_Pos)               /*!< SCU_PARITY MCHKCON: SELDS2 Mask         */\r
+#define SCU_PARITY_MCHKCON_USIC0DRA_Pos       8                                                       /*!< SCU_PARITY MCHKCON: USIC0DRA Position   */\r
+#define SCU_PARITY_MCHKCON_USIC0DRA_Msk       (0x01UL << SCU_PARITY_MCHKCON_USIC0DRA_Pos)             /*!< SCU_PARITY MCHKCON: USIC0DRA Mask       */\r
+#define SCU_PARITY_MCHKCON_USIC1DRA_Pos       9                                                       /*!< SCU_PARITY MCHKCON: USIC1DRA Position   */\r
+#define SCU_PARITY_MCHKCON_USIC1DRA_Msk       (0x01UL << SCU_PARITY_MCHKCON_USIC1DRA_Pos)             /*!< SCU_PARITY MCHKCON: USIC1DRA Mask       */\r
+#define SCU_PARITY_MCHKCON_MCANDRA_Pos        12                                                      /*!< SCU_PARITY MCHKCON: MCANDRA Position    */\r
+#define SCU_PARITY_MCHKCON_MCANDRA_Msk        (0x01UL << SCU_PARITY_MCHKCON_MCANDRA_Pos)              /*!< SCU_PARITY MCHKCON: MCANDRA Mask        */\r
+#define SCU_PARITY_MCHKCON_PPRFDRA_Pos        13                                                      /*!< SCU_PARITY MCHKCON: PPRFDRA Position    */\r
+#define SCU_PARITY_MCHKCON_PPRFDRA_Msk        (0x01UL << SCU_PARITY_MCHKCON_PPRFDRA_Pos)              /*!< SCU_PARITY MCHKCON: PPRFDRA Mask        */\r
+#define SCU_PARITY_MCHKCON_SELUSB_Pos         16                                                      /*!< SCU_PARITY MCHKCON: SELUSB Position     */\r
+#define SCU_PARITY_MCHKCON_SELUSB_Msk         (0x01UL << SCU_PARITY_MCHKCON_SELUSB_Pos)               /*!< SCU_PARITY MCHKCON: SELUSB Mask         */\r
+#define SCU_PARITY_MCHKCON_SELETH0TX_Pos      17                                                      /*!< SCU_PARITY MCHKCON: SELETH0TX Position  */\r
+#define SCU_PARITY_MCHKCON_SELETH0TX_Msk      (0x01UL << SCU_PARITY_MCHKCON_SELETH0TX_Pos)            /*!< SCU_PARITY MCHKCON: SELETH0TX Mask      */\r
+#define SCU_PARITY_MCHKCON_SELETH0RX_Pos      18                                                      /*!< SCU_PARITY MCHKCON: SELETH0RX Position  */\r
+#define SCU_PARITY_MCHKCON_SELETH0RX_Msk      (0x01UL << SCU_PARITY_MCHKCON_SELETH0RX_Pos)            /*!< SCU_PARITY MCHKCON: SELETH0RX Mask      */\r
+\r
+/* -------------------------------  SCU_PARITY_PETE  ------------------------------ */\r
+#define SCU_PARITY_PETE_PETEPS_Pos            0                                                       /*!< SCU_PARITY PETE: PETEPS Position        */\r
+#define SCU_PARITY_PETE_PETEPS_Msk            (0x01UL << SCU_PARITY_PETE_PETEPS_Pos)                  /*!< SCU_PARITY PETE: PETEPS Mask            */\r
+#define SCU_PARITY_PETE_PETEDS1_Pos           1                                                       /*!< SCU_PARITY PETE: PETEDS1 Position       */\r
+#define SCU_PARITY_PETE_PETEDS1_Msk           (0x01UL << SCU_PARITY_PETE_PETEDS1_Pos)                 /*!< SCU_PARITY PETE: PETEDS1 Mask           */\r
+#define SCU_PARITY_PETE_PETEDS2_Pos           2                                                       /*!< SCU_PARITY PETE: PETEDS2 Position       */\r
+#define SCU_PARITY_PETE_PETEDS2_Msk           (0x01UL << SCU_PARITY_PETE_PETEDS2_Pos)                 /*!< SCU_PARITY PETE: PETEDS2 Mask           */\r
+#define SCU_PARITY_PETE_PETEU0_Pos            8                                                       /*!< SCU_PARITY PETE: PETEU0 Position        */\r
+#define SCU_PARITY_PETE_PETEU0_Msk            (0x01UL << SCU_PARITY_PETE_PETEU0_Pos)                  /*!< SCU_PARITY PETE: PETEU0 Mask            */\r
+#define SCU_PARITY_PETE_PETEU1_Pos            9                                                       /*!< SCU_PARITY PETE: PETEU1 Position        */\r
+#define SCU_PARITY_PETE_PETEU1_Msk            (0x01UL << SCU_PARITY_PETE_PETEU1_Pos)                  /*!< SCU_PARITY PETE: PETEU1 Mask            */\r
+#define SCU_PARITY_PETE_PETEMC_Pos            12                                                      /*!< SCU_PARITY PETE: PETEMC Position        */\r
+#define SCU_PARITY_PETE_PETEMC_Msk            (0x01UL << SCU_PARITY_PETE_PETEMC_Pos)                  /*!< SCU_PARITY PETE: PETEMC Mask            */\r
+#define SCU_PARITY_PETE_PETEPPRF_Pos          13                                                      /*!< SCU_PARITY PETE: PETEPPRF Position      */\r
+#define SCU_PARITY_PETE_PETEPPRF_Msk          (0x01UL << SCU_PARITY_PETE_PETEPPRF_Pos)                /*!< SCU_PARITY PETE: PETEPPRF Mask          */\r
+#define SCU_PARITY_PETE_PETEUSB_Pos           16                                                      /*!< SCU_PARITY PETE: PETEUSB Position       */\r
+#define SCU_PARITY_PETE_PETEUSB_Msk           (0x01UL << SCU_PARITY_PETE_PETEUSB_Pos)                 /*!< SCU_PARITY PETE: PETEUSB Mask           */\r
+#define SCU_PARITY_PETE_PETEETH0TX_Pos        17                                                      /*!< SCU_PARITY PETE: PETEETH0TX Position    */\r
+#define SCU_PARITY_PETE_PETEETH0TX_Msk        (0x01UL << SCU_PARITY_PETE_PETEETH0TX_Pos)              /*!< SCU_PARITY PETE: PETEETH0TX Mask        */\r
+#define SCU_PARITY_PETE_PETEETH0RX_Pos        18                                                      /*!< SCU_PARITY PETE: PETEETH0RX Position    */\r
+#define SCU_PARITY_PETE_PETEETH0RX_Msk        (0x01UL << SCU_PARITY_PETE_PETEETH0RX_Pos)              /*!< SCU_PARITY PETE: PETEETH0RX Mask        */\r
+\r
+/* -----------------------------  SCU_PARITY_PERSTEN  ----------------------------- */\r
+#define SCU_PARITY_PERSTEN_RSEN_Pos           0                                                       /*!< SCU_PARITY PERSTEN: RSEN Position       */\r
+#define SCU_PARITY_PERSTEN_RSEN_Msk           (0x01UL << SCU_PARITY_PERSTEN_RSEN_Pos)                 /*!< SCU_PARITY PERSTEN: RSEN Mask           */\r
+\r
+/* ------------------------------  SCU_PARITY_PEFLAG  ----------------------------- */\r
+#define SCU_PARITY_PEFLAG_PEFPS_Pos           0                                                       /*!< SCU_PARITY PEFLAG: PEFPS Position       */\r
+#define SCU_PARITY_PEFLAG_PEFPS_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFPS_Pos)                 /*!< SCU_PARITY PEFLAG: PEFPS Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFDS1_Pos          1                                                       /*!< SCU_PARITY PEFLAG: PEFDS1 Position      */\r
+#define SCU_PARITY_PEFLAG_PEFDS1_Msk          (0x01UL << SCU_PARITY_PEFLAG_PEFDS1_Pos)                /*!< SCU_PARITY PEFLAG: PEFDS1 Mask          */\r
+#define SCU_PARITY_PEFLAG_PEFDS2_Pos          2                                                       /*!< SCU_PARITY PEFLAG: PEFDS2 Position      */\r
+#define SCU_PARITY_PEFLAG_PEFDS2_Msk          (0x01UL << SCU_PARITY_PEFLAG_PEFDS2_Pos)                /*!< SCU_PARITY PEFLAG: PEFDS2 Mask          */\r
+#define SCU_PARITY_PEFLAG_PEFU0_Pos           8                                                       /*!< SCU_PARITY PEFLAG: PEFU0 Position       */\r
+#define SCU_PARITY_PEFLAG_PEFU0_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFU0_Pos)                 /*!< SCU_PARITY PEFLAG: PEFU0 Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFU1_Pos           9                                                       /*!< SCU_PARITY PEFLAG: PEFU1 Position       */\r
+#define SCU_PARITY_PEFLAG_PEFU1_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFU1_Pos)                 /*!< SCU_PARITY PEFLAG: PEFU1 Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFMC_Pos           12                                                      /*!< SCU_PARITY PEFLAG: PEFMC Position       */\r
+#define SCU_PARITY_PEFLAG_PEFMC_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFMC_Pos)                 /*!< SCU_PARITY PEFLAG: PEFMC Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFPPRF_Pos         13                                                      /*!< SCU_PARITY PEFLAG: PEFPPRF Position     */\r
+#define SCU_PARITY_PEFLAG_PEFPPRF_Msk         (0x01UL << SCU_PARITY_PEFLAG_PEFPPRF_Pos)               /*!< SCU_PARITY PEFLAG: PEFPPRF Mask         */\r
+#define SCU_PARITY_PEFLAG_PEUSB_Pos           16                                                      /*!< SCU_PARITY PEFLAG: PEUSB Position       */\r
+#define SCU_PARITY_PEFLAG_PEUSB_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEUSB_Pos)                 /*!< SCU_PARITY PEFLAG: PEUSB Mask           */\r
+#define SCU_PARITY_PEFLAG_PEETH0TX_Pos        17                                                      /*!< SCU_PARITY PEFLAG: PEETH0TX Position    */\r
+#define SCU_PARITY_PEFLAG_PEETH0TX_Msk        (0x01UL << SCU_PARITY_PEFLAG_PEETH0TX_Pos)              /*!< SCU_PARITY PEFLAG: PEETH0TX Mask        */\r
+#define SCU_PARITY_PEFLAG_PEETH0RX_Pos        18                                                      /*!< SCU_PARITY PEFLAG: PEETH0RX Position    */\r
+#define SCU_PARITY_PEFLAG_PEETH0RX_Msk        (0x01UL << SCU_PARITY_PEFLAG_PEETH0RX_Pos)              /*!< SCU_PARITY PEFLAG: PEETH0RX Mask        */\r
+\r
+/* ------------------------------  SCU_PARITY_PMTPR  ------------------------------ */\r
+#define SCU_PARITY_PMTPR_PWR_Pos              0                                                       /*!< SCU_PARITY PMTPR: PWR Position          */\r
+#define SCU_PARITY_PMTPR_PWR_Msk              (0x000000ffUL << SCU_PARITY_PMTPR_PWR_Pos)              /*!< SCU_PARITY PMTPR: PWR Mask              */\r
+#define SCU_PARITY_PMTPR_PRD_Pos              8                                                       /*!< SCU_PARITY PMTPR: PRD Position          */\r
+#define SCU_PARITY_PMTPR_PRD_Msk              (0x000000ffUL << SCU_PARITY_PMTPR_PRD_Pos)              /*!< SCU_PARITY PMTPR: PRD Mask              */\r
+\r
+/* ------------------------------  SCU_PARITY_PMTSR  ------------------------------ */\r
+#define SCU_PARITY_PMTSR_MTENPS_Pos           0                                                       /*!< SCU_PARITY PMTSR: MTENPS Position       */\r
+#define SCU_PARITY_PMTSR_MTENPS_Msk           (0x01UL << SCU_PARITY_PMTSR_MTENPS_Pos)                 /*!< SCU_PARITY PMTSR: MTENPS Mask           */\r
+#define SCU_PARITY_PMTSR_MTENDS1_Pos          1                                                       /*!< SCU_PARITY PMTSR: MTENDS1 Position      */\r
+#define SCU_PARITY_PMTSR_MTENDS1_Msk          (0x01UL << SCU_PARITY_PMTSR_MTENDS1_Pos)                /*!< SCU_PARITY PMTSR: MTENDS1 Mask          */\r
+#define SCU_PARITY_PMTSR_MTENDS2_Pos          2                                                       /*!< SCU_PARITY PMTSR: MTENDS2 Position      */\r
+#define SCU_PARITY_PMTSR_MTENDS2_Msk          (0x01UL << SCU_PARITY_PMTSR_MTENDS2_Pos)                /*!< SCU_PARITY PMTSR: MTENDS2 Mask          */\r
+#define SCU_PARITY_PMTSR_MTEU0_Pos            8                                                       /*!< SCU_PARITY PMTSR: MTEU0 Position        */\r
+#define SCU_PARITY_PMTSR_MTEU0_Msk            (0x01UL << SCU_PARITY_PMTSR_MTEU0_Pos)                  /*!< SCU_PARITY PMTSR: MTEU0 Mask            */\r
+#define SCU_PARITY_PMTSR_MTEU1_Pos            9                                                       /*!< SCU_PARITY PMTSR: MTEU1 Position        */\r
+#define SCU_PARITY_PMTSR_MTEU1_Msk            (0x01UL << SCU_PARITY_PMTSR_MTEU1_Pos)                  /*!< SCU_PARITY PMTSR: MTEU1 Mask            */\r
+#define SCU_PARITY_PMTSR_MTEMC_Pos            12                                                      /*!< SCU_PARITY PMTSR: MTEMC Position        */\r
+#define SCU_PARITY_PMTSR_MTEMC_Msk            (0x01UL << SCU_PARITY_PMTSR_MTEMC_Pos)                  /*!< SCU_PARITY PMTSR: MTEMC Mask            */\r
+#define SCU_PARITY_PMTSR_MTEPPRF_Pos          13                                                      /*!< SCU_PARITY PMTSR: MTEPPRF Position      */\r
+#define SCU_PARITY_PMTSR_MTEPPRF_Msk          (0x01UL << SCU_PARITY_PMTSR_MTEPPRF_Pos)                /*!< SCU_PARITY PMTSR: MTEPPRF Mask          */\r
+#define SCU_PARITY_PMTSR_MTUSB_Pos            16                                                      /*!< SCU_PARITY PMTSR: MTUSB Position        */\r
+#define SCU_PARITY_PMTSR_MTUSB_Msk            (0x01UL << SCU_PARITY_PMTSR_MTUSB_Pos)                  /*!< SCU_PARITY PMTSR: MTUSB Mask            */\r
+#define SCU_PARITY_PMTSR_MTETH0TX_Pos         17                                                      /*!< SCU_PARITY PMTSR: MTETH0TX Position     */\r
+#define SCU_PARITY_PMTSR_MTETH0TX_Msk         (0x01UL << SCU_PARITY_PMTSR_MTETH0TX_Pos)               /*!< SCU_PARITY PMTSR: MTETH0TX Mask         */\r
+#define SCU_PARITY_PMTSR_MTETH0RX_Pos         18                                                      /*!< SCU_PARITY PMTSR: MTETH0RX Position     */\r
+#define SCU_PARITY_PMTSR_MTETH0RX_Msk         (0x01UL << SCU_PARITY_PMTSR_MTETH0RX_Pos)               /*!< SCU_PARITY PMTSR: MTETH0RX Mask         */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_TRAP' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPSTAT  ----------------------------- */\r
+#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos        0                                                       /*!< SCU_TRAP TRAPSTAT: SOSCWDGT Position    */\r
+#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk        (0x01UL << SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos)              /*!< SCU_TRAP TRAPSTAT: SOSCWDGT Mask        */\r
+#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos        2                                                       /*!< SCU_TRAP TRAPSTAT: SVCOLCKT Position    */\r
+#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk        (0x01UL << SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos)              /*!< SCU_TRAP TRAPSTAT: SVCOLCKT Mask        */\r
+#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos        3                                                       /*!< SCU_TRAP TRAPSTAT: UVCOLCKT Position    */\r
+#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk        (0x01UL << SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos)              /*!< SCU_TRAP TRAPSTAT: UVCOLCKT Mask        */\r
+#define SCU_TRAP_TRAPSTAT_PET_Pos             4                                                       /*!< SCU_TRAP TRAPSTAT: PET Position         */\r
+#define SCU_TRAP_TRAPSTAT_PET_Msk             (0x01UL << SCU_TRAP_TRAPSTAT_PET_Pos)                   /*!< SCU_TRAP TRAPSTAT: PET Mask             */\r
+#define SCU_TRAP_TRAPSTAT_BRWNT_Pos           5                                                       /*!< SCU_TRAP TRAPSTAT: BRWNT Position       */\r
+#define SCU_TRAP_TRAPSTAT_BRWNT_Msk           (0x01UL << SCU_TRAP_TRAPSTAT_BRWNT_Pos)                 /*!< SCU_TRAP TRAPSTAT: BRWNT Mask           */\r
+#define SCU_TRAP_TRAPSTAT_ULPWDGT_Pos         6                                                       /*!< SCU_TRAP TRAPSTAT: ULPWDGT Position     */\r
+#define SCU_TRAP_TRAPSTAT_ULPWDGT_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_ULPWDGT_Pos)               /*!< SCU_TRAP TRAPSTAT: ULPWDGT Mask         */\r
+#define SCU_TRAP_TRAPSTAT_BWERR0T_Pos         7                                                       /*!< SCU_TRAP TRAPSTAT: BWERR0T Position     */\r
+#define SCU_TRAP_TRAPSTAT_BWERR0T_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_BWERR0T_Pos)               /*!< SCU_TRAP TRAPSTAT: BWERR0T Mask         */\r
+#define SCU_TRAP_TRAPSTAT_BWERR1T_Pos         8                                                       /*!< SCU_TRAP TRAPSTAT: BWERR1T Position     */\r
+#define SCU_TRAP_TRAPSTAT_BWERR1T_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_BWERR1T_Pos)               /*!< SCU_TRAP TRAPSTAT: BWERR1T Mask         */\r
+#define SCU_TRAP_TRAPSTAT_TEMPHIT_Pos         12                                                      /*!< SCU_TRAP TRAPSTAT: TEMPHIT Position     */\r
+#define SCU_TRAP_TRAPSTAT_TEMPHIT_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_TEMPHIT_Pos)               /*!< SCU_TRAP TRAPSTAT: TEMPHIT Mask         */\r
+#define SCU_TRAP_TRAPSTAT_TEMPLOT_Pos         13                                                      /*!< SCU_TRAP TRAPSTAT: TEMPLOT Position     */\r
+#define SCU_TRAP_TRAPSTAT_TEMPLOT_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_TEMPLOT_Pos)               /*!< SCU_TRAP TRAPSTAT: TEMPLOT Mask         */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPRAW  ------------------------------ */\r
+#define SCU_TRAP_TRAPRAW_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPRAW: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPRAW_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPRAW_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPRAW: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPRAW_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPRAW: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPRAW_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPRAW_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPRAW: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPRAW_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPRAW: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPRAW_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPRAW_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPRAW: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPRAW_PET_Pos              4                                                       /*!< SCU_TRAP TRAPRAW: PET Position          */\r
+#define SCU_TRAP_TRAPRAW_PET_Msk              (0x01UL << SCU_TRAP_TRAPRAW_PET_Pos)                    /*!< SCU_TRAP TRAPRAW: PET Mask              */\r
+#define SCU_TRAP_TRAPRAW_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPRAW: BRWNT Position        */\r
+#define SCU_TRAP_TRAPRAW_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPRAW_BRWNT_Pos)                  /*!< SCU_TRAP TRAPRAW: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPRAW_ULPWDGT_Pos          6                                                       /*!< SCU_TRAP TRAPRAW: ULPWDGT Position      */\r
+#define SCU_TRAP_TRAPRAW_ULPWDGT_Msk          (0x01UL << SCU_TRAP_TRAPRAW_ULPWDGT_Pos)                /*!< SCU_TRAP TRAPRAW: ULPWDGT Mask          */\r
+#define SCU_TRAP_TRAPRAW_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPRAW: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPRAW_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPRAW_BWERR0T_Pos)                /*!< SCU_TRAP TRAPRAW: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPRAW_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPRAW: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPRAW_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPRAW_BWERR1T_Pos)                /*!< SCU_TRAP TRAPRAW: BWERR1T Mask          */\r
+#define SCU_TRAP_TRAPRAW_TEMPHIT_Pos          12                                                      /*!< SCU_TRAP TRAPRAW: TEMPHIT Position      */\r
+#define SCU_TRAP_TRAPRAW_TEMPHIT_Msk          (0x01UL << SCU_TRAP_TRAPRAW_TEMPHIT_Pos)                /*!< SCU_TRAP TRAPRAW: TEMPHIT Mask          */\r
+#define SCU_TRAP_TRAPRAW_TEMPLOT_Pos          13                                                      /*!< SCU_TRAP TRAPRAW: TEMPLOT Position      */\r
+#define SCU_TRAP_TRAPRAW_TEMPLOT_Msk          (0x01UL << SCU_TRAP_TRAPRAW_TEMPLOT_Pos)                /*!< SCU_TRAP TRAPRAW: TEMPLOT Mask          */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPDIS  ------------------------------ */\r
+#define SCU_TRAP_TRAPDIS_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPDIS: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPDIS_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPDIS_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPDIS: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPDIS_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPDIS: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPDIS_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPDIS_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPDIS: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPDIS_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPDIS: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPDIS_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPDIS_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPDIS: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPDIS_PET_Pos              4                                                       /*!< SCU_TRAP TRAPDIS: PET Position          */\r
+#define SCU_TRAP_TRAPDIS_PET_Msk              (0x01UL << SCU_TRAP_TRAPDIS_PET_Pos)                    /*!< SCU_TRAP TRAPDIS: PET Mask              */\r
+#define SCU_TRAP_TRAPDIS_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPDIS: BRWNT Position        */\r
+#define SCU_TRAP_TRAPDIS_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPDIS_BRWNT_Pos)                  /*!< SCU_TRAP TRAPDIS: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPDIS_ULPWDGT_Pos          6                                                       /*!< SCU_TRAP TRAPDIS: ULPWDGT Position      */\r
+#define SCU_TRAP_TRAPDIS_ULPWDGT_Msk          (0x01UL << SCU_TRAP_TRAPDIS_ULPWDGT_Pos)                /*!< SCU_TRAP TRAPDIS: ULPWDGT Mask          */\r
+#define SCU_TRAP_TRAPDIS_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPDIS: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPDIS_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPDIS_BWERR0T_Pos)                /*!< SCU_TRAP TRAPDIS: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPDIS_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPDIS: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPDIS_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPDIS_BWERR1T_Pos)                /*!< SCU_TRAP TRAPDIS: BWERR1T Mask          */\r
+#define SCU_TRAP_TRAPDIS_TEMPHIT_Pos          12                                                      /*!< SCU_TRAP TRAPDIS: TEMPHIT Position      */\r
+#define SCU_TRAP_TRAPDIS_TEMPHIT_Msk          (0x01UL << SCU_TRAP_TRAPDIS_TEMPHIT_Pos)                /*!< SCU_TRAP TRAPDIS: TEMPHIT Mask          */\r
+#define SCU_TRAP_TRAPDIS_TEMPLOT_Pos          13                                                      /*!< SCU_TRAP TRAPDIS: TEMPLOT Position      */\r
+#define SCU_TRAP_TRAPDIS_TEMPLOT_Msk          (0x01UL << SCU_TRAP_TRAPDIS_TEMPLOT_Pos)                /*!< SCU_TRAP TRAPDIS: TEMPLOT Mask          */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPCLR  ------------------------------ */\r
+#define SCU_TRAP_TRAPCLR_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPCLR: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPCLR_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPCLR_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPCLR: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPCLR_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPCLR: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPCLR_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPCLR_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPCLR: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPCLR_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPCLR: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPCLR_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPCLR_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPCLR: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPCLR_PET_Pos              4                                                       /*!< SCU_TRAP TRAPCLR: PET Position          */\r
+#define SCU_TRAP_TRAPCLR_PET_Msk              (0x01UL << SCU_TRAP_TRAPCLR_PET_Pos)                    /*!< SCU_TRAP TRAPCLR: PET Mask              */\r
+#define SCU_TRAP_TRAPCLR_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPCLR: BRWNT Position        */\r
+#define SCU_TRAP_TRAPCLR_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPCLR_BRWNT_Pos)                  /*!< SCU_TRAP TRAPCLR: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPCLR_ULPWDGT_Pos          6                                                       /*!< SCU_TRAP TRAPCLR: ULPWDGT Position      */\r
+#define SCU_TRAP_TRAPCLR_ULPWDGT_Msk          (0x01UL << SCU_TRAP_TRAPCLR_ULPWDGT_Pos)                /*!< SCU_TRAP TRAPCLR: ULPWDGT Mask          */\r
+#define SCU_TRAP_TRAPCLR_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPCLR: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPCLR_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPCLR_BWERR0T_Pos)                /*!< SCU_TRAP TRAPCLR: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPCLR_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPCLR: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPCLR_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPCLR_BWERR1T_Pos)                /*!< SCU_TRAP TRAPCLR: BWERR1T Mask          */\r
+#define SCU_TRAP_TRAPCLR_TEMPHIT_Pos          12                                                      /*!< SCU_TRAP TRAPCLR: TEMPHIT Position      */\r
+#define SCU_TRAP_TRAPCLR_TEMPHIT_Msk          (0x01UL << SCU_TRAP_TRAPCLR_TEMPHIT_Pos)                /*!< SCU_TRAP TRAPCLR: TEMPHIT Mask          */\r
+#define SCU_TRAP_TRAPCLR_TEMPLOT_Pos          13                                                      /*!< SCU_TRAP TRAPCLR: TEMPLOT Position      */\r
+#define SCU_TRAP_TRAPCLR_TEMPLOT_Msk          (0x01UL << SCU_TRAP_TRAPCLR_TEMPLOT_Pos)                /*!< SCU_TRAP TRAPCLR: TEMPLOT Mask          */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPSET  ------------------------------ */\r
+#define SCU_TRAP_TRAPSET_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPSET: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPSET_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPSET_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPSET: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPSET_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPSET: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPSET_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPSET_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPSET: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPSET_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPSET: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPSET_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPSET_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPSET: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPSET_PET_Pos              4                                                       /*!< SCU_TRAP TRAPSET: PET Position          */\r
+#define SCU_TRAP_TRAPSET_PET_Msk              (0x01UL << SCU_TRAP_TRAPSET_PET_Pos)                    /*!< SCU_TRAP TRAPSET: PET Mask              */\r
+#define SCU_TRAP_TRAPSET_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPSET: BRWNT Position        */\r
+#define SCU_TRAP_TRAPSET_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPSET_BRWNT_Pos)                  /*!< SCU_TRAP TRAPSET: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPSET_ULPWDT_Pos           6                                                       /*!< SCU_TRAP TRAPSET: ULPWDT Position       */\r
+#define SCU_TRAP_TRAPSET_ULPWDT_Msk           (0x01UL << SCU_TRAP_TRAPSET_ULPWDT_Pos)                 /*!< SCU_TRAP TRAPSET: ULPWDT Mask           */\r
+#define SCU_TRAP_TRAPSET_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPSET: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPSET_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPSET_BWERR0T_Pos)                /*!< SCU_TRAP TRAPSET: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPSET_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPSET: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPSET_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPSET_BWERR1T_Pos)                /*!< SCU_TRAP TRAPSET: BWERR1T Mask          */\r
+#define SCU_TRAP_TRAPSET_TEMPHIT_Pos          12                                                      /*!< SCU_TRAP TRAPSET: TEMPHIT Position      */\r
+#define SCU_TRAP_TRAPSET_TEMPHIT_Msk          (0x01UL << SCU_TRAP_TRAPSET_TEMPHIT_Pos)                /*!< SCU_TRAP TRAPSET: TEMPHIT Mask          */\r
+#define SCU_TRAP_TRAPSET_TEMPLOT_Pos          13                                                      /*!< SCU_TRAP TRAPSET: TEMPLOT Position      */\r
+#define SCU_TRAP_TRAPSET_TEMPLOT_Msk          (0x01UL << SCU_TRAP_TRAPSET_TEMPLOT_Pos)                /*!< SCU_TRAP TRAPSET: TEMPLOT Mask          */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================     struct 'SCU_HIBERNATE' Position & Mask     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------  SCU_HIBERNATE_HDSTAT  ---------------------------- */\r
+#define SCU_HIBERNATE_HDSTAT_EPEV_Pos         0                                                       /*!< SCU_HIBERNATE HDSTAT: EPEV Position     */\r
+#define SCU_HIBERNATE_HDSTAT_EPEV_Msk         (0x01UL << SCU_HIBERNATE_HDSTAT_EPEV_Pos)               /*!< SCU_HIBERNATE HDSTAT: EPEV Mask         */\r
+#define SCU_HIBERNATE_HDSTAT_ENEV_Pos         1                                                       /*!< SCU_HIBERNATE HDSTAT: ENEV Position     */\r
+#define SCU_HIBERNATE_HDSTAT_ENEV_Msk         (0x01UL << SCU_HIBERNATE_HDSTAT_ENEV_Pos)               /*!< SCU_HIBERNATE HDSTAT: ENEV Mask         */\r
+#define SCU_HIBERNATE_HDSTAT_RTCEV_Pos        2                                                       /*!< SCU_HIBERNATE HDSTAT: RTCEV Position    */\r
+#define SCU_HIBERNATE_HDSTAT_RTCEV_Msk        (0x01UL << SCU_HIBERNATE_HDSTAT_RTCEV_Pos)              /*!< SCU_HIBERNATE HDSTAT: RTCEV Mask        */\r
+#define SCU_HIBERNATE_HDSTAT_ULPWDG_Pos       3                                                       /*!< SCU_HIBERNATE HDSTAT: ULPWDG Position   */\r
+#define SCU_HIBERNATE_HDSTAT_ULPWDG_Msk       (0x01UL << SCU_HIBERNATE_HDSTAT_ULPWDG_Pos)             /*!< SCU_HIBERNATE HDSTAT: ULPWDG Mask       */\r
+#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos      4                                                       /*!< SCU_HIBERNATE HDSTAT: HIBNOUT Position  */\r
+#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk      (0x01UL << SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos)            /*!< SCU_HIBERNATE HDSTAT: HIBNOUT Mask      */\r
+#define SCU_HIBERNATE_HDSTAT_VBATPEV_Pos      8                                                       /*!< SCU_HIBERNATE HDSTAT: VBATPEV Position  */\r
+#define SCU_HIBERNATE_HDSTAT_VBATPEV_Msk      (0x01UL << SCU_HIBERNATE_HDSTAT_VBATPEV_Pos)            /*!< SCU_HIBERNATE HDSTAT: VBATPEV Mask      */\r
+#define SCU_HIBERNATE_HDSTAT_VBATNEV_Pos      9                                                       /*!< SCU_HIBERNATE HDSTAT: VBATNEV Position  */\r
+#define SCU_HIBERNATE_HDSTAT_VBATNEV_Msk      (0x01UL << SCU_HIBERNATE_HDSTAT_VBATNEV_Pos)            /*!< SCU_HIBERNATE HDSTAT: VBATNEV Mask      */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos   10                                                      /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV Position */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Msk   (0x01UL << SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos)         /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV Mask   */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos   11                                                      /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV Position */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Msk   (0x01UL << SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos)         /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV Mask   */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Pos   12                                                      /*!< SCU_HIBERNATE HDSTAT: AHIBIO1PEV Position */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Msk   (0x01UL << SCU_HIBERNATE_HDSTAT_AHIBIO1PEV_Pos)         /*!< SCU_HIBERNATE HDSTAT: AHIBIO1PEV Mask   */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Pos   13                                                      /*!< SCU_HIBERNATE HDSTAT: AHIBIO1NEV Position */\r
+#define SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Msk   (0x01UL << SCU_HIBERNATE_HDSTAT_AHIBIO1NEV_Pos)         /*!< SCU_HIBERNATE HDSTAT: AHIBIO1NEV Mask   */\r
+\r
+/* -----------------------------  SCU_HIBERNATE_HDCLR  ---------------------------- */\r
+#define SCU_HIBERNATE_HDCLR_EPEV_Pos          0                                                       /*!< SCU_HIBERNATE HDCLR: EPEV Position      */\r
+#define SCU_HIBERNATE_HDCLR_EPEV_Msk          (0x01UL << SCU_HIBERNATE_HDCLR_EPEV_Pos)                /*!< SCU_HIBERNATE HDCLR: EPEV Mask          */\r
+#define SCU_HIBERNATE_HDCLR_ENEV_Pos          1                                                       /*!< SCU_HIBERNATE HDCLR: ENEV Position      */\r
+#define SCU_HIBERNATE_HDCLR_ENEV_Msk          (0x01UL << SCU_HIBERNATE_HDCLR_ENEV_Pos)                /*!< SCU_HIBERNATE HDCLR: ENEV Mask          */\r
+#define SCU_HIBERNATE_HDCLR_RTCEV_Pos         2                                                       /*!< SCU_HIBERNATE HDCLR: RTCEV Position     */\r
+#define SCU_HIBERNATE_HDCLR_RTCEV_Msk         (0x01UL << SCU_HIBERNATE_HDCLR_RTCEV_Pos)               /*!< SCU_HIBERNATE HDCLR: RTCEV Mask         */\r
+#define SCU_HIBERNATE_HDCLR_ULPWDG_Pos        3                                                       /*!< SCU_HIBERNATE HDCLR: ULPWDG Position    */\r
+#define SCU_HIBERNATE_HDCLR_ULPWDG_Msk        (0x01UL << SCU_HIBERNATE_HDCLR_ULPWDG_Pos)              /*!< SCU_HIBERNATE HDCLR: ULPWDG Mask        */\r
+#define SCU_HIBERNATE_HDCLR_VBATPEV_Pos       8                                                       /*!< SCU_HIBERNATE HDCLR: VBATPEV Position   */\r
+#define SCU_HIBERNATE_HDCLR_VBATPEV_Msk       (0x01UL << SCU_HIBERNATE_HDCLR_VBATPEV_Pos)             /*!< SCU_HIBERNATE HDCLR: VBATPEV Mask       */\r
+#define SCU_HIBERNATE_HDCLR_VBATNEV_Pos       9                                                       /*!< SCU_HIBERNATE HDCLR: VBATNEV Position   */\r
+#define SCU_HIBERNATE_HDCLR_VBATNEV_Msk       (0x01UL << SCU_HIBERNATE_HDCLR_VBATNEV_Pos)             /*!< SCU_HIBERNATE HDCLR: VBATNEV Mask       */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Pos    10                                                      /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV Position */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Msk    (0x01UL << SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Pos)          /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV Mask    */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Pos    11                                                      /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV Position */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Msk    (0x01UL << SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Pos)          /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV Mask    */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO1PEV_Pos    12                                                      /*!< SCU_HIBERNATE HDCLR: AHIBIO1PEV Position */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO1PEV_Msk    (0x01UL << SCU_HIBERNATE_HDCLR_AHIBIO1PEV_Pos)          /*!< SCU_HIBERNATE HDCLR: AHIBIO1PEV Mask    */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO1NEV_Pos    13                                                      /*!< SCU_HIBERNATE HDCLR: AHIBIO1NEV Position */\r
+#define SCU_HIBERNATE_HDCLR_AHIBIO1NEV_Msk    (0x01UL << SCU_HIBERNATE_HDCLR_AHIBIO1NEV_Pos)          /*!< SCU_HIBERNATE HDCLR: AHIBIO1NEV Mask    */\r
+\r
+/* -----------------------------  SCU_HIBERNATE_HDSET  ---------------------------- */\r
+#define SCU_HIBERNATE_HDSET_EPEV_Pos          0                                                       /*!< SCU_HIBERNATE HDSET: EPEV Position      */\r
+#define SCU_HIBERNATE_HDSET_EPEV_Msk          (0x01UL << SCU_HIBERNATE_HDSET_EPEV_Pos)                /*!< SCU_HIBERNATE HDSET: EPEV Mask          */\r
+#define SCU_HIBERNATE_HDSET_ENEV_Pos          1                                                       /*!< SCU_HIBERNATE HDSET: ENEV Position      */\r
+#define SCU_HIBERNATE_HDSET_ENEV_Msk          (0x01UL << SCU_HIBERNATE_HDSET_ENEV_Pos)                /*!< SCU_HIBERNATE HDSET: ENEV Mask          */\r
+#define SCU_HIBERNATE_HDSET_RTCEV_Pos         2                                                       /*!< SCU_HIBERNATE HDSET: RTCEV Position     */\r
+#define SCU_HIBERNATE_HDSET_RTCEV_Msk         (0x01UL << SCU_HIBERNATE_HDSET_RTCEV_Pos)               /*!< SCU_HIBERNATE HDSET: RTCEV Mask         */\r
+#define SCU_HIBERNATE_HDSET_ULPWDG_Pos        3                                                       /*!< SCU_HIBERNATE HDSET: ULPWDG Position    */\r
+#define SCU_HIBERNATE_HDSET_ULPWDG_Msk        (0x01UL << SCU_HIBERNATE_HDSET_ULPWDG_Pos)              /*!< SCU_HIBERNATE HDSET: ULPWDG Mask        */\r
+#define SCU_HIBERNATE_HDSET_VBATPEV_Pos       8                                                       /*!< SCU_HIBERNATE HDSET: VBATPEV Position   */\r
+#define SCU_HIBERNATE_HDSET_VBATPEV_Msk       (0x01UL << SCU_HIBERNATE_HDSET_VBATPEV_Pos)             /*!< SCU_HIBERNATE HDSET: VBATPEV Mask       */\r
+#define SCU_HIBERNATE_HDSET_VBATNEV_Pos       9                                                       /*!< SCU_HIBERNATE HDSET: VBATNEV Position   */\r
+#define SCU_HIBERNATE_HDSET_VBATNEV_Msk       (0x01UL << SCU_HIBERNATE_HDSET_VBATNEV_Pos)             /*!< SCU_HIBERNATE HDSET: VBATNEV Mask       */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Pos    10                                                      /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV Position */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Msk    (0x01UL << SCU_HIBERNATE_HDSET_AHIBIO0PEV_Pos)          /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV Mask    */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Pos    11                                                      /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV Position */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Msk    (0x01UL << SCU_HIBERNATE_HDSET_AHIBIO0NEV_Pos)          /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV Mask    */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO1PEV_Pos    12                                                      /*!< SCU_HIBERNATE HDSET: AHIBIO1PEV Position */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO1PEV_Msk    (0x01UL << SCU_HIBERNATE_HDSET_AHIBIO1PEV_Pos)          /*!< SCU_HIBERNATE HDSET: AHIBIO1PEV Mask    */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO1NEV_Pos    13                                                      /*!< SCU_HIBERNATE HDSET: AHIBIO1NEV Position */\r
+#define SCU_HIBERNATE_HDSET_AHIBIO1NEV_Msk    (0x01UL << SCU_HIBERNATE_HDSET_AHIBIO1NEV_Pos)          /*!< SCU_HIBERNATE HDSET: AHIBIO1NEV Mask    */\r
+\r
+/* -----------------------------  SCU_HIBERNATE_HDCR  ----------------------------- */\r
+#define SCU_HIBERNATE_HDCR_WKPEP_Pos          0                                                       /*!< SCU_HIBERNATE HDCR: WKPEP Position      */\r
+#define SCU_HIBERNATE_HDCR_WKPEP_Msk          (0x01UL << SCU_HIBERNATE_HDCR_WKPEP_Pos)                /*!< SCU_HIBERNATE HDCR: WKPEP Mask          */\r
+#define SCU_HIBERNATE_HDCR_WKPEN_Pos          1                                                       /*!< SCU_HIBERNATE HDCR: WKPEN Position      */\r
+#define SCU_HIBERNATE_HDCR_WKPEN_Msk          (0x01UL << SCU_HIBERNATE_HDCR_WKPEN_Pos)                /*!< SCU_HIBERNATE HDCR: WKPEN Mask          */\r
+#define SCU_HIBERNATE_HDCR_RTCE_Pos           2                                                       /*!< SCU_HIBERNATE HDCR: RTCE Position       */\r
+#define SCU_HIBERNATE_HDCR_RTCE_Msk           (0x01UL << SCU_HIBERNATE_HDCR_RTCE_Pos)                 /*!< SCU_HIBERNATE HDCR: RTCE Mask           */\r
+#define SCU_HIBERNATE_HDCR_ULPWDGEN_Pos       3                                                       /*!< SCU_HIBERNATE HDCR: ULPWDGEN Position   */\r
+#define SCU_HIBERNATE_HDCR_ULPWDGEN_Msk       (0x01UL << SCU_HIBERNATE_HDCR_ULPWDGEN_Pos)             /*!< SCU_HIBERNATE HDCR: ULPWDGEN Mask       */\r
+#define SCU_HIBERNATE_HDCR_HIB_Pos            4                                                       /*!< SCU_HIBERNATE HDCR: HIB Position        */\r
+#define SCU_HIBERNATE_HDCR_HIB_Msk            (0x01UL << SCU_HIBERNATE_HDCR_HIB_Pos)                  /*!< SCU_HIBERNATE HDCR: HIB Mask            */\r
+#define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Pos    5                                                       /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL Position */\r
+#define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk    (0x01UL << SCU_HIBERNATE_HDCR_XTALGPI1SEL_Pos)          /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL Mask    */\r
+#define SCU_HIBERNATE_HDCR_RCS_Pos            6                                                       /*!< SCU_HIBERNATE HDCR: RCS Position        */\r
+#define SCU_HIBERNATE_HDCR_RCS_Msk            (0x01UL << SCU_HIBERNATE_HDCR_RCS_Pos)                  /*!< SCU_HIBERNATE HDCR: RCS Mask            */\r
+#define SCU_HIBERNATE_HDCR_STDBYSEL_Pos       7                                                       /*!< SCU_HIBERNATE HDCR: STDBYSEL Position   */\r
+#define SCU_HIBERNATE_HDCR_STDBYSEL_Msk       (0x01UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos)             /*!< SCU_HIBERNATE HDCR: STDBYSEL Mask       */\r
+#define SCU_HIBERNATE_HDCR_WKUPSEL_Pos        8                                                       /*!< SCU_HIBERNATE HDCR: WKUPSEL Position    */\r
+#define SCU_HIBERNATE_HDCR_WKUPSEL_Msk        (0x01UL << SCU_HIBERNATE_HDCR_WKUPSEL_Pos)              /*!< SCU_HIBERNATE HDCR: WKUPSEL Mask        */\r
+#define SCU_HIBERNATE_HDCR_GPI0SEL_Pos        10                                                      /*!< SCU_HIBERNATE HDCR: GPI0SEL Position    */\r
+#define SCU_HIBERNATE_HDCR_GPI0SEL_Msk        (0x01UL << SCU_HIBERNATE_HDCR_GPI0SEL_Pos)              /*!< SCU_HIBERNATE HDCR: GPI0SEL Mask        */\r
+#define SCU_HIBERNATE_HDCR_GPI1SEL_Pos        11                                                      /*!< SCU_HIBERNATE HDCR: GPI1SEL Position    */\r
+#define SCU_HIBERNATE_HDCR_GPI1SEL_Msk        (0x01UL << SCU_HIBERNATE_HDCR_GPI1SEL_Pos)              /*!< SCU_HIBERNATE HDCR: GPI1SEL Mask        */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0POL_Pos      12                                                      /*!< SCU_HIBERNATE HDCR: HIBIO0POL Position  */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0POL_Msk      (0x01UL << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos)            /*!< SCU_HIBERNATE HDCR: HIBIO0POL Mask      */\r
+#define SCU_HIBERNATE_HDCR_HIBIO1POL_Pos      13                                                      /*!< SCU_HIBERNATE HDCR: HIBIO1POL Position  */\r
+#define SCU_HIBERNATE_HDCR_HIBIO1POL_Msk      (0x01UL << SCU_HIBERNATE_HDCR_HIBIO1POL_Pos)            /*!< SCU_HIBERNATE HDCR: HIBIO1POL Mask      */\r
+#define SCU_HIBERNATE_HDCR_ADIG0SEL_Pos       14                                                      /*!< SCU_HIBERNATE HDCR: ADIG0SEL Position   */\r
+#define SCU_HIBERNATE_HDCR_ADIG0SEL_Msk       (0x01UL << SCU_HIBERNATE_HDCR_ADIG0SEL_Pos)             /*!< SCU_HIBERNATE HDCR: ADIG0SEL Mask       */\r
+#define SCU_HIBERNATE_HDCR_ADIG1SEL_Pos       15                                                      /*!< SCU_HIBERNATE HDCR: ADIG1SEL Position   */\r
+#define SCU_HIBERNATE_HDCR_ADIG1SEL_Msk       (0x01UL << SCU_HIBERNATE_HDCR_ADIG1SEL_Pos)             /*!< SCU_HIBERNATE HDCR: ADIG1SEL Mask       */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos      16                                                      /*!< SCU_HIBERNATE HDCR: HIBIO0SEL Position  */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk      (0x0fUL << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos)            /*!< SCU_HIBERNATE HDCR: HIBIO0SEL Mask      */\r
+#define SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos      20                                                      /*!< SCU_HIBERNATE HDCR: HIBIO1SEL Position  */\r
+#define SCU_HIBERNATE_HDCR_HIBIO1SEL_Msk      (0x0fUL << SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos)            /*!< SCU_HIBERNATE HDCR: HIBIO1SEL Mask      */\r
+#define SCU_HIBERNATE_HDCR_VBATLO_Pos         24                                                      /*!< SCU_HIBERNATE HDCR: VBATLO Position     */\r
+#define SCU_HIBERNATE_HDCR_VBATLO_Msk         (0x01UL << SCU_HIBERNATE_HDCR_VBATLO_Pos)               /*!< SCU_HIBERNATE HDCR: VBATLO Mask         */\r
+#define SCU_HIBERNATE_HDCR_VBATHI_Pos         25                                                      /*!< SCU_HIBERNATE HDCR: VBATHI Position     */\r
+#define SCU_HIBERNATE_HDCR_VBATHI_Msk         (0x01UL << SCU_HIBERNATE_HDCR_VBATHI_Pos)               /*!< SCU_HIBERNATE HDCR: VBATHI Mask         */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos      26                                                      /*!< SCU_HIBERNATE HDCR: AHIBIO0LO Position  */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO0LO_Msk      (0x01UL << SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos)            /*!< SCU_HIBERNATE HDCR: AHIBIO0LO Mask      */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos      27                                                      /*!< SCU_HIBERNATE HDCR: AHIBIO0HI Position  */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO0HI_Msk      (0x01UL << SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos)            /*!< SCU_HIBERNATE HDCR: AHIBIO0HI Mask      */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO1LO_Pos      28                                                      /*!< SCU_HIBERNATE HDCR: AHIBIO1LO Position  */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO1LO_Msk      (0x01UL << SCU_HIBERNATE_HDCR_AHIBIO1LO_Pos)            /*!< SCU_HIBERNATE HDCR: AHIBIO1LO Mask      */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO1HI_Pos      29                                                      /*!< SCU_HIBERNATE HDCR: AHIBIO1HI Position  */\r
+#define SCU_HIBERNATE_HDCR_AHIBIO1HI_Msk      (0x01UL << SCU_HIBERNATE_HDCR_AHIBIO1HI_Pos)            /*!< SCU_HIBERNATE HDCR: AHIBIO1HI Mask      */\r
+\r
+/* ---------------------------  SCU_HIBERNATE_OSCSICTRL  -------------------------- */\r
+#define SCU_HIBERNATE_OSCSICTRL_PWD_Pos       0                                                       /*!< SCU_HIBERNATE OSCSICTRL: PWD Position   */\r
+#define SCU_HIBERNATE_OSCSICTRL_PWD_Msk       (0x01UL << SCU_HIBERNATE_OSCSICTRL_PWD_Pos)             /*!< SCU_HIBERNATE OSCSICTRL: PWD Mask       */\r
+\r
+/* ---------------------------  SCU_HIBERNATE_OSCULSTAT  -------------------------- */\r
+#define SCU_HIBERNATE_OSCULSTAT_X1D_Pos       0                                                       /*!< SCU_HIBERNATE OSCULSTAT: X1D Position   */\r
+#define SCU_HIBERNATE_OSCULSTAT_X1D_Msk       (0x01UL << SCU_HIBERNATE_OSCULSTAT_X1D_Pos)             /*!< SCU_HIBERNATE OSCULSTAT: X1D Mask       */\r
+\r
+/* ---------------------------  SCU_HIBERNATE_OSCULCTRL  -------------------------- */\r
+#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos     0                                                       /*!< SCU_HIBERNATE OSCULCTRL: X1DEN Position */\r
+#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk     (0x01UL << SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos)           /*!< SCU_HIBERNATE OSCULCTRL: X1DEN Mask     */\r
+#define SCU_HIBERNATE_OSCULCTRL_MODE_Pos      4                                                       /*!< SCU_HIBERNATE OSCULCTRL: MODE Position  */\r
+#define SCU_HIBERNATE_OSCULCTRL_MODE_Msk      (0x03UL << SCU_HIBERNATE_OSCULCTRL_MODE_Pos)            /*!< SCU_HIBERNATE OSCULCTRL: MODE Mask      */\r
+\r
+/* ---------------------------  SCU_HIBERNATE_LPACCONF  --------------------------- */\r
+#define SCU_HIBERNATE_LPACCONF_CMPEN_Pos      0                                                       /*!< SCU_HIBERNATE LPACCONF: CMPEN Position  */\r
+#define SCU_HIBERNATE_LPACCONF_CMPEN_Msk      (0x07UL << SCU_HIBERNATE_LPACCONF_CMPEN_Pos)            /*!< SCU_HIBERNATE LPACCONF: CMPEN Mask      */\r
+#define SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos    4                                                       /*!< SCU_HIBERNATE LPACCONF: TRIGSEL Position */\r
+#define SCU_HIBERNATE_LPACCONF_TRIGSEL_Msk    (0x07UL << SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos)          /*!< SCU_HIBERNATE LPACCONF: TRIGSEL Mask    */\r
+#define SCU_HIBERNATE_LPACCONF_CONVDEL_Pos    12                                                      /*!< SCU_HIBERNATE LPACCONF: CONVDEL Position */\r
+#define SCU_HIBERNATE_LPACCONF_CONVDEL_Msk    (0x01UL << SCU_HIBERNATE_LPACCONF_CONVDEL_Pos)          /*!< SCU_HIBERNATE LPACCONF: CONVDEL Mask    */\r
+#define SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos  16                                                      /*!< SCU_HIBERNATE LPACCONF: INTERVCNT Position */\r
+#define SCU_HIBERNATE_LPACCONF_INTERVCNT_Msk  (0x00000fffUL << SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos)  /*!< SCU_HIBERNATE LPACCONF: INTERVCNT Mask  */\r
+#define SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos  28                                                      /*!< SCU_HIBERNATE LPACCONF: SETTLECNT Position */\r
+#define SCU_HIBERNATE_LPACCONF_SETTLECNT_Msk  (0x0fUL << SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos)        /*!< SCU_HIBERNATE LPACCONF: SETTLECNT Mask  */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_LPACTH0  --------------------------- */\r
+#define SCU_HIBERNATE_LPACTH0_VBATLO_Pos      0                                                       /*!< SCU_HIBERNATE LPACTH0: VBATLO Position  */\r
+#define SCU_HIBERNATE_LPACTH0_VBATLO_Msk      (0x3fUL << SCU_HIBERNATE_LPACTH0_VBATLO_Pos)            /*!< SCU_HIBERNATE LPACTH0: VBATLO Mask      */\r
+#define SCU_HIBERNATE_LPACTH0_VBATHI_Pos      8                                                       /*!< SCU_HIBERNATE LPACTH0: VBATHI Position  */\r
+#define SCU_HIBERNATE_LPACTH0_VBATHI_Msk      (0x3fUL << SCU_HIBERNATE_LPACTH0_VBATHI_Pos)            /*!< SCU_HIBERNATE LPACTH0: VBATHI Mask      */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_LPACTH1  --------------------------- */\r
+#define SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Pos   0                                                       /*!< SCU_HIBERNATE LPACTH1: AHIBIO0LO Position */\r
+#define SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Msk   (0x3fUL << SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Pos)         /*!< SCU_HIBERNATE LPACTH1: AHIBIO0LO Mask   */\r
+#define SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Pos   8                                                       /*!< SCU_HIBERNATE LPACTH1: AHIBIO0HI Position */\r
+#define SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Msk   (0x3fUL << SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Pos)         /*!< SCU_HIBERNATE LPACTH1: AHIBIO0HI Mask   */\r
+#define SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Pos   16                                                      /*!< SCU_HIBERNATE LPACTH1: AHIBIO1LO Position */\r
+#define SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Msk   (0x3fUL << SCU_HIBERNATE_LPACTH1_AHIBIO1LO_Pos)         /*!< SCU_HIBERNATE LPACTH1: AHIBIO1LO Mask   */\r
+#define SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Pos   24                                                      /*!< SCU_HIBERNATE LPACTH1: AHIBIO1HI Position */\r
+#define SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Msk   (0x3fUL << SCU_HIBERNATE_LPACTH1_AHIBIO1HI_Pos)         /*!< SCU_HIBERNATE LPACTH1: AHIBIO1HI Mask   */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_LPACST  ---------------------------- */\r
+#define SCU_HIBERNATE_LPACST_VBATSCMP_Pos     0                                                       /*!< SCU_HIBERNATE LPACST: VBATSCMP Position */\r
+#define SCU_HIBERNATE_LPACST_VBATSCMP_Msk     (0x01UL << SCU_HIBERNATE_LPACST_VBATSCMP_Pos)           /*!< SCU_HIBERNATE LPACST: VBATSCMP Mask     */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Pos  1                                                       /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP Position */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Msk  (0x01UL << SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Pos)        /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP Mask  */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Pos  2                                                       /*!< SCU_HIBERNATE LPACST: AHIBIO1SCMP Position */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Msk  (0x01UL << SCU_HIBERNATE_LPACST_AHIBIO1SCMP_Pos)        /*!< SCU_HIBERNATE LPACST: AHIBIO1SCMP Mask  */\r
+#define SCU_HIBERNATE_LPACST_VBATVAL_Pos      16                                                      /*!< SCU_HIBERNATE LPACST: VBATVAL Position  */\r
+#define SCU_HIBERNATE_LPACST_VBATVAL_Msk      (0x01UL << SCU_HIBERNATE_LPACST_VBATVAL_Pos)            /*!< SCU_HIBERNATE LPACST: VBATVAL Mask      */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Pos   17                                                      /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL Position */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Msk   (0x01UL << SCU_HIBERNATE_LPACST_AHIBIO0VAL_Pos)         /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL Mask   */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO1VAL_Pos   18                                                      /*!< SCU_HIBERNATE LPACST: AHIBIO1VAL Position */\r
+#define SCU_HIBERNATE_LPACST_AHIBIO1VAL_Msk   (0x01UL << SCU_HIBERNATE_LPACST_AHIBIO1VAL_Pos)         /*!< SCU_HIBERNATE LPACST: AHIBIO1VAL Mask   */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_LPACCLR  --------------------------- */\r
+#define SCU_HIBERNATE_LPACCLR_VBATSCMP_Pos    0                                                       /*!< SCU_HIBERNATE LPACCLR: VBATSCMP Position */\r
+#define SCU_HIBERNATE_LPACCLR_VBATSCMP_Msk    (0x01UL << SCU_HIBERNATE_LPACCLR_VBATSCMP_Pos)          /*!< SCU_HIBERNATE LPACCLR: VBATSCMP Mask    */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Pos 1                                                       /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP Position */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Pos)       /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP Mask */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO1SCMP_Pos 2                                                       /*!< SCU_HIBERNATE LPACCLR: AHIBIO1SCMP Position */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO1SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACCLR_AHIBIO1SCMP_Pos)       /*!< SCU_HIBERNATE LPACCLR: AHIBIO1SCMP Mask */\r
+#define SCU_HIBERNATE_LPACCLR_VBATVAL_Pos     16                                                      /*!< SCU_HIBERNATE LPACCLR: VBATVAL Position */\r
+#define SCU_HIBERNATE_LPACCLR_VBATVAL_Msk     (0x01UL << SCU_HIBERNATE_LPACCLR_VBATVAL_Pos)           /*!< SCU_HIBERNATE LPACCLR: VBATVAL Mask     */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Pos  17                                                      /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL Position */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Msk  (0x01UL << SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Pos)        /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL Mask  */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO1VAL_Pos  18                                                      /*!< SCU_HIBERNATE LPACCLR: AHIBIO1VAL Position */\r
+#define SCU_HIBERNATE_LPACCLR_AHIBIO1VAL_Msk  (0x01UL << SCU_HIBERNATE_LPACCLR_AHIBIO1VAL_Pos)        /*!< SCU_HIBERNATE LPACCLR: AHIBIO1VAL Mask  */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_LPACSET  --------------------------- */\r
+#define SCU_HIBERNATE_LPACSET_VBATSCMP_Pos    0                                                       /*!< SCU_HIBERNATE LPACSET: VBATSCMP Position */\r
+#define SCU_HIBERNATE_LPACSET_VBATSCMP_Msk    (0x01UL << SCU_HIBERNATE_LPACSET_VBATSCMP_Pos)          /*!< SCU_HIBERNATE LPACSET: VBATSCMP Mask    */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Pos 1                                                       /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP Position */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Pos)       /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP Mask */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO1SCMP_Pos 2                                                       /*!< SCU_HIBERNATE LPACSET: AHIBIO1SCMP Position */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO1SCMP_Msk (0x01UL << SCU_HIBERNATE_LPACSET_AHIBIO1SCMP_Pos)       /*!< SCU_HIBERNATE LPACSET: AHIBIO1SCMP Mask */\r
+#define SCU_HIBERNATE_LPACSET_VBATVAL_Pos     16                                                      /*!< SCU_HIBERNATE LPACSET: VBATVAL Position */\r
+#define SCU_HIBERNATE_LPACSET_VBATVAL_Msk     (0x01UL << SCU_HIBERNATE_LPACSET_VBATVAL_Pos)           /*!< SCU_HIBERNATE LPACSET: VBATVAL Mask     */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Pos  17                                                      /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL Position */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Msk  (0x01UL << SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Pos)        /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL Mask  */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO1VAL_Pos  18                                                      /*!< SCU_HIBERNATE LPACSET: AHIBIO1VAL Position */\r
+#define SCU_HIBERNATE_LPACSET_AHIBIO1VAL_Msk  (0x01UL << SCU_HIBERNATE_LPACSET_AHIBIO1VAL_Pos)        /*!< SCU_HIBERNATE LPACSET: AHIBIO1VAL Mask  */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_HINTST  ---------------------------- */\r
+#define SCU_HIBERNATE_HINTST_HIBNINT_Pos      0                                                       /*!< SCU_HIBERNATE HINTST: HIBNINT Position  */\r
+#define SCU_HIBERNATE_HINTST_HIBNINT_Msk      (0x01UL << SCU_HIBERNATE_HINTST_HIBNINT_Pos)            /*!< SCU_HIBERNATE HINTST: HIBNINT Mask      */\r
+#define SCU_HIBERNATE_HINTST_FLASHOFF_Pos     2                                                       /*!< SCU_HIBERNATE HINTST: FLASHOFF Position */\r
+#define SCU_HIBERNATE_HINTST_FLASHOFF_Msk     (0x01UL << SCU_HIBERNATE_HINTST_FLASHOFF_Pos)           /*!< SCU_HIBERNATE HINTST: FLASHOFF Mask     */\r
+#define SCU_HIBERNATE_HINTST_FLASHPD_Pos      3                                                       /*!< SCU_HIBERNATE HINTST: FLASHPD Position  */\r
+#define SCU_HIBERNATE_HINTST_FLASHPD_Msk      (0x01UL << SCU_HIBERNATE_HINTST_FLASHPD_Pos)            /*!< SCU_HIBERNATE HINTST: FLASHPD Mask      */\r
+#define SCU_HIBERNATE_HINTST_POFFD_Pos        4                                                       /*!< SCU_HIBERNATE HINTST: POFFD Position    */\r
+#define SCU_HIBERNATE_HINTST_POFFD_Msk        (0x01UL << SCU_HIBERNATE_HINTST_POFFD_Pos)              /*!< SCU_HIBERNATE HINTST: POFFD Mask        */\r
+#define SCU_HIBERNATE_HINTST_PPODEL_Pos       16                                                      /*!< SCU_HIBERNATE HINTST: PPODEL Position   */\r
+#define SCU_HIBERNATE_HINTST_PPODEL_Msk       (0x03UL << SCU_HIBERNATE_HINTST_PPODEL_Pos)             /*!< SCU_HIBERNATE HINTST: PPODEL Mask       */\r
+#define SCU_HIBERNATE_HINTST_POFFH_Pos        20                                                      /*!< SCU_HIBERNATE HINTST: POFFH Position    */\r
+#define SCU_HIBERNATE_HINTST_POFFH_Msk        (0x01UL << SCU_HIBERNATE_HINTST_POFFH_Pos)              /*!< SCU_HIBERNATE HINTST: POFFH Mask        */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_HINTCLR  --------------------------- */\r
+#define SCU_HIBERNATE_HINTCLR_HIBNINT_Pos     0                                                       /*!< SCU_HIBERNATE HINTCLR: HIBNINT Position */\r
+#define SCU_HIBERNATE_HINTCLR_HIBNINT_Msk     (0x01UL << SCU_HIBERNATE_HINTCLR_HIBNINT_Pos)           /*!< SCU_HIBERNATE HINTCLR: HIBNINT Mask     */\r
+#define SCU_HIBERNATE_HINTCLR_FLASHOFF_Pos    2                                                       /*!< SCU_HIBERNATE HINTCLR: FLASHOFF Position */\r
+#define SCU_HIBERNATE_HINTCLR_FLASHOFF_Msk    (0x01UL << SCU_HIBERNATE_HINTCLR_FLASHOFF_Pos)          /*!< SCU_HIBERNATE HINTCLR: FLASHOFF Mask    */\r
+#define SCU_HIBERNATE_HINTCLR_FLASHPD_Pos     3                                                       /*!< SCU_HIBERNATE HINTCLR: FLASHPD Position */\r
+#define SCU_HIBERNATE_HINTCLR_FLASHPD_Msk     (0x01UL << SCU_HIBERNATE_HINTCLR_FLASHPD_Pos)           /*!< SCU_HIBERNATE HINTCLR: FLASHPD Mask     */\r
+#define SCU_HIBERNATE_HINTCLR_POFFD_Pos       4                                                       /*!< SCU_HIBERNATE HINTCLR: POFFD Position   */\r
+#define SCU_HIBERNATE_HINTCLR_POFFD_Msk       (0x01UL << SCU_HIBERNATE_HINTCLR_POFFD_Pos)             /*!< SCU_HIBERNATE HINTCLR: POFFD Mask       */\r
+#define SCU_HIBERNATE_HINTCLR_PPODEL_Pos      16                                                      /*!< SCU_HIBERNATE HINTCLR: PPODEL Position  */\r
+#define SCU_HIBERNATE_HINTCLR_PPODEL_Msk      (0x03UL << SCU_HIBERNATE_HINTCLR_PPODEL_Pos)            /*!< SCU_HIBERNATE HINTCLR: PPODEL Mask      */\r
+#define SCU_HIBERNATE_HINTCLR_POFFH_Pos       20                                                      /*!< SCU_HIBERNATE HINTCLR: POFFH Position   */\r
+#define SCU_HIBERNATE_HINTCLR_POFFH_Msk       (0x01UL << SCU_HIBERNATE_HINTCLR_POFFH_Pos)             /*!< SCU_HIBERNATE HINTCLR: POFFH Mask       */\r
+\r
+/* ----------------------------  SCU_HIBERNATE_HINTSET  --------------------------- */\r
+#define SCU_HIBERNATE_HINTSET_HIBNINT_Pos     0                                                       /*!< SCU_HIBERNATE HINTSET: HIBNINT Position */\r
+#define SCU_HIBERNATE_HINTSET_HIBNINT_Msk     (0x01UL << SCU_HIBERNATE_HINTSET_HIBNINT_Pos)           /*!< SCU_HIBERNATE HINTSET: HIBNINT Mask     */\r
+#define SCU_HIBERNATE_HINTSET_VCOREOFF_Pos    1                                                       /*!< SCU_HIBERNATE HINTSET: VCOREOFF Position */\r
+#define SCU_HIBERNATE_HINTSET_VCOREOFF_Msk    (0x01UL << SCU_HIBERNATE_HINTSET_VCOREOFF_Pos)          /*!< SCU_HIBERNATE HINTSET: VCOREOFF Mask    */\r
+#define SCU_HIBERNATE_HINTSET_FLASHOFF_Pos    2                                                       /*!< SCU_HIBERNATE HINTSET: FLASHOFF Position */\r
+#define SCU_HIBERNATE_HINTSET_FLASHOFF_Msk    (0x01UL << SCU_HIBERNATE_HINTSET_FLASHOFF_Pos)          /*!< SCU_HIBERNATE HINTSET: FLASHOFF Mask    */\r
+#define SCU_HIBERNATE_HINTSET_FLASHPD_Pos     3                                                       /*!< SCU_HIBERNATE HINTSET: FLASHPD Position */\r
+#define SCU_HIBERNATE_HINTSET_FLASHPD_Msk     (0x01UL << SCU_HIBERNATE_HINTSET_FLASHPD_Pos)           /*!< SCU_HIBERNATE HINTSET: FLASHPD Mask     */\r
+#define SCU_HIBERNATE_HINTSET_POFFD_Pos       4                                                       /*!< SCU_HIBERNATE HINTSET: POFFD Position   */\r
+#define SCU_HIBERNATE_HINTSET_POFFD_Msk       (0x01UL << SCU_HIBERNATE_HINTSET_POFFD_Pos)             /*!< SCU_HIBERNATE HINTSET: POFFD Mask       */\r
+#define SCU_HIBERNATE_HINTSET_PPODEL_Pos      16                                                      /*!< SCU_HIBERNATE HINTSET: PPODEL Position  */\r
+#define SCU_HIBERNATE_HINTSET_PPODEL_Msk      (0x03UL << SCU_HIBERNATE_HINTSET_PPODEL_Pos)            /*!< SCU_HIBERNATE HINTSET: PPODEL Mask      */\r
+#define SCU_HIBERNATE_HINTSET_POFFH_Pos       20                                                      /*!< SCU_HIBERNATE HINTSET: POFFH Position   */\r
+#define SCU_HIBERNATE_HINTSET_POFFH_Msk       (0x01UL << SCU_HIBERNATE_HINTSET_POFFH_Pos)             /*!< SCU_HIBERNATE HINTSET: POFFH Mask       */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       struct 'SCU_POWER' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_POWER_PWRSTAT  ----------------------------- */\r
+#define SCU_POWER_PWRSTAT_HIBEN_Pos           0                                                       /*!< SCU_POWER PWRSTAT: HIBEN Position       */\r
+#define SCU_POWER_PWRSTAT_HIBEN_Msk           (0x01UL << SCU_POWER_PWRSTAT_HIBEN_Pos)                 /*!< SCU_POWER PWRSTAT: HIBEN Mask           */\r
+#define SCU_POWER_PWRSTAT_USBPHYPDQ_Pos       16                                                      /*!< SCU_POWER PWRSTAT: USBPHYPDQ Position   */\r
+#define SCU_POWER_PWRSTAT_USBPHYPDQ_Msk       (0x01UL << SCU_POWER_PWRSTAT_USBPHYPDQ_Pos)             /*!< SCU_POWER PWRSTAT: USBPHYPDQ Mask       */\r
+#define SCU_POWER_PWRSTAT_USBOTGEN_Pos        17                                                      /*!< SCU_POWER PWRSTAT: USBOTGEN Position    */\r
+#define SCU_POWER_PWRSTAT_USBOTGEN_Msk        (0x01UL << SCU_POWER_PWRSTAT_USBOTGEN_Pos)              /*!< SCU_POWER PWRSTAT: USBOTGEN Mask        */\r
+#define SCU_POWER_PWRSTAT_USBPUWQ_Pos         18                                                      /*!< SCU_POWER PWRSTAT: USBPUWQ Position     */\r
+#define SCU_POWER_PWRSTAT_USBPUWQ_Msk         (0x01UL << SCU_POWER_PWRSTAT_USBPUWQ_Pos)               /*!< SCU_POWER PWRSTAT: USBPUWQ Mask         */\r
+\r
+/* ------------------------------  SCU_POWER_PWRSET  ------------------------------ */\r
+#define SCU_POWER_PWRSET_HIB_Pos              0                                                       /*!< SCU_POWER PWRSET: HIB Position          */\r
+#define SCU_POWER_PWRSET_HIB_Msk              (0x01UL << SCU_POWER_PWRSET_HIB_Pos)                    /*!< SCU_POWER PWRSET: HIB Mask              */\r
+#define SCU_POWER_PWRSET_USBPHYPDQ_Pos        16                                                      /*!< SCU_POWER PWRSET: USBPHYPDQ Position    */\r
+#define SCU_POWER_PWRSET_USBPHYPDQ_Msk        (0x01UL << SCU_POWER_PWRSET_USBPHYPDQ_Pos)              /*!< SCU_POWER PWRSET: USBPHYPDQ Mask        */\r
+#define SCU_POWER_PWRSET_USBOTGEN_Pos         17                                                      /*!< SCU_POWER PWRSET: USBOTGEN Position     */\r
+#define SCU_POWER_PWRSET_USBOTGEN_Msk         (0x01UL << SCU_POWER_PWRSET_USBOTGEN_Pos)               /*!< SCU_POWER PWRSET: USBOTGEN Mask         */\r
+#define SCU_POWER_PWRSET_USBPUWQ_Pos          18                                                      /*!< SCU_POWER PWRSET: USBPUWQ Position      */\r
+#define SCU_POWER_PWRSET_USBPUWQ_Msk          (0x01UL << SCU_POWER_PWRSET_USBPUWQ_Pos)                /*!< SCU_POWER PWRSET: USBPUWQ Mask          */\r
+\r
+/* ------------------------------  SCU_POWER_PWRCLR  ------------------------------ */\r
+#define SCU_POWER_PWRCLR_HIB_Pos              0                                                       /*!< SCU_POWER PWRCLR: HIB Position          */\r
+#define SCU_POWER_PWRCLR_HIB_Msk              (0x01UL << SCU_POWER_PWRCLR_HIB_Pos)                    /*!< SCU_POWER PWRCLR: HIB Mask              */\r
+#define SCU_POWER_PWRCLR_USBPHYPDQ_Pos        16                                                      /*!< SCU_POWER PWRCLR: USBPHYPDQ Position    */\r
+#define SCU_POWER_PWRCLR_USBPHYPDQ_Msk        (0x01UL << SCU_POWER_PWRCLR_USBPHYPDQ_Pos)              /*!< SCU_POWER PWRCLR: USBPHYPDQ Mask        */\r
+#define SCU_POWER_PWRCLR_USBOTGEN_Pos         17                                                      /*!< SCU_POWER PWRCLR: USBOTGEN Position     */\r
+#define SCU_POWER_PWRCLR_USBOTGEN_Msk         (0x01UL << SCU_POWER_PWRCLR_USBOTGEN_Pos)               /*!< SCU_POWER PWRCLR: USBOTGEN Mask         */\r
+#define SCU_POWER_PWRCLR_USBPUWQ_Pos          18                                                      /*!< SCU_POWER PWRCLR: USBPUWQ Position      */\r
+#define SCU_POWER_PWRCLR_USBPUWQ_Msk          (0x01UL << SCU_POWER_PWRCLR_USBPUWQ_Pos)                /*!< SCU_POWER PWRCLR: USBPUWQ Mask          */\r
+\r
+/* ------------------------------  SCU_POWER_EVRSTAT  ----------------------------- */\r
+#define SCU_POWER_EVRSTAT_OV13_Pos            1                                                       /*!< SCU_POWER EVRSTAT: OV13 Position        */\r
+#define SCU_POWER_EVRSTAT_OV13_Msk            (0x01UL << SCU_POWER_EVRSTAT_OV13_Pos)                  /*!< SCU_POWER EVRSTAT: OV13 Mask            */\r
+\r
+/* ----------------------------  SCU_POWER_EVRVADCSTAT  --------------------------- */\r
+#define SCU_POWER_EVRVADCSTAT_VADC13V_Pos     0                                                       /*!< SCU_POWER EVRVADCSTAT: VADC13V Position */\r
+#define SCU_POWER_EVRVADCSTAT_VADC13V_Msk     (0x000000ffUL << SCU_POWER_EVRVADCSTAT_VADC13V_Pos)     /*!< SCU_POWER EVRVADCSTAT: VADC13V Mask     */\r
+#define SCU_POWER_EVRVADCSTAT_VADC33V_Pos     8                                                       /*!< SCU_POWER EVRVADCSTAT: VADC33V Position */\r
+#define SCU_POWER_EVRVADCSTAT_VADC33V_Msk     (0x000000ffUL << SCU_POWER_EVRVADCSTAT_VADC33V_Pos)     /*!< SCU_POWER EVRVADCSTAT: VADC33V Mask     */\r
+\r
+/* ------------------------------  SCU_POWER_PWRMON  ------------------------------ */\r
+#define SCU_POWER_PWRMON_THRS_Pos             0                                                       /*!< SCU_POWER PWRMON: THRS Position         */\r
+#define SCU_POWER_PWRMON_THRS_Msk             (0x000000ffUL << SCU_POWER_PWRMON_THRS_Pos)             /*!< SCU_POWER PWRMON: THRS Mask             */\r
+#define SCU_POWER_PWRMON_INTV_Pos             8                                                       /*!< SCU_POWER PWRMON: INTV Position         */\r
+#define SCU_POWER_PWRMON_INTV_Msk             (0x000000ffUL << SCU_POWER_PWRMON_INTV_Pos)             /*!< SCU_POWER PWRMON: INTV Mask             */\r
+#define SCU_POWER_PWRMON_ENB_Pos              16                                                      /*!< SCU_POWER PWRMON: ENB Position          */\r
+#define SCU_POWER_PWRMON_ENB_Msk              (0x01UL << SCU_POWER_PWRMON_ENB_Pos)                    /*!< SCU_POWER PWRMON: ENB Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       struct 'SCU_RESET' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_RESET_RSTSTAT  ----------------------------- */\r
+#define SCU_RESET_RSTSTAT_RSTSTAT_Pos         0                                                       /*!< SCU_RESET RSTSTAT: RSTSTAT Position     */\r
+#define SCU_RESET_RSTSTAT_RSTSTAT_Msk         (0x000000ffUL << SCU_RESET_RSTSTAT_RSTSTAT_Pos)         /*!< SCU_RESET RSTSTAT: RSTSTAT Mask         */\r
+#define SCU_RESET_RSTSTAT_HIBWK_Pos           8                                                       /*!< SCU_RESET RSTSTAT: HIBWK Position       */\r
+#define SCU_RESET_RSTSTAT_HIBWK_Msk           (0x01UL << SCU_RESET_RSTSTAT_HIBWK_Pos)                 /*!< SCU_RESET RSTSTAT: HIBWK Mask           */\r
+#define SCU_RESET_RSTSTAT_HIBRS_Pos           9                                                       /*!< SCU_RESET RSTSTAT: HIBRS Position       */\r
+#define SCU_RESET_RSTSTAT_HIBRS_Msk           (0x01UL << SCU_RESET_RSTSTAT_HIBRS_Pos)                 /*!< SCU_RESET RSTSTAT: HIBRS Mask           */\r
+#define SCU_RESET_RSTSTAT_LCKEN_Pos           10                                                      /*!< SCU_RESET RSTSTAT: LCKEN Position       */\r
+#define SCU_RESET_RSTSTAT_LCKEN_Msk           (0x01UL << SCU_RESET_RSTSTAT_LCKEN_Pos)                 /*!< SCU_RESET RSTSTAT: LCKEN Mask           */\r
+\r
+/* ------------------------------  SCU_RESET_RSTSET  ------------------------------ */\r
+#define SCU_RESET_RSTSET_HIBWK_Pos            8                                                       /*!< SCU_RESET RSTSET: HIBWK Position        */\r
+#define SCU_RESET_RSTSET_HIBWK_Msk            (0x01UL << SCU_RESET_RSTSET_HIBWK_Pos)                  /*!< SCU_RESET RSTSET: HIBWK Mask            */\r
+#define SCU_RESET_RSTSET_HIBRS_Pos            9                                                       /*!< SCU_RESET RSTSET: HIBRS Position        */\r
+#define SCU_RESET_RSTSET_HIBRS_Msk            (0x01UL << SCU_RESET_RSTSET_HIBRS_Pos)                  /*!< SCU_RESET RSTSET: HIBRS Mask            */\r
+#define SCU_RESET_RSTSET_LCKEN_Pos            10                                                      /*!< SCU_RESET RSTSET: LCKEN Position        */\r
+#define SCU_RESET_RSTSET_LCKEN_Msk            (0x01UL << SCU_RESET_RSTSET_LCKEN_Pos)                  /*!< SCU_RESET RSTSET: LCKEN Mask            */\r
+\r
+/* ------------------------------  SCU_RESET_RSTCLR  ------------------------------ */\r
+#define SCU_RESET_RSTCLR_RSCLR_Pos            0                                                       /*!< SCU_RESET RSTCLR: RSCLR Position        */\r
+#define SCU_RESET_RSTCLR_RSCLR_Msk            (0x01UL << SCU_RESET_RSTCLR_RSCLR_Pos)                  /*!< SCU_RESET RSTCLR: RSCLR Mask            */\r
+#define SCU_RESET_RSTCLR_HIBWK_Pos            8                                                       /*!< SCU_RESET RSTCLR: HIBWK Position        */\r
+#define SCU_RESET_RSTCLR_HIBWK_Msk            (0x01UL << SCU_RESET_RSTCLR_HIBWK_Pos)                  /*!< SCU_RESET RSTCLR: HIBWK Mask            */\r
+#define SCU_RESET_RSTCLR_HIBRS_Pos            9                                                       /*!< SCU_RESET RSTCLR: HIBRS Position        */\r
+#define SCU_RESET_RSTCLR_HIBRS_Msk            (0x01UL << SCU_RESET_RSTCLR_HIBRS_Pos)                  /*!< SCU_RESET RSTCLR: HIBRS Mask            */\r
+#define SCU_RESET_RSTCLR_LCKEN_Pos            10                                                      /*!< SCU_RESET RSTCLR: LCKEN Position        */\r
+#define SCU_RESET_RSTCLR_LCKEN_Msk            (0x01UL << SCU_RESET_RSTCLR_LCKEN_Pos)                  /*!< SCU_RESET RSTCLR: LCKEN Mask            */\r
+\r
+/* ------------------------------  SCU_RESET_PRSTAT0  ----------------------------- */\r
+#define SCU_RESET_PRSTAT0_VADCRS_Pos          0                                                       /*!< SCU_RESET PRSTAT0: VADCRS Position      */\r
+#define SCU_RESET_PRSTAT0_VADCRS_Msk          (0x01UL << SCU_RESET_PRSTAT0_VADCRS_Pos)                /*!< SCU_RESET PRSTAT0: VADCRS Mask          */\r
+#define SCU_RESET_PRSTAT0_DSDRS_Pos           1                                                       /*!< SCU_RESET PRSTAT0: DSDRS Position       */\r
+#define SCU_RESET_PRSTAT0_DSDRS_Msk           (0x01UL << SCU_RESET_PRSTAT0_DSDRS_Pos)                 /*!< SCU_RESET PRSTAT0: DSDRS Mask           */\r
+#define SCU_RESET_PRSTAT0_CCU40RS_Pos         2                                                       /*!< SCU_RESET PRSTAT0: CCU40RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU40RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU40RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU40RS Mask         */\r
+#define SCU_RESET_PRSTAT0_CCU41RS_Pos         3                                                       /*!< SCU_RESET PRSTAT0: CCU41RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU41RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU41RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU41RS Mask         */\r
+#define SCU_RESET_PRSTAT0_CCU42RS_Pos         4                                                       /*!< SCU_RESET PRSTAT0: CCU42RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU42RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU42RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU42RS Mask         */\r
+#define SCU_RESET_PRSTAT0_CCU80RS_Pos         7                                                       /*!< SCU_RESET PRSTAT0: CCU80RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU80RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU80RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU80RS Mask         */\r
+#define SCU_RESET_PRSTAT0_CCU81RS_Pos         8                                                       /*!< SCU_RESET PRSTAT0: CCU81RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU81RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU81RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU81RS Mask         */\r
+#define SCU_RESET_PRSTAT0_POSIF0RS_Pos        9                                                       /*!< SCU_RESET PRSTAT0: POSIF0RS Position    */\r
+#define SCU_RESET_PRSTAT0_POSIF0RS_Msk        (0x01UL << SCU_RESET_PRSTAT0_POSIF0RS_Pos)              /*!< SCU_RESET PRSTAT0: POSIF0RS Mask        */\r
+#define SCU_RESET_PRSTAT0_POSIF1RS_Pos        10                                                      /*!< SCU_RESET PRSTAT0: POSIF1RS Position    */\r
+#define SCU_RESET_PRSTAT0_POSIF1RS_Msk        (0x01UL << SCU_RESET_PRSTAT0_POSIF1RS_Pos)              /*!< SCU_RESET PRSTAT0: POSIF1RS Mask        */\r
+#define SCU_RESET_PRSTAT0_USIC0RS_Pos         11                                                      /*!< SCU_RESET PRSTAT0: USIC0RS Position     */\r
+#define SCU_RESET_PRSTAT0_USIC0RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_USIC0RS_Pos)               /*!< SCU_RESET PRSTAT0: USIC0RS Mask         */\r
+#define SCU_RESET_PRSTAT0_ERU1RS_Pos          16                                                      /*!< SCU_RESET PRSTAT0: ERU1RS Position      */\r
+#define SCU_RESET_PRSTAT0_ERU1RS_Msk          (0x01UL << SCU_RESET_PRSTAT0_ERU1RS_Pos)                /*!< SCU_RESET PRSTAT0: ERU1RS Mask          */\r
+#define SCU_RESET_PRSTAT0_HRPWM0RS_Pos        23                                                      /*!< SCU_RESET PRSTAT0: HRPWM0RS Position    */\r
+#define SCU_RESET_PRSTAT0_HRPWM0RS_Msk        (0x01UL << SCU_RESET_PRSTAT0_HRPWM0RS_Pos)              /*!< SCU_RESET PRSTAT0: HRPWM0RS Mask        */\r
+\r
+/* ------------------------------  SCU_RESET_PRSET0  ------------------------------ */\r
+#define SCU_RESET_PRSET0_VADCRS_Pos           0                                                       /*!< SCU_RESET PRSET0: VADCRS Position       */\r
+#define SCU_RESET_PRSET0_VADCRS_Msk           (0x01UL << SCU_RESET_PRSET0_VADCRS_Pos)                 /*!< SCU_RESET PRSET0: VADCRS Mask           */\r
+#define SCU_RESET_PRSET0_DSDRS_Pos            1                                                       /*!< SCU_RESET PRSET0: DSDRS Position        */\r
+#define SCU_RESET_PRSET0_DSDRS_Msk            (0x01UL << SCU_RESET_PRSET0_DSDRS_Pos)                  /*!< SCU_RESET PRSET0: DSDRS Mask            */\r
+#define SCU_RESET_PRSET0_CCU40RS_Pos          2                                                       /*!< SCU_RESET PRSET0: CCU40RS Position      */\r
+#define SCU_RESET_PRSET0_CCU40RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU40RS_Pos)                /*!< SCU_RESET PRSET0: CCU40RS Mask          */\r
+#define SCU_RESET_PRSET0_CCU41RS_Pos          3                                                       /*!< SCU_RESET PRSET0: CCU41RS Position      */\r
+#define SCU_RESET_PRSET0_CCU41RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU41RS_Pos)                /*!< SCU_RESET PRSET0: CCU41RS Mask          */\r
+#define SCU_RESET_PRSET0_CCU42RS_Pos          4                                                       /*!< SCU_RESET PRSET0: CCU42RS Position      */\r
+#define SCU_RESET_PRSET0_CCU42RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU42RS_Pos)                /*!< SCU_RESET PRSET0: CCU42RS Mask          */\r
+#define SCU_RESET_PRSET0_CCU80RS_Pos          7                                                       /*!< SCU_RESET PRSET0: CCU80RS Position      */\r
+#define SCU_RESET_PRSET0_CCU80RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU80RS_Pos)                /*!< SCU_RESET PRSET0: CCU80RS Mask          */\r
+#define SCU_RESET_PRSET0_CCU81RS_Pos          8                                                       /*!< SCU_RESET PRSET0: CCU81RS Position      */\r
+#define SCU_RESET_PRSET0_CCU81RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU81RS_Pos)                /*!< SCU_RESET PRSET0: CCU81RS Mask          */\r
+#define SCU_RESET_PRSET0_POSIF0RS_Pos         9                                                       /*!< SCU_RESET PRSET0: POSIF0RS Position     */\r
+#define SCU_RESET_PRSET0_POSIF0RS_Msk         (0x01UL << SCU_RESET_PRSET0_POSIF0RS_Pos)               /*!< SCU_RESET PRSET0: POSIF0RS Mask         */\r
+#define SCU_RESET_PRSET0_POSIF1RS_Pos         10                                                      /*!< SCU_RESET PRSET0: POSIF1RS Position     */\r
+#define SCU_RESET_PRSET0_POSIF1RS_Msk         (0x01UL << SCU_RESET_PRSET0_POSIF1RS_Pos)               /*!< SCU_RESET PRSET0: POSIF1RS Mask         */\r
+#define SCU_RESET_PRSET0_USIC0RS_Pos          11                                                      /*!< SCU_RESET PRSET0: USIC0RS Position      */\r
+#define SCU_RESET_PRSET0_USIC0RS_Msk          (0x01UL << SCU_RESET_PRSET0_USIC0RS_Pos)                /*!< SCU_RESET PRSET0: USIC0RS Mask          */\r
+#define SCU_RESET_PRSET0_ERU1RS_Pos           16                                                      /*!< SCU_RESET PRSET0: ERU1RS Position       */\r
+#define SCU_RESET_PRSET0_ERU1RS_Msk           (0x01UL << SCU_RESET_PRSET0_ERU1RS_Pos)                 /*!< SCU_RESET PRSET0: ERU1RS Mask           */\r
+#define SCU_RESET_PRSET0_HRPWM0RS_Pos         23                                                      /*!< SCU_RESET PRSET0: HRPWM0RS Position     */\r
+#define SCU_RESET_PRSET0_HRPWM0RS_Msk         (0x01UL << SCU_RESET_PRSET0_HRPWM0RS_Pos)               /*!< SCU_RESET PRSET0: HRPWM0RS Mask         */\r
+\r
+/* ------------------------------  SCU_RESET_PRCLR0  ------------------------------ */\r
+#define SCU_RESET_PRCLR0_VADCRS_Pos           0                                                       /*!< SCU_RESET PRCLR0: VADCRS Position       */\r
+#define SCU_RESET_PRCLR0_VADCRS_Msk           (0x01UL << SCU_RESET_PRCLR0_VADCRS_Pos)                 /*!< SCU_RESET PRCLR0: VADCRS Mask           */\r
+#define SCU_RESET_PRCLR0_DSDRS_Pos            1                                                       /*!< SCU_RESET PRCLR0: DSDRS Position        */\r
+#define SCU_RESET_PRCLR0_DSDRS_Msk            (0x01UL << SCU_RESET_PRCLR0_DSDRS_Pos)                  /*!< SCU_RESET PRCLR0: DSDRS Mask            */\r
+#define SCU_RESET_PRCLR0_CCU40RS_Pos          2                                                       /*!< SCU_RESET PRCLR0: CCU40RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU40RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU40RS_Pos)                /*!< SCU_RESET PRCLR0: CCU40RS Mask          */\r
+#define SCU_RESET_PRCLR0_CCU41RS_Pos          3                                                       /*!< SCU_RESET PRCLR0: CCU41RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU41RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU41RS_Pos)                /*!< SCU_RESET PRCLR0: CCU41RS Mask          */\r
+#define SCU_RESET_PRCLR0_CCU42RS_Pos          4                                                       /*!< SCU_RESET PRCLR0: CCU42RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU42RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU42RS_Pos)                /*!< SCU_RESET PRCLR0: CCU42RS Mask          */\r
+#define SCU_RESET_PRCLR0_CCU80RS_Pos          7                                                       /*!< SCU_RESET PRCLR0: CCU80RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU80RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU80RS_Pos)                /*!< SCU_RESET PRCLR0: CCU80RS Mask          */\r
+#define SCU_RESET_PRCLR0_CCU81RS_Pos          8                                                       /*!< SCU_RESET PRCLR0: CCU81RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU81RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU81RS_Pos)                /*!< SCU_RESET PRCLR0: CCU81RS Mask          */\r
+#define SCU_RESET_PRCLR0_POSIF0RS_Pos         9                                                       /*!< SCU_RESET PRCLR0: POSIF0RS Position     */\r
+#define SCU_RESET_PRCLR0_POSIF0RS_Msk         (0x01UL << SCU_RESET_PRCLR0_POSIF0RS_Pos)               /*!< SCU_RESET PRCLR0: POSIF0RS Mask         */\r
+#define SCU_RESET_PRCLR0_POSIF1RS_Pos         10                                                      /*!< SCU_RESET PRCLR0: POSIF1RS Position     */\r
+#define SCU_RESET_PRCLR0_POSIF1RS_Msk         (0x01UL << SCU_RESET_PRCLR0_POSIF1RS_Pos)               /*!< SCU_RESET PRCLR0: POSIF1RS Mask         */\r
+#define SCU_RESET_PRCLR0_USIC0RS_Pos          11                                                      /*!< SCU_RESET PRCLR0: USIC0RS Position      */\r
+#define SCU_RESET_PRCLR0_USIC0RS_Msk          (0x01UL << SCU_RESET_PRCLR0_USIC0RS_Pos)                /*!< SCU_RESET PRCLR0: USIC0RS Mask          */\r
+#define SCU_RESET_PRCLR0_ERU1RS_Pos           16                                                      /*!< SCU_RESET PRCLR0: ERU1RS Position       */\r
+#define SCU_RESET_PRCLR0_ERU1RS_Msk           (0x01UL << SCU_RESET_PRCLR0_ERU1RS_Pos)                 /*!< SCU_RESET PRCLR0: ERU1RS Mask           */\r
+#define SCU_RESET_PRCLR0_HRPWM0RS_Pos         23                                                      /*!< SCU_RESET PRCLR0: HRPWM0RS Position     */\r
+#define SCU_RESET_PRCLR0_HRPWM0RS_Msk         (0x01UL << SCU_RESET_PRCLR0_HRPWM0RS_Pos)               /*!< SCU_RESET PRCLR0: HRPWM0RS Mask         */\r
+\r
+/* ------------------------------  SCU_RESET_PRSTAT1  ----------------------------- */\r
+#define SCU_RESET_PRSTAT1_CCU43RS_Pos         0                                                       /*!< SCU_RESET PRSTAT1: CCU43RS Position     */\r
+#define SCU_RESET_PRSTAT1_CCU43RS_Msk         (0x01UL << SCU_RESET_PRSTAT1_CCU43RS_Pos)               /*!< SCU_RESET PRSTAT1: CCU43RS Mask         */\r
+#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos      3                                                       /*!< SCU_RESET PRSTAT1: LEDTSCU0RS Position  */\r
+#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk      (0x01UL << SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos)            /*!< SCU_RESET PRSTAT1: LEDTSCU0RS Mask      */\r
+#define SCU_RESET_PRSTAT1_MCAN0RS_Pos         4                                                       /*!< SCU_RESET PRSTAT1: MCAN0RS Position     */\r
+#define SCU_RESET_PRSTAT1_MCAN0RS_Msk         (0x01UL << SCU_RESET_PRSTAT1_MCAN0RS_Pos)               /*!< SCU_RESET PRSTAT1: MCAN0RS Mask         */\r
+#define SCU_RESET_PRSTAT1_DACRS_Pos           5                                                       /*!< SCU_RESET PRSTAT1: DACRS Position       */\r
+#define SCU_RESET_PRSTAT1_DACRS_Msk           (0x01UL << SCU_RESET_PRSTAT1_DACRS_Pos)                 /*!< SCU_RESET PRSTAT1: DACRS Mask           */\r
+#define SCU_RESET_PRSTAT1_USIC1RS_Pos         7                                                       /*!< SCU_RESET PRSTAT1: USIC1RS Position     */\r
+#define SCU_RESET_PRSTAT1_USIC1RS_Msk         (0x01UL << SCU_RESET_PRSTAT1_USIC1RS_Pos)               /*!< SCU_RESET PRSTAT1: USIC1RS Mask         */\r
+#define SCU_RESET_PRSTAT1_PPORTSRS_Pos        9                                                       /*!< SCU_RESET PRSTAT1: PPORTSRS Position    */\r
+#define SCU_RESET_PRSTAT1_PPORTSRS_Msk        (0x01UL << SCU_RESET_PRSTAT1_PPORTSRS_Pos)              /*!< SCU_RESET PRSTAT1: PPORTSRS Mask        */\r
+\r
+/* ------------------------------  SCU_RESET_PRSET1  ------------------------------ */\r
+#define SCU_RESET_PRSET1_CCU43RS_Pos          0                                                       /*!< SCU_RESET PRSET1: CCU43RS Position      */\r
+#define SCU_RESET_PRSET1_CCU43RS_Msk          (0x01UL << SCU_RESET_PRSET1_CCU43RS_Pos)                /*!< SCU_RESET PRSET1: CCU43RS Mask          */\r
+#define SCU_RESET_PRSET1_LEDTSCU0RS_Pos       3                                                       /*!< SCU_RESET PRSET1: LEDTSCU0RS Position   */\r
+#define SCU_RESET_PRSET1_LEDTSCU0RS_Msk       (0x01UL << SCU_RESET_PRSET1_LEDTSCU0RS_Pos)             /*!< SCU_RESET PRSET1: LEDTSCU0RS Mask       */\r
+#define SCU_RESET_PRSET1_MCAN0RS_Pos          4                                                       /*!< SCU_RESET PRSET1: MCAN0RS Position      */\r
+#define SCU_RESET_PRSET1_MCAN0RS_Msk          (0x01UL << SCU_RESET_PRSET1_MCAN0RS_Pos)                /*!< SCU_RESET PRSET1: MCAN0RS Mask          */\r
+#define SCU_RESET_PRSET1_DACRS_Pos            5                                                       /*!< SCU_RESET PRSET1: DACRS Position        */\r
+#define SCU_RESET_PRSET1_DACRS_Msk            (0x01UL << SCU_RESET_PRSET1_DACRS_Pos)                  /*!< SCU_RESET PRSET1: DACRS Mask            */\r
+#define SCU_RESET_PRSET1_USIC1RS_Pos          7                                                       /*!< SCU_RESET PRSET1: USIC1RS Position      */\r
+#define SCU_RESET_PRSET1_USIC1RS_Msk          (0x01UL << SCU_RESET_PRSET1_USIC1RS_Pos)                /*!< SCU_RESET PRSET1: USIC1RS Mask          */\r
+#define SCU_RESET_PRSET1_PPORTSRS_Pos         9                                                       /*!< SCU_RESET PRSET1: PPORTSRS Position     */\r
+#define SCU_RESET_PRSET1_PPORTSRS_Msk         (0x01UL << SCU_RESET_PRSET1_PPORTSRS_Pos)               /*!< SCU_RESET PRSET1: PPORTSRS Mask         */\r
+\r
+/* ------------------------------  SCU_RESET_PRCLR1  ------------------------------ */\r
+#define SCU_RESET_PRCLR1_CCU43RS_Pos          0                                                       /*!< SCU_RESET PRCLR1: CCU43RS Position      */\r
+#define SCU_RESET_PRCLR1_CCU43RS_Msk          (0x01UL << SCU_RESET_PRCLR1_CCU43RS_Pos)                /*!< SCU_RESET PRCLR1: CCU43RS Mask          */\r
+#define SCU_RESET_PRCLR1_LEDTSCU0RS_Pos       3                                                       /*!< SCU_RESET PRCLR1: LEDTSCU0RS Position   */\r
+#define SCU_RESET_PRCLR1_LEDTSCU0RS_Msk       (0x01UL << SCU_RESET_PRCLR1_LEDTSCU0RS_Pos)             /*!< SCU_RESET PRCLR1: LEDTSCU0RS Mask       */\r
+#define SCU_RESET_PRCLR1_MCAN0RS_Pos          4                                                       /*!< SCU_RESET PRCLR1: MCAN0RS Position      */\r
+#define SCU_RESET_PRCLR1_MCAN0RS_Msk          (0x01UL << SCU_RESET_PRCLR1_MCAN0RS_Pos)                /*!< SCU_RESET PRCLR1: MCAN0RS Mask          */\r
+#define SCU_RESET_PRCLR1_DACRS_Pos            5                                                       /*!< SCU_RESET PRCLR1: DACRS Position        */\r
+#define SCU_RESET_PRCLR1_DACRS_Msk            (0x01UL << SCU_RESET_PRCLR1_DACRS_Pos)                  /*!< SCU_RESET PRCLR1: DACRS Mask            */\r
+#define SCU_RESET_PRCLR1_USIC1RS_Pos          7                                                       /*!< SCU_RESET PRCLR1: USIC1RS Position      */\r
+#define SCU_RESET_PRCLR1_USIC1RS_Msk          (0x01UL << SCU_RESET_PRCLR1_USIC1RS_Pos)                /*!< SCU_RESET PRCLR1: USIC1RS Mask          */\r
+#define SCU_RESET_PRCLR1_PPORTSRS_Pos         9                                                       /*!< SCU_RESET PRCLR1: PPORTSRS Position     */\r
+#define SCU_RESET_PRCLR1_PPORTSRS_Msk         (0x01UL << SCU_RESET_PRCLR1_PPORTSRS_Pos)               /*!< SCU_RESET PRCLR1: PPORTSRS Mask         */\r
+\r
+/* ------------------------------  SCU_RESET_PRSTAT2  ----------------------------- */\r
+#define SCU_RESET_PRSTAT2_WDTRS_Pos           1                                                       /*!< SCU_RESET PRSTAT2: WDTRS Position       */\r
+#define SCU_RESET_PRSTAT2_WDTRS_Msk           (0x01UL << SCU_RESET_PRSTAT2_WDTRS_Pos)                 /*!< SCU_RESET PRSTAT2: WDTRS Mask           */\r
+#define SCU_RESET_PRSTAT2_ETH0RS_Pos          2                                                       /*!< SCU_RESET PRSTAT2: ETH0RS Position      */\r
+#define SCU_RESET_PRSTAT2_ETH0RS_Msk          (0x01UL << SCU_RESET_PRSTAT2_ETH0RS_Pos)                /*!< SCU_RESET PRSTAT2: ETH0RS Mask          */\r
+#define SCU_RESET_PRSTAT2_DMA0RS_Pos          4                                                       /*!< SCU_RESET PRSTAT2: DMA0RS Position      */\r
+#define SCU_RESET_PRSTAT2_DMA0RS_Msk          (0x01UL << SCU_RESET_PRSTAT2_DMA0RS_Pos)                /*!< SCU_RESET PRSTAT2: DMA0RS Mask          */\r
+#define SCU_RESET_PRSTAT2_FCERS_Pos           6                                                       /*!< SCU_RESET PRSTAT2: FCERS Position       */\r
+#define SCU_RESET_PRSTAT2_FCERS_Msk           (0x01UL << SCU_RESET_PRSTAT2_FCERS_Pos)                 /*!< SCU_RESET PRSTAT2: FCERS Mask           */\r
+#define SCU_RESET_PRSTAT2_USBRS_Pos           7                                                       /*!< SCU_RESET PRSTAT2: USBRS Position       */\r
+#define SCU_RESET_PRSTAT2_USBRS_Msk           (0x01UL << SCU_RESET_PRSTAT2_USBRS_Pos)                 /*!< SCU_RESET PRSTAT2: USBRS Mask           */\r
+\r
+/* ------------------------------  SCU_RESET_PRSET2  ------------------------------ */\r
+#define SCU_RESET_PRSET2_WDTRS_Pos            1                                                       /*!< SCU_RESET PRSET2: WDTRS Position        */\r
+#define SCU_RESET_PRSET2_WDTRS_Msk            (0x01UL << SCU_RESET_PRSET2_WDTRS_Pos)                  /*!< SCU_RESET PRSET2: WDTRS Mask            */\r
+#define SCU_RESET_PRSET2_ETH0RS_Pos           2                                                       /*!< SCU_RESET PRSET2: ETH0RS Position       */\r
+#define SCU_RESET_PRSET2_ETH0RS_Msk           (0x01UL << SCU_RESET_PRSET2_ETH0RS_Pos)                 /*!< SCU_RESET PRSET2: ETH0RS Mask           */\r
+#define SCU_RESET_PRSET2_DMA0RS_Pos           4                                                       /*!< SCU_RESET PRSET2: DMA0RS Position       */\r
+#define SCU_RESET_PRSET2_DMA0RS_Msk           (0x01UL << SCU_RESET_PRSET2_DMA0RS_Pos)                 /*!< SCU_RESET PRSET2: DMA0RS Mask           */\r
+#define SCU_RESET_PRSET2_FCERS_Pos            6                                                       /*!< SCU_RESET PRSET2: FCERS Position        */\r
+#define SCU_RESET_PRSET2_FCERS_Msk            (0x01UL << SCU_RESET_PRSET2_FCERS_Pos)                  /*!< SCU_RESET PRSET2: FCERS Mask            */\r
+#define SCU_RESET_PRSET2_USBRS_Pos            7                                                       /*!< SCU_RESET PRSET2: USBRS Position        */\r
+#define SCU_RESET_PRSET2_USBRS_Msk            (0x01UL << SCU_RESET_PRSET2_USBRS_Pos)                  /*!< SCU_RESET PRSET2: USBRS Mask            */\r
+\r
+/* ------------------------------  SCU_RESET_PRCLR2  ------------------------------ */\r
+#define SCU_RESET_PRCLR2_WDTRS_Pos            1                                                       /*!< SCU_RESET PRCLR2: WDTRS Position        */\r
+#define SCU_RESET_PRCLR2_WDTRS_Msk            (0x01UL << SCU_RESET_PRCLR2_WDTRS_Pos)                  /*!< SCU_RESET PRCLR2: WDTRS Mask            */\r
+#define SCU_RESET_PRCLR2_ETH0RS_Pos           2                                                       /*!< SCU_RESET PRCLR2: ETH0RS Position       */\r
+#define SCU_RESET_PRCLR2_ETH0RS_Msk           (0x01UL << SCU_RESET_PRCLR2_ETH0RS_Pos)                 /*!< SCU_RESET PRCLR2: ETH0RS Mask           */\r
+#define SCU_RESET_PRCLR2_DMA0RS_Pos           4                                                       /*!< SCU_RESET PRCLR2: DMA0RS Position       */\r
+#define SCU_RESET_PRCLR2_DMA0RS_Msk           (0x01UL << SCU_RESET_PRCLR2_DMA0RS_Pos)                 /*!< SCU_RESET PRCLR2: DMA0RS Mask           */\r
+#define SCU_RESET_PRCLR2_FCERS_Pos            6                                                       /*!< SCU_RESET PRCLR2: FCERS Position        */\r
+#define SCU_RESET_PRCLR2_FCERS_Msk            (0x01UL << SCU_RESET_PRCLR2_FCERS_Pos)                  /*!< SCU_RESET PRCLR2: FCERS Mask            */\r
+#define SCU_RESET_PRCLR2_USBRS_Pos            7                                                       /*!< SCU_RESET PRCLR2: USBRS Position        */\r
+#define SCU_RESET_PRCLR2_USBRS_Msk            (0x01UL << SCU_RESET_PRCLR2_USBRS_Pos)                  /*!< SCU_RESET PRCLR2: USBRS Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'LEDTS' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  LEDTS_ID  ---------------------------------- */\r
+#define LEDTS_ID_MOD_REV_Pos                  0                                                       /*!< LEDTS ID: MOD_REV Position              */\r
+#define LEDTS_ID_MOD_REV_Msk                  (0x000000ffUL << LEDTS_ID_MOD_REV_Pos)                  /*!< LEDTS ID: MOD_REV Mask                  */\r
+#define LEDTS_ID_MOD_TYPE_Pos                 8                                                       /*!< LEDTS ID: MOD_TYPE Position             */\r
+#define LEDTS_ID_MOD_TYPE_Msk                 (0x000000ffUL << LEDTS_ID_MOD_TYPE_Pos)                 /*!< LEDTS ID: MOD_TYPE Mask                 */\r
+#define LEDTS_ID_MOD_NUMBER_Pos               16                                                      /*!< LEDTS ID: MOD_NUMBER Position           */\r
+#define LEDTS_ID_MOD_NUMBER_Msk               (0x0000ffffUL << LEDTS_ID_MOD_NUMBER_Pos)               /*!< LEDTS ID: MOD_NUMBER Mask               */\r
+\r
+/* --------------------------------  LEDTS_GLOBCTL  ------------------------------- */\r
+#define LEDTS_GLOBCTL_TS_EN_Pos               0                                                       /*!< LEDTS GLOBCTL: TS_EN Position           */\r
+#define LEDTS_GLOBCTL_TS_EN_Msk               (0x01UL << LEDTS_GLOBCTL_TS_EN_Pos)                     /*!< LEDTS GLOBCTL: TS_EN Mask               */\r
+#define LEDTS_GLOBCTL_LD_EN_Pos               1                                                       /*!< LEDTS GLOBCTL: LD_EN Position           */\r
+#define LEDTS_GLOBCTL_LD_EN_Msk               (0x01UL << LEDTS_GLOBCTL_LD_EN_Pos)                     /*!< LEDTS GLOBCTL: LD_EN Mask               */\r
+#define LEDTS_GLOBCTL_CMTR_Pos                2                                                       /*!< LEDTS GLOBCTL: CMTR Position            */\r
+#define LEDTS_GLOBCTL_CMTR_Msk                (0x01UL << LEDTS_GLOBCTL_CMTR_Pos)                      /*!< LEDTS GLOBCTL: CMTR Mask                */\r
+#define LEDTS_GLOBCTL_ENSYNC_Pos              3                                                       /*!< LEDTS GLOBCTL: ENSYNC Position          */\r
+#define LEDTS_GLOBCTL_ENSYNC_Msk              (0x01UL << LEDTS_GLOBCTL_ENSYNC_Pos)                    /*!< LEDTS GLOBCTL: ENSYNC Mask              */\r
+#define LEDTS_GLOBCTL_SUSCFG_Pos              8                                                       /*!< LEDTS GLOBCTL: SUSCFG Position          */\r
+#define LEDTS_GLOBCTL_SUSCFG_Msk              (0x01UL << LEDTS_GLOBCTL_SUSCFG_Pos)                    /*!< LEDTS GLOBCTL: SUSCFG Mask              */\r
+#define LEDTS_GLOBCTL_MASKVAL_Pos             9                                                       /*!< LEDTS GLOBCTL: MASKVAL Position         */\r
+#define LEDTS_GLOBCTL_MASKVAL_Msk             (0x07UL << LEDTS_GLOBCTL_MASKVAL_Pos)                   /*!< LEDTS GLOBCTL: MASKVAL Mask             */\r
+#define LEDTS_GLOBCTL_FENVAL_Pos              12                                                      /*!< LEDTS GLOBCTL: FENVAL Position          */\r
+#define LEDTS_GLOBCTL_FENVAL_Msk              (0x01UL << LEDTS_GLOBCTL_FENVAL_Pos)                    /*!< LEDTS GLOBCTL: FENVAL Mask              */\r
+#define LEDTS_GLOBCTL_ITS_EN_Pos              13                                                      /*!< LEDTS GLOBCTL: ITS_EN Position          */\r
+#define LEDTS_GLOBCTL_ITS_EN_Msk              (0x01UL << LEDTS_GLOBCTL_ITS_EN_Pos)                    /*!< LEDTS GLOBCTL: ITS_EN Mask              */\r
+#define LEDTS_GLOBCTL_ITF_EN_Pos              14                                                      /*!< LEDTS GLOBCTL: ITF_EN Position          */\r
+#define LEDTS_GLOBCTL_ITF_EN_Msk              (0x01UL << LEDTS_GLOBCTL_ITF_EN_Pos)                    /*!< LEDTS GLOBCTL: ITF_EN Mask              */\r
+#define LEDTS_GLOBCTL_ITP_EN_Pos              15                                                      /*!< LEDTS GLOBCTL: ITP_EN Position          */\r
+#define LEDTS_GLOBCTL_ITP_EN_Msk              (0x01UL << LEDTS_GLOBCTL_ITP_EN_Pos)                    /*!< LEDTS GLOBCTL: ITP_EN Mask              */\r
+#define LEDTS_GLOBCTL_CLK_PS_Pos              16                                                      /*!< LEDTS GLOBCTL: CLK_PS Position          */\r
+#define LEDTS_GLOBCTL_CLK_PS_Msk              (0x0000ffffUL << LEDTS_GLOBCTL_CLK_PS_Pos)              /*!< LEDTS GLOBCTL: CLK_PS Mask              */\r
+\r
+/* ---------------------------------  LEDTS_FNCTL  -------------------------------- */\r
+#define LEDTS_FNCTL_PADT_Pos                  0                                                       /*!< LEDTS FNCTL: PADT Position              */\r
+#define LEDTS_FNCTL_PADT_Msk                  (0x07UL << LEDTS_FNCTL_PADT_Pos)                        /*!< LEDTS FNCTL: PADT Mask                  */\r
+#define LEDTS_FNCTL_PADTSW_Pos                3                                                       /*!< LEDTS FNCTL: PADTSW Position            */\r
+#define LEDTS_FNCTL_PADTSW_Msk                (0x01UL << LEDTS_FNCTL_PADTSW_Pos)                      /*!< LEDTS FNCTL: PADTSW Mask                */\r
+#define LEDTS_FNCTL_EPULL_Pos                 4                                                       /*!< LEDTS FNCTL: EPULL Position             */\r
+#define LEDTS_FNCTL_EPULL_Msk                 (0x01UL << LEDTS_FNCTL_EPULL_Pos)                       /*!< LEDTS FNCTL: EPULL Mask                 */\r
+#define LEDTS_FNCTL_FNCOL_Pos                 5                                                       /*!< LEDTS FNCTL: FNCOL Position             */\r
+#define LEDTS_FNCTL_FNCOL_Msk                 (0x07UL << LEDTS_FNCTL_FNCOL_Pos)                       /*!< LEDTS FNCTL: FNCOL Mask                 */\r
+#define LEDTS_FNCTL_ACCCNT_Pos                16                                                      /*!< LEDTS FNCTL: ACCCNT Position            */\r
+#define LEDTS_FNCTL_ACCCNT_Msk                (0x0fUL << LEDTS_FNCTL_ACCCNT_Pos)                      /*!< LEDTS FNCTL: ACCCNT Mask                */\r
+#define LEDTS_FNCTL_TSCCMP_Pos                20                                                      /*!< LEDTS FNCTL: TSCCMP Position            */\r
+#define LEDTS_FNCTL_TSCCMP_Msk                (0x01UL << LEDTS_FNCTL_TSCCMP_Pos)                      /*!< LEDTS FNCTL: TSCCMP Mask                */\r
+#define LEDTS_FNCTL_TSOEXT_Pos                21                                                      /*!< LEDTS FNCTL: TSOEXT Position            */\r
+#define LEDTS_FNCTL_TSOEXT_Msk                (0x03UL << LEDTS_FNCTL_TSOEXT_Pos)                      /*!< LEDTS FNCTL: TSOEXT Mask                */\r
+#define LEDTS_FNCTL_TSCTRR_Pos                23                                                      /*!< LEDTS FNCTL: TSCTRR Position            */\r
+#define LEDTS_FNCTL_TSCTRR_Msk                (0x01UL << LEDTS_FNCTL_TSCTRR_Pos)                      /*!< LEDTS FNCTL: TSCTRR Mask                */\r
+#define LEDTS_FNCTL_TSCTRSAT_Pos              24                                                      /*!< LEDTS FNCTL: TSCTRSAT Position          */\r
+#define LEDTS_FNCTL_TSCTRSAT_Msk              (0x01UL << LEDTS_FNCTL_TSCTRSAT_Pos)                    /*!< LEDTS FNCTL: TSCTRSAT Mask              */\r
+#define LEDTS_FNCTL_NR_TSIN_Pos               25                                                      /*!< LEDTS FNCTL: NR_TSIN Position           */\r
+#define LEDTS_FNCTL_NR_TSIN_Msk               (0x07UL << LEDTS_FNCTL_NR_TSIN_Pos)                     /*!< LEDTS FNCTL: NR_TSIN Mask               */\r
+#define LEDTS_FNCTL_COLLEV_Pos                28                                                      /*!< LEDTS FNCTL: COLLEV Position            */\r
+#define LEDTS_FNCTL_COLLEV_Msk                (0x01UL << LEDTS_FNCTL_COLLEV_Pos)                      /*!< LEDTS FNCTL: COLLEV Mask                */\r
+#define LEDTS_FNCTL_NR_LEDCOL_Pos             29                                                      /*!< LEDTS FNCTL: NR_LEDCOL Position         */\r
+#define LEDTS_FNCTL_NR_LEDCOL_Msk             (0x07UL << LEDTS_FNCTL_NR_LEDCOL_Pos)                   /*!< LEDTS FNCTL: NR_LEDCOL Mask             */\r
+\r
+/* ---------------------------------  LEDTS_EVFR  --------------------------------- */\r
+#define LEDTS_EVFR_TSF_Pos                    0                                                       /*!< LEDTS EVFR: TSF Position                */\r
+#define LEDTS_EVFR_TSF_Msk                    (0x01UL << LEDTS_EVFR_TSF_Pos)                          /*!< LEDTS EVFR: TSF Mask                    */\r
+#define LEDTS_EVFR_TFF_Pos                    1                                                       /*!< LEDTS EVFR: TFF Position                */\r
+#define LEDTS_EVFR_TFF_Msk                    (0x01UL << LEDTS_EVFR_TFF_Pos)                          /*!< LEDTS EVFR: TFF Mask                    */\r
+#define LEDTS_EVFR_TPF_Pos                    2                                                       /*!< LEDTS EVFR: TPF Position                */\r
+#define LEDTS_EVFR_TPF_Msk                    (0x01UL << LEDTS_EVFR_TPF_Pos)                          /*!< LEDTS EVFR: TPF Mask                    */\r
+#define LEDTS_EVFR_TSCTROVF_Pos               3                                                       /*!< LEDTS EVFR: TSCTROVF Position           */\r
+#define LEDTS_EVFR_TSCTROVF_Msk               (0x01UL << LEDTS_EVFR_TSCTROVF_Pos)                     /*!< LEDTS EVFR: TSCTROVF Mask               */\r
+#define LEDTS_EVFR_CTSF_Pos                   16                                                      /*!< LEDTS EVFR: CTSF Position               */\r
+#define LEDTS_EVFR_CTSF_Msk                   (0x01UL << LEDTS_EVFR_CTSF_Pos)                         /*!< LEDTS EVFR: CTSF Mask                   */\r
+#define LEDTS_EVFR_CTFF_Pos                   17                                                      /*!< LEDTS EVFR: CTFF Position               */\r
+#define LEDTS_EVFR_CTFF_Msk                   (0x01UL << LEDTS_EVFR_CTFF_Pos)                         /*!< LEDTS EVFR: CTFF Mask                   */\r
+#define LEDTS_EVFR_CTPF_Pos                   18                                                      /*!< LEDTS EVFR: CTPF Position               */\r
+#define LEDTS_EVFR_CTPF_Msk                   (0x01UL << LEDTS_EVFR_CTPF_Pos)                         /*!< LEDTS EVFR: CTPF Mask                   */\r
+\r
+/* ---------------------------------  LEDTS_TSVAL  -------------------------------- */\r
+#define LEDTS_TSVAL_TSCTRVALR_Pos             0                                                       /*!< LEDTS TSVAL: TSCTRVALR Position         */\r
+#define LEDTS_TSVAL_TSCTRVALR_Msk             (0x0000ffffUL << LEDTS_TSVAL_TSCTRVALR_Pos)             /*!< LEDTS TSVAL: TSCTRVALR Mask             */\r
+#define LEDTS_TSVAL_TSCTRVAL_Pos              16                                                      /*!< LEDTS TSVAL: TSCTRVAL Position          */\r
+#define LEDTS_TSVAL_TSCTRVAL_Msk              (0x0000ffffUL << LEDTS_TSVAL_TSCTRVAL_Pos)              /*!< LEDTS TSVAL: TSCTRVAL Mask              */\r
+\r
+/* ---------------------------------  LEDTS_LINE0  -------------------------------- */\r
+#define LEDTS_LINE0_LINE_0_Pos                0                                                       /*!< LEDTS LINE0: LINE_0 Position            */\r
+#define LEDTS_LINE0_LINE_0_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_0_Pos)                /*!< LEDTS LINE0: LINE_0 Mask                */\r
+#define LEDTS_LINE0_LINE_1_Pos                8                                                       /*!< LEDTS LINE0: LINE_1 Position            */\r
+#define LEDTS_LINE0_LINE_1_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_1_Pos)                /*!< LEDTS LINE0: LINE_1 Mask                */\r
+#define LEDTS_LINE0_LINE_2_Pos                16                                                      /*!< LEDTS LINE0: LINE_2 Position            */\r
+#define LEDTS_LINE0_LINE_2_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_2_Pos)                /*!< LEDTS LINE0: LINE_2 Mask                */\r
+#define LEDTS_LINE0_LINE_3_Pos                24                                                      /*!< LEDTS LINE0: LINE_3 Position            */\r
+#define LEDTS_LINE0_LINE_3_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_3_Pos)                /*!< LEDTS LINE0: LINE_3 Mask                */\r
+\r
+/* ---------------------------------  LEDTS_LINE1  -------------------------------- */\r
+#define LEDTS_LINE1_LINE_4_Pos                0                                                       /*!< LEDTS LINE1: LINE_4 Position            */\r
+#define LEDTS_LINE1_LINE_4_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_4_Pos)                /*!< LEDTS LINE1: LINE_4 Mask                */\r
+#define LEDTS_LINE1_LINE_5_Pos                8                                                       /*!< LEDTS LINE1: LINE_5 Position            */\r
+#define LEDTS_LINE1_LINE_5_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_5_Pos)                /*!< LEDTS LINE1: LINE_5 Mask                */\r
+#define LEDTS_LINE1_LINE_6_Pos                16                                                      /*!< LEDTS LINE1: LINE_6 Position            */\r
+#define LEDTS_LINE1_LINE_6_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_6_Pos)                /*!< LEDTS LINE1: LINE_6 Mask                */\r
+#define LEDTS_LINE1_LINE_A_Pos                24                                                      /*!< LEDTS LINE1: LINE_A Position            */\r
+#define LEDTS_LINE1_LINE_A_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_A_Pos)                /*!< LEDTS LINE1: LINE_A Mask                */\r
+\r
+/* --------------------------------  LEDTS_LDCMP0  -------------------------------- */\r
+#define LEDTS_LDCMP0_CMP_LD0_Pos              0                                                       /*!< LEDTS LDCMP0: CMP_LD0 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD0_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD0_Pos)              /*!< LEDTS LDCMP0: CMP_LD0 Mask              */\r
+#define LEDTS_LDCMP0_CMP_LD1_Pos              8                                                       /*!< LEDTS LDCMP0: CMP_LD1 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD1_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD1_Pos)              /*!< LEDTS LDCMP0: CMP_LD1 Mask              */\r
+#define LEDTS_LDCMP0_CMP_LD2_Pos              16                                                      /*!< LEDTS LDCMP0: CMP_LD2 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD2_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD2_Pos)              /*!< LEDTS LDCMP0: CMP_LD2 Mask              */\r
+#define LEDTS_LDCMP0_CMP_LD3_Pos              24                                                      /*!< LEDTS LDCMP0: CMP_LD3 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD3_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD3_Pos)              /*!< LEDTS LDCMP0: CMP_LD3 Mask              */\r
+\r
+/* --------------------------------  LEDTS_LDCMP1  -------------------------------- */\r
+#define LEDTS_LDCMP1_CMP_LD4_Pos              0                                                       /*!< LEDTS LDCMP1: CMP_LD4 Position          */\r
+#define LEDTS_LDCMP1_CMP_LD4_Msk              (0x000000ffUL << LEDTS_LDCMP1_CMP_LD4_Pos)              /*!< LEDTS LDCMP1: CMP_LD4 Mask              */\r
+#define LEDTS_LDCMP1_CMP_LD5_Pos              8                                                       /*!< LEDTS LDCMP1: CMP_LD5 Position          */\r
+#define LEDTS_LDCMP1_CMP_LD5_Msk              (0x000000ffUL << LEDTS_LDCMP1_CMP_LD5_Pos)              /*!< LEDTS LDCMP1: CMP_LD5 Mask              */\r
+#define LEDTS_LDCMP1_CMP_LD6_Pos              16                                                      /*!< LEDTS LDCMP1: CMP_LD6 Position          */\r
+#define LEDTS_LDCMP1_CMP_LD6_Msk              (0x000000ffUL << LEDTS_LDCMP1_CMP_LD6_Pos)              /*!< LEDTS LDCMP1: CMP_LD6 Mask              */\r
+#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos        24                                                      /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Position    */\r
+#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk        (0x000000ffUL << LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos)        /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Mask        */\r
+\r
+/* --------------------------------  LEDTS_TSCMP0  -------------------------------- */\r
+#define LEDTS_TSCMP0_CMP_TS0_Pos              0                                                       /*!< LEDTS TSCMP0: CMP_TS0 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS0_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS0_Pos)              /*!< LEDTS TSCMP0: CMP_TS0 Mask              */\r
+#define LEDTS_TSCMP0_CMP_TS1_Pos              8                                                       /*!< LEDTS TSCMP0: CMP_TS1 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS1_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS1_Pos)              /*!< LEDTS TSCMP0: CMP_TS1 Mask              */\r
+#define LEDTS_TSCMP0_CMP_TS2_Pos              16                                                      /*!< LEDTS TSCMP0: CMP_TS2 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS2_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS2_Pos)              /*!< LEDTS TSCMP0: CMP_TS2 Mask              */\r
+#define LEDTS_TSCMP0_CMP_TS3_Pos              24                                                      /*!< LEDTS TSCMP0: CMP_TS3 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS3_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS3_Pos)              /*!< LEDTS TSCMP0: CMP_TS3 Mask              */\r
+\r
+/* --------------------------------  LEDTS_TSCMP1  -------------------------------- */\r
+#define LEDTS_TSCMP1_CMP_TS4_Pos              0                                                       /*!< LEDTS TSCMP1: CMP_TS4 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS4_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS4_Pos)              /*!< LEDTS TSCMP1: CMP_TS4 Mask              */\r
+#define LEDTS_TSCMP1_CMP_TS5_Pos              8                                                       /*!< LEDTS TSCMP1: CMP_TS5 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS5_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS5_Pos)              /*!< LEDTS TSCMP1: CMP_TS5 Mask              */\r
+#define LEDTS_TSCMP1_CMP_TS6_Pos              16                                                      /*!< LEDTS TSCMP1: CMP_TS6 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS6_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS6_Pos)              /*!< LEDTS TSCMP1: CMP_TS6 Mask              */\r
+#define LEDTS_TSCMP1_CMP_TS7_Pos              24                                                      /*!< LEDTS TSCMP1: CMP_TS7 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS7_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS7_Pos)              /*!< LEDTS TSCMP1: CMP_TS7 Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'ETH0_CON' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  ETH0_CON_ETH0_CON  ----------------------------- */\r
+#define ETH_CON_RXD0_Pos            0                                                       /*!< ETH0_CON ETH0_CON: RXD0 Position        */\r
+#define ETH_CON_RXD0_Msk            (0x03UL << ETH_CON_RXD0_Pos)                  /*!< ETH0_CON ETH0_CON: RXD0 Mask            */\r
+#define ETH_CON_RXD1_Pos            2                                                       /*!< ETH0_CON ETH0_CON: RXD1 Position        */\r
+#define ETH_CON_RXD1_Msk            (0x03UL << ETH_CON_RXD1_Pos)                  /*!< ETH0_CON ETH0_CON: RXD1 Mask            */\r
+#define ETH_CON_RXD2_Pos            4                                                       /*!< ETH0_CON ETH0_CON: RXD2 Position        */\r
+#define ETH_CON_RXD2_Msk            (0x03UL << ETH_CON_RXD2_Pos)                  /*!< ETH0_CON ETH0_CON: RXD2 Mask            */\r
+#define ETH_CON_RXD3_Pos            6                                                       /*!< ETH0_CON ETH0_CON: RXD3 Position        */\r
+#define ETH_CON_RXD3_Msk            (0x03UL << ETH_CON_RXD3_Pos)                  /*!< ETH0_CON ETH0_CON: RXD3 Mask            */\r
+#define ETH_CON_CLK_RMII_Pos        8                                                       /*!< ETH0_CON ETH0_CON: CLK_RMII Position    */\r
+#define ETH_CON_CLK_RMII_Msk        (0x03UL << ETH_CON_CLK_RMII_Pos)              /*!< ETH0_CON ETH0_CON: CLK_RMII Mask        */\r
+#define ETH_CON_CRS_DV_Pos          10                                                      /*!< ETH0_CON ETH0_CON: CRS_DV Position      */\r
+#define ETH_CON_CRS_DV_Msk          (0x03UL << ETH_CON_CRS_DV_Pos)                /*!< ETH0_CON ETH0_CON: CRS_DV Mask          */\r
+#define ETH_CON_CRS_Pos             12                                                      /*!< ETH0_CON ETH0_CON: CRS Position         */\r
+#define ETH_CON_CRS_Msk             (0x03UL << ETH_CON_CRS_Pos)                   /*!< ETH0_CON ETH0_CON: CRS Mask             */\r
+#define ETH_CON_RXER_Pos            14                                                      /*!< ETH0_CON ETH0_CON: RXER Position        */\r
+#define ETH_CON_RXER_Msk            (0x03UL << ETH_CON_RXER_Pos)                  /*!< ETH0_CON ETH0_CON: RXER Mask            */\r
+#define ETH_CON_COL_Pos             16                                                      /*!< ETH0_CON ETH0_CON: COL Position         */\r
+#define ETH_CON_COL_Msk             (0x03UL << ETH_CON_COL_Pos)                   /*!< ETH0_CON ETH0_CON: COL Mask             */\r
+#define ETH_CON_CLK_TX_Pos          18                                                      /*!< ETH0_CON ETH0_CON: CLK_TX Position      */\r
+#define ETH_CON_CLK_TX_Msk          (0x03UL << ETH_CON_CLK_TX_Pos)                /*!< ETH0_CON ETH0_CON: CLK_TX Mask          */\r
+#define ETH_CON_MDIO_Pos            22                                                      /*!< ETH0_CON ETH0_CON: MDIO Position        */\r
+#define ETH_CON_MDIO_Msk            (0x03UL << ETH_CON_MDIO_Pos)                  /*!< ETH0_CON ETH0_CON: MDIO Mask            */\r
+#define ETH_CON_INFSEL_Pos          26                                                      /*!< ETH0_CON ETH0_CON: INFSEL Position      */\r
+#define ETH_CON_INFSEL_Msk          (0x01UL << ETH_CON_INFSEL_Pos)                /*!< ETH0_CON ETH0_CON: INFSEL Mask          */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'ETH' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------  ETH_MAC_CONFIGURATION  --------------------------- */\r
+#define ETH_MAC_CONFIGURATION_PRELEN_Pos      0                                                       /*!< ETH MAC_CONFIGURATION: PRELEN Position  */\r
+#define ETH_MAC_CONFIGURATION_PRELEN_Msk      (0x03UL << ETH_MAC_CONFIGURATION_PRELEN_Pos)            /*!< ETH MAC_CONFIGURATION: PRELEN Mask      */\r
+#define ETH_MAC_CONFIGURATION_RE_Pos          2                                                       /*!< ETH MAC_CONFIGURATION: RE Position      */\r
+#define ETH_MAC_CONFIGURATION_RE_Msk          (0x01UL << ETH_MAC_CONFIGURATION_RE_Pos)                /*!< ETH MAC_CONFIGURATION: RE Mask          */\r
+#define ETH_MAC_CONFIGURATION_TE_Pos          3                                                       /*!< ETH MAC_CONFIGURATION: TE Position      */\r
+#define ETH_MAC_CONFIGURATION_TE_Msk          (0x01UL << ETH_MAC_CONFIGURATION_TE_Pos)                /*!< ETH MAC_CONFIGURATION: TE Mask          */\r
+#define ETH_MAC_CONFIGURATION_DC_Pos          4                                                       /*!< ETH MAC_CONFIGURATION: DC Position      */\r
+#define ETH_MAC_CONFIGURATION_DC_Msk          (0x01UL << ETH_MAC_CONFIGURATION_DC_Pos)                /*!< ETH MAC_CONFIGURATION: DC Mask          */\r
+#define ETH_MAC_CONFIGURATION_BL_Pos          5                                                       /*!< ETH MAC_CONFIGURATION: BL Position      */\r
+#define ETH_MAC_CONFIGURATION_BL_Msk          (0x03UL << ETH_MAC_CONFIGURATION_BL_Pos)                /*!< ETH MAC_CONFIGURATION: BL Mask          */\r
+#define ETH_MAC_CONFIGURATION_ACS_Pos         7                                                       /*!< ETH MAC_CONFIGURATION: ACS Position     */\r
+#define ETH_MAC_CONFIGURATION_ACS_Msk         (0x01UL << ETH_MAC_CONFIGURATION_ACS_Pos)               /*!< ETH MAC_CONFIGURATION: ACS Mask         */\r
+#define ETH_MAC_CONFIGURATION_Reserved_8_Pos  8                                                       /*!< ETH MAC_CONFIGURATION: Reserved_8 Position */\r
+#define ETH_MAC_CONFIGURATION_Reserved_8_Msk  (0x01UL << ETH_MAC_CONFIGURATION_Reserved_8_Pos)        /*!< ETH MAC_CONFIGURATION: Reserved_8 Mask  */\r
+#define ETH_MAC_CONFIGURATION_DR_Pos          9                                                       /*!< ETH MAC_CONFIGURATION: DR Position      */\r
+#define ETH_MAC_CONFIGURATION_DR_Msk          (0x01UL << ETH_MAC_CONFIGURATION_DR_Pos)                /*!< ETH MAC_CONFIGURATION: DR Mask          */\r
+#define ETH_MAC_CONFIGURATION_IPC_Pos         10                                                      /*!< ETH MAC_CONFIGURATION: IPC Position     */\r
+#define ETH_MAC_CONFIGURATION_IPC_Msk         (0x01UL << ETH_MAC_CONFIGURATION_IPC_Pos)               /*!< ETH MAC_CONFIGURATION: IPC Mask         */\r
+#define ETH_MAC_CONFIGURATION_DM_Pos          11                                                      /*!< ETH MAC_CONFIGURATION: DM Position      */\r
+#define ETH_MAC_CONFIGURATION_DM_Msk          (0x01UL << ETH_MAC_CONFIGURATION_DM_Pos)                /*!< ETH MAC_CONFIGURATION: DM Mask          */\r
+#define ETH_MAC_CONFIGURATION_LM_Pos          12                                                      /*!< ETH MAC_CONFIGURATION: LM Position      */\r
+#define ETH_MAC_CONFIGURATION_LM_Msk          (0x01UL << ETH_MAC_CONFIGURATION_LM_Pos)                /*!< ETH MAC_CONFIGURATION: LM Mask          */\r
+#define ETH_MAC_CONFIGURATION_DO_Pos          13                                                      /*!< ETH MAC_CONFIGURATION: DO Position      */\r
+#define ETH_MAC_CONFIGURATION_DO_Msk          (0x01UL << ETH_MAC_CONFIGURATION_DO_Pos)                /*!< ETH MAC_CONFIGURATION: DO Mask          */\r
+#define ETH_MAC_CONFIGURATION_FES_Pos         14                                                      /*!< ETH MAC_CONFIGURATION: FES Position     */\r
+#define ETH_MAC_CONFIGURATION_FES_Msk         (0x01UL << ETH_MAC_CONFIGURATION_FES_Pos)               /*!< ETH MAC_CONFIGURATION: FES Mask         */\r
+#define ETH_MAC_CONFIGURATION_DCRS_Pos        16                                                      /*!< ETH MAC_CONFIGURATION: DCRS Position    */\r
+#define ETH_MAC_CONFIGURATION_DCRS_Msk        (0x01UL << ETH_MAC_CONFIGURATION_DCRS_Pos)              /*!< ETH MAC_CONFIGURATION: DCRS Mask        */\r
+#define ETH_MAC_CONFIGURATION_IFG_Pos         17                                                      /*!< ETH MAC_CONFIGURATION: IFG Position     */\r
+#define ETH_MAC_CONFIGURATION_IFG_Msk         (0x07UL << ETH_MAC_CONFIGURATION_IFG_Pos)               /*!< ETH MAC_CONFIGURATION: IFG Mask         */\r
+#define ETH_MAC_CONFIGURATION_JE_Pos          20                                                      /*!< ETH MAC_CONFIGURATION: JE Position      */\r
+#define ETH_MAC_CONFIGURATION_JE_Msk          (0x01UL << ETH_MAC_CONFIGURATION_JE_Pos)                /*!< ETH MAC_CONFIGURATION: JE Mask          */\r
+#define ETH_MAC_CONFIGURATION_BE_Pos          21                                                      /*!< ETH MAC_CONFIGURATION: BE Position      */\r
+#define ETH_MAC_CONFIGURATION_BE_Msk          (0x01UL << ETH_MAC_CONFIGURATION_BE_Pos)                /*!< ETH MAC_CONFIGURATION: BE Mask          */\r
+#define ETH_MAC_CONFIGURATION_JD_Pos          22                                                      /*!< ETH MAC_CONFIGURATION: JD Position      */\r
+#define ETH_MAC_CONFIGURATION_JD_Msk          (0x01UL << ETH_MAC_CONFIGURATION_JD_Pos)                /*!< ETH MAC_CONFIGURATION: JD Mask          */\r
+#define ETH_MAC_CONFIGURATION_WD_Pos          23                                                      /*!< ETH MAC_CONFIGURATION: WD Position      */\r
+#define ETH_MAC_CONFIGURATION_WD_Msk          (0x01UL << ETH_MAC_CONFIGURATION_WD_Pos)                /*!< ETH MAC_CONFIGURATION: WD Mask          */\r
+#define ETH_MAC_CONFIGURATION_TC_Pos          24                                                      /*!< ETH MAC_CONFIGURATION: TC Position      */\r
+#define ETH_MAC_CONFIGURATION_TC_Msk          (0x01UL << ETH_MAC_CONFIGURATION_TC_Pos)                /*!< ETH MAC_CONFIGURATION: TC Mask          */\r
+#define ETH_MAC_CONFIGURATION_CST_Pos         25                                                      /*!< ETH MAC_CONFIGURATION: CST Position     */\r
+#define ETH_MAC_CONFIGURATION_CST_Msk         (0x01UL << ETH_MAC_CONFIGURATION_CST_Pos)               /*!< ETH MAC_CONFIGURATION: CST Mask         */\r
+#define ETH_MAC_CONFIGURATION_Reserved_26_Pos 26                                                      /*!< ETH MAC_CONFIGURATION: Reserved_26 Position */\r
+#define ETH_MAC_CONFIGURATION_Reserved_26_Msk (0x01UL << ETH_MAC_CONFIGURATION_Reserved_26_Pos)       /*!< ETH MAC_CONFIGURATION: Reserved_26 Mask */\r
+#define ETH_MAC_CONFIGURATION_TWOKPE_Pos      27                                                      /*!< ETH MAC_CONFIGURATION: TWOKPE Position  */\r
+#define ETH_MAC_CONFIGURATION_TWOKPE_Msk      (0x01UL << ETH_MAC_CONFIGURATION_TWOKPE_Pos)            /*!< ETH MAC_CONFIGURATION: TWOKPE Mask      */\r
+#define ETH_MAC_CONFIGURATION_SARC_Pos        28                                                      /*!< ETH MAC_CONFIGURATION: SARC Position    */\r
+#define ETH_MAC_CONFIGURATION_SARC_Msk        (0x07UL << ETH_MAC_CONFIGURATION_SARC_Pos)              /*!< ETH MAC_CONFIGURATION: SARC Mask        */\r
+#define ETH_MAC_CONFIGURATION_Reserved_31_Pos 31                                                      /*!< ETH MAC_CONFIGURATION: Reserved_31 Position */\r
+#define ETH_MAC_CONFIGURATION_Reserved_31_Msk (0x01UL << ETH_MAC_CONFIGURATION_Reserved_31_Pos)       /*!< ETH MAC_CONFIGURATION: Reserved_31 Mask */\r
+\r
+/* ----------------------------  ETH_MAC_FRAME_FILTER  ---------------------------- */\r
+#define ETH_MAC_FRAME_FILTER_PR_Pos           0                                                       /*!< ETH MAC_FRAME_FILTER: PR Position       */\r
+#define ETH_MAC_FRAME_FILTER_PR_Msk           (0x01UL << ETH_MAC_FRAME_FILTER_PR_Pos)                 /*!< ETH MAC_FRAME_FILTER: PR Mask           */\r
+#define ETH_MAC_FRAME_FILTER_HUC_Pos          1                                                       /*!< ETH MAC_FRAME_FILTER: HUC Position      */\r
+#define ETH_MAC_FRAME_FILTER_HUC_Msk          (0x01UL << ETH_MAC_FRAME_FILTER_HUC_Pos)                /*!< ETH MAC_FRAME_FILTER: HUC Mask          */\r
+#define ETH_MAC_FRAME_FILTER_HMC_Pos          2                                                       /*!< ETH MAC_FRAME_FILTER: HMC Position      */\r
+#define ETH_MAC_FRAME_FILTER_HMC_Msk          (0x01UL << ETH_MAC_FRAME_FILTER_HMC_Pos)                /*!< ETH MAC_FRAME_FILTER: HMC Mask          */\r
+#define ETH_MAC_FRAME_FILTER_DAIF_Pos         3                                                       /*!< ETH MAC_FRAME_FILTER: DAIF Position     */\r
+#define ETH_MAC_FRAME_FILTER_DAIF_Msk         (0x01UL << ETH_MAC_FRAME_FILTER_DAIF_Pos)               /*!< ETH MAC_FRAME_FILTER: DAIF Mask         */\r
+#define ETH_MAC_FRAME_FILTER_PM_Pos           4                                                       /*!< ETH MAC_FRAME_FILTER: PM Position       */\r
+#define ETH_MAC_FRAME_FILTER_PM_Msk           (0x01UL << ETH_MAC_FRAME_FILTER_PM_Pos)                 /*!< ETH MAC_FRAME_FILTER: PM Mask           */\r
+#define ETH_MAC_FRAME_FILTER_DBF_Pos          5                                                       /*!< ETH MAC_FRAME_FILTER: DBF Position      */\r
+#define ETH_MAC_FRAME_FILTER_DBF_Msk          (0x01UL << ETH_MAC_FRAME_FILTER_DBF_Pos)                /*!< ETH MAC_FRAME_FILTER: DBF Mask          */\r
+#define ETH_MAC_FRAME_FILTER_PCF_Pos          6                                                       /*!< ETH MAC_FRAME_FILTER: PCF Position      */\r
+#define ETH_MAC_FRAME_FILTER_PCF_Msk          (0x03UL << ETH_MAC_FRAME_FILTER_PCF_Pos)                /*!< ETH MAC_FRAME_FILTER: PCF Mask          */\r
+#define ETH_MAC_FRAME_FILTER_SAIF_Pos         8                                                       /*!< ETH MAC_FRAME_FILTER: SAIF Position     */\r
+#define ETH_MAC_FRAME_FILTER_SAIF_Msk         (0x01UL << ETH_MAC_FRAME_FILTER_SAIF_Pos)               /*!< ETH MAC_FRAME_FILTER: SAIF Mask         */\r
+#define ETH_MAC_FRAME_FILTER_SAF_Pos          9                                                       /*!< ETH MAC_FRAME_FILTER: SAF Position      */\r
+#define ETH_MAC_FRAME_FILTER_SAF_Msk          (0x01UL << ETH_MAC_FRAME_FILTER_SAF_Pos)                /*!< ETH MAC_FRAME_FILTER: SAF Mask          */\r
+#define ETH_MAC_FRAME_FILTER_HPF_Pos          10                                                      /*!< ETH MAC_FRAME_FILTER: HPF Position      */\r
+#define ETH_MAC_FRAME_FILTER_HPF_Msk          (0x01UL << ETH_MAC_FRAME_FILTER_HPF_Pos)                /*!< ETH MAC_FRAME_FILTER: HPF Mask          */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_15_11_Pos 11                                                    /*!< ETH MAC_FRAME_FILTER: Reserved_15_11 Position */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_15_11_Msk (0x1fUL << ETH_MAC_FRAME_FILTER_Reserved_15_11_Pos)   /*!< ETH MAC_FRAME_FILTER: Reserved_15_11 Mask */\r
+#define ETH_MAC_FRAME_FILTER_VTFE_Pos         16                                                      /*!< ETH MAC_FRAME_FILTER: VTFE Position     */\r
+#define ETH_MAC_FRAME_FILTER_VTFE_Msk         (0x01UL << ETH_MAC_FRAME_FILTER_VTFE_Pos)               /*!< ETH MAC_FRAME_FILTER: VTFE Mask         */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_19_17_Pos 17                                                    /*!< ETH MAC_FRAME_FILTER: Reserved_19_17 Position */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_19_17_Msk (0x07UL << ETH_MAC_FRAME_FILTER_Reserved_19_17_Pos)   /*!< ETH MAC_FRAME_FILTER: Reserved_19_17 Mask */\r
+#define ETH_MAC_FRAME_FILTER_IPFE_Pos         20                                                      /*!< ETH MAC_FRAME_FILTER: IPFE Position     */\r
+#define ETH_MAC_FRAME_FILTER_IPFE_Msk         (0x01UL << ETH_MAC_FRAME_FILTER_IPFE_Pos)               /*!< ETH MAC_FRAME_FILTER: IPFE Mask         */\r
+#define ETH_MAC_FRAME_FILTER_DNTU_Pos         21                                                      /*!< ETH MAC_FRAME_FILTER: DNTU Position     */\r
+#define ETH_MAC_FRAME_FILTER_DNTU_Msk         (0x01UL << ETH_MAC_FRAME_FILTER_DNTU_Pos)               /*!< ETH MAC_FRAME_FILTER: DNTU Mask         */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_30_22_Pos 22                                                    /*!< ETH MAC_FRAME_FILTER: Reserved_30_22 Position */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_30_22_Msk (0x000001ffUL << ETH_MAC_FRAME_FILTER_Reserved_30_22_Pos)/*!< ETH MAC_FRAME_FILTER: Reserved_30_22 Mask */\r
+#define ETH_MAC_FRAME_FILTER_RA_Pos           31                                                      /*!< ETH MAC_FRAME_FILTER: RA Position       */\r
+#define ETH_MAC_FRAME_FILTER_RA_Msk           (0x01UL << ETH_MAC_FRAME_FILTER_RA_Pos)                 /*!< ETH MAC_FRAME_FILTER: RA Mask           */\r
+\r
+/* -----------------------------  ETH_HASH_TABLE_HIGH  ---------------------------- */\r
+#define ETH_HASH_TABLE_HIGH_HTH_Pos           0                                                       /*!< ETH HASH_TABLE_HIGH: HTH Position       */\r
+#define ETH_HASH_TABLE_HIGH_HTH_Msk           (0xffffffffUL << ETH_HASH_TABLE_HIGH_HTH_Pos)           /*!< ETH HASH_TABLE_HIGH: HTH Mask           */\r
+\r
+/* -----------------------------  ETH_HASH_TABLE_LOW  ----------------------------- */\r
+#define ETH_HASH_TABLE_LOW_HTL_Pos            0                                                       /*!< ETH HASH_TABLE_LOW: HTL Position        */\r
+#define ETH_HASH_TABLE_LOW_HTL_Msk            (0xffffffffUL << ETH_HASH_TABLE_LOW_HTL_Pos)            /*!< ETH HASH_TABLE_LOW: HTL Mask            */\r
+\r
+/* ------------------------------  ETH_GMII_ADDRESS  ------------------------------ */\r
+#define ETH_GMII_ADDRESS_MB_Pos               0                                                       /*!< ETH GMII_ADDRESS: MB Position           */\r
+#define ETH_GMII_ADDRESS_MB_Msk               (0x01UL << ETH_GMII_ADDRESS_MB_Pos)                     /*!< ETH GMII_ADDRESS: MB Mask               */\r
+#define ETH_GMII_ADDRESS_MW_Pos               1                                                       /*!< ETH GMII_ADDRESS: MW Position           */\r
+#define ETH_GMII_ADDRESS_MW_Msk               (0x01UL << ETH_GMII_ADDRESS_MW_Pos)                     /*!< ETH GMII_ADDRESS: MW Mask               */\r
+#define ETH_GMII_ADDRESS_CR_Pos               2                                                       /*!< ETH GMII_ADDRESS: CR Position           */\r
+#define ETH_GMII_ADDRESS_CR_Msk               (0x0fUL << ETH_GMII_ADDRESS_CR_Pos)                     /*!< ETH GMII_ADDRESS: CR Mask               */\r
+#define ETH_GMII_ADDRESS_MR_Pos               6                                                       /*!< ETH GMII_ADDRESS: MR Position           */\r
+#define ETH_GMII_ADDRESS_MR_Msk               (0x1fUL << ETH_GMII_ADDRESS_MR_Pos)                     /*!< ETH GMII_ADDRESS: MR Mask               */\r
+#define ETH_GMII_ADDRESS_PA_Pos               11                                                      /*!< ETH GMII_ADDRESS: PA Position           */\r
+#define ETH_GMII_ADDRESS_PA_Msk               (0x1fUL << ETH_GMII_ADDRESS_PA_Pos)                     /*!< ETH GMII_ADDRESS: PA Mask               */\r
+#define ETH_GMII_ADDRESS_Reserved_31_16_Pos   16                                                      /*!< ETH GMII_ADDRESS: Reserved_31_16 Position */\r
+#define ETH_GMII_ADDRESS_Reserved_31_16_Msk   (0x0000ffffUL << ETH_GMII_ADDRESS_Reserved_31_16_Pos)   /*!< ETH GMII_ADDRESS: Reserved_31_16 Mask   */\r
+\r
+/* --------------------------------  ETH_GMII_DATA  ------------------------------- */\r
+#define ETH_GMII_DATA_MD_Pos                  0                                                       /*!< ETH GMII_DATA: MD Position              */\r
+#define ETH_GMII_DATA_MD_Msk                  (0x0000ffffUL << ETH_GMII_DATA_MD_Pos)                  /*!< ETH GMII_DATA: MD Mask                  */\r
+#define ETH_GMII_DATA_Reserved_31_16_Pos      16                                                      /*!< ETH GMII_DATA: Reserved_31_16 Position  */\r
+#define ETH_GMII_DATA_Reserved_31_16_Msk      (0x0000ffffUL << ETH_GMII_DATA_Reserved_31_16_Pos)      /*!< ETH GMII_DATA: Reserved_31_16 Mask      */\r
+\r
+/* ------------------------------  ETH_FLOW_CONTROL  ------------------------------ */\r
+#define ETH_FLOW_CONTROL_FCA_BPA_Pos          0                                                       /*!< ETH FLOW_CONTROL: FCA_BPA Position      */\r
+#define ETH_FLOW_CONTROL_FCA_BPA_Msk          (0x01UL << ETH_FLOW_CONTROL_FCA_BPA_Pos)                /*!< ETH FLOW_CONTROL: FCA_BPA Mask          */\r
+#define ETH_FLOW_CONTROL_TFE_Pos              1                                                       /*!< ETH FLOW_CONTROL: TFE Position          */\r
+#define ETH_FLOW_CONTROL_TFE_Msk              (0x01UL << ETH_FLOW_CONTROL_TFE_Pos)                    /*!< ETH FLOW_CONTROL: TFE Mask              */\r
+#define ETH_FLOW_CONTROL_RFE_Pos              2                                                       /*!< ETH FLOW_CONTROL: RFE Position          */\r
+#define ETH_FLOW_CONTROL_RFE_Msk              (0x01UL << ETH_FLOW_CONTROL_RFE_Pos)                    /*!< ETH FLOW_CONTROL: RFE Mask              */\r
+#define ETH_FLOW_CONTROL_UP_Pos               3                                                       /*!< ETH FLOW_CONTROL: UP Position           */\r
+#define ETH_FLOW_CONTROL_UP_Msk               (0x01UL << ETH_FLOW_CONTROL_UP_Pos)                     /*!< ETH FLOW_CONTROL: UP Mask               */\r
+#define ETH_FLOW_CONTROL_PLT_Pos              4                                                       /*!< ETH FLOW_CONTROL: PLT Position          */\r
+#define ETH_FLOW_CONTROL_PLT_Msk              (0x03UL << ETH_FLOW_CONTROL_PLT_Pos)                    /*!< ETH FLOW_CONTROL: PLT Mask              */\r
+#define ETH_FLOW_CONTROL_Reserved_6_Pos       6                                                       /*!< ETH FLOW_CONTROL: Reserved_6 Position   */\r
+#define ETH_FLOW_CONTROL_Reserved_6_Msk       (0x01UL << ETH_FLOW_CONTROL_Reserved_6_Pos)             /*!< ETH FLOW_CONTROL: Reserved_6 Mask       */\r
+#define ETH_FLOW_CONTROL_DZPQ_Pos             7                                                       /*!< ETH FLOW_CONTROL: DZPQ Position         */\r
+#define ETH_FLOW_CONTROL_DZPQ_Msk             (0x01UL << ETH_FLOW_CONTROL_DZPQ_Pos)                   /*!< ETH FLOW_CONTROL: DZPQ Mask             */\r
+#define ETH_FLOW_CONTROL_Reserved_15_8_Pos    8                                                       /*!< ETH FLOW_CONTROL: Reserved_15_8 Position */\r
+#define ETH_FLOW_CONTROL_Reserved_15_8_Msk    (0x000000ffUL << ETH_FLOW_CONTROL_Reserved_15_8_Pos)    /*!< ETH FLOW_CONTROL: Reserved_15_8 Mask    */\r
+#define ETH_FLOW_CONTROL_PT_Pos               16                                                      /*!< ETH FLOW_CONTROL: PT Position           */\r
+#define ETH_FLOW_CONTROL_PT_Msk               (0x0000ffffUL << ETH_FLOW_CONTROL_PT_Pos)               /*!< ETH FLOW_CONTROL: PT Mask               */\r
+\r
+/* --------------------------------  ETH_VLAN_TAG  -------------------------------- */\r
+#define ETH_VLAN_TAG_VL_Pos                   0                                                       /*!< ETH VLAN_TAG: VL Position               */\r
+#define ETH_VLAN_TAG_VL_Msk                   (0x0000ffffUL << ETH_VLAN_TAG_VL_Pos)                   /*!< ETH VLAN_TAG: VL Mask                   */\r
+#define ETH_VLAN_TAG_ETV_Pos                  16                                                      /*!< ETH VLAN_TAG: ETV Position              */\r
+#define ETH_VLAN_TAG_ETV_Msk                  (0x01UL << ETH_VLAN_TAG_ETV_Pos)                        /*!< ETH VLAN_TAG: ETV Mask                  */\r
+#define ETH_VLAN_TAG_VTIM_Pos                 17                                                      /*!< ETH VLAN_TAG: VTIM Position             */\r
+#define ETH_VLAN_TAG_VTIM_Msk                 (0x01UL << ETH_VLAN_TAG_VTIM_Pos)                       /*!< ETH VLAN_TAG: VTIM Mask                 */\r
+#define ETH_VLAN_TAG_ESVL_Pos                 18                                                      /*!< ETH VLAN_TAG: ESVL Position             */\r
+#define ETH_VLAN_TAG_ESVL_Msk                 (0x01UL << ETH_VLAN_TAG_ESVL_Pos)                       /*!< ETH VLAN_TAG: ESVL Mask                 */\r
+#define ETH_VLAN_TAG_VTHM_Pos                 19                                                      /*!< ETH VLAN_TAG: VTHM Position             */\r
+#define ETH_VLAN_TAG_VTHM_Msk                 (0x01UL << ETH_VLAN_TAG_VTHM_Pos)                       /*!< ETH VLAN_TAG: VTHM Mask                 */\r
+#define ETH_VLAN_TAG_Reserved_31_20_Pos       20                                                      /*!< ETH VLAN_TAG: Reserved_31_20 Position   */\r
+#define ETH_VLAN_TAG_Reserved_31_20_Msk       (0x00000fffUL << ETH_VLAN_TAG_Reserved_31_20_Pos)       /*!< ETH VLAN_TAG: Reserved_31_20 Mask       */\r
+\r
+/* ---------------------------------  ETH_VERSION  -------------------------------- */\r
+#define ETH_VERSION_SNPSVER_Pos               0                                                       /*!< ETH VERSION: SNPSVER Position           */\r
+#define ETH_VERSION_SNPSVER_Msk               (0x000000ffUL << ETH_VERSION_SNPSVER_Pos)               /*!< ETH VERSION: SNPSVER Mask               */\r
+#define ETH_VERSION_USERVER_Pos               8                                                       /*!< ETH VERSION: USERVER Position           */\r
+#define ETH_VERSION_USERVER_Msk               (0x000000ffUL << ETH_VERSION_USERVER_Pos)               /*!< ETH VERSION: USERVER Mask               */\r
+#define ETH_VERSION_Reserved_31_16_Pos        16                                                      /*!< ETH VERSION: Reserved_31_16 Position    */\r
+#define ETH_VERSION_Reserved_31_16_Msk        (0x0000ffffUL << ETH_VERSION_Reserved_31_16_Pos)        /*!< ETH VERSION: Reserved_31_16 Mask        */\r
+\r
+/* ----------------------------------  ETH_DEBUG  --------------------------------- */\r
+#define ETH_DEBUG_RPESTS_Pos                  0                                                       /*!< ETH DEBUG: RPESTS Position              */\r
+#define ETH_DEBUG_RPESTS_Msk                  (0x01UL << ETH_DEBUG_RPESTS_Pos)                        /*!< ETH DEBUG: RPESTS Mask                  */\r
+#define ETH_DEBUG_RFCFCSTS_Pos                1                                                       /*!< ETH DEBUG: RFCFCSTS Position            */\r
+#define ETH_DEBUG_RFCFCSTS_Msk                (0x03UL << ETH_DEBUG_RFCFCSTS_Pos)                      /*!< ETH DEBUG: RFCFCSTS Mask                */\r
+#define ETH_DEBUG_Reserved_3_Pos              3                                                       /*!< ETH DEBUG: Reserved_3 Position          */\r
+#define ETH_DEBUG_Reserved_3_Msk              (0x01UL << ETH_DEBUG_Reserved_3_Pos)                    /*!< ETH DEBUG: Reserved_3 Mask              */\r
+#define ETH_DEBUG_RWCSTS_Pos                  4                                                       /*!< ETH DEBUG: RWCSTS Position              */\r
+#define ETH_DEBUG_RWCSTS_Msk                  (0x01UL << ETH_DEBUG_RWCSTS_Pos)                        /*!< ETH DEBUG: RWCSTS Mask                  */\r
+#define ETH_DEBUG_RRCSTS_Pos                  5                                                       /*!< ETH DEBUG: RRCSTS Position              */\r
+#define ETH_DEBUG_RRCSTS_Msk                  (0x03UL << ETH_DEBUG_RRCSTS_Pos)                        /*!< ETH DEBUG: RRCSTS Mask                  */\r
+#define ETH_DEBUG_Reserved_7_Pos              7                                                       /*!< ETH DEBUG: Reserved_7 Position          */\r
+#define ETH_DEBUG_Reserved_7_Msk              (0x01UL << ETH_DEBUG_Reserved_7_Pos)                    /*!< ETH DEBUG: Reserved_7 Mask              */\r
+#define ETH_DEBUG_RXFSTS_Pos                  8                                                       /*!< ETH DEBUG: RXFSTS Position              */\r
+#define ETH_DEBUG_RXFSTS_Msk                  (0x03UL << ETH_DEBUG_RXFSTS_Pos)                        /*!< ETH DEBUG: RXFSTS Mask                  */\r
+#define ETH_DEBUG_Reserved_15_10_Pos          10                                                      /*!< ETH DEBUG: Reserved_15_10 Position      */\r
+#define ETH_DEBUG_Reserved_15_10_Msk          (0x3fUL << ETH_DEBUG_Reserved_15_10_Pos)                /*!< ETH DEBUG: Reserved_15_10 Mask          */\r
+#define ETH_DEBUG_TPESTS_Pos                  16                                                      /*!< ETH DEBUG: TPESTS Position              */\r
+#define ETH_DEBUG_TPESTS_Msk                  (0x01UL << ETH_DEBUG_TPESTS_Pos)                        /*!< ETH DEBUG: TPESTS Mask                  */\r
+#define ETH_DEBUG_TFCSTS_Pos                  17                                                      /*!< ETH DEBUG: TFCSTS Position              */\r
+#define ETH_DEBUG_TFCSTS_Msk                  (0x03UL << ETH_DEBUG_TFCSTS_Pos)                        /*!< ETH DEBUG: TFCSTS Mask                  */\r
+#define ETH_DEBUG_TXPAUSED_Pos                19                                                      /*!< ETH DEBUG: TXPAUSED Position            */\r
+#define ETH_DEBUG_TXPAUSED_Msk                (0x01UL << ETH_DEBUG_TXPAUSED_Pos)                      /*!< ETH DEBUG: TXPAUSED Mask                */\r
+#define ETH_DEBUG_TRCSTS_Pos                  20                                                      /*!< ETH DEBUG: TRCSTS Position              */\r
+#define ETH_DEBUG_TRCSTS_Msk                  (0x03UL << ETH_DEBUG_TRCSTS_Pos)                        /*!< ETH DEBUG: TRCSTS Mask                  */\r
+#define ETH_DEBUG_TWCSTS_Pos                  22                                                      /*!< ETH DEBUG: TWCSTS Position              */\r
+#define ETH_DEBUG_TWCSTS_Msk                  (0x01UL << ETH_DEBUG_TWCSTS_Pos)                        /*!< ETH DEBUG: TWCSTS Mask                  */\r
+#define ETH_DEBUG_Reserved_23_Pos             23                                                      /*!< ETH DEBUG: Reserved_23 Position         */\r
+#define ETH_DEBUG_Reserved_23_Msk             (0x01UL << ETH_DEBUG_Reserved_23_Pos)                   /*!< ETH DEBUG: Reserved_23 Mask             */\r
+#define ETH_DEBUG_TXFSTS_Pos                  24                                                      /*!< ETH DEBUG: TXFSTS Position              */\r
+#define ETH_DEBUG_TXFSTS_Msk                  (0x01UL << ETH_DEBUG_TXFSTS_Pos)                        /*!< ETH DEBUG: TXFSTS Mask                  */\r
+#define ETH_DEBUG_TXSTSFSTS_Pos               25                                                      /*!< ETH DEBUG: TXSTSFSTS Position           */\r
+#define ETH_DEBUG_TXSTSFSTS_Msk               (0x01UL << ETH_DEBUG_TXSTSFSTS_Pos)                     /*!< ETH DEBUG: TXSTSFSTS Mask               */\r
+#define ETH_DEBUG_Reserved_31_26_Pos          26                                                      /*!< ETH DEBUG: Reserved_31_26 Position      */\r
+#define ETH_DEBUG_Reserved_31_26_Msk          (0x3fUL << ETH_DEBUG_Reserved_31_26_Pos)                /*!< ETH DEBUG: Reserved_31_26 Mask          */\r
+\r
+/* -----------------------  ETH_REMOTE_WAKE_UP_FRAME_FILTER  ---------------------- */\r
+#define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos 0                                              /*!< ETH REMOTE_WAKE_UP_FRAME_FILTER: WKUPFRMFTR Position */\r
+#define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Msk (0xffffffffUL << ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos)/*!< ETH REMOTE_WAKE_UP_FRAME_FILTER: WKUPFRMFTR Mask */\r
+\r
+/* ---------------------------  ETH_PMT_CONTROL_STATUS  --------------------------- */\r
+#define ETH_PMT_CONTROL_STATUS_PWRDWN_Pos     0                                                       /*!< ETH PMT_CONTROL_STATUS: PWRDWN Position */\r
+#define ETH_PMT_CONTROL_STATUS_PWRDWN_Msk     (0x01UL << ETH_PMT_CONTROL_STATUS_PWRDWN_Pos)           /*!< ETH PMT_CONTROL_STATUS: PWRDWN Mask     */\r
+#define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos   1                                                       /*!< ETH PMT_CONTROL_STATUS: MGKPKTEN Position */\r
+#define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Msk   (0x01UL << ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos)         /*!< ETH PMT_CONTROL_STATUS: MGKPKTEN Mask   */\r
+#define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos   2                                                       /*!< ETH PMT_CONTROL_STATUS: RWKPKTEN Position */\r
+#define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Msk   (0x01UL << ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos)         /*!< ETH PMT_CONTROL_STATUS: RWKPKTEN Mask   */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_4_3_Pos 3                                                     /*!< ETH PMT_CONTROL_STATUS: Reserved_4_3 Position */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_4_3_Msk (0x03UL << ETH_PMT_CONTROL_STATUS_Reserved_4_3_Pos)   /*!< ETH PMT_CONTROL_STATUS: Reserved_4_3 Mask */\r
+#define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos   5                                                       /*!< ETH PMT_CONTROL_STATUS: MGKPRCVD Position */\r
+#define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Msk   (0x01UL << ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos)         /*!< ETH PMT_CONTROL_STATUS: MGKPRCVD Mask   */\r
+#define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos   6                                                       /*!< ETH PMT_CONTROL_STATUS: RWKPRCVD Position */\r
+#define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Msk   (0x01UL << ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos)         /*!< ETH PMT_CONTROL_STATUS: RWKPRCVD Mask   */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_8_7_Pos 7                                                     /*!< ETH PMT_CONTROL_STATUS: Reserved_8_7 Position */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_8_7_Msk (0x03UL << ETH_PMT_CONTROL_STATUS_Reserved_8_7_Pos)   /*!< ETH PMT_CONTROL_STATUS: Reserved_8_7 Mask */\r
+#define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos  9                                                       /*!< ETH PMT_CONTROL_STATUS: GLBLUCAST Position */\r
+#define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Msk  (0x01UL << ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos)        /*!< ETH PMT_CONTROL_STATUS: GLBLUCAST Mask  */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_30_10_Pos 10                                                  /*!< ETH PMT_CONTROL_STATUS: Reserved_30_10 Position */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_30_10_Msk (0x001fffffUL << ETH_PMT_CONTROL_STATUS_Reserved_30_10_Pos)/*!< ETH PMT_CONTROL_STATUS: Reserved_30_10 Mask */\r
+#define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos 31                                                      /*!< ETH PMT_CONTROL_STATUS: RWKFILTRST Position */\r
+#define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Msk (0x01UL << ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos)       /*!< ETH PMT_CONTROL_STATUS: RWKFILTRST Mask */\r
+\r
+/* ----------------------------  ETH_INTERRUPT_STATUS  ---------------------------- */\r
+#define ETH_INTERRUPT_STATUS_Reserved_2_0_Pos 0                                                       /*!< ETH INTERRUPT_STATUS: Reserved_2_0 Position */\r
+#define ETH_INTERRUPT_STATUS_Reserved_2_0_Msk (0x07UL << ETH_INTERRUPT_STATUS_Reserved_2_0_Pos)       /*!< ETH INTERRUPT_STATUS: Reserved_2_0 Mask */\r
+#define ETH_INTERRUPT_STATUS_PMTIS_Pos        3                                                       /*!< ETH INTERRUPT_STATUS: PMTIS Position    */\r
+#define ETH_INTERRUPT_STATUS_PMTIS_Msk        (0x01UL << ETH_INTERRUPT_STATUS_PMTIS_Pos)              /*!< ETH INTERRUPT_STATUS: PMTIS Mask        */\r
+#define ETH_INTERRUPT_STATUS_MMCIS_Pos        4                                                       /*!< ETH INTERRUPT_STATUS: MMCIS Position    */\r
+#define ETH_INTERRUPT_STATUS_MMCIS_Msk        (0x01UL << ETH_INTERRUPT_STATUS_MMCIS_Pos)              /*!< ETH INTERRUPT_STATUS: MMCIS Mask        */\r
+#define ETH_INTERRUPT_STATUS_MMCRXIS_Pos      5                                                       /*!< ETH INTERRUPT_STATUS: MMCRXIS Position  */\r
+#define ETH_INTERRUPT_STATUS_MMCRXIS_Msk      (0x01UL << ETH_INTERRUPT_STATUS_MMCRXIS_Pos)            /*!< ETH INTERRUPT_STATUS: MMCRXIS Mask      */\r
+#define ETH_INTERRUPT_STATUS_MMCTXIS_Pos      6                                                       /*!< ETH INTERRUPT_STATUS: MMCTXIS Position  */\r
+#define ETH_INTERRUPT_STATUS_MMCTXIS_Msk      (0x01UL << ETH_INTERRUPT_STATUS_MMCTXIS_Pos)            /*!< ETH INTERRUPT_STATUS: MMCTXIS Mask      */\r
+#define ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos    7                                                       /*!< ETH INTERRUPT_STATUS: MMCRXIPIS Position */\r
+#define ETH_INTERRUPT_STATUS_MMCRXIPIS_Msk    (0x01UL << ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos)          /*!< ETH INTERRUPT_STATUS: MMCRXIPIS Mask    */\r
+#define ETH_INTERRUPT_STATUS_Reserved_8_Pos   8                                                       /*!< ETH INTERRUPT_STATUS: Reserved_8 Position */\r
+#define ETH_INTERRUPT_STATUS_Reserved_8_Msk   (0x01UL << ETH_INTERRUPT_STATUS_Reserved_8_Pos)         /*!< ETH INTERRUPT_STATUS: Reserved_8 Mask   */\r
+#define ETH_INTERRUPT_STATUS_TSIS_Pos         9                                                       /*!< ETH INTERRUPT_STATUS: TSIS Position     */\r
+#define ETH_INTERRUPT_STATUS_TSIS_Msk         (0x01UL << ETH_INTERRUPT_STATUS_TSIS_Pos)               /*!< ETH INTERRUPT_STATUS: TSIS Mask         */\r
+#define ETH_INTERRUPT_STATUS_Reserved_10_Pos  10                                                      /*!< ETH INTERRUPT_STATUS: Reserved_10 Position */\r
+#define ETH_INTERRUPT_STATUS_Reserved_10_Msk  (0x01UL << ETH_INTERRUPT_STATUS_Reserved_10_Pos)        /*!< ETH INTERRUPT_STATUS: Reserved_10 Mask  */\r
+#define ETH_INTERRUPT_STATUS_Reserved_31_11_Pos 11                                                    /*!< ETH INTERRUPT_STATUS: Reserved_31_11 Position */\r
+#define ETH_INTERRUPT_STATUS_Reserved_31_11_Msk (0x001fffffUL << ETH_INTERRUPT_STATUS_Reserved_31_11_Pos)/*!< ETH INTERRUPT_STATUS: Reserved_31_11 Mask */\r
+\r
+/* -----------------------------  ETH_INTERRUPT_MASK  ----------------------------- */\r
+#define ETH_INTERRUPT_MASK_Reserved_2_0_Pos   0                                                       /*!< ETH INTERRUPT_MASK: Reserved_2_0 Position */\r
+#define ETH_INTERRUPT_MASK_Reserved_2_0_Msk   (0x07UL << ETH_INTERRUPT_MASK_Reserved_2_0_Pos)         /*!< ETH INTERRUPT_MASK: Reserved_2_0 Mask   */\r
+#define ETH_INTERRUPT_MASK_PMTIM_Pos          3                                                       /*!< ETH INTERRUPT_MASK: PMTIM Position      */\r
+#define ETH_INTERRUPT_MASK_PMTIM_Msk          (0x01UL << ETH_INTERRUPT_MASK_PMTIM_Pos)                /*!< ETH INTERRUPT_MASK: PMTIM Mask          */\r
+#define ETH_INTERRUPT_MASK_Reserved_8_4_Pos   4                                                       /*!< ETH INTERRUPT_MASK: Reserved_8_4 Position */\r
+#define ETH_INTERRUPT_MASK_Reserved_8_4_Msk   (0x1fUL << ETH_INTERRUPT_MASK_Reserved_8_4_Pos)         /*!< ETH INTERRUPT_MASK: Reserved_8_4 Mask   */\r
+#define ETH_INTERRUPT_MASK_TSIM_Pos           9                                                       /*!< ETH INTERRUPT_MASK: TSIM Position       */\r
+#define ETH_INTERRUPT_MASK_TSIM_Msk           (0x01UL << ETH_INTERRUPT_MASK_TSIM_Pos)                 /*!< ETH INTERRUPT_MASK: TSIM Mask           */\r
+#define ETH_INTERRUPT_MASK_Reserved_31_10_Pos 10                                                      /*!< ETH INTERRUPT_MASK: Reserved_31_10 Position */\r
+#define ETH_INTERRUPT_MASK_Reserved_31_10_Msk (0x003fffffUL << ETH_INTERRUPT_MASK_Reserved_31_10_Pos) /*!< ETH INTERRUPT_MASK: Reserved_31_10 Mask */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS0_HIGH  --------------------------- */\r
+#define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos      0                                                       /*!< ETH MAC_ADDRESS0_HIGH: ADDRHI Position  */\r
+#define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Msk      (0x0000ffffUL << ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos)      /*!< ETH MAC_ADDRESS0_HIGH: ADDRHI Mask      */\r
+#define ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Pos 16                                                   /*!< ETH MAC_ADDRESS0_HIGH: Reserved_30_16 Position */\r
+#define ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Msk (0x00007fffUL << ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Pos)/*!< ETH MAC_ADDRESS0_HIGH: Reserved_30_16 Mask */\r
+#define ETH_MAC_ADDRESS0_HIGH_AE_Pos          31                                                      /*!< ETH MAC_ADDRESS0_HIGH: AE Position      */\r
+#define ETH_MAC_ADDRESS0_HIGH_AE_Msk          (0x01UL << ETH_MAC_ADDRESS0_HIGH_AE_Pos)                /*!< ETH MAC_ADDRESS0_HIGH: AE Mask          */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS0_LOW  ---------------------------- */\r
+#define ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos       0                                                       /*!< ETH MAC_ADDRESS0_LOW: ADDRLO Position   */\r
+#define ETH_MAC_ADDRESS0_LOW_ADDRLO_Msk       (0xffffffffUL << ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos)       /*!< ETH MAC_ADDRESS0_LOW: ADDRLO Mask       */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS1_HIGH  --------------------------- */\r
+#define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos      0                                                       /*!< ETH MAC_ADDRESS1_HIGH: ADDRHI Position  */\r
+#define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Msk      (0x0000ffffUL << ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos)      /*!< ETH MAC_ADDRESS1_HIGH: ADDRHI Mask      */\r
+#define ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Pos 16                                                   /*!< ETH MAC_ADDRESS1_HIGH: Reserved_23_16 Position */\r
+#define ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Msk (0x000000ffUL << ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Pos)/*!< ETH MAC_ADDRESS1_HIGH: Reserved_23_16 Mask */\r
+#define ETH_MAC_ADDRESS1_HIGH_MBC_Pos         24                                                      /*!< ETH MAC_ADDRESS1_HIGH: MBC Position     */\r
+#define ETH_MAC_ADDRESS1_HIGH_MBC_Msk         (0x3fUL << ETH_MAC_ADDRESS1_HIGH_MBC_Pos)               /*!< ETH MAC_ADDRESS1_HIGH: MBC Mask         */\r
+#define ETH_MAC_ADDRESS1_HIGH_SA_Pos          30                                                      /*!< ETH MAC_ADDRESS1_HIGH: SA Position      */\r
+#define ETH_MAC_ADDRESS1_HIGH_SA_Msk          (0x01UL << ETH_MAC_ADDRESS1_HIGH_SA_Pos)                /*!< ETH MAC_ADDRESS1_HIGH: SA Mask          */\r
+#define ETH_MAC_ADDRESS1_HIGH_AE_Pos          31                                                      /*!< ETH MAC_ADDRESS1_HIGH: AE Position      */\r
+#define ETH_MAC_ADDRESS1_HIGH_AE_Msk          (0x01UL << ETH_MAC_ADDRESS1_HIGH_AE_Pos)                /*!< ETH MAC_ADDRESS1_HIGH: AE Mask          */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS1_LOW  ---------------------------- */\r
+#define ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos       0                                                       /*!< ETH MAC_ADDRESS1_LOW: ADDRLO Position   */\r
+#define ETH_MAC_ADDRESS1_LOW_ADDRLO_Msk       (0xffffffffUL << ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos)       /*!< ETH MAC_ADDRESS1_LOW: ADDRLO Mask       */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS2_HIGH  --------------------------- */\r
+#define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos      0                                                       /*!< ETH MAC_ADDRESS2_HIGH: ADDRHI Position  */\r
+#define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Msk      (0x0000ffffUL << ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos)      /*!< ETH MAC_ADDRESS2_HIGH: ADDRHI Mask      */\r
+#define ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Pos 16                                                   /*!< ETH MAC_ADDRESS2_HIGH: Reserved_23_16 Position */\r
+#define ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Msk (0x000000ffUL << ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Pos)/*!< ETH MAC_ADDRESS2_HIGH: Reserved_23_16 Mask */\r
+#define ETH_MAC_ADDRESS2_HIGH_MBC_Pos         24                                                      /*!< ETH MAC_ADDRESS2_HIGH: MBC Position     */\r
+#define ETH_MAC_ADDRESS2_HIGH_MBC_Msk         (0x3fUL << ETH_MAC_ADDRESS2_HIGH_MBC_Pos)               /*!< ETH MAC_ADDRESS2_HIGH: MBC Mask         */\r
+#define ETH_MAC_ADDRESS2_HIGH_SA_Pos          30                                                      /*!< ETH MAC_ADDRESS2_HIGH: SA Position      */\r
+#define ETH_MAC_ADDRESS2_HIGH_SA_Msk          (0x01UL << ETH_MAC_ADDRESS2_HIGH_SA_Pos)                /*!< ETH MAC_ADDRESS2_HIGH: SA Mask          */\r
+#define ETH_MAC_ADDRESS2_HIGH_AE_Pos          31                                                      /*!< ETH MAC_ADDRESS2_HIGH: AE Position      */\r
+#define ETH_MAC_ADDRESS2_HIGH_AE_Msk          (0x01UL << ETH_MAC_ADDRESS2_HIGH_AE_Pos)                /*!< ETH MAC_ADDRESS2_HIGH: AE Mask          */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS2_LOW  ---------------------------- */\r
+#define ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos       0                                                       /*!< ETH MAC_ADDRESS2_LOW: ADDRLO Position   */\r
+#define ETH_MAC_ADDRESS2_LOW_ADDRLO_Msk       (0xffffffffUL << ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos)       /*!< ETH MAC_ADDRESS2_LOW: ADDRLO Mask       */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS3_HIGH  --------------------------- */\r
+#define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos      0                                                       /*!< ETH MAC_ADDRESS3_HIGH: ADDRHI Position  */\r
+#define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Msk      (0x0000ffffUL << ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos)      /*!< ETH MAC_ADDRESS3_HIGH: ADDRHI Mask      */\r
+#define ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Pos 16                                                   /*!< ETH MAC_ADDRESS3_HIGH: Reserved_23_16 Position */\r
+#define ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Msk (0x000000ffUL << ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Pos)/*!< ETH MAC_ADDRESS3_HIGH: Reserved_23_16 Mask */\r
+#define ETH_MAC_ADDRESS3_HIGH_MBC_Pos         24                                                      /*!< ETH MAC_ADDRESS3_HIGH: MBC Position     */\r
+#define ETH_MAC_ADDRESS3_HIGH_MBC_Msk         (0x3fUL << ETH_MAC_ADDRESS3_HIGH_MBC_Pos)               /*!< ETH MAC_ADDRESS3_HIGH: MBC Mask         */\r
+#define ETH_MAC_ADDRESS3_HIGH_SA_Pos          30                                                      /*!< ETH MAC_ADDRESS3_HIGH: SA Position      */\r
+#define ETH_MAC_ADDRESS3_HIGH_SA_Msk          (0x01UL << ETH_MAC_ADDRESS3_HIGH_SA_Pos)                /*!< ETH MAC_ADDRESS3_HIGH: SA Mask          */\r
+#define ETH_MAC_ADDRESS3_HIGH_AE_Pos          31                                                      /*!< ETH MAC_ADDRESS3_HIGH: AE Position      */\r
+#define ETH_MAC_ADDRESS3_HIGH_AE_Msk          (0x01UL << ETH_MAC_ADDRESS3_HIGH_AE_Pos)                /*!< ETH MAC_ADDRESS3_HIGH: AE Mask          */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS3_LOW  ---------------------------- */\r
+#define ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos       0                                                       /*!< ETH MAC_ADDRESS3_LOW: ADDRLO Position   */\r
+#define ETH_MAC_ADDRESS3_LOW_ADDRLO_Msk       (0xffffffffUL << ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos)       /*!< ETH MAC_ADDRESS3_LOW: ADDRLO Mask       */\r
+\r
+/* -------------------------------  ETH_MMC_CONTROL  ------------------------------ */\r
+#define ETH_MMC_CONTROL_CNTRST_Pos            0                                                       /*!< ETH MMC_CONTROL: CNTRST Position        */\r
+#define ETH_MMC_CONTROL_CNTRST_Msk            (0x01UL << ETH_MMC_CONTROL_CNTRST_Pos)                  /*!< ETH MMC_CONTROL: CNTRST Mask            */\r
+#define ETH_MMC_CONTROL_CNTSTOPRO_Pos         1                                                       /*!< ETH MMC_CONTROL: CNTSTOPRO Position     */\r
+#define ETH_MMC_CONTROL_CNTSTOPRO_Msk         (0x01UL << ETH_MMC_CONTROL_CNTSTOPRO_Pos)               /*!< ETH MMC_CONTROL: CNTSTOPRO Mask         */\r
+#define ETH_MMC_CONTROL_RSTONRD_Pos           2                                                       /*!< ETH MMC_CONTROL: RSTONRD Position       */\r
+#define ETH_MMC_CONTROL_RSTONRD_Msk           (0x01UL << ETH_MMC_CONTROL_RSTONRD_Pos)                 /*!< ETH MMC_CONTROL: RSTONRD Mask           */\r
+#define ETH_MMC_CONTROL_CNTFREEZ_Pos          3                                                       /*!< ETH MMC_CONTROL: CNTFREEZ Position      */\r
+#define ETH_MMC_CONTROL_CNTFREEZ_Msk          (0x01UL << ETH_MMC_CONTROL_CNTFREEZ_Pos)                /*!< ETH MMC_CONTROL: CNTFREEZ Mask          */\r
+#define ETH_MMC_CONTROL_CNTPRST_Pos           4                                                       /*!< ETH MMC_CONTROL: CNTPRST Position       */\r
+#define ETH_MMC_CONTROL_CNTPRST_Msk           (0x01UL << ETH_MMC_CONTROL_CNTPRST_Pos)                 /*!< ETH MMC_CONTROL: CNTPRST Mask           */\r
+#define ETH_MMC_CONTROL_CNTPRSTLVL_Pos        5                                                       /*!< ETH MMC_CONTROL: CNTPRSTLVL Position    */\r
+#define ETH_MMC_CONTROL_CNTPRSTLVL_Msk        (0x01UL << ETH_MMC_CONTROL_CNTPRSTLVL_Pos)              /*!< ETH MMC_CONTROL: CNTPRSTLVL Mask        */\r
+#define ETH_MMC_CONTROL_Reserved_7_6_Pos      6                                                       /*!< ETH MMC_CONTROL: Reserved_7_6 Position  */\r
+#define ETH_MMC_CONTROL_Reserved_7_6_Msk      (0x03UL << ETH_MMC_CONTROL_Reserved_7_6_Pos)            /*!< ETH MMC_CONTROL: Reserved_7_6 Mask      */\r
+#define ETH_MMC_CONTROL_UCDBC_Pos             8                                                       /*!< ETH MMC_CONTROL: UCDBC Position         */\r
+#define ETH_MMC_CONTROL_UCDBC_Msk             (0x01UL << ETH_MMC_CONTROL_UCDBC_Pos)                   /*!< ETH MMC_CONTROL: UCDBC Mask             */\r
+#define ETH_MMC_CONTROL_Reserved_31_9_Pos     9                                                       /*!< ETH MMC_CONTROL: Reserved_31_9 Position */\r
+#define ETH_MMC_CONTROL_Reserved_31_9_Msk     (0x007fffffUL << ETH_MMC_CONTROL_Reserved_31_9_Pos)     /*!< ETH MMC_CONTROL: Reserved_31_9 Mask     */\r
+\r
+/* --------------------------  ETH_MMC_RECEIVE_INTERRUPT  ------------------------- */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos 0                                                     /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBFRMIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBFRMIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos 1                                                     /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBOCTIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBOCTIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos 2                                                      /*!< ETH MMC_RECEIVE_INTERRUPT: RXGOCTIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos)     /*!< ETH MMC_RECEIVE_INTERRUPT: RXGOCTIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos 3                                                      /*!< ETH MMC_RECEIVE_INTERRUPT: RXBCGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos)     /*!< ETH MMC_RECEIVE_INTERRUPT: RXBCGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos 4                                                      /*!< ETH MMC_RECEIVE_INTERRUPT: RXMCGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos)     /*!< ETH MMC_RECEIVE_INTERRUPT: RXMCGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos 5                                                    /*!< ETH MMC_RECEIVE_INTERRUPT: RXCRCERFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCRCERFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos 6                                                   /*!< ETH MMC_RECEIVE_INTERRUPT: RXALGNERFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXALGNERFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos 7                                                     /*!< ETH MMC_RECEIVE_INTERRUPT: RXRUNTFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXRUNTFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos 8                                                    /*!< ETH MMC_RECEIVE_INTERRUPT: RXJABERFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXJABERFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos 9                                                   /*!< ETH MMC_RECEIVE_INTERRUPT: RXUSIZEGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXUSIZEGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos 10                                                  /*!< ETH MMC_RECEIVE_INTERRUPT: RXOSIZEGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXOSIZEGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos 11                                                 /*!< ETH MMC_RECEIVE_INTERRUPT: RX64OCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX64OCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos 12                                             /*!< ETH MMC_RECEIVE_INTERRUPT: RX65T127OCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX65T127OCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos 13                                            /*!< ETH MMC_RECEIVE_INTERRUPT: RX128T255OCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX128T255OCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos 14                                            /*!< ETH MMC_RECEIVE_INTERRUPT: RX256T511OCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX256T511OCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos 15                                           /*!< ETH MMC_RECEIVE_INTERRUPT: RX512T1023OCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX512T1023OCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos 16                                           /*!< ETH MMC_RECEIVE_INTERRUPT: RX1024TMAXOCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX1024TMAXOCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos 17                                                     /*!< ETH MMC_RECEIVE_INTERRUPT: RXUCGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos)     /*!< ETH MMC_RECEIVE_INTERRUPT: RXUCGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos 18                                                   /*!< ETH MMC_RECEIVE_INTERRUPT: RXLENERFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXLENERFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos 19                                                  /*!< ETH MMC_RECEIVE_INTERRUPT: RXORANGEFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXORANGEFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos 20                                                    /*!< ETH MMC_RECEIVE_INTERRUPT: RXPAUSFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXPAUSFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos 21                                                     /*!< ETH MMC_RECEIVE_INTERRUPT: RXFOVFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos)     /*!< ETH MMC_RECEIVE_INTERRUPT: RXFOVFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos 22                                                  /*!< ETH MMC_RECEIVE_INTERRUPT: RXVLANGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXVLANGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos 23                                                    /*!< ETH MMC_RECEIVE_INTERRUPT: RXWDOGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXWDOGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos 24                                                  /*!< ETH MMC_RECEIVE_INTERRUPT: RXRCVERRFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXRCVERRFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos 25                                                    /*!< ETH MMC_RECEIVE_INTERRUPT: RXCTRLFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXCTRLFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Pos 26                                               /*!< ETH MMC_RECEIVE_INTERRUPT: Reserved_31_26 Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Msk (0x3fUL << ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: Reserved_31_26 Mask */\r
+\r
+/* -------------------------  ETH_MMC_TRANSMIT_INTERRUPT  ------------------------- */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos 0                                                    /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBOCTIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBOCTIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos 1                                                    /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBFRMIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBFRMIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos 2                                                     /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos)   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos 3                                                     /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos)   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos 4                                                 /*!< ETH MMC_TRANSMIT_INTERRUPT: TX64OCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX64OCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos 5                                             /*!< ETH MMC_TRANSMIT_INTERRUPT: TX65T127OCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX65T127OCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos 6                                            /*!< ETH MMC_TRANSMIT_INTERRUPT: TX128T255OCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX128T255OCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos 7                                            /*!< ETH MMC_TRANSMIT_INTERRUPT: TX256T511OCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX256T511OCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos 8                                           /*!< ETH MMC_TRANSMIT_INTERRUPT: TX512T1023OCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX512T1023OCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos 9                                           /*!< ETH MMC_TRANSMIT_INTERRUPT: TX1024TMAXOCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX1024TMAXOCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos 10                                                   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUCGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUCGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos 11                                                   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos 12                                                   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos 13                                                /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUFLOWERFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXUFLOWERFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos 14                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXSCOLGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXSCOLGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos 15                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCOLGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCOLGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos 16                                                    /*!< ETH MMC_TRANSMIT_INTERRUPT: TXDEFFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos)   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXDEFFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos 17                                                 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXLATCOLFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXLATCOLFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos 18                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXCOLFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXCOLFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos 19                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXCARERFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXCARERFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos 20                                                    /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGOCTIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos)   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGOCTIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos 21                                                    /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGFRMIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos)   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGFRMIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos 22                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXDEFFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXDEFFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos 23                                                   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXPAUSFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXPAUSFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos 24                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXVLANGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXVLANGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos 25                                                 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXOSIZEGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXOSIZEGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Pos 26                                              /*!< ETH MMC_TRANSMIT_INTERRUPT: Reserved_31_26 Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Msk (0x3fUL << ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: Reserved_31_26 Mask */\r
+\r
+/* -----------------------  ETH_MMC_RECEIVE_INTERRUPT_MASK  ----------------------- */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos 0                                                /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBFRMIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBFRMIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos 1                                                /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBOCTIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBOCTIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos 2                                                 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGOCTIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGOCTIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos 3                                                 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXBCGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXBCGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos 4                                                 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXMCGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXMCGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos 5                                               /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCRCERFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCRCERFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos 6                                              /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXALGNERFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXALGNERFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos 7                                                /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRUNTFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRUNTFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos 8                                               /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXJABERFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXJABERFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos 9                                              /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUSIZEGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUSIZEGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos 10                                             /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXOSIZEGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXOSIZEGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos 11                                            /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX64OCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX64OCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos 12                                        /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX65T127OCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX65T127OCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos 13                                       /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX128T255OCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX128T255OCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos 14                                       /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX256T511OCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX256T511OCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos 15                                      /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX512T1023OCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX512T1023OCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos 16                                      /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX1024TMAXOCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX1024TMAXOCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos 17                                                /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUCGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUCGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos 18                                              /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXLENERFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXLENERFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos 19                                             /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXORANGEFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXORANGEFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos 20                                               /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXPAUSFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXPAUSFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos 21                                                /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXFOVFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXFOVFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos 22                                             /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXVLANGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXVLANGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos 23                                               /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXWDOGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXWDOGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos 24                                             /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRCVERRFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRCVERRFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos 25                                               /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCTRLFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCTRLFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Pos 26                                          /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: Reserved_31_26 Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Msk (0x3fUL << ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: Reserved_31_26 Mask */\r
+\r
+/* -----------------------  ETH_MMC_TRANSMIT_INTERRUPT_MASK  ---------------------- */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos 0                                               /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBOCTIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBOCTIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos 1                                               /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBFRMIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBFRMIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos 2                                                /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos 3                                                /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos 4                                            /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX64OCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX64OCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos 5                                        /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX65T127OCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX65T127OCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos 6                                       /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX128T255OCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX128T255OCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos 7                                       /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX256T511OCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX256T511OCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos 8                                      /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX512T1023OCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX512T1023OCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos 9                                      /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX1024TMAXOCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX1024TMAXOCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos 10                                              /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUCGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUCGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos 11                                              /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos 12                                              /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos 13                                           /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUFLOWERFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUFLOWERFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos 14                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXSCOLGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXSCOLGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos 15                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCOLGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCOLGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos 16                                               /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXDEFFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXDEFFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos 17                                            /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXLATCOLFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXLATCOLFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos 18                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXCOLFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXCOLFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos 19                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXCARERFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXCARERFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos 20                                               /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGOCTIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGOCTIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos 21                                               /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGFRMIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGFRMIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos 22                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXDEFFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXDEFFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos 23                                              /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXPAUSFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXPAUSFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos 24                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXVLANGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXVLANGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos 25                                            /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXOSIZEGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXOSIZEGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Pos 26                                         /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: Reserved_31_26 Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Msk (0x3fUL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: Reserved_31_26 Mask */\r
+\r
+/* -------------------------  ETH_TX_OCTET_COUNT_GOOD_BAD  ------------------------ */\r
+#define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos 0                                                     /*!< ETH TX_OCTET_COUNT_GOOD_BAD: TXOCTGB Position */\r
+#define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Msk (0xffffffffUL << ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos)/*!< ETH TX_OCTET_COUNT_GOOD_BAD: TXOCTGB Mask */\r
+\r
+/* -------------------------  ETH_TX_FRAME_COUNT_GOOD_BAD  ------------------------ */\r
+#define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos 0                                                     /*!< ETH TX_FRAME_COUNT_GOOD_BAD: TXFRMGB Position */\r
+#define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Msk (0xffffffffUL << ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos)/*!< ETH TX_FRAME_COUNT_GOOD_BAD: TXFRMGB Mask */\r
+\r
+/* ------------------------  ETH_TX_BROADCAST_FRAMES_GOOD  ------------------------ */\r
+#define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos 0                                                   /*!< ETH TX_BROADCAST_FRAMES_GOOD: TXBCASTG Position */\r
+#define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Msk (0xffffffffUL << ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos)/*!< ETH TX_BROADCAST_FRAMES_GOOD: TXBCASTG Mask */\r
+\r
+/* ------------------------  ETH_TX_MULTICAST_FRAMES_GOOD  ------------------------ */\r
+#define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos 0                                                   /*!< ETH TX_MULTICAST_FRAMES_GOOD: TXMCASTG Position */\r
+#define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Msk (0xffffffffUL << ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos)/*!< ETH TX_MULTICAST_FRAMES_GOOD: TXMCASTG Mask */\r
+\r
+/* -----------------------  ETH_TX_64OCTETS_FRAMES_GOOD_BAD  ---------------------- */\r
+#define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos 0                                               /*!< ETH TX_64OCTETS_FRAMES_GOOD_BAD: TX64OCTGB Position */\r
+#define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Msk (0xffffffffUL << ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos)/*!< ETH TX_64OCTETS_FRAMES_GOOD_BAD: TX64OCTGB Mask */\r
+\r
+/* --------------------  ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD  -------------------- */\r
+#define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos 0                                      /*!< ETH TX_65TO127OCTETS_FRAMES_GOOD_BAD: TX65_127OCTGB Position */\r
+#define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Msk (0xffffffffUL << ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos)/*!< ETH TX_65TO127OCTETS_FRAMES_GOOD_BAD: TX65_127OCTGB Mask */\r
+\r
+/* --------------------  ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos 0                                    /*!< ETH TX_128TO255OCTETS_FRAMES_GOOD_BAD: TX128_255OCTGB Position */\r
+#define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Msk (0xffffffffUL << ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos)/*!< ETH TX_128TO255OCTETS_FRAMES_GOOD_BAD: TX128_255OCTGB Mask */\r
+\r
+/* --------------------  ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos 0                                    /*!< ETH TX_256TO511OCTETS_FRAMES_GOOD_BAD: TX256_511OCTGB Position */\r
+#define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Msk (0xffffffffUL << ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos)/*!< ETH TX_256TO511OCTETS_FRAMES_GOOD_BAD: TX256_511OCTGB Mask */\r
+\r
+/* -------------------  ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos 0                                  /*!< ETH TX_512TO1023OCTETS_FRAMES_GOOD_BAD: TX512_1023OCTGB Position */\r
+#define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Msk (0xffffffffUL << ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos)/*!< ETH TX_512TO1023OCTETS_FRAMES_GOOD_BAD: TX512_1023OCTGB Mask */\r
+\r
+/* -------------------  ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos 0                                  /*!< ETH TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: TX1024_MAXOCTGB Position */\r
+#define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Msk (0xffffffffUL << ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos)/*!< ETH TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: TX1024_MAXOCTGB Mask */\r
+\r
+/* -----------------------  ETH_TX_UNICAST_FRAMES_GOOD_BAD  ----------------------- */\r
+#define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos 0                                                /*!< ETH TX_UNICAST_FRAMES_GOOD_BAD: TXUCASTGB Position */\r
+#define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Msk (0xffffffffUL << ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos)/*!< ETH TX_UNICAST_FRAMES_GOOD_BAD: TXUCASTGB Mask */\r
+\r
+/* ----------------------  ETH_TX_MULTICAST_FRAMES_GOOD_BAD  ---------------------- */\r
+#define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos 0                                              /*!< ETH TX_MULTICAST_FRAMES_GOOD_BAD: TXMCASTGB Position */\r
+#define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Msk (0xffffffffUL << ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos)/*!< ETH TX_MULTICAST_FRAMES_GOOD_BAD: TXMCASTGB Mask */\r
+\r
+/* ----------------------  ETH_TX_BROADCAST_FRAMES_GOOD_BAD  ---------------------- */\r
+#define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos 0                                              /*!< ETH TX_BROADCAST_FRAMES_GOOD_BAD: TXBCASTGB Position */\r
+#define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Msk (0xffffffffUL << ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos)/*!< ETH TX_BROADCAST_FRAMES_GOOD_BAD: TXBCASTGB Mask */\r
+\r
+/* ------------------------  ETH_TX_UNDERFLOW_ERROR_FRAMES  ----------------------- */\r
+#define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos 0                                                 /*!< ETH TX_UNDERFLOW_ERROR_FRAMES: TXUNDRFLW Position */\r
+#define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Msk (0xffffffffUL << ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos)/*!< ETH TX_UNDERFLOW_ERROR_FRAMES: TXUNDRFLW Mask */\r
+\r
+/* ---------------------  ETH_TX_SINGLE_COLLISION_GOOD_FRAMES  -------------------- */\r
+#define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos 0                                          /*!< ETH TX_SINGLE_COLLISION_GOOD_FRAMES: TXSNGLCOLG Position */\r
+#define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Msk (0xffffffffUL << ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos)/*!< ETH TX_SINGLE_COLLISION_GOOD_FRAMES: TXSNGLCOLG Mask */\r
+\r
+/* --------------------  ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES  ------------------- */\r
+#define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos 0                                        /*!< ETH TX_MULTIPLE_COLLISION_GOOD_FRAMES: TXMULTCOLG Position */\r
+#define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Msk (0xffffffffUL << ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos)/*!< ETH TX_MULTIPLE_COLLISION_GOOD_FRAMES: TXMULTCOLG Mask */\r
+\r
+/* ---------------------------  ETH_TX_DEFERRED_FRAMES  --------------------------- */\r
+#define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos    0                                                       /*!< ETH TX_DEFERRED_FRAMES: TXDEFRD Position */\r
+#define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Msk    (0xffffffffUL << ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos)    /*!< ETH TX_DEFERRED_FRAMES: TXDEFRD Mask    */\r
+\r
+/* ------------------------  ETH_TX_LATE_COLLISION_FRAMES  ------------------------ */\r
+#define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos 0                                                  /*!< ETH TX_LATE_COLLISION_FRAMES: TXLATECOL Position */\r
+#define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Msk (0xffffffffUL << ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos)/*!< ETH TX_LATE_COLLISION_FRAMES: TXLATECOL Mask */\r
+\r
+/* ----------------------  ETH_TX_EXCESSIVE_COLLISION_FRAMES  --------------------- */\r
+#define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos 0                                              /*!< ETH TX_EXCESSIVE_COLLISION_FRAMES: TXEXSCOL Position */\r
+#define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Msk (0xffffffffUL << ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos)/*!< ETH TX_EXCESSIVE_COLLISION_FRAMES: TXEXSCOL Mask */\r
+\r
+/* -------------------------  ETH_TX_CARRIER_ERROR_FRAMES  ------------------------ */\r
+#define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos 0                                                      /*!< ETH TX_CARRIER_ERROR_FRAMES: TXCARR Position */\r
+#define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Msk (0xffffffffUL << ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos)/*!< ETH TX_CARRIER_ERROR_FRAMES: TXCARR Mask */\r
+\r
+/* ---------------------------  ETH_TX_OCTET_COUNT_GOOD  -------------------------- */\r
+#define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos    0                                                       /*!< ETH TX_OCTET_COUNT_GOOD: TXOCTG Position */\r
+#define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Msk    (0xffffffffUL << ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos)    /*!< ETH TX_OCTET_COUNT_GOOD: TXOCTG Mask    */\r
+\r
+/* ---------------------------  ETH_TX_FRAME_COUNT_GOOD  -------------------------- */\r
+#define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos    0                                                       /*!< ETH TX_FRAME_COUNT_GOOD: TXFRMG Position */\r
+#define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Msk    (0xffffffffUL << ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos)    /*!< ETH TX_FRAME_COUNT_GOOD: TXFRMG Mask    */\r
+\r
+/* -----------------------  ETH_TX_EXCESSIVE_DEFERRAL_ERROR  ---------------------- */\r
+#define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos 0                                                /*!< ETH TX_EXCESSIVE_DEFERRAL_ERROR: TXEXSDEF Position */\r
+#define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Msk (0xffffffffUL << ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos)/*!< ETH TX_EXCESSIVE_DEFERRAL_ERROR: TXEXSDEF Mask */\r
+\r
+/* -----------------------------  ETH_TX_PAUSE_FRAMES  ---------------------------- */\r
+#define ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos       0                                                       /*!< ETH TX_PAUSE_FRAMES: TXPAUSE Position   */\r
+#define ETH_TX_PAUSE_FRAMES_TXPAUSE_Msk       (0xffffffffUL << ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos)       /*!< ETH TX_PAUSE_FRAMES: TXPAUSE Mask       */\r
+\r
+/* ---------------------------  ETH_TX_VLAN_FRAMES_GOOD  -------------------------- */\r
+#define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos   0                                                       /*!< ETH TX_VLAN_FRAMES_GOOD: TXVLANG Position */\r
+#define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Msk   (0xffffffffUL << ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos)   /*!< ETH TX_VLAN_FRAMES_GOOD: TXVLANG Mask   */\r
+\r
+/* --------------------------  ETH_TX_OSIZE_FRAMES_GOOD  -------------------------- */\r
+#define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos  0                                                       /*!< ETH TX_OSIZE_FRAMES_GOOD: TXOSIZG Position */\r
+#define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Msk  (0xffffffffUL << ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos)  /*!< ETH TX_OSIZE_FRAMES_GOOD: TXOSIZG Mask  */\r
+\r
+/* ------------------------  ETH_RX_FRAMES_COUNT_GOOD_BAD  ------------------------ */\r
+#define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos 0                                                    /*!< ETH RX_FRAMES_COUNT_GOOD_BAD: RXFRMGB Position */\r
+#define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Msk (0xffffffffUL << ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos)/*!< ETH RX_FRAMES_COUNT_GOOD_BAD: RXFRMGB Mask */\r
+\r
+/* -------------------------  ETH_RX_OCTET_COUNT_GOOD_BAD  ------------------------ */\r
+#define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos 0                                                     /*!< ETH RX_OCTET_COUNT_GOOD_BAD: RXOCTGB Position */\r
+#define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Msk (0xffffffffUL << ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos)/*!< ETH RX_OCTET_COUNT_GOOD_BAD: RXOCTGB Mask */\r
+\r
+/* ---------------------------  ETH_RX_OCTET_COUNT_GOOD  -------------------------- */\r
+#define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos    0                                                       /*!< ETH RX_OCTET_COUNT_GOOD: RXOCTG Position */\r
+#define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Msk    (0xffffffffUL << ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos)    /*!< ETH RX_OCTET_COUNT_GOOD: RXOCTG Mask    */\r
+\r
+/* ------------------------  ETH_RX_BROADCAST_FRAMES_GOOD  ------------------------ */\r
+#define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos 0                                                   /*!< ETH RX_BROADCAST_FRAMES_GOOD: RXBCASTG Position */\r
+#define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Msk (0xffffffffUL << ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos)/*!< ETH RX_BROADCAST_FRAMES_GOOD: RXBCASTG Mask */\r
+\r
+/* ------------------------  ETH_RX_MULTICAST_FRAMES_GOOD  ------------------------ */\r
+#define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos 0                                                   /*!< ETH RX_MULTICAST_FRAMES_GOOD: RXMCASTG Position */\r
+#define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Msk (0xffffffffUL << ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos)/*!< ETH RX_MULTICAST_FRAMES_GOOD: RXMCASTG Mask */\r
+\r
+/* ---------------------------  ETH_RX_CRC_ERROR_FRAMES  -------------------------- */\r
+#define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos  0                                                       /*!< ETH RX_CRC_ERROR_FRAMES: RXCRCERR Position */\r
+#define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Msk  (0xffffffffUL << ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos)  /*!< ETH RX_CRC_ERROR_FRAMES: RXCRCERR Mask  */\r
+\r
+/* ------------------------  ETH_RX_ALIGNMENT_ERROR_FRAMES  ----------------------- */\r
+#define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos 0                                                 /*!< ETH RX_ALIGNMENT_ERROR_FRAMES: RXALGNERR Position */\r
+#define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Msk (0xffffffffUL << ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos)/*!< ETH RX_ALIGNMENT_ERROR_FRAMES: RXALGNERR Mask */\r
+\r
+/* --------------------------  ETH_RX_RUNT_ERROR_FRAMES  -------------------------- */\r
+#define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos 0                                                      /*!< ETH RX_RUNT_ERROR_FRAMES: RXRUNTERR Position */\r
+#define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Msk (0xffffffffUL << ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos)/*!< ETH RX_RUNT_ERROR_FRAMES: RXRUNTERR Mask */\r
+\r
+/* -------------------------  ETH_RX_JABBER_ERROR_FRAMES  ------------------------- */\r
+#define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos 0                                                     /*!< ETH RX_JABBER_ERROR_FRAMES: RXJABERR Position */\r
+#define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Msk (0xffffffffUL << ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos)/*!< ETH RX_JABBER_ERROR_FRAMES: RXJABERR Mask */\r
+\r
+/* ------------------------  ETH_RX_UNDERSIZE_FRAMES_GOOD  ------------------------ */\r
+#define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos 0                                                 /*!< ETH RX_UNDERSIZE_FRAMES_GOOD: RXUNDERSZG Position */\r
+#define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Msk (0xffffffffUL << ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos)/*!< ETH RX_UNDERSIZE_FRAMES_GOOD: RXUNDERSZG Mask */\r
+\r
+/* -------------------------  ETH_RX_OVERSIZE_FRAMES_GOOD  ------------------------ */\r
+#define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos 0                                                   /*!< ETH RX_OVERSIZE_FRAMES_GOOD: RXOVERSZG Position */\r
+#define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Msk (0xffffffffUL << ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos)/*!< ETH RX_OVERSIZE_FRAMES_GOOD: RXOVERSZG Mask */\r
+\r
+/* -----------------------  ETH_RX_64OCTETS_FRAMES_GOOD_BAD  ---------------------- */\r
+#define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos 0                                               /*!< ETH RX_64OCTETS_FRAMES_GOOD_BAD: RX64OCTGB Position */\r
+#define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Msk (0xffffffffUL << ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos)/*!< ETH RX_64OCTETS_FRAMES_GOOD_BAD: RX64OCTGB Mask */\r
+\r
+/* --------------------  ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD  -------------------- */\r
+#define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos 0                                      /*!< ETH RX_65TO127OCTETS_FRAMES_GOOD_BAD: RX65_127OCTGB Position */\r
+#define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Msk (0xffffffffUL << ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos)/*!< ETH RX_65TO127OCTETS_FRAMES_GOOD_BAD: RX65_127OCTGB Mask */\r
+\r
+/* --------------------  ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos 0                                    /*!< ETH RX_128TO255OCTETS_FRAMES_GOOD_BAD: RX128_255OCTGB Position */\r
+#define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Msk (0xffffffffUL << ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos)/*!< ETH RX_128TO255OCTETS_FRAMES_GOOD_BAD: RX128_255OCTGB Mask */\r
+\r
+/* --------------------  ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos 0                                    /*!< ETH RX_256TO511OCTETS_FRAMES_GOOD_BAD: RX256_511OCTGB Position */\r
+#define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Msk (0xffffffffUL << ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos)/*!< ETH RX_256TO511OCTETS_FRAMES_GOOD_BAD: RX256_511OCTGB Mask */\r
+\r
+/* -------------------  ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos 0                                  /*!< ETH RX_512TO1023OCTETS_FRAMES_GOOD_BAD: RX512_1023OCTGB Position */\r
+#define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Msk (0xffffffffUL << ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos)/*!< ETH RX_512TO1023OCTETS_FRAMES_GOOD_BAD: RX512_1023OCTGB Mask */\r
+\r
+/* -------------------  ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos 0                                  /*!< ETH RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: RX1024_MAXOCTGB Position */\r
+#define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Msk (0xffffffffUL << ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos)/*!< ETH RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: RX1024_MAXOCTGB Mask */\r
+\r
+/* -------------------------  ETH_RX_UNICAST_FRAMES_GOOD  ------------------------- */\r
+#define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos 0                                                     /*!< ETH RX_UNICAST_FRAMES_GOOD: RXUCASTG Position */\r
+#define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Msk (0xffffffffUL << ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos)/*!< ETH RX_UNICAST_FRAMES_GOOD: RXUCASTG Mask */\r
+\r
+/* -------------------------  ETH_RX_LENGTH_ERROR_FRAMES  ------------------------- */\r
+#define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos 0                                                     /*!< ETH RX_LENGTH_ERROR_FRAMES: RXLENERR Position */\r
+#define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Msk (0xffffffffUL << ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos)/*!< ETH RX_LENGTH_ERROR_FRAMES: RXLENERR Mask */\r
+\r
+/* -----------------------  ETH_RX_OUT_OF_RANGE_TYPE_FRAMES  ---------------------- */\r
+#define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos 0                                              /*!< ETH RX_OUT_OF_RANGE_TYPE_FRAMES: RXOUTOFRNG Position */\r
+#define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Msk (0xffffffffUL << ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos)/*!< ETH RX_OUT_OF_RANGE_TYPE_FRAMES: RXOUTOFRNG Mask */\r
+\r
+/* -----------------------------  ETH_RX_PAUSE_FRAMES  ---------------------------- */\r
+#define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos    0                                                       /*!< ETH RX_PAUSE_FRAMES: RXPAUSEFRM Position */\r
+#define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Msk    (0xffffffffUL << ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos)    /*!< ETH RX_PAUSE_FRAMES: RXPAUSEFRM Mask    */\r
+\r
+/* -------------------------  ETH_RX_FIFO_OVERFLOW_FRAMES  ------------------------ */\r
+#define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos 0                                                  /*!< ETH RX_FIFO_OVERFLOW_FRAMES: RXFIFOOVFL Position */\r
+#define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Msk (0xffffffffUL << ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos)/*!< ETH RX_FIFO_OVERFLOW_FRAMES: RXFIFOOVFL Mask */\r
+\r
+/* -------------------------  ETH_RX_VLAN_FRAMES_GOOD_BAD  ------------------------ */\r
+#define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos 0                                                  /*!< ETH RX_VLAN_FRAMES_GOOD_BAD: RXVLANFRGB Position */\r
+#define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Msk (0xffffffffUL << ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos)/*!< ETH RX_VLAN_FRAMES_GOOD_BAD: RXVLANFRGB Mask */\r
+\r
+/* ------------------------  ETH_RX_WATCHDOG_ERROR_FRAMES  ------------------------ */\r
+#define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos 0                                                   /*!< ETH RX_WATCHDOG_ERROR_FRAMES: RXWDGERR Position */\r
+#define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Msk (0xffffffffUL << ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos)/*!< ETH RX_WATCHDOG_ERROR_FRAMES: RXWDGERR Mask */\r
+\r
+/* -------------------------  ETH_RX_RECEIVE_ERROR_FRAMES  ------------------------ */\r
+#define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos 0                                                    /*!< ETH RX_RECEIVE_ERROR_FRAMES: RXRCVERR Position */\r
+#define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Msk (0xffffffffUL << ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos)/*!< ETH RX_RECEIVE_ERROR_FRAMES: RXRCVERR Mask */\r
+\r
+/* -------------------------  ETH_RX_CONTROL_FRAMES_GOOD  ------------------------- */\r
+#define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos 0                                                      /*!< ETH RX_CONTROL_FRAMES_GOOD: RXCTRLG Position */\r
+#define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Msk (0xffffffffUL << ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos)/*!< ETH RX_CONTROL_FRAMES_GOOD: RXCTRLG Mask */\r
+\r
+/* ---------------------  ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK  --------------------- */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos 0                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos 1                                         /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HERFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HERFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos 2                                       /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos 3                                        /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos 4                                       /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos 5                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos 6                                         /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HERFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HERFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos 7                                       /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos 8                                            /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos 9                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPERFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPERFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos 10                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos 11                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPERFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPERFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos 12                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos 13                                         /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPERFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPERFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Pos 14                                      /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_15_14 Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_15_14 Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos 16                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos 17                                        /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HEROIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HEROIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos 18                                      /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos 19                                       /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos 20                                      /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos 21                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos 22                                        /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HEROIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HEROIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos 23                                      /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos 24                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos 25                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPEROIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPEROIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos 26                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos 27                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPEROIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPEROIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos 28                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos 29                                         /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPEROIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPEROIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Pos 30                                      /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_31_30 Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_31_30 Mask */\r
+\r
+/* ------------------------  ETH_MMC_IPC_RECEIVE_INTERRUPT  ----------------------- */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos 0                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos 1                                              /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HERFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HERFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos 2                                            /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos 3                                             /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos 4                                            /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos 5                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos 6                                              /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HERFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HERFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos 7                                            /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos 8                                                 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos 9                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPERFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPERFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos 10                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos 11                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPERFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPERFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos 12                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos 13                                              /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPERFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPERFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Pos 14                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_15_14 Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_15_14 Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos 16                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos 17                                             /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HEROIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HEROIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos 18                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos 19                                            /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos 20                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos 21                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos 22                                             /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HEROIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HEROIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos 23                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos 24                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos 25                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPEROIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPEROIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos 26                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos 27                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPEROIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPEROIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos 28                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos 29                                              /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPEROIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPEROIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Pos 30                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_31_30 Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_31_30 Mask */\r
+\r
+/* ---------------------------  ETH_RXIPV4_GOOD_FRAMES  --------------------------- */\r
+#define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos 0                                                      /*!< ETH RXIPV4_GOOD_FRAMES: RXIPV4GDFRM Position */\r
+#define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Msk (0xffffffffUL << ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos)/*!< ETH RXIPV4_GOOD_FRAMES: RXIPV4GDFRM Mask */\r
+\r
+/* -----------------------  ETH_RXIPV4_HEADER_ERROR_FRAMES  ----------------------- */\r
+#define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos 0                                          /*!< ETH RXIPV4_HEADER_ERROR_FRAMES: RXIPV4HDRERRFRM Position */\r
+#define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Msk (0xffffffffUL << ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos)/*!< ETH RXIPV4_HEADER_ERROR_FRAMES: RXIPV4HDRERRFRM Mask */\r
+\r
+/* ------------------------  ETH_RXIPV4_NO_PAYLOAD_FRAMES  ------------------------ */\r
+#define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos 0                                             /*!< ETH RXIPV4_NO_PAYLOAD_FRAMES: RXIPV4NOPAYFRM Position */\r
+#define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Msk (0xffffffffUL << ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos)/*!< ETH RXIPV4_NO_PAYLOAD_FRAMES: RXIPV4NOPAYFRM Mask */\r
+\r
+/* ------------------------  ETH_RXIPV4_FRAGMENTED_FRAMES  ------------------------ */\r
+#define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos 0                                              /*!< ETH RXIPV4_FRAGMENTED_FRAMES: RXIPV4FRAGFRM Position */\r
+#define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Msk (0xffffffffUL << ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos)/*!< ETH RXIPV4_FRAGMENTED_FRAMES: RXIPV4FRAGFRM Mask */\r
+\r
+/* -------------------  ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES  ------------------ */\r
+#define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos 0                                  /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES: RXIPV4UDSBLFRM Position */\r
+#define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Msk (0xffffffffUL << ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos)/*!< ETH RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES: RXIPV4UDSBLFRM Mask */\r
+\r
+/* ---------------------------  ETH_RXIPV6_GOOD_FRAMES  --------------------------- */\r
+#define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos 0                                                      /*!< ETH RXIPV6_GOOD_FRAMES: RXIPV6GDFRM Position */\r
+#define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Msk (0xffffffffUL << ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos)/*!< ETH RXIPV6_GOOD_FRAMES: RXIPV6GDFRM Mask */\r
+\r
+/* -----------------------  ETH_RXIPV6_HEADER_ERROR_FRAMES  ----------------------- */\r
+#define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos 0                                          /*!< ETH RXIPV6_HEADER_ERROR_FRAMES: RXIPV6HDRERRFRM Position */\r
+#define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Msk (0xffffffffUL << ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos)/*!< ETH RXIPV6_HEADER_ERROR_FRAMES: RXIPV6HDRERRFRM Mask */\r
+\r
+/* ------------------------  ETH_RXIPV6_NO_PAYLOAD_FRAMES  ------------------------ */\r
+#define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos 0                                             /*!< ETH RXIPV6_NO_PAYLOAD_FRAMES: RXIPV6NOPAYFRM Position */\r
+#define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Msk (0xffffffffUL << ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos)/*!< ETH RXIPV6_NO_PAYLOAD_FRAMES: RXIPV6NOPAYFRM Mask */\r
+\r
+/* ----------------------------  ETH_RXUDP_GOOD_FRAMES  --------------------------- */\r
+#define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos  0                                                       /*!< ETH RXUDP_GOOD_FRAMES: RXUDPGDFRM Position */\r
+#define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Msk  (0xffffffffUL << ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos)  /*!< ETH RXUDP_GOOD_FRAMES: RXUDPGDFRM Mask  */\r
+\r
+/* ---------------------------  ETH_RXUDP_ERROR_FRAMES  --------------------------- */\r
+#define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos 0                                                      /*!< ETH RXUDP_ERROR_FRAMES: RXUDPERRFRM Position */\r
+#define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Msk (0xffffffffUL << ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos)/*!< ETH RXUDP_ERROR_FRAMES: RXUDPERRFRM Mask */\r
+\r
+/* ----------------------------  ETH_RXTCP_GOOD_FRAMES  --------------------------- */\r
+#define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos  0                                                       /*!< ETH RXTCP_GOOD_FRAMES: RXTCPGDFRM Position */\r
+#define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Msk  (0xffffffffUL << ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos)  /*!< ETH RXTCP_GOOD_FRAMES: RXTCPGDFRM Mask  */\r
+\r
+/* ---------------------------  ETH_RXTCP_ERROR_FRAMES  --------------------------- */\r
+#define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos 0                                                      /*!< ETH RXTCP_ERROR_FRAMES: RXTCPERRFRM Position */\r
+#define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Msk (0xffffffffUL << ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos)/*!< ETH RXTCP_ERROR_FRAMES: RXTCPERRFRM Mask */\r
+\r
+/* ---------------------------  ETH_RXICMP_GOOD_FRAMES  --------------------------- */\r
+#define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos 0                                                      /*!< ETH RXICMP_GOOD_FRAMES: RXICMPGDFRM Position */\r
+#define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Msk (0xffffffffUL << ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos)/*!< ETH RXICMP_GOOD_FRAMES: RXICMPGDFRM Mask */\r
+\r
+/* ---------------------------  ETH_RXICMP_ERROR_FRAMES  -------------------------- */\r
+#define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos 0                                                    /*!< ETH RXICMP_ERROR_FRAMES: RXICMPERRFRM Position */\r
+#define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Msk (0xffffffffUL << ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos)/*!< ETH RXICMP_ERROR_FRAMES: RXICMPERRFRM Mask */\r
+\r
+/* ---------------------------  ETH_RXIPV4_GOOD_OCTETS  --------------------------- */\r
+#define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos 0                                                      /*!< ETH RXIPV4_GOOD_OCTETS: RXIPV4GDOCT Position */\r
+#define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Msk (0xffffffffUL << ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos)/*!< ETH RXIPV4_GOOD_OCTETS: RXIPV4GDOCT Mask */\r
+\r
+/* -----------------------  ETH_RXIPV4_HEADER_ERROR_OCTETS  ----------------------- */\r
+#define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos 0                                          /*!< ETH RXIPV4_HEADER_ERROR_OCTETS: RXIPV4HDRERROCT Position */\r
+#define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Msk (0xffffffffUL << ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos)/*!< ETH RXIPV4_HEADER_ERROR_OCTETS: RXIPV4HDRERROCT Mask */\r
+\r
+/* ------------------------  ETH_RXIPV4_NO_PAYLOAD_OCTETS  ------------------------ */\r
+#define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos 0                                             /*!< ETH RXIPV4_NO_PAYLOAD_OCTETS: RXIPV4NOPAYOCT Position */\r
+#define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Msk (0xffffffffUL << ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos)/*!< ETH RXIPV4_NO_PAYLOAD_OCTETS: RXIPV4NOPAYOCT Mask */\r
+\r
+/* ------------------------  ETH_RXIPV4_FRAGMENTED_OCTETS  ------------------------ */\r
+#define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos 0                                              /*!< ETH RXIPV4_FRAGMENTED_OCTETS: RXIPV4FRAGOCT Position */\r
+#define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Msk (0xffffffffUL << ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos)/*!< ETH RXIPV4_FRAGMENTED_OCTETS: RXIPV4FRAGOCT Mask */\r
+\r
+/* -------------------  ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS  ------------------- */\r
+#define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos 0                                   /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS: RXIPV4UDSBLOCT Position */\r
+#define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Msk (0xffffffffUL << ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos)/*!< ETH RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS: RXIPV4UDSBLOCT Mask */\r
+\r
+/* ---------------------------  ETH_RXIPV6_GOOD_OCTETS  --------------------------- */\r
+#define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos 0                                                      /*!< ETH RXIPV6_GOOD_OCTETS: RXIPV6GDOCT Position */\r
+#define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Msk (0xffffffffUL << ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos)/*!< ETH RXIPV6_GOOD_OCTETS: RXIPV6GDOCT Mask */\r
+\r
+/* -----------------------  ETH_RXIPV6_HEADER_ERROR_OCTETS  ----------------------- */\r
+#define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos 0                                          /*!< ETH RXIPV6_HEADER_ERROR_OCTETS: RXIPV6HDRERROCT Position */\r
+#define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Msk (0xffffffffUL << ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos)/*!< ETH RXIPV6_HEADER_ERROR_OCTETS: RXIPV6HDRERROCT Mask */\r
+\r
+/* ------------------------  ETH_RXIPV6_NO_PAYLOAD_OCTETS  ------------------------ */\r
+#define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos 0                                             /*!< ETH RXIPV6_NO_PAYLOAD_OCTETS: RXIPV6NOPAYOCT Position */\r
+#define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Msk (0xffffffffUL << ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos)/*!< ETH RXIPV6_NO_PAYLOAD_OCTETS: RXIPV6NOPAYOCT Mask */\r
+\r
+/* ----------------------------  ETH_RXUDP_GOOD_OCTETS  --------------------------- */\r
+#define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos  0                                                       /*!< ETH RXUDP_GOOD_OCTETS: RXUDPGDOCT Position */\r
+#define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Msk  (0xffffffffUL << ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos)  /*!< ETH RXUDP_GOOD_OCTETS: RXUDPGDOCT Mask  */\r
+\r
+/* ---------------------------  ETH_RXUDP_ERROR_OCTETS  --------------------------- */\r
+#define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos 0                                                      /*!< ETH RXUDP_ERROR_OCTETS: RXUDPERROCT Position */\r
+#define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Msk (0xffffffffUL << ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos)/*!< ETH RXUDP_ERROR_OCTETS: RXUDPERROCT Mask */\r
+\r
+/* ----------------------------  ETH_RXTCP_GOOD_OCTETS  --------------------------- */\r
+#define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos  0                                                       /*!< ETH RXTCP_GOOD_OCTETS: RXTCPGDOCT Position */\r
+#define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Msk  (0xffffffffUL << ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos)  /*!< ETH RXTCP_GOOD_OCTETS: RXTCPGDOCT Mask  */\r
+\r
+/* ---------------------------  ETH_RXTCP_ERROR_OCTETS  --------------------------- */\r
+#define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos 0                                                      /*!< ETH RXTCP_ERROR_OCTETS: RXTCPERROCT Position */\r
+#define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Msk (0xffffffffUL << ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos)/*!< ETH RXTCP_ERROR_OCTETS: RXTCPERROCT Mask */\r
+\r
+/* ---------------------------  ETH_RXICMP_GOOD_OCTETS  --------------------------- */\r
+#define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos 0                                                      /*!< ETH RXICMP_GOOD_OCTETS: RXICMPGDOCT Position */\r
+#define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Msk (0xffffffffUL << ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos)/*!< ETH RXICMP_GOOD_OCTETS: RXICMPGDOCT Mask */\r
+\r
+/* ---------------------------  ETH_RXICMP_ERROR_OCTETS  -------------------------- */\r
+#define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos 0                                                    /*!< ETH RXICMP_ERROR_OCTETS: RXICMPERROCT Position */\r
+#define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Msk (0xffffffffUL << ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos)/*!< ETH RXICMP_ERROR_OCTETS: RXICMPERROCT Mask */\r
+\r
+/* ----------------------------  ETH_TIMESTAMP_CONTROL  --------------------------- */\r
+#define ETH_TIMESTAMP_CONTROL_TSENA_Pos       0                                                       /*!< ETH TIMESTAMP_CONTROL: TSENA Position   */\r
+#define ETH_TIMESTAMP_CONTROL_TSENA_Msk       (0x01UL << ETH_TIMESTAMP_CONTROL_TSENA_Pos)             /*!< ETH TIMESTAMP_CONTROL: TSENA Mask       */\r
+#define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos    1                                                       /*!< ETH TIMESTAMP_CONTROL: TSCFUPDT Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk    (0x01UL << ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos)          /*!< ETH TIMESTAMP_CONTROL: TSCFUPDT Mask    */\r
+#define ETH_TIMESTAMP_CONTROL_TSINIT_Pos      2                                                       /*!< ETH TIMESTAMP_CONTROL: TSINIT Position  */\r
+#define ETH_TIMESTAMP_CONTROL_TSINIT_Msk      (0x01UL << ETH_TIMESTAMP_CONTROL_TSINIT_Pos)            /*!< ETH TIMESTAMP_CONTROL: TSINIT Mask      */\r
+#define ETH_TIMESTAMP_CONTROL_TSUPDT_Pos      3                                                       /*!< ETH TIMESTAMP_CONTROL: TSUPDT Position  */\r
+#define ETH_TIMESTAMP_CONTROL_TSUPDT_Msk      (0x01UL << ETH_TIMESTAMP_CONTROL_TSUPDT_Pos)            /*!< ETH TIMESTAMP_CONTROL: TSUPDT Mask      */\r
+#define ETH_TIMESTAMP_CONTROL_TSTRIG_Pos      4                                                       /*!< ETH TIMESTAMP_CONTROL: TSTRIG Position  */\r
+#define ETH_TIMESTAMP_CONTROL_TSTRIG_Msk      (0x01UL << ETH_TIMESTAMP_CONTROL_TSTRIG_Pos)            /*!< ETH TIMESTAMP_CONTROL: TSTRIG Mask      */\r
+#define ETH_TIMESTAMP_CONTROL_TSADDREG_Pos    5                                                       /*!< ETH TIMESTAMP_CONTROL: TSADDREG Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSADDREG_Msk    (0x01UL << ETH_TIMESTAMP_CONTROL_TSADDREG_Pos)          /*!< ETH TIMESTAMP_CONTROL: TSADDREG Mask    */\r
+#define ETH_TIMESTAMP_CONTROL_Reserved_7_6_Pos 6                                                      /*!< ETH TIMESTAMP_CONTROL: Reserved_7_6 Position */\r
+#define ETH_TIMESTAMP_CONTROL_Reserved_7_6_Msk (0x03UL << ETH_TIMESTAMP_CONTROL_Reserved_7_6_Pos)     /*!< ETH TIMESTAMP_CONTROL: Reserved_7_6 Mask */\r
+#define ETH_TIMESTAMP_CONTROL_TSENALL_Pos     8                                                       /*!< ETH TIMESTAMP_CONTROL: TSENALL Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSENALL_Msk     (0x01UL << ETH_TIMESTAMP_CONTROL_TSENALL_Pos)           /*!< ETH TIMESTAMP_CONTROL: TSENALL Mask     */\r
+#define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos   9                                                       /*!< ETH TIMESTAMP_CONTROL: TSCTRLSSR Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSCTRLSSR Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos   10                                                      /*!< ETH TIMESTAMP_CONTROL: TSVER2ENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSVER2ENA Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPENA_Pos     11                                                      /*!< ETH TIMESTAMP_CONTROL: TSIPENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPENA_Msk     (0x01UL << ETH_TIMESTAMP_CONTROL_TSIPENA_Pos)           /*!< ETH TIMESTAMP_CONTROL: TSIPENA Mask     */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos   12                                                      /*!< ETH TIMESTAMP_CONTROL: TSIPV6ENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSIPV6ENA Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos   13                                                      /*!< ETH TIMESTAMP_CONTROL: TSIPV4ENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSIPV4ENA Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos   14                                                      /*!< ETH TIMESTAMP_CONTROL: TSEVNTENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSEVNTENA Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos   15                                                      /*!< ETH TIMESTAMP_CONTROL: TSMSTRENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSMSTRENA Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos  16                                                      /*!< ETH TIMESTAMP_CONTROL: SNAPTYPSEL Position */\r
+#define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Msk  (0x03UL << ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos)        /*!< ETH TIMESTAMP_CONTROL: SNAPTYPSEL Mask  */\r
+#define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos 18                                                      /*!< ETH TIMESTAMP_CONTROL: TSENMACADDR Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos)       /*!< ETH TIMESTAMP_CONTROL: TSENMACADDR Mask */\r
+#define ETH_TIMESTAMP_CONTROL_Reserved_23_19_Pos 19                                                   /*!< ETH TIMESTAMP_CONTROL: Reserved_23_19 Position */\r
+#define ETH_TIMESTAMP_CONTROL_Reserved_23_19_Msk (0x00001fffUL << ETH_TIMESTAMP_CONTROL_Reserved_23_19_Pos)/*!< ETH TIMESTAMP_CONTROL: Reserved_23_19 Mask */\r
+\r
+/* --------------------------  ETH_SUB_SECOND_INCREMENT  -------------------------- */\r
+#define ETH_SUB_SECOND_INCREMENT_SSINC_Pos    0                                                       /*!< ETH SUB_SECOND_INCREMENT: SSINC Position */\r
+#define ETH_SUB_SECOND_INCREMENT_SSINC_Msk    (0x000000ffUL << ETH_SUB_SECOND_INCREMENT_SSINC_Pos)    /*!< ETH SUB_SECOND_INCREMENT: SSINC Mask    */\r
+#define ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Pos 8                                                  /*!< ETH SUB_SECOND_INCREMENT: Reserved_31_8 Position */\r
+#define ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Msk (0x00ffffffUL << ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Pos)/*!< ETH SUB_SECOND_INCREMENT: Reserved_31_8 Mask */\r
+\r
+/* ---------------------------  ETH_SYSTEM_TIME_SECONDS  -------------------------- */\r
+#define ETH_SYSTEM_TIME_SECONDS_TSS_Pos       0                                                       /*!< ETH SYSTEM_TIME_SECONDS: TSS Position   */\r
+#define ETH_SYSTEM_TIME_SECONDS_TSS_Msk       (0xffffffffUL << ETH_SYSTEM_TIME_SECONDS_TSS_Pos)       /*!< ETH SYSTEM_TIME_SECONDS: TSS Mask       */\r
+\r
+/* -------------------------  ETH_SYSTEM_TIME_NANOSECONDS  ------------------------ */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos  0                                                       /*!< ETH SYSTEM_TIME_NANOSECONDS: TSSS Position */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Msk  (0x7fffffffUL << ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos)  /*!< ETH SYSTEM_TIME_NANOSECONDS: TSSS Mask  */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Pos 31                                                /*!< ETH SYSTEM_TIME_NANOSECONDS: Reserved_31 Position */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Msk (0x01UL << ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Pos)/*!< ETH SYSTEM_TIME_NANOSECONDS: Reserved_31 Mask */\r
+\r
+/* -----------------------  ETH_SYSTEM_TIME_SECONDS_UPDATE  ----------------------- */\r
+#define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos 0                                                      /*!< ETH SYSTEM_TIME_SECONDS_UPDATE: TSS Position */\r
+#define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Msk (0xffffffffUL << ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos)/*!< ETH SYSTEM_TIME_SECONDS_UPDATE: TSS Mask */\r
+\r
+/* ---------------------  ETH_SYSTEM_TIME_NANOSECONDS_UPDATE  --------------------- */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos 0                                                 /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: TSSS Position */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Msk (0x7fffffffUL << ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos)/*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: TSSS Mask */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos 31                                              /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: ADDSUB Position */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk (0x01UL << ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos)/*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: ADDSUB Mask */\r
+\r
+/* ----------------------------  ETH_TIMESTAMP_ADDEND  ---------------------------- */\r
+#define ETH_TIMESTAMP_ADDEND_TSAR_Pos         0                                                       /*!< ETH TIMESTAMP_ADDEND: TSAR Position     */\r
+#define ETH_TIMESTAMP_ADDEND_TSAR_Msk         (0xffffffffUL << ETH_TIMESTAMP_ADDEND_TSAR_Pos)         /*!< ETH TIMESTAMP_ADDEND: TSAR Mask         */\r
+\r
+/* ---------------------------  ETH_TARGET_TIME_SECONDS  -------------------------- */\r
+#define ETH_TARGET_TIME_SECONDS_TSTR_Pos      0                                                       /*!< ETH TARGET_TIME_SECONDS: TSTR Position  */\r
+#define ETH_TARGET_TIME_SECONDS_TSTR_Msk      (0xffffffffUL << ETH_TARGET_TIME_SECONDS_TSTR_Pos)      /*!< ETH TARGET_TIME_SECONDS: TSTR Mask      */\r
+\r
+/* -------------------------  ETH_TARGET_TIME_NANOSECONDS  ------------------------ */\r
+#define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos 0                                                       /*!< ETH TARGET_TIME_NANOSECONDS: TTSLO Position */\r
+#define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Msk (0x7fffffffUL << ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos) /*!< ETH TARGET_TIME_NANOSECONDS: TTSLO Mask */\r
+#define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos 31                                                   /*!< ETH TARGET_TIME_NANOSECONDS: TRGTBUSY Position */\r
+#define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Msk (0x01UL << ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos) /*!< ETH TARGET_TIME_NANOSECONDS: TRGTBUSY Mask */\r
+\r
+/* ---------------------  ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS  -------------------- */\r
+#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos 0                                               /*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: TSHWR Position */\r
+#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Msk (0x0000ffffUL << ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos)/*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: TSHWR Mask */\r
+#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Pos 16                                     /*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: Reserved_31_16 Position */\r
+#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Msk (0x0000ffffUL << ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Pos)/*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: Reserved_31_16 Mask */\r
+\r
+/* ----------------------------  ETH_TIMESTAMP_STATUS  ---------------------------- */\r
+#define ETH_TIMESTAMP_STATUS_TSSOVF_Pos       0                                                       /*!< ETH TIMESTAMP_STATUS: TSSOVF Position   */\r
+#define ETH_TIMESTAMP_STATUS_TSSOVF_Msk       (0x01UL << ETH_TIMESTAMP_STATUS_TSSOVF_Pos)             /*!< ETH TIMESTAMP_STATUS: TSSOVF Mask       */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT_Pos      1                                                       /*!< ETH TIMESTAMP_STATUS: TSTARGT Position  */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT_Msk      (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT_Pos)            /*!< ETH TIMESTAMP_STATUS: TSTARGT Mask      */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_2_Pos   2                                                       /*!< ETH TIMESTAMP_STATUS: Reserved_2 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_2_Msk   (0x01UL << ETH_TIMESTAMP_STATUS_Reserved_2_Pos)         /*!< ETH TIMESTAMP_STATUS: Reserved_2 Mask   */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos    3                                                       /*!< ETH TIMESTAMP_STATUS: TSTRGTERR Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR_Msk    (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos)          /*!< ETH TIMESTAMP_STATUS: TSTRGTERR Mask    */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT1_Pos     4                                                       /*!< ETH TIMESTAMP_STATUS: TSTARGT1 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT1_Msk     (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT1_Pos)           /*!< ETH TIMESTAMP_STATUS: TSTARGT1 Mask     */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos   5                                                       /*!< ETH TIMESTAMP_STATUS: TSTRGTERR1 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Msk   (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos)         /*!< ETH TIMESTAMP_STATUS: TSTRGTERR1 Mask   */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT2_Pos     6                                                       /*!< ETH TIMESTAMP_STATUS: TSTARGT2 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT2_Msk     (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT2_Pos)           /*!< ETH TIMESTAMP_STATUS: TSTARGT2 Mask     */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos   7                                                       /*!< ETH TIMESTAMP_STATUS: TSTRGTERR2 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Msk   (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos)         /*!< ETH TIMESTAMP_STATUS: TSTRGTERR2 Mask   */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT3_Pos     8                                                       /*!< ETH TIMESTAMP_STATUS: TSTARGT3 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT3_Msk     (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT3_Pos)           /*!< ETH TIMESTAMP_STATUS: TSTARGT3 Mask     */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos   9                                                       /*!< ETH TIMESTAMP_STATUS: TSTRGTERR3 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Msk   (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos)         /*!< ETH TIMESTAMP_STATUS: TSTRGTERR3 Mask   */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_15_10_Pos 10                                                    /*!< ETH TIMESTAMP_STATUS: Reserved_15_10 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_15_10_Msk (0x3fUL << ETH_TIMESTAMP_STATUS_Reserved_15_10_Pos)   /*!< ETH TIMESTAMP_STATUS: Reserved_15_10 Mask */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_19_16_Pos 16                                                    /*!< ETH TIMESTAMP_STATUS: Reserved_19_16 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_19_16_Msk (0x0fUL << ETH_TIMESTAMP_STATUS_Reserved_19_16_Pos)   /*!< ETH TIMESTAMP_STATUS: Reserved_19_16 Mask */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_23_20_Pos 20                                                    /*!< ETH TIMESTAMP_STATUS: Reserved_23_20 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_23_20_Msk (0x0fUL << ETH_TIMESTAMP_STATUS_Reserved_23_20_Pos)   /*!< ETH TIMESTAMP_STATUS: Reserved_23_20 Mask */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_24_Pos  24                                                      /*!< ETH TIMESTAMP_STATUS: Reserved_24 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_24_Msk  (0x01UL << ETH_TIMESTAMP_STATUS_Reserved_24_Pos)        /*!< ETH TIMESTAMP_STATUS: Reserved_24 Mask  */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_29_25_Pos 25                                                    /*!< ETH TIMESTAMP_STATUS: Reserved_29_25 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_29_25_Msk (0x1fUL << ETH_TIMESTAMP_STATUS_Reserved_29_25_Pos)   /*!< ETH TIMESTAMP_STATUS: Reserved_29_25 Mask */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_31_30_Pos 30                                                    /*!< ETH TIMESTAMP_STATUS: Reserved_31_30 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_31_30_Msk (0x03UL << ETH_TIMESTAMP_STATUS_Reserved_31_30_Pos)   /*!< ETH TIMESTAMP_STATUS: Reserved_31_30 Mask */\r
+\r
+/* -------------------------------  ETH_PPS_CONTROL  ------------------------------ */\r
+#define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos    0                                                       /*!< ETH PPS_CONTROL: PPSCTRL_PPSCMD Position */\r
+#define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Msk    (0x0fUL << ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos)          /*!< ETH PPS_CONTROL: PPSCTRL_PPSCMD Mask    */\r
+#define ETH_PPS_CONTROL_PPSEN0_Pos            4                                                       /*!< ETH PPS_CONTROL: PPSEN0 Position        */\r
+#define ETH_PPS_CONTROL_PPSEN0_Msk            (0x01UL << ETH_PPS_CONTROL_PPSEN0_Pos)                  /*!< ETH PPS_CONTROL: PPSEN0 Mask            */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL0_Pos       5                                                       /*!< ETH PPS_CONTROL: TRGTMODSEL0 Position   */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL0_Msk       (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL0_Pos)             /*!< ETH PPS_CONTROL: TRGTMODSEL0 Mask       */\r
+#define ETH_PPS_CONTROL_Reserved_7_Pos        7                                                       /*!< ETH PPS_CONTROL: Reserved_7 Position    */\r
+#define ETH_PPS_CONTROL_Reserved_7_Msk        (0x01UL << ETH_PPS_CONTROL_Reserved_7_Pos)              /*!< ETH PPS_CONTROL: Reserved_7 Mask        */\r
+#define ETH_PPS_CONTROL_PPSCMD1_Pos           8                                                       /*!< ETH PPS_CONTROL: PPSCMD1 Position       */\r
+#define ETH_PPS_CONTROL_PPSCMD1_Msk           (0x07UL << ETH_PPS_CONTROL_PPSCMD1_Pos)                 /*!< ETH PPS_CONTROL: PPSCMD1 Mask           */\r
+#define ETH_PPS_CONTROL_Reserved_12_11_Pos    11                                                      /*!< ETH PPS_CONTROL: Reserved_12_11 Position */\r
+#define ETH_PPS_CONTROL_Reserved_12_11_Msk    (0x03UL << ETH_PPS_CONTROL_Reserved_12_11_Pos)          /*!< ETH PPS_CONTROL: Reserved_12_11 Mask    */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL1_Pos       13                                                      /*!< ETH PPS_CONTROL: TRGTMODSEL1 Position   */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL1_Msk       (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL1_Pos)             /*!< ETH PPS_CONTROL: TRGTMODSEL1 Mask       */\r
+#define ETH_PPS_CONTROL_Reserved_15_Pos       15                                                      /*!< ETH PPS_CONTROL: Reserved_15 Position   */\r
+#define ETH_PPS_CONTROL_Reserved_15_Msk       (0x01UL << ETH_PPS_CONTROL_Reserved_15_Pos)             /*!< ETH PPS_CONTROL: Reserved_15 Mask       */\r
+#define ETH_PPS_CONTROL_PPSCMD2_Pos           16                                                      /*!< ETH PPS_CONTROL: PPSCMD2 Position       */\r
+#define ETH_PPS_CONTROL_PPSCMD2_Msk           (0x07UL << ETH_PPS_CONTROL_PPSCMD2_Pos)                 /*!< ETH PPS_CONTROL: PPSCMD2 Mask           */\r
+#define ETH_PPS_CONTROL_Reserved_20_19_Pos    19                                                      /*!< ETH PPS_CONTROL: Reserved_20_19 Position */\r
+#define ETH_PPS_CONTROL_Reserved_20_19_Msk    (0x03UL << ETH_PPS_CONTROL_Reserved_20_19_Pos)          /*!< ETH PPS_CONTROL: Reserved_20_19 Mask    */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL2_Pos       21                                                      /*!< ETH PPS_CONTROL: TRGTMODSEL2 Position   */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL2_Msk       (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL2_Pos)             /*!< ETH PPS_CONTROL: TRGTMODSEL2 Mask       */\r
+#define ETH_PPS_CONTROL_Reserved_23_Pos       23                                                      /*!< ETH PPS_CONTROL: Reserved_23 Position   */\r
+#define ETH_PPS_CONTROL_Reserved_23_Msk       (0x01UL << ETH_PPS_CONTROL_Reserved_23_Pos)             /*!< ETH PPS_CONTROL: Reserved_23 Mask       */\r
+#define ETH_PPS_CONTROL_PPSCMD3_Pos           24                                                      /*!< ETH PPS_CONTROL: PPSCMD3 Position       */\r
+#define ETH_PPS_CONTROL_PPSCMD3_Msk           (0x07UL << ETH_PPS_CONTROL_PPSCMD3_Pos)                 /*!< ETH PPS_CONTROL: PPSCMD3 Mask           */\r
+#define ETH_PPS_CONTROL_Reserved_28_27_Pos    27                                                      /*!< ETH PPS_CONTROL: Reserved_28_27 Position */\r
+#define ETH_PPS_CONTROL_Reserved_28_27_Msk    (0x03UL << ETH_PPS_CONTROL_Reserved_28_27_Pos)          /*!< ETH PPS_CONTROL: Reserved_28_27 Mask    */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL3_Pos       29                                                      /*!< ETH PPS_CONTROL: TRGTMODSEL3 Position   */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL3_Msk       (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL3_Pos)             /*!< ETH PPS_CONTROL: TRGTMODSEL3 Mask       */\r
+#define ETH_PPS_CONTROL_Reserved_31_Pos       31                                                      /*!< ETH PPS_CONTROL: Reserved_31 Position   */\r
+#define ETH_PPS_CONTROL_Reserved_31_Msk       (0x01UL << ETH_PPS_CONTROL_Reserved_31_Pos)             /*!< ETH PPS_CONTROL: Reserved_31 Mask       */\r
+\r
+/* --------------------------------  ETH_BUS_MODE  -------------------------------- */\r
+#define ETH_BUS_MODE_SWR_Pos                  0                                                       /*!< ETH BUS_MODE: SWR Position              */\r
+#define ETH_BUS_MODE_SWR_Msk                  (0x01UL << ETH_BUS_MODE_SWR_Pos)                        /*!< ETH BUS_MODE: SWR Mask                  */\r
+#define ETH_BUS_MODE_DA_Pos                   1                                                       /*!< ETH BUS_MODE: DA Position               */\r
+#define ETH_BUS_MODE_DA_Msk                   (0x01UL << ETH_BUS_MODE_DA_Pos)                         /*!< ETH BUS_MODE: DA Mask                   */\r
+#define ETH_BUS_MODE_DSL_Pos                  2                                                       /*!< ETH BUS_MODE: DSL Position              */\r
+#define ETH_BUS_MODE_DSL_Msk                  (0x1fUL << ETH_BUS_MODE_DSL_Pos)                        /*!< ETH BUS_MODE: DSL Mask                  */\r
+#define ETH_BUS_MODE_Reserved_7_Pos           7                                                       /*!< ETH BUS_MODE: Reserved_7 Position       */\r
+#define ETH_BUS_MODE_Reserved_7_Msk           (0x01UL << ETH_BUS_MODE_Reserved_7_Pos)                 /*!< ETH BUS_MODE: Reserved_7 Mask           */\r
+#define ETH_BUS_MODE_PBL_Pos                  8                                                       /*!< ETH BUS_MODE: PBL Position              */\r
+#define ETH_BUS_MODE_PBL_Msk                  (0x3fUL << ETH_BUS_MODE_PBL_Pos)                        /*!< ETH BUS_MODE: PBL Mask                  */\r
+#define ETH_BUS_MODE_PR_Pos                   14                                                      /*!< ETH BUS_MODE: PR Position               */\r
+#define ETH_BUS_MODE_PR_Msk                   (0x03UL << ETH_BUS_MODE_PR_Pos)                         /*!< ETH BUS_MODE: PR Mask                   */\r
+#define ETH_BUS_MODE_FB_Pos                   16                                                      /*!< ETH BUS_MODE: FB Position               */\r
+#define ETH_BUS_MODE_FB_Msk                   (0x01UL << ETH_BUS_MODE_FB_Pos)                         /*!< ETH BUS_MODE: FB Mask                   */\r
+#define ETH_BUS_MODE_RPBL_Pos                 17                                                      /*!< ETH BUS_MODE: RPBL Position             */\r
+#define ETH_BUS_MODE_RPBL_Msk                 (0x3fUL << ETH_BUS_MODE_RPBL_Pos)                       /*!< ETH BUS_MODE: RPBL Mask                 */\r
+#define ETH_BUS_MODE_USP_Pos                  23                                                      /*!< ETH BUS_MODE: USP Position              */\r
+#define ETH_BUS_MODE_USP_Msk                  (0x01UL << ETH_BUS_MODE_USP_Pos)                        /*!< ETH BUS_MODE: USP Mask                  */\r
+#define ETH_BUS_MODE_EIGHTxPBL_Pos            24                                                      /*!< ETH BUS_MODE: EIGHTxPBL Position        */\r
+#define ETH_BUS_MODE_EIGHTxPBL_Msk            (0x01UL << ETH_BUS_MODE_EIGHTxPBL_Pos)                  /*!< ETH BUS_MODE: EIGHTxPBL Mask            */\r
+#define ETH_BUS_MODE_AAL_Pos                  25                                                      /*!< ETH BUS_MODE: AAL Position              */\r
+#define ETH_BUS_MODE_AAL_Msk                  (0x01UL << ETH_BUS_MODE_AAL_Pos)                        /*!< ETH BUS_MODE: AAL Mask                  */\r
+#define ETH_BUS_MODE_MB_Pos                   26                                                      /*!< ETH BUS_MODE: MB Position               */\r
+#define ETH_BUS_MODE_MB_Msk                   (0x01UL << ETH_BUS_MODE_MB_Pos)                         /*!< ETH BUS_MODE: MB Mask                   */\r
+#define ETH_BUS_MODE_TXPR_Pos                 27                                                      /*!< ETH BUS_MODE: TXPR Position             */\r
+#define ETH_BUS_MODE_TXPR_Msk                 (0x01UL << ETH_BUS_MODE_TXPR_Pos)                       /*!< ETH BUS_MODE: TXPR Mask                 */\r
+#define ETH_BUS_MODE_PRWG_Pos                 28                                                      /*!< ETH BUS_MODE: PRWG Position             */\r
+#define ETH_BUS_MODE_PRWG_Msk                 (0x03UL << ETH_BUS_MODE_PRWG_Pos)                       /*!< ETH BUS_MODE: PRWG Mask                 */\r
+#define ETH_BUS_MODE_Reserved_31_30_Pos       30                                                      /*!< ETH BUS_MODE: Reserved_31_30 Position   */\r
+#define ETH_BUS_MODE_Reserved_31_30_Msk       (0x03UL << ETH_BUS_MODE_Reserved_31_30_Pos)             /*!< ETH BUS_MODE: Reserved_31_30 Mask       */\r
+\r
+/* --------------------------  ETH_TRANSMIT_POLL_DEMAND  -------------------------- */\r
+#define ETH_TRANSMIT_POLL_DEMAND_TPD_Pos      0                                                       /*!< ETH TRANSMIT_POLL_DEMAND: TPD Position  */\r
+#define ETH_TRANSMIT_POLL_DEMAND_TPD_Msk      (0xffffffffUL << ETH_TRANSMIT_POLL_DEMAND_TPD_Pos)      /*!< ETH TRANSMIT_POLL_DEMAND: TPD Mask      */\r
+\r
+/* ---------------------------  ETH_RECEIVE_POLL_DEMAND  -------------------------- */\r
+#define ETH_RECEIVE_POLL_DEMAND_RPD_Pos       0                                                       /*!< ETH RECEIVE_POLL_DEMAND: RPD Position   */\r
+#define ETH_RECEIVE_POLL_DEMAND_RPD_Msk       (0xffffffffUL << ETH_RECEIVE_POLL_DEMAND_RPD_Pos)       /*!< ETH RECEIVE_POLL_DEMAND: RPD Mask       */\r
+\r
+/* ---------------------  ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS  -------------------- */\r
+#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos 0                                        /*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Position */\r
+#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Msk (0x03UL << ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos)/*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Mask */\r
+#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos 2                                        /*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: RDESLA_32bit Position */\r
+#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Msk (0x3fffffffUL << ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos)/*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: RDESLA_32bit Mask */\r
+\r
+/* --------------------  ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS  -------------------- */\r
+#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos 0                                       /*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Position */\r
+#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Msk (0x03UL << ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos)/*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Mask */\r
+#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos 2                                       /*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: TDESLA_32bit Position */\r
+#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Msk (0x3fffffffUL << ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos)/*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: TDESLA_32bit Mask */\r
+\r
+/* ---------------------------------  ETH_STATUS  --------------------------------- */\r
+#define ETH_STATUS_TI_Pos                     0                                                       /*!< ETH STATUS: TI Position                 */\r
+#define ETH_STATUS_TI_Msk                     (0x01UL << ETH_STATUS_TI_Pos)                           /*!< ETH STATUS: TI Mask                     */\r
+#define ETH_STATUS_TPS_Pos                    1                                                       /*!< ETH STATUS: TPS Position                */\r
+#define ETH_STATUS_TPS_Msk                    (0x01UL << ETH_STATUS_TPS_Pos)                          /*!< ETH STATUS: TPS Mask                    */\r
+#define ETH_STATUS_TU_Pos                     2                                                       /*!< ETH STATUS: TU Position                 */\r
+#define ETH_STATUS_TU_Msk                     (0x01UL << ETH_STATUS_TU_Pos)                           /*!< ETH STATUS: TU Mask                     */\r
+#define ETH_STATUS_TJT_Pos                    3                                                       /*!< ETH STATUS: TJT Position                */\r
+#define ETH_STATUS_TJT_Msk                    (0x01UL << ETH_STATUS_TJT_Pos)                          /*!< ETH STATUS: TJT Mask                    */\r
+#define ETH_STATUS_OVF_Pos                    4                                                       /*!< ETH STATUS: OVF Position                */\r
+#define ETH_STATUS_OVF_Msk                    (0x01UL << ETH_STATUS_OVF_Pos)                          /*!< ETH STATUS: OVF Mask                    */\r
+#define ETH_STATUS_UNF_Pos                    5                                                       /*!< ETH STATUS: UNF Position                */\r
+#define ETH_STATUS_UNF_Msk                    (0x01UL << ETH_STATUS_UNF_Pos)                          /*!< ETH STATUS: UNF Mask                    */\r
+#define ETH_STATUS_RI_Pos                     6                                                       /*!< ETH STATUS: RI Position                 */\r
+#define ETH_STATUS_RI_Msk                     (0x01UL << ETH_STATUS_RI_Pos)                           /*!< ETH STATUS: RI Mask                     */\r
+#define ETH_STATUS_RU_Pos                     7                                                       /*!< ETH STATUS: RU Position                 */\r
+#define ETH_STATUS_RU_Msk                     (0x01UL << ETH_STATUS_RU_Pos)                           /*!< ETH STATUS: RU Mask                     */\r
+#define ETH_STATUS_RPS_Pos                    8                                                       /*!< ETH STATUS: RPS Position                */\r
+#define ETH_STATUS_RPS_Msk                    (0x01UL << ETH_STATUS_RPS_Pos)                          /*!< ETH STATUS: RPS Mask                    */\r
+#define ETH_STATUS_RWT_Pos                    9                                                       /*!< ETH STATUS: RWT Position                */\r
+#define ETH_STATUS_RWT_Msk                    (0x01UL << ETH_STATUS_RWT_Pos)                          /*!< ETH STATUS: RWT Mask                    */\r
+#define ETH_STATUS_ETI_Pos                    10                                                      /*!< ETH STATUS: ETI Position                */\r
+#define ETH_STATUS_ETI_Msk                    (0x01UL << ETH_STATUS_ETI_Pos)                          /*!< ETH STATUS: ETI Mask                    */\r
+#define ETH_STATUS_Reserved_12_11_Pos         11                                                      /*!< ETH STATUS: Reserved_12_11 Position     */\r
+#define ETH_STATUS_Reserved_12_11_Msk         (0x03UL << ETH_STATUS_Reserved_12_11_Pos)               /*!< ETH STATUS: Reserved_12_11 Mask         */\r
+#define ETH_STATUS_FBI_Pos                    13                                                      /*!< ETH STATUS: FBI Position                */\r
+#define ETH_STATUS_FBI_Msk                    (0x01UL << ETH_STATUS_FBI_Pos)                          /*!< ETH STATUS: FBI Mask                    */\r
+#define ETH_STATUS_ERI_Pos                    14                                                      /*!< ETH STATUS: ERI Position                */\r
+#define ETH_STATUS_ERI_Msk                    (0x01UL << ETH_STATUS_ERI_Pos)                          /*!< ETH STATUS: ERI Mask                    */\r
+#define ETH_STATUS_AIS_Pos                    15                                                      /*!< ETH STATUS: AIS Position                */\r
+#define ETH_STATUS_AIS_Msk                    (0x01UL << ETH_STATUS_AIS_Pos)                          /*!< ETH STATUS: AIS Mask                    */\r
+#define ETH_STATUS_NIS_Pos                    16                                                      /*!< ETH STATUS: NIS Position                */\r
+#define ETH_STATUS_NIS_Msk                    (0x01UL << ETH_STATUS_NIS_Pos)                          /*!< ETH STATUS: NIS Mask                    */\r
+#define ETH_STATUS_RS_Pos                     17                                                      /*!< ETH STATUS: RS Position                 */\r
+#define ETH_STATUS_RS_Msk                     (0x07UL << ETH_STATUS_RS_Pos)                           /*!< ETH STATUS: RS Mask                     */\r
+#define ETH_STATUS_TS_Pos                     20                                                      /*!< ETH STATUS: TS Position                 */\r
+#define ETH_STATUS_TS_Msk                     (0x07UL << ETH_STATUS_TS_Pos)                           /*!< ETH STATUS: TS Mask                     */\r
+#define ETH_STATUS_EB_Pos                     23                                                      /*!< ETH STATUS: EB Position                 */\r
+#define ETH_STATUS_EB_Msk                     (0x07UL << ETH_STATUS_EB_Pos)                           /*!< ETH STATUS: EB Mask                     */\r
+#define ETH_STATUS_Reserved_26_Pos            26                                                      /*!< ETH STATUS: Reserved_26 Position        */\r
+#define ETH_STATUS_Reserved_26_Msk            (0x01UL << ETH_STATUS_Reserved_26_Pos)                  /*!< ETH STATUS: Reserved_26 Mask            */\r
+#define ETH_STATUS_EMI_Pos                    27                                                      /*!< ETH STATUS: EMI Position                */\r
+#define ETH_STATUS_EMI_Msk                    (0x01UL << ETH_STATUS_EMI_Pos)                          /*!< ETH STATUS: EMI Mask                    */\r
+#define ETH_STATUS_EPI_Pos                    28                                                      /*!< ETH STATUS: EPI Position                */\r
+#define ETH_STATUS_EPI_Msk                    (0x01UL << ETH_STATUS_EPI_Pos)                          /*!< ETH STATUS: EPI Mask                    */\r
+#define ETH_STATUS_TTI_Pos                    29                                                      /*!< ETH STATUS: TTI Position                */\r
+#define ETH_STATUS_TTI_Msk                    (0x01UL << ETH_STATUS_TTI_Pos)                          /*!< ETH STATUS: TTI Mask                    */\r
+#define ETH_STATUS_Reserved_30_Pos            30                                                      /*!< ETH STATUS: Reserved_30 Position        */\r
+#define ETH_STATUS_Reserved_30_Msk            (0x01UL << ETH_STATUS_Reserved_30_Pos)                  /*!< ETH STATUS: Reserved_30 Mask            */\r
+#define ETH_STATUS_Reserved_31_Pos            31                                                      /*!< ETH STATUS: Reserved_31 Position        */\r
+#define ETH_STATUS_Reserved_31_Msk            (0x01UL << ETH_STATUS_Reserved_31_Pos)                  /*!< ETH STATUS: Reserved_31 Mask            */\r
+\r
+/* -----------------------------  ETH_OPERATION_MODE  ----------------------------- */\r
+#define ETH_OPERATION_MODE_Reserved_0_Pos     0                                                       /*!< ETH OPERATION_MODE: Reserved_0 Position */\r
+#define ETH_OPERATION_MODE_Reserved_0_Msk     (0x01UL << ETH_OPERATION_MODE_Reserved_0_Pos)           /*!< ETH OPERATION_MODE: Reserved_0 Mask     */\r
+#define ETH_OPERATION_MODE_SR_Pos             1                                                       /*!< ETH OPERATION_MODE: SR Position         */\r
+#define ETH_OPERATION_MODE_SR_Msk             (0x01UL << ETH_OPERATION_MODE_SR_Pos)                   /*!< ETH OPERATION_MODE: SR Mask             */\r
+#define ETH_OPERATION_MODE_OSF_Pos            2                                                       /*!< ETH OPERATION_MODE: OSF Position        */\r
+#define ETH_OPERATION_MODE_OSF_Msk            (0x01UL << ETH_OPERATION_MODE_OSF_Pos)                  /*!< ETH OPERATION_MODE: OSF Mask            */\r
+#define ETH_OPERATION_MODE_RTC_Pos            3                                                       /*!< ETH OPERATION_MODE: RTC Position        */\r
+#define ETH_OPERATION_MODE_RTC_Msk            (0x03UL << ETH_OPERATION_MODE_RTC_Pos)                  /*!< ETH OPERATION_MODE: RTC Mask            */\r
+#define ETH_OPERATION_MODE_Reserved_5_Pos     5                                                       /*!< ETH OPERATION_MODE: Reserved_5 Position */\r
+#define ETH_OPERATION_MODE_Reserved_5_Msk     (0x01UL << ETH_OPERATION_MODE_Reserved_5_Pos)           /*!< ETH OPERATION_MODE: Reserved_5 Mask     */\r
+#define ETH_OPERATION_MODE_FUF_Pos            6                                                       /*!< ETH OPERATION_MODE: FUF Position        */\r
+#define ETH_OPERATION_MODE_FUF_Msk            (0x01UL << ETH_OPERATION_MODE_FUF_Pos)                  /*!< ETH OPERATION_MODE: FUF Mask            */\r
+#define ETH_OPERATION_MODE_FEF_Pos            7                                                       /*!< ETH OPERATION_MODE: FEF Position        */\r
+#define ETH_OPERATION_MODE_FEF_Msk            (0x01UL << ETH_OPERATION_MODE_FEF_Pos)                  /*!< ETH OPERATION_MODE: FEF Mask            */\r
+#define ETH_OPERATION_MODE_Reserved_12_8_Pos  8                                                       /*!< ETH OPERATION_MODE: Reserved_12_8 Position */\r
+#define ETH_OPERATION_MODE_Reserved_12_8_Msk  (0x1fUL << ETH_OPERATION_MODE_Reserved_12_8_Pos)        /*!< ETH OPERATION_MODE: Reserved_12_8 Mask  */\r
+#define ETH_OPERATION_MODE_ST_Pos             13                                                      /*!< ETH OPERATION_MODE: ST Position         */\r
+#define ETH_OPERATION_MODE_ST_Msk             (0x01UL << ETH_OPERATION_MODE_ST_Pos)                   /*!< ETH OPERATION_MODE: ST Mask             */\r
+#define ETH_OPERATION_MODE_TTC_Pos            14                                                      /*!< ETH OPERATION_MODE: TTC Position        */\r
+#define ETH_OPERATION_MODE_TTC_Msk            (0x07UL << ETH_OPERATION_MODE_TTC_Pos)                  /*!< ETH OPERATION_MODE: TTC Mask            */\r
+#define ETH_OPERATION_MODE_Reserved_19_17_Pos 17                                                      /*!< ETH OPERATION_MODE: Reserved_19_17 Position */\r
+#define ETH_OPERATION_MODE_Reserved_19_17_Msk (0x07UL << ETH_OPERATION_MODE_Reserved_19_17_Pos)       /*!< ETH OPERATION_MODE: Reserved_19_17 Mask */\r
+#define ETH_OPERATION_MODE_FTF_Pos            20                                                      /*!< ETH OPERATION_MODE: FTF Position        */\r
+#define ETH_OPERATION_MODE_FTF_Msk            (0x01UL << ETH_OPERATION_MODE_FTF_Pos)                  /*!< ETH OPERATION_MODE: FTF Mask            */\r
+#define ETH_OPERATION_MODE_TSF_Pos            21                                                      /*!< ETH OPERATION_MODE: TSF Position        */\r
+#define ETH_OPERATION_MODE_TSF_Msk            (0x01UL << ETH_OPERATION_MODE_TSF_Pos)                  /*!< ETH OPERATION_MODE: TSF Mask            */\r
+#define ETH_OPERATION_MODE_Reserved_23_22_Pos 22                                                      /*!< ETH OPERATION_MODE: Reserved_23_22 Position */\r
+#define ETH_OPERATION_MODE_Reserved_23_22_Msk (0x03UL << ETH_OPERATION_MODE_Reserved_23_22_Pos)       /*!< ETH OPERATION_MODE: Reserved_23_22 Mask */\r
+#define ETH_OPERATION_MODE_DFF_Pos            24                                                      /*!< ETH OPERATION_MODE: DFF Position        */\r
+#define ETH_OPERATION_MODE_DFF_Msk            (0x01UL << ETH_OPERATION_MODE_DFF_Pos)                  /*!< ETH OPERATION_MODE: DFF Mask            */\r
+#define ETH_OPERATION_MODE_RSF_Pos            25                                                      /*!< ETH OPERATION_MODE: RSF Position        */\r
+#define ETH_OPERATION_MODE_RSF_Msk            (0x01UL << ETH_OPERATION_MODE_RSF_Pos)                  /*!< ETH OPERATION_MODE: RSF Mask            */\r
+#define ETH_OPERATION_MODE_DT_Pos             26                                                      /*!< ETH OPERATION_MODE: DT Position         */\r
+#define ETH_OPERATION_MODE_DT_Msk             (0x01UL << ETH_OPERATION_MODE_DT_Pos)                   /*!< ETH OPERATION_MODE: DT Mask             */\r
+#define ETH_OPERATION_MODE_Reserved_31_27_Pos 27                                                      /*!< ETH OPERATION_MODE: Reserved_31_27 Position */\r
+#define ETH_OPERATION_MODE_Reserved_31_27_Msk (0x1fUL << ETH_OPERATION_MODE_Reserved_31_27_Pos)       /*!< ETH OPERATION_MODE: Reserved_31_27 Mask */\r
+\r
+/* ----------------------------  ETH_INTERRUPT_ENABLE  ---------------------------- */\r
+#define ETH_INTERRUPT_ENABLE_TIE_Pos          0                                                       /*!< ETH INTERRUPT_ENABLE: TIE Position      */\r
+#define ETH_INTERRUPT_ENABLE_TIE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_TIE_Pos)                /*!< ETH INTERRUPT_ENABLE: TIE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_TSE_Pos          1                                                       /*!< ETH INTERRUPT_ENABLE: TSE Position      */\r
+#define ETH_INTERRUPT_ENABLE_TSE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_TSE_Pos)                /*!< ETH INTERRUPT_ENABLE: TSE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_TUE_Pos          2                                                       /*!< ETH INTERRUPT_ENABLE: TUE Position      */\r
+#define ETH_INTERRUPT_ENABLE_TUE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_TUE_Pos)                /*!< ETH INTERRUPT_ENABLE: TUE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_TJE_Pos          3                                                       /*!< ETH INTERRUPT_ENABLE: TJE Position      */\r
+#define ETH_INTERRUPT_ENABLE_TJE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_TJE_Pos)                /*!< ETH INTERRUPT_ENABLE: TJE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_OVE_Pos          4                                                       /*!< ETH INTERRUPT_ENABLE: OVE Position      */\r
+#define ETH_INTERRUPT_ENABLE_OVE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_OVE_Pos)                /*!< ETH INTERRUPT_ENABLE: OVE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_UNE_Pos          5                                                       /*!< ETH INTERRUPT_ENABLE: UNE Position      */\r
+#define ETH_INTERRUPT_ENABLE_UNE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_UNE_Pos)                /*!< ETH INTERRUPT_ENABLE: UNE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_RIE_Pos          6                                                       /*!< ETH INTERRUPT_ENABLE: RIE Position      */\r
+#define ETH_INTERRUPT_ENABLE_RIE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_RIE_Pos)                /*!< ETH INTERRUPT_ENABLE: RIE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_RUE_Pos          7                                                       /*!< ETH INTERRUPT_ENABLE: RUE Position      */\r
+#define ETH_INTERRUPT_ENABLE_RUE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_RUE_Pos)                /*!< ETH INTERRUPT_ENABLE: RUE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_RSE_Pos          8                                                       /*!< ETH INTERRUPT_ENABLE: RSE Position      */\r
+#define ETH_INTERRUPT_ENABLE_RSE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_RSE_Pos)                /*!< ETH INTERRUPT_ENABLE: RSE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_RWE_Pos          9                                                       /*!< ETH INTERRUPT_ENABLE: RWE Position      */\r
+#define ETH_INTERRUPT_ENABLE_RWE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_RWE_Pos)                /*!< ETH INTERRUPT_ENABLE: RWE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_ETE_Pos          10                                                      /*!< ETH INTERRUPT_ENABLE: ETE Position      */\r
+#define ETH_INTERRUPT_ENABLE_ETE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_ETE_Pos)                /*!< ETH INTERRUPT_ENABLE: ETE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_Reserved_12_11_Pos 11                                                    /*!< ETH INTERRUPT_ENABLE: Reserved_12_11 Position */\r
+#define ETH_INTERRUPT_ENABLE_Reserved_12_11_Msk (0x03UL << ETH_INTERRUPT_ENABLE_Reserved_12_11_Pos)   /*!< ETH INTERRUPT_ENABLE: Reserved_12_11 Mask */\r
+#define ETH_INTERRUPT_ENABLE_FBE_Pos          13                                                      /*!< ETH INTERRUPT_ENABLE: FBE Position      */\r
+#define ETH_INTERRUPT_ENABLE_FBE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_FBE_Pos)                /*!< ETH INTERRUPT_ENABLE: FBE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_ERE_Pos          14                                                      /*!< ETH INTERRUPT_ENABLE: ERE Position      */\r
+#define ETH_INTERRUPT_ENABLE_ERE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_ERE_Pos)                /*!< ETH INTERRUPT_ENABLE: ERE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_AIE_Pos          15                                                      /*!< ETH INTERRUPT_ENABLE: AIE Position      */\r
+#define ETH_INTERRUPT_ENABLE_AIE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_AIE_Pos)                /*!< ETH INTERRUPT_ENABLE: AIE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_NIE_Pos          16                                                      /*!< ETH INTERRUPT_ENABLE: NIE Position      */\r
+#define ETH_INTERRUPT_ENABLE_NIE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_NIE_Pos)                /*!< ETH INTERRUPT_ENABLE: NIE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_Reserved_31_17_Pos 17                                                    /*!< ETH INTERRUPT_ENABLE: Reserved_31_17 Position */\r
+#define ETH_INTERRUPT_ENABLE_Reserved_31_17_Msk (0x00007fffUL << ETH_INTERRUPT_ENABLE_Reserved_31_17_Pos)/*!< ETH INTERRUPT_ENABLE: Reserved_31_17 Mask */\r
+\r
+/* ----------------  ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER  ---------------- */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos 0                                  /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISFRMCNT Position */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Msk (0x0000ffffUL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISFRMCNT Mask */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos 16                                 /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISCNTOVF Position */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Msk (0x01UL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISCNTOVF Mask */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos 17                                 /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFFRMCNT Position */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Msk (0x000007ffUL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFFRMCNT Mask */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos 28                                 /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFCNTOVF Position */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Msk (0x01UL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFCNTOVF Mask */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Pos 29                            /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: Reserved_31_29\r
+                                                         Position                                                                                  */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Msk (0x07UL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: Reserved_31_29\r
+                                                         Mask                                                                                      */\r
+\r
+/* --------------------  ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER  -------------------- */\r
+#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos 0                                               /*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: RIWT Position */\r
+#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Msk (0x000000ffUL << ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos)/*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: RIWT Mask */\r
+#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Pos 8                                      /*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: Reserved_31_8 Position */\r
+#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Msk (0x00ffffffUL << ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Pos)/*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: Reserved_31_8 Mask */\r
+\r
+/* -------------------------------  ETH_AHB_STATUS  ------------------------------- */\r
+#define ETH_AHB_STATUS_AHBMS_Pos              0                                                       /*!< ETH AHB_STATUS: AHBMS Position          */\r
+#define ETH_AHB_STATUS_AHBMS_Msk              (0x01UL << ETH_AHB_STATUS_AHBMS_Pos)                    /*!< ETH AHB_STATUS: AHBMS Mask              */\r
+#define ETH_AHB_STATUS_Reserved_1_Pos         1                                                       /*!< ETH AHB_STATUS: Reserved_1 Position     */\r
+#define ETH_AHB_STATUS_Reserved_1_Msk         (0x01UL << ETH_AHB_STATUS_Reserved_1_Pos)               /*!< ETH AHB_STATUS: Reserved_1 Mask         */\r
+#define ETH_AHB_STATUS_Reserved_31_2_Pos      2                                                       /*!< ETH AHB_STATUS: Reserved_31_2 Position  */\r
+#define ETH_AHB_STATUS_Reserved_31_2_Msk      (0x3fffffffUL << ETH_AHB_STATUS_Reserved_31_2_Pos)      /*!< ETH AHB_STATUS: Reserved_31_2 Mask      */\r
+\r
+/* --------------------  ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR  -------------------- */\r
+#define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos 0                                        /*!< ETH CURRENT_HOST_TRANSMIT_DESCRIPTOR: CURTDESAPTR Position */\r
+#define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos)/*!< ETH CURRENT_HOST_TRANSMIT_DESCRIPTOR: CURTDESAPTR Mask */\r
+\r
+/* ---------------------  ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR  -------------------- */\r
+#define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos 0                                         /*!< ETH CURRENT_HOST_RECEIVE_DESCRIPTOR: CURRDESAPTR Position */\r
+#define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos)/*!< ETH CURRENT_HOST_RECEIVE_DESCRIPTOR: CURRDESAPTR Mask */\r
+\r
+/* ------------------  ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS  ------------------ */\r
+#define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos 0                                    /*!< ETH CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS: CURTBUFAPTR Position */\r
+#define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos)/*!< ETH CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS: CURTBUFAPTR Mask */\r
+\r
+/* -------------------  ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS  ------------------ */\r
+#define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos 0                                     /*!< ETH CURRENT_HOST_RECEIVE_BUFFER_ADDRESS: CURRBUFAPTR Position */\r
+#define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos)/*!< ETH CURRENT_HOST_RECEIVE_BUFFER_ADDRESS: CURRBUFAPTR Mask */\r
+\r
+/* -------------------------------  ETH_HW_FEATURE  ------------------------------- */\r
+#define ETH_HW_FEATURE_MIISEL_Pos             0                                                       /*!< ETH HW_FEATURE: MIISEL Position         */\r
+#define ETH_HW_FEATURE_MIISEL_Msk             (0x01UL << ETH_HW_FEATURE_MIISEL_Pos)                   /*!< ETH HW_FEATURE: MIISEL Mask             */\r
+#define ETH_HW_FEATURE_GMIISEL_Pos            1                                                       /*!< ETH HW_FEATURE: GMIISEL Position        */\r
+#define ETH_HW_FEATURE_GMIISEL_Msk            (0x01UL << ETH_HW_FEATURE_GMIISEL_Pos)                  /*!< ETH HW_FEATURE: GMIISEL Mask            */\r
+#define ETH_HW_FEATURE_HDSEL_Pos              2                                                       /*!< ETH HW_FEATURE: HDSEL Position          */\r
+#define ETH_HW_FEATURE_HDSEL_Msk              (0x01UL << ETH_HW_FEATURE_HDSEL_Pos)                    /*!< ETH HW_FEATURE: HDSEL Mask              */\r
+#define ETH_HW_FEATURE_EXTHASHEN_Pos          3                                                       /*!< ETH HW_FEATURE: EXTHASHEN Position      */\r
+#define ETH_HW_FEATURE_EXTHASHEN_Msk          (0x01UL << ETH_HW_FEATURE_EXTHASHEN_Pos)                /*!< ETH HW_FEATURE: EXTHASHEN Mask          */\r
+#define ETH_HW_FEATURE_HASHSEL_Pos            4                                                       /*!< ETH HW_FEATURE: HASHSEL Position        */\r
+#define ETH_HW_FEATURE_HASHSEL_Msk            (0x01UL << ETH_HW_FEATURE_HASHSEL_Pos)                  /*!< ETH HW_FEATURE: HASHSEL Mask            */\r
+#define ETH_HW_FEATURE_ADDMACADRSEL_Pos       5                                                       /*!< ETH HW_FEATURE: ADDMACADRSEL Position   */\r
+#define ETH_HW_FEATURE_ADDMACADRSEL_Msk       (0x01UL << ETH_HW_FEATURE_ADDMACADRSEL_Pos)             /*!< ETH HW_FEATURE: ADDMACADRSEL Mask       */\r
+#define ETH_HW_FEATURE_PCSSEL_Pos             6                                                       /*!< ETH HW_FEATURE: PCSSEL Position         */\r
+#define ETH_HW_FEATURE_PCSSEL_Msk             (0x01UL << ETH_HW_FEATURE_PCSSEL_Pos)                   /*!< ETH HW_FEATURE: PCSSEL Mask             */\r
+#define ETH_HW_FEATURE_L3L4FLTREN_Pos         7                                                       /*!< ETH HW_FEATURE: L3L4FLTREN Position     */\r
+#define ETH_HW_FEATURE_L3L4FLTREN_Msk         (0x01UL << ETH_HW_FEATURE_L3L4FLTREN_Pos)               /*!< ETH HW_FEATURE: L3L4FLTREN Mask         */\r
+#define ETH_HW_FEATURE_SMASEL_Pos             8                                                       /*!< ETH HW_FEATURE: SMASEL Position         */\r
+#define ETH_HW_FEATURE_SMASEL_Msk             (0x01UL << ETH_HW_FEATURE_SMASEL_Pos)                   /*!< ETH HW_FEATURE: SMASEL Mask             */\r
+#define ETH_HW_FEATURE_RWKSEL_Pos             9                                                       /*!< ETH HW_FEATURE: RWKSEL Position         */\r
+#define ETH_HW_FEATURE_RWKSEL_Msk             (0x01UL << ETH_HW_FEATURE_RWKSEL_Pos)                   /*!< ETH HW_FEATURE: RWKSEL Mask             */\r
+#define ETH_HW_FEATURE_MGKSEL_Pos             10                                                      /*!< ETH HW_FEATURE: MGKSEL Position         */\r
+#define ETH_HW_FEATURE_MGKSEL_Msk             (0x01UL << ETH_HW_FEATURE_MGKSEL_Pos)                   /*!< ETH HW_FEATURE: MGKSEL Mask             */\r
+#define ETH_HW_FEATURE_MMCSEL_Pos             11                                                      /*!< ETH HW_FEATURE: MMCSEL Position         */\r
+#define ETH_HW_FEATURE_MMCSEL_Msk             (0x01UL << ETH_HW_FEATURE_MMCSEL_Pos)                   /*!< ETH HW_FEATURE: MMCSEL Mask             */\r
+#define ETH_HW_FEATURE_TSVER1SEL_Pos          12                                                      /*!< ETH HW_FEATURE: TSVER1SEL Position      */\r
+#define ETH_HW_FEATURE_TSVER1SEL_Msk          (0x01UL << ETH_HW_FEATURE_TSVER1SEL_Pos)                /*!< ETH HW_FEATURE: TSVER1SEL Mask          */\r
+#define ETH_HW_FEATURE_TSVER2SEL_Pos          13                                                      /*!< ETH HW_FEATURE: TSVER2SEL Position      */\r
+#define ETH_HW_FEATURE_TSVER2SEL_Msk          (0x01UL << ETH_HW_FEATURE_TSVER2SEL_Pos)                /*!< ETH HW_FEATURE: TSVER2SEL Mask          */\r
+#define ETH_HW_FEATURE_EEESEL_Pos             14                                                      /*!< ETH HW_FEATURE: EEESEL Position         */\r
+#define ETH_HW_FEATURE_EEESEL_Msk             (0x01UL << ETH_HW_FEATURE_EEESEL_Pos)                   /*!< ETH HW_FEATURE: EEESEL Mask             */\r
+#define ETH_HW_FEATURE_AVSEL_Pos              15                                                      /*!< ETH HW_FEATURE: AVSEL Position          */\r
+#define ETH_HW_FEATURE_AVSEL_Msk              (0x01UL << ETH_HW_FEATURE_AVSEL_Pos)                    /*!< ETH HW_FEATURE: AVSEL Mask              */\r
+#define ETH_HW_FEATURE_TXCOESEL_Pos           16                                                      /*!< ETH HW_FEATURE: TXCOESEL Position       */\r
+#define ETH_HW_FEATURE_TXCOESEL_Msk           (0x01UL << ETH_HW_FEATURE_TXCOESEL_Pos)                 /*!< ETH HW_FEATURE: TXCOESEL Mask           */\r
+#define ETH_HW_FEATURE_RXTYP1COE_Pos          17                                                      /*!< ETH HW_FEATURE: RXTYP1COE Position      */\r
+#define ETH_HW_FEATURE_RXTYP1COE_Msk          (0x01UL << ETH_HW_FEATURE_RXTYP1COE_Pos)                /*!< ETH HW_FEATURE: RXTYP1COE Mask          */\r
+#define ETH_HW_FEATURE_RXTYP2COE_Pos          18                                                      /*!< ETH HW_FEATURE: RXTYP2COE Position      */\r
+#define ETH_HW_FEATURE_RXTYP2COE_Msk          (0x01UL << ETH_HW_FEATURE_RXTYP2COE_Pos)                /*!< ETH HW_FEATURE: RXTYP2COE Mask          */\r
+#define ETH_HW_FEATURE_RXFIFOSIZE_Pos         19                                                      /*!< ETH HW_FEATURE: RXFIFOSIZE Position     */\r
+#define ETH_HW_FEATURE_RXFIFOSIZE_Msk         (0x01UL << ETH_HW_FEATURE_RXFIFOSIZE_Pos)               /*!< ETH HW_FEATURE: RXFIFOSIZE Mask         */\r
+#define ETH_HW_FEATURE_RXCHCNT_Pos            20                                                      /*!< ETH HW_FEATURE: RXCHCNT Position        */\r
+#define ETH_HW_FEATURE_RXCHCNT_Msk            (0x03UL << ETH_HW_FEATURE_RXCHCNT_Pos)                  /*!< ETH HW_FEATURE: RXCHCNT Mask            */\r
+#define ETH_HW_FEATURE_TXCHCNT_Pos            22                                                      /*!< ETH HW_FEATURE: TXCHCNT Position        */\r
+#define ETH_HW_FEATURE_TXCHCNT_Msk            (0x03UL << ETH_HW_FEATURE_TXCHCNT_Pos)                  /*!< ETH HW_FEATURE: TXCHCNT Mask            */\r
+#define ETH_HW_FEATURE_ENHDESSEL_Pos          24                                                      /*!< ETH HW_FEATURE: ENHDESSEL Position      */\r
+#define ETH_HW_FEATURE_ENHDESSEL_Msk          (0x01UL << ETH_HW_FEATURE_ENHDESSEL_Pos)                /*!< ETH HW_FEATURE: ENHDESSEL Mask          */\r
+#define ETH_HW_FEATURE_INTTSEN_Pos            25                                                      /*!< ETH HW_FEATURE: INTTSEN Position        */\r
+#define ETH_HW_FEATURE_INTTSEN_Msk            (0x01UL << ETH_HW_FEATURE_INTTSEN_Pos)                  /*!< ETH HW_FEATURE: INTTSEN Mask            */\r
+#define ETH_HW_FEATURE_FLEXIPPSEN_Pos         26                                                      /*!< ETH HW_FEATURE: FLEXIPPSEN Position     */\r
+#define ETH_HW_FEATURE_FLEXIPPSEN_Msk         (0x01UL << ETH_HW_FEATURE_FLEXIPPSEN_Pos)               /*!< ETH HW_FEATURE: FLEXIPPSEN Mask         */\r
+#define ETH_HW_FEATURE_SAVLANINS_Pos          27                                                      /*!< ETH HW_FEATURE: SAVLANINS Position      */\r
+#define ETH_HW_FEATURE_SAVLANINS_Msk          (0x01UL << ETH_HW_FEATURE_SAVLANINS_Pos)                /*!< ETH HW_FEATURE: SAVLANINS Mask          */\r
+#define ETH_HW_FEATURE_ACTPHYIF_Pos           28                                                      /*!< ETH HW_FEATURE: ACTPHYIF Position       */\r
+#define ETH_HW_FEATURE_ACTPHYIF_Msk           (0x07UL << ETH_HW_FEATURE_ACTPHYIF_Pos)                 /*!< ETH HW_FEATURE: ACTPHYIF Mask           */\r
+#define ETH_HW_FEATURE_Reserved_31_Pos        31                                                      /*!< ETH HW_FEATURE: Reserved_31 Position    */\r
+#define ETH_HW_FEATURE_Reserved_31_Msk        (0x01UL << ETH_HW_FEATURE_Reserved_31_Pos)              /*!< ETH HW_FEATURE: Reserved_31 Mask        */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'USB' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  USB_GOTGCTL  -------------------------------- */\r
+#define USB_GOTGCTL_SesReqScs_Pos             0                                                       /*!< USB GOTGCTL: SesReqScs Position         */\r
+#define USB_GOTGCTL_SesReqScs_Msk             (0x01UL << USB_GOTGCTL_SesReqScs_Pos)                   /*!< USB GOTGCTL: SesReqScs Mask             */\r
+#define USB_GOTGCTL_SesReq_Pos                1                                                       /*!< USB GOTGCTL: SesReq Position            */\r
+#define USB_GOTGCTL_SesReq_Msk                (0x01UL << USB_GOTGCTL_SesReq_Pos)                      /*!< USB GOTGCTL: SesReq Mask                */\r
+#define USB_GOTGCTL_VbvalidOvEn_Pos           2                                                       /*!< USB GOTGCTL: VbvalidOvEn Position       */\r
+#define USB_GOTGCTL_VbvalidOvEn_Msk           (0x01UL << USB_GOTGCTL_VbvalidOvEn_Pos)                 /*!< USB GOTGCTL: VbvalidOvEn Mask           */\r
+#define USB_GOTGCTL_VbvalidOvVal_Pos          3                                                       /*!< USB GOTGCTL: VbvalidOvVal Position      */\r
+#define USB_GOTGCTL_VbvalidOvVal_Msk          (0x01UL << USB_GOTGCTL_VbvalidOvVal_Pos)                /*!< USB GOTGCTL: VbvalidOvVal Mask          */\r
+#define USB_GOTGCTL_AvalidOvEn_Pos            4                                                       /*!< USB GOTGCTL: AvalidOvEn Position        */\r
+#define USB_GOTGCTL_AvalidOvEn_Msk            (0x01UL << USB_GOTGCTL_AvalidOvEn_Pos)                  /*!< USB GOTGCTL: AvalidOvEn Mask            */\r
+#define USB_GOTGCTL_AvalidOvVal_Pos           5                                                       /*!< USB GOTGCTL: AvalidOvVal Position       */\r
+#define USB_GOTGCTL_AvalidOvVal_Msk           (0x01UL << USB_GOTGCTL_AvalidOvVal_Pos)                 /*!< USB GOTGCTL: AvalidOvVal Mask           */\r
+#define USB_GOTGCTL_BvalidOvEn_Pos            6                                                       /*!< USB GOTGCTL: BvalidOvEn Position        */\r
+#define USB_GOTGCTL_BvalidOvEn_Msk            (0x01UL << USB_GOTGCTL_BvalidOvEn_Pos)                  /*!< USB GOTGCTL: BvalidOvEn Mask            */\r
+#define USB_GOTGCTL_BvalidOvVal_Pos           7                                                       /*!< USB GOTGCTL: BvalidOvVal Position       */\r
+#define USB_GOTGCTL_BvalidOvVal_Msk           (0x01UL << USB_GOTGCTL_BvalidOvVal_Pos)                 /*!< USB GOTGCTL: BvalidOvVal Mask           */\r
+#define USB_GOTGCTL_HstNegScs_Pos             8                                                       /*!< USB GOTGCTL: HstNegScs Position         */\r
+#define USB_GOTGCTL_HstNegScs_Msk             (0x01UL << USB_GOTGCTL_HstNegScs_Pos)                   /*!< USB GOTGCTL: HstNegScs Mask             */\r
+#define USB_GOTGCTL_HNPReq_Pos                9                                                       /*!< USB GOTGCTL: HNPReq Position            */\r
+#define USB_GOTGCTL_HNPReq_Msk                (0x01UL << USB_GOTGCTL_HNPReq_Pos)                      /*!< USB GOTGCTL: HNPReq Mask                */\r
+#define USB_GOTGCTL_HstSetHNPEn_Pos           10                                                      /*!< USB GOTGCTL: HstSetHNPEn Position       */\r
+#define USB_GOTGCTL_HstSetHNPEn_Msk           (0x01UL << USB_GOTGCTL_HstSetHNPEn_Pos)                 /*!< USB GOTGCTL: HstSetHNPEn Mask           */\r
+#define USB_GOTGCTL_DevHNPEn_Pos              11                                                      /*!< USB GOTGCTL: DevHNPEn Position          */\r
+#define USB_GOTGCTL_DevHNPEn_Msk              (0x01UL << USB_GOTGCTL_DevHNPEn_Pos)                    /*!< USB GOTGCTL: DevHNPEn Mask              */\r
+#define USB_GOTGCTL_ConlDSts_Pos              16                                                      /*!< USB GOTGCTL: ConlDSts Position          */\r
+#define USB_GOTGCTL_ConlDSts_Msk              (0x01UL << USB_GOTGCTL_ConlDSts_Pos)                    /*!< USB GOTGCTL: ConlDSts Mask              */\r
+#define USB_GOTGCTL_DbncTime_Pos              17                                                      /*!< USB GOTGCTL: DbncTime Position          */\r
+#define USB_GOTGCTL_DbncTime_Msk              (0x01UL << USB_GOTGCTL_DbncTime_Pos)                    /*!< USB GOTGCTL: DbncTime Mask              */\r
+#define USB_GOTGCTL_ASesVId_Pos               18                                                      /*!< USB GOTGCTL: ASesVId Position           */\r
+#define USB_GOTGCTL_ASesVId_Msk               (0x01UL << USB_GOTGCTL_ASesVId_Pos)                     /*!< USB GOTGCTL: ASesVId Mask               */\r
+#define USB_GOTGCTL_BSesVld_Pos               19                                                      /*!< USB GOTGCTL: BSesVld Position           */\r
+#define USB_GOTGCTL_BSesVld_Msk               (0x01UL << USB_GOTGCTL_BSesVld_Pos)                     /*!< USB GOTGCTL: BSesVld Mask               */\r
+#define USB_GOTGCTL_OTGVer_Pos                20                                                      /*!< USB GOTGCTL: OTGVer Position            */\r
+#define USB_GOTGCTL_OTGVer_Msk                (0x01UL << USB_GOTGCTL_OTGVer_Pos)                      /*!< USB GOTGCTL: OTGVer Mask                */\r
+\r
+/* ---------------------------------  USB_GOTGINT  -------------------------------- */\r
+#define USB_GOTGINT_SesEndDet_Pos             2                                                       /*!< USB GOTGINT: SesEndDet Position         */\r
+#define USB_GOTGINT_SesEndDet_Msk             (0x01UL << USB_GOTGINT_SesEndDet_Pos)                   /*!< USB GOTGINT: SesEndDet Mask             */\r
+#define USB_GOTGINT_SesReqSucStsChng_Pos      8                                                       /*!< USB GOTGINT: SesReqSucStsChng Position  */\r
+#define USB_GOTGINT_SesReqSucStsChng_Msk      (0x01UL << USB_GOTGINT_SesReqSucStsChng_Pos)            /*!< USB GOTGINT: SesReqSucStsChng Mask      */\r
+#define USB_GOTGINT_HstNegSucStsChng_Pos      9                                                       /*!< USB GOTGINT: HstNegSucStsChng Position  */\r
+#define USB_GOTGINT_HstNegSucStsChng_Msk      (0x01UL << USB_GOTGINT_HstNegSucStsChng_Pos)            /*!< USB GOTGINT: HstNegSucStsChng Mask      */\r
+#define USB_GOTGINT_HstNegDet_Pos             17                                                      /*!< USB GOTGINT: HstNegDet Position         */\r
+#define USB_GOTGINT_HstNegDet_Msk             (0x01UL << USB_GOTGINT_HstNegDet_Pos)                   /*!< USB GOTGINT: HstNegDet Mask             */\r
+#define USB_GOTGINT_ADevTOUTChg_Pos           18                                                      /*!< USB GOTGINT: ADevTOUTChg Position       */\r
+#define USB_GOTGINT_ADevTOUTChg_Msk           (0x01UL << USB_GOTGINT_ADevTOUTChg_Pos)                 /*!< USB GOTGINT: ADevTOUTChg Mask           */\r
+#define USB_GOTGINT_DbnceDone_Pos             19                                                      /*!< USB GOTGINT: DbnceDone Position         */\r
+#define USB_GOTGINT_DbnceDone_Msk             (0x01UL << USB_GOTGINT_DbnceDone_Pos)                   /*!< USB GOTGINT: DbnceDone Mask             */\r
+\r
+/* ---------------------------------  USB_GAHBCFG  -------------------------------- */\r
+#define USB_GAHBCFG_GlblIntrMsk_Pos           0                                                       /*!< USB GAHBCFG: GlblIntrMsk Position       */\r
+#define USB_GAHBCFG_GlblIntrMsk_Msk           (0x01UL << USB_GAHBCFG_GlblIntrMsk_Pos)                 /*!< USB GAHBCFG: GlblIntrMsk Mask           */\r
+#define USB_GAHBCFG_HBstLen_Pos               1                                                       /*!< USB GAHBCFG: HBstLen Position           */\r
+#define USB_GAHBCFG_HBstLen_Msk               (0x0fUL << USB_GAHBCFG_HBstLen_Pos)                     /*!< USB GAHBCFG: HBstLen Mask               */\r
+#define USB_GAHBCFG_DMAEn_Pos                 5                                                       /*!< USB GAHBCFG: DMAEn Position             */\r
+#define USB_GAHBCFG_DMAEn_Msk                 (0x01UL << USB_GAHBCFG_DMAEn_Pos)                       /*!< USB GAHBCFG: DMAEn Mask                 */\r
+#define USB_GAHBCFG_NPTxFEmpLvl_Pos           7                                                       /*!< USB GAHBCFG: NPTxFEmpLvl Position       */\r
+#define USB_GAHBCFG_NPTxFEmpLvl_Msk           (0x01UL << USB_GAHBCFG_NPTxFEmpLvl_Pos)                 /*!< USB GAHBCFG: NPTxFEmpLvl Mask           */\r
+#define USB_GAHBCFG_PTxFEmpLvl_Pos            8                                                       /*!< USB GAHBCFG: PTxFEmpLvl Position        */\r
+#define USB_GAHBCFG_PTxFEmpLvl_Msk            (0x01UL << USB_GAHBCFG_PTxFEmpLvl_Pos)                  /*!< USB GAHBCFG: PTxFEmpLvl Mask            */\r
+#define USB_GAHBCFG_AHBSingle_Pos             23                                                      /*!< USB GAHBCFG: AHBSingle Position         */\r
+#define USB_GAHBCFG_AHBSingle_Msk             (0x01UL << USB_GAHBCFG_AHBSingle_Pos)                   /*!< USB GAHBCFG: AHBSingle Mask             */\r
+\r
+/* ---------------------------------  USB_GUSBCFG  -------------------------------- */\r
+#define USB_GUSBCFG_TOutCal_Pos               0                                                       /*!< USB GUSBCFG: TOutCal Position           */\r
+#define USB_GUSBCFG_TOutCal_Msk               (0x07UL << USB_GUSBCFG_TOutCal_Pos)                     /*!< USB GUSBCFG: TOutCal Mask               */\r
+#define USB_GUSBCFG_PHYSel_Pos                6                                                       /*!< USB GUSBCFG: PHYSel Position            */\r
+#define USB_GUSBCFG_PHYSel_Msk                (0x01UL << USB_GUSBCFG_PHYSel_Pos)                      /*!< USB GUSBCFG: PHYSel Mask                */\r
+#define USB_GUSBCFG_SRPCap_Pos                8                                                       /*!< USB GUSBCFG: SRPCap Position            */\r
+#define USB_GUSBCFG_SRPCap_Msk                (0x01UL << USB_GUSBCFG_SRPCap_Pos)                      /*!< USB GUSBCFG: SRPCap Mask                */\r
+#define USB_GUSBCFG_HNPCap_Pos                9                                                       /*!< USB GUSBCFG: HNPCap Position            */\r
+#define USB_GUSBCFG_HNPCap_Msk                (0x01UL << USB_GUSBCFG_HNPCap_Pos)                      /*!< USB GUSBCFG: HNPCap Mask                */\r
+#define USB_GUSBCFG_USBTrdTim_Pos             10                                                      /*!< USB GUSBCFG: USBTrdTim Position         */\r
+#define USB_GUSBCFG_USBTrdTim_Msk             (0x0fUL << USB_GUSBCFG_USBTrdTim_Pos)                   /*!< USB GUSBCFG: USBTrdTim Mask             */\r
+#define USB_GUSBCFG_OtgI2CSel_Pos             16                                                      /*!< USB GUSBCFG: OtgI2CSel Position         */\r
+#define USB_GUSBCFG_OtgI2CSel_Msk             (0x01UL << USB_GUSBCFG_OtgI2CSel_Pos)                   /*!< USB GUSBCFG: OtgI2CSel Mask             */\r
+#define USB_GUSBCFG_TxEndDelay_Pos            28                                                      /*!< USB GUSBCFG: TxEndDelay Position        */\r
+#define USB_GUSBCFG_TxEndDelay_Msk            (0x01UL << USB_GUSBCFG_TxEndDelay_Pos)                  /*!< USB GUSBCFG: TxEndDelay Mask            */\r
+#define USB_GUSBCFG_ForceHstMode_Pos          29                                                      /*!< USB GUSBCFG: ForceHstMode Position      */\r
+#define USB_GUSBCFG_ForceHstMode_Msk          (0x01UL << USB_GUSBCFG_ForceHstMode_Pos)                /*!< USB GUSBCFG: ForceHstMode Mask          */\r
+#define USB_GUSBCFG_ForceDevMode_Pos          30                                                      /*!< USB GUSBCFG: ForceDevMode Position      */\r
+#define USB_GUSBCFG_ForceDevMode_Msk          (0x01UL << USB_GUSBCFG_ForceDevMode_Pos)                /*!< USB GUSBCFG: ForceDevMode Mask          */\r
+#define USB_GUSBCFG_CTP_Pos                   31                                                      /*!< USB GUSBCFG: CTP Position               */\r
+#define USB_GUSBCFG_CTP_Msk                   (0x01UL << USB_GUSBCFG_CTP_Pos)                         /*!< USB GUSBCFG: CTP Mask                   */\r
+\r
+/* ---------------------------------  USB_GRSTCTL  -------------------------------- */\r
+#define USB_GRSTCTL_CSftRst_Pos               0                                                       /*!< USB GRSTCTL: CSftRst Position           */\r
+#define USB_GRSTCTL_CSftRst_Msk               (0x01UL << USB_GRSTCTL_CSftRst_Pos)                     /*!< USB GRSTCTL: CSftRst Mask               */\r
+#define USB_GRSTCTL_FrmCntrRst_Pos            2                                                       /*!< USB GRSTCTL: FrmCntrRst Position        */\r
+#define USB_GRSTCTL_FrmCntrRst_Msk            (0x01UL << USB_GRSTCTL_FrmCntrRst_Pos)                  /*!< USB GRSTCTL: FrmCntrRst Mask            */\r
+#define USB_GRSTCTL_RxFFlsh_Pos               4                                                       /*!< USB GRSTCTL: RxFFlsh Position           */\r
+#define USB_GRSTCTL_RxFFlsh_Msk               (0x01UL << USB_GRSTCTL_RxFFlsh_Pos)                     /*!< USB GRSTCTL: RxFFlsh Mask               */\r
+#define USB_GRSTCTL_TxFFlsh_Pos               5                                                       /*!< USB GRSTCTL: TxFFlsh Position           */\r
+#define USB_GRSTCTL_TxFFlsh_Msk               (0x01UL << USB_GRSTCTL_TxFFlsh_Pos)                     /*!< USB GRSTCTL: TxFFlsh Mask               */\r
+#define USB_GRSTCTL_TxFNum_Pos                6                                                       /*!< USB GRSTCTL: TxFNum Position            */\r
+#define USB_GRSTCTL_TxFNum_Msk                (0x1fUL << USB_GRSTCTL_TxFNum_Pos)                      /*!< USB GRSTCTL: TxFNum Mask                */\r
+#define USB_GRSTCTL_DMAReq_Pos                30                                                      /*!< USB GRSTCTL: DMAReq Position            */\r
+#define USB_GRSTCTL_DMAReq_Msk                (0x01UL << USB_GRSTCTL_DMAReq_Pos)                      /*!< USB GRSTCTL: DMAReq Mask                */\r
+#define USB_GRSTCTL_AHBIdle_Pos               31                                                      /*!< USB GRSTCTL: AHBIdle Position           */\r
+#define USB_GRSTCTL_AHBIdle_Msk               (0x01UL << USB_GRSTCTL_AHBIdle_Pos)                     /*!< USB GRSTCTL: AHBIdle Mask               */\r
+\r
+/* ----------------------------  USB_GINTSTS_HOSTMODE  ---------------------------- */\r
+#define USB_GINTSTS_HOSTMODE_CurMod_Pos       0                                                       /*!< USB GINTSTS_HOSTMODE: CurMod Position   */\r
+#define USB_GINTSTS_HOSTMODE_CurMod_Msk       (0x01UL << USB_GINTSTS_HOSTMODE_CurMod_Pos)             /*!< USB GINTSTS_HOSTMODE: CurMod Mask       */\r
+#define USB_GINTSTS_HOSTMODE_ModeMis_Pos      1                                                       /*!< USB GINTSTS_HOSTMODE: ModeMis Position  */\r
+#define USB_GINTSTS_HOSTMODE_ModeMis_Msk      (0x01UL << USB_GINTSTS_HOSTMODE_ModeMis_Pos)            /*!< USB GINTSTS_HOSTMODE: ModeMis Mask      */\r
+#define USB_GINTSTS_HOSTMODE_OTGInt_Pos       2                                                       /*!< USB GINTSTS_HOSTMODE: OTGInt Position   */\r
+#define USB_GINTSTS_HOSTMODE_OTGInt_Msk       (0x01UL << USB_GINTSTS_HOSTMODE_OTGInt_Pos)             /*!< USB GINTSTS_HOSTMODE: OTGInt Mask       */\r
+#define USB_GINTSTS_HOSTMODE_Sof_Pos          3                                                       /*!< USB GINTSTS_HOSTMODE: Sof Position      */\r
+#define USB_GINTSTS_HOSTMODE_Sof_Msk          (0x01UL << USB_GINTSTS_HOSTMODE_Sof_Pos)                /*!< USB GINTSTS_HOSTMODE: Sof Mask          */\r
+#define USB_GINTSTS_HOSTMODE_RxFLvl_Pos       4                                                       /*!< USB GINTSTS_HOSTMODE: RxFLvl Position   */\r
+#define USB_GINTSTS_HOSTMODE_RxFLvl_Msk       (0x01UL << USB_GINTSTS_HOSTMODE_RxFLvl_Pos)             /*!< USB GINTSTS_HOSTMODE: RxFLvl Mask       */\r
+#define USB_GINTSTS_HOSTMODE_incomplP_Pos     21                                                      /*!< USB GINTSTS_HOSTMODE: incomplP Position */\r
+#define USB_GINTSTS_HOSTMODE_incomplP_Msk     (0x01UL << USB_GINTSTS_HOSTMODE_incomplP_Pos)           /*!< USB GINTSTS_HOSTMODE: incomplP Mask     */\r
+#define USB_GINTSTS_HOSTMODE_PrtInt_Pos       24                                                      /*!< USB GINTSTS_HOSTMODE: PrtInt Position   */\r
+#define USB_GINTSTS_HOSTMODE_PrtInt_Msk       (0x01UL << USB_GINTSTS_HOSTMODE_PrtInt_Pos)             /*!< USB GINTSTS_HOSTMODE: PrtInt Mask       */\r
+#define USB_GINTSTS_HOSTMODE_HChInt_Pos       25                                                      /*!< USB GINTSTS_HOSTMODE: HChInt Position   */\r
+#define USB_GINTSTS_HOSTMODE_HChInt_Msk       (0x01UL << USB_GINTSTS_HOSTMODE_HChInt_Pos)             /*!< USB GINTSTS_HOSTMODE: HChInt Mask       */\r
+#define USB_GINTSTS_HOSTMODE_PTxFEmp_Pos      26                                                      /*!< USB GINTSTS_HOSTMODE: PTxFEmp Position  */\r
+#define USB_GINTSTS_HOSTMODE_PTxFEmp_Msk      (0x01UL << USB_GINTSTS_HOSTMODE_PTxFEmp_Pos)            /*!< USB GINTSTS_HOSTMODE: PTxFEmp Mask      */\r
+#define USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos 28                                                      /*!< USB GINTSTS_HOSTMODE: ConIDStsChng Position */\r
+#define USB_GINTSTS_HOSTMODE_ConIDStsChng_Msk (0x01UL << USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos)       /*!< USB GINTSTS_HOSTMODE: ConIDStsChng Mask */\r
+#define USB_GINTSTS_HOSTMODE_DisconnInt_Pos   29                                                      /*!< USB GINTSTS_HOSTMODE: DisconnInt Position */\r
+#define USB_GINTSTS_HOSTMODE_DisconnInt_Msk   (0x01UL << USB_GINTSTS_HOSTMODE_DisconnInt_Pos)         /*!< USB GINTSTS_HOSTMODE: DisconnInt Mask   */\r
+#define USB_GINTSTS_HOSTMODE_SessReqInt_Pos   30                                                      /*!< USB GINTSTS_HOSTMODE: SessReqInt Position */\r
+#define USB_GINTSTS_HOSTMODE_SessReqInt_Msk   (0x01UL << USB_GINTSTS_HOSTMODE_SessReqInt_Pos)         /*!< USB GINTSTS_HOSTMODE: SessReqInt Mask   */\r
+#define USB_GINTSTS_HOSTMODE_WkUpInt_Pos      31                                                      /*!< USB GINTSTS_HOSTMODE: WkUpInt Position  */\r
+#define USB_GINTSTS_HOSTMODE_WkUpInt_Msk      (0x01UL << USB_GINTSTS_HOSTMODE_WkUpInt_Pos)            /*!< USB GINTSTS_HOSTMODE: WkUpInt Mask      */\r
+\r
+/* ---------------------------  USB_GINTSTS_DEVICEMODE  --------------------------- */\r
+#define USB_GINTSTS_DEVICEMODE_CurMod_Pos     0                                                       /*!< USB GINTSTS_DEVICEMODE: CurMod Position */\r
+#define USB_GINTSTS_DEVICEMODE_CurMod_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_CurMod_Pos)           /*!< USB GINTSTS_DEVICEMODE: CurMod Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_ModeMis_Pos    1                                                       /*!< USB GINTSTS_DEVICEMODE: ModeMis Position */\r
+#define USB_GINTSTS_DEVICEMODE_ModeMis_Msk    (0x01UL << USB_GINTSTS_DEVICEMODE_ModeMis_Pos)          /*!< USB GINTSTS_DEVICEMODE: ModeMis Mask    */\r
+#define USB_GINTSTS_DEVICEMODE_OTGInt_Pos     2                                                       /*!< USB GINTSTS_DEVICEMODE: OTGInt Position */\r
+#define USB_GINTSTS_DEVICEMODE_OTGInt_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_OTGInt_Pos)           /*!< USB GINTSTS_DEVICEMODE: OTGInt Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_Sof_Pos        3                                                       /*!< USB GINTSTS_DEVICEMODE: Sof Position    */\r
+#define USB_GINTSTS_DEVICEMODE_Sof_Msk        (0x01UL << USB_GINTSTS_DEVICEMODE_Sof_Pos)              /*!< USB GINTSTS_DEVICEMODE: Sof Mask        */\r
+#define USB_GINTSTS_DEVICEMODE_RxFLvl_Pos     4                                                       /*!< USB GINTSTS_DEVICEMODE: RxFLvl Position */\r
+#define USB_GINTSTS_DEVICEMODE_RxFLvl_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_RxFLvl_Pos)           /*!< USB GINTSTS_DEVICEMODE: RxFLvl Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_GINNakEff_Pos  6                                                       /*!< USB GINTSTS_DEVICEMODE: GINNakEff Position */\r
+#define USB_GINTSTS_DEVICEMODE_GINNakEff_Msk  (0x01UL << USB_GINTSTS_DEVICEMODE_GINNakEff_Pos)        /*!< USB GINTSTS_DEVICEMODE: GINNakEff Mask  */\r
+#define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos 7                                                       /*!< USB GINTSTS_DEVICEMODE: GOUTNakEff Position */\r
+#define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos)       /*!< USB GINTSTS_DEVICEMODE: GOUTNakEff Mask */\r
+#define USB_GINTSTS_DEVICEMODE_ErlySusp_Pos   10                                                      /*!< USB GINTSTS_DEVICEMODE: ErlySusp Position */\r
+#define USB_GINTSTS_DEVICEMODE_ErlySusp_Msk   (0x01UL << USB_GINTSTS_DEVICEMODE_ErlySusp_Pos)         /*!< USB GINTSTS_DEVICEMODE: ErlySusp Mask   */\r
+#define USB_GINTSTS_DEVICEMODE_USBSusp_Pos    11                                                      /*!< USB GINTSTS_DEVICEMODE: USBSusp Position */\r
+#define USB_GINTSTS_DEVICEMODE_USBSusp_Msk    (0x01UL << USB_GINTSTS_DEVICEMODE_USBSusp_Pos)          /*!< USB GINTSTS_DEVICEMODE: USBSusp Mask    */\r
+#define USB_GINTSTS_DEVICEMODE_USBRst_Pos     12                                                      /*!< USB GINTSTS_DEVICEMODE: USBRst Position */\r
+#define USB_GINTSTS_DEVICEMODE_USBRst_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_USBRst_Pos)           /*!< USB GINTSTS_DEVICEMODE: USBRst Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_EnumDone_Pos   13                                                      /*!< USB GINTSTS_DEVICEMODE: EnumDone Position */\r
+#define USB_GINTSTS_DEVICEMODE_EnumDone_Msk   (0x01UL << USB_GINTSTS_DEVICEMODE_EnumDone_Pos)         /*!< USB GINTSTS_DEVICEMODE: EnumDone Mask   */\r
+#define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos 14                                                      /*!< USB GINTSTS_DEVICEMODE: ISOOutDrop Position */\r
+#define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos)       /*!< USB GINTSTS_DEVICEMODE: ISOOutDrop Mask */\r
+#define USB_GINTSTS_DEVICEMODE_EOPF_Pos       15                                                      /*!< USB GINTSTS_DEVICEMODE: EOPF Position   */\r
+#define USB_GINTSTS_DEVICEMODE_EOPF_Msk       (0x01UL << USB_GINTSTS_DEVICEMODE_EOPF_Pos)             /*!< USB GINTSTS_DEVICEMODE: EOPF Mask       */\r
+#define USB_GINTSTS_DEVICEMODE_IEPInt_Pos     18                                                      /*!< USB GINTSTS_DEVICEMODE: IEPInt Position */\r
+#define USB_GINTSTS_DEVICEMODE_IEPInt_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_IEPInt_Pos)           /*!< USB GINTSTS_DEVICEMODE: IEPInt Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_OEPInt_Pos     19                                                      /*!< USB GINTSTS_DEVICEMODE: OEPInt Position */\r
+#define USB_GINTSTS_DEVICEMODE_OEPInt_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_OEPInt_Pos)           /*!< USB GINTSTS_DEVICEMODE: OEPInt Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_incompISOIN_Pos 20                                                     /*!< USB GINTSTS_DEVICEMODE: incompISOIN Position */\r
+#define USB_GINTSTS_DEVICEMODE_incompISOIN_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_incompISOIN_Pos)     /*!< USB GINTSTS_DEVICEMODE: incompISOIN Mask */\r
+#define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos 21                                                    /*!< USB GINTSTS_DEVICEMODE: incomplSOOUT Position */\r
+#define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos)   /*!< USB GINTSTS_DEVICEMODE: incomplSOOUT Mask */\r
+#define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos 28                                                    /*!< USB GINTSTS_DEVICEMODE: ConIDStsChng Position */\r
+#define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos)   /*!< USB GINTSTS_DEVICEMODE: ConIDStsChng Mask */\r
+#define USB_GINTSTS_DEVICEMODE_SessReqInt_Pos 30                                                      /*!< USB GINTSTS_DEVICEMODE: SessReqInt Position */\r
+#define USB_GINTSTS_DEVICEMODE_SessReqInt_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_SessReqInt_Pos)       /*!< USB GINTSTS_DEVICEMODE: SessReqInt Mask */\r
+#define USB_GINTSTS_DEVICEMODE_WkUpInt_Pos    31                                                      /*!< USB GINTSTS_DEVICEMODE: WkUpInt Position */\r
+#define USB_GINTSTS_DEVICEMODE_WkUpInt_Msk    (0x01UL << USB_GINTSTS_DEVICEMODE_WkUpInt_Pos)          /*!< USB GINTSTS_DEVICEMODE: WkUpInt Mask    */\r
+\r
+/* ----------------------------  USB_GINTMSK_HOSTMODE  ---------------------------- */\r
+#define USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos   1                                                       /*!< USB GINTMSK_HOSTMODE: ModeMisMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_ModeMisMsk_Msk   (0x01UL << USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos)         /*!< USB GINTMSK_HOSTMODE: ModeMisMsk Mask   */\r
+#define USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos    2                                                       /*!< USB GINTMSK_HOSTMODE: OTGIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_OTGIntMsk_Msk    (0x01UL << USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos)          /*!< USB GINTMSK_HOSTMODE: OTGIntMsk Mask    */\r
+#define USB_GINTMSK_HOSTMODE_SofMsk_Pos       3                                                       /*!< USB GINTMSK_HOSTMODE: SofMsk Position   */\r
+#define USB_GINTMSK_HOSTMODE_SofMsk_Msk       (0x01UL << USB_GINTMSK_HOSTMODE_SofMsk_Pos)             /*!< USB GINTMSK_HOSTMODE: SofMsk Mask       */\r
+#define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos    4                                                       /*!< USB GINTMSK_HOSTMODE: RxFLvlMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk    (0x01UL << USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos)          /*!< USB GINTMSK_HOSTMODE: RxFLvlMsk Mask    */\r
+#define USB_GINTMSK_HOSTMODE_incomplPMsk_Pos  21                                                      /*!< USB GINTMSK_HOSTMODE: incomplPMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_incomplPMsk_Msk  (0x01UL << USB_GINTMSK_HOSTMODE_incomplPMsk_Pos)        /*!< USB GINTMSK_HOSTMODE: incomplPMsk Mask  */\r
+#define USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos    24                                                      /*!< USB GINTMSK_HOSTMODE: PrtIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk    (0x01UL << USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos)          /*!< USB GINTMSK_HOSTMODE: PrtIntMsk Mask    */\r
+#define USB_GINTMSK_HOSTMODE_HChIntMsk_Pos    25                                                      /*!< USB GINTMSK_HOSTMODE: HChIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_HChIntMsk_Msk    (0x01UL << USB_GINTMSK_HOSTMODE_HChIntMsk_Pos)          /*!< USB GINTMSK_HOSTMODE: HChIntMsk Mask    */\r
+#define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos   26                                                      /*!< USB GINTMSK_HOSTMODE: PTxFEmpMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Msk   (0x01UL << USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos)         /*!< USB GINTMSK_HOSTMODE: PTxFEmpMsk Mask   */\r
+#define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos 28                                                   /*!< USB GINTMSK_HOSTMODE: ConIDStsChngMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos) /*!< USB GINTMSK_HOSTMODE: ConIDStsChngMsk Mask */\r
+#define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos 29                                                     /*!< USB GINTMSK_HOSTMODE: DisconnIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos)     /*!< USB GINTMSK_HOSTMODE: DisconnIntMsk Mask */\r
+#define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos 30                                                     /*!< USB GINTMSK_HOSTMODE: SessReqIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos)     /*!< USB GINTMSK_HOSTMODE: SessReqIntMsk Mask */\r
+#define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos   31                                                      /*!< USB GINTMSK_HOSTMODE: WkUpIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk   (0x01UL << USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos)         /*!< USB GINTMSK_HOSTMODE: WkUpIntMsk Mask   */\r
+\r
+/* ---------------------------  USB_GINTMSK_DEVICEMODE  --------------------------- */\r
+#define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos 1                                                       /*!< USB GINTMSK_DEVICEMODE: ModeMisMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos)       /*!< USB GINTMSK_DEVICEMODE: ModeMisMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos  2                                                       /*!< USB GINTMSK_DEVICEMODE: OTGIntMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Msk  (0x01UL << USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos)        /*!< USB GINTMSK_DEVICEMODE: OTGIntMsk Mask  */\r
+#define USB_GINTMSK_DEVICEMODE_SofMsk_Pos     3                                                       /*!< USB GINTMSK_DEVICEMODE: SofMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_SofMsk_Msk     (0x01UL << USB_GINTMSK_DEVICEMODE_SofMsk_Pos)           /*!< USB GINTMSK_DEVICEMODE: SofMsk Mask     */\r
+#define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos  4                                                       /*!< USB GINTMSK_DEVICEMODE: RxFLvlMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Msk  (0x01UL << USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos)        /*!< USB GINTMSK_DEVICEMODE: RxFLvlMsk Mask  */\r
+#define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos 6                                                     /*!< USB GINTMSK_DEVICEMODE: GINNakEffMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos)   /*!< USB GINTMSK_DEVICEMODE: GINNakEffMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos 7                                                    /*!< USB GINTMSK_DEVICEMODE: GOUTNakEffMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: GOUTNakEffMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos 10                                                     /*!< USB GINTMSK_DEVICEMODE: ErlySuspMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos)     /*!< USB GINTMSK_DEVICEMODE: ErlySuspMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos 11                                                      /*!< USB GINTMSK_DEVICEMODE: USBSuspMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos)       /*!< USB GINTMSK_DEVICEMODE: USBSuspMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos  12                                                      /*!< USB GINTMSK_DEVICEMODE: USBRstMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_USBRstMsk_Msk  (0x01UL << USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos)        /*!< USB GINTMSK_DEVICEMODE: USBRstMsk Mask  */\r
+#define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos 13                                                     /*!< USB GINTMSK_DEVICEMODE: EnumDoneMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos)     /*!< USB GINTMSK_DEVICEMODE: EnumDoneMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos 14                                                   /*!< USB GINTMSK_DEVICEMODE: ISOOutDropMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: ISOOutDropMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos    15                                                      /*!< USB GINTMSK_DEVICEMODE: EOPFMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_EOPFMsk_Msk    (0x01UL << USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos)          /*!< USB GINTMSK_DEVICEMODE: EOPFMsk Mask    */\r
+#define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos  18                                                      /*!< USB GINTMSK_DEVICEMODE: IEPIntMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Msk  (0x01UL << USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos)        /*!< USB GINTMSK_DEVICEMODE: IEPIntMsk Mask  */\r
+#define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos  19                                                      /*!< USB GINTMSK_DEVICEMODE: OEPIntMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Msk  (0x01UL << USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos)        /*!< USB GINTMSK_DEVICEMODE: OEPIntMsk Mask  */\r
+#define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos 20                                                  /*!< USB GINTMSK_DEVICEMODE: incompISOINMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos)/*!< USB GINTMSK_DEVICEMODE: incompISOINMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos 21                                                 /*!< USB GINTMSK_DEVICEMODE: incomplSOOUTMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos)/*!< USB GINTMSK_DEVICEMODE: incomplSOOUTMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos 28                                                 /*!< USB GINTMSK_DEVICEMODE: ConIDStsChngMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos)/*!< USB GINTMSK_DEVICEMODE: ConIDStsChngMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Pos 29                                                   /*!< USB GINTMSK_DEVICEMODE: DisconnIntMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: DisconnIntMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos 30                                                   /*!< USB GINTMSK_DEVICEMODE: SessReqIntMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: SessReqIntMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos 31                                                      /*!< USB GINTMSK_DEVICEMODE: WkUpIntMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos)       /*!< USB GINTMSK_DEVICEMODE: WkUpIntMsk Mask */\r
+\r
+/* ----------------------------  USB_GRXSTSR_HOSTMODE  ---------------------------- */\r
+#define USB_GRXSTSR_HOSTMODE_ChNum_Pos        0                                                       /*!< USB GRXSTSR_HOSTMODE: ChNum Position    */\r
+#define USB_GRXSTSR_HOSTMODE_ChNum_Msk        (0x0fUL << USB_GRXSTSR_HOSTMODE_ChNum_Pos)              /*!< USB GRXSTSR_HOSTMODE: ChNum Mask        */\r
+#define USB_GRXSTSR_HOSTMODE_BCnt_Pos         4                                                       /*!< USB GRXSTSR_HOSTMODE: BCnt Position     */\r
+#define USB_GRXSTSR_HOSTMODE_BCnt_Msk         (0x000007ffUL << USB_GRXSTSR_HOSTMODE_BCnt_Pos)         /*!< USB GRXSTSR_HOSTMODE: BCnt Mask         */\r
+#define USB_GRXSTSR_HOSTMODE_DPID_Pos         15                                                      /*!< USB GRXSTSR_HOSTMODE: DPID Position     */\r
+#define USB_GRXSTSR_HOSTMODE_DPID_Msk         (0x03UL << USB_GRXSTSR_HOSTMODE_DPID_Pos)               /*!< USB GRXSTSR_HOSTMODE: DPID Mask         */\r
+#define USB_GRXSTSR_HOSTMODE_PktSts_Pos       17                                                      /*!< USB GRXSTSR_HOSTMODE: PktSts Position   */\r
+#define USB_GRXSTSR_HOSTMODE_PktSts_Msk       (0x0fUL << USB_GRXSTSR_HOSTMODE_PktSts_Pos)             /*!< USB GRXSTSR_HOSTMODE: PktSts Mask       */\r
+\r
+/* ---------------------------  USB_GRXSTSR_DEVICEMODE  --------------------------- */\r
+#define USB_GRXSTSR_DEVICEMODE_EPNum_Pos      0                                                       /*!< USB GRXSTSR_DEVICEMODE: EPNum Position  */\r
+#define USB_GRXSTSR_DEVICEMODE_EPNum_Msk      (0x0fUL << USB_GRXSTSR_DEVICEMODE_EPNum_Pos)            /*!< USB GRXSTSR_DEVICEMODE: EPNum Mask      */\r
+#define USB_GRXSTSR_DEVICEMODE_BCnt_Pos       4                                                       /*!< USB GRXSTSR_DEVICEMODE: BCnt Position   */\r
+#define USB_GRXSTSR_DEVICEMODE_BCnt_Msk       (0x000007ffUL << USB_GRXSTSR_DEVICEMODE_BCnt_Pos)       /*!< USB GRXSTSR_DEVICEMODE: BCnt Mask       */\r
+#define USB_GRXSTSR_DEVICEMODE_DPID_Pos       15                                                      /*!< USB GRXSTSR_DEVICEMODE: DPID Position   */\r
+#define USB_GRXSTSR_DEVICEMODE_DPID_Msk       (0x03UL << USB_GRXSTSR_DEVICEMODE_DPID_Pos)             /*!< USB GRXSTSR_DEVICEMODE: DPID Mask       */\r
+#define USB_GRXSTSR_DEVICEMODE_PktSts_Pos     17                                                      /*!< USB GRXSTSR_DEVICEMODE: PktSts Position */\r
+#define USB_GRXSTSR_DEVICEMODE_PktSts_Msk     (0x0fUL << USB_GRXSTSR_DEVICEMODE_PktSts_Pos)           /*!< USB GRXSTSR_DEVICEMODE: PktSts Mask     */\r
+#define USB_GRXSTSR_DEVICEMODE_FN_Pos         21                                                      /*!< USB GRXSTSR_DEVICEMODE: FN Position     */\r
+#define USB_GRXSTSR_DEVICEMODE_FN_Msk         (0x0fUL << USB_GRXSTSR_DEVICEMODE_FN_Pos)               /*!< USB GRXSTSR_DEVICEMODE: FN Mask         */\r
+\r
+/* ---------------------------  USB_GRXSTSP_DEVICEMODE  --------------------------- */\r
+#define USB_GRXSTSP_DEVICEMODE_EPNum_Pos      0                                                       /*!< USB GRXSTSP_DEVICEMODE: EPNum Position  */\r
+#define USB_GRXSTSP_DEVICEMODE_EPNum_Msk      (0x0fUL << USB_GRXSTSP_DEVICEMODE_EPNum_Pos)            /*!< USB GRXSTSP_DEVICEMODE: EPNum Mask      */\r
+#define USB_GRXSTSP_DEVICEMODE_BCnt_Pos       4                                                       /*!< USB GRXSTSP_DEVICEMODE: BCnt Position   */\r
+#define USB_GRXSTSP_DEVICEMODE_BCnt_Msk       (0x000007ffUL << USB_GRXSTSP_DEVICEMODE_BCnt_Pos)       /*!< USB GRXSTSP_DEVICEMODE: BCnt Mask       */\r
+#define USB_GRXSTSP_DEVICEMODE_DPID_Pos       15                                                      /*!< USB GRXSTSP_DEVICEMODE: DPID Position   */\r
+#define USB_GRXSTSP_DEVICEMODE_DPID_Msk       (0x03UL << USB_GRXSTSP_DEVICEMODE_DPID_Pos)             /*!< USB GRXSTSP_DEVICEMODE: DPID Mask       */\r
+#define USB_GRXSTSP_DEVICEMODE_PktSts_Pos     17                                                      /*!< USB GRXSTSP_DEVICEMODE: PktSts Position */\r
+#define USB_GRXSTSP_DEVICEMODE_PktSts_Msk     (0x0fUL << USB_GRXSTSP_DEVICEMODE_PktSts_Pos)           /*!< USB GRXSTSP_DEVICEMODE: PktSts Mask     */\r
+#define USB_GRXSTSP_DEVICEMODE_FN_Pos         21                                                      /*!< USB GRXSTSP_DEVICEMODE: FN Position     */\r
+#define USB_GRXSTSP_DEVICEMODE_FN_Msk         (0x0fUL << USB_GRXSTSP_DEVICEMODE_FN_Pos)               /*!< USB GRXSTSP_DEVICEMODE: FN Mask         */\r
+\r
+/* ----------------------------  USB_GRXSTSP_HOSTMODE  ---------------------------- */\r
+#define USB_GRXSTSP_HOSTMODE_ChNum_Pos        0                                                       /*!< USB GRXSTSP_HOSTMODE: ChNum Position    */\r
+#define USB_GRXSTSP_HOSTMODE_ChNum_Msk        (0x0fUL << USB_GRXSTSP_HOSTMODE_ChNum_Pos)              /*!< USB GRXSTSP_HOSTMODE: ChNum Mask        */\r
+#define USB_GRXSTSP_HOSTMODE_BCnt_Pos         4                                                       /*!< USB GRXSTSP_HOSTMODE: BCnt Position     */\r
+#define USB_GRXSTSP_HOSTMODE_BCnt_Msk         (0x000007ffUL << USB_GRXSTSP_HOSTMODE_BCnt_Pos)         /*!< USB GRXSTSP_HOSTMODE: BCnt Mask         */\r
+#define USB_GRXSTSP_HOSTMODE_DPID_Pos         15                                                      /*!< USB GRXSTSP_HOSTMODE: DPID Position     */\r
+#define USB_GRXSTSP_HOSTMODE_DPID_Msk         (0x03UL << USB_GRXSTSP_HOSTMODE_DPID_Pos)               /*!< USB GRXSTSP_HOSTMODE: DPID Mask         */\r
+#define USB_GRXSTSP_HOSTMODE_PktSts_Pos       17                                                      /*!< USB GRXSTSP_HOSTMODE: PktSts Position   */\r
+#define USB_GRXSTSP_HOSTMODE_PktSts_Msk       (0x0fUL << USB_GRXSTSP_HOSTMODE_PktSts_Pos)             /*!< USB GRXSTSP_HOSTMODE: PktSts Mask       */\r
+\r
+/* ---------------------------------  USB_GRXFSIZ  -------------------------------- */\r
+#define USB_GRXFSIZ_RxFDep_Pos                0                                                       /*!< USB GRXFSIZ: RxFDep Position            */\r
+#define USB_GRXFSIZ_RxFDep_Msk                (0x0000ffffUL << USB_GRXFSIZ_RxFDep_Pos)                /*!< USB GRXFSIZ: RxFDep Mask                */\r
+\r
+/* ---------------------------  USB_GNPTXFSIZ_HOSTMODE  --------------------------- */\r
+#define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos 0                                                      /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFStAddr Position */\r
+#define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Msk (0x0000ffffUL << USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos)/*!< USB GNPTXFSIZ_HOSTMODE: NPTxFStAddr Mask */\r
+#define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos   16                                                      /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFDep Position */\r
+#define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Msk   (0x0000ffffUL << USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos)   /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFDep Mask   */\r
+\r
+/* --------------------------  USB_GNPTXFSIZ_DEVICEMODE  -------------------------- */\r
+#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Pos 0                                                 /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0StAddr Position */\r
+#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Msk (0x0000ffffUL << USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Pos)/*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0StAddr Mask */\r
+#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos 16                                                   /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0Dep Position */\r
+#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Msk (0x0000ffffUL << USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos)/*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0Dep Mask */\r
+\r
+/* --------------------------------  USB_GNPTXSTS  -------------------------------- */\r
+#define USB_GNPTXSTS_NPTxFSpcAvail_Pos        0                                                       /*!< USB GNPTXSTS: NPTxFSpcAvail Position    */\r
+#define USB_GNPTXSTS_NPTxFSpcAvail_Msk        (0x0000ffffUL << USB_GNPTXSTS_NPTxFSpcAvail_Pos)        /*!< USB GNPTXSTS: NPTxFSpcAvail Mask        */\r
+#define USB_GNPTXSTS_NPTxQSpcAvail_Pos        16                                                      /*!< USB GNPTXSTS: NPTxQSpcAvail Position    */\r
+#define USB_GNPTXSTS_NPTxQSpcAvail_Msk        (0x000000ffUL << USB_GNPTXSTS_NPTxQSpcAvail_Pos)        /*!< USB GNPTXSTS: NPTxQSpcAvail Mask        */\r
+#define USB_GNPTXSTS_NPTxQTop_Pos             24                                                      /*!< USB GNPTXSTS: NPTxQTop Position         */\r
+#define USB_GNPTXSTS_NPTxQTop_Msk             (0x7fUL << USB_GNPTXSTS_NPTxQTop_Pos)                   /*!< USB GNPTXSTS: NPTxQTop Mask             */\r
+\r
+/* ----------------------------------  USB_GUID  ---------------------------------- */\r
+#define USB_GUID_MOD_REV_Pos                  0                                                       /*!< USB GUID: MOD_REV Position              */\r
+#define USB_GUID_MOD_REV_Msk                  (0x000000ffUL << USB_GUID_MOD_REV_Pos)                  /*!< USB GUID: MOD_REV Mask                  */\r
+#define USB_GUID_MOD_TYPE_Pos                 8                                                       /*!< USB GUID: MOD_TYPE Position             */\r
+#define USB_GUID_MOD_TYPE_Msk                 (0x000000ffUL << USB_GUID_MOD_TYPE_Pos)                 /*!< USB GUID: MOD_TYPE Mask                 */\r
+#define USB_GUID_MOD_NUMBER_Pos               16                                                      /*!< USB GUID: MOD_NUMBER Position           */\r
+#define USB_GUID_MOD_NUMBER_Msk               (0x0000ffffUL << USB_GUID_MOD_NUMBER_Pos)               /*!< USB GUID: MOD_NUMBER Mask               */\r
+\r
+/* --------------------------------  USB_GDFIFOCFG  ------------------------------- */\r
+#define USB_GDFIFOCFG_GDFIFOCfg_Pos           0                                                       /*!< USB GDFIFOCFG: GDFIFOCfg Position       */\r
+#define USB_GDFIFOCFG_GDFIFOCfg_Msk           (0x0000ffffUL << USB_GDFIFOCFG_GDFIFOCfg_Pos)           /*!< USB GDFIFOCFG: GDFIFOCfg Mask           */\r
+#define USB_GDFIFOCFG_EPInfoBaseAddr_Pos      16                                                      /*!< USB GDFIFOCFG: EPInfoBaseAddr Position  */\r
+#define USB_GDFIFOCFG_EPInfoBaseAddr_Msk      (0x0000ffffUL << USB_GDFIFOCFG_EPInfoBaseAddr_Pos)      /*!< USB GDFIFOCFG: EPInfoBaseAddr Mask      */\r
+\r
+/* --------------------------------  USB_HPTXFSIZ  -------------------------------- */\r
+#define USB_HPTXFSIZ_PTxFStAddr_Pos           0                                                       /*!< USB HPTXFSIZ: PTxFStAddr Position       */\r
+#define USB_HPTXFSIZ_PTxFStAddr_Msk           (0x0000ffffUL << USB_HPTXFSIZ_PTxFStAddr_Pos)           /*!< USB HPTXFSIZ: PTxFStAddr Mask           */\r
+#define USB_HPTXFSIZ_PTxFSize_Pos             16                                                      /*!< USB HPTXFSIZ: PTxFSize Position         */\r
+#define USB_HPTXFSIZ_PTxFSize_Msk             (0x0000ffffUL << USB_HPTXFSIZ_PTxFSize_Pos)             /*!< USB HPTXFSIZ: PTxFSize Mask             */\r
+\r
+/* --------------------------------  USB_DIEPTXF1  -------------------------------- */\r
+#define USB_DIEPTXF1_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF1: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF1_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF1_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF1: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF1_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF1: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF1_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF1_INEPnTxFDep_Pos)          /*!< USB DIEPTXF1: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF2  -------------------------------- */\r
+#define USB_DIEPTXF2_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF2: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF2_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF2_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF2: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF2_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF2: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF2_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF2_INEPnTxFDep_Pos)          /*!< USB DIEPTXF2: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF3  -------------------------------- */\r
+#define USB_DIEPTXF3_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF3: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF3_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF3_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF3: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF3_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF3: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF3_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF3_INEPnTxFDep_Pos)          /*!< USB DIEPTXF3: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF4  -------------------------------- */\r
+#define USB_DIEPTXF4_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF4: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF4_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF4_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF4: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF4_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF4: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF4_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF4_INEPnTxFDep_Pos)          /*!< USB DIEPTXF4: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF5  -------------------------------- */\r
+#define USB_DIEPTXF5_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF5: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF5_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF5_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF5: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF5_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF5: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF5_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF5_INEPnTxFDep_Pos)          /*!< USB DIEPTXF5: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF6  -------------------------------- */\r
+#define USB_DIEPTXF6_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF6: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF6_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF6_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF6: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF6_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF6: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF6_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF6_INEPnTxFDep_Pos)          /*!< USB DIEPTXF6: INEPnTxFDep Mask          */\r
+\r
+/* ----------------------------------  USB_HCFG  ---------------------------------- */\r
+#define USB_HCFG_FSLSPclkSel_Pos              0                                                       /*!< USB HCFG: FSLSPclkSel Position          */\r
+#define USB_HCFG_FSLSPclkSel_Msk              (0x03UL << USB_HCFG_FSLSPclkSel_Pos)                    /*!< USB HCFG: FSLSPclkSel Mask              */\r
+#define USB_HCFG_FSLSSupp_Pos                 2                                                       /*!< USB HCFG: FSLSSupp Position             */\r
+#define USB_HCFG_FSLSSupp_Msk                 (0x01UL << USB_HCFG_FSLSSupp_Pos)                       /*!< USB HCFG: FSLSSupp Mask                 */\r
+#define USB_HCFG_DescDMA_Pos                  23                                                      /*!< USB HCFG: DescDMA Position              */\r
+#define USB_HCFG_DescDMA_Msk                  (0x01UL << USB_HCFG_DescDMA_Pos)                        /*!< USB HCFG: DescDMA Mask                  */\r
+#define USB_HCFG_FrListEn_Pos                 24                                                      /*!< USB HCFG: FrListEn Position             */\r
+#define USB_HCFG_FrListEn_Msk                 (0x03UL << USB_HCFG_FrListEn_Pos)                       /*!< USB HCFG: FrListEn Mask                 */\r
+#define USB_HCFG_PerSchedEna_Pos              26                                                      /*!< USB HCFG: PerSchedEna Position          */\r
+#define USB_HCFG_PerSchedEna_Msk              (0x01UL << USB_HCFG_PerSchedEna_Pos)                    /*!< USB HCFG: PerSchedEna Mask              */\r
+\r
+/* ----------------------------------  USB_HFIR  ---------------------------------- */\r
+#define USB_HFIR_FrInt_Pos                    0                                                       /*!< USB HFIR: FrInt Position                */\r
+#define USB_HFIR_FrInt_Msk                    (0x0000ffffUL << USB_HFIR_FrInt_Pos)                    /*!< USB HFIR: FrInt Mask                    */\r
+#define USB_HFIR_HFIRRldCtrl_Pos              16                                                      /*!< USB HFIR: HFIRRldCtrl Position          */\r
+#define USB_HFIR_HFIRRldCtrl_Msk              (0x01UL << USB_HFIR_HFIRRldCtrl_Pos)                    /*!< USB HFIR: HFIRRldCtrl Mask              */\r
+\r
+/* ----------------------------------  USB_HFNUM  --------------------------------- */\r
+#define USB_HFNUM_FrNum_Pos                   0                                                       /*!< USB HFNUM: FrNum Position               */\r
+#define USB_HFNUM_FrNum_Msk                   (0x0000ffffUL << USB_HFNUM_FrNum_Pos)                   /*!< USB HFNUM: FrNum Mask                   */\r
+#define USB_HFNUM_FrRem_Pos                   16                                                      /*!< USB HFNUM: FrRem Position               */\r
+#define USB_HFNUM_FrRem_Msk                   (0x0000ffffUL << USB_HFNUM_FrRem_Pos)                   /*!< USB HFNUM: FrRem Mask                   */\r
+\r
+/* ---------------------------------  USB_HPTXSTS  -------------------------------- */\r
+#define USB_HPTXSTS_PTxFSpcAvail_Pos          0                                                       /*!< USB HPTXSTS: PTxFSpcAvail Position      */\r
+#define USB_HPTXSTS_PTxFSpcAvail_Msk          (0x0000ffffUL << USB_HPTXSTS_PTxFSpcAvail_Pos)          /*!< USB HPTXSTS: PTxFSpcAvail Mask          */\r
+#define USB_HPTXSTS_PTxQSpcAvail_Pos          16                                                      /*!< USB HPTXSTS: PTxQSpcAvail Position      */\r
+#define USB_HPTXSTS_PTxQSpcAvail_Msk          (0x000000ffUL << USB_HPTXSTS_PTxQSpcAvail_Pos)          /*!< USB HPTXSTS: PTxQSpcAvail Mask          */\r
+#define USB_HPTXSTS_PTxQTop_Pos               24                                                      /*!< USB HPTXSTS: PTxQTop Position           */\r
+#define USB_HPTXSTS_PTxQTop_Msk               (0x000000ffUL << USB_HPTXSTS_PTxQTop_Pos)               /*!< USB HPTXSTS: PTxQTop Mask               */\r
+\r
+/* ----------------------------------  USB_HAINT  --------------------------------- */\r
+#define USB_HAINT_HAINT_Pos                   0                                                       /*!< USB HAINT: HAINT Position               */\r
+#define USB_HAINT_HAINT_Msk                   (0x00003fffUL << USB_HAINT_HAINT_Pos)                   /*!< USB HAINT: HAINT Mask                   */\r
+\r
+/* --------------------------------  USB_HAINTMSK  -------------------------------- */\r
+#define USB_HAINTMSK_HAINTMsk_Pos             0                                                       /*!< USB HAINTMSK: HAINTMsk Position         */\r
+#define USB_HAINTMSK_HAINTMsk_Msk             (0x00003fffUL << USB_HAINTMSK_HAINTMsk_Pos)             /*!< USB HAINTMSK: HAINTMsk Mask             */\r
+\r
+/* --------------------------------  USB_HFLBADDR  -------------------------------- */\r
+#define USB_HFLBADDR_Starting_Address_Pos     0                                                       /*!< USB HFLBADDR: Starting_Address Position */\r
+#define USB_HFLBADDR_Starting_Address_Msk     (0xffffffffUL << USB_HFLBADDR_Starting_Address_Pos)     /*!< USB HFLBADDR: Starting_Address Mask     */\r
+\r
+/* ----------------------------------  USB_HPRT  ---------------------------------- */\r
+#define USB_HPRT_PrtConnSts_Pos               0                                                       /*!< USB HPRT: PrtConnSts Position           */\r
+#define USB_HPRT_PrtConnSts_Msk               (0x01UL << USB_HPRT_PrtConnSts_Pos)                     /*!< USB HPRT: PrtConnSts Mask               */\r
+#define USB_HPRT_PrtConnDet_Pos               1                                                       /*!< USB HPRT: PrtConnDet Position           */\r
+#define USB_HPRT_PrtConnDet_Msk               (0x01UL << USB_HPRT_PrtConnDet_Pos)                     /*!< USB HPRT: PrtConnDet Mask               */\r
+#define USB_HPRT_PrtEna_Pos                   2                                                       /*!< USB HPRT: PrtEna Position               */\r
+#define USB_HPRT_PrtEna_Msk                   (0x01UL << USB_HPRT_PrtEna_Pos)                         /*!< USB HPRT: PrtEna Mask                   */\r
+#define USB_HPRT_PrtEnChng_Pos                3                                                       /*!< USB HPRT: PrtEnChng Position            */\r
+#define USB_HPRT_PrtEnChng_Msk                (0x01UL << USB_HPRT_PrtEnChng_Pos)                      /*!< USB HPRT: PrtEnChng Mask                */\r
+#define USB_HPRT_PrtOvrCurrAct_Pos            4                                                       /*!< USB HPRT: PrtOvrCurrAct Position        */\r
+#define USB_HPRT_PrtOvrCurrAct_Msk            (0x01UL << USB_HPRT_PrtOvrCurrAct_Pos)                  /*!< USB HPRT: PrtOvrCurrAct Mask            */\r
+#define USB_HPRT_PrtOvrCurrChng_Pos           5                                                       /*!< USB HPRT: PrtOvrCurrChng Position       */\r
+#define USB_HPRT_PrtOvrCurrChng_Msk           (0x01UL << USB_HPRT_PrtOvrCurrChng_Pos)                 /*!< USB HPRT: PrtOvrCurrChng Mask           */\r
+#define USB_HPRT_PrtRes_Pos                   6                                                       /*!< USB HPRT: PrtRes Position               */\r
+#define USB_HPRT_PrtRes_Msk                   (0x01UL << USB_HPRT_PrtRes_Pos)                         /*!< USB HPRT: PrtRes Mask                   */\r
+#define USB_HPRT_PrtSusp_Pos                  7                                                       /*!< USB HPRT: PrtSusp Position              */\r
+#define USB_HPRT_PrtSusp_Msk                  (0x01UL << USB_HPRT_PrtSusp_Pos)                        /*!< USB HPRT: PrtSusp Mask                  */\r
+#define USB_HPRT_PrtRst_Pos                   8                                                       /*!< USB HPRT: PrtRst Position               */\r
+#define USB_HPRT_PrtRst_Msk                   (0x01UL << USB_HPRT_PrtRst_Pos)                         /*!< USB HPRT: PrtRst Mask                   */\r
+#define USB_HPRT_PrtLnSts_Pos                 10                                                      /*!< USB HPRT: PrtLnSts Position             */\r
+#define USB_HPRT_PrtLnSts_Msk                 (0x03UL << USB_HPRT_PrtLnSts_Pos)                       /*!< USB HPRT: PrtLnSts Mask                 */\r
+#define USB_HPRT_PrtPwr_Pos                   12                                                      /*!< USB HPRT: PrtPwr Position               */\r
+#define USB_HPRT_PrtPwr_Msk                   (0x01UL << USB_HPRT_PrtPwr_Pos)                         /*!< USB HPRT: PrtPwr Mask                   */\r
+#define USB_HPRT_PrtSpd_Pos                   17                                                      /*!< USB HPRT: PrtSpd Position               */\r
+#define USB_HPRT_PrtSpd_Msk                   (0x03UL << USB_HPRT_PrtSpd_Pos)                         /*!< USB HPRT: PrtSpd Mask                   */\r
+\r
+/* ----------------------------------  USB_DCFG  ---------------------------------- */\r
+#define USB_DCFG_DevSpd_Pos                   0                                                       /*!< USB DCFG: DevSpd Position               */\r
+#define USB_DCFG_DevSpd_Msk                   (0x03UL << USB_DCFG_DevSpd_Pos)                         /*!< USB DCFG: DevSpd Mask                   */\r
+#define USB_DCFG_NZStsOUTHShk_Pos             2                                                       /*!< USB DCFG: NZStsOUTHShk Position         */\r
+#define USB_DCFG_NZStsOUTHShk_Msk             (0x01UL << USB_DCFG_NZStsOUTHShk_Pos)                   /*!< USB DCFG: NZStsOUTHShk Mask             */\r
+#define USB_DCFG_DevAddr_Pos                  4                                                       /*!< USB DCFG: DevAddr Position              */\r
+#define USB_DCFG_DevAddr_Msk                  (0x7fUL << USB_DCFG_DevAddr_Pos)                        /*!< USB DCFG: DevAddr Mask                  */\r
+#define USB_DCFG_PerFrInt_Pos                 11                                                      /*!< USB DCFG: PerFrInt Position             */\r
+#define USB_DCFG_PerFrInt_Msk                 (0x03UL << USB_DCFG_PerFrInt_Pos)                       /*!< USB DCFG: PerFrInt Mask                 */\r
+#define USB_DCFG_DescDMA_Pos                  23                                                      /*!< USB DCFG: DescDMA Position              */\r
+#define USB_DCFG_DescDMA_Msk                  (0x01UL << USB_DCFG_DescDMA_Pos)                        /*!< USB DCFG: DescDMA Mask                  */\r
+#define USB_DCFG_PerSchIntvl_Pos              24                                                      /*!< USB DCFG: PerSchIntvl Position          */\r
+#define USB_DCFG_PerSchIntvl_Msk              (0x03UL << USB_DCFG_PerSchIntvl_Pos)                    /*!< USB DCFG: PerSchIntvl Mask              */\r
+\r
+/* ----------------------------------  USB_DCTL  ---------------------------------- */\r
+#define USB_DCTL_RmtWkUpSig_Pos               0                                                       /*!< USB DCTL: RmtWkUpSig Position           */\r
+#define USB_DCTL_RmtWkUpSig_Msk               (0x01UL << USB_DCTL_RmtWkUpSig_Pos)                     /*!< USB DCTL: RmtWkUpSig Mask               */\r
+#define USB_DCTL_SftDiscon_Pos                1                                                       /*!< USB DCTL: SftDiscon Position            */\r
+#define USB_DCTL_SftDiscon_Msk                (0x01UL << USB_DCTL_SftDiscon_Pos)                      /*!< USB DCTL: SftDiscon Mask                */\r
+#define USB_DCTL_GNPINNakSts_Pos              2                                                       /*!< USB DCTL: GNPINNakSts Position          */\r
+#define USB_DCTL_GNPINNakSts_Msk              (0x01UL << USB_DCTL_GNPINNakSts_Pos)                    /*!< USB DCTL: GNPINNakSts Mask              */\r
+#define USB_DCTL_GOUTNakSts_Pos               3                                                       /*!< USB DCTL: GOUTNakSts Position           */\r
+#define USB_DCTL_GOUTNakSts_Msk               (0x01UL << USB_DCTL_GOUTNakSts_Pos)                     /*!< USB DCTL: GOUTNakSts Mask               */\r
+#define USB_DCTL_SGNPInNak_Pos                7                                                       /*!< USB DCTL: SGNPInNak Position            */\r
+#define USB_DCTL_SGNPInNak_Msk                (0x01UL << USB_DCTL_SGNPInNak_Pos)                      /*!< USB DCTL: SGNPInNak Mask                */\r
+#define USB_DCTL_CGNPInNak_Pos                8                                                       /*!< USB DCTL: CGNPInNak Position            */\r
+#define USB_DCTL_CGNPInNak_Msk                (0x01UL << USB_DCTL_CGNPInNak_Pos)                      /*!< USB DCTL: CGNPInNak Mask                */\r
+#define USB_DCTL_SGOUTNak_Pos                 9                                                       /*!< USB DCTL: SGOUTNak Position             */\r
+#define USB_DCTL_SGOUTNak_Msk                 (0x01UL << USB_DCTL_SGOUTNak_Pos)                       /*!< USB DCTL: SGOUTNak Mask                 */\r
+#define USB_DCTL_CGOUTNak_Pos                 10                                                      /*!< USB DCTL: CGOUTNak Position             */\r
+#define USB_DCTL_CGOUTNak_Msk                 (0x01UL << USB_DCTL_CGOUTNak_Pos)                       /*!< USB DCTL: CGOUTNak Mask                 */\r
+#define USB_DCTL_GMC_Pos                      13                                                      /*!< USB DCTL: GMC Position                  */\r
+#define USB_DCTL_GMC_Msk                      (0x03UL << USB_DCTL_GMC_Pos)                            /*!< USB DCTL: GMC Mask                      */\r
+#define USB_DCTL_IgnrFrmNum_Pos               15                                                      /*!< USB DCTL: IgnrFrmNum Position           */\r
+#define USB_DCTL_IgnrFrmNum_Msk               (0x01UL << USB_DCTL_IgnrFrmNum_Pos)                     /*!< USB DCTL: IgnrFrmNum Mask               */\r
+#define USB_DCTL_NakOnBble_Pos                16                                                      /*!< USB DCTL: NakOnBble Position            */\r
+#define USB_DCTL_NakOnBble_Msk                (0x01UL << USB_DCTL_NakOnBble_Pos)                      /*!< USB DCTL: NakOnBble Mask                */\r
+#define USB_DCTL_EnContOnBNA_Pos              17                                                      /*!< USB DCTL: EnContOnBNA Position          */\r
+#define USB_DCTL_EnContOnBNA_Msk              (0x01UL << USB_DCTL_EnContOnBNA_Pos)                    /*!< USB DCTL: EnContOnBNA Mask              */\r
+\r
+/* ----------------------------------  USB_DSTS  ---------------------------------- */\r
+#define USB_DSTS_SuspSts_Pos                  0                                                       /*!< USB DSTS: SuspSts Position              */\r
+#define USB_DSTS_SuspSts_Msk                  (0x01UL << USB_DSTS_SuspSts_Pos)                        /*!< USB DSTS: SuspSts Mask                  */\r
+#define USB_DSTS_EnumSpd_Pos                  1                                                       /*!< USB DSTS: EnumSpd Position              */\r
+#define USB_DSTS_EnumSpd_Msk                  (0x03UL << USB_DSTS_EnumSpd_Pos)                        /*!< USB DSTS: EnumSpd Mask                  */\r
+#define USB_DSTS_ErrticErr_Pos                3                                                       /*!< USB DSTS: ErrticErr Position            */\r
+#define USB_DSTS_ErrticErr_Msk                (0x01UL << USB_DSTS_ErrticErr_Pos)                      /*!< USB DSTS: ErrticErr Mask                */\r
+#define USB_DSTS_SOFFN_Pos                    8                                                       /*!< USB DSTS: SOFFN Position                */\r
+#define USB_DSTS_SOFFN_Msk                    (0x00003fffUL << USB_DSTS_SOFFN_Pos)                    /*!< USB DSTS: SOFFN Mask                    */\r
+\r
+/* ---------------------------------  USB_DIEPMSK  -------------------------------- */\r
+#define USB_DIEPMSK_XferComplMsk_Pos          0                                                       /*!< USB DIEPMSK: XferComplMsk Position      */\r
+#define USB_DIEPMSK_XferComplMsk_Msk          (0x01UL << USB_DIEPMSK_XferComplMsk_Pos)                /*!< USB DIEPMSK: XferComplMsk Mask          */\r
+#define USB_DIEPMSK_EPDisbldMsk_Pos           1                                                       /*!< USB DIEPMSK: EPDisbldMsk Position       */\r
+#define USB_DIEPMSK_EPDisbldMsk_Msk           (0x01UL << USB_DIEPMSK_EPDisbldMsk_Pos)                 /*!< USB DIEPMSK: EPDisbldMsk Mask           */\r
+#define USB_DIEPMSK_AHBErrMsk_Pos             2                                                       /*!< USB DIEPMSK: AHBErrMsk Position         */\r
+#define USB_DIEPMSK_AHBErrMsk_Msk             (0x01UL << USB_DIEPMSK_AHBErrMsk_Pos)                   /*!< USB DIEPMSK: AHBErrMsk Mask             */\r
+#define USB_DIEPMSK_TimeOUTMsk_Pos            3                                                       /*!< USB DIEPMSK: TimeOUTMsk Position        */\r
+#define USB_DIEPMSK_TimeOUTMsk_Msk            (0x01UL << USB_DIEPMSK_TimeOUTMsk_Pos)                  /*!< USB DIEPMSK: TimeOUTMsk Mask            */\r
+#define USB_DIEPMSK_INTknTXFEmpMsk_Pos        4                                                       /*!< USB DIEPMSK: INTknTXFEmpMsk Position    */\r
+#define USB_DIEPMSK_INTknTXFEmpMsk_Msk        (0x01UL << USB_DIEPMSK_INTknTXFEmpMsk_Pos)              /*!< USB DIEPMSK: INTknTXFEmpMsk Mask        */\r
+#define USB_DIEPMSK_INEPNakEffMsk_Pos         6                                                       /*!< USB DIEPMSK: INEPNakEffMsk Position     */\r
+#define USB_DIEPMSK_INEPNakEffMsk_Msk         (0x01UL << USB_DIEPMSK_INEPNakEffMsk_Pos)               /*!< USB DIEPMSK: INEPNakEffMsk Mask         */\r
+#define USB_DIEPMSK_TxfifoUndrnMsk_Pos        8                                                       /*!< USB DIEPMSK: TxfifoUndrnMsk Position    */\r
+#define USB_DIEPMSK_TxfifoUndrnMsk_Msk        (0x01UL << USB_DIEPMSK_TxfifoUndrnMsk_Pos)              /*!< USB DIEPMSK: TxfifoUndrnMsk Mask        */\r
+#define USB_DIEPMSK_BNAInIntrMsk_Pos          9                                                       /*!< USB DIEPMSK: BNAInIntrMsk Position      */\r
+#define USB_DIEPMSK_BNAInIntrMsk_Msk          (0x01UL << USB_DIEPMSK_BNAInIntrMsk_Pos)                /*!< USB DIEPMSK: BNAInIntrMsk Mask          */\r
+#define USB_DIEPMSK_NAKMsk_Pos                13                                                      /*!< USB DIEPMSK: NAKMsk Position            */\r
+#define USB_DIEPMSK_NAKMsk_Msk                (0x01UL << USB_DIEPMSK_NAKMsk_Pos)                      /*!< USB DIEPMSK: NAKMsk Mask                */\r
+\r
+/* ---------------------------------  USB_DOEPMSK  -------------------------------- */\r
+#define USB_DOEPMSK_XferComplMsk_Pos          0                                                       /*!< USB DOEPMSK: XferComplMsk Position      */\r
+#define USB_DOEPMSK_XferComplMsk_Msk          (0x01UL << USB_DOEPMSK_XferComplMsk_Pos)                /*!< USB DOEPMSK: XferComplMsk Mask          */\r
+#define USB_DOEPMSK_EPDisbldMsk_Pos           1                                                       /*!< USB DOEPMSK: EPDisbldMsk Position       */\r
+#define USB_DOEPMSK_EPDisbldMsk_Msk           (0x01UL << USB_DOEPMSK_EPDisbldMsk_Pos)                 /*!< USB DOEPMSK: EPDisbldMsk Mask           */\r
+#define USB_DOEPMSK_AHBErrMsk_Pos             2                                                       /*!< USB DOEPMSK: AHBErrMsk Position         */\r
+#define USB_DOEPMSK_AHBErrMsk_Msk             (0x01UL << USB_DOEPMSK_AHBErrMsk_Pos)                   /*!< USB DOEPMSK: AHBErrMsk Mask             */\r
+#define USB_DOEPMSK_SetUPMsk_Pos              3                                                       /*!< USB DOEPMSK: SetUPMsk Position          */\r
+#define USB_DOEPMSK_SetUPMsk_Msk              (0x01UL << USB_DOEPMSK_SetUPMsk_Pos)                    /*!< USB DOEPMSK: SetUPMsk Mask              */\r
+#define USB_DOEPMSK_OUTTknEPdisMsk_Pos        4                                                       /*!< USB DOEPMSK: OUTTknEPdisMsk Position    */\r
+#define USB_DOEPMSK_OUTTknEPdisMsk_Msk        (0x01UL << USB_DOEPMSK_OUTTknEPdisMsk_Pos)              /*!< USB DOEPMSK: OUTTknEPdisMsk Mask        */\r
+#define USB_DOEPMSK_Back2BackSETup_Pos        6                                                       /*!< USB DOEPMSK: Back2BackSETup Position    */\r
+#define USB_DOEPMSK_Back2BackSETup_Msk        (0x01UL << USB_DOEPMSK_Back2BackSETup_Pos)              /*!< USB DOEPMSK: Back2BackSETup Mask        */\r
+#define USB_DOEPMSK_OutPktErrMsk_Pos          8                                                       /*!< USB DOEPMSK: OutPktErrMsk Position      */\r
+#define USB_DOEPMSK_OutPktErrMsk_Msk          (0x01UL << USB_DOEPMSK_OutPktErrMsk_Pos)                /*!< USB DOEPMSK: OutPktErrMsk Mask          */\r
+#define USB_DOEPMSK_BnaOutIntrMsk_Pos         9                                                       /*!< USB DOEPMSK: BnaOutIntrMsk Position     */\r
+#define USB_DOEPMSK_BnaOutIntrMsk_Msk         (0x01UL << USB_DOEPMSK_BnaOutIntrMsk_Pos)               /*!< USB DOEPMSK: BnaOutIntrMsk Mask         */\r
+#define USB_DOEPMSK_BbleErrMsk_Pos            12                                                      /*!< USB DOEPMSK: BbleErrMsk Position        */\r
+#define USB_DOEPMSK_BbleErrMsk_Msk            (0x01UL << USB_DOEPMSK_BbleErrMsk_Pos)                  /*!< USB DOEPMSK: BbleErrMsk Mask            */\r
+#define USB_DOEPMSK_NAKMsk_Pos                13                                                      /*!< USB DOEPMSK: NAKMsk Position            */\r
+#define USB_DOEPMSK_NAKMsk_Msk                (0x01UL << USB_DOEPMSK_NAKMsk_Pos)                      /*!< USB DOEPMSK: NAKMsk Mask                */\r
+#define USB_DOEPMSK_NYETMsk_Pos               14                                                      /*!< USB DOEPMSK: NYETMsk Position           */\r
+#define USB_DOEPMSK_NYETMsk_Msk               (0x01UL << USB_DOEPMSK_NYETMsk_Pos)                     /*!< USB DOEPMSK: NYETMsk Mask               */\r
+\r
+/* ----------------------------------  USB_DAINT  --------------------------------- */\r
+#define USB_DAINT_InEpInt_Pos                 0                                                       /*!< USB DAINT: InEpInt Position             */\r
+#define USB_DAINT_InEpInt_Msk                 (0x0000ffffUL << USB_DAINT_InEpInt_Pos)                 /*!< USB DAINT: InEpInt Mask                 */\r
+#define USB_DAINT_OutEPInt_Pos                16                                                      /*!< USB DAINT: OutEPInt Position            */\r
+#define USB_DAINT_OutEPInt_Msk                (0x0000ffffUL << USB_DAINT_OutEPInt_Pos)                /*!< USB DAINT: OutEPInt Mask                */\r
+\r
+/* --------------------------------  USB_DAINTMSK  -------------------------------- */\r
+#define USB_DAINTMSK_InEpMsk_Pos              0                                                       /*!< USB DAINTMSK: InEpMsk Position          */\r
+#define USB_DAINTMSK_InEpMsk_Msk              (0x0000ffffUL << USB_DAINTMSK_InEpMsk_Pos)              /*!< USB DAINTMSK: InEpMsk Mask              */\r
+#define USB_DAINTMSK_OutEpMsk_Pos             16                                                      /*!< USB DAINTMSK: OutEpMsk Position         */\r
+#define USB_DAINTMSK_OutEpMsk_Msk             (0x0000ffffUL << USB_DAINTMSK_OutEpMsk_Pos)             /*!< USB DAINTMSK: OutEpMsk Mask             */\r
+\r
+/* --------------------------------  USB_DVBUSDIS  -------------------------------- */\r
+#define USB_DVBUSDIS_DVBUSDis_Pos             0                                                       /*!< USB DVBUSDIS: DVBUSDis Position         */\r
+#define USB_DVBUSDIS_DVBUSDis_Msk             (0x0000ffffUL << USB_DVBUSDIS_DVBUSDis_Pos)             /*!< USB DVBUSDIS: DVBUSDis Mask             */\r
+\r
+/* -------------------------------  USB_DVBUSPULSE  ------------------------------- */\r
+#define USB_DVBUSPULSE_DVBUSPulse_Pos         0                                                       /*!< USB DVBUSPULSE: DVBUSPulse Position     */\r
+#define USB_DVBUSPULSE_DVBUSPulse_Msk         (0x00000fffUL << USB_DVBUSPULSE_DVBUSPulse_Pos)         /*!< USB DVBUSPULSE: DVBUSPulse Mask         */\r
+\r
+/* -------------------------------  USB_DIEPEMPMSK  ------------------------------- */\r
+#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos      0                                                       /*!< USB DIEPEMPMSK: InEpTxfEmpMsk Position  */\r
+#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk      (0x0000ffffUL << USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos)      /*!< USB DIEPEMPMSK: InEpTxfEmpMsk Mask      */\r
+\r
+/* ---------------------------------  USB_PCGCCTL  -------------------------------- */\r
+#define USB_PCGCCTL_StopPclk_Pos              0                                                       /*!< USB PCGCCTL: StopPclk Position          */\r
+#define USB_PCGCCTL_StopPclk_Msk              (0x01UL << USB_PCGCCTL_StopPclk_Pos)                    /*!< USB PCGCCTL: StopPclk Mask              */\r
+#define USB_PCGCCTL_GateHclk_Pos              1                                                       /*!< USB PCGCCTL: GateHclk Position          */\r
+#define USB_PCGCCTL_GateHclk_Msk              (0x01UL << USB_PCGCCTL_GateHclk_Pos)                    /*!< USB PCGCCTL: GateHclk Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'USB0_EP0' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  USB_EP_DIEPCTL0  ----------------------------- */\r
+#define USB_EP_DIEPCTL0_MPS_Pos             0                                                       /*!< USB0_EP0 DIEPCTL0: MPS Position         */\r
+#define USB_EP_DIEPCTL0_MPS_Msk             (0x03UL << USB_EP_DIEPCTL0_MPS_Pos)                   /*!< USB0_EP0 DIEPCTL0: MPS Mask             */\r
+#define USB_EP_DIEPCTL0_USBActEP_Pos        15                                                      /*!< USB0_EP0 DIEPCTL0: USBActEP Position    */\r
+#define USB_EP_DIEPCTL0_USBActEP_Msk        (0x01UL << USB_EP_DIEPCTL0_USBActEP_Pos)              /*!< USB0_EP0 DIEPCTL0: USBActEP Mask        */\r
+#define USB_EP_DIEPCTL0_NAKSts_Pos          17                                                      /*!< USB0_EP0 DIEPCTL0: NAKSts Position      */\r
+#define USB_EP_DIEPCTL0_NAKSts_Msk          (0x01UL << USB_EP_DIEPCTL0_NAKSts_Pos)                /*!< USB0_EP0 DIEPCTL0: NAKSts Mask          */\r
+#define USB_EP_DIEPCTL0_EPType_Pos          18                                                      /*!< USB0_EP0 DIEPCTL0: EPType Position      */\r
+#define USB_EP_DIEPCTL0_EPType_Msk          (0x03UL << USB_EP_DIEPCTL0_EPType_Pos)                /*!< USB0_EP0 DIEPCTL0: EPType Mask          */\r
+#define USB_EP_DIEPCTL0_Stall_Pos           21                                                      /*!< USB0_EP0 DIEPCTL0: Stall Position       */\r
+#define USB_EP_DIEPCTL0_Stall_Msk           (0x01UL << USB_EP_DIEPCTL0_Stall_Pos)                 /*!< USB0_EP0 DIEPCTL0: Stall Mask           */\r
+#define USB_EP_DIEPCTL0_TxFNum_Pos          22                                                      /*!< USB0_EP0 DIEPCTL0: TxFNum Position      */\r
+#define USB_EP_DIEPCTL0_TxFNum_Msk          (0x0fUL << USB_EP_DIEPCTL0_TxFNum_Pos)                /*!< USB0_EP0 DIEPCTL0: TxFNum Mask          */\r
+#define USB_EP_DIEPCTL0_CNAK_Pos            26                                                      /*!< USB0_EP0 DIEPCTL0: CNAK Position        */\r
+#define USB_EP_DIEPCTL0_CNAK_Msk            (0x01UL << USB_EP_DIEPCTL0_CNAK_Pos)                  /*!< USB0_EP0 DIEPCTL0: CNAK Mask            */\r
+#define USB_EP_DIEPCTL0_SNAK_Pos            27                                                      /*!< USB0_EP0 DIEPCTL0: SNAK Position        */\r
+#define USB_EP_DIEPCTL0_SNAK_Msk            (0x01UL << USB_EP_DIEPCTL0_SNAK_Pos)                  /*!< USB0_EP0 DIEPCTL0: SNAK Mask            */\r
+#define USB_EP_DIEPCTL0_EPDis_Pos           30                                                      /*!< USB0_EP0 DIEPCTL0: EPDis Position       */\r
+#define USB_EP_DIEPCTL0_EPDis_Msk           (0x01UL << USB_EP_DIEPCTL0_EPDis_Pos)                 /*!< USB0_EP0 DIEPCTL0: EPDis Mask           */\r
+#define USB_EP_DIEPCTL0_EPEna_Pos           31                                                      /*!< USB0_EP0 DIEPCTL0: EPEna Position       */\r
+#define USB_EP_DIEPCTL0_EPEna_Msk           (0x01UL << USB_EP_DIEPCTL0_EPEna_Pos)                 /*!< USB0_EP0 DIEPCTL0: EPEna Mask           */\r
+\r
+/* ------------------------------  USB_EP_DIEPINT0  ----------------------------- */\r
+#define USB_EP_DIEPINT0_XferCompl_Pos       0                                                       /*!< USB0_EP0 DIEPINT0: XferCompl Position   */\r
+#define USB_EP_DIEPINT0_XferCompl_Msk       (0x01UL << USB_EP_DIEPINT0_XferCompl_Pos)             /*!< USB0_EP0 DIEPINT0: XferCompl Mask       */\r
+#define USB_EP_DIEPINT0_EPDisbld_Pos        1                                                       /*!< USB0_EP0 DIEPINT0: EPDisbld Position    */\r
+#define USB_EP_DIEPINT0_EPDisbld_Msk        (0x01UL << USB_EP_DIEPINT0_EPDisbld_Pos)              /*!< USB0_EP0 DIEPINT0: EPDisbld Mask        */\r
+#define USB_EP_DIEPINT0_AHBErr_Pos          2                                                       /*!< USB0_EP0 DIEPINT0: AHBErr Position      */\r
+#define USB_EP_DIEPINT0_AHBErr_Msk          (0x01UL << USB_EP_DIEPINT0_AHBErr_Pos)                /*!< USB0_EP0 DIEPINT0: AHBErr Mask          */\r
+#define USB_EP_DIEPINT0_TimeOUT_Pos         3                                                       /*!< USB0_EP0 DIEPINT0: TimeOUT Position     */\r
+#define USB_EP_DIEPINT0_TimeOUT_Msk         (0x01UL << USB_EP_DIEPINT0_TimeOUT_Pos)               /*!< USB0_EP0 DIEPINT0: TimeOUT Mask         */\r
+#define USB_EP_DIEPINT0_INTknTXFEmp_Pos     4                                                       /*!< USB0_EP0 DIEPINT0: INTknTXFEmp Position */\r
+#define USB_EP_DIEPINT0_INTknTXFEmp_Msk     (0x01UL << USB_EP_DIEPINT0_INTknTXFEmp_Pos)           /*!< USB0_EP0 DIEPINT0: INTknTXFEmp Mask     */\r
+#define USB_EP_DIEPINT0_INEPNakEff_Pos      6                                                       /*!< USB0_EP0 DIEPINT0: INEPNakEff Position  */\r
+#define USB_EP_DIEPINT0_INEPNakEff_Msk      (0x01UL << USB_EP_DIEPINT0_INEPNakEff_Pos)            /*!< USB0_EP0 DIEPINT0: INEPNakEff Mask      */\r
+#define USB_EP_DIEPINT0_TxFEmp_Pos          7                                                       /*!< USB0_EP0 DIEPINT0: TxFEmp Position      */\r
+#define USB_EP_DIEPINT0_TxFEmp_Msk          (0x01UL << USB_EP_DIEPINT0_TxFEmp_Pos)                /*!< USB0_EP0 DIEPINT0: TxFEmp Mask          */\r
+#define USB_EP_DIEPINT0_BNAIntr_Pos         9                                                       /*!< USB0_EP0 DIEPINT0: BNAIntr Position     */\r
+#define USB_EP_DIEPINT0_BNAIntr_Msk         (0x01UL << USB_EP_DIEPINT0_BNAIntr_Pos)               /*!< USB0_EP0 DIEPINT0: BNAIntr Mask         */\r
+\r
+/* -----------------------------  USB_EP_DIEPTSIZ0  ----------------------------- */\r
+#define USB_EP_DIEPTSIZ0_XferSize_Pos       0                                                       /*!< USB0_EP0 DIEPTSIZ0: XferSize Position   */\r
+#define USB_EP_DIEPTSIZ0_XferSize_Msk       (0x7fUL << USB_EP_DIEPTSIZ0_XferSize_Pos)             /*!< USB0_EP0 DIEPTSIZ0: XferSize Mask       */\r
+#define USB_EP_DIEPTSIZ0_PktCnt_Pos         19                                                      /*!< USB0_EP0 DIEPTSIZ0: PktCnt Position     */\r
+#define USB_EP_DIEPTSIZ0_PktCnt_Msk         (0x03UL << USB_EP_DIEPTSIZ0_PktCnt_Pos)               /*!< USB0_EP0 DIEPTSIZ0: PktCnt Mask         */\r
+\r
+/* ------------------------------  USB_EP_DIEPDMA0  ----------------------------- */\r
+#define USB_EP_DIEPDMA0_DMAAddr_Pos         0                                                       /*!< USB0_EP0 DIEPDMA0: DMAAddr Position     */\r
+#define USB_EP_DIEPDMA0_DMAAddr_Msk         (0xffffffffUL << USB_EP_DIEPDMA0_DMAAddr_Pos)         /*!< USB0_EP0 DIEPDMA0: DMAAddr Mask         */\r
+\r
+/* ------------------------------  USB_EP_DTXFSTS0  ----------------------------- */\r
+#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos 0                                                       /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail Position */\r
+#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk (0x0000ffffUL << USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail Mask */\r
+\r
+/* -----------------------------  USB_EP_DIEPDMAB0  ----------------------------- */\r
+#define USB_EP_DIEPDMAB0_DMABufferAddr_Pos  0                                                       /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr Position */\r
+#define USB_EP_DIEPDMAB0_DMABufferAddr_Msk  (0xffffffffUL << USB_EP_DIEPDMAB0_DMABufferAddr_Pos)  /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr Mask  */\r
+\r
+/* ------------------------------  USB_EP_DOEPCTL0  ----------------------------- */\r
+#define USB_EP_DOEPCTL0_MPS_Pos             0                                                       /*!< USB0_EP0 DOEPCTL0: MPS Position         */\r
+#define USB_EP_DOEPCTL0_MPS_Msk             (0x03UL << USB_EP_DOEPCTL0_MPS_Pos)                   /*!< USB0_EP0 DOEPCTL0: MPS Mask             */\r
+#define USB_EP_DOEPCTL0_USBActEP_Pos        15                                                      /*!< USB0_EP0 DOEPCTL0: USBActEP Position    */\r
+#define USB_EP_DOEPCTL0_USBActEP_Msk        (0x01UL << USB_EP_DOEPCTL0_USBActEP_Pos)              /*!< USB0_EP0 DOEPCTL0: USBActEP Mask        */\r
+#define USB_EP_DOEPCTL0_NAKSts_Pos          17                                                      /*!< USB0_EP0 DOEPCTL0: NAKSts Position      */\r
+#define USB_EP_DOEPCTL0_NAKSts_Msk          (0x01UL << USB_EP_DOEPCTL0_NAKSts_Pos)                /*!< USB0_EP0 DOEPCTL0: NAKSts Mask          */\r
+#define USB_EP_DOEPCTL0_EPType_Pos          18                                                      /*!< USB0_EP0 DOEPCTL0: EPType Position      */\r
+#define USB_EP_DOEPCTL0_EPType_Msk          (0x03UL << USB_EP_DOEPCTL0_EPType_Pos)                /*!< USB0_EP0 DOEPCTL0: EPType Mask          */\r
+#define USB_EP_DOEPCTL0_Snp_Pos             20                                                      /*!< USB0_EP0 DOEPCTL0: Snp Position         */\r
+#define USB_EP_DOEPCTL0_Snp_Msk             (0x01UL << USB_EP_DOEPCTL0_Snp_Pos)                   /*!< USB0_EP0 DOEPCTL0: Snp Mask             */\r
+#define USB_EP_DOEPCTL0_Stall_Pos           21                                                      /*!< USB0_EP0 DOEPCTL0: Stall Position       */\r
+#define USB_EP_DOEPCTL0_Stall_Msk           (0x01UL << USB_EP_DOEPCTL0_Stall_Pos)                 /*!< USB0_EP0 DOEPCTL0: Stall Mask           */\r
+#define USB_EP_DOEPCTL0_CNAK_Pos            26                                                      /*!< USB0_EP0 DOEPCTL0: CNAK Position        */\r
+#define USB_EP_DOEPCTL0_CNAK_Msk            (0x01UL << USB_EP_DOEPCTL0_CNAK_Pos)                  /*!< USB0_EP0 DOEPCTL0: CNAK Mask            */\r
+#define USB_EP_DOEPCTL0_SNAK_Pos            27                                                      /*!< USB0_EP0 DOEPCTL0: SNAK Position        */\r
+#define USB_EP_DOEPCTL0_SNAK_Msk            (0x01UL << USB_EP_DOEPCTL0_SNAK_Pos)                  /*!< USB0_EP0 DOEPCTL0: SNAK Mask            */\r
+#define USB_EP_DOEPCTL0_EPDis_Pos           30                                                      /*!< USB0_EP0 DOEPCTL0: EPDis Position       */\r
+#define USB_EP_DOEPCTL0_EPDis_Msk           (0x01UL << USB_EP_DOEPCTL0_EPDis_Pos)                 /*!< USB0_EP0 DOEPCTL0: EPDis Mask           */\r
+#define USB_EP_DOEPCTL0_EPEna_Pos           31                                                      /*!< USB0_EP0 DOEPCTL0: EPEna Position       */\r
+#define USB_EP_DOEPCTL0_EPEna_Msk           (0x01UL << USB_EP_DOEPCTL0_EPEna_Pos)                 /*!< USB0_EP0 DOEPCTL0: EPEna Mask           */\r
+\r
+/* ------------------------------  USB_EP_DOEPINT0  ----------------------------- */\r
+#define USB_EP_DOEPINT0_XferCompl_Pos       0                                                       /*!< USB0_EP0 DOEPINT0: XferCompl Position   */\r
+#define USB_EP_DOEPINT0_XferCompl_Msk       (0x01UL << USB_EP_DOEPINT0_XferCompl_Pos)             /*!< USB0_EP0 DOEPINT0: XferCompl Mask       */\r
+#define USB_EP_DOEPINT0_EPDisbld_Pos        1                                                       /*!< USB0_EP0 DOEPINT0: EPDisbld Position    */\r
+#define USB_EP_DOEPINT0_EPDisbld_Msk        (0x01UL << USB_EP_DOEPINT0_EPDisbld_Pos)              /*!< USB0_EP0 DOEPINT0: EPDisbld Mask        */\r
+#define USB_EP_DOEPINT0_AHBErr_Pos          2                                                       /*!< USB0_EP0 DOEPINT0: AHBErr Position      */\r
+#define USB_EP_DOEPINT0_AHBErr_Msk          (0x01UL << USB_EP_DOEPINT0_AHBErr_Pos)                /*!< USB0_EP0 DOEPINT0: AHBErr Mask          */\r
+#define USB_EP_DOEPINT0_SetUp_Pos           3                                                       /*!< USB0_EP0 DOEPINT0: SetUp Position       */\r
+#define USB_EP_DOEPINT0_SetUp_Msk           (0x01UL << USB_EP_DOEPINT0_SetUp_Pos)                 /*!< USB0_EP0 DOEPINT0: SetUp Mask           */\r
+#define USB_EP_DOEPINT0_OUTTknEPdis_Pos     4                                                       /*!< USB0_EP0 DOEPINT0: OUTTknEPdis Position */\r
+#define USB_EP_DOEPINT0_OUTTknEPdis_Msk     (0x01UL << USB_EP_DOEPINT0_OUTTknEPdis_Pos)           /*!< USB0_EP0 DOEPINT0: OUTTknEPdis Mask     */\r
+#define USB_EP_DOEPINT0_StsPhseRcvd_Pos     5                                                       /*!< USB0_EP0 DOEPINT0: StsPhseRcvd Position */\r
+#define USB_EP_DOEPINT0_StsPhseRcvd_Msk     (0x01UL << USB_EP_DOEPINT0_StsPhseRcvd_Pos)           /*!< USB0_EP0 DOEPINT0: StsPhseRcvd Mask     */\r
+#define USB_EP_DOEPINT0_Back2BackSETup_Pos  6                                                       /*!< USB0_EP0 DOEPINT0: Back2BackSETup Position */\r
+#define USB_EP_DOEPINT0_Back2BackSETup_Msk  (0x01UL << USB_EP_DOEPINT0_Back2BackSETup_Pos)        /*!< USB0_EP0 DOEPINT0: Back2BackSETup Mask  */\r
+#define USB_EP_DOEPINT0_BNAIntr_Pos         9                                                       /*!< USB0_EP0 DOEPINT0: BNAIntr Position     */\r
+#define USB_EP_DOEPINT0_BNAIntr_Msk         (0x01UL << USB_EP_DOEPINT0_BNAIntr_Pos)               /*!< USB0_EP0 DOEPINT0: BNAIntr Mask         */\r
+#define USB_EP_DOEPINT0_PktDrpSts_Pos       11                                                      /*!< USB0_EP0 DOEPINT0: PktDrpSts Position   */\r
+#define USB_EP_DOEPINT0_PktDrpSts_Msk       (0x01UL << USB_EP_DOEPINT0_PktDrpSts_Pos)             /*!< USB0_EP0 DOEPINT0: PktDrpSts Mask       */\r
+#define USB_EP_DOEPINT0_BbleErrIntrpt_Pos   12                                                      /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt Position */\r
+#define USB_EP_DOEPINT0_BbleErrIntrpt_Msk   (0x01UL << USB_EP_DOEPINT0_BbleErrIntrpt_Pos)         /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt Mask   */\r
+#define USB_EP_DOEPINT0_NAKIntrpt_Pos       13                                                      /*!< USB0_EP0 DOEPINT0: NAKIntrpt Position   */\r
+#define USB_EP_DOEPINT0_NAKIntrpt_Msk       (0x01UL << USB_EP_DOEPINT0_NAKIntrpt_Pos)             /*!< USB0_EP0 DOEPINT0: NAKIntrpt Mask       */\r
+#define USB_EP_DOEPINT0_NYETIntrpt_Pos      14                                                      /*!< USB0_EP0 DOEPINT0: NYETIntrpt Position  */\r
+#define USB_EP_DOEPINT0_NYETIntrpt_Msk      (0x01UL << USB_EP_DOEPINT0_NYETIntrpt_Pos)            /*!< USB0_EP0 DOEPINT0: NYETIntrpt Mask      */\r
+\r
+/* -----------------------------  USB_EP_DOEPTSIZ0  ----------------------------- */\r
+#define USB_EP_DOEPTSIZ0_XferSize_Pos       0                                                       /*!< USB0_EP0 DOEPTSIZ0: XferSize Position   */\r
+#define USB_EP_DOEPTSIZ0_XferSize_Msk       (0x7fUL << USB_EP_DOEPTSIZ0_XferSize_Pos)             /*!< USB0_EP0 DOEPTSIZ0: XferSize Mask       */\r
+#define USB_EP_DOEPTSIZ0_PktCnt_Pos         19                                                      /*!< USB0_EP0 DOEPTSIZ0: PktCnt Position     */\r
+#define USB_EP_DOEPTSIZ0_PktCnt_Msk         (0x03UL << USB_EP_DOEPTSIZ0_PktCnt_Pos)               /*!< USB0_EP0 DOEPTSIZ0: PktCnt Mask         */\r
+#define USB_EP_DOEPTSIZ0_SUPCnt_Pos         29                                                      /*!< USB0_EP0 DOEPTSIZ0: SUPCnt Position     */\r
+#define USB_EP_DOEPTSIZ0_SUPCnt_Msk         (0x03UL << USB_EP_DOEPTSIZ0_SUPCnt_Pos)               /*!< USB0_EP0 DOEPTSIZ0: SUPCnt Mask         */\r
+\r
+/* ------------------------------  USB_EP_DOEPDMA0  ----------------------------- */\r
+#define USB_EP_DOEPDMA0_DMAAddr_Pos         0                                                       /*!< USB0_EP0 DOEPDMA0: DMAAddr Position     */\r
+#define USB_EP_DOEPDMA0_DMAAddr_Msk         (0xffffffffUL << USB_EP_DOEPDMA0_DMAAddr_Pos)         /*!< USB0_EP0 DOEPDMA0: DMAAddr Mask         */\r
+\r
+/* -----------------------------  USB_EP_DOEPDMAB0  ----------------------------- */\r
+#define USB_EP_DOEPDMAB0_DMABufferAddr_Pos  0                                                       /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr Position */\r
+#define USB_EP_DOEPDMAB0_DMABufferAddr_Msk  (0xffffffffUL << USB_EP_DOEPDMAB0_DMABufferAddr_Pos)  /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr Mask  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'USB_EP' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------  USB_EP_DIEPCTL_ISOCONT  --------------------------- */\r
+#define USB_EP_DIEPCTL_ISOCONT_MPS_Pos        0                                                       /*!< USB_EP DIEPCTL_ISOCONT: MPS Position    */\r
+#define USB_EP_DIEPCTL_ISOCONT_MPS_Msk        (0x000007ffUL << USB_EP_DIEPCTL_ISOCONT_MPS_Pos)        /*!< USB_EP DIEPCTL_ISOCONT: MPS Mask        */\r
+#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos   15                                                      /*!< USB_EP DIEPCTL_ISOCONT: USBActEP Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk   (0x01UL << USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos)         /*!< USB_EP DIEPCTL_ISOCONT: USBActEP Mask   */\r
+#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos   16                                                      /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk   (0x01UL << USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos)         /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum Mask   */\r
+#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos     17                                                      /*!< USB_EP DIEPCTL_ISOCONT: NAKSts Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk     (0x01UL << USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos)           /*!< USB_EP DIEPCTL_ISOCONT: NAKSts Mask     */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPType_Pos     18                                                      /*!< USB_EP DIEPCTL_ISOCONT: EPType Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPType_Msk     (0x03UL << USB_EP_DIEPCTL_ISOCONT_EPType_Pos)           /*!< USB_EP DIEPCTL_ISOCONT: EPType Mask     */\r
+#define USB_EP_DIEPCTL_ISOCONT_Snp_Pos        20                                                      /*!< USB_EP DIEPCTL_ISOCONT: Snp Position    */\r
+#define USB_EP_DIEPCTL_ISOCONT_Snp_Msk        (0x01UL << USB_EP_DIEPCTL_ISOCONT_Snp_Pos)              /*!< USB_EP DIEPCTL_ISOCONT: Snp Mask        */\r
+#define USB_EP_DIEPCTL_ISOCONT_Stall_Pos      21                                                      /*!< USB_EP DIEPCTL_ISOCONT: Stall Position  */\r
+#define USB_EP_DIEPCTL_ISOCONT_Stall_Msk      (0x01UL << USB_EP_DIEPCTL_ISOCONT_Stall_Pos)            /*!< USB_EP DIEPCTL_ISOCONT: Stall Mask      */\r
+#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos     22                                                      /*!< USB_EP DIEPCTL_ISOCONT: TxFNum Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk     (0x0fUL << USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos)           /*!< USB_EP DIEPCTL_ISOCONT: TxFNum Mask     */\r
+#define USB_EP_DIEPCTL_ISOCONT_CNAK_Pos       26                                                      /*!< USB_EP DIEPCTL_ISOCONT: CNAK Position   */\r
+#define USB_EP_DIEPCTL_ISOCONT_CNAK_Msk       (0x01UL << USB_EP_DIEPCTL_ISOCONT_CNAK_Pos)             /*!< USB_EP DIEPCTL_ISOCONT: CNAK Mask       */\r
+#define USB_EP_DIEPCTL_ISOCONT_SNAK_Pos       27                                                      /*!< USB_EP DIEPCTL_ISOCONT: SNAK Position   */\r
+#define USB_EP_DIEPCTL_ISOCONT_SNAK_Msk       (0x01UL << USB_EP_DIEPCTL_ISOCONT_SNAK_Pos)             /*!< USB_EP DIEPCTL_ISOCONT: SNAK Mask       */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos  28                                                      /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk  (0x01UL << USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos)        /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr Mask  */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos   29                                                      /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk   (0x01UL << USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos)         /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr Mask   */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPDis_Pos      30                                                      /*!< USB_EP DIEPCTL_ISOCONT: EPDis Position  */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPDis_Msk      (0x01UL << USB_EP_DIEPCTL_ISOCONT_EPDis_Pos)            /*!< USB_EP DIEPCTL_ISOCONT: EPDis Mask      */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPEna_Pos      31                                                      /*!< USB_EP DIEPCTL_ISOCONT: EPEna Position  */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPEna_Msk      (0x01UL << USB_EP_DIEPCTL_ISOCONT_EPEna_Pos)            /*!< USB_EP DIEPCTL_ISOCONT: EPEna Mask      */\r
+\r
+/* ---------------------------  USB_EP_DIEPCTL_INTBULK  --------------------------- */\r
+#define USB_EP_DIEPCTL_INTBULK_MPS_Pos        0                                                       /*!< USB_EP DIEPCTL_INTBULK: MPS Position    */\r
+#define USB_EP_DIEPCTL_INTBULK_MPS_Msk        (0x000007ffUL << USB_EP_DIEPCTL_INTBULK_MPS_Pos)        /*!< USB_EP DIEPCTL_INTBULK: MPS Mask        */\r
+#define USB_EP_DIEPCTL_INTBULK_USBActEP_Pos   15                                                      /*!< USB_EP DIEPCTL_INTBULK: USBActEP Position */\r
+#define USB_EP_DIEPCTL_INTBULK_USBActEP_Msk   (0x01UL << USB_EP_DIEPCTL_INTBULK_USBActEP_Pos)         /*!< USB_EP DIEPCTL_INTBULK: USBActEP Mask   */\r
+#define USB_EP_DIEPCTL_INTBULK_DPID_Pos       16                                                      /*!< USB_EP DIEPCTL_INTBULK: DPID Position   */\r
+#define USB_EP_DIEPCTL_INTBULK_DPID_Msk       (0x01UL << USB_EP_DIEPCTL_INTBULK_DPID_Pos)             /*!< USB_EP DIEPCTL_INTBULK: DPID Mask       */\r
+#define USB_EP_DIEPCTL_INTBULK_NAKSts_Pos     17                                                      /*!< USB_EP DIEPCTL_INTBULK: NAKSts Position */\r
+#define USB_EP_DIEPCTL_INTBULK_NAKSts_Msk     (0x01UL << USB_EP_DIEPCTL_INTBULK_NAKSts_Pos)           /*!< USB_EP DIEPCTL_INTBULK: NAKSts Mask     */\r
+#define USB_EP_DIEPCTL_INTBULK_EPType_Pos     18                                                      /*!< USB_EP DIEPCTL_INTBULK: EPType Position */\r
+#define USB_EP_DIEPCTL_INTBULK_EPType_Msk     (0x03UL << USB_EP_DIEPCTL_INTBULK_EPType_Pos)           /*!< USB_EP DIEPCTL_INTBULK: EPType Mask     */\r
+#define USB_EP_DIEPCTL_INTBULK_Snp_Pos        20                                                      /*!< USB_EP DIEPCTL_INTBULK: Snp Position    */\r
+#define USB_EP_DIEPCTL_INTBULK_Snp_Msk        (0x01UL << USB_EP_DIEPCTL_INTBULK_Snp_Pos)              /*!< USB_EP DIEPCTL_INTBULK: Snp Mask        */\r
+#define USB_EP_DIEPCTL_INTBULK_Stall_Pos      21                                                      /*!< USB_EP DIEPCTL_INTBULK: Stall Position  */\r
+#define USB_EP_DIEPCTL_INTBULK_Stall_Msk      (0x01UL << USB_EP_DIEPCTL_INTBULK_Stall_Pos)            /*!< USB_EP DIEPCTL_INTBULK: Stall Mask      */\r
+#define USB_EP_DIEPCTL_INTBULK_TxFNum_Pos     22                                                      /*!< USB_EP DIEPCTL_INTBULK: TxFNum Position */\r
+#define USB_EP_DIEPCTL_INTBULK_TxFNum_Msk     (0x0fUL << USB_EP_DIEPCTL_INTBULK_TxFNum_Pos)           /*!< USB_EP DIEPCTL_INTBULK: TxFNum Mask     */\r
+#define USB_EP_DIEPCTL_INTBULK_CNAK_Pos       26                                                      /*!< USB_EP DIEPCTL_INTBULK: CNAK Position   */\r
+#define USB_EP_DIEPCTL_INTBULK_CNAK_Msk       (0x01UL << USB_EP_DIEPCTL_INTBULK_CNAK_Pos)             /*!< USB_EP DIEPCTL_INTBULK: CNAK Mask       */\r
+#define USB_EP_DIEPCTL_INTBULK_SNAK_Pos       27                                                      /*!< USB_EP DIEPCTL_INTBULK: SNAK Position   */\r
+#define USB_EP_DIEPCTL_INTBULK_SNAK_Msk       (0x01UL << USB_EP_DIEPCTL_INTBULK_SNAK_Pos)             /*!< USB_EP DIEPCTL_INTBULK: SNAK Mask       */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos   28                                                      /*!< USB_EP DIEPCTL_INTBULK: SetD0PID Position */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk   (0x01UL << USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos)         /*!< USB_EP DIEPCTL_INTBULK: SetD0PID Mask   */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos   29                                                      /*!< USB_EP DIEPCTL_INTBULK: SetD1PID Position */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk   (0x01UL << USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos)         /*!< USB_EP DIEPCTL_INTBULK: SetD1PID Mask   */\r
+#define USB_EP_DIEPCTL_INTBULK_EPDis_Pos      30                                                      /*!< USB_EP DIEPCTL_INTBULK: EPDis Position  */\r
+#define USB_EP_DIEPCTL_INTBULK_EPDis_Msk      (0x01UL << USB_EP_DIEPCTL_INTBULK_EPDis_Pos)            /*!< USB_EP DIEPCTL_INTBULK: EPDis Mask      */\r
+#define USB_EP_DIEPCTL_INTBULK_EPEna_Pos      31                                                      /*!< USB_EP DIEPCTL_INTBULK: EPEna Position  */\r
+#define USB_EP_DIEPCTL_INTBULK_EPEna_Msk      (0x01UL << USB_EP_DIEPCTL_INTBULK_EPEna_Pos)            /*!< USB_EP DIEPCTL_INTBULK: EPEna Mask      */\r
+\r
+/* -------------------------------  USB_EP_DIEPINT  ------------------------------- */\r
+#define USB_EP_DIEPINT_XferCompl_Pos          0                                                       /*!< USB_EP DIEPINT: XferCompl Position      */\r
+#define USB_EP_DIEPINT_XferCompl_Msk          (0x01UL << USB_EP_DIEPINT_XferCompl_Pos)                /*!< USB_EP DIEPINT: XferCompl Mask          */\r
+#define USB_EP_DIEPINT_EPDisbld_Pos           1                                                       /*!< USB_EP DIEPINT: EPDisbld Position       */\r
+#define USB_EP_DIEPINT_EPDisbld_Msk           (0x01UL << USB_EP_DIEPINT_EPDisbld_Pos)                 /*!< USB_EP DIEPINT: EPDisbld Mask           */\r
+#define USB_EP_DIEPINT_AHBErr_Pos             2                                                       /*!< USB_EP DIEPINT: AHBErr Position         */\r
+#define USB_EP_DIEPINT_AHBErr_Msk             (0x01UL << USB_EP_DIEPINT_AHBErr_Pos)                   /*!< USB_EP DIEPINT: AHBErr Mask             */\r
+#define USB_EP_DIEPINT_TimeOUT_Pos            3                                                       /*!< USB_EP DIEPINT: TimeOUT Position        */\r
+#define USB_EP_DIEPINT_TimeOUT_Msk            (0x01UL << USB_EP_DIEPINT_TimeOUT_Pos)                  /*!< USB_EP DIEPINT: TimeOUT Mask            */\r
+#define USB_EP_DIEPINT_INTknTXFEmp_Pos        4                                                       /*!< USB_EP DIEPINT: INTknTXFEmp Position    */\r
+#define USB_EP_DIEPINT_INTknTXFEmp_Msk        (0x01UL << USB_EP_DIEPINT_INTknTXFEmp_Pos)              /*!< USB_EP DIEPINT: INTknTXFEmp Mask        */\r
+#define USB_EP_DIEPINT_INEPNakEff_Pos         6                                                       /*!< USB_EP DIEPINT: INEPNakEff Position     */\r
+#define USB_EP_DIEPINT_INEPNakEff_Msk         (0x01UL << USB_EP_DIEPINT_INEPNakEff_Pos)               /*!< USB_EP DIEPINT: INEPNakEff Mask         */\r
+#define USB_EP_DIEPINT_TxFEmp_Pos             7                                                       /*!< USB_EP DIEPINT: TxFEmp Position         */\r
+#define USB_EP_DIEPINT_TxFEmp_Msk             (0x01UL << USB_EP_DIEPINT_TxFEmp_Pos)                   /*!< USB_EP DIEPINT: TxFEmp Mask             */\r
+#define USB_EP_DIEPINT_BNAIntr_Pos            9                                                       /*!< USB_EP DIEPINT: BNAIntr Position        */\r
+#define USB_EP_DIEPINT_BNAIntr_Msk            (0x01UL << USB_EP_DIEPINT_BNAIntr_Pos)                  /*!< USB_EP DIEPINT: BNAIntr Mask            */\r
+\r
+/* -------------------------------  USB_EP_DIEPTSIZ  ------------------------------ */\r
+#define USB_EP_DIEPTSIZ_XferSize_Pos          0                                                       /*!< USB_EP DIEPTSIZ: XferSize Position      */\r
+#define USB_EP_DIEPTSIZ_XferSize_Msk          (0x0007ffffUL << USB_EP_DIEPTSIZ_XferSize_Pos)          /*!< USB_EP DIEPTSIZ: XferSize Mask          */\r
+#define USB_EP_DIEPTSIZ_PktCnt_Pos            19                                                      /*!< USB_EP DIEPTSIZ: PktCnt Position        */\r
+#define USB_EP_DIEPTSIZ_PktCnt_Msk            (0x000003ffUL << USB_EP_DIEPTSIZ_PktCnt_Pos)            /*!< USB_EP DIEPTSIZ: PktCnt Mask            */\r
+\r
+/* -------------------------------  USB_EP_DIEPDMA  ------------------------------- */\r
+#define USB_EP_DIEPDMA_DMAAddr_Pos            0                                                       /*!< USB_EP DIEPDMA: DMAAddr Position        */\r
+#define USB_EP_DIEPDMA_DMAAddr_Msk            (0xffffffffUL << USB_EP_DIEPDMA_DMAAddr_Pos)            /*!< USB_EP DIEPDMA: DMAAddr Mask            */\r
+\r
+/* -------------------------------  USB_EP_DTXFSTS  ------------------------------- */\r
+#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos    0                                                       /*!< USB_EP DTXFSTS: INEPTxFSpcAvail Position */\r
+#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk    (0x0000ffffUL << USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos)    /*!< USB_EP DTXFSTS: INEPTxFSpcAvail Mask    */\r
+\r
+/* -------------------------------  USB_EP_DIEPDMAB  ------------------------------ */\r
+#define USB_EP_DIEPDMAB_DMABufferAddr_Pos     0                                                       /*!< USB_EP DIEPDMAB: DMABufferAddr Position */\r
+#define USB_EP_DIEPDMAB_DMABufferAddr_Msk     (0xffffffffUL << USB_EP_DIEPDMAB_DMABufferAddr_Pos)     /*!< USB_EP DIEPDMAB: DMABufferAddr Mask     */\r
+\r
+/* ---------------------------  USB_EP_DOEPCTL_ISOCONT  --------------------------- */\r
+#define USB_EP_DOEPCTL_ISOCONT_MPS_Pos        0                                                       /*!< USB_EP DOEPCTL_ISOCONT: MPS Position    */\r
+#define USB_EP_DOEPCTL_ISOCONT_MPS_Msk        (0x000007ffUL << USB_EP_DOEPCTL_ISOCONT_MPS_Pos)        /*!< USB_EP DOEPCTL_ISOCONT: MPS Mask        */\r
+#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos   15                                                      /*!< USB_EP DOEPCTL_ISOCONT: USBActEP Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk   (0x01UL << USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos)         /*!< USB_EP DOEPCTL_ISOCONT: USBActEP Mask   */\r
+#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos   16                                                      /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk   (0x01UL << USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos)         /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum Mask   */\r
+#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos     17                                                      /*!< USB_EP DOEPCTL_ISOCONT: NAKSts Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk     (0x01UL << USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos)           /*!< USB_EP DOEPCTL_ISOCONT: NAKSts Mask     */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPType_Pos     18                                                      /*!< USB_EP DOEPCTL_ISOCONT: EPType Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPType_Msk     (0x03UL << USB_EP_DOEPCTL_ISOCONT_EPType_Pos)           /*!< USB_EP DOEPCTL_ISOCONT: EPType Mask     */\r
+#define USB_EP_DOEPCTL_ISOCONT_Snp_Pos        20                                                      /*!< USB_EP DOEPCTL_ISOCONT: Snp Position    */\r
+#define USB_EP_DOEPCTL_ISOCONT_Snp_Msk        (0x01UL << USB_EP_DOEPCTL_ISOCONT_Snp_Pos)              /*!< USB_EP DOEPCTL_ISOCONT: Snp Mask        */\r
+#define USB_EP_DOEPCTL_ISOCONT_Stall_Pos      21                                                      /*!< USB_EP DOEPCTL_ISOCONT: Stall Position  */\r
+#define USB_EP_DOEPCTL_ISOCONT_Stall_Msk      (0x01UL << USB_EP_DOEPCTL_ISOCONT_Stall_Pos)            /*!< USB_EP DOEPCTL_ISOCONT: Stall Mask      */\r
+#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos     22                                                      /*!< USB_EP DOEPCTL_ISOCONT: TxFNum Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk     (0x0fUL << USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos)           /*!< USB_EP DOEPCTL_ISOCONT: TxFNum Mask     */\r
+#define USB_EP_DOEPCTL_ISOCONT_CNAK_Pos       26                                                      /*!< USB_EP DOEPCTL_ISOCONT: CNAK Position   */\r
+#define USB_EP_DOEPCTL_ISOCONT_CNAK_Msk       (0x01UL << USB_EP_DOEPCTL_ISOCONT_CNAK_Pos)             /*!< USB_EP DOEPCTL_ISOCONT: CNAK Mask       */\r
+#define USB_EP_DOEPCTL_ISOCONT_SNAK_Pos       27                                                      /*!< USB_EP DOEPCTL_ISOCONT: SNAK Position   */\r
+#define USB_EP_DOEPCTL_ISOCONT_SNAK_Msk       (0x01UL << USB_EP_DOEPCTL_ISOCONT_SNAK_Pos)             /*!< USB_EP DOEPCTL_ISOCONT: SNAK Mask       */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos  28                                                      /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk  (0x01UL << USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos)        /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr Mask  */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos   29                                                      /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk   (0x01UL << USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos)         /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr Mask   */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPDis_Pos      30                                                      /*!< USB_EP DOEPCTL_ISOCONT: EPDis Position  */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPDis_Msk      (0x01UL << USB_EP_DOEPCTL_ISOCONT_EPDis_Pos)            /*!< USB_EP DOEPCTL_ISOCONT: EPDis Mask      */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPEna_Pos      31                                                      /*!< USB_EP DOEPCTL_ISOCONT: EPEna Position  */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPEna_Msk      (0x01UL << USB_EP_DOEPCTL_ISOCONT_EPEna_Pos)            /*!< USB_EP DOEPCTL_ISOCONT: EPEna Mask      */\r
+\r
+/* ---------------------------  USB_EP_DOEPCTL_INTBULK  --------------------------- */\r
+#define USB_EP_DOEPCTL_INTBULK_MPS_Pos        0                                                       /*!< USB_EP DOEPCTL_INTBULK: MPS Position    */\r
+#define USB_EP_DOEPCTL_INTBULK_MPS_Msk        (0x000007ffUL << USB_EP_DOEPCTL_INTBULK_MPS_Pos)        /*!< USB_EP DOEPCTL_INTBULK: MPS Mask        */\r
+#define USB_EP_DOEPCTL_INTBULK_USBActEP_Pos   15                                                      /*!< USB_EP DOEPCTL_INTBULK: USBActEP Position */\r
+#define USB_EP_DOEPCTL_INTBULK_USBActEP_Msk   (0x01UL << USB_EP_DOEPCTL_INTBULK_USBActEP_Pos)         /*!< USB_EP DOEPCTL_INTBULK: USBActEP Mask   */\r
+#define USB_EP_DOEPCTL_INTBULK_DPID_Pos       16                                                      /*!< USB_EP DOEPCTL_INTBULK: DPID Position   */\r
+#define USB_EP_DOEPCTL_INTBULK_DPID_Msk       (0x01UL << USB_EP_DOEPCTL_INTBULK_DPID_Pos)             /*!< USB_EP DOEPCTL_INTBULK: DPID Mask       */\r
+#define USB_EP_DOEPCTL_INTBULK_NAKSts_Pos     17                                                      /*!< USB_EP DOEPCTL_INTBULK: NAKSts Position */\r
+#define USB_EP_DOEPCTL_INTBULK_NAKSts_Msk     (0x01UL << USB_EP_DOEPCTL_INTBULK_NAKSts_Pos)           /*!< USB_EP DOEPCTL_INTBULK: NAKSts Mask     */\r
+#define USB_EP_DOEPCTL_INTBULK_EPType_Pos     18                                                      /*!< USB_EP DOEPCTL_INTBULK: EPType Position */\r
+#define USB_EP_DOEPCTL_INTBULK_EPType_Msk     (0x03UL << USB_EP_DOEPCTL_INTBULK_EPType_Pos)           /*!< USB_EP DOEPCTL_INTBULK: EPType Mask     */\r
+#define USB_EP_DOEPCTL_INTBULK_Snp_Pos        20                                                      /*!< USB_EP DOEPCTL_INTBULK: Snp Position    */\r
+#define USB_EP_DOEPCTL_INTBULK_Snp_Msk        (0x01UL << USB_EP_DOEPCTL_INTBULK_Snp_Pos)              /*!< USB_EP DOEPCTL_INTBULK: Snp Mask        */\r
+#define USB_EP_DOEPCTL_INTBULK_Stall_Pos      21                                                      /*!< USB_EP DOEPCTL_INTBULK: Stall Position  */\r
+#define USB_EP_DOEPCTL_INTBULK_Stall_Msk      (0x01UL << USB_EP_DOEPCTL_INTBULK_Stall_Pos)            /*!< USB_EP DOEPCTL_INTBULK: Stall Mask      */\r
+#define USB_EP_DOEPCTL_INTBULK_TxFNum_Pos     22                                                      /*!< USB_EP DOEPCTL_INTBULK: TxFNum Position */\r
+#define USB_EP_DOEPCTL_INTBULK_TxFNum_Msk     (0x0fUL << USB_EP_DOEPCTL_INTBULK_TxFNum_Pos)           /*!< USB_EP DOEPCTL_INTBULK: TxFNum Mask     */\r
+#define USB_EP_DOEPCTL_INTBULK_CNAK_Pos       26                                                      /*!< USB_EP DOEPCTL_INTBULK: CNAK Position   */\r
+#define USB_EP_DOEPCTL_INTBULK_CNAK_Msk       (0x01UL << USB_EP_DOEPCTL_INTBULK_CNAK_Pos)             /*!< USB_EP DOEPCTL_INTBULK: CNAK Mask       */\r
+#define USB_EP_DOEPCTL_INTBULK_SNAK_Pos       27                                                      /*!< USB_EP DOEPCTL_INTBULK: SNAK Position   */\r
+#define USB_EP_DOEPCTL_INTBULK_SNAK_Msk       (0x01UL << USB_EP_DOEPCTL_INTBULK_SNAK_Pos)             /*!< USB_EP DOEPCTL_INTBULK: SNAK Mask       */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos   28                                                      /*!< USB_EP DOEPCTL_INTBULK: SetD0PID Position */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk   (0x01UL << USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos)         /*!< USB_EP DOEPCTL_INTBULK: SetD0PID Mask   */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos   29                                                      /*!< USB_EP DOEPCTL_INTBULK: SetD1PID Position */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk   (0x01UL << USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos)         /*!< USB_EP DOEPCTL_INTBULK: SetD1PID Mask   */\r
+#define USB_EP_DOEPCTL_INTBULK_EPDis_Pos      30                                                      /*!< USB_EP DOEPCTL_INTBULK: EPDis Position  */\r
+#define USB_EP_DOEPCTL_INTBULK_EPDis_Msk      (0x01UL << USB_EP_DOEPCTL_INTBULK_EPDis_Pos)            /*!< USB_EP DOEPCTL_INTBULK: EPDis Mask      */\r
+#define USB_EP_DOEPCTL_INTBULK_EPEna_Pos      31                                                      /*!< USB_EP DOEPCTL_INTBULK: EPEna Position  */\r
+#define USB_EP_DOEPCTL_INTBULK_EPEna_Msk      (0x01UL << USB_EP_DOEPCTL_INTBULK_EPEna_Pos)            /*!< USB_EP DOEPCTL_INTBULK: EPEna Mask      */\r
+\r
+/* -------------------------------  USB_EP_DOEPINT  ------------------------------- */\r
+#define USB_EP_DOEPINT_XferCompl_Pos          0                                                       /*!< USB_EP DOEPINT: XferCompl Position      */\r
+#define USB_EP_DOEPINT_XferCompl_Msk          (0x01UL << USB_EP_DOEPINT_XferCompl_Pos)                /*!< USB_EP DOEPINT: XferCompl Mask          */\r
+#define USB_EP_DOEPINT_EPDisbld_Pos           1                                                       /*!< USB_EP DOEPINT: EPDisbld Position       */\r
+#define USB_EP_DOEPINT_EPDisbld_Msk           (0x01UL << USB_EP_DOEPINT_EPDisbld_Pos)                 /*!< USB_EP DOEPINT: EPDisbld Mask           */\r
+#define USB_EP_DOEPINT_AHBErr_Pos             2                                                       /*!< USB_EP DOEPINT: AHBErr Position         */\r
+#define USB_EP_DOEPINT_AHBErr_Msk             (0x01UL << USB_EP_DOEPINT_AHBErr_Pos)                   /*!< USB_EP DOEPINT: AHBErr Mask             */\r
+#define USB_EP_DOEPINT_SetUp_Pos              3                                                       /*!< USB_EP DOEPINT: SetUp Position          */\r
+#define USB_EP_DOEPINT_SetUp_Msk              (0x01UL << USB_EP_DOEPINT_SetUp_Pos)                    /*!< USB_EP DOEPINT: SetUp Mask              */\r
+#define USB_EP_DOEPINT_OUTTknEPdis_Pos        4                                                       /*!< USB_EP DOEPINT: OUTTknEPdis Position    */\r
+#define USB_EP_DOEPINT_OUTTknEPdis_Msk        (0x01UL << USB_EP_DOEPINT_OUTTknEPdis_Pos)              /*!< USB_EP DOEPINT: OUTTknEPdis Mask        */\r
+#define USB_EP_DOEPINT_StsPhseRcvd_Pos        5                                                       /*!< USB_EP DOEPINT: StsPhseRcvd Position    */\r
+#define USB_EP_DOEPINT_StsPhseRcvd_Msk        (0x01UL << USB_EP_DOEPINT_StsPhseRcvd_Pos)              /*!< USB_EP DOEPINT: StsPhseRcvd Mask        */\r
+#define USB_EP_DOEPINT_Back2BackSETup_Pos     6                                                       /*!< USB_EP DOEPINT: Back2BackSETup Position */\r
+#define USB_EP_DOEPINT_Back2BackSETup_Msk     (0x01UL << USB_EP_DOEPINT_Back2BackSETup_Pos)           /*!< USB_EP DOEPINT: Back2BackSETup Mask     */\r
+#define USB_EP_DOEPINT_BNAIntr_Pos            9                                                       /*!< USB_EP DOEPINT: BNAIntr Position        */\r
+#define USB_EP_DOEPINT_BNAIntr_Msk            (0x01UL << USB_EP_DOEPINT_BNAIntr_Pos)                  /*!< USB_EP DOEPINT: BNAIntr Mask            */\r
+#define USB_EP_DOEPINT_PktDrpSts_Pos          11                                                      /*!< USB_EP DOEPINT: PktDrpSts Position      */\r
+#define USB_EP_DOEPINT_PktDrpSts_Msk          (0x01UL << USB_EP_DOEPINT_PktDrpSts_Pos)                /*!< USB_EP DOEPINT: PktDrpSts Mask          */\r
+#define USB_EP_DOEPINT_BbleErrIntrpt_Pos      12                                                      /*!< USB_EP DOEPINT: BbleErrIntrpt Position  */\r
+#define USB_EP_DOEPINT_BbleErrIntrpt_Msk      (0x01UL << USB_EP_DOEPINT_BbleErrIntrpt_Pos)            /*!< USB_EP DOEPINT: BbleErrIntrpt Mask      */\r
+#define USB_EP_DOEPINT_NAKIntrpt_Pos          13                                                      /*!< USB_EP DOEPINT: NAKIntrpt Position      */\r
+#define USB_EP_DOEPINT_NAKIntrpt_Msk          (0x01UL << USB_EP_DOEPINT_NAKIntrpt_Pos)                /*!< USB_EP DOEPINT: NAKIntrpt Mask          */\r
+#define USB_EP_DOEPINT_NYETIntrpt_Pos         14                                                      /*!< USB_EP DOEPINT: NYETIntrpt Position     */\r
+#define USB_EP_DOEPINT_NYETIntrpt_Msk         (0x01UL << USB_EP_DOEPINT_NYETIntrpt_Pos)               /*!< USB_EP DOEPINT: NYETIntrpt Mask         */\r
+\r
+/* -----------------------------  USB_EP_DOEPTSIZ_ISO  ---------------------------- */\r
+#define USB_EP_DOEPTSIZ_ISO_XferSize_Pos      0                                                       /*!< USB_EP DOEPTSIZ_ISO: XferSize Position  */\r
+#define USB_EP_DOEPTSIZ_ISO_XferSize_Msk      (0x0007ffffUL << USB_EP_DOEPTSIZ_ISO_XferSize_Pos)      /*!< USB_EP DOEPTSIZ_ISO: XferSize Mask      */\r
+#define USB_EP_DOEPTSIZ_ISO_PktCnt_Pos        19                                                      /*!< USB_EP DOEPTSIZ_ISO: PktCnt Position    */\r
+#define USB_EP_DOEPTSIZ_ISO_PktCnt_Msk        (0x000003ffUL << USB_EP_DOEPTSIZ_ISO_PktCnt_Pos)        /*!< USB_EP DOEPTSIZ_ISO: PktCnt Mask        */\r
+#define USB_EP_DOEPTSIZ_ISO_RxDPID_Pos        29                                                      /*!< USB_EP DOEPTSIZ_ISO: RxDPID Position    */\r
+#define USB_EP_DOEPTSIZ_ISO_RxDPID_Msk        (0x03UL << USB_EP_DOEPTSIZ_ISO_RxDPID_Pos)              /*!< USB_EP DOEPTSIZ_ISO: RxDPID Mask        */\r
+\r
+/* ---------------------------  USB_EP_DOEPTSIZ_CONTROL  -------------------------- */\r
+#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos  0                                                       /*!< USB_EP DOEPTSIZ_CONTROL: XferSize Position */\r
+#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk  (0x0007ffffUL << USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos)  /*!< USB_EP DOEPTSIZ_CONTROL: XferSize Mask  */\r
+#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos    19                                                      /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt Position */\r
+#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk    (0x000003ffUL << USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos)    /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt Mask    */\r
+#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos    29                                                      /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt Position */\r
+#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk    (0x03UL << USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos)          /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt Mask    */\r
+\r
+/* -------------------------------  USB_EP_DOEPDMA  ------------------------------- */\r
+#define USB_EP_DOEPDMA_DMAAddr_Pos            0                                                       /*!< USB_EP DOEPDMA: DMAAddr Position        */\r
+#define USB_EP_DOEPDMA_DMAAddr_Msk            (0xffffffffUL << USB_EP_DOEPDMA_DMAAddr_Pos)            /*!< USB_EP DOEPDMA: DMAAddr Mask            */\r
+\r
+/* -------------------------------  USB_EP_DOEPDMAB  ------------------------------ */\r
+#define USB_EP_DOEPDMAB_DMABufferAddr_Pos     0                                                       /*!< USB_EP DOEPDMAB: DMABufferAddr Position */\r
+#define USB_EP_DOEPDMAB_DMABufferAddr_Msk     (0xffffffffUL << USB_EP_DOEPDMAB_DMABufferAddr_Pos)     /*!< USB_EP DOEPDMAB: DMABufferAddr Mask     */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'USB_CH' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  USB_CH_HCCHAR  ------------------------------- */\r
+#define USB_CH_HCCHAR_MPS_Pos                 0                                                       /*!< USB_CH HCCHAR: MPS Position             */\r
+#define USB_CH_HCCHAR_MPS_Msk                 (0x000007ffUL << USB_CH_HCCHAR_MPS_Pos)                 /*!< USB_CH HCCHAR: MPS Mask                 */\r
+#define USB_CH_HCCHAR_EPNum_Pos               11                                                      /*!< USB_CH HCCHAR: EPNum Position           */\r
+#define USB_CH_HCCHAR_EPNum_Msk               (0x0fUL << USB_CH_HCCHAR_EPNum_Pos)                     /*!< USB_CH HCCHAR: EPNum Mask               */\r
+#define USB_CH_HCCHAR_EPDir_Pos               15                                                      /*!< USB_CH HCCHAR: EPDir Position           */\r
+#define USB_CH_HCCHAR_EPDir_Msk               (0x01UL << USB_CH_HCCHAR_EPDir_Pos)                     /*!< USB_CH HCCHAR: EPDir Mask               */\r
+#define USB_CH_HCCHAR_EPType_Pos              18                                                      /*!< USB_CH HCCHAR: EPType Position          */\r
+#define USB_CH_HCCHAR_EPType_Msk              (0x03UL << USB_CH_HCCHAR_EPType_Pos)                    /*!< USB_CH HCCHAR: EPType Mask              */\r
+#define USB_CH_HCCHAR_MC_EC_Pos               20                                                      /*!< USB_CH HCCHAR: MC_EC Position           */\r
+#define USB_CH_HCCHAR_MC_EC_Msk               (0x03UL << USB_CH_HCCHAR_MC_EC_Pos)                     /*!< USB_CH HCCHAR: MC_EC Mask               */\r
+#define USB_CH_HCCHAR_DevAddr_Pos             22                                                      /*!< USB_CH HCCHAR: DevAddr Position         */\r
+#define USB_CH_HCCHAR_DevAddr_Msk             (0x7fUL << USB_CH_HCCHAR_DevAddr_Pos)                   /*!< USB_CH HCCHAR: DevAddr Mask             */\r
+#define USB_CH_HCCHAR_OddFrm_Pos              29                                                      /*!< USB_CH HCCHAR: OddFrm Position          */\r
+#define USB_CH_HCCHAR_OddFrm_Msk              (0x01UL << USB_CH_HCCHAR_OddFrm_Pos)                    /*!< USB_CH HCCHAR: OddFrm Mask              */\r
+#define USB_CH_HCCHAR_ChDis_Pos               30                                                      /*!< USB_CH HCCHAR: ChDis Position           */\r
+#define USB_CH_HCCHAR_ChDis_Msk               (0x01UL << USB_CH_HCCHAR_ChDis_Pos)                     /*!< USB_CH HCCHAR: ChDis Mask               */\r
+#define USB_CH_HCCHAR_ChEna_Pos               31                                                      /*!< USB_CH HCCHAR: ChEna Position           */\r
+#define USB_CH_HCCHAR_ChEna_Msk               (0x01UL << USB_CH_HCCHAR_ChEna_Pos)                     /*!< USB_CH HCCHAR: ChEna Mask               */\r
+\r
+/* --------------------------------  USB_CH_HCINT  -------------------------------- */\r
+#define USB_CH_HCINT_XferCompl_Pos            0                                                       /*!< USB_CH HCINT: XferCompl Position        */\r
+#define USB_CH_HCINT_XferCompl_Msk            (0x01UL << USB_CH_HCINT_XferCompl_Pos)                  /*!< USB_CH HCINT: XferCompl Mask            */\r
+#define USB_CH_HCINT_ChHltd_Pos               1                                                       /*!< USB_CH HCINT: ChHltd Position           */\r
+#define USB_CH_HCINT_ChHltd_Msk               (0x01UL << USB_CH_HCINT_ChHltd_Pos)                     /*!< USB_CH HCINT: ChHltd Mask               */\r
+#define USB_CH_HCINT_AHBErr_Pos               2                                                       /*!< USB_CH HCINT: AHBErr Position           */\r
+#define USB_CH_HCINT_AHBErr_Msk               (0x01UL << USB_CH_HCINT_AHBErr_Pos)                     /*!< USB_CH HCINT: AHBErr Mask               */\r
+#define USB_CH_HCINT_STALL_Pos                3                                                       /*!< USB_CH HCINT: STALL Position            */\r
+#define USB_CH_HCINT_STALL_Msk                (0x01UL << USB_CH_HCINT_STALL_Pos)                      /*!< USB_CH HCINT: STALL Mask                */\r
+#define USB_CH_HCINT_NAK_Pos                  4                                                       /*!< USB_CH HCINT: NAK Position              */\r
+#define USB_CH_HCINT_NAK_Msk                  (0x01UL << USB_CH_HCINT_NAK_Pos)                        /*!< USB_CH HCINT: NAK Mask                  */\r
+#define USB_CH_HCINT_ACK_Pos                  5                                                       /*!< USB_CH HCINT: ACK Position              */\r
+#define USB_CH_HCINT_ACK_Msk                  (0x01UL << USB_CH_HCINT_ACK_Pos)                        /*!< USB_CH HCINT: ACK Mask                  */\r
+#define USB_CH_HCINT_NYET_Pos                 6                                                       /*!< USB_CH HCINT: NYET Position             */\r
+#define USB_CH_HCINT_NYET_Msk                 (0x01UL << USB_CH_HCINT_NYET_Pos)                       /*!< USB_CH HCINT: NYET Mask                 */\r
+#define USB_CH_HCINT_XactErr_Pos              7                                                       /*!< USB_CH HCINT: XactErr Position          */\r
+#define USB_CH_HCINT_XactErr_Msk              (0x01UL << USB_CH_HCINT_XactErr_Pos)                    /*!< USB_CH HCINT: XactErr Mask              */\r
+#define USB_CH_HCINT_BblErr_Pos               8                                                       /*!< USB_CH HCINT: BblErr Position           */\r
+#define USB_CH_HCINT_BblErr_Msk               (0x01UL << USB_CH_HCINT_BblErr_Pos)                     /*!< USB_CH HCINT: BblErr Mask               */\r
+#define USB_CH_HCINT_FrmOvrun_Pos             9                                                       /*!< USB_CH HCINT: FrmOvrun Position         */\r
+#define USB_CH_HCINT_FrmOvrun_Msk             (0x01UL << USB_CH_HCINT_FrmOvrun_Pos)                   /*!< USB_CH HCINT: FrmOvrun Mask             */\r
+#define USB_CH_HCINT_DataTglErr_Pos           10                                                      /*!< USB_CH HCINT: DataTglErr Position       */\r
+#define USB_CH_HCINT_DataTglErr_Msk           (0x01UL << USB_CH_HCINT_DataTglErr_Pos)                 /*!< USB_CH HCINT: DataTglErr Mask           */\r
+#define USB_CH_HCINT_BNAIntr_Pos              11                                                      /*!< USB_CH HCINT: BNAIntr Position          */\r
+#define USB_CH_HCINT_BNAIntr_Msk              (0x01UL << USB_CH_HCINT_BNAIntr_Pos)                    /*!< USB_CH HCINT: BNAIntr Mask              */\r
+#define USB_CH_HCINT_XCS_XACT_ERR_Pos         12                                                      /*!< USB_CH HCINT: XCS_XACT_ERR Position     */\r
+#define USB_CH_HCINT_XCS_XACT_ERR_Msk         (0x01UL << USB_CH_HCINT_XCS_XACT_ERR_Pos)               /*!< USB_CH HCINT: XCS_XACT_ERR Mask         */\r
+#define USB_CH_HCINT_DESC_LST_ROLLIntr_Pos    13                                                      /*!< USB_CH HCINT: DESC_LST_ROLLIntr Position */\r
+#define USB_CH_HCINT_DESC_LST_ROLLIntr_Msk    (0x01UL << USB_CH_HCINT_DESC_LST_ROLLIntr_Pos)          /*!< USB_CH HCINT: DESC_LST_ROLLIntr Mask    */\r
+\r
+/* -------------------------------  USB_CH_HCINTMSK  ------------------------------ */\r
+#define USB_CH_HCINTMSK_XferComplMsk_Pos      0                                                       /*!< USB_CH HCINTMSK: XferComplMsk Position  */\r
+#define USB_CH_HCINTMSK_XferComplMsk_Msk      (0x01UL << USB_CH_HCINTMSK_XferComplMsk_Pos)            /*!< USB_CH HCINTMSK: XferComplMsk Mask      */\r
+#define USB_CH_HCINTMSK_ChHltdMsk_Pos         1                                                       /*!< USB_CH HCINTMSK: ChHltdMsk Position     */\r
+#define USB_CH_HCINTMSK_ChHltdMsk_Msk         (0x01UL << USB_CH_HCINTMSK_ChHltdMsk_Pos)               /*!< USB_CH HCINTMSK: ChHltdMsk Mask         */\r
+#define USB_CH_HCINTMSK_AHBErrMsk_Pos         2                                                       /*!< USB_CH HCINTMSK: AHBErrMsk Position     */\r
+#define USB_CH_HCINTMSK_AHBErrMsk_Msk         (0x01UL << USB_CH_HCINTMSK_AHBErrMsk_Pos)               /*!< USB_CH HCINTMSK: AHBErrMsk Mask         */\r
+#define USB_CH_HCINTMSK_StallMsk_Pos          3                                                       /*!< USB_CH HCINTMSK: StallMsk Position      */\r
+#define USB_CH_HCINTMSK_StallMsk_Msk          (0x01UL << USB_CH_HCINTMSK_StallMsk_Pos)                /*!< USB_CH HCINTMSK: StallMsk Mask          */\r
+#define USB_CH_HCINTMSK_NakMsk_Pos            4                                                       /*!< USB_CH HCINTMSK: NakMsk Position        */\r
+#define USB_CH_HCINTMSK_NakMsk_Msk            (0x01UL << USB_CH_HCINTMSK_NakMsk_Pos)                  /*!< USB_CH HCINTMSK: NakMsk Mask            */\r
+#define USB_CH_HCINTMSK_AckMsk_Pos            5                                                       /*!< USB_CH HCINTMSK: AckMsk Position        */\r
+#define USB_CH_HCINTMSK_AckMsk_Msk            (0x01UL << USB_CH_HCINTMSK_AckMsk_Pos)                  /*!< USB_CH HCINTMSK: AckMsk Mask            */\r
+#define USB_CH_HCINTMSK_NyetMsk_Pos           6                                                       /*!< USB_CH HCINTMSK: NyetMsk Position       */\r
+#define USB_CH_HCINTMSK_NyetMsk_Msk           (0x01UL << USB_CH_HCINTMSK_NyetMsk_Pos)                 /*!< USB_CH HCINTMSK: NyetMsk Mask           */\r
+#define USB_CH_HCINTMSK_XactErrMsk_Pos        7                                                       /*!< USB_CH HCINTMSK: XactErrMsk Position    */\r
+#define USB_CH_HCINTMSK_XactErrMsk_Msk        (0x01UL << USB_CH_HCINTMSK_XactErrMsk_Pos)              /*!< USB_CH HCINTMSK: XactErrMsk Mask        */\r
+#define USB_CH_HCINTMSK_BblErrMsk_Pos         8                                                       /*!< USB_CH HCINTMSK: BblErrMsk Position     */\r
+#define USB_CH_HCINTMSK_BblErrMsk_Msk         (0x01UL << USB_CH_HCINTMSK_BblErrMsk_Pos)               /*!< USB_CH HCINTMSK: BblErrMsk Mask         */\r
+#define USB_CH_HCINTMSK_FrmOvrunMsk_Pos       9                                                       /*!< USB_CH HCINTMSK: FrmOvrunMsk Position   */\r
+#define USB_CH_HCINTMSK_FrmOvrunMsk_Msk       (0x01UL << USB_CH_HCINTMSK_FrmOvrunMsk_Pos)             /*!< USB_CH HCINTMSK: FrmOvrunMsk Mask       */\r
+#define USB_CH_HCINTMSK_DataTglErrMsk_Pos     10                                                      /*!< USB_CH HCINTMSK: DataTglErrMsk Position */\r
+#define USB_CH_HCINTMSK_DataTglErrMsk_Msk     (0x01UL << USB_CH_HCINTMSK_DataTglErrMsk_Pos)           /*!< USB_CH HCINTMSK: DataTglErrMsk Mask     */\r
+#define USB_CH_HCINTMSK_BNAIntrMsk_Pos        11                                                      /*!< USB_CH HCINTMSK: BNAIntrMsk Position    */\r
+#define USB_CH_HCINTMSK_BNAIntrMsk_Msk        (0x01UL << USB_CH_HCINTMSK_BNAIntrMsk_Pos)              /*!< USB_CH HCINTMSK: BNAIntrMsk Mask        */\r
+#define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos 13                                                   /*!< USB_CH HCINTMSK: DESC_LST_ROLLIntrMsk Position */\r
+#define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Msk (0x01UL << USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos) /*!< USB_CH HCINTMSK: DESC_LST_ROLLIntrMsk Mask */\r
+\r
+/* --------------------------  USB_CH_HCTSIZ_BUFFERMODE  -------------------------- */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos 0                                                       /*!< USB_CH HCTSIZ_BUFFERMODE: XferSize Position */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Msk (0x0007ffffUL << USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos) /*!< USB_CH HCTSIZ_BUFFERMODE: XferSize Mask */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos   19                                                      /*!< USB_CH HCTSIZ_BUFFERMODE: PktCnt Position */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk   (0x000003ffUL << USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos)   /*!< USB_CH HCTSIZ_BUFFERMODE: PktCnt Mask   */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos      29                                                      /*!< USB_CH HCTSIZ_BUFFERMODE: Pid Position  */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk      (0x03UL << USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos)            /*!< USB_CH HCTSIZ_BUFFERMODE: Pid Mask      */\r
+\r
+/* --------------------------  USB_CH_HCTSIZ_SCATGATHER  -------------------------- */\r
+#define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos 0                                                     /*!< USB_CH HCTSIZ_SCATGATHER: SCHED_INFO Position */\r
+#define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Msk (0x000000ffUL << USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos)/*!< USB_CH HCTSIZ_SCATGATHER: SCHED_INFO Mask */\r
+#define USB_CH_HCTSIZ_SCATGATHER_NTD_Pos      8                                                       /*!< USB_CH HCTSIZ_SCATGATHER: NTD Position  */\r
+#define USB_CH_HCTSIZ_SCATGATHER_NTD_Msk      (0x000000ffUL << USB_CH_HCTSIZ_SCATGATHER_NTD_Pos)      /*!< USB_CH HCTSIZ_SCATGATHER: NTD Mask      */\r
+#define USB_CH_HCTSIZ_SCATGATHER_Pid_Pos      29                                                      /*!< USB_CH HCTSIZ_SCATGATHER: Pid Position  */\r
+#define USB_CH_HCTSIZ_SCATGATHER_Pid_Msk      (0x03UL << USB_CH_HCTSIZ_SCATGATHER_Pid_Pos)            /*!< USB_CH HCTSIZ_SCATGATHER: Pid Mask      */\r
+\r
+/* ---------------------------  USB_CH_HCDMA_BUFFERMODE  -------------------------- */\r
+#define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos   0                                                       /*!< USB_CH HCDMA_BUFFERMODE: DMAAddr Position */\r
+#define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Msk   (0xffffffffUL << USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos)   /*!< USB_CH HCDMA_BUFFERMODE: DMAAddr Mask   */\r
+\r
+/* ---------------------------  USB_CH_HCDMA_SCATGATHER  -------------------------- */\r
+#define USB_CH_HCDMA_SCATGATHER_CTD_Pos       3                                                       /*!< USB_CH HCDMA_SCATGATHER: CTD Position   */\r
+#define USB_CH_HCDMA_SCATGATHER_CTD_Msk       (0x3fUL << USB_CH_HCDMA_SCATGATHER_CTD_Pos)             /*!< USB_CH HCDMA_SCATGATHER: CTD Mask       */\r
+#define USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos   9                                                       /*!< USB_CH HCDMA_SCATGATHER: DMAAddr Position */\r
+#define USB_CH_HCDMA_SCATGATHER_DMAAddr_Msk   (0x007fffffUL << USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos)   /*!< USB_CH HCDMA_SCATGATHER: DMAAddr Mask   */\r
+\r
+/* --------------------------------  USB_CH_HCDMAB  ------------------------------- */\r
+#define USB_CH_HCDMAB_Buffer_Address_Pos      0                                                       /*!< USB_CH HCDMAB: Buffer_Address Position  */\r
+#define USB_CH_HCDMAB_Buffer_Address_Msk      (0xffffffffUL << USB_CH_HCDMAB_Buffer_Address_Pos)      /*!< USB_CH HCDMAB: Buffer_Address Mask      */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'USIC' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  USIC_ID  ---------------------------------- */\r
+#define USIC_ID_MOD_REV_Pos                   0                                                       /*!< USIC ID: MOD_REV Position               */\r
+#define USIC_ID_MOD_REV_Msk                   (0x000000ffUL << USIC_ID_MOD_REV_Pos)                   /*!< USIC ID: MOD_REV Mask                   */\r
+#define USIC_ID_MOD_TYPE_Pos                  8                                                       /*!< USIC ID: MOD_TYPE Position              */\r
+#define USIC_ID_MOD_TYPE_Msk                  (0x000000ffUL << USIC_ID_MOD_TYPE_Pos)                  /*!< USIC ID: MOD_TYPE Mask                  */\r
+#define USIC_ID_MOD_NUMBER_Pos                16                                                      /*!< USIC ID: MOD_NUMBER Position            */\r
+#define USIC_ID_MOD_NUMBER_Msk                (0x0000ffffUL << USIC_ID_MOD_NUMBER_Pos)                /*!< USIC ID: MOD_NUMBER Mask                */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'USIC_CH' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  USIC_CH_CCFG  -------------------------------- */\r
+#define USIC_CH_CCFG_SSC_Pos                  0                                                       /*!< USIC_CH CCFG: SSC Position              */\r
+#define USIC_CH_CCFG_SSC_Msk                  (0x01UL << USIC_CH_CCFG_SSC_Pos)                        /*!< USIC_CH CCFG: SSC Mask                  */\r
+#define USIC_CH_CCFG_ASC_Pos                  1                                                       /*!< USIC_CH CCFG: ASC Position              */\r
+#define USIC_CH_CCFG_ASC_Msk                  (0x01UL << USIC_CH_CCFG_ASC_Pos)                        /*!< USIC_CH CCFG: ASC Mask                  */\r
+#define USIC_CH_CCFG_IIC_Pos                  2                                                       /*!< USIC_CH CCFG: IIC Position              */\r
+#define USIC_CH_CCFG_IIC_Msk                  (0x01UL << USIC_CH_CCFG_IIC_Pos)                        /*!< USIC_CH CCFG: IIC Mask                  */\r
+#define USIC_CH_CCFG_IIS_Pos                  3                                                       /*!< USIC_CH CCFG: IIS Position              */\r
+#define USIC_CH_CCFG_IIS_Msk                  (0x01UL << USIC_CH_CCFG_IIS_Pos)                        /*!< USIC_CH CCFG: IIS Mask                  */\r
+#define USIC_CH_CCFG_RB_Pos                   6                                                       /*!< USIC_CH CCFG: RB Position               */\r
+#define USIC_CH_CCFG_RB_Msk                   (0x01UL << USIC_CH_CCFG_RB_Pos)                         /*!< USIC_CH CCFG: RB Mask                   */\r
+#define USIC_CH_CCFG_TB_Pos                   7                                                       /*!< USIC_CH CCFG: TB Position               */\r
+#define USIC_CH_CCFG_TB_Msk                   (0x01UL << USIC_CH_CCFG_TB_Pos)                         /*!< USIC_CH CCFG: TB Mask                   */\r
+\r
+/* --------------------------------  USIC_CH_KSCFG  ------------------------------- */\r
+#define USIC_CH_KSCFG_MODEN_Pos               0                                                       /*!< USIC_CH KSCFG: MODEN Position           */\r
+#define USIC_CH_KSCFG_MODEN_Msk               (0x01UL << USIC_CH_KSCFG_MODEN_Pos)                     /*!< USIC_CH KSCFG: MODEN Mask               */\r
+#define USIC_CH_KSCFG_BPMODEN_Pos             1                                                       /*!< USIC_CH KSCFG: BPMODEN Position         */\r
+#define USIC_CH_KSCFG_BPMODEN_Msk             (0x01UL << USIC_CH_KSCFG_BPMODEN_Pos)                   /*!< USIC_CH KSCFG: BPMODEN Mask             */\r
+#define USIC_CH_KSCFG_NOMCFG_Pos              4                                                       /*!< USIC_CH KSCFG: NOMCFG Position          */\r
+#define USIC_CH_KSCFG_NOMCFG_Msk              (0x03UL << USIC_CH_KSCFG_NOMCFG_Pos)                    /*!< USIC_CH KSCFG: NOMCFG Mask              */\r
+#define USIC_CH_KSCFG_BPNOM_Pos               7                                                       /*!< USIC_CH KSCFG: BPNOM Position           */\r
+#define USIC_CH_KSCFG_BPNOM_Msk               (0x01UL << USIC_CH_KSCFG_BPNOM_Pos)                     /*!< USIC_CH KSCFG: BPNOM Mask               */\r
+#define USIC_CH_KSCFG_SUMCFG_Pos              8                                                       /*!< USIC_CH KSCFG: SUMCFG Position          */\r
+#define USIC_CH_KSCFG_SUMCFG_Msk              (0x03UL << USIC_CH_KSCFG_SUMCFG_Pos)                    /*!< USIC_CH KSCFG: SUMCFG Mask              */\r
+#define USIC_CH_KSCFG_BPSUM_Pos               11                                                      /*!< USIC_CH KSCFG: BPSUM Position           */\r
+#define USIC_CH_KSCFG_BPSUM_Msk               (0x01UL << USIC_CH_KSCFG_BPSUM_Pos)                     /*!< USIC_CH KSCFG: BPSUM Mask               */\r
+\r
+/* ---------------------------------  USIC_CH_FDR  -------------------------------- */\r
+#define USIC_CH_FDR_STEP_Pos                  0                                                       /*!< USIC_CH FDR: STEP Position              */\r
+#define USIC_CH_FDR_STEP_Msk                  (0x000003ffUL << USIC_CH_FDR_STEP_Pos)                  /*!< USIC_CH FDR: STEP Mask                  */\r
+#define USIC_CH_FDR_DM_Pos                    14                                                      /*!< USIC_CH FDR: DM Position                */\r
+#define USIC_CH_FDR_DM_Msk                    (0x03UL << USIC_CH_FDR_DM_Pos)                          /*!< USIC_CH FDR: DM Mask                    */\r
+#define USIC_CH_FDR_RESULT_Pos                16                                                      /*!< USIC_CH FDR: RESULT Position            */\r
+#define USIC_CH_FDR_RESULT_Msk                (0x000003ffUL << USIC_CH_FDR_RESULT_Pos)                /*!< USIC_CH FDR: RESULT Mask                */\r
+\r
+/* ---------------------------------  USIC_CH_BRG  -------------------------------- */\r
+#define USIC_CH_BRG_CLKSEL_Pos                0                                                       /*!< USIC_CH BRG: CLKSEL Position            */\r
+#define USIC_CH_BRG_CLKSEL_Msk                (0x03UL << USIC_CH_BRG_CLKSEL_Pos)                      /*!< USIC_CH BRG: CLKSEL Mask                */\r
+#define USIC_CH_BRG_TMEN_Pos                  3                                                       /*!< USIC_CH BRG: TMEN Position              */\r
+#define USIC_CH_BRG_TMEN_Msk                  (0x01UL << USIC_CH_BRG_TMEN_Pos)                        /*!< USIC_CH BRG: TMEN Mask                  */\r
+#define USIC_CH_BRG_PPPEN_Pos                 4                                                       /*!< USIC_CH BRG: PPPEN Position             */\r
+#define USIC_CH_BRG_PPPEN_Msk                 (0x01UL << USIC_CH_BRG_PPPEN_Pos)                       /*!< USIC_CH BRG: PPPEN Mask                 */\r
+#define USIC_CH_BRG_CTQSEL_Pos                6                                                       /*!< USIC_CH BRG: CTQSEL Position            */\r
+#define USIC_CH_BRG_CTQSEL_Msk                (0x03UL << USIC_CH_BRG_CTQSEL_Pos)                      /*!< USIC_CH BRG: CTQSEL Mask                */\r
+#define USIC_CH_BRG_PCTQ_Pos                  8                                                       /*!< USIC_CH BRG: PCTQ Position              */\r
+#define USIC_CH_BRG_PCTQ_Msk                  (0x03UL << USIC_CH_BRG_PCTQ_Pos)                        /*!< USIC_CH BRG: PCTQ Mask                  */\r
+#define USIC_CH_BRG_DCTQ_Pos                  10                                                      /*!< USIC_CH BRG: DCTQ Position              */\r
+#define USIC_CH_BRG_DCTQ_Msk                  (0x1fUL << USIC_CH_BRG_DCTQ_Pos)                        /*!< USIC_CH BRG: DCTQ Mask                  */\r
+#define USIC_CH_BRG_PDIV_Pos                  16                                                      /*!< USIC_CH BRG: PDIV Position              */\r
+#define USIC_CH_BRG_PDIV_Msk                  (0x000003ffUL << USIC_CH_BRG_PDIV_Pos)                  /*!< USIC_CH BRG: PDIV Mask                  */\r
+#define USIC_CH_BRG_SCLKOSEL_Pos              28                                                      /*!< USIC_CH BRG: SCLKOSEL Position          */\r
+#define USIC_CH_BRG_SCLKOSEL_Msk              (0x01UL << USIC_CH_BRG_SCLKOSEL_Pos)                    /*!< USIC_CH BRG: SCLKOSEL Mask              */\r
+#define USIC_CH_BRG_MCLKCFG_Pos               29                                                      /*!< USIC_CH BRG: MCLKCFG Position           */\r
+#define USIC_CH_BRG_MCLKCFG_Msk               (0x01UL << USIC_CH_BRG_MCLKCFG_Pos)                     /*!< USIC_CH BRG: MCLKCFG Mask               */\r
+#define USIC_CH_BRG_SCLKCFG_Pos               30                                                      /*!< USIC_CH BRG: SCLKCFG Position           */\r
+#define USIC_CH_BRG_SCLKCFG_Msk               (0x03UL << USIC_CH_BRG_SCLKCFG_Pos)                     /*!< USIC_CH BRG: SCLKCFG Mask               */\r
+\r
+/* --------------------------------  USIC_CH_INPR  -------------------------------- */\r
+#define USIC_CH_INPR_TSINP_Pos                0                                                       /*!< USIC_CH INPR: TSINP Position            */\r
+#define USIC_CH_INPR_TSINP_Msk                (0x07UL << USIC_CH_INPR_TSINP_Pos)                      /*!< USIC_CH INPR: TSINP Mask                */\r
+#define USIC_CH_INPR_TBINP_Pos                4                                                       /*!< USIC_CH INPR: TBINP Position            */\r
+#define USIC_CH_INPR_TBINP_Msk                (0x07UL << USIC_CH_INPR_TBINP_Pos)                      /*!< USIC_CH INPR: TBINP Mask                */\r
+#define USIC_CH_INPR_RINP_Pos                 8                                                       /*!< USIC_CH INPR: RINP Position             */\r
+#define USIC_CH_INPR_RINP_Msk                 (0x07UL << USIC_CH_INPR_RINP_Pos)                       /*!< USIC_CH INPR: RINP Mask                 */\r
+#define USIC_CH_INPR_AINP_Pos                 12                                                      /*!< USIC_CH INPR: AINP Position             */\r
+#define USIC_CH_INPR_AINP_Msk                 (0x07UL << USIC_CH_INPR_AINP_Pos)                       /*!< USIC_CH INPR: AINP Mask                 */\r
+#define USIC_CH_INPR_PINP_Pos                 16                                                      /*!< USIC_CH INPR: PINP Position             */\r
+#define USIC_CH_INPR_PINP_Msk                 (0x07UL << USIC_CH_INPR_PINP_Pos)                       /*!< USIC_CH INPR: PINP Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX0CR  ------------------------------- */\r
+#define USIC_CH_DX0CR_DSEL_Pos                0                                                       /*!< USIC_CH DX0CR: DSEL Position            */\r
+#define USIC_CH_DX0CR_DSEL_Msk                (0x07UL << USIC_CH_DX0CR_DSEL_Pos)                      /*!< USIC_CH DX0CR: DSEL Mask                */\r
+#define USIC_CH_DX0CR_INSW_Pos                4                                                       /*!< USIC_CH DX0CR: INSW Position            */\r
+#define USIC_CH_DX0CR_INSW_Msk                (0x01UL << USIC_CH_DX0CR_INSW_Pos)                      /*!< USIC_CH DX0CR: INSW Mask                */\r
+#define USIC_CH_DX0CR_DFEN_Pos                5                                                       /*!< USIC_CH DX0CR: DFEN Position            */\r
+#define USIC_CH_DX0CR_DFEN_Msk                (0x01UL << USIC_CH_DX0CR_DFEN_Pos)                      /*!< USIC_CH DX0CR: DFEN Mask                */\r
+#define USIC_CH_DX0CR_DSEN_Pos                6                                                       /*!< USIC_CH DX0CR: DSEN Position            */\r
+#define USIC_CH_DX0CR_DSEN_Msk                (0x01UL << USIC_CH_DX0CR_DSEN_Pos)                      /*!< USIC_CH DX0CR: DSEN Mask                */\r
+#define USIC_CH_DX0CR_DPOL_Pos                8                                                       /*!< USIC_CH DX0CR: DPOL Position            */\r
+#define USIC_CH_DX0CR_DPOL_Msk                (0x01UL << USIC_CH_DX0CR_DPOL_Pos)                      /*!< USIC_CH DX0CR: DPOL Mask                */\r
+#define USIC_CH_DX0CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX0CR: SFSEL Position           */\r
+#define USIC_CH_DX0CR_SFSEL_Msk               (0x01UL << USIC_CH_DX0CR_SFSEL_Pos)                     /*!< USIC_CH DX0CR: SFSEL Mask               */\r
+#define USIC_CH_DX0CR_CM_Pos                  10                                                      /*!< USIC_CH DX0CR: CM Position              */\r
+#define USIC_CH_DX0CR_CM_Msk                  (0x03UL << USIC_CH_DX0CR_CM_Pos)                        /*!< USIC_CH DX0CR: CM Mask                  */\r
+#define USIC_CH_DX0CR_DXS_Pos                 15                                                      /*!< USIC_CH DX0CR: DXS Position             */\r
+#define USIC_CH_DX0CR_DXS_Msk                 (0x01UL << USIC_CH_DX0CR_DXS_Pos)                       /*!< USIC_CH DX0CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX1CR  ------------------------------- */\r
+#define USIC_CH_DX1CR_DSEL_Pos                0                                                       /*!< USIC_CH DX1CR: DSEL Position            */\r
+#define USIC_CH_DX1CR_DSEL_Msk                (0x07UL << USIC_CH_DX1CR_DSEL_Pos)                      /*!< USIC_CH DX1CR: DSEL Mask                */\r
+#define USIC_CH_DX1CR_DCEN_Pos                3                                                       /*!< USIC_CH DX1CR: DCEN Position            */\r
+#define USIC_CH_DX1CR_DCEN_Msk                (0x01UL << USIC_CH_DX1CR_DCEN_Pos)                      /*!< USIC_CH DX1CR: DCEN Mask                */\r
+#define USIC_CH_DX1CR_INSW_Pos                4                                                       /*!< USIC_CH DX1CR: INSW Position            */\r
+#define USIC_CH_DX1CR_INSW_Msk                (0x01UL << USIC_CH_DX1CR_INSW_Pos)                      /*!< USIC_CH DX1CR: INSW Mask                */\r
+#define USIC_CH_DX1CR_DFEN_Pos                5                                                       /*!< USIC_CH DX1CR: DFEN Position            */\r
+#define USIC_CH_DX1CR_DFEN_Msk                (0x01UL << USIC_CH_DX1CR_DFEN_Pos)                      /*!< USIC_CH DX1CR: DFEN Mask                */\r
+#define USIC_CH_DX1CR_DSEN_Pos                6                                                       /*!< USIC_CH DX1CR: DSEN Position            */\r
+#define USIC_CH_DX1CR_DSEN_Msk                (0x01UL << USIC_CH_DX1CR_DSEN_Pos)                      /*!< USIC_CH DX1CR: DSEN Mask                */\r
+#define USIC_CH_DX1CR_DPOL_Pos                8                                                       /*!< USIC_CH DX1CR: DPOL Position            */\r
+#define USIC_CH_DX1CR_DPOL_Msk                (0x01UL << USIC_CH_DX1CR_DPOL_Pos)                      /*!< USIC_CH DX1CR: DPOL Mask                */\r
+#define USIC_CH_DX1CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX1CR: SFSEL Position           */\r
+#define USIC_CH_DX1CR_SFSEL_Msk               (0x01UL << USIC_CH_DX1CR_SFSEL_Pos)                     /*!< USIC_CH DX1CR: SFSEL Mask               */\r
+#define USIC_CH_DX1CR_CM_Pos                  10                                                      /*!< USIC_CH DX1CR: CM Position              */\r
+#define USIC_CH_DX1CR_CM_Msk                  (0x03UL << USIC_CH_DX1CR_CM_Pos)                        /*!< USIC_CH DX1CR: CM Mask                  */\r
+#define USIC_CH_DX1CR_DXS_Pos                 15                                                      /*!< USIC_CH DX1CR: DXS Position             */\r
+#define USIC_CH_DX1CR_DXS_Msk                 (0x01UL << USIC_CH_DX1CR_DXS_Pos)                       /*!< USIC_CH DX1CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX2CR  ------------------------------- */\r
+#define USIC_CH_DX2CR_DSEL_Pos                0                                                       /*!< USIC_CH DX2CR: DSEL Position            */\r
+#define USIC_CH_DX2CR_DSEL_Msk                (0x07UL << USIC_CH_DX2CR_DSEL_Pos)                      /*!< USIC_CH DX2CR: DSEL Mask                */\r
+#define USIC_CH_DX2CR_INSW_Pos                4                                                       /*!< USIC_CH DX2CR: INSW Position            */\r
+#define USIC_CH_DX2CR_INSW_Msk                (0x01UL << USIC_CH_DX2CR_INSW_Pos)                      /*!< USIC_CH DX2CR: INSW Mask                */\r
+#define USIC_CH_DX2CR_DFEN_Pos                5                                                       /*!< USIC_CH DX2CR: DFEN Position            */\r
+#define USIC_CH_DX2CR_DFEN_Msk                (0x01UL << USIC_CH_DX2CR_DFEN_Pos)                      /*!< USIC_CH DX2CR: DFEN Mask                */\r
+#define USIC_CH_DX2CR_DSEN_Pos                6                                                       /*!< USIC_CH DX2CR: DSEN Position            */\r
+#define USIC_CH_DX2CR_DSEN_Msk                (0x01UL << USIC_CH_DX2CR_DSEN_Pos)                      /*!< USIC_CH DX2CR: DSEN Mask                */\r
+#define USIC_CH_DX2CR_DPOL_Pos                8                                                       /*!< USIC_CH DX2CR: DPOL Position            */\r
+#define USIC_CH_DX2CR_DPOL_Msk                (0x01UL << USIC_CH_DX2CR_DPOL_Pos)                      /*!< USIC_CH DX2CR: DPOL Mask                */\r
+#define USIC_CH_DX2CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX2CR: SFSEL Position           */\r
+#define USIC_CH_DX2CR_SFSEL_Msk               (0x01UL << USIC_CH_DX2CR_SFSEL_Pos)                     /*!< USIC_CH DX2CR: SFSEL Mask               */\r
+#define USIC_CH_DX2CR_CM_Pos                  10                                                      /*!< USIC_CH DX2CR: CM Position              */\r
+#define USIC_CH_DX2CR_CM_Msk                  (0x03UL << USIC_CH_DX2CR_CM_Pos)                        /*!< USIC_CH DX2CR: CM Mask                  */\r
+#define USIC_CH_DX2CR_DXS_Pos                 15                                                      /*!< USIC_CH DX2CR: DXS Position             */\r
+#define USIC_CH_DX2CR_DXS_Msk                 (0x01UL << USIC_CH_DX2CR_DXS_Pos)                       /*!< USIC_CH DX2CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX3CR  ------------------------------- */\r
+#define USIC_CH_DX3CR_DSEL_Pos                0                                                       /*!< USIC_CH DX3CR: DSEL Position            */\r
+#define USIC_CH_DX3CR_DSEL_Msk                (0x07UL << USIC_CH_DX3CR_DSEL_Pos)                      /*!< USIC_CH DX3CR: DSEL Mask                */\r
+#define USIC_CH_DX3CR_INSW_Pos                4                                                       /*!< USIC_CH DX3CR: INSW Position            */\r
+#define USIC_CH_DX3CR_INSW_Msk                (0x01UL << USIC_CH_DX3CR_INSW_Pos)                      /*!< USIC_CH DX3CR: INSW Mask                */\r
+#define USIC_CH_DX3CR_DFEN_Pos                5                                                       /*!< USIC_CH DX3CR: DFEN Position            */\r
+#define USIC_CH_DX3CR_DFEN_Msk                (0x01UL << USIC_CH_DX3CR_DFEN_Pos)                      /*!< USIC_CH DX3CR: DFEN Mask                */\r
+#define USIC_CH_DX3CR_DSEN_Pos                6                                                       /*!< USIC_CH DX3CR: DSEN Position            */\r
+#define USIC_CH_DX3CR_DSEN_Msk                (0x01UL << USIC_CH_DX3CR_DSEN_Pos)                      /*!< USIC_CH DX3CR: DSEN Mask                */\r
+#define USIC_CH_DX3CR_DPOL_Pos                8                                                       /*!< USIC_CH DX3CR: DPOL Position            */\r
+#define USIC_CH_DX3CR_DPOL_Msk                (0x01UL << USIC_CH_DX3CR_DPOL_Pos)                      /*!< USIC_CH DX3CR: DPOL Mask                */\r
+#define USIC_CH_DX3CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX3CR: SFSEL Position           */\r
+#define USIC_CH_DX3CR_SFSEL_Msk               (0x01UL << USIC_CH_DX3CR_SFSEL_Pos)                     /*!< USIC_CH DX3CR: SFSEL Mask               */\r
+#define USIC_CH_DX3CR_CM_Pos                  10                                                      /*!< USIC_CH DX3CR: CM Position              */\r
+#define USIC_CH_DX3CR_CM_Msk                  (0x03UL << USIC_CH_DX3CR_CM_Pos)                        /*!< USIC_CH DX3CR: CM Mask                  */\r
+#define USIC_CH_DX3CR_DXS_Pos                 15                                                      /*!< USIC_CH DX3CR: DXS Position             */\r
+#define USIC_CH_DX3CR_DXS_Msk                 (0x01UL << USIC_CH_DX3CR_DXS_Pos)                       /*!< USIC_CH DX3CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX4CR  ------------------------------- */\r
+#define USIC_CH_DX4CR_DSEL_Pos                0                                                       /*!< USIC_CH DX4CR: DSEL Position            */\r
+#define USIC_CH_DX4CR_DSEL_Msk                (0x07UL << USIC_CH_DX4CR_DSEL_Pos)                      /*!< USIC_CH DX4CR: DSEL Mask                */\r
+#define USIC_CH_DX4CR_INSW_Pos                4                                                       /*!< USIC_CH DX4CR: INSW Position            */\r
+#define USIC_CH_DX4CR_INSW_Msk                (0x01UL << USIC_CH_DX4CR_INSW_Pos)                      /*!< USIC_CH DX4CR: INSW Mask                */\r
+#define USIC_CH_DX4CR_DFEN_Pos                5                                                       /*!< USIC_CH DX4CR: DFEN Position            */\r
+#define USIC_CH_DX4CR_DFEN_Msk                (0x01UL << USIC_CH_DX4CR_DFEN_Pos)                      /*!< USIC_CH DX4CR: DFEN Mask                */\r
+#define USIC_CH_DX4CR_DSEN_Pos                6                                                       /*!< USIC_CH DX4CR: DSEN Position            */\r
+#define USIC_CH_DX4CR_DSEN_Msk                (0x01UL << USIC_CH_DX4CR_DSEN_Pos)                      /*!< USIC_CH DX4CR: DSEN Mask                */\r
+#define USIC_CH_DX4CR_DPOL_Pos                8                                                       /*!< USIC_CH DX4CR: DPOL Position            */\r
+#define USIC_CH_DX4CR_DPOL_Msk                (0x01UL << USIC_CH_DX4CR_DPOL_Pos)                      /*!< USIC_CH DX4CR: DPOL Mask                */\r
+#define USIC_CH_DX4CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX4CR: SFSEL Position           */\r
+#define USIC_CH_DX4CR_SFSEL_Msk               (0x01UL << USIC_CH_DX4CR_SFSEL_Pos)                     /*!< USIC_CH DX4CR: SFSEL Mask               */\r
+#define USIC_CH_DX4CR_CM_Pos                  10                                                      /*!< USIC_CH DX4CR: CM Position              */\r
+#define USIC_CH_DX4CR_CM_Msk                  (0x03UL << USIC_CH_DX4CR_CM_Pos)                        /*!< USIC_CH DX4CR: CM Mask                  */\r
+#define USIC_CH_DX4CR_DXS_Pos                 15                                                      /*!< USIC_CH DX4CR: DXS Position             */\r
+#define USIC_CH_DX4CR_DXS_Msk                 (0x01UL << USIC_CH_DX4CR_DXS_Pos)                       /*!< USIC_CH DX4CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX5CR  ------------------------------- */\r
+#define USIC_CH_DX5CR_DSEL_Pos                0                                                       /*!< USIC_CH DX5CR: DSEL Position            */\r
+#define USIC_CH_DX5CR_DSEL_Msk                (0x07UL << USIC_CH_DX5CR_DSEL_Pos)                      /*!< USIC_CH DX5CR: DSEL Mask                */\r
+#define USIC_CH_DX5CR_INSW_Pos                4                                                       /*!< USIC_CH DX5CR: INSW Position            */\r
+#define USIC_CH_DX5CR_INSW_Msk                (0x01UL << USIC_CH_DX5CR_INSW_Pos)                      /*!< USIC_CH DX5CR: INSW Mask                */\r
+#define USIC_CH_DX5CR_DFEN_Pos                5                                                       /*!< USIC_CH DX5CR: DFEN Position            */\r
+#define USIC_CH_DX5CR_DFEN_Msk                (0x01UL << USIC_CH_DX5CR_DFEN_Pos)                      /*!< USIC_CH DX5CR: DFEN Mask                */\r
+#define USIC_CH_DX5CR_DSEN_Pos                6                                                       /*!< USIC_CH DX5CR: DSEN Position            */\r
+#define USIC_CH_DX5CR_DSEN_Msk                (0x01UL << USIC_CH_DX5CR_DSEN_Pos)                      /*!< USIC_CH DX5CR: DSEN Mask                */\r
+#define USIC_CH_DX5CR_DPOL_Pos                8                                                       /*!< USIC_CH DX5CR: DPOL Position            */\r
+#define USIC_CH_DX5CR_DPOL_Msk                (0x01UL << USIC_CH_DX5CR_DPOL_Pos)                      /*!< USIC_CH DX5CR: DPOL Mask                */\r
+#define USIC_CH_DX5CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX5CR: SFSEL Position           */\r
+#define USIC_CH_DX5CR_SFSEL_Msk               (0x01UL << USIC_CH_DX5CR_SFSEL_Pos)                     /*!< USIC_CH DX5CR: SFSEL Mask               */\r
+#define USIC_CH_DX5CR_CM_Pos                  10                                                      /*!< USIC_CH DX5CR: CM Position              */\r
+#define USIC_CH_DX5CR_CM_Msk                  (0x03UL << USIC_CH_DX5CR_CM_Pos)                        /*!< USIC_CH DX5CR: CM Mask                  */\r
+#define USIC_CH_DX5CR_DXS_Pos                 15                                                      /*!< USIC_CH DX5CR: DXS Position             */\r
+#define USIC_CH_DX5CR_DXS_Msk                 (0x01UL << USIC_CH_DX5CR_DXS_Pos)                       /*!< USIC_CH DX5CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_SCTR  -------------------------------- */\r
+#define USIC_CH_SCTR_SDIR_Pos                 0                                                       /*!< USIC_CH SCTR: SDIR Position             */\r
+#define USIC_CH_SCTR_SDIR_Msk                 (0x01UL << USIC_CH_SCTR_SDIR_Pos)                       /*!< USIC_CH SCTR: SDIR Mask                 */\r
+#define USIC_CH_SCTR_PDL_Pos                  1                                                       /*!< USIC_CH SCTR: PDL Position              */\r
+#define USIC_CH_SCTR_PDL_Msk                  (0x01UL << USIC_CH_SCTR_PDL_Pos)                        /*!< USIC_CH SCTR: PDL Mask                  */\r
+#define USIC_CH_SCTR_DSM_Pos                  2                                                       /*!< USIC_CH SCTR: DSM Position              */\r
+#define USIC_CH_SCTR_DSM_Msk                  (0x03UL << USIC_CH_SCTR_DSM_Pos)                        /*!< USIC_CH SCTR: DSM Mask                  */\r
+#define USIC_CH_SCTR_HPCDIR_Pos               4                                                       /*!< USIC_CH SCTR: HPCDIR Position           */\r
+#define USIC_CH_SCTR_HPCDIR_Msk               (0x01UL << USIC_CH_SCTR_HPCDIR_Pos)                     /*!< USIC_CH SCTR: HPCDIR Mask               */\r
+#define USIC_CH_SCTR_DOCFG_Pos                6                                                       /*!< USIC_CH SCTR: DOCFG Position            */\r
+#define USIC_CH_SCTR_DOCFG_Msk                (0x03UL << USIC_CH_SCTR_DOCFG_Pos)                      /*!< USIC_CH SCTR: DOCFG Mask                */\r
+#define USIC_CH_SCTR_TRM_Pos                  8                                                       /*!< USIC_CH SCTR: TRM Position              */\r
+#define USIC_CH_SCTR_TRM_Msk                  (0x03UL << USIC_CH_SCTR_TRM_Pos)                        /*!< USIC_CH SCTR: TRM Mask                  */\r
+#define USIC_CH_SCTR_FLE_Pos                  16                                                      /*!< USIC_CH SCTR: FLE Position              */\r
+#define USIC_CH_SCTR_FLE_Msk                  (0x3fUL << USIC_CH_SCTR_FLE_Pos)                        /*!< USIC_CH SCTR: FLE Mask                  */\r
+#define USIC_CH_SCTR_WLE_Pos                  24                                                      /*!< USIC_CH SCTR: WLE Position              */\r
+#define USIC_CH_SCTR_WLE_Msk                  (0x0fUL << USIC_CH_SCTR_WLE_Pos)                        /*!< USIC_CH SCTR: WLE Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_TCSR  -------------------------------- */\r
+#define USIC_CH_TCSR_WLEMD_Pos                0                                                       /*!< USIC_CH TCSR: WLEMD Position            */\r
+#define USIC_CH_TCSR_WLEMD_Msk                (0x01UL << USIC_CH_TCSR_WLEMD_Pos)                      /*!< USIC_CH TCSR: WLEMD Mask                */\r
+#define USIC_CH_TCSR_SELMD_Pos                1                                                       /*!< USIC_CH TCSR: SELMD Position            */\r
+#define USIC_CH_TCSR_SELMD_Msk                (0x01UL << USIC_CH_TCSR_SELMD_Pos)                      /*!< USIC_CH TCSR: SELMD Mask                */\r
+#define USIC_CH_TCSR_FLEMD_Pos                2                                                       /*!< USIC_CH TCSR: FLEMD Position            */\r
+#define USIC_CH_TCSR_FLEMD_Msk                (0x01UL << USIC_CH_TCSR_FLEMD_Pos)                      /*!< USIC_CH TCSR: FLEMD Mask                */\r
+#define USIC_CH_TCSR_WAMD_Pos                 3                                                       /*!< USIC_CH TCSR: WAMD Position             */\r
+#define USIC_CH_TCSR_WAMD_Msk                 (0x01UL << USIC_CH_TCSR_WAMD_Pos)                       /*!< USIC_CH TCSR: WAMD Mask                 */\r
+#define USIC_CH_TCSR_HPCMD_Pos                4                                                       /*!< USIC_CH TCSR: HPCMD Position            */\r
+#define USIC_CH_TCSR_HPCMD_Msk                (0x01UL << USIC_CH_TCSR_HPCMD_Pos)                      /*!< USIC_CH TCSR: HPCMD Mask                */\r
+#define USIC_CH_TCSR_SOF_Pos                  5                                                       /*!< USIC_CH TCSR: SOF Position              */\r
+#define USIC_CH_TCSR_SOF_Msk                  (0x01UL << USIC_CH_TCSR_SOF_Pos)                        /*!< USIC_CH TCSR: SOF Mask                  */\r
+#define USIC_CH_TCSR_EOF_Pos                  6                                                       /*!< USIC_CH TCSR: EOF Position              */\r
+#define USIC_CH_TCSR_EOF_Msk                  (0x01UL << USIC_CH_TCSR_EOF_Pos)                        /*!< USIC_CH TCSR: EOF Mask                  */\r
+#define USIC_CH_TCSR_TDV_Pos                  7                                                       /*!< USIC_CH TCSR: TDV Position              */\r
+#define USIC_CH_TCSR_TDV_Msk                  (0x01UL << USIC_CH_TCSR_TDV_Pos)                        /*!< USIC_CH TCSR: TDV Mask                  */\r
+#define USIC_CH_TCSR_TDSSM_Pos                8                                                       /*!< USIC_CH TCSR: TDSSM Position            */\r
+#define USIC_CH_TCSR_TDSSM_Msk                (0x01UL << USIC_CH_TCSR_TDSSM_Pos)                      /*!< USIC_CH TCSR: TDSSM Mask                */\r
+#define USIC_CH_TCSR_TDEN_Pos                 10                                                      /*!< USIC_CH TCSR: TDEN Position             */\r
+#define USIC_CH_TCSR_TDEN_Msk                 (0x03UL << USIC_CH_TCSR_TDEN_Pos)                       /*!< USIC_CH TCSR: TDEN Mask                 */\r
+#define USIC_CH_TCSR_TDVTR_Pos                12                                                      /*!< USIC_CH TCSR: TDVTR Position            */\r
+#define USIC_CH_TCSR_TDVTR_Msk                (0x01UL << USIC_CH_TCSR_TDVTR_Pos)                      /*!< USIC_CH TCSR: TDVTR Mask                */\r
+#define USIC_CH_TCSR_WA_Pos                   13                                                      /*!< USIC_CH TCSR: WA Position               */\r
+#define USIC_CH_TCSR_WA_Msk                   (0x01UL << USIC_CH_TCSR_WA_Pos)                         /*!< USIC_CH TCSR: WA Mask                   */\r
+#define USIC_CH_TCSR_TSOF_Pos                 24                                                      /*!< USIC_CH TCSR: TSOF Position             */\r
+#define USIC_CH_TCSR_TSOF_Msk                 (0x01UL << USIC_CH_TCSR_TSOF_Pos)                       /*!< USIC_CH TCSR: TSOF Mask                 */\r
+#define USIC_CH_TCSR_TV_Pos                   26                                                      /*!< USIC_CH TCSR: TV Position               */\r
+#define USIC_CH_TCSR_TV_Msk                   (0x01UL << USIC_CH_TCSR_TV_Pos)                         /*!< USIC_CH TCSR: TV Mask                   */\r
+#define USIC_CH_TCSR_TVC_Pos                  27                                                      /*!< USIC_CH TCSR: TVC Position              */\r
+#define USIC_CH_TCSR_TVC_Msk                  (0x01UL << USIC_CH_TCSR_TVC_Pos)                        /*!< USIC_CH TCSR: TVC Mask                  */\r
+#define USIC_CH_TCSR_TE_Pos                   28                                                      /*!< USIC_CH TCSR: TE Position               */\r
+#define USIC_CH_TCSR_TE_Msk                   (0x01UL << USIC_CH_TCSR_TE_Pos)                         /*!< USIC_CH TCSR: TE Mask                   */\r
+\r
+/* ---------------------------------  USIC_CH_PCR  -------------------------------- */\r
+#define USIC_CH_PCR_CTR0_Pos                  0                                                       /*!< USIC_CH PCR: CTR0 Position              */\r
+#define USIC_CH_PCR_CTR0_Msk                  (0x01UL << USIC_CH_PCR_CTR0_Pos)                        /*!< USIC_CH PCR: CTR0 Mask                  */\r
+#define USIC_CH_PCR_CTR1_Pos                  1                                                       /*!< USIC_CH PCR: CTR1 Position              */\r
+#define USIC_CH_PCR_CTR1_Msk                  (0x01UL << USIC_CH_PCR_CTR1_Pos)                        /*!< USIC_CH PCR: CTR1 Mask                  */\r
+#define USIC_CH_PCR_CTR2_Pos                  2                                                       /*!< USIC_CH PCR: CTR2 Position              */\r
+#define USIC_CH_PCR_CTR2_Msk                  (0x01UL << USIC_CH_PCR_CTR2_Pos)                        /*!< USIC_CH PCR: CTR2 Mask                  */\r
+#define USIC_CH_PCR_CTR3_Pos                  3                                                       /*!< USIC_CH PCR: CTR3 Position              */\r
+#define USIC_CH_PCR_CTR3_Msk                  (0x01UL << USIC_CH_PCR_CTR3_Pos)                        /*!< USIC_CH PCR: CTR3 Mask                  */\r
+#define USIC_CH_PCR_CTR4_Pos                  4                                                       /*!< USIC_CH PCR: CTR4 Position              */\r
+#define USIC_CH_PCR_CTR4_Msk                  (0x01UL << USIC_CH_PCR_CTR4_Pos)                        /*!< USIC_CH PCR: CTR4 Mask                  */\r
+#define USIC_CH_PCR_CTR5_Pos                  5                                                       /*!< USIC_CH PCR: CTR5 Position              */\r
+#define USIC_CH_PCR_CTR5_Msk                  (0x01UL << USIC_CH_PCR_CTR5_Pos)                        /*!< USIC_CH PCR: CTR5 Mask                  */\r
+#define USIC_CH_PCR_CTR6_Pos                  6                                                       /*!< USIC_CH PCR: CTR6 Position              */\r
+#define USIC_CH_PCR_CTR6_Msk                  (0x01UL << USIC_CH_PCR_CTR6_Pos)                        /*!< USIC_CH PCR: CTR6 Mask                  */\r
+#define USIC_CH_PCR_CTR7_Pos                  7                                                       /*!< USIC_CH PCR: CTR7 Position              */\r
+#define USIC_CH_PCR_CTR7_Msk                  (0x01UL << USIC_CH_PCR_CTR7_Pos)                        /*!< USIC_CH PCR: CTR7 Mask                  */\r
+#define USIC_CH_PCR_CTR8_Pos                  8                                                       /*!< USIC_CH PCR: CTR8 Position              */\r
+#define USIC_CH_PCR_CTR8_Msk                  (0x01UL << USIC_CH_PCR_CTR8_Pos)                        /*!< USIC_CH PCR: CTR8 Mask                  */\r
+#define USIC_CH_PCR_CTR9_Pos                  9                                                       /*!< USIC_CH PCR: CTR9 Position              */\r
+#define USIC_CH_PCR_CTR9_Msk                  (0x01UL << USIC_CH_PCR_CTR9_Pos)                        /*!< USIC_CH PCR: CTR9 Mask                  */\r
+#define USIC_CH_PCR_CTR10_Pos                 10                                                      /*!< USIC_CH PCR: CTR10 Position             */\r
+#define USIC_CH_PCR_CTR10_Msk                 (0x01UL << USIC_CH_PCR_CTR10_Pos)                       /*!< USIC_CH PCR: CTR10 Mask                 */\r
+#define USIC_CH_PCR_CTR11_Pos                 11                                                      /*!< USIC_CH PCR: CTR11 Position             */\r
+#define USIC_CH_PCR_CTR11_Msk                 (0x01UL << USIC_CH_PCR_CTR11_Pos)                       /*!< USIC_CH PCR: CTR11 Mask                 */\r
+#define USIC_CH_PCR_CTR12_Pos                 12                                                      /*!< USIC_CH PCR: CTR12 Position             */\r
+#define USIC_CH_PCR_CTR12_Msk                 (0x01UL << USIC_CH_PCR_CTR12_Pos)                       /*!< USIC_CH PCR: CTR12 Mask                 */\r
+#define USIC_CH_PCR_CTR13_Pos                 13                                                      /*!< USIC_CH PCR: CTR13 Position             */\r
+#define USIC_CH_PCR_CTR13_Msk                 (0x01UL << USIC_CH_PCR_CTR13_Pos)                       /*!< USIC_CH PCR: CTR13 Mask                 */\r
+#define USIC_CH_PCR_CTR14_Pos                 14                                                      /*!< USIC_CH PCR: CTR14 Position             */\r
+#define USIC_CH_PCR_CTR14_Msk                 (0x01UL << USIC_CH_PCR_CTR14_Pos)                       /*!< USIC_CH PCR: CTR14 Mask                 */\r
+#define USIC_CH_PCR_CTR15_Pos                 15                                                      /*!< USIC_CH PCR: CTR15 Position             */\r
+#define USIC_CH_PCR_CTR15_Msk                 (0x01UL << USIC_CH_PCR_CTR15_Pos)                       /*!< USIC_CH PCR: CTR15 Mask                 */\r
+#define USIC_CH_PCR_CTR16_Pos                 16                                                      /*!< USIC_CH PCR: CTR16 Position             */\r
+#define USIC_CH_PCR_CTR16_Msk                 (0x01UL << USIC_CH_PCR_CTR16_Pos)                       /*!< USIC_CH PCR: CTR16 Mask                 */\r
+#define USIC_CH_PCR_CTR17_Pos                 17                                                      /*!< USIC_CH PCR: CTR17 Position             */\r
+#define USIC_CH_PCR_CTR17_Msk                 (0x01UL << USIC_CH_PCR_CTR17_Pos)                       /*!< USIC_CH PCR: CTR17 Mask                 */\r
+#define USIC_CH_PCR_CTR18_Pos                 18                                                      /*!< USIC_CH PCR: CTR18 Position             */\r
+#define USIC_CH_PCR_CTR18_Msk                 (0x01UL << USIC_CH_PCR_CTR18_Pos)                       /*!< USIC_CH PCR: CTR18 Mask                 */\r
+#define USIC_CH_PCR_CTR19_Pos                 19                                                      /*!< USIC_CH PCR: CTR19 Position             */\r
+#define USIC_CH_PCR_CTR19_Msk                 (0x01UL << USIC_CH_PCR_CTR19_Pos)                       /*!< USIC_CH PCR: CTR19 Mask                 */\r
+#define USIC_CH_PCR_CTR20_Pos                 20                                                      /*!< USIC_CH PCR: CTR20 Position             */\r
+#define USIC_CH_PCR_CTR20_Msk                 (0x01UL << USIC_CH_PCR_CTR20_Pos)                       /*!< USIC_CH PCR: CTR20 Mask                 */\r
+#define USIC_CH_PCR_CTR21_Pos                 21                                                      /*!< USIC_CH PCR: CTR21 Position             */\r
+#define USIC_CH_PCR_CTR21_Msk                 (0x01UL << USIC_CH_PCR_CTR21_Pos)                       /*!< USIC_CH PCR: CTR21 Mask                 */\r
+#define USIC_CH_PCR_CTR22_Pos                 22                                                      /*!< USIC_CH PCR: CTR22 Position             */\r
+#define USIC_CH_PCR_CTR22_Msk                 (0x01UL << USIC_CH_PCR_CTR22_Pos)                       /*!< USIC_CH PCR: CTR22 Mask                 */\r
+#define USIC_CH_PCR_CTR23_Pos                 23                                                      /*!< USIC_CH PCR: CTR23 Position             */\r
+#define USIC_CH_PCR_CTR23_Msk                 (0x01UL << USIC_CH_PCR_CTR23_Pos)                       /*!< USIC_CH PCR: CTR23 Mask                 */\r
+#define USIC_CH_PCR_CTR24_Pos                 24                                                      /*!< USIC_CH PCR: CTR24 Position             */\r
+#define USIC_CH_PCR_CTR24_Msk                 (0x01UL << USIC_CH_PCR_CTR24_Pos)                       /*!< USIC_CH PCR: CTR24 Mask                 */\r
+#define USIC_CH_PCR_CTR25_Pos                 25                                                      /*!< USIC_CH PCR: CTR25 Position             */\r
+#define USIC_CH_PCR_CTR25_Msk                 (0x01UL << USIC_CH_PCR_CTR25_Pos)                       /*!< USIC_CH PCR: CTR25 Mask                 */\r
+#define USIC_CH_PCR_CTR26_Pos                 26                                                      /*!< USIC_CH PCR: CTR26 Position             */\r
+#define USIC_CH_PCR_CTR26_Msk                 (0x01UL << USIC_CH_PCR_CTR26_Pos)                       /*!< USIC_CH PCR: CTR26 Mask                 */\r
+#define USIC_CH_PCR_CTR27_Pos                 27                                                      /*!< USIC_CH PCR: CTR27 Position             */\r
+#define USIC_CH_PCR_CTR27_Msk                 (0x01UL << USIC_CH_PCR_CTR27_Pos)                       /*!< USIC_CH PCR: CTR27 Mask                 */\r
+#define USIC_CH_PCR_CTR28_Pos                 28                                                      /*!< USIC_CH PCR: CTR28 Position             */\r
+#define USIC_CH_PCR_CTR28_Msk                 (0x01UL << USIC_CH_PCR_CTR28_Pos)                       /*!< USIC_CH PCR: CTR28 Mask                 */\r
+#define USIC_CH_PCR_CTR29_Pos                 29                                                      /*!< USIC_CH PCR: CTR29 Position             */\r
+#define USIC_CH_PCR_CTR29_Msk                 (0x01UL << USIC_CH_PCR_CTR29_Pos)                       /*!< USIC_CH PCR: CTR29 Mask                 */\r
+#define USIC_CH_PCR_CTR30_Pos                 30                                                      /*!< USIC_CH PCR: CTR30 Position             */\r
+#define USIC_CH_PCR_CTR30_Msk                 (0x01UL << USIC_CH_PCR_CTR30_Pos)                       /*!< USIC_CH PCR: CTR30 Mask                 */\r
+#define USIC_CH_PCR_CTR31_Pos                 31                                                      /*!< USIC_CH PCR: CTR31 Position             */\r
+#define USIC_CH_PCR_CTR31_Msk                 (0x01UL << USIC_CH_PCR_CTR31_Pos)                       /*!< USIC_CH PCR: CTR31 Mask                 */\r
+\r
+/* -----------------------------  USIC_CH_PCR_ASCMode  ---------------------------- */\r
+#define USIC_CH_PCR_ASCMode_SMD_Pos           0                                                       /*!< USIC_CH PCR_ASCMode: SMD Position       */\r
+#define USIC_CH_PCR_ASCMode_SMD_Msk           (0x01UL << USIC_CH_PCR_ASCMode_SMD_Pos)                 /*!< USIC_CH PCR_ASCMode: SMD Mask           */\r
+#define USIC_CH_PCR_ASCMode_STPB_Pos          1                                                       /*!< USIC_CH PCR_ASCMode: STPB Position      */\r
+#define USIC_CH_PCR_ASCMode_STPB_Msk          (0x01UL << USIC_CH_PCR_ASCMode_STPB_Pos)                /*!< USIC_CH PCR_ASCMode: STPB Mask          */\r
+#define USIC_CH_PCR_ASCMode_IDM_Pos           2                                                       /*!< USIC_CH PCR_ASCMode: IDM Position       */\r
+#define USIC_CH_PCR_ASCMode_IDM_Msk           (0x01UL << USIC_CH_PCR_ASCMode_IDM_Pos)                 /*!< USIC_CH PCR_ASCMode: IDM Mask           */\r
+#define USIC_CH_PCR_ASCMode_SBIEN_Pos         3                                                       /*!< USIC_CH PCR_ASCMode: SBIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_SBIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_SBIEN_Pos)               /*!< USIC_CH PCR_ASCMode: SBIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_CDEN_Pos          4                                                       /*!< USIC_CH PCR_ASCMode: CDEN Position      */\r
+#define USIC_CH_PCR_ASCMode_CDEN_Msk          (0x01UL << USIC_CH_PCR_ASCMode_CDEN_Pos)                /*!< USIC_CH PCR_ASCMode: CDEN Mask          */\r
+#define USIC_CH_PCR_ASCMode_RNIEN_Pos         5                                                       /*!< USIC_CH PCR_ASCMode: RNIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_RNIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_RNIEN_Pos)               /*!< USIC_CH PCR_ASCMode: RNIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_FEIEN_Pos         6                                                       /*!< USIC_CH PCR_ASCMode: FEIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_FEIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_FEIEN_Pos)               /*!< USIC_CH PCR_ASCMode: FEIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_FFIEN_Pos         7                                                       /*!< USIC_CH PCR_ASCMode: FFIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_FFIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_FFIEN_Pos)               /*!< USIC_CH PCR_ASCMode: FFIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_SP_Pos            8                                                       /*!< USIC_CH PCR_ASCMode: SP Position        */\r
+#define USIC_CH_PCR_ASCMode_SP_Msk            (0x1fUL << USIC_CH_PCR_ASCMode_SP_Pos)                  /*!< USIC_CH PCR_ASCMode: SP Mask            */\r
+#define USIC_CH_PCR_ASCMode_PL_Pos            13                                                      /*!< USIC_CH PCR_ASCMode: PL Position        */\r
+#define USIC_CH_PCR_ASCMode_PL_Msk            (0x07UL << USIC_CH_PCR_ASCMode_PL_Pos)                  /*!< USIC_CH PCR_ASCMode: PL Mask            */\r
+#define USIC_CH_PCR_ASCMode_RSTEN_Pos         16                                                      /*!< USIC_CH PCR_ASCMode: RSTEN Position     */\r
+#define USIC_CH_PCR_ASCMode_RSTEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_RSTEN_Pos)               /*!< USIC_CH PCR_ASCMode: RSTEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_TSTEN_Pos         17                                                      /*!< USIC_CH PCR_ASCMode: TSTEN Position     */\r
+#define USIC_CH_PCR_ASCMode_TSTEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_TSTEN_Pos)               /*!< USIC_CH PCR_ASCMode: TSTEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_ASCMode: MCLK Position      */\r
+#define USIC_CH_PCR_ASCMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_ASCMode_MCLK_Pos)                /*!< USIC_CH PCR_ASCMode: MCLK Mask          */\r
+\r
+/* -----------------------------  USIC_CH_PCR_SSCMode  ---------------------------- */\r
+#define USIC_CH_PCR_SSCMode_MSLSEN_Pos        0                                                       /*!< USIC_CH PCR_SSCMode: MSLSEN Position    */\r
+#define USIC_CH_PCR_SSCMode_MSLSEN_Msk        (0x01UL << USIC_CH_PCR_SSCMode_MSLSEN_Pos)              /*!< USIC_CH PCR_SSCMode: MSLSEN Mask        */\r
+#define USIC_CH_PCR_SSCMode_SELCTR_Pos        1                                                       /*!< USIC_CH PCR_SSCMode: SELCTR Position    */\r
+#define USIC_CH_PCR_SSCMode_SELCTR_Msk        (0x01UL << USIC_CH_PCR_SSCMode_SELCTR_Pos)              /*!< USIC_CH PCR_SSCMode: SELCTR Mask        */\r
+#define USIC_CH_PCR_SSCMode_SELINV_Pos        2                                                       /*!< USIC_CH PCR_SSCMode: SELINV Position    */\r
+#define USIC_CH_PCR_SSCMode_SELINV_Msk        (0x01UL << USIC_CH_PCR_SSCMode_SELINV_Pos)              /*!< USIC_CH PCR_SSCMode: SELINV Mask        */\r
+#define USIC_CH_PCR_SSCMode_FEM_Pos           3                                                       /*!< USIC_CH PCR_SSCMode: FEM Position       */\r
+#define USIC_CH_PCR_SSCMode_FEM_Msk           (0x01UL << USIC_CH_PCR_SSCMode_FEM_Pos)                 /*!< USIC_CH PCR_SSCMode: FEM Mask           */\r
+#define USIC_CH_PCR_SSCMode_CTQSEL1_Pos       4                                                       /*!< USIC_CH PCR_SSCMode: CTQSEL1 Position   */\r
+#define USIC_CH_PCR_SSCMode_CTQSEL1_Msk       (0x03UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos)             /*!< USIC_CH PCR_SSCMode: CTQSEL1 Mask       */\r
+#define USIC_CH_PCR_SSCMode_PCTQ1_Pos         6                                                       /*!< USIC_CH PCR_SSCMode: PCTQ1 Position     */\r
+#define USIC_CH_PCR_SSCMode_PCTQ1_Msk         (0x03UL << USIC_CH_PCR_SSCMode_PCTQ1_Pos)               /*!< USIC_CH PCR_SSCMode: PCTQ1 Mask         */\r
+#define USIC_CH_PCR_SSCMode_DCTQ1_Pos         8                                                       /*!< USIC_CH PCR_SSCMode: DCTQ1 Position     */\r
+#define USIC_CH_PCR_SSCMode_DCTQ1_Msk         (0x1fUL << USIC_CH_PCR_SSCMode_DCTQ1_Pos)               /*!< USIC_CH PCR_SSCMode: DCTQ1 Mask         */\r
+#define USIC_CH_PCR_SSCMode_PARIEN_Pos        13                                                      /*!< USIC_CH PCR_SSCMode: PARIEN Position    */\r
+#define USIC_CH_PCR_SSCMode_PARIEN_Msk        (0x01UL << USIC_CH_PCR_SSCMode_PARIEN_Pos)              /*!< USIC_CH PCR_SSCMode: PARIEN Mask        */\r
+#define USIC_CH_PCR_SSCMode_MSLSIEN_Pos       14                                                      /*!< USIC_CH PCR_SSCMode: MSLSIEN Position   */\r
+#define USIC_CH_PCR_SSCMode_MSLSIEN_Msk       (0x01UL << USIC_CH_PCR_SSCMode_MSLSIEN_Pos)             /*!< USIC_CH PCR_SSCMode: MSLSIEN Mask       */\r
+#define USIC_CH_PCR_SSCMode_DX2TIEN_Pos       15                                                      /*!< USIC_CH PCR_SSCMode: DX2TIEN Position   */\r
+#define USIC_CH_PCR_SSCMode_DX2TIEN_Msk       (0x01UL << USIC_CH_PCR_SSCMode_DX2TIEN_Pos)             /*!< USIC_CH PCR_SSCMode: DX2TIEN Mask       */\r
+#define USIC_CH_PCR_SSCMode_SELO_Pos          16                                                      /*!< USIC_CH PCR_SSCMode: SELO Position      */\r
+#define USIC_CH_PCR_SSCMode_SELO_Msk          (0x000000ffUL << USIC_CH_PCR_SSCMode_SELO_Pos)          /*!< USIC_CH PCR_SSCMode: SELO Mask          */\r
+#define USIC_CH_PCR_SSCMode_TIWEN_Pos         24                                                      /*!< USIC_CH PCR_SSCMode: TIWEN Position     */\r
+#define USIC_CH_PCR_SSCMode_TIWEN_Msk         (0x01UL << USIC_CH_PCR_SSCMode_TIWEN_Pos)               /*!< USIC_CH PCR_SSCMode: TIWEN Mask         */\r
+#define USIC_CH_PCR_SSCMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_SSCMode: MCLK Position      */\r
+#define USIC_CH_PCR_SSCMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_SSCMode_MCLK_Pos)                /*!< USIC_CH PCR_SSCMode: MCLK Mask          */\r
+\r
+/* -----------------------------  USIC_CH_PCR_IICMode  ---------------------------- */\r
+#define USIC_CH_PCR_IICMode_SLAD_Pos          0                                                       /*!< USIC_CH PCR_IICMode: SLAD Position      */\r
+#define USIC_CH_PCR_IICMode_SLAD_Msk          (0x0000ffffUL << USIC_CH_PCR_IICMode_SLAD_Pos)          /*!< USIC_CH PCR_IICMode: SLAD Mask          */\r
+#define USIC_CH_PCR_IICMode_ACK00_Pos         16                                                      /*!< USIC_CH PCR_IICMode: ACK00 Position     */\r
+#define USIC_CH_PCR_IICMode_ACK00_Msk         (0x01UL << USIC_CH_PCR_IICMode_ACK00_Pos)               /*!< USIC_CH PCR_IICMode: ACK00 Mask         */\r
+#define USIC_CH_PCR_IICMode_STIM_Pos          17                                                      /*!< USIC_CH PCR_IICMode: STIM Position      */\r
+#define USIC_CH_PCR_IICMode_STIM_Msk          (0x01UL << USIC_CH_PCR_IICMode_STIM_Pos)                /*!< USIC_CH PCR_IICMode: STIM Mask          */\r
+#define USIC_CH_PCR_IICMode_SCRIEN_Pos        18                                                      /*!< USIC_CH PCR_IICMode: SCRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_SCRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_SCRIEN_Pos)              /*!< USIC_CH PCR_IICMode: SCRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_RSCRIEN_Pos       19                                                      /*!< USIC_CH PCR_IICMode: RSCRIEN Position   */\r
+#define USIC_CH_PCR_IICMode_RSCRIEN_Msk       (0x01UL << USIC_CH_PCR_IICMode_RSCRIEN_Pos)             /*!< USIC_CH PCR_IICMode: RSCRIEN Mask       */\r
+#define USIC_CH_PCR_IICMode_PCRIEN_Pos        20                                                      /*!< USIC_CH PCR_IICMode: PCRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_PCRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_PCRIEN_Pos)              /*!< USIC_CH PCR_IICMode: PCRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_NACKIEN_Pos       21                                                      /*!< USIC_CH PCR_IICMode: NACKIEN Position   */\r
+#define USIC_CH_PCR_IICMode_NACKIEN_Msk       (0x01UL << USIC_CH_PCR_IICMode_NACKIEN_Pos)             /*!< USIC_CH PCR_IICMode: NACKIEN Mask       */\r
+#define USIC_CH_PCR_IICMode_ARLIEN_Pos        22                                                      /*!< USIC_CH PCR_IICMode: ARLIEN Position    */\r
+#define USIC_CH_PCR_IICMode_ARLIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_ARLIEN_Pos)              /*!< USIC_CH PCR_IICMode: ARLIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_SRRIEN_Pos        23                                                      /*!< USIC_CH PCR_IICMode: SRRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_SRRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_SRRIEN_Pos)              /*!< USIC_CH PCR_IICMode: SRRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_ERRIEN_Pos        24                                                      /*!< USIC_CH PCR_IICMode: ERRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_ERRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_ERRIEN_Pos)              /*!< USIC_CH PCR_IICMode: ERRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_SACKDIS_Pos       25                                                      /*!< USIC_CH PCR_IICMode: SACKDIS Position   */\r
+#define USIC_CH_PCR_IICMode_SACKDIS_Msk       (0x01UL << USIC_CH_PCR_IICMode_SACKDIS_Pos)             /*!< USIC_CH PCR_IICMode: SACKDIS Mask       */\r
+#define USIC_CH_PCR_IICMode_HDEL_Pos          26                                                      /*!< USIC_CH PCR_IICMode: HDEL Position      */\r
+#define USIC_CH_PCR_IICMode_HDEL_Msk          (0x0fUL << USIC_CH_PCR_IICMode_HDEL_Pos)                /*!< USIC_CH PCR_IICMode: HDEL Mask          */\r
+#define USIC_CH_PCR_IICMode_ACKIEN_Pos        30                                                      /*!< USIC_CH PCR_IICMode: ACKIEN Position    */\r
+#define USIC_CH_PCR_IICMode_ACKIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_ACKIEN_Pos)              /*!< USIC_CH PCR_IICMode: ACKIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_IICMode: MCLK Position      */\r
+#define USIC_CH_PCR_IICMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_IICMode_MCLK_Pos)                /*!< USIC_CH PCR_IICMode: MCLK Mask          */\r
+\r
+/* -----------------------------  USIC_CH_PCR_IISMode  ---------------------------- */\r
+#define USIC_CH_PCR_IISMode_WAGEN_Pos         0                                                       /*!< USIC_CH PCR_IISMode: WAGEN Position     */\r
+#define USIC_CH_PCR_IISMode_WAGEN_Msk         (0x01UL << USIC_CH_PCR_IISMode_WAGEN_Pos)               /*!< USIC_CH PCR_IISMode: WAGEN Mask         */\r
+#define USIC_CH_PCR_IISMode_DTEN_Pos          1                                                       /*!< USIC_CH PCR_IISMode: DTEN Position      */\r
+#define USIC_CH_PCR_IISMode_DTEN_Msk          (0x01UL << USIC_CH_PCR_IISMode_DTEN_Pos)                /*!< USIC_CH PCR_IISMode: DTEN Mask          */\r
+#define USIC_CH_PCR_IISMode_SELINV_Pos        2                                                       /*!< USIC_CH PCR_IISMode: SELINV Position    */\r
+#define USIC_CH_PCR_IISMode_SELINV_Msk        (0x01UL << USIC_CH_PCR_IISMode_SELINV_Pos)              /*!< USIC_CH PCR_IISMode: SELINV Mask        */\r
+#define USIC_CH_PCR_IISMode_WAFEIEN_Pos       4                                                       /*!< USIC_CH PCR_IISMode: WAFEIEN Position   */\r
+#define USIC_CH_PCR_IISMode_WAFEIEN_Msk       (0x01UL << USIC_CH_PCR_IISMode_WAFEIEN_Pos)             /*!< USIC_CH PCR_IISMode: WAFEIEN Mask       */\r
+#define USIC_CH_PCR_IISMode_WAREIEN_Pos       5                                                       /*!< USIC_CH PCR_IISMode: WAREIEN Position   */\r
+#define USIC_CH_PCR_IISMode_WAREIEN_Msk       (0x01UL << USIC_CH_PCR_IISMode_WAREIEN_Pos)             /*!< USIC_CH PCR_IISMode: WAREIEN Mask       */\r
+#define USIC_CH_PCR_IISMode_ENDIEN_Pos        6                                                       /*!< USIC_CH PCR_IISMode: ENDIEN Position    */\r
+#define USIC_CH_PCR_IISMode_ENDIEN_Msk        (0x01UL << USIC_CH_PCR_IISMode_ENDIEN_Pos)              /*!< USIC_CH PCR_IISMode: ENDIEN Mask        */\r
+#define USIC_CH_PCR_IISMode_DX2TIEN_Pos       15                                                      /*!< USIC_CH PCR_IISMode: DX2TIEN Position   */\r
+#define USIC_CH_PCR_IISMode_DX2TIEN_Msk       (0x01UL << USIC_CH_PCR_IISMode_DX2TIEN_Pos)             /*!< USIC_CH PCR_IISMode: DX2TIEN Mask       */\r
+#define USIC_CH_PCR_IISMode_TDEL_Pos          16                                                      /*!< USIC_CH PCR_IISMode: TDEL Position      */\r
+#define USIC_CH_PCR_IISMode_TDEL_Msk          (0x3fUL << USIC_CH_PCR_IISMode_TDEL_Pos)                /*!< USIC_CH PCR_IISMode: TDEL Mask          */\r
+#define USIC_CH_PCR_IISMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_IISMode: MCLK Position      */\r
+#define USIC_CH_PCR_IISMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_IISMode_MCLK_Pos)                /*!< USIC_CH PCR_IISMode: MCLK Mask          */\r
+\r
+/* ---------------------------------  USIC_CH_CCR  -------------------------------- */\r
+#define USIC_CH_CCR_MODE_Pos                  0                                                       /*!< USIC_CH CCR: MODE Position              */\r
+#define USIC_CH_CCR_MODE_Msk                  (0x0fUL << USIC_CH_CCR_MODE_Pos)                        /*!< USIC_CH CCR: MODE Mask                  */\r
+#define USIC_CH_CCR_HPCEN_Pos                 6                                                       /*!< USIC_CH CCR: HPCEN Position             */\r
+#define USIC_CH_CCR_HPCEN_Msk                 (0x03UL << USIC_CH_CCR_HPCEN_Pos)                       /*!< USIC_CH CCR: HPCEN Mask                 */\r
+#define USIC_CH_CCR_PM_Pos                    8                                                       /*!< USIC_CH CCR: PM Position                */\r
+#define USIC_CH_CCR_PM_Msk                    (0x03UL << USIC_CH_CCR_PM_Pos)                          /*!< USIC_CH CCR: PM Mask                    */\r
+#define USIC_CH_CCR_RSIEN_Pos                 10                                                      /*!< USIC_CH CCR: RSIEN Position             */\r
+#define USIC_CH_CCR_RSIEN_Msk                 (0x01UL << USIC_CH_CCR_RSIEN_Pos)                       /*!< USIC_CH CCR: RSIEN Mask                 */\r
+#define USIC_CH_CCR_DLIEN_Pos                 11                                                      /*!< USIC_CH CCR: DLIEN Position             */\r
+#define USIC_CH_CCR_DLIEN_Msk                 (0x01UL << USIC_CH_CCR_DLIEN_Pos)                       /*!< USIC_CH CCR: DLIEN Mask                 */\r
+#define USIC_CH_CCR_TSIEN_Pos                 12                                                      /*!< USIC_CH CCR: TSIEN Position             */\r
+#define USIC_CH_CCR_TSIEN_Msk                 (0x01UL << USIC_CH_CCR_TSIEN_Pos)                       /*!< USIC_CH CCR: TSIEN Mask                 */\r
+#define USIC_CH_CCR_TBIEN_Pos                 13                                                      /*!< USIC_CH CCR: TBIEN Position             */\r
+#define USIC_CH_CCR_TBIEN_Msk                 (0x01UL << USIC_CH_CCR_TBIEN_Pos)                       /*!< USIC_CH CCR: TBIEN Mask                 */\r
+#define USIC_CH_CCR_RIEN_Pos                  14                                                      /*!< USIC_CH CCR: RIEN Position              */\r
+#define USIC_CH_CCR_RIEN_Msk                  (0x01UL << USIC_CH_CCR_RIEN_Pos)                        /*!< USIC_CH CCR: RIEN Mask                  */\r
+#define USIC_CH_CCR_AIEN_Pos                  15                                                      /*!< USIC_CH CCR: AIEN Position              */\r
+#define USIC_CH_CCR_AIEN_Msk                  (0x01UL << USIC_CH_CCR_AIEN_Pos)                        /*!< USIC_CH CCR: AIEN Mask                  */\r
+#define USIC_CH_CCR_BRGIEN_Pos                16                                                      /*!< USIC_CH CCR: BRGIEN Position            */\r
+#define USIC_CH_CCR_BRGIEN_Msk                (0x01UL << USIC_CH_CCR_BRGIEN_Pos)                      /*!< USIC_CH CCR: BRGIEN Mask                */\r
+\r
+/* --------------------------------  USIC_CH_CMTR  -------------------------------- */\r
+#define USIC_CH_CMTR_CTV_Pos                  0                                                       /*!< USIC_CH CMTR: CTV Position              */\r
+#define USIC_CH_CMTR_CTV_Msk                  (0x000003ffUL << USIC_CH_CMTR_CTV_Pos)                  /*!< USIC_CH CMTR: CTV Mask                  */\r
+\r
+/* ---------------------------------  USIC_CH_PSR  -------------------------------- */\r
+#define USIC_CH_PSR_ST0_Pos                   0                                                       /*!< USIC_CH PSR: ST0 Position               */\r
+#define USIC_CH_PSR_ST0_Msk                   (0x01UL << USIC_CH_PSR_ST0_Pos)                         /*!< USIC_CH PSR: ST0 Mask                   */\r
+#define USIC_CH_PSR_ST1_Pos                   1                                                       /*!< USIC_CH PSR: ST1 Position               */\r
+#define USIC_CH_PSR_ST1_Msk                   (0x01UL << USIC_CH_PSR_ST1_Pos)                         /*!< USIC_CH PSR: ST1 Mask                   */\r
+#define USIC_CH_PSR_ST2_Pos                   2                                                       /*!< USIC_CH PSR: ST2 Position               */\r
+#define USIC_CH_PSR_ST2_Msk                   (0x01UL << USIC_CH_PSR_ST2_Pos)                         /*!< USIC_CH PSR: ST2 Mask                   */\r
+#define USIC_CH_PSR_ST3_Pos                   3                                                       /*!< USIC_CH PSR: ST3 Position               */\r
+#define USIC_CH_PSR_ST3_Msk                   (0x01UL << USIC_CH_PSR_ST3_Pos)                         /*!< USIC_CH PSR: ST3 Mask                   */\r
+#define USIC_CH_PSR_ST4_Pos                   4                                                       /*!< USIC_CH PSR: ST4 Position               */\r
+#define USIC_CH_PSR_ST4_Msk                   (0x01UL << USIC_CH_PSR_ST4_Pos)                         /*!< USIC_CH PSR: ST4 Mask                   */\r
+#define USIC_CH_PSR_ST5_Pos                   5                                                       /*!< USIC_CH PSR: ST5 Position               */\r
+#define USIC_CH_PSR_ST5_Msk                   (0x01UL << USIC_CH_PSR_ST5_Pos)                         /*!< USIC_CH PSR: ST5 Mask                   */\r
+#define USIC_CH_PSR_ST6_Pos                   6                                                       /*!< USIC_CH PSR: ST6 Position               */\r
+#define USIC_CH_PSR_ST6_Msk                   (0x01UL << USIC_CH_PSR_ST6_Pos)                         /*!< USIC_CH PSR: ST6 Mask                   */\r
+#define USIC_CH_PSR_ST7_Pos                   7                                                       /*!< USIC_CH PSR: ST7 Position               */\r
+#define USIC_CH_PSR_ST7_Msk                   (0x01UL << USIC_CH_PSR_ST7_Pos)                         /*!< USIC_CH PSR: ST7 Mask                   */\r
+#define USIC_CH_PSR_ST8_Pos                   8                                                       /*!< USIC_CH PSR: ST8 Position               */\r
+#define USIC_CH_PSR_ST8_Msk                   (0x01UL << USIC_CH_PSR_ST8_Pos)                         /*!< USIC_CH PSR: ST8 Mask                   */\r
+#define USIC_CH_PSR_ST9_Pos                   9                                                       /*!< USIC_CH PSR: ST9 Position               */\r
+#define USIC_CH_PSR_ST9_Msk                   (0x01UL << USIC_CH_PSR_ST9_Pos)                         /*!< USIC_CH PSR: ST9 Mask                   */\r
+#define USIC_CH_PSR_RSIF_Pos                  10                                                      /*!< USIC_CH PSR: RSIF Position              */\r
+#define USIC_CH_PSR_RSIF_Msk                  (0x01UL << USIC_CH_PSR_RSIF_Pos)                        /*!< USIC_CH PSR: RSIF Mask                  */\r
+#define USIC_CH_PSR_DLIF_Pos                  11                                                      /*!< USIC_CH PSR: DLIF Position              */\r
+#define USIC_CH_PSR_DLIF_Msk                  (0x01UL << USIC_CH_PSR_DLIF_Pos)                        /*!< USIC_CH PSR: DLIF Mask                  */\r
+#define USIC_CH_PSR_TSIF_Pos                  12                                                      /*!< USIC_CH PSR: TSIF Position              */\r
+#define USIC_CH_PSR_TSIF_Msk                  (0x01UL << USIC_CH_PSR_TSIF_Pos)                        /*!< USIC_CH PSR: TSIF Mask                  */\r
+#define USIC_CH_PSR_TBIF_Pos                  13                                                      /*!< USIC_CH PSR: TBIF Position              */\r
+#define USIC_CH_PSR_TBIF_Msk                  (0x01UL << USIC_CH_PSR_TBIF_Pos)                        /*!< USIC_CH PSR: TBIF Mask                  */\r
+#define USIC_CH_PSR_RIF_Pos                   14                                                      /*!< USIC_CH PSR: RIF Position               */\r
+#define USIC_CH_PSR_RIF_Msk                   (0x01UL << USIC_CH_PSR_RIF_Pos)                         /*!< USIC_CH PSR: RIF Mask                   */\r
+#define USIC_CH_PSR_AIF_Pos                   15                                                      /*!< USIC_CH PSR: AIF Position               */\r
+#define USIC_CH_PSR_AIF_Msk                   (0x01UL << USIC_CH_PSR_AIF_Pos)                         /*!< USIC_CH PSR: AIF Mask                   */\r
+#define USIC_CH_PSR_BRGIF_Pos                 16                                                      /*!< USIC_CH PSR: BRGIF Position             */\r
+#define USIC_CH_PSR_BRGIF_Msk                 (0x01UL << USIC_CH_PSR_BRGIF_Pos)                       /*!< USIC_CH PSR: BRGIF Mask                 */\r
+\r
+/* -----------------------------  USIC_CH_PSR_ASCMode  ---------------------------- */\r
+#define USIC_CH_PSR_ASCMode_TXIDLE_Pos        0                                                       /*!< USIC_CH PSR_ASCMode: TXIDLE Position    */\r
+#define USIC_CH_PSR_ASCMode_TXIDLE_Msk        (0x01UL << USIC_CH_PSR_ASCMode_TXIDLE_Pos)              /*!< USIC_CH PSR_ASCMode: TXIDLE Mask        */\r
+#define USIC_CH_PSR_ASCMode_RXIDLE_Pos        1                                                       /*!< USIC_CH PSR_ASCMode: RXIDLE Position    */\r
+#define USIC_CH_PSR_ASCMode_RXIDLE_Msk        (0x01UL << USIC_CH_PSR_ASCMode_RXIDLE_Pos)              /*!< USIC_CH PSR_ASCMode: RXIDLE Mask        */\r
+#define USIC_CH_PSR_ASCMode_SBD_Pos           2                                                       /*!< USIC_CH PSR_ASCMode: SBD Position       */\r
+#define USIC_CH_PSR_ASCMode_SBD_Msk           (0x01UL << USIC_CH_PSR_ASCMode_SBD_Pos)                 /*!< USIC_CH PSR_ASCMode: SBD Mask           */\r
+#define USIC_CH_PSR_ASCMode_COL_Pos           3                                                       /*!< USIC_CH PSR_ASCMode: COL Position       */\r
+#define USIC_CH_PSR_ASCMode_COL_Msk           (0x01UL << USIC_CH_PSR_ASCMode_COL_Pos)                 /*!< USIC_CH PSR_ASCMode: COL Mask           */\r
+#define USIC_CH_PSR_ASCMode_RNS_Pos           4                                                       /*!< USIC_CH PSR_ASCMode: RNS Position       */\r
+#define USIC_CH_PSR_ASCMode_RNS_Msk           (0x01UL << USIC_CH_PSR_ASCMode_RNS_Pos)                 /*!< USIC_CH PSR_ASCMode: RNS Mask           */\r
+#define USIC_CH_PSR_ASCMode_FER0_Pos          5                                                       /*!< USIC_CH PSR_ASCMode: FER0 Position      */\r
+#define USIC_CH_PSR_ASCMode_FER0_Msk          (0x01UL << USIC_CH_PSR_ASCMode_FER0_Pos)                /*!< USIC_CH PSR_ASCMode: FER0 Mask          */\r
+#define USIC_CH_PSR_ASCMode_FER1_Pos          6                                                       /*!< USIC_CH PSR_ASCMode: FER1 Position      */\r
+#define USIC_CH_PSR_ASCMode_FER1_Msk          (0x01UL << USIC_CH_PSR_ASCMode_FER1_Pos)                /*!< USIC_CH PSR_ASCMode: FER1 Mask          */\r
+#define USIC_CH_PSR_ASCMode_RFF_Pos           7                                                       /*!< USIC_CH PSR_ASCMode: RFF Position       */\r
+#define USIC_CH_PSR_ASCMode_RFF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_RFF_Pos)                 /*!< USIC_CH PSR_ASCMode: RFF Mask           */\r
+#define USIC_CH_PSR_ASCMode_TFF_Pos           8                                                       /*!< USIC_CH PSR_ASCMode: TFF Position       */\r
+#define USIC_CH_PSR_ASCMode_TFF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_TFF_Pos)                 /*!< USIC_CH PSR_ASCMode: TFF Mask           */\r
+#define USIC_CH_PSR_ASCMode_BUSY_Pos          9                                                       /*!< USIC_CH PSR_ASCMode: BUSY Position      */\r
+#define USIC_CH_PSR_ASCMode_BUSY_Msk          (0x01UL << USIC_CH_PSR_ASCMode_BUSY_Pos)                /*!< USIC_CH PSR_ASCMode: BUSY Mask          */\r
+#define USIC_CH_PSR_ASCMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_ASCMode: RSIF Position      */\r
+#define USIC_CH_PSR_ASCMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_RSIF_Pos)                /*!< USIC_CH PSR_ASCMode: RSIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_ASCMode: DLIF Position      */\r
+#define USIC_CH_PSR_ASCMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_DLIF_Pos)                /*!< USIC_CH PSR_ASCMode: DLIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_ASCMode: TSIF Position      */\r
+#define USIC_CH_PSR_ASCMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_TSIF_Pos)                /*!< USIC_CH PSR_ASCMode: TSIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_ASCMode: TBIF Position      */\r
+#define USIC_CH_PSR_ASCMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_TBIF_Pos)                /*!< USIC_CH PSR_ASCMode: TBIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_ASCMode: RIF Position       */\r
+#define USIC_CH_PSR_ASCMode_RIF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_RIF_Pos)                 /*!< USIC_CH PSR_ASCMode: RIF Mask           */\r
+#define USIC_CH_PSR_ASCMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_ASCMode: AIF Position       */\r
+#define USIC_CH_PSR_ASCMode_AIF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_AIF_Pos)                 /*!< USIC_CH PSR_ASCMode: AIF Mask           */\r
+#define USIC_CH_PSR_ASCMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_ASCMode: BRGIF Position     */\r
+#define USIC_CH_PSR_ASCMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_ASCMode_BRGIF_Pos)               /*!< USIC_CH PSR_ASCMode: BRGIF Mask         */\r
+\r
+/* -----------------------------  USIC_CH_PSR_SSCMode  ---------------------------- */\r
+#define USIC_CH_PSR_SSCMode_MSLS_Pos          0                                                       /*!< USIC_CH PSR_SSCMode: MSLS Position      */\r
+#define USIC_CH_PSR_SSCMode_MSLS_Msk          (0x01UL << USIC_CH_PSR_SSCMode_MSLS_Pos)                /*!< USIC_CH PSR_SSCMode: MSLS Mask          */\r
+#define USIC_CH_PSR_SSCMode_DX2S_Pos          1                                                       /*!< USIC_CH PSR_SSCMode: DX2S Position      */\r
+#define USIC_CH_PSR_SSCMode_DX2S_Msk          (0x01UL << USIC_CH_PSR_SSCMode_DX2S_Pos)                /*!< USIC_CH PSR_SSCMode: DX2S Mask          */\r
+#define USIC_CH_PSR_SSCMode_MSLSEV_Pos        2                                                       /*!< USIC_CH PSR_SSCMode: MSLSEV Position    */\r
+#define USIC_CH_PSR_SSCMode_MSLSEV_Msk        (0x01UL << USIC_CH_PSR_SSCMode_MSLSEV_Pos)              /*!< USIC_CH PSR_SSCMode: MSLSEV Mask        */\r
+#define USIC_CH_PSR_SSCMode_DX2TEV_Pos        3                                                       /*!< USIC_CH PSR_SSCMode: DX2TEV Position    */\r
+#define USIC_CH_PSR_SSCMode_DX2TEV_Msk        (0x01UL << USIC_CH_PSR_SSCMode_DX2TEV_Pos)              /*!< USIC_CH PSR_SSCMode: DX2TEV Mask        */\r
+#define USIC_CH_PSR_SSCMode_PARERR_Pos        4                                                       /*!< USIC_CH PSR_SSCMode: PARERR Position    */\r
+#define USIC_CH_PSR_SSCMode_PARERR_Msk        (0x01UL << USIC_CH_PSR_SSCMode_PARERR_Pos)              /*!< USIC_CH PSR_SSCMode: PARERR Mask        */\r
+#define USIC_CH_PSR_SSCMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_SSCMode: RSIF Position      */\r
+#define USIC_CH_PSR_SSCMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_RSIF_Pos)                /*!< USIC_CH PSR_SSCMode: RSIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_SSCMode: DLIF Position      */\r
+#define USIC_CH_PSR_SSCMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_DLIF_Pos)                /*!< USIC_CH PSR_SSCMode: DLIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_SSCMode: TSIF Position      */\r
+#define USIC_CH_PSR_SSCMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_TSIF_Pos)                /*!< USIC_CH PSR_SSCMode: TSIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_SSCMode: TBIF Position      */\r
+#define USIC_CH_PSR_SSCMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_TBIF_Pos)                /*!< USIC_CH PSR_SSCMode: TBIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_SSCMode: RIF Position       */\r
+#define USIC_CH_PSR_SSCMode_RIF_Msk           (0x01UL << USIC_CH_PSR_SSCMode_RIF_Pos)                 /*!< USIC_CH PSR_SSCMode: RIF Mask           */\r
+#define USIC_CH_PSR_SSCMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_SSCMode: AIF Position       */\r
+#define USIC_CH_PSR_SSCMode_AIF_Msk           (0x01UL << USIC_CH_PSR_SSCMode_AIF_Pos)                 /*!< USIC_CH PSR_SSCMode: AIF Mask           */\r
+#define USIC_CH_PSR_SSCMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_SSCMode: BRGIF Position     */\r
+#define USIC_CH_PSR_SSCMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_SSCMode_BRGIF_Pos)               /*!< USIC_CH PSR_SSCMode: BRGIF Mask         */\r
+\r
+/* -----------------------------  USIC_CH_PSR_IICMode  ---------------------------- */\r
+#define USIC_CH_PSR_IICMode_SLSEL_Pos         0                                                       /*!< USIC_CH PSR_IICMode: SLSEL Position     */\r
+#define USIC_CH_PSR_IICMode_SLSEL_Msk         (0x01UL << USIC_CH_PSR_IICMode_SLSEL_Pos)               /*!< USIC_CH PSR_IICMode: SLSEL Mask         */\r
+#define USIC_CH_PSR_IICMode_WTDF_Pos          1                                                       /*!< USIC_CH PSR_IICMode: WTDF Position      */\r
+#define USIC_CH_PSR_IICMode_WTDF_Msk          (0x01UL << USIC_CH_PSR_IICMode_WTDF_Pos)                /*!< USIC_CH PSR_IICMode: WTDF Mask          */\r
+#define USIC_CH_PSR_IICMode_SCR_Pos           2                                                       /*!< USIC_CH PSR_IICMode: SCR Position       */\r
+#define USIC_CH_PSR_IICMode_SCR_Msk           (0x01UL << USIC_CH_PSR_IICMode_SCR_Pos)                 /*!< USIC_CH PSR_IICMode: SCR Mask           */\r
+#define USIC_CH_PSR_IICMode_RSCR_Pos          3                                                       /*!< USIC_CH PSR_IICMode: RSCR Position      */\r
+#define USIC_CH_PSR_IICMode_RSCR_Msk          (0x01UL << USIC_CH_PSR_IICMode_RSCR_Pos)                /*!< USIC_CH PSR_IICMode: RSCR Mask          */\r
+#define USIC_CH_PSR_IICMode_PCR_Pos           4                                                       /*!< USIC_CH PSR_IICMode: PCR Position       */\r
+#define USIC_CH_PSR_IICMode_PCR_Msk           (0x01UL << USIC_CH_PSR_IICMode_PCR_Pos)                 /*!< USIC_CH PSR_IICMode: PCR Mask           */\r
+#define USIC_CH_PSR_IICMode_NACK_Pos          5                                                       /*!< USIC_CH PSR_IICMode: NACK Position      */\r
+#define USIC_CH_PSR_IICMode_NACK_Msk          (0x01UL << USIC_CH_PSR_IICMode_NACK_Pos)                /*!< USIC_CH PSR_IICMode: NACK Mask          */\r
+#define USIC_CH_PSR_IICMode_ARL_Pos           6                                                       /*!< USIC_CH PSR_IICMode: ARL Position       */\r
+#define USIC_CH_PSR_IICMode_ARL_Msk           (0x01UL << USIC_CH_PSR_IICMode_ARL_Pos)                 /*!< USIC_CH PSR_IICMode: ARL Mask           */\r
+#define USIC_CH_PSR_IICMode_SRR_Pos           7                                                       /*!< USIC_CH PSR_IICMode: SRR Position       */\r
+#define USIC_CH_PSR_IICMode_SRR_Msk           (0x01UL << USIC_CH_PSR_IICMode_SRR_Pos)                 /*!< USIC_CH PSR_IICMode: SRR Mask           */\r
+#define USIC_CH_PSR_IICMode_ERR_Pos           8                                                       /*!< USIC_CH PSR_IICMode: ERR Position       */\r
+#define USIC_CH_PSR_IICMode_ERR_Msk           (0x01UL << USIC_CH_PSR_IICMode_ERR_Pos)                 /*!< USIC_CH PSR_IICMode: ERR Mask           */\r
+#define USIC_CH_PSR_IICMode_ACK_Pos           9                                                       /*!< USIC_CH PSR_IICMode: ACK Position       */\r
+#define USIC_CH_PSR_IICMode_ACK_Msk           (0x01UL << USIC_CH_PSR_IICMode_ACK_Pos)                 /*!< USIC_CH PSR_IICMode: ACK Mask           */\r
+#define USIC_CH_PSR_IICMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_IICMode: RSIF Position      */\r
+#define USIC_CH_PSR_IICMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_RSIF_Pos)                /*!< USIC_CH PSR_IICMode: RSIF Mask          */\r
+#define USIC_CH_PSR_IICMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_IICMode: DLIF Position      */\r
+#define USIC_CH_PSR_IICMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_DLIF_Pos)                /*!< USIC_CH PSR_IICMode: DLIF Mask          */\r
+#define USIC_CH_PSR_IICMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_IICMode: TSIF Position      */\r
+#define USIC_CH_PSR_IICMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_TSIF_Pos)                /*!< USIC_CH PSR_IICMode: TSIF Mask          */\r
+#define USIC_CH_PSR_IICMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_IICMode: TBIF Position      */\r
+#define USIC_CH_PSR_IICMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_TBIF_Pos)                /*!< USIC_CH PSR_IICMode: TBIF Mask          */\r
+#define USIC_CH_PSR_IICMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_IICMode: RIF Position       */\r
+#define USIC_CH_PSR_IICMode_RIF_Msk           (0x01UL << USIC_CH_PSR_IICMode_RIF_Pos)                 /*!< USIC_CH PSR_IICMode: RIF Mask           */\r
+#define USIC_CH_PSR_IICMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_IICMode: AIF Position       */\r
+#define USIC_CH_PSR_IICMode_AIF_Msk           (0x01UL << USIC_CH_PSR_IICMode_AIF_Pos)                 /*!< USIC_CH PSR_IICMode: AIF Mask           */\r
+#define USIC_CH_PSR_IICMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_IICMode: BRGIF Position     */\r
+#define USIC_CH_PSR_IICMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_IICMode_BRGIF_Pos)               /*!< USIC_CH PSR_IICMode: BRGIF Mask         */\r
+\r
+/* -----------------------------  USIC_CH_PSR_IISMode  ---------------------------- */\r
+#define USIC_CH_PSR_IISMode_WA_Pos            0                                                       /*!< USIC_CH PSR_IISMode: WA Position        */\r
+#define USIC_CH_PSR_IISMode_WA_Msk            (0x01UL << USIC_CH_PSR_IISMode_WA_Pos)                  /*!< USIC_CH PSR_IISMode: WA Mask            */\r
+#define USIC_CH_PSR_IISMode_DX2S_Pos          1                                                       /*!< USIC_CH PSR_IISMode: DX2S Position      */\r
+#define USIC_CH_PSR_IISMode_DX2S_Msk          (0x01UL << USIC_CH_PSR_IISMode_DX2S_Pos)                /*!< USIC_CH PSR_IISMode: DX2S Mask          */\r
+#define USIC_CH_PSR_IISMode_DX2TEV_Pos        3                                                       /*!< USIC_CH PSR_IISMode: DX2TEV Position    */\r
+#define USIC_CH_PSR_IISMode_DX2TEV_Msk        (0x01UL << USIC_CH_PSR_IISMode_DX2TEV_Pos)              /*!< USIC_CH PSR_IISMode: DX2TEV Mask        */\r
+#define USIC_CH_PSR_IISMode_WAFE_Pos          4                                                       /*!< USIC_CH PSR_IISMode: WAFE Position      */\r
+#define USIC_CH_PSR_IISMode_WAFE_Msk          (0x01UL << USIC_CH_PSR_IISMode_WAFE_Pos)                /*!< USIC_CH PSR_IISMode: WAFE Mask          */\r
+#define USIC_CH_PSR_IISMode_WARE_Pos          5                                                       /*!< USIC_CH PSR_IISMode: WARE Position      */\r
+#define USIC_CH_PSR_IISMode_WARE_Msk          (0x01UL << USIC_CH_PSR_IISMode_WARE_Pos)                /*!< USIC_CH PSR_IISMode: WARE Mask          */\r
+#define USIC_CH_PSR_IISMode_END_Pos           6                                                       /*!< USIC_CH PSR_IISMode: END Position       */\r
+#define USIC_CH_PSR_IISMode_END_Msk           (0x01UL << USIC_CH_PSR_IISMode_END_Pos)                 /*!< USIC_CH PSR_IISMode: END Mask           */\r
+#define USIC_CH_PSR_IISMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_IISMode: RSIF Position      */\r
+#define USIC_CH_PSR_IISMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_RSIF_Pos)                /*!< USIC_CH PSR_IISMode: RSIF Mask          */\r
+#define USIC_CH_PSR_IISMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_IISMode: DLIF Position      */\r
+#define USIC_CH_PSR_IISMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_DLIF_Pos)                /*!< USIC_CH PSR_IISMode: DLIF Mask          */\r
+#define USIC_CH_PSR_IISMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_IISMode: TSIF Position      */\r
+#define USIC_CH_PSR_IISMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_TSIF_Pos)                /*!< USIC_CH PSR_IISMode: TSIF Mask          */\r
+#define USIC_CH_PSR_IISMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_IISMode: TBIF Position      */\r
+#define USIC_CH_PSR_IISMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_TBIF_Pos)                /*!< USIC_CH PSR_IISMode: TBIF Mask          */\r
+#define USIC_CH_PSR_IISMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_IISMode: RIF Position       */\r
+#define USIC_CH_PSR_IISMode_RIF_Msk           (0x01UL << USIC_CH_PSR_IISMode_RIF_Pos)                 /*!< USIC_CH PSR_IISMode: RIF Mask           */\r
+#define USIC_CH_PSR_IISMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_IISMode: AIF Position       */\r
+#define USIC_CH_PSR_IISMode_AIF_Msk           (0x01UL << USIC_CH_PSR_IISMode_AIF_Pos)                 /*!< USIC_CH PSR_IISMode: AIF Mask           */\r
+#define USIC_CH_PSR_IISMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_IISMode: BRGIF Position     */\r
+#define USIC_CH_PSR_IISMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_IISMode_BRGIF_Pos)               /*!< USIC_CH PSR_IISMode: BRGIF Mask         */\r
+\r
+/* --------------------------------  USIC_CH_PSCR  -------------------------------- */\r
+#define USIC_CH_PSCR_CST0_Pos                 0                                                       /*!< USIC_CH PSCR: CST0 Position             */\r
+#define USIC_CH_PSCR_CST0_Msk                 (0x01UL << USIC_CH_PSCR_CST0_Pos)                       /*!< USIC_CH PSCR: CST0 Mask                 */\r
+#define USIC_CH_PSCR_CST1_Pos                 1                                                       /*!< USIC_CH PSCR: CST1 Position             */\r
+#define USIC_CH_PSCR_CST1_Msk                 (0x01UL << USIC_CH_PSCR_CST1_Pos)                       /*!< USIC_CH PSCR: CST1 Mask                 */\r
+#define USIC_CH_PSCR_CST2_Pos                 2                                                       /*!< USIC_CH PSCR: CST2 Position             */\r
+#define USIC_CH_PSCR_CST2_Msk                 (0x01UL << USIC_CH_PSCR_CST2_Pos)                       /*!< USIC_CH PSCR: CST2 Mask                 */\r
+#define USIC_CH_PSCR_CST3_Pos                 3                                                       /*!< USIC_CH PSCR: CST3 Position             */\r
+#define USIC_CH_PSCR_CST3_Msk                 (0x01UL << USIC_CH_PSCR_CST3_Pos)                       /*!< USIC_CH PSCR: CST3 Mask                 */\r
+#define USIC_CH_PSCR_CST4_Pos                 4                                                       /*!< USIC_CH PSCR: CST4 Position             */\r
+#define USIC_CH_PSCR_CST4_Msk                 (0x01UL << USIC_CH_PSCR_CST4_Pos)                       /*!< USIC_CH PSCR: CST4 Mask                 */\r
+#define USIC_CH_PSCR_CST5_Pos                 5                                                       /*!< USIC_CH PSCR: CST5 Position             */\r
+#define USIC_CH_PSCR_CST5_Msk                 (0x01UL << USIC_CH_PSCR_CST5_Pos)                       /*!< USIC_CH PSCR: CST5 Mask                 */\r
+#define USIC_CH_PSCR_CST6_Pos                 6                                                       /*!< USIC_CH PSCR: CST6 Position             */\r
+#define USIC_CH_PSCR_CST6_Msk                 (0x01UL << USIC_CH_PSCR_CST6_Pos)                       /*!< USIC_CH PSCR: CST6 Mask                 */\r
+#define USIC_CH_PSCR_CST7_Pos                 7                                                       /*!< USIC_CH PSCR: CST7 Position             */\r
+#define USIC_CH_PSCR_CST7_Msk                 (0x01UL << USIC_CH_PSCR_CST7_Pos)                       /*!< USIC_CH PSCR: CST7 Mask                 */\r
+#define USIC_CH_PSCR_CST8_Pos                 8                                                       /*!< USIC_CH PSCR: CST8 Position             */\r
+#define USIC_CH_PSCR_CST8_Msk                 (0x01UL << USIC_CH_PSCR_CST8_Pos)                       /*!< USIC_CH PSCR: CST8 Mask                 */\r
+#define USIC_CH_PSCR_CST9_Pos                 9                                                       /*!< USIC_CH PSCR: CST9 Position             */\r
+#define USIC_CH_PSCR_CST9_Msk                 (0x01UL << USIC_CH_PSCR_CST9_Pos)                       /*!< USIC_CH PSCR: CST9 Mask                 */\r
+#define USIC_CH_PSCR_CRSIF_Pos                10                                                      /*!< USIC_CH PSCR: CRSIF Position            */\r
+#define USIC_CH_PSCR_CRSIF_Msk                (0x01UL << USIC_CH_PSCR_CRSIF_Pos)                      /*!< USIC_CH PSCR: CRSIF Mask                */\r
+#define USIC_CH_PSCR_CDLIF_Pos                11                                                      /*!< USIC_CH PSCR: CDLIF Position            */\r
+#define USIC_CH_PSCR_CDLIF_Msk                (0x01UL << USIC_CH_PSCR_CDLIF_Pos)                      /*!< USIC_CH PSCR: CDLIF Mask                */\r
+#define USIC_CH_PSCR_CTSIF_Pos                12                                                      /*!< USIC_CH PSCR: CTSIF Position            */\r
+#define USIC_CH_PSCR_CTSIF_Msk                (0x01UL << USIC_CH_PSCR_CTSIF_Pos)                      /*!< USIC_CH PSCR: CTSIF Mask                */\r
+#define USIC_CH_PSCR_CTBIF_Pos                13                                                      /*!< USIC_CH PSCR: CTBIF Position            */\r
+#define USIC_CH_PSCR_CTBIF_Msk                (0x01UL << USIC_CH_PSCR_CTBIF_Pos)                      /*!< USIC_CH PSCR: CTBIF Mask                */\r
+#define USIC_CH_PSCR_CRIF_Pos                 14                                                      /*!< USIC_CH PSCR: CRIF Position             */\r
+#define USIC_CH_PSCR_CRIF_Msk                 (0x01UL << USIC_CH_PSCR_CRIF_Pos)                       /*!< USIC_CH PSCR: CRIF Mask                 */\r
+#define USIC_CH_PSCR_CAIF_Pos                 15                                                      /*!< USIC_CH PSCR: CAIF Position             */\r
+#define USIC_CH_PSCR_CAIF_Msk                 (0x01UL << USIC_CH_PSCR_CAIF_Pos)                       /*!< USIC_CH PSCR: CAIF Mask                 */\r
+#define USIC_CH_PSCR_CBRGIF_Pos               16                                                      /*!< USIC_CH PSCR: CBRGIF Position           */\r
+#define USIC_CH_PSCR_CBRGIF_Msk               (0x01UL << USIC_CH_PSCR_CBRGIF_Pos)                     /*!< USIC_CH PSCR: CBRGIF Mask               */\r
+\r
+/* -------------------------------  USIC_CH_RBUFSR  ------------------------------- */\r
+#define USIC_CH_RBUFSR_WLEN_Pos               0                                                       /*!< USIC_CH RBUFSR: WLEN Position           */\r
+#define USIC_CH_RBUFSR_WLEN_Msk               (0x0fUL << USIC_CH_RBUFSR_WLEN_Pos)                     /*!< USIC_CH RBUFSR: WLEN Mask               */\r
+#define USIC_CH_RBUFSR_SOF_Pos                6                                                       /*!< USIC_CH RBUFSR: SOF Position            */\r
+#define USIC_CH_RBUFSR_SOF_Msk                (0x01UL << USIC_CH_RBUFSR_SOF_Pos)                      /*!< USIC_CH RBUFSR: SOF Mask                */\r
+#define USIC_CH_RBUFSR_PAR_Pos                8                                                       /*!< USIC_CH RBUFSR: PAR Position            */\r
+#define USIC_CH_RBUFSR_PAR_Msk                (0x01UL << USIC_CH_RBUFSR_PAR_Pos)                      /*!< USIC_CH RBUFSR: PAR Mask                */\r
+#define USIC_CH_RBUFSR_PERR_Pos               9                                                       /*!< USIC_CH RBUFSR: PERR Position           */\r
+#define USIC_CH_RBUFSR_PERR_Msk               (0x01UL << USIC_CH_RBUFSR_PERR_Pos)                     /*!< USIC_CH RBUFSR: PERR Mask               */\r
+#define USIC_CH_RBUFSR_RDV0_Pos               13                                                      /*!< USIC_CH RBUFSR: RDV0 Position           */\r
+#define USIC_CH_RBUFSR_RDV0_Msk               (0x01UL << USIC_CH_RBUFSR_RDV0_Pos)                     /*!< USIC_CH RBUFSR: RDV0 Mask               */\r
+#define USIC_CH_RBUFSR_RDV1_Pos               14                                                      /*!< USIC_CH RBUFSR: RDV1 Position           */\r
+#define USIC_CH_RBUFSR_RDV1_Msk               (0x01UL << USIC_CH_RBUFSR_RDV1_Pos)                     /*!< USIC_CH RBUFSR: RDV1 Mask               */\r
+#define USIC_CH_RBUFSR_DS_Pos                 15                                                      /*!< USIC_CH RBUFSR: DS Position             */\r
+#define USIC_CH_RBUFSR_DS_Msk                 (0x01UL << USIC_CH_RBUFSR_DS_Pos)                       /*!< USIC_CH RBUFSR: DS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_RBUF  -------------------------------- */\r
+#define USIC_CH_RBUF_DSR_Pos                  0                                                       /*!< USIC_CH RBUF: DSR Position              */\r
+#define USIC_CH_RBUF_DSR_Msk                  (0x0000ffffUL << USIC_CH_RBUF_DSR_Pos)                  /*!< USIC_CH RBUF: DSR Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_RBUFD  ------------------------------- */\r
+#define USIC_CH_RBUFD_DSR_Pos                 0                                                       /*!< USIC_CH RBUFD: DSR Position             */\r
+#define USIC_CH_RBUFD_DSR_Msk                 (0x0000ffffUL << USIC_CH_RBUFD_DSR_Pos)                 /*!< USIC_CH RBUFD: DSR Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_RBUF0  ------------------------------- */\r
+#define USIC_CH_RBUF0_DSR0_Pos                0                                                       /*!< USIC_CH RBUF0: DSR0 Position            */\r
+#define USIC_CH_RBUF0_DSR0_Msk                (0x0000ffffUL << USIC_CH_RBUF0_DSR0_Pos)                /*!< USIC_CH RBUF0: DSR0 Mask                */\r
+\r
+/* --------------------------------  USIC_CH_RBUF1  ------------------------------- */\r
+#define USIC_CH_RBUF1_DSR1_Pos                0                                                       /*!< USIC_CH RBUF1: DSR1 Position            */\r
+#define USIC_CH_RBUF1_DSR1_Msk                (0x0000ffffUL << USIC_CH_RBUF1_DSR1_Pos)                /*!< USIC_CH RBUF1: DSR1 Mask                */\r
+\r
+/* ------------------------------  USIC_CH_RBUF01SR  ------------------------------ */\r
+#define USIC_CH_RBUF01SR_WLEN0_Pos            0                                                       /*!< USIC_CH RBUF01SR: WLEN0 Position        */\r
+#define USIC_CH_RBUF01SR_WLEN0_Msk            (0x0fUL << USIC_CH_RBUF01SR_WLEN0_Pos)                  /*!< USIC_CH RBUF01SR: WLEN0 Mask            */\r
+#define USIC_CH_RBUF01SR_SOF0_Pos             6                                                       /*!< USIC_CH RBUF01SR: SOF0 Position         */\r
+#define USIC_CH_RBUF01SR_SOF0_Msk             (0x01UL << USIC_CH_RBUF01SR_SOF0_Pos)                   /*!< USIC_CH RBUF01SR: SOF0 Mask             */\r
+#define USIC_CH_RBUF01SR_PAR0_Pos             8                                                       /*!< USIC_CH RBUF01SR: PAR0 Position         */\r
+#define USIC_CH_RBUF01SR_PAR0_Msk             (0x01UL << USIC_CH_RBUF01SR_PAR0_Pos)                   /*!< USIC_CH RBUF01SR: PAR0 Mask             */\r
+#define USIC_CH_RBUF01SR_PERR0_Pos            9                                                       /*!< USIC_CH RBUF01SR: PERR0 Position        */\r
+#define USIC_CH_RBUF01SR_PERR0_Msk            (0x01UL << USIC_CH_RBUF01SR_PERR0_Pos)                  /*!< USIC_CH RBUF01SR: PERR0 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV00_Pos            13                                                      /*!< USIC_CH RBUF01SR: RDV00 Position        */\r
+#define USIC_CH_RBUF01SR_RDV00_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV00_Pos)                  /*!< USIC_CH RBUF01SR: RDV00 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV01_Pos            14                                                      /*!< USIC_CH RBUF01SR: RDV01 Position        */\r
+#define USIC_CH_RBUF01SR_RDV01_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV01_Pos)                  /*!< USIC_CH RBUF01SR: RDV01 Mask            */\r
+#define USIC_CH_RBUF01SR_DS0_Pos              15                                                      /*!< USIC_CH RBUF01SR: DS0 Position          */\r
+#define USIC_CH_RBUF01SR_DS0_Msk              (0x01UL << USIC_CH_RBUF01SR_DS0_Pos)                    /*!< USIC_CH RBUF01SR: DS0 Mask              */\r
+#define USIC_CH_RBUF01SR_WLEN1_Pos            16                                                      /*!< USIC_CH RBUF01SR: WLEN1 Position        */\r
+#define USIC_CH_RBUF01SR_WLEN1_Msk            (0x0fUL << USIC_CH_RBUF01SR_WLEN1_Pos)                  /*!< USIC_CH RBUF01SR: WLEN1 Mask            */\r
+#define USIC_CH_RBUF01SR_SOF1_Pos             22                                                      /*!< USIC_CH RBUF01SR: SOF1 Position         */\r
+#define USIC_CH_RBUF01SR_SOF1_Msk             (0x01UL << USIC_CH_RBUF01SR_SOF1_Pos)                   /*!< USIC_CH RBUF01SR: SOF1 Mask             */\r
+#define USIC_CH_RBUF01SR_PAR1_Pos             24                                                      /*!< USIC_CH RBUF01SR: PAR1 Position         */\r
+#define USIC_CH_RBUF01SR_PAR1_Msk             (0x01UL << USIC_CH_RBUF01SR_PAR1_Pos)                   /*!< USIC_CH RBUF01SR: PAR1 Mask             */\r
+#define USIC_CH_RBUF01SR_PERR1_Pos            25                                                      /*!< USIC_CH RBUF01SR: PERR1 Position        */\r
+#define USIC_CH_RBUF01SR_PERR1_Msk            (0x01UL << USIC_CH_RBUF01SR_PERR1_Pos)                  /*!< USIC_CH RBUF01SR: PERR1 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV10_Pos            29                                                      /*!< USIC_CH RBUF01SR: RDV10 Position        */\r
+#define USIC_CH_RBUF01SR_RDV10_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV10_Pos)                  /*!< USIC_CH RBUF01SR: RDV10 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV11_Pos            30                                                      /*!< USIC_CH RBUF01SR: RDV11 Position        */\r
+#define USIC_CH_RBUF01SR_RDV11_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV11_Pos)                  /*!< USIC_CH RBUF01SR: RDV11 Mask            */\r
+#define USIC_CH_RBUF01SR_DS1_Pos              31                                                      /*!< USIC_CH RBUF01SR: DS1 Position          */\r
+#define USIC_CH_RBUF01SR_DS1_Msk              (0x01UL << USIC_CH_RBUF01SR_DS1_Pos)                    /*!< USIC_CH RBUF01SR: DS1 Mask              */\r
+\r
+/* ---------------------------------  USIC_CH_FMR  -------------------------------- */\r
+#define USIC_CH_FMR_MTDV_Pos                  0                                                       /*!< USIC_CH FMR: MTDV Position              */\r
+#define USIC_CH_FMR_MTDV_Msk                  (0x03UL << USIC_CH_FMR_MTDV_Pos)                        /*!< USIC_CH FMR: MTDV Mask                  */\r
+#define USIC_CH_FMR_ATVC_Pos                  4                                                       /*!< USIC_CH FMR: ATVC Position              */\r
+#define USIC_CH_FMR_ATVC_Msk                  (0x01UL << USIC_CH_FMR_ATVC_Pos)                        /*!< USIC_CH FMR: ATVC Mask                  */\r
+#define USIC_CH_FMR_CRDV0_Pos                 14                                                      /*!< USIC_CH FMR: CRDV0 Position             */\r
+#define USIC_CH_FMR_CRDV0_Msk                 (0x01UL << USIC_CH_FMR_CRDV0_Pos)                       /*!< USIC_CH FMR: CRDV0 Mask                 */\r
+#define USIC_CH_FMR_CRDV1_Pos                 15                                                      /*!< USIC_CH FMR: CRDV1 Position             */\r
+#define USIC_CH_FMR_CRDV1_Msk                 (0x01UL << USIC_CH_FMR_CRDV1_Pos)                       /*!< USIC_CH FMR: CRDV1 Mask                 */\r
+#define USIC_CH_FMR_SIO0_Pos                  16                                                      /*!< USIC_CH FMR: SIO0 Position              */\r
+#define USIC_CH_FMR_SIO0_Msk                  (0x01UL << USIC_CH_FMR_SIO0_Pos)                        /*!< USIC_CH FMR: SIO0 Mask                  */\r
+#define USIC_CH_FMR_SIO1_Pos                  17                                                      /*!< USIC_CH FMR: SIO1 Position              */\r
+#define USIC_CH_FMR_SIO1_Msk                  (0x01UL << USIC_CH_FMR_SIO1_Pos)                        /*!< USIC_CH FMR: SIO1 Mask                  */\r
+#define USIC_CH_FMR_SIO2_Pos                  18                                                      /*!< USIC_CH FMR: SIO2 Position              */\r
+#define USIC_CH_FMR_SIO2_Msk                  (0x01UL << USIC_CH_FMR_SIO2_Pos)                        /*!< USIC_CH FMR: SIO2 Mask                  */\r
+#define USIC_CH_FMR_SIO3_Pos                  19                                                      /*!< USIC_CH FMR: SIO3 Position              */\r
+#define USIC_CH_FMR_SIO3_Msk                  (0x01UL << USIC_CH_FMR_SIO3_Pos)                        /*!< USIC_CH FMR: SIO3 Mask                  */\r
+#define USIC_CH_FMR_SIO4_Pos                  20                                                      /*!< USIC_CH FMR: SIO4 Position              */\r
+#define USIC_CH_FMR_SIO4_Msk                  (0x01UL << USIC_CH_FMR_SIO4_Pos)                        /*!< USIC_CH FMR: SIO4 Mask                  */\r
+#define USIC_CH_FMR_SIO5_Pos                  21                                                      /*!< USIC_CH FMR: SIO5 Position              */\r
+#define USIC_CH_FMR_SIO5_Msk                  (0x01UL << USIC_CH_FMR_SIO5_Pos)                        /*!< USIC_CH FMR: SIO5 Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_TBUF  -------------------------------- */\r
+#define USIC_CH_TBUF_TDATA_Pos                0                                                       /*!< USIC_CH TBUF: TDATA Position            */\r
+#define USIC_CH_TBUF_TDATA_Msk                (0x0000ffffUL << USIC_CH_TBUF_TDATA_Pos)                /*!< USIC_CH TBUF: TDATA Mask                */\r
+\r
+/* ---------------------------------  USIC_CH_BYP  -------------------------------- */\r
+#define USIC_CH_BYP_BDATA_Pos                 0                                                       /*!< USIC_CH BYP: BDATA Position             */\r
+#define USIC_CH_BYP_BDATA_Msk                 (0x0000ffffUL << USIC_CH_BYP_BDATA_Pos)                 /*!< USIC_CH BYP: BDATA Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_BYPCR  ------------------------------- */\r
+#define USIC_CH_BYPCR_BWLE_Pos                0                                                       /*!< USIC_CH BYPCR: BWLE Position            */\r
+#define USIC_CH_BYPCR_BWLE_Msk                (0x0fUL << USIC_CH_BYPCR_BWLE_Pos)                      /*!< USIC_CH BYPCR: BWLE Mask                */\r
+#define USIC_CH_BYPCR_BDSSM_Pos               8                                                       /*!< USIC_CH BYPCR: BDSSM Position           */\r
+#define USIC_CH_BYPCR_BDSSM_Msk               (0x01UL << USIC_CH_BYPCR_BDSSM_Pos)                     /*!< USIC_CH BYPCR: BDSSM Mask               */\r
+#define USIC_CH_BYPCR_BDEN_Pos                10                                                      /*!< USIC_CH BYPCR: BDEN Position            */\r
+#define USIC_CH_BYPCR_BDEN_Msk                (0x03UL << USIC_CH_BYPCR_BDEN_Pos)                      /*!< USIC_CH BYPCR: BDEN Mask                */\r
+#define USIC_CH_BYPCR_BDVTR_Pos               12                                                      /*!< USIC_CH BYPCR: BDVTR Position           */\r
+#define USIC_CH_BYPCR_BDVTR_Msk               (0x01UL << USIC_CH_BYPCR_BDVTR_Pos)                     /*!< USIC_CH BYPCR: BDVTR Mask               */\r
+#define USIC_CH_BYPCR_BPRIO_Pos               13                                                      /*!< USIC_CH BYPCR: BPRIO Position           */\r
+#define USIC_CH_BYPCR_BPRIO_Msk               (0x01UL << USIC_CH_BYPCR_BPRIO_Pos)                     /*!< USIC_CH BYPCR: BPRIO Mask               */\r
+#define USIC_CH_BYPCR_BDV_Pos                 15                                                      /*!< USIC_CH BYPCR: BDV Position             */\r
+#define USIC_CH_BYPCR_BDV_Msk                 (0x01UL << USIC_CH_BYPCR_BDV_Pos)                       /*!< USIC_CH BYPCR: BDV Mask                 */\r
+#define USIC_CH_BYPCR_BSELO_Pos               16                                                      /*!< USIC_CH BYPCR: BSELO Position           */\r
+#define USIC_CH_BYPCR_BSELO_Msk               (0x1fUL << USIC_CH_BYPCR_BSELO_Pos)                     /*!< USIC_CH BYPCR: BSELO Mask               */\r
+#define USIC_CH_BYPCR_BHPC_Pos                21                                                      /*!< USIC_CH BYPCR: BHPC Position            */\r
+#define USIC_CH_BYPCR_BHPC_Msk                (0x07UL << USIC_CH_BYPCR_BHPC_Pos)                      /*!< USIC_CH BYPCR: BHPC Mask                */\r
+\r
+/* --------------------------------  USIC_CH_TBCTR  ------------------------------- */\r
+#define USIC_CH_TBCTR_DPTR_Pos                0                                                       /*!< USIC_CH TBCTR: DPTR Position            */\r
+#define USIC_CH_TBCTR_DPTR_Msk                (0x3fUL << USIC_CH_TBCTR_DPTR_Pos)                      /*!< USIC_CH TBCTR: DPTR Mask                */\r
+#define USIC_CH_TBCTR_LIMIT_Pos               8                                                       /*!< USIC_CH TBCTR: LIMIT Position           */\r
+#define USIC_CH_TBCTR_LIMIT_Msk               (0x3fUL << USIC_CH_TBCTR_LIMIT_Pos)                     /*!< USIC_CH TBCTR: LIMIT Mask               */\r
+#define USIC_CH_TBCTR_STBTM_Pos               14                                                      /*!< USIC_CH TBCTR: STBTM Position           */\r
+#define USIC_CH_TBCTR_STBTM_Msk               (0x01UL << USIC_CH_TBCTR_STBTM_Pos)                     /*!< USIC_CH TBCTR: STBTM Mask               */\r
+#define USIC_CH_TBCTR_STBTEN_Pos              15                                                      /*!< USIC_CH TBCTR: STBTEN Position          */\r
+#define USIC_CH_TBCTR_STBTEN_Msk              (0x01UL << USIC_CH_TBCTR_STBTEN_Pos)                    /*!< USIC_CH TBCTR: STBTEN Mask              */\r
+#define USIC_CH_TBCTR_STBINP_Pos              16                                                      /*!< USIC_CH TBCTR: STBINP Position          */\r
+#define USIC_CH_TBCTR_STBINP_Msk              (0x07UL << USIC_CH_TBCTR_STBINP_Pos)                    /*!< USIC_CH TBCTR: STBINP Mask              */\r
+#define USIC_CH_TBCTR_ATBINP_Pos              19                                                      /*!< USIC_CH TBCTR: ATBINP Position          */\r
+#define USIC_CH_TBCTR_ATBINP_Msk              (0x07UL << USIC_CH_TBCTR_ATBINP_Pos)                    /*!< USIC_CH TBCTR: ATBINP Mask              */\r
+#define USIC_CH_TBCTR_SIZE_Pos                24                                                      /*!< USIC_CH TBCTR: SIZE Position            */\r
+#define USIC_CH_TBCTR_SIZE_Msk                (0x07UL << USIC_CH_TBCTR_SIZE_Pos)                      /*!< USIC_CH TBCTR: SIZE Mask                */\r
+#define USIC_CH_TBCTR_LOF_Pos                 28                                                      /*!< USIC_CH TBCTR: LOF Position             */\r
+#define USIC_CH_TBCTR_LOF_Msk                 (0x01UL << USIC_CH_TBCTR_LOF_Pos)                       /*!< USIC_CH TBCTR: LOF Mask                 */\r
+#define USIC_CH_TBCTR_STBIEN_Pos              30                                                      /*!< USIC_CH TBCTR: STBIEN Position          */\r
+#define USIC_CH_TBCTR_STBIEN_Msk              (0x01UL << USIC_CH_TBCTR_STBIEN_Pos)                    /*!< USIC_CH TBCTR: STBIEN Mask              */\r
+#define USIC_CH_TBCTR_TBERIEN_Pos             31                                                      /*!< USIC_CH TBCTR: TBERIEN Position         */\r
+#define USIC_CH_TBCTR_TBERIEN_Msk             (0x01UL << USIC_CH_TBCTR_TBERIEN_Pos)                   /*!< USIC_CH TBCTR: TBERIEN Mask             */\r
+\r
+/* --------------------------------  USIC_CH_RBCTR  ------------------------------- */\r
+#define USIC_CH_RBCTR_DPTR_Pos                0                                                       /*!< USIC_CH RBCTR: DPTR Position            */\r
+#define USIC_CH_RBCTR_DPTR_Msk                (0x3fUL << USIC_CH_RBCTR_DPTR_Pos)                      /*!< USIC_CH RBCTR: DPTR Mask                */\r
+#define USIC_CH_RBCTR_LIMIT_Pos               8                                                       /*!< USIC_CH RBCTR: LIMIT Position           */\r
+#define USIC_CH_RBCTR_LIMIT_Msk               (0x3fUL << USIC_CH_RBCTR_LIMIT_Pos)                     /*!< USIC_CH RBCTR: LIMIT Mask               */\r
+#define USIC_CH_RBCTR_SRBTM_Pos               14                                                      /*!< USIC_CH RBCTR: SRBTM Position           */\r
+#define USIC_CH_RBCTR_SRBTM_Msk               (0x01UL << USIC_CH_RBCTR_SRBTM_Pos)                     /*!< USIC_CH RBCTR: SRBTM Mask               */\r
+#define USIC_CH_RBCTR_SRBTEN_Pos              15                                                      /*!< USIC_CH RBCTR: SRBTEN Position          */\r
+#define USIC_CH_RBCTR_SRBTEN_Msk              (0x01UL << USIC_CH_RBCTR_SRBTEN_Pos)                    /*!< USIC_CH RBCTR: SRBTEN Mask              */\r
+#define USIC_CH_RBCTR_SRBINP_Pos              16                                                      /*!< USIC_CH RBCTR: SRBINP Position          */\r
+#define USIC_CH_RBCTR_SRBINP_Msk              (0x07UL << USIC_CH_RBCTR_SRBINP_Pos)                    /*!< USIC_CH RBCTR: SRBINP Mask              */\r
+#define USIC_CH_RBCTR_ARBINP_Pos              19                                                      /*!< USIC_CH RBCTR: ARBINP Position          */\r
+#define USIC_CH_RBCTR_ARBINP_Msk              (0x07UL << USIC_CH_RBCTR_ARBINP_Pos)                    /*!< USIC_CH RBCTR: ARBINP Mask              */\r
+#define USIC_CH_RBCTR_RCIM_Pos                22                                                      /*!< USIC_CH RBCTR: RCIM Position            */\r
+#define USIC_CH_RBCTR_RCIM_Msk                (0x03UL << USIC_CH_RBCTR_RCIM_Pos)                      /*!< USIC_CH RBCTR: RCIM Mask                */\r
+#define USIC_CH_RBCTR_SIZE_Pos                24                                                      /*!< USIC_CH RBCTR: SIZE Position            */\r
+#define USIC_CH_RBCTR_SIZE_Msk                (0x07UL << USIC_CH_RBCTR_SIZE_Pos)                      /*!< USIC_CH RBCTR: SIZE Mask                */\r
+#define USIC_CH_RBCTR_RNM_Pos                 27                                                      /*!< USIC_CH RBCTR: RNM Position             */\r
+#define USIC_CH_RBCTR_RNM_Msk                 (0x01UL << USIC_CH_RBCTR_RNM_Pos)                       /*!< USIC_CH RBCTR: RNM Mask                 */\r
+#define USIC_CH_RBCTR_LOF_Pos                 28                                                      /*!< USIC_CH RBCTR: LOF Position             */\r
+#define USIC_CH_RBCTR_LOF_Msk                 (0x01UL << USIC_CH_RBCTR_LOF_Pos)                       /*!< USIC_CH RBCTR: LOF Mask                 */\r
+#define USIC_CH_RBCTR_ARBIEN_Pos              29                                                      /*!< USIC_CH RBCTR: ARBIEN Position          */\r
+#define USIC_CH_RBCTR_ARBIEN_Msk              (0x01UL << USIC_CH_RBCTR_ARBIEN_Pos)                    /*!< USIC_CH RBCTR: ARBIEN Mask              */\r
+#define USIC_CH_RBCTR_SRBIEN_Pos              30                                                      /*!< USIC_CH RBCTR: SRBIEN Position          */\r
+#define USIC_CH_RBCTR_SRBIEN_Msk              (0x01UL << USIC_CH_RBCTR_SRBIEN_Pos)                    /*!< USIC_CH RBCTR: SRBIEN Mask              */\r
+#define USIC_CH_RBCTR_RBERIEN_Pos             31                                                      /*!< USIC_CH RBCTR: RBERIEN Position         */\r
+#define USIC_CH_RBCTR_RBERIEN_Msk             (0x01UL << USIC_CH_RBCTR_RBERIEN_Pos)                   /*!< USIC_CH RBCTR: RBERIEN Mask             */\r
+\r
+/* -------------------------------  USIC_CH_TRBPTR  ------------------------------- */\r
+#define USIC_CH_TRBPTR_TDIPTR_Pos             0                                                       /*!< USIC_CH TRBPTR: TDIPTR Position         */\r
+#define USIC_CH_TRBPTR_TDIPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_TDIPTR_Pos)                   /*!< USIC_CH TRBPTR: TDIPTR Mask             */\r
+#define USIC_CH_TRBPTR_TDOPTR_Pos             8                                                       /*!< USIC_CH TRBPTR: TDOPTR Position         */\r
+#define USIC_CH_TRBPTR_TDOPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_TDOPTR_Pos)                   /*!< USIC_CH TRBPTR: TDOPTR Mask             */\r
+#define USIC_CH_TRBPTR_RDIPTR_Pos             16                                                      /*!< USIC_CH TRBPTR: RDIPTR Position         */\r
+#define USIC_CH_TRBPTR_RDIPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_RDIPTR_Pos)                   /*!< USIC_CH TRBPTR: RDIPTR Mask             */\r
+#define USIC_CH_TRBPTR_RDOPTR_Pos             24                                                      /*!< USIC_CH TRBPTR: RDOPTR Position         */\r
+#define USIC_CH_TRBPTR_RDOPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_RDOPTR_Pos)                   /*!< USIC_CH TRBPTR: RDOPTR Mask             */\r
+\r
+/* --------------------------------  USIC_CH_TRBSR  ------------------------------- */\r
+#define USIC_CH_TRBSR_SRBI_Pos                0                                                       /*!< USIC_CH TRBSR: SRBI Position            */\r
+#define USIC_CH_TRBSR_SRBI_Msk                (0x01UL << USIC_CH_TRBSR_SRBI_Pos)                      /*!< USIC_CH TRBSR: SRBI Mask                */\r
+#define USIC_CH_TRBSR_RBERI_Pos               1                                                       /*!< USIC_CH TRBSR: RBERI Position           */\r
+#define USIC_CH_TRBSR_RBERI_Msk               (0x01UL << USIC_CH_TRBSR_RBERI_Pos)                     /*!< USIC_CH TRBSR: RBERI Mask               */\r
+#define USIC_CH_TRBSR_ARBI_Pos                2                                                       /*!< USIC_CH TRBSR: ARBI Position            */\r
+#define USIC_CH_TRBSR_ARBI_Msk                (0x01UL << USIC_CH_TRBSR_ARBI_Pos)                      /*!< USIC_CH TRBSR: ARBI Mask                */\r
+#define USIC_CH_TRBSR_REMPTY_Pos              3                                                       /*!< USIC_CH TRBSR: REMPTY Position          */\r
+#define USIC_CH_TRBSR_REMPTY_Msk              (0x01UL << USIC_CH_TRBSR_REMPTY_Pos)                    /*!< USIC_CH TRBSR: REMPTY Mask              */\r
+#define USIC_CH_TRBSR_RFULL_Pos               4                                                       /*!< USIC_CH TRBSR: RFULL Position           */\r
+#define USIC_CH_TRBSR_RFULL_Msk               (0x01UL << USIC_CH_TRBSR_RFULL_Pos)                     /*!< USIC_CH TRBSR: RFULL Mask               */\r
+#define USIC_CH_TRBSR_RBUS_Pos                5                                                       /*!< USIC_CH TRBSR: RBUS Position            */\r
+#define USIC_CH_TRBSR_RBUS_Msk                (0x01UL << USIC_CH_TRBSR_RBUS_Pos)                      /*!< USIC_CH TRBSR: RBUS Mask                */\r
+#define USIC_CH_TRBSR_SRBT_Pos                6                                                       /*!< USIC_CH TRBSR: SRBT Position            */\r
+#define USIC_CH_TRBSR_SRBT_Msk                (0x01UL << USIC_CH_TRBSR_SRBT_Pos)                      /*!< USIC_CH TRBSR: SRBT Mask                */\r
+#define USIC_CH_TRBSR_STBI_Pos                8                                                       /*!< USIC_CH TRBSR: STBI Position            */\r
+#define USIC_CH_TRBSR_STBI_Msk                (0x01UL << USIC_CH_TRBSR_STBI_Pos)                      /*!< USIC_CH TRBSR: STBI Mask                */\r
+#define USIC_CH_TRBSR_TBERI_Pos               9                                                       /*!< USIC_CH TRBSR: TBERI Position           */\r
+#define USIC_CH_TRBSR_TBERI_Msk               (0x01UL << USIC_CH_TRBSR_TBERI_Pos)                     /*!< USIC_CH TRBSR: TBERI Mask               */\r
+#define USIC_CH_TRBSR_TEMPTY_Pos              11                                                      /*!< USIC_CH TRBSR: TEMPTY Position          */\r
+#define USIC_CH_TRBSR_TEMPTY_Msk              (0x01UL << USIC_CH_TRBSR_TEMPTY_Pos)                    /*!< USIC_CH TRBSR: TEMPTY Mask              */\r
+#define USIC_CH_TRBSR_TFULL_Pos               12                                                      /*!< USIC_CH TRBSR: TFULL Position           */\r
+#define USIC_CH_TRBSR_TFULL_Msk               (0x01UL << USIC_CH_TRBSR_TFULL_Pos)                     /*!< USIC_CH TRBSR: TFULL Mask               */\r
+#define USIC_CH_TRBSR_TBUS_Pos                13                                                      /*!< USIC_CH TRBSR: TBUS Position            */\r
+#define USIC_CH_TRBSR_TBUS_Msk                (0x01UL << USIC_CH_TRBSR_TBUS_Pos)                      /*!< USIC_CH TRBSR: TBUS Mask                */\r
+#define USIC_CH_TRBSR_STBT_Pos                14                                                      /*!< USIC_CH TRBSR: STBT Position            */\r
+#define USIC_CH_TRBSR_STBT_Msk                (0x01UL << USIC_CH_TRBSR_STBT_Pos)                      /*!< USIC_CH TRBSR: STBT Mask                */\r
+#define USIC_CH_TRBSR_RBFLVL_Pos              16                                                      /*!< USIC_CH TRBSR: RBFLVL Position          */\r
+#define USIC_CH_TRBSR_RBFLVL_Msk              (0x7fUL << USIC_CH_TRBSR_RBFLVL_Pos)                    /*!< USIC_CH TRBSR: RBFLVL Mask              */\r
+#define USIC_CH_TRBSR_TBFLVL_Pos              24                                                      /*!< USIC_CH TRBSR: TBFLVL Position          */\r
+#define USIC_CH_TRBSR_TBFLVL_Msk              (0x7fUL << USIC_CH_TRBSR_TBFLVL_Pos)                    /*!< USIC_CH TRBSR: TBFLVL Mask              */\r
+\r
+/* -------------------------------  USIC_CH_TRBSCR  ------------------------------- */\r
+#define USIC_CH_TRBSCR_CSRBI_Pos              0                                                       /*!< USIC_CH TRBSCR: CSRBI Position          */\r
+#define USIC_CH_TRBSCR_CSRBI_Msk              (0x01UL << USIC_CH_TRBSCR_CSRBI_Pos)                    /*!< USIC_CH TRBSCR: CSRBI Mask              */\r
+#define USIC_CH_TRBSCR_CRBERI_Pos             1                                                       /*!< USIC_CH TRBSCR: CRBERI Position         */\r
+#define USIC_CH_TRBSCR_CRBERI_Msk             (0x01UL << USIC_CH_TRBSCR_CRBERI_Pos)                   /*!< USIC_CH TRBSCR: CRBERI Mask             */\r
+#define USIC_CH_TRBSCR_CARBI_Pos              2                                                       /*!< USIC_CH TRBSCR: CARBI Position          */\r
+#define USIC_CH_TRBSCR_CARBI_Msk              (0x01UL << USIC_CH_TRBSCR_CARBI_Pos)                    /*!< USIC_CH TRBSCR: CARBI Mask              */\r
+#define USIC_CH_TRBSCR_CSTBI_Pos              8                                                       /*!< USIC_CH TRBSCR: CSTBI Position          */\r
+#define USIC_CH_TRBSCR_CSTBI_Msk              (0x01UL << USIC_CH_TRBSCR_CSTBI_Pos)                    /*!< USIC_CH TRBSCR: CSTBI Mask              */\r
+#define USIC_CH_TRBSCR_CTBERI_Pos             9                                                       /*!< USIC_CH TRBSCR: CTBERI Position         */\r
+#define USIC_CH_TRBSCR_CTBERI_Msk             (0x01UL << USIC_CH_TRBSCR_CTBERI_Pos)                   /*!< USIC_CH TRBSCR: CTBERI Mask             */\r
+#define USIC_CH_TRBSCR_CBDV_Pos               10                                                      /*!< USIC_CH TRBSCR: CBDV Position           */\r
+#define USIC_CH_TRBSCR_CBDV_Msk               (0x01UL << USIC_CH_TRBSCR_CBDV_Pos)                     /*!< USIC_CH TRBSCR: CBDV Mask               */\r
+#define USIC_CH_TRBSCR_FLUSHRB_Pos            14                                                      /*!< USIC_CH TRBSCR: FLUSHRB Position        */\r
+#define USIC_CH_TRBSCR_FLUSHRB_Msk            (0x01UL << USIC_CH_TRBSCR_FLUSHRB_Pos)                  /*!< USIC_CH TRBSCR: FLUSHRB Mask            */\r
+#define USIC_CH_TRBSCR_FLUSHTB_Pos            15                                                      /*!< USIC_CH TRBSCR: FLUSHTB Position        */\r
+#define USIC_CH_TRBSCR_FLUSHTB_Msk            (0x01UL << USIC_CH_TRBSCR_FLUSHTB_Pos)                  /*!< USIC_CH TRBSCR: FLUSHTB Mask            */\r
+\r
+/* --------------------------------  USIC_CH_OUTR  -------------------------------- */\r
+#define USIC_CH_OUTR_DSR_Pos                  0                                                       /*!< USIC_CH OUTR: DSR Position              */\r
+#define USIC_CH_OUTR_DSR_Msk                  (0x0000ffffUL << USIC_CH_OUTR_DSR_Pos)                  /*!< USIC_CH OUTR: DSR Mask                  */\r
+#define USIC_CH_OUTR_RCI_Pos                  16                                                      /*!< USIC_CH OUTR: RCI Position              */\r
+#define USIC_CH_OUTR_RCI_Msk                  (0x1fUL << USIC_CH_OUTR_RCI_Pos)                        /*!< USIC_CH OUTR: RCI Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_OUTDR  ------------------------------- */\r
+#define USIC_CH_OUTDR_DSR_Pos                 0                                                       /*!< USIC_CH OUTDR: DSR Position             */\r
+#define USIC_CH_OUTDR_DSR_Msk                 (0x0000ffffUL << USIC_CH_OUTDR_DSR_Pos)                 /*!< USIC_CH OUTDR: DSR Mask                 */\r
+#define USIC_CH_OUTDR_RCI_Pos                 16                                                      /*!< USIC_CH OUTDR: RCI Position             */\r
+#define USIC_CH_OUTDR_RCI_Msk                 (0x1fUL << USIC_CH_OUTDR_RCI_Pos)                       /*!< USIC_CH OUTDR: RCI Mask                 */\r
+\r
+/* ---------------------------------  USIC_CH_IN  --------------------------------- */\r
+#define USIC_CH_IN_TDATA_Pos                  0                                                       /*!< USIC_CH IN: TDATA Position              */\r
+#define USIC_CH_IN_TDATA_Msk                  (0x0000ffffUL << USIC_CH_IN_TDATA_Pos)                  /*!< USIC_CH IN: TDATA Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'CAN' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  CAN_CLC  ---------------------------------- */\r
+#define CAN_CLC_DISR_Pos                      0                                                       /*!< CAN CLC: DISR Position                  */\r
+#define CAN_CLC_DISR_Msk                      (0x01UL << CAN_CLC_DISR_Pos)                            /*!< CAN CLC: DISR Mask                      */\r
+#define CAN_CLC_DISS_Pos                      1                                                       /*!< CAN CLC: DISS Position                  */\r
+#define CAN_CLC_DISS_Msk                      (0x01UL << CAN_CLC_DISS_Pos)                            /*!< CAN CLC: DISS Mask                      */\r
+#define CAN_CLC_EDIS_Pos                      3                                                       /*!< CAN CLC: EDIS Position                  */\r
+#define CAN_CLC_EDIS_Msk                      (0x01UL << CAN_CLC_EDIS_Pos)                            /*!< CAN CLC: EDIS Mask                      */\r
+#define CAN_CLC_SBWE_Pos                      4                                                       /*!< CAN CLC: SBWE Position                  */\r
+#define CAN_CLC_SBWE_Msk                      (0x01UL << CAN_CLC_SBWE_Pos)                            /*!< CAN CLC: SBWE Mask                      */\r
+\r
+/* -----------------------------------  CAN_ID  ----------------------------------- */\r
+#define CAN_ID_MOD_REV_Pos                    0                                                       /*!< CAN ID: MOD_REV Position                */\r
+#define CAN_ID_MOD_REV_Msk                    (0x000000ffUL << CAN_ID_MOD_REV_Pos)                    /*!< CAN ID: MOD_REV Mask                    */\r
+#define CAN_ID_MOD_TYPE_Pos                   8                                                       /*!< CAN ID: MOD_TYPE Position               */\r
+#define CAN_ID_MOD_TYPE_Msk                   (0x000000ffUL << CAN_ID_MOD_TYPE_Pos)                   /*!< CAN ID: MOD_TYPE Mask                   */\r
+#define CAN_ID_MOD_NUMBER_Pos                 16                                                      /*!< CAN ID: MOD_NUMBER Position             */\r
+#define CAN_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << CAN_ID_MOD_NUMBER_Pos)                 /*!< CAN ID: MOD_NUMBER Mask                 */\r
+\r
+/* -----------------------------------  CAN_FDR  ---------------------------------- */\r
+#define CAN_FDR_STEP_Pos                      0                                                       /*!< CAN FDR: STEP Position                  */\r
+#define CAN_FDR_STEP_Msk                      (0x000003ffUL << CAN_FDR_STEP_Pos)                      /*!< CAN FDR: STEP Mask                      */\r
+#define CAN_FDR_SM_Pos                        11                                                      /*!< CAN FDR: SM Position                    */\r
+#define CAN_FDR_SM_Msk                        (0x01UL << CAN_FDR_SM_Pos)                              /*!< CAN FDR: SM Mask                        */\r
+#define CAN_FDR_SC_Pos                        12                                                      /*!< CAN FDR: SC Position                    */\r
+#define CAN_FDR_SC_Msk                        (0x03UL << CAN_FDR_SC_Pos)                              /*!< CAN FDR: SC Mask                        */\r
+#define CAN_FDR_DM_Pos                        14                                                      /*!< CAN FDR: DM Position                    */\r
+#define CAN_FDR_DM_Msk                        (0x03UL << CAN_FDR_DM_Pos)                              /*!< CAN FDR: DM Mask                        */\r
+#define CAN_FDR_RESULT_Pos                    16                                                      /*!< CAN FDR: RESULT Position                */\r
+#define CAN_FDR_RESULT_Msk                    (0x000003ffUL << CAN_FDR_RESULT_Pos)                    /*!< CAN FDR: RESULT Mask                    */\r
+#define CAN_FDR_SUSACK_Pos                    28                                                      /*!< CAN FDR: SUSACK Position                */\r
+#define CAN_FDR_SUSACK_Msk                    (0x01UL << CAN_FDR_SUSACK_Pos)                          /*!< CAN FDR: SUSACK Mask                    */\r
+#define CAN_FDR_SUSREQ_Pos                    29                                                      /*!< CAN FDR: SUSREQ Position                */\r
+#define CAN_FDR_SUSREQ_Msk                    (0x01UL << CAN_FDR_SUSREQ_Pos)                          /*!< CAN FDR: SUSREQ Mask                    */\r
+#define CAN_FDR_ENHW_Pos                      30                                                      /*!< CAN FDR: ENHW Position                  */\r
+#define CAN_FDR_ENHW_Msk                      (0x01UL << CAN_FDR_ENHW_Pos)                            /*!< CAN FDR: ENHW Mask                      */\r
+#define CAN_FDR_DISCLK_Pos                    31                                                      /*!< CAN FDR: DISCLK Position                */\r
+#define CAN_FDR_DISCLK_Msk                    (0x01UL << CAN_FDR_DISCLK_Pos)                          /*!< CAN FDR: DISCLK Mask                    */\r
+\r
+/* ----------------------------------  CAN_LIST  ---------------------------------- */\r
+#define CAN_LIST_BEGIN_Pos                    0                                                       /*!< CAN LIST: BEGIN Position                */\r
+#define CAN_LIST_BEGIN_Msk                    (0x000000ffUL << CAN_LIST_BEGIN_Pos)                    /*!< CAN LIST: BEGIN Mask                    */\r
+#define CAN_LIST_END_Pos                      8                                                       /*!< CAN LIST: END Position                  */\r
+#define CAN_LIST_END_Msk                      (0x000000ffUL << CAN_LIST_END_Pos)                      /*!< CAN LIST: END Mask                      */\r
+#define CAN_LIST_SIZE_Pos                     16                                                      /*!< CAN LIST: SIZE Position                 */\r
+#define CAN_LIST_SIZE_Msk                     (0x000000ffUL << CAN_LIST_SIZE_Pos)                     /*!< CAN LIST: SIZE Mask                     */\r
+#define CAN_LIST_EMPTY_Pos                    24                                                      /*!< CAN LIST: EMPTY Position                */\r
+#define CAN_LIST_EMPTY_Msk                    (0x01UL << CAN_LIST_EMPTY_Pos)                          /*!< CAN LIST: EMPTY Mask                    */\r
+\r
+/* ----------------------------------  CAN_MSPND  --------------------------------- */\r
+#define CAN_MSPND_PND_Pos                     0                                                       /*!< CAN MSPND: PND Position                 */\r
+#define CAN_MSPND_PND_Msk                     (0xffffffffUL << CAN_MSPND_PND_Pos)                     /*!< CAN MSPND: PND Mask                     */\r
+\r
+/* ----------------------------------  CAN_MSID  ---------------------------------- */\r
+#define CAN_MSID_INDEX_Pos                    0                                                       /*!< CAN MSID: INDEX Position                */\r
+#define CAN_MSID_INDEX_Msk                    (0x3fUL << CAN_MSID_INDEX_Pos)                          /*!< CAN MSID: INDEX Mask                    */\r
+\r
+/* ---------------------------------  CAN_MSIMASK  -------------------------------- */\r
+#define CAN_MSIMASK_IM_Pos                    0                                                       /*!< CAN MSIMASK: IM Position                */\r
+#define CAN_MSIMASK_IM_Msk                    (0xffffffffUL << CAN_MSIMASK_IM_Pos)                    /*!< CAN MSIMASK: IM Mask                    */\r
+\r
+/* ---------------------------------  CAN_PANCTR  --------------------------------- */\r
+#define CAN_PANCTR_PANCMD_Pos                 0                                                       /*!< CAN PANCTR: PANCMD Position             */\r
+#define CAN_PANCTR_PANCMD_Msk                 (0x000000ffUL << CAN_PANCTR_PANCMD_Pos)                 /*!< CAN PANCTR: PANCMD Mask                 */\r
+#define CAN_PANCTR_BUSY_Pos                   8                                                       /*!< CAN PANCTR: BUSY Position               */\r
+#define CAN_PANCTR_BUSY_Msk                   (0x01UL << CAN_PANCTR_BUSY_Pos)                         /*!< CAN PANCTR: BUSY Mask                   */\r
+#define CAN_PANCTR_RBUSY_Pos                  9                                                       /*!< CAN PANCTR: RBUSY Position              */\r
+#define CAN_PANCTR_RBUSY_Msk                  (0x01UL << CAN_PANCTR_RBUSY_Pos)                        /*!< CAN PANCTR: RBUSY Mask                  */\r
+#define CAN_PANCTR_PANAR1_Pos                 16                                                      /*!< CAN PANCTR: PANAR1 Position             */\r
+#define CAN_PANCTR_PANAR1_Msk                 (0x000000ffUL << CAN_PANCTR_PANAR1_Pos)                 /*!< CAN PANCTR: PANAR1 Mask                 */\r
+#define CAN_PANCTR_PANAR2_Pos                 24                                                      /*!< CAN PANCTR: PANAR2 Position             */\r
+#define CAN_PANCTR_PANAR2_Msk                 (0x000000ffUL << CAN_PANCTR_PANAR2_Pos)                 /*!< CAN PANCTR: PANAR2 Mask                 */\r
+\r
+/* -----------------------------------  CAN_MCR  ---------------------------------- */\r
+#define CAN_MCR_MPSEL_Pos                     12                                                      /*!< CAN MCR: MPSEL Position                 */\r
+#define CAN_MCR_MPSEL_Msk                     (0x0fUL << CAN_MCR_MPSEL_Pos)                           /*!< CAN MCR: MPSEL Mask                     */\r
+\r
+/* ----------------------------------  CAN_MITR  ---------------------------------- */\r
+#define CAN_MITR_IT_Pos                       0                                                       /*!< CAN MITR: IT Position                   */\r
+#define CAN_MITR_IT_Msk                       (0x000000ffUL << CAN_MITR_IT_Pos)                       /*!< CAN MITR: IT Mask                       */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        Group 'CAN_NODE' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CAN_NODE_NCR  -------------------------------- */\r
+#define CAN_NODE_NCR_INIT_Pos                 0                                                       /*!< CAN_NODE NCR: INIT Position             */\r
+#define CAN_NODE_NCR_INIT_Msk                 (0x01UL << CAN_NODE_NCR_INIT_Pos)                       /*!< CAN_NODE NCR: INIT Mask                 */\r
+#define CAN_NODE_NCR_TRIE_Pos                 1                                                       /*!< CAN_NODE NCR: TRIE Position             */\r
+#define CAN_NODE_NCR_TRIE_Msk                 (0x01UL << CAN_NODE_NCR_TRIE_Pos)                       /*!< CAN_NODE NCR: TRIE Mask                 */\r
+#define CAN_NODE_NCR_LECIE_Pos                2                                                       /*!< CAN_NODE NCR: LECIE Position            */\r
+#define CAN_NODE_NCR_LECIE_Msk                (0x01UL << CAN_NODE_NCR_LECIE_Pos)                      /*!< CAN_NODE NCR: LECIE Mask                */\r
+#define CAN_NODE_NCR_ALIE_Pos                 3                                                       /*!< CAN_NODE NCR: ALIE Position             */\r
+#define CAN_NODE_NCR_ALIE_Msk                 (0x01UL << CAN_NODE_NCR_ALIE_Pos)                       /*!< CAN_NODE NCR: ALIE Mask                 */\r
+#define CAN_NODE_NCR_CANDIS_Pos               4                                                       /*!< CAN_NODE NCR: CANDIS Position           */\r
+#define CAN_NODE_NCR_CANDIS_Msk               (0x01UL << CAN_NODE_NCR_CANDIS_Pos)                     /*!< CAN_NODE NCR: CANDIS Mask               */\r
+#define CAN_NODE_NCR_CCE_Pos                  6                                                       /*!< CAN_NODE NCR: CCE Position              */\r
+#define CAN_NODE_NCR_CCE_Msk                  (0x01UL << CAN_NODE_NCR_CCE_Pos)                        /*!< CAN_NODE NCR: CCE Mask                  */\r
+#define CAN_NODE_NCR_CALM_Pos                 7                                                       /*!< CAN_NODE NCR: CALM Position             */\r
+#define CAN_NODE_NCR_CALM_Msk                 (0x01UL << CAN_NODE_NCR_CALM_Pos)                       /*!< CAN_NODE NCR: CALM Mask                 */\r
+#define CAN_NODE_NCR_SUSEN_Pos                8                                                       /*!< CAN_NODE NCR: SUSEN Position            */\r
+#define CAN_NODE_NCR_SUSEN_Msk                (0x01UL << CAN_NODE_NCR_SUSEN_Pos)                      /*!< CAN_NODE NCR: SUSEN Mask                */\r
+\r
+/* --------------------------------  CAN_NODE_NSR  -------------------------------- */\r
+#define CAN_NODE_NSR_LEC_Pos                  0                                                       /*!< CAN_NODE NSR: LEC Position              */\r
+#define CAN_NODE_NSR_LEC_Msk                  (0x07UL << CAN_NODE_NSR_LEC_Pos)                        /*!< CAN_NODE NSR: LEC Mask                  */\r
+#define CAN_NODE_NSR_TXOK_Pos                 3                                                       /*!< CAN_NODE NSR: TXOK Position             */\r
+#define CAN_NODE_NSR_TXOK_Msk                 (0x01UL << CAN_NODE_NSR_TXOK_Pos)                       /*!< CAN_NODE NSR: TXOK Mask                 */\r
+#define CAN_NODE_NSR_RXOK_Pos                 4                                                       /*!< CAN_NODE NSR: RXOK Position             */\r
+#define CAN_NODE_NSR_RXOK_Msk                 (0x01UL << CAN_NODE_NSR_RXOK_Pos)                       /*!< CAN_NODE NSR: RXOK Mask                 */\r
+#define CAN_NODE_NSR_ALERT_Pos                5                                                       /*!< CAN_NODE NSR: ALERT Position            */\r
+#define CAN_NODE_NSR_ALERT_Msk                (0x01UL << CAN_NODE_NSR_ALERT_Pos)                      /*!< CAN_NODE NSR: ALERT Mask                */\r
+#define CAN_NODE_NSR_EWRN_Pos                 6                                                       /*!< CAN_NODE NSR: EWRN Position             */\r
+#define CAN_NODE_NSR_EWRN_Msk                 (0x01UL << CAN_NODE_NSR_EWRN_Pos)                       /*!< CAN_NODE NSR: EWRN Mask                 */\r
+#define CAN_NODE_NSR_BOFF_Pos                 7                                                       /*!< CAN_NODE NSR: BOFF Position             */\r
+#define CAN_NODE_NSR_BOFF_Msk                 (0x01UL << CAN_NODE_NSR_BOFF_Pos)                       /*!< CAN_NODE NSR: BOFF Mask                 */\r
+#define CAN_NODE_NSR_LLE_Pos                  8                                                       /*!< CAN_NODE NSR: LLE Position              */\r
+#define CAN_NODE_NSR_LLE_Msk                  (0x01UL << CAN_NODE_NSR_LLE_Pos)                        /*!< CAN_NODE NSR: LLE Mask                  */\r
+#define CAN_NODE_NSR_LOE_Pos                  9                                                       /*!< CAN_NODE NSR: LOE Position              */\r
+#define CAN_NODE_NSR_LOE_Msk                  (0x01UL << CAN_NODE_NSR_LOE_Pos)                        /*!< CAN_NODE NSR: LOE Mask                  */\r
+#define CAN_NODE_NSR_SUSACK_Pos               10                                                      /*!< CAN_NODE NSR: SUSACK Position           */\r
+#define CAN_NODE_NSR_SUSACK_Msk               (0x01UL << CAN_NODE_NSR_SUSACK_Pos)                     /*!< CAN_NODE NSR: SUSACK Mask               */\r
+\r
+/* --------------------------------  CAN_NODE_NIPR  ------------------------------- */\r
+#define CAN_NODE_NIPR_ALINP_Pos               0                                                       /*!< CAN_NODE NIPR: ALINP Position           */\r
+#define CAN_NODE_NIPR_ALINP_Msk               (0x07UL << CAN_NODE_NIPR_ALINP_Pos)                     /*!< CAN_NODE NIPR: ALINP Mask               */\r
+#define CAN_NODE_NIPR_LECINP_Pos              4                                                       /*!< CAN_NODE NIPR: LECINP Position          */\r
+#define CAN_NODE_NIPR_LECINP_Msk              (0x07UL << CAN_NODE_NIPR_LECINP_Pos)                    /*!< CAN_NODE NIPR: LECINP Mask              */\r
+#define CAN_NODE_NIPR_TRINP_Pos               8                                                       /*!< CAN_NODE NIPR: TRINP Position           */\r
+#define CAN_NODE_NIPR_TRINP_Msk               (0x07UL << CAN_NODE_NIPR_TRINP_Pos)                     /*!< CAN_NODE NIPR: TRINP Mask               */\r
+#define CAN_NODE_NIPR_CFCINP_Pos              12                                                      /*!< CAN_NODE NIPR: CFCINP Position          */\r
+#define CAN_NODE_NIPR_CFCINP_Msk              (0x07UL << CAN_NODE_NIPR_CFCINP_Pos)                    /*!< CAN_NODE NIPR: CFCINP Mask              */\r
+\r
+/* --------------------------------  CAN_NODE_NPCR  ------------------------------- */\r
+#define CAN_NODE_NPCR_RXSEL_Pos               0                                                       /*!< CAN_NODE NPCR: RXSEL Position           */\r
+#define CAN_NODE_NPCR_RXSEL_Msk               (0x07UL << CAN_NODE_NPCR_RXSEL_Pos)                     /*!< CAN_NODE NPCR: RXSEL Mask               */\r
+#define CAN_NODE_NPCR_LBM_Pos                 8                                                       /*!< CAN_NODE NPCR: LBM Position             */\r
+#define CAN_NODE_NPCR_LBM_Msk                 (0x01UL << CAN_NODE_NPCR_LBM_Pos)                       /*!< CAN_NODE NPCR: LBM Mask                 */\r
+\r
+/* --------------------------------  CAN_NODE_NBTR  ------------------------------- */\r
+#define CAN_NODE_NBTR_BRP_Pos                 0                                                       /*!< CAN_NODE NBTR: BRP Position             */\r
+#define CAN_NODE_NBTR_BRP_Msk                 (0x3fUL << CAN_NODE_NBTR_BRP_Pos)                       /*!< CAN_NODE NBTR: BRP Mask                 */\r
+#define CAN_NODE_NBTR_SJW_Pos                 6                                                       /*!< CAN_NODE NBTR: SJW Position             */\r
+#define CAN_NODE_NBTR_SJW_Msk                 (0x03UL << CAN_NODE_NBTR_SJW_Pos)                       /*!< CAN_NODE NBTR: SJW Mask                 */\r
+#define CAN_NODE_NBTR_TSEG1_Pos               8                                                       /*!< CAN_NODE NBTR: TSEG1 Position           */\r
+#define CAN_NODE_NBTR_TSEG1_Msk               (0x0fUL << CAN_NODE_NBTR_TSEG1_Pos)                     /*!< CAN_NODE NBTR: TSEG1 Mask               */\r
+#define CAN_NODE_NBTR_TSEG2_Pos               12                                                      /*!< CAN_NODE NBTR: TSEG2 Position           */\r
+#define CAN_NODE_NBTR_TSEG2_Msk               (0x07UL << CAN_NODE_NBTR_TSEG2_Pos)                     /*!< CAN_NODE NBTR: TSEG2 Mask               */\r
+#define CAN_NODE_NBTR_DIV8_Pos                15                                                      /*!< CAN_NODE NBTR: DIV8 Position            */\r
+#define CAN_NODE_NBTR_DIV8_Msk                (0x01UL << CAN_NODE_NBTR_DIV8_Pos)                      /*!< CAN_NODE NBTR: DIV8 Mask                */\r
+\r
+/* -------------------------------  CAN_NODE_NECNT  ------------------------------- */\r
+#define CAN_NODE_NECNT_REC_Pos                0                                                       /*!< CAN_NODE NECNT: REC Position            */\r
+#define CAN_NODE_NECNT_REC_Msk                (0x000000ffUL << CAN_NODE_NECNT_REC_Pos)                /*!< CAN_NODE NECNT: REC Mask                */\r
+#define CAN_NODE_NECNT_TEC_Pos                8                                                       /*!< CAN_NODE NECNT: TEC Position            */\r
+#define CAN_NODE_NECNT_TEC_Msk                (0x000000ffUL << CAN_NODE_NECNT_TEC_Pos)                /*!< CAN_NODE NECNT: TEC Mask                */\r
+#define CAN_NODE_NECNT_EWRNLVL_Pos            16                                                      /*!< CAN_NODE NECNT: EWRNLVL Position        */\r
+#define CAN_NODE_NECNT_EWRNLVL_Msk            (0x000000ffUL << CAN_NODE_NECNT_EWRNLVL_Pos)            /*!< CAN_NODE NECNT: EWRNLVL Mask            */\r
+#define CAN_NODE_NECNT_LETD_Pos               24                                                      /*!< CAN_NODE NECNT: LETD Position           */\r
+#define CAN_NODE_NECNT_LETD_Msk               (0x01UL << CAN_NODE_NECNT_LETD_Pos)                     /*!< CAN_NODE NECNT: LETD Mask               */\r
+#define CAN_NODE_NECNT_LEINC_Pos              25                                                      /*!< CAN_NODE NECNT: LEINC Position          */\r
+#define CAN_NODE_NECNT_LEINC_Msk              (0x01UL << CAN_NODE_NECNT_LEINC_Pos)                    /*!< CAN_NODE NECNT: LEINC Mask              */\r
+\r
+/* --------------------------------  CAN_NODE_NFCR  ------------------------------- */\r
+#define CAN_NODE_NFCR_CFC_Pos                 0                                                       /*!< CAN_NODE NFCR: CFC Position             */\r
+#define CAN_NODE_NFCR_CFC_Msk                 (0x0000ffffUL << CAN_NODE_NFCR_CFC_Pos)                 /*!< CAN_NODE NFCR: CFC Mask                 */\r
+#define CAN_NODE_NFCR_CFSEL_Pos               16                                                      /*!< CAN_NODE NFCR: CFSEL Position           */\r
+#define CAN_NODE_NFCR_CFSEL_Msk               (0x07UL << CAN_NODE_NFCR_CFSEL_Pos)                     /*!< CAN_NODE NFCR: CFSEL Mask               */\r
+#define CAN_NODE_NFCR_CFMOD_Pos               19                                                      /*!< CAN_NODE NFCR: CFMOD Position           */\r
+#define CAN_NODE_NFCR_CFMOD_Msk               (0x03UL << CAN_NODE_NFCR_CFMOD_Pos)                     /*!< CAN_NODE NFCR: CFMOD Mask               */\r
+#define CAN_NODE_NFCR_CFCIE_Pos               22                                                      /*!< CAN_NODE NFCR: CFCIE Position           */\r
+#define CAN_NODE_NFCR_CFCIE_Msk               (0x01UL << CAN_NODE_NFCR_CFCIE_Pos)                     /*!< CAN_NODE NFCR: CFCIE Mask               */\r
+#define CAN_NODE_NFCR_CFCOV_Pos               23                                                      /*!< CAN_NODE NFCR: CFCOV Position           */\r
+#define CAN_NODE_NFCR_CFCOV_Msk               (0x01UL << CAN_NODE_NFCR_CFCOV_Pos)                     /*!< CAN_NODE NFCR: CFCOV Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'CAN_MO' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CAN_MO_MOFCR  -------------------------------- */\r
+#define CAN_MO_MOFCR_MMC_Pos                  0                                                       /*!< CAN_MO MOFCR: MMC Position              */\r
+#define CAN_MO_MOFCR_MMC_Msk                  (0x0fUL << CAN_MO_MOFCR_MMC_Pos)                        /*!< CAN_MO MOFCR: MMC Mask                  */\r
+#define CAN_MO_MOFCR_GDFS_Pos                 8                                                       /*!< CAN_MO MOFCR: GDFS Position             */\r
+#define CAN_MO_MOFCR_GDFS_Msk                 (0x01UL << CAN_MO_MOFCR_GDFS_Pos)                       /*!< CAN_MO MOFCR: GDFS Mask                 */\r
+#define CAN_MO_MOFCR_IDC_Pos                  9                                                       /*!< CAN_MO MOFCR: IDC Position              */\r
+#define CAN_MO_MOFCR_IDC_Msk                  (0x01UL << CAN_MO_MOFCR_IDC_Pos)                        /*!< CAN_MO MOFCR: IDC Mask                  */\r
+#define CAN_MO_MOFCR_DLCC_Pos                 10                                                      /*!< CAN_MO MOFCR: DLCC Position             */\r
+#define CAN_MO_MOFCR_DLCC_Msk                 (0x01UL << CAN_MO_MOFCR_DLCC_Pos)                       /*!< CAN_MO MOFCR: DLCC Mask                 */\r
+#define CAN_MO_MOFCR_DATC_Pos                 11                                                      /*!< CAN_MO MOFCR: DATC Position             */\r
+#define CAN_MO_MOFCR_DATC_Msk                 (0x01UL << CAN_MO_MOFCR_DATC_Pos)                       /*!< CAN_MO MOFCR: DATC Mask                 */\r
+#define CAN_MO_MOFCR_RXIE_Pos                 16                                                      /*!< CAN_MO MOFCR: RXIE Position             */\r
+#define CAN_MO_MOFCR_RXIE_Msk                 (0x01UL << CAN_MO_MOFCR_RXIE_Pos)                       /*!< CAN_MO MOFCR: RXIE Mask                 */\r
+#define CAN_MO_MOFCR_TXIE_Pos                 17                                                      /*!< CAN_MO MOFCR: TXIE Position             */\r
+#define CAN_MO_MOFCR_TXIE_Msk                 (0x01UL << CAN_MO_MOFCR_TXIE_Pos)                       /*!< CAN_MO MOFCR: TXIE Mask                 */\r
+#define CAN_MO_MOFCR_OVIE_Pos                 18                                                      /*!< CAN_MO MOFCR: OVIE Position             */\r
+#define CAN_MO_MOFCR_OVIE_Msk                 (0x01UL << CAN_MO_MOFCR_OVIE_Pos)                       /*!< CAN_MO MOFCR: OVIE Mask                 */\r
+#define CAN_MO_MOFCR_FRREN_Pos                20                                                      /*!< CAN_MO MOFCR: FRREN Position            */\r
+#define CAN_MO_MOFCR_FRREN_Msk                (0x01UL << CAN_MO_MOFCR_FRREN_Pos)                      /*!< CAN_MO MOFCR: FRREN Mask                */\r
+#define CAN_MO_MOFCR_RMM_Pos                  21                                                      /*!< CAN_MO MOFCR: RMM Position              */\r
+#define CAN_MO_MOFCR_RMM_Msk                  (0x01UL << CAN_MO_MOFCR_RMM_Pos)                        /*!< CAN_MO MOFCR: RMM Mask                  */\r
+#define CAN_MO_MOFCR_SDT_Pos                  22                                                      /*!< CAN_MO MOFCR: SDT Position              */\r
+#define CAN_MO_MOFCR_SDT_Msk                  (0x01UL << CAN_MO_MOFCR_SDT_Pos)                        /*!< CAN_MO MOFCR: SDT Mask                  */\r
+#define CAN_MO_MOFCR_STT_Pos                  23                                                      /*!< CAN_MO MOFCR: STT Position              */\r
+#define CAN_MO_MOFCR_STT_Msk                  (0x01UL << CAN_MO_MOFCR_STT_Pos)                        /*!< CAN_MO MOFCR: STT Mask                  */\r
+#define CAN_MO_MOFCR_DLC_Pos                  24                                                      /*!< CAN_MO MOFCR: DLC Position              */\r
+#define CAN_MO_MOFCR_DLC_Msk                  (0x0fUL << CAN_MO_MOFCR_DLC_Pos)                        /*!< CAN_MO MOFCR: DLC Mask                  */\r
+\r
+/* --------------------------------  CAN_MO_MOFGPR  ------------------------------- */\r
+#define CAN_MO_MOFGPR_BOT_Pos                 0                                                       /*!< CAN_MO MOFGPR: BOT Position             */\r
+#define CAN_MO_MOFGPR_BOT_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_BOT_Pos)                 /*!< CAN_MO MOFGPR: BOT Mask                 */\r
+#define CAN_MO_MOFGPR_TOP_Pos                 8                                                       /*!< CAN_MO MOFGPR: TOP Position             */\r
+#define CAN_MO_MOFGPR_TOP_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_TOP_Pos)                 /*!< CAN_MO MOFGPR: TOP Mask                 */\r
+#define CAN_MO_MOFGPR_CUR_Pos                 16                                                      /*!< CAN_MO MOFGPR: CUR Position             */\r
+#define CAN_MO_MOFGPR_CUR_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_CUR_Pos)                 /*!< CAN_MO MOFGPR: CUR Mask                 */\r
+#define CAN_MO_MOFGPR_SEL_Pos                 24                                                      /*!< CAN_MO MOFGPR: SEL Position             */\r
+#define CAN_MO_MOFGPR_SEL_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_SEL_Pos)                 /*!< CAN_MO MOFGPR: SEL Mask                 */\r
+\r
+/* --------------------------------  CAN_MO_MOIPR  -------------------------------- */\r
+#define CAN_MO_MOIPR_RXINP_Pos                0                                                       /*!< CAN_MO MOIPR: RXINP Position            */\r
+#define CAN_MO_MOIPR_RXINP_Msk                (0x07UL << CAN_MO_MOIPR_RXINP_Pos)                      /*!< CAN_MO MOIPR: RXINP Mask                */\r
+#define CAN_MO_MOIPR_TXINP_Pos                4                                                       /*!< CAN_MO MOIPR: TXINP Position            */\r
+#define CAN_MO_MOIPR_TXINP_Msk                (0x07UL << CAN_MO_MOIPR_TXINP_Pos)                      /*!< CAN_MO MOIPR: TXINP Mask                */\r
+#define CAN_MO_MOIPR_MPN_Pos                  8                                                       /*!< CAN_MO MOIPR: MPN Position              */\r
+#define CAN_MO_MOIPR_MPN_Msk                  (0x000000ffUL << CAN_MO_MOIPR_MPN_Pos)                  /*!< CAN_MO MOIPR: MPN Mask                  */\r
+#define CAN_MO_MOIPR_CFCVAL_Pos               16                                                      /*!< CAN_MO MOIPR: CFCVAL Position           */\r
+#define CAN_MO_MOIPR_CFCVAL_Msk               (0x0000ffffUL << CAN_MO_MOIPR_CFCVAL_Pos)               /*!< CAN_MO MOIPR: CFCVAL Mask               */\r
+\r
+/* --------------------------------  CAN_MO_MOAMR  -------------------------------- */\r
+#define CAN_MO_MOAMR_AM_Pos                   0                                                       /*!< CAN_MO MOAMR: AM Position               */\r
+#define CAN_MO_MOAMR_AM_Msk                   (0x1fffffffUL << CAN_MO_MOAMR_AM_Pos)                   /*!< CAN_MO MOAMR: AM Mask                   */\r
+#define CAN_MO_MOAMR_MIDE_Pos                 29                                                      /*!< CAN_MO MOAMR: MIDE Position             */\r
+#define CAN_MO_MOAMR_MIDE_Msk                 (0x01UL << CAN_MO_MOAMR_MIDE_Pos)                       /*!< CAN_MO MOAMR: MIDE Mask                 */\r
+\r
+/* -------------------------------  CAN_MO_MODATAL  ------------------------------- */\r
+#define CAN_MO_MODATAL_DB0_Pos                0                                                       /*!< CAN_MO MODATAL: DB0 Position            */\r
+#define CAN_MO_MODATAL_DB0_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB0_Pos)                /*!< CAN_MO MODATAL: DB0 Mask                */\r
+#define CAN_MO_MODATAL_DB1_Pos                8                                                       /*!< CAN_MO MODATAL: DB1 Position            */\r
+#define CAN_MO_MODATAL_DB1_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB1_Pos)                /*!< CAN_MO MODATAL: DB1 Mask                */\r
+#define CAN_MO_MODATAL_DB2_Pos                16                                                      /*!< CAN_MO MODATAL: DB2 Position            */\r
+#define CAN_MO_MODATAL_DB2_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB2_Pos)                /*!< CAN_MO MODATAL: DB2 Mask                */\r
+#define CAN_MO_MODATAL_DB3_Pos                24                                                      /*!< CAN_MO MODATAL: DB3 Position            */\r
+#define CAN_MO_MODATAL_DB3_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB3_Pos)                /*!< CAN_MO MODATAL: DB3 Mask                */\r
+\r
+/* -------------------------------  CAN_MO_MODATAH  ------------------------------- */\r
+#define CAN_MO_MODATAH_DB4_Pos                0                                                       /*!< CAN_MO MODATAH: DB4 Position            */\r
+#define CAN_MO_MODATAH_DB4_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB4_Pos)                /*!< CAN_MO MODATAH: DB4 Mask                */\r
+#define CAN_MO_MODATAH_DB5_Pos                8                                                       /*!< CAN_MO MODATAH: DB5 Position            */\r
+#define CAN_MO_MODATAH_DB5_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB5_Pos)                /*!< CAN_MO MODATAH: DB5 Mask                */\r
+#define CAN_MO_MODATAH_DB6_Pos                16                                                      /*!< CAN_MO MODATAH: DB6 Position            */\r
+#define CAN_MO_MODATAH_DB6_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB6_Pos)                /*!< CAN_MO MODATAH: DB6 Mask                */\r
+#define CAN_MO_MODATAH_DB7_Pos                24                                                      /*!< CAN_MO MODATAH: DB7 Position            */\r
+#define CAN_MO_MODATAH_DB7_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB7_Pos)                /*!< CAN_MO MODATAH: DB7 Mask                */\r
+\r
+/* ---------------------------------  CAN_MO_MOAR  -------------------------------- */\r
+#define CAN_MO_MOAR_ID_Pos                    0                                                       /*!< CAN_MO MOAR: ID Position                */\r
+#define CAN_MO_MOAR_ID_Msk                    (0x1fffffffUL << CAN_MO_MOAR_ID_Pos)                    /*!< CAN_MO MOAR: ID Mask                    */\r
+#define CAN_MO_MOAR_IDE_Pos                   29                                                      /*!< CAN_MO MOAR: IDE Position               */\r
+#define CAN_MO_MOAR_IDE_Msk                   (0x01UL << CAN_MO_MOAR_IDE_Pos)                         /*!< CAN_MO MOAR: IDE Mask                   */\r
+#define CAN_MO_MOAR_PRI_Pos                   30                                                      /*!< CAN_MO MOAR: PRI Position               */\r
+#define CAN_MO_MOAR_PRI_Msk                   (0x03UL << CAN_MO_MOAR_PRI_Pos)                         /*!< CAN_MO MOAR: PRI Mask                   */\r
+\r
+/* --------------------------------  CAN_MO_MOCTR  -------------------------------- */\r
+#define CAN_MO_MOCTR_RESRXPND_Pos             0                                                       /*!< CAN_MO MOCTR: RESRXPND Position         */\r
+#define CAN_MO_MOCTR_RESRXPND_Msk             (0x01UL << CAN_MO_MOCTR_RESRXPND_Pos)                   /*!< CAN_MO MOCTR: RESRXPND Mask             */\r
+#define CAN_MO_MOCTR_RESTXPND_Pos             1                                                       /*!< CAN_MO MOCTR: RESTXPND Position         */\r
+#define CAN_MO_MOCTR_RESTXPND_Msk             (0x01UL << CAN_MO_MOCTR_RESTXPND_Pos)                   /*!< CAN_MO MOCTR: RESTXPND Mask             */\r
+#define CAN_MO_MOCTR_RESRXUPD_Pos             2                                                       /*!< CAN_MO MOCTR: RESRXUPD Position         */\r
+#define CAN_MO_MOCTR_RESRXUPD_Msk             (0x01UL << CAN_MO_MOCTR_RESRXUPD_Pos)                   /*!< CAN_MO MOCTR: RESRXUPD Mask             */\r
+#define CAN_MO_MOCTR_RESNEWDAT_Pos            3                                                       /*!< CAN_MO MOCTR: RESNEWDAT Position        */\r
+#define CAN_MO_MOCTR_RESNEWDAT_Msk            (0x01UL << CAN_MO_MOCTR_RESNEWDAT_Pos)                  /*!< CAN_MO MOCTR: RESNEWDAT Mask            */\r
+#define CAN_MO_MOCTR_RESMSGLST_Pos            4                                                       /*!< CAN_MO MOCTR: RESMSGLST Position        */\r
+#define CAN_MO_MOCTR_RESMSGLST_Msk            (0x01UL << CAN_MO_MOCTR_RESMSGLST_Pos)                  /*!< CAN_MO MOCTR: RESMSGLST Mask            */\r
+#define CAN_MO_MOCTR_RESMSGVAL_Pos            5                                                       /*!< CAN_MO MOCTR: RESMSGVAL Position        */\r
+#define CAN_MO_MOCTR_RESMSGVAL_Msk            (0x01UL << CAN_MO_MOCTR_RESMSGVAL_Pos)                  /*!< CAN_MO MOCTR: RESMSGVAL Mask            */\r
+#define CAN_MO_MOCTR_RESRTSEL_Pos             6                                                       /*!< CAN_MO MOCTR: RESRTSEL Position         */\r
+#define CAN_MO_MOCTR_RESRTSEL_Msk             (0x01UL << CAN_MO_MOCTR_RESRTSEL_Pos)                   /*!< CAN_MO MOCTR: RESRTSEL Mask             */\r
+#define CAN_MO_MOCTR_RESRXEN_Pos              7                                                       /*!< CAN_MO MOCTR: RESRXEN Position          */\r
+#define CAN_MO_MOCTR_RESRXEN_Msk              (0x01UL << CAN_MO_MOCTR_RESRXEN_Pos)                    /*!< CAN_MO MOCTR: RESRXEN Mask              */\r
+#define CAN_MO_MOCTR_RESTXRQ_Pos              8                                                       /*!< CAN_MO MOCTR: RESTXRQ Position          */\r
+#define CAN_MO_MOCTR_RESTXRQ_Msk              (0x01UL << CAN_MO_MOCTR_RESTXRQ_Pos)                    /*!< CAN_MO MOCTR: RESTXRQ Mask              */\r
+#define CAN_MO_MOCTR_RESTXEN0_Pos             9                                                       /*!< CAN_MO MOCTR: RESTXEN0 Position         */\r
+#define CAN_MO_MOCTR_RESTXEN0_Msk             (0x01UL << CAN_MO_MOCTR_RESTXEN0_Pos)                   /*!< CAN_MO MOCTR: RESTXEN0 Mask             */\r
+#define CAN_MO_MOCTR_RESTXEN1_Pos             10                                                      /*!< CAN_MO MOCTR: RESTXEN1 Position         */\r
+#define CAN_MO_MOCTR_RESTXEN1_Msk             (0x01UL << CAN_MO_MOCTR_RESTXEN1_Pos)                   /*!< CAN_MO MOCTR: RESTXEN1 Mask             */\r
+#define CAN_MO_MOCTR_RESDIR_Pos               11                                                      /*!< CAN_MO MOCTR: RESDIR Position           */\r
+#define CAN_MO_MOCTR_RESDIR_Msk               (0x01UL << CAN_MO_MOCTR_RESDIR_Pos)                     /*!< CAN_MO MOCTR: RESDIR Mask               */\r
+#define CAN_MO_MOCTR_SETRXPND_Pos             16                                                      /*!< CAN_MO MOCTR: SETRXPND Position         */\r
+#define CAN_MO_MOCTR_SETRXPND_Msk             (0x01UL << CAN_MO_MOCTR_SETRXPND_Pos)                   /*!< CAN_MO MOCTR: SETRXPND Mask             */\r
+#define CAN_MO_MOCTR_SETTXPND_Pos             17                                                      /*!< CAN_MO MOCTR: SETTXPND Position         */\r
+#define CAN_MO_MOCTR_SETTXPND_Msk             (0x01UL << CAN_MO_MOCTR_SETTXPND_Pos)                   /*!< CAN_MO MOCTR: SETTXPND Mask             */\r
+#define CAN_MO_MOCTR_SETRXUPD_Pos             18                                                      /*!< CAN_MO MOCTR: SETRXUPD Position         */\r
+#define CAN_MO_MOCTR_SETRXUPD_Msk             (0x01UL << CAN_MO_MOCTR_SETRXUPD_Pos)                   /*!< CAN_MO MOCTR: SETRXUPD Mask             */\r
+#define CAN_MO_MOCTR_SETNEWDAT_Pos            19                                                      /*!< CAN_MO MOCTR: SETNEWDAT Position        */\r
+#define CAN_MO_MOCTR_SETNEWDAT_Msk            (0x01UL << CAN_MO_MOCTR_SETNEWDAT_Pos)                  /*!< CAN_MO MOCTR: SETNEWDAT Mask            */\r
+#define CAN_MO_MOCTR_SETMSGLST_Pos            20                                                      /*!< CAN_MO MOCTR: SETMSGLST Position        */\r
+#define CAN_MO_MOCTR_SETMSGLST_Msk            (0x01UL << CAN_MO_MOCTR_SETMSGLST_Pos)                  /*!< CAN_MO MOCTR: SETMSGLST Mask            */\r
+#define CAN_MO_MOCTR_SETMSGVAL_Pos            21                                                      /*!< CAN_MO MOCTR: SETMSGVAL Position        */\r
+#define CAN_MO_MOCTR_SETMSGVAL_Msk            (0x01UL << CAN_MO_MOCTR_SETMSGVAL_Pos)                  /*!< CAN_MO MOCTR: SETMSGVAL Mask            */\r
+#define CAN_MO_MOCTR_SETRTSEL_Pos             22                                                      /*!< CAN_MO MOCTR: SETRTSEL Position         */\r
+#define CAN_MO_MOCTR_SETRTSEL_Msk             (0x01UL << CAN_MO_MOCTR_SETRTSEL_Pos)                   /*!< CAN_MO MOCTR: SETRTSEL Mask             */\r
+#define CAN_MO_MOCTR_SETRXEN_Pos              23                                                      /*!< CAN_MO MOCTR: SETRXEN Position          */\r
+#define CAN_MO_MOCTR_SETRXEN_Msk              (0x01UL << CAN_MO_MOCTR_SETRXEN_Pos)                    /*!< CAN_MO MOCTR: SETRXEN Mask              */\r
+#define CAN_MO_MOCTR_SETTXRQ_Pos              24                                                      /*!< CAN_MO MOCTR: SETTXRQ Position          */\r
+#define CAN_MO_MOCTR_SETTXRQ_Msk              (0x01UL << CAN_MO_MOCTR_SETTXRQ_Pos)                    /*!< CAN_MO MOCTR: SETTXRQ Mask              */\r
+#define CAN_MO_MOCTR_SETTXEN0_Pos             25                                                      /*!< CAN_MO MOCTR: SETTXEN0 Position         */\r
+#define CAN_MO_MOCTR_SETTXEN0_Msk             (0x01UL << CAN_MO_MOCTR_SETTXEN0_Pos)                   /*!< CAN_MO MOCTR: SETTXEN0 Mask             */\r
+#define CAN_MO_MOCTR_SETTXEN1_Pos             26                                                      /*!< CAN_MO MOCTR: SETTXEN1 Position         */\r
+#define CAN_MO_MOCTR_SETTXEN1_Msk             (0x01UL << CAN_MO_MOCTR_SETTXEN1_Pos)                   /*!< CAN_MO MOCTR: SETTXEN1 Mask             */\r
+#define CAN_MO_MOCTR_SETDIR_Pos               27                                                      /*!< CAN_MO MOCTR: SETDIR Position           */\r
+#define CAN_MO_MOCTR_SETDIR_Msk               (0x01UL << CAN_MO_MOCTR_SETDIR_Pos)                     /*!< CAN_MO MOCTR: SETDIR Mask               */\r
+\r
+/* --------------------------------  CAN_MO_MOSTAT  ------------------------------- */\r
+#define CAN_MO_MOSTAT_RXPND_Pos               0                                                       /*!< CAN_MO MOSTAT: RXPND Position           */\r
+#define CAN_MO_MOSTAT_RXPND_Msk               (0x01UL << CAN_MO_MOSTAT_RXPND_Pos)                     /*!< CAN_MO MOSTAT: RXPND Mask               */\r
+#define CAN_MO_MOSTAT_TXPND_Pos               1                                                       /*!< CAN_MO MOSTAT: TXPND Position           */\r
+#define CAN_MO_MOSTAT_TXPND_Msk               (0x01UL << CAN_MO_MOSTAT_TXPND_Pos)                     /*!< CAN_MO MOSTAT: TXPND Mask               */\r
+#define CAN_MO_MOSTAT_RXUPD_Pos               2                                                       /*!< CAN_MO MOSTAT: RXUPD Position           */\r
+#define CAN_MO_MOSTAT_RXUPD_Msk               (0x01UL << CAN_MO_MOSTAT_RXUPD_Pos)                     /*!< CAN_MO MOSTAT: RXUPD Mask               */\r
+#define CAN_MO_MOSTAT_NEWDAT_Pos              3                                                       /*!< CAN_MO MOSTAT: NEWDAT Position          */\r
+#define CAN_MO_MOSTAT_NEWDAT_Msk              (0x01UL << CAN_MO_MOSTAT_NEWDAT_Pos)                    /*!< CAN_MO MOSTAT: NEWDAT Mask              */\r
+#define CAN_MO_MOSTAT_MSGLST_Pos              4                                                       /*!< CAN_MO MOSTAT: MSGLST Position          */\r
+#define CAN_MO_MOSTAT_MSGLST_Msk              (0x01UL << CAN_MO_MOSTAT_MSGLST_Pos)                    /*!< CAN_MO MOSTAT: MSGLST Mask              */\r
+#define CAN_MO_MOSTAT_MSGVAL_Pos              5                                                       /*!< CAN_MO MOSTAT: MSGVAL Position          */\r
+#define CAN_MO_MOSTAT_MSGVAL_Msk              (0x01UL << CAN_MO_MOSTAT_MSGVAL_Pos)                    /*!< CAN_MO MOSTAT: MSGVAL Mask              */\r
+#define CAN_MO_MOSTAT_RTSEL_Pos               6                                                       /*!< CAN_MO MOSTAT: RTSEL Position           */\r
+#define CAN_MO_MOSTAT_RTSEL_Msk               (0x01UL << CAN_MO_MOSTAT_RTSEL_Pos)                     /*!< CAN_MO MOSTAT: RTSEL Mask               */\r
+#define CAN_MO_MOSTAT_RXEN_Pos                7                                                       /*!< CAN_MO MOSTAT: RXEN Position            */\r
+#define CAN_MO_MOSTAT_RXEN_Msk                (0x01UL << CAN_MO_MOSTAT_RXEN_Pos)                      /*!< CAN_MO MOSTAT: RXEN Mask                */\r
+#define CAN_MO_MOSTAT_TXRQ_Pos                8                                                       /*!< CAN_MO MOSTAT: TXRQ Position            */\r
+#define CAN_MO_MOSTAT_TXRQ_Msk                (0x01UL << CAN_MO_MOSTAT_TXRQ_Pos)                      /*!< CAN_MO MOSTAT: TXRQ Mask                */\r
+#define CAN_MO_MOSTAT_TXEN0_Pos               9                                                       /*!< CAN_MO MOSTAT: TXEN0 Position           */\r
+#define CAN_MO_MOSTAT_TXEN0_Msk               (0x01UL << CAN_MO_MOSTAT_TXEN0_Pos)                     /*!< CAN_MO MOSTAT: TXEN0 Mask               */\r
+#define CAN_MO_MOSTAT_TXEN1_Pos               10                                                      /*!< CAN_MO MOSTAT: TXEN1 Position           */\r
+#define CAN_MO_MOSTAT_TXEN1_Msk               (0x01UL << CAN_MO_MOSTAT_TXEN1_Pos)                     /*!< CAN_MO MOSTAT: TXEN1 Mask               */\r
+#define CAN_MO_MOSTAT_DIR_Pos                 11                                                      /*!< CAN_MO MOSTAT: DIR Position             */\r
+#define CAN_MO_MOSTAT_DIR_Msk                 (0x01UL << CAN_MO_MOSTAT_DIR_Pos)                       /*!< CAN_MO MOSTAT: DIR Mask                 */\r
+#define CAN_MO_MOSTAT_LIST_Pos                12                                                      /*!< CAN_MO MOSTAT: LIST Position            */\r
+#define CAN_MO_MOSTAT_LIST_Msk                (0x0fUL << CAN_MO_MOSTAT_LIST_Pos)                      /*!< CAN_MO MOSTAT: LIST Mask                */\r
+#define CAN_MO_MOSTAT_PPREV_Pos               16                                                      /*!< CAN_MO MOSTAT: PPREV Position           */\r
+#define CAN_MO_MOSTAT_PPREV_Msk               (0x000000ffUL << CAN_MO_MOSTAT_PPREV_Pos)               /*!< CAN_MO MOSTAT: PPREV Mask               */\r
+#define CAN_MO_MOSTAT_PNEXT_Pos               24                                                      /*!< CAN_MO MOSTAT: PNEXT Position           */\r
+#define CAN_MO_MOSTAT_PNEXT_Msk               (0x000000ffUL << CAN_MO_MOSTAT_PNEXT_Pos)               /*!< CAN_MO MOSTAT: PNEXT Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'VADC' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  VADC_CLC  ---------------------------------- */\r
+#define VADC_CLC_DISR_Pos                     0                                                       /*!< VADC CLC: DISR Position                 */\r
+#define VADC_CLC_DISR_Msk                     (0x01UL << VADC_CLC_DISR_Pos)                           /*!< VADC CLC: DISR Mask                     */\r
+#define VADC_CLC_DISS_Pos                     1                                                       /*!< VADC CLC: DISS Position                 */\r
+#define VADC_CLC_DISS_Msk                     (0x01UL << VADC_CLC_DISS_Pos)                           /*!< VADC CLC: DISS Mask                     */\r
+#define VADC_CLC_EDIS_Pos                     3                                                       /*!< VADC CLC: EDIS Position                 */\r
+#define VADC_CLC_EDIS_Msk                     (0x01UL << VADC_CLC_EDIS_Pos)                           /*!< VADC CLC: EDIS Mask                     */\r
+\r
+/* -----------------------------------  VADC_ID  ---------------------------------- */\r
+#define VADC_ID_MOD_REV_Pos                   0                                                       /*!< VADC ID: MOD_REV Position               */\r
+#define VADC_ID_MOD_REV_Msk                   (0x000000ffUL << VADC_ID_MOD_REV_Pos)                   /*!< VADC ID: MOD_REV Mask                   */\r
+#define VADC_ID_MOD_TYPE_Pos                  8                                                       /*!< VADC ID: MOD_TYPE Position              */\r
+#define VADC_ID_MOD_TYPE_Msk                  (0x000000ffUL << VADC_ID_MOD_TYPE_Pos)                  /*!< VADC ID: MOD_TYPE Mask                  */\r
+#define VADC_ID_MOD_NUMBER_Pos                16                                                      /*!< VADC ID: MOD_NUMBER Position            */\r
+#define VADC_ID_MOD_NUMBER_Msk                (0x0000ffffUL << VADC_ID_MOD_NUMBER_Pos)                /*!< VADC ID: MOD_NUMBER Mask                */\r
+\r
+/* ----------------------------------  VADC_OCS  ---------------------------------- */\r
+#define VADC_OCS_TGS_Pos                      0                                                       /*!< VADC OCS: TGS Position                  */\r
+#define VADC_OCS_TGS_Msk                      (0x03UL << VADC_OCS_TGS_Pos)                            /*!< VADC OCS: TGS Mask                      */\r
+#define VADC_OCS_TGB_Pos                      2                                                       /*!< VADC OCS: TGB Position                  */\r
+#define VADC_OCS_TGB_Msk                      (0x01UL << VADC_OCS_TGB_Pos)                            /*!< VADC OCS: TGB Mask                      */\r
+#define VADC_OCS_TG_P_Pos                     3                                                       /*!< VADC OCS: TG_P Position                 */\r
+#define VADC_OCS_TG_P_Msk                     (0x01UL << VADC_OCS_TG_P_Pos)                           /*!< VADC OCS: TG_P Mask                     */\r
+#define VADC_OCS_SUS_Pos                      24                                                      /*!< VADC OCS: SUS Position                  */\r
+#define VADC_OCS_SUS_Msk                      (0x0fUL << VADC_OCS_SUS_Pos)                            /*!< VADC OCS: SUS Mask                      */\r
+#define VADC_OCS_SUS_P_Pos                    28                                                      /*!< VADC OCS: SUS_P Position                */\r
+#define VADC_OCS_SUS_P_Msk                    (0x01UL << VADC_OCS_SUS_P_Pos)                          /*!< VADC OCS: SUS_P Mask                    */\r
+#define VADC_OCS_SUSSTA_Pos                   29                                                      /*!< VADC OCS: SUSSTA Position               */\r
+#define VADC_OCS_SUSSTA_Msk                   (0x01UL << VADC_OCS_SUSSTA_Pos)                         /*!< VADC OCS: SUSSTA Mask                   */\r
+\r
+/* --------------------------------  VADC_GLOBCFG  -------------------------------- */\r
+#define VADC_GLOBCFG_DIVA_Pos                 0                                                       /*!< VADC GLOBCFG: DIVA Position             */\r
+#define VADC_GLOBCFG_DIVA_Msk                 (0x1fUL << VADC_GLOBCFG_DIVA_Pos)                       /*!< VADC GLOBCFG: DIVA Mask                 */\r
+#define VADC_GLOBCFG_DCMSB_Pos                7                                                       /*!< VADC GLOBCFG: DCMSB Position            */\r
+#define VADC_GLOBCFG_DCMSB_Msk                (0x01UL << VADC_GLOBCFG_DCMSB_Pos)                      /*!< VADC GLOBCFG: DCMSB Mask                */\r
+#define VADC_GLOBCFG_DIVD_Pos                 8                                                       /*!< VADC GLOBCFG: DIVD Position             */\r
+#define VADC_GLOBCFG_DIVD_Msk                 (0x03UL << VADC_GLOBCFG_DIVD_Pos)                       /*!< VADC GLOBCFG: DIVD Mask                 */\r
+#define VADC_GLOBCFG_DIVWC_Pos                15                                                      /*!< VADC GLOBCFG: DIVWC Position            */\r
+#define VADC_GLOBCFG_DIVWC_Msk                (0x01UL << VADC_GLOBCFG_DIVWC_Pos)                      /*!< VADC GLOBCFG: DIVWC Mask                */\r
+#define VADC_GLOBCFG_DPCAL0_Pos               16                                                      /*!< VADC GLOBCFG: DPCAL0 Position           */\r
+#define VADC_GLOBCFG_DPCAL0_Msk               (0x01UL << VADC_GLOBCFG_DPCAL0_Pos)                     /*!< VADC GLOBCFG: DPCAL0 Mask               */\r
+#define VADC_GLOBCFG_DPCAL1_Pos               17                                                      /*!< VADC GLOBCFG: DPCAL1 Position           */\r
+#define VADC_GLOBCFG_DPCAL1_Msk               (0x01UL << VADC_GLOBCFG_DPCAL1_Pos)                     /*!< VADC GLOBCFG: DPCAL1 Mask               */\r
+#define VADC_GLOBCFG_DPCAL2_Pos               18                                                      /*!< VADC GLOBCFG: DPCAL2 Position           */\r
+#define VADC_GLOBCFG_DPCAL2_Msk               (0x01UL << VADC_GLOBCFG_DPCAL2_Pos)                     /*!< VADC GLOBCFG: DPCAL2 Mask               */\r
+#define VADC_GLOBCFG_DPCAL3_Pos               19                                                      /*!< VADC GLOBCFG: DPCAL3 Position           */\r
+#define VADC_GLOBCFG_DPCAL3_Msk               (0x01UL << VADC_GLOBCFG_DPCAL3_Pos)                     /*!< VADC GLOBCFG: DPCAL3 Mask               */\r
+#define VADC_GLOBCFG_SUCAL_Pos                31                                                      /*!< VADC GLOBCFG: SUCAL Position            */\r
+#define VADC_GLOBCFG_SUCAL_Msk                (0x01UL << VADC_GLOBCFG_SUCAL_Pos)                      /*!< VADC GLOBCFG: SUCAL Mask                */\r
+\r
+/* -------------------------------  VADC_GLOBICLASS  ------------------------------ */\r
+#define VADC_GLOBICLASS_STCS_Pos              0                                                       /*!< VADC GLOBICLASS: STCS Position          */\r
+#define VADC_GLOBICLASS_STCS_Msk              (0x1fUL << VADC_GLOBICLASS_STCS_Pos)                    /*!< VADC GLOBICLASS: STCS Mask              */\r
+#define VADC_GLOBICLASS_CMS_Pos               8                                                       /*!< VADC GLOBICLASS: CMS Position           */\r
+#define VADC_GLOBICLASS_CMS_Msk               (0x07UL << VADC_GLOBICLASS_CMS_Pos)                     /*!< VADC GLOBICLASS: CMS Mask               */\r
+#define VADC_GLOBICLASS_STCE_Pos              16                                                      /*!< VADC GLOBICLASS: STCE Position          */\r
+#define VADC_GLOBICLASS_STCE_Msk              (0x1fUL << VADC_GLOBICLASS_STCE_Pos)                    /*!< VADC GLOBICLASS: STCE Mask              */\r
+#define VADC_GLOBICLASS_CME_Pos               24                                                      /*!< VADC GLOBICLASS: CME Position           */\r
+#define VADC_GLOBICLASS_CME_Msk               (0x07UL << VADC_GLOBICLASS_CME_Pos)                     /*!< VADC GLOBICLASS: CME Mask               */\r
+\r
+/* -------------------------------  VADC_GLOBBOUND  ------------------------------- */\r
+#define VADC_GLOBBOUND_BOUNDARY0_Pos          0                                                       /*!< VADC GLOBBOUND: BOUNDARY0 Position      */\r
+#define VADC_GLOBBOUND_BOUNDARY0_Msk          (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY0_Pos)          /*!< VADC GLOBBOUND: BOUNDARY0 Mask          */\r
+#define VADC_GLOBBOUND_BOUNDARY1_Pos          16                                                      /*!< VADC GLOBBOUND: BOUNDARY1 Position      */\r
+#define VADC_GLOBBOUND_BOUNDARY1_Msk          (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY1_Pos)          /*!< VADC GLOBBOUND: BOUNDARY1 Mask          */\r
+\r
+/* -------------------------------  VADC_GLOBEFLAG  ------------------------------- */\r
+#define VADC_GLOBEFLAG_SEVGLB_Pos             0                                                       /*!< VADC GLOBEFLAG: SEVGLB Position         */\r
+#define VADC_GLOBEFLAG_SEVGLB_Msk             (0x01UL << VADC_GLOBEFLAG_SEVGLB_Pos)                   /*!< VADC GLOBEFLAG: SEVGLB Mask             */\r
+#define VADC_GLOBEFLAG_REVGLB_Pos             8                                                       /*!< VADC GLOBEFLAG: REVGLB Position         */\r
+#define VADC_GLOBEFLAG_REVGLB_Msk             (0x01UL << VADC_GLOBEFLAG_REVGLB_Pos)                   /*!< VADC GLOBEFLAG: REVGLB Mask             */\r
+#define VADC_GLOBEFLAG_SEVGLBCLR_Pos          16                                                      /*!< VADC GLOBEFLAG: SEVGLBCLR Position      */\r
+#define VADC_GLOBEFLAG_SEVGLBCLR_Msk          (0x01UL << VADC_GLOBEFLAG_SEVGLBCLR_Pos)                /*!< VADC GLOBEFLAG: SEVGLBCLR Mask          */\r
+#define VADC_GLOBEFLAG_REVGLBCLR_Pos          24                                                      /*!< VADC GLOBEFLAG: REVGLBCLR Position      */\r
+#define VADC_GLOBEFLAG_REVGLBCLR_Msk          (0x01UL << VADC_GLOBEFLAG_REVGLBCLR_Pos)                /*!< VADC GLOBEFLAG: REVGLBCLR Mask          */\r
+\r
+/* --------------------------------  VADC_GLOBEVNP  ------------------------------- */\r
+#define VADC_GLOBEVNP_SEV0NP_Pos              0                                                       /*!< VADC GLOBEVNP: SEV0NP Position          */\r
+#define VADC_GLOBEVNP_SEV0NP_Msk              (0x0fUL << VADC_GLOBEVNP_SEV0NP_Pos)                    /*!< VADC GLOBEVNP: SEV0NP Mask              */\r
+#define VADC_GLOBEVNP_REV0NP_Pos              16                                                      /*!< VADC GLOBEVNP: REV0NP Position          */\r
+#define VADC_GLOBEVNP_REV0NP_Msk              (0x0fUL << VADC_GLOBEVNP_REV0NP_Pos)                    /*!< VADC GLOBEVNP: REV0NP Mask              */\r
+\r
+/* ---------------------------------  VADC_GLOBTF  -------------------------------- */\r
+#define VADC_GLOBTF_CDGR_Pos                  4                                                       /*!< VADC GLOBTF: CDGR Position              */\r
+#define VADC_GLOBTF_CDGR_Msk                  (0x0fUL << VADC_GLOBTF_CDGR_Pos)                        /*!< VADC GLOBTF: CDGR Mask                  */\r
+#define VADC_GLOBTF_CDEN_Pos                  8                                                       /*!< VADC GLOBTF: CDEN Position              */\r
+#define VADC_GLOBTF_CDEN_Msk                  (0x01UL << VADC_GLOBTF_CDEN_Pos)                        /*!< VADC GLOBTF: CDEN Mask                  */\r
+#define VADC_GLOBTF_CDSEL_Pos                 9                                                       /*!< VADC GLOBTF: CDSEL Position             */\r
+#define VADC_GLOBTF_CDSEL_Msk                 (0x03UL << VADC_GLOBTF_CDSEL_Pos)                       /*!< VADC GLOBTF: CDSEL Mask                 */\r
+#define VADC_GLOBTF_CDWC_Pos                  15                                                      /*!< VADC GLOBTF: CDWC Position              */\r
+#define VADC_GLOBTF_CDWC_Msk                  (0x01UL << VADC_GLOBTF_CDWC_Pos)                        /*!< VADC GLOBTF: CDWC Mask                  */\r
+#define VADC_GLOBTF_PDD_Pos                   16                                                      /*!< VADC GLOBTF: PDD Position               */\r
+#define VADC_GLOBTF_PDD_Msk                   (0x01UL << VADC_GLOBTF_PDD_Pos)                         /*!< VADC GLOBTF: PDD Mask                   */\r
+#define VADC_GLOBTF_MDWC_Pos                  23                                                      /*!< VADC GLOBTF: MDWC Position              */\r
+#define VADC_GLOBTF_MDWC_Msk                  (0x01UL << VADC_GLOBTF_MDWC_Pos)                        /*!< VADC GLOBTF: MDWC Mask                  */\r
+\r
+/* ---------------------------------  VADC_BRSSEL  -------------------------------- */\r
+#define VADC_BRSSEL_CHSELG0_Pos               0                                                       /*!< VADC BRSSEL: CHSELG0 Position           */\r
+#define VADC_BRSSEL_CHSELG0_Msk               (0x01UL << VADC_BRSSEL_CHSELG0_Pos)                     /*!< VADC BRSSEL: CHSELG0 Mask               */\r
+#define VADC_BRSSEL_CHSELG1_Pos               1                                                       /*!< VADC BRSSEL: CHSELG1 Position           */\r
+#define VADC_BRSSEL_CHSELG1_Msk               (0x01UL << VADC_BRSSEL_CHSELG1_Pos)                     /*!< VADC BRSSEL: CHSELG1 Mask               */\r
+#define VADC_BRSSEL_CHSELG2_Pos               2                                                       /*!< VADC BRSSEL: CHSELG2 Position           */\r
+#define VADC_BRSSEL_CHSELG2_Msk               (0x01UL << VADC_BRSSEL_CHSELG2_Pos)                     /*!< VADC BRSSEL: CHSELG2 Mask               */\r
+#define VADC_BRSSEL_CHSELG3_Pos               3                                                       /*!< VADC BRSSEL: CHSELG3 Position           */\r
+#define VADC_BRSSEL_CHSELG3_Msk               (0x01UL << VADC_BRSSEL_CHSELG3_Pos)                     /*!< VADC BRSSEL: CHSELG3 Mask               */\r
+#define VADC_BRSSEL_CHSELG4_Pos               4                                                       /*!< VADC BRSSEL: CHSELG4 Position           */\r
+#define VADC_BRSSEL_CHSELG4_Msk               (0x01UL << VADC_BRSSEL_CHSELG4_Pos)                     /*!< VADC BRSSEL: CHSELG4 Mask               */\r
+#define VADC_BRSSEL_CHSELG5_Pos               5                                                       /*!< VADC BRSSEL: CHSELG5 Position           */\r
+#define VADC_BRSSEL_CHSELG5_Msk               (0x01UL << VADC_BRSSEL_CHSELG5_Pos)                     /*!< VADC BRSSEL: CHSELG5 Mask               */\r
+#define VADC_BRSSEL_CHSELG6_Pos               6                                                       /*!< VADC BRSSEL: CHSELG6 Position           */\r
+#define VADC_BRSSEL_CHSELG6_Msk               (0x01UL << VADC_BRSSEL_CHSELG6_Pos)                     /*!< VADC BRSSEL: CHSELG6 Mask               */\r
+#define VADC_BRSSEL_CHSELG7_Pos               7                                                       /*!< VADC BRSSEL: CHSELG7 Position           */\r
+#define VADC_BRSSEL_CHSELG7_Msk               (0x01UL << VADC_BRSSEL_CHSELG7_Pos)                     /*!< VADC BRSSEL: CHSELG7 Mask               */\r
+\r
+/* ---------------------------------  VADC_BRSPND  -------------------------------- */\r
+#define VADC_BRSPND_CHPNDG0_Pos               0                                                       /*!< VADC BRSPND: CHPNDG0 Position           */\r
+#define VADC_BRSPND_CHPNDG0_Msk               (0x01UL << VADC_BRSPND_CHPNDG0_Pos)                     /*!< VADC BRSPND: CHPNDG0 Mask               */\r
+#define VADC_BRSPND_CHPNDG1_Pos               1                                                       /*!< VADC BRSPND: CHPNDG1 Position           */\r
+#define VADC_BRSPND_CHPNDG1_Msk               (0x01UL << VADC_BRSPND_CHPNDG1_Pos)                     /*!< VADC BRSPND: CHPNDG1 Mask               */\r
+#define VADC_BRSPND_CHPNDG2_Pos               2                                                       /*!< VADC BRSPND: CHPNDG2 Position           */\r
+#define VADC_BRSPND_CHPNDG2_Msk               (0x01UL << VADC_BRSPND_CHPNDG2_Pos)                     /*!< VADC BRSPND: CHPNDG2 Mask               */\r
+#define VADC_BRSPND_CHPNDG3_Pos               3                                                       /*!< VADC BRSPND: CHPNDG3 Position           */\r
+#define VADC_BRSPND_CHPNDG3_Msk               (0x01UL << VADC_BRSPND_CHPNDG3_Pos)                     /*!< VADC BRSPND: CHPNDG3 Mask               */\r
+#define VADC_BRSPND_CHPNDG4_Pos               4                                                       /*!< VADC BRSPND: CHPNDG4 Position           */\r
+#define VADC_BRSPND_CHPNDG4_Msk               (0x01UL << VADC_BRSPND_CHPNDG4_Pos)                     /*!< VADC BRSPND: CHPNDG4 Mask               */\r
+#define VADC_BRSPND_CHPNDG5_Pos               5                                                       /*!< VADC BRSPND: CHPNDG5 Position           */\r
+#define VADC_BRSPND_CHPNDG5_Msk               (0x01UL << VADC_BRSPND_CHPNDG5_Pos)                     /*!< VADC BRSPND: CHPNDG5 Mask               */\r
+#define VADC_BRSPND_CHPNDG6_Pos               6                                                       /*!< VADC BRSPND: CHPNDG6 Position           */\r
+#define VADC_BRSPND_CHPNDG6_Msk               (0x01UL << VADC_BRSPND_CHPNDG6_Pos)                     /*!< VADC BRSPND: CHPNDG6 Mask               */\r
+#define VADC_BRSPND_CHPNDG7_Pos               7                                                       /*!< VADC BRSPND: CHPNDG7 Position           */\r
+#define VADC_BRSPND_CHPNDG7_Msk               (0x01UL << VADC_BRSPND_CHPNDG7_Pos)                     /*!< VADC BRSPND: CHPNDG7 Mask               */\r
+\r
+/* --------------------------------  VADC_BRSCTRL  -------------------------------- */\r
+#define VADC_BRSCTRL_XTSEL_Pos                8                                                       /*!< VADC BRSCTRL: XTSEL Position            */\r
+#define VADC_BRSCTRL_XTSEL_Msk                (0x0fUL << VADC_BRSCTRL_XTSEL_Pos)                      /*!< VADC BRSCTRL: XTSEL Mask                */\r
+#define VADC_BRSCTRL_XTLVL_Pos                12                                                      /*!< VADC BRSCTRL: XTLVL Position            */\r
+#define VADC_BRSCTRL_XTLVL_Msk                (0x01UL << VADC_BRSCTRL_XTLVL_Pos)                      /*!< VADC BRSCTRL: XTLVL Mask                */\r
+#define VADC_BRSCTRL_XTMODE_Pos               13                                                      /*!< VADC BRSCTRL: XTMODE Position           */\r
+#define VADC_BRSCTRL_XTMODE_Msk               (0x03UL << VADC_BRSCTRL_XTMODE_Pos)                     /*!< VADC BRSCTRL: XTMODE Mask               */\r
+#define VADC_BRSCTRL_XTWC_Pos                 15                                                      /*!< VADC BRSCTRL: XTWC Position             */\r
+#define VADC_BRSCTRL_XTWC_Msk                 (0x01UL << VADC_BRSCTRL_XTWC_Pos)                       /*!< VADC BRSCTRL: XTWC Mask                 */\r
+#define VADC_BRSCTRL_GTSEL_Pos                16                                                      /*!< VADC BRSCTRL: GTSEL Position            */\r
+#define VADC_BRSCTRL_GTSEL_Msk                (0x0fUL << VADC_BRSCTRL_GTSEL_Pos)                      /*!< VADC BRSCTRL: GTSEL Mask                */\r
+#define VADC_BRSCTRL_GTLVL_Pos                20                                                      /*!< VADC BRSCTRL: GTLVL Position            */\r
+#define VADC_BRSCTRL_GTLVL_Msk                (0x01UL << VADC_BRSCTRL_GTLVL_Pos)                      /*!< VADC BRSCTRL: GTLVL Mask                */\r
+#define VADC_BRSCTRL_GTWC_Pos                 23                                                      /*!< VADC BRSCTRL: GTWC Position             */\r
+#define VADC_BRSCTRL_GTWC_Msk                 (0x01UL << VADC_BRSCTRL_GTWC_Pos)                       /*!< VADC BRSCTRL: GTWC Mask                 */\r
+\r
+/* ---------------------------------  VADC_BRSMR  --------------------------------- */\r
+#define VADC_BRSMR_ENGT_Pos                   0                                                       /*!< VADC BRSMR: ENGT Position               */\r
+#define VADC_BRSMR_ENGT_Msk                   (0x03UL << VADC_BRSMR_ENGT_Pos)                         /*!< VADC BRSMR: ENGT Mask                   */\r
+#define VADC_BRSMR_ENTR_Pos                   2                                                       /*!< VADC BRSMR: ENTR Position               */\r
+#define VADC_BRSMR_ENTR_Msk                   (0x01UL << VADC_BRSMR_ENTR_Pos)                         /*!< VADC BRSMR: ENTR Mask                   */\r
+#define VADC_BRSMR_ENSI_Pos                   3                                                       /*!< VADC BRSMR: ENSI Position               */\r
+#define VADC_BRSMR_ENSI_Msk                   (0x01UL << VADC_BRSMR_ENSI_Pos)                         /*!< VADC BRSMR: ENSI Mask                   */\r
+#define VADC_BRSMR_SCAN_Pos                   4                                                       /*!< VADC BRSMR: SCAN Position               */\r
+#define VADC_BRSMR_SCAN_Msk                   (0x01UL << VADC_BRSMR_SCAN_Pos)                         /*!< VADC BRSMR: SCAN Mask                   */\r
+#define VADC_BRSMR_LDM_Pos                    5                                                       /*!< VADC BRSMR: LDM Position                */\r
+#define VADC_BRSMR_LDM_Msk                    (0x01UL << VADC_BRSMR_LDM_Pos)                          /*!< VADC BRSMR: LDM Mask                    */\r
+#define VADC_BRSMR_REQGT_Pos                  7                                                       /*!< VADC BRSMR: REQGT Position              */\r
+#define VADC_BRSMR_REQGT_Msk                  (0x01UL << VADC_BRSMR_REQGT_Pos)                        /*!< VADC BRSMR: REQGT Mask                  */\r
+#define VADC_BRSMR_CLRPND_Pos                 8                                                       /*!< VADC BRSMR: CLRPND Position             */\r
+#define VADC_BRSMR_CLRPND_Msk                 (0x01UL << VADC_BRSMR_CLRPND_Pos)                       /*!< VADC BRSMR: CLRPND Mask                 */\r
+#define VADC_BRSMR_LDEV_Pos                   9                                                       /*!< VADC BRSMR: LDEV Position               */\r
+#define VADC_BRSMR_LDEV_Msk                   (0x01UL << VADC_BRSMR_LDEV_Pos)                         /*!< VADC BRSMR: LDEV Mask                   */\r
+#define VADC_BRSMR_RPTDIS_Pos                 16                                                      /*!< VADC BRSMR: RPTDIS Position             */\r
+#define VADC_BRSMR_RPTDIS_Msk                 (0x01UL << VADC_BRSMR_RPTDIS_Pos)                       /*!< VADC BRSMR: RPTDIS Mask                 */\r
+\r
+/* --------------------------------  VADC_GLOBRCR  -------------------------------- */\r
+#define VADC_GLOBRCR_DRCTR_Pos                16                                                      /*!< VADC GLOBRCR: DRCTR Position            */\r
+#define VADC_GLOBRCR_DRCTR_Msk                (0x0fUL << VADC_GLOBRCR_DRCTR_Pos)                      /*!< VADC GLOBRCR: DRCTR Mask                */\r
+#define VADC_GLOBRCR_WFR_Pos                  24                                                      /*!< VADC GLOBRCR: WFR Position              */\r
+#define VADC_GLOBRCR_WFR_Msk                  (0x01UL << VADC_GLOBRCR_WFR_Pos)                        /*!< VADC GLOBRCR: WFR Mask                  */\r
+#define VADC_GLOBRCR_SRGEN_Pos                31                                                      /*!< VADC GLOBRCR: SRGEN Position            */\r
+#define VADC_GLOBRCR_SRGEN_Msk                (0x01UL << VADC_GLOBRCR_SRGEN_Pos)                      /*!< VADC GLOBRCR: SRGEN Mask                */\r
+\r
+/* --------------------------------  VADC_GLOBRES  -------------------------------- */\r
+#define VADC_GLOBRES_RESULT_Pos               0                                                       /*!< VADC GLOBRES: RESULT Position           */\r
+#define VADC_GLOBRES_RESULT_Msk               (0x0000ffffUL << VADC_GLOBRES_RESULT_Pos)               /*!< VADC GLOBRES: RESULT Mask               */\r
+#define VADC_GLOBRES_GNR_Pos                  16                                                      /*!< VADC GLOBRES: GNR Position              */\r
+#define VADC_GLOBRES_GNR_Msk                  (0x0fUL << VADC_GLOBRES_GNR_Pos)                        /*!< VADC GLOBRES: GNR Mask                  */\r
+#define VADC_GLOBRES_CHNR_Pos                 20                                                      /*!< VADC GLOBRES: CHNR Position             */\r
+#define VADC_GLOBRES_CHNR_Msk                 (0x1fUL << VADC_GLOBRES_CHNR_Pos)                       /*!< VADC GLOBRES: CHNR Mask                 */\r
+#define VADC_GLOBRES_EMUX_Pos                 25                                                      /*!< VADC GLOBRES: EMUX Position             */\r
+#define VADC_GLOBRES_EMUX_Msk                 (0x07UL << VADC_GLOBRES_EMUX_Pos)                       /*!< VADC GLOBRES: EMUX Mask                 */\r
+#define VADC_GLOBRES_CRS_Pos                  28                                                      /*!< VADC GLOBRES: CRS Position              */\r
+#define VADC_GLOBRES_CRS_Msk                  (0x03UL << VADC_GLOBRES_CRS_Pos)                        /*!< VADC GLOBRES: CRS Mask                  */\r
+#define VADC_GLOBRES_FCR_Pos                  30                                                      /*!< VADC GLOBRES: FCR Position              */\r
+#define VADC_GLOBRES_FCR_Msk                  (0x01UL << VADC_GLOBRES_FCR_Pos)                        /*!< VADC GLOBRES: FCR Mask                  */\r
+#define VADC_GLOBRES_VF_Pos                   31                                                      /*!< VADC GLOBRES: VF Position               */\r
+#define VADC_GLOBRES_VF_Msk                   (0x01UL << VADC_GLOBRES_VF_Pos)                         /*!< VADC GLOBRES: VF Mask                   */\r
+\r
+/* --------------------------------  VADC_GLOBRESD  ------------------------------- */\r
+#define VADC_GLOBRESD_RESULT_Pos              0                                                       /*!< VADC GLOBRESD: RESULT Position          */\r
+#define VADC_GLOBRESD_RESULT_Msk              (0x0000ffffUL << VADC_GLOBRESD_RESULT_Pos)              /*!< VADC GLOBRESD: RESULT Mask              */\r
+#define VADC_GLOBRESD_GNR_Pos                 16                                                      /*!< VADC GLOBRESD: GNR Position             */\r
+#define VADC_GLOBRESD_GNR_Msk                 (0x0fUL << VADC_GLOBRESD_GNR_Pos)                       /*!< VADC GLOBRESD: GNR Mask                 */\r
+#define VADC_GLOBRESD_CHNR_Pos                20                                                      /*!< VADC GLOBRESD: CHNR Position            */\r
+#define VADC_GLOBRESD_CHNR_Msk                (0x1fUL << VADC_GLOBRESD_CHNR_Pos)                      /*!< VADC GLOBRESD: CHNR Mask                */\r
+#define VADC_GLOBRESD_EMUX_Pos                25                                                      /*!< VADC GLOBRESD: EMUX Position            */\r
+#define VADC_GLOBRESD_EMUX_Msk                (0x07UL << VADC_GLOBRESD_EMUX_Pos)                      /*!< VADC GLOBRESD: EMUX Mask                */\r
+#define VADC_GLOBRESD_CRS_Pos                 28                                                      /*!< VADC GLOBRESD: CRS Position             */\r
+#define VADC_GLOBRESD_CRS_Msk                 (0x03UL << VADC_GLOBRESD_CRS_Pos)                       /*!< VADC GLOBRESD: CRS Mask                 */\r
+#define VADC_GLOBRESD_FCR_Pos                 30                                                      /*!< VADC GLOBRESD: FCR Position             */\r
+#define VADC_GLOBRESD_FCR_Msk                 (0x01UL << VADC_GLOBRESD_FCR_Pos)                       /*!< VADC GLOBRESD: FCR Mask                 */\r
+#define VADC_GLOBRESD_VF_Pos                  31                                                      /*!< VADC GLOBRESD: VF Position              */\r
+#define VADC_GLOBRESD_VF_Msk                  (0x01UL << VADC_GLOBRESD_VF_Pos)                        /*!< VADC GLOBRESD: VF Mask                  */\r
+\r
+/* --------------------------------  VADC_EMUXSEL  -------------------------------- */\r
+#define VADC_EMUXSEL_EMUXGRP0_Pos             0                                                       /*!< VADC EMUXSEL: EMUXGRP0 Position         */\r
+#define VADC_EMUXSEL_EMUXGRP0_Msk             (0x0fUL << VADC_EMUXSEL_EMUXGRP0_Pos)                   /*!< VADC EMUXSEL: EMUXGRP0 Mask             */\r
+#define VADC_EMUXSEL_EMUXGRP1_Pos             4                                                       /*!< VADC EMUXSEL: EMUXGRP1 Position         */\r
+#define VADC_EMUXSEL_EMUXGRP1_Msk             (0x0fUL << VADC_EMUXSEL_EMUXGRP1_Pos)                   /*!< VADC EMUXSEL: EMUXGRP1 Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'VADC_G' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  VADC_G_ARBCFG  ------------------------------- */\r
+#define VADC_G_ARBCFG_ANONC_Pos               0                                                       /*!< VADC_G ARBCFG: ANONC Position           */\r
+#define VADC_G_ARBCFG_ANONC_Msk               (0x03UL << VADC_G_ARBCFG_ANONC_Pos)                     /*!< VADC_G ARBCFG: ANONC Mask               */\r
+#define VADC_G_ARBCFG_ARBRND_Pos              4                                                       /*!< VADC_G ARBCFG: ARBRND Position          */\r
+#define VADC_G_ARBCFG_ARBRND_Msk              (0x03UL << VADC_G_ARBCFG_ARBRND_Pos)                    /*!< VADC_G ARBCFG: ARBRND Mask              */\r
+#define VADC_G_ARBCFG_ARBM_Pos                7                                                       /*!< VADC_G ARBCFG: ARBM Position            */\r
+#define VADC_G_ARBCFG_ARBM_Msk                (0x01UL << VADC_G_ARBCFG_ARBM_Pos)                      /*!< VADC_G ARBCFG: ARBM Mask                */\r
+#define VADC_G_ARBCFG_ANONS_Pos               16                                                      /*!< VADC_G ARBCFG: ANONS Position           */\r
+#define VADC_G_ARBCFG_ANONS_Msk               (0x03UL << VADC_G_ARBCFG_ANONS_Pos)                     /*!< VADC_G ARBCFG: ANONS Mask               */\r
+#define VADC_G_ARBCFG_CAL_Pos                 28                                                      /*!< VADC_G ARBCFG: CAL Position             */\r
+#define VADC_G_ARBCFG_CAL_Msk                 (0x01UL << VADC_G_ARBCFG_CAL_Pos)                       /*!< VADC_G ARBCFG: CAL Mask                 */\r
+#define VADC_G_ARBCFG_BUSY_Pos                30                                                      /*!< VADC_G ARBCFG: BUSY Position            */\r
+#define VADC_G_ARBCFG_BUSY_Msk                (0x01UL << VADC_G_ARBCFG_BUSY_Pos)                      /*!< VADC_G ARBCFG: BUSY Mask                */\r
+#define VADC_G_ARBCFG_SAMPLE_Pos              31                                                      /*!< VADC_G ARBCFG: SAMPLE Position          */\r
+#define VADC_G_ARBCFG_SAMPLE_Msk              (0x01UL << VADC_G_ARBCFG_SAMPLE_Pos)                    /*!< VADC_G ARBCFG: SAMPLE Mask              */\r
+\r
+/* --------------------------------  VADC_G_ARBPR  -------------------------------- */\r
+#define VADC_G_ARBPR_PRIO0_Pos                0                                                       /*!< VADC_G ARBPR: PRIO0 Position            */\r
+#define VADC_G_ARBPR_PRIO0_Msk                (0x03UL << VADC_G_ARBPR_PRIO0_Pos)                      /*!< VADC_G ARBPR: PRIO0 Mask                */\r
+#define VADC_G_ARBPR_CSM0_Pos                 3                                                       /*!< VADC_G ARBPR: CSM0 Position             */\r
+#define VADC_G_ARBPR_CSM0_Msk                 (0x01UL << VADC_G_ARBPR_CSM0_Pos)                       /*!< VADC_G ARBPR: CSM0 Mask                 */\r
+#define VADC_G_ARBPR_PRIO1_Pos                4                                                       /*!< VADC_G ARBPR: PRIO1 Position            */\r
+#define VADC_G_ARBPR_PRIO1_Msk                (0x03UL << VADC_G_ARBPR_PRIO1_Pos)                      /*!< VADC_G ARBPR: PRIO1 Mask                */\r
+#define VADC_G_ARBPR_CSM1_Pos                 7                                                       /*!< VADC_G ARBPR: CSM1 Position             */\r
+#define VADC_G_ARBPR_CSM1_Msk                 (0x01UL << VADC_G_ARBPR_CSM1_Pos)                       /*!< VADC_G ARBPR: CSM1 Mask                 */\r
+#define VADC_G_ARBPR_PRIO2_Pos                8                                                       /*!< VADC_G ARBPR: PRIO2 Position            */\r
+#define VADC_G_ARBPR_PRIO2_Msk                (0x03UL << VADC_G_ARBPR_PRIO2_Pos)                      /*!< VADC_G ARBPR: PRIO2 Mask                */\r
+#define VADC_G_ARBPR_CSM2_Pos                 11                                                      /*!< VADC_G ARBPR: CSM2 Position             */\r
+#define VADC_G_ARBPR_CSM2_Msk                 (0x01UL << VADC_G_ARBPR_CSM2_Pos)                       /*!< VADC_G ARBPR: CSM2 Mask                 */\r
+#define VADC_G_ARBPR_ASEN0_Pos                24                                                      /*!< VADC_G ARBPR: ASEN0 Position            */\r
+#define VADC_G_ARBPR_ASEN0_Msk                (0x01UL << VADC_G_ARBPR_ASEN0_Pos)                      /*!< VADC_G ARBPR: ASEN0 Mask                */\r
+#define VADC_G_ARBPR_ASEN1_Pos                25                                                      /*!< VADC_G ARBPR: ASEN1 Position            */\r
+#define VADC_G_ARBPR_ASEN1_Msk                (0x01UL << VADC_G_ARBPR_ASEN1_Pos)                      /*!< VADC_G ARBPR: ASEN1 Mask                */\r
+#define VADC_G_ARBPR_ASEN2_Pos                26                                                      /*!< VADC_G ARBPR: ASEN2 Position            */\r
+#define VADC_G_ARBPR_ASEN2_Msk                (0x01UL << VADC_G_ARBPR_ASEN2_Pos)                      /*!< VADC_G ARBPR: ASEN2 Mask                */\r
+\r
+/* --------------------------------  VADC_G_CHASS  -------------------------------- */\r
+#define VADC_G_CHASS_ASSCH0_Pos               0                                                       /*!< VADC_G CHASS: ASSCH0 Position           */\r
+#define VADC_G_CHASS_ASSCH0_Msk               (0x01UL << VADC_G_CHASS_ASSCH0_Pos)                     /*!< VADC_G CHASS: ASSCH0 Mask               */\r
+#define VADC_G_CHASS_ASSCH1_Pos               1                                                       /*!< VADC_G CHASS: ASSCH1 Position           */\r
+#define VADC_G_CHASS_ASSCH1_Msk               (0x01UL << VADC_G_CHASS_ASSCH1_Pos)                     /*!< VADC_G CHASS: ASSCH1 Mask               */\r
+#define VADC_G_CHASS_ASSCH2_Pos               2                                                       /*!< VADC_G CHASS: ASSCH2 Position           */\r
+#define VADC_G_CHASS_ASSCH2_Msk               (0x01UL << VADC_G_CHASS_ASSCH2_Pos)                     /*!< VADC_G CHASS: ASSCH2 Mask               */\r
+#define VADC_G_CHASS_ASSCH3_Pos               3                                                       /*!< VADC_G CHASS: ASSCH3 Position           */\r
+#define VADC_G_CHASS_ASSCH3_Msk               (0x01UL << VADC_G_CHASS_ASSCH3_Pos)                     /*!< VADC_G CHASS: ASSCH3 Mask               */\r
+#define VADC_G_CHASS_ASSCH4_Pos               4                                                       /*!< VADC_G CHASS: ASSCH4 Position           */\r
+#define VADC_G_CHASS_ASSCH4_Msk               (0x01UL << VADC_G_CHASS_ASSCH4_Pos)                     /*!< VADC_G CHASS: ASSCH4 Mask               */\r
+#define VADC_G_CHASS_ASSCH5_Pos               5                                                       /*!< VADC_G CHASS: ASSCH5 Position           */\r
+#define VADC_G_CHASS_ASSCH5_Msk               (0x01UL << VADC_G_CHASS_ASSCH5_Pos)                     /*!< VADC_G CHASS: ASSCH5 Mask               */\r
+#define VADC_G_CHASS_ASSCH6_Pos               6                                                       /*!< VADC_G CHASS: ASSCH6 Position           */\r
+#define VADC_G_CHASS_ASSCH6_Msk               (0x01UL << VADC_G_CHASS_ASSCH6_Pos)                     /*!< VADC_G CHASS: ASSCH6 Mask               */\r
+#define VADC_G_CHASS_ASSCH7_Pos               7                                                       /*!< VADC_G CHASS: ASSCH7 Position           */\r
+#define VADC_G_CHASS_ASSCH7_Msk               (0x01UL << VADC_G_CHASS_ASSCH7_Pos)                     /*!< VADC_G CHASS: ASSCH7 Mask               */\r
+\r
+/* --------------------------------  VADC_G_ICLASS  ------------------------------- */\r
+#define VADC_G_ICLASS_STCS_Pos                0                                                       /*!< VADC_G ICLASS: STCS Position            */\r
+#define VADC_G_ICLASS_STCS_Msk                (0x1fUL << VADC_G_ICLASS_STCS_Pos)                      /*!< VADC_G ICLASS: STCS Mask                */\r
+#define VADC_G_ICLASS_CMS_Pos                 8                                                       /*!< VADC_G ICLASS: CMS Position             */\r
+#define VADC_G_ICLASS_CMS_Msk                 (0x07UL << VADC_G_ICLASS_CMS_Pos)                       /*!< VADC_G ICLASS: CMS Mask                 */\r
+#define VADC_G_ICLASS_STCE_Pos                16                                                      /*!< VADC_G ICLASS: STCE Position            */\r
+#define VADC_G_ICLASS_STCE_Msk                (0x1fUL << VADC_G_ICLASS_STCE_Pos)                      /*!< VADC_G ICLASS: STCE Mask                */\r
+#define VADC_G_ICLASS_CME_Pos                 24                                                      /*!< VADC_G ICLASS: CME Position             */\r
+#define VADC_G_ICLASS_CME_Msk                 (0x07UL << VADC_G_ICLASS_CME_Pos)                       /*!< VADC_G ICLASS: CME Mask                 */\r
+\r
+/* --------------------------------  VADC_G_ALIAS  -------------------------------- */\r
+#define VADC_G_ALIAS_ALIAS0_Pos               0                                                       /*!< VADC_G ALIAS: ALIAS0 Position           */\r
+#define VADC_G_ALIAS_ALIAS0_Msk               (0x1fUL << VADC_G_ALIAS_ALIAS0_Pos)                     /*!< VADC_G ALIAS: ALIAS0 Mask               */\r
+#define VADC_G_ALIAS_ALIAS1_Pos               8                                                       /*!< VADC_G ALIAS: ALIAS1 Position           */\r
+#define VADC_G_ALIAS_ALIAS1_Msk               (0x1fUL << VADC_G_ALIAS_ALIAS1_Pos)                     /*!< VADC_G ALIAS: ALIAS1 Mask               */\r
+\r
+/* --------------------------------  VADC_G_BOUND  -------------------------------- */\r
+#define VADC_G_BOUND_BOUNDARY0_Pos            0                                                       /*!< VADC_G BOUND: BOUNDARY0 Position        */\r
+#define VADC_G_BOUND_BOUNDARY0_Msk            (0x00000fffUL << VADC_G_BOUND_BOUNDARY0_Pos)            /*!< VADC_G BOUND: BOUNDARY0 Mask            */\r
+#define VADC_G_BOUND_BOUNDARY1_Pos            16                                                      /*!< VADC_G BOUND: BOUNDARY1 Position        */\r
+#define VADC_G_BOUND_BOUNDARY1_Msk            (0x00000fffUL << VADC_G_BOUND_BOUNDARY1_Pos)            /*!< VADC_G BOUND: BOUNDARY1 Mask            */\r
+\r
+/* --------------------------------  VADC_G_SYNCTR  ------------------------------- */\r
+#define VADC_G_SYNCTR_STSEL_Pos               0                                                       /*!< VADC_G SYNCTR: STSEL Position           */\r
+#define VADC_G_SYNCTR_STSEL_Msk               (0x03UL << VADC_G_SYNCTR_STSEL_Pos)                     /*!< VADC_G SYNCTR: STSEL Mask               */\r
+#define VADC_G_SYNCTR_EVALR1_Pos              4                                                       /*!< VADC_G SYNCTR: EVALR1 Position          */\r
+#define VADC_G_SYNCTR_EVALR1_Msk              (0x01UL << VADC_G_SYNCTR_EVALR1_Pos)                    /*!< VADC_G SYNCTR: EVALR1 Mask              */\r
+#define VADC_G_SYNCTR_EVALR2_Pos              5                                                       /*!< VADC_G SYNCTR: EVALR2 Position          */\r
+#define VADC_G_SYNCTR_EVALR2_Msk              (0x01UL << VADC_G_SYNCTR_EVALR2_Pos)                    /*!< VADC_G SYNCTR: EVALR2 Mask              */\r
+#define VADC_G_SYNCTR_EVALR3_Pos              6                                                       /*!< VADC_G SYNCTR: EVALR3 Position          */\r
+#define VADC_G_SYNCTR_EVALR3_Msk              (0x01UL << VADC_G_SYNCTR_EVALR3_Pos)                    /*!< VADC_G SYNCTR: EVALR3 Mask              */\r
+\r
+/* ---------------------------------  VADC_G_BFL  --------------------------------- */\r
+#define VADC_G_BFL_BFL0_Pos                   0                                                       /*!< VADC_G BFL: BFL0 Position               */\r
+#define VADC_G_BFL_BFL0_Msk                   (0x01UL << VADC_G_BFL_BFL0_Pos)                         /*!< VADC_G BFL: BFL0 Mask                   */\r
+#define VADC_G_BFL_BFL1_Pos                   1                                                       /*!< VADC_G BFL: BFL1 Position               */\r
+#define VADC_G_BFL_BFL1_Msk                   (0x01UL << VADC_G_BFL_BFL1_Pos)                         /*!< VADC_G BFL: BFL1 Mask                   */\r
+#define VADC_G_BFL_BFL2_Pos                   2                                                       /*!< VADC_G BFL: BFL2 Position               */\r
+#define VADC_G_BFL_BFL2_Msk                   (0x01UL << VADC_G_BFL_BFL2_Pos)                         /*!< VADC_G BFL: BFL2 Mask                   */\r
+#define VADC_G_BFL_BFL3_Pos                   3                                                       /*!< VADC_G BFL: BFL3 Position               */\r
+#define VADC_G_BFL_BFL3_Msk                   (0x01UL << VADC_G_BFL_BFL3_Pos)                         /*!< VADC_G BFL: BFL3 Mask                   */\r
+#define VADC_G_BFL_BFE0_Pos                   16                                                      /*!< VADC_G BFL: BFE0 Position               */\r
+#define VADC_G_BFL_BFE0_Msk                   (0x01UL << VADC_G_BFL_BFE0_Pos)                         /*!< VADC_G BFL: BFE0 Mask                   */\r
+#define VADC_G_BFL_BFE1_Pos                   17                                                      /*!< VADC_G BFL: BFE1 Position               */\r
+#define VADC_G_BFL_BFE1_Msk                   (0x01UL << VADC_G_BFL_BFE1_Pos)                         /*!< VADC_G BFL: BFE1 Mask                   */\r
+#define VADC_G_BFL_BFE2_Pos                   18                                                      /*!< VADC_G BFL: BFE2 Position               */\r
+#define VADC_G_BFL_BFE2_Msk                   (0x01UL << VADC_G_BFL_BFE2_Pos)                         /*!< VADC_G BFL: BFE2 Mask                   */\r
+#define VADC_G_BFL_BFE3_Pos                   19                                                      /*!< VADC_G BFL: BFE3 Position               */\r
+#define VADC_G_BFL_BFE3_Msk                   (0x01UL << VADC_G_BFL_BFE3_Pos)                         /*!< VADC_G BFL: BFE3 Mask                   */\r
+\r
+/* --------------------------------  VADC_G_QCTRL0  ------------------------------- */\r
+#define VADC_G_QCTRL0_XTSEL_Pos               8                                                       /*!< VADC_G QCTRL0: XTSEL Position           */\r
+#define VADC_G_QCTRL0_XTSEL_Msk               (0x0fUL << VADC_G_QCTRL0_XTSEL_Pos)                     /*!< VADC_G QCTRL0: XTSEL Mask               */\r
+#define VADC_G_QCTRL0_XTLVL_Pos               12                                                      /*!< VADC_G QCTRL0: XTLVL Position           */\r
+#define VADC_G_QCTRL0_XTLVL_Msk               (0x01UL << VADC_G_QCTRL0_XTLVL_Pos)                     /*!< VADC_G QCTRL0: XTLVL Mask               */\r
+#define VADC_G_QCTRL0_XTMODE_Pos              13                                                      /*!< VADC_G QCTRL0: XTMODE Position          */\r
+#define VADC_G_QCTRL0_XTMODE_Msk              (0x03UL << VADC_G_QCTRL0_XTMODE_Pos)                    /*!< VADC_G QCTRL0: XTMODE Mask              */\r
+#define VADC_G_QCTRL0_XTWC_Pos                15                                                      /*!< VADC_G QCTRL0: XTWC Position            */\r
+#define VADC_G_QCTRL0_XTWC_Msk                (0x01UL << VADC_G_QCTRL0_XTWC_Pos)                      /*!< VADC_G QCTRL0: XTWC Mask                */\r
+#define VADC_G_QCTRL0_GTSEL_Pos               16                                                      /*!< VADC_G QCTRL0: GTSEL Position           */\r
+#define VADC_G_QCTRL0_GTSEL_Msk               (0x0fUL << VADC_G_QCTRL0_GTSEL_Pos)                     /*!< VADC_G QCTRL0: GTSEL Mask               */\r
+#define VADC_G_QCTRL0_GTLVL_Pos               20                                                      /*!< VADC_G QCTRL0: GTLVL Position           */\r
+#define VADC_G_QCTRL0_GTLVL_Msk               (0x01UL << VADC_G_QCTRL0_GTLVL_Pos)                     /*!< VADC_G QCTRL0: GTLVL Mask               */\r
+#define VADC_G_QCTRL0_GTWC_Pos                23                                                      /*!< VADC_G QCTRL0: GTWC Position            */\r
+#define VADC_G_QCTRL0_GTWC_Msk                (0x01UL << VADC_G_QCTRL0_GTWC_Pos)                      /*!< VADC_G QCTRL0: GTWC Mask                */\r
+#define VADC_G_QCTRL0_TMEN_Pos                28                                                      /*!< VADC_G QCTRL0: TMEN Position            */\r
+#define VADC_G_QCTRL0_TMEN_Msk                (0x01UL << VADC_G_QCTRL0_TMEN_Pos)                      /*!< VADC_G QCTRL0: TMEN Mask                */\r
+#define VADC_G_QCTRL0_TMWC_Pos                31                                                      /*!< VADC_G QCTRL0: TMWC Position            */\r
+#define VADC_G_QCTRL0_TMWC_Msk                (0x01UL << VADC_G_QCTRL0_TMWC_Pos)                      /*!< VADC_G QCTRL0: TMWC Mask                */\r
+\r
+/* ---------------------------------  VADC_G_QMR0  -------------------------------- */\r
+#define VADC_G_QMR0_ENGT_Pos                  0                                                       /*!< VADC_G QMR0: ENGT Position              */\r
+#define VADC_G_QMR0_ENGT_Msk                  (0x03UL << VADC_G_QMR0_ENGT_Pos)                        /*!< VADC_G QMR0: ENGT Mask                  */\r
+#define VADC_G_QMR0_ENTR_Pos                  2                                                       /*!< VADC_G QMR0: ENTR Position              */\r
+#define VADC_G_QMR0_ENTR_Msk                  (0x01UL << VADC_G_QMR0_ENTR_Pos)                        /*!< VADC_G QMR0: ENTR Mask                  */\r
+#define VADC_G_QMR0_CLRV_Pos                  8                                                       /*!< VADC_G QMR0: CLRV Position              */\r
+#define VADC_G_QMR0_CLRV_Msk                  (0x01UL << VADC_G_QMR0_CLRV_Pos)                        /*!< VADC_G QMR0: CLRV Mask                  */\r
+#define VADC_G_QMR0_TREV_Pos                  9                                                       /*!< VADC_G QMR0: TREV Position              */\r
+#define VADC_G_QMR0_TREV_Msk                  (0x01UL << VADC_G_QMR0_TREV_Pos)                        /*!< VADC_G QMR0: TREV Mask                  */\r
+#define VADC_G_QMR0_FLUSH_Pos                 10                                                      /*!< VADC_G QMR0: FLUSH Position             */\r
+#define VADC_G_QMR0_FLUSH_Msk                 (0x01UL << VADC_G_QMR0_FLUSH_Pos)                       /*!< VADC_G QMR0: FLUSH Mask                 */\r
+#define VADC_G_QMR0_CEV_Pos                   11                                                      /*!< VADC_G QMR0: CEV Position               */\r
+#define VADC_G_QMR0_CEV_Msk                   (0x01UL << VADC_G_QMR0_CEV_Pos)                         /*!< VADC_G QMR0: CEV Mask                   */\r
+#define VADC_G_QMR0_RPTDIS_Pos                16                                                      /*!< VADC_G QMR0: RPTDIS Position            */\r
+#define VADC_G_QMR0_RPTDIS_Msk                (0x01UL << VADC_G_QMR0_RPTDIS_Pos)                      /*!< VADC_G QMR0: RPTDIS Mask                */\r
+\r
+/* ---------------------------------  VADC_G_QSR0  -------------------------------- */\r
+#define VADC_G_QSR0_FILL_Pos                  0                                                       /*!< VADC_G QSR0: FILL Position              */\r
+#define VADC_G_QSR0_FILL_Msk                  (0x0fUL << VADC_G_QSR0_FILL_Pos)                        /*!< VADC_G QSR0: FILL Mask                  */\r
+#define VADC_G_QSR0_EMPTY_Pos                 5                                                       /*!< VADC_G QSR0: EMPTY Position             */\r
+#define VADC_G_QSR0_EMPTY_Msk                 (0x01UL << VADC_G_QSR0_EMPTY_Pos)                       /*!< VADC_G QSR0: EMPTY Mask                 */\r
+#define VADC_G_QSR0_REQGT_Pos                 7                                                       /*!< VADC_G QSR0: REQGT Position             */\r
+#define VADC_G_QSR0_REQGT_Msk                 (0x01UL << VADC_G_QSR0_REQGT_Pos)                       /*!< VADC_G QSR0: REQGT Mask                 */\r
+#define VADC_G_QSR0_EV_Pos                    8                                                       /*!< VADC_G QSR0: EV Position                */\r
+#define VADC_G_QSR0_EV_Msk                    (0x01UL << VADC_G_QSR0_EV_Pos)                          /*!< VADC_G QSR0: EV Mask                    */\r
+\r
+/* ---------------------------------  VADC_G_Q0R0  -------------------------------- */\r
+#define VADC_G_Q0R0_REQCHNR_Pos               0                                                       /*!< VADC_G Q0R0: REQCHNR Position           */\r
+#define VADC_G_Q0R0_REQCHNR_Msk               (0x1fUL << VADC_G_Q0R0_REQCHNR_Pos)                     /*!< VADC_G Q0R0: REQCHNR Mask               */\r
+#define VADC_G_Q0R0_RF_Pos                    5                                                       /*!< VADC_G Q0R0: RF Position                */\r
+#define VADC_G_Q0R0_RF_Msk                    (0x01UL << VADC_G_Q0R0_RF_Pos)                          /*!< VADC_G Q0R0: RF Mask                    */\r
+#define VADC_G_Q0R0_ENSI_Pos                  6                                                       /*!< VADC_G Q0R0: ENSI Position              */\r
+#define VADC_G_Q0R0_ENSI_Msk                  (0x01UL << VADC_G_Q0R0_ENSI_Pos)                        /*!< VADC_G Q0R0: ENSI Mask                  */\r
+#define VADC_G_Q0R0_EXTR_Pos                  7                                                       /*!< VADC_G Q0R0: EXTR Position              */\r
+#define VADC_G_Q0R0_EXTR_Msk                  (0x01UL << VADC_G_Q0R0_EXTR_Pos)                        /*!< VADC_G Q0R0: EXTR Mask                  */\r
+#define VADC_G_Q0R0_V_Pos                     8                                                       /*!< VADC_G Q0R0: V Position                 */\r
+#define VADC_G_Q0R0_V_Msk                     (0x01UL << VADC_G_Q0R0_V_Pos)                           /*!< VADC_G Q0R0: V Mask                     */\r
+\r
+/* --------------------------------  VADC_G_QINR0  -------------------------------- */\r
+#define VADC_G_QINR0_REQCHNR_Pos              0                                                       /*!< VADC_G QINR0: REQCHNR Position          */\r
+#define VADC_G_QINR0_REQCHNR_Msk              (0x1fUL << VADC_G_QINR0_REQCHNR_Pos)                    /*!< VADC_G QINR0: REQCHNR Mask              */\r
+#define VADC_G_QINR0_RF_Pos                   5                                                       /*!< VADC_G QINR0: RF Position               */\r
+#define VADC_G_QINR0_RF_Msk                   (0x01UL << VADC_G_QINR0_RF_Pos)                         /*!< VADC_G QINR0: RF Mask                   */\r
+#define VADC_G_QINR0_ENSI_Pos                 6                                                       /*!< VADC_G QINR0: ENSI Position             */\r
+#define VADC_G_QINR0_ENSI_Msk                 (0x01UL << VADC_G_QINR0_ENSI_Pos)                       /*!< VADC_G QINR0: ENSI Mask                 */\r
+#define VADC_G_QINR0_EXTR_Pos                 7                                                       /*!< VADC_G QINR0: EXTR Position             */\r
+#define VADC_G_QINR0_EXTR_Msk                 (0x01UL << VADC_G_QINR0_EXTR_Pos)                       /*!< VADC_G QINR0: EXTR Mask                 */\r
+\r
+/* --------------------------------  VADC_G_QBUR0  -------------------------------- */\r
+#define VADC_G_QBUR0_REQCHNR_Pos              0                                                       /*!< VADC_G QBUR0: REQCHNR Position          */\r
+#define VADC_G_QBUR0_REQCHNR_Msk              (0x1fUL << VADC_G_QBUR0_REQCHNR_Pos)                    /*!< VADC_G QBUR0: REQCHNR Mask              */\r
+#define VADC_G_QBUR0_RF_Pos                   5                                                       /*!< VADC_G QBUR0: RF Position               */\r
+#define VADC_G_QBUR0_RF_Msk                   (0x01UL << VADC_G_QBUR0_RF_Pos)                         /*!< VADC_G QBUR0: RF Mask                   */\r
+#define VADC_G_QBUR0_ENSI_Pos                 6                                                       /*!< VADC_G QBUR0: ENSI Position             */\r
+#define VADC_G_QBUR0_ENSI_Msk                 (0x01UL << VADC_G_QBUR0_ENSI_Pos)                       /*!< VADC_G QBUR0: ENSI Mask                 */\r
+#define VADC_G_QBUR0_EXTR_Pos                 7                                                       /*!< VADC_G QBUR0: EXTR Position             */\r
+#define VADC_G_QBUR0_EXTR_Msk                 (0x01UL << VADC_G_QBUR0_EXTR_Pos)                       /*!< VADC_G QBUR0: EXTR Mask                 */\r
+#define VADC_G_QBUR0_V_Pos                    8                                                       /*!< VADC_G QBUR0: V Position                */\r
+#define VADC_G_QBUR0_V_Msk                    (0x01UL << VADC_G_QBUR0_V_Pos)                          /*!< VADC_G QBUR0: V Mask                    */\r
+\r
+/* --------------------------------  VADC_G_ASCTRL  ------------------------------- */\r
+#define VADC_G_ASCTRL_XTSEL_Pos               8                                                       /*!< VADC_G ASCTRL: XTSEL Position           */\r
+#define VADC_G_ASCTRL_XTSEL_Msk               (0x0fUL << VADC_G_ASCTRL_XTSEL_Pos)                     /*!< VADC_G ASCTRL: XTSEL Mask               */\r
+#define VADC_G_ASCTRL_XTLVL_Pos               12                                                      /*!< VADC_G ASCTRL: XTLVL Position           */\r
+#define VADC_G_ASCTRL_XTLVL_Msk               (0x01UL << VADC_G_ASCTRL_XTLVL_Pos)                     /*!< VADC_G ASCTRL: XTLVL Mask               */\r
+#define VADC_G_ASCTRL_XTMODE_Pos              13                                                      /*!< VADC_G ASCTRL: XTMODE Position          */\r
+#define VADC_G_ASCTRL_XTMODE_Msk              (0x03UL << VADC_G_ASCTRL_XTMODE_Pos)                    /*!< VADC_G ASCTRL: XTMODE Mask              */\r
+#define VADC_G_ASCTRL_XTWC_Pos                15                                                      /*!< VADC_G ASCTRL: XTWC Position            */\r
+#define VADC_G_ASCTRL_XTWC_Msk                (0x01UL << VADC_G_ASCTRL_XTWC_Pos)                      /*!< VADC_G ASCTRL: XTWC Mask                */\r
+#define VADC_G_ASCTRL_GTSEL_Pos               16                                                      /*!< VADC_G ASCTRL: GTSEL Position           */\r
+#define VADC_G_ASCTRL_GTSEL_Msk               (0x0fUL << VADC_G_ASCTRL_GTSEL_Pos)                     /*!< VADC_G ASCTRL: GTSEL Mask               */\r
+#define VADC_G_ASCTRL_GTLVL_Pos               20                                                      /*!< VADC_G ASCTRL: GTLVL Position           */\r
+#define VADC_G_ASCTRL_GTLVL_Msk               (0x01UL << VADC_G_ASCTRL_GTLVL_Pos)                     /*!< VADC_G ASCTRL: GTLVL Mask               */\r
+#define VADC_G_ASCTRL_GTWC_Pos                23                                                      /*!< VADC_G ASCTRL: GTWC Position            */\r
+#define VADC_G_ASCTRL_GTWC_Msk                (0x01UL << VADC_G_ASCTRL_GTWC_Pos)                      /*!< VADC_G ASCTRL: GTWC Mask                */\r
+#define VADC_G_ASCTRL_TMEN_Pos                28                                                      /*!< VADC_G ASCTRL: TMEN Position            */\r
+#define VADC_G_ASCTRL_TMEN_Msk                (0x01UL << VADC_G_ASCTRL_TMEN_Pos)                      /*!< VADC_G ASCTRL: TMEN Mask                */\r
+#define VADC_G_ASCTRL_TMWC_Pos                31                                                      /*!< VADC_G ASCTRL: TMWC Position            */\r
+#define VADC_G_ASCTRL_TMWC_Msk                (0x01UL << VADC_G_ASCTRL_TMWC_Pos)                      /*!< VADC_G ASCTRL: TMWC Mask                */\r
+\r
+/* ---------------------------------  VADC_G_ASMR  -------------------------------- */\r
+#define VADC_G_ASMR_ENGT_Pos                  0                                                       /*!< VADC_G ASMR: ENGT Position              */\r
+#define VADC_G_ASMR_ENGT_Msk                  (0x03UL << VADC_G_ASMR_ENGT_Pos)                        /*!< VADC_G ASMR: ENGT Mask                  */\r
+#define VADC_G_ASMR_ENTR_Pos                  2                                                       /*!< VADC_G ASMR: ENTR Position              */\r
+#define VADC_G_ASMR_ENTR_Msk                  (0x01UL << VADC_G_ASMR_ENTR_Pos)                        /*!< VADC_G ASMR: ENTR Mask                  */\r
+#define VADC_G_ASMR_ENSI_Pos                  3                                                       /*!< VADC_G ASMR: ENSI Position              */\r
+#define VADC_G_ASMR_ENSI_Msk                  (0x01UL << VADC_G_ASMR_ENSI_Pos)                        /*!< VADC_G ASMR: ENSI Mask                  */\r
+#define VADC_G_ASMR_SCAN_Pos                  4                                                       /*!< VADC_G ASMR: SCAN Position              */\r
+#define VADC_G_ASMR_SCAN_Msk                  (0x01UL << VADC_G_ASMR_SCAN_Pos)                        /*!< VADC_G ASMR: SCAN Mask                  */\r
+#define VADC_G_ASMR_LDM_Pos                   5                                                       /*!< VADC_G ASMR: LDM Position               */\r
+#define VADC_G_ASMR_LDM_Msk                   (0x01UL << VADC_G_ASMR_LDM_Pos)                         /*!< VADC_G ASMR: LDM Mask                   */\r
+#define VADC_G_ASMR_REQGT_Pos                 7                                                       /*!< VADC_G ASMR: REQGT Position             */\r
+#define VADC_G_ASMR_REQGT_Msk                 (0x01UL << VADC_G_ASMR_REQGT_Pos)                       /*!< VADC_G ASMR: REQGT Mask                 */\r
+#define VADC_G_ASMR_CLRPND_Pos                8                                                       /*!< VADC_G ASMR: CLRPND Position            */\r
+#define VADC_G_ASMR_CLRPND_Msk                (0x01UL << VADC_G_ASMR_CLRPND_Pos)                      /*!< VADC_G ASMR: CLRPND Mask                */\r
+#define VADC_G_ASMR_LDEV_Pos                  9                                                       /*!< VADC_G ASMR: LDEV Position              */\r
+#define VADC_G_ASMR_LDEV_Msk                  (0x01UL << VADC_G_ASMR_LDEV_Pos)                        /*!< VADC_G ASMR: LDEV Mask                  */\r
+#define VADC_G_ASMR_RPTDIS_Pos                16                                                      /*!< VADC_G ASMR: RPTDIS Position            */\r
+#define VADC_G_ASMR_RPTDIS_Msk                (0x01UL << VADC_G_ASMR_RPTDIS_Pos)                      /*!< VADC_G ASMR: RPTDIS Mask                */\r
+\r
+/* --------------------------------  VADC_G_ASSEL  -------------------------------- */\r
+#define VADC_G_ASSEL_CHSEL0_Pos               0                                                       /*!< VADC_G ASSEL: CHSEL0 Position           */\r
+#define VADC_G_ASSEL_CHSEL0_Msk               (0x01UL << VADC_G_ASSEL_CHSEL0_Pos)                     /*!< VADC_G ASSEL: CHSEL0 Mask               */\r
+#define VADC_G_ASSEL_CHSEL1_Pos               1                                                       /*!< VADC_G ASSEL: CHSEL1 Position           */\r
+#define VADC_G_ASSEL_CHSEL1_Msk               (0x01UL << VADC_G_ASSEL_CHSEL1_Pos)                     /*!< VADC_G ASSEL: CHSEL1 Mask               */\r
+#define VADC_G_ASSEL_CHSEL2_Pos               2                                                       /*!< VADC_G ASSEL: CHSEL2 Position           */\r
+#define VADC_G_ASSEL_CHSEL2_Msk               (0x01UL << VADC_G_ASSEL_CHSEL2_Pos)                     /*!< VADC_G ASSEL: CHSEL2 Mask               */\r
+#define VADC_G_ASSEL_CHSEL3_Pos               3                                                       /*!< VADC_G ASSEL: CHSEL3 Position           */\r
+#define VADC_G_ASSEL_CHSEL3_Msk               (0x01UL << VADC_G_ASSEL_CHSEL3_Pos)                     /*!< VADC_G ASSEL: CHSEL3 Mask               */\r
+#define VADC_G_ASSEL_CHSEL4_Pos               4                                                       /*!< VADC_G ASSEL: CHSEL4 Position           */\r
+#define VADC_G_ASSEL_CHSEL4_Msk               (0x01UL << VADC_G_ASSEL_CHSEL4_Pos)                     /*!< VADC_G ASSEL: CHSEL4 Mask               */\r
+#define VADC_G_ASSEL_CHSEL5_Pos               5                                                       /*!< VADC_G ASSEL: CHSEL5 Position           */\r
+#define VADC_G_ASSEL_CHSEL5_Msk               (0x01UL << VADC_G_ASSEL_CHSEL5_Pos)                     /*!< VADC_G ASSEL: CHSEL5 Mask               */\r
+#define VADC_G_ASSEL_CHSEL6_Pos               6                                                       /*!< VADC_G ASSEL: CHSEL6 Position           */\r
+#define VADC_G_ASSEL_CHSEL6_Msk               (0x01UL << VADC_G_ASSEL_CHSEL6_Pos)                     /*!< VADC_G ASSEL: CHSEL6 Mask               */\r
+#define VADC_G_ASSEL_CHSEL7_Pos               7                                                       /*!< VADC_G ASSEL: CHSEL7 Position           */\r
+#define VADC_G_ASSEL_CHSEL7_Msk               (0x01UL << VADC_G_ASSEL_CHSEL7_Pos)                     /*!< VADC_G ASSEL: CHSEL7 Mask               */\r
+\r
+/* --------------------------------  VADC_G_ASPND  -------------------------------- */\r
+#define VADC_G_ASPND_CHPND0_Pos               0                                                       /*!< VADC_G ASPND: CHPND0 Position           */\r
+#define VADC_G_ASPND_CHPND0_Msk               (0x01UL << VADC_G_ASPND_CHPND0_Pos)                     /*!< VADC_G ASPND: CHPND0 Mask               */\r
+#define VADC_G_ASPND_CHPND1_Pos               1                                                       /*!< VADC_G ASPND: CHPND1 Position           */\r
+#define VADC_G_ASPND_CHPND1_Msk               (0x01UL << VADC_G_ASPND_CHPND1_Pos)                     /*!< VADC_G ASPND: CHPND1 Mask               */\r
+#define VADC_G_ASPND_CHPND2_Pos               2                                                       /*!< VADC_G ASPND: CHPND2 Position           */\r
+#define VADC_G_ASPND_CHPND2_Msk               (0x01UL << VADC_G_ASPND_CHPND2_Pos)                     /*!< VADC_G ASPND: CHPND2 Mask               */\r
+#define VADC_G_ASPND_CHPND3_Pos               3                                                       /*!< VADC_G ASPND: CHPND3 Position           */\r
+#define VADC_G_ASPND_CHPND3_Msk               (0x01UL << VADC_G_ASPND_CHPND3_Pos)                     /*!< VADC_G ASPND: CHPND3 Mask               */\r
+#define VADC_G_ASPND_CHPND4_Pos               4                                                       /*!< VADC_G ASPND: CHPND4 Position           */\r
+#define VADC_G_ASPND_CHPND4_Msk               (0x01UL << VADC_G_ASPND_CHPND4_Pos)                     /*!< VADC_G ASPND: CHPND4 Mask               */\r
+#define VADC_G_ASPND_CHPND5_Pos               5                                                       /*!< VADC_G ASPND: CHPND5 Position           */\r
+#define VADC_G_ASPND_CHPND5_Msk               (0x01UL << VADC_G_ASPND_CHPND5_Pos)                     /*!< VADC_G ASPND: CHPND5 Mask               */\r
+#define VADC_G_ASPND_CHPND6_Pos               6                                                       /*!< VADC_G ASPND: CHPND6 Position           */\r
+#define VADC_G_ASPND_CHPND6_Msk               (0x01UL << VADC_G_ASPND_CHPND6_Pos)                     /*!< VADC_G ASPND: CHPND6 Mask               */\r
+#define VADC_G_ASPND_CHPND7_Pos               7                                                       /*!< VADC_G ASPND: CHPND7 Position           */\r
+#define VADC_G_ASPND_CHPND7_Msk               (0x01UL << VADC_G_ASPND_CHPND7_Pos)                     /*!< VADC_G ASPND: CHPND7 Mask               */\r
+\r
+/* --------------------------------  VADC_G_CEFLAG  ------------------------------- */\r
+#define VADC_G_CEFLAG_CEV0_Pos                0                                                       /*!< VADC_G CEFLAG: CEV0 Position            */\r
+#define VADC_G_CEFLAG_CEV0_Msk                (0x01UL << VADC_G_CEFLAG_CEV0_Pos)                      /*!< VADC_G CEFLAG: CEV0 Mask                */\r
+#define VADC_G_CEFLAG_CEV1_Pos                1                                                       /*!< VADC_G CEFLAG: CEV1 Position            */\r
+#define VADC_G_CEFLAG_CEV1_Msk                (0x01UL << VADC_G_CEFLAG_CEV1_Pos)                      /*!< VADC_G CEFLAG: CEV1 Mask                */\r
+#define VADC_G_CEFLAG_CEV2_Pos                2                                                       /*!< VADC_G CEFLAG: CEV2 Position            */\r
+#define VADC_G_CEFLAG_CEV2_Msk                (0x01UL << VADC_G_CEFLAG_CEV2_Pos)                      /*!< VADC_G CEFLAG: CEV2 Mask                */\r
+#define VADC_G_CEFLAG_CEV3_Pos                3                                                       /*!< VADC_G CEFLAG: CEV3 Position            */\r
+#define VADC_G_CEFLAG_CEV3_Msk                (0x01UL << VADC_G_CEFLAG_CEV3_Pos)                      /*!< VADC_G CEFLAG: CEV3 Mask                */\r
+#define VADC_G_CEFLAG_CEV4_Pos                4                                                       /*!< VADC_G CEFLAG: CEV4 Position            */\r
+#define VADC_G_CEFLAG_CEV4_Msk                (0x01UL << VADC_G_CEFLAG_CEV4_Pos)                      /*!< VADC_G CEFLAG: CEV4 Mask                */\r
+#define VADC_G_CEFLAG_CEV5_Pos                5                                                       /*!< VADC_G CEFLAG: CEV5 Position            */\r
+#define VADC_G_CEFLAG_CEV5_Msk                (0x01UL << VADC_G_CEFLAG_CEV5_Pos)                      /*!< VADC_G CEFLAG: CEV5 Mask                */\r
+#define VADC_G_CEFLAG_CEV6_Pos                6                                                       /*!< VADC_G CEFLAG: CEV6 Position            */\r
+#define VADC_G_CEFLAG_CEV6_Msk                (0x01UL << VADC_G_CEFLAG_CEV6_Pos)                      /*!< VADC_G CEFLAG: CEV6 Mask                */\r
+#define VADC_G_CEFLAG_CEV7_Pos                7                                                       /*!< VADC_G CEFLAG: CEV7 Position            */\r
+#define VADC_G_CEFLAG_CEV7_Msk                (0x01UL << VADC_G_CEFLAG_CEV7_Pos)                      /*!< VADC_G CEFLAG: CEV7 Mask                */\r
+\r
+/* --------------------------------  VADC_G_REFLAG  ------------------------------- */\r
+#define VADC_G_REFLAG_REV0_Pos                0                                                       /*!< VADC_G REFLAG: REV0 Position            */\r
+#define VADC_G_REFLAG_REV0_Msk                (0x01UL << VADC_G_REFLAG_REV0_Pos)                      /*!< VADC_G REFLAG: REV0 Mask                */\r
+#define VADC_G_REFLAG_REV1_Pos                1                                                       /*!< VADC_G REFLAG: REV1 Position            */\r
+#define VADC_G_REFLAG_REV1_Msk                (0x01UL << VADC_G_REFLAG_REV1_Pos)                      /*!< VADC_G REFLAG: REV1 Mask                */\r
+#define VADC_G_REFLAG_REV2_Pos                2                                                       /*!< VADC_G REFLAG: REV2 Position            */\r
+#define VADC_G_REFLAG_REV2_Msk                (0x01UL << VADC_G_REFLAG_REV2_Pos)                      /*!< VADC_G REFLAG: REV2 Mask                */\r
+#define VADC_G_REFLAG_REV3_Pos                3                                                       /*!< VADC_G REFLAG: REV3 Position            */\r
+#define VADC_G_REFLAG_REV3_Msk                (0x01UL << VADC_G_REFLAG_REV3_Pos)                      /*!< VADC_G REFLAG: REV3 Mask                */\r
+#define VADC_G_REFLAG_REV4_Pos                4                                                       /*!< VADC_G REFLAG: REV4 Position            */\r
+#define VADC_G_REFLAG_REV4_Msk                (0x01UL << VADC_G_REFLAG_REV4_Pos)                      /*!< VADC_G REFLAG: REV4 Mask                */\r
+#define VADC_G_REFLAG_REV5_Pos                5                                                       /*!< VADC_G REFLAG: REV5 Position            */\r
+#define VADC_G_REFLAG_REV5_Msk                (0x01UL << VADC_G_REFLAG_REV5_Pos)                      /*!< VADC_G REFLAG: REV5 Mask                */\r
+#define VADC_G_REFLAG_REV6_Pos                6                                                       /*!< VADC_G REFLAG: REV6 Position            */\r
+#define VADC_G_REFLAG_REV6_Msk                (0x01UL << VADC_G_REFLAG_REV6_Pos)                      /*!< VADC_G REFLAG: REV6 Mask                */\r
+#define VADC_G_REFLAG_REV7_Pos                7                                                       /*!< VADC_G REFLAG: REV7 Position            */\r
+#define VADC_G_REFLAG_REV7_Msk                (0x01UL << VADC_G_REFLAG_REV7_Pos)                      /*!< VADC_G REFLAG: REV7 Mask                */\r
+#define VADC_G_REFLAG_REV8_Pos                8                                                       /*!< VADC_G REFLAG: REV8 Position            */\r
+#define VADC_G_REFLAG_REV8_Msk                (0x01UL << VADC_G_REFLAG_REV8_Pos)                      /*!< VADC_G REFLAG: REV8 Mask                */\r
+#define VADC_G_REFLAG_REV9_Pos                9                                                       /*!< VADC_G REFLAG: REV9 Position            */\r
+#define VADC_G_REFLAG_REV9_Msk                (0x01UL << VADC_G_REFLAG_REV9_Pos)                      /*!< VADC_G REFLAG: REV9 Mask                */\r
+#define VADC_G_REFLAG_REV10_Pos               10                                                      /*!< VADC_G REFLAG: REV10 Position           */\r
+#define VADC_G_REFLAG_REV10_Msk               (0x01UL << VADC_G_REFLAG_REV10_Pos)                     /*!< VADC_G REFLAG: REV10 Mask               */\r
+#define VADC_G_REFLAG_REV11_Pos               11                                                      /*!< VADC_G REFLAG: REV11 Position           */\r
+#define VADC_G_REFLAG_REV11_Msk               (0x01UL << VADC_G_REFLAG_REV11_Pos)                     /*!< VADC_G REFLAG: REV11 Mask               */\r
+#define VADC_G_REFLAG_REV12_Pos               12                                                      /*!< VADC_G REFLAG: REV12 Position           */\r
+#define VADC_G_REFLAG_REV12_Msk               (0x01UL << VADC_G_REFLAG_REV12_Pos)                     /*!< VADC_G REFLAG: REV12 Mask               */\r
+#define VADC_G_REFLAG_REV13_Pos               13                                                      /*!< VADC_G REFLAG: REV13 Position           */\r
+#define VADC_G_REFLAG_REV13_Msk               (0x01UL << VADC_G_REFLAG_REV13_Pos)                     /*!< VADC_G REFLAG: REV13 Mask               */\r
+#define VADC_G_REFLAG_REV14_Pos               14                                                      /*!< VADC_G REFLAG: REV14 Position           */\r
+#define VADC_G_REFLAG_REV14_Msk               (0x01UL << VADC_G_REFLAG_REV14_Pos)                     /*!< VADC_G REFLAG: REV14 Mask               */\r
+#define VADC_G_REFLAG_REV15_Pos               15                                                      /*!< VADC_G REFLAG: REV15 Position           */\r
+#define VADC_G_REFLAG_REV15_Msk               (0x01UL << VADC_G_REFLAG_REV15_Pos)                     /*!< VADC_G REFLAG: REV15 Mask               */\r
+\r
+/* --------------------------------  VADC_G_SEFLAG  ------------------------------- */\r
+#define VADC_G_SEFLAG_SEV0_Pos                0                                                       /*!< VADC_G SEFLAG: SEV0 Position            */\r
+#define VADC_G_SEFLAG_SEV0_Msk                (0x01UL << VADC_G_SEFLAG_SEV0_Pos)                      /*!< VADC_G SEFLAG: SEV0 Mask                */\r
+#define VADC_G_SEFLAG_SEV1_Pos                1                                                       /*!< VADC_G SEFLAG: SEV1 Position            */\r
+#define VADC_G_SEFLAG_SEV1_Msk                (0x01UL << VADC_G_SEFLAG_SEV1_Pos)                      /*!< VADC_G SEFLAG: SEV1 Mask                */\r
+\r
+/* --------------------------------  VADC_G_CEFCLR  ------------------------------- */\r
+#define VADC_G_CEFCLR_CEV0_Pos                0                                                       /*!< VADC_G CEFCLR: CEV0 Position            */\r
+#define VADC_G_CEFCLR_CEV0_Msk                (0x01UL << VADC_G_CEFCLR_CEV0_Pos)                      /*!< VADC_G CEFCLR: CEV0 Mask                */\r
+#define VADC_G_CEFCLR_CEV1_Pos                1                                                       /*!< VADC_G CEFCLR: CEV1 Position            */\r
+#define VADC_G_CEFCLR_CEV1_Msk                (0x01UL << VADC_G_CEFCLR_CEV1_Pos)                      /*!< VADC_G CEFCLR: CEV1 Mask                */\r
+#define VADC_G_CEFCLR_CEV2_Pos                2                                                       /*!< VADC_G CEFCLR: CEV2 Position            */\r
+#define VADC_G_CEFCLR_CEV2_Msk                (0x01UL << VADC_G_CEFCLR_CEV2_Pos)                      /*!< VADC_G CEFCLR: CEV2 Mask                */\r
+#define VADC_G_CEFCLR_CEV3_Pos                3                                                       /*!< VADC_G CEFCLR: CEV3 Position            */\r
+#define VADC_G_CEFCLR_CEV3_Msk                (0x01UL << VADC_G_CEFCLR_CEV3_Pos)                      /*!< VADC_G CEFCLR: CEV3 Mask                */\r
+#define VADC_G_CEFCLR_CEV4_Pos                4                                                       /*!< VADC_G CEFCLR: CEV4 Position            */\r
+#define VADC_G_CEFCLR_CEV4_Msk                (0x01UL << VADC_G_CEFCLR_CEV4_Pos)                      /*!< VADC_G CEFCLR: CEV4 Mask                */\r
+#define VADC_G_CEFCLR_CEV5_Pos                5                                                       /*!< VADC_G CEFCLR: CEV5 Position            */\r
+#define VADC_G_CEFCLR_CEV5_Msk                (0x01UL << VADC_G_CEFCLR_CEV5_Pos)                      /*!< VADC_G CEFCLR: CEV5 Mask                */\r
+#define VADC_G_CEFCLR_CEV6_Pos                6                                                       /*!< VADC_G CEFCLR: CEV6 Position            */\r
+#define VADC_G_CEFCLR_CEV6_Msk                (0x01UL << VADC_G_CEFCLR_CEV6_Pos)                      /*!< VADC_G CEFCLR: CEV6 Mask                */\r
+#define VADC_G_CEFCLR_CEV7_Pos                7                                                       /*!< VADC_G CEFCLR: CEV7 Position            */\r
+#define VADC_G_CEFCLR_CEV7_Msk                (0x01UL << VADC_G_CEFCLR_CEV7_Pos)                      /*!< VADC_G CEFCLR: CEV7 Mask                */\r
+\r
+/* --------------------------------  VADC_G_REFCLR  ------------------------------- */\r
+#define VADC_G_REFCLR_REV0_Pos                0                                                       /*!< VADC_G REFCLR: REV0 Position            */\r
+#define VADC_G_REFCLR_REV0_Msk                (0x01UL << VADC_G_REFCLR_REV0_Pos)                      /*!< VADC_G REFCLR: REV0 Mask                */\r
+#define VADC_G_REFCLR_REV1_Pos                1                                                       /*!< VADC_G REFCLR: REV1 Position            */\r
+#define VADC_G_REFCLR_REV1_Msk                (0x01UL << VADC_G_REFCLR_REV1_Pos)                      /*!< VADC_G REFCLR: REV1 Mask                */\r
+#define VADC_G_REFCLR_REV2_Pos                2                                                       /*!< VADC_G REFCLR: REV2 Position            */\r
+#define VADC_G_REFCLR_REV2_Msk                (0x01UL << VADC_G_REFCLR_REV2_Pos)                      /*!< VADC_G REFCLR: REV2 Mask                */\r
+#define VADC_G_REFCLR_REV3_Pos                3                                                       /*!< VADC_G REFCLR: REV3 Position            */\r
+#define VADC_G_REFCLR_REV3_Msk                (0x01UL << VADC_G_REFCLR_REV3_Pos)                      /*!< VADC_G REFCLR: REV3 Mask                */\r
+#define VADC_G_REFCLR_REV4_Pos                4                                                       /*!< VADC_G REFCLR: REV4 Position            */\r
+#define VADC_G_REFCLR_REV4_Msk                (0x01UL << VADC_G_REFCLR_REV4_Pos)                      /*!< VADC_G REFCLR: REV4 Mask                */\r
+#define VADC_G_REFCLR_REV5_Pos                5                                                       /*!< VADC_G REFCLR: REV5 Position            */\r
+#define VADC_G_REFCLR_REV5_Msk                (0x01UL << VADC_G_REFCLR_REV5_Pos)                      /*!< VADC_G REFCLR: REV5 Mask                */\r
+#define VADC_G_REFCLR_REV6_Pos                6                                                       /*!< VADC_G REFCLR: REV6 Position            */\r
+#define VADC_G_REFCLR_REV6_Msk                (0x01UL << VADC_G_REFCLR_REV6_Pos)                      /*!< VADC_G REFCLR: REV6 Mask                */\r
+#define VADC_G_REFCLR_REV7_Pos                7                                                       /*!< VADC_G REFCLR: REV7 Position            */\r
+#define VADC_G_REFCLR_REV7_Msk                (0x01UL << VADC_G_REFCLR_REV7_Pos)                      /*!< VADC_G REFCLR: REV7 Mask                */\r
+#define VADC_G_REFCLR_REV8_Pos                8                                                       /*!< VADC_G REFCLR: REV8 Position            */\r
+#define VADC_G_REFCLR_REV8_Msk                (0x01UL << VADC_G_REFCLR_REV8_Pos)                      /*!< VADC_G REFCLR: REV8 Mask                */\r
+#define VADC_G_REFCLR_REV9_Pos                9                                                       /*!< VADC_G REFCLR: REV9 Position            */\r
+#define VADC_G_REFCLR_REV9_Msk                (0x01UL << VADC_G_REFCLR_REV9_Pos)                      /*!< VADC_G REFCLR: REV9 Mask                */\r
+#define VADC_G_REFCLR_REV10_Pos               10                                                      /*!< VADC_G REFCLR: REV10 Position           */\r
+#define VADC_G_REFCLR_REV10_Msk               (0x01UL << VADC_G_REFCLR_REV10_Pos)                     /*!< VADC_G REFCLR: REV10 Mask               */\r
+#define VADC_G_REFCLR_REV11_Pos               11                                                      /*!< VADC_G REFCLR: REV11 Position           */\r
+#define VADC_G_REFCLR_REV11_Msk               (0x01UL << VADC_G_REFCLR_REV11_Pos)                     /*!< VADC_G REFCLR: REV11 Mask               */\r
+#define VADC_G_REFCLR_REV12_Pos               12                                                      /*!< VADC_G REFCLR: REV12 Position           */\r
+#define VADC_G_REFCLR_REV12_Msk               (0x01UL << VADC_G_REFCLR_REV12_Pos)                     /*!< VADC_G REFCLR: REV12 Mask               */\r
+#define VADC_G_REFCLR_REV13_Pos               13                                                      /*!< VADC_G REFCLR: REV13 Position           */\r
+#define VADC_G_REFCLR_REV13_Msk               (0x01UL << VADC_G_REFCLR_REV13_Pos)                     /*!< VADC_G REFCLR: REV13 Mask               */\r
+#define VADC_G_REFCLR_REV14_Pos               14                                                      /*!< VADC_G REFCLR: REV14 Position           */\r
+#define VADC_G_REFCLR_REV14_Msk               (0x01UL << VADC_G_REFCLR_REV14_Pos)                     /*!< VADC_G REFCLR: REV14 Mask               */\r
+#define VADC_G_REFCLR_REV15_Pos               15                                                      /*!< VADC_G REFCLR: REV15 Position           */\r
+#define VADC_G_REFCLR_REV15_Msk               (0x01UL << VADC_G_REFCLR_REV15_Pos)                     /*!< VADC_G REFCLR: REV15 Mask               */\r
+\r
+/* --------------------------------  VADC_G_SEFCLR  ------------------------------- */\r
+#define VADC_G_SEFCLR_SEV0_Pos                0                                                       /*!< VADC_G SEFCLR: SEV0 Position            */\r
+#define VADC_G_SEFCLR_SEV0_Msk                (0x01UL << VADC_G_SEFCLR_SEV0_Pos)                      /*!< VADC_G SEFCLR: SEV0 Mask                */\r
+#define VADC_G_SEFCLR_SEV1_Pos                1                                                       /*!< VADC_G SEFCLR: SEV1 Position            */\r
+#define VADC_G_SEFCLR_SEV1_Msk                (0x01UL << VADC_G_SEFCLR_SEV1_Pos)                      /*!< VADC_G SEFCLR: SEV1 Mask                */\r
+\r
+/* --------------------------------  VADC_G_CEVNP0  ------------------------------- */\r
+#define VADC_G_CEVNP0_CEV0NP_Pos              0                                                       /*!< VADC_G CEVNP0: CEV0NP Position          */\r
+#define VADC_G_CEVNP0_CEV0NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV0NP_Pos)                    /*!< VADC_G CEVNP0: CEV0NP Mask              */\r
+#define VADC_G_CEVNP0_CEV1NP_Pos              4                                                       /*!< VADC_G CEVNP0: CEV1NP Position          */\r
+#define VADC_G_CEVNP0_CEV1NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV1NP_Pos)                    /*!< VADC_G CEVNP0: CEV1NP Mask              */\r
+#define VADC_G_CEVNP0_CEV2NP_Pos              8                                                       /*!< VADC_G CEVNP0: CEV2NP Position          */\r
+#define VADC_G_CEVNP0_CEV2NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV2NP_Pos)                    /*!< VADC_G CEVNP0: CEV2NP Mask              */\r
+#define VADC_G_CEVNP0_CEV3NP_Pos              12                                                      /*!< VADC_G CEVNP0: CEV3NP Position          */\r
+#define VADC_G_CEVNP0_CEV3NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV3NP_Pos)                    /*!< VADC_G CEVNP0: CEV3NP Mask              */\r
+#define VADC_G_CEVNP0_CEV4NP_Pos              16                                                      /*!< VADC_G CEVNP0: CEV4NP Position          */\r
+#define VADC_G_CEVNP0_CEV4NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV4NP_Pos)                    /*!< VADC_G CEVNP0: CEV4NP Mask              */\r
+#define VADC_G_CEVNP0_CEV5NP_Pos              20                                                      /*!< VADC_G CEVNP0: CEV5NP Position          */\r
+#define VADC_G_CEVNP0_CEV5NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV5NP_Pos)                    /*!< VADC_G CEVNP0: CEV5NP Mask              */\r
+#define VADC_G_CEVNP0_CEV6NP_Pos              24                                                      /*!< VADC_G CEVNP0: CEV6NP Position          */\r
+#define VADC_G_CEVNP0_CEV6NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV6NP_Pos)                    /*!< VADC_G CEVNP0: CEV6NP Mask              */\r
+#define VADC_G_CEVNP0_CEV7NP_Pos              28                                                      /*!< VADC_G CEVNP0: CEV7NP Position          */\r
+#define VADC_G_CEVNP0_CEV7NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV7NP_Pos)                    /*!< VADC_G CEVNP0: CEV7NP Mask              */\r
+\r
+/* --------------------------------  VADC_G_REVNP0  ------------------------------- */\r
+#define VADC_G_REVNP0_REV0NP_Pos              0                                                       /*!< VADC_G REVNP0: REV0NP Position          */\r
+#define VADC_G_REVNP0_REV0NP_Msk              (0x0fUL << VADC_G_REVNP0_REV0NP_Pos)                    /*!< VADC_G REVNP0: REV0NP Mask              */\r
+#define VADC_G_REVNP0_REV1NP_Pos              4                                                       /*!< VADC_G REVNP0: REV1NP Position          */\r
+#define VADC_G_REVNP0_REV1NP_Msk              (0x0fUL << VADC_G_REVNP0_REV1NP_Pos)                    /*!< VADC_G REVNP0: REV1NP Mask              */\r
+#define VADC_G_REVNP0_REV2NP_Pos              8                                                       /*!< VADC_G REVNP0: REV2NP Position          */\r
+#define VADC_G_REVNP0_REV2NP_Msk              (0x0fUL << VADC_G_REVNP0_REV2NP_Pos)                    /*!< VADC_G REVNP0: REV2NP Mask              */\r
+#define VADC_G_REVNP0_REV3NP_Pos              12                                                      /*!< VADC_G REVNP0: REV3NP Position          */\r
+#define VADC_G_REVNP0_REV3NP_Msk              (0x0fUL << VADC_G_REVNP0_REV3NP_Pos)                    /*!< VADC_G REVNP0: REV3NP Mask              */\r
+#define VADC_G_REVNP0_REV4NP_Pos              16                                                      /*!< VADC_G REVNP0: REV4NP Position          */\r
+#define VADC_G_REVNP0_REV4NP_Msk              (0x0fUL << VADC_G_REVNP0_REV4NP_Pos)                    /*!< VADC_G REVNP0: REV4NP Mask              */\r
+#define VADC_G_REVNP0_REV5NP_Pos              20                                                      /*!< VADC_G REVNP0: REV5NP Position          */\r
+#define VADC_G_REVNP0_REV5NP_Msk              (0x0fUL << VADC_G_REVNP0_REV5NP_Pos)                    /*!< VADC_G REVNP0: REV5NP Mask              */\r
+#define VADC_G_REVNP0_REV6NP_Pos              24                                                      /*!< VADC_G REVNP0: REV6NP Position          */\r
+#define VADC_G_REVNP0_REV6NP_Msk              (0x0fUL << VADC_G_REVNP0_REV6NP_Pos)                    /*!< VADC_G REVNP0: REV6NP Mask              */\r
+#define VADC_G_REVNP0_REV7NP_Pos              28                                                      /*!< VADC_G REVNP0: REV7NP Position          */\r
+#define VADC_G_REVNP0_REV7NP_Msk              (0x0fUL << VADC_G_REVNP0_REV7NP_Pos)                    /*!< VADC_G REVNP0: REV7NP Mask              */\r
+\r
+/* --------------------------------  VADC_G_REVNP1  ------------------------------- */\r
+#define VADC_G_REVNP1_REV8NP_Pos              0                                                       /*!< VADC_G REVNP1: REV8NP Position          */\r
+#define VADC_G_REVNP1_REV8NP_Msk              (0x0fUL << VADC_G_REVNP1_REV8NP_Pos)                    /*!< VADC_G REVNP1: REV8NP Mask              */\r
+#define VADC_G_REVNP1_REV9NP_Pos              4                                                       /*!< VADC_G REVNP1: REV9NP Position          */\r
+#define VADC_G_REVNP1_REV9NP_Msk              (0x0fUL << VADC_G_REVNP1_REV9NP_Pos)                    /*!< VADC_G REVNP1: REV9NP Mask              */\r
+#define VADC_G_REVNP1_REV10NP_Pos             8                                                       /*!< VADC_G REVNP1: REV10NP Position         */\r
+#define VADC_G_REVNP1_REV10NP_Msk             (0x0fUL << VADC_G_REVNP1_REV10NP_Pos)                   /*!< VADC_G REVNP1: REV10NP Mask             */\r
+#define VADC_G_REVNP1_REV11NP_Pos             12                                                      /*!< VADC_G REVNP1: REV11NP Position         */\r
+#define VADC_G_REVNP1_REV11NP_Msk             (0x0fUL << VADC_G_REVNP1_REV11NP_Pos)                   /*!< VADC_G REVNP1: REV11NP Mask             */\r
+#define VADC_G_REVNP1_REV12NP_Pos             16                                                      /*!< VADC_G REVNP1: REV12NP Position         */\r
+#define VADC_G_REVNP1_REV12NP_Msk             (0x0fUL << VADC_G_REVNP1_REV12NP_Pos)                   /*!< VADC_G REVNP1: REV12NP Mask             */\r
+#define VADC_G_REVNP1_REV13NP_Pos             20                                                      /*!< VADC_G REVNP1: REV13NP Position         */\r
+#define VADC_G_REVNP1_REV13NP_Msk             (0x0fUL << VADC_G_REVNP1_REV13NP_Pos)                   /*!< VADC_G REVNP1: REV13NP Mask             */\r
+#define VADC_G_REVNP1_REV14NP_Pos             24                                                      /*!< VADC_G REVNP1: REV14NP Position         */\r
+#define VADC_G_REVNP1_REV14NP_Msk             (0x0fUL << VADC_G_REVNP1_REV14NP_Pos)                   /*!< VADC_G REVNP1: REV14NP Mask             */\r
+#define VADC_G_REVNP1_REV15NP_Pos             28                                                      /*!< VADC_G REVNP1: REV15NP Position         */\r
+#define VADC_G_REVNP1_REV15NP_Msk             (0x0fUL << VADC_G_REVNP1_REV15NP_Pos)                   /*!< VADC_G REVNP1: REV15NP Mask             */\r
+\r
+/* --------------------------------  VADC_G_SEVNP  -------------------------------- */\r
+#define VADC_G_SEVNP_SEV0NP_Pos               0                                                       /*!< VADC_G SEVNP: SEV0NP Position           */\r
+#define VADC_G_SEVNP_SEV0NP_Msk               (0x0fUL << VADC_G_SEVNP_SEV0NP_Pos)                     /*!< VADC_G SEVNP: SEV0NP Mask               */\r
+#define VADC_G_SEVNP_SEV1NP_Pos               4                                                       /*!< VADC_G SEVNP: SEV1NP Position           */\r
+#define VADC_G_SEVNP_SEV1NP_Msk               (0x0fUL << VADC_G_SEVNP_SEV1NP_Pos)                     /*!< VADC_G SEVNP: SEV1NP Mask               */\r
+\r
+/* --------------------------------  VADC_G_SRACT  -------------------------------- */\r
+#define VADC_G_SRACT_AGSR0_Pos                0                                                       /*!< VADC_G SRACT: AGSR0 Position            */\r
+#define VADC_G_SRACT_AGSR0_Msk                (0x01UL << VADC_G_SRACT_AGSR0_Pos)                      /*!< VADC_G SRACT: AGSR0 Mask                */\r
+#define VADC_G_SRACT_AGSR1_Pos                1                                                       /*!< VADC_G SRACT: AGSR1 Position            */\r
+#define VADC_G_SRACT_AGSR1_Msk                (0x01UL << VADC_G_SRACT_AGSR1_Pos)                      /*!< VADC_G SRACT: AGSR1 Mask                */\r
+#define VADC_G_SRACT_AGSR2_Pos                2                                                       /*!< VADC_G SRACT: AGSR2 Position            */\r
+#define VADC_G_SRACT_AGSR2_Msk                (0x01UL << VADC_G_SRACT_AGSR2_Pos)                      /*!< VADC_G SRACT: AGSR2 Mask                */\r
+#define VADC_G_SRACT_AGSR3_Pos                3                                                       /*!< VADC_G SRACT: AGSR3 Position            */\r
+#define VADC_G_SRACT_AGSR3_Msk                (0x01UL << VADC_G_SRACT_AGSR3_Pos)                      /*!< VADC_G SRACT: AGSR3 Mask                */\r
+#define VADC_G_SRACT_ASSR0_Pos                8                                                       /*!< VADC_G SRACT: ASSR0 Position            */\r
+#define VADC_G_SRACT_ASSR0_Msk                (0x01UL << VADC_G_SRACT_ASSR0_Pos)                      /*!< VADC_G SRACT: ASSR0 Mask                */\r
+#define VADC_G_SRACT_ASSR1_Pos                9                                                       /*!< VADC_G SRACT: ASSR1 Position            */\r
+#define VADC_G_SRACT_ASSR1_Msk                (0x01UL << VADC_G_SRACT_ASSR1_Pos)                      /*!< VADC_G SRACT: ASSR1 Mask                */\r
+#define VADC_G_SRACT_ASSR2_Pos                10                                                      /*!< VADC_G SRACT: ASSR2 Position            */\r
+#define VADC_G_SRACT_ASSR2_Msk                (0x01UL << VADC_G_SRACT_ASSR2_Pos)                      /*!< VADC_G SRACT: ASSR2 Mask                */\r
+#define VADC_G_SRACT_ASSR3_Pos                11                                                      /*!< VADC_G SRACT: ASSR3 Position            */\r
+#define VADC_G_SRACT_ASSR3_Msk                (0x01UL << VADC_G_SRACT_ASSR3_Pos)                      /*!< VADC_G SRACT: ASSR3 Mask                */\r
+\r
+/* -------------------------------  VADC_G_EMUXCTR  ------------------------------- */\r
+#define VADC_G_EMUXCTR_EMUXSET_Pos            0                                                       /*!< VADC_G EMUXCTR: EMUXSET Position        */\r
+#define VADC_G_EMUXCTR_EMUXSET_Msk            (0x07UL << VADC_G_EMUXCTR_EMUXSET_Pos)                  /*!< VADC_G EMUXCTR: EMUXSET Mask            */\r
+#define VADC_G_EMUXCTR_EMUXACT_Pos            8                                                       /*!< VADC_G EMUXCTR: EMUXACT Position        */\r
+#define VADC_G_EMUXCTR_EMUXACT_Msk            (0x07UL << VADC_G_EMUXCTR_EMUXACT_Pos)                  /*!< VADC_G EMUXCTR: EMUXACT Mask            */\r
+#define VADC_G_EMUXCTR_EMUXCH_Pos             16                                                      /*!< VADC_G EMUXCTR: EMUXCH Position         */\r
+#define VADC_G_EMUXCTR_EMUXCH_Msk             (0x000003ffUL << VADC_G_EMUXCTR_EMUXCH_Pos)             /*!< VADC_G EMUXCTR: EMUXCH Mask             */\r
+#define VADC_G_EMUXCTR_EMUXMODE_Pos           26                                                      /*!< VADC_G EMUXCTR: EMUXMODE Position       */\r
+#define VADC_G_EMUXCTR_EMUXMODE_Msk           (0x03UL << VADC_G_EMUXCTR_EMUXMODE_Pos)                 /*!< VADC_G EMUXCTR: EMUXMODE Mask           */\r
+#define VADC_G_EMUXCTR_EMXCOD_Pos             28                                                      /*!< VADC_G EMUXCTR: EMXCOD Position         */\r
+#define VADC_G_EMUXCTR_EMXCOD_Msk             (0x01UL << VADC_G_EMUXCTR_EMXCOD_Pos)                   /*!< VADC_G EMUXCTR: EMXCOD Mask             */\r
+#define VADC_G_EMUXCTR_EMXST_Pos              29                                                      /*!< VADC_G EMUXCTR: EMXST Position          */\r
+#define VADC_G_EMUXCTR_EMXST_Msk              (0x01UL << VADC_G_EMUXCTR_EMXST_Pos)                    /*!< VADC_G EMUXCTR: EMXST Mask              */\r
+#define VADC_G_EMUXCTR_EMXCSS_Pos             30                                                      /*!< VADC_G EMUXCTR: EMXCSS Position         */\r
+#define VADC_G_EMUXCTR_EMXCSS_Msk             (0x01UL << VADC_G_EMUXCTR_EMXCSS_Pos)                   /*!< VADC_G EMUXCTR: EMXCSS Mask             */\r
+#define VADC_G_EMUXCTR_EMXWC_Pos              31                                                      /*!< VADC_G EMUXCTR: EMXWC Position          */\r
+#define VADC_G_EMUXCTR_EMXWC_Msk              (0x01UL << VADC_G_EMUXCTR_EMXWC_Pos)                    /*!< VADC_G EMUXCTR: EMXWC Mask              */\r
+\r
+/* ---------------------------------  VADC_G_VFR  --------------------------------- */\r
+#define VADC_G_VFR_VF0_Pos                    0                                                       /*!< VADC_G VFR: VF0 Position                */\r
+#define VADC_G_VFR_VF0_Msk                    (0x01UL << VADC_G_VFR_VF0_Pos)                          /*!< VADC_G VFR: VF0 Mask                    */\r
+#define VADC_G_VFR_VF1_Pos                    1                                                       /*!< VADC_G VFR: VF1 Position                */\r
+#define VADC_G_VFR_VF1_Msk                    (0x01UL << VADC_G_VFR_VF1_Pos)                          /*!< VADC_G VFR: VF1 Mask                    */\r
+#define VADC_G_VFR_VF2_Pos                    2                                                       /*!< VADC_G VFR: VF2 Position                */\r
+#define VADC_G_VFR_VF2_Msk                    (0x01UL << VADC_G_VFR_VF2_Pos)                          /*!< VADC_G VFR: VF2 Mask                    */\r
+#define VADC_G_VFR_VF3_Pos                    3                                                       /*!< VADC_G VFR: VF3 Position                */\r
+#define VADC_G_VFR_VF3_Msk                    (0x01UL << VADC_G_VFR_VF3_Pos)                          /*!< VADC_G VFR: VF3 Mask                    */\r
+#define VADC_G_VFR_VF4_Pos                    4                                                       /*!< VADC_G VFR: VF4 Position                */\r
+#define VADC_G_VFR_VF4_Msk                    (0x01UL << VADC_G_VFR_VF4_Pos)                          /*!< VADC_G VFR: VF4 Mask                    */\r
+#define VADC_G_VFR_VF5_Pos                    5                                                       /*!< VADC_G VFR: VF5 Position                */\r
+#define VADC_G_VFR_VF5_Msk                    (0x01UL << VADC_G_VFR_VF5_Pos)                          /*!< VADC_G VFR: VF5 Mask                    */\r
+#define VADC_G_VFR_VF6_Pos                    6                                                       /*!< VADC_G VFR: VF6 Position                */\r
+#define VADC_G_VFR_VF6_Msk                    (0x01UL << VADC_G_VFR_VF6_Pos)                          /*!< VADC_G VFR: VF6 Mask                    */\r
+#define VADC_G_VFR_VF7_Pos                    7                                                       /*!< VADC_G VFR: VF7 Position                */\r
+#define VADC_G_VFR_VF7_Msk                    (0x01UL << VADC_G_VFR_VF7_Pos)                          /*!< VADC_G VFR: VF7 Mask                    */\r
+#define VADC_G_VFR_VF8_Pos                    8                                                       /*!< VADC_G VFR: VF8 Position                */\r
+#define VADC_G_VFR_VF8_Msk                    (0x01UL << VADC_G_VFR_VF8_Pos)                          /*!< VADC_G VFR: VF8 Mask                    */\r
+#define VADC_G_VFR_VF9_Pos                    9                                                       /*!< VADC_G VFR: VF9 Position                */\r
+#define VADC_G_VFR_VF9_Msk                    (0x01UL << VADC_G_VFR_VF9_Pos)                          /*!< VADC_G VFR: VF9 Mask                    */\r
+#define VADC_G_VFR_VF10_Pos                   10                                                      /*!< VADC_G VFR: VF10 Position               */\r
+#define VADC_G_VFR_VF10_Msk                   (0x01UL << VADC_G_VFR_VF10_Pos)                         /*!< VADC_G VFR: VF10 Mask                   */\r
+#define VADC_G_VFR_VF11_Pos                   11                                                      /*!< VADC_G VFR: VF11 Position               */\r
+#define VADC_G_VFR_VF11_Msk                   (0x01UL << VADC_G_VFR_VF11_Pos)                         /*!< VADC_G VFR: VF11 Mask                   */\r
+#define VADC_G_VFR_VF12_Pos                   12                                                      /*!< VADC_G VFR: VF12 Position               */\r
+#define VADC_G_VFR_VF12_Msk                   (0x01UL << VADC_G_VFR_VF12_Pos)                         /*!< VADC_G VFR: VF12 Mask                   */\r
+#define VADC_G_VFR_VF13_Pos                   13                                                      /*!< VADC_G VFR: VF13 Position               */\r
+#define VADC_G_VFR_VF13_Msk                   (0x01UL << VADC_G_VFR_VF13_Pos)                         /*!< VADC_G VFR: VF13 Mask                   */\r
+#define VADC_G_VFR_VF14_Pos                   14                                                      /*!< VADC_G VFR: VF14 Position               */\r
+#define VADC_G_VFR_VF14_Msk                   (0x01UL << VADC_G_VFR_VF14_Pos)                         /*!< VADC_G VFR: VF14 Mask                   */\r
+#define VADC_G_VFR_VF15_Pos                   15                                                      /*!< VADC_G VFR: VF15 Position               */\r
+#define VADC_G_VFR_VF15_Msk                   (0x01UL << VADC_G_VFR_VF15_Pos)                         /*!< VADC_G VFR: VF15 Mask                   */\r
+\r
+/* --------------------------------  VADC_G_CHCTR  -------------------------------- */\r
+#define VADC_G_CHCTR_ICLSEL_Pos               0                                                       /*!< VADC_G CHCTR: ICLSEL Position           */\r
+#define VADC_G_CHCTR_ICLSEL_Msk               (0x03UL << VADC_G_CHCTR_ICLSEL_Pos)                     /*!< VADC_G CHCTR: ICLSEL Mask               */\r
+#define VADC_G_CHCTR_BNDSELL_Pos              4                                                       /*!< VADC_G CHCTR: BNDSELL Position          */\r
+#define VADC_G_CHCTR_BNDSELL_Msk              (0x03UL << VADC_G_CHCTR_BNDSELL_Pos)                    /*!< VADC_G CHCTR: BNDSELL Mask              */\r
+#define VADC_G_CHCTR_BNDSELU_Pos              6                                                       /*!< VADC_G CHCTR: BNDSELU Position          */\r
+#define VADC_G_CHCTR_BNDSELU_Msk              (0x03UL << VADC_G_CHCTR_BNDSELU_Pos)                    /*!< VADC_G CHCTR: BNDSELU Mask              */\r
+#define VADC_G_CHCTR_CHEVMODE_Pos             8                                                       /*!< VADC_G CHCTR: CHEVMODE Position         */\r
+#define VADC_G_CHCTR_CHEVMODE_Msk             (0x03UL << VADC_G_CHCTR_CHEVMODE_Pos)                   /*!< VADC_G CHCTR: CHEVMODE Mask             */\r
+#define VADC_G_CHCTR_SYNC_Pos                 10                                                      /*!< VADC_G CHCTR: SYNC Position             */\r
+#define VADC_G_CHCTR_SYNC_Msk                 (0x01UL << VADC_G_CHCTR_SYNC_Pos)                       /*!< VADC_G CHCTR: SYNC Mask                 */\r
+#define VADC_G_CHCTR_REFSEL_Pos               11                                                      /*!< VADC_G CHCTR: REFSEL Position           */\r
+#define VADC_G_CHCTR_REFSEL_Msk               (0x01UL << VADC_G_CHCTR_REFSEL_Pos)                     /*!< VADC_G CHCTR: REFSEL Mask               */\r
+#define VADC_G_CHCTR_RESREG_Pos               16                                                      /*!< VADC_G CHCTR: RESREG Position           */\r
+#define VADC_G_CHCTR_RESREG_Msk               (0x0fUL << VADC_G_CHCTR_RESREG_Pos)                     /*!< VADC_G CHCTR: RESREG Mask               */\r
+#define VADC_G_CHCTR_RESTBS_Pos               20                                                      /*!< VADC_G CHCTR: RESTBS Position           */\r
+#define VADC_G_CHCTR_RESTBS_Msk               (0x01UL << VADC_G_CHCTR_RESTBS_Pos)                     /*!< VADC_G CHCTR: RESTBS Mask               */\r
+#define VADC_G_CHCTR_RESPOS_Pos               21                                                      /*!< VADC_G CHCTR: RESPOS Position           */\r
+#define VADC_G_CHCTR_RESPOS_Msk               (0x01UL << VADC_G_CHCTR_RESPOS_Pos)                     /*!< VADC_G CHCTR: RESPOS Mask               */\r
+#define VADC_G_CHCTR_BWDCH_Pos                28                                                      /*!< VADC_G CHCTR: BWDCH Position            */\r
+#define VADC_G_CHCTR_BWDCH_Msk                (0x03UL << VADC_G_CHCTR_BWDCH_Pos)                      /*!< VADC_G CHCTR: BWDCH Mask                */\r
+#define VADC_G_CHCTR_BWDEN_Pos                30                                                      /*!< VADC_G CHCTR: BWDEN Position            */\r
+#define VADC_G_CHCTR_BWDEN_Msk                (0x01UL << VADC_G_CHCTR_BWDEN_Pos)                      /*!< VADC_G CHCTR: BWDEN Mask                */\r
+\r
+/* ---------------------------------  VADC_G_RCR  --------------------------------- */\r
+#define VADC_G_RCR_DRCTR_Pos                  16                                                      /*!< VADC_G RCR: DRCTR Position              */\r
+#define VADC_G_RCR_DRCTR_Msk                  (0x0fUL << VADC_G_RCR_DRCTR_Pos)                        /*!< VADC_G RCR: DRCTR Mask                  */\r
+#define VADC_G_RCR_DMM_Pos                    20                                                      /*!< VADC_G RCR: DMM Position                */\r
+#define VADC_G_RCR_DMM_Msk                    (0x03UL << VADC_G_RCR_DMM_Pos)                          /*!< VADC_G RCR: DMM Mask                    */\r
+#define VADC_G_RCR_WFR_Pos                    24                                                      /*!< VADC_G RCR: WFR Position                */\r
+#define VADC_G_RCR_WFR_Msk                    (0x01UL << VADC_G_RCR_WFR_Pos)                          /*!< VADC_G RCR: WFR Mask                    */\r
+#define VADC_G_RCR_FEN_Pos                    25                                                      /*!< VADC_G RCR: FEN Position                */\r
+#define VADC_G_RCR_FEN_Msk                    (0x03UL << VADC_G_RCR_FEN_Pos)                          /*!< VADC_G RCR: FEN Mask                    */\r
+#define VADC_G_RCR_SRGEN_Pos                  31                                                      /*!< VADC_G RCR: SRGEN Position              */\r
+#define VADC_G_RCR_SRGEN_Msk                  (0x01UL << VADC_G_RCR_SRGEN_Pos)                        /*!< VADC_G RCR: SRGEN Mask                  */\r
+\r
+/* ---------------------------------  VADC_G_RES  --------------------------------- */\r
+#define VADC_G_RES_RESULT_Pos                 0                                                       /*!< VADC_G RES: RESULT Position             */\r
+#define VADC_G_RES_RESULT_Msk                 (0x0000ffffUL << VADC_G_RES_RESULT_Pos)                 /*!< VADC_G RES: RESULT Mask                 */\r
+#define VADC_G_RES_DRC_Pos                    16                                                      /*!< VADC_G RES: DRC Position                */\r
+#define VADC_G_RES_DRC_Msk                    (0x0fUL << VADC_G_RES_DRC_Pos)                          /*!< VADC_G RES: DRC Mask                    */\r
+#define VADC_G_RES_CHNR_Pos                   20                                                      /*!< VADC_G RES: CHNR Position               */\r
+#define VADC_G_RES_CHNR_Msk                   (0x1fUL << VADC_G_RES_CHNR_Pos)                         /*!< VADC_G RES: CHNR Mask                   */\r
+#define VADC_G_RES_EMUX_Pos                   25                                                      /*!< VADC_G RES: EMUX Position               */\r
+#define VADC_G_RES_EMUX_Msk                   (0x07UL << VADC_G_RES_EMUX_Pos)                         /*!< VADC_G RES: EMUX Mask                   */\r
+#define VADC_G_RES_CRS_Pos                    28                                                      /*!< VADC_G RES: CRS Position                */\r
+#define VADC_G_RES_CRS_Msk                    (0x03UL << VADC_G_RES_CRS_Pos)                          /*!< VADC_G RES: CRS Mask                    */\r
+#define VADC_G_RES_FCR_Pos                    30                                                      /*!< VADC_G RES: FCR Position                */\r
+#define VADC_G_RES_FCR_Msk                    (0x01UL << VADC_G_RES_FCR_Pos)                          /*!< VADC_G RES: FCR Mask                    */\r
+#define VADC_G_RES_VF_Pos                     31                                                      /*!< VADC_G RES: VF Position                 */\r
+#define VADC_G_RES_VF_Msk                     (0x01UL << VADC_G_RES_VF_Pos)                           /*!< VADC_G RES: VF Mask                     */\r
+\r
+/* ---------------------------------  VADC_G_RESD  -------------------------------- */\r
+#define VADC_G_RESD_RESULT_Pos                0                                                       /*!< VADC_G RESD: RESULT Position            */\r
+#define VADC_G_RESD_RESULT_Msk                (0x0000ffffUL << VADC_G_RESD_RESULT_Pos)                /*!< VADC_G RESD: RESULT Mask                */\r
+#define VADC_G_RESD_DRC_Pos                   16                                                      /*!< VADC_G RESD: DRC Position               */\r
+#define VADC_G_RESD_DRC_Msk                   (0x0fUL << VADC_G_RESD_DRC_Pos)                         /*!< VADC_G RESD: DRC Mask                   */\r
+#define VADC_G_RESD_CHNR_Pos                  20                                                      /*!< VADC_G RESD: CHNR Position              */\r
+#define VADC_G_RESD_CHNR_Msk                  (0x1fUL << VADC_G_RESD_CHNR_Pos)                        /*!< VADC_G RESD: CHNR Mask                  */\r
+#define VADC_G_RESD_EMUX_Pos                  25                                                      /*!< VADC_G RESD: EMUX Position              */\r
+#define VADC_G_RESD_EMUX_Msk                  (0x07UL << VADC_G_RESD_EMUX_Pos)                        /*!< VADC_G RESD: EMUX Mask                  */\r
+#define VADC_G_RESD_CRS_Pos                   28                                                      /*!< VADC_G RESD: CRS Position               */\r
+#define VADC_G_RESD_CRS_Msk                   (0x03UL << VADC_G_RESD_CRS_Pos)                         /*!< VADC_G RESD: CRS Mask                   */\r
+#define VADC_G_RESD_FCR_Pos                   30                                                      /*!< VADC_G RESD: FCR Position               */\r
+#define VADC_G_RESD_FCR_Msk                   (0x01UL << VADC_G_RESD_FCR_Pos)                         /*!< VADC_G RESD: FCR Mask                   */\r
+#define VADC_G_RESD_VF_Pos                    31                                                      /*!< VADC_G RESD: VF Position                */\r
+#define VADC_G_RESD_VF_Msk                    (0x01UL << VADC_G_RESD_VF_Pos)                          /*!< VADC_G RESD: VF Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'DSD' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  DSD_CLC  ---------------------------------- */\r
+#define DSD_CLC_DISR_Pos                      0                                                       /*!< DSD CLC: DISR Position                  */\r
+#define DSD_CLC_DISR_Msk                      (0x01UL << DSD_CLC_DISR_Pos)                            /*!< DSD CLC: DISR Mask                      */\r
+#define DSD_CLC_DISS_Pos                      1                                                       /*!< DSD CLC: DISS Position                  */\r
+#define DSD_CLC_DISS_Msk                      (0x01UL << DSD_CLC_DISS_Pos)                            /*!< DSD CLC: DISS Mask                      */\r
+#define DSD_CLC_EDIS_Pos                      3                                                       /*!< DSD CLC: EDIS Position                  */\r
+#define DSD_CLC_EDIS_Msk                      (0x01UL << DSD_CLC_EDIS_Pos)                            /*!< DSD CLC: EDIS Mask                      */\r
+\r
+/* -----------------------------------  DSD_ID  ----------------------------------- */\r
+#define DSD_ID_MOD_REV_Pos                    0                                                       /*!< DSD ID: MOD_REV Position                */\r
+#define DSD_ID_MOD_REV_Msk                    (0x000000ffUL << DSD_ID_MOD_REV_Pos)                    /*!< DSD ID: MOD_REV Mask                    */\r
+#define DSD_ID_MOD_TYPE_Pos                   8                                                       /*!< DSD ID: MOD_TYPE Position               */\r
+#define DSD_ID_MOD_TYPE_Msk                   (0x000000ffUL << DSD_ID_MOD_TYPE_Pos)                   /*!< DSD ID: MOD_TYPE Mask                   */\r
+#define DSD_ID_MOD_NUMBER_Pos                 16                                                      /*!< DSD ID: MOD_NUMBER Position             */\r
+#define DSD_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << DSD_ID_MOD_NUMBER_Pos)                 /*!< DSD ID: MOD_NUMBER Mask                 */\r
+\r
+/* -----------------------------------  DSD_OCS  ---------------------------------- */\r
+#define DSD_OCS_SUS_Pos                       24                                                      /*!< DSD OCS: SUS Position                   */\r
+#define DSD_OCS_SUS_Msk                       (0x0fUL << DSD_OCS_SUS_Pos)                             /*!< DSD OCS: SUS Mask                       */\r
+#define DSD_OCS_SUS_P_Pos                     28                                                      /*!< DSD OCS: SUS_P Position                 */\r
+#define DSD_OCS_SUS_P_Msk                     (0x01UL << DSD_OCS_SUS_P_Pos)                           /*!< DSD OCS: SUS_P Mask                     */\r
+#define DSD_OCS_SUSSTA_Pos                    29                                                      /*!< DSD OCS: SUSSTA Position                */\r
+#define DSD_OCS_SUSSTA_Msk                    (0x01UL << DSD_OCS_SUSSTA_Pos)                          /*!< DSD OCS: SUSSTA Mask                    */\r
+\r
+/* ---------------------------------  DSD_GLOBCFG  -------------------------------- */\r
+#define DSD_GLOBCFG_MCSEL_Pos                 0                                                       /*!< DSD GLOBCFG: MCSEL Position             */\r
+#define DSD_GLOBCFG_MCSEL_Msk                 (0x07UL << DSD_GLOBCFG_MCSEL_Pos)                       /*!< DSD GLOBCFG: MCSEL Mask                 */\r
+\r
+/* ---------------------------------  DSD_GLOBRC  --------------------------------- */\r
+#define DSD_GLOBRC_CH0RUN_Pos                 0                                                       /*!< DSD GLOBRC: CH0RUN Position             */\r
+#define DSD_GLOBRC_CH0RUN_Msk                 (0x01UL << DSD_GLOBRC_CH0RUN_Pos)                       /*!< DSD GLOBRC: CH0RUN Mask                 */\r
+#define DSD_GLOBRC_CH1RUN_Pos                 1                                                       /*!< DSD GLOBRC: CH1RUN Position             */\r
+#define DSD_GLOBRC_CH1RUN_Msk                 (0x01UL << DSD_GLOBRC_CH1RUN_Pos)                       /*!< DSD GLOBRC: CH1RUN Mask                 */\r
+#define DSD_GLOBRC_CH2RUN_Pos                 2                                                       /*!< DSD GLOBRC: CH2RUN Position             */\r
+#define DSD_GLOBRC_CH2RUN_Msk                 (0x01UL << DSD_GLOBRC_CH2RUN_Pos)                       /*!< DSD GLOBRC: CH2RUN Mask                 */\r
+#define DSD_GLOBRC_CH3RUN_Pos                 3                                                       /*!< DSD GLOBRC: CH3RUN Position             */\r
+#define DSD_GLOBRC_CH3RUN_Msk                 (0x01UL << DSD_GLOBRC_CH3RUN_Pos)                       /*!< DSD GLOBRC: CH3RUN Mask                 */\r
+\r
+/* ----------------------------------  DSD_CGCFG  --------------------------------- */\r
+#define DSD_CGCFG_CGMOD_Pos                   0                                                       /*!< DSD CGCFG: CGMOD Position               */\r
+#define DSD_CGCFG_CGMOD_Msk                   (0x03UL << DSD_CGCFG_CGMOD_Pos)                         /*!< DSD CGCFG: CGMOD Mask                   */\r
+#define DSD_CGCFG_BREV_Pos                    2                                                       /*!< DSD CGCFG: BREV Position                */\r
+#define DSD_CGCFG_BREV_Msk                    (0x01UL << DSD_CGCFG_BREV_Pos)                          /*!< DSD CGCFG: BREV Mask                    */\r
+#define DSD_CGCFG_SIGPOL_Pos                  3                                                       /*!< DSD CGCFG: SIGPOL Position              */\r
+#define DSD_CGCFG_SIGPOL_Msk                  (0x01UL << DSD_CGCFG_SIGPOL_Pos)                        /*!< DSD CGCFG: SIGPOL Mask                  */\r
+#define DSD_CGCFG_DIVCG_Pos                   4                                                       /*!< DSD CGCFG: DIVCG Position               */\r
+#define DSD_CGCFG_DIVCG_Msk                   (0x0fUL << DSD_CGCFG_DIVCG_Pos)                         /*!< DSD CGCFG: DIVCG Mask                   */\r
+#define DSD_CGCFG_RUN_Pos                     15                                                      /*!< DSD CGCFG: RUN Position                 */\r
+#define DSD_CGCFG_RUN_Msk                     (0x01UL << DSD_CGCFG_RUN_Pos)                           /*!< DSD CGCFG: RUN Mask                     */\r
+#define DSD_CGCFG_BITCOUNT_Pos                16                                                      /*!< DSD CGCFG: BITCOUNT Position            */\r
+#define DSD_CGCFG_BITCOUNT_Msk                (0x1fUL << DSD_CGCFG_BITCOUNT_Pos)                      /*!< DSD CGCFG: BITCOUNT Mask                */\r
+#define DSD_CGCFG_STEPCOUNT_Pos               24                                                      /*!< DSD CGCFG: STEPCOUNT Position           */\r
+#define DSD_CGCFG_STEPCOUNT_Msk               (0x0fUL << DSD_CGCFG_STEPCOUNT_Pos)                     /*!< DSD CGCFG: STEPCOUNT Mask               */\r
+#define DSD_CGCFG_STEPS_Pos                   28                                                      /*!< DSD CGCFG: STEPS Position               */\r
+#define DSD_CGCFG_STEPS_Msk                   (0x01UL << DSD_CGCFG_STEPS_Pos)                         /*!< DSD CGCFG: STEPS Mask                   */\r
+#define DSD_CGCFG_STEPD_Pos                   29                                                      /*!< DSD CGCFG: STEPD Position               */\r
+#define DSD_CGCFG_STEPD_Msk                   (0x01UL << DSD_CGCFG_STEPD_Pos)                         /*!< DSD CGCFG: STEPD Mask                   */\r
+#define DSD_CGCFG_SGNCG_Pos                   30                                                      /*!< DSD CGCFG: SGNCG Position               */\r
+#define DSD_CGCFG_SGNCG_Msk                   (0x01UL << DSD_CGCFG_SGNCG_Pos)                         /*!< DSD CGCFG: SGNCG Mask                   */\r
+\r
+/* ---------------------------------  DSD_EVFLAG  --------------------------------- */\r
+#define DSD_EVFLAG_RESEV0_Pos                 0                                                       /*!< DSD EVFLAG: RESEV0 Position             */\r
+#define DSD_EVFLAG_RESEV0_Msk                 (0x01UL << DSD_EVFLAG_RESEV0_Pos)                       /*!< DSD EVFLAG: RESEV0 Mask                 */\r
+#define DSD_EVFLAG_RESEV1_Pos                 1                                                       /*!< DSD EVFLAG: RESEV1 Position             */\r
+#define DSD_EVFLAG_RESEV1_Msk                 (0x01UL << DSD_EVFLAG_RESEV1_Pos)                       /*!< DSD EVFLAG: RESEV1 Mask                 */\r
+#define DSD_EVFLAG_RESEV2_Pos                 2                                                       /*!< DSD EVFLAG: RESEV2 Position             */\r
+#define DSD_EVFLAG_RESEV2_Msk                 (0x01UL << DSD_EVFLAG_RESEV2_Pos)                       /*!< DSD EVFLAG: RESEV2 Mask                 */\r
+#define DSD_EVFLAG_RESEV3_Pos                 3                                                       /*!< DSD EVFLAG: RESEV3 Position             */\r
+#define DSD_EVFLAG_RESEV3_Msk                 (0x01UL << DSD_EVFLAG_RESEV3_Pos)                       /*!< DSD EVFLAG: RESEV3 Mask                 */\r
+#define DSD_EVFLAG_ALEV0_Pos                  16                                                      /*!< DSD EVFLAG: ALEV0 Position              */\r
+#define DSD_EVFLAG_ALEV0_Msk                  (0x01UL << DSD_EVFLAG_ALEV0_Pos)                        /*!< DSD EVFLAG: ALEV0 Mask                  */\r
+#define DSD_EVFLAG_ALEV1_Pos                  17                                                      /*!< DSD EVFLAG: ALEV1 Position              */\r
+#define DSD_EVFLAG_ALEV1_Msk                  (0x01UL << DSD_EVFLAG_ALEV1_Pos)                        /*!< DSD EVFLAG: ALEV1 Mask                  */\r
+#define DSD_EVFLAG_ALEV2_Pos                  18                                                      /*!< DSD EVFLAG: ALEV2 Position              */\r
+#define DSD_EVFLAG_ALEV2_Msk                  (0x01UL << DSD_EVFLAG_ALEV2_Pos)                        /*!< DSD EVFLAG: ALEV2 Mask                  */\r
+#define DSD_EVFLAG_ALEV3_Pos                  19                                                      /*!< DSD EVFLAG: ALEV3 Position              */\r
+#define DSD_EVFLAG_ALEV3_Msk                  (0x01UL << DSD_EVFLAG_ALEV3_Pos)                        /*!< DSD EVFLAG: ALEV3 Mask                  */\r
+#define DSD_EVFLAG_ALEV4_Pos                  20                                                      /*!< DSD EVFLAG: ALEV4 Position              */\r
+#define DSD_EVFLAG_ALEV4_Msk                  (0x01UL << DSD_EVFLAG_ALEV4_Pos)                        /*!< DSD EVFLAG: ALEV4 Mask                  */\r
+#define DSD_EVFLAG_ALEV5_Pos                  21                                                      /*!< DSD EVFLAG: ALEV5 Position              */\r
+#define DSD_EVFLAG_ALEV5_Msk                  (0x01UL << DSD_EVFLAG_ALEV5_Pos)                        /*!< DSD EVFLAG: ALEV5 Mask                  */\r
+#define DSD_EVFLAG_ALEV6_Pos                  22                                                      /*!< DSD EVFLAG: ALEV6 Position              */\r
+#define DSD_EVFLAG_ALEV6_Msk                  (0x01UL << DSD_EVFLAG_ALEV6_Pos)                        /*!< DSD EVFLAG: ALEV6 Mask                  */\r
+#define DSD_EVFLAG_ALEV7_Pos                  23                                                      /*!< DSD EVFLAG: ALEV7 Position              */\r
+#define DSD_EVFLAG_ALEV7_Msk                  (0x01UL << DSD_EVFLAG_ALEV7_Pos)                        /*!< DSD EVFLAG: ALEV7 Mask                  */\r
+#define DSD_EVFLAG_ALEV8_Pos                  24                                                      /*!< DSD EVFLAG: ALEV8 Position              */\r
+#define DSD_EVFLAG_ALEV8_Msk                  (0x01UL << DSD_EVFLAG_ALEV8_Pos)                        /*!< DSD EVFLAG: ALEV8 Mask                  */\r
+#define DSD_EVFLAG_ALEV9_Pos                  25                                                      /*!< DSD EVFLAG: ALEV9 Position              */\r
+#define DSD_EVFLAG_ALEV9_Msk                  (0x01UL << DSD_EVFLAG_ALEV9_Pos)                        /*!< DSD EVFLAG: ALEV9 Mask                  */\r
+\r
+/* --------------------------------  DSD_EVFLAGCLR  ------------------------------- */\r
+#define DSD_EVFLAGCLR_RESEC0_Pos              0                                                       /*!< DSD EVFLAGCLR: RESEC0 Position          */\r
+#define DSD_EVFLAGCLR_RESEC0_Msk              (0x01UL << DSD_EVFLAGCLR_RESEC0_Pos)                    /*!< DSD EVFLAGCLR: RESEC0 Mask              */\r
+#define DSD_EVFLAGCLR_RESEC1_Pos              1                                                       /*!< DSD EVFLAGCLR: RESEC1 Position          */\r
+#define DSD_EVFLAGCLR_RESEC1_Msk              (0x01UL << DSD_EVFLAGCLR_RESEC1_Pos)                    /*!< DSD EVFLAGCLR: RESEC1 Mask              */\r
+#define DSD_EVFLAGCLR_RESEC2_Pos              2                                                       /*!< DSD EVFLAGCLR: RESEC2 Position          */\r
+#define DSD_EVFLAGCLR_RESEC2_Msk              (0x01UL << DSD_EVFLAGCLR_RESEC2_Pos)                    /*!< DSD EVFLAGCLR: RESEC2 Mask              */\r
+#define DSD_EVFLAGCLR_RESEC3_Pos              3                                                       /*!< DSD EVFLAGCLR: RESEC3 Position          */\r
+#define DSD_EVFLAGCLR_RESEC3_Msk              (0x01UL << DSD_EVFLAGCLR_RESEC3_Pos)                    /*!< DSD EVFLAGCLR: RESEC3 Mask              */\r
+#define DSD_EVFLAGCLR_ALEC0_Pos               16                                                      /*!< DSD EVFLAGCLR: ALEC0 Position           */\r
+#define DSD_EVFLAGCLR_ALEC0_Msk               (0x01UL << DSD_EVFLAGCLR_ALEC0_Pos)                     /*!< DSD EVFLAGCLR: ALEC0 Mask               */\r
+#define DSD_EVFLAGCLR_ALEC1_Pos               17                                                      /*!< DSD EVFLAGCLR: ALEC1 Position           */\r
+#define DSD_EVFLAGCLR_ALEC1_Msk               (0x01UL << DSD_EVFLAGCLR_ALEC1_Pos)                     /*!< DSD EVFLAGCLR: ALEC1 Mask               */\r
+#define DSD_EVFLAGCLR_ALEC2_Pos               18                                                      /*!< DSD EVFLAGCLR: ALEC2 Position           */\r
+#define DSD_EVFLAGCLR_ALEC2_Msk               (0x01UL << DSD_EVFLAGCLR_ALEC2_Pos)                     /*!< DSD EVFLAGCLR: ALEC2 Mask               */\r
+#define DSD_EVFLAGCLR_ALEC3_Pos               19                                                      /*!< DSD EVFLAGCLR: ALEC3 Position           */\r
+#define DSD_EVFLAGCLR_ALEC3_Msk               (0x01UL << DSD_EVFLAGCLR_ALEC3_Pos)                     /*!< DSD EVFLAGCLR: ALEC3 Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'DSD_CH' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  DSD_CH_MODCFG  ------------------------------- */\r
+#define DSD_CH_MODCFG_DIVM_Pos                16                                                      /*!< DSD_CH MODCFG: DIVM Position            */\r
+#define DSD_CH_MODCFG_DIVM_Msk                (0x0fUL << DSD_CH_MODCFG_DIVM_Pos)                      /*!< DSD_CH MODCFG: DIVM Mask                */\r
+#define DSD_CH_MODCFG_DWC_Pos                 23                                                      /*!< DSD_CH MODCFG: DWC Position             */\r
+#define DSD_CH_MODCFG_DWC_Msk                 (0x01UL << DSD_CH_MODCFG_DWC_Pos)                       /*!< DSD_CH MODCFG: DWC Mask                 */\r
+\r
+/* --------------------------------  DSD_CH_DICFG  -------------------------------- */\r
+#define DSD_CH_DICFG_DSRC_Pos                 0                                                       /*!< DSD_CH DICFG: DSRC Position             */\r
+#define DSD_CH_DICFG_DSRC_Msk                 (0x0fUL << DSD_CH_DICFG_DSRC_Pos)                       /*!< DSD_CH DICFG: DSRC Mask                 */\r
+#define DSD_CH_DICFG_DSWC_Pos                 7                                                       /*!< DSD_CH DICFG: DSWC Position             */\r
+#define DSD_CH_DICFG_DSWC_Msk                 (0x01UL << DSD_CH_DICFG_DSWC_Pos)                       /*!< DSD_CH DICFG: DSWC Mask                 */\r
+#define DSD_CH_DICFG_ITRMODE_Pos              8                                                       /*!< DSD_CH DICFG: ITRMODE Position          */\r
+#define DSD_CH_DICFG_ITRMODE_Msk              (0x03UL << DSD_CH_DICFG_ITRMODE_Pos)                    /*!< DSD_CH DICFG: ITRMODE Mask              */\r
+#define DSD_CH_DICFG_TSTRMODE_Pos             10                                                      /*!< DSD_CH DICFG: TSTRMODE Position         */\r
+#define DSD_CH_DICFG_TSTRMODE_Msk             (0x03UL << DSD_CH_DICFG_TSTRMODE_Pos)                   /*!< DSD_CH DICFG: TSTRMODE Mask             */\r
+#define DSD_CH_DICFG_TRSEL_Pos                12                                                      /*!< DSD_CH DICFG: TRSEL Position            */\r
+#define DSD_CH_DICFG_TRSEL_Msk                (0x07UL << DSD_CH_DICFG_TRSEL_Pos)                      /*!< DSD_CH DICFG: TRSEL Mask                */\r
+#define DSD_CH_DICFG_TRWC_Pos                 15                                                      /*!< DSD_CH DICFG: TRWC Position             */\r
+#define DSD_CH_DICFG_TRWC_Msk                 (0x01UL << DSD_CH_DICFG_TRWC_Pos)                       /*!< DSD_CH DICFG: TRWC Mask                 */\r
+#define DSD_CH_DICFG_CSRC_Pos                 16                                                      /*!< DSD_CH DICFG: CSRC Position             */\r
+#define DSD_CH_DICFG_CSRC_Msk                 (0x0fUL << DSD_CH_DICFG_CSRC_Pos)                       /*!< DSD_CH DICFG: CSRC Mask                 */\r
+#define DSD_CH_DICFG_STROBE_Pos               20                                                      /*!< DSD_CH DICFG: STROBE Position           */\r
+#define DSD_CH_DICFG_STROBE_Msk               (0x0fUL << DSD_CH_DICFG_STROBE_Pos)                     /*!< DSD_CH DICFG: STROBE Mask               */\r
+#define DSD_CH_DICFG_SCWC_Pos                 31                                                      /*!< DSD_CH DICFG: SCWC Position             */\r
+#define DSD_CH_DICFG_SCWC_Msk                 (0x01UL << DSD_CH_DICFG_SCWC_Pos)                       /*!< DSD_CH DICFG: SCWC Mask                 */\r
+\r
+/* --------------------------------  DSD_CH_FCFGC  -------------------------------- */\r
+#define DSD_CH_FCFGC_CFMDF_Pos                0                                                       /*!< DSD_CH FCFGC: CFMDF Position            */\r
+#define DSD_CH_FCFGC_CFMDF_Msk                (0x000000ffUL << DSD_CH_FCFGC_CFMDF_Pos)                /*!< DSD_CH FCFGC: CFMDF Mask                */\r
+#define DSD_CH_FCFGC_CFMC_Pos                 8                                                       /*!< DSD_CH FCFGC: CFMC Position             */\r
+#define DSD_CH_FCFGC_CFMC_Msk                 (0x03UL << DSD_CH_FCFGC_CFMC_Pos)                       /*!< DSD_CH FCFGC: CFMC Mask                 */\r
+#define DSD_CH_FCFGC_CFEN_Pos                 10                                                      /*!< DSD_CH FCFGC: CFEN Position             */\r
+#define DSD_CH_FCFGC_CFEN_Msk                 (0x01UL << DSD_CH_FCFGC_CFEN_Pos)                       /*!< DSD_CH FCFGC: CFEN Mask                 */\r
+#define DSD_CH_FCFGC_SRGM_Pos                 14                                                      /*!< DSD_CH FCFGC: SRGM Position             */\r
+#define DSD_CH_FCFGC_SRGM_Msk                 (0x03UL << DSD_CH_FCFGC_SRGM_Pos)                       /*!< DSD_CH FCFGC: SRGM Mask                 */\r
+#define DSD_CH_FCFGC_CFMSV_Pos                16                                                      /*!< DSD_CH FCFGC: CFMSV Position            */\r
+#define DSD_CH_FCFGC_CFMSV_Msk                (0x000000ffUL << DSD_CH_FCFGC_CFMSV_Pos)                /*!< DSD_CH FCFGC: CFMSV Mask                */\r
+#define DSD_CH_FCFGC_CFMDCNT_Pos              24                                                      /*!< DSD_CH FCFGC: CFMDCNT Position          */\r
+#define DSD_CH_FCFGC_CFMDCNT_Msk              (0x000000ffUL << DSD_CH_FCFGC_CFMDCNT_Pos)              /*!< DSD_CH FCFGC: CFMDCNT Mask              */\r
+\r
+/* --------------------------------  DSD_CH_FCFGA  -------------------------------- */\r
+#define DSD_CH_FCFGA_CFADF_Pos                0                                                       /*!< DSD_CH FCFGA: CFADF Position            */\r
+#define DSD_CH_FCFGA_CFADF_Msk                (0x000000ffUL << DSD_CH_FCFGA_CFADF_Pos)                /*!< DSD_CH FCFGA: CFADF Mask                */\r
+#define DSD_CH_FCFGA_CFAC_Pos                 8                                                       /*!< DSD_CH FCFGA: CFAC Position             */\r
+#define DSD_CH_FCFGA_CFAC_Msk                 (0x03UL << DSD_CH_FCFGA_CFAC_Pos)                       /*!< DSD_CH FCFGA: CFAC Mask                 */\r
+#define DSD_CH_FCFGA_SRGA_Pos                 10                                                      /*!< DSD_CH FCFGA: SRGA Position             */\r
+#define DSD_CH_FCFGA_SRGA_Msk                 (0x03UL << DSD_CH_FCFGA_SRGA_Pos)                       /*!< DSD_CH FCFGA: SRGA Mask                 */\r
+#define DSD_CH_FCFGA_ESEL_Pos                 12                                                      /*!< DSD_CH FCFGA: ESEL Position             */\r
+#define DSD_CH_FCFGA_ESEL_Msk                 (0x03UL << DSD_CH_FCFGA_ESEL_Pos)                       /*!< DSD_CH FCFGA: ESEL Mask                 */\r
+#define DSD_CH_FCFGA_EGT_Pos                  14                                                      /*!< DSD_CH FCFGA: EGT Position              */\r
+#define DSD_CH_FCFGA_EGT_Msk                  (0x01UL << DSD_CH_FCFGA_EGT_Pos)                        /*!< DSD_CH FCFGA: EGT Mask                  */\r
+#define DSD_CH_FCFGA_CFADCNT_Pos              24                                                      /*!< DSD_CH FCFGA: CFADCNT Position          */\r
+#define DSD_CH_FCFGA_CFADCNT_Msk              (0x000000ffUL << DSD_CH_FCFGA_CFADCNT_Pos)              /*!< DSD_CH FCFGA: CFADCNT Mask              */\r
+\r
+/* --------------------------------  DSD_CH_IWCTR  -------------------------------- */\r
+#define DSD_CH_IWCTR_NVALCNT_Pos              0                                                       /*!< DSD_CH IWCTR: NVALCNT Position          */\r
+#define DSD_CH_IWCTR_NVALCNT_Msk              (0x3fUL << DSD_CH_IWCTR_NVALCNT_Pos)                    /*!< DSD_CH IWCTR: NVALCNT Mask              */\r
+#define DSD_CH_IWCTR_INTEN_Pos                7                                                       /*!< DSD_CH IWCTR: INTEN Position            */\r
+#define DSD_CH_IWCTR_INTEN_Msk                (0x01UL << DSD_CH_IWCTR_INTEN_Pos)                      /*!< DSD_CH IWCTR: INTEN Mask                */\r
+#define DSD_CH_IWCTR_REPCNT_Pos               8                                                       /*!< DSD_CH IWCTR: REPCNT Position           */\r
+#define DSD_CH_IWCTR_REPCNT_Msk               (0x0fUL << DSD_CH_IWCTR_REPCNT_Pos)                     /*!< DSD_CH IWCTR: REPCNT Mask               */\r
+#define DSD_CH_IWCTR_REPVAL_Pos               12                                                      /*!< DSD_CH IWCTR: REPVAL Position           */\r
+#define DSD_CH_IWCTR_REPVAL_Msk               (0x0fUL << DSD_CH_IWCTR_REPVAL_Pos)                     /*!< DSD_CH IWCTR: REPVAL Mask               */\r
+#define DSD_CH_IWCTR_NVALDIS_Pos              16                                                      /*!< DSD_CH IWCTR: NVALDIS Position          */\r
+#define DSD_CH_IWCTR_NVALDIS_Msk              (0x3fUL << DSD_CH_IWCTR_NVALDIS_Pos)                    /*!< DSD_CH IWCTR: NVALDIS Mask              */\r
+#define DSD_CH_IWCTR_IWS_Pos                  23                                                      /*!< DSD_CH IWCTR: IWS Position              */\r
+#define DSD_CH_IWCTR_IWS_Msk                  (0x01UL << DSD_CH_IWCTR_IWS_Pos)                        /*!< DSD_CH IWCTR: IWS Mask                  */\r
+#define DSD_CH_IWCTR_NVALINT_Pos              24                                                      /*!< DSD_CH IWCTR: NVALINT Position          */\r
+#define DSD_CH_IWCTR_NVALINT_Msk              (0x3fUL << DSD_CH_IWCTR_NVALINT_Pos)                    /*!< DSD_CH IWCTR: NVALINT Mask              */\r
+\r
+/* -------------------------------  DSD_CH_BOUNDSEL  ------------------------------ */\r
+#define DSD_CH_BOUNDSEL_BOUNDARYL_Pos         0                                                       /*!< DSD_CH BOUNDSEL: BOUNDARYL Position     */\r
+#define DSD_CH_BOUNDSEL_BOUNDARYL_Msk         (0x0000ffffUL << DSD_CH_BOUNDSEL_BOUNDARYL_Pos)         /*!< DSD_CH BOUNDSEL: BOUNDARYL Mask         */\r
+#define DSD_CH_BOUNDSEL_BOUNDARYU_Pos         16                                                      /*!< DSD_CH BOUNDSEL: BOUNDARYU Position     */\r
+#define DSD_CH_BOUNDSEL_BOUNDARYU_Msk         (0x0000ffffUL << DSD_CH_BOUNDSEL_BOUNDARYU_Pos)         /*!< DSD_CH BOUNDSEL: BOUNDARYU Mask         */\r
+\r
+/* ---------------------------------  DSD_CH_RESM  -------------------------------- */\r
+#define DSD_CH_RESM_RESULT_Pos                0                                                       /*!< DSD_CH RESM: RESULT Position            */\r
+#define DSD_CH_RESM_RESULT_Msk                (0x0000ffffUL << DSD_CH_RESM_RESULT_Pos)                /*!< DSD_CH RESM: RESULT Mask                */\r
+\r
+/* ---------------------------------  DSD_CH_OFFM  -------------------------------- */\r
+#define DSD_CH_OFFM_OFFSET_Pos                0                                                       /*!< DSD_CH OFFM: OFFSET Position            */\r
+#define DSD_CH_OFFM_OFFSET_Msk                (0x0000ffffUL << DSD_CH_OFFM_OFFSET_Pos)                /*!< DSD_CH OFFM: OFFSET Mask                */\r
+\r
+/* ---------------------------------  DSD_CH_RESA  -------------------------------- */\r
+#define DSD_CH_RESA_RESULT_Pos                0                                                       /*!< DSD_CH RESA: RESULT Position            */\r
+#define DSD_CH_RESA_RESULT_Msk                (0x0000ffffUL << DSD_CH_RESA_RESULT_Pos)                /*!< DSD_CH RESA: RESULT Mask                */\r
+\r
+/* --------------------------------  DSD_CH_TSTMP  -------------------------------- */\r
+#define DSD_CH_TSTMP_RESULT_Pos               0                                                       /*!< DSD_CH TSTMP: RESULT Position           */\r
+#define DSD_CH_TSTMP_RESULT_Msk               (0x0000ffffUL << DSD_CH_TSTMP_RESULT_Pos)               /*!< DSD_CH TSTMP: RESULT Mask               */\r
+#define DSD_CH_TSTMP_CFMDCNT_Pos              16                                                      /*!< DSD_CH TSTMP: CFMDCNT Position          */\r
+#define DSD_CH_TSTMP_CFMDCNT_Msk              (0x000000ffUL << DSD_CH_TSTMP_CFMDCNT_Pos)              /*!< DSD_CH TSTMP: CFMDCNT Mask              */\r
+#define DSD_CH_TSTMP_NVALCNT_Pos              24                                                      /*!< DSD_CH TSTMP: NVALCNT Position          */\r
+#define DSD_CH_TSTMP_NVALCNT_Msk              (0x3fUL << DSD_CH_TSTMP_NVALCNT_Pos)                    /*!< DSD_CH TSTMP: NVALCNT Mask              */\r
+\r
+/* --------------------------------  DSD_CH_CGSYNC  ------------------------------- */\r
+#define DSD_CH_CGSYNC_SDCOUNT_Pos             0                                                       /*!< DSD_CH CGSYNC: SDCOUNT Position         */\r
+#define DSD_CH_CGSYNC_SDCOUNT_Msk             (0x000000ffUL << DSD_CH_CGSYNC_SDCOUNT_Pos)             /*!< DSD_CH CGSYNC: SDCOUNT Mask             */\r
+#define DSD_CH_CGSYNC_SDCAP_Pos               8                                                       /*!< DSD_CH CGSYNC: SDCAP Position           */\r
+#define DSD_CH_CGSYNC_SDCAP_Msk               (0x000000ffUL << DSD_CH_CGSYNC_SDCAP_Pos)               /*!< DSD_CH CGSYNC: SDCAP Mask               */\r
+#define DSD_CH_CGSYNC_SDPOS_Pos               16                                                      /*!< DSD_CH CGSYNC: SDPOS Position           */\r
+#define DSD_CH_CGSYNC_SDPOS_Msk               (0x000000ffUL << DSD_CH_CGSYNC_SDPOS_Pos)               /*!< DSD_CH CGSYNC: SDPOS Mask               */\r
+#define DSD_CH_CGSYNC_SDNEG_Pos               24                                                      /*!< DSD_CH CGSYNC: SDNEG Position           */\r
+#define DSD_CH_CGSYNC_SDNEG_Msk               (0x000000ffUL << DSD_CH_CGSYNC_SDNEG_Pos)               /*!< DSD_CH CGSYNC: SDNEG Mask               */\r
+\r
+/* -------------------------------  DSD_CH_RECTCFG  ------------------------------- */\r
+#define DSD_CH_RECTCFG_RFEN_Pos               0                                                       /*!< DSD_CH RECTCFG: RFEN Position           */\r
+#define DSD_CH_RECTCFG_RFEN_Msk               (0x01UL << DSD_CH_RECTCFG_RFEN_Pos)                     /*!< DSD_CH RECTCFG: RFEN Mask               */\r
+#define DSD_CH_RECTCFG_SSRC_Pos               4                                                       /*!< DSD_CH RECTCFG: SSRC Position           */\r
+#define DSD_CH_RECTCFG_SSRC_Msk               (0x03UL << DSD_CH_RECTCFG_SSRC_Pos)                     /*!< DSD_CH RECTCFG: SSRC Mask               */\r
+#define DSD_CH_RECTCFG_SDVAL_Pos              15                                                      /*!< DSD_CH RECTCFG: SDVAL Position          */\r
+#define DSD_CH_RECTCFG_SDVAL_Msk              (0x01UL << DSD_CH_RECTCFG_SDVAL_Pos)                    /*!< DSD_CH RECTCFG: SDVAL Mask              */\r
+#define DSD_CH_RECTCFG_SGNCS_Pos              30                                                      /*!< DSD_CH RECTCFG: SGNCS Position          */\r
+#define DSD_CH_RECTCFG_SGNCS_Msk              (0x01UL << DSD_CH_RECTCFG_SGNCS_Pos)                    /*!< DSD_CH RECTCFG: SGNCS Mask              */\r
+#define DSD_CH_RECTCFG_SGND_Pos               31                                                      /*!< DSD_CH RECTCFG: SGND Position           */\r
+#define DSD_CH_RECTCFG_SGND_Msk               (0x01UL << DSD_CH_RECTCFG_SGND_Pos)                     /*!< DSD_CH RECTCFG: SGND Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'DAC' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  DAC_ID  ----------------------------------- */\r
+#define DAC_ID_MODR_Pos                       0                                                       /*!< DAC ID: MODR Position                   */\r
+#define DAC_ID_MODR_Msk                       (0x000000ffUL << DAC_ID_MODR_Pos)                       /*!< DAC ID: MODR Mask                       */\r
+#define DAC_ID_MODT_Pos                       8                                                       /*!< DAC ID: MODT Position                   */\r
+#define DAC_ID_MODT_Msk                       (0x000000ffUL << DAC_ID_MODT_Pos)                       /*!< DAC ID: MODT Mask                       */\r
+#define DAC_ID_MODN_Pos                       16                                                      /*!< DAC ID: MODN Position                   */\r
+#define DAC_ID_MODN_Msk                       (0x0000ffffUL << DAC_ID_MODN_Pos)                       /*!< DAC ID: MODN Mask                       */\r
+\r
+/* --------------------------------  DAC_DAC0CFG0  -------------------------------- */\r
+#define DAC_DAC0CFG0_FREQ_Pos                 0                                                       /*!< DAC DAC0CFG0: FREQ Position             */\r
+#define DAC_DAC0CFG0_FREQ_Msk                 (0x000fffffUL << DAC_DAC0CFG0_FREQ_Pos)                 /*!< DAC DAC0CFG0: FREQ Mask                 */\r
+#define DAC_DAC0CFG0_MODE_Pos                 20                                                      /*!< DAC DAC0CFG0: MODE Position             */\r
+#define DAC_DAC0CFG0_MODE_Msk                 (0x07UL << DAC_DAC0CFG0_MODE_Pos)                       /*!< DAC DAC0CFG0: MODE Mask                 */\r
+#define DAC_DAC0CFG0_SIGN_Pos                 23                                                      /*!< DAC DAC0CFG0: SIGN Position             */\r
+#define DAC_DAC0CFG0_SIGN_Msk                 (0x01UL << DAC_DAC0CFG0_SIGN_Pos)                       /*!< DAC DAC0CFG0: SIGN Mask                 */\r
+#define DAC_DAC0CFG0_FIFOIND_Pos              24                                                      /*!< DAC DAC0CFG0: FIFOIND Position          */\r
+#define DAC_DAC0CFG0_FIFOIND_Msk              (0x03UL << DAC_DAC0CFG0_FIFOIND_Pos)                    /*!< DAC DAC0CFG0: FIFOIND Mask              */\r
+#define DAC_DAC0CFG0_FIFOEMP_Pos              26                                                      /*!< DAC DAC0CFG0: FIFOEMP Position          */\r
+#define DAC_DAC0CFG0_FIFOEMP_Msk              (0x01UL << DAC_DAC0CFG0_FIFOEMP_Pos)                    /*!< DAC DAC0CFG0: FIFOEMP Mask              */\r
+#define DAC_DAC0CFG0_FIFOFUL_Pos              27                                                      /*!< DAC DAC0CFG0: FIFOFUL Position          */\r
+#define DAC_DAC0CFG0_FIFOFUL_Msk              (0x01UL << DAC_DAC0CFG0_FIFOFUL_Pos)                    /*!< DAC DAC0CFG0: FIFOFUL Mask              */\r
+#define DAC_DAC0CFG0_SIGNEN_Pos               29                                                      /*!< DAC DAC0CFG0: SIGNEN Position           */\r
+#define DAC_DAC0CFG0_SIGNEN_Msk               (0x01UL << DAC_DAC0CFG0_SIGNEN_Pos)                     /*!< DAC DAC0CFG0: SIGNEN Mask               */\r
+#define DAC_DAC0CFG0_SREN_Pos                 30                                                      /*!< DAC DAC0CFG0: SREN Position             */\r
+#define DAC_DAC0CFG0_SREN_Msk                 (0x01UL << DAC_DAC0CFG0_SREN_Pos)                       /*!< DAC DAC0CFG0: SREN Mask                 */\r
+#define DAC_DAC0CFG0_RUN_Pos                  31                                                      /*!< DAC DAC0CFG0: RUN Position              */\r
+#define DAC_DAC0CFG0_RUN_Msk                  (0x01UL << DAC_DAC0CFG0_RUN_Pos)                        /*!< DAC DAC0CFG0: RUN Mask                  */\r
+\r
+/* --------------------------------  DAC_DAC0CFG1  -------------------------------- */\r
+#define DAC_DAC0CFG1_SCALE_Pos                0                                                       /*!< DAC DAC0CFG1: SCALE Position            */\r
+#define DAC_DAC0CFG1_SCALE_Msk                (0x07UL << DAC_DAC0CFG1_SCALE_Pos)                      /*!< DAC DAC0CFG1: SCALE Mask                */\r
+#define DAC_DAC0CFG1_MULDIV_Pos               3                                                       /*!< DAC DAC0CFG1: MULDIV Position           */\r
+#define DAC_DAC0CFG1_MULDIV_Msk               (0x01UL << DAC_DAC0CFG1_MULDIV_Pos)                     /*!< DAC DAC0CFG1: MULDIV Mask               */\r
+#define DAC_DAC0CFG1_OFFS_Pos                 4                                                       /*!< DAC DAC0CFG1: OFFS Position             */\r
+#define DAC_DAC0CFG1_OFFS_Msk                 (0x000000ffUL << DAC_DAC0CFG1_OFFS_Pos)                 /*!< DAC DAC0CFG1: OFFS Mask                 */\r
+#define DAC_DAC0CFG1_TRIGSEL_Pos              12                                                      /*!< DAC DAC0CFG1: TRIGSEL Position          */\r
+#define DAC_DAC0CFG1_TRIGSEL_Msk              (0x07UL << DAC_DAC0CFG1_TRIGSEL_Pos)                    /*!< DAC DAC0CFG1: TRIGSEL Mask              */\r
+#define DAC_DAC0CFG1_DATMOD_Pos               15                                                      /*!< DAC DAC0CFG1: DATMOD Position           */\r
+#define DAC_DAC0CFG1_DATMOD_Msk               (0x01UL << DAC_DAC0CFG1_DATMOD_Pos)                     /*!< DAC DAC0CFG1: DATMOD Mask               */\r
+#define DAC_DAC0CFG1_SWTRIG_Pos               16                                                      /*!< DAC DAC0CFG1: SWTRIG Position           */\r
+#define DAC_DAC0CFG1_SWTRIG_Msk               (0x01UL << DAC_DAC0CFG1_SWTRIG_Pos)                     /*!< DAC DAC0CFG1: SWTRIG Mask               */\r
+#define DAC_DAC0CFG1_TRIGMOD_Pos              17                                                      /*!< DAC DAC0CFG1: TRIGMOD Position          */\r
+#define DAC_DAC0CFG1_TRIGMOD_Msk              (0x03UL << DAC_DAC0CFG1_TRIGMOD_Pos)                    /*!< DAC DAC0CFG1: TRIGMOD Mask              */\r
+#define DAC_DAC0CFG1_ANACFG_Pos               19                                                      /*!< DAC DAC0CFG1: ANACFG Position           */\r
+#define DAC_DAC0CFG1_ANACFG_Msk               (0x1fUL << DAC_DAC0CFG1_ANACFG_Pos)                     /*!< DAC DAC0CFG1: ANACFG Mask               */\r
+#define DAC_DAC0CFG1_ANAEN_Pos                24                                                      /*!< DAC DAC0CFG1: ANAEN Position            */\r
+#define DAC_DAC0CFG1_ANAEN_Msk                (0x01UL << DAC_DAC0CFG1_ANAEN_Pos)                      /*!< DAC DAC0CFG1: ANAEN Mask                */\r
+#define DAC_DAC0CFG1_REFCFGL_Pos              28                                                      /*!< DAC DAC0CFG1: REFCFGL Position          */\r
+#define DAC_DAC0CFG1_REFCFGL_Msk              (0x0fUL << DAC_DAC0CFG1_REFCFGL_Pos)                    /*!< DAC DAC0CFG1: REFCFGL Mask              */\r
+\r
+/* --------------------------------  DAC_DAC1CFG0  -------------------------------- */\r
+#define DAC_DAC1CFG0_FREQ_Pos                 0                                                       /*!< DAC DAC1CFG0: FREQ Position             */\r
+#define DAC_DAC1CFG0_FREQ_Msk                 (0x000fffffUL << DAC_DAC1CFG0_FREQ_Pos)                 /*!< DAC DAC1CFG0: FREQ Mask                 */\r
+#define DAC_DAC1CFG0_MODE_Pos                 20                                                      /*!< DAC DAC1CFG0: MODE Position             */\r
+#define DAC_DAC1CFG0_MODE_Msk                 (0x07UL << DAC_DAC1CFG0_MODE_Pos)                       /*!< DAC DAC1CFG0: MODE Mask                 */\r
+#define DAC_DAC1CFG0_SIGN_Pos                 23                                                      /*!< DAC DAC1CFG0: SIGN Position             */\r
+#define DAC_DAC1CFG0_SIGN_Msk                 (0x01UL << DAC_DAC1CFG0_SIGN_Pos)                       /*!< DAC DAC1CFG0: SIGN Mask                 */\r
+#define DAC_DAC1CFG0_FIFOIND_Pos              24                                                      /*!< DAC DAC1CFG0: FIFOIND Position          */\r
+#define DAC_DAC1CFG0_FIFOIND_Msk              (0x03UL << DAC_DAC1CFG0_FIFOIND_Pos)                    /*!< DAC DAC1CFG0: FIFOIND Mask              */\r
+#define DAC_DAC1CFG0_FIFOEMP_Pos              26                                                      /*!< DAC DAC1CFG0: FIFOEMP Position          */\r
+#define DAC_DAC1CFG0_FIFOEMP_Msk              (0x01UL << DAC_DAC1CFG0_FIFOEMP_Pos)                    /*!< DAC DAC1CFG0: FIFOEMP Mask              */\r
+#define DAC_DAC1CFG0_FIFOFUL_Pos              27                                                      /*!< DAC DAC1CFG0: FIFOFUL Position          */\r
+#define DAC_DAC1CFG0_FIFOFUL_Msk              (0x01UL << DAC_DAC1CFG0_FIFOFUL_Pos)                    /*!< DAC DAC1CFG0: FIFOFUL Mask              */\r
+#define DAC_DAC1CFG0_SIGNEN_Pos               29                                                      /*!< DAC DAC1CFG0: SIGNEN Position           */\r
+#define DAC_DAC1CFG0_SIGNEN_Msk               (0x01UL << DAC_DAC1CFG0_SIGNEN_Pos)                     /*!< DAC DAC1CFG0: SIGNEN Mask               */\r
+#define DAC_DAC1CFG0_SREN_Pos                 30                                                      /*!< DAC DAC1CFG0: SREN Position             */\r
+#define DAC_DAC1CFG0_SREN_Msk                 (0x01UL << DAC_DAC1CFG0_SREN_Pos)                       /*!< DAC DAC1CFG0: SREN Mask                 */\r
+#define DAC_DAC1CFG0_RUN_Pos                  31                                                      /*!< DAC DAC1CFG0: RUN Position              */\r
+#define DAC_DAC1CFG0_RUN_Msk                  (0x01UL << DAC_DAC1CFG0_RUN_Pos)                        /*!< DAC DAC1CFG0: RUN Mask                  */\r
+\r
+/* --------------------------------  DAC_DAC1CFG1  -------------------------------- */\r
+#define DAC_DAC1CFG1_SCALE_Pos                0                                                       /*!< DAC DAC1CFG1: SCALE Position            */\r
+#define DAC_DAC1CFG1_SCALE_Msk                (0x07UL << DAC_DAC1CFG1_SCALE_Pos)                      /*!< DAC DAC1CFG1: SCALE Mask                */\r
+#define DAC_DAC1CFG1_MULDIV_Pos               3                                                       /*!< DAC DAC1CFG1: MULDIV Position           */\r
+#define DAC_DAC1CFG1_MULDIV_Msk               (0x01UL << DAC_DAC1CFG1_MULDIV_Pos)                     /*!< DAC DAC1CFG1: MULDIV Mask               */\r
+#define DAC_DAC1CFG1_OFFS_Pos                 4                                                       /*!< DAC DAC1CFG1: OFFS Position             */\r
+#define DAC_DAC1CFG1_OFFS_Msk                 (0x000000ffUL << DAC_DAC1CFG1_OFFS_Pos)                 /*!< DAC DAC1CFG1: OFFS Mask                 */\r
+#define DAC_DAC1CFG1_TRIGSEL_Pos              12                                                      /*!< DAC DAC1CFG1: TRIGSEL Position          */\r
+#define DAC_DAC1CFG1_TRIGSEL_Msk              (0x07UL << DAC_DAC1CFG1_TRIGSEL_Pos)                    /*!< DAC DAC1CFG1: TRIGSEL Mask              */\r
+#define DAC_DAC1CFG1_SWTRIG_Pos               16                                                      /*!< DAC DAC1CFG1: SWTRIG Position           */\r
+#define DAC_DAC1CFG1_SWTRIG_Msk               (0x01UL << DAC_DAC1CFG1_SWTRIG_Pos)                     /*!< DAC DAC1CFG1: SWTRIG Mask               */\r
+#define DAC_DAC1CFG1_TRIGMOD_Pos              17                                                      /*!< DAC DAC1CFG1: TRIGMOD Position          */\r
+#define DAC_DAC1CFG1_TRIGMOD_Msk              (0x03UL << DAC_DAC1CFG1_TRIGMOD_Pos)                    /*!< DAC DAC1CFG1: TRIGMOD Mask              */\r
+#define DAC_DAC1CFG1_ANACFG_Pos               19                                                      /*!< DAC DAC1CFG1: ANACFG Position           */\r
+#define DAC_DAC1CFG1_ANACFG_Msk               (0x1fUL << DAC_DAC1CFG1_ANACFG_Pos)                     /*!< DAC DAC1CFG1: ANACFG Mask               */\r
+#define DAC_DAC1CFG1_ANAEN_Pos                24                                                      /*!< DAC DAC1CFG1: ANAEN Position            */\r
+#define DAC_DAC1CFG1_ANAEN_Msk                (0x01UL << DAC_DAC1CFG1_ANAEN_Pos)                      /*!< DAC DAC1CFG1: ANAEN Mask                */\r
+#define DAC_DAC1CFG1_REFCFGH_Pos              28                                                      /*!< DAC DAC1CFG1: REFCFGH Position          */\r
+#define DAC_DAC1CFG1_REFCFGH_Msk              (0x0fUL << DAC_DAC1CFG1_REFCFGH_Pos)                    /*!< DAC DAC1CFG1: REFCFGH Mask              */\r
+\r
+/* --------------------------------  DAC_DAC0DATA  -------------------------------- */\r
+#define DAC_DAC0DATA_DATA0_Pos                0                                                       /*!< DAC DAC0DATA: DATA0 Position            */\r
+#define DAC_DAC0DATA_DATA0_Msk                (0x00000fffUL << DAC_DAC0DATA_DATA0_Pos)                /*!< DAC DAC0DATA: DATA0 Mask                */\r
+\r
+/* --------------------------------  DAC_DAC1DATA  -------------------------------- */\r
+#define DAC_DAC1DATA_DATA1_Pos                0                                                       /*!< DAC DAC1DATA: DATA1 Position            */\r
+#define DAC_DAC1DATA_DATA1_Msk                (0x00000fffUL << DAC_DAC1DATA_DATA1_Pos)                /*!< DAC DAC1DATA: DATA1 Mask                */\r
+\r
+/* --------------------------------  DAC_DAC01DATA  ------------------------------- */\r
+#define DAC_DAC01DATA_DATA0_Pos               0                                                       /*!< DAC DAC01DATA: DATA0 Position           */\r
+#define DAC_DAC01DATA_DATA0_Msk               (0x00000fffUL << DAC_DAC01DATA_DATA0_Pos)               /*!< DAC DAC01DATA: DATA0 Mask               */\r
+#define DAC_DAC01DATA_DATA1_Pos               16                                                      /*!< DAC DAC01DATA: DATA1 Position           */\r
+#define DAC_DAC01DATA_DATA1_Msk               (0x00000fffUL << DAC_DAC01DATA_DATA1_Pos)               /*!< DAC DAC01DATA: DATA1 Mask               */\r
+\r
+/* --------------------------------  DAC_DAC0PATL  -------------------------------- */\r
+#define DAC_DAC0PATL_PAT0_Pos                 0                                                       /*!< DAC DAC0PATL: PAT0 Position             */\r
+#define DAC_DAC0PATL_PAT0_Msk                 (0x1fUL << DAC_DAC0PATL_PAT0_Pos)                       /*!< DAC DAC0PATL: PAT0 Mask                 */\r
+#define DAC_DAC0PATL_PAT1_Pos                 5                                                       /*!< DAC DAC0PATL: PAT1 Position             */\r
+#define DAC_DAC0PATL_PAT1_Msk                 (0x1fUL << DAC_DAC0PATL_PAT1_Pos)                       /*!< DAC DAC0PATL: PAT1 Mask                 */\r
+#define DAC_DAC0PATL_PAT2_Pos                 10                                                      /*!< DAC DAC0PATL: PAT2 Position             */\r
+#define DAC_DAC0PATL_PAT2_Msk                 (0x1fUL << DAC_DAC0PATL_PAT2_Pos)                       /*!< DAC DAC0PATL: PAT2 Mask                 */\r
+#define DAC_DAC0PATL_PAT3_Pos                 15                                                      /*!< DAC DAC0PATL: PAT3 Position             */\r
+#define DAC_DAC0PATL_PAT3_Msk                 (0x1fUL << DAC_DAC0PATL_PAT3_Pos)                       /*!< DAC DAC0PATL: PAT3 Mask                 */\r
+#define DAC_DAC0PATL_PAT4_Pos                 20                                                      /*!< DAC DAC0PATL: PAT4 Position             */\r
+#define DAC_DAC0PATL_PAT4_Msk                 (0x1fUL << DAC_DAC0PATL_PAT4_Pos)                       /*!< DAC DAC0PATL: PAT4 Mask                 */\r
+#define DAC_DAC0PATL_PAT5_Pos                 25                                                      /*!< DAC DAC0PATL: PAT5 Position             */\r
+#define DAC_DAC0PATL_PAT5_Msk                 (0x1fUL << DAC_DAC0PATL_PAT5_Pos)                       /*!< DAC DAC0PATL: PAT5 Mask                 */\r
+\r
+/* --------------------------------  DAC_DAC0PATH  -------------------------------- */\r
+#define DAC_DAC0PATH_PAT6_Pos                 0                                                       /*!< DAC DAC0PATH: PAT6 Position             */\r
+#define DAC_DAC0PATH_PAT6_Msk                 (0x1fUL << DAC_DAC0PATH_PAT6_Pos)                       /*!< DAC DAC0PATH: PAT6 Mask                 */\r
+#define DAC_DAC0PATH_PAT7_Pos                 5                                                       /*!< DAC DAC0PATH: PAT7 Position             */\r
+#define DAC_DAC0PATH_PAT7_Msk                 (0x1fUL << DAC_DAC0PATH_PAT7_Pos)                       /*!< DAC DAC0PATH: PAT7 Mask                 */\r
+#define DAC_DAC0PATH_PAT8_Pos                 10                                                      /*!< DAC DAC0PATH: PAT8 Position             */\r
+#define DAC_DAC0PATH_PAT8_Msk                 (0x1fUL << DAC_DAC0PATH_PAT8_Pos)                       /*!< DAC DAC0PATH: PAT8 Mask                 */\r
+\r
+/* --------------------------------  DAC_DAC1PATL  -------------------------------- */\r
+#define DAC_DAC1PATL_PAT0_Pos                 0                                                       /*!< DAC DAC1PATL: PAT0 Position             */\r
+#define DAC_DAC1PATL_PAT0_Msk                 (0x1fUL << DAC_DAC1PATL_PAT0_Pos)                       /*!< DAC DAC1PATL: PAT0 Mask                 */\r
+#define DAC_DAC1PATL_PAT1_Pos                 5                                                       /*!< DAC DAC1PATL: PAT1 Position             */\r
+#define DAC_DAC1PATL_PAT1_Msk                 (0x1fUL << DAC_DAC1PATL_PAT1_Pos)                       /*!< DAC DAC1PATL: PAT1 Mask                 */\r
+#define DAC_DAC1PATL_PAT2_Pos                 10                                                      /*!< DAC DAC1PATL: PAT2 Position             */\r
+#define DAC_DAC1PATL_PAT2_Msk                 (0x1fUL << DAC_DAC1PATL_PAT2_Pos)                       /*!< DAC DAC1PATL: PAT2 Mask                 */\r
+#define DAC_DAC1PATL_PAT3_Pos                 15                                                      /*!< DAC DAC1PATL: PAT3 Position             */\r
+#define DAC_DAC1PATL_PAT3_Msk                 (0x1fUL << DAC_DAC1PATL_PAT3_Pos)                       /*!< DAC DAC1PATL: PAT3 Mask                 */\r
+#define DAC_DAC1PATL_PAT4_Pos                 20                                                      /*!< DAC DAC1PATL: PAT4 Position             */\r
+#define DAC_DAC1PATL_PAT4_Msk                 (0x1fUL << DAC_DAC1PATL_PAT4_Pos)                       /*!< DAC DAC1PATL: PAT4 Mask                 */\r
+#define DAC_DAC1PATL_PAT5_Pos                 25                                                      /*!< DAC DAC1PATL: PAT5 Position             */\r
+#define DAC_DAC1PATL_PAT5_Msk                 (0x1fUL << DAC_DAC1PATL_PAT5_Pos)                       /*!< DAC DAC1PATL: PAT5 Mask                 */\r
+\r
+/* --------------------------------  DAC_DAC1PATH  -------------------------------- */\r
+#define DAC_DAC1PATH_PAT6_Pos                 0                                                       /*!< DAC DAC1PATH: PAT6 Position             */\r
+#define DAC_DAC1PATH_PAT6_Msk                 (0x1fUL << DAC_DAC1PATH_PAT6_Pos)                       /*!< DAC DAC1PATH: PAT6 Mask                 */\r
+#define DAC_DAC1PATH_PAT7_Pos                 5                                                       /*!< DAC DAC1PATH: PAT7 Position             */\r
+#define DAC_DAC1PATH_PAT7_Msk                 (0x1fUL << DAC_DAC1PATH_PAT7_Pos)                       /*!< DAC DAC1PATH: PAT7 Mask                 */\r
+#define DAC_DAC1PATH_PAT8_Pos                 10                                                      /*!< DAC DAC1PATH: PAT8 Position             */\r
+#define DAC_DAC1PATH_PAT8_Msk                 (0x1fUL << DAC_DAC1PATH_PAT8_Pos)                       /*!< DAC DAC1PATH: PAT8 Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'CCU4' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  CCU4_GCTRL  --------------------------------- */\r
+#define CCU4_GCTRL_PRBC_Pos                   0                                                       /*!< CCU4 GCTRL: PRBC Position               */\r
+#define CCU4_GCTRL_PRBC_Msk                   (0x07UL << CCU4_GCTRL_PRBC_Pos)                         /*!< CCU4 GCTRL: PRBC Mask                   */\r
+#define CCU4_GCTRL_PCIS_Pos                   4                                                       /*!< CCU4 GCTRL: PCIS Position               */\r
+#define CCU4_GCTRL_PCIS_Msk                   (0x03UL << CCU4_GCTRL_PCIS_Pos)                         /*!< CCU4 GCTRL: PCIS Mask                   */\r
+#define CCU4_GCTRL_SUSCFG_Pos                 8                                                       /*!< CCU4 GCTRL: SUSCFG Position             */\r
+#define CCU4_GCTRL_SUSCFG_Msk                 (0x03UL << CCU4_GCTRL_SUSCFG_Pos)                       /*!< CCU4 GCTRL: SUSCFG Mask                 */\r
+#define CCU4_GCTRL_MSE0_Pos                   10                                                      /*!< CCU4 GCTRL: MSE0 Position               */\r
+#define CCU4_GCTRL_MSE0_Msk                   (0x01UL << CCU4_GCTRL_MSE0_Pos)                         /*!< CCU4 GCTRL: MSE0 Mask                   */\r
+#define CCU4_GCTRL_MSE1_Pos                   11                                                      /*!< CCU4 GCTRL: MSE1 Position               */\r
+#define CCU4_GCTRL_MSE1_Msk                   (0x01UL << CCU4_GCTRL_MSE1_Pos)                         /*!< CCU4 GCTRL: MSE1 Mask                   */\r
+#define CCU4_GCTRL_MSE2_Pos                   12                                                      /*!< CCU4 GCTRL: MSE2 Position               */\r
+#define CCU4_GCTRL_MSE2_Msk                   (0x01UL << CCU4_GCTRL_MSE2_Pos)                         /*!< CCU4 GCTRL: MSE2 Mask                   */\r
+#define CCU4_GCTRL_MSE3_Pos                   13                                                      /*!< CCU4 GCTRL: MSE3 Position               */\r
+#define CCU4_GCTRL_MSE3_Msk                   (0x01UL << CCU4_GCTRL_MSE3_Pos)                         /*!< CCU4 GCTRL: MSE3 Mask                   */\r
+#define CCU4_GCTRL_MSDE_Pos                   14                                                      /*!< CCU4 GCTRL: MSDE Position               */\r
+#define CCU4_GCTRL_MSDE_Msk                   (0x03UL << CCU4_GCTRL_MSDE_Pos)                         /*!< CCU4 GCTRL: MSDE Mask                   */\r
+\r
+/* ---------------------------------  CCU4_GSTAT  --------------------------------- */\r
+#define CCU4_GSTAT_S0I_Pos                    0                                                       /*!< CCU4 GSTAT: S0I Position                */\r
+#define CCU4_GSTAT_S0I_Msk                    (0x01UL << CCU4_GSTAT_S0I_Pos)                          /*!< CCU4 GSTAT: S0I Mask                    */\r
+#define CCU4_GSTAT_S1I_Pos                    1                                                       /*!< CCU4 GSTAT: S1I Position                */\r
+#define CCU4_GSTAT_S1I_Msk                    (0x01UL << CCU4_GSTAT_S1I_Pos)                          /*!< CCU4 GSTAT: S1I Mask                    */\r
+#define CCU4_GSTAT_S2I_Pos                    2                                                       /*!< CCU4 GSTAT: S2I Position                */\r
+#define CCU4_GSTAT_S2I_Msk                    (0x01UL << CCU4_GSTAT_S2I_Pos)                          /*!< CCU4 GSTAT: S2I Mask                    */\r
+#define CCU4_GSTAT_S3I_Pos                    3                                                       /*!< CCU4 GSTAT: S3I Position                */\r
+#define CCU4_GSTAT_S3I_Msk                    (0x01UL << CCU4_GSTAT_S3I_Pos)                          /*!< CCU4 GSTAT: S3I Mask                    */\r
+#define CCU4_GSTAT_PRB_Pos                    8                                                       /*!< CCU4 GSTAT: PRB Position                */\r
+#define CCU4_GSTAT_PRB_Msk                    (0x01UL << CCU4_GSTAT_PRB_Pos)                          /*!< CCU4 GSTAT: PRB Mask                    */\r
+\r
+/* ---------------------------------  CCU4_GIDLS  --------------------------------- */\r
+#define CCU4_GIDLS_SS0I_Pos                   0                                                       /*!< CCU4 GIDLS: SS0I Position               */\r
+#define CCU4_GIDLS_SS0I_Msk                   (0x01UL << CCU4_GIDLS_SS0I_Pos)                         /*!< CCU4 GIDLS: SS0I Mask                   */\r
+#define CCU4_GIDLS_SS1I_Pos                   1                                                       /*!< CCU4 GIDLS: SS1I Position               */\r
+#define CCU4_GIDLS_SS1I_Msk                   (0x01UL << CCU4_GIDLS_SS1I_Pos)                         /*!< CCU4 GIDLS: SS1I Mask                   */\r
+#define CCU4_GIDLS_SS2I_Pos                   2                                                       /*!< CCU4 GIDLS: SS2I Position               */\r
+#define CCU4_GIDLS_SS2I_Msk                   (0x01UL << CCU4_GIDLS_SS2I_Pos)                         /*!< CCU4 GIDLS: SS2I Mask                   */\r
+#define CCU4_GIDLS_SS3I_Pos                   3                                                       /*!< CCU4 GIDLS: SS3I Position               */\r
+#define CCU4_GIDLS_SS3I_Msk                   (0x01UL << CCU4_GIDLS_SS3I_Pos)                         /*!< CCU4 GIDLS: SS3I Mask                   */\r
+#define CCU4_GIDLS_CPRB_Pos                   8                                                       /*!< CCU4 GIDLS: CPRB Position               */\r
+#define CCU4_GIDLS_CPRB_Msk                   (0x01UL << CCU4_GIDLS_CPRB_Pos)                         /*!< CCU4 GIDLS: CPRB Mask                   */\r
+#define CCU4_GIDLS_PSIC_Pos                   9                                                       /*!< CCU4 GIDLS: PSIC Position               */\r
+#define CCU4_GIDLS_PSIC_Msk                   (0x01UL << CCU4_GIDLS_PSIC_Pos)                         /*!< CCU4 GIDLS: PSIC Mask                   */\r
+\r
+/* ---------------------------------  CCU4_GIDLC  --------------------------------- */\r
+#define CCU4_GIDLC_CS0I_Pos                   0                                                       /*!< CCU4 GIDLC: CS0I Position               */\r
+#define CCU4_GIDLC_CS0I_Msk                   (0x01UL << CCU4_GIDLC_CS0I_Pos)                         /*!< CCU4 GIDLC: CS0I Mask                   */\r
+#define CCU4_GIDLC_CS1I_Pos                   1                                                       /*!< CCU4 GIDLC: CS1I Position               */\r
+#define CCU4_GIDLC_CS1I_Msk                   (0x01UL << CCU4_GIDLC_CS1I_Pos)                         /*!< CCU4 GIDLC: CS1I Mask                   */\r
+#define CCU4_GIDLC_CS2I_Pos                   2                                                       /*!< CCU4 GIDLC: CS2I Position               */\r
+#define CCU4_GIDLC_CS2I_Msk                   (0x01UL << CCU4_GIDLC_CS2I_Pos)                         /*!< CCU4 GIDLC: CS2I Mask                   */\r
+#define CCU4_GIDLC_CS3I_Pos                   3                                                       /*!< CCU4 GIDLC: CS3I Position               */\r
+#define CCU4_GIDLC_CS3I_Msk                   (0x01UL << CCU4_GIDLC_CS3I_Pos)                         /*!< CCU4 GIDLC: CS3I Mask                   */\r
+#define CCU4_GIDLC_SPRB_Pos                   8                                                       /*!< CCU4 GIDLC: SPRB Position               */\r
+#define CCU4_GIDLC_SPRB_Msk                   (0x01UL << CCU4_GIDLC_SPRB_Pos)                         /*!< CCU4 GIDLC: SPRB Mask                   */\r
+\r
+/* ----------------------------------  CCU4_GCSS  --------------------------------- */\r
+#define CCU4_GCSS_S0SE_Pos                    0                                                       /*!< CCU4 GCSS: S0SE Position                */\r
+#define CCU4_GCSS_S0SE_Msk                    (0x01UL << CCU4_GCSS_S0SE_Pos)                          /*!< CCU4 GCSS: S0SE Mask                    */\r
+#define CCU4_GCSS_S0DSE_Pos                   1                                                       /*!< CCU4 GCSS: S0DSE Position               */\r
+#define CCU4_GCSS_S0DSE_Msk                   (0x01UL << CCU4_GCSS_S0DSE_Pos)                         /*!< CCU4 GCSS: S0DSE Mask                   */\r
+#define CCU4_GCSS_S0PSE_Pos                   2                                                       /*!< CCU4 GCSS: S0PSE Position               */\r
+#define CCU4_GCSS_S0PSE_Msk                   (0x01UL << CCU4_GCSS_S0PSE_Pos)                         /*!< CCU4 GCSS: S0PSE Mask                   */\r
+#define CCU4_GCSS_S1SE_Pos                    4                                                       /*!< CCU4 GCSS: S1SE Position                */\r
+#define CCU4_GCSS_S1SE_Msk                    (0x01UL << CCU4_GCSS_S1SE_Pos)                          /*!< CCU4 GCSS: S1SE Mask                    */\r
+#define CCU4_GCSS_S1DSE_Pos                   5                                                       /*!< CCU4 GCSS: S1DSE Position               */\r
+#define CCU4_GCSS_S1DSE_Msk                   (0x01UL << CCU4_GCSS_S1DSE_Pos)                         /*!< CCU4 GCSS: S1DSE Mask                   */\r
+#define CCU4_GCSS_S1PSE_Pos                   6                                                       /*!< CCU4 GCSS: S1PSE Position               */\r
+#define CCU4_GCSS_S1PSE_Msk                   (0x01UL << CCU4_GCSS_S1PSE_Pos)                         /*!< CCU4 GCSS: S1PSE Mask                   */\r
+#define CCU4_GCSS_S2SE_Pos                    8                                                       /*!< CCU4 GCSS: S2SE Position                */\r
+#define CCU4_GCSS_S2SE_Msk                    (0x01UL << CCU4_GCSS_S2SE_Pos)                          /*!< CCU4 GCSS: S2SE Mask                    */\r
+#define CCU4_GCSS_S2DSE_Pos                   9                                                       /*!< CCU4 GCSS: S2DSE Position               */\r
+#define CCU4_GCSS_S2DSE_Msk                   (0x01UL << CCU4_GCSS_S2DSE_Pos)                         /*!< CCU4 GCSS: S2DSE Mask                   */\r
+#define CCU4_GCSS_S2PSE_Pos                   10                                                      /*!< CCU4 GCSS: S2PSE Position               */\r
+#define CCU4_GCSS_S2PSE_Msk                   (0x01UL << CCU4_GCSS_S2PSE_Pos)                         /*!< CCU4 GCSS: S2PSE Mask                   */\r
+#define CCU4_GCSS_S3SE_Pos                    12                                                      /*!< CCU4 GCSS: S3SE Position                */\r
+#define CCU4_GCSS_S3SE_Msk                    (0x01UL << CCU4_GCSS_S3SE_Pos)                          /*!< CCU4 GCSS: S3SE Mask                    */\r
+#define CCU4_GCSS_S3DSE_Pos                   13                                                      /*!< CCU4 GCSS: S3DSE Position               */\r
+#define CCU4_GCSS_S3DSE_Msk                   (0x01UL << CCU4_GCSS_S3DSE_Pos)                         /*!< CCU4 GCSS: S3DSE Mask                   */\r
+#define CCU4_GCSS_S3PSE_Pos                   14                                                      /*!< CCU4 GCSS: S3PSE Position               */\r
+#define CCU4_GCSS_S3PSE_Msk                   (0x01UL << CCU4_GCSS_S3PSE_Pos)                         /*!< CCU4 GCSS: S3PSE Mask                   */\r
+#define CCU4_GCSS_S0STS_Pos                   16                                                      /*!< CCU4 GCSS: S0STS Position               */\r
+#define CCU4_GCSS_S0STS_Msk                   (0x01UL << CCU4_GCSS_S0STS_Pos)                         /*!< CCU4 GCSS: S0STS Mask                   */\r
+#define CCU4_GCSS_S1STS_Pos                   17                                                      /*!< CCU4 GCSS: S1STS Position               */\r
+#define CCU4_GCSS_S1STS_Msk                   (0x01UL << CCU4_GCSS_S1STS_Pos)                         /*!< CCU4 GCSS: S1STS Mask                   */\r
+#define CCU4_GCSS_S2STS_Pos                   18                                                      /*!< CCU4 GCSS: S2STS Position               */\r
+#define CCU4_GCSS_S2STS_Msk                   (0x01UL << CCU4_GCSS_S2STS_Pos)                         /*!< CCU4 GCSS: S2STS Mask                   */\r
+#define CCU4_GCSS_S3STS_Pos                   19                                                      /*!< CCU4 GCSS: S3STS Position               */\r
+#define CCU4_GCSS_S3STS_Msk                   (0x01UL << CCU4_GCSS_S3STS_Pos)                         /*!< CCU4 GCSS: S3STS Mask                   */\r
+\r
+/* ----------------------------------  CCU4_GCSC  --------------------------------- */\r
+#define CCU4_GCSC_S0SC_Pos                    0                                                       /*!< CCU4 GCSC: S0SC Position                */\r
+#define CCU4_GCSC_S0SC_Msk                    (0x01UL << CCU4_GCSC_S0SC_Pos)                          /*!< CCU4 GCSC: S0SC Mask                    */\r
+#define CCU4_GCSC_S0DSC_Pos                   1                                                       /*!< CCU4 GCSC: S0DSC Position               */\r
+#define CCU4_GCSC_S0DSC_Msk                   (0x01UL << CCU4_GCSC_S0DSC_Pos)                         /*!< CCU4 GCSC: S0DSC Mask                   */\r
+#define CCU4_GCSC_S0PSC_Pos                   2                                                       /*!< CCU4 GCSC: S0PSC Position               */\r
+#define CCU4_GCSC_S0PSC_Msk                   (0x01UL << CCU4_GCSC_S0PSC_Pos)                         /*!< CCU4 GCSC: S0PSC Mask                   */\r
+#define CCU4_GCSC_S1SC_Pos                    4                                                       /*!< CCU4 GCSC: S1SC Position                */\r
+#define CCU4_GCSC_S1SC_Msk                    (0x01UL << CCU4_GCSC_S1SC_Pos)                          /*!< CCU4 GCSC: S1SC Mask                    */\r
+#define CCU4_GCSC_S1DSC_Pos                   5                                                       /*!< CCU4 GCSC: S1DSC Position               */\r
+#define CCU4_GCSC_S1DSC_Msk                   (0x01UL << CCU4_GCSC_S1DSC_Pos)                         /*!< CCU4 GCSC: S1DSC Mask                   */\r
+#define CCU4_GCSC_S1PSC_Pos                   6                                                       /*!< CCU4 GCSC: S1PSC Position               */\r
+#define CCU4_GCSC_S1PSC_Msk                   (0x01UL << CCU4_GCSC_S1PSC_Pos)                         /*!< CCU4 GCSC: S1PSC Mask                   */\r
+#define CCU4_GCSC_S2SC_Pos                    8                                                       /*!< CCU4 GCSC: S2SC Position                */\r
+#define CCU4_GCSC_S2SC_Msk                    (0x01UL << CCU4_GCSC_S2SC_Pos)                          /*!< CCU4 GCSC: S2SC Mask                    */\r
+#define CCU4_GCSC_S2DSC_Pos                   9                                                       /*!< CCU4 GCSC: S2DSC Position               */\r
+#define CCU4_GCSC_S2DSC_Msk                   (0x01UL << CCU4_GCSC_S2DSC_Pos)                         /*!< CCU4 GCSC: S2DSC Mask                   */\r
+#define CCU4_GCSC_S2PSC_Pos                   10                                                      /*!< CCU4 GCSC: S2PSC Position               */\r
+#define CCU4_GCSC_S2PSC_Msk                   (0x01UL << CCU4_GCSC_S2PSC_Pos)                         /*!< CCU4 GCSC: S2PSC Mask                   */\r
+#define CCU4_GCSC_S3SC_Pos                    12                                                      /*!< CCU4 GCSC: S3SC Position                */\r
+#define CCU4_GCSC_S3SC_Msk                    (0x01UL << CCU4_GCSC_S3SC_Pos)                          /*!< CCU4 GCSC: S3SC Mask                    */\r
+#define CCU4_GCSC_S3DSC_Pos                   13                                                      /*!< CCU4 GCSC: S3DSC Position               */\r
+#define CCU4_GCSC_S3DSC_Msk                   (0x01UL << CCU4_GCSC_S3DSC_Pos)                         /*!< CCU4 GCSC: S3DSC Mask                   */\r
+#define CCU4_GCSC_S3PSC_Pos                   14                                                      /*!< CCU4 GCSC: S3PSC Position               */\r
+#define CCU4_GCSC_S3PSC_Msk                   (0x01UL << CCU4_GCSC_S3PSC_Pos)                         /*!< CCU4 GCSC: S3PSC Mask                   */\r
+#define CCU4_GCSC_S0STC_Pos                   16                                                      /*!< CCU4 GCSC: S0STC Position               */\r
+#define CCU4_GCSC_S0STC_Msk                   (0x01UL << CCU4_GCSC_S0STC_Pos)                         /*!< CCU4 GCSC: S0STC Mask                   */\r
+#define CCU4_GCSC_S1STC_Pos                   17                                                      /*!< CCU4 GCSC: S1STC Position               */\r
+#define CCU4_GCSC_S1STC_Msk                   (0x01UL << CCU4_GCSC_S1STC_Pos)                         /*!< CCU4 GCSC: S1STC Mask                   */\r
+#define CCU4_GCSC_S2STC_Pos                   18                                                      /*!< CCU4 GCSC: S2STC Position               */\r
+#define CCU4_GCSC_S2STC_Msk                   (0x01UL << CCU4_GCSC_S2STC_Pos)                         /*!< CCU4 GCSC: S2STC Mask                   */\r
+#define CCU4_GCSC_S3STC_Pos                   19                                                      /*!< CCU4 GCSC: S3STC Position               */\r
+#define CCU4_GCSC_S3STC_Msk                   (0x01UL << CCU4_GCSC_S3STC_Pos)                         /*!< CCU4 GCSC: S3STC Mask                   */\r
+\r
+/* ----------------------------------  CCU4_GCST  --------------------------------- */\r
+#define CCU4_GCST_S0SS_Pos                    0                                                       /*!< CCU4 GCST: S0SS Position                */\r
+#define CCU4_GCST_S0SS_Msk                    (0x01UL << CCU4_GCST_S0SS_Pos)                          /*!< CCU4 GCST: S0SS Mask                    */\r
+#define CCU4_GCST_S0DSS_Pos                   1                                                       /*!< CCU4 GCST: S0DSS Position               */\r
+#define CCU4_GCST_S0DSS_Msk                   (0x01UL << CCU4_GCST_S0DSS_Pos)                         /*!< CCU4 GCST: S0DSS Mask                   */\r
+#define CCU4_GCST_S0PSS_Pos                   2                                                       /*!< CCU4 GCST: S0PSS Position               */\r
+#define CCU4_GCST_S0PSS_Msk                   (0x01UL << CCU4_GCST_S0PSS_Pos)                         /*!< CCU4 GCST: S0PSS Mask                   */\r
+#define CCU4_GCST_S1SS_Pos                    4                                                       /*!< CCU4 GCST: S1SS Position                */\r
+#define CCU4_GCST_S1SS_Msk                    (0x01UL << CCU4_GCST_S1SS_Pos)                          /*!< CCU4 GCST: S1SS Mask                    */\r
+#define CCU4_GCST_S1DSS_Pos                   5                                                       /*!< CCU4 GCST: S1DSS Position               */\r
+#define CCU4_GCST_S1DSS_Msk                   (0x01UL << CCU4_GCST_S1DSS_Pos)                         /*!< CCU4 GCST: S1DSS Mask                   */\r
+#define CCU4_GCST_S1PSS_Pos                   6                                                       /*!< CCU4 GCST: S1PSS Position               */\r
+#define CCU4_GCST_S1PSS_Msk                   (0x01UL << CCU4_GCST_S1PSS_Pos)                         /*!< CCU4 GCST: S1PSS Mask                   */\r
+#define CCU4_GCST_S2SS_Pos                    8                                                       /*!< CCU4 GCST: S2SS Position                */\r
+#define CCU4_GCST_S2SS_Msk                    (0x01UL << CCU4_GCST_S2SS_Pos)                          /*!< CCU4 GCST: S2SS Mask                    */\r
+#define CCU4_GCST_S2DSS_Pos                   9                                                       /*!< CCU4 GCST: S2DSS Position               */\r
+#define CCU4_GCST_S2DSS_Msk                   (0x01UL << CCU4_GCST_S2DSS_Pos)                         /*!< CCU4 GCST: S2DSS Mask                   */\r
+#define CCU4_GCST_S2PSS_Pos                   10                                                      /*!< CCU4 GCST: S2PSS Position               */\r
+#define CCU4_GCST_S2PSS_Msk                   (0x01UL << CCU4_GCST_S2PSS_Pos)                         /*!< CCU4 GCST: S2PSS Mask                   */\r
+#define CCU4_GCST_S3SS_Pos                    12                                                      /*!< CCU4 GCST: S3SS Position                */\r
+#define CCU4_GCST_S3SS_Msk                    (0x01UL << CCU4_GCST_S3SS_Pos)                          /*!< CCU4 GCST: S3SS Mask                    */\r
+#define CCU4_GCST_S3DSS_Pos                   13                                                      /*!< CCU4 GCST: S3DSS Position               */\r
+#define CCU4_GCST_S3DSS_Msk                   (0x01UL << CCU4_GCST_S3DSS_Pos)                         /*!< CCU4 GCST: S3DSS Mask                   */\r
+#define CCU4_GCST_S3PSS_Pos                   14                                                      /*!< CCU4 GCST: S3PSS Position               */\r
+#define CCU4_GCST_S3PSS_Msk                   (0x01UL << CCU4_GCST_S3PSS_Pos)                         /*!< CCU4 GCST: S3PSS Mask                   */\r
+#define CCU4_GCST_CC40ST_Pos                  16                                                      /*!< CCU4 GCST: CC40ST Position              */\r
+#define CCU4_GCST_CC40ST_Msk                  (0x01UL << CCU4_GCST_CC40ST_Pos)                        /*!< CCU4 GCST: CC40ST Mask                  */\r
+#define CCU4_GCST_CC41ST_Pos                  17                                                      /*!< CCU4 GCST: CC41ST Position              */\r
+#define CCU4_GCST_CC41ST_Msk                  (0x01UL << CCU4_GCST_CC41ST_Pos)                        /*!< CCU4 GCST: CC41ST Mask                  */\r
+#define CCU4_GCST_CC42ST_Pos                  18                                                      /*!< CCU4 GCST: CC42ST Position              */\r
+#define CCU4_GCST_CC42ST_Msk                  (0x01UL << CCU4_GCST_CC42ST_Pos)                        /*!< CCU4 GCST: CC42ST Mask                  */\r
+#define CCU4_GCST_CC43ST_Pos                  19                                                      /*!< CCU4 GCST: CC43ST Position              */\r
+#define CCU4_GCST_CC43ST_Msk                  (0x01UL << CCU4_GCST_CC43ST_Pos)                        /*!< CCU4 GCST: CC43ST Mask                  */\r
+\r
+/* ----------------------------------  CCU4_ECRD  --------------------------------- */\r
+#define CCU4_ECRD_CAPV_Pos                    0                                                       /*!< CCU4 ECRD: CAPV Position                */\r
+#define CCU4_ECRD_CAPV_Msk                    (0x0000ffffUL << CCU4_ECRD_CAPV_Pos)                    /*!< CCU4 ECRD: CAPV Mask                    */\r
+#define CCU4_ECRD_FPCV_Pos                    16                                                      /*!< CCU4 ECRD: FPCV Position                */\r
+#define CCU4_ECRD_FPCV_Msk                    (0x0fUL << CCU4_ECRD_FPCV_Pos)                          /*!< CCU4 ECRD: FPCV Mask                    */\r
+#define CCU4_ECRD_SPTR_Pos                    20                                                      /*!< CCU4 ECRD: SPTR Position                */\r
+#define CCU4_ECRD_SPTR_Msk                    (0x03UL << CCU4_ECRD_SPTR_Pos)                          /*!< CCU4 ECRD: SPTR Mask                    */\r
+#define CCU4_ECRD_VPTR_Pos                    22                                                      /*!< CCU4 ECRD: VPTR Position                */\r
+#define CCU4_ECRD_VPTR_Msk                    (0x03UL << CCU4_ECRD_VPTR_Pos)                          /*!< CCU4 ECRD: VPTR Mask                    */\r
+#define CCU4_ECRD_FFL_Pos                     24                                                      /*!< CCU4 ECRD: FFL Position                 */\r
+#define CCU4_ECRD_FFL_Msk                     (0x01UL << CCU4_ECRD_FFL_Pos)                           /*!< CCU4 ECRD: FFL Mask                     */\r
+\r
+/* ----------------------------------  CCU4_MIDR  --------------------------------- */\r
+#define CCU4_MIDR_MODR_Pos                    0                                                       /*!< CCU4 MIDR: MODR Position                */\r
+#define CCU4_MIDR_MODR_Msk                    (0x000000ffUL << CCU4_MIDR_MODR_Pos)                    /*!< CCU4 MIDR: MODR Mask                    */\r
+#define CCU4_MIDR_MODT_Pos                    8                                                       /*!< CCU4 MIDR: MODT Position                */\r
+#define CCU4_MIDR_MODT_Msk                    (0x000000ffUL << CCU4_MIDR_MODT_Pos)                    /*!< CCU4 MIDR: MODT Mask                    */\r
+#define CCU4_MIDR_MODN_Pos                    16                                                      /*!< CCU4 MIDR: MODN Position                */\r
+#define CCU4_MIDR_MODN_Msk                    (0x0000ffffUL << CCU4_MIDR_MODN_Pos)                    /*!< CCU4 MIDR: MODN Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        Group 'CCU4_CC4' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CCU4_CC4_INS  -------------------------------- */\r
+#define CCU4_CC4_INS_EV0IS_Pos                0                                                       /*!< CCU4_CC4 INS: EV0IS Position            */\r
+#define CCU4_CC4_INS_EV0IS_Msk                (0x0fUL << CCU4_CC4_INS_EV0IS_Pos)                      /*!< CCU4_CC4 INS: EV0IS Mask                */\r
+#define CCU4_CC4_INS_EV1IS_Pos                4                                                       /*!< CCU4_CC4 INS: EV1IS Position            */\r
+#define CCU4_CC4_INS_EV1IS_Msk                (0x0fUL << CCU4_CC4_INS_EV1IS_Pos)                      /*!< CCU4_CC4 INS: EV1IS Mask                */\r
+#define CCU4_CC4_INS_EV2IS_Pos                8                                                       /*!< CCU4_CC4 INS: EV2IS Position            */\r
+#define CCU4_CC4_INS_EV2IS_Msk                (0x0fUL << CCU4_CC4_INS_EV2IS_Pos)                      /*!< CCU4_CC4 INS: EV2IS Mask                */\r
+#define CCU4_CC4_INS_EV0EM_Pos                16                                                      /*!< CCU4_CC4 INS: EV0EM Position            */\r
+#define CCU4_CC4_INS_EV0EM_Msk                (0x03UL << CCU4_CC4_INS_EV0EM_Pos)                      /*!< CCU4_CC4 INS: EV0EM Mask                */\r
+#define CCU4_CC4_INS_EV1EM_Pos                18                                                      /*!< CCU4_CC4 INS: EV1EM Position            */\r
+#define CCU4_CC4_INS_EV1EM_Msk                (0x03UL << CCU4_CC4_INS_EV1EM_Pos)                      /*!< CCU4_CC4 INS: EV1EM Mask                */\r
+#define CCU4_CC4_INS_EV2EM_Pos                20                                                      /*!< CCU4_CC4 INS: EV2EM Position            */\r
+#define CCU4_CC4_INS_EV2EM_Msk                (0x03UL << CCU4_CC4_INS_EV2EM_Pos)                      /*!< CCU4_CC4 INS: EV2EM Mask                */\r
+#define CCU4_CC4_INS_EV0LM_Pos                22                                                      /*!< CCU4_CC4 INS: EV0LM Position            */\r
+#define CCU4_CC4_INS_EV0LM_Msk                (0x01UL << CCU4_CC4_INS_EV0LM_Pos)                      /*!< CCU4_CC4 INS: EV0LM Mask                */\r
+#define CCU4_CC4_INS_EV1LM_Pos                23                                                      /*!< CCU4_CC4 INS: EV1LM Position            */\r
+#define CCU4_CC4_INS_EV1LM_Msk                (0x01UL << CCU4_CC4_INS_EV1LM_Pos)                      /*!< CCU4_CC4 INS: EV1LM Mask                */\r
+#define CCU4_CC4_INS_EV2LM_Pos                24                                                      /*!< CCU4_CC4 INS: EV2LM Position            */\r
+#define CCU4_CC4_INS_EV2LM_Msk                (0x01UL << CCU4_CC4_INS_EV2LM_Pos)                      /*!< CCU4_CC4 INS: EV2LM Mask                */\r
+#define CCU4_CC4_INS_LPF0M_Pos                25                                                      /*!< CCU4_CC4 INS: LPF0M Position            */\r
+#define CCU4_CC4_INS_LPF0M_Msk                (0x03UL << CCU4_CC4_INS_LPF0M_Pos)                      /*!< CCU4_CC4 INS: LPF0M Mask                */\r
+#define CCU4_CC4_INS_LPF1M_Pos                27                                                      /*!< CCU4_CC4 INS: LPF1M Position            */\r
+#define CCU4_CC4_INS_LPF1M_Msk                (0x03UL << CCU4_CC4_INS_LPF1M_Pos)                      /*!< CCU4_CC4 INS: LPF1M Mask                */\r
+#define CCU4_CC4_INS_LPF2M_Pos                29                                                      /*!< CCU4_CC4 INS: LPF2M Position            */\r
+#define CCU4_CC4_INS_LPF2M_Msk                (0x03UL << CCU4_CC4_INS_LPF2M_Pos)                      /*!< CCU4_CC4 INS: LPF2M Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_CMC  -------------------------------- */\r
+#define CCU4_CC4_CMC_STRTS_Pos                0                                                       /*!< CCU4_CC4 CMC: STRTS Position            */\r
+#define CCU4_CC4_CMC_STRTS_Msk                (0x03UL << CCU4_CC4_CMC_STRTS_Pos)                      /*!< CCU4_CC4 CMC: STRTS Mask                */\r
+#define CCU4_CC4_CMC_ENDS_Pos                 2                                                       /*!< CCU4_CC4 CMC: ENDS Position             */\r
+#define CCU4_CC4_CMC_ENDS_Msk                 (0x03UL << CCU4_CC4_CMC_ENDS_Pos)                       /*!< CCU4_CC4 CMC: ENDS Mask                 */\r
+#define CCU4_CC4_CMC_CAP0S_Pos                4                                                       /*!< CCU4_CC4 CMC: CAP0S Position            */\r
+#define CCU4_CC4_CMC_CAP0S_Msk                (0x03UL << CCU4_CC4_CMC_CAP0S_Pos)                      /*!< CCU4_CC4 CMC: CAP0S Mask                */\r
+#define CCU4_CC4_CMC_CAP1S_Pos                6                                                       /*!< CCU4_CC4 CMC: CAP1S Position            */\r
+#define CCU4_CC4_CMC_CAP1S_Msk                (0x03UL << CCU4_CC4_CMC_CAP1S_Pos)                      /*!< CCU4_CC4 CMC: CAP1S Mask                */\r
+#define CCU4_CC4_CMC_GATES_Pos                8                                                       /*!< CCU4_CC4 CMC: GATES Position            */\r
+#define CCU4_CC4_CMC_GATES_Msk                (0x03UL << CCU4_CC4_CMC_GATES_Pos)                      /*!< CCU4_CC4 CMC: GATES Mask                */\r
+#define CCU4_CC4_CMC_UDS_Pos                  10                                                      /*!< CCU4_CC4 CMC: UDS Position              */\r
+#define CCU4_CC4_CMC_UDS_Msk                  (0x03UL << CCU4_CC4_CMC_UDS_Pos)                        /*!< CCU4_CC4 CMC: UDS Mask                  */\r
+#define CCU4_CC4_CMC_LDS_Pos                  12                                                      /*!< CCU4_CC4 CMC: LDS Position              */\r
+#define CCU4_CC4_CMC_LDS_Msk                  (0x03UL << CCU4_CC4_CMC_LDS_Pos)                        /*!< CCU4_CC4 CMC: LDS Mask                  */\r
+#define CCU4_CC4_CMC_CNTS_Pos                 14                                                      /*!< CCU4_CC4 CMC: CNTS Position             */\r
+#define CCU4_CC4_CMC_CNTS_Msk                 (0x03UL << CCU4_CC4_CMC_CNTS_Pos)                       /*!< CCU4_CC4 CMC: CNTS Mask                 */\r
+#define CCU4_CC4_CMC_OFS_Pos                  16                                                      /*!< CCU4_CC4 CMC: OFS Position              */\r
+#define CCU4_CC4_CMC_OFS_Msk                  (0x01UL << CCU4_CC4_CMC_OFS_Pos)                        /*!< CCU4_CC4 CMC: OFS Mask                  */\r
+#define CCU4_CC4_CMC_TS_Pos                   17                                                      /*!< CCU4_CC4 CMC: TS Position               */\r
+#define CCU4_CC4_CMC_TS_Msk                   (0x01UL << CCU4_CC4_CMC_TS_Pos)                         /*!< CCU4_CC4 CMC: TS Mask                   */\r
+#define CCU4_CC4_CMC_MOS_Pos                  18                                                      /*!< CCU4_CC4 CMC: MOS Position              */\r
+#define CCU4_CC4_CMC_MOS_Msk                  (0x03UL << CCU4_CC4_CMC_MOS_Pos)                        /*!< CCU4_CC4 CMC: MOS Mask                  */\r
+#define CCU4_CC4_CMC_TCE_Pos                  20                                                      /*!< CCU4_CC4 CMC: TCE Position              */\r
+#define CCU4_CC4_CMC_TCE_Msk                  (0x01UL << CCU4_CC4_CMC_TCE_Pos)                        /*!< CCU4_CC4 CMC: TCE Mask                  */\r
+\r
+/* --------------------------------  CCU4_CC4_TCST  ------------------------------- */\r
+#define CCU4_CC4_TCST_TRB_Pos                 0                                                       /*!< CCU4_CC4 TCST: TRB Position             */\r
+#define CCU4_CC4_TCST_TRB_Msk                 (0x01UL << CCU4_CC4_TCST_TRB_Pos)                       /*!< CCU4_CC4 TCST: TRB Mask                 */\r
+#define CCU4_CC4_TCST_CDIR_Pos                1                                                       /*!< CCU4_CC4 TCST: CDIR Position            */\r
+#define CCU4_CC4_TCST_CDIR_Msk                (0x01UL << CCU4_CC4_TCST_CDIR_Pos)                      /*!< CCU4_CC4 TCST: CDIR Mask                */\r
+\r
+/* -------------------------------  CCU4_CC4_TCSET  ------------------------------- */\r
+#define CCU4_CC4_TCSET_TRBS_Pos               0                                                       /*!< CCU4_CC4 TCSET: TRBS Position           */\r
+#define CCU4_CC4_TCSET_TRBS_Msk               (0x01UL << CCU4_CC4_TCSET_TRBS_Pos)                     /*!< CCU4_CC4 TCSET: TRBS Mask               */\r
+\r
+/* -------------------------------  CCU4_CC4_TCCLR  ------------------------------- */\r
+#define CCU4_CC4_TCCLR_TRBC_Pos               0                                                       /*!< CCU4_CC4 TCCLR: TRBC Position           */\r
+#define CCU4_CC4_TCCLR_TRBC_Msk               (0x01UL << CCU4_CC4_TCCLR_TRBC_Pos)                     /*!< CCU4_CC4 TCCLR: TRBC Mask               */\r
+#define CCU4_CC4_TCCLR_TCC_Pos                1                                                       /*!< CCU4_CC4 TCCLR: TCC Position            */\r
+#define CCU4_CC4_TCCLR_TCC_Msk                (0x01UL << CCU4_CC4_TCCLR_TCC_Pos)                      /*!< CCU4_CC4 TCCLR: TCC Mask                */\r
+#define CCU4_CC4_TCCLR_DITC_Pos               2                                                       /*!< CCU4_CC4 TCCLR: DITC Position           */\r
+#define CCU4_CC4_TCCLR_DITC_Msk               (0x01UL << CCU4_CC4_TCCLR_DITC_Pos)                     /*!< CCU4_CC4 TCCLR: DITC Mask               */\r
+\r
+/* ---------------------------------  CCU4_CC4_TC  -------------------------------- */\r
+#define CCU4_CC4_TC_TCM_Pos                   0                                                       /*!< CCU4_CC4 TC: TCM Position               */\r
+#define CCU4_CC4_TC_TCM_Msk                   (0x01UL << CCU4_CC4_TC_TCM_Pos)                         /*!< CCU4_CC4 TC: TCM Mask                   */\r
+#define CCU4_CC4_TC_TSSM_Pos                  1                                                       /*!< CCU4_CC4 TC: TSSM Position              */\r
+#define CCU4_CC4_TC_TSSM_Msk                  (0x01UL << CCU4_CC4_TC_TSSM_Pos)                        /*!< CCU4_CC4 TC: TSSM Mask                  */\r
+#define CCU4_CC4_TC_CLST_Pos                  2                                                       /*!< CCU4_CC4 TC: CLST Position              */\r
+#define CCU4_CC4_TC_CLST_Msk                  (0x01UL << CCU4_CC4_TC_CLST_Pos)                        /*!< CCU4_CC4 TC: CLST Mask                  */\r
+#define CCU4_CC4_TC_CMOD_Pos                  3                                                       /*!< CCU4_CC4 TC: CMOD Position              */\r
+#define CCU4_CC4_TC_CMOD_Msk                  (0x01UL << CCU4_CC4_TC_CMOD_Pos)                        /*!< CCU4_CC4 TC: CMOD Mask                  */\r
+#define CCU4_CC4_TC_ECM_Pos                   4                                                       /*!< CCU4_CC4 TC: ECM Position               */\r
+#define CCU4_CC4_TC_ECM_Msk                   (0x01UL << CCU4_CC4_TC_ECM_Pos)                         /*!< CCU4_CC4 TC: ECM Mask                   */\r
+#define CCU4_CC4_TC_CAPC_Pos                  5                                                       /*!< CCU4_CC4 TC: CAPC Position              */\r
+#define CCU4_CC4_TC_CAPC_Msk                  (0x03UL << CCU4_CC4_TC_CAPC_Pos)                        /*!< CCU4_CC4 TC: CAPC Mask                  */\r
+#define CCU4_CC4_TC_ENDM_Pos                  8                                                       /*!< CCU4_CC4 TC: ENDM Position              */\r
+#define CCU4_CC4_TC_ENDM_Msk                  (0x03UL << CCU4_CC4_TC_ENDM_Pos)                        /*!< CCU4_CC4 TC: ENDM Mask                  */\r
+#define CCU4_CC4_TC_STRM_Pos                  10                                                      /*!< CCU4_CC4 TC: STRM Position              */\r
+#define CCU4_CC4_TC_STRM_Msk                  (0x01UL << CCU4_CC4_TC_STRM_Pos)                        /*!< CCU4_CC4 TC: STRM Mask                  */\r
+#define CCU4_CC4_TC_SCE_Pos                   11                                                      /*!< CCU4_CC4 TC: SCE Position               */\r
+#define CCU4_CC4_TC_SCE_Msk                   (0x01UL << CCU4_CC4_TC_SCE_Pos)                         /*!< CCU4_CC4 TC: SCE Mask                   */\r
+#define CCU4_CC4_TC_CCS_Pos                   12                                                      /*!< CCU4_CC4 TC: CCS Position               */\r
+#define CCU4_CC4_TC_CCS_Msk                   (0x01UL << CCU4_CC4_TC_CCS_Pos)                         /*!< CCU4_CC4 TC: CCS Mask                   */\r
+#define CCU4_CC4_TC_DITHE_Pos                 13                                                      /*!< CCU4_CC4 TC: DITHE Position             */\r
+#define CCU4_CC4_TC_DITHE_Msk                 (0x03UL << CCU4_CC4_TC_DITHE_Pos)                       /*!< CCU4_CC4 TC: DITHE Mask                 */\r
+#define CCU4_CC4_TC_DIM_Pos                   15                                                      /*!< CCU4_CC4 TC: DIM Position               */\r
+#define CCU4_CC4_TC_DIM_Msk                   (0x01UL << CCU4_CC4_TC_DIM_Pos)                         /*!< CCU4_CC4 TC: DIM Mask                   */\r
+#define CCU4_CC4_TC_FPE_Pos                   16                                                      /*!< CCU4_CC4 TC: FPE Position               */\r
+#define CCU4_CC4_TC_FPE_Msk                   (0x01UL << CCU4_CC4_TC_FPE_Pos)                         /*!< CCU4_CC4 TC: FPE Mask                   */\r
+#define CCU4_CC4_TC_TRAPE_Pos                 17                                                      /*!< CCU4_CC4 TC: TRAPE Position             */\r
+#define CCU4_CC4_TC_TRAPE_Msk                 (0x01UL << CCU4_CC4_TC_TRAPE_Pos)                       /*!< CCU4_CC4 TC: TRAPE Mask                 */\r
+#define CCU4_CC4_TC_TRPSE_Pos                 21                                                      /*!< CCU4_CC4 TC: TRPSE Position             */\r
+#define CCU4_CC4_TC_TRPSE_Msk                 (0x01UL << CCU4_CC4_TC_TRPSE_Pos)                       /*!< CCU4_CC4 TC: TRPSE Mask                 */\r
+#define CCU4_CC4_TC_TRPSW_Pos                 22                                                      /*!< CCU4_CC4 TC: TRPSW Position             */\r
+#define CCU4_CC4_TC_TRPSW_Msk                 (0x01UL << CCU4_CC4_TC_TRPSW_Pos)                       /*!< CCU4_CC4 TC: TRPSW Mask                 */\r
+#define CCU4_CC4_TC_EMS_Pos                   23                                                      /*!< CCU4_CC4 TC: EMS Position               */\r
+#define CCU4_CC4_TC_EMS_Msk                   (0x01UL << CCU4_CC4_TC_EMS_Pos)                         /*!< CCU4_CC4 TC: EMS Mask                   */\r
+#define CCU4_CC4_TC_EMT_Pos                   24                                                      /*!< CCU4_CC4 TC: EMT Position               */\r
+#define CCU4_CC4_TC_EMT_Msk                   (0x01UL << CCU4_CC4_TC_EMT_Pos)                         /*!< CCU4_CC4 TC: EMT Mask                   */\r
+#define CCU4_CC4_TC_MCME_Pos                  25                                                      /*!< CCU4_CC4 TC: MCME Position              */\r
+#define CCU4_CC4_TC_MCME_Msk                  (0x01UL << CCU4_CC4_TC_MCME_Pos)                        /*!< CCU4_CC4 TC: MCME Mask                  */\r
+\r
+/* --------------------------------  CCU4_CC4_PSL  -------------------------------- */\r
+#define CCU4_CC4_PSL_PSL_Pos                  0                                                       /*!< CCU4_CC4 PSL: PSL Position              */\r
+#define CCU4_CC4_PSL_PSL_Msk                  (0x01UL << CCU4_CC4_PSL_PSL_Pos)                        /*!< CCU4_CC4 PSL: PSL Mask                  */\r
+\r
+/* --------------------------------  CCU4_CC4_DIT  -------------------------------- */\r
+#define CCU4_CC4_DIT_DCV_Pos                  0                                                       /*!< CCU4_CC4 DIT: DCV Position              */\r
+#define CCU4_CC4_DIT_DCV_Msk                  (0x0fUL << CCU4_CC4_DIT_DCV_Pos)                        /*!< CCU4_CC4 DIT: DCV Mask                  */\r
+#define CCU4_CC4_DIT_DCNT_Pos                 8                                                       /*!< CCU4_CC4 DIT: DCNT Position             */\r
+#define CCU4_CC4_DIT_DCNT_Msk                 (0x0fUL << CCU4_CC4_DIT_DCNT_Pos)                       /*!< CCU4_CC4 DIT: DCNT Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_DITS  ------------------------------- */\r
+#define CCU4_CC4_DITS_DCVS_Pos                0                                                       /*!< CCU4_CC4 DITS: DCVS Position            */\r
+#define CCU4_CC4_DITS_DCVS_Msk                (0x0fUL << CCU4_CC4_DITS_DCVS_Pos)                      /*!< CCU4_CC4 DITS: DCVS Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_PSC  -------------------------------- */\r
+#define CCU4_CC4_PSC_PSIV_Pos                 0                                                       /*!< CCU4_CC4 PSC: PSIV Position             */\r
+#define CCU4_CC4_PSC_PSIV_Msk                 (0x0fUL << CCU4_CC4_PSC_PSIV_Pos)                       /*!< CCU4_CC4 PSC: PSIV Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_FPC  -------------------------------- */\r
+#define CCU4_CC4_FPC_PCMP_Pos                 0                                                       /*!< CCU4_CC4 FPC: PCMP Position             */\r
+#define CCU4_CC4_FPC_PCMP_Msk                 (0x0fUL << CCU4_CC4_FPC_PCMP_Pos)                       /*!< CCU4_CC4 FPC: PCMP Mask                 */\r
+#define CCU4_CC4_FPC_PVAL_Pos                 8                                                       /*!< CCU4_CC4 FPC: PVAL Position             */\r
+#define CCU4_CC4_FPC_PVAL_Msk                 (0x0fUL << CCU4_CC4_FPC_PVAL_Pos)                       /*!< CCU4_CC4 FPC: PVAL Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_FPCS  ------------------------------- */\r
+#define CCU4_CC4_FPCS_PCMP_Pos                0                                                       /*!< CCU4_CC4 FPCS: PCMP Position            */\r
+#define CCU4_CC4_FPCS_PCMP_Msk                (0x0fUL << CCU4_CC4_FPCS_PCMP_Pos)                      /*!< CCU4_CC4 FPCS: PCMP Mask                */\r
+\r
+/* ---------------------------------  CCU4_CC4_PR  -------------------------------- */\r
+#define CCU4_CC4_PR_PR_Pos                    0                                                       /*!< CCU4_CC4 PR: PR Position                */\r
+#define CCU4_CC4_PR_PR_Msk                    (0x0000ffffUL << CCU4_CC4_PR_PR_Pos)                    /*!< CCU4_CC4 PR: PR Mask                    */\r
+\r
+/* --------------------------------  CCU4_CC4_PRS  -------------------------------- */\r
+#define CCU4_CC4_PRS_PRS_Pos                  0                                                       /*!< CCU4_CC4 PRS: PRS Position              */\r
+#define CCU4_CC4_PRS_PRS_Msk                  (0x0000ffffUL << CCU4_CC4_PRS_PRS_Pos)                  /*!< CCU4_CC4 PRS: PRS Mask                  */\r
+\r
+/* ---------------------------------  CCU4_CC4_CR  -------------------------------- */\r
+#define CCU4_CC4_CR_CR_Pos                    0                                                       /*!< CCU4_CC4 CR: CR Position                */\r
+#define CCU4_CC4_CR_CR_Msk                    (0x0000ffffUL << CCU4_CC4_CR_CR_Pos)                    /*!< CCU4_CC4 CR: CR Mask                    */\r
+\r
+/* --------------------------------  CCU4_CC4_CRS  -------------------------------- */\r
+#define CCU4_CC4_CRS_CRS_Pos                  0                                                       /*!< CCU4_CC4 CRS: CRS Position              */\r
+#define CCU4_CC4_CRS_CRS_Msk                  (0x0000ffffUL << CCU4_CC4_CRS_CRS_Pos)                  /*!< CCU4_CC4 CRS: CRS Mask                  */\r
+\r
+/* -------------------------------  CCU4_CC4_TIMER  ------------------------------- */\r
+#define CCU4_CC4_TIMER_TVAL_Pos               0                                                       /*!< CCU4_CC4 TIMER: TVAL Position           */\r
+#define CCU4_CC4_TIMER_TVAL_Msk               (0x0000ffffUL << CCU4_CC4_TIMER_TVAL_Pos)               /*!< CCU4_CC4 TIMER: TVAL Mask               */\r
+\r
+/* ---------------------------------  CCU4_CC4_CV  -------------------------------- */\r
+#define CCU4_CC4_CV_CAPTV_Pos                 0                                                       /*!< CCU4_CC4 CV: CAPTV Position             */\r
+#define CCU4_CC4_CV_CAPTV_Msk                 (0x0000ffffUL << CCU4_CC4_CV_CAPTV_Pos)                 /*!< CCU4_CC4 CV: CAPTV Mask                 */\r
+#define CCU4_CC4_CV_FPCV_Pos                  16                                                      /*!< CCU4_CC4 CV: FPCV Position              */\r
+#define CCU4_CC4_CV_FPCV_Msk                  (0x0fUL << CCU4_CC4_CV_FPCV_Pos)                        /*!< CCU4_CC4 CV: FPCV Mask                  */\r
+#define CCU4_CC4_CV_FFL_Pos                   20                                                      /*!< CCU4_CC4 CV: FFL Position               */\r
+#define CCU4_CC4_CV_FFL_Msk                   (0x01UL << CCU4_CC4_CV_FFL_Pos)                         /*!< CCU4_CC4 CV: FFL Mask                   */\r
+\r
+/* --------------------------------  CCU4_CC4_INTS  ------------------------------- */\r
+#define CCU4_CC4_INTS_PMUS_Pos                0                                                       /*!< CCU4_CC4 INTS: PMUS Position            */\r
+#define CCU4_CC4_INTS_PMUS_Msk                (0x01UL << CCU4_CC4_INTS_PMUS_Pos)                      /*!< CCU4_CC4 INTS: PMUS Mask                */\r
+#define CCU4_CC4_INTS_OMDS_Pos                1                                                       /*!< CCU4_CC4 INTS: OMDS Position            */\r
+#define CCU4_CC4_INTS_OMDS_Msk                (0x01UL << CCU4_CC4_INTS_OMDS_Pos)                      /*!< CCU4_CC4 INTS: OMDS Mask                */\r
+#define CCU4_CC4_INTS_CMUS_Pos                2                                                       /*!< CCU4_CC4 INTS: CMUS Position            */\r
+#define CCU4_CC4_INTS_CMUS_Msk                (0x01UL << CCU4_CC4_INTS_CMUS_Pos)                      /*!< CCU4_CC4 INTS: CMUS Mask                */\r
+#define CCU4_CC4_INTS_CMDS_Pos                3                                                       /*!< CCU4_CC4 INTS: CMDS Position            */\r
+#define CCU4_CC4_INTS_CMDS_Msk                (0x01UL << CCU4_CC4_INTS_CMDS_Pos)                      /*!< CCU4_CC4 INTS: CMDS Mask                */\r
+#define CCU4_CC4_INTS_E0AS_Pos                8                                                       /*!< CCU4_CC4 INTS: E0AS Position            */\r
+#define CCU4_CC4_INTS_E0AS_Msk                (0x01UL << CCU4_CC4_INTS_E0AS_Pos)                      /*!< CCU4_CC4 INTS: E0AS Mask                */\r
+#define CCU4_CC4_INTS_E1AS_Pos                9                                                       /*!< CCU4_CC4 INTS: E1AS Position            */\r
+#define CCU4_CC4_INTS_E1AS_Msk                (0x01UL << CCU4_CC4_INTS_E1AS_Pos)                      /*!< CCU4_CC4 INTS: E1AS Mask                */\r
+#define CCU4_CC4_INTS_E2AS_Pos                10                                                      /*!< CCU4_CC4 INTS: E2AS Position            */\r
+#define CCU4_CC4_INTS_E2AS_Msk                (0x01UL << CCU4_CC4_INTS_E2AS_Pos)                      /*!< CCU4_CC4 INTS: E2AS Mask                */\r
+#define CCU4_CC4_INTS_TRPF_Pos                11                                                      /*!< CCU4_CC4 INTS: TRPF Position            */\r
+#define CCU4_CC4_INTS_TRPF_Msk                (0x01UL << CCU4_CC4_INTS_TRPF_Pos)                      /*!< CCU4_CC4 INTS: TRPF Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_INTE  ------------------------------- */\r
+#define CCU4_CC4_INTE_PME_Pos                 0                                                       /*!< CCU4_CC4 INTE: PME Position             */\r
+#define CCU4_CC4_INTE_PME_Msk                 (0x01UL << CCU4_CC4_INTE_PME_Pos)                       /*!< CCU4_CC4 INTE: PME Mask                 */\r
+#define CCU4_CC4_INTE_OME_Pos                 1                                                       /*!< CCU4_CC4 INTE: OME Position             */\r
+#define CCU4_CC4_INTE_OME_Msk                 (0x01UL << CCU4_CC4_INTE_OME_Pos)                       /*!< CCU4_CC4 INTE: OME Mask                 */\r
+#define CCU4_CC4_INTE_CMUE_Pos                2                                                       /*!< CCU4_CC4 INTE: CMUE Position            */\r
+#define CCU4_CC4_INTE_CMUE_Msk                (0x01UL << CCU4_CC4_INTE_CMUE_Pos)                      /*!< CCU4_CC4 INTE: CMUE Mask                */\r
+#define CCU4_CC4_INTE_CMDE_Pos                3                                                       /*!< CCU4_CC4 INTE: CMDE Position            */\r
+#define CCU4_CC4_INTE_CMDE_Msk                (0x01UL << CCU4_CC4_INTE_CMDE_Pos)                      /*!< CCU4_CC4 INTE: CMDE Mask                */\r
+#define CCU4_CC4_INTE_E0AE_Pos                8                                                       /*!< CCU4_CC4 INTE: E0AE Position            */\r
+#define CCU4_CC4_INTE_E0AE_Msk                (0x01UL << CCU4_CC4_INTE_E0AE_Pos)                      /*!< CCU4_CC4 INTE: E0AE Mask                */\r
+#define CCU4_CC4_INTE_E1AE_Pos                9                                                       /*!< CCU4_CC4 INTE: E1AE Position            */\r
+#define CCU4_CC4_INTE_E1AE_Msk                (0x01UL << CCU4_CC4_INTE_E1AE_Pos)                      /*!< CCU4_CC4 INTE: E1AE Mask                */\r
+#define CCU4_CC4_INTE_E2AE_Pos                10                                                      /*!< CCU4_CC4 INTE: E2AE Position            */\r
+#define CCU4_CC4_INTE_E2AE_Msk                (0x01UL << CCU4_CC4_INTE_E2AE_Pos)                      /*!< CCU4_CC4 INTE: E2AE Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_SRS  -------------------------------- */\r
+#define CCU4_CC4_SRS_POSR_Pos                 0                                                       /*!< CCU4_CC4 SRS: POSR Position             */\r
+#define CCU4_CC4_SRS_POSR_Msk                 (0x03UL << CCU4_CC4_SRS_POSR_Pos)                       /*!< CCU4_CC4 SRS: POSR Mask                 */\r
+#define CCU4_CC4_SRS_CMSR_Pos                 2                                                       /*!< CCU4_CC4 SRS: CMSR Position             */\r
+#define CCU4_CC4_SRS_CMSR_Msk                 (0x03UL << CCU4_CC4_SRS_CMSR_Pos)                       /*!< CCU4_CC4 SRS: CMSR Mask                 */\r
+#define CCU4_CC4_SRS_E0SR_Pos                 8                                                       /*!< CCU4_CC4 SRS: E0SR Position             */\r
+#define CCU4_CC4_SRS_E0SR_Msk                 (0x03UL << CCU4_CC4_SRS_E0SR_Pos)                       /*!< CCU4_CC4 SRS: E0SR Mask                 */\r
+#define CCU4_CC4_SRS_E1SR_Pos                 10                                                      /*!< CCU4_CC4 SRS: E1SR Position             */\r
+#define CCU4_CC4_SRS_E1SR_Msk                 (0x03UL << CCU4_CC4_SRS_E1SR_Pos)                       /*!< CCU4_CC4 SRS: E1SR Mask                 */\r
+#define CCU4_CC4_SRS_E2SR_Pos                 12                                                      /*!< CCU4_CC4 SRS: E2SR Position             */\r
+#define CCU4_CC4_SRS_E2SR_Msk                 (0x03UL << CCU4_CC4_SRS_E2SR_Pos)                       /*!< CCU4_CC4 SRS: E2SR Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_SWS  -------------------------------- */\r
+#define CCU4_CC4_SWS_SPM_Pos                  0                                                       /*!< CCU4_CC4 SWS: SPM Position              */\r
+#define CCU4_CC4_SWS_SPM_Msk                  (0x01UL << CCU4_CC4_SWS_SPM_Pos)                        /*!< CCU4_CC4 SWS: SPM Mask                  */\r
+#define CCU4_CC4_SWS_SOM_Pos                  1                                                       /*!< CCU4_CC4 SWS: SOM Position              */\r
+#define CCU4_CC4_SWS_SOM_Msk                  (0x01UL << CCU4_CC4_SWS_SOM_Pos)                        /*!< CCU4_CC4 SWS: SOM Mask                  */\r
+#define CCU4_CC4_SWS_SCMU_Pos                 2                                                       /*!< CCU4_CC4 SWS: SCMU Position             */\r
+#define CCU4_CC4_SWS_SCMU_Msk                 (0x01UL << CCU4_CC4_SWS_SCMU_Pos)                       /*!< CCU4_CC4 SWS: SCMU Mask                 */\r
+#define CCU4_CC4_SWS_SCMD_Pos                 3                                                       /*!< CCU4_CC4 SWS: SCMD Position             */\r
+#define CCU4_CC4_SWS_SCMD_Msk                 (0x01UL << CCU4_CC4_SWS_SCMD_Pos)                       /*!< CCU4_CC4 SWS: SCMD Mask                 */\r
+#define CCU4_CC4_SWS_SE0A_Pos                 8                                                       /*!< CCU4_CC4 SWS: SE0A Position             */\r
+#define CCU4_CC4_SWS_SE0A_Msk                 (0x01UL << CCU4_CC4_SWS_SE0A_Pos)                       /*!< CCU4_CC4 SWS: SE0A Mask                 */\r
+#define CCU4_CC4_SWS_SE1A_Pos                 9                                                       /*!< CCU4_CC4 SWS: SE1A Position             */\r
+#define CCU4_CC4_SWS_SE1A_Msk                 (0x01UL << CCU4_CC4_SWS_SE1A_Pos)                       /*!< CCU4_CC4 SWS: SE1A Mask                 */\r
+#define CCU4_CC4_SWS_SE2A_Pos                 10                                                      /*!< CCU4_CC4 SWS: SE2A Position             */\r
+#define CCU4_CC4_SWS_SE2A_Msk                 (0x01UL << CCU4_CC4_SWS_SE2A_Pos)                       /*!< CCU4_CC4 SWS: SE2A Mask                 */\r
+#define CCU4_CC4_SWS_STRPF_Pos                11                                                      /*!< CCU4_CC4 SWS: STRPF Position            */\r
+#define CCU4_CC4_SWS_STRPF_Msk                (0x01UL << CCU4_CC4_SWS_STRPF_Pos)                      /*!< CCU4_CC4 SWS: STRPF Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_SWR  -------------------------------- */\r
+#define CCU4_CC4_SWR_RPM_Pos                  0                                                       /*!< CCU4_CC4 SWR: RPM Position              */\r
+#define CCU4_CC4_SWR_RPM_Msk                  (0x01UL << CCU4_CC4_SWR_RPM_Pos)                        /*!< CCU4_CC4 SWR: RPM Mask                  */\r
+#define CCU4_CC4_SWR_ROM_Pos                  1                                                       /*!< CCU4_CC4 SWR: ROM Position              */\r
+#define CCU4_CC4_SWR_ROM_Msk                  (0x01UL << CCU4_CC4_SWR_ROM_Pos)                        /*!< CCU4_CC4 SWR: ROM Mask                  */\r
+#define CCU4_CC4_SWR_RCMU_Pos                 2                                                       /*!< CCU4_CC4 SWR: RCMU Position             */\r
+#define CCU4_CC4_SWR_RCMU_Msk                 (0x01UL << CCU4_CC4_SWR_RCMU_Pos)                       /*!< CCU4_CC4 SWR: RCMU Mask                 */\r
+#define CCU4_CC4_SWR_RCMD_Pos                 3                                                       /*!< CCU4_CC4 SWR: RCMD Position             */\r
+#define CCU4_CC4_SWR_RCMD_Msk                 (0x01UL << CCU4_CC4_SWR_RCMD_Pos)                       /*!< CCU4_CC4 SWR: RCMD Mask                 */\r
+#define CCU4_CC4_SWR_RE0A_Pos                 8                                                       /*!< CCU4_CC4 SWR: RE0A Position             */\r
+#define CCU4_CC4_SWR_RE0A_Msk                 (0x01UL << CCU4_CC4_SWR_RE0A_Pos)                       /*!< CCU4_CC4 SWR: RE0A Mask                 */\r
+#define CCU4_CC4_SWR_RE1A_Pos                 9                                                       /*!< CCU4_CC4 SWR: RE1A Position             */\r
+#define CCU4_CC4_SWR_RE1A_Msk                 (0x01UL << CCU4_CC4_SWR_RE1A_Pos)                       /*!< CCU4_CC4 SWR: RE1A Mask                 */\r
+#define CCU4_CC4_SWR_RE2A_Pos                 10                                                      /*!< CCU4_CC4 SWR: RE2A Position             */\r
+#define CCU4_CC4_SWR_RE2A_Msk                 (0x01UL << CCU4_CC4_SWR_RE2A_Pos)                       /*!< CCU4_CC4 SWR: RE2A Mask                 */\r
+#define CCU4_CC4_SWR_RTRPF_Pos                11                                                      /*!< CCU4_CC4 SWR: RTRPF Position            */\r
+#define CCU4_CC4_SWR_RTRPF_Msk                (0x01UL << CCU4_CC4_SWR_RTRPF_Pos)                      /*!< CCU4_CC4 SWR: RTRPF Mask                */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'CCU8' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  CCU8_GCTRL  --------------------------------- */\r
+#define CCU8_GCTRL_PRBC_Pos                   0                                                       /*!< CCU8 GCTRL: PRBC Position               */\r
+#define CCU8_GCTRL_PRBC_Msk                   (0x07UL << CCU8_GCTRL_PRBC_Pos)                         /*!< CCU8 GCTRL: PRBC Mask                   */\r
+#define CCU8_GCTRL_PCIS_Pos                   4                                                       /*!< CCU8 GCTRL: PCIS Position               */\r
+#define CCU8_GCTRL_PCIS_Msk                   (0x03UL << CCU8_GCTRL_PCIS_Pos)                         /*!< CCU8 GCTRL: PCIS Mask                   */\r
+#define CCU8_GCTRL_SUSCFG_Pos                 8                                                       /*!< CCU8 GCTRL: SUSCFG Position             */\r
+#define CCU8_GCTRL_SUSCFG_Msk                 (0x03UL << CCU8_GCTRL_SUSCFG_Pos)                       /*!< CCU8 GCTRL: SUSCFG Mask                 */\r
+#define CCU8_GCTRL_MSE0_Pos                   10                                                      /*!< CCU8 GCTRL: MSE0 Position               */\r
+#define CCU8_GCTRL_MSE0_Msk                   (0x01UL << CCU8_GCTRL_MSE0_Pos)                         /*!< CCU8 GCTRL: MSE0 Mask                   */\r
+#define CCU8_GCTRL_MSE1_Pos                   11                                                      /*!< CCU8 GCTRL: MSE1 Position               */\r
+#define CCU8_GCTRL_MSE1_Msk                   (0x01UL << CCU8_GCTRL_MSE1_Pos)                         /*!< CCU8 GCTRL: MSE1 Mask                   */\r
+#define CCU8_GCTRL_MSE2_Pos                   12                                                      /*!< CCU8 GCTRL: MSE2 Position               */\r
+#define CCU8_GCTRL_MSE2_Msk                   (0x01UL << CCU8_GCTRL_MSE2_Pos)                         /*!< CCU8 GCTRL: MSE2 Mask                   */\r
+#define CCU8_GCTRL_MSE3_Pos                   13                                                      /*!< CCU8 GCTRL: MSE3 Position               */\r
+#define CCU8_GCTRL_MSE3_Msk                   (0x01UL << CCU8_GCTRL_MSE3_Pos)                         /*!< CCU8 GCTRL: MSE3 Mask                   */\r
+#define CCU8_GCTRL_MSDE_Pos                   14                                                      /*!< CCU8 GCTRL: MSDE Position               */\r
+#define CCU8_GCTRL_MSDE_Msk                   (0x03UL << CCU8_GCTRL_MSDE_Pos)                         /*!< CCU8 GCTRL: MSDE Mask                   */\r
+\r
+/* ---------------------------------  CCU8_GSTAT  --------------------------------- */\r
+#define CCU8_GSTAT_S0I_Pos                    0                                                       /*!< CCU8 GSTAT: S0I Position                */\r
+#define CCU8_GSTAT_S0I_Msk                    (0x01UL << CCU8_GSTAT_S0I_Pos)                          /*!< CCU8 GSTAT: S0I Mask                    */\r
+#define CCU8_GSTAT_S1I_Pos                    1                                                       /*!< CCU8 GSTAT: S1I Position                */\r
+#define CCU8_GSTAT_S1I_Msk                    (0x01UL << CCU8_GSTAT_S1I_Pos)                          /*!< CCU8 GSTAT: S1I Mask                    */\r
+#define CCU8_GSTAT_S2I_Pos                    2                                                       /*!< CCU8 GSTAT: S2I Position                */\r
+#define CCU8_GSTAT_S2I_Msk                    (0x01UL << CCU8_GSTAT_S2I_Pos)                          /*!< CCU8 GSTAT: S2I Mask                    */\r
+#define CCU8_GSTAT_S3I_Pos                    3                                                       /*!< CCU8 GSTAT: S3I Position                */\r
+#define CCU8_GSTAT_S3I_Msk                    (0x01UL << CCU8_GSTAT_S3I_Pos)                          /*!< CCU8 GSTAT: S3I Mask                    */\r
+#define CCU8_GSTAT_PRB_Pos                    8                                                       /*!< CCU8 GSTAT: PRB Position                */\r
+#define CCU8_GSTAT_PRB_Msk                    (0x01UL << CCU8_GSTAT_PRB_Pos)                          /*!< CCU8 GSTAT: PRB Mask                    */\r
+#define CCU8_GSTAT_PCRB_Pos                   10                                                      /*!< CCU8 GSTAT: PCRB Position               */\r
+#define CCU8_GSTAT_PCRB_Msk                   (0x01UL << CCU8_GSTAT_PCRB_Pos)                         /*!< CCU8 GSTAT: PCRB Mask                   */\r
+\r
+/* ---------------------------------  CCU8_GIDLS  --------------------------------- */\r
+#define CCU8_GIDLS_SS0I_Pos                   0                                                       /*!< CCU8 GIDLS: SS0I Position               */\r
+#define CCU8_GIDLS_SS0I_Msk                   (0x01UL << CCU8_GIDLS_SS0I_Pos)                         /*!< CCU8 GIDLS: SS0I Mask                   */\r
+#define CCU8_GIDLS_SS1I_Pos                   1                                                       /*!< CCU8 GIDLS: SS1I Position               */\r
+#define CCU8_GIDLS_SS1I_Msk                   (0x01UL << CCU8_GIDLS_SS1I_Pos)                         /*!< CCU8 GIDLS: SS1I Mask                   */\r
+#define CCU8_GIDLS_SS2I_Pos                   2                                                       /*!< CCU8 GIDLS: SS2I Position               */\r
+#define CCU8_GIDLS_SS2I_Msk                   (0x01UL << CCU8_GIDLS_SS2I_Pos)                         /*!< CCU8 GIDLS: SS2I Mask                   */\r
+#define CCU8_GIDLS_SS3I_Pos                   3                                                       /*!< CCU8 GIDLS: SS3I Position               */\r
+#define CCU8_GIDLS_SS3I_Msk                   (0x01UL << CCU8_GIDLS_SS3I_Pos)                         /*!< CCU8 GIDLS: SS3I Mask                   */\r
+#define CCU8_GIDLS_CPRB_Pos                   8                                                       /*!< CCU8 GIDLS: CPRB Position               */\r
+#define CCU8_GIDLS_CPRB_Msk                   (0x01UL << CCU8_GIDLS_CPRB_Pos)                         /*!< CCU8 GIDLS: CPRB Mask                   */\r
+#define CCU8_GIDLS_PSIC_Pos                   9                                                       /*!< CCU8 GIDLS: PSIC Position               */\r
+#define CCU8_GIDLS_PSIC_Msk                   (0x01UL << CCU8_GIDLS_PSIC_Pos)                         /*!< CCU8 GIDLS: PSIC Mask                   */\r
+#define CCU8_GIDLS_CPCH_Pos                   10                                                      /*!< CCU8 GIDLS: CPCH Position               */\r
+#define CCU8_GIDLS_CPCH_Msk                   (0x01UL << CCU8_GIDLS_CPCH_Pos)                         /*!< CCU8 GIDLS: CPCH Mask                   */\r
+\r
+/* ---------------------------------  CCU8_GIDLC  --------------------------------- */\r
+#define CCU8_GIDLC_CS0I_Pos                   0                                                       /*!< CCU8 GIDLC: CS0I Position               */\r
+#define CCU8_GIDLC_CS0I_Msk                   (0x01UL << CCU8_GIDLC_CS0I_Pos)                         /*!< CCU8 GIDLC: CS0I Mask                   */\r
+#define CCU8_GIDLC_CS1I_Pos                   1                                                       /*!< CCU8 GIDLC: CS1I Position               */\r
+#define CCU8_GIDLC_CS1I_Msk                   (0x01UL << CCU8_GIDLC_CS1I_Pos)                         /*!< CCU8 GIDLC: CS1I Mask                   */\r
+#define CCU8_GIDLC_CS2I_Pos                   2                                                       /*!< CCU8 GIDLC: CS2I Position               */\r
+#define CCU8_GIDLC_CS2I_Msk                   (0x01UL << CCU8_GIDLC_CS2I_Pos)                         /*!< CCU8 GIDLC: CS2I Mask                   */\r
+#define CCU8_GIDLC_CS3I_Pos                   3                                                       /*!< CCU8 GIDLC: CS3I Position               */\r
+#define CCU8_GIDLC_CS3I_Msk                   (0x01UL << CCU8_GIDLC_CS3I_Pos)                         /*!< CCU8 GIDLC: CS3I Mask                   */\r
+#define CCU8_GIDLC_SPRB_Pos                   8                                                       /*!< CCU8 GIDLC: SPRB Position               */\r
+#define CCU8_GIDLC_SPRB_Msk                   (0x01UL << CCU8_GIDLC_SPRB_Pos)                         /*!< CCU8 GIDLC: SPRB Mask                   */\r
+#define CCU8_GIDLC_SPCH_Pos                   10                                                      /*!< CCU8 GIDLC: SPCH Position               */\r
+#define CCU8_GIDLC_SPCH_Msk                   (0x01UL << CCU8_GIDLC_SPCH_Pos)                         /*!< CCU8 GIDLC: SPCH Mask                   */\r
+\r
+/* ----------------------------------  CCU8_GCSS  --------------------------------- */\r
+#define CCU8_GCSS_S0SE_Pos                    0                                                       /*!< CCU8 GCSS: S0SE Position                */\r
+#define CCU8_GCSS_S0SE_Msk                    (0x01UL << CCU8_GCSS_S0SE_Pos)                          /*!< CCU8 GCSS: S0SE Mask                    */\r
+#define CCU8_GCSS_S0DSE_Pos                   1                                                       /*!< CCU8 GCSS: S0DSE Position               */\r
+#define CCU8_GCSS_S0DSE_Msk                   (0x01UL << CCU8_GCSS_S0DSE_Pos)                         /*!< CCU8 GCSS: S0DSE Mask                   */\r
+#define CCU8_GCSS_S0PSE_Pos                   2                                                       /*!< CCU8 GCSS: S0PSE Position               */\r
+#define CCU8_GCSS_S0PSE_Msk                   (0x01UL << CCU8_GCSS_S0PSE_Pos)                         /*!< CCU8 GCSS: S0PSE Mask                   */\r
+#define CCU8_GCSS_S1SE_Pos                    4                                                       /*!< CCU8 GCSS: S1SE Position                */\r
+#define CCU8_GCSS_S1SE_Msk                    (0x01UL << CCU8_GCSS_S1SE_Pos)                          /*!< CCU8 GCSS: S1SE Mask                    */\r
+#define CCU8_GCSS_S1DSE_Pos                   5                                                       /*!< CCU8 GCSS: S1DSE Position               */\r
+#define CCU8_GCSS_S1DSE_Msk                   (0x01UL << CCU8_GCSS_S1DSE_Pos)                         /*!< CCU8 GCSS: S1DSE Mask                   */\r
+#define CCU8_GCSS_S1PSE_Pos                   6                                                       /*!< CCU8 GCSS: S1PSE Position               */\r
+#define CCU8_GCSS_S1PSE_Msk                   (0x01UL << CCU8_GCSS_S1PSE_Pos)                         /*!< CCU8 GCSS: S1PSE Mask                   */\r
+#define CCU8_GCSS_S2SE_Pos                    8                                                       /*!< CCU8 GCSS: S2SE Position                */\r
+#define CCU8_GCSS_S2SE_Msk                    (0x01UL << CCU8_GCSS_S2SE_Pos)                          /*!< CCU8 GCSS: S2SE Mask                    */\r
+#define CCU8_GCSS_S2DSE_Pos                   9                                                       /*!< CCU8 GCSS: S2DSE Position               */\r
+#define CCU8_GCSS_S2DSE_Msk                   (0x01UL << CCU8_GCSS_S2DSE_Pos)                         /*!< CCU8 GCSS: S2DSE Mask                   */\r
+#define CCU8_GCSS_S2PSE_Pos                   10                                                      /*!< CCU8 GCSS: S2PSE Position               */\r
+#define CCU8_GCSS_S2PSE_Msk                   (0x01UL << CCU8_GCSS_S2PSE_Pos)                         /*!< CCU8 GCSS: S2PSE Mask                   */\r
+#define CCU8_GCSS_S3SE_Pos                    12                                                      /*!< CCU8 GCSS: S3SE Position                */\r
+#define CCU8_GCSS_S3SE_Msk                    (0x01UL << CCU8_GCSS_S3SE_Pos)                          /*!< CCU8 GCSS: S3SE Mask                    */\r
+#define CCU8_GCSS_S3DSE_Pos                   13                                                      /*!< CCU8 GCSS: S3DSE Position               */\r
+#define CCU8_GCSS_S3DSE_Msk                   (0x01UL << CCU8_GCSS_S3DSE_Pos)                         /*!< CCU8 GCSS: S3DSE Mask                   */\r
+#define CCU8_GCSS_S3PSE_Pos                   14                                                      /*!< CCU8 GCSS: S3PSE Position               */\r
+#define CCU8_GCSS_S3PSE_Msk                   (0x01UL << CCU8_GCSS_S3PSE_Pos)                         /*!< CCU8 GCSS: S3PSE Mask                   */\r
+#define CCU8_GCSS_S0ST1S_Pos                  16                                                      /*!< CCU8 GCSS: S0ST1S Position              */\r
+#define CCU8_GCSS_S0ST1S_Msk                  (0x01UL << CCU8_GCSS_S0ST1S_Pos)                        /*!< CCU8 GCSS: S0ST1S Mask                  */\r
+#define CCU8_GCSS_S1ST1S_Pos                  17                                                      /*!< CCU8 GCSS: S1ST1S Position              */\r
+#define CCU8_GCSS_S1ST1S_Msk                  (0x01UL << CCU8_GCSS_S1ST1S_Pos)                        /*!< CCU8 GCSS: S1ST1S Mask                  */\r
+#define CCU8_GCSS_S2ST1S_Pos                  18                                                      /*!< CCU8 GCSS: S2ST1S Position              */\r
+#define CCU8_GCSS_S2ST1S_Msk                  (0x01UL << CCU8_GCSS_S2ST1S_Pos)                        /*!< CCU8 GCSS: S2ST1S Mask                  */\r
+#define CCU8_GCSS_S3ST1S_Pos                  19                                                      /*!< CCU8 GCSS: S3ST1S Position              */\r
+#define CCU8_GCSS_S3ST1S_Msk                  (0x01UL << CCU8_GCSS_S3ST1S_Pos)                        /*!< CCU8 GCSS: S3ST1S Mask                  */\r
+#define CCU8_GCSS_S0ST2S_Pos                  20                                                      /*!< CCU8 GCSS: S0ST2S Position              */\r
+#define CCU8_GCSS_S0ST2S_Msk                  (0x01UL << CCU8_GCSS_S0ST2S_Pos)                        /*!< CCU8 GCSS: S0ST2S Mask                  */\r
+#define CCU8_GCSS_S1ST2S_Pos                  21                                                      /*!< CCU8 GCSS: S1ST2S Position              */\r
+#define CCU8_GCSS_S1ST2S_Msk                  (0x01UL << CCU8_GCSS_S1ST2S_Pos)                        /*!< CCU8 GCSS: S1ST2S Mask                  */\r
+#define CCU8_GCSS_S2ST2S_Pos                  22                                                      /*!< CCU8 GCSS: S2ST2S Position              */\r
+#define CCU8_GCSS_S2ST2S_Msk                  (0x01UL << CCU8_GCSS_S2ST2S_Pos)                        /*!< CCU8 GCSS: S2ST2S Mask                  */\r
+#define CCU8_GCSS_S3ST2S_Pos                  23                                                      /*!< CCU8 GCSS: S3ST2S Position              */\r
+#define CCU8_GCSS_S3ST2S_Msk                  (0x01UL << CCU8_GCSS_S3ST2S_Pos)                        /*!< CCU8 GCSS: S3ST2S Mask                  */\r
+\r
+/* ----------------------------------  CCU8_GCSC  --------------------------------- */\r
+#define CCU8_GCSC_S0SC_Pos                    0                                                       /*!< CCU8 GCSC: S0SC Position                */\r
+#define CCU8_GCSC_S0SC_Msk                    (0x01UL << CCU8_GCSC_S0SC_Pos)                          /*!< CCU8 GCSC: S0SC Mask                    */\r
+#define CCU8_GCSC_S0DSC_Pos                   1                                                       /*!< CCU8 GCSC: S0DSC Position               */\r
+#define CCU8_GCSC_S0DSC_Msk                   (0x01UL << CCU8_GCSC_S0DSC_Pos)                         /*!< CCU8 GCSC: S0DSC Mask                   */\r
+#define CCU8_GCSC_S0PSC_Pos                   2                                                       /*!< CCU8 GCSC: S0PSC Position               */\r
+#define CCU8_GCSC_S0PSC_Msk                   (0x01UL << CCU8_GCSC_S0PSC_Pos)                         /*!< CCU8 GCSC: S0PSC Mask                   */\r
+#define CCU8_GCSC_S1SC_Pos                    4                                                       /*!< CCU8 GCSC: S1SC Position                */\r
+#define CCU8_GCSC_S1SC_Msk                    (0x01UL << CCU8_GCSC_S1SC_Pos)                          /*!< CCU8 GCSC: S1SC Mask                    */\r
+#define CCU8_GCSC_S1DSC_Pos                   5                                                       /*!< CCU8 GCSC: S1DSC Position               */\r
+#define CCU8_GCSC_S1DSC_Msk                   (0x01UL << CCU8_GCSC_S1DSC_Pos)                         /*!< CCU8 GCSC: S1DSC Mask                   */\r
+#define CCU8_GCSC_S1PSC_Pos                   6                                                       /*!< CCU8 GCSC: S1PSC Position               */\r
+#define CCU8_GCSC_S1PSC_Msk                   (0x01UL << CCU8_GCSC_S1PSC_Pos)                         /*!< CCU8 GCSC: S1PSC Mask                   */\r
+#define CCU8_GCSC_S2SC_Pos                    8                                                       /*!< CCU8 GCSC: S2SC Position                */\r
+#define CCU8_GCSC_S2SC_Msk                    (0x01UL << CCU8_GCSC_S2SC_Pos)                          /*!< CCU8 GCSC: S2SC Mask                    */\r
+#define CCU8_GCSC_S2DSC_Pos                   9                                                       /*!< CCU8 GCSC: S2DSC Position               */\r
+#define CCU8_GCSC_S2DSC_Msk                   (0x01UL << CCU8_GCSC_S2DSC_Pos)                         /*!< CCU8 GCSC: S2DSC Mask                   */\r
+#define CCU8_GCSC_S2PSC_Pos                   10                                                      /*!< CCU8 GCSC: S2PSC Position               */\r
+#define CCU8_GCSC_S2PSC_Msk                   (0x01UL << CCU8_GCSC_S2PSC_Pos)                         /*!< CCU8 GCSC: S2PSC Mask                   */\r
+#define CCU8_GCSC_S3SC_Pos                    12                                                      /*!< CCU8 GCSC: S3SC Position                */\r
+#define CCU8_GCSC_S3SC_Msk                    (0x01UL << CCU8_GCSC_S3SC_Pos)                          /*!< CCU8 GCSC: S3SC Mask                    */\r
+#define CCU8_GCSC_S3DSC_Pos                   13                                                      /*!< CCU8 GCSC: S3DSC Position               */\r
+#define CCU8_GCSC_S3DSC_Msk                   (0x01UL << CCU8_GCSC_S3DSC_Pos)                         /*!< CCU8 GCSC: S3DSC Mask                   */\r
+#define CCU8_GCSC_S3PSC_Pos                   14                                                      /*!< CCU8 GCSC: S3PSC Position               */\r
+#define CCU8_GCSC_S3PSC_Msk                   (0x01UL << CCU8_GCSC_S3PSC_Pos)                         /*!< CCU8 GCSC: S3PSC Mask                   */\r
+#define CCU8_GCSC_S0ST1C_Pos                  16                                                      /*!< CCU8 GCSC: S0ST1C Position              */\r
+#define CCU8_GCSC_S0ST1C_Msk                  (0x01UL << CCU8_GCSC_S0ST1C_Pos)                        /*!< CCU8 GCSC: S0ST1C Mask                  */\r
+#define CCU8_GCSC_S1ST1C_Pos                  17                                                      /*!< CCU8 GCSC: S1ST1C Position              */\r
+#define CCU8_GCSC_S1ST1C_Msk                  (0x01UL << CCU8_GCSC_S1ST1C_Pos)                        /*!< CCU8 GCSC: S1ST1C Mask                  */\r
+#define CCU8_GCSC_S2ST1C_Pos                  18                                                      /*!< CCU8 GCSC: S2ST1C Position              */\r
+#define CCU8_GCSC_S2ST1C_Msk                  (0x01UL << CCU8_GCSC_S2ST1C_Pos)                        /*!< CCU8 GCSC: S2ST1C Mask                  */\r
+#define CCU8_GCSC_S3ST1C_Pos                  19                                                      /*!< CCU8 GCSC: S3ST1C Position              */\r
+#define CCU8_GCSC_S3ST1C_Msk                  (0x01UL << CCU8_GCSC_S3ST1C_Pos)                        /*!< CCU8 GCSC: S3ST1C Mask                  */\r
+#define CCU8_GCSC_S0ST2C_Pos                  20                                                      /*!< CCU8 GCSC: S0ST2C Position              */\r
+#define CCU8_GCSC_S0ST2C_Msk                  (0x01UL << CCU8_GCSC_S0ST2C_Pos)                        /*!< CCU8 GCSC: S0ST2C Mask                  */\r
+#define CCU8_GCSC_S1ST2C_Pos                  21                                                      /*!< CCU8 GCSC: S1ST2C Position              */\r
+#define CCU8_GCSC_S1ST2C_Msk                  (0x01UL << CCU8_GCSC_S1ST2C_Pos)                        /*!< CCU8 GCSC: S1ST2C Mask                  */\r
+#define CCU8_GCSC_S2ST2C_Pos                  22                                                      /*!< CCU8 GCSC: S2ST2C Position              */\r
+#define CCU8_GCSC_S2ST2C_Msk                  (0x01UL << CCU8_GCSC_S2ST2C_Pos)                        /*!< CCU8 GCSC: S2ST2C Mask                  */\r
+#define CCU8_GCSC_S3ST2C_Pos                  23                                                      /*!< CCU8 GCSC: S3ST2C Position              */\r
+#define CCU8_GCSC_S3ST2C_Msk                  (0x01UL << CCU8_GCSC_S3ST2C_Pos)                        /*!< CCU8 GCSC: S3ST2C Mask                  */\r
+\r
+/* ----------------------------------  CCU8_GCST  --------------------------------- */\r
+#define CCU8_GCST_S0SS_Pos                    0                                                       /*!< CCU8 GCST: S0SS Position                */\r
+#define CCU8_GCST_S0SS_Msk                    (0x01UL << CCU8_GCST_S0SS_Pos)                          /*!< CCU8 GCST: S0SS Mask                    */\r
+#define CCU8_GCST_S0DSS_Pos                   1                                                       /*!< CCU8 GCST: S0DSS Position               */\r
+#define CCU8_GCST_S0DSS_Msk                   (0x01UL << CCU8_GCST_S0DSS_Pos)                         /*!< CCU8 GCST: S0DSS Mask                   */\r
+#define CCU8_GCST_S0PSS_Pos                   2                                                       /*!< CCU8 GCST: S0PSS Position               */\r
+#define CCU8_GCST_S0PSS_Msk                   (0x01UL << CCU8_GCST_S0PSS_Pos)                         /*!< CCU8 GCST: S0PSS Mask                   */\r
+#define CCU8_GCST_S1SS_Pos                    4                                                       /*!< CCU8 GCST: S1SS Position                */\r
+#define CCU8_GCST_S1SS_Msk                    (0x01UL << CCU8_GCST_S1SS_Pos)                          /*!< CCU8 GCST: S1SS Mask                    */\r
+#define CCU8_GCST_S1DSS_Pos                   5                                                       /*!< CCU8 GCST: S1DSS Position               */\r
+#define CCU8_GCST_S1DSS_Msk                   (0x01UL << CCU8_GCST_S1DSS_Pos)                         /*!< CCU8 GCST: S1DSS Mask                   */\r
+#define CCU8_GCST_S1PSS_Pos                   6                                                       /*!< CCU8 GCST: S1PSS Position               */\r
+#define CCU8_GCST_S1PSS_Msk                   (0x01UL << CCU8_GCST_S1PSS_Pos)                         /*!< CCU8 GCST: S1PSS Mask                   */\r
+#define CCU8_GCST_S2SS_Pos                    8                                                       /*!< CCU8 GCST: S2SS Position                */\r
+#define CCU8_GCST_S2SS_Msk                    (0x01UL << CCU8_GCST_S2SS_Pos)                          /*!< CCU8 GCST: S2SS Mask                    */\r
+#define CCU8_GCST_S2DSS_Pos                   9                                                       /*!< CCU8 GCST: S2DSS Position               */\r
+#define CCU8_GCST_S2DSS_Msk                   (0x01UL << CCU8_GCST_S2DSS_Pos)                         /*!< CCU8 GCST: S2DSS Mask                   */\r
+#define CCU8_GCST_S2PSS_Pos                   10                                                      /*!< CCU8 GCST: S2PSS Position               */\r
+#define CCU8_GCST_S2PSS_Msk                   (0x01UL << CCU8_GCST_S2PSS_Pos)                         /*!< CCU8 GCST: S2PSS Mask                   */\r
+#define CCU8_GCST_S3SS_Pos                    12                                                      /*!< CCU8 GCST: S3SS Position                */\r
+#define CCU8_GCST_S3SS_Msk                    (0x01UL << CCU8_GCST_S3SS_Pos)                          /*!< CCU8 GCST: S3SS Mask                    */\r
+#define CCU8_GCST_S3DSS_Pos                   13                                                      /*!< CCU8 GCST: S3DSS Position               */\r
+#define CCU8_GCST_S3DSS_Msk                   (0x01UL << CCU8_GCST_S3DSS_Pos)                         /*!< CCU8 GCST: S3DSS Mask                   */\r
+#define CCU8_GCST_S3PSS_Pos                   14                                                      /*!< CCU8 GCST: S3PSS Position               */\r
+#define CCU8_GCST_S3PSS_Msk                   (0x01UL << CCU8_GCST_S3PSS_Pos)                         /*!< CCU8 GCST: S3PSS Mask                   */\r
+#define CCU8_GCST_CC80ST1_Pos                 16                                                      /*!< CCU8 GCST: CC80ST1 Position             */\r
+#define CCU8_GCST_CC80ST1_Msk                 (0x01UL << CCU8_GCST_CC80ST1_Pos)                       /*!< CCU8 GCST: CC80ST1 Mask                 */\r
+#define CCU8_GCST_CC81ST1_Pos                 17                                                      /*!< CCU8 GCST: CC81ST1 Position             */\r
+#define CCU8_GCST_CC81ST1_Msk                 (0x01UL << CCU8_GCST_CC81ST1_Pos)                       /*!< CCU8 GCST: CC81ST1 Mask                 */\r
+#define CCU8_GCST_CC82ST1_Pos                 18                                                      /*!< CCU8 GCST: CC82ST1 Position             */\r
+#define CCU8_GCST_CC82ST1_Msk                 (0x01UL << CCU8_GCST_CC82ST1_Pos)                       /*!< CCU8 GCST: CC82ST1 Mask                 */\r
+#define CCU8_GCST_CC83ST1_Pos                 19                                                      /*!< CCU8 GCST: CC83ST1 Position             */\r
+#define CCU8_GCST_CC83ST1_Msk                 (0x01UL << CCU8_GCST_CC83ST1_Pos)                       /*!< CCU8 GCST: CC83ST1 Mask                 */\r
+#define CCU8_GCST_CC80ST2_Pos                 20                                                      /*!< CCU8 GCST: CC80ST2 Position             */\r
+#define CCU8_GCST_CC80ST2_Msk                 (0x01UL << CCU8_GCST_CC80ST2_Pos)                       /*!< CCU8 GCST: CC80ST2 Mask                 */\r
+#define CCU8_GCST_CC81ST2_Pos                 21                                                      /*!< CCU8 GCST: CC81ST2 Position             */\r
+#define CCU8_GCST_CC81ST2_Msk                 (0x01UL << CCU8_GCST_CC81ST2_Pos)                       /*!< CCU8 GCST: CC81ST2 Mask                 */\r
+#define CCU8_GCST_CC82ST2_Pos                 22                                                      /*!< CCU8 GCST: CC82ST2 Position             */\r
+#define CCU8_GCST_CC82ST2_Msk                 (0x01UL << CCU8_GCST_CC82ST2_Pos)                       /*!< CCU8 GCST: CC82ST2 Mask                 */\r
+#define CCU8_GCST_CC83ST2_Pos                 23                                                      /*!< CCU8 GCST: CC83ST2 Position             */\r
+#define CCU8_GCST_CC83ST2_Msk                 (0x01UL << CCU8_GCST_CC83ST2_Pos)                       /*!< CCU8 GCST: CC83ST2 Mask                 */\r
+\r
+/* ---------------------------------  CCU8_GPCHK  --------------------------------- */\r
+#define CCU8_GPCHK_PASE_Pos                   0                                                       /*!< CCU8 GPCHK: PASE Position               */\r
+#define CCU8_GPCHK_PASE_Msk                   (0x01UL << CCU8_GPCHK_PASE_Pos)                         /*!< CCU8 GPCHK: PASE Mask                   */\r
+#define CCU8_GPCHK_PACS_Pos                   1                                                       /*!< CCU8 GPCHK: PACS Position               */\r
+#define CCU8_GPCHK_PACS_Msk                   (0x03UL << CCU8_GPCHK_PACS_Pos)                         /*!< CCU8 GPCHK: PACS Mask                   */\r
+#define CCU8_GPCHK_PISEL_Pos                  3                                                       /*!< CCU8 GPCHK: PISEL Position              */\r
+#define CCU8_GPCHK_PISEL_Msk                  (0x03UL << CCU8_GPCHK_PISEL_Pos)                        /*!< CCU8 GPCHK: PISEL Mask                  */\r
+#define CCU8_GPCHK_PCDS_Pos                   5                                                       /*!< CCU8 GPCHK: PCDS Position               */\r
+#define CCU8_GPCHK_PCDS_Msk                   (0x03UL << CCU8_GPCHK_PCDS_Pos)                         /*!< CCU8 GPCHK: PCDS Mask                   */\r
+#define CCU8_GPCHK_PCTS_Pos                   7                                                       /*!< CCU8 GPCHK: PCTS Position               */\r
+#define CCU8_GPCHK_PCTS_Msk                   (0x01UL << CCU8_GPCHK_PCTS_Pos)                         /*!< CCU8 GPCHK: PCTS Mask                   */\r
+#define CCU8_GPCHK_PCST_Pos                   15                                                      /*!< CCU8 GPCHK: PCST Position               */\r
+#define CCU8_GPCHK_PCST_Msk                   (0x01UL << CCU8_GPCHK_PCST_Pos)                         /*!< CCU8 GPCHK: PCST Mask                   */\r
+#define CCU8_GPCHK_PCSEL0_Pos                 16                                                      /*!< CCU8 GPCHK: PCSEL0 Position             */\r
+#define CCU8_GPCHK_PCSEL0_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL0_Pos)                       /*!< CCU8 GPCHK: PCSEL0 Mask                 */\r
+#define CCU8_GPCHK_PCSEL1_Pos                 20                                                      /*!< CCU8 GPCHK: PCSEL1 Position             */\r
+#define CCU8_GPCHK_PCSEL1_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL1_Pos)                       /*!< CCU8 GPCHK: PCSEL1 Mask                 */\r
+#define CCU8_GPCHK_PCSEL2_Pos                 24                                                      /*!< CCU8 GPCHK: PCSEL2 Position             */\r
+#define CCU8_GPCHK_PCSEL2_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL2_Pos)                       /*!< CCU8 GPCHK: PCSEL2 Mask                 */\r
+#define CCU8_GPCHK_PCSEL3_Pos                 28                                                      /*!< CCU8 GPCHK: PCSEL3 Position             */\r
+#define CCU8_GPCHK_PCSEL3_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL3_Pos)                       /*!< CCU8 GPCHK: PCSEL3 Mask                 */\r
+\r
+/* ----------------------------------  CCU8_ECRD  --------------------------------- */\r
+#define CCU8_ECRD_CAPV_Pos                    0                                                       /*!< CCU8 ECRD: CAPV Position                */\r
+#define CCU8_ECRD_CAPV_Msk                    (0x0000ffffUL << CCU8_ECRD_CAPV_Pos)                    /*!< CCU8 ECRD: CAPV Mask                    */\r
+#define CCU8_ECRD_FPCV_Pos                    16                                                      /*!< CCU8 ECRD: FPCV Position                */\r
+#define CCU8_ECRD_FPCV_Msk                    (0x0fUL << CCU8_ECRD_FPCV_Pos)                          /*!< CCU8 ECRD: FPCV Mask                    */\r
+#define CCU8_ECRD_SPTR_Pos                    20                                                      /*!< CCU8 ECRD: SPTR Position                */\r
+#define CCU8_ECRD_SPTR_Msk                    (0x03UL << CCU8_ECRD_SPTR_Pos)                          /*!< CCU8 ECRD: SPTR Mask                    */\r
+#define CCU8_ECRD_VPTR_Pos                    22                                                      /*!< CCU8 ECRD: VPTR Position                */\r
+#define CCU8_ECRD_VPTR_Msk                    (0x03UL << CCU8_ECRD_VPTR_Pos)                          /*!< CCU8 ECRD: VPTR Mask                    */\r
+#define CCU8_ECRD_FFL_Pos                     24                                                      /*!< CCU8 ECRD: FFL Position                 */\r
+#define CCU8_ECRD_FFL_Msk                     (0x01UL << CCU8_ECRD_FFL_Pos)                           /*!< CCU8 ECRD: FFL Mask                     */\r
+\r
+/* ----------------------------------  CCU8_MIDR  --------------------------------- */\r
+#define CCU8_MIDR_MODR_Pos                    0                                                       /*!< CCU8 MIDR: MODR Position                */\r
+#define CCU8_MIDR_MODR_Msk                    (0x000000ffUL << CCU8_MIDR_MODR_Pos)                    /*!< CCU8 MIDR: MODR Mask                    */\r
+#define CCU8_MIDR_MODT_Pos                    8                                                       /*!< CCU8 MIDR: MODT Position                */\r
+#define CCU8_MIDR_MODT_Msk                    (0x000000ffUL << CCU8_MIDR_MODT_Pos)                    /*!< CCU8 MIDR: MODT Mask                    */\r
+#define CCU8_MIDR_MODN_Pos                    16                                                      /*!< CCU8 MIDR: MODN Position                */\r
+#define CCU8_MIDR_MODN_Msk                    (0x0000ffffUL << CCU8_MIDR_MODN_Pos)                    /*!< CCU8 MIDR: MODN Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        Group 'CCU8_CC8' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CCU8_CC8_INS  -------------------------------- */\r
+#define CCU8_CC8_INS_EV0IS_Pos                0                                                       /*!< CCU8_CC8 INS: EV0IS Position            */\r
+#define CCU8_CC8_INS_EV0IS_Msk                (0x0fUL << CCU8_CC8_INS_EV0IS_Pos)                      /*!< CCU8_CC8 INS: EV0IS Mask                */\r
+#define CCU8_CC8_INS_EV1IS_Pos                4                                                       /*!< CCU8_CC8 INS: EV1IS Position            */\r
+#define CCU8_CC8_INS_EV1IS_Msk                (0x0fUL << CCU8_CC8_INS_EV1IS_Pos)                      /*!< CCU8_CC8 INS: EV1IS Mask                */\r
+#define CCU8_CC8_INS_EV2IS_Pos                8                                                       /*!< CCU8_CC8 INS: EV2IS Position            */\r
+#define CCU8_CC8_INS_EV2IS_Msk                (0x0fUL << CCU8_CC8_INS_EV2IS_Pos)                      /*!< CCU8_CC8 INS: EV2IS Mask                */\r
+#define CCU8_CC8_INS_EV0EM_Pos                16                                                      /*!< CCU8_CC8 INS: EV0EM Position            */\r
+#define CCU8_CC8_INS_EV0EM_Msk                (0x03UL << CCU8_CC8_INS_EV0EM_Pos)                      /*!< CCU8_CC8 INS: EV0EM Mask                */\r
+#define CCU8_CC8_INS_EV1EM_Pos                18                                                      /*!< CCU8_CC8 INS: EV1EM Position            */\r
+#define CCU8_CC8_INS_EV1EM_Msk                (0x03UL << CCU8_CC8_INS_EV1EM_Pos)                      /*!< CCU8_CC8 INS: EV1EM Mask                */\r
+#define CCU8_CC8_INS_EV2EM_Pos                20                                                      /*!< CCU8_CC8 INS: EV2EM Position            */\r
+#define CCU8_CC8_INS_EV2EM_Msk                (0x03UL << CCU8_CC8_INS_EV2EM_Pos)                      /*!< CCU8_CC8 INS: EV2EM Mask                */\r
+#define CCU8_CC8_INS_EV0LM_Pos                22                                                      /*!< CCU8_CC8 INS: EV0LM Position            */\r
+#define CCU8_CC8_INS_EV0LM_Msk                (0x01UL << CCU8_CC8_INS_EV0LM_Pos)                      /*!< CCU8_CC8 INS: EV0LM Mask                */\r
+#define CCU8_CC8_INS_EV1LM_Pos                23                                                      /*!< CCU8_CC8 INS: EV1LM Position            */\r
+#define CCU8_CC8_INS_EV1LM_Msk                (0x01UL << CCU8_CC8_INS_EV1LM_Pos)                      /*!< CCU8_CC8 INS: EV1LM Mask                */\r
+#define CCU8_CC8_INS_EV2LM_Pos                24                                                      /*!< CCU8_CC8 INS: EV2LM Position            */\r
+#define CCU8_CC8_INS_EV2LM_Msk                (0x01UL << CCU8_CC8_INS_EV2LM_Pos)                      /*!< CCU8_CC8 INS: EV2LM Mask                */\r
+#define CCU8_CC8_INS_LPF0M_Pos                25                                                      /*!< CCU8_CC8 INS: LPF0M Position            */\r
+#define CCU8_CC8_INS_LPF0M_Msk                (0x03UL << CCU8_CC8_INS_LPF0M_Pos)                      /*!< CCU8_CC8 INS: LPF0M Mask                */\r
+#define CCU8_CC8_INS_LPF1M_Pos                27                                                      /*!< CCU8_CC8 INS: LPF1M Position            */\r
+#define CCU8_CC8_INS_LPF1M_Msk                (0x03UL << CCU8_CC8_INS_LPF1M_Pos)                      /*!< CCU8_CC8 INS: LPF1M Mask                */\r
+#define CCU8_CC8_INS_LPF2M_Pos                29                                                      /*!< CCU8_CC8 INS: LPF2M Position            */\r
+#define CCU8_CC8_INS_LPF2M_Msk                (0x03UL << CCU8_CC8_INS_LPF2M_Pos)                      /*!< CCU8_CC8 INS: LPF2M Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_CMC  -------------------------------- */\r
+#define CCU8_CC8_CMC_STRTS_Pos                0                                                       /*!< CCU8_CC8 CMC: STRTS Position            */\r
+#define CCU8_CC8_CMC_STRTS_Msk                (0x03UL << CCU8_CC8_CMC_STRTS_Pos)                      /*!< CCU8_CC8 CMC: STRTS Mask                */\r
+#define CCU8_CC8_CMC_ENDS_Pos                 2                                                       /*!< CCU8_CC8 CMC: ENDS Position             */\r
+#define CCU8_CC8_CMC_ENDS_Msk                 (0x03UL << CCU8_CC8_CMC_ENDS_Pos)                       /*!< CCU8_CC8 CMC: ENDS Mask                 */\r
+#define CCU8_CC8_CMC_CAP0S_Pos                4                                                       /*!< CCU8_CC8 CMC: CAP0S Position            */\r
+#define CCU8_CC8_CMC_CAP0S_Msk                (0x03UL << CCU8_CC8_CMC_CAP0S_Pos)                      /*!< CCU8_CC8 CMC: CAP0S Mask                */\r
+#define CCU8_CC8_CMC_CAP1S_Pos                6                                                       /*!< CCU8_CC8 CMC: CAP1S Position            */\r
+#define CCU8_CC8_CMC_CAP1S_Msk                (0x03UL << CCU8_CC8_CMC_CAP1S_Pos)                      /*!< CCU8_CC8 CMC: CAP1S Mask                */\r
+#define CCU8_CC8_CMC_GATES_Pos                8                                                       /*!< CCU8_CC8 CMC: GATES Position            */\r
+#define CCU8_CC8_CMC_GATES_Msk                (0x03UL << CCU8_CC8_CMC_GATES_Pos)                      /*!< CCU8_CC8 CMC: GATES Mask                */\r
+#define CCU8_CC8_CMC_UDS_Pos                  10                                                      /*!< CCU8_CC8 CMC: UDS Position              */\r
+#define CCU8_CC8_CMC_UDS_Msk                  (0x03UL << CCU8_CC8_CMC_UDS_Pos)                        /*!< CCU8_CC8 CMC: UDS Mask                  */\r
+#define CCU8_CC8_CMC_LDS_Pos                  12                                                      /*!< CCU8_CC8 CMC: LDS Position              */\r
+#define CCU8_CC8_CMC_LDS_Msk                  (0x03UL << CCU8_CC8_CMC_LDS_Pos)                        /*!< CCU8_CC8 CMC: LDS Mask                  */\r
+#define CCU8_CC8_CMC_CNTS_Pos                 14                                                      /*!< CCU8_CC8 CMC: CNTS Position             */\r
+#define CCU8_CC8_CMC_CNTS_Msk                 (0x03UL << CCU8_CC8_CMC_CNTS_Pos)                       /*!< CCU8_CC8 CMC: CNTS Mask                 */\r
+#define CCU8_CC8_CMC_OFS_Pos                  16                                                      /*!< CCU8_CC8 CMC: OFS Position              */\r
+#define CCU8_CC8_CMC_OFS_Msk                  (0x01UL << CCU8_CC8_CMC_OFS_Pos)                        /*!< CCU8_CC8 CMC: OFS Mask                  */\r
+#define CCU8_CC8_CMC_TS_Pos                   17                                                      /*!< CCU8_CC8 CMC: TS Position               */\r
+#define CCU8_CC8_CMC_TS_Msk                   (0x01UL << CCU8_CC8_CMC_TS_Pos)                         /*!< CCU8_CC8 CMC: TS Mask                   */\r
+#define CCU8_CC8_CMC_MOS_Pos                  18                                                      /*!< CCU8_CC8 CMC: MOS Position              */\r
+#define CCU8_CC8_CMC_MOS_Msk                  (0x03UL << CCU8_CC8_CMC_MOS_Pos)                        /*!< CCU8_CC8 CMC: MOS Mask                  */\r
+#define CCU8_CC8_CMC_TCE_Pos                  20                                                      /*!< CCU8_CC8 CMC: TCE Position              */\r
+#define CCU8_CC8_CMC_TCE_Msk                  (0x01UL << CCU8_CC8_CMC_TCE_Pos)                        /*!< CCU8_CC8 CMC: TCE Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_TCST  ------------------------------- */\r
+#define CCU8_CC8_TCST_TRB_Pos                 0                                                       /*!< CCU8_CC8 TCST: TRB Position             */\r
+#define CCU8_CC8_TCST_TRB_Msk                 (0x01UL << CCU8_CC8_TCST_TRB_Pos)                       /*!< CCU8_CC8 TCST: TRB Mask                 */\r
+#define CCU8_CC8_TCST_CDIR_Pos                1                                                       /*!< CCU8_CC8 TCST: CDIR Position            */\r
+#define CCU8_CC8_TCST_CDIR_Msk                (0x01UL << CCU8_CC8_TCST_CDIR_Pos)                      /*!< CCU8_CC8 TCST: CDIR Mask                */\r
+#define CCU8_CC8_TCST_DTR1_Pos                3                                                       /*!< CCU8_CC8 TCST: DTR1 Position            */\r
+#define CCU8_CC8_TCST_DTR1_Msk                (0x01UL << CCU8_CC8_TCST_DTR1_Pos)                      /*!< CCU8_CC8 TCST: DTR1 Mask                */\r
+#define CCU8_CC8_TCST_DTR2_Pos                4                                                       /*!< CCU8_CC8 TCST: DTR2 Position            */\r
+#define CCU8_CC8_TCST_DTR2_Msk                (0x01UL << CCU8_CC8_TCST_DTR2_Pos)                      /*!< CCU8_CC8 TCST: DTR2 Mask                */\r
+\r
+/* -------------------------------  CCU8_CC8_TCSET  ------------------------------- */\r
+#define CCU8_CC8_TCSET_TRBS_Pos               0                                                       /*!< CCU8_CC8 TCSET: TRBS Position           */\r
+#define CCU8_CC8_TCSET_TRBS_Msk               (0x01UL << CCU8_CC8_TCSET_TRBS_Pos)                     /*!< CCU8_CC8 TCSET: TRBS Mask               */\r
+\r
+/* -------------------------------  CCU8_CC8_TCCLR  ------------------------------- */\r
+#define CCU8_CC8_TCCLR_TRBC_Pos               0                                                       /*!< CCU8_CC8 TCCLR: TRBC Position           */\r
+#define CCU8_CC8_TCCLR_TRBC_Msk               (0x01UL << CCU8_CC8_TCCLR_TRBC_Pos)                     /*!< CCU8_CC8 TCCLR: TRBC Mask               */\r
+#define CCU8_CC8_TCCLR_TCC_Pos                1                                                       /*!< CCU8_CC8 TCCLR: TCC Position            */\r
+#define CCU8_CC8_TCCLR_TCC_Msk                (0x01UL << CCU8_CC8_TCCLR_TCC_Pos)                      /*!< CCU8_CC8 TCCLR: TCC Mask                */\r
+#define CCU8_CC8_TCCLR_DITC_Pos               2                                                       /*!< CCU8_CC8 TCCLR: DITC Position           */\r
+#define CCU8_CC8_TCCLR_DITC_Msk               (0x01UL << CCU8_CC8_TCCLR_DITC_Pos)                     /*!< CCU8_CC8 TCCLR: DITC Mask               */\r
+#define CCU8_CC8_TCCLR_DTC1C_Pos              3                                                       /*!< CCU8_CC8 TCCLR: DTC1C Position          */\r
+#define CCU8_CC8_TCCLR_DTC1C_Msk              (0x01UL << CCU8_CC8_TCCLR_DTC1C_Pos)                    /*!< CCU8_CC8 TCCLR: DTC1C Mask              */\r
+#define CCU8_CC8_TCCLR_DTC2C_Pos              4                                                       /*!< CCU8_CC8 TCCLR: DTC2C Position          */\r
+#define CCU8_CC8_TCCLR_DTC2C_Msk              (0x01UL << CCU8_CC8_TCCLR_DTC2C_Pos)                    /*!< CCU8_CC8 TCCLR: DTC2C Mask              */\r
+\r
+/* ---------------------------------  CCU8_CC8_TC  -------------------------------- */\r
+#define CCU8_CC8_TC_TCM_Pos                   0                                                       /*!< CCU8_CC8 TC: TCM Position               */\r
+#define CCU8_CC8_TC_TCM_Msk                   (0x01UL << CCU8_CC8_TC_TCM_Pos)                         /*!< CCU8_CC8 TC: TCM Mask                   */\r
+#define CCU8_CC8_TC_TSSM_Pos                  1                                                       /*!< CCU8_CC8 TC: TSSM Position              */\r
+#define CCU8_CC8_TC_TSSM_Msk                  (0x01UL << CCU8_CC8_TC_TSSM_Pos)                        /*!< CCU8_CC8 TC: TSSM Mask                  */\r
+#define CCU8_CC8_TC_CLST_Pos                  2                                                       /*!< CCU8_CC8 TC: CLST Position              */\r
+#define CCU8_CC8_TC_CLST_Msk                  (0x01UL << CCU8_CC8_TC_CLST_Pos)                        /*!< CCU8_CC8 TC: CLST Mask                  */\r
+#define CCU8_CC8_TC_CMOD_Pos                  3                                                       /*!< CCU8_CC8 TC: CMOD Position              */\r
+#define CCU8_CC8_TC_CMOD_Msk                  (0x01UL << CCU8_CC8_TC_CMOD_Pos)                        /*!< CCU8_CC8 TC: CMOD Mask                  */\r
+#define CCU8_CC8_TC_ECM_Pos                   4                                                       /*!< CCU8_CC8 TC: ECM Position               */\r
+#define CCU8_CC8_TC_ECM_Msk                   (0x01UL << CCU8_CC8_TC_ECM_Pos)                         /*!< CCU8_CC8 TC: ECM Mask                   */\r
+#define CCU8_CC8_TC_CAPC_Pos                  5                                                       /*!< CCU8_CC8 TC: CAPC Position              */\r
+#define CCU8_CC8_TC_CAPC_Msk                  (0x03UL << CCU8_CC8_TC_CAPC_Pos)                        /*!< CCU8_CC8 TC: CAPC Mask                  */\r
+#define CCU8_CC8_TC_TLS_Pos                   7                                                       /*!< CCU8_CC8 TC: TLS Position               */\r
+#define CCU8_CC8_TC_TLS_Msk                   (0x01UL << CCU8_CC8_TC_TLS_Pos)                         /*!< CCU8_CC8 TC: TLS Mask                   */\r
+#define CCU8_CC8_TC_ENDM_Pos                  8                                                       /*!< CCU8_CC8 TC: ENDM Position              */\r
+#define CCU8_CC8_TC_ENDM_Msk                  (0x03UL << CCU8_CC8_TC_ENDM_Pos)                        /*!< CCU8_CC8 TC: ENDM Mask                  */\r
+#define CCU8_CC8_TC_STRM_Pos                  10                                                      /*!< CCU8_CC8 TC: STRM Position              */\r
+#define CCU8_CC8_TC_STRM_Msk                  (0x01UL << CCU8_CC8_TC_STRM_Pos)                        /*!< CCU8_CC8 TC: STRM Mask                  */\r
+#define CCU8_CC8_TC_SCE_Pos                   11                                                      /*!< CCU8_CC8 TC: SCE Position               */\r
+#define CCU8_CC8_TC_SCE_Msk                   (0x01UL << CCU8_CC8_TC_SCE_Pos)                         /*!< CCU8_CC8 TC: SCE Mask                   */\r
+#define CCU8_CC8_TC_CCS_Pos                   12                                                      /*!< CCU8_CC8 TC: CCS Position               */\r
+#define CCU8_CC8_TC_CCS_Msk                   (0x01UL << CCU8_CC8_TC_CCS_Pos)                         /*!< CCU8_CC8 TC: CCS Mask                   */\r
+#define CCU8_CC8_TC_DITHE_Pos                 13                                                      /*!< CCU8_CC8 TC: DITHE Position             */\r
+#define CCU8_CC8_TC_DITHE_Msk                 (0x03UL << CCU8_CC8_TC_DITHE_Pos)                       /*!< CCU8_CC8 TC: DITHE Mask                 */\r
+#define CCU8_CC8_TC_DIM_Pos                   15                                                      /*!< CCU8_CC8 TC: DIM Position               */\r
+#define CCU8_CC8_TC_DIM_Msk                   (0x01UL << CCU8_CC8_TC_DIM_Pos)                         /*!< CCU8_CC8 TC: DIM Mask                   */\r
+#define CCU8_CC8_TC_FPE_Pos                   16                                                      /*!< CCU8_CC8 TC: FPE Position               */\r
+#define CCU8_CC8_TC_FPE_Msk                   (0x01UL << CCU8_CC8_TC_FPE_Pos)                         /*!< CCU8_CC8 TC: FPE Mask                   */\r
+#define CCU8_CC8_TC_TRAPE0_Pos                17                                                      /*!< CCU8_CC8 TC: TRAPE0 Position            */\r
+#define CCU8_CC8_TC_TRAPE0_Msk                (0x01UL << CCU8_CC8_TC_TRAPE0_Pos)                      /*!< CCU8_CC8 TC: TRAPE0 Mask                */\r
+#define CCU8_CC8_TC_TRAPE1_Pos                18                                                      /*!< CCU8_CC8 TC: TRAPE1 Position            */\r
+#define CCU8_CC8_TC_TRAPE1_Msk                (0x01UL << CCU8_CC8_TC_TRAPE1_Pos)                      /*!< CCU8_CC8 TC: TRAPE1 Mask                */\r
+#define CCU8_CC8_TC_TRAPE2_Pos                19                                                      /*!< CCU8_CC8 TC: TRAPE2 Position            */\r
+#define CCU8_CC8_TC_TRAPE2_Msk                (0x01UL << CCU8_CC8_TC_TRAPE2_Pos)                      /*!< CCU8_CC8 TC: TRAPE2 Mask                */\r
+#define CCU8_CC8_TC_TRAPE3_Pos                20                                                      /*!< CCU8_CC8 TC: TRAPE3 Position            */\r
+#define CCU8_CC8_TC_TRAPE3_Msk                (0x01UL << CCU8_CC8_TC_TRAPE3_Pos)                      /*!< CCU8_CC8 TC: TRAPE3 Mask                */\r
+#define CCU8_CC8_TC_TRPSE_Pos                 21                                                      /*!< CCU8_CC8 TC: TRPSE Position             */\r
+#define CCU8_CC8_TC_TRPSE_Msk                 (0x01UL << CCU8_CC8_TC_TRPSE_Pos)                       /*!< CCU8_CC8 TC: TRPSE Mask                 */\r
+#define CCU8_CC8_TC_TRPSW_Pos                 22                                                      /*!< CCU8_CC8 TC: TRPSW Position             */\r
+#define CCU8_CC8_TC_TRPSW_Msk                 (0x01UL << CCU8_CC8_TC_TRPSW_Pos)                       /*!< CCU8_CC8 TC: TRPSW Mask                 */\r
+#define CCU8_CC8_TC_EMS_Pos                   23                                                      /*!< CCU8_CC8 TC: EMS Position               */\r
+#define CCU8_CC8_TC_EMS_Msk                   (0x01UL << CCU8_CC8_TC_EMS_Pos)                         /*!< CCU8_CC8 TC: EMS Mask                   */\r
+#define CCU8_CC8_TC_EMT_Pos                   24                                                      /*!< CCU8_CC8 TC: EMT Position               */\r
+#define CCU8_CC8_TC_EMT_Msk                   (0x01UL << CCU8_CC8_TC_EMT_Pos)                         /*!< CCU8_CC8 TC: EMT Mask                   */\r
+#define CCU8_CC8_TC_MCME1_Pos                 25                                                      /*!< CCU8_CC8 TC: MCME1 Position             */\r
+#define CCU8_CC8_TC_MCME1_Msk                 (0x01UL << CCU8_CC8_TC_MCME1_Pos)                       /*!< CCU8_CC8 TC: MCME1 Mask                 */\r
+#define CCU8_CC8_TC_MCME2_Pos                 26                                                      /*!< CCU8_CC8 TC: MCME2 Position             */\r
+#define CCU8_CC8_TC_MCME2_Msk                 (0x01UL << CCU8_CC8_TC_MCME2_Pos)                       /*!< CCU8_CC8 TC: MCME2 Mask                 */\r
+#define CCU8_CC8_TC_EME_Pos                   27                                                      /*!< CCU8_CC8 TC: EME Position               */\r
+#define CCU8_CC8_TC_EME_Msk                   (0x03UL << CCU8_CC8_TC_EME_Pos)                         /*!< CCU8_CC8 TC: EME Mask                   */\r
+#define CCU8_CC8_TC_STOS_Pos                  29                                                      /*!< CCU8_CC8 TC: STOS Position              */\r
+#define CCU8_CC8_TC_STOS_Msk                  (0x03UL << CCU8_CC8_TC_STOS_Pos)                        /*!< CCU8_CC8 TC: STOS Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_PSL  -------------------------------- */\r
+#define CCU8_CC8_PSL_PSL11_Pos                0                                                       /*!< CCU8_CC8 PSL: PSL11 Position            */\r
+#define CCU8_CC8_PSL_PSL11_Msk                (0x01UL << CCU8_CC8_PSL_PSL11_Pos)                      /*!< CCU8_CC8 PSL: PSL11 Mask                */\r
+#define CCU8_CC8_PSL_PSL12_Pos                1                                                       /*!< CCU8_CC8 PSL: PSL12 Position            */\r
+#define CCU8_CC8_PSL_PSL12_Msk                (0x01UL << CCU8_CC8_PSL_PSL12_Pos)                      /*!< CCU8_CC8 PSL: PSL12 Mask                */\r
+#define CCU8_CC8_PSL_PSL21_Pos                2                                                       /*!< CCU8_CC8 PSL: PSL21 Position            */\r
+#define CCU8_CC8_PSL_PSL21_Msk                (0x01UL << CCU8_CC8_PSL_PSL21_Pos)                      /*!< CCU8_CC8 PSL: PSL21 Mask                */\r
+#define CCU8_CC8_PSL_PSL22_Pos                3                                                       /*!< CCU8_CC8 PSL: PSL22 Position            */\r
+#define CCU8_CC8_PSL_PSL22_Msk                (0x01UL << CCU8_CC8_PSL_PSL22_Pos)                      /*!< CCU8_CC8 PSL: PSL22 Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_DIT  -------------------------------- */\r
+#define CCU8_CC8_DIT_DCV_Pos                  0                                                       /*!< CCU8_CC8 DIT: DCV Position              */\r
+#define CCU8_CC8_DIT_DCV_Msk                  (0x0fUL << CCU8_CC8_DIT_DCV_Pos)                        /*!< CCU8_CC8 DIT: DCV Mask                  */\r
+#define CCU8_CC8_DIT_DCNT_Pos                 8                                                       /*!< CCU8_CC8 DIT: DCNT Position             */\r
+#define CCU8_CC8_DIT_DCNT_Msk                 (0x0fUL << CCU8_CC8_DIT_DCNT_Pos)                       /*!< CCU8_CC8 DIT: DCNT Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_DITS  ------------------------------- */\r
+#define CCU8_CC8_DITS_DCVS_Pos                0                                                       /*!< CCU8_CC8 DITS: DCVS Position            */\r
+#define CCU8_CC8_DITS_DCVS_Msk                (0x0fUL << CCU8_CC8_DITS_DCVS_Pos)                      /*!< CCU8_CC8 DITS: DCVS Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_PSC  -------------------------------- */\r
+#define CCU8_CC8_PSC_PSIV_Pos                 0                                                       /*!< CCU8_CC8 PSC: PSIV Position             */\r
+#define CCU8_CC8_PSC_PSIV_Msk                 (0x0fUL << CCU8_CC8_PSC_PSIV_Pos)                       /*!< CCU8_CC8 PSC: PSIV Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_FPC  -------------------------------- */\r
+#define CCU8_CC8_FPC_PCMP_Pos                 0                                                       /*!< CCU8_CC8 FPC: PCMP Position             */\r
+#define CCU8_CC8_FPC_PCMP_Msk                 (0x0fUL << CCU8_CC8_FPC_PCMP_Pos)                       /*!< CCU8_CC8 FPC: PCMP Mask                 */\r
+#define CCU8_CC8_FPC_PVAL_Pos                 8                                                       /*!< CCU8_CC8 FPC: PVAL Position             */\r
+#define CCU8_CC8_FPC_PVAL_Msk                 (0x0fUL << CCU8_CC8_FPC_PVAL_Pos)                       /*!< CCU8_CC8 FPC: PVAL Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_FPCS  ------------------------------- */\r
+#define CCU8_CC8_FPCS_PCMP_Pos                0                                                       /*!< CCU8_CC8 FPCS: PCMP Position            */\r
+#define CCU8_CC8_FPCS_PCMP_Msk                (0x0fUL << CCU8_CC8_FPCS_PCMP_Pos)                      /*!< CCU8_CC8 FPCS: PCMP Mask                */\r
+\r
+/* ---------------------------------  CCU8_CC8_PR  -------------------------------- */\r
+#define CCU8_CC8_PR_PR_Pos                    0                                                       /*!< CCU8_CC8 PR: PR Position                */\r
+#define CCU8_CC8_PR_PR_Msk                    (0x0000ffffUL << CCU8_CC8_PR_PR_Pos)                    /*!< CCU8_CC8 PR: PR Mask                    */\r
+\r
+/* --------------------------------  CCU8_CC8_PRS  -------------------------------- */\r
+#define CCU8_CC8_PRS_PRS_Pos                  0                                                       /*!< CCU8_CC8 PRS: PRS Position              */\r
+#define CCU8_CC8_PRS_PRS_Msk                  (0x0000ffffUL << CCU8_CC8_PRS_PRS_Pos)                  /*!< CCU8_CC8 PRS: PRS Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_CR1  -------------------------------- */\r
+#define CCU8_CC8_CR1_CR1_Pos                  0                                                       /*!< CCU8_CC8 CR1: CR1 Position              */\r
+#define CCU8_CC8_CR1_CR1_Msk                  (0x0000ffffUL << CCU8_CC8_CR1_CR1_Pos)                  /*!< CCU8_CC8 CR1: CR1 Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_CR1S  ------------------------------- */\r
+#define CCU8_CC8_CR1S_CR1S_Pos                0                                                       /*!< CCU8_CC8 CR1S: CR1S Position            */\r
+#define CCU8_CC8_CR1S_CR1S_Msk                (0x0000ffffUL << CCU8_CC8_CR1S_CR1S_Pos)                /*!< CCU8_CC8 CR1S: CR1S Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_CR2  -------------------------------- */\r
+#define CCU8_CC8_CR2_CR2_Pos                  0                                                       /*!< CCU8_CC8 CR2: CR2 Position              */\r
+#define CCU8_CC8_CR2_CR2_Msk                  (0x0000ffffUL << CCU8_CC8_CR2_CR2_Pos)                  /*!< CCU8_CC8 CR2: CR2 Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_CR2S  ------------------------------- */\r
+#define CCU8_CC8_CR2S_CR2S_Pos                0                                                       /*!< CCU8_CC8 CR2S: CR2S Position            */\r
+#define CCU8_CC8_CR2S_CR2S_Msk                (0x0000ffffUL << CCU8_CC8_CR2S_CR2S_Pos)                /*!< CCU8_CC8 CR2S: CR2S Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_CHC  -------------------------------- */\r
+#define CCU8_CC8_CHC_ASE_Pos                  0                                                       /*!< CCU8_CC8 CHC: ASE Position              */\r
+#define CCU8_CC8_CHC_ASE_Msk                  (0x01UL << CCU8_CC8_CHC_ASE_Pos)                        /*!< CCU8_CC8 CHC: ASE Mask                  */\r
+#define CCU8_CC8_CHC_OCS1_Pos                 1                                                       /*!< CCU8_CC8 CHC: OCS1 Position             */\r
+#define CCU8_CC8_CHC_OCS1_Msk                 (0x01UL << CCU8_CC8_CHC_OCS1_Pos)                       /*!< CCU8_CC8 CHC: OCS1 Mask                 */\r
+#define CCU8_CC8_CHC_OCS2_Pos                 2                                                       /*!< CCU8_CC8 CHC: OCS2 Position             */\r
+#define CCU8_CC8_CHC_OCS2_Msk                 (0x01UL << CCU8_CC8_CHC_OCS2_Pos)                       /*!< CCU8_CC8 CHC: OCS2 Mask                 */\r
+#define CCU8_CC8_CHC_OCS3_Pos                 3                                                       /*!< CCU8_CC8 CHC: OCS3 Position             */\r
+#define CCU8_CC8_CHC_OCS3_Msk                 (0x01UL << CCU8_CC8_CHC_OCS3_Pos)                       /*!< CCU8_CC8 CHC: OCS3 Mask                 */\r
+#define CCU8_CC8_CHC_OCS4_Pos                 4                                                       /*!< CCU8_CC8 CHC: OCS4 Position             */\r
+#define CCU8_CC8_CHC_OCS4_Msk                 (0x01UL << CCU8_CC8_CHC_OCS4_Pos)                       /*!< CCU8_CC8 CHC: OCS4 Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_DTC  -------------------------------- */\r
+#define CCU8_CC8_DTC_DTE1_Pos                 0                                                       /*!< CCU8_CC8 DTC: DTE1 Position             */\r
+#define CCU8_CC8_DTC_DTE1_Msk                 (0x01UL << CCU8_CC8_DTC_DTE1_Pos)                       /*!< CCU8_CC8 DTC: DTE1 Mask                 */\r
+#define CCU8_CC8_DTC_DTE2_Pos                 1                                                       /*!< CCU8_CC8 DTC: DTE2 Position             */\r
+#define CCU8_CC8_DTC_DTE2_Msk                 (0x01UL << CCU8_CC8_DTC_DTE2_Pos)                       /*!< CCU8_CC8 DTC: DTE2 Mask                 */\r
+#define CCU8_CC8_DTC_DCEN1_Pos                2                                                       /*!< CCU8_CC8 DTC: DCEN1 Position            */\r
+#define CCU8_CC8_DTC_DCEN1_Msk                (0x01UL << CCU8_CC8_DTC_DCEN1_Pos)                      /*!< CCU8_CC8 DTC: DCEN1 Mask                */\r
+#define CCU8_CC8_DTC_DCEN2_Pos                3                                                       /*!< CCU8_CC8 DTC: DCEN2 Position            */\r
+#define CCU8_CC8_DTC_DCEN2_Msk                (0x01UL << CCU8_CC8_DTC_DCEN2_Pos)                      /*!< CCU8_CC8 DTC: DCEN2 Mask                */\r
+#define CCU8_CC8_DTC_DCEN3_Pos                4                                                       /*!< CCU8_CC8 DTC: DCEN3 Position            */\r
+#define CCU8_CC8_DTC_DCEN3_Msk                (0x01UL << CCU8_CC8_DTC_DCEN3_Pos)                      /*!< CCU8_CC8 DTC: DCEN3 Mask                */\r
+#define CCU8_CC8_DTC_DCEN4_Pos                5                                                       /*!< CCU8_CC8 DTC: DCEN4 Position            */\r
+#define CCU8_CC8_DTC_DCEN4_Msk                (0x01UL << CCU8_CC8_DTC_DCEN4_Pos)                      /*!< CCU8_CC8 DTC: DCEN4 Mask                */\r
+#define CCU8_CC8_DTC_DTCC_Pos                 6                                                       /*!< CCU8_CC8 DTC: DTCC Position             */\r
+#define CCU8_CC8_DTC_DTCC_Msk                 (0x03UL << CCU8_CC8_DTC_DTCC_Pos)                       /*!< CCU8_CC8 DTC: DTCC Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_DC1R  ------------------------------- */\r
+#define CCU8_CC8_DC1R_DT1R_Pos                0                                                       /*!< CCU8_CC8 DC1R: DT1R Position            */\r
+#define CCU8_CC8_DC1R_DT1R_Msk                (0x000000ffUL << CCU8_CC8_DC1R_DT1R_Pos)                /*!< CCU8_CC8 DC1R: DT1R Mask                */\r
+#define CCU8_CC8_DC1R_DT1F_Pos                8                                                       /*!< CCU8_CC8 DC1R: DT1F Position            */\r
+#define CCU8_CC8_DC1R_DT1F_Msk                (0x000000ffUL << CCU8_CC8_DC1R_DT1F_Pos)                /*!< CCU8_CC8 DC1R: DT1F Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_DC2R  ------------------------------- */\r
+#define CCU8_CC8_DC2R_DT2R_Pos                0                                                       /*!< CCU8_CC8 DC2R: DT2R Position            */\r
+#define CCU8_CC8_DC2R_DT2R_Msk                (0x000000ffUL << CCU8_CC8_DC2R_DT2R_Pos)                /*!< CCU8_CC8 DC2R: DT2R Mask                */\r
+#define CCU8_CC8_DC2R_DT2F_Pos                8                                                       /*!< CCU8_CC8 DC2R: DT2F Position            */\r
+#define CCU8_CC8_DC2R_DT2F_Msk                (0x000000ffUL << CCU8_CC8_DC2R_DT2F_Pos)                /*!< CCU8_CC8 DC2R: DT2F Mask                */\r
+\r
+/* -------------------------------  CCU8_CC8_TIMER  ------------------------------- */\r
+#define CCU8_CC8_TIMER_TVAL_Pos               0                                                       /*!< CCU8_CC8 TIMER: TVAL Position           */\r
+#define CCU8_CC8_TIMER_TVAL_Msk               (0x0000ffffUL << CCU8_CC8_TIMER_TVAL_Pos)               /*!< CCU8_CC8 TIMER: TVAL Mask               */\r
+\r
+/* ---------------------------------  CCU8_CC8_CV  -------------------------------- */\r
+#define CCU8_CC8_CV_CAPTV_Pos                 0                                                       /*!< CCU8_CC8 CV: CAPTV Position             */\r
+#define CCU8_CC8_CV_CAPTV_Msk                 (0x0000ffffUL << CCU8_CC8_CV_CAPTV_Pos)                 /*!< CCU8_CC8 CV: CAPTV Mask                 */\r
+#define CCU8_CC8_CV_FPCV_Pos                  16                                                      /*!< CCU8_CC8 CV: FPCV Position              */\r
+#define CCU8_CC8_CV_FPCV_Msk                  (0x0fUL << CCU8_CC8_CV_FPCV_Pos)                        /*!< CCU8_CC8 CV: FPCV Mask                  */\r
+#define CCU8_CC8_CV_FFL_Pos                   20                                                      /*!< CCU8_CC8 CV: FFL Position               */\r
+#define CCU8_CC8_CV_FFL_Msk                   (0x01UL << CCU8_CC8_CV_FFL_Pos)                         /*!< CCU8_CC8 CV: FFL Mask                   */\r
+\r
+/* --------------------------------  CCU8_CC8_INTS  ------------------------------- */\r
+#define CCU8_CC8_INTS_PMUS_Pos                0                                                       /*!< CCU8_CC8 INTS: PMUS Position            */\r
+#define CCU8_CC8_INTS_PMUS_Msk                (0x01UL << CCU8_CC8_INTS_PMUS_Pos)                      /*!< CCU8_CC8 INTS: PMUS Mask                */\r
+#define CCU8_CC8_INTS_OMDS_Pos                1                                                       /*!< CCU8_CC8 INTS: OMDS Position            */\r
+#define CCU8_CC8_INTS_OMDS_Msk                (0x01UL << CCU8_CC8_INTS_OMDS_Pos)                      /*!< CCU8_CC8 INTS: OMDS Mask                */\r
+#define CCU8_CC8_INTS_CMU1S_Pos               2                                                       /*!< CCU8_CC8 INTS: CMU1S Position           */\r
+#define CCU8_CC8_INTS_CMU1S_Msk               (0x01UL << CCU8_CC8_INTS_CMU1S_Pos)                     /*!< CCU8_CC8 INTS: CMU1S Mask               */\r
+#define CCU8_CC8_INTS_CMD1S_Pos               3                                                       /*!< CCU8_CC8 INTS: CMD1S Position           */\r
+#define CCU8_CC8_INTS_CMD1S_Msk               (0x01UL << CCU8_CC8_INTS_CMD1S_Pos)                     /*!< CCU8_CC8 INTS: CMD1S Mask               */\r
+#define CCU8_CC8_INTS_CMU2S_Pos               4                                                       /*!< CCU8_CC8 INTS: CMU2S Position           */\r
+#define CCU8_CC8_INTS_CMU2S_Msk               (0x01UL << CCU8_CC8_INTS_CMU2S_Pos)                     /*!< CCU8_CC8 INTS: CMU2S Mask               */\r
+#define CCU8_CC8_INTS_CMD2S_Pos               5                                                       /*!< CCU8_CC8 INTS: CMD2S Position           */\r
+#define CCU8_CC8_INTS_CMD2S_Msk               (0x01UL << CCU8_CC8_INTS_CMD2S_Pos)                     /*!< CCU8_CC8 INTS: CMD2S Mask               */\r
+#define CCU8_CC8_INTS_E0AS_Pos                8                                                       /*!< CCU8_CC8 INTS: E0AS Position            */\r
+#define CCU8_CC8_INTS_E0AS_Msk                (0x01UL << CCU8_CC8_INTS_E0AS_Pos)                      /*!< CCU8_CC8 INTS: E0AS Mask                */\r
+#define CCU8_CC8_INTS_E1AS_Pos                9                                                       /*!< CCU8_CC8 INTS: E1AS Position            */\r
+#define CCU8_CC8_INTS_E1AS_Msk                (0x01UL << CCU8_CC8_INTS_E1AS_Pos)                      /*!< CCU8_CC8 INTS: E1AS Mask                */\r
+#define CCU8_CC8_INTS_E2AS_Pos                10                                                      /*!< CCU8_CC8 INTS: E2AS Position            */\r
+#define CCU8_CC8_INTS_E2AS_Msk                (0x01UL << CCU8_CC8_INTS_E2AS_Pos)                      /*!< CCU8_CC8 INTS: E2AS Mask                */\r
+#define CCU8_CC8_INTS_TRPF_Pos                11                                                      /*!< CCU8_CC8 INTS: TRPF Position            */\r
+#define CCU8_CC8_INTS_TRPF_Msk                (0x01UL << CCU8_CC8_INTS_TRPF_Pos)                      /*!< CCU8_CC8 INTS: TRPF Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_INTE  ------------------------------- */\r
+#define CCU8_CC8_INTE_PME_Pos                 0                                                       /*!< CCU8_CC8 INTE: PME Position             */\r
+#define CCU8_CC8_INTE_PME_Msk                 (0x01UL << CCU8_CC8_INTE_PME_Pos)                       /*!< CCU8_CC8 INTE: PME Mask                 */\r
+#define CCU8_CC8_INTE_OME_Pos                 1                                                       /*!< CCU8_CC8 INTE: OME Position             */\r
+#define CCU8_CC8_INTE_OME_Msk                 (0x01UL << CCU8_CC8_INTE_OME_Pos)                       /*!< CCU8_CC8 INTE: OME Mask                 */\r
+#define CCU8_CC8_INTE_CMU1E_Pos               2                                                       /*!< CCU8_CC8 INTE: CMU1E Position           */\r
+#define CCU8_CC8_INTE_CMU1E_Msk               (0x01UL << CCU8_CC8_INTE_CMU1E_Pos)                     /*!< CCU8_CC8 INTE: CMU1E Mask               */\r
+#define CCU8_CC8_INTE_CMD1E_Pos               3                                                       /*!< CCU8_CC8 INTE: CMD1E Position           */\r
+#define CCU8_CC8_INTE_CMD1E_Msk               (0x01UL << CCU8_CC8_INTE_CMD1E_Pos)                     /*!< CCU8_CC8 INTE: CMD1E Mask               */\r
+#define CCU8_CC8_INTE_CMU2E_Pos               4                                                       /*!< CCU8_CC8 INTE: CMU2E Position           */\r
+#define CCU8_CC8_INTE_CMU2E_Msk               (0x01UL << CCU8_CC8_INTE_CMU2E_Pos)                     /*!< CCU8_CC8 INTE: CMU2E Mask               */\r
+#define CCU8_CC8_INTE_CMD2E_Pos               5                                                       /*!< CCU8_CC8 INTE: CMD2E Position           */\r
+#define CCU8_CC8_INTE_CMD2E_Msk               (0x01UL << CCU8_CC8_INTE_CMD2E_Pos)                     /*!< CCU8_CC8 INTE: CMD2E Mask               */\r
+#define CCU8_CC8_INTE_E0AE_Pos                8                                                       /*!< CCU8_CC8 INTE: E0AE Position            */\r
+#define CCU8_CC8_INTE_E0AE_Msk                (0x01UL << CCU8_CC8_INTE_E0AE_Pos)                      /*!< CCU8_CC8 INTE: E0AE Mask                */\r
+#define CCU8_CC8_INTE_E1AE_Pos                9                                                       /*!< CCU8_CC8 INTE: E1AE Position            */\r
+#define CCU8_CC8_INTE_E1AE_Msk                (0x01UL << CCU8_CC8_INTE_E1AE_Pos)                      /*!< CCU8_CC8 INTE: E1AE Mask                */\r
+#define CCU8_CC8_INTE_E2AE_Pos                10                                                      /*!< CCU8_CC8 INTE: E2AE Position            */\r
+#define CCU8_CC8_INTE_E2AE_Msk                (0x01UL << CCU8_CC8_INTE_E2AE_Pos)                      /*!< CCU8_CC8 INTE: E2AE Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_SRS  -------------------------------- */\r
+#define CCU8_CC8_SRS_POSR_Pos                 0                                                       /*!< CCU8_CC8 SRS: POSR Position             */\r
+#define CCU8_CC8_SRS_POSR_Msk                 (0x03UL << CCU8_CC8_SRS_POSR_Pos)                       /*!< CCU8_CC8 SRS: POSR Mask                 */\r
+#define CCU8_CC8_SRS_CM1SR_Pos                2                                                       /*!< CCU8_CC8 SRS: CM1SR Position            */\r
+#define CCU8_CC8_SRS_CM1SR_Msk                (0x03UL << CCU8_CC8_SRS_CM1SR_Pos)                      /*!< CCU8_CC8 SRS: CM1SR Mask                */\r
+#define CCU8_CC8_SRS_CM2SR_Pos                4                                                       /*!< CCU8_CC8 SRS: CM2SR Position            */\r
+#define CCU8_CC8_SRS_CM2SR_Msk                (0x03UL << CCU8_CC8_SRS_CM2SR_Pos)                      /*!< CCU8_CC8 SRS: CM2SR Mask                */\r
+#define CCU8_CC8_SRS_E0SR_Pos                 8                                                       /*!< CCU8_CC8 SRS: E0SR Position             */\r
+#define CCU8_CC8_SRS_E0SR_Msk                 (0x03UL << CCU8_CC8_SRS_E0SR_Pos)                       /*!< CCU8_CC8 SRS: E0SR Mask                 */\r
+#define CCU8_CC8_SRS_E1SR_Pos                 10                                                      /*!< CCU8_CC8 SRS: E1SR Position             */\r
+#define CCU8_CC8_SRS_E1SR_Msk                 (0x03UL << CCU8_CC8_SRS_E1SR_Pos)                       /*!< CCU8_CC8 SRS: E1SR Mask                 */\r
+#define CCU8_CC8_SRS_E2SR_Pos                 12                                                      /*!< CCU8_CC8 SRS: E2SR Position             */\r
+#define CCU8_CC8_SRS_E2SR_Msk                 (0x03UL << CCU8_CC8_SRS_E2SR_Pos)                       /*!< CCU8_CC8 SRS: E2SR Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_SWS  -------------------------------- */\r
+#define CCU8_CC8_SWS_SPM_Pos                  0                                                       /*!< CCU8_CC8 SWS: SPM Position              */\r
+#define CCU8_CC8_SWS_SPM_Msk                  (0x01UL << CCU8_CC8_SWS_SPM_Pos)                        /*!< CCU8_CC8 SWS: SPM Mask                  */\r
+#define CCU8_CC8_SWS_SOM_Pos                  1                                                       /*!< CCU8_CC8 SWS: SOM Position              */\r
+#define CCU8_CC8_SWS_SOM_Msk                  (0x01UL << CCU8_CC8_SWS_SOM_Pos)                        /*!< CCU8_CC8 SWS: SOM Mask                  */\r
+#define CCU8_CC8_SWS_SCM1U_Pos                2                                                       /*!< CCU8_CC8 SWS: SCM1U Position            */\r
+#define CCU8_CC8_SWS_SCM1U_Msk                (0x01UL << CCU8_CC8_SWS_SCM1U_Pos)                      /*!< CCU8_CC8 SWS: SCM1U Mask                */\r
+#define CCU8_CC8_SWS_SCM1D_Pos                3                                                       /*!< CCU8_CC8 SWS: SCM1D Position            */\r
+#define CCU8_CC8_SWS_SCM1D_Msk                (0x01UL << CCU8_CC8_SWS_SCM1D_Pos)                      /*!< CCU8_CC8 SWS: SCM1D Mask                */\r
+#define CCU8_CC8_SWS_SCM2U_Pos                4                                                       /*!< CCU8_CC8 SWS: SCM2U Position            */\r
+#define CCU8_CC8_SWS_SCM2U_Msk                (0x01UL << CCU8_CC8_SWS_SCM2U_Pos)                      /*!< CCU8_CC8 SWS: SCM2U Mask                */\r
+#define CCU8_CC8_SWS_SCM2D_Pos                5                                                       /*!< CCU8_CC8 SWS: SCM2D Position            */\r
+#define CCU8_CC8_SWS_SCM2D_Msk                (0x01UL << CCU8_CC8_SWS_SCM2D_Pos)                      /*!< CCU8_CC8 SWS: SCM2D Mask                */\r
+#define CCU8_CC8_SWS_SE0A_Pos                 8                                                       /*!< CCU8_CC8 SWS: SE0A Position             */\r
+#define CCU8_CC8_SWS_SE0A_Msk                 (0x01UL << CCU8_CC8_SWS_SE0A_Pos)                       /*!< CCU8_CC8 SWS: SE0A Mask                 */\r
+#define CCU8_CC8_SWS_SE1A_Pos                 9                                                       /*!< CCU8_CC8 SWS: SE1A Position             */\r
+#define CCU8_CC8_SWS_SE1A_Msk                 (0x01UL << CCU8_CC8_SWS_SE1A_Pos)                       /*!< CCU8_CC8 SWS: SE1A Mask                 */\r
+#define CCU8_CC8_SWS_SE2A_Pos                 10                                                      /*!< CCU8_CC8 SWS: SE2A Position             */\r
+#define CCU8_CC8_SWS_SE2A_Msk                 (0x01UL << CCU8_CC8_SWS_SE2A_Pos)                       /*!< CCU8_CC8 SWS: SE2A Mask                 */\r
+#define CCU8_CC8_SWS_STRPF_Pos                11                                                      /*!< CCU8_CC8 SWS: STRPF Position            */\r
+#define CCU8_CC8_SWS_STRPF_Msk                (0x01UL << CCU8_CC8_SWS_STRPF_Pos)                      /*!< CCU8_CC8 SWS: STRPF Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_SWR  -------------------------------- */\r
+#define CCU8_CC8_SWR_RPM_Pos                  0                                                       /*!< CCU8_CC8 SWR: RPM Position              */\r
+#define CCU8_CC8_SWR_RPM_Msk                  (0x01UL << CCU8_CC8_SWR_RPM_Pos)                        /*!< CCU8_CC8 SWR: RPM Mask                  */\r
+#define CCU8_CC8_SWR_ROM_Pos                  1                                                       /*!< CCU8_CC8 SWR: ROM Position              */\r
+#define CCU8_CC8_SWR_ROM_Msk                  (0x01UL << CCU8_CC8_SWR_ROM_Pos)                        /*!< CCU8_CC8 SWR: ROM Mask                  */\r
+#define CCU8_CC8_SWR_RCM1U_Pos                2                                                       /*!< CCU8_CC8 SWR: RCM1U Position            */\r
+#define CCU8_CC8_SWR_RCM1U_Msk                (0x01UL << CCU8_CC8_SWR_RCM1U_Pos)                      /*!< CCU8_CC8 SWR: RCM1U Mask                */\r
+#define CCU8_CC8_SWR_RCM1D_Pos                3                                                       /*!< CCU8_CC8 SWR: RCM1D Position            */\r
+#define CCU8_CC8_SWR_RCM1D_Msk                (0x01UL << CCU8_CC8_SWR_RCM1D_Pos)                      /*!< CCU8_CC8 SWR: RCM1D Mask                */\r
+#define CCU8_CC8_SWR_RCM2U_Pos                4                                                       /*!< CCU8_CC8 SWR: RCM2U Position            */\r
+#define CCU8_CC8_SWR_RCM2U_Msk                (0x01UL << CCU8_CC8_SWR_RCM2U_Pos)                      /*!< CCU8_CC8 SWR: RCM2U Mask                */\r
+#define CCU8_CC8_SWR_RCM2D_Pos                5                                                       /*!< CCU8_CC8 SWR: RCM2D Position            */\r
+#define CCU8_CC8_SWR_RCM2D_Msk                (0x01UL << CCU8_CC8_SWR_RCM2D_Pos)                      /*!< CCU8_CC8 SWR: RCM2D Mask                */\r
+#define CCU8_CC8_SWR_RE0A_Pos                 8                                                       /*!< CCU8_CC8 SWR: RE0A Position             */\r
+#define CCU8_CC8_SWR_RE0A_Msk                 (0x01UL << CCU8_CC8_SWR_RE0A_Pos)                       /*!< CCU8_CC8 SWR: RE0A Mask                 */\r
+#define CCU8_CC8_SWR_RE1A_Pos                 9                                                       /*!< CCU8_CC8 SWR: RE1A Position             */\r
+#define CCU8_CC8_SWR_RE1A_Msk                 (0x01UL << CCU8_CC8_SWR_RE1A_Pos)                       /*!< CCU8_CC8 SWR: RE1A Mask                 */\r
+#define CCU8_CC8_SWR_RE2A_Pos                 10                                                      /*!< CCU8_CC8 SWR: RE2A Position             */\r
+#define CCU8_CC8_SWR_RE2A_Msk                 (0x01UL << CCU8_CC8_SWR_RE2A_Pos)                       /*!< CCU8_CC8 SWR: RE2A Mask                 */\r
+#define CCU8_CC8_SWR_RTRPF_Pos                11                                                      /*!< CCU8_CC8 SWR: RTRPF Position            */\r
+#define CCU8_CC8_SWR_RTRPF_Msk                (0x01UL << CCU8_CC8_SWR_RTRPF_Pos)                      /*!< CCU8_CC8 SWR: RTRPF Mask                */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'HRPWM0' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  HRPWM0_HRBSC  -------------------------------- */\r
+#define HRPWM0_HRBSC_SUSCFG_Pos               0                                                       /*!< HRPWM0 HRBSC: SUSCFG Position           */\r
+#define HRPWM0_HRBSC_SUSCFG_Msk               (0x07UL << HRPWM0_HRBSC_SUSCFG_Pos)                     /*!< HRPWM0 HRBSC: SUSCFG Mask               */\r
+#define HRPWM0_HRBSC_HRBE_Pos                 8                                                       /*!< HRPWM0 HRBSC: HRBE Position             */\r
+#define HRPWM0_HRBSC_HRBE_Msk                 (0x01UL << HRPWM0_HRBSC_HRBE_Pos)                       /*!< HRPWM0 HRBSC: HRBE Mask                 */\r
+\r
+/* ---------------------------------  HRPWM0_MIDR  -------------------------------- */\r
+#define HRPWM0_MIDR_MODR_Pos                  0                                                       /*!< HRPWM0 MIDR: MODR Position              */\r
+#define HRPWM0_MIDR_MODR_Msk                  (0x000000ffUL << HRPWM0_MIDR_MODR_Pos)                  /*!< HRPWM0 MIDR: MODR Mask                  */\r
+#define HRPWM0_MIDR_MODT_Pos                  8                                                       /*!< HRPWM0 MIDR: MODT Position              */\r
+#define HRPWM0_MIDR_MODT_Msk                  (0x000000ffUL << HRPWM0_MIDR_MODT_Pos)                  /*!< HRPWM0 MIDR: MODT Mask                  */\r
+#define HRPWM0_MIDR_MODN_Pos                  16                                                      /*!< HRPWM0 MIDR: MODN Position              */\r
+#define HRPWM0_MIDR_MODN_Msk                  (0x0000ffffUL << HRPWM0_MIDR_MODN_Pos)                  /*!< HRPWM0 MIDR: MODN Mask                  */\r
+\r
+/* --------------------------------  HRPWM0_GLBANA  ------------------------------- */\r
+#define HRPWM0_GLBANA_SLDLY_Pos               0                                                       /*!< HRPWM0 GLBANA: SLDLY Position           */\r
+#define HRPWM0_GLBANA_SLDLY_Msk               (0x03UL << HRPWM0_GLBANA_SLDLY_Pos)                     /*!< HRPWM0 GLBANA: SLDLY Mask               */\r
+#define HRPWM0_GLBANA_FUP_Pos                 2                                                       /*!< HRPWM0 GLBANA: FUP Position             */\r
+#define HRPWM0_GLBANA_FUP_Msk                 (0x01UL << HRPWM0_GLBANA_FUP_Pos)                       /*!< HRPWM0 GLBANA: FUP Mask                 */\r
+#define HRPWM0_GLBANA_FDN_Pos                 3                                                       /*!< HRPWM0 GLBANA: FDN Position             */\r
+#define HRPWM0_GLBANA_FDN_Msk                 (0x01UL << HRPWM0_GLBANA_FDN_Pos)                       /*!< HRPWM0 GLBANA: FDN Mask                 */\r
+#define HRPWM0_GLBANA_SLCP_Pos                6                                                       /*!< HRPWM0 GLBANA: SLCP Position            */\r
+#define HRPWM0_GLBANA_SLCP_Msk                (0x07UL << HRPWM0_GLBANA_SLCP_Pos)                      /*!< HRPWM0 GLBANA: SLCP Mask                */\r
+#define HRPWM0_GLBANA_SLIBLDO_Pos             9                                                       /*!< HRPWM0 GLBANA: SLIBLDO Position         */\r
+#define HRPWM0_GLBANA_SLIBLDO_Msk             (0x03UL << HRPWM0_GLBANA_SLIBLDO_Pos)                   /*!< HRPWM0 GLBANA: SLIBLDO Mask             */\r
+#define HRPWM0_GLBANA_SLIBLF_Pos              11                                                      /*!< HRPWM0 GLBANA: SLIBLF Position          */\r
+#define HRPWM0_GLBANA_SLIBLF_Msk              (0x03UL << HRPWM0_GLBANA_SLIBLF_Pos)                    /*!< HRPWM0 GLBANA: SLIBLF Mask              */\r
+#define HRPWM0_GLBANA_SLVREF_Pos              13                                                      /*!< HRPWM0 GLBANA: SLVREF Position          */\r
+#define HRPWM0_GLBANA_SLVREF_Msk              (0x07UL << HRPWM0_GLBANA_SLVREF_Pos)                    /*!< HRPWM0 GLBANA: SLVREF Mask              */\r
+#define HRPWM0_GLBANA_TRIBIAS_Pos             16                                                      /*!< HRPWM0 GLBANA: TRIBIAS Position         */\r
+#define HRPWM0_GLBANA_TRIBIAS_Msk             (0x03UL << HRPWM0_GLBANA_TRIBIAS_Pos)                   /*!< HRPWM0 GLBANA: TRIBIAS Mask             */\r
+#define HRPWM0_GLBANA_GHREN_Pos               18                                                      /*!< HRPWM0 GLBANA: GHREN Position           */\r
+#define HRPWM0_GLBANA_GHREN_Msk               (0x01UL << HRPWM0_GLBANA_GHREN_Pos)                     /*!< HRPWM0 GLBANA: GHREN Mask               */\r
+\r
+/* --------------------------------  HRPWM0_CSGCFG  ------------------------------- */\r
+#define HRPWM0_CSGCFG_C0PM_Pos                0                                                       /*!< HRPWM0 CSGCFG: C0PM Position            */\r
+#define HRPWM0_CSGCFG_C0PM_Msk                (0x03UL << HRPWM0_CSGCFG_C0PM_Pos)                      /*!< HRPWM0 CSGCFG: C0PM Mask                */\r
+#define HRPWM0_CSGCFG_C1PM_Pos                2                                                       /*!< HRPWM0 CSGCFG: C1PM Position            */\r
+#define HRPWM0_CSGCFG_C1PM_Msk                (0x03UL << HRPWM0_CSGCFG_C1PM_Pos)                      /*!< HRPWM0 CSGCFG: C1PM Mask                */\r
+#define HRPWM0_CSGCFG_C2PM_Pos                4                                                       /*!< HRPWM0 CSGCFG: C2PM Position            */\r
+#define HRPWM0_CSGCFG_C2PM_Msk                (0x03UL << HRPWM0_CSGCFG_C2PM_Pos)                      /*!< HRPWM0 CSGCFG: C2PM Mask                */\r
+#define HRPWM0_CSGCFG_C0CD_Pos                16                                                      /*!< HRPWM0 CSGCFG: C0CD Position            */\r
+#define HRPWM0_CSGCFG_C0CD_Msk                (0x01UL << HRPWM0_CSGCFG_C0CD_Pos)                      /*!< HRPWM0 CSGCFG: C0CD Mask                */\r
+#define HRPWM0_CSGCFG_C1CD_Pos                17                                                      /*!< HRPWM0 CSGCFG: C1CD Position            */\r
+#define HRPWM0_CSGCFG_C1CD_Msk                (0x01UL << HRPWM0_CSGCFG_C1CD_Pos)                      /*!< HRPWM0 CSGCFG: C1CD Mask                */\r
+#define HRPWM0_CSGCFG_C2CD_Pos                18                                                      /*!< HRPWM0 CSGCFG: C2CD Position            */\r
+#define HRPWM0_CSGCFG_C2CD_Msk                (0x01UL << HRPWM0_CSGCFG_C2CD_Pos)                      /*!< HRPWM0 CSGCFG: C2CD Mask                */\r
+\r
+/* -------------------------------  HRPWM0_CSGSETG  ------------------------------- */\r
+#define HRPWM0_CSGSETG_SD0R_Pos               0                                                       /*!< HRPWM0 CSGSETG: SD0R Position           */\r
+#define HRPWM0_CSGSETG_SD0R_Msk               (0x01UL << HRPWM0_CSGSETG_SD0R_Pos)                     /*!< HRPWM0 CSGSETG: SD0R Mask               */\r
+#define HRPWM0_CSGSETG_SC0R_Pos               1                                                       /*!< HRPWM0 CSGSETG: SC0R Position           */\r
+#define HRPWM0_CSGSETG_SC0R_Msk               (0x01UL << HRPWM0_CSGSETG_SC0R_Pos)                     /*!< HRPWM0 CSGSETG: SC0R Mask               */\r
+#define HRPWM0_CSGSETG_SC0P_Pos               2                                                       /*!< HRPWM0 CSGSETG: SC0P Position           */\r
+#define HRPWM0_CSGSETG_SC0P_Msk               (0x01UL << HRPWM0_CSGSETG_SC0P_Pos)                     /*!< HRPWM0 CSGSETG: SC0P Mask               */\r
+#define HRPWM0_CSGSETG_SD1R_Pos               4                                                       /*!< HRPWM0 CSGSETG: SD1R Position           */\r
+#define HRPWM0_CSGSETG_SD1R_Msk               (0x01UL << HRPWM0_CSGSETG_SD1R_Pos)                     /*!< HRPWM0 CSGSETG: SD1R Mask               */\r
+#define HRPWM0_CSGSETG_SC1R_Pos               5                                                       /*!< HRPWM0 CSGSETG: SC1R Position           */\r
+#define HRPWM0_CSGSETG_SC1R_Msk               (0x01UL << HRPWM0_CSGSETG_SC1R_Pos)                     /*!< HRPWM0 CSGSETG: SC1R Mask               */\r
+#define HRPWM0_CSGSETG_SC1P_Pos               6                                                       /*!< HRPWM0 CSGSETG: SC1P Position           */\r
+#define HRPWM0_CSGSETG_SC1P_Msk               (0x01UL << HRPWM0_CSGSETG_SC1P_Pos)                     /*!< HRPWM0 CSGSETG: SC1P Mask               */\r
+#define HRPWM0_CSGSETG_SD2R_Pos               8                                                       /*!< HRPWM0 CSGSETG: SD2R Position           */\r
+#define HRPWM0_CSGSETG_SD2R_Msk               (0x01UL << HRPWM0_CSGSETG_SD2R_Pos)                     /*!< HRPWM0 CSGSETG: SD2R Mask               */\r
+#define HRPWM0_CSGSETG_SC2R_Pos               9                                                       /*!< HRPWM0 CSGSETG: SC2R Position           */\r
+#define HRPWM0_CSGSETG_SC2R_Msk               (0x01UL << HRPWM0_CSGSETG_SC2R_Pos)                     /*!< HRPWM0 CSGSETG: SC2R Mask               */\r
+#define HRPWM0_CSGSETG_SC2P_Pos               10                                                      /*!< HRPWM0 CSGSETG: SC2P Position           */\r
+#define HRPWM0_CSGSETG_SC2P_Msk               (0x01UL << HRPWM0_CSGSETG_SC2P_Pos)                     /*!< HRPWM0 CSGSETG: SC2P Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSGCLRG  ------------------------------- */\r
+#define HRPWM0_CSGCLRG_CD0R_Pos               0                                                       /*!< HRPWM0 CSGCLRG: CD0R Position           */\r
+#define HRPWM0_CSGCLRG_CD0R_Msk               (0x01UL << HRPWM0_CSGCLRG_CD0R_Pos)                     /*!< HRPWM0 CSGCLRG: CD0R Mask               */\r
+#define HRPWM0_CSGCLRG_CC0R_Pos               1                                                       /*!< HRPWM0 CSGCLRG: CC0R Position           */\r
+#define HRPWM0_CSGCLRG_CC0R_Msk               (0x01UL << HRPWM0_CSGCLRG_CC0R_Pos)                     /*!< HRPWM0 CSGCLRG: CC0R Mask               */\r
+#define HRPWM0_CSGCLRG_CC0P_Pos               2                                                       /*!< HRPWM0 CSGCLRG: CC0P Position           */\r
+#define HRPWM0_CSGCLRG_CC0P_Msk               (0x01UL << HRPWM0_CSGCLRG_CC0P_Pos)                     /*!< HRPWM0 CSGCLRG: CC0P Mask               */\r
+#define HRPWM0_CSGCLRG_CD1R_Pos               4                                                       /*!< HRPWM0 CSGCLRG: CD1R Position           */\r
+#define HRPWM0_CSGCLRG_CD1R_Msk               (0x01UL << HRPWM0_CSGCLRG_CD1R_Pos)                     /*!< HRPWM0 CSGCLRG: CD1R Mask               */\r
+#define HRPWM0_CSGCLRG_CC1R_Pos               5                                                       /*!< HRPWM0 CSGCLRG: CC1R Position           */\r
+#define HRPWM0_CSGCLRG_CC1R_Msk               (0x01UL << HRPWM0_CSGCLRG_CC1R_Pos)                     /*!< HRPWM0 CSGCLRG: CC1R Mask               */\r
+#define HRPWM0_CSGCLRG_CC1P_Pos               6                                                       /*!< HRPWM0 CSGCLRG: CC1P Position           */\r
+#define HRPWM0_CSGCLRG_CC1P_Msk               (0x01UL << HRPWM0_CSGCLRG_CC1P_Pos)                     /*!< HRPWM0 CSGCLRG: CC1P Mask               */\r
+#define HRPWM0_CSGCLRG_CD2R_Pos               8                                                       /*!< HRPWM0 CSGCLRG: CD2R Position           */\r
+#define HRPWM0_CSGCLRG_CD2R_Msk               (0x01UL << HRPWM0_CSGCLRG_CD2R_Pos)                     /*!< HRPWM0 CSGCLRG: CD2R Mask               */\r
+#define HRPWM0_CSGCLRG_CC2R_Pos               9                                                       /*!< HRPWM0 CSGCLRG: CC2R Position           */\r
+#define HRPWM0_CSGCLRG_CC2R_Msk               (0x01UL << HRPWM0_CSGCLRG_CC2R_Pos)                     /*!< HRPWM0 CSGCLRG: CC2R Mask               */\r
+#define HRPWM0_CSGCLRG_CC2P_Pos               10                                                      /*!< HRPWM0 CSGCLRG: CC2P Position           */\r
+#define HRPWM0_CSGCLRG_CC2P_Msk               (0x01UL << HRPWM0_CSGCLRG_CC2P_Pos)                     /*!< HRPWM0 CSGCLRG: CC2P Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSGSTATG  ------------------------------ */\r
+#define HRPWM0_CSGSTATG_D0RB_Pos              0                                                       /*!< HRPWM0 CSGSTATG: D0RB Position          */\r
+#define HRPWM0_CSGSTATG_D0RB_Msk              (0x01UL << HRPWM0_CSGSTATG_D0RB_Pos)                    /*!< HRPWM0 CSGSTATG: D0RB Mask              */\r
+#define HRPWM0_CSGSTATG_C0RB_Pos              1                                                       /*!< HRPWM0 CSGSTATG: C0RB Position          */\r
+#define HRPWM0_CSGSTATG_C0RB_Msk              (0x01UL << HRPWM0_CSGSTATG_C0RB_Pos)                    /*!< HRPWM0 CSGSTATG: C0RB Mask              */\r
+#define HRPWM0_CSGSTATG_PSLS0_Pos             2                                                       /*!< HRPWM0 CSGSTATG: PSLS0 Position         */\r
+#define HRPWM0_CSGSTATG_PSLS0_Msk             (0x01UL << HRPWM0_CSGSTATG_PSLS0_Pos)                   /*!< HRPWM0 CSGSTATG: PSLS0 Mask             */\r
+#define HRPWM0_CSGSTATG_D1RB_Pos              4                                                       /*!< HRPWM0 CSGSTATG: D1RB Position          */\r
+#define HRPWM0_CSGSTATG_D1RB_Msk              (0x01UL << HRPWM0_CSGSTATG_D1RB_Pos)                    /*!< HRPWM0 CSGSTATG: D1RB Mask              */\r
+#define HRPWM0_CSGSTATG_C1RB_Pos              5                                                       /*!< HRPWM0 CSGSTATG: C1RB Position          */\r
+#define HRPWM0_CSGSTATG_C1RB_Msk              (0x01UL << HRPWM0_CSGSTATG_C1RB_Pos)                    /*!< HRPWM0 CSGSTATG: C1RB Mask              */\r
+#define HRPWM0_CSGSTATG_PSLS1_Pos             6                                                       /*!< HRPWM0 CSGSTATG: PSLS1 Position         */\r
+#define HRPWM0_CSGSTATG_PSLS1_Msk             (0x01UL << HRPWM0_CSGSTATG_PSLS1_Pos)                   /*!< HRPWM0 CSGSTATG: PSLS1 Mask             */\r
+#define HRPWM0_CSGSTATG_D2RB_Pos              8                                                       /*!< HRPWM0 CSGSTATG: D2RB Position          */\r
+#define HRPWM0_CSGSTATG_D2RB_Msk              (0x01UL << HRPWM0_CSGSTATG_D2RB_Pos)                    /*!< HRPWM0 CSGSTATG: D2RB Mask              */\r
+#define HRPWM0_CSGSTATG_C2RB_Pos              9                                                       /*!< HRPWM0 CSGSTATG: C2RB Position          */\r
+#define HRPWM0_CSGSTATG_C2RB_Msk              (0x01UL << HRPWM0_CSGSTATG_C2RB_Pos)                    /*!< HRPWM0 CSGSTATG: C2RB Mask              */\r
+#define HRPWM0_CSGSTATG_PSLS2_Pos             10                                                      /*!< HRPWM0 CSGSTATG: PSLS2 Position         */\r
+#define HRPWM0_CSGSTATG_PSLS2_Msk             (0x01UL << HRPWM0_CSGSTATG_PSLS2_Pos)                   /*!< HRPWM0 CSGSTATG: PSLS2 Mask             */\r
+\r
+/* --------------------------------  HRPWM0_CSGFCG  ------------------------------- */\r
+#define HRPWM0_CSGFCG_S0STR_Pos               0                                                       /*!< HRPWM0 CSGFCG: S0STR Position           */\r
+#define HRPWM0_CSGFCG_S0STR_Msk               (0x01UL << HRPWM0_CSGFCG_S0STR_Pos)                     /*!< HRPWM0 CSGFCG: S0STR Mask               */\r
+#define HRPWM0_CSGFCG_S0STP_Pos               1                                                       /*!< HRPWM0 CSGFCG: S0STP Position           */\r
+#define HRPWM0_CSGFCG_S0STP_Msk               (0x01UL << HRPWM0_CSGFCG_S0STP_Pos)                     /*!< HRPWM0 CSGFCG: S0STP Mask               */\r
+#define HRPWM0_CSGFCG_PS0STR_Pos              2                                                       /*!< HRPWM0 CSGFCG: PS0STR Position          */\r
+#define HRPWM0_CSGFCG_PS0STR_Msk              (0x01UL << HRPWM0_CSGFCG_PS0STR_Pos)                    /*!< HRPWM0 CSGFCG: PS0STR Mask              */\r
+#define HRPWM0_CSGFCG_PS0STP_Pos              3                                                       /*!< HRPWM0 CSGFCG: PS0STP Position          */\r
+#define HRPWM0_CSGFCG_PS0STP_Msk              (0x01UL << HRPWM0_CSGFCG_PS0STP_Pos)                    /*!< HRPWM0 CSGFCG: PS0STP Mask              */\r
+#define HRPWM0_CSGFCG_PS0CLR_Pos              4                                                       /*!< HRPWM0 CSGFCG: PS0CLR Position          */\r
+#define HRPWM0_CSGFCG_PS0CLR_Msk              (0x01UL << HRPWM0_CSGFCG_PS0CLR_Pos)                    /*!< HRPWM0 CSGFCG: PS0CLR Mask              */\r
+#define HRPWM0_CSGFCG_S1STR_Pos               8                                                       /*!< HRPWM0 CSGFCG: S1STR Position           */\r
+#define HRPWM0_CSGFCG_S1STR_Msk               (0x01UL << HRPWM0_CSGFCG_S1STR_Pos)                     /*!< HRPWM0 CSGFCG: S1STR Mask               */\r
+#define HRPWM0_CSGFCG_S1STP_Pos               9                                                       /*!< HRPWM0 CSGFCG: S1STP Position           */\r
+#define HRPWM0_CSGFCG_S1STP_Msk               (0x01UL << HRPWM0_CSGFCG_S1STP_Pos)                     /*!< HRPWM0 CSGFCG: S1STP Mask               */\r
+#define HRPWM0_CSGFCG_PS1STR_Pos              10                                                      /*!< HRPWM0 CSGFCG: PS1STR Position          */\r
+#define HRPWM0_CSGFCG_PS1STR_Msk              (0x01UL << HRPWM0_CSGFCG_PS1STR_Pos)                    /*!< HRPWM0 CSGFCG: PS1STR Mask              */\r
+#define HRPWM0_CSGFCG_PS1STP_Pos              11                                                      /*!< HRPWM0 CSGFCG: PS1STP Position          */\r
+#define HRPWM0_CSGFCG_PS1STP_Msk              (0x01UL << HRPWM0_CSGFCG_PS1STP_Pos)                    /*!< HRPWM0 CSGFCG: PS1STP Mask              */\r
+#define HRPWM0_CSGFCG_PS1CLR_Pos              12                                                      /*!< HRPWM0 CSGFCG: PS1CLR Position          */\r
+#define HRPWM0_CSGFCG_PS1CLR_Msk              (0x01UL << HRPWM0_CSGFCG_PS1CLR_Pos)                    /*!< HRPWM0 CSGFCG: PS1CLR Mask              */\r
+#define HRPWM0_CSGFCG_S2STR_Pos               16                                                      /*!< HRPWM0 CSGFCG: S2STR Position           */\r
+#define HRPWM0_CSGFCG_S2STR_Msk               (0x01UL << HRPWM0_CSGFCG_S2STR_Pos)                     /*!< HRPWM0 CSGFCG: S2STR Mask               */\r
+#define HRPWM0_CSGFCG_S2STP_Pos               17                                                      /*!< HRPWM0 CSGFCG: S2STP Position           */\r
+#define HRPWM0_CSGFCG_S2STP_Msk               (0x01UL << HRPWM0_CSGFCG_S2STP_Pos)                     /*!< HRPWM0 CSGFCG: S2STP Mask               */\r
+#define HRPWM0_CSGFCG_PS2STR_Pos              18                                                      /*!< HRPWM0 CSGFCG: PS2STR Position          */\r
+#define HRPWM0_CSGFCG_PS2STR_Msk              (0x01UL << HRPWM0_CSGFCG_PS2STR_Pos)                    /*!< HRPWM0 CSGFCG: PS2STR Mask              */\r
+#define HRPWM0_CSGFCG_PS2STP_Pos              19                                                      /*!< HRPWM0 CSGFCG: PS2STP Position          */\r
+#define HRPWM0_CSGFCG_PS2STP_Msk              (0x01UL << HRPWM0_CSGFCG_PS2STP_Pos)                    /*!< HRPWM0 CSGFCG: PS2STP Mask              */\r
+#define HRPWM0_CSGFCG_PS2CLR_Pos              20                                                      /*!< HRPWM0 CSGFCG: PS2CLR Position          */\r
+#define HRPWM0_CSGFCG_PS2CLR_Msk              (0x01UL << HRPWM0_CSGFCG_PS2CLR_Pos)                    /*!< HRPWM0 CSGFCG: PS2CLR Mask              */\r
+\r
+/* --------------------------------  HRPWM0_CSGFSG  ------------------------------- */\r
+#define HRPWM0_CSGFSG_S0RB_Pos                0                                                       /*!< HRPWM0 CSGFSG: S0RB Position            */\r
+#define HRPWM0_CSGFSG_S0RB_Msk                (0x01UL << HRPWM0_CSGFSG_S0RB_Pos)                      /*!< HRPWM0 CSGFSG: S0RB Mask                */\r
+#define HRPWM0_CSGFSG_P0RB_Pos                1                                                       /*!< HRPWM0 CSGFSG: P0RB Position            */\r
+#define HRPWM0_CSGFSG_P0RB_Msk                (0x01UL << HRPWM0_CSGFSG_P0RB_Pos)                      /*!< HRPWM0 CSGFSG: P0RB Mask                */\r
+#define HRPWM0_CSGFSG_S1RB_Pos                8                                                       /*!< HRPWM0 CSGFSG: S1RB Position            */\r
+#define HRPWM0_CSGFSG_S1RB_Msk                (0x01UL << HRPWM0_CSGFSG_S1RB_Pos)                      /*!< HRPWM0 CSGFSG: S1RB Mask                */\r
+#define HRPWM0_CSGFSG_P1RB_Pos                9                                                       /*!< HRPWM0 CSGFSG: P1RB Position            */\r
+#define HRPWM0_CSGFSG_P1RB_Msk                (0x01UL << HRPWM0_CSGFSG_P1RB_Pos)                      /*!< HRPWM0 CSGFSG: P1RB Mask                */\r
+#define HRPWM0_CSGFSG_S2RB_Pos                16                                                      /*!< HRPWM0 CSGFSG: S2RB Position            */\r
+#define HRPWM0_CSGFSG_S2RB_Msk                (0x01UL << HRPWM0_CSGFSG_S2RB_Pos)                      /*!< HRPWM0 CSGFSG: S2RB Mask                */\r
+#define HRPWM0_CSGFSG_P2RB_Pos                17                                                      /*!< HRPWM0 CSGFSG: P2RB Position            */\r
+#define HRPWM0_CSGFSG_P2RB_Msk                (0x01UL << HRPWM0_CSGFSG_P2RB_Pos)                      /*!< HRPWM0 CSGFSG: P2RB Mask                */\r
+\r
+/* --------------------------------  HRPWM0_CSGTRG  ------------------------------- */\r
+#define HRPWM0_CSGTRG_D0SES_Pos               0                                                       /*!< HRPWM0 CSGTRG: D0SES Position           */\r
+#define HRPWM0_CSGTRG_D0SES_Msk               (0x01UL << HRPWM0_CSGTRG_D0SES_Pos)                     /*!< HRPWM0 CSGTRG: D0SES Mask               */\r
+#define HRPWM0_CSGTRG_D0SVS_Pos               1                                                       /*!< HRPWM0 CSGTRG: D0SVS Position           */\r
+#define HRPWM0_CSGTRG_D0SVS_Msk               (0x01UL << HRPWM0_CSGTRG_D0SVS_Pos)                     /*!< HRPWM0 CSGTRG: D0SVS Mask               */\r
+#define HRPWM0_CSGTRG_D1SES_Pos               4                                                       /*!< HRPWM0 CSGTRG: D1SES Position           */\r
+#define HRPWM0_CSGTRG_D1SES_Msk               (0x01UL << HRPWM0_CSGTRG_D1SES_Pos)                     /*!< HRPWM0 CSGTRG: D1SES Mask               */\r
+#define HRPWM0_CSGTRG_D1SVS_Pos               5                                                       /*!< HRPWM0 CSGTRG: D1SVS Position           */\r
+#define HRPWM0_CSGTRG_D1SVS_Msk               (0x01UL << HRPWM0_CSGTRG_D1SVS_Pos)                     /*!< HRPWM0 CSGTRG: D1SVS Mask               */\r
+#define HRPWM0_CSGTRG_D2SES_Pos               8                                                       /*!< HRPWM0 CSGTRG: D2SES Position           */\r
+#define HRPWM0_CSGTRG_D2SES_Msk               (0x01UL << HRPWM0_CSGTRG_D2SES_Pos)                     /*!< HRPWM0 CSGTRG: D2SES Mask               */\r
+#define HRPWM0_CSGTRG_D2SVS_Pos               9                                                       /*!< HRPWM0 CSGTRG: D2SVS Position           */\r
+#define HRPWM0_CSGTRG_D2SVS_Msk               (0x01UL << HRPWM0_CSGTRG_D2SVS_Pos)                     /*!< HRPWM0 CSGTRG: D2SVS Mask               */\r
+\r
+/* --------------------------------  HRPWM0_CSGTRC  ------------------------------- */\r
+#define HRPWM0_CSGTRC_D0SEC_Pos               0                                                       /*!< HRPWM0 CSGTRC: D0SEC Position           */\r
+#define HRPWM0_CSGTRC_D0SEC_Msk               (0x01UL << HRPWM0_CSGTRC_D0SEC_Pos)                     /*!< HRPWM0 CSGTRC: D0SEC Mask               */\r
+#define HRPWM0_CSGTRC_D1SEC_Pos               4                                                       /*!< HRPWM0 CSGTRC: D1SEC Position           */\r
+#define HRPWM0_CSGTRC_D1SEC_Msk               (0x01UL << HRPWM0_CSGTRC_D1SEC_Pos)                     /*!< HRPWM0 CSGTRC: D1SEC Mask               */\r
+#define HRPWM0_CSGTRC_D2SEC_Pos               8                                                       /*!< HRPWM0 CSGTRC: D2SEC Position           */\r
+#define HRPWM0_CSGTRC_D2SEC_Msk               (0x01UL << HRPWM0_CSGTRC_D2SEC_Pos)                     /*!< HRPWM0 CSGTRC: D2SEC Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSGTRSG  ------------------------------- */\r
+#define HRPWM0_CSGTRSG_D0STE_Pos              0                                                       /*!< HRPWM0 CSGTRSG: D0STE Position          */\r
+#define HRPWM0_CSGTRSG_D0STE_Msk              (0x01UL << HRPWM0_CSGTRSG_D0STE_Pos)                    /*!< HRPWM0 CSGTRSG: D0STE Mask              */\r
+#define HRPWM0_CSGTRSG_SW0ST_Pos              1                                                       /*!< HRPWM0 CSGTRSG: SW0ST Position          */\r
+#define HRPWM0_CSGTRSG_SW0ST_Msk              (0x01UL << HRPWM0_CSGTRSG_SW0ST_Pos)                    /*!< HRPWM0 CSGTRSG: SW0ST Mask              */\r
+#define HRPWM0_CSGTRSG_D1STE_Pos              4                                                       /*!< HRPWM0 CSGTRSG: D1STE Position          */\r
+#define HRPWM0_CSGTRSG_D1STE_Msk              (0x01UL << HRPWM0_CSGTRSG_D1STE_Pos)                    /*!< HRPWM0 CSGTRSG: D1STE Mask              */\r
+#define HRPWM0_CSGTRSG_SW1ST_Pos              5                                                       /*!< HRPWM0 CSGTRSG: SW1ST Position          */\r
+#define HRPWM0_CSGTRSG_SW1ST_Msk              (0x01UL << HRPWM0_CSGTRSG_SW1ST_Pos)                    /*!< HRPWM0 CSGTRSG: SW1ST Mask              */\r
+#define HRPWM0_CSGTRSG_D2STE_Pos              8                                                       /*!< HRPWM0 CSGTRSG: D2STE Position          */\r
+#define HRPWM0_CSGTRSG_D2STE_Msk              (0x01UL << HRPWM0_CSGTRSG_D2STE_Pos)                    /*!< HRPWM0 CSGTRSG: D2STE Mask              */\r
+#define HRPWM0_CSGTRSG_SW2ST_Pos              9                                                       /*!< HRPWM0 CSGTRSG: SW2ST Position          */\r
+#define HRPWM0_CSGTRSG_SW2ST_Msk              (0x01UL << HRPWM0_CSGTRSG_SW2ST_Pos)                    /*!< HRPWM0 CSGTRSG: SW2ST Mask              */\r
+\r
+/* --------------------------------  HRPWM0_HRCCFG  ------------------------------- */\r
+#define HRPWM0_HRCCFG_HRCPM_Pos               0                                                       /*!< HRPWM0 HRCCFG: HRCPM Position           */\r
+#define HRPWM0_HRCCFG_HRCPM_Msk               (0x01UL << HRPWM0_HRCCFG_HRCPM_Pos)                     /*!< HRPWM0 HRCCFG: HRCPM Mask               */\r
+#define HRPWM0_HRCCFG_HRC0E_Pos               4                                                       /*!< HRPWM0 HRCCFG: HRC0E Position           */\r
+#define HRPWM0_HRCCFG_HRC0E_Msk               (0x01UL << HRPWM0_HRCCFG_HRC0E_Pos)                     /*!< HRPWM0 HRCCFG: HRC0E Mask               */\r
+#define HRPWM0_HRCCFG_HRC1E_Pos               5                                                       /*!< HRPWM0 HRCCFG: HRC1E Position           */\r
+#define HRPWM0_HRCCFG_HRC1E_Msk               (0x01UL << HRPWM0_HRCCFG_HRC1E_Pos)                     /*!< HRPWM0 HRCCFG: HRC1E Mask               */\r
+#define HRPWM0_HRCCFG_HRC2E_Pos               6                                                       /*!< HRPWM0 HRCCFG: HRC2E Position           */\r
+#define HRPWM0_HRCCFG_HRC2E_Msk               (0x01UL << HRPWM0_HRCCFG_HRC2E_Pos)                     /*!< HRPWM0 HRCCFG: HRC2E Mask               */\r
+#define HRPWM0_HRCCFG_HRC3E_Pos               7                                                       /*!< HRPWM0 HRCCFG: HRC3E Position           */\r
+#define HRPWM0_HRCCFG_HRC3E_Msk               (0x01UL << HRPWM0_HRCCFG_HRC3E_Pos)                     /*!< HRPWM0 HRCCFG: HRC3E Mask               */\r
+#define HRPWM0_HRCCFG_CLKC_Pos                16                                                      /*!< HRPWM0 HRCCFG: CLKC Position            */\r
+#define HRPWM0_HRCCFG_CLKC_Msk                (0x07UL << HRPWM0_HRCCFG_CLKC_Pos)                      /*!< HRPWM0 HRCCFG: CLKC Mask                */\r
+#define HRPWM0_HRCCFG_LRC0E_Pos               20                                                      /*!< HRPWM0 HRCCFG: LRC0E Position           */\r
+#define HRPWM0_HRCCFG_LRC0E_Msk               (0x01UL << HRPWM0_HRCCFG_LRC0E_Pos)                     /*!< HRPWM0 HRCCFG: LRC0E Mask               */\r
+#define HRPWM0_HRCCFG_LRC1E_Pos               21                                                      /*!< HRPWM0 HRCCFG: LRC1E Position           */\r
+#define HRPWM0_HRCCFG_LRC1E_Msk               (0x01UL << HRPWM0_HRCCFG_LRC1E_Pos)                     /*!< HRPWM0 HRCCFG: LRC1E Mask               */\r
+#define HRPWM0_HRCCFG_LRC2E_Pos               22                                                      /*!< HRPWM0 HRCCFG: LRC2E Position           */\r
+#define HRPWM0_HRCCFG_LRC2E_Msk               (0x01UL << HRPWM0_HRCCFG_LRC2E_Pos)                     /*!< HRPWM0 HRCCFG: LRC2E Mask               */\r
+#define HRPWM0_HRCCFG_LRC3E_Pos               23                                                      /*!< HRPWM0 HRCCFG: LRC3E Position           */\r
+#define HRPWM0_HRCCFG_LRC3E_Msk               (0x01UL << HRPWM0_HRCCFG_LRC3E_Pos)                     /*!< HRPWM0 HRCCFG: LRC3E Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRCSTRG  ------------------------------- */\r
+#define HRPWM0_HRCSTRG_H0ES_Pos               0                                                       /*!< HRPWM0 HRCSTRG: H0ES Position           */\r
+#define HRPWM0_HRCSTRG_H0ES_Msk               (0x01UL << HRPWM0_HRCSTRG_H0ES_Pos)                     /*!< HRPWM0 HRCSTRG: H0ES Mask               */\r
+#define HRPWM0_HRCSTRG_H0DES_Pos              1                                                       /*!< HRPWM0 HRCSTRG: H0DES Position          */\r
+#define HRPWM0_HRCSTRG_H0DES_Msk              (0x01UL << HRPWM0_HRCSTRG_H0DES_Pos)                    /*!< HRPWM0 HRCSTRG: H0DES Mask              */\r
+#define HRPWM0_HRCSTRG_H1ES_Pos               4                                                       /*!< HRPWM0 HRCSTRG: H1ES Position           */\r
+#define HRPWM0_HRCSTRG_H1ES_Msk               (0x01UL << HRPWM0_HRCSTRG_H1ES_Pos)                     /*!< HRPWM0 HRCSTRG: H1ES Mask               */\r
+#define HRPWM0_HRCSTRG_H1DES_Pos              5                                                       /*!< HRPWM0 HRCSTRG: H1DES Position          */\r
+#define HRPWM0_HRCSTRG_H1DES_Msk              (0x01UL << HRPWM0_HRCSTRG_H1DES_Pos)                    /*!< HRPWM0 HRCSTRG: H1DES Mask              */\r
+#define HRPWM0_HRCSTRG_H2ES_Pos               8                                                       /*!< HRPWM0 HRCSTRG: H2ES Position           */\r
+#define HRPWM0_HRCSTRG_H2ES_Msk               (0x01UL << HRPWM0_HRCSTRG_H2ES_Pos)                     /*!< HRPWM0 HRCSTRG: H2ES Mask               */\r
+#define HRPWM0_HRCSTRG_H2DES_Pos              9                                                       /*!< HRPWM0 HRCSTRG: H2DES Position          */\r
+#define HRPWM0_HRCSTRG_H2DES_Msk              (0x01UL << HRPWM0_HRCSTRG_H2DES_Pos)                    /*!< HRPWM0 HRCSTRG: H2DES Mask              */\r
+#define HRPWM0_HRCSTRG_H3ES_Pos               12                                                      /*!< HRPWM0 HRCSTRG: H3ES Position           */\r
+#define HRPWM0_HRCSTRG_H3ES_Msk               (0x01UL << HRPWM0_HRCSTRG_H3ES_Pos)                     /*!< HRPWM0 HRCSTRG: H3ES Mask               */\r
+#define HRPWM0_HRCSTRG_H3DES_Pos              13                                                      /*!< HRPWM0 HRCSTRG: H3DES Position          */\r
+#define HRPWM0_HRCSTRG_H3DES_Msk              (0x01UL << HRPWM0_HRCSTRG_H3DES_Pos)                    /*!< HRPWM0 HRCSTRG: H3DES Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRCCTRG  ------------------------------- */\r
+#define HRPWM0_HRCCTRG_H0EC_Pos               0                                                       /*!< HRPWM0 HRCCTRG: H0EC Position           */\r
+#define HRPWM0_HRCCTRG_H0EC_Msk               (0x01UL << HRPWM0_HRCCTRG_H0EC_Pos)                     /*!< HRPWM0 HRCCTRG: H0EC Mask               */\r
+#define HRPWM0_HRCCTRG_H0DEC_Pos              1                                                       /*!< HRPWM0 HRCCTRG: H0DEC Position          */\r
+#define HRPWM0_HRCCTRG_H0DEC_Msk              (0x01UL << HRPWM0_HRCCTRG_H0DEC_Pos)                    /*!< HRPWM0 HRCCTRG: H0DEC Mask              */\r
+#define HRPWM0_HRCCTRG_H1EC_Pos               4                                                       /*!< HRPWM0 HRCCTRG: H1EC Position           */\r
+#define HRPWM0_HRCCTRG_H1EC_Msk               (0x01UL << HRPWM0_HRCCTRG_H1EC_Pos)                     /*!< HRPWM0 HRCCTRG: H1EC Mask               */\r
+#define HRPWM0_HRCCTRG_H1DEC_Pos              5                                                       /*!< HRPWM0 HRCCTRG: H1DEC Position          */\r
+#define HRPWM0_HRCCTRG_H1DEC_Msk              (0x01UL << HRPWM0_HRCCTRG_H1DEC_Pos)                    /*!< HRPWM0 HRCCTRG: H1DEC Mask              */\r
+#define HRPWM0_HRCCTRG_H2CEC_Pos              8                                                       /*!< HRPWM0 HRCCTRG: H2CEC Position          */\r
+#define HRPWM0_HRCCTRG_H2CEC_Msk              (0x01UL << HRPWM0_HRCCTRG_H2CEC_Pos)                    /*!< HRPWM0 HRCCTRG: H2CEC Mask              */\r
+#define HRPWM0_HRCCTRG_H2DEC_Pos              9                                                       /*!< HRPWM0 HRCCTRG: H2DEC Position          */\r
+#define HRPWM0_HRCCTRG_H2DEC_Msk              (0x01UL << HRPWM0_HRCCTRG_H2DEC_Pos)                    /*!< HRPWM0 HRCCTRG: H2DEC Mask              */\r
+#define HRPWM0_HRCCTRG_H3EC_Pos               12                                                      /*!< HRPWM0 HRCCTRG: H3EC Position           */\r
+#define HRPWM0_HRCCTRG_H3EC_Msk               (0x01UL << HRPWM0_HRCCTRG_H3EC_Pos)                     /*!< HRPWM0 HRCCTRG: H3EC Mask               */\r
+#define HRPWM0_HRCCTRG_H3DEC_Pos              13                                                      /*!< HRPWM0 HRCCTRG: H3DEC Position          */\r
+#define HRPWM0_HRCCTRG_H3DEC_Msk              (0x01UL << HRPWM0_HRCCTRG_H3DEC_Pos)                    /*!< HRPWM0 HRCCTRG: H3DEC Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRCSTSG  ------------------------------- */\r
+#define HRPWM0_HRCSTSG_H0STE_Pos              0                                                       /*!< HRPWM0 HRCSTSG: H0STE Position          */\r
+#define HRPWM0_HRCSTSG_H0STE_Msk              (0x01UL << HRPWM0_HRCSTSG_H0STE_Pos)                    /*!< HRPWM0 HRCSTSG: H0STE Mask              */\r
+#define HRPWM0_HRCSTSG_H0DSTE_Pos             1                                                       /*!< HRPWM0 HRCSTSG: H0DSTE Position         */\r
+#define HRPWM0_HRCSTSG_H0DSTE_Msk             (0x01UL << HRPWM0_HRCSTSG_H0DSTE_Pos)                   /*!< HRPWM0 HRCSTSG: H0DSTE Mask             */\r
+#define HRPWM0_HRCSTSG_H1STE_Pos              4                                                       /*!< HRPWM0 HRCSTSG: H1STE Position          */\r
+#define HRPWM0_HRCSTSG_H1STE_Msk              (0x01UL << HRPWM0_HRCSTSG_H1STE_Pos)                    /*!< HRPWM0 HRCSTSG: H1STE Mask              */\r
+#define HRPWM0_HRCSTSG_H1DSTE_Pos             5                                                       /*!< HRPWM0 HRCSTSG: H1DSTE Position         */\r
+#define HRPWM0_HRCSTSG_H1DSTE_Msk             (0x01UL << HRPWM0_HRCSTSG_H1DSTE_Pos)                   /*!< HRPWM0 HRCSTSG: H1DSTE Mask             */\r
+#define HRPWM0_HRCSTSG_H2STE_Pos              8                                                       /*!< HRPWM0 HRCSTSG: H2STE Position          */\r
+#define HRPWM0_HRCSTSG_H2STE_Msk              (0x01UL << HRPWM0_HRCSTSG_H2STE_Pos)                    /*!< HRPWM0 HRCSTSG: H2STE Mask              */\r
+#define HRPWM0_HRCSTSG_H2DSTE_Pos             9                                                       /*!< HRPWM0 HRCSTSG: H2DSTE Position         */\r
+#define HRPWM0_HRCSTSG_H2DSTE_Msk             (0x01UL << HRPWM0_HRCSTSG_H2DSTE_Pos)                   /*!< HRPWM0 HRCSTSG: H2DSTE Mask             */\r
+#define HRPWM0_HRCSTSG_H3STE_Pos              12                                                      /*!< HRPWM0 HRCSTSG: H3STE Position          */\r
+#define HRPWM0_HRCSTSG_H3STE_Msk              (0x01UL << HRPWM0_HRCSTSG_H3STE_Pos)                    /*!< HRPWM0 HRCSTSG: H3STE Mask              */\r
+#define HRPWM0_HRCSTSG_H3DSTE_Pos             13                                                      /*!< HRPWM0 HRCSTSG: H3DSTE Position         */\r
+#define HRPWM0_HRCSTSG_H3DSTE_Msk             (0x01UL << HRPWM0_HRCSTSG_H3DSTE_Pos)                   /*!< HRPWM0 HRCSTSG: H3DSTE Mask             */\r
+\r
+/* --------------------------------  HRPWM0_HRGHRS  ------------------------------- */\r
+#define HRPWM0_HRGHRS_HRGR_Pos                0                                                       /*!< HRPWM0 HRGHRS: HRGR Position            */\r
+#define HRPWM0_HRGHRS_HRGR_Msk                (0x01UL << HRPWM0_HRGHRS_HRGR_Pos)                      /*!< HRPWM0 HRGHRS: HRGR Mask                */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       Group 'HRPWM0_CSG' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_CSG_DCI  ------------------------------- */\r
+#define HRPWM0_CSG_DCI_SVIS_Pos               0                                                       /*!< HRPWM0_CSG DCI: SVIS Position           */\r
+#define HRPWM0_CSG_DCI_SVIS_Msk               (0x0fUL << HRPWM0_CSG_DCI_SVIS_Pos)                     /*!< HRPWM0_CSG DCI: SVIS Mask               */\r
+#define HRPWM0_CSG_DCI_STRIS_Pos              4                                                       /*!< HRPWM0_CSG DCI: STRIS Position          */\r
+#define HRPWM0_CSG_DCI_STRIS_Msk              (0x0fUL << HRPWM0_CSG_DCI_STRIS_Pos)                    /*!< HRPWM0_CSG DCI: STRIS Mask              */\r
+#define HRPWM0_CSG_DCI_STPIS_Pos              8                                                       /*!< HRPWM0_CSG DCI: STPIS Position          */\r
+#define HRPWM0_CSG_DCI_STPIS_Msk              (0x0fUL << HRPWM0_CSG_DCI_STPIS_Pos)                    /*!< HRPWM0_CSG DCI: STPIS Mask              */\r
+#define HRPWM0_CSG_DCI_TRGIS_Pos              12                                                      /*!< HRPWM0_CSG DCI: TRGIS Position          */\r
+#define HRPWM0_CSG_DCI_TRGIS_Msk              (0x0fUL << HRPWM0_CSG_DCI_TRGIS_Pos)                    /*!< HRPWM0_CSG DCI: TRGIS Mask              */\r
+#define HRPWM0_CSG_DCI_STIS_Pos               16                                                      /*!< HRPWM0_CSG DCI: STIS Position           */\r
+#define HRPWM0_CSG_DCI_STIS_Msk               (0x0fUL << HRPWM0_CSG_DCI_STIS_Pos)                     /*!< HRPWM0_CSG DCI: STIS Mask               */\r
+#define HRPWM0_CSG_DCI_SCS_Pos                20                                                      /*!< HRPWM0_CSG DCI: SCS Position            */\r
+#define HRPWM0_CSG_DCI_SCS_Msk                (0x03UL << HRPWM0_CSG_DCI_SCS_Pos)                      /*!< HRPWM0_CSG DCI: SCS Mask                */\r
+\r
+/* -------------------------------  HRPWM0_CSG_IES  ------------------------------- */\r
+#define HRPWM0_CSG_IES_SVLS_Pos               0                                                       /*!< HRPWM0_CSG IES: SVLS Position           */\r
+#define HRPWM0_CSG_IES_SVLS_Msk               (0x03UL << HRPWM0_CSG_IES_SVLS_Pos)                     /*!< HRPWM0_CSG IES: SVLS Mask               */\r
+#define HRPWM0_CSG_IES_STRES_Pos              2                                                       /*!< HRPWM0_CSG IES: STRES Position          */\r
+#define HRPWM0_CSG_IES_STRES_Msk              (0x03UL << HRPWM0_CSG_IES_STRES_Pos)                    /*!< HRPWM0_CSG IES: STRES Mask              */\r
+#define HRPWM0_CSG_IES_STPES_Pos              4                                                       /*!< HRPWM0_CSG IES: STPES Position          */\r
+#define HRPWM0_CSG_IES_STPES_Msk              (0x03UL << HRPWM0_CSG_IES_STPES_Pos)                    /*!< HRPWM0_CSG IES: STPES Mask              */\r
+#define HRPWM0_CSG_IES_TRGES_Pos              6                                                       /*!< HRPWM0_CSG IES: TRGES Position          */\r
+#define HRPWM0_CSG_IES_TRGES_Msk              (0x03UL << HRPWM0_CSG_IES_TRGES_Pos)                    /*!< HRPWM0_CSG IES: TRGES Mask              */\r
+#define HRPWM0_CSG_IES_STES_Pos               8                                                       /*!< HRPWM0_CSG IES: STES Position           */\r
+#define HRPWM0_CSG_IES_STES_Msk               (0x03UL << HRPWM0_CSG_IES_STES_Pos)                     /*!< HRPWM0_CSG IES: STES Mask               */\r
+\r
+/* --------------------------------  HRPWM0_CSG_SC  ------------------------------- */\r
+#define HRPWM0_CSG_SC_PSRM_Pos                0                                                       /*!< HRPWM0_CSG SC: PSRM Position            */\r
+#define HRPWM0_CSG_SC_PSRM_Msk                (0x03UL << HRPWM0_CSG_SC_PSRM_Pos)                      /*!< HRPWM0_CSG SC: PSRM Mask                */\r
+#define HRPWM0_CSG_SC_PSTM_Pos                2                                                       /*!< HRPWM0_CSG SC: PSTM Position            */\r
+#define HRPWM0_CSG_SC_PSTM_Msk                (0x03UL << HRPWM0_CSG_SC_PSTM_Pos)                      /*!< HRPWM0_CSG SC: PSTM Mask                */\r
+#define HRPWM0_CSG_SC_FPD_Pos                 4                                                       /*!< HRPWM0_CSG SC: FPD Position             */\r
+#define HRPWM0_CSG_SC_FPD_Msk                 (0x01UL << HRPWM0_CSG_SC_FPD_Pos)                       /*!< HRPWM0_CSG SC: FPD Mask                 */\r
+#define HRPWM0_CSG_SC_PSV_Pos                 5                                                       /*!< HRPWM0_CSG SC: PSV Position             */\r
+#define HRPWM0_CSG_SC_PSV_Msk                 (0x03UL << HRPWM0_CSG_SC_PSV_Pos)                       /*!< HRPWM0_CSG SC: PSV Mask                 */\r
+#define HRPWM0_CSG_SC_SCM_Pos                 8                                                       /*!< HRPWM0_CSG SC: SCM Position             */\r
+#define HRPWM0_CSG_SC_SCM_Msk                 (0x03UL << HRPWM0_CSG_SC_SCM_Pos)                       /*!< HRPWM0_CSG SC: SCM Mask                 */\r
+#define HRPWM0_CSG_SC_SSRM_Pos                10                                                      /*!< HRPWM0_CSG SC: SSRM Position            */\r
+#define HRPWM0_CSG_SC_SSRM_Msk                (0x03UL << HRPWM0_CSG_SC_SSRM_Pos)                      /*!< HRPWM0_CSG SC: SSRM Mask                */\r
+#define HRPWM0_CSG_SC_SSTM_Pos                12                                                      /*!< HRPWM0_CSG SC: SSTM Position            */\r
+#define HRPWM0_CSG_SC_SSTM_Msk                (0x03UL << HRPWM0_CSG_SC_SSTM_Pos)                      /*!< HRPWM0_CSG SC: SSTM Mask                */\r
+#define HRPWM0_CSG_SC_SVSC_Pos                14                                                      /*!< HRPWM0_CSG SC: SVSC Position            */\r
+#define HRPWM0_CSG_SC_SVSC_Msk                (0x03UL << HRPWM0_CSG_SC_SVSC_Pos)                      /*!< HRPWM0_CSG SC: SVSC Mask                */\r
+#define HRPWM0_CSG_SC_SWSM_Pos                16                                                      /*!< HRPWM0_CSG SC: SWSM Position            */\r
+#define HRPWM0_CSG_SC_SWSM_Msk                (0x03UL << HRPWM0_CSG_SC_SWSM_Pos)                      /*!< HRPWM0_CSG SC: SWSM Mask                */\r
+#define HRPWM0_CSG_SC_GCFG_Pos                18                                                      /*!< HRPWM0_CSG SC: GCFG Position            */\r
+#define HRPWM0_CSG_SC_GCFG_Msk                (0x03UL << HRPWM0_CSG_SC_GCFG_Pos)                      /*!< HRPWM0_CSG SC: GCFG Mask                */\r
+#define HRPWM0_CSG_SC_IST_Pos                 20                                                      /*!< HRPWM0_CSG SC: IST Position             */\r
+#define HRPWM0_CSG_SC_IST_Msk                 (0x01UL << HRPWM0_CSG_SC_IST_Pos)                       /*!< HRPWM0_CSG SC: IST Mask                 */\r
+#define HRPWM0_CSG_SC_PSE_Pos                 21                                                      /*!< HRPWM0_CSG SC: PSE Position             */\r
+#define HRPWM0_CSG_SC_PSE_Msk                 (0x01UL << HRPWM0_CSG_SC_PSE_Pos)                       /*!< HRPWM0_CSG SC: PSE Mask                 */\r
+#define HRPWM0_CSG_SC_PSWM_Pos                24                                                      /*!< HRPWM0_CSG SC: PSWM Position            */\r
+#define HRPWM0_CSG_SC_PSWM_Msk                (0x03UL << HRPWM0_CSG_SC_PSWM_Pos)                      /*!< HRPWM0_CSG SC: PSWM Mask                */\r
+\r
+/* --------------------------------  HRPWM0_CSG_PC  ------------------------------- */\r
+#define HRPWM0_CSG_PC_PSWV_Pos                0                                                       /*!< HRPWM0_CSG PC: PSWV Position            */\r
+#define HRPWM0_CSG_PC_PSWV_Msk                (0x3fUL << HRPWM0_CSG_PC_PSWV_Pos)                      /*!< HRPWM0_CSG PC: PSWV Mask                */\r
+\r
+/* -------------------------------  HRPWM0_CSG_DSV1  ------------------------------ */\r
+#define HRPWM0_CSG_DSV1_DSV1_Pos              0                                                       /*!< HRPWM0_CSG DSV1: DSV1 Position          */\r
+#define HRPWM0_CSG_DSV1_DSV1_Msk              (0x000003ffUL << HRPWM0_CSG_DSV1_DSV1_Pos)              /*!< HRPWM0_CSG DSV1: DSV1 Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG_DSV2  ------------------------------ */\r
+#define HRPWM0_CSG_DSV2_DSV2_Pos              0                                                       /*!< HRPWM0_CSG DSV2: DSV2 Position          */\r
+#define HRPWM0_CSG_DSV2_DSV2_Msk              (0x000003ffUL << HRPWM0_CSG_DSV2_DSV2_Pos)              /*!< HRPWM0_CSG DSV2: DSV2 Mask              */\r
+\r
+/* ------------------------------  HRPWM0_CSG_SDSV1  ------------------------------ */\r
+#define HRPWM0_CSG_SDSV1_SDSV1_Pos            0                                                       /*!< HRPWM0_CSG SDSV1: SDSV1 Position        */\r
+#define HRPWM0_CSG_SDSV1_SDSV1_Msk            (0x000003ffUL << HRPWM0_CSG_SDSV1_SDSV1_Pos)            /*!< HRPWM0_CSG SDSV1: SDSV1 Mask            */\r
+\r
+/* -------------------------------  HRPWM0_CSG_SPC  ------------------------------- */\r
+#define HRPWM0_CSG_SPC_SPSWV_Pos              0                                                       /*!< HRPWM0_CSG SPC: SPSWV Position          */\r
+#define HRPWM0_CSG_SPC_SPSWV_Msk              (0x3fUL << HRPWM0_CSG_SPC_SPSWV_Pos)                    /*!< HRPWM0_CSG SPC: SPSWV Mask              */\r
+\r
+/* --------------------------------  HRPWM0_CSG_CC  ------------------------------- */\r
+#define HRPWM0_CSG_CC_IBS_Pos                 0                                                       /*!< HRPWM0_CSG CC: IBS Position             */\r
+#define HRPWM0_CSG_CC_IBS_Msk                 (0x0fUL << HRPWM0_CSG_CC_IBS_Pos)                       /*!< HRPWM0_CSG CC: IBS Mask                 */\r
+#define HRPWM0_CSG_CC_IMCS_Pos                8                                                       /*!< HRPWM0_CSG CC: IMCS Position            */\r
+#define HRPWM0_CSG_CC_IMCS_Msk                (0x01UL << HRPWM0_CSG_CC_IMCS_Pos)                      /*!< HRPWM0_CSG CC: IMCS Mask                */\r
+#define HRPWM0_CSG_CC_IMCC_Pos                9                                                       /*!< HRPWM0_CSG CC: IMCC Position            */\r
+#define HRPWM0_CSG_CC_IMCC_Msk                (0x03UL << HRPWM0_CSG_CC_IMCC_Pos)                      /*!< HRPWM0_CSG CC: IMCC Mask                */\r
+#define HRPWM0_CSG_CC_ESE_Pos                 11                                                      /*!< HRPWM0_CSG CC: ESE Position             */\r
+#define HRPWM0_CSG_CC_ESE_Msk                 (0x01UL << HRPWM0_CSG_CC_ESE_Pos)                       /*!< HRPWM0_CSG CC: ESE Mask                 */\r
+#define HRPWM0_CSG_CC_OIE_Pos                 12                                                      /*!< HRPWM0_CSG CC: OIE Position             */\r
+#define HRPWM0_CSG_CC_OIE_Msk                 (0x01UL << HRPWM0_CSG_CC_OIE_Pos)                       /*!< HRPWM0_CSG CC: OIE Mask                 */\r
+#define HRPWM0_CSG_CC_OSE_Pos                 13                                                      /*!< HRPWM0_CSG CC: OSE Position             */\r
+#define HRPWM0_CSG_CC_OSE_Msk                 (0x01UL << HRPWM0_CSG_CC_OSE_Pos)                       /*!< HRPWM0_CSG CC: OSE Mask                 */\r
+#define HRPWM0_CSG_CC_BLMC_Pos                14                                                      /*!< HRPWM0_CSG CC: BLMC Position            */\r
+#define HRPWM0_CSG_CC_BLMC_Msk                (0x03UL << HRPWM0_CSG_CC_BLMC_Pos)                      /*!< HRPWM0_CSG CC: BLMC Mask                */\r
+#define HRPWM0_CSG_CC_EBE_Pos                 16                                                      /*!< HRPWM0_CSG CC: EBE Position             */\r
+#define HRPWM0_CSG_CC_EBE_Msk                 (0x01UL << HRPWM0_CSG_CC_EBE_Pos)                       /*!< HRPWM0_CSG CC: EBE Mask                 */\r
+#define HRPWM0_CSG_CC_COFE_Pos                17                                                      /*!< HRPWM0_CSG CC: COFE Position            */\r
+#define HRPWM0_CSG_CC_COFE_Msk                (0x01UL << HRPWM0_CSG_CC_COFE_Pos)                      /*!< HRPWM0_CSG CC: COFE Mask                */\r
+#define HRPWM0_CSG_CC_COFM_Pos                18                                                      /*!< HRPWM0_CSG CC: COFM Position            */\r
+#define HRPWM0_CSG_CC_COFM_Msk                (0x0fUL << HRPWM0_CSG_CC_COFM_Pos)                      /*!< HRPWM0_CSG CC: COFM Mask                */\r
+#define HRPWM0_CSG_CC_COFC_Pos                24                                                      /*!< HRPWM0_CSG CC: COFC Position            */\r
+#define HRPWM0_CSG_CC_COFC_Msk                (0x03UL << HRPWM0_CSG_CC_COFC_Pos)                      /*!< HRPWM0_CSG CC: COFC Mask                */\r
+\r
+/* -------------------------------  HRPWM0_CSG_PLC  ------------------------------- */\r
+#define HRPWM0_CSG_PLC_IPLS_Pos               0                                                       /*!< HRPWM0_CSG PLC: IPLS Position           */\r
+#define HRPWM0_CSG_PLC_IPLS_Msk               (0x0fUL << HRPWM0_CSG_PLC_IPLS_Pos)                     /*!< HRPWM0_CSG PLC: IPLS Mask               */\r
+#define HRPWM0_CSG_PLC_PLCL_Pos               8                                                       /*!< HRPWM0_CSG PLC: PLCL Position           */\r
+#define HRPWM0_CSG_PLC_PLCL_Msk               (0x03UL << HRPWM0_CSG_PLC_PLCL_Pos)                     /*!< HRPWM0_CSG PLC: PLCL Mask               */\r
+#define HRPWM0_CSG_PLC_PSL_Pos                10                                                      /*!< HRPWM0_CSG PLC: PSL Position            */\r
+#define HRPWM0_CSG_PLC_PSL_Msk                (0x01UL << HRPWM0_CSG_PLC_PSL_Pos)                      /*!< HRPWM0_CSG PLC: PSL Mask                */\r
+#define HRPWM0_CSG_PLC_PLSW_Pos               11                                                      /*!< HRPWM0_CSG PLC: PLSW Position           */\r
+#define HRPWM0_CSG_PLC_PLSW_Msk               (0x01UL << HRPWM0_CSG_PLC_PLSW_Pos)                     /*!< HRPWM0_CSG PLC: PLSW Mask               */\r
+#define HRPWM0_CSG_PLC_PLEC_Pos               12                                                      /*!< HRPWM0_CSG PLC: PLEC Position           */\r
+#define HRPWM0_CSG_PLC_PLEC_Msk               (0x03UL << HRPWM0_CSG_PLC_PLEC_Pos)                     /*!< HRPWM0_CSG PLC: PLEC Mask               */\r
+#define HRPWM0_CSG_PLC_PLXC_Pos               14                                                      /*!< HRPWM0_CSG PLC: PLXC Position           */\r
+#define HRPWM0_CSG_PLC_PLXC_Msk               (0x03UL << HRPWM0_CSG_PLC_PLXC_Pos)                     /*!< HRPWM0_CSG PLC: PLXC Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG_BLV  ------------------------------- */\r
+#define HRPWM0_CSG_BLV_BLV_Pos                0                                                       /*!< HRPWM0_CSG BLV: BLV Position            */\r
+#define HRPWM0_CSG_BLV_BLV_Msk                (0x000000ffUL << HRPWM0_CSG_BLV_BLV_Pos)                /*!< HRPWM0_CSG BLV: BLV Mask                */\r
+\r
+/* -------------------------------  HRPWM0_CSG_SRE  ------------------------------- */\r
+#define HRPWM0_CSG_SRE_VLS1E_Pos              0                                                       /*!< HRPWM0_CSG SRE: VLS1E Position          */\r
+#define HRPWM0_CSG_SRE_VLS1E_Msk              (0x01UL << HRPWM0_CSG_SRE_VLS1E_Pos)                    /*!< HRPWM0_CSG SRE: VLS1E Mask              */\r
+#define HRPWM0_CSG_SRE_VLS2E_Pos              1                                                       /*!< HRPWM0_CSG SRE: VLS2E Position          */\r
+#define HRPWM0_CSG_SRE_VLS2E_Msk              (0x01UL << HRPWM0_CSG_SRE_VLS2E_Pos)                    /*!< HRPWM0_CSG SRE: VLS2E Mask              */\r
+#define HRPWM0_CSG_SRE_TRGSE_Pos              2                                                       /*!< HRPWM0_CSG SRE: TRGSE Position          */\r
+#define HRPWM0_CSG_SRE_TRGSE_Msk              (0x01UL << HRPWM0_CSG_SRE_TRGSE_Pos)                    /*!< HRPWM0_CSG SRE: TRGSE Mask              */\r
+#define HRPWM0_CSG_SRE_STRSE_Pos              3                                                       /*!< HRPWM0_CSG SRE: STRSE Position          */\r
+#define HRPWM0_CSG_SRE_STRSE_Msk              (0x01UL << HRPWM0_CSG_SRE_STRSE_Pos)                    /*!< HRPWM0_CSG SRE: STRSE Mask              */\r
+#define HRPWM0_CSG_SRE_STPSE_Pos              4                                                       /*!< HRPWM0_CSG SRE: STPSE Position          */\r
+#define HRPWM0_CSG_SRE_STPSE_Msk              (0x01UL << HRPWM0_CSG_SRE_STPSE_Pos)                    /*!< HRPWM0_CSG SRE: STPSE Mask              */\r
+#define HRPWM0_CSG_SRE_STDE_Pos               5                                                       /*!< HRPWM0_CSG SRE: STDE Position           */\r
+#define HRPWM0_CSG_SRE_STDE_Msk               (0x01UL << HRPWM0_CSG_SRE_STDE_Pos)                     /*!< HRPWM0_CSG SRE: STDE Mask               */\r
+#define HRPWM0_CSG_SRE_CRSE_Pos               6                                                       /*!< HRPWM0_CSG SRE: CRSE Position           */\r
+#define HRPWM0_CSG_SRE_CRSE_Msk               (0x01UL << HRPWM0_CSG_SRE_CRSE_Pos)                     /*!< HRPWM0_CSG SRE: CRSE Mask               */\r
+#define HRPWM0_CSG_SRE_CFSE_Pos               7                                                       /*!< HRPWM0_CSG SRE: CFSE Position           */\r
+#define HRPWM0_CSG_SRE_CFSE_Msk               (0x01UL << HRPWM0_CSG_SRE_CFSE_Pos)                     /*!< HRPWM0_CSG SRE: CFSE Mask               */\r
+#define HRPWM0_CSG_SRE_CSEE_Pos               8                                                       /*!< HRPWM0_CSG SRE: CSEE Position           */\r
+#define HRPWM0_CSG_SRE_CSEE_Msk               (0x01UL << HRPWM0_CSG_SRE_CSEE_Pos)                     /*!< HRPWM0_CSG SRE: CSEE Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG_SRS  ------------------------------- */\r
+#define HRPWM0_CSG_SRS_VLS1S_Pos              0                                                       /*!< HRPWM0_CSG SRS: VLS1S Position          */\r
+#define HRPWM0_CSG_SRS_VLS1S_Msk              (0x03UL << HRPWM0_CSG_SRS_VLS1S_Pos)                    /*!< HRPWM0_CSG SRS: VLS1S Mask              */\r
+#define HRPWM0_CSG_SRS_VLS2S_Pos              2                                                       /*!< HRPWM0_CSG SRS: VLS2S Position          */\r
+#define HRPWM0_CSG_SRS_VLS2S_Msk              (0x03UL << HRPWM0_CSG_SRS_VLS2S_Pos)                    /*!< HRPWM0_CSG SRS: VLS2S Mask              */\r
+#define HRPWM0_CSG_SRS_TRLS_Pos               4                                                       /*!< HRPWM0_CSG SRS: TRLS Position           */\r
+#define HRPWM0_CSG_SRS_TRLS_Msk               (0x03UL << HRPWM0_CSG_SRS_TRLS_Pos)                     /*!< HRPWM0_CSG SRS: TRLS Mask               */\r
+#define HRPWM0_CSG_SRS_SSLS_Pos               6                                                       /*!< HRPWM0_CSG SRS: SSLS Position           */\r
+#define HRPWM0_CSG_SRS_SSLS_Msk               (0x03UL << HRPWM0_CSG_SRS_SSLS_Pos)                     /*!< HRPWM0_CSG SRS: SSLS Mask               */\r
+#define HRPWM0_CSG_SRS_STLS_Pos               8                                                       /*!< HRPWM0_CSG SRS: STLS Position           */\r
+#define HRPWM0_CSG_SRS_STLS_Msk               (0x03UL << HRPWM0_CSG_SRS_STLS_Pos)                     /*!< HRPWM0_CSG SRS: STLS Mask               */\r
+#define HRPWM0_CSG_SRS_CRFLS_Pos              10                                                      /*!< HRPWM0_CSG SRS: CRFLS Position          */\r
+#define HRPWM0_CSG_SRS_CRFLS_Msk              (0x03UL << HRPWM0_CSG_SRS_CRFLS_Pos)                    /*!< HRPWM0_CSG SRS: CRFLS Mask              */\r
+#define HRPWM0_CSG_SRS_CSLS_Pos               12                                                      /*!< HRPWM0_CSG SRS: CSLS Position           */\r
+#define HRPWM0_CSG_SRS_CSLS_Msk               (0x03UL << HRPWM0_CSG_SRS_CSLS_Pos)                     /*!< HRPWM0_CSG SRS: CSLS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG_SWS  ------------------------------- */\r
+#define HRPWM0_CSG_SWS_SVLS1_Pos              0                                                       /*!< HRPWM0_CSG SWS: SVLS1 Position          */\r
+#define HRPWM0_CSG_SWS_SVLS1_Msk              (0x01UL << HRPWM0_CSG_SWS_SVLS1_Pos)                    /*!< HRPWM0_CSG SWS: SVLS1 Mask              */\r
+#define HRPWM0_CSG_SWS_SVLS2_Pos              1                                                       /*!< HRPWM0_CSG SWS: SVLS2 Position          */\r
+#define HRPWM0_CSG_SWS_SVLS2_Msk              (0x01UL << HRPWM0_CSG_SWS_SVLS2_Pos)                    /*!< HRPWM0_CSG SWS: SVLS2 Mask              */\r
+#define HRPWM0_CSG_SWS_STRGS_Pos              2                                                       /*!< HRPWM0_CSG SWS: STRGS Position          */\r
+#define HRPWM0_CSG_SWS_STRGS_Msk              (0x01UL << HRPWM0_CSG_SWS_STRGS_Pos)                    /*!< HRPWM0_CSG SWS: STRGS Mask              */\r
+#define HRPWM0_CSG_SWS_SSTRS_Pos              3                                                       /*!< HRPWM0_CSG SWS: SSTRS Position          */\r
+#define HRPWM0_CSG_SWS_SSTRS_Msk              (0x01UL << HRPWM0_CSG_SWS_SSTRS_Pos)                    /*!< HRPWM0_CSG SWS: SSTRS Mask              */\r
+#define HRPWM0_CSG_SWS_SSTPS_Pos              4                                                       /*!< HRPWM0_CSG SWS: SSTPS Position          */\r
+#define HRPWM0_CSG_SWS_SSTPS_Msk              (0x01UL << HRPWM0_CSG_SWS_SSTPS_Pos)                    /*!< HRPWM0_CSG SWS: SSTPS Mask              */\r
+#define HRPWM0_CSG_SWS_SSTD_Pos               5                                                       /*!< HRPWM0_CSG SWS: SSTD Position           */\r
+#define HRPWM0_CSG_SWS_SSTD_Msk               (0x01UL << HRPWM0_CSG_SWS_SSTD_Pos)                     /*!< HRPWM0_CSG SWS: SSTD Mask               */\r
+#define HRPWM0_CSG_SWS_SCRS_Pos               6                                                       /*!< HRPWM0_CSG SWS: SCRS Position           */\r
+#define HRPWM0_CSG_SWS_SCRS_Msk               (0x01UL << HRPWM0_CSG_SWS_SCRS_Pos)                     /*!< HRPWM0_CSG SWS: SCRS Mask               */\r
+#define HRPWM0_CSG_SWS_SCFS_Pos               7                                                       /*!< HRPWM0_CSG SWS: SCFS Position           */\r
+#define HRPWM0_CSG_SWS_SCFS_Msk               (0x01UL << HRPWM0_CSG_SWS_SCFS_Pos)                     /*!< HRPWM0_CSG SWS: SCFS Mask               */\r
+#define HRPWM0_CSG_SWS_SCSS_Pos               8                                                       /*!< HRPWM0_CSG SWS: SCSS Position           */\r
+#define HRPWM0_CSG_SWS_SCSS_Msk               (0x01UL << HRPWM0_CSG_SWS_SCSS_Pos)                     /*!< HRPWM0_CSG SWS: SCSS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG_SWC  ------------------------------- */\r
+#define HRPWM0_CSG_SWC_CVLS1_Pos              0                                                       /*!< HRPWM0_CSG SWC: CVLS1 Position          */\r
+#define HRPWM0_CSG_SWC_CVLS1_Msk              (0x01UL << HRPWM0_CSG_SWC_CVLS1_Pos)                    /*!< HRPWM0_CSG SWC: CVLS1 Mask              */\r
+#define HRPWM0_CSG_SWC_CVLS2_Pos              1                                                       /*!< HRPWM0_CSG SWC: CVLS2 Position          */\r
+#define HRPWM0_CSG_SWC_CVLS2_Msk              (0x01UL << HRPWM0_CSG_SWC_CVLS2_Pos)                    /*!< HRPWM0_CSG SWC: CVLS2 Mask              */\r
+#define HRPWM0_CSG_SWC_CTRGS_Pos              2                                                       /*!< HRPWM0_CSG SWC: CTRGS Position          */\r
+#define HRPWM0_CSG_SWC_CTRGS_Msk              (0x01UL << HRPWM0_CSG_SWC_CTRGS_Pos)                    /*!< HRPWM0_CSG SWC: CTRGS Mask              */\r
+#define HRPWM0_CSG_SWC_CSTRS_Pos              3                                                       /*!< HRPWM0_CSG SWC: CSTRS Position          */\r
+#define HRPWM0_CSG_SWC_CSTRS_Msk              (0x01UL << HRPWM0_CSG_SWC_CSTRS_Pos)                    /*!< HRPWM0_CSG SWC: CSTRS Mask              */\r
+#define HRPWM0_CSG_SWC_CSTPS_Pos              4                                                       /*!< HRPWM0_CSG SWC: CSTPS Position          */\r
+#define HRPWM0_CSG_SWC_CSTPS_Msk              (0x01UL << HRPWM0_CSG_SWC_CSTPS_Pos)                    /*!< HRPWM0_CSG SWC: CSTPS Mask              */\r
+#define HRPWM0_CSG_SWC_CSTD_Pos               5                                                       /*!< HRPWM0_CSG SWC: CSTD Position           */\r
+#define HRPWM0_CSG_SWC_CSTD_Msk               (0x01UL << HRPWM0_CSG_SWC_CSTD_Pos)                     /*!< HRPWM0_CSG SWC: CSTD Mask               */\r
+#define HRPWM0_CSG_SWC_CCRS_Pos               6                                                       /*!< HRPWM0_CSG SWC: CCRS Position           */\r
+#define HRPWM0_CSG_SWC_CCRS_Msk               (0x01UL << HRPWM0_CSG_SWC_CCRS_Pos)                     /*!< HRPWM0_CSG SWC: CCRS Mask               */\r
+#define HRPWM0_CSG_SWC_CCFS_Pos               7                                                       /*!< HRPWM0_CSG SWC: CCFS Position           */\r
+#define HRPWM0_CSG_SWC_CCFS_Msk               (0x01UL << HRPWM0_CSG_SWC_CCFS_Pos)                     /*!< HRPWM0_CSG SWC: CCFS Mask               */\r
+#define HRPWM0_CSG_SWC_CCSS_Pos               8                                                       /*!< HRPWM0_CSG SWC: CCSS Position           */\r
+#define HRPWM0_CSG_SWC_CCSS_Msk               (0x01UL << HRPWM0_CSG_SWC_CCSS_Pos)                     /*!< HRPWM0_CSG SWC: CCSS Mask               */\r
+\r
+/* ------------------------------  HRPWM0_CSG_ISTAT  ------------------------------ */\r
+#define HRPWM0_CSG_ISTAT_VLS1S_Pos            0                                                       /*!< HRPWM0_CSG ISTAT: VLS1S Position        */\r
+#define HRPWM0_CSG_ISTAT_VLS1S_Msk            (0x01UL << HRPWM0_CSG_ISTAT_VLS1S_Pos)                  /*!< HRPWM0_CSG ISTAT: VLS1S Mask            */\r
+#define HRPWM0_CSG_ISTAT_VLS2S_Pos            1                                                       /*!< HRPWM0_CSG ISTAT: VLS2S Position        */\r
+#define HRPWM0_CSG_ISTAT_VLS2S_Msk            (0x01UL << HRPWM0_CSG_ISTAT_VLS2S_Pos)                  /*!< HRPWM0_CSG ISTAT: VLS2S Mask            */\r
+#define HRPWM0_CSG_ISTAT_TRGSS_Pos            2                                                       /*!< HRPWM0_CSG ISTAT: TRGSS Position        */\r
+#define HRPWM0_CSG_ISTAT_TRGSS_Msk            (0x01UL << HRPWM0_CSG_ISTAT_TRGSS_Pos)                  /*!< HRPWM0_CSG ISTAT: TRGSS Mask            */\r
+#define HRPWM0_CSG_ISTAT_STRSS_Pos            3                                                       /*!< HRPWM0_CSG ISTAT: STRSS Position        */\r
+#define HRPWM0_CSG_ISTAT_STRSS_Msk            (0x01UL << HRPWM0_CSG_ISTAT_STRSS_Pos)                  /*!< HRPWM0_CSG ISTAT: STRSS Mask            */\r
+#define HRPWM0_CSG_ISTAT_STPSS_Pos            4                                                       /*!< HRPWM0_CSG ISTAT: STPSS Position        */\r
+#define HRPWM0_CSG_ISTAT_STPSS_Msk            (0x01UL << HRPWM0_CSG_ISTAT_STPSS_Pos)                  /*!< HRPWM0_CSG ISTAT: STPSS Mask            */\r
+#define HRPWM0_CSG_ISTAT_STDS_Pos             5                                                       /*!< HRPWM0_CSG ISTAT: STDS Position         */\r
+#define HRPWM0_CSG_ISTAT_STDS_Msk             (0x01UL << HRPWM0_CSG_ISTAT_STDS_Pos)                   /*!< HRPWM0_CSG ISTAT: STDS Mask             */\r
+#define HRPWM0_CSG_ISTAT_CRSS_Pos             6                                                       /*!< HRPWM0_CSG ISTAT: CRSS Position         */\r
+#define HRPWM0_CSG_ISTAT_CRSS_Msk             (0x01UL << HRPWM0_CSG_ISTAT_CRSS_Pos)                   /*!< HRPWM0_CSG ISTAT: CRSS Mask             */\r
+#define HRPWM0_CSG_ISTAT_CFSS_Pos             7                                                       /*!< HRPWM0_CSG ISTAT: CFSS Position         */\r
+#define HRPWM0_CSG_ISTAT_CFSS_Msk             (0x01UL << HRPWM0_CSG_ISTAT_CFSS_Pos)                   /*!< HRPWM0_CSG ISTAT: CFSS Mask             */\r
+#define HRPWM0_CSG_ISTAT_CSES_Pos             8                                                       /*!< HRPWM0_CSG ISTAT: CSES Position         */\r
+#define HRPWM0_CSG_ISTAT_CSES_Msk             (0x01UL << HRPWM0_CSG_ISTAT_CSES_Pos)                   /*!< HRPWM0_CSG ISTAT: CSES Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_CSG0' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_CSG0_DCI  ------------------------------ */\r
+#define HRPWM0_CSG0_DCI_SVIS_Pos              0                                                       /*!< HRPWM0_CSG0 DCI: SVIS Position          */\r
+#define HRPWM0_CSG0_DCI_SVIS_Msk              (0x0fUL << HRPWM0_CSG0_DCI_SVIS_Pos)                    /*!< HRPWM0_CSG0 DCI: SVIS Mask              */\r
+#define HRPWM0_CSG0_DCI_STRIS_Pos             4                                                       /*!< HRPWM0_CSG0 DCI: STRIS Position         */\r
+#define HRPWM0_CSG0_DCI_STRIS_Msk             (0x0fUL << HRPWM0_CSG0_DCI_STRIS_Pos)                   /*!< HRPWM0_CSG0 DCI: STRIS Mask             */\r
+#define HRPWM0_CSG0_DCI_STPIS_Pos             8                                                       /*!< HRPWM0_CSG0 DCI: STPIS Position         */\r
+#define HRPWM0_CSG0_DCI_STPIS_Msk             (0x0fUL << HRPWM0_CSG0_DCI_STPIS_Pos)                   /*!< HRPWM0_CSG0 DCI: STPIS Mask             */\r
+#define HRPWM0_CSG0_DCI_TRGIS_Pos             12                                                      /*!< HRPWM0_CSG0 DCI: TRGIS Position         */\r
+#define HRPWM0_CSG0_DCI_TRGIS_Msk             (0x0fUL << HRPWM0_CSG0_DCI_TRGIS_Pos)                   /*!< HRPWM0_CSG0 DCI: TRGIS Mask             */\r
+#define HRPWM0_CSG0_DCI_STIS_Pos              16                                                      /*!< HRPWM0_CSG0 DCI: STIS Position          */\r
+#define HRPWM0_CSG0_DCI_STIS_Msk              (0x0fUL << HRPWM0_CSG0_DCI_STIS_Pos)                    /*!< HRPWM0_CSG0 DCI: STIS Mask              */\r
+#define HRPWM0_CSG0_DCI_SCS_Pos               20                                                      /*!< HRPWM0_CSG0 DCI: SCS Position           */\r
+#define HRPWM0_CSG0_DCI_SCS_Msk               (0x03UL << HRPWM0_CSG0_DCI_SCS_Pos)                     /*!< HRPWM0_CSG0 DCI: SCS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_IES  ------------------------------ */\r
+#define HRPWM0_CSG0_IES_SVLS_Pos              0                                                       /*!< HRPWM0_CSG0 IES: SVLS Position          */\r
+#define HRPWM0_CSG0_IES_SVLS_Msk              (0x03UL << HRPWM0_CSG0_IES_SVLS_Pos)                    /*!< HRPWM0_CSG0 IES: SVLS Mask              */\r
+#define HRPWM0_CSG0_IES_STRES_Pos             2                                                       /*!< HRPWM0_CSG0 IES: STRES Position         */\r
+#define HRPWM0_CSG0_IES_STRES_Msk             (0x03UL << HRPWM0_CSG0_IES_STRES_Pos)                   /*!< HRPWM0_CSG0 IES: STRES Mask             */\r
+#define HRPWM0_CSG0_IES_STPES_Pos             4                                                       /*!< HRPWM0_CSG0 IES: STPES Position         */\r
+#define HRPWM0_CSG0_IES_STPES_Msk             (0x03UL << HRPWM0_CSG0_IES_STPES_Pos)                   /*!< HRPWM0_CSG0 IES: STPES Mask             */\r
+#define HRPWM0_CSG0_IES_TRGES_Pos             6                                                       /*!< HRPWM0_CSG0 IES: TRGES Position         */\r
+#define HRPWM0_CSG0_IES_TRGES_Msk             (0x03UL << HRPWM0_CSG0_IES_TRGES_Pos)                   /*!< HRPWM0_CSG0 IES: TRGES Mask             */\r
+#define HRPWM0_CSG0_IES_STES_Pos              8                                                       /*!< HRPWM0_CSG0 IES: STES Position          */\r
+#define HRPWM0_CSG0_IES_STES_Msk              (0x03UL << HRPWM0_CSG0_IES_STES_Pos)                    /*!< HRPWM0_CSG0 IES: STES Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SC  ------------------------------- */\r
+#define HRPWM0_CSG0_SC_PSRM_Pos               0                                                       /*!< HRPWM0_CSG0 SC: PSRM Position           */\r
+#define HRPWM0_CSG0_SC_PSRM_Msk               (0x03UL << HRPWM0_CSG0_SC_PSRM_Pos)                     /*!< HRPWM0_CSG0 SC: PSRM Mask               */\r
+#define HRPWM0_CSG0_SC_PSTM_Pos               2                                                       /*!< HRPWM0_CSG0 SC: PSTM Position           */\r
+#define HRPWM0_CSG0_SC_PSTM_Msk               (0x03UL << HRPWM0_CSG0_SC_PSTM_Pos)                     /*!< HRPWM0_CSG0 SC: PSTM Mask               */\r
+#define HRPWM0_CSG0_SC_FPD_Pos                4                                                       /*!< HRPWM0_CSG0 SC: FPD Position            */\r
+#define HRPWM0_CSG0_SC_FPD_Msk                (0x01UL << HRPWM0_CSG0_SC_FPD_Pos)                      /*!< HRPWM0_CSG0 SC: FPD Mask                */\r
+#define HRPWM0_CSG0_SC_PSV_Pos                5                                                       /*!< HRPWM0_CSG0 SC: PSV Position            */\r
+#define HRPWM0_CSG0_SC_PSV_Msk                (0x03UL << HRPWM0_CSG0_SC_PSV_Pos)                      /*!< HRPWM0_CSG0 SC: PSV Mask                */\r
+#define HRPWM0_CSG0_SC_SCM_Pos                8                                                       /*!< HRPWM0_CSG0 SC: SCM Position            */\r
+#define HRPWM0_CSG0_SC_SCM_Msk                (0x03UL << HRPWM0_CSG0_SC_SCM_Pos)                      /*!< HRPWM0_CSG0 SC: SCM Mask                */\r
+#define HRPWM0_CSG0_SC_SSRM_Pos               10                                                      /*!< HRPWM0_CSG0 SC: SSRM Position           */\r
+#define HRPWM0_CSG0_SC_SSRM_Msk               (0x03UL << HRPWM0_CSG0_SC_SSRM_Pos)                     /*!< HRPWM0_CSG0 SC: SSRM Mask               */\r
+#define HRPWM0_CSG0_SC_SSTM_Pos               12                                                      /*!< HRPWM0_CSG0 SC: SSTM Position           */\r
+#define HRPWM0_CSG0_SC_SSTM_Msk               (0x03UL << HRPWM0_CSG0_SC_SSTM_Pos)                     /*!< HRPWM0_CSG0 SC: SSTM Mask               */\r
+#define HRPWM0_CSG0_SC_SVSC_Pos               14                                                      /*!< HRPWM0_CSG0 SC: SVSC Position           */\r
+#define HRPWM0_CSG0_SC_SVSC_Msk               (0x03UL << HRPWM0_CSG0_SC_SVSC_Pos)                     /*!< HRPWM0_CSG0 SC: SVSC Mask               */\r
+#define HRPWM0_CSG0_SC_SWSM_Pos               16                                                      /*!< HRPWM0_CSG0 SC: SWSM Position           */\r
+#define HRPWM0_CSG0_SC_SWSM_Msk               (0x03UL << HRPWM0_CSG0_SC_SWSM_Pos)                     /*!< HRPWM0_CSG0 SC: SWSM Mask               */\r
+#define HRPWM0_CSG0_SC_GCFG_Pos               18                                                      /*!< HRPWM0_CSG0 SC: GCFG Position           */\r
+#define HRPWM0_CSG0_SC_GCFG_Msk               (0x03UL << HRPWM0_CSG0_SC_GCFG_Pos)                     /*!< HRPWM0_CSG0 SC: GCFG Mask               */\r
+#define HRPWM0_CSG0_SC_IST_Pos                20                                                      /*!< HRPWM0_CSG0 SC: IST Position            */\r
+#define HRPWM0_CSG0_SC_IST_Msk                (0x01UL << HRPWM0_CSG0_SC_IST_Pos)                      /*!< HRPWM0_CSG0 SC: IST Mask                */\r
+#define HRPWM0_CSG0_SC_PSE_Pos                21                                                      /*!< HRPWM0_CSG0 SC: PSE Position            */\r
+#define HRPWM0_CSG0_SC_PSE_Msk                (0x01UL << HRPWM0_CSG0_SC_PSE_Pos)                      /*!< HRPWM0_CSG0 SC: PSE Mask                */\r
+#define HRPWM0_CSG0_SC_PSWM_Pos               24                                                      /*!< HRPWM0_CSG0 SC: PSWM Position           */\r
+#define HRPWM0_CSG0_SC_PSWM_Msk               (0x03UL << HRPWM0_CSG0_SC_PSWM_Pos)                     /*!< HRPWM0_CSG0 SC: PSWM Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_PC  ------------------------------- */\r
+#define HRPWM0_CSG0_PC_PSWV_Pos               0                                                       /*!< HRPWM0_CSG0 PC: PSWV Position           */\r
+#define HRPWM0_CSG0_PC_PSWV_Msk               (0x3fUL << HRPWM0_CSG0_PC_PSWV_Pos)                     /*!< HRPWM0_CSG0 PC: PSWV Mask               */\r
+\r
+/* ------------------------------  HRPWM0_CSG0_DSV1  ------------------------------ */\r
+#define HRPWM0_CSG0_DSV1_DSV1_Pos             0                                                       /*!< HRPWM0_CSG0 DSV1: DSV1 Position         */\r
+#define HRPWM0_CSG0_DSV1_DSV1_Msk             (0x000003ffUL << HRPWM0_CSG0_DSV1_DSV1_Pos)             /*!< HRPWM0_CSG0 DSV1: DSV1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG0_DSV2  ------------------------------ */\r
+#define HRPWM0_CSG0_DSV2_DSV2_Pos             0                                                       /*!< HRPWM0_CSG0 DSV2: DSV2 Position         */\r
+#define HRPWM0_CSG0_DSV2_DSV2_Msk             (0x000003ffUL << HRPWM0_CSG0_DSV2_DSV2_Pos)             /*!< HRPWM0_CSG0 DSV2: DSV2 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG0_SDSV1  ----------------------------- */\r
+#define HRPWM0_CSG0_SDSV1_SDSV1_Pos           0                                                       /*!< HRPWM0_CSG0 SDSV1: SDSV1 Position       */\r
+#define HRPWM0_CSG0_SDSV1_SDSV1_Msk           (0x000003ffUL << HRPWM0_CSG0_SDSV1_SDSV1_Pos)           /*!< HRPWM0_CSG0 SDSV1: SDSV1 Mask           */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SPC  ------------------------------ */\r
+#define HRPWM0_CSG0_SPC_SPSWV_Pos             0                                                       /*!< HRPWM0_CSG0 SPC: SPSWV Position         */\r
+#define HRPWM0_CSG0_SPC_SPSWV_Msk             (0x3fUL << HRPWM0_CSG0_SPC_SPSWV_Pos)                   /*!< HRPWM0_CSG0 SPC: SPSWV Mask             */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_CC  ------------------------------- */\r
+#define HRPWM0_CSG0_CC_IBS_Pos                0                                                       /*!< HRPWM0_CSG0 CC: IBS Position            */\r
+#define HRPWM0_CSG0_CC_IBS_Msk                (0x0fUL << HRPWM0_CSG0_CC_IBS_Pos)                      /*!< HRPWM0_CSG0 CC: IBS Mask                */\r
+#define HRPWM0_CSG0_CC_IMCS_Pos               8                                                       /*!< HRPWM0_CSG0 CC: IMCS Position           */\r
+#define HRPWM0_CSG0_CC_IMCS_Msk               (0x01UL << HRPWM0_CSG0_CC_IMCS_Pos)                     /*!< HRPWM0_CSG0 CC: IMCS Mask               */\r
+#define HRPWM0_CSG0_CC_IMCC_Pos               9                                                       /*!< HRPWM0_CSG0 CC: IMCC Position           */\r
+#define HRPWM0_CSG0_CC_IMCC_Msk               (0x03UL << HRPWM0_CSG0_CC_IMCC_Pos)                     /*!< HRPWM0_CSG0 CC: IMCC Mask               */\r
+#define HRPWM0_CSG0_CC_ESE_Pos                11                                                      /*!< HRPWM0_CSG0 CC: ESE Position            */\r
+#define HRPWM0_CSG0_CC_ESE_Msk                (0x01UL << HRPWM0_CSG0_CC_ESE_Pos)                      /*!< HRPWM0_CSG0 CC: ESE Mask                */\r
+#define HRPWM0_CSG0_CC_OIE_Pos                12                                                      /*!< HRPWM0_CSG0 CC: OIE Position            */\r
+#define HRPWM0_CSG0_CC_OIE_Msk                (0x01UL << HRPWM0_CSG0_CC_OIE_Pos)                      /*!< HRPWM0_CSG0 CC: OIE Mask                */\r
+#define HRPWM0_CSG0_CC_OSE_Pos                13                                                      /*!< HRPWM0_CSG0 CC: OSE Position            */\r
+#define HRPWM0_CSG0_CC_OSE_Msk                (0x01UL << HRPWM0_CSG0_CC_OSE_Pos)                      /*!< HRPWM0_CSG0 CC: OSE Mask                */\r
+#define HRPWM0_CSG0_CC_BLMC_Pos               14                                                      /*!< HRPWM0_CSG0 CC: BLMC Position           */\r
+#define HRPWM0_CSG0_CC_BLMC_Msk               (0x03UL << HRPWM0_CSG0_CC_BLMC_Pos)                     /*!< HRPWM0_CSG0 CC: BLMC Mask               */\r
+#define HRPWM0_CSG0_CC_EBE_Pos                16                                                      /*!< HRPWM0_CSG0 CC: EBE Position            */\r
+#define HRPWM0_CSG0_CC_EBE_Msk                (0x01UL << HRPWM0_CSG0_CC_EBE_Pos)                      /*!< HRPWM0_CSG0 CC: EBE Mask                */\r
+#define HRPWM0_CSG0_CC_COFE_Pos               17                                                      /*!< HRPWM0_CSG0 CC: COFE Position           */\r
+#define HRPWM0_CSG0_CC_COFE_Msk               (0x01UL << HRPWM0_CSG0_CC_COFE_Pos)                     /*!< HRPWM0_CSG0 CC: COFE Mask               */\r
+#define HRPWM0_CSG0_CC_COFM_Pos               18                                                      /*!< HRPWM0_CSG0 CC: COFM Position           */\r
+#define HRPWM0_CSG0_CC_COFM_Msk               (0x0fUL << HRPWM0_CSG0_CC_COFM_Pos)                     /*!< HRPWM0_CSG0 CC: COFM Mask               */\r
+#define HRPWM0_CSG0_CC_COFC_Pos               24                                                      /*!< HRPWM0_CSG0 CC: COFC Position           */\r
+#define HRPWM0_CSG0_CC_COFC_Msk               (0x03UL << HRPWM0_CSG0_CC_COFC_Pos)                     /*!< HRPWM0_CSG0 CC: COFC Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_PLC  ------------------------------ */\r
+#define HRPWM0_CSG0_PLC_IPLS_Pos              0                                                       /*!< HRPWM0_CSG0 PLC: IPLS Position          */\r
+#define HRPWM0_CSG0_PLC_IPLS_Msk              (0x0fUL << HRPWM0_CSG0_PLC_IPLS_Pos)                    /*!< HRPWM0_CSG0 PLC: IPLS Mask              */\r
+#define HRPWM0_CSG0_PLC_PLCL_Pos              8                                                       /*!< HRPWM0_CSG0 PLC: PLCL Position          */\r
+#define HRPWM0_CSG0_PLC_PLCL_Msk              (0x03UL << HRPWM0_CSG0_PLC_PLCL_Pos)                    /*!< HRPWM0_CSG0 PLC: PLCL Mask              */\r
+#define HRPWM0_CSG0_PLC_PSL_Pos               10                                                      /*!< HRPWM0_CSG0 PLC: PSL Position           */\r
+#define HRPWM0_CSG0_PLC_PSL_Msk               (0x01UL << HRPWM0_CSG0_PLC_PSL_Pos)                     /*!< HRPWM0_CSG0 PLC: PSL Mask               */\r
+#define HRPWM0_CSG0_PLC_PLSW_Pos              11                                                      /*!< HRPWM0_CSG0 PLC: PLSW Position          */\r
+#define HRPWM0_CSG0_PLC_PLSW_Msk              (0x01UL << HRPWM0_CSG0_PLC_PLSW_Pos)                    /*!< HRPWM0_CSG0 PLC: PLSW Mask              */\r
+#define HRPWM0_CSG0_PLC_PLEC_Pos              12                                                      /*!< HRPWM0_CSG0 PLC: PLEC Position          */\r
+#define HRPWM0_CSG0_PLC_PLEC_Msk              (0x03UL << HRPWM0_CSG0_PLC_PLEC_Pos)                    /*!< HRPWM0_CSG0 PLC: PLEC Mask              */\r
+#define HRPWM0_CSG0_PLC_PLXC_Pos              14                                                      /*!< HRPWM0_CSG0 PLC: PLXC Position          */\r
+#define HRPWM0_CSG0_PLC_PLXC_Msk              (0x03UL << HRPWM0_CSG0_PLC_PLXC_Pos)                    /*!< HRPWM0_CSG0 PLC: PLXC Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_BLV  ------------------------------ */\r
+#define HRPWM0_CSG0_BLV_BLV_Pos               0                                                       /*!< HRPWM0_CSG0 BLV: BLV Position           */\r
+#define HRPWM0_CSG0_BLV_BLV_Msk               (0x000000ffUL << HRPWM0_CSG0_BLV_BLV_Pos)               /*!< HRPWM0_CSG0 BLV: BLV Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SRE  ------------------------------ */\r
+#define HRPWM0_CSG0_SRE_VLS1E_Pos             0                                                       /*!< HRPWM0_CSG0 SRE: VLS1E Position         */\r
+#define HRPWM0_CSG0_SRE_VLS1E_Msk             (0x01UL << HRPWM0_CSG0_SRE_VLS1E_Pos)                   /*!< HRPWM0_CSG0 SRE: VLS1E Mask             */\r
+#define HRPWM0_CSG0_SRE_VLS2E_Pos             1                                                       /*!< HRPWM0_CSG0 SRE: VLS2E Position         */\r
+#define HRPWM0_CSG0_SRE_VLS2E_Msk             (0x01UL << HRPWM0_CSG0_SRE_VLS2E_Pos)                   /*!< HRPWM0_CSG0 SRE: VLS2E Mask             */\r
+#define HRPWM0_CSG0_SRE_TRGSE_Pos             2                                                       /*!< HRPWM0_CSG0 SRE: TRGSE Position         */\r
+#define HRPWM0_CSG0_SRE_TRGSE_Msk             (0x01UL << HRPWM0_CSG0_SRE_TRGSE_Pos)                   /*!< HRPWM0_CSG0 SRE: TRGSE Mask             */\r
+#define HRPWM0_CSG0_SRE_STRSE_Pos             3                                                       /*!< HRPWM0_CSG0 SRE: STRSE Position         */\r
+#define HRPWM0_CSG0_SRE_STRSE_Msk             (0x01UL << HRPWM0_CSG0_SRE_STRSE_Pos)                   /*!< HRPWM0_CSG0 SRE: STRSE Mask             */\r
+#define HRPWM0_CSG0_SRE_STPSE_Pos             4                                                       /*!< HRPWM0_CSG0 SRE: STPSE Position         */\r
+#define HRPWM0_CSG0_SRE_STPSE_Msk             (0x01UL << HRPWM0_CSG0_SRE_STPSE_Pos)                   /*!< HRPWM0_CSG0 SRE: STPSE Mask             */\r
+#define HRPWM0_CSG0_SRE_STDE_Pos              5                                                       /*!< HRPWM0_CSG0 SRE: STDE Position          */\r
+#define HRPWM0_CSG0_SRE_STDE_Msk              (0x01UL << HRPWM0_CSG0_SRE_STDE_Pos)                    /*!< HRPWM0_CSG0 SRE: STDE Mask              */\r
+#define HRPWM0_CSG0_SRE_CRSE_Pos              6                                                       /*!< HRPWM0_CSG0 SRE: CRSE Position          */\r
+#define HRPWM0_CSG0_SRE_CRSE_Msk              (0x01UL << HRPWM0_CSG0_SRE_CRSE_Pos)                    /*!< HRPWM0_CSG0 SRE: CRSE Mask              */\r
+#define HRPWM0_CSG0_SRE_CFSE_Pos              7                                                       /*!< HRPWM0_CSG0 SRE: CFSE Position          */\r
+#define HRPWM0_CSG0_SRE_CFSE_Msk              (0x01UL << HRPWM0_CSG0_SRE_CFSE_Pos)                    /*!< HRPWM0_CSG0 SRE: CFSE Mask              */\r
+#define HRPWM0_CSG0_SRE_CSEE_Pos              8                                                       /*!< HRPWM0_CSG0 SRE: CSEE Position          */\r
+#define HRPWM0_CSG0_SRE_CSEE_Msk              (0x01UL << HRPWM0_CSG0_SRE_CSEE_Pos)                    /*!< HRPWM0_CSG0 SRE: CSEE Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SRS  ------------------------------ */\r
+#define HRPWM0_CSG0_SRS_VLS1S_Pos             0                                                       /*!< HRPWM0_CSG0 SRS: VLS1S Position         */\r
+#define HRPWM0_CSG0_SRS_VLS1S_Msk             (0x03UL << HRPWM0_CSG0_SRS_VLS1S_Pos)                   /*!< HRPWM0_CSG0 SRS: VLS1S Mask             */\r
+#define HRPWM0_CSG0_SRS_VLS2S_Pos             2                                                       /*!< HRPWM0_CSG0 SRS: VLS2S Position         */\r
+#define HRPWM0_CSG0_SRS_VLS2S_Msk             (0x03UL << HRPWM0_CSG0_SRS_VLS2S_Pos)                   /*!< HRPWM0_CSG0 SRS: VLS2S Mask             */\r
+#define HRPWM0_CSG0_SRS_TRLS_Pos              4                                                       /*!< HRPWM0_CSG0 SRS: TRLS Position          */\r
+#define HRPWM0_CSG0_SRS_TRLS_Msk              (0x03UL << HRPWM0_CSG0_SRS_TRLS_Pos)                    /*!< HRPWM0_CSG0 SRS: TRLS Mask              */\r
+#define HRPWM0_CSG0_SRS_SSLS_Pos              6                                                       /*!< HRPWM0_CSG0 SRS: SSLS Position          */\r
+#define HRPWM0_CSG0_SRS_SSLS_Msk              (0x03UL << HRPWM0_CSG0_SRS_SSLS_Pos)                    /*!< HRPWM0_CSG0 SRS: SSLS Mask              */\r
+#define HRPWM0_CSG0_SRS_STLS_Pos              8                                                       /*!< HRPWM0_CSG0 SRS: STLS Position          */\r
+#define HRPWM0_CSG0_SRS_STLS_Msk              (0x03UL << HRPWM0_CSG0_SRS_STLS_Pos)                    /*!< HRPWM0_CSG0 SRS: STLS Mask              */\r
+#define HRPWM0_CSG0_SRS_CRFLS_Pos             10                                                      /*!< HRPWM0_CSG0 SRS: CRFLS Position         */\r
+#define HRPWM0_CSG0_SRS_CRFLS_Msk             (0x03UL << HRPWM0_CSG0_SRS_CRFLS_Pos)                   /*!< HRPWM0_CSG0 SRS: CRFLS Mask             */\r
+#define HRPWM0_CSG0_SRS_CSLS_Pos              12                                                      /*!< HRPWM0_CSG0 SRS: CSLS Position          */\r
+#define HRPWM0_CSG0_SRS_CSLS_Msk              (0x03UL << HRPWM0_CSG0_SRS_CSLS_Pos)                    /*!< HRPWM0_CSG0 SRS: CSLS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SWS  ------------------------------ */\r
+#define HRPWM0_CSG0_SWS_SVLS1_Pos             0                                                       /*!< HRPWM0_CSG0 SWS: SVLS1 Position         */\r
+#define HRPWM0_CSG0_SWS_SVLS1_Msk             (0x01UL << HRPWM0_CSG0_SWS_SVLS1_Pos)                   /*!< HRPWM0_CSG0 SWS: SVLS1 Mask             */\r
+#define HRPWM0_CSG0_SWS_SVLS2_Pos             1                                                       /*!< HRPWM0_CSG0 SWS: SVLS2 Position         */\r
+#define HRPWM0_CSG0_SWS_SVLS2_Msk             (0x01UL << HRPWM0_CSG0_SWS_SVLS2_Pos)                   /*!< HRPWM0_CSG0 SWS: SVLS2 Mask             */\r
+#define HRPWM0_CSG0_SWS_STRGS_Pos             2                                                       /*!< HRPWM0_CSG0 SWS: STRGS Position         */\r
+#define HRPWM0_CSG0_SWS_STRGS_Msk             (0x01UL << HRPWM0_CSG0_SWS_STRGS_Pos)                   /*!< HRPWM0_CSG0 SWS: STRGS Mask             */\r
+#define HRPWM0_CSG0_SWS_SSTRS_Pos             3                                                       /*!< HRPWM0_CSG0 SWS: SSTRS Position         */\r
+#define HRPWM0_CSG0_SWS_SSTRS_Msk             (0x01UL << HRPWM0_CSG0_SWS_SSTRS_Pos)                   /*!< HRPWM0_CSG0 SWS: SSTRS Mask             */\r
+#define HRPWM0_CSG0_SWS_SSTPS_Pos             4                                                       /*!< HRPWM0_CSG0 SWS: SSTPS Position         */\r
+#define HRPWM0_CSG0_SWS_SSTPS_Msk             (0x01UL << HRPWM0_CSG0_SWS_SSTPS_Pos)                   /*!< HRPWM0_CSG0 SWS: SSTPS Mask             */\r
+#define HRPWM0_CSG0_SWS_SSTD_Pos              5                                                       /*!< HRPWM0_CSG0 SWS: SSTD Position          */\r
+#define HRPWM0_CSG0_SWS_SSTD_Msk              (0x01UL << HRPWM0_CSG0_SWS_SSTD_Pos)                    /*!< HRPWM0_CSG0 SWS: SSTD Mask              */\r
+#define HRPWM0_CSG0_SWS_SCRS_Pos              6                                                       /*!< HRPWM0_CSG0 SWS: SCRS Position          */\r
+#define HRPWM0_CSG0_SWS_SCRS_Msk              (0x01UL << HRPWM0_CSG0_SWS_SCRS_Pos)                    /*!< HRPWM0_CSG0 SWS: SCRS Mask              */\r
+#define HRPWM0_CSG0_SWS_SCFS_Pos              7                                                       /*!< HRPWM0_CSG0 SWS: SCFS Position          */\r
+#define HRPWM0_CSG0_SWS_SCFS_Msk              (0x01UL << HRPWM0_CSG0_SWS_SCFS_Pos)                    /*!< HRPWM0_CSG0 SWS: SCFS Mask              */\r
+#define HRPWM0_CSG0_SWS_SCSS_Pos              8                                                       /*!< HRPWM0_CSG0 SWS: SCSS Position          */\r
+#define HRPWM0_CSG0_SWS_SCSS_Msk              (0x01UL << HRPWM0_CSG0_SWS_SCSS_Pos)                    /*!< HRPWM0_CSG0 SWS: SCSS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG0_SWC  ------------------------------ */\r
+#define HRPWM0_CSG0_SWC_CVLS1_Pos             0                                                       /*!< HRPWM0_CSG0 SWC: CVLS1 Position         */\r
+#define HRPWM0_CSG0_SWC_CVLS1_Msk             (0x01UL << HRPWM0_CSG0_SWC_CVLS1_Pos)                   /*!< HRPWM0_CSG0 SWC: CVLS1 Mask             */\r
+#define HRPWM0_CSG0_SWC_CVLS2_Pos             1                                                       /*!< HRPWM0_CSG0 SWC: CVLS2 Position         */\r
+#define HRPWM0_CSG0_SWC_CVLS2_Msk             (0x01UL << HRPWM0_CSG0_SWC_CVLS2_Pos)                   /*!< HRPWM0_CSG0 SWC: CVLS2 Mask             */\r
+#define HRPWM0_CSG0_SWC_CTRGS_Pos             2                                                       /*!< HRPWM0_CSG0 SWC: CTRGS Position         */\r
+#define HRPWM0_CSG0_SWC_CTRGS_Msk             (0x01UL << HRPWM0_CSG0_SWC_CTRGS_Pos)                   /*!< HRPWM0_CSG0 SWC: CTRGS Mask             */\r
+#define HRPWM0_CSG0_SWC_CSTRS_Pos             3                                                       /*!< HRPWM0_CSG0 SWC: CSTRS Position         */\r
+#define HRPWM0_CSG0_SWC_CSTRS_Msk             (0x01UL << HRPWM0_CSG0_SWC_CSTRS_Pos)                   /*!< HRPWM0_CSG0 SWC: CSTRS Mask             */\r
+#define HRPWM0_CSG0_SWC_CSTPS_Pos             4                                                       /*!< HRPWM0_CSG0 SWC: CSTPS Position         */\r
+#define HRPWM0_CSG0_SWC_CSTPS_Msk             (0x01UL << HRPWM0_CSG0_SWC_CSTPS_Pos)                   /*!< HRPWM0_CSG0 SWC: CSTPS Mask             */\r
+#define HRPWM0_CSG0_SWC_CSTD_Pos              5                                                       /*!< HRPWM0_CSG0 SWC: CSTD Position          */\r
+#define HRPWM0_CSG0_SWC_CSTD_Msk              (0x01UL << HRPWM0_CSG0_SWC_CSTD_Pos)                    /*!< HRPWM0_CSG0 SWC: CSTD Mask              */\r
+#define HRPWM0_CSG0_SWC_CCRS_Pos              6                                                       /*!< HRPWM0_CSG0 SWC: CCRS Position          */\r
+#define HRPWM0_CSG0_SWC_CCRS_Msk              (0x01UL << HRPWM0_CSG0_SWC_CCRS_Pos)                    /*!< HRPWM0_CSG0 SWC: CCRS Mask              */\r
+#define HRPWM0_CSG0_SWC_CCFS_Pos              7                                                       /*!< HRPWM0_CSG0 SWC: CCFS Position          */\r
+#define HRPWM0_CSG0_SWC_CCFS_Msk              (0x01UL << HRPWM0_CSG0_SWC_CCFS_Pos)                    /*!< HRPWM0_CSG0 SWC: CCFS Mask              */\r
+#define HRPWM0_CSG0_SWC_CCSS_Pos              8                                                       /*!< HRPWM0_CSG0 SWC: CCSS Position          */\r
+#define HRPWM0_CSG0_SWC_CCSS_Msk              (0x01UL << HRPWM0_CSG0_SWC_CCSS_Pos)                    /*!< HRPWM0_CSG0 SWC: CCSS Mask              */\r
+\r
+/* ------------------------------  HRPWM0_CSG0_ISTAT  ----------------------------- */\r
+#define HRPWM0_CSG0_ISTAT_VLS1S_Pos           0                                                       /*!< HRPWM0_CSG0 ISTAT: VLS1S Position       */\r
+#define HRPWM0_CSG0_ISTAT_VLS1S_Msk           (0x01UL << HRPWM0_CSG0_ISTAT_VLS1S_Pos)                 /*!< HRPWM0_CSG0 ISTAT: VLS1S Mask           */\r
+#define HRPWM0_CSG0_ISTAT_VLS2S_Pos           1                                                       /*!< HRPWM0_CSG0 ISTAT: VLS2S Position       */\r
+#define HRPWM0_CSG0_ISTAT_VLS2S_Msk           (0x01UL << HRPWM0_CSG0_ISTAT_VLS2S_Pos)                 /*!< HRPWM0_CSG0 ISTAT: VLS2S Mask           */\r
+#define HRPWM0_CSG0_ISTAT_TRGSS_Pos           2                                                       /*!< HRPWM0_CSG0 ISTAT: TRGSS Position       */\r
+#define HRPWM0_CSG0_ISTAT_TRGSS_Msk           (0x01UL << HRPWM0_CSG0_ISTAT_TRGSS_Pos)                 /*!< HRPWM0_CSG0 ISTAT: TRGSS Mask           */\r
+#define HRPWM0_CSG0_ISTAT_STRSS_Pos           3                                                       /*!< HRPWM0_CSG0 ISTAT: STRSS Position       */\r
+#define HRPWM0_CSG0_ISTAT_STRSS_Msk           (0x01UL << HRPWM0_CSG0_ISTAT_STRSS_Pos)                 /*!< HRPWM0_CSG0 ISTAT: STRSS Mask           */\r
+#define HRPWM0_CSG0_ISTAT_STPSS_Pos           4                                                       /*!< HRPWM0_CSG0 ISTAT: STPSS Position       */\r
+#define HRPWM0_CSG0_ISTAT_STPSS_Msk           (0x01UL << HRPWM0_CSG0_ISTAT_STPSS_Pos)                 /*!< HRPWM0_CSG0 ISTAT: STPSS Mask           */\r
+#define HRPWM0_CSG0_ISTAT_STDS_Pos            5                                                       /*!< HRPWM0_CSG0 ISTAT: STDS Position        */\r
+#define HRPWM0_CSG0_ISTAT_STDS_Msk            (0x01UL << HRPWM0_CSG0_ISTAT_STDS_Pos)                  /*!< HRPWM0_CSG0 ISTAT: STDS Mask            */\r
+#define HRPWM0_CSG0_ISTAT_CRSS_Pos            6                                                       /*!< HRPWM0_CSG0 ISTAT: CRSS Position        */\r
+#define HRPWM0_CSG0_ISTAT_CRSS_Msk            (0x01UL << HRPWM0_CSG0_ISTAT_CRSS_Pos)                  /*!< HRPWM0_CSG0 ISTAT: CRSS Mask            */\r
+#define HRPWM0_CSG0_ISTAT_CFSS_Pos            7                                                       /*!< HRPWM0_CSG0 ISTAT: CFSS Position        */\r
+#define HRPWM0_CSG0_ISTAT_CFSS_Msk            (0x01UL << HRPWM0_CSG0_ISTAT_CFSS_Pos)                  /*!< HRPWM0_CSG0 ISTAT: CFSS Mask            */\r
+#define HRPWM0_CSG0_ISTAT_CSES_Pos            8                                                       /*!< HRPWM0_CSG0 ISTAT: CSES Position        */\r
+#define HRPWM0_CSG0_ISTAT_CSES_Msk            (0x01UL << HRPWM0_CSG0_ISTAT_CSES_Pos)                  /*!< HRPWM0_CSG0 ISTAT: CSES Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_CSG1' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_CSG1_DCI  ------------------------------ */\r
+#define HRPWM0_CSG1_DCI_SVIS_Pos              0                                                       /*!< HRPWM0_CSG1 DCI: SVIS Position          */\r
+#define HRPWM0_CSG1_DCI_SVIS_Msk              (0x0fUL << HRPWM0_CSG1_DCI_SVIS_Pos)                    /*!< HRPWM0_CSG1 DCI: SVIS Mask              */\r
+#define HRPWM0_CSG1_DCI_STRIS_Pos             4                                                       /*!< HRPWM0_CSG1 DCI: STRIS Position         */\r
+#define HRPWM0_CSG1_DCI_STRIS_Msk             (0x0fUL << HRPWM0_CSG1_DCI_STRIS_Pos)                   /*!< HRPWM0_CSG1 DCI: STRIS Mask             */\r
+#define HRPWM0_CSG1_DCI_STPIS_Pos             8                                                       /*!< HRPWM0_CSG1 DCI: STPIS Position         */\r
+#define HRPWM0_CSG1_DCI_STPIS_Msk             (0x0fUL << HRPWM0_CSG1_DCI_STPIS_Pos)                   /*!< HRPWM0_CSG1 DCI: STPIS Mask             */\r
+#define HRPWM0_CSG1_DCI_TRGIS_Pos             12                                                      /*!< HRPWM0_CSG1 DCI: TRGIS Position         */\r
+#define HRPWM0_CSG1_DCI_TRGIS_Msk             (0x0fUL << HRPWM0_CSG1_DCI_TRGIS_Pos)                   /*!< HRPWM0_CSG1 DCI: TRGIS Mask             */\r
+#define HRPWM0_CSG1_DCI_STIS_Pos              16                                                      /*!< HRPWM0_CSG1 DCI: STIS Position          */\r
+#define HRPWM0_CSG1_DCI_STIS_Msk              (0x0fUL << HRPWM0_CSG1_DCI_STIS_Pos)                    /*!< HRPWM0_CSG1 DCI: STIS Mask              */\r
+#define HRPWM0_CSG1_DCI_SCS_Pos               20                                                      /*!< HRPWM0_CSG1 DCI: SCS Position           */\r
+#define HRPWM0_CSG1_DCI_SCS_Msk               (0x03UL << HRPWM0_CSG1_DCI_SCS_Pos)                     /*!< HRPWM0_CSG1 DCI: SCS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_IES  ------------------------------ */\r
+#define HRPWM0_CSG1_IES_SVLS_Pos              0                                                       /*!< HRPWM0_CSG1 IES: SVLS Position          */\r
+#define HRPWM0_CSG1_IES_SVLS_Msk              (0x03UL << HRPWM0_CSG1_IES_SVLS_Pos)                    /*!< HRPWM0_CSG1 IES: SVLS Mask              */\r
+#define HRPWM0_CSG1_IES_STRES_Pos             2                                                       /*!< HRPWM0_CSG1 IES: STRES Position         */\r
+#define HRPWM0_CSG1_IES_STRES_Msk             (0x03UL << HRPWM0_CSG1_IES_STRES_Pos)                   /*!< HRPWM0_CSG1 IES: STRES Mask             */\r
+#define HRPWM0_CSG1_IES_STPES_Pos             4                                                       /*!< HRPWM0_CSG1 IES: STPES Position         */\r
+#define HRPWM0_CSG1_IES_STPES_Msk             (0x03UL << HRPWM0_CSG1_IES_STPES_Pos)                   /*!< HRPWM0_CSG1 IES: STPES Mask             */\r
+#define HRPWM0_CSG1_IES_TRGES_Pos             6                                                       /*!< HRPWM0_CSG1 IES: TRGES Position         */\r
+#define HRPWM0_CSG1_IES_TRGES_Msk             (0x03UL << HRPWM0_CSG1_IES_TRGES_Pos)                   /*!< HRPWM0_CSG1 IES: TRGES Mask             */\r
+#define HRPWM0_CSG1_IES_STES_Pos              8                                                       /*!< HRPWM0_CSG1 IES: STES Position          */\r
+#define HRPWM0_CSG1_IES_STES_Msk              (0x03UL << HRPWM0_CSG1_IES_STES_Pos)                    /*!< HRPWM0_CSG1 IES: STES Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SC  ------------------------------- */\r
+#define HRPWM0_CSG1_SC_PSRM_Pos               0                                                       /*!< HRPWM0_CSG1 SC: PSRM Position           */\r
+#define HRPWM0_CSG1_SC_PSRM_Msk               (0x03UL << HRPWM0_CSG1_SC_PSRM_Pos)                     /*!< HRPWM0_CSG1 SC: PSRM Mask               */\r
+#define HRPWM0_CSG1_SC_PSTM_Pos               2                                                       /*!< HRPWM0_CSG1 SC: PSTM Position           */\r
+#define HRPWM0_CSG1_SC_PSTM_Msk               (0x03UL << HRPWM0_CSG1_SC_PSTM_Pos)                     /*!< HRPWM0_CSG1 SC: PSTM Mask               */\r
+#define HRPWM0_CSG1_SC_FPD_Pos                4                                                       /*!< HRPWM0_CSG1 SC: FPD Position            */\r
+#define HRPWM0_CSG1_SC_FPD_Msk                (0x01UL << HRPWM0_CSG1_SC_FPD_Pos)                      /*!< HRPWM0_CSG1 SC: FPD Mask                */\r
+#define HRPWM0_CSG1_SC_PSV_Pos                5                                                       /*!< HRPWM0_CSG1 SC: PSV Position            */\r
+#define HRPWM0_CSG1_SC_PSV_Msk                (0x03UL << HRPWM0_CSG1_SC_PSV_Pos)                      /*!< HRPWM0_CSG1 SC: PSV Mask                */\r
+#define HRPWM0_CSG1_SC_SCM_Pos                8                                                       /*!< HRPWM0_CSG1 SC: SCM Position            */\r
+#define HRPWM0_CSG1_SC_SCM_Msk                (0x03UL << HRPWM0_CSG1_SC_SCM_Pos)                      /*!< HRPWM0_CSG1 SC: SCM Mask                */\r
+#define HRPWM0_CSG1_SC_SSRM_Pos               10                                                      /*!< HRPWM0_CSG1 SC: SSRM Position           */\r
+#define HRPWM0_CSG1_SC_SSRM_Msk               (0x03UL << HRPWM0_CSG1_SC_SSRM_Pos)                     /*!< HRPWM0_CSG1 SC: SSRM Mask               */\r
+#define HRPWM0_CSG1_SC_SSTM_Pos               12                                                      /*!< HRPWM0_CSG1 SC: SSTM Position           */\r
+#define HRPWM0_CSG1_SC_SSTM_Msk               (0x03UL << HRPWM0_CSG1_SC_SSTM_Pos)                     /*!< HRPWM0_CSG1 SC: SSTM Mask               */\r
+#define HRPWM0_CSG1_SC_SVSC_Pos               14                                                      /*!< HRPWM0_CSG1 SC: SVSC Position           */\r
+#define HRPWM0_CSG1_SC_SVSC_Msk               (0x03UL << HRPWM0_CSG1_SC_SVSC_Pos)                     /*!< HRPWM0_CSG1 SC: SVSC Mask               */\r
+#define HRPWM0_CSG1_SC_SWSM_Pos               16                                                      /*!< HRPWM0_CSG1 SC: SWSM Position           */\r
+#define HRPWM0_CSG1_SC_SWSM_Msk               (0x03UL << HRPWM0_CSG1_SC_SWSM_Pos)                     /*!< HRPWM0_CSG1 SC: SWSM Mask               */\r
+#define HRPWM0_CSG1_SC_GCFG_Pos               18                                                      /*!< HRPWM0_CSG1 SC: GCFG Position           */\r
+#define HRPWM0_CSG1_SC_GCFG_Msk               (0x03UL << HRPWM0_CSG1_SC_GCFG_Pos)                     /*!< HRPWM0_CSG1 SC: GCFG Mask               */\r
+#define HRPWM0_CSG1_SC_IST_Pos                20                                                      /*!< HRPWM0_CSG1 SC: IST Position            */\r
+#define HRPWM0_CSG1_SC_IST_Msk                (0x01UL << HRPWM0_CSG1_SC_IST_Pos)                      /*!< HRPWM0_CSG1 SC: IST Mask                */\r
+#define HRPWM0_CSG1_SC_PSE_Pos                21                                                      /*!< HRPWM0_CSG1 SC: PSE Position            */\r
+#define HRPWM0_CSG1_SC_PSE_Msk                (0x01UL << HRPWM0_CSG1_SC_PSE_Pos)                      /*!< HRPWM0_CSG1 SC: PSE Mask                */\r
+#define HRPWM0_CSG1_SC_PSWM_Pos               24                                                      /*!< HRPWM0_CSG1 SC: PSWM Position           */\r
+#define HRPWM0_CSG1_SC_PSWM_Msk               (0x03UL << HRPWM0_CSG1_SC_PSWM_Pos)                     /*!< HRPWM0_CSG1 SC: PSWM Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_PC  ------------------------------- */\r
+#define HRPWM0_CSG1_PC_PSWV_Pos               0                                                       /*!< HRPWM0_CSG1 PC: PSWV Position           */\r
+#define HRPWM0_CSG1_PC_PSWV_Msk               (0x3fUL << HRPWM0_CSG1_PC_PSWV_Pos)                     /*!< HRPWM0_CSG1 PC: PSWV Mask               */\r
+\r
+/* ------------------------------  HRPWM0_CSG1_DSV1  ------------------------------ */\r
+#define HRPWM0_CSG1_DSV1_DSV1_Pos             0                                                       /*!< HRPWM0_CSG1 DSV1: DSV1 Position         */\r
+#define HRPWM0_CSG1_DSV1_DSV1_Msk             (0x000003ffUL << HRPWM0_CSG1_DSV1_DSV1_Pos)             /*!< HRPWM0_CSG1 DSV1: DSV1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG1_DSV2  ------------------------------ */\r
+#define HRPWM0_CSG1_DSV2_DSV2_Pos             0                                                       /*!< HRPWM0_CSG1 DSV2: DSV2 Position         */\r
+#define HRPWM0_CSG1_DSV2_DSV2_Msk             (0x000003ffUL << HRPWM0_CSG1_DSV2_DSV2_Pos)             /*!< HRPWM0_CSG1 DSV2: DSV2 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG1_SDSV1  ----------------------------- */\r
+#define HRPWM0_CSG1_SDSV1_SDSV1_Pos           0                                                       /*!< HRPWM0_CSG1 SDSV1: SDSV1 Position       */\r
+#define HRPWM0_CSG1_SDSV1_SDSV1_Msk           (0x000003ffUL << HRPWM0_CSG1_SDSV1_SDSV1_Pos)           /*!< HRPWM0_CSG1 SDSV1: SDSV1 Mask           */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SPC  ------------------------------ */\r
+#define HRPWM0_CSG1_SPC_SPSWV_Pos             0                                                       /*!< HRPWM0_CSG1 SPC: SPSWV Position         */\r
+#define HRPWM0_CSG1_SPC_SPSWV_Msk             (0x3fUL << HRPWM0_CSG1_SPC_SPSWV_Pos)                   /*!< HRPWM0_CSG1 SPC: SPSWV Mask             */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_CC  ------------------------------- */\r
+#define HRPWM0_CSG1_CC_IBS_Pos                0                                                       /*!< HRPWM0_CSG1 CC: IBS Position            */\r
+#define HRPWM0_CSG1_CC_IBS_Msk                (0x0fUL << HRPWM0_CSG1_CC_IBS_Pos)                      /*!< HRPWM0_CSG1 CC: IBS Mask                */\r
+#define HRPWM0_CSG1_CC_IMCS_Pos               8                                                       /*!< HRPWM0_CSG1 CC: IMCS Position           */\r
+#define HRPWM0_CSG1_CC_IMCS_Msk               (0x01UL << HRPWM0_CSG1_CC_IMCS_Pos)                     /*!< HRPWM0_CSG1 CC: IMCS Mask               */\r
+#define HRPWM0_CSG1_CC_IMCC_Pos               9                                                       /*!< HRPWM0_CSG1 CC: IMCC Position           */\r
+#define HRPWM0_CSG1_CC_IMCC_Msk               (0x03UL << HRPWM0_CSG1_CC_IMCC_Pos)                     /*!< HRPWM0_CSG1 CC: IMCC Mask               */\r
+#define HRPWM0_CSG1_CC_ESE_Pos                11                                                      /*!< HRPWM0_CSG1 CC: ESE Position            */\r
+#define HRPWM0_CSG1_CC_ESE_Msk                (0x01UL << HRPWM0_CSG1_CC_ESE_Pos)                      /*!< HRPWM0_CSG1 CC: ESE Mask                */\r
+#define HRPWM0_CSG1_CC_OIE_Pos                12                                                      /*!< HRPWM0_CSG1 CC: OIE Position            */\r
+#define HRPWM0_CSG1_CC_OIE_Msk                (0x01UL << HRPWM0_CSG1_CC_OIE_Pos)                      /*!< HRPWM0_CSG1 CC: OIE Mask                */\r
+#define HRPWM0_CSG1_CC_OSE_Pos                13                                                      /*!< HRPWM0_CSG1 CC: OSE Position            */\r
+#define HRPWM0_CSG1_CC_OSE_Msk                (0x01UL << HRPWM0_CSG1_CC_OSE_Pos)                      /*!< HRPWM0_CSG1 CC: OSE Mask                */\r
+#define HRPWM0_CSG1_CC_BLMC_Pos               14                                                      /*!< HRPWM0_CSG1 CC: BLMC Position           */\r
+#define HRPWM0_CSG1_CC_BLMC_Msk               (0x03UL << HRPWM0_CSG1_CC_BLMC_Pos)                     /*!< HRPWM0_CSG1 CC: BLMC Mask               */\r
+#define HRPWM0_CSG1_CC_EBE_Pos                16                                                      /*!< HRPWM0_CSG1 CC: EBE Position            */\r
+#define HRPWM0_CSG1_CC_EBE_Msk                (0x01UL << HRPWM0_CSG1_CC_EBE_Pos)                      /*!< HRPWM0_CSG1 CC: EBE Mask                */\r
+#define HRPWM0_CSG1_CC_COFE_Pos               17                                                      /*!< HRPWM0_CSG1 CC: COFE Position           */\r
+#define HRPWM0_CSG1_CC_COFE_Msk               (0x01UL << HRPWM0_CSG1_CC_COFE_Pos)                     /*!< HRPWM0_CSG1 CC: COFE Mask               */\r
+#define HRPWM0_CSG1_CC_COFM_Pos               18                                                      /*!< HRPWM0_CSG1 CC: COFM Position           */\r
+#define HRPWM0_CSG1_CC_COFM_Msk               (0x0fUL << HRPWM0_CSG1_CC_COFM_Pos)                     /*!< HRPWM0_CSG1 CC: COFM Mask               */\r
+#define HRPWM0_CSG1_CC_COFC_Pos               24                                                      /*!< HRPWM0_CSG1 CC: COFC Position           */\r
+#define HRPWM0_CSG1_CC_COFC_Msk               (0x03UL << HRPWM0_CSG1_CC_COFC_Pos)                     /*!< HRPWM0_CSG1 CC: COFC Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_PLC  ------------------------------ */\r
+#define HRPWM0_CSG1_PLC_IPLS_Pos              0                                                       /*!< HRPWM0_CSG1 PLC: IPLS Position          */\r
+#define HRPWM0_CSG1_PLC_IPLS_Msk              (0x0fUL << HRPWM0_CSG1_PLC_IPLS_Pos)                    /*!< HRPWM0_CSG1 PLC: IPLS Mask              */\r
+#define HRPWM0_CSG1_PLC_PLCL_Pos              8                                                       /*!< HRPWM0_CSG1 PLC: PLCL Position          */\r
+#define HRPWM0_CSG1_PLC_PLCL_Msk              (0x03UL << HRPWM0_CSG1_PLC_PLCL_Pos)                    /*!< HRPWM0_CSG1 PLC: PLCL Mask              */\r
+#define HRPWM0_CSG1_PLC_PSL_Pos               10                                                      /*!< HRPWM0_CSG1 PLC: PSL Position           */\r
+#define HRPWM0_CSG1_PLC_PSL_Msk               (0x01UL << HRPWM0_CSG1_PLC_PSL_Pos)                     /*!< HRPWM0_CSG1 PLC: PSL Mask               */\r
+#define HRPWM0_CSG1_PLC_PLSW_Pos              11                                                      /*!< HRPWM0_CSG1 PLC: PLSW Position          */\r
+#define HRPWM0_CSG1_PLC_PLSW_Msk              (0x01UL << HRPWM0_CSG1_PLC_PLSW_Pos)                    /*!< HRPWM0_CSG1 PLC: PLSW Mask              */\r
+#define HRPWM0_CSG1_PLC_PLEC_Pos              12                                                      /*!< HRPWM0_CSG1 PLC: PLEC Position          */\r
+#define HRPWM0_CSG1_PLC_PLEC_Msk              (0x03UL << HRPWM0_CSG1_PLC_PLEC_Pos)                    /*!< HRPWM0_CSG1 PLC: PLEC Mask              */\r
+#define HRPWM0_CSG1_PLC_PLXC_Pos              14                                                      /*!< HRPWM0_CSG1 PLC: PLXC Position          */\r
+#define HRPWM0_CSG1_PLC_PLXC_Msk              (0x03UL << HRPWM0_CSG1_PLC_PLXC_Pos)                    /*!< HRPWM0_CSG1 PLC: PLXC Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_BLV  ------------------------------ */\r
+#define HRPWM0_CSG1_BLV_BLV_Pos               0                                                       /*!< HRPWM0_CSG1 BLV: BLV Position           */\r
+#define HRPWM0_CSG1_BLV_BLV_Msk               (0x000000ffUL << HRPWM0_CSG1_BLV_BLV_Pos)               /*!< HRPWM0_CSG1 BLV: BLV Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SRE  ------------------------------ */\r
+#define HRPWM0_CSG1_SRE_VLS1E_Pos             0                                                       /*!< HRPWM0_CSG1 SRE: VLS1E Position         */\r
+#define HRPWM0_CSG1_SRE_VLS1E_Msk             (0x01UL << HRPWM0_CSG1_SRE_VLS1E_Pos)                   /*!< HRPWM0_CSG1 SRE: VLS1E Mask             */\r
+#define HRPWM0_CSG1_SRE_VLS2E_Pos             1                                                       /*!< HRPWM0_CSG1 SRE: VLS2E Position         */\r
+#define HRPWM0_CSG1_SRE_VLS2E_Msk             (0x01UL << HRPWM0_CSG1_SRE_VLS2E_Pos)                   /*!< HRPWM0_CSG1 SRE: VLS2E Mask             */\r
+#define HRPWM0_CSG1_SRE_TRGSE_Pos             2                                                       /*!< HRPWM0_CSG1 SRE: TRGSE Position         */\r
+#define HRPWM0_CSG1_SRE_TRGSE_Msk             (0x01UL << HRPWM0_CSG1_SRE_TRGSE_Pos)                   /*!< HRPWM0_CSG1 SRE: TRGSE Mask             */\r
+#define HRPWM0_CSG1_SRE_STRSE_Pos             3                                                       /*!< HRPWM0_CSG1 SRE: STRSE Position         */\r
+#define HRPWM0_CSG1_SRE_STRSE_Msk             (0x01UL << HRPWM0_CSG1_SRE_STRSE_Pos)                   /*!< HRPWM0_CSG1 SRE: STRSE Mask             */\r
+#define HRPWM0_CSG1_SRE_STPSE_Pos             4                                                       /*!< HRPWM0_CSG1 SRE: STPSE Position         */\r
+#define HRPWM0_CSG1_SRE_STPSE_Msk             (0x01UL << HRPWM0_CSG1_SRE_STPSE_Pos)                   /*!< HRPWM0_CSG1 SRE: STPSE Mask             */\r
+#define HRPWM0_CSG1_SRE_STDE_Pos              5                                                       /*!< HRPWM0_CSG1 SRE: STDE Position          */\r
+#define HRPWM0_CSG1_SRE_STDE_Msk              (0x01UL << HRPWM0_CSG1_SRE_STDE_Pos)                    /*!< HRPWM0_CSG1 SRE: STDE Mask              */\r
+#define HRPWM0_CSG1_SRE_CRSE_Pos              6                                                       /*!< HRPWM0_CSG1 SRE: CRSE Position          */\r
+#define HRPWM0_CSG1_SRE_CRSE_Msk              (0x01UL << HRPWM0_CSG1_SRE_CRSE_Pos)                    /*!< HRPWM0_CSG1 SRE: CRSE Mask              */\r
+#define HRPWM0_CSG1_SRE_CFSE_Pos              7                                                       /*!< HRPWM0_CSG1 SRE: CFSE Position          */\r
+#define HRPWM0_CSG1_SRE_CFSE_Msk              (0x01UL << HRPWM0_CSG1_SRE_CFSE_Pos)                    /*!< HRPWM0_CSG1 SRE: CFSE Mask              */\r
+#define HRPWM0_CSG1_SRE_CSEE_Pos              8                                                       /*!< HRPWM0_CSG1 SRE: CSEE Position          */\r
+#define HRPWM0_CSG1_SRE_CSEE_Msk              (0x01UL << HRPWM0_CSG1_SRE_CSEE_Pos)                    /*!< HRPWM0_CSG1 SRE: CSEE Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SRS  ------------------------------ */\r
+#define HRPWM0_CSG1_SRS_VLS1S_Pos             0                                                       /*!< HRPWM0_CSG1 SRS: VLS1S Position         */\r
+#define HRPWM0_CSG1_SRS_VLS1S_Msk             (0x03UL << HRPWM0_CSG1_SRS_VLS1S_Pos)                   /*!< HRPWM0_CSG1 SRS: VLS1S Mask             */\r
+#define HRPWM0_CSG1_SRS_VLS2S_Pos             2                                                       /*!< HRPWM0_CSG1 SRS: VLS2S Position         */\r
+#define HRPWM0_CSG1_SRS_VLS2S_Msk             (0x03UL << HRPWM0_CSG1_SRS_VLS2S_Pos)                   /*!< HRPWM0_CSG1 SRS: VLS2S Mask             */\r
+#define HRPWM0_CSG1_SRS_TRLS_Pos              4                                                       /*!< HRPWM0_CSG1 SRS: TRLS Position          */\r
+#define HRPWM0_CSG1_SRS_TRLS_Msk              (0x03UL << HRPWM0_CSG1_SRS_TRLS_Pos)                    /*!< HRPWM0_CSG1 SRS: TRLS Mask              */\r
+#define HRPWM0_CSG1_SRS_SSLS_Pos              6                                                       /*!< HRPWM0_CSG1 SRS: SSLS Position          */\r
+#define HRPWM0_CSG1_SRS_SSLS_Msk              (0x03UL << HRPWM0_CSG1_SRS_SSLS_Pos)                    /*!< HRPWM0_CSG1 SRS: SSLS Mask              */\r
+#define HRPWM0_CSG1_SRS_STLS_Pos              8                                                       /*!< HRPWM0_CSG1 SRS: STLS Position          */\r
+#define HRPWM0_CSG1_SRS_STLS_Msk              (0x03UL << HRPWM0_CSG1_SRS_STLS_Pos)                    /*!< HRPWM0_CSG1 SRS: STLS Mask              */\r
+#define HRPWM0_CSG1_SRS_CRFLS_Pos             10                                                      /*!< HRPWM0_CSG1 SRS: CRFLS Position         */\r
+#define HRPWM0_CSG1_SRS_CRFLS_Msk             (0x03UL << HRPWM0_CSG1_SRS_CRFLS_Pos)                   /*!< HRPWM0_CSG1 SRS: CRFLS Mask             */\r
+#define HRPWM0_CSG1_SRS_CSLS_Pos              12                                                      /*!< HRPWM0_CSG1 SRS: CSLS Position          */\r
+#define HRPWM0_CSG1_SRS_CSLS_Msk              (0x03UL << HRPWM0_CSG1_SRS_CSLS_Pos)                    /*!< HRPWM0_CSG1 SRS: CSLS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SWS  ------------------------------ */\r
+#define HRPWM0_CSG1_SWS_SVLS1_Pos             0                                                       /*!< HRPWM0_CSG1 SWS: SVLS1 Position         */\r
+#define HRPWM0_CSG1_SWS_SVLS1_Msk             (0x01UL << HRPWM0_CSG1_SWS_SVLS1_Pos)                   /*!< HRPWM0_CSG1 SWS: SVLS1 Mask             */\r
+#define HRPWM0_CSG1_SWS_SVLS2_Pos             1                                                       /*!< HRPWM0_CSG1 SWS: SVLS2 Position         */\r
+#define HRPWM0_CSG1_SWS_SVLS2_Msk             (0x01UL << HRPWM0_CSG1_SWS_SVLS2_Pos)                   /*!< HRPWM0_CSG1 SWS: SVLS2 Mask             */\r
+#define HRPWM0_CSG1_SWS_STRGS_Pos             2                                                       /*!< HRPWM0_CSG1 SWS: STRGS Position         */\r
+#define HRPWM0_CSG1_SWS_STRGS_Msk             (0x01UL << HRPWM0_CSG1_SWS_STRGS_Pos)                   /*!< HRPWM0_CSG1 SWS: STRGS Mask             */\r
+#define HRPWM0_CSG1_SWS_SSTRS_Pos             3                                                       /*!< HRPWM0_CSG1 SWS: SSTRS Position         */\r
+#define HRPWM0_CSG1_SWS_SSTRS_Msk             (0x01UL << HRPWM0_CSG1_SWS_SSTRS_Pos)                   /*!< HRPWM0_CSG1 SWS: SSTRS Mask             */\r
+#define HRPWM0_CSG1_SWS_SSTPS_Pos             4                                                       /*!< HRPWM0_CSG1 SWS: SSTPS Position         */\r
+#define HRPWM0_CSG1_SWS_SSTPS_Msk             (0x01UL << HRPWM0_CSG1_SWS_SSTPS_Pos)                   /*!< HRPWM0_CSG1 SWS: SSTPS Mask             */\r
+#define HRPWM0_CSG1_SWS_SSTD_Pos              5                                                       /*!< HRPWM0_CSG1 SWS: SSTD Position          */\r
+#define HRPWM0_CSG1_SWS_SSTD_Msk              (0x01UL << HRPWM0_CSG1_SWS_SSTD_Pos)                    /*!< HRPWM0_CSG1 SWS: SSTD Mask              */\r
+#define HRPWM0_CSG1_SWS_SCRS_Pos              6                                                       /*!< HRPWM0_CSG1 SWS: SCRS Position          */\r
+#define HRPWM0_CSG1_SWS_SCRS_Msk              (0x01UL << HRPWM0_CSG1_SWS_SCRS_Pos)                    /*!< HRPWM0_CSG1 SWS: SCRS Mask              */\r
+#define HRPWM0_CSG1_SWS_SCFS_Pos              7                                                       /*!< HRPWM0_CSG1 SWS: SCFS Position          */\r
+#define HRPWM0_CSG1_SWS_SCFS_Msk              (0x01UL << HRPWM0_CSG1_SWS_SCFS_Pos)                    /*!< HRPWM0_CSG1 SWS: SCFS Mask              */\r
+#define HRPWM0_CSG1_SWS_SCSS_Pos              8                                                       /*!< HRPWM0_CSG1 SWS: SCSS Position          */\r
+#define HRPWM0_CSG1_SWS_SCSS_Msk              (0x01UL << HRPWM0_CSG1_SWS_SCSS_Pos)                    /*!< HRPWM0_CSG1 SWS: SCSS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG1_SWC  ------------------------------ */\r
+#define HRPWM0_CSG1_SWC_CVLS1_Pos             0                                                       /*!< HRPWM0_CSG1 SWC: CVLS1 Position         */\r
+#define HRPWM0_CSG1_SWC_CVLS1_Msk             (0x01UL << HRPWM0_CSG1_SWC_CVLS1_Pos)                   /*!< HRPWM0_CSG1 SWC: CVLS1 Mask             */\r
+#define HRPWM0_CSG1_SWC_CVLS2_Pos             1                                                       /*!< HRPWM0_CSG1 SWC: CVLS2 Position         */\r
+#define HRPWM0_CSG1_SWC_CVLS2_Msk             (0x01UL << HRPWM0_CSG1_SWC_CVLS2_Pos)                   /*!< HRPWM0_CSG1 SWC: CVLS2 Mask             */\r
+#define HRPWM0_CSG1_SWC_CTRGS_Pos             2                                                       /*!< HRPWM0_CSG1 SWC: CTRGS Position         */\r
+#define HRPWM0_CSG1_SWC_CTRGS_Msk             (0x01UL << HRPWM0_CSG1_SWC_CTRGS_Pos)                   /*!< HRPWM0_CSG1 SWC: CTRGS Mask             */\r
+#define HRPWM0_CSG1_SWC_CSTRS_Pos             3                                                       /*!< HRPWM0_CSG1 SWC: CSTRS Position         */\r
+#define HRPWM0_CSG1_SWC_CSTRS_Msk             (0x01UL << HRPWM0_CSG1_SWC_CSTRS_Pos)                   /*!< HRPWM0_CSG1 SWC: CSTRS Mask             */\r
+#define HRPWM0_CSG1_SWC_CSTPS_Pos             4                                                       /*!< HRPWM0_CSG1 SWC: CSTPS Position         */\r
+#define HRPWM0_CSG1_SWC_CSTPS_Msk             (0x01UL << HRPWM0_CSG1_SWC_CSTPS_Pos)                   /*!< HRPWM0_CSG1 SWC: CSTPS Mask             */\r
+#define HRPWM0_CSG1_SWC_CSTD_Pos              5                                                       /*!< HRPWM0_CSG1 SWC: CSTD Position          */\r
+#define HRPWM0_CSG1_SWC_CSTD_Msk              (0x01UL << HRPWM0_CSG1_SWC_CSTD_Pos)                    /*!< HRPWM0_CSG1 SWC: CSTD Mask              */\r
+#define HRPWM0_CSG1_SWC_CCRS_Pos              6                                                       /*!< HRPWM0_CSG1 SWC: CCRS Position          */\r
+#define HRPWM0_CSG1_SWC_CCRS_Msk              (0x01UL << HRPWM0_CSG1_SWC_CCRS_Pos)                    /*!< HRPWM0_CSG1 SWC: CCRS Mask              */\r
+#define HRPWM0_CSG1_SWC_CCFS_Pos              7                                                       /*!< HRPWM0_CSG1 SWC: CCFS Position          */\r
+#define HRPWM0_CSG1_SWC_CCFS_Msk              (0x01UL << HRPWM0_CSG1_SWC_CCFS_Pos)                    /*!< HRPWM0_CSG1 SWC: CCFS Mask              */\r
+#define HRPWM0_CSG1_SWC_CCSS_Pos              8                                                       /*!< HRPWM0_CSG1 SWC: CCSS Position          */\r
+#define HRPWM0_CSG1_SWC_CCSS_Msk              (0x01UL << HRPWM0_CSG1_SWC_CCSS_Pos)                    /*!< HRPWM0_CSG1 SWC: CCSS Mask              */\r
+\r
+/* ------------------------------  HRPWM0_CSG1_ISTAT  ----------------------------- */\r
+#define HRPWM0_CSG1_ISTAT_VLS1S_Pos           0                                                       /*!< HRPWM0_CSG1 ISTAT: VLS1S Position       */\r
+#define HRPWM0_CSG1_ISTAT_VLS1S_Msk           (0x01UL << HRPWM0_CSG1_ISTAT_VLS1S_Pos)                 /*!< HRPWM0_CSG1 ISTAT: VLS1S Mask           */\r
+#define HRPWM0_CSG1_ISTAT_VLS2S_Pos           1                                                       /*!< HRPWM0_CSG1 ISTAT: VLS2S Position       */\r
+#define HRPWM0_CSG1_ISTAT_VLS2S_Msk           (0x01UL << HRPWM0_CSG1_ISTAT_VLS2S_Pos)                 /*!< HRPWM0_CSG1 ISTAT: VLS2S Mask           */\r
+#define HRPWM0_CSG1_ISTAT_TRGSS_Pos           2                                                       /*!< HRPWM0_CSG1 ISTAT: TRGSS Position       */\r
+#define HRPWM0_CSG1_ISTAT_TRGSS_Msk           (0x01UL << HRPWM0_CSG1_ISTAT_TRGSS_Pos)                 /*!< HRPWM0_CSG1 ISTAT: TRGSS Mask           */\r
+#define HRPWM0_CSG1_ISTAT_STRSS_Pos           3                                                       /*!< HRPWM0_CSG1 ISTAT: STRSS Position       */\r
+#define HRPWM0_CSG1_ISTAT_STRSS_Msk           (0x01UL << HRPWM0_CSG1_ISTAT_STRSS_Pos)                 /*!< HRPWM0_CSG1 ISTAT: STRSS Mask           */\r
+#define HRPWM0_CSG1_ISTAT_STPSS_Pos           4                                                       /*!< HRPWM0_CSG1 ISTAT: STPSS Position       */\r
+#define HRPWM0_CSG1_ISTAT_STPSS_Msk           (0x01UL << HRPWM0_CSG1_ISTAT_STPSS_Pos)                 /*!< HRPWM0_CSG1 ISTAT: STPSS Mask           */\r
+#define HRPWM0_CSG1_ISTAT_STDS_Pos            5                                                       /*!< HRPWM0_CSG1 ISTAT: STDS Position        */\r
+#define HRPWM0_CSG1_ISTAT_STDS_Msk            (0x01UL << HRPWM0_CSG1_ISTAT_STDS_Pos)                  /*!< HRPWM0_CSG1 ISTAT: STDS Mask            */\r
+#define HRPWM0_CSG1_ISTAT_CRSS_Pos            6                                                       /*!< HRPWM0_CSG1 ISTAT: CRSS Position        */\r
+#define HRPWM0_CSG1_ISTAT_CRSS_Msk            (0x01UL << HRPWM0_CSG1_ISTAT_CRSS_Pos)                  /*!< HRPWM0_CSG1 ISTAT: CRSS Mask            */\r
+#define HRPWM0_CSG1_ISTAT_CFSS_Pos            7                                                       /*!< HRPWM0_CSG1 ISTAT: CFSS Position        */\r
+#define HRPWM0_CSG1_ISTAT_CFSS_Msk            (0x01UL << HRPWM0_CSG1_ISTAT_CFSS_Pos)                  /*!< HRPWM0_CSG1 ISTAT: CFSS Mask            */\r
+#define HRPWM0_CSG1_ISTAT_CSES_Pos            8                                                       /*!< HRPWM0_CSG1 ISTAT: CSES Position        */\r
+#define HRPWM0_CSG1_ISTAT_CSES_Msk            (0x01UL << HRPWM0_CSG1_ISTAT_CSES_Pos)                  /*!< HRPWM0_CSG1 ISTAT: CSES Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_CSG2' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_CSG2_DCI  ------------------------------ */\r
+#define HRPWM0_CSG2_DCI_SVIS_Pos              0                                                       /*!< HRPWM0_CSG2 DCI: SVIS Position          */\r
+#define HRPWM0_CSG2_DCI_SVIS_Msk              (0x0fUL << HRPWM0_CSG2_DCI_SVIS_Pos)                    /*!< HRPWM0_CSG2 DCI: SVIS Mask              */\r
+#define HRPWM0_CSG2_DCI_STRIS_Pos             4                                                       /*!< HRPWM0_CSG2 DCI: STRIS Position         */\r
+#define HRPWM0_CSG2_DCI_STRIS_Msk             (0x0fUL << HRPWM0_CSG2_DCI_STRIS_Pos)                   /*!< HRPWM0_CSG2 DCI: STRIS Mask             */\r
+#define HRPWM0_CSG2_DCI_STPIS_Pos             8                                                       /*!< HRPWM0_CSG2 DCI: STPIS Position         */\r
+#define HRPWM0_CSG2_DCI_STPIS_Msk             (0x0fUL << HRPWM0_CSG2_DCI_STPIS_Pos)                   /*!< HRPWM0_CSG2 DCI: STPIS Mask             */\r
+#define HRPWM0_CSG2_DCI_TRGIS_Pos             12                                                      /*!< HRPWM0_CSG2 DCI: TRGIS Position         */\r
+#define HRPWM0_CSG2_DCI_TRGIS_Msk             (0x0fUL << HRPWM0_CSG2_DCI_TRGIS_Pos)                   /*!< HRPWM0_CSG2 DCI: TRGIS Mask             */\r
+#define HRPWM0_CSG2_DCI_STIS_Pos              16                                                      /*!< HRPWM0_CSG2 DCI: STIS Position          */\r
+#define HRPWM0_CSG2_DCI_STIS_Msk              (0x0fUL << HRPWM0_CSG2_DCI_STIS_Pos)                    /*!< HRPWM0_CSG2 DCI: STIS Mask              */\r
+#define HRPWM0_CSG2_DCI_SCS_Pos               20                                                      /*!< HRPWM0_CSG2 DCI: SCS Position           */\r
+#define HRPWM0_CSG2_DCI_SCS_Msk               (0x03UL << HRPWM0_CSG2_DCI_SCS_Pos)                     /*!< HRPWM0_CSG2 DCI: SCS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_IES  ------------------------------ */\r
+#define HRPWM0_CSG2_IES_SVLS_Pos              0                                                       /*!< HRPWM0_CSG2 IES: SVLS Position          */\r
+#define HRPWM0_CSG2_IES_SVLS_Msk              (0x03UL << HRPWM0_CSG2_IES_SVLS_Pos)                    /*!< HRPWM0_CSG2 IES: SVLS Mask              */\r
+#define HRPWM0_CSG2_IES_STRES_Pos             2                                                       /*!< HRPWM0_CSG2 IES: STRES Position         */\r
+#define HRPWM0_CSG2_IES_STRES_Msk             (0x03UL << HRPWM0_CSG2_IES_STRES_Pos)                   /*!< HRPWM0_CSG2 IES: STRES Mask             */\r
+#define HRPWM0_CSG2_IES_STPES_Pos             4                                                       /*!< HRPWM0_CSG2 IES: STPES Position         */\r
+#define HRPWM0_CSG2_IES_STPES_Msk             (0x03UL << HRPWM0_CSG2_IES_STPES_Pos)                   /*!< HRPWM0_CSG2 IES: STPES Mask             */\r
+#define HRPWM0_CSG2_IES_TRGES_Pos             6                                                       /*!< HRPWM0_CSG2 IES: TRGES Position         */\r
+#define HRPWM0_CSG2_IES_TRGES_Msk             (0x03UL << HRPWM0_CSG2_IES_TRGES_Pos)                   /*!< HRPWM0_CSG2 IES: TRGES Mask             */\r
+#define HRPWM0_CSG2_IES_STES_Pos              8                                                       /*!< HRPWM0_CSG2 IES: STES Position          */\r
+#define HRPWM0_CSG2_IES_STES_Msk              (0x03UL << HRPWM0_CSG2_IES_STES_Pos)                    /*!< HRPWM0_CSG2 IES: STES Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SC  ------------------------------- */\r
+#define HRPWM0_CSG2_SC_PSRM_Pos               0                                                       /*!< HRPWM0_CSG2 SC: PSRM Position           */\r
+#define HRPWM0_CSG2_SC_PSRM_Msk               (0x03UL << HRPWM0_CSG2_SC_PSRM_Pos)                     /*!< HRPWM0_CSG2 SC: PSRM Mask               */\r
+#define HRPWM0_CSG2_SC_PSTM_Pos               2                                                       /*!< HRPWM0_CSG2 SC: PSTM Position           */\r
+#define HRPWM0_CSG2_SC_PSTM_Msk               (0x03UL << HRPWM0_CSG2_SC_PSTM_Pos)                     /*!< HRPWM0_CSG2 SC: PSTM Mask               */\r
+#define HRPWM0_CSG2_SC_FPD_Pos                4                                                       /*!< HRPWM0_CSG2 SC: FPD Position            */\r
+#define HRPWM0_CSG2_SC_FPD_Msk                (0x01UL << HRPWM0_CSG2_SC_FPD_Pos)                      /*!< HRPWM0_CSG2 SC: FPD Mask                */\r
+#define HRPWM0_CSG2_SC_PSV_Pos                5                                                       /*!< HRPWM0_CSG2 SC: PSV Position            */\r
+#define HRPWM0_CSG2_SC_PSV_Msk                (0x03UL << HRPWM0_CSG2_SC_PSV_Pos)                      /*!< HRPWM0_CSG2 SC: PSV Mask                */\r
+#define HRPWM0_CSG2_SC_SCM_Pos                8                                                       /*!< HRPWM0_CSG2 SC: SCM Position            */\r
+#define HRPWM0_CSG2_SC_SCM_Msk                (0x03UL << HRPWM0_CSG2_SC_SCM_Pos)                      /*!< HRPWM0_CSG2 SC: SCM Mask                */\r
+#define HRPWM0_CSG2_SC_SSRM_Pos               10                                                      /*!< HRPWM0_CSG2 SC: SSRM Position           */\r
+#define HRPWM0_CSG2_SC_SSRM_Msk               (0x03UL << HRPWM0_CSG2_SC_SSRM_Pos)                     /*!< HRPWM0_CSG2 SC: SSRM Mask               */\r
+#define HRPWM0_CSG2_SC_SSTM_Pos               12                                                      /*!< HRPWM0_CSG2 SC: SSTM Position           */\r
+#define HRPWM0_CSG2_SC_SSTM_Msk               (0x03UL << HRPWM0_CSG2_SC_SSTM_Pos)                     /*!< HRPWM0_CSG2 SC: SSTM Mask               */\r
+#define HRPWM0_CSG2_SC_SVSC_Pos               14                                                      /*!< HRPWM0_CSG2 SC: SVSC Position           */\r
+#define HRPWM0_CSG2_SC_SVSC_Msk               (0x03UL << HRPWM0_CSG2_SC_SVSC_Pos)                     /*!< HRPWM0_CSG2 SC: SVSC Mask               */\r
+#define HRPWM0_CSG2_SC_SWSM_Pos               16                                                      /*!< HRPWM0_CSG2 SC: SWSM Position           */\r
+#define HRPWM0_CSG2_SC_SWSM_Msk               (0x03UL << HRPWM0_CSG2_SC_SWSM_Pos)                     /*!< HRPWM0_CSG2 SC: SWSM Mask               */\r
+#define HRPWM0_CSG2_SC_GCFG_Pos               18                                                      /*!< HRPWM0_CSG2 SC: GCFG Position           */\r
+#define HRPWM0_CSG2_SC_GCFG_Msk               (0x03UL << HRPWM0_CSG2_SC_GCFG_Pos)                     /*!< HRPWM0_CSG2 SC: GCFG Mask               */\r
+#define HRPWM0_CSG2_SC_IST_Pos                20                                                      /*!< HRPWM0_CSG2 SC: IST Position            */\r
+#define HRPWM0_CSG2_SC_IST_Msk                (0x01UL << HRPWM0_CSG2_SC_IST_Pos)                      /*!< HRPWM0_CSG2 SC: IST Mask                */\r
+#define HRPWM0_CSG2_SC_PSE_Pos                21                                                      /*!< HRPWM0_CSG2 SC: PSE Position            */\r
+#define HRPWM0_CSG2_SC_PSE_Msk                (0x01UL << HRPWM0_CSG2_SC_PSE_Pos)                      /*!< HRPWM0_CSG2 SC: PSE Mask                */\r
+#define HRPWM0_CSG2_SC_PSWM_Pos               24                                                      /*!< HRPWM0_CSG2 SC: PSWM Position           */\r
+#define HRPWM0_CSG2_SC_PSWM_Msk               (0x03UL << HRPWM0_CSG2_SC_PSWM_Pos)                     /*!< HRPWM0_CSG2 SC: PSWM Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_PC  ------------------------------- */\r
+#define HRPWM0_CSG2_PC_PSWV_Pos               0                                                       /*!< HRPWM0_CSG2 PC: PSWV Position           */\r
+#define HRPWM0_CSG2_PC_PSWV_Msk               (0x3fUL << HRPWM0_CSG2_PC_PSWV_Pos)                     /*!< HRPWM0_CSG2 PC: PSWV Mask               */\r
+\r
+/* ------------------------------  HRPWM0_CSG2_DSV1  ------------------------------ */\r
+#define HRPWM0_CSG2_DSV1_DSV1_Pos             0                                                       /*!< HRPWM0_CSG2 DSV1: DSV1 Position         */\r
+#define HRPWM0_CSG2_DSV1_DSV1_Msk             (0x000003ffUL << HRPWM0_CSG2_DSV1_DSV1_Pos)             /*!< HRPWM0_CSG2 DSV1: DSV1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG2_DSV2  ------------------------------ */\r
+#define HRPWM0_CSG2_DSV2_DSV2_Pos             0                                                       /*!< HRPWM0_CSG2 DSV2: DSV2 Position         */\r
+#define HRPWM0_CSG2_DSV2_DSV2_Msk             (0x000003ffUL << HRPWM0_CSG2_DSV2_DSV2_Pos)             /*!< HRPWM0_CSG2 DSV2: DSV2 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_CSG2_SDSV1  ----------------------------- */\r
+#define HRPWM0_CSG2_SDSV1_SDSV1_Pos           0                                                       /*!< HRPWM0_CSG2 SDSV1: SDSV1 Position       */\r
+#define HRPWM0_CSG2_SDSV1_SDSV1_Msk           (0x000003ffUL << HRPWM0_CSG2_SDSV1_SDSV1_Pos)           /*!< HRPWM0_CSG2 SDSV1: SDSV1 Mask           */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SPC  ------------------------------ */\r
+#define HRPWM0_CSG2_SPC_SPSWV_Pos             0                                                       /*!< HRPWM0_CSG2 SPC: SPSWV Position         */\r
+#define HRPWM0_CSG2_SPC_SPSWV_Msk             (0x3fUL << HRPWM0_CSG2_SPC_SPSWV_Pos)                   /*!< HRPWM0_CSG2 SPC: SPSWV Mask             */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_CC  ------------------------------- */\r
+#define HRPWM0_CSG2_CC_IBS_Pos                0                                                       /*!< HRPWM0_CSG2 CC: IBS Position            */\r
+#define HRPWM0_CSG2_CC_IBS_Msk                (0x0fUL << HRPWM0_CSG2_CC_IBS_Pos)                      /*!< HRPWM0_CSG2 CC: IBS Mask                */\r
+#define HRPWM0_CSG2_CC_IMCS_Pos               8                                                       /*!< HRPWM0_CSG2 CC: IMCS Position           */\r
+#define HRPWM0_CSG2_CC_IMCS_Msk               (0x01UL << HRPWM0_CSG2_CC_IMCS_Pos)                     /*!< HRPWM0_CSG2 CC: IMCS Mask               */\r
+#define HRPWM0_CSG2_CC_IMCC_Pos               9                                                       /*!< HRPWM0_CSG2 CC: IMCC Position           */\r
+#define HRPWM0_CSG2_CC_IMCC_Msk               (0x03UL << HRPWM0_CSG2_CC_IMCC_Pos)                     /*!< HRPWM0_CSG2 CC: IMCC Mask               */\r
+#define HRPWM0_CSG2_CC_ESE_Pos                11                                                      /*!< HRPWM0_CSG2 CC: ESE Position            */\r
+#define HRPWM0_CSG2_CC_ESE_Msk                (0x01UL << HRPWM0_CSG2_CC_ESE_Pos)                      /*!< HRPWM0_CSG2 CC: ESE Mask                */\r
+#define HRPWM0_CSG2_CC_OIE_Pos                12                                                      /*!< HRPWM0_CSG2 CC: OIE Position            */\r
+#define HRPWM0_CSG2_CC_OIE_Msk                (0x01UL << HRPWM0_CSG2_CC_OIE_Pos)                      /*!< HRPWM0_CSG2 CC: OIE Mask                */\r
+#define HRPWM0_CSG2_CC_OSE_Pos                13                                                      /*!< HRPWM0_CSG2 CC: OSE Position            */\r
+#define HRPWM0_CSG2_CC_OSE_Msk                (0x01UL << HRPWM0_CSG2_CC_OSE_Pos)                      /*!< HRPWM0_CSG2 CC: OSE Mask                */\r
+#define HRPWM0_CSG2_CC_BLMC_Pos               14                                                      /*!< HRPWM0_CSG2 CC: BLMC Position           */\r
+#define HRPWM0_CSG2_CC_BLMC_Msk               (0x03UL << HRPWM0_CSG2_CC_BLMC_Pos)                     /*!< HRPWM0_CSG2 CC: BLMC Mask               */\r
+#define HRPWM0_CSG2_CC_EBE_Pos                16                                                      /*!< HRPWM0_CSG2 CC: EBE Position            */\r
+#define HRPWM0_CSG2_CC_EBE_Msk                (0x01UL << HRPWM0_CSG2_CC_EBE_Pos)                      /*!< HRPWM0_CSG2 CC: EBE Mask                */\r
+#define HRPWM0_CSG2_CC_COFE_Pos               17                                                      /*!< HRPWM0_CSG2 CC: COFE Position           */\r
+#define HRPWM0_CSG2_CC_COFE_Msk               (0x01UL << HRPWM0_CSG2_CC_COFE_Pos)                     /*!< HRPWM0_CSG2 CC: COFE Mask               */\r
+#define HRPWM0_CSG2_CC_COFM_Pos               18                                                      /*!< HRPWM0_CSG2 CC: COFM Position           */\r
+#define HRPWM0_CSG2_CC_COFM_Msk               (0x0fUL << HRPWM0_CSG2_CC_COFM_Pos)                     /*!< HRPWM0_CSG2 CC: COFM Mask               */\r
+#define HRPWM0_CSG2_CC_COFC_Pos               24                                                      /*!< HRPWM0_CSG2 CC: COFC Position           */\r
+#define HRPWM0_CSG2_CC_COFC_Msk               (0x03UL << HRPWM0_CSG2_CC_COFC_Pos)                     /*!< HRPWM0_CSG2 CC: COFC Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_PLC  ------------------------------ */\r
+#define HRPWM0_CSG2_PLC_IPLS_Pos              0                                                       /*!< HRPWM0_CSG2 PLC: IPLS Position          */\r
+#define HRPWM0_CSG2_PLC_IPLS_Msk              (0x0fUL << HRPWM0_CSG2_PLC_IPLS_Pos)                    /*!< HRPWM0_CSG2 PLC: IPLS Mask              */\r
+#define HRPWM0_CSG2_PLC_PLCL_Pos              8                                                       /*!< HRPWM0_CSG2 PLC: PLCL Position          */\r
+#define HRPWM0_CSG2_PLC_PLCL_Msk              (0x03UL << HRPWM0_CSG2_PLC_PLCL_Pos)                    /*!< HRPWM0_CSG2 PLC: PLCL Mask              */\r
+#define HRPWM0_CSG2_PLC_PSL_Pos               10                                                      /*!< HRPWM0_CSG2 PLC: PSL Position           */\r
+#define HRPWM0_CSG2_PLC_PSL_Msk               (0x01UL << HRPWM0_CSG2_PLC_PSL_Pos)                     /*!< HRPWM0_CSG2 PLC: PSL Mask               */\r
+#define HRPWM0_CSG2_PLC_PLSW_Pos              11                                                      /*!< HRPWM0_CSG2 PLC: PLSW Position          */\r
+#define HRPWM0_CSG2_PLC_PLSW_Msk              (0x01UL << HRPWM0_CSG2_PLC_PLSW_Pos)                    /*!< HRPWM0_CSG2 PLC: PLSW Mask              */\r
+#define HRPWM0_CSG2_PLC_PLEC_Pos              12                                                      /*!< HRPWM0_CSG2 PLC: PLEC Position          */\r
+#define HRPWM0_CSG2_PLC_PLEC_Msk              (0x03UL << HRPWM0_CSG2_PLC_PLEC_Pos)                    /*!< HRPWM0_CSG2 PLC: PLEC Mask              */\r
+#define HRPWM0_CSG2_PLC_PLXC_Pos              14                                                      /*!< HRPWM0_CSG2 PLC: PLXC Position          */\r
+#define HRPWM0_CSG2_PLC_PLXC_Msk              (0x03UL << HRPWM0_CSG2_PLC_PLXC_Pos)                    /*!< HRPWM0_CSG2 PLC: PLXC Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_BLV  ------------------------------ */\r
+#define HRPWM0_CSG2_BLV_BLV_Pos               0                                                       /*!< HRPWM0_CSG2 BLV: BLV Position           */\r
+#define HRPWM0_CSG2_BLV_BLV_Msk               (0x000000ffUL << HRPWM0_CSG2_BLV_BLV_Pos)               /*!< HRPWM0_CSG2 BLV: BLV Mask               */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SRE  ------------------------------ */\r
+#define HRPWM0_CSG2_SRE_VLS1E_Pos             0                                                       /*!< HRPWM0_CSG2 SRE: VLS1E Position         */\r
+#define HRPWM0_CSG2_SRE_VLS1E_Msk             (0x01UL << HRPWM0_CSG2_SRE_VLS1E_Pos)                   /*!< HRPWM0_CSG2 SRE: VLS1E Mask             */\r
+#define HRPWM0_CSG2_SRE_VLS2E_Pos             1                                                       /*!< HRPWM0_CSG2 SRE: VLS2E Position         */\r
+#define HRPWM0_CSG2_SRE_VLS2E_Msk             (0x01UL << HRPWM0_CSG2_SRE_VLS2E_Pos)                   /*!< HRPWM0_CSG2 SRE: VLS2E Mask             */\r
+#define HRPWM0_CSG2_SRE_TRGSE_Pos             2                                                       /*!< HRPWM0_CSG2 SRE: TRGSE Position         */\r
+#define HRPWM0_CSG2_SRE_TRGSE_Msk             (0x01UL << HRPWM0_CSG2_SRE_TRGSE_Pos)                   /*!< HRPWM0_CSG2 SRE: TRGSE Mask             */\r
+#define HRPWM0_CSG2_SRE_STRSE_Pos             3                                                       /*!< HRPWM0_CSG2 SRE: STRSE Position         */\r
+#define HRPWM0_CSG2_SRE_STRSE_Msk             (0x01UL << HRPWM0_CSG2_SRE_STRSE_Pos)                   /*!< HRPWM0_CSG2 SRE: STRSE Mask             */\r
+#define HRPWM0_CSG2_SRE_STPSE_Pos             4                                                       /*!< HRPWM0_CSG2 SRE: STPSE Position         */\r
+#define HRPWM0_CSG2_SRE_STPSE_Msk             (0x01UL << HRPWM0_CSG2_SRE_STPSE_Pos)                   /*!< HRPWM0_CSG2 SRE: STPSE Mask             */\r
+#define HRPWM0_CSG2_SRE_STDE_Pos              5                                                       /*!< HRPWM0_CSG2 SRE: STDE Position          */\r
+#define HRPWM0_CSG2_SRE_STDE_Msk              (0x01UL << HRPWM0_CSG2_SRE_STDE_Pos)                    /*!< HRPWM0_CSG2 SRE: STDE Mask              */\r
+#define HRPWM0_CSG2_SRE_CRSE_Pos              6                                                       /*!< HRPWM0_CSG2 SRE: CRSE Position          */\r
+#define HRPWM0_CSG2_SRE_CRSE_Msk              (0x01UL << HRPWM0_CSG2_SRE_CRSE_Pos)                    /*!< HRPWM0_CSG2 SRE: CRSE Mask              */\r
+#define HRPWM0_CSG2_SRE_CFSE_Pos              7                                                       /*!< HRPWM0_CSG2 SRE: CFSE Position          */\r
+#define HRPWM0_CSG2_SRE_CFSE_Msk              (0x01UL << HRPWM0_CSG2_SRE_CFSE_Pos)                    /*!< HRPWM0_CSG2 SRE: CFSE Mask              */\r
+#define HRPWM0_CSG2_SRE_CSEE_Pos              8                                                       /*!< HRPWM0_CSG2 SRE: CSEE Position          */\r
+#define HRPWM0_CSG2_SRE_CSEE_Msk              (0x01UL << HRPWM0_CSG2_SRE_CSEE_Pos)                    /*!< HRPWM0_CSG2 SRE: CSEE Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SRS  ------------------------------ */\r
+#define HRPWM0_CSG2_SRS_VLS1S_Pos             0                                                       /*!< HRPWM0_CSG2 SRS: VLS1S Position         */\r
+#define HRPWM0_CSG2_SRS_VLS1S_Msk             (0x03UL << HRPWM0_CSG2_SRS_VLS1S_Pos)                   /*!< HRPWM0_CSG2 SRS: VLS1S Mask             */\r
+#define HRPWM0_CSG2_SRS_VLS2S_Pos             2                                                       /*!< HRPWM0_CSG2 SRS: VLS2S Position         */\r
+#define HRPWM0_CSG2_SRS_VLS2S_Msk             (0x03UL << HRPWM0_CSG2_SRS_VLS2S_Pos)                   /*!< HRPWM0_CSG2 SRS: VLS2S Mask             */\r
+#define HRPWM0_CSG2_SRS_TRLS_Pos              4                                                       /*!< HRPWM0_CSG2 SRS: TRLS Position          */\r
+#define HRPWM0_CSG2_SRS_TRLS_Msk              (0x03UL << HRPWM0_CSG2_SRS_TRLS_Pos)                    /*!< HRPWM0_CSG2 SRS: TRLS Mask              */\r
+#define HRPWM0_CSG2_SRS_SSLS_Pos              6                                                       /*!< HRPWM0_CSG2 SRS: SSLS Position          */\r
+#define HRPWM0_CSG2_SRS_SSLS_Msk              (0x03UL << HRPWM0_CSG2_SRS_SSLS_Pos)                    /*!< HRPWM0_CSG2 SRS: SSLS Mask              */\r
+#define HRPWM0_CSG2_SRS_STLS_Pos              8                                                       /*!< HRPWM0_CSG2 SRS: STLS Position          */\r
+#define HRPWM0_CSG2_SRS_STLS_Msk              (0x03UL << HRPWM0_CSG2_SRS_STLS_Pos)                    /*!< HRPWM0_CSG2 SRS: STLS Mask              */\r
+#define HRPWM0_CSG2_SRS_CRFLS_Pos             10                                                      /*!< HRPWM0_CSG2 SRS: CRFLS Position         */\r
+#define HRPWM0_CSG2_SRS_CRFLS_Msk             (0x03UL << HRPWM0_CSG2_SRS_CRFLS_Pos)                   /*!< HRPWM0_CSG2 SRS: CRFLS Mask             */\r
+#define HRPWM0_CSG2_SRS_CSLS_Pos              12                                                      /*!< HRPWM0_CSG2 SRS: CSLS Position          */\r
+#define HRPWM0_CSG2_SRS_CSLS_Msk              (0x03UL << HRPWM0_CSG2_SRS_CSLS_Pos)                    /*!< HRPWM0_CSG2 SRS: CSLS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SWS  ------------------------------ */\r
+#define HRPWM0_CSG2_SWS_SVLS1_Pos             0                                                       /*!< HRPWM0_CSG2 SWS: SVLS1 Position         */\r
+#define HRPWM0_CSG2_SWS_SVLS1_Msk             (0x01UL << HRPWM0_CSG2_SWS_SVLS1_Pos)                   /*!< HRPWM0_CSG2 SWS: SVLS1 Mask             */\r
+#define HRPWM0_CSG2_SWS_SVLS2_Pos             1                                                       /*!< HRPWM0_CSG2 SWS: SVLS2 Position         */\r
+#define HRPWM0_CSG2_SWS_SVLS2_Msk             (0x01UL << HRPWM0_CSG2_SWS_SVLS2_Pos)                   /*!< HRPWM0_CSG2 SWS: SVLS2 Mask             */\r
+#define HRPWM0_CSG2_SWS_STRGS_Pos             2                                                       /*!< HRPWM0_CSG2 SWS: STRGS Position         */\r
+#define HRPWM0_CSG2_SWS_STRGS_Msk             (0x01UL << HRPWM0_CSG2_SWS_STRGS_Pos)                   /*!< HRPWM0_CSG2 SWS: STRGS Mask             */\r
+#define HRPWM0_CSG2_SWS_SSTRS_Pos             3                                                       /*!< HRPWM0_CSG2 SWS: SSTRS Position         */\r
+#define HRPWM0_CSG2_SWS_SSTRS_Msk             (0x01UL << HRPWM0_CSG2_SWS_SSTRS_Pos)                   /*!< HRPWM0_CSG2 SWS: SSTRS Mask             */\r
+#define HRPWM0_CSG2_SWS_SSTPS_Pos             4                                                       /*!< HRPWM0_CSG2 SWS: SSTPS Position         */\r
+#define HRPWM0_CSG2_SWS_SSTPS_Msk             (0x01UL << HRPWM0_CSG2_SWS_SSTPS_Pos)                   /*!< HRPWM0_CSG2 SWS: SSTPS Mask             */\r
+#define HRPWM0_CSG2_SWS_SSTD_Pos              5                                                       /*!< HRPWM0_CSG2 SWS: SSTD Position          */\r
+#define HRPWM0_CSG2_SWS_SSTD_Msk              (0x01UL << HRPWM0_CSG2_SWS_SSTD_Pos)                    /*!< HRPWM0_CSG2 SWS: SSTD Mask              */\r
+#define HRPWM0_CSG2_SWS_SCRS_Pos              6                                                       /*!< HRPWM0_CSG2 SWS: SCRS Position          */\r
+#define HRPWM0_CSG2_SWS_SCRS_Msk              (0x01UL << HRPWM0_CSG2_SWS_SCRS_Pos)                    /*!< HRPWM0_CSG2 SWS: SCRS Mask              */\r
+#define HRPWM0_CSG2_SWS_SCFS_Pos              7                                                       /*!< HRPWM0_CSG2 SWS: SCFS Position          */\r
+#define HRPWM0_CSG2_SWS_SCFS_Msk              (0x01UL << HRPWM0_CSG2_SWS_SCFS_Pos)                    /*!< HRPWM0_CSG2 SWS: SCFS Mask              */\r
+#define HRPWM0_CSG2_SWS_SCSS_Pos              8                                                       /*!< HRPWM0_CSG2 SWS: SCSS Position          */\r
+#define HRPWM0_CSG2_SWS_SCSS_Msk              (0x01UL << HRPWM0_CSG2_SWS_SCSS_Pos)                    /*!< HRPWM0_CSG2 SWS: SCSS Mask              */\r
+\r
+/* -------------------------------  HRPWM0_CSG2_SWC  ------------------------------ */\r
+#define HRPWM0_CSG2_SWC_CVLS1_Pos             0                                                       /*!< HRPWM0_CSG2 SWC: CVLS1 Position         */\r
+#define HRPWM0_CSG2_SWC_CVLS1_Msk             (0x01UL << HRPWM0_CSG2_SWC_CVLS1_Pos)                   /*!< HRPWM0_CSG2 SWC: CVLS1 Mask             */\r
+#define HRPWM0_CSG2_SWC_CVLS2_Pos             1                                                       /*!< HRPWM0_CSG2 SWC: CVLS2 Position         */\r
+#define HRPWM0_CSG2_SWC_CVLS2_Msk             (0x01UL << HRPWM0_CSG2_SWC_CVLS2_Pos)                   /*!< HRPWM0_CSG2 SWC: CVLS2 Mask             */\r
+#define HRPWM0_CSG2_SWC_CTRGS_Pos             2                                                       /*!< HRPWM0_CSG2 SWC: CTRGS Position         */\r
+#define HRPWM0_CSG2_SWC_CTRGS_Msk             (0x01UL << HRPWM0_CSG2_SWC_CTRGS_Pos)                   /*!< HRPWM0_CSG2 SWC: CTRGS Mask             */\r
+#define HRPWM0_CSG2_SWC_CSTRS_Pos             3                                                       /*!< HRPWM0_CSG2 SWC: CSTRS Position         */\r
+#define HRPWM0_CSG2_SWC_CSTRS_Msk             (0x01UL << HRPWM0_CSG2_SWC_CSTRS_Pos)                   /*!< HRPWM0_CSG2 SWC: CSTRS Mask             */\r
+#define HRPWM0_CSG2_SWC_CSTPS_Pos             4                                                       /*!< HRPWM0_CSG2 SWC: CSTPS Position         */\r
+#define HRPWM0_CSG2_SWC_CSTPS_Msk             (0x01UL << HRPWM0_CSG2_SWC_CSTPS_Pos)                   /*!< HRPWM0_CSG2 SWC: CSTPS Mask             */\r
+#define HRPWM0_CSG2_SWC_CSTD_Pos              5                                                       /*!< HRPWM0_CSG2 SWC: CSTD Position          */\r
+#define HRPWM0_CSG2_SWC_CSTD_Msk              (0x01UL << HRPWM0_CSG2_SWC_CSTD_Pos)                    /*!< HRPWM0_CSG2 SWC: CSTD Mask              */\r
+#define HRPWM0_CSG2_SWC_CCRS_Pos              6                                                       /*!< HRPWM0_CSG2 SWC: CCRS Position          */\r
+#define HRPWM0_CSG2_SWC_CCRS_Msk              (0x01UL << HRPWM0_CSG2_SWC_CCRS_Pos)                    /*!< HRPWM0_CSG2 SWC: CCRS Mask              */\r
+#define HRPWM0_CSG2_SWC_CCFS_Pos              7                                                       /*!< HRPWM0_CSG2 SWC: CCFS Position          */\r
+#define HRPWM0_CSG2_SWC_CCFS_Msk              (0x01UL << HRPWM0_CSG2_SWC_CCFS_Pos)                    /*!< HRPWM0_CSG2 SWC: CCFS Mask              */\r
+#define HRPWM0_CSG2_SWC_CCSS_Pos              8                                                       /*!< HRPWM0_CSG2 SWC: CCSS Position          */\r
+#define HRPWM0_CSG2_SWC_CCSS_Msk              (0x01UL << HRPWM0_CSG2_SWC_CCSS_Pos)                    /*!< HRPWM0_CSG2 SWC: CCSS Mask              */\r
+\r
+/* ------------------------------  HRPWM0_CSG2_ISTAT  ----------------------------- */\r
+#define HRPWM0_CSG2_ISTAT_VLS1S_Pos           0                                                       /*!< HRPWM0_CSG2 ISTAT: VLS1S Position       */\r
+#define HRPWM0_CSG2_ISTAT_VLS1S_Msk           (0x01UL << HRPWM0_CSG2_ISTAT_VLS1S_Pos)                 /*!< HRPWM0_CSG2 ISTAT: VLS1S Mask           */\r
+#define HRPWM0_CSG2_ISTAT_VLS2S_Pos           1                                                       /*!< HRPWM0_CSG2 ISTAT: VLS2S Position       */\r
+#define HRPWM0_CSG2_ISTAT_VLS2S_Msk           (0x01UL << HRPWM0_CSG2_ISTAT_VLS2S_Pos)                 /*!< HRPWM0_CSG2 ISTAT: VLS2S Mask           */\r
+#define HRPWM0_CSG2_ISTAT_TRGSS_Pos           2                                                       /*!< HRPWM0_CSG2 ISTAT: TRGSS Position       */\r
+#define HRPWM0_CSG2_ISTAT_TRGSS_Msk           (0x01UL << HRPWM0_CSG2_ISTAT_TRGSS_Pos)                 /*!< HRPWM0_CSG2 ISTAT: TRGSS Mask           */\r
+#define HRPWM0_CSG2_ISTAT_STRSS_Pos           3                                                       /*!< HRPWM0_CSG2 ISTAT: STRSS Position       */\r
+#define HRPWM0_CSG2_ISTAT_STRSS_Msk           (0x01UL << HRPWM0_CSG2_ISTAT_STRSS_Pos)                 /*!< HRPWM0_CSG2 ISTAT: STRSS Mask           */\r
+#define HRPWM0_CSG2_ISTAT_STPSS_Pos           4                                                       /*!< HRPWM0_CSG2 ISTAT: STPSS Position       */\r
+#define HRPWM0_CSG2_ISTAT_STPSS_Msk           (0x01UL << HRPWM0_CSG2_ISTAT_STPSS_Pos)                 /*!< HRPWM0_CSG2 ISTAT: STPSS Mask           */\r
+#define HRPWM0_CSG2_ISTAT_STDS_Pos            5                                                       /*!< HRPWM0_CSG2 ISTAT: STDS Position        */\r
+#define HRPWM0_CSG2_ISTAT_STDS_Msk            (0x01UL << HRPWM0_CSG2_ISTAT_STDS_Pos)                  /*!< HRPWM0_CSG2 ISTAT: STDS Mask            */\r
+#define HRPWM0_CSG2_ISTAT_CRSS_Pos            6                                                       /*!< HRPWM0_CSG2 ISTAT: CRSS Position        */\r
+#define HRPWM0_CSG2_ISTAT_CRSS_Msk            (0x01UL << HRPWM0_CSG2_ISTAT_CRSS_Pos)                  /*!< HRPWM0_CSG2 ISTAT: CRSS Mask            */\r
+#define HRPWM0_CSG2_ISTAT_CFSS_Pos            7                                                       /*!< HRPWM0_CSG2 ISTAT: CFSS Position        */\r
+#define HRPWM0_CSG2_ISTAT_CFSS_Msk            (0x01UL << HRPWM0_CSG2_ISTAT_CFSS_Pos)                  /*!< HRPWM0_CSG2 ISTAT: CFSS Mask            */\r
+#define HRPWM0_CSG2_ISTAT_CSES_Pos            8                                                       /*!< HRPWM0_CSG2 ISTAT: CSES Position        */\r
+#define HRPWM0_CSG2_ISTAT_CSES_Msk            (0x01UL << HRPWM0_CSG2_ISTAT_CSES_Pos)                  /*!< HRPWM0_CSG2 ISTAT: CSES Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       Group 'HRPWM0_HRC' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  HRPWM0_HRC_GC  ------------------------------- */\r
+#define HRPWM0_HRC_GC_HRM0_Pos                0                                                       /*!< HRPWM0_HRC GC: HRM0 Position            */\r
+#define HRPWM0_HRC_GC_HRM0_Msk                (0x03UL << HRPWM0_HRC_GC_HRM0_Pos)                      /*!< HRPWM0_HRC GC: HRM0 Mask                */\r
+#define HRPWM0_HRC_GC_HRM1_Pos                2                                                       /*!< HRPWM0_HRC GC: HRM1 Position            */\r
+#define HRPWM0_HRC_GC_HRM1_Msk                (0x03UL << HRPWM0_HRC_GC_HRM1_Pos)                      /*!< HRPWM0_HRC GC: HRM1 Mask                */\r
+#define HRPWM0_HRC_GC_DTE_Pos                 8                                                       /*!< HRPWM0_HRC GC: DTE Position             */\r
+#define HRPWM0_HRC_GC_DTE_Msk                 (0x01UL << HRPWM0_HRC_GC_DTE_Pos)                       /*!< HRPWM0_HRC GC: DTE Mask                 */\r
+#define HRPWM0_HRC_GC_TR0E_Pos                9                                                       /*!< HRPWM0_HRC GC: TR0E Position            */\r
+#define HRPWM0_HRC_GC_TR0E_Msk                (0x01UL << HRPWM0_HRC_GC_TR0E_Pos)                      /*!< HRPWM0_HRC GC: TR0E Mask                */\r
+#define HRPWM0_HRC_GC_TR1E_Pos                10                                                      /*!< HRPWM0_HRC GC: TR1E Position            */\r
+#define HRPWM0_HRC_GC_TR1E_Msk                (0x01UL << HRPWM0_HRC_GC_TR1E_Pos)                      /*!< HRPWM0_HRC GC: TR1E Mask                */\r
+#define HRPWM0_HRC_GC_STC_Pos                 11                                                      /*!< HRPWM0_HRC GC: STC Position             */\r
+#define HRPWM0_HRC_GC_STC_Msk                 (0x01UL << HRPWM0_HRC_GC_STC_Pos)                       /*!< HRPWM0_HRC GC: STC Mask                 */\r
+#define HRPWM0_HRC_GC_DSTC_Pos                12                                                      /*!< HRPWM0_HRC GC: DSTC Position            */\r
+#define HRPWM0_HRC_GC_DSTC_Msk                (0x01UL << HRPWM0_HRC_GC_DSTC_Pos)                      /*!< HRPWM0_HRC GC: DSTC Mask                */\r
+#define HRPWM0_HRC_GC_OCS0_Pos                13                                                      /*!< HRPWM0_HRC GC: OCS0 Position            */\r
+#define HRPWM0_HRC_GC_OCS0_Msk                (0x01UL << HRPWM0_HRC_GC_OCS0_Pos)                      /*!< HRPWM0_HRC GC: OCS0 Mask                */\r
+#define HRPWM0_HRC_GC_OCS1_Pos                14                                                      /*!< HRPWM0_HRC GC: OCS1 Position            */\r
+#define HRPWM0_HRC_GC_OCS1_Msk                (0x01UL << HRPWM0_HRC_GC_OCS1_Pos)                      /*!< HRPWM0_HRC GC: OCS1 Mask                */\r
+#define HRPWM0_HRC_GC_DTUS_Pos                16                                                      /*!< HRPWM0_HRC GC: DTUS Position            */\r
+#define HRPWM0_HRC_GC_DTUS_Msk                (0x01UL << HRPWM0_HRC_GC_DTUS_Pos)                      /*!< HRPWM0_HRC GC: DTUS Mask                */\r
+\r
+/* --------------------------------  HRPWM0_HRC_PL  ------------------------------- */\r
+#define HRPWM0_HRC_PL_PSL0_Pos                0                                                       /*!< HRPWM0_HRC PL: PSL0 Position            */\r
+#define HRPWM0_HRC_PL_PSL0_Msk                (0x01UL << HRPWM0_HRC_PL_PSL0_Pos)                      /*!< HRPWM0_HRC PL: PSL0 Mask                */\r
+#define HRPWM0_HRC_PL_PSL1_Pos                1                                                       /*!< HRPWM0_HRC PL: PSL1 Position            */\r
+#define HRPWM0_HRC_PL_PSL1_Msk                (0x01UL << HRPWM0_HRC_PL_PSL1_Pos)                      /*!< HRPWM0_HRC PL: PSL1 Mask                */\r
+\r
+/* -------------------------------  HRPWM0_HRC_GSEL  ------------------------------ */\r
+#define HRPWM0_HRC_GSEL_C0SS_Pos              0                                                       /*!< HRPWM0_HRC GSEL: C0SS Position          */\r
+#define HRPWM0_HRC_GSEL_C0SS_Msk              (0x07UL << HRPWM0_HRC_GSEL_C0SS_Pos)                    /*!< HRPWM0_HRC GSEL: C0SS Mask              */\r
+#define HRPWM0_HRC_GSEL_C0CS_Pos              3                                                       /*!< HRPWM0_HRC GSEL: C0CS Position          */\r
+#define HRPWM0_HRC_GSEL_C0CS_Msk              (0x07UL << HRPWM0_HRC_GSEL_C0CS_Pos)                    /*!< HRPWM0_HRC GSEL: C0CS Mask              */\r
+#define HRPWM0_HRC_GSEL_S0M_Pos               6                                                       /*!< HRPWM0_HRC GSEL: S0M Position           */\r
+#define HRPWM0_HRC_GSEL_S0M_Msk               (0x03UL << HRPWM0_HRC_GSEL_S0M_Pos)                     /*!< HRPWM0_HRC GSEL: S0M Mask               */\r
+#define HRPWM0_HRC_GSEL_C0M_Pos               8                                                       /*!< HRPWM0_HRC GSEL: C0M Position           */\r
+#define HRPWM0_HRC_GSEL_C0M_Msk               (0x03UL << HRPWM0_HRC_GSEL_C0M_Pos)                     /*!< HRPWM0_HRC GSEL: C0M Mask               */\r
+#define HRPWM0_HRC_GSEL_S0ES_Pos              10                                                      /*!< HRPWM0_HRC GSEL: S0ES Position          */\r
+#define HRPWM0_HRC_GSEL_S0ES_Msk              (0x03UL << HRPWM0_HRC_GSEL_S0ES_Pos)                    /*!< HRPWM0_HRC GSEL: S0ES Mask              */\r
+#define HRPWM0_HRC_GSEL_C0ES_Pos              12                                                      /*!< HRPWM0_HRC GSEL: C0ES Position          */\r
+#define HRPWM0_HRC_GSEL_C0ES_Msk              (0x03UL << HRPWM0_HRC_GSEL_C0ES_Pos)                    /*!< HRPWM0_HRC GSEL: C0ES Mask              */\r
+#define HRPWM0_HRC_GSEL_C1SS_Pos              16                                                      /*!< HRPWM0_HRC GSEL: C1SS Position          */\r
+#define HRPWM0_HRC_GSEL_C1SS_Msk              (0x07UL << HRPWM0_HRC_GSEL_C1SS_Pos)                    /*!< HRPWM0_HRC GSEL: C1SS Mask              */\r
+#define HRPWM0_HRC_GSEL_C1CS_Pos              19                                                      /*!< HRPWM0_HRC GSEL: C1CS Position          */\r
+#define HRPWM0_HRC_GSEL_C1CS_Msk              (0x07UL << HRPWM0_HRC_GSEL_C1CS_Pos)                    /*!< HRPWM0_HRC GSEL: C1CS Mask              */\r
+#define HRPWM0_HRC_GSEL_S1M_Pos               22                                                      /*!< HRPWM0_HRC GSEL: S1M Position           */\r
+#define HRPWM0_HRC_GSEL_S1M_Msk               (0x03UL << HRPWM0_HRC_GSEL_S1M_Pos)                     /*!< HRPWM0_HRC GSEL: S1M Mask               */\r
+#define HRPWM0_HRC_GSEL_C1M_Pos               24                                                      /*!< HRPWM0_HRC GSEL: C1M Position           */\r
+#define HRPWM0_HRC_GSEL_C1M_Msk               (0x03UL << HRPWM0_HRC_GSEL_C1M_Pos)                     /*!< HRPWM0_HRC GSEL: C1M Mask               */\r
+#define HRPWM0_HRC_GSEL_S1ES_Pos              26                                                      /*!< HRPWM0_HRC GSEL: S1ES Position          */\r
+#define HRPWM0_HRC_GSEL_S1ES_Msk              (0x03UL << HRPWM0_HRC_GSEL_S1ES_Pos)                    /*!< HRPWM0_HRC GSEL: S1ES Mask              */\r
+#define HRPWM0_HRC_GSEL_C1ES_Pos              28                                                      /*!< HRPWM0_HRC GSEL: C1ES Position          */\r
+#define HRPWM0_HRC_GSEL_C1ES_Msk              (0x03UL << HRPWM0_HRC_GSEL_C1ES_Pos)                    /*!< HRPWM0_HRC GSEL: C1ES Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC_TSEL  ------------------------------ */\r
+#define HRPWM0_HRC_TSEL_TSEL0_Pos             0                                                       /*!< HRPWM0_HRC TSEL: TSEL0 Position         */\r
+#define HRPWM0_HRC_TSEL_TSEL0_Msk             (0x07UL << HRPWM0_HRC_TSEL_TSEL0_Pos)                   /*!< HRPWM0_HRC TSEL: TSEL0 Mask             */\r
+#define HRPWM0_HRC_TSEL_TSEL1_Pos             3                                                       /*!< HRPWM0_HRC TSEL: TSEL1 Position         */\r
+#define HRPWM0_HRC_TSEL_TSEL1_Msk             (0x07UL << HRPWM0_HRC_TSEL_TSEL1_Pos)                   /*!< HRPWM0_HRC TSEL: TSEL1 Mask             */\r
+#define HRPWM0_HRC_TSEL_TS0E_Pos              16                                                      /*!< HRPWM0_HRC TSEL: TS0E Position          */\r
+#define HRPWM0_HRC_TSEL_TS0E_Msk              (0x01UL << HRPWM0_HRC_TSEL_TS0E_Pos)                    /*!< HRPWM0_HRC TSEL: TS0E Mask              */\r
+#define HRPWM0_HRC_TSEL_TS1E_Pos              17                                                      /*!< HRPWM0_HRC TSEL: TS1E Position          */\r
+#define HRPWM0_HRC_TSEL_TS1E_Msk              (0x01UL << HRPWM0_HRC_TSEL_TS1E_Pos)                    /*!< HRPWM0_HRC TSEL: TS1E Mask              */\r
+\r
+/* --------------------------------  HRPWM0_HRC_SC  ------------------------------- */\r
+#define HRPWM0_HRC_SC_ST_Pos                  0                                                       /*!< HRPWM0_HRC SC: ST Position              */\r
+#define HRPWM0_HRC_SC_ST_Msk                  (0x01UL << HRPWM0_HRC_SC_ST_Pos)                        /*!< HRPWM0_HRC SC: ST Mask                  */\r
+\r
+/* -------------------------------  HRPWM0_HRC_DCR  ------------------------------- */\r
+#define HRPWM0_HRC_DCR_DTRV_Pos               0                                                       /*!< HRPWM0_HRC DCR: DTRV Position           */\r
+#define HRPWM0_HRC_DCR_DTRV_Msk               (0x0000ffffUL << HRPWM0_HRC_DCR_DTRV_Pos)               /*!< HRPWM0_HRC DCR: DTRV Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC_DCF  ------------------------------- */\r
+#define HRPWM0_HRC_DCF_DTFV_Pos               0                                                       /*!< HRPWM0_HRC DCF: DTFV Position           */\r
+#define HRPWM0_HRC_DCF_DTFV_Msk               (0x0000ffffUL << HRPWM0_HRC_DCF_DTFV_Pos)               /*!< HRPWM0_HRC DCF: DTFV Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC_CR1  ------------------------------- */\r
+#define HRPWM0_HRC_CR1_CR1_Pos                0                                                       /*!< HRPWM0_HRC CR1: CR1 Position            */\r
+#define HRPWM0_HRC_CR1_CR1_Msk                (0x000000ffUL << HRPWM0_HRC_CR1_CR1_Pos)                /*!< HRPWM0_HRC CR1: CR1 Mask                */\r
+\r
+/* -------------------------------  HRPWM0_HRC_CR2  ------------------------------- */\r
+#define HRPWM0_HRC_CR2_CR2_Pos                0                                                       /*!< HRPWM0_HRC CR2: CR2 Position            */\r
+#define HRPWM0_HRC_CR2_CR2_Msk                (0x000000ffUL << HRPWM0_HRC_CR2_CR2_Pos)                /*!< HRPWM0_HRC CR2: CR2 Mask                */\r
+\r
+/* -------------------------------  HRPWM0_HRC_SSC  ------------------------------- */\r
+#define HRPWM0_HRC_SSC_SST_Pos                0                                                       /*!< HRPWM0_HRC SSC: SST Position            */\r
+#define HRPWM0_HRC_SSC_SST_Msk                (0x01UL << HRPWM0_HRC_SSC_SST_Pos)                      /*!< HRPWM0_HRC SSC: SST Mask                */\r
+\r
+/* -------------------------------  HRPWM0_HRC_SDCR  ------------------------------ */\r
+#define HRPWM0_HRC_SDCR_SDTRV_Pos             0                                                       /*!< HRPWM0_HRC SDCR: SDTRV Position         */\r
+#define HRPWM0_HRC_SDCR_SDTRV_Msk             (0x0000ffffUL << HRPWM0_HRC_SDCR_SDTRV_Pos)             /*!< HRPWM0_HRC SDCR: SDTRV Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC_SDCF  ------------------------------ */\r
+#define HRPWM0_HRC_SDCF_SDTFV_Pos             0                                                       /*!< HRPWM0_HRC SDCF: SDTFV Position         */\r
+#define HRPWM0_HRC_SDCF_SDTFV_Msk             (0x0000ffffUL << HRPWM0_HRC_SDCF_SDTFV_Pos)             /*!< HRPWM0_HRC SDCF: SDTFV Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC_SCR1  ------------------------------ */\r
+#define HRPWM0_HRC_SCR1_SCR1_Pos              0                                                       /*!< HRPWM0_HRC SCR1: SCR1 Position          */\r
+#define HRPWM0_HRC_SCR1_SCR1_Msk              (0x000000ffUL << HRPWM0_HRC_SCR1_SCR1_Pos)              /*!< HRPWM0_HRC SCR1: SCR1 Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC_SCR2  ------------------------------ */\r
+#define HRPWM0_HRC_SCR2_SCR2_Pos              0                                                       /*!< HRPWM0_HRC SCR2: SCR2 Position          */\r
+#define HRPWM0_HRC_SCR2_SCR2_Msk              (0x000000ffUL << HRPWM0_HRC_SCR2_SCR2_Pos)              /*!< HRPWM0_HRC SCR2: SCR2 Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_HRC0' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_HRC0_GC  ------------------------------- */\r
+#define HRPWM0_HRC0_GC_HRM0_Pos               0                                                       /*!< HRPWM0_HRC0 GC: HRM0 Position           */\r
+#define HRPWM0_HRC0_GC_HRM0_Msk               (0x03UL << HRPWM0_HRC0_GC_HRM0_Pos)                     /*!< HRPWM0_HRC0 GC: HRM0 Mask               */\r
+#define HRPWM0_HRC0_GC_HRM1_Pos               2                                                       /*!< HRPWM0_HRC0 GC: HRM1 Position           */\r
+#define HRPWM0_HRC0_GC_HRM1_Msk               (0x03UL << HRPWM0_HRC0_GC_HRM1_Pos)                     /*!< HRPWM0_HRC0 GC: HRM1 Mask               */\r
+#define HRPWM0_HRC0_GC_DTE_Pos                8                                                       /*!< HRPWM0_HRC0 GC: DTE Position            */\r
+#define HRPWM0_HRC0_GC_DTE_Msk                (0x01UL << HRPWM0_HRC0_GC_DTE_Pos)                      /*!< HRPWM0_HRC0 GC: DTE Mask                */\r
+#define HRPWM0_HRC0_GC_TR0E_Pos               9                                                       /*!< HRPWM0_HRC0 GC: TR0E Position           */\r
+#define HRPWM0_HRC0_GC_TR0E_Msk               (0x01UL << HRPWM0_HRC0_GC_TR0E_Pos)                     /*!< HRPWM0_HRC0 GC: TR0E Mask               */\r
+#define HRPWM0_HRC0_GC_TR1E_Pos               10                                                      /*!< HRPWM0_HRC0 GC: TR1E Position           */\r
+#define HRPWM0_HRC0_GC_TR1E_Msk               (0x01UL << HRPWM0_HRC0_GC_TR1E_Pos)                     /*!< HRPWM0_HRC0 GC: TR1E Mask               */\r
+#define HRPWM0_HRC0_GC_STC_Pos                11                                                      /*!< HRPWM0_HRC0 GC: STC Position            */\r
+#define HRPWM0_HRC0_GC_STC_Msk                (0x01UL << HRPWM0_HRC0_GC_STC_Pos)                      /*!< HRPWM0_HRC0 GC: STC Mask                */\r
+#define HRPWM0_HRC0_GC_DSTC_Pos               12                                                      /*!< HRPWM0_HRC0 GC: DSTC Position           */\r
+#define HRPWM0_HRC0_GC_DSTC_Msk               (0x01UL << HRPWM0_HRC0_GC_DSTC_Pos)                     /*!< HRPWM0_HRC0 GC: DSTC Mask               */\r
+#define HRPWM0_HRC0_GC_OCS0_Pos               13                                                      /*!< HRPWM0_HRC0 GC: OCS0 Position           */\r
+#define HRPWM0_HRC0_GC_OCS0_Msk               (0x01UL << HRPWM0_HRC0_GC_OCS0_Pos)                     /*!< HRPWM0_HRC0 GC: OCS0 Mask               */\r
+#define HRPWM0_HRC0_GC_OCS1_Pos               14                                                      /*!< HRPWM0_HRC0 GC: OCS1 Position           */\r
+#define HRPWM0_HRC0_GC_OCS1_Msk               (0x01UL << HRPWM0_HRC0_GC_OCS1_Pos)                     /*!< HRPWM0_HRC0 GC: OCS1 Mask               */\r
+#define HRPWM0_HRC0_GC_DTUS_Pos               16                                                      /*!< HRPWM0_HRC0 GC: DTUS Position           */\r
+#define HRPWM0_HRC0_GC_DTUS_Msk               (0x01UL << HRPWM0_HRC0_GC_DTUS_Pos)                     /*!< HRPWM0_HRC0 GC: DTUS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_PL  ------------------------------- */\r
+#define HRPWM0_HRC0_PL_PSL0_Pos               0                                                       /*!< HRPWM0_HRC0 PL: PSL0 Position           */\r
+#define HRPWM0_HRC0_PL_PSL0_Msk               (0x01UL << HRPWM0_HRC0_PL_PSL0_Pos)                     /*!< HRPWM0_HRC0 PL: PSL0 Mask               */\r
+#define HRPWM0_HRC0_PL_PSL1_Pos               1                                                       /*!< HRPWM0_HRC0 PL: PSL1 Position           */\r
+#define HRPWM0_HRC0_PL_PSL1_Msk               (0x01UL << HRPWM0_HRC0_PL_PSL1_Pos)                     /*!< HRPWM0_HRC0 PL: PSL1 Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_GSEL  ------------------------------ */\r
+#define HRPWM0_HRC0_GSEL_C0SS_Pos             0                                                       /*!< HRPWM0_HRC0 GSEL: C0SS Position         */\r
+#define HRPWM0_HRC0_GSEL_C0SS_Msk             (0x07UL << HRPWM0_HRC0_GSEL_C0SS_Pos)                   /*!< HRPWM0_HRC0 GSEL: C0SS Mask             */\r
+#define HRPWM0_HRC0_GSEL_C0CS_Pos             3                                                       /*!< HRPWM0_HRC0 GSEL: C0CS Position         */\r
+#define HRPWM0_HRC0_GSEL_C0CS_Msk             (0x07UL << HRPWM0_HRC0_GSEL_C0CS_Pos)                   /*!< HRPWM0_HRC0 GSEL: C0CS Mask             */\r
+#define HRPWM0_HRC0_GSEL_S0M_Pos              6                                                       /*!< HRPWM0_HRC0 GSEL: S0M Position          */\r
+#define HRPWM0_HRC0_GSEL_S0M_Msk              (0x03UL << HRPWM0_HRC0_GSEL_S0M_Pos)                    /*!< HRPWM0_HRC0 GSEL: S0M Mask              */\r
+#define HRPWM0_HRC0_GSEL_C0M_Pos              8                                                       /*!< HRPWM0_HRC0 GSEL: C0M Position          */\r
+#define HRPWM0_HRC0_GSEL_C0M_Msk              (0x03UL << HRPWM0_HRC0_GSEL_C0M_Pos)                    /*!< HRPWM0_HRC0 GSEL: C0M Mask              */\r
+#define HRPWM0_HRC0_GSEL_S0ES_Pos             10                                                      /*!< HRPWM0_HRC0 GSEL: S0ES Position         */\r
+#define HRPWM0_HRC0_GSEL_S0ES_Msk             (0x03UL << HRPWM0_HRC0_GSEL_S0ES_Pos)                   /*!< HRPWM0_HRC0 GSEL: S0ES Mask             */\r
+#define HRPWM0_HRC0_GSEL_C0ES_Pos             12                                                      /*!< HRPWM0_HRC0 GSEL: C0ES Position         */\r
+#define HRPWM0_HRC0_GSEL_C0ES_Msk             (0x03UL << HRPWM0_HRC0_GSEL_C0ES_Pos)                   /*!< HRPWM0_HRC0 GSEL: C0ES Mask             */\r
+#define HRPWM0_HRC0_GSEL_C1SS_Pos             16                                                      /*!< HRPWM0_HRC0 GSEL: C1SS Position         */\r
+#define HRPWM0_HRC0_GSEL_C1SS_Msk             (0x07UL << HRPWM0_HRC0_GSEL_C1SS_Pos)                   /*!< HRPWM0_HRC0 GSEL: C1SS Mask             */\r
+#define HRPWM0_HRC0_GSEL_C1CS_Pos             19                                                      /*!< HRPWM0_HRC0 GSEL: C1CS Position         */\r
+#define HRPWM0_HRC0_GSEL_C1CS_Msk             (0x07UL << HRPWM0_HRC0_GSEL_C1CS_Pos)                   /*!< HRPWM0_HRC0 GSEL: C1CS Mask             */\r
+#define HRPWM0_HRC0_GSEL_S1M_Pos              22                                                      /*!< HRPWM0_HRC0 GSEL: S1M Position          */\r
+#define HRPWM0_HRC0_GSEL_S1M_Msk              (0x03UL << HRPWM0_HRC0_GSEL_S1M_Pos)                    /*!< HRPWM0_HRC0 GSEL: S1M Mask              */\r
+#define HRPWM0_HRC0_GSEL_C1M_Pos              24                                                      /*!< HRPWM0_HRC0 GSEL: C1M Position          */\r
+#define HRPWM0_HRC0_GSEL_C1M_Msk              (0x03UL << HRPWM0_HRC0_GSEL_C1M_Pos)                    /*!< HRPWM0_HRC0 GSEL: C1M Mask              */\r
+#define HRPWM0_HRC0_GSEL_S1ES_Pos             26                                                      /*!< HRPWM0_HRC0 GSEL: S1ES Position         */\r
+#define HRPWM0_HRC0_GSEL_S1ES_Msk             (0x03UL << HRPWM0_HRC0_GSEL_S1ES_Pos)                   /*!< HRPWM0_HRC0 GSEL: S1ES Mask             */\r
+#define HRPWM0_HRC0_GSEL_C1ES_Pos             28                                                      /*!< HRPWM0_HRC0 GSEL: C1ES Position         */\r
+#define HRPWM0_HRC0_GSEL_C1ES_Msk             (0x03UL << HRPWM0_HRC0_GSEL_C1ES_Pos)                   /*!< HRPWM0_HRC0 GSEL: C1ES Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_TSEL  ------------------------------ */\r
+#define HRPWM0_HRC0_TSEL_TSEL0_Pos            0                                                       /*!< HRPWM0_HRC0 TSEL: TSEL0 Position        */\r
+#define HRPWM0_HRC0_TSEL_TSEL0_Msk            (0x07UL << HRPWM0_HRC0_TSEL_TSEL0_Pos)                  /*!< HRPWM0_HRC0 TSEL: TSEL0 Mask            */\r
+#define HRPWM0_HRC0_TSEL_TSEL1_Pos            3                                                       /*!< HRPWM0_HRC0 TSEL: TSEL1 Position        */\r
+#define HRPWM0_HRC0_TSEL_TSEL1_Msk            (0x07UL << HRPWM0_HRC0_TSEL_TSEL1_Pos)                  /*!< HRPWM0_HRC0 TSEL: TSEL1 Mask            */\r
+#define HRPWM0_HRC0_TSEL_TS0E_Pos             16                                                      /*!< HRPWM0_HRC0 TSEL: TS0E Position         */\r
+#define HRPWM0_HRC0_TSEL_TS0E_Msk             (0x01UL << HRPWM0_HRC0_TSEL_TS0E_Pos)                   /*!< HRPWM0_HRC0 TSEL: TS0E Mask             */\r
+#define HRPWM0_HRC0_TSEL_TS1E_Pos             17                                                      /*!< HRPWM0_HRC0 TSEL: TS1E Position         */\r
+#define HRPWM0_HRC0_TSEL_TS1E_Msk             (0x01UL << HRPWM0_HRC0_TSEL_TS1E_Pos)                   /*!< HRPWM0_HRC0 TSEL: TS1E Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_SC  ------------------------------- */\r
+#define HRPWM0_HRC0_SC_ST_Pos                 0                                                       /*!< HRPWM0_HRC0 SC: ST Position             */\r
+#define HRPWM0_HRC0_SC_ST_Msk                 (0x01UL << HRPWM0_HRC0_SC_ST_Pos)                       /*!< HRPWM0_HRC0 SC: ST Mask                 */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_DCR  ------------------------------ */\r
+#define HRPWM0_HRC0_DCR_DTRV_Pos              0                                                       /*!< HRPWM0_HRC0 DCR: DTRV Position          */\r
+#define HRPWM0_HRC0_DCR_DTRV_Msk              (0x0000ffffUL << HRPWM0_HRC0_DCR_DTRV_Pos)              /*!< HRPWM0_HRC0 DCR: DTRV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_DCF  ------------------------------ */\r
+#define HRPWM0_HRC0_DCF_DTFV_Pos              0                                                       /*!< HRPWM0_HRC0 DCF: DTFV Position          */\r
+#define HRPWM0_HRC0_DCF_DTFV_Msk              (0x0000ffffUL << HRPWM0_HRC0_DCF_DTFV_Pos)              /*!< HRPWM0_HRC0 DCF: DTFV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_CR1  ------------------------------ */\r
+#define HRPWM0_HRC0_CR1_CR1_Pos               0                                                       /*!< HRPWM0_HRC0 CR1: CR1 Position           */\r
+#define HRPWM0_HRC0_CR1_CR1_Msk               (0x000000ffUL << HRPWM0_HRC0_CR1_CR1_Pos)               /*!< HRPWM0_HRC0 CR1: CR1 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_CR2  ------------------------------ */\r
+#define HRPWM0_HRC0_CR2_CR2_Pos               0                                                       /*!< HRPWM0_HRC0 CR2: CR2 Position           */\r
+#define HRPWM0_HRC0_CR2_CR2_Msk               (0x000000ffUL << HRPWM0_HRC0_CR2_CR2_Pos)               /*!< HRPWM0_HRC0 CR2: CR2 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC0_SSC  ------------------------------ */\r
+#define HRPWM0_HRC0_SSC_SST_Pos               0                                                       /*!< HRPWM0_HRC0 SSC: SST Position           */\r
+#define HRPWM0_HRC0_SSC_SST_Msk               (0x01UL << HRPWM0_HRC0_SSC_SST_Pos)                     /*!< HRPWM0_HRC0 SSC: SST Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_SDCR  ------------------------------ */\r
+#define HRPWM0_HRC0_SDCR_SDTRV_Pos            0                                                       /*!< HRPWM0_HRC0 SDCR: SDTRV Position        */\r
+#define HRPWM0_HRC0_SDCR_SDTRV_Msk            (0x0000ffffUL << HRPWM0_HRC0_SDCR_SDTRV_Pos)            /*!< HRPWM0_HRC0 SDCR: SDTRV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_SDCF  ------------------------------ */\r
+#define HRPWM0_HRC0_SDCF_SDTFV_Pos            0                                                       /*!< HRPWM0_HRC0 SDCF: SDTFV Position        */\r
+#define HRPWM0_HRC0_SDCF_SDTFV_Msk            (0x0000ffffUL << HRPWM0_HRC0_SDCF_SDTFV_Pos)            /*!< HRPWM0_HRC0 SDCF: SDTFV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_SCR1  ------------------------------ */\r
+#define HRPWM0_HRC0_SCR1_SCR1_Pos             0                                                       /*!< HRPWM0_HRC0 SCR1: SCR1 Position         */\r
+#define HRPWM0_HRC0_SCR1_SCR1_Msk             (0x000000ffUL << HRPWM0_HRC0_SCR1_SCR1_Pos)             /*!< HRPWM0_HRC0 SCR1: SCR1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC0_SCR2  ------------------------------ */\r
+#define HRPWM0_HRC0_SCR2_SCR2_Pos             0                                                       /*!< HRPWM0_HRC0 SCR2: SCR2 Position         */\r
+#define HRPWM0_HRC0_SCR2_SCR2_Msk             (0x000000ffUL << HRPWM0_HRC0_SCR2_SCR2_Pos)             /*!< HRPWM0_HRC0 SCR2: SCR2 Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_HRC1' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_HRC1_GC  ------------------------------- */\r
+#define HRPWM0_HRC1_GC_HRM0_Pos               0                                                       /*!< HRPWM0_HRC1 GC: HRM0 Position           */\r
+#define HRPWM0_HRC1_GC_HRM0_Msk               (0x03UL << HRPWM0_HRC1_GC_HRM0_Pos)                     /*!< HRPWM0_HRC1 GC: HRM0 Mask               */\r
+#define HRPWM0_HRC1_GC_HRM1_Pos               2                                                       /*!< HRPWM0_HRC1 GC: HRM1 Position           */\r
+#define HRPWM0_HRC1_GC_HRM1_Msk               (0x03UL << HRPWM0_HRC1_GC_HRM1_Pos)                     /*!< HRPWM0_HRC1 GC: HRM1 Mask               */\r
+#define HRPWM0_HRC1_GC_DTE_Pos                8                                                       /*!< HRPWM0_HRC1 GC: DTE Position            */\r
+#define HRPWM0_HRC1_GC_DTE_Msk                (0x01UL << HRPWM0_HRC1_GC_DTE_Pos)                      /*!< HRPWM0_HRC1 GC: DTE Mask                */\r
+#define HRPWM0_HRC1_GC_TR0E_Pos               9                                                       /*!< HRPWM0_HRC1 GC: TR0E Position           */\r
+#define HRPWM0_HRC1_GC_TR0E_Msk               (0x01UL << HRPWM0_HRC1_GC_TR0E_Pos)                     /*!< HRPWM0_HRC1 GC: TR0E Mask               */\r
+#define HRPWM0_HRC1_GC_TR1E_Pos               10                                                      /*!< HRPWM0_HRC1 GC: TR1E Position           */\r
+#define HRPWM0_HRC1_GC_TR1E_Msk               (0x01UL << HRPWM0_HRC1_GC_TR1E_Pos)                     /*!< HRPWM0_HRC1 GC: TR1E Mask               */\r
+#define HRPWM0_HRC1_GC_STC_Pos                11                                                      /*!< HRPWM0_HRC1 GC: STC Position            */\r
+#define HRPWM0_HRC1_GC_STC_Msk                (0x01UL << HRPWM0_HRC1_GC_STC_Pos)                      /*!< HRPWM0_HRC1 GC: STC Mask                */\r
+#define HRPWM0_HRC1_GC_DSTC_Pos               12                                                      /*!< HRPWM0_HRC1 GC: DSTC Position           */\r
+#define HRPWM0_HRC1_GC_DSTC_Msk               (0x01UL << HRPWM0_HRC1_GC_DSTC_Pos)                     /*!< HRPWM0_HRC1 GC: DSTC Mask               */\r
+#define HRPWM0_HRC1_GC_OCS0_Pos               13                                                      /*!< HRPWM0_HRC1 GC: OCS0 Position           */\r
+#define HRPWM0_HRC1_GC_OCS0_Msk               (0x01UL << HRPWM0_HRC1_GC_OCS0_Pos)                     /*!< HRPWM0_HRC1 GC: OCS0 Mask               */\r
+#define HRPWM0_HRC1_GC_OCS1_Pos               14                                                      /*!< HRPWM0_HRC1 GC: OCS1 Position           */\r
+#define HRPWM0_HRC1_GC_OCS1_Msk               (0x01UL << HRPWM0_HRC1_GC_OCS1_Pos)                     /*!< HRPWM0_HRC1 GC: OCS1 Mask               */\r
+#define HRPWM0_HRC1_GC_DTUS_Pos               16                                                      /*!< HRPWM0_HRC1 GC: DTUS Position           */\r
+#define HRPWM0_HRC1_GC_DTUS_Msk               (0x01UL << HRPWM0_HRC1_GC_DTUS_Pos)                     /*!< HRPWM0_HRC1 GC: DTUS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_PL  ------------------------------- */\r
+#define HRPWM0_HRC1_PL_PSL0_Pos               0                                                       /*!< HRPWM0_HRC1 PL: PSL0 Position           */\r
+#define HRPWM0_HRC1_PL_PSL0_Msk               (0x01UL << HRPWM0_HRC1_PL_PSL0_Pos)                     /*!< HRPWM0_HRC1 PL: PSL0 Mask               */\r
+#define HRPWM0_HRC1_PL_PSL1_Pos               1                                                       /*!< HRPWM0_HRC1 PL: PSL1 Position           */\r
+#define HRPWM0_HRC1_PL_PSL1_Msk               (0x01UL << HRPWM0_HRC1_PL_PSL1_Pos)                     /*!< HRPWM0_HRC1 PL: PSL1 Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_GSEL  ------------------------------ */\r
+#define HRPWM0_HRC1_GSEL_C0SS_Pos             0                                                       /*!< HRPWM0_HRC1 GSEL: C0SS Position         */\r
+#define HRPWM0_HRC1_GSEL_C0SS_Msk             (0x07UL << HRPWM0_HRC1_GSEL_C0SS_Pos)                   /*!< HRPWM0_HRC1 GSEL: C0SS Mask             */\r
+#define HRPWM0_HRC1_GSEL_C0CS_Pos             3                                                       /*!< HRPWM0_HRC1 GSEL: C0CS Position         */\r
+#define HRPWM0_HRC1_GSEL_C0CS_Msk             (0x07UL << HRPWM0_HRC1_GSEL_C0CS_Pos)                   /*!< HRPWM0_HRC1 GSEL: C0CS Mask             */\r
+#define HRPWM0_HRC1_GSEL_S0M_Pos              6                                                       /*!< HRPWM0_HRC1 GSEL: S0M Position          */\r
+#define HRPWM0_HRC1_GSEL_S0M_Msk              (0x03UL << HRPWM0_HRC1_GSEL_S0M_Pos)                    /*!< HRPWM0_HRC1 GSEL: S0M Mask              */\r
+#define HRPWM0_HRC1_GSEL_C0M_Pos              8                                                       /*!< HRPWM0_HRC1 GSEL: C0M Position          */\r
+#define HRPWM0_HRC1_GSEL_C0M_Msk              (0x03UL << HRPWM0_HRC1_GSEL_C0M_Pos)                    /*!< HRPWM0_HRC1 GSEL: C0M Mask              */\r
+#define HRPWM0_HRC1_GSEL_S0ES_Pos             10                                                      /*!< HRPWM0_HRC1 GSEL: S0ES Position         */\r
+#define HRPWM0_HRC1_GSEL_S0ES_Msk             (0x03UL << HRPWM0_HRC1_GSEL_S0ES_Pos)                   /*!< HRPWM0_HRC1 GSEL: S0ES Mask             */\r
+#define HRPWM0_HRC1_GSEL_C0ES_Pos             12                                                      /*!< HRPWM0_HRC1 GSEL: C0ES Position         */\r
+#define HRPWM0_HRC1_GSEL_C0ES_Msk             (0x03UL << HRPWM0_HRC1_GSEL_C0ES_Pos)                   /*!< HRPWM0_HRC1 GSEL: C0ES Mask             */\r
+#define HRPWM0_HRC1_GSEL_C1SS_Pos             16                                                      /*!< HRPWM0_HRC1 GSEL: C1SS Position         */\r
+#define HRPWM0_HRC1_GSEL_C1SS_Msk             (0x07UL << HRPWM0_HRC1_GSEL_C1SS_Pos)                   /*!< HRPWM0_HRC1 GSEL: C1SS Mask             */\r
+#define HRPWM0_HRC1_GSEL_C1CS_Pos             19                                                      /*!< HRPWM0_HRC1 GSEL: C1CS Position         */\r
+#define HRPWM0_HRC1_GSEL_C1CS_Msk             (0x07UL << HRPWM0_HRC1_GSEL_C1CS_Pos)                   /*!< HRPWM0_HRC1 GSEL: C1CS Mask             */\r
+#define HRPWM0_HRC1_GSEL_S1M_Pos              22                                                      /*!< HRPWM0_HRC1 GSEL: S1M Position          */\r
+#define HRPWM0_HRC1_GSEL_S1M_Msk              (0x03UL << HRPWM0_HRC1_GSEL_S1M_Pos)                    /*!< HRPWM0_HRC1 GSEL: S1M Mask              */\r
+#define HRPWM0_HRC1_GSEL_C1M_Pos              24                                                      /*!< HRPWM0_HRC1 GSEL: C1M Position          */\r
+#define HRPWM0_HRC1_GSEL_C1M_Msk              (0x03UL << HRPWM0_HRC1_GSEL_C1M_Pos)                    /*!< HRPWM0_HRC1 GSEL: C1M Mask              */\r
+#define HRPWM0_HRC1_GSEL_S1ES_Pos             26                                                      /*!< HRPWM0_HRC1 GSEL: S1ES Position         */\r
+#define HRPWM0_HRC1_GSEL_S1ES_Msk             (0x03UL << HRPWM0_HRC1_GSEL_S1ES_Pos)                   /*!< HRPWM0_HRC1 GSEL: S1ES Mask             */\r
+#define HRPWM0_HRC1_GSEL_C1ES_Pos             28                                                      /*!< HRPWM0_HRC1 GSEL: C1ES Position         */\r
+#define HRPWM0_HRC1_GSEL_C1ES_Msk             (0x03UL << HRPWM0_HRC1_GSEL_C1ES_Pos)                   /*!< HRPWM0_HRC1 GSEL: C1ES Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_TSEL  ------------------------------ */\r
+#define HRPWM0_HRC1_TSEL_TSEL0_Pos            0                                                       /*!< HRPWM0_HRC1 TSEL: TSEL0 Position        */\r
+#define HRPWM0_HRC1_TSEL_TSEL0_Msk            (0x07UL << HRPWM0_HRC1_TSEL_TSEL0_Pos)                  /*!< HRPWM0_HRC1 TSEL: TSEL0 Mask            */\r
+#define HRPWM0_HRC1_TSEL_TSEL1_Pos            3                                                       /*!< HRPWM0_HRC1 TSEL: TSEL1 Position        */\r
+#define HRPWM0_HRC1_TSEL_TSEL1_Msk            (0x07UL << HRPWM0_HRC1_TSEL_TSEL1_Pos)                  /*!< HRPWM0_HRC1 TSEL: TSEL1 Mask            */\r
+#define HRPWM0_HRC1_TSEL_TS0E_Pos             16                                                      /*!< HRPWM0_HRC1 TSEL: TS0E Position         */\r
+#define HRPWM0_HRC1_TSEL_TS0E_Msk             (0x01UL << HRPWM0_HRC1_TSEL_TS0E_Pos)                   /*!< HRPWM0_HRC1 TSEL: TS0E Mask             */\r
+#define HRPWM0_HRC1_TSEL_TS1E_Pos             17                                                      /*!< HRPWM0_HRC1 TSEL: TS1E Position         */\r
+#define HRPWM0_HRC1_TSEL_TS1E_Msk             (0x01UL << HRPWM0_HRC1_TSEL_TS1E_Pos)                   /*!< HRPWM0_HRC1 TSEL: TS1E Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_SC  ------------------------------- */\r
+#define HRPWM0_HRC1_SC_ST_Pos                 0                                                       /*!< HRPWM0_HRC1 SC: ST Position             */\r
+#define HRPWM0_HRC1_SC_ST_Msk                 (0x01UL << HRPWM0_HRC1_SC_ST_Pos)                       /*!< HRPWM0_HRC1 SC: ST Mask                 */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_DCR  ------------------------------ */\r
+#define HRPWM0_HRC1_DCR_DTRV_Pos              0                                                       /*!< HRPWM0_HRC1 DCR: DTRV Position          */\r
+#define HRPWM0_HRC1_DCR_DTRV_Msk              (0x0000ffffUL << HRPWM0_HRC1_DCR_DTRV_Pos)              /*!< HRPWM0_HRC1 DCR: DTRV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_DCF  ------------------------------ */\r
+#define HRPWM0_HRC1_DCF_DTFV_Pos              0                                                       /*!< HRPWM0_HRC1 DCF: DTFV Position          */\r
+#define HRPWM0_HRC1_DCF_DTFV_Msk              (0x0000ffffUL << HRPWM0_HRC1_DCF_DTFV_Pos)              /*!< HRPWM0_HRC1 DCF: DTFV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_CR1  ------------------------------ */\r
+#define HRPWM0_HRC1_CR1_CR1_Pos               0                                                       /*!< HRPWM0_HRC1 CR1: CR1 Position           */\r
+#define HRPWM0_HRC1_CR1_CR1_Msk               (0x000000ffUL << HRPWM0_HRC1_CR1_CR1_Pos)               /*!< HRPWM0_HRC1 CR1: CR1 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_CR2  ------------------------------ */\r
+#define HRPWM0_HRC1_CR2_CR2_Pos               0                                                       /*!< HRPWM0_HRC1 CR2: CR2 Position           */\r
+#define HRPWM0_HRC1_CR2_CR2_Msk               (0x000000ffUL << HRPWM0_HRC1_CR2_CR2_Pos)               /*!< HRPWM0_HRC1 CR2: CR2 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC1_SSC  ------------------------------ */\r
+#define HRPWM0_HRC1_SSC_SST_Pos               0                                                       /*!< HRPWM0_HRC1 SSC: SST Position           */\r
+#define HRPWM0_HRC1_SSC_SST_Msk               (0x01UL << HRPWM0_HRC1_SSC_SST_Pos)                     /*!< HRPWM0_HRC1 SSC: SST Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_SDCR  ------------------------------ */\r
+#define HRPWM0_HRC1_SDCR_SDTRV_Pos            0                                                       /*!< HRPWM0_HRC1 SDCR: SDTRV Position        */\r
+#define HRPWM0_HRC1_SDCR_SDTRV_Msk            (0x0000ffffUL << HRPWM0_HRC1_SDCR_SDTRV_Pos)            /*!< HRPWM0_HRC1 SDCR: SDTRV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_SDCF  ------------------------------ */\r
+#define HRPWM0_HRC1_SDCF_SDTFV_Pos            0                                                       /*!< HRPWM0_HRC1 SDCF: SDTFV Position        */\r
+#define HRPWM0_HRC1_SDCF_SDTFV_Msk            (0x0000ffffUL << HRPWM0_HRC1_SDCF_SDTFV_Pos)            /*!< HRPWM0_HRC1 SDCF: SDTFV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_SCR1  ------------------------------ */\r
+#define HRPWM0_HRC1_SCR1_SCR1_Pos             0                                                       /*!< HRPWM0_HRC1 SCR1: SCR1 Position         */\r
+#define HRPWM0_HRC1_SCR1_SCR1_Msk             (0x000000ffUL << HRPWM0_HRC1_SCR1_SCR1_Pos)             /*!< HRPWM0_HRC1 SCR1: SCR1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC1_SCR2  ------------------------------ */\r
+#define HRPWM0_HRC1_SCR2_SCR2_Pos             0                                                       /*!< HRPWM0_HRC1 SCR2: SCR2 Position         */\r
+#define HRPWM0_HRC1_SCR2_SCR2_Msk             (0x000000ffUL << HRPWM0_HRC1_SCR2_SCR2_Pos)             /*!< HRPWM0_HRC1 SCR2: SCR2 Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_HRC2' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_HRC2_GC  ------------------------------- */\r
+#define HRPWM0_HRC2_GC_HRM0_Pos               0                                                       /*!< HRPWM0_HRC2 GC: HRM0 Position           */\r
+#define HRPWM0_HRC2_GC_HRM0_Msk               (0x03UL << HRPWM0_HRC2_GC_HRM0_Pos)                     /*!< HRPWM0_HRC2 GC: HRM0 Mask               */\r
+#define HRPWM0_HRC2_GC_HRM1_Pos               2                                                       /*!< HRPWM0_HRC2 GC: HRM1 Position           */\r
+#define HRPWM0_HRC2_GC_HRM1_Msk               (0x03UL << HRPWM0_HRC2_GC_HRM1_Pos)                     /*!< HRPWM0_HRC2 GC: HRM1 Mask               */\r
+#define HRPWM0_HRC2_GC_DTE_Pos                8                                                       /*!< HRPWM0_HRC2 GC: DTE Position            */\r
+#define HRPWM0_HRC2_GC_DTE_Msk                (0x01UL << HRPWM0_HRC2_GC_DTE_Pos)                      /*!< HRPWM0_HRC2 GC: DTE Mask                */\r
+#define HRPWM0_HRC2_GC_TR0E_Pos               9                                                       /*!< HRPWM0_HRC2 GC: TR0E Position           */\r
+#define HRPWM0_HRC2_GC_TR0E_Msk               (0x01UL << HRPWM0_HRC2_GC_TR0E_Pos)                     /*!< HRPWM0_HRC2 GC: TR0E Mask               */\r
+#define HRPWM0_HRC2_GC_TR1E_Pos               10                                                      /*!< HRPWM0_HRC2 GC: TR1E Position           */\r
+#define HRPWM0_HRC2_GC_TR1E_Msk               (0x01UL << HRPWM0_HRC2_GC_TR1E_Pos)                     /*!< HRPWM0_HRC2 GC: TR1E Mask               */\r
+#define HRPWM0_HRC2_GC_STC_Pos                11                                                      /*!< HRPWM0_HRC2 GC: STC Position            */\r
+#define HRPWM0_HRC2_GC_STC_Msk                (0x01UL << HRPWM0_HRC2_GC_STC_Pos)                      /*!< HRPWM0_HRC2 GC: STC Mask                */\r
+#define HRPWM0_HRC2_GC_DSTC_Pos               12                                                      /*!< HRPWM0_HRC2 GC: DSTC Position           */\r
+#define HRPWM0_HRC2_GC_DSTC_Msk               (0x01UL << HRPWM0_HRC2_GC_DSTC_Pos)                     /*!< HRPWM0_HRC2 GC: DSTC Mask               */\r
+#define HRPWM0_HRC2_GC_OCS0_Pos               13                                                      /*!< HRPWM0_HRC2 GC: OCS0 Position           */\r
+#define HRPWM0_HRC2_GC_OCS0_Msk               (0x01UL << HRPWM0_HRC2_GC_OCS0_Pos)                     /*!< HRPWM0_HRC2 GC: OCS0 Mask               */\r
+#define HRPWM0_HRC2_GC_OCS1_Pos               14                                                      /*!< HRPWM0_HRC2 GC: OCS1 Position           */\r
+#define HRPWM0_HRC2_GC_OCS1_Msk               (0x01UL << HRPWM0_HRC2_GC_OCS1_Pos)                     /*!< HRPWM0_HRC2 GC: OCS1 Mask               */\r
+#define HRPWM0_HRC2_GC_DTUS_Pos               16                                                      /*!< HRPWM0_HRC2 GC: DTUS Position           */\r
+#define HRPWM0_HRC2_GC_DTUS_Msk               (0x01UL << HRPWM0_HRC2_GC_DTUS_Pos)                     /*!< HRPWM0_HRC2 GC: DTUS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_PL  ------------------------------- */\r
+#define HRPWM0_HRC2_PL_PSL0_Pos               0                                                       /*!< HRPWM0_HRC2 PL: PSL0 Position           */\r
+#define HRPWM0_HRC2_PL_PSL0_Msk               (0x01UL << HRPWM0_HRC2_PL_PSL0_Pos)                     /*!< HRPWM0_HRC2 PL: PSL0 Mask               */\r
+#define HRPWM0_HRC2_PL_PSL1_Pos               1                                                       /*!< HRPWM0_HRC2 PL: PSL1 Position           */\r
+#define HRPWM0_HRC2_PL_PSL1_Msk               (0x01UL << HRPWM0_HRC2_PL_PSL1_Pos)                     /*!< HRPWM0_HRC2 PL: PSL1 Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_GSEL  ------------------------------ */\r
+#define HRPWM0_HRC2_GSEL_C0SS_Pos             0                                                       /*!< HRPWM0_HRC2 GSEL: C0SS Position         */\r
+#define HRPWM0_HRC2_GSEL_C0SS_Msk             (0x07UL << HRPWM0_HRC2_GSEL_C0SS_Pos)                   /*!< HRPWM0_HRC2 GSEL: C0SS Mask             */\r
+#define HRPWM0_HRC2_GSEL_C0CS_Pos             3                                                       /*!< HRPWM0_HRC2 GSEL: C0CS Position         */\r
+#define HRPWM0_HRC2_GSEL_C0CS_Msk             (0x07UL << HRPWM0_HRC2_GSEL_C0CS_Pos)                   /*!< HRPWM0_HRC2 GSEL: C0CS Mask             */\r
+#define HRPWM0_HRC2_GSEL_S0M_Pos              6                                                       /*!< HRPWM0_HRC2 GSEL: S0M Position          */\r
+#define HRPWM0_HRC2_GSEL_S0M_Msk              (0x03UL << HRPWM0_HRC2_GSEL_S0M_Pos)                    /*!< HRPWM0_HRC2 GSEL: S0M Mask              */\r
+#define HRPWM0_HRC2_GSEL_C0M_Pos              8                                                       /*!< HRPWM0_HRC2 GSEL: C0M Position          */\r
+#define HRPWM0_HRC2_GSEL_C0M_Msk              (0x03UL << HRPWM0_HRC2_GSEL_C0M_Pos)                    /*!< HRPWM0_HRC2 GSEL: C0M Mask              */\r
+#define HRPWM0_HRC2_GSEL_S0ES_Pos             10                                                      /*!< HRPWM0_HRC2 GSEL: S0ES Position         */\r
+#define HRPWM0_HRC2_GSEL_S0ES_Msk             (0x03UL << HRPWM0_HRC2_GSEL_S0ES_Pos)                   /*!< HRPWM0_HRC2 GSEL: S0ES Mask             */\r
+#define HRPWM0_HRC2_GSEL_C0ES_Pos             12                                                      /*!< HRPWM0_HRC2 GSEL: C0ES Position         */\r
+#define HRPWM0_HRC2_GSEL_C0ES_Msk             (0x03UL << HRPWM0_HRC2_GSEL_C0ES_Pos)                   /*!< HRPWM0_HRC2 GSEL: C0ES Mask             */\r
+#define HRPWM0_HRC2_GSEL_C1SS_Pos             16                                                      /*!< HRPWM0_HRC2 GSEL: C1SS Position         */\r
+#define HRPWM0_HRC2_GSEL_C1SS_Msk             (0x07UL << HRPWM0_HRC2_GSEL_C1SS_Pos)                   /*!< HRPWM0_HRC2 GSEL: C1SS Mask             */\r
+#define HRPWM0_HRC2_GSEL_C1CS_Pos             19                                                      /*!< HRPWM0_HRC2 GSEL: C1CS Position         */\r
+#define HRPWM0_HRC2_GSEL_C1CS_Msk             (0x07UL << HRPWM0_HRC2_GSEL_C1CS_Pos)                   /*!< HRPWM0_HRC2 GSEL: C1CS Mask             */\r
+#define HRPWM0_HRC2_GSEL_S1M_Pos              22                                                      /*!< HRPWM0_HRC2 GSEL: S1M Position          */\r
+#define HRPWM0_HRC2_GSEL_S1M_Msk              (0x03UL << HRPWM0_HRC2_GSEL_S1M_Pos)                    /*!< HRPWM0_HRC2 GSEL: S1M Mask              */\r
+#define HRPWM0_HRC2_GSEL_C1M_Pos              24                                                      /*!< HRPWM0_HRC2 GSEL: C1M Position          */\r
+#define HRPWM0_HRC2_GSEL_C1M_Msk              (0x03UL << HRPWM0_HRC2_GSEL_C1M_Pos)                    /*!< HRPWM0_HRC2 GSEL: C1M Mask              */\r
+#define HRPWM0_HRC2_GSEL_S1ES_Pos             26                                                      /*!< HRPWM0_HRC2 GSEL: S1ES Position         */\r
+#define HRPWM0_HRC2_GSEL_S1ES_Msk             (0x03UL << HRPWM0_HRC2_GSEL_S1ES_Pos)                   /*!< HRPWM0_HRC2 GSEL: S1ES Mask             */\r
+#define HRPWM0_HRC2_GSEL_C1ES_Pos             28                                                      /*!< HRPWM0_HRC2 GSEL: C1ES Position         */\r
+#define HRPWM0_HRC2_GSEL_C1ES_Msk             (0x03UL << HRPWM0_HRC2_GSEL_C1ES_Pos)                   /*!< HRPWM0_HRC2 GSEL: C1ES Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_TSEL  ------------------------------ */\r
+#define HRPWM0_HRC2_TSEL_TSEL0_Pos            0                                                       /*!< HRPWM0_HRC2 TSEL: TSEL0 Position        */\r
+#define HRPWM0_HRC2_TSEL_TSEL0_Msk            (0x07UL << HRPWM0_HRC2_TSEL_TSEL0_Pos)                  /*!< HRPWM0_HRC2 TSEL: TSEL0 Mask            */\r
+#define HRPWM0_HRC2_TSEL_TSEL1_Pos            3                                                       /*!< HRPWM0_HRC2 TSEL: TSEL1 Position        */\r
+#define HRPWM0_HRC2_TSEL_TSEL1_Msk            (0x07UL << HRPWM0_HRC2_TSEL_TSEL1_Pos)                  /*!< HRPWM0_HRC2 TSEL: TSEL1 Mask            */\r
+#define HRPWM0_HRC2_TSEL_TS0E_Pos             16                                                      /*!< HRPWM0_HRC2 TSEL: TS0E Position         */\r
+#define HRPWM0_HRC2_TSEL_TS0E_Msk             (0x01UL << HRPWM0_HRC2_TSEL_TS0E_Pos)                   /*!< HRPWM0_HRC2 TSEL: TS0E Mask             */\r
+#define HRPWM0_HRC2_TSEL_TS1E_Pos             17                                                      /*!< HRPWM0_HRC2 TSEL: TS1E Position         */\r
+#define HRPWM0_HRC2_TSEL_TS1E_Msk             (0x01UL << HRPWM0_HRC2_TSEL_TS1E_Pos)                   /*!< HRPWM0_HRC2 TSEL: TS1E Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_SC  ------------------------------- */\r
+#define HRPWM0_HRC2_SC_ST_Pos                 0                                                       /*!< HRPWM0_HRC2 SC: ST Position             */\r
+#define HRPWM0_HRC2_SC_ST_Msk                 (0x01UL << HRPWM0_HRC2_SC_ST_Pos)                       /*!< HRPWM0_HRC2 SC: ST Mask                 */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_DCR  ------------------------------ */\r
+#define HRPWM0_HRC2_DCR_DTRV_Pos              0                                                       /*!< HRPWM0_HRC2 DCR: DTRV Position          */\r
+#define HRPWM0_HRC2_DCR_DTRV_Msk              (0x0000ffffUL << HRPWM0_HRC2_DCR_DTRV_Pos)              /*!< HRPWM0_HRC2 DCR: DTRV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_DCF  ------------------------------ */\r
+#define HRPWM0_HRC2_DCF_DTFV_Pos              0                                                       /*!< HRPWM0_HRC2 DCF: DTFV Position          */\r
+#define HRPWM0_HRC2_DCF_DTFV_Msk              (0x0000ffffUL << HRPWM0_HRC2_DCF_DTFV_Pos)              /*!< HRPWM0_HRC2 DCF: DTFV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_CR1  ------------------------------ */\r
+#define HRPWM0_HRC2_CR1_CR1_Pos               0                                                       /*!< HRPWM0_HRC2 CR1: CR1 Position           */\r
+#define HRPWM0_HRC2_CR1_CR1_Msk               (0x000000ffUL << HRPWM0_HRC2_CR1_CR1_Pos)               /*!< HRPWM0_HRC2 CR1: CR1 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_CR2  ------------------------------ */\r
+#define HRPWM0_HRC2_CR2_CR2_Pos               0                                                       /*!< HRPWM0_HRC2 CR2: CR2 Position           */\r
+#define HRPWM0_HRC2_CR2_CR2_Msk               (0x000000ffUL << HRPWM0_HRC2_CR2_CR2_Pos)               /*!< HRPWM0_HRC2 CR2: CR2 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC2_SSC  ------------------------------ */\r
+#define HRPWM0_HRC2_SSC_SST_Pos               0                                                       /*!< HRPWM0_HRC2 SSC: SST Position           */\r
+#define HRPWM0_HRC2_SSC_SST_Msk               (0x01UL << HRPWM0_HRC2_SSC_SST_Pos)                     /*!< HRPWM0_HRC2 SSC: SST Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_SDCR  ------------------------------ */\r
+#define HRPWM0_HRC2_SDCR_SDTRV_Pos            0                                                       /*!< HRPWM0_HRC2 SDCR: SDTRV Position        */\r
+#define HRPWM0_HRC2_SDCR_SDTRV_Msk            (0x0000ffffUL << HRPWM0_HRC2_SDCR_SDTRV_Pos)            /*!< HRPWM0_HRC2 SDCR: SDTRV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_SDCF  ------------------------------ */\r
+#define HRPWM0_HRC2_SDCF_SDTFV_Pos            0                                                       /*!< HRPWM0_HRC2 SDCF: SDTFV Position        */\r
+#define HRPWM0_HRC2_SDCF_SDTFV_Msk            (0x0000ffffUL << HRPWM0_HRC2_SDCF_SDTFV_Pos)            /*!< HRPWM0_HRC2 SDCF: SDTFV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_SCR1  ------------------------------ */\r
+#define HRPWM0_HRC2_SCR1_SCR1_Pos             0                                                       /*!< HRPWM0_HRC2 SCR1: SCR1 Position         */\r
+#define HRPWM0_HRC2_SCR1_SCR1_Msk             (0x000000ffUL << HRPWM0_HRC2_SCR1_SCR1_Pos)             /*!< HRPWM0_HRC2 SCR1: SCR1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC2_SCR2  ------------------------------ */\r
+#define HRPWM0_HRC2_SCR2_SCR2_Pos             0                                                       /*!< HRPWM0_HRC2 SCR2: SCR2 Position         */\r
+#define HRPWM0_HRC2_SCR2_SCR2_Msk             (0x000000ffUL << HRPWM0_HRC2_SCR2_SCR2_Pos)             /*!< HRPWM0_HRC2 SCR2: SCR2 Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'HRPWM0_HRC3' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  HRPWM0_HRC3_GC  ------------------------------- */\r
+#define HRPWM0_HRC3_GC_HRM0_Pos               0                                                       /*!< HRPWM0_HRC3 GC: HRM0 Position           */\r
+#define HRPWM0_HRC3_GC_HRM0_Msk               (0x03UL << HRPWM0_HRC3_GC_HRM0_Pos)                     /*!< HRPWM0_HRC3 GC: HRM0 Mask               */\r
+#define HRPWM0_HRC3_GC_HRM1_Pos               2                                                       /*!< HRPWM0_HRC3 GC: HRM1 Position           */\r
+#define HRPWM0_HRC3_GC_HRM1_Msk               (0x03UL << HRPWM0_HRC3_GC_HRM1_Pos)                     /*!< HRPWM0_HRC3 GC: HRM1 Mask               */\r
+#define HRPWM0_HRC3_GC_DTE_Pos                8                                                       /*!< HRPWM0_HRC3 GC: DTE Position            */\r
+#define HRPWM0_HRC3_GC_DTE_Msk                (0x01UL << HRPWM0_HRC3_GC_DTE_Pos)                      /*!< HRPWM0_HRC3 GC: DTE Mask                */\r
+#define HRPWM0_HRC3_GC_TR0E_Pos               9                                                       /*!< HRPWM0_HRC3 GC: TR0E Position           */\r
+#define HRPWM0_HRC3_GC_TR0E_Msk               (0x01UL << HRPWM0_HRC3_GC_TR0E_Pos)                     /*!< HRPWM0_HRC3 GC: TR0E Mask               */\r
+#define HRPWM0_HRC3_GC_TR1E_Pos               10                                                      /*!< HRPWM0_HRC3 GC: TR1E Position           */\r
+#define HRPWM0_HRC3_GC_TR1E_Msk               (0x01UL << HRPWM0_HRC3_GC_TR1E_Pos)                     /*!< HRPWM0_HRC3 GC: TR1E Mask               */\r
+#define HRPWM0_HRC3_GC_STC_Pos                11                                                      /*!< HRPWM0_HRC3 GC: STC Position            */\r
+#define HRPWM0_HRC3_GC_STC_Msk                (0x01UL << HRPWM0_HRC3_GC_STC_Pos)                      /*!< HRPWM0_HRC3 GC: STC Mask                */\r
+#define HRPWM0_HRC3_GC_DSTC_Pos               12                                                      /*!< HRPWM0_HRC3 GC: DSTC Position           */\r
+#define HRPWM0_HRC3_GC_DSTC_Msk               (0x01UL << HRPWM0_HRC3_GC_DSTC_Pos)                     /*!< HRPWM0_HRC3 GC: DSTC Mask               */\r
+#define HRPWM0_HRC3_GC_OCS0_Pos               13                                                      /*!< HRPWM0_HRC3 GC: OCS0 Position           */\r
+#define HRPWM0_HRC3_GC_OCS0_Msk               (0x01UL << HRPWM0_HRC3_GC_OCS0_Pos)                     /*!< HRPWM0_HRC3 GC: OCS0 Mask               */\r
+#define HRPWM0_HRC3_GC_OCS1_Pos               14                                                      /*!< HRPWM0_HRC3 GC: OCS1 Position           */\r
+#define HRPWM0_HRC3_GC_OCS1_Msk               (0x01UL << HRPWM0_HRC3_GC_OCS1_Pos)                     /*!< HRPWM0_HRC3 GC: OCS1 Mask               */\r
+#define HRPWM0_HRC3_GC_DTUS_Pos               16                                                      /*!< HRPWM0_HRC3 GC: DTUS Position           */\r
+#define HRPWM0_HRC3_GC_DTUS_Msk               (0x01UL << HRPWM0_HRC3_GC_DTUS_Pos)                     /*!< HRPWM0_HRC3 GC: DTUS Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_PL  ------------------------------- */\r
+#define HRPWM0_HRC3_PL_PSL0_Pos               0                                                       /*!< HRPWM0_HRC3 PL: PSL0 Position           */\r
+#define HRPWM0_HRC3_PL_PSL0_Msk               (0x01UL << HRPWM0_HRC3_PL_PSL0_Pos)                     /*!< HRPWM0_HRC3 PL: PSL0 Mask               */\r
+#define HRPWM0_HRC3_PL_PSL1_Pos               1                                                       /*!< HRPWM0_HRC3 PL: PSL1 Position           */\r
+#define HRPWM0_HRC3_PL_PSL1_Msk               (0x01UL << HRPWM0_HRC3_PL_PSL1_Pos)                     /*!< HRPWM0_HRC3 PL: PSL1 Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_GSEL  ------------------------------ */\r
+#define HRPWM0_HRC3_GSEL_C0SS_Pos             0                                                       /*!< HRPWM0_HRC3 GSEL: C0SS Position         */\r
+#define HRPWM0_HRC3_GSEL_C0SS_Msk             (0x07UL << HRPWM0_HRC3_GSEL_C0SS_Pos)                   /*!< HRPWM0_HRC3 GSEL: C0SS Mask             */\r
+#define HRPWM0_HRC3_GSEL_C0CS_Pos             3                                                       /*!< HRPWM0_HRC3 GSEL: C0CS Position         */\r
+#define HRPWM0_HRC3_GSEL_C0CS_Msk             (0x07UL << HRPWM0_HRC3_GSEL_C0CS_Pos)                   /*!< HRPWM0_HRC3 GSEL: C0CS Mask             */\r
+#define HRPWM0_HRC3_GSEL_S0M_Pos              6                                                       /*!< HRPWM0_HRC3 GSEL: S0M Position          */\r
+#define HRPWM0_HRC3_GSEL_S0M_Msk              (0x03UL << HRPWM0_HRC3_GSEL_S0M_Pos)                    /*!< HRPWM0_HRC3 GSEL: S0M Mask              */\r
+#define HRPWM0_HRC3_GSEL_C0M_Pos              8                                                       /*!< HRPWM0_HRC3 GSEL: C0M Position          */\r
+#define HRPWM0_HRC3_GSEL_C0M_Msk              (0x03UL << HRPWM0_HRC3_GSEL_C0M_Pos)                    /*!< HRPWM0_HRC3 GSEL: C0M Mask              */\r
+#define HRPWM0_HRC3_GSEL_S0ES_Pos             10                                                      /*!< HRPWM0_HRC3 GSEL: S0ES Position         */\r
+#define HRPWM0_HRC3_GSEL_S0ES_Msk             (0x03UL << HRPWM0_HRC3_GSEL_S0ES_Pos)                   /*!< HRPWM0_HRC3 GSEL: S0ES Mask             */\r
+#define HRPWM0_HRC3_GSEL_C0ES_Pos             12                                                      /*!< HRPWM0_HRC3 GSEL: C0ES Position         */\r
+#define HRPWM0_HRC3_GSEL_C0ES_Msk             (0x03UL << HRPWM0_HRC3_GSEL_C0ES_Pos)                   /*!< HRPWM0_HRC3 GSEL: C0ES Mask             */\r
+#define HRPWM0_HRC3_GSEL_C1SS_Pos             16                                                      /*!< HRPWM0_HRC3 GSEL: C1SS Position         */\r
+#define HRPWM0_HRC3_GSEL_C1SS_Msk             (0x07UL << HRPWM0_HRC3_GSEL_C1SS_Pos)                   /*!< HRPWM0_HRC3 GSEL: C1SS Mask             */\r
+#define HRPWM0_HRC3_GSEL_C1CS_Pos             19                                                      /*!< HRPWM0_HRC3 GSEL: C1CS Position         */\r
+#define HRPWM0_HRC3_GSEL_C1CS_Msk             (0x07UL << HRPWM0_HRC3_GSEL_C1CS_Pos)                   /*!< HRPWM0_HRC3 GSEL: C1CS Mask             */\r
+#define HRPWM0_HRC3_GSEL_S1M_Pos              22                                                      /*!< HRPWM0_HRC3 GSEL: S1M Position          */\r
+#define HRPWM0_HRC3_GSEL_S1M_Msk              (0x03UL << HRPWM0_HRC3_GSEL_S1M_Pos)                    /*!< HRPWM0_HRC3 GSEL: S1M Mask              */\r
+#define HRPWM0_HRC3_GSEL_C1M_Pos              24                                                      /*!< HRPWM0_HRC3 GSEL: C1M Position          */\r
+#define HRPWM0_HRC3_GSEL_C1M_Msk              (0x03UL << HRPWM0_HRC3_GSEL_C1M_Pos)                    /*!< HRPWM0_HRC3 GSEL: C1M Mask              */\r
+#define HRPWM0_HRC3_GSEL_S1ES_Pos             26                                                      /*!< HRPWM0_HRC3 GSEL: S1ES Position         */\r
+#define HRPWM0_HRC3_GSEL_S1ES_Msk             (0x03UL << HRPWM0_HRC3_GSEL_S1ES_Pos)                   /*!< HRPWM0_HRC3 GSEL: S1ES Mask             */\r
+#define HRPWM0_HRC3_GSEL_C1ES_Pos             28                                                      /*!< HRPWM0_HRC3 GSEL: C1ES Position         */\r
+#define HRPWM0_HRC3_GSEL_C1ES_Msk             (0x03UL << HRPWM0_HRC3_GSEL_C1ES_Pos)                   /*!< HRPWM0_HRC3 GSEL: C1ES Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_TSEL  ------------------------------ */\r
+#define HRPWM0_HRC3_TSEL_TSEL0_Pos            0                                                       /*!< HRPWM0_HRC3 TSEL: TSEL0 Position        */\r
+#define HRPWM0_HRC3_TSEL_TSEL0_Msk            (0x07UL << HRPWM0_HRC3_TSEL_TSEL0_Pos)                  /*!< HRPWM0_HRC3 TSEL: TSEL0 Mask            */\r
+#define HRPWM0_HRC3_TSEL_TSEL1_Pos            3                                                       /*!< HRPWM0_HRC3 TSEL: TSEL1 Position        */\r
+#define HRPWM0_HRC3_TSEL_TSEL1_Msk            (0x07UL << HRPWM0_HRC3_TSEL_TSEL1_Pos)                  /*!< HRPWM0_HRC3 TSEL: TSEL1 Mask            */\r
+#define HRPWM0_HRC3_TSEL_TS0E_Pos             16                                                      /*!< HRPWM0_HRC3 TSEL: TS0E Position         */\r
+#define HRPWM0_HRC3_TSEL_TS0E_Msk             (0x01UL << HRPWM0_HRC3_TSEL_TS0E_Pos)                   /*!< HRPWM0_HRC3 TSEL: TS0E Mask             */\r
+#define HRPWM0_HRC3_TSEL_TS1E_Pos             17                                                      /*!< HRPWM0_HRC3 TSEL: TS1E Position         */\r
+#define HRPWM0_HRC3_TSEL_TS1E_Msk             (0x01UL << HRPWM0_HRC3_TSEL_TS1E_Pos)                   /*!< HRPWM0_HRC3 TSEL: TS1E Mask             */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_SC  ------------------------------- */\r
+#define HRPWM0_HRC3_SC_ST_Pos                 0                                                       /*!< HRPWM0_HRC3 SC: ST Position             */\r
+#define HRPWM0_HRC3_SC_ST_Msk                 (0x01UL << HRPWM0_HRC3_SC_ST_Pos)                       /*!< HRPWM0_HRC3 SC: ST Mask                 */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_DCR  ------------------------------ */\r
+#define HRPWM0_HRC3_DCR_DTRV_Pos              0                                                       /*!< HRPWM0_HRC3 DCR: DTRV Position          */\r
+#define HRPWM0_HRC3_DCR_DTRV_Msk              (0x0000ffffUL << HRPWM0_HRC3_DCR_DTRV_Pos)              /*!< HRPWM0_HRC3 DCR: DTRV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_DCF  ------------------------------ */\r
+#define HRPWM0_HRC3_DCF_DTFV_Pos              0                                                       /*!< HRPWM0_HRC3 DCF: DTFV Position          */\r
+#define HRPWM0_HRC3_DCF_DTFV_Msk              (0x0000ffffUL << HRPWM0_HRC3_DCF_DTFV_Pos)              /*!< HRPWM0_HRC3 DCF: DTFV Mask              */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_CR1  ------------------------------ */\r
+#define HRPWM0_HRC3_CR1_CR1_Pos               0                                                       /*!< HRPWM0_HRC3 CR1: CR1 Position           */\r
+#define HRPWM0_HRC3_CR1_CR1_Msk               (0x000000ffUL << HRPWM0_HRC3_CR1_CR1_Pos)               /*!< HRPWM0_HRC3 CR1: CR1 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_CR2  ------------------------------ */\r
+#define HRPWM0_HRC3_CR2_CR2_Pos               0                                                       /*!< HRPWM0_HRC3 CR2: CR2 Position           */\r
+#define HRPWM0_HRC3_CR2_CR2_Msk               (0x000000ffUL << HRPWM0_HRC3_CR2_CR2_Pos)               /*!< HRPWM0_HRC3 CR2: CR2 Mask               */\r
+\r
+/* -------------------------------  HRPWM0_HRC3_SSC  ------------------------------ */\r
+#define HRPWM0_HRC3_SSC_SST_Pos               0                                                       /*!< HRPWM0_HRC3 SSC: SST Position           */\r
+#define HRPWM0_HRC3_SSC_SST_Msk               (0x01UL << HRPWM0_HRC3_SSC_SST_Pos)                     /*!< HRPWM0_HRC3 SSC: SST Mask               */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_SDCR  ------------------------------ */\r
+#define HRPWM0_HRC3_SDCR_SDTRV_Pos            0                                                       /*!< HRPWM0_HRC3 SDCR: SDTRV Position        */\r
+#define HRPWM0_HRC3_SDCR_SDTRV_Msk            (0x0000ffffUL << HRPWM0_HRC3_SDCR_SDTRV_Pos)            /*!< HRPWM0_HRC3 SDCR: SDTRV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_SDCF  ------------------------------ */\r
+#define HRPWM0_HRC3_SDCF_SDTFV_Pos            0                                                       /*!< HRPWM0_HRC3 SDCF: SDTFV Position        */\r
+#define HRPWM0_HRC3_SDCF_SDTFV_Msk            (0x0000ffffUL << HRPWM0_HRC3_SDCF_SDTFV_Pos)            /*!< HRPWM0_HRC3 SDCF: SDTFV Mask            */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_SCR1  ------------------------------ */\r
+#define HRPWM0_HRC3_SCR1_SCR1_Pos             0                                                       /*!< HRPWM0_HRC3 SCR1: SCR1 Position         */\r
+#define HRPWM0_HRC3_SCR1_SCR1_Msk             (0x000000ffUL << HRPWM0_HRC3_SCR1_SCR1_Pos)             /*!< HRPWM0_HRC3 SCR1: SCR1 Mask             */\r
+\r
+/* ------------------------------  HRPWM0_HRC3_SCR2  ------------------------------ */\r
+#define HRPWM0_HRC3_SCR2_SCR2_Pos             0                                                       /*!< HRPWM0_HRC3 SCR2: SCR2 Position         */\r
+#define HRPWM0_HRC3_SCR2_SCR2_Msk             (0x000000ffUL << HRPWM0_HRC3_SCR2_SCR2_Pos)             /*!< HRPWM0_HRC3 SCR2: SCR2 Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'POSIF' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  POSIF_PCONF  -------------------------------- */\r
+#define POSIF_PCONF_FSEL_Pos                  0                                                       /*!< POSIF PCONF: FSEL Position              */\r
+#define POSIF_PCONF_FSEL_Msk                  (0x03UL << POSIF_PCONF_FSEL_Pos)                        /*!< POSIF PCONF: FSEL Mask                  */\r
+#define POSIF_PCONF_QDCM_Pos                  2                                                       /*!< POSIF PCONF: QDCM Position              */\r
+#define POSIF_PCONF_QDCM_Msk                  (0x01UL << POSIF_PCONF_QDCM_Pos)                        /*!< POSIF PCONF: QDCM Mask                  */\r
+#define POSIF_PCONF_HIDG_Pos                  4                                                       /*!< POSIF PCONF: HIDG Position              */\r
+#define POSIF_PCONF_HIDG_Msk                  (0x01UL << POSIF_PCONF_HIDG_Pos)                        /*!< POSIF PCONF: HIDG Mask                  */\r
+#define POSIF_PCONF_MCUE_Pos                  5                                                       /*!< POSIF PCONF: MCUE Position              */\r
+#define POSIF_PCONF_MCUE_Msk                  (0x01UL << POSIF_PCONF_MCUE_Pos)                        /*!< POSIF PCONF: MCUE Mask                  */\r
+#define POSIF_PCONF_INSEL0_Pos                8                                                       /*!< POSIF PCONF: INSEL0 Position            */\r
+#define POSIF_PCONF_INSEL0_Msk                (0x03UL << POSIF_PCONF_INSEL0_Pos)                      /*!< POSIF PCONF: INSEL0 Mask                */\r
+#define POSIF_PCONF_INSEL1_Pos                10                                                      /*!< POSIF PCONF: INSEL1 Position            */\r
+#define POSIF_PCONF_INSEL1_Msk                (0x03UL << POSIF_PCONF_INSEL1_Pos)                      /*!< POSIF PCONF: INSEL1 Mask                */\r
+#define POSIF_PCONF_INSEL2_Pos                12                                                      /*!< POSIF PCONF: INSEL2 Position            */\r
+#define POSIF_PCONF_INSEL2_Msk                (0x03UL << POSIF_PCONF_INSEL2_Pos)                      /*!< POSIF PCONF: INSEL2 Mask                */\r
+#define POSIF_PCONF_DSEL_Pos                  16                                                      /*!< POSIF PCONF: DSEL Position              */\r
+#define POSIF_PCONF_DSEL_Msk                  (0x01UL << POSIF_PCONF_DSEL_Pos)                        /*!< POSIF PCONF: DSEL Mask                  */\r
+#define POSIF_PCONF_SPES_Pos                  17                                                      /*!< POSIF PCONF: SPES Position              */\r
+#define POSIF_PCONF_SPES_Msk                  (0x01UL << POSIF_PCONF_SPES_Pos)                        /*!< POSIF PCONF: SPES Mask                  */\r
+#define POSIF_PCONF_MSETS_Pos                 18                                                      /*!< POSIF PCONF: MSETS Position             */\r
+#define POSIF_PCONF_MSETS_Msk                 (0x07UL << POSIF_PCONF_MSETS_Pos)                       /*!< POSIF PCONF: MSETS Mask                 */\r
+#define POSIF_PCONF_MSES_Pos                  21                                                      /*!< POSIF PCONF: MSES Position              */\r
+#define POSIF_PCONF_MSES_Msk                  (0x01UL << POSIF_PCONF_MSES_Pos)                        /*!< POSIF PCONF: MSES Mask                  */\r
+#define POSIF_PCONF_MSYNS_Pos                 22                                                      /*!< POSIF PCONF: MSYNS Position             */\r
+#define POSIF_PCONF_MSYNS_Msk                 (0x03UL << POSIF_PCONF_MSYNS_Pos)                       /*!< POSIF PCONF: MSYNS Mask                 */\r
+#define POSIF_PCONF_EWIS_Pos                  24                                                      /*!< POSIF PCONF: EWIS Position              */\r
+#define POSIF_PCONF_EWIS_Msk                  (0x03UL << POSIF_PCONF_EWIS_Pos)                        /*!< POSIF PCONF: EWIS Mask                  */\r
+#define POSIF_PCONF_EWIE_Pos                  26                                                      /*!< POSIF PCONF: EWIE Position              */\r
+#define POSIF_PCONF_EWIE_Msk                  (0x01UL << POSIF_PCONF_EWIE_Pos)                        /*!< POSIF PCONF: EWIE Mask                  */\r
+#define POSIF_PCONF_EWIL_Pos                  27                                                      /*!< POSIF PCONF: EWIL Position              */\r
+#define POSIF_PCONF_EWIL_Msk                  (0x01UL << POSIF_PCONF_EWIL_Pos)                        /*!< POSIF PCONF: EWIL Mask                  */\r
+#define POSIF_PCONF_LPC_Pos                   28                                                      /*!< POSIF PCONF: LPC Position               */\r
+#define POSIF_PCONF_LPC_Msk                   (0x07UL << POSIF_PCONF_LPC_Pos)                         /*!< POSIF PCONF: LPC Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PSUS  --------------------------------- */\r
+#define POSIF_PSUS_QSUS_Pos                   0                                                       /*!< POSIF PSUS: QSUS Position               */\r
+#define POSIF_PSUS_QSUS_Msk                   (0x03UL << POSIF_PSUS_QSUS_Pos)                         /*!< POSIF PSUS: QSUS Mask                   */\r
+#define POSIF_PSUS_MSUS_Pos                   2                                                       /*!< POSIF PSUS: MSUS Position               */\r
+#define POSIF_PSUS_MSUS_Msk                   (0x03UL << POSIF_PSUS_MSUS_Pos)                         /*!< POSIF PSUS: MSUS Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PRUNS  -------------------------------- */\r
+#define POSIF_PRUNS_SRB_Pos                   0                                                       /*!< POSIF PRUNS: SRB Position               */\r
+#define POSIF_PRUNS_SRB_Msk                   (0x01UL << POSIF_PRUNS_SRB_Pos)                         /*!< POSIF PRUNS: SRB Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PRUNC  -------------------------------- */\r
+#define POSIF_PRUNC_CRB_Pos                   0                                                       /*!< POSIF PRUNC: CRB Position               */\r
+#define POSIF_PRUNC_CRB_Msk                   (0x01UL << POSIF_PRUNC_CRB_Pos)                         /*!< POSIF PRUNC: CRB Mask                   */\r
+#define POSIF_PRUNC_CSM_Pos                   1                                                       /*!< POSIF PRUNC: CSM Position               */\r
+#define POSIF_PRUNC_CSM_Msk                   (0x01UL << POSIF_PRUNC_CSM_Pos)                         /*!< POSIF PRUNC: CSM Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PRUN  --------------------------------- */\r
+#define POSIF_PRUN_RB_Pos                     0                                                       /*!< POSIF PRUN: RB Position                 */\r
+#define POSIF_PRUN_RB_Msk                     (0x01UL << POSIF_PRUN_RB_Pos)                           /*!< POSIF PRUN: RB Mask                     */\r
+\r
+/* ---------------------------------  POSIF_MIDR  --------------------------------- */\r
+#define POSIF_MIDR_MODR_Pos                   0                                                       /*!< POSIF MIDR: MODR Position               */\r
+#define POSIF_MIDR_MODR_Msk                   (0x000000ffUL << POSIF_MIDR_MODR_Pos)                   /*!< POSIF MIDR: MODR Mask                   */\r
+#define POSIF_MIDR_MODT_Pos                   8                                                       /*!< POSIF MIDR: MODT Position               */\r
+#define POSIF_MIDR_MODT_Msk                   (0x000000ffUL << POSIF_MIDR_MODT_Pos)                   /*!< POSIF MIDR: MODT Mask                   */\r
+#define POSIF_MIDR_MODN_Pos                   16                                                      /*!< POSIF MIDR: MODN Position               */\r
+#define POSIF_MIDR_MODN_Msk                   (0x0000ffffUL << POSIF_MIDR_MODN_Pos)                   /*!< POSIF MIDR: MODN Mask                   */\r
+\r
+/* ---------------------------------  POSIF_HALP  --------------------------------- */\r
+#define POSIF_HALP_HCP_Pos                    0                                                       /*!< POSIF HALP: HCP Position                */\r
+#define POSIF_HALP_HCP_Msk                    (0x07UL << POSIF_HALP_HCP_Pos)                          /*!< POSIF HALP: HCP Mask                    */\r
+#define POSIF_HALP_HEP_Pos                    3                                                       /*!< POSIF HALP: HEP Position                */\r
+#define POSIF_HALP_HEP_Msk                    (0x07UL << POSIF_HALP_HEP_Pos)                          /*!< POSIF HALP: HEP Mask                    */\r
+\r
+/* ---------------------------------  POSIF_HALPS  -------------------------------- */\r
+#define POSIF_HALPS_HCPS_Pos                  0                                                       /*!< POSIF HALPS: HCPS Position              */\r
+#define POSIF_HALPS_HCPS_Msk                  (0x07UL << POSIF_HALPS_HCPS_Pos)                        /*!< POSIF HALPS: HCPS Mask                  */\r
+#define POSIF_HALPS_HEPS_Pos                  3                                                       /*!< POSIF HALPS: HEPS Position              */\r
+#define POSIF_HALPS_HEPS_Msk                  (0x07UL << POSIF_HALPS_HEPS_Pos)                        /*!< POSIF HALPS: HEPS Mask                  */\r
+\r
+/* ----------------------------------  POSIF_MCM  --------------------------------- */\r
+#define POSIF_MCM_MCMP_Pos                    0                                                       /*!< POSIF MCM: MCMP Position                */\r
+#define POSIF_MCM_MCMP_Msk                    (0x0000ffffUL << POSIF_MCM_MCMP_Pos)                    /*!< POSIF MCM: MCMP Mask                    */\r
+\r
+/* ---------------------------------  POSIF_MCSM  --------------------------------- */\r
+#define POSIF_MCSM_MCMPS_Pos                  0                                                       /*!< POSIF MCSM: MCMPS Position              */\r
+#define POSIF_MCSM_MCMPS_Msk                  (0x0000ffffUL << POSIF_MCSM_MCMPS_Pos)                  /*!< POSIF MCSM: MCMPS Mask                  */\r
+\r
+/* ---------------------------------  POSIF_MCMS  --------------------------------- */\r
+#define POSIF_MCMS_MNPS_Pos                   0                                                       /*!< POSIF MCMS: MNPS Position               */\r
+#define POSIF_MCMS_MNPS_Msk                   (0x01UL << POSIF_MCMS_MNPS_Pos)                         /*!< POSIF MCMS: MNPS Mask                   */\r
+#define POSIF_MCMS_STHR_Pos                   1                                                       /*!< POSIF MCMS: STHR Position               */\r
+#define POSIF_MCMS_STHR_Msk                   (0x01UL << POSIF_MCMS_STHR_Pos)                         /*!< POSIF MCMS: STHR Mask                   */\r
+#define POSIF_MCMS_STMR_Pos                   2                                                       /*!< POSIF MCMS: STMR Position               */\r
+#define POSIF_MCMS_STMR_Msk                   (0x01UL << POSIF_MCMS_STMR_Pos)                         /*!< POSIF MCMS: STMR Mask                   */\r
+\r
+/* ---------------------------------  POSIF_MCMC  --------------------------------- */\r
+#define POSIF_MCMC_MNPC_Pos                   0                                                       /*!< POSIF MCMC: MNPC Position               */\r
+#define POSIF_MCMC_MNPC_Msk                   (0x01UL << POSIF_MCMC_MNPC_Pos)                         /*!< POSIF MCMC: MNPC Mask                   */\r
+#define POSIF_MCMC_MPC_Pos                    1                                                       /*!< POSIF MCMC: MPC Position                */\r
+#define POSIF_MCMC_MPC_Msk                    (0x01UL << POSIF_MCMC_MPC_Pos)                          /*!< POSIF MCMC: MPC Mask                    */\r
+\r
+/* ---------------------------------  POSIF_MCMF  --------------------------------- */\r
+#define POSIF_MCMF_MSS_Pos                    0                                                       /*!< POSIF MCMF: MSS Position                */\r
+#define POSIF_MCMF_MSS_Msk                    (0x01UL << POSIF_MCMF_MSS_Pos)                          /*!< POSIF MCMF: MSS Mask                    */\r
+\r
+/* ----------------------------------  POSIF_QDC  --------------------------------- */\r
+#define POSIF_QDC_PALS_Pos                    0                                                       /*!< POSIF QDC: PALS Position                */\r
+#define POSIF_QDC_PALS_Msk                    (0x01UL << POSIF_QDC_PALS_Pos)                          /*!< POSIF QDC: PALS Mask                    */\r
+#define POSIF_QDC_PBLS_Pos                    1                                                       /*!< POSIF QDC: PBLS Position                */\r
+#define POSIF_QDC_PBLS_Msk                    (0x01UL << POSIF_QDC_PBLS_Pos)                          /*!< POSIF QDC: PBLS Mask                    */\r
+#define POSIF_QDC_PHS_Pos                     2                                                       /*!< POSIF QDC: PHS Position                 */\r
+#define POSIF_QDC_PHS_Msk                     (0x01UL << POSIF_QDC_PHS_Pos)                           /*!< POSIF QDC: PHS Mask                     */\r
+#define POSIF_QDC_ICM_Pos                     4                                                       /*!< POSIF QDC: ICM Position                 */\r
+#define POSIF_QDC_ICM_Msk                     (0x03UL << POSIF_QDC_ICM_Pos)                           /*!< POSIF QDC: ICM Mask                     */\r
+#define POSIF_QDC_DVAL_Pos                    8                                                       /*!< POSIF QDC: DVAL Position                */\r
+#define POSIF_QDC_DVAL_Msk                    (0x01UL << POSIF_QDC_DVAL_Pos)                          /*!< POSIF QDC: DVAL Mask                    */\r
+\r
+/* ---------------------------------  POSIF_PFLG  --------------------------------- */\r
+#define POSIF_PFLG_CHES_Pos                   0                                                       /*!< POSIF PFLG: CHES Position               */\r
+#define POSIF_PFLG_CHES_Msk                   (0x01UL << POSIF_PFLG_CHES_Pos)                         /*!< POSIF PFLG: CHES Mask                   */\r
+#define POSIF_PFLG_WHES_Pos                   1                                                       /*!< POSIF PFLG: WHES Position               */\r
+#define POSIF_PFLG_WHES_Msk                   (0x01UL << POSIF_PFLG_WHES_Pos)                         /*!< POSIF PFLG: WHES Mask                   */\r
+#define POSIF_PFLG_HIES_Pos                   2                                                       /*!< POSIF PFLG: HIES Position               */\r
+#define POSIF_PFLG_HIES_Msk                   (0x01UL << POSIF_PFLG_HIES_Pos)                         /*!< POSIF PFLG: HIES Mask                   */\r
+#define POSIF_PFLG_MSTS_Pos                   4                                                       /*!< POSIF PFLG: MSTS Position               */\r
+#define POSIF_PFLG_MSTS_Msk                   (0x01UL << POSIF_PFLG_MSTS_Pos)                         /*!< POSIF PFLG: MSTS Mask                   */\r
+#define POSIF_PFLG_INDXS_Pos                  8                                                       /*!< POSIF PFLG: INDXS Position              */\r
+#define POSIF_PFLG_INDXS_Msk                  (0x01UL << POSIF_PFLG_INDXS_Pos)                        /*!< POSIF PFLG: INDXS Mask                  */\r
+#define POSIF_PFLG_ERRS_Pos                   9                                                       /*!< POSIF PFLG: ERRS Position               */\r
+#define POSIF_PFLG_ERRS_Msk                   (0x01UL << POSIF_PFLG_ERRS_Pos)                         /*!< POSIF PFLG: ERRS Mask                   */\r
+#define POSIF_PFLG_CNTS_Pos                   10                                                      /*!< POSIF PFLG: CNTS Position               */\r
+#define POSIF_PFLG_CNTS_Msk                   (0x01UL << POSIF_PFLG_CNTS_Pos)                         /*!< POSIF PFLG: CNTS Mask                   */\r
+#define POSIF_PFLG_DIRS_Pos                   11                                                      /*!< POSIF PFLG: DIRS Position               */\r
+#define POSIF_PFLG_DIRS_Msk                   (0x01UL << POSIF_PFLG_DIRS_Pos)                         /*!< POSIF PFLG: DIRS Mask                   */\r
+#define POSIF_PFLG_PCLKS_Pos                  12                                                      /*!< POSIF PFLG: PCLKS Position              */\r
+#define POSIF_PFLG_PCLKS_Msk                  (0x01UL << POSIF_PFLG_PCLKS_Pos)                        /*!< POSIF PFLG: PCLKS Mask                  */\r
+\r
+/* ---------------------------------  POSIF_PFLGE  -------------------------------- */\r
+#define POSIF_PFLGE_ECHE_Pos                  0                                                       /*!< POSIF PFLGE: ECHE Position              */\r
+#define POSIF_PFLGE_ECHE_Msk                  (0x01UL << POSIF_PFLGE_ECHE_Pos)                        /*!< POSIF PFLGE: ECHE Mask                  */\r
+#define POSIF_PFLGE_EWHE_Pos                  1                                                       /*!< POSIF PFLGE: EWHE Position              */\r
+#define POSIF_PFLGE_EWHE_Msk                  (0x01UL << POSIF_PFLGE_EWHE_Pos)                        /*!< POSIF PFLGE: EWHE Mask                  */\r
+#define POSIF_PFLGE_EHIE_Pos                  2                                                       /*!< POSIF PFLGE: EHIE Position              */\r
+#define POSIF_PFLGE_EHIE_Msk                  (0x01UL << POSIF_PFLGE_EHIE_Pos)                        /*!< POSIF PFLGE: EHIE Mask                  */\r
+#define POSIF_PFLGE_EMST_Pos                  4                                                       /*!< POSIF PFLGE: EMST Position              */\r
+#define POSIF_PFLGE_EMST_Msk                  (0x01UL << POSIF_PFLGE_EMST_Pos)                        /*!< POSIF PFLGE: EMST Mask                  */\r
+#define POSIF_PFLGE_EINDX_Pos                 8                                                       /*!< POSIF PFLGE: EINDX Position             */\r
+#define POSIF_PFLGE_EINDX_Msk                 (0x01UL << POSIF_PFLGE_EINDX_Pos)                       /*!< POSIF PFLGE: EINDX Mask                 */\r
+#define POSIF_PFLGE_EERR_Pos                  9                                                       /*!< POSIF PFLGE: EERR Position              */\r
+#define POSIF_PFLGE_EERR_Msk                  (0x01UL << POSIF_PFLGE_EERR_Pos)                        /*!< POSIF PFLGE: EERR Mask                  */\r
+#define POSIF_PFLGE_ECNT_Pos                  10                                                      /*!< POSIF PFLGE: ECNT Position              */\r
+#define POSIF_PFLGE_ECNT_Msk                  (0x01UL << POSIF_PFLGE_ECNT_Pos)                        /*!< POSIF PFLGE: ECNT Mask                  */\r
+#define POSIF_PFLGE_EDIR_Pos                  11                                                      /*!< POSIF PFLGE: EDIR Position              */\r
+#define POSIF_PFLGE_EDIR_Msk                  (0x01UL << POSIF_PFLGE_EDIR_Pos)                        /*!< POSIF PFLGE: EDIR Mask                  */\r
+#define POSIF_PFLGE_EPCLK_Pos                 12                                                      /*!< POSIF PFLGE: EPCLK Position             */\r
+#define POSIF_PFLGE_EPCLK_Msk                 (0x01UL << POSIF_PFLGE_EPCLK_Pos)                       /*!< POSIF PFLGE: EPCLK Mask                 */\r
+#define POSIF_PFLGE_CHESEL_Pos                16                                                      /*!< POSIF PFLGE: CHESEL Position            */\r
+#define POSIF_PFLGE_CHESEL_Msk                (0x01UL << POSIF_PFLGE_CHESEL_Pos)                      /*!< POSIF PFLGE: CHESEL Mask                */\r
+#define POSIF_PFLGE_WHESEL_Pos                17                                                      /*!< POSIF PFLGE: WHESEL Position            */\r
+#define POSIF_PFLGE_WHESEL_Msk                (0x01UL << POSIF_PFLGE_WHESEL_Pos)                      /*!< POSIF PFLGE: WHESEL Mask                */\r
+#define POSIF_PFLGE_HIESEL_Pos                18                                                      /*!< POSIF PFLGE: HIESEL Position            */\r
+#define POSIF_PFLGE_HIESEL_Msk                (0x01UL << POSIF_PFLGE_HIESEL_Pos)                      /*!< POSIF PFLGE: HIESEL Mask                */\r
+#define POSIF_PFLGE_MSTSEL_Pos                20                                                      /*!< POSIF PFLGE: MSTSEL Position            */\r
+#define POSIF_PFLGE_MSTSEL_Msk                (0x01UL << POSIF_PFLGE_MSTSEL_Pos)                      /*!< POSIF PFLGE: MSTSEL Mask                */\r
+#define POSIF_PFLGE_INDSEL_Pos                24                                                      /*!< POSIF PFLGE: INDSEL Position            */\r
+#define POSIF_PFLGE_INDSEL_Msk                (0x01UL << POSIF_PFLGE_INDSEL_Pos)                      /*!< POSIF PFLGE: INDSEL Mask                */\r
+#define POSIF_PFLGE_ERRSEL_Pos                25                                                      /*!< POSIF PFLGE: ERRSEL Position            */\r
+#define POSIF_PFLGE_ERRSEL_Msk                (0x01UL << POSIF_PFLGE_ERRSEL_Pos)                      /*!< POSIF PFLGE: ERRSEL Mask                */\r
+#define POSIF_PFLGE_CNTSEL_Pos                26                                                      /*!< POSIF PFLGE: CNTSEL Position            */\r
+#define POSIF_PFLGE_CNTSEL_Msk                (0x01UL << POSIF_PFLGE_CNTSEL_Pos)                      /*!< POSIF PFLGE: CNTSEL Mask                */\r
+#define POSIF_PFLGE_DIRSEL_Pos                27                                                      /*!< POSIF PFLGE: DIRSEL Position            */\r
+#define POSIF_PFLGE_DIRSEL_Msk                (0x01UL << POSIF_PFLGE_DIRSEL_Pos)                      /*!< POSIF PFLGE: DIRSEL Mask                */\r
+#define POSIF_PFLGE_PCLSEL_Pos                28                                                      /*!< POSIF PFLGE: PCLSEL Position            */\r
+#define POSIF_PFLGE_PCLSEL_Msk                (0x01UL << POSIF_PFLGE_PCLSEL_Pos)                      /*!< POSIF PFLGE: PCLSEL Mask                */\r
+\r
+/* ---------------------------------  POSIF_SPFLG  -------------------------------- */\r
+#define POSIF_SPFLG_SCHE_Pos                  0                                                       /*!< POSIF SPFLG: SCHE Position              */\r
+#define POSIF_SPFLG_SCHE_Msk                  (0x01UL << POSIF_SPFLG_SCHE_Pos)                        /*!< POSIF SPFLG: SCHE Mask                  */\r
+#define POSIF_SPFLG_SWHE_Pos                  1                                                       /*!< POSIF SPFLG: SWHE Position              */\r
+#define POSIF_SPFLG_SWHE_Msk                  (0x01UL << POSIF_SPFLG_SWHE_Pos)                        /*!< POSIF SPFLG: SWHE Mask                  */\r
+#define POSIF_SPFLG_SHIE_Pos                  2                                                       /*!< POSIF SPFLG: SHIE Position              */\r
+#define POSIF_SPFLG_SHIE_Msk                  (0x01UL << POSIF_SPFLG_SHIE_Pos)                        /*!< POSIF SPFLG: SHIE Mask                  */\r
+#define POSIF_SPFLG_SMST_Pos                  4                                                       /*!< POSIF SPFLG: SMST Position              */\r
+#define POSIF_SPFLG_SMST_Msk                  (0x01UL << POSIF_SPFLG_SMST_Pos)                        /*!< POSIF SPFLG: SMST Mask                  */\r
+#define POSIF_SPFLG_SINDX_Pos                 8                                                       /*!< POSIF SPFLG: SINDX Position             */\r
+#define POSIF_SPFLG_SINDX_Msk                 (0x01UL << POSIF_SPFLG_SINDX_Pos)                       /*!< POSIF SPFLG: SINDX Mask                 */\r
+#define POSIF_SPFLG_SERR_Pos                  9                                                       /*!< POSIF SPFLG: SERR Position              */\r
+#define POSIF_SPFLG_SERR_Msk                  (0x01UL << POSIF_SPFLG_SERR_Pos)                        /*!< POSIF SPFLG: SERR Mask                  */\r
+#define POSIF_SPFLG_SCNT_Pos                  10                                                      /*!< POSIF SPFLG: SCNT Position              */\r
+#define POSIF_SPFLG_SCNT_Msk                  (0x01UL << POSIF_SPFLG_SCNT_Pos)                        /*!< POSIF SPFLG: SCNT Mask                  */\r
+#define POSIF_SPFLG_SDIR_Pos                  11                                                      /*!< POSIF SPFLG: SDIR Position              */\r
+#define POSIF_SPFLG_SDIR_Msk                  (0x01UL << POSIF_SPFLG_SDIR_Pos)                        /*!< POSIF SPFLG: SDIR Mask                  */\r
+#define POSIF_SPFLG_SPCLK_Pos                 12                                                      /*!< POSIF SPFLG: SPCLK Position             */\r
+#define POSIF_SPFLG_SPCLK_Msk                 (0x01UL << POSIF_SPFLG_SPCLK_Pos)                       /*!< POSIF SPFLG: SPCLK Mask                 */\r
+\r
+/* ---------------------------------  POSIF_RPFLG  -------------------------------- */\r
+#define POSIF_RPFLG_RCHE_Pos                  0                                                       /*!< POSIF RPFLG: RCHE Position              */\r
+#define POSIF_RPFLG_RCHE_Msk                  (0x01UL << POSIF_RPFLG_RCHE_Pos)                        /*!< POSIF RPFLG: RCHE Mask                  */\r
+#define POSIF_RPFLG_RWHE_Pos                  1                                                       /*!< POSIF RPFLG: RWHE Position              */\r
+#define POSIF_RPFLG_RWHE_Msk                  (0x01UL << POSIF_RPFLG_RWHE_Pos)                        /*!< POSIF RPFLG: RWHE Mask                  */\r
+#define POSIF_RPFLG_RHIE_Pos                  2                                                       /*!< POSIF RPFLG: RHIE Position              */\r
+#define POSIF_RPFLG_RHIE_Msk                  (0x01UL << POSIF_RPFLG_RHIE_Pos)                        /*!< POSIF RPFLG: RHIE Mask                  */\r
+#define POSIF_RPFLG_RMST_Pos                  4                                                       /*!< POSIF RPFLG: RMST Position              */\r
+#define POSIF_RPFLG_RMST_Msk                  (0x01UL << POSIF_RPFLG_RMST_Pos)                        /*!< POSIF RPFLG: RMST Mask                  */\r
+#define POSIF_RPFLG_RINDX_Pos                 8                                                       /*!< POSIF RPFLG: RINDX Position             */\r
+#define POSIF_RPFLG_RINDX_Msk                 (0x01UL << POSIF_RPFLG_RINDX_Pos)                       /*!< POSIF RPFLG: RINDX Mask                 */\r
+#define POSIF_RPFLG_RERR_Pos                  9                                                       /*!< POSIF RPFLG: RERR Position              */\r
+#define POSIF_RPFLG_RERR_Msk                  (0x01UL << POSIF_RPFLG_RERR_Pos)                        /*!< POSIF RPFLG: RERR Mask                  */\r
+#define POSIF_RPFLG_RCNT_Pos                  10                                                      /*!< POSIF RPFLG: RCNT Position              */\r
+#define POSIF_RPFLG_RCNT_Msk                  (0x01UL << POSIF_RPFLG_RCNT_Pos)                        /*!< POSIF RPFLG: RCNT Mask                  */\r
+#define POSIF_RPFLG_RDIR_Pos                  11                                                      /*!< POSIF RPFLG: RDIR Position              */\r
+#define POSIF_RPFLG_RDIR_Msk                  (0x01UL << POSIF_RPFLG_RDIR_Pos)                        /*!< POSIF RPFLG: RDIR Mask                  */\r
+#define POSIF_RPFLG_RPCLK_Pos                 12                                                      /*!< POSIF RPFLG: RPCLK Position             */\r
+#define POSIF_RPFLG_RPCLK_Msk                 (0x01UL << POSIF_RPFLG_RPCLK_Pos)                       /*!< POSIF RPFLG: RPCLK Mask                 */\r
+\r
+/* ---------------------------------  POSIF_PDBG  --------------------------------- */\r
+#define POSIF_PDBG_QCSV_Pos                   0                                                       /*!< POSIF PDBG: QCSV Position               */\r
+#define POSIF_PDBG_QCSV_Msk                   (0x03UL << POSIF_PDBG_QCSV_Pos)                         /*!< POSIF PDBG: QCSV Mask                   */\r
+#define POSIF_PDBG_QPSV_Pos                   2                                                       /*!< POSIF PDBG: QPSV Position               */\r
+#define POSIF_PDBG_QPSV_Msk                   (0x03UL << POSIF_PDBG_QPSV_Pos)                         /*!< POSIF PDBG: QPSV Mask                   */\r
+#define POSIF_PDBG_IVAL_Pos                   4                                                       /*!< POSIF PDBG: IVAL Position               */\r
+#define POSIF_PDBG_IVAL_Msk                   (0x01UL << POSIF_PDBG_IVAL_Pos)                         /*!< POSIF PDBG: IVAL Mask                   */\r
+#define POSIF_PDBG_HSP_Pos                    5                                                       /*!< POSIF PDBG: HSP Position                */\r
+#define POSIF_PDBG_HSP_Msk                    (0x07UL << POSIF_PDBG_HSP_Pos)                          /*!< POSIF PDBG: HSP Mask                    */\r
+#define POSIF_PDBG_LPP0_Pos                   8                                                       /*!< POSIF PDBG: LPP0 Position               */\r
+#define POSIF_PDBG_LPP0_Msk                   (0x3fUL << POSIF_PDBG_LPP0_Pos)                         /*!< POSIF PDBG: LPP0 Mask                   */\r
+#define POSIF_PDBG_LPP1_Pos                   16                                                      /*!< POSIF PDBG: LPP1 Position               */\r
+#define POSIF_PDBG_LPP1_Msk                   (0x3fUL << POSIF_PDBG_LPP1_Pos)                         /*!< POSIF PDBG: LPP1 Mask                   */\r
+#define POSIF_PDBG_LPP2_Pos                   22                                                      /*!< POSIF PDBG: LPP2 Position               */\r
+#define POSIF_PDBG_LPP2_Msk                   (0x3fUL << POSIF_PDBG_LPP2_Pos)                         /*!< POSIF PDBG: LPP2 Mask                   */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT0' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT0_OUT  --------------------------------- */\r
+#define PORT0_OUT_P0_Pos                      0                                                       /*!< PORT0 OUT: P0 Position                  */\r
+#define PORT0_OUT_P0_Msk                      (0x01UL << PORT0_OUT_P0_Pos)                            /*!< PORT0 OUT: P0 Mask                      */\r
+#define PORT0_OUT_P1_Pos                      1                                                       /*!< PORT0 OUT: P1 Position                  */\r
+#define PORT0_OUT_P1_Msk                      (0x01UL << PORT0_OUT_P1_Pos)                            /*!< PORT0 OUT: P1 Mask                      */\r
+#define PORT0_OUT_P2_Pos                      2                                                       /*!< PORT0 OUT: P2 Position                  */\r
+#define PORT0_OUT_P2_Msk                      (0x01UL << PORT0_OUT_P2_Pos)                            /*!< PORT0 OUT: P2 Mask                      */\r
+#define PORT0_OUT_P3_Pos                      3                                                       /*!< PORT0 OUT: P3 Position                  */\r
+#define PORT0_OUT_P3_Msk                      (0x01UL << PORT0_OUT_P3_Pos)                            /*!< PORT0 OUT: P3 Mask                      */\r
+#define PORT0_OUT_P4_Pos                      4                                                       /*!< PORT0 OUT: P4 Position                  */\r
+#define PORT0_OUT_P4_Msk                      (0x01UL << PORT0_OUT_P4_Pos)                            /*!< PORT0 OUT: P4 Mask                      */\r
+#define PORT0_OUT_P5_Pos                      5                                                       /*!< PORT0 OUT: P5 Position                  */\r
+#define PORT0_OUT_P5_Msk                      (0x01UL << PORT0_OUT_P5_Pos)                            /*!< PORT0 OUT: P5 Mask                      */\r
+#define PORT0_OUT_P6_Pos                      6                                                       /*!< PORT0 OUT: P6 Position                  */\r
+#define PORT0_OUT_P6_Msk                      (0x01UL << PORT0_OUT_P6_Pos)                            /*!< PORT0 OUT: P6 Mask                      */\r
+#define PORT0_OUT_P7_Pos                      7                                                       /*!< PORT0 OUT: P7 Position                  */\r
+#define PORT0_OUT_P7_Msk                      (0x01UL << PORT0_OUT_P7_Pos)                            /*!< PORT0 OUT: P7 Mask                      */\r
+#define PORT0_OUT_P8_Pos                      8                                                       /*!< PORT0 OUT: P8 Position                  */\r
+#define PORT0_OUT_P8_Msk                      (0x01UL << PORT0_OUT_P8_Pos)                            /*!< PORT0 OUT: P8 Mask                      */\r
+#define PORT0_OUT_P9_Pos                      9                                                       /*!< PORT0 OUT: P9 Position                  */\r
+#define PORT0_OUT_P9_Msk                      (0x01UL << PORT0_OUT_P9_Pos)                            /*!< PORT0 OUT: P9 Mask                      */\r
+#define PORT0_OUT_P10_Pos                     10                                                      /*!< PORT0 OUT: P10 Position                 */\r
+#define PORT0_OUT_P10_Msk                     (0x01UL << PORT0_OUT_P10_Pos)                           /*!< PORT0 OUT: P10 Mask                     */\r
+#define PORT0_OUT_P11_Pos                     11                                                      /*!< PORT0 OUT: P11 Position                 */\r
+#define PORT0_OUT_P11_Msk                     (0x01UL << PORT0_OUT_P11_Pos)                           /*!< PORT0 OUT: P11 Mask                     */\r
+#define PORT0_OUT_P12_Pos                     12                                                      /*!< PORT0 OUT: P12 Position                 */\r
+#define PORT0_OUT_P12_Msk                     (0x01UL << PORT0_OUT_P12_Pos)                           /*!< PORT0 OUT: P12 Mask                     */\r
+#define PORT0_OUT_P13_Pos                     13                                                      /*!< PORT0 OUT: P13 Position                 */\r
+#define PORT0_OUT_P13_Msk                     (0x01UL << PORT0_OUT_P13_Pos)                           /*!< PORT0 OUT: P13 Mask                     */\r
+#define PORT0_OUT_P14_Pos                     14                                                      /*!< PORT0 OUT: P14 Position                 */\r
+#define PORT0_OUT_P14_Msk                     (0x01UL << PORT0_OUT_P14_Pos)                           /*!< PORT0 OUT: P14 Mask                     */\r
+#define PORT0_OUT_P15_Pos                     15                                                      /*!< PORT0 OUT: P15 Position                 */\r
+#define PORT0_OUT_P15_Msk                     (0x01UL << PORT0_OUT_P15_Pos)                           /*!< PORT0 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT0_OMR  --------------------------------- */\r
+#define PORT0_OMR_PS0_Pos                     0                                                       /*!< PORT0 OMR: PS0 Position                 */\r
+#define PORT0_OMR_PS0_Msk                     (0x01UL << PORT0_OMR_PS0_Pos)                           /*!< PORT0 OMR: PS0 Mask                     */\r
+#define PORT0_OMR_PS1_Pos                     1                                                       /*!< PORT0 OMR: PS1 Position                 */\r
+#define PORT0_OMR_PS1_Msk                     (0x01UL << PORT0_OMR_PS1_Pos)                           /*!< PORT0 OMR: PS1 Mask                     */\r
+#define PORT0_OMR_PS2_Pos                     2                                                       /*!< PORT0 OMR: PS2 Position                 */\r
+#define PORT0_OMR_PS2_Msk                     (0x01UL << PORT0_OMR_PS2_Pos)                           /*!< PORT0 OMR: PS2 Mask                     */\r
+#define PORT0_OMR_PS3_Pos                     3                                                       /*!< PORT0 OMR: PS3 Position                 */\r
+#define PORT0_OMR_PS3_Msk                     (0x01UL << PORT0_OMR_PS3_Pos)                           /*!< PORT0 OMR: PS3 Mask                     */\r
+#define PORT0_OMR_PS4_Pos                     4                                                       /*!< PORT0 OMR: PS4 Position                 */\r
+#define PORT0_OMR_PS4_Msk                     (0x01UL << PORT0_OMR_PS4_Pos)                           /*!< PORT0 OMR: PS4 Mask                     */\r
+#define PORT0_OMR_PS5_Pos                     5                                                       /*!< PORT0 OMR: PS5 Position                 */\r
+#define PORT0_OMR_PS5_Msk                     (0x01UL << PORT0_OMR_PS5_Pos)                           /*!< PORT0 OMR: PS5 Mask                     */\r
+#define PORT0_OMR_PS6_Pos                     6                                                       /*!< PORT0 OMR: PS6 Position                 */\r
+#define PORT0_OMR_PS6_Msk                     (0x01UL << PORT0_OMR_PS6_Pos)                           /*!< PORT0 OMR: PS6 Mask                     */\r
+#define PORT0_OMR_PS7_Pos                     7                                                       /*!< PORT0 OMR: PS7 Position                 */\r
+#define PORT0_OMR_PS7_Msk                     (0x01UL << PORT0_OMR_PS7_Pos)                           /*!< PORT0 OMR: PS7 Mask                     */\r
+#define PORT0_OMR_PS8_Pos                     8                                                       /*!< PORT0 OMR: PS8 Position                 */\r
+#define PORT0_OMR_PS8_Msk                     (0x01UL << PORT0_OMR_PS8_Pos)                           /*!< PORT0 OMR: PS8 Mask                     */\r
+#define PORT0_OMR_PS9_Pos                     9                                                       /*!< PORT0 OMR: PS9 Position                 */\r
+#define PORT0_OMR_PS9_Msk                     (0x01UL << PORT0_OMR_PS9_Pos)                           /*!< PORT0 OMR: PS9 Mask                     */\r
+#define PORT0_OMR_PS10_Pos                    10                                                      /*!< PORT0 OMR: PS10 Position                */\r
+#define PORT0_OMR_PS10_Msk                    (0x01UL << PORT0_OMR_PS10_Pos)                          /*!< PORT0 OMR: PS10 Mask                    */\r
+#define PORT0_OMR_PS11_Pos                    11                                                      /*!< PORT0 OMR: PS11 Position                */\r
+#define PORT0_OMR_PS11_Msk                    (0x01UL << PORT0_OMR_PS11_Pos)                          /*!< PORT0 OMR: PS11 Mask                    */\r
+#define PORT0_OMR_PS12_Pos                    12                                                      /*!< PORT0 OMR: PS12 Position                */\r
+#define PORT0_OMR_PS12_Msk                    (0x01UL << PORT0_OMR_PS12_Pos)                          /*!< PORT0 OMR: PS12 Mask                    */\r
+#define PORT0_OMR_PS13_Pos                    13                                                      /*!< PORT0 OMR: PS13 Position                */\r
+#define PORT0_OMR_PS13_Msk                    (0x01UL << PORT0_OMR_PS13_Pos)                          /*!< PORT0 OMR: PS13 Mask                    */\r
+#define PORT0_OMR_PS14_Pos                    14                                                      /*!< PORT0 OMR: PS14 Position                */\r
+#define PORT0_OMR_PS14_Msk                    (0x01UL << PORT0_OMR_PS14_Pos)                          /*!< PORT0 OMR: PS14 Mask                    */\r
+#define PORT0_OMR_PS15_Pos                    15                                                      /*!< PORT0 OMR: PS15 Position                */\r
+#define PORT0_OMR_PS15_Msk                    (0x01UL << PORT0_OMR_PS15_Pos)                          /*!< PORT0 OMR: PS15 Mask                    */\r
+#define PORT0_OMR_PR0_Pos                     16                                                      /*!< PORT0 OMR: PR0 Position                 */\r
+#define PORT0_OMR_PR0_Msk                     (0x01UL << PORT0_OMR_PR0_Pos)                           /*!< PORT0 OMR: PR0 Mask                     */\r
+#define PORT0_OMR_PR1_Pos                     17                                                      /*!< PORT0 OMR: PR1 Position                 */\r
+#define PORT0_OMR_PR1_Msk                     (0x01UL << PORT0_OMR_PR1_Pos)                           /*!< PORT0 OMR: PR1 Mask                     */\r
+#define PORT0_OMR_PR2_Pos                     18                                                      /*!< PORT0 OMR: PR2 Position                 */\r
+#define PORT0_OMR_PR2_Msk                     (0x01UL << PORT0_OMR_PR2_Pos)                           /*!< PORT0 OMR: PR2 Mask                     */\r
+#define PORT0_OMR_PR3_Pos                     19                                                      /*!< PORT0 OMR: PR3 Position                 */\r
+#define PORT0_OMR_PR3_Msk                     (0x01UL << PORT0_OMR_PR3_Pos)                           /*!< PORT0 OMR: PR3 Mask                     */\r
+#define PORT0_OMR_PR4_Pos                     20                                                      /*!< PORT0 OMR: PR4 Position                 */\r
+#define PORT0_OMR_PR4_Msk                     (0x01UL << PORT0_OMR_PR4_Pos)                           /*!< PORT0 OMR: PR4 Mask                     */\r
+#define PORT0_OMR_PR5_Pos                     21                                                      /*!< PORT0 OMR: PR5 Position                 */\r
+#define PORT0_OMR_PR5_Msk                     (0x01UL << PORT0_OMR_PR5_Pos)                           /*!< PORT0 OMR: PR5 Mask                     */\r
+#define PORT0_OMR_PR6_Pos                     22                                                      /*!< PORT0 OMR: PR6 Position                 */\r
+#define PORT0_OMR_PR6_Msk                     (0x01UL << PORT0_OMR_PR6_Pos)                           /*!< PORT0 OMR: PR6 Mask                     */\r
+#define PORT0_OMR_PR7_Pos                     23                                                      /*!< PORT0 OMR: PR7 Position                 */\r
+#define PORT0_OMR_PR7_Msk                     (0x01UL << PORT0_OMR_PR7_Pos)                           /*!< PORT0 OMR: PR7 Mask                     */\r
+#define PORT0_OMR_PR8_Pos                     24                                                      /*!< PORT0 OMR: PR8 Position                 */\r
+#define PORT0_OMR_PR8_Msk                     (0x01UL << PORT0_OMR_PR8_Pos)                           /*!< PORT0 OMR: PR8 Mask                     */\r
+#define PORT0_OMR_PR9_Pos                     25                                                      /*!< PORT0 OMR: PR9 Position                 */\r
+#define PORT0_OMR_PR9_Msk                     (0x01UL << PORT0_OMR_PR9_Pos)                           /*!< PORT0 OMR: PR9 Mask                     */\r
+#define PORT0_OMR_PR10_Pos                    26                                                      /*!< PORT0 OMR: PR10 Position                */\r
+#define PORT0_OMR_PR10_Msk                    (0x01UL << PORT0_OMR_PR10_Pos)                          /*!< PORT0 OMR: PR10 Mask                    */\r
+#define PORT0_OMR_PR11_Pos                    27                                                      /*!< PORT0 OMR: PR11 Position                */\r
+#define PORT0_OMR_PR11_Msk                    (0x01UL << PORT0_OMR_PR11_Pos)                          /*!< PORT0 OMR: PR11 Mask                    */\r
+#define PORT0_OMR_PR12_Pos                    28                                                      /*!< PORT0 OMR: PR12 Position                */\r
+#define PORT0_OMR_PR12_Msk                    (0x01UL << PORT0_OMR_PR12_Pos)                          /*!< PORT0 OMR: PR12 Mask                    */\r
+#define PORT0_OMR_PR13_Pos                    29                                                      /*!< PORT0 OMR: PR13 Position                */\r
+#define PORT0_OMR_PR13_Msk                    (0x01UL << PORT0_OMR_PR13_Pos)                          /*!< PORT0 OMR: PR13 Mask                    */\r
+#define PORT0_OMR_PR14_Pos                    30                                                      /*!< PORT0 OMR: PR14 Position                */\r
+#define PORT0_OMR_PR14_Msk                    (0x01UL << PORT0_OMR_PR14_Pos)                          /*!< PORT0 OMR: PR14 Mask                    */\r
+#define PORT0_OMR_PR15_Pos                    31                                                      /*!< PORT0 OMR: PR15 Position                */\r
+#define PORT0_OMR_PR15_Msk                    (0x01UL << PORT0_OMR_PR15_Pos)                          /*!< PORT0 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT0_IOCR0  -------------------------------- */\r
+#define PORT0_IOCR0_PC0_Pos                   3                                                       /*!< PORT0 IOCR0: PC0 Position               */\r
+#define PORT0_IOCR0_PC0_Msk                   (0x1fUL << PORT0_IOCR0_PC0_Pos)                         /*!< PORT0 IOCR0: PC0 Mask                   */\r
+#define PORT0_IOCR0_PC1_Pos                   11                                                      /*!< PORT0 IOCR0: PC1 Position               */\r
+#define PORT0_IOCR0_PC1_Msk                   (0x1fUL << PORT0_IOCR0_PC1_Pos)                         /*!< PORT0 IOCR0: PC1 Mask                   */\r
+#define PORT0_IOCR0_PC2_Pos                   19                                                      /*!< PORT0 IOCR0: PC2 Position               */\r
+#define PORT0_IOCR0_PC2_Msk                   (0x1fUL << PORT0_IOCR0_PC2_Pos)                         /*!< PORT0 IOCR0: PC2 Mask                   */\r
+#define PORT0_IOCR0_PC3_Pos                   27                                                      /*!< PORT0 IOCR0: PC3 Position               */\r
+#define PORT0_IOCR0_PC3_Msk                   (0x1fUL << PORT0_IOCR0_PC3_Pos)                         /*!< PORT0 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_IOCR4  -------------------------------- */\r
+#define PORT0_IOCR4_PC4_Pos                   3                                                       /*!< PORT0 IOCR4: PC4 Position               */\r
+#define PORT0_IOCR4_PC4_Msk                   (0x1fUL << PORT0_IOCR4_PC4_Pos)                         /*!< PORT0 IOCR4: PC4 Mask                   */\r
+#define PORT0_IOCR4_PC5_Pos                   11                                                      /*!< PORT0 IOCR4: PC5 Position               */\r
+#define PORT0_IOCR4_PC5_Msk                   (0x1fUL << PORT0_IOCR4_PC5_Pos)                         /*!< PORT0 IOCR4: PC5 Mask                   */\r
+#define PORT0_IOCR4_PC6_Pos                   19                                                      /*!< PORT0 IOCR4: PC6 Position               */\r
+#define PORT0_IOCR4_PC6_Msk                   (0x1fUL << PORT0_IOCR4_PC6_Pos)                         /*!< PORT0 IOCR4: PC6 Mask                   */\r
+#define PORT0_IOCR4_PC7_Pos                   27                                                      /*!< PORT0 IOCR4: PC7 Position               */\r
+#define PORT0_IOCR4_PC7_Msk                   (0x1fUL << PORT0_IOCR4_PC7_Pos)                         /*!< PORT0 IOCR4: PC7 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_IOCR8  -------------------------------- */\r
+#define PORT0_IOCR8_PC8_Pos                   3                                                       /*!< PORT0 IOCR8: PC8 Position               */\r
+#define PORT0_IOCR8_PC8_Msk                   (0x1fUL << PORT0_IOCR8_PC8_Pos)                         /*!< PORT0 IOCR8: PC8 Mask                   */\r
+#define PORT0_IOCR8_PC9_Pos                   11                                                      /*!< PORT0 IOCR8: PC9 Position               */\r
+#define PORT0_IOCR8_PC9_Msk                   (0x1fUL << PORT0_IOCR8_PC9_Pos)                         /*!< PORT0 IOCR8: PC9 Mask                   */\r
+#define PORT0_IOCR8_PC10_Pos                  19                                                      /*!< PORT0 IOCR8: PC10 Position              */\r
+#define PORT0_IOCR8_PC10_Msk                  (0x1fUL << PORT0_IOCR8_PC10_Pos)                        /*!< PORT0 IOCR8: PC10 Mask                  */\r
+#define PORT0_IOCR8_PC11_Pos                  27                                                      /*!< PORT0 IOCR8: PC11 Position              */\r
+#define PORT0_IOCR8_PC11_Msk                  (0x1fUL << PORT0_IOCR8_PC11_Pos)                        /*!< PORT0 IOCR8: PC11 Mask                  */\r
+\r
+/* --------------------------------  PORT0_IOCR12  -------------------------------- */\r
+#define PORT0_IOCR12_PC12_Pos                 3                                                       /*!< PORT0 IOCR12: PC12 Position             */\r
+#define PORT0_IOCR12_PC12_Msk                 (0x1fUL << PORT0_IOCR12_PC12_Pos)                       /*!< PORT0 IOCR12: PC12 Mask                 */\r
+#define PORT0_IOCR12_PC13_Pos                 11                                                      /*!< PORT0 IOCR12: PC13 Position             */\r
+#define PORT0_IOCR12_PC13_Msk                 (0x1fUL << PORT0_IOCR12_PC13_Pos)                       /*!< PORT0 IOCR12: PC13 Mask                 */\r
+#define PORT0_IOCR12_PC14_Pos                 19                                                      /*!< PORT0 IOCR12: PC14 Position             */\r
+#define PORT0_IOCR12_PC14_Msk                 (0x1fUL << PORT0_IOCR12_PC14_Pos)                       /*!< PORT0 IOCR12: PC14 Mask                 */\r
+#define PORT0_IOCR12_PC15_Pos                 27                                                      /*!< PORT0 IOCR12: PC15 Position             */\r
+#define PORT0_IOCR12_PC15_Msk                 (0x1fUL << PORT0_IOCR12_PC15_Pos)                       /*!< PORT0 IOCR12: PC15 Mask                 */\r
+\r
+/* ----------------------------------  PORT0_IN  ---------------------------------- */\r
+#define PORT0_IN_P0_Pos                       0                                                       /*!< PORT0 IN: P0 Position                   */\r
+#define PORT0_IN_P0_Msk                       (0x01UL << PORT0_IN_P0_Pos)                             /*!< PORT0 IN: P0 Mask                       */\r
+#define PORT0_IN_P1_Pos                       1                                                       /*!< PORT0 IN: P1 Position                   */\r
+#define PORT0_IN_P1_Msk                       (0x01UL << PORT0_IN_P1_Pos)                             /*!< PORT0 IN: P1 Mask                       */\r
+#define PORT0_IN_P2_Pos                       2                                                       /*!< PORT0 IN: P2 Position                   */\r
+#define PORT0_IN_P2_Msk                       (0x01UL << PORT0_IN_P2_Pos)                             /*!< PORT0 IN: P2 Mask                       */\r
+#define PORT0_IN_P3_Pos                       3                                                       /*!< PORT0 IN: P3 Position                   */\r
+#define PORT0_IN_P3_Msk                       (0x01UL << PORT0_IN_P3_Pos)                             /*!< PORT0 IN: P3 Mask                       */\r
+#define PORT0_IN_P4_Pos                       4                                                       /*!< PORT0 IN: P4 Position                   */\r
+#define PORT0_IN_P4_Msk                       (0x01UL << PORT0_IN_P4_Pos)                             /*!< PORT0 IN: P4 Mask                       */\r
+#define PORT0_IN_P5_Pos                       5                                                       /*!< PORT0 IN: P5 Position                   */\r
+#define PORT0_IN_P5_Msk                       (0x01UL << PORT0_IN_P5_Pos)                             /*!< PORT0 IN: P5 Mask                       */\r
+#define PORT0_IN_P6_Pos                       6                                                       /*!< PORT0 IN: P6 Position                   */\r
+#define PORT0_IN_P6_Msk                       (0x01UL << PORT0_IN_P6_Pos)                             /*!< PORT0 IN: P6 Mask                       */\r
+#define PORT0_IN_P7_Pos                       7                                                       /*!< PORT0 IN: P7 Position                   */\r
+#define PORT0_IN_P7_Msk                       (0x01UL << PORT0_IN_P7_Pos)                             /*!< PORT0 IN: P7 Mask                       */\r
+#define PORT0_IN_P8_Pos                       8                                                       /*!< PORT0 IN: P8 Position                   */\r
+#define PORT0_IN_P8_Msk                       (0x01UL << PORT0_IN_P8_Pos)                             /*!< PORT0 IN: P8 Mask                       */\r
+#define PORT0_IN_P9_Pos                       9                                                       /*!< PORT0 IN: P9 Position                   */\r
+#define PORT0_IN_P9_Msk                       (0x01UL << PORT0_IN_P9_Pos)                             /*!< PORT0 IN: P9 Mask                       */\r
+#define PORT0_IN_P10_Pos                      10                                                      /*!< PORT0 IN: P10 Position                  */\r
+#define PORT0_IN_P10_Msk                      (0x01UL << PORT0_IN_P10_Pos)                            /*!< PORT0 IN: P10 Mask                      */\r
+#define PORT0_IN_P11_Pos                      11                                                      /*!< PORT0 IN: P11 Position                  */\r
+#define PORT0_IN_P11_Msk                      (0x01UL << PORT0_IN_P11_Pos)                            /*!< PORT0 IN: P11 Mask                      */\r
+#define PORT0_IN_P12_Pos                      12                                                      /*!< PORT0 IN: P12 Position                  */\r
+#define PORT0_IN_P12_Msk                      (0x01UL << PORT0_IN_P12_Pos)                            /*!< PORT0 IN: P12 Mask                      */\r
+#define PORT0_IN_P13_Pos                      13                                                      /*!< PORT0 IN: P13 Position                  */\r
+#define PORT0_IN_P13_Msk                      (0x01UL << PORT0_IN_P13_Pos)                            /*!< PORT0 IN: P13 Mask                      */\r
+#define PORT0_IN_P14_Pos                      14                                                      /*!< PORT0 IN: P14 Position                  */\r
+#define PORT0_IN_P14_Msk                      (0x01UL << PORT0_IN_P14_Pos)                            /*!< PORT0 IN: P14 Mask                      */\r
+#define PORT0_IN_P15_Pos                      15                                                      /*!< PORT0 IN: P15 Position                  */\r
+#define PORT0_IN_P15_Msk                      (0x01UL << PORT0_IN_P15_Pos)                            /*!< PORT0 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT0_PDR0  --------------------------------- */\r
+#define PORT0_PDR0_PD0_Pos                    0                                                       /*!< PORT0 PDR0: PD0 Position                */\r
+#define PORT0_PDR0_PD0_Msk                    (0x07UL << PORT0_PDR0_PD0_Pos)                          /*!< PORT0 PDR0: PD0 Mask                    */\r
+#define PORT0_PDR0_PD1_Pos                    4                                                       /*!< PORT0 PDR0: PD1 Position                */\r
+#define PORT0_PDR0_PD1_Msk                    (0x07UL << PORT0_PDR0_PD1_Pos)                          /*!< PORT0 PDR0: PD1 Mask                    */\r
+#define PORT0_PDR0_PD2_Pos                    8                                                       /*!< PORT0 PDR0: PD2 Position                */\r
+#define PORT0_PDR0_PD2_Msk                    (0x07UL << PORT0_PDR0_PD2_Pos)                          /*!< PORT0 PDR0: PD2 Mask                    */\r
+#define PORT0_PDR0_PD3_Pos                    12                                                      /*!< PORT0 PDR0: PD3 Position                */\r
+#define PORT0_PDR0_PD3_Msk                    (0x07UL << PORT0_PDR0_PD3_Pos)                          /*!< PORT0 PDR0: PD3 Mask                    */\r
+#define PORT0_PDR0_PD4_Pos                    16                                                      /*!< PORT0 PDR0: PD4 Position                */\r
+#define PORT0_PDR0_PD4_Msk                    (0x07UL << PORT0_PDR0_PD4_Pos)                          /*!< PORT0 PDR0: PD4 Mask                    */\r
+#define PORT0_PDR0_PD5_Pos                    20                                                      /*!< PORT0 PDR0: PD5 Position                */\r
+#define PORT0_PDR0_PD5_Msk                    (0x07UL << PORT0_PDR0_PD5_Pos)                          /*!< PORT0 PDR0: PD5 Mask                    */\r
+#define PORT0_PDR0_PD6_Pos                    24                                                      /*!< PORT0 PDR0: PD6 Position                */\r
+#define PORT0_PDR0_PD6_Msk                    (0x07UL << PORT0_PDR0_PD6_Pos)                          /*!< PORT0 PDR0: PD6 Mask                    */\r
+#define PORT0_PDR0_PD7_Pos                    28                                                      /*!< PORT0 PDR0: PD7 Position                */\r
+#define PORT0_PDR0_PD7_Msk                    (0x07UL << PORT0_PDR0_PD7_Pos)                          /*!< PORT0 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT0_PDR1  --------------------------------- */\r
+#define PORT0_PDR1_PD8_Pos                    0                                                       /*!< PORT0 PDR1: PD8 Position                */\r
+#define PORT0_PDR1_PD8_Msk                    (0x07UL << PORT0_PDR1_PD8_Pos)                          /*!< PORT0 PDR1: PD8 Mask                    */\r
+#define PORT0_PDR1_PD9_Pos                    4                                                       /*!< PORT0 PDR1: PD9 Position                */\r
+#define PORT0_PDR1_PD9_Msk                    (0x07UL << PORT0_PDR1_PD9_Pos)                          /*!< PORT0 PDR1: PD9 Mask                    */\r
+#define PORT0_PDR1_PD10_Pos                   8                                                       /*!< PORT0 PDR1: PD10 Position               */\r
+#define PORT0_PDR1_PD10_Msk                   (0x07UL << PORT0_PDR1_PD10_Pos)                         /*!< PORT0 PDR1: PD10 Mask                   */\r
+#define PORT0_PDR1_PD11_Pos                   12                                                      /*!< PORT0 PDR1: PD11 Position               */\r
+#define PORT0_PDR1_PD11_Msk                   (0x07UL << PORT0_PDR1_PD11_Pos)                         /*!< PORT0 PDR1: PD11 Mask                   */\r
+#define PORT0_PDR1_PD12_Pos                   16                                                      /*!< PORT0 PDR1: PD12 Position               */\r
+#define PORT0_PDR1_PD12_Msk                   (0x07UL << PORT0_PDR1_PD12_Pos)                         /*!< PORT0 PDR1: PD12 Mask                   */\r
+#define PORT0_PDR1_PD13_Pos                   20                                                      /*!< PORT0 PDR1: PD13 Position               */\r
+#define PORT0_PDR1_PD13_Msk                   (0x07UL << PORT0_PDR1_PD13_Pos)                         /*!< PORT0 PDR1: PD13 Mask                   */\r
+#define PORT0_PDR1_PD14_Pos                   24                                                      /*!< PORT0 PDR1: PD14 Position               */\r
+#define PORT0_PDR1_PD14_Msk                   (0x07UL << PORT0_PDR1_PD14_Pos)                         /*!< PORT0 PDR1: PD14 Mask                   */\r
+#define PORT0_PDR1_PD15_Pos                   28                                                      /*!< PORT0 PDR1: PD15 Position               */\r
+#define PORT0_PDR1_PD15_Msk                   (0x07UL << PORT0_PDR1_PD15_Pos)                         /*!< PORT0 PDR1: PD15 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_PDISC  -------------------------------- */\r
+#define PORT0_PDISC_PDIS0_Pos                 0                                                       /*!< PORT0 PDISC: PDIS0 Position             */\r
+#define PORT0_PDISC_PDIS0_Msk                 (0x01UL << PORT0_PDISC_PDIS0_Pos)                       /*!< PORT0 PDISC: PDIS0 Mask                 */\r
+#define PORT0_PDISC_PDIS1_Pos                 1                                                       /*!< PORT0 PDISC: PDIS1 Position             */\r
+#define PORT0_PDISC_PDIS1_Msk                 (0x01UL << PORT0_PDISC_PDIS1_Pos)                       /*!< PORT0 PDISC: PDIS1 Mask                 */\r
+#define PORT0_PDISC_PDIS2_Pos                 2                                                       /*!< PORT0 PDISC: PDIS2 Position             */\r
+#define PORT0_PDISC_PDIS2_Msk                 (0x01UL << PORT0_PDISC_PDIS2_Pos)                       /*!< PORT0 PDISC: PDIS2 Mask                 */\r
+#define PORT0_PDISC_PDIS3_Pos                 3                                                       /*!< PORT0 PDISC: PDIS3 Position             */\r
+#define PORT0_PDISC_PDIS3_Msk                 (0x01UL << PORT0_PDISC_PDIS3_Pos)                       /*!< PORT0 PDISC: PDIS3 Mask                 */\r
+#define PORT0_PDISC_PDIS4_Pos                 4                                                       /*!< PORT0 PDISC: PDIS4 Position             */\r
+#define PORT0_PDISC_PDIS4_Msk                 (0x01UL << PORT0_PDISC_PDIS4_Pos)                       /*!< PORT0 PDISC: PDIS4 Mask                 */\r
+#define PORT0_PDISC_PDIS5_Pos                 5                                                       /*!< PORT0 PDISC: PDIS5 Position             */\r
+#define PORT0_PDISC_PDIS5_Msk                 (0x01UL << PORT0_PDISC_PDIS5_Pos)                       /*!< PORT0 PDISC: PDIS5 Mask                 */\r
+#define PORT0_PDISC_PDIS6_Pos                 6                                                       /*!< PORT0 PDISC: PDIS6 Position             */\r
+#define PORT0_PDISC_PDIS6_Msk                 (0x01UL << PORT0_PDISC_PDIS6_Pos)                       /*!< PORT0 PDISC: PDIS6 Mask                 */\r
+#define PORT0_PDISC_PDIS7_Pos                 7                                                       /*!< PORT0 PDISC: PDIS7 Position             */\r
+#define PORT0_PDISC_PDIS7_Msk                 (0x01UL << PORT0_PDISC_PDIS7_Pos)                       /*!< PORT0 PDISC: PDIS7 Mask                 */\r
+#define PORT0_PDISC_PDIS8_Pos                 8                                                       /*!< PORT0 PDISC: PDIS8 Position             */\r
+#define PORT0_PDISC_PDIS8_Msk                 (0x01UL << PORT0_PDISC_PDIS8_Pos)                       /*!< PORT0 PDISC: PDIS8 Mask                 */\r
+#define PORT0_PDISC_PDIS9_Pos                 9                                                       /*!< PORT0 PDISC: PDIS9 Position             */\r
+#define PORT0_PDISC_PDIS9_Msk                 (0x01UL << PORT0_PDISC_PDIS9_Pos)                       /*!< PORT0 PDISC: PDIS9 Mask                 */\r
+#define PORT0_PDISC_PDIS10_Pos                10                                                      /*!< PORT0 PDISC: PDIS10 Position            */\r
+#define PORT0_PDISC_PDIS10_Msk                (0x01UL << PORT0_PDISC_PDIS10_Pos)                      /*!< PORT0 PDISC: PDIS10 Mask                */\r
+#define PORT0_PDISC_PDIS11_Pos                11                                                      /*!< PORT0 PDISC: PDIS11 Position            */\r
+#define PORT0_PDISC_PDIS11_Msk                (0x01UL << PORT0_PDISC_PDIS11_Pos)                      /*!< PORT0 PDISC: PDIS11 Mask                */\r
+#define PORT0_PDISC_PDIS12_Pos                12                                                      /*!< PORT0 PDISC: PDIS12 Position            */\r
+#define PORT0_PDISC_PDIS12_Msk                (0x01UL << PORT0_PDISC_PDIS12_Pos)                      /*!< PORT0 PDISC: PDIS12 Mask                */\r
+#define PORT0_PDISC_PDIS13_Pos                13                                                      /*!< PORT0 PDISC: PDIS13 Position            */\r
+#define PORT0_PDISC_PDIS13_Msk                (0x01UL << PORT0_PDISC_PDIS13_Pos)                      /*!< PORT0 PDISC: PDIS13 Mask                */\r
+#define PORT0_PDISC_PDIS14_Pos                14                                                      /*!< PORT0 PDISC: PDIS14 Position            */\r
+#define PORT0_PDISC_PDIS14_Msk                (0x01UL << PORT0_PDISC_PDIS14_Pos)                      /*!< PORT0 PDISC: PDIS14 Mask                */\r
+#define PORT0_PDISC_PDIS15_Pos                15                                                      /*!< PORT0 PDISC: PDIS15 Position            */\r
+#define PORT0_PDISC_PDIS15_Msk                (0x01UL << PORT0_PDISC_PDIS15_Pos)                      /*!< PORT0 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT0_PPS  --------------------------------- */\r
+#define PORT0_PPS_PPS0_Pos                    0                                                       /*!< PORT0 PPS: PPS0 Position                */\r
+#define PORT0_PPS_PPS0_Msk                    (0x01UL << PORT0_PPS_PPS0_Pos)                          /*!< PORT0 PPS: PPS0 Mask                    */\r
+#define PORT0_PPS_PPS1_Pos                    1                                                       /*!< PORT0 PPS: PPS1 Position                */\r
+#define PORT0_PPS_PPS1_Msk                    (0x01UL << PORT0_PPS_PPS1_Pos)                          /*!< PORT0 PPS: PPS1 Mask                    */\r
+#define PORT0_PPS_PPS2_Pos                    2                                                       /*!< PORT0 PPS: PPS2 Position                */\r
+#define PORT0_PPS_PPS2_Msk                    (0x01UL << PORT0_PPS_PPS2_Pos)                          /*!< PORT0 PPS: PPS2 Mask                    */\r
+#define PORT0_PPS_PPS3_Pos                    3                                                       /*!< PORT0 PPS: PPS3 Position                */\r
+#define PORT0_PPS_PPS3_Msk                    (0x01UL << PORT0_PPS_PPS3_Pos)                          /*!< PORT0 PPS: PPS3 Mask                    */\r
+#define PORT0_PPS_PPS4_Pos                    4                                                       /*!< PORT0 PPS: PPS4 Position                */\r
+#define PORT0_PPS_PPS4_Msk                    (0x01UL << PORT0_PPS_PPS4_Pos)                          /*!< PORT0 PPS: PPS4 Mask                    */\r
+#define PORT0_PPS_PPS5_Pos                    5                                                       /*!< PORT0 PPS: PPS5 Position                */\r
+#define PORT0_PPS_PPS5_Msk                    (0x01UL << PORT0_PPS_PPS5_Pos)                          /*!< PORT0 PPS: PPS5 Mask                    */\r
+#define PORT0_PPS_PPS6_Pos                    6                                                       /*!< PORT0 PPS: PPS6 Position                */\r
+#define PORT0_PPS_PPS6_Msk                    (0x01UL << PORT0_PPS_PPS6_Pos)                          /*!< PORT0 PPS: PPS6 Mask                    */\r
+#define PORT0_PPS_PPS7_Pos                    7                                                       /*!< PORT0 PPS: PPS7 Position                */\r
+#define PORT0_PPS_PPS7_Msk                    (0x01UL << PORT0_PPS_PPS7_Pos)                          /*!< PORT0 PPS: PPS7 Mask                    */\r
+#define PORT0_PPS_PPS8_Pos                    8                                                       /*!< PORT0 PPS: PPS8 Position                */\r
+#define PORT0_PPS_PPS8_Msk                    (0x01UL << PORT0_PPS_PPS8_Pos)                          /*!< PORT0 PPS: PPS8 Mask                    */\r
+#define PORT0_PPS_PPS9_Pos                    9                                                       /*!< PORT0 PPS: PPS9 Position                */\r
+#define PORT0_PPS_PPS9_Msk                    (0x01UL << PORT0_PPS_PPS9_Pos)                          /*!< PORT0 PPS: PPS9 Mask                    */\r
+#define PORT0_PPS_PPS10_Pos                   10                                                      /*!< PORT0 PPS: PPS10 Position               */\r
+#define PORT0_PPS_PPS10_Msk                   (0x01UL << PORT0_PPS_PPS10_Pos)                         /*!< PORT0 PPS: PPS10 Mask                   */\r
+#define PORT0_PPS_PPS11_Pos                   11                                                      /*!< PORT0 PPS: PPS11 Position               */\r
+#define PORT0_PPS_PPS11_Msk                   (0x01UL << PORT0_PPS_PPS11_Pos)                         /*!< PORT0 PPS: PPS11 Mask                   */\r
+#define PORT0_PPS_PPS12_Pos                   12                                                      /*!< PORT0 PPS: PPS12 Position               */\r
+#define PORT0_PPS_PPS12_Msk                   (0x01UL << PORT0_PPS_PPS12_Pos)                         /*!< PORT0 PPS: PPS12 Mask                   */\r
+#define PORT0_PPS_PPS13_Pos                   13                                                      /*!< PORT0 PPS: PPS13 Position               */\r
+#define PORT0_PPS_PPS13_Msk                   (0x01UL << PORT0_PPS_PPS13_Pos)                         /*!< PORT0 PPS: PPS13 Mask                   */\r
+#define PORT0_PPS_PPS14_Pos                   14                                                      /*!< PORT0 PPS: PPS14 Position               */\r
+#define PORT0_PPS_PPS14_Msk                   (0x01UL << PORT0_PPS_PPS14_Pos)                         /*!< PORT0 PPS: PPS14 Mask                   */\r
+#define PORT0_PPS_PPS15_Pos                   15                                                      /*!< PORT0 PPS: PPS15 Position               */\r
+#define PORT0_PPS_PPS15_Msk                   (0x01UL << PORT0_PPS_PPS15_Pos)                         /*!< PORT0 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_HWSEL  -------------------------------- */\r
+#define PORT0_HWSEL_HW0_Pos                   0                                                       /*!< PORT0 HWSEL: HW0 Position               */\r
+#define PORT0_HWSEL_HW0_Msk                   (0x03UL << PORT0_HWSEL_HW0_Pos)                         /*!< PORT0 HWSEL: HW0 Mask                   */\r
+#define PORT0_HWSEL_HW1_Pos                   2                                                       /*!< PORT0 HWSEL: HW1 Position               */\r
+#define PORT0_HWSEL_HW1_Msk                   (0x03UL << PORT0_HWSEL_HW1_Pos)                         /*!< PORT0 HWSEL: HW1 Mask                   */\r
+#define PORT0_HWSEL_HW2_Pos                   4                                                       /*!< PORT0 HWSEL: HW2 Position               */\r
+#define PORT0_HWSEL_HW2_Msk                   (0x03UL << PORT0_HWSEL_HW2_Pos)                         /*!< PORT0 HWSEL: HW2 Mask                   */\r
+#define PORT0_HWSEL_HW3_Pos                   6                                                       /*!< PORT0 HWSEL: HW3 Position               */\r
+#define PORT0_HWSEL_HW3_Msk                   (0x03UL << PORT0_HWSEL_HW3_Pos)                         /*!< PORT0 HWSEL: HW3 Mask                   */\r
+#define PORT0_HWSEL_HW4_Pos                   8                                                       /*!< PORT0 HWSEL: HW4 Position               */\r
+#define PORT0_HWSEL_HW4_Msk                   (0x03UL << PORT0_HWSEL_HW4_Pos)                         /*!< PORT0 HWSEL: HW4 Mask                   */\r
+#define PORT0_HWSEL_HW5_Pos                   10                                                      /*!< PORT0 HWSEL: HW5 Position               */\r
+#define PORT0_HWSEL_HW5_Msk                   (0x03UL << PORT0_HWSEL_HW5_Pos)                         /*!< PORT0 HWSEL: HW5 Mask                   */\r
+#define PORT0_HWSEL_HW6_Pos                   12                                                      /*!< PORT0 HWSEL: HW6 Position               */\r
+#define PORT0_HWSEL_HW6_Msk                   (0x03UL << PORT0_HWSEL_HW6_Pos)                         /*!< PORT0 HWSEL: HW6 Mask                   */\r
+#define PORT0_HWSEL_HW7_Pos                   14                                                      /*!< PORT0 HWSEL: HW7 Position               */\r
+#define PORT0_HWSEL_HW7_Msk                   (0x03UL << PORT0_HWSEL_HW7_Pos)                         /*!< PORT0 HWSEL: HW7 Mask                   */\r
+#define PORT0_HWSEL_HW8_Pos                   16                                                      /*!< PORT0 HWSEL: HW8 Position               */\r
+#define PORT0_HWSEL_HW8_Msk                   (0x03UL << PORT0_HWSEL_HW8_Pos)                         /*!< PORT0 HWSEL: HW8 Mask                   */\r
+#define PORT0_HWSEL_HW9_Pos                   18                                                      /*!< PORT0 HWSEL: HW9 Position               */\r
+#define PORT0_HWSEL_HW9_Msk                   (0x03UL << PORT0_HWSEL_HW9_Pos)                         /*!< PORT0 HWSEL: HW9 Mask                   */\r
+#define PORT0_HWSEL_HW10_Pos                  20                                                      /*!< PORT0 HWSEL: HW10 Position              */\r
+#define PORT0_HWSEL_HW10_Msk                  (0x03UL << PORT0_HWSEL_HW10_Pos)                        /*!< PORT0 HWSEL: HW10 Mask                  */\r
+#define PORT0_HWSEL_HW11_Pos                  22                                                      /*!< PORT0 HWSEL: HW11 Position              */\r
+#define PORT0_HWSEL_HW11_Msk                  (0x03UL << PORT0_HWSEL_HW11_Pos)                        /*!< PORT0 HWSEL: HW11 Mask                  */\r
+#define PORT0_HWSEL_HW12_Pos                  24                                                      /*!< PORT0 HWSEL: HW12 Position              */\r
+#define PORT0_HWSEL_HW12_Msk                  (0x03UL << PORT0_HWSEL_HW12_Pos)                        /*!< PORT0 HWSEL: HW12 Mask                  */\r
+#define PORT0_HWSEL_HW13_Pos                  26                                                      /*!< PORT0 HWSEL: HW13 Position              */\r
+#define PORT0_HWSEL_HW13_Msk                  (0x03UL << PORT0_HWSEL_HW13_Pos)                        /*!< PORT0 HWSEL: HW13 Mask                  */\r
+#define PORT0_HWSEL_HW14_Pos                  28                                                      /*!< PORT0 HWSEL: HW14 Position              */\r
+#define PORT0_HWSEL_HW14_Msk                  (0x03UL << PORT0_HWSEL_HW14_Pos)                        /*!< PORT0 HWSEL: HW14 Mask                  */\r
+#define PORT0_HWSEL_HW15_Pos                  30                                                      /*!< PORT0 HWSEL: HW15 Position              */\r
+#define PORT0_HWSEL_HW15_Msk                  (0x03UL << PORT0_HWSEL_HW15_Pos)                        /*!< PORT0 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT1' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT1_OUT  --------------------------------- */\r
+#define PORT1_OUT_P0_Pos                      0                                                       /*!< PORT1 OUT: P0 Position                  */\r
+#define PORT1_OUT_P0_Msk                      (0x01UL << PORT1_OUT_P0_Pos)                            /*!< PORT1 OUT: P0 Mask                      */\r
+#define PORT1_OUT_P1_Pos                      1                                                       /*!< PORT1 OUT: P1 Position                  */\r
+#define PORT1_OUT_P1_Msk                      (0x01UL << PORT1_OUT_P1_Pos)                            /*!< PORT1 OUT: P1 Mask                      */\r
+#define PORT1_OUT_P2_Pos                      2                                                       /*!< PORT1 OUT: P2 Position                  */\r
+#define PORT1_OUT_P2_Msk                      (0x01UL << PORT1_OUT_P2_Pos)                            /*!< PORT1 OUT: P2 Mask                      */\r
+#define PORT1_OUT_P3_Pos                      3                                                       /*!< PORT1 OUT: P3 Position                  */\r
+#define PORT1_OUT_P3_Msk                      (0x01UL << PORT1_OUT_P3_Pos)                            /*!< PORT1 OUT: P3 Mask                      */\r
+#define PORT1_OUT_P4_Pos                      4                                                       /*!< PORT1 OUT: P4 Position                  */\r
+#define PORT1_OUT_P4_Msk                      (0x01UL << PORT1_OUT_P4_Pos)                            /*!< PORT1 OUT: P4 Mask                      */\r
+#define PORT1_OUT_P5_Pos                      5                                                       /*!< PORT1 OUT: P5 Position                  */\r
+#define PORT1_OUT_P5_Msk                      (0x01UL << PORT1_OUT_P5_Pos)                            /*!< PORT1 OUT: P5 Mask                      */\r
+#define PORT1_OUT_P6_Pos                      6                                                       /*!< PORT1 OUT: P6 Position                  */\r
+#define PORT1_OUT_P6_Msk                      (0x01UL << PORT1_OUT_P6_Pos)                            /*!< PORT1 OUT: P6 Mask                      */\r
+#define PORT1_OUT_P7_Pos                      7                                                       /*!< PORT1 OUT: P7 Position                  */\r
+#define PORT1_OUT_P7_Msk                      (0x01UL << PORT1_OUT_P7_Pos)                            /*!< PORT1 OUT: P7 Mask                      */\r
+#define PORT1_OUT_P8_Pos                      8                                                       /*!< PORT1 OUT: P8 Position                  */\r
+#define PORT1_OUT_P8_Msk                      (0x01UL << PORT1_OUT_P8_Pos)                            /*!< PORT1 OUT: P8 Mask                      */\r
+#define PORT1_OUT_P9_Pos                      9                                                       /*!< PORT1 OUT: P9 Position                  */\r
+#define PORT1_OUT_P9_Msk                      (0x01UL << PORT1_OUT_P9_Pos)                            /*!< PORT1 OUT: P9 Mask                      */\r
+#define PORT1_OUT_P10_Pos                     10                                                      /*!< PORT1 OUT: P10 Position                 */\r
+#define PORT1_OUT_P10_Msk                     (0x01UL << PORT1_OUT_P10_Pos)                           /*!< PORT1 OUT: P10 Mask                     */\r
+#define PORT1_OUT_P11_Pos                     11                                                      /*!< PORT1 OUT: P11 Position                 */\r
+#define PORT1_OUT_P11_Msk                     (0x01UL << PORT1_OUT_P11_Pos)                           /*!< PORT1 OUT: P11 Mask                     */\r
+#define PORT1_OUT_P12_Pos                     12                                                      /*!< PORT1 OUT: P12 Position                 */\r
+#define PORT1_OUT_P12_Msk                     (0x01UL << PORT1_OUT_P12_Pos)                           /*!< PORT1 OUT: P12 Mask                     */\r
+#define PORT1_OUT_P13_Pos                     13                                                      /*!< PORT1 OUT: P13 Position                 */\r
+#define PORT1_OUT_P13_Msk                     (0x01UL << PORT1_OUT_P13_Pos)                           /*!< PORT1 OUT: P13 Mask                     */\r
+#define PORT1_OUT_P14_Pos                     14                                                      /*!< PORT1 OUT: P14 Position                 */\r
+#define PORT1_OUT_P14_Msk                     (0x01UL << PORT1_OUT_P14_Pos)                           /*!< PORT1 OUT: P14 Mask                     */\r
+#define PORT1_OUT_P15_Pos                     15                                                      /*!< PORT1 OUT: P15 Position                 */\r
+#define PORT1_OUT_P15_Msk                     (0x01UL << PORT1_OUT_P15_Pos)                           /*!< PORT1 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT1_OMR  --------------------------------- */\r
+#define PORT1_OMR_PS0_Pos                     0                                                       /*!< PORT1 OMR: PS0 Position                 */\r
+#define PORT1_OMR_PS0_Msk                     (0x01UL << PORT1_OMR_PS0_Pos)                           /*!< PORT1 OMR: PS0 Mask                     */\r
+#define PORT1_OMR_PS1_Pos                     1                                                       /*!< PORT1 OMR: PS1 Position                 */\r
+#define PORT1_OMR_PS1_Msk                     (0x01UL << PORT1_OMR_PS1_Pos)                           /*!< PORT1 OMR: PS1 Mask                     */\r
+#define PORT1_OMR_PS2_Pos                     2                                                       /*!< PORT1 OMR: PS2 Position                 */\r
+#define PORT1_OMR_PS2_Msk                     (0x01UL << PORT1_OMR_PS2_Pos)                           /*!< PORT1 OMR: PS2 Mask                     */\r
+#define PORT1_OMR_PS3_Pos                     3                                                       /*!< PORT1 OMR: PS3 Position                 */\r
+#define PORT1_OMR_PS3_Msk                     (0x01UL << PORT1_OMR_PS3_Pos)                           /*!< PORT1 OMR: PS3 Mask                     */\r
+#define PORT1_OMR_PS4_Pos                     4                                                       /*!< PORT1 OMR: PS4 Position                 */\r
+#define PORT1_OMR_PS4_Msk                     (0x01UL << PORT1_OMR_PS4_Pos)                           /*!< PORT1 OMR: PS4 Mask                     */\r
+#define PORT1_OMR_PS5_Pos                     5                                                       /*!< PORT1 OMR: PS5 Position                 */\r
+#define PORT1_OMR_PS5_Msk                     (0x01UL << PORT1_OMR_PS5_Pos)                           /*!< PORT1 OMR: PS5 Mask                     */\r
+#define PORT1_OMR_PS6_Pos                     6                                                       /*!< PORT1 OMR: PS6 Position                 */\r
+#define PORT1_OMR_PS6_Msk                     (0x01UL << PORT1_OMR_PS6_Pos)                           /*!< PORT1 OMR: PS6 Mask                     */\r
+#define PORT1_OMR_PS7_Pos                     7                                                       /*!< PORT1 OMR: PS7 Position                 */\r
+#define PORT1_OMR_PS7_Msk                     (0x01UL << PORT1_OMR_PS7_Pos)                           /*!< PORT1 OMR: PS7 Mask                     */\r
+#define PORT1_OMR_PS8_Pos                     8                                                       /*!< PORT1 OMR: PS8 Position                 */\r
+#define PORT1_OMR_PS8_Msk                     (0x01UL << PORT1_OMR_PS8_Pos)                           /*!< PORT1 OMR: PS8 Mask                     */\r
+#define PORT1_OMR_PS9_Pos                     9                                                       /*!< PORT1 OMR: PS9 Position                 */\r
+#define PORT1_OMR_PS9_Msk                     (0x01UL << PORT1_OMR_PS9_Pos)                           /*!< PORT1 OMR: PS9 Mask                     */\r
+#define PORT1_OMR_PS10_Pos                    10                                                      /*!< PORT1 OMR: PS10 Position                */\r
+#define PORT1_OMR_PS10_Msk                    (0x01UL << PORT1_OMR_PS10_Pos)                          /*!< PORT1 OMR: PS10 Mask                    */\r
+#define PORT1_OMR_PS11_Pos                    11                                                      /*!< PORT1 OMR: PS11 Position                */\r
+#define PORT1_OMR_PS11_Msk                    (0x01UL << PORT1_OMR_PS11_Pos)                          /*!< PORT1 OMR: PS11 Mask                    */\r
+#define PORT1_OMR_PS12_Pos                    12                                                      /*!< PORT1 OMR: PS12 Position                */\r
+#define PORT1_OMR_PS12_Msk                    (0x01UL << PORT1_OMR_PS12_Pos)                          /*!< PORT1 OMR: PS12 Mask                    */\r
+#define PORT1_OMR_PS13_Pos                    13                                                      /*!< PORT1 OMR: PS13 Position                */\r
+#define PORT1_OMR_PS13_Msk                    (0x01UL << PORT1_OMR_PS13_Pos)                          /*!< PORT1 OMR: PS13 Mask                    */\r
+#define PORT1_OMR_PS14_Pos                    14                                                      /*!< PORT1 OMR: PS14 Position                */\r
+#define PORT1_OMR_PS14_Msk                    (0x01UL << PORT1_OMR_PS14_Pos)                          /*!< PORT1 OMR: PS14 Mask                    */\r
+#define PORT1_OMR_PS15_Pos                    15                                                      /*!< PORT1 OMR: PS15 Position                */\r
+#define PORT1_OMR_PS15_Msk                    (0x01UL << PORT1_OMR_PS15_Pos)                          /*!< PORT1 OMR: PS15 Mask                    */\r
+#define PORT1_OMR_PR0_Pos                     16                                                      /*!< PORT1 OMR: PR0 Position                 */\r
+#define PORT1_OMR_PR0_Msk                     (0x01UL << PORT1_OMR_PR0_Pos)                           /*!< PORT1 OMR: PR0 Mask                     */\r
+#define PORT1_OMR_PR1_Pos                     17                                                      /*!< PORT1 OMR: PR1 Position                 */\r
+#define PORT1_OMR_PR1_Msk                     (0x01UL << PORT1_OMR_PR1_Pos)                           /*!< PORT1 OMR: PR1 Mask                     */\r
+#define PORT1_OMR_PR2_Pos                     18                                                      /*!< PORT1 OMR: PR2 Position                 */\r
+#define PORT1_OMR_PR2_Msk                     (0x01UL << PORT1_OMR_PR2_Pos)                           /*!< PORT1 OMR: PR2 Mask                     */\r
+#define PORT1_OMR_PR3_Pos                     19                                                      /*!< PORT1 OMR: PR3 Position                 */\r
+#define PORT1_OMR_PR3_Msk                     (0x01UL << PORT1_OMR_PR3_Pos)                           /*!< PORT1 OMR: PR3 Mask                     */\r
+#define PORT1_OMR_PR4_Pos                     20                                                      /*!< PORT1 OMR: PR4 Position                 */\r
+#define PORT1_OMR_PR4_Msk                     (0x01UL << PORT1_OMR_PR4_Pos)                           /*!< PORT1 OMR: PR4 Mask                     */\r
+#define PORT1_OMR_PR5_Pos                     21                                                      /*!< PORT1 OMR: PR5 Position                 */\r
+#define PORT1_OMR_PR5_Msk                     (0x01UL << PORT1_OMR_PR5_Pos)                           /*!< PORT1 OMR: PR5 Mask                     */\r
+#define PORT1_OMR_PR6_Pos                     22                                                      /*!< PORT1 OMR: PR6 Position                 */\r
+#define PORT1_OMR_PR6_Msk                     (0x01UL << PORT1_OMR_PR6_Pos)                           /*!< PORT1 OMR: PR6 Mask                     */\r
+#define PORT1_OMR_PR7_Pos                     23                                                      /*!< PORT1 OMR: PR7 Position                 */\r
+#define PORT1_OMR_PR7_Msk                     (0x01UL << PORT1_OMR_PR7_Pos)                           /*!< PORT1 OMR: PR7 Mask                     */\r
+#define PORT1_OMR_PR8_Pos                     24                                                      /*!< PORT1 OMR: PR8 Position                 */\r
+#define PORT1_OMR_PR8_Msk                     (0x01UL << PORT1_OMR_PR8_Pos)                           /*!< PORT1 OMR: PR8 Mask                     */\r
+#define PORT1_OMR_PR9_Pos                     25                                                      /*!< PORT1 OMR: PR9 Position                 */\r
+#define PORT1_OMR_PR9_Msk                     (0x01UL << PORT1_OMR_PR9_Pos)                           /*!< PORT1 OMR: PR9 Mask                     */\r
+#define PORT1_OMR_PR10_Pos                    26                                                      /*!< PORT1 OMR: PR10 Position                */\r
+#define PORT1_OMR_PR10_Msk                    (0x01UL << PORT1_OMR_PR10_Pos)                          /*!< PORT1 OMR: PR10 Mask                    */\r
+#define PORT1_OMR_PR11_Pos                    27                                                      /*!< PORT1 OMR: PR11 Position                */\r
+#define PORT1_OMR_PR11_Msk                    (0x01UL << PORT1_OMR_PR11_Pos)                          /*!< PORT1 OMR: PR11 Mask                    */\r
+#define PORT1_OMR_PR12_Pos                    28                                                      /*!< PORT1 OMR: PR12 Position                */\r
+#define PORT1_OMR_PR12_Msk                    (0x01UL << PORT1_OMR_PR12_Pos)                          /*!< PORT1 OMR: PR12 Mask                    */\r
+#define PORT1_OMR_PR13_Pos                    29                                                      /*!< PORT1 OMR: PR13 Position                */\r
+#define PORT1_OMR_PR13_Msk                    (0x01UL << PORT1_OMR_PR13_Pos)                          /*!< PORT1 OMR: PR13 Mask                    */\r
+#define PORT1_OMR_PR14_Pos                    30                                                      /*!< PORT1 OMR: PR14 Position                */\r
+#define PORT1_OMR_PR14_Msk                    (0x01UL << PORT1_OMR_PR14_Pos)                          /*!< PORT1 OMR: PR14 Mask                    */\r
+#define PORT1_OMR_PR15_Pos                    31                                                      /*!< PORT1 OMR: PR15 Position                */\r
+#define PORT1_OMR_PR15_Msk                    (0x01UL << PORT1_OMR_PR15_Pos)                          /*!< PORT1 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT1_IOCR0  -------------------------------- */\r
+#define PORT1_IOCR0_PC0_Pos                   3                                                       /*!< PORT1 IOCR0: PC0 Position               */\r
+#define PORT1_IOCR0_PC0_Msk                   (0x1fUL << PORT1_IOCR0_PC0_Pos)                         /*!< PORT1 IOCR0: PC0 Mask                   */\r
+#define PORT1_IOCR0_PC1_Pos                   11                                                      /*!< PORT1 IOCR0: PC1 Position               */\r
+#define PORT1_IOCR0_PC1_Msk                   (0x1fUL << PORT1_IOCR0_PC1_Pos)                         /*!< PORT1 IOCR0: PC1 Mask                   */\r
+#define PORT1_IOCR0_PC2_Pos                   19                                                      /*!< PORT1 IOCR0: PC2 Position               */\r
+#define PORT1_IOCR0_PC2_Msk                   (0x1fUL << PORT1_IOCR0_PC2_Pos)                         /*!< PORT1 IOCR0: PC2 Mask                   */\r
+#define PORT1_IOCR0_PC3_Pos                   27                                                      /*!< PORT1 IOCR0: PC3 Position               */\r
+#define PORT1_IOCR0_PC3_Msk                   (0x1fUL << PORT1_IOCR0_PC3_Pos)                         /*!< PORT1 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_IOCR4  -------------------------------- */\r
+#define PORT1_IOCR4_PC4_Pos                   3                                                       /*!< PORT1 IOCR4: PC4 Position               */\r
+#define PORT1_IOCR4_PC4_Msk                   (0x1fUL << PORT1_IOCR4_PC4_Pos)                         /*!< PORT1 IOCR4: PC4 Mask                   */\r
+#define PORT1_IOCR4_PC5_Pos                   11                                                      /*!< PORT1 IOCR4: PC5 Position               */\r
+#define PORT1_IOCR4_PC5_Msk                   (0x1fUL << PORT1_IOCR4_PC5_Pos)                         /*!< PORT1 IOCR4: PC5 Mask                   */\r
+#define PORT1_IOCR4_PC6_Pos                   19                                                      /*!< PORT1 IOCR4: PC6 Position               */\r
+#define PORT1_IOCR4_PC6_Msk                   (0x1fUL << PORT1_IOCR4_PC6_Pos)                         /*!< PORT1 IOCR4: PC6 Mask                   */\r
+#define PORT1_IOCR4_PC7_Pos                   27                                                      /*!< PORT1 IOCR4: PC7 Position               */\r
+#define PORT1_IOCR4_PC7_Msk                   (0x1fUL << PORT1_IOCR4_PC7_Pos)                         /*!< PORT1 IOCR4: PC7 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_IOCR8  -------------------------------- */\r
+#define PORT1_IOCR8_PC8_Pos                   3                                                       /*!< PORT1 IOCR8: PC8 Position               */\r
+#define PORT1_IOCR8_PC8_Msk                   (0x1fUL << PORT1_IOCR8_PC8_Pos)                         /*!< PORT1 IOCR8: PC8 Mask                   */\r
+#define PORT1_IOCR8_PC9_Pos                   11                                                      /*!< PORT1 IOCR8: PC9 Position               */\r
+#define PORT1_IOCR8_PC9_Msk                   (0x1fUL << PORT1_IOCR8_PC9_Pos)                         /*!< PORT1 IOCR8: PC9 Mask                   */\r
+#define PORT1_IOCR8_PC10_Pos                  19                                                      /*!< PORT1 IOCR8: PC10 Position              */\r
+#define PORT1_IOCR8_PC10_Msk                  (0x1fUL << PORT1_IOCR8_PC10_Pos)                        /*!< PORT1 IOCR8: PC10 Mask                  */\r
+#define PORT1_IOCR8_PC11_Pos                  27                                                      /*!< PORT1 IOCR8: PC11 Position              */\r
+#define PORT1_IOCR8_PC11_Msk                  (0x1fUL << PORT1_IOCR8_PC11_Pos)                        /*!< PORT1 IOCR8: PC11 Mask                  */\r
+\r
+/* --------------------------------  PORT1_IOCR12  -------------------------------- */\r
+#define PORT1_IOCR12_PC12_Pos                 3                                                       /*!< PORT1 IOCR12: PC12 Position             */\r
+#define PORT1_IOCR12_PC12_Msk                 (0x1fUL << PORT1_IOCR12_PC12_Pos)                       /*!< PORT1 IOCR12: PC12 Mask                 */\r
+#define PORT1_IOCR12_PC13_Pos                 11                                                      /*!< PORT1 IOCR12: PC13 Position             */\r
+#define PORT1_IOCR12_PC13_Msk                 (0x1fUL << PORT1_IOCR12_PC13_Pos)                       /*!< PORT1 IOCR12: PC13 Mask                 */\r
+#define PORT1_IOCR12_PC14_Pos                 19                                                      /*!< PORT1 IOCR12: PC14 Position             */\r
+#define PORT1_IOCR12_PC14_Msk                 (0x1fUL << PORT1_IOCR12_PC14_Pos)                       /*!< PORT1 IOCR12: PC14 Mask                 */\r
+#define PORT1_IOCR12_PC15_Pos                 27                                                      /*!< PORT1 IOCR12: PC15 Position             */\r
+#define PORT1_IOCR12_PC15_Msk                 (0x1fUL << PORT1_IOCR12_PC15_Pos)                       /*!< PORT1 IOCR12: PC15 Mask                 */\r
+\r
+/* ----------------------------------  PORT1_IN  ---------------------------------- */\r
+#define PORT1_IN_P0_Pos                       0                                                       /*!< PORT1 IN: P0 Position                   */\r
+#define PORT1_IN_P0_Msk                       (0x01UL << PORT1_IN_P0_Pos)                             /*!< PORT1 IN: P0 Mask                       */\r
+#define PORT1_IN_P1_Pos                       1                                                       /*!< PORT1 IN: P1 Position                   */\r
+#define PORT1_IN_P1_Msk                       (0x01UL << PORT1_IN_P1_Pos)                             /*!< PORT1 IN: P1 Mask                       */\r
+#define PORT1_IN_P2_Pos                       2                                                       /*!< PORT1 IN: P2 Position                   */\r
+#define PORT1_IN_P2_Msk                       (0x01UL << PORT1_IN_P2_Pos)                             /*!< PORT1 IN: P2 Mask                       */\r
+#define PORT1_IN_P3_Pos                       3                                                       /*!< PORT1 IN: P3 Position                   */\r
+#define PORT1_IN_P3_Msk                       (0x01UL << PORT1_IN_P3_Pos)                             /*!< PORT1 IN: P3 Mask                       */\r
+#define PORT1_IN_P4_Pos                       4                                                       /*!< PORT1 IN: P4 Position                   */\r
+#define PORT1_IN_P4_Msk                       (0x01UL << PORT1_IN_P4_Pos)                             /*!< PORT1 IN: P4 Mask                       */\r
+#define PORT1_IN_P5_Pos                       5                                                       /*!< PORT1 IN: P5 Position                   */\r
+#define PORT1_IN_P5_Msk                       (0x01UL << PORT1_IN_P5_Pos)                             /*!< PORT1 IN: P5 Mask                       */\r
+#define PORT1_IN_P6_Pos                       6                                                       /*!< PORT1 IN: P6 Position                   */\r
+#define PORT1_IN_P6_Msk                       (0x01UL << PORT1_IN_P6_Pos)                             /*!< PORT1 IN: P6 Mask                       */\r
+#define PORT1_IN_P7_Pos                       7                                                       /*!< PORT1 IN: P7 Position                   */\r
+#define PORT1_IN_P7_Msk                       (0x01UL << PORT1_IN_P7_Pos)                             /*!< PORT1 IN: P7 Mask                       */\r
+#define PORT1_IN_P8_Pos                       8                                                       /*!< PORT1 IN: P8 Position                   */\r
+#define PORT1_IN_P8_Msk                       (0x01UL << PORT1_IN_P8_Pos)                             /*!< PORT1 IN: P8 Mask                       */\r
+#define PORT1_IN_P9_Pos                       9                                                       /*!< PORT1 IN: P9 Position                   */\r
+#define PORT1_IN_P9_Msk                       (0x01UL << PORT1_IN_P9_Pos)                             /*!< PORT1 IN: P9 Mask                       */\r
+#define PORT1_IN_P10_Pos                      10                                                      /*!< PORT1 IN: P10 Position                  */\r
+#define PORT1_IN_P10_Msk                      (0x01UL << PORT1_IN_P10_Pos)                            /*!< PORT1 IN: P10 Mask                      */\r
+#define PORT1_IN_P11_Pos                      11                                                      /*!< PORT1 IN: P11 Position                  */\r
+#define PORT1_IN_P11_Msk                      (0x01UL << PORT1_IN_P11_Pos)                            /*!< PORT1 IN: P11 Mask                      */\r
+#define PORT1_IN_P12_Pos                      12                                                      /*!< PORT1 IN: P12 Position                  */\r
+#define PORT1_IN_P12_Msk                      (0x01UL << PORT1_IN_P12_Pos)                            /*!< PORT1 IN: P12 Mask                      */\r
+#define PORT1_IN_P13_Pos                      13                                                      /*!< PORT1 IN: P13 Position                  */\r
+#define PORT1_IN_P13_Msk                      (0x01UL << PORT1_IN_P13_Pos)                            /*!< PORT1 IN: P13 Mask                      */\r
+#define PORT1_IN_P14_Pos                      14                                                      /*!< PORT1 IN: P14 Position                  */\r
+#define PORT1_IN_P14_Msk                      (0x01UL << PORT1_IN_P14_Pos)                            /*!< PORT1 IN: P14 Mask                      */\r
+#define PORT1_IN_P15_Pos                      15                                                      /*!< PORT1 IN: P15 Position                  */\r
+#define PORT1_IN_P15_Msk                      (0x01UL << PORT1_IN_P15_Pos)                            /*!< PORT1 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT1_PDR0  --------------------------------- */\r
+#define PORT1_PDR0_PD0_Pos                    0                                                       /*!< PORT1 PDR0: PD0 Position                */\r
+#define PORT1_PDR0_PD0_Msk                    (0x07UL << PORT1_PDR0_PD0_Pos)                          /*!< PORT1 PDR0: PD0 Mask                    */\r
+#define PORT1_PDR0_PD1_Pos                    4                                                       /*!< PORT1 PDR0: PD1 Position                */\r
+#define PORT1_PDR0_PD1_Msk                    (0x07UL << PORT1_PDR0_PD1_Pos)                          /*!< PORT1 PDR0: PD1 Mask                    */\r
+#define PORT1_PDR0_PD2_Pos                    8                                                       /*!< PORT1 PDR0: PD2 Position                */\r
+#define PORT1_PDR0_PD2_Msk                    (0x07UL << PORT1_PDR0_PD2_Pos)                          /*!< PORT1 PDR0: PD2 Mask                    */\r
+#define PORT1_PDR0_PD3_Pos                    12                                                      /*!< PORT1 PDR0: PD3 Position                */\r
+#define PORT1_PDR0_PD3_Msk                    (0x07UL << PORT1_PDR0_PD3_Pos)                          /*!< PORT1 PDR0: PD3 Mask                    */\r
+#define PORT1_PDR0_PD4_Pos                    16                                                      /*!< PORT1 PDR0: PD4 Position                */\r
+#define PORT1_PDR0_PD4_Msk                    (0x07UL << PORT1_PDR0_PD4_Pos)                          /*!< PORT1 PDR0: PD4 Mask                    */\r
+#define PORT1_PDR0_PD5_Pos                    20                                                      /*!< PORT1 PDR0: PD5 Position                */\r
+#define PORT1_PDR0_PD5_Msk                    (0x07UL << PORT1_PDR0_PD5_Pos)                          /*!< PORT1 PDR0: PD5 Mask                    */\r
+#define PORT1_PDR0_PD6_Pos                    24                                                      /*!< PORT1 PDR0: PD6 Position                */\r
+#define PORT1_PDR0_PD6_Msk                    (0x07UL << PORT1_PDR0_PD6_Pos)                          /*!< PORT1 PDR0: PD6 Mask                    */\r
+#define PORT1_PDR0_PD7_Pos                    28                                                      /*!< PORT1 PDR0: PD7 Position                */\r
+#define PORT1_PDR0_PD7_Msk                    (0x07UL << PORT1_PDR0_PD7_Pos)                          /*!< PORT1 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT1_PDR1  --------------------------------- */\r
+#define PORT1_PDR1_PD8_Pos                    0                                                       /*!< PORT1 PDR1: PD8 Position                */\r
+#define PORT1_PDR1_PD8_Msk                    (0x07UL << PORT1_PDR1_PD8_Pos)                          /*!< PORT1 PDR1: PD8 Mask                    */\r
+#define PORT1_PDR1_PD9_Pos                    4                                                       /*!< PORT1 PDR1: PD9 Position                */\r
+#define PORT1_PDR1_PD9_Msk                    (0x07UL << PORT1_PDR1_PD9_Pos)                          /*!< PORT1 PDR1: PD9 Mask                    */\r
+#define PORT1_PDR1_PD10_Pos                   8                                                       /*!< PORT1 PDR1: PD10 Position               */\r
+#define PORT1_PDR1_PD10_Msk                   (0x07UL << PORT1_PDR1_PD10_Pos)                         /*!< PORT1 PDR1: PD10 Mask                   */\r
+#define PORT1_PDR1_PD11_Pos                   12                                                      /*!< PORT1 PDR1: PD11 Position               */\r
+#define PORT1_PDR1_PD11_Msk                   (0x07UL << PORT1_PDR1_PD11_Pos)                         /*!< PORT1 PDR1: PD11 Mask                   */\r
+#define PORT1_PDR1_PD12_Pos                   16                                                      /*!< PORT1 PDR1: PD12 Position               */\r
+#define PORT1_PDR1_PD12_Msk                   (0x07UL << PORT1_PDR1_PD12_Pos)                         /*!< PORT1 PDR1: PD12 Mask                   */\r
+#define PORT1_PDR1_PD13_Pos                   20                                                      /*!< PORT1 PDR1: PD13 Position               */\r
+#define PORT1_PDR1_PD13_Msk                   (0x07UL << PORT1_PDR1_PD13_Pos)                         /*!< PORT1 PDR1: PD13 Mask                   */\r
+#define PORT1_PDR1_PD14_Pos                   24                                                      /*!< PORT1 PDR1: PD14 Position               */\r
+#define PORT1_PDR1_PD14_Msk                   (0x07UL << PORT1_PDR1_PD14_Pos)                         /*!< PORT1 PDR1: PD14 Mask                   */\r
+#define PORT1_PDR1_PD15_Pos                   28                                                      /*!< PORT1 PDR1: PD15 Position               */\r
+#define PORT1_PDR1_PD15_Msk                   (0x07UL << PORT1_PDR1_PD15_Pos)                         /*!< PORT1 PDR1: PD15 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_PDISC  -------------------------------- */\r
+#define PORT1_PDISC_PDIS0_Pos                 0                                                       /*!< PORT1 PDISC: PDIS0 Position             */\r
+#define PORT1_PDISC_PDIS0_Msk                 (0x01UL << PORT1_PDISC_PDIS0_Pos)                       /*!< PORT1 PDISC: PDIS0 Mask                 */\r
+#define PORT1_PDISC_PDIS1_Pos                 1                                                       /*!< PORT1 PDISC: PDIS1 Position             */\r
+#define PORT1_PDISC_PDIS1_Msk                 (0x01UL << PORT1_PDISC_PDIS1_Pos)                       /*!< PORT1 PDISC: PDIS1 Mask                 */\r
+#define PORT1_PDISC_PDIS2_Pos                 2                                                       /*!< PORT1 PDISC: PDIS2 Position             */\r
+#define PORT1_PDISC_PDIS2_Msk                 (0x01UL << PORT1_PDISC_PDIS2_Pos)                       /*!< PORT1 PDISC: PDIS2 Mask                 */\r
+#define PORT1_PDISC_PDIS3_Pos                 3                                                       /*!< PORT1 PDISC: PDIS3 Position             */\r
+#define PORT1_PDISC_PDIS3_Msk                 (0x01UL << PORT1_PDISC_PDIS3_Pos)                       /*!< PORT1 PDISC: PDIS3 Mask                 */\r
+#define PORT1_PDISC_PDIS4_Pos                 4                                                       /*!< PORT1 PDISC: PDIS4 Position             */\r
+#define PORT1_PDISC_PDIS4_Msk                 (0x01UL << PORT1_PDISC_PDIS4_Pos)                       /*!< PORT1 PDISC: PDIS4 Mask                 */\r
+#define PORT1_PDISC_PDIS5_Pos                 5                                                       /*!< PORT1 PDISC: PDIS5 Position             */\r
+#define PORT1_PDISC_PDIS5_Msk                 (0x01UL << PORT1_PDISC_PDIS5_Pos)                       /*!< PORT1 PDISC: PDIS5 Mask                 */\r
+#define PORT1_PDISC_PDIS6_Pos                 6                                                       /*!< PORT1 PDISC: PDIS6 Position             */\r
+#define PORT1_PDISC_PDIS6_Msk                 (0x01UL << PORT1_PDISC_PDIS6_Pos)                       /*!< PORT1 PDISC: PDIS6 Mask                 */\r
+#define PORT1_PDISC_PDIS7_Pos                 7                                                       /*!< PORT1 PDISC: PDIS7 Position             */\r
+#define PORT1_PDISC_PDIS7_Msk                 (0x01UL << PORT1_PDISC_PDIS7_Pos)                       /*!< PORT1 PDISC: PDIS7 Mask                 */\r
+#define PORT1_PDISC_PDIS8_Pos                 8                                                       /*!< PORT1 PDISC: PDIS8 Position             */\r
+#define PORT1_PDISC_PDIS8_Msk                 (0x01UL << PORT1_PDISC_PDIS8_Pos)                       /*!< PORT1 PDISC: PDIS8 Mask                 */\r
+#define PORT1_PDISC_PDIS9_Pos                 9                                                       /*!< PORT1 PDISC: PDIS9 Position             */\r
+#define PORT1_PDISC_PDIS9_Msk                 (0x01UL << PORT1_PDISC_PDIS9_Pos)                       /*!< PORT1 PDISC: PDIS9 Mask                 */\r
+#define PORT1_PDISC_PDIS10_Pos                10                                                      /*!< PORT1 PDISC: PDIS10 Position            */\r
+#define PORT1_PDISC_PDIS10_Msk                (0x01UL << PORT1_PDISC_PDIS10_Pos)                      /*!< PORT1 PDISC: PDIS10 Mask                */\r
+#define PORT1_PDISC_PDIS11_Pos                11                                                      /*!< PORT1 PDISC: PDIS11 Position            */\r
+#define PORT1_PDISC_PDIS11_Msk                (0x01UL << PORT1_PDISC_PDIS11_Pos)                      /*!< PORT1 PDISC: PDIS11 Mask                */\r
+#define PORT1_PDISC_PDIS12_Pos                12                                                      /*!< PORT1 PDISC: PDIS12 Position            */\r
+#define PORT1_PDISC_PDIS12_Msk                (0x01UL << PORT1_PDISC_PDIS12_Pos)                      /*!< PORT1 PDISC: PDIS12 Mask                */\r
+#define PORT1_PDISC_PDIS13_Pos                13                                                      /*!< PORT1 PDISC: PDIS13 Position            */\r
+#define PORT1_PDISC_PDIS13_Msk                (0x01UL << PORT1_PDISC_PDIS13_Pos)                      /*!< PORT1 PDISC: PDIS13 Mask                */\r
+#define PORT1_PDISC_PDIS14_Pos                14                                                      /*!< PORT1 PDISC: PDIS14 Position            */\r
+#define PORT1_PDISC_PDIS14_Msk                (0x01UL << PORT1_PDISC_PDIS14_Pos)                      /*!< PORT1 PDISC: PDIS14 Mask                */\r
+#define PORT1_PDISC_PDIS15_Pos                15                                                      /*!< PORT1 PDISC: PDIS15 Position            */\r
+#define PORT1_PDISC_PDIS15_Msk                (0x01UL << PORT1_PDISC_PDIS15_Pos)                      /*!< PORT1 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT1_PPS  --------------------------------- */\r
+#define PORT1_PPS_PPS0_Pos                    0                                                       /*!< PORT1 PPS: PPS0 Position                */\r
+#define PORT1_PPS_PPS0_Msk                    (0x01UL << PORT1_PPS_PPS0_Pos)                          /*!< PORT1 PPS: PPS0 Mask                    */\r
+#define PORT1_PPS_PPS1_Pos                    1                                                       /*!< PORT1 PPS: PPS1 Position                */\r
+#define PORT1_PPS_PPS1_Msk                    (0x01UL << PORT1_PPS_PPS1_Pos)                          /*!< PORT1 PPS: PPS1 Mask                    */\r
+#define PORT1_PPS_PPS2_Pos                    2                                                       /*!< PORT1 PPS: PPS2 Position                */\r
+#define PORT1_PPS_PPS2_Msk                    (0x01UL << PORT1_PPS_PPS2_Pos)                          /*!< PORT1 PPS: PPS2 Mask                    */\r
+#define PORT1_PPS_PPS3_Pos                    3                                                       /*!< PORT1 PPS: PPS3 Position                */\r
+#define PORT1_PPS_PPS3_Msk                    (0x01UL << PORT1_PPS_PPS3_Pos)                          /*!< PORT1 PPS: PPS3 Mask                    */\r
+#define PORT1_PPS_PPS4_Pos                    4                                                       /*!< PORT1 PPS: PPS4 Position                */\r
+#define PORT1_PPS_PPS4_Msk                    (0x01UL << PORT1_PPS_PPS4_Pos)                          /*!< PORT1 PPS: PPS4 Mask                    */\r
+#define PORT1_PPS_PPS5_Pos                    5                                                       /*!< PORT1 PPS: PPS5 Position                */\r
+#define PORT1_PPS_PPS5_Msk                    (0x01UL << PORT1_PPS_PPS5_Pos)                          /*!< PORT1 PPS: PPS5 Mask                    */\r
+#define PORT1_PPS_PPS6_Pos                    6                                                       /*!< PORT1 PPS: PPS6 Position                */\r
+#define PORT1_PPS_PPS6_Msk                    (0x01UL << PORT1_PPS_PPS6_Pos)                          /*!< PORT1 PPS: PPS6 Mask                    */\r
+#define PORT1_PPS_PPS7_Pos                    7                                                       /*!< PORT1 PPS: PPS7 Position                */\r
+#define PORT1_PPS_PPS7_Msk                    (0x01UL << PORT1_PPS_PPS7_Pos)                          /*!< PORT1 PPS: PPS7 Mask                    */\r
+#define PORT1_PPS_PPS8_Pos                    8                                                       /*!< PORT1 PPS: PPS8 Position                */\r
+#define PORT1_PPS_PPS8_Msk                    (0x01UL << PORT1_PPS_PPS8_Pos)                          /*!< PORT1 PPS: PPS8 Mask                    */\r
+#define PORT1_PPS_PPS9_Pos                    9                                                       /*!< PORT1 PPS: PPS9 Position                */\r
+#define PORT1_PPS_PPS9_Msk                    (0x01UL << PORT1_PPS_PPS9_Pos)                          /*!< PORT1 PPS: PPS9 Mask                    */\r
+#define PORT1_PPS_PPS10_Pos                   10                                                      /*!< PORT1 PPS: PPS10 Position               */\r
+#define PORT1_PPS_PPS10_Msk                   (0x01UL << PORT1_PPS_PPS10_Pos)                         /*!< PORT1 PPS: PPS10 Mask                   */\r
+#define PORT1_PPS_PPS11_Pos                   11                                                      /*!< PORT1 PPS: PPS11 Position               */\r
+#define PORT1_PPS_PPS11_Msk                   (0x01UL << PORT1_PPS_PPS11_Pos)                         /*!< PORT1 PPS: PPS11 Mask                   */\r
+#define PORT1_PPS_PPS12_Pos                   12                                                      /*!< PORT1 PPS: PPS12 Position               */\r
+#define PORT1_PPS_PPS12_Msk                   (0x01UL << PORT1_PPS_PPS12_Pos)                         /*!< PORT1 PPS: PPS12 Mask                   */\r
+#define PORT1_PPS_PPS13_Pos                   13                                                      /*!< PORT1 PPS: PPS13 Position               */\r
+#define PORT1_PPS_PPS13_Msk                   (0x01UL << PORT1_PPS_PPS13_Pos)                         /*!< PORT1 PPS: PPS13 Mask                   */\r
+#define PORT1_PPS_PPS14_Pos                   14                                                      /*!< PORT1 PPS: PPS14 Position               */\r
+#define PORT1_PPS_PPS14_Msk                   (0x01UL << PORT1_PPS_PPS14_Pos)                         /*!< PORT1 PPS: PPS14 Mask                   */\r
+#define PORT1_PPS_PPS15_Pos                   15                                                      /*!< PORT1 PPS: PPS15 Position               */\r
+#define PORT1_PPS_PPS15_Msk                   (0x01UL << PORT1_PPS_PPS15_Pos)                         /*!< PORT1 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_HWSEL  -------------------------------- */\r
+#define PORT1_HWSEL_HW0_Pos                   0                                                       /*!< PORT1 HWSEL: HW0 Position               */\r
+#define PORT1_HWSEL_HW0_Msk                   (0x03UL << PORT1_HWSEL_HW0_Pos)                         /*!< PORT1 HWSEL: HW0 Mask                   */\r
+#define PORT1_HWSEL_HW1_Pos                   2                                                       /*!< PORT1 HWSEL: HW1 Position               */\r
+#define PORT1_HWSEL_HW1_Msk                   (0x03UL << PORT1_HWSEL_HW1_Pos)                         /*!< PORT1 HWSEL: HW1 Mask                   */\r
+#define PORT1_HWSEL_HW2_Pos                   4                                                       /*!< PORT1 HWSEL: HW2 Position               */\r
+#define PORT1_HWSEL_HW2_Msk                   (0x03UL << PORT1_HWSEL_HW2_Pos)                         /*!< PORT1 HWSEL: HW2 Mask                   */\r
+#define PORT1_HWSEL_HW3_Pos                   6                                                       /*!< PORT1 HWSEL: HW3 Position               */\r
+#define PORT1_HWSEL_HW3_Msk                   (0x03UL << PORT1_HWSEL_HW3_Pos)                         /*!< PORT1 HWSEL: HW3 Mask                   */\r
+#define PORT1_HWSEL_HW4_Pos                   8                                                       /*!< PORT1 HWSEL: HW4 Position               */\r
+#define PORT1_HWSEL_HW4_Msk                   (0x03UL << PORT1_HWSEL_HW4_Pos)                         /*!< PORT1 HWSEL: HW4 Mask                   */\r
+#define PORT1_HWSEL_HW5_Pos                   10                                                      /*!< PORT1 HWSEL: HW5 Position               */\r
+#define PORT1_HWSEL_HW5_Msk                   (0x03UL << PORT1_HWSEL_HW5_Pos)                         /*!< PORT1 HWSEL: HW5 Mask                   */\r
+#define PORT1_HWSEL_HW6_Pos                   12                                                      /*!< PORT1 HWSEL: HW6 Position               */\r
+#define PORT1_HWSEL_HW6_Msk                   (0x03UL << PORT1_HWSEL_HW6_Pos)                         /*!< PORT1 HWSEL: HW6 Mask                   */\r
+#define PORT1_HWSEL_HW7_Pos                   14                                                      /*!< PORT1 HWSEL: HW7 Position               */\r
+#define PORT1_HWSEL_HW7_Msk                   (0x03UL << PORT1_HWSEL_HW7_Pos)                         /*!< PORT1 HWSEL: HW7 Mask                   */\r
+#define PORT1_HWSEL_HW8_Pos                   16                                                      /*!< PORT1 HWSEL: HW8 Position               */\r
+#define PORT1_HWSEL_HW8_Msk                   (0x03UL << PORT1_HWSEL_HW8_Pos)                         /*!< PORT1 HWSEL: HW8 Mask                   */\r
+#define PORT1_HWSEL_HW9_Pos                   18                                                      /*!< PORT1 HWSEL: HW9 Position               */\r
+#define PORT1_HWSEL_HW9_Msk                   (0x03UL << PORT1_HWSEL_HW9_Pos)                         /*!< PORT1 HWSEL: HW9 Mask                   */\r
+#define PORT1_HWSEL_HW10_Pos                  20                                                      /*!< PORT1 HWSEL: HW10 Position              */\r
+#define PORT1_HWSEL_HW10_Msk                  (0x03UL << PORT1_HWSEL_HW10_Pos)                        /*!< PORT1 HWSEL: HW10 Mask                  */\r
+#define PORT1_HWSEL_HW11_Pos                  22                                                      /*!< PORT1 HWSEL: HW11 Position              */\r
+#define PORT1_HWSEL_HW11_Msk                  (0x03UL << PORT1_HWSEL_HW11_Pos)                        /*!< PORT1 HWSEL: HW11 Mask                  */\r
+#define PORT1_HWSEL_HW12_Pos                  24                                                      /*!< PORT1 HWSEL: HW12 Position              */\r
+#define PORT1_HWSEL_HW12_Msk                  (0x03UL << PORT1_HWSEL_HW12_Pos)                        /*!< PORT1 HWSEL: HW12 Mask                  */\r
+#define PORT1_HWSEL_HW13_Pos                  26                                                      /*!< PORT1 HWSEL: HW13 Position              */\r
+#define PORT1_HWSEL_HW13_Msk                  (0x03UL << PORT1_HWSEL_HW13_Pos)                        /*!< PORT1 HWSEL: HW13 Mask                  */\r
+#define PORT1_HWSEL_HW14_Pos                  28                                                      /*!< PORT1 HWSEL: HW14 Position              */\r
+#define PORT1_HWSEL_HW14_Msk                  (0x03UL << PORT1_HWSEL_HW14_Pos)                        /*!< PORT1 HWSEL: HW14 Mask                  */\r
+#define PORT1_HWSEL_HW15_Pos                  30                                                      /*!< PORT1 HWSEL: HW15 Position              */\r
+#define PORT1_HWSEL_HW15_Msk                  (0x03UL << PORT1_HWSEL_HW15_Pos)                        /*!< PORT1 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT2' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT2_OUT  --------------------------------- */\r
+#define PORT2_OUT_P0_Pos                      0                                                       /*!< PORT2 OUT: P0 Position                  */\r
+#define PORT2_OUT_P0_Msk                      (0x01UL << PORT2_OUT_P0_Pos)                            /*!< PORT2 OUT: P0 Mask                      */\r
+#define PORT2_OUT_P1_Pos                      1                                                       /*!< PORT2 OUT: P1 Position                  */\r
+#define PORT2_OUT_P1_Msk                      (0x01UL << PORT2_OUT_P1_Pos)                            /*!< PORT2 OUT: P1 Mask                      */\r
+#define PORT2_OUT_P2_Pos                      2                                                       /*!< PORT2 OUT: P2 Position                  */\r
+#define PORT2_OUT_P2_Msk                      (0x01UL << PORT2_OUT_P2_Pos)                            /*!< PORT2 OUT: P2 Mask                      */\r
+#define PORT2_OUT_P3_Pos                      3                                                       /*!< PORT2 OUT: P3 Position                  */\r
+#define PORT2_OUT_P3_Msk                      (0x01UL << PORT2_OUT_P3_Pos)                            /*!< PORT2 OUT: P3 Mask                      */\r
+#define PORT2_OUT_P4_Pos                      4                                                       /*!< PORT2 OUT: P4 Position                  */\r
+#define PORT2_OUT_P4_Msk                      (0x01UL << PORT2_OUT_P4_Pos)                            /*!< PORT2 OUT: P4 Mask                      */\r
+#define PORT2_OUT_P5_Pos                      5                                                       /*!< PORT2 OUT: P5 Position                  */\r
+#define PORT2_OUT_P5_Msk                      (0x01UL << PORT2_OUT_P5_Pos)                            /*!< PORT2 OUT: P5 Mask                      */\r
+#define PORT2_OUT_P6_Pos                      6                                                       /*!< PORT2 OUT: P6 Position                  */\r
+#define PORT2_OUT_P6_Msk                      (0x01UL << PORT2_OUT_P6_Pos)                            /*!< PORT2 OUT: P6 Mask                      */\r
+#define PORT2_OUT_P7_Pos                      7                                                       /*!< PORT2 OUT: P7 Position                  */\r
+#define PORT2_OUT_P7_Msk                      (0x01UL << PORT2_OUT_P7_Pos)                            /*!< PORT2 OUT: P7 Mask                      */\r
+#define PORT2_OUT_P8_Pos                      8                                                       /*!< PORT2 OUT: P8 Position                  */\r
+#define PORT2_OUT_P8_Msk                      (0x01UL << PORT2_OUT_P8_Pos)                            /*!< PORT2 OUT: P8 Mask                      */\r
+#define PORT2_OUT_P9_Pos                      9                                                       /*!< PORT2 OUT: P9 Position                  */\r
+#define PORT2_OUT_P9_Msk                      (0x01UL << PORT2_OUT_P9_Pos)                            /*!< PORT2 OUT: P9 Mask                      */\r
+#define PORT2_OUT_P10_Pos                     10                                                      /*!< PORT2 OUT: P10 Position                 */\r
+#define PORT2_OUT_P10_Msk                     (0x01UL << PORT2_OUT_P10_Pos)                           /*!< PORT2 OUT: P10 Mask                     */\r
+#define PORT2_OUT_P11_Pos                     11                                                      /*!< PORT2 OUT: P11 Position                 */\r
+#define PORT2_OUT_P11_Msk                     (0x01UL << PORT2_OUT_P11_Pos)                           /*!< PORT2 OUT: P11 Mask                     */\r
+#define PORT2_OUT_P12_Pos                     12                                                      /*!< PORT2 OUT: P12 Position                 */\r
+#define PORT2_OUT_P12_Msk                     (0x01UL << PORT2_OUT_P12_Pos)                           /*!< PORT2 OUT: P12 Mask                     */\r
+#define PORT2_OUT_P13_Pos                     13                                                      /*!< PORT2 OUT: P13 Position                 */\r
+#define PORT2_OUT_P13_Msk                     (0x01UL << PORT2_OUT_P13_Pos)                           /*!< PORT2 OUT: P13 Mask                     */\r
+#define PORT2_OUT_P14_Pos                     14                                                      /*!< PORT2 OUT: P14 Position                 */\r
+#define PORT2_OUT_P14_Msk                     (0x01UL << PORT2_OUT_P14_Pos)                           /*!< PORT2 OUT: P14 Mask                     */\r
+#define PORT2_OUT_P15_Pos                     15                                                      /*!< PORT2 OUT: P15 Position                 */\r
+#define PORT2_OUT_P15_Msk                     (0x01UL << PORT2_OUT_P15_Pos)                           /*!< PORT2 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT2_OMR  --------------------------------- */\r
+#define PORT2_OMR_PS0_Pos                     0                                                       /*!< PORT2 OMR: PS0 Position                 */\r
+#define PORT2_OMR_PS0_Msk                     (0x01UL << PORT2_OMR_PS0_Pos)                           /*!< PORT2 OMR: PS0 Mask                     */\r
+#define PORT2_OMR_PS1_Pos                     1                                                       /*!< PORT2 OMR: PS1 Position                 */\r
+#define PORT2_OMR_PS1_Msk                     (0x01UL << PORT2_OMR_PS1_Pos)                           /*!< PORT2 OMR: PS1 Mask                     */\r
+#define PORT2_OMR_PS2_Pos                     2                                                       /*!< PORT2 OMR: PS2 Position                 */\r
+#define PORT2_OMR_PS2_Msk                     (0x01UL << PORT2_OMR_PS2_Pos)                           /*!< PORT2 OMR: PS2 Mask                     */\r
+#define PORT2_OMR_PS3_Pos                     3                                                       /*!< PORT2 OMR: PS3 Position                 */\r
+#define PORT2_OMR_PS3_Msk                     (0x01UL << PORT2_OMR_PS3_Pos)                           /*!< PORT2 OMR: PS3 Mask                     */\r
+#define PORT2_OMR_PS4_Pos                     4                                                       /*!< PORT2 OMR: PS4 Position                 */\r
+#define PORT2_OMR_PS4_Msk                     (0x01UL << PORT2_OMR_PS4_Pos)                           /*!< PORT2 OMR: PS4 Mask                     */\r
+#define PORT2_OMR_PS5_Pos                     5                                                       /*!< PORT2 OMR: PS5 Position                 */\r
+#define PORT2_OMR_PS5_Msk                     (0x01UL << PORT2_OMR_PS5_Pos)                           /*!< PORT2 OMR: PS5 Mask                     */\r
+#define PORT2_OMR_PS6_Pos                     6                                                       /*!< PORT2 OMR: PS6 Position                 */\r
+#define PORT2_OMR_PS6_Msk                     (0x01UL << PORT2_OMR_PS6_Pos)                           /*!< PORT2 OMR: PS6 Mask                     */\r
+#define PORT2_OMR_PS7_Pos                     7                                                       /*!< PORT2 OMR: PS7 Position                 */\r
+#define PORT2_OMR_PS7_Msk                     (0x01UL << PORT2_OMR_PS7_Pos)                           /*!< PORT2 OMR: PS7 Mask                     */\r
+#define PORT2_OMR_PS8_Pos                     8                                                       /*!< PORT2 OMR: PS8 Position                 */\r
+#define PORT2_OMR_PS8_Msk                     (0x01UL << PORT2_OMR_PS8_Pos)                           /*!< PORT2 OMR: PS8 Mask                     */\r
+#define PORT2_OMR_PS9_Pos                     9                                                       /*!< PORT2 OMR: PS9 Position                 */\r
+#define PORT2_OMR_PS9_Msk                     (0x01UL << PORT2_OMR_PS9_Pos)                           /*!< PORT2 OMR: PS9 Mask                     */\r
+#define PORT2_OMR_PS10_Pos                    10                                                      /*!< PORT2 OMR: PS10 Position                */\r
+#define PORT2_OMR_PS10_Msk                    (0x01UL << PORT2_OMR_PS10_Pos)                          /*!< PORT2 OMR: PS10 Mask                    */\r
+#define PORT2_OMR_PS11_Pos                    11                                                      /*!< PORT2 OMR: PS11 Position                */\r
+#define PORT2_OMR_PS11_Msk                    (0x01UL << PORT2_OMR_PS11_Pos)                          /*!< PORT2 OMR: PS11 Mask                    */\r
+#define PORT2_OMR_PS12_Pos                    12                                                      /*!< PORT2 OMR: PS12 Position                */\r
+#define PORT2_OMR_PS12_Msk                    (0x01UL << PORT2_OMR_PS12_Pos)                          /*!< PORT2 OMR: PS12 Mask                    */\r
+#define PORT2_OMR_PS13_Pos                    13                                                      /*!< PORT2 OMR: PS13 Position                */\r
+#define PORT2_OMR_PS13_Msk                    (0x01UL << PORT2_OMR_PS13_Pos)                          /*!< PORT2 OMR: PS13 Mask                    */\r
+#define PORT2_OMR_PS14_Pos                    14                                                      /*!< PORT2 OMR: PS14 Position                */\r
+#define PORT2_OMR_PS14_Msk                    (0x01UL << PORT2_OMR_PS14_Pos)                          /*!< PORT2 OMR: PS14 Mask                    */\r
+#define PORT2_OMR_PS15_Pos                    15                                                      /*!< PORT2 OMR: PS15 Position                */\r
+#define PORT2_OMR_PS15_Msk                    (0x01UL << PORT2_OMR_PS15_Pos)                          /*!< PORT2 OMR: PS15 Mask                    */\r
+#define PORT2_OMR_PR0_Pos                     16                                                      /*!< PORT2 OMR: PR0 Position                 */\r
+#define PORT2_OMR_PR0_Msk                     (0x01UL << PORT2_OMR_PR0_Pos)                           /*!< PORT2 OMR: PR0 Mask                     */\r
+#define PORT2_OMR_PR1_Pos                     17                                                      /*!< PORT2 OMR: PR1 Position                 */\r
+#define PORT2_OMR_PR1_Msk                     (0x01UL << PORT2_OMR_PR1_Pos)                           /*!< PORT2 OMR: PR1 Mask                     */\r
+#define PORT2_OMR_PR2_Pos                     18                                                      /*!< PORT2 OMR: PR2 Position                 */\r
+#define PORT2_OMR_PR2_Msk                     (0x01UL << PORT2_OMR_PR2_Pos)                           /*!< PORT2 OMR: PR2 Mask                     */\r
+#define PORT2_OMR_PR3_Pos                     19                                                      /*!< PORT2 OMR: PR3 Position                 */\r
+#define PORT2_OMR_PR3_Msk                     (0x01UL << PORT2_OMR_PR3_Pos)                           /*!< PORT2 OMR: PR3 Mask                     */\r
+#define PORT2_OMR_PR4_Pos                     20                                                      /*!< PORT2 OMR: PR4 Position                 */\r
+#define PORT2_OMR_PR4_Msk                     (0x01UL << PORT2_OMR_PR4_Pos)                           /*!< PORT2 OMR: PR4 Mask                     */\r
+#define PORT2_OMR_PR5_Pos                     21                                                      /*!< PORT2 OMR: PR5 Position                 */\r
+#define PORT2_OMR_PR5_Msk                     (0x01UL << PORT2_OMR_PR5_Pos)                           /*!< PORT2 OMR: PR5 Mask                     */\r
+#define PORT2_OMR_PR6_Pos                     22                                                      /*!< PORT2 OMR: PR6 Position                 */\r
+#define PORT2_OMR_PR6_Msk                     (0x01UL << PORT2_OMR_PR6_Pos)                           /*!< PORT2 OMR: PR6 Mask                     */\r
+#define PORT2_OMR_PR7_Pos                     23                                                      /*!< PORT2 OMR: PR7 Position                 */\r
+#define PORT2_OMR_PR7_Msk                     (0x01UL << PORT2_OMR_PR7_Pos)                           /*!< PORT2 OMR: PR7 Mask                     */\r
+#define PORT2_OMR_PR8_Pos                     24                                                      /*!< PORT2 OMR: PR8 Position                 */\r
+#define PORT2_OMR_PR8_Msk                     (0x01UL << PORT2_OMR_PR8_Pos)                           /*!< PORT2 OMR: PR8 Mask                     */\r
+#define PORT2_OMR_PR9_Pos                     25                                                      /*!< PORT2 OMR: PR9 Position                 */\r
+#define PORT2_OMR_PR9_Msk                     (0x01UL << PORT2_OMR_PR9_Pos)                           /*!< PORT2 OMR: PR9 Mask                     */\r
+#define PORT2_OMR_PR10_Pos                    26                                                      /*!< PORT2 OMR: PR10 Position                */\r
+#define PORT2_OMR_PR10_Msk                    (0x01UL << PORT2_OMR_PR10_Pos)                          /*!< PORT2 OMR: PR10 Mask                    */\r
+#define PORT2_OMR_PR11_Pos                    27                                                      /*!< PORT2 OMR: PR11 Position                */\r
+#define PORT2_OMR_PR11_Msk                    (0x01UL << PORT2_OMR_PR11_Pos)                          /*!< PORT2 OMR: PR11 Mask                    */\r
+#define PORT2_OMR_PR12_Pos                    28                                                      /*!< PORT2 OMR: PR12 Position                */\r
+#define PORT2_OMR_PR12_Msk                    (0x01UL << PORT2_OMR_PR12_Pos)                          /*!< PORT2 OMR: PR12 Mask                    */\r
+#define PORT2_OMR_PR13_Pos                    29                                                      /*!< PORT2 OMR: PR13 Position                */\r
+#define PORT2_OMR_PR13_Msk                    (0x01UL << PORT2_OMR_PR13_Pos)                          /*!< PORT2 OMR: PR13 Mask                    */\r
+#define PORT2_OMR_PR14_Pos                    30                                                      /*!< PORT2 OMR: PR14 Position                */\r
+#define PORT2_OMR_PR14_Msk                    (0x01UL << PORT2_OMR_PR14_Pos)                          /*!< PORT2 OMR: PR14 Mask                    */\r
+#define PORT2_OMR_PR15_Pos                    31                                                      /*!< PORT2 OMR: PR15 Position                */\r
+#define PORT2_OMR_PR15_Msk                    (0x01UL << PORT2_OMR_PR15_Pos)                          /*!< PORT2 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT2_IOCR0  -------------------------------- */\r
+#define PORT2_IOCR0_PC0_Pos                   3                                                       /*!< PORT2 IOCR0: PC0 Position               */\r
+#define PORT2_IOCR0_PC0_Msk                   (0x1fUL << PORT2_IOCR0_PC0_Pos)                         /*!< PORT2 IOCR0: PC0 Mask                   */\r
+#define PORT2_IOCR0_PC1_Pos                   11                                                      /*!< PORT2 IOCR0: PC1 Position               */\r
+#define PORT2_IOCR0_PC1_Msk                   (0x1fUL << PORT2_IOCR0_PC1_Pos)                         /*!< PORT2 IOCR0: PC1 Mask                   */\r
+#define PORT2_IOCR0_PC2_Pos                   19                                                      /*!< PORT2 IOCR0: PC2 Position               */\r
+#define PORT2_IOCR0_PC2_Msk                   (0x1fUL << PORT2_IOCR0_PC2_Pos)                         /*!< PORT2 IOCR0: PC2 Mask                   */\r
+#define PORT2_IOCR0_PC3_Pos                   27                                                      /*!< PORT2 IOCR0: PC3 Position               */\r
+#define PORT2_IOCR0_PC3_Msk                   (0x1fUL << PORT2_IOCR0_PC3_Pos)                         /*!< PORT2 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_IOCR4  -------------------------------- */\r
+#define PORT2_IOCR4_PC4_Pos                   3                                                       /*!< PORT2 IOCR4: PC4 Position               */\r
+#define PORT2_IOCR4_PC4_Msk                   (0x1fUL << PORT2_IOCR4_PC4_Pos)                         /*!< PORT2 IOCR4: PC4 Mask                   */\r
+#define PORT2_IOCR4_PC5_Pos                   11                                                      /*!< PORT2 IOCR4: PC5 Position               */\r
+#define PORT2_IOCR4_PC5_Msk                   (0x1fUL << PORT2_IOCR4_PC5_Pos)                         /*!< PORT2 IOCR4: PC5 Mask                   */\r
+#define PORT2_IOCR4_PC6_Pos                   19                                                      /*!< PORT2 IOCR4: PC6 Position               */\r
+#define PORT2_IOCR4_PC6_Msk                   (0x1fUL << PORT2_IOCR4_PC6_Pos)                         /*!< PORT2 IOCR4: PC6 Mask                   */\r
+#define PORT2_IOCR4_PC7_Pos                   27                                                      /*!< PORT2 IOCR4: PC7 Position               */\r
+#define PORT2_IOCR4_PC7_Msk                   (0x1fUL << PORT2_IOCR4_PC7_Pos)                         /*!< PORT2 IOCR4: PC7 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_IOCR8  -------------------------------- */\r
+#define PORT2_IOCR8_PC8_Pos                   3                                                       /*!< PORT2 IOCR8: PC8 Position               */\r
+#define PORT2_IOCR8_PC8_Msk                   (0x1fUL << PORT2_IOCR8_PC8_Pos)                         /*!< PORT2 IOCR8: PC8 Mask                   */\r
+#define PORT2_IOCR8_PC9_Pos                   11                                                      /*!< PORT2 IOCR8: PC9 Position               */\r
+#define PORT2_IOCR8_PC9_Msk                   (0x1fUL << PORT2_IOCR8_PC9_Pos)                         /*!< PORT2 IOCR8: PC9 Mask                   */\r
+#define PORT2_IOCR8_PC10_Pos                  19                                                      /*!< PORT2 IOCR8: PC10 Position              */\r
+#define PORT2_IOCR8_PC10_Msk                  (0x1fUL << PORT2_IOCR8_PC10_Pos)                        /*!< PORT2 IOCR8: PC10 Mask                  */\r
+#define PORT2_IOCR8_PC11_Pos                  27                                                      /*!< PORT2 IOCR8: PC11 Position              */\r
+#define PORT2_IOCR8_PC11_Msk                  (0x1fUL << PORT2_IOCR8_PC11_Pos)                        /*!< PORT2 IOCR8: PC11 Mask                  */\r
+\r
+/* --------------------------------  PORT2_IOCR12  -------------------------------- */\r
+#define PORT2_IOCR12_PC12_Pos                 3                                                       /*!< PORT2 IOCR12: PC12 Position             */\r
+#define PORT2_IOCR12_PC12_Msk                 (0x1fUL << PORT2_IOCR12_PC12_Pos)                       /*!< PORT2 IOCR12: PC12 Mask                 */\r
+#define PORT2_IOCR12_PC13_Pos                 11                                                      /*!< PORT2 IOCR12: PC13 Position             */\r
+#define PORT2_IOCR12_PC13_Msk                 (0x1fUL << PORT2_IOCR12_PC13_Pos)                       /*!< PORT2 IOCR12: PC13 Mask                 */\r
+#define PORT2_IOCR12_PC14_Pos                 19                                                      /*!< PORT2 IOCR12: PC14 Position             */\r
+#define PORT2_IOCR12_PC14_Msk                 (0x1fUL << PORT2_IOCR12_PC14_Pos)                       /*!< PORT2 IOCR12: PC14 Mask                 */\r
+#define PORT2_IOCR12_PC15_Pos                 27                                                      /*!< PORT2 IOCR12: PC15 Position             */\r
+#define PORT2_IOCR12_PC15_Msk                 (0x1fUL << PORT2_IOCR12_PC15_Pos)                       /*!< PORT2 IOCR12: PC15 Mask                 */\r
+\r
+/* ----------------------------------  PORT2_IN  ---------------------------------- */\r
+#define PORT2_IN_P0_Pos                       0                                                       /*!< PORT2 IN: P0 Position                   */\r
+#define PORT2_IN_P0_Msk                       (0x01UL << PORT2_IN_P0_Pos)                             /*!< PORT2 IN: P0 Mask                       */\r
+#define PORT2_IN_P1_Pos                       1                                                       /*!< PORT2 IN: P1 Position                   */\r
+#define PORT2_IN_P1_Msk                       (0x01UL << PORT2_IN_P1_Pos)                             /*!< PORT2 IN: P1 Mask                       */\r
+#define PORT2_IN_P2_Pos                       2                                                       /*!< PORT2 IN: P2 Position                   */\r
+#define PORT2_IN_P2_Msk                       (0x01UL << PORT2_IN_P2_Pos)                             /*!< PORT2 IN: P2 Mask                       */\r
+#define PORT2_IN_P3_Pos                       3                                                       /*!< PORT2 IN: P3 Position                   */\r
+#define PORT2_IN_P3_Msk                       (0x01UL << PORT2_IN_P3_Pos)                             /*!< PORT2 IN: P3 Mask                       */\r
+#define PORT2_IN_P4_Pos                       4                                                       /*!< PORT2 IN: P4 Position                   */\r
+#define PORT2_IN_P4_Msk                       (0x01UL << PORT2_IN_P4_Pos)                             /*!< PORT2 IN: P4 Mask                       */\r
+#define PORT2_IN_P5_Pos                       5                                                       /*!< PORT2 IN: P5 Position                   */\r
+#define PORT2_IN_P5_Msk                       (0x01UL << PORT2_IN_P5_Pos)                             /*!< PORT2 IN: P5 Mask                       */\r
+#define PORT2_IN_P6_Pos                       6                                                       /*!< PORT2 IN: P6 Position                   */\r
+#define PORT2_IN_P6_Msk                       (0x01UL << PORT2_IN_P6_Pos)                             /*!< PORT2 IN: P6 Mask                       */\r
+#define PORT2_IN_P7_Pos                       7                                                       /*!< PORT2 IN: P7 Position                   */\r
+#define PORT2_IN_P7_Msk                       (0x01UL << PORT2_IN_P7_Pos)                             /*!< PORT2 IN: P7 Mask                       */\r
+#define PORT2_IN_P8_Pos                       8                                                       /*!< PORT2 IN: P8 Position                   */\r
+#define PORT2_IN_P8_Msk                       (0x01UL << PORT2_IN_P8_Pos)                             /*!< PORT2 IN: P8 Mask                       */\r
+#define PORT2_IN_P9_Pos                       9                                                       /*!< PORT2 IN: P9 Position                   */\r
+#define PORT2_IN_P9_Msk                       (0x01UL << PORT2_IN_P9_Pos)                             /*!< PORT2 IN: P9 Mask                       */\r
+#define PORT2_IN_P10_Pos                      10                                                      /*!< PORT2 IN: P10 Position                  */\r
+#define PORT2_IN_P10_Msk                      (0x01UL << PORT2_IN_P10_Pos)                            /*!< PORT2 IN: P10 Mask                      */\r
+#define PORT2_IN_P11_Pos                      11                                                      /*!< PORT2 IN: P11 Position                  */\r
+#define PORT2_IN_P11_Msk                      (0x01UL << PORT2_IN_P11_Pos)                            /*!< PORT2 IN: P11 Mask                      */\r
+#define PORT2_IN_P12_Pos                      12                                                      /*!< PORT2 IN: P12 Position                  */\r
+#define PORT2_IN_P12_Msk                      (0x01UL << PORT2_IN_P12_Pos)                            /*!< PORT2 IN: P12 Mask                      */\r
+#define PORT2_IN_P13_Pos                      13                                                      /*!< PORT2 IN: P13 Position                  */\r
+#define PORT2_IN_P13_Msk                      (0x01UL << PORT2_IN_P13_Pos)                            /*!< PORT2 IN: P13 Mask                      */\r
+#define PORT2_IN_P14_Pos                      14                                                      /*!< PORT2 IN: P14 Position                  */\r
+#define PORT2_IN_P14_Msk                      (0x01UL << PORT2_IN_P14_Pos)                            /*!< PORT2 IN: P14 Mask                      */\r
+#define PORT2_IN_P15_Pos                      15                                                      /*!< PORT2 IN: P15 Position                  */\r
+#define PORT2_IN_P15_Msk                      (0x01UL << PORT2_IN_P15_Pos)                            /*!< PORT2 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT2_PDR0  --------------------------------- */\r
+#define PORT2_PDR0_PD0_Pos                    0                                                       /*!< PORT2 PDR0: PD0 Position                */\r
+#define PORT2_PDR0_PD0_Msk                    (0x07UL << PORT2_PDR0_PD0_Pos)                          /*!< PORT2 PDR0: PD0 Mask                    */\r
+#define PORT2_PDR0_PD1_Pos                    4                                                       /*!< PORT2 PDR0: PD1 Position                */\r
+#define PORT2_PDR0_PD1_Msk                    (0x07UL << PORT2_PDR0_PD1_Pos)                          /*!< PORT2 PDR0: PD1 Mask                    */\r
+#define PORT2_PDR0_PD2_Pos                    8                                                       /*!< PORT2 PDR0: PD2 Position                */\r
+#define PORT2_PDR0_PD2_Msk                    (0x07UL << PORT2_PDR0_PD2_Pos)                          /*!< PORT2 PDR0: PD2 Mask                    */\r
+#define PORT2_PDR0_PD3_Pos                    12                                                      /*!< PORT2 PDR0: PD3 Position                */\r
+#define PORT2_PDR0_PD3_Msk                    (0x07UL << PORT2_PDR0_PD3_Pos)                          /*!< PORT2 PDR0: PD3 Mask                    */\r
+#define PORT2_PDR0_PD4_Pos                    16                                                      /*!< PORT2 PDR0: PD4 Position                */\r
+#define PORT2_PDR0_PD4_Msk                    (0x07UL << PORT2_PDR0_PD4_Pos)                          /*!< PORT2 PDR0: PD4 Mask                    */\r
+#define PORT2_PDR0_PD5_Pos                    20                                                      /*!< PORT2 PDR0: PD5 Position                */\r
+#define PORT2_PDR0_PD5_Msk                    (0x07UL << PORT2_PDR0_PD5_Pos)                          /*!< PORT2 PDR0: PD5 Mask                    */\r
+#define PORT2_PDR0_PD6_Pos                    24                                                      /*!< PORT2 PDR0: PD6 Position                */\r
+#define PORT2_PDR0_PD6_Msk                    (0x07UL << PORT2_PDR0_PD6_Pos)                          /*!< PORT2 PDR0: PD6 Mask                    */\r
+#define PORT2_PDR0_PD7_Pos                    28                                                      /*!< PORT2 PDR0: PD7 Position                */\r
+#define PORT2_PDR0_PD7_Msk                    (0x07UL << PORT2_PDR0_PD7_Pos)                          /*!< PORT2 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT2_PDR1  --------------------------------- */\r
+#define PORT2_PDR1_PD8_Pos                    0                                                       /*!< PORT2 PDR1: PD8 Position                */\r
+#define PORT2_PDR1_PD8_Msk                    (0x07UL << PORT2_PDR1_PD8_Pos)                          /*!< PORT2 PDR1: PD8 Mask                    */\r
+#define PORT2_PDR1_PD9_Pos                    4                                                       /*!< PORT2 PDR1: PD9 Position                */\r
+#define PORT2_PDR1_PD9_Msk                    (0x07UL << PORT2_PDR1_PD9_Pos)                          /*!< PORT2 PDR1: PD9 Mask                    */\r
+#define PORT2_PDR1_PD10_Pos                   8                                                       /*!< PORT2 PDR1: PD10 Position               */\r
+#define PORT2_PDR1_PD10_Msk                   (0x07UL << PORT2_PDR1_PD10_Pos)                         /*!< PORT2 PDR1: PD10 Mask                   */\r
+#define PORT2_PDR1_PD11_Pos                   12                                                      /*!< PORT2 PDR1: PD11 Position               */\r
+#define PORT2_PDR1_PD11_Msk                   (0x07UL << PORT2_PDR1_PD11_Pos)                         /*!< PORT2 PDR1: PD11 Mask                   */\r
+#define PORT2_PDR1_PD12_Pos                   16                                                      /*!< PORT2 PDR1: PD12 Position               */\r
+#define PORT2_PDR1_PD12_Msk                   (0x07UL << PORT2_PDR1_PD12_Pos)                         /*!< PORT2 PDR1: PD12 Mask                   */\r
+#define PORT2_PDR1_PD13_Pos                   20                                                      /*!< PORT2 PDR1: PD13 Position               */\r
+#define PORT2_PDR1_PD13_Msk                   (0x07UL << PORT2_PDR1_PD13_Pos)                         /*!< PORT2 PDR1: PD13 Mask                   */\r
+#define PORT2_PDR1_PD14_Pos                   24                                                      /*!< PORT2 PDR1: PD14 Position               */\r
+#define PORT2_PDR1_PD14_Msk                   (0x07UL << PORT2_PDR1_PD14_Pos)                         /*!< PORT2 PDR1: PD14 Mask                   */\r
+#define PORT2_PDR1_PD15_Pos                   28                                                      /*!< PORT2 PDR1: PD15 Position               */\r
+#define PORT2_PDR1_PD15_Msk                   (0x07UL << PORT2_PDR1_PD15_Pos)                         /*!< PORT2 PDR1: PD15 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_PDISC  -------------------------------- */\r
+#define PORT2_PDISC_PDIS0_Pos                 0                                                       /*!< PORT2 PDISC: PDIS0 Position             */\r
+#define PORT2_PDISC_PDIS0_Msk                 (0x01UL << PORT2_PDISC_PDIS0_Pos)                       /*!< PORT2 PDISC: PDIS0 Mask                 */\r
+#define PORT2_PDISC_PDIS1_Pos                 1                                                       /*!< PORT2 PDISC: PDIS1 Position             */\r
+#define PORT2_PDISC_PDIS1_Msk                 (0x01UL << PORT2_PDISC_PDIS1_Pos)                       /*!< PORT2 PDISC: PDIS1 Mask                 */\r
+#define PORT2_PDISC_PDIS2_Pos                 2                                                       /*!< PORT2 PDISC: PDIS2 Position             */\r
+#define PORT2_PDISC_PDIS2_Msk                 (0x01UL << PORT2_PDISC_PDIS2_Pos)                       /*!< PORT2 PDISC: PDIS2 Mask                 */\r
+#define PORT2_PDISC_PDIS3_Pos                 3                                                       /*!< PORT2 PDISC: PDIS3 Position             */\r
+#define PORT2_PDISC_PDIS3_Msk                 (0x01UL << PORT2_PDISC_PDIS3_Pos)                       /*!< PORT2 PDISC: PDIS3 Mask                 */\r
+#define PORT2_PDISC_PDIS4_Pos                 4                                                       /*!< PORT2 PDISC: PDIS4 Position             */\r
+#define PORT2_PDISC_PDIS4_Msk                 (0x01UL << PORT2_PDISC_PDIS4_Pos)                       /*!< PORT2 PDISC: PDIS4 Mask                 */\r
+#define PORT2_PDISC_PDIS5_Pos                 5                                                       /*!< PORT2 PDISC: PDIS5 Position             */\r
+#define PORT2_PDISC_PDIS5_Msk                 (0x01UL << PORT2_PDISC_PDIS5_Pos)                       /*!< PORT2 PDISC: PDIS5 Mask                 */\r
+#define PORT2_PDISC_PDIS6_Pos                 6                                                       /*!< PORT2 PDISC: PDIS6 Position             */\r
+#define PORT2_PDISC_PDIS6_Msk                 (0x01UL << PORT2_PDISC_PDIS6_Pos)                       /*!< PORT2 PDISC: PDIS6 Mask                 */\r
+#define PORT2_PDISC_PDIS7_Pos                 7                                                       /*!< PORT2 PDISC: PDIS7 Position             */\r
+#define PORT2_PDISC_PDIS7_Msk                 (0x01UL << PORT2_PDISC_PDIS7_Pos)                       /*!< PORT2 PDISC: PDIS7 Mask                 */\r
+#define PORT2_PDISC_PDIS8_Pos                 8                                                       /*!< PORT2 PDISC: PDIS8 Position             */\r
+#define PORT2_PDISC_PDIS8_Msk                 (0x01UL << PORT2_PDISC_PDIS8_Pos)                       /*!< PORT2 PDISC: PDIS8 Mask                 */\r
+#define PORT2_PDISC_PDIS9_Pos                 9                                                       /*!< PORT2 PDISC: PDIS9 Position             */\r
+#define PORT2_PDISC_PDIS9_Msk                 (0x01UL << PORT2_PDISC_PDIS9_Pos)                       /*!< PORT2 PDISC: PDIS9 Mask                 */\r
+#define PORT2_PDISC_PDIS10_Pos                10                                                      /*!< PORT2 PDISC: PDIS10 Position            */\r
+#define PORT2_PDISC_PDIS10_Msk                (0x01UL << PORT2_PDISC_PDIS10_Pos)                      /*!< PORT2 PDISC: PDIS10 Mask                */\r
+#define PORT2_PDISC_PDIS11_Pos                11                                                      /*!< PORT2 PDISC: PDIS11 Position            */\r
+#define PORT2_PDISC_PDIS11_Msk                (0x01UL << PORT2_PDISC_PDIS11_Pos)                      /*!< PORT2 PDISC: PDIS11 Mask                */\r
+#define PORT2_PDISC_PDIS12_Pos                12                                                      /*!< PORT2 PDISC: PDIS12 Position            */\r
+#define PORT2_PDISC_PDIS12_Msk                (0x01UL << PORT2_PDISC_PDIS12_Pos)                      /*!< PORT2 PDISC: PDIS12 Mask                */\r
+#define PORT2_PDISC_PDIS13_Pos                13                                                      /*!< PORT2 PDISC: PDIS13 Position            */\r
+#define PORT2_PDISC_PDIS13_Msk                (0x01UL << PORT2_PDISC_PDIS13_Pos)                      /*!< PORT2 PDISC: PDIS13 Mask                */\r
+#define PORT2_PDISC_PDIS14_Pos                14                                                      /*!< PORT2 PDISC: PDIS14 Position            */\r
+#define PORT2_PDISC_PDIS14_Msk                (0x01UL << PORT2_PDISC_PDIS14_Pos)                      /*!< PORT2 PDISC: PDIS14 Mask                */\r
+#define PORT2_PDISC_PDIS15_Pos                15                                                      /*!< PORT2 PDISC: PDIS15 Position            */\r
+#define PORT2_PDISC_PDIS15_Msk                (0x01UL << PORT2_PDISC_PDIS15_Pos)                      /*!< PORT2 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT2_PPS  --------------------------------- */\r
+#define PORT2_PPS_PPS0_Pos                    0                                                       /*!< PORT2 PPS: PPS0 Position                */\r
+#define PORT2_PPS_PPS0_Msk                    (0x01UL << PORT2_PPS_PPS0_Pos)                          /*!< PORT2 PPS: PPS0 Mask                    */\r
+#define PORT2_PPS_PPS1_Pos                    1                                                       /*!< PORT2 PPS: PPS1 Position                */\r
+#define PORT2_PPS_PPS1_Msk                    (0x01UL << PORT2_PPS_PPS1_Pos)                          /*!< PORT2 PPS: PPS1 Mask                    */\r
+#define PORT2_PPS_PPS2_Pos                    2                                                       /*!< PORT2 PPS: PPS2 Position                */\r
+#define PORT2_PPS_PPS2_Msk                    (0x01UL << PORT2_PPS_PPS2_Pos)                          /*!< PORT2 PPS: PPS2 Mask                    */\r
+#define PORT2_PPS_PPS3_Pos                    3                                                       /*!< PORT2 PPS: PPS3 Position                */\r
+#define PORT2_PPS_PPS3_Msk                    (0x01UL << PORT2_PPS_PPS3_Pos)                          /*!< PORT2 PPS: PPS3 Mask                    */\r
+#define PORT2_PPS_PPS4_Pos                    4                                                       /*!< PORT2 PPS: PPS4 Position                */\r
+#define PORT2_PPS_PPS4_Msk                    (0x01UL << PORT2_PPS_PPS4_Pos)                          /*!< PORT2 PPS: PPS4 Mask                    */\r
+#define PORT2_PPS_PPS5_Pos                    5                                                       /*!< PORT2 PPS: PPS5 Position                */\r
+#define PORT2_PPS_PPS5_Msk                    (0x01UL << PORT2_PPS_PPS5_Pos)                          /*!< PORT2 PPS: PPS5 Mask                    */\r
+#define PORT2_PPS_PPS6_Pos                    6                                                       /*!< PORT2 PPS: PPS6 Position                */\r
+#define PORT2_PPS_PPS6_Msk                    (0x01UL << PORT2_PPS_PPS6_Pos)                          /*!< PORT2 PPS: PPS6 Mask                    */\r
+#define PORT2_PPS_PPS7_Pos                    7                                                       /*!< PORT2 PPS: PPS7 Position                */\r
+#define PORT2_PPS_PPS7_Msk                    (0x01UL << PORT2_PPS_PPS7_Pos)                          /*!< PORT2 PPS: PPS7 Mask                    */\r
+#define PORT2_PPS_PPS8_Pos                    8                                                       /*!< PORT2 PPS: PPS8 Position                */\r
+#define PORT2_PPS_PPS8_Msk                    (0x01UL << PORT2_PPS_PPS8_Pos)                          /*!< PORT2 PPS: PPS8 Mask                    */\r
+#define PORT2_PPS_PPS9_Pos                    9                                                       /*!< PORT2 PPS: PPS9 Position                */\r
+#define PORT2_PPS_PPS9_Msk                    (0x01UL << PORT2_PPS_PPS9_Pos)                          /*!< PORT2 PPS: PPS9 Mask                    */\r
+#define PORT2_PPS_PPS10_Pos                   10                                                      /*!< PORT2 PPS: PPS10 Position               */\r
+#define PORT2_PPS_PPS10_Msk                   (0x01UL << PORT2_PPS_PPS10_Pos)                         /*!< PORT2 PPS: PPS10 Mask                   */\r
+#define PORT2_PPS_PPS11_Pos                   11                                                      /*!< PORT2 PPS: PPS11 Position               */\r
+#define PORT2_PPS_PPS11_Msk                   (0x01UL << PORT2_PPS_PPS11_Pos)                         /*!< PORT2 PPS: PPS11 Mask                   */\r
+#define PORT2_PPS_PPS12_Pos                   12                                                      /*!< PORT2 PPS: PPS12 Position               */\r
+#define PORT2_PPS_PPS12_Msk                   (0x01UL << PORT2_PPS_PPS12_Pos)                         /*!< PORT2 PPS: PPS12 Mask                   */\r
+#define PORT2_PPS_PPS13_Pos                   13                                                      /*!< PORT2 PPS: PPS13 Position               */\r
+#define PORT2_PPS_PPS13_Msk                   (0x01UL << PORT2_PPS_PPS13_Pos)                         /*!< PORT2 PPS: PPS13 Mask                   */\r
+#define PORT2_PPS_PPS14_Pos                   14                                                      /*!< PORT2 PPS: PPS14 Position               */\r
+#define PORT2_PPS_PPS14_Msk                   (0x01UL << PORT2_PPS_PPS14_Pos)                         /*!< PORT2 PPS: PPS14 Mask                   */\r
+#define PORT2_PPS_PPS15_Pos                   15                                                      /*!< PORT2 PPS: PPS15 Position               */\r
+#define PORT2_PPS_PPS15_Msk                   (0x01UL << PORT2_PPS_PPS15_Pos)                         /*!< PORT2 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_HWSEL  -------------------------------- */\r
+#define PORT2_HWSEL_HW0_Pos                   0                                                       /*!< PORT2 HWSEL: HW0 Position               */\r
+#define PORT2_HWSEL_HW0_Msk                   (0x03UL << PORT2_HWSEL_HW0_Pos)                         /*!< PORT2 HWSEL: HW0 Mask                   */\r
+#define PORT2_HWSEL_HW1_Pos                   2                                                       /*!< PORT2 HWSEL: HW1 Position               */\r
+#define PORT2_HWSEL_HW1_Msk                   (0x03UL << PORT2_HWSEL_HW1_Pos)                         /*!< PORT2 HWSEL: HW1 Mask                   */\r
+#define PORT2_HWSEL_HW2_Pos                   4                                                       /*!< PORT2 HWSEL: HW2 Position               */\r
+#define PORT2_HWSEL_HW2_Msk                   (0x03UL << PORT2_HWSEL_HW2_Pos)                         /*!< PORT2 HWSEL: HW2 Mask                   */\r
+#define PORT2_HWSEL_HW3_Pos                   6                                                       /*!< PORT2 HWSEL: HW3 Position               */\r
+#define PORT2_HWSEL_HW3_Msk                   (0x03UL << PORT2_HWSEL_HW3_Pos)                         /*!< PORT2 HWSEL: HW3 Mask                   */\r
+#define PORT2_HWSEL_HW4_Pos                   8                                                       /*!< PORT2 HWSEL: HW4 Position               */\r
+#define PORT2_HWSEL_HW4_Msk                   (0x03UL << PORT2_HWSEL_HW4_Pos)                         /*!< PORT2 HWSEL: HW4 Mask                   */\r
+#define PORT2_HWSEL_HW5_Pos                   10                                                      /*!< PORT2 HWSEL: HW5 Position               */\r
+#define PORT2_HWSEL_HW5_Msk                   (0x03UL << PORT2_HWSEL_HW5_Pos)                         /*!< PORT2 HWSEL: HW5 Mask                   */\r
+#define PORT2_HWSEL_HW6_Pos                   12                                                      /*!< PORT2 HWSEL: HW6 Position               */\r
+#define PORT2_HWSEL_HW6_Msk                   (0x03UL << PORT2_HWSEL_HW6_Pos)                         /*!< PORT2 HWSEL: HW6 Mask                   */\r
+#define PORT2_HWSEL_HW7_Pos                   14                                                      /*!< PORT2 HWSEL: HW7 Position               */\r
+#define PORT2_HWSEL_HW7_Msk                   (0x03UL << PORT2_HWSEL_HW7_Pos)                         /*!< PORT2 HWSEL: HW7 Mask                   */\r
+#define PORT2_HWSEL_HW8_Pos                   16                                                      /*!< PORT2 HWSEL: HW8 Position               */\r
+#define PORT2_HWSEL_HW8_Msk                   (0x03UL << PORT2_HWSEL_HW8_Pos)                         /*!< PORT2 HWSEL: HW8 Mask                   */\r
+#define PORT2_HWSEL_HW9_Pos                   18                                                      /*!< PORT2 HWSEL: HW9 Position               */\r
+#define PORT2_HWSEL_HW9_Msk                   (0x03UL << PORT2_HWSEL_HW9_Pos)                         /*!< PORT2 HWSEL: HW9 Mask                   */\r
+#define PORT2_HWSEL_HW10_Pos                  20                                                      /*!< PORT2 HWSEL: HW10 Position              */\r
+#define PORT2_HWSEL_HW10_Msk                  (0x03UL << PORT2_HWSEL_HW10_Pos)                        /*!< PORT2 HWSEL: HW10 Mask                  */\r
+#define PORT2_HWSEL_HW11_Pos                  22                                                      /*!< PORT2 HWSEL: HW11 Position              */\r
+#define PORT2_HWSEL_HW11_Msk                  (0x03UL << PORT2_HWSEL_HW11_Pos)                        /*!< PORT2 HWSEL: HW11 Mask                  */\r
+#define PORT2_HWSEL_HW12_Pos                  24                                                      /*!< PORT2 HWSEL: HW12 Position              */\r
+#define PORT2_HWSEL_HW12_Msk                  (0x03UL << PORT2_HWSEL_HW12_Pos)                        /*!< PORT2 HWSEL: HW12 Mask                  */\r
+#define PORT2_HWSEL_HW13_Pos                  26                                                      /*!< PORT2 HWSEL: HW13 Position              */\r
+#define PORT2_HWSEL_HW13_Msk                  (0x03UL << PORT2_HWSEL_HW13_Pos)                        /*!< PORT2 HWSEL: HW13 Mask                  */\r
+#define PORT2_HWSEL_HW14_Pos                  28                                                      /*!< PORT2 HWSEL: HW14 Position              */\r
+#define PORT2_HWSEL_HW14_Msk                  (0x03UL << PORT2_HWSEL_HW14_Pos)                        /*!< PORT2 HWSEL: HW14 Mask                  */\r
+#define PORT2_HWSEL_HW15_Pos                  30                                                      /*!< PORT2 HWSEL: HW15 Position              */\r
+#define PORT2_HWSEL_HW15_Msk                  (0x03UL << PORT2_HWSEL_HW15_Pos)                        /*!< PORT2 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT3' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT3_OUT  --------------------------------- */\r
+#define PORT3_OUT_P0_Pos                      0                                                       /*!< PORT3 OUT: P0 Position                  */\r
+#define PORT3_OUT_P0_Msk                      (0x01UL << PORT3_OUT_P0_Pos)                            /*!< PORT3 OUT: P0 Mask                      */\r
+#define PORT3_OUT_P1_Pos                      1                                                       /*!< PORT3 OUT: P1 Position                  */\r
+#define PORT3_OUT_P1_Msk                      (0x01UL << PORT3_OUT_P1_Pos)                            /*!< PORT3 OUT: P1 Mask                      */\r
+#define PORT3_OUT_P2_Pos                      2                                                       /*!< PORT3 OUT: P2 Position                  */\r
+#define PORT3_OUT_P2_Msk                      (0x01UL << PORT3_OUT_P2_Pos)                            /*!< PORT3 OUT: P2 Mask                      */\r
+#define PORT3_OUT_P3_Pos                      3                                                       /*!< PORT3 OUT: P3 Position                  */\r
+#define PORT3_OUT_P3_Msk                      (0x01UL << PORT3_OUT_P3_Pos)                            /*!< PORT3 OUT: P3 Mask                      */\r
+#define PORT3_OUT_P4_Pos                      4                                                       /*!< PORT3 OUT: P4 Position                  */\r
+#define PORT3_OUT_P4_Msk                      (0x01UL << PORT3_OUT_P4_Pos)                            /*!< PORT3 OUT: P4 Mask                      */\r
+#define PORT3_OUT_P5_Pos                      5                                                       /*!< PORT3 OUT: P5 Position                  */\r
+#define PORT3_OUT_P5_Msk                      (0x01UL << PORT3_OUT_P5_Pos)                            /*!< PORT3 OUT: P5 Mask                      */\r
+#define PORT3_OUT_P6_Pos                      6                                                       /*!< PORT3 OUT: P6 Position                  */\r
+#define PORT3_OUT_P6_Msk                      (0x01UL << PORT3_OUT_P6_Pos)                            /*!< PORT3 OUT: P6 Mask                      */\r
+#define PORT3_OUT_P7_Pos                      7                                                       /*!< PORT3 OUT: P7 Position                  */\r
+#define PORT3_OUT_P7_Msk                      (0x01UL << PORT3_OUT_P7_Pos)                            /*!< PORT3 OUT: P7 Mask                      */\r
+#define PORT3_OUT_P8_Pos                      8                                                       /*!< PORT3 OUT: P8 Position                  */\r
+#define PORT3_OUT_P8_Msk                      (0x01UL << PORT3_OUT_P8_Pos)                            /*!< PORT3 OUT: P8 Mask                      */\r
+#define PORT3_OUT_P9_Pos                      9                                                       /*!< PORT3 OUT: P9 Position                  */\r
+#define PORT3_OUT_P9_Msk                      (0x01UL << PORT3_OUT_P9_Pos)                            /*!< PORT3 OUT: P9 Mask                      */\r
+#define PORT3_OUT_P10_Pos                     10                                                      /*!< PORT3 OUT: P10 Position                 */\r
+#define PORT3_OUT_P10_Msk                     (0x01UL << PORT3_OUT_P10_Pos)                           /*!< PORT3 OUT: P10 Mask                     */\r
+#define PORT3_OUT_P11_Pos                     11                                                      /*!< PORT3 OUT: P11 Position                 */\r
+#define PORT3_OUT_P11_Msk                     (0x01UL << PORT3_OUT_P11_Pos)                           /*!< PORT3 OUT: P11 Mask                     */\r
+#define PORT3_OUT_P12_Pos                     12                                                      /*!< PORT3 OUT: P12 Position                 */\r
+#define PORT3_OUT_P12_Msk                     (0x01UL << PORT3_OUT_P12_Pos)                           /*!< PORT3 OUT: P12 Mask                     */\r
+#define PORT3_OUT_P13_Pos                     13                                                      /*!< PORT3 OUT: P13 Position                 */\r
+#define PORT3_OUT_P13_Msk                     (0x01UL << PORT3_OUT_P13_Pos)                           /*!< PORT3 OUT: P13 Mask                     */\r
+#define PORT3_OUT_P14_Pos                     14                                                      /*!< PORT3 OUT: P14 Position                 */\r
+#define PORT3_OUT_P14_Msk                     (0x01UL << PORT3_OUT_P14_Pos)                           /*!< PORT3 OUT: P14 Mask                     */\r
+#define PORT3_OUT_P15_Pos                     15                                                      /*!< PORT3 OUT: P15 Position                 */\r
+#define PORT3_OUT_P15_Msk                     (0x01UL << PORT3_OUT_P15_Pos)                           /*!< PORT3 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT3_OMR  --------------------------------- */\r
+#define PORT3_OMR_PS0_Pos                     0                                                       /*!< PORT3 OMR: PS0 Position                 */\r
+#define PORT3_OMR_PS0_Msk                     (0x01UL << PORT3_OMR_PS0_Pos)                           /*!< PORT3 OMR: PS0 Mask                     */\r
+#define PORT3_OMR_PS1_Pos                     1                                                       /*!< PORT3 OMR: PS1 Position                 */\r
+#define PORT3_OMR_PS1_Msk                     (0x01UL << PORT3_OMR_PS1_Pos)                           /*!< PORT3 OMR: PS1 Mask                     */\r
+#define PORT3_OMR_PS2_Pos                     2                                                       /*!< PORT3 OMR: PS2 Position                 */\r
+#define PORT3_OMR_PS2_Msk                     (0x01UL << PORT3_OMR_PS2_Pos)                           /*!< PORT3 OMR: PS2 Mask                     */\r
+#define PORT3_OMR_PS3_Pos                     3                                                       /*!< PORT3 OMR: PS3 Position                 */\r
+#define PORT3_OMR_PS3_Msk                     (0x01UL << PORT3_OMR_PS3_Pos)                           /*!< PORT3 OMR: PS3 Mask                     */\r
+#define PORT3_OMR_PS4_Pos                     4                                                       /*!< PORT3 OMR: PS4 Position                 */\r
+#define PORT3_OMR_PS4_Msk                     (0x01UL << PORT3_OMR_PS4_Pos)                           /*!< PORT3 OMR: PS4 Mask                     */\r
+#define PORT3_OMR_PS5_Pos                     5                                                       /*!< PORT3 OMR: PS5 Position                 */\r
+#define PORT3_OMR_PS5_Msk                     (0x01UL << PORT3_OMR_PS5_Pos)                           /*!< PORT3 OMR: PS5 Mask                     */\r
+#define PORT3_OMR_PS6_Pos                     6                                                       /*!< PORT3 OMR: PS6 Position                 */\r
+#define PORT3_OMR_PS6_Msk                     (0x01UL << PORT3_OMR_PS6_Pos)                           /*!< PORT3 OMR: PS6 Mask                     */\r
+#define PORT3_OMR_PS7_Pos                     7                                                       /*!< PORT3 OMR: PS7 Position                 */\r
+#define PORT3_OMR_PS7_Msk                     (0x01UL << PORT3_OMR_PS7_Pos)                           /*!< PORT3 OMR: PS7 Mask                     */\r
+#define PORT3_OMR_PS8_Pos                     8                                                       /*!< PORT3 OMR: PS8 Position                 */\r
+#define PORT3_OMR_PS8_Msk                     (0x01UL << PORT3_OMR_PS8_Pos)                           /*!< PORT3 OMR: PS8 Mask                     */\r
+#define PORT3_OMR_PS9_Pos                     9                                                       /*!< PORT3 OMR: PS9 Position                 */\r
+#define PORT3_OMR_PS9_Msk                     (0x01UL << PORT3_OMR_PS9_Pos)                           /*!< PORT3 OMR: PS9 Mask                     */\r
+#define PORT3_OMR_PS10_Pos                    10                                                      /*!< PORT3 OMR: PS10 Position                */\r
+#define PORT3_OMR_PS10_Msk                    (0x01UL << PORT3_OMR_PS10_Pos)                          /*!< PORT3 OMR: PS10 Mask                    */\r
+#define PORT3_OMR_PS11_Pos                    11                                                      /*!< PORT3 OMR: PS11 Position                */\r
+#define PORT3_OMR_PS11_Msk                    (0x01UL << PORT3_OMR_PS11_Pos)                          /*!< PORT3 OMR: PS11 Mask                    */\r
+#define PORT3_OMR_PS12_Pos                    12                                                      /*!< PORT3 OMR: PS12 Position                */\r
+#define PORT3_OMR_PS12_Msk                    (0x01UL << PORT3_OMR_PS12_Pos)                          /*!< PORT3 OMR: PS12 Mask                    */\r
+#define PORT3_OMR_PS13_Pos                    13                                                      /*!< PORT3 OMR: PS13 Position                */\r
+#define PORT3_OMR_PS13_Msk                    (0x01UL << PORT3_OMR_PS13_Pos)                          /*!< PORT3 OMR: PS13 Mask                    */\r
+#define PORT3_OMR_PS14_Pos                    14                                                      /*!< PORT3 OMR: PS14 Position                */\r
+#define PORT3_OMR_PS14_Msk                    (0x01UL << PORT3_OMR_PS14_Pos)                          /*!< PORT3 OMR: PS14 Mask                    */\r
+#define PORT3_OMR_PS15_Pos                    15                                                      /*!< PORT3 OMR: PS15 Position                */\r
+#define PORT3_OMR_PS15_Msk                    (0x01UL << PORT3_OMR_PS15_Pos)                          /*!< PORT3 OMR: PS15 Mask                    */\r
+#define PORT3_OMR_PR0_Pos                     16                                                      /*!< PORT3 OMR: PR0 Position                 */\r
+#define PORT3_OMR_PR0_Msk                     (0x01UL << PORT3_OMR_PR0_Pos)                           /*!< PORT3 OMR: PR0 Mask                     */\r
+#define PORT3_OMR_PR1_Pos                     17                                                      /*!< PORT3 OMR: PR1 Position                 */\r
+#define PORT3_OMR_PR1_Msk                     (0x01UL << PORT3_OMR_PR1_Pos)                           /*!< PORT3 OMR: PR1 Mask                     */\r
+#define PORT3_OMR_PR2_Pos                     18                                                      /*!< PORT3 OMR: PR2 Position                 */\r
+#define PORT3_OMR_PR2_Msk                     (0x01UL << PORT3_OMR_PR2_Pos)                           /*!< PORT3 OMR: PR2 Mask                     */\r
+#define PORT3_OMR_PR3_Pos                     19                                                      /*!< PORT3 OMR: PR3 Position                 */\r
+#define PORT3_OMR_PR3_Msk                     (0x01UL << PORT3_OMR_PR3_Pos)                           /*!< PORT3 OMR: PR3 Mask                     */\r
+#define PORT3_OMR_PR4_Pos                     20                                                      /*!< PORT3 OMR: PR4 Position                 */\r
+#define PORT3_OMR_PR4_Msk                     (0x01UL << PORT3_OMR_PR4_Pos)                           /*!< PORT3 OMR: PR4 Mask                     */\r
+#define PORT3_OMR_PR5_Pos                     21                                                      /*!< PORT3 OMR: PR5 Position                 */\r
+#define PORT3_OMR_PR5_Msk                     (0x01UL << PORT3_OMR_PR5_Pos)                           /*!< PORT3 OMR: PR5 Mask                     */\r
+#define PORT3_OMR_PR6_Pos                     22                                                      /*!< PORT3 OMR: PR6 Position                 */\r
+#define PORT3_OMR_PR6_Msk                     (0x01UL << PORT3_OMR_PR6_Pos)                           /*!< PORT3 OMR: PR6 Mask                     */\r
+#define PORT3_OMR_PR7_Pos                     23                                                      /*!< PORT3 OMR: PR7 Position                 */\r
+#define PORT3_OMR_PR7_Msk                     (0x01UL << PORT3_OMR_PR7_Pos)                           /*!< PORT3 OMR: PR7 Mask                     */\r
+#define PORT3_OMR_PR8_Pos                     24                                                      /*!< PORT3 OMR: PR8 Position                 */\r
+#define PORT3_OMR_PR8_Msk                     (0x01UL << PORT3_OMR_PR8_Pos)                           /*!< PORT3 OMR: PR8 Mask                     */\r
+#define PORT3_OMR_PR9_Pos                     25                                                      /*!< PORT3 OMR: PR9 Position                 */\r
+#define PORT3_OMR_PR9_Msk                     (0x01UL << PORT3_OMR_PR9_Pos)                           /*!< PORT3 OMR: PR9 Mask                     */\r
+#define PORT3_OMR_PR10_Pos                    26                                                      /*!< PORT3 OMR: PR10 Position                */\r
+#define PORT3_OMR_PR10_Msk                    (0x01UL << PORT3_OMR_PR10_Pos)                          /*!< PORT3 OMR: PR10 Mask                    */\r
+#define PORT3_OMR_PR11_Pos                    27                                                      /*!< PORT3 OMR: PR11 Position                */\r
+#define PORT3_OMR_PR11_Msk                    (0x01UL << PORT3_OMR_PR11_Pos)                          /*!< PORT3 OMR: PR11 Mask                    */\r
+#define PORT3_OMR_PR12_Pos                    28                                                      /*!< PORT3 OMR: PR12 Position                */\r
+#define PORT3_OMR_PR12_Msk                    (0x01UL << PORT3_OMR_PR12_Pos)                          /*!< PORT3 OMR: PR12 Mask                    */\r
+#define PORT3_OMR_PR13_Pos                    29                                                      /*!< PORT3 OMR: PR13 Position                */\r
+#define PORT3_OMR_PR13_Msk                    (0x01UL << PORT3_OMR_PR13_Pos)                          /*!< PORT3 OMR: PR13 Mask                    */\r
+#define PORT3_OMR_PR14_Pos                    30                                                      /*!< PORT3 OMR: PR14 Position                */\r
+#define PORT3_OMR_PR14_Msk                    (0x01UL << PORT3_OMR_PR14_Pos)                          /*!< PORT3 OMR: PR14 Mask                    */\r
+#define PORT3_OMR_PR15_Pos                    31                                                      /*!< PORT3 OMR: PR15 Position                */\r
+#define PORT3_OMR_PR15_Msk                    (0x01UL << PORT3_OMR_PR15_Pos)                          /*!< PORT3 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT3_IOCR0  -------------------------------- */\r
+#define PORT3_IOCR0_PC0_Pos                   3                                                       /*!< PORT3 IOCR0: PC0 Position               */\r
+#define PORT3_IOCR0_PC0_Msk                   (0x1fUL << PORT3_IOCR0_PC0_Pos)                         /*!< PORT3 IOCR0: PC0 Mask                   */\r
+#define PORT3_IOCR0_PC1_Pos                   11                                                      /*!< PORT3 IOCR0: PC1 Position               */\r
+#define PORT3_IOCR0_PC1_Msk                   (0x1fUL << PORT3_IOCR0_PC1_Pos)                         /*!< PORT3 IOCR0: PC1 Mask                   */\r
+#define PORT3_IOCR0_PC2_Pos                   19                                                      /*!< PORT3 IOCR0: PC2 Position               */\r
+#define PORT3_IOCR0_PC2_Msk                   (0x1fUL << PORT3_IOCR0_PC2_Pos)                         /*!< PORT3 IOCR0: PC2 Mask                   */\r
+#define PORT3_IOCR0_PC3_Pos                   27                                                      /*!< PORT3 IOCR0: PC3 Position               */\r
+#define PORT3_IOCR0_PC3_Msk                   (0x1fUL << PORT3_IOCR0_PC3_Pos)                         /*!< PORT3 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT3_IOCR4  -------------------------------- */\r
+#define PORT3_IOCR4_PC4_Pos                   3                                                       /*!< PORT3 IOCR4: PC4 Position               */\r
+#define PORT3_IOCR4_PC4_Msk                   (0x1fUL << PORT3_IOCR4_PC4_Pos)                         /*!< PORT3 IOCR4: PC4 Mask                   */\r
+#define PORT3_IOCR4_PC5_Pos                   11                                                      /*!< PORT3 IOCR4: PC5 Position               */\r
+#define PORT3_IOCR4_PC5_Msk                   (0x1fUL << PORT3_IOCR4_PC5_Pos)                         /*!< PORT3 IOCR4: PC5 Mask                   */\r
+#define PORT3_IOCR4_PC6_Pos                   19                                                      /*!< PORT3 IOCR4: PC6 Position               */\r
+#define PORT3_IOCR4_PC6_Msk                   (0x1fUL << PORT3_IOCR4_PC6_Pos)                         /*!< PORT3 IOCR4: PC6 Mask                   */\r
+#define PORT3_IOCR4_PC7_Pos                   27                                                      /*!< PORT3 IOCR4: PC7 Position               */\r
+#define PORT3_IOCR4_PC7_Msk                   (0x1fUL << PORT3_IOCR4_PC7_Pos)                         /*!< PORT3 IOCR4: PC7 Mask                   */\r
+\r
+/* ----------------------------------  PORT3_IN  ---------------------------------- */\r
+#define PORT3_IN_P0_Pos                       0                                                       /*!< PORT3 IN: P0 Position                   */\r
+#define PORT3_IN_P0_Msk                       (0x01UL << PORT3_IN_P0_Pos)                             /*!< PORT3 IN: P0 Mask                       */\r
+#define PORT3_IN_P1_Pos                       1                                                       /*!< PORT3 IN: P1 Position                   */\r
+#define PORT3_IN_P1_Msk                       (0x01UL << PORT3_IN_P1_Pos)                             /*!< PORT3 IN: P1 Mask                       */\r
+#define PORT3_IN_P2_Pos                       2                                                       /*!< PORT3 IN: P2 Position                   */\r
+#define PORT3_IN_P2_Msk                       (0x01UL << PORT3_IN_P2_Pos)                             /*!< PORT3 IN: P2 Mask                       */\r
+#define PORT3_IN_P3_Pos                       3                                                       /*!< PORT3 IN: P3 Position                   */\r
+#define PORT3_IN_P3_Msk                       (0x01UL << PORT3_IN_P3_Pos)                             /*!< PORT3 IN: P3 Mask                       */\r
+#define PORT3_IN_P4_Pos                       4                                                       /*!< PORT3 IN: P4 Position                   */\r
+#define PORT3_IN_P4_Msk                       (0x01UL << PORT3_IN_P4_Pos)                             /*!< PORT3 IN: P4 Mask                       */\r
+#define PORT3_IN_P5_Pos                       5                                                       /*!< PORT3 IN: P5 Position                   */\r
+#define PORT3_IN_P5_Msk                       (0x01UL << PORT3_IN_P5_Pos)                             /*!< PORT3 IN: P5 Mask                       */\r
+#define PORT3_IN_P6_Pos                       6                                                       /*!< PORT3 IN: P6 Position                   */\r
+#define PORT3_IN_P6_Msk                       (0x01UL << PORT3_IN_P6_Pos)                             /*!< PORT3 IN: P6 Mask                       */\r
+#define PORT3_IN_P7_Pos                       7                                                       /*!< PORT3 IN: P7 Position                   */\r
+#define PORT3_IN_P7_Msk                       (0x01UL << PORT3_IN_P7_Pos)                             /*!< PORT3 IN: P7 Mask                       */\r
+#define PORT3_IN_P8_Pos                       8                                                       /*!< PORT3 IN: P8 Position                   */\r
+#define PORT3_IN_P8_Msk                       (0x01UL << PORT3_IN_P8_Pos)                             /*!< PORT3 IN: P8 Mask                       */\r
+#define PORT3_IN_P9_Pos                       9                                                       /*!< PORT3 IN: P9 Position                   */\r
+#define PORT3_IN_P9_Msk                       (0x01UL << PORT3_IN_P9_Pos)                             /*!< PORT3 IN: P9 Mask                       */\r
+#define PORT3_IN_P10_Pos                      10                                                      /*!< PORT3 IN: P10 Position                  */\r
+#define PORT3_IN_P10_Msk                      (0x01UL << PORT3_IN_P10_Pos)                            /*!< PORT3 IN: P10 Mask                      */\r
+#define PORT3_IN_P11_Pos                      11                                                      /*!< PORT3 IN: P11 Position                  */\r
+#define PORT3_IN_P11_Msk                      (0x01UL << PORT3_IN_P11_Pos)                            /*!< PORT3 IN: P11 Mask                      */\r
+#define PORT3_IN_P12_Pos                      12                                                      /*!< PORT3 IN: P12 Position                  */\r
+#define PORT3_IN_P12_Msk                      (0x01UL << PORT3_IN_P12_Pos)                            /*!< PORT3 IN: P12 Mask                      */\r
+#define PORT3_IN_P13_Pos                      13                                                      /*!< PORT3 IN: P13 Position                  */\r
+#define PORT3_IN_P13_Msk                      (0x01UL << PORT3_IN_P13_Pos)                            /*!< PORT3 IN: P13 Mask                      */\r
+#define PORT3_IN_P14_Pos                      14                                                      /*!< PORT3 IN: P14 Position                  */\r
+#define PORT3_IN_P14_Msk                      (0x01UL << PORT3_IN_P14_Pos)                            /*!< PORT3 IN: P14 Mask                      */\r
+#define PORT3_IN_P15_Pos                      15                                                      /*!< PORT3 IN: P15 Position                  */\r
+#define PORT3_IN_P15_Msk                      (0x01UL << PORT3_IN_P15_Pos)                            /*!< PORT3 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT3_PDR0  --------------------------------- */\r
+#define PORT3_PDR0_PD0_Pos                    0                                                       /*!< PORT3 PDR0: PD0 Position                */\r
+#define PORT3_PDR0_PD0_Msk                    (0x07UL << PORT3_PDR0_PD0_Pos)                          /*!< PORT3 PDR0: PD0 Mask                    */\r
+#define PORT3_PDR0_PD1_Pos                    4                                                       /*!< PORT3 PDR0: PD1 Position                */\r
+#define PORT3_PDR0_PD1_Msk                    (0x07UL << PORT3_PDR0_PD1_Pos)                          /*!< PORT3 PDR0: PD1 Mask                    */\r
+#define PORT3_PDR0_PD2_Pos                    8                                                       /*!< PORT3 PDR0: PD2 Position                */\r
+#define PORT3_PDR0_PD2_Msk                    (0x07UL << PORT3_PDR0_PD2_Pos)                          /*!< PORT3 PDR0: PD2 Mask                    */\r
+#define PORT3_PDR0_PD3_Pos                    12                                                      /*!< PORT3 PDR0: PD3 Position                */\r
+#define PORT3_PDR0_PD3_Msk                    (0x07UL << PORT3_PDR0_PD3_Pos)                          /*!< PORT3 PDR0: PD3 Mask                    */\r
+#define PORT3_PDR0_PD4_Pos                    16                                                      /*!< PORT3 PDR0: PD4 Position                */\r
+#define PORT3_PDR0_PD4_Msk                    (0x07UL << PORT3_PDR0_PD4_Pos)                          /*!< PORT3 PDR0: PD4 Mask                    */\r
+#define PORT3_PDR0_PD5_Pos                    20                                                      /*!< PORT3 PDR0: PD5 Position                */\r
+#define PORT3_PDR0_PD5_Msk                    (0x07UL << PORT3_PDR0_PD5_Pos)                          /*!< PORT3 PDR0: PD5 Mask                    */\r
+#define PORT3_PDR0_PD6_Pos                    24                                                      /*!< PORT3 PDR0: PD6 Position                */\r
+#define PORT3_PDR0_PD6_Msk                    (0x07UL << PORT3_PDR0_PD6_Pos)                          /*!< PORT3 PDR0: PD6 Mask                    */\r
+#define PORT3_PDR0_PD7_Pos                    28                                                      /*!< PORT3 PDR0: PD7 Position                */\r
+#define PORT3_PDR0_PD7_Msk                    (0x07UL << PORT3_PDR0_PD7_Pos)                          /*!< PORT3 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT3_PDISC  -------------------------------- */\r
+#define PORT3_PDISC_PDIS0_Pos                 0                                                       /*!< PORT3 PDISC: PDIS0 Position             */\r
+#define PORT3_PDISC_PDIS0_Msk                 (0x01UL << PORT3_PDISC_PDIS0_Pos)                       /*!< PORT3 PDISC: PDIS0 Mask                 */\r
+#define PORT3_PDISC_PDIS1_Pos                 1                                                       /*!< PORT3 PDISC: PDIS1 Position             */\r
+#define PORT3_PDISC_PDIS1_Msk                 (0x01UL << PORT3_PDISC_PDIS1_Pos)                       /*!< PORT3 PDISC: PDIS1 Mask                 */\r
+#define PORT3_PDISC_PDIS2_Pos                 2                                                       /*!< PORT3 PDISC: PDIS2 Position             */\r
+#define PORT3_PDISC_PDIS2_Msk                 (0x01UL << PORT3_PDISC_PDIS2_Pos)                       /*!< PORT3 PDISC: PDIS2 Mask                 */\r
+#define PORT3_PDISC_PDIS3_Pos                 3                                                       /*!< PORT3 PDISC: PDIS3 Position             */\r
+#define PORT3_PDISC_PDIS3_Msk                 (0x01UL << PORT3_PDISC_PDIS3_Pos)                       /*!< PORT3 PDISC: PDIS3 Mask                 */\r
+#define PORT3_PDISC_PDIS4_Pos                 4                                                       /*!< PORT3 PDISC: PDIS4 Position             */\r
+#define PORT3_PDISC_PDIS4_Msk                 (0x01UL << PORT3_PDISC_PDIS4_Pos)                       /*!< PORT3 PDISC: PDIS4 Mask                 */\r
+#define PORT3_PDISC_PDIS5_Pos                 5                                                       /*!< PORT3 PDISC: PDIS5 Position             */\r
+#define PORT3_PDISC_PDIS5_Msk                 (0x01UL << PORT3_PDISC_PDIS5_Pos)                       /*!< PORT3 PDISC: PDIS5 Mask                 */\r
+#define PORT3_PDISC_PDIS6_Pos                 6                                                       /*!< PORT3 PDISC: PDIS6 Position             */\r
+#define PORT3_PDISC_PDIS6_Msk                 (0x01UL << PORT3_PDISC_PDIS6_Pos)                       /*!< PORT3 PDISC: PDIS6 Mask                 */\r
+#define PORT3_PDISC_PDIS7_Pos                 7                                                       /*!< PORT3 PDISC: PDIS7 Position             */\r
+#define PORT3_PDISC_PDIS7_Msk                 (0x01UL << PORT3_PDISC_PDIS7_Pos)                       /*!< PORT3 PDISC: PDIS7 Mask                 */\r
+#define PORT3_PDISC_PDIS8_Pos                 8                                                       /*!< PORT3 PDISC: PDIS8 Position             */\r
+#define PORT3_PDISC_PDIS8_Msk                 (0x01UL << PORT3_PDISC_PDIS8_Pos)                       /*!< PORT3 PDISC: PDIS8 Mask                 */\r
+#define PORT3_PDISC_PDIS9_Pos                 9                                                       /*!< PORT3 PDISC: PDIS9 Position             */\r
+#define PORT3_PDISC_PDIS9_Msk                 (0x01UL << PORT3_PDISC_PDIS9_Pos)                       /*!< PORT3 PDISC: PDIS9 Mask                 */\r
+#define PORT3_PDISC_PDIS10_Pos                10                                                      /*!< PORT3 PDISC: PDIS10 Position            */\r
+#define PORT3_PDISC_PDIS10_Msk                (0x01UL << PORT3_PDISC_PDIS10_Pos)                      /*!< PORT3 PDISC: PDIS10 Mask                */\r
+#define PORT3_PDISC_PDIS11_Pos                11                                                      /*!< PORT3 PDISC: PDIS11 Position            */\r
+#define PORT3_PDISC_PDIS11_Msk                (0x01UL << PORT3_PDISC_PDIS11_Pos)                      /*!< PORT3 PDISC: PDIS11 Mask                */\r
+#define PORT3_PDISC_PDIS12_Pos                12                                                      /*!< PORT3 PDISC: PDIS12 Position            */\r
+#define PORT3_PDISC_PDIS12_Msk                (0x01UL << PORT3_PDISC_PDIS12_Pos)                      /*!< PORT3 PDISC: PDIS12 Mask                */\r
+#define PORT3_PDISC_PDIS13_Pos                13                                                      /*!< PORT3 PDISC: PDIS13 Position            */\r
+#define PORT3_PDISC_PDIS13_Msk                (0x01UL << PORT3_PDISC_PDIS13_Pos)                      /*!< PORT3 PDISC: PDIS13 Mask                */\r
+#define PORT3_PDISC_PDIS14_Pos                14                                                      /*!< PORT3 PDISC: PDIS14 Position            */\r
+#define PORT3_PDISC_PDIS14_Msk                (0x01UL << PORT3_PDISC_PDIS14_Pos)                      /*!< PORT3 PDISC: PDIS14 Mask                */\r
+#define PORT3_PDISC_PDIS15_Pos                15                                                      /*!< PORT3 PDISC: PDIS15 Position            */\r
+#define PORT3_PDISC_PDIS15_Msk                (0x01UL << PORT3_PDISC_PDIS15_Pos)                      /*!< PORT3 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT3_PPS  --------------------------------- */\r
+#define PORT3_PPS_PPS0_Pos                    0                                                       /*!< PORT3 PPS: PPS0 Position                */\r
+#define PORT3_PPS_PPS0_Msk                    (0x01UL << PORT3_PPS_PPS0_Pos)                          /*!< PORT3 PPS: PPS0 Mask                    */\r
+#define PORT3_PPS_PPS1_Pos                    1                                                       /*!< PORT3 PPS: PPS1 Position                */\r
+#define PORT3_PPS_PPS1_Msk                    (0x01UL << PORT3_PPS_PPS1_Pos)                          /*!< PORT3 PPS: PPS1 Mask                    */\r
+#define PORT3_PPS_PPS2_Pos                    2                                                       /*!< PORT3 PPS: PPS2 Position                */\r
+#define PORT3_PPS_PPS2_Msk                    (0x01UL << PORT3_PPS_PPS2_Pos)                          /*!< PORT3 PPS: PPS2 Mask                    */\r
+#define PORT3_PPS_PPS3_Pos                    3                                                       /*!< PORT3 PPS: PPS3 Position                */\r
+#define PORT3_PPS_PPS3_Msk                    (0x01UL << PORT3_PPS_PPS3_Pos)                          /*!< PORT3 PPS: PPS3 Mask                    */\r
+#define PORT3_PPS_PPS4_Pos                    4                                                       /*!< PORT3 PPS: PPS4 Position                */\r
+#define PORT3_PPS_PPS4_Msk                    (0x01UL << PORT3_PPS_PPS4_Pos)                          /*!< PORT3 PPS: PPS4 Mask                    */\r
+#define PORT3_PPS_PPS5_Pos                    5                                                       /*!< PORT3 PPS: PPS5 Position                */\r
+#define PORT3_PPS_PPS5_Msk                    (0x01UL << PORT3_PPS_PPS5_Pos)                          /*!< PORT3 PPS: PPS5 Mask                    */\r
+#define PORT3_PPS_PPS6_Pos                    6                                                       /*!< PORT3 PPS: PPS6 Position                */\r
+#define PORT3_PPS_PPS6_Msk                    (0x01UL << PORT3_PPS_PPS6_Pos)                          /*!< PORT3 PPS: PPS6 Mask                    */\r
+#define PORT3_PPS_PPS7_Pos                    7                                                       /*!< PORT3 PPS: PPS7 Position                */\r
+#define PORT3_PPS_PPS7_Msk                    (0x01UL << PORT3_PPS_PPS7_Pos)                          /*!< PORT3 PPS: PPS7 Mask                    */\r
+#define PORT3_PPS_PPS8_Pos                    8                                                       /*!< PORT3 PPS: PPS8 Position                */\r
+#define PORT3_PPS_PPS8_Msk                    (0x01UL << PORT3_PPS_PPS8_Pos)                          /*!< PORT3 PPS: PPS8 Mask                    */\r
+#define PORT3_PPS_PPS9_Pos                    9                                                       /*!< PORT3 PPS: PPS9 Position                */\r
+#define PORT3_PPS_PPS9_Msk                    (0x01UL << PORT3_PPS_PPS9_Pos)                          /*!< PORT3 PPS: PPS9 Mask                    */\r
+#define PORT3_PPS_PPS10_Pos                   10                                                      /*!< PORT3 PPS: PPS10 Position               */\r
+#define PORT3_PPS_PPS10_Msk                   (0x01UL << PORT3_PPS_PPS10_Pos)                         /*!< PORT3 PPS: PPS10 Mask                   */\r
+#define PORT3_PPS_PPS11_Pos                   11                                                      /*!< PORT3 PPS: PPS11 Position               */\r
+#define PORT3_PPS_PPS11_Msk                   (0x01UL << PORT3_PPS_PPS11_Pos)                         /*!< PORT3 PPS: PPS11 Mask                   */\r
+#define PORT3_PPS_PPS12_Pos                   12                                                      /*!< PORT3 PPS: PPS12 Position               */\r
+#define PORT3_PPS_PPS12_Msk                   (0x01UL << PORT3_PPS_PPS12_Pos)                         /*!< PORT3 PPS: PPS12 Mask                   */\r
+#define PORT3_PPS_PPS13_Pos                   13                                                      /*!< PORT3 PPS: PPS13 Position               */\r
+#define PORT3_PPS_PPS13_Msk                   (0x01UL << PORT3_PPS_PPS13_Pos)                         /*!< PORT3 PPS: PPS13 Mask                   */\r
+#define PORT3_PPS_PPS14_Pos                   14                                                      /*!< PORT3 PPS: PPS14 Position               */\r
+#define PORT3_PPS_PPS14_Msk                   (0x01UL << PORT3_PPS_PPS14_Pos)                         /*!< PORT3 PPS: PPS14 Mask                   */\r
+#define PORT3_PPS_PPS15_Pos                   15                                                      /*!< PORT3 PPS: PPS15 Position               */\r
+#define PORT3_PPS_PPS15_Msk                   (0x01UL << PORT3_PPS_PPS15_Pos)                         /*!< PORT3 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT3_HWSEL  -------------------------------- */\r
+#define PORT3_HWSEL_HW0_Pos                   0                                                       /*!< PORT3 HWSEL: HW0 Position               */\r
+#define PORT3_HWSEL_HW0_Msk                   (0x03UL << PORT3_HWSEL_HW0_Pos)                         /*!< PORT3 HWSEL: HW0 Mask                   */\r
+#define PORT3_HWSEL_HW1_Pos                   2                                                       /*!< PORT3 HWSEL: HW1 Position               */\r
+#define PORT3_HWSEL_HW1_Msk                   (0x03UL << PORT3_HWSEL_HW1_Pos)                         /*!< PORT3 HWSEL: HW1 Mask                   */\r
+#define PORT3_HWSEL_HW2_Pos                   4                                                       /*!< PORT3 HWSEL: HW2 Position               */\r
+#define PORT3_HWSEL_HW2_Msk                   (0x03UL << PORT3_HWSEL_HW2_Pos)                         /*!< PORT3 HWSEL: HW2 Mask                   */\r
+#define PORT3_HWSEL_HW3_Pos                   6                                                       /*!< PORT3 HWSEL: HW3 Position               */\r
+#define PORT3_HWSEL_HW3_Msk                   (0x03UL << PORT3_HWSEL_HW3_Pos)                         /*!< PORT3 HWSEL: HW3 Mask                   */\r
+#define PORT3_HWSEL_HW4_Pos                   8                                                       /*!< PORT3 HWSEL: HW4 Position               */\r
+#define PORT3_HWSEL_HW4_Msk                   (0x03UL << PORT3_HWSEL_HW4_Pos)                         /*!< PORT3 HWSEL: HW4 Mask                   */\r
+#define PORT3_HWSEL_HW5_Pos                   10                                                      /*!< PORT3 HWSEL: HW5 Position               */\r
+#define PORT3_HWSEL_HW5_Msk                   (0x03UL << PORT3_HWSEL_HW5_Pos)                         /*!< PORT3 HWSEL: HW5 Mask                   */\r
+#define PORT3_HWSEL_HW6_Pos                   12                                                      /*!< PORT3 HWSEL: HW6 Position               */\r
+#define PORT3_HWSEL_HW6_Msk                   (0x03UL << PORT3_HWSEL_HW6_Pos)                         /*!< PORT3 HWSEL: HW6 Mask                   */\r
+#define PORT3_HWSEL_HW7_Pos                   14                                                      /*!< PORT3 HWSEL: HW7 Position               */\r
+#define PORT3_HWSEL_HW7_Msk                   (0x03UL << PORT3_HWSEL_HW7_Pos)                         /*!< PORT3 HWSEL: HW7 Mask                   */\r
+#define PORT3_HWSEL_HW8_Pos                   16                                                      /*!< PORT3 HWSEL: HW8 Position               */\r
+#define PORT3_HWSEL_HW8_Msk                   (0x03UL << PORT3_HWSEL_HW8_Pos)                         /*!< PORT3 HWSEL: HW8 Mask                   */\r
+#define PORT3_HWSEL_HW9_Pos                   18                                                      /*!< PORT3 HWSEL: HW9 Position               */\r
+#define PORT3_HWSEL_HW9_Msk                   (0x03UL << PORT3_HWSEL_HW9_Pos)                         /*!< PORT3 HWSEL: HW9 Mask                   */\r
+#define PORT3_HWSEL_HW10_Pos                  20                                                      /*!< PORT3 HWSEL: HW10 Position              */\r
+#define PORT3_HWSEL_HW10_Msk                  (0x03UL << PORT3_HWSEL_HW10_Pos)                        /*!< PORT3 HWSEL: HW10 Mask                  */\r
+#define PORT3_HWSEL_HW11_Pos                  22                                                      /*!< PORT3 HWSEL: HW11 Position              */\r
+#define PORT3_HWSEL_HW11_Msk                  (0x03UL << PORT3_HWSEL_HW11_Pos)                        /*!< PORT3 HWSEL: HW11 Mask                  */\r
+#define PORT3_HWSEL_HW12_Pos                  24                                                      /*!< PORT3 HWSEL: HW12 Position              */\r
+#define PORT3_HWSEL_HW12_Msk                  (0x03UL << PORT3_HWSEL_HW12_Pos)                        /*!< PORT3 HWSEL: HW12 Mask                  */\r
+#define PORT3_HWSEL_HW13_Pos                  26                                                      /*!< PORT3 HWSEL: HW13 Position              */\r
+#define PORT3_HWSEL_HW13_Msk                  (0x03UL << PORT3_HWSEL_HW13_Pos)                        /*!< PORT3 HWSEL: HW13 Mask                  */\r
+#define PORT3_HWSEL_HW14_Pos                  28                                                      /*!< PORT3 HWSEL: HW14 Position              */\r
+#define PORT3_HWSEL_HW14_Msk                  (0x03UL << PORT3_HWSEL_HW14_Pos)                        /*!< PORT3 HWSEL: HW14 Mask                  */\r
+#define PORT3_HWSEL_HW15_Pos                  30                                                      /*!< PORT3 HWSEL: HW15 Position              */\r
+#define PORT3_HWSEL_HW15_Msk                  (0x03UL << PORT3_HWSEL_HW15_Pos)                        /*!< PORT3 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT4' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT4_OUT  --------------------------------- */\r
+#define PORT4_OUT_P0_Pos                      0                                                       /*!< PORT4 OUT: P0 Position                  */\r
+#define PORT4_OUT_P0_Msk                      (0x01UL << PORT4_OUT_P0_Pos)                            /*!< PORT4 OUT: P0 Mask                      */\r
+#define PORT4_OUT_P1_Pos                      1                                                       /*!< PORT4 OUT: P1 Position                  */\r
+#define PORT4_OUT_P1_Msk                      (0x01UL << PORT4_OUT_P1_Pos)                            /*!< PORT4 OUT: P1 Mask                      */\r
+#define PORT4_OUT_P2_Pos                      2                                                       /*!< PORT4 OUT: P2 Position                  */\r
+#define PORT4_OUT_P2_Msk                      (0x01UL << PORT4_OUT_P2_Pos)                            /*!< PORT4 OUT: P2 Mask                      */\r
+#define PORT4_OUT_P3_Pos                      3                                                       /*!< PORT4 OUT: P3 Position                  */\r
+#define PORT4_OUT_P3_Msk                      (0x01UL << PORT4_OUT_P3_Pos)                            /*!< PORT4 OUT: P3 Mask                      */\r
+#define PORT4_OUT_P4_Pos                      4                                                       /*!< PORT4 OUT: P4 Position                  */\r
+#define PORT4_OUT_P4_Msk                      (0x01UL << PORT4_OUT_P4_Pos)                            /*!< PORT4 OUT: P4 Mask                      */\r
+#define PORT4_OUT_P5_Pos                      5                                                       /*!< PORT4 OUT: P5 Position                  */\r
+#define PORT4_OUT_P5_Msk                      (0x01UL << PORT4_OUT_P5_Pos)                            /*!< PORT4 OUT: P5 Mask                      */\r
+#define PORT4_OUT_P6_Pos                      6                                                       /*!< PORT4 OUT: P6 Position                  */\r
+#define PORT4_OUT_P6_Msk                      (0x01UL << PORT4_OUT_P6_Pos)                            /*!< PORT4 OUT: P6 Mask                      */\r
+#define PORT4_OUT_P7_Pos                      7                                                       /*!< PORT4 OUT: P7 Position                  */\r
+#define PORT4_OUT_P7_Msk                      (0x01UL << PORT4_OUT_P7_Pos)                            /*!< PORT4 OUT: P7 Mask                      */\r
+#define PORT4_OUT_P8_Pos                      8                                                       /*!< PORT4 OUT: P8 Position                  */\r
+#define PORT4_OUT_P8_Msk                      (0x01UL << PORT4_OUT_P8_Pos)                            /*!< PORT4 OUT: P8 Mask                      */\r
+#define PORT4_OUT_P9_Pos                      9                                                       /*!< PORT4 OUT: P9 Position                  */\r
+#define PORT4_OUT_P9_Msk                      (0x01UL << PORT4_OUT_P9_Pos)                            /*!< PORT4 OUT: P9 Mask                      */\r
+#define PORT4_OUT_P10_Pos                     10                                                      /*!< PORT4 OUT: P10 Position                 */\r
+#define PORT4_OUT_P10_Msk                     (0x01UL << PORT4_OUT_P10_Pos)                           /*!< PORT4 OUT: P10 Mask                     */\r
+#define PORT4_OUT_P11_Pos                     11                                                      /*!< PORT4 OUT: P11 Position                 */\r
+#define PORT4_OUT_P11_Msk                     (0x01UL << PORT4_OUT_P11_Pos)                           /*!< PORT4 OUT: P11 Mask                     */\r
+#define PORT4_OUT_P12_Pos                     12                                                      /*!< PORT4 OUT: P12 Position                 */\r
+#define PORT4_OUT_P12_Msk                     (0x01UL << PORT4_OUT_P12_Pos)                           /*!< PORT4 OUT: P12 Mask                     */\r
+#define PORT4_OUT_P13_Pos                     13                                                      /*!< PORT4 OUT: P13 Position                 */\r
+#define PORT4_OUT_P13_Msk                     (0x01UL << PORT4_OUT_P13_Pos)                           /*!< PORT4 OUT: P13 Mask                     */\r
+#define PORT4_OUT_P14_Pos                     14                                                      /*!< PORT4 OUT: P14 Position                 */\r
+#define PORT4_OUT_P14_Msk                     (0x01UL << PORT4_OUT_P14_Pos)                           /*!< PORT4 OUT: P14 Mask                     */\r
+#define PORT4_OUT_P15_Pos                     15                                                      /*!< PORT4 OUT: P15 Position                 */\r
+#define PORT4_OUT_P15_Msk                     (0x01UL << PORT4_OUT_P15_Pos)                           /*!< PORT4 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT4_OMR  --------------------------------- */\r
+#define PORT4_OMR_PS0_Pos                     0                                                       /*!< PORT4 OMR: PS0 Position                 */\r
+#define PORT4_OMR_PS0_Msk                     (0x01UL << PORT4_OMR_PS0_Pos)                           /*!< PORT4 OMR: PS0 Mask                     */\r
+#define PORT4_OMR_PS1_Pos                     1                                                       /*!< PORT4 OMR: PS1 Position                 */\r
+#define PORT4_OMR_PS1_Msk                     (0x01UL << PORT4_OMR_PS1_Pos)                           /*!< PORT4 OMR: PS1 Mask                     */\r
+#define PORT4_OMR_PS2_Pos                     2                                                       /*!< PORT4 OMR: PS2 Position                 */\r
+#define PORT4_OMR_PS2_Msk                     (0x01UL << PORT4_OMR_PS2_Pos)                           /*!< PORT4 OMR: PS2 Mask                     */\r
+#define PORT4_OMR_PS3_Pos                     3                                                       /*!< PORT4 OMR: PS3 Position                 */\r
+#define PORT4_OMR_PS3_Msk                     (0x01UL << PORT4_OMR_PS3_Pos)                           /*!< PORT4 OMR: PS3 Mask                     */\r
+#define PORT4_OMR_PS4_Pos                     4                                                       /*!< PORT4 OMR: PS4 Position                 */\r
+#define PORT4_OMR_PS4_Msk                     (0x01UL << PORT4_OMR_PS4_Pos)                           /*!< PORT4 OMR: PS4 Mask                     */\r
+#define PORT4_OMR_PS5_Pos                     5                                                       /*!< PORT4 OMR: PS5 Position                 */\r
+#define PORT4_OMR_PS5_Msk                     (0x01UL << PORT4_OMR_PS5_Pos)                           /*!< PORT4 OMR: PS5 Mask                     */\r
+#define PORT4_OMR_PS6_Pos                     6                                                       /*!< PORT4 OMR: PS6 Position                 */\r
+#define PORT4_OMR_PS6_Msk                     (0x01UL << PORT4_OMR_PS6_Pos)                           /*!< PORT4 OMR: PS6 Mask                     */\r
+#define PORT4_OMR_PS7_Pos                     7                                                       /*!< PORT4 OMR: PS7 Position                 */\r
+#define PORT4_OMR_PS7_Msk                     (0x01UL << PORT4_OMR_PS7_Pos)                           /*!< PORT4 OMR: PS7 Mask                     */\r
+#define PORT4_OMR_PS8_Pos                     8                                                       /*!< PORT4 OMR: PS8 Position                 */\r
+#define PORT4_OMR_PS8_Msk                     (0x01UL << PORT4_OMR_PS8_Pos)                           /*!< PORT4 OMR: PS8 Mask                     */\r
+#define PORT4_OMR_PS9_Pos                     9                                                       /*!< PORT4 OMR: PS9 Position                 */\r
+#define PORT4_OMR_PS9_Msk                     (0x01UL << PORT4_OMR_PS9_Pos)                           /*!< PORT4 OMR: PS9 Mask                     */\r
+#define PORT4_OMR_PS10_Pos                    10                                                      /*!< PORT4 OMR: PS10 Position                */\r
+#define PORT4_OMR_PS10_Msk                    (0x01UL << PORT4_OMR_PS10_Pos)                          /*!< PORT4 OMR: PS10 Mask                    */\r
+#define PORT4_OMR_PS11_Pos                    11                                                      /*!< PORT4 OMR: PS11 Position                */\r
+#define PORT4_OMR_PS11_Msk                    (0x01UL << PORT4_OMR_PS11_Pos)                          /*!< PORT4 OMR: PS11 Mask                    */\r
+#define PORT4_OMR_PS12_Pos                    12                                                      /*!< PORT4 OMR: PS12 Position                */\r
+#define PORT4_OMR_PS12_Msk                    (0x01UL << PORT4_OMR_PS12_Pos)                          /*!< PORT4 OMR: PS12 Mask                    */\r
+#define PORT4_OMR_PS13_Pos                    13                                                      /*!< PORT4 OMR: PS13 Position                */\r
+#define PORT4_OMR_PS13_Msk                    (0x01UL << PORT4_OMR_PS13_Pos)                          /*!< PORT4 OMR: PS13 Mask                    */\r
+#define PORT4_OMR_PS14_Pos                    14                                                      /*!< PORT4 OMR: PS14 Position                */\r
+#define PORT4_OMR_PS14_Msk                    (0x01UL << PORT4_OMR_PS14_Pos)                          /*!< PORT4 OMR: PS14 Mask                    */\r
+#define PORT4_OMR_PS15_Pos                    15                                                      /*!< PORT4 OMR: PS15 Position                */\r
+#define PORT4_OMR_PS15_Msk                    (0x01UL << PORT4_OMR_PS15_Pos)                          /*!< PORT4 OMR: PS15 Mask                    */\r
+#define PORT4_OMR_PR0_Pos                     16                                                      /*!< PORT4 OMR: PR0 Position                 */\r
+#define PORT4_OMR_PR0_Msk                     (0x01UL << PORT4_OMR_PR0_Pos)                           /*!< PORT4 OMR: PR0 Mask                     */\r
+#define PORT4_OMR_PR1_Pos                     17                                                      /*!< PORT4 OMR: PR1 Position                 */\r
+#define PORT4_OMR_PR1_Msk                     (0x01UL << PORT4_OMR_PR1_Pos)                           /*!< PORT4 OMR: PR1 Mask                     */\r
+#define PORT4_OMR_PR2_Pos                     18                                                      /*!< PORT4 OMR: PR2 Position                 */\r
+#define PORT4_OMR_PR2_Msk                     (0x01UL << PORT4_OMR_PR2_Pos)                           /*!< PORT4 OMR: PR2 Mask                     */\r
+#define PORT4_OMR_PR3_Pos                     19                                                      /*!< PORT4 OMR: PR3 Position                 */\r
+#define PORT4_OMR_PR3_Msk                     (0x01UL << PORT4_OMR_PR3_Pos)                           /*!< PORT4 OMR: PR3 Mask                     */\r
+#define PORT4_OMR_PR4_Pos                     20                                                      /*!< PORT4 OMR: PR4 Position                 */\r
+#define PORT4_OMR_PR4_Msk                     (0x01UL << PORT4_OMR_PR4_Pos)                           /*!< PORT4 OMR: PR4 Mask                     */\r
+#define PORT4_OMR_PR5_Pos                     21                                                      /*!< PORT4 OMR: PR5 Position                 */\r
+#define PORT4_OMR_PR5_Msk                     (0x01UL << PORT4_OMR_PR5_Pos)                           /*!< PORT4 OMR: PR5 Mask                     */\r
+#define PORT4_OMR_PR6_Pos                     22                                                      /*!< PORT4 OMR: PR6 Position                 */\r
+#define PORT4_OMR_PR6_Msk                     (0x01UL << PORT4_OMR_PR6_Pos)                           /*!< PORT4 OMR: PR6 Mask                     */\r
+#define PORT4_OMR_PR7_Pos                     23                                                      /*!< PORT4 OMR: PR7 Position                 */\r
+#define PORT4_OMR_PR7_Msk                     (0x01UL << PORT4_OMR_PR7_Pos)                           /*!< PORT4 OMR: PR7 Mask                     */\r
+#define PORT4_OMR_PR8_Pos                     24                                                      /*!< PORT4 OMR: PR8 Position                 */\r
+#define PORT4_OMR_PR8_Msk                     (0x01UL << PORT4_OMR_PR8_Pos)                           /*!< PORT4 OMR: PR8 Mask                     */\r
+#define PORT4_OMR_PR9_Pos                     25                                                      /*!< PORT4 OMR: PR9 Position                 */\r
+#define PORT4_OMR_PR9_Msk                     (0x01UL << PORT4_OMR_PR9_Pos)                           /*!< PORT4 OMR: PR9 Mask                     */\r
+#define PORT4_OMR_PR10_Pos                    26                                                      /*!< PORT4 OMR: PR10 Position                */\r
+#define PORT4_OMR_PR10_Msk                    (0x01UL << PORT4_OMR_PR10_Pos)                          /*!< PORT4 OMR: PR10 Mask                    */\r
+#define PORT4_OMR_PR11_Pos                    27                                                      /*!< PORT4 OMR: PR11 Position                */\r
+#define PORT4_OMR_PR11_Msk                    (0x01UL << PORT4_OMR_PR11_Pos)                          /*!< PORT4 OMR: PR11 Mask                    */\r
+#define PORT4_OMR_PR12_Pos                    28                                                      /*!< PORT4 OMR: PR12 Position                */\r
+#define PORT4_OMR_PR12_Msk                    (0x01UL << PORT4_OMR_PR12_Pos)                          /*!< PORT4 OMR: PR12 Mask                    */\r
+#define PORT4_OMR_PR13_Pos                    29                                                      /*!< PORT4 OMR: PR13 Position                */\r
+#define PORT4_OMR_PR13_Msk                    (0x01UL << PORT4_OMR_PR13_Pos)                          /*!< PORT4 OMR: PR13 Mask                    */\r
+#define PORT4_OMR_PR14_Pos                    30                                                      /*!< PORT4 OMR: PR14 Position                */\r
+#define PORT4_OMR_PR14_Msk                    (0x01UL << PORT4_OMR_PR14_Pos)                          /*!< PORT4 OMR: PR14 Mask                    */\r
+#define PORT4_OMR_PR15_Pos                    31                                                      /*!< PORT4 OMR: PR15 Position                */\r
+#define PORT4_OMR_PR15_Msk                    (0x01UL << PORT4_OMR_PR15_Pos)                          /*!< PORT4 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT4_IOCR0  -------------------------------- */\r
+#define PORT4_IOCR0_PC0_Pos                   3                                                       /*!< PORT4 IOCR0: PC0 Position               */\r
+#define PORT4_IOCR0_PC0_Msk                   (0x1fUL << PORT4_IOCR0_PC0_Pos)                         /*!< PORT4 IOCR0: PC0 Mask                   */\r
+#define PORT4_IOCR0_PC1_Pos                   11                                                      /*!< PORT4 IOCR0: PC1 Position               */\r
+#define PORT4_IOCR0_PC1_Msk                   (0x1fUL << PORT4_IOCR0_PC1_Pos)                         /*!< PORT4 IOCR0: PC1 Mask                   */\r
+#define PORT4_IOCR0_PC2_Pos                   19                                                      /*!< PORT4 IOCR0: PC2 Position               */\r
+#define PORT4_IOCR0_PC2_Msk                   (0x1fUL << PORT4_IOCR0_PC2_Pos)                         /*!< PORT4 IOCR0: PC2 Mask                   */\r
+#define PORT4_IOCR0_PC3_Pos                   27                                                      /*!< PORT4 IOCR0: PC3 Position               */\r
+#define PORT4_IOCR0_PC3_Msk                   (0x1fUL << PORT4_IOCR0_PC3_Pos)                         /*!< PORT4 IOCR0: PC3 Mask                   */\r
+\r
+/* ----------------------------------  PORT4_IN  ---------------------------------- */\r
+#define PORT4_IN_P0_Pos                       0                                                       /*!< PORT4 IN: P0 Position                   */\r
+#define PORT4_IN_P0_Msk                       (0x01UL << PORT4_IN_P0_Pos)                             /*!< PORT4 IN: P0 Mask                       */\r
+#define PORT4_IN_P1_Pos                       1                                                       /*!< PORT4 IN: P1 Position                   */\r
+#define PORT4_IN_P1_Msk                       (0x01UL << PORT4_IN_P1_Pos)                             /*!< PORT4 IN: P1 Mask                       */\r
+#define PORT4_IN_P2_Pos                       2                                                       /*!< PORT4 IN: P2 Position                   */\r
+#define PORT4_IN_P2_Msk                       (0x01UL << PORT4_IN_P2_Pos)                             /*!< PORT4 IN: P2 Mask                       */\r
+#define PORT4_IN_P3_Pos                       3                                                       /*!< PORT4 IN: P3 Position                   */\r
+#define PORT4_IN_P3_Msk                       (0x01UL << PORT4_IN_P3_Pos)                             /*!< PORT4 IN: P3 Mask                       */\r
+#define PORT4_IN_P4_Pos                       4                                                       /*!< PORT4 IN: P4 Position                   */\r
+#define PORT4_IN_P4_Msk                       (0x01UL << PORT4_IN_P4_Pos)                             /*!< PORT4 IN: P4 Mask                       */\r
+#define PORT4_IN_P5_Pos                       5                                                       /*!< PORT4 IN: P5 Position                   */\r
+#define PORT4_IN_P5_Msk                       (0x01UL << PORT4_IN_P5_Pos)                             /*!< PORT4 IN: P5 Mask                       */\r
+#define PORT4_IN_P6_Pos                       6                                                       /*!< PORT4 IN: P6 Position                   */\r
+#define PORT4_IN_P6_Msk                       (0x01UL << PORT4_IN_P6_Pos)                             /*!< PORT4 IN: P6 Mask                       */\r
+#define PORT4_IN_P7_Pos                       7                                                       /*!< PORT4 IN: P7 Position                   */\r
+#define PORT4_IN_P7_Msk                       (0x01UL << PORT4_IN_P7_Pos)                             /*!< PORT4 IN: P7 Mask                       */\r
+#define PORT4_IN_P8_Pos                       8                                                       /*!< PORT4 IN: P8 Position                   */\r
+#define PORT4_IN_P8_Msk                       (0x01UL << PORT4_IN_P8_Pos)                             /*!< PORT4 IN: P8 Mask                       */\r
+#define PORT4_IN_P9_Pos                       9                                                       /*!< PORT4 IN: P9 Position                   */\r
+#define PORT4_IN_P9_Msk                       (0x01UL << PORT4_IN_P9_Pos)                             /*!< PORT4 IN: P9 Mask                       */\r
+#define PORT4_IN_P10_Pos                      10                                                      /*!< PORT4 IN: P10 Position                  */\r
+#define PORT4_IN_P10_Msk                      (0x01UL << PORT4_IN_P10_Pos)                            /*!< PORT4 IN: P10 Mask                      */\r
+#define PORT4_IN_P11_Pos                      11                                                      /*!< PORT4 IN: P11 Position                  */\r
+#define PORT4_IN_P11_Msk                      (0x01UL << PORT4_IN_P11_Pos)                            /*!< PORT4 IN: P11 Mask                      */\r
+#define PORT4_IN_P12_Pos                      12                                                      /*!< PORT4 IN: P12 Position                  */\r
+#define PORT4_IN_P12_Msk                      (0x01UL << PORT4_IN_P12_Pos)                            /*!< PORT4 IN: P12 Mask                      */\r
+#define PORT4_IN_P13_Pos                      13                                                      /*!< PORT4 IN: P13 Position                  */\r
+#define PORT4_IN_P13_Msk                      (0x01UL << PORT4_IN_P13_Pos)                            /*!< PORT4 IN: P13 Mask                      */\r
+#define PORT4_IN_P14_Pos                      14                                                      /*!< PORT4 IN: P14 Position                  */\r
+#define PORT4_IN_P14_Msk                      (0x01UL << PORT4_IN_P14_Pos)                            /*!< PORT4 IN: P14 Mask                      */\r
+#define PORT4_IN_P15_Pos                      15                                                      /*!< PORT4 IN: P15 Position                  */\r
+#define PORT4_IN_P15_Msk                      (0x01UL << PORT4_IN_P15_Pos)                            /*!< PORT4 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT4_PDR0  --------------------------------- */\r
+#define PORT4_PDR0_PD0_Pos                    0                                                       /*!< PORT4 PDR0: PD0 Position                */\r
+#define PORT4_PDR0_PD0_Msk                    (0x07UL << PORT4_PDR0_PD0_Pos)                          /*!< PORT4 PDR0: PD0 Mask                    */\r
+#define PORT4_PDR0_PD1_Pos                    4                                                       /*!< PORT4 PDR0: PD1 Position                */\r
+#define PORT4_PDR0_PD1_Msk                    (0x07UL << PORT4_PDR0_PD1_Pos)                          /*!< PORT4 PDR0: PD1 Mask                    */\r
+#define PORT4_PDR0_PD2_Pos                    8                                                       /*!< PORT4 PDR0: PD2 Position                */\r
+#define PORT4_PDR0_PD2_Msk                    (0x07UL << PORT4_PDR0_PD2_Pos)                          /*!< PORT4 PDR0: PD2 Mask                    */\r
+#define PORT4_PDR0_PD3_Pos                    12                                                      /*!< PORT4 PDR0: PD3 Position                */\r
+#define PORT4_PDR0_PD3_Msk                    (0x07UL << PORT4_PDR0_PD3_Pos)                          /*!< PORT4 PDR0: PD3 Mask                    */\r
+#define PORT4_PDR0_PD4_Pos                    16                                                      /*!< PORT4 PDR0: PD4 Position                */\r
+#define PORT4_PDR0_PD4_Msk                    (0x07UL << PORT4_PDR0_PD4_Pos)                          /*!< PORT4 PDR0: PD4 Mask                    */\r
+#define PORT4_PDR0_PD5_Pos                    20                                                      /*!< PORT4 PDR0: PD5 Position                */\r
+#define PORT4_PDR0_PD5_Msk                    (0x07UL << PORT4_PDR0_PD5_Pos)                          /*!< PORT4 PDR0: PD5 Mask                    */\r
+#define PORT4_PDR0_PD6_Pos                    24                                                      /*!< PORT4 PDR0: PD6 Position                */\r
+#define PORT4_PDR0_PD6_Msk                    (0x07UL << PORT4_PDR0_PD6_Pos)                          /*!< PORT4 PDR0: PD6 Mask                    */\r
+#define PORT4_PDR0_PD7_Pos                    28                                                      /*!< PORT4 PDR0: PD7 Position                */\r
+#define PORT4_PDR0_PD7_Msk                    (0x07UL << PORT4_PDR0_PD7_Pos)                          /*!< PORT4 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT4_PDISC  -------------------------------- */\r
+#define PORT4_PDISC_PDIS0_Pos                 0                                                       /*!< PORT4 PDISC: PDIS0 Position             */\r
+#define PORT4_PDISC_PDIS0_Msk                 (0x01UL << PORT4_PDISC_PDIS0_Pos)                       /*!< PORT4 PDISC: PDIS0 Mask                 */\r
+#define PORT4_PDISC_PDIS1_Pos                 1                                                       /*!< PORT4 PDISC: PDIS1 Position             */\r
+#define PORT4_PDISC_PDIS1_Msk                 (0x01UL << PORT4_PDISC_PDIS1_Pos)                       /*!< PORT4 PDISC: PDIS1 Mask                 */\r
+#define PORT4_PDISC_PDIS2_Pos                 2                                                       /*!< PORT4 PDISC: PDIS2 Position             */\r
+#define PORT4_PDISC_PDIS2_Msk                 (0x01UL << PORT4_PDISC_PDIS2_Pos)                       /*!< PORT4 PDISC: PDIS2 Mask                 */\r
+#define PORT4_PDISC_PDIS3_Pos                 3                                                       /*!< PORT4 PDISC: PDIS3 Position             */\r
+#define PORT4_PDISC_PDIS3_Msk                 (0x01UL << PORT4_PDISC_PDIS3_Pos)                       /*!< PORT4 PDISC: PDIS3 Mask                 */\r
+#define PORT4_PDISC_PDIS4_Pos                 4                                                       /*!< PORT4 PDISC: PDIS4 Position             */\r
+#define PORT4_PDISC_PDIS4_Msk                 (0x01UL << PORT4_PDISC_PDIS4_Pos)                       /*!< PORT4 PDISC: PDIS4 Mask                 */\r
+#define PORT4_PDISC_PDIS5_Pos                 5                                                       /*!< PORT4 PDISC: PDIS5 Position             */\r
+#define PORT4_PDISC_PDIS5_Msk                 (0x01UL << PORT4_PDISC_PDIS5_Pos)                       /*!< PORT4 PDISC: PDIS5 Mask                 */\r
+#define PORT4_PDISC_PDIS6_Pos                 6                                                       /*!< PORT4 PDISC: PDIS6 Position             */\r
+#define PORT4_PDISC_PDIS6_Msk                 (0x01UL << PORT4_PDISC_PDIS6_Pos)                       /*!< PORT4 PDISC: PDIS6 Mask                 */\r
+#define PORT4_PDISC_PDIS7_Pos                 7                                                       /*!< PORT4 PDISC: PDIS7 Position             */\r
+#define PORT4_PDISC_PDIS7_Msk                 (0x01UL << PORT4_PDISC_PDIS7_Pos)                       /*!< PORT4 PDISC: PDIS7 Mask                 */\r
+#define PORT4_PDISC_PDIS8_Pos                 8                                                       /*!< PORT4 PDISC: PDIS8 Position             */\r
+#define PORT4_PDISC_PDIS8_Msk                 (0x01UL << PORT4_PDISC_PDIS8_Pos)                       /*!< PORT4 PDISC: PDIS8 Mask                 */\r
+#define PORT4_PDISC_PDIS9_Pos                 9                                                       /*!< PORT4 PDISC: PDIS9 Position             */\r
+#define PORT4_PDISC_PDIS9_Msk                 (0x01UL << PORT4_PDISC_PDIS9_Pos)                       /*!< PORT4 PDISC: PDIS9 Mask                 */\r
+#define PORT4_PDISC_PDIS10_Pos                10                                                      /*!< PORT4 PDISC: PDIS10 Position            */\r
+#define PORT4_PDISC_PDIS10_Msk                (0x01UL << PORT4_PDISC_PDIS10_Pos)                      /*!< PORT4 PDISC: PDIS10 Mask                */\r
+#define PORT4_PDISC_PDIS11_Pos                11                                                      /*!< PORT4 PDISC: PDIS11 Position            */\r
+#define PORT4_PDISC_PDIS11_Msk                (0x01UL << PORT4_PDISC_PDIS11_Pos)                      /*!< PORT4 PDISC: PDIS11 Mask                */\r
+#define PORT4_PDISC_PDIS12_Pos                12                                                      /*!< PORT4 PDISC: PDIS12 Position            */\r
+#define PORT4_PDISC_PDIS12_Msk                (0x01UL << PORT4_PDISC_PDIS12_Pos)                      /*!< PORT4 PDISC: PDIS12 Mask                */\r
+#define PORT4_PDISC_PDIS13_Pos                13                                                      /*!< PORT4 PDISC: PDIS13 Position            */\r
+#define PORT4_PDISC_PDIS13_Msk                (0x01UL << PORT4_PDISC_PDIS13_Pos)                      /*!< PORT4 PDISC: PDIS13 Mask                */\r
+#define PORT4_PDISC_PDIS14_Pos                14                                                      /*!< PORT4 PDISC: PDIS14 Position            */\r
+#define PORT4_PDISC_PDIS14_Msk                (0x01UL << PORT4_PDISC_PDIS14_Pos)                      /*!< PORT4 PDISC: PDIS14 Mask                */\r
+#define PORT4_PDISC_PDIS15_Pos                15                                                      /*!< PORT4 PDISC: PDIS15 Position            */\r
+#define PORT4_PDISC_PDIS15_Msk                (0x01UL << PORT4_PDISC_PDIS15_Pos)                      /*!< PORT4 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT4_PPS  --------------------------------- */\r
+#define PORT4_PPS_PPS0_Pos                    0                                                       /*!< PORT4 PPS: PPS0 Position                */\r
+#define PORT4_PPS_PPS0_Msk                    (0x01UL << PORT4_PPS_PPS0_Pos)                          /*!< PORT4 PPS: PPS0 Mask                    */\r
+#define PORT4_PPS_PPS1_Pos                    1                                                       /*!< PORT4 PPS: PPS1 Position                */\r
+#define PORT4_PPS_PPS1_Msk                    (0x01UL << PORT4_PPS_PPS1_Pos)                          /*!< PORT4 PPS: PPS1 Mask                    */\r
+#define PORT4_PPS_PPS2_Pos                    2                                                       /*!< PORT4 PPS: PPS2 Position                */\r
+#define PORT4_PPS_PPS2_Msk                    (0x01UL << PORT4_PPS_PPS2_Pos)                          /*!< PORT4 PPS: PPS2 Mask                    */\r
+#define PORT4_PPS_PPS3_Pos                    3                                                       /*!< PORT4 PPS: PPS3 Position                */\r
+#define PORT4_PPS_PPS3_Msk                    (0x01UL << PORT4_PPS_PPS3_Pos)                          /*!< PORT4 PPS: PPS3 Mask                    */\r
+#define PORT4_PPS_PPS4_Pos                    4                                                       /*!< PORT4 PPS: PPS4 Position                */\r
+#define PORT4_PPS_PPS4_Msk                    (0x01UL << PORT4_PPS_PPS4_Pos)                          /*!< PORT4 PPS: PPS4 Mask                    */\r
+#define PORT4_PPS_PPS5_Pos                    5                                                       /*!< PORT4 PPS: PPS5 Position                */\r
+#define PORT4_PPS_PPS5_Msk                    (0x01UL << PORT4_PPS_PPS5_Pos)                          /*!< PORT4 PPS: PPS5 Mask                    */\r
+#define PORT4_PPS_PPS6_Pos                    6                                                       /*!< PORT4 PPS: PPS6 Position                */\r
+#define PORT4_PPS_PPS6_Msk                    (0x01UL << PORT4_PPS_PPS6_Pos)                          /*!< PORT4 PPS: PPS6 Mask                    */\r
+#define PORT4_PPS_PPS7_Pos                    7                                                       /*!< PORT4 PPS: PPS7 Position                */\r
+#define PORT4_PPS_PPS7_Msk                    (0x01UL << PORT4_PPS_PPS7_Pos)                          /*!< PORT4 PPS: PPS7 Mask                    */\r
+#define PORT4_PPS_PPS8_Pos                    8                                                       /*!< PORT4 PPS: PPS8 Position                */\r
+#define PORT4_PPS_PPS8_Msk                    (0x01UL << PORT4_PPS_PPS8_Pos)                          /*!< PORT4 PPS: PPS8 Mask                    */\r
+#define PORT4_PPS_PPS9_Pos                    9                                                       /*!< PORT4 PPS: PPS9 Position                */\r
+#define PORT4_PPS_PPS9_Msk                    (0x01UL << PORT4_PPS_PPS9_Pos)                          /*!< PORT4 PPS: PPS9 Mask                    */\r
+#define PORT4_PPS_PPS10_Pos                   10                                                      /*!< PORT4 PPS: PPS10 Position               */\r
+#define PORT4_PPS_PPS10_Msk                   (0x01UL << PORT4_PPS_PPS10_Pos)                         /*!< PORT4 PPS: PPS10 Mask                   */\r
+#define PORT4_PPS_PPS11_Pos                   11                                                      /*!< PORT4 PPS: PPS11 Position               */\r
+#define PORT4_PPS_PPS11_Msk                   (0x01UL << PORT4_PPS_PPS11_Pos)                         /*!< PORT4 PPS: PPS11 Mask                   */\r
+#define PORT4_PPS_PPS12_Pos                   12                                                      /*!< PORT4 PPS: PPS12 Position               */\r
+#define PORT4_PPS_PPS12_Msk                   (0x01UL << PORT4_PPS_PPS12_Pos)                         /*!< PORT4 PPS: PPS12 Mask                   */\r
+#define PORT4_PPS_PPS13_Pos                   13                                                      /*!< PORT4 PPS: PPS13 Position               */\r
+#define PORT4_PPS_PPS13_Msk                   (0x01UL << PORT4_PPS_PPS13_Pos)                         /*!< PORT4 PPS: PPS13 Mask                   */\r
+#define PORT4_PPS_PPS14_Pos                   14                                                      /*!< PORT4 PPS: PPS14 Position               */\r
+#define PORT4_PPS_PPS14_Msk                   (0x01UL << PORT4_PPS_PPS14_Pos)                         /*!< PORT4 PPS: PPS14 Mask                   */\r
+#define PORT4_PPS_PPS15_Pos                   15                                                      /*!< PORT4 PPS: PPS15 Position               */\r
+#define PORT4_PPS_PPS15_Msk                   (0x01UL << PORT4_PPS_PPS15_Pos)                         /*!< PORT4 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT4_HWSEL  -------------------------------- */\r
+#define PORT4_HWSEL_HW0_Pos                   0                                                       /*!< PORT4 HWSEL: HW0 Position               */\r
+#define PORT4_HWSEL_HW0_Msk                   (0x03UL << PORT4_HWSEL_HW0_Pos)                         /*!< PORT4 HWSEL: HW0 Mask                   */\r
+#define PORT4_HWSEL_HW1_Pos                   2                                                       /*!< PORT4 HWSEL: HW1 Position               */\r
+#define PORT4_HWSEL_HW1_Msk                   (0x03UL << PORT4_HWSEL_HW1_Pos)                         /*!< PORT4 HWSEL: HW1 Mask                   */\r
+#define PORT4_HWSEL_HW2_Pos                   4                                                       /*!< PORT4 HWSEL: HW2 Position               */\r
+#define PORT4_HWSEL_HW2_Msk                   (0x03UL << PORT4_HWSEL_HW2_Pos)                         /*!< PORT4 HWSEL: HW2 Mask                   */\r
+#define PORT4_HWSEL_HW3_Pos                   6                                                       /*!< PORT4 HWSEL: HW3 Position               */\r
+#define PORT4_HWSEL_HW3_Msk                   (0x03UL << PORT4_HWSEL_HW3_Pos)                         /*!< PORT4 HWSEL: HW3 Mask                   */\r
+#define PORT4_HWSEL_HW4_Pos                   8                                                       /*!< PORT4 HWSEL: HW4 Position               */\r
+#define PORT4_HWSEL_HW4_Msk                   (0x03UL << PORT4_HWSEL_HW4_Pos)                         /*!< PORT4 HWSEL: HW4 Mask                   */\r
+#define PORT4_HWSEL_HW5_Pos                   10                                                      /*!< PORT4 HWSEL: HW5 Position               */\r
+#define PORT4_HWSEL_HW5_Msk                   (0x03UL << PORT4_HWSEL_HW5_Pos)                         /*!< PORT4 HWSEL: HW5 Mask                   */\r
+#define PORT4_HWSEL_HW6_Pos                   12                                                      /*!< PORT4 HWSEL: HW6 Position               */\r
+#define PORT4_HWSEL_HW6_Msk                   (0x03UL << PORT4_HWSEL_HW6_Pos)                         /*!< PORT4 HWSEL: HW6 Mask                   */\r
+#define PORT4_HWSEL_HW7_Pos                   14                                                      /*!< PORT4 HWSEL: HW7 Position               */\r
+#define PORT4_HWSEL_HW7_Msk                   (0x03UL << PORT4_HWSEL_HW7_Pos)                         /*!< PORT4 HWSEL: HW7 Mask                   */\r
+#define PORT4_HWSEL_HW8_Pos                   16                                                      /*!< PORT4 HWSEL: HW8 Position               */\r
+#define PORT4_HWSEL_HW8_Msk                   (0x03UL << PORT4_HWSEL_HW8_Pos)                         /*!< PORT4 HWSEL: HW8 Mask                   */\r
+#define PORT4_HWSEL_HW9_Pos                   18                                                      /*!< PORT4 HWSEL: HW9 Position               */\r
+#define PORT4_HWSEL_HW9_Msk                   (0x03UL << PORT4_HWSEL_HW9_Pos)                         /*!< PORT4 HWSEL: HW9 Mask                   */\r
+#define PORT4_HWSEL_HW10_Pos                  20                                                      /*!< PORT4 HWSEL: HW10 Position              */\r
+#define PORT4_HWSEL_HW10_Msk                  (0x03UL << PORT4_HWSEL_HW10_Pos)                        /*!< PORT4 HWSEL: HW10 Mask                  */\r
+#define PORT4_HWSEL_HW11_Pos                  22                                                      /*!< PORT4 HWSEL: HW11 Position              */\r
+#define PORT4_HWSEL_HW11_Msk                  (0x03UL << PORT4_HWSEL_HW11_Pos)                        /*!< PORT4 HWSEL: HW11 Mask                  */\r
+#define PORT4_HWSEL_HW12_Pos                  24                                                      /*!< PORT4 HWSEL: HW12 Position              */\r
+#define PORT4_HWSEL_HW12_Msk                  (0x03UL << PORT4_HWSEL_HW12_Pos)                        /*!< PORT4 HWSEL: HW12 Mask                  */\r
+#define PORT4_HWSEL_HW13_Pos                  26                                                      /*!< PORT4 HWSEL: HW13 Position              */\r
+#define PORT4_HWSEL_HW13_Msk                  (0x03UL << PORT4_HWSEL_HW13_Pos)                        /*!< PORT4 HWSEL: HW13 Mask                  */\r
+#define PORT4_HWSEL_HW14_Pos                  28                                                      /*!< PORT4 HWSEL: HW14 Position              */\r
+#define PORT4_HWSEL_HW14_Msk                  (0x03UL << PORT4_HWSEL_HW14_Pos)                        /*!< PORT4 HWSEL: HW14 Mask                  */\r
+#define PORT4_HWSEL_HW15_Pos                  30                                                      /*!< PORT4 HWSEL: HW15 Position              */\r
+#define PORT4_HWSEL_HW15_Msk                  (0x03UL << PORT4_HWSEL_HW15_Pos)                        /*!< PORT4 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT5' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT5_OUT  --------------------------------- */\r
+#define PORT5_OUT_P0_Pos                      0                                                       /*!< PORT5 OUT: P0 Position                  */\r
+#define PORT5_OUT_P0_Msk                      (0x01UL << PORT5_OUT_P0_Pos)                            /*!< PORT5 OUT: P0 Mask                      */\r
+#define PORT5_OUT_P1_Pos                      1                                                       /*!< PORT5 OUT: P1 Position                  */\r
+#define PORT5_OUT_P1_Msk                      (0x01UL << PORT5_OUT_P1_Pos)                            /*!< PORT5 OUT: P1 Mask                      */\r
+#define PORT5_OUT_P2_Pos                      2                                                       /*!< PORT5 OUT: P2 Position                  */\r
+#define PORT5_OUT_P2_Msk                      (0x01UL << PORT5_OUT_P2_Pos)                            /*!< PORT5 OUT: P2 Mask                      */\r
+#define PORT5_OUT_P3_Pos                      3                                                       /*!< PORT5 OUT: P3 Position                  */\r
+#define PORT5_OUT_P3_Msk                      (0x01UL << PORT5_OUT_P3_Pos)                            /*!< PORT5 OUT: P3 Mask                      */\r
+#define PORT5_OUT_P4_Pos                      4                                                       /*!< PORT5 OUT: P4 Position                  */\r
+#define PORT5_OUT_P4_Msk                      (0x01UL << PORT5_OUT_P4_Pos)                            /*!< PORT5 OUT: P4 Mask                      */\r
+#define PORT5_OUT_P5_Pos                      5                                                       /*!< PORT5 OUT: P5 Position                  */\r
+#define PORT5_OUT_P5_Msk                      (0x01UL << PORT5_OUT_P5_Pos)                            /*!< PORT5 OUT: P5 Mask                      */\r
+#define PORT5_OUT_P6_Pos                      6                                                       /*!< PORT5 OUT: P6 Position                  */\r
+#define PORT5_OUT_P6_Msk                      (0x01UL << PORT5_OUT_P6_Pos)                            /*!< PORT5 OUT: P6 Mask                      */\r
+#define PORT5_OUT_P7_Pos                      7                                                       /*!< PORT5 OUT: P7 Position                  */\r
+#define PORT5_OUT_P7_Msk                      (0x01UL << PORT5_OUT_P7_Pos)                            /*!< PORT5 OUT: P7 Mask                      */\r
+#define PORT5_OUT_P8_Pos                      8                                                       /*!< PORT5 OUT: P8 Position                  */\r
+#define PORT5_OUT_P8_Msk                      (0x01UL << PORT5_OUT_P8_Pos)                            /*!< PORT5 OUT: P8 Mask                      */\r
+#define PORT5_OUT_P9_Pos                      9                                                       /*!< PORT5 OUT: P9 Position                  */\r
+#define PORT5_OUT_P9_Msk                      (0x01UL << PORT5_OUT_P9_Pos)                            /*!< PORT5 OUT: P9 Mask                      */\r
+#define PORT5_OUT_P10_Pos                     10                                                      /*!< PORT5 OUT: P10 Position                 */\r
+#define PORT5_OUT_P10_Msk                     (0x01UL << PORT5_OUT_P10_Pos)                           /*!< PORT5 OUT: P10 Mask                     */\r
+#define PORT5_OUT_P11_Pos                     11                                                      /*!< PORT5 OUT: P11 Position                 */\r
+#define PORT5_OUT_P11_Msk                     (0x01UL << PORT5_OUT_P11_Pos)                           /*!< PORT5 OUT: P11 Mask                     */\r
+#define PORT5_OUT_P12_Pos                     12                                                      /*!< PORT5 OUT: P12 Position                 */\r
+#define PORT5_OUT_P12_Msk                     (0x01UL << PORT5_OUT_P12_Pos)                           /*!< PORT5 OUT: P12 Mask                     */\r
+#define PORT5_OUT_P13_Pos                     13                                                      /*!< PORT5 OUT: P13 Position                 */\r
+#define PORT5_OUT_P13_Msk                     (0x01UL << PORT5_OUT_P13_Pos)                           /*!< PORT5 OUT: P13 Mask                     */\r
+#define PORT5_OUT_P14_Pos                     14                                                      /*!< PORT5 OUT: P14 Position                 */\r
+#define PORT5_OUT_P14_Msk                     (0x01UL << PORT5_OUT_P14_Pos)                           /*!< PORT5 OUT: P14 Mask                     */\r
+#define PORT5_OUT_P15_Pos                     15                                                      /*!< PORT5 OUT: P15 Position                 */\r
+#define PORT5_OUT_P15_Msk                     (0x01UL << PORT5_OUT_P15_Pos)                           /*!< PORT5 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT5_OMR  --------------------------------- */\r
+#define PORT5_OMR_PS0_Pos                     0                                                       /*!< PORT5 OMR: PS0 Position                 */\r
+#define PORT5_OMR_PS0_Msk                     (0x01UL << PORT5_OMR_PS0_Pos)                           /*!< PORT5 OMR: PS0 Mask                     */\r
+#define PORT5_OMR_PS1_Pos                     1                                                       /*!< PORT5 OMR: PS1 Position                 */\r
+#define PORT5_OMR_PS1_Msk                     (0x01UL << PORT5_OMR_PS1_Pos)                           /*!< PORT5 OMR: PS1 Mask                     */\r
+#define PORT5_OMR_PS2_Pos                     2                                                       /*!< PORT5 OMR: PS2 Position                 */\r
+#define PORT5_OMR_PS2_Msk                     (0x01UL << PORT5_OMR_PS2_Pos)                           /*!< PORT5 OMR: PS2 Mask                     */\r
+#define PORT5_OMR_PS3_Pos                     3                                                       /*!< PORT5 OMR: PS3 Position                 */\r
+#define PORT5_OMR_PS3_Msk                     (0x01UL << PORT5_OMR_PS3_Pos)                           /*!< PORT5 OMR: PS3 Mask                     */\r
+#define PORT5_OMR_PS4_Pos                     4                                                       /*!< PORT5 OMR: PS4 Position                 */\r
+#define PORT5_OMR_PS4_Msk                     (0x01UL << PORT5_OMR_PS4_Pos)                           /*!< PORT5 OMR: PS4 Mask                     */\r
+#define PORT5_OMR_PS5_Pos                     5                                                       /*!< PORT5 OMR: PS5 Position                 */\r
+#define PORT5_OMR_PS5_Msk                     (0x01UL << PORT5_OMR_PS5_Pos)                           /*!< PORT5 OMR: PS5 Mask                     */\r
+#define PORT5_OMR_PS6_Pos                     6                                                       /*!< PORT5 OMR: PS6 Position                 */\r
+#define PORT5_OMR_PS6_Msk                     (0x01UL << PORT5_OMR_PS6_Pos)                           /*!< PORT5 OMR: PS6 Mask                     */\r
+#define PORT5_OMR_PS7_Pos                     7                                                       /*!< PORT5 OMR: PS7 Position                 */\r
+#define PORT5_OMR_PS7_Msk                     (0x01UL << PORT5_OMR_PS7_Pos)                           /*!< PORT5 OMR: PS7 Mask                     */\r
+#define PORT5_OMR_PS8_Pos                     8                                                       /*!< PORT5 OMR: PS8 Position                 */\r
+#define PORT5_OMR_PS8_Msk                     (0x01UL << PORT5_OMR_PS8_Pos)                           /*!< PORT5 OMR: PS8 Mask                     */\r
+#define PORT5_OMR_PS9_Pos                     9                                                       /*!< PORT5 OMR: PS9 Position                 */\r
+#define PORT5_OMR_PS9_Msk                     (0x01UL << PORT5_OMR_PS9_Pos)                           /*!< PORT5 OMR: PS9 Mask                     */\r
+#define PORT5_OMR_PS10_Pos                    10                                                      /*!< PORT5 OMR: PS10 Position                */\r
+#define PORT5_OMR_PS10_Msk                    (0x01UL << PORT5_OMR_PS10_Pos)                          /*!< PORT5 OMR: PS10 Mask                    */\r
+#define PORT5_OMR_PS11_Pos                    11                                                      /*!< PORT5 OMR: PS11 Position                */\r
+#define PORT5_OMR_PS11_Msk                    (0x01UL << PORT5_OMR_PS11_Pos)                          /*!< PORT5 OMR: PS11 Mask                    */\r
+#define PORT5_OMR_PS12_Pos                    12                                                      /*!< PORT5 OMR: PS12 Position                */\r
+#define PORT5_OMR_PS12_Msk                    (0x01UL << PORT5_OMR_PS12_Pos)                          /*!< PORT5 OMR: PS12 Mask                    */\r
+#define PORT5_OMR_PS13_Pos                    13                                                      /*!< PORT5 OMR: PS13 Position                */\r
+#define PORT5_OMR_PS13_Msk                    (0x01UL << PORT5_OMR_PS13_Pos)                          /*!< PORT5 OMR: PS13 Mask                    */\r
+#define PORT5_OMR_PS14_Pos                    14                                                      /*!< PORT5 OMR: PS14 Position                */\r
+#define PORT5_OMR_PS14_Msk                    (0x01UL << PORT5_OMR_PS14_Pos)                          /*!< PORT5 OMR: PS14 Mask                    */\r
+#define PORT5_OMR_PS15_Pos                    15                                                      /*!< PORT5 OMR: PS15 Position                */\r
+#define PORT5_OMR_PS15_Msk                    (0x01UL << PORT5_OMR_PS15_Pos)                          /*!< PORT5 OMR: PS15 Mask                    */\r
+#define PORT5_OMR_PR0_Pos                     16                                                      /*!< PORT5 OMR: PR0 Position                 */\r
+#define PORT5_OMR_PR0_Msk                     (0x01UL << PORT5_OMR_PR0_Pos)                           /*!< PORT5 OMR: PR0 Mask                     */\r
+#define PORT5_OMR_PR1_Pos                     17                                                      /*!< PORT5 OMR: PR1 Position                 */\r
+#define PORT5_OMR_PR1_Msk                     (0x01UL << PORT5_OMR_PR1_Pos)                           /*!< PORT5 OMR: PR1 Mask                     */\r
+#define PORT5_OMR_PR2_Pos                     18                                                      /*!< PORT5 OMR: PR2 Position                 */\r
+#define PORT5_OMR_PR2_Msk                     (0x01UL << PORT5_OMR_PR2_Pos)                           /*!< PORT5 OMR: PR2 Mask                     */\r
+#define PORT5_OMR_PR3_Pos                     19                                                      /*!< PORT5 OMR: PR3 Position                 */\r
+#define PORT5_OMR_PR3_Msk                     (0x01UL << PORT5_OMR_PR3_Pos)                           /*!< PORT5 OMR: PR3 Mask                     */\r
+#define PORT5_OMR_PR4_Pos                     20                                                      /*!< PORT5 OMR: PR4 Position                 */\r
+#define PORT5_OMR_PR4_Msk                     (0x01UL << PORT5_OMR_PR4_Pos)                           /*!< PORT5 OMR: PR4 Mask                     */\r
+#define PORT5_OMR_PR5_Pos                     21                                                      /*!< PORT5 OMR: PR5 Position                 */\r
+#define PORT5_OMR_PR5_Msk                     (0x01UL << PORT5_OMR_PR5_Pos)                           /*!< PORT5 OMR: PR5 Mask                     */\r
+#define PORT5_OMR_PR6_Pos                     22                                                      /*!< PORT5 OMR: PR6 Position                 */\r
+#define PORT5_OMR_PR6_Msk                     (0x01UL << PORT5_OMR_PR6_Pos)                           /*!< PORT5 OMR: PR6 Mask                     */\r
+#define PORT5_OMR_PR7_Pos                     23                                                      /*!< PORT5 OMR: PR7 Position                 */\r
+#define PORT5_OMR_PR7_Msk                     (0x01UL << PORT5_OMR_PR7_Pos)                           /*!< PORT5 OMR: PR7 Mask                     */\r
+#define PORT5_OMR_PR8_Pos                     24                                                      /*!< PORT5 OMR: PR8 Position                 */\r
+#define PORT5_OMR_PR8_Msk                     (0x01UL << PORT5_OMR_PR8_Pos)                           /*!< PORT5 OMR: PR8 Mask                     */\r
+#define PORT5_OMR_PR9_Pos                     25                                                      /*!< PORT5 OMR: PR9 Position                 */\r
+#define PORT5_OMR_PR9_Msk                     (0x01UL << PORT5_OMR_PR9_Pos)                           /*!< PORT5 OMR: PR9 Mask                     */\r
+#define PORT5_OMR_PR10_Pos                    26                                                      /*!< PORT5 OMR: PR10 Position                */\r
+#define PORT5_OMR_PR10_Msk                    (0x01UL << PORT5_OMR_PR10_Pos)                          /*!< PORT5 OMR: PR10 Mask                    */\r
+#define PORT5_OMR_PR11_Pos                    27                                                      /*!< PORT5 OMR: PR11 Position                */\r
+#define PORT5_OMR_PR11_Msk                    (0x01UL << PORT5_OMR_PR11_Pos)                          /*!< PORT5 OMR: PR11 Mask                    */\r
+#define PORT5_OMR_PR12_Pos                    28                                                      /*!< PORT5 OMR: PR12 Position                */\r
+#define PORT5_OMR_PR12_Msk                    (0x01UL << PORT5_OMR_PR12_Pos)                          /*!< PORT5 OMR: PR12 Mask                    */\r
+#define PORT5_OMR_PR13_Pos                    29                                                      /*!< PORT5 OMR: PR13 Position                */\r
+#define PORT5_OMR_PR13_Msk                    (0x01UL << PORT5_OMR_PR13_Pos)                          /*!< PORT5 OMR: PR13 Mask                    */\r
+#define PORT5_OMR_PR14_Pos                    30                                                      /*!< PORT5 OMR: PR14 Position                */\r
+#define PORT5_OMR_PR14_Msk                    (0x01UL << PORT5_OMR_PR14_Pos)                          /*!< PORT5 OMR: PR14 Mask                    */\r
+#define PORT5_OMR_PR15_Pos                    31                                                      /*!< PORT5 OMR: PR15 Position                */\r
+#define PORT5_OMR_PR15_Msk                    (0x01UL << PORT5_OMR_PR15_Pos)                          /*!< PORT5 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT5_IOCR0  -------------------------------- */\r
+#define PORT5_IOCR0_PC0_Pos                   3                                                       /*!< PORT5 IOCR0: PC0 Position               */\r
+#define PORT5_IOCR0_PC0_Msk                   (0x1fUL << PORT5_IOCR0_PC0_Pos)                         /*!< PORT5 IOCR0: PC0 Mask                   */\r
+#define PORT5_IOCR0_PC1_Pos                   11                                                      /*!< PORT5 IOCR0: PC1 Position               */\r
+#define PORT5_IOCR0_PC1_Msk                   (0x1fUL << PORT5_IOCR0_PC1_Pos)                         /*!< PORT5 IOCR0: PC1 Mask                   */\r
+#define PORT5_IOCR0_PC2_Pos                   19                                                      /*!< PORT5 IOCR0: PC2 Position               */\r
+#define PORT5_IOCR0_PC2_Msk                   (0x1fUL << PORT5_IOCR0_PC2_Pos)                         /*!< PORT5 IOCR0: PC2 Mask                   */\r
+#define PORT5_IOCR0_PC3_Pos                   27                                                      /*!< PORT5 IOCR0: PC3 Position               */\r
+#define PORT5_IOCR0_PC3_Msk                   (0x1fUL << PORT5_IOCR0_PC3_Pos)                         /*!< PORT5 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT5_IOCR4  -------------------------------- */\r
+#define PORT5_IOCR4_PC4_Pos                   3                                                       /*!< PORT5 IOCR4: PC4 Position               */\r
+#define PORT5_IOCR4_PC4_Msk                   (0x1fUL << PORT5_IOCR4_PC4_Pos)                         /*!< PORT5 IOCR4: PC4 Mask                   */\r
+#define PORT5_IOCR4_PC5_Pos                   11                                                      /*!< PORT5 IOCR4: PC5 Position               */\r
+#define PORT5_IOCR4_PC5_Msk                   (0x1fUL << PORT5_IOCR4_PC5_Pos)                         /*!< PORT5 IOCR4: PC5 Mask                   */\r
+#define PORT5_IOCR4_PC6_Pos                   19                                                      /*!< PORT5 IOCR4: PC6 Position               */\r
+#define PORT5_IOCR4_PC6_Msk                   (0x1fUL << PORT5_IOCR4_PC6_Pos)                         /*!< PORT5 IOCR4: PC6 Mask                   */\r
+#define PORT5_IOCR4_PC7_Pos                   27                                                      /*!< PORT5 IOCR4: PC7 Position               */\r
+#define PORT5_IOCR4_PC7_Msk                   (0x1fUL << PORT5_IOCR4_PC7_Pos)                         /*!< PORT5 IOCR4: PC7 Mask                   */\r
+\r
+/* ----------------------------------  PORT5_IN  ---------------------------------- */\r
+#define PORT5_IN_P0_Pos                       0                                                       /*!< PORT5 IN: P0 Position                   */\r
+#define PORT5_IN_P0_Msk                       (0x01UL << PORT5_IN_P0_Pos)                             /*!< PORT5 IN: P0 Mask                       */\r
+#define PORT5_IN_P1_Pos                       1                                                       /*!< PORT5 IN: P1 Position                   */\r
+#define PORT5_IN_P1_Msk                       (0x01UL << PORT5_IN_P1_Pos)                             /*!< PORT5 IN: P1 Mask                       */\r
+#define PORT5_IN_P2_Pos                       2                                                       /*!< PORT5 IN: P2 Position                   */\r
+#define PORT5_IN_P2_Msk                       (0x01UL << PORT5_IN_P2_Pos)                             /*!< PORT5 IN: P2 Mask                       */\r
+#define PORT5_IN_P3_Pos                       3                                                       /*!< PORT5 IN: P3 Position                   */\r
+#define PORT5_IN_P3_Msk                       (0x01UL << PORT5_IN_P3_Pos)                             /*!< PORT5 IN: P3 Mask                       */\r
+#define PORT5_IN_P4_Pos                       4                                                       /*!< PORT5 IN: P4 Position                   */\r
+#define PORT5_IN_P4_Msk                       (0x01UL << PORT5_IN_P4_Pos)                             /*!< PORT5 IN: P4 Mask                       */\r
+#define PORT5_IN_P5_Pos                       5                                                       /*!< PORT5 IN: P5 Position                   */\r
+#define PORT5_IN_P5_Msk                       (0x01UL << PORT5_IN_P5_Pos)                             /*!< PORT5 IN: P5 Mask                       */\r
+#define PORT5_IN_P6_Pos                       6                                                       /*!< PORT5 IN: P6 Position                   */\r
+#define PORT5_IN_P6_Msk                       (0x01UL << PORT5_IN_P6_Pos)                             /*!< PORT5 IN: P6 Mask                       */\r
+#define PORT5_IN_P7_Pos                       7                                                       /*!< PORT5 IN: P7 Position                   */\r
+#define PORT5_IN_P7_Msk                       (0x01UL << PORT5_IN_P7_Pos)                             /*!< PORT5 IN: P7 Mask                       */\r
+#define PORT5_IN_P8_Pos                       8                                                       /*!< PORT5 IN: P8 Position                   */\r
+#define PORT5_IN_P8_Msk                       (0x01UL << PORT5_IN_P8_Pos)                             /*!< PORT5 IN: P8 Mask                       */\r
+#define PORT5_IN_P9_Pos                       9                                                       /*!< PORT5 IN: P9 Position                   */\r
+#define PORT5_IN_P9_Msk                       (0x01UL << PORT5_IN_P9_Pos)                             /*!< PORT5 IN: P9 Mask                       */\r
+#define PORT5_IN_P10_Pos                      10                                                      /*!< PORT5 IN: P10 Position                  */\r
+#define PORT5_IN_P10_Msk                      (0x01UL << PORT5_IN_P10_Pos)                            /*!< PORT5 IN: P10 Mask                      */\r
+#define PORT5_IN_P11_Pos                      11                                                      /*!< PORT5 IN: P11 Position                  */\r
+#define PORT5_IN_P11_Msk                      (0x01UL << PORT5_IN_P11_Pos)                            /*!< PORT5 IN: P11 Mask                      */\r
+#define PORT5_IN_P12_Pos                      12                                                      /*!< PORT5 IN: P12 Position                  */\r
+#define PORT5_IN_P12_Msk                      (0x01UL << PORT5_IN_P12_Pos)                            /*!< PORT5 IN: P12 Mask                      */\r
+#define PORT5_IN_P13_Pos                      13                                                      /*!< PORT5 IN: P13 Position                  */\r
+#define PORT5_IN_P13_Msk                      (0x01UL << PORT5_IN_P13_Pos)                            /*!< PORT5 IN: P13 Mask                      */\r
+#define PORT5_IN_P14_Pos                      14                                                      /*!< PORT5 IN: P14 Position                  */\r
+#define PORT5_IN_P14_Msk                      (0x01UL << PORT5_IN_P14_Pos)                            /*!< PORT5 IN: P14 Mask                      */\r
+#define PORT5_IN_P15_Pos                      15                                                      /*!< PORT5 IN: P15 Position                  */\r
+#define PORT5_IN_P15_Msk                      (0x01UL << PORT5_IN_P15_Pos)                            /*!< PORT5 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT5_PDR0  --------------------------------- */\r
+#define PORT5_PDR0_PD0_Pos                    0                                                       /*!< PORT5 PDR0: PD0 Position                */\r
+#define PORT5_PDR0_PD0_Msk                    (0x07UL << PORT5_PDR0_PD0_Pos)                          /*!< PORT5 PDR0: PD0 Mask                    */\r
+#define PORT5_PDR0_PD1_Pos                    4                                                       /*!< PORT5 PDR0: PD1 Position                */\r
+#define PORT5_PDR0_PD1_Msk                    (0x07UL << PORT5_PDR0_PD1_Pos)                          /*!< PORT5 PDR0: PD1 Mask                    */\r
+#define PORT5_PDR0_PD2_Pos                    8                                                       /*!< PORT5 PDR0: PD2 Position                */\r
+#define PORT5_PDR0_PD2_Msk                    (0x07UL << PORT5_PDR0_PD2_Pos)                          /*!< PORT5 PDR0: PD2 Mask                    */\r
+#define PORT5_PDR0_PD3_Pos                    12                                                      /*!< PORT5 PDR0: PD3 Position                */\r
+#define PORT5_PDR0_PD3_Msk                    (0x07UL << PORT5_PDR0_PD3_Pos)                          /*!< PORT5 PDR0: PD3 Mask                    */\r
+#define PORT5_PDR0_PD4_Pos                    16                                                      /*!< PORT5 PDR0: PD4 Position                */\r
+#define PORT5_PDR0_PD4_Msk                    (0x07UL << PORT5_PDR0_PD4_Pos)                          /*!< PORT5 PDR0: PD4 Mask                    */\r
+#define PORT5_PDR0_PD5_Pos                    20                                                      /*!< PORT5 PDR0: PD5 Position                */\r
+#define PORT5_PDR0_PD5_Msk                    (0x07UL << PORT5_PDR0_PD5_Pos)                          /*!< PORT5 PDR0: PD5 Mask                    */\r
+#define PORT5_PDR0_PD6_Pos                    24                                                      /*!< PORT5 PDR0: PD6 Position                */\r
+#define PORT5_PDR0_PD6_Msk                    (0x07UL << PORT5_PDR0_PD6_Pos)                          /*!< PORT5 PDR0: PD6 Mask                    */\r
+#define PORT5_PDR0_PD7_Pos                    28                                                      /*!< PORT5 PDR0: PD7 Position                */\r
+#define PORT5_PDR0_PD7_Msk                    (0x07UL << PORT5_PDR0_PD7_Pos)                          /*!< PORT5 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT5_PDISC  -------------------------------- */\r
+#define PORT5_PDISC_PDIS0_Pos                 0                                                       /*!< PORT5 PDISC: PDIS0 Position             */\r
+#define PORT5_PDISC_PDIS0_Msk                 (0x01UL << PORT5_PDISC_PDIS0_Pos)                       /*!< PORT5 PDISC: PDIS0 Mask                 */\r
+#define PORT5_PDISC_PDIS1_Pos                 1                                                       /*!< PORT5 PDISC: PDIS1 Position             */\r
+#define PORT5_PDISC_PDIS1_Msk                 (0x01UL << PORT5_PDISC_PDIS1_Pos)                       /*!< PORT5 PDISC: PDIS1 Mask                 */\r
+#define PORT5_PDISC_PDIS2_Pos                 2                                                       /*!< PORT5 PDISC: PDIS2 Position             */\r
+#define PORT5_PDISC_PDIS2_Msk                 (0x01UL << PORT5_PDISC_PDIS2_Pos)                       /*!< PORT5 PDISC: PDIS2 Mask                 */\r
+#define PORT5_PDISC_PDIS3_Pos                 3                                                       /*!< PORT5 PDISC: PDIS3 Position             */\r
+#define PORT5_PDISC_PDIS3_Msk                 (0x01UL << PORT5_PDISC_PDIS3_Pos)                       /*!< PORT5 PDISC: PDIS3 Mask                 */\r
+#define PORT5_PDISC_PDIS4_Pos                 4                                                       /*!< PORT5 PDISC: PDIS4 Position             */\r
+#define PORT5_PDISC_PDIS4_Msk                 (0x01UL << PORT5_PDISC_PDIS4_Pos)                       /*!< PORT5 PDISC: PDIS4 Mask                 */\r
+#define PORT5_PDISC_PDIS5_Pos                 5                                                       /*!< PORT5 PDISC: PDIS5 Position             */\r
+#define PORT5_PDISC_PDIS5_Msk                 (0x01UL << PORT5_PDISC_PDIS5_Pos)                       /*!< PORT5 PDISC: PDIS5 Mask                 */\r
+#define PORT5_PDISC_PDIS6_Pos                 6                                                       /*!< PORT5 PDISC: PDIS6 Position             */\r
+#define PORT5_PDISC_PDIS6_Msk                 (0x01UL << PORT5_PDISC_PDIS6_Pos)                       /*!< PORT5 PDISC: PDIS6 Mask                 */\r
+#define PORT5_PDISC_PDIS7_Pos                 7                                                       /*!< PORT5 PDISC: PDIS7 Position             */\r
+#define PORT5_PDISC_PDIS7_Msk                 (0x01UL << PORT5_PDISC_PDIS7_Pos)                       /*!< PORT5 PDISC: PDIS7 Mask                 */\r
+#define PORT5_PDISC_PDIS8_Pos                 8                                                       /*!< PORT5 PDISC: PDIS8 Position             */\r
+#define PORT5_PDISC_PDIS8_Msk                 (0x01UL << PORT5_PDISC_PDIS8_Pos)                       /*!< PORT5 PDISC: PDIS8 Mask                 */\r
+#define PORT5_PDISC_PDIS9_Pos                 9                                                       /*!< PORT5 PDISC: PDIS9 Position             */\r
+#define PORT5_PDISC_PDIS9_Msk                 (0x01UL << PORT5_PDISC_PDIS9_Pos)                       /*!< PORT5 PDISC: PDIS9 Mask                 */\r
+#define PORT5_PDISC_PDIS10_Pos                10                                                      /*!< PORT5 PDISC: PDIS10 Position            */\r
+#define PORT5_PDISC_PDIS10_Msk                (0x01UL << PORT5_PDISC_PDIS10_Pos)                      /*!< PORT5 PDISC: PDIS10 Mask                */\r
+#define PORT5_PDISC_PDIS11_Pos                11                                                      /*!< PORT5 PDISC: PDIS11 Position            */\r
+#define PORT5_PDISC_PDIS11_Msk                (0x01UL << PORT5_PDISC_PDIS11_Pos)                      /*!< PORT5 PDISC: PDIS11 Mask                */\r
+#define PORT5_PDISC_PDIS12_Pos                12                                                      /*!< PORT5 PDISC: PDIS12 Position            */\r
+#define PORT5_PDISC_PDIS12_Msk                (0x01UL << PORT5_PDISC_PDIS12_Pos)                      /*!< PORT5 PDISC: PDIS12 Mask                */\r
+#define PORT5_PDISC_PDIS13_Pos                13                                                      /*!< PORT5 PDISC: PDIS13 Position            */\r
+#define PORT5_PDISC_PDIS13_Msk                (0x01UL << PORT5_PDISC_PDIS13_Pos)                      /*!< PORT5 PDISC: PDIS13 Mask                */\r
+#define PORT5_PDISC_PDIS14_Pos                14                                                      /*!< PORT5 PDISC: PDIS14 Position            */\r
+#define PORT5_PDISC_PDIS14_Msk                (0x01UL << PORT5_PDISC_PDIS14_Pos)                      /*!< PORT5 PDISC: PDIS14 Mask                */\r
+#define PORT5_PDISC_PDIS15_Pos                15                                                      /*!< PORT5 PDISC: PDIS15 Position            */\r
+#define PORT5_PDISC_PDIS15_Msk                (0x01UL << PORT5_PDISC_PDIS15_Pos)                      /*!< PORT5 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT5_PPS  --------------------------------- */\r
+#define PORT5_PPS_PPS0_Pos                    0                                                       /*!< PORT5 PPS: PPS0 Position                */\r
+#define PORT5_PPS_PPS0_Msk                    (0x01UL << PORT5_PPS_PPS0_Pos)                          /*!< PORT5 PPS: PPS0 Mask                    */\r
+#define PORT5_PPS_PPS1_Pos                    1                                                       /*!< PORT5 PPS: PPS1 Position                */\r
+#define PORT5_PPS_PPS1_Msk                    (0x01UL << PORT5_PPS_PPS1_Pos)                          /*!< PORT5 PPS: PPS1 Mask                    */\r
+#define PORT5_PPS_PPS2_Pos                    2                                                       /*!< PORT5 PPS: PPS2 Position                */\r
+#define PORT5_PPS_PPS2_Msk                    (0x01UL << PORT5_PPS_PPS2_Pos)                          /*!< PORT5 PPS: PPS2 Mask                    */\r
+#define PORT5_PPS_PPS3_Pos                    3                                                       /*!< PORT5 PPS: PPS3 Position                */\r
+#define PORT5_PPS_PPS3_Msk                    (0x01UL << PORT5_PPS_PPS3_Pos)                          /*!< PORT5 PPS: PPS3 Mask                    */\r
+#define PORT5_PPS_PPS4_Pos                    4                                                       /*!< PORT5 PPS: PPS4 Position                */\r
+#define PORT5_PPS_PPS4_Msk                    (0x01UL << PORT5_PPS_PPS4_Pos)                          /*!< PORT5 PPS: PPS4 Mask                    */\r
+#define PORT5_PPS_PPS5_Pos                    5                                                       /*!< PORT5 PPS: PPS5 Position                */\r
+#define PORT5_PPS_PPS5_Msk                    (0x01UL << PORT5_PPS_PPS5_Pos)                          /*!< PORT5 PPS: PPS5 Mask                    */\r
+#define PORT5_PPS_PPS6_Pos                    6                                                       /*!< PORT5 PPS: PPS6 Position                */\r
+#define PORT5_PPS_PPS6_Msk                    (0x01UL << PORT5_PPS_PPS6_Pos)                          /*!< PORT5 PPS: PPS6 Mask                    */\r
+#define PORT5_PPS_PPS7_Pos                    7                                                       /*!< PORT5 PPS: PPS7 Position                */\r
+#define PORT5_PPS_PPS7_Msk                    (0x01UL << PORT5_PPS_PPS7_Pos)                          /*!< PORT5 PPS: PPS7 Mask                    */\r
+#define PORT5_PPS_PPS8_Pos                    8                                                       /*!< PORT5 PPS: PPS8 Position                */\r
+#define PORT5_PPS_PPS8_Msk                    (0x01UL << PORT5_PPS_PPS8_Pos)                          /*!< PORT5 PPS: PPS8 Mask                    */\r
+#define PORT5_PPS_PPS9_Pos                    9                                                       /*!< PORT5 PPS: PPS9 Position                */\r
+#define PORT5_PPS_PPS9_Msk                    (0x01UL << PORT5_PPS_PPS9_Pos)                          /*!< PORT5 PPS: PPS9 Mask                    */\r
+#define PORT5_PPS_PPS10_Pos                   10                                                      /*!< PORT5 PPS: PPS10 Position               */\r
+#define PORT5_PPS_PPS10_Msk                   (0x01UL << PORT5_PPS_PPS10_Pos)                         /*!< PORT5 PPS: PPS10 Mask                   */\r
+#define PORT5_PPS_PPS11_Pos                   11                                                      /*!< PORT5 PPS: PPS11 Position               */\r
+#define PORT5_PPS_PPS11_Msk                   (0x01UL << PORT5_PPS_PPS11_Pos)                         /*!< PORT5 PPS: PPS11 Mask                   */\r
+#define PORT5_PPS_PPS12_Pos                   12                                                      /*!< PORT5 PPS: PPS12 Position               */\r
+#define PORT5_PPS_PPS12_Msk                   (0x01UL << PORT5_PPS_PPS12_Pos)                         /*!< PORT5 PPS: PPS12 Mask                   */\r
+#define PORT5_PPS_PPS13_Pos                   13                                                      /*!< PORT5 PPS: PPS13 Position               */\r
+#define PORT5_PPS_PPS13_Msk                   (0x01UL << PORT5_PPS_PPS13_Pos)                         /*!< PORT5 PPS: PPS13 Mask                   */\r
+#define PORT5_PPS_PPS14_Pos                   14                                                      /*!< PORT5 PPS: PPS14 Position               */\r
+#define PORT5_PPS_PPS14_Msk                   (0x01UL << PORT5_PPS_PPS14_Pos)                         /*!< PORT5 PPS: PPS14 Mask                   */\r
+#define PORT5_PPS_PPS15_Pos                   15                                                      /*!< PORT5 PPS: PPS15 Position               */\r
+#define PORT5_PPS_PPS15_Msk                   (0x01UL << PORT5_PPS_PPS15_Pos)                         /*!< PORT5 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT5_HWSEL  -------------------------------- */\r
+#define PORT5_HWSEL_HW0_Pos                   0                                                       /*!< PORT5 HWSEL: HW0 Position               */\r
+#define PORT5_HWSEL_HW0_Msk                   (0x03UL << PORT5_HWSEL_HW0_Pos)                         /*!< PORT5 HWSEL: HW0 Mask                   */\r
+#define PORT5_HWSEL_HW1_Pos                   2                                                       /*!< PORT5 HWSEL: HW1 Position               */\r
+#define PORT5_HWSEL_HW1_Msk                   (0x03UL << PORT5_HWSEL_HW1_Pos)                         /*!< PORT5 HWSEL: HW1 Mask                   */\r
+#define PORT5_HWSEL_HW2_Pos                   4                                                       /*!< PORT5 HWSEL: HW2 Position               */\r
+#define PORT5_HWSEL_HW2_Msk                   (0x03UL << PORT5_HWSEL_HW2_Pos)                         /*!< PORT5 HWSEL: HW2 Mask                   */\r
+#define PORT5_HWSEL_HW3_Pos                   6                                                       /*!< PORT5 HWSEL: HW3 Position               */\r
+#define PORT5_HWSEL_HW3_Msk                   (0x03UL << PORT5_HWSEL_HW3_Pos)                         /*!< PORT5 HWSEL: HW3 Mask                   */\r
+#define PORT5_HWSEL_HW4_Pos                   8                                                       /*!< PORT5 HWSEL: HW4 Position               */\r
+#define PORT5_HWSEL_HW4_Msk                   (0x03UL << PORT5_HWSEL_HW4_Pos)                         /*!< PORT5 HWSEL: HW4 Mask                   */\r
+#define PORT5_HWSEL_HW5_Pos                   10                                                      /*!< PORT5 HWSEL: HW5 Position               */\r
+#define PORT5_HWSEL_HW5_Msk                   (0x03UL << PORT5_HWSEL_HW5_Pos)                         /*!< PORT5 HWSEL: HW5 Mask                   */\r
+#define PORT5_HWSEL_HW6_Pos                   12                                                      /*!< PORT5 HWSEL: HW6 Position               */\r
+#define PORT5_HWSEL_HW6_Msk                   (0x03UL << PORT5_HWSEL_HW6_Pos)                         /*!< PORT5 HWSEL: HW6 Mask                   */\r
+#define PORT5_HWSEL_HW7_Pos                   14                                                      /*!< PORT5 HWSEL: HW7 Position               */\r
+#define PORT5_HWSEL_HW7_Msk                   (0x03UL << PORT5_HWSEL_HW7_Pos)                         /*!< PORT5 HWSEL: HW7 Mask                   */\r
+#define PORT5_HWSEL_HW8_Pos                   16                                                      /*!< PORT5 HWSEL: HW8 Position               */\r
+#define PORT5_HWSEL_HW8_Msk                   (0x03UL << PORT5_HWSEL_HW8_Pos)                         /*!< PORT5 HWSEL: HW8 Mask                   */\r
+#define PORT5_HWSEL_HW9_Pos                   18                                                      /*!< PORT5 HWSEL: HW9 Position               */\r
+#define PORT5_HWSEL_HW9_Msk                   (0x03UL << PORT5_HWSEL_HW9_Pos)                         /*!< PORT5 HWSEL: HW9 Mask                   */\r
+#define PORT5_HWSEL_HW10_Pos                  20                                                      /*!< PORT5 HWSEL: HW10 Position              */\r
+#define PORT5_HWSEL_HW10_Msk                  (0x03UL << PORT5_HWSEL_HW10_Pos)                        /*!< PORT5 HWSEL: HW10 Mask                  */\r
+#define PORT5_HWSEL_HW11_Pos                  22                                                      /*!< PORT5 HWSEL: HW11 Position              */\r
+#define PORT5_HWSEL_HW11_Msk                  (0x03UL << PORT5_HWSEL_HW11_Pos)                        /*!< PORT5 HWSEL: HW11 Mask                  */\r
+#define PORT5_HWSEL_HW12_Pos                  24                                                      /*!< PORT5 HWSEL: HW12 Position              */\r
+#define PORT5_HWSEL_HW12_Msk                  (0x03UL << PORT5_HWSEL_HW12_Pos)                        /*!< PORT5 HWSEL: HW12 Mask                  */\r
+#define PORT5_HWSEL_HW13_Pos                  26                                                      /*!< PORT5 HWSEL: HW13 Position              */\r
+#define PORT5_HWSEL_HW13_Msk                  (0x03UL << PORT5_HWSEL_HW13_Pos)                        /*!< PORT5 HWSEL: HW13 Mask                  */\r
+#define PORT5_HWSEL_HW14_Pos                  28                                                      /*!< PORT5 HWSEL: HW14 Position              */\r
+#define PORT5_HWSEL_HW14_Msk                  (0x03UL << PORT5_HWSEL_HW14_Pos)                        /*!< PORT5 HWSEL: HW14 Mask                  */\r
+#define PORT5_HWSEL_HW15_Pos                  30                                                      /*!< PORT5 HWSEL: HW15 Position              */\r
+#define PORT5_HWSEL_HW15_Msk                  (0x03UL << PORT5_HWSEL_HW15_Pos)                        /*!< PORT5 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT14' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  PORT14_OUT  --------------------------------- */\r
+#define PORT14_OUT_P0_Pos                     0                                                       /*!< PORT14 OUT: P0 Position                 */\r
+#define PORT14_OUT_P0_Msk                     (0x01UL << PORT14_OUT_P0_Pos)                           /*!< PORT14 OUT: P0 Mask                     */\r
+#define PORT14_OUT_P1_Pos                     1                                                       /*!< PORT14 OUT: P1 Position                 */\r
+#define PORT14_OUT_P1_Msk                     (0x01UL << PORT14_OUT_P1_Pos)                           /*!< PORT14 OUT: P1 Mask                     */\r
+#define PORT14_OUT_P2_Pos                     2                                                       /*!< PORT14 OUT: P2 Position                 */\r
+#define PORT14_OUT_P2_Msk                     (0x01UL << PORT14_OUT_P2_Pos)                           /*!< PORT14 OUT: P2 Mask                     */\r
+#define PORT14_OUT_P3_Pos                     3                                                       /*!< PORT14 OUT: P3 Position                 */\r
+#define PORT14_OUT_P3_Msk                     (0x01UL << PORT14_OUT_P3_Pos)                           /*!< PORT14 OUT: P3 Mask                     */\r
+#define PORT14_OUT_P4_Pos                     4                                                       /*!< PORT14 OUT: P4 Position                 */\r
+#define PORT14_OUT_P4_Msk                     (0x01UL << PORT14_OUT_P4_Pos)                           /*!< PORT14 OUT: P4 Mask                     */\r
+#define PORT14_OUT_P5_Pos                     5                                                       /*!< PORT14 OUT: P5 Position                 */\r
+#define PORT14_OUT_P5_Msk                     (0x01UL << PORT14_OUT_P5_Pos)                           /*!< PORT14 OUT: P5 Mask                     */\r
+#define PORT14_OUT_P6_Pos                     6                                                       /*!< PORT14 OUT: P6 Position                 */\r
+#define PORT14_OUT_P6_Msk                     (0x01UL << PORT14_OUT_P6_Pos)                           /*!< PORT14 OUT: P6 Mask                     */\r
+#define PORT14_OUT_P7_Pos                     7                                                       /*!< PORT14 OUT: P7 Position                 */\r
+#define PORT14_OUT_P7_Msk                     (0x01UL << PORT14_OUT_P7_Pos)                           /*!< PORT14 OUT: P7 Mask                     */\r
+#define PORT14_OUT_P8_Pos                     8                                                       /*!< PORT14 OUT: P8 Position                 */\r
+#define PORT14_OUT_P8_Msk                     (0x01UL << PORT14_OUT_P8_Pos)                           /*!< PORT14 OUT: P8 Mask                     */\r
+#define PORT14_OUT_P9_Pos                     9                                                       /*!< PORT14 OUT: P9 Position                 */\r
+#define PORT14_OUT_P9_Msk                     (0x01UL << PORT14_OUT_P9_Pos)                           /*!< PORT14 OUT: P9 Mask                     */\r
+#define PORT14_OUT_P10_Pos                    10                                                      /*!< PORT14 OUT: P10 Position                */\r
+#define PORT14_OUT_P10_Msk                    (0x01UL << PORT14_OUT_P10_Pos)                          /*!< PORT14 OUT: P10 Mask                    */\r
+#define PORT14_OUT_P11_Pos                    11                                                      /*!< PORT14 OUT: P11 Position                */\r
+#define PORT14_OUT_P11_Msk                    (0x01UL << PORT14_OUT_P11_Pos)                          /*!< PORT14 OUT: P11 Mask                    */\r
+#define PORT14_OUT_P12_Pos                    12                                                      /*!< PORT14 OUT: P12 Position                */\r
+#define PORT14_OUT_P12_Msk                    (0x01UL << PORT14_OUT_P12_Pos)                          /*!< PORT14 OUT: P12 Mask                    */\r
+#define PORT14_OUT_P13_Pos                    13                                                      /*!< PORT14 OUT: P13 Position                */\r
+#define PORT14_OUT_P13_Msk                    (0x01UL << PORT14_OUT_P13_Pos)                          /*!< PORT14 OUT: P13 Mask                    */\r
+#define PORT14_OUT_P14_Pos                    14                                                      /*!< PORT14 OUT: P14 Position                */\r
+#define PORT14_OUT_P14_Msk                    (0x01UL << PORT14_OUT_P14_Pos)                          /*!< PORT14 OUT: P14 Mask                    */\r
+#define PORT14_OUT_P15_Pos                    15                                                      /*!< PORT14 OUT: P15 Position                */\r
+#define PORT14_OUT_P15_Msk                    (0x01UL << PORT14_OUT_P15_Pos)                          /*!< PORT14 OUT: P15 Mask                    */\r
+\r
+/* ---------------------------------  PORT14_OMR  --------------------------------- */\r
+#define PORT14_OMR_PS0_Pos                    0                                                       /*!< PORT14 OMR: PS0 Position                */\r
+#define PORT14_OMR_PS0_Msk                    (0x01UL << PORT14_OMR_PS0_Pos)                          /*!< PORT14 OMR: PS0 Mask                    */\r
+#define PORT14_OMR_PS1_Pos                    1                                                       /*!< PORT14 OMR: PS1 Position                */\r
+#define PORT14_OMR_PS1_Msk                    (0x01UL << PORT14_OMR_PS1_Pos)                          /*!< PORT14 OMR: PS1 Mask                    */\r
+#define PORT14_OMR_PS2_Pos                    2                                                       /*!< PORT14 OMR: PS2 Position                */\r
+#define PORT14_OMR_PS2_Msk                    (0x01UL << PORT14_OMR_PS2_Pos)                          /*!< PORT14 OMR: PS2 Mask                    */\r
+#define PORT14_OMR_PS3_Pos                    3                                                       /*!< PORT14 OMR: PS3 Position                */\r
+#define PORT14_OMR_PS3_Msk                    (0x01UL << PORT14_OMR_PS3_Pos)                          /*!< PORT14 OMR: PS3 Mask                    */\r
+#define PORT14_OMR_PS4_Pos                    4                                                       /*!< PORT14 OMR: PS4 Position                */\r
+#define PORT14_OMR_PS4_Msk                    (0x01UL << PORT14_OMR_PS4_Pos)                          /*!< PORT14 OMR: PS4 Mask                    */\r
+#define PORT14_OMR_PS5_Pos                    5                                                       /*!< PORT14 OMR: PS5 Position                */\r
+#define PORT14_OMR_PS5_Msk                    (0x01UL << PORT14_OMR_PS5_Pos)                          /*!< PORT14 OMR: PS5 Mask                    */\r
+#define PORT14_OMR_PS6_Pos                    6                                                       /*!< PORT14 OMR: PS6 Position                */\r
+#define PORT14_OMR_PS6_Msk                    (0x01UL << PORT14_OMR_PS6_Pos)                          /*!< PORT14 OMR: PS6 Mask                    */\r
+#define PORT14_OMR_PS7_Pos                    7                                                       /*!< PORT14 OMR: PS7 Position                */\r
+#define PORT14_OMR_PS7_Msk                    (0x01UL << PORT14_OMR_PS7_Pos)                          /*!< PORT14 OMR: PS7 Mask                    */\r
+#define PORT14_OMR_PS8_Pos                    8                                                       /*!< PORT14 OMR: PS8 Position                */\r
+#define PORT14_OMR_PS8_Msk                    (0x01UL << PORT14_OMR_PS8_Pos)                          /*!< PORT14 OMR: PS8 Mask                    */\r
+#define PORT14_OMR_PS9_Pos                    9                                                       /*!< PORT14 OMR: PS9 Position                */\r
+#define PORT14_OMR_PS9_Msk                    (0x01UL << PORT14_OMR_PS9_Pos)                          /*!< PORT14 OMR: PS9 Mask                    */\r
+#define PORT14_OMR_PS10_Pos                   10                                                      /*!< PORT14 OMR: PS10 Position               */\r
+#define PORT14_OMR_PS10_Msk                   (0x01UL << PORT14_OMR_PS10_Pos)                         /*!< PORT14 OMR: PS10 Mask                   */\r
+#define PORT14_OMR_PS11_Pos                   11                                                      /*!< PORT14 OMR: PS11 Position               */\r
+#define PORT14_OMR_PS11_Msk                   (0x01UL << PORT14_OMR_PS11_Pos)                         /*!< PORT14 OMR: PS11 Mask                   */\r
+#define PORT14_OMR_PS12_Pos                   12                                                      /*!< PORT14 OMR: PS12 Position               */\r
+#define PORT14_OMR_PS12_Msk                   (0x01UL << PORT14_OMR_PS12_Pos)                         /*!< PORT14 OMR: PS12 Mask                   */\r
+#define PORT14_OMR_PS13_Pos                   13                                                      /*!< PORT14 OMR: PS13 Position               */\r
+#define PORT14_OMR_PS13_Msk                   (0x01UL << PORT14_OMR_PS13_Pos)                         /*!< PORT14 OMR: PS13 Mask                   */\r
+#define PORT14_OMR_PS14_Pos                   14                                                      /*!< PORT14 OMR: PS14 Position               */\r
+#define PORT14_OMR_PS14_Msk                   (0x01UL << PORT14_OMR_PS14_Pos)                         /*!< PORT14 OMR: PS14 Mask                   */\r
+#define PORT14_OMR_PS15_Pos                   15                                                      /*!< PORT14 OMR: PS15 Position               */\r
+#define PORT14_OMR_PS15_Msk                   (0x01UL << PORT14_OMR_PS15_Pos)                         /*!< PORT14 OMR: PS15 Mask                   */\r
+#define PORT14_OMR_PR0_Pos                    16                                                      /*!< PORT14 OMR: PR0 Position                */\r
+#define PORT14_OMR_PR0_Msk                    (0x01UL << PORT14_OMR_PR0_Pos)                          /*!< PORT14 OMR: PR0 Mask                    */\r
+#define PORT14_OMR_PR1_Pos                    17                                                      /*!< PORT14 OMR: PR1 Position                */\r
+#define PORT14_OMR_PR1_Msk                    (0x01UL << PORT14_OMR_PR1_Pos)                          /*!< PORT14 OMR: PR1 Mask                    */\r
+#define PORT14_OMR_PR2_Pos                    18                                                      /*!< PORT14 OMR: PR2 Position                */\r
+#define PORT14_OMR_PR2_Msk                    (0x01UL << PORT14_OMR_PR2_Pos)                          /*!< PORT14 OMR: PR2 Mask                    */\r
+#define PORT14_OMR_PR3_Pos                    19                                                      /*!< PORT14 OMR: PR3 Position                */\r
+#define PORT14_OMR_PR3_Msk                    (0x01UL << PORT14_OMR_PR3_Pos)                          /*!< PORT14 OMR: PR3 Mask                    */\r
+#define PORT14_OMR_PR4_Pos                    20                                                      /*!< PORT14 OMR: PR4 Position                */\r
+#define PORT14_OMR_PR4_Msk                    (0x01UL << PORT14_OMR_PR4_Pos)                          /*!< PORT14 OMR: PR4 Mask                    */\r
+#define PORT14_OMR_PR5_Pos                    21                                                      /*!< PORT14 OMR: PR5 Position                */\r
+#define PORT14_OMR_PR5_Msk                    (0x01UL << PORT14_OMR_PR5_Pos)                          /*!< PORT14 OMR: PR5 Mask                    */\r
+#define PORT14_OMR_PR6_Pos                    22                                                      /*!< PORT14 OMR: PR6 Position                */\r
+#define PORT14_OMR_PR6_Msk                    (0x01UL << PORT14_OMR_PR6_Pos)                          /*!< PORT14 OMR: PR6 Mask                    */\r
+#define PORT14_OMR_PR7_Pos                    23                                                      /*!< PORT14 OMR: PR7 Position                */\r
+#define PORT14_OMR_PR7_Msk                    (0x01UL << PORT14_OMR_PR7_Pos)                          /*!< PORT14 OMR: PR7 Mask                    */\r
+#define PORT14_OMR_PR8_Pos                    24                                                      /*!< PORT14 OMR: PR8 Position                */\r
+#define PORT14_OMR_PR8_Msk                    (0x01UL << PORT14_OMR_PR8_Pos)                          /*!< PORT14 OMR: PR8 Mask                    */\r
+#define PORT14_OMR_PR9_Pos                    25                                                      /*!< PORT14 OMR: PR9 Position                */\r
+#define PORT14_OMR_PR9_Msk                    (0x01UL << PORT14_OMR_PR9_Pos)                          /*!< PORT14 OMR: PR9 Mask                    */\r
+#define PORT14_OMR_PR10_Pos                   26                                                      /*!< PORT14 OMR: PR10 Position               */\r
+#define PORT14_OMR_PR10_Msk                   (0x01UL << PORT14_OMR_PR10_Pos)                         /*!< PORT14 OMR: PR10 Mask                   */\r
+#define PORT14_OMR_PR11_Pos                   27                                                      /*!< PORT14 OMR: PR11 Position               */\r
+#define PORT14_OMR_PR11_Msk                   (0x01UL << PORT14_OMR_PR11_Pos)                         /*!< PORT14 OMR: PR11 Mask                   */\r
+#define PORT14_OMR_PR12_Pos                   28                                                      /*!< PORT14 OMR: PR12 Position               */\r
+#define PORT14_OMR_PR12_Msk                   (0x01UL << PORT14_OMR_PR12_Pos)                         /*!< PORT14 OMR: PR12 Mask                   */\r
+#define PORT14_OMR_PR13_Pos                   29                                                      /*!< PORT14 OMR: PR13 Position               */\r
+#define PORT14_OMR_PR13_Msk                   (0x01UL << PORT14_OMR_PR13_Pos)                         /*!< PORT14 OMR: PR13 Mask                   */\r
+#define PORT14_OMR_PR14_Pos                   30                                                      /*!< PORT14 OMR: PR14 Position               */\r
+#define PORT14_OMR_PR14_Msk                   (0x01UL << PORT14_OMR_PR14_Pos)                         /*!< PORT14 OMR: PR14 Mask                   */\r
+#define PORT14_OMR_PR15_Pos                   31                                                      /*!< PORT14 OMR: PR15 Position               */\r
+#define PORT14_OMR_PR15_Msk                   (0x01UL << PORT14_OMR_PR15_Pos)                         /*!< PORT14 OMR: PR15 Mask                   */\r
+\r
+/* --------------------------------  PORT14_IOCR0  -------------------------------- */\r
+#define PORT14_IOCR0_PC0_Pos                  3                                                       /*!< PORT14 IOCR0: PC0 Position              */\r
+#define PORT14_IOCR0_PC0_Msk                  (0x1fUL << PORT14_IOCR0_PC0_Pos)                        /*!< PORT14 IOCR0: PC0 Mask                  */\r
+#define PORT14_IOCR0_PC1_Pos                  11                                                      /*!< PORT14 IOCR0: PC1 Position              */\r
+#define PORT14_IOCR0_PC1_Msk                  (0x1fUL << PORT14_IOCR0_PC1_Pos)                        /*!< PORT14 IOCR0: PC1 Mask                  */\r
+#define PORT14_IOCR0_PC2_Pos                  19                                                      /*!< PORT14 IOCR0: PC2 Position              */\r
+#define PORT14_IOCR0_PC2_Msk                  (0x1fUL << PORT14_IOCR0_PC2_Pos)                        /*!< PORT14 IOCR0: PC2 Mask                  */\r
+#define PORT14_IOCR0_PC3_Pos                  27                                                      /*!< PORT14 IOCR0: PC3 Position              */\r
+#define PORT14_IOCR0_PC3_Msk                  (0x1fUL << PORT14_IOCR0_PC3_Pos)                        /*!< PORT14 IOCR0: PC3 Mask                  */\r
+\r
+/* --------------------------------  PORT14_IOCR4  -------------------------------- */\r
+#define PORT14_IOCR4_PC4_Pos                  3                                                       /*!< PORT14 IOCR4: PC4 Position              */\r
+#define PORT14_IOCR4_PC4_Msk                  (0x1fUL << PORT14_IOCR4_PC4_Pos)                        /*!< PORT14 IOCR4: PC4 Mask                  */\r
+#define PORT14_IOCR4_PC5_Pos                  11                                                      /*!< PORT14 IOCR4: PC5 Position              */\r
+#define PORT14_IOCR4_PC5_Msk                  (0x1fUL << PORT14_IOCR4_PC5_Pos)                        /*!< PORT14 IOCR4: PC5 Mask                  */\r
+#define PORT14_IOCR4_PC6_Pos                  19                                                      /*!< PORT14 IOCR4: PC6 Position              */\r
+#define PORT14_IOCR4_PC6_Msk                  (0x1fUL << PORT14_IOCR4_PC6_Pos)                        /*!< PORT14 IOCR4: PC6 Mask                  */\r
+#define PORT14_IOCR4_PC7_Pos                  27                                                      /*!< PORT14 IOCR4: PC7 Position              */\r
+#define PORT14_IOCR4_PC7_Msk                  (0x1fUL << PORT14_IOCR4_PC7_Pos)                        /*!< PORT14 IOCR4: PC7 Mask                  */\r
+\r
+/* --------------------------------  PORT14_IOCR8  -------------------------------- */\r
+#define PORT14_IOCR8_PC8_Pos                  3                                                       /*!< PORT14 IOCR8: PC8 Position              */\r
+#define PORT14_IOCR8_PC8_Msk                  (0x1fUL << PORT14_IOCR8_PC8_Pos)                        /*!< PORT14 IOCR8: PC8 Mask                  */\r
+#define PORT14_IOCR8_PC9_Pos                  11                                                      /*!< PORT14 IOCR8: PC9 Position              */\r
+#define PORT14_IOCR8_PC9_Msk                  (0x1fUL << PORT14_IOCR8_PC9_Pos)                        /*!< PORT14 IOCR8: PC9 Mask                  */\r
+#define PORT14_IOCR8_PC10_Pos                 19                                                      /*!< PORT14 IOCR8: PC10 Position             */\r
+#define PORT14_IOCR8_PC10_Msk                 (0x1fUL << PORT14_IOCR8_PC10_Pos)                       /*!< PORT14 IOCR8: PC10 Mask                 */\r
+#define PORT14_IOCR8_PC11_Pos                 27                                                      /*!< PORT14 IOCR8: PC11 Position             */\r
+#define PORT14_IOCR8_PC11_Msk                 (0x1fUL << PORT14_IOCR8_PC11_Pos)                       /*!< PORT14 IOCR8: PC11 Mask                 */\r
+\r
+/* --------------------------------  PORT14_IOCR12  ------------------------------- */\r
+#define PORT14_IOCR12_PC12_Pos                3                                                       /*!< PORT14 IOCR12: PC12 Position            */\r
+#define PORT14_IOCR12_PC12_Msk                (0x1fUL << PORT14_IOCR12_PC12_Pos)                      /*!< PORT14 IOCR12: PC12 Mask                */\r
+#define PORT14_IOCR12_PC13_Pos                11                                                      /*!< PORT14 IOCR12: PC13 Position            */\r
+#define PORT14_IOCR12_PC13_Msk                (0x1fUL << PORT14_IOCR12_PC13_Pos)                      /*!< PORT14 IOCR12: PC13 Mask                */\r
+#define PORT14_IOCR12_PC14_Pos                19                                                      /*!< PORT14 IOCR12: PC14 Position            */\r
+#define PORT14_IOCR12_PC14_Msk                (0x1fUL << PORT14_IOCR12_PC14_Pos)                      /*!< PORT14 IOCR12: PC14 Mask                */\r
+#define PORT14_IOCR12_PC15_Pos                27                                                      /*!< PORT14 IOCR12: PC15 Position            */\r
+#define PORT14_IOCR12_PC15_Msk                (0x1fUL << PORT14_IOCR12_PC15_Pos)                      /*!< PORT14 IOCR12: PC15 Mask                */\r
+\r
+/* ----------------------------------  PORT14_IN  --------------------------------- */\r
+#define PORT14_IN_P0_Pos                      0                                                       /*!< PORT14 IN: P0 Position                  */\r
+#define PORT14_IN_P0_Msk                      (0x01UL << PORT14_IN_P0_Pos)                            /*!< PORT14 IN: P0 Mask                      */\r
+#define PORT14_IN_P1_Pos                      1                                                       /*!< PORT14 IN: P1 Position                  */\r
+#define PORT14_IN_P1_Msk                      (0x01UL << PORT14_IN_P1_Pos)                            /*!< PORT14 IN: P1 Mask                      */\r
+#define PORT14_IN_P2_Pos                      2                                                       /*!< PORT14 IN: P2 Position                  */\r
+#define PORT14_IN_P2_Msk                      (0x01UL << PORT14_IN_P2_Pos)                            /*!< PORT14 IN: P2 Mask                      */\r
+#define PORT14_IN_P3_Pos                      3                                                       /*!< PORT14 IN: P3 Position                  */\r
+#define PORT14_IN_P3_Msk                      (0x01UL << PORT14_IN_P3_Pos)                            /*!< PORT14 IN: P3 Mask                      */\r
+#define PORT14_IN_P4_Pos                      4                                                       /*!< PORT14 IN: P4 Position                  */\r
+#define PORT14_IN_P4_Msk                      (0x01UL << PORT14_IN_P4_Pos)                            /*!< PORT14 IN: P4 Mask                      */\r
+#define PORT14_IN_P5_Pos                      5                                                       /*!< PORT14 IN: P5 Position                  */\r
+#define PORT14_IN_P5_Msk                      (0x01UL << PORT14_IN_P5_Pos)                            /*!< PORT14 IN: P5 Mask                      */\r
+#define PORT14_IN_P6_Pos                      6                                                       /*!< PORT14 IN: P6 Position                  */\r
+#define PORT14_IN_P6_Msk                      (0x01UL << PORT14_IN_P6_Pos)                            /*!< PORT14 IN: P6 Mask                      */\r
+#define PORT14_IN_P7_Pos                      7                                                       /*!< PORT14 IN: P7 Position                  */\r
+#define PORT14_IN_P7_Msk                      (0x01UL << PORT14_IN_P7_Pos)                            /*!< PORT14 IN: P7 Mask                      */\r
+#define PORT14_IN_P8_Pos                      8                                                       /*!< PORT14 IN: P8 Position                  */\r
+#define PORT14_IN_P8_Msk                      (0x01UL << PORT14_IN_P8_Pos)                            /*!< PORT14 IN: P8 Mask                      */\r
+#define PORT14_IN_P9_Pos                      9                                                       /*!< PORT14 IN: P9 Position                  */\r
+#define PORT14_IN_P9_Msk                      (0x01UL << PORT14_IN_P9_Pos)                            /*!< PORT14 IN: P9 Mask                      */\r
+#define PORT14_IN_P10_Pos                     10                                                      /*!< PORT14 IN: P10 Position                 */\r
+#define PORT14_IN_P10_Msk                     (0x01UL << PORT14_IN_P10_Pos)                           /*!< PORT14 IN: P10 Mask                     */\r
+#define PORT14_IN_P11_Pos                     11                                                      /*!< PORT14 IN: P11 Position                 */\r
+#define PORT14_IN_P11_Msk                     (0x01UL << PORT14_IN_P11_Pos)                           /*!< PORT14 IN: P11 Mask                     */\r
+#define PORT14_IN_P12_Pos                     12                                                      /*!< PORT14 IN: P12 Position                 */\r
+#define PORT14_IN_P12_Msk                     (0x01UL << PORT14_IN_P12_Pos)                           /*!< PORT14 IN: P12 Mask                     */\r
+#define PORT14_IN_P13_Pos                     13                                                      /*!< PORT14 IN: P13 Position                 */\r
+#define PORT14_IN_P13_Msk                     (0x01UL << PORT14_IN_P13_Pos)                           /*!< PORT14 IN: P13 Mask                     */\r
+#define PORT14_IN_P14_Pos                     14                                                      /*!< PORT14 IN: P14 Position                 */\r
+#define PORT14_IN_P14_Msk                     (0x01UL << PORT14_IN_P14_Pos)                           /*!< PORT14 IN: P14 Mask                     */\r
+#define PORT14_IN_P15_Pos                     15                                                      /*!< PORT14 IN: P15 Position                 */\r
+#define PORT14_IN_P15_Msk                     (0x01UL << PORT14_IN_P15_Pos)                           /*!< PORT14 IN: P15 Mask                     */\r
+\r
+/* --------------------------------  PORT14_PDISC  -------------------------------- */\r
+#define PORT14_PDISC_PDIS0_Pos                0                                                       /*!< PORT14 PDISC: PDIS0 Position            */\r
+#define PORT14_PDISC_PDIS0_Msk                (0x01UL << PORT14_PDISC_PDIS0_Pos)                      /*!< PORT14 PDISC: PDIS0 Mask                */\r
+#define PORT14_PDISC_PDIS1_Pos                1                                                       /*!< PORT14 PDISC: PDIS1 Position            */\r
+#define PORT14_PDISC_PDIS1_Msk                (0x01UL << PORT14_PDISC_PDIS1_Pos)                      /*!< PORT14 PDISC: PDIS1 Mask                */\r
+#define PORT14_PDISC_PDIS2_Pos                2                                                       /*!< PORT14 PDISC: PDIS2 Position            */\r
+#define PORT14_PDISC_PDIS2_Msk                (0x01UL << PORT14_PDISC_PDIS2_Pos)                      /*!< PORT14 PDISC: PDIS2 Mask                */\r
+#define PORT14_PDISC_PDIS3_Pos                3                                                       /*!< PORT14 PDISC: PDIS3 Position            */\r
+#define PORT14_PDISC_PDIS3_Msk                (0x01UL << PORT14_PDISC_PDIS3_Pos)                      /*!< PORT14 PDISC: PDIS3 Mask                */\r
+#define PORT14_PDISC_PDIS4_Pos                4                                                       /*!< PORT14 PDISC: PDIS4 Position            */\r
+#define PORT14_PDISC_PDIS4_Msk                (0x01UL << PORT14_PDISC_PDIS4_Pos)                      /*!< PORT14 PDISC: PDIS4 Mask                */\r
+#define PORT14_PDISC_PDIS5_Pos                5                                                       /*!< PORT14 PDISC: PDIS5 Position            */\r
+#define PORT14_PDISC_PDIS5_Msk                (0x01UL << PORT14_PDISC_PDIS5_Pos)                      /*!< PORT14 PDISC: PDIS5 Mask                */\r
+#define PORT14_PDISC_PDIS6_Pos                6                                                       /*!< PORT14 PDISC: PDIS6 Position            */\r
+#define PORT14_PDISC_PDIS6_Msk                (0x01UL << PORT14_PDISC_PDIS6_Pos)                      /*!< PORT14 PDISC: PDIS6 Mask                */\r
+#define PORT14_PDISC_PDIS7_Pos                7                                                       /*!< PORT14 PDISC: PDIS7 Position            */\r
+#define PORT14_PDISC_PDIS7_Msk                (0x01UL << PORT14_PDISC_PDIS7_Pos)                      /*!< PORT14 PDISC: PDIS7 Mask                */\r
+#define PORT14_PDISC_PDIS8_Pos                8                                                       /*!< PORT14 PDISC: PDIS8 Position            */\r
+#define PORT14_PDISC_PDIS8_Msk                (0x01UL << PORT14_PDISC_PDIS8_Pos)                      /*!< PORT14 PDISC: PDIS8 Mask                */\r
+#define PORT14_PDISC_PDIS9_Pos                9                                                       /*!< PORT14 PDISC: PDIS9 Position            */\r
+#define PORT14_PDISC_PDIS9_Msk                (0x01UL << PORT14_PDISC_PDIS9_Pos)                      /*!< PORT14 PDISC: PDIS9 Mask                */\r
+#define PORT14_PDISC_PDIS10_Pos               10                                                      /*!< PORT14 PDISC: PDIS10 Position           */\r
+#define PORT14_PDISC_PDIS10_Msk               (0x01UL << PORT14_PDISC_PDIS10_Pos)                     /*!< PORT14 PDISC: PDIS10 Mask               */\r
+#define PORT14_PDISC_PDIS11_Pos               11                                                      /*!< PORT14 PDISC: PDIS11 Position           */\r
+#define PORT14_PDISC_PDIS11_Msk               (0x01UL << PORT14_PDISC_PDIS11_Pos)                     /*!< PORT14 PDISC: PDIS11 Mask               */\r
+#define PORT14_PDISC_PDIS12_Pos               12                                                      /*!< PORT14 PDISC: PDIS12 Position           */\r
+#define PORT14_PDISC_PDIS12_Msk               (0x01UL << PORT14_PDISC_PDIS12_Pos)                     /*!< PORT14 PDISC: PDIS12 Mask               */\r
+#define PORT14_PDISC_PDIS13_Pos               13                                                      /*!< PORT14 PDISC: PDIS13 Position           */\r
+#define PORT14_PDISC_PDIS13_Msk               (0x01UL << PORT14_PDISC_PDIS13_Pos)                     /*!< PORT14 PDISC: PDIS13 Mask               */\r
+#define PORT14_PDISC_PDIS14_Pos               14                                                      /*!< PORT14 PDISC: PDIS14 Position           */\r
+#define PORT14_PDISC_PDIS14_Msk               (0x01UL << PORT14_PDISC_PDIS14_Pos)                     /*!< PORT14 PDISC: PDIS14 Mask               */\r
+#define PORT14_PDISC_PDIS15_Pos               15                                                      /*!< PORT14 PDISC: PDIS15 Position           */\r
+#define PORT14_PDISC_PDIS15_Msk               (0x01UL << PORT14_PDISC_PDIS15_Pos)                     /*!< PORT14 PDISC: PDIS15 Mask               */\r
+\r
+/* ---------------------------------  PORT14_PPS  --------------------------------- */\r
+#define PORT14_PPS_PPS0_Pos                   0                                                       /*!< PORT14 PPS: PPS0 Position               */\r
+#define PORT14_PPS_PPS0_Msk                   (0x01UL << PORT14_PPS_PPS0_Pos)                         /*!< PORT14 PPS: PPS0 Mask                   */\r
+#define PORT14_PPS_PPS1_Pos                   1                                                       /*!< PORT14 PPS: PPS1 Position               */\r
+#define PORT14_PPS_PPS1_Msk                   (0x01UL << PORT14_PPS_PPS1_Pos)                         /*!< PORT14 PPS: PPS1 Mask                   */\r
+#define PORT14_PPS_PPS2_Pos                   2                                                       /*!< PORT14 PPS: PPS2 Position               */\r
+#define PORT14_PPS_PPS2_Msk                   (0x01UL << PORT14_PPS_PPS2_Pos)                         /*!< PORT14 PPS: PPS2 Mask                   */\r
+#define PORT14_PPS_PPS3_Pos                   3                                                       /*!< PORT14 PPS: PPS3 Position               */\r
+#define PORT14_PPS_PPS3_Msk                   (0x01UL << PORT14_PPS_PPS3_Pos)                         /*!< PORT14 PPS: PPS3 Mask                   */\r
+#define PORT14_PPS_PPS4_Pos                   4                                                       /*!< PORT14 PPS: PPS4 Position               */\r
+#define PORT14_PPS_PPS4_Msk                   (0x01UL << PORT14_PPS_PPS4_Pos)                         /*!< PORT14 PPS: PPS4 Mask                   */\r
+#define PORT14_PPS_PPS5_Pos                   5                                                       /*!< PORT14 PPS: PPS5 Position               */\r
+#define PORT14_PPS_PPS5_Msk                   (0x01UL << PORT14_PPS_PPS5_Pos)                         /*!< PORT14 PPS: PPS5 Mask                   */\r
+#define PORT14_PPS_PPS6_Pos                   6                                                       /*!< PORT14 PPS: PPS6 Position               */\r
+#define PORT14_PPS_PPS6_Msk                   (0x01UL << PORT14_PPS_PPS6_Pos)                         /*!< PORT14 PPS: PPS6 Mask                   */\r
+#define PORT14_PPS_PPS7_Pos                   7                                                       /*!< PORT14 PPS: PPS7 Position               */\r
+#define PORT14_PPS_PPS7_Msk                   (0x01UL << PORT14_PPS_PPS7_Pos)                         /*!< PORT14 PPS: PPS7 Mask                   */\r
+#define PORT14_PPS_PPS8_Pos                   8                                                       /*!< PORT14 PPS: PPS8 Position               */\r
+#define PORT14_PPS_PPS8_Msk                   (0x01UL << PORT14_PPS_PPS8_Pos)                         /*!< PORT14 PPS: PPS8 Mask                   */\r
+#define PORT14_PPS_PPS9_Pos                   9                                                       /*!< PORT14 PPS: PPS9 Position               */\r
+#define PORT14_PPS_PPS9_Msk                   (0x01UL << PORT14_PPS_PPS9_Pos)                         /*!< PORT14 PPS: PPS9 Mask                   */\r
+#define PORT14_PPS_PPS10_Pos                  10                                                      /*!< PORT14 PPS: PPS10 Position              */\r
+#define PORT14_PPS_PPS10_Msk                  (0x01UL << PORT14_PPS_PPS10_Pos)                        /*!< PORT14 PPS: PPS10 Mask                  */\r
+#define PORT14_PPS_PPS11_Pos                  11                                                      /*!< PORT14 PPS: PPS11 Position              */\r
+#define PORT14_PPS_PPS11_Msk                  (0x01UL << PORT14_PPS_PPS11_Pos)                        /*!< PORT14 PPS: PPS11 Mask                  */\r
+#define PORT14_PPS_PPS12_Pos                  12                                                      /*!< PORT14 PPS: PPS12 Position              */\r
+#define PORT14_PPS_PPS12_Msk                  (0x01UL << PORT14_PPS_PPS12_Pos)                        /*!< PORT14 PPS: PPS12 Mask                  */\r
+#define PORT14_PPS_PPS13_Pos                  13                                                      /*!< PORT14 PPS: PPS13 Position              */\r
+#define PORT14_PPS_PPS13_Msk                  (0x01UL << PORT14_PPS_PPS13_Pos)                        /*!< PORT14 PPS: PPS13 Mask                  */\r
+#define PORT14_PPS_PPS14_Pos                  14                                                      /*!< PORT14 PPS: PPS14 Position              */\r
+#define PORT14_PPS_PPS14_Msk                  (0x01UL << PORT14_PPS_PPS14_Pos)                        /*!< PORT14 PPS: PPS14 Mask                  */\r
+#define PORT14_PPS_PPS15_Pos                  15                                                      /*!< PORT14 PPS: PPS15 Position              */\r
+#define PORT14_PPS_PPS15_Msk                  (0x01UL << PORT14_PPS_PPS15_Pos)                        /*!< PORT14 PPS: PPS15 Mask                  */\r
+\r
+/* --------------------------------  PORT14_HWSEL  -------------------------------- */\r
+#define PORT14_HWSEL_HW0_Pos                  0                                                       /*!< PORT14 HWSEL: HW0 Position              */\r
+#define PORT14_HWSEL_HW0_Msk                  (0x03UL << PORT14_HWSEL_HW0_Pos)                        /*!< PORT14 HWSEL: HW0 Mask                  */\r
+#define PORT14_HWSEL_HW1_Pos                  2                                                       /*!< PORT14 HWSEL: HW1 Position              */\r
+#define PORT14_HWSEL_HW1_Msk                  (0x03UL << PORT14_HWSEL_HW1_Pos)                        /*!< PORT14 HWSEL: HW1 Mask                  */\r
+#define PORT14_HWSEL_HW2_Pos                  4                                                       /*!< PORT14 HWSEL: HW2 Position              */\r
+#define PORT14_HWSEL_HW2_Msk                  (0x03UL << PORT14_HWSEL_HW2_Pos)                        /*!< PORT14 HWSEL: HW2 Mask                  */\r
+#define PORT14_HWSEL_HW3_Pos                  6                                                       /*!< PORT14 HWSEL: HW3 Position              */\r
+#define PORT14_HWSEL_HW3_Msk                  (0x03UL << PORT14_HWSEL_HW3_Pos)                        /*!< PORT14 HWSEL: HW3 Mask                  */\r
+#define PORT14_HWSEL_HW4_Pos                  8                                                       /*!< PORT14 HWSEL: HW4 Position              */\r
+#define PORT14_HWSEL_HW4_Msk                  (0x03UL << PORT14_HWSEL_HW4_Pos)                        /*!< PORT14 HWSEL: HW4 Mask                  */\r
+#define PORT14_HWSEL_HW5_Pos                  10                                                      /*!< PORT14 HWSEL: HW5 Position              */\r
+#define PORT14_HWSEL_HW5_Msk                  (0x03UL << PORT14_HWSEL_HW5_Pos)                        /*!< PORT14 HWSEL: HW5 Mask                  */\r
+#define PORT14_HWSEL_HW6_Pos                  12                                                      /*!< PORT14 HWSEL: HW6 Position              */\r
+#define PORT14_HWSEL_HW6_Msk                  (0x03UL << PORT14_HWSEL_HW6_Pos)                        /*!< PORT14 HWSEL: HW6 Mask                  */\r
+#define PORT14_HWSEL_HW7_Pos                  14                                                      /*!< PORT14 HWSEL: HW7 Position              */\r
+#define PORT14_HWSEL_HW7_Msk                  (0x03UL << PORT14_HWSEL_HW7_Pos)                        /*!< PORT14 HWSEL: HW7 Mask                  */\r
+#define PORT14_HWSEL_HW8_Pos                  16                                                      /*!< PORT14 HWSEL: HW8 Position              */\r
+#define PORT14_HWSEL_HW8_Msk                  (0x03UL << PORT14_HWSEL_HW8_Pos)                        /*!< PORT14 HWSEL: HW8 Mask                  */\r
+#define PORT14_HWSEL_HW9_Pos                  18                                                      /*!< PORT14 HWSEL: HW9 Position              */\r
+#define PORT14_HWSEL_HW9_Msk                  (0x03UL << PORT14_HWSEL_HW9_Pos)                        /*!< PORT14 HWSEL: HW9 Mask                  */\r
+#define PORT14_HWSEL_HW10_Pos                 20                                                      /*!< PORT14 HWSEL: HW10 Position             */\r
+#define PORT14_HWSEL_HW10_Msk                 (0x03UL << PORT14_HWSEL_HW10_Pos)                       /*!< PORT14 HWSEL: HW10 Mask                 */\r
+#define PORT14_HWSEL_HW11_Pos                 22                                                      /*!< PORT14 HWSEL: HW11 Position             */\r
+#define PORT14_HWSEL_HW11_Msk                 (0x03UL << PORT14_HWSEL_HW11_Pos)                       /*!< PORT14 HWSEL: HW11 Mask                 */\r
+#define PORT14_HWSEL_HW12_Pos                 24                                                      /*!< PORT14 HWSEL: HW12 Position             */\r
+#define PORT14_HWSEL_HW12_Msk                 (0x03UL << PORT14_HWSEL_HW12_Pos)                       /*!< PORT14 HWSEL: HW12 Mask                 */\r
+#define PORT14_HWSEL_HW13_Pos                 26                                                      /*!< PORT14 HWSEL: HW13 Position             */\r
+#define PORT14_HWSEL_HW13_Msk                 (0x03UL << PORT14_HWSEL_HW13_Pos)                       /*!< PORT14 HWSEL: HW13 Mask                 */\r
+#define PORT14_HWSEL_HW14_Pos                 28                                                      /*!< PORT14 HWSEL: HW14 Position             */\r
+#define PORT14_HWSEL_HW14_Msk                 (0x03UL << PORT14_HWSEL_HW14_Pos)                       /*!< PORT14 HWSEL: HW14 Mask                 */\r
+#define PORT14_HWSEL_HW15_Pos                 30                                                      /*!< PORT14 HWSEL: HW15 Position             */\r
+#define PORT14_HWSEL_HW15_Msk                 (0x03UL << PORT14_HWSEL_HW15_Pos)                       /*!< PORT14 HWSEL: HW15 Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT15' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  PORT15_OUT  --------------------------------- */\r
+#define PORT15_OUT_P0_Pos                     0                                                       /*!< PORT15 OUT: P0 Position                 */\r
+#define PORT15_OUT_P0_Msk                     (0x01UL << PORT15_OUT_P0_Pos)                           /*!< PORT15 OUT: P0 Mask                     */\r
+#define PORT15_OUT_P1_Pos                     1                                                       /*!< PORT15 OUT: P1 Position                 */\r
+#define PORT15_OUT_P1_Msk                     (0x01UL << PORT15_OUT_P1_Pos)                           /*!< PORT15 OUT: P1 Mask                     */\r
+#define PORT15_OUT_P2_Pos                     2                                                       /*!< PORT15 OUT: P2 Position                 */\r
+#define PORT15_OUT_P2_Msk                     (0x01UL << PORT15_OUT_P2_Pos)                           /*!< PORT15 OUT: P2 Mask                     */\r
+#define PORT15_OUT_P3_Pos                     3                                                       /*!< PORT15 OUT: P3 Position                 */\r
+#define PORT15_OUT_P3_Msk                     (0x01UL << PORT15_OUT_P3_Pos)                           /*!< PORT15 OUT: P3 Mask                     */\r
+#define PORT15_OUT_P4_Pos                     4                                                       /*!< PORT15 OUT: P4 Position                 */\r
+#define PORT15_OUT_P4_Msk                     (0x01UL << PORT15_OUT_P4_Pos)                           /*!< PORT15 OUT: P4 Mask                     */\r
+#define PORT15_OUT_P5_Pos                     5                                                       /*!< PORT15 OUT: P5 Position                 */\r
+#define PORT15_OUT_P5_Msk                     (0x01UL << PORT15_OUT_P5_Pos)                           /*!< PORT15 OUT: P5 Mask                     */\r
+#define PORT15_OUT_P6_Pos                     6                                                       /*!< PORT15 OUT: P6 Position                 */\r
+#define PORT15_OUT_P6_Msk                     (0x01UL << PORT15_OUT_P6_Pos)                           /*!< PORT15 OUT: P6 Mask                     */\r
+#define PORT15_OUT_P7_Pos                     7                                                       /*!< PORT15 OUT: P7 Position                 */\r
+#define PORT15_OUT_P7_Msk                     (0x01UL << PORT15_OUT_P7_Pos)                           /*!< PORT15 OUT: P7 Mask                     */\r
+#define PORT15_OUT_P8_Pos                     8                                                       /*!< PORT15 OUT: P8 Position                 */\r
+#define PORT15_OUT_P8_Msk                     (0x01UL << PORT15_OUT_P8_Pos)                           /*!< PORT15 OUT: P8 Mask                     */\r
+#define PORT15_OUT_P9_Pos                     9                                                       /*!< PORT15 OUT: P9 Position                 */\r
+#define PORT15_OUT_P9_Msk                     (0x01UL << PORT15_OUT_P9_Pos)                           /*!< PORT15 OUT: P9 Mask                     */\r
+#define PORT15_OUT_P10_Pos                    10                                                      /*!< PORT15 OUT: P10 Position                */\r
+#define PORT15_OUT_P10_Msk                    (0x01UL << PORT15_OUT_P10_Pos)                          /*!< PORT15 OUT: P10 Mask                    */\r
+#define PORT15_OUT_P11_Pos                    11                                                      /*!< PORT15 OUT: P11 Position                */\r
+#define PORT15_OUT_P11_Msk                    (0x01UL << PORT15_OUT_P11_Pos)                          /*!< PORT15 OUT: P11 Mask                    */\r
+#define PORT15_OUT_P12_Pos                    12                                                      /*!< PORT15 OUT: P12 Position                */\r
+#define PORT15_OUT_P12_Msk                    (0x01UL << PORT15_OUT_P12_Pos)                          /*!< PORT15 OUT: P12 Mask                    */\r
+#define PORT15_OUT_P13_Pos                    13                                                      /*!< PORT15 OUT: P13 Position                */\r
+#define PORT15_OUT_P13_Msk                    (0x01UL << PORT15_OUT_P13_Pos)                          /*!< PORT15 OUT: P13 Mask                    */\r
+#define PORT15_OUT_P14_Pos                    14                                                      /*!< PORT15 OUT: P14 Position                */\r
+#define PORT15_OUT_P14_Msk                    (0x01UL << PORT15_OUT_P14_Pos)                          /*!< PORT15 OUT: P14 Mask                    */\r
+#define PORT15_OUT_P15_Pos                    15                                                      /*!< PORT15 OUT: P15 Position                */\r
+#define PORT15_OUT_P15_Msk                    (0x01UL << PORT15_OUT_P15_Pos)                          /*!< PORT15 OUT: P15 Mask                    */\r
+\r
+/* ---------------------------------  PORT15_OMR  --------------------------------- */\r
+#define PORT15_OMR_PS0_Pos                    0                                                       /*!< PORT15 OMR: PS0 Position                */\r
+#define PORT15_OMR_PS0_Msk                    (0x01UL << PORT15_OMR_PS0_Pos)                          /*!< PORT15 OMR: PS0 Mask                    */\r
+#define PORT15_OMR_PS1_Pos                    1                                                       /*!< PORT15 OMR: PS1 Position                */\r
+#define PORT15_OMR_PS1_Msk                    (0x01UL << PORT15_OMR_PS1_Pos)                          /*!< PORT15 OMR: PS1 Mask                    */\r
+#define PORT15_OMR_PS2_Pos                    2                                                       /*!< PORT15 OMR: PS2 Position                */\r
+#define PORT15_OMR_PS2_Msk                    (0x01UL << PORT15_OMR_PS2_Pos)                          /*!< PORT15 OMR: PS2 Mask                    */\r
+#define PORT15_OMR_PS3_Pos                    3                                                       /*!< PORT15 OMR: PS3 Position                */\r
+#define PORT15_OMR_PS3_Msk                    (0x01UL << PORT15_OMR_PS3_Pos)                          /*!< PORT15 OMR: PS3 Mask                    */\r
+#define PORT15_OMR_PS4_Pos                    4                                                       /*!< PORT15 OMR: PS4 Position                */\r
+#define PORT15_OMR_PS4_Msk                    (0x01UL << PORT15_OMR_PS4_Pos)                          /*!< PORT15 OMR: PS4 Mask                    */\r
+#define PORT15_OMR_PS5_Pos                    5                                                       /*!< PORT15 OMR: PS5 Position                */\r
+#define PORT15_OMR_PS5_Msk                    (0x01UL << PORT15_OMR_PS5_Pos)                          /*!< PORT15 OMR: PS5 Mask                    */\r
+#define PORT15_OMR_PS6_Pos                    6                                                       /*!< PORT15 OMR: PS6 Position                */\r
+#define PORT15_OMR_PS6_Msk                    (0x01UL << PORT15_OMR_PS6_Pos)                          /*!< PORT15 OMR: PS6 Mask                    */\r
+#define PORT15_OMR_PS7_Pos                    7                                                       /*!< PORT15 OMR: PS7 Position                */\r
+#define PORT15_OMR_PS7_Msk                    (0x01UL << PORT15_OMR_PS7_Pos)                          /*!< PORT15 OMR: PS7 Mask                    */\r
+#define PORT15_OMR_PS8_Pos                    8                                                       /*!< PORT15 OMR: PS8 Position                */\r
+#define PORT15_OMR_PS8_Msk                    (0x01UL << PORT15_OMR_PS8_Pos)                          /*!< PORT15 OMR: PS8 Mask                    */\r
+#define PORT15_OMR_PS9_Pos                    9                                                       /*!< PORT15 OMR: PS9 Position                */\r
+#define PORT15_OMR_PS9_Msk                    (0x01UL << PORT15_OMR_PS9_Pos)                          /*!< PORT15 OMR: PS9 Mask                    */\r
+#define PORT15_OMR_PS10_Pos                   10                                                      /*!< PORT15 OMR: PS10 Position               */\r
+#define PORT15_OMR_PS10_Msk                   (0x01UL << PORT15_OMR_PS10_Pos)                         /*!< PORT15 OMR: PS10 Mask                   */\r
+#define PORT15_OMR_PS11_Pos                   11                                                      /*!< PORT15 OMR: PS11 Position               */\r
+#define PORT15_OMR_PS11_Msk                   (0x01UL << PORT15_OMR_PS11_Pos)                         /*!< PORT15 OMR: PS11 Mask                   */\r
+#define PORT15_OMR_PS12_Pos                   12                                                      /*!< PORT15 OMR: PS12 Position               */\r
+#define PORT15_OMR_PS12_Msk                   (0x01UL << PORT15_OMR_PS12_Pos)                         /*!< PORT15 OMR: PS12 Mask                   */\r
+#define PORT15_OMR_PS13_Pos                   13                                                      /*!< PORT15 OMR: PS13 Position               */\r
+#define PORT15_OMR_PS13_Msk                   (0x01UL << PORT15_OMR_PS13_Pos)                         /*!< PORT15 OMR: PS13 Mask                   */\r
+#define PORT15_OMR_PS14_Pos                   14                                                      /*!< PORT15 OMR: PS14 Position               */\r
+#define PORT15_OMR_PS14_Msk                   (0x01UL << PORT15_OMR_PS14_Pos)                         /*!< PORT15 OMR: PS14 Mask                   */\r
+#define PORT15_OMR_PS15_Pos                   15                                                      /*!< PORT15 OMR: PS15 Position               */\r
+#define PORT15_OMR_PS15_Msk                   (0x01UL << PORT15_OMR_PS15_Pos)                         /*!< PORT15 OMR: PS15 Mask                   */\r
+#define PORT15_OMR_PR0_Pos                    16                                                      /*!< PORT15 OMR: PR0 Position                */\r
+#define PORT15_OMR_PR0_Msk                    (0x01UL << PORT15_OMR_PR0_Pos)                          /*!< PORT15 OMR: PR0 Mask                    */\r
+#define PORT15_OMR_PR1_Pos                    17                                                      /*!< PORT15 OMR: PR1 Position                */\r
+#define PORT15_OMR_PR1_Msk                    (0x01UL << PORT15_OMR_PR1_Pos)                          /*!< PORT15 OMR: PR1 Mask                    */\r
+#define PORT15_OMR_PR2_Pos                    18                                                      /*!< PORT15 OMR: PR2 Position                */\r
+#define PORT15_OMR_PR2_Msk                    (0x01UL << PORT15_OMR_PR2_Pos)                          /*!< PORT15 OMR: PR2 Mask                    */\r
+#define PORT15_OMR_PR3_Pos                    19                                                      /*!< PORT15 OMR: PR3 Position                */\r
+#define PORT15_OMR_PR3_Msk                    (0x01UL << PORT15_OMR_PR3_Pos)                          /*!< PORT15 OMR: PR3 Mask                    */\r
+#define PORT15_OMR_PR4_Pos                    20                                                      /*!< PORT15 OMR: PR4 Position                */\r
+#define PORT15_OMR_PR4_Msk                    (0x01UL << PORT15_OMR_PR4_Pos)                          /*!< PORT15 OMR: PR4 Mask                    */\r
+#define PORT15_OMR_PR5_Pos                    21                                                      /*!< PORT15 OMR: PR5 Position                */\r
+#define PORT15_OMR_PR5_Msk                    (0x01UL << PORT15_OMR_PR5_Pos)                          /*!< PORT15 OMR: PR5 Mask                    */\r
+#define PORT15_OMR_PR6_Pos                    22                                                      /*!< PORT15 OMR: PR6 Position                */\r
+#define PORT15_OMR_PR6_Msk                    (0x01UL << PORT15_OMR_PR6_Pos)                          /*!< PORT15 OMR: PR6 Mask                    */\r
+#define PORT15_OMR_PR7_Pos                    23                                                      /*!< PORT15 OMR: PR7 Position                */\r
+#define PORT15_OMR_PR7_Msk                    (0x01UL << PORT15_OMR_PR7_Pos)                          /*!< PORT15 OMR: PR7 Mask                    */\r
+#define PORT15_OMR_PR8_Pos                    24                                                      /*!< PORT15 OMR: PR8 Position                */\r
+#define PORT15_OMR_PR8_Msk                    (0x01UL << PORT15_OMR_PR8_Pos)                          /*!< PORT15 OMR: PR8 Mask                    */\r
+#define PORT15_OMR_PR9_Pos                    25                                                      /*!< PORT15 OMR: PR9 Position                */\r
+#define PORT15_OMR_PR9_Msk                    (0x01UL << PORT15_OMR_PR9_Pos)                          /*!< PORT15 OMR: PR9 Mask                    */\r
+#define PORT15_OMR_PR10_Pos                   26                                                      /*!< PORT15 OMR: PR10 Position               */\r
+#define PORT15_OMR_PR10_Msk                   (0x01UL << PORT15_OMR_PR10_Pos)                         /*!< PORT15 OMR: PR10 Mask                   */\r
+#define PORT15_OMR_PR11_Pos                   27                                                      /*!< PORT15 OMR: PR11 Position               */\r
+#define PORT15_OMR_PR11_Msk                   (0x01UL << PORT15_OMR_PR11_Pos)                         /*!< PORT15 OMR: PR11 Mask                   */\r
+#define PORT15_OMR_PR12_Pos                   28                                                      /*!< PORT15 OMR: PR12 Position               */\r
+#define PORT15_OMR_PR12_Msk                   (0x01UL << PORT15_OMR_PR12_Pos)                         /*!< PORT15 OMR: PR12 Mask                   */\r
+#define PORT15_OMR_PR13_Pos                   29                                                      /*!< PORT15 OMR: PR13 Position               */\r
+#define PORT15_OMR_PR13_Msk                   (0x01UL << PORT15_OMR_PR13_Pos)                         /*!< PORT15 OMR: PR13 Mask                   */\r
+#define PORT15_OMR_PR14_Pos                   30                                                      /*!< PORT15 OMR: PR14 Position               */\r
+#define PORT15_OMR_PR14_Msk                   (0x01UL << PORT15_OMR_PR14_Pos)                         /*!< PORT15 OMR: PR14 Mask                   */\r
+#define PORT15_OMR_PR15_Pos                   31                                                      /*!< PORT15 OMR: PR15 Position               */\r
+#define PORT15_OMR_PR15_Msk                   (0x01UL << PORT15_OMR_PR15_Pos)                         /*!< PORT15 OMR: PR15 Mask                   */\r
+\r
+/* --------------------------------  PORT15_IOCR0  -------------------------------- */\r
+#define PORT15_IOCR0_PC0_Pos                  3                                                       /*!< PORT15 IOCR0: PC0 Position              */\r
+#define PORT15_IOCR0_PC0_Msk                  (0x1fUL << PORT15_IOCR0_PC0_Pos)                        /*!< PORT15 IOCR0: PC0 Mask                  */\r
+#define PORT15_IOCR0_PC1_Pos                  11                                                      /*!< PORT15 IOCR0: PC1 Position              */\r
+#define PORT15_IOCR0_PC1_Msk                  (0x1fUL << PORT15_IOCR0_PC1_Pos)                        /*!< PORT15 IOCR0: PC1 Mask                  */\r
+#define PORT15_IOCR0_PC2_Pos                  19                                                      /*!< PORT15 IOCR0: PC2 Position              */\r
+#define PORT15_IOCR0_PC2_Msk                  (0x1fUL << PORT15_IOCR0_PC2_Pos)                        /*!< PORT15 IOCR0: PC2 Mask                  */\r
+#define PORT15_IOCR0_PC3_Pos                  27                                                      /*!< PORT15 IOCR0: PC3 Position              */\r
+#define PORT15_IOCR0_PC3_Msk                  (0x1fUL << PORT15_IOCR0_PC3_Pos)                        /*!< PORT15 IOCR0: PC3 Mask                  */\r
+\r
+/* --------------------------------  PORT15_IOCR4  -------------------------------- */\r
+#define PORT15_IOCR4_PC4_Pos                  3                                                       /*!< PORT15 IOCR4: PC4 Position              */\r
+#define PORT15_IOCR4_PC4_Msk                  (0x1fUL << PORT15_IOCR4_PC4_Pos)                        /*!< PORT15 IOCR4: PC4 Mask                  */\r
+#define PORT15_IOCR4_PC5_Pos                  11                                                      /*!< PORT15 IOCR4: PC5 Position              */\r
+#define PORT15_IOCR4_PC5_Msk                  (0x1fUL << PORT15_IOCR4_PC5_Pos)                        /*!< PORT15 IOCR4: PC5 Mask                  */\r
+#define PORT15_IOCR4_PC6_Pos                  19                                                      /*!< PORT15 IOCR4: PC6 Position              */\r
+#define PORT15_IOCR4_PC6_Msk                  (0x1fUL << PORT15_IOCR4_PC6_Pos)                        /*!< PORT15 IOCR4: PC6 Mask                  */\r
+#define PORT15_IOCR4_PC7_Pos                  27                                                      /*!< PORT15 IOCR4: PC7 Position              */\r
+#define PORT15_IOCR4_PC7_Msk                  (0x1fUL << PORT15_IOCR4_PC7_Pos)                        /*!< PORT15 IOCR4: PC7 Mask                  */\r
+\r
+/* --------------------------------  PORT15_IOCR8  -------------------------------- */\r
+#define PORT15_IOCR8_PC8_Pos                  3                                                       /*!< PORT15 IOCR8: PC8 Position              */\r
+#define PORT15_IOCR8_PC8_Msk                  (0x1fUL << PORT15_IOCR8_PC8_Pos)                        /*!< PORT15 IOCR8: PC8 Mask                  */\r
+#define PORT15_IOCR8_PC9_Pos                  11                                                      /*!< PORT15 IOCR8: PC9 Position              */\r
+#define PORT15_IOCR8_PC9_Msk                  (0x1fUL << PORT15_IOCR8_PC9_Pos)                        /*!< PORT15 IOCR8: PC9 Mask                  */\r
+#define PORT15_IOCR8_PC10_Pos                 19                                                      /*!< PORT15 IOCR8: PC10 Position             */\r
+#define PORT15_IOCR8_PC10_Msk                 (0x1fUL << PORT15_IOCR8_PC10_Pos)                       /*!< PORT15 IOCR8: PC10 Mask                 */\r
+#define PORT15_IOCR8_PC11_Pos                 27                                                      /*!< PORT15 IOCR8: PC11 Position             */\r
+#define PORT15_IOCR8_PC11_Msk                 (0x1fUL << PORT15_IOCR8_PC11_Pos)                       /*!< PORT15 IOCR8: PC11 Mask                 */\r
+\r
+/* ----------------------------------  PORT15_IN  --------------------------------- */\r
+#define PORT15_IN_P0_Pos                      0                                                       /*!< PORT15 IN: P0 Position                  */\r
+#define PORT15_IN_P0_Msk                      (0x01UL << PORT15_IN_P0_Pos)                            /*!< PORT15 IN: P0 Mask                      */\r
+#define PORT15_IN_P1_Pos                      1                                                       /*!< PORT15 IN: P1 Position                  */\r
+#define PORT15_IN_P1_Msk                      (0x01UL << PORT15_IN_P1_Pos)                            /*!< PORT15 IN: P1 Mask                      */\r
+#define PORT15_IN_P2_Pos                      2                                                       /*!< PORT15 IN: P2 Position                  */\r
+#define PORT15_IN_P2_Msk                      (0x01UL << PORT15_IN_P2_Pos)                            /*!< PORT15 IN: P2 Mask                      */\r
+#define PORT15_IN_P3_Pos                      3                                                       /*!< PORT15 IN: P3 Position                  */\r
+#define PORT15_IN_P3_Msk                      (0x01UL << PORT15_IN_P3_Pos)                            /*!< PORT15 IN: P3 Mask                      */\r
+#define PORT15_IN_P4_Pos                      4                                                       /*!< PORT15 IN: P4 Position                  */\r
+#define PORT15_IN_P4_Msk                      (0x01UL << PORT15_IN_P4_Pos)                            /*!< PORT15 IN: P4 Mask                      */\r
+#define PORT15_IN_P5_Pos                      5                                                       /*!< PORT15 IN: P5 Position                  */\r
+#define PORT15_IN_P5_Msk                      (0x01UL << PORT15_IN_P5_Pos)                            /*!< PORT15 IN: P5 Mask                      */\r
+#define PORT15_IN_P6_Pos                      6                                                       /*!< PORT15 IN: P6 Position                  */\r
+#define PORT15_IN_P6_Msk                      (0x01UL << PORT15_IN_P6_Pos)                            /*!< PORT15 IN: P6 Mask                      */\r
+#define PORT15_IN_P7_Pos                      7                                                       /*!< PORT15 IN: P7 Position                  */\r
+#define PORT15_IN_P7_Msk                      (0x01UL << PORT15_IN_P7_Pos)                            /*!< PORT15 IN: P7 Mask                      */\r
+#define PORT15_IN_P8_Pos                      8                                                       /*!< PORT15 IN: P8 Position                  */\r
+#define PORT15_IN_P8_Msk                      (0x01UL << PORT15_IN_P8_Pos)                            /*!< PORT15 IN: P8 Mask                      */\r
+#define PORT15_IN_P9_Pos                      9                                                       /*!< PORT15 IN: P9 Position                  */\r
+#define PORT15_IN_P9_Msk                      (0x01UL << PORT15_IN_P9_Pos)                            /*!< PORT15 IN: P9 Mask                      */\r
+#define PORT15_IN_P10_Pos                     10                                                      /*!< PORT15 IN: P10 Position                 */\r
+#define PORT15_IN_P10_Msk                     (0x01UL << PORT15_IN_P10_Pos)                           /*!< PORT15 IN: P10 Mask                     */\r
+#define PORT15_IN_P11_Pos                     11                                                      /*!< PORT15 IN: P11 Position                 */\r
+#define PORT15_IN_P11_Msk                     (0x01UL << PORT15_IN_P11_Pos)                           /*!< PORT15 IN: P11 Mask                     */\r
+#define PORT15_IN_P12_Pos                     12                                                      /*!< PORT15 IN: P12 Position                 */\r
+#define PORT15_IN_P12_Msk                     (0x01UL << PORT15_IN_P12_Pos)                           /*!< PORT15 IN: P12 Mask                     */\r
+#define PORT15_IN_P13_Pos                     13                                                      /*!< PORT15 IN: P13 Position                 */\r
+#define PORT15_IN_P13_Msk                     (0x01UL << PORT15_IN_P13_Pos)                           /*!< PORT15 IN: P13 Mask                     */\r
+#define PORT15_IN_P14_Pos                     14                                                      /*!< PORT15 IN: P14 Position                 */\r
+#define PORT15_IN_P14_Msk                     (0x01UL << PORT15_IN_P14_Pos)                           /*!< PORT15 IN: P14 Mask                     */\r
+#define PORT15_IN_P15_Pos                     15                                                      /*!< PORT15 IN: P15 Position                 */\r
+#define PORT15_IN_P15_Msk                     (0x01UL << PORT15_IN_P15_Pos)                           /*!< PORT15 IN: P15 Mask                     */\r
+\r
+/* --------------------------------  PORT15_PDISC  -------------------------------- */\r
+#define PORT15_PDISC_PDIS0_Pos                0                                                       /*!< PORT15 PDISC: PDIS0 Position            */\r
+#define PORT15_PDISC_PDIS0_Msk                (0x01UL << PORT15_PDISC_PDIS0_Pos)                      /*!< PORT15 PDISC: PDIS0 Mask                */\r
+#define PORT15_PDISC_PDIS1_Pos                1                                                       /*!< PORT15 PDISC: PDIS1 Position            */\r
+#define PORT15_PDISC_PDIS1_Msk                (0x01UL << PORT15_PDISC_PDIS1_Pos)                      /*!< PORT15 PDISC: PDIS1 Mask                */\r
+#define PORT15_PDISC_PDIS2_Pos                2                                                       /*!< PORT15 PDISC: PDIS2 Position            */\r
+#define PORT15_PDISC_PDIS2_Msk                (0x01UL << PORT15_PDISC_PDIS2_Pos)                      /*!< PORT15 PDISC: PDIS2 Mask                */\r
+#define PORT15_PDISC_PDIS3_Pos                3                                                       /*!< PORT15 PDISC: PDIS3 Position            */\r
+#define PORT15_PDISC_PDIS3_Msk                (0x01UL << PORT15_PDISC_PDIS3_Pos)                      /*!< PORT15 PDISC: PDIS3 Mask                */\r
+#define PORT15_PDISC_PDIS4_Pos                4                                                       /*!< PORT15 PDISC: PDIS4 Position            */\r
+#define PORT15_PDISC_PDIS4_Msk                (0x01UL << PORT15_PDISC_PDIS4_Pos)                      /*!< PORT15 PDISC: PDIS4 Mask                */\r
+#define PORT15_PDISC_PDIS5_Pos                5                                                       /*!< PORT15 PDISC: PDIS5 Position            */\r
+#define PORT15_PDISC_PDIS5_Msk                (0x01UL << PORT15_PDISC_PDIS5_Pos)                      /*!< PORT15 PDISC: PDIS5 Mask                */\r
+#define PORT15_PDISC_PDIS6_Pos                6                                                       /*!< PORT15 PDISC: PDIS6 Position            */\r
+#define PORT15_PDISC_PDIS6_Msk                (0x01UL << PORT15_PDISC_PDIS6_Pos)                      /*!< PORT15 PDISC: PDIS6 Mask                */\r
+#define PORT15_PDISC_PDIS7_Pos                7                                                       /*!< PORT15 PDISC: PDIS7 Position            */\r
+#define PORT15_PDISC_PDIS7_Msk                (0x01UL << PORT15_PDISC_PDIS7_Pos)                      /*!< PORT15 PDISC: PDIS7 Mask                */\r
+#define PORT15_PDISC_PDIS8_Pos                8                                                       /*!< PORT15 PDISC: PDIS8 Position            */\r
+#define PORT15_PDISC_PDIS8_Msk                (0x01UL << PORT15_PDISC_PDIS8_Pos)                      /*!< PORT15 PDISC: PDIS8 Mask                */\r
+#define PORT15_PDISC_PDIS9_Pos                9                                                       /*!< PORT15 PDISC: PDIS9 Position            */\r
+#define PORT15_PDISC_PDIS9_Msk                (0x01UL << PORT15_PDISC_PDIS9_Pos)                      /*!< PORT15 PDISC: PDIS9 Mask                */\r
+#define PORT15_PDISC_PDIS10_Pos               10                                                      /*!< PORT15 PDISC: PDIS10 Position           */\r
+#define PORT15_PDISC_PDIS10_Msk               (0x01UL << PORT15_PDISC_PDIS10_Pos)                     /*!< PORT15 PDISC: PDIS10 Mask               */\r
+#define PORT15_PDISC_PDIS11_Pos               11                                                      /*!< PORT15 PDISC: PDIS11 Position           */\r
+#define PORT15_PDISC_PDIS11_Msk               (0x01UL << PORT15_PDISC_PDIS11_Pos)                     /*!< PORT15 PDISC: PDIS11 Mask               */\r
+#define PORT15_PDISC_PDIS12_Pos               12                                                      /*!< PORT15 PDISC: PDIS12 Position           */\r
+#define PORT15_PDISC_PDIS12_Msk               (0x01UL << PORT15_PDISC_PDIS12_Pos)                     /*!< PORT15 PDISC: PDIS12 Mask               */\r
+#define PORT15_PDISC_PDIS13_Pos               13                                                      /*!< PORT15 PDISC: PDIS13 Position           */\r
+#define PORT15_PDISC_PDIS13_Msk               (0x01UL << PORT15_PDISC_PDIS13_Pos)                     /*!< PORT15 PDISC: PDIS13 Mask               */\r
+#define PORT15_PDISC_PDIS14_Pos               14                                                      /*!< PORT15 PDISC: PDIS14 Position           */\r
+#define PORT15_PDISC_PDIS14_Msk               (0x01UL << PORT15_PDISC_PDIS14_Pos)                     /*!< PORT15 PDISC: PDIS14 Mask               */\r
+#define PORT15_PDISC_PDIS15_Pos               15                                                      /*!< PORT15 PDISC: PDIS15 Position           */\r
+#define PORT15_PDISC_PDIS15_Msk               (0x01UL << PORT15_PDISC_PDIS15_Pos)                     /*!< PORT15 PDISC: PDIS15 Mask               */\r
+\r
+/* ---------------------------------  PORT15_PPS  --------------------------------- */\r
+#define PORT15_PPS_PPS0_Pos                   0                                                       /*!< PORT15 PPS: PPS0 Position               */\r
+#define PORT15_PPS_PPS0_Msk                   (0x01UL << PORT15_PPS_PPS0_Pos)                         /*!< PORT15 PPS: PPS0 Mask                   */\r
+#define PORT15_PPS_PPS1_Pos                   1                                                       /*!< PORT15 PPS: PPS1 Position               */\r
+#define PORT15_PPS_PPS1_Msk                   (0x01UL << PORT15_PPS_PPS1_Pos)                         /*!< PORT15 PPS: PPS1 Mask                   */\r
+#define PORT15_PPS_PPS2_Pos                   2                                                       /*!< PORT15 PPS: PPS2 Position               */\r
+#define PORT15_PPS_PPS2_Msk                   (0x01UL << PORT15_PPS_PPS2_Pos)                         /*!< PORT15 PPS: PPS2 Mask                   */\r
+#define PORT15_PPS_PPS3_Pos                   3                                                       /*!< PORT15 PPS: PPS3 Position               */\r
+#define PORT15_PPS_PPS3_Msk                   (0x01UL << PORT15_PPS_PPS3_Pos)                         /*!< PORT15 PPS: PPS3 Mask                   */\r
+#define PORT15_PPS_PPS4_Pos                   4                                                       /*!< PORT15 PPS: PPS4 Position               */\r
+#define PORT15_PPS_PPS4_Msk                   (0x01UL << PORT15_PPS_PPS4_Pos)                         /*!< PORT15 PPS: PPS4 Mask                   */\r
+#define PORT15_PPS_PPS5_Pos                   5                                                       /*!< PORT15 PPS: PPS5 Position               */\r
+#define PORT15_PPS_PPS5_Msk                   (0x01UL << PORT15_PPS_PPS5_Pos)                         /*!< PORT15 PPS: PPS5 Mask                   */\r
+#define PORT15_PPS_PPS6_Pos                   6                                                       /*!< PORT15 PPS: PPS6 Position               */\r
+#define PORT15_PPS_PPS6_Msk                   (0x01UL << PORT15_PPS_PPS6_Pos)                         /*!< PORT15 PPS: PPS6 Mask                   */\r
+#define PORT15_PPS_PPS7_Pos                   7                                                       /*!< PORT15 PPS: PPS7 Position               */\r
+#define PORT15_PPS_PPS7_Msk                   (0x01UL << PORT15_PPS_PPS7_Pos)                         /*!< PORT15 PPS: PPS7 Mask                   */\r
+#define PORT15_PPS_PPS8_Pos                   8                                                       /*!< PORT15 PPS: PPS8 Position               */\r
+#define PORT15_PPS_PPS8_Msk                   (0x01UL << PORT15_PPS_PPS8_Pos)                         /*!< PORT15 PPS: PPS8 Mask                   */\r
+#define PORT15_PPS_PPS9_Pos                   9                                                       /*!< PORT15 PPS: PPS9 Position               */\r
+#define PORT15_PPS_PPS9_Msk                   (0x01UL << PORT15_PPS_PPS9_Pos)                         /*!< PORT15 PPS: PPS9 Mask                   */\r
+#define PORT15_PPS_PPS10_Pos                  10                                                      /*!< PORT15 PPS: PPS10 Position              */\r
+#define PORT15_PPS_PPS10_Msk                  (0x01UL << PORT15_PPS_PPS10_Pos)                        /*!< PORT15 PPS: PPS10 Mask                  */\r
+#define PORT15_PPS_PPS11_Pos                  11                                                      /*!< PORT15 PPS: PPS11 Position              */\r
+#define PORT15_PPS_PPS11_Msk                  (0x01UL << PORT15_PPS_PPS11_Pos)                        /*!< PORT15 PPS: PPS11 Mask                  */\r
+#define PORT15_PPS_PPS12_Pos                  12                                                      /*!< PORT15 PPS: PPS12 Position              */\r
+#define PORT15_PPS_PPS12_Msk                  (0x01UL << PORT15_PPS_PPS12_Pos)                        /*!< PORT15 PPS: PPS12 Mask                  */\r
+#define PORT15_PPS_PPS13_Pos                  13                                                      /*!< PORT15 PPS: PPS13 Position              */\r
+#define PORT15_PPS_PPS13_Msk                  (0x01UL << PORT15_PPS_PPS13_Pos)                        /*!< PORT15 PPS: PPS13 Mask                  */\r
+#define PORT15_PPS_PPS14_Pos                  14                                                      /*!< PORT15 PPS: PPS14 Position              */\r
+#define PORT15_PPS_PPS14_Msk                  (0x01UL << PORT15_PPS_PPS14_Pos)                        /*!< PORT15 PPS: PPS14 Mask                  */\r
+#define PORT15_PPS_PPS15_Pos                  15                                                      /*!< PORT15 PPS: PPS15 Position              */\r
+#define PORT15_PPS_PPS15_Msk                  (0x01UL << PORT15_PPS_PPS15_Pos)                        /*!< PORT15 PPS: PPS15 Mask                  */\r
+\r
+/* --------------------------------  PORT15_HWSEL  -------------------------------- */\r
+#define PORT15_HWSEL_HW0_Pos                  0                                                       /*!< PORT15 HWSEL: HW0 Position              */\r
+#define PORT15_HWSEL_HW0_Msk                  (0x03UL << PORT15_HWSEL_HW0_Pos)                        /*!< PORT15 HWSEL: HW0 Mask                  */\r
+#define PORT15_HWSEL_HW1_Pos                  2                                                       /*!< PORT15 HWSEL: HW1 Position              */\r
+#define PORT15_HWSEL_HW1_Msk                  (0x03UL << PORT15_HWSEL_HW1_Pos)                        /*!< PORT15 HWSEL: HW1 Mask                  */\r
+#define PORT15_HWSEL_HW2_Pos                  4                                                       /*!< PORT15 HWSEL: HW2 Position              */\r
+#define PORT15_HWSEL_HW2_Msk                  (0x03UL << PORT15_HWSEL_HW2_Pos)                        /*!< PORT15 HWSEL: HW2 Mask                  */\r
+#define PORT15_HWSEL_HW3_Pos                  6                                                       /*!< PORT15 HWSEL: HW3 Position              */\r
+#define PORT15_HWSEL_HW3_Msk                  (0x03UL << PORT15_HWSEL_HW3_Pos)                        /*!< PORT15 HWSEL: HW3 Mask                  */\r
+#define PORT15_HWSEL_HW4_Pos                  8                                                       /*!< PORT15 HWSEL: HW4 Position              */\r
+#define PORT15_HWSEL_HW4_Msk                  (0x03UL << PORT15_HWSEL_HW4_Pos)                        /*!< PORT15 HWSEL: HW4 Mask                  */\r
+#define PORT15_HWSEL_HW5_Pos                  10                                                      /*!< PORT15 HWSEL: HW5 Position              */\r
+#define PORT15_HWSEL_HW5_Msk                  (0x03UL << PORT15_HWSEL_HW5_Pos)                        /*!< PORT15 HWSEL: HW5 Mask                  */\r
+#define PORT15_HWSEL_HW6_Pos                  12                                                      /*!< PORT15 HWSEL: HW6 Position              */\r
+#define PORT15_HWSEL_HW6_Msk                  (0x03UL << PORT15_HWSEL_HW6_Pos)                        /*!< PORT15 HWSEL: HW6 Mask                  */\r
+#define PORT15_HWSEL_HW7_Pos                  14                                                      /*!< PORT15 HWSEL: HW7 Position              */\r
+#define PORT15_HWSEL_HW7_Msk                  (0x03UL << PORT15_HWSEL_HW7_Pos)                        /*!< PORT15 HWSEL: HW7 Mask                  */\r
+#define PORT15_HWSEL_HW8_Pos                  16                                                      /*!< PORT15 HWSEL: HW8 Position              */\r
+#define PORT15_HWSEL_HW8_Msk                  (0x03UL << PORT15_HWSEL_HW8_Pos)                        /*!< PORT15 HWSEL: HW8 Mask                  */\r
+#define PORT15_HWSEL_HW9_Pos                  18                                                      /*!< PORT15 HWSEL: HW9 Position              */\r
+#define PORT15_HWSEL_HW9_Msk                  (0x03UL << PORT15_HWSEL_HW9_Pos)                        /*!< PORT15 HWSEL: HW9 Mask                  */\r
+#define PORT15_HWSEL_HW10_Pos                 20                                                      /*!< PORT15 HWSEL: HW10 Position             */\r
+#define PORT15_HWSEL_HW10_Msk                 (0x03UL << PORT15_HWSEL_HW10_Pos)                       /*!< PORT15 HWSEL: HW10 Mask                 */\r
+#define PORT15_HWSEL_HW11_Pos                 22                                                      /*!< PORT15 HWSEL: HW11 Position             */\r
+#define PORT15_HWSEL_HW11_Msk                 (0x03UL << PORT15_HWSEL_HW11_Pos)                       /*!< PORT15 HWSEL: HW11 Mask                 */\r
+#define PORT15_HWSEL_HW12_Pos                 24                                                      /*!< PORT15 HWSEL: HW12 Position             */\r
+#define PORT15_HWSEL_HW12_Msk                 (0x03UL << PORT15_HWSEL_HW12_Pos)                       /*!< PORT15 HWSEL: HW12 Mask                 */\r
+#define PORT15_HWSEL_HW13_Pos                 26                                                      /*!< PORT15 HWSEL: HW13 Position             */\r
+#define PORT15_HWSEL_HW13_Msk                 (0x03UL << PORT15_HWSEL_HW13_Pos)                       /*!< PORT15 HWSEL: HW13 Mask                 */\r
+#define PORT15_HWSEL_HW14_Pos                 28                                                      /*!< PORT15 HWSEL: HW14 Position             */\r
+#define PORT15_HWSEL_HW14_Msk                 (0x03UL << PORT15_HWSEL_HW14_Pos)                       /*!< PORT15 HWSEL: HW14 Mask                 */\r
+#define PORT15_HWSEL_HW15_Pos                 30                                                      /*!< PORT15 HWSEL: HW15 Position             */\r
+#define PORT15_HWSEL_HW15_Msk                 (0x03UL << PORT15_HWSEL_HW15_Pos)                       /*!< PORT15 HWSEL: HW15 Mask                 */\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              Peripheral memory map             ================ */\r
+/* ================================================================================ */\r
+\r
+#define PPB_BASE                        0xE000E000UL\r
+#define DLR_BASE                        0x50004900UL\r
+#define ERU0_BASE                       0x50004800UL\r
+#define ERU1_BASE                       0x40044000UL\r
+#define GPDMA0_BASE                     0x500142C0UL\r
+#define GPDMA0_CH0_BASE                 0x50014000UL\r
+#define GPDMA0_CH1_BASE                 0x50014058UL\r
+#define GPDMA0_CH2_BASE                 0x500140B0UL\r
+#define GPDMA0_CH3_BASE                 0x50014108UL\r
+#define GPDMA0_CH4_BASE                 0x50014160UL\r
+#define GPDMA0_CH5_BASE                 0x500141B8UL\r
+#define GPDMA0_CH6_BASE                 0x50014210UL\r
+#define GPDMA0_CH7_BASE                 0x50014268UL\r
+#define FCE_BASE                        0x50020000UL\r
+#define FCE_KE0_BASE                    0x50020020UL\r
+#define FCE_KE1_BASE                    0x50020040UL\r
+#define FCE_KE2_BASE                    0x50020060UL\r
+#define FCE_KE3_BASE                    0x50020080UL\r
+#define PBA0_BASE                       0x40000000UL\r
+#define PBA1_BASE                       0x48000000UL\r
+#define FLASH0_BASE                     0x58001000UL\r
+#define PREF_BASE                       0x58004000UL\r
+#define PMU0_BASE                       0x58000508UL\r
+#define WDT_BASE                        0x50008000UL\r
+#define RTC_BASE                        0x50004A00UL\r
+#define SCU_CLK_BASE                    0x50004600UL\r
+#define SCU_OSC_BASE                    0x50004700UL\r
+#define SCU_PLL_BASE                    0x50004710UL\r
+#define SCU_GENERAL_BASE                0x50004000UL\r
+#define SCU_INTERRUPT_BASE              0x50004074UL\r
+#define SCU_PARITY_BASE                 0x5000413CUL\r
+#define SCU_TRAP_BASE                   0x50004160UL\r
+#define SCU_HIBERNATE_BASE              0x50004300UL\r
+#define SCU_POWER_BASE                  0x50004200UL\r
+#define SCU_RESET_BASE                  0x50004400UL\r
+#define LEDTS0_BASE                     0x48010000UL\r
+#define ETH0_CON_BASE                   0x50004040UL\r
+#define ETH0_BASE                       0x5000C000UL\r
+#define USB0_BASE                       0x50040000UL\r
+#define USB_EP_BASE                   0x50040900UL\r
+#define USB0_EP1_BASE                   0x50040920UL\r
+#define USB0_EP2_BASE                   0x50040940UL\r
+#define USB0_EP3_BASE                   0x50040960UL\r
+#define USB0_EP4_BASE                   0x50040980UL\r
+#define USB0_EP5_BASE                   0x500409A0UL\r
+#define USB0_EP6_BASE                   0x500409C0UL\r
+#define USB0_CH0_BASE                   0x50040500UL\r
+#define USB0_CH1_BASE                   0x50040520UL\r
+#define USB0_CH2_BASE                   0x50040540UL\r
+#define USB0_CH3_BASE                   0x50040560UL\r
+#define USB0_CH4_BASE                   0x50040580UL\r
+#define USB0_CH5_BASE                   0x500405A0UL\r
+#define USB0_CH6_BASE                   0x500405C0UL\r
+#define USB0_CH7_BASE                   0x500405E0UL\r
+#define USB0_CH8_BASE                   0x50040600UL\r
+#define USB0_CH9_BASE                   0x50040620UL\r
+#define USB0_CH10_BASE                  0x50040640UL\r
+#define USB0_CH11_BASE                  0x50040660UL\r
+#define USB0_CH12_BASE                  0x50040680UL\r
+#define USB0_CH13_BASE                  0x500406A0UL\r
+#define USIC0_BASE                      0x40030008UL\r
+#define USIC1_BASE                      0x48020008UL\r
+#define USIC0_CH0_BASE                  0x40030000UL\r
+#define USIC0_CH1_BASE                  0x40030200UL\r
+#define USIC1_CH0_BASE                  0x48020000UL\r
+#define USIC1_CH1_BASE                  0x48020200UL\r
+#define CAN_BASE                        0x48014000UL\r
+#define CAN_NODE0_BASE                  0x48014200UL\r
+#define CAN_NODE1_BASE                  0x48014300UL\r
+#define CAN_MO0_BASE                    0x48015000UL\r
+#define CAN_MO1_BASE                    0x48015020UL\r
+#define CAN_MO2_BASE                    0x48015040UL\r
+#define CAN_MO3_BASE                    0x48015060UL\r
+#define CAN_MO4_BASE                    0x48015080UL\r
+#define CAN_MO5_BASE                    0x480150A0UL\r
+#define CAN_MO6_BASE                    0x480150C0UL\r
+#define CAN_MO7_BASE                    0x480150E0UL\r
+#define CAN_MO8_BASE                    0x48015100UL\r
+#define CAN_MO9_BASE                    0x48015120UL\r
+#define CAN_MO10_BASE                   0x48015140UL\r
+#define CAN_MO11_BASE                   0x48015160UL\r
+#define CAN_MO12_BASE                   0x48015180UL\r
+#define CAN_MO13_BASE                   0x480151A0UL\r
+#define CAN_MO14_BASE                   0x480151C0UL\r
+#define CAN_MO15_BASE                   0x480151E0UL\r
+#define CAN_MO16_BASE                   0x48015200UL\r
+#define CAN_MO17_BASE                   0x48015220UL\r
+#define CAN_MO18_BASE                   0x48015240UL\r
+#define CAN_MO19_BASE                   0x48015260UL\r
+#define CAN_MO20_BASE                   0x48015280UL\r
+#define CAN_MO21_BASE                   0x480152A0UL\r
+#define CAN_MO22_BASE                   0x480152C0UL\r
+#define CAN_MO23_BASE                   0x480152E0UL\r
+#define CAN_MO24_BASE                   0x48015300UL\r
+#define CAN_MO25_BASE                   0x48015320UL\r
+#define CAN_MO26_BASE                   0x48015340UL\r
+#define CAN_MO27_BASE                   0x48015360UL\r
+#define CAN_MO28_BASE                   0x48015380UL\r
+#define CAN_MO29_BASE                   0x480153A0UL\r
+#define CAN_MO30_BASE                   0x480153C0UL\r
+#define CAN_MO31_BASE                   0x480153E0UL\r
+#define CAN_MO32_BASE                   0x48015400UL\r
+#define CAN_MO33_BASE                   0x48015420UL\r
+#define CAN_MO34_BASE                   0x48015440UL\r
+#define CAN_MO35_BASE                   0x48015460UL\r
+#define CAN_MO36_BASE                   0x48015480UL\r
+#define CAN_MO37_BASE                   0x480154A0UL\r
+#define CAN_MO38_BASE                   0x480154C0UL\r
+#define CAN_MO39_BASE                   0x480154E0UL\r
+#define CAN_MO40_BASE                   0x48015500UL\r
+#define CAN_MO41_BASE                   0x48015520UL\r
+#define CAN_MO42_BASE                   0x48015540UL\r
+#define CAN_MO43_BASE                   0x48015560UL\r
+#define CAN_MO44_BASE                   0x48015580UL\r
+#define CAN_MO45_BASE                   0x480155A0UL\r
+#define CAN_MO46_BASE                   0x480155C0UL\r
+#define CAN_MO47_BASE                   0x480155E0UL\r
+#define CAN_MO48_BASE                   0x48015600UL\r
+#define CAN_MO49_BASE                   0x48015620UL\r
+#define CAN_MO50_BASE                   0x48015640UL\r
+#define CAN_MO51_BASE                   0x48015660UL\r
+#define CAN_MO52_BASE                   0x48015680UL\r
+#define CAN_MO53_BASE                   0x480156A0UL\r
+#define CAN_MO54_BASE                   0x480156C0UL\r
+#define CAN_MO55_BASE                   0x480156E0UL\r
+#define CAN_MO56_BASE                   0x48015700UL\r
+#define CAN_MO57_BASE                   0x48015720UL\r
+#define CAN_MO58_BASE                   0x48015740UL\r
+#define CAN_MO59_BASE                   0x48015760UL\r
+#define CAN_MO60_BASE                   0x48015780UL\r
+#define CAN_MO61_BASE                   0x480157A0UL\r
+#define CAN_MO62_BASE                   0x480157C0UL\r
+#define CAN_MO63_BASE                   0x480157E0UL\r
+#define VADC_BASE                       0x40004000UL\r
+#define VADC_G0_BASE                    0x40004400UL\r
+#define VADC_G1_BASE                    0x40004800UL\r
+#define VADC_G2_BASE                    0x40004C00UL\r
+#define VADC_G3_BASE                    0x40005000UL\r
+#define DSD_BASE                        0x40008000UL\r
+#define DSD_CH0_BASE                    0x40008100UL\r
+#define DSD_CH1_BASE                    0x40008200UL\r
+#define DSD_CH2_BASE                    0x40008300UL\r
+#define DSD_CH3_BASE                    0x40008400UL\r
+#define DAC_BASE                        0x48018000UL\r
+#define CCU40_BASE                      0x4000C000UL\r
+#define CCU41_BASE                      0x40010000UL\r
+#define CCU42_BASE                      0x40014000UL\r
+#define CCU43_BASE                      0x48004000UL\r
+#define CCU40_CC40_BASE                 0x4000C100UL\r
+#define CCU40_CC41_BASE                 0x4000C200UL\r
+#define CCU40_CC42_BASE                 0x4000C300UL\r
+#define CCU40_CC43_BASE                 0x4000C400UL\r
+#define CCU41_CC40_BASE                 0x40010100UL\r
+#define CCU41_CC41_BASE                 0x40010200UL\r
+#define CCU41_CC42_BASE                 0x40010300UL\r
+#define CCU41_CC43_BASE                 0x40010400UL\r
+#define CCU42_CC40_BASE                 0x40014100UL\r
+#define CCU42_CC41_BASE                 0x40014200UL\r
+#define CCU42_CC42_BASE                 0x40014300UL\r
+#define CCU42_CC43_BASE                 0x40014400UL\r
+#define CCU43_CC40_BASE                 0x48004100UL\r
+#define CCU43_CC41_BASE                 0x48004200UL\r
+#define CCU43_CC42_BASE                 0x48004300UL\r
+#define CCU43_CC43_BASE                 0x48004400UL\r
+#define CCU80_BASE                      0x40020000UL\r
+#define CCU81_BASE                      0x40024000UL\r
+#define CCU80_CC80_BASE                 0x40020100UL\r
+#define CCU80_CC81_BASE                 0x40020200UL\r
+#define CCU80_CC82_BASE                 0x40020300UL\r
+#define CCU80_CC83_BASE                 0x40020400UL\r
+#define CCU81_CC80_BASE                 0x40024100UL\r
+#define CCU81_CC81_BASE                 0x40024200UL\r
+#define CCU81_CC82_BASE                 0x40024300UL\r
+#define CCU81_CC83_BASE                 0x40024400UL\r
+#define HRPWM0_BASE                     0x40020900UL\r
+#define HRPWM0_CSG0_BASE                0x40020A00UL\r
+#define HRPWM0_CSG1_BASE                0x40020B00UL\r
+#define HRPWM0_CSG2_BASE                0x40020C00UL\r
+#define HRPWM0_HRC0_BASE                0x40021300UL\r
+#define HRPWM0_HRC1_BASE                0x40021400UL\r
+#define HRPWM0_HRC2_BASE                0x40021500UL\r
+#define HRPWM0_HRC3_BASE                0x40021600UL\r
+#define POSIF0_BASE                     0x40028000UL\r
+#define POSIF1_BASE                     0x4002C000UL\r
+#define PORT0_BASE                      0x48028000UL\r
+#define PORT1_BASE                      0x48028100UL\r
+#define PORT2_BASE                      0x48028200UL\r
+#define PORT3_BASE                      0x48028300UL\r
+#define PORT4_BASE                      0x48028400UL\r
+#define PORT5_BASE                      0x48028500UL\r
+#define PORT14_BASE                     0x48028E00UL\r
+#define PORT15_BASE                     0x48028F00UL\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================             Peripheral declaration             ================ */\r
+/* ================================================================================ */\r
+\r
+#define PPB                             ((PPB_Type                *) PPB_BASE)\r
+#define DLR                             ((DLR_GLOBAL_TypeDef                *) DLR_BASE)\r
+#define ERU0                            ((ERU_GLOBAL_TypeDef                *) ERU0_BASE)\r
+#define ERU1                            ((ERU_GLOBAL_TypeDef                *) ERU1_BASE)\r
+#define GPDMA0                          ((GPDMA0_GLOBAL_TypeDef             *) GPDMA0_BASE)\r
+#define GPDMA0_CH0                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH0_BASE)\r
+#define GPDMA0_CH1                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH1_BASE)\r
+#define GPDMA0_CH2                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH2_BASE)\r
+#define GPDMA0_CH3                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH3_BASE)\r
+#define GPDMA0_CH4                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH4_BASE)\r
+#define GPDMA0_CH5                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH5_BASE)\r
+#define GPDMA0_CH6                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH6_BASE)\r
+#define GPDMA0_CH7                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH7_BASE)\r
+#define FCE                             ((FCE_GLOBAL_TypeDef                *) FCE_BASE)\r
+#define FCE_KE0                         ((FCE_KE_TypeDef             *) FCE_KE0_BASE)\r
+#define FCE_KE1                         ((FCE_KE_TypeDef             *) FCE_KE1_BASE)\r
+#define FCE_KE2                         ((FCE_KE_TypeDef             *) FCE_KE2_BASE)\r
+#define FCE_KE3                         ((FCE_KE_TypeDef             *) FCE_KE3_BASE)\r
+#define PBA0                            ((PBA_GLOBAL_TypeDef                *) PBA0_BASE)\r
+#define PBA1                            ((PBA_GLOBAL_TypeDef                *) PBA1_BASE)\r
+#define FLASH0                          ((FLASH0_GLOBAL_TypeDef              *) FLASH0_BASE)\r
+#define PREF                            ((PREF_GLOBAL_TypeDef               *) PREF_BASE)\r
+#define PMU0                            ((PMU0_GLOBAL_TypeDef                *) PMU0_BASE)\r
+#define WDT                             ((WDT_GLOBAL_TypeDef                *) WDT_BASE)\r
+#define RTC                             ((RTC_GLOBAL_TypeDef                *) RTC_BASE)\r
+#define SCU_CLK                         ((SCU_CLK_TypeDef            *) SCU_CLK_BASE)\r
+#define SCU_OSC                         ((SCU_OSC_TypeDef            *) SCU_OSC_BASE)\r
+#define SCU_PLL                         ((SCU_PLL_TypeDef            *) SCU_PLL_BASE)\r
+#define SCU_GENERAL                     ((SCU_GENERAL_TypeDef        *) SCU_GENERAL_BASE)\r
+#define SCU_INTERRUPT                   ((SCU_INTERRUPT_TypeDef      *) SCU_INTERRUPT_BASE)\r
+#define SCU_PARITY                      ((SCU_PARITY_TypeDef         *) SCU_PARITY_BASE)\r
+#define SCU_TRAP                        ((SCU_TRAP_TypeDef           *) SCU_TRAP_BASE)\r
+#define SCU_HIBERNATE                   ((SCU_HIBERNATE_TypeDef      *) SCU_HIBERNATE_BASE)\r
+#define SCU_POWER                       ((SCU_POWER_TypeDef          *) SCU_POWER_BASE)\r
+#define SCU_RESET                       ((SCU_RESET_TypeDef          *) SCU_RESET_BASE)\r
+#define LEDTS0                          ((LEDTS0_GLOBAL_TypeDef              *) LEDTS0_BASE)\r
+#define ETH0_CON                        ((ETH0_CON_GLOBAL_TypeDef           *) ETH0_CON_BASE)\r
+#define ETH0                            ((ETH_GLOBAL_TypeDef                *) ETH0_BASE)\r
+#define USB0                            ((USB0_GLOBAL_TypeDef                *) USB0_BASE)\r
+#define USB0_EP0                        ((USB0_EP0_TypeDef           *) USB_EP_BASE)\r
+#define USB0_EP1                        ((USB0_EP_TypeDef             *) USB0_EP1_BASE)\r
+#define USB0_EP2                        ((USB0_EP_TypeDef             *) USB0_EP2_BASE)\r
+#define USB0_EP3                        ((USB0_EP_TypeDef             *) USB0_EP3_BASE)\r
+#define USB0_EP4                        ((USB0_EP_TypeDef             *) USB0_EP4_BASE)\r
+#define USB0_EP5                        ((USB0_EP_TypeDef             *) USB0_EP5_BASE)\r
+#define USB0_EP6                        ((USB0_EP_TypeDef             *) USB0_EP6_BASE)\r
+#define USB0_CH0                        ((USB0_CH_TypeDef             *) USB0_CH0_BASE)\r
+#define USB0_CH1                        ((USB0_CH_TypeDef             *) USB0_CH1_BASE)\r
+#define USB0_CH2                        ((USB0_CH_TypeDef             *) USB0_CH2_BASE)\r
+#define USB0_CH3                        ((USB0_CH_TypeDef             *) USB0_CH3_BASE)\r
+#define USB0_CH4                        ((USB0_CH_TypeDef             *) USB0_CH4_BASE)\r
+#define USB0_CH5                        ((USB0_CH_TypeDef             *) USB0_CH5_BASE)\r
+#define USB0_CH6                        ((USB0_CH_TypeDef             *) USB0_CH6_BASE)\r
+#define USB0_CH7                        ((USB0_CH_TypeDef             *) USB0_CH7_BASE)\r
+#define USB0_CH8                        ((USB0_CH_TypeDef             *) USB0_CH8_BASE)\r
+#define USB0_CH9                        ((USB0_CH_TypeDef             *) USB0_CH9_BASE)\r
+#define USB0_CH10                       ((USB0_CH_TypeDef             *) USB0_CH10_BASE)\r
+#define USB0_CH11                       ((USB0_CH_TypeDef             *) USB0_CH11_BASE)\r
+#define USB0_CH12                       ((USB0_CH_TypeDef             *) USB0_CH12_BASE)\r
+#define USB0_CH13                       ((USB0_CH_TypeDef             *) USB0_CH13_BASE)\r
+#define USIC0                           ((USIC_GLOBAL_TypeDef               *) USIC0_BASE)\r
+#define USIC1                           ((USIC_GLOBAL_TypeDef               *) USIC1_BASE)\r
+#define USIC0_CH0                       ((USIC_CH_TypeDef            *) USIC0_CH0_BASE)\r
+#define USIC0_CH1                       ((USIC_CH_TypeDef            *) USIC0_CH1_BASE)\r
+#define USIC1_CH0                       ((USIC_CH_TypeDef            *) USIC1_CH0_BASE)\r
+#define USIC1_CH1                       ((USIC_CH_TypeDef            *) USIC1_CH1_BASE)\r
+#define CAN                             ((CAN_GLOBAL_TypeDef                *) CAN_BASE)\r
+#define CAN_NODE0                       ((CAN_NODE_TypeDef           *) CAN_NODE0_BASE)\r
+#define CAN_NODE1                       ((CAN_NODE_TypeDef           *) CAN_NODE1_BASE)\r
+#define CAN_MO0                         ((CAN_MO_TypeDef             *) CAN_MO0_BASE)\r
+#define CAN_MO1                         ((CAN_MO_TypeDef             *) CAN_MO1_BASE)\r
+#define CAN_MO2                         ((CAN_MO_TypeDef             *) CAN_MO2_BASE)\r
+#define CAN_MO3                         ((CAN_MO_TypeDef             *) CAN_MO3_BASE)\r
+#define CAN_MO4                         ((CAN_MO_TypeDef             *) CAN_MO4_BASE)\r
+#define CAN_MO5                         ((CAN_MO_TypeDef             *) CAN_MO5_BASE)\r
+#define CAN_MO6                         ((CAN_MO_TypeDef             *) CAN_MO6_BASE)\r
+#define CAN_MO7                         ((CAN_MO_TypeDef             *) CAN_MO7_BASE)\r
+#define CAN_MO8                         ((CAN_MO_TypeDef             *) CAN_MO8_BASE)\r
+#define CAN_MO9                         ((CAN_MO_TypeDef             *) CAN_MO9_BASE)\r
+#define CAN_MO10                        ((CAN_MO_TypeDef             *) CAN_MO10_BASE)\r
+#define CAN_MO11                        ((CAN_MO_TypeDef             *) CAN_MO11_BASE)\r
+#define CAN_MO12                        ((CAN_MO_TypeDef             *) CAN_MO12_BASE)\r
+#define CAN_MO13                        ((CAN_MO_TypeDef             *) CAN_MO13_BASE)\r
+#define CAN_MO14                        ((CAN_MO_TypeDef             *) CAN_MO14_BASE)\r
+#define CAN_MO15                        ((CAN_MO_TypeDef             *) CAN_MO15_BASE)\r
+#define CAN_MO16                        ((CAN_MO_TypeDef             *) CAN_MO16_BASE)\r
+#define CAN_MO17                        ((CAN_MO_TypeDef             *) CAN_MO17_BASE)\r
+#define CAN_MO18                        ((CAN_MO_TypeDef             *) CAN_MO18_BASE)\r
+#define CAN_MO19                        ((CAN_MO_TypeDef             *) CAN_MO19_BASE)\r
+#define CAN_MO20                        ((CAN_MO_TypeDef             *) CAN_MO20_BASE)\r
+#define CAN_MO21                        ((CAN_MO_TypeDef             *) CAN_MO21_BASE)\r
+#define CAN_MO22                        ((CAN_MO_TypeDef             *) CAN_MO22_BASE)\r
+#define CAN_MO23                        ((CAN_MO_TypeDef             *) CAN_MO23_BASE)\r
+#define CAN_MO24                        ((CAN_MO_TypeDef             *) CAN_MO24_BASE)\r
+#define CAN_MO25                        ((CAN_MO_TypeDef             *) CAN_MO25_BASE)\r
+#define CAN_MO26                        ((CAN_MO_TypeDef             *) CAN_MO26_BASE)\r
+#define CAN_MO27                        ((CAN_MO_TypeDef             *) CAN_MO27_BASE)\r
+#define CAN_MO28                        ((CAN_MO_TypeDef             *) CAN_MO28_BASE)\r
+#define CAN_MO29                        ((CAN_MO_TypeDef             *) CAN_MO29_BASE)\r
+#define CAN_MO30                        ((CAN_MO_TypeDef             *) CAN_MO30_BASE)\r
+#define CAN_MO31                        ((CAN_MO_TypeDef             *) CAN_MO31_BASE)\r
+#define CAN_MO32                        ((CAN_MO_TypeDef             *) CAN_MO32_BASE)\r
+#define CAN_MO33                        ((CAN_MO_TypeDef             *) CAN_MO33_BASE)\r
+#define CAN_MO34                        ((CAN_MO_TypeDef             *) CAN_MO34_BASE)\r
+#define CAN_MO35                        ((CAN_MO_TypeDef             *) CAN_MO35_BASE)\r
+#define CAN_MO36                        ((CAN_MO_TypeDef             *) CAN_MO36_BASE)\r
+#define CAN_MO37                        ((CAN_MO_TypeDef             *) CAN_MO37_BASE)\r
+#define CAN_MO38                        ((CAN_MO_TypeDef             *) CAN_MO38_BASE)\r
+#define CAN_MO39                        ((CAN_MO_TypeDef             *) CAN_MO39_BASE)\r
+#define CAN_MO40                        ((CAN_MO_TypeDef             *) CAN_MO40_BASE)\r
+#define CAN_MO41                        ((CAN_MO_TypeDef             *) CAN_MO41_BASE)\r
+#define CAN_MO42                        ((CAN_MO_TypeDef             *) CAN_MO42_BASE)\r
+#define CAN_MO43                        ((CAN_MO_TypeDef             *) CAN_MO43_BASE)\r
+#define CAN_MO44                        ((CAN_MO_TypeDef             *) CAN_MO44_BASE)\r
+#define CAN_MO45                        ((CAN_MO_TypeDef             *) CAN_MO45_BASE)\r
+#define CAN_MO46                        ((CAN_MO_TypeDef             *) CAN_MO46_BASE)\r
+#define CAN_MO47                        ((CAN_MO_TypeDef             *) CAN_MO47_BASE)\r
+#define CAN_MO48                        ((CAN_MO_TypeDef             *) CAN_MO48_BASE)\r
+#define CAN_MO49                        ((CAN_MO_TypeDef             *) CAN_MO49_BASE)\r
+#define CAN_MO50                        ((CAN_MO_TypeDef             *) CAN_MO50_BASE)\r
+#define CAN_MO51                        ((CAN_MO_TypeDef             *) CAN_MO51_BASE)\r
+#define CAN_MO52                        ((CAN_MO_TypeDef             *) CAN_MO52_BASE)\r
+#define CAN_MO53                        ((CAN_MO_TypeDef             *) CAN_MO53_BASE)\r
+#define CAN_MO54                        ((CAN_MO_TypeDef             *) CAN_MO54_BASE)\r
+#define CAN_MO55                        ((CAN_MO_TypeDef             *) CAN_MO55_BASE)\r
+#define CAN_MO56                        ((CAN_MO_TypeDef             *) CAN_MO56_BASE)\r
+#define CAN_MO57                        ((CAN_MO_TypeDef             *) CAN_MO57_BASE)\r
+#define CAN_MO58                        ((CAN_MO_TypeDef             *) CAN_MO58_BASE)\r
+#define CAN_MO59                        ((CAN_MO_TypeDef             *) CAN_MO59_BASE)\r
+#define CAN_MO60                        ((CAN_MO_TypeDef             *) CAN_MO60_BASE)\r
+#define CAN_MO61                        ((CAN_MO_TypeDef             *) CAN_MO61_BASE)\r
+#define CAN_MO62                        ((CAN_MO_TypeDef             *) CAN_MO62_BASE)\r
+#define CAN_MO63                        ((CAN_MO_TypeDef             *) CAN_MO63_BASE)\r
+#define VADC                            ((VADC_GLOBAL_TypeDef               *) VADC_BASE)\r
+#define VADC_G0                         ((VADC_G_TypeDef             *) VADC_G0_BASE)\r
+#define VADC_G1                         ((VADC_G_TypeDef             *) VADC_G1_BASE)\r
+#define VADC_G2                         ((VADC_G_TypeDef             *) VADC_G2_BASE)\r
+#define VADC_G3                         ((VADC_G_TypeDef             *) VADC_G3_BASE)\r
+#define DSD                             ((DSD_GLOBAL_TypeDef                *) DSD_BASE)\r
+#define DSD_CH0                         ((DSD_CH_TypeDef             *) DSD_CH0_BASE)\r
+#define DSD_CH1                         ((DSD_CH_TypeDef             *) DSD_CH1_BASE)\r
+#define DSD_CH2                         ((DSD_CH_TypeDef             *) DSD_CH2_BASE)\r
+#define DSD_CH3                         ((DSD_CH_TypeDef             *) DSD_CH3_BASE)\r
+#define DAC                             ((DAC_GLOBAL_TypeDef                *) DAC_BASE)\r
+#define CCU40                           ((CCU4_GLOBAL_TypeDef               *) CCU40_BASE)\r
+#define CCU41                           ((CCU4_GLOBAL_TypeDef               *) CCU41_BASE)\r
+#define CCU42                           ((CCU4_GLOBAL_TypeDef               *) CCU42_BASE)\r
+#define CCU43                           ((CCU4_GLOBAL_TypeDef               *) CCU43_BASE)\r
+#define CCU40_CC40                      ((CCU4_CC4_TypeDef           *) CCU40_CC40_BASE)\r
+#define CCU40_CC41                      ((CCU4_CC4_TypeDef           *) CCU40_CC41_BASE)\r
+#define CCU40_CC42                      ((CCU4_CC4_TypeDef           *) CCU40_CC42_BASE)\r
+#define CCU40_CC43                      ((CCU4_CC4_TypeDef           *) CCU40_CC43_BASE)\r
+#define CCU41_CC40                      ((CCU4_CC4_TypeDef           *) CCU41_CC40_BASE)\r
+#define CCU41_CC41                      ((CCU4_CC4_TypeDef           *) CCU41_CC41_BASE)\r
+#define CCU41_CC42                      ((CCU4_CC4_TypeDef           *) CCU41_CC42_BASE)\r
+#define CCU41_CC43                      ((CCU4_CC4_TypeDef           *) CCU41_CC43_BASE)\r
+#define CCU42_CC40                      ((CCU4_CC4_TypeDef           *) CCU42_CC40_BASE)\r
+#define CCU42_CC41                      ((CCU4_CC4_TypeDef           *) CCU42_CC41_BASE)\r
+#define CCU42_CC42                      ((CCU4_CC4_TypeDef           *) CCU42_CC42_BASE)\r
+#define CCU42_CC43                      ((CCU4_CC4_TypeDef           *) CCU42_CC43_BASE)\r
+#define CCU43_CC40                      ((CCU4_CC4_TypeDef           *) CCU43_CC40_BASE)\r
+#define CCU43_CC41                      ((CCU4_CC4_TypeDef           *) CCU43_CC41_BASE)\r
+#define CCU43_CC42                      ((CCU4_CC4_TypeDef           *) CCU43_CC42_BASE)\r
+#define CCU43_CC43                      ((CCU4_CC4_TypeDef           *) CCU43_CC43_BASE)\r
+#define CCU80                           ((CCU8_GLOBAL_TypeDef               *) CCU80_BASE)\r
+#define CCU81                           ((CCU8_GLOBAL_TypeDef               *) CCU81_BASE)\r
+#define CCU80_CC80                      ((CCU8_CC8_TypeDef           *) CCU80_CC80_BASE)\r
+#define CCU80_CC81                      ((CCU8_CC8_TypeDef           *) CCU80_CC81_BASE)\r
+#define CCU80_CC82                      ((CCU8_CC8_TypeDef           *) CCU80_CC82_BASE)\r
+#define CCU80_CC83                      ((CCU8_CC8_TypeDef           *) CCU80_CC83_BASE)\r
+#define CCU81_CC80                      ((CCU8_CC8_TypeDef           *) CCU81_CC80_BASE)\r
+#define CCU81_CC81                      ((CCU8_CC8_TypeDef           *) CCU81_CC81_BASE)\r
+#define CCU81_CC82                      ((CCU8_CC8_TypeDef           *) CCU81_CC82_BASE)\r
+#define CCU81_CC83                      ((CCU8_CC8_TypeDef           *) CCU81_CC83_BASE)\r
+#define HRPWM0                          ((HRPWM0_Type             *) HRPWM0_BASE)\r
+#define HRPWM0_CSG0                     ((HRPWM0_CSG_Type         *) HRPWM0_CSG0_BASE)\r
+#define HRPWM0_CSG1                     ((HRPWM0_CSG_Type         *) HRPWM0_CSG1_BASE)\r
+#define HRPWM0_CSG2                     ((HRPWM0_CSG_Type         *) HRPWM0_CSG2_BASE)\r
+#define HRPWM0_HRC0                     ((HRPWM0_HRC_Type         *) HRPWM0_HRC0_BASE)\r
+#define HRPWM0_HRC1                     ((HRPWM0_HRC_Type         *) HRPWM0_HRC1_BASE)\r
+#define HRPWM0_HRC2                     ((HRPWM0_HRC_Type         *) HRPWM0_HRC2_BASE)\r
+#define HRPWM0_HRC3                     ((HRPWM0_HRC_Type         *) HRPWM0_HRC3_BASE)\r
+#define POSIF0                          ((POSIF_GLOBAL_TypeDef              *) POSIF0_BASE)\r
+#define POSIF1                          ((POSIF_GLOBAL_TypeDef              *) POSIF1_BASE)\r
+#define PORT0                           ((PORT0_Type              *) PORT0_BASE)\r
+#define PORT1                           ((PORT1_Type              *) PORT1_BASE)\r
+#define PORT2                           ((PORT2_Type              *) PORT2_BASE)\r
+#define PORT3                           ((PORT3_Type              *) PORT3_BASE)\r
+#define PORT4                           ((PORT4_Type              *) PORT4_BASE)\r
+#define PORT5                           ((PORT5_Type              *) PORT5_BASE)\r
+#define PORT14                          ((PORT14_Type             *) PORT14_BASE)\r
+#define PORT15                          ((PORT15_Type             *) PORT15_BASE)\r
+\r
+\r
+/** @} */ /* End of group Device_Peripheral_Registers */\r
+/** @} */ /* End of group XMC4400 */\r
+/** @} */ /* End of group Infineon */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif  /* XMC4400_H */\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4500.h
new file mode 100644 (file)
index 0000000..f06f5fe
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4500.h
@@ -0,0 +1,16851 @@
+\r
+/****************************************************************************************************//**\r
+ * @file     XMC4500.h\r
+ *\r
+ * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for\r
+ *           XMC4500 from Infineon.\r
+ *\r
+ * @version  V1.2.0 (Reference Manual v1.2)\r
+ * @date     6. February 2013\r
+ *\r
+ * @note     Generated with SVDConv V2.78b \r
+ *           from CMSIS SVD File 'XMC4500_Processed_SVD.xml' Version 1.2.0 (Reference Manual v1.2),\r
+ *******************************************************************************************************/\r
+\r
+\r
+\r
+/** @addtogroup Infineon\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup XMC4500\r
+  * @{\r
+  */\r
+\r
+#ifndef XMC4500_H\r
+#define XMC4500_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/* -------------------------  Interrupt Number Definition  ------------------------ */\r
+\r
+typedef enum {\r
+/* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */\r
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */\r
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */\r
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */\r
+  MemoryManagement_IRQn         = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation\r
+                                                         and No Match                                                          */\r
+  BusFault_IRQn                 = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory\r
+                                                         related Fault                                                         */\r
+  UsageFault_IRQn               = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */\r
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */\r
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */\r
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */\r
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */\r
+/* ---------------------  XMC4500 Specific Interrupt Numbers  --------------------- */\r
+  SCU_0_IRQn                    =   0,              /*!<   0  SCU_0                                                            */\r
+  ERU0_0_IRQn                   =   1,              /*!<   1  ERU0_0                                                           */\r
+  ERU0_1_IRQn                   =   2,              /*!<   2  ERU0_1                                                           */\r
+  ERU0_2_IRQn                   =   3,              /*!<   3  ERU0_2                                                           */\r
+  ERU0_3_IRQn                   =   4,              /*!<   4  ERU0_3                                                           */\r
+  ERU1_0_IRQn                   =   5,              /*!<   5  ERU1_0                                                           */\r
+  ERU1_1_IRQn                   =   6,              /*!<   6  ERU1_1                                                           */\r
+  ERU1_2_IRQn                   =   7,              /*!<   7  ERU1_2                                                           */\r
+  ERU1_3_IRQn                   =   8,              /*!<   8  ERU1_3                                                           */\r
+  PMU0_0_IRQn                   =  12,              /*!<  12  PMU0_0                                                           */\r
+  VADC0_C0_0_IRQn               =  14,              /*!<  14  VADC0_C0_0                                                       */\r
+  VADC0_C0_1_IRQn               =  15,              /*!<  15  VADC0_C0_1                                                       */\r
+  VADC0_C0_2_IRQn               =  16,              /*!<  16  VADC0_C0_2                                                       */\r
+  VADC0_C0_3_IRQn               =  17,              /*!<  17  VADC0_C0_3                                                       */\r
+  VADC0_G0_0_IRQn               =  18,              /*!<  18  VADC0_G0_0                                                       */\r
+  VADC0_G0_1_IRQn               =  19,              /*!<  19  VADC0_G0_1                                                       */\r
+  VADC0_G0_2_IRQn               =  20,              /*!<  20  VADC0_G0_2                                                       */\r
+  VADC0_G0_3_IRQn               =  21,              /*!<  21  VADC0_G0_3                                                       */\r
+  VADC0_G1_0_IRQn               =  22,              /*!<  22  VADC0_G1_0                                                       */\r
+  VADC0_G1_1_IRQn               =  23,              /*!<  23  VADC0_G1_1                                                       */\r
+  VADC0_G1_2_IRQn               =  24,              /*!<  24  VADC0_G1_2                                                       */\r
+  VADC0_G1_3_IRQn               =  25,              /*!<  25  VADC0_G1_3                                                       */\r
+  VADC0_G2_0_IRQn               =  26,              /*!<  26  VADC0_G2_0                                                       */\r
+  VADC0_G2_1_IRQn               =  27,              /*!<  27  VADC0_G2_1                                                       */\r
+  VADC0_G2_2_IRQn               =  28,              /*!<  28  VADC0_G2_2                                                       */\r
+  VADC0_G2_3_IRQn               =  29,              /*!<  29  VADC0_G2_3                                                       */\r
+  VADC0_G3_0_IRQn               =  30,              /*!<  30  VADC0_G3_0                                                       */\r
+  VADC0_G3_1_IRQn               =  31,              /*!<  31  VADC0_G3_1                                                       */\r
+  VADC0_G3_2_IRQn               =  32,              /*!<  32  VADC0_G3_2                                                       */\r
+  VADC0_G3_3_IRQn               =  33,              /*!<  33  VADC0_G3_3                                                       */\r
+  DSD0_M_0_IRQn                 =  34,              /*!<  34  DSD0_M_0                                                         */\r
+  DSD0_M_1_IRQn                 =  35,              /*!<  35  DSD0_M_1                                                         */\r
+  DSD0_M_2_IRQn                 =  36,              /*!<  36  DSD0_M_2                                                         */\r
+  DSD0_M_3_IRQn                 =  37,              /*!<  37  DSD0_M_3                                                         */\r
+  DSD0_A_4_IRQn                 =  38,              /*!<  38  DSD0_A_4                                                         */\r
+  DSD0_A_5_IRQn                 =  39,              /*!<  39  DSD0_A_5                                                         */\r
+  DSD0_A_6_IRQn                 =  40,              /*!<  40  DSD0_A_6                                                         */\r
+  DSD0_A_7_IRQn                 =  41,              /*!<  41  DSD0_A_7                                                         */\r
+  DAC0_0_IRQn                   =  42,              /*!<  42  DAC0_0                                                           */\r
+  DAC0_1_IRQn                   =  43,              /*!<  43  DAC0_1                                                           */\r
+  CCU40_0_IRQn                  =  44,              /*!<  44  CCU40_0                                                          */\r
+  CCU40_1_IRQn                  =  45,              /*!<  45  CCU40_1                                                          */\r
+  CCU40_2_IRQn                  =  46,              /*!<  46  CCU40_2                                                          */\r
+  CCU40_3_IRQn                  =  47,              /*!<  47  CCU40_3                                                          */\r
+  CCU41_0_IRQn                  =  48,              /*!<  48  CCU41_0                                                          */\r
+  CCU41_1_IRQn                  =  49,              /*!<  49  CCU41_1                                                          */\r
+  CCU41_2_IRQn                  =  50,              /*!<  50  CCU41_2                                                          */\r
+  CCU41_3_IRQn                  =  51,              /*!<  51  CCU41_3                                                          */\r
+  CCU42_0_IRQn                  =  52,              /*!<  52  CCU42_0                                                          */\r
+  CCU42_1_IRQn                  =  53,              /*!<  53  CCU42_1                                                          */\r
+  CCU42_2_IRQn                  =  54,              /*!<  54  CCU42_2                                                          */\r
+  CCU42_3_IRQn                  =  55,              /*!<  55  CCU42_3                                                          */\r
+  CCU43_0_IRQn                  =  56,              /*!<  56  CCU43_0                                                          */\r
+  CCU43_1_IRQn                  =  57,              /*!<  57  CCU43_1                                                          */\r
+  CCU43_2_IRQn                  =  58,              /*!<  58  CCU43_2                                                          */\r
+  CCU43_3_IRQn                  =  59,              /*!<  59  CCU43_3                                                          */\r
+  CCU80_0_IRQn                  =  60,              /*!<  60  CCU80_0                                                          */\r
+  CCU80_1_IRQn                  =  61,              /*!<  61  CCU80_1                                                          */\r
+  CCU80_2_IRQn                  =  62,              /*!<  62  CCU80_2                                                          */\r
+  CCU80_3_IRQn                  =  63,              /*!<  63  CCU80_3                                                          */\r
+  CCU81_0_IRQn                  =  64,              /*!<  64  CCU81_0                                                          */\r
+  CCU81_1_IRQn                  =  65,              /*!<  65  CCU81_1                                                          */\r
+  CCU81_2_IRQn                  =  66,              /*!<  66  CCU81_2                                                          */\r
+  CCU81_3_IRQn                  =  67,              /*!<  67  CCU81_3                                                          */\r
+  POSIF0_0_IRQn                 =  68,              /*!<  68  POSIF0_0                                                         */\r
+  POSIF0_1_IRQn                 =  69,              /*!<  69  POSIF0_1                                                         */\r
+  POSIF1_0_IRQn                 =  70,              /*!<  70  POSIF1_0                                                         */\r
+  POSIF1_1_IRQn                 =  71,              /*!<  71  POSIF1_1                                                         */\r
+  CAN0_0_IRQn                   =  76,              /*!<  76  CAN0_0                                                           */\r
+  CAN0_1_IRQn                   =  77,              /*!<  77  CAN0_1                                                           */\r
+  CAN0_2_IRQn                   =  78,              /*!<  78  CAN0_2                                                           */\r
+  CAN0_3_IRQn                   =  79,              /*!<  79  CAN0_3                                                           */\r
+  CAN0_4_IRQn                   =  80,              /*!<  80  CAN0_4                                                           */\r
+  CAN0_5_IRQn                   =  81,              /*!<  81  CAN0_5                                                           */\r
+  CAN0_6_IRQn                   =  82,              /*!<  82  CAN0_6                                                           */\r
+  CAN0_7_IRQn                   =  83,              /*!<  83  CAN0_7                                                           */\r
+  USIC0_0_IRQn                  =  84,              /*!<  84  USIC0_0                                                          */\r
+  USIC0_1_IRQn                  =  85,              /*!<  85  USIC0_1                                                          */\r
+  USIC0_2_IRQn                  =  86,              /*!<  86  USIC0_2                                                          */\r
+  USIC0_3_IRQn                  =  87,              /*!<  87  USIC0_3                                                          */\r
+  USIC0_4_IRQn                  =  88,              /*!<  88  USIC0_4                                                          */\r
+  USIC0_5_IRQn                  =  89,              /*!<  89  USIC0_5                                                          */\r
+  USIC1_0_IRQn                  =  90,              /*!<  90  USIC1_0                                                          */\r
+  USIC1_1_IRQn                  =  91,              /*!<  91  USIC1_1                                                          */\r
+  USIC1_2_IRQn                  =  92,              /*!<  92  USIC1_2                                                          */\r
+  USIC1_3_IRQn                  =  93,              /*!<  93  USIC1_3                                                          */\r
+  USIC1_4_IRQn                  =  94,              /*!<  94  USIC1_4                                                          */\r
+  USIC1_5_IRQn                  =  95,              /*!<  95  USIC1_5                                                          */\r
+  USIC2_0_IRQn                  =  96,              /*!<  96  USIC2_0                                                          */\r
+  USIC2_1_IRQn                  =  97,              /*!<  97  USIC2_1                                                          */\r
+  USIC2_2_IRQn                  =  98,              /*!<  98  USIC2_2                                                          */\r
+  USIC2_3_IRQn                  =  99,              /*!<  99  USIC2_3                                                          */\r
+  USIC2_4_IRQn                  = 100,              /*!< 100  USIC2_4                                                          */\r
+  USIC2_5_IRQn                  = 101,              /*!< 101  USIC2_5                                                          */\r
+  LEDTS0_0_IRQn                 = 102,              /*!< 102  LEDTS0_0                                                         */\r
+  FCE0_0_IRQn                   = 104,              /*!< 104  FCE0_0                                                           */\r
+  GPDMA0_0_IRQn                 = 105,              /*!< 105  GPDMA0_0                                                         */\r
+  SDMMC0_0_IRQn                 = 106,              /*!< 106  SDMMC0_0                                                         */\r
+  USB0_0_IRQn                   = 107,              /*!< 107  USB0_0                                                           */\r
+  ETH0_0_IRQn                   = 108,              /*!< 108  ETH0_0                                                           */\r
+  GPDMA1_0_IRQn                 = 110               /*!< 110  GPDMA1_0                                                         */\r
+} IRQn_Type;\r
+\r
+\r
+/** @addtogroup Configuration_of_CMSIS\r
+  * @{\r
+  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      Processor and Core Peripheral Section     ================ */\r
+/* ================================================================================ */\r
+\r
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */\r
+#define __CM4_REV                 0x0200            /*!< Cortex-M4 Core Revision                                               */\r
+#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */\r
+#define __NVIC_PRIO_BITS               6            /*!< Number of Bits used for Priority Levels                               */\r
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */\r
+#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */\r
+/** @} */ /* End of group Configuration_of_CMSIS */\r
+\r
+#include <core_cm4.h>                               /*!< Cortex-M4 processor and core peripherals                              */\r
+#include "system_XMC4500.h"                         /*!< XMC4500 System                                                        */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       Device Specific Peripheral Section       ================ */\r
+/* ================================================================================ */\r
+/* Macro to modify desired bitfields of a register */\r
+#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \\r
+                                                        ((uint32_t)mask)) | \\r
+                                          (reg & ((uint32_t)~((uint32_t)mask)))\r
+\r
+/* Macro to modify desired bitfields of a register */\r
+#define WR_REG_SIZE(reg, mask, pos, val, size) {  \\r
+uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \\r
+uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \\r
+uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \\r
+uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \\r
+reg = (uint##size##_t) (VAL2 | VAL4);\\r
+}\r
+\r
+/** Macro to read bitfields from a register */\r
+#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)\r
+\r
+/** Macro to read bitfields from a register */\r
+#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \\r
+                                                      (uint32_t)mask) >> pos) )\r
+\r
+/** Macro to set a bit in register */\r
+#define SET_BIT(reg, pos)     (reg |= ((uint32_t)1<<pos))\r
+\r
+/** Macro to clear a bit in register */\r
+#define CLR_BIT(reg, pos)     (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) )\r
+/*\r
+* ==========================================================================\r
+* ---------- Interrupt Handler Definition ----------------------------------\r
+* ==========================================================================\r
+*/\r
+#define IRQ_Hdlr_0   SCU_0_IRQHandler\r
+#define IRQ_Hdlr_1   ERU0_0_IRQHandler\r
+#define IRQ_Hdlr_2   ERU0_1_IRQHandler\r
+#define IRQ_Hdlr_3   ERU0_2_IRQHandler\r
+#define IRQ_Hdlr_4   ERU0_3_IRQHandler\r
+#define IRQ_Hdlr_5   ERU1_0_IRQHandler\r
+#define IRQ_Hdlr_6   ERU1_1_IRQHandler\r
+#define IRQ_Hdlr_7   ERU1_2_IRQHandler\r
+#define IRQ_Hdlr_8   ERU1_3_IRQHandler\r
+#define IRQ_Hdlr_12  PMU0_0_IRQHandler\r
+#define IRQ_Hdlr_14  VADC0_C0_0_IRQHandler\r
+#define IRQ_Hdlr_15  VADC0_C0_1_IRQHandler\r
+#define IRQ_Hdlr_16  VADC0_C0_2_IRQHandler\r
+#define IRQ_Hdlr_17  VADC0_C0_3_IRQHandler\r
+#define IRQ_Hdlr_18  VADC0_G0_0_IRQHandler\r
+#define IRQ_Hdlr_19  VADC0_G0_1_IRQHandler\r
+#define IRQ_Hdlr_20  VADC0_G0_2_IRQHandler\r
+#define IRQ_Hdlr_21  VADC0_G0_3_IRQHandler\r
+#define IRQ_Hdlr_22  VADC0_G1_0_IRQHandler\r
+#define IRQ_Hdlr_23  VADC0_G1_1_IRQHandler\r
+#define IRQ_Hdlr_24  VADC0_G1_2_IRQHandler\r
+#define IRQ_Hdlr_25  VADC0_G1_3_IRQHandler\r
+#define IRQ_Hdlr_26  VADC0_G2_0_IRQHandler\r
+#define IRQ_Hdlr_27  VADC0_G2_1_IRQHandler\r
+#define IRQ_Hdlr_28  VADC0_G2_2_IRQHandler\r
+#define IRQ_Hdlr_29  VADC0_G2_3_IRQHandler\r
+#define IRQ_Hdlr_30  VADC0_G3_0_IRQHandler\r
+#define IRQ_Hdlr_31  VADC0_G3_1_IRQHandler\r
+#define IRQ_Hdlr_32  VADC0_G3_2_IRQHandler\r
+#define IRQ_Hdlr_33  VADC0_G3_3_IRQHandler\r
+#define IRQ_Hdlr_34  DSD0_0_IRQHandler\r
+#define IRQ_Hdlr_35  DSD0_1_IRQHandler\r
+#define IRQ_Hdlr_36  DSD0_2_IRQHandler\r
+#define IRQ_Hdlr_37  DSD0_3_IRQHandler\r
+#define IRQ_Hdlr_38  DSD0_4_IRQHandler\r
+#define IRQ_Hdlr_39  DSD0_5_IRQHandler\r
+#define IRQ_Hdlr_40  DSD0_6_IRQHandler\r
+#define IRQ_Hdlr_41  DSD0_7_IRQHandler\r
+#define IRQ_Hdlr_42  DAC0_0_IRQHandler\r
+#define IRQ_Hdlr_43  DAC0_1_IRQHandler\r
+#define IRQ_Hdlr_44  CCU40_0_IRQHandler\r
+#define IRQ_Hdlr_45  CCU40_1_IRQHandler\r
+#define IRQ_Hdlr_46  CCU40_2_IRQHandler\r
+#define IRQ_Hdlr_47  CCU40_3_IRQHandler\r
+#define IRQ_Hdlr_48  CCU41_0_IRQHandler\r
+#define IRQ_Hdlr_49  CCU41_1_IRQHandler\r
+#define IRQ_Hdlr_50  CCU41_2_IRQHandler\r
+#define IRQ_Hdlr_51  CCU41_3_IRQHandler\r
+#define IRQ_Hdlr_52  CCU42_0_IRQHandler\r
+#define IRQ_Hdlr_53  CCU42_1_IRQHandler\r
+#define IRQ_Hdlr_54  CCU42_2_IRQHandler\r
+#define IRQ_Hdlr_55  CCU42_3_IRQHandler\r
+#define IRQ_Hdlr_56  CCU43_0_IRQHandler\r
+#define IRQ_Hdlr_57  CCU43_1_IRQHandler\r
+#define IRQ_Hdlr_58  CCU43_2_IRQHandler\r
+#define IRQ_Hdlr_59  CCU43_3_IRQHandler\r
+#define IRQ_Hdlr_60  CCU80_0_IRQHandler\r
+#define IRQ_Hdlr_61  CCU80_1_IRQHandler\r
+#define IRQ_Hdlr_62  CCU80_2_IRQHandler\r
+#define IRQ_Hdlr_63  CCU80_3_IRQHandler\r
+#define IRQ_Hdlr_64  CCU81_0_IRQHandler\r
+#define IRQ_Hdlr_65  CCU81_1_IRQHandler\r
+#define IRQ_Hdlr_66  CCU81_2_IRQHandler\r
+#define IRQ_Hdlr_67  CCU81_3_IRQHandler\r
+#define IRQ_Hdlr_68  POSIF0_0_IRQHandler\r
+#define IRQ_Hdlr_69  POSIF0_1_IRQHandler\r
+#define IRQ_Hdlr_70  POSIF1_0_IRQHandler\r
+#define IRQ_Hdlr_71  POSIF1_1_IRQHandler\r
+#define IRQ_Hdlr_76  CAN0_0_IRQHandler\r
+#define IRQ_Hdlr_77  CAN0_1_IRQHandler\r
+#define IRQ_Hdlr_78  CAN0_2_IRQHandler\r
+#define IRQ_Hdlr_79  CAN0_3_IRQHandler\r
+#define IRQ_Hdlr_80  CAN0_4_IRQHandler\r
+#define IRQ_Hdlr_81  CAN0_5_IRQHandler\r
+#define IRQ_Hdlr_82  CAN0_6_IRQHandler\r
+#define IRQ_Hdlr_83  CAN0_7_IRQHandler\r
+#define IRQ_Hdlr_84  USIC0_0_IRQHandler\r
+#define IRQ_Hdlr_85  USIC0_1_IRQHandler\r
+#define IRQ_Hdlr_86  USIC0_2_IRQHandler\r
+#define IRQ_Hdlr_87  USIC0_3_IRQHandler\r
+#define IRQ_Hdlr_88  USIC0_4_IRQHandler\r
+#define IRQ_Hdlr_89  USIC0_5_IRQHandler\r
+#define IRQ_Hdlr_90  USIC1_0_IRQHandler\r
+#define IRQ_Hdlr_91  USIC1_1_IRQHandler\r
+#define IRQ_Hdlr_92  USIC1_2_IRQHandler\r
+#define IRQ_Hdlr_93  USIC1_3_IRQHandler\r
+#define IRQ_Hdlr_94  USIC1_4_IRQHandler\r
+#define IRQ_Hdlr_95  USIC1_5_IRQHandler\r
+#define IRQ_Hdlr_96  USIC2_0_IRQHandler\r
+#define IRQ_Hdlr_97  USIC2_1_IRQHandler\r
+#define IRQ_Hdlr_98  USIC2_2_IRQHandler\r
+#define IRQ_Hdlr_99  USIC2_3_IRQHandler\r
+#define IRQ_Hdlr_100 USIC2_4_IRQHandler\r
+#define IRQ_Hdlr_101 USIC2_5_IRQHandler\r
+#define IRQ_Hdlr_102 LEDTS0_0_IRQHandler\r
+#define IRQ_Hdlr_104 FCE0_0_IRQHandler\r
+#define IRQ_Hdlr_105 GPDMA0_0_IRQHandler\r
+#define IRQ_Hdlr_106 SDMMC0_0_IRQHandler\r
+#define IRQ_Hdlr_107 USB0_0_IRQHandler\r
+#define IRQ_Hdlr_108 ETH0_0_IRQHandler\r
+#define IRQ_Hdlr_110 GPDMA1_0_IRQHandler\r
+\r
+/*\r
+* ==========================================================================\r
+* ---------- Interrupt Handler retrieval macro -----------------------------\r
+* ==========================================================================\r
+*/\r
+#define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N\r
+\r
+/** @addtogroup Device_Peripheral_Registers\r
+  * @{\r
+  */\r
+\r
+\r
+/* -------------------  Start of section using anonymous unions  ------------------ */\r
+#if defined(__CC_ARM)\r
+  #pragma push\r
+  #pragma anon_unions\r
+#elif defined(__ICCARM__)\r
+  #pragma language=extended\r
+#elif defined(__GNUC__)\r
+  /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+/* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+  #pragma warning 586\r
+#else\r
+  #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       PPB                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Cortex-M4 Private Peripheral Block (PPB)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0xE000E000) PPB Structure                                          */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  ACTLR;                             /*!< (@ 0xE000E008) Auxiliary Control Register                             */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  SYST_CSR;                          /*!< (@ 0xE000E010) SysTick Control and Status Register                    */\r
+  __IO uint32_t  SYST_RVR;                          /*!< (@ 0xE000E014) SysTick Reload Value Register                          */\r
+  __IO uint32_t  SYST_CVR;                          /*!< (@ 0xE000E018) SysTick Current Value Register                         */\r
+  __IO uint32_t  SYST_CALIB;                        /*!< (@ 0xE000E01C) SysTick Calibration Value Register r                   */\r
+  __I  uint32_t  RESERVED2[56];\r
+  __IO uint32_t  NVIC_ISER0;                        /*!< (@ 0xE000E100) Interrupt Set-enable Register 0                        */\r
+  __IO uint32_t  NVIC_ISER1;                        /*!< (@ 0xE000E104) Interrupt Set-enable Register 1                        */\r
+  __IO uint32_t  NVIC_ISER2;                        /*!< (@ 0xE000E108) Interrupt Set-enable Register 2                        */\r
+  __IO uint32_t  NVIC_ISER3;                        /*!< (@ 0xE000E10C) Interrupt Set-enable Register 3                        */\r
+  __I  uint32_t  RESERVED3[28];\r
+  __IO uint32_t  NVIC_ICER0;                        /*!< (@ 0xE000E180) Interrupt Clear-enable Register 0                      */\r
+  __IO uint32_t  NVIC_ICER1;                        /*!< (@ 0xE000E184) Interrupt Clear-enable Register 1                      */\r
+  __IO uint32_t  NVIC_ICER2;                        /*!< (@ 0xE000E188) Interrupt Clear-enable Register 2                      */\r
+  __IO uint32_t  NVIC_ICER3;                        /*!< (@ 0xE000E18C) Interrupt Clear-enable Register 3                      */\r
+  __I  uint32_t  RESERVED4[28];\r
+  __IO uint32_t  NVIC_ISPR0;                        /*!< (@ 0xE000E200) Interrupt Set-pending Register 0                       */\r
+  __IO uint32_t  NVIC_ISPR1;                        /*!< (@ 0xE000E204) Interrupt Set-pending Register 1                       */\r
+  __IO uint32_t  NVIC_ISPR2;                        /*!< (@ 0xE000E208) Interrupt Set-pending Register 2                       */\r
+  __IO uint32_t  NVIC_ISPR3;                        /*!< (@ 0xE000E20C) Interrupt Set-pending Register 3                       */\r
+  __I  uint32_t  RESERVED5[28];\r
+  __IO uint32_t  NVIC_ICPR0;                        /*!< (@ 0xE000E280) Interrupt Clear-pending Register 0                     */\r
+  __IO uint32_t  NVIC_ICPR1;                        /*!< (@ 0xE000E284) Interrupt Clear-pending Register 1                     */\r
+  __IO uint32_t  NVIC_ICPR2;                        /*!< (@ 0xE000E288) Interrupt Clear-pending Register 2                     */\r
+  __IO uint32_t  NVIC_ICPR3;                        /*!< (@ 0xE000E28C) Interrupt Clear-pending Register 3                     */\r
+  __I  uint32_t  RESERVED6[28];\r
+  __IO uint32_t  NVIC_IABR0;                        /*!< (@ 0xE000E300) Interrupt Active Bit Register 0                        */\r
+  __IO uint32_t  NVIC_IABR1;                        /*!< (@ 0xE000E304) Interrupt Active Bit Register 1                        */\r
+  __IO uint32_t  NVIC_IABR2;                        /*!< (@ 0xE000E308) Interrupt Active Bit Register 2                        */\r
+  __IO uint32_t  NVIC_IABR3;                        /*!< (@ 0xE000E30C) Interrupt Active Bit Register 3                        */\r
+  __I  uint32_t  RESERVED7[60];\r
+  __IO uint32_t  NVIC_IPR0;                         /*!< (@ 0xE000E400) Interrupt Priority Register 0                          */\r
+  __IO uint32_t  NVIC_IPR1;                         /*!< (@ 0xE000E404) Interrupt Priority Register 1                          */\r
+  __IO uint32_t  NVIC_IPR2;                         /*!< (@ 0xE000E408) Interrupt Priority Register 2                          */\r
+  __IO uint32_t  NVIC_IPR3;                         /*!< (@ 0xE000E40C) Interrupt Priority Register 3                          */\r
+  __IO uint32_t  NVIC_IPR4;                         /*!< (@ 0xE000E410) Interrupt Priority Register 4                          */\r
+  __IO uint32_t  NVIC_IPR5;                         /*!< (@ 0xE000E414) Interrupt Priority Register 5                          */\r
+  __IO uint32_t  NVIC_IPR6;                         /*!< (@ 0xE000E418) Interrupt Priority Register 6                          */\r
+  __IO uint32_t  NVIC_IPR7;                         /*!< (@ 0xE000E41C) Interrupt Priority Register 7                          */\r
+  __IO uint32_t  NVIC_IPR8;                         /*!< (@ 0xE000E420) Interrupt Priority Register 8                          */\r
+  __IO uint32_t  NVIC_IPR9;                         /*!< (@ 0xE000E424) Interrupt Priority Register 9                          */\r
+  __IO uint32_t  NVIC_IPR10;                        /*!< (@ 0xE000E428) Interrupt Priority Register 10                         */\r
+  __IO uint32_t  NVIC_IPR11;                        /*!< (@ 0xE000E42C) Interrupt Priority Register 11                         */\r
+  __IO uint32_t  NVIC_IPR12;                        /*!< (@ 0xE000E430) Interrupt Priority Register 12                         */\r
+  __IO uint32_t  NVIC_IPR13;                        /*!< (@ 0xE000E434) Interrupt Priority Register 13                         */\r
+  __IO uint32_t  NVIC_IPR14;                        /*!< (@ 0xE000E438) Interrupt Priority Register 14                         */\r
+  __IO uint32_t  NVIC_IPR15;                        /*!< (@ 0xE000E43C) Interrupt Priority Register 15                         */\r
+  __IO uint32_t  NVIC_IPR16;                        /*!< (@ 0xE000E440) Interrupt Priority Register 16                         */\r
+  __IO uint32_t  NVIC_IPR17;                        /*!< (@ 0xE000E444) Interrupt Priority Register 17                         */\r
+  __IO uint32_t  NVIC_IPR18;                        /*!< (@ 0xE000E448) Interrupt Priority Register 18                         */\r
+  __IO uint32_t  NVIC_IPR19;                        /*!< (@ 0xE000E44C) Interrupt Priority Register 19                         */\r
+  __IO uint32_t  NVIC_IPR20;                        /*!< (@ 0xE000E450) Interrupt Priority Register 20                         */\r
+  __IO uint32_t  NVIC_IPR21;                        /*!< (@ 0xE000E454) Interrupt Priority Register 21                         */\r
+  __IO uint32_t  NVIC_IPR22;                        /*!< (@ 0xE000E458) Interrupt Priority Register 22                         */\r
+  __IO uint32_t  NVIC_IPR23;                        /*!< (@ 0xE000E45C) Interrupt Priority Register 23                         */\r
+  __IO uint32_t  NVIC_IPR24;                        /*!< (@ 0xE000E460) Interrupt Priority Register 24                         */\r
+  __IO uint32_t  NVIC_IPR25;                        /*!< (@ 0xE000E464) Interrupt Priority Register 25                         */\r
+  __IO uint32_t  NVIC_IPR26;                        /*!< (@ 0xE000E468) Interrupt Priority Register 26                         */\r
+  __IO uint32_t  NVIC_IPR27;                        /*!< (@ 0xE000E46C) Interrupt Priority Register 27                         */\r
+  __I  uint32_t  RESERVED8[548];\r
+  __I  uint32_t  CPUID;                             /*!< (@ 0xE000ED00) CPUID Base Register                                    */\r
+  __IO uint32_t  ICSR;                              /*!< (@ 0xE000ED04) Interrupt Control and State Register                   */\r
+  __IO uint32_t  VTOR;                              /*!< (@ 0xE000ED08) Vector Table Offset Register                           */\r
+  __IO uint32_t  AIRCR;                             /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register       */\r
+  __IO uint32_t  SCR;                               /*!< (@ 0xE000ED10) System Control Register                                */\r
+  __IO uint32_t  CCR;                               /*!< (@ 0xE000ED14) Configuration and Control Register                     */\r
+  __IO uint32_t  SHPR1;                             /*!< (@ 0xE000ED18) System Handler Priority Register 1                     */\r
+  __IO uint32_t  SHPR2;                             /*!< (@ 0xE000ED1C) System Handler Priority Register 2                     */\r
+  __IO uint32_t  SHPR3;                             /*!< (@ 0xE000ED20) System Handler Priority Register 3                     */\r
+  __IO uint32_t  SHCSR;                             /*!< (@ 0xE000ED24) System Handler Control and State Register              */\r
+  __IO uint32_t  CFSR;                              /*!< (@ 0xE000ED28) Configurable Fault Status Register                     */\r
+  __IO uint32_t  HFSR;                              /*!< (@ 0xE000ED2C) HardFault Status Register                              */\r
+  __I  uint32_t  RESERVED9;\r
+  __IO uint32_t  MMFAR;                             /*!< (@ 0xE000ED34) MemManage Fault Address Register                       */\r
+  __IO uint32_t  BFAR;                              /*!< (@ 0xE000ED38) BusFault Address Register                              */\r
+  __IO uint32_t  AFSR;                              /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register                        */\r
+  __I  uint32_t  RESERVED10[18];\r
+  __IO uint32_t  CPACR;                             /*!< (@ 0xE000ED88) Coprocessor Access Control Register                    */\r
+  __I  uint32_t  RESERVED11;\r
+  __I  uint32_t  MPU_TYPE;                          /*!< (@ 0xE000ED90) MPU Type Register                                      */\r
+  __IO uint32_t  MPU_CTRL;                          /*!< (@ 0xE000ED94) MPU Control Register                                   */\r
+  __IO uint32_t  MPU_RNR;                           /*!< (@ 0xE000ED98) MPU Region Number Register                             */\r
+  __IO uint32_t  MPU_RBAR;                          /*!< (@ 0xE000ED9C) MPU Region Base Address Register                       */\r
+  __IO uint32_t  MPU_RASR;                          /*!< (@ 0xE000EDA0) MPU Region Attribute and Size Register                 */\r
+  __IO uint32_t  MPU_RBAR_A1;                       /*!< (@ 0xE000EDA4) MPU Region Base Address Register A1                    */\r
+  __IO uint32_t  MPU_RASR_A1;                       /*!< (@ 0xE000EDA8) MPU Region Attribute and Size Register A1              */\r
+  __IO uint32_t  MPU_RBAR_A2;                       /*!< (@ 0xE000EDAC) MPU Region Base Address Register A2                    */\r
+  __IO uint32_t  MPU_RASR_A2;                       /*!< (@ 0xE000EDB0) MPU Region Attribute and Size Register A2              */\r
+  __IO uint32_t  MPU_RBAR_A3;                       /*!< (@ 0xE000EDB4) MPU Region Base Address Register A3                    */\r
+  __IO uint32_t  MPU_RASR_A3;                       /*!< (@ 0xE000EDB8) MPU Region Attribute and Size Register A3              */\r
+  __I  uint32_t  RESERVED12[81];\r
+  __O  uint32_t  STIR;                              /*!< (@ 0xE000EF00) Software Trigger Interrupt Register                    */\r
+  __I  uint32_t  RESERVED13[12];\r
+  __IO uint32_t  FPCCR;                             /*!< (@ 0xE000EF34) Floating-point Context Control Register                */\r
+  __IO uint32_t  FPCAR;                             /*!< (@ 0xE000EF38) Floating-point Context Address Register                */\r
+  __IO uint32_t  FPDSCR;                            /*!< (@ 0xE000EF3C) Floating-point Default Status Control Register         */\r
+} PPB_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       DLR                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief DMA Line Router (DLR)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004900) DLR Structure                                          */\r
+  __I  uint32_t  OVRSTAT;                           /*!< (@ 0x50004900) Overrun Status                                         */\r
+  __O  uint32_t  OVRCLR;                            /*!< (@ 0x50004904) Overrun Clear                                          */\r
+  __IO uint32_t  SRSEL0;                            /*!< (@ 0x50004908) Service Request Selection 0                            */\r
+  __IO uint32_t  SRSEL1;                            /*!< (@ 0x5000490C) Service Request Selection 1                            */\r
+  __IO uint32_t  LNEN;                              /*!< (@ 0x50004910) Line Enable                                            */\r
+} DLR_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   ERU [ERU0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Event Request Unit 0 (ERU)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004800) ERU Structure                                          */\r
+  __IO uint32_t  EXISEL;                            /*!< (@ 0x50004800) Event Input Select                                     */\r
+  __I  uint32_t  RESERVED0[3];\r
+  __IO uint32_t  EXICON[4];                         /*!< (@ 0x50004810) Event Input Control                                    */\r
+  __IO uint32_t  EXOCON[4];                         /*!< (@ 0x50004820) Event Output Trigger Control                           */\r
+} ERU_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     GPDMA0                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief General Purpose DMA Unit 0 (GPDMA0)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x500142C0) GPDMA0 Structure                                       */\r
+  __IO uint32_t  RAWTFR;                            /*!< (@ 0x500142C0) Raw IntTfr Status                                      */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  RAWBLOCK;                          /*!< (@ 0x500142C8) Raw IntBlock Status                                    */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  RAWSRCTRAN;                        /*!< (@ 0x500142D0) Raw IntSrcTran Status                                  */\r
+  __I  uint32_t  RESERVED2;\r
+  __IO uint32_t  RAWDSTTRAN;                        /*!< (@ 0x500142D8) Raw IntBlock Status                                    */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  RAWERR;                            /*!< (@ 0x500142E0) Raw IntErr Status                                      */\r
+  __I  uint32_t  RESERVED4;\r
+  __I  uint32_t  STATUSTFR;                         /*!< (@ 0x500142E8) IntTfr Status                                          */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  STATUSBLOCK;                       /*!< (@ 0x500142F0) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED6;\r
+  __I  uint32_t  STATUSSRCTRAN;                     /*!< (@ 0x500142F8) IntSrcTran Status                                      */\r
+  __I  uint32_t  RESERVED7;\r
+  __I  uint32_t  STATUSDSTTRAN;                     /*!< (@ 0x50014300) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED8;\r
+  __I  uint32_t  STATUSERR;                         /*!< (@ 0x50014308) IntErr Status                                          */\r
+  __I  uint32_t  RESERVED9;\r
+  __IO uint32_t  MASKTFR;                           /*!< (@ 0x50014310) Mask for Raw IntTfr Status                             */\r
+  __I  uint32_t  RESERVED10;\r
+  __IO uint32_t  MASKBLOCK;                         /*!< (@ 0x50014318) Mask for Raw IntBlock Status                           */\r
+  __I  uint32_t  RESERVED11;\r
+  __IO uint32_t  MASKSRCTRAN;                       /*!< (@ 0x50014320) Mask for Raw IntSrcTran Status                         */\r
+  __I  uint32_t  RESERVED12;\r
+  __IO uint32_t  MASKDSTTRAN;                       /*!< (@ 0x50014328) Mask for Raw IntBlock Status                           */\r
+  __I  uint32_t  RESERVED13;\r
+  __IO uint32_t  MASKERR;                           /*!< (@ 0x50014330) Mask for Raw IntErr Status                             */\r
+  __I  uint32_t  RESERVED14;\r
+  __O  uint32_t  CLEARTFR;                          /*!< (@ 0x50014338) IntTfr Status                                          */\r
+  __I  uint32_t  RESERVED15;\r
+  __O  uint32_t  CLEARBLOCK;                        /*!< (@ 0x50014340) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED16;\r
+  __O  uint32_t  CLEARSRCTRAN;                      /*!< (@ 0x50014348) IntSrcTran Status                                      */\r
+  __I  uint32_t  RESERVED17;\r
+  __O  uint32_t  CLEARDSTTRAN;                      /*!< (@ 0x50014350) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED18;\r
+  __O  uint32_t  CLEARERR;                          /*!< (@ 0x50014358) IntErr Status                                          */\r
+  __I  uint32_t  RESERVED19;\r
+  __I  uint32_t  STATUSINT;                         /*!< (@ 0x50014360) Combined Interrupt Status Register                     */\r
+  __I  uint32_t  RESERVED20;\r
+  __IO uint32_t  REQSRCREG;                         /*!< (@ 0x50014368) Source Software Transaction Request Register           */\r
+  __I  uint32_t  RESERVED21;\r
+  __IO uint32_t  REQDSTREG;                         /*!< (@ 0x50014370) Destination Software Transaction Request Register      */\r
+  __I  uint32_t  RESERVED22;\r
+  __IO uint32_t  SGLREQSRCREG;                      /*!< (@ 0x50014378) Single Source Transaction Request Register             */\r
+  __I  uint32_t  RESERVED23;\r
+  __IO uint32_t  SGLREQDSTREG;                      /*!< (@ 0x50014380) Single Destination Transaction Request Register        */\r
+  __I  uint32_t  RESERVED24;\r
+  __IO uint32_t  LSTSRCREG;                         /*!< (@ 0x50014388) Last Source Transaction Request Register               */\r
+  __I  uint32_t  RESERVED25;\r
+  __IO uint32_t  LSTDSTREG;                         /*!< (@ 0x50014390) Last Destination Transaction Request Register          */\r
+  __I  uint32_t  RESERVED26;\r
+  __IO uint32_t  DMACFGREG;                         /*!< (@ 0x50014398) GPDMA Configuration Register                           */\r
+  __I  uint32_t  RESERVED27;\r
+  __IO uint32_t  CHENREG;                           /*!< (@ 0x500143A0) GPDMA Channel Enable Register                          */\r
+  __I  uint32_t  RESERVED28;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x500143A8) GPDMA0 ID Register                                     */\r
+  __I  uint32_t  RESERVED29[19];\r
+  __I  uint32_t  TYPE;                              /*!< (@ 0x500143F8) GPDMA Component Type                                   */\r
+  __I  uint32_t  VERSION;                           /*!< (@ 0x500143FC) DMA Component Version                                  */\r
+} GPDMA0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================            GPDMA0_CH0_1 [GPDMA0_CH0]           ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief General Purpose DMA Unit 0 (GPDMA0_CH0_1)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50014000) GPDMA0_CH0_1 Structure                                 */\r
+  __IO uint32_t  SAR;                               /*!< (@ 0x50014000) Source Address Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DAR;                               /*!< (@ 0x50014008) Destination Address Register                           */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  LLP;                               /*!< (@ 0x50014010) Linked List Pointer Register                           */\r
+  __I  uint32_t  RESERVED2;\r
+  __IO uint32_t  CTLL;                              /*!< (@ 0x50014018) Control Register Low                                   */\r
+  __IO uint32_t  CTLH;                              /*!< (@ 0x5001401C) Control Register High                                  */\r
+  __IO uint32_t  SSTAT;                             /*!< (@ 0x50014020) Source Status Register                                 */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  DSTAT;                             /*!< (@ 0x50014028) Destination Status Register                            */\r
+  __I  uint32_t  RESERVED4;\r
+  __IO uint32_t  SSTATAR;                           /*!< (@ 0x50014030) Source Status Address Register                         */\r
+  __I  uint32_t  RESERVED5;\r
+  __IO uint32_t  DSTATAR;                           /*!< (@ 0x50014038) Destination Status Address Register                    */\r
+  __I  uint32_t  RESERVED6;\r
+  __IO uint32_t  CFGL;                              /*!< (@ 0x50014040) Configuration Register Low                             */\r
+  __IO uint32_t  CFGH;                              /*!< (@ 0x50014044) Configuration Register High                            */\r
+  __IO uint32_t  SGR;                               /*!< (@ 0x50014048) Source Gather Register                                 */\r
+  __I  uint32_t  RESERVED7;\r
+  __IO uint32_t  DSR;                               /*!< (@ 0x50014050) Destination Scatter Register                           */\r
+} GPDMA0_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================            GPDMA0_CH2_7 [GPDMA0_CH2]           ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief General Purpose DMA Unit 0 (GPDMA0_CH2_7)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x500140B0) GPDMA0_CH2_7 Structure                                 */\r
+  __IO uint32_t  SAR;                               /*!< (@ 0x500140B0) Source Address Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DAR;                               /*!< (@ 0x500140B8) Destination Address Register                           */\r
+  __I  uint32_t  RESERVED1[3];\r
+  __IO uint32_t  CTLL;                              /*!< (@ 0x500140C8) Control Register Low                                   */\r
+  __IO uint32_t  CTLH;                              /*!< (@ 0x500140CC) Control Register High                                  */\r
+  __I  uint32_t  RESERVED2[8];\r
+  __IO uint32_t  CFGL;                              /*!< (@ 0x500140F0) Configuration Register Low                             */\r
+  __IO uint32_t  CFGH;                              /*!< (@ 0x500140F4) Configuration Register High                            */\r
+} GPDMA0_CH2_7_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     GPDMA1                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief General Purpose DMA Unit 1 (GPDMA1)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x500182C0) GPDMA1 Structure                                       */\r
+  __IO uint32_t  RAWTFR;                            /*!< (@ 0x500182C0) Raw IntTfr Status                                      */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  RAWBLOCK;                          /*!< (@ 0x500182C8) Raw IntBlock Status                                    */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  RAWSRCTRAN;                        /*!< (@ 0x500182D0) Raw IntSrcTran Status                                  */\r
+  __I  uint32_t  RESERVED2;\r
+  __IO uint32_t  RAWDSTTRAN;                        /*!< (@ 0x500182D8) Raw IntBlock Status                                    */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  RAWERR;                            /*!< (@ 0x500182E0) Raw IntErr Status                                      */\r
+  __I  uint32_t  RESERVED4;\r
+  __I  uint32_t  STATUSTFR;                         /*!< (@ 0x500182E8) IntTfr Status                                          */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  STATUSBLOCK;                       /*!< (@ 0x500182F0) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED6;\r
+  __I  uint32_t  STATUSSRCTRAN;                     /*!< (@ 0x500182F8) IntSrcTran Status                                      */\r
+  __I  uint32_t  RESERVED7;\r
+  __I  uint32_t  STATUSDSTTRAN;                     /*!< (@ 0x50018300) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED8;\r
+  __I  uint32_t  STATUSERR;                         /*!< (@ 0x50018308) IntErr Status                                          */\r
+  __I  uint32_t  RESERVED9;\r
+  __IO uint32_t  MASKTFR;                           /*!< (@ 0x50018310) Mask for Raw IntTfr Status                             */\r
+  __I  uint32_t  RESERVED10;\r
+  __IO uint32_t  MASKBLOCK;                         /*!< (@ 0x50018318) Mask for Raw IntBlock Status                           */\r
+  __I  uint32_t  RESERVED11;\r
+  __IO uint32_t  MASKSRCTRAN;                       /*!< (@ 0x50018320) Mask for Raw IntSrcTran Status                         */\r
+  __I  uint32_t  RESERVED12;\r
+  __IO uint32_t  MASKDSTTRAN;                       /*!< (@ 0x50018328) Mask for Raw IntBlock Status                           */\r
+  __I  uint32_t  RESERVED13;\r
+  __IO uint32_t  MASKERR;                           /*!< (@ 0x50018330) Mask for Raw IntErr Status                             */\r
+  __I  uint32_t  RESERVED14;\r
+  __O  uint32_t  CLEARTFR;                          /*!< (@ 0x50018338) IntTfr Status                                          */\r
+  __I  uint32_t  RESERVED15;\r
+  __O  uint32_t  CLEARBLOCK;                        /*!< (@ 0x50018340) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED16;\r
+  __O  uint32_t  CLEARSRCTRAN;                      /*!< (@ 0x50018348) IntSrcTran Status                                      */\r
+  __I  uint32_t  RESERVED17;\r
+  __O  uint32_t  CLEARDSTTRAN;                      /*!< (@ 0x50018350) IntBlock Status                                        */\r
+  __I  uint32_t  RESERVED18;\r
+  __O  uint32_t  CLEARERR;                          /*!< (@ 0x50018358) IntErr Status                                          */\r
+  __I  uint32_t  RESERVED19;\r
+  __I  uint32_t  STATUSINT;                         /*!< (@ 0x50018360) Combined Interrupt Status Register                     */\r
+  __I  uint32_t  RESERVED20;\r
+  __IO uint32_t  REQSRCREG;                         /*!< (@ 0x50018368) Source Software Transaction Request Register           */\r
+  __I  uint32_t  RESERVED21;\r
+  __IO uint32_t  REQDSTREG;                         /*!< (@ 0x50018370) Destination Software Transaction Request Register      */\r
+  __I  uint32_t  RESERVED22;\r
+  __IO uint32_t  SGLREQSRCREG;                      /*!< (@ 0x50018378) Single Source Transaction Request Register             */\r
+  __I  uint32_t  RESERVED23;\r
+  __IO uint32_t  SGLREQDSTREG;                      /*!< (@ 0x50018380) Single Destination Transaction Request Register        */\r
+  __I  uint32_t  RESERVED24;\r
+  __IO uint32_t  LSTSRCREG;                         /*!< (@ 0x50018388) Last Source Transaction Request Register               */\r
+  __I  uint32_t  RESERVED25;\r
+  __IO uint32_t  LSTDSTREG;                         /*!< (@ 0x50018390) Last Destination Transaction Request Register          */\r
+  __I  uint32_t  RESERVED26;\r
+  __IO uint32_t  DMACFGREG;                         /*!< (@ 0x50018398) GPDMA Configuration Register                           */\r
+  __I  uint32_t  RESERVED27;\r
+  __IO uint32_t  CHENREG;                           /*!< (@ 0x500183A0) GPDMA Channel Enable Register                          */\r
+  __I  uint32_t  RESERVED28;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x500183A8) GPDMA1 ID Register                                     */\r
+  __I  uint32_t  RESERVED29[19];\r
+  __I  uint32_t  TYPE;                              /*!< (@ 0x500183F8) GPDMA Component Type                                   */\r
+  __I  uint32_t  VERSION;                           /*!< (@ 0x500183FC) DMA Component Version                                  */\r
+} GPDMA1_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================             GPDMA1_CH [GPDMA1_CH0]             ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief General Purpose DMA Unit 1 (GPDMA1_CH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50018000) GPDMA1_CH Structure                                    */\r
+  __IO uint32_t  SAR;                               /*!< (@ 0x50018000) Source Address Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DAR;                               /*!< (@ 0x50018008) Destination Address Register                           */\r
+  __I  uint32_t  RESERVED1[3];\r
+  __IO uint32_t  CTLL;                              /*!< (@ 0x50018018) Control Register Low                                   */\r
+  __IO uint32_t  CTLH;                              /*!< (@ 0x5001801C) Control Register High                                  */\r
+  __I  uint32_t  RESERVED2[8];\r
+  __IO uint32_t  CFGL;                              /*!< (@ 0x50018040) Configuration Register Low                             */\r
+  __IO uint32_t  CFGH;                              /*!< (@ 0x50018044) Configuration Register High                            */\r
+} GPDMA1_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       FCE                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Flexible CRC Engine (FCE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50020000) FCE Structure                                          */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x50020000) Clock Control Register                                 */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50020008) Module Identification Register                         */\r
+} FCE_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                FCE_KE [FCE_KE0]                ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Flexible CRC Engine (FCE_KE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50020020) FCE_KE Structure                                       */\r
+  __IO uint32_t  IR;                                /*!< (@ 0x50020020) Input Register                                         */\r
+  __I  uint32_t  RES;                               /*!< (@ 0x50020024) CRC Result Register                                    */\r
+  __IO uint32_t  CFG;                               /*!< (@ 0x50020028) CRC Configuration Register                             */\r
+  __IO uint32_t  STS;                               /*!< (@ 0x5002002C) CRC Status Register                                    */\r
+  __IO uint32_t  LENGTH;                            /*!< (@ 0x50020030) CRC Length Register                                    */\r
+  __IO uint32_t  CHECK;                             /*!< (@ 0x50020034) CRC Check Register                                     */\r
+  __IO uint32_t  CRC;                               /*!< (@ 0x50020038) CRC Register                                           */\r
+  __IO uint32_t  CTR;                               /*!< (@ 0x5002003C) CRC Test Register                                      */\r
+} FCE_KE_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   PBA [PBA0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Peripheral Bridge AHB 0 (PBA)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40000000) PBA Structure                                          */\r
+  __IO uint32_t  STS;                               /*!< (@ 0x40000000) Peripheral Bridge Status Register                      */\r
+  __I  uint32_t  WADDR;                             /*!< (@ 0x40000004) PBA Write Error Address Register                       */\r
+} PBA_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                 FLASH [FLASH0]                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Flash Memory Controller (FLASH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x58001000) FLASH Structure                                        */\r
+  __I  uint32_t  RESERVED0[1026];\r
+  __I  uint32_t  ID;                                /*!< (@ 0x58002008) Flash Module Identification Register                   */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  FSR;                               /*!< (@ 0x58002010) Flash Status Register                                  */\r
+  __IO uint32_t  FCON;                              /*!< (@ 0x58002014) Flash Configuration Register                           */\r
+  __IO uint32_t  MARP;                              /*!< (@ 0x58002018) Margin Control Register PFLASH                         */\r
+  __I  uint32_t  RESERVED2;\r
+  __I  uint32_t  PROCON0;                           /*!< (@ 0x58002020) Flash Protection Configuration Register User\r
+                                                         0                                                                     */\r
+  __I  uint32_t  PROCON1;                           /*!< (@ 0x58002024) Flash Protection Configuration Register User\r
+                                                         1                                                                     */\r
+  __I  uint32_t  PROCON2;                           /*!< (@ 0x58002028) Flash Protection Configuration Register User\r
+                                                         2                                                                     */\r
+} FLASH0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PREF                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Prefetch Unit (PREF)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x58004000) PREF Structure                                         */\r
+  __IO uint32_t  PCON;                              /*!< (@ 0x58004000) Prefetch Configuration Register                        */\r
+} PREF_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   PMU [PMU0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Program Management Unit (PMU)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x58000508) PMU Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x58000508) PMU0 Identification Register                           */\r
+} PMU0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       WDT                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Watch Dog Timer (WDT)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50008000) WDT Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50008000) WDT ID Register                                        */\r
+  __IO uint32_t  CTR;                               /*!< (@ 0x50008004) WDT Control Register                                   */\r
+  __O  uint32_t  SRV;                               /*!< (@ 0x50008008) WDT Service Register                                   */\r
+  __I  uint32_t  TIM;                               /*!< (@ 0x5000800C) WDT Timer Register                                     */\r
+  __IO uint32_t  WLB;                               /*!< (@ 0x50008010) WDT Window Lower Bound Register                        */\r
+  __IO uint32_t  WUB;                               /*!< (@ 0x50008014) WDT Window Upper Bound Register                        */\r
+  __I  uint32_t  WDTSTS;                            /*!< (@ 0x50008018) WDT Status Register                                    */\r
+  __O  uint32_t  WDTCLR;                            /*!< (@ 0x5000801C) WDT Clear Register                                     */\r
+} WDT_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       RTC                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Real Time Clock (RTC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004A00) RTC Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50004A00) RTC ID Register                                        */\r
+  __IO uint32_t  CTR;                               /*!< (@ 0x50004A04) RTC Control Register                                   */\r
+  __I  uint32_t  RAWSTAT;                           /*!< (@ 0x50004A08) RTC Raw Service Request Register                       */\r
+  __I  uint32_t  STSSR;                             /*!< (@ 0x50004A0C) RTC Service Request Status Register                    */\r
+  __IO uint32_t  MSKSR;                             /*!< (@ 0x50004A10) RTC Service Request Mask Register                      */\r
+  __O  uint32_t  CLRSR;                             /*!< (@ 0x50004A14) RTC Clear Service Request Register                     */\r
+  __IO uint32_t  ATIM0;                             /*!< (@ 0x50004A18) RTC Alarm Time Register 0                              */\r
+  __IO uint32_t  ATIM1;                             /*!< (@ 0x50004A1C) RTC Alarm Time Register 1                              */\r
+  __IO uint32_t  TIM0;                              /*!< (@ 0x50004A20) RTC Time Register 0                                    */\r
+  __IO uint32_t  TIM1;                              /*!< (@ 0x50004A24) RTC Time Register 1                                    */\r
+} RTC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     SCU_CLK                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_CLK)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004600) SCU_CLK Structure                                      */\r
+  __I  uint32_t  CLKSTAT;                           /*!< (@ 0x50004600) Clock Status Register                                  */\r
+  __O  uint32_t  CLKSET;                            /*!< (@ 0x50004604) CLK Set Register                                       */\r
+  __O  uint32_t  CLKCLR;                            /*!< (@ 0x50004608) CLK Clear Register                                     */\r
+  __IO uint32_t  SYSCLKCR;                          /*!< (@ 0x5000460C) System Clock Control Register                          */\r
+  __IO uint32_t  CPUCLKCR;                          /*!< (@ 0x50004610) CPU Clock Control Register                             */\r
+  __IO uint32_t  PBCLKCR;                           /*!< (@ 0x50004614) Peripheral Bus Clock Control Register                  */\r
+  __IO uint32_t  USBCLKCR;                          /*!< (@ 0x50004618) USB Clock Control Register                             */\r
+  __IO uint32_t  EBUCLKCR;                          /*!< (@ 0x5000461C) EBU Clock Control Register                             */\r
+  __IO uint32_t  CCUCLKCR;                          /*!< (@ 0x50004620) CCU Clock Control Register                             */\r
+  __IO uint32_t  WDTCLKCR;                          /*!< (@ 0x50004624) WDT Clock Control Register                             */\r
+  __IO uint32_t  EXTCLKCR;                          /*!< (@ 0x50004628) External Clock Control                                 */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  SLEEPCR;                           /*!< (@ 0x50004630) Sleep Control Register                                 */\r
+  __IO uint32_t  DSLEEPCR;                          /*!< (@ 0x50004634) Deep Sleep Control Register                            */\r
+} SCU_CLK_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     SCU_OSC                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_OSC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004700) SCU_OSC Structure                                      */\r
+  __I  uint32_t  OSCHPSTAT;                         /*!< (@ 0x50004700) OSC_HP Status Register                                 */\r
+  __IO uint32_t  OSCHPCTRL;                         /*!< (@ 0x50004704) OSC_HP Control Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  CLKCALCONST;                       /*!< (@ 0x5000470C) Clock Calibration Constant Register                    */\r
+} SCU_OSC_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     SCU_PLL                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_PLL)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004710) SCU_PLL Structure                                      */\r
+  __I  uint32_t  PLLSTAT;                           /*!< (@ 0x50004710) PLL Status Register                                    */\r
+  __IO uint32_t  PLLCON0;                           /*!< (@ 0x50004714) PLL Configuration 0 Register                           */\r
+  __IO uint32_t  PLLCON1;                           /*!< (@ 0x50004718) PLL Configuration 1 Register                           */\r
+  __IO uint32_t  PLLCON2;                           /*!< (@ 0x5000471C) PLL Configuration 2 Register                           */\r
+  __I  uint32_t  USBPLLSTAT;                        /*!< (@ 0x50004720) USB PLL Status Register                                */\r
+  __IO uint32_t  USBPLLCON;                         /*!< (@ 0x50004724) USB PLL Configuration Register                         */\r
+  __I  uint32_t  RESERVED0[4];\r
+  __I  uint32_t  CLKMXSTAT;                         /*!< (@ 0x50004738) Clock Multiplexing Status Register                     */\r
+} SCU_PLL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   SCU_GENERAL                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_GENERAL)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004000) SCU_GENERAL Structure                                  */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x50004000) SCU Module ID Register                                 */\r
+  __I  uint32_t  IDCHIP;                            /*!< (@ 0x50004004) Chip ID Register                                       */\r
+  __I  uint32_t  IDMANUF;                           /*!< (@ 0x50004008) Manufactory ID Register                                */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  STCON;                             /*!< (@ 0x50004010) Startup Configuration Register                         */\r
+  __I  uint32_t  RESERVED1[6];\r
+  __IO uint32_t  GPR[2];                            /*!< (@ 0x5000402C) General Purpose Register 0                             */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  CCUCON;                            /*!< (@ 0x5000404C) CCU Control Register                                   */\r
+  __I  uint32_t  RESERVED3[15];\r
+  __IO uint32_t  DTSCON;                            /*!< (@ 0x5000408C) Die Temperature Sensor Control Register                */\r
+  __I  uint32_t  DTSSTAT;                           /*!< (@ 0x50004090) Die Temperature Sensor Status Register                 */\r
+  __I  uint32_t  RESERVED4[2];\r
+  __IO uint32_t  SDMMCDEL;                          /*!< (@ 0x5000409C) SD-MMC Delay Control Register                          */\r
+  __IO uint32_t  GORCEN[2];                         /*!< (@ 0x500040A0) Out of Range Comparator Enable Register 0              */\r
+  __I  uint32_t  RESERVED5[7];\r
+  __I  uint32_t  MIRRSTS;                           /*!< (@ 0x500040C4) Mirror Write Status Register                           */\r
+  __IO uint32_t  RMACR;                             /*!< (@ 0x500040C8) Retention Memory Access Control Register               */\r
+  __IO uint32_t  RMDATA;                            /*!< (@ 0x500040CC) Retention Memory Access Data Register                  */\r
+} SCU_GENERAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  SCU_INTERRUPT                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_INTERRUPT)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004074) SCU_INTERRUPT Structure                                */\r
+  __I  uint32_t  SRSTAT;                            /*!< (@ 0x50004074) SCU Service Request Status                             */\r
+  __I  uint32_t  SRRAW;                             /*!< (@ 0x50004078) SCU Raw Service Request Status                         */\r
+  __IO uint32_t  SRMSK;                             /*!< (@ 0x5000407C) SCU Service Request Mask                               */\r
+  __O  uint32_t  SRCLR;                             /*!< (@ 0x50004080) SCU Service Request Clear                              */\r
+  __O  uint32_t  SRSET;                             /*!< (@ 0x50004084) SCU Service Request Set                                */\r
+  __IO uint32_t  NMIREQEN;                          /*!< (@ 0x50004088) SCU Service Request Mask                               */\r
+} SCU_INTERRUPT_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   SCU_PARITY                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_PARITY)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x5000413C) SCU_PARITY Structure                                   */\r
+  __IO uint32_t  PEEN;                              /*!< (@ 0x5000413C) Parity Error Enable Register                           */\r
+  __IO uint32_t  MCHKCON;                           /*!< (@ 0x50004140) Memory Checking Control Register                       */\r
+  __IO uint32_t  PETE;                              /*!< (@ 0x50004144) Parity Error Trap Enable Register                      */\r
+  __IO uint32_t  PERSTEN;                           /*!< (@ 0x50004148) Parity Error Reset Enable Register                     */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  PEFLAG;                            /*!< (@ 0x50004150) Parity Error Flag Register                             */\r
+  __IO uint32_t  PMTPR;                             /*!< (@ 0x50004154) Parity Memory Test Pattern Register                    */\r
+  __IO uint32_t  PMTSR;                             /*!< (@ 0x50004158) Parity Memory Test Select Register                     */\r
+} SCU_PARITY_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    SCU_TRAP                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_TRAP)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004160) SCU_TRAP Structure                                     */\r
+  __I  uint32_t  TRAPSTAT;                          /*!< (@ 0x50004160) Trap Status Register                                   */\r
+  __I  uint32_t  TRAPRAW;                           /*!< (@ 0x50004164) Trap Raw Status Register                               */\r
+  __IO uint32_t  TRAPDIS;                           /*!< (@ 0x50004168) Trap Disable Register                                  */\r
+  __O  uint32_t  TRAPCLR;                           /*!< (@ 0x5000416C) Trap Clear Register                                    */\r
+  __O  uint32_t  TRAPSET;                           /*!< (@ 0x50004170) Trap Set Register                                      */\r
+} SCU_TRAP_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  SCU_HIBERNATE                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_HIBERNATE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004300) SCU_HIBERNATE Structure                                */\r
+  __I  uint32_t  HDSTAT;                            /*!< (@ 0x50004300) Hibernate Domain Status Register                       */\r
+  __O  uint32_t  HDCLR;                             /*!< (@ 0x50004304) Hibernate Domain Status Clear Register                 */\r
+  __O  uint32_t  HDSET;                             /*!< (@ 0x50004308) Hibernate Domain Status Set Register                   */\r
+  __IO uint32_t  HDCR;                              /*!< (@ 0x5000430C) Hibernate Domain Control Register                      */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  OSCSICTRL;                         /*!< (@ 0x50004314) fOSI Control Register                                  */\r
+  __I  uint32_t  OSCULSTAT;                         /*!< (@ 0x50004318) OSC_ULP Status Register                                */\r
+  __IO uint32_t  OSCULCTRL;                         /*!< (@ 0x5000431C) OSC_ULP Control Register                               */\r
+} SCU_HIBERNATE_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    SCU_POWER                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_POWER)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004200) SCU_POWER Structure                                    */\r
+  __I  uint32_t  PWRSTAT;                           /*!< (@ 0x50004200) PCU Status Register                                    */\r
+  __O  uint32_t  PWRSET;                            /*!< (@ 0x50004204) PCU Set Control Register                               */\r
+  __O  uint32_t  PWRCLR;                            /*!< (@ 0x50004208) PCU Clear Control Register                             */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  EVRSTAT;                           /*!< (@ 0x50004210) EVR Status Register                                    */\r
+  __I  uint32_t  EVRVADCSTAT;                       /*!< (@ 0x50004214) EVR VADC Status Register                               */\r
+  __I  uint32_t  RESERVED1[5];\r
+  __IO uint32_t  PWRMON;                            /*!< (@ 0x5000422C) Power Monitor Control                                  */\r
+} SCU_POWER_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    SCU_RESET                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief System Control Unit (SCU_RESET)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004400) SCU_RESET Structure                                    */\r
+  __I  uint32_t  RSTSTAT;                           /*!< (@ 0x50004400) RCU Reset Status                                       */\r
+  __O  uint32_t  RSTSET;                            /*!< (@ 0x50004404) RCU Reset Set Register                                 */\r
+  __O  uint32_t  RSTCLR;                            /*!< (@ 0x50004408) RCU Reset Clear Register                               */\r
+  __I  uint32_t  PRSTAT0;                           /*!< (@ 0x5000440C) RCU Peripheral 0 Reset Status                          */\r
+  __O  uint32_t  PRSET0;                            /*!< (@ 0x50004410) RCU Peripheral 0 Reset Set                             */\r
+  __O  uint32_t  PRCLR0;                            /*!< (@ 0x50004414) RCU Peripheral 0 Reset Clear                           */\r
+  __I  uint32_t  PRSTAT1;                           /*!< (@ 0x50004418) RCU Peripheral 1 Reset Status                          */\r
+  __O  uint32_t  PRSET1;                            /*!< (@ 0x5000441C) RCU Peripheral 1 Reset Set                             */\r
+  __O  uint32_t  PRCLR1;                            /*!< (@ 0x50004420) RCU Peripheral 1 Reset Clear                           */\r
+  __I  uint32_t  PRSTAT2;                           /*!< (@ 0x50004424) RCU Peripheral 2 Reset Status                          */\r
+  __O  uint32_t  PRSET2;                            /*!< (@ 0x50004428) RCU Peripheral 2 Reset Set                             */\r
+  __O  uint32_t  PRCLR2;                            /*!< (@ 0x5000442C) RCU Peripheral 2 Reset Clear                           */\r
+  __I  uint32_t  PRSTAT3;                           /*!< (@ 0x50004430) RCU Peripheral 3 Reset Status                          */\r
+  __O  uint32_t  PRSET3;                            /*!< (@ 0x50004434) RCU Peripheral 3 Reset Set                             */\r
+  __O  uint32_t  PRCLR3;                            /*!< (@ 0x50004438) RCU Peripheral 3 Reset Clear                           */\r
+} SCU_RESET_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                 LEDTS [LEDTS0]                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief LED and Touch Sense Unit 0 (LEDTS)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48010000) LEDTS Structure                                        */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x48010000) Module Identification Register                         */\r
+  __IO uint32_t  GLOBCTL;                           /*!< (@ 0x48010004) Global Control Register                                */\r
+  __IO uint32_t  FNCTL;                             /*!< (@ 0x48010008) Function Control Register                              */\r
+  __O  uint32_t  EVFR;                              /*!< (@ 0x4801000C) Event Flag Register                                    */\r
+  __IO uint32_t  TSVAL;                             /*!< (@ 0x48010010) Touch-sense TS-Counter Value                           */\r
+  __IO uint32_t  LINE0;                             /*!< (@ 0x48010014) Line Pattern Register 0                                */\r
+  __IO uint32_t  LINE1;                             /*!< (@ 0x48010018) Line Pattern Register 1                                */\r
+  __IO uint32_t  LDCMP0;                            /*!< (@ 0x4801001C) LED Compare Register 0                                 */\r
+  __IO uint32_t  LDCMP1;                            /*!< (@ 0x48010020) LED Compare Register 1                                 */\r
+  __IO uint32_t  TSCMP0;                            /*!< (@ 0x48010024) Touch-sense Compare Register 0                         */\r
+  __IO uint32_t  TSCMP1;                            /*!< (@ 0x48010028) Touch-sense Compare Register 1                         */\r
+} LEDTS0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      SDMMC                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief SD and Multimediacard Interface (SDMMC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x4801C000) SDMMC Structure                                        */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint16_t  BLOCK_SIZE;                        /*!< (@ 0x4801C004) Block Size Register                                    */\r
+  __IO uint16_t  BLOCK_COUNT;                       /*!< (@ 0x4801C006) Block Count Register                                   */\r
+  __IO uint32_t  ARGUMENT1;                         /*!< (@ 0x4801C008) Argument1 Register                                     */\r
+  __IO uint16_t  TRANSFER_MODE;                     /*!< (@ 0x4801C00C) Transfer Mode Register                                 */\r
+  __IO uint16_t  COMMAND;                           /*!< (@ 0x4801C00E) Command Register                                       */\r
+  __I  uint32_t  RESPONSE0;                         /*!< (@ 0x4801C010) Response 0 Register                                    */\r
+  __I  uint32_t  RESPONSE2;                         /*!< (@ 0x4801C014) Response 2 Register                                    */\r
+  __I  uint32_t  RESPONSE4;                         /*!< (@ 0x4801C018) Response 4 Register                                    */\r
+  __I  uint32_t  RESPONSE6;                         /*!< (@ 0x4801C01C) Response 6 Register                                    */\r
+  __IO uint32_t  DATA_BUFFER;                       /*!< (@ 0x4801C020) Data Buffer Register                                   */\r
+  __I  uint32_t  PRESENT_STATE;                     /*!< (@ 0x4801C024) Present State Register                                 */\r
+  __IO uint8_t   HOST_CTRL;                         /*!< (@ 0x4801C028) Host Control Register                                  */\r
+  __IO uint8_t   POWER_CTRL;                        /*!< (@ 0x4801C029) Power Control Register                                 */\r
+  __IO uint8_t   BLOCK_GAP_CTRL;                    /*!< (@ 0x4801C02A) Block Gap Control Register                             */\r
+  __IO uint8_t   WAKEUP_CTRL;                       /*!< (@ 0x4801C02B) Wake-up Control Register                               */\r
+  __IO uint16_t  CLOCK_CTRL;                        /*!< (@ 0x4801C02C) Clock Control Register                                 */\r
+  __IO uint8_t   TIMEOUT_CTRL;                      /*!< (@ 0x4801C02E) Timeout Control Register                               */\r
+  __IO uint8_t   SW_RESET;                          /*!< (@ 0x4801C02F) Software Reset Register                                */\r
+  __IO uint16_t  INT_STATUS_NORM;                   /*!< (@ 0x4801C030) Normal Interrupt Status Register                       */\r
+  __IO uint16_t  INT_STATUS_ERR;                    /*!< (@ 0x4801C032) Error Interrupt Status Register                        */\r
+  __IO uint16_t  EN_INT_STATUS_NORM;                /*!< (@ 0x4801C034) Normal Interrupt Status Enable Register                */\r
+  __IO uint16_t  EN_INT_STATUS_ERR;                 /*!< (@ 0x4801C036) Error Interrupt Status Enable Register                 */\r
+  __IO uint16_t  EN_INT_SIGNAL_NORM;                /*!< (@ 0x4801C038) Normal Interrupt Signal Enable Register                */\r
+  __IO uint16_t  EN_INT_SIGNAL_ERR;                 /*!< (@ 0x4801C03A) Error Interrupt Signal Enable Register                 */\r
+  __I  uint16_t  ACMD_ERR_STATUS;                   /*!< (@ 0x4801C03C) Auto CMD Error Status Register                         */\r
+  __I  uint16_t  RESERVED1[9];\r
+  __O  uint16_t  FORCE_EVENT_ACMD_ERR_STATUS;       /*!< (@ 0x4801C050) Force Event Register for Auto CMD Error Status         */\r
+  __O  uint16_t  FORCE_EVENT_ERR_STATUS;            /*!< (@ 0x4801C052) Force Event Register for Error Interrupt Status        */\r
+  __I  uint32_t  RESERVED2[8];\r
+  __O  uint32_t  DEBUG_SEL;                         /*!< (@ 0x4801C074) Debug Selection Register                               */\r
+  __I  uint32_t  RESERVED3[30];\r
+  __IO uint32_t  SPI;                               /*!< (@ 0x4801C0F0) SPI Interrupt Support Register                         */\r
+  __I  uint32_t  RESERVED4[2];\r
+  __I  uint16_t  SLOT_INT_STATUS;                   /*!< (@ 0x4801C0FC) Slot Interrupt Status Register                         */\r
+} SDMMC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       EBU                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief External Bus Unit (EBU)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x58008000) EBU Structure                                          */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x58008000) EBU Clock Control Register                             */\r
+  __IO uint32_t  MODCON;                            /*!< (@ 0x58008004) EBU Configuration Register                             */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x58008008) EBU Module Identification Register                     */\r
+  __IO uint32_t  USERCON;                           /*!< (@ 0x5800800C) EBU Test/Control Configuration Register                */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  ADDRSEL0;                          /*!< (@ 0x58008018) EBU Address Select Register 0                          */\r
+  __IO uint32_t  ADDRSEL1;                          /*!< (@ 0x5800801C) EBU Address Select Register 1                          */\r
+  __IO uint32_t  ADDRSEL2;                          /*!< (@ 0x58008020) EBU Address Select Register 2                          */\r
+  __IO uint32_t  ADDRSEL3;                          /*!< (@ 0x58008024) EBU Address Select Register 3                          */\r
+  __IO uint32_t  BUSRCON0;                          /*!< (@ 0x58008028) EBU Bus Configuration Register                         */\r
+  __IO uint32_t  BUSRAP0;                           /*!< (@ 0x5800802C) EBU Bus Read Access Parameter Register                 */\r
+  __IO uint32_t  BUSWCON0;                          /*!< (@ 0x58008030) EBU Bus Write Configuration Register                   */\r
+  __IO uint32_t  BUSWAP0;                           /*!< (@ 0x58008034) EBU Bus Write Access Parameter Register                */\r
+  __IO uint32_t  BUSRCON1;                          /*!< (@ 0x58008038) EBU Bus Configuration Register                         */\r
+  __IO uint32_t  BUSRAP1;                           /*!< (@ 0x5800803C) EBU Bus Read Access Parameter Register                 */\r
+  __IO uint32_t  BUSWCON1;                          /*!< (@ 0x58008040) EBU Bus Write Configuration Register                   */\r
+  __IO uint32_t  BUSWAP1;                           /*!< (@ 0x58008044) EBU Bus Write Access Parameter Register                */\r
+  __IO uint32_t  BUSRCON2;                          /*!< (@ 0x58008048) EBU Bus Configuration Register                         */\r
+  __IO uint32_t  BUSRAP2;                           /*!< (@ 0x5800804C) EBU Bus Read Access Parameter Register                 */\r
+  __IO uint32_t  BUSWCON2;                          /*!< (@ 0x58008050) EBU Bus Write Configuration Register                   */\r
+  __IO uint32_t  BUSWAP2;                           /*!< (@ 0x58008054) EBU Bus Write Access Parameter Register                */\r
+  __IO uint32_t  BUSRCON3;                          /*!< (@ 0x58008058) EBU Bus Configuration Register                         */\r
+  __IO uint32_t  BUSRAP3;                           /*!< (@ 0x5800805C) EBU Bus Read Access Parameter Register                 */\r
+  __IO uint32_t  BUSWCON3;                          /*!< (@ 0x58008060) EBU Bus Write Configuration Register                   */\r
+  __IO uint32_t  BUSWAP3;                           /*!< (@ 0x58008064) EBU Bus Write Access Parameter Register                */\r
+  __IO uint32_t  SDRMCON;                           /*!< (@ 0x58008068) EBU SDRAM Control Register                             */\r
+  __IO uint32_t  SDRMOD;                            /*!< (@ 0x5800806C) EBU SDRAM Mode Register                                */\r
+  __IO uint32_t  SDRMREF;                           /*!< (@ 0x58008070) EBU SDRAM Refresh Control Register                     */\r
+  __I  uint32_t  SDRSTAT;                           /*!< (@ 0x58008074) EBU SDRAM Status Register                              */\r
+} EBU_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    ETH0_CON                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Ethernet Control Register (ETH0_CON)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50004040) ETH0_CON Structure                                     */\r
+  __IO uint32_t  CON;                          /*!< (@ 0x50004040) Ethernet 0 Port Control Register                       */\r
+} ETH0_CON_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   ETH [ETH0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Ethernet Unit 0 (ETH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x5000C000) ETH Structure                                          */\r
+  __IO uint32_t  MAC_CONFIGURATION;                 /*!< (@ 0x5000C000) MAC Configuration Register                             */\r
+  __IO uint32_t  MAC_FRAME_FILTER;                  /*!< (@ 0x5000C004) MAC Frame Filter                                       */\r
+  __IO uint32_t  HASH_TABLE_HIGH;                   /*!< (@ 0x5000C008) Hash Table High Register                               */\r
+  __IO uint32_t  HASH_TABLE_LOW;                    /*!< (@ 0x5000C00C) Hash Table Low Register                                */\r
+  __IO uint32_t  GMII_ADDRESS;                      /*!< (@ 0x5000C010) MII Address Register                                   */\r
+  __IO uint32_t  GMII_DATA;                         /*!< (@ 0x5000C014) MII Data Register                                      */\r
+  __IO uint32_t  FLOW_CONTROL;                      /*!< (@ 0x5000C018) Flow Control Register                                  */\r
+  __IO uint32_t  VLAN_TAG;                          /*!< (@ 0x5000C01C) VLAN Tag Register                                      */\r
+  __I  uint32_t  VERSION;                           /*!< (@ 0x5000C020) Version Register                                       */\r
+  __I  uint32_t  DEBUG;                             /*!< (@ 0x5000C024) Debug Register                                         */\r
+  __IO uint32_t  REMOTE_WAKE_UP_FRAME_FILTER;       /*!< (@ 0x5000C028) Remote Wake Up Frame Filter Register                   */\r
+  __IO uint32_t  PMT_CONTROL_STATUS;                /*!< (@ 0x5000C02C) PMT Control and Status Register                        */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __I  uint32_t  INTERRUPT_STATUS;                  /*!< (@ 0x5000C038) Interrupt Register                                     */\r
+  __IO uint32_t  INTERRUPT_MASK;                    /*!< (@ 0x5000C03C) Interrupt Mask Register                                */\r
+  __IO uint32_t  MAC_ADDRESS0_HIGH;                 /*!< (@ 0x5000C040) MAC Address0 High Register                             */\r
+  __IO uint32_t  MAC_ADDRESS0_LOW;                  /*!< (@ 0x5000C044) MAC Address0 Low Register                              */\r
+  __IO uint32_t  MAC_ADDRESS1_HIGH;                 /*!< (@ 0x5000C048) MAC Address1 High Register                             */\r
+  __IO uint32_t  MAC_ADDRESS1_LOW;                  /*!< (@ 0x5000C04C) MAC Address1 Low Register                              */\r
+  __IO uint32_t  MAC_ADDRESS2_HIGH;                 /*!< (@ 0x5000C050) MAC Address2 High Register                             */\r
+  __IO uint32_t  MAC_ADDRESS2_LOW;                  /*!< (@ 0x5000C054) MAC Address2 Low Register                              */\r
+  __IO uint32_t  MAC_ADDRESS3_HIGH;                 /*!< (@ 0x5000C058) MAC Address3 High Register                             */\r
+  __IO uint32_t  MAC_ADDRESS3_LOW;                  /*!< (@ 0x5000C05C) MAC Address3 Low Register                              */\r
+  __I  uint32_t  RESERVED1[40];\r
+  __IO uint32_t  MMC_CONTROL;                       /*!< (@ 0x5000C100) MMC Control Register                                   */\r
+  __I  uint32_t  MMC_RECEIVE_INTERRUPT;             /*!< (@ 0x5000C104) MMC Receive Interrupt Register                         */\r
+  __I  uint32_t  MMC_TRANSMIT_INTERRUPT;            /*!< (@ 0x5000C108) MMC Transmit Interrupt Register                        */\r
+  __IO uint32_t  MMC_RECEIVE_INTERRUPT_MASK;        /*!< (@ 0x5000C10C) MMC Reveive Interrupt Mask Register                    */\r
+  __IO uint32_t  MMC_TRANSMIT_INTERRUPT_MASK;       /*!< (@ 0x5000C110) MMC Transmit Interrupt Mask Register                   */\r
+  __I  uint32_t  TX_OCTET_COUNT_GOOD_BAD;           /*!< (@ 0x5000C114) Transmit Octet Count for Good and Bad Frames\r
+                                                         Register                                                              */\r
+  __I  uint32_t  TX_FRAME_COUNT_GOOD_BAD;           /*!< (@ 0x5000C118) Transmit Frame Count for Goodand Bad Frames Register   */\r
+  __I  uint32_t  TX_BROADCAST_FRAMES_GOOD;          /*!< (@ 0x5000C11C) Transmit Frame Count for Good Broadcast Frames         */\r
+  __I  uint32_t  TX_MULTICAST_FRAMES_GOOD;          /*!< (@ 0x5000C120) Transmit Frame Count for Good Multicast Frames         */\r
+  __I  uint32_t  TX_64OCTETS_FRAMES_GOOD_BAD;       /*!< (@ 0x5000C124) Transmit Octet Count for Good and Bad 64 Byte\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_65TO127OCTETS_FRAMES_GOOD_BAD;  /*!< (@ 0x5000C128) Transmit Octet Count for Good and Bad 65 to 127\r
+                                                         Bytes Frames                                                          */\r
+  __I  uint32_t  TX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C12C) Transmit Octet Count for Good and Bad 128 to\r
+                                                         255 Bytes Frames                                                      */\r
+  __I  uint32_t  TX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C130) Transmit Octet Count for Good and Bad 256 to\r
+                                                         511 Bytes Frames                                                      */\r
+  __I  uint32_t  TX_512TO1023OCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C134) Transmit Octet Count for Good and Bad 512 to\r
+                                                         1023 Bytes Frames                                                     */\r
+  __I  uint32_t  TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C138) Transmit Octet Count for Good and Bad 1024 to\r
+                                                         Maxsize Bytes Frames                                                  */\r
+  __I  uint32_t  TX_UNICAST_FRAMES_GOOD_BAD;        /*!< (@ 0x5000C13C) Transmit Frame Count for Good and Bad Unicast\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_MULTICAST_FRAMES_GOOD_BAD;      /*!< (@ 0x5000C140) Transmit Frame Count for Good and Bad Multicast\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_BROADCAST_FRAMES_GOOD_BAD;      /*!< (@ 0x5000C144) Transmit Frame Count for Good and Bad Broadcast\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_UNDERFLOW_ERROR_FRAMES;         /*!< (@ 0x5000C148) Transmit Frame Count for Underflow Error Frames        */\r
+  __I  uint32_t  TX_SINGLE_COLLISION_GOOD_FRAMES;   /*!< (@ 0x5000C14C) Transmit Frame Count for Frames Transmitted after\r
+                                                         Single Collision                                                      */\r
+  __I  uint32_t  TX_MULTIPLE_COLLISION_GOOD_FRAMES; /*!< (@ 0x5000C150) Transmit Frame Count for Frames Transmitted after\r
+                                                         Multiple Collision                                                    */\r
+  __I  uint32_t  TX_DEFERRED_FRAMES;                /*!< (@ 0x5000C154) Tx Deferred Frames Register                            */\r
+  __I  uint32_t  TX_LATE_COLLISION_FRAMES;          /*!< (@ 0x5000C158) Transmit Frame Count for Late Collision Error\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_EXCESSIVE_COLLISION_FRAMES;     /*!< (@ 0x5000C15C) Transmit Frame Count for Excessive Collision\r
+                                                         Error Frames                                                          */\r
+  __I  uint32_t  TX_CARRIER_ERROR_FRAMES;           /*!< (@ 0x5000C160) Transmit Frame Count for Carrier Sense Error\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_OCTET_COUNT_GOOD;               /*!< (@ 0x5000C164) Tx Octet Count Good Register                           */\r
+  __I  uint32_t  TX_FRAME_COUNT_GOOD;               /*!< (@ 0x5000C168) Tx Frame Count Good Register                           */\r
+  __I  uint32_t  TX_EXCESSIVE_DEFERRAL_ERROR;       /*!< (@ 0x5000C16C) Transmit Frame Count for Excessive Deferral Error\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  TX_PAUSE_FRAMES;                   /*!< (@ 0x5000C170) Transmit Frame Count for Good PAUSE Frames             */\r
+  __I  uint32_t  TX_VLAN_FRAMES_GOOD;               /*!< (@ 0x5000C174) Transmit Frame Count for Good VLAN Frames              */\r
+  __I  uint32_t  TX_OSIZE_FRAMES_GOOD;              /*!< (@ 0x5000C178) Transmit Frame Count for Good Oversize Frames          */\r
+  __I  uint32_t  RESERVED2;\r
+  __I  uint32_t  RX_FRAMES_COUNT_GOOD_BAD;          /*!< (@ 0x5000C180) Receive Frame Count for Good and Bad Frames            */\r
+  __I  uint32_t  RX_OCTET_COUNT_GOOD_BAD;           /*!< (@ 0x5000C184) Receive Octet Count for Good and Bad Frames            */\r
+  __I  uint32_t  RX_OCTET_COUNT_GOOD;               /*!< (@ 0x5000C188) Rx Octet Count Good Register                           */\r
+  __I  uint32_t  RX_BROADCAST_FRAMES_GOOD;          /*!< (@ 0x5000C18C) Receive Frame Count for Good Broadcast Frames          */\r
+  __I  uint32_t  RX_MULTICAST_FRAMES_GOOD;          /*!< (@ 0x5000C190) Receive Frame Count for Good Multicast Frames          */\r
+  __I  uint32_t  RX_CRC_ERROR_FRAMES;               /*!< (@ 0x5000C194) Receive Frame Count for CRC Error Frames               */\r
+  __I  uint32_t  RX_ALIGNMENT_ERROR_FRAMES;         /*!< (@ 0x5000C198) Receive Frame Count for Alignment Error Frames         */\r
+  __I  uint32_t  RX_RUNT_ERROR_FRAMES;              /*!< (@ 0x5000C19C) Receive Frame Count for Runt Error Frames              */\r
+  __I  uint32_t  RX_JABBER_ERROR_FRAMES;            /*!< (@ 0x5000C1A0) Receive Frame Count for Jabber Error Frames            */\r
+  __I  uint32_t  RX_UNDERSIZE_FRAMES_GOOD;          /*!< (@ 0x5000C1A4) Receive Frame Count for Undersize Frames               */\r
+  __I  uint32_t  RX_OVERSIZE_FRAMES_GOOD;           /*!< (@ 0x5000C1A8) Rx Oversize Frames Good Register                       */\r
+  __I  uint32_t  RX_64OCTETS_FRAMES_GOOD_BAD;       /*!< (@ 0x5000C1AC) Receive Frame Count for Good and Bad 64 Byte\r
+                                                         Frames                                                                */\r
+  __I  uint32_t  RX_65TO127OCTETS_FRAMES_GOOD_BAD;  /*!< (@ 0x5000C1B0) Receive Frame Count for Good and Bad 65 to 127\r
+                                                         Bytes Frames                                                          */\r
+  __I  uint32_t  RX_128TO255OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B4) Receive Frame Count for Good and Bad 128 to 255\r
+                                                         Bytes Frames                                                          */\r
+  __I  uint32_t  RX_256TO511OCTETS_FRAMES_GOOD_BAD; /*!< (@ 0x5000C1B8) Receive Frame Count for Good and Bad 256 to 511\r
+                                                         Bytes Frames                                                          */\r
+  __I  uint32_t  RX_512TO1023OCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C1BC) Receive Frame Count for Good and Bad 512 to 1,023\r
+                                                         Bytes Frames                                                          */\r
+  __I  uint32_t  RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;/*!< (@ 0x5000C1C0) Receive Frame Count for Good and Bad 1,024 to\r
+                                                         Maxsize Bytes Frames                                                  */\r
+  __I  uint32_t  RX_UNICAST_FRAMES_GOOD;            /*!< (@ 0x5000C1C4) Receive Frame Count for Good Unicast Frames            */\r
+  __I  uint32_t  RX_LENGTH_ERROR_FRAMES;            /*!< (@ 0x5000C1C8) Receive Frame Count for Length Error Frames            */\r
+  __I  uint32_t  RX_OUT_OF_RANGE_TYPE_FRAMES;       /*!< (@ 0x5000C1CC) Receive Frame Count for Out of Range Frames            */\r
+  __I  uint32_t  RX_PAUSE_FRAMES;                   /*!< (@ 0x5000C1D0) Receive Frame Count for PAUSE Frames                   */\r
+  __I  uint32_t  RX_FIFO_OVERFLOW_FRAMES;           /*!< (@ 0x5000C1D4) Receive Frame Count for FIFO Overflow Frames           */\r
+  __I  uint32_t  RX_VLAN_FRAMES_GOOD_BAD;           /*!< (@ 0x5000C1D8) Receive Frame Count for Good and Bad VLAN Frames       */\r
+  __I  uint32_t  RX_WATCHDOG_ERROR_FRAMES;          /*!< (@ 0x5000C1DC) Receive Frame Count for Watchdog Error Frames          */\r
+  __I  uint32_t  RX_RECEIVE_ERROR_FRAMES;           /*!< (@ 0x5000C1E0) Receive Frame Count for Receive Error Frames           */\r
+  __I  uint32_t  RX_CONTROL_FRAMES_GOOD;            /*!< (@ 0x5000C1E4) Receive Frame Count for Good Control Frames Frames     */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __IO uint32_t  MMC_IPC_RECEIVE_INTERRUPT_MASK;    /*!< (@ 0x5000C200) MMC Receive Checksum Offload Interrupt Mask Register   */\r
+  __I  uint32_t  RESERVED4;\r
+  __I  uint32_t  MMC_IPC_RECEIVE_INTERRUPT;         /*!< (@ 0x5000C208) MMC Receive Checksum Offload Interrupt Register        */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  RXIPV4_GOOD_FRAMES;                /*!< (@ 0x5000C210) RxIPv4 Good Frames Register                            */\r
+  __I  uint32_t  RXIPV4_HEADER_ERROR_FRAMES;        /*!< (@ 0x5000C214) Receive IPV4 Header Error Frame Counter Register       */\r
+  __I  uint32_t  RXIPV4_NO_PAYLOAD_FRAMES;          /*!< (@ 0x5000C218) Receive IPV4 No Payload Frame Counter Register         */\r
+  __I  uint32_t  RXIPV4_FRAGMENTED_FRAMES;          /*!< (@ 0x5000C21C) Receive IPV4 Fragmented Frame Counter Register         */\r
+  __I  uint32_t  RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES;/*!< (@ 0x5000C220) Receive IPV4 UDP Checksum Disabled Frame Counter\r
+                                                         Register                                                              */\r
+  __I  uint32_t  RXIPV6_GOOD_FRAMES;                /*!< (@ 0x5000C224) RxIPv6 Good Frames Register                            */\r
+  __I  uint32_t  RXIPV6_HEADER_ERROR_FRAMES;        /*!< (@ 0x5000C228) Receive IPV6 Header Error Frame Counter Register       */\r
+  __I  uint32_t  RXIPV6_NO_PAYLOAD_FRAMES;          /*!< (@ 0x5000C22C) Receive IPV6 No Payload Frame Counter Register         */\r
+  __I  uint32_t  RXUDP_GOOD_FRAMES;                 /*!< (@ 0x5000C230) RxUDP Good Frames Register                             */\r
+  __I  uint32_t  RXUDP_ERROR_FRAMES;                /*!< (@ 0x5000C234) RxUDP Error Frames Register                            */\r
+  __I  uint32_t  RXTCP_GOOD_FRAMES;                 /*!< (@ 0x5000C238) RxTCP Good Frames Register                             */\r
+  __I  uint32_t  RXTCP_ERROR_FRAMES;                /*!< (@ 0x5000C23C) RxTCP Error Frames Register                            */\r
+  __I  uint32_t  RXICMP_GOOD_FRAMES;                /*!< (@ 0x5000C240) RxICMP Good Frames Register                            */\r
+  __I  uint32_t  RXICMP_ERROR_FRAMES;               /*!< (@ 0x5000C244) RxICMP Error Frames Register                           */\r
+  __I  uint32_t  RESERVED6[2];\r
+  __I  uint32_t  RXIPV4_GOOD_OCTETS;                /*!< (@ 0x5000C250) RxIPv4 Good Octets Register                            */\r
+  __I  uint32_t  RXIPV4_HEADER_ERROR_OCTETS;        /*!< (@ 0x5000C254) Receive IPV4 Header Error Octet Counter Register       */\r
+  __I  uint32_t  RXIPV4_NO_PAYLOAD_OCTETS;          /*!< (@ 0x5000C258) Receive IPV4 No Payload Octet Counter Register         */\r
+  __I  uint32_t  RXIPV4_FRAGMENTED_OCTETS;          /*!< (@ 0x5000C25C) Receive IPV4 Fragmented Octet Counter Register         */\r
+  __I  uint32_t  RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS;/*!< (@ 0x5000C260) Receive IPV4 Fragmented Octet Counter Register         */\r
+  __I  uint32_t  RXIPV6_GOOD_OCTETS;                /*!< (@ 0x5000C264) RxIPv6 Good Octets Register                            */\r
+  __I  uint32_t  RXIPV6_HEADER_ERROR_OCTETS;        /*!< (@ 0x5000C268) Receive IPV6 Header Error Octet Counter Register       */\r
+  __I  uint32_t  RXIPV6_NO_PAYLOAD_OCTETS;          /*!< (@ 0x5000C26C) Receive IPV6 No Payload Octet Counter Register         */\r
+  __I  uint32_t  RXUDP_GOOD_OCTETS;                 /*!< (@ 0x5000C270) Receive UDP Good Octets Register                       */\r
+  __I  uint32_t  RXUDP_ERROR_OCTETS;                /*!< (@ 0x5000C274) Receive UDP Error Octets Register                      */\r
+  __I  uint32_t  RXTCP_GOOD_OCTETS;                 /*!< (@ 0x5000C278) Receive TCP Good Octets Register                       */\r
+  __I  uint32_t  RXTCP_ERROR_OCTETS;                /*!< (@ 0x5000C27C) Receive TCP Error Octets Register                      */\r
+  __I  uint32_t  RXICMP_GOOD_OCTETS;                /*!< (@ 0x5000C280) Receive ICMP Good Octets Register                      */\r
+  __I  uint32_t  RXICMP_ERROR_OCTETS;               /*!< (@ 0x5000C284) Receive ICMP Error Octets Register                     */\r
+  __I  uint32_t  RESERVED7[286];\r
+  __IO uint32_t  TIMESTAMP_CONTROL;                 /*!< (@ 0x5000C700) Timestamp Control Register                             */\r
+  __IO uint32_t  SUB_SECOND_INCREMENT;              /*!< (@ 0x5000C704) Sub-Second Increment Register                          */\r
+  __I  uint32_t  SYSTEM_TIME_SECONDS;               /*!< (@ 0x5000C708) System Time - Seconds Register                         */\r
+  __I  uint32_t  SYSTEM_TIME_NANOSECONDS;           /*!< (@ 0x5000C70C) System Time Nanoseconds Register                       */\r
+  __IO uint32_t  SYSTEM_TIME_SECONDS_UPDATE;        /*!< (@ 0x5000C710) System Time - Seconds Update Register                  */\r
+  __IO uint32_t  SYSTEM_TIME_NANOSECONDS_UPDATE;    /*!< (@ 0x5000C714) System Time Nanoseconds Update Register                */\r
+  __IO uint32_t  TIMESTAMP_ADDEND;                  /*!< (@ 0x5000C718) Timestamp Addend Register                              */\r
+  __IO uint32_t  TARGET_TIME_SECONDS;               /*!< (@ 0x5000C71C) Target Time Seconds Register                           */\r
+  __IO uint32_t  TARGET_TIME_NANOSECONDS;           /*!< (@ 0x5000C720) Target Time Nanoseconds Register                       */\r
+  __IO uint32_t  SYSTEM_TIME_HIGHER_WORD_SECONDS;   /*!< (@ 0x5000C724) System Time - Higher Word Seconds Register             */\r
+  __I  uint32_t  TIMESTAMP_STATUS;                  /*!< (@ 0x5000C728) Timestamp Status Register                              */\r
+  __IO uint32_t  PPS_CONTROL;                       /*!< (@ 0x5000C72C) PPS Control Register                                   */\r
+  __I  uint32_t  RESERVED8[564];\r
+  __IO uint32_t  BUS_MODE;                          /*!< (@ 0x5000D000) Bus Mode Register                                      */\r
+  __IO uint32_t  TRANSMIT_POLL_DEMAND;              /*!< (@ 0x5000D004) Transmit Poll Demand Register                          */\r
+  __IO uint32_t  RECEIVE_POLL_DEMAND;               /*!< (@ 0x5000D008) Receive Poll Demand Register                           */\r
+  __IO uint32_t  RECEIVE_DESCRIPTOR_LIST_ADDRESS;   /*!< (@ 0x5000D00C) Receive Descriptor Address Register                    */\r
+  __IO uint32_t  TRANSMIT_DESCRIPTOR_LIST_ADDRESS;  /*!< (@ 0x5000D010) Transmit descripter Address Register                   */\r
+  __IO uint32_t  STATUS;                            /*!< (@ 0x5000D014) Status Register                                        */\r
+  __IO uint32_t  OPERATION_MODE;                    /*!< (@ 0x5000D018) Operation Mode Register                                */\r
+  __IO uint32_t  INTERRUPT_ENABLE;                  /*!< (@ 0x5000D01C) Interrupt Enable Register                              */\r
+  __I  uint32_t  MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER;/*!< (@ 0x5000D020) Missed Frame and Buffer Overflow Counter Register */\r
+  __IO uint32_t  RECEIVE_INTERRUPT_WATCHDOG_TIMER;  /*!< (@ 0x5000D024) Receive Interrupt Watchdog Timer Register              */\r
+  __I  uint32_t  RESERVED9;\r
+  __I  uint32_t  AHB_STATUS;                        /*!< (@ 0x5000D02C) AHB Status Register                                    */\r
+  __I  uint32_t  RESERVED10[6];\r
+  __I  uint32_t  CURRENT_HOST_TRANSMIT_DESCRIPTOR;  /*!< (@ 0x5000D048) Current Host Transmit Descriptor Register              */\r
+  __I  uint32_t  CURRENT_HOST_RECEIVE_DESCRIPTOR;   /*!< (@ 0x5000D04C) Current Host Receive Descriptor Register               */\r
+  __I  uint32_t  CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS;/*!< (@ 0x5000D050) Current Host Transmit Buffer Address Register        */\r
+  __I  uint32_t  CURRENT_HOST_RECEIVE_BUFFER_ADDRESS;/*!< (@ 0x5000D054) Current Host Receive Buffer Address Register          */\r
+  __IO uint32_t  HW_FEATURE;                        /*!< (@ 0x5000D058) HW Feature Register                                    */\r
+} ETH_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                   USB [USB0]                   ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Bus (USB)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50040000) USB Structure                                          */\r
+  __IO uint32_t  GOTGCTL;                           /*!< (@ 0x50040000) Control and Status Register                            */\r
+  __IO uint32_t  GOTGINT;                           /*!< (@ 0x50040004) OTG Interrupt Register                                 */\r
+  __IO uint32_t  GAHBCFG;                           /*!< (@ 0x50040008) AHB Configuration Register                             */\r
+  __IO uint32_t  GUSBCFG;                           /*!< (@ 0x5004000C) USB Configuration Register                             */\r
+  __IO uint32_t  GRSTCTL;                           /*!< (@ 0x50040010) Reset Register                                         */\r
+  \r
+  union {\r
+    __IO uint32_t  GINTSTS_DEVICEMODE;              /*!< (@ 0x50040014) Interrupt Register [DEVICEMODE]                        */\r
+    __IO uint32_t  GINTSTS_HOSTMODE;                /*!< (@ 0x50040014) Interrupt Register [HOSTMODE]                          */\r
+  };\r
+  \r
+  union {\r
+    __IO uint32_t  GINTMSK_DEVICEMODE;              /*!< (@ 0x50040018) Interrupt Mask Register [DEVICEMODE]                   */\r
+    __IO uint32_t  GINTMSK_HOSTMODE;                /*!< (@ 0x50040018) Interrupt Mask Register [HOSTMODE]                     */\r
+  };\r
+  \r
+  union {\r
+    __I  uint32_t  GRXSTSR_DEVICEMODE;              /*!< (@ 0x5004001C) Receive Status Debug Read Register [DEVICEMODE]        */\r
+    __I  uint32_t  GRXSTSR_HOSTMODE;                /*!< (@ 0x5004001C) Receive Status Debug Read Register [HOSTMODE]          */\r
+  };\r
+  \r
+  union {\r
+    __I  uint32_t  GRXSTSP_DEVICEMODE;              /*!< (@ 0x50040020) Receive Status Read and Pop Register [DEVICEMODE]      */\r
+    __I  uint32_t  GRXSTSP_HOSTMODE;                /*!< (@ 0x50040020) Receive Status Read and Pop Register [HOSTMODE]        */\r
+  };\r
+  __IO uint32_t  GRXFSIZ;                           /*!< (@ 0x50040024) Receive FIFO Size Register                             */\r
+  \r
+  union {\r
+    __IO uint32_t  GNPTXFSIZ_DEVICEMODE;            /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register [DEVICEMODE]  */\r
+    __IO uint32_t  GNPTXFSIZ_HOSTMODE;              /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register [HOSTMODE]    */\r
+  };\r
+  __I  uint32_t  GNPTXSTS;                          /*!< (@ 0x5004002C) Non-Periodic Transmit FIFO/Queue Status Register       */\r
+  __I  uint32_t  RESERVED0[3];\r
+  __IO uint32_t  GUID;                              /*!< (@ 0x5004003C) USB Module Identification Register                     */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __IO uint32_t  GDFIFOCFG;                         /*!< (@ 0x5004005C) Global DFIFO Software Config Register                  */\r
+  __I  uint32_t  RESERVED2[40];\r
+  __IO uint32_t  HPTXFSIZ;                          /*!< (@ 0x50040100) Host Periodic Transmit FIFO Size Register              */\r
+  __IO uint32_t  DIEPTXF1;                          /*!< (@ 0x50040104) Device IN Endpoint 1 Transmit FIFO Size Register       */\r
+  __IO uint32_t  DIEPTXF2;                          /*!< (@ 0x50040108) Device IN Endpoint 2 Transmit FIFO Size Register       */\r
+  __IO uint32_t  DIEPTXF3;                          /*!< (@ 0x5004010C) Device IN Endpoint 3 Transmit FIFO Size Register       */\r
+  __IO uint32_t  DIEPTXF4;                          /*!< (@ 0x50040110) Device IN Endpoint 4 Transmit FIFO Size Register       */\r
+  __IO uint32_t  DIEPTXF5;                          /*!< (@ 0x50040114) Device IN Endpoint 5 Transmit FIFO Size Register       */\r
+  __IO uint32_t  DIEPTXF6;                          /*!< (@ 0x50040118) Device IN Endpoint 6 Transmit FIFO Size Register       */\r
+  __I  uint32_t  RESERVED3[185];\r
+  __IO uint32_t  HCFG;                              /*!< (@ 0x50040400) Host Configuration Register                            */\r
+  __IO uint32_t  HFIR;                              /*!< (@ 0x50040404) Host Frame Interval Register                           */\r
+  __IO uint32_t  HFNUM;                             /*!< (@ 0x50040408) Host Frame Number/Frame Time Remaining Register        */\r
+  __I  uint32_t  RESERVED4;\r
+  __IO uint32_t  HPTXSTS;                           /*!< (@ 0x50040410) Host Periodic Transmit FIFO/ Queue Status Register     */\r
+  __I  uint32_t  HAINT;                             /*!< (@ 0x50040414) Host All Channels Interrupt Register                   */\r
+  __IO uint32_t  HAINTMSK;                          /*!< (@ 0x50040418) Host All Channels Interrupt Mask Register              */\r
+  __IO uint32_t  HFLBADDR;                          /*!< (@ 0x5004041C) Host Frame List Base Address Register                  */\r
+  __I  uint32_t  RESERVED5[8];\r
+  __IO uint32_t  HPRT;                              /*!< (@ 0x50040440) Host Port Control and Status Register                  */\r
+  __I  uint32_t  RESERVED6[239];\r
+  __IO uint32_t  DCFG;                              /*!< (@ 0x50040800) Device Configuration Register                          */\r
+  __IO uint32_t  DCTL;                              /*!< (@ 0x50040804) Device Control Register                                */\r
+  __I  uint32_t  DSTS;                              /*!< (@ 0x50040808) Device Status Register                                 */\r
+  __I  uint32_t  RESERVED7;\r
+  __IO uint32_t  DIEPMSK;                           /*!< (@ 0x50040810) Device IN Endpoint Common Interrupt Mask Register      */\r
+  __IO uint32_t  DOEPMSK;                           /*!< (@ 0x50040814) Device OUT Endpoint Common Interrupt Mask Register     */\r
+  __I  uint32_t  DAINT;                             /*!< (@ 0x50040818) Device All Endpoints Interrupt Register                */\r
+  __IO uint32_t  DAINTMSK;                          /*!< (@ 0x5004081C) Device All Endpoints Interrupt Mask Register           */\r
+  __I  uint32_t  RESERVED8[2];\r
+  __IO uint32_t  DVBUSDIS;                          /*!< (@ 0x50040828) Device VBUS Discharge Time Register                    */\r
+  __IO uint32_t  DVBUSPULSE;                        /*!< (@ 0x5004082C) Device VBUS Pulsing Time Register                      */\r
+  __I  uint32_t  RESERVED9;\r
+  __IO uint32_t  DIEPEMPMSK;                        /*!< (@ 0x50040834) Device IN Endpoint FIFO Empty Interrupt Mask\r
+                                                         Register                                                              */\r
+  __I  uint32_t  RESERVED10[370];\r
+  __IO uint32_t  PCGCCTL;                           /*!< (@ 0x50040E00) Power and Clock Gating Control Register                */\r
+} USB0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                    USB0_EP0                    ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Bus (USB0_EP0)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50040900) USB0_EP0 Structure                                     */\r
+  __IO uint32_t  DIEPCTL0;                          /*!< (@ 0x50040900) Device Control IN Endpoint 0 Control Register          */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DIEPINT0;                          /*!< (@ 0x50040908) Device Endpoint-0 Interrupt Register                   */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  DIEPTSIZ0;                         /*!< (@ 0x50040910) Device IN Endpoint 0 Transfer Size Register            */\r
+  __IO uint32_t  DIEPDMA0;                          /*!< (@ 0x50040914) Device Endpoint-0 DMA Address Register                 */\r
+  __I  uint32_t  DTXFSTS0;                          /*!< (@ 0x50040918) Device IN Endpoint Transmit FIFO Status Register       */\r
+  __I  uint32_t  DIEPDMAB0;                         /*!< (@ 0x5004091C) Device Endpoint-0 DMA Buffer Address Register          */\r
+  __I  uint32_t  RESERVED2[120];\r
+  __IO uint32_t  DOEPCTL0;                          /*!< (@ 0x50040B00) Device Control OUT Endpoint 0 Control Register         */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  DOEPINT0;                          /*!< (@ 0x50040B08) Device Endpoint-0 Interrupt Register                   */\r
+  __I  uint32_t  RESERVED4;\r
+  __IO uint32_t  DOEPTSIZ0;                         /*!< (@ 0x50040B10) Device OUT Endpoint 0 Transfer Size Register           */\r
+  __IO uint32_t  DOEPDMA0;                          /*!< (@ 0x50040B14) Device Endpoint-0 DMA Address Register                 */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  DOEPDMAB0;                         /*!< (@ 0x50040B1C) Device Endpoint-0 DMA Buffer Address Register          */\r
+} USB0_EP0_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                USB_EP [USB0_EP1]               ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Bus (USB_EP)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50040920) USB_EP Structure                                       */\r
+  \r
+  union {\r
+    __IO uint32_t  DIEPCTL_INTBULK;                 /*!< (@ 0x50040920) Device Endpoint Control Register [INTBULK]             */\r
+    __IO uint32_t  DIEPCTL_ISOCONT;                 /*!< (@ 0x50040920) Device Endpoint Control Register [ISOCONT]             */\r
+  };\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DIEPINT;                           /*!< (@ 0x50040928) Device Endpoint Interrupt Register                     */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  DIEPTSIZ;                          /*!< (@ 0x50040930) Device Endpoint Transfer Size Register                 */\r
+  __IO uint32_t  DIEPDMA;                           /*!< (@ 0x50040934) Device Endpoint DMA Address Register                   */\r
+  __I  uint32_t  DTXFSTS;                           /*!< (@ 0x50040938) Device IN Endpoint Transmit FIFO Status Register       */\r
+  __I  uint32_t  DIEPDMAB;                          /*!< (@ 0x5004093C) Device Endpoint DMA Buffer Address Register            */\r
+  __I  uint32_t  RESERVED2[120];\r
+  \r
+  union {\r
+    __IO uint32_t  DOEPCTL_INTBULK;                 /*!< (@ 0x50040B20) Device Endpoint Control Register [INTBULK]             */\r
+    __IO uint32_t  DOEPCTL_ISOCONT;                 /*!< (@ 0x50040B20) Device Endpoint Control Register [ISOCONT]             */\r
+  };\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  DOEPINT;                           /*!< (@ 0x50040B28) Device Endpoint Interrupt Register                     */\r
+  __I  uint32_t  RESERVED4;\r
+  \r
+  union {\r
+    __IO uint32_t  DOEPTSIZ_CONTROL;                /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [CONT]          */\r
+    __IO uint32_t  DOEPTSIZ_ISO;                    /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [ISO]           */\r
+  };\r
+  __IO uint32_t  DOEPDMA;                           /*!< (@ 0x50040B34) Device Endpoint DMA Address Register                   */\r
+  __I  uint32_t  RESERVED5;\r
+  __I  uint32_t  DOEPDMAB;                          /*!< (@ 0x50040B3C) Device Endpoint DMA Buffer Address Register            */\r
+} USB0_EP_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                USB_CH [USB0_CH0]               ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Bus (USB_CH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x50040500) USB_CH Structure                                       */\r
+  __IO uint32_t  HCCHAR;                            /*!< (@ 0x50040500) Host Channel Characteristics Register                  */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  HCINT;                             /*!< (@ 0x50040508) Host Channel Interrupt Register                        */\r
+  __IO uint32_t  HCINTMSK;                          /*!< (@ 0x5004050C) Host Channel Interrupt Mask Register                   */\r
+  \r
+  union {\r
+    __IO uint32_t  HCTSIZ_SCATGATHER;               /*!< (@ 0x50040510) Host Channel Transfer Size Register [SCATGATHER]       */\r
+    __IO uint32_t  HCTSIZ_BUFFERMODE;               /*!< (@ 0x50040510) Host Channel Transfer Size Register [BUFFERMODE]       */\r
+  };\r
+  \r
+  union {\r
+    __IO uint32_t  HCDMA_SCATGATHER;                /*!< (@ 0x50040514) Host Channel DMA Address Register [SCATGATHER]         */\r
+    __IO uint32_t  HCDMA_BUFFERMODE;                /*!< (@ 0x50040514) Host Channel DMA Address Register [BUFFERMODE]         */\r
+  };\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  HCDMAB;                            /*!< (@ 0x5004051C) Host Channel DMA Buffer Address Register               */\r
+} USB0_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  USIC [USIC0]                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Interface Controller 0 (USIC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40030008) USIC Structure                                         */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x40030008) Module Identification Register                         */\r
+} USIC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================               USIC_CH [USIC0_CH0]              ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Universal Serial Interface Controller 0 (USIC_CH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40030000) USIC_CH Structure                                      */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  CCFG;                              /*!< (@ 0x40030004) Channel Configuration Register                         */\r
+  __I  uint32_t  RESERVED1;\r
+  __IO uint32_t  KSCFG;                             /*!< (@ 0x4003000C) Kernel State Configuration Register                    */\r
+  __IO uint32_t  FDR;                               /*!< (@ 0x40030010) Fractional Divider Register                            */\r
+  __IO uint32_t  BRG;                               /*!< (@ 0x40030014) Baud Rate Generator Register                           */\r
+  __IO uint32_t  INPR;                              /*!< (@ 0x40030018) Interrupt Node Pointer Register                        */\r
+  __IO uint32_t  DX0CR;                             /*!< (@ 0x4003001C) Input Control Register 0                               */\r
+  __IO uint32_t  DX1CR;                             /*!< (@ 0x40030020) Input Control Register 1                               */\r
+  __IO uint32_t  DX2CR;                             /*!< (@ 0x40030024) Input Control Register 2                               */\r
+  __IO uint32_t  DX3CR;                             /*!< (@ 0x40030028) Input Control Register 3                               */\r
+  __IO uint32_t  DX4CR;                             /*!< (@ 0x4003002C) Input Control Register 4                               */\r
+  __IO uint32_t  DX5CR;                             /*!< (@ 0x40030030) Input Control Register 5                               */\r
+  __IO uint32_t  SCTR;                              /*!< (@ 0x40030034) Shift Control Register                                 */\r
+  __IO uint32_t  TCSR;                              /*!< (@ 0x40030038) Transmit Control/Status Register                       */\r
+  \r
+  union {\r
+    __IO uint32_t  PCR_IICMode;                     /*!< (@ 0x4003003C) Protocol Control Register [IIC Mode]                   */\r
+    __IO uint32_t  PCR_IISMode;                     /*!< (@ 0x4003003C) Protocol Control Register [IIS Mode]                   */\r
+    __IO uint32_t  PCR_SSCMode;                     /*!< (@ 0x4003003C) Protocol Control Register [SSC Mode]                   */\r
+    __IO uint32_t  PCR;                             /*!< (@ 0x4003003C) Protocol Control Register                              */\r
+    __IO uint32_t  PCR_ASCMode;                     /*!< (@ 0x4003003C) Protocol Control Register [ASC Mode]                   */\r
+  };\r
+  __IO uint32_t  CCR;                               /*!< (@ 0x40030040) Channel Control Register                               */\r
+  __IO uint32_t  CMTR;                              /*!< (@ 0x40030044) Capture Mode Timer Register                            */\r
+  \r
+  union {\r
+    __IO uint32_t  PSR_IICMode;                     /*!< (@ 0x40030048) Protocol Status Register [IIC Mode]                    */\r
+    __IO uint32_t  PSR_IISMode;                     /*!< (@ 0x40030048) Protocol Status Register [IIS Mode]                    */\r
+    __IO uint32_t  PSR_SSCMode;                     /*!< (@ 0x40030048) Protocol Status Register [SSC Mode]                    */\r
+    __IO uint32_t  PSR;                             /*!< (@ 0x40030048) Protocol Status Register                               */\r
+    __IO uint32_t  PSR_ASCMode;                     /*!< (@ 0x40030048) Protocol Status Register [ASC Mode]                    */\r
+  };\r
+  __O  uint32_t  PSCR;                              /*!< (@ 0x4003004C) Protocol Status Clear Register                         */\r
+  __I  uint32_t  RBUFSR;                            /*!< (@ 0x40030050) Receiver Buffer Status Register                        */\r
+  __I  uint32_t  RBUF;                              /*!< (@ 0x40030054) Receiver Buffer Register                               */\r
+  __I  uint32_t  RBUFD;                             /*!< (@ 0x40030058) Receiver Buffer Register for Debugger                  */\r
+  __I  uint32_t  RBUF0;                             /*!< (@ 0x4003005C) Receiver Buffer Register 0                             */\r
+  __I  uint32_t  RBUF1;                             /*!< (@ 0x40030060) Receiver Buffer Register 1                             */\r
+  __I  uint32_t  RBUF01SR;                          /*!< (@ 0x40030064) Receiver Buffer 01 Status Register                     */\r
+  __O  uint32_t  FMR;                               /*!< (@ 0x40030068) Flag Modification Register                             */\r
+  __I  uint32_t  RESERVED2[5];\r
+  __IO uint32_t  TBUF[32];                          /*!< (@ 0x40030080) Transmit Buffer                                        */\r
+  __IO uint32_t  BYP;                               /*!< (@ 0x40030100) Bypass Data Register                                   */\r
+  __IO uint32_t  BYPCR;                             /*!< (@ 0x40030104) Bypass Control Register                                */\r
+  __IO uint32_t  TBCTR;                             /*!< (@ 0x40030108) Transmitter Buffer Control Register                    */\r
+  __IO uint32_t  RBCTR;                             /*!< (@ 0x4003010C) Receiver Buffer Control Register                       */\r
+  __I  uint32_t  TRBPTR;                            /*!< (@ 0x40030110) Transmit/Receive Buffer Pointer Register               */\r
+  __IO uint32_t  TRBSR;                             /*!< (@ 0x40030114) Transmit/Receive Buffer Status Register                */\r
+  __O  uint32_t  TRBSCR;                            /*!< (@ 0x40030118) Transmit/Receive Buffer Status Clear Register          */\r
+  __I  uint32_t  OUTR;                              /*!< (@ 0x4003011C) Receiver Buffer Output Register                        */\r
+  __I  uint32_t  OUTDR;                             /*!< (@ 0x40030120) Receiver Buffer Output Register L for Debugger         */\r
+  __I  uint32_t  RESERVED3[23];\r
+  __O  uint32_t  IN[32];                            /*!< (@ 0x40030180) Transmit FIFO Buffer                                   */\r
+} USIC_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       CAN                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Controller Area Networks (CAN)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48014000) CAN Structure                                          */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x48014000) CAN Clock Control Register                             */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x48014008) Module Identification Register                         */\r
+  __IO uint32_t  FDR;                               /*!< (@ 0x4801400C) CAN Fractional Divider Register                        */\r
+  __I  uint32_t  RESERVED1[60];\r
+  __I  uint32_t  LIST[8];                           /*!< (@ 0x48014100) List Register                                          */\r
+  __I  uint32_t  RESERVED2[8];\r
+  __IO uint32_t  MSPND[8];                          /*!< (@ 0x48014140) Message Pending Register                               */\r
+  __I  uint32_t  RESERVED3[8];\r
+  __I  uint32_t  MSID[8];                           /*!< (@ 0x48014180) Message Index Register                                 */\r
+  __I  uint32_t  RESERVED4[8];\r
+  __IO uint32_t  MSIMASK;                           /*!< (@ 0x480141C0) Message Index Mask Register                            */\r
+  __IO uint32_t  PANCTR;                            /*!< (@ 0x480141C4) Panel Control Register                                 */\r
+  __IO uint32_t  MCR;                               /*!< (@ 0x480141C8) Module Control Register                                */\r
+  __O  uint32_t  MITR;                              /*!< (@ 0x480141CC) Module Interrupt Trigger Register                      */\r
+} CAN_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              CAN_NODE [CAN_NODE0]              ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Controller Area Networks (CAN_NODE)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48014200) CAN_NODE Structure                                     */\r
+  __IO uint32_t  NCR;                               /*!< (@ 0x48014200) Node Control Register                                  */\r
+  __IO uint32_t  NSR;                               /*!< (@ 0x48014204) Node Status Register                                   */\r
+  __IO uint32_t  NIPR;                              /*!< (@ 0x48014208) Node Interrupt Pointer Register                        */\r
+  __IO uint32_t  NPCR;                              /*!< (@ 0x4801420C) Node Port Control Register                             */\r
+  __IO uint32_t  NBTR;                              /*!< (@ 0x48014210) Node Bit Timing Register                               */\r
+  __IO uint32_t  NECNT;                             /*!< (@ 0x48014214) Node Error Counter Register                            */\r
+  __IO uint32_t  NFCR;                              /*!< (@ 0x48014218) Node Frame Counter Register                            */\r
+} CAN_NODE_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                CAN_MO [CAN_MO0]                ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Controller Area Networks (CAN_MO)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48015000) CAN_MO Structure                                       */\r
+  __IO uint32_t  MOFCR;                             /*!< (@ 0x48015000) Message Object Function Control Register               */\r
+  __IO uint32_t  MOFGPR;                            /*!< (@ 0x48015004) Message Object FIFO/Gateway Pointer Register           */\r
+  __IO uint32_t  MOIPR;                             /*!< (@ 0x48015008) Message Object Interrupt Pointer Register              */\r
+  __IO uint32_t  MOAMR;                             /*!< (@ 0x4801500C) Message Object Acceptance Mask Register                */\r
+  __IO uint32_t  MODATAL;                           /*!< (@ 0x48015010) Message Object Data Register Low                       */\r
+  __IO uint32_t  MODATAH;                           /*!< (@ 0x48015014) Message Object Data Register High                      */\r
+  __IO uint32_t  MOAR;                              /*!< (@ 0x48015018) Message Object Arbitration Register                    */\r
+  \r
+  union {\r
+    __I  uint32_t  MOSTAT;                          /*!< (@ 0x4801501C) Message Object Status Register                         */\r
+    __O  uint32_t  MOCTR;                           /*!< (@ 0x4801501C) Message Object Control Register                        */\r
+  };\r
+} CAN_MO_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      VADC                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Analog to Digital Converter (VADC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40004000) VADC Structure                                         */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x40004000) Clock Control Register                                 */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x40004008) Module Identification Register                         */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __IO uint32_t  OCS;                               /*!< (@ 0x40004028) OCDS Control and Status Register                       */\r
+  __I  uint32_t  RESERVED2[21];\r
+  __IO uint32_t  GLOBCFG;                           /*!< (@ 0x40004080) Global Configuration Register                          */\r
+  __I  uint32_t  RESERVED3[7];\r
+  __IO uint32_t  GLOBICLASS[2];                     /*!< (@ 0x400040A0) Input Class Register, Global                           */\r
+  __I  uint32_t  RESERVED4[4];\r
+  __IO uint32_t  GLOBBOUND;                         /*!< (@ 0x400040B8) Global Boundary Select Register                        */\r
+  __I  uint32_t  RESERVED5[9];\r
+  __IO uint32_t  GLOBEFLAG;                         /*!< (@ 0x400040E0) Global Event Flag Register                             */\r
+  __I  uint32_t  RESERVED6[23];\r
+  __IO uint32_t  GLOBEVNP;                          /*!< (@ 0x40004140) Global Event Node Pointer Register                     */\r
+  __I  uint32_t  RESERVED7[7];\r
+  __IO uint32_t  GLOBTF;                            /*!< (@ 0x40004160) Global Test Functions Register                         */\r
+  __I  uint32_t  RESERVED8[7];\r
+  __IO uint32_t  BRSSEL[4];                         /*!< (@ 0x40004180) Background Request Source Channel Select Register      */\r
+  __I  uint32_t  RESERVED9[12];\r
+  __IO uint32_t  BRSPND[4];                         /*!< (@ 0x400041C0) Background Request Source Pending Register             */\r
+  __I  uint32_t  RESERVED10[12];\r
+  __IO uint32_t  BRSCTRL;                           /*!< (@ 0x40004200) Background Request Source Control Register             */\r
+  __IO uint32_t  BRSMR;                             /*!< (@ 0x40004204) Background Request Source Mode Register                */\r
+  __I  uint32_t  RESERVED11[30];\r
+  __IO uint32_t  GLOBRCR;                           /*!< (@ 0x40004280) Global Result Control Register                         */\r
+  __I  uint32_t  RESERVED12[31];\r
+  __IO uint32_t  GLOBRES;                           /*!< (@ 0x40004300) Global Result Register                                 */\r
+  __I  uint32_t  RESERVED13[31];\r
+  __IO uint32_t  GLOBRESD;                          /*!< (@ 0x40004380) Global Result Register, Debug                          */\r
+  __I  uint32_t  RESERVED14[27];\r
+  __IO uint32_t  EMUXSEL;                           /*!< (@ 0x400043F0) External Multiplexer Select Register                   */\r
+} VADC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                VADC_G [VADC_G0]                ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Analog to Digital Converter (VADC_G)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40004400) VADC_G Structure                                       */\r
+  __I  uint32_t  RESERVED0[32];\r
+  __IO uint32_t  ARBCFG;                            /*!< (@ 0x40004480) Arbitration Configuration Register                     */\r
+  __IO uint32_t  ARBPR;                             /*!< (@ 0x40004484) Arbitration Priority Register                          */\r
+  __IO uint32_t  CHASS;                             /*!< (@ 0x40004488) Channel Assignment Register                            */\r
+  __I  uint32_t  RESERVED1[5];\r
+  __IO uint32_t  ICLASS[2];                         /*!< (@ 0x400044A0) Input Class Register                                   */\r
+  __I  uint32_t  RESERVED2[2];\r
+  __IO uint32_t  ALIAS;                             /*!< (@ 0x400044B0) Alias Register                                         */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  BOUND;                             /*!< (@ 0x400044B8) Boundary Select Register                               */\r
+  __I  uint32_t  RESERVED4;\r
+  __IO uint32_t  SYNCTR;                            /*!< (@ 0x400044C0) Synchronization Control Register                       */\r
+  __I  uint32_t  RESERVED5;\r
+  __IO uint32_t  BFL;                               /*!< (@ 0x400044C8) Boundary Flag Register                                 */\r
+  __I  uint32_t  RESERVED6[13];\r
+  __IO uint32_t  QCTRL0;                            /*!< (@ 0x40004500) Queue 0 Source Control Register                        */\r
+  __IO uint32_t  QMR0;                              /*!< (@ 0x40004504) Queue 0 Mode Register                                  */\r
+  __I  uint32_t  QSR0;                              /*!< (@ 0x40004508) Queue 0 Status Register                                */\r
+  __I  uint32_t  Q0R0;                              /*!< (@ 0x4000450C) Queue 0 Register 0                                     */\r
+  \r
+  union {\r
+    __I  uint32_t  QBUR0;                           /*!< (@ 0x40004510) Queue 0 Backup Register                                */\r
+    __O  uint32_t  QINR0;                           /*!< (@ 0x40004510) Queue 0 Input Register                                 */\r
+  };\r
+  __I  uint32_t  RESERVED7[3];\r
+  __IO uint32_t  ASCTRL;                            /*!< (@ 0x40004520) Autoscan Source Control Register                       */\r
+  __IO uint32_t  ASMR;                              /*!< (@ 0x40004524) Autoscan Source Mode Register                          */\r
+  __IO uint32_t  ASSEL;                             /*!< (@ 0x40004528) Autoscan Source Channel Select Register                */\r
+  __IO uint32_t  ASPND;                             /*!< (@ 0x4000452C) Autoscan Source Pending Register                       */\r
+  __I  uint32_t  RESERVED8[20];\r
+  __IO uint32_t  CEFLAG;                            /*!< (@ 0x40004580) Channel Event Flag Register                            */\r
+  __IO uint32_t  REFLAG;                            /*!< (@ 0x40004584) Result Event Flag Register                             */\r
+  __IO uint32_t  SEFLAG;                            /*!< (@ 0x40004588) Source Event Flag Register                             */\r
+  __I  uint32_t  RESERVED9;\r
+  __O  uint32_t  CEFCLR;                            /*!< (@ 0x40004590) Channel Event Flag Clear Register                      */\r
+  __O  uint32_t  REFCLR;                            /*!< (@ 0x40004594) Result Event Flag Clear Register                       */\r
+  __O  uint32_t  SEFCLR;                            /*!< (@ 0x40004598) Source Event Flag Clear Register                       */\r
+  __I  uint32_t  RESERVED10;\r
+  __IO uint32_t  CEVNP0;                            /*!< (@ 0x400045A0) Channel Event Node Pointer Register 0                  */\r
+  __I  uint32_t  RESERVED11[3];\r
+  __IO uint32_t  REVNP0;                            /*!< (@ 0x400045B0) Result Event Node Pointer Register 0                   */\r
+  __IO uint32_t  REVNP1;                            /*!< (@ 0x400045B4) Result Event Node Pointer Register 1                   */\r
+  __I  uint32_t  RESERVED12[2];\r
+  __IO uint32_t  SEVNP;                             /*!< (@ 0x400045C0) Source Event Node Pointer Register                     */\r
+  __I  uint32_t  RESERVED13;\r
+  __O  uint32_t  SRACT;                             /*!< (@ 0x400045C8) Service Request Software Activation Trigger            */\r
+  __I  uint32_t  RESERVED14[9];\r
+  __IO uint32_t  EMUXCTR;                           /*!< (@ 0x400045F0) External Multiplexer Control Register                  */\r
+  __I  uint32_t  RESERVED15;\r
+  __IO uint32_t  VFR;                               /*!< (@ 0x400045F8) Valid Flag Register                                    */\r
+  __I  uint32_t  RESERVED16;\r
+  __IO uint32_t  CHCTR[8];                          /*!< (@ 0x40004600) Channel Ctrl. Reg.                                     */\r
+  __I  uint32_t  RESERVED17[24];\r
+  __IO uint32_t  RCR[16];                           /*!< (@ 0x40004680) Result Control Register                                */\r
+  __I  uint32_t  RESERVED18[16];\r
+  __IO uint32_t  RES[16];                           /*!< (@ 0x40004700) Result Register                                        */\r
+  __I  uint32_t  RESERVED19[16];\r
+  __I  uint32_t  RESD[16];                          /*!< (@ 0x40004780) Result Register, Debug                                 */\r
+} VADC_G_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       DSD                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Delta Sigma Demodulator (DSD)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40008000) DSD Structure                                          */\r
+  __IO uint32_t  CLC;                               /*!< (@ 0x40008000) Clock Control Register                                 */\r
+  __I  uint32_t  RESERVED0;\r
+  __I  uint32_t  ID;                                /*!< (@ 0x40008008) Module Identification Register                         */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __IO uint32_t  OCS;                               /*!< (@ 0x40008028) OCDS Control and Status Register                       */\r
+  __I  uint32_t  RESERVED2[21];\r
+  __IO uint32_t  GLOBCFG;                           /*!< (@ 0x40008080) Global Configuration Register                          */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  GLOBRC;                            /*!< (@ 0x40008088) Global Run Control Register                            */\r
+  __I  uint32_t  RESERVED4[5];\r
+  __IO uint32_t  CGCFG;                             /*!< (@ 0x400080A0) Carrier Generator Configuration Register               */\r
+  __I  uint32_t  RESERVED5[15];\r
+  __IO uint32_t  EVFLAG;                            /*!< (@ 0x400080E0) Event Flag Register                                    */\r
+  __O  uint32_t  EVFLAGCLR;                         /*!< (@ 0x400080E4) Event Flag Clear Register                              */\r
+} DSD_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                DSD_CH [DSD_CH0]                ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Delta Sigma Demodulator (DSD_CH)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40008100) DSD_CH Structure                                       */\r
+  __IO uint32_t  MODCFG;                            /*!< (@ 0x40008100) Modulator Configuration Register                       */\r
+  __I  uint32_t  RESERVED0;\r
+  __IO uint32_t  DICFG;                             /*!< (@ 0x40008108) Demodulator Input Configuration Register               */\r
+  __I  uint32_t  RESERVED1[2];\r
+  __IO uint32_t  FCFGC;                             /*!< (@ 0x40008114) Filter Configuration Register, Main Comb Filter        */\r
+  __IO uint32_t  FCFGA;                             /*!< (@ 0x40008118) Filter Configuration Register, Auxiliary Filter        */\r
+  __I  uint32_t  RESERVED2;\r
+  __IO uint32_t  IWCTR;                             /*!< (@ 0x40008120) Integration Window Control Register                    */\r
+  __I  uint32_t  RESERVED3;\r
+  __IO uint32_t  BOUNDSEL;                          /*!< (@ 0x40008128) Boundary Select Register                               */\r
+  __I  uint32_t  RESERVED4;\r
+  __I  uint32_t  RESM;                              /*!< (@ 0x40008130) Result Register, Main Filter                           */\r
+  __I  uint32_t  RESERVED5;\r
+  __IO uint32_t  OFFM;                              /*!< (@ 0x40008138) Offset Register, Main Filter                           */\r
+  __I  uint32_t  RESERVED6;\r
+  __I  uint32_t  RESA;                              /*!< (@ 0x40008140) Result Register, Auxiliary Filter                      */\r
+  __I  uint32_t  RESERVED7[3];\r
+  __I  uint32_t  TSTMP;                             /*!< (@ 0x40008150) Time-Stamp Register                                    */\r
+  __I  uint32_t  RESERVED8[19];\r
+  __IO uint32_t  CGSYNC;                            /*!< (@ 0x400081A0) Carrier Generator Synchronization Register             */\r
+  __I  uint32_t  RESERVED9;\r
+  __IO uint32_t  RECTCFG;                           /*!< (@ 0x400081A8) Rectification Configuration Register                   */\r
+} DSD_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                       DAC                      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Digital to Analog Converter (DAC)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48018000) DAC Structure                                          */\r
+  __I  uint32_t  ID;                                /*!< (@ 0x48018000) Module Identification Register                         */\r
+  __IO uint32_t  DAC0CFG0;                          /*!< (@ 0x48018004) DAC0 Configuration Register 0                          */\r
+  __IO uint32_t  DAC0CFG1;                          /*!< (@ 0x48018008) DAC0 Configuration Register 1                          */\r
+  __IO uint32_t  DAC1CFG0;                          /*!< (@ 0x4801800C) DAC1 Configuration Register 0                          */\r
+  __IO uint32_t  DAC1CFG1;                          /*!< (@ 0x48018010) DAC1 Configuration Register 1                          */\r
+  __IO uint32_t  DAC0DATA;                          /*!< (@ 0x48018014) DAC0 Data Register                                     */\r
+  __IO uint32_t  DAC1DATA;                          /*!< (@ 0x48018018) DAC1 Data Register                                     */\r
+  __IO uint32_t  DAC01DATA;                         /*!< (@ 0x4801801C) DAC01 Data Register                                    */\r
+  __IO uint32_t  DAC0PATL;                          /*!< (@ 0x48018020) DAC0 Lower Pattern Register                            */\r
+  __IO uint32_t  DAC0PATH;                          /*!< (@ 0x48018024) DAC0 Higher Pattern Register                           */\r
+  __IO uint32_t  DAC1PATL;                          /*!< (@ 0x48018028) DAC1 Lower Pattern Register                            */\r
+  __IO uint32_t  DAC1PATH;                          /*!< (@ 0x4801802C) DAC1 Higher Pattern Register                           */\r
+} DAC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  CCU4 [CCU40]                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 4 - Unit 0 (CCU4)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x4000C000) CCU4 Structure                                         */\r
+  __IO uint32_t  GCTRL;                             /*!< (@ 0x4000C000) Global Control Register                                */\r
+  __I  uint32_t  GSTAT;                             /*!< (@ 0x4000C004) Global Status Register                                 */\r
+  __O  uint32_t  GIDLS;                             /*!< (@ 0x4000C008) Global Idle Set                                        */\r
+  __O  uint32_t  GIDLC;                             /*!< (@ 0x4000C00C) Global Idle Clear                                      */\r
+  __O  uint32_t  GCSS;                              /*!< (@ 0x4000C010) Global Channel Set                                     */\r
+  __O  uint32_t  GCSC;                              /*!< (@ 0x4000C014) Global Channel Clear                                   */\r
+  __I  uint32_t  GCST;                              /*!< (@ 0x4000C018) Global Channel Status                                  */\r
+  __I  uint32_t  RESERVED0[13];\r
+  __I  uint32_t  ECRD;                              /*!< (@ 0x4000C050) Extended Capture Mode Read                             */\r
+  __I  uint32_t  RESERVED1[11];\r
+  __I  uint32_t  MIDR;                              /*!< (@ 0x4000C080) Module Identification                                  */\r
+} CCU4_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              CCU4_CC4 [CCU40_CC40]             ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x4000C100) CCU4_CC4 Structure                                     */\r
+  __IO uint32_t  INS;                               /*!< (@ 0x4000C100) Input Selector Configuration                           */\r
+  __IO uint32_t  CMC;                               /*!< (@ 0x4000C104) Connection Matrix Control                              */\r
+  __I  uint32_t  TCST;                              /*!< (@ 0x4000C108) Slice Timer Status                                     */\r
+  __O  uint32_t  TCSET;                             /*!< (@ 0x4000C10C) Slice Timer Run Set                                    */\r
+  __O  uint32_t  TCCLR;                             /*!< (@ 0x4000C110) Slice Timer Clear                                      */\r
+  __IO uint32_t  TC;                                /*!< (@ 0x4000C114) Slice Timer Control                                    */\r
+  __IO uint32_t  PSL;                               /*!< (@ 0x4000C118) Passive Level Config                                   */\r
+  __I  uint32_t  DIT;                               /*!< (@ 0x4000C11C) Dither Config                                          */\r
+  __IO uint32_t  DITS;                              /*!< (@ 0x4000C120) Dither Shadow Register                                 */\r
+  __IO uint32_t  PSC;                               /*!< (@ 0x4000C124) Prescaler Control                                      */\r
+  __IO uint32_t  FPC;                               /*!< (@ 0x4000C128) Floating Prescaler Control                             */\r
+  __IO uint32_t  FPCS;                              /*!< (@ 0x4000C12C) Floating Prescaler Shadow                              */\r
+  __I  uint32_t  PR;                                /*!< (@ 0x4000C130) Timer Period Value                                     */\r
+  __IO uint32_t  PRS;                               /*!< (@ 0x4000C134) Timer Shadow Period Value                              */\r
+  __I  uint32_t  CR;                                /*!< (@ 0x4000C138) Timer Compare Value                                    */\r
+  __IO uint32_t  CRS;                               /*!< (@ 0x4000C13C) Timer Shadow Compare Value                             */\r
+  __I  uint32_t  RESERVED0[12];\r
+  __IO uint32_t  TIMER;                             /*!< (@ 0x4000C170) Timer Value                                            */\r
+  __I  uint32_t  CV[4];                             /*!< (@ 0x4000C174) Capture Register 0                                     */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __I  uint32_t  INTS;                              /*!< (@ 0x4000C1A0) Interrupt Status                                       */\r
+  __IO uint32_t  INTE;                              /*!< (@ 0x4000C1A4) Interrupt Enable Control                               */\r
+  __IO uint32_t  SRS;                               /*!< (@ 0x4000C1A8) Service Request Selector                               */\r
+  __O  uint32_t  SWS;                               /*!< (@ 0x4000C1AC) Interrupt Status Set                                   */\r
+  __O  uint32_t  SWR;                               /*!< (@ 0x4000C1B0) Interrupt Status Clear                                 */\r
+} CCU4_CC4_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                  CCU8 [CCU80]                  ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 8 - Unit 0 (CCU8)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40020000) CCU8 Structure                                         */\r
+  __IO uint32_t  GCTRL;                             /*!< (@ 0x40020000) Global Control Register                                */\r
+  __I  uint32_t  GSTAT;                             /*!< (@ 0x40020004) Global Status Register                                 */\r
+  __O  uint32_t  GIDLS;                             /*!< (@ 0x40020008) Global Idle Set                                        */\r
+  __O  uint32_t  GIDLC;                             /*!< (@ 0x4002000C) Global Idle Clear                                      */\r
+  __O  uint32_t  GCSS;                              /*!< (@ 0x40020010) Global Channel Set                                     */\r
+  __O  uint32_t  GCSC;                              /*!< (@ 0x40020014) Global Channel Clear                                   */\r
+  __I  uint32_t  GCST;                              /*!< (@ 0x40020018) Global Channel status                                  */\r
+  __IO uint32_t  GPCHK;                             /*!< (@ 0x4002001C) Parity Checker Configuration                           */\r
+  __I  uint32_t  RESERVED0[12];\r
+  __I  uint32_t  ECRD;                              /*!< (@ 0x40020050) Extended Capture Mode Read                             */\r
+  __I  uint32_t  RESERVED1[11];\r
+  __I  uint32_t  MIDR;                              /*!< (@ 0x40020080) Module Identification                                  */\r
+} CCU8_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              CCU8_CC8 [CCU80_CC80]             ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Capture Compare Unit 8 - Unit 0 (CCU8_CC8)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40020100) CCU8_CC8 Structure                                     */\r
+  __IO uint32_t  INS;                               /*!< (@ 0x40020100) Input Selector Configuration                           */\r
+  __IO uint32_t  CMC;                               /*!< (@ 0x40020104) Connection Matrix Control                              */\r
+  __I  uint32_t  TCST;                              /*!< (@ 0x40020108) Slice Timer Status                                     */\r
+  __O  uint32_t  TCSET;                             /*!< (@ 0x4002010C) Slice Timer Run Set                                    */\r
+  __O  uint32_t  TCCLR;                             /*!< (@ 0x40020110) Slice Timer Clear                                      */\r
+  __IO uint32_t  TC;                                /*!< (@ 0x40020114) Slice Timer Control                                    */\r
+  __IO uint32_t  PSL;                               /*!< (@ 0x40020118) Passive Level Config                                   */\r
+  __I  uint32_t  DIT;                               /*!< (@ 0x4002011C) Dither Config                                          */\r
+  __IO uint32_t  DITS;                              /*!< (@ 0x40020120) Dither Shadow Register                                 */\r
+  __IO uint32_t  PSC;                               /*!< (@ 0x40020124) Prescaler Control                                      */\r
+  __IO uint32_t  FPC;                               /*!< (@ 0x40020128) Floating Prescaler Control                             */\r
+  __IO uint32_t  FPCS;                              /*!< (@ 0x4002012C) Floating Prescaler Shadow                              */\r
+  __I  uint32_t  PR;                                /*!< (@ 0x40020130) Timer Period Value                                     */\r
+  __IO uint32_t  PRS;                               /*!< (@ 0x40020134) Timer Shadow Period Value                              */\r
+  __I  uint32_t  CR1;                               /*!< (@ 0x40020138) Channel 1 Compare Value                                */\r
+  __IO uint32_t  CR1S;                              /*!< (@ 0x4002013C) Channel 1 Compare Shadow Value                         */\r
+  __I  uint32_t  CR2;                               /*!< (@ 0x40020140) Channel 2 Compare Value                                */\r
+  __IO uint32_t  CR2S;                              /*!< (@ 0x40020144) Channel 2 Compare Shadow Value                         */\r
+  __IO uint32_t  CHC;                               /*!< (@ 0x40020148) Channel Control                                        */\r
+  __IO uint32_t  DTC;                               /*!< (@ 0x4002014C) Dead Time Control                                      */\r
+  __IO uint32_t  DC1R;                              /*!< (@ 0x40020150) Channel 1 Dead Time Values                             */\r
+  __IO uint32_t  DC2R;                              /*!< (@ 0x40020154) Channel 2 Dead Time Values                             */\r
+  __I  uint32_t  RESERVED0[6];\r
+  __IO uint32_t  TIMER;                             /*!< (@ 0x40020170) Timer Value                                            */\r
+  __I  uint32_t  CV[4];                             /*!< (@ 0x40020174) Capture Register 0                                     */\r
+  __I  uint32_t  RESERVED1[7];\r
+  __I  uint32_t  INTS;                              /*!< (@ 0x400201A0) Interrupt Status                                       */\r
+  __IO uint32_t  INTE;                              /*!< (@ 0x400201A4) Interrupt Enable Control                               */\r
+  __IO uint32_t  SRS;                               /*!< (@ 0x400201A8) Service Request Selector                               */\r
+  __O  uint32_t  SWS;                               /*!< (@ 0x400201AC) Interrupt Status Set                                   */\r
+  __O  uint32_t  SWR;                               /*!< (@ 0x400201B0) Interrupt Status Clear                                 */\r
+} CCU8_CC8_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                 POSIF [POSIF0]                 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Position Interface 0 (POSIF)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x40028000) POSIF Structure                                        */\r
+  __IO uint32_t  PCONF;                             /*!< (@ 0x40028000) POSIF configuration                                    */\r
+  __IO uint32_t  PSUS;                              /*!< (@ 0x40028004) POSIF Suspend Config                                   */\r
+  __O  uint32_t  PRUNS;                             /*!< (@ 0x40028008) POSIF Run Bit Set                                      */\r
+  __O  uint32_t  PRUNC;                             /*!< (@ 0x4002800C) POSIF Run Bit Clear                                    */\r
+  __I  uint32_t  PRUN;                              /*!< (@ 0x40028010) POSIF Run Bit Status                                   */\r
+  __I  uint32_t  RESERVED0[3];\r
+  __I  uint32_t  MIDR;                              /*!< (@ 0x40028020) Module Identification register                         */\r
+  __I  uint32_t  RESERVED1[3];\r
+  __I  uint32_t  HALP;                              /*!< (@ 0x40028030) Hall Sensor Patterns                                   */\r
+  __IO uint32_t  HALPS;                             /*!< (@ 0x40028034) Hall Sensor Shadow Patterns                            */\r
+  __I  uint32_t  RESERVED2[2];\r
+  __I  uint32_t  MCM;                               /*!< (@ 0x40028040) Multi-Channel Pattern                                  */\r
+  __IO uint32_t  MCSM;                              /*!< (@ 0x40028044) Multi-Channel Shadow Pattern                           */\r
+  __O  uint32_t  MCMS;                              /*!< (@ 0x40028048) Multi-Channel Pattern Control set                      */\r
+  __O  uint32_t  MCMC;                              /*!< (@ 0x4002804C) Multi-Channel Pattern Control clear                    */\r
+  __I  uint32_t  MCMF;                              /*!< (@ 0x40028050) Multi-Channel Pattern Control flag                     */\r
+  __I  uint32_t  RESERVED3[3];\r
+  __IO uint32_t  QDC;                               /*!< (@ 0x40028060) Quadrature Decoder Control                             */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __I  uint32_t  PFLG;                              /*!< (@ 0x40028070) POSIF Interrupt Flags                                  */\r
+  __IO uint32_t  PFLGE;                             /*!< (@ 0x40028074) POSIF Interrupt Enable                                 */\r
+  __O  uint32_t  SPFLG;                             /*!< (@ 0x40028078) POSIF Interrupt Set                                    */\r
+  __O  uint32_t  RPFLG;                             /*!< (@ 0x4002807C) POSIF Interrupt Clear                                  */\r
+  __I  uint32_t  RESERVED5[32];\r
+  __I  uint32_t  PDBG;                              /*!< (@ 0x40028100) POSIF Debug register                                   */\r
+} POSIF_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT0                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 0 (PORT0)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028000) PORT0 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028000) Port 0 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028004) Port 0 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028010) Port 0 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028014) Port 0 Input/Output Control Register 4                 */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028018) Port 0 Input/Output Control Register 8                 */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x4802801C) Port 0 Input/Output Control Register 12                */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028024) Port 0 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028040) Port 0 Pad Driver Mode 0 Register                      */\r
+  __IO uint32_t  PDR1;                              /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Register                      */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028060) Port 0 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028070) Port 0 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028074) Port 0 Pin Hardware Select Register                    */\r
+} PORT0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT1                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 1 (PORT1)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028100) PORT1 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028100) Port 1 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028104) Port 1 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028110) Port 1 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028114) Port 1 Input/Output Control Register 4                 */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028118) Port 1 Input/Output Control Register 8                 */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x4802811C) Port 1 Input/Output Control Register 12                */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028124) Port 1 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028140) Port 1 Pad Driver Mode 0 Register                      */\r
+  __IO uint32_t  PDR1;                              /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Register                      */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028160) Port 1 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028170) Port 1 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028174) Port 1 Pin Hardware Select Register                    */\r
+} PORT1_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT2                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 2 (PORT2)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028200) PORT2 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028200) Port 2 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028204) Port 2 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028210) Port 2 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028214) Port 2 Input/Output Control Register 4                 */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028218) Port 2 Input/Output Control Register 8                 */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x4802821C) Port 2 Input/Output Control Register 12                */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028224) Port 2 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028240) Port 2 Pad Driver Mode 0 Register                      */\r
+  __IO uint32_t  PDR1;                              /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Register                      */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028260) Port 2 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028270) Port 2 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028274) Port 2 Pin Hardware Select Register                    */\r
+} PORT2_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT3                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 3 (PORT3)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028300) PORT3 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028300) Port 3 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028304) Port 3 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028310) Port 3 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028314) Port 3 Input/Output Control Register 4                 */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028318) Port 3 Input/Output Control Register 8                 */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x4802831C) Port 3 Input/Output Control Register 12                */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028324) Port 3 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028340) Port 3 Pad Driver Mode 0 Register                      */\r
+  __IO uint32_t  PDR1;                              /*!< (@ 0x48028344) Port 3 Pad Driver Mode 1 Register                      */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028360) Port 3 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028370) Port 3 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028374) Port 3 Pin Hardware Select Register                    */\r
+} PORT3_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT4                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 4 (PORT4)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028400) PORT4 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028400) Port 4 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028404) Port 4 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028410) Port 4 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028414) Port 4 Input/Output Control Register 4                 */\r
+  __I  uint32_t  RESERVED1[3];\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028424) Port 4 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028440) Port 4 Pad Driver Mode 0 Register                      */\r
+  __I  uint32_t  RESERVED3[7];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028460) Port 4 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028470) Port 4 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028474) Port 4 Pin Hardware Select Register                    */\r
+} PORT4_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT5                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 5 (PORT5)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028500) PORT5 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028500) Port 5 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028504) Port 5 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028510) Port 5 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028514) Port 5 Input/Output Control Register 4                 */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028518) Port 5 Input/Output Control Register 8                 */\r
+  __I  uint32_t  RESERVED1[2];\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028524) Port 5 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028540) Port 5 Pad Driver Mode 0 Register                      */\r
+  __IO uint32_t  PDR1;                              /*!< (@ 0x48028544) Port 5 Pad Driver Mode 1 Register                      */\r
+  __I  uint32_t  RESERVED3[6];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028560) Port 5 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028570) Port 5 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028574) Port 5 Pin Hardware Select Register                    */\r
+} PORT5_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                      PORT6                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 6 (PORT6)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028600) PORT6 Structure                                        */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028600) Port 6 Output Register                                 */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028604) Port 6 Output Modification Register                    */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028610) Port 6 Input/Output Control Register 0                 */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028614) Port 6 Input/Output Control Register 4                 */\r
+  __I  uint32_t  RESERVED1[3];\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028624) Port 6 Input Register                                  */\r
+  __I  uint32_t  RESERVED2[6];\r
+  __IO uint32_t  PDR0;                              /*!< (@ 0x48028640) Port 6 Pad Driver Mode 0 Register                      */\r
+  __I  uint32_t  RESERVED3[7];\r
+  __I  uint32_t  PDISC;                             /*!< (@ 0x48028660) Port 6 Pin Function Decision Control Register          */\r
+  __I  uint32_t  RESERVED4[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028670) Port 6 Pin Power Save Register                         */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028674) Port 6 Pin Hardware Select Register                    */\r
+} PORT6_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     PORT14                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 14 (PORT14)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028E00) PORT14 Structure                                       */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028E00) Port 14 Output Register                                */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028E04) Port 14 Output Modification Register                   */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028E10) Port 14 Input/Output Control Register 0                */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028E14) Port 14 Input/Output Control Register 4                */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028E18) Port 14 Input/Output Control Register 8                */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x48028E1C) Port 14 Input/Output Control Register 12               */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028E24) Port 14 Input Register                                 */\r
+  __I  uint32_t  RESERVED2[14];\r
+  __IO uint32_t  PDISC;                             /*!< (@ 0x48028E60) Port 14 Pin Function Decision Control Register         */\r
+  __I  uint32_t  RESERVED3[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028E70) Port 14 Pin Power Save Register                        */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028E74) Port 14 Pin Hardware Select Register                   */\r
+} PORT14_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================                     PORT15                     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+  * @brief Port 15 (PORT15)\r
+  */\r
+\r
+typedef struct {                                    /*!< (@ 0x48028F00) PORT15 Structure                                       */\r
+  __IO uint32_t  OUT;                               /*!< (@ 0x48028F00) Port 15 Output Register                                */\r
+  __O  uint32_t  OMR;                               /*!< (@ 0x48028F04) Port 15 Output Modification Register                   */\r
+  __I  uint32_t  RESERVED0[2];\r
+  __IO uint32_t  IOCR0;                             /*!< (@ 0x48028F10) Port 15 Input/Output Control Register 0                */\r
+  __IO uint32_t  IOCR4;                             /*!< (@ 0x48028F14) Port 15 Input/Output Control Register 4                */\r
+  __IO uint32_t  IOCR8;                             /*!< (@ 0x48028F18) Port 15 Input/Output Control Register 8                */\r
+  __IO uint32_t  IOCR12;                            /*!< (@ 0x48028F1C) Port 15 Input/Output Control Register 12               */\r
+  __I  uint32_t  RESERVED1;\r
+  __I  uint32_t  IN;                                /*!< (@ 0x48028F24) Port 15 Input Register                                 */\r
+  __I  uint32_t  RESERVED2[14];\r
+  __IO uint32_t  PDISC;                             /*!< (@ 0x48028F60) Port 15 Pin Function Decision Control Register         */\r
+  __I  uint32_t  RESERVED3[3];\r
+  __IO uint32_t  PPS;                               /*!< (@ 0x48028F70) Port 15 Pin Power Save Register                        */\r
+  __IO uint32_t  HWSEL;                             /*!< (@ 0x48028F74) Port 15 Pin Hardware Select Register                   */\r
+} PORT15_Type;\r
+\r
+\r
+/* --------------------  End of section using anonymous unions  ------------------- */\r
+#if defined(__CC_ARM)\r
+  #pragma pop\r
+#elif defined(__ICCARM__)\r
+  /* leave anonymous unions enabled */\r
+#elif defined(__GNUC__)\r
+  /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+  /* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+  #pragma warning restore\r
+#else\r
+  #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'PPB' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PPB_ACTLR  --------------------------------- */\r
+#define PPB_ACTLR_DISMCYCINT_Pos              0                                                       /*!< PPB ACTLR: DISMCYCINT Position          */\r
+#define PPB_ACTLR_DISMCYCINT_Msk              (0x01UL << PPB_ACTLR_DISMCYCINT_Pos)                    /*!< PPB ACTLR: DISMCYCINT Mask              */\r
+#define PPB_ACTLR_DISDEFWBUF_Pos              1                                                       /*!< PPB ACTLR: DISDEFWBUF Position          */\r
+#define PPB_ACTLR_DISDEFWBUF_Msk              (0x01UL << PPB_ACTLR_DISDEFWBUF_Pos)                    /*!< PPB ACTLR: DISDEFWBUF Mask              */\r
+#define PPB_ACTLR_DISFOLD_Pos                 2                                                       /*!< PPB ACTLR: DISFOLD Position             */\r
+#define PPB_ACTLR_DISFOLD_Msk                 (0x01UL << PPB_ACTLR_DISFOLD_Pos)                       /*!< PPB ACTLR: DISFOLD Mask                 */\r
+#define PPB_ACTLR_DISFPCA_Pos                 8                                                       /*!< PPB ACTLR: DISFPCA Position             */\r
+#define PPB_ACTLR_DISFPCA_Msk                 (0x01UL << PPB_ACTLR_DISFPCA_Pos)                       /*!< PPB ACTLR: DISFPCA Mask                 */\r
+#define PPB_ACTLR_DISOOFP_Pos                 9                                                       /*!< PPB ACTLR: DISOOFP Position             */\r
+#define PPB_ACTLR_DISOOFP_Msk                 (0x01UL << PPB_ACTLR_DISOOFP_Pos)                       /*!< PPB ACTLR: DISOOFP Mask                 */\r
+\r
+/* --------------------------------  PPB_SYST_CSR  -------------------------------- */\r
+#define PPB_SYST_CSR_ENABLE_Pos               0                                                       /*!< PPB SYST_CSR: ENABLE Position           */\r
+#define PPB_SYST_CSR_ENABLE_Msk               (0x01UL << PPB_SYST_CSR_ENABLE_Pos)                     /*!< PPB SYST_CSR: ENABLE Mask               */\r
+#define PPB_SYST_CSR_TICKINT_Pos              1                                                       /*!< PPB SYST_CSR: TICKINT Position          */\r
+#define PPB_SYST_CSR_TICKINT_Msk              (0x01UL << PPB_SYST_CSR_TICKINT_Pos)                    /*!< PPB SYST_CSR: TICKINT Mask              */\r
+#define PPB_SYST_CSR_CLKSOURCE_Pos            2                                                       /*!< PPB SYST_CSR: CLKSOURCE Position        */\r
+#define PPB_SYST_CSR_CLKSOURCE_Msk            (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos)                  /*!< PPB SYST_CSR: CLKSOURCE Mask            */\r
+#define PPB_SYST_CSR_COUNTFLAG_Pos            16                                                      /*!< PPB SYST_CSR: COUNTFLAG Position        */\r
+#define PPB_SYST_CSR_COUNTFLAG_Msk            (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos)                  /*!< PPB SYST_CSR: COUNTFLAG Mask            */\r
+\r
+/* --------------------------------  PPB_SYST_RVR  -------------------------------- */\r
+#define PPB_SYST_RVR_RELOAD_Pos               0                                                       /*!< PPB SYST_RVR: RELOAD Position           */\r
+#define PPB_SYST_RVR_RELOAD_Msk               (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos)               /*!< PPB SYST_RVR: RELOAD Mask               */\r
+\r
+/* --------------------------------  PPB_SYST_CVR  -------------------------------- */\r
+#define PPB_SYST_CVR_CURRENT_Pos              0                                                       /*!< PPB SYST_CVR: CURRENT Position          */\r
+#define PPB_SYST_CVR_CURRENT_Msk              (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos)              /*!< PPB SYST_CVR: CURRENT Mask              */\r
+\r
+/* -------------------------------  PPB_SYST_CALIB  ------------------------------- */\r
+#define PPB_SYST_CALIB_TENMS_Pos              0                                                       /*!< PPB SYST_CALIB: TENMS Position          */\r
+#define PPB_SYST_CALIB_TENMS_Msk              (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos)              /*!< PPB SYST_CALIB: TENMS Mask              */\r
+#define PPB_SYST_CALIB_SKEW_Pos               30                                                      /*!< PPB SYST_CALIB: SKEW Position           */\r
+#define PPB_SYST_CALIB_SKEW_Msk               (0x01UL << PPB_SYST_CALIB_SKEW_Pos)                     /*!< PPB SYST_CALIB: SKEW Mask               */\r
+#define PPB_SYST_CALIB_NOREF_Pos              31                                                      /*!< PPB SYST_CALIB: NOREF Position          */\r
+#define PPB_SYST_CALIB_NOREF_Msk              (0x01UL << PPB_SYST_CALIB_NOREF_Pos)                    /*!< PPB SYST_CALIB: NOREF Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER0  ------------------------------- */\r
+#define PPB_NVIC_ISER0_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER0: SETENA Position         */\r
+#define PPB_NVIC_ISER0_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER0_SETENA_Pos)             /*!< PPB NVIC_ISER0: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER1  ------------------------------- */\r
+#define PPB_NVIC_ISER1_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER1: SETENA Position         */\r
+#define PPB_NVIC_ISER1_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER1_SETENA_Pos)             /*!< PPB NVIC_ISER1: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER2  ------------------------------- */\r
+#define PPB_NVIC_ISER2_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER2: SETENA Position         */\r
+#define PPB_NVIC_ISER2_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER2_SETENA_Pos)             /*!< PPB NVIC_ISER2: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISER3  ------------------------------- */\r
+#define PPB_NVIC_ISER3_SETENA_Pos             0                                                       /*!< PPB NVIC_ISER3: SETENA Position         */\r
+#define PPB_NVIC_ISER3_SETENA_Msk             (0xffffffffUL << PPB_NVIC_ISER3_SETENA_Pos)             /*!< PPB NVIC_ISER3: SETENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER0  ------------------------------- */\r
+#define PPB_NVIC_ICER0_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER0: CLRENA Position         */\r
+#define PPB_NVIC_ICER0_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER0_CLRENA_Pos)             /*!< PPB NVIC_ICER0: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER1  ------------------------------- */\r
+#define PPB_NVIC_ICER1_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER1: CLRENA Position         */\r
+#define PPB_NVIC_ICER1_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER1_CLRENA_Pos)             /*!< PPB NVIC_ICER1: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER2  ------------------------------- */\r
+#define PPB_NVIC_ICER2_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER2: CLRENA Position         */\r
+#define PPB_NVIC_ICER2_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER2_CLRENA_Pos)             /*!< PPB NVIC_ICER2: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ICER3  ------------------------------- */\r
+#define PPB_NVIC_ICER3_CLRENA_Pos             0                                                       /*!< PPB NVIC_ICER3: CLRENA Position         */\r
+#define PPB_NVIC_ICER3_CLRENA_Msk             (0xffffffffUL << PPB_NVIC_ICER3_CLRENA_Pos)             /*!< PPB NVIC_ICER3: CLRENA Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR0  ------------------------------- */\r
+#define PPB_NVIC_ISPR0_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR0: SETPEND Position        */\r
+#define PPB_NVIC_ISPR0_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR0_SETPEND_Pos)            /*!< PPB NVIC_ISPR0: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR1  ------------------------------- */\r
+#define PPB_NVIC_ISPR1_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR1: SETPEND Position        */\r
+#define PPB_NVIC_ISPR1_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR1_SETPEND_Pos)            /*!< PPB NVIC_ISPR1: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR2  ------------------------------- */\r
+#define PPB_NVIC_ISPR2_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR2: SETPEND Position        */\r
+#define PPB_NVIC_ISPR2_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR2_SETPEND_Pos)            /*!< PPB NVIC_ISPR2: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ISPR3  ------------------------------- */\r
+#define PPB_NVIC_ISPR3_SETPEND_Pos            0                                                       /*!< PPB NVIC_ISPR3: SETPEND Position        */\r
+#define PPB_NVIC_ISPR3_SETPEND_Msk            (0xffffffffUL << PPB_NVIC_ISPR3_SETPEND_Pos)            /*!< PPB NVIC_ISPR3: SETPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR0  ------------------------------- */\r
+#define PPB_NVIC_ICPR0_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR0: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR0_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR0_CLRPEND_Pos)            /*!< PPB NVIC_ICPR0: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR1  ------------------------------- */\r
+#define PPB_NVIC_ICPR1_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR1: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR1_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR1_CLRPEND_Pos)            /*!< PPB NVIC_ICPR1: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR2  ------------------------------- */\r
+#define PPB_NVIC_ICPR2_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR2: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR2_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR2_CLRPEND_Pos)            /*!< PPB NVIC_ICPR2: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_ICPR3  ------------------------------- */\r
+#define PPB_NVIC_ICPR3_CLRPEND_Pos            0                                                       /*!< PPB NVIC_ICPR3: CLRPEND Position        */\r
+#define PPB_NVIC_ICPR3_CLRPEND_Msk            (0xffffffffUL << PPB_NVIC_ICPR3_CLRPEND_Pos)            /*!< PPB NVIC_ICPR3: CLRPEND Mask            */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR0  ------------------------------- */\r
+#define PPB_NVIC_IABR0_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR0: ACTIVE Position         */\r
+#define PPB_NVIC_IABR0_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR0_ACTIVE_Pos)             /*!< PPB NVIC_IABR0: ACTIVE Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR1  ------------------------------- */\r
+#define PPB_NVIC_IABR1_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR1: ACTIVE Position         */\r
+#define PPB_NVIC_IABR1_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR1_ACTIVE_Pos)             /*!< PPB NVIC_IABR1: ACTIVE Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR2  ------------------------------- */\r
+#define PPB_NVIC_IABR2_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR2: ACTIVE Position         */\r
+#define PPB_NVIC_IABR2_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR2_ACTIVE_Pos)             /*!< PPB NVIC_IABR2: ACTIVE Mask             */\r
+\r
+/* -------------------------------  PPB_NVIC_IABR3  ------------------------------- */\r
+#define PPB_NVIC_IABR3_ACTIVE_Pos             0                                                       /*!< PPB NVIC_IABR3: ACTIVE Position         */\r
+#define PPB_NVIC_IABR3_ACTIVE_Msk             (0xffffffffUL << PPB_NVIC_IABR3_ACTIVE_Pos)             /*!< PPB NVIC_IABR3: ACTIVE Mask             */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR0  ------------------------------- */\r
+#define PPB_NVIC_IPR0_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR0: PRI_0 Position           */\r
+#define PPB_NVIC_IPR0_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos)               /*!< PPB NVIC_IPR0: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR0_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR0: PRI_1 Position           */\r
+#define PPB_NVIC_IPR0_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos)               /*!< PPB NVIC_IPR0: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR0_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR0: PRI_2 Position           */\r
+#define PPB_NVIC_IPR0_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos)               /*!< PPB NVIC_IPR0: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR0_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR0: PRI_3 Position           */\r
+#define PPB_NVIC_IPR0_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos)               /*!< PPB NVIC_IPR0: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR1  ------------------------------- */\r
+#define PPB_NVIC_IPR1_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR1: PRI_0 Position           */\r
+#define PPB_NVIC_IPR1_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos)               /*!< PPB NVIC_IPR1: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR1_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR1: PRI_1 Position           */\r
+#define PPB_NVIC_IPR1_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos)               /*!< PPB NVIC_IPR1: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR1_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR1: PRI_2 Position           */\r
+#define PPB_NVIC_IPR1_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos)               /*!< PPB NVIC_IPR1: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR1_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR1: PRI_3 Position           */\r
+#define PPB_NVIC_IPR1_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos)               /*!< PPB NVIC_IPR1: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR2  ------------------------------- */\r
+#define PPB_NVIC_IPR2_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR2: PRI_0 Position           */\r
+#define PPB_NVIC_IPR2_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos)               /*!< PPB NVIC_IPR2: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR2_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR2: PRI_1 Position           */\r
+#define PPB_NVIC_IPR2_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos)               /*!< PPB NVIC_IPR2: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR2_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR2: PRI_2 Position           */\r
+#define PPB_NVIC_IPR2_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos)               /*!< PPB NVIC_IPR2: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR2_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR2: PRI_3 Position           */\r
+#define PPB_NVIC_IPR2_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos)               /*!< PPB NVIC_IPR2: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR3  ------------------------------- */\r
+#define PPB_NVIC_IPR3_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR3: PRI_0 Position           */\r
+#define PPB_NVIC_IPR3_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos)               /*!< PPB NVIC_IPR3: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR3_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR3: PRI_1 Position           */\r
+#define PPB_NVIC_IPR3_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos)               /*!< PPB NVIC_IPR3: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR3_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR3: PRI_2 Position           */\r
+#define PPB_NVIC_IPR3_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos)               /*!< PPB NVIC_IPR3: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR3_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR3: PRI_3 Position           */\r
+#define PPB_NVIC_IPR3_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos)               /*!< PPB NVIC_IPR3: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR4  ------------------------------- */\r
+#define PPB_NVIC_IPR4_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR4: PRI_0 Position           */\r
+#define PPB_NVIC_IPR4_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos)               /*!< PPB NVIC_IPR4: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR4_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR4: PRI_1 Position           */\r
+#define PPB_NVIC_IPR4_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos)               /*!< PPB NVIC_IPR4: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR4_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR4: PRI_2 Position           */\r
+#define PPB_NVIC_IPR4_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos)               /*!< PPB NVIC_IPR4: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR4_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR4: PRI_3 Position           */\r
+#define PPB_NVIC_IPR4_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos)               /*!< PPB NVIC_IPR4: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR5  ------------------------------- */\r
+#define PPB_NVIC_IPR5_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR5: PRI_0 Position           */\r
+#define PPB_NVIC_IPR5_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos)               /*!< PPB NVIC_IPR5: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR5_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR5: PRI_1 Position           */\r
+#define PPB_NVIC_IPR5_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos)               /*!< PPB NVIC_IPR5: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR5_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR5: PRI_2 Position           */\r
+#define PPB_NVIC_IPR5_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos)               /*!< PPB NVIC_IPR5: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR5_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR5: PRI_3 Position           */\r
+#define PPB_NVIC_IPR5_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos)               /*!< PPB NVIC_IPR5: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR6  ------------------------------- */\r
+#define PPB_NVIC_IPR6_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR6: PRI_0 Position           */\r
+#define PPB_NVIC_IPR6_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos)               /*!< PPB NVIC_IPR6: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR6_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR6: PRI_1 Position           */\r
+#define PPB_NVIC_IPR6_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos)               /*!< PPB NVIC_IPR6: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR6_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR6: PRI_2 Position           */\r
+#define PPB_NVIC_IPR6_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos)               /*!< PPB NVIC_IPR6: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR6_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR6: PRI_3 Position           */\r
+#define PPB_NVIC_IPR6_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos)               /*!< PPB NVIC_IPR6: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR7  ------------------------------- */\r
+#define PPB_NVIC_IPR7_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR7: PRI_0 Position           */\r
+#define PPB_NVIC_IPR7_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos)               /*!< PPB NVIC_IPR7: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR7_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR7: PRI_1 Position           */\r
+#define PPB_NVIC_IPR7_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos)               /*!< PPB NVIC_IPR7: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR7_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR7: PRI_2 Position           */\r
+#define PPB_NVIC_IPR7_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos)               /*!< PPB NVIC_IPR7: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR7_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR7: PRI_3 Position           */\r
+#define PPB_NVIC_IPR7_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos)               /*!< PPB NVIC_IPR7: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR8  ------------------------------- */\r
+#define PPB_NVIC_IPR8_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR8: PRI_0 Position           */\r
+#define PPB_NVIC_IPR8_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_0_Pos)               /*!< PPB NVIC_IPR8: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR8_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR8: PRI_1 Position           */\r
+#define PPB_NVIC_IPR8_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_1_Pos)               /*!< PPB NVIC_IPR8: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR8_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR8: PRI_2 Position           */\r
+#define PPB_NVIC_IPR8_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_2_Pos)               /*!< PPB NVIC_IPR8: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR8_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR8: PRI_3 Position           */\r
+#define PPB_NVIC_IPR8_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR8_PRI_3_Pos)               /*!< PPB NVIC_IPR8: PRI_3 Mask               */\r
+\r
+/* --------------------------------  PPB_NVIC_IPR9  ------------------------------- */\r
+#define PPB_NVIC_IPR9_PRI_0_Pos               0                                                       /*!< PPB NVIC_IPR9: PRI_0 Position           */\r
+#define PPB_NVIC_IPR9_PRI_0_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_0_Pos)               /*!< PPB NVIC_IPR9: PRI_0 Mask               */\r
+#define PPB_NVIC_IPR9_PRI_1_Pos               8                                                       /*!< PPB NVIC_IPR9: PRI_1 Position           */\r
+#define PPB_NVIC_IPR9_PRI_1_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_1_Pos)               /*!< PPB NVIC_IPR9: PRI_1 Mask               */\r
+#define PPB_NVIC_IPR9_PRI_2_Pos               16                                                      /*!< PPB NVIC_IPR9: PRI_2 Position           */\r
+#define PPB_NVIC_IPR9_PRI_2_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_2_Pos)               /*!< PPB NVIC_IPR9: PRI_2 Mask               */\r
+#define PPB_NVIC_IPR9_PRI_3_Pos               24                                                      /*!< PPB NVIC_IPR9: PRI_3 Position           */\r
+#define PPB_NVIC_IPR9_PRI_3_Msk               (0x000000ffUL << PPB_NVIC_IPR9_PRI_3_Pos)               /*!< PPB NVIC_IPR9: PRI_3 Mask               */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR10  ------------------------------- */\r
+#define PPB_NVIC_IPR10_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR10: PRI_0 Position          */\r
+#define PPB_NVIC_IPR10_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_0_Pos)              /*!< PPB NVIC_IPR10: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR10_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR10: PRI_1 Position          */\r
+#define PPB_NVIC_IPR10_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_1_Pos)              /*!< PPB NVIC_IPR10: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR10_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR10: PRI_2 Position          */\r
+#define PPB_NVIC_IPR10_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_2_Pos)              /*!< PPB NVIC_IPR10: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR10_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR10: PRI_3 Position          */\r
+#define PPB_NVIC_IPR10_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR10_PRI_3_Pos)              /*!< PPB NVIC_IPR10: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR11  ------------------------------- */\r
+#define PPB_NVIC_IPR11_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR11: PRI_0 Position          */\r
+#define PPB_NVIC_IPR11_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_0_Pos)              /*!< PPB NVIC_IPR11: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR11_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR11: PRI_1 Position          */\r
+#define PPB_NVIC_IPR11_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_1_Pos)              /*!< PPB NVIC_IPR11: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR11_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR11: PRI_2 Position          */\r
+#define PPB_NVIC_IPR11_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_2_Pos)              /*!< PPB NVIC_IPR11: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR11_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR11: PRI_3 Position          */\r
+#define PPB_NVIC_IPR11_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR11_PRI_3_Pos)              /*!< PPB NVIC_IPR11: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR12  ------------------------------- */\r
+#define PPB_NVIC_IPR12_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR12: PRI_0 Position          */\r
+#define PPB_NVIC_IPR12_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_0_Pos)              /*!< PPB NVIC_IPR12: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR12_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR12: PRI_1 Position          */\r
+#define PPB_NVIC_IPR12_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_1_Pos)              /*!< PPB NVIC_IPR12: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR12_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR12: PRI_2 Position          */\r
+#define PPB_NVIC_IPR12_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_2_Pos)              /*!< PPB NVIC_IPR12: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR12_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR12: PRI_3 Position          */\r
+#define PPB_NVIC_IPR12_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR12_PRI_3_Pos)              /*!< PPB NVIC_IPR12: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR13  ------------------------------- */\r
+#define PPB_NVIC_IPR13_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR13: PRI_0 Position          */\r
+#define PPB_NVIC_IPR13_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_0_Pos)              /*!< PPB NVIC_IPR13: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR13_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR13: PRI_1 Position          */\r
+#define PPB_NVIC_IPR13_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_1_Pos)              /*!< PPB NVIC_IPR13: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR13_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR13: PRI_2 Position          */\r
+#define PPB_NVIC_IPR13_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_2_Pos)              /*!< PPB NVIC_IPR13: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR13_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR13: PRI_3 Position          */\r
+#define PPB_NVIC_IPR13_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR13_PRI_3_Pos)              /*!< PPB NVIC_IPR13: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR14  ------------------------------- */\r
+#define PPB_NVIC_IPR14_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR14: PRI_0 Position          */\r
+#define PPB_NVIC_IPR14_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_0_Pos)              /*!< PPB NVIC_IPR14: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR14_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR14: PRI_1 Position          */\r
+#define PPB_NVIC_IPR14_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_1_Pos)              /*!< PPB NVIC_IPR14: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR14_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR14: PRI_2 Position          */\r
+#define PPB_NVIC_IPR14_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_2_Pos)              /*!< PPB NVIC_IPR14: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR14_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR14: PRI_3 Position          */\r
+#define PPB_NVIC_IPR14_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR14_PRI_3_Pos)              /*!< PPB NVIC_IPR14: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR15  ------------------------------- */\r
+#define PPB_NVIC_IPR15_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR15: PRI_0 Position          */\r
+#define PPB_NVIC_IPR15_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_0_Pos)              /*!< PPB NVIC_IPR15: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR15_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR15: PRI_1 Position          */\r
+#define PPB_NVIC_IPR15_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_1_Pos)              /*!< PPB NVIC_IPR15: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR15_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR15: PRI_2 Position          */\r
+#define PPB_NVIC_IPR15_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_2_Pos)              /*!< PPB NVIC_IPR15: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR15_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR15: PRI_3 Position          */\r
+#define PPB_NVIC_IPR15_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR15_PRI_3_Pos)              /*!< PPB NVIC_IPR15: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR16  ------------------------------- */\r
+#define PPB_NVIC_IPR16_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR16: PRI_0 Position          */\r
+#define PPB_NVIC_IPR16_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_0_Pos)              /*!< PPB NVIC_IPR16: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR16_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR16: PRI_1 Position          */\r
+#define PPB_NVIC_IPR16_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_1_Pos)              /*!< PPB NVIC_IPR16: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR16_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR16: PRI_2 Position          */\r
+#define PPB_NVIC_IPR16_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_2_Pos)              /*!< PPB NVIC_IPR16: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR16_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR16: PRI_3 Position          */\r
+#define PPB_NVIC_IPR16_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR16_PRI_3_Pos)              /*!< PPB NVIC_IPR16: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR17  ------------------------------- */\r
+#define PPB_NVIC_IPR17_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR17: PRI_0 Position          */\r
+#define PPB_NVIC_IPR17_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_0_Pos)              /*!< PPB NVIC_IPR17: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR17_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR17: PRI_1 Position          */\r
+#define PPB_NVIC_IPR17_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_1_Pos)              /*!< PPB NVIC_IPR17: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR17_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR17: PRI_2 Position          */\r
+#define PPB_NVIC_IPR17_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_2_Pos)              /*!< PPB NVIC_IPR17: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR17_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR17: PRI_3 Position          */\r
+#define PPB_NVIC_IPR17_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR17_PRI_3_Pos)              /*!< PPB NVIC_IPR17: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR18  ------------------------------- */\r
+#define PPB_NVIC_IPR18_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR18: PRI_0 Position          */\r
+#define PPB_NVIC_IPR18_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_0_Pos)              /*!< PPB NVIC_IPR18: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR18_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR18: PRI_1 Position          */\r
+#define PPB_NVIC_IPR18_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_1_Pos)              /*!< PPB NVIC_IPR18: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR18_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR18: PRI_2 Position          */\r
+#define PPB_NVIC_IPR18_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_2_Pos)              /*!< PPB NVIC_IPR18: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR18_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR18: PRI_3 Position          */\r
+#define PPB_NVIC_IPR18_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR18_PRI_3_Pos)              /*!< PPB NVIC_IPR18: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR19  ------------------------------- */\r
+#define PPB_NVIC_IPR19_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR19: PRI_0 Position          */\r
+#define PPB_NVIC_IPR19_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_0_Pos)              /*!< PPB NVIC_IPR19: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR19_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR19: PRI_1 Position          */\r
+#define PPB_NVIC_IPR19_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_1_Pos)              /*!< PPB NVIC_IPR19: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR19_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR19: PRI_2 Position          */\r
+#define PPB_NVIC_IPR19_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_2_Pos)              /*!< PPB NVIC_IPR19: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR19_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR19: PRI_3 Position          */\r
+#define PPB_NVIC_IPR19_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR19_PRI_3_Pos)              /*!< PPB NVIC_IPR19: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR20  ------------------------------- */\r
+#define PPB_NVIC_IPR20_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR20: PRI_0 Position          */\r
+#define PPB_NVIC_IPR20_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_0_Pos)              /*!< PPB NVIC_IPR20: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR20_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR20: PRI_1 Position          */\r
+#define PPB_NVIC_IPR20_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_1_Pos)              /*!< PPB NVIC_IPR20: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR20_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR20: PRI_2 Position          */\r
+#define PPB_NVIC_IPR20_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_2_Pos)              /*!< PPB NVIC_IPR20: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR20_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR20: PRI_3 Position          */\r
+#define PPB_NVIC_IPR20_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR20_PRI_3_Pos)              /*!< PPB NVIC_IPR20: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR21  ------------------------------- */\r
+#define PPB_NVIC_IPR21_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR21: PRI_0 Position          */\r
+#define PPB_NVIC_IPR21_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_0_Pos)              /*!< PPB NVIC_IPR21: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR21_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR21: PRI_1 Position          */\r
+#define PPB_NVIC_IPR21_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_1_Pos)              /*!< PPB NVIC_IPR21: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR21_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR21: PRI_2 Position          */\r
+#define PPB_NVIC_IPR21_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_2_Pos)              /*!< PPB NVIC_IPR21: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR21_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR21: PRI_3 Position          */\r
+#define PPB_NVIC_IPR21_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR21_PRI_3_Pos)              /*!< PPB NVIC_IPR21: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR22  ------------------------------- */\r
+#define PPB_NVIC_IPR22_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR22: PRI_0 Position          */\r
+#define PPB_NVIC_IPR22_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_0_Pos)              /*!< PPB NVIC_IPR22: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR22_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR22: PRI_1 Position          */\r
+#define PPB_NVIC_IPR22_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_1_Pos)              /*!< PPB NVIC_IPR22: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR22_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR22: PRI_2 Position          */\r
+#define PPB_NVIC_IPR22_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_2_Pos)              /*!< PPB NVIC_IPR22: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR22_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR22: PRI_3 Position          */\r
+#define PPB_NVIC_IPR22_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR22_PRI_3_Pos)              /*!< PPB NVIC_IPR22: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR23  ------------------------------- */\r
+#define PPB_NVIC_IPR23_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR23: PRI_0 Position          */\r
+#define PPB_NVIC_IPR23_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_0_Pos)              /*!< PPB NVIC_IPR23: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR23_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR23: PRI_1 Position          */\r
+#define PPB_NVIC_IPR23_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_1_Pos)              /*!< PPB NVIC_IPR23: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR23_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR23: PRI_2 Position          */\r
+#define PPB_NVIC_IPR23_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_2_Pos)              /*!< PPB NVIC_IPR23: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR23_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR23: PRI_3 Position          */\r
+#define PPB_NVIC_IPR23_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR23_PRI_3_Pos)              /*!< PPB NVIC_IPR23: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR24  ------------------------------- */\r
+#define PPB_NVIC_IPR24_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR24: PRI_0 Position          */\r
+#define PPB_NVIC_IPR24_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_0_Pos)              /*!< PPB NVIC_IPR24: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR24_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR24: PRI_1 Position          */\r
+#define PPB_NVIC_IPR24_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_1_Pos)              /*!< PPB NVIC_IPR24: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR24_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR24: PRI_2 Position          */\r
+#define PPB_NVIC_IPR24_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_2_Pos)              /*!< PPB NVIC_IPR24: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR24_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR24: PRI_3 Position          */\r
+#define PPB_NVIC_IPR24_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR24_PRI_3_Pos)              /*!< PPB NVIC_IPR24: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR25  ------------------------------- */\r
+#define PPB_NVIC_IPR25_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR25: PRI_0 Position          */\r
+#define PPB_NVIC_IPR25_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_0_Pos)              /*!< PPB NVIC_IPR25: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR25_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR25: PRI_1 Position          */\r
+#define PPB_NVIC_IPR25_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_1_Pos)              /*!< PPB NVIC_IPR25: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR25_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR25: PRI_2 Position          */\r
+#define PPB_NVIC_IPR25_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_2_Pos)              /*!< PPB NVIC_IPR25: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR25_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR25: PRI_3 Position          */\r
+#define PPB_NVIC_IPR25_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR25_PRI_3_Pos)              /*!< PPB NVIC_IPR25: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR26  ------------------------------- */\r
+#define PPB_NVIC_IPR26_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR26: PRI_0 Position          */\r
+#define PPB_NVIC_IPR26_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_0_Pos)              /*!< PPB NVIC_IPR26: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR26_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR26: PRI_1 Position          */\r
+#define PPB_NVIC_IPR26_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_1_Pos)              /*!< PPB NVIC_IPR26: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR26_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR26: PRI_2 Position          */\r
+#define PPB_NVIC_IPR26_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_2_Pos)              /*!< PPB NVIC_IPR26: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR26_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR26: PRI_3 Position          */\r
+#define PPB_NVIC_IPR26_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR26_PRI_3_Pos)              /*!< PPB NVIC_IPR26: PRI_3 Mask              */\r
+\r
+/* -------------------------------  PPB_NVIC_IPR27  ------------------------------- */\r
+#define PPB_NVIC_IPR27_PRI_0_Pos              0                                                       /*!< PPB NVIC_IPR27: PRI_0 Position          */\r
+#define PPB_NVIC_IPR27_PRI_0_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_0_Pos)              /*!< PPB NVIC_IPR27: PRI_0 Mask              */\r
+#define PPB_NVIC_IPR27_PRI_1_Pos              8                                                       /*!< PPB NVIC_IPR27: PRI_1 Position          */\r
+#define PPB_NVIC_IPR27_PRI_1_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_1_Pos)              /*!< PPB NVIC_IPR27: PRI_1 Mask              */\r
+#define PPB_NVIC_IPR27_PRI_2_Pos              16                                                      /*!< PPB NVIC_IPR27: PRI_2 Position          */\r
+#define PPB_NVIC_IPR27_PRI_2_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_2_Pos)              /*!< PPB NVIC_IPR27: PRI_2 Mask              */\r
+#define PPB_NVIC_IPR27_PRI_3_Pos              24                                                      /*!< PPB NVIC_IPR27: PRI_3 Position          */\r
+#define PPB_NVIC_IPR27_PRI_3_Msk              (0x000000ffUL << PPB_NVIC_IPR27_PRI_3_Pos)              /*!< PPB NVIC_IPR27: PRI_3 Mask              */\r
+\r
+/* ----------------------------------  PPB_CPUID  --------------------------------- */\r
+#define PPB_CPUID_Revision_Pos                0                                                       /*!< PPB CPUID: Revision Position            */\r
+#define PPB_CPUID_Revision_Msk                (0x0fUL << PPB_CPUID_Revision_Pos)                      /*!< PPB CPUID: Revision Mask                */\r
+#define PPB_CPUID_PartNo_Pos                  4                                                       /*!< PPB CPUID: PartNo Position              */\r
+#define PPB_CPUID_PartNo_Msk                  (0x00000fffUL << PPB_CPUID_PartNo_Pos)                  /*!< PPB CPUID: PartNo Mask                  */\r
+#define PPB_CPUID_Constant_Pos                16                                                      /*!< PPB CPUID: Constant Position            */\r
+#define PPB_CPUID_Constant_Msk                (0x0fUL << PPB_CPUID_Constant_Pos)                      /*!< PPB CPUID: Constant Mask                */\r
+#define PPB_CPUID_Variant_Pos                 20                                                      /*!< PPB CPUID: Variant Position             */\r
+#define PPB_CPUID_Variant_Msk                 (0x0fUL << PPB_CPUID_Variant_Pos)                       /*!< PPB CPUID: Variant Mask                 */\r
+#define PPB_CPUID_Implementer_Pos             24                                                      /*!< PPB CPUID: Implementer Position         */\r
+#define PPB_CPUID_Implementer_Msk             (0x000000ffUL << PPB_CPUID_Implementer_Pos)             /*!< PPB CPUID: Implementer Mask             */\r
+\r
+/* ----------------------------------  PPB_ICSR  ---------------------------------- */\r
+#define PPB_ICSR_VECTACTIVE_Pos               0                                                       /*!< PPB ICSR: VECTACTIVE Position           */\r
+#define PPB_ICSR_VECTACTIVE_Msk               (0x000001ffUL << PPB_ICSR_VECTACTIVE_Pos)               /*!< PPB ICSR: VECTACTIVE Mask               */\r
+#define PPB_ICSR_RETTOBASE_Pos                11                                                      /*!< PPB ICSR: RETTOBASE Position            */\r
+#define PPB_ICSR_RETTOBASE_Msk                (0x01UL << PPB_ICSR_RETTOBASE_Pos)                      /*!< PPB ICSR: RETTOBASE Mask                */\r
+#define PPB_ICSR_VECTPENDING_Pos              12                                                      /*!< PPB ICSR: VECTPENDING Position          */\r
+#define PPB_ICSR_VECTPENDING_Msk              (0x3fUL << PPB_ICSR_VECTPENDING_Pos)                    /*!< PPB ICSR: VECTPENDING Mask              */\r
+#define PPB_ICSR_ISRPENDING_Pos               22                                                      /*!< PPB ICSR: ISRPENDING Position           */\r
+#define PPB_ICSR_ISRPENDING_Msk               (0x01UL << PPB_ICSR_ISRPENDING_Pos)                     /*!< PPB ICSR: ISRPENDING Mask               */\r
+#define PPB_ICSR_Res_Pos                      23                                                      /*!< PPB ICSR: Res Position                  */\r
+#define PPB_ICSR_Res_Msk                      (0x01UL << PPB_ICSR_Res_Pos)                            /*!< PPB ICSR: Res Mask                      */\r
+#define PPB_ICSR_PENDSTCLR_Pos                25                                                      /*!< PPB ICSR: PENDSTCLR Position            */\r
+#define PPB_ICSR_PENDSTCLR_Msk                (0x01UL << PPB_ICSR_PENDSTCLR_Pos)                      /*!< PPB ICSR: PENDSTCLR Mask                */\r
+#define PPB_ICSR_PENDSTSET_Pos                26                                                      /*!< PPB ICSR: PENDSTSET Position            */\r
+#define PPB_ICSR_PENDSTSET_Msk                (0x01UL << PPB_ICSR_PENDSTSET_Pos)                      /*!< PPB ICSR: PENDSTSET Mask                */\r
+#define PPB_ICSR_PENDSVCLR_Pos                27                                                      /*!< PPB ICSR: PENDSVCLR Position            */\r
+#define PPB_ICSR_PENDSVCLR_Msk                (0x01UL << PPB_ICSR_PENDSVCLR_Pos)                      /*!< PPB ICSR: PENDSVCLR Mask                */\r
+#define PPB_ICSR_PENDSVSET_Pos                28                                                      /*!< PPB ICSR: PENDSVSET Position            */\r
+#define PPB_ICSR_PENDSVSET_Msk                (0x01UL << PPB_ICSR_PENDSVSET_Pos)                      /*!< PPB ICSR: PENDSVSET Mask                */\r
+#define PPB_ICSR_NMIPENDSET_Pos               31                                                      /*!< PPB ICSR: NMIPENDSET Position           */\r
+#define PPB_ICSR_NMIPENDSET_Msk               (0x01UL << PPB_ICSR_NMIPENDSET_Pos)                     /*!< PPB ICSR: NMIPENDSET Mask               */\r
+\r
+/* ----------------------------------  PPB_VTOR  ---------------------------------- */\r
+#define PPB_VTOR_TBLOFF_Pos                   10                                                      /*!< PPB VTOR: TBLOFF Position               */\r
+#define PPB_VTOR_TBLOFF_Msk                   (0x003fffffUL << PPB_VTOR_TBLOFF_Pos)                   /*!< PPB VTOR: TBLOFF Mask                   */\r
+\r
+/* ----------------------------------  PPB_AIRCR  --------------------------------- */\r
+#define PPB_AIRCR_VECTRESET_Pos               0                                                       /*!< PPB AIRCR: VECTRESET Position           */\r
+#define PPB_AIRCR_VECTRESET_Msk               (0x01UL << PPB_AIRCR_VECTRESET_Pos)                     /*!< PPB AIRCR: VECTRESET Mask               */\r
+#define PPB_AIRCR_VECTCLRACTIVE_Pos           1                                                       /*!< PPB AIRCR: VECTCLRACTIVE Position       */\r
+#define PPB_AIRCR_VECTCLRACTIVE_Msk           (0x01UL << PPB_AIRCR_VECTCLRACTIVE_Pos)                 /*!< PPB AIRCR: VECTCLRACTIVE Mask           */\r
+#define PPB_AIRCR_SYSRESETREQ_Pos             2                                                       /*!< PPB AIRCR: SYSRESETREQ Position         */\r
+#define PPB_AIRCR_SYSRESETREQ_Msk             (0x01UL << PPB_AIRCR_SYSRESETREQ_Pos)                   /*!< PPB AIRCR: SYSRESETREQ Mask             */\r
+#define PPB_AIRCR_PRIGROUP_Pos                8                                                       /*!< PPB AIRCR: PRIGROUP Position            */\r
+#define PPB_AIRCR_PRIGROUP_Msk                (0x07UL << PPB_AIRCR_PRIGROUP_Pos)                      /*!< PPB AIRCR: PRIGROUP Mask                */\r
+#define PPB_AIRCR_ENDIANNESS_Pos              15                                                      /*!< PPB AIRCR: ENDIANNESS Position          */\r
+#define PPB_AIRCR_ENDIANNESS_Msk              (0x01UL << PPB_AIRCR_ENDIANNESS_Pos)                    /*!< PPB AIRCR: ENDIANNESS Mask              */\r
+#define PPB_AIRCR_VECTKEY_Pos                 16                                                      /*!< PPB AIRCR: VECTKEY Position             */\r
+#define PPB_AIRCR_VECTKEY_Msk                 (0x0000ffffUL << PPB_AIRCR_VECTKEY_Pos)                 /*!< PPB AIRCR: VECTKEY Mask                 */\r
+\r
+/* -----------------------------------  PPB_SCR  ---------------------------------- */\r
+#define PPB_SCR_SLEEPONEXIT_Pos               1                                                       /*!< PPB SCR: SLEEPONEXIT Position           */\r
+#define PPB_SCR_SLEEPONEXIT_Msk               (0x01UL << PPB_SCR_SLEEPONEXIT_Pos)                     /*!< PPB SCR: SLEEPONEXIT Mask               */\r
+#define PPB_SCR_SLEEPDEEP_Pos                 2                                                       /*!< PPB SCR: SLEEPDEEP Position             */\r
+#define PPB_SCR_SLEEPDEEP_Msk                 (0x01UL << PPB_SCR_SLEEPDEEP_Pos)                       /*!< PPB SCR: SLEEPDEEP Mask                 */\r
+#define PPB_SCR_SEVONPEND_Pos                 4                                                       /*!< PPB SCR: SEVONPEND Position             */\r
+#define PPB_SCR_SEVONPEND_Msk                 (0x01UL << PPB_SCR_SEVONPEND_Pos)                       /*!< PPB SCR: SEVONPEND Mask                 */\r
+\r
+/* -----------------------------------  PPB_CCR  ---------------------------------- */\r
+#define PPB_CCR_NONBASETHRDENA_Pos            0                                                       /*!< PPB CCR: NONBASETHRDENA Position        */\r
+#define PPB_CCR_NONBASETHRDENA_Msk            (0x01UL << PPB_CCR_NONBASETHRDENA_Pos)                  /*!< PPB CCR: NONBASETHRDENA Mask            */\r
+#define PPB_CCR_USERSETMPEND_Pos              1                                                       /*!< PPB CCR: USERSETMPEND Position          */\r
+#define PPB_CCR_USERSETMPEND_Msk              (0x01UL << PPB_CCR_USERSETMPEND_Pos)                    /*!< PPB CCR: USERSETMPEND Mask              */\r
+#define PPB_CCR_UNALIGN_TRP_Pos               3                                                       /*!< PPB CCR: UNALIGN_TRP Position           */\r
+#define PPB_CCR_UNALIGN_TRP_Msk               (0x01UL << PPB_CCR_UNALIGN_TRP_Pos)                     /*!< PPB CCR: UNALIGN_TRP Mask               */\r
+#define PPB_CCR_DIV_0_TRP_Pos                 4                                                       /*!< PPB CCR: DIV_0_TRP Position             */\r
+#define PPB_CCR_DIV_0_TRP_Msk                 (0x01UL << PPB_CCR_DIV_0_TRP_Pos)                       /*!< PPB CCR: DIV_0_TRP Mask                 */\r
+#define PPB_CCR_BFHFNMIGN_Pos                 8                                                       /*!< PPB CCR: BFHFNMIGN Position             */\r
+#define PPB_CCR_BFHFNMIGN_Msk                 (0x01UL << PPB_CCR_BFHFNMIGN_Pos)                       /*!< PPB CCR: BFHFNMIGN Mask                 */\r
+#define PPB_CCR_STKALIGN_Pos                  9                                                       /*!< PPB CCR: STKALIGN Position              */\r
+#define PPB_CCR_STKALIGN_Msk                  (0x01UL << PPB_CCR_STKALIGN_Pos)                        /*!< PPB CCR: STKALIGN Mask                  */\r
+\r
+/* ----------------------------------  PPB_SHPR1  --------------------------------- */\r
+#define PPB_SHPR1_PRI_4_Pos                   0                                                       /*!< PPB SHPR1: PRI_4 Position               */\r
+#define PPB_SHPR1_PRI_4_Msk                   (0x000000ffUL << PPB_SHPR1_PRI_4_Pos)                   /*!< PPB SHPR1: PRI_4 Mask                   */\r
+#define PPB_SHPR1_PRI_5_Pos                   8                                                       /*!< PPB SHPR1: PRI_5 Position               */\r
+#define PPB_SHPR1_PRI_5_Msk                   (0x000000ffUL << PPB_SHPR1_PRI_5_Pos)                   /*!< PPB SHPR1: PRI_5 Mask                   */\r
+#define PPB_SHPR1_PRI_6_Pos                   16                                                      /*!< PPB SHPR1: PRI_6 Position               */\r
+#define PPB_SHPR1_PRI_6_Msk                   (0x000000ffUL << PPB_SHPR1_PRI_6_Pos)                   /*!< PPB SHPR1: PRI_6 Mask                   */\r
+\r
+/* ----------------------------------  PPB_SHPR2  --------------------------------- */\r
+#define PPB_SHPR2_PRI_11_Pos                  24                                                      /*!< PPB SHPR2: PRI_11 Position              */\r
+#define PPB_SHPR2_PRI_11_Msk                  (0x000000ffUL << PPB_SHPR2_PRI_11_Pos)                  /*!< PPB SHPR2: PRI_11 Mask                  */\r
+\r
+/* ----------------------------------  PPB_SHPR3  --------------------------------- */\r
+#define PPB_SHPR3_PRI_14_Pos                  16                                                      /*!< PPB SHPR3: PRI_14 Position              */\r
+#define PPB_SHPR3_PRI_14_Msk                  (0x000000ffUL << PPB_SHPR3_PRI_14_Pos)                  /*!< PPB SHPR3: PRI_14 Mask                  */\r
+#define PPB_SHPR3_PRI_15_Pos                  24                                                      /*!< PPB SHPR3: PRI_15 Position              */\r
+#define PPB_SHPR3_PRI_15_Msk                  (0x000000ffUL << PPB_SHPR3_PRI_15_Pos)                  /*!< PPB SHPR3: PRI_15 Mask                  */\r
+\r
+/* ----------------------------------  PPB_SHCSR  --------------------------------- */\r
+#define PPB_SHCSR_MEMFAULTACT_Pos             0                                                       /*!< PPB SHCSR: MEMFAULTACT Position         */\r
+#define PPB_SHCSR_MEMFAULTACT_Msk             (0x01UL << PPB_SHCSR_MEMFAULTACT_Pos)                   /*!< PPB SHCSR: MEMFAULTACT Mask             */\r
+#define PPB_SHCSR_BUSFAULTACT_Pos             1                                                       /*!< PPB SHCSR: BUSFAULTACT Position         */\r
+#define PPB_SHCSR_BUSFAULTACT_Msk             (0x01UL << PPB_SHCSR_BUSFAULTACT_Pos)                   /*!< PPB SHCSR: BUSFAULTACT Mask             */\r
+#define PPB_SHCSR_USGFAULTACT_Pos             3                                                       /*!< PPB SHCSR: USGFAULTACT Position         */\r
+#define PPB_SHCSR_USGFAULTACT_Msk             (0x01UL << PPB_SHCSR_USGFAULTACT_Pos)                   /*!< PPB SHCSR: USGFAULTACT Mask             */\r
+#define PPB_SHCSR_SVCALLACT_Pos               7                                                       /*!< PPB SHCSR: SVCALLACT Position           */\r
+#define PPB_SHCSR_SVCALLACT_Msk               (0x01UL << PPB_SHCSR_SVCALLACT_Pos)                     /*!< PPB SHCSR: SVCALLACT Mask               */\r
+#define PPB_SHCSR_MONITORACT_Pos              8                                                       /*!< PPB SHCSR: MONITORACT Position          */\r
+#define PPB_SHCSR_MONITORACT_Msk              (0x01UL << PPB_SHCSR_MONITORACT_Pos)                    /*!< PPB SHCSR: MONITORACT Mask              */\r
+#define PPB_SHCSR_PENDSVACT_Pos               10                                                      /*!< PPB SHCSR: PENDSVACT Position           */\r
+#define PPB_SHCSR_PENDSVACT_Msk               (0x01UL << PPB_SHCSR_PENDSVACT_Pos)                     /*!< PPB SHCSR: PENDSVACT Mask               */\r
+#define PPB_SHCSR_SYSTICKACT_Pos              11                                                      /*!< PPB SHCSR: SYSTICKACT Position          */\r
+#define PPB_SHCSR_SYSTICKACT_Msk              (0x01UL << PPB_SHCSR_SYSTICKACT_Pos)                    /*!< PPB SHCSR: SYSTICKACT Mask              */\r
+#define PPB_SHCSR_USGFAULTPENDED_Pos          12                                                      /*!< PPB SHCSR: USGFAULTPENDED Position      */\r
+#define PPB_SHCSR_USGFAULTPENDED_Msk          (0x01UL << PPB_SHCSR_USGFAULTPENDED_Pos)                /*!< PPB SHCSR: USGFAULTPENDED Mask          */\r
+#define PPB_SHCSR_MEMFAULTPENDED_Pos          13                                                      /*!< PPB SHCSR: MEMFAULTPENDED Position      */\r
+#define PPB_SHCSR_MEMFAULTPENDED_Msk          (0x01UL << PPB_SHCSR_MEMFAULTPENDED_Pos)                /*!< PPB SHCSR: MEMFAULTPENDED Mask          */\r
+#define PPB_SHCSR_BUSFAULTPENDED_Pos          14                                                      /*!< PPB SHCSR: BUSFAULTPENDED Position      */\r
+#define PPB_SHCSR_BUSFAULTPENDED_Msk          (0x01UL << PPB_SHCSR_BUSFAULTPENDED_Pos)                /*!< PPB SHCSR: BUSFAULTPENDED Mask          */\r
+#define PPB_SHCSR_SVCALLPENDED_Pos            15                                                      /*!< PPB SHCSR: SVCALLPENDED Position        */\r
+#define PPB_SHCSR_SVCALLPENDED_Msk            (0x01UL << PPB_SHCSR_SVCALLPENDED_Pos)                  /*!< PPB SHCSR: SVCALLPENDED Mask            */\r
+#define PPB_SHCSR_MEMFAULTENA_Pos             16                                                      /*!< PPB SHCSR: MEMFAULTENA Position         */\r
+#define PPB_SHCSR_MEMFAULTENA_Msk             (0x01UL << PPB_SHCSR_MEMFAULTENA_Pos)                   /*!< PPB SHCSR: MEMFAULTENA Mask             */\r
+#define PPB_SHCSR_BUSFAULTENA_Pos             17                                                      /*!< PPB SHCSR: BUSFAULTENA Position         */\r
+#define PPB_SHCSR_BUSFAULTENA_Msk             (0x01UL << PPB_SHCSR_BUSFAULTENA_Pos)                   /*!< PPB SHCSR: BUSFAULTENA Mask             */\r
+#define PPB_SHCSR_USGFAULTENA_Pos             18                                                      /*!< PPB SHCSR: USGFAULTENA Position         */\r
+#define PPB_SHCSR_USGFAULTENA_Msk             (0x01UL << PPB_SHCSR_USGFAULTENA_Pos)                   /*!< PPB SHCSR: USGFAULTENA Mask             */\r
+\r
+/* ----------------------------------  PPB_CFSR  ---------------------------------- */\r
+#define PPB_CFSR_IACCVIOL_Pos                 0                                                       /*!< PPB CFSR: IACCVIOL Position             */\r
+#define PPB_CFSR_IACCVIOL_Msk                 (0x01UL << PPB_CFSR_IACCVIOL_Pos)                       /*!< PPB CFSR: IACCVIOL Mask                 */\r
+#define PPB_CFSR_DACCVIOL_Pos                 1                                                       /*!< PPB CFSR: DACCVIOL Position             */\r
+#define PPB_CFSR_DACCVIOL_Msk                 (0x01UL << PPB_CFSR_DACCVIOL_Pos)                       /*!< PPB CFSR: DACCVIOL Mask                 */\r
+#define PPB_CFSR_MUNSTKERR_Pos                3                                                       /*!< PPB CFSR: MUNSTKERR Position            */\r
+#define PPB_CFSR_MUNSTKERR_Msk                (0x01UL << PPB_CFSR_MUNSTKERR_Pos)                      /*!< PPB CFSR: MUNSTKERR Mask                */\r
+#define PPB_CFSR_MSTKERR_Pos                  4                                                       /*!< PPB CFSR: MSTKERR Position              */\r
+#define PPB_CFSR_MSTKERR_Msk                  (0x01UL << PPB_CFSR_MSTKERR_Pos)                        /*!< PPB CFSR: MSTKERR Mask                  */\r
+#define PPB_CFSR_MLSPERR_Pos                  5                                                       /*!< PPB CFSR: MLSPERR Position              */\r
+#define PPB_CFSR_MLSPERR_Msk                  (0x01UL << PPB_CFSR_MLSPERR_Pos)                        /*!< PPB CFSR: MLSPERR Mask                  */\r
+#define PPB_CFSR_MMARVALID_Pos                7                                                       /*!< PPB CFSR: MMARVALID Position            */\r
+#define PPB_CFSR_MMARVALID_Msk                (0x01UL << PPB_CFSR_MMARVALID_Pos)                      /*!< PPB CFSR: MMARVALID Mask                */\r
+#define PPB_CFSR_IBUSERR_Pos                  8                                                       /*!< PPB CFSR: IBUSERR Position              */\r
+#define PPB_CFSR_IBUSERR_Msk                  (0x01UL << PPB_CFSR_IBUSERR_Pos)                        /*!< PPB CFSR: IBUSERR Mask                  */\r
+#define PPB_CFSR_PRECISERR_Pos                9                                                       /*!< PPB CFSR: PRECISERR Position            */\r
+#define PPB_CFSR_PRECISERR_Msk                (0x01UL << PPB_CFSR_PRECISERR_Pos)                      /*!< PPB CFSR: PRECISERR Mask                */\r
+#define PPB_CFSR_IMPRECISERR_Pos              10                                                      /*!< PPB CFSR: IMPRECISERR Position          */\r
+#define PPB_CFSR_IMPRECISERR_Msk              (0x01UL << PPB_CFSR_IMPRECISERR_Pos)                    /*!< PPB CFSR: IMPRECISERR Mask              */\r
+#define PPB_CFSR_UNSTKERR_Pos                 11                                                      /*!< PPB CFSR: UNSTKERR Position             */\r
+#define PPB_CFSR_UNSTKERR_Msk                 (0x01UL << PPB_CFSR_UNSTKERR_Pos)                       /*!< PPB CFSR: UNSTKERR Mask                 */\r
+#define PPB_CFSR_STKERR_Pos                   12                                                      /*!< PPB CFSR: STKERR Position               */\r
+#define PPB_CFSR_STKERR_Msk                   (0x01UL << PPB_CFSR_STKERR_Pos)                         /*!< PPB CFSR: STKERR Mask                   */\r
+#define PPB_CFSR_LSPERR_Pos                   13                                                      /*!< PPB CFSR: LSPERR Position               */\r
+#define PPB_CFSR_LSPERR_Msk                   (0x01UL << PPB_CFSR_LSPERR_Pos)                         /*!< PPB CFSR: LSPERR Mask                   */\r
+#define PPB_CFSR_BFARVALID_Pos                15                                                      /*!< PPB CFSR: BFARVALID Position            */\r
+#define PPB_CFSR_BFARVALID_Msk                (0x01UL << PPB_CFSR_BFARVALID_Pos)                      /*!< PPB CFSR: BFARVALID Mask                */\r
+#define PPB_CFSR_UNDEFINSTR_Pos               16                                                      /*!< PPB CFSR: UNDEFINSTR Position           */\r
+#define PPB_CFSR_UNDEFINSTR_Msk               (0x01UL << PPB_CFSR_UNDEFINSTR_Pos)                     /*!< PPB CFSR: UNDEFINSTR Mask               */\r
+#define PPB_CFSR_INVSTATE_Pos                 17                                                      /*!< PPB CFSR: INVSTATE Position             */\r
+#define PPB_CFSR_INVSTATE_Msk                 (0x01UL << PPB_CFSR_INVSTATE_Pos)                       /*!< PPB CFSR: INVSTATE Mask                 */\r
+#define PPB_CFSR_INVPC_Pos                    18                                                      /*!< PPB CFSR: INVPC Position                */\r
+#define PPB_CFSR_INVPC_Msk                    (0x01UL << PPB_CFSR_INVPC_Pos)                          /*!< PPB CFSR: INVPC Mask                    */\r
+#define PPB_CFSR_NOCP_Pos                     19                                                      /*!< PPB CFSR: NOCP Position                 */\r
+#define PPB_CFSR_NOCP_Msk                     (0x01UL << PPB_CFSR_NOCP_Pos)                           /*!< PPB CFSR: NOCP Mask                     */\r
+#define PPB_CFSR_UNALIGNED_Pos                24                                                      /*!< PPB CFSR: UNALIGNED Position            */\r
+#define PPB_CFSR_UNALIGNED_Msk                (0x01UL << PPB_CFSR_UNALIGNED_Pos)                      /*!< PPB CFSR: UNALIGNED Mask                */\r
+#define PPB_CFSR_DIVBYZERO_Pos                25                                                      /*!< PPB CFSR: DIVBYZERO Position            */\r
+#define PPB_CFSR_DIVBYZERO_Msk                (0x01UL << PPB_CFSR_DIVBYZERO_Pos)                      /*!< PPB CFSR: DIVBYZERO Mask                */\r
+\r
+/* ----------------------------------  PPB_HFSR  ---------------------------------- */\r
+#define PPB_HFSR_VECTTBL_Pos                  1                                                       /*!< PPB HFSR: VECTTBL Position              */\r
+#define PPB_HFSR_VECTTBL_Msk                  (0x01UL << PPB_HFSR_VECTTBL_Pos)                        /*!< PPB HFSR: VECTTBL Mask                  */\r
+#define PPB_HFSR_FORCED_Pos                   30                                                      /*!< PPB HFSR: FORCED Position               */\r
+#define PPB_HFSR_FORCED_Msk                   (0x01UL << PPB_HFSR_FORCED_Pos)                         /*!< PPB HFSR: FORCED Mask                   */\r
+#define PPB_HFSR_DEBUGEVT_Pos                 31                                                      /*!< PPB HFSR: DEBUGEVT Position             */\r
+#define PPB_HFSR_DEBUGEVT_Msk                 (0x01UL << PPB_HFSR_DEBUGEVT_Pos)                       /*!< PPB HFSR: DEBUGEVT Mask                 */\r
+\r
+/* ----------------------------------  PPB_MMFAR  --------------------------------- */\r
+#define PPB_MMFAR_ADDRESS_Pos                 0                                                       /*!< PPB MMFAR: ADDRESS Position             */\r
+#define PPB_MMFAR_ADDRESS_Msk                 (0xffffffffUL << PPB_MMFAR_ADDRESS_Pos)                 /*!< PPB MMFAR: ADDRESS Mask                 */\r
+\r
+/* ----------------------------------  PPB_BFAR  ---------------------------------- */\r
+#define PPB_BFAR_ADDRESS_Pos                  0                                                       /*!< PPB BFAR: ADDRESS Position              */\r
+#define PPB_BFAR_ADDRESS_Msk                  (0xffffffffUL << PPB_BFAR_ADDRESS_Pos)                  /*!< PPB BFAR: ADDRESS Mask                  */\r
+\r
+/* ----------------------------------  PPB_AFSR  ---------------------------------- */\r
+#define PPB_AFSR_VALUE_Pos                    0                                                       /*!< PPB AFSR: VALUE Position                */\r
+#define PPB_AFSR_VALUE_Msk                    (0xffffffffUL << PPB_AFSR_VALUE_Pos)                    /*!< PPB AFSR: VALUE Mask                    */\r
+\r
+/* ----------------------------------  PPB_CPACR  --------------------------------- */\r
+#define PPB_CPACR_CP10_Pos                    20                                                      /*!< PPB CPACR: CP10 Position                */\r
+#define PPB_CPACR_CP10_Msk                    (0x03UL << PPB_CPACR_CP10_Pos)                          /*!< PPB CPACR: CP10 Mask                    */\r
+#define PPB_CPACR_CP11_Pos                    22                                                      /*!< PPB CPACR: CP11 Position                */\r
+#define PPB_CPACR_CP11_Msk                    (0x03UL << PPB_CPACR_CP11_Pos)                          /*!< PPB CPACR: CP11 Mask                    */\r
+\r
+/* --------------------------------  PPB_MPU_TYPE  -------------------------------- */\r
+#define PPB_MPU_TYPE_SEPARATE_Pos             0                                                       /*!< PPB MPU_TYPE: SEPARATE Position         */\r
+#define PPB_MPU_TYPE_SEPARATE_Msk             (0x01UL << PPB_MPU_TYPE_SEPARATE_Pos)                   /*!< PPB MPU_TYPE: SEPARATE Mask             */\r
+#define PPB_MPU_TYPE_DREGION_Pos              8                                                       /*!< PPB MPU_TYPE: DREGION Position          */\r
+#define PPB_MPU_TYPE_DREGION_Msk              (0x000000ffUL << PPB_MPU_TYPE_DREGION_Pos)              /*!< PPB MPU_TYPE: DREGION Mask              */\r
+#define PPB_MPU_TYPE_IREGION_Pos              16                                                      /*!< PPB MPU_TYPE: IREGION Position          */\r
+#define PPB_MPU_TYPE_IREGION_Msk              (0x000000ffUL << PPB_MPU_TYPE_IREGION_Pos)              /*!< PPB MPU_TYPE: IREGION Mask              */\r
+\r
+/* --------------------------------  PPB_MPU_CTRL  -------------------------------- */\r
+#define PPB_MPU_CTRL_ENABLE_Pos               0                                                       /*!< PPB MPU_CTRL: ENABLE Position           */\r
+#define PPB_MPU_CTRL_ENABLE_Msk               (0x01UL << PPB_MPU_CTRL_ENABLE_Pos)                     /*!< PPB MPU_CTRL: ENABLE Mask               */\r
+#define PPB_MPU_CTRL_HFNMIENA_Pos             1                                                       /*!< PPB MPU_CTRL: HFNMIENA Position         */\r
+#define PPB_MPU_CTRL_HFNMIENA_Msk             (0x01UL << PPB_MPU_CTRL_HFNMIENA_Pos)                   /*!< PPB MPU_CTRL: HFNMIENA Mask             */\r
+#define PPB_MPU_CTRL_PRIVDEFENA_Pos           2                                                       /*!< PPB MPU_CTRL: PRIVDEFENA Position       */\r
+#define PPB_MPU_CTRL_PRIVDEFENA_Msk           (0x01UL << PPB_MPU_CTRL_PRIVDEFENA_Pos)                 /*!< PPB MPU_CTRL: PRIVDEFENA Mask           */\r
+\r
+/* ---------------------------------  PPB_MPU_RNR  -------------------------------- */\r
+#define PPB_MPU_RNR_REGION_Pos                0                                                       /*!< PPB MPU_RNR: REGION Position            */\r
+#define PPB_MPU_RNR_REGION_Msk                (0x000000ffUL << PPB_MPU_RNR_REGION_Pos)                /*!< PPB MPU_RNR: REGION Mask                */\r
+\r
+/* --------------------------------  PPB_MPU_RBAR  -------------------------------- */\r
+#define PPB_MPU_RBAR_REGION_Pos               0                                                       /*!< PPB MPU_RBAR: REGION Position           */\r
+#define PPB_MPU_RBAR_REGION_Msk               (0x0fUL << PPB_MPU_RBAR_REGION_Pos)                     /*!< PPB MPU_RBAR: REGION Mask               */\r
+#define PPB_MPU_RBAR_VALID_Pos                4                                                       /*!< PPB MPU_RBAR: VALID Position            */\r
+#define PPB_MPU_RBAR_VALID_Msk                (0x01UL << PPB_MPU_RBAR_VALID_Pos)                      /*!< PPB MPU_RBAR: VALID Mask                */\r
+#define PPB_MPU_RBAR_ADDR_Pos                 9                                                       /*!< PPB MPU_RBAR: ADDR Position             */\r
+#define PPB_MPU_RBAR_ADDR_Msk                 (0x007fffffUL << PPB_MPU_RBAR_ADDR_Pos)                 /*!< PPB MPU_RBAR: ADDR Mask                 */\r
+\r
+/* --------------------------------  PPB_MPU_RASR  -------------------------------- */\r
+#define PPB_MPU_RASR_ENABLE_Pos               0                                                       /*!< PPB MPU_RASR: ENABLE Position           */\r
+#define PPB_MPU_RASR_ENABLE_Msk               (0x01UL << PPB_MPU_RASR_ENABLE_Pos)                     /*!< PPB MPU_RASR: ENABLE Mask               */\r
+#define PPB_MPU_RASR_SIZE_Pos                 1                                                       /*!< PPB MPU_RASR: SIZE Position             */\r
+#define PPB_MPU_RASR_SIZE_Msk                 (0x1fUL << PPB_MPU_RASR_SIZE_Pos)                       /*!< PPB MPU_RASR: SIZE Mask                 */\r
+#define PPB_MPU_RASR_SRD_Pos                  8                                                       /*!< PPB MPU_RASR: SRD Position              */\r
+#define PPB_MPU_RASR_SRD_Msk                  (0x000000ffUL << PPB_MPU_RASR_SRD_Pos)                  /*!< PPB MPU_RASR: SRD Mask                  */\r
+#define PPB_MPU_RASR_B_Pos                    16                                                      /*!< PPB MPU_RASR: B Position                */\r
+#define PPB_MPU_RASR_B_Msk                    (0x01UL << PPB_MPU_RASR_B_Pos)                          /*!< PPB MPU_RASR: B Mask                    */\r
+#define PPB_MPU_RASR_C_Pos                    17                                                      /*!< PPB MPU_RASR: C Position                */\r
+#define PPB_MPU_RASR_C_Msk                    (0x01UL << PPB_MPU_RASR_C_Pos)                          /*!< PPB MPU_RASR: C Mask                    */\r
+#define PPB_MPU_RASR_S_Pos                    18                                                      /*!< PPB MPU_RASR: S Position                */\r
+#define PPB_MPU_RASR_S_Msk                    (0x01UL << PPB_MPU_RASR_S_Pos)                          /*!< PPB MPU_RASR: S Mask                    */\r
+#define PPB_MPU_RASR_TEX_Pos                  19                                                      /*!< PPB MPU_RASR: TEX Position              */\r
+#define PPB_MPU_RASR_TEX_Msk                  (0x07UL << PPB_MPU_RASR_TEX_Pos)                        /*!< PPB MPU_RASR: TEX Mask                  */\r
+#define PPB_MPU_RASR_AP_Pos                   24                                                      /*!< PPB MPU_RASR: AP Position               */\r
+#define PPB_MPU_RASR_AP_Msk                   (0x07UL << PPB_MPU_RASR_AP_Pos)                         /*!< PPB MPU_RASR: AP Mask                   */\r
+#define PPB_MPU_RASR_XN_Pos                   28                                                      /*!< PPB MPU_RASR: XN Position               */\r
+#define PPB_MPU_RASR_XN_Msk                   (0x01UL << PPB_MPU_RASR_XN_Pos)                         /*!< PPB MPU_RASR: XN Mask                   */\r
+\r
+/* -------------------------------  PPB_MPU_RBAR_A1  ------------------------------ */\r
+#define PPB_MPU_RBAR_A1_REGION_Pos            0                                                       /*!< PPB MPU_RBAR_A1: REGION Position        */\r
+#define PPB_MPU_RBAR_A1_REGION_Msk            (0x0fUL << PPB_MPU_RBAR_A1_REGION_Pos)                  /*!< PPB MPU_RBAR_A1: REGION Mask            */\r
+#define PPB_MPU_RBAR_A1_VALID_Pos             4                                                       /*!< PPB MPU_RBAR_A1: VALID Position         */\r
+#define PPB_MPU_RBAR_A1_VALID_Msk             (0x01UL << PPB_MPU_RBAR_A1_VALID_Pos)                   /*!< PPB MPU_RBAR_A1: VALID Mask             */\r
+#define PPB_MPU_RBAR_A1_ADDR_Pos              9                                                       /*!< PPB MPU_RBAR_A1: ADDR Position          */\r
+#define PPB_MPU_RBAR_A1_ADDR_Msk              (0x007fffffUL << PPB_MPU_RBAR_A1_ADDR_Pos)              /*!< PPB MPU_RBAR_A1: ADDR Mask              */\r
+\r
+/* -------------------------------  PPB_MPU_RASR_A1  ------------------------------ */\r
+#define PPB_MPU_RASR_A1_ENABLE_Pos            0                                                       /*!< PPB MPU_RASR_A1: ENABLE Position        */\r
+#define PPB_MPU_RASR_A1_ENABLE_Msk            (0x01UL << PPB_MPU_RASR_A1_ENABLE_Pos)                  /*!< PPB MPU_RASR_A1: ENABLE Mask            */\r
+#define PPB_MPU_RASR_A1_SIZE_Pos              1                                                       /*!< PPB MPU_RASR_A1: SIZE Position          */\r
+#define PPB_MPU_RASR_A1_SIZE_Msk              (0x1fUL << PPB_MPU_RASR_A1_SIZE_Pos)                    /*!< PPB MPU_RASR_A1: SIZE Mask              */\r
+#define PPB_MPU_RASR_A1_SRD_Pos               8                                                       /*!< PPB MPU_RASR_A1: SRD Position           */\r
+#define PPB_MPU_RASR_A1_SRD_Msk               (0x000000ffUL << PPB_MPU_RASR_A1_SRD_Pos)               /*!< PPB MPU_RASR_A1: SRD Mask               */\r
+#define PPB_MPU_RASR_A1_B_Pos                 16                                                      /*!< PPB MPU_RASR_A1: B Position             */\r
+#define PPB_MPU_RASR_A1_B_Msk                 (0x01UL << PPB_MPU_RASR_A1_B_Pos)                       /*!< PPB MPU_RASR_A1: B Mask                 */\r
+#define PPB_MPU_RASR_A1_C_Pos                 17                                                      /*!< PPB MPU_RASR_A1: C Position             */\r
+#define PPB_MPU_RASR_A1_C_Msk                 (0x01UL << PPB_MPU_RASR_A1_C_Pos)                       /*!< PPB MPU_RASR_A1: C Mask                 */\r
+#define PPB_MPU_RASR_A1_S_Pos                 18                                                      /*!< PPB MPU_RASR_A1: S Position             */\r
+#define PPB_MPU_RASR_A1_S_Msk                 (0x01UL << PPB_MPU_RASR_A1_S_Pos)                       /*!< PPB MPU_RASR_A1: S Mask                 */\r
+#define PPB_MPU_RASR_A1_TEX_Pos               19                                                      /*!< PPB MPU_RASR_A1: TEX Position           */\r
+#define PPB_MPU_RASR_A1_TEX_Msk               (0x07UL << PPB_MPU_RASR_A1_TEX_Pos)                     /*!< PPB MPU_RASR_A1: TEX Mask               */\r
+#define PPB_MPU_RASR_A1_AP_Pos                24                                                      /*!< PPB MPU_RASR_A1: AP Position            */\r
+#define PPB_MPU_RASR_A1_AP_Msk                (0x07UL << PPB_MPU_RASR_A1_AP_Pos)                      /*!< PPB MPU_RASR_A1: AP Mask                */\r
+#define PPB_MPU_RASR_A1_XN_Pos                28                                                      /*!< PPB MPU_RASR_A1: XN Position            */\r
+#define PPB_MPU_RASR_A1_XN_Msk                (0x01UL << PPB_MPU_RASR_A1_XN_Pos)                      /*!< PPB MPU_RASR_A1: XN Mask                */\r
+\r
+/* -------------------------------  PPB_MPU_RBAR_A2  ------------------------------ */\r
+#define PPB_MPU_RBAR_A2_REGION_Pos            0                                                       /*!< PPB MPU_RBAR_A2: REGION Position        */\r
+#define PPB_MPU_RBAR_A2_REGION_Msk            (0x0fUL << PPB_MPU_RBAR_A2_REGION_Pos)                  /*!< PPB MPU_RBAR_A2: REGION Mask            */\r
+#define PPB_MPU_RBAR_A2_VALID_Pos             4                                                       /*!< PPB MPU_RBAR_A2: VALID Position         */\r
+#define PPB_MPU_RBAR_A2_VALID_Msk             (0x01UL << PPB_MPU_RBAR_A2_VALID_Pos)                   /*!< PPB MPU_RBAR_A2: VALID Mask             */\r
+#define PPB_MPU_RBAR_A2_ADDR_Pos              9                                                       /*!< PPB MPU_RBAR_A2: ADDR Position          */\r
+#define PPB_MPU_RBAR_A2_ADDR_Msk              (0x007fffffUL << PPB_MPU_RBAR_A2_ADDR_Pos)              /*!< PPB MPU_RBAR_A2: ADDR Mask              */\r
+\r
+/* -------------------------------  PPB_MPU_RASR_A2  ------------------------------ */\r
+#define PPB_MPU_RASR_A2_ENABLE_Pos            0                                                       /*!< PPB MPU_RASR_A2: ENABLE Position        */\r
+#define PPB_MPU_RASR_A2_ENABLE_Msk            (0x01UL << PPB_MPU_RASR_A2_ENABLE_Pos)                  /*!< PPB MPU_RASR_A2: ENABLE Mask            */\r
+#define PPB_MPU_RASR_A2_SIZE_Pos              1                                                       /*!< PPB MPU_RASR_A2: SIZE Position          */\r
+#define PPB_MPU_RASR_A2_SIZE_Msk              (0x1fUL << PPB_MPU_RASR_A2_SIZE_Pos)                    /*!< PPB MPU_RASR_A2: SIZE Mask              */\r
+#define PPB_MPU_RASR_A2_SRD_Pos               8                                                       /*!< PPB MPU_RASR_A2: SRD Position           */\r
+#define PPB_MPU_RASR_A2_SRD_Msk               (0x000000ffUL << PPB_MPU_RASR_A2_SRD_Pos)               /*!< PPB MPU_RASR_A2: SRD Mask               */\r
+#define PPB_MPU_RASR_A2_B_Pos                 16                                                      /*!< PPB MPU_RASR_A2: B Position             */\r
+#define PPB_MPU_RASR_A2_B_Msk                 (0x01UL << PPB_MPU_RASR_A2_B_Pos)                       /*!< PPB MPU_RASR_A2: B Mask                 */\r
+#define PPB_MPU_RASR_A2_C_Pos                 17                                                      /*!< PPB MPU_RASR_A2: C Position             */\r
+#define PPB_MPU_RASR_A2_C_Msk                 (0x01UL << PPB_MPU_RASR_A2_C_Pos)                       /*!< PPB MPU_RASR_A2: C Mask                 */\r
+#define PPB_MPU_RASR_A2_S_Pos                 18                                                      /*!< PPB MPU_RASR_A2: S Position             */\r
+#define PPB_MPU_RASR_A2_S_Msk                 (0x01UL << PPB_MPU_RASR_A2_S_Pos)                       /*!< PPB MPU_RASR_A2: S Mask                 */\r
+#define PPB_MPU_RASR_A2_TEX_Pos               19                                                      /*!< PPB MPU_RASR_A2: TEX Position           */\r
+#define PPB_MPU_RASR_A2_TEX_Msk               (0x07UL << PPB_MPU_RASR_A2_TEX_Pos)                     /*!< PPB MPU_RASR_A2: TEX Mask               */\r
+#define PPB_MPU_RASR_A2_AP_Pos                24                                                      /*!< PPB MPU_RASR_A2: AP Position            */\r
+#define PPB_MPU_RASR_A2_AP_Msk                (0x07UL << PPB_MPU_RASR_A2_AP_Pos)                      /*!< PPB MPU_RASR_A2: AP Mask                */\r
+#define PPB_MPU_RASR_A2_XN_Pos                28                                                      /*!< PPB MPU_RASR_A2: XN Position            */\r
+#define PPB_MPU_RASR_A2_XN_Msk                (0x01UL << PPB_MPU_RASR_A2_XN_Pos)                      /*!< PPB MPU_RASR_A2: XN Mask                */\r
+\r
+/* -------------------------------  PPB_MPU_RBAR_A3  ------------------------------ */\r
+#define PPB_MPU_RBAR_A3_REGION_Pos            0                                                       /*!< PPB MPU_RBAR_A3: REGION Position        */\r
+#define PPB_MPU_RBAR_A3_REGION_Msk            (0x0fUL << PPB_MPU_RBAR_A3_REGION_Pos)                  /*!< PPB MPU_RBAR_A3: REGION Mask            */\r
+#define PPB_MPU_RBAR_A3_VALID_Pos             4                                                       /*!< PPB MPU_RBAR_A3: VALID Position         */\r
+#define PPB_MPU_RBAR_A3_VALID_Msk             (0x01UL << PPB_MPU_RBAR_A3_VALID_Pos)                   /*!< PPB MPU_RBAR_A3: VALID Mask             */\r
+#define PPB_MPU_RBAR_A3_ADDR_Pos              9                                                       /*!< PPB MPU_RBAR_A3: ADDR Position          */\r
+#define PPB_MPU_RBAR_A3_ADDR_Msk              (0x007fffffUL << PPB_MPU_RBAR_A3_ADDR_Pos)              /*!< PPB MPU_RBAR_A3: ADDR Mask              */\r
+\r
+/* -------------------------------  PPB_MPU_RASR_A3  ------------------------------ */\r
+#define PPB_MPU_RASR_A3_ENABLE_Pos            0                                                       /*!< PPB MPU_RASR_A3: ENABLE Position        */\r
+#define PPB_MPU_RASR_A3_ENABLE_Msk            (0x01UL << PPB_MPU_RASR_A3_ENABLE_Pos)                  /*!< PPB MPU_RASR_A3: ENABLE Mask            */\r
+#define PPB_MPU_RASR_A3_SIZE_Pos              1                                                       /*!< PPB MPU_RASR_A3: SIZE Position          */\r
+#define PPB_MPU_RASR_A3_SIZE_Msk              (0x1fUL << PPB_MPU_RASR_A3_SIZE_Pos)                    /*!< PPB MPU_RASR_A3: SIZE Mask              */\r
+#define PPB_MPU_RASR_A3_SRD_Pos               8                                                       /*!< PPB MPU_RASR_A3: SRD Position           */\r
+#define PPB_MPU_RASR_A3_SRD_Msk               (0x000000ffUL << PPB_MPU_RASR_A3_SRD_Pos)               /*!< PPB MPU_RASR_A3: SRD Mask               */\r
+#define PPB_MPU_RASR_A3_B_Pos                 16                                                      /*!< PPB MPU_RASR_A3: B Position             */\r
+#define PPB_MPU_RASR_A3_B_Msk                 (0x01UL << PPB_MPU_RASR_A3_B_Pos)                       /*!< PPB MPU_RASR_A3: B Mask                 */\r
+#define PPB_MPU_RASR_A3_C_Pos                 17                                                      /*!< PPB MPU_RASR_A3: C Position             */\r
+#define PPB_MPU_RASR_A3_C_Msk                 (0x01UL << PPB_MPU_RASR_A3_C_Pos)                       /*!< PPB MPU_RASR_A3: C Mask                 */\r
+#define PPB_MPU_RASR_A3_S_Pos                 18                                                      /*!< PPB MPU_RASR_A3: S Position             */\r
+#define PPB_MPU_RASR_A3_S_Msk                 (0x01UL << PPB_MPU_RASR_A3_S_Pos)                       /*!< PPB MPU_RASR_A3: S Mask                 */\r
+#define PPB_MPU_RASR_A3_TEX_Pos               19                                                      /*!< PPB MPU_RASR_A3: TEX Position           */\r
+#define PPB_MPU_RASR_A3_TEX_Msk               (0x07UL << PPB_MPU_RASR_A3_TEX_Pos)                     /*!< PPB MPU_RASR_A3: TEX Mask               */\r
+#define PPB_MPU_RASR_A3_AP_Pos                24                                                      /*!< PPB MPU_RASR_A3: AP Position            */\r
+#define PPB_MPU_RASR_A3_AP_Msk                (0x07UL << PPB_MPU_RASR_A3_AP_Pos)                      /*!< PPB MPU_RASR_A3: AP Mask                */\r
+#define PPB_MPU_RASR_A3_XN_Pos                28                                                      /*!< PPB MPU_RASR_A3: XN Position            */\r
+#define PPB_MPU_RASR_A3_XN_Msk                (0x01UL << PPB_MPU_RASR_A3_XN_Pos)                      /*!< PPB MPU_RASR_A3: XN Mask                */\r
+\r
+/* ----------------------------------  PPB_STIR  ---------------------------------- */\r
+#define PPB_STIR_INTID_Pos                    0                                                       /*!< PPB STIR: INTID Position                */\r
+#define PPB_STIR_INTID_Msk                    (0x000001ffUL << PPB_STIR_INTID_Pos)                    /*!< PPB STIR: INTID Mask                    */\r
+\r
+/* ----------------------------------  PPB_FPCCR  --------------------------------- */\r
+#define PPB_FPCCR_LSPACT_Pos                  0                                                       /*!< PPB FPCCR: LSPACT Position              */\r
+#define PPB_FPCCR_LSPACT_Msk                  (0x01UL << PPB_FPCCR_LSPACT_Pos)                        /*!< PPB FPCCR: LSPACT Mask                  */\r
+#define PPB_FPCCR_USER_Pos                    1                                                       /*!< PPB FPCCR: USER Position                */\r
+#define PPB_FPCCR_USER_Msk                    (0x01UL << PPB_FPCCR_USER_Pos)                          /*!< PPB FPCCR: USER Mask                    */\r
+#define PPB_FPCCR_THREAD_Pos                  3                                                       /*!< PPB FPCCR: THREAD Position              */\r
+#define PPB_FPCCR_THREAD_Msk                  (0x01UL << PPB_FPCCR_THREAD_Pos)                        /*!< PPB FPCCR: THREAD Mask                  */\r
+#define PPB_FPCCR_HFRDY_Pos                   4                                                       /*!< PPB FPCCR: HFRDY Position               */\r
+#define PPB_FPCCR_HFRDY_Msk                   (0x01UL << PPB_FPCCR_HFRDY_Pos)                         /*!< PPB FPCCR: HFRDY Mask                   */\r
+#define PPB_FPCCR_MMRDY_Pos                   5                                                       /*!< PPB FPCCR: MMRDY Position               */\r
+#define PPB_FPCCR_MMRDY_Msk                   (0x01UL << PPB_FPCCR_MMRDY_Pos)                         /*!< PPB FPCCR: MMRDY Mask                   */\r
+#define PPB_FPCCR_BFRDY_Pos                   6                                                       /*!< PPB FPCCR: BFRDY Position               */\r
+#define PPB_FPCCR_BFRDY_Msk                   (0x01UL << PPB_FPCCR_BFRDY_Pos)                         /*!< PPB FPCCR: BFRDY Mask                   */\r
+#define PPB_FPCCR_MONRDY_Pos                  8                                                       /*!< PPB FPCCR: MONRDY Position              */\r
+#define PPB_FPCCR_MONRDY_Msk                  (0x01UL << PPB_FPCCR_MONRDY_Pos)                        /*!< PPB FPCCR: MONRDY Mask                  */\r
+#define PPB_FPCCR_LSPEN_Pos                   30                                                      /*!< PPB FPCCR: LSPEN Position               */\r
+#define PPB_FPCCR_LSPEN_Msk                   (0x01UL << PPB_FPCCR_LSPEN_Pos)                         /*!< PPB FPCCR: LSPEN Mask                   */\r
+#define PPB_FPCCR_ASPEN_Pos                   31                                                      /*!< PPB FPCCR: ASPEN Position               */\r
+#define PPB_FPCCR_ASPEN_Msk                   (0x01UL << PPB_FPCCR_ASPEN_Pos)                         /*!< PPB FPCCR: ASPEN Mask                   */\r
+\r
+/* ----------------------------------  PPB_FPCAR  --------------------------------- */\r
+#define PPB_FPCAR_ADDRESS_Pos                 3                                                       /*!< PPB FPCAR: ADDRESS Position             */\r
+#define PPB_FPCAR_ADDRESS_Msk                 (0x1fffffffUL << PPB_FPCAR_ADDRESS_Pos)                 /*!< PPB FPCAR: ADDRESS Mask                 */\r
+\r
+/* ---------------------------------  PPB_FPDSCR  --------------------------------- */\r
+#define PPB_FPDSCR_RMode_Pos                  22                                                      /*!< PPB FPDSCR: RMode Position              */\r
+#define PPB_FPDSCR_RMode_Msk                  (0x03UL << PPB_FPDSCR_RMode_Pos)                        /*!< PPB FPDSCR: RMode Mask                  */\r
+#define PPB_FPDSCR_FZ_Pos                     24                                                      /*!< PPB FPDSCR: FZ Position                 */\r
+#define PPB_FPDSCR_FZ_Msk                     (0x01UL << PPB_FPDSCR_FZ_Pos)                           /*!< PPB FPDSCR: FZ Mask                     */\r
+#define PPB_FPDSCR_DN_Pos                     25                                                      /*!< PPB FPDSCR: DN Position                 */\r
+#define PPB_FPDSCR_DN_Msk                     (0x01UL << PPB_FPDSCR_DN_Pos)                           /*!< PPB FPDSCR: DN Mask                     */\r
+#define PPB_FPDSCR_AHP_Pos                    26                                                      /*!< PPB FPDSCR: AHP Position                */\r
+#define PPB_FPDSCR_AHP_Msk                    (0x01UL << PPB_FPDSCR_AHP_Pos)                          /*!< PPB FPDSCR: AHP Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'DLR' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  DLR_OVRSTAT  -------------------------------- */\r
+#define DLR_OVRSTAT_LN0_Pos                   0                                                       /*!< DLR OVRSTAT: LN0 Position               */\r
+#define DLR_OVRSTAT_LN0_Msk                   (0x01UL << DLR_OVRSTAT_LN0_Pos)                         /*!< DLR OVRSTAT: LN0 Mask                   */\r
+#define DLR_OVRSTAT_LN1_Pos                   1                                                       /*!< DLR OVRSTAT: LN1 Position               */\r
+#define DLR_OVRSTAT_LN1_Msk                   (0x01UL << DLR_OVRSTAT_LN1_Pos)                         /*!< DLR OVRSTAT: LN1 Mask                   */\r
+#define DLR_OVRSTAT_LN2_Pos                   2                                                       /*!< DLR OVRSTAT: LN2 Position               */\r
+#define DLR_OVRSTAT_LN2_Msk                   (0x01UL << DLR_OVRSTAT_LN2_Pos)                         /*!< DLR OVRSTAT: LN2 Mask                   */\r
+#define DLR_OVRSTAT_LN3_Pos                   3                                                       /*!< DLR OVRSTAT: LN3 Position               */\r
+#define DLR_OVRSTAT_LN3_Msk                   (0x01UL << DLR_OVRSTAT_LN3_Pos)                         /*!< DLR OVRSTAT: LN3 Mask                   */\r
+#define DLR_OVRSTAT_LN4_Pos                   4                                                       /*!< DLR OVRSTAT: LN4 Position               */\r
+#define DLR_OVRSTAT_LN4_Msk                   (0x01UL << DLR_OVRSTAT_LN4_Pos)                         /*!< DLR OVRSTAT: LN4 Mask                   */\r
+#define DLR_OVRSTAT_LN5_Pos                   5                                                       /*!< DLR OVRSTAT: LN5 Position               */\r
+#define DLR_OVRSTAT_LN5_Msk                   (0x01UL << DLR_OVRSTAT_LN5_Pos)                         /*!< DLR OVRSTAT: LN5 Mask                   */\r
+#define DLR_OVRSTAT_LN6_Pos                   6                                                       /*!< DLR OVRSTAT: LN6 Position               */\r
+#define DLR_OVRSTAT_LN6_Msk                   (0x01UL << DLR_OVRSTAT_LN6_Pos)                         /*!< DLR OVRSTAT: LN6 Mask                   */\r
+#define DLR_OVRSTAT_LN7_Pos                   7                                                       /*!< DLR OVRSTAT: LN7 Position               */\r
+#define DLR_OVRSTAT_LN7_Msk                   (0x01UL << DLR_OVRSTAT_LN7_Pos)                         /*!< DLR OVRSTAT: LN7 Mask                   */\r
+#define DLR_OVRSTAT_LN8_Pos                   8                                                       /*!< DLR OVRSTAT: LN8 Position               */\r
+#define DLR_OVRSTAT_LN8_Msk                   (0x01UL << DLR_OVRSTAT_LN8_Pos)                         /*!< DLR OVRSTAT: LN8 Mask                   */\r
+#define DLR_OVRSTAT_LN9_Pos                   9                                                       /*!< DLR OVRSTAT: LN9 Position               */\r
+#define DLR_OVRSTAT_LN9_Msk                   (0x01UL << DLR_OVRSTAT_LN9_Pos)                         /*!< DLR OVRSTAT: LN9 Mask                   */\r
+#define DLR_OVRSTAT_LN10_Pos                  10                                                      /*!< DLR OVRSTAT: LN10 Position              */\r
+#define DLR_OVRSTAT_LN10_Msk                  (0x01UL << DLR_OVRSTAT_LN10_Pos)                        /*!< DLR OVRSTAT: LN10 Mask                  */\r
+#define DLR_OVRSTAT_LN11_Pos                  11                                                      /*!< DLR OVRSTAT: LN11 Position              */\r
+#define DLR_OVRSTAT_LN11_Msk                  (0x01UL << DLR_OVRSTAT_LN11_Pos)                        /*!< DLR OVRSTAT: LN11 Mask                  */\r
+\r
+/* ---------------------------------  DLR_OVRCLR  --------------------------------- */\r
+#define DLR_OVRCLR_LN0_Pos                    0                                                       /*!< DLR OVRCLR: LN0 Position                */\r
+#define DLR_OVRCLR_LN0_Msk                    (0x01UL << DLR_OVRCLR_LN0_Pos)                          /*!< DLR OVRCLR: LN0 Mask                    */\r
+#define DLR_OVRCLR_LN1_Pos                    1                                                       /*!< DLR OVRCLR: LN1 Position                */\r
+#define DLR_OVRCLR_LN1_Msk                    (0x01UL << DLR_OVRCLR_LN1_Pos)                          /*!< DLR OVRCLR: LN1 Mask                    */\r
+#define DLR_OVRCLR_LN2_Pos                    2                                                       /*!< DLR OVRCLR: LN2 Position                */\r
+#define DLR_OVRCLR_LN2_Msk                    (0x01UL << DLR_OVRCLR_LN2_Pos)                          /*!< DLR OVRCLR: LN2 Mask                    */\r
+#define DLR_OVRCLR_LN3_Pos                    3                                                       /*!< DLR OVRCLR: LN3 Position                */\r
+#define DLR_OVRCLR_LN3_Msk                    (0x01UL << DLR_OVRCLR_LN3_Pos)                          /*!< DLR OVRCLR: LN3 Mask                    */\r
+#define DLR_OVRCLR_LN4_Pos                    4                                                       /*!< DLR OVRCLR: LN4 Position                */\r
+#define DLR_OVRCLR_LN4_Msk                    (0x01UL << DLR_OVRCLR_LN4_Pos)                          /*!< DLR OVRCLR: LN4 Mask                    */\r
+#define DLR_OVRCLR_LN5_Pos                    5                                                       /*!< DLR OVRCLR: LN5 Position                */\r
+#define DLR_OVRCLR_LN5_Msk                    (0x01UL << DLR_OVRCLR_LN5_Pos)                          /*!< DLR OVRCLR: LN5 Mask                    */\r
+#define DLR_OVRCLR_LN6_Pos                    6                                                       /*!< DLR OVRCLR: LN6 Position                */\r
+#define DLR_OVRCLR_LN6_Msk                    (0x01UL << DLR_OVRCLR_LN6_Pos)                          /*!< DLR OVRCLR: LN6 Mask                    */\r
+#define DLR_OVRCLR_LN7_Pos                    7                                                       /*!< DLR OVRCLR: LN7 Position                */\r
+#define DLR_OVRCLR_LN7_Msk                    (0x01UL << DLR_OVRCLR_LN7_Pos)                          /*!< DLR OVRCLR: LN7 Mask                    */\r
+#define DLR_OVRCLR_LN8_Pos                    8                                                       /*!< DLR OVRCLR: LN8 Position                */\r
+#define DLR_OVRCLR_LN8_Msk                    (0x01UL << DLR_OVRCLR_LN8_Pos)                          /*!< DLR OVRCLR: LN8 Mask                    */\r
+#define DLR_OVRCLR_LN9_Pos                    9                                                       /*!< DLR OVRCLR: LN9 Position                */\r
+#define DLR_OVRCLR_LN9_Msk                    (0x01UL << DLR_OVRCLR_LN9_Pos)                          /*!< DLR OVRCLR: LN9 Mask                    */\r
+#define DLR_OVRCLR_LN10_Pos                   10                                                      /*!< DLR OVRCLR: LN10 Position               */\r
+#define DLR_OVRCLR_LN10_Msk                   (0x01UL << DLR_OVRCLR_LN10_Pos)                         /*!< DLR OVRCLR: LN10 Mask                   */\r
+#define DLR_OVRCLR_LN11_Pos                   11                                                      /*!< DLR OVRCLR: LN11 Position               */\r
+#define DLR_OVRCLR_LN11_Msk                   (0x01UL << DLR_OVRCLR_LN11_Pos)                         /*!< DLR OVRCLR: LN11 Mask                   */\r
+\r
+/* ---------------------------------  DLR_SRSEL0  --------------------------------- */\r
+#define DLR_SRSEL0_RS0_Pos                    0                                                       /*!< DLR SRSEL0: RS0 Position                */\r
+#define DLR_SRSEL0_RS0_Msk                    (0x0fUL << DLR_SRSEL0_RS0_Pos)                          /*!< DLR SRSEL0: RS0 Mask                    */\r
+#define DLR_SRSEL0_RS1_Pos                    4                                                       /*!< DLR SRSEL0: RS1 Position                */\r
+#define DLR_SRSEL0_RS1_Msk                    (0x0fUL << DLR_SRSEL0_RS1_Pos)                          /*!< DLR SRSEL0: RS1 Mask                    */\r
+#define DLR_SRSEL0_RS2_Pos                    8                                                       /*!< DLR SRSEL0: RS2 Position                */\r
+#define DLR_SRSEL0_RS2_Msk                    (0x0fUL << DLR_SRSEL0_RS2_Pos)                          /*!< DLR SRSEL0: RS2 Mask                    */\r
+#define DLR_SRSEL0_RS3_Pos                    12                                                      /*!< DLR SRSEL0: RS3 Position                */\r
+#define DLR_SRSEL0_RS3_Msk                    (0x0fUL << DLR_SRSEL0_RS3_Pos)                          /*!< DLR SRSEL0: RS3 Mask                    */\r
+#define DLR_SRSEL0_RS4_Pos                    16                                                      /*!< DLR SRSEL0: RS4 Position                */\r
+#define DLR_SRSEL0_RS4_Msk                    (0x0fUL << DLR_SRSEL0_RS4_Pos)                          /*!< DLR SRSEL0: RS4 Mask                    */\r
+#define DLR_SRSEL0_RS5_Pos                    20                                                      /*!< DLR SRSEL0: RS5 Position                */\r
+#define DLR_SRSEL0_RS5_Msk                    (0x0fUL << DLR_SRSEL0_RS5_Pos)                          /*!< DLR SRSEL0: RS5 Mask                    */\r
+#define DLR_SRSEL0_RS6_Pos                    24                                                      /*!< DLR SRSEL0: RS6 Position                */\r
+#define DLR_SRSEL0_RS6_Msk                    (0x0fUL << DLR_SRSEL0_RS6_Pos)                          /*!< DLR SRSEL0: RS6 Mask                    */\r
+#define DLR_SRSEL0_RS7_Pos                    28                                                      /*!< DLR SRSEL0: RS7 Position                */\r
+#define DLR_SRSEL0_RS7_Msk                    (0x0fUL << DLR_SRSEL0_RS7_Pos)                          /*!< DLR SRSEL0: RS7 Mask                    */\r
+\r
+/* ---------------------------------  DLR_SRSEL1  --------------------------------- */\r
+#define DLR_SRSEL1_RS8_Pos                    0                                                       /*!< DLR SRSEL1: RS8 Position                */\r
+#define DLR_SRSEL1_RS8_Msk                    (0x0fUL << DLR_SRSEL1_RS8_Pos)                          /*!< DLR SRSEL1: RS8 Mask                    */\r
+#define DLR_SRSEL1_RS9_Pos                    4                                                       /*!< DLR SRSEL1: RS9 Position                */\r
+#define DLR_SRSEL1_RS9_Msk                    (0x0fUL << DLR_SRSEL1_RS9_Pos)                          /*!< DLR SRSEL1: RS9 Mask                    */\r
+#define DLR_SRSEL1_RS10_Pos                   8                                                       /*!< DLR SRSEL1: RS10 Position               */\r
+#define DLR_SRSEL1_RS10_Msk                   (0x0fUL << DLR_SRSEL1_RS10_Pos)                         /*!< DLR SRSEL1: RS10 Mask                   */\r
+#define DLR_SRSEL1_RS11_Pos                   12                                                      /*!< DLR SRSEL1: RS11 Position               */\r
+#define DLR_SRSEL1_RS11_Msk                   (0x0fUL << DLR_SRSEL1_RS11_Pos)                         /*!< DLR SRSEL1: RS11 Mask                   */\r
+\r
+/* ----------------------------------  DLR_LNEN  ---------------------------------- */\r
+#define DLR_LNEN_LN0_Pos                      0                                                       /*!< DLR LNEN: LN0 Position                  */\r
+#define DLR_LNEN_LN0_Msk                      (0x01UL << DLR_LNEN_LN0_Pos)                            /*!< DLR LNEN: LN0 Mask                      */\r
+#define DLR_LNEN_LN1_Pos                      1                                                       /*!< DLR LNEN: LN1 Position                  */\r
+#define DLR_LNEN_LN1_Msk                      (0x01UL << DLR_LNEN_LN1_Pos)                            /*!< DLR LNEN: LN1 Mask                      */\r
+#define DLR_LNEN_LN2_Pos                      2                                                       /*!< DLR LNEN: LN2 Position                  */\r
+#define DLR_LNEN_LN2_Msk                      (0x01UL << DLR_LNEN_LN2_Pos)                            /*!< DLR LNEN: LN2 Mask                      */\r
+#define DLR_LNEN_LN3_Pos                      3                                                       /*!< DLR LNEN: LN3 Position                  */\r
+#define DLR_LNEN_LN3_Msk                      (0x01UL << DLR_LNEN_LN3_Pos)                            /*!< DLR LNEN: LN3 Mask                      */\r
+#define DLR_LNEN_LN4_Pos                      4                                                       /*!< DLR LNEN: LN4 Position                  */\r
+#define DLR_LNEN_LN4_Msk                      (0x01UL << DLR_LNEN_LN4_Pos)                            /*!< DLR LNEN: LN4 Mask                      */\r
+#define DLR_LNEN_LN5_Pos                      5                                                       /*!< DLR LNEN: LN5 Position                  */\r
+#define DLR_LNEN_LN5_Msk                      (0x01UL << DLR_LNEN_LN5_Pos)                            /*!< DLR LNEN: LN5 Mask                      */\r
+#define DLR_LNEN_LN6_Pos                      6                                                       /*!< DLR LNEN: LN6 Position                  */\r
+#define DLR_LNEN_LN6_Msk                      (0x01UL << DLR_LNEN_LN6_Pos)                            /*!< DLR LNEN: LN6 Mask                      */\r
+#define DLR_LNEN_LN7_Pos                      7                                                       /*!< DLR LNEN: LN7 Position                  */\r
+#define DLR_LNEN_LN7_Msk                      (0x01UL << DLR_LNEN_LN7_Pos)                            /*!< DLR LNEN: LN7 Mask                      */\r
+#define DLR_LNEN_LN8_Pos                      8                                                       /*!< DLR LNEN: LN8 Position                  */\r
+#define DLR_LNEN_LN8_Msk                      (0x01UL << DLR_LNEN_LN8_Pos)                            /*!< DLR LNEN: LN8 Mask                      */\r
+#define DLR_LNEN_LN9_Pos                      9                                                       /*!< DLR LNEN: LN9 Position                  */\r
+#define DLR_LNEN_LN9_Msk                      (0x01UL << DLR_LNEN_LN9_Pos)                            /*!< DLR LNEN: LN9 Mask                      */\r
+#define DLR_LNEN_LN10_Pos                     10                                                      /*!< DLR LNEN: LN10 Position                 */\r
+#define DLR_LNEN_LN10_Msk                     (0x01UL << DLR_LNEN_LN10_Pos)                           /*!< DLR LNEN: LN10 Mask                     */\r
+#define DLR_LNEN_LN11_Pos                     11                                                      /*!< DLR LNEN: LN11 Position                 */\r
+#define DLR_LNEN_LN11_Msk                     (0x01UL << DLR_LNEN_LN11_Pos)                           /*!< DLR LNEN: LN11 Mask                     */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'ERU' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  ERU_EXISEL  --------------------------------- */\r
+#define ERU_EXISEL_EXS0A_Pos                  0                                                       /*!< ERU EXISEL: EXS0A Position              */\r
+#define ERU_EXISEL_EXS0A_Msk                  (0x03UL << ERU_EXISEL_EXS0A_Pos)                        /*!< ERU EXISEL: EXS0A Mask                  */\r
+#define ERU_EXISEL_EXS0B_Pos                  2                                                       /*!< ERU EXISEL: EXS0B Position              */\r
+#define ERU_EXISEL_EXS0B_Msk                  (0x03UL << ERU_EXISEL_EXS0B_Pos)                        /*!< ERU EXISEL: EXS0B Mask                  */\r
+#define ERU_EXISEL_EXS1A_Pos                  4                                                       /*!< ERU EXISEL: EXS1A Position              */\r
+#define ERU_EXISEL_EXS1A_Msk                  (0x03UL << ERU_EXISEL_EXS1A_Pos)                        /*!< ERU EXISEL: EXS1A Mask                  */\r
+#define ERU_EXISEL_EXS1B_Pos                  6                                                       /*!< ERU EXISEL: EXS1B Position              */\r
+#define ERU_EXISEL_EXS1B_Msk                  (0x03UL << ERU_EXISEL_EXS1B_Pos)                        /*!< ERU EXISEL: EXS1B Mask                  */\r
+#define ERU_EXISEL_EXS2A_Pos                  8                                                       /*!< ERU EXISEL: EXS2A Position              */\r
+#define ERU_EXISEL_EXS2A_Msk                  (0x03UL << ERU_EXISEL_EXS2A_Pos)                        /*!< ERU EXISEL: EXS2A Mask                  */\r
+#define ERU_EXISEL_EXS2B_Pos                  10                                                      /*!< ERU EXISEL: EXS2B Position              */\r
+#define ERU_EXISEL_EXS2B_Msk                  (0x03UL << ERU_EXISEL_EXS2B_Pos)                        /*!< ERU EXISEL: EXS2B Mask                  */\r
+#define ERU_EXISEL_EXS3A_Pos                  12                                                      /*!< ERU EXISEL: EXS3A Position              */\r
+#define ERU_EXISEL_EXS3A_Msk                  (0x03UL << ERU_EXISEL_EXS3A_Pos)                        /*!< ERU EXISEL: EXS3A Mask                  */\r
+#define ERU_EXISEL_EXS3B_Pos                  14                                                      /*!< ERU EXISEL: EXS3B Position              */\r
+#define ERU_EXISEL_EXS3B_Msk                  (0x03UL << ERU_EXISEL_EXS3B_Pos)                        /*!< ERU EXISEL: EXS3B Mask                  */\r
+\r
+/* ---------------------------------  ERU_EXICON  --------------------------------- */\r
+#define ERU_EXICON_PE_Pos                     0                                                       /*!< ERU EXICON: PE Position                 */\r
+#define ERU_EXICON_PE_Msk                     (0x01UL << ERU_EXICON_PE_Pos)                           /*!< ERU EXICON: PE Mask                     */\r
+#define ERU_EXICON_LD_Pos                     1                                                       /*!< ERU EXICON: LD Position                 */\r
+#define ERU_EXICON_LD_Msk                     (0x01UL << ERU_EXICON_LD_Pos)                           /*!< ERU EXICON: LD Mask                     */\r
+#define ERU_EXICON_RE_Pos                     2                                                       /*!< ERU EXICON: RE Position                 */\r
+#define ERU_EXICON_RE_Msk                     (0x01UL << ERU_EXICON_RE_Pos)                           /*!< ERU EXICON: RE Mask                     */\r
+#define ERU_EXICON_FE_Pos                     3                                                       /*!< ERU EXICON: FE Position                 */\r
+#define ERU_EXICON_FE_Msk                     (0x01UL << ERU_EXICON_FE_Pos)                           /*!< ERU EXICON: FE Mask                     */\r
+#define ERU_EXICON_OCS_Pos                    4                                                       /*!< ERU EXICON: OCS Position                */\r
+#define ERU_EXICON_OCS_Msk                    (0x07UL << ERU_EXICON_OCS_Pos)                          /*!< ERU EXICON: OCS Mask                    */\r
+#define ERU_EXICON_FL_Pos                     7                                                       /*!< ERU EXICON: FL Position                 */\r
+#define ERU_EXICON_FL_Msk                     (0x01UL << ERU_EXICON_FL_Pos)                           /*!< ERU EXICON: FL Mask                     */\r
+#define ERU_EXICON_SS_Pos                     8                                                       /*!< ERU EXICON: SS Position                 */\r
+#define ERU_EXICON_SS_Msk                     (0x03UL << ERU_EXICON_SS_Pos)                           /*!< ERU EXICON: SS Mask                     */\r
+#define ERU_EXICON_NA_Pos                     10                                                      /*!< ERU EXICON: NA Position                 */\r
+#define ERU_EXICON_NA_Msk                     (0x01UL << ERU_EXICON_NA_Pos)                           /*!< ERU EXICON: NA Mask                     */\r
+#define ERU_EXICON_NB_Pos                     11                                                      /*!< ERU EXICON: NB Position                 */\r
+#define ERU_EXICON_NB_Msk                     (0x01UL << ERU_EXICON_NB_Pos)                           /*!< ERU EXICON: NB Mask                     */\r
+\r
+/* ---------------------------------  ERU_EXOCON  --------------------------------- */\r
+#define ERU_EXOCON_ISS_Pos                    0                                                       /*!< ERU EXOCON: ISS Position                */\r
+#define ERU_EXOCON_ISS_Msk                    (0x03UL << ERU_EXOCON_ISS_Pos)                          /*!< ERU EXOCON: ISS Mask                    */\r
+#define ERU_EXOCON_GEEN_Pos                   2                                                       /*!< ERU EXOCON: GEEN Position               */\r
+#define ERU_EXOCON_GEEN_Msk                   (0x01UL << ERU_EXOCON_GEEN_Pos)                         /*!< ERU EXOCON: GEEN Mask                   */\r
+#define ERU_EXOCON_PDR_Pos                    3                                                       /*!< ERU EXOCON: PDR Position                */\r
+#define ERU_EXOCON_PDR_Msk                    (0x01UL << ERU_EXOCON_PDR_Pos)                          /*!< ERU EXOCON: PDR Mask                    */\r
+#define ERU_EXOCON_GP_Pos                     4                                                       /*!< ERU EXOCON: GP Position                 */\r
+#define ERU_EXOCON_GP_Msk                     (0x03UL << ERU_EXOCON_GP_Pos)                           /*!< ERU EXOCON: GP Mask                     */\r
+#define ERU_EXOCON_IPEN0_Pos                  12                                                      /*!< ERU EXOCON: IPEN0 Position              */\r
+#define ERU_EXOCON_IPEN0_Msk                  (0x01UL << ERU_EXOCON_IPEN0_Pos)                        /*!< ERU EXOCON: IPEN0 Mask                  */\r
+#define ERU_EXOCON_IPEN1_Pos                  13                                                      /*!< ERU EXOCON: IPEN1 Position              */\r
+#define ERU_EXOCON_IPEN1_Msk                  (0x01UL << ERU_EXOCON_IPEN1_Pos)                        /*!< ERU EXOCON: IPEN1 Mask                  */\r
+#define ERU_EXOCON_IPEN2_Pos                  14                                                      /*!< ERU EXOCON: IPEN2 Position              */\r
+#define ERU_EXOCON_IPEN2_Msk                  (0x01UL << ERU_EXOCON_IPEN2_Pos)                        /*!< ERU EXOCON: IPEN2 Mask                  */\r
+#define ERU_EXOCON_IPEN3_Pos                  15                                                      /*!< ERU EXOCON: IPEN3 Position              */\r
+#define ERU_EXOCON_IPEN3_Msk                  (0x01UL << ERU_EXOCON_IPEN3_Pos)                        /*!< ERU EXOCON: IPEN3 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'GPDMA0' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  GPDMA0_RAWTFR  ------------------------------- */\r
+#define GPDMA0_RAWTFR_CH0_Pos                 0                                                       /*!< GPDMA0 RAWTFR: CH0 Position             */\r
+#define GPDMA0_RAWTFR_CH0_Msk                 (0x01UL << GPDMA0_RAWTFR_CH0_Pos)                       /*!< GPDMA0 RAWTFR: CH0 Mask                 */\r
+#define GPDMA0_RAWTFR_CH1_Pos                 1                                                       /*!< GPDMA0 RAWTFR: CH1 Position             */\r
+#define GPDMA0_RAWTFR_CH1_Msk                 (0x01UL << GPDMA0_RAWTFR_CH1_Pos)                       /*!< GPDMA0 RAWTFR: CH1 Mask                 */\r
+#define GPDMA0_RAWTFR_CH2_Pos                 2                                                       /*!< GPDMA0 RAWTFR: CH2 Position             */\r
+#define GPDMA0_RAWTFR_CH2_Msk                 (0x01UL << GPDMA0_RAWTFR_CH2_Pos)                       /*!< GPDMA0 RAWTFR: CH2 Mask                 */\r
+#define GPDMA0_RAWTFR_CH3_Pos                 3                                                       /*!< GPDMA0 RAWTFR: CH3 Position             */\r
+#define GPDMA0_RAWTFR_CH3_Msk                 (0x01UL << GPDMA0_RAWTFR_CH3_Pos)                       /*!< GPDMA0 RAWTFR: CH3 Mask                 */\r
+#define GPDMA0_RAWTFR_CH4_Pos                 4                                                       /*!< GPDMA0 RAWTFR: CH4 Position             */\r
+#define GPDMA0_RAWTFR_CH4_Msk                 (0x01UL << GPDMA0_RAWTFR_CH4_Pos)                       /*!< GPDMA0 RAWTFR: CH4 Mask                 */\r
+#define GPDMA0_RAWTFR_CH5_Pos                 5                                                       /*!< GPDMA0 RAWTFR: CH5 Position             */\r
+#define GPDMA0_RAWTFR_CH5_Msk                 (0x01UL << GPDMA0_RAWTFR_CH5_Pos)                       /*!< GPDMA0 RAWTFR: CH5 Mask                 */\r
+#define GPDMA0_RAWTFR_CH6_Pos                 6                                                       /*!< GPDMA0 RAWTFR: CH6 Position             */\r
+#define GPDMA0_RAWTFR_CH6_Msk                 (0x01UL << GPDMA0_RAWTFR_CH6_Pos)                       /*!< GPDMA0 RAWTFR: CH6 Mask                 */\r
+#define GPDMA0_RAWTFR_CH7_Pos                 7                                                       /*!< GPDMA0 RAWTFR: CH7 Position             */\r
+#define GPDMA0_RAWTFR_CH7_Msk                 (0x01UL << GPDMA0_RAWTFR_CH7_Pos)                       /*!< GPDMA0 RAWTFR: CH7 Mask                 */\r
+\r
+/* -------------------------------  GPDMA0_RAWBLOCK  ------------------------------ */\r
+#define GPDMA0_RAWBLOCK_CH0_Pos               0                                                       /*!< GPDMA0 RAWBLOCK: CH0 Position           */\r
+#define GPDMA0_RAWBLOCK_CH0_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH0_Pos)                     /*!< GPDMA0 RAWBLOCK: CH0 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH1_Pos               1                                                       /*!< GPDMA0 RAWBLOCK: CH1 Position           */\r
+#define GPDMA0_RAWBLOCK_CH1_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH1_Pos)                     /*!< GPDMA0 RAWBLOCK: CH1 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH2_Pos               2                                                       /*!< GPDMA0 RAWBLOCK: CH2 Position           */\r
+#define GPDMA0_RAWBLOCK_CH2_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH2_Pos)                     /*!< GPDMA0 RAWBLOCK: CH2 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH3_Pos               3                                                       /*!< GPDMA0 RAWBLOCK: CH3 Position           */\r
+#define GPDMA0_RAWBLOCK_CH3_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH3_Pos)                     /*!< GPDMA0 RAWBLOCK: CH3 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH4_Pos               4                                                       /*!< GPDMA0 RAWBLOCK: CH4 Position           */\r
+#define GPDMA0_RAWBLOCK_CH4_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH4_Pos)                     /*!< GPDMA0 RAWBLOCK: CH4 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH5_Pos               5                                                       /*!< GPDMA0 RAWBLOCK: CH5 Position           */\r
+#define GPDMA0_RAWBLOCK_CH5_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH5_Pos)                     /*!< GPDMA0 RAWBLOCK: CH5 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH6_Pos               6                                                       /*!< GPDMA0 RAWBLOCK: CH6 Position           */\r
+#define GPDMA0_RAWBLOCK_CH6_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH6_Pos)                     /*!< GPDMA0 RAWBLOCK: CH6 Mask               */\r
+#define GPDMA0_RAWBLOCK_CH7_Pos               7                                                       /*!< GPDMA0 RAWBLOCK: CH7 Position           */\r
+#define GPDMA0_RAWBLOCK_CH7_Msk               (0x01UL << GPDMA0_RAWBLOCK_CH7_Pos)                     /*!< GPDMA0 RAWBLOCK: CH7 Mask               */\r
+\r
+/* ------------------------------  GPDMA0_RAWSRCTRAN  ----------------------------- */\r
+#define GPDMA0_RAWSRCTRAN_CH0_Pos             0                                                       /*!< GPDMA0 RAWSRCTRAN: CH0 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH0_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH0_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH0 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH1_Pos             1                                                       /*!< GPDMA0 RAWSRCTRAN: CH1 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH1_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH1_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH1 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH2_Pos             2                                                       /*!< GPDMA0 RAWSRCTRAN: CH2 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH2_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH2_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH2 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH3_Pos             3                                                       /*!< GPDMA0 RAWSRCTRAN: CH3 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH3_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH3_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH3 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH4_Pos             4                                                       /*!< GPDMA0 RAWSRCTRAN: CH4 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH4_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH4_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH4 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH5_Pos             5                                                       /*!< GPDMA0 RAWSRCTRAN: CH5 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH5_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH5_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH5 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH6_Pos             6                                                       /*!< GPDMA0 RAWSRCTRAN: CH6 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH6_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH6_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH6 Mask             */\r
+#define GPDMA0_RAWSRCTRAN_CH7_Pos             7                                                       /*!< GPDMA0 RAWSRCTRAN: CH7 Position         */\r
+#define GPDMA0_RAWSRCTRAN_CH7_Msk             (0x01UL << GPDMA0_RAWSRCTRAN_CH7_Pos)                   /*!< GPDMA0 RAWSRCTRAN: CH7 Mask             */\r
+\r
+/* ------------------------------  GPDMA0_RAWDSTTRAN  ----------------------------- */\r
+#define GPDMA0_RAWDSTTRAN_CH0_Pos             0                                                       /*!< GPDMA0 RAWDSTTRAN: CH0 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH0_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH0_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH0 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH1_Pos             1                                                       /*!< GPDMA0 RAWDSTTRAN: CH1 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH1_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH1_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH1 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH2_Pos             2                                                       /*!< GPDMA0 RAWDSTTRAN: CH2 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH2_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH2_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH2 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH3_Pos             3                                                       /*!< GPDMA0 RAWDSTTRAN: CH3 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH3_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH3_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH3 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH4_Pos             4                                                       /*!< GPDMA0 RAWDSTTRAN: CH4 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH4_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH4_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH4 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH5_Pos             5                                                       /*!< GPDMA0 RAWDSTTRAN: CH5 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH5_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH5_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH5 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH6_Pos             6                                                       /*!< GPDMA0 RAWDSTTRAN: CH6 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH6_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH6_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH6 Mask             */\r
+#define GPDMA0_RAWDSTTRAN_CH7_Pos             7                                                       /*!< GPDMA0 RAWDSTTRAN: CH7 Position         */\r
+#define GPDMA0_RAWDSTTRAN_CH7_Msk             (0x01UL << GPDMA0_RAWDSTTRAN_CH7_Pos)                   /*!< GPDMA0 RAWDSTTRAN: CH7 Mask             */\r
+\r
+/* --------------------------------  GPDMA0_RAWERR  ------------------------------- */\r
+#define GPDMA0_RAWERR_CH0_Pos                 0                                                       /*!< GPDMA0 RAWERR: CH0 Position             */\r
+#define GPDMA0_RAWERR_CH0_Msk                 (0x01UL << GPDMA0_RAWERR_CH0_Pos)                       /*!< GPDMA0 RAWERR: CH0 Mask                 */\r
+#define GPDMA0_RAWERR_CH1_Pos                 1                                                       /*!< GPDMA0 RAWERR: CH1 Position             */\r
+#define GPDMA0_RAWERR_CH1_Msk                 (0x01UL << GPDMA0_RAWERR_CH1_Pos)                       /*!< GPDMA0 RAWERR: CH1 Mask                 */\r
+#define GPDMA0_RAWERR_CH2_Pos                 2                                                       /*!< GPDMA0 RAWERR: CH2 Position             */\r
+#define GPDMA0_RAWERR_CH2_Msk                 (0x01UL << GPDMA0_RAWERR_CH2_Pos)                       /*!< GPDMA0 RAWERR: CH2 Mask                 */\r
+#define GPDMA0_RAWERR_CH3_Pos                 3                                                       /*!< GPDMA0 RAWERR: CH3 Position             */\r
+#define GPDMA0_RAWERR_CH3_Msk                 (0x01UL << GPDMA0_RAWERR_CH3_Pos)                       /*!< GPDMA0 RAWERR: CH3 Mask                 */\r
+#define GPDMA0_RAWERR_CH4_Pos                 4                                                       /*!< GPDMA0 RAWERR: CH4 Position             */\r
+#define GPDMA0_RAWERR_CH4_Msk                 (0x01UL << GPDMA0_RAWERR_CH4_Pos)                       /*!< GPDMA0 RAWERR: CH4 Mask                 */\r
+#define GPDMA0_RAWERR_CH5_Pos                 5                                                       /*!< GPDMA0 RAWERR: CH5 Position             */\r
+#define GPDMA0_RAWERR_CH5_Msk                 (0x01UL << GPDMA0_RAWERR_CH5_Pos)                       /*!< GPDMA0 RAWERR: CH5 Mask                 */\r
+#define GPDMA0_RAWERR_CH6_Pos                 6                                                       /*!< GPDMA0 RAWERR: CH6 Position             */\r
+#define GPDMA0_RAWERR_CH6_Msk                 (0x01UL << GPDMA0_RAWERR_CH6_Pos)                       /*!< GPDMA0 RAWERR: CH6 Mask                 */\r
+#define GPDMA0_RAWERR_CH7_Pos                 7                                                       /*!< GPDMA0 RAWERR: CH7 Position             */\r
+#define GPDMA0_RAWERR_CH7_Msk                 (0x01UL << GPDMA0_RAWERR_CH7_Pos)                       /*!< GPDMA0 RAWERR: CH7 Mask                 */\r
+\r
+/* ------------------------------  GPDMA0_STATUSTFR  ------------------------------ */\r
+#define GPDMA0_STATUSTFR_CH0_Pos              0                                                       /*!< GPDMA0 STATUSTFR: CH0 Position          */\r
+#define GPDMA0_STATUSTFR_CH0_Msk              (0x01UL << GPDMA0_STATUSTFR_CH0_Pos)                    /*!< GPDMA0 STATUSTFR: CH0 Mask              */\r
+#define GPDMA0_STATUSTFR_CH1_Pos              1                                                       /*!< GPDMA0 STATUSTFR: CH1 Position          */\r
+#define GPDMA0_STATUSTFR_CH1_Msk              (0x01UL << GPDMA0_STATUSTFR_CH1_Pos)                    /*!< GPDMA0 STATUSTFR: CH1 Mask              */\r
+#define GPDMA0_STATUSTFR_CH2_Pos              2                                                       /*!< GPDMA0 STATUSTFR: CH2 Position          */\r
+#define GPDMA0_STATUSTFR_CH2_Msk              (0x01UL << GPDMA0_STATUSTFR_CH2_Pos)                    /*!< GPDMA0 STATUSTFR: CH2 Mask              */\r
+#define GPDMA0_STATUSTFR_CH3_Pos              3                                                       /*!< GPDMA0 STATUSTFR: CH3 Position          */\r
+#define GPDMA0_STATUSTFR_CH3_Msk              (0x01UL << GPDMA0_STATUSTFR_CH3_Pos)                    /*!< GPDMA0 STATUSTFR: CH3 Mask              */\r
+#define GPDMA0_STATUSTFR_CH4_Pos              4                                                       /*!< GPDMA0 STATUSTFR: CH4 Position          */\r
+#define GPDMA0_STATUSTFR_CH4_Msk              (0x01UL << GPDMA0_STATUSTFR_CH4_Pos)                    /*!< GPDMA0 STATUSTFR: CH4 Mask              */\r
+#define GPDMA0_STATUSTFR_CH5_Pos              5                                                       /*!< GPDMA0 STATUSTFR: CH5 Position          */\r
+#define GPDMA0_STATUSTFR_CH5_Msk              (0x01UL << GPDMA0_STATUSTFR_CH5_Pos)                    /*!< GPDMA0 STATUSTFR: CH5 Mask              */\r
+#define GPDMA0_STATUSTFR_CH6_Pos              6                                                       /*!< GPDMA0 STATUSTFR: CH6 Position          */\r
+#define GPDMA0_STATUSTFR_CH6_Msk              (0x01UL << GPDMA0_STATUSTFR_CH6_Pos)                    /*!< GPDMA0 STATUSTFR: CH6 Mask              */\r
+#define GPDMA0_STATUSTFR_CH7_Pos              7                                                       /*!< GPDMA0 STATUSTFR: CH7 Position          */\r
+#define GPDMA0_STATUSTFR_CH7_Msk              (0x01UL << GPDMA0_STATUSTFR_CH7_Pos)                    /*!< GPDMA0 STATUSTFR: CH7 Mask              */\r
+\r
+/* -----------------------------  GPDMA0_STATUSBLOCK  ----------------------------- */\r
+#define GPDMA0_STATUSBLOCK_CH0_Pos            0                                                       /*!< GPDMA0 STATUSBLOCK: CH0 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH0_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH0_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH0 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH1_Pos            1                                                       /*!< GPDMA0 STATUSBLOCK: CH1 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH1_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH1_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH1 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH2_Pos            2                                                       /*!< GPDMA0 STATUSBLOCK: CH2 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH2_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH2_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH2 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH3_Pos            3                                                       /*!< GPDMA0 STATUSBLOCK: CH3 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH3_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH3_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH3 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH4_Pos            4                                                       /*!< GPDMA0 STATUSBLOCK: CH4 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH4_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH4_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH4 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH5_Pos            5                                                       /*!< GPDMA0 STATUSBLOCK: CH5 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH5_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH5_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH5 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH6_Pos            6                                                       /*!< GPDMA0 STATUSBLOCK: CH6 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH6_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH6_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH6 Mask            */\r
+#define GPDMA0_STATUSBLOCK_CH7_Pos            7                                                       /*!< GPDMA0 STATUSBLOCK: CH7 Position        */\r
+#define GPDMA0_STATUSBLOCK_CH7_Msk            (0x01UL << GPDMA0_STATUSBLOCK_CH7_Pos)                  /*!< GPDMA0 STATUSBLOCK: CH7 Mask            */\r
+\r
+/* ----------------------------  GPDMA0_STATUSSRCTRAN  ---------------------------- */\r
+#define GPDMA0_STATUSSRCTRAN_CH0_Pos          0                                                       /*!< GPDMA0 STATUSSRCTRAN: CH0 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH0_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH0_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH0 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH1_Pos          1                                                       /*!< GPDMA0 STATUSSRCTRAN: CH1 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH1_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH1_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH1 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH2_Pos          2                                                       /*!< GPDMA0 STATUSSRCTRAN: CH2 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH2_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH2_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH2 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH3_Pos          3                                                       /*!< GPDMA0 STATUSSRCTRAN: CH3 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH3_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH3_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH3 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH4_Pos          4                                                       /*!< GPDMA0 STATUSSRCTRAN: CH4 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH4_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH4_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH4 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH5_Pos          5                                                       /*!< GPDMA0 STATUSSRCTRAN: CH5 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH5_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH5_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH5 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH6_Pos          6                                                       /*!< GPDMA0 STATUSSRCTRAN: CH6 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH6_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH6_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH6 Mask          */\r
+#define GPDMA0_STATUSSRCTRAN_CH7_Pos          7                                                       /*!< GPDMA0 STATUSSRCTRAN: CH7 Position      */\r
+#define GPDMA0_STATUSSRCTRAN_CH7_Msk          (0x01UL << GPDMA0_STATUSSRCTRAN_CH7_Pos)                /*!< GPDMA0 STATUSSRCTRAN: CH7 Mask          */\r
+\r
+/* ----------------------------  GPDMA0_STATUSDSTTRAN  ---------------------------- */\r
+#define GPDMA0_STATUSDSTTRAN_CH0_Pos          0                                                       /*!< GPDMA0 STATUSDSTTRAN: CH0 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH0_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH0_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH0 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH1_Pos          1                                                       /*!< GPDMA0 STATUSDSTTRAN: CH1 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH1_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH1_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH1 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH2_Pos          2                                                       /*!< GPDMA0 STATUSDSTTRAN: CH2 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH2_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH2_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH2 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH3_Pos          3                                                       /*!< GPDMA0 STATUSDSTTRAN: CH3 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH3_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH3_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH3 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH4_Pos          4                                                       /*!< GPDMA0 STATUSDSTTRAN: CH4 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH4_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH4_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH4 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH5_Pos          5                                                       /*!< GPDMA0 STATUSDSTTRAN: CH5 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH5_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH5_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH5 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH6_Pos          6                                                       /*!< GPDMA0 STATUSDSTTRAN: CH6 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH6_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH6_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH6 Mask          */\r
+#define GPDMA0_STATUSDSTTRAN_CH7_Pos          7                                                       /*!< GPDMA0 STATUSDSTTRAN: CH7 Position      */\r
+#define GPDMA0_STATUSDSTTRAN_CH7_Msk          (0x01UL << GPDMA0_STATUSDSTTRAN_CH7_Pos)                /*!< GPDMA0 STATUSDSTTRAN: CH7 Mask          */\r
+\r
+/* ------------------------------  GPDMA0_STATUSERR  ------------------------------ */\r
+#define GPDMA0_STATUSERR_CH0_Pos              0                                                       /*!< GPDMA0 STATUSERR: CH0 Position          */\r
+#define GPDMA0_STATUSERR_CH0_Msk              (0x01UL << GPDMA0_STATUSERR_CH0_Pos)                    /*!< GPDMA0 STATUSERR: CH0 Mask              */\r
+#define GPDMA0_STATUSERR_CH1_Pos              1                                                       /*!< GPDMA0 STATUSERR: CH1 Position          */\r
+#define GPDMA0_STATUSERR_CH1_Msk              (0x01UL << GPDMA0_STATUSERR_CH1_Pos)                    /*!< GPDMA0 STATUSERR: CH1 Mask              */\r
+#define GPDMA0_STATUSERR_CH2_Pos              2                                                       /*!< GPDMA0 STATUSERR: CH2 Position          */\r
+#define GPDMA0_STATUSERR_CH2_Msk              (0x01UL << GPDMA0_STATUSERR_CH2_Pos)                    /*!< GPDMA0 STATUSERR: CH2 Mask              */\r
+#define GPDMA0_STATUSERR_CH3_Pos              3                                                       /*!< GPDMA0 STATUSERR: CH3 Position          */\r
+#define GPDMA0_STATUSERR_CH3_Msk              (0x01UL << GPDMA0_STATUSERR_CH3_Pos)                    /*!< GPDMA0 STATUSERR: CH3 Mask              */\r
+#define GPDMA0_STATUSERR_CH4_Pos              4                                                       /*!< GPDMA0 STATUSERR: CH4 Position          */\r
+#define GPDMA0_STATUSERR_CH4_Msk              (0x01UL << GPDMA0_STATUSERR_CH4_Pos)                    /*!< GPDMA0 STATUSERR: CH4 Mask              */\r
+#define GPDMA0_STATUSERR_CH5_Pos              5                                                       /*!< GPDMA0 STATUSERR: CH5 Position          */\r
+#define GPDMA0_STATUSERR_CH5_Msk              (0x01UL << GPDMA0_STATUSERR_CH5_Pos)                    /*!< GPDMA0 STATUSERR: CH5 Mask              */\r
+#define GPDMA0_STATUSERR_CH6_Pos              6                                                       /*!< GPDMA0 STATUSERR: CH6 Position          */\r
+#define GPDMA0_STATUSERR_CH6_Msk              (0x01UL << GPDMA0_STATUSERR_CH6_Pos)                    /*!< GPDMA0 STATUSERR: CH6 Mask              */\r
+#define GPDMA0_STATUSERR_CH7_Pos              7                                                       /*!< GPDMA0 STATUSERR: CH7 Position          */\r
+#define GPDMA0_STATUSERR_CH7_Msk              (0x01UL << GPDMA0_STATUSERR_CH7_Pos)                    /*!< GPDMA0 STATUSERR: CH7 Mask              */\r
+\r
+/* -------------------------------  GPDMA0_MASKTFR  ------------------------------- */\r
+#define GPDMA0_MASKTFR_CH0_Pos                0                                                       /*!< GPDMA0 MASKTFR: CH0 Position            */\r
+#define GPDMA0_MASKTFR_CH0_Msk                (0x01UL << GPDMA0_MASKTFR_CH0_Pos)                      /*!< GPDMA0 MASKTFR: CH0 Mask                */\r
+#define GPDMA0_MASKTFR_CH1_Pos                1                                                       /*!< GPDMA0 MASKTFR: CH1 Position            */\r
+#define GPDMA0_MASKTFR_CH1_Msk                (0x01UL << GPDMA0_MASKTFR_CH1_Pos)                      /*!< GPDMA0 MASKTFR: CH1 Mask                */\r
+#define GPDMA0_MASKTFR_CH2_Pos                2                                                       /*!< GPDMA0 MASKTFR: CH2 Position            */\r
+#define GPDMA0_MASKTFR_CH2_Msk                (0x01UL << GPDMA0_MASKTFR_CH2_Pos)                      /*!< GPDMA0 MASKTFR: CH2 Mask                */\r
+#define GPDMA0_MASKTFR_CH3_Pos                3                                                       /*!< GPDMA0 MASKTFR: CH3 Position            */\r
+#define GPDMA0_MASKTFR_CH3_Msk                (0x01UL << GPDMA0_MASKTFR_CH3_Pos)                      /*!< GPDMA0 MASKTFR: CH3 Mask                */\r
+#define GPDMA0_MASKTFR_CH4_Pos                4                                                       /*!< GPDMA0 MASKTFR: CH4 Position            */\r
+#define GPDMA0_MASKTFR_CH4_Msk                (0x01UL << GPDMA0_MASKTFR_CH4_Pos)                      /*!< GPDMA0 MASKTFR: CH4 Mask                */\r
+#define GPDMA0_MASKTFR_CH5_Pos                5                                                       /*!< GPDMA0 MASKTFR: CH5 Position            */\r
+#define GPDMA0_MASKTFR_CH5_Msk                (0x01UL << GPDMA0_MASKTFR_CH5_Pos)                      /*!< GPDMA0 MASKTFR: CH5 Mask                */\r
+#define GPDMA0_MASKTFR_CH6_Pos                6                                                       /*!< GPDMA0 MASKTFR: CH6 Position            */\r
+#define GPDMA0_MASKTFR_CH6_Msk                (0x01UL << GPDMA0_MASKTFR_CH6_Pos)                      /*!< GPDMA0 MASKTFR: CH6 Mask                */\r
+#define GPDMA0_MASKTFR_CH7_Pos                7                                                       /*!< GPDMA0 MASKTFR: CH7 Position            */\r
+#define GPDMA0_MASKTFR_CH7_Msk                (0x01UL << GPDMA0_MASKTFR_CH7_Pos)                      /*!< GPDMA0 MASKTFR: CH7 Mask                */\r
+#define GPDMA0_MASKTFR_WE_CH0_Pos             8                                                       /*!< GPDMA0 MASKTFR: WE_CH0 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH0_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH0_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH0 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH1_Pos             9                                                       /*!< GPDMA0 MASKTFR: WE_CH1 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH1_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH1_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH1 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH2_Pos             10                                                      /*!< GPDMA0 MASKTFR: WE_CH2 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH2_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH2_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH2 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH3_Pos             11                                                      /*!< GPDMA0 MASKTFR: WE_CH3 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH3_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH3_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH3 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH4_Pos             12                                                      /*!< GPDMA0 MASKTFR: WE_CH4 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH4_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH4_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH4 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH5_Pos             13                                                      /*!< GPDMA0 MASKTFR: WE_CH5 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH5_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH5_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH5 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH6_Pos             14                                                      /*!< GPDMA0 MASKTFR: WE_CH6 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH6_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH6_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH6 Mask             */\r
+#define GPDMA0_MASKTFR_WE_CH7_Pos             15                                                      /*!< GPDMA0 MASKTFR: WE_CH7 Position         */\r
+#define GPDMA0_MASKTFR_WE_CH7_Msk             (0x01UL << GPDMA0_MASKTFR_WE_CH7_Pos)                   /*!< GPDMA0 MASKTFR: WE_CH7 Mask             */\r
+\r
+/* ------------------------------  GPDMA0_MASKBLOCK  ------------------------------ */\r
+#define GPDMA0_MASKBLOCK_CH0_Pos              0                                                       /*!< GPDMA0 MASKBLOCK: CH0 Position          */\r
+#define GPDMA0_MASKBLOCK_CH0_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH0_Pos)                    /*!< GPDMA0 MASKBLOCK: CH0 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH1_Pos              1                                                       /*!< GPDMA0 MASKBLOCK: CH1 Position          */\r
+#define GPDMA0_MASKBLOCK_CH1_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH1_Pos)                    /*!< GPDMA0 MASKBLOCK: CH1 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH2_Pos              2                                                       /*!< GPDMA0 MASKBLOCK: CH2 Position          */\r
+#define GPDMA0_MASKBLOCK_CH2_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH2_Pos)                    /*!< GPDMA0 MASKBLOCK: CH2 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH3_Pos              3                                                       /*!< GPDMA0 MASKBLOCK: CH3 Position          */\r
+#define GPDMA0_MASKBLOCK_CH3_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH3_Pos)                    /*!< GPDMA0 MASKBLOCK: CH3 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH4_Pos              4                                                       /*!< GPDMA0 MASKBLOCK: CH4 Position          */\r
+#define GPDMA0_MASKBLOCK_CH4_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH4_Pos)                    /*!< GPDMA0 MASKBLOCK: CH4 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH5_Pos              5                                                       /*!< GPDMA0 MASKBLOCK: CH5 Position          */\r
+#define GPDMA0_MASKBLOCK_CH5_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH5_Pos)                    /*!< GPDMA0 MASKBLOCK: CH5 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH6_Pos              6                                                       /*!< GPDMA0 MASKBLOCK: CH6 Position          */\r
+#define GPDMA0_MASKBLOCK_CH6_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH6_Pos)                    /*!< GPDMA0 MASKBLOCK: CH6 Mask              */\r
+#define GPDMA0_MASKBLOCK_CH7_Pos              7                                                       /*!< GPDMA0 MASKBLOCK: CH7 Position          */\r
+#define GPDMA0_MASKBLOCK_CH7_Msk              (0x01UL << GPDMA0_MASKBLOCK_CH7_Pos)                    /*!< GPDMA0 MASKBLOCK: CH7 Mask              */\r
+#define GPDMA0_MASKBLOCK_WE_CH0_Pos           8                                                       /*!< GPDMA0 MASKBLOCK: WE_CH0 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH0_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH0_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH0 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH1_Pos           9                                                       /*!< GPDMA0 MASKBLOCK: WE_CH1 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH1_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH1_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH1 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH2_Pos           10                                                      /*!< GPDMA0 MASKBLOCK: WE_CH2 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH2_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH2_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH2 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH3_Pos           11                                                      /*!< GPDMA0 MASKBLOCK: WE_CH3 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH3_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH3_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH3 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH4_Pos           12                                                      /*!< GPDMA0 MASKBLOCK: WE_CH4 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH4_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH4_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH4 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH5_Pos           13                                                      /*!< GPDMA0 MASKBLOCK: WE_CH5 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH5_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH5_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH5 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH6_Pos           14                                                      /*!< GPDMA0 MASKBLOCK: WE_CH6 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH6_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH6_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH6 Mask           */\r
+#define GPDMA0_MASKBLOCK_WE_CH7_Pos           15                                                      /*!< GPDMA0 MASKBLOCK: WE_CH7 Position       */\r
+#define GPDMA0_MASKBLOCK_WE_CH7_Msk           (0x01UL << GPDMA0_MASKBLOCK_WE_CH7_Pos)                 /*!< GPDMA0 MASKBLOCK: WE_CH7 Mask           */\r
+\r
+/* -----------------------------  GPDMA0_MASKSRCTRAN  ----------------------------- */\r
+#define GPDMA0_MASKSRCTRAN_CH0_Pos            0                                                       /*!< GPDMA0 MASKSRCTRAN: CH0 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH0_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH0_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH0 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH1_Pos            1                                                       /*!< GPDMA0 MASKSRCTRAN: CH1 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH1_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH1_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH1 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH2_Pos            2                                                       /*!< GPDMA0 MASKSRCTRAN: CH2 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH2_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH2_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH2 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH3_Pos            3                                                       /*!< GPDMA0 MASKSRCTRAN: CH3 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH3_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH3_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH3 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH4_Pos            4                                                       /*!< GPDMA0 MASKSRCTRAN: CH4 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH4_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH4_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH4 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH5_Pos            5                                                       /*!< GPDMA0 MASKSRCTRAN: CH5 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH5_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH5_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH5 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH6_Pos            6                                                       /*!< GPDMA0 MASKSRCTRAN: CH6 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH6_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH6_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH6 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_CH7_Pos            7                                                       /*!< GPDMA0 MASKSRCTRAN: CH7 Position        */\r
+#define GPDMA0_MASKSRCTRAN_CH7_Msk            (0x01UL << GPDMA0_MASKSRCTRAN_CH7_Pos)                  /*!< GPDMA0 MASKSRCTRAN: CH7 Mask            */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH0_Pos         8                                                       /*!< GPDMA0 MASKSRCTRAN: WE_CH0 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH0_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH0_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH0 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH1_Pos         9                                                       /*!< GPDMA0 MASKSRCTRAN: WE_CH1 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH1_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH1_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH1 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH2_Pos         10                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH2 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH2_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH2_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH2 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH3_Pos         11                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH3 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH3_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH3_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH3 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH4_Pos         12                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH4 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH4_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH4_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH4 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH5_Pos         13                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH5 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH5_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH5_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH5 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH6_Pos         14                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH6 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH6_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH6_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH6 Mask         */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH7_Pos         15                                                      /*!< GPDMA0 MASKSRCTRAN: WE_CH7 Position     */\r
+#define GPDMA0_MASKSRCTRAN_WE_CH7_Msk         (0x01UL << GPDMA0_MASKSRCTRAN_WE_CH7_Pos)               /*!< GPDMA0 MASKSRCTRAN: WE_CH7 Mask         */\r
+\r
+/* -----------------------------  GPDMA0_MASKDSTTRAN  ----------------------------- */\r
+#define GPDMA0_MASKDSTTRAN_CH0_Pos            0                                                       /*!< GPDMA0 MASKDSTTRAN: CH0 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH0_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH0_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH0 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH1_Pos            1                                                       /*!< GPDMA0 MASKDSTTRAN: CH1 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH1_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH1_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH1 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH2_Pos            2                                                       /*!< GPDMA0 MASKDSTTRAN: CH2 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH2_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH2_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH2 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH3_Pos            3                                                       /*!< GPDMA0 MASKDSTTRAN: CH3 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH3_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH3_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH3 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH4_Pos            4                                                       /*!< GPDMA0 MASKDSTTRAN: CH4 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH4_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH4_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH4 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH5_Pos            5                                                       /*!< GPDMA0 MASKDSTTRAN: CH5 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH5_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH5_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH5 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH6_Pos            6                                                       /*!< GPDMA0 MASKDSTTRAN: CH6 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH6_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH6_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH6 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_CH7_Pos            7                                                       /*!< GPDMA0 MASKDSTTRAN: CH7 Position        */\r
+#define GPDMA0_MASKDSTTRAN_CH7_Msk            (0x01UL << GPDMA0_MASKDSTTRAN_CH7_Pos)                  /*!< GPDMA0 MASKDSTTRAN: CH7 Mask            */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH0_Pos         8                                                       /*!< GPDMA0 MASKDSTTRAN: WE_CH0 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH0_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH0_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH0 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH1_Pos         9                                                       /*!< GPDMA0 MASKDSTTRAN: WE_CH1 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH1_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH1_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH1 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH2_Pos         10                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH2 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH2_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH2_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH2 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH3_Pos         11                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH3 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH3_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH3_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH3 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH4_Pos         12                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH4 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH4_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH4_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH4 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH5_Pos         13                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH5 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH5_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH5_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH5 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH6_Pos         14                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH6 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH6_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH6_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH6 Mask         */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH7_Pos         15                                                      /*!< GPDMA0 MASKDSTTRAN: WE_CH7 Position     */\r
+#define GPDMA0_MASKDSTTRAN_WE_CH7_Msk         (0x01UL << GPDMA0_MASKDSTTRAN_WE_CH7_Pos)               /*!< GPDMA0 MASKDSTTRAN: WE_CH7 Mask         */\r
+\r
+/* -------------------------------  GPDMA0_MASKERR  ------------------------------- */\r
+#define GPDMA0_MASKERR_CH0_Pos                0                                                       /*!< GPDMA0 MASKERR: CH0 Position            */\r
+#define GPDMA0_MASKERR_CH0_Msk                (0x01UL << GPDMA0_MASKERR_CH0_Pos)                      /*!< GPDMA0 MASKERR: CH0 Mask                */\r
+#define GPDMA0_MASKERR_CH1_Pos                1                                                       /*!< GPDMA0 MASKERR: CH1 Position            */\r
+#define GPDMA0_MASKERR_CH1_Msk                (0x01UL << GPDMA0_MASKERR_CH1_Pos)                      /*!< GPDMA0 MASKERR: CH1 Mask                */\r
+#define GPDMA0_MASKERR_CH2_Pos                2                                                       /*!< GPDMA0 MASKERR: CH2 Position            */\r
+#define GPDMA0_MASKERR_CH2_Msk                (0x01UL << GPDMA0_MASKERR_CH2_Pos)                      /*!< GPDMA0 MASKERR: CH2 Mask                */\r
+#define GPDMA0_MASKERR_CH3_Pos                3                                                       /*!< GPDMA0 MASKERR: CH3 Position            */\r
+#define GPDMA0_MASKERR_CH3_Msk                (0x01UL << GPDMA0_MASKERR_CH3_Pos)                      /*!< GPDMA0 MASKERR: CH3 Mask                */\r
+#define GPDMA0_MASKERR_CH4_Pos                4                                                       /*!< GPDMA0 MASKERR: CH4 Position            */\r
+#define GPDMA0_MASKERR_CH4_Msk                (0x01UL << GPDMA0_MASKERR_CH4_Pos)                      /*!< GPDMA0 MASKERR: CH4 Mask                */\r
+#define GPDMA0_MASKERR_CH5_Pos                5                                                       /*!< GPDMA0 MASKERR: CH5 Position            */\r
+#define GPDMA0_MASKERR_CH5_Msk                (0x01UL << GPDMA0_MASKERR_CH5_Pos)                      /*!< GPDMA0 MASKERR: CH5 Mask                */\r
+#define GPDMA0_MASKERR_CH6_Pos                6                                                       /*!< GPDMA0 MASKERR: CH6 Position            */\r
+#define GPDMA0_MASKERR_CH6_Msk                (0x01UL << GPDMA0_MASKERR_CH6_Pos)                      /*!< GPDMA0 MASKERR: CH6 Mask                */\r
+#define GPDMA0_MASKERR_CH7_Pos                7                                                       /*!< GPDMA0 MASKERR: CH7 Position            */\r
+#define GPDMA0_MASKERR_CH7_Msk                (0x01UL << GPDMA0_MASKERR_CH7_Pos)                      /*!< GPDMA0 MASKERR: CH7 Mask                */\r
+#define GPDMA0_MASKERR_WE_CH0_Pos             8                                                       /*!< GPDMA0 MASKERR: WE_CH0 Position         */\r
+#define GPDMA0_MASKERR_WE_CH0_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH0_Pos)                   /*!< GPDMA0 MASKERR: WE_CH0 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH1_Pos             9                                                       /*!< GPDMA0 MASKERR: WE_CH1 Position         */\r
+#define GPDMA0_MASKERR_WE_CH1_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH1_Pos)                   /*!< GPDMA0 MASKERR: WE_CH1 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH2_Pos             10                                                      /*!< GPDMA0 MASKERR: WE_CH2 Position         */\r
+#define GPDMA0_MASKERR_WE_CH2_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH2_Pos)                   /*!< GPDMA0 MASKERR: WE_CH2 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH3_Pos             11                                                      /*!< GPDMA0 MASKERR: WE_CH3 Position         */\r
+#define GPDMA0_MASKERR_WE_CH3_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH3_Pos)                   /*!< GPDMA0 MASKERR: WE_CH3 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH4_Pos             12                                                      /*!< GPDMA0 MASKERR: WE_CH4 Position         */\r
+#define GPDMA0_MASKERR_WE_CH4_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH4_Pos)                   /*!< GPDMA0 MASKERR: WE_CH4 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH5_Pos             13                                                      /*!< GPDMA0 MASKERR: WE_CH5 Position         */\r
+#define GPDMA0_MASKERR_WE_CH5_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH5_Pos)                   /*!< GPDMA0 MASKERR: WE_CH5 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH6_Pos             14                                                      /*!< GPDMA0 MASKERR: WE_CH6 Position         */\r
+#define GPDMA0_MASKERR_WE_CH6_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH6_Pos)                   /*!< GPDMA0 MASKERR: WE_CH6 Mask             */\r
+#define GPDMA0_MASKERR_WE_CH7_Pos             15                                                      /*!< GPDMA0 MASKERR: WE_CH7 Position         */\r
+#define GPDMA0_MASKERR_WE_CH7_Msk             (0x01UL << GPDMA0_MASKERR_WE_CH7_Pos)                   /*!< GPDMA0 MASKERR: WE_CH7 Mask             */\r
+\r
+/* -------------------------------  GPDMA0_CLEARTFR  ------------------------------ */\r
+#define GPDMA0_CLEARTFR_CH0_Pos               0                                                       /*!< GPDMA0 CLEARTFR: CH0 Position           */\r
+#define GPDMA0_CLEARTFR_CH0_Msk               (0x01UL << GPDMA0_CLEARTFR_CH0_Pos)                     /*!< GPDMA0 CLEARTFR: CH0 Mask               */\r
+#define GPDMA0_CLEARTFR_CH1_Pos               1                                                       /*!< GPDMA0 CLEARTFR: CH1 Position           */\r
+#define GPDMA0_CLEARTFR_CH1_Msk               (0x01UL << GPDMA0_CLEARTFR_CH1_Pos)                     /*!< GPDMA0 CLEARTFR: CH1 Mask               */\r
+#define GPDMA0_CLEARTFR_CH2_Pos               2                                                       /*!< GPDMA0 CLEARTFR: CH2 Position           */\r
+#define GPDMA0_CLEARTFR_CH2_Msk               (0x01UL << GPDMA0_CLEARTFR_CH2_Pos)                     /*!< GPDMA0 CLEARTFR: CH2 Mask               */\r
+#define GPDMA0_CLEARTFR_CH3_Pos               3                                                       /*!< GPDMA0 CLEARTFR: CH3 Position           */\r
+#define GPDMA0_CLEARTFR_CH3_Msk               (0x01UL << GPDMA0_CLEARTFR_CH3_Pos)                     /*!< GPDMA0 CLEARTFR: CH3 Mask               */\r
+#define GPDMA0_CLEARTFR_CH4_Pos               4                                                       /*!< GPDMA0 CLEARTFR: CH4 Position           */\r
+#define GPDMA0_CLEARTFR_CH4_Msk               (0x01UL << GPDMA0_CLEARTFR_CH4_Pos)                     /*!< GPDMA0 CLEARTFR: CH4 Mask               */\r
+#define GPDMA0_CLEARTFR_CH5_Pos               5                                                       /*!< GPDMA0 CLEARTFR: CH5 Position           */\r
+#define GPDMA0_CLEARTFR_CH5_Msk               (0x01UL << GPDMA0_CLEARTFR_CH5_Pos)                     /*!< GPDMA0 CLEARTFR: CH5 Mask               */\r
+#define GPDMA0_CLEARTFR_CH6_Pos               6                                                       /*!< GPDMA0 CLEARTFR: CH6 Position           */\r
+#define GPDMA0_CLEARTFR_CH6_Msk               (0x01UL << GPDMA0_CLEARTFR_CH6_Pos)                     /*!< GPDMA0 CLEARTFR: CH6 Mask               */\r
+#define GPDMA0_CLEARTFR_CH7_Pos               7                                                       /*!< GPDMA0 CLEARTFR: CH7 Position           */\r
+#define GPDMA0_CLEARTFR_CH7_Msk               (0x01UL << GPDMA0_CLEARTFR_CH7_Pos)                     /*!< GPDMA0 CLEARTFR: CH7 Mask               */\r
+\r
+/* ------------------------------  GPDMA0_CLEARBLOCK  ----------------------------- */\r
+#define GPDMA0_CLEARBLOCK_CH0_Pos             0                                                       /*!< GPDMA0 CLEARBLOCK: CH0 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH0_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH0_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH0 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH1_Pos             1                                                       /*!< GPDMA0 CLEARBLOCK: CH1 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH1_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH1_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH1 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH2_Pos             2                                                       /*!< GPDMA0 CLEARBLOCK: CH2 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH2_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH2_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH2 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH3_Pos             3                                                       /*!< GPDMA0 CLEARBLOCK: CH3 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH3_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH3_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH3 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH4_Pos             4                                                       /*!< GPDMA0 CLEARBLOCK: CH4 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH4_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH4_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH4 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH5_Pos             5                                                       /*!< GPDMA0 CLEARBLOCK: CH5 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH5_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH5_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH5 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH6_Pos             6                                                       /*!< GPDMA0 CLEARBLOCK: CH6 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH6_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH6_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH6 Mask             */\r
+#define GPDMA0_CLEARBLOCK_CH7_Pos             7                                                       /*!< GPDMA0 CLEARBLOCK: CH7 Position         */\r
+#define GPDMA0_CLEARBLOCK_CH7_Msk             (0x01UL << GPDMA0_CLEARBLOCK_CH7_Pos)                   /*!< GPDMA0 CLEARBLOCK: CH7 Mask             */\r
+\r
+/* -----------------------------  GPDMA0_CLEARSRCTRAN  ---------------------------- */\r
+#define GPDMA0_CLEARSRCTRAN_CH0_Pos           0                                                       /*!< GPDMA0 CLEARSRCTRAN: CH0 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH0_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH0_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH0 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH1_Pos           1                                                       /*!< GPDMA0 CLEARSRCTRAN: CH1 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH1_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH1_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH1 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH2_Pos           2                                                       /*!< GPDMA0 CLEARSRCTRAN: CH2 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH2_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH2_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH2 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH3_Pos           3                                                       /*!< GPDMA0 CLEARSRCTRAN: CH3 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH3_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH3_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH3 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH4_Pos           4                                                       /*!< GPDMA0 CLEARSRCTRAN: CH4 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH4_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH4_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH4 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH5_Pos           5                                                       /*!< GPDMA0 CLEARSRCTRAN: CH5 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH5_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH5_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH5 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH6_Pos           6                                                       /*!< GPDMA0 CLEARSRCTRAN: CH6 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH6_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH6_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH6 Mask           */\r
+#define GPDMA0_CLEARSRCTRAN_CH7_Pos           7                                                       /*!< GPDMA0 CLEARSRCTRAN: CH7 Position       */\r
+#define GPDMA0_CLEARSRCTRAN_CH7_Msk           (0x01UL << GPDMA0_CLEARSRCTRAN_CH7_Pos)                 /*!< GPDMA0 CLEARSRCTRAN: CH7 Mask           */\r
+\r
+/* -----------------------------  GPDMA0_CLEARDSTTRAN  ---------------------------- */\r
+#define GPDMA0_CLEARDSTTRAN_CH0_Pos           0                                                       /*!< GPDMA0 CLEARDSTTRAN: CH0 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH0_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH0_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH0 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH1_Pos           1                                                       /*!< GPDMA0 CLEARDSTTRAN: CH1 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH1_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH1_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH1 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH2_Pos           2                                                       /*!< GPDMA0 CLEARDSTTRAN: CH2 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH2_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH2_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH2 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH3_Pos           3                                                       /*!< GPDMA0 CLEARDSTTRAN: CH3 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH3_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH3_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH3 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH4_Pos           4                                                       /*!< GPDMA0 CLEARDSTTRAN: CH4 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH4_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH4_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH4 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH5_Pos           5                                                       /*!< GPDMA0 CLEARDSTTRAN: CH5 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH5_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH5_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH5 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH6_Pos           6                                                       /*!< GPDMA0 CLEARDSTTRAN: CH6 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH6_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH6_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH6 Mask           */\r
+#define GPDMA0_CLEARDSTTRAN_CH7_Pos           7                                                       /*!< GPDMA0 CLEARDSTTRAN: CH7 Position       */\r
+#define GPDMA0_CLEARDSTTRAN_CH7_Msk           (0x01UL << GPDMA0_CLEARDSTTRAN_CH7_Pos)                 /*!< GPDMA0 CLEARDSTTRAN: CH7 Mask           */\r
+\r
+/* -------------------------------  GPDMA0_CLEARERR  ------------------------------ */\r
+#define GPDMA0_CLEARERR_CH0_Pos               0                                                       /*!< GPDMA0 CLEARERR: CH0 Position           */\r
+#define GPDMA0_CLEARERR_CH0_Msk               (0x01UL << GPDMA0_CLEARERR_CH0_Pos)                     /*!< GPDMA0 CLEARERR: CH0 Mask               */\r
+#define GPDMA0_CLEARERR_CH1_Pos               1                                                       /*!< GPDMA0 CLEARERR: CH1 Position           */\r
+#define GPDMA0_CLEARERR_CH1_Msk               (0x01UL << GPDMA0_CLEARERR_CH1_Pos)                     /*!< GPDMA0 CLEARERR: CH1 Mask               */\r
+#define GPDMA0_CLEARERR_CH2_Pos               2                                                       /*!< GPDMA0 CLEARERR: CH2 Position           */\r
+#define GPDMA0_CLEARERR_CH2_Msk               (0x01UL << GPDMA0_CLEARERR_CH2_Pos)                     /*!< GPDMA0 CLEARERR: CH2 Mask               */\r
+#define GPDMA0_CLEARERR_CH3_Pos               3                                                       /*!< GPDMA0 CLEARERR: CH3 Position           */\r
+#define GPDMA0_CLEARERR_CH3_Msk               (0x01UL << GPDMA0_CLEARERR_CH3_Pos)                     /*!< GPDMA0 CLEARERR: CH3 Mask               */\r
+#define GPDMA0_CLEARERR_CH4_Pos               4                                                       /*!< GPDMA0 CLEARERR: CH4 Position           */\r
+#define GPDMA0_CLEARERR_CH4_Msk               (0x01UL << GPDMA0_CLEARERR_CH4_Pos)                     /*!< GPDMA0 CLEARERR: CH4 Mask               */\r
+#define GPDMA0_CLEARERR_CH5_Pos               5                                                       /*!< GPDMA0 CLEARERR: CH5 Position           */\r
+#define GPDMA0_CLEARERR_CH5_Msk               (0x01UL << GPDMA0_CLEARERR_CH5_Pos)                     /*!< GPDMA0 CLEARERR: CH5 Mask               */\r
+#define GPDMA0_CLEARERR_CH6_Pos               6                                                       /*!< GPDMA0 CLEARERR: CH6 Position           */\r
+#define GPDMA0_CLEARERR_CH6_Msk               (0x01UL << GPDMA0_CLEARERR_CH6_Pos)                     /*!< GPDMA0 CLEARERR: CH6 Mask               */\r
+#define GPDMA0_CLEARERR_CH7_Pos               7                                                       /*!< GPDMA0 CLEARERR: CH7 Position           */\r
+#define GPDMA0_CLEARERR_CH7_Msk               (0x01UL << GPDMA0_CLEARERR_CH7_Pos)                     /*!< GPDMA0 CLEARERR: CH7 Mask               */\r
+\r
+/* ------------------------------  GPDMA0_STATUSINT  ------------------------------ */\r
+#define GPDMA0_STATUSINT_TFR_Pos              0                                                       /*!< GPDMA0 STATUSINT: TFR Position          */\r
+#define GPDMA0_STATUSINT_TFR_Msk              (0x01UL << GPDMA0_STATUSINT_TFR_Pos)                    /*!< GPDMA0 STATUSINT: TFR Mask              */\r
+#define GPDMA0_STATUSINT_BLOCK_Pos            1                                                       /*!< GPDMA0 STATUSINT: BLOCK Position        */\r
+#define GPDMA0_STATUSINT_BLOCK_Msk            (0x01UL << GPDMA0_STATUSINT_BLOCK_Pos)                  /*!< GPDMA0 STATUSINT: BLOCK Mask            */\r
+#define GPDMA0_STATUSINT_SRCT_Pos             2                                                       /*!< GPDMA0 STATUSINT: SRCT Position         */\r
+#define GPDMA0_STATUSINT_SRCT_Msk             (0x01UL << GPDMA0_STATUSINT_SRCT_Pos)                   /*!< GPDMA0 STATUSINT: SRCT Mask             */\r
+#define GPDMA0_STATUSINT_DSTT_Pos             3                                                       /*!< GPDMA0 STATUSINT: DSTT Position         */\r
+#define GPDMA0_STATUSINT_DSTT_Msk             (0x01UL << GPDMA0_STATUSINT_DSTT_Pos)                   /*!< GPDMA0 STATUSINT: DSTT Mask             */\r
+#define GPDMA0_STATUSINT_ERR_Pos              4                                                       /*!< GPDMA0 STATUSINT: ERR Position          */\r
+#define GPDMA0_STATUSINT_ERR_Msk              (0x01UL << GPDMA0_STATUSINT_ERR_Pos)                    /*!< GPDMA0 STATUSINT: ERR Mask              */\r
+\r
+/* ------------------------------  GPDMA0_REQSRCREG  ------------------------------ */\r
+#define GPDMA0_REQSRCREG_CH0_Pos              0                                                       /*!< GPDMA0 REQSRCREG: CH0 Position          */\r
+#define GPDMA0_REQSRCREG_CH0_Msk              (0x01UL << GPDMA0_REQSRCREG_CH0_Pos)                    /*!< GPDMA0 REQSRCREG: CH0 Mask              */\r
+#define GPDMA0_REQSRCREG_CH1_Pos              1                                                       /*!< GPDMA0 REQSRCREG: CH1 Position          */\r
+#define GPDMA0_REQSRCREG_CH1_Msk              (0x01UL << GPDMA0_REQSRCREG_CH1_Pos)                    /*!< GPDMA0 REQSRCREG: CH1 Mask              */\r
+#define GPDMA0_REQSRCREG_CH2_Pos              2                                                       /*!< GPDMA0 REQSRCREG: CH2 Position          */\r
+#define GPDMA0_REQSRCREG_CH2_Msk              (0x01UL << GPDMA0_REQSRCREG_CH2_Pos)                    /*!< GPDMA0 REQSRCREG: CH2 Mask              */\r
+#define GPDMA0_REQSRCREG_CH3_Pos              3                                                       /*!< GPDMA0 REQSRCREG: CH3 Position          */\r
+#define GPDMA0_REQSRCREG_CH3_Msk              (0x01UL << GPDMA0_REQSRCREG_CH3_Pos)                    /*!< GPDMA0 REQSRCREG: CH3 Mask              */\r
+#define GPDMA0_REQSRCREG_CH4_Pos              4                                                       /*!< GPDMA0 REQSRCREG: CH4 Position          */\r
+#define GPDMA0_REQSRCREG_CH4_Msk              (0x01UL << GPDMA0_REQSRCREG_CH4_Pos)                    /*!< GPDMA0 REQSRCREG: CH4 Mask              */\r
+#define GPDMA0_REQSRCREG_CH5_Pos              5                                                       /*!< GPDMA0 REQSRCREG: CH5 Position          */\r
+#define GPDMA0_REQSRCREG_CH5_Msk              (0x01UL << GPDMA0_REQSRCREG_CH5_Pos)                    /*!< GPDMA0 REQSRCREG: CH5 Mask              */\r
+#define GPDMA0_REQSRCREG_CH6_Pos              6                                                       /*!< GPDMA0 REQSRCREG: CH6 Position          */\r
+#define GPDMA0_REQSRCREG_CH6_Msk              (0x01UL << GPDMA0_REQSRCREG_CH6_Pos)                    /*!< GPDMA0 REQSRCREG: CH6 Mask              */\r
+#define GPDMA0_REQSRCREG_CH7_Pos              7                                                       /*!< GPDMA0 REQSRCREG: CH7 Position          */\r
+#define GPDMA0_REQSRCREG_CH7_Msk              (0x01UL << GPDMA0_REQSRCREG_CH7_Pos)                    /*!< GPDMA0 REQSRCREG: CH7 Mask              */\r
+#define GPDMA0_REQSRCREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 REQSRCREG: WE_CH0 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH0_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH0_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH0 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 REQSRCREG: WE_CH1 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH1_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH1_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH1 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 REQSRCREG: WE_CH2 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH2_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH2_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH2 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 REQSRCREG: WE_CH3 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH3_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH3_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH3 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 REQSRCREG: WE_CH4 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH4_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH4_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH4 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 REQSRCREG: WE_CH5 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH5_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH5_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH5 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 REQSRCREG: WE_CH6 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH6_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH6_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH6 Mask           */\r
+#define GPDMA0_REQSRCREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 REQSRCREG: WE_CH7 Position       */\r
+#define GPDMA0_REQSRCREG_WE_CH7_Msk           (0x01UL << GPDMA0_REQSRCREG_WE_CH7_Pos)                 /*!< GPDMA0 REQSRCREG: WE_CH7 Mask           */\r
+\r
+/* ------------------------------  GPDMA0_REQDSTREG  ------------------------------ */\r
+#define GPDMA0_REQDSTREG_CH0_Pos              0                                                       /*!< GPDMA0 REQDSTREG: CH0 Position          */\r
+#define GPDMA0_REQDSTREG_CH0_Msk              (0x01UL << GPDMA0_REQDSTREG_CH0_Pos)                    /*!< GPDMA0 REQDSTREG: CH0 Mask              */\r
+#define GPDMA0_REQDSTREG_CH1_Pos              1                                                       /*!< GPDMA0 REQDSTREG: CH1 Position          */\r
+#define GPDMA0_REQDSTREG_CH1_Msk              (0x01UL << GPDMA0_REQDSTREG_CH1_Pos)                    /*!< GPDMA0 REQDSTREG: CH1 Mask              */\r
+#define GPDMA0_REQDSTREG_CH2_Pos              2                                                       /*!< GPDMA0 REQDSTREG: CH2 Position          */\r
+#define GPDMA0_REQDSTREG_CH2_Msk              (0x01UL << GPDMA0_REQDSTREG_CH2_Pos)                    /*!< GPDMA0 REQDSTREG: CH2 Mask              */\r
+#define GPDMA0_REQDSTREG_CH3_Pos              3                                                       /*!< GPDMA0 REQDSTREG: CH3 Position          */\r
+#define GPDMA0_REQDSTREG_CH3_Msk              (0x01UL << GPDMA0_REQDSTREG_CH3_Pos)                    /*!< GPDMA0 REQDSTREG: CH3 Mask              */\r
+#define GPDMA0_REQDSTREG_CH4_Pos              4                                                       /*!< GPDMA0 REQDSTREG: CH4 Position          */\r
+#define GPDMA0_REQDSTREG_CH4_Msk              (0x01UL << GPDMA0_REQDSTREG_CH4_Pos)                    /*!< GPDMA0 REQDSTREG: CH4 Mask              */\r
+#define GPDMA0_REQDSTREG_CH5_Pos              5                                                       /*!< GPDMA0 REQDSTREG: CH5 Position          */\r
+#define GPDMA0_REQDSTREG_CH5_Msk              (0x01UL << GPDMA0_REQDSTREG_CH5_Pos)                    /*!< GPDMA0 REQDSTREG: CH5 Mask              */\r
+#define GPDMA0_REQDSTREG_CH6_Pos              6                                                       /*!< GPDMA0 REQDSTREG: CH6 Position          */\r
+#define GPDMA0_REQDSTREG_CH6_Msk              (0x01UL << GPDMA0_REQDSTREG_CH6_Pos)                    /*!< GPDMA0 REQDSTREG: CH6 Mask              */\r
+#define GPDMA0_REQDSTREG_CH7_Pos              7                                                       /*!< GPDMA0 REQDSTREG: CH7 Position          */\r
+#define GPDMA0_REQDSTREG_CH7_Msk              (0x01UL << GPDMA0_REQDSTREG_CH7_Pos)                    /*!< GPDMA0 REQDSTREG: CH7 Mask              */\r
+#define GPDMA0_REQDSTREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 REQDSTREG: WE_CH0 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH0_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH0_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH0 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 REQDSTREG: WE_CH1 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH1_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH1_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH1 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 REQDSTREG: WE_CH2 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH2_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH2_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH2 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 REQDSTREG: WE_CH3 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH3_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH3_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH3 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 REQDSTREG: WE_CH4 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH4_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH4_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH4 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 REQDSTREG: WE_CH5 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH5_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH5_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH5 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 REQDSTREG: WE_CH6 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH6_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH6_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH6 Mask           */\r
+#define GPDMA0_REQDSTREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 REQDSTREG: WE_CH7 Position       */\r
+#define GPDMA0_REQDSTREG_WE_CH7_Msk           (0x01UL << GPDMA0_REQDSTREG_WE_CH7_Pos)                 /*!< GPDMA0 REQDSTREG: WE_CH7 Mask           */\r
+\r
+/* -----------------------------  GPDMA0_SGLREQSRCREG  ---------------------------- */\r
+#define GPDMA0_SGLREQSRCREG_CH0_Pos           0                                                       /*!< GPDMA0 SGLREQSRCREG: CH0 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH0_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH0_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH0 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH1_Pos           1                                                       /*!< GPDMA0 SGLREQSRCREG: CH1 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH1_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH1_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH1 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH2_Pos           2                                                       /*!< GPDMA0 SGLREQSRCREG: CH2 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH2_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH2_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH2 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH3_Pos           3                                                       /*!< GPDMA0 SGLREQSRCREG: CH3 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH3_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH3_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH3 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH4_Pos           4                                                       /*!< GPDMA0 SGLREQSRCREG: CH4 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH4_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH4_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH4 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH5_Pos           5                                                       /*!< GPDMA0 SGLREQSRCREG: CH5 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH5_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH5_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH5 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH6_Pos           6                                                       /*!< GPDMA0 SGLREQSRCREG: CH6 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH6_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH6_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH6 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_CH7_Pos           7                                                       /*!< GPDMA0 SGLREQSRCREG: CH7 Position       */\r
+#define GPDMA0_SGLREQSRCREG_CH7_Msk           (0x01UL << GPDMA0_SGLREQSRCREG_CH7_Pos)                 /*!< GPDMA0 SGLREQSRCREG: CH7 Mask           */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH0_Pos        8                                                       /*!< GPDMA0 SGLREQSRCREG: WE_CH0 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH0_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH0_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH0 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH1_Pos        9                                                       /*!< GPDMA0 SGLREQSRCREG: WE_CH1 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH1_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH1_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH1 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH2_Pos        10                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH2 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH2_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH2_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH2 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH3_Pos        11                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH3 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH3_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH3_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH3 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH4_Pos        12                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH4 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH4_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH4_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH4 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH5_Pos        13                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH5 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH5_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH5_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH5 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH6_Pos        14                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH6 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH6_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH6_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH6 Mask        */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH7_Pos        15                                                      /*!< GPDMA0 SGLREQSRCREG: WE_CH7 Position    */\r
+#define GPDMA0_SGLREQSRCREG_WE_CH7_Msk        (0x01UL << GPDMA0_SGLREQSRCREG_WE_CH7_Pos)              /*!< GPDMA0 SGLREQSRCREG: WE_CH7 Mask        */\r
+\r
+/* -----------------------------  GPDMA0_SGLREQDSTREG  ---------------------------- */\r
+#define GPDMA0_SGLREQDSTREG_CH0_Pos           0                                                       /*!< GPDMA0 SGLREQDSTREG: CH0 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH0_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH0_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH0 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH1_Pos           1                                                       /*!< GPDMA0 SGLREQDSTREG: CH1 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH1_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH1_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH1 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH2_Pos           2                                                       /*!< GPDMA0 SGLREQDSTREG: CH2 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH2_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH2_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH2 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH3_Pos           3                                                       /*!< GPDMA0 SGLREQDSTREG: CH3 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH3_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH3_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH3 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH4_Pos           4                                                       /*!< GPDMA0 SGLREQDSTREG: CH4 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH4_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH4_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH4 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH5_Pos           5                                                       /*!< GPDMA0 SGLREQDSTREG: CH5 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH5_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH5_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH5 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH6_Pos           6                                                       /*!< GPDMA0 SGLREQDSTREG: CH6 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH6_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH6_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH6 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_CH7_Pos           7                                                       /*!< GPDMA0 SGLREQDSTREG: CH7 Position       */\r
+#define GPDMA0_SGLREQDSTREG_CH7_Msk           (0x01UL << GPDMA0_SGLREQDSTREG_CH7_Pos)                 /*!< GPDMA0 SGLREQDSTREG: CH7 Mask           */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH0_Pos        8                                                       /*!< GPDMA0 SGLREQDSTREG: WE_CH0 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH0_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH0_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH0 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH1_Pos        9                                                       /*!< GPDMA0 SGLREQDSTREG: WE_CH1 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH1_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH1_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH1 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH2_Pos        10                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH2 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH2_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH2_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH2 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH3_Pos        11                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH3 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH3_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH3_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH3 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH4_Pos        12                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH4 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH4_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH4_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH4 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH5_Pos        13                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH5 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH5_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH5_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH5 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH6_Pos        14                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH6 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH6_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH6_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH6 Mask        */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH7_Pos        15                                                      /*!< GPDMA0 SGLREQDSTREG: WE_CH7 Position    */\r
+#define GPDMA0_SGLREQDSTREG_WE_CH7_Msk        (0x01UL << GPDMA0_SGLREQDSTREG_WE_CH7_Pos)              /*!< GPDMA0 SGLREQDSTREG: WE_CH7 Mask        */\r
+\r
+/* ------------------------------  GPDMA0_LSTSRCREG  ------------------------------ */\r
+#define GPDMA0_LSTSRCREG_CH0_Pos              0                                                       /*!< GPDMA0 LSTSRCREG: CH0 Position          */\r
+#define GPDMA0_LSTSRCREG_CH0_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH0_Pos)                    /*!< GPDMA0 LSTSRCREG: CH0 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH1_Pos              1                                                       /*!< GPDMA0 LSTSRCREG: CH1 Position          */\r
+#define GPDMA0_LSTSRCREG_CH1_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH1_Pos)                    /*!< GPDMA0 LSTSRCREG: CH1 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH2_Pos              2                                                       /*!< GPDMA0 LSTSRCREG: CH2 Position          */\r
+#define GPDMA0_LSTSRCREG_CH2_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH2_Pos)                    /*!< GPDMA0 LSTSRCREG: CH2 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH3_Pos              3                                                       /*!< GPDMA0 LSTSRCREG: CH3 Position          */\r
+#define GPDMA0_LSTSRCREG_CH3_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH3_Pos)                    /*!< GPDMA0 LSTSRCREG: CH3 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH4_Pos              4                                                       /*!< GPDMA0 LSTSRCREG: CH4 Position          */\r
+#define GPDMA0_LSTSRCREG_CH4_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH4_Pos)                    /*!< GPDMA0 LSTSRCREG: CH4 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH5_Pos              5                                                       /*!< GPDMA0 LSTSRCREG: CH5 Position          */\r
+#define GPDMA0_LSTSRCREG_CH5_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH5_Pos)                    /*!< GPDMA0 LSTSRCREG: CH5 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH6_Pos              6                                                       /*!< GPDMA0 LSTSRCREG: CH6 Position          */\r
+#define GPDMA0_LSTSRCREG_CH6_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH6_Pos)                    /*!< GPDMA0 LSTSRCREG: CH6 Mask              */\r
+#define GPDMA0_LSTSRCREG_CH7_Pos              7                                                       /*!< GPDMA0 LSTSRCREG: CH7 Position          */\r
+#define GPDMA0_LSTSRCREG_CH7_Msk              (0x01UL << GPDMA0_LSTSRCREG_CH7_Pos)                    /*!< GPDMA0 LSTSRCREG: CH7 Mask              */\r
+#define GPDMA0_LSTSRCREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 LSTSRCREG: WE_CH0 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH0_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH0_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH0 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 LSTSRCREG: WE_CH1 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH1_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH1_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH1 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 LSTSRCREG: WE_CH2 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH2_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH2_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH2 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 LSTSRCREG: WE_CH3 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH3_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH3_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH3 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 LSTSRCREG: WE_CH4 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH4_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH4_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH4 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 LSTSRCREG: WE_CH5 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH5_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH5_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH5 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 LSTSRCREG: WE_CH6 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH6_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH6_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH6 Mask           */\r
+#define GPDMA0_LSTSRCREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 LSTSRCREG: WE_CH7 Position       */\r
+#define GPDMA0_LSTSRCREG_WE_CH7_Msk           (0x01UL << GPDMA0_LSTSRCREG_WE_CH7_Pos)                 /*!< GPDMA0 LSTSRCREG: WE_CH7 Mask           */\r
+\r
+/* ------------------------------  GPDMA0_LSTDSTREG  ------------------------------ */\r
+#define GPDMA0_LSTDSTREG_CH0_Pos              0                                                       /*!< GPDMA0 LSTDSTREG: CH0 Position          */\r
+#define GPDMA0_LSTDSTREG_CH0_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH0_Pos)                    /*!< GPDMA0 LSTDSTREG: CH0 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH1_Pos              1                                                       /*!< GPDMA0 LSTDSTREG: CH1 Position          */\r
+#define GPDMA0_LSTDSTREG_CH1_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH1_Pos)                    /*!< GPDMA0 LSTDSTREG: CH1 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH2_Pos              2                                                       /*!< GPDMA0 LSTDSTREG: CH2 Position          */\r
+#define GPDMA0_LSTDSTREG_CH2_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH2_Pos)                    /*!< GPDMA0 LSTDSTREG: CH2 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH3_Pos              3                                                       /*!< GPDMA0 LSTDSTREG: CH3 Position          */\r
+#define GPDMA0_LSTDSTREG_CH3_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH3_Pos)                    /*!< GPDMA0 LSTDSTREG: CH3 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH4_Pos              4                                                       /*!< GPDMA0 LSTDSTREG: CH4 Position          */\r
+#define GPDMA0_LSTDSTREG_CH4_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH4_Pos)                    /*!< GPDMA0 LSTDSTREG: CH4 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH5_Pos              5                                                       /*!< GPDMA0 LSTDSTREG: CH5 Position          */\r
+#define GPDMA0_LSTDSTREG_CH5_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH5_Pos)                    /*!< GPDMA0 LSTDSTREG: CH5 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH6_Pos              6                                                       /*!< GPDMA0 LSTDSTREG: CH6 Position          */\r
+#define GPDMA0_LSTDSTREG_CH6_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH6_Pos)                    /*!< GPDMA0 LSTDSTREG: CH6 Mask              */\r
+#define GPDMA0_LSTDSTREG_CH7_Pos              7                                                       /*!< GPDMA0 LSTDSTREG: CH7 Position          */\r
+#define GPDMA0_LSTDSTREG_CH7_Msk              (0x01UL << GPDMA0_LSTDSTREG_CH7_Pos)                    /*!< GPDMA0 LSTDSTREG: CH7 Mask              */\r
+#define GPDMA0_LSTDSTREG_WE_CH0_Pos           8                                                       /*!< GPDMA0 LSTDSTREG: WE_CH0 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH0_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH0_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH0 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH1_Pos           9                                                       /*!< GPDMA0 LSTDSTREG: WE_CH1 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH1_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH1_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH1 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH2_Pos           10                                                      /*!< GPDMA0 LSTDSTREG: WE_CH2 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH2_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH2_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH2 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH3_Pos           11                                                      /*!< GPDMA0 LSTDSTREG: WE_CH3 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH3_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH3_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH3 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH4_Pos           12                                                      /*!< GPDMA0 LSTDSTREG: WE_CH4 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH4_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH4_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH4 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH5_Pos           13                                                      /*!< GPDMA0 LSTDSTREG: WE_CH5 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH5_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH5_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH5 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH6_Pos           14                                                      /*!< GPDMA0 LSTDSTREG: WE_CH6 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH6_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH6_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH6 Mask           */\r
+#define GPDMA0_LSTDSTREG_WE_CH7_Pos           15                                                      /*!< GPDMA0 LSTDSTREG: WE_CH7 Position       */\r
+#define GPDMA0_LSTDSTREG_WE_CH7_Msk           (0x01UL << GPDMA0_LSTDSTREG_WE_CH7_Pos)                 /*!< GPDMA0 LSTDSTREG: WE_CH7 Mask           */\r
+\r
+/* ------------------------------  GPDMA0_DMACFGREG  ------------------------------ */\r
+#define GPDMA0_DMACFGREG_DMA_EN_Pos           0                                                       /*!< GPDMA0 DMACFGREG: DMA_EN Position       */\r
+#define GPDMA0_DMACFGREG_DMA_EN_Msk           (0x01UL << GPDMA0_DMACFGREG_DMA_EN_Pos)                 /*!< GPDMA0 DMACFGREG: DMA_EN Mask           */\r
+\r
+/* -------------------------------  GPDMA0_CHENREG  ------------------------------- */\r
+#define GPDMA0_CHENREG_CH_Pos                 0                                                       /*!< GPDMA0 CHENREG: CH Position             */\r
+#define GPDMA0_CHENREG_CH_Msk                 (0x000000ffUL << GPDMA0_CHENREG_CH_Pos)                 /*!< GPDMA0 CHENREG: CH Mask                 */\r
+#define GPDMA0_CHENREG_WE_CH_Pos              8                                                       /*!< GPDMA0 CHENREG: WE_CH Position          */\r
+#define GPDMA0_CHENREG_WE_CH_Msk              (0x000000ffUL << GPDMA0_CHENREG_WE_CH_Pos)              /*!< GPDMA0 CHENREG: WE_CH Mask              */\r
+\r
+/* ----------------------------------  GPDMA0_ID  --------------------------------- */\r
+#define GPDMA0_ID_VALUE_Pos                   0                                                       /*!< GPDMA0 ID: VALUE Position               */\r
+#define GPDMA0_ID_VALUE_Msk                   (0xffffffffUL << GPDMA0_ID_VALUE_Pos)                   /*!< GPDMA0 ID: VALUE Mask                   */\r
+\r
+/* ---------------------------------  GPDMA0_TYPE  -------------------------------- */\r
+#define GPDMA0_TYPE_VALUE_Pos                 0                                                       /*!< GPDMA0 TYPE: VALUE Position             */\r
+#define GPDMA0_TYPE_VALUE_Msk                 (0xffffffffUL << GPDMA0_TYPE_VALUE_Pos)                 /*!< GPDMA0 TYPE: VALUE Mask                 */\r
+\r
+/* -------------------------------  GPDMA0_VERSION  ------------------------------- */\r
+#define GPDMA0_VERSION_VALUE_Pos              0                                                       /*!< GPDMA0 VERSION: VALUE Position          */\r
+#define GPDMA0_VERSION_VALUE_Msk              (0xffffffffUL << GPDMA0_VERSION_VALUE_Pos)              /*!< GPDMA0 VERSION: VALUE Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      Group 'GPDMA0_CH0_1' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  GPDMA0_CH_SAR  ------------------------------ */\r
+#define GPDMA0_CH_SAR_SAR_Pos              0                                                       /*!< GPDMA0_CH0_1 SAR: SAR Position          */\r
+#define GPDMA0_CH_SAR_SAR_Msk              (0xffffffffUL << GPDMA0_CH_SAR_SAR_Pos)              /*!< GPDMA0_CH0_1 SAR: SAR Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_DAR  ------------------------------ */\r
+#define GPDMA0_CH_DAR_DAR_Pos              0                                                       /*!< GPDMA0_CH0_1 DAR: DAR Position          */\r
+#define GPDMA0_CH_DAR_DAR_Msk              (0xffffffffUL << GPDMA0_CH_DAR_DAR_Pos)              /*!< GPDMA0_CH0_1 DAR: DAR Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_LLP  ------------------------------ */\r
+#define GPDMA0_CH_LLP_LOC_Pos              2                                                       /*!< GPDMA0_CH0_1 LLP: LOC Position          */\r
+#define GPDMA0_CH_LLP_LOC_Msk              (0x3fffffffUL << GPDMA0_CH_LLP_LOC_Pos)              /*!< GPDMA0_CH0_1 LLP: LOC Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_CTLL  ----------------------------- */\r
+#define GPDMA0_CH_CTLL_INT_EN_Pos          0                                                       /*!< GPDMA0_CH0_1 CTLL: INT_EN Position      */\r
+#define GPDMA0_CH_CTLL_INT_EN_Msk          (0x01UL << GPDMA0_CH_CTLL_INT_EN_Pos)                /*!< GPDMA0_CH0_1 CTLL: INT_EN Mask          */\r
+#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos    1                                                       /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH Position */\r
+#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk    (0x07UL << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos)          /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH Mask    */\r
+#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos    4                                                       /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH Position */\r
+#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk    (0x07UL << GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos)          /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH Mask    */\r
+#define GPDMA0_CH_CTLL_DINC_Pos            7                                                       /*!< GPDMA0_CH0_1 CTLL: DINC Position        */\r
+#define GPDMA0_CH_CTLL_DINC_Msk            (0x03UL << GPDMA0_CH_CTLL_DINC_Pos)                  /*!< GPDMA0_CH0_1 CTLL: DINC Mask            */\r
+#define GPDMA0_CH_CTLL_SINC_Pos            9                                                       /*!< GPDMA0_CH0_1 CTLL: SINC Position        */\r
+#define GPDMA0_CH_CTLL_SINC_Msk            (0x03UL << GPDMA0_CH_CTLL_SINC_Pos)                  /*!< GPDMA0_CH0_1 CTLL: SINC Mask            */\r
+#define GPDMA0_CH_CTLL_DEST_MSIZE_Pos      11                                                      /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE Position  */\r
+#define GPDMA0_CH_CTLL_DEST_MSIZE_Msk      (0x07UL << GPDMA0_CH_CTLL_DEST_MSIZE_Pos)            /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE Mask      */\r
+#define GPDMA0_CH_CTLL_SRC_MSIZE_Pos       14                                                      /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE Position   */\r
+#define GPDMA0_CH_CTLL_SRC_MSIZE_Msk       (0x07UL << GPDMA0_CH_CTLL_SRC_MSIZE_Pos)             /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE Mask       */\r
+#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos   17                                                      /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN Position */\r
+#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk   (0x01UL << GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos)         /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN Mask   */\r
+#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos  18                                                      /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN Position */\r
+#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk  (0x01UL << GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos)        /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN Mask  */\r
+#define GPDMA0_CH_CTLL_TT_FC_Pos           20                                                      /*!< GPDMA0_CH0_1 CTLL: TT_FC Position       */\r
+#define GPDMA0_CH_CTLL_TT_FC_Msk           (0x07UL << GPDMA0_CH_CTLL_TT_FC_Pos)                 /*!< GPDMA0_CH0_1 CTLL: TT_FC Mask           */\r
+#define GPDMA0_CH_CTLL_LLP_DST_EN_Pos      27                                                      /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN Position  */\r
+#define GPDMA0_CH_CTLL_LLP_DST_EN_Msk      (0x01UL << GPDMA0_CH_CTLL_LLP_DST_EN_Pos)            /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN Mask      */\r
+#define GPDMA0_CH_CTLL_LLP_SRC_EN_Pos      28                                                      /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN Position  */\r
+#define GPDMA0_CH_CTLL_LLP_SRC_EN_Msk      (0x01UL << GPDMA0_CH_CTLL_LLP_SRC_EN_Pos)            /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN Mask      */\r
+\r
+/* ------------------------------  GPDMA0_CH_CTLH  ----------------------------- */\r
+#define GPDMA0_CH_CTLH_BLOCK_TS_Pos        0                                                       /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS Position    */\r
+#define GPDMA0_CH_CTLH_BLOCK_TS_Msk        (0x00000fffUL << GPDMA0_CH_CTLH_BLOCK_TS_Pos)        /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS Mask        */\r
+#define GPDMA0_CH_CTLH_DONE_Pos            12                                                      /*!< GPDMA0_CH0_1 CTLH: DONE Position        */\r
+#define GPDMA0_CH_CTLH_DONE_Msk            (0x01UL << GPDMA0_CH_CTLH_DONE_Pos)                  /*!< GPDMA0_CH0_1 CTLH: DONE Mask            */\r
+\r
+/* -----------------------------  GPDMA0_CH_SSTAT  ----------------------------- */\r
+#define GPDMA0_CH_SSTAT_SSTAT_Pos          0                                                       /*!< GPDMA0_CH0_1 SSTAT: SSTAT Position      */\r
+#define GPDMA0_CH_SSTAT_SSTAT_Msk          (0xffffffffUL << GPDMA0_CH_SSTAT_SSTAT_Pos)          /*!< GPDMA0_CH0_1 SSTAT: SSTAT Mask          */\r
+\r
+/* -----------------------------  GPDMA0_CH_DSTAT  ----------------------------- */\r
+#define GPDMA0_CH_DSTAT_DSTAT_Pos          0                                                       /*!< GPDMA0_CH0_1 DSTAT: DSTAT Position      */\r
+#define GPDMA0_CH_DSTAT_DSTAT_Msk          (0xffffffffUL << GPDMA0_CH_DSTAT_DSTAT_Pos)          /*!< GPDMA0_CH0_1 DSTAT: DSTAT Mask          */\r
+\r
+/* ----------------------------  GPDMA0_CH_SSTATAR  ---------------------------- */\r
+#define GPDMA0_CH_SSTATAR_SSTATAR_Pos      0                                                       /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR Position  */\r
+#define GPDMA0_CH_SSTATAR_SSTATAR_Msk      (0xffffffffUL << GPDMA0_CH_SSTATAR_SSTATAR_Pos)      /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR Mask      */\r
+\r
+/* ----------------------------  GPDMA0_CH_DSTATAR  ---------------------------- */\r
+#define GPDMA0_CH_DSTATAR_DSTATAR_Pos      0                                                       /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR Position  */\r
+#define GPDMA0_CH_DSTATAR_DSTATAR_Msk      (0xffffffffUL << GPDMA0_CH_DSTATAR_DSTATAR_Pos)      /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR Mask      */\r
+\r
+/* ------------------------------  GPDMA0_CH_CFGL  ----------------------------- */\r
+#define GPDMA0_CH_CFGL_CH_PRIOR_Pos        5                                                       /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR Position    */\r
+#define GPDMA0_CH_CFGL_CH_PRIOR_Msk        (0x07UL << GPDMA0_CH_CFGL_CH_PRIOR_Pos)              /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR Mask        */\r
+#define GPDMA0_CH_CFGL_CH_SUSP_Pos         8                                                       /*!< GPDMA0_CH0_1 CFGL: CH_SUSP Position     */\r
+#define GPDMA0_CH_CFGL_CH_SUSP_Msk         (0x01UL << GPDMA0_CH_CFGL_CH_SUSP_Pos)               /*!< GPDMA0_CH0_1 CFGL: CH_SUSP Mask         */\r
+#define GPDMA0_CH_CFGL_FIFO_EMPTY_Pos      9                                                       /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY Position  */\r
+#define GPDMA0_CH_CFGL_FIFO_EMPTY_Msk      (0x01UL << GPDMA0_CH_CFGL_FIFO_EMPTY_Pos)            /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY Mask      */\r
+#define GPDMA0_CH_CFGL_HS_SEL_DST_Pos      10                                                      /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST Position  */\r
+#define GPDMA0_CH_CFGL_HS_SEL_DST_Msk      (0x01UL << GPDMA0_CH_CFGL_HS_SEL_DST_Pos)            /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST Mask      */\r
+#define GPDMA0_CH_CFGL_HS_SEL_SRC_Pos      11                                                      /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC Position  */\r
+#define GPDMA0_CH_CFGL_HS_SEL_SRC_Msk      (0x01UL << GPDMA0_CH_CFGL_HS_SEL_SRC_Pos)            /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC Mask      */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_L_Pos       12                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L Position   */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_L_Msk       (0x03UL << GPDMA0_CH_CFGL_LOCK_CH_L_Pos)             /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L Mask       */\r
+#define GPDMA0_CH_CFGL_LOCK_B_L_Pos        14                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L Position    */\r
+#define GPDMA0_CH_CFGL_LOCK_B_L_Msk        (0x03UL << GPDMA0_CH_CFGL_LOCK_B_L_Pos)              /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L Mask        */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_Pos         16                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_CH Position     */\r
+#define GPDMA0_CH_CFGL_LOCK_CH_Msk         (0x01UL << GPDMA0_CH_CFGL_LOCK_CH_Pos)               /*!< GPDMA0_CH0_1 CFGL: LOCK_CH Mask         */\r
+#define GPDMA0_CH_CFGL_LOCK_B_Pos          17                                                      /*!< GPDMA0_CH0_1 CFGL: LOCK_B Position      */\r
+#define GPDMA0_CH_CFGL_LOCK_B_Msk          (0x01UL << GPDMA0_CH_CFGL_LOCK_B_Pos)                /*!< GPDMA0_CH0_1 CFGL: LOCK_B Mask          */\r
+#define GPDMA0_CH_CFGL_DST_HS_POL_Pos      18                                                      /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL Position  */\r
+#define GPDMA0_CH_CFGL_DST_HS_POL_Msk      (0x01UL << GPDMA0_CH_CFGL_DST_HS_POL_Pos)            /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL Mask      */\r
+#define GPDMA0_CH_CFGL_SRC_HS_POL_Pos      19                                                      /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL Position  */\r
+#define GPDMA0_CH_CFGL_SRC_HS_POL_Msk      (0x01UL << GPDMA0_CH_CFGL_SRC_HS_POL_Pos)            /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL Mask      */\r
+#define GPDMA0_CH_CFGL_MAX_ABRST_Pos       20                                                      /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST Position   */\r
+#define GPDMA0_CH_CFGL_MAX_ABRST_Msk       (0x000003ffUL << GPDMA0_CH_CFGL_MAX_ABRST_Pos)       /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST Mask       */\r
+#define GPDMA0_CH_CFGL_RELOAD_SRC_Pos      30                                                      /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC Position  */\r
+#define GPDMA0_CH_CFGL_RELOAD_SRC_Msk      (0x01UL << GPDMA0_CH_CFGL_RELOAD_SRC_Pos)            /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC Mask      */\r
+#define GPDMA0_CH_CFGL_RELOAD_DST_Pos      31                                                      /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST Position  */\r
+#define GPDMA0_CH_CFGL_RELOAD_DST_Msk      (0x01UL << GPDMA0_CH_CFGL_RELOAD_DST_Pos)            /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST Mask      */\r
+\r
+/* ------------------------------  GPDMA0_CH_CFGH  ----------------------------- */\r
+#define GPDMA0_CH_CFGH_FCMODE_Pos          0                                                       /*!< GPDMA0_CH0_1 CFGH: FCMODE Position      */\r
+#define GPDMA0_CH_CFGH_FCMODE_Msk          (0x01UL << GPDMA0_CH_CFGH_FCMODE_Pos)                /*!< GPDMA0_CH0_1 CFGH: FCMODE Mask          */\r
+#define GPDMA0_CH_CFGH_FIFO_MODE_Pos       1                                                       /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE Position   */\r
+#define GPDMA0_CH_CFGH_FIFO_MODE_Msk       (0x01UL << GPDMA0_CH_CFGH_FIFO_MODE_Pos)             /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE Mask       */\r
+#define GPDMA0_CH_CFGH_PROTCTL_Pos         2                                                       /*!< GPDMA0_CH0_1 CFGH: PROTCTL Position     */\r
+#define GPDMA0_CH_CFGH_PROTCTL_Msk         (0x07UL << GPDMA0_CH_CFGH_PROTCTL_Pos)               /*!< GPDMA0_CH0_1 CFGH: PROTCTL Mask         */\r
+#define GPDMA0_CH_CFGH_DS_UPD_EN_Pos       5                                                       /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN Position   */\r
+#define GPDMA0_CH_CFGH_DS_UPD_EN_Msk       (0x01UL << GPDMA0_CH_CFGH_DS_UPD_EN_Pos)             /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN Mask       */\r
+#define GPDMA0_CH_CFGH_SS_UPD_EN_Pos       6                                                       /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN Position   */\r
+#define GPDMA0_CH_CFGH_SS_UPD_EN_Msk       (0x01UL << GPDMA0_CH_CFGH_SS_UPD_EN_Pos)             /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN Mask       */\r
+#define GPDMA0_CH_CFGH_SRC_PER_Pos         7                                                       /*!< GPDMA0_CH0_1 CFGH: SRC_PER Position     */\r
+#define GPDMA0_CH_CFGH_SRC_PER_Msk         (0x0fUL << GPDMA0_CH_CFGH_SRC_PER_Pos)               /*!< GPDMA0_CH0_1 CFGH: SRC_PER Mask         */\r
+#define GPDMA0_CH_CFGH_DEST_PER_Pos        11                                                      /*!< GPDMA0_CH0_1 CFGH: DEST_PER Position    */\r
+#define GPDMA0_CH_CFGH_DEST_PER_Msk        (0x0fUL << GPDMA0_CH_CFGH_DEST_PER_Pos)              /*!< GPDMA0_CH0_1 CFGH: DEST_PER Mask        */\r
+\r
+/* ------------------------------  GPDMA0_CH_SGR  ------------------------------ */\r
+#define GPDMA0_CH_SGR_SGI_Pos              0                                                       /*!< GPDMA0_CH0_1 SGR: SGI Position          */\r
+#define GPDMA0_CH_SGR_SGI_Msk              (0x000fffffUL << GPDMA0_CH_SGR_SGI_Pos)              /*!< GPDMA0_CH0_1 SGR: SGI Mask              */\r
+#define GPDMA0_CH_SGR_SGC_Pos              20                                                      /*!< GPDMA0_CH0_1 SGR: SGC Position          */\r
+#define GPDMA0_CH_SGR_SGC_Msk              (0x00000fffUL << GPDMA0_CH_SGR_SGC_Pos)              /*!< GPDMA0_CH0_1 SGR: SGC Mask              */\r
+\r
+/* ------------------------------  GPDMA0_CH_DSR  ------------------------------ */\r
+#define GPDMA0_CH_DSR_DSI_Pos              0                                                       /*!< GPDMA0_CH0_1 DSR: DSI Position          */\r
+#define GPDMA0_CH_DSR_DSI_Msk              (0x000fffffUL << GPDMA0_CH_DSR_DSI_Pos)              /*!< GPDMA0_CH0_1 DSR: DSI Mask              */\r
+#define GPDMA0_CH_DSR_DSC_Pos              20                                                      /*!< GPDMA0_CH0_1 DSR: DSC Position          */\r
+#define GPDMA0_CH_DSR_DSC_Msk              (0x00000fffUL << GPDMA0_CH_DSR_DSC_Pos)              /*!< GPDMA0_CH0_1 DSR: DSC Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'GPDMA1' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  GPDMA1_RAWTFR  ------------------------------- */\r
+#define GPDMA1_RAWTFR_CH0_Pos                 0                                                       /*!< GPDMA1 RAWTFR: CH0 Position             */\r
+#define GPDMA1_RAWTFR_CH0_Msk                 (0x01UL << GPDMA1_RAWTFR_CH0_Pos)                       /*!< GPDMA1 RAWTFR: CH0 Mask                 */\r
+#define GPDMA1_RAWTFR_CH1_Pos                 1                                                       /*!< GPDMA1 RAWTFR: CH1 Position             */\r
+#define GPDMA1_RAWTFR_CH1_Msk                 (0x01UL << GPDMA1_RAWTFR_CH1_Pos)                       /*!< GPDMA1 RAWTFR: CH1 Mask                 */\r
+#define GPDMA1_RAWTFR_CH2_Pos                 2                                                       /*!< GPDMA1 RAWTFR: CH2 Position             */\r
+#define GPDMA1_RAWTFR_CH2_Msk                 (0x01UL << GPDMA1_RAWTFR_CH2_Pos)                       /*!< GPDMA1 RAWTFR: CH2 Mask                 */\r
+#define GPDMA1_RAWTFR_CH3_Pos                 3                                                       /*!< GPDMA1 RAWTFR: CH3 Position             */\r
+#define GPDMA1_RAWTFR_CH3_Msk                 (0x01UL << GPDMA1_RAWTFR_CH3_Pos)                       /*!< GPDMA1 RAWTFR: CH3 Mask                 */\r
+\r
+/* -------------------------------  GPDMA1_RAWBLOCK  ------------------------------ */\r
+#define GPDMA1_RAWBLOCK_CH0_Pos               0                                                       /*!< GPDMA1 RAWBLOCK: CH0 Position           */\r
+#define GPDMA1_RAWBLOCK_CH0_Msk               (0x01UL << GPDMA1_RAWBLOCK_CH0_Pos)                     /*!< GPDMA1 RAWBLOCK: CH0 Mask               */\r
+#define GPDMA1_RAWBLOCK_CH1_Pos               1                                                       /*!< GPDMA1 RAWBLOCK: CH1 Position           */\r
+#define GPDMA1_RAWBLOCK_CH1_Msk               (0x01UL << GPDMA1_RAWBLOCK_CH1_Pos)                     /*!< GPDMA1 RAWBLOCK: CH1 Mask               */\r
+#define GPDMA1_RAWBLOCK_CH2_Pos               2                                                       /*!< GPDMA1 RAWBLOCK: CH2 Position           */\r
+#define GPDMA1_RAWBLOCK_CH2_Msk               (0x01UL << GPDMA1_RAWBLOCK_CH2_Pos)                     /*!< GPDMA1 RAWBLOCK: CH2 Mask               */\r
+#define GPDMA1_RAWBLOCK_CH3_Pos               3                                                       /*!< GPDMA1 RAWBLOCK: CH3 Position           */\r
+#define GPDMA1_RAWBLOCK_CH3_Msk               (0x01UL << GPDMA1_RAWBLOCK_CH3_Pos)                     /*!< GPDMA1 RAWBLOCK: CH3 Mask               */\r
+\r
+/* ------------------------------  GPDMA1_RAWSRCTRAN  ----------------------------- */\r
+#define GPDMA1_RAWSRCTRAN_CH0_Pos             0                                                       /*!< GPDMA1 RAWSRCTRAN: CH0 Position         */\r
+#define GPDMA1_RAWSRCTRAN_CH0_Msk             (0x01UL << GPDMA1_RAWSRCTRAN_CH0_Pos)                   /*!< GPDMA1 RAWSRCTRAN: CH0 Mask             */\r
+#define GPDMA1_RAWSRCTRAN_CH1_Pos             1                                                       /*!< GPDMA1 RAWSRCTRAN: CH1 Position         */\r
+#define GPDMA1_RAWSRCTRAN_CH1_Msk             (0x01UL << GPDMA1_RAWSRCTRAN_CH1_Pos)                   /*!< GPDMA1 RAWSRCTRAN: CH1 Mask             */\r
+#define GPDMA1_RAWSRCTRAN_CH2_Pos             2                                                       /*!< GPDMA1 RAWSRCTRAN: CH2 Position         */\r
+#define GPDMA1_RAWSRCTRAN_CH2_Msk             (0x01UL << GPDMA1_RAWSRCTRAN_CH2_Pos)                   /*!< GPDMA1 RAWSRCTRAN: CH2 Mask             */\r
+#define GPDMA1_RAWSRCTRAN_CH3_Pos             3                                                       /*!< GPDMA1 RAWSRCTRAN: CH3 Position         */\r
+#define GPDMA1_RAWSRCTRAN_CH3_Msk             (0x01UL << GPDMA1_RAWSRCTRAN_CH3_Pos)                   /*!< GPDMA1 RAWSRCTRAN: CH3 Mask             */\r
+\r
+/* ------------------------------  GPDMA1_RAWDSTTRAN  ----------------------------- */\r
+#define GPDMA1_RAWDSTTRAN_CH0_Pos             0                                                       /*!< GPDMA1 RAWDSTTRAN: CH0 Position         */\r
+#define GPDMA1_RAWDSTTRAN_CH0_Msk             (0x01UL << GPDMA1_RAWDSTTRAN_CH0_Pos)                   /*!< GPDMA1 RAWDSTTRAN: CH0 Mask             */\r
+#define GPDMA1_RAWDSTTRAN_CH1_Pos             1                                                       /*!< GPDMA1 RAWDSTTRAN: CH1 Position         */\r
+#define GPDMA1_RAWDSTTRAN_CH1_Msk             (0x01UL << GPDMA1_RAWDSTTRAN_CH1_Pos)                   /*!< GPDMA1 RAWDSTTRAN: CH1 Mask             */\r
+#define GPDMA1_RAWDSTTRAN_CH2_Pos             2                                                       /*!< GPDMA1 RAWDSTTRAN: CH2 Position         */\r
+#define GPDMA1_RAWDSTTRAN_CH2_Msk             (0x01UL << GPDMA1_RAWDSTTRAN_CH2_Pos)                   /*!< GPDMA1 RAWDSTTRAN: CH2 Mask             */\r
+#define GPDMA1_RAWDSTTRAN_CH3_Pos             3                                                       /*!< GPDMA1 RAWDSTTRAN: CH3 Position         */\r
+#define GPDMA1_RAWDSTTRAN_CH3_Msk             (0x01UL << GPDMA1_RAWDSTTRAN_CH3_Pos)                   /*!< GPDMA1 RAWDSTTRAN: CH3 Mask             */\r
+\r
+/* --------------------------------  GPDMA1_RAWERR  ------------------------------- */\r
+#define GPDMA1_RAWERR_CH0_Pos                 0                                                       /*!< GPDMA1 RAWERR: CH0 Position             */\r
+#define GPDMA1_RAWERR_CH0_Msk                 (0x01UL << GPDMA1_RAWERR_CH0_Pos)                       /*!< GPDMA1 RAWERR: CH0 Mask                 */\r
+#define GPDMA1_RAWERR_CH1_Pos                 1                                                       /*!< GPDMA1 RAWERR: CH1 Position             */\r
+#define GPDMA1_RAWERR_CH1_Msk                 (0x01UL << GPDMA1_RAWERR_CH1_Pos)                       /*!< GPDMA1 RAWERR: CH1 Mask                 */\r
+#define GPDMA1_RAWERR_CH2_Pos                 2                                                       /*!< GPDMA1 RAWERR: CH2 Position             */\r
+#define GPDMA1_RAWERR_CH2_Msk                 (0x01UL << GPDMA1_RAWERR_CH2_Pos)                       /*!< GPDMA1 RAWERR: CH2 Mask                 */\r
+#define GPDMA1_RAWERR_CH3_Pos                 3                                                       /*!< GPDMA1 RAWERR: CH3 Position             */\r
+#define GPDMA1_RAWERR_CH3_Msk                 (0x01UL << GPDMA1_RAWERR_CH3_Pos)                       /*!< GPDMA1 RAWERR: CH3 Mask                 */\r
+\r
+/* ------------------------------  GPDMA1_STATUSTFR  ------------------------------ */\r
+#define GPDMA1_STATUSTFR_CH0_Pos              0                                                       /*!< GPDMA1 STATUSTFR: CH0 Position          */\r
+#define GPDMA1_STATUSTFR_CH0_Msk              (0x01UL << GPDMA1_STATUSTFR_CH0_Pos)                    /*!< GPDMA1 STATUSTFR: CH0 Mask              */\r
+#define GPDMA1_STATUSTFR_CH1_Pos              1                                                       /*!< GPDMA1 STATUSTFR: CH1 Position          */\r
+#define GPDMA1_STATUSTFR_CH1_Msk              (0x01UL << GPDMA1_STATUSTFR_CH1_Pos)                    /*!< GPDMA1 STATUSTFR: CH1 Mask              */\r
+#define GPDMA1_STATUSTFR_CH2_Pos              2                                                       /*!< GPDMA1 STATUSTFR: CH2 Position          */\r
+#define GPDMA1_STATUSTFR_CH2_Msk              (0x01UL << GPDMA1_STATUSTFR_CH2_Pos)                    /*!< GPDMA1 STATUSTFR: CH2 Mask              */\r
+#define GPDMA1_STATUSTFR_CH3_Pos              3                                                       /*!< GPDMA1 STATUSTFR: CH3 Position          */\r
+#define GPDMA1_STATUSTFR_CH3_Msk              (0x01UL << GPDMA1_STATUSTFR_CH3_Pos)                    /*!< GPDMA1 STATUSTFR: CH3 Mask              */\r
+\r
+/* -----------------------------  GPDMA1_STATUSBLOCK  ----------------------------- */\r
+#define GPDMA1_STATUSBLOCK_CH0_Pos            0                                                       /*!< GPDMA1 STATUSBLOCK: CH0 Position        */\r
+#define GPDMA1_STATUSBLOCK_CH0_Msk            (0x01UL << GPDMA1_STATUSBLOCK_CH0_Pos)                  /*!< GPDMA1 STATUSBLOCK: CH0 Mask            */\r
+#define GPDMA1_STATUSBLOCK_CH1_Pos            1                                                       /*!< GPDMA1 STATUSBLOCK: CH1 Position        */\r
+#define GPDMA1_STATUSBLOCK_CH1_Msk            (0x01UL << GPDMA1_STATUSBLOCK_CH1_Pos)                  /*!< GPDMA1 STATUSBLOCK: CH1 Mask            */\r
+#define GPDMA1_STATUSBLOCK_CH2_Pos            2                                                       /*!< GPDMA1 STATUSBLOCK: CH2 Position        */\r
+#define GPDMA1_STATUSBLOCK_CH2_Msk            (0x01UL << GPDMA1_STATUSBLOCK_CH2_Pos)                  /*!< GPDMA1 STATUSBLOCK: CH2 Mask            */\r
+#define GPDMA1_STATUSBLOCK_CH3_Pos            3                                                       /*!< GPDMA1 STATUSBLOCK: CH3 Position        */\r
+#define GPDMA1_STATUSBLOCK_CH3_Msk            (0x01UL << GPDMA1_STATUSBLOCK_CH3_Pos)                  /*!< GPDMA1 STATUSBLOCK: CH3 Mask            */\r
+\r
+/* ----------------------------  GPDMA1_STATUSSRCTRAN  ---------------------------- */\r
+#define GPDMA1_STATUSSRCTRAN_CH0_Pos          0                                                       /*!< GPDMA1 STATUSSRCTRAN: CH0 Position      */\r
+#define GPDMA1_STATUSSRCTRAN_CH0_Msk          (0x01UL << GPDMA1_STATUSSRCTRAN_CH0_Pos)                /*!< GPDMA1 STATUSSRCTRAN: CH0 Mask          */\r
+#define GPDMA1_STATUSSRCTRAN_CH1_Pos          1                                                       /*!< GPDMA1 STATUSSRCTRAN: CH1 Position      */\r
+#define GPDMA1_STATUSSRCTRAN_CH1_Msk          (0x01UL << GPDMA1_STATUSSRCTRAN_CH1_Pos)                /*!< GPDMA1 STATUSSRCTRAN: CH1 Mask          */\r
+#define GPDMA1_STATUSSRCTRAN_CH2_Pos          2                                                       /*!< GPDMA1 STATUSSRCTRAN: CH2 Position      */\r
+#define GPDMA1_STATUSSRCTRAN_CH2_Msk          (0x01UL << GPDMA1_STATUSSRCTRAN_CH2_Pos)                /*!< GPDMA1 STATUSSRCTRAN: CH2 Mask          */\r
+#define GPDMA1_STATUSSRCTRAN_CH3_Pos          3                                                       /*!< GPDMA1 STATUSSRCTRAN: CH3 Position      */\r
+#define GPDMA1_STATUSSRCTRAN_CH3_Msk          (0x01UL << GPDMA1_STATUSSRCTRAN_CH3_Pos)                /*!< GPDMA1 STATUSSRCTRAN: CH3 Mask          */\r
+\r
+/* ----------------------------  GPDMA1_STATUSDSTTRAN  ---------------------------- */\r
+#define GPDMA1_STATUSDSTTRAN_CH0_Pos          0                                                       /*!< GPDMA1 STATUSDSTTRAN: CH0 Position      */\r
+#define GPDMA1_STATUSDSTTRAN_CH0_Msk          (0x01UL << GPDMA1_STATUSDSTTRAN_CH0_Pos)                /*!< GPDMA1 STATUSDSTTRAN: CH0 Mask          */\r
+#define GPDMA1_STATUSDSTTRAN_CH1_Pos          1                                                       /*!< GPDMA1 STATUSDSTTRAN: CH1 Position      */\r
+#define GPDMA1_STATUSDSTTRAN_CH1_Msk          (0x01UL << GPDMA1_STATUSDSTTRAN_CH1_Pos)                /*!< GPDMA1 STATUSDSTTRAN: CH1 Mask          */\r
+#define GPDMA1_STATUSDSTTRAN_CH2_Pos          2                                                       /*!< GPDMA1 STATUSDSTTRAN: CH2 Position      */\r
+#define GPDMA1_STATUSDSTTRAN_CH2_Msk          (0x01UL << GPDMA1_STATUSDSTTRAN_CH2_Pos)                /*!< GPDMA1 STATUSDSTTRAN: CH2 Mask          */\r
+#define GPDMA1_STATUSDSTTRAN_CH3_Pos          3                                                       /*!< GPDMA1 STATUSDSTTRAN: CH3 Position      */\r
+#define GPDMA1_STATUSDSTTRAN_CH3_Msk          (0x01UL << GPDMA1_STATUSDSTTRAN_CH3_Pos)                /*!< GPDMA1 STATUSDSTTRAN: CH3 Mask          */\r
+\r
+/* ------------------------------  GPDMA1_STATUSERR  ------------------------------ */\r
+#define GPDMA1_STATUSERR_CH0_Pos              0                                                       /*!< GPDMA1 STATUSERR: CH0 Position          */\r
+#define GPDMA1_STATUSERR_CH0_Msk              (0x01UL << GPDMA1_STATUSERR_CH0_Pos)                    /*!< GPDMA1 STATUSERR: CH0 Mask              */\r
+#define GPDMA1_STATUSERR_CH1_Pos              1                                                       /*!< GPDMA1 STATUSERR: CH1 Position          */\r
+#define GPDMA1_STATUSERR_CH1_Msk              (0x01UL << GPDMA1_STATUSERR_CH1_Pos)                    /*!< GPDMA1 STATUSERR: CH1 Mask              */\r
+#define GPDMA1_STATUSERR_CH2_Pos              2                                                       /*!< GPDMA1 STATUSERR: CH2 Position          */\r
+#define GPDMA1_STATUSERR_CH2_Msk              (0x01UL << GPDMA1_STATUSERR_CH2_Pos)                    /*!< GPDMA1 STATUSERR: CH2 Mask              */\r
+#define GPDMA1_STATUSERR_CH3_Pos              3                                                       /*!< GPDMA1 STATUSERR: CH3 Position          */\r
+#define GPDMA1_STATUSERR_CH3_Msk              (0x01UL << GPDMA1_STATUSERR_CH3_Pos)                    /*!< GPDMA1 STATUSERR: CH3 Mask              */\r
+\r
+/* -------------------------------  GPDMA1_MASKTFR  ------------------------------- */\r
+#define GPDMA1_MASKTFR_CH0_Pos                0                                                       /*!< GPDMA1 MASKTFR: CH0 Position            */\r
+#define GPDMA1_MASKTFR_CH0_Msk                (0x01UL << GPDMA1_MASKTFR_CH0_Pos)                      /*!< GPDMA1 MASKTFR: CH0 Mask                */\r
+#define GPDMA1_MASKTFR_CH1_Pos                1                                                       /*!< GPDMA1 MASKTFR: CH1 Position            */\r
+#define GPDMA1_MASKTFR_CH1_Msk                (0x01UL << GPDMA1_MASKTFR_CH1_Pos)                      /*!< GPDMA1 MASKTFR: CH1 Mask                */\r
+#define GPDMA1_MASKTFR_CH2_Pos                2                                                       /*!< GPDMA1 MASKTFR: CH2 Position            */\r
+#define GPDMA1_MASKTFR_CH2_Msk                (0x01UL << GPDMA1_MASKTFR_CH2_Pos)                      /*!< GPDMA1 MASKTFR: CH2 Mask                */\r
+#define GPDMA1_MASKTFR_CH3_Pos                3                                                       /*!< GPDMA1 MASKTFR: CH3 Position            */\r
+#define GPDMA1_MASKTFR_CH3_Msk                (0x01UL << GPDMA1_MASKTFR_CH3_Pos)                      /*!< GPDMA1 MASKTFR: CH3 Mask                */\r
+#define GPDMA1_MASKTFR_WE_CH0_Pos             8                                                       /*!< GPDMA1 MASKTFR: WE_CH0 Position         */\r
+#define GPDMA1_MASKTFR_WE_CH0_Msk             (0x01UL << GPDMA1_MASKTFR_WE_CH0_Pos)                   /*!< GPDMA1 MASKTFR: WE_CH0 Mask             */\r
+#define GPDMA1_MASKTFR_WE_CH1_Pos             9                                                       /*!< GPDMA1 MASKTFR: WE_CH1 Position         */\r
+#define GPDMA1_MASKTFR_WE_CH1_Msk             (0x01UL << GPDMA1_MASKTFR_WE_CH1_Pos)                   /*!< GPDMA1 MASKTFR: WE_CH1 Mask             */\r
+#define GPDMA1_MASKTFR_WE_CH2_Pos             10                                                      /*!< GPDMA1 MASKTFR: WE_CH2 Position         */\r
+#define GPDMA1_MASKTFR_WE_CH2_Msk             (0x01UL << GPDMA1_MASKTFR_WE_CH2_Pos)                   /*!< GPDMA1 MASKTFR: WE_CH2 Mask             */\r
+#define GPDMA1_MASKTFR_WE_CH3_Pos             11                                                      /*!< GPDMA1 MASKTFR: WE_CH3 Position         */\r
+#define GPDMA1_MASKTFR_WE_CH3_Msk             (0x01UL << GPDMA1_MASKTFR_WE_CH3_Pos)                   /*!< GPDMA1 MASKTFR: WE_CH3 Mask             */\r
+\r
+/* ------------------------------  GPDMA1_MASKBLOCK  ------------------------------ */\r
+#define GPDMA1_MASKBLOCK_CH0_Pos              0                                                       /*!< GPDMA1 MASKBLOCK: CH0 Position          */\r
+#define GPDMA1_MASKBLOCK_CH0_Msk              (0x01UL << GPDMA1_MASKBLOCK_CH0_Pos)                    /*!< GPDMA1 MASKBLOCK: CH0 Mask              */\r
+#define GPDMA1_MASKBLOCK_CH1_Pos              1                                                       /*!< GPDMA1 MASKBLOCK: CH1 Position          */\r
+#define GPDMA1_MASKBLOCK_CH1_Msk              (0x01UL << GPDMA1_MASKBLOCK_CH1_Pos)                    /*!< GPDMA1 MASKBLOCK: CH1 Mask              */\r
+#define GPDMA1_MASKBLOCK_CH2_Pos              2                                                       /*!< GPDMA1 MASKBLOCK: CH2 Position          */\r
+#define GPDMA1_MASKBLOCK_CH2_Msk              (0x01UL << GPDMA1_MASKBLOCK_CH2_Pos)                    /*!< GPDMA1 MASKBLOCK: CH2 Mask              */\r
+#define GPDMA1_MASKBLOCK_CH3_Pos              3                                                       /*!< GPDMA1 MASKBLOCK: CH3 Position          */\r
+#define GPDMA1_MASKBLOCK_CH3_Msk              (0x01UL << GPDMA1_MASKBLOCK_CH3_Pos)                    /*!< GPDMA1 MASKBLOCK: CH3 Mask              */\r
+#define GPDMA1_MASKBLOCK_WE_CH0_Pos           8                                                       /*!< GPDMA1 MASKBLOCK: WE_CH0 Position       */\r
+#define GPDMA1_MASKBLOCK_WE_CH0_Msk           (0x01UL << GPDMA1_MASKBLOCK_WE_CH0_Pos)                 /*!< GPDMA1 MASKBLOCK: WE_CH0 Mask           */\r
+#define GPDMA1_MASKBLOCK_WE_CH1_Pos           9                                                       /*!< GPDMA1 MASKBLOCK: WE_CH1 Position       */\r
+#define GPDMA1_MASKBLOCK_WE_CH1_Msk           (0x01UL << GPDMA1_MASKBLOCK_WE_CH1_Pos)                 /*!< GPDMA1 MASKBLOCK: WE_CH1 Mask           */\r
+#define GPDMA1_MASKBLOCK_WE_CH2_Pos           10                                                      /*!< GPDMA1 MASKBLOCK: WE_CH2 Position       */\r
+#define GPDMA1_MASKBLOCK_WE_CH2_Msk           (0x01UL << GPDMA1_MASKBLOCK_WE_CH2_Pos)                 /*!< GPDMA1 MASKBLOCK: WE_CH2 Mask           */\r
+#define GPDMA1_MASKBLOCK_WE_CH3_Pos           11                                                      /*!< GPDMA1 MASKBLOCK: WE_CH3 Position       */\r
+#define GPDMA1_MASKBLOCK_WE_CH3_Msk           (0x01UL << GPDMA1_MASKBLOCK_WE_CH3_Pos)                 /*!< GPDMA1 MASKBLOCK: WE_CH3 Mask           */\r
+\r
+/* -----------------------------  GPDMA1_MASKSRCTRAN  ----------------------------- */\r
+#define GPDMA1_MASKSRCTRAN_CH0_Pos            0                                                       /*!< GPDMA1 MASKSRCTRAN: CH0 Position        */\r
+#define GPDMA1_MASKSRCTRAN_CH0_Msk            (0x01UL << GPDMA1_MASKSRCTRAN_CH0_Pos)                  /*!< GPDMA1 MASKSRCTRAN: CH0 Mask            */\r
+#define GPDMA1_MASKSRCTRAN_CH1_Pos            1                                                       /*!< GPDMA1 MASKSRCTRAN: CH1 Position        */\r
+#define GPDMA1_MASKSRCTRAN_CH1_Msk            (0x01UL << GPDMA1_MASKSRCTRAN_CH1_Pos)                  /*!< GPDMA1 MASKSRCTRAN: CH1 Mask            */\r
+#define GPDMA1_MASKSRCTRAN_CH2_Pos            2                                                       /*!< GPDMA1 MASKSRCTRAN: CH2 Position        */\r
+#define GPDMA1_MASKSRCTRAN_CH2_Msk            (0x01UL << GPDMA1_MASKSRCTRAN_CH2_Pos)                  /*!< GPDMA1 MASKSRCTRAN: CH2 Mask            */\r
+#define GPDMA1_MASKSRCTRAN_CH3_Pos            3                                                       /*!< GPDMA1 MASKSRCTRAN: CH3 Position        */\r
+#define GPDMA1_MASKSRCTRAN_CH3_Msk            (0x01UL << GPDMA1_MASKSRCTRAN_CH3_Pos)                  /*!< GPDMA1 MASKSRCTRAN: CH3 Mask            */\r
+#define GPDMA1_MASKSRCTRAN_WE_CH0_Pos         8                                                       /*!< GPDMA1 MASKSRCTRAN: WE_CH0 Position     */\r
+#define GPDMA1_MASKSRCTRAN_WE_CH0_Msk         (0x01UL << GPDMA1_MASKSRCTRAN_WE_CH0_Pos)               /*!< GPDMA1 MASKSRCTRAN: WE_CH0 Mask         */\r
+#define GPDMA1_MASKSRCTRAN_WE_CH1_Pos         9                                                       /*!< GPDMA1 MASKSRCTRAN: WE_CH1 Position     */\r
+#define GPDMA1_MASKSRCTRAN_WE_CH1_Msk         (0x01UL << GPDMA1_MASKSRCTRAN_WE_CH1_Pos)               /*!< GPDMA1 MASKSRCTRAN: WE_CH1 Mask         */\r
+#define GPDMA1_MASKSRCTRAN_WE_CH2_Pos         10                                                      /*!< GPDMA1 MASKSRCTRAN: WE_CH2 Position     */\r
+#define GPDMA1_MASKSRCTRAN_WE_CH2_Msk         (0x01UL << GPDMA1_MASKSRCTRAN_WE_CH2_Pos)               /*!< GPDMA1 MASKSRCTRAN: WE_CH2 Mask         */\r
+#define GPDMA1_MASKSRCTRAN_WE_CH3_Pos         11                                                      /*!< GPDMA1 MASKSRCTRAN: WE_CH3 Position     */\r
+#define GPDMA1_MASKSRCTRAN_WE_CH3_Msk         (0x01UL << GPDMA1_MASKSRCTRAN_WE_CH3_Pos)               /*!< GPDMA1 MASKSRCTRAN: WE_CH3 Mask         */\r
+\r
+/* -----------------------------  GPDMA1_MASKDSTTRAN  ----------------------------- */\r
+#define GPDMA1_MASKDSTTRAN_CH0_Pos            0                                                       /*!< GPDMA1 MASKDSTTRAN: CH0 Position        */\r
+#define GPDMA1_MASKDSTTRAN_CH0_Msk            (0x01UL << GPDMA1_MASKDSTTRAN_CH0_Pos)                  /*!< GPDMA1 MASKDSTTRAN: CH0 Mask            */\r
+#define GPDMA1_MASKDSTTRAN_CH1_Pos            1                                                       /*!< GPDMA1 MASKDSTTRAN: CH1 Position        */\r
+#define GPDMA1_MASKDSTTRAN_CH1_Msk            (0x01UL << GPDMA1_MASKDSTTRAN_CH1_Pos)                  /*!< GPDMA1 MASKDSTTRAN: CH1 Mask            */\r
+#define GPDMA1_MASKDSTTRAN_CH2_Pos            2                                                       /*!< GPDMA1 MASKDSTTRAN: CH2 Position        */\r
+#define GPDMA1_MASKDSTTRAN_CH2_Msk            (0x01UL << GPDMA1_MASKDSTTRAN_CH2_Pos)                  /*!< GPDMA1 MASKDSTTRAN: CH2 Mask            */\r
+#define GPDMA1_MASKDSTTRAN_CH3_Pos            3                                                       /*!< GPDMA1 MASKDSTTRAN: CH3 Position        */\r
+#define GPDMA1_MASKDSTTRAN_CH3_Msk            (0x01UL << GPDMA1_MASKDSTTRAN_CH3_Pos)                  /*!< GPDMA1 MASKDSTTRAN: CH3 Mask            */\r
+#define GPDMA1_MASKDSTTRAN_WE_CH0_Pos         8                                                       /*!< GPDMA1 MASKDSTTRAN: WE_CH0 Position     */\r
+#define GPDMA1_MASKDSTTRAN_WE_CH0_Msk         (0x01UL << GPDMA1_MASKDSTTRAN_WE_CH0_Pos)               /*!< GPDMA1 MASKDSTTRAN: WE_CH0 Mask         */\r
+#define GPDMA1_MASKDSTTRAN_WE_CH1_Pos         9                                                       /*!< GPDMA1 MASKDSTTRAN: WE_CH1 Position     */\r
+#define GPDMA1_MASKDSTTRAN_WE_CH1_Msk         (0x01UL << GPDMA1_MASKDSTTRAN_WE_CH1_Pos)               /*!< GPDMA1 MASKDSTTRAN: WE_CH1 Mask         */\r
+#define GPDMA1_MASKDSTTRAN_WE_CH2_Pos         10                                                      /*!< GPDMA1 MASKDSTTRAN: WE_CH2 Position     */\r
+#define GPDMA1_MASKDSTTRAN_WE_CH2_Msk         (0x01UL << GPDMA1_MASKDSTTRAN_WE_CH2_Pos)               /*!< GPDMA1 MASKDSTTRAN: WE_CH2 Mask         */\r
+#define GPDMA1_MASKDSTTRAN_WE_CH3_Pos         11                                                      /*!< GPDMA1 MASKDSTTRAN: WE_CH3 Position     */\r
+#define GPDMA1_MASKDSTTRAN_WE_CH3_Msk         (0x01UL << GPDMA1_MASKDSTTRAN_WE_CH3_Pos)               /*!< GPDMA1 MASKDSTTRAN: WE_CH3 Mask         */\r
+\r
+/* -------------------------------  GPDMA1_MASKERR  ------------------------------- */\r
+#define GPDMA1_MASKERR_CH0_Pos                0                                                       /*!< GPDMA1 MASKERR: CH0 Position            */\r
+#define GPDMA1_MASKERR_CH0_Msk                (0x01UL << GPDMA1_MASKERR_CH0_Pos)                      /*!< GPDMA1 MASKERR: CH0 Mask                */\r
+#define GPDMA1_MASKERR_CH1_Pos                1                                                       /*!< GPDMA1 MASKERR: CH1 Position            */\r
+#define GPDMA1_MASKERR_CH1_Msk                (0x01UL << GPDMA1_MASKERR_CH1_Pos)                      /*!< GPDMA1 MASKERR: CH1 Mask                */\r
+#define GPDMA1_MASKERR_CH2_Pos                2                                                       /*!< GPDMA1 MASKERR: CH2 Position            */\r
+#define GPDMA1_MASKERR_CH2_Msk                (0x01UL << GPDMA1_MASKERR_CH2_Pos)                      /*!< GPDMA1 MASKERR: CH2 Mask                */\r
+#define GPDMA1_MASKERR_CH3_Pos                3                                                       /*!< GPDMA1 MASKERR: CH3 Position            */\r
+#define GPDMA1_MASKERR_CH3_Msk                (0x01UL << GPDMA1_MASKERR_CH3_Pos)                      /*!< GPDMA1 MASKERR: CH3 Mask                */\r
+#define GPDMA1_MASKERR_WE_CH0_Pos             8                                                       /*!< GPDMA1 MASKERR: WE_CH0 Position         */\r
+#define GPDMA1_MASKERR_WE_CH0_Msk             (0x01UL << GPDMA1_MASKERR_WE_CH0_Pos)                   /*!< GPDMA1 MASKERR: WE_CH0 Mask             */\r
+#define GPDMA1_MASKERR_WE_CH1_Pos             9                                                       /*!< GPDMA1 MASKERR: WE_CH1 Position         */\r
+#define GPDMA1_MASKERR_WE_CH1_Msk             (0x01UL << GPDMA1_MASKERR_WE_CH1_Pos)                   /*!< GPDMA1 MASKERR: WE_CH1 Mask             */\r
+#define GPDMA1_MASKERR_WE_CH2_Pos             10                                                      /*!< GPDMA1 MASKERR: WE_CH2 Position         */\r
+#define GPDMA1_MASKERR_WE_CH2_Msk             (0x01UL << GPDMA1_MASKERR_WE_CH2_Pos)                   /*!< GPDMA1 MASKERR: WE_CH2 Mask             */\r
+#define GPDMA1_MASKERR_WE_CH3_Pos             11                                                      /*!< GPDMA1 MASKERR: WE_CH3 Position         */\r
+#define GPDMA1_MASKERR_WE_CH3_Msk             (0x01UL << GPDMA1_MASKERR_WE_CH3_Pos)                   /*!< GPDMA1 MASKERR: WE_CH3 Mask             */\r
+\r
+/* -------------------------------  GPDMA1_CLEARTFR  ------------------------------ */\r
+#define GPDMA1_CLEARTFR_CH0_Pos               0                                                       /*!< GPDMA1 CLEARTFR: CH0 Position           */\r
+#define GPDMA1_CLEARTFR_CH0_Msk               (0x01UL << GPDMA1_CLEARTFR_CH0_Pos)                     /*!< GPDMA1 CLEARTFR: CH0 Mask               */\r
+#define GPDMA1_CLEARTFR_CH1_Pos               1                                                       /*!< GPDMA1 CLEARTFR: CH1 Position           */\r
+#define GPDMA1_CLEARTFR_CH1_Msk               (0x01UL << GPDMA1_CLEARTFR_CH1_Pos)                     /*!< GPDMA1 CLEARTFR: CH1 Mask               */\r
+#define GPDMA1_CLEARTFR_CH2_Pos               2                                                       /*!< GPDMA1 CLEARTFR: CH2 Position           */\r
+#define GPDMA1_CLEARTFR_CH2_Msk               (0x01UL << GPDMA1_CLEARTFR_CH2_Pos)                     /*!< GPDMA1 CLEARTFR: CH2 Mask               */\r
+#define GPDMA1_CLEARTFR_CH3_Pos               3                                                       /*!< GPDMA1 CLEARTFR: CH3 Position           */\r
+#define GPDMA1_CLEARTFR_CH3_Msk               (0x01UL << GPDMA1_CLEARTFR_CH3_Pos)                     /*!< GPDMA1 CLEARTFR: CH3 Mask               */\r
+\r
+/* ------------------------------  GPDMA1_CLEARBLOCK  ----------------------------- */\r
+#define GPDMA1_CLEARBLOCK_CH0_Pos             0                                                       /*!< GPDMA1 CLEARBLOCK: CH0 Position         */\r
+#define GPDMA1_CLEARBLOCK_CH0_Msk             (0x01UL << GPDMA1_CLEARBLOCK_CH0_Pos)                   /*!< GPDMA1 CLEARBLOCK: CH0 Mask             */\r
+#define GPDMA1_CLEARBLOCK_CH1_Pos             1                                                       /*!< GPDMA1 CLEARBLOCK: CH1 Position         */\r
+#define GPDMA1_CLEARBLOCK_CH1_Msk             (0x01UL << GPDMA1_CLEARBLOCK_CH1_Pos)                   /*!< GPDMA1 CLEARBLOCK: CH1 Mask             */\r
+#define GPDMA1_CLEARBLOCK_CH2_Pos             2                                                       /*!< GPDMA1 CLEARBLOCK: CH2 Position         */\r
+#define GPDMA1_CLEARBLOCK_CH2_Msk             (0x01UL << GPDMA1_CLEARBLOCK_CH2_Pos)                   /*!< GPDMA1 CLEARBLOCK: CH2 Mask             */\r
+#define GPDMA1_CLEARBLOCK_CH3_Pos             3                                                       /*!< GPDMA1 CLEARBLOCK: CH3 Position         */\r
+#define GPDMA1_CLEARBLOCK_CH3_Msk             (0x01UL << GPDMA1_CLEARBLOCK_CH3_Pos)                   /*!< GPDMA1 CLEARBLOCK: CH3 Mask             */\r
+\r
+/* -----------------------------  GPDMA1_CLEARSRCTRAN  ---------------------------- */\r
+#define GPDMA1_CLEARSRCTRAN_CH0_Pos           0                                                       /*!< GPDMA1 CLEARSRCTRAN: CH0 Position       */\r
+#define GPDMA1_CLEARSRCTRAN_CH0_Msk           (0x01UL << GPDMA1_CLEARSRCTRAN_CH0_Pos)                 /*!< GPDMA1 CLEARSRCTRAN: CH0 Mask           */\r
+#define GPDMA1_CLEARSRCTRAN_CH1_Pos           1                                                       /*!< GPDMA1 CLEARSRCTRAN: CH1 Position       */\r
+#define GPDMA1_CLEARSRCTRAN_CH1_Msk           (0x01UL << GPDMA1_CLEARSRCTRAN_CH1_Pos)                 /*!< GPDMA1 CLEARSRCTRAN: CH1 Mask           */\r
+#define GPDMA1_CLEARSRCTRAN_CH2_Pos           2                                                       /*!< GPDMA1 CLEARSRCTRAN: CH2 Position       */\r
+#define GPDMA1_CLEARSRCTRAN_CH2_Msk           (0x01UL << GPDMA1_CLEARSRCTRAN_CH2_Pos)                 /*!< GPDMA1 CLEARSRCTRAN: CH2 Mask           */\r
+#define GPDMA1_CLEARSRCTRAN_CH3_Pos           3                                                       /*!< GPDMA1 CLEARSRCTRAN: CH3 Position       */\r
+#define GPDMA1_CLEARSRCTRAN_CH3_Msk           (0x01UL << GPDMA1_CLEARSRCTRAN_CH3_Pos)                 /*!< GPDMA1 CLEARSRCTRAN: CH3 Mask           */\r
+\r
+/* -----------------------------  GPDMA1_CLEARDSTTRAN  ---------------------------- */\r
+#define GPDMA1_CLEARDSTTRAN_CH0_Pos           0                                                       /*!< GPDMA1 CLEARDSTTRAN: CH0 Position       */\r
+#define GPDMA1_CLEARDSTTRAN_CH0_Msk           (0x01UL << GPDMA1_CLEARDSTTRAN_CH0_Pos)                 /*!< GPDMA1 CLEARDSTTRAN: CH0 Mask           */\r
+#define GPDMA1_CLEARDSTTRAN_CH1_Pos           1                                                       /*!< GPDMA1 CLEARDSTTRAN: CH1 Position       */\r
+#define GPDMA1_CLEARDSTTRAN_CH1_Msk           (0x01UL << GPDMA1_CLEARDSTTRAN_CH1_Pos)                 /*!< GPDMA1 CLEARDSTTRAN: CH1 Mask           */\r
+#define GPDMA1_CLEARDSTTRAN_CH2_Pos           2                                                       /*!< GPDMA1 CLEARDSTTRAN: CH2 Position       */\r
+#define GPDMA1_CLEARDSTTRAN_CH2_Msk           (0x01UL << GPDMA1_CLEARDSTTRAN_CH2_Pos)                 /*!< GPDMA1 CLEARDSTTRAN: CH2 Mask           */\r
+#define GPDMA1_CLEARDSTTRAN_CH3_Pos           3                                                       /*!< GPDMA1 CLEARDSTTRAN: CH3 Position       */\r
+#define GPDMA1_CLEARDSTTRAN_CH3_Msk           (0x01UL << GPDMA1_CLEARDSTTRAN_CH3_Pos)                 /*!< GPDMA1 CLEARDSTTRAN: CH3 Mask           */\r
+\r
+/* -------------------------------  GPDMA1_CLEARERR  ------------------------------ */\r
+#define GPDMA1_CLEARERR_CH0_Pos               0                                                       /*!< GPDMA1 CLEARERR: CH0 Position           */\r
+#define GPDMA1_CLEARERR_CH0_Msk               (0x01UL << GPDMA1_CLEARERR_CH0_Pos)                     /*!< GPDMA1 CLEARERR: CH0 Mask               */\r
+#define GPDMA1_CLEARERR_CH1_Pos               1                                                       /*!< GPDMA1 CLEARERR: CH1 Position           */\r
+#define GPDMA1_CLEARERR_CH1_Msk               (0x01UL << GPDMA1_CLEARERR_CH1_Pos)                     /*!< GPDMA1 CLEARERR: CH1 Mask               */\r
+#define GPDMA1_CLEARERR_CH2_Pos               2                                                       /*!< GPDMA1 CLEARERR: CH2 Position           */\r
+#define GPDMA1_CLEARERR_CH2_Msk               (0x01UL << GPDMA1_CLEARERR_CH2_Pos)                     /*!< GPDMA1 CLEARERR: CH2 Mask               */\r
+#define GPDMA1_CLEARERR_CH3_Pos               3                                                       /*!< GPDMA1 CLEARERR: CH3 Position           */\r
+#define GPDMA1_CLEARERR_CH3_Msk               (0x01UL << GPDMA1_CLEARERR_CH3_Pos)                     /*!< GPDMA1 CLEARERR: CH3 Mask               */\r
+\r
+/* ------------------------------  GPDMA1_STATUSINT  ------------------------------ */\r
+#define GPDMA1_STATUSINT_TFR_Pos              0                                                       /*!< GPDMA1 STATUSINT: TFR Position          */\r
+#define GPDMA1_STATUSINT_TFR_Msk              (0x01UL << GPDMA1_STATUSINT_TFR_Pos)                    /*!< GPDMA1 STATUSINT: TFR Mask              */\r
+#define GPDMA1_STATUSINT_BLOCK_Pos            1                                                       /*!< GPDMA1 STATUSINT: BLOCK Position        */\r
+#define GPDMA1_STATUSINT_BLOCK_Msk            (0x01UL << GPDMA1_STATUSINT_BLOCK_Pos)                  /*!< GPDMA1 STATUSINT: BLOCK Mask            */\r
+#define GPDMA1_STATUSINT_SRCT_Pos             2                                                       /*!< GPDMA1 STATUSINT: SRCT Position         */\r
+#define GPDMA1_STATUSINT_SRCT_Msk             (0x01UL << GPDMA1_STATUSINT_SRCT_Pos)                   /*!< GPDMA1 STATUSINT: SRCT Mask             */\r
+#define GPDMA1_STATUSINT_DSTT_Pos             3                                                       /*!< GPDMA1 STATUSINT: DSTT Position         */\r
+#define GPDMA1_STATUSINT_DSTT_Msk             (0x01UL << GPDMA1_STATUSINT_DSTT_Pos)                   /*!< GPDMA1 STATUSINT: DSTT Mask             */\r
+#define GPDMA1_STATUSINT_ERR_Pos              4                                                       /*!< GPDMA1 STATUSINT: ERR Position          */\r
+#define GPDMA1_STATUSINT_ERR_Msk              (0x01UL << GPDMA1_STATUSINT_ERR_Pos)                    /*!< GPDMA1 STATUSINT: ERR Mask              */\r
+\r
+/* ------------------------------  GPDMA1_REQSRCREG  ------------------------------ */\r
+#define GPDMA1_REQSRCREG_CH0_Pos              0                                                       /*!< GPDMA1 REQSRCREG: CH0 Position          */\r
+#define GPDMA1_REQSRCREG_CH0_Msk              (0x01UL << GPDMA1_REQSRCREG_CH0_Pos)                    /*!< GPDMA1 REQSRCREG: CH0 Mask              */\r
+#define GPDMA1_REQSRCREG_CH1_Pos              1                                                       /*!< GPDMA1 REQSRCREG: CH1 Position          */\r
+#define GPDMA1_REQSRCREG_CH1_Msk              (0x01UL << GPDMA1_REQSRCREG_CH1_Pos)                    /*!< GPDMA1 REQSRCREG: CH1 Mask              */\r
+#define GPDMA1_REQSRCREG_CH2_Pos              2                                                       /*!< GPDMA1 REQSRCREG: CH2 Position          */\r
+#define GPDMA1_REQSRCREG_CH2_Msk              (0x01UL << GPDMA1_REQSRCREG_CH2_Pos)                    /*!< GPDMA1 REQSRCREG: CH2 Mask              */\r
+#define GPDMA1_REQSRCREG_CH3_Pos              3                                                       /*!< GPDMA1 REQSRCREG: CH3 Position          */\r
+#define GPDMA1_REQSRCREG_CH3_Msk              (0x01UL << GPDMA1_REQSRCREG_CH3_Pos)                    /*!< GPDMA1 REQSRCREG: CH3 Mask              */\r
+#define GPDMA1_REQSRCREG_WE_CH0_Pos           8                                                       /*!< GPDMA1 REQSRCREG: WE_CH0 Position       */\r
+#define GPDMA1_REQSRCREG_WE_CH0_Msk           (0x01UL << GPDMA1_REQSRCREG_WE_CH0_Pos)                 /*!< GPDMA1 REQSRCREG: WE_CH0 Mask           */\r
+#define GPDMA1_REQSRCREG_WE_CH1_Pos           9                                                       /*!< GPDMA1 REQSRCREG: WE_CH1 Position       */\r
+#define GPDMA1_REQSRCREG_WE_CH1_Msk           (0x01UL << GPDMA1_REQSRCREG_WE_CH1_Pos)                 /*!< GPDMA1 REQSRCREG: WE_CH1 Mask           */\r
+#define GPDMA1_REQSRCREG_WE_CH2_Pos           10                                                      /*!< GPDMA1 REQSRCREG: WE_CH2 Position       */\r
+#define GPDMA1_REQSRCREG_WE_CH2_Msk           (0x01UL << GPDMA1_REQSRCREG_WE_CH2_Pos)                 /*!< GPDMA1 REQSRCREG: WE_CH2 Mask           */\r
+#define GPDMA1_REQSRCREG_WE_CH3_Pos           11                                                      /*!< GPDMA1 REQSRCREG: WE_CH3 Position       */\r
+#define GPDMA1_REQSRCREG_WE_CH3_Msk           (0x01UL << GPDMA1_REQSRCREG_WE_CH3_Pos)                 /*!< GPDMA1 REQSRCREG: WE_CH3 Mask           */\r
+\r
+/* ------------------------------  GPDMA1_REQDSTREG  ------------------------------ */\r
+#define GPDMA1_REQDSTREG_CH0_Pos              0                                                       /*!< GPDMA1 REQDSTREG: CH0 Position          */\r
+#define GPDMA1_REQDSTREG_CH0_Msk              (0x01UL << GPDMA1_REQDSTREG_CH0_Pos)                    /*!< GPDMA1 REQDSTREG: CH0 Mask              */\r
+#define GPDMA1_REQDSTREG_CH1_Pos              1                                                       /*!< GPDMA1 REQDSTREG: CH1 Position          */\r
+#define GPDMA1_REQDSTREG_CH1_Msk              (0x01UL << GPDMA1_REQDSTREG_CH1_Pos)                    /*!< GPDMA1 REQDSTREG: CH1 Mask              */\r
+#define GPDMA1_REQDSTREG_CH2_Pos              2                                                       /*!< GPDMA1 REQDSTREG: CH2 Position          */\r
+#define GPDMA1_REQDSTREG_CH2_Msk              (0x01UL << GPDMA1_REQDSTREG_CH2_Pos)                    /*!< GPDMA1 REQDSTREG: CH2 Mask              */\r
+#define GPDMA1_REQDSTREG_CH3_Pos              3                                                       /*!< GPDMA1 REQDSTREG: CH3 Position          */\r
+#define GPDMA1_REQDSTREG_CH3_Msk              (0x01UL << GPDMA1_REQDSTREG_CH3_Pos)                    /*!< GPDMA1 REQDSTREG: CH3 Mask              */\r
+#define GPDMA1_REQDSTREG_WE_CH0_Pos           8                                                       /*!< GPDMA1 REQDSTREG: WE_CH0 Position       */\r
+#define GPDMA1_REQDSTREG_WE_CH0_Msk           (0x01UL << GPDMA1_REQDSTREG_WE_CH0_Pos)                 /*!< GPDMA1 REQDSTREG: WE_CH0 Mask           */\r
+#define GPDMA1_REQDSTREG_WE_CH1_Pos           9                                                       /*!< GPDMA1 REQDSTREG: WE_CH1 Position       */\r
+#define GPDMA1_REQDSTREG_WE_CH1_Msk           (0x01UL << GPDMA1_REQDSTREG_WE_CH1_Pos)                 /*!< GPDMA1 REQDSTREG: WE_CH1 Mask           */\r
+#define GPDMA1_REQDSTREG_WE_CH2_Pos           10                                                      /*!< GPDMA1 REQDSTREG: WE_CH2 Position       */\r
+#define GPDMA1_REQDSTREG_WE_CH2_Msk           (0x01UL << GPDMA1_REQDSTREG_WE_CH2_Pos)                 /*!< GPDMA1 REQDSTREG: WE_CH2 Mask           */\r
+#define GPDMA1_REQDSTREG_WE_CH3_Pos           11                                                      /*!< GPDMA1 REQDSTREG: WE_CH3 Position       */\r
+#define GPDMA1_REQDSTREG_WE_CH3_Msk           (0x01UL << GPDMA1_REQDSTREG_WE_CH3_Pos)                 /*!< GPDMA1 REQDSTREG: WE_CH3 Mask           */\r
+\r
+/* -----------------------------  GPDMA1_SGLREQSRCREG  ---------------------------- */\r
+#define GPDMA1_SGLREQSRCREG_CH0_Pos           0                                                       /*!< GPDMA1 SGLREQSRCREG: CH0 Position       */\r
+#define GPDMA1_SGLREQSRCREG_CH0_Msk           (0x01UL << GPDMA1_SGLREQSRCREG_CH0_Pos)                 /*!< GPDMA1 SGLREQSRCREG: CH0 Mask           */\r
+#define GPDMA1_SGLREQSRCREG_CH1_Pos           1                                                       /*!< GPDMA1 SGLREQSRCREG: CH1 Position       */\r
+#define GPDMA1_SGLREQSRCREG_CH1_Msk           (0x01UL << GPDMA1_SGLREQSRCREG_CH1_Pos)                 /*!< GPDMA1 SGLREQSRCREG: CH1 Mask           */\r
+#define GPDMA1_SGLREQSRCREG_CH2_Pos           2                                                       /*!< GPDMA1 SGLREQSRCREG: CH2 Position       */\r
+#define GPDMA1_SGLREQSRCREG_CH2_Msk           (0x01UL << GPDMA1_SGLREQSRCREG_CH2_Pos)                 /*!< GPDMA1 SGLREQSRCREG: CH2 Mask           */\r
+#define GPDMA1_SGLREQSRCREG_CH3_Pos           3                                                       /*!< GPDMA1 SGLREQSRCREG: CH3 Position       */\r
+#define GPDMA1_SGLREQSRCREG_CH3_Msk           (0x01UL << GPDMA1_SGLREQSRCREG_CH3_Pos)                 /*!< GPDMA1 SGLREQSRCREG: CH3 Mask           */\r
+#define GPDMA1_SGLREQSRCREG_WE_CH0_Pos        8                                                       /*!< GPDMA1 SGLREQSRCREG: WE_CH0 Position    */\r
+#define GPDMA1_SGLREQSRCREG_WE_CH0_Msk        (0x01UL << GPDMA1_SGLREQSRCREG_WE_CH0_Pos)              /*!< GPDMA1 SGLREQSRCREG: WE_CH0 Mask        */\r
+#define GPDMA1_SGLREQSRCREG_WE_CH1_Pos        9                                                       /*!< GPDMA1 SGLREQSRCREG: WE_CH1 Position    */\r
+#define GPDMA1_SGLREQSRCREG_WE_CH1_Msk        (0x01UL << GPDMA1_SGLREQSRCREG_WE_CH1_Pos)              /*!< GPDMA1 SGLREQSRCREG: WE_CH1 Mask        */\r
+#define GPDMA1_SGLREQSRCREG_WE_CH2_Pos        10                                                      /*!< GPDMA1 SGLREQSRCREG: WE_CH2 Position    */\r
+#define GPDMA1_SGLREQSRCREG_WE_CH2_Msk        (0x01UL << GPDMA1_SGLREQSRCREG_WE_CH2_Pos)              /*!< GPDMA1 SGLREQSRCREG: WE_CH2 Mask        */\r
+#define GPDMA1_SGLREQSRCREG_WE_CH3_Pos        11                                                      /*!< GPDMA1 SGLREQSRCREG: WE_CH3 Position    */\r
+#define GPDMA1_SGLREQSRCREG_WE_CH3_Msk        (0x01UL << GPDMA1_SGLREQSRCREG_WE_CH3_Pos)              /*!< GPDMA1 SGLREQSRCREG: WE_CH3 Mask        */\r
+\r
+/* -----------------------------  GPDMA1_SGLREQDSTREG  ---------------------------- */\r
+#define GPDMA1_SGLREQDSTREG_CH0_Pos           0                                                       /*!< GPDMA1 SGLREQDSTREG: CH0 Position       */\r
+#define GPDMA1_SGLREQDSTREG_CH0_Msk           (0x01UL << GPDMA1_SGLREQDSTREG_CH0_Pos)                 /*!< GPDMA1 SGLREQDSTREG: CH0 Mask           */\r
+#define GPDMA1_SGLREQDSTREG_CH1_Pos           1                                                       /*!< GPDMA1 SGLREQDSTREG: CH1 Position       */\r
+#define GPDMA1_SGLREQDSTREG_CH1_Msk           (0x01UL << GPDMA1_SGLREQDSTREG_CH1_Pos)                 /*!< GPDMA1 SGLREQDSTREG: CH1 Mask           */\r
+#define GPDMA1_SGLREQDSTREG_CH2_Pos           2                                                       /*!< GPDMA1 SGLREQDSTREG: CH2 Position       */\r
+#define GPDMA1_SGLREQDSTREG_CH2_Msk           (0x01UL << GPDMA1_SGLREQDSTREG_CH2_Pos)                 /*!< GPDMA1 SGLREQDSTREG: CH2 Mask           */\r
+#define GPDMA1_SGLREQDSTREG_CH3_Pos           3                                                       /*!< GPDMA1 SGLREQDSTREG: CH3 Position       */\r
+#define GPDMA1_SGLREQDSTREG_CH3_Msk           (0x01UL << GPDMA1_SGLREQDSTREG_CH3_Pos)                 /*!< GPDMA1 SGLREQDSTREG: CH3 Mask           */\r
+#define GPDMA1_SGLREQDSTREG_WE_CH0_Pos        8                                                       /*!< GPDMA1 SGLREQDSTREG: WE_CH0 Position    */\r
+#define GPDMA1_SGLREQDSTREG_WE_CH0_Msk        (0x01UL << GPDMA1_SGLREQDSTREG_WE_CH0_Pos)              /*!< GPDMA1 SGLREQDSTREG: WE_CH0 Mask        */\r
+#define GPDMA1_SGLREQDSTREG_WE_CH1_Pos        9                                                       /*!< GPDMA1 SGLREQDSTREG: WE_CH1 Position    */\r
+#define GPDMA1_SGLREQDSTREG_WE_CH1_Msk        (0x01UL << GPDMA1_SGLREQDSTREG_WE_CH1_Pos)              /*!< GPDMA1 SGLREQDSTREG: WE_CH1 Mask        */\r
+#define GPDMA1_SGLREQDSTREG_WE_CH2_Pos        10                                                      /*!< GPDMA1 SGLREQDSTREG: WE_CH2 Position    */\r
+#define GPDMA1_SGLREQDSTREG_WE_CH2_Msk        (0x01UL << GPDMA1_SGLREQDSTREG_WE_CH2_Pos)              /*!< GPDMA1 SGLREQDSTREG: WE_CH2 Mask        */\r
+#define GPDMA1_SGLREQDSTREG_WE_CH3_Pos        11                                                      /*!< GPDMA1 SGLREQDSTREG: WE_CH3 Position    */\r
+#define GPDMA1_SGLREQDSTREG_WE_CH3_Msk        (0x01UL << GPDMA1_SGLREQDSTREG_WE_CH3_Pos)              /*!< GPDMA1 SGLREQDSTREG: WE_CH3 Mask        */\r
+\r
+/* ------------------------------  GPDMA1_LSTSRCREG  ------------------------------ */\r
+#define GPDMA1_LSTSRCREG_CH0_Pos              0                                                       /*!< GPDMA1 LSTSRCREG: CH0 Position          */\r
+#define GPDMA1_LSTSRCREG_CH0_Msk              (0x01UL << GPDMA1_LSTSRCREG_CH0_Pos)                    /*!< GPDMA1 LSTSRCREG: CH0 Mask              */\r
+#define GPDMA1_LSTSRCREG_CH1_Pos              1                                                       /*!< GPDMA1 LSTSRCREG: CH1 Position          */\r
+#define GPDMA1_LSTSRCREG_CH1_Msk              (0x01UL << GPDMA1_LSTSRCREG_CH1_Pos)                    /*!< GPDMA1 LSTSRCREG: CH1 Mask              */\r
+#define GPDMA1_LSTSRCREG_CH2_Pos              2                                                       /*!< GPDMA1 LSTSRCREG: CH2 Position          */\r
+#define GPDMA1_LSTSRCREG_CH2_Msk              (0x01UL << GPDMA1_LSTSRCREG_CH2_Pos)                    /*!< GPDMA1 LSTSRCREG: CH2 Mask              */\r
+#define GPDMA1_LSTSRCREG_CH3_Pos              3                                                       /*!< GPDMA1 LSTSRCREG: CH3 Position          */\r
+#define GPDMA1_LSTSRCREG_CH3_Msk              (0x01UL << GPDMA1_LSTSRCREG_CH3_Pos)                    /*!< GPDMA1 LSTSRCREG: CH3 Mask              */\r
+#define GPDMA1_LSTSRCREG_WE_CH0_Pos           8                                                       /*!< GPDMA1 LSTSRCREG: WE_CH0 Position       */\r
+#define GPDMA1_LSTSRCREG_WE_CH0_Msk           (0x01UL << GPDMA1_LSTSRCREG_WE_CH0_Pos)                 /*!< GPDMA1 LSTSRCREG: WE_CH0 Mask           */\r
+#define GPDMA1_LSTSRCREG_WE_CH1_Pos           9                                                       /*!< GPDMA1 LSTSRCREG: WE_CH1 Position       */\r
+#define GPDMA1_LSTSRCREG_WE_CH1_Msk           (0x01UL << GPDMA1_LSTSRCREG_WE_CH1_Pos)                 /*!< GPDMA1 LSTSRCREG: WE_CH1 Mask           */\r
+#define GPDMA1_LSTSRCREG_WE_CH2_Pos           10                                                      /*!< GPDMA1 LSTSRCREG: WE_CH2 Position       */\r
+#define GPDMA1_LSTSRCREG_WE_CH2_Msk           (0x01UL << GPDMA1_LSTSRCREG_WE_CH2_Pos)                 /*!< GPDMA1 LSTSRCREG: WE_CH2 Mask           */\r
+#define GPDMA1_LSTSRCREG_WE_CH3_Pos           11                                                      /*!< GPDMA1 LSTSRCREG: WE_CH3 Position       */\r
+#define GPDMA1_LSTSRCREG_WE_CH3_Msk           (0x01UL << GPDMA1_LSTSRCREG_WE_CH3_Pos)                 /*!< GPDMA1 LSTSRCREG: WE_CH3 Mask           */\r
+\r
+/* ------------------------------  GPDMA1_LSTDSTREG  ------------------------------ */\r
+#define GPDMA1_LSTDSTREG_CH0_Pos              0                                                       /*!< GPDMA1 LSTDSTREG: CH0 Position          */\r
+#define GPDMA1_LSTDSTREG_CH0_Msk              (0x01UL << GPDMA1_LSTDSTREG_CH0_Pos)                    /*!< GPDMA1 LSTDSTREG: CH0 Mask              */\r
+#define GPDMA1_LSTDSTREG_CH1_Pos              1                                                       /*!< GPDMA1 LSTDSTREG: CH1 Position          */\r
+#define GPDMA1_LSTDSTREG_CH1_Msk              (0x01UL << GPDMA1_LSTDSTREG_CH1_Pos)                    /*!< GPDMA1 LSTDSTREG: CH1 Mask              */\r
+#define GPDMA1_LSTDSTREG_CH2_Pos              2                                                       /*!< GPDMA1 LSTDSTREG: CH2 Position          */\r
+#define GPDMA1_LSTDSTREG_CH2_Msk              (0x01UL << GPDMA1_LSTDSTREG_CH2_Pos)                    /*!< GPDMA1 LSTDSTREG: CH2 Mask              */\r
+#define GPDMA1_LSTDSTREG_CH3_Pos              3                                                       /*!< GPDMA1 LSTDSTREG: CH3 Position          */\r
+#define GPDMA1_LSTDSTREG_CH3_Msk              (0x01UL << GPDMA1_LSTDSTREG_CH3_Pos)                    /*!< GPDMA1 LSTDSTREG: CH3 Mask              */\r
+#define GPDMA1_LSTDSTREG_WE_CH0_Pos           8                                                       /*!< GPDMA1 LSTDSTREG: WE_CH0 Position       */\r
+#define GPDMA1_LSTDSTREG_WE_CH0_Msk           (0x01UL << GPDMA1_LSTDSTREG_WE_CH0_Pos)                 /*!< GPDMA1 LSTDSTREG: WE_CH0 Mask           */\r
+#define GPDMA1_LSTDSTREG_WE_CH1_Pos           9                                                       /*!< GPDMA1 LSTDSTREG: WE_CH1 Position       */\r
+#define GPDMA1_LSTDSTREG_WE_CH1_Msk           (0x01UL << GPDMA1_LSTDSTREG_WE_CH1_Pos)                 /*!< GPDMA1 LSTDSTREG: WE_CH1 Mask           */\r
+#define GPDMA1_LSTDSTREG_WE_CH2_Pos           10                                                      /*!< GPDMA1 LSTDSTREG: WE_CH2 Position       */\r
+#define GPDMA1_LSTDSTREG_WE_CH2_Msk           (0x01UL << GPDMA1_LSTDSTREG_WE_CH2_Pos)                 /*!< GPDMA1 LSTDSTREG: WE_CH2 Mask           */\r
+#define GPDMA1_LSTDSTREG_WE_CH3_Pos           11                                                      /*!< GPDMA1 LSTDSTREG: WE_CH3 Position       */\r
+#define GPDMA1_LSTDSTREG_WE_CH3_Msk           (0x01UL << GPDMA1_LSTDSTREG_WE_CH3_Pos)                 /*!< GPDMA1 LSTDSTREG: WE_CH3 Mask           */\r
+\r
+/* ------------------------------  GPDMA1_DMACFGREG  ------------------------------ */\r
+#define GPDMA1_DMACFGREG_DMA_EN_Pos           0                                                       /*!< GPDMA1 DMACFGREG: DMA_EN Position       */\r
+#define GPDMA1_DMACFGREG_DMA_EN_Msk           (0x01UL << GPDMA1_DMACFGREG_DMA_EN_Pos)                 /*!< GPDMA1 DMACFGREG: DMA_EN Mask           */\r
+\r
+/* -------------------------------  GPDMA1_CHENREG  ------------------------------- */\r
+#define GPDMA1_CHENREG_CH_Pos                 0                                                       /*!< GPDMA1 CHENREG: CH Position             */\r
+#define GPDMA1_CHENREG_CH_Msk                 (0x0fUL << GPDMA1_CHENREG_CH_Pos)                       /*!< GPDMA1 CHENREG: CH Mask                 */\r
+#define GPDMA1_CHENREG_WE_CH_Pos              8                                                       /*!< GPDMA1 CHENREG: WE_CH Position          */\r
+#define GPDMA1_CHENREG_WE_CH_Msk              (0x0fUL << GPDMA1_CHENREG_WE_CH_Pos)                    /*!< GPDMA1 CHENREG: WE_CH Mask              */\r
+\r
+/* ----------------------------------  GPDMA1_ID  --------------------------------- */\r
+#define GPDMA1_ID_VALUE_Pos                   0                                                       /*!< GPDMA1 ID: VALUE Position               */\r
+#define GPDMA1_ID_VALUE_Msk                   (0xffffffffUL << GPDMA1_ID_VALUE_Pos)                   /*!< GPDMA1 ID: VALUE Mask                   */\r
+\r
+/* ---------------------------------  GPDMA1_TYPE  -------------------------------- */\r
+#define GPDMA1_TYPE_VALUE_Pos                 0                                                       /*!< GPDMA1 TYPE: VALUE Position             */\r
+#define GPDMA1_TYPE_VALUE_Msk                 (0xffffffffUL << GPDMA1_TYPE_VALUE_Pos)                 /*!< GPDMA1 TYPE: VALUE Mask                 */\r
+\r
+/* -------------------------------  GPDMA1_VERSION  ------------------------------- */\r
+#define GPDMA1_VERSION_VALUE_Pos              0                                                       /*!< GPDMA1 VERSION: VALUE Position          */\r
+#define GPDMA1_VERSION_VALUE_Msk              (0xffffffffUL << GPDMA1_VERSION_VALUE_Pos)              /*!< GPDMA1 VERSION: VALUE Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        Group 'GPDMA1_CH' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  GPDMA1_CH_SAR  ------------------------------- */\r
+#define GPDMA1_CH_SAR_SAR_Pos                 0                                                       /*!< GPDMA1_CH SAR: SAR Position             */\r
+#define GPDMA1_CH_SAR_SAR_Msk                 (0xffffffffUL << GPDMA1_CH_SAR_SAR_Pos)                 /*!< GPDMA1_CH SAR: SAR Mask                 */\r
+\r
+/* --------------------------------  GPDMA1_CH_DAR  ------------------------------- */\r
+#define GPDMA1_CH_DAR_DAR_Pos                 0                                                       /*!< GPDMA1_CH DAR: DAR Position             */\r
+#define GPDMA1_CH_DAR_DAR_Msk                 (0xffffffffUL << GPDMA1_CH_DAR_DAR_Pos)                 /*!< GPDMA1_CH DAR: DAR Mask                 */\r
+\r
+/* -------------------------------  GPDMA1_CH_CTLL  ------------------------------- */\r
+#define GPDMA1_CH_CTLL_INT_EN_Pos             0                                                       /*!< GPDMA1_CH CTLL: INT_EN Position         */\r
+#define GPDMA1_CH_CTLL_INT_EN_Msk             (0x01UL << GPDMA1_CH_CTLL_INT_EN_Pos)                   /*!< GPDMA1_CH CTLL: INT_EN Mask             */\r
+#define GPDMA1_CH_CTLL_DST_TR_WIDTH_Pos       1                                                       /*!< GPDMA1_CH CTLL: DST_TR_WIDTH Position   */\r
+#define GPDMA1_CH_CTLL_DST_TR_WIDTH_Msk       (0x07UL << GPDMA1_CH_CTLL_DST_TR_WIDTH_Pos)             /*!< GPDMA1_CH CTLL: DST_TR_WIDTH Mask       */\r
+#define GPDMA1_CH_CTLL_SRC_TR_WIDTH_Pos       4                                                       /*!< GPDMA1_CH CTLL: SRC_TR_WIDTH Position   */\r
+#define GPDMA1_CH_CTLL_SRC_TR_WIDTH_Msk       (0x07UL << GPDMA1_CH_CTLL_SRC_TR_WIDTH_Pos)             /*!< GPDMA1_CH CTLL: SRC_TR_WIDTH Mask       */\r
+#define GPDMA1_CH_CTLL_DINC_Pos               7                                                       /*!< GPDMA1_CH CTLL: DINC Position           */\r
+#define GPDMA1_CH_CTLL_DINC_Msk               (0x03UL << GPDMA1_CH_CTLL_DINC_Pos)                     /*!< GPDMA1_CH CTLL: DINC Mask               */\r
+#define GPDMA1_CH_CTLL_SINC_Pos               9                                                       /*!< GPDMA1_CH CTLL: SINC Position           */\r
+#define GPDMA1_CH_CTLL_SINC_Msk               (0x03UL << GPDMA1_CH_CTLL_SINC_Pos)                     /*!< GPDMA1_CH CTLL: SINC Mask               */\r
+#define GPDMA1_CH_CTLL_DEST_MSIZE_Pos         11                                                      /*!< GPDMA1_CH CTLL: DEST_MSIZE Position     */\r
+#define GPDMA1_CH_CTLL_DEST_MSIZE_Msk         (0x07UL << GPDMA1_CH_CTLL_DEST_MSIZE_Pos)               /*!< GPDMA1_CH CTLL: DEST_MSIZE Mask         */\r
+#define GPDMA1_CH_CTLL_SRC_MSIZE_Pos          14                                                      /*!< GPDMA1_CH CTLL: SRC_MSIZE Position      */\r
+#define GPDMA1_CH_CTLL_SRC_MSIZE_Msk          (0x07UL << GPDMA1_CH_CTLL_SRC_MSIZE_Pos)                /*!< GPDMA1_CH CTLL: SRC_MSIZE Mask          */\r
+#define GPDMA1_CH_CTLL_TT_FC_Pos              20                                                      /*!< GPDMA1_CH CTLL: TT_FC Position          */\r
+#define GPDMA1_CH_CTLL_TT_FC_Msk              (0x07UL << GPDMA1_CH_CTLL_TT_FC_Pos)                    /*!< GPDMA1_CH CTLL: TT_FC Mask              */\r
+\r
+/* -------------------------------  GPDMA1_CH_CTLH  ------------------------------- */\r
+#define GPDMA1_CH_CTLH_BLOCK_TS_Pos           0                                                       /*!< GPDMA1_CH CTLH: BLOCK_TS Position       */\r
+#define GPDMA1_CH_CTLH_BLOCK_TS_Msk           (0x00000fffUL << GPDMA1_CH_CTLH_BLOCK_TS_Pos)           /*!< GPDMA1_CH CTLH: BLOCK_TS Mask           */\r
+#define GPDMA1_CH_CTLH_DONE_Pos               12                                                      /*!< GPDMA1_CH CTLH: DONE Position           */\r
+#define GPDMA1_CH_CTLH_DONE_Msk               (0x01UL << GPDMA1_CH_CTLH_DONE_Pos)                     /*!< GPDMA1_CH CTLH: DONE Mask               */\r
+\r
+/* -------------------------------  GPDMA1_CH_CFGL  ------------------------------- */\r
+#define GPDMA1_CH_CFGL_CH_PRIOR_Pos           5                                                       /*!< GPDMA1_CH CFGL: CH_PRIOR Position       */\r
+#define GPDMA1_CH_CFGL_CH_PRIOR_Msk           (0x07UL << GPDMA1_CH_CFGL_CH_PRIOR_Pos)                 /*!< GPDMA1_CH CFGL: CH_PRIOR Mask           */\r
+#define GPDMA1_CH_CFGL_CH_SUSP_Pos            8                                                       /*!< GPDMA1_CH CFGL: CH_SUSP Position        */\r
+#define GPDMA1_CH_CFGL_CH_SUSP_Msk            (0x01UL << GPDMA1_CH_CFGL_CH_SUSP_Pos)                  /*!< GPDMA1_CH CFGL: CH_SUSP Mask            */\r
+#define GPDMA1_CH_CFGL_FIFO_EMPTY_Pos         9                                                       /*!< GPDMA1_CH CFGL: FIFO_EMPTY Position     */\r
+#define GPDMA1_CH_CFGL_FIFO_EMPTY_Msk         (0x01UL << GPDMA1_CH_CFGL_FIFO_EMPTY_Pos)               /*!< GPDMA1_CH CFGL: FIFO_EMPTY Mask         */\r
+#define GPDMA1_CH_CFGL_HS_SEL_DST_Pos         10                                                      /*!< GPDMA1_CH CFGL: HS_SEL_DST Position     */\r
+#define GPDMA1_CH_CFGL_HS_SEL_DST_Msk         (0x01UL << GPDMA1_CH_CFGL_HS_SEL_DST_Pos)               /*!< GPDMA1_CH CFGL: HS_SEL_DST Mask         */\r
+#define GPDMA1_CH_CFGL_HS_SEL_SRC_Pos         11                                                      /*!< GPDMA1_CH CFGL: HS_SEL_SRC Position     */\r
+#define GPDMA1_CH_CFGL_HS_SEL_SRC_Msk         (0x01UL << GPDMA1_CH_CFGL_HS_SEL_SRC_Pos)               /*!< GPDMA1_CH CFGL: HS_SEL_SRC Mask         */\r
+#define GPDMA1_CH_CFGL_LOCK_CH_L_Pos          12                                                      /*!< GPDMA1_CH CFGL: LOCK_CH_L Position      */\r
+#define GPDMA1_CH_CFGL_LOCK_CH_L_Msk          (0x03UL << GPDMA1_CH_CFGL_LOCK_CH_L_Pos)                /*!< GPDMA1_CH CFGL: LOCK_CH_L Mask          */\r
+#define GPDMA1_CH_CFGL_LOCK_B_L_Pos           14                                                      /*!< GPDMA1_CH CFGL: LOCK_B_L Position       */\r
+#define GPDMA1_CH_CFGL_LOCK_B_L_Msk           (0x03UL << GPDMA1_CH_CFGL_LOCK_B_L_Pos)                 /*!< GPDMA1_CH CFGL: LOCK_B_L Mask           */\r
+#define GPDMA1_CH_CFGL_LOCK_CH_Pos            16                                                      /*!< GPDMA1_CH CFGL: LOCK_CH Position        */\r
+#define GPDMA1_CH_CFGL_LOCK_CH_Msk            (0x01UL << GPDMA1_CH_CFGL_LOCK_CH_Pos)                  /*!< GPDMA1_CH CFGL: LOCK_CH Mask            */\r
+#define GPDMA1_CH_CFGL_LOCK_B_Pos             17                                                      /*!< GPDMA1_CH CFGL: LOCK_B Position         */\r
+#define GPDMA1_CH_CFGL_LOCK_B_Msk             (0x01UL << GPDMA1_CH_CFGL_LOCK_B_Pos)                   /*!< GPDMA1_CH CFGL: LOCK_B Mask             */\r
+#define GPDMA1_CH_CFGL_DST_HS_POL_Pos         18                                                      /*!< GPDMA1_CH CFGL: DST_HS_POL Position     */\r
+#define GPDMA1_CH_CFGL_DST_HS_POL_Msk         (0x01UL << GPDMA1_CH_CFGL_DST_HS_POL_Pos)               /*!< GPDMA1_CH CFGL: DST_HS_POL Mask         */\r
+#define GPDMA1_CH_CFGL_SRC_HS_POL_Pos         19                                                      /*!< GPDMA1_CH CFGL: SRC_HS_POL Position     */\r
+#define GPDMA1_CH_CFGL_SRC_HS_POL_Msk         (0x01UL << GPDMA1_CH_CFGL_SRC_HS_POL_Pos)               /*!< GPDMA1_CH CFGL: SRC_HS_POL Mask         */\r
+#define GPDMA1_CH_CFGL_MAX_ABRST_Pos          20                                                      /*!< GPDMA1_CH CFGL: MAX_ABRST Position      */\r
+#define GPDMA1_CH_CFGL_MAX_ABRST_Msk          (0x000003ffUL << GPDMA1_CH_CFGL_MAX_ABRST_Pos)          /*!< GPDMA1_CH CFGL: MAX_ABRST Mask          */\r
+\r
+/* -------------------------------  GPDMA1_CH_CFGH  ------------------------------- */\r
+#define GPDMA1_CH_CFGH_FCMODE_Pos             0                                                       /*!< GPDMA1_CH CFGH: FCMODE Position         */\r
+#define GPDMA1_CH_CFGH_FCMODE_Msk             (0x01UL << GPDMA1_CH_CFGH_FCMODE_Pos)                   /*!< GPDMA1_CH CFGH: FCMODE Mask             */\r
+#define GPDMA1_CH_CFGH_FIFO_MODE_Pos          1                                                       /*!< GPDMA1_CH CFGH: FIFO_MODE Position      */\r
+#define GPDMA1_CH_CFGH_FIFO_MODE_Msk          (0x01UL << GPDMA1_CH_CFGH_FIFO_MODE_Pos)                /*!< GPDMA1_CH CFGH: FIFO_MODE Mask          */\r
+#define GPDMA1_CH_CFGH_PROTCTL_Pos            2                                                       /*!< GPDMA1_CH CFGH: PROTCTL Position        */\r
+#define GPDMA1_CH_CFGH_PROTCTL_Msk            (0x07UL << GPDMA1_CH_CFGH_PROTCTL_Pos)                  /*!< GPDMA1_CH CFGH: PROTCTL Mask            */\r
+#define GPDMA1_CH_CFGH_SRC_PER_Pos            7                                                       /*!< GPDMA1_CH CFGH: SRC_PER Position        */\r
+#define GPDMA1_CH_CFGH_SRC_PER_Msk            (0x0fUL << GPDMA1_CH_CFGH_SRC_PER_Pos)                  /*!< GPDMA1_CH CFGH: SRC_PER Mask            */\r
+#define GPDMA1_CH_CFGH_DEST_PER_Pos           11                                                      /*!< GPDMA1_CH CFGH: DEST_PER Position       */\r
+#define GPDMA1_CH_CFGH_DEST_PER_Msk           (0x0fUL << GPDMA1_CH_CFGH_DEST_PER_Pos)                 /*!< GPDMA1_CH CFGH: DEST_PER Mask           */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'FCE' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  FCE_CLC  ---------------------------------- */\r
+#define FCE_CLC_DISR_Pos                      0                                                       /*!< FCE CLC: DISR Position                  */\r
+#define FCE_CLC_DISR_Msk                      (0x01UL << FCE_CLC_DISR_Pos)                            /*!< FCE CLC: DISR Mask                      */\r
+#define FCE_CLC_DISS_Pos                      1                                                       /*!< FCE CLC: DISS Position                  */\r
+#define FCE_CLC_DISS_Msk                      (0x01UL << FCE_CLC_DISS_Pos)                            /*!< FCE CLC: DISS Mask                      */\r
+\r
+/* -----------------------------------  FCE_ID  ----------------------------------- */\r
+#define FCE_ID_MOD_REV_Pos                    0                                                       /*!< FCE ID: MOD_REV Position                */\r
+#define FCE_ID_MOD_REV_Msk                    (0x000000ffUL << FCE_ID_MOD_REV_Pos)                    /*!< FCE ID: MOD_REV Mask                    */\r
+#define FCE_ID_MOD_TYPE_Pos                   8                                                       /*!< FCE ID: MOD_TYPE Position               */\r
+#define FCE_ID_MOD_TYPE_Msk                   (0x000000ffUL << FCE_ID_MOD_TYPE_Pos)                   /*!< FCE ID: MOD_TYPE Mask                   */\r
+#define FCE_ID_MOD_NUMBER_Pos                 16                                                      /*!< FCE ID: MOD_NUMBER Position             */\r
+#define FCE_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << FCE_ID_MOD_NUMBER_Pos)                 /*!< FCE ID: MOD_NUMBER Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'FCE_KE' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  FCE_KE_IR  --------------------------------- */\r
+#define FCE_KE_IR_IR_Pos                      0                                                       /*!< FCE_KE IR: IR Position                  */\r
+#define FCE_KE_IR_IR_Msk                      (0xffffffffUL << FCE_KE_IR_IR_Pos)                      /*!< FCE_KE IR: IR Mask                      */\r
+\r
+/* ---------------------------------  FCE_KE_RES  --------------------------------- */\r
+#define FCE_KE_RES_RES_Pos                    0                                                       /*!< FCE_KE RES: RES Position                */\r
+#define FCE_KE_RES_RES_Msk                    (0xffffffffUL << FCE_KE_RES_RES_Pos)                    /*!< FCE_KE RES: RES Mask                    */\r
+\r
+/* ---------------------------------  FCE_KE_CFG  --------------------------------- */\r
+#define FCE_KE_CFG_CMI_Pos                    0                                                       /*!< FCE_KE CFG: CMI Position                */\r
+#define FCE_KE_CFG_CMI_Msk                    (0x01UL << FCE_KE_CFG_CMI_Pos)                          /*!< FCE_KE CFG: CMI Mask                    */\r
+#define FCE_KE_CFG_CEI_Pos                    1                                                       /*!< FCE_KE CFG: CEI Position                */\r
+#define FCE_KE_CFG_CEI_Msk                    (0x01UL << FCE_KE_CFG_CEI_Pos)                          /*!< FCE_KE CFG: CEI Mask                    */\r
+#define FCE_KE_CFG_LEI_Pos                    2                                                       /*!< FCE_KE CFG: LEI Position                */\r
+#define FCE_KE_CFG_LEI_Msk                    (0x01UL << FCE_KE_CFG_LEI_Pos)                          /*!< FCE_KE CFG: LEI Mask                    */\r
+#define FCE_KE_CFG_BEI_Pos                    3                                                       /*!< FCE_KE CFG: BEI Position                */\r
+#define FCE_KE_CFG_BEI_Msk                    (0x01UL << FCE_KE_CFG_BEI_Pos)                          /*!< FCE_KE CFG: BEI Mask                    */\r
+#define FCE_KE_CFG_CCE_Pos                    4                                                       /*!< FCE_KE CFG: CCE Position                */\r
+#define FCE_KE_CFG_CCE_Msk                    (0x01UL << FCE_KE_CFG_CCE_Pos)                          /*!< FCE_KE CFG: CCE Mask                    */\r
+#define FCE_KE_CFG_ALR_Pos                    5                                                       /*!< FCE_KE CFG: ALR Position                */\r
+#define FCE_KE_CFG_ALR_Msk                    (0x01UL << FCE_KE_CFG_ALR_Pos)                          /*!< FCE_KE CFG: ALR Mask                    */\r
+#define FCE_KE_CFG_REFIN_Pos                  8                                                       /*!< FCE_KE CFG: REFIN Position              */\r
+#define FCE_KE_CFG_REFIN_Msk                  (0x01UL << FCE_KE_CFG_REFIN_Pos)                        /*!< FCE_KE CFG: REFIN Mask                  */\r
+#define FCE_KE_CFG_REFOUT_Pos                 9                                                       /*!< FCE_KE CFG: REFOUT Position             */\r
+#define FCE_KE_CFG_REFOUT_Msk                 (0x01UL << FCE_KE_CFG_REFOUT_Pos)                       /*!< FCE_KE CFG: REFOUT Mask                 */\r
+#define FCE_KE_CFG_XSEL_Pos                   10                                                      /*!< FCE_KE CFG: XSEL Position               */\r
+#define FCE_KE_CFG_XSEL_Msk                   (0x01UL << FCE_KE_CFG_XSEL_Pos)                         /*!< FCE_KE CFG: XSEL Mask                   */\r
+\r
+/* ---------------------------------  FCE_KE_STS  --------------------------------- */\r
+#define FCE_KE_STS_CMF_Pos                    0                                                       /*!< FCE_KE STS: CMF Position                */\r
+#define FCE_KE_STS_CMF_Msk                    (0x01UL << FCE_KE_STS_CMF_Pos)                          /*!< FCE_KE STS: CMF Mask                    */\r
+#define FCE_KE_STS_CEF_Pos                    1                                                       /*!< FCE_KE STS: CEF Position                */\r
+#define FCE_KE_STS_CEF_Msk                    (0x01UL << FCE_KE_STS_CEF_Pos)                          /*!< FCE_KE STS: CEF Mask                    */\r
+#define FCE_KE_STS_LEF_Pos                    2                                                       /*!< FCE_KE STS: LEF Position                */\r
+#define FCE_KE_STS_LEF_Msk                    (0x01UL << FCE_KE_STS_LEF_Pos)                          /*!< FCE_KE STS: LEF Mask                    */\r
+#define FCE_KE_STS_BEF_Pos                    3                                                       /*!< FCE_KE STS: BEF Position                */\r
+#define FCE_KE_STS_BEF_Msk                    (0x01UL << FCE_KE_STS_BEF_Pos)                          /*!< FCE_KE STS: BEF Mask                    */\r
+\r
+/* --------------------------------  FCE_KE_LENGTH  ------------------------------- */\r
+#define FCE_KE_LENGTH_LENGTH_Pos              0                                                       /*!< FCE_KE LENGTH: LENGTH Position          */\r
+#define FCE_KE_LENGTH_LENGTH_Msk              (0x0000ffffUL << FCE_KE_LENGTH_LENGTH_Pos)              /*!< FCE_KE LENGTH: LENGTH Mask              */\r
+\r
+/* --------------------------------  FCE_KE_CHECK  -------------------------------- */\r
+#define FCE_KE_CHECK_CHECK_Pos                0                                                       /*!< FCE_KE CHECK: CHECK Position            */\r
+#define FCE_KE_CHECK_CHECK_Msk                (0xffffffffUL << FCE_KE_CHECK_CHECK_Pos)                /*!< FCE_KE CHECK: CHECK Mask                */\r
+\r
+/* ---------------------------------  FCE_KE_CRC  --------------------------------- */\r
+#define FCE_KE_CRC_CRC_Pos                    0                                                       /*!< FCE_KE CRC: CRC Position                */\r
+#define FCE_KE_CRC_CRC_Msk                    (0xffffffffUL << FCE_KE_CRC_CRC_Pos)                    /*!< FCE_KE CRC: CRC Mask                    */\r
+\r
+/* ---------------------------------  FCE_KE_CTR  --------------------------------- */\r
+#define FCE_KE_CTR_FCM_Pos                    0                                                       /*!< FCE_KE CTR: FCM Position                */\r
+#define FCE_KE_CTR_FCM_Msk                    (0x01UL << FCE_KE_CTR_FCM_Pos)                          /*!< FCE_KE CTR: FCM Mask                    */\r
+#define FCE_KE_CTR_FRM_CFG_Pos                1                                                       /*!< FCE_KE CTR: FRM_CFG Position            */\r
+#define FCE_KE_CTR_FRM_CFG_Msk                (0x01UL << FCE_KE_CTR_FRM_CFG_Pos)                      /*!< FCE_KE CTR: FRM_CFG Mask                */\r
+#define FCE_KE_CTR_FRM_CHECK_Pos              2                                                       /*!< FCE_KE CTR: FRM_CHECK Position          */\r
+#define FCE_KE_CTR_FRM_CHECK_Msk              (0x01UL << FCE_KE_CTR_FRM_CHECK_Pos)                    /*!< FCE_KE CTR: FRM_CHECK Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'PBA' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  PBA_STS  ---------------------------------- */\r
+#define PBA_STS_WERR_Pos                      0                                                       /*!< PBA STS: WERR Position                  */\r
+#define PBA_STS_WERR_Msk                      (0x01UL << PBA_STS_WERR_Pos)                            /*!< PBA STS: WERR Mask                      */\r
+\r
+/* ----------------------------------  PBA_WADDR  --------------------------------- */\r
+#define PBA_WADDR_WADDR_Pos                   0                                                       /*!< PBA WADDR: WADDR Position               */\r
+#define PBA_WADDR_WADDR_Msk                   (0xffffffffUL << PBA_WADDR_WADDR_Pos)                   /*!< PBA WADDR: WADDR Mask                   */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'FLASH' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  FLASH_ID  ---------------------------------- */\r
+#define FLASH_ID_MOD_REV_Pos                  0                                                       /*!< FLASH ID: MOD_REV Position              */\r
+#define FLASH_ID_MOD_REV_Msk                  (0x000000ffUL << FLASH_ID_MOD_REV_Pos)                  /*!< FLASH ID: MOD_REV Mask                  */\r
+#define FLASH_ID_MOD_TYPE_Pos                 8                                                       /*!< FLASH ID: MOD_TYPE Position             */\r
+#define FLASH_ID_MOD_TYPE_Msk                 (0x000000ffUL << FLASH_ID_MOD_TYPE_Pos)                 /*!< FLASH ID: MOD_TYPE Mask                 */\r
+#define FLASH_ID_MOD_NUMBER_Pos               16                                                      /*!< FLASH ID: MOD_NUMBER Position           */\r
+#define FLASH_ID_MOD_NUMBER_Msk               (0x0000ffffUL << FLASH_ID_MOD_NUMBER_Pos)               /*!< FLASH ID: MOD_NUMBER Mask               */\r
+\r
+/* ----------------------------------  FLASH_FSR  --------------------------------- */\r
+#define FLASH_FSR_PBUSY_Pos                   0                                                       /*!< FLASH FSR: PBUSY Position               */\r
+#define FLASH_FSR_PBUSY_Msk                   (0x01UL << FLASH_FSR_PBUSY_Pos)                         /*!< FLASH FSR: PBUSY Mask                   */\r
+#define FLASH_FSR_FABUSY_Pos                  1                                                       /*!< FLASH FSR: FABUSY Position              */\r
+#define FLASH_FSR_FABUSY_Msk                  (0x01UL << FLASH_FSR_FABUSY_Pos)                        /*!< FLASH FSR: FABUSY Mask                  */\r
+#define FLASH_FSR_PROG_Pos                    4                                                       /*!< FLASH FSR: PROG Position                */\r
+#define FLASH_FSR_PROG_Msk                    (0x01UL << FLASH_FSR_PROG_Pos)                          /*!< FLASH FSR: PROG Mask                    */\r
+#define FLASH_FSR_ERASE_Pos                   5                                                       /*!< FLASH FSR: ERASE Position               */\r
+#define FLASH_FSR_ERASE_Msk                   (0x01UL << FLASH_FSR_ERASE_Pos)                         /*!< FLASH FSR: ERASE Mask                   */\r
+#define FLASH_FSR_PFPAGE_Pos                  6                                                       /*!< FLASH FSR: PFPAGE Position              */\r
+#define FLASH_FSR_PFPAGE_Msk                  (0x01UL << FLASH_FSR_PFPAGE_Pos)                        /*!< FLASH FSR: PFPAGE Mask                  */\r
+#define FLASH_FSR_PFOPER_Pos                  8                                                       /*!< FLASH FSR: PFOPER Position              */\r
+#define FLASH_FSR_PFOPER_Msk                  (0x01UL << FLASH_FSR_PFOPER_Pos)                        /*!< FLASH FSR: PFOPER Mask                  */\r
+#define FLASH_FSR_SQER_Pos                    10                                                      /*!< FLASH FSR: SQER Position                */\r
+#define FLASH_FSR_SQER_Msk                    (0x01UL << FLASH_FSR_SQER_Pos)                          /*!< FLASH FSR: SQER Mask                    */\r
+#define FLASH_FSR_PROER_Pos                   11                                                      /*!< FLASH FSR: PROER Position               */\r
+#define FLASH_FSR_PROER_Msk                   (0x01UL << FLASH_FSR_PROER_Pos)                         /*!< FLASH FSR: PROER Mask                   */\r
+#define FLASH_FSR_PFSBER_Pos                  12                                                      /*!< FLASH FSR: PFSBER Position              */\r
+#define FLASH_FSR_PFSBER_Msk                  (0x01UL << FLASH_FSR_PFSBER_Pos)                        /*!< FLASH FSR: PFSBER Mask                  */\r
+#define FLASH_FSR_PFDBER_Pos                  14                                                      /*!< FLASH FSR: PFDBER Position              */\r
+#define FLASH_FSR_PFDBER_Msk                  (0x01UL << FLASH_FSR_PFDBER_Pos)                        /*!< FLASH FSR: PFDBER Mask                  */\r
+#define FLASH_FSR_PROIN_Pos                   16                                                      /*!< FLASH FSR: PROIN Position               */\r
+#define FLASH_FSR_PROIN_Msk                   (0x01UL << FLASH_FSR_PROIN_Pos)                         /*!< FLASH FSR: PROIN Mask                   */\r
+#define FLASH_FSR_RPROIN_Pos                  18                                                      /*!< FLASH FSR: RPROIN Position              */\r
+#define FLASH_FSR_RPROIN_Msk                  (0x01UL << FLASH_FSR_RPROIN_Pos)                        /*!< FLASH FSR: RPROIN Mask                  */\r
+#define FLASH_FSR_RPRODIS_Pos                 19                                                      /*!< FLASH FSR: RPRODIS Position             */\r
+#define FLASH_FSR_RPRODIS_Msk                 (0x01UL << FLASH_FSR_RPRODIS_Pos)                       /*!< FLASH FSR: RPRODIS Mask                 */\r
+#define FLASH_FSR_WPROIN0_Pos                 21                                                      /*!< FLASH FSR: WPROIN0 Position             */\r
+#define FLASH_FSR_WPROIN0_Msk                 (0x01UL << FLASH_FSR_WPROIN0_Pos)                       /*!< FLASH FSR: WPROIN0 Mask                 */\r
+#define FLASH_FSR_WPROIN1_Pos                 22                                                      /*!< FLASH FSR: WPROIN1 Position             */\r
+#define FLASH_FSR_WPROIN1_Msk                 (0x01UL << FLASH_FSR_WPROIN1_Pos)                       /*!< FLASH FSR: WPROIN1 Mask                 */\r
+#define FLASH_FSR_WPROIN2_Pos                 23                                                      /*!< FLASH FSR: WPROIN2 Position             */\r
+#define FLASH_FSR_WPROIN2_Msk                 (0x01UL << FLASH_FSR_WPROIN2_Pos)                       /*!< FLASH FSR: WPROIN2 Mask                 */\r
+#define FLASH_FSR_WPRODIS0_Pos                25                                                      /*!< FLASH FSR: WPRODIS0 Position            */\r
+#define FLASH_FSR_WPRODIS0_Msk                (0x01UL << FLASH_FSR_WPRODIS0_Pos)                      /*!< FLASH FSR: WPRODIS0 Mask                */\r
+#define FLASH_FSR_WPRODIS1_Pos                26                                                      /*!< FLASH FSR: WPRODIS1 Position            */\r
+#define FLASH_FSR_WPRODIS1_Msk                (0x01UL << FLASH_FSR_WPRODIS1_Pos)                      /*!< FLASH FSR: WPRODIS1 Mask                */\r
+#define FLASH_FSR_SLM_Pos                     28                                                      /*!< FLASH FSR: SLM Position                 */\r
+#define FLASH_FSR_SLM_Msk                     (0x01UL << FLASH_FSR_SLM_Pos)                           /*!< FLASH FSR: SLM Mask                     */\r
+#define FLASH_FSR_X_Pos                       30                                                      /*!< FLASH FSR: X Position                   */\r
+#define FLASH_FSR_X_Msk                       (0x01UL << FLASH_FSR_X_Pos)                             /*!< FLASH FSR: X Mask                       */\r
+#define FLASH_FSR_VER_Pos                     31                                                      /*!< FLASH FSR: VER Position                 */\r
+#define FLASH_FSR_VER_Msk                     (0x01UL << FLASH_FSR_VER_Pos)                           /*!< FLASH FSR: VER Mask                     */\r
+\r
+/* ---------------------------------  FLASH_FCON  --------------------------------- */\r
+#define FLASH_FCON_WSPFLASH_Pos               0                                                       /*!< FLASH FCON: WSPFLASH Position           */\r
+#define FLASH_FCON_WSPFLASH_Msk               (0x0fUL << FLASH_FCON_WSPFLASH_Pos)                     /*!< FLASH FCON: WSPFLASH Mask               */\r
+#define FLASH_FCON_WSECPF_Pos                 4                                                       /*!< FLASH FCON: WSECPF Position             */\r
+#define FLASH_FCON_WSECPF_Msk                 (0x01UL << FLASH_FCON_WSECPF_Pos)                       /*!< FLASH FCON: WSECPF Mask                 */\r
+#define FLASH_FCON_IDLE_Pos                   13                                                      /*!< FLASH FCON: IDLE Position               */\r
+#define FLASH_FCON_IDLE_Msk                   (0x01UL << FLASH_FCON_IDLE_Pos)                         /*!< FLASH FCON: IDLE Mask                   */\r
+#define FLASH_FCON_ESLDIS_Pos                 14                                                      /*!< FLASH FCON: ESLDIS Position             */\r
+#define FLASH_FCON_ESLDIS_Msk                 (0x01UL << FLASH_FCON_ESLDIS_Pos)                       /*!< FLASH FCON: ESLDIS Mask                 */\r
+#define FLASH_FCON_SLEEP_Pos                  15                                                      /*!< FLASH FCON: SLEEP Position              */\r
+#define FLASH_FCON_SLEEP_Msk                  (0x01UL << FLASH_FCON_SLEEP_Pos)                        /*!< FLASH FCON: SLEEP Mask                  */\r
+#define FLASH_FCON_RPA_Pos                    16                                                      /*!< FLASH FCON: RPA Position                */\r
+#define FLASH_FCON_RPA_Msk                    (0x01UL << FLASH_FCON_RPA_Pos)                          /*!< FLASH FCON: RPA Mask                    */\r
+#define FLASH_FCON_DCF_Pos                    17                                                      /*!< FLASH FCON: DCF Position                */\r
+#define FLASH_FCON_DCF_Msk                    (0x01UL << FLASH_FCON_DCF_Pos)                          /*!< FLASH FCON: DCF Mask                    */\r
+#define FLASH_FCON_DDF_Pos                    18                                                      /*!< FLASH FCON: DDF Position                */\r
+#define FLASH_FCON_DDF_Msk                    (0x01UL << FLASH_FCON_DDF_Pos)                          /*!< FLASH FCON: DDF Mask                    */\r
+#define FLASH_FCON_VOPERM_Pos                 24                                                      /*!< FLASH FCON: VOPERM Position             */\r
+#define FLASH_FCON_VOPERM_Msk                 (0x01UL << FLASH_FCON_VOPERM_Pos)                       /*!< FLASH FCON: VOPERM Mask                 */\r
+#define FLASH_FCON_SQERM_Pos                  25                                                      /*!< FLASH FCON: SQERM Position              */\r
+#define FLASH_FCON_SQERM_Msk                  (0x01UL << FLASH_FCON_SQERM_Pos)                        /*!< FLASH FCON: SQERM Mask                  */\r
+#define FLASH_FCON_PROERM_Pos                 26                                                      /*!< FLASH FCON: PROERM Position             */\r
+#define FLASH_FCON_PROERM_Msk                 (0x01UL << FLASH_FCON_PROERM_Pos)                       /*!< FLASH FCON: PROERM Mask                 */\r
+#define FLASH_FCON_PFSBERM_Pos                27                                                      /*!< FLASH FCON: PFSBERM Position            */\r
+#define FLASH_FCON_PFSBERM_Msk                (0x01UL << FLASH_FCON_PFSBERM_Pos)                      /*!< FLASH FCON: PFSBERM Mask                */\r
+#define FLASH_FCON_PFDBERM_Pos                29                                                      /*!< FLASH FCON: PFDBERM Position            */\r
+#define FLASH_FCON_PFDBERM_Msk                (0x01UL << FLASH_FCON_PFDBERM_Pos)                      /*!< FLASH FCON: PFDBERM Mask                */\r
+#define FLASH_FCON_EOBM_Pos                   31                                                      /*!< FLASH FCON: EOBM Position               */\r
+#define FLASH_FCON_EOBM_Msk                   (0x01UL << FLASH_FCON_EOBM_Pos)                         /*!< FLASH FCON: EOBM Mask                   */\r
+\r
+/* ---------------------------------  FLASH_MARP  --------------------------------- */\r
+#define FLASH_MARP_MARGIN_Pos                 0                                                       /*!< FLASH MARP: MARGIN Position             */\r
+#define FLASH_MARP_MARGIN_Msk                 (0x0fUL << FLASH_MARP_MARGIN_Pos)                       /*!< FLASH MARP: MARGIN Mask                 */\r
+#define FLASH_MARP_TRAPDIS_Pos                15                                                      /*!< FLASH MARP: TRAPDIS Position            */\r
+#define FLASH_MARP_TRAPDIS_Msk                (0x01UL << FLASH_MARP_TRAPDIS_Pos)                      /*!< FLASH MARP: TRAPDIS Mask                */\r
+\r
+/* --------------------------------  FLASH_PROCON0  ------------------------------- */\r
+#define FLASH_PROCON0_S0L_Pos                 0                                                       /*!< FLASH PROCON0: S0L Position             */\r
+#define FLASH_PROCON0_S0L_Msk                 (0x01UL << FLASH_PROCON0_S0L_Pos)                       /*!< FLASH PROCON0: S0L Mask                 */\r
+#define FLASH_PROCON0_S1L_Pos                 1                                                       /*!< FLASH PROCON0: S1L Position             */\r
+#define FLASH_PROCON0_S1L_Msk                 (0x01UL << FLASH_PROCON0_S1L_Pos)                       /*!< FLASH PROCON0: S1L Mask                 */\r
+#define FLASH_PROCON0_S2L_Pos                 2                                                       /*!< FLASH PROCON0: S2L Position             */\r
+#define FLASH_PROCON0_S2L_Msk                 (0x01UL << FLASH_PROCON0_S2L_Pos)                       /*!< FLASH PROCON0: S2L Mask                 */\r
+#define FLASH_PROCON0_S3L_Pos                 3                                                       /*!< FLASH PROCON0: S3L Position             */\r
+#define FLASH_PROCON0_S3L_Msk                 (0x01UL << FLASH_PROCON0_S3L_Pos)                       /*!< FLASH PROCON0: S3L Mask                 */\r
+#define FLASH_PROCON0_S4L_Pos                 4                                                       /*!< FLASH PROCON0: S4L Position             */\r
+#define FLASH_PROCON0_S4L_Msk                 (0x01UL << FLASH_PROCON0_S4L_Pos)                       /*!< FLASH PROCON0: S4L Mask                 */\r
+#define FLASH_PROCON0_S5L_Pos                 5                                                       /*!< FLASH PROCON0: S5L Position             */\r
+#define FLASH_PROCON0_S5L_Msk                 (0x01UL << FLASH_PROCON0_S5L_Pos)                       /*!< FLASH PROCON0: S5L Mask                 */\r
+#define FLASH_PROCON0_S6L_Pos                 6                                                       /*!< FLASH PROCON0: S6L Position             */\r
+#define FLASH_PROCON0_S6L_Msk                 (0x01UL << FLASH_PROCON0_S6L_Pos)                       /*!< FLASH PROCON0: S6L Mask                 */\r
+#define FLASH_PROCON0_S7L_Pos                 7                                                       /*!< FLASH PROCON0: S7L Position             */\r
+#define FLASH_PROCON0_S7L_Msk                 (0x01UL << FLASH_PROCON0_S7L_Pos)                       /*!< FLASH PROCON0: S7L Mask                 */\r
+#define FLASH_PROCON0_S8L_Pos                 8                                                       /*!< FLASH PROCON0: S8L Position             */\r
+#define FLASH_PROCON0_S8L_Msk                 (0x01UL << FLASH_PROCON0_S8L_Pos)                       /*!< FLASH PROCON0: S8L Mask                 */\r
+#define FLASH_PROCON0_S9L_Pos                 9                                                       /*!< FLASH PROCON0: S9L Position             */\r
+#define FLASH_PROCON0_S9L_Msk                 (0x01UL << FLASH_PROCON0_S9L_Pos)                       /*!< FLASH PROCON0: S9L Mask                 */\r
+#define FLASH_PROCON0_S10_S11L_Pos            10                                                      /*!< FLASH PROCON0: S10_S11L Position        */\r
+#define FLASH_PROCON0_S10_S11L_Msk            (0x01UL << FLASH_PROCON0_S10_S11L_Pos)                  /*!< FLASH PROCON0: S10_S11L Mask            */\r
+#define FLASH_PROCON0_RPRO_Pos                15                                                      /*!< FLASH PROCON0: RPRO Position            */\r
+#define FLASH_PROCON0_RPRO_Msk                (0x01UL << FLASH_PROCON0_RPRO_Pos)                      /*!< FLASH PROCON0: RPRO Mask                */\r
+\r
+/* --------------------------------  FLASH_PROCON1  ------------------------------- */\r
+#define FLASH_PROCON1_S0L_Pos                 0                                                       /*!< FLASH PROCON1: S0L Position             */\r
+#define FLASH_PROCON1_S0L_Msk                 (0x01UL << FLASH_PROCON1_S0L_Pos)                       /*!< FLASH PROCON1: S0L Mask                 */\r
+#define FLASH_PROCON1_S1L_Pos                 1                                                       /*!< FLASH PROCON1: S1L Position             */\r
+#define FLASH_PROCON1_S1L_Msk                 (0x01UL << FLASH_PROCON1_S1L_Pos)                       /*!< FLASH PROCON1: S1L Mask                 */\r
+#define FLASH_PROCON1_S2L_Pos                 2                                                       /*!< FLASH PROCON1: S2L Position             */\r
+#define FLASH_PROCON1_S2L_Msk                 (0x01UL << FLASH_PROCON1_S2L_Pos)                       /*!< FLASH PROCON1: S2L Mask                 */\r
+#define FLASH_PROCON1_S3L_Pos                 3                                                       /*!< FLASH PROCON1: S3L Position             */\r
+#define FLASH_PROCON1_S3L_Msk                 (0x01UL << FLASH_PROCON1_S3L_Pos)                       /*!< FLASH PROCON1: S3L Mask                 */\r
+#define FLASH_PROCON1_S4L_Pos                 4                                                       /*!< FLASH PROCON1: S4L Position             */\r
+#define FLASH_PROCON1_S4L_Msk                 (0x01UL << FLASH_PROCON1_S4L_Pos)                       /*!< FLASH PROCON1: S4L Mask                 */\r
+#define FLASH_PROCON1_S5L_Pos                 5                                                       /*!< FLASH PROCON1: S5L Position             */\r
+#define FLASH_PROCON1_S5L_Msk                 (0x01UL << FLASH_PROCON1_S5L_Pos)                       /*!< FLASH PROCON1: S5L Mask                 */\r
+#define FLASH_PROCON1_S6L_Pos                 6                                                       /*!< FLASH PROCON1: S6L Position             */\r
+#define FLASH_PROCON1_S6L_Msk                 (0x01UL << FLASH_PROCON1_S6L_Pos)                       /*!< FLASH PROCON1: S6L Mask                 */\r
+#define FLASH_PROCON1_S7L_Pos                 7                                                       /*!< FLASH PROCON1: S7L Position             */\r
+#define FLASH_PROCON1_S7L_Msk                 (0x01UL << FLASH_PROCON1_S7L_Pos)                       /*!< FLASH PROCON1: S7L Mask                 */\r
+#define FLASH_PROCON1_S8L_Pos                 8                                                       /*!< FLASH PROCON1: S8L Position             */\r
+#define FLASH_PROCON1_S8L_Msk                 (0x01UL << FLASH_PROCON1_S8L_Pos)                       /*!< FLASH PROCON1: S8L Mask                 */\r
+#define FLASH_PROCON1_S9L_Pos                 9                                                       /*!< FLASH PROCON1: S9L Position             */\r
+#define FLASH_PROCON1_S9L_Msk                 (0x01UL << FLASH_PROCON1_S9L_Pos)                       /*!< FLASH PROCON1: S9L Mask                 */\r
+#define FLASH_PROCON1_S10_S11L_Pos            10                                                      /*!< FLASH PROCON1: S10_S11L Position        */\r
+#define FLASH_PROCON1_S10_S11L_Msk            (0x01UL << FLASH_PROCON1_S10_S11L_Pos)                  /*!< FLASH PROCON1: S10_S11L Mask            */\r
+\r
+/* --------------------------------  FLASH_PROCON2  ------------------------------- */\r
+#define FLASH_PROCON2_S0ROM_Pos               0                                                       /*!< FLASH PROCON2: S0ROM Position           */\r
+#define FLASH_PROCON2_S0ROM_Msk               (0x01UL << FLASH_PROCON2_S0ROM_Pos)                     /*!< FLASH PROCON2: S0ROM Mask               */\r
+#define FLASH_PROCON2_S1ROM_Pos               1                                                       /*!< FLASH PROCON2: S1ROM Position           */\r
+#define FLASH_PROCON2_S1ROM_Msk               (0x01UL << FLASH_PROCON2_S1ROM_Pos)                     /*!< FLASH PROCON2: S1ROM Mask               */\r
+#define FLASH_PROCON2_S2ROM_Pos               2                                                       /*!< FLASH PROCON2: S2ROM Position           */\r
+#define FLASH_PROCON2_S2ROM_Msk               (0x01UL << FLASH_PROCON2_S2ROM_Pos)                     /*!< FLASH PROCON2: S2ROM Mask               */\r
+#define FLASH_PROCON2_S3ROM_Pos               3                                                       /*!< FLASH PROCON2: S3ROM Position           */\r
+#define FLASH_PROCON2_S3ROM_Msk               (0x01UL << FLASH_PROCON2_S3ROM_Pos)                     /*!< FLASH PROCON2: S3ROM Mask               */\r
+#define FLASH_PROCON2_S4ROM_Pos               4                                                       /*!< FLASH PROCON2: S4ROM Position           */\r
+#define FLASH_PROCON2_S4ROM_Msk               (0x01UL << FLASH_PROCON2_S4ROM_Pos)                     /*!< FLASH PROCON2: S4ROM Mask               */\r
+#define FLASH_PROCON2_S5ROM_Pos               5                                                       /*!< FLASH PROCON2: S5ROM Position           */\r
+#define FLASH_PROCON2_S5ROM_Msk               (0x01UL << FLASH_PROCON2_S5ROM_Pos)                     /*!< FLASH PROCON2: S5ROM Mask               */\r
+#define FLASH_PROCON2_S6ROM_Pos               6                                                       /*!< FLASH PROCON2: S6ROM Position           */\r
+#define FLASH_PROCON2_S6ROM_Msk               (0x01UL << FLASH_PROCON2_S6ROM_Pos)                     /*!< FLASH PROCON2: S6ROM Mask               */\r
+#define FLASH_PROCON2_S7ROM_Pos               7                                                       /*!< FLASH PROCON2: S7ROM Position           */\r
+#define FLASH_PROCON2_S7ROM_Msk               (0x01UL << FLASH_PROCON2_S7ROM_Pos)                     /*!< FLASH PROCON2: S7ROM Mask               */\r
+#define FLASH_PROCON2_S8ROM_Pos               8                                                       /*!< FLASH PROCON2: S8ROM Position           */\r
+#define FLASH_PROCON2_S8ROM_Msk               (0x01UL << FLASH_PROCON2_S8ROM_Pos)                     /*!< FLASH PROCON2: S8ROM Mask               */\r
+#define FLASH_PROCON2_S9ROM_Pos               9                                                       /*!< FLASH PROCON2: S9ROM Position           */\r
+#define FLASH_PROCON2_S9ROM_Msk               (0x01UL << FLASH_PROCON2_S9ROM_Pos)                     /*!< FLASH PROCON2: S9ROM Mask               */\r
+#define FLASH_PROCON2_S10_S11ROM_Pos          10                                                      /*!< FLASH PROCON2: S10_S11ROM Position      */\r
+#define FLASH_PROCON2_S10_S11ROM_Msk          (0x01UL << FLASH_PROCON2_S10_S11ROM_Pos)                /*!< FLASH PROCON2: S10_S11ROM Mask          */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'PREF' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PREF_PCON  --------------------------------- */\r
+#define PREF_PCON_IBYP_Pos                    0                                                       /*!< PREF PCON: IBYP Position                */\r
+#define PREF_PCON_IBYP_Msk                    (0x01UL << PREF_PCON_IBYP_Pos)                          /*!< PREF PCON: IBYP Mask                    */\r
+#define PREF_PCON_IINV_Pos                    1                                                       /*!< PREF PCON: IINV Position                */\r
+#define PREF_PCON_IINV_Msk                    (0x01UL << PREF_PCON_IINV_Pos)                          /*!< PREF PCON: IINV Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'PMU' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  PMU_ID  ----------------------------------- */\r
+#define PMU_ID_MOD_REV_Pos                    0                                                       /*!< PMU ID: MOD_REV Position                */\r
+#define PMU_ID_MOD_REV_Msk                    (0x000000ffUL << PMU_ID_MOD_REV_Pos)                    /*!< PMU ID: MOD_REV Mask                    */\r
+#define PMU_ID_MOD_TYPE_Pos                   8                                                       /*!< PMU ID: MOD_TYPE Position               */\r
+#define PMU_ID_MOD_TYPE_Msk                   (0x000000ffUL << PMU_ID_MOD_TYPE_Pos)                   /*!< PMU ID: MOD_TYPE Mask                   */\r
+#define PMU_ID_MOD_NUMBER_Pos                 16                                                      /*!< PMU ID: MOD_NUMBER Position             */\r
+#define PMU_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << PMU_ID_MOD_NUMBER_Pos)                 /*!< PMU ID: MOD_NUMBER Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'WDT' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  WDT_ID  ----------------------------------- */\r
+#define WDT_ID_MOD_REV_Pos                    0                                                       /*!< WDT ID: MOD_REV Position                */\r
+#define WDT_ID_MOD_REV_Msk                    (0x000000ffUL << WDT_ID_MOD_REV_Pos)                    /*!< WDT ID: MOD_REV Mask                    */\r
+#define WDT_ID_MOD_TYPE_Pos                   8                                                       /*!< WDT ID: MOD_TYPE Position               */\r
+#define WDT_ID_MOD_TYPE_Msk                   (0x000000ffUL << WDT_ID_MOD_TYPE_Pos)                   /*!< WDT ID: MOD_TYPE Mask                   */\r
+#define WDT_ID_MOD_NUMBER_Pos                 16                                                      /*!< WDT ID: MOD_NUMBER Position             */\r
+#define WDT_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << WDT_ID_MOD_NUMBER_Pos)                 /*!< WDT ID: MOD_NUMBER Mask                 */\r
+\r
+/* -----------------------------------  WDT_CTR  ---------------------------------- */\r
+#define WDT_CTR_ENB_Pos                       0                                                       /*!< WDT CTR: ENB Position                   */\r
+#define WDT_CTR_ENB_Msk                       (0x01UL << WDT_CTR_ENB_Pos)                             /*!< WDT CTR: ENB Mask                       */\r
+#define WDT_CTR_PRE_Pos                       1                                                       /*!< WDT CTR: PRE Position                   */\r
+#define WDT_CTR_PRE_Msk                       (0x01UL << WDT_CTR_PRE_Pos)                             /*!< WDT CTR: PRE Mask                       */\r
+#define WDT_CTR_DSP_Pos                       4                                                       /*!< WDT CTR: DSP Position                   */\r
+#define WDT_CTR_DSP_Msk                       (0x01UL << WDT_CTR_DSP_Pos)                             /*!< WDT CTR: DSP Mask                       */\r
+#define WDT_CTR_SPW_Pos                       8                                                       /*!< WDT CTR: SPW Position                   */\r
+#define WDT_CTR_SPW_Msk                       (0x000000ffUL << WDT_CTR_SPW_Pos)                       /*!< WDT CTR: SPW Mask                       */\r
+\r
+/* -----------------------------------  WDT_SRV  ---------------------------------- */\r
+#define WDT_SRV_SRV_Pos                       0                                                       /*!< WDT SRV: SRV Position                   */\r
+#define WDT_SRV_SRV_Msk                       (0xffffffffUL << WDT_SRV_SRV_Pos)                       /*!< WDT SRV: SRV Mask                       */\r
+\r
+/* -----------------------------------  WDT_TIM  ---------------------------------- */\r
+#define WDT_TIM_TIM_Pos                       0                                                       /*!< WDT TIM: TIM Position                   */\r
+#define WDT_TIM_TIM_Msk                       (0xffffffffUL << WDT_TIM_TIM_Pos)                       /*!< WDT TIM: TIM Mask                       */\r
+\r
+/* -----------------------------------  WDT_WLB  ---------------------------------- */\r
+#define WDT_WLB_WLB_Pos                       0                                                       /*!< WDT WLB: WLB Position                   */\r
+#define WDT_WLB_WLB_Msk                       (0xffffffffUL << WDT_WLB_WLB_Pos)                       /*!< WDT WLB: WLB Mask                       */\r
+\r
+/* -----------------------------------  WDT_WUB  ---------------------------------- */\r
+#define WDT_WUB_WUB_Pos                       0                                                       /*!< WDT WUB: WUB Position                   */\r
+#define WDT_WUB_WUB_Msk                       (0xffffffffUL << WDT_WUB_WUB_Pos)                       /*!< WDT WUB: WUB Mask                       */\r
+\r
+/* ---------------------------------  WDT_WDTSTS  --------------------------------- */\r
+#define WDT_WDTSTS_ALMS_Pos                   0                                                       /*!< WDT WDTSTS: ALMS Position               */\r
+#define WDT_WDTSTS_ALMS_Msk                   (0x01UL << WDT_WDTSTS_ALMS_Pos)                         /*!< WDT WDTSTS: ALMS Mask                   */\r
+\r
+/* ---------------------------------  WDT_WDTCLR  --------------------------------- */\r
+#define WDT_WDTCLR_ALMC_Pos                   0                                                       /*!< WDT WDTCLR: ALMC Position               */\r
+#define WDT_WDTCLR_ALMC_Msk                   (0x01UL << WDT_WDTCLR_ALMC_Pos)                         /*!< WDT WDTCLR: ALMC Mask                   */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'RTC' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  RTC_ID  ----------------------------------- */\r
+#define RTC_ID_MOD_REV_Pos                    0                                                       /*!< RTC ID: MOD_REV Position                */\r
+#define RTC_ID_MOD_REV_Msk                    (0x000000ffUL << RTC_ID_MOD_REV_Pos)                    /*!< RTC ID: MOD_REV Mask                    */\r
+#define RTC_ID_MOD_TYPE_Pos                   8                                                       /*!< RTC ID: MOD_TYPE Position               */\r
+#define RTC_ID_MOD_TYPE_Msk                   (0x000000ffUL << RTC_ID_MOD_TYPE_Pos)                   /*!< RTC ID: MOD_TYPE Mask                   */\r
+#define RTC_ID_MOD_NUMBER_Pos                 16                                                      /*!< RTC ID: MOD_NUMBER Position             */\r
+#define RTC_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << RTC_ID_MOD_NUMBER_Pos)                 /*!< RTC ID: MOD_NUMBER Mask                 */\r
+\r
+/* -----------------------------------  RTC_CTR  ---------------------------------- */\r
+#define RTC_CTR_ENB_Pos                       0                                                       /*!< RTC CTR: ENB Position                   */\r
+#define RTC_CTR_ENB_Msk                       (0x01UL << RTC_CTR_ENB_Pos)                             /*!< RTC CTR: ENB Mask                       */\r
+#define RTC_CTR_TAE_Pos                       2                                                       /*!< RTC CTR: TAE Position                   */\r
+#define RTC_CTR_TAE_Msk                       (0x01UL << RTC_CTR_TAE_Pos)                             /*!< RTC CTR: TAE Mask                       */\r
+#define RTC_CTR_ESEC_Pos                      8                                                       /*!< RTC CTR: ESEC Position                  */\r
+#define RTC_CTR_ESEC_Msk                      (0x01UL << RTC_CTR_ESEC_Pos)                            /*!< RTC CTR: ESEC Mask                      */\r
+#define RTC_CTR_EMIC_Pos                      9                                                       /*!< RTC CTR: EMIC Position                  */\r
+#define RTC_CTR_EMIC_Msk                      (0x01UL << RTC_CTR_EMIC_Pos)                            /*!< RTC CTR: EMIC Mask                      */\r
+#define RTC_CTR_EHOC_Pos                      10                                                      /*!< RTC CTR: EHOC Position                  */\r
+#define RTC_CTR_EHOC_Msk                      (0x01UL << RTC_CTR_EHOC_Pos)                            /*!< RTC CTR: EHOC Mask                      */\r
+#define RTC_CTR_EDAC_Pos                      11                                                      /*!< RTC CTR: EDAC Position                  */\r
+#define RTC_CTR_EDAC_Msk                      (0x01UL << RTC_CTR_EDAC_Pos)                            /*!< RTC CTR: EDAC Mask                      */\r
+#define RTC_CTR_EMOC_Pos                      13                                                      /*!< RTC CTR: EMOC Position                  */\r
+#define RTC_CTR_EMOC_Msk                      (0x01UL << RTC_CTR_EMOC_Pos)                            /*!< RTC CTR: EMOC Mask                      */\r
+#define RTC_CTR_EYEC_Pos                      14                                                      /*!< RTC CTR: EYEC Position                  */\r
+#define RTC_CTR_EYEC_Msk                      (0x01UL << RTC_CTR_EYEC_Pos)                            /*!< RTC CTR: EYEC Mask                      */\r
+#define RTC_CTR_DIV_Pos                       16                                                      /*!< RTC CTR: DIV Position                   */\r
+#define RTC_CTR_DIV_Msk                       (0x0000ffffUL << RTC_CTR_DIV_Pos)                       /*!< RTC CTR: DIV Mask                       */\r
+\r
+/* ---------------------------------  RTC_RAWSTAT  -------------------------------- */\r
+#define RTC_RAWSTAT_RPSE_Pos                  0                                                       /*!< RTC RAWSTAT: RPSE Position              */\r
+#define RTC_RAWSTAT_RPSE_Msk                  (0x01UL << RTC_RAWSTAT_RPSE_Pos)                        /*!< RTC RAWSTAT: RPSE Mask                  */\r
+#define RTC_RAWSTAT_RPMI_Pos                  1                                                       /*!< RTC RAWSTAT: RPMI Position              */\r
+#define RTC_RAWSTAT_RPMI_Msk                  (0x01UL << RTC_RAWSTAT_RPMI_Pos)                        /*!< RTC RAWSTAT: RPMI Mask                  */\r
+#define RTC_RAWSTAT_RPHO_Pos                  2                                                       /*!< RTC RAWSTAT: RPHO Position              */\r
+#define RTC_RAWSTAT_RPHO_Msk                  (0x01UL << RTC_RAWSTAT_RPHO_Pos)                        /*!< RTC RAWSTAT: RPHO Mask                  */\r
+#define RTC_RAWSTAT_RPDA_Pos                  3                                                       /*!< RTC RAWSTAT: RPDA Position              */\r
+#define RTC_RAWSTAT_RPDA_Msk                  (0x01UL << RTC_RAWSTAT_RPDA_Pos)                        /*!< RTC RAWSTAT: RPDA Mask                  */\r
+#define RTC_RAWSTAT_RPMO_Pos                  5                                                       /*!< RTC RAWSTAT: RPMO Position              */\r
+#define RTC_RAWSTAT_RPMO_Msk                  (0x01UL << RTC_RAWSTAT_RPMO_Pos)                        /*!< RTC RAWSTAT: RPMO Mask                  */\r
+#define RTC_RAWSTAT_RPYE_Pos                  6                                                       /*!< RTC RAWSTAT: RPYE Position              */\r
+#define RTC_RAWSTAT_RPYE_Msk                  (0x01UL << RTC_RAWSTAT_RPYE_Pos)                        /*!< RTC RAWSTAT: RPYE Mask                  */\r
+#define RTC_RAWSTAT_RAI_Pos                   8                                                       /*!< RTC RAWSTAT: RAI Position               */\r
+#define RTC_RAWSTAT_RAI_Msk                   (0x01UL << RTC_RAWSTAT_RAI_Pos)                         /*!< RTC RAWSTAT: RAI Mask                   */\r
+\r
+/* ----------------------------------  RTC_STSSR  --------------------------------- */\r
+#define RTC_STSSR_SPSE_Pos                    0                                                       /*!< RTC STSSR: SPSE Position                */\r
+#define RTC_STSSR_SPSE_Msk                    (0x01UL << RTC_STSSR_SPSE_Pos)                          /*!< RTC STSSR: SPSE Mask                    */\r
+#define RTC_STSSR_SPMI_Pos                    1                                                       /*!< RTC STSSR: SPMI Position                */\r
+#define RTC_STSSR_SPMI_Msk                    (0x01UL << RTC_STSSR_SPMI_Pos)                          /*!< RTC STSSR: SPMI Mask                    */\r
+#define RTC_STSSR_SPHO_Pos                    2                                                       /*!< RTC STSSR: SPHO Position                */\r
+#define RTC_STSSR_SPHO_Msk                    (0x01UL << RTC_STSSR_SPHO_Pos)                          /*!< RTC STSSR: SPHO Mask                    */\r
+#define RTC_STSSR_SPDA_Pos                    3                                                       /*!< RTC STSSR: SPDA Position                */\r
+#define RTC_STSSR_SPDA_Msk                    (0x01UL << RTC_STSSR_SPDA_Pos)                          /*!< RTC STSSR: SPDA Mask                    */\r
+#define RTC_STSSR_SPMO_Pos                    5                                                       /*!< RTC STSSR: SPMO Position                */\r
+#define RTC_STSSR_SPMO_Msk                    (0x01UL << RTC_STSSR_SPMO_Pos)                          /*!< RTC STSSR: SPMO Mask                    */\r
+#define RTC_STSSR_SPYE_Pos                    6                                                       /*!< RTC STSSR: SPYE Position                */\r
+#define RTC_STSSR_SPYE_Msk                    (0x01UL << RTC_STSSR_SPYE_Pos)                          /*!< RTC STSSR: SPYE Mask                    */\r
+#define RTC_STSSR_SAI_Pos                     8                                                       /*!< RTC STSSR: SAI Position                 */\r
+#define RTC_STSSR_SAI_Msk                     (0x01UL << RTC_STSSR_SAI_Pos)                           /*!< RTC STSSR: SAI Mask                     */\r
+\r
+/* ----------------------------------  RTC_MSKSR  --------------------------------- */\r
+#define RTC_MSKSR_MPSE_Pos                    0                                                       /*!< RTC MSKSR: MPSE Position                */\r
+#define RTC_MSKSR_MPSE_Msk                    (0x01UL << RTC_MSKSR_MPSE_Pos)                          /*!< RTC MSKSR: MPSE Mask                    */\r
+#define RTC_MSKSR_MPMI_Pos                    1                                                       /*!< RTC MSKSR: MPMI Position                */\r
+#define RTC_MSKSR_MPMI_Msk                    (0x01UL << RTC_MSKSR_MPMI_Pos)                          /*!< RTC MSKSR: MPMI Mask                    */\r
+#define RTC_MSKSR_MPHO_Pos                    2                                                       /*!< RTC MSKSR: MPHO Position                */\r
+#define RTC_MSKSR_MPHO_Msk                    (0x01UL << RTC_MSKSR_MPHO_Pos)                          /*!< RTC MSKSR: MPHO Mask                    */\r
+#define RTC_MSKSR_MPDA_Pos                    3                                                       /*!< RTC MSKSR: MPDA Position                */\r
+#define RTC_MSKSR_MPDA_Msk                    (0x01UL << RTC_MSKSR_MPDA_Pos)                          /*!< RTC MSKSR: MPDA Mask                    */\r
+#define RTC_MSKSR_MPMO_Pos                    5                                                       /*!< RTC MSKSR: MPMO Position                */\r
+#define RTC_MSKSR_MPMO_Msk                    (0x01UL << RTC_MSKSR_MPMO_Pos)                          /*!< RTC MSKSR: MPMO Mask                    */\r
+#define RTC_MSKSR_MPYE_Pos                    6                                                       /*!< RTC MSKSR: MPYE Position                */\r
+#define RTC_MSKSR_MPYE_Msk                    (0x01UL << RTC_MSKSR_MPYE_Pos)                          /*!< RTC MSKSR: MPYE Mask                    */\r
+#define RTC_MSKSR_MAI_Pos                     8                                                       /*!< RTC MSKSR: MAI Position                 */\r
+#define RTC_MSKSR_MAI_Msk                     (0x01UL << RTC_MSKSR_MAI_Pos)                           /*!< RTC MSKSR: MAI Mask                     */\r
+\r
+/* ----------------------------------  RTC_CLRSR  --------------------------------- */\r
+#define RTC_CLRSR_RPSE_Pos                    0                                                       /*!< RTC CLRSR: RPSE Position                */\r
+#define RTC_CLRSR_RPSE_Msk                    (0x01UL << RTC_CLRSR_RPSE_Pos)                          /*!< RTC CLRSR: RPSE Mask                    */\r
+#define RTC_CLRSR_RPMI_Pos                    1                                                       /*!< RTC CLRSR: RPMI Position                */\r
+#define RTC_CLRSR_RPMI_Msk                    (0x01UL << RTC_CLRSR_RPMI_Pos)                          /*!< RTC CLRSR: RPMI Mask                    */\r
+#define RTC_CLRSR_RPHO_Pos                    2                                                       /*!< RTC CLRSR: RPHO Position                */\r
+#define RTC_CLRSR_RPHO_Msk                    (0x01UL << RTC_CLRSR_RPHO_Pos)                          /*!< RTC CLRSR: RPHO Mask                    */\r
+#define RTC_CLRSR_RPDA_Pos                    3                                                       /*!< RTC CLRSR: RPDA Position                */\r
+#define RTC_CLRSR_RPDA_Msk                    (0x01UL << RTC_CLRSR_RPDA_Pos)                          /*!< RTC CLRSR: RPDA Mask                    */\r
+#define RTC_CLRSR_RPMO_Pos                    5                                                       /*!< RTC CLRSR: RPMO Position                */\r
+#define RTC_CLRSR_RPMO_Msk                    (0x01UL << RTC_CLRSR_RPMO_Pos)                          /*!< RTC CLRSR: RPMO Mask                    */\r
+#define RTC_CLRSR_RPYE_Pos                    6                                                       /*!< RTC CLRSR: RPYE Position                */\r
+#define RTC_CLRSR_RPYE_Msk                    (0x01UL << RTC_CLRSR_RPYE_Pos)                          /*!< RTC CLRSR: RPYE Mask                    */\r
+#define RTC_CLRSR_RAI_Pos                     8                                                       /*!< RTC CLRSR: RAI Position                 */\r
+#define RTC_CLRSR_RAI_Msk                     (0x01UL << RTC_CLRSR_RAI_Pos)                           /*!< RTC CLRSR: RAI Mask                     */\r
+\r
+/* ----------------------------------  RTC_ATIM0  --------------------------------- */\r
+#define RTC_ATIM0_ASE_Pos                     0                                                       /*!< RTC ATIM0: ASE Position                 */\r
+#define RTC_ATIM0_ASE_Msk                     (0x3fUL << RTC_ATIM0_ASE_Pos)                           /*!< RTC ATIM0: ASE Mask                     */\r
+#define RTC_ATIM0_AMI_Pos                     8                                                       /*!< RTC ATIM0: AMI Position                 */\r
+#define RTC_ATIM0_AMI_Msk                     (0x3fUL << RTC_ATIM0_AMI_Pos)                           /*!< RTC ATIM0: AMI Mask                     */\r
+#define RTC_ATIM0_AHO_Pos                     16                                                      /*!< RTC ATIM0: AHO Position                 */\r
+#define RTC_ATIM0_AHO_Msk                     (0x1fUL << RTC_ATIM0_AHO_Pos)                           /*!< RTC ATIM0: AHO Mask                     */\r
+#define RTC_ATIM0_ADA_Pos                     24                                                      /*!< RTC ATIM0: ADA Position                 */\r
+#define RTC_ATIM0_ADA_Msk                     (0x1fUL << RTC_ATIM0_ADA_Pos)                           /*!< RTC ATIM0: ADA Mask                     */\r
+\r
+/* ----------------------------------  RTC_ATIM1  --------------------------------- */\r
+#define RTC_ATIM1_AMO_Pos                     8                                                       /*!< RTC ATIM1: AMO Position                 */\r
+#define RTC_ATIM1_AMO_Msk                     (0x0fUL << RTC_ATIM1_AMO_Pos)                           /*!< RTC ATIM1: AMO Mask                     */\r
+#define RTC_ATIM1_AYE_Pos                     16                                                      /*!< RTC ATIM1: AYE Position                 */\r
+#define RTC_ATIM1_AYE_Msk                     (0x0000ffffUL << RTC_ATIM1_AYE_Pos)                     /*!< RTC ATIM1: AYE Mask                     */\r
+\r
+/* ----------------------------------  RTC_TIM0  ---------------------------------- */\r
+#define RTC_TIM0_SE_Pos                       0                                                       /*!< RTC TIM0: SE Position                   */\r
+#define RTC_TIM0_SE_Msk                       (0x3fUL << RTC_TIM0_SE_Pos)                             /*!< RTC TIM0: SE Mask                       */\r
+#define RTC_TIM0_MI_Pos                       8                                                       /*!< RTC TIM0: MI Position                   */\r
+#define RTC_TIM0_MI_Msk                       (0x3fUL << RTC_TIM0_MI_Pos)                             /*!< RTC TIM0: MI Mask                       */\r
+#define RTC_TIM0_HO_Pos                       16                                                      /*!< RTC TIM0: HO Position                   */\r
+#define RTC_TIM0_HO_Msk                       (0x1fUL << RTC_TIM0_HO_Pos)                             /*!< RTC TIM0: HO Mask                       */\r
+#define RTC_TIM0_DA_Pos                       24                                                      /*!< RTC TIM0: DA Position                   */\r
+#define RTC_TIM0_DA_Msk                       (0x1fUL << RTC_TIM0_DA_Pos)                             /*!< RTC TIM0: DA Mask                       */\r
+\r
+/* ----------------------------------  RTC_TIM1  ---------------------------------- */\r
+#define RTC_TIM1_DAWE_Pos                     0                                                       /*!< RTC TIM1: DAWE Position                 */\r
+#define RTC_TIM1_DAWE_Msk                     (0x07UL << RTC_TIM1_DAWE_Pos)                           /*!< RTC TIM1: DAWE Mask                     */\r
+#define RTC_TIM1_MO_Pos                       8                                                       /*!< RTC TIM1: MO Position                   */\r
+#define RTC_TIM1_MO_Msk                       (0x0fUL << RTC_TIM1_MO_Pos)                             /*!< RTC TIM1: MO Mask                       */\r
+#define RTC_TIM1_YE_Pos                       16                                                      /*!< RTC TIM1: YE Position                   */\r
+#define RTC_TIM1_YE_Msk                       (0x0000ffffUL << RTC_TIM1_YE_Pos)                       /*!< RTC TIM1: YE Mask                       */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_CLK' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_CLK_CLKSTAT  ------------------------------ */\r
+#define SCU_CLK_CLKSTAT_USBCST_Pos            0                                                       /*!< SCU_CLK CLKSTAT: USBCST Position        */\r
+#define SCU_CLK_CLKSTAT_USBCST_Msk            (0x01UL << SCU_CLK_CLKSTAT_USBCST_Pos)                  /*!< SCU_CLK CLKSTAT: USBCST Mask            */\r
+#define SCU_CLK_CLKSTAT_MMCCST_Pos            1                                                       /*!< SCU_CLK CLKSTAT: MMCCST Position        */\r
+#define SCU_CLK_CLKSTAT_MMCCST_Msk            (0x01UL << SCU_CLK_CLKSTAT_MMCCST_Pos)                  /*!< SCU_CLK CLKSTAT: MMCCST Mask            */\r
+#define SCU_CLK_CLKSTAT_ETH0CST_Pos           2                                                       /*!< SCU_CLK CLKSTAT: ETH0CST Position       */\r
+#define SCU_CLK_CLKSTAT_ETH0CST_Msk           (0x01UL << SCU_CLK_CLKSTAT_ETH0CST_Pos)                 /*!< SCU_CLK CLKSTAT: ETH0CST Mask           */\r
+#define SCU_CLK_CLKSTAT_EBUCST_Pos            3                                                       /*!< SCU_CLK CLKSTAT: EBUCST Position        */\r
+#define SCU_CLK_CLKSTAT_EBUCST_Msk            (0x01UL << SCU_CLK_CLKSTAT_EBUCST_Pos)                  /*!< SCU_CLK CLKSTAT: EBUCST Mask            */\r
+#define SCU_CLK_CLKSTAT_CCUCST_Pos            4                                                       /*!< SCU_CLK CLKSTAT: CCUCST Position        */\r
+#define SCU_CLK_CLKSTAT_CCUCST_Msk            (0x01UL << SCU_CLK_CLKSTAT_CCUCST_Pos)                  /*!< SCU_CLK CLKSTAT: CCUCST Mask            */\r
+#define SCU_CLK_CLKSTAT_WDTCST_Pos            5                                                       /*!< SCU_CLK CLKSTAT: WDTCST Position        */\r
+#define SCU_CLK_CLKSTAT_WDTCST_Msk            (0x01UL << SCU_CLK_CLKSTAT_WDTCST_Pos)                  /*!< SCU_CLK CLKSTAT: WDTCST Mask            */\r
+\r
+/* -------------------------------  SCU_CLK_CLKSET  ------------------------------- */\r
+#define SCU_CLK_CLKSET_USBCEN_Pos             0                                                       /*!< SCU_CLK CLKSET: USBCEN Position         */\r
+#define SCU_CLK_CLKSET_USBCEN_Msk             (0x01UL << SCU_CLK_CLKSET_USBCEN_Pos)                   /*!< SCU_CLK CLKSET: USBCEN Mask             */\r
+#define SCU_CLK_CLKSET_MMCCEN_Pos             1                                                       /*!< SCU_CLK CLKSET: MMCCEN Position         */\r
+#define SCU_CLK_CLKSET_MMCCEN_Msk             (0x01UL << SCU_CLK_CLKSET_MMCCEN_Pos)                   /*!< SCU_CLK CLKSET: MMCCEN Mask             */\r
+#define SCU_CLK_CLKSET_ETH0CEN_Pos            2                                                       /*!< SCU_CLK CLKSET: ETH0CEN Position        */\r
+#define SCU_CLK_CLKSET_ETH0CEN_Msk            (0x01UL << SCU_CLK_CLKSET_ETH0CEN_Pos)                  /*!< SCU_CLK CLKSET: ETH0CEN Mask            */\r
+#define SCU_CLK_CLKSET_EBUCEN_Pos             3                                                       /*!< SCU_CLK CLKSET: EBUCEN Position         */\r
+#define SCU_CLK_CLKSET_EBUCEN_Msk             (0x01UL << SCU_CLK_CLKSET_EBUCEN_Pos)                   /*!< SCU_CLK CLKSET: EBUCEN Mask             */\r
+#define SCU_CLK_CLKSET_CCUCEN_Pos             4                                                       /*!< SCU_CLK CLKSET: CCUCEN Position         */\r
+#define SCU_CLK_CLKSET_CCUCEN_Msk             (0x01UL << SCU_CLK_CLKSET_CCUCEN_Pos)                   /*!< SCU_CLK CLKSET: CCUCEN Mask             */\r
+#define SCU_CLK_CLKSET_WDTCEN_Pos             5                                                       /*!< SCU_CLK CLKSET: WDTCEN Position         */\r
+#define SCU_CLK_CLKSET_WDTCEN_Msk             (0x01UL << SCU_CLK_CLKSET_WDTCEN_Pos)                   /*!< SCU_CLK CLKSET: WDTCEN Mask             */\r
+\r
+/* -------------------------------  SCU_CLK_CLKCLR  ------------------------------- */\r
+#define SCU_CLK_CLKCLR_USBCDI_Pos             0                                                       /*!< SCU_CLK CLKCLR: USBCDI Position         */\r
+#define SCU_CLK_CLKCLR_USBCDI_Msk             (0x01UL << SCU_CLK_CLKCLR_USBCDI_Pos)                   /*!< SCU_CLK CLKCLR: USBCDI Mask             */\r
+#define SCU_CLK_CLKCLR_MMCCDI_Pos             1                                                       /*!< SCU_CLK CLKCLR: MMCCDI Position         */\r
+#define SCU_CLK_CLKCLR_MMCCDI_Msk             (0x01UL << SCU_CLK_CLKCLR_MMCCDI_Pos)                   /*!< SCU_CLK CLKCLR: MMCCDI Mask             */\r
+#define SCU_CLK_CLKCLR_ETH0CDI_Pos            2                                                       /*!< SCU_CLK CLKCLR: ETH0CDI Position        */\r
+#define SCU_CLK_CLKCLR_ETH0CDI_Msk            (0x01UL << SCU_CLK_CLKCLR_ETH0CDI_Pos)                  /*!< SCU_CLK CLKCLR: ETH0CDI Mask            */\r
+#define SCU_CLK_CLKCLR_EBUCDI_Pos             3                                                       /*!< SCU_CLK CLKCLR: EBUCDI Position         */\r
+#define SCU_CLK_CLKCLR_EBUCDI_Msk             (0x01UL << SCU_CLK_CLKCLR_EBUCDI_Pos)                   /*!< SCU_CLK CLKCLR: EBUCDI Mask             */\r
+#define SCU_CLK_CLKCLR_CCUCDI_Pos             4                                                       /*!< SCU_CLK CLKCLR: CCUCDI Position         */\r
+#define SCU_CLK_CLKCLR_CCUCDI_Msk             (0x01UL << SCU_CLK_CLKCLR_CCUCDI_Pos)                   /*!< SCU_CLK CLKCLR: CCUCDI Mask             */\r
+#define SCU_CLK_CLKCLR_WDTCDI_Pos             5                                                       /*!< SCU_CLK CLKCLR: WDTCDI Position         */\r
+#define SCU_CLK_CLKCLR_WDTCDI_Msk             (0x01UL << SCU_CLK_CLKCLR_WDTCDI_Pos)                   /*!< SCU_CLK CLKCLR: WDTCDI Mask             */\r
+\r
+/* ------------------------------  SCU_CLK_SYSCLKCR  ------------------------------ */\r
+#define SCU_CLK_SYSCLKCR_SYSDIV_Pos           0                                                       /*!< SCU_CLK SYSCLKCR: SYSDIV Position       */\r
+#define SCU_CLK_SYSCLKCR_SYSDIV_Msk           (0x000000ffUL << SCU_CLK_SYSCLKCR_SYSDIV_Pos)           /*!< SCU_CLK SYSCLKCR: SYSDIV Mask           */\r
+#define SCU_CLK_SYSCLKCR_SYSSEL_Pos           16                                                      /*!< SCU_CLK SYSCLKCR: SYSSEL Position       */\r
+#define SCU_CLK_SYSCLKCR_SYSSEL_Msk           (0x01UL << SCU_CLK_SYSCLKCR_SYSSEL_Pos)                 /*!< SCU_CLK SYSCLKCR: SYSSEL Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CPUCLKCR  ------------------------------ */\r
+#define SCU_CLK_CPUCLKCR_CPUDIV_Pos           0                                                       /*!< SCU_CLK CPUCLKCR: CPUDIV Position       */\r
+#define SCU_CLK_CPUCLKCR_CPUDIV_Msk           (0x01UL << SCU_CLK_CPUCLKCR_CPUDIV_Pos)                 /*!< SCU_CLK CPUCLKCR: CPUDIV Mask           */\r
+\r
+/* -------------------------------  SCU_CLK_PBCLKCR  ------------------------------ */\r
+#define SCU_CLK_PBCLKCR_PBDIV_Pos             0                                                       /*!< SCU_CLK PBCLKCR: PBDIV Position         */\r
+#define SCU_CLK_PBCLKCR_PBDIV_Msk             (0x01UL << SCU_CLK_PBCLKCR_PBDIV_Pos)                   /*!< SCU_CLK PBCLKCR: PBDIV Mask             */\r
+\r
+/* ------------------------------  SCU_CLK_USBCLKCR  ------------------------------ */\r
+#define SCU_CLK_USBCLKCR_USBDIV_Pos           0                                                       /*!< SCU_CLK USBCLKCR: USBDIV Position       */\r
+#define SCU_CLK_USBCLKCR_USBDIV_Msk           (0x07UL << SCU_CLK_USBCLKCR_USBDIV_Pos)                 /*!< SCU_CLK USBCLKCR: USBDIV Mask           */\r
+#define SCU_CLK_USBCLKCR_USBSEL_Pos           16                                                      /*!< SCU_CLK USBCLKCR: USBSEL Position       */\r
+#define SCU_CLK_USBCLKCR_USBSEL_Msk           (0x01UL << SCU_CLK_USBCLKCR_USBSEL_Pos)                 /*!< SCU_CLK USBCLKCR: USBSEL Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_EBUCLKCR  ------------------------------ */\r
+#define SCU_CLK_EBUCLKCR_EBUDIV_Pos           0                                                       /*!< SCU_CLK EBUCLKCR: EBUDIV Position       */\r
+#define SCU_CLK_EBUCLKCR_EBUDIV_Msk           (0x3fUL << SCU_CLK_EBUCLKCR_EBUDIV_Pos)                 /*!< SCU_CLK EBUCLKCR: EBUDIV Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_CCUCLKCR  ------------------------------ */\r
+#define SCU_CLK_CCUCLKCR_CCUDIV_Pos           0                                                       /*!< SCU_CLK CCUCLKCR: CCUDIV Position       */\r
+#define SCU_CLK_CCUCLKCR_CCUDIV_Msk           (0x01UL << SCU_CLK_CCUCLKCR_CCUDIV_Pos)                 /*!< SCU_CLK CCUCLKCR: CCUDIV Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_WDTCLKCR  ------------------------------ */\r
+#define SCU_CLK_WDTCLKCR_WDTDIV_Pos           0                                                       /*!< SCU_CLK WDTCLKCR: WDTDIV Position       */\r
+#define SCU_CLK_WDTCLKCR_WDTDIV_Msk           (0x000000ffUL << SCU_CLK_WDTCLKCR_WDTDIV_Pos)           /*!< SCU_CLK WDTCLKCR: WDTDIV Mask           */\r
+#define SCU_CLK_WDTCLKCR_WDTSEL_Pos           16                                                      /*!< SCU_CLK WDTCLKCR: WDTSEL Position       */\r
+#define SCU_CLK_WDTCLKCR_WDTSEL_Msk           (0x03UL << SCU_CLK_WDTCLKCR_WDTSEL_Pos)                 /*!< SCU_CLK WDTCLKCR: WDTSEL Mask           */\r
+\r
+/* ------------------------------  SCU_CLK_EXTCLKCR  ------------------------------ */\r
+#define SCU_CLK_EXTCLKCR_ECKSEL_Pos           0                                                       /*!< SCU_CLK EXTCLKCR: ECKSEL Position       */\r
+#define SCU_CLK_EXTCLKCR_ECKSEL_Msk           (0x03UL << SCU_CLK_EXTCLKCR_ECKSEL_Pos)                 /*!< SCU_CLK EXTCLKCR: ECKSEL Mask           */\r
+#define SCU_CLK_EXTCLKCR_ECKDIV_Pos           16                                                      /*!< SCU_CLK EXTCLKCR: ECKDIV Position       */\r
+#define SCU_CLK_EXTCLKCR_ECKDIV_Msk           (0x000001ffUL << SCU_CLK_EXTCLKCR_ECKDIV_Pos)           /*!< SCU_CLK EXTCLKCR: ECKDIV Mask           */\r
+\r
+/* -------------------------------  SCU_CLK_SLEEPCR  ------------------------------ */\r
+#define SCU_CLK_SLEEPCR_SYSSEL_Pos            0                                                       /*!< SCU_CLK SLEEPCR: SYSSEL Position        */\r
+#define SCU_CLK_SLEEPCR_SYSSEL_Msk            (0x01UL << SCU_CLK_SLEEPCR_SYSSEL_Pos)                  /*!< SCU_CLK SLEEPCR: SYSSEL Mask            */\r
+#define SCU_CLK_SLEEPCR_USBCR_Pos             16                                                      /*!< SCU_CLK SLEEPCR: USBCR Position         */\r
+#define SCU_CLK_SLEEPCR_USBCR_Msk             (0x01UL << SCU_CLK_SLEEPCR_USBCR_Pos)                   /*!< SCU_CLK SLEEPCR: USBCR Mask             */\r
+#define SCU_CLK_SLEEPCR_MMCCR_Pos             17                                                      /*!< SCU_CLK SLEEPCR: MMCCR Position         */\r
+#define SCU_CLK_SLEEPCR_MMCCR_Msk             (0x01UL << SCU_CLK_SLEEPCR_MMCCR_Pos)                   /*!< SCU_CLK SLEEPCR: MMCCR Mask             */\r
+#define SCU_CLK_SLEEPCR_ETH0CR_Pos            18                                                      /*!< SCU_CLK SLEEPCR: ETH0CR Position        */\r
+#define SCU_CLK_SLEEPCR_ETH0CR_Msk            (0x01UL << SCU_CLK_SLEEPCR_ETH0CR_Pos)                  /*!< SCU_CLK SLEEPCR: ETH0CR Mask            */\r
+#define SCU_CLK_SLEEPCR_EBUCR_Pos             19                                                      /*!< SCU_CLK SLEEPCR: EBUCR Position         */\r
+#define SCU_CLK_SLEEPCR_EBUCR_Msk             (0x01UL << SCU_CLK_SLEEPCR_EBUCR_Pos)                   /*!< SCU_CLK SLEEPCR: EBUCR Mask             */\r
+#define SCU_CLK_SLEEPCR_CCUCR_Pos             20                                                      /*!< SCU_CLK SLEEPCR: CCUCR Position         */\r
+#define SCU_CLK_SLEEPCR_CCUCR_Msk             (0x01UL << SCU_CLK_SLEEPCR_CCUCR_Pos)                   /*!< SCU_CLK SLEEPCR: CCUCR Mask             */\r
+#define SCU_CLK_SLEEPCR_WDTCR_Pos             21                                                      /*!< SCU_CLK SLEEPCR: WDTCR Position         */\r
+#define SCU_CLK_SLEEPCR_WDTCR_Msk             (0x01UL << SCU_CLK_SLEEPCR_WDTCR_Pos)                   /*!< SCU_CLK SLEEPCR: WDTCR Mask             */\r
+\r
+/* ------------------------------  SCU_CLK_DSLEEPCR  ------------------------------ */\r
+#define SCU_CLK_DSLEEPCR_SYSSEL_Pos           0                                                       /*!< SCU_CLK DSLEEPCR: SYSSEL Position       */\r
+#define SCU_CLK_DSLEEPCR_SYSSEL_Msk           (0x03UL << SCU_CLK_DSLEEPCR_SYSSEL_Pos)                 /*!< SCU_CLK DSLEEPCR: SYSSEL Mask           */\r
+#define SCU_CLK_DSLEEPCR_FPDN_Pos             11                                                      /*!< SCU_CLK DSLEEPCR: FPDN Position         */\r
+#define SCU_CLK_DSLEEPCR_FPDN_Msk             (0x01UL << SCU_CLK_DSLEEPCR_FPDN_Pos)                   /*!< SCU_CLK DSLEEPCR: FPDN Mask             */\r
+#define SCU_CLK_DSLEEPCR_PLLPDN_Pos           12                                                      /*!< SCU_CLK DSLEEPCR: PLLPDN Position       */\r
+#define SCU_CLK_DSLEEPCR_PLLPDN_Msk           (0x01UL << SCU_CLK_DSLEEPCR_PLLPDN_Pos)                 /*!< SCU_CLK DSLEEPCR: PLLPDN Mask           */\r
+#define SCU_CLK_DSLEEPCR_VCOPDN_Pos           13                                                      /*!< SCU_CLK DSLEEPCR: VCOPDN Position       */\r
+#define SCU_CLK_DSLEEPCR_VCOPDN_Msk           (0x01UL << SCU_CLK_DSLEEPCR_VCOPDN_Pos)                 /*!< SCU_CLK DSLEEPCR: VCOPDN Mask           */\r
+#define SCU_CLK_DSLEEPCR_USBCR_Pos            16                                                      /*!< SCU_CLK DSLEEPCR: USBCR Position        */\r
+#define SCU_CLK_DSLEEPCR_USBCR_Msk            (0x01UL << SCU_CLK_DSLEEPCR_USBCR_Pos)                  /*!< SCU_CLK DSLEEPCR: USBCR Mask            */\r
+#define SCU_CLK_DSLEEPCR_MMCCR_Pos            17                                                      /*!< SCU_CLK DSLEEPCR: MMCCR Position        */\r
+#define SCU_CLK_DSLEEPCR_MMCCR_Msk            (0x01UL << SCU_CLK_DSLEEPCR_MMCCR_Pos)                  /*!< SCU_CLK DSLEEPCR: MMCCR Mask            */\r
+#define SCU_CLK_DSLEEPCR_ETH0CR_Pos           18                                                      /*!< SCU_CLK DSLEEPCR: ETH0CR Position       */\r
+#define SCU_CLK_DSLEEPCR_ETH0CR_Msk           (0x01UL << SCU_CLK_DSLEEPCR_ETH0CR_Pos)                 /*!< SCU_CLK DSLEEPCR: ETH0CR Mask           */\r
+#define SCU_CLK_DSLEEPCR_EBUCR_Pos            19                                                      /*!< SCU_CLK DSLEEPCR: EBUCR Position        */\r
+#define SCU_CLK_DSLEEPCR_EBUCR_Msk            (0x01UL << SCU_CLK_DSLEEPCR_EBUCR_Pos)                  /*!< SCU_CLK DSLEEPCR: EBUCR Mask            */\r
+#define SCU_CLK_DSLEEPCR_CCUCR_Pos            20                                                      /*!< SCU_CLK DSLEEPCR: CCUCR Position        */\r
+#define SCU_CLK_DSLEEPCR_CCUCR_Msk            (0x01UL << SCU_CLK_DSLEEPCR_CCUCR_Pos)                  /*!< SCU_CLK DSLEEPCR: CCUCR Mask            */\r
+#define SCU_CLK_DSLEEPCR_WDTCR_Pos            21                                                      /*!< SCU_CLK DSLEEPCR: WDTCR Position        */\r
+#define SCU_CLK_DSLEEPCR_WDTCR_Msk            (0x01UL << SCU_CLK_DSLEEPCR_WDTCR_Pos)                  /*!< SCU_CLK DSLEEPCR: WDTCR Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_OSC' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_OSC_OSCHPSTAT  ----------------------------- */\r
+#define SCU_OSC_OSCHPSTAT_X1D_Pos             0                                                       /*!< SCU_OSC OSCHPSTAT: X1D Position         */\r
+#define SCU_OSC_OSCHPSTAT_X1D_Msk             (0x01UL << SCU_OSC_OSCHPSTAT_X1D_Pos)                   /*!< SCU_OSC OSCHPSTAT: X1D Mask             */\r
+\r
+/* ------------------------------  SCU_OSC_OSCHPCTRL  ----------------------------- */\r
+#define SCU_OSC_OSCHPCTRL_X1DEN_Pos           0                                                       /*!< SCU_OSC OSCHPCTRL: X1DEN Position       */\r
+#define SCU_OSC_OSCHPCTRL_X1DEN_Msk           (0x01UL << SCU_OSC_OSCHPCTRL_X1DEN_Pos)                 /*!< SCU_OSC OSCHPCTRL: X1DEN Mask           */\r
+#define SCU_OSC_OSCHPCTRL_SHBY_Pos            1                                                       /*!< SCU_OSC OSCHPCTRL: SHBY Position        */\r
+#define SCU_OSC_OSCHPCTRL_SHBY_Msk            (0x01UL << SCU_OSC_OSCHPCTRL_SHBY_Pos)                  /*!< SCU_OSC OSCHPCTRL: SHBY Mask            */\r
+#define SCU_OSC_OSCHPCTRL_MODE_Pos            4                                                       /*!< SCU_OSC OSCHPCTRL: MODE Position        */\r
+#define SCU_OSC_OSCHPCTRL_MODE_Msk            (0x03UL << SCU_OSC_OSCHPCTRL_MODE_Pos)                  /*!< SCU_OSC OSCHPCTRL: MODE Mask            */\r
+#define SCU_OSC_OSCHPCTRL_OSCVAL_Pos          16                                                      /*!< SCU_OSC OSCHPCTRL: OSCVAL Position      */\r
+#define SCU_OSC_OSCHPCTRL_OSCVAL_Msk          (0x1fUL << SCU_OSC_OSCHPCTRL_OSCVAL_Pos)                /*!< SCU_OSC OSCHPCTRL: OSCVAL Mask          */\r
+\r
+/* -----------------------------  SCU_OSC_CLKCALCONST  ---------------------------- */\r
+#define SCU_OSC_CLKCALCONST_CALIBCONST_Pos    0                                                       /*!< SCU_OSC CLKCALCONST: CALIBCONST Position */\r
+#define SCU_OSC_CLKCALCONST_CALIBCONST_Msk    (0x0fUL << SCU_OSC_CLKCALCONST_CALIBCONST_Pos)          /*!< SCU_OSC CLKCALCONST: CALIBCONST Mask    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_PLL' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_PLL_PLLSTAT  ------------------------------ */\r
+#define SCU_PLL_PLLSTAT_VCOBYST_Pos           0                                                       /*!< SCU_PLL PLLSTAT: VCOBYST Position       */\r
+#define SCU_PLL_PLLSTAT_VCOBYST_Msk           (0x01UL << SCU_PLL_PLLSTAT_VCOBYST_Pos)                 /*!< SCU_PLL PLLSTAT: VCOBYST Mask           */\r
+#define SCU_PLL_PLLSTAT_PWDSTAT_Pos           1                                                       /*!< SCU_PLL PLLSTAT: PWDSTAT Position       */\r
+#define SCU_PLL_PLLSTAT_PWDSTAT_Msk           (0x01UL << SCU_PLL_PLLSTAT_PWDSTAT_Pos)                 /*!< SCU_PLL PLLSTAT: PWDSTAT Mask           */\r
+#define SCU_PLL_PLLSTAT_VCOLOCK_Pos           2                                                       /*!< SCU_PLL PLLSTAT: VCOLOCK Position       */\r
+#define SCU_PLL_PLLSTAT_VCOLOCK_Msk           (0x01UL << SCU_PLL_PLLSTAT_VCOLOCK_Pos)                 /*!< SCU_PLL PLLSTAT: VCOLOCK Mask           */\r
+#define SCU_PLL_PLLSTAT_K1RDY_Pos             4                                                       /*!< SCU_PLL PLLSTAT: K1RDY Position         */\r
+#define SCU_PLL_PLLSTAT_K1RDY_Msk             (0x01UL << SCU_PLL_PLLSTAT_K1RDY_Pos)                   /*!< SCU_PLL PLLSTAT: K1RDY Mask             */\r
+#define SCU_PLL_PLLSTAT_K2RDY_Pos             5                                                       /*!< SCU_PLL PLLSTAT: K2RDY Position         */\r
+#define SCU_PLL_PLLSTAT_K2RDY_Msk             (0x01UL << SCU_PLL_PLLSTAT_K2RDY_Pos)                   /*!< SCU_PLL PLLSTAT: K2RDY Mask             */\r
+#define SCU_PLL_PLLSTAT_BY_Pos                6                                                       /*!< SCU_PLL PLLSTAT: BY Position            */\r
+#define SCU_PLL_PLLSTAT_BY_Msk                (0x01UL << SCU_PLL_PLLSTAT_BY_Pos)                      /*!< SCU_PLL PLLSTAT: BY Mask                */\r
+#define SCU_PLL_PLLSTAT_PLLLV_Pos             7                                                       /*!< SCU_PLL PLLSTAT: PLLLV Position         */\r
+#define SCU_PLL_PLLSTAT_PLLLV_Msk             (0x01UL << SCU_PLL_PLLSTAT_PLLLV_Pos)                   /*!< SCU_PLL PLLSTAT: PLLLV Mask             */\r
+#define SCU_PLL_PLLSTAT_PLLHV_Pos             8                                                       /*!< SCU_PLL PLLSTAT: PLLHV Position         */\r
+#define SCU_PLL_PLLSTAT_PLLHV_Msk             (0x01UL << SCU_PLL_PLLSTAT_PLLHV_Pos)                   /*!< SCU_PLL PLLSTAT: PLLHV Mask             */\r
+#define SCU_PLL_PLLSTAT_PLLSP_Pos             9                                                       /*!< SCU_PLL PLLSTAT: PLLSP Position         */\r
+#define SCU_PLL_PLLSTAT_PLLSP_Msk             (0x01UL << SCU_PLL_PLLSTAT_PLLSP_Pos)                   /*!< SCU_PLL PLLSTAT: PLLSP Mask             */\r
+\r
+/* -------------------------------  SCU_PLL_PLLCON0  ------------------------------ */\r
+#define SCU_PLL_PLLCON0_VCOBYP_Pos            0                                                       /*!< SCU_PLL PLLCON0: VCOBYP Position        */\r
+#define SCU_PLL_PLLCON0_VCOBYP_Msk            (0x01UL << SCU_PLL_PLLCON0_VCOBYP_Pos)                  /*!< SCU_PLL PLLCON0: VCOBYP Mask            */\r
+#define SCU_PLL_PLLCON0_VCOPWD_Pos            1                                                       /*!< SCU_PLL PLLCON0: VCOPWD Position        */\r
+#define SCU_PLL_PLLCON0_VCOPWD_Msk            (0x01UL << SCU_PLL_PLLCON0_VCOPWD_Pos)                  /*!< SCU_PLL PLLCON0: VCOPWD Mask            */\r
+#define SCU_PLL_PLLCON0_VCOTR_Pos             2                                                       /*!< SCU_PLL PLLCON0: VCOTR Position         */\r
+#define SCU_PLL_PLLCON0_VCOTR_Msk             (0x01UL << SCU_PLL_PLLCON0_VCOTR_Pos)                   /*!< SCU_PLL PLLCON0: VCOTR Mask             */\r
+#define SCU_PLL_PLLCON0_FINDIS_Pos            4                                                       /*!< SCU_PLL PLLCON0: FINDIS Position        */\r
+#define SCU_PLL_PLLCON0_FINDIS_Msk            (0x01UL << SCU_PLL_PLLCON0_FINDIS_Pos)                  /*!< SCU_PLL PLLCON0: FINDIS Mask            */\r
+#define SCU_PLL_PLLCON0_OSCDISCDIS_Pos        6                                                       /*!< SCU_PLL PLLCON0: OSCDISCDIS Position    */\r
+#define SCU_PLL_PLLCON0_OSCDISCDIS_Msk        (0x01UL << SCU_PLL_PLLCON0_OSCDISCDIS_Pos)              /*!< SCU_PLL PLLCON0: OSCDISCDIS Mask        */\r
+#define SCU_PLL_PLLCON0_PLLPWD_Pos            16                                                      /*!< SCU_PLL PLLCON0: PLLPWD Position        */\r
+#define SCU_PLL_PLLCON0_PLLPWD_Msk            (0x01UL << SCU_PLL_PLLCON0_PLLPWD_Pos)                  /*!< SCU_PLL PLLCON0: PLLPWD Mask            */\r
+#define SCU_PLL_PLLCON0_OSCRES_Pos            17                                                      /*!< SCU_PLL PLLCON0: OSCRES Position        */\r
+#define SCU_PLL_PLLCON0_OSCRES_Msk            (0x01UL << SCU_PLL_PLLCON0_OSCRES_Pos)                  /*!< SCU_PLL PLLCON0: OSCRES Mask            */\r
+#define SCU_PLL_PLLCON0_RESLD_Pos             18                                                      /*!< SCU_PLL PLLCON0: RESLD Position         */\r
+#define SCU_PLL_PLLCON0_RESLD_Msk             (0x01UL << SCU_PLL_PLLCON0_RESLD_Pos)                   /*!< SCU_PLL PLLCON0: RESLD Mask             */\r
+#define SCU_PLL_PLLCON0_AOTREN_Pos            19                                                      /*!< SCU_PLL PLLCON0: AOTREN Position        */\r
+#define SCU_PLL_PLLCON0_AOTREN_Msk            (0x01UL << SCU_PLL_PLLCON0_AOTREN_Pos)                  /*!< SCU_PLL PLLCON0: AOTREN Mask            */\r
+#define SCU_PLL_PLLCON0_FOTR_Pos              20                                                      /*!< SCU_PLL PLLCON0: FOTR Position          */\r
+#define SCU_PLL_PLLCON0_FOTR_Msk              (0x01UL << SCU_PLL_PLLCON0_FOTR_Pos)                    /*!< SCU_PLL PLLCON0: FOTR Mask              */\r
+\r
+/* -------------------------------  SCU_PLL_PLLCON1  ------------------------------ */\r
+#define SCU_PLL_PLLCON1_K1DIV_Pos             0                                                       /*!< SCU_PLL PLLCON1: K1DIV Position         */\r
+#define SCU_PLL_PLLCON1_K1DIV_Msk             (0x7fUL << SCU_PLL_PLLCON1_K1DIV_Pos)                   /*!< SCU_PLL PLLCON1: K1DIV Mask             */\r
+#define SCU_PLL_PLLCON1_NDIV_Pos              8                                                       /*!< SCU_PLL PLLCON1: NDIV Position          */\r
+#define SCU_PLL_PLLCON1_NDIV_Msk              (0x7fUL << SCU_PLL_PLLCON1_NDIV_Pos)                    /*!< SCU_PLL PLLCON1: NDIV Mask              */\r
+#define SCU_PLL_PLLCON1_K2DIV_Pos             16                                                      /*!< SCU_PLL PLLCON1: K2DIV Position         */\r
+#define SCU_PLL_PLLCON1_K2DIV_Msk             (0x7fUL << SCU_PLL_PLLCON1_K2DIV_Pos)                   /*!< SCU_PLL PLLCON1: K2DIV Mask             */\r
+#define SCU_PLL_PLLCON1_PDIV_Pos              24                                                      /*!< SCU_PLL PLLCON1: PDIV Position          */\r
+#define SCU_PLL_PLLCON1_PDIV_Msk              (0x0fUL << SCU_PLL_PLLCON1_PDIV_Pos)                    /*!< SCU_PLL PLLCON1: PDIV Mask              */\r
+\r
+/* -------------------------------  SCU_PLL_PLLCON2  ------------------------------ */\r
+#define SCU_PLL_PLLCON2_PINSEL_Pos            0                                                       /*!< SCU_PLL PLLCON2: PINSEL Position        */\r
+#define SCU_PLL_PLLCON2_PINSEL_Msk            (0x01UL << SCU_PLL_PLLCON2_PINSEL_Pos)                  /*!< SCU_PLL PLLCON2: PINSEL Mask            */\r
+#define SCU_PLL_PLLCON2_K1INSEL_Pos           8                                                       /*!< SCU_PLL PLLCON2: K1INSEL Position       */\r
+#define SCU_PLL_PLLCON2_K1INSEL_Msk           (0x01UL << SCU_PLL_PLLCON2_K1INSEL_Pos)                 /*!< SCU_PLL PLLCON2: K1INSEL Mask           */\r
+\r
+/* -----------------------------  SCU_PLL_USBPLLSTAT  ----------------------------- */\r
+#define SCU_PLL_USBPLLSTAT_VCOBYST_Pos        0                                                       /*!< SCU_PLL USBPLLSTAT: VCOBYST Position    */\r
+#define SCU_PLL_USBPLLSTAT_VCOBYST_Msk        (0x01UL << SCU_PLL_USBPLLSTAT_VCOBYST_Pos)              /*!< SCU_PLL USBPLLSTAT: VCOBYST Mask        */\r
+#define SCU_PLL_USBPLLSTAT_PWDSTAT_Pos        1                                                       /*!< SCU_PLL USBPLLSTAT: PWDSTAT Position    */\r
+#define SCU_PLL_USBPLLSTAT_PWDSTAT_Msk        (0x01UL << SCU_PLL_USBPLLSTAT_PWDSTAT_Pos)              /*!< SCU_PLL USBPLLSTAT: PWDSTAT Mask        */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCK_Pos        2                                                       /*!< SCU_PLL USBPLLSTAT: VCOLOCK Position    */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCK_Msk        (0x01UL << SCU_PLL_USBPLLSTAT_VCOLOCK_Pos)              /*!< SCU_PLL USBPLLSTAT: VCOLOCK Mask        */\r
+#define SCU_PLL_USBPLLSTAT_BY_Pos             6                                                       /*!< SCU_PLL USBPLLSTAT: BY Position         */\r
+#define SCU_PLL_USBPLLSTAT_BY_Msk             (0x01UL << SCU_PLL_USBPLLSTAT_BY_Pos)                   /*!< SCU_PLL USBPLLSTAT: BY Mask             */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos      7                                                       /*!< SCU_PLL USBPLLSTAT: VCOLOCKED Position  */\r
+#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk      (0x01UL << SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos)            /*!< SCU_PLL USBPLLSTAT: VCOLOCKED Mask      */\r
+\r
+/* ------------------------------  SCU_PLL_USBPLLCON  ----------------------------- */\r
+#define SCU_PLL_USBPLLCON_VCOBYP_Pos          0                                                       /*!< SCU_PLL USBPLLCON: VCOBYP Position      */\r
+#define SCU_PLL_USBPLLCON_VCOBYP_Msk          (0x01UL << SCU_PLL_USBPLLCON_VCOBYP_Pos)                /*!< SCU_PLL USBPLLCON: VCOBYP Mask          */\r
+#define SCU_PLL_USBPLLCON_VCOPWD_Pos          1                                                       /*!< SCU_PLL USBPLLCON: VCOPWD Position      */\r
+#define SCU_PLL_USBPLLCON_VCOPWD_Msk          (0x01UL << SCU_PLL_USBPLLCON_VCOPWD_Pos)                /*!< SCU_PLL USBPLLCON: VCOPWD Mask          */\r
+#define SCU_PLL_USBPLLCON_VCOTR_Pos           2                                                       /*!< SCU_PLL USBPLLCON: VCOTR Position       */\r
+#define SCU_PLL_USBPLLCON_VCOTR_Msk           (0x01UL << SCU_PLL_USBPLLCON_VCOTR_Pos)                 /*!< SCU_PLL USBPLLCON: VCOTR Mask           */\r
+#define SCU_PLL_USBPLLCON_FINDIS_Pos          4                                                       /*!< SCU_PLL USBPLLCON: FINDIS Position      */\r
+#define SCU_PLL_USBPLLCON_FINDIS_Msk          (0x01UL << SCU_PLL_USBPLLCON_FINDIS_Pos)                /*!< SCU_PLL USBPLLCON: FINDIS Mask          */\r
+#define SCU_PLL_USBPLLCON_OSCDISCDIS_Pos      6                                                       /*!< SCU_PLL USBPLLCON: OSCDISCDIS Position  */\r
+#define SCU_PLL_USBPLLCON_OSCDISCDIS_Msk      (0x01UL << SCU_PLL_USBPLLCON_OSCDISCDIS_Pos)            /*!< SCU_PLL USBPLLCON: OSCDISCDIS Mask      */\r
+#define SCU_PLL_USBPLLCON_NDIV_Pos            8                                                       /*!< SCU_PLL USBPLLCON: NDIV Position        */\r
+#define SCU_PLL_USBPLLCON_NDIV_Msk            (0x7fUL << SCU_PLL_USBPLLCON_NDIV_Pos)                  /*!< SCU_PLL USBPLLCON: NDIV Mask            */\r
+#define SCU_PLL_USBPLLCON_PLLPWD_Pos          16                                                      /*!< SCU_PLL USBPLLCON: PLLPWD Position      */\r
+#define SCU_PLL_USBPLLCON_PLLPWD_Msk          (0x01UL << SCU_PLL_USBPLLCON_PLLPWD_Pos)                /*!< SCU_PLL USBPLLCON: PLLPWD Mask          */\r
+#define SCU_PLL_USBPLLCON_RESLD_Pos           18                                                      /*!< SCU_PLL USBPLLCON: RESLD Position       */\r
+#define SCU_PLL_USBPLLCON_RESLD_Msk           (0x01UL << SCU_PLL_USBPLLCON_RESLD_Pos)                 /*!< SCU_PLL USBPLLCON: RESLD Mask           */\r
+#define SCU_PLL_USBPLLCON_PDIV_Pos            24                                                      /*!< SCU_PLL USBPLLCON: PDIV Position        */\r
+#define SCU_PLL_USBPLLCON_PDIV_Msk            (0x0fUL << SCU_PLL_USBPLLCON_PDIV_Pos)                  /*!< SCU_PLL USBPLLCON: PDIV Mask            */\r
+\r
+/* ------------------------------  SCU_PLL_CLKMXSTAT  ----------------------------- */\r
+#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos       0                                                       /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX Position   */\r
+#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk       (0x03UL << SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos)             /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX Mask       */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================      struct 'SCU_GENERAL' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_GENERAL_ID  ------------------------------- */\r
+#define SCU_GENERAL_ID_MOD_REV_Pos            0                                                       /*!< SCU_GENERAL ID: MOD_REV Position        */\r
+#define SCU_GENERAL_ID_MOD_REV_Msk            (0x000000ffUL << SCU_GENERAL_ID_MOD_REV_Pos)            /*!< SCU_GENERAL ID: MOD_REV Mask            */\r
+#define SCU_GENERAL_ID_MOD_TYPE_Pos           8                                                       /*!< SCU_GENERAL ID: MOD_TYPE Position       */\r
+#define SCU_GENERAL_ID_MOD_TYPE_Msk           (0x000000ffUL << SCU_GENERAL_ID_MOD_TYPE_Pos)           /*!< SCU_GENERAL ID: MOD_TYPE Mask           */\r
+#define SCU_GENERAL_ID_MOD_NUMBER_Pos         16                                                      /*!< SCU_GENERAL ID: MOD_NUMBER Position     */\r
+#define SCU_GENERAL_ID_MOD_NUMBER_Msk         (0x0000ffffUL << SCU_GENERAL_ID_MOD_NUMBER_Pos)         /*!< SCU_GENERAL ID: MOD_NUMBER Mask         */\r
+\r
+/* -----------------------------  SCU_GENERAL_IDCHIP  ----------------------------- */\r
+#define SCU_GENERAL_IDCHIP_IDCHIP_Pos         0                                                       /*!< SCU_GENERAL IDCHIP: IDCHIP Position     */\r
+#define SCU_GENERAL_IDCHIP_IDCHIP_Msk         (0xffffffffUL << SCU_GENERAL_IDCHIP_IDCHIP_Pos)         /*!< SCU_GENERAL IDCHIP: IDCHIP Mask         */\r
+\r
+/* -----------------------------  SCU_GENERAL_IDMANUF  ---------------------------- */\r
+#define SCU_GENERAL_IDMANUF_DEPT_Pos          0                                                       /*!< SCU_GENERAL IDMANUF: DEPT Position      */\r
+#define SCU_GENERAL_IDMANUF_DEPT_Msk          (0x1fUL << SCU_GENERAL_IDMANUF_DEPT_Pos)                /*!< SCU_GENERAL IDMANUF: DEPT Mask          */\r
+#define SCU_GENERAL_IDMANUF_MANUF_Pos         5                                                       /*!< SCU_GENERAL IDMANUF: MANUF Position     */\r
+#define SCU_GENERAL_IDMANUF_MANUF_Msk         (0x000007ffUL << SCU_GENERAL_IDMANUF_MANUF_Pos)         /*!< SCU_GENERAL IDMANUF: MANUF Mask         */\r
+\r
+/* ------------------------------  SCU_GENERAL_STCON  ----------------------------- */\r
+#define SCU_GENERAL_STCON_HWCON_Pos           0                                                       /*!< SCU_GENERAL STCON: HWCON Position       */\r
+#define SCU_GENERAL_STCON_HWCON_Msk           (0x03UL << SCU_GENERAL_STCON_HWCON_Pos)                 /*!< SCU_GENERAL STCON: HWCON Mask           */\r
+#define SCU_GENERAL_STCON_SWCON_Pos           8                                                       /*!< SCU_GENERAL STCON: SWCON Position       */\r
+#define SCU_GENERAL_STCON_SWCON_Msk           (0x0fUL << SCU_GENERAL_STCON_SWCON_Pos)                 /*!< SCU_GENERAL STCON: SWCON Mask           */\r
+\r
+/* -------------------------------  SCU_GENERAL_GPR  ------------------------------ */\r
+#define SCU_GENERAL_GPR_DAT_Pos               0                                                       /*!< SCU_GENERAL GPR: DAT Position           */\r
+#define SCU_GENERAL_GPR_DAT_Msk               (0xffffffffUL << SCU_GENERAL_GPR_DAT_Pos)               /*!< SCU_GENERAL GPR: DAT Mask               */\r
+\r
+/* -----------------------------  SCU_GENERAL_CCUCON  ----------------------------- */\r
+#define SCU_GENERAL_CCUCON_GSC40_Pos          0                                                       /*!< SCU_GENERAL CCUCON: GSC40 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC40_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC40_Pos)                /*!< SCU_GENERAL CCUCON: GSC40 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC41_Pos          1                                                       /*!< SCU_GENERAL CCUCON: GSC41 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC41_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC41_Pos)                /*!< SCU_GENERAL CCUCON: GSC41 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC42_Pos          2                                                       /*!< SCU_GENERAL CCUCON: GSC42 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC42_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC42_Pos)                /*!< SCU_GENERAL CCUCON: GSC42 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC43_Pos          3                                                       /*!< SCU_GENERAL CCUCON: GSC43 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC43_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC43_Pos)                /*!< SCU_GENERAL CCUCON: GSC43 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC80_Pos          8                                                       /*!< SCU_GENERAL CCUCON: GSC80 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC80_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC80_Pos)                /*!< SCU_GENERAL CCUCON: GSC80 Mask          */\r
+#define SCU_GENERAL_CCUCON_GSC81_Pos          9                                                       /*!< SCU_GENERAL CCUCON: GSC81 Position      */\r
+#define SCU_GENERAL_CCUCON_GSC81_Msk          (0x01UL << SCU_GENERAL_CCUCON_GSC81_Pos)                /*!< SCU_GENERAL CCUCON: GSC81 Mask          */\r
+\r
+/* -----------------------------  SCU_GENERAL_DTSCON  ----------------------------- */\r
+#define SCU_GENERAL_DTSCON_PWD_Pos            0                                                       /*!< SCU_GENERAL DTSCON: PWD Position        */\r
+#define SCU_GENERAL_DTSCON_PWD_Msk            (0x01UL << SCU_GENERAL_DTSCON_PWD_Pos)                  /*!< SCU_GENERAL DTSCON: PWD Mask            */\r
+#define SCU_GENERAL_DTSCON_START_Pos          1                                                       /*!< SCU_GENERAL DTSCON: START Position      */\r
+#define SCU_GENERAL_DTSCON_START_Msk          (0x01UL << SCU_GENERAL_DTSCON_START_Pos)                /*!< SCU_GENERAL DTSCON: START Mask          */\r
+#define SCU_GENERAL_DTSCON_OFFSET_Pos         4                                                       /*!< SCU_GENERAL DTSCON: OFFSET Position     */\r
+#define SCU_GENERAL_DTSCON_OFFSET_Msk         (0x7fUL << SCU_GENERAL_DTSCON_OFFSET_Pos)               /*!< SCU_GENERAL DTSCON: OFFSET Mask         */\r
+#define SCU_GENERAL_DTSCON_GAIN_Pos           11                                                      /*!< SCU_GENERAL DTSCON: GAIN Position       */\r
+#define SCU_GENERAL_DTSCON_GAIN_Msk           (0x3fUL << SCU_GENERAL_DTSCON_GAIN_Pos)                 /*!< SCU_GENERAL DTSCON: GAIN Mask           */\r
+#define SCU_GENERAL_DTSCON_REFTRIM_Pos        17                                                      /*!< SCU_GENERAL DTSCON: REFTRIM Position    */\r
+#define SCU_GENERAL_DTSCON_REFTRIM_Msk        (0x07UL << SCU_GENERAL_DTSCON_REFTRIM_Pos)              /*!< SCU_GENERAL DTSCON: REFTRIM Mask        */\r
+#define SCU_GENERAL_DTSCON_BGTRIM_Pos         20                                                      /*!< SCU_GENERAL DTSCON: BGTRIM Position     */\r
+#define SCU_GENERAL_DTSCON_BGTRIM_Msk         (0x0fUL << SCU_GENERAL_DTSCON_BGTRIM_Pos)               /*!< SCU_GENERAL DTSCON: BGTRIM Mask         */\r
+\r
+/* -----------------------------  SCU_GENERAL_DTSSTAT  ---------------------------- */\r
+#define SCU_GENERAL_DTSSTAT_RESULT_Pos        0                                                       /*!< SCU_GENERAL DTSSTAT: RESULT Position    */\r
+#define SCU_GENERAL_DTSSTAT_RESULT_Msk        (0x000003ffUL << SCU_GENERAL_DTSSTAT_RESULT_Pos)        /*!< SCU_GENERAL DTSSTAT: RESULT Mask        */\r
+#define SCU_GENERAL_DTSSTAT_RDY_Pos           14                                                      /*!< SCU_GENERAL DTSSTAT: RDY Position       */\r
+#define SCU_GENERAL_DTSSTAT_RDY_Msk           (0x01UL << SCU_GENERAL_DTSSTAT_RDY_Pos)                 /*!< SCU_GENERAL DTSSTAT: RDY Mask           */\r
+#define SCU_GENERAL_DTSSTAT_BUSY_Pos          15                                                      /*!< SCU_GENERAL DTSSTAT: BUSY Position      */\r
+#define SCU_GENERAL_DTSSTAT_BUSY_Msk          (0x01UL << SCU_GENERAL_DTSSTAT_BUSY_Pos)                /*!< SCU_GENERAL DTSSTAT: BUSY Mask          */\r
+\r
+/* ----------------------------  SCU_GENERAL_SDMMCDEL  ---------------------------- */\r
+#define SCU_GENERAL_SDMMCDEL_TAPEN_Pos        0                                                       /*!< SCU_GENERAL SDMMCDEL: TAPEN Position    */\r
+#define SCU_GENERAL_SDMMCDEL_TAPEN_Msk        (0x01UL << SCU_GENERAL_SDMMCDEL_TAPEN_Pos)              /*!< SCU_GENERAL SDMMCDEL: TAPEN Mask        */\r
+#define SCU_GENERAL_SDMMCDEL_TAPDEL_Pos       4                                                       /*!< SCU_GENERAL SDMMCDEL: TAPDEL Position   */\r
+#define SCU_GENERAL_SDMMCDEL_TAPDEL_Msk       (0x0fUL << SCU_GENERAL_SDMMCDEL_TAPDEL_Pos)             /*!< SCU_GENERAL SDMMCDEL: TAPDEL Mask       */\r
+\r
+/* -----------------------------  SCU_GENERAL_GORCEN  ----------------------------- */\r
+#define SCU_GENERAL_GORCEN_ENORC6_Pos         6                                                       /*!< SCU_GENERAL GORCEN: ENORC6 Position     */\r
+#define SCU_GENERAL_GORCEN_ENORC6_Msk         (0x01UL << SCU_GENERAL_GORCEN_ENORC6_Pos)               /*!< SCU_GENERAL GORCEN: ENORC6 Mask         */\r
+#define SCU_GENERAL_GORCEN_ENORC7_Pos         7                                                       /*!< SCU_GENERAL GORCEN: ENORC7 Position     */\r
+#define SCU_GENERAL_GORCEN_ENORC7_Msk         (0x01UL << SCU_GENERAL_GORCEN_ENORC7_Pos)               /*!< SCU_GENERAL GORCEN: ENORC7 Mask         */\r
+\r
+/* -----------------------------  SCU_GENERAL_MIRRSTS  ---------------------------- */\r
+#define SCU_GENERAL_MIRRSTS_HDCLR_Pos         1                                                       /*!< SCU_GENERAL MIRRSTS: HDCLR Position     */\r
+#define SCU_GENERAL_MIRRSTS_HDCLR_Msk         (0x01UL << SCU_GENERAL_MIRRSTS_HDCLR_Pos)               /*!< SCU_GENERAL MIRRSTS: HDCLR Mask         */\r
+#define SCU_GENERAL_MIRRSTS_HDSET_Pos         2                                                       /*!< SCU_GENERAL MIRRSTS: HDSET Position     */\r
+#define SCU_GENERAL_MIRRSTS_HDSET_Msk         (0x01UL << SCU_GENERAL_MIRRSTS_HDSET_Pos)               /*!< SCU_GENERAL MIRRSTS: HDSET Mask         */\r
+#define SCU_GENERAL_MIRRSTS_HDCR_Pos          3                                                       /*!< SCU_GENERAL MIRRSTS: HDCR Position      */\r
+#define SCU_GENERAL_MIRRSTS_HDCR_Msk          (0x01UL << SCU_GENERAL_MIRRSTS_HDCR_Pos)                /*!< SCU_GENERAL MIRRSTS: HDCR Mask          */\r
+#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos     5                                                       /*!< SCU_GENERAL MIRRSTS: OSCSICTRL Position */\r
+#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos)           /*!< SCU_GENERAL MIRRSTS: OSCSICTRL Mask     */\r
+#define SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos     6                                                       /*!< SCU_GENERAL MIRRSTS: OSCULSTAT Position */\r
+#define SCU_GENERAL_MIRRSTS_OSCULSTAT_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_OSCULSTAT_Pos)           /*!< SCU_GENERAL MIRRSTS: OSCULSTAT Mask     */\r
+#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos     7                                                       /*!< SCU_GENERAL MIRRSTS: OSCULCTRL Position */\r
+#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos)           /*!< SCU_GENERAL MIRRSTS: OSCULCTRL Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos       8                                                       /*!< SCU_GENERAL MIRRSTS: RTC_CTR Position   */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk       (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CTR_Pos)             /*!< SCU_GENERAL MIRRSTS: RTC_CTR Mask       */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos     9                                                       /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos     10                                                      /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos      11                                                      /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Position  */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk      (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos)            /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Mask      */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos      12                                                      /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Position  */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk      (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos)            /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Mask      */\r
+#define SCU_GENERAL_MIRRSTS_RMX_Pos           13                                                      /*!< SCU_GENERAL MIRRSTS: RMX Position       */\r
+#define SCU_GENERAL_MIRRSTS_RMX_Msk           (0x01UL << SCU_GENERAL_MIRRSTS_RMX_Pos)                 /*!< SCU_GENERAL MIRRSTS: RMX Mask           */\r
+#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos     14                                                      /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR Mask     */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos     15                                                      /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk     (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos)           /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR Mask     */\r
+\r
+/* ------------------------------  SCU_GENERAL_RMACR  ----------------------------- */\r
+#define SCU_GENERAL_RMACR_RDWR_Pos            0                                                       /*!< SCU_GENERAL RMACR: RDWR Position        */\r
+#define SCU_GENERAL_RMACR_RDWR_Msk            (0x01UL << SCU_GENERAL_RMACR_RDWR_Pos)                  /*!< SCU_GENERAL RMACR: RDWR Mask            */\r
+#define SCU_GENERAL_RMACR_ADDR_Pos            16                                                      /*!< SCU_GENERAL RMACR: ADDR Position        */\r
+#define SCU_GENERAL_RMACR_ADDR_Msk            (0x0fUL << SCU_GENERAL_RMACR_ADDR_Pos)                  /*!< SCU_GENERAL RMACR: ADDR Mask            */\r
+\r
+/* -----------------------------  SCU_GENERAL_RMDATA  ----------------------------- */\r
+#define SCU_GENERAL_RMDATA_DATA_Pos           0                                                       /*!< SCU_GENERAL RMDATA: DATA Position       */\r
+#define SCU_GENERAL_RMDATA_DATA_Msk           (0xffffffffUL << SCU_GENERAL_RMDATA_DATA_Pos)           /*!< SCU_GENERAL RMDATA: DATA Mask           */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================     struct 'SCU_INTERRUPT' Position & Mask     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------  SCU_INTERRUPT_SRSTAT  ---------------------------- */\r
+#define SCU_INTERRUPT_SRSTAT_PRWARN_Pos       0                                                       /*!< SCU_INTERRUPT SRSTAT: PRWARN Position   */\r
+#define SCU_INTERRUPT_SRSTAT_PRWARN_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_PRWARN_Pos)             /*!< SCU_INTERRUPT SRSTAT: PRWARN Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_PI_Pos           1                                                       /*!< SCU_INTERRUPT SRSTAT: PI Position       */\r
+#define SCU_INTERRUPT_SRSTAT_PI_Msk           (0x01UL << SCU_INTERRUPT_SRSTAT_PI_Pos)                 /*!< SCU_INTERRUPT SRSTAT: PI Mask           */\r
+#define SCU_INTERRUPT_SRSTAT_AI_Pos           2                                                       /*!< SCU_INTERRUPT SRSTAT: AI Position       */\r
+#define SCU_INTERRUPT_SRSTAT_AI_Msk           (0x01UL << SCU_INTERRUPT_SRSTAT_AI_Pos)                 /*!< SCU_INTERRUPT SRSTAT: AI Mask           */\r
+#define SCU_INTERRUPT_SRSTAT_DLROVR_Pos       3                                                       /*!< SCU_INTERRUPT SRSTAT: DLROVR Position   */\r
+#define SCU_INTERRUPT_SRSTAT_DLROVR_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_DLROVR_Pos)             /*!< SCU_INTERRUPT SRSTAT: DLROVR Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_HDSTAT_Pos       16                                                      /*!< SCU_INTERRUPT SRSTAT: HDSTAT Position   */\r
+#define SCU_INTERRUPT_SRSTAT_HDSTAT_Msk       (0x01UL << SCU_INTERRUPT_SRSTAT_HDSTAT_Pos)             /*!< SCU_INTERRUPT SRSTAT: HDSTAT Mask       */\r
+#define SCU_INTERRUPT_SRSTAT_HDCLR_Pos        17                                                      /*!< SCU_INTERRUPT SRSTAT: HDCLR Position    */\r
+#define SCU_INTERRUPT_SRSTAT_HDCLR_Msk        (0x01UL << SCU_INTERRUPT_SRSTAT_HDCLR_Pos)              /*!< SCU_INTERRUPT SRSTAT: HDCLR Mask        */\r
+#define SCU_INTERRUPT_SRSTAT_HDSET_Pos        18                                                      /*!< SCU_INTERRUPT SRSTAT: HDSET Position    */\r
+#define SCU_INTERRUPT_SRSTAT_HDSET_Msk        (0x01UL << SCU_INTERRUPT_SRSTAT_HDSET_Pos)              /*!< SCU_INTERRUPT SRSTAT: HDSET Mask        */\r
+#define SCU_INTERRUPT_SRSTAT_HDCR_Pos         19                                                      /*!< SCU_INTERRUPT SRSTAT: HDCR Position     */\r
+#define SCU_INTERRUPT_SRSTAT_HDCR_Msk         (0x01UL << SCU_INTERRUPT_SRSTAT_HDCR_Pos)               /*!< SCU_INTERRUPT SRSTAT: HDCR Mask         */\r
+#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos    21                                                      /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos)          /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos    22                                                      /*!< SCU_INTERRUPT SRSTAT: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULSTAT_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_OSCULSTAT_Pos)          /*!< SCU_INTERRUPT SRSTAT: OSCULSTAT Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos    23                                                      /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos)          /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos      24                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_CTR Position  */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk      (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos)            /*!< SCU_INTERRUPT SRSTAT: RTC_CTR Mask      */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos    25                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos)          /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos    26                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk    (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos)          /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 Mask    */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos     27                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk     (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos)           /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 Mask     */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos     28                                                      /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 Position */\r
+#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk     (0x01UL << SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos)           /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 Mask     */\r
+#define SCU_INTERRUPT_SRSTAT_RMX_Pos          29                                                      /*!< SCU_INTERRUPT SRSTAT: RMX Position      */\r
+#define SCU_INTERRUPT_SRSTAT_RMX_Msk          (0x01UL << SCU_INTERRUPT_SRSTAT_RMX_Pos)                /*!< SCU_INTERRUPT SRSTAT: RMX Mask          */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRRAW  ---------------------------- */\r
+#define SCU_INTERRUPT_SRRAW_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRRAW: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRRAW_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_PRWARN_Pos)              /*!< SCU_INTERRUPT SRRAW: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRRAW_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRRAW: PI Position        */\r
+#define SCU_INTERRUPT_SRRAW_PI_Msk            (0x01UL << SCU_INTERRUPT_SRRAW_PI_Pos)                  /*!< SCU_INTERRUPT SRRAW: PI Mask            */\r
+#define SCU_INTERRUPT_SRRAW_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRRAW: AI Position        */\r
+#define SCU_INTERRUPT_SRRAW_AI_Msk            (0x01UL << SCU_INTERRUPT_SRRAW_AI_Pos)                  /*!< SCU_INTERRUPT SRRAW: AI Mask            */\r
+#define SCU_INTERRUPT_SRRAW_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRRAW: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRRAW_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_DLROVR_Pos)              /*!< SCU_INTERRUPT SRRAW: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRRAW_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRRAW: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRRAW_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRRAW_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRRAW: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRRAW_HDCLR_Pos         17                                                      /*!< SCU_INTERRUPT SRRAW: HDCLR Position     */\r
+#define SCU_INTERRUPT_SRRAW_HDCLR_Msk         (0x01UL << SCU_INTERRUPT_SRRAW_HDCLR_Pos)               /*!< SCU_INTERRUPT SRRAW: HDCLR Mask         */\r
+#define SCU_INTERRUPT_SRRAW_HDSET_Pos         18                                                      /*!< SCU_INTERRUPT SRRAW: HDSET Position     */\r
+#define SCU_INTERRUPT_SRRAW_HDSET_Msk         (0x01UL << SCU_INTERRUPT_SRRAW_HDSET_Pos)               /*!< SCU_INTERRUPT SRRAW: HDSET Mask         */\r
+#define SCU_INTERRUPT_SRRAW_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRRAW: HDCR Position      */\r
+#define SCU_INTERRUPT_SRRAW_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRRAW_HDCR_Pos)                /*!< SCU_INTERRUPT SRRAW: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRRAW: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRRAW: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRRAW: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRRAW_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRRAW: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRRAW: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRRAW: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRRAW: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRRAW_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRRAW: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRRAW_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRRAW: RMX Position       */\r
+#define SCU_INTERRUPT_SRRAW_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRRAW_RMX_Pos)                 /*!< SCU_INTERRUPT SRRAW: RMX Mask           */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRMSK  ---------------------------- */\r
+#define SCU_INTERRUPT_SRMSK_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRMSK: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRMSK_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_PRWARN_Pos)              /*!< SCU_INTERRUPT SRMSK: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRMSK_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRMSK: PI Position        */\r
+#define SCU_INTERRUPT_SRMSK_PI_Msk            (0x01UL << SCU_INTERRUPT_SRMSK_PI_Pos)                  /*!< SCU_INTERRUPT SRMSK: PI Mask            */\r
+#define SCU_INTERRUPT_SRMSK_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRMSK: AI Position        */\r
+#define SCU_INTERRUPT_SRMSK_AI_Msk            (0x01UL << SCU_INTERRUPT_SRMSK_AI_Pos)                  /*!< SCU_INTERRUPT SRMSK: AI Mask            */\r
+#define SCU_INTERRUPT_SRMSK_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRMSK: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRMSK_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_DLROVR_Pos)              /*!< SCU_INTERRUPT SRMSK: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRMSK_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRMSK: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRMSK_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRMSK_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRMSK: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRMSK_HDCLR_Pos         17                                                      /*!< SCU_INTERRUPT SRMSK: HDCLR Position     */\r
+#define SCU_INTERRUPT_SRMSK_HDCLR_Msk         (0x01UL << SCU_INTERRUPT_SRMSK_HDCLR_Pos)               /*!< SCU_INTERRUPT SRMSK: HDCLR Mask         */\r
+#define SCU_INTERRUPT_SRMSK_HDSET_Pos         18                                                      /*!< SCU_INTERRUPT SRMSK: HDSET Position     */\r
+#define SCU_INTERRUPT_SRMSK_HDSET_Msk         (0x01UL << SCU_INTERRUPT_SRMSK_HDSET_Pos)               /*!< SCU_INTERRUPT SRMSK: HDSET Mask         */\r
+#define SCU_INTERRUPT_SRMSK_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRMSK: HDCR Position      */\r
+#define SCU_INTERRUPT_SRMSK_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRMSK_HDCR_Pos)                /*!< SCU_INTERRUPT SRMSK: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRMSK: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRMSK: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRMSK: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRMSK_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRMSK: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRMSK: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRMSK: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRMSK: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRMSK_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRMSK: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRMSK_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRMSK: RMX Position       */\r
+#define SCU_INTERRUPT_SRMSK_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRMSK_RMX_Pos)                 /*!< SCU_INTERRUPT SRMSK: RMX Mask           */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRCLR  ---------------------------- */\r
+#define SCU_INTERRUPT_SRCLR_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRCLR: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRCLR_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_PRWARN_Pos)              /*!< SCU_INTERRUPT SRCLR: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRCLR_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRCLR: PI Position        */\r
+#define SCU_INTERRUPT_SRCLR_PI_Msk            (0x01UL << SCU_INTERRUPT_SRCLR_PI_Pos)                  /*!< SCU_INTERRUPT SRCLR: PI Mask            */\r
+#define SCU_INTERRUPT_SRCLR_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRCLR: AI Position        */\r
+#define SCU_INTERRUPT_SRCLR_AI_Msk            (0x01UL << SCU_INTERRUPT_SRCLR_AI_Pos)                  /*!< SCU_INTERRUPT SRCLR: AI Mask            */\r
+#define SCU_INTERRUPT_SRCLR_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRCLR: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRCLR_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_DLROVR_Pos)              /*!< SCU_INTERRUPT SRCLR: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRCLR_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRCLR: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRCLR_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRCLR_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRCLR: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRCLR_HDCLR_Pos         17                                                      /*!< SCU_INTERRUPT SRCLR: HDCLR Position     */\r
+#define SCU_INTERRUPT_SRCLR_HDCLR_Msk         (0x01UL << SCU_INTERRUPT_SRCLR_HDCLR_Pos)               /*!< SCU_INTERRUPT SRCLR: HDCLR Mask         */\r
+#define SCU_INTERRUPT_SRCLR_HDSET_Pos         18                                                      /*!< SCU_INTERRUPT SRCLR: HDSET Position     */\r
+#define SCU_INTERRUPT_SRCLR_HDSET_Msk         (0x01UL << SCU_INTERRUPT_SRCLR_HDSET_Pos)               /*!< SCU_INTERRUPT SRCLR: HDSET Mask         */\r
+#define SCU_INTERRUPT_SRCLR_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRCLR: HDCR Position      */\r
+#define SCU_INTERRUPT_SRCLR_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRCLR_HDCR_Pos)                /*!< SCU_INTERRUPT SRCLR: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRCLR: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRCLR: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRCLR: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRCLR_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRCLR: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRCLR: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRCLR: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRCLR: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRCLR_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRCLR: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRCLR_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRCLR: RMX Position       */\r
+#define SCU_INTERRUPT_SRCLR_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRCLR_RMX_Pos)                 /*!< SCU_INTERRUPT SRCLR: RMX Mask           */\r
+\r
+/* -----------------------------  SCU_INTERRUPT_SRSET  ---------------------------- */\r
+#define SCU_INTERRUPT_SRSET_PRWARN_Pos        0                                                       /*!< SCU_INTERRUPT SRSET: PRWARN Position    */\r
+#define SCU_INTERRUPT_SRSET_PRWARN_Msk        (0x01UL << SCU_INTERRUPT_SRSET_PRWARN_Pos)              /*!< SCU_INTERRUPT SRSET: PRWARN Mask        */\r
+#define SCU_INTERRUPT_SRSET_PI_Pos            1                                                       /*!< SCU_INTERRUPT SRSET: PI Position        */\r
+#define SCU_INTERRUPT_SRSET_PI_Msk            (0x01UL << SCU_INTERRUPT_SRSET_PI_Pos)                  /*!< SCU_INTERRUPT SRSET: PI Mask            */\r
+#define SCU_INTERRUPT_SRSET_AI_Pos            2                                                       /*!< SCU_INTERRUPT SRSET: AI Position        */\r
+#define SCU_INTERRUPT_SRSET_AI_Msk            (0x01UL << SCU_INTERRUPT_SRSET_AI_Pos)                  /*!< SCU_INTERRUPT SRSET: AI Mask            */\r
+#define SCU_INTERRUPT_SRSET_DLROVR_Pos        3                                                       /*!< SCU_INTERRUPT SRSET: DLROVR Position    */\r
+#define SCU_INTERRUPT_SRSET_DLROVR_Msk        (0x01UL << SCU_INTERRUPT_SRSET_DLROVR_Pos)              /*!< SCU_INTERRUPT SRSET: DLROVR Mask        */\r
+#define SCU_INTERRUPT_SRSET_HDSTAT_Pos        16                                                      /*!< SCU_INTERRUPT SRSET: HDSTAT Position    */\r
+#define SCU_INTERRUPT_SRSET_HDSTAT_Msk        (0x01UL << SCU_INTERRUPT_SRSET_HDSTAT_Pos)              /*!< SCU_INTERRUPT SRSET: HDSTAT Mask        */\r
+#define SCU_INTERRUPT_SRSET_HDCRCLR_Pos       17                                                      /*!< SCU_INTERRUPT SRSET: HDCRCLR Position   */\r
+#define SCU_INTERRUPT_SRSET_HDCRCLR_Msk       (0x01UL << SCU_INTERRUPT_SRSET_HDCRCLR_Pos)             /*!< SCU_INTERRUPT SRSET: HDCRCLR Mask       */\r
+#define SCU_INTERRUPT_SRSET_HDCRSET_Pos       18                                                      /*!< SCU_INTERRUPT SRSET: HDCRSET Position   */\r
+#define SCU_INTERRUPT_SRSET_HDCRSET_Msk       (0x01UL << SCU_INTERRUPT_SRSET_HDCRSET_Pos)             /*!< SCU_INTERRUPT SRSET: HDCRSET Mask       */\r
+#define SCU_INTERRUPT_SRSET_HDCR_Pos          19                                                      /*!< SCU_INTERRUPT SRSET: HDCR Position      */\r
+#define SCU_INTERRUPT_SRSET_HDCR_Msk          (0x01UL << SCU_INTERRUPT_SRSET_HDCR_Pos)                /*!< SCU_INTERRUPT SRSET: HDCR Mask          */\r
+#define SCU_INTERRUPT_SRSET_OSCSICTRL_Pos     21                                                      /*!< SCU_INTERRUPT SRSET: OSCSICTRL Position */\r
+#define SCU_INTERRUPT_SRSET_OSCSICTRL_Msk     (0x01UL << SCU_INTERRUPT_SRSET_OSCSICTRL_Pos)           /*!< SCU_INTERRUPT SRSET: OSCSICTRL Mask     */\r
+#define SCU_INTERRUPT_SRSET_OSCULSTAT_Pos     22                                                      /*!< SCU_INTERRUPT SRSET: OSCULSTAT Position */\r
+#define SCU_INTERRUPT_SRSET_OSCULSTAT_Msk     (0x01UL << SCU_INTERRUPT_SRSET_OSCULSTAT_Pos)           /*!< SCU_INTERRUPT SRSET: OSCULSTAT Mask     */\r
+#define SCU_INTERRUPT_SRSET_OSCULCTRL_Pos     23                                                      /*!< SCU_INTERRUPT SRSET: OSCULCTRL Position */\r
+#define SCU_INTERRUPT_SRSET_OSCULCTRL_Msk     (0x01UL << SCU_INTERRUPT_SRSET_OSCULCTRL_Pos)           /*!< SCU_INTERRUPT SRSET: OSCULCTRL Mask     */\r
+#define SCU_INTERRUPT_SRSET_RTC_CTR_Pos       24                                                      /*!< SCU_INTERRUPT SRSET: RTC_CTR Position   */\r
+#define SCU_INTERRUPT_SRSET_RTC_CTR_Msk       (0x01UL << SCU_INTERRUPT_SRSET_RTC_CTR_Pos)             /*!< SCU_INTERRUPT SRSET: RTC_CTR Mask       */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos     25                                                      /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk     (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos)           /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Mask     */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos     26                                                      /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk     (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos)           /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Mask     */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos      27                                                      /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Position  */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk      (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM0_Pos)            /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Mask      */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos      28                                                      /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Position  */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk      (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM1_Pos)            /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Mask      */\r
+#define SCU_INTERRUPT_SRSET_RMX_Pos           29                                                      /*!< SCU_INTERRUPT SRSET: RMX Position       */\r
+#define SCU_INTERRUPT_SRSET_RMX_Msk           (0x01UL << SCU_INTERRUPT_SRSET_RMX_Pos)                 /*!< SCU_INTERRUPT SRSET: RMX Mask           */\r
+\r
+/* ---------------------------  SCU_INTERRUPT_NMIREQEN  --------------------------- */\r
+#define SCU_INTERRUPT_NMIREQEN_PRWARN_Pos     0                                                       /*!< SCU_INTERRUPT NMIREQEN: PRWARN Position */\r
+#define SCU_INTERRUPT_NMIREQEN_PRWARN_Msk     (0x01UL << SCU_INTERRUPT_NMIREQEN_PRWARN_Pos)           /*!< SCU_INTERRUPT NMIREQEN: PRWARN Mask     */\r
+#define SCU_INTERRUPT_NMIREQEN_PI_Pos         1                                                       /*!< SCU_INTERRUPT NMIREQEN: PI Position     */\r
+#define SCU_INTERRUPT_NMIREQEN_PI_Msk         (0x01UL << SCU_INTERRUPT_NMIREQEN_PI_Pos)               /*!< SCU_INTERRUPT NMIREQEN: PI Mask         */\r
+#define SCU_INTERRUPT_NMIREQEN_AI_Pos         2                                                       /*!< SCU_INTERRUPT NMIREQEN: AI Position     */\r
+#define SCU_INTERRUPT_NMIREQEN_AI_Msk         (0x01UL << SCU_INTERRUPT_NMIREQEN_AI_Pos)               /*!< SCU_INTERRUPT NMIREQEN: AI Mask         */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU00_Pos      16                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU00 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU00_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU00_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU00 Mask      */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU01_Pos      17                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU01 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU01_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU01_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU01 Mask      */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU02_Pos      18                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU02 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU02_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU02_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU02 Mask      */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU03_Pos      19                                                      /*!< SCU_INTERRUPT NMIREQEN: ERU03 Position  */\r
+#define SCU_INTERRUPT_NMIREQEN_ERU03_Msk      (0x01UL << SCU_INTERRUPT_NMIREQEN_ERU03_Pos)            /*!< SCU_INTERRUPT NMIREQEN: ERU03 Mask      */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       struct 'SCU_PARITY' Position & Mask      ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------  SCU_PARITY_PEEN  ------------------------------ */\r
+#define SCU_PARITY_PEEN_PEENPS_Pos            0                                                       /*!< SCU_PARITY PEEN: PEENPS Position        */\r
+#define SCU_PARITY_PEEN_PEENPS_Msk            (0x01UL << SCU_PARITY_PEEN_PEENPS_Pos)                  /*!< SCU_PARITY PEEN: PEENPS Mask            */\r
+#define SCU_PARITY_PEEN_PEENDS1_Pos           1                                                       /*!< SCU_PARITY PEEN: PEENDS1 Position       */\r
+#define SCU_PARITY_PEEN_PEENDS1_Msk           (0x01UL << SCU_PARITY_PEEN_PEENDS1_Pos)                 /*!< SCU_PARITY PEEN: PEENDS1 Mask           */\r
+#define SCU_PARITY_PEEN_PEENDS2_Pos           2                                                       /*!< SCU_PARITY PEEN: PEENDS2 Position       */\r
+#define SCU_PARITY_PEEN_PEENDS2_Msk           (0x01UL << SCU_PARITY_PEEN_PEENDS2_Pos)                 /*!< SCU_PARITY PEEN: PEENDS2 Mask           */\r
+#define SCU_PARITY_PEEN_PEENU0_Pos            8                                                       /*!< SCU_PARITY PEEN: PEENU0 Position        */\r
+#define SCU_PARITY_PEEN_PEENU0_Msk            (0x01UL << SCU_PARITY_PEEN_PEENU0_Pos)                  /*!< SCU_PARITY PEEN: PEENU0 Mask            */\r
+#define SCU_PARITY_PEEN_PEENU1_Pos            9                                                       /*!< SCU_PARITY PEEN: PEENU1 Position        */\r
+#define SCU_PARITY_PEEN_PEENU1_Msk            (0x01UL << SCU_PARITY_PEEN_PEENU1_Pos)                  /*!< SCU_PARITY PEEN: PEENU1 Mask            */\r
+#define SCU_PARITY_PEEN_PEENU2_Pos            10                                                      /*!< SCU_PARITY PEEN: PEENU2 Position        */\r
+#define SCU_PARITY_PEEN_PEENU2_Msk            (0x01UL << SCU_PARITY_PEEN_PEENU2_Pos)                  /*!< SCU_PARITY PEEN: PEENU2 Mask            */\r
+#define SCU_PARITY_PEEN_PEENMC_Pos            12                                                      /*!< SCU_PARITY PEEN: PEENMC Position        */\r
+#define SCU_PARITY_PEEN_PEENMC_Msk            (0x01UL << SCU_PARITY_PEEN_PEENMC_Pos)                  /*!< SCU_PARITY PEEN: PEENMC Mask            */\r
+#define SCU_PARITY_PEEN_PEENPPRF_Pos          13                                                      /*!< SCU_PARITY PEEN: PEENPPRF Position      */\r
+#define SCU_PARITY_PEEN_PEENPPRF_Msk          (0x01UL << SCU_PARITY_PEEN_PEENPPRF_Pos)                /*!< SCU_PARITY PEEN: PEENPPRF Mask          */\r
+#define SCU_PARITY_PEEN_PEENUSB_Pos           16                                                      /*!< SCU_PARITY PEEN: PEENUSB Position       */\r
+#define SCU_PARITY_PEEN_PEENUSB_Msk           (0x01UL << SCU_PARITY_PEEN_PEENUSB_Pos)                 /*!< SCU_PARITY PEEN: PEENUSB Mask           */\r
+#define SCU_PARITY_PEEN_PEENETH0TX_Pos        17                                                      /*!< SCU_PARITY PEEN: PEENETH0TX Position    */\r
+#define SCU_PARITY_PEEN_PEENETH0TX_Msk        (0x01UL << SCU_PARITY_PEEN_PEENETH0TX_Pos)              /*!< SCU_PARITY PEEN: PEENETH0TX Mask        */\r
+#define SCU_PARITY_PEEN_PEENETH0RX_Pos        18                                                      /*!< SCU_PARITY PEEN: PEENETH0RX Position    */\r
+#define SCU_PARITY_PEEN_PEENETH0RX_Msk        (0x01UL << SCU_PARITY_PEEN_PEENETH0RX_Pos)              /*!< SCU_PARITY PEEN: PEENETH0RX Mask        */\r
+#define SCU_PARITY_PEEN_PEENSD0_Pos           19                                                      /*!< SCU_PARITY PEEN: PEENSD0 Position       */\r
+#define SCU_PARITY_PEEN_PEENSD0_Msk           (0x01UL << SCU_PARITY_PEEN_PEENSD0_Pos)                 /*!< SCU_PARITY PEEN: PEENSD0 Mask           */\r
+#define SCU_PARITY_PEEN_PEENSD1_Pos           20                                                      /*!< SCU_PARITY PEEN: PEENSD1 Position       */\r
+#define SCU_PARITY_PEEN_PEENSD1_Msk           (0x01UL << SCU_PARITY_PEEN_PEENSD1_Pos)                 /*!< SCU_PARITY PEEN: PEENSD1 Mask           */\r
+\r
+/* -----------------------------  SCU_PARITY_MCHKCON  ----------------------------- */\r
+#define SCU_PARITY_MCHKCON_SELPS_Pos          0                                                       /*!< SCU_PARITY MCHKCON: SELPS Position      */\r
+#define SCU_PARITY_MCHKCON_SELPS_Msk          (0x01UL << SCU_PARITY_MCHKCON_SELPS_Pos)                /*!< SCU_PARITY MCHKCON: SELPS Mask          */\r
+#define SCU_PARITY_MCHKCON_SELDS1_Pos         1                                                       /*!< SCU_PARITY MCHKCON: SELDS1 Position     */\r
+#define SCU_PARITY_MCHKCON_SELDS1_Msk         (0x01UL << SCU_PARITY_MCHKCON_SELDS1_Pos)               /*!< SCU_PARITY MCHKCON: SELDS1 Mask         */\r
+#define SCU_PARITY_MCHKCON_SELDS2_Pos         2                                                       /*!< SCU_PARITY MCHKCON: SELDS2 Position     */\r
+#define SCU_PARITY_MCHKCON_SELDS2_Msk         (0x01UL << SCU_PARITY_MCHKCON_SELDS2_Pos)               /*!< SCU_PARITY MCHKCON: SELDS2 Mask         */\r
+#define SCU_PARITY_MCHKCON_USIC0DRA_Pos       8                                                       /*!< SCU_PARITY MCHKCON: USIC0DRA Position   */\r
+#define SCU_PARITY_MCHKCON_USIC0DRA_Msk       (0x01UL << SCU_PARITY_MCHKCON_USIC0DRA_Pos)             /*!< SCU_PARITY MCHKCON: USIC0DRA Mask       */\r
+#define SCU_PARITY_MCHKCON_USIC1DRA_Pos       9                                                       /*!< SCU_PARITY MCHKCON: USIC1DRA Position   */\r
+#define SCU_PARITY_MCHKCON_USIC1DRA_Msk       (0x01UL << SCU_PARITY_MCHKCON_USIC1DRA_Pos)             /*!< SCU_PARITY MCHKCON: USIC1DRA Mask       */\r
+#define SCU_PARITY_MCHKCON_USIC2DRA_Pos       10                                                      /*!< SCU_PARITY MCHKCON: USIC2DRA Position   */\r
+#define SCU_PARITY_MCHKCON_USIC2DRA_Msk       (0x01UL << SCU_PARITY_MCHKCON_USIC2DRA_Pos)             /*!< SCU_PARITY MCHKCON: USIC2DRA Mask       */\r
+#define SCU_PARITY_MCHKCON_MCANDRA_Pos        12                                                      /*!< SCU_PARITY MCHKCON: MCANDRA Position    */\r
+#define SCU_PARITY_MCHKCON_MCANDRA_Msk        (0x01UL << SCU_PARITY_MCHKCON_MCANDRA_Pos)              /*!< SCU_PARITY MCHKCON: MCANDRA Mask        */\r
+#define SCU_PARITY_MCHKCON_PPRFDRA_Pos        13                                                      /*!< SCU_PARITY MCHKCON: PPRFDRA Position    */\r
+#define SCU_PARITY_MCHKCON_PPRFDRA_Msk        (0x01UL << SCU_PARITY_MCHKCON_PPRFDRA_Pos)              /*!< SCU_PARITY MCHKCON: PPRFDRA Mask        */\r
+#define SCU_PARITY_MCHKCON_SELUSB_Pos         16                                                      /*!< SCU_PARITY MCHKCON: SELUSB Position     */\r
+#define SCU_PARITY_MCHKCON_SELUSB_Msk         (0x01UL << SCU_PARITY_MCHKCON_SELUSB_Pos)               /*!< SCU_PARITY MCHKCON: SELUSB Mask         */\r
+#define SCU_PARITY_MCHKCON_SELETH0TX_Pos      17                                                      /*!< SCU_PARITY MCHKCON: SELETH0TX Position  */\r
+#define SCU_PARITY_MCHKCON_SELETH0TX_Msk      (0x01UL << SCU_PARITY_MCHKCON_SELETH0TX_Pos)            /*!< SCU_PARITY MCHKCON: SELETH0TX Mask      */\r
+#define SCU_PARITY_MCHKCON_SELETH0RX_Pos      18                                                      /*!< SCU_PARITY MCHKCON: SELETH0RX Position  */\r
+#define SCU_PARITY_MCHKCON_SELETH0RX_Msk      (0x01UL << SCU_PARITY_MCHKCON_SELETH0RX_Pos)            /*!< SCU_PARITY MCHKCON: SELETH0RX Mask      */\r
+#define SCU_PARITY_MCHKCON_SELSD0_Pos         19                                                      /*!< SCU_PARITY MCHKCON: SELSD0 Position     */\r
+#define SCU_PARITY_MCHKCON_SELSD0_Msk         (0x01UL << SCU_PARITY_MCHKCON_SELSD0_Pos)               /*!< SCU_PARITY MCHKCON: SELSD0 Mask         */\r
+#define SCU_PARITY_MCHKCON_SELSD1_Pos         20                                                      /*!< SCU_PARITY MCHKCON: SELSD1 Position     */\r
+#define SCU_PARITY_MCHKCON_SELSD1_Msk         (0x01UL << SCU_PARITY_MCHKCON_SELSD1_Pos)               /*!< SCU_PARITY MCHKCON: SELSD1 Mask         */\r
+\r
+/* -------------------------------  SCU_PARITY_PETE  ------------------------------ */\r
+#define SCU_PARITY_PETE_PETEPS_Pos            0                                                       /*!< SCU_PARITY PETE: PETEPS Position        */\r
+#define SCU_PARITY_PETE_PETEPS_Msk            (0x01UL << SCU_PARITY_PETE_PETEPS_Pos)                  /*!< SCU_PARITY PETE: PETEPS Mask            */\r
+#define SCU_PARITY_PETE_PETEDS1_Pos           1                                                       /*!< SCU_PARITY PETE: PETEDS1 Position       */\r
+#define SCU_PARITY_PETE_PETEDS1_Msk           (0x01UL << SCU_PARITY_PETE_PETEDS1_Pos)                 /*!< SCU_PARITY PETE: PETEDS1 Mask           */\r
+#define SCU_PARITY_PETE_PETEDS2_Pos           2                                                       /*!< SCU_PARITY PETE: PETEDS2 Position       */\r
+#define SCU_PARITY_PETE_PETEDS2_Msk           (0x01UL << SCU_PARITY_PETE_PETEDS2_Pos)                 /*!< SCU_PARITY PETE: PETEDS2 Mask           */\r
+#define SCU_PARITY_PETE_PETEU0_Pos            8                                                       /*!< SCU_PARITY PETE: PETEU0 Position        */\r
+#define SCU_PARITY_PETE_PETEU0_Msk            (0x01UL << SCU_PARITY_PETE_PETEU0_Pos)                  /*!< SCU_PARITY PETE: PETEU0 Mask            */\r
+#define SCU_PARITY_PETE_PETEU1_Pos            9                                                       /*!< SCU_PARITY PETE: PETEU1 Position        */\r
+#define SCU_PARITY_PETE_PETEU1_Msk            (0x01UL << SCU_PARITY_PETE_PETEU1_Pos)                  /*!< SCU_PARITY PETE: PETEU1 Mask            */\r
+#define SCU_PARITY_PETE_PETEU2_Pos            10                                                      /*!< SCU_PARITY PETE: PETEU2 Position        */\r
+#define SCU_PARITY_PETE_PETEU2_Msk            (0x01UL << SCU_PARITY_PETE_PETEU2_Pos)                  /*!< SCU_PARITY PETE: PETEU2 Mask            */\r
+#define SCU_PARITY_PETE_PETEMC_Pos            12                                                      /*!< SCU_PARITY PETE: PETEMC Position        */\r
+#define SCU_PARITY_PETE_PETEMC_Msk            (0x01UL << SCU_PARITY_PETE_PETEMC_Pos)                  /*!< SCU_PARITY PETE: PETEMC Mask            */\r
+#define SCU_PARITY_PETE_PETEPPRF_Pos          13                                                      /*!< SCU_PARITY PETE: PETEPPRF Position      */\r
+#define SCU_PARITY_PETE_PETEPPRF_Msk          (0x01UL << SCU_PARITY_PETE_PETEPPRF_Pos)                /*!< SCU_PARITY PETE: PETEPPRF Mask          */\r
+#define SCU_PARITY_PETE_PETEUSB_Pos           16                                                      /*!< SCU_PARITY PETE: PETEUSB Position       */\r
+#define SCU_PARITY_PETE_PETEUSB_Msk           (0x01UL << SCU_PARITY_PETE_PETEUSB_Pos)                 /*!< SCU_PARITY PETE: PETEUSB Mask           */\r
+#define SCU_PARITY_PETE_PETEETH0TX_Pos        17                                                      /*!< SCU_PARITY PETE: PETEETH0TX Position    */\r
+#define SCU_PARITY_PETE_PETEETH0TX_Msk        (0x01UL << SCU_PARITY_PETE_PETEETH0TX_Pos)              /*!< SCU_PARITY PETE: PETEETH0TX Mask        */\r
+#define SCU_PARITY_PETE_PETEETH0RX_Pos        18                                                      /*!< SCU_PARITY PETE: PETEETH0RX Position    */\r
+#define SCU_PARITY_PETE_PETEETH0RX_Msk        (0x01UL << SCU_PARITY_PETE_PETEETH0RX_Pos)              /*!< SCU_PARITY PETE: PETEETH0RX Mask        */\r
+#define SCU_PARITY_PETE_PETESD0_Pos           19                                                      /*!< SCU_PARITY PETE: PETESD0 Position       */\r
+#define SCU_PARITY_PETE_PETESD0_Msk           (0x01UL << SCU_PARITY_PETE_PETESD0_Pos)                 /*!< SCU_PARITY PETE: PETESD0 Mask           */\r
+#define SCU_PARITY_PETE_PETESD1_Pos           20                                                      /*!< SCU_PARITY PETE: PETESD1 Position       */\r
+#define SCU_PARITY_PETE_PETESD1_Msk           (0x01UL << SCU_PARITY_PETE_PETESD1_Pos)                 /*!< SCU_PARITY PETE: PETESD1 Mask           */\r
+\r
+/* -----------------------------  SCU_PARITY_PERSTEN  ----------------------------- */\r
+#define SCU_PARITY_PERSTEN_RSEN_Pos           0                                                       /*!< SCU_PARITY PERSTEN: RSEN Position       */\r
+#define SCU_PARITY_PERSTEN_RSEN_Msk           (0x01UL << SCU_PARITY_PERSTEN_RSEN_Pos)                 /*!< SCU_PARITY PERSTEN: RSEN Mask           */\r
+\r
+/* ------------------------------  SCU_PARITY_PEFLAG  ----------------------------- */\r
+#define SCU_PARITY_PEFLAG_PEFPS_Pos           0                                                       /*!< SCU_PARITY PEFLAG: PEFPS Position       */\r
+#define SCU_PARITY_PEFLAG_PEFPS_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFPS_Pos)                 /*!< SCU_PARITY PEFLAG: PEFPS Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFDS1_Pos          1                                                       /*!< SCU_PARITY PEFLAG: PEFDS1 Position      */\r
+#define SCU_PARITY_PEFLAG_PEFDS1_Msk          (0x01UL << SCU_PARITY_PEFLAG_PEFDS1_Pos)                /*!< SCU_PARITY PEFLAG: PEFDS1 Mask          */\r
+#define SCU_PARITY_PEFLAG_PEFDS2_Pos          2                                                       /*!< SCU_PARITY PEFLAG: PEFDS2 Position      */\r
+#define SCU_PARITY_PEFLAG_PEFDS2_Msk          (0x01UL << SCU_PARITY_PEFLAG_PEFDS2_Pos)                /*!< SCU_PARITY PEFLAG: PEFDS2 Mask          */\r
+#define SCU_PARITY_PEFLAG_PEFU0_Pos           8                                                       /*!< SCU_PARITY PEFLAG: PEFU0 Position       */\r
+#define SCU_PARITY_PEFLAG_PEFU0_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFU0_Pos)                 /*!< SCU_PARITY PEFLAG: PEFU0 Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFU1_Pos           9                                                       /*!< SCU_PARITY PEFLAG: PEFU1 Position       */\r
+#define SCU_PARITY_PEFLAG_PEFU1_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFU1_Pos)                 /*!< SCU_PARITY PEFLAG: PEFU1 Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFU2_Pos           10                                                      /*!< SCU_PARITY PEFLAG: PEFU2 Position       */\r
+#define SCU_PARITY_PEFLAG_PEFU2_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFU2_Pos)                 /*!< SCU_PARITY PEFLAG: PEFU2 Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFMC_Pos           12                                                      /*!< SCU_PARITY PEFLAG: PEFMC Position       */\r
+#define SCU_PARITY_PEFLAG_PEFMC_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEFMC_Pos)                 /*!< SCU_PARITY PEFLAG: PEFMC Mask           */\r
+#define SCU_PARITY_PEFLAG_PEFPPRF_Pos         13                                                      /*!< SCU_PARITY PEFLAG: PEFPPRF Position     */\r
+#define SCU_PARITY_PEFLAG_PEFPPRF_Msk         (0x01UL << SCU_PARITY_PEFLAG_PEFPPRF_Pos)               /*!< SCU_PARITY PEFLAG: PEFPPRF Mask         */\r
+#define SCU_PARITY_PEFLAG_PEUSB_Pos           16                                                      /*!< SCU_PARITY PEFLAG: PEUSB Position       */\r
+#define SCU_PARITY_PEFLAG_PEUSB_Msk           (0x01UL << SCU_PARITY_PEFLAG_PEUSB_Pos)                 /*!< SCU_PARITY PEFLAG: PEUSB Mask           */\r
+#define SCU_PARITY_PEFLAG_PEETH0TX_Pos        17                                                      /*!< SCU_PARITY PEFLAG: PEETH0TX Position    */\r
+#define SCU_PARITY_PEFLAG_PEETH0TX_Msk        (0x01UL << SCU_PARITY_PEFLAG_PEETH0TX_Pos)              /*!< SCU_PARITY PEFLAG: PEETH0TX Mask        */\r
+#define SCU_PARITY_PEFLAG_PEETH0RX_Pos        18                                                      /*!< SCU_PARITY PEFLAG: PEETH0RX Position    */\r
+#define SCU_PARITY_PEFLAG_PEETH0RX_Msk        (0x01UL << SCU_PARITY_PEFLAG_PEETH0RX_Pos)              /*!< SCU_PARITY PEFLAG: PEETH0RX Mask        */\r
+#define SCU_PARITY_PEFLAG_PESD0_Pos           19                                                      /*!< SCU_PARITY PEFLAG: PESD0 Position       */\r
+#define SCU_PARITY_PEFLAG_PESD0_Msk           (0x01UL << SCU_PARITY_PEFLAG_PESD0_Pos)                 /*!< SCU_PARITY PEFLAG: PESD0 Mask           */\r
+#define SCU_PARITY_PEFLAG_PESD1_Pos           20                                                      /*!< SCU_PARITY PEFLAG: PESD1 Position       */\r
+#define SCU_PARITY_PEFLAG_PESD1_Msk           (0x01UL << SCU_PARITY_PEFLAG_PESD1_Pos)                 /*!< SCU_PARITY PEFLAG: PESD1 Mask           */\r
+\r
+/* ------------------------------  SCU_PARITY_PMTPR  ------------------------------ */\r
+#define SCU_PARITY_PMTPR_PWR_Pos              0                                                       /*!< SCU_PARITY PMTPR: PWR Position          */\r
+#define SCU_PARITY_PMTPR_PWR_Msk              (0x000000ffUL << SCU_PARITY_PMTPR_PWR_Pos)              /*!< SCU_PARITY PMTPR: PWR Mask              */\r
+#define SCU_PARITY_PMTPR_PRD_Pos              8                                                       /*!< SCU_PARITY PMTPR: PRD Position          */\r
+#define SCU_PARITY_PMTPR_PRD_Msk              (0x000000ffUL << SCU_PARITY_PMTPR_PRD_Pos)              /*!< SCU_PARITY PMTPR: PRD Mask              */\r
+\r
+/* ------------------------------  SCU_PARITY_PMTSR  ------------------------------ */\r
+#define SCU_PARITY_PMTSR_MTENPS_Pos           0                                                       /*!< SCU_PARITY PMTSR: MTENPS Position       */\r
+#define SCU_PARITY_PMTSR_MTENPS_Msk           (0x01UL << SCU_PARITY_PMTSR_MTENPS_Pos)                 /*!< SCU_PARITY PMTSR: MTENPS Mask           */\r
+#define SCU_PARITY_PMTSR_MTENDS1_Pos          1                                                       /*!< SCU_PARITY PMTSR: MTENDS1 Position      */\r
+#define SCU_PARITY_PMTSR_MTENDS1_Msk          (0x01UL << SCU_PARITY_PMTSR_MTENDS1_Pos)                /*!< SCU_PARITY PMTSR: MTENDS1 Mask          */\r
+#define SCU_PARITY_PMTSR_MTENDS2_Pos          2                                                       /*!< SCU_PARITY PMTSR: MTENDS2 Position      */\r
+#define SCU_PARITY_PMTSR_MTENDS2_Msk          (0x01UL << SCU_PARITY_PMTSR_MTENDS2_Pos)                /*!< SCU_PARITY PMTSR: MTENDS2 Mask          */\r
+#define SCU_PARITY_PMTSR_MTEU0_Pos            8                                                       /*!< SCU_PARITY PMTSR: MTEU0 Position        */\r
+#define SCU_PARITY_PMTSR_MTEU0_Msk            (0x01UL << SCU_PARITY_PMTSR_MTEU0_Pos)                  /*!< SCU_PARITY PMTSR: MTEU0 Mask            */\r
+#define SCU_PARITY_PMTSR_MTEU1_Pos            9                                                       /*!< SCU_PARITY PMTSR: MTEU1 Position        */\r
+#define SCU_PARITY_PMTSR_MTEU1_Msk            (0x01UL << SCU_PARITY_PMTSR_MTEU1_Pos)                  /*!< SCU_PARITY PMTSR: MTEU1 Mask            */\r
+#define SCU_PARITY_PMTSR_MTEU2_Pos            10                                                      /*!< SCU_PARITY PMTSR: MTEU2 Position        */\r
+#define SCU_PARITY_PMTSR_MTEU2_Msk            (0x01UL << SCU_PARITY_PMTSR_MTEU2_Pos)                  /*!< SCU_PARITY PMTSR: MTEU2 Mask            */\r
+#define SCU_PARITY_PMTSR_MTEMC_Pos            12                                                      /*!< SCU_PARITY PMTSR: MTEMC Position        */\r
+#define SCU_PARITY_PMTSR_MTEMC_Msk            (0x01UL << SCU_PARITY_PMTSR_MTEMC_Pos)                  /*!< SCU_PARITY PMTSR: MTEMC Mask            */\r
+#define SCU_PARITY_PMTSR_MTEPPRF_Pos          13                                                      /*!< SCU_PARITY PMTSR: MTEPPRF Position      */\r
+#define SCU_PARITY_PMTSR_MTEPPRF_Msk          (0x01UL << SCU_PARITY_PMTSR_MTEPPRF_Pos)                /*!< SCU_PARITY PMTSR: MTEPPRF Mask          */\r
+#define SCU_PARITY_PMTSR_MTUSB_Pos            16                                                      /*!< SCU_PARITY PMTSR: MTUSB Position        */\r
+#define SCU_PARITY_PMTSR_MTUSB_Msk            (0x01UL << SCU_PARITY_PMTSR_MTUSB_Pos)                  /*!< SCU_PARITY PMTSR: MTUSB Mask            */\r
+#define SCU_PARITY_PMTSR_MTETH0TX_Pos         17                                                      /*!< SCU_PARITY PMTSR: MTETH0TX Position     */\r
+#define SCU_PARITY_PMTSR_MTETH0TX_Msk         (0x01UL << SCU_PARITY_PMTSR_MTETH0TX_Pos)               /*!< SCU_PARITY PMTSR: MTETH0TX Mask         */\r
+#define SCU_PARITY_PMTSR_MTETH0RX_Pos         18                                                      /*!< SCU_PARITY PMTSR: MTETH0RX Position     */\r
+#define SCU_PARITY_PMTSR_MTETH0RX_Msk         (0x01UL << SCU_PARITY_PMTSR_MTETH0RX_Pos)               /*!< SCU_PARITY PMTSR: MTETH0RX Mask         */\r
+#define SCU_PARITY_PMTSR_MTSD0_Pos            19                                                      /*!< SCU_PARITY PMTSR: MTSD0 Position        */\r
+#define SCU_PARITY_PMTSR_MTSD0_Msk            (0x01UL << SCU_PARITY_PMTSR_MTSD0_Pos)                  /*!< SCU_PARITY PMTSR: MTSD0 Mask            */\r
+#define SCU_PARITY_PMTSR_MTSD1_Pos            20                                                      /*!< SCU_PARITY PMTSR: MTSD1 Position        */\r
+#define SCU_PARITY_PMTSR_MTSD1_Msk            (0x01UL << SCU_PARITY_PMTSR_MTSD1_Pos)                  /*!< SCU_PARITY PMTSR: MTSD1 Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'SCU_TRAP' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPSTAT  ----------------------------- */\r
+#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos        0                                                       /*!< SCU_TRAP TRAPSTAT: SOSCWDGT Position    */\r
+#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk        (0x01UL << SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos)              /*!< SCU_TRAP TRAPSTAT: SOSCWDGT Mask        */\r
+#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos        2                                                       /*!< SCU_TRAP TRAPSTAT: SVCOLCKT Position    */\r
+#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk        (0x01UL << SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos)              /*!< SCU_TRAP TRAPSTAT: SVCOLCKT Mask        */\r
+#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos        3                                                       /*!< SCU_TRAP TRAPSTAT: UVCOLCKT Position    */\r
+#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk        (0x01UL << SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos)              /*!< SCU_TRAP TRAPSTAT: UVCOLCKT Mask        */\r
+#define SCU_TRAP_TRAPSTAT_PET_Pos             4                                                       /*!< SCU_TRAP TRAPSTAT: PET Position         */\r
+#define SCU_TRAP_TRAPSTAT_PET_Msk             (0x01UL << SCU_TRAP_TRAPSTAT_PET_Pos)                   /*!< SCU_TRAP TRAPSTAT: PET Mask             */\r
+#define SCU_TRAP_TRAPSTAT_BRWNT_Pos           5                                                       /*!< SCU_TRAP TRAPSTAT: BRWNT Position       */\r
+#define SCU_TRAP_TRAPSTAT_BRWNT_Msk           (0x01UL << SCU_TRAP_TRAPSTAT_BRWNT_Pos)                 /*!< SCU_TRAP TRAPSTAT: BRWNT Mask           */\r
+#define SCU_TRAP_TRAPSTAT_ULPWDGT_Pos         6                                                       /*!< SCU_TRAP TRAPSTAT: ULPWDGT Position     */\r
+#define SCU_TRAP_TRAPSTAT_ULPWDGT_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_ULPWDGT_Pos)               /*!< SCU_TRAP TRAPSTAT: ULPWDGT Mask         */\r
+#define SCU_TRAP_TRAPSTAT_BWERR0T_Pos         7                                                       /*!< SCU_TRAP TRAPSTAT: BWERR0T Position     */\r
+#define SCU_TRAP_TRAPSTAT_BWERR0T_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_BWERR0T_Pos)               /*!< SCU_TRAP TRAPSTAT: BWERR0T Mask         */\r
+#define SCU_TRAP_TRAPSTAT_BWERR1T_Pos         8                                                       /*!< SCU_TRAP TRAPSTAT: BWERR1T Position     */\r
+#define SCU_TRAP_TRAPSTAT_BWERR1T_Msk         (0x01UL << SCU_TRAP_TRAPSTAT_BWERR1T_Pos)               /*!< SCU_TRAP TRAPSTAT: BWERR1T Mask         */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPRAW  ------------------------------ */\r
+#define SCU_TRAP_TRAPRAW_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPRAW: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPRAW_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPRAW_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPRAW: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPRAW_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPRAW: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPRAW_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPRAW_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPRAW: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPRAW_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPRAW: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPRAW_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPRAW_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPRAW: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPRAW_PET_Pos              4                                                       /*!< SCU_TRAP TRAPRAW: PET Position          */\r
+#define SCU_TRAP_TRAPRAW_PET_Msk              (0x01UL << SCU_TRAP_TRAPRAW_PET_Pos)                    /*!< SCU_TRAP TRAPRAW: PET Mask              */\r
+#define SCU_TRAP_TRAPRAW_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPRAW: BRWNT Position        */\r
+#define SCU_TRAP_TRAPRAW_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPRAW_BRWNT_Pos)                  /*!< SCU_TRAP TRAPRAW: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPRAW_ULPWDGT_Pos          6                                                       /*!< SCU_TRAP TRAPRAW: ULPWDGT Position      */\r
+#define SCU_TRAP_TRAPRAW_ULPWDGT_Msk          (0x01UL << SCU_TRAP_TRAPRAW_ULPWDGT_Pos)                /*!< SCU_TRAP TRAPRAW: ULPWDGT Mask          */\r
+#define SCU_TRAP_TRAPRAW_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPRAW: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPRAW_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPRAW_BWERR0T_Pos)                /*!< SCU_TRAP TRAPRAW: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPRAW_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPRAW: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPRAW_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPRAW_BWERR1T_Pos)                /*!< SCU_TRAP TRAPRAW: BWERR1T Mask          */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPDIS  ------------------------------ */\r
+#define SCU_TRAP_TRAPDIS_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPDIS: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPDIS_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPDIS_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPDIS: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPDIS_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPDIS: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPDIS_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPDIS_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPDIS: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPDIS_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPDIS: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPDIS_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPDIS_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPDIS: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPDIS_PET_Pos              4                                                       /*!< SCU_TRAP TRAPDIS: PET Position          */\r
+#define SCU_TRAP_TRAPDIS_PET_Msk              (0x01UL << SCU_TRAP_TRAPDIS_PET_Pos)                    /*!< SCU_TRAP TRAPDIS: PET Mask              */\r
+#define SCU_TRAP_TRAPDIS_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPDIS: BRWNT Position        */\r
+#define SCU_TRAP_TRAPDIS_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPDIS_BRWNT_Pos)                  /*!< SCU_TRAP TRAPDIS: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPDIS_ULPWDGT_Pos          6                                                       /*!< SCU_TRAP TRAPDIS: ULPWDGT Position      */\r
+#define SCU_TRAP_TRAPDIS_ULPWDGT_Msk          (0x01UL << SCU_TRAP_TRAPDIS_ULPWDGT_Pos)                /*!< SCU_TRAP TRAPDIS: ULPWDGT Mask          */\r
+#define SCU_TRAP_TRAPDIS_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPDIS: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPDIS_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPDIS_BWERR0T_Pos)                /*!< SCU_TRAP TRAPDIS: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPDIS_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPDIS: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPDIS_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPDIS_BWERR1T_Pos)                /*!< SCU_TRAP TRAPDIS: BWERR1T Mask          */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPCLR  ------------------------------ */\r
+#define SCU_TRAP_TRAPCLR_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPCLR: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPCLR_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPCLR_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPCLR: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPCLR_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPCLR: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPCLR_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPCLR_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPCLR: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPCLR_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPCLR: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPCLR_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPCLR_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPCLR: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPCLR_PET_Pos              4                                                       /*!< SCU_TRAP TRAPCLR: PET Position          */\r
+#define SCU_TRAP_TRAPCLR_PET_Msk              (0x01UL << SCU_TRAP_TRAPCLR_PET_Pos)                    /*!< SCU_TRAP TRAPCLR: PET Mask              */\r
+#define SCU_TRAP_TRAPCLR_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPCLR: BRWNT Position        */\r
+#define SCU_TRAP_TRAPCLR_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPCLR_BRWNT_Pos)                  /*!< SCU_TRAP TRAPCLR: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPCLR_ULPWDGT_Pos          6                                                       /*!< SCU_TRAP TRAPCLR: ULPWDGT Position      */\r
+#define SCU_TRAP_TRAPCLR_ULPWDGT_Msk          (0x01UL << SCU_TRAP_TRAPCLR_ULPWDGT_Pos)                /*!< SCU_TRAP TRAPCLR: ULPWDGT Mask          */\r
+#define SCU_TRAP_TRAPCLR_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPCLR: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPCLR_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPCLR_BWERR0T_Pos)                /*!< SCU_TRAP TRAPCLR: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPCLR_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPCLR: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPCLR_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPCLR_BWERR1T_Pos)                /*!< SCU_TRAP TRAPCLR: BWERR1T Mask          */\r
+\r
+/* ------------------------------  SCU_TRAP_TRAPSET  ------------------------------ */\r
+#define SCU_TRAP_TRAPSET_SOSCWDGT_Pos         0                                                       /*!< SCU_TRAP TRAPSET: SOSCWDGT Position     */\r
+#define SCU_TRAP_TRAPSET_SOSCWDGT_Msk         (0x01UL << SCU_TRAP_TRAPSET_SOSCWDGT_Pos)               /*!< SCU_TRAP TRAPSET: SOSCWDGT Mask         */\r
+#define SCU_TRAP_TRAPSET_SVCOLCKT_Pos         2                                                       /*!< SCU_TRAP TRAPSET: SVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPSET_SVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPSET_SVCOLCKT_Pos)               /*!< SCU_TRAP TRAPSET: SVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPSET_UVCOLCKT_Pos         3                                                       /*!< SCU_TRAP TRAPSET: UVCOLCKT Position     */\r
+#define SCU_TRAP_TRAPSET_UVCOLCKT_Msk         (0x01UL << SCU_TRAP_TRAPSET_UVCOLCKT_Pos)               /*!< SCU_TRAP TRAPSET: UVCOLCKT Mask         */\r
+#define SCU_TRAP_TRAPSET_PET_Pos              4                                                       /*!< SCU_TRAP TRAPSET: PET Position          */\r
+#define SCU_TRAP_TRAPSET_PET_Msk              (0x01UL << SCU_TRAP_TRAPSET_PET_Pos)                    /*!< SCU_TRAP TRAPSET: PET Mask              */\r
+#define SCU_TRAP_TRAPSET_BRWNT_Pos            5                                                       /*!< SCU_TRAP TRAPSET: BRWNT Position        */\r
+#define SCU_TRAP_TRAPSET_BRWNT_Msk            (0x01UL << SCU_TRAP_TRAPSET_BRWNT_Pos)                  /*!< SCU_TRAP TRAPSET: BRWNT Mask            */\r
+#define SCU_TRAP_TRAPSET_ULPWDT_Pos           6                                                       /*!< SCU_TRAP TRAPSET: ULPWDT Position       */\r
+#define SCU_TRAP_TRAPSET_ULPWDT_Msk           (0x01UL << SCU_TRAP_TRAPSET_ULPWDT_Pos)                 /*!< SCU_TRAP TRAPSET: ULPWDT Mask           */\r
+#define SCU_TRAP_TRAPSET_BWERR0T_Pos          7                                                       /*!< SCU_TRAP TRAPSET: BWERR0T Position      */\r
+#define SCU_TRAP_TRAPSET_BWERR0T_Msk          (0x01UL << SCU_TRAP_TRAPSET_BWERR0T_Pos)                /*!< SCU_TRAP TRAPSET: BWERR0T Mask          */\r
+#define SCU_TRAP_TRAPSET_BWERR1T_Pos          8                                                       /*!< SCU_TRAP TRAPSET: BWERR1T Position      */\r
+#define SCU_TRAP_TRAPSET_BWERR1T_Msk          (0x01UL << SCU_TRAP_TRAPSET_BWERR1T_Pos)                /*!< SCU_TRAP TRAPSET: BWERR1T Mask          */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================     struct 'SCU_HIBERNATE' Position & Mask     ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------  SCU_HIBERNATE_HDSTAT  ---------------------------- */\r
+#define SCU_HIBERNATE_HDSTAT_EPEV_Pos         0                                                       /*!< SCU_HIBERNATE HDSTAT: EPEV Position     */\r
+#define SCU_HIBERNATE_HDSTAT_EPEV_Msk         (0x01UL << SCU_HIBERNATE_HDSTAT_EPEV_Pos)               /*!< SCU_HIBERNATE HDSTAT: EPEV Mask         */\r
+#define SCU_HIBERNATE_HDSTAT_ENEV_Pos         1                                                       /*!< SCU_HIBERNATE HDSTAT: ENEV Position     */\r
+#define SCU_HIBERNATE_HDSTAT_ENEV_Msk         (0x01UL << SCU_HIBERNATE_HDSTAT_ENEV_Pos)               /*!< SCU_HIBERNATE HDSTAT: ENEV Mask         */\r
+#define SCU_HIBERNATE_HDSTAT_RTCEV_Pos        2                                                       /*!< SCU_HIBERNATE HDSTAT: RTCEV Position    */\r
+#define SCU_HIBERNATE_HDSTAT_RTCEV_Msk        (0x01UL << SCU_HIBERNATE_HDSTAT_RTCEV_Pos)              /*!< SCU_HIBERNATE HDSTAT: RTCEV Mask        */\r
+#define SCU_HIBERNATE_HDSTAT_ULPWDG_Pos       3                                                       /*!< SCU_HIBERNATE HDSTAT: ULPWDG Position   */\r
+#define SCU_HIBERNATE_HDSTAT_ULPWDG_Msk       (0x01UL << SCU_HIBERNATE_HDSTAT_ULPWDG_Pos)             /*!< SCU_HIBERNATE HDSTAT: ULPWDG Mask       */\r
+#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos      4                                                       /*!< SCU_HIBERNATE HDSTAT: HIBNOUT Position  */\r
+#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk      (0x01UL << SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos)            /*!< SCU_HIBERNATE HDSTAT: HIBNOUT Mask      */\r
+\r
+/* -----------------------------  SCU_HIBERNATE_HDCLR  ---------------------------- */\r
+#define SCU_HIBERNATE_HDCLR_EPEV_Pos          0                                                       /*!< SCU_HIBERNATE HDCLR: EPEV Position      */\r
+#define SCU_HIBERNATE_HDCLR_EPEV_Msk          (0x01UL << SCU_HIBERNATE_HDCLR_EPEV_Pos)                /*!< SCU_HIBERNATE HDCLR: EPEV Mask          */\r
+#define SCU_HIBERNATE_HDCLR_ENEV_Pos          1                                                       /*!< SCU_HIBERNATE HDCLR: ENEV Position      */\r
+#define SCU_HIBERNATE_HDCLR_ENEV_Msk          (0x01UL << SCU_HIBERNATE_HDCLR_ENEV_Pos)                /*!< SCU_HIBERNATE HDCLR: ENEV Mask          */\r
+#define SCU_HIBERNATE_HDCLR_RTCEV_Pos         2                                                       /*!< SCU_HIBERNATE HDCLR: RTCEV Position     */\r
+#define SCU_HIBERNATE_HDCLR_RTCEV_Msk         (0x01UL << SCU_HIBERNATE_HDCLR_RTCEV_Pos)               /*!< SCU_HIBERNATE HDCLR: RTCEV Mask         */\r
+#define SCU_HIBERNATE_HDCLR_ULPWDG_Pos        3                                                       /*!< SCU_HIBERNATE HDCLR: ULPWDG Position    */\r
+#define SCU_HIBERNATE_HDCLR_ULPWDG_Msk        (0x01UL << SCU_HIBERNATE_HDCLR_ULPWDG_Pos)              /*!< SCU_HIBERNATE HDCLR: ULPWDG Mask        */\r
+\r
+/* -----------------------------  SCU_HIBERNATE_HDSET  ---------------------------- */\r
+#define SCU_HIBERNATE_HDSET_EPEV_Pos          0                                                       /*!< SCU_HIBERNATE HDSET: EPEV Position      */\r
+#define SCU_HIBERNATE_HDSET_EPEV_Msk          (0x01UL << SCU_HIBERNATE_HDSET_EPEV_Pos)                /*!< SCU_HIBERNATE HDSET: EPEV Mask          */\r
+#define SCU_HIBERNATE_HDSET_ENEV_Pos          1                                                       /*!< SCU_HIBERNATE HDSET: ENEV Position      */\r
+#define SCU_HIBERNATE_HDSET_ENEV_Msk          (0x01UL << SCU_HIBERNATE_HDSET_ENEV_Pos)                /*!< SCU_HIBERNATE HDSET: ENEV Mask          */\r
+#define SCU_HIBERNATE_HDSET_RTCEV_Pos         2                                                       /*!< SCU_HIBERNATE HDSET: RTCEV Position     */\r
+#define SCU_HIBERNATE_HDSET_RTCEV_Msk         (0x01UL << SCU_HIBERNATE_HDSET_RTCEV_Pos)               /*!< SCU_HIBERNATE HDSET: RTCEV Mask         */\r
+#define SCU_HIBERNATE_HDSET_ULPWDG_Pos        3                                                       /*!< SCU_HIBERNATE HDSET: ULPWDG Position    */\r
+#define SCU_HIBERNATE_HDSET_ULPWDG_Msk        (0x01UL << SCU_HIBERNATE_HDSET_ULPWDG_Pos)              /*!< SCU_HIBERNATE HDSET: ULPWDG Mask        */\r
+\r
+/* -----------------------------  SCU_HIBERNATE_HDCR  ----------------------------- */\r
+#define SCU_HIBERNATE_HDCR_WKPEP_Pos          0                                                       /*!< SCU_HIBERNATE HDCR: WKPEP Position      */\r
+#define SCU_HIBERNATE_HDCR_WKPEP_Msk          (0x01UL << SCU_HIBERNATE_HDCR_WKPEP_Pos)                /*!< SCU_HIBERNATE HDCR: WKPEP Mask          */\r
+#define SCU_HIBERNATE_HDCR_WKPEN_Pos          1                                                       /*!< SCU_HIBERNATE HDCR: WKPEN Position      */\r
+#define SCU_HIBERNATE_HDCR_WKPEN_Msk          (0x01UL << SCU_HIBERNATE_HDCR_WKPEN_Pos)                /*!< SCU_HIBERNATE HDCR: WKPEN Mask          */\r
+#define SCU_HIBERNATE_HDCR_RTCE_Pos           2                                                       /*!< SCU_HIBERNATE HDCR: RTCE Position       */\r
+#define SCU_HIBERNATE_HDCR_RTCE_Msk           (0x01UL << SCU_HIBERNATE_HDCR_RTCE_Pos)                 /*!< SCU_HIBERNATE HDCR: RTCE Mask           */\r
+#define SCU_HIBERNATE_HDCR_ULPWDGEN_Pos       3                                                       /*!< SCU_HIBERNATE HDCR: ULPWDGEN Position   */\r
+#define SCU_HIBERNATE_HDCR_ULPWDGEN_Msk       (0x01UL << SCU_HIBERNATE_HDCR_ULPWDGEN_Pos)             /*!< SCU_HIBERNATE HDCR: ULPWDGEN Mask       */\r
+#define SCU_HIBERNATE_HDCR_HIB_Pos            4                                                       /*!< SCU_HIBERNATE HDCR: HIB Position        */\r
+#define SCU_HIBERNATE_HDCR_HIB_Msk            (0x01UL << SCU_HIBERNATE_HDCR_HIB_Pos)                  /*!< SCU_HIBERNATE HDCR: HIB Mask            */\r
+#define SCU_HIBERNATE_HDCR_RCS_Pos            6                                                       /*!< SCU_HIBERNATE HDCR: RCS Position        */\r
+#define SCU_HIBERNATE_HDCR_RCS_Msk            (0x01UL << SCU_HIBERNATE_HDCR_RCS_Pos)                  /*!< SCU_HIBERNATE HDCR: RCS Mask            */\r
+#define SCU_HIBERNATE_HDCR_STDBYSEL_Pos       7                                                       /*!< SCU_HIBERNATE HDCR: STDBYSEL Position   */\r
+#define SCU_HIBERNATE_HDCR_STDBYSEL_Msk       (0x01UL << SCU_HIBERNATE_HDCR_STDBYSEL_Pos)             /*!< SCU_HIBERNATE HDCR: STDBYSEL Mask       */\r
+#define SCU_HIBERNATE_HDCR_WKUPSEL_Pos        8                                                       /*!< SCU_HIBERNATE HDCR: WKUPSEL Position    */\r
+#define SCU_HIBERNATE_HDCR_WKUPSEL_Msk        (0x01UL << SCU_HIBERNATE_HDCR_WKUPSEL_Pos)              /*!< SCU_HIBERNATE HDCR: WKUPSEL Mask        */\r
+#define SCU_HIBERNATE_HDCR_GPI0SEL_Pos        10                                                      /*!< SCU_HIBERNATE HDCR: GPI0SEL Position    */\r
+#define SCU_HIBERNATE_HDCR_GPI0SEL_Msk        (0x01UL << SCU_HIBERNATE_HDCR_GPI0SEL_Pos)              /*!< SCU_HIBERNATE HDCR: GPI0SEL Mask        */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0POL_Pos      12                                                      /*!< SCU_HIBERNATE HDCR: HIBIO0POL Position  */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0POL_Msk      (0x01UL << SCU_HIBERNATE_HDCR_HIBIO0POL_Pos)            /*!< SCU_HIBERNATE HDCR: HIBIO0POL Mask      */\r
+#define SCU_HIBERNATE_HDCR_HIBIO1POL_Pos      13                                                      /*!< SCU_HIBERNATE HDCR: HIBIO1POL Position  */\r
+#define SCU_HIBERNATE_HDCR_HIBIO1POL_Msk      (0x01UL << SCU_HIBERNATE_HDCR_HIBIO1POL_Pos)            /*!< SCU_HIBERNATE HDCR: HIBIO1POL Mask      */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos      16                                                      /*!< SCU_HIBERNATE HDCR: HIBIO0SEL Position  */\r
+#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk      (0x0fUL << SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos)            /*!< SCU_HIBERNATE HDCR: HIBIO0SEL Mask      */\r
+#define SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos      20                                                      /*!< SCU_HIBERNATE HDCR: HIBIO1SEL Position  */\r
+#define SCU_HIBERNATE_HDCR_HIBIO1SEL_Msk      (0x0fUL << SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos)            /*!< SCU_HIBERNATE HDCR: HIBIO1SEL Mask      */\r
+\r
+/* ---------------------------  SCU_HIBERNATE_OSCSICTRL  -------------------------- */\r
+#define SCU_HIBERNATE_OSCSICTRL_PWD_Pos       0                                                       /*!< SCU_HIBERNATE OSCSICTRL: PWD Position   */\r
+#define SCU_HIBERNATE_OSCSICTRL_PWD_Msk       (0x01UL << SCU_HIBERNATE_OSCSICTRL_PWD_Pos)             /*!< SCU_HIBERNATE OSCSICTRL: PWD Mask       */\r
+\r
+/* ---------------------------  SCU_HIBERNATE_OSCULSTAT  -------------------------- */\r
+#define SCU_HIBERNATE_OSCULSTAT_X1D_Pos       0                                                       /*!< SCU_HIBERNATE OSCULSTAT: X1D Position   */\r
+#define SCU_HIBERNATE_OSCULSTAT_X1D_Msk       (0x01UL << SCU_HIBERNATE_OSCULSTAT_X1D_Pos)             /*!< SCU_HIBERNATE OSCULSTAT: X1D Mask       */\r
+\r
+/* ---------------------------  SCU_HIBERNATE_OSCULCTRL  -------------------------- */\r
+#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos     0                                                       /*!< SCU_HIBERNATE OSCULCTRL: X1DEN Position */\r
+#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk     (0x01UL << SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos)           /*!< SCU_HIBERNATE OSCULCTRL: X1DEN Mask     */\r
+#define SCU_HIBERNATE_OSCULCTRL_MODE_Pos      4                                                       /*!< SCU_HIBERNATE OSCULCTRL: MODE Position  */\r
+#define SCU_HIBERNATE_OSCULCTRL_MODE_Msk      (0x03UL << SCU_HIBERNATE_OSCULCTRL_MODE_Pos)            /*!< SCU_HIBERNATE OSCULCTRL: MODE Mask      */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       struct 'SCU_POWER' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_POWER_PWRSTAT  ----------------------------- */\r
+#define SCU_POWER_PWRSTAT_HIBEN_Pos           0                                                       /*!< SCU_POWER PWRSTAT: HIBEN Position       */\r
+#define SCU_POWER_PWRSTAT_HIBEN_Msk           (0x01UL << SCU_POWER_PWRSTAT_HIBEN_Pos)                 /*!< SCU_POWER PWRSTAT: HIBEN Mask           */\r
+#define SCU_POWER_PWRSTAT_USBPHYPDQ_Pos       16                                                      /*!< SCU_POWER PWRSTAT: USBPHYPDQ Position   */\r
+#define SCU_POWER_PWRSTAT_USBPHYPDQ_Msk       (0x01UL << SCU_POWER_PWRSTAT_USBPHYPDQ_Pos)             /*!< SCU_POWER PWRSTAT: USBPHYPDQ Mask       */\r
+#define SCU_POWER_PWRSTAT_USBOTGEN_Pos        17                                                      /*!< SCU_POWER PWRSTAT: USBOTGEN Position    */\r
+#define SCU_POWER_PWRSTAT_USBOTGEN_Msk        (0x01UL << SCU_POWER_PWRSTAT_USBOTGEN_Pos)              /*!< SCU_POWER PWRSTAT: USBOTGEN Mask        */\r
+#define SCU_POWER_PWRSTAT_USBPUWQ_Pos         18                                                      /*!< SCU_POWER PWRSTAT: USBPUWQ Position     */\r
+#define SCU_POWER_PWRSTAT_USBPUWQ_Msk         (0x01UL << SCU_POWER_PWRSTAT_USBPUWQ_Pos)               /*!< SCU_POWER PWRSTAT: USBPUWQ Mask         */\r
+\r
+/* ------------------------------  SCU_POWER_PWRSET  ------------------------------ */\r
+#define SCU_POWER_PWRSET_HIB_Pos              0                                                       /*!< SCU_POWER PWRSET: HIB Position          */\r
+#define SCU_POWER_PWRSET_HIB_Msk              (0x01UL << SCU_POWER_PWRSET_HIB_Pos)                    /*!< SCU_POWER PWRSET: HIB Mask              */\r
+#define SCU_POWER_PWRSET_USBPHYPDQ_Pos        16                                                      /*!< SCU_POWER PWRSET: USBPHYPDQ Position    */\r
+#define SCU_POWER_PWRSET_USBPHYPDQ_Msk        (0x01UL << SCU_POWER_PWRSET_USBPHYPDQ_Pos)              /*!< SCU_POWER PWRSET: USBPHYPDQ Mask        */\r
+#define SCU_POWER_PWRSET_USBOTGEN_Pos         17                                                      /*!< SCU_POWER PWRSET: USBOTGEN Position     */\r
+#define SCU_POWER_PWRSET_USBOTGEN_Msk         (0x01UL << SCU_POWER_PWRSET_USBOTGEN_Pos)               /*!< SCU_POWER PWRSET: USBOTGEN Mask         */\r
+#define SCU_POWER_PWRSET_USBPUWQ_Pos          18                                                      /*!< SCU_POWER PWRSET: USBPUWQ Position      */\r
+#define SCU_POWER_PWRSET_USBPUWQ_Msk          (0x01UL << SCU_POWER_PWRSET_USBPUWQ_Pos)                /*!< SCU_POWER PWRSET: USBPUWQ Mask          */\r
+\r
+/* ------------------------------  SCU_POWER_PWRCLR  ------------------------------ */\r
+#define SCU_POWER_PWRCLR_HIB_Pos              0                                                       /*!< SCU_POWER PWRCLR: HIB Position          */\r
+#define SCU_POWER_PWRCLR_HIB_Msk              (0x01UL << SCU_POWER_PWRCLR_HIB_Pos)                    /*!< SCU_POWER PWRCLR: HIB Mask              */\r
+#define SCU_POWER_PWRCLR_USBPHYPDQ_Pos        16                                                      /*!< SCU_POWER PWRCLR: USBPHYPDQ Position    */\r
+#define SCU_POWER_PWRCLR_USBPHYPDQ_Msk        (0x01UL << SCU_POWER_PWRCLR_USBPHYPDQ_Pos)              /*!< SCU_POWER PWRCLR: USBPHYPDQ Mask        */\r
+#define SCU_POWER_PWRCLR_USBOTGEN_Pos         17                                                      /*!< SCU_POWER PWRCLR: USBOTGEN Position     */\r
+#define SCU_POWER_PWRCLR_USBOTGEN_Msk         (0x01UL << SCU_POWER_PWRCLR_USBOTGEN_Pos)               /*!< SCU_POWER PWRCLR: USBOTGEN Mask         */\r
+#define SCU_POWER_PWRCLR_USBPUWQ_Pos          18                                                      /*!< SCU_POWER PWRCLR: USBPUWQ Position      */\r
+#define SCU_POWER_PWRCLR_USBPUWQ_Msk          (0x01UL << SCU_POWER_PWRCLR_USBPUWQ_Pos)                /*!< SCU_POWER PWRCLR: USBPUWQ Mask          */\r
+\r
+/* ------------------------------  SCU_POWER_EVRSTAT  ----------------------------- */\r
+#define SCU_POWER_EVRSTAT_OV13_Pos            1                                                       /*!< SCU_POWER EVRSTAT: OV13 Position        */\r
+#define SCU_POWER_EVRSTAT_OV13_Msk            (0x01UL << SCU_POWER_EVRSTAT_OV13_Pos)                  /*!< SCU_POWER EVRSTAT: OV13 Mask            */\r
+\r
+/* ----------------------------  SCU_POWER_EVRVADCSTAT  --------------------------- */\r
+#define SCU_POWER_EVRVADCSTAT_VADC13V_Pos     0                                                       /*!< SCU_POWER EVRVADCSTAT: VADC13V Position */\r
+#define SCU_POWER_EVRVADCSTAT_VADC13V_Msk     (0x000000ffUL << SCU_POWER_EVRVADCSTAT_VADC13V_Pos)     /*!< SCU_POWER EVRVADCSTAT: VADC13V Mask     */\r
+#define SCU_POWER_EVRVADCSTAT_VADC33V_Pos     8                                                       /*!< SCU_POWER EVRVADCSTAT: VADC33V Position */\r
+#define SCU_POWER_EVRVADCSTAT_VADC33V_Msk     (0x000000ffUL << SCU_POWER_EVRVADCSTAT_VADC33V_Pos)     /*!< SCU_POWER EVRVADCSTAT: VADC33V Mask     */\r
+\r
+/* ------------------------------  SCU_POWER_PWRMON  ------------------------------ */\r
+#define SCU_POWER_PWRMON_THRS_Pos             0                                                       /*!< SCU_POWER PWRMON: THRS Position         */\r
+#define SCU_POWER_PWRMON_THRS_Msk             (0x000000ffUL << SCU_POWER_PWRMON_THRS_Pos)             /*!< SCU_POWER PWRMON: THRS Mask             */\r
+#define SCU_POWER_PWRMON_INTV_Pos             8                                                       /*!< SCU_POWER PWRMON: INTV Position         */\r
+#define SCU_POWER_PWRMON_INTV_Msk             (0x000000ffUL << SCU_POWER_PWRMON_INTV_Pos)             /*!< SCU_POWER PWRMON: INTV Mask             */\r
+#define SCU_POWER_PWRMON_ENB_Pos              16                                                      /*!< SCU_POWER PWRMON: ENB Position          */\r
+#define SCU_POWER_PWRMON_ENB_Msk              (0x01UL << SCU_POWER_PWRMON_ENB_Pos)                    /*!< SCU_POWER PWRMON: ENB Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================       struct 'SCU_RESET' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SCU_RESET_RSTSTAT  ----------------------------- */\r
+#define SCU_RESET_RSTSTAT_RSTSTAT_Pos         0                                                       /*!< SCU_RESET RSTSTAT: RSTSTAT Position     */\r
+#define SCU_RESET_RSTSTAT_RSTSTAT_Msk         (0x000000ffUL << SCU_RESET_RSTSTAT_RSTSTAT_Pos)         /*!< SCU_RESET RSTSTAT: RSTSTAT Mask         */\r
+#define SCU_RESET_RSTSTAT_HIBWK_Pos           8                                                       /*!< SCU_RESET RSTSTAT: HIBWK Position       */\r
+#define SCU_RESET_RSTSTAT_HIBWK_Msk           (0x01UL << SCU_RESET_RSTSTAT_HIBWK_Pos)                 /*!< SCU_RESET RSTSTAT: HIBWK Mask           */\r
+#define SCU_RESET_RSTSTAT_HIBRS_Pos           9                                                       /*!< SCU_RESET RSTSTAT: HIBRS Position       */\r
+#define SCU_RESET_RSTSTAT_HIBRS_Msk           (0x01UL << SCU_RESET_RSTSTAT_HIBRS_Pos)                 /*!< SCU_RESET RSTSTAT: HIBRS Mask           */\r
+#define SCU_RESET_RSTSTAT_LCKEN_Pos           10                                                      /*!< SCU_RESET RSTSTAT: LCKEN Position       */\r
+#define SCU_RESET_RSTSTAT_LCKEN_Msk           (0x01UL << SCU_RESET_RSTSTAT_LCKEN_Pos)                 /*!< SCU_RESET RSTSTAT: LCKEN Mask           */\r
+\r
+/* ------------------------------  SCU_RESET_RSTSET  ------------------------------ */\r
+#define SCU_RESET_RSTSET_HIBWK_Pos            8                                                       /*!< SCU_RESET RSTSET: HIBWK Position        */\r
+#define SCU_RESET_RSTSET_HIBWK_Msk            (0x01UL << SCU_RESET_RSTSET_HIBWK_Pos)                  /*!< SCU_RESET RSTSET: HIBWK Mask            */\r
+#define SCU_RESET_RSTSET_HIBRS_Pos            9                                                       /*!< SCU_RESET RSTSET: HIBRS Position        */\r
+#define SCU_RESET_RSTSET_HIBRS_Msk            (0x01UL << SCU_RESET_RSTSET_HIBRS_Pos)                  /*!< SCU_RESET RSTSET: HIBRS Mask            */\r
+#define SCU_RESET_RSTSET_LCKEN_Pos            10                                                      /*!< SCU_RESET RSTSET: LCKEN Position        */\r
+#define SCU_RESET_RSTSET_LCKEN_Msk            (0x01UL << SCU_RESET_RSTSET_LCKEN_Pos)                  /*!< SCU_RESET RSTSET: LCKEN Mask            */\r
+\r
+/* ------------------------------  SCU_RESET_RSTCLR  ------------------------------ */\r
+#define SCU_RESET_RSTCLR_RSCLR_Pos            0                                                       /*!< SCU_RESET RSTCLR: RSCLR Position        */\r
+#define SCU_RESET_RSTCLR_RSCLR_Msk            (0x01UL << SCU_RESET_RSTCLR_RSCLR_Pos)                  /*!< SCU_RESET RSTCLR: RSCLR Mask            */\r
+#define SCU_RESET_RSTCLR_HIBWK_Pos            8                                                       /*!< SCU_RESET RSTCLR: HIBWK Position        */\r
+#define SCU_RESET_RSTCLR_HIBWK_Msk            (0x01UL << SCU_RESET_RSTCLR_HIBWK_Pos)                  /*!< SCU_RESET RSTCLR: HIBWK Mask            */\r
+#define SCU_RESET_RSTCLR_HIBRS_Pos            9                                                       /*!< SCU_RESET RSTCLR: HIBRS Position        */\r
+#define SCU_RESET_RSTCLR_HIBRS_Msk            (0x01UL << SCU_RESET_RSTCLR_HIBRS_Pos)                  /*!< SCU_RESET RSTCLR: HIBRS Mask            */\r
+#define SCU_RESET_RSTCLR_LCKEN_Pos            10                                                      /*!< SCU_RESET RSTCLR: LCKEN Position        */\r
+#define SCU_RESET_RSTCLR_LCKEN_Msk            (0x01UL << SCU_RESET_RSTCLR_LCKEN_Pos)                  /*!< SCU_RESET RSTCLR: LCKEN Mask            */\r
+\r
+/* ------------------------------  SCU_RESET_PRSTAT0  ----------------------------- */\r
+#define SCU_RESET_PRSTAT0_VADCRS_Pos          0                                                       /*!< SCU_RESET PRSTAT0: VADCRS Position      */\r
+#define SCU_RESET_PRSTAT0_VADCRS_Msk          (0x01UL << SCU_RESET_PRSTAT0_VADCRS_Pos)                /*!< SCU_RESET PRSTAT0: VADCRS Mask          */\r
+#define SCU_RESET_PRSTAT0_DSDRS_Pos           1                                                       /*!< SCU_RESET PRSTAT0: DSDRS Position       */\r
+#define SCU_RESET_PRSTAT0_DSDRS_Msk           (0x01UL << SCU_RESET_PRSTAT0_DSDRS_Pos)                 /*!< SCU_RESET PRSTAT0: DSDRS Mask           */\r
+#define SCU_RESET_PRSTAT0_CCU40RS_Pos         2                                                       /*!< SCU_RESET PRSTAT0: CCU40RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU40RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU40RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU40RS Mask         */\r
+#define SCU_RESET_PRSTAT0_CCU41RS_Pos         3                                                       /*!< SCU_RESET PRSTAT0: CCU41RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU41RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU41RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU41RS Mask         */\r
+#define SCU_RESET_PRSTAT0_CCU42RS_Pos         4                                                       /*!< SCU_RESET PRSTAT0: CCU42RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU42RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU42RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU42RS Mask         */\r
+#define SCU_RESET_PRSTAT0_CCU80RS_Pos         7                                                       /*!< SCU_RESET PRSTAT0: CCU80RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU80RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU80RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU80RS Mask         */\r
+#define SCU_RESET_PRSTAT0_CCU81RS_Pos         8                                                       /*!< SCU_RESET PRSTAT0: CCU81RS Position     */\r
+#define SCU_RESET_PRSTAT0_CCU81RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_CCU81RS_Pos)               /*!< SCU_RESET PRSTAT0: CCU81RS Mask         */\r
+#define SCU_RESET_PRSTAT0_POSIF0RS_Pos        9                                                       /*!< SCU_RESET PRSTAT0: POSIF0RS Position    */\r
+#define SCU_RESET_PRSTAT0_POSIF0RS_Msk        (0x01UL << SCU_RESET_PRSTAT0_POSIF0RS_Pos)              /*!< SCU_RESET PRSTAT0: POSIF0RS Mask        */\r
+#define SCU_RESET_PRSTAT0_POSIF1RS_Pos        10                                                      /*!< SCU_RESET PRSTAT0: POSIF1RS Position    */\r
+#define SCU_RESET_PRSTAT0_POSIF1RS_Msk        (0x01UL << SCU_RESET_PRSTAT0_POSIF1RS_Pos)              /*!< SCU_RESET PRSTAT0: POSIF1RS Mask        */\r
+#define SCU_RESET_PRSTAT0_USIC0RS_Pos         11                                                      /*!< SCU_RESET PRSTAT0: USIC0RS Position     */\r
+#define SCU_RESET_PRSTAT0_USIC0RS_Msk         (0x01UL << SCU_RESET_PRSTAT0_USIC0RS_Pos)               /*!< SCU_RESET PRSTAT0: USIC0RS Mask         */\r
+#define SCU_RESET_PRSTAT0_ERU1RS_Pos          16                                                      /*!< SCU_RESET PRSTAT0: ERU1RS Position      */\r
+#define SCU_RESET_PRSTAT0_ERU1RS_Msk          (0x01UL << SCU_RESET_PRSTAT0_ERU1RS_Pos)                /*!< SCU_RESET PRSTAT0: ERU1RS Mask          */\r
+\r
+/* ------------------------------  SCU_RESET_PRSET0  ------------------------------ */\r
+#define SCU_RESET_PRSET0_VADCRS_Pos           0                                                       /*!< SCU_RESET PRSET0: VADCRS Position       */\r
+#define SCU_RESET_PRSET0_VADCRS_Msk           (0x01UL << SCU_RESET_PRSET0_VADCRS_Pos)                 /*!< SCU_RESET PRSET0: VADCRS Mask           */\r
+#define SCU_RESET_PRSET0_DSDRS_Pos            1                                                       /*!< SCU_RESET PRSET0: DSDRS Position        */\r
+#define SCU_RESET_PRSET0_DSDRS_Msk            (0x01UL << SCU_RESET_PRSET0_DSDRS_Pos)                  /*!< SCU_RESET PRSET0: DSDRS Mask            */\r
+#define SCU_RESET_PRSET0_CCU40RS_Pos          2                                                       /*!< SCU_RESET PRSET0: CCU40RS Position      */\r
+#define SCU_RESET_PRSET0_CCU40RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU40RS_Pos)                /*!< SCU_RESET PRSET0: CCU40RS Mask          */\r
+#define SCU_RESET_PRSET0_CCU41RS_Pos          3                                                       /*!< SCU_RESET PRSET0: CCU41RS Position      */\r
+#define SCU_RESET_PRSET0_CCU41RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU41RS_Pos)                /*!< SCU_RESET PRSET0: CCU41RS Mask          */\r
+#define SCU_RESET_PRSET0_CCU42RS_Pos          4                                                       /*!< SCU_RESET PRSET0: CCU42RS Position      */\r
+#define SCU_RESET_PRSET0_CCU42RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU42RS_Pos)                /*!< SCU_RESET PRSET0: CCU42RS Mask          */\r
+#define SCU_RESET_PRSET0_CCU80RS_Pos          7                                                       /*!< SCU_RESET PRSET0: CCU80RS Position      */\r
+#define SCU_RESET_PRSET0_CCU80RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU80RS_Pos)                /*!< SCU_RESET PRSET0: CCU80RS Mask          */\r
+#define SCU_RESET_PRSET0_CCU81RS_Pos          8                                                       /*!< SCU_RESET PRSET0: CCU81RS Position      */\r
+#define SCU_RESET_PRSET0_CCU81RS_Msk          (0x01UL << SCU_RESET_PRSET0_CCU81RS_Pos)                /*!< SCU_RESET PRSET0: CCU81RS Mask          */\r
+#define SCU_RESET_PRSET0_POSIF0RS_Pos         9                                                       /*!< SCU_RESET PRSET0: POSIF0RS Position     */\r
+#define SCU_RESET_PRSET0_POSIF0RS_Msk         (0x01UL << SCU_RESET_PRSET0_POSIF0RS_Pos)               /*!< SCU_RESET PRSET0: POSIF0RS Mask         */\r
+#define SCU_RESET_PRSET0_POSIF1RS_Pos         10                                                      /*!< SCU_RESET PRSET0: POSIF1RS Position     */\r
+#define SCU_RESET_PRSET0_POSIF1RS_Msk         (0x01UL << SCU_RESET_PRSET0_POSIF1RS_Pos)               /*!< SCU_RESET PRSET0: POSIF1RS Mask         */\r
+#define SCU_RESET_PRSET0_USIC0RS_Pos          11                                                      /*!< SCU_RESET PRSET0: USIC0RS Position      */\r
+#define SCU_RESET_PRSET0_USIC0RS_Msk          (0x01UL << SCU_RESET_PRSET0_USIC0RS_Pos)                /*!< SCU_RESET PRSET0: USIC0RS Mask          */\r
+#define SCU_RESET_PRSET0_ERU1RS_Pos           16                                                      /*!< SCU_RESET PRSET0: ERU1RS Position       */\r
+#define SCU_RESET_PRSET0_ERU1RS_Msk           (0x01UL << SCU_RESET_PRSET0_ERU1RS_Pos)                 /*!< SCU_RESET PRSET0: ERU1RS Mask           */\r
+\r
+/* ------------------------------  SCU_RESET_PRCLR0  ------------------------------ */\r
+#define SCU_RESET_PRCLR0_VADCRS_Pos           0                                                       /*!< SCU_RESET PRCLR0: VADCRS Position       */\r
+#define SCU_RESET_PRCLR0_VADCRS_Msk           (0x01UL << SCU_RESET_PRCLR0_VADCRS_Pos)                 /*!< SCU_RESET PRCLR0: VADCRS Mask           */\r
+#define SCU_RESET_PRCLR0_DSDRS_Pos            1                                                       /*!< SCU_RESET PRCLR0: DSDRS Position        */\r
+#define SCU_RESET_PRCLR0_DSDRS_Msk            (0x01UL << SCU_RESET_PRCLR0_DSDRS_Pos)                  /*!< SCU_RESET PRCLR0: DSDRS Mask            */\r
+#define SCU_RESET_PRCLR0_CCU40RS_Pos          2                                                       /*!< SCU_RESET PRCLR0: CCU40RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU40RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU40RS_Pos)                /*!< SCU_RESET PRCLR0: CCU40RS Mask          */\r
+#define SCU_RESET_PRCLR0_CCU41RS_Pos          3                                                       /*!< SCU_RESET PRCLR0: CCU41RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU41RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU41RS_Pos)                /*!< SCU_RESET PRCLR0: CCU41RS Mask          */\r
+#define SCU_RESET_PRCLR0_CCU42RS_Pos          4                                                       /*!< SCU_RESET PRCLR0: CCU42RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU42RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU42RS_Pos)                /*!< SCU_RESET PRCLR0: CCU42RS Mask          */\r
+#define SCU_RESET_PRCLR0_CCU80RS_Pos          7                                                       /*!< SCU_RESET PRCLR0: CCU80RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU80RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU80RS_Pos)                /*!< SCU_RESET PRCLR0: CCU80RS Mask          */\r
+#define SCU_RESET_PRCLR0_CCU81RS_Pos          8                                                       /*!< SCU_RESET PRCLR0: CCU81RS Position      */\r
+#define SCU_RESET_PRCLR0_CCU81RS_Msk          (0x01UL << SCU_RESET_PRCLR0_CCU81RS_Pos)                /*!< SCU_RESET PRCLR0: CCU81RS Mask          */\r
+#define SCU_RESET_PRCLR0_POSIF0RS_Pos         9                                                       /*!< SCU_RESET PRCLR0: POSIF0RS Position     */\r
+#define SCU_RESET_PRCLR0_POSIF0RS_Msk         (0x01UL << SCU_RESET_PRCLR0_POSIF0RS_Pos)               /*!< SCU_RESET PRCLR0: POSIF0RS Mask         */\r
+#define SCU_RESET_PRCLR0_POSIF1RS_Pos         10                                                      /*!< SCU_RESET PRCLR0: POSIF1RS Position     */\r
+#define SCU_RESET_PRCLR0_POSIF1RS_Msk         (0x01UL << SCU_RESET_PRCLR0_POSIF1RS_Pos)               /*!< SCU_RESET PRCLR0: POSIF1RS Mask         */\r
+#define SCU_RESET_PRCLR0_USIC0RS_Pos          11                                                      /*!< SCU_RESET PRCLR0: USIC0RS Position      */\r
+#define SCU_RESET_PRCLR0_USIC0RS_Msk          (0x01UL << SCU_RESET_PRCLR0_USIC0RS_Pos)                /*!< SCU_RESET PRCLR0: USIC0RS Mask          */\r
+#define SCU_RESET_PRCLR0_ERU1RS_Pos           16                                                      /*!< SCU_RESET PRCLR0: ERU1RS Position       */\r
+#define SCU_RESET_PRCLR0_ERU1RS_Msk           (0x01UL << SCU_RESET_PRCLR0_ERU1RS_Pos)                 /*!< SCU_RESET PRCLR0: ERU1RS Mask           */\r
+\r
+/* ------------------------------  SCU_RESET_PRSTAT1  ----------------------------- */\r
+#define SCU_RESET_PRSTAT1_CCU43RS_Pos         0                                                       /*!< SCU_RESET PRSTAT1: CCU43RS Position     */\r
+#define SCU_RESET_PRSTAT1_CCU43RS_Msk         (0x01UL << SCU_RESET_PRSTAT1_CCU43RS_Pos)               /*!< SCU_RESET PRSTAT1: CCU43RS Mask         */\r
+#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos      3                                                       /*!< SCU_RESET PRSTAT1: LEDTSCU0RS Position  */\r
+#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk      (0x01UL << SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos)            /*!< SCU_RESET PRSTAT1: LEDTSCU0RS Mask      */\r
+#define SCU_RESET_PRSTAT1_MCAN0RS_Pos         4                                                       /*!< SCU_RESET PRSTAT1: MCAN0RS Position     */\r
+#define SCU_RESET_PRSTAT1_MCAN0RS_Msk         (0x01UL << SCU_RESET_PRSTAT1_MCAN0RS_Pos)               /*!< SCU_RESET PRSTAT1: MCAN0RS Mask         */\r
+#define SCU_RESET_PRSTAT1_DACRS_Pos           5                                                       /*!< SCU_RESET PRSTAT1: DACRS Position       */\r
+#define SCU_RESET_PRSTAT1_DACRS_Msk           (0x01UL << SCU_RESET_PRSTAT1_DACRS_Pos)                 /*!< SCU_RESET PRSTAT1: DACRS Mask           */\r
+#define SCU_RESET_PRSTAT1_MMCIRS_Pos          6                                                       /*!< SCU_RESET PRSTAT1: MMCIRS Position      */\r
+#define SCU_RESET_PRSTAT1_MMCIRS_Msk          (0x01UL << SCU_RESET_PRSTAT1_MMCIRS_Pos)                /*!< SCU_RESET PRSTAT1: MMCIRS Mask          */\r
+#define SCU_RESET_PRSTAT1_USIC1RS_Pos         7                                                       /*!< SCU_RESET PRSTAT1: USIC1RS Position     */\r
+#define SCU_RESET_PRSTAT1_USIC1RS_Msk         (0x01UL << SCU_RESET_PRSTAT1_USIC1RS_Pos)               /*!< SCU_RESET PRSTAT1: USIC1RS Mask         */\r
+#define SCU_RESET_PRSTAT1_USIC2RS_Pos         8                                                       /*!< SCU_RESET PRSTAT1: USIC2RS Position     */\r
+#define SCU_RESET_PRSTAT1_USIC2RS_Msk         (0x01UL << SCU_RESET_PRSTAT1_USIC2RS_Pos)               /*!< SCU_RESET PRSTAT1: USIC2RS Mask         */\r
+#define SCU_RESET_PRSTAT1_PPORTSRS_Pos        9                                                       /*!< SCU_RESET PRSTAT1: PPORTSRS Position    */\r
+#define SCU_RESET_PRSTAT1_PPORTSRS_Msk        (0x01UL << SCU_RESET_PRSTAT1_PPORTSRS_Pos)              /*!< SCU_RESET PRSTAT1: PPORTSRS Mask        */\r
+\r
+/* ------------------------------  SCU_RESET_PRSET1  ------------------------------ */\r
+#define SCU_RESET_PRSET1_CCU43RS_Pos          0                                                       /*!< SCU_RESET PRSET1: CCU43RS Position      */\r
+#define SCU_RESET_PRSET1_CCU43RS_Msk          (0x01UL << SCU_RESET_PRSET1_CCU43RS_Pos)                /*!< SCU_RESET PRSET1: CCU43RS Mask          */\r
+#define SCU_RESET_PRSET1_LEDTSCU0RS_Pos       3                                                       /*!< SCU_RESET PRSET1: LEDTSCU0RS Position   */\r
+#define SCU_RESET_PRSET1_LEDTSCU0RS_Msk       (0x01UL << SCU_RESET_PRSET1_LEDTSCU0RS_Pos)             /*!< SCU_RESET PRSET1: LEDTSCU0RS Mask       */\r
+#define SCU_RESET_PRSET1_MCAN0RS_Pos          4                                                       /*!< SCU_RESET PRSET1: MCAN0RS Position      */\r
+#define SCU_RESET_PRSET1_MCAN0RS_Msk          (0x01UL << SCU_RESET_PRSET1_MCAN0RS_Pos)                /*!< SCU_RESET PRSET1: MCAN0RS Mask          */\r
+#define SCU_RESET_PRSET1_DACRS_Pos            5                                                       /*!< SCU_RESET PRSET1: DACRS Position        */\r
+#define SCU_RESET_PRSET1_DACRS_Msk            (0x01UL << SCU_RESET_PRSET1_DACRS_Pos)                  /*!< SCU_RESET PRSET1: DACRS Mask            */\r
+#define SCU_RESET_PRSET1_MMCIRS_Pos           6                                                       /*!< SCU_RESET PRSET1: MMCIRS Position       */\r
+#define SCU_RESET_PRSET1_MMCIRS_Msk           (0x01UL << SCU_RESET_PRSET1_MMCIRS_Pos)                 /*!< SCU_RESET PRSET1: MMCIRS Mask           */\r
+#define SCU_RESET_PRSET1_USIC1RS_Pos          7                                                       /*!< SCU_RESET PRSET1: USIC1RS Position      */\r
+#define SCU_RESET_PRSET1_USIC1RS_Msk          (0x01UL << SCU_RESET_PRSET1_USIC1RS_Pos)                /*!< SCU_RESET PRSET1: USIC1RS Mask          */\r
+#define SCU_RESET_PRSET1_USIC2RS_Pos          8                                                       /*!< SCU_RESET PRSET1: USIC2RS Position      */\r
+#define SCU_RESET_PRSET1_USIC2RS_Msk          (0x01UL << SCU_RESET_PRSET1_USIC2RS_Pos)                /*!< SCU_RESET PRSET1: USIC2RS Mask          */\r
+#define SCU_RESET_PRSET1_PPORTSRS_Pos         9                                                       /*!< SCU_RESET PRSET1: PPORTSRS Position     */\r
+#define SCU_RESET_PRSET1_PPORTSRS_Msk         (0x01UL << SCU_RESET_PRSET1_PPORTSRS_Pos)               /*!< SCU_RESET PRSET1: PPORTSRS Mask         */\r
+\r
+/* ------------------------------  SCU_RESET_PRCLR1  ------------------------------ */\r
+#define SCU_RESET_PRCLR1_CCU43RS_Pos          0                                                       /*!< SCU_RESET PRCLR1: CCU43RS Position      */\r
+#define SCU_RESET_PRCLR1_CCU43RS_Msk          (0x01UL << SCU_RESET_PRCLR1_CCU43RS_Pos)                /*!< SCU_RESET PRCLR1: CCU43RS Mask          */\r
+#define SCU_RESET_PRCLR1_LEDTSCU0RS_Pos       3                                                       /*!< SCU_RESET PRCLR1: LEDTSCU0RS Position   */\r
+#define SCU_RESET_PRCLR1_LEDTSCU0RS_Msk       (0x01UL << SCU_RESET_PRCLR1_LEDTSCU0RS_Pos)             /*!< SCU_RESET PRCLR1: LEDTSCU0RS Mask       */\r
+#define SCU_RESET_PRCLR1_MCAN0RS_Pos          4                                                       /*!< SCU_RESET PRCLR1: MCAN0RS Position      */\r
+#define SCU_RESET_PRCLR1_MCAN0RS_Msk          (0x01UL << SCU_RESET_PRCLR1_MCAN0RS_Pos)                /*!< SCU_RESET PRCLR1: MCAN0RS Mask          */\r
+#define SCU_RESET_PRCLR1_DACRS_Pos            5                                                       /*!< SCU_RESET PRCLR1: DACRS Position        */\r
+#define SCU_RESET_PRCLR1_DACRS_Msk            (0x01UL << SCU_RESET_PRCLR1_DACRS_Pos)                  /*!< SCU_RESET PRCLR1: DACRS Mask            */\r
+#define SCU_RESET_PRCLR1_MMCIRS_Pos           6                                                       /*!< SCU_RESET PRCLR1: MMCIRS Position       */\r
+#define SCU_RESET_PRCLR1_MMCIRS_Msk           (0x01UL << SCU_RESET_PRCLR1_MMCIRS_Pos)                 /*!< SCU_RESET PRCLR1: MMCIRS Mask           */\r
+#define SCU_RESET_PRCLR1_USIC1RS_Pos          7                                                       /*!< SCU_RESET PRCLR1: USIC1RS Position      */\r
+#define SCU_RESET_PRCLR1_USIC1RS_Msk          (0x01UL << SCU_RESET_PRCLR1_USIC1RS_Pos)                /*!< SCU_RESET PRCLR1: USIC1RS Mask          */\r
+#define SCU_RESET_PRCLR1_USIC2RS_Pos          8                                                       /*!< SCU_RESET PRCLR1: USIC2RS Position      */\r
+#define SCU_RESET_PRCLR1_USIC2RS_Msk          (0x01UL << SCU_RESET_PRCLR1_USIC2RS_Pos)                /*!< SCU_RESET PRCLR1: USIC2RS Mask          */\r
+#define SCU_RESET_PRCLR1_PPORTSRS_Pos         9                                                       /*!< SCU_RESET PRCLR1: PPORTSRS Position     */\r
+#define SCU_RESET_PRCLR1_PPORTSRS_Msk         (0x01UL << SCU_RESET_PRCLR1_PPORTSRS_Pos)               /*!< SCU_RESET PRCLR1: PPORTSRS Mask         */\r
+\r
+/* ------------------------------  SCU_RESET_PRSTAT2  ----------------------------- */\r
+#define SCU_RESET_PRSTAT2_WDTRS_Pos           1                                                       /*!< SCU_RESET PRSTAT2: WDTRS Position       */\r
+#define SCU_RESET_PRSTAT2_WDTRS_Msk           (0x01UL << SCU_RESET_PRSTAT2_WDTRS_Pos)                 /*!< SCU_RESET PRSTAT2: WDTRS Mask           */\r
+#define SCU_RESET_PRSTAT2_ETH0RS_Pos          2                                                       /*!< SCU_RESET PRSTAT2: ETH0RS Position      */\r
+#define SCU_RESET_PRSTAT2_ETH0RS_Msk          (0x01UL << SCU_RESET_PRSTAT2_ETH0RS_Pos)                /*!< SCU_RESET PRSTAT2: ETH0RS Mask          */\r
+#define SCU_RESET_PRSTAT2_DMA0RS_Pos          4                                                       /*!< SCU_RESET PRSTAT2: DMA0RS Position      */\r
+#define SCU_RESET_PRSTAT2_DMA0RS_Msk          (0x01UL << SCU_RESET_PRSTAT2_DMA0RS_Pos)                /*!< SCU_RESET PRSTAT2: DMA0RS Mask          */\r
+#define SCU_RESET_PRSTAT2_DMA1RS_Pos          5                                                       /*!< SCU_RESET PRSTAT2: DMA1RS Position      */\r
+#define SCU_RESET_PRSTAT2_DMA1RS_Msk          (0x01UL << SCU_RESET_PRSTAT2_DMA1RS_Pos)                /*!< SCU_RESET PRSTAT2: DMA1RS Mask          */\r
+#define SCU_RESET_PRSTAT2_FCERS_Pos           6                                                       /*!< SCU_RESET PRSTAT2: FCERS Position       */\r
+#define SCU_RESET_PRSTAT2_FCERS_Msk           (0x01UL << SCU_RESET_PRSTAT2_FCERS_Pos)                 /*!< SCU_RESET PRSTAT2: FCERS Mask           */\r
+#define SCU_RESET_PRSTAT2_USBRS_Pos           7                                                       /*!< SCU_RESET PRSTAT2: USBRS Position       */\r
+#define SCU_RESET_PRSTAT2_USBRS_Msk           (0x01UL << SCU_RESET_PRSTAT2_USBRS_Pos)                 /*!< SCU_RESET PRSTAT2: USBRS Mask           */\r
+\r
+/* ------------------------------  SCU_RESET_PRSET2  ------------------------------ */\r
+#define SCU_RESET_PRSET2_WDTRS_Pos            1                                                       /*!< SCU_RESET PRSET2: WDTRS Position        */\r
+#define SCU_RESET_PRSET2_WDTRS_Msk            (0x01UL << SCU_RESET_PRSET2_WDTRS_Pos)                  /*!< SCU_RESET PRSET2: WDTRS Mask            */\r
+#define SCU_RESET_PRSET2_ETH0RS_Pos           2                                                       /*!< SCU_RESET PRSET2: ETH0RS Position       */\r
+#define SCU_RESET_PRSET2_ETH0RS_Msk           (0x01UL << SCU_RESET_PRSET2_ETH0RS_Pos)                 /*!< SCU_RESET PRSET2: ETH0RS Mask           */\r
+#define SCU_RESET_PRSET2_DMA0RS_Pos           4                                                       /*!< SCU_RESET PRSET2: DMA0RS Position       */\r
+#define SCU_RESET_PRSET2_DMA0RS_Msk           (0x01UL << SCU_RESET_PRSET2_DMA0RS_Pos)                 /*!< SCU_RESET PRSET2: DMA0RS Mask           */\r
+#define SCU_RESET_PRSET2_DMA1RS_Pos           5                                                       /*!< SCU_RESET PRSET2: DMA1RS Position       */\r
+#define SCU_RESET_PRSET2_DMA1RS_Msk           (0x01UL << SCU_RESET_PRSET2_DMA1RS_Pos)                 /*!< SCU_RESET PRSET2: DMA1RS Mask           */\r
+#define SCU_RESET_PRSET2_FCERS_Pos            6                                                       /*!< SCU_RESET PRSET2: FCERS Position        */\r
+#define SCU_RESET_PRSET2_FCERS_Msk            (0x01UL << SCU_RESET_PRSET2_FCERS_Pos)                  /*!< SCU_RESET PRSET2: FCERS Mask            */\r
+#define SCU_RESET_PRSET2_USBRS_Pos            7                                                       /*!< SCU_RESET PRSET2: USBRS Position        */\r
+#define SCU_RESET_PRSET2_USBRS_Msk            (0x01UL << SCU_RESET_PRSET2_USBRS_Pos)                  /*!< SCU_RESET PRSET2: USBRS Mask            */\r
+\r
+/* ------------------------------  SCU_RESET_PRCLR2  ------------------------------ */\r
+#define SCU_RESET_PRCLR2_WDTRS_Pos            1                                                       /*!< SCU_RESET PRCLR2: WDTRS Position        */\r
+#define SCU_RESET_PRCLR2_WDTRS_Msk            (0x01UL << SCU_RESET_PRCLR2_WDTRS_Pos)                  /*!< SCU_RESET PRCLR2: WDTRS Mask            */\r
+#define SCU_RESET_PRCLR2_ETH0RS_Pos           2                                                       /*!< SCU_RESET PRCLR2: ETH0RS Position       */\r
+#define SCU_RESET_PRCLR2_ETH0RS_Msk           (0x01UL << SCU_RESET_PRCLR2_ETH0RS_Pos)                 /*!< SCU_RESET PRCLR2: ETH0RS Mask           */\r
+#define SCU_RESET_PRCLR2_DMA0RS_Pos           4                                                       /*!< SCU_RESET PRCLR2: DMA0RS Position       */\r
+#define SCU_RESET_PRCLR2_DMA0RS_Msk           (0x01UL << SCU_RESET_PRCLR2_DMA0RS_Pos)                 /*!< SCU_RESET PRCLR2: DMA0RS Mask           */\r
+#define SCU_RESET_PRCLR2_DMA1RS_Pos           5                                                       /*!< SCU_RESET PRCLR2: DMA1RS Position       */\r
+#define SCU_RESET_PRCLR2_DMA1RS_Msk           (0x01UL << SCU_RESET_PRCLR2_DMA1RS_Pos)                 /*!< SCU_RESET PRCLR2: DMA1RS Mask           */\r
+#define SCU_RESET_PRCLR2_FCERS_Pos            6                                                       /*!< SCU_RESET PRCLR2: FCERS Position        */\r
+#define SCU_RESET_PRCLR2_FCERS_Msk            (0x01UL << SCU_RESET_PRCLR2_FCERS_Pos)                  /*!< SCU_RESET PRCLR2: FCERS Mask            */\r
+#define SCU_RESET_PRCLR2_USBRS_Pos            7                                                       /*!< SCU_RESET PRCLR2: USBRS Position        */\r
+#define SCU_RESET_PRCLR2_USBRS_Msk            (0x01UL << SCU_RESET_PRCLR2_USBRS_Pos)                  /*!< SCU_RESET PRCLR2: USBRS Mask            */\r
+\r
+/* ------------------------------  SCU_RESET_PRSTAT3  ----------------------------- */\r
+#define SCU_RESET_PRSTAT3_EBURS_Pos           2                                                       /*!< SCU_RESET PRSTAT3: EBURS Position       */\r
+#define SCU_RESET_PRSTAT3_EBURS_Msk           (0x01UL << SCU_RESET_PRSTAT3_EBURS_Pos)                 /*!< SCU_RESET PRSTAT3: EBURS Mask           */\r
+\r
+/* ------------------------------  SCU_RESET_PRSET3  ------------------------------ */\r
+#define SCU_RESET_PRSET3_EBURS_Pos            2                                                       /*!< SCU_RESET PRSET3: EBURS Position        */\r
+#define SCU_RESET_PRSET3_EBURS_Msk            (0x01UL << SCU_RESET_PRSET3_EBURS_Pos)                  /*!< SCU_RESET PRSET3: EBURS Mask            */\r
+\r
+/* ------------------------------  SCU_RESET_PRCLR3  ------------------------------ */\r
+#define SCU_RESET_PRCLR3_EBURS_Pos            2                                                       /*!< SCU_RESET PRCLR3: EBURS Position        */\r
+#define SCU_RESET_PRCLR3_EBURS_Msk            (0x01UL << SCU_RESET_PRCLR3_EBURS_Pos)                  /*!< SCU_RESET PRCLR3: EBURS Mask            */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'LEDTS' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  LEDTS_ID  ---------------------------------- */\r
+#define LEDTS_ID_MOD_REV_Pos                  0                                                       /*!< LEDTS ID: MOD_REV Position              */\r
+#define LEDTS_ID_MOD_REV_Msk                  (0x000000ffUL << LEDTS_ID_MOD_REV_Pos)                  /*!< LEDTS ID: MOD_REV Mask                  */\r
+#define LEDTS_ID_MOD_TYPE_Pos                 8                                                       /*!< LEDTS ID: MOD_TYPE Position             */\r
+#define LEDTS_ID_MOD_TYPE_Msk                 (0x000000ffUL << LEDTS_ID_MOD_TYPE_Pos)                 /*!< LEDTS ID: MOD_TYPE Mask                 */\r
+#define LEDTS_ID_MOD_NUMBER_Pos               16                                                      /*!< LEDTS ID: MOD_NUMBER Position           */\r
+#define LEDTS_ID_MOD_NUMBER_Msk               (0x0000ffffUL << LEDTS_ID_MOD_NUMBER_Pos)               /*!< LEDTS ID: MOD_NUMBER Mask               */\r
+\r
+/* --------------------------------  LEDTS_GLOBCTL  ------------------------------- */\r
+#define LEDTS_GLOBCTL_TS_EN_Pos               0                                                       /*!< LEDTS GLOBCTL: TS_EN Position           */\r
+#define LEDTS_GLOBCTL_TS_EN_Msk               (0x01UL << LEDTS_GLOBCTL_TS_EN_Pos)                     /*!< LEDTS GLOBCTL: TS_EN Mask               */\r
+#define LEDTS_GLOBCTL_LD_EN_Pos               1                                                       /*!< LEDTS GLOBCTL: LD_EN Position           */\r
+#define LEDTS_GLOBCTL_LD_EN_Msk               (0x01UL << LEDTS_GLOBCTL_LD_EN_Pos)                     /*!< LEDTS GLOBCTL: LD_EN Mask               */\r
+#define LEDTS_GLOBCTL_CMTR_Pos                2                                                       /*!< LEDTS GLOBCTL: CMTR Position            */\r
+#define LEDTS_GLOBCTL_CMTR_Msk                (0x01UL << LEDTS_GLOBCTL_CMTR_Pos)                      /*!< LEDTS GLOBCTL: CMTR Mask                */\r
+#define LEDTS_GLOBCTL_ENSYNC_Pos              3                                                       /*!< LEDTS GLOBCTL: ENSYNC Position          */\r
+#define LEDTS_GLOBCTL_ENSYNC_Msk              (0x01UL << LEDTS_GLOBCTL_ENSYNC_Pos)                    /*!< LEDTS GLOBCTL: ENSYNC Mask              */\r
+#define LEDTS_GLOBCTL_SUSCFG_Pos              8                                                       /*!< LEDTS GLOBCTL: SUSCFG Position          */\r
+#define LEDTS_GLOBCTL_SUSCFG_Msk              (0x01UL << LEDTS_GLOBCTL_SUSCFG_Pos)                    /*!< LEDTS GLOBCTL: SUSCFG Mask              */\r
+#define LEDTS_GLOBCTL_MASKVAL_Pos             9                                                       /*!< LEDTS GLOBCTL: MASKVAL Position         */\r
+#define LEDTS_GLOBCTL_MASKVAL_Msk             (0x07UL << LEDTS_GLOBCTL_MASKVAL_Pos)                   /*!< LEDTS GLOBCTL: MASKVAL Mask             */\r
+#define LEDTS_GLOBCTL_FENVAL_Pos              12                                                      /*!< LEDTS GLOBCTL: FENVAL Position          */\r
+#define LEDTS_GLOBCTL_FENVAL_Msk              (0x01UL << LEDTS_GLOBCTL_FENVAL_Pos)                    /*!< LEDTS GLOBCTL: FENVAL Mask              */\r
+#define LEDTS_GLOBCTL_ITS_EN_Pos              13                                                      /*!< LEDTS GLOBCTL: ITS_EN Position          */\r
+#define LEDTS_GLOBCTL_ITS_EN_Msk              (0x01UL << LEDTS_GLOBCTL_ITS_EN_Pos)                    /*!< LEDTS GLOBCTL: ITS_EN Mask              */\r
+#define LEDTS_GLOBCTL_ITF_EN_Pos              14                                                      /*!< LEDTS GLOBCTL: ITF_EN Position          */\r
+#define LEDTS_GLOBCTL_ITF_EN_Msk              (0x01UL << LEDTS_GLOBCTL_ITF_EN_Pos)                    /*!< LEDTS GLOBCTL: ITF_EN Mask              */\r
+#define LEDTS_GLOBCTL_ITP_EN_Pos              15                                                      /*!< LEDTS GLOBCTL: ITP_EN Position          */\r
+#define LEDTS_GLOBCTL_ITP_EN_Msk              (0x01UL << LEDTS_GLOBCTL_ITP_EN_Pos)                    /*!< LEDTS GLOBCTL: ITP_EN Mask              */\r
+#define LEDTS_GLOBCTL_CLK_PS_Pos              16                                                      /*!< LEDTS GLOBCTL: CLK_PS Position          */\r
+#define LEDTS_GLOBCTL_CLK_PS_Msk              (0x0000ffffUL << LEDTS_GLOBCTL_CLK_PS_Pos)              /*!< LEDTS GLOBCTL: CLK_PS Mask              */\r
+\r
+/* ---------------------------------  LEDTS_FNCTL  -------------------------------- */\r
+#define LEDTS_FNCTL_PADT_Pos                  0                                                       /*!< LEDTS FNCTL: PADT Position              */\r
+#define LEDTS_FNCTL_PADT_Msk                  (0x07UL << LEDTS_FNCTL_PADT_Pos)                        /*!< LEDTS FNCTL: PADT Mask                  */\r
+#define LEDTS_FNCTL_PADTSW_Pos                3                                                       /*!< LEDTS FNCTL: PADTSW Position            */\r
+#define LEDTS_FNCTL_PADTSW_Msk                (0x01UL << LEDTS_FNCTL_PADTSW_Pos)                      /*!< LEDTS FNCTL: PADTSW Mask                */\r
+#define LEDTS_FNCTL_EPULL_Pos                 4                                                       /*!< LEDTS FNCTL: EPULL Position             */\r
+#define LEDTS_FNCTL_EPULL_Msk                 (0x01UL << LEDTS_FNCTL_EPULL_Pos)                       /*!< LEDTS FNCTL: EPULL Mask                 */\r
+#define LEDTS_FNCTL_FNCOL_Pos                 5                                                       /*!< LEDTS FNCTL: FNCOL Position             */\r
+#define LEDTS_FNCTL_FNCOL_Msk                 (0x07UL << LEDTS_FNCTL_FNCOL_Pos)                       /*!< LEDTS FNCTL: FNCOL Mask                 */\r
+#define LEDTS_FNCTL_ACCCNT_Pos                16                                                      /*!< LEDTS FNCTL: ACCCNT Position            */\r
+#define LEDTS_FNCTL_ACCCNT_Msk                (0x0fUL << LEDTS_FNCTL_ACCCNT_Pos)                      /*!< LEDTS FNCTL: ACCCNT Mask                */\r
+#define LEDTS_FNCTL_TSCCMP_Pos                20                                                      /*!< LEDTS FNCTL: TSCCMP Position            */\r
+#define LEDTS_FNCTL_TSCCMP_Msk                (0x01UL << LEDTS_FNCTL_TSCCMP_Pos)                      /*!< LEDTS FNCTL: TSCCMP Mask                */\r
+#define LEDTS_FNCTL_TSOEXT_Pos                21                                                      /*!< LEDTS FNCTL: TSOEXT Position            */\r
+#define LEDTS_FNCTL_TSOEXT_Msk                (0x03UL << LEDTS_FNCTL_TSOEXT_Pos)                      /*!< LEDTS FNCTL: TSOEXT Mask                */\r
+#define LEDTS_FNCTL_TSCTRR_Pos                23                                                      /*!< LEDTS FNCTL: TSCTRR Position            */\r
+#define LEDTS_FNCTL_TSCTRR_Msk                (0x01UL << LEDTS_FNCTL_TSCTRR_Pos)                      /*!< LEDTS FNCTL: TSCTRR Mask                */\r
+#define LEDTS_FNCTL_TSCTRSAT_Pos              24                                                      /*!< LEDTS FNCTL: TSCTRSAT Position          */\r
+#define LEDTS_FNCTL_TSCTRSAT_Msk              (0x01UL << LEDTS_FNCTL_TSCTRSAT_Pos)                    /*!< LEDTS FNCTL: TSCTRSAT Mask              */\r
+#define LEDTS_FNCTL_NR_TSIN_Pos               25                                                      /*!< LEDTS FNCTL: NR_TSIN Position           */\r
+#define LEDTS_FNCTL_NR_TSIN_Msk               (0x07UL << LEDTS_FNCTL_NR_TSIN_Pos)                     /*!< LEDTS FNCTL: NR_TSIN Mask               */\r
+#define LEDTS_FNCTL_COLLEV_Pos                28                                                      /*!< LEDTS FNCTL: COLLEV Position            */\r
+#define LEDTS_FNCTL_COLLEV_Msk                (0x01UL << LEDTS_FNCTL_COLLEV_Pos)                      /*!< LEDTS FNCTL: COLLEV Mask                */\r
+#define LEDTS_FNCTL_NR_LEDCOL_Pos             29                                                      /*!< LEDTS FNCTL: NR_LEDCOL Position         */\r
+#define LEDTS_FNCTL_NR_LEDCOL_Msk             (0x07UL << LEDTS_FNCTL_NR_LEDCOL_Pos)                   /*!< LEDTS FNCTL: NR_LEDCOL Mask             */\r
+\r
+/* ---------------------------------  LEDTS_EVFR  --------------------------------- */\r
+#define LEDTS_EVFR_TSF_Pos                    0                                                       /*!< LEDTS EVFR: TSF Position                */\r
+#define LEDTS_EVFR_TSF_Msk                    (0x01UL << LEDTS_EVFR_TSF_Pos)                          /*!< LEDTS EVFR: TSF Mask                    */\r
+#define LEDTS_EVFR_TFF_Pos                    1                                                       /*!< LEDTS EVFR: TFF Position                */\r
+#define LEDTS_EVFR_TFF_Msk                    (0x01UL << LEDTS_EVFR_TFF_Pos)                          /*!< LEDTS EVFR: TFF Mask                    */\r
+#define LEDTS_EVFR_TPF_Pos                    2                                                       /*!< LEDTS EVFR: TPF Position                */\r
+#define LEDTS_EVFR_TPF_Msk                    (0x01UL << LEDTS_EVFR_TPF_Pos)                          /*!< LEDTS EVFR: TPF Mask                    */\r
+#define LEDTS_EVFR_TSCTROVF_Pos               3                                                       /*!< LEDTS EVFR: TSCTROVF Position           */\r
+#define LEDTS_EVFR_TSCTROVF_Msk               (0x01UL << LEDTS_EVFR_TSCTROVF_Pos)                     /*!< LEDTS EVFR: TSCTROVF Mask               */\r
+#define LEDTS_EVFR_CTSF_Pos                   16                                                      /*!< LEDTS EVFR: CTSF Position               */\r
+#define LEDTS_EVFR_CTSF_Msk                   (0x01UL << LEDTS_EVFR_CTSF_Pos)                         /*!< LEDTS EVFR: CTSF Mask                   */\r
+#define LEDTS_EVFR_CTFF_Pos                   17                                                      /*!< LEDTS EVFR: CTFF Position               */\r
+#define LEDTS_EVFR_CTFF_Msk                   (0x01UL << LEDTS_EVFR_CTFF_Pos)                         /*!< LEDTS EVFR: CTFF Mask                   */\r
+#define LEDTS_EVFR_CTPF_Pos                   18                                                      /*!< LEDTS EVFR: CTPF Position               */\r
+#define LEDTS_EVFR_CTPF_Msk                   (0x01UL << LEDTS_EVFR_CTPF_Pos)                         /*!< LEDTS EVFR: CTPF Mask                   */\r
+\r
+/* ---------------------------------  LEDTS_TSVAL  -------------------------------- */\r
+#define LEDTS_TSVAL_TSCTRVALR_Pos             0                                                       /*!< LEDTS TSVAL: TSCTRVALR Position         */\r
+#define LEDTS_TSVAL_TSCTRVALR_Msk             (0x0000ffffUL << LEDTS_TSVAL_TSCTRVALR_Pos)             /*!< LEDTS TSVAL: TSCTRVALR Mask             */\r
+#define LEDTS_TSVAL_TSCTRVAL_Pos              16                                                      /*!< LEDTS TSVAL: TSCTRVAL Position          */\r
+#define LEDTS_TSVAL_TSCTRVAL_Msk              (0x0000ffffUL << LEDTS_TSVAL_TSCTRVAL_Pos)              /*!< LEDTS TSVAL: TSCTRVAL Mask              */\r
+\r
+/* ---------------------------------  LEDTS_LINE0  -------------------------------- */\r
+#define LEDTS_LINE0_LINE_0_Pos                0                                                       /*!< LEDTS LINE0: LINE_0 Position            */\r
+#define LEDTS_LINE0_LINE_0_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_0_Pos)                /*!< LEDTS LINE0: LINE_0 Mask                */\r
+#define LEDTS_LINE0_LINE_1_Pos                8                                                       /*!< LEDTS LINE0: LINE_1 Position            */\r
+#define LEDTS_LINE0_LINE_1_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_1_Pos)                /*!< LEDTS LINE0: LINE_1 Mask                */\r
+#define LEDTS_LINE0_LINE_2_Pos                16                                                      /*!< LEDTS LINE0: LINE_2 Position            */\r
+#define LEDTS_LINE0_LINE_2_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_2_Pos)                /*!< LEDTS LINE0: LINE_2 Mask                */\r
+#define LEDTS_LINE0_LINE_3_Pos                24                                                      /*!< LEDTS LINE0: LINE_3 Position            */\r
+#define LEDTS_LINE0_LINE_3_Msk                (0x000000ffUL << LEDTS_LINE0_LINE_3_Pos)                /*!< LEDTS LINE0: LINE_3 Mask                */\r
+\r
+/* ---------------------------------  LEDTS_LINE1  -------------------------------- */\r
+#define LEDTS_LINE1_LINE_4_Pos                0                                                       /*!< LEDTS LINE1: LINE_4 Position            */\r
+#define LEDTS_LINE1_LINE_4_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_4_Pos)                /*!< LEDTS LINE1: LINE_4 Mask                */\r
+#define LEDTS_LINE1_LINE_5_Pos                8                                                       /*!< LEDTS LINE1: LINE_5 Position            */\r
+#define LEDTS_LINE1_LINE_5_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_5_Pos)                /*!< LEDTS LINE1: LINE_5 Mask                */\r
+#define LEDTS_LINE1_LINE_6_Pos                16                                                      /*!< LEDTS LINE1: LINE_6 Position            */\r
+#define LEDTS_LINE1_LINE_6_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_6_Pos)                /*!< LEDTS LINE1: LINE_6 Mask                */\r
+#define LEDTS_LINE1_LINE_A_Pos                24                                                      /*!< LEDTS LINE1: LINE_A Position            */\r
+#define LEDTS_LINE1_LINE_A_Msk                (0x000000ffUL << LEDTS_LINE1_LINE_A_Pos)                /*!< LEDTS LINE1: LINE_A Mask                */\r
+\r
+/* --------------------------------  LEDTS_LDCMP0  -------------------------------- */\r
+#define LEDTS_LDCMP0_CMP_LD0_Pos              0                                                       /*!< LEDTS LDCMP0: CMP_LD0 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD0_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD0_Pos)              /*!< LEDTS LDCMP0: CMP_LD0 Mask              */\r
+#define LEDTS_LDCMP0_CMP_LD1_Pos              8                                                       /*!< LEDTS LDCMP0: CMP_LD1 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD1_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD1_Pos)              /*!< LEDTS LDCMP0: CMP_LD1 Mask              */\r
+#define LEDTS_LDCMP0_CMP_LD2_Pos              16                                                      /*!< LEDTS LDCMP0: CMP_LD2 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD2_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD2_Pos)              /*!< LEDTS LDCMP0: CMP_LD2 Mask              */\r
+#define LEDTS_LDCMP0_CMP_LD3_Pos              24                                                      /*!< LEDTS LDCMP0: CMP_LD3 Position          */\r
+#define LEDTS_LDCMP0_CMP_LD3_Msk              (0x000000ffUL << LEDTS_LDCMP0_CMP_LD3_Pos)              /*!< LEDTS LDCMP0: CMP_LD3 Mask              */\r
+\r
+/* --------------------------------  LEDTS_LDCMP1  -------------------------------- */\r
+#define LEDTS_LDCMP1_CMP_LD4_Pos              0                                                       /*!< LEDTS LDCMP1: CMP_LD4 Position          */\r
+#define LEDTS_LDCMP1_CMP_LD4_Msk              (0x000000ffUL << LEDTS_LDCMP1_CMP_LD4_Pos)              /*!< LEDTS LDCMP1: CMP_LD4 Mask              */\r
+#define LEDTS_LDCMP1_CMP_LD5_Pos              8                                                       /*!< LEDTS LDCMP1: CMP_LD5 Position          */\r
+#define LEDTS_LDCMP1_CMP_LD5_Msk              (0x000000ffUL << LEDTS_LDCMP1_CMP_LD5_Pos)              /*!< LEDTS LDCMP1: CMP_LD5 Mask              */\r
+#define LEDTS_LDCMP1_CMP_LD6_Pos              16                                                      /*!< LEDTS LDCMP1: CMP_LD6 Position          */\r
+#define LEDTS_LDCMP1_CMP_LD6_Msk              (0x000000ffUL << LEDTS_LDCMP1_CMP_LD6_Pos)              /*!< LEDTS LDCMP1: CMP_LD6 Mask              */\r
+#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos        24                                                      /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Position    */\r
+#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk        (0x000000ffUL << LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos)        /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Mask        */\r
+\r
+/* --------------------------------  LEDTS_TSCMP0  -------------------------------- */\r
+#define LEDTS_TSCMP0_CMP_TS0_Pos              0                                                       /*!< LEDTS TSCMP0: CMP_TS0 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS0_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS0_Pos)              /*!< LEDTS TSCMP0: CMP_TS0 Mask              */\r
+#define LEDTS_TSCMP0_CMP_TS1_Pos              8                                                       /*!< LEDTS TSCMP0: CMP_TS1 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS1_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS1_Pos)              /*!< LEDTS TSCMP0: CMP_TS1 Mask              */\r
+#define LEDTS_TSCMP0_CMP_TS2_Pos              16                                                      /*!< LEDTS TSCMP0: CMP_TS2 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS2_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS2_Pos)              /*!< LEDTS TSCMP0: CMP_TS2 Mask              */\r
+#define LEDTS_TSCMP0_CMP_TS3_Pos              24                                                      /*!< LEDTS TSCMP0: CMP_TS3 Position          */\r
+#define LEDTS_TSCMP0_CMP_TS3_Msk              (0x000000ffUL << LEDTS_TSCMP0_CMP_TS3_Pos)              /*!< LEDTS TSCMP0: CMP_TS3 Mask              */\r
+\r
+/* --------------------------------  LEDTS_TSCMP1  -------------------------------- */\r
+#define LEDTS_TSCMP1_CMP_TS4_Pos              0                                                       /*!< LEDTS TSCMP1: CMP_TS4 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS4_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS4_Pos)              /*!< LEDTS TSCMP1: CMP_TS4 Mask              */\r
+#define LEDTS_TSCMP1_CMP_TS5_Pos              8                                                       /*!< LEDTS TSCMP1: CMP_TS5 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS5_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS5_Pos)              /*!< LEDTS TSCMP1: CMP_TS5 Mask              */\r
+#define LEDTS_TSCMP1_CMP_TS6_Pos              16                                                      /*!< LEDTS TSCMP1: CMP_TS6 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS6_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS6_Pos)              /*!< LEDTS TSCMP1: CMP_TS6 Mask              */\r
+#define LEDTS_TSCMP1_CMP_TS7_Pos              24                                                      /*!< LEDTS TSCMP1: CMP_TS7 Position          */\r
+#define LEDTS_TSCMP1_CMP_TS7_Msk              (0x000000ffUL << LEDTS_TSCMP1_CMP_TS7_Pos)              /*!< LEDTS TSCMP1: CMP_TS7 Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'SDMMC' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  SDMMC_BLOCK_SIZE  ------------------------------ */\r
+#define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Pos    0                                                       /*!< SDMMC BLOCK_SIZE: TX_BLOCK_SIZE Position */\r
+#define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Msk    (0x00000fffUL << SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Pos)    /*!< SDMMC BLOCK_SIZE: TX_BLOCK_SIZE Mask    */\r
+#define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Pos 15                                                      /*!< SDMMC BLOCK_SIZE: TX_BLOCK_SIZE_12 Position */\r
+#define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Msk (0x01UL << SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Pos)       /*!< SDMMC BLOCK_SIZE: TX_BLOCK_SIZE_12 Mask */\r
+\r
+/* ------------------------------  SDMMC_BLOCK_COUNT  ----------------------------- */\r
+#define SDMMC_BLOCK_COUNT_BLOCK_COUNT_Pos     0                                                       /*!< SDMMC BLOCK_COUNT: BLOCK_COUNT Position */\r
+#define SDMMC_BLOCK_COUNT_BLOCK_COUNT_Msk     (0x0000ffffUL << SDMMC_BLOCK_COUNT_BLOCK_COUNT_Pos)     /*!< SDMMC BLOCK_COUNT: BLOCK_COUNT Mask     */\r
+\r
+/* -------------------------------  SDMMC_ARGUMENT1  ------------------------------ */\r
+#define SDMMC_ARGUMENT1_ARGUMENT1_Pos         0                                                       /*!< SDMMC ARGUMENT1: ARGUMENT1 Position     */\r
+#define SDMMC_ARGUMENT1_ARGUMENT1_Msk         (0xffffffffUL << SDMMC_ARGUMENT1_ARGUMENT1_Pos)         /*!< SDMMC ARGUMENT1: ARGUMENT1 Mask         */\r
+\r
+/* -----------------------------  SDMMC_TRANSFER_MODE  ---------------------------- */\r
+#define SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Pos 1                                                      /*!< SDMMC TRANSFER_MODE: BLOCK_COUNT_EN Position */\r
+#define SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Msk (0x01UL << SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Pos)     /*!< SDMMC TRANSFER_MODE: BLOCK_COUNT_EN Mask */\r
+#define SDMMC_TRANSFER_MODE_ACMD_EN_Pos       2                                                       /*!< SDMMC TRANSFER_MODE: ACMD_EN Position   */\r
+#define SDMMC_TRANSFER_MODE_ACMD_EN_Msk       (0x03UL << SDMMC_TRANSFER_MODE_ACMD_EN_Pos)             /*!< SDMMC TRANSFER_MODE: ACMD_EN Mask       */\r
+#define SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos 4                                                       /*!< SDMMC TRANSFER_MODE: TX_DIR_SELECT Position */\r
+#define SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Msk (0x01UL << SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos)       /*!< SDMMC TRANSFER_MODE: TX_DIR_SELECT Mask */\r
+#define SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Pos 5                                                  /*!< SDMMC TRANSFER_MODE: MULTI_BLOCK_SELECT Position */\r
+#define SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Msk (0x01UL << SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Pos)/*!< SDMMC TRANSFER_MODE: MULTI_BLOCK_SELECT Mask */\r
+#define SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Pos  6                                                       /*!< SDMMC TRANSFER_MODE: CMD_COMP_ATA Position */\r
+#define SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Msk  (0x01UL << SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Pos)        /*!< SDMMC TRANSFER_MODE: CMD_COMP_ATA Mask  */\r
+\r
+/* --------------------------------  SDMMC_COMMAND  ------------------------------- */\r
+#define SDMMC_COMMAND_RESP_TYPE_SELECT_Pos    0                                                       /*!< SDMMC COMMAND: RESP_TYPE_SELECT Position */\r
+#define SDMMC_COMMAND_RESP_TYPE_SELECT_Msk    (0x03UL << SDMMC_COMMAND_RESP_TYPE_SELECT_Pos)          /*!< SDMMC COMMAND: RESP_TYPE_SELECT Mask    */\r
+#define SDMMC_COMMAND_CMD_CRC_CHECK_EN_Pos    3                                                       /*!< SDMMC COMMAND: CMD_CRC_CHECK_EN Position */\r
+#define SDMMC_COMMAND_CMD_CRC_CHECK_EN_Msk    (0x01UL << SDMMC_COMMAND_CMD_CRC_CHECK_EN_Pos)          /*!< SDMMC COMMAND: CMD_CRC_CHECK_EN Mask    */\r
+#define SDMMC_COMMAND_CMD_IND_CHECK_EN_Pos    4                                                       /*!< SDMMC COMMAND: CMD_IND_CHECK_EN Position */\r
+#define SDMMC_COMMAND_CMD_IND_CHECK_EN_Msk    (0x01UL << SDMMC_COMMAND_CMD_IND_CHECK_EN_Pos)          /*!< SDMMC COMMAND: CMD_IND_CHECK_EN Mask    */\r
+#define SDMMC_COMMAND_DATA_PRESENT_SELECT_Pos 5                                                       /*!< SDMMC COMMAND: DATA_PRESENT_SELECT Position */\r
+#define SDMMC_COMMAND_DATA_PRESENT_SELECT_Msk (0x01UL << SDMMC_COMMAND_DATA_PRESENT_SELECT_Pos)       /*!< SDMMC COMMAND: DATA_PRESENT_SELECT Mask */\r
+#define SDMMC_COMMAND_CMD_TYPE_Pos            6                                                       /*!< SDMMC COMMAND: CMD_TYPE Position        */\r
+#define SDMMC_COMMAND_CMD_TYPE_Msk            (0x03UL << SDMMC_COMMAND_CMD_TYPE_Pos)                  /*!< SDMMC COMMAND: CMD_TYPE Mask            */\r
+#define SDMMC_COMMAND_CMD_IND_Pos             8                                                       /*!< SDMMC COMMAND: CMD_IND Position         */\r
+#define SDMMC_COMMAND_CMD_IND_Msk             (0x3fUL << SDMMC_COMMAND_CMD_IND_Pos)                   /*!< SDMMC COMMAND: CMD_IND Mask             */\r
+\r
+/* -------------------------------  SDMMC_RESPONSE0  ------------------------------ */\r
+#define SDMMC_RESPONSE0_RESPONSE0_Pos         0                                                       /*!< SDMMC RESPONSE0: RESPONSE0 Position     */\r
+#define SDMMC_RESPONSE0_RESPONSE0_Msk         (0x0000ffffUL << SDMMC_RESPONSE0_RESPONSE0_Pos)         /*!< SDMMC RESPONSE0: RESPONSE0 Mask         */\r
+#define SDMMC_RESPONSE0_RESPONSE1_Pos         16                                                      /*!< SDMMC RESPONSE0: RESPONSE1 Position     */\r
+#define SDMMC_RESPONSE0_RESPONSE1_Msk         (0x0000ffffUL << SDMMC_RESPONSE0_RESPONSE1_Pos)         /*!< SDMMC RESPONSE0: RESPONSE1 Mask         */\r
+\r
+/* -------------------------------  SDMMC_RESPONSE2  ------------------------------ */\r
+#define SDMMC_RESPONSE2_RESPONSE2_Pos         0                                                       /*!< SDMMC RESPONSE2: RESPONSE2 Position     */\r
+#define SDMMC_RESPONSE2_RESPONSE2_Msk         (0x0000ffffUL << SDMMC_RESPONSE2_RESPONSE2_Pos)         /*!< SDMMC RESPONSE2: RESPONSE2 Mask         */\r
+#define SDMMC_RESPONSE2_RESPONSE3_Pos         16                                                      /*!< SDMMC RESPONSE2: RESPONSE3 Position     */\r
+#define SDMMC_RESPONSE2_RESPONSE3_Msk         (0x0000ffffUL << SDMMC_RESPONSE2_RESPONSE3_Pos)         /*!< SDMMC RESPONSE2: RESPONSE3 Mask         */\r
+\r
+/* -------------------------------  SDMMC_RESPONSE4  ------------------------------ */\r
+#define SDMMC_RESPONSE4_RESPONSE4_Pos         0                                                       /*!< SDMMC RESPONSE4: RESPONSE4 Position     */\r
+#define SDMMC_RESPONSE4_RESPONSE4_Msk         (0x0000ffffUL << SDMMC_RESPONSE4_RESPONSE4_Pos)         /*!< SDMMC RESPONSE4: RESPONSE4 Mask         */\r
+#define SDMMC_RESPONSE4_RESPONSE5_Pos         16                                                      /*!< SDMMC RESPONSE4: RESPONSE5 Position     */\r
+#define SDMMC_RESPONSE4_RESPONSE5_Msk         (0x0000ffffUL << SDMMC_RESPONSE4_RESPONSE5_Pos)         /*!< SDMMC RESPONSE4: RESPONSE5 Mask         */\r
+\r
+/* -------------------------------  SDMMC_RESPONSE6  ------------------------------ */\r
+#define SDMMC_RESPONSE6_RESPONSE6_Pos         0                                                       /*!< SDMMC RESPONSE6: RESPONSE6 Position     */\r
+#define SDMMC_RESPONSE6_RESPONSE6_Msk         (0x0000ffffUL << SDMMC_RESPONSE6_RESPONSE6_Pos)         /*!< SDMMC RESPONSE6: RESPONSE6 Mask         */\r
+#define SDMMC_RESPONSE6_RESPONSE7_Pos         16                                                      /*!< SDMMC RESPONSE6: RESPONSE7 Position     */\r
+#define SDMMC_RESPONSE6_RESPONSE7_Msk         (0x0000ffffUL << SDMMC_RESPONSE6_RESPONSE7_Pos)         /*!< SDMMC RESPONSE6: RESPONSE7 Mask         */\r
+\r
+/* ------------------------------  SDMMC_DATA_BUFFER  ----------------------------- */\r
+#define SDMMC_DATA_BUFFER_DATA_BUFFER_Pos     0                                                       /*!< SDMMC DATA_BUFFER: DATA_BUFFER Position */\r
+#define SDMMC_DATA_BUFFER_DATA_BUFFER_Msk     (0xffffffffUL << SDMMC_DATA_BUFFER_DATA_BUFFER_Pos)     /*!< SDMMC DATA_BUFFER: DATA_BUFFER Mask     */\r
+\r
+/* -----------------------------  SDMMC_PRESENT_STATE  ---------------------------- */\r
+#define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Pos 0                                                 /*!< SDMMC PRESENT_STATE: COMMAND_INHIBIT_CMD Position */\r
+#define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Msk (0x01UL << SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Pos)/*!< SDMMC PRESENT_STATE: COMMAND_INHIBIT_CMD Mask */\r
+#define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Pos 1                                                 /*!< SDMMC PRESENT_STATE: COMMAND_INHIBIT_DAT Position */\r
+#define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Msk (0x01UL << SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Pos)/*!< SDMMC PRESENT_STATE: COMMAND_INHIBIT_DAT Mask */\r
+#define SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Pos 2                                                     /*!< SDMMC PRESENT_STATE: DAT_LINE_ACTIVE Position */\r
+#define SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Msk (0x01UL << SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Pos)   /*!< SDMMC PRESENT_STATE: DAT_LINE_ACTIVE Mask */\r
+#define SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Pos 8                                               /*!< SDMMC PRESENT_STATE: WRITE_TRANSFER_ACTIVE Position */\r
+#define SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Msk (0x01UL << SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Pos)/*!< SDMMC PRESENT_STATE: WRITE_TRANSFER_ACTIVE Mask */\r
+#define SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Pos 9                                                /*!< SDMMC PRESENT_STATE: READ_TRANSFER_ACTIVE Position */\r
+#define SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Msk (0x01UL << SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Pos)/*!< SDMMC PRESENT_STATE: READ_TRANSFER_ACTIVE Mask */\r
+#define SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Pos 10                                                /*!< SDMMC PRESENT_STATE: BUFFER_WRITE_ENABLE Position */\r
+#define SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Msk (0x01UL << SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Pos)/*!< SDMMC PRESENT_STATE: BUFFER_WRITE_ENABLE Mask */\r
+#define SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Pos 11                                                 /*!< SDMMC PRESENT_STATE: BUFFER_READ_ENABLE Position */\r
+#define SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Msk (0x01UL << SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Pos)/*!< SDMMC PRESENT_STATE: BUFFER_READ_ENABLE Mask */\r
+#define SDMMC_PRESENT_STATE_CARD_INSERTED_Pos 16                                                      /*!< SDMMC PRESENT_STATE: CARD_INSERTED Position */\r
+#define SDMMC_PRESENT_STATE_CARD_INSERTED_Msk (0x01UL << SDMMC_PRESENT_STATE_CARD_INSERTED_Pos)       /*!< SDMMC PRESENT_STATE: CARD_INSERTED Mask */\r
+#define SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Pos 17                                                  /*!< SDMMC PRESENT_STATE: CARD_STATE_STABLE Position */\r
+#define SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Msk (0x01UL << SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Pos)/*!< SDMMC PRESENT_STATE: CARD_STATE_STABLE Mask */\r
+#define SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Pos 18                                              /*!< SDMMC PRESENT_STATE: CARD_DETECT_PIN_LEVEL Position */\r
+#define SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Msk (0x01UL << SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Pos)/*!< SDMMC PRESENT_STATE: CARD_DETECT_PIN_LEVEL Mask */\r
+#define SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Pos 19                                            /*!< SDMMC PRESENT_STATE: WRITE_PROTECT_PIN_LEVEL Position */\r
+#define SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Msk (0x01UL << SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Pos)/*!< SDMMC PRESENT_STATE: WRITE_PROTECT_PIN_LEVEL Mask */\r
+#define SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos 20                                                  /*!< SDMMC PRESENT_STATE: DAT_3_0_PIN_LEVEL Position */\r
+#define SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Msk (0x0fUL << SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos)/*!< SDMMC PRESENT_STATE: DAT_3_0_PIN_LEVEL Mask */\r
+#define SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Pos 24                                                     /*!< SDMMC PRESENT_STATE: CMD_LINE_LEVEL Position */\r
+#define SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Msk (0x01UL << SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Pos)     /*!< SDMMC PRESENT_STATE: CMD_LINE_LEVEL Mask */\r
+#define SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Pos 25                                                  /*!< SDMMC PRESENT_STATE: DAT_7_4_PIN_LEVEL Position */\r
+#define SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Msk (0x0fUL << SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Pos)/*!< SDMMC PRESENT_STATE: DAT_7_4_PIN_LEVEL Mask */\r
+\r
+/* -------------------------------  SDMMC_HOST_CTRL  ------------------------------ */\r
+#define SDMMC_HOST_CTRL_LED_CTRL_Pos          0                                                       /*!< SDMMC HOST_CTRL: LED_CTRL Position      */\r
+#define SDMMC_HOST_CTRL_LED_CTRL_Msk          (0x01UL << SDMMC_HOST_CTRL_LED_CTRL_Pos)                /*!< SDMMC HOST_CTRL: LED_CTRL Mask          */\r
+#define SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos     1                                                       /*!< SDMMC HOST_CTRL: DATA_TX_WIDTH Position */\r
+#define SDMMC_HOST_CTRL_DATA_TX_WIDTH_Msk     (0x01UL << SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos)           /*!< SDMMC HOST_CTRL: DATA_TX_WIDTH Mask     */\r
+#define SDMMC_HOST_CTRL_HIGH_SPEED_EN_Pos     2                                                       /*!< SDMMC HOST_CTRL: HIGH_SPEED_EN Position */\r
+#define SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk     (0x01UL << SDMMC_HOST_CTRL_HIGH_SPEED_EN_Pos)           /*!< SDMMC HOST_CTRL: HIGH_SPEED_EN Mask     */\r
+#define SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos 6                                                  /*!< SDMMC HOST_CTRL: CARD_DETECT_TEST_LEVEL Position */\r
+#define SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Msk (0x01UL << SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos)/*!< SDMMC HOST_CTRL: CARD_DETECT_TEST_LEVEL Mask */\r
+#define SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos 7                                                  /*!< SDMMC HOST_CTRL: CARD_DET_SIGNAL_DETECT Position */\r
+#define SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Msk (0x01UL << SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos)/*!< SDMMC HOST_CTRL: CARD_DET_SIGNAL_DETECT Mask */\r
+\r
+/* ------------------------------  SDMMC_POWER_CTRL  ------------------------------ */\r
+#define SDMMC_POWER_CTRL_SD_BUS_POWER_Pos     0                                                       /*!< SDMMC POWER_CTRL: SD_BUS_POWER Position */\r
+#define SDMMC_POWER_CTRL_SD_BUS_POWER_Msk     (0x01UL << SDMMC_POWER_CTRL_SD_BUS_POWER_Pos)           /*!< SDMMC POWER_CTRL: SD_BUS_POWER Mask     */\r
+#define SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos 1                                                     /*!< SDMMC POWER_CTRL: SD_BUS_VOLTAGE_SEL Position */\r
+#define SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Msk (0x07UL << SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos)   /*!< SDMMC POWER_CTRL: SD_BUS_VOLTAGE_SEL Mask */\r
+#define SDMMC_POWER_CTRL_HARDWARE_RESET_Pos   4                                                       /*!< SDMMC POWER_CTRL: HARDWARE_RESET Position */\r
+#define SDMMC_POWER_CTRL_HARDWARE_RESET_Msk   (0x01UL << SDMMC_POWER_CTRL_HARDWARE_RESET_Pos)         /*!< SDMMC POWER_CTRL: HARDWARE_RESET Mask   */\r
+\r
+/* ----------------------------  SDMMC_BLOCK_GAP_CTRL  ---------------------------- */\r
+#define SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Pos 0                                                  /*!< SDMMC BLOCK_GAP_CTRL: STOP_AT_BLOCK_GAP Position */\r
+#define SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Msk (0x01UL << SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Pos)/*!< SDMMC BLOCK_GAP_CTRL: STOP_AT_BLOCK_GAP Mask */\r
+#define SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos 1                                                       /*!< SDMMC BLOCK_GAP_CTRL: CONTINUE_REQ Position */\r
+#define SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Msk (0x01UL << SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos)       /*!< SDMMC BLOCK_GAP_CTRL: CONTINUE_REQ Mask */\r
+#define SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Pos 2                                                     /*!< SDMMC BLOCK_GAP_CTRL: READ_WAIT_CTRL Position */\r
+#define SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Msk (0x01UL << SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Pos)   /*!< SDMMC BLOCK_GAP_CTRL: READ_WAIT_CTRL Mask */\r
+#define SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Pos 3                                                   /*!< SDMMC BLOCK_GAP_CTRL: INT_AT_BLOCK_GAP Position */\r
+#define SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk (0x01UL << SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Pos)/*!< SDMMC BLOCK_GAP_CTRL: INT_AT_BLOCK_GAP Mask */\r
+#define SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Pos     4                                                       /*!< SDMMC BLOCK_GAP_CTRL: SPI_MODE Position */\r
+#define SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Msk     (0x01UL << SDMMC_BLOCK_GAP_CTRL_SPI_MODE_Pos)           /*!< SDMMC BLOCK_GAP_CTRL: SPI_MODE Mask     */\r
+\r
+/* ------------------------------  SDMMC_WAKEUP_CTRL  ----------------------------- */\r
+#define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Pos 0                                                   /*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_INT Position */\r
+#define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Msk (0x01UL << SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Pos)/*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_INT Mask */\r
+#define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Pos 1                                                   /*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_INS Position */\r
+#define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Msk (0x01UL << SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Pos)/*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_INS Mask */\r
+#define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Pos 2                                                   /*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_REM Position */\r
+#define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Msk (0x01UL << SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Pos)/*!< SDMMC WAKEUP_CTRL: WAKEUP_EVENT_EN_REM Mask */\r
+\r
+/* ------------------------------  SDMMC_CLOCK_CTRL  ------------------------------ */\r
+#define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Pos 0                                                      /*!< SDMMC CLOCK_CTRL: INTERNAL_CLOCK_EN Position */\r
+#define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Msk (0x01UL << SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Pos)     /*!< SDMMC CLOCK_CTRL: INTERNAL_CLOCK_EN Mask */\r
+#define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Pos 1                                                  /*!< SDMMC CLOCK_CTRL: INTERNAL_CLOCK_STABLE Position */\r
+#define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Msk (0x01UL << SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Pos)/*!< SDMMC CLOCK_CTRL: INTERNAL_CLOCK_STABLE Mask */\r
+#define SDMMC_CLOCK_CTRL_SDCLOCK_EN_Pos       2                                                       /*!< SDMMC CLOCK_CTRL: SDCLOCK_EN Position   */\r
+#define SDMMC_CLOCK_CTRL_SDCLOCK_EN_Msk       (0x01UL << SDMMC_CLOCK_CTRL_SDCLOCK_EN_Pos)             /*!< SDMMC CLOCK_CTRL: SDCLOCK_EN Mask       */\r
+#define SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos   8                                                       /*!< SDMMC CLOCK_CTRL: SDCLK_FREQ_SEL Position */\r
+#define SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Msk   (0x000000ffUL << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos)   /*!< SDMMC CLOCK_CTRL: SDCLK_FREQ_SEL Mask   */\r
+\r
+/* -----------------------------  SDMMC_TIMEOUT_CTRL  ----------------------------- */\r
+#define SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos 0                                                  /*!< SDMMC TIMEOUT_CTRL: DAT_TIMEOUT_CNT_VAL Position */\r
+#define SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Msk (0x0fUL << SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos)/*!< SDMMC TIMEOUT_CTRL: DAT_TIMEOUT_CNT_VAL Mask */\r
+\r
+/* -------------------------------  SDMMC_SW_RESET  ------------------------------- */\r
+#define SDMMC_SW_RESET_SW_RST_ALL_Pos         0                                                       /*!< SDMMC SW_RESET: SW_RST_ALL Position     */\r
+#define SDMMC_SW_RESET_SW_RST_ALL_Msk         (0x01UL << SDMMC_SW_RESET_SW_RST_ALL_Pos)               /*!< SDMMC SW_RESET: SW_RST_ALL Mask         */\r
+#define SDMMC_SW_RESET_SW_RST_CMD_LINE_Pos    1                                                       /*!< SDMMC SW_RESET: SW_RST_CMD_LINE Position */\r
+#define SDMMC_SW_RESET_SW_RST_CMD_LINE_Msk    (0x01UL << SDMMC_SW_RESET_SW_RST_CMD_LINE_Pos)          /*!< SDMMC SW_RESET: SW_RST_CMD_LINE Mask    */\r
+#define SDMMC_SW_RESET_SW_RST_DAT_LINE_Pos    2                                                       /*!< SDMMC SW_RESET: SW_RST_DAT_LINE Position */\r
+#define SDMMC_SW_RESET_SW_RST_DAT_LINE_Msk    (0x01UL << SDMMC_SW_RESET_SW_RST_DAT_LINE_Pos)          /*!< SDMMC SW_RESET: SW_RST_DAT_LINE Mask    */\r
+\r
+/* ----------------------------  SDMMC_INT_STATUS_NORM  --------------------------- */\r
+#define SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Pos 0                                                      /*!< SDMMC INT_STATUS_NORM: CMD_COMPLETE Position */\r
+#define SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Msk (0x01UL << SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Pos)     /*!< SDMMC INT_STATUS_NORM: CMD_COMPLETE Mask */\r
+#define SDMMC_INT_STATUS_NORM_TX_COMPLETE_Pos 1                                                       /*!< SDMMC INT_STATUS_NORM: TX_COMPLETE Position */\r
+#define SDMMC_INT_STATUS_NORM_TX_COMPLETE_Msk (0x01UL << SDMMC_INT_STATUS_NORM_TX_COMPLETE_Pos)       /*!< SDMMC INT_STATUS_NORM: TX_COMPLETE Mask */\r
+#define SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Pos 2                                                   /*!< SDMMC INT_STATUS_NORM: BLOCK_GAP_EVENT Position */\r
+#define SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Msk (0x01UL << SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Pos)/*!< SDMMC INT_STATUS_NORM: BLOCK_GAP_EVENT Mask */\r
+#define SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Pos 4                                                  /*!< SDMMC INT_STATUS_NORM: BUFF_WRITE_READY Position */\r
+#define SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Msk (0x01UL << SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Pos)/*!< SDMMC INT_STATUS_NORM: BUFF_WRITE_READY Mask */\r
+#define SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Pos 5                                                   /*!< SDMMC INT_STATUS_NORM: BUFF_READ_READY Position */\r
+#define SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Msk (0x01UL << SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Pos)/*!< SDMMC INT_STATUS_NORM: BUFF_READ_READY Mask */\r
+#define SDMMC_INT_STATUS_NORM_CARD_INS_Pos    6                                                       /*!< SDMMC INT_STATUS_NORM: CARD_INS Position */\r
+#define SDMMC_INT_STATUS_NORM_CARD_INS_Msk    (0x01UL << SDMMC_INT_STATUS_NORM_CARD_INS_Pos)          /*!< SDMMC INT_STATUS_NORM: CARD_INS Mask    */\r
+#define SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Pos 7                                                      /*!< SDMMC INT_STATUS_NORM: CARD_REMOVAL Position */\r
+#define SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Msk (0x01UL << SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Pos)     /*!< SDMMC INT_STATUS_NORM: CARD_REMOVAL Mask */\r
+#define SDMMC_INT_STATUS_NORM_CARD_INT_Pos    8                                                       /*!< SDMMC INT_STATUS_NORM: CARD_INT Position */\r
+#define SDMMC_INT_STATUS_NORM_CARD_INT_Msk    (0x01UL << SDMMC_INT_STATUS_NORM_CARD_INT_Pos)          /*!< SDMMC INT_STATUS_NORM: CARD_INT Mask    */\r
+#define SDMMC_INT_STATUS_NORM_ERR_INT_Pos     15                                                      /*!< SDMMC INT_STATUS_NORM: ERR_INT Position */\r
+#define SDMMC_INT_STATUS_NORM_ERR_INT_Msk     (0x01UL << SDMMC_INT_STATUS_NORM_ERR_INT_Pos)           /*!< SDMMC INT_STATUS_NORM: ERR_INT Mask     */\r
+\r
+/* ----------------------------  SDMMC_INT_STATUS_ERR  ---------------------------- */\r
+#define SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Pos 0                                                    /*!< SDMMC INT_STATUS_ERR: CMD_TIMEOUT_ERR Position */\r
+#define SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Msk (0x01UL << SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Pos) /*!< SDMMC INT_STATUS_ERR: CMD_TIMEOUT_ERR Mask */\r
+#define SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Pos  1                                                       /*!< SDMMC INT_STATUS_ERR: CMD_CRC_ERR Position */\r
+#define SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Msk  (0x01UL << SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Pos)        /*!< SDMMC INT_STATUS_ERR: CMD_CRC_ERR Mask  */\r
+#define SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Pos 2                                                    /*!< SDMMC INT_STATUS_ERR: CMD_END_BIT_ERR Position */\r
+#define SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Msk (0x01UL << SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Pos) /*!< SDMMC INT_STATUS_ERR: CMD_END_BIT_ERR Mask */\r
+#define SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Pos  3                                                       /*!< SDMMC INT_STATUS_ERR: CMD_IND_ERR Position */\r
+#define SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Msk  (0x01UL << SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Pos)        /*!< SDMMC INT_STATUS_ERR: CMD_IND_ERR Mask  */\r
+#define SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Pos 4                                                   /*!< SDMMC INT_STATUS_ERR: DATA_TIMEOUT_ERR Position */\r
+#define SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Msk (0x01UL << SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Pos)/*!< SDMMC INT_STATUS_ERR: DATA_TIMEOUT_ERR Mask */\r
+#define SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Pos 5                                                       /*!< SDMMC INT_STATUS_ERR: DATA_CRC_ERR Position */\r
+#define SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Msk (0x01UL << SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Pos)       /*!< SDMMC INT_STATUS_ERR: DATA_CRC_ERR Mask */\r
+#define SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Pos 6                                                   /*!< SDMMC INT_STATUS_ERR: DATA_END_BIT_ERR Position */\r
+#define SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Msk (0x01UL << SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Pos)/*!< SDMMC INT_STATUS_ERR: DATA_END_BIT_ERR Mask */\r
+#define SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Pos 7                                                  /*!< SDMMC INT_STATUS_ERR: CURRENT_LIMIT_ERR Position */\r
+#define SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Msk (0x01UL << SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Pos)/*!< SDMMC INT_STATUS_ERR: CURRENT_LIMIT_ERR Mask */\r
+#define SDMMC_INT_STATUS_ERR_ACMD_ERR_Pos     8                                                       /*!< SDMMC INT_STATUS_ERR: ACMD_ERR Position */\r
+#define SDMMC_INT_STATUS_ERR_ACMD_ERR_Msk     (0x01UL << SDMMC_INT_STATUS_ERR_ACMD_ERR_Pos)           /*!< SDMMC INT_STATUS_ERR: ACMD_ERR Mask     */\r
+#define SDMMC_INT_STATUS_ERR_CEATA_ERR_Pos    13                                                      /*!< SDMMC INT_STATUS_ERR: CEATA_ERR Position */\r
+#define SDMMC_INT_STATUS_ERR_CEATA_ERR_Msk    (0x01UL << SDMMC_INT_STATUS_ERR_CEATA_ERR_Pos)          /*!< SDMMC INT_STATUS_ERR: CEATA_ERR Mask    */\r
+\r
+/* --------------------------  SDMMC_EN_INT_STATUS_NORM  -------------------------- */\r
+#define SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Pos 0                                                /*!< SDMMC EN_INT_STATUS_NORM: CMD_COMPLETE_EN Position */\r
+#define SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Pos)/*!< SDMMC EN_INT_STATUS_NORM: CMD_COMPLETE_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Pos 1                                                 /*!< SDMMC EN_INT_STATUS_NORM: TX_COMPLETE_EN Position */\r
+#define SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Pos)/*!< SDMMC EN_INT_STATUS_NORM: TX_COMPLETE_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Pos 2                                             /*!< SDMMC EN_INT_STATUS_NORM: BLOCK_GAP_EVENT_EN Position */\r
+#define SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Pos)/*!< SDMMC EN_INT_STATUS_NORM: BLOCK_GAP_EVENT_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Pos 4                                            /*!< SDMMC EN_INT_STATUS_NORM: BUFF_WRITE_READY_EN Position */\r
+#define SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Pos)/*!< SDMMC EN_INT_STATUS_NORM: BUFF_WRITE_READY_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Pos 5                                             /*!< SDMMC EN_INT_STATUS_NORM: BUFF_READ_READY_EN Position */\r
+#define SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Pos)/*!< SDMMC EN_INT_STATUS_NORM: BUFF_READ_READY_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Pos 6                                                    /*!< SDMMC EN_INT_STATUS_NORM: CARD_INS_EN Position */\r
+#define SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Pos) /*!< SDMMC EN_INT_STATUS_NORM: CARD_INS_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Pos 7                                                /*!< SDMMC EN_INT_STATUS_NORM: CARD_REMOVAL_EN Position */\r
+#define SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Pos)/*!< SDMMC EN_INT_STATUS_NORM: CARD_REMOVAL_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Pos 8                                                    /*!< SDMMC EN_INT_STATUS_NORM: CARD_INT_EN Position */\r
+#define SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Pos) /*!< SDMMC EN_INT_STATUS_NORM: CARD_INT_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Pos 15                                                    /*!< SDMMC EN_INT_STATUS_NORM: FIXED_TO_0 Position */\r
+#define SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Msk (0x01UL << SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Pos)   /*!< SDMMC EN_INT_STATUS_NORM: FIXED_TO_0 Mask */\r
+\r
+/* ---------------------------  SDMMC_EN_INT_STATUS_ERR  -------------------------- */\r
+#define SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Pos 0                                              /*!< SDMMC EN_INT_STATUS_ERR: CMD_TIMEOUT_ERR_EN Position */\r
+#define SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Pos)/*!< SDMMC EN_INT_STATUS_ERR: CMD_TIMEOUT_ERR_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Pos 1                                                  /*!< SDMMC EN_INT_STATUS_ERR: CMD_CRC_ERR_EN Position */\r
+#define SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Pos)/*!< SDMMC EN_INT_STATUS_ERR: CMD_CRC_ERR_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Pos 2                                              /*!< SDMMC EN_INT_STATUS_ERR: CMD_END_BIT_ERR_EN Position */\r
+#define SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Pos)/*!< SDMMC EN_INT_STATUS_ERR: CMD_END_BIT_ERR_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Pos 3                                                  /*!< SDMMC EN_INT_STATUS_ERR: CMD_IND_ERR_EN Position */\r
+#define SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Pos)/*!< SDMMC EN_INT_STATUS_ERR: CMD_IND_ERR_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Pos 4                                             /*!< SDMMC EN_INT_STATUS_ERR: DATA_TIMEOUT_ERR_EN Position */\r
+#define SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Pos)/*!< SDMMC EN_INT_STATUS_ERR: DATA_TIMEOUT_ERR_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Pos 5                                                 /*!< SDMMC EN_INT_STATUS_ERR: DATA_CRC_ERR_EN Position */\r
+#define SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Pos)/*!< SDMMC EN_INT_STATUS_ERR: DATA_CRC_ERR_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Pos 6                                             /*!< SDMMC EN_INT_STATUS_ERR: DATA_END_BIT_ERR_EN Position */\r
+#define SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Pos)/*!< SDMMC EN_INT_STATUS_ERR: DATA_END_BIT_ERR_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Pos 7                                            /*!< SDMMC EN_INT_STATUS_ERR: CURRENT_LIMIT_ERR_EN Position */\r
+#define SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Pos)/*!< SDMMC EN_INT_STATUS_ERR: CURRENT_LIMIT_ERR_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Pos 8                                                     /*!< SDMMC EN_INT_STATUS_ERR: ACMD_ERR_EN Position */\r
+#define SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Pos)   /*!< SDMMC EN_INT_STATUS_ERR: ACMD_ERR_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Pos 12                                             /*!< SDMMC EN_INT_STATUS_ERR: TARGET_RESP_ERR_EN Position */\r
+#define SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Pos)/*!< SDMMC EN_INT_STATUS_ERR: TARGET_RESP_ERR_EN Mask */\r
+#define SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Pos 13                                                   /*!< SDMMC EN_INT_STATUS_ERR: CEATA_ERR_EN Position */\r
+#define SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Pos) /*!< SDMMC EN_INT_STATUS_ERR: CEATA_ERR_EN Mask */\r
+\r
+/* --------------------------  SDMMC_EN_INT_SIGNAL_NORM  -------------------------- */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Pos 0                                                /*!< SDMMC EN_INT_SIGNAL_NORM: CMD_COMPLETE_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_NORM: CMD_COMPLETE_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Pos 1                                                 /*!< SDMMC EN_INT_SIGNAL_NORM: TX_COMPLETE_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_NORM: TX_COMPLETE_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Pos 2                                             /*!< SDMMC EN_INT_SIGNAL_NORM: BLOCK_GAP_EVENT_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_NORM: BLOCK_GAP_EVENT_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Pos 4                                            /*!< SDMMC EN_INT_SIGNAL_NORM: BUFF_WRITE_READY_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_NORM: BUFF_WRITE_READY_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Pos 5                                             /*!< SDMMC EN_INT_SIGNAL_NORM: BUFF_READ_READY_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_NORM: BUFF_READ_READY_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Pos 6                                                    /*!< SDMMC EN_INT_SIGNAL_NORM: CARD_INS_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Pos) /*!< SDMMC EN_INT_SIGNAL_NORM: CARD_INS_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Pos 7                                                /*!< SDMMC EN_INT_SIGNAL_NORM: CARD_REMOVAL_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_NORM: CARD_REMOVAL_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Pos 8                                                    /*!< SDMMC EN_INT_SIGNAL_NORM: CARD_INT_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Pos) /*!< SDMMC EN_INT_SIGNAL_NORM: CARD_INT_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Pos 15                                                    /*!< SDMMC EN_INT_SIGNAL_NORM: FIXED_TO_0 Position */\r
+#define SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Pos)   /*!< SDMMC EN_INT_SIGNAL_NORM: FIXED_TO_0 Mask */\r
+\r
+/* ---------------------------  SDMMC_EN_INT_SIGNAL_ERR  -------------------------- */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Pos 0                                              /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_TIMEOUT_ERR_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_ERR: CMD_TIMEOUT_ERR_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Pos 1                                                  /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_CRC_ERR_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_ERR: CMD_CRC_ERR_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Pos 2                                              /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_END_BIT_ERR_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_ERR: CMD_END_BIT_ERR_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Pos 3                                                  /*!< SDMMC EN_INT_SIGNAL_ERR: CMD_IND_ERR_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_ERR: CMD_IND_ERR_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Pos 4                                             /*!< SDMMC EN_INT_SIGNAL_ERR: DATA_TIMEOUT_ERR_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_ERR: DATA_TIMEOUT_ERR_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Pos 5                                                 /*!< SDMMC EN_INT_SIGNAL_ERR: DATA_CRC_ERR_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_ERR: DATA_CRC_ERR_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Pos 6                                             /*!< SDMMC EN_INT_SIGNAL_ERR: DATA_END_BIT_ERR_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_ERR: DATA_END_BIT_ERR_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Pos 7                                            /*!< SDMMC EN_INT_SIGNAL_ERR: CURRENT_LIMIT_ERR_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_ERR: CURRENT_LIMIT_ERR_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Pos 8                                                     /*!< SDMMC EN_INT_SIGNAL_ERR: ACMD_ERR_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Pos)   /*!< SDMMC EN_INT_SIGNAL_ERR: ACMD_ERR_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Pos 12                                             /*!< SDMMC EN_INT_SIGNAL_ERR: TARGET_RESP_ERR_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Pos)/*!< SDMMC EN_INT_SIGNAL_ERR: TARGET_RESP_ERR_EN Mask */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Pos 13                                                   /*!< SDMMC EN_INT_SIGNAL_ERR: CEATA_ERR_EN Position */\r
+#define SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Msk (0x01UL << SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Pos) /*!< SDMMC EN_INT_SIGNAL_ERR: CEATA_ERR_EN Mask */\r
+\r
+/* ----------------------------  SDMMC_ACMD_ERR_STATUS  --------------------------- */\r
+#define SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Pos 0                                               /*!< SDMMC ACMD_ERR_STATUS: ACMD12_NOT_EXEC_ERR Position */\r
+#define SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Msk (0x01UL << SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Pos)/*!< SDMMC ACMD_ERR_STATUS: ACMD12_NOT_EXEC_ERR Mask */\r
+#define SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Pos 1                                                  /*!< SDMMC ACMD_ERR_STATUS: ACMD_TIMEOUT_ERR Position */\r
+#define SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Msk (0x01UL << SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Pos)/*!< SDMMC ACMD_ERR_STATUS: ACMD_TIMEOUT_ERR Mask */\r
+#define SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Pos 2                                                      /*!< SDMMC ACMD_ERR_STATUS: ACMD_CRC_ERR Position */\r
+#define SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Msk (0x01UL << SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Pos)     /*!< SDMMC ACMD_ERR_STATUS: ACMD_CRC_ERR Mask */\r
+#define SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Pos 3                                                  /*!< SDMMC ACMD_ERR_STATUS: ACMD_END_BIT_ERR Position */\r
+#define SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Msk (0x01UL << SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Pos)/*!< SDMMC ACMD_ERR_STATUS: ACMD_END_BIT_ERR Mask */\r
+#define SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Pos 4                                                      /*!< SDMMC ACMD_ERR_STATUS: ACMD_IND_ERR Position */\r
+#define SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Msk (0x01UL << SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Pos)     /*!< SDMMC ACMD_ERR_STATUS: ACMD_IND_ERR Mask */\r
+#define SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Pos 7                                      /*!< SDMMC ACMD_ERR_STATUS: CMD_NOT_ISSUED_BY_ACMD12_ERR Position */\r
+#define SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Msk (0x01UL << SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Pos)/*!< SDMMC ACMD_ERR_STATUS: CMD_NOT_ISSUED_BY_ACMD12_ERR Mask */\r
+\r
+/* ----------------------  SDMMC_FORCE_EVENT_ACMD_ERR_STATUS  --------------------- */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Pos 0                                      /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_NOT_EXEC Position */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Msk (0x01UL << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Pos)/*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_NOT_EXEC Mask */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Pos 1                                   /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_TIMEOUT_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Pos)/*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_TIMEOUT_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Pos 2                                       /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_CRC_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Pos)/*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_CRC_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Pos 3                                   /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_END_BIT_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Pos)/*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_END_BIT_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Pos 4                                       /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_IND_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Pos)/*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_ACMD_IND_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Pos 7                          /*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_CMD_NOT_ISSUED_ACMD12_ERR\r
+                                                         Position                                                                                  */\r
+#define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Pos)/*!< SDMMC FORCE_EVENT_ACMD_ERR_STATUS: FE_CMD_NOT_ISSUED_ACMD12_ERR\r
+                                                         Mask                                                                                      */\r
+\r
+/* ------------------------  SDMMC_FORCE_EVENT_ERR_STATUS  ------------------------ */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Pos 0                                         /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_TIMEOUT_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Pos)/*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_TIMEOUT_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Pos 1                                             /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_CRC_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Pos)/*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_CRC_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Pos 2                                         /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_END_BIT_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Pos)/*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_END_BIT_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Pos 3                                             /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_IND_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Pos)/*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CMD_IND_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Pos 4                                        /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_TIMEOUT_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Pos)/*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_TIMEOUT_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Pos 5                                            /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_CRC_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Pos)/*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_CRC_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Pos 6                                        /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_END_BIT_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Pos)/*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_DATA_END_BIT_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Pos 7                                       /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CURRENT_LIMIT_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Pos)/*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CURRENT_LIMIT_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Pos 8                                              /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_ACMD12_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Pos)/*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_ACMD12_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Pos 12                                    /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_TARGET_RESPONSE_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Pos)/*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_TARGET_RESPONSE_ERR Mask */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Pos 13                                              /*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CEATA_ERR Position */\r
+#define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Msk (0x01UL << SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Pos)/*!< SDMMC FORCE_EVENT_ERR_STATUS: FE_CEATA_ERR Mask */\r
+\r
+/* -------------------------------  SDMMC_DEBUG_SEL  ------------------------------ */\r
+#define SDMMC_DEBUG_SEL_DEBUG_SEL_Pos         0                                                       /*!< SDMMC DEBUG_SEL: DEBUG_SEL Position     */\r
+#define SDMMC_DEBUG_SEL_DEBUG_SEL_Msk         (0x01UL << SDMMC_DEBUG_SEL_DEBUG_SEL_Pos)               /*!< SDMMC DEBUG_SEL: DEBUG_SEL Mask         */\r
+\r
+/* ----------------------------------  SDMMC_SPI  --------------------------------- */\r
+#define SDMMC_SPI_SPI_INT_SUPPORT_Pos         0                                                       /*!< SDMMC SPI: SPI_INT_SUPPORT Position     */\r
+#define SDMMC_SPI_SPI_INT_SUPPORT_Msk         (0x000000ffUL << SDMMC_SPI_SPI_INT_SUPPORT_Pos)         /*!< SDMMC SPI: SPI_INT_SUPPORT Mask         */\r
+\r
+/* ----------------------------  SDMMC_SLOT_INT_STATUS  --------------------------- */\r
+#define SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Pos 0                                                   /*!< SDMMC SLOT_INT_STATUS: SLOT_INT_STATUS Position */\r
+#define SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Msk (0x000000ffUL << SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Pos)/*!< SDMMC SLOT_INT_STATUS: SLOT_INT_STATUS Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'EBU' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  EBU_CLC  ---------------------------------- */\r
+#define EBU_CLC_DISR_Pos                      0                                                       /*!< EBU CLC: DISR Position                  */\r
+#define EBU_CLC_DISR_Msk                      (0x01UL << EBU_CLC_DISR_Pos)                            /*!< EBU CLC: DISR Mask                      */\r
+#define EBU_CLC_DISS_Pos                      1                                                       /*!< EBU CLC: DISS Position                  */\r
+#define EBU_CLC_DISS_Msk                      (0x01UL << EBU_CLC_DISS_Pos)                            /*!< EBU CLC: DISS Mask                      */\r
+#define EBU_CLC_SYNC_Pos                      16                                                      /*!< EBU CLC: SYNC Position                  */\r
+#define EBU_CLC_SYNC_Msk                      (0x01UL << EBU_CLC_SYNC_Pos)                            /*!< EBU CLC: SYNC Mask                      */\r
+#define EBU_CLC_DIV2_Pos                      17                                                      /*!< EBU CLC: DIV2 Position                  */\r
+#define EBU_CLC_DIV2_Msk                      (0x01UL << EBU_CLC_DIV2_Pos)                            /*!< EBU CLC: DIV2 Mask                      */\r
+#define EBU_CLC_EBUDIV_Pos                    18                                                      /*!< EBU CLC: EBUDIV Position                */\r
+#define EBU_CLC_EBUDIV_Msk                    (0x03UL << EBU_CLC_EBUDIV_Pos)                          /*!< EBU CLC: EBUDIV Mask                    */\r
+#define EBU_CLC_SYNCACK_Pos                   20                                                      /*!< EBU CLC: SYNCACK Position               */\r
+#define EBU_CLC_SYNCACK_Msk                   (0x01UL << EBU_CLC_SYNCACK_Pos)                         /*!< EBU CLC: SYNCACK Mask                   */\r
+#define EBU_CLC_DIV2ACK_Pos                   21                                                      /*!< EBU CLC: DIV2ACK Position               */\r
+#define EBU_CLC_DIV2ACK_Msk                   (0x01UL << EBU_CLC_DIV2ACK_Pos)                         /*!< EBU CLC: DIV2ACK Mask                   */\r
+#define EBU_CLC_EBUDIVACK_Pos                 22                                                      /*!< EBU CLC: EBUDIVACK Position             */\r
+#define EBU_CLC_EBUDIVACK_Msk                 (0x03UL << EBU_CLC_EBUDIVACK_Pos)                       /*!< EBU CLC: EBUDIVACK Mask                 */\r
+\r
+/* ---------------------------------  EBU_MODCON  --------------------------------- */\r
+#define EBU_MODCON_STS_Pos                    0                                                       /*!< EBU MODCON: STS Position                */\r
+#define EBU_MODCON_STS_Msk                    (0x01UL << EBU_MODCON_STS_Pos)                          /*!< EBU MODCON: STS Mask                    */\r
+#define EBU_MODCON_LCKABRT_Pos                1                                                       /*!< EBU MODCON: LCKABRT Position            */\r
+#define EBU_MODCON_LCKABRT_Msk                (0x01UL << EBU_MODCON_LCKABRT_Pos)                      /*!< EBU MODCON: LCKABRT Mask                */\r
+#define EBU_MODCON_SDTRI_Pos                  2                                                       /*!< EBU MODCON: SDTRI Position              */\r
+#define EBU_MODCON_SDTRI_Msk                  (0x01UL << EBU_MODCON_SDTRI_Pos)                        /*!< EBU MODCON: SDTRI Mask                  */\r
+#define EBU_MODCON_EXTLOCK_Pos                4                                                       /*!< EBU MODCON: EXTLOCK Position            */\r
+#define EBU_MODCON_EXTLOCK_Msk                (0x01UL << EBU_MODCON_EXTLOCK_Pos)                      /*!< EBU MODCON: EXTLOCK Mask                */\r
+#define EBU_MODCON_ARBSYNC_Pos                5                                                       /*!< EBU MODCON: ARBSYNC Position            */\r
+#define EBU_MODCON_ARBSYNC_Msk                (0x01UL << EBU_MODCON_ARBSYNC_Pos)                      /*!< EBU MODCON: ARBSYNC Mask                */\r
+#define EBU_MODCON_ARBMODE_Pos                6                                                       /*!< EBU MODCON: ARBMODE Position            */\r
+#define EBU_MODCON_ARBMODE_Msk                (0x03UL << EBU_MODCON_ARBMODE_Pos)                      /*!< EBU MODCON: ARBMODE Mask                */\r
+#define EBU_MODCON_TIMEOUTC_Pos               8                                                       /*!< EBU MODCON: TIMEOUTC Position           */\r
+#define EBU_MODCON_TIMEOUTC_Msk               (0x000000ffUL << EBU_MODCON_TIMEOUTC_Pos)               /*!< EBU MODCON: TIMEOUTC Mask               */\r
+#define EBU_MODCON_LOCKTIMEOUT_Pos            16                                                      /*!< EBU MODCON: LOCKTIMEOUT Position        */\r
+#define EBU_MODCON_LOCKTIMEOUT_Msk            (0x000000ffUL << EBU_MODCON_LOCKTIMEOUT_Pos)            /*!< EBU MODCON: LOCKTIMEOUT Mask            */\r
+#define EBU_MODCON_GLOBALCS_Pos               24                                                      /*!< EBU MODCON: GLOBALCS Position           */\r
+#define EBU_MODCON_GLOBALCS_Msk               (0x0fUL << EBU_MODCON_GLOBALCS_Pos)                     /*!< EBU MODCON: GLOBALCS Mask               */\r
+#define EBU_MODCON_ACCSINH_Pos                28                                                      /*!< EBU MODCON: ACCSINH Position            */\r
+#define EBU_MODCON_ACCSINH_Msk                (0x01UL << EBU_MODCON_ACCSINH_Pos)                      /*!< EBU MODCON: ACCSINH Mask                */\r
+#define EBU_MODCON_ACCSINHACK_Pos             29                                                      /*!< EBU MODCON: ACCSINHACK Position         */\r
+#define EBU_MODCON_ACCSINHACK_Msk             (0x01UL << EBU_MODCON_ACCSINHACK_Pos)                   /*!< EBU MODCON: ACCSINHACK Mask             */\r
+#define EBU_MODCON_ALE_Pos                    31                                                      /*!< EBU MODCON: ALE Position                */\r
+#define EBU_MODCON_ALE_Msk                    (0x01UL << EBU_MODCON_ALE_Pos)                          /*!< EBU MODCON: ALE Mask                    */\r
+\r
+/* -----------------------------------  EBU_ID  ----------------------------------- */\r
+#define EBU_ID_MOD_REV_Pos                    0                                                       /*!< EBU ID: MOD_REV Position                */\r
+#define EBU_ID_MOD_REV_Msk                    (0x000000ffUL << EBU_ID_MOD_REV_Pos)                    /*!< EBU ID: MOD_REV Mask                    */\r
+#define EBU_ID_MOD_TYPE_Pos                   8                                                       /*!< EBU ID: MOD_TYPE Position               */\r
+#define EBU_ID_MOD_TYPE_Msk                   (0x000000ffUL << EBU_ID_MOD_TYPE_Pos)                   /*!< EBU ID: MOD_TYPE Mask                   */\r
+#define EBU_ID_MOD_NUMBER_Pos                 16                                                      /*!< EBU ID: MOD_NUMBER Position             */\r
+#define EBU_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << EBU_ID_MOD_NUMBER_Pos)                 /*!< EBU ID: MOD_NUMBER Mask                 */\r
+\r
+/* ---------------------------------  EBU_USERCON  -------------------------------- */\r
+#define EBU_USERCON_DIP_Pos                   0                                                       /*!< EBU USERCON: DIP Position               */\r
+#define EBU_USERCON_DIP_Msk                   (0x01UL << EBU_USERCON_DIP_Pos)                         /*!< EBU USERCON: DIP Mask                   */\r
+#define EBU_USERCON_ADDIO_Pos                 16                                                      /*!< EBU USERCON: ADDIO Position             */\r
+#define EBU_USERCON_ADDIO_Msk                 (0x000001ffUL << EBU_USERCON_ADDIO_Pos)                 /*!< EBU USERCON: ADDIO Mask                 */\r
+#define EBU_USERCON_ADVIO_Pos                 25                                                      /*!< EBU USERCON: ADVIO Position             */\r
+#define EBU_USERCON_ADVIO_Msk                 (0x01UL << EBU_USERCON_ADVIO_Pos)                       /*!< EBU USERCON: ADVIO Mask                 */\r
+\r
+/* --------------------------------  EBU_ADDRSEL0  -------------------------------- */\r
+#define EBU_ADDRSEL0_REGENAB_Pos              0                                                       /*!< EBU ADDRSEL0: REGENAB Position          */\r
+#define EBU_ADDRSEL0_REGENAB_Msk              (0x01UL << EBU_ADDRSEL0_REGENAB_Pos)                    /*!< EBU ADDRSEL0: REGENAB Mask              */\r
+#define EBU_ADDRSEL0_ALTENAB_Pos              1                                                       /*!< EBU ADDRSEL0: ALTENAB Position          */\r
+#define EBU_ADDRSEL0_ALTENAB_Msk              (0x01UL << EBU_ADDRSEL0_ALTENAB_Pos)                    /*!< EBU ADDRSEL0: ALTENAB Mask              */\r
+#define EBU_ADDRSEL0_WPROT_Pos                2                                                       /*!< EBU ADDRSEL0: WPROT Position            */\r
+#define EBU_ADDRSEL0_WPROT_Msk                (0x01UL << EBU_ADDRSEL0_WPROT_Pos)                      /*!< EBU ADDRSEL0: WPROT Mask                */\r
+\r
+/* --------------------------------  EBU_ADDRSEL1  -------------------------------- */\r
+#define EBU_ADDRSEL1_REGENAB_Pos              0                                                       /*!< EBU ADDRSEL1: REGENAB Position          */\r
+#define EBU_ADDRSEL1_REGENAB_Msk              (0x01UL << EBU_ADDRSEL1_REGENAB_Pos)                    /*!< EBU ADDRSEL1: REGENAB Mask              */\r
+#define EBU_ADDRSEL1_ALTENAB_Pos              1                                                       /*!< EBU ADDRSEL1: ALTENAB Position          */\r
+#define EBU_ADDRSEL1_ALTENAB_Msk              (0x01UL << EBU_ADDRSEL1_ALTENAB_Pos)                    /*!< EBU ADDRSEL1: ALTENAB Mask              */\r
+#define EBU_ADDRSEL1_WPROT_Pos                2                                                       /*!< EBU ADDRSEL1: WPROT Position            */\r
+#define EBU_ADDRSEL1_WPROT_Msk                (0x01UL << EBU_ADDRSEL1_WPROT_Pos)                      /*!< EBU ADDRSEL1: WPROT Mask                */\r
+\r
+/* --------------------------------  EBU_ADDRSEL2  -------------------------------- */\r
+#define EBU_ADDRSEL2_REGENAB_Pos              0                                                       /*!< EBU ADDRSEL2: REGENAB Position          */\r
+#define EBU_ADDRSEL2_REGENAB_Msk              (0x01UL << EBU_ADDRSEL2_REGENAB_Pos)                    /*!< EBU ADDRSEL2: REGENAB Mask              */\r
+#define EBU_ADDRSEL2_ALTENAB_Pos              1                                                       /*!< EBU ADDRSEL2: ALTENAB Position          */\r
+#define EBU_ADDRSEL2_ALTENAB_Msk              (0x01UL << EBU_ADDRSEL2_ALTENAB_Pos)                    /*!< EBU ADDRSEL2: ALTENAB Mask              */\r
+#define EBU_ADDRSEL2_WPROT_Pos                2                                                       /*!< EBU ADDRSEL2: WPROT Position            */\r
+#define EBU_ADDRSEL2_WPROT_Msk                (0x01UL << EBU_ADDRSEL2_WPROT_Pos)                      /*!< EBU ADDRSEL2: WPROT Mask                */\r
+\r
+/* --------------------------------  EBU_ADDRSEL3  -------------------------------- */\r
+#define EBU_ADDRSEL3_REGENAB_Pos              0                                                       /*!< EBU ADDRSEL3: REGENAB Position          */\r
+#define EBU_ADDRSEL3_REGENAB_Msk              (0x01UL << EBU_ADDRSEL3_REGENAB_Pos)                    /*!< EBU ADDRSEL3: REGENAB Mask              */\r
+#define EBU_ADDRSEL3_ALTENAB_Pos              1                                                       /*!< EBU ADDRSEL3: ALTENAB Position          */\r
+#define EBU_ADDRSEL3_ALTENAB_Msk              (0x01UL << EBU_ADDRSEL3_ALTENAB_Pos)                    /*!< EBU ADDRSEL3: ALTENAB Mask              */\r
+#define EBU_ADDRSEL3_WPROT_Pos                2                                                       /*!< EBU ADDRSEL3: WPROT Position            */\r
+#define EBU_ADDRSEL3_WPROT_Msk                (0x01UL << EBU_ADDRSEL3_WPROT_Pos)                      /*!< EBU ADDRSEL3: WPROT Mask                */\r
+\r
+/* --------------------------------  EBU_BUSRCON0  -------------------------------- */\r
+#define EBU_BUSRCON0_FETBLEN_Pos              0                                                       /*!< EBU BUSRCON0: FETBLEN Position          */\r
+#define EBU_BUSRCON0_FETBLEN_Msk              (0x07UL << EBU_BUSRCON0_FETBLEN_Pos)                    /*!< EBU BUSRCON0: FETBLEN Mask              */\r
+#define EBU_BUSRCON0_FBBMSEL_Pos              3                                                       /*!< EBU BUSRCON0: FBBMSEL Position          */\r
+#define EBU_BUSRCON0_FBBMSEL_Msk              (0x01UL << EBU_BUSRCON0_FBBMSEL_Pos)                    /*!< EBU BUSRCON0: FBBMSEL Mask              */\r
+#define EBU_BUSRCON0_BFSSS_Pos                4                                                       /*!< EBU BUSRCON0: BFSSS Position            */\r
+#define EBU_BUSRCON0_BFSSS_Msk                (0x01UL << EBU_BUSRCON0_BFSSS_Pos)                      /*!< EBU BUSRCON0: BFSSS Mask                */\r
+#define EBU_BUSRCON0_FDBKEN_Pos               5                                                       /*!< EBU BUSRCON0: FDBKEN Position           */\r
+#define EBU_BUSRCON0_FDBKEN_Msk               (0x01UL << EBU_BUSRCON0_FDBKEN_Pos)                     /*!< EBU BUSRCON0: FDBKEN Mask               */\r
+#define EBU_BUSRCON0_BFCMSEL_Pos              6                                                       /*!< EBU BUSRCON0: BFCMSEL Position          */\r
+#define EBU_BUSRCON0_BFCMSEL_Msk              (0x01UL << EBU_BUSRCON0_BFCMSEL_Pos)                    /*!< EBU BUSRCON0: BFCMSEL Mask              */\r
+#define EBU_BUSRCON0_NAA_Pos                  7                                                       /*!< EBU BUSRCON0: NAA Position              */\r
+#define EBU_BUSRCON0_NAA_Msk                  (0x01UL << EBU_BUSRCON0_NAA_Pos)                        /*!< EBU BUSRCON0: NAA Mask                  */\r
+#define EBU_BUSRCON0_ECSE_Pos                 16                                                      /*!< EBU BUSRCON0: ECSE Position             */\r
+#define EBU_BUSRCON0_ECSE_Msk                 (0x01UL << EBU_BUSRCON0_ECSE_Pos)                       /*!< EBU BUSRCON0: ECSE Mask                 */\r
+#define EBU_BUSRCON0_EBSE_Pos                 17                                                      /*!< EBU BUSRCON0: EBSE Position             */\r
+#define EBU_BUSRCON0_EBSE_Msk                 (0x01UL << EBU_BUSRCON0_EBSE_Pos)                       /*!< EBU BUSRCON0: EBSE Mask                 */\r
+#define EBU_BUSRCON0_DBA_Pos                  18                                                      /*!< EBU BUSRCON0: DBA Position              */\r
+#define EBU_BUSRCON0_DBA_Msk                  (0x01UL << EBU_BUSRCON0_DBA_Pos)                        /*!< EBU BUSRCON0: DBA Mask                  */\r
+#define EBU_BUSRCON0_WAITINV_Pos              19                                                      /*!< EBU BUSRCON0: WAITINV Position          */\r
+#define EBU_BUSRCON0_WAITINV_Msk              (0x01UL << EBU_BUSRCON0_WAITINV_Pos)                    /*!< EBU BUSRCON0: WAITINV Mask              */\r
+#define EBU_BUSRCON0_BCGEN_Pos                20                                                      /*!< EBU BUSRCON0: BCGEN Position            */\r
+#define EBU_BUSRCON0_BCGEN_Msk                (0x03UL << EBU_BUSRCON0_BCGEN_Pos)                      /*!< EBU BUSRCON0: BCGEN Mask                */\r
+#define EBU_BUSRCON0_PORTW_Pos                22                                                      /*!< EBU BUSRCON0: PORTW Position            */\r
+#define EBU_BUSRCON0_PORTW_Msk                (0x03UL << EBU_BUSRCON0_PORTW_Pos)                      /*!< EBU BUSRCON0: PORTW Mask                */\r
+#define EBU_BUSRCON0_WAIT_Pos                 24                                                      /*!< EBU BUSRCON0: WAIT Position             */\r
+#define EBU_BUSRCON0_WAIT_Msk                 (0x03UL << EBU_BUSRCON0_WAIT_Pos)                       /*!< EBU BUSRCON0: WAIT Mask                 */\r
+#define EBU_BUSRCON0_AAP_Pos                  26                                                      /*!< EBU BUSRCON0: AAP Position              */\r
+#define EBU_BUSRCON0_AAP_Msk                  (0x01UL << EBU_BUSRCON0_AAP_Pos)                        /*!< EBU BUSRCON0: AAP Mask                  */\r
+#define EBU_BUSRCON0_AGEN_Pos                 28                                                      /*!< EBU BUSRCON0: AGEN Position             */\r
+#define EBU_BUSRCON0_AGEN_Msk                 (0x0fUL << EBU_BUSRCON0_AGEN_Pos)                       /*!< EBU BUSRCON0: AGEN Mask                 */\r
+\r
+/* ---------------------------------  EBU_BUSRAP0  -------------------------------- */\r
+#define EBU_BUSRAP0_RDDTACS_Pos               0                                                       /*!< EBU BUSRAP0: RDDTACS Position           */\r
+#define EBU_BUSRAP0_RDDTACS_Msk               (0x0fUL << EBU_BUSRAP0_RDDTACS_Pos)                     /*!< EBU BUSRAP0: RDDTACS Mask               */\r
+#define EBU_BUSRAP0_RDRECOVC_Pos              4                                                       /*!< EBU BUSRAP0: RDRECOVC Position          */\r
+#define EBU_BUSRAP0_RDRECOVC_Msk              (0x07UL << EBU_BUSRAP0_RDRECOVC_Pos)                    /*!< EBU BUSRAP0: RDRECOVC Mask              */\r
+#define EBU_BUSRAP0_WAITRDC_Pos               7                                                       /*!< EBU BUSRAP0: WAITRDC Position           */\r
+#define EBU_BUSRAP0_WAITRDC_Msk               (0x1fUL << EBU_BUSRAP0_WAITRDC_Pos)                     /*!< EBU BUSRAP0: WAITRDC Mask               */\r
+#define EBU_BUSRAP0_DATAC_Pos                 12                                                      /*!< EBU BUSRAP0: DATAC Position             */\r
+#define EBU_BUSRAP0_DATAC_Msk                 (0x0fUL << EBU_BUSRAP0_DATAC_Pos)                       /*!< EBU BUSRAP0: DATAC Mask                 */\r
+#define EBU_BUSRAP0_EXTCLOCK_Pos              16                                                      /*!< EBU BUSRAP0: EXTCLOCK Position          */\r
+#define EBU_BUSRAP0_EXTCLOCK_Msk              (0x03UL << EBU_BUSRAP0_EXTCLOCK_Pos)                    /*!< EBU BUSRAP0: EXTCLOCK Mask              */\r
+#define EBU_BUSRAP0_EXTDATA_Pos               18                                                      /*!< EBU BUSRAP0: EXTDATA Position           */\r
+#define EBU_BUSRAP0_EXTDATA_Msk               (0x03UL << EBU_BUSRAP0_EXTDATA_Pos)                     /*!< EBU BUSRAP0: EXTDATA Mask               */\r
+#define EBU_BUSRAP0_CMDDELAY_Pos              20                                                      /*!< EBU BUSRAP0: CMDDELAY Position          */\r
+#define EBU_BUSRAP0_CMDDELAY_Msk              (0x0fUL << EBU_BUSRAP0_CMDDELAY_Pos)                    /*!< EBU BUSRAP0: CMDDELAY Mask              */\r
+#define EBU_BUSRAP0_AHOLDC_Pos                24                                                      /*!< EBU BUSRAP0: AHOLDC Position            */\r
+#define EBU_BUSRAP0_AHOLDC_Msk                (0x0fUL << EBU_BUSRAP0_AHOLDC_Pos)                      /*!< EBU BUSRAP0: AHOLDC Mask                */\r
+#define EBU_BUSRAP0_ADDRC_Pos                 28                                                      /*!< EBU BUSRAP0: ADDRC Position             */\r
+#define EBU_BUSRAP0_ADDRC_Msk                 (0x0fUL << EBU_BUSRAP0_ADDRC_Pos)                       /*!< EBU BUSRAP0: ADDRC Mask                 */\r
+\r
+/* --------------------------------  EBU_BUSWCON0  -------------------------------- */\r
+#define EBU_BUSWCON0_FETBLEN_Pos              0                                                       /*!< EBU BUSWCON0: FETBLEN Position          */\r
+#define EBU_BUSWCON0_FETBLEN_Msk              (0x07UL << EBU_BUSWCON0_FETBLEN_Pos)                    /*!< EBU BUSWCON0: FETBLEN Mask              */\r
+#define EBU_BUSWCON0_FBBMSEL_Pos              3                                                       /*!< EBU BUSWCON0: FBBMSEL Position          */\r
+#define EBU_BUSWCON0_FBBMSEL_Msk              (0x01UL << EBU_BUSWCON0_FBBMSEL_Pos)                    /*!< EBU BUSWCON0: FBBMSEL Mask              */\r
+#define EBU_BUSWCON0_NAA_Pos                  7                                                       /*!< EBU BUSWCON0: NAA Position              */\r
+#define EBU_BUSWCON0_NAA_Msk                  (0x01UL << EBU_BUSWCON0_NAA_Pos)                        /*!< EBU BUSWCON0: NAA Mask                  */\r
+#define EBU_BUSWCON0_ECSE_Pos                 16                                                      /*!< EBU BUSWCON0: ECSE Position             */\r
+#define EBU_BUSWCON0_ECSE_Msk                 (0x01UL << EBU_BUSWCON0_ECSE_Pos)                       /*!< EBU BUSWCON0: ECSE Mask                 */\r
+#define EBU_BUSWCON0_EBSE_Pos                 17                                                      /*!< EBU BUSWCON0: EBSE Position             */\r
+#define EBU_BUSWCON0_EBSE_Msk                 (0x01UL << EBU_BUSWCON0_EBSE_Pos)                       /*!< EBU BUSWCON0: EBSE Mask                 */\r
+#define EBU_BUSWCON0_WAITINV_Pos              19                                                      /*!< EBU BUSWCON0: WAITINV Position          */\r
+#define EBU_BUSWCON0_WAITINV_Msk              (0x01UL << EBU_BUSWCON0_WAITINV_Pos)                    /*!< EBU BUSWCON0: WAITINV Mask              */\r
+#define EBU_BUSWCON0_BCGEN_Pos                20                                                      /*!< EBU BUSWCON0: BCGEN Position            */\r
+#define EBU_BUSWCON0_BCGEN_Msk                (0x03UL << EBU_BUSWCON0_BCGEN_Pos)                      /*!< EBU BUSWCON0: BCGEN Mask                */\r
+#define EBU_BUSWCON0_PORTW_Pos                22                                                      /*!< EBU BUSWCON0: PORTW Position            */\r
+#define EBU_BUSWCON0_PORTW_Msk                (0x03UL << EBU_BUSWCON0_PORTW_Pos)                      /*!< EBU BUSWCON0: PORTW Mask                */\r
+#define EBU_BUSWCON0_WAIT_Pos                 24                                                      /*!< EBU BUSWCON0: WAIT Position             */\r
+#define EBU_BUSWCON0_WAIT_Msk                 (0x03UL << EBU_BUSWCON0_WAIT_Pos)                       /*!< EBU BUSWCON0: WAIT Mask                 */\r
+#define EBU_BUSWCON0_AAP_Pos                  26                                                      /*!< EBU BUSWCON0: AAP Position              */\r
+#define EBU_BUSWCON0_AAP_Msk                  (0x01UL << EBU_BUSWCON0_AAP_Pos)                        /*!< EBU BUSWCON0: AAP Mask                  */\r
+#define EBU_BUSWCON0_LOCKCS_Pos               27                                                      /*!< EBU BUSWCON0: LOCKCS Position           */\r
+#define EBU_BUSWCON0_LOCKCS_Msk               (0x01UL << EBU_BUSWCON0_LOCKCS_Pos)                     /*!< EBU BUSWCON0: LOCKCS Mask               */\r
+#define EBU_BUSWCON0_AGEN_Pos                 28                                                      /*!< EBU BUSWCON0: AGEN Position             */\r
+#define EBU_BUSWCON0_AGEN_Msk                 (0x0fUL << EBU_BUSWCON0_AGEN_Pos)                       /*!< EBU BUSWCON0: AGEN Mask                 */\r
+\r
+/* ---------------------------------  EBU_BUSWAP0  -------------------------------- */\r
+#define EBU_BUSWAP0_WRDTACS_Pos               0                                                       /*!< EBU BUSWAP0: WRDTACS Position           */\r
+#define EBU_BUSWAP0_WRDTACS_Msk               (0x0fUL << EBU_BUSWAP0_WRDTACS_Pos)                     /*!< EBU BUSWAP0: WRDTACS Mask               */\r
+#define EBU_BUSWAP0_WRRECOVC_Pos              4                                                       /*!< EBU BUSWAP0: WRRECOVC Position          */\r
+#define EBU_BUSWAP0_WRRECOVC_Msk              (0x07UL << EBU_BUSWAP0_WRRECOVC_Pos)                    /*!< EBU BUSWAP0: WRRECOVC Mask              */\r
+#define EBU_BUSWAP0_WAITWRC_Pos               7                                                       /*!< EBU BUSWAP0: WAITWRC Position           */\r
+#define EBU_BUSWAP0_WAITWRC_Msk               (0x1fUL << EBU_BUSWAP0_WAITWRC_Pos)                     /*!< EBU BUSWAP0: WAITWRC Mask               */\r
+#define EBU_BUSWAP0_DATAC_Pos                 12                                                      /*!< EBU BUSWAP0: DATAC Position             */\r
+#define EBU_BUSWAP0_DATAC_Msk                 (0x0fUL << EBU_BUSWAP0_DATAC_Pos)                       /*!< EBU BUSWAP0: DATAC Mask                 */\r
+#define EBU_BUSWAP0_EXTCLOCK_Pos              16                                                      /*!< EBU BUSWAP0: EXTCLOCK Position          */\r
+#define EBU_BUSWAP0_EXTCLOCK_Msk              (0x03UL << EBU_BUSWAP0_EXTCLOCK_Pos)                    /*!< EBU BUSWAP0: EXTCLOCK Mask              */\r
+#define EBU_BUSWAP0_EXTDATA_Pos               18                                                      /*!< EBU BUSWAP0: EXTDATA Position           */\r
+#define EBU_BUSWAP0_EXTDATA_Msk               (0x03UL << EBU_BUSWAP0_EXTDATA_Pos)                     /*!< EBU BUSWAP0: EXTDATA Mask               */\r
+#define EBU_BUSWAP0_CMDDELAY_Pos              20                                                      /*!< EBU BUSWAP0: CMDDELAY Position          */\r
+#define EBU_BUSWAP0_CMDDELAY_Msk              (0x0fUL << EBU_BUSWAP0_CMDDELAY_Pos)                    /*!< EBU BUSWAP0: CMDDELAY Mask              */\r
+#define EBU_BUSWAP0_AHOLDC_Pos                24                                                      /*!< EBU BUSWAP0: AHOLDC Position            */\r
+#define EBU_BUSWAP0_AHOLDC_Msk                (0x0fUL << EBU_BUSWAP0_AHOLDC_Pos)                      /*!< EBU BUSWAP0: AHOLDC Mask                */\r
+#define EBU_BUSWAP0_ADDRC_Pos                 28                                                      /*!< EBU BUSWAP0: ADDRC Position             */\r
+#define EBU_BUSWAP0_ADDRC_Msk                 (0x0fUL << EBU_BUSWAP0_ADDRC_Pos)                       /*!< EBU BUSWAP0: ADDRC Mask                 */\r
+\r
+/* --------------------------------  EBU_BUSRCON1  -------------------------------- */\r
+#define EBU_BUSRCON1_FETBLEN_Pos              0                                                       /*!< EBU BUSRCON1: FETBLEN Position          */\r
+#define EBU_BUSRCON1_FETBLEN_Msk              (0x07UL << EBU_BUSRCON1_FETBLEN_Pos)                    /*!< EBU BUSRCON1: FETBLEN Mask              */\r
+#define EBU_BUSRCON1_FBBMSEL_Pos              3                                                       /*!< EBU BUSRCON1: FBBMSEL Position          */\r
+#define EBU_BUSRCON1_FBBMSEL_Msk              (0x01UL << EBU_BUSRCON1_FBBMSEL_Pos)                    /*!< EBU BUSRCON1: FBBMSEL Mask              */\r
+#define EBU_BUSRCON1_BFSSS_Pos                4                                                       /*!< EBU BUSRCON1: BFSSS Position            */\r
+#define EBU_BUSRCON1_BFSSS_Msk                (0x01UL << EBU_BUSRCON1_BFSSS_Pos)                      /*!< EBU BUSRCON1: BFSSS Mask                */\r
+#define EBU_BUSRCON1_FDBKEN_Pos               5                                                       /*!< EBU BUSRCON1: FDBKEN Position           */\r
+#define EBU_BUSRCON1_FDBKEN_Msk               (0x01UL << EBU_BUSRCON1_FDBKEN_Pos)                     /*!< EBU BUSRCON1: FDBKEN Mask               */\r
+#define EBU_BUSRCON1_BFCMSEL_Pos              6                                                       /*!< EBU BUSRCON1: BFCMSEL Position          */\r
+#define EBU_BUSRCON1_BFCMSEL_Msk              (0x01UL << EBU_BUSRCON1_BFCMSEL_Pos)                    /*!< EBU BUSRCON1: BFCMSEL Mask              */\r
+#define EBU_BUSRCON1_NAA_Pos                  7                                                       /*!< EBU BUSRCON1: NAA Position              */\r
+#define EBU_BUSRCON1_NAA_Msk                  (0x01UL << EBU_BUSRCON1_NAA_Pos)                        /*!< EBU BUSRCON1: NAA Mask                  */\r
+#define EBU_BUSRCON1_ECSE_Pos                 16                                                      /*!< EBU BUSRCON1: ECSE Position             */\r
+#define EBU_BUSRCON1_ECSE_Msk                 (0x01UL << EBU_BUSRCON1_ECSE_Pos)                       /*!< EBU BUSRCON1: ECSE Mask                 */\r
+#define EBU_BUSRCON1_EBSE_Pos                 17                                                      /*!< EBU BUSRCON1: EBSE Position             */\r
+#define EBU_BUSRCON1_EBSE_Msk                 (0x01UL << EBU_BUSRCON1_EBSE_Pos)                       /*!< EBU BUSRCON1: EBSE Mask                 */\r
+#define EBU_BUSRCON1_DBA_Pos                  18                                                      /*!< EBU BUSRCON1: DBA Position              */\r
+#define EBU_BUSRCON1_DBA_Msk                  (0x01UL << EBU_BUSRCON1_DBA_Pos)                        /*!< EBU BUSRCON1: DBA Mask                  */\r
+#define EBU_BUSRCON1_WAITINV_Pos              19                                                      /*!< EBU BUSRCON1: WAITINV Position          */\r
+#define EBU_BUSRCON1_WAITINV_Msk              (0x01UL << EBU_BUSRCON1_WAITINV_Pos)                    /*!< EBU BUSRCON1: WAITINV Mask              */\r
+#define EBU_BUSRCON1_BCGEN_Pos                20                                                      /*!< EBU BUSRCON1: BCGEN Position            */\r
+#define EBU_BUSRCON1_BCGEN_Msk                (0x03UL << EBU_BUSRCON1_BCGEN_Pos)                      /*!< EBU BUSRCON1: BCGEN Mask                */\r
+#define EBU_BUSRCON1_PORTW_Pos                22                                                      /*!< EBU BUSRCON1: PORTW Position            */\r
+#define EBU_BUSRCON1_PORTW_Msk                (0x03UL << EBU_BUSRCON1_PORTW_Pos)                      /*!< EBU BUSRCON1: PORTW Mask                */\r
+#define EBU_BUSRCON1_WAIT_Pos                 24                                                      /*!< EBU BUSRCON1: WAIT Position             */\r
+#define EBU_BUSRCON1_WAIT_Msk                 (0x03UL << EBU_BUSRCON1_WAIT_Pos)                       /*!< EBU BUSRCON1: WAIT Mask                 */\r
+#define EBU_BUSRCON1_AAP_Pos                  26                                                      /*!< EBU BUSRCON1: AAP Position              */\r
+#define EBU_BUSRCON1_AAP_Msk                  (0x01UL << EBU_BUSRCON1_AAP_Pos)                        /*!< EBU BUSRCON1: AAP Mask                  */\r
+#define EBU_BUSRCON1_AGEN_Pos                 28                                                      /*!< EBU BUSRCON1: AGEN Position             */\r
+#define EBU_BUSRCON1_AGEN_Msk                 (0x0fUL << EBU_BUSRCON1_AGEN_Pos)                       /*!< EBU BUSRCON1: AGEN Mask                 */\r
+\r
+/* ---------------------------------  EBU_BUSRAP1  -------------------------------- */\r
+#define EBU_BUSRAP1_RDDTACS_Pos               0                                                       /*!< EBU BUSRAP1: RDDTACS Position           */\r
+#define EBU_BUSRAP1_RDDTACS_Msk               (0x0fUL << EBU_BUSRAP1_RDDTACS_Pos)                     /*!< EBU BUSRAP1: RDDTACS Mask               */\r
+#define EBU_BUSRAP1_RDRECOVC_Pos              4                                                       /*!< EBU BUSRAP1: RDRECOVC Position          */\r
+#define EBU_BUSRAP1_RDRECOVC_Msk              (0x07UL << EBU_BUSRAP1_RDRECOVC_Pos)                    /*!< EBU BUSRAP1: RDRECOVC Mask              */\r
+#define EBU_BUSRAP1_WAITRDC_Pos               7                                                       /*!< EBU BUSRAP1: WAITRDC Position           */\r
+#define EBU_BUSRAP1_WAITRDC_Msk               (0x1fUL << EBU_BUSRAP1_WAITRDC_Pos)                     /*!< EBU BUSRAP1: WAITRDC Mask               */\r
+#define EBU_BUSRAP1_DATAC_Pos                 12                                                      /*!< EBU BUSRAP1: DATAC Position             */\r
+#define EBU_BUSRAP1_DATAC_Msk                 (0x0fUL << EBU_BUSRAP1_DATAC_Pos)                       /*!< EBU BUSRAP1: DATAC Mask                 */\r
+#define EBU_BUSRAP1_EXTCLOCK_Pos              16                                                      /*!< EBU BUSRAP1: EXTCLOCK Position          */\r
+#define EBU_BUSRAP1_EXTCLOCK_Msk              (0x03UL << EBU_BUSRAP1_EXTCLOCK_Pos)                    /*!< EBU BUSRAP1: EXTCLOCK Mask              */\r
+#define EBU_BUSRAP1_EXTDATA_Pos               18                                                      /*!< EBU BUSRAP1: EXTDATA Position           */\r
+#define EBU_BUSRAP1_EXTDATA_Msk               (0x03UL << EBU_BUSRAP1_EXTDATA_Pos)                     /*!< EBU BUSRAP1: EXTDATA Mask               */\r
+#define EBU_BUSRAP1_CMDDELAY_Pos              20                                                      /*!< EBU BUSRAP1: CMDDELAY Position          */\r
+#define EBU_BUSRAP1_CMDDELAY_Msk              (0x0fUL << EBU_BUSRAP1_CMDDELAY_Pos)                    /*!< EBU BUSRAP1: CMDDELAY Mask              */\r
+#define EBU_BUSRAP1_AHOLDC_Pos                24                                                      /*!< EBU BUSRAP1: AHOLDC Position            */\r
+#define EBU_BUSRAP1_AHOLDC_Msk                (0x0fUL << EBU_BUSRAP1_AHOLDC_Pos)                      /*!< EBU BUSRAP1: AHOLDC Mask                */\r
+#define EBU_BUSRAP1_ADDRC_Pos                 28                                                      /*!< EBU BUSRAP1: ADDRC Position             */\r
+#define EBU_BUSRAP1_ADDRC_Msk                 (0x0fUL << EBU_BUSRAP1_ADDRC_Pos)                       /*!< EBU BUSRAP1: ADDRC Mask                 */\r
+\r
+/* --------------------------------  EBU_BUSWCON1  -------------------------------- */\r
+#define EBU_BUSWCON1_FETBLEN_Pos              0                                                       /*!< EBU BUSWCON1: FETBLEN Position          */\r
+#define EBU_BUSWCON1_FETBLEN_Msk              (0x07UL << EBU_BUSWCON1_FETBLEN_Pos)                    /*!< EBU BUSWCON1: FETBLEN Mask              */\r
+#define EBU_BUSWCON1_FBBMSEL_Pos              3                                                       /*!< EBU BUSWCON1: FBBMSEL Position          */\r
+#define EBU_BUSWCON1_FBBMSEL_Msk              (0x01UL << EBU_BUSWCON1_FBBMSEL_Pos)                    /*!< EBU BUSWCON1: FBBMSEL Mask              */\r
+#define EBU_BUSWCON1_NAA_Pos                  7                                                       /*!< EBU BUSWCON1: NAA Position              */\r
+#define EBU_BUSWCON1_NAA_Msk                  (0x01UL << EBU_BUSWCON1_NAA_Pos)                        /*!< EBU BUSWCON1: NAA Mask                  */\r
+#define EBU_BUSWCON1_ECSE_Pos                 16                                                      /*!< EBU BUSWCON1: ECSE Position             */\r
+#define EBU_BUSWCON1_ECSE_Msk                 (0x01UL << EBU_BUSWCON1_ECSE_Pos)                       /*!< EBU BUSWCON1: ECSE Mask                 */\r
+#define EBU_BUSWCON1_EBSE_Pos                 17                                                      /*!< EBU BUSWCON1: EBSE Position             */\r
+#define EBU_BUSWCON1_EBSE_Msk                 (0x01UL << EBU_BUSWCON1_EBSE_Pos)                       /*!< EBU BUSWCON1: EBSE Mask                 */\r
+#define EBU_BUSWCON1_WAITINV_Pos              19                                                      /*!< EBU BUSWCON1: WAITINV Position          */\r
+#define EBU_BUSWCON1_WAITINV_Msk              (0x01UL << EBU_BUSWCON1_WAITINV_Pos)                    /*!< EBU BUSWCON1: WAITINV Mask              */\r
+#define EBU_BUSWCON1_BCGEN_Pos                20                                                      /*!< EBU BUSWCON1: BCGEN Position            */\r
+#define EBU_BUSWCON1_BCGEN_Msk                (0x03UL << EBU_BUSWCON1_BCGEN_Pos)                      /*!< EBU BUSWCON1: BCGEN Mask                */\r
+#define EBU_BUSWCON1_PORTW_Pos                22                                                      /*!< EBU BUSWCON1: PORTW Position            */\r
+#define EBU_BUSWCON1_PORTW_Msk                (0x03UL << EBU_BUSWCON1_PORTW_Pos)                      /*!< EBU BUSWCON1: PORTW Mask                */\r
+#define EBU_BUSWCON1_WAIT_Pos                 24                                                      /*!< EBU BUSWCON1: WAIT Position             */\r
+#define EBU_BUSWCON1_WAIT_Msk                 (0x03UL << EBU_BUSWCON1_WAIT_Pos)                       /*!< EBU BUSWCON1: WAIT Mask                 */\r
+#define EBU_BUSWCON1_AAP_Pos                  26                                                      /*!< EBU BUSWCON1: AAP Position              */\r
+#define EBU_BUSWCON1_AAP_Msk                  (0x01UL << EBU_BUSWCON1_AAP_Pos)                        /*!< EBU BUSWCON1: AAP Mask                  */\r
+#define EBU_BUSWCON1_LOCKCS_Pos               27                                                      /*!< EBU BUSWCON1: LOCKCS Position           */\r
+#define EBU_BUSWCON1_LOCKCS_Msk               (0x01UL << EBU_BUSWCON1_LOCKCS_Pos)                     /*!< EBU BUSWCON1: LOCKCS Mask               */\r
+#define EBU_BUSWCON1_AGEN_Pos                 28                                                      /*!< EBU BUSWCON1: AGEN Position             */\r
+#define EBU_BUSWCON1_AGEN_Msk                 (0x0fUL << EBU_BUSWCON1_AGEN_Pos)                       /*!< EBU BUSWCON1: AGEN Mask                 */\r
+\r
+/* ---------------------------------  EBU_BUSWAP1  -------------------------------- */\r
+#define EBU_BUSWAP1_WRDTACS_Pos               0                                                       /*!< EBU BUSWAP1: WRDTACS Position           */\r
+#define EBU_BUSWAP1_WRDTACS_Msk               (0x0fUL << EBU_BUSWAP1_WRDTACS_Pos)                     /*!< EBU BUSWAP1: WRDTACS Mask               */\r
+#define EBU_BUSWAP1_WRRECOVC_Pos              4                                                       /*!< EBU BUSWAP1: WRRECOVC Position          */\r
+#define EBU_BUSWAP1_WRRECOVC_Msk              (0x07UL << EBU_BUSWAP1_WRRECOVC_Pos)                    /*!< EBU BUSWAP1: WRRECOVC Mask              */\r
+#define EBU_BUSWAP1_WAITWRC_Pos               7                                                       /*!< EBU BUSWAP1: WAITWRC Position           */\r
+#define EBU_BUSWAP1_WAITWRC_Msk               (0x1fUL << EBU_BUSWAP1_WAITWRC_Pos)                     /*!< EBU BUSWAP1: WAITWRC Mask               */\r
+#define EBU_BUSWAP1_DATAC_Pos                 12                                                      /*!< EBU BUSWAP1: DATAC Position             */\r
+#define EBU_BUSWAP1_DATAC_Msk                 (0x0fUL << EBU_BUSWAP1_DATAC_Pos)                       /*!< EBU BUSWAP1: DATAC Mask                 */\r
+#define EBU_BUSWAP1_EXTCLOCK_Pos              16                                                      /*!< EBU BUSWAP1: EXTCLOCK Position          */\r
+#define EBU_BUSWAP1_EXTCLOCK_Msk              (0x03UL << EBU_BUSWAP1_EXTCLOCK_Pos)                    /*!< EBU BUSWAP1: EXTCLOCK Mask              */\r
+#define EBU_BUSWAP1_EXTDATA_Pos               18                                                      /*!< EBU BUSWAP1: EXTDATA Position           */\r
+#define EBU_BUSWAP1_EXTDATA_Msk               (0x03UL << EBU_BUSWAP1_EXTDATA_Pos)                     /*!< EBU BUSWAP1: EXTDATA Mask               */\r
+#define EBU_BUSWAP1_CMDDELAY_Pos              20                                                      /*!< EBU BUSWAP1: CMDDELAY Position          */\r
+#define EBU_BUSWAP1_CMDDELAY_Msk              (0x0fUL << EBU_BUSWAP1_CMDDELAY_Pos)                    /*!< EBU BUSWAP1: CMDDELAY Mask              */\r
+#define EBU_BUSWAP1_AHOLDC_Pos                24                                                      /*!< EBU BUSWAP1: AHOLDC Position            */\r
+#define EBU_BUSWAP1_AHOLDC_Msk                (0x0fUL << EBU_BUSWAP1_AHOLDC_Pos)                      /*!< EBU BUSWAP1: AHOLDC Mask                */\r
+#define EBU_BUSWAP1_ADDRC_Pos                 28                                                      /*!< EBU BUSWAP1: ADDRC Position             */\r
+#define EBU_BUSWAP1_ADDRC_Msk                 (0x0fUL << EBU_BUSWAP1_ADDRC_Pos)                       /*!< EBU BUSWAP1: ADDRC Mask                 */\r
+\r
+/* --------------------------------  EBU_BUSRCON2  -------------------------------- */\r
+#define EBU_BUSRCON2_FETBLEN_Pos              0                                                       /*!< EBU BUSRCON2: FETBLEN Position          */\r
+#define EBU_BUSRCON2_FETBLEN_Msk              (0x07UL << EBU_BUSRCON2_FETBLEN_Pos)                    /*!< EBU BUSRCON2: FETBLEN Mask              */\r
+#define EBU_BUSRCON2_FBBMSEL_Pos              3                                                       /*!< EBU BUSRCON2: FBBMSEL Position          */\r
+#define EBU_BUSRCON2_FBBMSEL_Msk              (0x01UL << EBU_BUSRCON2_FBBMSEL_Pos)                    /*!< EBU BUSRCON2: FBBMSEL Mask              */\r
+#define EBU_BUSRCON2_BFSSS_Pos                4                                                       /*!< EBU BUSRCON2: BFSSS Position            */\r
+#define EBU_BUSRCON2_BFSSS_Msk                (0x01UL << EBU_BUSRCON2_BFSSS_Pos)                      /*!< EBU BUSRCON2: BFSSS Mask                */\r
+#define EBU_BUSRCON2_FDBKEN_Pos               5                                                       /*!< EBU BUSRCON2: FDBKEN Position           */\r
+#define EBU_BUSRCON2_FDBKEN_Msk               (0x01UL << EBU_BUSRCON2_FDBKEN_Pos)                     /*!< EBU BUSRCON2: FDBKEN Mask               */\r
+#define EBU_BUSRCON2_BFCMSEL_Pos              6                                                       /*!< EBU BUSRCON2: BFCMSEL Position          */\r
+#define EBU_BUSRCON2_BFCMSEL_Msk              (0x01UL << EBU_BUSRCON2_BFCMSEL_Pos)                    /*!< EBU BUSRCON2: BFCMSEL Mask              */\r
+#define EBU_BUSRCON2_NAA_Pos                  7                                                       /*!< EBU BUSRCON2: NAA Position              */\r
+#define EBU_BUSRCON2_NAA_Msk                  (0x01UL << EBU_BUSRCON2_NAA_Pos)                        /*!< EBU BUSRCON2: NAA Mask                  */\r
+#define EBU_BUSRCON2_ECSE_Pos                 16                                                      /*!< EBU BUSRCON2: ECSE Position             */\r
+#define EBU_BUSRCON2_ECSE_Msk                 (0x01UL << EBU_BUSRCON2_ECSE_Pos)                       /*!< EBU BUSRCON2: ECSE Mask                 */\r
+#define EBU_BUSRCON2_EBSE_Pos                 17                                                      /*!< EBU BUSRCON2: EBSE Position             */\r
+#define EBU_BUSRCON2_EBSE_Msk                 (0x01UL << EBU_BUSRCON2_EBSE_Pos)                       /*!< EBU BUSRCON2: EBSE Mask                 */\r
+#define EBU_BUSRCON2_DBA_Pos                  18                                                      /*!< EBU BUSRCON2: DBA Position              */\r
+#define EBU_BUSRCON2_DBA_Msk                  (0x01UL << EBU_BUSRCON2_DBA_Pos)                        /*!< EBU BUSRCON2: DBA Mask                  */\r
+#define EBU_BUSRCON2_WAITINV_Pos              19                                                      /*!< EBU BUSRCON2: WAITINV Position          */\r
+#define EBU_BUSRCON2_WAITINV_Msk              (0x01UL << EBU_BUSRCON2_WAITINV_Pos)                    /*!< EBU BUSRCON2: WAITINV Mask              */\r
+#define EBU_BUSRCON2_BCGEN_Pos                20                                                      /*!< EBU BUSRCON2: BCGEN Position            */\r
+#define EBU_BUSRCON2_BCGEN_Msk                (0x03UL << EBU_BUSRCON2_BCGEN_Pos)                      /*!< EBU BUSRCON2: BCGEN Mask                */\r
+#define EBU_BUSRCON2_PORTW_Pos                22                                                      /*!< EBU BUSRCON2: PORTW Position            */\r
+#define EBU_BUSRCON2_PORTW_Msk                (0x03UL << EBU_BUSRCON2_PORTW_Pos)                      /*!< EBU BUSRCON2: PORTW Mask                */\r
+#define EBU_BUSRCON2_WAIT_Pos                 24                                                      /*!< EBU BUSRCON2: WAIT Position             */\r
+#define EBU_BUSRCON2_WAIT_Msk                 (0x03UL << EBU_BUSRCON2_WAIT_Pos)                       /*!< EBU BUSRCON2: WAIT Mask                 */\r
+#define EBU_BUSRCON2_AAP_Pos                  26                                                      /*!< EBU BUSRCON2: AAP Position              */\r
+#define EBU_BUSRCON2_AAP_Msk                  (0x01UL << EBU_BUSRCON2_AAP_Pos)                        /*!< EBU BUSRCON2: AAP Mask                  */\r
+#define EBU_BUSRCON2_AGEN_Pos                 28                                                      /*!< EBU BUSRCON2: AGEN Position             */\r
+#define EBU_BUSRCON2_AGEN_Msk                 (0x0fUL << EBU_BUSRCON2_AGEN_Pos)                       /*!< EBU BUSRCON2: AGEN Mask                 */\r
+\r
+/* ---------------------------------  EBU_BUSRAP2  -------------------------------- */\r
+#define EBU_BUSRAP2_RDDTACS_Pos               0                                                       /*!< EBU BUSRAP2: RDDTACS Position           */\r
+#define EBU_BUSRAP2_RDDTACS_Msk               (0x0fUL << EBU_BUSRAP2_RDDTACS_Pos)                     /*!< EBU BUSRAP2: RDDTACS Mask               */\r
+#define EBU_BUSRAP2_RDRECOVC_Pos              4                                                       /*!< EBU BUSRAP2: RDRECOVC Position          */\r
+#define EBU_BUSRAP2_RDRECOVC_Msk              (0x07UL << EBU_BUSRAP2_RDRECOVC_Pos)                    /*!< EBU BUSRAP2: RDRECOVC Mask              */\r
+#define EBU_BUSRAP2_WAITRDC_Pos               7                                                       /*!< EBU BUSRAP2: WAITRDC Position           */\r
+#define EBU_BUSRAP2_WAITRDC_Msk               (0x1fUL << EBU_BUSRAP2_WAITRDC_Pos)                     /*!< EBU BUSRAP2: WAITRDC Mask               */\r
+#define EBU_BUSRAP2_DATAC_Pos                 12                                                      /*!< EBU BUSRAP2: DATAC Position             */\r
+#define EBU_BUSRAP2_DATAC_Msk                 (0x0fUL << EBU_BUSRAP2_DATAC_Pos)                       /*!< EBU BUSRAP2: DATAC Mask                 */\r
+#define EBU_BUSRAP2_EXTCLOCK_Pos              16                                                      /*!< EBU BUSRAP2: EXTCLOCK Position          */\r
+#define EBU_BUSRAP2_EXTCLOCK_Msk              (0x03UL << EBU_BUSRAP2_EXTCLOCK_Pos)                    /*!< EBU BUSRAP2: EXTCLOCK Mask              */\r
+#define EBU_BUSRAP2_EXTDATA_Pos               18                                                      /*!< EBU BUSRAP2: EXTDATA Position           */\r
+#define EBU_BUSRAP2_EXTDATA_Msk               (0x03UL << EBU_BUSRAP2_EXTDATA_Pos)                     /*!< EBU BUSRAP2: EXTDATA Mask               */\r
+#define EBU_BUSRAP2_CMDDELAY_Pos              20                                                      /*!< EBU BUSRAP2: CMDDELAY Position          */\r
+#define EBU_BUSRAP2_CMDDELAY_Msk              (0x0fUL << EBU_BUSRAP2_CMDDELAY_Pos)                    /*!< EBU BUSRAP2: CMDDELAY Mask              */\r
+#define EBU_BUSRAP2_AHOLDC_Pos                24                                                      /*!< EBU BUSRAP2: AHOLDC Position            */\r
+#define EBU_BUSRAP2_AHOLDC_Msk                (0x0fUL << EBU_BUSRAP2_AHOLDC_Pos)                      /*!< EBU BUSRAP2: AHOLDC Mask                */\r
+#define EBU_BUSRAP2_ADDRC_Pos                 28                                                      /*!< EBU BUSRAP2: ADDRC Position             */\r
+#define EBU_BUSRAP2_ADDRC_Msk                 (0x0fUL << EBU_BUSRAP2_ADDRC_Pos)                       /*!< EBU BUSRAP2: ADDRC Mask                 */\r
+\r
+/* --------------------------------  EBU_BUSWCON2  -------------------------------- */\r
+#define EBU_BUSWCON2_FETBLEN_Pos              0                                                       /*!< EBU BUSWCON2: FETBLEN Position          */\r
+#define EBU_BUSWCON2_FETBLEN_Msk              (0x07UL << EBU_BUSWCON2_FETBLEN_Pos)                    /*!< EBU BUSWCON2: FETBLEN Mask              */\r
+#define EBU_BUSWCON2_FBBMSEL_Pos              3                                                       /*!< EBU BUSWCON2: FBBMSEL Position          */\r
+#define EBU_BUSWCON2_FBBMSEL_Msk              (0x01UL << EBU_BUSWCON2_FBBMSEL_Pos)                    /*!< EBU BUSWCON2: FBBMSEL Mask              */\r
+#define EBU_BUSWCON2_NAA_Pos                  7                                                       /*!< EBU BUSWCON2: NAA Position              */\r
+#define EBU_BUSWCON2_NAA_Msk                  (0x01UL << EBU_BUSWCON2_NAA_Pos)                        /*!< EBU BUSWCON2: NAA Mask                  */\r
+#define EBU_BUSWCON2_ECSE_Pos                 16                                                      /*!< EBU BUSWCON2: ECSE Position             */\r
+#define EBU_BUSWCON2_ECSE_Msk                 (0x01UL << EBU_BUSWCON2_ECSE_Pos)                       /*!< EBU BUSWCON2: ECSE Mask                 */\r
+#define EBU_BUSWCON2_EBSE_Pos                 17                                                      /*!< EBU BUSWCON2: EBSE Position             */\r
+#define EBU_BUSWCON2_EBSE_Msk                 (0x01UL << EBU_BUSWCON2_EBSE_Pos)                       /*!< EBU BUSWCON2: EBSE Mask                 */\r
+#define EBU_BUSWCON2_WAITINV_Pos              19                                                      /*!< EBU BUSWCON2: WAITINV Position          */\r
+#define EBU_BUSWCON2_WAITINV_Msk              (0x01UL << EBU_BUSWCON2_WAITINV_Pos)                    /*!< EBU BUSWCON2: WAITINV Mask              */\r
+#define EBU_BUSWCON2_BCGEN_Pos                20                                                      /*!< EBU BUSWCON2: BCGEN Position            */\r
+#define EBU_BUSWCON2_BCGEN_Msk                (0x03UL << EBU_BUSWCON2_BCGEN_Pos)                      /*!< EBU BUSWCON2: BCGEN Mask                */\r
+#define EBU_BUSWCON2_PORTW_Pos                22                                                      /*!< EBU BUSWCON2: PORTW Position            */\r
+#define EBU_BUSWCON2_PORTW_Msk                (0x03UL << EBU_BUSWCON2_PORTW_Pos)                      /*!< EBU BUSWCON2: PORTW Mask                */\r
+#define EBU_BUSWCON2_WAIT_Pos                 24                                                      /*!< EBU BUSWCON2: WAIT Position             */\r
+#define EBU_BUSWCON2_WAIT_Msk                 (0x03UL << EBU_BUSWCON2_WAIT_Pos)                       /*!< EBU BUSWCON2: WAIT Mask                 */\r
+#define EBU_BUSWCON2_AAP_Pos                  26                                                      /*!< EBU BUSWCON2: AAP Position              */\r
+#define EBU_BUSWCON2_AAP_Msk                  (0x01UL << EBU_BUSWCON2_AAP_Pos)                        /*!< EBU BUSWCON2: AAP Mask                  */\r
+#define EBU_BUSWCON2_LOCKCS_Pos               27                                                      /*!< EBU BUSWCON2: LOCKCS Position           */\r
+#define EBU_BUSWCON2_LOCKCS_Msk               (0x01UL << EBU_BUSWCON2_LOCKCS_Pos)                     /*!< EBU BUSWCON2: LOCKCS Mask               */\r
+#define EBU_BUSWCON2_AGEN_Pos                 28                                                      /*!< EBU BUSWCON2: AGEN Position             */\r
+#define EBU_BUSWCON2_AGEN_Msk                 (0x0fUL << EBU_BUSWCON2_AGEN_Pos)                       /*!< EBU BUSWCON2: AGEN Mask                 */\r
+\r
+/* ---------------------------------  EBU_BUSWAP2  -------------------------------- */\r
+#define EBU_BUSWAP2_WRDTACS_Pos               0                                                       /*!< EBU BUSWAP2: WRDTACS Position           */\r
+#define EBU_BUSWAP2_WRDTACS_Msk               (0x0fUL << EBU_BUSWAP2_WRDTACS_Pos)                     /*!< EBU BUSWAP2: WRDTACS Mask               */\r
+#define EBU_BUSWAP2_WRRECOVC_Pos              4                                                       /*!< EBU BUSWAP2: WRRECOVC Position          */\r
+#define EBU_BUSWAP2_WRRECOVC_Msk              (0x07UL << EBU_BUSWAP2_WRRECOVC_Pos)                    /*!< EBU BUSWAP2: WRRECOVC Mask              */\r
+#define EBU_BUSWAP2_WAITWRC_Pos               7                                                       /*!< EBU BUSWAP2: WAITWRC Position           */\r
+#define EBU_BUSWAP2_WAITWRC_Msk               (0x1fUL << EBU_BUSWAP2_WAITWRC_Pos)                     /*!< EBU BUSWAP2: WAITWRC Mask               */\r
+#define EBU_BUSWAP2_DATAC_Pos                 12                                                      /*!< EBU BUSWAP2: DATAC Position             */\r
+#define EBU_BUSWAP2_DATAC_Msk                 (0x0fUL << EBU_BUSWAP2_DATAC_Pos)                       /*!< EBU BUSWAP2: DATAC Mask                 */\r
+#define EBU_BUSWAP2_EXTCLOCK_Pos              16                                                      /*!< EBU BUSWAP2: EXTCLOCK Position          */\r
+#define EBU_BUSWAP2_EXTCLOCK_Msk              (0x03UL << EBU_BUSWAP2_EXTCLOCK_Pos)                    /*!< EBU BUSWAP2: EXTCLOCK Mask              */\r
+#define EBU_BUSWAP2_EXTDATA_Pos               18                                                      /*!< EBU BUSWAP2: EXTDATA Position           */\r
+#define EBU_BUSWAP2_EXTDATA_Msk               (0x03UL << EBU_BUSWAP2_EXTDATA_Pos)                     /*!< EBU BUSWAP2: EXTDATA Mask               */\r
+#define EBU_BUSWAP2_CMDDELAY_Pos              20                                                      /*!< EBU BUSWAP2: CMDDELAY Position          */\r
+#define EBU_BUSWAP2_CMDDELAY_Msk              (0x0fUL << EBU_BUSWAP2_CMDDELAY_Pos)                    /*!< EBU BUSWAP2: CMDDELAY Mask              */\r
+#define EBU_BUSWAP2_AHOLDC_Pos                24                                                      /*!< EBU BUSWAP2: AHOLDC Position            */\r
+#define EBU_BUSWAP2_AHOLDC_Msk                (0x0fUL << EBU_BUSWAP2_AHOLDC_Pos)                      /*!< EBU BUSWAP2: AHOLDC Mask                */\r
+#define EBU_BUSWAP2_ADDRC_Pos                 28                                                      /*!< EBU BUSWAP2: ADDRC Position             */\r
+#define EBU_BUSWAP2_ADDRC_Msk                 (0x0fUL << EBU_BUSWAP2_ADDRC_Pos)                       /*!< EBU BUSWAP2: ADDRC Mask                 */\r
+\r
+/* --------------------------------  EBU_BUSRCON3  -------------------------------- */\r
+#define EBU_BUSRCON3_FETBLEN_Pos              0                                                       /*!< EBU BUSRCON3: FETBLEN Position          */\r
+#define EBU_BUSRCON3_FETBLEN_Msk              (0x07UL << EBU_BUSRCON3_FETBLEN_Pos)                    /*!< EBU BUSRCON3: FETBLEN Mask              */\r
+#define EBU_BUSRCON3_FBBMSEL_Pos              3                                                       /*!< EBU BUSRCON3: FBBMSEL Position          */\r
+#define EBU_BUSRCON3_FBBMSEL_Msk              (0x01UL << EBU_BUSRCON3_FBBMSEL_Pos)                    /*!< EBU BUSRCON3: FBBMSEL Mask              */\r
+#define EBU_BUSRCON3_BFSSS_Pos                4                                                       /*!< EBU BUSRCON3: BFSSS Position            */\r
+#define EBU_BUSRCON3_BFSSS_Msk                (0x01UL << EBU_BUSRCON3_BFSSS_Pos)                      /*!< EBU BUSRCON3: BFSSS Mask                */\r
+#define EBU_BUSRCON3_FDBKEN_Pos               5                                                       /*!< EBU BUSRCON3: FDBKEN Position           */\r
+#define EBU_BUSRCON3_FDBKEN_Msk               (0x01UL << EBU_BUSRCON3_FDBKEN_Pos)                     /*!< EBU BUSRCON3: FDBKEN Mask               */\r
+#define EBU_BUSRCON3_BFCMSEL_Pos              6                                                       /*!< EBU BUSRCON3: BFCMSEL Position          */\r
+#define EBU_BUSRCON3_BFCMSEL_Msk              (0x01UL << EBU_BUSRCON3_BFCMSEL_Pos)                    /*!< EBU BUSRCON3: BFCMSEL Mask              */\r
+#define EBU_BUSRCON3_NAA_Pos                  7                                                       /*!< EBU BUSRCON3: NAA Position              */\r
+#define EBU_BUSRCON3_NAA_Msk                  (0x01UL << EBU_BUSRCON3_NAA_Pos)                        /*!< EBU BUSRCON3: NAA Mask                  */\r
+#define EBU_BUSRCON3_ECSE_Pos                 16                                                      /*!< EBU BUSRCON3: ECSE Position             */\r
+#define EBU_BUSRCON3_ECSE_Msk                 (0x01UL << EBU_BUSRCON3_ECSE_Pos)                       /*!< EBU BUSRCON3: ECSE Mask                 */\r
+#define EBU_BUSRCON3_EBSE_Pos                 17                                                      /*!< EBU BUSRCON3: EBSE Position             */\r
+#define EBU_BUSRCON3_EBSE_Msk                 (0x01UL << EBU_BUSRCON3_EBSE_Pos)                       /*!< EBU BUSRCON3: EBSE Mask                 */\r
+#define EBU_BUSRCON3_DBA_Pos                  18                                                      /*!< EBU BUSRCON3: DBA Position              */\r
+#define EBU_BUSRCON3_DBA_Msk                  (0x01UL << EBU_BUSRCON3_DBA_Pos)                        /*!< EBU BUSRCON3: DBA Mask                  */\r
+#define EBU_BUSRCON3_WAITINV_Pos              19                                                      /*!< EBU BUSRCON3: WAITINV Position          */\r
+#define EBU_BUSRCON3_WAITINV_Msk              (0x01UL << EBU_BUSRCON3_WAITINV_Pos)                    /*!< EBU BUSRCON3: WAITINV Mask              */\r
+#define EBU_BUSRCON3_BCGEN_Pos                20                                                      /*!< EBU BUSRCON3: BCGEN Position            */\r
+#define EBU_BUSRCON3_BCGEN_Msk                (0x03UL << EBU_BUSRCON3_BCGEN_Pos)                      /*!< EBU BUSRCON3: BCGEN Mask                */\r
+#define EBU_BUSRCON3_PORTW_Pos                22                                                      /*!< EBU BUSRCON3: PORTW Position            */\r
+#define EBU_BUSRCON3_PORTW_Msk                (0x03UL << EBU_BUSRCON3_PORTW_Pos)                      /*!< EBU BUSRCON3: PORTW Mask                */\r
+#define EBU_BUSRCON3_WAIT_Pos                 24                                                      /*!< EBU BUSRCON3: WAIT Position             */\r
+#define EBU_BUSRCON3_WAIT_Msk                 (0x03UL << EBU_BUSRCON3_WAIT_Pos)                       /*!< EBU BUSRCON3: WAIT Mask                 */\r
+#define EBU_BUSRCON3_AAP_Pos                  26                                                      /*!< EBU BUSRCON3: AAP Position              */\r
+#define EBU_BUSRCON3_AAP_Msk                  (0x01UL << EBU_BUSRCON3_AAP_Pos)                        /*!< EBU BUSRCON3: AAP Mask                  */\r
+#define EBU_BUSRCON3_AGEN_Pos                 28                                                      /*!< EBU BUSRCON3: AGEN Position             */\r
+#define EBU_BUSRCON3_AGEN_Msk                 (0x0fUL << EBU_BUSRCON3_AGEN_Pos)                       /*!< EBU BUSRCON3: AGEN Mask                 */\r
+\r
+/* ---------------------------------  EBU_BUSRAP3  -------------------------------- */\r
+#define EBU_BUSRAP3_RDDTACS_Pos               0                                                       /*!< EBU BUSRAP3: RDDTACS Position           */\r
+#define EBU_BUSRAP3_RDDTACS_Msk               (0x0fUL << EBU_BUSRAP3_RDDTACS_Pos)                     /*!< EBU BUSRAP3: RDDTACS Mask               */\r
+#define EBU_BUSRAP3_RDRECOVC_Pos              4                                                       /*!< EBU BUSRAP3: RDRECOVC Position          */\r
+#define EBU_BUSRAP3_RDRECOVC_Msk              (0x07UL << EBU_BUSRAP3_RDRECOVC_Pos)                    /*!< EBU BUSRAP3: RDRECOVC Mask              */\r
+#define EBU_BUSRAP3_WAITRDC_Pos               7                                                       /*!< EBU BUSRAP3: WAITRDC Position           */\r
+#define EBU_BUSRAP3_WAITRDC_Msk               (0x1fUL << EBU_BUSRAP3_WAITRDC_Pos)                     /*!< EBU BUSRAP3: WAITRDC Mask               */\r
+#define EBU_BUSRAP3_DATAC_Pos                 12                                                      /*!< EBU BUSRAP3: DATAC Position             */\r
+#define EBU_BUSRAP3_DATAC_Msk                 (0x0fUL << EBU_BUSRAP3_DATAC_Pos)                       /*!< EBU BUSRAP3: DATAC Mask                 */\r
+#define EBU_BUSRAP3_EXTCLOCK_Pos              16                                                      /*!< EBU BUSRAP3: EXTCLOCK Position          */\r
+#define EBU_BUSRAP3_EXTCLOCK_Msk              (0x03UL << EBU_BUSRAP3_EXTCLOCK_Pos)                    /*!< EBU BUSRAP3: EXTCLOCK Mask              */\r
+#define EBU_BUSRAP3_EXTDATA_Pos               18                                                      /*!< EBU BUSRAP3: EXTDATA Position           */\r
+#define EBU_BUSRAP3_EXTDATA_Msk               (0x03UL << EBU_BUSRAP3_EXTDATA_Pos)                     /*!< EBU BUSRAP3: EXTDATA Mask               */\r
+#define EBU_BUSRAP3_CMDDELAY_Pos              20                                                      /*!< EBU BUSRAP3: CMDDELAY Position          */\r
+#define EBU_BUSRAP3_CMDDELAY_Msk              (0x0fUL << EBU_BUSRAP3_CMDDELAY_Pos)                    /*!< EBU BUSRAP3: CMDDELAY Mask              */\r
+#define EBU_BUSRAP3_AHOLDC_Pos                24                                                      /*!< EBU BUSRAP3: AHOLDC Position            */\r
+#define EBU_BUSRAP3_AHOLDC_Msk                (0x0fUL << EBU_BUSRAP3_AHOLDC_Pos)                      /*!< EBU BUSRAP3: AHOLDC Mask                */\r
+#define EBU_BUSRAP3_ADDRC_Pos                 28                                                      /*!< EBU BUSRAP3: ADDRC Position             */\r
+#define EBU_BUSRAP3_ADDRC_Msk                 (0x0fUL << EBU_BUSRAP3_ADDRC_Pos)                       /*!< EBU BUSRAP3: ADDRC Mask                 */\r
+\r
+/* --------------------------------  EBU_BUSWCON3  -------------------------------- */\r
+#define EBU_BUSWCON3_FETBLEN_Pos              0                                                       /*!< EBU BUSWCON3: FETBLEN Position          */\r
+#define EBU_BUSWCON3_FETBLEN_Msk              (0x07UL << EBU_BUSWCON3_FETBLEN_Pos)                    /*!< EBU BUSWCON3: FETBLEN Mask              */\r
+#define EBU_BUSWCON3_FBBMSEL_Pos              3                                                       /*!< EBU BUSWCON3: FBBMSEL Position          */\r
+#define EBU_BUSWCON3_FBBMSEL_Msk              (0x01UL << EBU_BUSWCON3_FBBMSEL_Pos)                    /*!< EBU BUSWCON3: FBBMSEL Mask              */\r
+#define EBU_BUSWCON3_NAA_Pos                  7                                                       /*!< EBU BUSWCON3: NAA Position              */\r
+#define EBU_BUSWCON3_NAA_Msk                  (0x01UL << EBU_BUSWCON3_NAA_Pos)                        /*!< EBU BUSWCON3: NAA Mask                  */\r
+#define EBU_BUSWCON3_ECSE_Pos                 16                                                      /*!< EBU BUSWCON3: ECSE Position             */\r
+#define EBU_BUSWCON3_ECSE_Msk                 (0x01UL << EBU_BUSWCON3_ECSE_Pos)                       /*!< EBU BUSWCON3: ECSE Mask                 */\r
+#define EBU_BUSWCON3_EBSE_Pos                 17                                                      /*!< EBU BUSWCON3: EBSE Position             */\r
+#define EBU_BUSWCON3_EBSE_Msk                 (0x01UL << EBU_BUSWCON3_EBSE_Pos)                       /*!< EBU BUSWCON3: EBSE Mask                 */\r
+#define EBU_BUSWCON3_WAITINV_Pos              19                                                      /*!< EBU BUSWCON3: WAITINV Position          */\r
+#define EBU_BUSWCON3_WAITINV_Msk              (0x01UL << EBU_BUSWCON3_WAITINV_Pos)                    /*!< EBU BUSWCON3: WAITINV Mask              */\r
+#define EBU_BUSWCON3_BCGEN_Pos                20                                                      /*!< EBU BUSWCON3: BCGEN Position            */\r
+#define EBU_BUSWCON3_BCGEN_Msk                (0x03UL << EBU_BUSWCON3_BCGEN_Pos)                      /*!< EBU BUSWCON3: BCGEN Mask                */\r
+#define EBU_BUSWCON3_PORTW_Pos                22                                                      /*!< EBU BUSWCON3: PORTW Position            */\r
+#define EBU_BUSWCON3_PORTW_Msk                (0x03UL << EBU_BUSWCON3_PORTW_Pos)                      /*!< EBU BUSWCON3: PORTW Mask                */\r
+#define EBU_BUSWCON3_WAIT_Pos                 24                                                      /*!< EBU BUSWCON3: WAIT Position             */\r
+#define EBU_BUSWCON3_WAIT_Msk                 (0x03UL << EBU_BUSWCON3_WAIT_Pos)                       /*!< EBU BUSWCON3: WAIT Mask                 */\r
+#define EBU_BUSWCON3_AAP_Pos                  26                                                      /*!< EBU BUSWCON3: AAP Position              */\r
+#define EBU_BUSWCON3_AAP_Msk                  (0x01UL << EBU_BUSWCON3_AAP_Pos)                        /*!< EBU BUSWCON3: AAP Mask                  */\r
+#define EBU_BUSWCON3_LOCKCS_Pos               27                                                      /*!< EBU BUSWCON3: LOCKCS Position           */\r
+#define EBU_BUSWCON3_LOCKCS_Msk               (0x01UL << EBU_BUSWCON3_LOCKCS_Pos)                     /*!< EBU BUSWCON3: LOCKCS Mask               */\r
+#define EBU_BUSWCON3_AGEN_Pos                 28                                                      /*!< EBU BUSWCON3: AGEN Position             */\r
+#define EBU_BUSWCON3_AGEN_Msk                 (0x0fUL << EBU_BUSWCON3_AGEN_Pos)                       /*!< EBU BUSWCON3: AGEN Mask                 */\r
+\r
+/* ---------------------------------  EBU_BUSWAP3  -------------------------------- */\r
+#define EBU_BUSWAP3_WRDTACS_Pos               0                                                       /*!< EBU BUSWAP3: WRDTACS Position           */\r
+#define EBU_BUSWAP3_WRDTACS_Msk               (0x0fUL << EBU_BUSWAP3_WRDTACS_Pos)                     /*!< EBU BUSWAP3: WRDTACS Mask               */\r
+#define EBU_BUSWAP3_WRRECOVC_Pos              4                                                       /*!< EBU BUSWAP3: WRRECOVC Position          */\r
+#define EBU_BUSWAP3_WRRECOVC_Msk              (0x07UL << EBU_BUSWAP3_WRRECOVC_Pos)                    /*!< EBU BUSWAP3: WRRECOVC Mask              */\r
+#define EBU_BUSWAP3_WAITWRC_Pos               7                                                       /*!< EBU BUSWAP3: WAITWRC Position           */\r
+#define EBU_BUSWAP3_WAITWRC_Msk               (0x1fUL << EBU_BUSWAP3_WAITWRC_Pos)                     /*!< EBU BUSWAP3: WAITWRC Mask               */\r
+#define EBU_BUSWAP3_DATAC_Pos                 12                                                      /*!< EBU BUSWAP3: DATAC Position             */\r
+#define EBU_BUSWAP3_DATAC_Msk                 (0x0fUL << EBU_BUSWAP3_DATAC_Pos)                       /*!< EBU BUSWAP3: DATAC Mask                 */\r
+#define EBU_BUSWAP3_EXTCLOCK_Pos              16                                                      /*!< EBU BUSWAP3: EXTCLOCK Position          */\r
+#define EBU_BUSWAP3_EXTCLOCK_Msk              (0x03UL << EBU_BUSWAP3_EXTCLOCK_Pos)                    /*!< EBU BUSWAP3: EXTCLOCK Mask              */\r
+#define EBU_BUSWAP3_EXTDATA_Pos               18                                                      /*!< EBU BUSWAP3: EXTDATA Position           */\r
+#define EBU_BUSWAP3_EXTDATA_Msk               (0x03UL << EBU_BUSWAP3_EXTDATA_Pos)                     /*!< EBU BUSWAP3: EXTDATA Mask               */\r
+#define EBU_BUSWAP3_CMDDELAY_Pos              20                                                      /*!< EBU BUSWAP3: CMDDELAY Position          */\r
+#define EBU_BUSWAP3_CMDDELAY_Msk              (0x0fUL << EBU_BUSWAP3_CMDDELAY_Pos)                    /*!< EBU BUSWAP3: CMDDELAY Mask              */\r
+#define EBU_BUSWAP3_AHOLDC_Pos                24                                                      /*!< EBU BUSWAP3: AHOLDC Position            */\r
+#define EBU_BUSWAP3_AHOLDC_Msk                (0x0fUL << EBU_BUSWAP3_AHOLDC_Pos)                      /*!< EBU BUSWAP3: AHOLDC Mask                */\r
+#define EBU_BUSWAP3_ADDRC_Pos                 28                                                      /*!< EBU BUSWAP3: ADDRC Position             */\r
+#define EBU_BUSWAP3_ADDRC_Msk                 (0x0fUL << EBU_BUSWAP3_ADDRC_Pos)                       /*!< EBU BUSWAP3: ADDRC Mask                 */\r
+\r
+/* ---------------------------------  EBU_SDRMCON  -------------------------------- */\r
+#define EBU_SDRMCON_CRAS_Pos                  0                                                       /*!< EBU SDRMCON: CRAS Position              */\r
+#define EBU_SDRMCON_CRAS_Msk                  (0x0fUL << EBU_SDRMCON_CRAS_Pos)                        /*!< EBU SDRMCON: CRAS Mask                  */\r
+#define EBU_SDRMCON_CRFSH_Pos                 4                                                       /*!< EBU SDRMCON: CRFSH Position             */\r
+#define EBU_SDRMCON_CRFSH_Msk                 (0x0fUL << EBU_SDRMCON_CRFSH_Pos)                       /*!< EBU SDRMCON: CRFSH Mask                 */\r
+#define EBU_SDRMCON_CRSC_Pos                  8                                                       /*!< EBU SDRMCON: CRSC Position              */\r
+#define EBU_SDRMCON_CRSC_Msk                  (0x03UL << EBU_SDRMCON_CRSC_Pos)                        /*!< EBU SDRMCON: CRSC Mask                  */\r
+#define EBU_SDRMCON_CRP_Pos                   10                                                      /*!< EBU SDRMCON: CRP Position               */\r
+#define EBU_SDRMCON_CRP_Msk                   (0x03UL << EBU_SDRMCON_CRP_Pos)                         /*!< EBU SDRMCON: CRP Mask                   */\r
+#define EBU_SDRMCON_AWIDTH_Pos                12                                                      /*!< EBU SDRMCON: AWIDTH Position            */\r
+#define EBU_SDRMCON_AWIDTH_Msk                (0x03UL << EBU_SDRMCON_AWIDTH_Pos)                      /*!< EBU SDRMCON: AWIDTH Mask                */\r
+#define EBU_SDRMCON_CRCD_Pos                  14                                                      /*!< EBU SDRMCON: CRCD Position              */\r
+#define EBU_SDRMCON_CRCD_Msk                  (0x03UL << EBU_SDRMCON_CRCD_Pos)                        /*!< EBU SDRMCON: CRCD Mask                  */\r
+#define EBU_SDRMCON_CRC_Pos                   16                                                      /*!< EBU SDRMCON: CRC Position               */\r
+#define EBU_SDRMCON_CRC_Msk                   (0x07UL << EBU_SDRMCON_CRC_Pos)                         /*!< EBU SDRMCON: CRC Mask                   */\r
+#define EBU_SDRMCON_ROWM_Pos                  19                                                      /*!< EBU SDRMCON: ROWM Position              */\r
+#define EBU_SDRMCON_ROWM_Msk                  (0x07UL << EBU_SDRMCON_ROWM_Pos)                        /*!< EBU SDRMCON: ROWM Mask                  */\r
+#define EBU_SDRMCON_BANKM_Pos                 22                                                      /*!< EBU SDRMCON: BANKM Position             */\r
+#define EBU_SDRMCON_BANKM_Msk                 (0x07UL << EBU_SDRMCON_BANKM_Pos)                       /*!< EBU SDRMCON: BANKM Mask                 */\r
+#define EBU_SDRMCON_CRCE_Pos                  25                                                      /*!< EBU SDRMCON: CRCE Position              */\r
+#define EBU_SDRMCON_CRCE_Msk                  (0x07UL << EBU_SDRMCON_CRCE_Pos)                        /*!< EBU SDRMCON: CRCE Mask                  */\r
+#define EBU_SDRMCON_CLKDIS_Pos                28                                                      /*!< EBU SDRMCON: CLKDIS Position            */\r
+#define EBU_SDRMCON_CLKDIS_Msk                (0x01UL << EBU_SDRMCON_CLKDIS_Pos)                      /*!< EBU SDRMCON: CLKDIS Mask                */\r
+#define EBU_SDRMCON_PWR_MODE_Pos              29                                                      /*!< EBU SDRMCON: PWR_MODE Position          */\r
+#define EBU_SDRMCON_PWR_MODE_Msk              (0x03UL << EBU_SDRMCON_PWR_MODE_Pos)                    /*!< EBU SDRMCON: PWR_MODE Mask              */\r
+#define EBU_SDRMCON_SDCMSEL_Pos               31                                                      /*!< EBU SDRMCON: SDCMSEL Position           */\r
+#define EBU_SDRMCON_SDCMSEL_Msk               (0x01UL << EBU_SDRMCON_SDCMSEL_Pos)                     /*!< EBU SDRMCON: SDCMSEL Mask               */\r
+\r
+/* ---------------------------------  EBU_SDRMOD  --------------------------------- */\r
+#define EBU_SDRMOD_BURSTL_Pos                 0                                                       /*!< EBU SDRMOD: BURSTL Position             */\r
+#define EBU_SDRMOD_BURSTL_Msk                 (0x07UL << EBU_SDRMOD_BURSTL_Pos)                       /*!< EBU SDRMOD: BURSTL Mask                 */\r
+#define EBU_SDRMOD_BTYP_Pos                   3                                                       /*!< EBU SDRMOD: BTYP Position               */\r
+#define EBU_SDRMOD_BTYP_Msk                   (0x01UL << EBU_SDRMOD_BTYP_Pos)                         /*!< EBU SDRMOD: BTYP Mask                   */\r
+#define EBU_SDRMOD_CASLAT_Pos                 4                                                       /*!< EBU SDRMOD: CASLAT Position             */\r
+#define EBU_SDRMOD_CASLAT_Msk                 (0x07UL << EBU_SDRMOD_CASLAT_Pos)                       /*!< EBU SDRMOD: CASLAT Mask                 */\r
+#define EBU_SDRMOD_OPMODE_Pos                 7                                                       /*!< EBU SDRMOD: OPMODE Position             */\r
+#define EBU_SDRMOD_OPMODE_Msk                 (0x7fUL << EBU_SDRMOD_OPMODE_Pos)                       /*!< EBU SDRMOD: OPMODE Mask                 */\r
+#define EBU_SDRMOD_COLDSTART_Pos              15                                                      /*!< EBU SDRMOD: COLDSTART Position          */\r
+#define EBU_SDRMOD_COLDSTART_Msk              (0x01UL << EBU_SDRMOD_COLDSTART_Pos)                    /*!< EBU SDRMOD: COLDSTART Mask              */\r
+#define EBU_SDRMOD_XOPM_Pos                   16                                                      /*!< EBU SDRMOD: XOPM Position               */\r
+#define EBU_SDRMOD_XOPM_Msk                   (0x00000fffUL << EBU_SDRMOD_XOPM_Pos)                   /*!< EBU SDRMOD: XOPM Mask                   */\r
+#define EBU_SDRMOD_XBA_Pos                    28                                                      /*!< EBU SDRMOD: XBA Position                */\r
+#define EBU_SDRMOD_XBA_Msk                    (0x0fUL << EBU_SDRMOD_XBA_Pos)                          /*!< EBU SDRMOD: XBA Mask                    */\r
+\r
+/* ---------------------------------  EBU_SDRMREF  -------------------------------- */\r
+#define EBU_SDRMREF_REFRESHC_Pos              0                                                       /*!< EBU SDRMREF: REFRESHC Position          */\r
+#define EBU_SDRMREF_REFRESHC_Msk              (0x3fUL << EBU_SDRMREF_REFRESHC_Pos)                    /*!< EBU SDRMREF: REFRESHC Mask              */\r
+#define EBU_SDRMREF_REFRESHR_Pos              6                                                       /*!< EBU SDRMREF: REFRESHR Position          */\r
+#define EBU_SDRMREF_REFRESHR_Msk              (0x07UL << EBU_SDRMREF_REFRESHR_Pos)                    /*!< EBU SDRMREF: REFRESHR Mask              */\r
+#define EBU_SDRMREF_SELFREXST_Pos             9                                                       /*!< EBU SDRMREF: SELFREXST Position         */\r
+#define EBU_SDRMREF_SELFREXST_Msk             (0x01UL << EBU_SDRMREF_SELFREXST_Pos)                   /*!< EBU SDRMREF: SELFREXST Mask             */\r
+#define EBU_SDRMREF_SELFREX_Pos               10                                                      /*!< EBU SDRMREF: SELFREX Position           */\r
+#define EBU_SDRMREF_SELFREX_Msk               (0x01UL << EBU_SDRMREF_SELFREX_Pos)                     /*!< EBU SDRMREF: SELFREX Mask               */\r
+#define EBU_SDRMREF_SELFRENST_Pos             11                                                      /*!< EBU SDRMREF: SELFRENST Position         */\r
+#define EBU_SDRMREF_SELFRENST_Msk             (0x01UL << EBU_SDRMREF_SELFRENST_Pos)                   /*!< EBU SDRMREF: SELFRENST Mask             */\r
+#define EBU_SDRMREF_SELFREN_Pos               12                                                      /*!< EBU SDRMREF: SELFREN Position           */\r
+#define EBU_SDRMREF_SELFREN_Msk               (0x01UL << EBU_SDRMREF_SELFREN_Pos)                     /*!< EBU SDRMREF: SELFREN Mask               */\r
+#define EBU_SDRMREF_AUTOSELFR_Pos             13                                                      /*!< EBU SDRMREF: AUTOSELFR Position         */\r
+#define EBU_SDRMREF_AUTOSELFR_Msk             (0x01UL << EBU_SDRMREF_AUTOSELFR_Pos)                   /*!< EBU SDRMREF: AUTOSELFR Mask             */\r
+#define EBU_SDRMREF_ERFSHC_Pos                14                                                      /*!< EBU SDRMREF: ERFSHC Position            */\r
+#define EBU_SDRMREF_ERFSHC_Msk                (0x03UL << EBU_SDRMREF_ERFSHC_Pos)                      /*!< EBU SDRMREF: ERFSHC Mask                */\r
+#define EBU_SDRMREF_SELFREX_DLY_Pos           16                                                      /*!< EBU SDRMREF: SELFREX_DLY Position       */\r
+#define EBU_SDRMREF_SELFREX_DLY_Msk           (0x000000ffUL << EBU_SDRMREF_SELFREX_DLY_Pos)           /*!< EBU SDRMREF: SELFREX_DLY Mask           */\r
+#define EBU_SDRMREF_ARFSH_Pos                 24                                                      /*!< EBU SDRMREF: ARFSH Position             */\r
+#define EBU_SDRMREF_ARFSH_Msk                 (0x01UL << EBU_SDRMREF_ARFSH_Pos)                       /*!< EBU SDRMREF: ARFSH Mask                 */\r
+#define EBU_SDRMREF_RES_DLY_Pos               25                                                      /*!< EBU SDRMREF: RES_DLY Position           */\r
+#define EBU_SDRMREF_RES_DLY_Msk               (0x07UL << EBU_SDRMREF_RES_DLY_Pos)                     /*!< EBU SDRMREF: RES_DLY Mask               */\r
+\r
+/* ---------------------------------  EBU_SDRSTAT  -------------------------------- */\r
+#define EBU_SDRSTAT_REFERR_Pos                0                                                       /*!< EBU SDRSTAT: REFERR Position            */\r
+#define EBU_SDRSTAT_REFERR_Msk                (0x01UL << EBU_SDRSTAT_REFERR_Pos)                      /*!< EBU SDRSTAT: REFERR Mask                */\r
+#define EBU_SDRSTAT_SDRMBUSY_Pos              1                                                       /*!< EBU SDRSTAT: SDRMBUSY Position          */\r
+#define EBU_SDRSTAT_SDRMBUSY_Msk              (0x01UL << EBU_SDRSTAT_SDRMBUSY_Pos)                    /*!< EBU SDRSTAT: SDRMBUSY Mask              */\r
+#define EBU_SDRSTAT_SDERR_Pos                 2                                                       /*!< EBU SDRSTAT: SDERR Position             */\r
+#define EBU_SDRSTAT_SDERR_Msk                 (0x01UL << EBU_SDRSTAT_SDERR_Pos)                       /*!< EBU SDRSTAT: SDERR Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'ETH0_CON' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  ETH0_CON_ETH0_CON  ----------------------------- */\r
+#define ETH_CON_RXD0_Pos            0                                                       /*!< ETH0_CON ETH0_CON: RXD0 Position        */\r
+#define ETH_CON_RXD0_Msk            (0x03UL << ETH_CON_RXD0_Pos)                  /*!< ETH0_CON ETH0_CON: RXD0 Mask            */\r
+#define ETH_CON_RXD1_Pos            2                                                       /*!< ETH0_CON ETH0_CON: RXD1 Position        */\r
+#define ETH_CON_RXD1_Msk            (0x03UL << ETH_CON_RXD1_Pos)                  /*!< ETH0_CON ETH0_CON: RXD1 Mask            */\r
+#define ETH_CON_RXD2_Pos            4                                                       /*!< ETH0_CON ETH0_CON: RXD2 Position        */\r
+#define ETH_CON_RXD2_Msk            (0x03UL << ETH_CON_RXD2_Pos)                  /*!< ETH0_CON ETH0_CON: RXD2 Mask            */\r
+#define ETH_CON_RXD3_Pos            6                                                       /*!< ETH0_CON ETH0_CON: RXD3 Position        */\r
+#define ETH_CON_RXD3_Msk            (0x03UL << ETH_CON_RXD3_Pos)                  /*!< ETH0_CON ETH0_CON: RXD3 Mask            */\r
+#define ETH_CON_CLK_RMII_Pos        8                                                       /*!< ETH0_CON ETH0_CON: CLK_RMII Position    */\r
+#define ETH_CON_CLK_RMII_Msk        (0x03UL << ETH_CON_CLK_RMII_Pos)              /*!< ETH0_CON ETH0_CON: CLK_RMII Mask        */\r
+#define ETH_CON_CRS_DV_Pos          10                                                      /*!< ETH0_CON ETH0_CON: CRS_DV Position      */\r
+#define ETH_CON_CRS_DV_Msk          (0x03UL << ETH_CON_CRS_DV_Pos)                /*!< ETH0_CON ETH0_CON: CRS_DV Mask          */\r
+#define ETH_CON_CRS_Pos             12                                                      /*!< ETH0_CON ETH0_CON: CRS Position         */\r
+#define ETH_CON_CRS_Msk             (0x03UL << ETH_CON_CRS_Pos)                   /*!< ETH0_CON ETH0_CON: CRS Mask             */\r
+#define ETH_CON_RXER_Pos            14                                                      /*!< ETH0_CON ETH0_CON: RXER Position        */\r
+#define ETH_CON_RXER_Msk            (0x03UL << ETH_CON_RXER_Pos)                  /*!< ETH0_CON ETH0_CON: RXER Mask            */\r
+#define ETH_CON_COL_Pos             16                                                      /*!< ETH0_CON ETH0_CON: COL Position         */\r
+#define ETH_CON_COL_Msk             (0x03UL << ETH_CON_COL_Pos)                   /*!< ETH0_CON ETH0_CON: COL Mask             */\r
+#define ETH_CON_CLK_TX_Pos          18                                                      /*!< ETH0_CON ETH0_CON: CLK_TX Position      */\r
+#define ETH_CON_CLK_TX_Msk          (0x03UL << ETH_CON_CLK_TX_Pos)                /*!< ETH0_CON ETH0_CON: CLK_TX Mask          */\r
+#define ETH_CON_MDIO_Pos            22                                                      /*!< ETH0_CON ETH0_CON: MDIO Position        */\r
+#define ETH_CON_MDIO_Msk            (0x03UL << ETH_CON_MDIO_Pos)                  /*!< ETH0_CON ETH0_CON: MDIO Mask            */\r
+#define ETH_CON_INFSEL_Pos          26                                                      /*!< ETH0_CON ETH0_CON: INFSEL Position      */\r
+#define ETH_CON_INFSEL_Msk          (0x01UL << ETH_CON_INFSEL_Pos)                /*!< ETH0_CON ETH0_CON: INFSEL Mask          */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'ETH' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------  ETH_MAC_CONFIGURATION  --------------------------- */\r
+#define ETH_MAC_CONFIGURATION_PRELEN_Pos      0                                                       /*!< ETH MAC_CONFIGURATION: PRELEN Position  */\r
+#define ETH_MAC_CONFIGURATION_PRELEN_Msk      (0x03UL << ETH_MAC_CONFIGURATION_PRELEN_Pos)            /*!< ETH MAC_CONFIGURATION: PRELEN Mask      */\r
+#define ETH_MAC_CONFIGURATION_RE_Pos          2                                                       /*!< ETH MAC_CONFIGURATION: RE Position      */\r
+#define ETH_MAC_CONFIGURATION_RE_Msk          (0x01UL << ETH_MAC_CONFIGURATION_RE_Pos)                /*!< ETH MAC_CONFIGURATION: RE Mask          */\r
+#define ETH_MAC_CONFIGURATION_TE_Pos          3                                                       /*!< ETH MAC_CONFIGURATION: TE Position      */\r
+#define ETH_MAC_CONFIGURATION_TE_Msk          (0x01UL << ETH_MAC_CONFIGURATION_TE_Pos)                /*!< ETH MAC_CONFIGURATION: TE Mask          */\r
+#define ETH_MAC_CONFIGURATION_DC_Pos          4                                                       /*!< ETH MAC_CONFIGURATION: DC Position      */\r
+#define ETH_MAC_CONFIGURATION_DC_Msk          (0x01UL << ETH_MAC_CONFIGURATION_DC_Pos)                /*!< ETH MAC_CONFIGURATION: DC Mask          */\r
+#define ETH_MAC_CONFIGURATION_BL_Pos          5                                                       /*!< ETH MAC_CONFIGURATION: BL Position      */\r
+#define ETH_MAC_CONFIGURATION_BL_Msk          (0x03UL << ETH_MAC_CONFIGURATION_BL_Pos)                /*!< ETH MAC_CONFIGURATION: BL Mask          */\r
+#define ETH_MAC_CONFIGURATION_ACS_Pos         7                                                       /*!< ETH MAC_CONFIGURATION: ACS Position     */\r
+#define ETH_MAC_CONFIGURATION_ACS_Msk         (0x01UL << ETH_MAC_CONFIGURATION_ACS_Pos)               /*!< ETH MAC_CONFIGURATION: ACS Mask         */\r
+#define ETH_MAC_CONFIGURATION_Reserved_8_Pos  8                                                       /*!< ETH MAC_CONFIGURATION: Reserved_8 Position */\r
+#define ETH_MAC_CONFIGURATION_Reserved_8_Msk  (0x01UL << ETH_MAC_CONFIGURATION_Reserved_8_Pos)        /*!< ETH MAC_CONFIGURATION: Reserved_8 Mask  */\r
+#define ETH_MAC_CONFIGURATION_DR_Pos          9                                                       /*!< ETH MAC_CONFIGURATION: DR Position      */\r
+#define ETH_MAC_CONFIGURATION_DR_Msk          (0x01UL << ETH_MAC_CONFIGURATION_DR_Pos)                /*!< ETH MAC_CONFIGURATION: DR Mask          */\r
+#define ETH_MAC_CONFIGURATION_IPC_Pos         10                                                      /*!< ETH MAC_CONFIGURATION: IPC Position     */\r
+#define ETH_MAC_CONFIGURATION_IPC_Msk         (0x01UL << ETH_MAC_CONFIGURATION_IPC_Pos)               /*!< ETH MAC_CONFIGURATION: IPC Mask         */\r
+#define ETH_MAC_CONFIGURATION_DM_Pos          11                                                      /*!< ETH MAC_CONFIGURATION: DM Position      */\r
+#define ETH_MAC_CONFIGURATION_DM_Msk          (0x01UL << ETH_MAC_CONFIGURATION_DM_Pos)                /*!< ETH MAC_CONFIGURATION: DM Mask          */\r
+#define ETH_MAC_CONFIGURATION_LM_Pos          12                                                      /*!< ETH MAC_CONFIGURATION: LM Position      */\r
+#define ETH_MAC_CONFIGURATION_LM_Msk          (0x01UL << ETH_MAC_CONFIGURATION_LM_Pos)                /*!< ETH MAC_CONFIGURATION: LM Mask          */\r
+#define ETH_MAC_CONFIGURATION_DO_Pos          13                                                      /*!< ETH MAC_CONFIGURATION: DO Position      */\r
+#define ETH_MAC_CONFIGURATION_DO_Msk          (0x01UL << ETH_MAC_CONFIGURATION_DO_Pos)                /*!< ETH MAC_CONFIGURATION: DO Mask          */\r
+#define ETH_MAC_CONFIGURATION_FES_Pos         14                                                      /*!< ETH MAC_CONFIGURATION: FES Position     */\r
+#define ETH_MAC_CONFIGURATION_FES_Msk         (0x01UL << ETH_MAC_CONFIGURATION_FES_Pos)               /*!< ETH MAC_CONFIGURATION: FES Mask         */\r
+#define ETH_MAC_CONFIGURATION_DCRS_Pos        16                                                      /*!< ETH MAC_CONFIGURATION: DCRS Position    */\r
+#define ETH_MAC_CONFIGURATION_DCRS_Msk        (0x01UL << ETH_MAC_CONFIGURATION_DCRS_Pos)              /*!< ETH MAC_CONFIGURATION: DCRS Mask        */\r
+#define ETH_MAC_CONFIGURATION_IFG_Pos         17                                                      /*!< ETH MAC_CONFIGURATION: IFG Position     */\r
+#define ETH_MAC_CONFIGURATION_IFG_Msk         (0x07UL << ETH_MAC_CONFIGURATION_IFG_Pos)               /*!< ETH MAC_CONFIGURATION: IFG Mask         */\r
+#define ETH_MAC_CONFIGURATION_JE_Pos          20                                                      /*!< ETH MAC_CONFIGURATION: JE Position      */\r
+#define ETH_MAC_CONFIGURATION_JE_Msk          (0x01UL << ETH_MAC_CONFIGURATION_JE_Pos)                /*!< ETH MAC_CONFIGURATION: JE Mask          */\r
+#define ETH_MAC_CONFIGURATION_BE_Pos          21                                                      /*!< ETH MAC_CONFIGURATION: BE Position      */\r
+#define ETH_MAC_CONFIGURATION_BE_Msk          (0x01UL << ETH_MAC_CONFIGURATION_BE_Pos)                /*!< ETH MAC_CONFIGURATION: BE Mask          */\r
+#define ETH_MAC_CONFIGURATION_JD_Pos          22                                                      /*!< ETH MAC_CONFIGURATION: JD Position      */\r
+#define ETH_MAC_CONFIGURATION_JD_Msk          (0x01UL << ETH_MAC_CONFIGURATION_JD_Pos)                /*!< ETH MAC_CONFIGURATION: JD Mask          */\r
+#define ETH_MAC_CONFIGURATION_WD_Pos          23                                                      /*!< ETH MAC_CONFIGURATION: WD Position      */\r
+#define ETH_MAC_CONFIGURATION_WD_Msk          (0x01UL << ETH_MAC_CONFIGURATION_WD_Pos)                /*!< ETH MAC_CONFIGURATION: WD Mask          */\r
+#define ETH_MAC_CONFIGURATION_TC_Pos          24                                                      /*!< ETH MAC_CONFIGURATION: TC Position      */\r
+#define ETH_MAC_CONFIGURATION_TC_Msk          (0x01UL << ETH_MAC_CONFIGURATION_TC_Pos)                /*!< ETH MAC_CONFIGURATION: TC Mask          */\r
+#define ETH_MAC_CONFIGURATION_CST_Pos         25                                                      /*!< ETH MAC_CONFIGURATION: CST Position     */\r
+#define ETH_MAC_CONFIGURATION_CST_Msk         (0x01UL << ETH_MAC_CONFIGURATION_CST_Pos)               /*!< ETH MAC_CONFIGURATION: CST Mask         */\r
+#define ETH_MAC_CONFIGURATION_Reserved_26_Pos 26                                                      /*!< ETH MAC_CONFIGURATION: Reserved_26 Position */\r
+#define ETH_MAC_CONFIGURATION_Reserved_26_Msk (0x01UL << ETH_MAC_CONFIGURATION_Reserved_26_Pos)       /*!< ETH MAC_CONFIGURATION: Reserved_26 Mask */\r
+#define ETH_MAC_CONFIGURATION_TWOKPE_Pos      27                                                      /*!< ETH MAC_CONFIGURATION: TWOKPE Position  */\r
+#define ETH_MAC_CONFIGURATION_TWOKPE_Msk      (0x01UL << ETH_MAC_CONFIGURATION_TWOKPE_Pos)            /*!< ETH MAC_CONFIGURATION: TWOKPE Mask      */\r
+#define ETH_MAC_CONFIGURATION_SARC_Pos        28                                                      /*!< ETH MAC_CONFIGURATION: SARC Position    */\r
+#define ETH_MAC_CONFIGURATION_SARC_Msk        (0x07UL << ETH_MAC_CONFIGURATION_SARC_Pos)              /*!< ETH MAC_CONFIGURATION: SARC Mask        */\r
+#define ETH_MAC_CONFIGURATION_Reserved_31_Pos 31                                                      /*!< ETH MAC_CONFIGURATION: Reserved_31 Position */\r
+#define ETH_MAC_CONFIGURATION_Reserved_31_Msk (0x01UL << ETH_MAC_CONFIGURATION_Reserved_31_Pos)       /*!< ETH MAC_CONFIGURATION: Reserved_31 Mask */\r
+\r
+/* ----------------------------  ETH_MAC_FRAME_FILTER  ---------------------------- */\r
+#define ETH_MAC_FRAME_FILTER_PR_Pos           0                                                       /*!< ETH MAC_FRAME_FILTER: PR Position       */\r
+#define ETH_MAC_FRAME_FILTER_PR_Msk           (0x01UL << ETH_MAC_FRAME_FILTER_PR_Pos)                 /*!< ETH MAC_FRAME_FILTER: PR Mask           */\r
+#define ETH_MAC_FRAME_FILTER_HUC_Pos          1                                                       /*!< ETH MAC_FRAME_FILTER: HUC Position      */\r
+#define ETH_MAC_FRAME_FILTER_HUC_Msk          (0x01UL << ETH_MAC_FRAME_FILTER_HUC_Pos)                /*!< ETH MAC_FRAME_FILTER: HUC Mask          */\r
+#define ETH_MAC_FRAME_FILTER_HMC_Pos          2                                                       /*!< ETH MAC_FRAME_FILTER: HMC Position      */\r
+#define ETH_MAC_FRAME_FILTER_HMC_Msk          (0x01UL << ETH_MAC_FRAME_FILTER_HMC_Pos)                /*!< ETH MAC_FRAME_FILTER: HMC Mask          */\r
+#define ETH_MAC_FRAME_FILTER_DAIF_Pos         3                                                       /*!< ETH MAC_FRAME_FILTER: DAIF Position     */\r
+#define ETH_MAC_FRAME_FILTER_DAIF_Msk         (0x01UL << ETH_MAC_FRAME_FILTER_DAIF_Pos)               /*!< ETH MAC_FRAME_FILTER: DAIF Mask         */\r
+#define ETH_MAC_FRAME_FILTER_PM_Pos           4                                                       /*!< ETH MAC_FRAME_FILTER: PM Position       */\r
+#define ETH_MAC_FRAME_FILTER_PM_Msk           (0x01UL << ETH_MAC_FRAME_FILTER_PM_Pos)                 /*!< ETH MAC_FRAME_FILTER: PM Mask           */\r
+#define ETH_MAC_FRAME_FILTER_DBF_Pos          5                                                       /*!< ETH MAC_FRAME_FILTER: DBF Position      */\r
+#define ETH_MAC_FRAME_FILTER_DBF_Msk          (0x01UL << ETH_MAC_FRAME_FILTER_DBF_Pos)                /*!< ETH MAC_FRAME_FILTER: DBF Mask          */\r
+#define ETH_MAC_FRAME_FILTER_PCF_Pos          6                                                       /*!< ETH MAC_FRAME_FILTER: PCF Position      */\r
+#define ETH_MAC_FRAME_FILTER_PCF_Msk          (0x03UL << ETH_MAC_FRAME_FILTER_PCF_Pos)                /*!< ETH MAC_FRAME_FILTER: PCF Mask          */\r
+#define ETH_MAC_FRAME_FILTER_SAIF_Pos         8                                                       /*!< ETH MAC_FRAME_FILTER: SAIF Position     */\r
+#define ETH_MAC_FRAME_FILTER_SAIF_Msk         (0x01UL << ETH_MAC_FRAME_FILTER_SAIF_Pos)               /*!< ETH MAC_FRAME_FILTER: SAIF Mask         */\r
+#define ETH_MAC_FRAME_FILTER_SAF_Pos          9                                                       /*!< ETH MAC_FRAME_FILTER: SAF Position      */\r
+#define ETH_MAC_FRAME_FILTER_SAF_Msk          (0x01UL << ETH_MAC_FRAME_FILTER_SAF_Pos)                /*!< ETH MAC_FRAME_FILTER: SAF Mask          */\r
+#define ETH_MAC_FRAME_FILTER_HPF_Pos          10                                                      /*!< ETH MAC_FRAME_FILTER: HPF Position      */\r
+#define ETH_MAC_FRAME_FILTER_HPF_Msk          (0x01UL << ETH_MAC_FRAME_FILTER_HPF_Pos)                /*!< ETH MAC_FRAME_FILTER: HPF Mask          */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_15_11_Pos 11                                                    /*!< ETH MAC_FRAME_FILTER: Reserved_15_11 Position */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_15_11_Msk (0x1fUL << ETH_MAC_FRAME_FILTER_Reserved_15_11_Pos)   /*!< ETH MAC_FRAME_FILTER: Reserved_15_11 Mask */\r
+#define ETH_MAC_FRAME_FILTER_VTFE_Pos         16                                                      /*!< ETH MAC_FRAME_FILTER: VTFE Position     */\r
+#define ETH_MAC_FRAME_FILTER_VTFE_Msk         (0x01UL << ETH_MAC_FRAME_FILTER_VTFE_Pos)               /*!< ETH MAC_FRAME_FILTER: VTFE Mask         */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_19_17_Pos 17                                                    /*!< ETH MAC_FRAME_FILTER: Reserved_19_17 Position */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_19_17_Msk (0x07UL << ETH_MAC_FRAME_FILTER_Reserved_19_17_Pos)   /*!< ETH MAC_FRAME_FILTER: Reserved_19_17 Mask */\r
+#define ETH_MAC_FRAME_FILTER_IPFE_Pos         20                                                      /*!< ETH MAC_FRAME_FILTER: IPFE Position     */\r
+#define ETH_MAC_FRAME_FILTER_IPFE_Msk         (0x01UL << ETH_MAC_FRAME_FILTER_IPFE_Pos)               /*!< ETH MAC_FRAME_FILTER: IPFE Mask         */\r
+#define ETH_MAC_FRAME_FILTER_DNTU_Pos         21                                                      /*!< ETH MAC_FRAME_FILTER: DNTU Position     */\r
+#define ETH_MAC_FRAME_FILTER_DNTU_Msk         (0x01UL << ETH_MAC_FRAME_FILTER_DNTU_Pos)               /*!< ETH MAC_FRAME_FILTER: DNTU Mask         */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_30_22_Pos 22                                                    /*!< ETH MAC_FRAME_FILTER: Reserved_30_22 Position */\r
+#define ETH_MAC_FRAME_FILTER_Reserved_30_22_Msk (0x000001ffUL << ETH_MAC_FRAME_FILTER_Reserved_30_22_Pos)/*!< ETH MAC_FRAME_FILTER: Reserved_30_22 Mask */\r
+#define ETH_MAC_FRAME_FILTER_RA_Pos           31                                                      /*!< ETH MAC_FRAME_FILTER: RA Position       */\r
+#define ETH_MAC_FRAME_FILTER_RA_Msk           (0x01UL << ETH_MAC_FRAME_FILTER_RA_Pos)                 /*!< ETH MAC_FRAME_FILTER: RA Mask           */\r
+\r
+/* -----------------------------  ETH_HASH_TABLE_HIGH  ---------------------------- */\r
+#define ETH_HASH_TABLE_HIGH_HTH_Pos           0                                                       /*!< ETH HASH_TABLE_HIGH: HTH Position       */\r
+#define ETH_HASH_TABLE_HIGH_HTH_Msk           (0xffffffffUL << ETH_HASH_TABLE_HIGH_HTH_Pos)           /*!< ETH HASH_TABLE_HIGH: HTH Mask           */\r
+\r
+/* -----------------------------  ETH_HASH_TABLE_LOW  ----------------------------- */\r
+#define ETH_HASH_TABLE_LOW_HTL_Pos            0                                                       /*!< ETH HASH_TABLE_LOW: HTL Position        */\r
+#define ETH_HASH_TABLE_LOW_HTL_Msk            (0xffffffffUL << ETH_HASH_TABLE_LOW_HTL_Pos)            /*!< ETH HASH_TABLE_LOW: HTL Mask            */\r
+\r
+/* ------------------------------  ETH_GMII_ADDRESS  ------------------------------ */\r
+#define ETH_GMII_ADDRESS_MB_Pos               0                                                       /*!< ETH GMII_ADDRESS: MB Position           */\r
+#define ETH_GMII_ADDRESS_MB_Msk               (0x01UL << ETH_GMII_ADDRESS_MB_Pos)                     /*!< ETH GMII_ADDRESS: MB Mask               */\r
+#define ETH_GMII_ADDRESS_MW_Pos               1                                                       /*!< ETH GMII_ADDRESS: MW Position           */\r
+#define ETH_GMII_ADDRESS_MW_Msk               (0x01UL << ETH_GMII_ADDRESS_MW_Pos)                     /*!< ETH GMII_ADDRESS: MW Mask               */\r
+#define ETH_GMII_ADDRESS_CR_Pos               2                                                       /*!< ETH GMII_ADDRESS: CR Position           */\r
+#define ETH_GMII_ADDRESS_CR_Msk               (0x0fUL << ETH_GMII_ADDRESS_CR_Pos)                     /*!< ETH GMII_ADDRESS: CR Mask               */\r
+#define ETH_GMII_ADDRESS_MR_Pos               6                                                       /*!< ETH GMII_ADDRESS: MR Position           */\r
+#define ETH_GMII_ADDRESS_MR_Msk               (0x1fUL << ETH_GMII_ADDRESS_MR_Pos)                     /*!< ETH GMII_ADDRESS: MR Mask               */\r
+#define ETH_GMII_ADDRESS_PA_Pos               11                                                      /*!< ETH GMII_ADDRESS: PA Position           */\r
+#define ETH_GMII_ADDRESS_PA_Msk               (0x1fUL << ETH_GMII_ADDRESS_PA_Pos)                     /*!< ETH GMII_ADDRESS: PA Mask               */\r
+#define ETH_GMII_ADDRESS_Reserved_31_16_Pos   16                                                      /*!< ETH GMII_ADDRESS: Reserved_31_16 Position */\r
+#define ETH_GMII_ADDRESS_Reserved_31_16_Msk   (0x0000ffffUL << ETH_GMII_ADDRESS_Reserved_31_16_Pos)   /*!< ETH GMII_ADDRESS: Reserved_31_16 Mask   */\r
+\r
+/* --------------------------------  ETH_GMII_DATA  ------------------------------- */\r
+#define ETH_GMII_DATA_MD_Pos                  0                                                       /*!< ETH GMII_DATA: MD Position              */\r
+#define ETH_GMII_DATA_MD_Msk                  (0x0000ffffUL << ETH_GMII_DATA_MD_Pos)                  /*!< ETH GMII_DATA: MD Mask                  */\r
+#define ETH_GMII_DATA_Reserved_31_16_Pos      16                                                      /*!< ETH GMII_DATA: Reserved_31_16 Position  */\r
+#define ETH_GMII_DATA_Reserved_31_16_Msk      (0x0000ffffUL << ETH_GMII_DATA_Reserved_31_16_Pos)      /*!< ETH GMII_DATA: Reserved_31_16 Mask      */\r
+\r
+/* ------------------------------  ETH_FLOW_CONTROL  ------------------------------ */\r
+#define ETH_FLOW_CONTROL_FCA_BPA_Pos          0                                                       /*!< ETH FLOW_CONTROL: FCA_BPA Position      */\r
+#define ETH_FLOW_CONTROL_FCA_BPA_Msk          (0x01UL << ETH_FLOW_CONTROL_FCA_BPA_Pos)                /*!< ETH FLOW_CONTROL: FCA_BPA Mask          */\r
+#define ETH_FLOW_CONTROL_TFE_Pos              1                                                       /*!< ETH FLOW_CONTROL: TFE Position          */\r
+#define ETH_FLOW_CONTROL_TFE_Msk              (0x01UL << ETH_FLOW_CONTROL_TFE_Pos)                    /*!< ETH FLOW_CONTROL: TFE Mask              */\r
+#define ETH_FLOW_CONTROL_RFE_Pos              2                                                       /*!< ETH FLOW_CONTROL: RFE Position          */\r
+#define ETH_FLOW_CONTROL_RFE_Msk              (0x01UL << ETH_FLOW_CONTROL_RFE_Pos)                    /*!< ETH FLOW_CONTROL: RFE Mask              */\r
+#define ETH_FLOW_CONTROL_UP_Pos               3                                                       /*!< ETH FLOW_CONTROL: UP Position           */\r
+#define ETH_FLOW_CONTROL_UP_Msk               (0x01UL << ETH_FLOW_CONTROL_UP_Pos)                     /*!< ETH FLOW_CONTROL: UP Mask               */\r
+#define ETH_FLOW_CONTROL_PLT_Pos              4                                                       /*!< ETH FLOW_CONTROL: PLT Position          */\r
+#define ETH_FLOW_CONTROL_PLT_Msk              (0x03UL << ETH_FLOW_CONTROL_PLT_Pos)                    /*!< ETH FLOW_CONTROL: PLT Mask              */\r
+#define ETH_FLOW_CONTROL_Reserved_6_Pos       6                                                       /*!< ETH FLOW_CONTROL: Reserved_6 Position   */\r
+#define ETH_FLOW_CONTROL_Reserved_6_Msk       (0x01UL << ETH_FLOW_CONTROL_Reserved_6_Pos)             /*!< ETH FLOW_CONTROL: Reserved_6 Mask       */\r
+#define ETH_FLOW_CONTROL_DZPQ_Pos             7                                                       /*!< ETH FLOW_CONTROL: DZPQ Position         */\r
+#define ETH_FLOW_CONTROL_DZPQ_Msk             (0x01UL << ETH_FLOW_CONTROL_DZPQ_Pos)                   /*!< ETH FLOW_CONTROL: DZPQ Mask             */\r
+#define ETH_FLOW_CONTROL_Reserved_15_8_Pos    8                                                       /*!< ETH FLOW_CONTROL: Reserved_15_8 Position */\r
+#define ETH_FLOW_CONTROL_Reserved_15_8_Msk    (0x000000ffUL << ETH_FLOW_CONTROL_Reserved_15_8_Pos)    /*!< ETH FLOW_CONTROL: Reserved_15_8 Mask    */\r
+#define ETH_FLOW_CONTROL_PT_Pos               16                                                      /*!< ETH FLOW_CONTROL: PT Position           */\r
+#define ETH_FLOW_CONTROL_PT_Msk               (0x0000ffffUL << ETH_FLOW_CONTROL_PT_Pos)               /*!< ETH FLOW_CONTROL: PT Mask               */\r
+\r
+/* --------------------------------  ETH_VLAN_TAG  -------------------------------- */\r
+#define ETH_VLAN_TAG_VL_Pos                   0                                                       /*!< ETH VLAN_TAG: VL Position               */\r
+#define ETH_VLAN_TAG_VL_Msk                   (0x0000ffffUL << ETH_VLAN_TAG_VL_Pos)                   /*!< ETH VLAN_TAG: VL Mask                   */\r
+#define ETH_VLAN_TAG_ETV_Pos                  16                                                      /*!< ETH VLAN_TAG: ETV Position              */\r
+#define ETH_VLAN_TAG_ETV_Msk                  (0x01UL << ETH_VLAN_TAG_ETV_Pos)                        /*!< ETH VLAN_TAG: ETV Mask                  */\r
+#define ETH_VLAN_TAG_VTIM_Pos                 17                                                      /*!< ETH VLAN_TAG: VTIM Position             */\r
+#define ETH_VLAN_TAG_VTIM_Msk                 (0x01UL << ETH_VLAN_TAG_VTIM_Pos)                       /*!< ETH VLAN_TAG: VTIM Mask                 */\r
+#define ETH_VLAN_TAG_ESVL_Pos                 18                                                      /*!< ETH VLAN_TAG: ESVL Position             */\r
+#define ETH_VLAN_TAG_ESVL_Msk                 (0x01UL << ETH_VLAN_TAG_ESVL_Pos)                       /*!< ETH VLAN_TAG: ESVL Mask                 */\r
+#define ETH_VLAN_TAG_VTHM_Pos                 19                                                      /*!< ETH VLAN_TAG: VTHM Position             */\r
+#define ETH_VLAN_TAG_VTHM_Msk                 (0x01UL << ETH_VLAN_TAG_VTHM_Pos)                       /*!< ETH VLAN_TAG: VTHM Mask                 */\r
+#define ETH_VLAN_TAG_Reserved_31_20_Pos       20                                                      /*!< ETH VLAN_TAG: Reserved_31_20 Position   */\r
+#define ETH_VLAN_TAG_Reserved_31_20_Msk       (0x00000fffUL << ETH_VLAN_TAG_Reserved_31_20_Pos)       /*!< ETH VLAN_TAG: Reserved_31_20 Mask       */\r
+\r
+/* ---------------------------------  ETH_VERSION  -------------------------------- */\r
+#define ETH_VERSION_SNPSVER_Pos               0                                                       /*!< ETH VERSION: SNPSVER Position           */\r
+#define ETH_VERSION_SNPSVER_Msk               (0x000000ffUL << ETH_VERSION_SNPSVER_Pos)               /*!< ETH VERSION: SNPSVER Mask               */\r
+#define ETH_VERSION_USERVER_Pos               8                                                       /*!< ETH VERSION: USERVER Position           */\r
+#define ETH_VERSION_USERVER_Msk               (0x000000ffUL << ETH_VERSION_USERVER_Pos)               /*!< ETH VERSION: USERVER Mask               */\r
+#define ETH_VERSION_Reserved_31_16_Pos        16                                                      /*!< ETH VERSION: Reserved_31_16 Position    */\r
+#define ETH_VERSION_Reserved_31_16_Msk        (0x0000ffffUL << ETH_VERSION_Reserved_31_16_Pos)        /*!< ETH VERSION: Reserved_31_16 Mask        */\r
+\r
+/* ----------------------------------  ETH_DEBUG  --------------------------------- */\r
+#define ETH_DEBUG_RPESTS_Pos                  0                                                       /*!< ETH DEBUG: RPESTS Position              */\r
+#define ETH_DEBUG_RPESTS_Msk                  (0x01UL << ETH_DEBUG_RPESTS_Pos)                        /*!< ETH DEBUG: RPESTS Mask                  */\r
+#define ETH_DEBUG_RFCFCSTS_Pos                1                                                       /*!< ETH DEBUG: RFCFCSTS Position            */\r
+#define ETH_DEBUG_RFCFCSTS_Msk                (0x03UL << ETH_DEBUG_RFCFCSTS_Pos)                      /*!< ETH DEBUG: RFCFCSTS Mask                */\r
+#define ETH_DEBUG_Reserved_3_Pos              3                                                       /*!< ETH DEBUG: Reserved_3 Position          */\r
+#define ETH_DEBUG_Reserved_3_Msk              (0x01UL << ETH_DEBUG_Reserved_3_Pos)                    /*!< ETH DEBUG: Reserved_3 Mask              */\r
+#define ETH_DEBUG_RWCSTS_Pos                  4                                                       /*!< ETH DEBUG: RWCSTS Position              */\r
+#define ETH_DEBUG_RWCSTS_Msk                  (0x01UL << ETH_DEBUG_RWCSTS_Pos)                        /*!< ETH DEBUG: RWCSTS Mask                  */\r
+#define ETH_DEBUG_RRCSTS_Pos                  5                                                       /*!< ETH DEBUG: RRCSTS Position              */\r
+#define ETH_DEBUG_RRCSTS_Msk                  (0x03UL << ETH_DEBUG_RRCSTS_Pos)                        /*!< ETH DEBUG: RRCSTS Mask                  */\r
+#define ETH_DEBUG_Reserved_7_Pos              7                                                       /*!< ETH DEBUG: Reserved_7 Position          */\r
+#define ETH_DEBUG_Reserved_7_Msk              (0x01UL << ETH_DEBUG_Reserved_7_Pos)                    /*!< ETH DEBUG: Reserved_7 Mask              */\r
+#define ETH_DEBUG_RXFSTS_Pos                  8                                                       /*!< ETH DEBUG: RXFSTS Position              */\r
+#define ETH_DEBUG_RXFSTS_Msk                  (0x03UL << ETH_DEBUG_RXFSTS_Pos)                        /*!< ETH DEBUG: RXFSTS Mask                  */\r
+#define ETH_DEBUG_Reserved_15_10_Pos          10                                                      /*!< ETH DEBUG: Reserved_15_10 Position      */\r
+#define ETH_DEBUG_Reserved_15_10_Msk          (0x3fUL << ETH_DEBUG_Reserved_15_10_Pos)                /*!< ETH DEBUG: Reserved_15_10 Mask          */\r
+#define ETH_DEBUG_TPESTS_Pos                  16                                                      /*!< ETH DEBUG: TPESTS Position              */\r
+#define ETH_DEBUG_TPESTS_Msk                  (0x01UL << ETH_DEBUG_TPESTS_Pos)                        /*!< ETH DEBUG: TPESTS Mask                  */\r
+#define ETH_DEBUG_TFCSTS_Pos                  17                                                      /*!< ETH DEBUG: TFCSTS Position              */\r
+#define ETH_DEBUG_TFCSTS_Msk                  (0x03UL << ETH_DEBUG_TFCSTS_Pos)                        /*!< ETH DEBUG: TFCSTS Mask                  */\r
+#define ETH_DEBUG_TXPAUSED_Pos                19                                                      /*!< ETH DEBUG: TXPAUSED Position            */\r
+#define ETH_DEBUG_TXPAUSED_Msk                (0x01UL << ETH_DEBUG_TXPAUSED_Pos)                      /*!< ETH DEBUG: TXPAUSED Mask                */\r
+#define ETH_DEBUG_TRCSTS_Pos                  20                                                      /*!< ETH DEBUG: TRCSTS Position              */\r
+#define ETH_DEBUG_TRCSTS_Msk                  (0x03UL << ETH_DEBUG_TRCSTS_Pos)                        /*!< ETH DEBUG: TRCSTS Mask                  */\r
+#define ETH_DEBUG_TWCSTS_Pos                  22                                                      /*!< ETH DEBUG: TWCSTS Position              */\r
+#define ETH_DEBUG_TWCSTS_Msk                  (0x01UL << ETH_DEBUG_TWCSTS_Pos)                        /*!< ETH DEBUG: TWCSTS Mask                  */\r
+#define ETH_DEBUG_Reserved_23_Pos             23                                                      /*!< ETH DEBUG: Reserved_23 Position         */\r
+#define ETH_DEBUG_Reserved_23_Msk             (0x01UL << ETH_DEBUG_Reserved_23_Pos)                   /*!< ETH DEBUG: Reserved_23 Mask             */\r
+#define ETH_DEBUG_TXFSTS_Pos                  24                                                      /*!< ETH DEBUG: TXFSTS Position              */\r
+#define ETH_DEBUG_TXFSTS_Msk                  (0x01UL << ETH_DEBUG_TXFSTS_Pos)                        /*!< ETH DEBUG: TXFSTS Mask                  */\r
+#define ETH_DEBUG_TXSTSFSTS_Pos               25                                                      /*!< ETH DEBUG: TXSTSFSTS Position           */\r
+#define ETH_DEBUG_TXSTSFSTS_Msk               (0x01UL << ETH_DEBUG_TXSTSFSTS_Pos)                     /*!< ETH DEBUG: TXSTSFSTS Mask               */\r
+#define ETH_DEBUG_Reserved_31_26_Pos          26                                                      /*!< ETH DEBUG: Reserved_31_26 Position      */\r
+#define ETH_DEBUG_Reserved_31_26_Msk          (0x3fUL << ETH_DEBUG_Reserved_31_26_Pos)                /*!< ETH DEBUG: Reserved_31_26 Mask          */\r
+\r
+/* -----------------------  ETH_REMOTE_WAKE_UP_FRAME_FILTER  ---------------------- */\r
+#define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos 0                                              /*!< ETH REMOTE_WAKE_UP_FRAME_FILTER: WKUPFRMFTR Position */\r
+#define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Msk (0xffffffffUL << ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos)/*!< ETH REMOTE_WAKE_UP_FRAME_FILTER: WKUPFRMFTR Mask */\r
+\r
+/* ---------------------------  ETH_PMT_CONTROL_STATUS  --------------------------- */\r
+#define ETH_PMT_CONTROL_STATUS_PWRDWN_Pos     0                                                       /*!< ETH PMT_CONTROL_STATUS: PWRDWN Position */\r
+#define ETH_PMT_CONTROL_STATUS_PWRDWN_Msk     (0x01UL << ETH_PMT_CONTROL_STATUS_PWRDWN_Pos)           /*!< ETH PMT_CONTROL_STATUS: PWRDWN Mask     */\r
+#define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos   1                                                       /*!< ETH PMT_CONTROL_STATUS: MGKPKTEN Position */\r
+#define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Msk   (0x01UL << ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos)         /*!< ETH PMT_CONTROL_STATUS: MGKPKTEN Mask   */\r
+#define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos   2                                                       /*!< ETH PMT_CONTROL_STATUS: RWKPKTEN Position */\r
+#define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Msk   (0x01UL << ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos)         /*!< ETH PMT_CONTROL_STATUS: RWKPKTEN Mask   */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_4_3_Pos 3                                                     /*!< ETH PMT_CONTROL_STATUS: Reserved_4_3 Position */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_4_3_Msk (0x03UL << ETH_PMT_CONTROL_STATUS_Reserved_4_3_Pos)   /*!< ETH PMT_CONTROL_STATUS: Reserved_4_3 Mask */\r
+#define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos   5                                                       /*!< ETH PMT_CONTROL_STATUS: MGKPRCVD Position */\r
+#define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Msk   (0x01UL << ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos)         /*!< ETH PMT_CONTROL_STATUS: MGKPRCVD Mask   */\r
+#define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos   6                                                       /*!< ETH PMT_CONTROL_STATUS: RWKPRCVD Position */\r
+#define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Msk   (0x01UL << ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos)         /*!< ETH PMT_CONTROL_STATUS: RWKPRCVD Mask   */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_8_7_Pos 7                                                     /*!< ETH PMT_CONTROL_STATUS: Reserved_8_7 Position */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_8_7_Msk (0x03UL << ETH_PMT_CONTROL_STATUS_Reserved_8_7_Pos)   /*!< ETH PMT_CONTROL_STATUS: Reserved_8_7 Mask */\r
+#define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos  9                                                       /*!< ETH PMT_CONTROL_STATUS: GLBLUCAST Position */\r
+#define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Msk  (0x01UL << ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos)        /*!< ETH PMT_CONTROL_STATUS: GLBLUCAST Mask  */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_30_10_Pos 10                                                  /*!< ETH PMT_CONTROL_STATUS: Reserved_30_10 Position */\r
+#define ETH_PMT_CONTROL_STATUS_Reserved_30_10_Msk (0x001fffffUL << ETH_PMT_CONTROL_STATUS_Reserved_30_10_Pos)/*!< ETH PMT_CONTROL_STATUS: Reserved_30_10 Mask */\r
+#define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos 31                                                      /*!< ETH PMT_CONTROL_STATUS: RWKFILTRST Position */\r
+#define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Msk (0x01UL << ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos)       /*!< ETH PMT_CONTROL_STATUS: RWKFILTRST Mask */\r
+\r
+/* ----------------------------  ETH_INTERRUPT_STATUS  ---------------------------- */\r
+#define ETH_INTERRUPT_STATUS_Reserved_2_0_Pos 0                                                       /*!< ETH INTERRUPT_STATUS: Reserved_2_0 Position */\r
+#define ETH_INTERRUPT_STATUS_Reserved_2_0_Msk (0x07UL << ETH_INTERRUPT_STATUS_Reserved_2_0_Pos)       /*!< ETH INTERRUPT_STATUS: Reserved_2_0 Mask */\r
+#define ETH_INTERRUPT_STATUS_PMTIS_Pos        3                                                       /*!< ETH INTERRUPT_STATUS: PMTIS Position    */\r
+#define ETH_INTERRUPT_STATUS_PMTIS_Msk        (0x01UL << ETH_INTERRUPT_STATUS_PMTIS_Pos)              /*!< ETH INTERRUPT_STATUS: PMTIS Mask        */\r
+#define ETH_INTERRUPT_STATUS_MMCIS_Pos        4                                                       /*!< ETH INTERRUPT_STATUS: MMCIS Position    */\r
+#define ETH_INTERRUPT_STATUS_MMCIS_Msk        (0x01UL << ETH_INTERRUPT_STATUS_MMCIS_Pos)              /*!< ETH INTERRUPT_STATUS: MMCIS Mask        */\r
+#define ETH_INTERRUPT_STATUS_MMCRXIS_Pos      5                                                       /*!< ETH INTERRUPT_STATUS: MMCRXIS Position  */\r
+#define ETH_INTERRUPT_STATUS_MMCRXIS_Msk      (0x01UL << ETH_INTERRUPT_STATUS_MMCRXIS_Pos)            /*!< ETH INTERRUPT_STATUS: MMCRXIS Mask      */\r
+#define ETH_INTERRUPT_STATUS_MMCTXIS_Pos      6                                                       /*!< ETH INTERRUPT_STATUS: MMCTXIS Position  */\r
+#define ETH_INTERRUPT_STATUS_MMCTXIS_Msk      (0x01UL << ETH_INTERRUPT_STATUS_MMCTXIS_Pos)            /*!< ETH INTERRUPT_STATUS: MMCTXIS Mask      */\r
+#define ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos    7                                                       /*!< ETH INTERRUPT_STATUS: MMCRXIPIS Position */\r
+#define ETH_INTERRUPT_STATUS_MMCRXIPIS_Msk    (0x01UL << ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos)          /*!< ETH INTERRUPT_STATUS: MMCRXIPIS Mask    */\r
+#define ETH_INTERRUPT_STATUS_Reserved_8_Pos   8                                                       /*!< ETH INTERRUPT_STATUS: Reserved_8 Position */\r
+#define ETH_INTERRUPT_STATUS_Reserved_8_Msk   (0x01UL << ETH_INTERRUPT_STATUS_Reserved_8_Pos)         /*!< ETH INTERRUPT_STATUS: Reserved_8 Mask   */\r
+#define ETH_INTERRUPT_STATUS_TSIS_Pos         9                                                       /*!< ETH INTERRUPT_STATUS: TSIS Position     */\r
+#define ETH_INTERRUPT_STATUS_TSIS_Msk         (0x01UL << ETH_INTERRUPT_STATUS_TSIS_Pos)               /*!< ETH INTERRUPT_STATUS: TSIS Mask         */\r
+#define ETH_INTERRUPT_STATUS_Reserved_10_Pos  10                                                      /*!< ETH INTERRUPT_STATUS: Reserved_10 Position */\r
+#define ETH_INTERRUPT_STATUS_Reserved_10_Msk  (0x01UL << ETH_INTERRUPT_STATUS_Reserved_10_Pos)        /*!< ETH INTERRUPT_STATUS: Reserved_10 Mask  */\r
+#define ETH_INTERRUPT_STATUS_Reserved_31_11_Pos 11                                                    /*!< ETH INTERRUPT_STATUS: Reserved_31_11 Position */\r
+#define ETH_INTERRUPT_STATUS_Reserved_31_11_Msk (0x001fffffUL << ETH_INTERRUPT_STATUS_Reserved_31_11_Pos)/*!< ETH INTERRUPT_STATUS: Reserved_31_11 Mask */\r
+\r
+/* -----------------------------  ETH_INTERRUPT_MASK  ----------------------------- */\r
+#define ETH_INTERRUPT_MASK_Reserved_2_0_Pos   0                                                       /*!< ETH INTERRUPT_MASK: Reserved_2_0 Position */\r
+#define ETH_INTERRUPT_MASK_Reserved_2_0_Msk   (0x07UL << ETH_INTERRUPT_MASK_Reserved_2_0_Pos)         /*!< ETH INTERRUPT_MASK: Reserved_2_0 Mask   */\r
+#define ETH_INTERRUPT_MASK_PMTIM_Pos          3                                                       /*!< ETH INTERRUPT_MASK: PMTIM Position      */\r
+#define ETH_INTERRUPT_MASK_PMTIM_Msk          (0x01UL << ETH_INTERRUPT_MASK_PMTIM_Pos)                /*!< ETH INTERRUPT_MASK: PMTIM Mask          */\r
+#define ETH_INTERRUPT_MASK_Reserved_8_4_Pos   4                                                       /*!< ETH INTERRUPT_MASK: Reserved_8_4 Position */\r
+#define ETH_INTERRUPT_MASK_Reserved_8_4_Msk   (0x1fUL << ETH_INTERRUPT_MASK_Reserved_8_4_Pos)         /*!< ETH INTERRUPT_MASK: Reserved_8_4 Mask   */\r
+#define ETH_INTERRUPT_MASK_TSIM_Pos           9                                                       /*!< ETH INTERRUPT_MASK: TSIM Position       */\r
+#define ETH_INTERRUPT_MASK_TSIM_Msk           (0x01UL << ETH_INTERRUPT_MASK_TSIM_Pos)                 /*!< ETH INTERRUPT_MASK: TSIM Mask           */\r
+#define ETH_INTERRUPT_MASK_Reserved_31_10_Pos 10                                                      /*!< ETH INTERRUPT_MASK: Reserved_31_10 Position */\r
+#define ETH_INTERRUPT_MASK_Reserved_31_10_Msk (0x003fffffUL << ETH_INTERRUPT_MASK_Reserved_31_10_Pos) /*!< ETH INTERRUPT_MASK: Reserved_31_10 Mask */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS0_HIGH  --------------------------- */\r
+#define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos      0                                                       /*!< ETH MAC_ADDRESS0_HIGH: ADDRHI Position  */\r
+#define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Msk      (0x0000ffffUL << ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos)      /*!< ETH MAC_ADDRESS0_HIGH: ADDRHI Mask      */\r
+#define ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Pos 16                                                   /*!< ETH MAC_ADDRESS0_HIGH: Reserved_30_16 Position */\r
+#define ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Msk (0x00007fffUL << ETH_MAC_ADDRESS0_HIGH_Reserved_30_16_Pos)/*!< ETH MAC_ADDRESS0_HIGH: Reserved_30_16 Mask */\r
+#define ETH_MAC_ADDRESS0_HIGH_AE_Pos          31                                                      /*!< ETH MAC_ADDRESS0_HIGH: AE Position      */\r
+#define ETH_MAC_ADDRESS0_HIGH_AE_Msk          (0x01UL << ETH_MAC_ADDRESS0_HIGH_AE_Pos)                /*!< ETH MAC_ADDRESS0_HIGH: AE Mask          */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS0_LOW  ---------------------------- */\r
+#define ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos       0                                                       /*!< ETH MAC_ADDRESS0_LOW: ADDRLO Position   */\r
+#define ETH_MAC_ADDRESS0_LOW_ADDRLO_Msk       (0xffffffffUL << ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos)       /*!< ETH MAC_ADDRESS0_LOW: ADDRLO Mask       */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS1_HIGH  --------------------------- */\r
+#define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos      0                                                       /*!< ETH MAC_ADDRESS1_HIGH: ADDRHI Position  */\r
+#define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Msk      (0x0000ffffUL << ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos)      /*!< ETH MAC_ADDRESS1_HIGH: ADDRHI Mask      */\r
+#define ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Pos 16                                                   /*!< ETH MAC_ADDRESS1_HIGH: Reserved_23_16 Position */\r
+#define ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Msk (0x000000ffUL << ETH_MAC_ADDRESS1_HIGH_Reserved_23_16_Pos)/*!< ETH MAC_ADDRESS1_HIGH: Reserved_23_16 Mask */\r
+#define ETH_MAC_ADDRESS1_HIGH_MBC_Pos         24                                                      /*!< ETH MAC_ADDRESS1_HIGH: MBC Position     */\r
+#define ETH_MAC_ADDRESS1_HIGH_MBC_Msk         (0x3fUL << ETH_MAC_ADDRESS1_HIGH_MBC_Pos)               /*!< ETH MAC_ADDRESS1_HIGH: MBC Mask         */\r
+#define ETH_MAC_ADDRESS1_HIGH_SA_Pos          30                                                      /*!< ETH MAC_ADDRESS1_HIGH: SA Position      */\r
+#define ETH_MAC_ADDRESS1_HIGH_SA_Msk          (0x01UL << ETH_MAC_ADDRESS1_HIGH_SA_Pos)                /*!< ETH MAC_ADDRESS1_HIGH: SA Mask          */\r
+#define ETH_MAC_ADDRESS1_HIGH_AE_Pos          31                                                      /*!< ETH MAC_ADDRESS1_HIGH: AE Position      */\r
+#define ETH_MAC_ADDRESS1_HIGH_AE_Msk          (0x01UL << ETH_MAC_ADDRESS1_HIGH_AE_Pos)                /*!< ETH MAC_ADDRESS1_HIGH: AE Mask          */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS1_LOW  ---------------------------- */\r
+#define ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos       0                                                       /*!< ETH MAC_ADDRESS1_LOW: ADDRLO Position   */\r
+#define ETH_MAC_ADDRESS1_LOW_ADDRLO_Msk       (0xffffffffUL << ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos)       /*!< ETH MAC_ADDRESS1_LOW: ADDRLO Mask       */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS2_HIGH  --------------------------- */\r
+#define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos      0                                                       /*!< ETH MAC_ADDRESS2_HIGH: ADDRHI Position  */\r
+#define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Msk      (0x0000ffffUL << ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos)      /*!< ETH MAC_ADDRESS2_HIGH: ADDRHI Mask      */\r
+#define ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Pos 16                                                   /*!< ETH MAC_ADDRESS2_HIGH: Reserved_23_16 Position */\r
+#define ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Msk (0x000000ffUL << ETH_MAC_ADDRESS2_HIGH_Reserved_23_16_Pos)/*!< ETH MAC_ADDRESS2_HIGH: Reserved_23_16 Mask */\r
+#define ETH_MAC_ADDRESS2_HIGH_MBC_Pos         24                                                      /*!< ETH MAC_ADDRESS2_HIGH: MBC Position     */\r
+#define ETH_MAC_ADDRESS2_HIGH_MBC_Msk         (0x3fUL << ETH_MAC_ADDRESS2_HIGH_MBC_Pos)               /*!< ETH MAC_ADDRESS2_HIGH: MBC Mask         */\r
+#define ETH_MAC_ADDRESS2_HIGH_SA_Pos          30                                                      /*!< ETH MAC_ADDRESS2_HIGH: SA Position      */\r
+#define ETH_MAC_ADDRESS2_HIGH_SA_Msk          (0x01UL << ETH_MAC_ADDRESS2_HIGH_SA_Pos)                /*!< ETH MAC_ADDRESS2_HIGH: SA Mask          */\r
+#define ETH_MAC_ADDRESS2_HIGH_AE_Pos          31                                                      /*!< ETH MAC_ADDRESS2_HIGH: AE Position      */\r
+#define ETH_MAC_ADDRESS2_HIGH_AE_Msk          (0x01UL << ETH_MAC_ADDRESS2_HIGH_AE_Pos)                /*!< ETH MAC_ADDRESS2_HIGH: AE Mask          */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS2_LOW  ---------------------------- */\r
+#define ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos       0                                                       /*!< ETH MAC_ADDRESS2_LOW: ADDRLO Position   */\r
+#define ETH_MAC_ADDRESS2_LOW_ADDRLO_Msk       (0xffffffffUL << ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos)       /*!< ETH MAC_ADDRESS2_LOW: ADDRLO Mask       */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS3_HIGH  --------------------------- */\r
+#define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos      0                                                       /*!< ETH MAC_ADDRESS3_HIGH: ADDRHI Position  */\r
+#define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Msk      (0x0000ffffUL << ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos)      /*!< ETH MAC_ADDRESS3_HIGH: ADDRHI Mask      */\r
+#define ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Pos 16                                                   /*!< ETH MAC_ADDRESS3_HIGH: Reserved_23_16 Position */\r
+#define ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Msk (0x000000ffUL << ETH_MAC_ADDRESS3_HIGH_Reserved_23_16_Pos)/*!< ETH MAC_ADDRESS3_HIGH: Reserved_23_16 Mask */\r
+#define ETH_MAC_ADDRESS3_HIGH_MBC_Pos         24                                                      /*!< ETH MAC_ADDRESS3_HIGH: MBC Position     */\r
+#define ETH_MAC_ADDRESS3_HIGH_MBC_Msk         (0x3fUL << ETH_MAC_ADDRESS3_HIGH_MBC_Pos)               /*!< ETH MAC_ADDRESS3_HIGH: MBC Mask         */\r
+#define ETH_MAC_ADDRESS3_HIGH_SA_Pos          30                                                      /*!< ETH MAC_ADDRESS3_HIGH: SA Position      */\r
+#define ETH_MAC_ADDRESS3_HIGH_SA_Msk          (0x01UL << ETH_MAC_ADDRESS3_HIGH_SA_Pos)                /*!< ETH MAC_ADDRESS3_HIGH: SA Mask          */\r
+#define ETH_MAC_ADDRESS3_HIGH_AE_Pos          31                                                      /*!< ETH MAC_ADDRESS3_HIGH: AE Position      */\r
+#define ETH_MAC_ADDRESS3_HIGH_AE_Msk          (0x01UL << ETH_MAC_ADDRESS3_HIGH_AE_Pos)                /*!< ETH MAC_ADDRESS3_HIGH: AE Mask          */\r
+\r
+/* ----------------------------  ETH_MAC_ADDRESS3_LOW  ---------------------------- */\r
+#define ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos       0                                                       /*!< ETH MAC_ADDRESS3_LOW: ADDRLO Position   */\r
+#define ETH_MAC_ADDRESS3_LOW_ADDRLO_Msk       (0xffffffffUL << ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos)       /*!< ETH MAC_ADDRESS3_LOW: ADDRLO Mask       */\r
+\r
+/* -------------------------------  ETH_MMC_CONTROL  ------------------------------ */\r
+#define ETH_MMC_CONTROL_CNTRST_Pos            0                                                       /*!< ETH MMC_CONTROL: CNTRST Position        */\r
+#define ETH_MMC_CONTROL_CNTRST_Msk            (0x01UL << ETH_MMC_CONTROL_CNTRST_Pos)                  /*!< ETH MMC_CONTROL: CNTRST Mask            */\r
+#define ETH_MMC_CONTROL_CNTSTOPRO_Pos         1                                                       /*!< ETH MMC_CONTROL: CNTSTOPRO Position     */\r
+#define ETH_MMC_CONTROL_CNTSTOPRO_Msk         (0x01UL << ETH_MMC_CONTROL_CNTSTOPRO_Pos)               /*!< ETH MMC_CONTROL: CNTSTOPRO Mask         */\r
+#define ETH_MMC_CONTROL_RSTONRD_Pos           2                                                       /*!< ETH MMC_CONTROL: RSTONRD Position       */\r
+#define ETH_MMC_CONTROL_RSTONRD_Msk           (0x01UL << ETH_MMC_CONTROL_RSTONRD_Pos)                 /*!< ETH MMC_CONTROL: RSTONRD Mask           */\r
+#define ETH_MMC_CONTROL_CNTFREEZ_Pos          3                                                       /*!< ETH MMC_CONTROL: CNTFREEZ Position      */\r
+#define ETH_MMC_CONTROL_CNTFREEZ_Msk          (0x01UL << ETH_MMC_CONTROL_CNTFREEZ_Pos)                /*!< ETH MMC_CONTROL: CNTFREEZ Mask          */\r
+#define ETH_MMC_CONTROL_CNTPRST_Pos           4                                                       /*!< ETH MMC_CONTROL: CNTPRST Position       */\r
+#define ETH_MMC_CONTROL_CNTPRST_Msk           (0x01UL << ETH_MMC_CONTROL_CNTPRST_Pos)                 /*!< ETH MMC_CONTROL: CNTPRST Mask           */\r
+#define ETH_MMC_CONTROL_CNTPRSTLVL_Pos        5                                                       /*!< ETH MMC_CONTROL: CNTPRSTLVL Position    */\r
+#define ETH_MMC_CONTROL_CNTPRSTLVL_Msk        (0x01UL << ETH_MMC_CONTROL_CNTPRSTLVL_Pos)              /*!< ETH MMC_CONTROL: CNTPRSTLVL Mask        */\r
+#define ETH_MMC_CONTROL_Reserved_7_6_Pos      6                                                       /*!< ETH MMC_CONTROL: Reserved_7_6 Position  */\r
+#define ETH_MMC_CONTROL_Reserved_7_6_Msk      (0x03UL << ETH_MMC_CONTROL_Reserved_7_6_Pos)            /*!< ETH MMC_CONTROL: Reserved_7_6 Mask      */\r
+#define ETH_MMC_CONTROL_UCDBC_Pos             8                                                       /*!< ETH MMC_CONTROL: UCDBC Position         */\r
+#define ETH_MMC_CONTROL_UCDBC_Msk             (0x01UL << ETH_MMC_CONTROL_UCDBC_Pos)                   /*!< ETH MMC_CONTROL: UCDBC Mask             */\r
+#define ETH_MMC_CONTROL_Reserved_31_9_Pos     9                                                       /*!< ETH MMC_CONTROL: Reserved_31_9 Position */\r
+#define ETH_MMC_CONTROL_Reserved_31_9_Msk     (0x007fffffUL << ETH_MMC_CONTROL_Reserved_31_9_Pos)     /*!< ETH MMC_CONTROL: Reserved_31_9 Mask     */\r
+\r
+/* --------------------------  ETH_MMC_RECEIVE_INTERRUPT  ------------------------- */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos 0                                                     /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBFRMIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBFRMIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos 1                                                     /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBOCTIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXGBOCTIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos 2                                                      /*!< ETH MMC_RECEIVE_INTERRUPT: RXGOCTIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos)     /*!< ETH MMC_RECEIVE_INTERRUPT: RXGOCTIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos 3                                                      /*!< ETH MMC_RECEIVE_INTERRUPT: RXBCGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos)     /*!< ETH MMC_RECEIVE_INTERRUPT: RXBCGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos 4                                                      /*!< ETH MMC_RECEIVE_INTERRUPT: RXMCGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos)     /*!< ETH MMC_RECEIVE_INTERRUPT: RXMCGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos 5                                                    /*!< ETH MMC_RECEIVE_INTERRUPT: RXCRCERFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXCRCERFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos 6                                                   /*!< ETH MMC_RECEIVE_INTERRUPT: RXALGNERFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXALGNERFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos 7                                                     /*!< ETH MMC_RECEIVE_INTERRUPT: RXRUNTFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXRUNTFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos 8                                                    /*!< ETH MMC_RECEIVE_INTERRUPT: RXJABERFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXJABERFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos 9                                                   /*!< ETH MMC_RECEIVE_INTERRUPT: RXUSIZEGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXUSIZEGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos 10                                                  /*!< ETH MMC_RECEIVE_INTERRUPT: RXOSIZEGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXOSIZEGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos 11                                                 /*!< ETH MMC_RECEIVE_INTERRUPT: RX64OCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX64OCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos 12                                             /*!< ETH MMC_RECEIVE_INTERRUPT: RX65T127OCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX65T127OCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos 13                                            /*!< ETH MMC_RECEIVE_INTERRUPT: RX128T255OCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX128T255OCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos 14                                            /*!< ETH MMC_RECEIVE_INTERRUPT: RX256T511OCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX256T511OCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos 15                                           /*!< ETH MMC_RECEIVE_INTERRUPT: RX512T1023OCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX512T1023OCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos 16                                           /*!< ETH MMC_RECEIVE_INTERRUPT: RX1024TMAXOCTGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RX1024TMAXOCTGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos 17                                                     /*!< ETH MMC_RECEIVE_INTERRUPT: RXUCGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos)     /*!< ETH MMC_RECEIVE_INTERRUPT: RXUCGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos 18                                                   /*!< ETH MMC_RECEIVE_INTERRUPT: RXLENERFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos) /*!< ETH MMC_RECEIVE_INTERRUPT: RXLENERFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos 19                                                  /*!< ETH MMC_RECEIVE_INTERRUPT: RXORANGEFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXORANGEFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos 20                                                    /*!< ETH MMC_RECEIVE_INTERRUPT: RXPAUSFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXPAUSFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos 21                                                     /*!< ETH MMC_RECEIVE_INTERRUPT: RXFOVFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos)     /*!< ETH MMC_RECEIVE_INTERRUPT: RXFOVFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos 22                                                  /*!< ETH MMC_RECEIVE_INTERRUPT: RXVLANGBFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXVLANGBFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos 23                                                    /*!< ETH MMC_RECEIVE_INTERRUPT: RXWDOGFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXWDOGFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos 24                                                  /*!< ETH MMC_RECEIVE_INTERRUPT: RXRCVERRFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: RXRCVERRFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos 25                                                    /*!< ETH MMC_RECEIVE_INTERRUPT: RXCTRLFIS Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos)   /*!< ETH MMC_RECEIVE_INTERRUPT: RXCTRLFIS Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Pos 26                                               /*!< ETH MMC_RECEIVE_INTERRUPT: Reserved_31_26 Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Msk (0x3fUL << ETH_MMC_RECEIVE_INTERRUPT_Reserved_31_26_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT: Reserved_31_26 Mask */\r
+\r
+/* -------------------------  ETH_MMC_TRANSMIT_INTERRUPT  ------------------------- */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos 0                                                    /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBOCTIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBOCTIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos 1                                                    /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBFRMIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGBFRMIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos 2                                                     /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos)   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos 3                                                     /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos)   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos 4                                                 /*!< ETH MMC_TRANSMIT_INTERRUPT: TX64OCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX64OCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos 5                                             /*!< ETH MMC_TRANSMIT_INTERRUPT: TX65T127OCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX65T127OCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos 6                                            /*!< ETH MMC_TRANSMIT_INTERRUPT: TX128T255OCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX128T255OCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos 7                                            /*!< ETH MMC_TRANSMIT_INTERRUPT: TX256T511OCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX256T511OCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos 8                                           /*!< ETH MMC_TRANSMIT_INTERRUPT: TX512T1023OCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX512T1023OCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos 9                                           /*!< ETH MMC_TRANSMIT_INTERRUPT: TX1024TMAXOCTGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TX1024TMAXOCTGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos 10                                                   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUCGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUCGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos 11                                                   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos 12                                                   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGBFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXBCGBFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos 13                                                /*!< ETH MMC_TRANSMIT_INTERRUPT: TXUFLOWERFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXUFLOWERFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos 14                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXSCOLGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXSCOLGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos 15                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCOLGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXMCOLGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos 16                                                    /*!< ETH MMC_TRANSMIT_INTERRUPT: TXDEFFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos)   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXDEFFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos 17                                                 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXLATCOLFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXLATCOLFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos 18                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXCOLFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXCOLFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos 19                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXCARERFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXCARERFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos 20                                                    /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGOCTIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos)   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGOCTIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos 21                                                    /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGFRMIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos)   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXGFRMIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos 22                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXDEFFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXEXDEFFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos 23                                                   /*!< ETH MMC_TRANSMIT_INTERRUPT: TXPAUSFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos) /*!< ETH MMC_TRANSMIT_INTERRUPT: TXPAUSFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos 24                                                  /*!< ETH MMC_TRANSMIT_INTERRUPT: TXVLANGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXVLANGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos 25                                                 /*!< ETH MMC_TRANSMIT_INTERRUPT: TXOSIZEGFIS Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: TXOSIZEGFIS Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Pos 26                                              /*!< ETH MMC_TRANSMIT_INTERRUPT: Reserved_31_26 Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Msk (0x3fUL << ETH_MMC_TRANSMIT_INTERRUPT_Reserved_31_26_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT: Reserved_31_26 Mask */\r
+\r
+/* -----------------------  ETH_MMC_RECEIVE_INTERRUPT_MASK  ----------------------- */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos 0                                                /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBFRMIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBFRMIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos 1                                                /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBOCTIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGBOCTIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos 2                                                 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGOCTIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXGOCTIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos 3                                                 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXBCGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXBCGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos 4                                                 /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXMCGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXMCGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos 5                                               /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCRCERFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCRCERFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos 6                                              /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXALGNERFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXALGNERFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos 7                                                /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRUNTFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRUNTFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos 8                                               /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXJABERFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXJABERFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos 9                                              /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUSIZEGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUSIZEGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos 10                                             /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXOSIZEGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXOSIZEGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos 11                                            /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX64OCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX64OCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos 12                                        /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX65T127OCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX65T127OCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos 13                                       /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX128T255OCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX128T255OCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos 14                                       /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX256T511OCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX256T511OCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos 15                                      /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX512T1023OCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX512T1023OCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos 16                                      /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX1024TMAXOCTGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RX1024TMAXOCTGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos 17                                                /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUCGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXUCGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos 18                                              /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXLENERFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXLENERFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos 19                                             /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXORANGEFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXORANGEFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos 20                                               /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXPAUSFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXPAUSFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos 21                                                /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXFOVFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXFOVFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos 22                                             /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXVLANGBFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXVLANGBFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos 23                                               /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXWDOGFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXWDOGFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos 24                                             /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRCVERRFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXRCVERRFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos 25                                               /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCTRLFIM Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Msk (0x01UL << ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: RXCTRLFIM Mask */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Pos 26                                          /*!< ETH MMC_RECEIVE_INTERRUPT_MASK: Reserved_31_26 Position */\r
+#define ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Msk (0x3fUL << ETH_MMC_RECEIVE_INTERRUPT_MASK_Reserved_31_26_Pos)/*!< ETH MMC_RECEIVE_INTERRUPT_MASK: Reserved_31_26 Mask */\r
+\r
+/* -----------------------  ETH_MMC_TRANSMIT_INTERRUPT_MASK  ---------------------- */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos 0                                               /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBOCTIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBOCTIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos 1                                               /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBFRMIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGBFRMIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos 2                                                /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos 3                                                /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos 4                                            /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX64OCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX64OCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos 5                                        /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX65T127OCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX65T127OCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos 6                                       /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX128T255OCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX128T255OCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos 7                                       /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX256T511OCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX256T511OCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos 8                                      /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX512T1023OCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX512T1023OCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos 9                                      /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX1024TMAXOCTGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TX1024TMAXOCTGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos 10                                              /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUCGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUCGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos 11                                              /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos 12                                              /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGBFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXBCGBFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos 13                                           /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUFLOWERFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXUFLOWERFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos 14                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXSCOLGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXSCOLGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos 15                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCOLGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXMCOLGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos 16                                               /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXDEFFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXDEFFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos 17                                            /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXLATCOLFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXLATCOLFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos 18                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXCOLFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXCOLFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos 19                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXCARERFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXCARERFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos 20                                               /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGOCTIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGOCTIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos 21                                               /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGFRMIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXGFRMIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos 22                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXDEFFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXEXDEFFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos 23                                              /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXPAUSFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXPAUSFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos 24                                             /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXVLANGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXVLANGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos 25                                            /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXOSIZEGFIM Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Msk (0x01UL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: TXOSIZEGFIM Mask */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Pos 26                                         /*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: Reserved_31_26 Position */\r
+#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Msk (0x3fUL << ETH_MMC_TRANSMIT_INTERRUPT_MASK_Reserved_31_26_Pos)/*!< ETH MMC_TRANSMIT_INTERRUPT_MASK: Reserved_31_26 Mask */\r
+\r
+/* -------------------------  ETH_TX_OCTET_COUNT_GOOD_BAD  ------------------------ */\r
+#define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos 0                                                     /*!< ETH TX_OCTET_COUNT_GOOD_BAD: TXOCTGB Position */\r
+#define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Msk (0xffffffffUL << ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos)/*!< ETH TX_OCTET_COUNT_GOOD_BAD: TXOCTGB Mask */\r
+\r
+/* -------------------------  ETH_TX_FRAME_COUNT_GOOD_BAD  ------------------------ */\r
+#define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos 0                                                     /*!< ETH TX_FRAME_COUNT_GOOD_BAD: TXFRMGB Position */\r
+#define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Msk (0xffffffffUL << ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos)/*!< ETH TX_FRAME_COUNT_GOOD_BAD: TXFRMGB Mask */\r
+\r
+/* ------------------------  ETH_TX_BROADCAST_FRAMES_GOOD  ------------------------ */\r
+#define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos 0                                                   /*!< ETH TX_BROADCAST_FRAMES_GOOD: TXBCASTG Position */\r
+#define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Msk (0xffffffffUL << ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos)/*!< ETH TX_BROADCAST_FRAMES_GOOD: TXBCASTG Mask */\r
+\r
+/* ------------------------  ETH_TX_MULTICAST_FRAMES_GOOD  ------------------------ */\r
+#define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos 0                                                   /*!< ETH TX_MULTICAST_FRAMES_GOOD: TXMCASTG Position */\r
+#define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Msk (0xffffffffUL << ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos)/*!< ETH TX_MULTICAST_FRAMES_GOOD: TXMCASTG Mask */\r
+\r
+/* -----------------------  ETH_TX_64OCTETS_FRAMES_GOOD_BAD  ---------------------- */\r
+#define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos 0                                               /*!< ETH TX_64OCTETS_FRAMES_GOOD_BAD: TX64OCTGB Position */\r
+#define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Msk (0xffffffffUL << ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos)/*!< ETH TX_64OCTETS_FRAMES_GOOD_BAD: TX64OCTGB Mask */\r
+\r
+/* --------------------  ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD  -------------------- */\r
+#define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos 0                                      /*!< ETH TX_65TO127OCTETS_FRAMES_GOOD_BAD: TX65_127OCTGB Position */\r
+#define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Msk (0xffffffffUL << ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos)/*!< ETH TX_65TO127OCTETS_FRAMES_GOOD_BAD: TX65_127OCTGB Mask */\r
+\r
+/* --------------------  ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos 0                                    /*!< ETH TX_128TO255OCTETS_FRAMES_GOOD_BAD: TX128_255OCTGB Position */\r
+#define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Msk (0xffffffffUL << ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos)/*!< ETH TX_128TO255OCTETS_FRAMES_GOOD_BAD: TX128_255OCTGB Mask */\r
+\r
+/* --------------------  ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos 0                                    /*!< ETH TX_256TO511OCTETS_FRAMES_GOOD_BAD: TX256_511OCTGB Position */\r
+#define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Msk (0xffffffffUL << ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos)/*!< ETH TX_256TO511OCTETS_FRAMES_GOOD_BAD: TX256_511OCTGB Mask */\r
+\r
+/* -------------------  ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos 0                                  /*!< ETH TX_512TO1023OCTETS_FRAMES_GOOD_BAD: TX512_1023OCTGB Position */\r
+#define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Msk (0xffffffffUL << ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos)/*!< ETH TX_512TO1023OCTETS_FRAMES_GOOD_BAD: TX512_1023OCTGB Mask */\r
+\r
+/* -------------------  ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos 0                                  /*!< ETH TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: TX1024_MAXOCTGB Position */\r
+#define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Msk (0xffffffffUL << ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos)/*!< ETH TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: TX1024_MAXOCTGB Mask */\r
+\r
+/* -----------------------  ETH_TX_UNICAST_FRAMES_GOOD_BAD  ----------------------- */\r
+#define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos 0                                                /*!< ETH TX_UNICAST_FRAMES_GOOD_BAD: TXUCASTGB Position */\r
+#define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Msk (0xffffffffUL << ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos)/*!< ETH TX_UNICAST_FRAMES_GOOD_BAD: TXUCASTGB Mask */\r
+\r
+/* ----------------------  ETH_TX_MULTICAST_FRAMES_GOOD_BAD  ---------------------- */\r
+#define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos 0                                              /*!< ETH TX_MULTICAST_FRAMES_GOOD_BAD: TXMCASTGB Position */\r
+#define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Msk (0xffffffffUL << ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos)/*!< ETH TX_MULTICAST_FRAMES_GOOD_BAD: TXMCASTGB Mask */\r
+\r
+/* ----------------------  ETH_TX_BROADCAST_FRAMES_GOOD_BAD  ---------------------- */\r
+#define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos 0                                              /*!< ETH TX_BROADCAST_FRAMES_GOOD_BAD: TXBCASTGB Position */\r
+#define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Msk (0xffffffffUL << ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos)/*!< ETH TX_BROADCAST_FRAMES_GOOD_BAD: TXBCASTGB Mask */\r
+\r
+/* ------------------------  ETH_TX_UNDERFLOW_ERROR_FRAMES  ----------------------- */\r
+#define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos 0                                                 /*!< ETH TX_UNDERFLOW_ERROR_FRAMES: TXUNDRFLW Position */\r
+#define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Msk (0xffffffffUL << ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos)/*!< ETH TX_UNDERFLOW_ERROR_FRAMES: TXUNDRFLW Mask */\r
+\r
+/* ---------------------  ETH_TX_SINGLE_COLLISION_GOOD_FRAMES  -------------------- */\r
+#define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos 0                                          /*!< ETH TX_SINGLE_COLLISION_GOOD_FRAMES: TXSNGLCOLG Position */\r
+#define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Msk (0xffffffffUL << ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos)/*!< ETH TX_SINGLE_COLLISION_GOOD_FRAMES: TXSNGLCOLG Mask */\r
+\r
+/* --------------------  ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES  ------------------- */\r
+#define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos 0                                        /*!< ETH TX_MULTIPLE_COLLISION_GOOD_FRAMES: TXMULTCOLG Position */\r
+#define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Msk (0xffffffffUL << ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos)/*!< ETH TX_MULTIPLE_COLLISION_GOOD_FRAMES: TXMULTCOLG Mask */\r
+\r
+/* ---------------------------  ETH_TX_DEFERRED_FRAMES  --------------------------- */\r
+#define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos    0                                                       /*!< ETH TX_DEFERRED_FRAMES: TXDEFRD Position */\r
+#define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Msk    (0xffffffffUL << ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos)    /*!< ETH TX_DEFERRED_FRAMES: TXDEFRD Mask    */\r
+\r
+/* ------------------------  ETH_TX_LATE_COLLISION_FRAMES  ------------------------ */\r
+#define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos 0                                                  /*!< ETH TX_LATE_COLLISION_FRAMES: TXLATECOL Position */\r
+#define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Msk (0xffffffffUL << ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos)/*!< ETH TX_LATE_COLLISION_FRAMES: TXLATECOL Mask */\r
+\r
+/* ----------------------  ETH_TX_EXCESSIVE_COLLISION_FRAMES  --------------------- */\r
+#define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos 0                                              /*!< ETH TX_EXCESSIVE_COLLISION_FRAMES: TXEXSCOL Position */\r
+#define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Msk (0xffffffffUL << ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos)/*!< ETH TX_EXCESSIVE_COLLISION_FRAMES: TXEXSCOL Mask */\r
+\r
+/* -------------------------  ETH_TX_CARRIER_ERROR_FRAMES  ------------------------ */\r
+#define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos 0                                                      /*!< ETH TX_CARRIER_ERROR_FRAMES: TXCARR Position */\r
+#define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Msk (0xffffffffUL << ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos)/*!< ETH TX_CARRIER_ERROR_FRAMES: TXCARR Mask */\r
+\r
+/* ---------------------------  ETH_TX_OCTET_COUNT_GOOD  -------------------------- */\r
+#define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos    0                                                       /*!< ETH TX_OCTET_COUNT_GOOD: TXOCTG Position */\r
+#define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Msk    (0xffffffffUL << ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos)    /*!< ETH TX_OCTET_COUNT_GOOD: TXOCTG Mask    */\r
+\r
+/* ---------------------------  ETH_TX_FRAME_COUNT_GOOD  -------------------------- */\r
+#define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos    0                                                       /*!< ETH TX_FRAME_COUNT_GOOD: TXFRMG Position */\r
+#define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Msk    (0xffffffffUL << ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos)    /*!< ETH TX_FRAME_COUNT_GOOD: TXFRMG Mask    */\r
+\r
+/* -----------------------  ETH_TX_EXCESSIVE_DEFERRAL_ERROR  ---------------------- */\r
+#define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos 0                                                /*!< ETH TX_EXCESSIVE_DEFERRAL_ERROR: TXEXSDEF Position */\r
+#define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Msk (0xffffffffUL << ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos)/*!< ETH TX_EXCESSIVE_DEFERRAL_ERROR: TXEXSDEF Mask */\r
+\r
+/* -----------------------------  ETH_TX_PAUSE_FRAMES  ---------------------------- */\r
+#define ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos       0                                                       /*!< ETH TX_PAUSE_FRAMES: TXPAUSE Position   */\r
+#define ETH_TX_PAUSE_FRAMES_TXPAUSE_Msk       (0xffffffffUL << ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos)       /*!< ETH TX_PAUSE_FRAMES: TXPAUSE Mask       */\r
+\r
+/* ---------------------------  ETH_TX_VLAN_FRAMES_GOOD  -------------------------- */\r
+#define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos   0                                                       /*!< ETH TX_VLAN_FRAMES_GOOD: TXVLANG Position */\r
+#define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Msk   (0xffffffffUL << ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos)   /*!< ETH TX_VLAN_FRAMES_GOOD: TXVLANG Mask   */\r
+\r
+/* --------------------------  ETH_TX_OSIZE_FRAMES_GOOD  -------------------------- */\r
+#define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos  0                                                       /*!< ETH TX_OSIZE_FRAMES_GOOD: TXOSIZG Position */\r
+#define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Msk  (0xffffffffUL << ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos)  /*!< ETH TX_OSIZE_FRAMES_GOOD: TXOSIZG Mask  */\r
+\r
+/* ------------------------  ETH_RX_FRAMES_COUNT_GOOD_BAD  ------------------------ */\r
+#define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos 0                                                    /*!< ETH RX_FRAMES_COUNT_GOOD_BAD: RXFRMGB Position */\r
+#define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Msk (0xffffffffUL << ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos)/*!< ETH RX_FRAMES_COUNT_GOOD_BAD: RXFRMGB Mask */\r
+\r
+/* -------------------------  ETH_RX_OCTET_COUNT_GOOD_BAD  ------------------------ */\r
+#define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos 0                                                     /*!< ETH RX_OCTET_COUNT_GOOD_BAD: RXOCTGB Position */\r
+#define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Msk (0xffffffffUL << ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos)/*!< ETH RX_OCTET_COUNT_GOOD_BAD: RXOCTGB Mask */\r
+\r
+/* ---------------------------  ETH_RX_OCTET_COUNT_GOOD  -------------------------- */\r
+#define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos    0                                                       /*!< ETH RX_OCTET_COUNT_GOOD: RXOCTG Position */\r
+#define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Msk    (0xffffffffUL << ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos)    /*!< ETH RX_OCTET_COUNT_GOOD: RXOCTG Mask    */\r
+\r
+/* ------------------------  ETH_RX_BROADCAST_FRAMES_GOOD  ------------------------ */\r
+#define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos 0                                                   /*!< ETH RX_BROADCAST_FRAMES_GOOD: RXBCASTG Position */\r
+#define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Msk (0xffffffffUL << ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos)/*!< ETH RX_BROADCAST_FRAMES_GOOD: RXBCASTG Mask */\r
+\r
+/* ------------------------  ETH_RX_MULTICAST_FRAMES_GOOD  ------------------------ */\r
+#define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos 0                                                   /*!< ETH RX_MULTICAST_FRAMES_GOOD: RXMCASTG Position */\r
+#define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Msk (0xffffffffUL << ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos)/*!< ETH RX_MULTICAST_FRAMES_GOOD: RXMCASTG Mask */\r
+\r
+/* ---------------------------  ETH_RX_CRC_ERROR_FRAMES  -------------------------- */\r
+#define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos  0                                                       /*!< ETH RX_CRC_ERROR_FRAMES: RXCRCERR Position */\r
+#define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Msk  (0xffffffffUL << ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos)  /*!< ETH RX_CRC_ERROR_FRAMES: RXCRCERR Mask  */\r
+\r
+/* ------------------------  ETH_RX_ALIGNMENT_ERROR_FRAMES  ----------------------- */\r
+#define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos 0                                                 /*!< ETH RX_ALIGNMENT_ERROR_FRAMES: RXALGNERR Position */\r
+#define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Msk (0xffffffffUL << ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos)/*!< ETH RX_ALIGNMENT_ERROR_FRAMES: RXALGNERR Mask */\r
+\r
+/* --------------------------  ETH_RX_RUNT_ERROR_FRAMES  -------------------------- */\r
+#define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos 0                                                      /*!< ETH RX_RUNT_ERROR_FRAMES: RXRUNTERR Position */\r
+#define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Msk (0xffffffffUL << ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos)/*!< ETH RX_RUNT_ERROR_FRAMES: RXRUNTERR Mask */\r
+\r
+/* -------------------------  ETH_RX_JABBER_ERROR_FRAMES  ------------------------- */\r
+#define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos 0                                                     /*!< ETH RX_JABBER_ERROR_FRAMES: RXJABERR Position */\r
+#define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Msk (0xffffffffUL << ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos)/*!< ETH RX_JABBER_ERROR_FRAMES: RXJABERR Mask */\r
+\r
+/* ------------------------  ETH_RX_UNDERSIZE_FRAMES_GOOD  ------------------------ */\r
+#define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos 0                                                 /*!< ETH RX_UNDERSIZE_FRAMES_GOOD: RXUNDERSZG Position */\r
+#define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Msk (0xffffffffUL << ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos)/*!< ETH RX_UNDERSIZE_FRAMES_GOOD: RXUNDERSZG Mask */\r
+\r
+/* -------------------------  ETH_RX_OVERSIZE_FRAMES_GOOD  ------------------------ */\r
+#define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos 0                                                   /*!< ETH RX_OVERSIZE_FRAMES_GOOD: RXOVERSZG Position */\r
+#define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Msk (0xffffffffUL << ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos)/*!< ETH RX_OVERSIZE_FRAMES_GOOD: RXOVERSZG Mask */\r
+\r
+/* -----------------------  ETH_RX_64OCTETS_FRAMES_GOOD_BAD  ---------------------- */\r
+#define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos 0                                               /*!< ETH RX_64OCTETS_FRAMES_GOOD_BAD: RX64OCTGB Position */\r
+#define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Msk (0xffffffffUL << ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos)/*!< ETH RX_64OCTETS_FRAMES_GOOD_BAD: RX64OCTGB Mask */\r
+\r
+/* --------------------  ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD  -------------------- */\r
+#define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos 0                                      /*!< ETH RX_65TO127OCTETS_FRAMES_GOOD_BAD: RX65_127OCTGB Position */\r
+#define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Msk (0xffffffffUL << ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos)/*!< ETH RX_65TO127OCTETS_FRAMES_GOOD_BAD: RX65_127OCTGB Mask */\r
+\r
+/* --------------------  ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos 0                                    /*!< ETH RX_128TO255OCTETS_FRAMES_GOOD_BAD: RX128_255OCTGB Position */\r
+#define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Msk (0xffffffffUL << ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos)/*!< ETH RX_128TO255OCTETS_FRAMES_GOOD_BAD: RX128_255OCTGB Mask */\r
+\r
+/* --------------------  ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos 0                                    /*!< ETH RX_256TO511OCTETS_FRAMES_GOOD_BAD: RX256_511OCTGB Position */\r
+#define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Msk (0xffffffffUL << ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos)/*!< ETH RX_256TO511OCTETS_FRAMES_GOOD_BAD: RX256_511OCTGB Mask */\r
+\r
+/* -------------------  ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos 0                                  /*!< ETH RX_512TO1023OCTETS_FRAMES_GOOD_BAD: RX512_1023OCTGB Position */\r
+#define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Msk (0xffffffffUL << ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos)/*!< ETH RX_512TO1023OCTETS_FRAMES_GOOD_BAD: RX512_1023OCTGB Mask */\r
+\r
+/* -------------------  ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD  ------------------- */\r
+#define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos 0                                  /*!< ETH RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: RX1024_MAXOCTGB Position */\r
+#define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Msk (0xffffffffUL << ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos)/*!< ETH RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD: RX1024_MAXOCTGB Mask */\r
+\r
+/* -------------------------  ETH_RX_UNICAST_FRAMES_GOOD  ------------------------- */\r
+#define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos 0                                                     /*!< ETH RX_UNICAST_FRAMES_GOOD: RXUCASTG Position */\r
+#define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Msk (0xffffffffUL << ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos)/*!< ETH RX_UNICAST_FRAMES_GOOD: RXUCASTG Mask */\r
+\r
+/* -------------------------  ETH_RX_LENGTH_ERROR_FRAMES  ------------------------- */\r
+#define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos 0                                                     /*!< ETH RX_LENGTH_ERROR_FRAMES: RXLENERR Position */\r
+#define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Msk (0xffffffffUL << ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos)/*!< ETH RX_LENGTH_ERROR_FRAMES: RXLENERR Mask */\r
+\r
+/* -----------------------  ETH_RX_OUT_OF_RANGE_TYPE_FRAMES  ---------------------- */\r
+#define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos 0                                              /*!< ETH RX_OUT_OF_RANGE_TYPE_FRAMES: RXOUTOFRNG Position */\r
+#define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Msk (0xffffffffUL << ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos)/*!< ETH RX_OUT_OF_RANGE_TYPE_FRAMES: RXOUTOFRNG Mask */\r
+\r
+/* -----------------------------  ETH_RX_PAUSE_FRAMES  ---------------------------- */\r
+#define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos    0                                                       /*!< ETH RX_PAUSE_FRAMES: RXPAUSEFRM Position */\r
+#define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Msk    (0xffffffffUL << ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos)    /*!< ETH RX_PAUSE_FRAMES: RXPAUSEFRM Mask    */\r
+\r
+/* -------------------------  ETH_RX_FIFO_OVERFLOW_FRAMES  ------------------------ */\r
+#define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos 0                                                  /*!< ETH RX_FIFO_OVERFLOW_FRAMES: RXFIFOOVFL Position */\r
+#define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Msk (0xffffffffUL << ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos)/*!< ETH RX_FIFO_OVERFLOW_FRAMES: RXFIFOOVFL Mask */\r
+\r
+/* -------------------------  ETH_RX_VLAN_FRAMES_GOOD_BAD  ------------------------ */\r
+#define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos 0                                                  /*!< ETH RX_VLAN_FRAMES_GOOD_BAD: RXVLANFRGB Position */\r
+#define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Msk (0xffffffffUL << ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos)/*!< ETH RX_VLAN_FRAMES_GOOD_BAD: RXVLANFRGB Mask */\r
+\r
+/* ------------------------  ETH_RX_WATCHDOG_ERROR_FRAMES  ------------------------ */\r
+#define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos 0                                                   /*!< ETH RX_WATCHDOG_ERROR_FRAMES: RXWDGERR Position */\r
+#define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Msk (0xffffffffUL << ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos)/*!< ETH RX_WATCHDOG_ERROR_FRAMES: RXWDGERR Mask */\r
+\r
+/* -------------------------  ETH_RX_RECEIVE_ERROR_FRAMES  ------------------------ */\r
+#define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos 0                                                    /*!< ETH RX_RECEIVE_ERROR_FRAMES: RXRCVERR Position */\r
+#define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Msk (0xffffffffUL << ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos)/*!< ETH RX_RECEIVE_ERROR_FRAMES: RXRCVERR Mask */\r
+\r
+/* -------------------------  ETH_RX_CONTROL_FRAMES_GOOD  ------------------------- */\r
+#define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos 0                                                      /*!< ETH RX_CONTROL_FRAMES_GOOD: RXCTRLG Position */\r
+#define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Msk (0xffffffffUL << ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos)/*!< ETH RX_CONTROL_FRAMES_GOOD: RXCTRLG Mask */\r
+\r
+/* ---------------------  ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK  --------------------- */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos 0                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos 1                                         /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HERFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HERFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos 2                                       /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos 3                                        /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos 4                                       /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos 5                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos 6                                         /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HERFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HERFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos 7                                       /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos 8                                            /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos 9                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPERFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPERFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos 10                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos 11                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPERFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPERFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos 12                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos 13                                         /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPERFIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPERFIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Pos 14                                      /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_15_14 Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_15_14_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_15_14 Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos 16                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4GOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos 17                                        /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HEROIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4HEROIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos 18                                      /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4NOPAYOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos 19                                       /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4FRAGOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos 20                                      /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV4UDSBLOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos 21                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6GOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos 22                                        /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HEROIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6HEROIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos 23                                      /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXIPV6NOPAYOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos 24                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPGOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos 25                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPEROIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXUDPEROIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos 26                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPGOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos 27                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPEROIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXTCPEROIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos 28                                          /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGOIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPGOIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos 29                                         /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPEROIM Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: RXICMPEROIM Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Pos 30                                      /*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_31_30 Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_Reserved_31_30_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT_MASK: Reserved_31_30 Mask */\r
+\r
+/* ------------------------  ETH_MMC_IPC_RECEIVE_INTERRUPT  ----------------------- */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos 0                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos 1                                              /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HERFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HERFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos 2                                            /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos 3                                             /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos 4                                            /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos 5                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos 6                                              /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HERFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HERFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos 7                                            /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos 8                                                 /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos 9                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPERFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPERFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos 10                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos 11                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPERFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPERFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos 12                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos 13                                              /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPERFIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPERFIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Pos 14                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_15_14 Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_15_14_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_15_14 Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos 16                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4GOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos 17                                             /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HEROIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4HEROIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos 18                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4NOPAYOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos 19                                            /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4FRAGOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos 20                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV4UDSBLOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos 21                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6GOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos 22                                             /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HEROIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6HEROIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos 23                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXIPV6NOPAYOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos 24                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPGOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos 25                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPEROIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXUDPEROIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos 26                                                /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPGOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos 27                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPEROIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXTCPEROIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos 28                                               /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGOIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPGOIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos 29                                              /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPEROIS Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Msk (0x01UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: RXICMPEROIS Mask */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Pos 30                                           /*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_31_30 Position */\r
+#define ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Msk (0x03UL << ETH_MMC_IPC_RECEIVE_INTERRUPT_Reserved_31_30_Pos)/*!< ETH MMC_IPC_RECEIVE_INTERRUPT: Reserved_31_30 Mask */\r
+\r
+/* ---------------------------  ETH_RXIPV4_GOOD_FRAMES  --------------------------- */\r
+#define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos 0                                                      /*!< ETH RXIPV4_GOOD_FRAMES: RXIPV4GDFRM Position */\r
+#define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Msk (0xffffffffUL << ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos)/*!< ETH RXIPV4_GOOD_FRAMES: RXIPV4GDFRM Mask */\r
+\r
+/* -----------------------  ETH_RXIPV4_HEADER_ERROR_FRAMES  ----------------------- */\r
+#define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos 0                                          /*!< ETH RXIPV4_HEADER_ERROR_FRAMES: RXIPV4HDRERRFRM Position */\r
+#define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Msk (0xffffffffUL << ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos)/*!< ETH RXIPV4_HEADER_ERROR_FRAMES: RXIPV4HDRERRFRM Mask */\r
+\r
+/* ------------------------  ETH_RXIPV4_NO_PAYLOAD_FRAMES  ------------------------ */\r
+#define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos 0                                             /*!< ETH RXIPV4_NO_PAYLOAD_FRAMES: RXIPV4NOPAYFRM Position */\r
+#define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Msk (0xffffffffUL << ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos)/*!< ETH RXIPV4_NO_PAYLOAD_FRAMES: RXIPV4NOPAYFRM Mask */\r
+\r
+/* ------------------------  ETH_RXIPV4_FRAGMENTED_FRAMES  ------------------------ */\r
+#define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos 0                                              /*!< ETH RXIPV4_FRAGMENTED_FRAMES: RXIPV4FRAGFRM Position */\r
+#define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Msk (0xffffffffUL << ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos)/*!< ETH RXIPV4_FRAGMENTED_FRAMES: RXIPV4FRAGFRM Mask */\r
+\r
+/* -------------------  ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES  ------------------ */\r
+#define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos 0                                  /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES: RXIPV4UDSBLFRM Position */\r
+#define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Msk (0xffffffffUL << ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos)/*!< ETH RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES: RXIPV4UDSBLFRM Mask */\r
+\r
+/* ---------------------------  ETH_RXIPV6_GOOD_FRAMES  --------------------------- */\r
+#define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos 0                                                      /*!< ETH RXIPV6_GOOD_FRAMES: RXIPV6GDFRM Position */\r
+#define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Msk (0xffffffffUL << ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos)/*!< ETH RXIPV6_GOOD_FRAMES: RXIPV6GDFRM Mask */\r
+\r
+/* -----------------------  ETH_RXIPV6_HEADER_ERROR_FRAMES  ----------------------- */\r
+#define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos 0                                          /*!< ETH RXIPV6_HEADER_ERROR_FRAMES: RXIPV6HDRERRFRM Position */\r
+#define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Msk (0xffffffffUL << ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos)/*!< ETH RXIPV6_HEADER_ERROR_FRAMES: RXIPV6HDRERRFRM Mask */\r
+\r
+/* ------------------------  ETH_RXIPV6_NO_PAYLOAD_FRAMES  ------------------------ */\r
+#define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos 0                                             /*!< ETH RXIPV6_NO_PAYLOAD_FRAMES: RXIPV6NOPAYFRM Position */\r
+#define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Msk (0xffffffffUL << ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos)/*!< ETH RXIPV6_NO_PAYLOAD_FRAMES: RXIPV6NOPAYFRM Mask */\r
+\r
+/* ----------------------------  ETH_RXUDP_GOOD_FRAMES  --------------------------- */\r
+#define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos  0                                                       /*!< ETH RXUDP_GOOD_FRAMES: RXUDPGDFRM Position */\r
+#define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Msk  (0xffffffffUL << ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos)  /*!< ETH RXUDP_GOOD_FRAMES: RXUDPGDFRM Mask  */\r
+\r
+/* ---------------------------  ETH_RXUDP_ERROR_FRAMES  --------------------------- */\r
+#define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos 0                                                      /*!< ETH RXUDP_ERROR_FRAMES: RXUDPERRFRM Position */\r
+#define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Msk (0xffffffffUL << ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos)/*!< ETH RXUDP_ERROR_FRAMES: RXUDPERRFRM Mask */\r
+\r
+/* ----------------------------  ETH_RXTCP_GOOD_FRAMES  --------------------------- */\r
+#define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos  0                                                       /*!< ETH RXTCP_GOOD_FRAMES: RXTCPGDFRM Position */\r
+#define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Msk  (0xffffffffUL << ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos)  /*!< ETH RXTCP_GOOD_FRAMES: RXTCPGDFRM Mask  */\r
+\r
+/* ---------------------------  ETH_RXTCP_ERROR_FRAMES  --------------------------- */\r
+#define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos 0                                                      /*!< ETH RXTCP_ERROR_FRAMES: RXTCPERRFRM Position */\r
+#define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Msk (0xffffffffUL << ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos)/*!< ETH RXTCP_ERROR_FRAMES: RXTCPERRFRM Mask */\r
+\r
+/* ---------------------------  ETH_RXICMP_GOOD_FRAMES  --------------------------- */\r
+#define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos 0                                                      /*!< ETH RXICMP_GOOD_FRAMES: RXICMPGDFRM Position */\r
+#define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Msk (0xffffffffUL << ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos)/*!< ETH RXICMP_GOOD_FRAMES: RXICMPGDFRM Mask */\r
+\r
+/* ---------------------------  ETH_RXICMP_ERROR_FRAMES  -------------------------- */\r
+#define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos 0                                                    /*!< ETH RXICMP_ERROR_FRAMES: RXICMPERRFRM Position */\r
+#define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Msk (0xffffffffUL << ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos)/*!< ETH RXICMP_ERROR_FRAMES: RXICMPERRFRM Mask */\r
+\r
+/* ---------------------------  ETH_RXIPV4_GOOD_OCTETS  --------------------------- */\r
+#define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos 0                                                      /*!< ETH RXIPV4_GOOD_OCTETS: RXIPV4GDOCT Position */\r
+#define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Msk (0xffffffffUL << ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos)/*!< ETH RXIPV4_GOOD_OCTETS: RXIPV4GDOCT Mask */\r
+\r
+/* -----------------------  ETH_RXIPV4_HEADER_ERROR_OCTETS  ----------------------- */\r
+#define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos 0                                          /*!< ETH RXIPV4_HEADER_ERROR_OCTETS: RXIPV4HDRERROCT Position */\r
+#define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Msk (0xffffffffUL << ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos)/*!< ETH RXIPV4_HEADER_ERROR_OCTETS: RXIPV4HDRERROCT Mask */\r
+\r
+/* ------------------------  ETH_RXIPV4_NO_PAYLOAD_OCTETS  ------------------------ */\r
+#define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos 0                                             /*!< ETH RXIPV4_NO_PAYLOAD_OCTETS: RXIPV4NOPAYOCT Position */\r
+#define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Msk (0xffffffffUL << ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos)/*!< ETH RXIPV4_NO_PAYLOAD_OCTETS: RXIPV4NOPAYOCT Mask */\r
+\r
+/* ------------------------  ETH_RXIPV4_FRAGMENTED_OCTETS  ------------------------ */\r
+#define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos 0                                              /*!< ETH RXIPV4_FRAGMENTED_OCTETS: RXIPV4FRAGOCT Position */\r
+#define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Msk (0xffffffffUL << ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos)/*!< ETH RXIPV4_FRAGMENTED_OCTETS: RXIPV4FRAGOCT Mask */\r
+\r
+/* -------------------  ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS  ------------------- */\r
+#define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos 0                                   /*!< ETH RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS: RXIPV4UDSBLOCT Position */\r
+#define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Msk (0xffffffffUL << ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos)/*!< ETH RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS: RXIPV4UDSBLOCT Mask */\r
+\r
+/* ---------------------------  ETH_RXIPV6_GOOD_OCTETS  --------------------------- */\r
+#define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos 0                                                      /*!< ETH RXIPV6_GOOD_OCTETS: RXIPV6GDOCT Position */\r
+#define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Msk (0xffffffffUL << ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos)/*!< ETH RXIPV6_GOOD_OCTETS: RXIPV6GDOCT Mask */\r
+\r
+/* -----------------------  ETH_RXIPV6_HEADER_ERROR_OCTETS  ----------------------- */\r
+#define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos 0                                          /*!< ETH RXIPV6_HEADER_ERROR_OCTETS: RXIPV6HDRERROCT Position */\r
+#define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Msk (0xffffffffUL << ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos)/*!< ETH RXIPV6_HEADER_ERROR_OCTETS: RXIPV6HDRERROCT Mask */\r
+\r
+/* ------------------------  ETH_RXIPV6_NO_PAYLOAD_OCTETS  ------------------------ */\r
+#define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos 0                                             /*!< ETH RXIPV6_NO_PAYLOAD_OCTETS: RXIPV6NOPAYOCT Position */\r
+#define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Msk (0xffffffffUL << ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos)/*!< ETH RXIPV6_NO_PAYLOAD_OCTETS: RXIPV6NOPAYOCT Mask */\r
+\r
+/* ----------------------------  ETH_RXUDP_GOOD_OCTETS  --------------------------- */\r
+#define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos  0                                                       /*!< ETH RXUDP_GOOD_OCTETS: RXUDPGDOCT Position */\r
+#define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Msk  (0xffffffffUL << ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos)  /*!< ETH RXUDP_GOOD_OCTETS: RXUDPGDOCT Mask  */\r
+\r
+/* ---------------------------  ETH_RXUDP_ERROR_OCTETS  --------------------------- */\r
+#define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos 0                                                      /*!< ETH RXUDP_ERROR_OCTETS: RXUDPERROCT Position */\r
+#define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Msk (0xffffffffUL << ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos)/*!< ETH RXUDP_ERROR_OCTETS: RXUDPERROCT Mask */\r
+\r
+/* ----------------------------  ETH_RXTCP_GOOD_OCTETS  --------------------------- */\r
+#define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos  0                                                       /*!< ETH RXTCP_GOOD_OCTETS: RXTCPGDOCT Position */\r
+#define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Msk  (0xffffffffUL << ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos)  /*!< ETH RXTCP_GOOD_OCTETS: RXTCPGDOCT Mask  */\r
+\r
+/* ---------------------------  ETH_RXTCP_ERROR_OCTETS  --------------------------- */\r
+#define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos 0                                                      /*!< ETH RXTCP_ERROR_OCTETS: RXTCPERROCT Position */\r
+#define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Msk (0xffffffffUL << ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos)/*!< ETH RXTCP_ERROR_OCTETS: RXTCPERROCT Mask */\r
+\r
+/* ---------------------------  ETH_RXICMP_GOOD_OCTETS  --------------------------- */\r
+#define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos 0                                                      /*!< ETH RXICMP_GOOD_OCTETS: RXICMPGDOCT Position */\r
+#define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Msk (0xffffffffUL << ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos)/*!< ETH RXICMP_GOOD_OCTETS: RXICMPGDOCT Mask */\r
+\r
+/* ---------------------------  ETH_RXICMP_ERROR_OCTETS  -------------------------- */\r
+#define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos 0                                                    /*!< ETH RXICMP_ERROR_OCTETS: RXICMPERROCT Position */\r
+#define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Msk (0xffffffffUL << ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos)/*!< ETH RXICMP_ERROR_OCTETS: RXICMPERROCT Mask */\r
+\r
+/* ----------------------------  ETH_TIMESTAMP_CONTROL  --------------------------- */\r
+#define ETH_TIMESTAMP_CONTROL_TSENA_Pos       0                                                       /*!< ETH TIMESTAMP_CONTROL: TSENA Position   */\r
+#define ETH_TIMESTAMP_CONTROL_TSENA_Msk       (0x01UL << ETH_TIMESTAMP_CONTROL_TSENA_Pos)             /*!< ETH TIMESTAMP_CONTROL: TSENA Mask       */\r
+#define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos    1                                                       /*!< ETH TIMESTAMP_CONTROL: TSCFUPDT Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk    (0x01UL << ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos)          /*!< ETH TIMESTAMP_CONTROL: TSCFUPDT Mask    */\r
+#define ETH_TIMESTAMP_CONTROL_TSINIT_Pos      2                                                       /*!< ETH TIMESTAMP_CONTROL: TSINIT Position  */\r
+#define ETH_TIMESTAMP_CONTROL_TSINIT_Msk      (0x01UL << ETH_TIMESTAMP_CONTROL_TSINIT_Pos)            /*!< ETH TIMESTAMP_CONTROL: TSINIT Mask      */\r
+#define ETH_TIMESTAMP_CONTROL_TSUPDT_Pos      3                                                       /*!< ETH TIMESTAMP_CONTROL: TSUPDT Position  */\r
+#define ETH_TIMESTAMP_CONTROL_TSUPDT_Msk      (0x01UL << ETH_TIMESTAMP_CONTROL_TSUPDT_Pos)            /*!< ETH TIMESTAMP_CONTROL: TSUPDT Mask      */\r
+#define ETH_TIMESTAMP_CONTROL_TSTRIG_Pos      4                                                       /*!< ETH TIMESTAMP_CONTROL: TSTRIG Position  */\r
+#define ETH_TIMESTAMP_CONTROL_TSTRIG_Msk      (0x01UL << ETH_TIMESTAMP_CONTROL_TSTRIG_Pos)            /*!< ETH TIMESTAMP_CONTROL: TSTRIG Mask      */\r
+#define ETH_TIMESTAMP_CONTROL_TSADDREG_Pos    5                                                       /*!< ETH TIMESTAMP_CONTROL: TSADDREG Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSADDREG_Msk    (0x01UL << ETH_TIMESTAMP_CONTROL_TSADDREG_Pos)          /*!< ETH TIMESTAMP_CONTROL: TSADDREG Mask    */\r
+#define ETH_TIMESTAMP_CONTROL_Reserved_7_6_Pos 6                                                      /*!< ETH TIMESTAMP_CONTROL: Reserved_7_6 Position */\r
+#define ETH_TIMESTAMP_CONTROL_Reserved_7_6_Msk (0x03UL << ETH_TIMESTAMP_CONTROL_Reserved_7_6_Pos)     /*!< ETH TIMESTAMP_CONTROL: Reserved_7_6 Mask */\r
+#define ETH_TIMESTAMP_CONTROL_TSENALL_Pos     8                                                       /*!< ETH TIMESTAMP_CONTROL: TSENALL Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSENALL_Msk     (0x01UL << ETH_TIMESTAMP_CONTROL_TSENALL_Pos)           /*!< ETH TIMESTAMP_CONTROL: TSENALL Mask     */\r
+#define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos   9                                                       /*!< ETH TIMESTAMP_CONTROL: TSCTRLSSR Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSCTRLSSR Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos   10                                                      /*!< ETH TIMESTAMP_CONTROL: TSVER2ENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSVER2ENA Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPENA_Pos     11                                                      /*!< ETH TIMESTAMP_CONTROL: TSIPENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPENA_Msk     (0x01UL << ETH_TIMESTAMP_CONTROL_TSIPENA_Pos)           /*!< ETH TIMESTAMP_CONTROL: TSIPENA Mask     */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos   12                                                      /*!< ETH TIMESTAMP_CONTROL: TSIPV6ENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSIPV6ENA Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos   13                                                      /*!< ETH TIMESTAMP_CONTROL: TSIPV4ENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSIPV4ENA Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos   14                                                      /*!< ETH TIMESTAMP_CONTROL: TSEVNTENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSEVNTENA Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos   15                                                      /*!< ETH TIMESTAMP_CONTROL: TSMSTRENA Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Msk   (0x01UL << ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos)         /*!< ETH TIMESTAMP_CONTROL: TSMSTRENA Mask   */\r
+#define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos  16                                                      /*!< ETH TIMESTAMP_CONTROL: SNAPTYPSEL Position */\r
+#define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Msk  (0x03UL << ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos)        /*!< ETH TIMESTAMP_CONTROL: SNAPTYPSEL Mask  */\r
+#define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos 18                                                      /*!< ETH TIMESTAMP_CONTROL: TSENMACADDR Position */\r
+#define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Msk (0x01UL << ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos)       /*!< ETH TIMESTAMP_CONTROL: TSENMACADDR Mask */\r
+#define ETH_TIMESTAMP_CONTROL_Reserved_23_19_Pos 19                                                   /*!< ETH TIMESTAMP_CONTROL: Reserved_23_19 Position */\r
+#define ETH_TIMESTAMP_CONTROL_Reserved_23_19_Msk (0x00001fffUL << ETH_TIMESTAMP_CONTROL_Reserved_23_19_Pos)/*!< ETH TIMESTAMP_CONTROL: Reserved_23_19 Mask */\r
+\r
+/* --------------------------  ETH_SUB_SECOND_INCREMENT  -------------------------- */\r
+#define ETH_SUB_SECOND_INCREMENT_SSINC_Pos    0                                                       /*!< ETH SUB_SECOND_INCREMENT: SSINC Position */\r
+#define ETH_SUB_SECOND_INCREMENT_SSINC_Msk    (0x000000ffUL << ETH_SUB_SECOND_INCREMENT_SSINC_Pos)    /*!< ETH SUB_SECOND_INCREMENT: SSINC Mask    */\r
+#define ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Pos 8                                                  /*!< ETH SUB_SECOND_INCREMENT: Reserved_31_8 Position */\r
+#define ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Msk (0x00ffffffUL << ETH_SUB_SECOND_INCREMENT_Reserved_31_8_Pos)/*!< ETH SUB_SECOND_INCREMENT: Reserved_31_8 Mask */\r
+\r
+/* ---------------------------  ETH_SYSTEM_TIME_SECONDS  -------------------------- */\r
+#define ETH_SYSTEM_TIME_SECONDS_TSS_Pos       0                                                       /*!< ETH SYSTEM_TIME_SECONDS: TSS Position   */\r
+#define ETH_SYSTEM_TIME_SECONDS_TSS_Msk       (0xffffffffUL << ETH_SYSTEM_TIME_SECONDS_TSS_Pos)       /*!< ETH SYSTEM_TIME_SECONDS: TSS Mask       */\r
+\r
+/* -------------------------  ETH_SYSTEM_TIME_NANOSECONDS  ------------------------ */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos  0                                                       /*!< ETH SYSTEM_TIME_NANOSECONDS: TSSS Position */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Msk  (0x7fffffffUL << ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos)  /*!< ETH SYSTEM_TIME_NANOSECONDS: TSSS Mask  */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Pos 31                                                /*!< ETH SYSTEM_TIME_NANOSECONDS: Reserved_31 Position */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Msk (0x01UL << ETH_SYSTEM_TIME_NANOSECONDS_Reserved_31_Pos)/*!< ETH SYSTEM_TIME_NANOSECONDS: Reserved_31 Mask */\r
+\r
+/* -----------------------  ETH_SYSTEM_TIME_SECONDS_UPDATE  ----------------------- */\r
+#define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos 0                                                      /*!< ETH SYSTEM_TIME_SECONDS_UPDATE: TSS Position */\r
+#define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Msk (0xffffffffUL << ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos)/*!< ETH SYSTEM_TIME_SECONDS_UPDATE: TSS Mask */\r
+\r
+/* ---------------------  ETH_SYSTEM_TIME_NANOSECONDS_UPDATE  --------------------- */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos 0                                                 /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: TSSS Position */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Msk (0x7fffffffUL << ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos)/*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: TSSS Mask */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos 31                                              /*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: ADDSUB Position */\r
+#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk (0x01UL << ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos)/*!< ETH SYSTEM_TIME_NANOSECONDS_UPDATE: ADDSUB Mask */\r
+\r
+/* ----------------------------  ETH_TIMESTAMP_ADDEND  ---------------------------- */\r
+#define ETH_TIMESTAMP_ADDEND_TSAR_Pos         0                                                       /*!< ETH TIMESTAMP_ADDEND: TSAR Position     */\r
+#define ETH_TIMESTAMP_ADDEND_TSAR_Msk         (0xffffffffUL << ETH_TIMESTAMP_ADDEND_TSAR_Pos)         /*!< ETH TIMESTAMP_ADDEND: TSAR Mask         */\r
+\r
+/* ---------------------------  ETH_TARGET_TIME_SECONDS  -------------------------- */\r
+#define ETH_TARGET_TIME_SECONDS_TSTR_Pos      0                                                       /*!< ETH TARGET_TIME_SECONDS: TSTR Position  */\r
+#define ETH_TARGET_TIME_SECONDS_TSTR_Msk      (0xffffffffUL << ETH_TARGET_TIME_SECONDS_TSTR_Pos)      /*!< ETH TARGET_TIME_SECONDS: TSTR Mask      */\r
+\r
+/* -------------------------  ETH_TARGET_TIME_NANOSECONDS  ------------------------ */\r
+#define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos 0                                                       /*!< ETH TARGET_TIME_NANOSECONDS: TTSLO Position */\r
+#define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Msk (0x7fffffffUL << ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos) /*!< ETH TARGET_TIME_NANOSECONDS: TTSLO Mask */\r
+#define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos 31                                                   /*!< ETH TARGET_TIME_NANOSECONDS: TRGTBUSY Position */\r
+#define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Msk (0x01UL << ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos) /*!< ETH TARGET_TIME_NANOSECONDS: TRGTBUSY Mask */\r
+\r
+/* ---------------------  ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS  -------------------- */\r
+#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos 0                                               /*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: TSHWR Position */\r
+#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Msk (0x0000ffffUL << ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos)/*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: TSHWR Mask */\r
+#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Pos 16                                     /*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: Reserved_31_16 Position */\r
+#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Msk (0x0000ffffUL << ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_Reserved_31_16_Pos)/*!< ETH SYSTEM_TIME_HIGHER_WORD_SECONDS: Reserved_31_16 Mask */\r
+\r
+/* ----------------------------  ETH_TIMESTAMP_STATUS  ---------------------------- */\r
+#define ETH_TIMESTAMP_STATUS_TSSOVF_Pos       0                                                       /*!< ETH TIMESTAMP_STATUS: TSSOVF Position   */\r
+#define ETH_TIMESTAMP_STATUS_TSSOVF_Msk       (0x01UL << ETH_TIMESTAMP_STATUS_TSSOVF_Pos)             /*!< ETH TIMESTAMP_STATUS: TSSOVF Mask       */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT_Pos      1                                                       /*!< ETH TIMESTAMP_STATUS: TSTARGT Position  */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT_Msk      (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT_Pos)            /*!< ETH TIMESTAMP_STATUS: TSTARGT Mask      */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_2_Pos   2                                                       /*!< ETH TIMESTAMP_STATUS: Reserved_2 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_2_Msk   (0x01UL << ETH_TIMESTAMP_STATUS_Reserved_2_Pos)         /*!< ETH TIMESTAMP_STATUS: Reserved_2 Mask   */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos    3                                                       /*!< ETH TIMESTAMP_STATUS: TSTRGTERR Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR_Msk    (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos)          /*!< ETH TIMESTAMP_STATUS: TSTRGTERR Mask    */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT1_Pos     4                                                       /*!< ETH TIMESTAMP_STATUS: TSTARGT1 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT1_Msk     (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT1_Pos)           /*!< ETH TIMESTAMP_STATUS: TSTARGT1 Mask     */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos   5                                                       /*!< ETH TIMESTAMP_STATUS: TSTRGTERR1 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Msk   (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos)         /*!< ETH TIMESTAMP_STATUS: TSTRGTERR1 Mask   */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT2_Pos     6                                                       /*!< ETH TIMESTAMP_STATUS: TSTARGT2 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT2_Msk     (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT2_Pos)           /*!< ETH TIMESTAMP_STATUS: TSTARGT2 Mask     */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos   7                                                       /*!< ETH TIMESTAMP_STATUS: TSTRGTERR2 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Msk   (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos)         /*!< ETH TIMESTAMP_STATUS: TSTRGTERR2 Mask   */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT3_Pos     8                                                       /*!< ETH TIMESTAMP_STATUS: TSTARGT3 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTARGT3_Msk     (0x01UL << ETH_TIMESTAMP_STATUS_TSTARGT3_Pos)           /*!< ETH TIMESTAMP_STATUS: TSTARGT3 Mask     */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos   9                                                       /*!< ETH TIMESTAMP_STATUS: TSTRGTERR3 Position */\r
+#define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Msk   (0x01UL << ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos)         /*!< ETH TIMESTAMP_STATUS: TSTRGTERR3 Mask   */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_15_10_Pos 10                                                    /*!< ETH TIMESTAMP_STATUS: Reserved_15_10 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_15_10_Msk (0x3fUL << ETH_TIMESTAMP_STATUS_Reserved_15_10_Pos)   /*!< ETH TIMESTAMP_STATUS: Reserved_15_10 Mask */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_19_16_Pos 16                                                    /*!< ETH TIMESTAMP_STATUS: Reserved_19_16 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_19_16_Msk (0x0fUL << ETH_TIMESTAMP_STATUS_Reserved_19_16_Pos)   /*!< ETH TIMESTAMP_STATUS: Reserved_19_16 Mask */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_23_20_Pos 20                                                    /*!< ETH TIMESTAMP_STATUS: Reserved_23_20 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_23_20_Msk (0x0fUL << ETH_TIMESTAMP_STATUS_Reserved_23_20_Pos)   /*!< ETH TIMESTAMP_STATUS: Reserved_23_20 Mask */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_24_Pos  24                                                      /*!< ETH TIMESTAMP_STATUS: Reserved_24 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_24_Msk  (0x01UL << ETH_TIMESTAMP_STATUS_Reserved_24_Pos)        /*!< ETH TIMESTAMP_STATUS: Reserved_24 Mask  */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_29_25_Pos 25                                                    /*!< ETH TIMESTAMP_STATUS: Reserved_29_25 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_29_25_Msk (0x1fUL << ETH_TIMESTAMP_STATUS_Reserved_29_25_Pos)   /*!< ETH TIMESTAMP_STATUS: Reserved_29_25 Mask */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_31_30_Pos 30                                                    /*!< ETH TIMESTAMP_STATUS: Reserved_31_30 Position */\r
+#define ETH_TIMESTAMP_STATUS_Reserved_31_30_Msk (0x03UL << ETH_TIMESTAMP_STATUS_Reserved_31_30_Pos)   /*!< ETH TIMESTAMP_STATUS: Reserved_31_30 Mask */\r
+\r
+/* -------------------------------  ETH_PPS_CONTROL  ------------------------------ */\r
+#define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos    0                                                       /*!< ETH PPS_CONTROL: PPSCTRL_PPSCMD Position */\r
+#define ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Msk    (0x0fUL << ETH_PPS_CONTROL_PPSCTRL_PPSCMD_Pos)          /*!< ETH PPS_CONTROL: PPSCTRL_PPSCMD Mask    */\r
+#define ETH_PPS_CONTROL_PPSEN0_Pos            4                                                       /*!< ETH PPS_CONTROL: PPSEN0 Position        */\r
+#define ETH_PPS_CONTROL_PPSEN0_Msk            (0x01UL << ETH_PPS_CONTROL_PPSEN0_Pos)                  /*!< ETH PPS_CONTROL: PPSEN0 Mask            */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL0_Pos       5                                                       /*!< ETH PPS_CONTROL: TRGTMODSEL0 Position   */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL0_Msk       (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL0_Pos)             /*!< ETH PPS_CONTROL: TRGTMODSEL0 Mask       */\r
+#define ETH_PPS_CONTROL_Reserved_7_Pos        7                                                       /*!< ETH PPS_CONTROL: Reserved_7 Position    */\r
+#define ETH_PPS_CONTROL_Reserved_7_Msk        (0x01UL << ETH_PPS_CONTROL_Reserved_7_Pos)              /*!< ETH PPS_CONTROL: Reserved_7 Mask        */\r
+#define ETH_PPS_CONTROL_PPSCMD1_Pos           8                                                       /*!< ETH PPS_CONTROL: PPSCMD1 Position       */\r
+#define ETH_PPS_CONTROL_PPSCMD1_Msk           (0x07UL << ETH_PPS_CONTROL_PPSCMD1_Pos)                 /*!< ETH PPS_CONTROL: PPSCMD1 Mask           */\r
+#define ETH_PPS_CONTROL_Reserved_12_11_Pos    11                                                      /*!< ETH PPS_CONTROL: Reserved_12_11 Position */\r
+#define ETH_PPS_CONTROL_Reserved_12_11_Msk    (0x03UL << ETH_PPS_CONTROL_Reserved_12_11_Pos)          /*!< ETH PPS_CONTROL: Reserved_12_11 Mask    */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL1_Pos       13                                                      /*!< ETH PPS_CONTROL: TRGTMODSEL1 Position   */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL1_Msk       (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL1_Pos)             /*!< ETH PPS_CONTROL: TRGTMODSEL1 Mask       */\r
+#define ETH_PPS_CONTROL_Reserved_15_Pos       15                                                      /*!< ETH PPS_CONTROL: Reserved_15 Position   */\r
+#define ETH_PPS_CONTROL_Reserved_15_Msk       (0x01UL << ETH_PPS_CONTROL_Reserved_15_Pos)             /*!< ETH PPS_CONTROL: Reserved_15 Mask       */\r
+#define ETH_PPS_CONTROL_PPSCMD2_Pos           16                                                      /*!< ETH PPS_CONTROL: PPSCMD2 Position       */\r
+#define ETH_PPS_CONTROL_PPSCMD2_Msk           (0x07UL << ETH_PPS_CONTROL_PPSCMD2_Pos)                 /*!< ETH PPS_CONTROL: PPSCMD2 Mask           */\r
+#define ETH_PPS_CONTROL_Reserved_20_19_Pos    19                                                      /*!< ETH PPS_CONTROL: Reserved_20_19 Position */\r
+#define ETH_PPS_CONTROL_Reserved_20_19_Msk    (0x03UL << ETH_PPS_CONTROL_Reserved_20_19_Pos)          /*!< ETH PPS_CONTROL: Reserved_20_19 Mask    */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL2_Pos       21                                                      /*!< ETH PPS_CONTROL: TRGTMODSEL2 Position   */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL2_Msk       (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL2_Pos)             /*!< ETH PPS_CONTROL: TRGTMODSEL2 Mask       */\r
+#define ETH_PPS_CONTROL_Reserved_23_Pos       23                                                      /*!< ETH PPS_CONTROL: Reserved_23 Position   */\r
+#define ETH_PPS_CONTROL_Reserved_23_Msk       (0x01UL << ETH_PPS_CONTROL_Reserved_23_Pos)             /*!< ETH PPS_CONTROL: Reserved_23 Mask       */\r
+#define ETH_PPS_CONTROL_PPSCMD3_Pos           24                                                      /*!< ETH PPS_CONTROL: PPSCMD3 Position       */\r
+#define ETH_PPS_CONTROL_PPSCMD3_Msk           (0x07UL << ETH_PPS_CONTROL_PPSCMD3_Pos)                 /*!< ETH PPS_CONTROL: PPSCMD3 Mask           */\r
+#define ETH_PPS_CONTROL_Reserved_28_27_Pos    27                                                      /*!< ETH PPS_CONTROL: Reserved_28_27 Position */\r
+#define ETH_PPS_CONTROL_Reserved_28_27_Msk    (0x03UL << ETH_PPS_CONTROL_Reserved_28_27_Pos)          /*!< ETH PPS_CONTROL: Reserved_28_27 Mask    */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL3_Pos       29                                                      /*!< ETH PPS_CONTROL: TRGTMODSEL3 Position   */\r
+#define ETH_PPS_CONTROL_TRGTMODSEL3_Msk       (0x03UL << ETH_PPS_CONTROL_TRGTMODSEL3_Pos)             /*!< ETH PPS_CONTROL: TRGTMODSEL3 Mask       */\r
+#define ETH_PPS_CONTROL_Reserved_31_Pos       31                                                      /*!< ETH PPS_CONTROL: Reserved_31 Position   */\r
+#define ETH_PPS_CONTROL_Reserved_31_Msk       (0x01UL << ETH_PPS_CONTROL_Reserved_31_Pos)             /*!< ETH PPS_CONTROL: Reserved_31 Mask       */\r
+\r
+/* --------------------------------  ETH_BUS_MODE  -------------------------------- */\r
+#define ETH_BUS_MODE_SWR_Pos                  0                                                       /*!< ETH BUS_MODE: SWR Position              */\r
+#define ETH_BUS_MODE_SWR_Msk                  (0x01UL << ETH_BUS_MODE_SWR_Pos)                        /*!< ETH BUS_MODE: SWR Mask                  */\r
+#define ETH_BUS_MODE_DA_Pos                   1                                                       /*!< ETH BUS_MODE: DA Position               */\r
+#define ETH_BUS_MODE_DA_Msk                   (0x01UL << ETH_BUS_MODE_DA_Pos)                         /*!< ETH BUS_MODE: DA Mask                   */\r
+#define ETH_BUS_MODE_DSL_Pos                  2                                                       /*!< ETH BUS_MODE: DSL Position              */\r
+#define ETH_BUS_MODE_DSL_Msk                  (0x1fUL << ETH_BUS_MODE_DSL_Pos)                        /*!< ETH BUS_MODE: DSL Mask                  */\r
+#define ETH_BUS_MODE_Reserved_7_Pos           7                                                       /*!< ETH BUS_MODE: Reserved_7 Position       */\r
+#define ETH_BUS_MODE_Reserved_7_Msk           (0x01UL << ETH_BUS_MODE_Reserved_7_Pos)                 /*!< ETH BUS_MODE: Reserved_7 Mask           */\r
+#define ETH_BUS_MODE_PBL_Pos                  8                                                       /*!< ETH BUS_MODE: PBL Position              */\r
+#define ETH_BUS_MODE_PBL_Msk                  (0x3fUL << ETH_BUS_MODE_PBL_Pos)                        /*!< ETH BUS_MODE: PBL Mask                  */\r
+#define ETH_BUS_MODE_PR_Pos                   14                                                      /*!< ETH BUS_MODE: PR Position               */\r
+#define ETH_BUS_MODE_PR_Msk                   (0x03UL << ETH_BUS_MODE_PR_Pos)                         /*!< ETH BUS_MODE: PR Mask                   */\r
+#define ETH_BUS_MODE_FB_Pos                   16                                                      /*!< ETH BUS_MODE: FB Position               */\r
+#define ETH_BUS_MODE_FB_Msk                   (0x01UL << ETH_BUS_MODE_FB_Pos)                         /*!< ETH BUS_MODE: FB Mask                   */\r
+#define ETH_BUS_MODE_RPBL_Pos                 17                                                      /*!< ETH BUS_MODE: RPBL Position             */\r
+#define ETH_BUS_MODE_RPBL_Msk                 (0x3fUL << ETH_BUS_MODE_RPBL_Pos)                       /*!< ETH BUS_MODE: RPBL Mask                 */\r
+#define ETH_BUS_MODE_USP_Pos                  23                                                      /*!< ETH BUS_MODE: USP Position              */\r
+#define ETH_BUS_MODE_USP_Msk                  (0x01UL << ETH_BUS_MODE_USP_Pos)                        /*!< ETH BUS_MODE: USP Mask                  */\r
+#define ETH_BUS_MODE_EIGHTxPBL_Pos            24                                                      /*!< ETH BUS_MODE: EIGHTxPBL Position        */\r
+#define ETH_BUS_MODE_EIGHTxPBL_Msk            (0x01UL << ETH_BUS_MODE_EIGHTxPBL_Pos)                  /*!< ETH BUS_MODE: EIGHTxPBL Mask            */\r
+#define ETH_BUS_MODE_AAL_Pos                  25                                                      /*!< ETH BUS_MODE: AAL Position              */\r
+#define ETH_BUS_MODE_AAL_Msk                  (0x01UL << ETH_BUS_MODE_AAL_Pos)                        /*!< ETH BUS_MODE: AAL Mask                  */\r
+#define ETH_BUS_MODE_MB_Pos                   26                                                      /*!< ETH BUS_MODE: MB Position               */\r
+#define ETH_BUS_MODE_MB_Msk                   (0x01UL << ETH_BUS_MODE_MB_Pos)                         /*!< ETH BUS_MODE: MB Mask                   */\r
+#define ETH_BUS_MODE_TXPR_Pos                 27                                                      /*!< ETH BUS_MODE: TXPR Position             */\r
+#define ETH_BUS_MODE_TXPR_Msk                 (0x01UL << ETH_BUS_MODE_TXPR_Pos)                       /*!< ETH BUS_MODE: TXPR Mask                 */\r
+#define ETH_BUS_MODE_PRWG_Pos                 28                                                      /*!< ETH BUS_MODE: PRWG Position             */\r
+#define ETH_BUS_MODE_PRWG_Msk                 (0x03UL << ETH_BUS_MODE_PRWG_Pos)                       /*!< ETH BUS_MODE: PRWG Mask                 */\r
+#define ETH_BUS_MODE_Reserved_31_30_Pos       30                                                      /*!< ETH BUS_MODE: Reserved_31_30 Position   */\r
+#define ETH_BUS_MODE_Reserved_31_30_Msk       (0x03UL << ETH_BUS_MODE_Reserved_31_30_Pos)             /*!< ETH BUS_MODE: Reserved_31_30 Mask       */\r
+\r
+/* --------------------------  ETH_TRANSMIT_POLL_DEMAND  -------------------------- */\r
+#define ETH_TRANSMIT_POLL_DEMAND_TPD_Pos      0                                                       /*!< ETH TRANSMIT_POLL_DEMAND: TPD Position  */\r
+#define ETH_TRANSMIT_POLL_DEMAND_TPD_Msk      (0xffffffffUL << ETH_TRANSMIT_POLL_DEMAND_TPD_Pos)      /*!< ETH TRANSMIT_POLL_DEMAND: TPD Mask      */\r
+\r
+/* ---------------------------  ETH_RECEIVE_POLL_DEMAND  -------------------------- */\r
+#define ETH_RECEIVE_POLL_DEMAND_RPD_Pos       0                                                       /*!< ETH RECEIVE_POLL_DEMAND: RPD Position   */\r
+#define ETH_RECEIVE_POLL_DEMAND_RPD_Msk       (0xffffffffUL << ETH_RECEIVE_POLL_DEMAND_RPD_Pos)       /*!< ETH RECEIVE_POLL_DEMAND: RPD Mask       */\r
+\r
+/* ---------------------  ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS  -------------------- */\r
+#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos 0                                        /*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Position */\r
+#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Msk (0x03UL << ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos)/*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Mask */\r
+#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos 2                                        /*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: RDESLA_32bit Position */\r
+#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Msk (0x3fffffffUL << ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos)/*!< ETH RECEIVE_DESCRIPTOR_LIST_ADDRESS: RDESLA_32bit Mask */\r
+\r
+/* --------------------  ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS  -------------------- */\r
+#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos 0                                       /*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Position */\r
+#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Msk (0x03UL << ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_Reserved_1_0_Pos)/*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: Reserved_1_0 Mask */\r
+#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos 2                                       /*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: TDESLA_32bit Position */\r
+#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Msk (0x3fffffffUL << ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos)/*!< ETH TRANSMIT_DESCRIPTOR_LIST_ADDRESS: TDESLA_32bit Mask */\r
+\r
+/* ---------------------------------  ETH_STATUS  --------------------------------- */\r
+#define ETH_STATUS_TI_Pos                     0                                                       /*!< ETH STATUS: TI Position                 */\r
+#define ETH_STATUS_TI_Msk                     (0x01UL << ETH_STATUS_TI_Pos)                           /*!< ETH STATUS: TI Mask                     */\r
+#define ETH_STATUS_TPS_Pos                    1                                                       /*!< ETH STATUS: TPS Position                */\r
+#define ETH_STATUS_TPS_Msk                    (0x01UL << ETH_STATUS_TPS_Pos)                          /*!< ETH STATUS: TPS Mask                    */\r
+#define ETH_STATUS_TU_Pos                     2                                                       /*!< ETH STATUS: TU Position                 */\r
+#define ETH_STATUS_TU_Msk                     (0x01UL << ETH_STATUS_TU_Pos)                           /*!< ETH STATUS: TU Mask                     */\r
+#define ETH_STATUS_TJT_Pos                    3                                                       /*!< ETH STATUS: TJT Position                */\r
+#define ETH_STATUS_TJT_Msk                    (0x01UL << ETH_STATUS_TJT_Pos)                          /*!< ETH STATUS: TJT Mask                    */\r
+#define ETH_STATUS_OVF_Pos                    4                                                       /*!< ETH STATUS: OVF Position                */\r
+#define ETH_STATUS_OVF_Msk                    (0x01UL << ETH_STATUS_OVF_Pos)                          /*!< ETH STATUS: OVF Mask                    */\r
+#define ETH_STATUS_UNF_Pos                    5                                                       /*!< ETH STATUS: UNF Position                */\r
+#define ETH_STATUS_UNF_Msk                    (0x01UL << ETH_STATUS_UNF_Pos)                          /*!< ETH STATUS: UNF Mask                    */\r
+#define ETH_STATUS_RI_Pos                     6                                                       /*!< ETH STATUS: RI Position                 */\r
+#define ETH_STATUS_RI_Msk                     (0x01UL << ETH_STATUS_RI_Pos)                           /*!< ETH STATUS: RI Mask                     */\r
+#define ETH_STATUS_RU_Pos                     7                                                       /*!< ETH STATUS: RU Position                 */\r
+#define ETH_STATUS_RU_Msk                     (0x01UL << ETH_STATUS_RU_Pos)                           /*!< ETH STATUS: RU Mask                     */\r
+#define ETH_STATUS_RPS_Pos                    8                                                       /*!< ETH STATUS: RPS Position                */\r
+#define ETH_STATUS_RPS_Msk                    (0x01UL << ETH_STATUS_RPS_Pos)                          /*!< ETH STATUS: RPS Mask                    */\r
+#define ETH_STATUS_RWT_Pos                    9                                                       /*!< ETH STATUS: RWT Position                */\r
+#define ETH_STATUS_RWT_Msk                    (0x01UL << ETH_STATUS_RWT_Pos)                          /*!< ETH STATUS: RWT Mask                    */\r
+#define ETH_STATUS_ETI_Pos                    10                                                      /*!< ETH STATUS: ETI Position                */\r
+#define ETH_STATUS_ETI_Msk                    (0x01UL << ETH_STATUS_ETI_Pos)                          /*!< ETH STATUS: ETI Mask                    */\r
+#define ETH_STATUS_Reserved_12_11_Pos         11                                                      /*!< ETH STATUS: Reserved_12_11 Position     */\r
+#define ETH_STATUS_Reserved_12_11_Msk         (0x03UL << ETH_STATUS_Reserved_12_11_Pos)               /*!< ETH STATUS: Reserved_12_11 Mask         */\r
+#define ETH_STATUS_FBI_Pos                    13                                                      /*!< ETH STATUS: FBI Position                */\r
+#define ETH_STATUS_FBI_Msk                    (0x01UL << ETH_STATUS_FBI_Pos)                          /*!< ETH STATUS: FBI Mask                    */\r
+#define ETH_STATUS_ERI_Pos                    14                                                      /*!< ETH STATUS: ERI Position                */\r
+#define ETH_STATUS_ERI_Msk                    (0x01UL << ETH_STATUS_ERI_Pos)                          /*!< ETH STATUS: ERI Mask                    */\r
+#define ETH_STATUS_AIS_Pos                    15                                                      /*!< ETH STATUS: AIS Position                */\r
+#define ETH_STATUS_AIS_Msk                    (0x01UL << ETH_STATUS_AIS_Pos)                          /*!< ETH STATUS: AIS Mask                    */\r
+#define ETH_STATUS_NIS_Pos                    16                                                      /*!< ETH STATUS: NIS Position                */\r
+#define ETH_STATUS_NIS_Msk                    (0x01UL << ETH_STATUS_NIS_Pos)                          /*!< ETH STATUS: NIS Mask                    */\r
+#define ETH_STATUS_RS_Pos                     17                                                      /*!< ETH STATUS: RS Position                 */\r
+#define ETH_STATUS_RS_Msk                     (0x07UL << ETH_STATUS_RS_Pos)                           /*!< ETH STATUS: RS Mask                     */\r
+#define ETH_STATUS_TS_Pos                     20                                                      /*!< ETH STATUS: TS Position                 */\r
+#define ETH_STATUS_TS_Msk                     (0x07UL << ETH_STATUS_TS_Pos)                           /*!< ETH STATUS: TS Mask                     */\r
+#define ETH_STATUS_EB_Pos                     23                                                      /*!< ETH STATUS: EB Position                 */\r
+#define ETH_STATUS_EB_Msk                     (0x07UL << ETH_STATUS_EB_Pos)                           /*!< ETH STATUS: EB Mask                     */\r
+#define ETH_STATUS_Reserved_26_Pos            26                                                      /*!< ETH STATUS: Reserved_26 Position        */\r
+#define ETH_STATUS_Reserved_26_Msk            (0x01UL << ETH_STATUS_Reserved_26_Pos)                  /*!< ETH STATUS: Reserved_26 Mask            */\r
+#define ETH_STATUS_EMI_Pos                    27                                                      /*!< ETH STATUS: EMI Position                */\r
+#define ETH_STATUS_EMI_Msk                    (0x01UL << ETH_STATUS_EMI_Pos)                          /*!< ETH STATUS: EMI Mask                    */\r
+#define ETH_STATUS_EPI_Pos                    28                                                      /*!< ETH STATUS: EPI Position                */\r
+#define ETH_STATUS_EPI_Msk                    (0x01UL << ETH_STATUS_EPI_Pos)                          /*!< ETH STATUS: EPI Mask                    */\r
+#define ETH_STATUS_TTI_Pos                    29                                                      /*!< ETH STATUS: TTI Position                */\r
+#define ETH_STATUS_TTI_Msk                    (0x01UL << ETH_STATUS_TTI_Pos)                          /*!< ETH STATUS: TTI Mask                    */\r
+#define ETH_STATUS_Reserved_30_Pos            30                                                      /*!< ETH STATUS: Reserved_30 Position        */\r
+#define ETH_STATUS_Reserved_30_Msk            (0x01UL << ETH_STATUS_Reserved_30_Pos)                  /*!< ETH STATUS: Reserved_30 Mask            */\r
+#define ETH_STATUS_Reserved_31_Pos            31                                                      /*!< ETH STATUS: Reserved_31 Position        */\r
+#define ETH_STATUS_Reserved_31_Msk            (0x01UL << ETH_STATUS_Reserved_31_Pos)                  /*!< ETH STATUS: Reserved_31 Mask            */\r
+\r
+/* -----------------------------  ETH_OPERATION_MODE  ----------------------------- */\r
+#define ETH_OPERATION_MODE_Reserved_0_Pos     0                                                       /*!< ETH OPERATION_MODE: Reserved_0 Position */\r
+#define ETH_OPERATION_MODE_Reserved_0_Msk     (0x01UL << ETH_OPERATION_MODE_Reserved_0_Pos)           /*!< ETH OPERATION_MODE: Reserved_0 Mask     */\r
+#define ETH_OPERATION_MODE_SR_Pos             1                                                       /*!< ETH OPERATION_MODE: SR Position         */\r
+#define ETH_OPERATION_MODE_SR_Msk             (0x01UL << ETH_OPERATION_MODE_SR_Pos)                   /*!< ETH OPERATION_MODE: SR Mask             */\r
+#define ETH_OPERATION_MODE_OSF_Pos            2                                                       /*!< ETH OPERATION_MODE: OSF Position        */\r
+#define ETH_OPERATION_MODE_OSF_Msk            (0x01UL << ETH_OPERATION_MODE_OSF_Pos)                  /*!< ETH OPERATION_MODE: OSF Mask            */\r
+#define ETH_OPERATION_MODE_RTC_Pos            3                                                       /*!< ETH OPERATION_MODE: RTC Position        */\r
+#define ETH_OPERATION_MODE_RTC_Msk            (0x03UL << ETH_OPERATION_MODE_RTC_Pos)                  /*!< ETH OPERATION_MODE: RTC Mask            */\r
+#define ETH_OPERATION_MODE_Reserved_5_Pos     5                                                       /*!< ETH OPERATION_MODE: Reserved_5 Position */\r
+#define ETH_OPERATION_MODE_Reserved_5_Msk     (0x01UL << ETH_OPERATION_MODE_Reserved_5_Pos)           /*!< ETH OPERATION_MODE: Reserved_5 Mask     */\r
+#define ETH_OPERATION_MODE_FUF_Pos            6                                                       /*!< ETH OPERATION_MODE: FUF Position        */\r
+#define ETH_OPERATION_MODE_FUF_Msk            (0x01UL << ETH_OPERATION_MODE_FUF_Pos)                  /*!< ETH OPERATION_MODE: FUF Mask            */\r
+#define ETH_OPERATION_MODE_FEF_Pos            7                                                       /*!< ETH OPERATION_MODE: FEF Position        */\r
+#define ETH_OPERATION_MODE_FEF_Msk            (0x01UL << ETH_OPERATION_MODE_FEF_Pos)                  /*!< ETH OPERATION_MODE: FEF Mask            */\r
+#define ETH_OPERATION_MODE_Reserved_12_8_Pos  8                                                       /*!< ETH OPERATION_MODE: Reserved_12_8 Position */\r
+#define ETH_OPERATION_MODE_Reserved_12_8_Msk  (0x1fUL << ETH_OPERATION_MODE_Reserved_12_8_Pos)        /*!< ETH OPERATION_MODE: Reserved_12_8 Mask  */\r
+#define ETH_OPERATION_MODE_ST_Pos             13                                                      /*!< ETH OPERATION_MODE: ST Position         */\r
+#define ETH_OPERATION_MODE_ST_Msk             (0x01UL << ETH_OPERATION_MODE_ST_Pos)                   /*!< ETH OPERATION_MODE: ST Mask             */\r
+#define ETH_OPERATION_MODE_TTC_Pos            14                                                      /*!< ETH OPERATION_MODE: TTC Position        */\r
+#define ETH_OPERATION_MODE_TTC_Msk            (0x07UL << ETH_OPERATION_MODE_TTC_Pos)                  /*!< ETH OPERATION_MODE: TTC Mask            */\r
+#define ETH_OPERATION_MODE_Reserved_19_17_Pos 17                                                      /*!< ETH OPERATION_MODE: Reserved_19_17 Position */\r
+#define ETH_OPERATION_MODE_Reserved_19_17_Msk (0x07UL << ETH_OPERATION_MODE_Reserved_19_17_Pos)       /*!< ETH OPERATION_MODE: Reserved_19_17 Mask */\r
+#define ETH_OPERATION_MODE_FTF_Pos            20                                                      /*!< ETH OPERATION_MODE: FTF Position        */\r
+#define ETH_OPERATION_MODE_FTF_Msk            (0x01UL << ETH_OPERATION_MODE_FTF_Pos)                  /*!< ETH OPERATION_MODE: FTF Mask            */\r
+#define ETH_OPERATION_MODE_TSF_Pos            21                                                      /*!< ETH OPERATION_MODE: TSF Position        */\r
+#define ETH_OPERATION_MODE_TSF_Msk            (0x01UL << ETH_OPERATION_MODE_TSF_Pos)                  /*!< ETH OPERATION_MODE: TSF Mask            */\r
+#define ETH_OPERATION_MODE_Reserved_23_22_Pos 22                                                      /*!< ETH OPERATION_MODE: Reserved_23_22 Position */\r
+#define ETH_OPERATION_MODE_Reserved_23_22_Msk (0x03UL << ETH_OPERATION_MODE_Reserved_23_22_Pos)       /*!< ETH OPERATION_MODE: Reserved_23_22 Mask */\r
+#define ETH_OPERATION_MODE_DFF_Pos            24                                                      /*!< ETH OPERATION_MODE: DFF Position        */\r
+#define ETH_OPERATION_MODE_DFF_Msk            (0x01UL << ETH_OPERATION_MODE_DFF_Pos)                  /*!< ETH OPERATION_MODE: DFF Mask            */\r
+#define ETH_OPERATION_MODE_RSF_Pos            25                                                      /*!< ETH OPERATION_MODE: RSF Position        */\r
+#define ETH_OPERATION_MODE_RSF_Msk            (0x01UL << ETH_OPERATION_MODE_RSF_Pos)                  /*!< ETH OPERATION_MODE: RSF Mask            */\r
+#define ETH_OPERATION_MODE_DT_Pos             26                                                      /*!< ETH OPERATION_MODE: DT Position         */\r
+#define ETH_OPERATION_MODE_DT_Msk             (0x01UL << ETH_OPERATION_MODE_DT_Pos)                   /*!< ETH OPERATION_MODE: DT Mask             */\r
+#define ETH_OPERATION_MODE_Reserved_31_27_Pos 27                                                      /*!< ETH OPERATION_MODE: Reserved_31_27 Position */\r
+#define ETH_OPERATION_MODE_Reserved_31_27_Msk (0x1fUL << ETH_OPERATION_MODE_Reserved_31_27_Pos)       /*!< ETH OPERATION_MODE: Reserved_31_27 Mask */\r
+\r
+/* ----------------------------  ETH_INTERRUPT_ENABLE  ---------------------------- */\r
+#define ETH_INTERRUPT_ENABLE_TIE_Pos          0                                                       /*!< ETH INTERRUPT_ENABLE: TIE Position      */\r
+#define ETH_INTERRUPT_ENABLE_TIE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_TIE_Pos)                /*!< ETH INTERRUPT_ENABLE: TIE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_TSE_Pos          1                                                       /*!< ETH INTERRUPT_ENABLE: TSE Position      */\r
+#define ETH_INTERRUPT_ENABLE_TSE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_TSE_Pos)                /*!< ETH INTERRUPT_ENABLE: TSE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_TUE_Pos          2                                                       /*!< ETH INTERRUPT_ENABLE: TUE Position      */\r
+#define ETH_INTERRUPT_ENABLE_TUE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_TUE_Pos)                /*!< ETH INTERRUPT_ENABLE: TUE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_TJE_Pos          3                                                       /*!< ETH INTERRUPT_ENABLE: TJE Position      */\r
+#define ETH_INTERRUPT_ENABLE_TJE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_TJE_Pos)                /*!< ETH INTERRUPT_ENABLE: TJE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_OVE_Pos          4                                                       /*!< ETH INTERRUPT_ENABLE: OVE Position      */\r
+#define ETH_INTERRUPT_ENABLE_OVE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_OVE_Pos)                /*!< ETH INTERRUPT_ENABLE: OVE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_UNE_Pos          5                                                       /*!< ETH INTERRUPT_ENABLE: UNE Position      */\r
+#define ETH_INTERRUPT_ENABLE_UNE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_UNE_Pos)                /*!< ETH INTERRUPT_ENABLE: UNE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_RIE_Pos          6                                                       /*!< ETH INTERRUPT_ENABLE: RIE Position      */\r
+#define ETH_INTERRUPT_ENABLE_RIE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_RIE_Pos)                /*!< ETH INTERRUPT_ENABLE: RIE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_RUE_Pos          7                                                       /*!< ETH INTERRUPT_ENABLE: RUE Position      */\r
+#define ETH_INTERRUPT_ENABLE_RUE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_RUE_Pos)                /*!< ETH INTERRUPT_ENABLE: RUE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_RSE_Pos          8                                                       /*!< ETH INTERRUPT_ENABLE: RSE Position      */\r
+#define ETH_INTERRUPT_ENABLE_RSE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_RSE_Pos)                /*!< ETH INTERRUPT_ENABLE: RSE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_RWE_Pos          9                                                       /*!< ETH INTERRUPT_ENABLE: RWE Position      */\r
+#define ETH_INTERRUPT_ENABLE_RWE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_RWE_Pos)                /*!< ETH INTERRUPT_ENABLE: RWE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_ETE_Pos          10                                                      /*!< ETH INTERRUPT_ENABLE: ETE Position      */\r
+#define ETH_INTERRUPT_ENABLE_ETE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_ETE_Pos)                /*!< ETH INTERRUPT_ENABLE: ETE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_Reserved_12_11_Pos 11                                                    /*!< ETH INTERRUPT_ENABLE: Reserved_12_11 Position */\r
+#define ETH_INTERRUPT_ENABLE_Reserved_12_11_Msk (0x03UL << ETH_INTERRUPT_ENABLE_Reserved_12_11_Pos)   /*!< ETH INTERRUPT_ENABLE: Reserved_12_11 Mask */\r
+#define ETH_INTERRUPT_ENABLE_FBE_Pos          13                                                      /*!< ETH INTERRUPT_ENABLE: FBE Position      */\r
+#define ETH_INTERRUPT_ENABLE_FBE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_FBE_Pos)                /*!< ETH INTERRUPT_ENABLE: FBE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_ERE_Pos          14                                                      /*!< ETH INTERRUPT_ENABLE: ERE Position      */\r
+#define ETH_INTERRUPT_ENABLE_ERE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_ERE_Pos)                /*!< ETH INTERRUPT_ENABLE: ERE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_AIE_Pos          15                                                      /*!< ETH INTERRUPT_ENABLE: AIE Position      */\r
+#define ETH_INTERRUPT_ENABLE_AIE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_AIE_Pos)                /*!< ETH INTERRUPT_ENABLE: AIE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_NIE_Pos          16                                                      /*!< ETH INTERRUPT_ENABLE: NIE Position      */\r
+#define ETH_INTERRUPT_ENABLE_NIE_Msk          (0x01UL << ETH_INTERRUPT_ENABLE_NIE_Pos)                /*!< ETH INTERRUPT_ENABLE: NIE Mask          */\r
+#define ETH_INTERRUPT_ENABLE_Reserved_31_17_Pos 17                                                    /*!< ETH INTERRUPT_ENABLE: Reserved_31_17 Position */\r
+#define ETH_INTERRUPT_ENABLE_Reserved_31_17_Msk (0x00007fffUL << ETH_INTERRUPT_ENABLE_Reserved_31_17_Pos)/*!< ETH INTERRUPT_ENABLE: Reserved_31_17 Mask */\r
+\r
+/* ----------------  ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER  ---------------- */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos 0                                  /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISFRMCNT Position */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Msk (0x0000ffffUL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISFRMCNT Mask */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos 16                                 /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISCNTOVF Position */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Msk (0x01UL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: MISCNTOVF Mask */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos 17                                 /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFFRMCNT Position */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Msk (0x000007ffUL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFFRMCNT Mask */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos 28                                 /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFCNTOVF Position */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Msk (0x01UL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: OVFCNTOVF Mask */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Pos 29                            /*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: Reserved_31_29\r
+                                                         Position                                                                                  */\r
+#define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Msk (0x07UL << ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_Reserved_31_29_Pos)/*!< ETH MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER: Reserved_31_29\r
+                                                         Mask                                                                                      */\r
+\r
+/* --------------------  ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER  -------------------- */\r
+#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos 0                                               /*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: RIWT Position */\r
+#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Msk (0x000000ffUL << ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos)/*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: RIWT Mask */\r
+#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Pos 8                                      /*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: Reserved_31_8 Position */\r
+#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Msk (0x00ffffffUL << ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_Reserved_31_8_Pos)/*!< ETH RECEIVE_INTERRUPT_WATCHDOG_TIMER: Reserved_31_8 Mask */\r
+\r
+/* -------------------------------  ETH_AHB_STATUS  ------------------------------- */\r
+#define ETH_AHB_STATUS_AHBMS_Pos              0                                                       /*!< ETH AHB_STATUS: AHBMS Position          */\r
+#define ETH_AHB_STATUS_AHBMS_Msk              (0x01UL << ETH_AHB_STATUS_AHBMS_Pos)                    /*!< ETH AHB_STATUS: AHBMS Mask              */\r
+#define ETH_AHB_STATUS_Reserved_1_Pos         1                                                       /*!< ETH AHB_STATUS: Reserved_1 Position     */\r
+#define ETH_AHB_STATUS_Reserved_1_Msk         (0x01UL << ETH_AHB_STATUS_Reserved_1_Pos)               /*!< ETH AHB_STATUS: Reserved_1 Mask         */\r
+#define ETH_AHB_STATUS_Reserved_31_2_Pos      2                                                       /*!< ETH AHB_STATUS: Reserved_31_2 Position  */\r
+#define ETH_AHB_STATUS_Reserved_31_2_Msk      (0x3fffffffUL << ETH_AHB_STATUS_Reserved_31_2_Pos)      /*!< ETH AHB_STATUS: Reserved_31_2 Mask      */\r
+\r
+/* --------------------  ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR  -------------------- */\r
+#define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos 0                                        /*!< ETH CURRENT_HOST_TRANSMIT_DESCRIPTOR: CURTDESAPTR Position */\r
+#define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos)/*!< ETH CURRENT_HOST_TRANSMIT_DESCRIPTOR: CURTDESAPTR Mask */\r
+\r
+/* ---------------------  ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR  -------------------- */\r
+#define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos 0                                         /*!< ETH CURRENT_HOST_RECEIVE_DESCRIPTOR: CURRDESAPTR Position */\r
+#define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos)/*!< ETH CURRENT_HOST_RECEIVE_DESCRIPTOR: CURRDESAPTR Mask */\r
+\r
+/* ------------------  ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS  ------------------ */\r
+#define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos 0                                    /*!< ETH CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS: CURTBUFAPTR Position */\r
+#define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos)/*!< ETH CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS: CURTBUFAPTR Mask */\r
+\r
+/* -------------------  ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS  ------------------ */\r
+#define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos 0                                     /*!< ETH CURRENT_HOST_RECEIVE_BUFFER_ADDRESS: CURRBUFAPTR Position */\r
+#define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Msk (0xffffffffUL << ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos)/*!< ETH CURRENT_HOST_RECEIVE_BUFFER_ADDRESS: CURRBUFAPTR Mask */\r
+\r
+/* -------------------------------  ETH_HW_FEATURE  ------------------------------- */\r
+#define ETH_HW_FEATURE_MIISEL_Pos             0                                                       /*!< ETH HW_FEATURE: MIISEL Position         */\r
+#define ETH_HW_FEATURE_MIISEL_Msk             (0x01UL << ETH_HW_FEATURE_MIISEL_Pos)                   /*!< ETH HW_FEATURE: MIISEL Mask             */\r
+#define ETH_HW_FEATURE_GMIISEL_Pos            1                                                       /*!< ETH HW_FEATURE: GMIISEL Position        */\r
+#define ETH_HW_FEATURE_GMIISEL_Msk            (0x01UL << ETH_HW_FEATURE_GMIISEL_Pos)                  /*!< ETH HW_FEATURE: GMIISEL Mask            */\r
+#define ETH_HW_FEATURE_HDSEL_Pos              2                                                       /*!< ETH HW_FEATURE: HDSEL Position          */\r
+#define ETH_HW_FEATURE_HDSEL_Msk              (0x01UL << ETH_HW_FEATURE_HDSEL_Pos)                    /*!< ETH HW_FEATURE: HDSEL Mask              */\r
+#define ETH_HW_FEATURE_EXTHASHEN_Pos          3                                                       /*!< ETH HW_FEATURE: EXTHASHEN Position      */\r
+#define ETH_HW_FEATURE_EXTHASHEN_Msk          (0x01UL << ETH_HW_FEATURE_EXTHASHEN_Pos)                /*!< ETH HW_FEATURE: EXTHASHEN Mask          */\r
+#define ETH_HW_FEATURE_HASHSEL_Pos            4                                                       /*!< ETH HW_FEATURE: HASHSEL Position        */\r
+#define ETH_HW_FEATURE_HASHSEL_Msk            (0x01UL << ETH_HW_FEATURE_HASHSEL_Pos)                  /*!< ETH HW_FEATURE: HASHSEL Mask            */\r
+#define ETH_HW_FEATURE_ADDMACADRSEL_Pos       5                                                       /*!< ETH HW_FEATURE: ADDMACADRSEL Position   */\r
+#define ETH_HW_FEATURE_ADDMACADRSEL_Msk       (0x01UL << ETH_HW_FEATURE_ADDMACADRSEL_Pos)             /*!< ETH HW_FEATURE: ADDMACADRSEL Mask       */\r
+#define ETH_HW_FEATURE_PCSSEL_Pos             6                                                       /*!< ETH HW_FEATURE: PCSSEL Position         */\r
+#define ETH_HW_FEATURE_PCSSEL_Msk             (0x01UL << ETH_HW_FEATURE_PCSSEL_Pos)                   /*!< ETH HW_FEATURE: PCSSEL Mask             */\r
+#define ETH_HW_FEATURE_L3L4FLTREN_Pos         7                                                       /*!< ETH HW_FEATURE: L3L4FLTREN Position     */\r
+#define ETH_HW_FEATURE_L3L4FLTREN_Msk         (0x01UL << ETH_HW_FEATURE_L3L4FLTREN_Pos)               /*!< ETH HW_FEATURE: L3L4FLTREN Mask         */\r
+#define ETH_HW_FEATURE_SMASEL_Pos             8                                                       /*!< ETH HW_FEATURE: SMASEL Position         */\r
+#define ETH_HW_FEATURE_SMASEL_Msk             (0x01UL << ETH_HW_FEATURE_SMASEL_Pos)                   /*!< ETH HW_FEATURE: SMASEL Mask             */\r
+#define ETH_HW_FEATURE_RWKSEL_Pos             9                                                       /*!< ETH HW_FEATURE: RWKSEL Position         */\r
+#define ETH_HW_FEATURE_RWKSEL_Msk             (0x01UL << ETH_HW_FEATURE_RWKSEL_Pos)                   /*!< ETH HW_FEATURE: RWKSEL Mask             */\r
+#define ETH_HW_FEATURE_MGKSEL_Pos             10                                                      /*!< ETH HW_FEATURE: MGKSEL Position         */\r
+#define ETH_HW_FEATURE_MGKSEL_Msk             (0x01UL << ETH_HW_FEATURE_MGKSEL_Pos)                   /*!< ETH HW_FEATURE: MGKSEL Mask             */\r
+#define ETH_HW_FEATURE_MMCSEL_Pos             11                                                      /*!< ETH HW_FEATURE: MMCSEL Position         */\r
+#define ETH_HW_FEATURE_MMCSEL_Msk             (0x01UL << ETH_HW_FEATURE_MMCSEL_Pos)                   /*!< ETH HW_FEATURE: MMCSEL Mask             */\r
+#define ETH_HW_FEATURE_TSVER1SEL_Pos          12                                                      /*!< ETH HW_FEATURE: TSVER1SEL Position      */\r
+#define ETH_HW_FEATURE_TSVER1SEL_Msk          (0x01UL << ETH_HW_FEATURE_TSVER1SEL_Pos)                /*!< ETH HW_FEATURE: TSVER1SEL Mask          */\r
+#define ETH_HW_FEATURE_TSVER2SEL_Pos          13                                                      /*!< ETH HW_FEATURE: TSVER2SEL Position      */\r
+#define ETH_HW_FEATURE_TSVER2SEL_Msk          (0x01UL << ETH_HW_FEATURE_TSVER2SEL_Pos)                /*!< ETH HW_FEATURE: TSVER2SEL Mask          */\r
+#define ETH_HW_FEATURE_EEESEL_Pos             14                                                      /*!< ETH HW_FEATURE: EEESEL Position         */\r
+#define ETH_HW_FEATURE_EEESEL_Msk             (0x01UL << ETH_HW_FEATURE_EEESEL_Pos)                   /*!< ETH HW_FEATURE: EEESEL Mask             */\r
+#define ETH_HW_FEATURE_AVSEL_Pos              15                                                      /*!< ETH HW_FEATURE: AVSEL Position          */\r
+#define ETH_HW_FEATURE_AVSEL_Msk              (0x01UL << ETH_HW_FEATURE_AVSEL_Pos)                    /*!< ETH HW_FEATURE: AVSEL Mask              */\r
+#define ETH_HW_FEATURE_TXCOESEL_Pos           16                                                      /*!< ETH HW_FEATURE: TXCOESEL Position       */\r
+#define ETH_HW_FEATURE_TXCOESEL_Msk           (0x01UL << ETH_HW_FEATURE_TXCOESEL_Pos)                 /*!< ETH HW_FEATURE: TXCOESEL Mask           */\r
+#define ETH_HW_FEATURE_RXTYP1COE_Pos          17                                                      /*!< ETH HW_FEATURE: RXTYP1COE Position      */\r
+#define ETH_HW_FEATURE_RXTYP1COE_Msk          (0x01UL << ETH_HW_FEATURE_RXTYP1COE_Pos)                /*!< ETH HW_FEATURE: RXTYP1COE Mask          */\r
+#define ETH_HW_FEATURE_RXTYP2COE_Pos          18                                                      /*!< ETH HW_FEATURE: RXTYP2COE Position      */\r
+#define ETH_HW_FEATURE_RXTYP2COE_Msk          (0x01UL << ETH_HW_FEATURE_RXTYP2COE_Pos)                /*!< ETH HW_FEATURE: RXTYP2COE Mask          */\r
+#define ETH_HW_FEATURE_RXFIFOSIZE_Pos         19                                                      /*!< ETH HW_FEATURE: RXFIFOSIZE Position     */\r
+#define ETH_HW_FEATURE_RXFIFOSIZE_Msk         (0x01UL << ETH_HW_FEATURE_RXFIFOSIZE_Pos)               /*!< ETH HW_FEATURE: RXFIFOSIZE Mask         */\r
+#define ETH_HW_FEATURE_RXCHCNT_Pos            20                                                      /*!< ETH HW_FEATURE: RXCHCNT Position        */\r
+#define ETH_HW_FEATURE_RXCHCNT_Msk            (0x03UL << ETH_HW_FEATURE_RXCHCNT_Pos)                  /*!< ETH HW_FEATURE: RXCHCNT Mask            */\r
+#define ETH_HW_FEATURE_TXCHCNT_Pos            22                                                      /*!< ETH HW_FEATURE: TXCHCNT Position        */\r
+#define ETH_HW_FEATURE_TXCHCNT_Msk            (0x03UL << ETH_HW_FEATURE_TXCHCNT_Pos)                  /*!< ETH HW_FEATURE: TXCHCNT Mask            */\r
+#define ETH_HW_FEATURE_ENHDESSEL_Pos          24                                                      /*!< ETH HW_FEATURE: ENHDESSEL Position      */\r
+#define ETH_HW_FEATURE_ENHDESSEL_Msk          (0x01UL << ETH_HW_FEATURE_ENHDESSEL_Pos)                /*!< ETH HW_FEATURE: ENHDESSEL Mask          */\r
+#define ETH_HW_FEATURE_INTTSEN_Pos            25                                                      /*!< ETH HW_FEATURE: INTTSEN Position        */\r
+#define ETH_HW_FEATURE_INTTSEN_Msk            (0x01UL << ETH_HW_FEATURE_INTTSEN_Pos)                  /*!< ETH HW_FEATURE: INTTSEN Mask            */\r
+#define ETH_HW_FEATURE_FLEXIPPSEN_Pos         26                                                      /*!< ETH HW_FEATURE: FLEXIPPSEN Position     */\r
+#define ETH_HW_FEATURE_FLEXIPPSEN_Msk         (0x01UL << ETH_HW_FEATURE_FLEXIPPSEN_Pos)               /*!< ETH HW_FEATURE: FLEXIPPSEN Mask         */\r
+#define ETH_HW_FEATURE_SAVLANINS_Pos          27                                                      /*!< ETH HW_FEATURE: SAVLANINS Position      */\r
+#define ETH_HW_FEATURE_SAVLANINS_Msk          (0x01UL << ETH_HW_FEATURE_SAVLANINS_Pos)                /*!< ETH HW_FEATURE: SAVLANINS Mask          */\r
+#define ETH_HW_FEATURE_ACTPHYIF_Pos           28                                                      /*!< ETH HW_FEATURE: ACTPHYIF Position       */\r
+#define ETH_HW_FEATURE_ACTPHYIF_Msk           (0x07UL << ETH_HW_FEATURE_ACTPHYIF_Pos)                 /*!< ETH HW_FEATURE: ACTPHYIF Mask           */\r
+#define ETH_HW_FEATURE_Reserved_31_Pos        31                                                      /*!< ETH HW_FEATURE: Reserved_31 Position    */\r
+#define ETH_HW_FEATURE_Reserved_31_Msk        (0x01UL << ETH_HW_FEATURE_Reserved_31_Pos)              /*!< ETH HW_FEATURE: Reserved_31 Mask        */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================           Group 'USB' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  USB_GOTGCTL  -------------------------------- */\r
+#define USB_GOTGCTL_SesReqScs_Pos             0                                                       /*!< USB GOTGCTL: SesReqScs Position         */\r
+#define USB_GOTGCTL_SesReqScs_Msk             (0x01UL << USB_GOTGCTL_SesReqScs_Pos)                   /*!< USB GOTGCTL: SesReqScs Mask             */\r
+#define USB_GOTGCTL_SesReq_Pos                1                                                       /*!< USB GOTGCTL: SesReq Position            */\r
+#define USB_GOTGCTL_SesReq_Msk                (0x01UL << USB_GOTGCTL_SesReq_Pos)                      /*!< USB GOTGCTL: SesReq Mask                */\r
+#define USB_GOTGCTL_VbvalidOvEn_Pos           2                                                       /*!< USB GOTGCTL: VbvalidOvEn Position       */\r
+#define USB_GOTGCTL_VbvalidOvEn_Msk           (0x01UL << USB_GOTGCTL_VbvalidOvEn_Pos)                 /*!< USB GOTGCTL: VbvalidOvEn Mask           */\r
+#define USB_GOTGCTL_VbvalidOvVal_Pos          3                                                       /*!< USB GOTGCTL: VbvalidOvVal Position      */\r
+#define USB_GOTGCTL_VbvalidOvVal_Msk          (0x01UL << USB_GOTGCTL_VbvalidOvVal_Pos)                /*!< USB GOTGCTL: VbvalidOvVal Mask          */\r
+#define USB_GOTGCTL_AvalidOvEn_Pos            4                                                       /*!< USB GOTGCTL: AvalidOvEn Position        */\r
+#define USB_GOTGCTL_AvalidOvEn_Msk            (0x01UL << USB_GOTGCTL_AvalidOvEn_Pos)                  /*!< USB GOTGCTL: AvalidOvEn Mask            */\r
+#define USB_GOTGCTL_AvalidOvVal_Pos           5                                                       /*!< USB GOTGCTL: AvalidOvVal Position       */\r
+#define USB_GOTGCTL_AvalidOvVal_Msk           (0x01UL << USB_GOTGCTL_AvalidOvVal_Pos)                 /*!< USB GOTGCTL: AvalidOvVal Mask           */\r
+#define USB_GOTGCTL_BvalidOvEn_Pos            6                                                       /*!< USB GOTGCTL: BvalidOvEn Position        */\r
+#define USB_GOTGCTL_BvalidOvEn_Msk            (0x01UL << USB_GOTGCTL_BvalidOvEn_Pos)                  /*!< USB GOTGCTL: BvalidOvEn Mask            */\r
+#define USB_GOTGCTL_BvalidOvVal_Pos           7                                                       /*!< USB GOTGCTL: BvalidOvVal Position       */\r
+#define USB_GOTGCTL_BvalidOvVal_Msk           (0x01UL << USB_GOTGCTL_BvalidOvVal_Pos)                 /*!< USB GOTGCTL: BvalidOvVal Mask           */\r
+#define USB_GOTGCTL_HstNegScs_Pos             8                                                       /*!< USB GOTGCTL: HstNegScs Position         */\r
+#define USB_GOTGCTL_HstNegScs_Msk             (0x01UL << USB_GOTGCTL_HstNegScs_Pos)                   /*!< USB GOTGCTL: HstNegScs Mask             */\r
+#define USB_GOTGCTL_HNPReq_Pos                9                                                       /*!< USB GOTGCTL: HNPReq Position            */\r
+#define USB_GOTGCTL_HNPReq_Msk                (0x01UL << USB_GOTGCTL_HNPReq_Pos)                      /*!< USB GOTGCTL: HNPReq Mask                */\r
+#define USB_GOTGCTL_HstSetHNPEn_Pos           10                                                      /*!< USB GOTGCTL: HstSetHNPEn Position       */\r
+#define USB_GOTGCTL_HstSetHNPEn_Msk           (0x01UL << USB_GOTGCTL_HstSetHNPEn_Pos)                 /*!< USB GOTGCTL: HstSetHNPEn Mask           */\r
+#define USB_GOTGCTL_DevHNPEn_Pos              11                                                      /*!< USB GOTGCTL: DevHNPEn Position          */\r
+#define USB_GOTGCTL_DevHNPEn_Msk              (0x01UL << USB_GOTGCTL_DevHNPEn_Pos)                    /*!< USB GOTGCTL: DevHNPEn Mask              */\r
+#define USB_GOTGCTL_ConlDSts_Pos              16                                                      /*!< USB GOTGCTL: ConlDSts Position          */\r
+#define USB_GOTGCTL_ConlDSts_Msk              (0x01UL << USB_GOTGCTL_ConlDSts_Pos)                    /*!< USB GOTGCTL: ConlDSts Mask              */\r
+#define USB_GOTGCTL_DbncTime_Pos              17                                                      /*!< USB GOTGCTL: DbncTime Position          */\r
+#define USB_GOTGCTL_DbncTime_Msk              (0x01UL << USB_GOTGCTL_DbncTime_Pos)                    /*!< USB GOTGCTL: DbncTime Mask              */\r
+#define USB_GOTGCTL_ASesVId_Pos               18                                                      /*!< USB GOTGCTL: ASesVId Position           */\r
+#define USB_GOTGCTL_ASesVId_Msk               (0x01UL << USB_GOTGCTL_ASesVId_Pos)                     /*!< USB GOTGCTL: ASesVId Mask               */\r
+#define USB_GOTGCTL_BSesVld_Pos               19                                                      /*!< USB GOTGCTL: BSesVld Position           */\r
+#define USB_GOTGCTL_BSesVld_Msk               (0x01UL << USB_GOTGCTL_BSesVld_Pos)                     /*!< USB GOTGCTL: BSesVld Mask               */\r
+#define USB_GOTGCTL_OTGVer_Pos                20                                                      /*!< USB GOTGCTL: OTGVer Position            */\r
+#define USB_GOTGCTL_OTGVer_Msk                (0x01UL << USB_GOTGCTL_OTGVer_Pos)                      /*!< USB GOTGCTL: OTGVer Mask                */\r
+\r
+/* ---------------------------------  USB_GOTGINT  -------------------------------- */\r
+#define USB_GOTGINT_SesEndDet_Pos             2                                                       /*!< USB GOTGINT: SesEndDet Position         */\r
+#define USB_GOTGINT_SesEndDet_Msk             (0x01UL << USB_GOTGINT_SesEndDet_Pos)                   /*!< USB GOTGINT: SesEndDet Mask             */\r
+#define USB_GOTGINT_SesReqSucStsChng_Pos      8                                                       /*!< USB GOTGINT: SesReqSucStsChng Position  */\r
+#define USB_GOTGINT_SesReqSucStsChng_Msk      (0x01UL << USB_GOTGINT_SesReqSucStsChng_Pos)            /*!< USB GOTGINT: SesReqSucStsChng Mask      */\r
+#define USB_GOTGINT_HstNegSucStsChng_Pos      9                                                       /*!< USB GOTGINT: HstNegSucStsChng Position  */\r
+#define USB_GOTGINT_HstNegSucStsChng_Msk      (0x01UL << USB_GOTGINT_HstNegSucStsChng_Pos)            /*!< USB GOTGINT: HstNegSucStsChng Mask      */\r
+#define USB_GOTGINT_HstNegDet_Pos             17                                                      /*!< USB GOTGINT: HstNegDet Position         */\r
+#define USB_GOTGINT_HstNegDet_Msk             (0x01UL << USB_GOTGINT_HstNegDet_Pos)                   /*!< USB GOTGINT: HstNegDet Mask             */\r
+#define USB_GOTGINT_ADevTOUTChg_Pos           18                                                      /*!< USB GOTGINT: ADevTOUTChg Position       */\r
+#define USB_GOTGINT_ADevTOUTChg_Msk           (0x01UL << USB_GOTGINT_ADevTOUTChg_Pos)                 /*!< USB GOTGINT: ADevTOUTChg Mask           */\r
+#define USB_GOTGINT_DbnceDone_Pos             19                                                      /*!< USB GOTGINT: DbnceDone Position         */\r
+#define USB_GOTGINT_DbnceDone_Msk             (0x01UL << USB_GOTGINT_DbnceDone_Pos)                   /*!< USB GOTGINT: DbnceDone Mask             */\r
+\r
+/* ---------------------------------  USB_GAHBCFG  -------------------------------- */\r
+#define USB_GAHBCFG_GlblIntrMsk_Pos           0                                                       /*!< USB GAHBCFG: GlblIntrMsk Position       */\r
+#define USB_GAHBCFG_GlblIntrMsk_Msk           (0x01UL << USB_GAHBCFG_GlblIntrMsk_Pos)                 /*!< USB GAHBCFG: GlblIntrMsk Mask           */\r
+#define USB_GAHBCFG_HBstLen_Pos               1                                                       /*!< USB GAHBCFG: HBstLen Position           */\r
+#define USB_GAHBCFG_HBstLen_Msk               (0x0fUL << USB_GAHBCFG_HBstLen_Pos)                     /*!< USB GAHBCFG: HBstLen Mask               */\r
+#define USB_GAHBCFG_DMAEn_Pos                 5                                                       /*!< USB GAHBCFG: DMAEn Position             */\r
+#define USB_GAHBCFG_DMAEn_Msk                 (0x01UL << USB_GAHBCFG_DMAEn_Pos)                       /*!< USB GAHBCFG: DMAEn Mask                 */\r
+#define USB_GAHBCFG_NPTxFEmpLvl_Pos           7                                                       /*!< USB GAHBCFG: NPTxFEmpLvl Position       */\r
+#define USB_GAHBCFG_NPTxFEmpLvl_Msk           (0x01UL << USB_GAHBCFG_NPTxFEmpLvl_Pos)                 /*!< USB GAHBCFG: NPTxFEmpLvl Mask           */\r
+#define USB_GAHBCFG_PTxFEmpLvl_Pos            8                                                       /*!< USB GAHBCFG: PTxFEmpLvl Position        */\r
+#define USB_GAHBCFG_PTxFEmpLvl_Msk            (0x01UL << USB_GAHBCFG_PTxFEmpLvl_Pos)                  /*!< USB GAHBCFG: PTxFEmpLvl Mask            */\r
+\r
+/* ---------------------------------  USB_GUSBCFG  -------------------------------- */\r
+#define USB_GUSBCFG_TOutCal_Pos               0                                                       /*!< USB GUSBCFG: TOutCal Position           */\r
+#define USB_GUSBCFG_TOutCal_Msk               (0x07UL << USB_GUSBCFG_TOutCal_Pos)                     /*!< USB GUSBCFG: TOutCal Mask               */\r
+#define USB_GUSBCFG_PHYSel_Pos                6                                                       /*!< USB GUSBCFG: PHYSel Position            */\r
+#define USB_GUSBCFG_PHYSel_Msk                (0x01UL << USB_GUSBCFG_PHYSel_Pos)                      /*!< USB GUSBCFG: PHYSel Mask                */\r
+#define USB_GUSBCFG_SRPCap_Pos                8                                                       /*!< USB GUSBCFG: SRPCap Position            */\r
+#define USB_GUSBCFG_SRPCap_Msk                (0x01UL << USB_GUSBCFG_SRPCap_Pos)                      /*!< USB GUSBCFG: SRPCap Mask                */\r
+#define USB_GUSBCFG_HNPCap_Pos                9                                                       /*!< USB GUSBCFG: HNPCap Position            */\r
+#define USB_GUSBCFG_HNPCap_Msk                (0x01UL << USB_GUSBCFG_HNPCap_Pos)                      /*!< USB GUSBCFG: HNPCap Mask                */\r
+#define USB_GUSBCFG_USBTrdTim_Pos             10                                                      /*!< USB GUSBCFG: USBTrdTim Position         */\r
+#define USB_GUSBCFG_USBTrdTim_Msk             (0x0fUL << USB_GUSBCFG_USBTrdTim_Pos)                   /*!< USB GUSBCFG: USBTrdTim Mask             */\r
+#define USB_GUSBCFG_OtgI2CSel_Pos             16                                                      /*!< USB GUSBCFG: OtgI2CSel Position         */\r
+#define USB_GUSBCFG_OtgI2CSel_Msk             (0x01UL << USB_GUSBCFG_OtgI2CSel_Pos)                   /*!< USB GUSBCFG: OtgI2CSel Mask             */\r
+#define USB_GUSBCFG_TxEndDelay_Pos            28                                                      /*!< USB GUSBCFG: TxEndDelay Position        */\r
+#define USB_GUSBCFG_TxEndDelay_Msk            (0x01UL << USB_GUSBCFG_TxEndDelay_Pos)                  /*!< USB GUSBCFG: TxEndDelay Mask            */\r
+#define USB_GUSBCFG_ForceHstMode_Pos          29                                                      /*!< USB GUSBCFG: ForceHstMode Position      */\r
+#define USB_GUSBCFG_ForceHstMode_Msk          (0x01UL << USB_GUSBCFG_ForceHstMode_Pos)                /*!< USB GUSBCFG: ForceHstMode Mask          */\r
+#define USB_GUSBCFG_ForceDevMode_Pos          30                                                      /*!< USB GUSBCFG: ForceDevMode Position      */\r
+#define USB_GUSBCFG_ForceDevMode_Msk          (0x01UL << USB_GUSBCFG_ForceDevMode_Pos)                /*!< USB GUSBCFG: ForceDevMode Mask          */\r
+#define USB_GUSBCFG_CTP_Pos                   31                                                      /*!< USB GUSBCFG: CTP Position               */\r
+#define USB_GUSBCFG_CTP_Msk                   (0x01UL << USB_GUSBCFG_CTP_Pos)                         /*!< USB GUSBCFG: CTP Mask                   */\r
+\r
+/* ---------------------------------  USB_GRSTCTL  -------------------------------- */\r
+#define USB_GRSTCTL_CSftRst_Pos               0                                                       /*!< USB GRSTCTL: CSftRst Position           */\r
+#define USB_GRSTCTL_CSftRst_Msk               (0x01UL << USB_GRSTCTL_CSftRst_Pos)                     /*!< USB GRSTCTL: CSftRst Mask               */\r
+#define USB_GRSTCTL_FrmCntrRst_Pos            2                                                       /*!< USB GRSTCTL: FrmCntrRst Position        */\r
+#define USB_GRSTCTL_FrmCntrRst_Msk            (0x01UL << USB_GRSTCTL_FrmCntrRst_Pos)                  /*!< USB GRSTCTL: FrmCntrRst Mask            */\r
+#define USB_GRSTCTL_RxFFlsh_Pos               4                                                       /*!< USB GRSTCTL: RxFFlsh Position           */\r
+#define USB_GRSTCTL_RxFFlsh_Msk               (0x01UL << USB_GRSTCTL_RxFFlsh_Pos)                     /*!< USB GRSTCTL: RxFFlsh Mask               */\r
+#define USB_GRSTCTL_TxFFlsh_Pos               5                                                       /*!< USB GRSTCTL: TxFFlsh Position           */\r
+#define USB_GRSTCTL_TxFFlsh_Msk               (0x01UL << USB_GRSTCTL_TxFFlsh_Pos)                     /*!< USB GRSTCTL: TxFFlsh Mask               */\r
+#define USB_GRSTCTL_TxFNum_Pos                6                                                       /*!< USB GRSTCTL: TxFNum Position            */\r
+#define USB_GRSTCTL_TxFNum_Msk                (0x1fUL << USB_GRSTCTL_TxFNum_Pos)                      /*!< USB GRSTCTL: TxFNum Mask                */\r
+#define USB_GRSTCTL_DMAReq_Pos                30                                                      /*!< USB GRSTCTL: DMAReq Position            */\r
+#define USB_GRSTCTL_DMAReq_Msk                (0x01UL << USB_GRSTCTL_DMAReq_Pos)                      /*!< USB GRSTCTL: DMAReq Mask                */\r
+#define USB_GRSTCTL_AHBIdle_Pos               31                                                      /*!< USB GRSTCTL: AHBIdle Position           */\r
+#define USB_GRSTCTL_AHBIdle_Msk               (0x01UL << USB_GRSTCTL_AHBIdle_Pos)                     /*!< USB GRSTCTL: AHBIdle Mask               */\r
+\r
+/* ----------------------------  USB_GINTSTS_HOSTMODE  ---------------------------- */\r
+#define USB_GINTSTS_HOSTMODE_CurMod_Pos       0                                                       /*!< USB GINTSTS_HOSTMODE: CurMod Position   */\r
+#define USB_GINTSTS_HOSTMODE_CurMod_Msk       (0x01UL << USB_GINTSTS_HOSTMODE_CurMod_Pos)             /*!< USB GINTSTS_HOSTMODE: CurMod Mask       */\r
+#define USB_GINTSTS_HOSTMODE_ModeMis_Pos      1                                                       /*!< USB GINTSTS_HOSTMODE: ModeMis Position  */\r
+#define USB_GINTSTS_HOSTMODE_ModeMis_Msk      (0x01UL << USB_GINTSTS_HOSTMODE_ModeMis_Pos)            /*!< USB GINTSTS_HOSTMODE: ModeMis Mask      */\r
+#define USB_GINTSTS_HOSTMODE_OTGInt_Pos       2                                                       /*!< USB GINTSTS_HOSTMODE: OTGInt Position   */\r
+#define USB_GINTSTS_HOSTMODE_OTGInt_Msk       (0x01UL << USB_GINTSTS_HOSTMODE_OTGInt_Pos)             /*!< USB GINTSTS_HOSTMODE: OTGInt Mask       */\r
+#define USB_GINTSTS_HOSTMODE_Sof_Pos          3                                                       /*!< USB GINTSTS_HOSTMODE: Sof Position      */\r
+#define USB_GINTSTS_HOSTMODE_Sof_Msk          (0x01UL << USB_GINTSTS_HOSTMODE_Sof_Pos)                /*!< USB GINTSTS_HOSTMODE: Sof Mask          */\r
+#define USB_GINTSTS_HOSTMODE_RxFLvl_Pos       4                                                       /*!< USB GINTSTS_HOSTMODE: RxFLvl Position   */\r
+#define USB_GINTSTS_HOSTMODE_RxFLvl_Msk       (0x01UL << USB_GINTSTS_HOSTMODE_RxFLvl_Pos)             /*!< USB GINTSTS_HOSTMODE: RxFLvl Mask       */\r
+#define USB_GINTSTS_HOSTMODE_incomplP_Pos     21                                                      /*!< USB GINTSTS_HOSTMODE: incomplP Position */\r
+#define USB_GINTSTS_HOSTMODE_incomplP_Msk     (0x01UL << USB_GINTSTS_HOSTMODE_incomplP_Pos)           /*!< USB GINTSTS_HOSTMODE: incomplP Mask     */\r
+#define USB_GINTSTS_HOSTMODE_PrtInt_Pos       24                                                      /*!< USB GINTSTS_HOSTMODE: PrtInt Position   */\r
+#define USB_GINTSTS_HOSTMODE_PrtInt_Msk       (0x01UL << USB_GINTSTS_HOSTMODE_PrtInt_Pos)             /*!< USB GINTSTS_HOSTMODE: PrtInt Mask       */\r
+#define USB_GINTSTS_HOSTMODE_HChInt_Pos       25                                                      /*!< USB GINTSTS_HOSTMODE: HChInt Position   */\r
+#define USB_GINTSTS_HOSTMODE_HChInt_Msk       (0x01UL << USB_GINTSTS_HOSTMODE_HChInt_Pos)             /*!< USB GINTSTS_HOSTMODE: HChInt Mask       */\r
+#define USB_GINTSTS_HOSTMODE_PTxFEmp_Pos      26                                                      /*!< USB GINTSTS_HOSTMODE: PTxFEmp Position  */\r
+#define USB_GINTSTS_HOSTMODE_PTxFEmp_Msk      (0x01UL << USB_GINTSTS_HOSTMODE_PTxFEmp_Pos)            /*!< USB GINTSTS_HOSTMODE: PTxFEmp Mask      */\r
+#define USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos 28                                                      /*!< USB GINTSTS_HOSTMODE: ConIDStsChng Position */\r
+#define USB_GINTSTS_HOSTMODE_ConIDStsChng_Msk (0x01UL << USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos)       /*!< USB GINTSTS_HOSTMODE: ConIDStsChng Mask */\r
+#define USB_GINTSTS_HOSTMODE_DisconnInt_Pos   29                                                      /*!< USB GINTSTS_HOSTMODE: DisconnInt Position */\r
+#define USB_GINTSTS_HOSTMODE_DisconnInt_Msk   (0x01UL << USB_GINTSTS_HOSTMODE_DisconnInt_Pos)         /*!< USB GINTSTS_HOSTMODE: DisconnInt Mask   */\r
+#define USB_GINTSTS_HOSTMODE_SessReqInt_Pos   30                                                      /*!< USB GINTSTS_HOSTMODE: SessReqInt Position */\r
+#define USB_GINTSTS_HOSTMODE_SessReqInt_Msk   (0x01UL << USB_GINTSTS_HOSTMODE_SessReqInt_Pos)         /*!< USB GINTSTS_HOSTMODE: SessReqInt Mask   */\r
+#define USB_GINTSTS_HOSTMODE_WkUpInt_Pos      31                                                      /*!< USB GINTSTS_HOSTMODE: WkUpInt Position  */\r
+#define USB_GINTSTS_HOSTMODE_WkUpInt_Msk      (0x01UL << USB_GINTSTS_HOSTMODE_WkUpInt_Pos)            /*!< USB GINTSTS_HOSTMODE: WkUpInt Mask      */\r
+\r
+/* ---------------------------  USB_GINTSTS_DEVICEMODE  --------------------------- */\r
+#define USB_GINTSTS_DEVICEMODE_CurMod_Pos     0                                                       /*!< USB GINTSTS_DEVICEMODE: CurMod Position */\r
+#define USB_GINTSTS_DEVICEMODE_CurMod_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_CurMod_Pos)           /*!< USB GINTSTS_DEVICEMODE: CurMod Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_ModeMis_Pos    1                                                       /*!< USB GINTSTS_DEVICEMODE: ModeMis Position */\r
+#define USB_GINTSTS_DEVICEMODE_ModeMis_Msk    (0x01UL << USB_GINTSTS_DEVICEMODE_ModeMis_Pos)          /*!< USB GINTSTS_DEVICEMODE: ModeMis Mask    */\r
+#define USB_GINTSTS_DEVICEMODE_OTGInt_Pos     2                                                       /*!< USB GINTSTS_DEVICEMODE: OTGInt Position */\r
+#define USB_GINTSTS_DEVICEMODE_OTGInt_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_OTGInt_Pos)           /*!< USB GINTSTS_DEVICEMODE: OTGInt Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_Sof_Pos        3                                                       /*!< USB GINTSTS_DEVICEMODE: Sof Position    */\r
+#define USB_GINTSTS_DEVICEMODE_Sof_Msk        (0x01UL << USB_GINTSTS_DEVICEMODE_Sof_Pos)              /*!< USB GINTSTS_DEVICEMODE: Sof Mask        */\r
+#define USB_GINTSTS_DEVICEMODE_RxFLvl_Pos     4                                                       /*!< USB GINTSTS_DEVICEMODE: RxFLvl Position */\r
+#define USB_GINTSTS_DEVICEMODE_RxFLvl_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_RxFLvl_Pos)           /*!< USB GINTSTS_DEVICEMODE: RxFLvl Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_GINNakEff_Pos  6                                                       /*!< USB GINTSTS_DEVICEMODE: GINNakEff Position */\r
+#define USB_GINTSTS_DEVICEMODE_GINNakEff_Msk  (0x01UL << USB_GINTSTS_DEVICEMODE_GINNakEff_Pos)        /*!< USB GINTSTS_DEVICEMODE: GINNakEff Mask  */\r
+#define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos 7                                                       /*!< USB GINTSTS_DEVICEMODE: GOUTNakEff Position */\r
+#define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos)       /*!< USB GINTSTS_DEVICEMODE: GOUTNakEff Mask */\r
+#define USB_GINTSTS_DEVICEMODE_ErlySusp_Pos   10                                                      /*!< USB GINTSTS_DEVICEMODE: ErlySusp Position */\r
+#define USB_GINTSTS_DEVICEMODE_ErlySusp_Msk   (0x01UL << USB_GINTSTS_DEVICEMODE_ErlySusp_Pos)         /*!< USB GINTSTS_DEVICEMODE: ErlySusp Mask   */\r
+#define USB_GINTSTS_DEVICEMODE_USBSusp_Pos    11                                                      /*!< USB GINTSTS_DEVICEMODE: USBSusp Position */\r
+#define USB_GINTSTS_DEVICEMODE_USBSusp_Msk    (0x01UL << USB_GINTSTS_DEVICEMODE_USBSusp_Pos)          /*!< USB GINTSTS_DEVICEMODE: USBSusp Mask    */\r
+#define USB_GINTSTS_DEVICEMODE_USBRst_Pos     12                                                      /*!< USB GINTSTS_DEVICEMODE: USBRst Position */\r
+#define USB_GINTSTS_DEVICEMODE_USBRst_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_USBRst_Pos)           /*!< USB GINTSTS_DEVICEMODE: USBRst Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_EnumDone_Pos   13                                                      /*!< USB GINTSTS_DEVICEMODE: EnumDone Position */\r
+#define USB_GINTSTS_DEVICEMODE_EnumDone_Msk   (0x01UL << USB_GINTSTS_DEVICEMODE_EnumDone_Pos)         /*!< USB GINTSTS_DEVICEMODE: EnumDone Mask   */\r
+#define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos 14                                                      /*!< USB GINTSTS_DEVICEMODE: ISOOutDrop Position */\r
+#define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos)       /*!< USB GINTSTS_DEVICEMODE: ISOOutDrop Mask */\r
+#define USB_GINTSTS_DEVICEMODE_EOPF_Pos       15                                                      /*!< USB GINTSTS_DEVICEMODE: EOPF Position   */\r
+#define USB_GINTSTS_DEVICEMODE_EOPF_Msk       (0x01UL << USB_GINTSTS_DEVICEMODE_EOPF_Pos)             /*!< USB GINTSTS_DEVICEMODE: EOPF Mask       */\r
+#define USB_GINTSTS_DEVICEMODE_IEPInt_Pos     18                                                      /*!< USB GINTSTS_DEVICEMODE: IEPInt Position */\r
+#define USB_GINTSTS_DEVICEMODE_IEPInt_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_IEPInt_Pos)           /*!< USB GINTSTS_DEVICEMODE: IEPInt Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_OEPInt_Pos     19                                                      /*!< USB GINTSTS_DEVICEMODE: OEPInt Position */\r
+#define USB_GINTSTS_DEVICEMODE_OEPInt_Msk     (0x01UL << USB_GINTSTS_DEVICEMODE_OEPInt_Pos)           /*!< USB GINTSTS_DEVICEMODE: OEPInt Mask     */\r
+#define USB_GINTSTS_DEVICEMODE_incompISOIN_Pos 20                                                     /*!< USB GINTSTS_DEVICEMODE: incompISOIN Position */\r
+#define USB_GINTSTS_DEVICEMODE_incompISOIN_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_incompISOIN_Pos)     /*!< USB GINTSTS_DEVICEMODE: incompISOIN Mask */\r
+#define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos 21                                                    /*!< USB GINTSTS_DEVICEMODE: incomplSOOUT Position */\r
+#define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos)   /*!< USB GINTSTS_DEVICEMODE: incomplSOOUT Mask */\r
+#define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos 28                                                    /*!< USB GINTSTS_DEVICEMODE: ConIDStsChng Position */\r
+#define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos)   /*!< USB GINTSTS_DEVICEMODE: ConIDStsChng Mask */\r
+#define USB_GINTSTS_DEVICEMODE_SessReqInt_Pos 30                                                      /*!< USB GINTSTS_DEVICEMODE: SessReqInt Position */\r
+#define USB_GINTSTS_DEVICEMODE_SessReqInt_Msk (0x01UL << USB_GINTSTS_DEVICEMODE_SessReqInt_Pos)       /*!< USB GINTSTS_DEVICEMODE: SessReqInt Mask */\r
+#define USB_GINTSTS_DEVICEMODE_WkUpInt_Pos    31                                                      /*!< USB GINTSTS_DEVICEMODE: WkUpInt Position */\r
+#define USB_GINTSTS_DEVICEMODE_WkUpInt_Msk    (0x01UL << USB_GINTSTS_DEVICEMODE_WkUpInt_Pos)          /*!< USB GINTSTS_DEVICEMODE: WkUpInt Mask    */\r
+\r
+/* ----------------------------  USB_GINTMSK_HOSTMODE  ---------------------------- */\r
+#define USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos   1                                                       /*!< USB GINTMSK_HOSTMODE: ModeMisMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_ModeMisMsk_Msk   (0x01UL << USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos)         /*!< USB GINTMSK_HOSTMODE: ModeMisMsk Mask   */\r
+#define USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos    2                                                       /*!< USB GINTMSK_HOSTMODE: OTGIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_OTGIntMsk_Msk    (0x01UL << USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos)          /*!< USB GINTMSK_HOSTMODE: OTGIntMsk Mask    */\r
+#define USB_GINTMSK_HOSTMODE_SofMsk_Pos       3                                                       /*!< USB GINTMSK_HOSTMODE: SofMsk Position   */\r
+#define USB_GINTMSK_HOSTMODE_SofMsk_Msk       (0x01UL << USB_GINTMSK_HOSTMODE_SofMsk_Pos)             /*!< USB GINTMSK_HOSTMODE: SofMsk Mask       */\r
+#define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos    4                                                       /*!< USB GINTMSK_HOSTMODE: RxFLvlMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk    (0x01UL << USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos)          /*!< USB GINTMSK_HOSTMODE: RxFLvlMsk Mask    */\r
+#define USB_GINTMSK_HOSTMODE_incomplPMsk_Pos  21                                                      /*!< USB GINTMSK_HOSTMODE: incomplPMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_incomplPMsk_Msk  (0x01UL << USB_GINTMSK_HOSTMODE_incomplPMsk_Pos)        /*!< USB GINTMSK_HOSTMODE: incomplPMsk Mask  */\r
+#define USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos    24                                                      /*!< USB GINTMSK_HOSTMODE: PrtIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk    (0x01UL << USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos)          /*!< USB GINTMSK_HOSTMODE: PrtIntMsk Mask    */\r
+#define USB_GINTMSK_HOSTMODE_HChIntMsk_Pos    25                                                      /*!< USB GINTMSK_HOSTMODE: HChIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_HChIntMsk_Msk    (0x01UL << USB_GINTMSK_HOSTMODE_HChIntMsk_Pos)          /*!< USB GINTMSK_HOSTMODE: HChIntMsk Mask    */\r
+#define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos   26                                                      /*!< USB GINTMSK_HOSTMODE: PTxFEmpMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Msk   (0x01UL << USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos)         /*!< USB GINTMSK_HOSTMODE: PTxFEmpMsk Mask   */\r
+#define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos 28                                                   /*!< USB GINTMSK_HOSTMODE: ConIDStsChngMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos) /*!< USB GINTMSK_HOSTMODE: ConIDStsChngMsk Mask */\r
+#define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos 29                                                     /*!< USB GINTMSK_HOSTMODE: DisconnIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos)     /*!< USB GINTMSK_HOSTMODE: DisconnIntMsk Mask */\r
+#define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos 30                                                     /*!< USB GINTMSK_HOSTMODE: SessReqIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Msk (0x01UL << USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos)     /*!< USB GINTMSK_HOSTMODE: SessReqIntMsk Mask */\r
+#define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos   31                                                      /*!< USB GINTMSK_HOSTMODE: WkUpIntMsk Position */\r
+#define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk   (0x01UL << USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos)         /*!< USB GINTMSK_HOSTMODE: WkUpIntMsk Mask   */\r
+\r
+/* ---------------------------  USB_GINTMSK_DEVICEMODE  --------------------------- */\r
+#define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos 1                                                       /*!< USB GINTMSK_DEVICEMODE: ModeMisMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos)       /*!< USB GINTMSK_DEVICEMODE: ModeMisMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos  2                                                       /*!< USB GINTMSK_DEVICEMODE: OTGIntMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Msk  (0x01UL << USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos)        /*!< USB GINTMSK_DEVICEMODE: OTGIntMsk Mask  */\r
+#define USB_GINTMSK_DEVICEMODE_SofMsk_Pos     3                                                       /*!< USB GINTMSK_DEVICEMODE: SofMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_SofMsk_Msk     (0x01UL << USB_GINTMSK_DEVICEMODE_SofMsk_Pos)           /*!< USB GINTMSK_DEVICEMODE: SofMsk Mask     */\r
+#define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos  4                                                       /*!< USB GINTMSK_DEVICEMODE: RxFLvlMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Msk  (0x01UL << USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos)        /*!< USB GINTMSK_DEVICEMODE: RxFLvlMsk Mask  */\r
+#define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos 6                                                     /*!< USB GINTMSK_DEVICEMODE: GINNakEffMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos)   /*!< USB GINTMSK_DEVICEMODE: GINNakEffMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos 7                                                    /*!< USB GINTMSK_DEVICEMODE: GOUTNakEffMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: GOUTNakEffMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos 10                                                     /*!< USB GINTMSK_DEVICEMODE: ErlySuspMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos)     /*!< USB GINTMSK_DEVICEMODE: ErlySuspMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos 11                                                      /*!< USB GINTMSK_DEVICEMODE: USBSuspMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos)       /*!< USB GINTMSK_DEVICEMODE: USBSuspMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos  12                                                      /*!< USB GINTMSK_DEVICEMODE: USBRstMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_USBRstMsk_Msk  (0x01UL << USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos)        /*!< USB GINTMSK_DEVICEMODE: USBRstMsk Mask  */\r
+#define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos 13                                                     /*!< USB GINTMSK_DEVICEMODE: EnumDoneMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos)     /*!< USB GINTMSK_DEVICEMODE: EnumDoneMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos 14                                                   /*!< USB GINTMSK_DEVICEMODE: ISOOutDropMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: ISOOutDropMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos    15                                                      /*!< USB GINTMSK_DEVICEMODE: EOPFMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_EOPFMsk_Msk    (0x01UL << USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos)          /*!< USB GINTMSK_DEVICEMODE: EOPFMsk Mask    */\r
+#define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos  18                                                      /*!< USB GINTMSK_DEVICEMODE: IEPIntMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Msk  (0x01UL << USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos)        /*!< USB GINTMSK_DEVICEMODE: IEPIntMsk Mask  */\r
+#define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos  19                                                      /*!< USB GINTMSK_DEVICEMODE: OEPIntMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Msk  (0x01UL << USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos)        /*!< USB GINTMSK_DEVICEMODE: OEPIntMsk Mask  */\r
+#define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos 20                                                  /*!< USB GINTMSK_DEVICEMODE: incompISOINMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos)/*!< USB GINTMSK_DEVICEMODE: incompISOINMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos 21                                                 /*!< USB GINTMSK_DEVICEMODE: incomplSOOUTMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos)/*!< USB GINTMSK_DEVICEMODE: incomplSOOUTMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos 28                                                 /*!< USB GINTMSK_DEVICEMODE: ConIDStsChngMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos)/*!< USB GINTMSK_DEVICEMODE: ConIDStsChngMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos 30                                                   /*!< USB GINTMSK_DEVICEMODE: SessReqIntMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos) /*!< USB GINTMSK_DEVICEMODE: SessReqIntMsk Mask */\r
+#define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos 31                                                      /*!< USB GINTMSK_DEVICEMODE: WkUpIntMsk Position */\r
+#define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Msk (0x01UL << USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos)       /*!< USB GINTMSK_DEVICEMODE: WkUpIntMsk Mask */\r
+\r
+/* ----------------------------  USB_GRXSTSR_HOSTMODE  ---------------------------- */\r
+#define USB_GRXSTSR_HOSTMODE_ChNum_Pos        0                                                       /*!< USB GRXSTSR_HOSTMODE: ChNum Position    */\r
+#define USB_GRXSTSR_HOSTMODE_ChNum_Msk        (0x0fUL << USB_GRXSTSR_HOSTMODE_ChNum_Pos)              /*!< USB GRXSTSR_HOSTMODE: ChNum Mask        */\r
+#define USB_GRXSTSR_HOSTMODE_BCnt_Pos         4                                                       /*!< USB GRXSTSR_HOSTMODE: BCnt Position     */\r
+#define USB_GRXSTSR_HOSTMODE_BCnt_Msk         (0x000007ffUL << USB_GRXSTSR_HOSTMODE_BCnt_Pos)         /*!< USB GRXSTSR_HOSTMODE: BCnt Mask         */\r
+#define USB_GRXSTSR_HOSTMODE_DPID_Pos         15                                                      /*!< USB GRXSTSR_HOSTMODE: DPID Position     */\r
+#define USB_GRXSTSR_HOSTMODE_DPID_Msk         (0x03UL << USB_GRXSTSR_HOSTMODE_DPID_Pos)               /*!< USB GRXSTSR_HOSTMODE: DPID Mask         */\r
+#define USB_GRXSTSR_HOSTMODE_PktSts_Pos       17                                                      /*!< USB GRXSTSR_HOSTMODE: PktSts Position   */\r
+#define USB_GRXSTSR_HOSTMODE_PktSts_Msk       (0x0fUL << USB_GRXSTSR_HOSTMODE_PktSts_Pos)             /*!< USB GRXSTSR_HOSTMODE: PktSts Mask       */\r
+\r
+/* ---------------------------  USB_GRXSTSR_DEVICEMODE  --------------------------- */\r
+#define USB_GRXSTSR_DEVICEMODE_EPNum_Pos      0                                                       /*!< USB GRXSTSR_DEVICEMODE: EPNum Position  */\r
+#define USB_GRXSTSR_DEVICEMODE_EPNum_Msk      (0x0fUL << USB_GRXSTSR_DEVICEMODE_EPNum_Pos)            /*!< USB GRXSTSR_DEVICEMODE: EPNum Mask      */\r
+#define USB_GRXSTSR_DEVICEMODE_BCnt_Pos       4                                                       /*!< USB GRXSTSR_DEVICEMODE: BCnt Position   */\r
+#define USB_GRXSTSR_DEVICEMODE_BCnt_Msk       (0x000007ffUL << USB_GRXSTSR_DEVICEMODE_BCnt_Pos)       /*!< USB GRXSTSR_DEVICEMODE: BCnt Mask       */\r
+#define USB_GRXSTSR_DEVICEMODE_DPID_Pos       15                                                      /*!< USB GRXSTSR_DEVICEMODE: DPID Position   */\r
+#define USB_GRXSTSR_DEVICEMODE_DPID_Msk       (0x03UL << USB_GRXSTSR_DEVICEMODE_DPID_Pos)             /*!< USB GRXSTSR_DEVICEMODE: DPID Mask       */\r
+#define USB_GRXSTSR_DEVICEMODE_PktSts_Pos     17                                                      /*!< USB GRXSTSR_DEVICEMODE: PktSts Position */\r
+#define USB_GRXSTSR_DEVICEMODE_PktSts_Msk     (0x0fUL << USB_GRXSTSR_DEVICEMODE_PktSts_Pos)           /*!< USB GRXSTSR_DEVICEMODE: PktSts Mask     */\r
+#define USB_GRXSTSR_DEVICEMODE_FN_Pos         21                                                      /*!< USB GRXSTSR_DEVICEMODE: FN Position     */\r
+#define USB_GRXSTSR_DEVICEMODE_FN_Msk         (0x0fUL << USB_GRXSTSR_DEVICEMODE_FN_Pos)               /*!< USB GRXSTSR_DEVICEMODE: FN Mask         */\r
+\r
+/* ----------------------------  USB_GRXSTSP_HOSTMODE  ---------------------------- */\r
+#define USB_GRXSTSP_HOSTMODE_ChNum_Pos        0                                                       /*!< USB GRXSTSP_HOSTMODE: ChNum Position    */\r
+#define USB_GRXSTSP_HOSTMODE_ChNum_Msk        (0x0fUL << USB_GRXSTSP_HOSTMODE_ChNum_Pos)              /*!< USB GRXSTSP_HOSTMODE: ChNum Mask        */\r
+#define USB_GRXSTSP_HOSTMODE_BCnt_Pos         4                                                       /*!< USB GRXSTSP_HOSTMODE: BCnt Position     */\r
+#define USB_GRXSTSP_HOSTMODE_BCnt_Msk         (0x000007ffUL << USB_GRXSTSP_HOSTMODE_BCnt_Pos)         /*!< USB GRXSTSP_HOSTMODE: BCnt Mask         */\r
+#define USB_GRXSTSP_HOSTMODE_DPID_Pos         15                                                      /*!< USB GRXSTSP_HOSTMODE: DPID Position     */\r
+#define USB_GRXSTSP_HOSTMODE_DPID_Msk         (0x03UL << USB_GRXSTSP_HOSTMODE_DPID_Pos)               /*!< USB GRXSTSP_HOSTMODE: DPID Mask         */\r
+#define USB_GRXSTSP_HOSTMODE_PktSts_Pos       17                                                      /*!< USB GRXSTSP_HOSTMODE: PktSts Position   */\r
+#define USB_GRXSTSP_HOSTMODE_PktSts_Msk       (0x0fUL << USB_GRXSTSP_HOSTMODE_PktSts_Pos)             /*!< USB GRXSTSP_HOSTMODE: PktSts Mask       */\r
+\r
+/* ---------------------------  USB_GRXSTSP_DEVICEMODE  --------------------------- */\r
+#define USB_GRXSTSP_DEVICEMODE_EPNum_Pos      0                                                       /*!< USB GRXSTSP_DEVICEMODE: EPNum Position  */\r
+#define USB_GRXSTSP_DEVICEMODE_EPNum_Msk      (0x0fUL << USB_GRXSTSP_DEVICEMODE_EPNum_Pos)            /*!< USB GRXSTSP_DEVICEMODE: EPNum Mask      */\r
+#define USB_GRXSTSP_DEVICEMODE_BCnt_Pos       4                                                       /*!< USB GRXSTSP_DEVICEMODE: BCnt Position   */\r
+#define USB_GRXSTSP_DEVICEMODE_BCnt_Msk       (0x000007ffUL << USB_GRXSTSP_DEVICEMODE_BCnt_Pos)       /*!< USB GRXSTSP_DEVICEMODE: BCnt Mask       */\r
+#define USB_GRXSTSP_DEVICEMODE_DPID_Pos       15                                                      /*!< USB GRXSTSP_DEVICEMODE: DPID Position   */\r
+#define USB_GRXSTSP_DEVICEMODE_DPID_Msk       (0x03UL << USB_GRXSTSP_DEVICEMODE_DPID_Pos)             /*!< USB GRXSTSP_DEVICEMODE: DPID Mask       */\r
+#define USB_GRXSTSP_DEVICEMODE_PktSts_Pos     17                                                      /*!< USB GRXSTSP_DEVICEMODE: PktSts Position */\r
+#define USB_GRXSTSP_DEVICEMODE_PktSts_Msk     (0x0fUL << USB_GRXSTSP_DEVICEMODE_PktSts_Pos)           /*!< USB GRXSTSP_DEVICEMODE: PktSts Mask     */\r
+#define USB_GRXSTSP_DEVICEMODE_FN_Pos         21                                                      /*!< USB GRXSTSP_DEVICEMODE: FN Position     */\r
+#define USB_GRXSTSP_DEVICEMODE_FN_Msk         (0x0fUL << USB_GRXSTSP_DEVICEMODE_FN_Pos)               /*!< USB GRXSTSP_DEVICEMODE: FN Mask         */\r
+\r
+/* ---------------------------------  USB_GRXFSIZ  -------------------------------- */\r
+#define USB_GRXFSIZ_RxFDep_Pos                0                                                       /*!< USB GRXFSIZ: RxFDep Position            */\r
+#define USB_GRXFSIZ_RxFDep_Msk                (0x0000ffffUL << USB_GRXFSIZ_RxFDep_Pos)                /*!< USB GRXFSIZ: RxFDep Mask                */\r
+\r
+/* ---------------------------  USB_GNPTXFSIZ_HOSTMODE  --------------------------- */\r
+#define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos 0                                                      /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFStAddr Position */\r
+#define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Msk (0x0000ffffUL << USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos)/*!< USB GNPTXFSIZ_HOSTMODE: NPTxFStAddr Mask */\r
+#define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos   16                                                      /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFDep Position */\r
+#define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Msk   (0x0000ffffUL << USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos)   /*!< USB GNPTXFSIZ_HOSTMODE: NPTxFDep Mask   */\r
+\r
+/* --------------------------  USB_GNPTXFSIZ_DEVICEMODE  -------------------------- */\r
+#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Pos 0                                                 /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0StAddr Position */\r
+#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Msk (0x0000ffffUL << USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Pos)/*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0StAddr Mask */\r
+#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos 16                                                   /*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0Dep Position */\r
+#define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Msk (0x0000ffffUL << USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos)/*!< USB GNPTXFSIZ_DEVICEMODE: INEPTxF0Dep Mask */\r
+\r
+/* --------------------------------  USB_GNPTXSTS  -------------------------------- */\r
+#define USB_GNPTXSTS_NPTxFSpcAvail_Pos        0                                                       /*!< USB GNPTXSTS: NPTxFSpcAvail Position    */\r
+#define USB_GNPTXSTS_NPTxFSpcAvail_Msk        (0x0000ffffUL << USB_GNPTXSTS_NPTxFSpcAvail_Pos)        /*!< USB GNPTXSTS: NPTxFSpcAvail Mask        */\r
+#define USB_GNPTXSTS_NPTxQSpcAvail_Pos        16                                                      /*!< USB GNPTXSTS: NPTxQSpcAvail Position    */\r
+#define USB_GNPTXSTS_NPTxQSpcAvail_Msk        (0x000000ffUL << USB_GNPTXSTS_NPTxQSpcAvail_Pos)        /*!< USB GNPTXSTS: NPTxQSpcAvail Mask        */\r
+#define USB_GNPTXSTS_NPTxQTop_Pos             24                                                      /*!< USB GNPTXSTS: NPTxQTop Position         */\r
+#define USB_GNPTXSTS_NPTxQTop_Msk             (0x7fUL << USB_GNPTXSTS_NPTxQTop_Pos)                   /*!< USB GNPTXSTS: NPTxQTop Mask             */\r
+\r
+/* ----------------------------------  USB_GUID  ---------------------------------- */\r
+#define USB_GUID_MOD_REV_Pos                  0                                                       /*!< USB GUID: MOD_REV Position              */\r
+#define USB_GUID_MOD_REV_Msk                  (0x000000ffUL << USB_GUID_MOD_REV_Pos)                  /*!< USB GUID: MOD_REV Mask                  */\r
+#define USB_GUID_MOD_TYPE_Pos                 8                                                       /*!< USB GUID: MOD_TYPE Position             */\r
+#define USB_GUID_MOD_TYPE_Msk                 (0x000000ffUL << USB_GUID_MOD_TYPE_Pos)                 /*!< USB GUID: MOD_TYPE Mask                 */\r
+#define USB_GUID_MOD_NUMBER_Pos               16                                                      /*!< USB GUID: MOD_NUMBER Position           */\r
+#define USB_GUID_MOD_NUMBER_Msk               (0x0000ffffUL << USB_GUID_MOD_NUMBER_Pos)               /*!< USB GUID: MOD_NUMBER Mask               */\r
+\r
+/* --------------------------------  USB_GDFIFOCFG  ------------------------------- */\r
+#define USB_GDFIFOCFG_GDFIFOCfg_Pos           0                                                       /*!< USB GDFIFOCFG: GDFIFOCfg Position       */\r
+#define USB_GDFIFOCFG_GDFIFOCfg_Msk           (0x0000ffffUL << USB_GDFIFOCFG_GDFIFOCfg_Pos)           /*!< USB GDFIFOCFG: GDFIFOCfg Mask           */\r
+#define USB_GDFIFOCFG_EPInfoBaseAddr_Pos      16                                                      /*!< USB GDFIFOCFG: EPInfoBaseAddr Position  */\r
+#define USB_GDFIFOCFG_EPInfoBaseAddr_Msk      (0x0000ffffUL << USB_GDFIFOCFG_EPInfoBaseAddr_Pos)      /*!< USB GDFIFOCFG: EPInfoBaseAddr Mask      */\r
+\r
+/* --------------------------------  USB_HPTXFSIZ  -------------------------------- */\r
+#define USB_HPTXFSIZ_PTxFStAddr_Pos           0                                                       /*!< USB HPTXFSIZ: PTxFStAddr Position       */\r
+#define USB_HPTXFSIZ_PTxFStAddr_Msk           (0x0000ffffUL << USB_HPTXFSIZ_PTxFStAddr_Pos)           /*!< USB HPTXFSIZ: PTxFStAddr Mask           */\r
+#define USB_HPTXFSIZ_PTxFSize_Pos             16                                                      /*!< USB HPTXFSIZ: PTxFSize Position         */\r
+#define USB_HPTXFSIZ_PTxFSize_Msk             (0x0000ffffUL << USB_HPTXFSIZ_PTxFSize_Pos)             /*!< USB HPTXFSIZ: PTxFSize Mask             */\r
+\r
+/* --------------------------------  USB_DIEPTXF1  -------------------------------- */\r
+#define USB_DIEPTXF1_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF1: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF1_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF1_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF1: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF1_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF1: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF1_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF1_INEPnTxFDep_Pos)          /*!< USB DIEPTXF1: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF2  -------------------------------- */\r
+#define USB_DIEPTXF2_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF2: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF2_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF2_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF2: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF2_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF2: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF2_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF2_INEPnTxFDep_Pos)          /*!< USB DIEPTXF2: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF3  -------------------------------- */\r
+#define USB_DIEPTXF3_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF3: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF3_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF3_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF3: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF3_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF3: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF3_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF3_INEPnTxFDep_Pos)          /*!< USB DIEPTXF3: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF4  -------------------------------- */\r
+#define USB_DIEPTXF4_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF4: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF4_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF4_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF4: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF4_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF4: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF4_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF4_INEPnTxFDep_Pos)          /*!< USB DIEPTXF4: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF5  -------------------------------- */\r
+#define USB_DIEPTXF5_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF5: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF5_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF5_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF5: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF5_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF5: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF5_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF5_INEPnTxFDep_Pos)          /*!< USB DIEPTXF5: INEPnTxFDep Mask          */\r
+\r
+/* --------------------------------  USB_DIEPTXF6  -------------------------------- */\r
+#define USB_DIEPTXF6_INEPnTxFStAddr_Pos       0                                                       /*!< USB DIEPTXF6: INEPnTxFStAddr Position   */\r
+#define USB_DIEPTXF6_INEPnTxFStAddr_Msk       (0x0000ffffUL << USB_DIEPTXF6_INEPnTxFStAddr_Pos)       /*!< USB DIEPTXF6: INEPnTxFStAddr Mask       */\r
+#define USB_DIEPTXF6_INEPnTxFDep_Pos          16                                                      /*!< USB DIEPTXF6: INEPnTxFDep Position      */\r
+#define USB_DIEPTXF6_INEPnTxFDep_Msk          (0x0000ffffUL << USB_DIEPTXF6_INEPnTxFDep_Pos)          /*!< USB DIEPTXF6: INEPnTxFDep Mask          */\r
+\r
+/* ----------------------------------  USB_HCFG  ---------------------------------- */\r
+#define USB_HCFG_FSLSPclkSel_Pos              0                                                       /*!< USB HCFG: FSLSPclkSel Position          */\r
+#define USB_HCFG_FSLSPclkSel_Msk              (0x03UL << USB_HCFG_FSLSPclkSel_Pos)                    /*!< USB HCFG: FSLSPclkSel Mask              */\r
+#define USB_HCFG_FSLSSupp_Pos                 2                                                       /*!< USB HCFG: FSLSSupp Position             */\r
+#define USB_HCFG_FSLSSupp_Msk                 (0x01UL << USB_HCFG_FSLSSupp_Pos)                       /*!< USB HCFG: FSLSSupp Mask                 */\r
+#define USB_HCFG_DescDMA_Pos                  23                                                      /*!< USB HCFG: DescDMA Position              */\r
+#define USB_HCFG_DescDMA_Msk                  (0x01UL << USB_HCFG_DescDMA_Pos)                        /*!< USB HCFG: DescDMA Mask                  */\r
+#define USB_HCFG_FrListEn_Pos                 24                                                      /*!< USB HCFG: FrListEn Position             */\r
+#define USB_HCFG_FrListEn_Msk                 (0x03UL << USB_HCFG_FrListEn_Pos)                       /*!< USB HCFG: FrListEn Mask                 */\r
+#define USB_HCFG_PerSchedEna_Pos              26                                                      /*!< USB HCFG: PerSchedEna Position          */\r
+#define USB_HCFG_PerSchedEna_Msk              (0x01UL << USB_HCFG_PerSchedEna_Pos)                    /*!< USB HCFG: PerSchedEna Mask              */\r
+\r
+/* ----------------------------------  USB_HFIR  ---------------------------------- */\r
+#define USB_HFIR_FrInt_Pos                    0                                                       /*!< USB HFIR: FrInt Position                */\r
+#define USB_HFIR_FrInt_Msk                    (0x0000ffffUL << USB_HFIR_FrInt_Pos)                    /*!< USB HFIR: FrInt Mask                    */\r
+#define USB_HFIR_HFIRRldCtrl_Pos              16                                                      /*!< USB HFIR: HFIRRldCtrl Position          */\r
+#define USB_HFIR_HFIRRldCtrl_Msk              (0x01UL << USB_HFIR_HFIRRldCtrl_Pos)                    /*!< USB HFIR: HFIRRldCtrl Mask              */\r
+\r
+/* ----------------------------------  USB_HFNUM  --------------------------------- */\r
+#define USB_HFNUM_FrNum_Pos                   0                                                       /*!< USB HFNUM: FrNum Position               */\r
+#define USB_HFNUM_FrNum_Msk                   (0x0000ffffUL << USB_HFNUM_FrNum_Pos)                   /*!< USB HFNUM: FrNum Mask                   */\r
+#define USB_HFNUM_FrRem_Pos                   16                                                      /*!< USB HFNUM: FrRem Position               */\r
+#define USB_HFNUM_FrRem_Msk                   (0x0000ffffUL << USB_HFNUM_FrRem_Pos)                   /*!< USB HFNUM: FrRem Mask                   */\r
+\r
+/* ---------------------------------  USB_HPTXSTS  -------------------------------- */\r
+#define USB_HPTXSTS_PTxFSpcAvail_Pos          0                                                       /*!< USB HPTXSTS: PTxFSpcAvail Position      */\r
+#define USB_HPTXSTS_PTxFSpcAvail_Msk          (0x0000ffffUL << USB_HPTXSTS_PTxFSpcAvail_Pos)          /*!< USB HPTXSTS: PTxFSpcAvail Mask          */\r
+#define USB_HPTXSTS_PTxQSpcAvail_Pos          16                                                      /*!< USB HPTXSTS: PTxQSpcAvail Position      */\r
+#define USB_HPTXSTS_PTxQSpcAvail_Msk          (0x000000ffUL << USB_HPTXSTS_PTxQSpcAvail_Pos)          /*!< USB HPTXSTS: PTxQSpcAvail Mask          */\r
+#define USB_HPTXSTS_PTxQTop_Pos               24                                                      /*!< USB HPTXSTS: PTxQTop Position           */\r
+#define USB_HPTXSTS_PTxQTop_Msk               (0x000000ffUL << USB_HPTXSTS_PTxQTop_Pos)               /*!< USB HPTXSTS: PTxQTop Mask               */\r
+\r
+/* ----------------------------------  USB_HAINT  --------------------------------- */\r
+#define USB_HAINT_HAINT_Pos                   0                                                       /*!< USB HAINT: HAINT Position               */\r
+#define USB_HAINT_HAINT_Msk                   (0x00003fffUL << USB_HAINT_HAINT_Pos)                   /*!< USB HAINT: HAINT Mask                   */\r
+\r
+/* --------------------------------  USB_HAINTMSK  -------------------------------- */\r
+#define USB_HAINTMSK_HAINTMsk_Pos             0                                                       /*!< USB HAINTMSK: HAINTMsk Position         */\r
+#define USB_HAINTMSK_HAINTMsk_Msk             (0x00003fffUL << USB_HAINTMSK_HAINTMsk_Pos)             /*!< USB HAINTMSK: HAINTMsk Mask             */\r
+\r
+/* --------------------------------  USB_HFLBADDR  -------------------------------- */\r
+#define USB_HFLBADDR_Starting_Address_Pos     0                                                       /*!< USB HFLBADDR: Starting_Address Position */\r
+#define USB_HFLBADDR_Starting_Address_Msk     (0xffffffffUL << USB_HFLBADDR_Starting_Address_Pos)     /*!< USB HFLBADDR: Starting_Address Mask     */\r
+\r
+/* ----------------------------------  USB_HPRT  ---------------------------------- */\r
+#define USB_HPRT_PrtConnSts_Pos               0                                                       /*!< USB HPRT: PrtConnSts Position           */\r
+#define USB_HPRT_PrtConnSts_Msk               (0x01UL << USB_HPRT_PrtConnSts_Pos)                     /*!< USB HPRT: PrtConnSts Mask               */\r
+#define USB_HPRT_PrtConnDet_Pos               1                                                       /*!< USB HPRT: PrtConnDet Position           */\r
+#define USB_HPRT_PrtConnDet_Msk               (0x01UL << USB_HPRT_PrtConnDet_Pos)                     /*!< USB HPRT: PrtConnDet Mask               */\r
+#define USB_HPRT_PrtEna_Pos                   2                                                       /*!< USB HPRT: PrtEna Position               */\r
+#define USB_HPRT_PrtEna_Msk                   (0x01UL << USB_HPRT_PrtEna_Pos)                         /*!< USB HPRT: PrtEna Mask                   */\r
+#define USB_HPRT_PrtEnChng_Pos                3                                                       /*!< USB HPRT: PrtEnChng Position            */\r
+#define USB_HPRT_PrtEnChng_Msk                (0x01UL << USB_HPRT_PrtEnChng_Pos)                      /*!< USB HPRT: PrtEnChng Mask                */\r
+#define USB_HPRT_PrtOvrCurrAct_Pos            4                                                       /*!< USB HPRT: PrtOvrCurrAct Position        */\r
+#define USB_HPRT_PrtOvrCurrAct_Msk            (0x01UL << USB_HPRT_PrtOvrCurrAct_Pos)                  /*!< USB HPRT: PrtOvrCurrAct Mask            */\r
+#define USB_HPRT_PrtOvrCurrChng_Pos           5                                                       /*!< USB HPRT: PrtOvrCurrChng Position       */\r
+#define USB_HPRT_PrtOvrCurrChng_Msk           (0x01UL << USB_HPRT_PrtOvrCurrChng_Pos)                 /*!< USB HPRT: PrtOvrCurrChng Mask           */\r
+#define USB_HPRT_PrtRes_Pos                   6                                                       /*!< USB HPRT: PrtRes Position               */\r
+#define USB_HPRT_PrtRes_Msk                   (0x01UL << USB_HPRT_PrtRes_Pos)                         /*!< USB HPRT: PrtRes Mask                   */\r
+#define USB_HPRT_PrtSusp_Pos                  7                                                       /*!< USB HPRT: PrtSusp Position              */\r
+#define USB_HPRT_PrtSusp_Msk                  (0x01UL << USB_HPRT_PrtSusp_Pos)                        /*!< USB HPRT: PrtSusp Mask                  */\r
+#define USB_HPRT_PrtRst_Pos                   8                                                       /*!< USB HPRT: PrtRst Position               */\r
+#define USB_HPRT_PrtRst_Msk                   (0x01UL << USB_HPRT_PrtRst_Pos)                         /*!< USB HPRT: PrtRst Mask                   */\r
+#define USB_HPRT_PrtLnSts_Pos                 10                                                      /*!< USB HPRT: PrtLnSts Position             */\r
+#define USB_HPRT_PrtLnSts_Msk                 (0x03UL << USB_HPRT_PrtLnSts_Pos)                       /*!< USB HPRT: PrtLnSts Mask                 */\r
+#define USB_HPRT_PrtPwr_Pos                   12                                                      /*!< USB HPRT: PrtPwr Position               */\r
+#define USB_HPRT_PrtPwr_Msk                   (0x01UL << USB_HPRT_PrtPwr_Pos)                         /*!< USB HPRT: PrtPwr Mask                   */\r
+#define USB_HPRT_PrtSpd_Pos                   17                                                      /*!< USB HPRT: PrtSpd Position               */\r
+#define USB_HPRT_PrtSpd_Msk                   (0x03UL << USB_HPRT_PrtSpd_Pos)                         /*!< USB HPRT: PrtSpd Mask                   */\r
+\r
+/* ----------------------------------  USB_DCFG  ---------------------------------- */\r
+#define USB_DCFG_DevSpd_Pos                   0                                                       /*!< USB DCFG: DevSpd Position               */\r
+#define USB_DCFG_DevSpd_Msk                   (0x03UL << USB_DCFG_DevSpd_Pos)                         /*!< USB DCFG: DevSpd Mask                   */\r
+#define USB_DCFG_NZStsOUTHShk_Pos             2                                                       /*!< USB DCFG: NZStsOUTHShk Position         */\r
+#define USB_DCFG_NZStsOUTHShk_Msk             (0x01UL << USB_DCFG_NZStsOUTHShk_Pos)                   /*!< USB DCFG: NZStsOUTHShk Mask             */\r
+#define USB_DCFG_DevAddr_Pos                  4                                                       /*!< USB DCFG: DevAddr Position              */\r
+#define USB_DCFG_DevAddr_Msk                  (0x7fUL << USB_DCFG_DevAddr_Pos)                        /*!< USB DCFG: DevAddr Mask                  */\r
+#define USB_DCFG_PerFrInt_Pos                 11                                                      /*!< USB DCFG: PerFrInt Position             */\r
+#define USB_DCFG_PerFrInt_Msk                 (0x03UL << USB_DCFG_PerFrInt_Pos)                       /*!< USB DCFG: PerFrInt Mask                 */\r
+#define USB_DCFG_DescDMA_Pos                  23                                                      /*!< USB DCFG: DescDMA Position              */\r
+#define USB_DCFG_DescDMA_Msk                  (0x01UL << USB_DCFG_DescDMA_Pos)                        /*!< USB DCFG: DescDMA Mask                  */\r
+#define USB_DCFG_PerSchIntvl_Pos              24                                                      /*!< USB DCFG: PerSchIntvl Position          */\r
+#define USB_DCFG_PerSchIntvl_Msk              (0x03UL << USB_DCFG_PerSchIntvl_Pos)                    /*!< USB DCFG: PerSchIntvl Mask              */\r
+\r
+/* ----------------------------------  USB_DCTL  ---------------------------------- */\r
+#define USB_DCTL_RmtWkUpSig_Pos               0                                                       /*!< USB DCTL: RmtWkUpSig Position           */\r
+#define USB_DCTL_RmtWkUpSig_Msk               (0x01UL << USB_DCTL_RmtWkUpSig_Pos)                     /*!< USB DCTL: RmtWkUpSig Mask               */\r
+#define USB_DCTL_SftDiscon_Pos                1                                                       /*!< USB DCTL: SftDiscon Position            */\r
+#define USB_DCTL_SftDiscon_Msk                (0x01UL << USB_DCTL_SftDiscon_Pos)                      /*!< USB DCTL: SftDiscon Mask                */\r
+#define USB_DCTL_GNPINNakSts_Pos              2                                                       /*!< USB DCTL: GNPINNakSts Position          */\r
+#define USB_DCTL_GNPINNakSts_Msk              (0x01UL << USB_DCTL_GNPINNakSts_Pos)                    /*!< USB DCTL: GNPINNakSts Mask              */\r
+#define USB_DCTL_GOUTNakSts_Pos               3                                                       /*!< USB DCTL: GOUTNakSts Position           */\r
+#define USB_DCTL_GOUTNakSts_Msk               (0x01UL << USB_DCTL_GOUTNakSts_Pos)                     /*!< USB DCTL: GOUTNakSts Mask               */\r
+#define USB_DCTL_SGNPInNak_Pos                7                                                       /*!< USB DCTL: SGNPInNak Position            */\r
+#define USB_DCTL_SGNPInNak_Msk                (0x01UL << USB_DCTL_SGNPInNak_Pos)                      /*!< USB DCTL: SGNPInNak Mask                */\r
+#define USB_DCTL_CGNPInNak_Pos                8                                                       /*!< USB DCTL: CGNPInNak Position            */\r
+#define USB_DCTL_CGNPInNak_Msk                (0x01UL << USB_DCTL_CGNPInNak_Pos)                      /*!< USB DCTL: CGNPInNak Mask                */\r
+#define USB_DCTL_SGOUTNak_Pos                 9                                                       /*!< USB DCTL: SGOUTNak Position             */\r
+#define USB_DCTL_SGOUTNak_Msk                 (0x01UL << USB_DCTL_SGOUTNak_Pos)                       /*!< USB DCTL: SGOUTNak Mask                 */\r
+#define USB_DCTL_CGOUTNak_Pos                 10                                                      /*!< USB DCTL: CGOUTNak Position             */\r
+#define USB_DCTL_CGOUTNak_Msk                 (0x01UL << USB_DCTL_CGOUTNak_Pos)                       /*!< USB DCTL: CGOUTNak Mask                 */\r
+#define USB_DCTL_GMC_Pos                      13                                                      /*!< USB DCTL: GMC Position                  */\r
+#define USB_DCTL_GMC_Msk                      (0x03UL << USB_DCTL_GMC_Pos)                            /*!< USB DCTL: GMC Mask                      */\r
+#define USB_DCTL_IgnrFrmNum_Pos               15                                                      /*!< USB DCTL: IgnrFrmNum Position           */\r
+#define USB_DCTL_IgnrFrmNum_Msk               (0x01UL << USB_DCTL_IgnrFrmNum_Pos)                     /*!< USB DCTL: IgnrFrmNum Mask               */\r
+#define USB_DCTL_NakOnBble_Pos                16                                                      /*!< USB DCTL: NakOnBble Position            */\r
+#define USB_DCTL_NakOnBble_Msk                (0x01UL << USB_DCTL_NakOnBble_Pos)                      /*!< USB DCTL: NakOnBble Mask                */\r
+\r
+/* ----------------------------------  USB_DSTS  ---------------------------------- */\r
+#define USB_DSTS_SuspSts_Pos                  0                                                       /*!< USB DSTS: SuspSts Position              */\r
+#define USB_DSTS_SuspSts_Msk                  (0x01UL << USB_DSTS_SuspSts_Pos)                        /*!< USB DSTS: SuspSts Mask                  */\r
+#define USB_DSTS_EnumSpd_Pos                  1                                                       /*!< USB DSTS: EnumSpd Position              */\r
+#define USB_DSTS_EnumSpd_Msk                  (0x03UL << USB_DSTS_EnumSpd_Pos)                        /*!< USB DSTS: EnumSpd Mask                  */\r
+#define USB_DSTS_ErrticErr_Pos                3                                                       /*!< USB DSTS: ErrticErr Position            */\r
+#define USB_DSTS_ErrticErr_Msk                (0x01UL << USB_DSTS_ErrticErr_Pos)                      /*!< USB DSTS: ErrticErr Mask                */\r
+#define USB_DSTS_SOFFN_Pos                    8                                                       /*!< USB DSTS: SOFFN Position                */\r
+#define USB_DSTS_SOFFN_Msk                    (0x00003fffUL << USB_DSTS_SOFFN_Pos)                    /*!< USB DSTS: SOFFN Mask                    */\r
+\r
+/* ---------------------------------  USB_DIEPMSK  -------------------------------- */\r
+#define USB_DIEPMSK_XferComplMsk_Pos          0                                                       /*!< USB DIEPMSK: XferComplMsk Position      */\r
+#define USB_DIEPMSK_XferComplMsk_Msk          (0x01UL << USB_DIEPMSK_XferComplMsk_Pos)                /*!< USB DIEPMSK: XferComplMsk Mask          */\r
+#define USB_DIEPMSK_EPDisbldMsk_Pos           1                                                       /*!< USB DIEPMSK: EPDisbldMsk Position       */\r
+#define USB_DIEPMSK_EPDisbldMsk_Msk           (0x01UL << USB_DIEPMSK_EPDisbldMsk_Pos)                 /*!< USB DIEPMSK: EPDisbldMsk Mask           */\r
+#define USB_DIEPMSK_AHBErrMsk_Pos             2                                                       /*!< USB DIEPMSK: AHBErrMsk Position         */\r
+#define USB_DIEPMSK_AHBErrMsk_Msk             (0x01UL << USB_DIEPMSK_AHBErrMsk_Pos)                   /*!< USB DIEPMSK: AHBErrMsk Mask             */\r
+#define USB_DIEPMSK_TimeOUTMsk_Pos            3                                                       /*!< USB DIEPMSK: TimeOUTMsk Position        */\r
+#define USB_DIEPMSK_TimeOUTMsk_Msk            (0x01UL << USB_DIEPMSK_TimeOUTMsk_Pos)                  /*!< USB DIEPMSK: TimeOUTMsk Mask            */\r
+#define USB_DIEPMSK_INTknTXFEmpMsk_Pos        4                                                       /*!< USB DIEPMSK: INTknTXFEmpMsk Position    */\r
+#define USB_DIEPMSK_INTknTXFEmpMsk_Msk        (0x01UL << USB_DIEPMSK_INTknTXFEmpMsk_Pos)              /*!< USB DIEPMSK: INTknTXFEmpMsk Mask        */\r
+#define USB_DIEPMSK_INEPNakEffMsk_Pos         6                                                       /*!< USB DIEPMSK: INEPNakEffMsk Position     */\r
+#define USB_DIEPMSK_INEPNakEffMsk_Msk         (0x01UL << USB_DIEPMSK_INEPNakEffMsk_Pos)               /*!< USB DIEPMSK: INEPNakEffMsk Mask         */\r
+#define USB_DIEPMSK_TxfifoUndrnMsk_Pos        8                                                       /*!< USB DIEPMSK: TxfifoUndrnMsk Position    */\r
+#define USB_DIEPMSK_TxfifoUndrnMsk_Msk        (0x01UL << USB_DIEPMSK_TxfifoUndrnMsk_Pos)              /*!< USB DIEPMSK: TxfifoUndrnMsk Mask        */\r
+#define USB_DIEPMSK_BNAInIntrMsk_Pos          9                                                       /*!< USB DIEPMSK: BNAInIntrMsk Position      */\r
+#define USB_DIEPMSK_BNAInIntrMsk_Msk          (0x01UL << USB_DIEPMSK_BNAInIntrMsk_Pos)                /*!< USB DIEPMSK: BNAInIntrMsk Mask          */\r
+#define USB_DIEPMSK_NAKMsk_Pos                13                                                      /*!< USB DIEPMSK: NAKMsk Position            */\r
+#define USB_DIEPMSK_NAKMsk_Msk                (0x01UL << USB_DIEPMSK_NAKMsk_Pos)                      /*!< USB DIEPMSK: NAKMsk Mask                */\r
+\r
+/* ---------------------------------  USB_DOEPMSK  -------------------------------- */\r
+#define USB_DOEPMSK_XferComplMsk_Pos          0                                                       /*!< USB DOEPMSK: XferComplMsk Position      */\r
+#define USB_DOEPMSK_XferComplMsk_Msk          (0x01UL << USB_DOEPMSK_XferComplMsk_Pos)                /*!< USB DOEPMSK: XferComplMsk Mask          */\r
+#define USB_DOEPMSK_EPDisbldMsk_Pos           1                                                       /*!< USB DOEPMSK: EPDisbldMsk Position       */\r
+#define USB_DOEPMSK_EPDisbldMsk_Msk           (0x01UL << USB_DOEPMSK_EPDisbldMsk_Pos)                 /*!< USB DOEPMSK: EPDisbldMsk Mask           */\r
+#define USB_DOEPMSK_AHBErrMsk_Pos             2                                                       /*!< USB DOEPMSK: AHBErrMsk Position         */\r
+#define USB_DOEPMSK_AHBErrMsk_Msk             (0x01UL << USB_DOEPMSK_AHBErrMsk_Pos)                   /*!< USB DOEPMSK: AHBErrMsk Mask             */\r
+#define USB_DOEPMSK_SetUPMsk_Pos              3                                                       /*!< USB DOEPMSK: SetUPMsk Position          */\r
+#define USB_DOEPMSK_SetUPMsk_Msk              (0x01UL << USB_DOEPMSK_SetUPMsk_Pos)                    /*!< USB DOEPMSK: SetUPMsk Mask              */\r
+#define USB_DOEPMSK_OUTTknEPdisMsk_Pos        4                                                       /*!< USB DOEPMSK: OUTTknEPdisMsk Position    */\r
+#define USB_DOEPMSK_OUTTknEPdisMsk_Msk        (0x01UL << USB_DOEPMSK_OUTTknEPdisMsk_Pos)              /*!< USB DOEPMSK: OUTTknEPdisMsk Mask        */\r
+#define USB_DOEPMSK_Back2BackSETup_Pos        6                                                       /*!< USB DOEPMSK: Back2BackSETup Position    */\r
+#define USB_DOEPMSK_Back2BackSETup_Msk        (0x01UL << USB_DOEPMSK_Back2BackSETup_Pos)              /*!< USB DOEPMSK: Back2BackSETup Mask        */\r
+#define USB_DOEPMSK_OutPktErrMsk_Pos          8                                                       /*!< USB DOEPMSK: OutPktErrMsk Position      */\r
+#define USB_DOEPMSK_OutPktErrMsk_Msk          (0x01UL << USB_DOEPMSK_OutPktErrMsk_Pos)                /*!< USB DOEPMSK: OutPktErrMsk Mask          */\r
+#define USB_DOEPMSK_BnaOutIntrMsk_Pos         9                                                       /*!< USB DOEPMSK: BnaOutIntrMsk Position     */\r
+#define USB_DOEPMSK_BnaOutIntrMsk_Msk         (0x01UL << USB_DOEPMSK_BnaOutIntrMsk_Pos)               /*!< USB DOEPMSK: BnaOutIntrMsk Mask         */\r
+#define USB_DOEPMSK_BbleErrMsk_Pos            12                                                      /*!< USB DOEPMSK: BbleErrMsk Position        */\r
+#define USB_DOEPMSK_BbleErrMsk_Msk            (0x01UL << USB_DOEPMSK_BbleErrMsk_Pos)                  /*!< USB DOEPMSK: BbleErrMsk Mask            */\r
+#define USB_DOEPMSK_NAKMsk_Pos                13                                                      /*!< USB DOEPMSK: NAKMsk Position            */\r
+#define USB_DOEPMSK_NAKMsk_Msk                (0x01UL << USB_DOEPMSK_NAKMsk_Pos)                      /*!< USB DOEPMSK: NAKMsk Mask                */\r
+#define USB_DOEPMSK_NYETMsk_Pos               14                                                      /*!< USB DOEPMSK: NYETMsk Position           */\r
+#define USB_DOEPMSK_NYETMsk_Msk               (0x01UL << USB_DOEPMSK_NYETMsk_Pos)                     /*!< USB DOEPMSK: NYETMsk Mask               */\r
+\r
+/* ----------------------------------  USB_DAINT  --------------------------------- */\r
+#define USB_DAINT_InEpInt_Pos                 0                                                       /*!< USB DAINT: InEpInt Position             */\r
+#define USB_DAINT_InEpInt_Msk                 (0x0000ffffUL << USB_DAINT_InEpInt_Pos)                 /*!< USB DAINT: InEpInt Mask                 */\r
+#define USB_DAINT_OutEPInt_Pos                16                                                      /*!< USB DAINT: OutEPInt Position            */\r
+#define USB_DAINT_OutEPInt_Msk                (0x0000ffffUL << USB_DAINT_OutEPInt_Pos)                /*!< USB DAINT: OutEPInt Mask                */\r
+\r
+/* --------------------------------  USB_DAINTMSK  -------------------------------- */\r
+#define USB_DAINTMSK_InEpMsk_Pos              0                                                       /*!< USB DAINTMSK: InEpMsk Position          */\r
+#define USB_DAINTMSK_InEpMsk_Msk              (0x0000ffffUL << USB_DAINTMSK_InEpMsk_Pos)              /*!< USB DAINTMSK: InEpMsk Mask              */\r
+#define USB_DAINTMSK_OutEpMsk_Pos             16                                                      /*!< USB DAINTMSK: OutEpMsk Position         */\r
+#define USB_DAINTMSK_OutEpMsk_Msk             (0x0000ffffUL << USB_DAINTMSK_OutEpMsk_Pos)             /*!< USB DAINTMSK: OutEpMsk Mask             */\r
+\r
+/* --------------------------------  USB_DVBUSDIS  -------------------------------- */\r
+#define USB_DVBUSDIS_DVBUSDis_Pos             0                                                       /*!< USB DVBUSDIS: DVBUSDis Position         */\r
+#define USB_DVBUSDIS_DVBUSDis_Msk             (0x0000ffffUL << USB_DVBUSDIS_DVBUSDis_Pos)             /*!< USB DVBUSDIS: DVBUSDis Mask             */\r
+\r
+/* -------------------------------  USB_DVBUSPULSE  ------------------------------- */\r
+#define USB_DVBUSPULSE_DVBUSPulse_Pos         0                                                       /*!< USB DVBUSPULSE: DVBUSPulse Position     */\r
+#define USB_DVBUSPULSE_DVBUSPulse_Msk         (0x00000fffUL << USB_DVBUSPULSE_DVBUSPulse_Pos)         /*!< USB DVBUSPULSE: DVBUSPulse Mask         */\r
+\r
+/* -------------------------------  USB_DIEPEMPMSK  ------------------------------- */\r
+#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos      0                                                       /*!< USB DIEPEMPMSK: InEpTxfEmpMsk Position  */\r
+#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk      (0x0000ffffUL << USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos)      /*!< USB DIEPEMPMSK: InEpTxfEmpMsk Mask      */\r
+\r
+/* ---------------------------------  USB_PCGCCTL  -------------------------------- */\r
+#define USB_PCGCCTL_StopPclk_Pos              0                                                       /*!< USB PCGCCTL: StopPclk Position          */\r
+#define USB_PCGCCTL_StopPclk_Msk              (0x01UL << USB_PCGCCTL_StopPclk_Pos)                    /*!< USB PCGCCTL: StopPclk Mask              */\r
+#define USB_PCGCCTL_GateHclk_Pos              1                                                       /*!< USB PCGCCTL: GateHclk Position          */\r
+#define USB_PCGCCTL_GateHclk_Msk              (0x01UL << USB_PCGCCTL_GateHclk_Pos)                    /*!< USB PCGCCTL: GateHclk Mask              */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        struct 'USB0_EP0' Position & Mask       ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------  USB_EP_DIEPCTL0  ----------------------------- */\r
+#define USB_EP_DIEPCTL0_MPS_Pos             0                                                       /*!< USB0_EP0 DIEPCTL0: MPS Position         */\r
+#define USB_EP_DIEPCTL0_MPS_Msk             (0x03UL << USB_EP_DIEPCTL0_MPS_Pos)                   /*!< USB0_EP0 DIEPCTL0: MPS Mask             */\r
+#define USB_EP_DIEPCTL0_USBActEP_Pos        15                                                      /*!< USB0_EP0 DIEPCTL0: USBActEP Position    */\r
+#define USB_EP_DIEPCTL0_USBActEP_Msk        (0x01UL << USB_EP_DIEPCTL0_USBActEP_Pos)              /*!< USB0_EP0 DIEPCTL0: USBActEP Mask        */\r
+#define USB_EP_DIEPCTL0_NAKSts_Pos          17                                                      /*!< USB0_EP0 DIEPCTL0: NAKSts Position      */\r
+#define USB_EP_DIEPCTL0_NAKSts_Msk          (0x01UL << USB_EP_DIEPCTL0_NAKSts_Pos)                /*!< USB0_EP0 DIEPCTL0: NAKSts Mask          */\r
+#define USB_EP_DIEPCTL0_EPType_Pos          18                                                      /*!< USB0_EP0 DIEPCTL0: EPType Position      */\r
+#define USB_EP_DIEPCTL0_EPType_Msk          (0x03UL << USB_EP_DIEPCTL0_EPType_Pos)                /*!< USB0_EP0 DIEPCTL0: EPType Mask          */\r
+#define USB_EP_DIEPCTL0_Stall_Pos           21                                                      /*!< USB0_EP0 DIEPCTL0: Stall Position       */\r
+#define USB_EP_DIEPCTL0_Stall_Msk           (0x01UL << USB_EP_DIEPCTL0_Stall_Pos)                 /*!< USB0_EP0 DIEPCTL0: Stall Mask           */\r
+#define USB_EP_DIEPCTL0_TxFNum_Pos          22                                                      /*!< USB0_EP0 DIEPCTL0: TxFNum Position      */\r
+#define USB_EP_DIEPCTL0_TxFNum_Msk          (0x0fUL << USB_EP_DIEPCTL0_TxFNum_Pos)                /*!< USB0_EP0 DIEPCTL0: TxFNum Mask          */\r
+#define USB_EP_DIEPCTL0_CNAK_Pos            26                                                      /*!< USB0_EP0 DIEPCTL0: CNAK Position        */\r
+#define USB_EP_DIEPCTL0_CNAK_Msk            (0x01UL << USB_EP_DIEPCTL0_CNAK_Pos)                  /*!< USB0_EP0 DIEPCTL0: CNAK Mask            */\r
+#define USB_EP_DIEPCTL0_SNAK_Pos            27                                                      /*!< USB0_EP0 DIEPCTL0: SNAK Position        */\r
+#define USB_EP_DIEPCTL0_SNAK_Msk            (0x01UL << USB_EP_DIEPCTL0_SNAK_Pos)                  /*!< USB0_EP0 DIEPCTL0: SNAK Mask            */\r
+#define USB_EP_DIEPCTL0_EPDis_Pos           30                                                      /*!< USB0_EP0 DIEPCTL0: EPDis Position       */\r
+#define USB_EP_DIEPCTL0_EPDis_Msk           (0x01UL << USB_EP_DIEPCTL0_EPDis_Pos)                 /*!< USB0_EP0 DIEPCTL0: EPDis Mask           */\r
+#define USB_EP_DIEPCTL0_EPEna_Pos           31                                                      /*!< USB0_EP0 DIEPCTL0: EPEna Position       */\r
+#define USB_EP_DIEPCTL0_EPEna_Msk           (0x01UL << USB_EP_DIEPCTL0_EPEna_Pos)                 /*!< USB0_EP0 DIEPCTL0: EPEna Mask           */\r
+\r
+/* ------------------------------  USB_EP_DIEPINT0  ----------------------------- */\r
+#define USB_EP_DIEPINT0_XferCompl_Pos       0                                                       /*!< USB0_EP0 DIEPINT0: XferCompl Position   */\r
+#define USB_EP_DIEPINT0_XferCompl_Msk       (0x01UL << USB_EP_DIEPINT0_XferCompl_Pos)             /*!< USB0_EP0 DIEPINT0: XferCompl Mask       */\r
+#define USB_EP_DIEPINT0_EPDisbld_Pos        1                                                       /*!< USB0_EP0 DIEPINT0: EPDisbld Position    */\r
+#define USB_EP_DIEPINT0_EPDisbld_Msk        (0x01UL << USB_EP_DIEPINT0_EPDisbld_Pos)              /*!< USB0_EP0 DIEPINT0: EPDisbld Mask        */\r
+#define USB_EP_DIEPINT0_AHBErr_Pos          2                                                       /*!< USB0_EP0 DIEPINT0: AHBErr Position      */\r
+#define USB_EP_DIEPINT0_AHBErr_Msk          (0x01UL << USB_EP_DIEPINT0_AHBErr_Pos)                /*!< USB0_EP0 DIEPINT0: AHBErr Mask          */\r
+#define USB_EP_DIEPINT0_TimeOUT_Pos         3                                                       /*!< USB0_EP0 DIEPINT0: TimeOUT Position     */\r
+#define USB_EP_DIEPINT0_TimeOUT_Msk         (0x01UL << USB_EP_DIEPINT0_TimeOUT_Pos)               /*!< USB0_EP0 DIEPINT0: TimeOUT Mask         */\r
+#define USB_EP_DIEPINT0_INTknTXFEmp_Pos     4                                                       /*!< USB0_EP0 DIEPINT0: INTknTXFEmp Position */\r
+#define USB_EP_DIEPINT0_INTknTXFEmp_Msk     (0x01UL << USB_EP_DIEPINT0_INTknTXFEmp_Pos)           /*!< USB0_EP0 DIEPINT0: INTknTXFEmp Mask     */\r
+#define USB_EP_DIEPINT0_INEPNakEff_Pos      6                                                       /*!< USB0_EP0 DIEPINT0: INEPNakEff Position  */\r
+#define USB_EP_DIEPINT0_INEPNakEff_Msk      (0x01UL << USB_EP_DIEPINT0_INEPNakEff_Pos)            /*!< USB0_EP0 DIEPINT0: INEPNakEff Mask      */\r
+#define USB_EP_DIEPINT0_TxFEmp_Pos          7                                                       /*!< USB0_EP0 DIEPINT0: TxFEmp Position      */\r
+#define USB_EP_DIEPINT0_TxFEmp_Msk          (0x01UL << USB_EP_DIEPINT0_TxFEmp_Pos)                /*!< USB0_EP0 DIEPINT0: TxFEmp Mask          */\r
+#define USB_EP_DIEPINT0_BNAIntr_Pos         9                                                       /*!< USB0_EP0 DIEPINT0: BNAIntr Position     */\r
+#define USB_EP_DIEPINT0_BNAIntr_Msk         (0x01UL << USB_EP_DIEPINT0_BNAIntr_Pos)               /*!< USB0_EP0 DIEPINT0: BNAIntr Mask         */\r
+\r
+/* -----------------------------  USB_EP_DIEPTSIZ0  ----------------------------- */\r
+#define USB_EP_DIEPTSIZ0_XferSize_Pos       0                                                       /*!< USB0_EP0 DIEPTSIZ0: XferSize Position   */\r
+#define USB_EP_DIEPTSIZ0_XferSize_Msk       (0x7fUL << USB_EP_DIEPTSIZ0_XferSize_Pos)             /*!< USB0_EP0 DIEPTSIZ0: XferSize Mask       */\r
+#define USB_EP_DIEPTSIZ0_PktCnt_Pos         19                                                      /*!< USB0_EP0 DIEPTSIZ0: PktCnt Position     */\r
+#define USB_EP_DIEPTSIZ0_PktCnt_Msk         (0x03UL << USB_EP_DIEPTSIZ0_PktCnt_Pos)               /*!< USB0_EP0 DIEPTSIZ0: PktCnt Mask         */\r
+\r
+/* ------------------------------  USB_EP_DIEPDMA0  ----------------------------- */\r
+#define USB_EP_DIEPDMA0_DMAAddr_Pos         0                                                       /*!< USB0_EP0 DIEPDMA0: DMAAddr Position     */\r
+#define USB_EP_DIEPDMA0_DMAAddr_Msk         (0xffffffffUL << USB_EP_DIEPDMA0_DMAAddr_Pos)         /*!< USB0_EP0 DIEPDMA0: DMAAddr Mask         */\r
+\r
+/* ------------------------------  USB_EP_DTXFSTS0  ----------------------------- */\r
+#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos 0                                                       /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail Position */\r
+#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk (0x0000ffffUL << USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail Mask */\r
+\r
+/* -----------------------------  USB_EP_DIEPDMAB0  ----------------------------- */\r
+#define USB_EP_DIEPDMAB0_DMABufferAddr_Pos  0                                                       /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr Position */\r
+#define USB_EP_DIEPDMAB0_DMABufferAddr_Msk  (0xffffffffUL << USB_EP_DIEPDMAB0_DMABufferAddr_Pos)  /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr Mask  */\r
+\r
+/* ------------------------------  USB_EP_DOEPCTL0  ----------------------------- */\r
+#define USB_EP_DOEPCTL0_MPS_Pos             0                                                       /*!< USB0_EP0 DOEPCTL0: MPS Position         */\r
+#define USB_EP_DOEPCTL0_MPS_Msk             (0x03UL << USB_EP_DOEPCTL0_MPS_Pos)                   /*!< USB0_EP0 DOEPCTL0: MPS Mask             */\r
+#define USB_EP_DOEPCTL0_USBActEP_Pos        15                                                      /*!< USB0_EP0 DOEPCTL0: USBActEP Position    */\r
+#define USB_EP_DOEPCTL0_USBActEP_Msk        (0x01UL << USB_EP_DOEPCTL0_USBActEP_Pos)              /*!< USB0_EP0 DOEPCTL0: USBActEP Mask        */\r
+#define USB_EP_DOEPCTL0_NAKSts_Pos          17                                                      /*!< USB0_EP0 DOEPCTL0: NAKSts Position      */\r
+#define USB_EP_DOEPCTL0_NAKSts_Msk          (0x01UL << USB_EP_DOEPCTL0_NAKSts_Pos)                /*!< USB0_EP0 DOEPCTL0: NAKSts Mask          */\r
+#define USB_EP_DOEPCTL0_EPType_Pos          18                                                      /*!< USB0_EP0 DOEPCTL0: EPType Position      */\r
+#define USB_EP_DOEPCTL0_EPType_Msk          (0x03UL << USB_EP_DOEPCTL0_EPType_Pos)                /*!< USB0_EP0 DOEPCTL0: EPType Mask          */\r
+#define USB_EP_DOEPCTL0_Snp_Pos             20                                                      /*!< USB0_EP0 DOEPCTL0: Snp Position         */\r
+#define USB_EP_DOEPCTL0_Snp_Msk             (0x01UL << USB_EP_DOEPCTL0_Snp_Pos)                   /*!< USB0_EP0 DOEPCTL0: Snp Mask             */\r
+#define USB_EP_DOEPCTL0_Stall_Pos           21                                                      /*!< USB0_EP0 DOEPCTL0: Stall Position       */\r
+#define USB_EP_DOEPCTL0_Stall_Msk           (0x01UL << USB_EP_DOEPCTL0_Stall_Pos)                 /*!< USB0_EP0 DOEPCTL0: Stall Mask           */\r
+#define USB_EP_DOEPCTL0_CNAK_Pos            26                                                      /*!< USB0_EP0 DOEPCTL0: CNAK Position        */\r
+#define USB_EP_DOEPCTL0_CNAK_Msk            (0x01UL << USB_EP_DOEPCTL0_CNAK_Pos)                  /*!< USB0_EP0 DOEPCTL0: CNAK Mask            */\r
+#define USB_EP_DOEPCTL0_SNAK_Pos            27                                                      /*!< USB0_EP0 DOEPCTL0: SNAK Position        */\r
+#define USB_EP_DOEPCTL0_SNAK_Msk            (0x01UL << USB_EP_DOEPCTL0_SNAK_Pos)                  /*!< USB0_EP0 DOEPCTL0: SNAK Mask            */\r
+#define USB_EP_DOEPCTL0_EPDis_Pos           30                                                      /*!< USB0_EP0 DOEPCTL0: EPDis Position       */\r
+#define USB_EP_DOEPCTL0_EPDis_Msk           (0x01UL << USB_EP_DOEPCTL0_EPDis_Pos)                 /*!< USB0_EP0 DOEPCTL0: EPDis Mask           */\r
+#define USB_EP_DOEPCTL0_EPEna_Pos           31                                                      /*!< USB0_EP0 DOEPCTL0: EPEna Position       */\r
+#define USB_EP_DOEPCTL0_EPEna_Msk           (0x01UL << USB_EP_DOEPCTL0_EPEna_Pos)                 /*!< USB0_EP0 DOEPCTL0: EPEna Mask           */\r
+\r
+/* ------------------------------  USB_EP_DOEPINT0  ----------------------------- */\r
+#define USB_EP_DOEPINT0_XferCompl_Pos       0                                                       /*!< USB0_EP0 DOEPINT0: XferCompl Position   */\r
+#define USB_EP_DOEPINT0_XferCompl_Msk       (0x01UL << USB_EP_DOEPINT0_XferCompl_Pos)             /*!< USB0_EP0 DOEPINT0: XferCompl Mask       */\r
+#define USB_EP_DOEPINT0_EPDisbld_Pos        1                                                       /*!< USB0_EP0 DOEPINT0: EPDisbld Position    */\r
+#define USB_EP_DOEPINT0_EPDisbld_Msk        (0x01UL << USB_EP_DOEPINT0_EPDisbld_Pos)              /*!< USB0_EP0 DOEPINT0: EPDisbld Mask        */\r
+#define USB_EP_DOEPINT0_AHBErr_Pos          2                                                       /*!< USB0_EP0 DOEPINT0: AHBErr Position      */\r
+#define USB_EP_DOEPINT0_AHBErr_Msk          (0x01UL << USB_EP_DOEPINT0_AHBErr_Pos)                /*!< USB0_EP0 DOEPINT0: AHBErr Mask          */\r
+#define USB_EP_DOEPINT0_SetUp_Pos           3                                                       /*!< USB0_EP0 DOEPINT0: SetUp Position       */\r
+#define USB_EP_DOEPINT0_SetUp_Msk           (0x01UL << USB_EP_DOEPINT0_SetUp_Pos)                 /*!< USB0_EP0 DOEPINT0: SetUp Mask           */\r
+#define USB_EP_DOEPINT0_OUTTknEPdis_Pos     4                                                       /*!< USB0_EP0 DOEPINT0: OUTTknEPdis Position */\r
+#define USB_EP_DOEPINT0_OUTTknEPdis_Msk     (0x01UL << USB_EP_DOEPINT0_OUTTknEPdis_Pos)           /*!< USB0_EP0 DOEPINT0: OUTTknEPdis Mask     */\r
+#define USB_EP_DOEPINT0_StsPhseRcvd_Pos     5                                                       /*!< USB0_EP0 DOEPINT0: StsPhseRcvd Position */\r
+#define USB_EP_DOEPINT0_StsPhseRcvd_Msk     (0x01UL << USB_EP_DOEPINT0_StsPhseRcvd_Pos)           /*!< USB0_EP0 DOEPINT0: StsPhseRcvd Mask     */\r
+#define USB_EP_DOEPINT0_Back2BackSETup_Pos  6                                                       /*!< USB0_EP0 DOEPINT0: Back2BackSETup Position */\r
+#define USB_EP_DOEPINT0_Back2BackSETup_Msk  (0x01UL << USB_EP_DOEPINT0_Back2BackSETup_Pos)        /*!< USB0_EP0 DOEPINT0: Back2BackSETup Mask  */\r
+#define USB_EP_DOEPINT0_BNAIntr_Pos         9                                                       /*!< USB0_EP0 DOEPINT0: BNAIntr Position     */\r
+#define USB_EP_DOEPINT0_BNAIntr_Msk         (0x01UL << USB_EP_DOEPINT0_BNAIntr_Pos)               /*!< USB0_EP0 DOEPINT0: BNAIntr Mask         */\r
+#define USB_EP_DOEPINT0_PktDrpSts_Pos       11                                                      /*!< USB0_EP0 DOEPINT0: PktDrpSts Position   */\r
+#define USB_EP_DOEPINT0_PktDrpSts_Msk       (0x01UL << USB_EP_DOEPINT0_PktDrpSts_Pos)             /*!< USB0_EP0 DOEPINT0: PktDrpSts Mask       */\r
+#define USB_EP_DOEPINT0_BbleErrIntrpt_Pos   12                                                      /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt Position */\r
+#define USB_EP_DOEPINT0_BbleErrIntrpt_Msk   (0x01UL << USB_EP_DOEPINT0_BbleErrIntrpt_Pos)         /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt Mask   */\r
+#define USB_EP_DOEPINT0_NAKIntrpt_Pos       13                                                      /*!< USB0_EP0 DOEPINT0: NAKIntrpt Position   */\r
+#define USB_EP_DOEPINT0_NAKIntrpt_Msk       (0x01UL << USB_EP_DOEPINT0_NAKIntrpt_Pos)             /*!< USB0_EP0 DOEPINT0: NAKIntrpt Mask       */\r
+#define USB_EP_DOEPINT0_NYETIntrpt_Pos      14                                                      /*!< USB0_EP0 DOEPINT0: NYETIntrpt Position  */\r
+#define USB_EP_DOEPINT0_NYETIntrpt_Msk      (0x01UL << USB_EP_DOEPINT0_NYETIntrpt_Pos)            /*!< USB0_EP0 DOEPINT0: NYETIntrpt Mask      */\r
+\r
+/* -----------------------------  USB_EP_DOEPTSIZ0  ----------------------------- */\r
+#define USB_EP_DOEPTSIZ0_XferSize_Pos       0                                                       /*!< USB0_EP0 DOEPTSIZ0: XferSize Position   */\r
+#define USB_EP_DOEPTSIZ0_XferSize_Msk       (0x7fUL << USB_EP_DOEPTSIZ0_XferSize_Pos)             /*!< USB0_EP0 DOEPTSIZ0: XferSize Mask       */\r
+#define USB_EP_DOEPTSIZ0_PktCnt_Pos         19                                                      /*!< USB0_EP0 DOEPTSIZ0: PktCnt Position     */\r
+#define USB_EP_DOEPTSIZ0_PktCnt_Msk         (0x03UL << USB_EP_DOEPTSIZ0_PktCnt_Pos)               /*!< USB0_EP0 DOEPTSIZ0: PktCnt Mask         */\r
+#define USB_EP_DOEPTSIZ0_SUPCnt_Pos         29                                                      /*!< USB0_EP0 DOEPTSIZ0: SUPCnt Position     */\r
+#define USB_EP_DOEPTSIZ0_SUPCnt_Msk         (0x03UL << USB_EP_DOEPTSIZ0_SUPCnt_Pos)               /*!< USB0_EP0 DOEPTSIZ0: SUPCnt Mask         */\r
+\r
+/* ------------------------------  USB_EP_DOEPDMA0  ----------------------------- */\r
+#define USB_EP_DOEPDMA0_DMAAddr_Pos         0                                                       /*!< USB0_EP0 DOEPDMA0: DMAAddr Position     */\r
+#define USB_EP_DOEPDMA0_DMAAddr_Msk         (0xffffffffUL << USB_EP_DOEPDMA0_DMAAddr_Pos)         /*!< USB0_EP0 DOEPDMA0: DMAAddr Mask         */\r
+\r
+/* -----------------------------  USB_EP_DOEPDMAB0  ----------------------------- */\r
+#define USB_EP_DOEPDMAB0_DMABufferAddr_Pos  0                                                       /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr Position */\r
+#define USB_EP_DOEPDMAB0_DMABufferAddr_Msk  (0xffffffffUL << USB_EP_DOEPDMAB0_DMABufferAddr_Pos)  /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr Mask  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'USB_EP' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------  USB_EP_DIEPCTL_ISOCONT  --------------------------- */\r
+#define USB_EP_DIEPCTL_ISOCONT_MPS_Pos        0                                                       /*!< USB_EP DIEPCTL_ISOCONT: MPS Position    */\r
+#define USB_EP_DIEPCTL_ISOCONT_MPS_Msk        (0x000007ffUL << USB_EP_DIEPCTL_ISOCONT_MPS_Pos)        /*!< USB_EP DIEPCTL_ISOCONT: MPS Mask        */\r
+#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos   15                                                      /*!< USB_EP DIEPCTL_ISOCONT: USBActEP Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk   (0x01UL << USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos)         /*!< USB_EP DIEPCTL_ISOCONT: USBActEP Mask   */\r
+#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos   16                                                      /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk   (0x01UL << USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos)         /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum Mask   */\r
+#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos     17                                                      /*!< USB_EP DIEPCTL_ISOCONT: NAKSts Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk     (0x01UL << USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos)           /*!< USB_EP DIEPCTL_ISOCONT: NAKSts Mask     */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPType_Pos     18                                                      /*!< USB_EP DIEPCTL_ISOCONT: EPType Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPType_Msk     (0x03UL << USB_EP_DIEPCTL_ISOCONT_EPType_Pos)           /*!< USB_EP DIEPCTL_ISOCONT: EPType Mask     */\r
+#define USB_EP_DIEPCTL_ISOCONT_Snp_Pos        20                                                      /*!< USB_EP DIEPCTL_ISOCONT: Snp Position    */\r
+#define USB_EP_DIEPCTL_ISOCONT_Snp_Msk        (0x01UL << USB_EP_DIEPCTL_ISOCONT_Snp_Pos)              /*!< USB_EP DIEPCTL_ISOCONT: Snp Mask        */\r
+#define USB_EP_DIEPCTL_ISOCONT_Stall_Pos      21                                                      /*!< USB_EP DIEPCTL_ISOCONT: Stall Position  */\r
+#define USB_EP_DIEPCTL_ISOCONT_Stall_Msk      (0x01UL << USB_EP_DIEPCTL_ISOCONT_Stall_Pos)            /*!< USB_EP DIEPCTL_ISOCONT: Stall Mask      */\r
+#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos     22                                                      /*!< USB_EP DIEPCTL_ISOCONT: TxFNum Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk     (0x0fUL << USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos)           /*!< USB_EP DIEPCTL_ISOCONT: TxFNum Mask     */\r
+#define USB_EP_DIEPCTL_ISOCONT_CNAK_Pos       26                                                      /*!< USB_EP DIEPCTL_ISOCONT: CNAK Position   */\r
+#define USB_EP_DIEPCTL_ISOCONT_CNAK_Msk       (0x01UL << USB_EP_DIEPCTL_ISOCONT_CNAK_Pos)             /*!< USB_EP DIEPCTL_ISOCONT: CNAK Mask       */\r
+#define USB_EP_DIEPCTL_ISOCONT_SNAK_Pos       27                                                      /*!< USB_EP DIEPCTL_ISOCONT: SNAK Position   */\r
+#define USB_EP_DIEPCTL_ISOCONT_SNAK_Msk       (0x01UL << USB_EP_DIEPCTL_ISOCONT_SNAK_Pos)             /*!< USB_EP DIEPCTL_ISOCONT: SNAK Mask       */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos  28                                                      /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk  (0x01UL << USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos)        /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr Mask  */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos   29                                                      /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr Position */\r
+#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk   (0x01UL << USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos)         /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr Mask   */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPDis_Pos      30                                                      /*!< USB_EP DIEPCTL_ISOCONT: EPDis Position  */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPDis_Msk      (0x01UL << USB_EP_DIEPCTL_ISOCONT_EPDis_Pos)            /*!< USB_EP DIEPCTL_ISOCONT: EPDis Mask      */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPEna_Pos      31                                                      /*!< USB_EP DIEPCTL_ISOCONT: EPEna Position  */\r
+#define USB_EP_DIEPCTL_ISOCONT_EPEna_Msk      (0x01UL << USB_EP_DIEPCTL_ISOCONT_EPEna_Pos)            /*!< USB_EP DIEPCTL_ISOCONT: EPEna Mask      */\r
+\r
+/* ---------------------------  USB_EP_DIEPCTL_INTBULK  --------------------------- */\r
+#define USB_EP_DIEPCTL_INTBULK_MPS_Pos        0                                                       /*!< USB_EP DIEPCTL_INTBULK: MPS Position    */\r
+#define USB_EP_DIEPCTL_INTBULK_MPS_Msk        (0x000007ffUL << USB_EP_DIEPCTL_INTBULK_MPS_Pos)        /*!< USB_EP DIEPCTL_INTBULK: MPS Mask        */\r
+#define USB_EP_DIEPCTL_INTBULK_USBActEP_Pos   15                                                      /*!< USB_EP DIEPCTL_INTBULK: USBActEP Position */\r
+#define USB_EP_DIEPCTL_INTBULK_USBActEP_Msk   (0x01UL << USB_EP_DIEPCTL_INTBULK_USBActEP_Pos)         /*!< USB_EP DIEPCTL_INTBULK: USBActEP Mask   */\r
+#define USB_EP_DIEPCTL_INTBULK_DPID_Pos       16                                                      /*!< USB_EP DIEPCTL_INTBULK: DPID Position   */\r
+#define USB_EP_DIEPCTL_INTBULK_DPID_Msk       (0x01UL << USB_EP_DIEPCTL_INTBULK_DPID_Pos)             /*!< USB_EP DIEPCTL_INTBULK: DPID Mask       */\r
+#define USB_EP_DIEPCTL_INTBULK_NAKSts_Pos     17                                                      /*!< USB_EP DIEPCTL_INTBULK: NAKSts Position */\r
+#define USB_EP_DIEPCTL_INTBULK_NAKSts_Msk     (0x01UL << USB_EP_DIEPCTL_INTBULK_NAKSts_Pos)           /*!< USB_EP DIEPCTL_INTBULK: NAKSts Mask     */\r
+#define USB_EP_DIEPCTL_INTBULK_EPType_Pos     18                                                      /*!< USB_EP DIEPCTL_INTBULK: EPType Position */\r
+#define USB_EP_DIEPCTL_INTBULK_EPType_Msk     (0x03UL << USB_EP_DIEPCTL_INTBULK_EPType_Pos)           /*!< USB_EP DIEPCTL_INTBULK: EPType Mask     */\r
+#define USB_EP_DIEPCTL_INTBULK_Snp_Pos        20                                                      /*!< USB_EP DIEPCTL_INTBULK: Snp Position    */\r
+#define USB_EP_DIEPCTL_INTBULK_Snp_Msk        (0x01UL << USB_EP_DIEPCTL_INTBULK_Snp_Pos)              /*!< USB_EP DIEPCTL_INTBULK: Snp Mask        */\r
+#define USB_EP_DIEPCTL_INTBULK_Stall_Pos      21                                                      /*!< USB_EP DIEPCTL_INTBULK: Stall Position  */\r
+#define USB_EP_DIEPCTL_INTBULK_Stall_Msk      (0x01UL << USB_EP_DIEPCTL_INTBULK_Stall_Pos)            /*!< USB_EP DIEPCTL_INTBULK: Stall Mask      */\r
+#define USB_EP_DIEPCTL_INTBULK_TxFNum_Pos     22                                                      /*!< USB_EP DIEPCTL_INTBULK: TxFNum Position */\r
+#define USB_EP_DIEPCTL_INTBULK_TxFNum_Msk     (0x0fUL << USB_EP_DIEPCTL_INTBULK_TxFNum_Pos)           /*!< USB_EP DIEPCTL_INTBULK: TxFNum Mask     */\r
+#define USB_EP_DIEPCTL_INTBULK_CNAK_Pos       26                                                      /*!< USB_EP DIEPCTL_INTBULK: CNAK Position   */\r
+#define USB_EP_DIEPCTL_INTBULK_CNAK_Msk       (0x01UL << USB_EP_DIEPCTL_INTBULK_CNAK_Pos)             /*!< USB_EP DIEPCTL_INTBULK: CNAK Mask       */\r
+#define USB_EP_DIEPCTL_INTBULK_SNAK_Pos       27                                                      /*!< USB_EP DIEPCTL_INTBULK: SNAK Position   */\r
+#define USB_EP_DIEPCTL_INTBULK_SNAK_Msk       (0x01UL << USB_EP_DIEPCTL_INTBULK_SNAK_Pos)             /*!< USB_EP DIEPCTL_INTBULK: SNAK Mask       */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos   28                                                      /*!< USB_EP DIEPCTL_INTBULK: SetD0PID Position */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk   (0x01UL << USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos)         /*!< USB_EP DIEPCTL_INTBULK: SetD0PID Mask   */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos   29                                                      /*!< USB_EP DIEPCTL_INTBULK: SetD1PID Position */\r
+#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk   (0x01UL << USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos)         /*!< USB_EP DIEPCTL_INTBULK: SetD1PID Mask   */\r
+#define USB_EP_DIEPCTL_INTBULK_EPDis_Pos      30                                                      /*!< USB_EP DIEPCTL_INTBULK: EPDis Position  */\r
+#define USB_EP_DIEPCTL_INTBULK_EPDis_Msk      (0x01UL << USB_EP_DIEPCTL_INTBULK_EPDis_Pos)            /*!< USB_EP DIEPCTL_INTBULK: EPDis Mask      */\r
+#define USB_EP_DIEPCTL_INTBULK_EPEna_Pos      31                                                      /*!< USB_EP DIEPCTL_INTBULK: EPEna Position  */\r
+#define USB_EP_DIEPCTL_INTBULK_EPEna_Msk      (0x01UL << USB_EP_DIEPCTL_INTBULK_EPEna_Pos)            /*!< USB_EP DIEPCTL_INTBULK: EPEna Mask      */\r
+\r
+/* -------------------------------  USB_EP_DIEPINT  ------------------------------- */\r
+#define USB_EP_DIEPINT_XferCompl_Pos          0                                                       /*!< USB_EP DIEPINT: XferCompl Position      */\r
+#define USB_EP_DIEPINT_XferCompl_Msk          (0x01UL << USB_EP_DIEPINT_XferCompl_Pos)                /*!< USB_EP DIEPINT: XferCompl Mask          */\r
+#define USB_EP_DIEPINT_EPDisbld_Pos           1                                                       /*!< USB_EP DIEPINT: EPDisbld Position       */\r
+#define USB_EP_DIEPINT_EPDisbld_Msk           (0x01UL << USB_EP_DIEPINT_EPDisbld_Pos)                 /*!< USB_EP DIEPINT: EPDisbld Mask           */\r
+#define USB_EP_DIEPINT_AHBErr_Pos             2                                                       /*!< USB_EP DIEPINT: AHBErr Position         */\r
+#define USB_EP_DIEPINT_AHBErr_Msk             (0x01UL << USB_EP_DIEPINT_AHBErr_Pos)                   /*!< USB_EP DIEPINT: AHBErr Mask             */\r
+#define USB_EP_DIEPINT_TimeOUT_Pos            3                                                       /*!< USB_EP DIEPINT: TimeOUT Position        */\r
+#define USB_EP_DIEPINT_TimeOUT_Msk            (0x01UL << USB_EP_DIEPINT_TimeOUT_Pos)                  /*!< USB_EP DIEPINT: TimeOUT Mask            */\r
+#define USB_EP_DIEPINT_INTknTXFEmp_Pos        4                                                       /*!< USB_EP DIEPINT: INTknTXFEmp Position    */\r
+#define USB_EP_DIEPINT_INTknTXFEmp_Msk        (0x01UL << USB_EP_DIEPINT_INTknTXFEmp_Pos)              /*!< USB_EP DIEPINT: INTknTXFEmp Mask        */\r
+#define USB_EP_DIEPINT_INEPNakEff_Pos         6                                                       /*!< USB_EP DIEPINT: INEPNakEff Position     */\r
+#define USB_EP_DIEPINT_INEPNakEff_Msk         (0x01UL << USB_EP_DIEPINT_INEPNakEff_Pos)               /*!< USB_EP DIEPINT: INEPNakEff Mask         */\r
+#define USB_EP_DIEPINT_TxFEmp_Pos             7                                                       /*!< USB_EP DIEPINT: TxFEmp Position         */\r
+#define USB_EP_DIEPINT_TxFEmp_Msk             (0x01UL << USB_EP_DIEPINT_TxFEmp_Pos)                   /*!< USB_EP DIEPINT: TxFEmp Mask             */\r
+#define USB_EP_DIEPINT_BNAIntr_Pos            9                                                       /*!< USB_EP DIEPINT: BNAIntr Position        */\r
+#define USB_EP_DIEPINT_BNAIntr_Msk            (0x01UL << USB_EP_DIEPINT_BNAIntr_Pos)                  /*!< USB_EP DIEPINT: BNAIntr Mask            */\r
+\r
+/* -------------------------------  USB_EP_DIEPTSIZ  ------------------------------ */\r
+#define USB_EP_DIEPTSIZ_XferSize_Pos          0                                                       /*!< USB_EP DIEPTSIZ: XferSize Position      */\r
+#define USB_EP_DIEPTSIZ_XferSize_Msk          (0x0007ffffUL << USB_EP_DIEPTSIZ_XferSize_Pos)          /*!< USB_EP DIEPTSIZ: XferSize Mask          */\r
+#define USB_EP_DIEPTSIZ_PktCnt_Pos            19                                                      /*!< USB_EP DIEPTSIZ: PktCnt Position        */\r
+#define USB_EP_DIEPTSIZ_PktCnt_Msk            (0x000003ffUL << USB_EP_DIEPTSIZ_PktCnt_Pos)            /*!< USB_EP DIEPTSIZ: PktCnt Mask            */\r
+\r
+/* -------------------------------  USB_EP_DIEPDMA  ------------------------------- */\r
+#define USB_EP_DIEPDMA_DMAAddr_Pos            0                                                       /*!< USB_EP DIEPDMA: DMAAddr Position        */\r
+#define USB_EP_DIEPDMA_DMAAddr_Msk            (0xffffffffUL << USB_EP_DIEPDMA_DMAAddr_Pos)            /*!< USB_EP DIEPDMA: DMAAddr Mask            */\r
+\r
+/* -------------------------------  USB_EP_DTXFSTS  ------------------------------- */\r
+#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos    0                                                       /*!< USB_EP DTXFSTS: INEPTxFSpcAvail Position */\r
+#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk    (0x0000ffffUL << USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos)    /*!< USB_EP DTXFSTS: INEPTxFSpcAvail Mask    */\r
+\r
+/* -------------------------------  USB_EP_DIEPDMAB  ------------------------------ */\r
+#define USB_EP_DIEPDMAB_DMABufferAddr_Pos     0                                                       /*!< USB_EP DIEPDMAB: DMABufferAddr Position */\r
+#define USB_EP_DIEPDMAB_DMABufferAddr_Msk     (0xffffffffUL << USB_EP_DIEPDMAB_DMABufferAddr_Pos)     /*!< USB_EP DIEPDMAB: DMABufferAddr Mask     */\r
+\r
+/* ---------------------------  USB_EP_DOEPCTL_ISOCONT  --------------------------- */\r
+#define USB_EP_DOEPCTL_ISOCONT_MPS_Pos        0                                                       /*!< USB_EP DOEPCTL_ISOCONT: MPS Position    */\r
+#define USB_EP_DOEPCTL_ISOCONT_MPS_Msk        (0x000007ffUL << USB_EP_DOEPCTL_ISOCONT_MPS_Pos)        /*!< USB_EP DOEPCTL_ISOCONT: MPS Mask        */\r
+#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos   15                                                      /*!< USB_EP DOEPCTL_ISOCONT: USBActEP Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk   (0x01UL << USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos)         /*!< USB_EP DOEPCTL_ISOCONT: USBActEP Mask   */\r
+#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos   16                                                      /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk   (0x01UL << USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos)         /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum Mask   */\r
+#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos     17                                                      /*!< USB_EP DOEPCTL_ISOCONT: NAKSts Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk     (0x01UL << USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos)           /*!< USB_EP DOEPCTL_ISOCONT: NAKSts Mask     */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPType_Pos     18                                                      /*!< USB_EP DOEPCTL_ISOCONT: EPType Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPType_Msk     (0x03UL << USB_EP_DOEPCTL_ISOCONT_EPType_Pos)           /*!< USB_EP DOEPCTL_ISOCONT: EPType Mask     */\r
+#define USB_EP_DOEPCTL_ISOCONT_Snp_Pos        20                                                      /*!< USB_EP DOEPCTL_ISOCONT: Snp Position    */\r
+#define USB_EP_DOEPCTL_ISOCONT_Snp_Msk        (0x01UL << USB_EP_DOEPCTL_ISOCONT_Snp_Pos)              /*!< USB_EP DOEPCTL_ISOCONT: Snp Mask        */\r
+#define USB_EP_DOEPCTL_ISOCONT_Stall_Pos      21                                                      /*!< USB_EP DOEPCTL_ISOCONT: Stall Position  */\r
+#define USB_EP_DOEPCTL_ISOCONT_Stall_Msk      (0x01UL << USB_EP_DOEPCTL_ISOCONT_Stall_Pos)            /*!< USB_EP DOEPCTL_ISOCONT: Stall Mask      */\r
+#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos     22                                                      /*!< USB_EP DOEPCTL_ISOCONT: TxFNum Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk     (0x0fUL << USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos)           /*!< USB_EP DOEPCTL_ISOCONT: TxFNum Mask     */\r
+#define USB_EP_DOEPCTL_ISOCONT_CNAK_Pos       26                                                      /*!< USB_EP DOEPCTL_ISOCONT: CNAK Position   */\r
+#define USB_EP_DOEPCTL_ISOCONT_CNAK_Msk       (0x01UL << USB_EP_DOEPCTL_ISOCONT_CNAK_Pos)             /*!< USB_EP DOEPCTL_ISOCONT: CNAK Mask       */\r
+#define USB_EP_DOEPCTL_ISOCONT_SNAK_Pos       27                                                      /*!< USB_EP DOEPCTL_ISOCONT: SNAK Position   */\r
+#define USB_EP_DOEPCTL_ISOCONT_SNAK_Msk       (0x01UL << USB_EP_DOEPCTL_ISOCONT_SNAK_Pos)             /*!< USB_EP DOEPCTL_ISOCONT: SNAK Mask       */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos  28                                                      /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk  (0x01UL << USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos)        /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr Mask  */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos   29                                                      /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr Position */\r
+#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk   (0x01UL << USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos)         /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr Mask   */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPDis_Pos      30                                                      /*!< USB_EP DOEPCTL_ISOCONT: EPDis Position  */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPDis_Msk      (0x01UL << USB_EP_DOEPCTL_ISOCONT_EPDis_Pos)            /*!< USB_EP DOEPCTL_ISOCONT: EPDis Mask      */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPEna_Pos      31                                                      /*!< USB_EP DOEPCTL_ISOCONT: EPEna Position  */\r
+#define USB_EP_DOEPCTL_ISOCONT_EPEna_Msk      (0x01UL << USB_EP_DOEPCTL_ISOCONT_EPEna_Pos)            /*!< USB_EP DOEPCTL_ISOCONT: EPEna Mask      */\r
+\r
+/* ---------------------------  USB_EP_DOEPCTL_INTBULK  --------------------------- */\r
+#define USB_EP_DOEPCTL_INTBULK_MPS_Pos        0                                                       /*!< USB_EP DOEPCTL_INTBULK: MPS Position    */\r
+#define USB_EP_DOEPCTL_INTBULK_MPS_Msk        (0x000007ffUL << USB_EP_DOEPCTL_INTBULK_MPS_Pos)        /*!< USB_EP DOEPCTL_INTBULK: MPS Mask        */\r
+#define USB_EP_DOEPCTL_INTBULK_USBActEP_Pos   15                                                      /*!< USB_EP DOEPCTL_INTBULK: USBActEP Position */\r
+#define USB_EP_DOEPCTL_INTBULK_USBActEP_Msk   (0x01UL << USB_EP_DOEPCTL_INTBULK_USBActEP_Pos)         /*!< USB_EP DOEPCTL_INTBULK: USBActEP Mask   */\r
+#define USB_EP_DOEPCTL_INTBULK_DPID_Pos       16                                                      /*!< USB_EP DOEPCTL_INTBULK: DPID Position   */\r
+#define USB_EP_DOEPCTL_INTBULK_DPID_Msk       (0x01UL << USB_EP_DOEPCTL_INTBULK_DPID_Pos)             /*!< USB_EP DOEPCTL_INTBULK: DPID Mask       */\r
+#define USB_EP_DOEPCTL_INTBULK_NAKSts_Pos     17                                                      /*!< USB_EP DOEPCTL_INTBULK: NAKSts Position */\r
+#define USB_EP_DOEPCTL_INTBULK_NAKSts_Msk     (0x01UL << USB_EP_DOEPCTL_INTBULK_NAKSts_Pos)           /*!< USB_EP DOEPCTL_INTBULK: NAKSts Mask     */\r
+#define USB_EP_DOEPCTL_INTBULK_EPType_Pos     18                                                      /*!< USB_EP DOEPCTL_INTBULK: EPType Position */\r
+#define USB_EP_DOEPCTL_INTBULK_EPType_Msk     (0x03UL << USB_EP_DOEPCTL_INTBULK_EPType_Pos)           /*!< USB_EP DOEPCTL_INTBULK: EPType Mask     */\r
+#define USB_EP_DOEPCTL_INTBULK_Snp_Pos        20                                                      /*!< USB_EP DOEPCTL_INTBULK: Snp Position    */\r
+#define USB_EP_DOEPCTL_INTBULK_Snp_Msk        (0x01UL << USB_EP_DOEPCTL_INTBULK_Snp_Pos)              /*!< USB_EP DOEPCTL_INTBULK: Snp Mask        */\r
+#define USB_EP_DOEPCTL_INTBULK_Stall_Pos      21                                                      /*!< USB_EP DOEPCTL_INTBULK: Stall Position  */\r
+#define USB_EP_DOEPCTL_INTBULK_Stall_Msk      (0x01UL << USB_EP_DOEPCTL_INTBULK_Stall_Pos)            /*!< USB_EP DOEPCTL_INTBULK: Stall Mask      */\r
+#define USB_EP_DOEPCTL_INTBULK_TxFNum_Pos     22                                                      /*!< USB_EP DOEPCTL_INTBULK: TxFNum Position */\r
+#define USB_EP_DOEPCTL_INTBULK_TxFNum_Msk     (0x0fUL << USB_EP_DOEPCTL_INTBULK_TxFNum_Pos)           /*!< USB_EP DOEPCTL_INTBULK: TxFNum Mask     */\r
+#define USB_EP_DOEPCTL_INTBULK_CNAK_Pos       26                                                      /*!< USB_EP DOEPCTL_INTBULK: CNAK Position   */\r
+#define USB_EP_DOEPCTL_INTBULK_CNAK_Msk       (0x01UL << USB_EP_DOEPCTL_INTBULK_CNAK_Pos)             /*!< USB_EP DOEPCTL_INTBULK: CNAK Mask       */\r
+#define USB_EP_DOEPCTL_INTBULK_SNAK_Pos       27                                                      /*!< USB_EP DOEPCTL_INTBULK: SNAK Position   */\r
+#define USB_EP_DOEPCTL_INTBULK_SNAK_Msk       (0x01UL << USB_EP_DOEPCTL_INTBULK_SNAK_Pos)             /*!< USB_EP DOEPCTL_INTBULK: SNAK Mask       */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos   28                                                      /*!< USB_EP DOEPCTL_INTBULK: SetD0PID Position */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk   (0x01UL << USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos)         /*!< USB_EP DOEPCTL_INTBULK: SetD0PID Mask   */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos   29                                                      /*!< USB_EP DOEPCTL_INTBULK: SetD1PID Position */\r
+#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk   (0x01UL << USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos)         /*!< USB_EP DOEPCTL_INTBULK: SetD1PID Mask   */\r
+#define USB_EP_DOEPCTL_INTBULK_EPDis_Pos      30                                                      /*!< USB_EP DOEPCTL_INTBULK: EPDis Position  */\r
+#define USB_EP_DOEPCTL_INTBULK_EPDis_Msk      (0x01UL << USB_EP_DOEPCTL_INTBULK_EPDis_Pos)            /*!< USB_EP DOEPCTL_INTBULK: EPDis Mask      */\r
+#define USB_EP_DOEPCTL_INTBULK_EPEna_Pos      31                                                      /*!< USB_EP DOEPCTL_INTBULK: EPEna Position  */\r
+#define USB_EP_DOEPCTL_INTBULK_EPEna_Msk      (0x01UL << USB_EP_DOEPCTL_INTBULK_EPEna_Pos)            /*!< USB_EP DOEPCTL_INTBULK: EPEna Mask      */\r
+\r
+/* -------------------------------  USB_EP_DOEPINT  ------------------------------- */\r
+#define USB_EP_DOEPINT_XferCompl_Pos          0                                                       /*!< USB_EP DOEPINT: XferCompl Position      */\r
+#define USB_EP_DOEPINT_XferCompl_Msk          (0x01UL << USB_EP_DOEPINT_XferCompl_Pos)                /*!< USB_EP DOEPINT: XferCompl Mask          */\r
+#define USB_EP_DOEPINT_EPDisbld_Pos           1                                                       /*!< USB_EP DOEPINT: EPDisbld Position       */\r
+#define USB_EP_DOEPINT_EPDisbld_Msk           (0x01UL << USB_EP_DOEPINT_EPDisbld_Pos)                 /*!< USB_EP DOEPINT: EPDisbld Mask           */\r
+#define USB_EP_DOEPINT_AHBErr_Pos             2                                                       /*!< USB_EP DOEPINT: AHBErr Position         */\r
+#define USB_EP_DOEPINT_AHBErr_Msk             (0x01UL << USB_EP_DOEPINT_AHBErr_Pos)                   /*!< USB_EP DOEPINT: AHBErr Mask             */\r
+#define USB_EP_DOEPINT_SetUp_Pos              3                                                       /*!< USB_EP DOEPINT: SetUp Position          */\r
+#define USB_EP_DOEPINT_SetUp_Msk              (0x01UL << USB_EP_DOEPINT_SetUp_Pos)                    /*!< USB_EP DOEPINT: SetUp Mask              */\r
+#define USB_EP_DOEPINT_OUTTknEPdis_Pos        4                                                       /*!< USB_EP DOEPINT: OUTTknEPdis Position    */\r
+#define USB_EP_DOEPINT_OUTTknEPdis_Msk        (0x01UL << USB_EP_DOEPINT_OUTTknEPdis_Pos)              /*!< USB_EP DOEPINT: OUTTknEPdis Mask        */\r
+#define USB_EP_DOEPINT_StsPhseRcvd_Pos        5                                                       /*!< USB_EP DOEPINT: StsPhseRcvd Position    */\r
+#define USB_EP_DOEPINT_StsPhseRcvd_Msk        (0x01UL << USB_EP_DOEPINT_StsPhseRcvd_Pos)              /*!< USB_EP DOEPINT: StsPhseRcvd Mask        */\r
+#define USB_EP_DOEPINT_Back2BackSETup_Pos     6                                                       /*!< USB_EP DOEPINT: Back2BackSETup Position */\r
+#define USB_EP_DOEPINT_Back2BackSETup_Msk     (0x01UL << USB_EP_DOEPINT_Back2BackSETup_Pos)           /*!< USB_EP DOEPINT: Back2BackSETup Mask     */\r
+#define USB_EP_DOEPINT_BNAIntr_Pos            9                                                       /*!< USB_EP DOEPINT: BNAIntr Position        */\r
+#define USB_EP_DOEPINT_BNAIntr_Msk            (0x01UL << USB_EP_DOEPINT_BNAIntr_Pos)                  /*!< USB_EP DOEPINT: BNAIntr Mask            */\r
+#define USB_EP_DOEPINT_PktDrpSts_Pos          11                                                      /*!< USB_EP DOEPINT: PktDrpSts Position      */\r
+#define USB_EP_DOEPINT_PktDrpSts_Msk          (0x01UL << USB_EP_DOEPINT_PktDrpSts_Pos)                /*!< USB_EP DOEPINT: PktDrpSts Mask          */\r
+#define USB_EP_DOEPINT_BbleErrIntrpt_Pos      12                                                      /*!< USB_EP DOEPINT: BbleErrIntrpt Position  */\r
+#define USB_EP_DOEPINT_BbleErrIntrpt_Msk      (0x01UL << USB_EP_DOEPINT_BbleErrIntrpt_Pos)            /*!< USB_EP DOEPINT: BbleErrIntrpt Mask      */\r
+#define USB_EP_DOEPINT_NAKIntrpt_Pos          13                                                      /*!< USB_EP DOEPINT: NAKIntrpt Position      */\r
+#define USB_EP_DOEPINT_NAKIntrpt_Msk          (0x01UL << USB_EP_DOEPINT_NAKIntrpt_Pos)                /*!< USB_EP DOEPINT: NAKIntrpt Mask          */\r
+#define USB_EP_DOEPINT_NYETIntrpt_Pos         14                                                      /*!< USB_EP DOEPINT: NYETIntrpt Position     */\r
+#define USB_EP_DOEPINT_NYETIntrpt_Msk         (0x01UL << USB_EP_DOEPINT_NYETIntrpt_Pos)               /*!< USB_EP DOEPINT: NYETIntrpt Mask         */\r
+\r
+/* -----------------------------  USB_EP_DOEPTSIZ_ISO  ---------------------------- */\r
+#define USB_EP_DOEPTSIZ_ISO_XferSize_Pos      0                                                       /*!< USB_EP DOEPTSIZ_ISO: XferSize Position  */\r
+#define USB_EP_DOEPTSIZ_ISO_XferSize_Msk      (0x0007ffffUL << USB_EP_DOEPTSIZ_ISO_XferSize_Pos)      /*!< USB_EP DOEPTSIZ_ISO: XferSize Mask      */\r
+#define USB_EP_DOEPTSIZ_ISO_PktCnt_Pos        19                                                      /*!< USB_EP DOEPTSIZ_ISO: PktCnt Position    */\r
+#define USB_EP_DOEPTSIZ_ISO_PktCnt_Msk        (0x000003ffUL << USB_EP_DOEPTSIZ_ISO_PktCnt_Pos)        /*!< USB_EP DOEPTSIZ_ISO: PktCnt Mask        */\r
+#define USB_EP_DOEPTSIZ_ISO_RxDPID_Pos        29                                                      /*!< USB_EP DOEPTSIZ_ISO: RxDPID Position    */\r
+#define USB_EP_DOEPTSIZ_ISO_RxDPID_Msk        (0x03UL << USB_EP_DOEPTSIZ_ISO_RxDPID_Pos)              /*!< USB_EP DOEPTSIZ_ISO: RxDPID Mask        */\r
+\r
+/* ---------------------------  USB_EP_DOEPTSIZ_CONTROL  -------------------------- */\r
+#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos  0                                                       /*!< USB_EP DOEPTSIZ_CONTROL: XferSize Position */\r
+#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk  (0x0007ffffUL << USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos)  /*!< USB_EP DOEPTSIZ_CONTROL: XferSize Mask  */\r
+#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos    19                                                      /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt Position */\r
+#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk    (0x000003ffUL << USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos)    /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt Mask    */\r
+#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos    29                                                      /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt Position */\r
+#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk    (0x03UL << USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos)          /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt Mask    */\r
+\r
+/* -------------------------------  USB_EP_DOEPDMA  ------------------------------- */\r
+#define USB_EP_DOEPDMA_DMAAddr_Pos            0                                                       /*!< USB_EP DOEPDMA: DMAAddr Position        */\r
+#define USB_EP_DOEPDMA_DMAAddr_Msk            (0xffffffffUL << USB_EP_DOEPDMA_DMAAddr_Pos)            /*!< USB_EP DOEPDMA: DMAAddr Mask            */\r
+\r
+/* -------------------------------  USB_EP_DOEPDMAB  ------------------------------ */\r
+#define USB_EP_DOEPDMAB_DMABufferAddr_Pos     0                                                       /*!< USB_EP DOEPDMAB: DMABufferAddr Position */\r
+#define USB_EP_DOEPDMAB_DMABufferAddr_Msk     (0xffffffffUL << USB_EP_DOEPDMAB_DMABufferAddr_Pos)     /*!< USB_EP DOEPDMAB: DMABufferAddr Mask     */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'USB_CH' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  USB_CH_HCCHAR  ------------------------------- */\r
+#define USB_CH_HCCHAR_MPS_Pos                 0                                                       /*!< USB_CH HCCHAR: MPS Position             */\r
+#define USB_CH_HCCHAR_MPS_Msk                 (0x000007ffUL << USB_CH_HCCHAR_MPS_Pos)                 /*!< USB_CH HCCHAR: MPS Mask                 */\r
+#define USB_CH_HCCHAR_EPNum_Pos               11                                                      /*!< USB_CH HCCHAR: EPNum Position           */\r
+#define USB_CH_HCCHAR_EPNum_Msk               (0x0fUL << USB_CH_HCCHAR_EPNum_Pos)                     /*!< USB_CH HCCHAR: EPNum Mask               */\r
+#define USB_CH_HCCHAR_EPDir_Pos               15                                                      /*!< USB_CH HCCHAR: EPDir Position           */\r
+#define USB_CH_HCCHAR_EPDir_Msk               (0x01UL << USB_CH_HCCHAR_EPDir_Pos)                     /*!< USB_CH HCCHAR: EPDir Mask               */\r
+#define USB_CH_HCCHAR_EPType_Pos              18                                                      /*!< USB_CH HCCHAR: EPType Position          */\r
+#define USB_CH_HCCHAR_EPType_Msk              (0x03UL << USB_CH_HCCHAR_EPType_Pos)                    /*!< USB_CH HCCHAR: EPType Mask              */\r
+#define USB_CH_HCCHAR_MC_EC_Pos               20                                                      /*!< USB_CH HCCHAR: MC_EC Position           */\r
+#define USB_CH_HCCHAR_MC_EC_Msk               (0x03UL << USB_CH_HCCHAR_MC_EC_Pos)                     /*!< USB_CH HCCHAR: MC_EC Mask               */\r
+#define USB_CH_HCCHAR_DevAddr_Pos             22                                                      /*!< USB_CH HCCHAR: DevAddr Position         */\r
+#define USB_CH_HCCHAR_DevAddr_Msk             (0x7fUL << USB_CH_HCCHAR_DevAddr_Pos)                   /*!< USB_CH HCCHAR: DevAddr Mask             */\r
+#define USB_CH_HCCHAR_OddFrm_Pos              29                                                      /*!< USB_CH HCCHAR: OddFrm Position          */\r
+#define USB_CH_HCCHAR_OddFrm_Msk              (0x01UL << USB_CH_HCCHAR_OddFrm_Pos)                    /*!< USB_CH HCCHAR: OddFrm Mask              */\r
+#define USB_CH_HCCHAR_ChDis_Pos               30                                                      /*!< USB_CH HCCHAR: ChDis Position           */\r
+#define USB_CH_HCCHAR_ChDis_Msk               (0x01UL << USB_CH_HCCHAR_ChDis_Pos)                     /*!< USB_CH HCCHAR: ChDis Mask               */\r
+#define USB_CH_HCCHAR_ChEna_Pos               31                                                      /*!< USB_CH HCCHAR: ChEna Position           */\r
+#define USB_CH_HCCHAR_ChEna_Msk               (0x01UL << USB_CH_HCCHAR_ChEna_Pos)                     /*!< USB_CH HCCHAR: ChEna Mask               */\r
+\r
+/* --------------------------------  USB_CH_HCINT  -------------------------------- */\r
+#define USB_CH_HCINT_XferCompl_Pos            0                                                       /*!< USB_CH HCINT: XferCompl Position        */\r
+#define USB_CH_HCINT_XferCompl_Msk            (0x01UL << USB_CH_HCINT_XferCompl_Pos)                  /*!< USB_CH HCINT: XferCompl Mask            */\r
+#define USB_CH_HCINT_ChHltd_Pos               1                                                       /*!< USB_CH HCINT: ChHltd Position           */\r
+#define USB_CH_HCINT_ChHltd_Msk               (0x01UL << USB_CH_HCINT_ChHltd_Pos)                     /*!< USB_CH HCINT: ChHltd Mask               */\r
+#define USB_CH_HCINT_AHBErr_Pos               2                                                       /*!< USB_CH HCINT: AHBErr Position           */\r
+#define USB_CH_HCINT_AHBErr_Msk               (0x01UL << USB_CH_HCINT_AHBErr_Pos)                     /*!< USB_CH HCINT: AHBErr Mask               */\r
+#define USB_CH_HCINT_STALL_Pos                3                                                       /*!< USB_CH HCINT: STALL Position            */\r
+#define USB_CH_HCINT_STALL_Msk                (0x01UL << USB_CH_HCINT_STALL_Pos)                      /*!< USB_CH HCINT: STALL Mask                */\r
+#define USB_CH_HCINT_NAK_Pos                  4                                                       /*!< USB_CH HCINT: NAK Position              */\r
+#define USB_CH_HCINT_NAK_Msk                  (0x01UL << USB_CH_HCINT_NAK_Pos)                        /*!< USB_CH HCINT: NAK Mask                  */\r
+#define USB_CH_HCINT_ACK_Pos                  5                                                       /*!< USB_CH HCINT: ACK Position              */\r
+#define USB_CH_HCINT_ACK_Msk                  (0x01UL << USB_CH_HCINT_ACK_Pos)                        /*!< USB_CH HCINT: ACK Mask                  */\r
+#define USB_CH_HCINT_NYET_Pos                 6                                                       /*!< USB_CH HCINT: NYET Position             */\r
+#define USB_CH_HCINT_NYET_Msk                 (0x01UL << USB_CH_HCINT_NYET_Pos)                       /*!< USB_CH HCINT: NYET Mask                 */\r
+#define USB_CH_HCINT_XactErr_Pos              7                                                       /*!< USB_CH HCINT: XactErr Position          */\r
+#define USB_CH_HCINT_XactErr_Msk              (0x01UL << USB_CH_HCINT_XactErr_Pos)                    /*!< USB_CH HCINT: XactErr Mask              */\r
+#define USB_CH_HCINT_BblErr_Pos               8                                                       /*!< USB_CH HCINT: BblErr Position           */\r
+#define USB_CH_HCINT_BblErr_Msk               (0x01UL << USB_CH_HCINT_BblErr_Pos)                     /*!< USB_CH HCINT: BblErr Mask               */\r
+#define USB_CH_HCINT_FrmOvrun_Pos             9                                                       /*!< USB_CH HCINT: FrmOvrun Position         */\r
+#define USB_CH_HCINT_FrmOvrun_Msk             (0x01UL << USB_CH_HCINT_FrmOvrun_Pos)                   /*!< USB_CH HCINT: FrmOvrun Mask             */\r
+#define USB_CH_HCINT_DataTglErr_Pos           10                                                      /*!< USB_CH HCINT: DataTglErr Position       */\r
+#define USB_CH_HCINT_DataTglErr_Msk           (0x01UL << USB_CH_HCINT_DataTglErr_Pos)                 /*!< USB_CH HCINT: DataTglErr Mask           */\r
+#define USB_CH_HCINT_BNAIntr_Pos              11                                                      /*!< USB_CH HCINT: BNAIntr Position          */\r
+#define USB_CH_HCINT_BNAIntr_Msk              (0x01UL << USB_CH_HCINT_BNAIntr_Pos)                    /*!< USB_CH HCINT: BNAIntr Mask              */\r
+#define USB_CH_HCINT_XCS_XACT_ERR_Pos         12                                                      /*!< USB_CH HCINT: XCS_XACT_ERR Position     */\r
+#define USB_CH_HCINT_XCS_XACT_ERR_Msk         (0x01UL << USB_CH_HCINT_XCS_XACT_ERR_Pos)               /*!< USB_CH HCINT: XCS_XACT_ERR Mask         */\r
+#define USB_CH_HCINT_DESC_LST_ROLLIntr_Pos    13                                                      /*!< USB_CH HCINT: DESC_LST_ROLLIntr Position */\r
+#define USB_CH_HCINT_DESC_LST_ROLLIntr_Msk    (0x01UL << USB_CH_HCINT_DESC_LST_ROLLIntr_Pos)          /*!< USB_CH HCINT: DESC_LST_ROLLIntr Mask    */\r
+\r
+/* -------------------------------  USB_CH_HCINTMSK  ------------------------------ */\r
+#define USB_CH_HCINTMSK_XferComplMsk_Pos      0                                                       /*!< USB_CH HCINTMSK: XferComplMsk Position  */\r
+#define USB_CH_HCINTMSK_XferComplMsk_Msk      (0x01UL << USB_CH_HCINTMSK_XferComplMsk_Pos)            /*!< USB_CH HCINTMSK: XferComplMsk Mask      */\r
+#define USB_CH_HCINTMSK_ChHltdMsk_Pos         1                                                       /*!< USB_CH HCINTMSK: ChHltdMsk Position     */\r
+#define USB_CH_HCINTMSK_ChHltdMsk_Msk         (0x01UL << USB_CH_HCINTMSK_ChHltdMsk_Pos)               /*!< USB_CH HCINTMSK: ChHltdMsk Mask         */\r
+#define USB_CH_HCINTMSK_AHBErrMsk_Pos         2                                                       /*!< USB_CH HCINTMSK: AHBErrMsk Position     */\r
+#define USB_CH_HCINTMSK_AHBErrMsk_Msk         (0x01UL << USB_CH_HCINTMSK_AHBErrMsk_Pos)               /*!< USB_CH HCINTMSK: AHBErrMsk Mask         */\r
+#define USB_CH_HCINTMSK_StallMsk_Pos          3                                                       /*!< USB_CH HCINTMSK: StallMsk Position      */\r
+#define USB_CH_HCINTMSK_StallMsk_Msk          (0x01UL << USB_CH_HCINTMSK_StallMsk_Pos)                /*!< USB_CH HCINTMSK: StallMsk Mask          */\r
+#define USB_CH_HCINTMSK_NakMsk_Pos            4                                                       /*!< USB_CH HCINTMSK: NakMsk Position        */\r
+#define USB_CH_HCINTMSK_NakMsk_Msk            (0x01UL << USB_CH_HCINTMSK_NakMsk_Pos)                  /*!< USB_CH HCINTMSK: NakMsk Mask            */\r
+#define USB_CH_HCINTMSK_AckMsk_Pos            5                                                       /*!< USB_CH HCINTMSK: AckMsk Position        */\r
+#define USB_CH_HCINTMSK_AckMsk_Msk            (0x01UL << USB_CH_HCINTMSK_AckMsk_Pos)                  /*!< USB_CH HCINTMSK: AckMsk Mask            */\r
+#define USB_CH_HCINTMSK_NyetMsk_Pos           6                                                       /*!< USB_CH HCINTMSK: NyetMsk Position       */\r
+#define USB_CH_HCINTMSK_NyetMsk_Msk           (0x01UL << USB_CH_HCINTMSK_NyetMsk_Pos)                 /*!< USB_CH HCINTMSK: NyetMsk Mask           */\r
+#define USB_CH_HCINTMSK_XactErrMsk_Pos        7                                                       /*!< USB_CH HCINTMSK: XactErrMsk Position    */\r
+#define USB_CH_HCINTMSK_XactErrMsk_Msk        (0x01UL << USB_CH_HCINTMSK_XactErrMsk_Pos)              /*!< USB_CH HCINTMSK: XactErrMsk Mask        */\r
+#define USB_CH_HCINTMSK_BblErrMsk_Pos         8                                                       /*!< USB_CH HCINTMSK: BblErrMsk Position     */\r
+#define USB_CH_HCINTMSK_BblErrMsk_Msk         (0x01UL << USB_CH_HCINTMSK_BblErrMsk_Pos)               /*!< USB_CH HCINTMSK: BblErrMsk Mask         */\r
+#define USB_CH_HCINTMSK_FrmOvrunMsk_Pos       9                                                       /*!< USB_CH HCINTMSK: FrmOvrunMsk Position   */\r
+#define USB_CH_HCINTMSK_FrmOvrunMsk_Msk       (0x01UL << USB_CH_HCINTMSK_FrmOvrunMsk_Pos)             /*!< USB_CH HCINTMSK: FrmOvrunMsk Mask       */\r
+#define USB_CH_HCINTMSK_DataTglErrMsk_Pos     10                                                      /*!< USB_CH HCINTMSK: DataTglErrMsk Position */\r
+#define USB_CH_HCINTMSK_DataTglErrMsk_Msk     (0x01UL << USB_CH_HCINTMSK_DataTglErrMsk_Pos)           /*!< USB_CH HCINTMSK: DataTglErrMsk Mask     */\r
+#define USB_CH_HCINTMSK_BNAIntrMsk_Pos        11                                                      /*!< USB_CH HCINTMSK: BNAIntrMsk Position    */\r
+#define USB_CH_HCINTMSK_BNAIntrMsk_Msk        (0x01UL << USB_CH_HCINTMSK_BNAIntrMsk_Pos)              /*!< USB_CH HCINTMSK: BNAIntrMsk Mask        */\r
+#define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos 13                                                   /*!< USB_CH HCINTMSK: DESC_LST_ROLLIntrMsk Position */\r
+#define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Msk (0x01UL << USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos) /*!< USB_CH HCINTMSK: DESC_LST_ROLLIntrMsk Mask */\r
+\r
+/* --------------------------  USB_CH_HCTSIZ_BUFFERMODE  -------------------------- */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos 0                                                       /*!< USB_CH HCTSIZ_BUFFERMODE: XferSize Position */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Msk (0x0007ffffUL << USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos) /*!< USB_CH HCTSIZ_BUFFERMODE: XferSize Mask */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos   19                                                      /*!< USB_CH HCTSIZ_BUFFERMODE: PktCnt Position */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk   (0x000003ffUL << USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos)   /*!< USB_CH HCTSIZ_BUFFERMODE: PktCnt Mask   */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos      29                                                      /*!< USB_CH HCTSIZ_BUFFERMODE: Pid Position  */\r
+#define USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk      (0x03UL << USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos)            /*!< USB_CH HCTSIZ_BUFFERMODE: Pid Mask      */\r
+\r
+/* --------------------------  USB_CH_HCTSIZ_SCATGATHER  -------------------------- */\r
+#define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos 0                                                     /*!< USB_CH HCTSIZ_SCATGATHER: SCHED_INFO Position */\r
+#define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Msk (0x000000ffUL << USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos)/*!< USB_CH HCTSIZ_SCATGATHER: SCHED_INFO Mask */\r
+#define USB_CH_HCTSIZ_SCATGATHER_NTD_Pos      8                                                       /*!< USB_CH HCTSIZ_SCATGATHER: NTD Position  */\r
+#define USB_CH_HCTSIZ_SCATGATHER_NTD_Msk      (0x000000ffUL << USB_CH_HCTSIZ_SCATGATHER_NTD_Pos)      /*!< USB_CH HCTSIZ_SCATGATHER: NTD Mask      */\r
+#define USB_CH_HCTSIZ_SCATGATHER_Pid_Pos      29                                                      /*!< USB_CH HCTSIZ_SCATGATHER: Pid Position  */\r
+#define USB_CH_HCTSIZ_SCATGATHER_Pid_Msk      (0x03UL << USB_CH_HCTSIZ_SCATGATHER_Pid_Pos)            /*!< USB_CH HCTSIZ_SCATGATHER: Pid Mask      */\r
+\r
+/* ---------------------------  USB_CH_HCDMA_BUFFERMODE  -------------------------- */\r
+#define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos   0                                                       /*!< USB_CH HCDMA_BUFFERMODE: DMAAddr Position */\r
+#define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Msk   (0xffffffffUL << USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos)   /*!< USB_CH HCDMA_BUFFERMODE: DMAAddr Mask   */\r
+\r
+/* ---------------------------  USB_CH_HCDMA_SCATGATHER  -------------------------- */\r
+#define USB_CH_HCDMA_SCATGATHER_CTD_Pos       3                                                       /*!< USB_CH HCDMA_SCATGATHER: CTD Position   */\r
+#define USB_CH_HCDMA_SCATGATHER_CTD_Msk       (0x3fUL << USB_CH_HCDMA_SCATGATHER_CTD_Pos)             /*!< USB_CH HCDMA_SCATGATHER: CTD Mask       */\r
+#define USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos   9                                                       /*!< USB_CH HCDMA_SCATGATHER: DMAAddr Position */\r
+#define USB_CH_HCDMA_SCATGATHER_DMAAddr_Msk   (0x007fffffUL << USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos)   /*!< USB_CH HCDMA_SCATGATHER: DMAAddr Mask   */\r
+\r
+/* --------------------------------  USB_CH_HCDMAB  ------------------------------- */\r
+#define USB_CH_HCDMAB_Buffer_Address_Pos      0                                                       /*!< USB_CH HCDMAB: Buffer_Address Position  */\r
+#define USB_CH_HCDMAB_Buffer_Address_Msk      (0xffffffffUL << USB_CH_HCDMAB_Buffer_Address_Pos)      /*!< USB_CH HCDMAB: Buffer_Address Mask      */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'USIC' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  USIC_ID  ---------------------------------- */\r
+#define USIC_ID_MOD_REV_Pos                   0                                                       /*!< USIC ID: MOD_REV Position               */\r
+#define USIC_ID_MOD_REV_Msk                   (0x000000ffUL << USIC_ID_MOD_REV_Pos)                   /*!< USIC ID: MOD_REV Mask                   */\r
+#define USIC_ID_MOD_TYPE_Pos                  8                                                       /*!< USIC ID: MOD_TYPE Position              */\r
+#define USIC_ID_MOD_TYPE_Msk                  (0x000000ffUL << USIC_ID_MOD_TYPE_Pos)                  /*!< USIC ID: MOD_TYPE Mask                  */\r
+#define USIC_ID_MOD_NUMBER_Pos                16                                                      /*!< USIC ID: MOD_NUMBER Position            */\r
+#define USIC_ID_MOD_NUMBER_Msk                (0x0000ffffUL << USIC_ID_MOD_NUMBER_Pos)                /*!< USIC ID: MOD_NUMBER Mask                */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'USIC_CH' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  USIC_CH_CCFG  -------------------------------- */\r
+#define USIC_CH_CCFG_SSC_Pos                  0                                                       /*!< USIC_CH CCFG: SSC Position              */\r
+#define USIC_CH_CCFG_SSC_Msk                  (0x01UL << USIC_CH_CCFG_SSC_Pos)                        /*!< USIC_CH CCFG: SSC Mask                  */\r
+#define USIC_CH_CCFG_ASC_Pos                  1                                                       /*!< USIC_CH CCFG: ASC Position              */\r
+#define USIC_CH_CCFG_ASC_Msk                  (0x01UL << USIC_CH_CCFG_ASC_Pos)                        /*!< USIC_CH CCFG: ASC Mask                  */\r
+#define USIC_CH_CCFG_IIC_Pos                  2                                                       /*!< USIC_CH CCFG: IIC Position              */\r
+#define USIC_CH_CCFG_IIC_Msk                  (0x01UL << USIC_CH_CCFG_IIC_Pos)                        /*!< USIC_CH CCFG: IIC Mask                  */\r
+#define USIC_CH_CCFG_IIS_Pos                  3                                                       /*!< USIC_CH CCFG: IIS Position              */\r
+#define USIC_CH_CCFG_IIS_Msk                  (0x01UL << USIC_CH_CCFG_IIS_Pos)                        /*!< USIC_CH CCFG: IIS Mask                  */\r
+#define USIC_CH_CCFG_RB_Pos                   6                                                       /*!< USIC_CH CCFG: RB Position               */\r
+#define USIC_CH_CCFG_RB_Msk                   (0x01UL << USIC_CH_CCFG_RB_Pos)                         /*!< USIC_CH CCFG: RB Mask                   */\r
+#define USIC_CH_CCFG_TB_Pos                   7                                                       /*!< USIC_CH CCFG: TB Position               */\r
+#define USIC_CH_CCFG_TB_Msk                   (0x01UL << USIC_CH_CCFG_TB_Pos)                         /*!< USIC_CH CCFG: TB Mask                   */\r
+\r
+/* --------------------------------  USIC_CH_KSCFG  ------------------------------- */\r
+#define USIC_CH_KSCFG_MODEN_Pos               0                                                       /*!< USIC_CH KSCFG: MODEN Position           */\r
+#define USIC_CH_KSCFG_MODEN_Msk               (0x01UL << USIC_CH_KSCFG_MODEN_Pos)                     /*!< USIC_CH KSCFG: MODEN Mask               */\r
+#define USIC_CH_KSCFG_BPMODEN_Pos             1                                                       /*!< USIC_CH KSCFG: BPMODEN Position         */\r
+#define USIC_CH_KSCFG_BPMODEN_Msk             (0x01UL << USIC_CH_KSCFG_BPMODEN_Pos)                   /*!< USIC_CH KSCFG: BPMODEN Mask             */\r
+#define USIC_CH_KSCFG_NOMCFG_Pos              4                                                       /*!< USIC_CH KSCFG: NOMCFG Position          */\r
+#define USIC_CH_KSCFG_NOMCFG_Msk              (0x03UL << USIC_CH_KSCFG_NOMCFG_Pos)                    /*!< USIC_CH KSCFG: NOMCFG Mask              */\r
+#define USIC_CH_KSCFG_BPNOM_Pos               7                                                       /*!< USIC_CH KSCFG: BPNOM Position           */\r
+#define USIC_CH_KSCFG_BPNOM_Msk               (0x01UL << USIC_CH_KSCFG_BPNOM_Pos)                     /*!< USIC_CH KSCFG: BPNOM Mask               */\r
+#define USIC_CH_KSCFG_SUMCFG_Pos              8                                                       /*!< USIC_CH KSCFG: SUMCFG Position          */\r
+#define USIC_CH_KSCFG_SUMCFG_Msk              (0x03UL << USIC_CH_KSCFG_SUMCFG_Pos)                    /*!< USIC_CH KSCFG: SUMCFG Mask              */\r
+#define USIC_CH_KSCFG_BPSUM_Pos               11                                                      /*!< USIC_CH KSCFG: BPSUM Position           */\r
+#define USIC_CH_KSCFG_BPSUM_Msk               (0x01UL << USIC_CH_KSCFG_BPSUM_Pos)                     /*!< USIC_CH KSCFG: BPSUM Mask               */\r
+\r
+/* ---------------------------------  USIC_CH_FDR  -------------------------------- */\r
+#define USIC_CH_FDR_STEP_Pos                  0                                                       /*!< USIC_CH FDR: STEP Position              */\r
+#define USIC_CH_FDR_STEP_Msk                  (0x000003ffUL << USIC_CH_FDR_STEP_Pos)                  /*!< USIC_CH FDR: STEP Mask                  */\r
+#define USIC_CH_FDR_DM_Pos                    14                                                      /*!< USIC_CH FDR: DM Position                */\r
+#define USIC_CH_FDR_DM_Msk                    (0x03UL << USIC_CH_FDR_DM_Pos)                          /*!< USIC_CH FDR: DM Mask                    */\r
+#define USIC_CH_FDR_RESULT_Pos                16                                                      /*!< USIC_CH FDR: RESULT Position            */\r
+#define USIC_CH_FDR_RESULT_Msk                (0x000003ffUL << USIC_CH_FDR_RESULT_Pos)                /*!< USIC_CH FDR: RESULT Mask                */\r
+\r
+/* ---------------------------------  USIC_CH_BRG  -------------------------------- */\r
+#define USIC_CH_BRG_CLKSEL_Pos                0                                                       /*!< USIC_CH BRG: CLKSEL Position            */\r
+#define USIC_CH_BRG_CLKSEL_Msk                (0x03UL << USIC_CH_BRG_CLKSEL_Pos)                      /*!< USIC_CH BRG: CLKSEL Mask                */\r
+#define USIC_CH_BRG_TMEN_Pos                  3                                                       /*!< USIC_CH BRG: TMEN Position              */\r
+#define USIC_CH_BRG_TMEN_Msk                  (0x01UL << USIC_CH_BRG_TMEN_Pos)                        /*!< USIC_CH BRG: TMEN Mask                  */\r
+#define USIC_CH_BRG_PPPEN_Pos                 4                                                       /*!< USIC_CH BRG: PPPEN Position             */\r
+#define USIC_CH_BRG_PPPEN_Msk                 (0x01UL << USIC_CH_BRG_PPPEN_Pos)                       /*!< USIC_CH BRG: PPPEN Mask                 */\r
+#define USIC_CH_BRG_CTQSEL_Pos                6                                                       /*!< USIC_CH BRG: CTQSEL Position            */\r
+#define USIC_CH_BRG_CTQSEL_Msk                (0x03UL << USIC_CH_BRG_CTQSEL_Pos)                      /*!< USIC_CH BRG: CTQSEL Mask                */\r
+#define USIC_CH_BRG_PCTQ_Pos                  8                                                       /*!< USIC_CH BRG: PCTQ Position              */\r
+#define USIC_CH_BRG_PCTQ_Msk                  (0x03UL << USIC_CH_BRG_PCTQ_Pos)                        /*!< USIC_CH BRG: PCTQ Mask                  */\r
+#define USIC_CH_BRG_DCTQ_Pos                  10                                                      /*!< USIC_CH BRG: DCTQ Position              */\r
+#define USIC_CH_BRG_DCTQ_Msk                  (0x1fUL << USIC_CH_BRG_DCTQ_Pos)                        /*!< USIC_CH BRG: DCTQ Mask                  */\r
+#define USIC_CH_BRG_PDIV_Pos                  16                                                      /*!< USIC_CH BRG: PDIV Position              */\r
+#define USIC_CH_BRG_PDIV_Msk                  (0x000003ffUL << USIC_CH_BRG_PDIV_Pos)                  /*!< USIC_CH BRG: PDIV Mask                  */\r
+#define USIC_CH_BRG_SCLKOSEL_Pos              28                                                      /*!< USIC_CH BRG: SCLKOSEL Position          */\r
+#define USIC_CH_BRG_SCLKOSEL_Msk              (0x01UL << USIC_CH_BRG_SCLKOSEL_Pos)                    /*!< USIC_CH BRG: SCLKOSEL Mask              */\r
+#define USIC_CH_BRG_MCLKCFG_Pos               29                                                      /*!< USIC_CH BRG: MCLKCFG Position           */\r
+#define USIC_CH_BRG_MCLKCFG_Msk               (0x01UL << USIC_CH_BRG_MCLKCFG_Pos)                     /*!< USIC_CH BRG: MCLKCFG Mask               */\r
+#define USIC_CH_BRG_SCLKCFG_Pos               30                                                      /*!< USIC_CH BRG: SCLKCFG Position           */\r
+#define USIC_CH_BRG_SCLKCFG_Msk               (0x03UL << USIC_CH_BRG_SCLKCFG_Pos)                     /*!< USIC_CH BRG: SCLKCFG Mask               */\r
+\r
+/* --------------------------------  USIC_CH_INPR  -------------------------------- */\r
+#define USIC_CH_INPR_TSINP_Pos                0                                                       /*!< USIC_CH INPR: TSINP Position            */\r
+#define USIC_CH_INPR_TSINP_Msk                (0x07UL << USIC_CH_INPR_TSINP_Pos)                      /*!< USIC_CH INPR: TSINP Mask                */\r
+#define USIC_CH_INPR_TBINP_Pos                4                                                       /*!< USIC_CH INPR: TBINP Position            */\r
+#define USIC_CH_INPR_TBINP_Msk                (0x07UL << USIC_CH_INPR_TBINP_Pos)                      /*!< USIC_CH INPR: TBINP Mask                */\r
+#define USIC_CH_INPR_RINP_Pos                 8                                                       /*!< USIC_CH INPR: RINP Position             */\r
+#define USIC_CH_INPR_RINP_Msk                 (0x07UL << USIC_CH_INPR_RINP_Pos)                       /*!< USIC_CH INPR: RINP Mask                 */\r
+#define USIC_CH_INPR_AINP_Pos                 12                                                      /*!< USIC_CH INPR: AINP Position             */\r
+#define USIC_CH_INPR_AINP_Msk                 (0x07UL << USIC_CH_INPR_AINP_Pos)                       /*!< USIC_CH INPR: AINP Mask                 */\r
+#define USIC_CH_INPR_PINP_Pos                 16                                                      /*!< USIC_CH INPR: PINP Position             */\r
+#define USIC_CH_INPR_PINP_Msk                 (0x07UL << USIC_CH_INPR_PINP_Pos)                       /*!< USIC_CH INPR: PINP Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX0CR  ------------------------------- */\r
+#define USIC_CH_DX0CR_DSEL_Pos                0                                                       /*!< USIC_CH DX0CR: DSEL Position            */\r
+#define USIC_CH_DX0CR_DSEL_Msk                (0x07UL << USIC_CH_DX0CR_DSEL_Pos)                      /*!< USIC_CH DX0CR: DSEL Mask                */\r
+#define USIC_CH_DX0CR_INSW_Pos                4                                                       /*!< USIC_CH DX0CR: INSW Position            */\r
+#define USIC_CH_DX0CR_INSW_Msk                (0x01UL << USIC_CH_DX0CR_INSW_Pos)                      /*!< USIC_CH DX0CR: INSW Mask                */\r
+#define USIC_CH_DX0CR_DFEN_Pos                5                                                       /*!< USIC_CH DX0CR: DFEN Position            */\r
+#define USIC_CH_DX0CR_DFEN_Msk                (0x01UL << USIC_CH_DX0CR_DFEN_Pos)                      /*!< USIC_CH DX0CR: DFEN Mask                */\r
+#define USIC_CH_DX0CR_DSEN_Pos                6                                                       /*!< USIC_CH DX0CR: DSEN Position            */\r
+#define USIC_CH_DX0CR_DSEN_Msk                (0x01UL << USIC_CH_DX0CR_DSEN_Pos)                      /*!< USIC_CH DX0CR: DSEN Mask                */\r
+#define USIC_CH_DX0CR_DPOL_Pos                8                                                       /*!< USIC_CH DX0CR: DPOL Position            */\r
+#define USIC_CH_DX0CR_DPOL_Msk                (0x01UL << USIC_CH_DX0CR_DPOL_Pos)                      /*!< USIC_CH DX0CR: DPOL Mask                */\r
+#define USIC_CH_DX0CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX0CR: SFSEL Position           */\r
+#define USIC_CH_DX0CR_SFSEL_Msk               (0x01UL << USIC_CH_DX0CR_SFSEL_Pos)                     /*!< USIC_CH DX0CR: SFSEL Mask               */\r
+#define USIC_CH_DX0CR_CM_Pos                  10                                                      /*!< USIC_CH DX0CR: CM Position              */\r
+#define USIC_CH_DX0CR_CM_Msk                  (0x03UL << USIC_CH_DX0CR_CM_Pos)                        /*!< USIC_CH DX0CR: CM Mask                  */\r
+#define USIC_CH_DX0CR_DXS_Pos                 15                                                      /*!< USIC_CH DX0CR: DXS Position             */\r
+#define USIC_CH_DX0CR_DXS_Msk                 (0x01UL << USIC_CH_DX0CR_DXS_Pos)                       /*!< USIC_CH DX0CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX1CR  ------------------------------- */\r
+#define USIC_CH_DX1CR_DSEL_Pos                0                                                       /*!< USIC_CH DX1CR: DSEL Position            */\r
+#define USIC_CH_DX1CR_DSEL_Msk                (0x07UL << USIC_CH_DX1CR_DSEL_Pos)                      /*!< USIC_CH DX1CR: DSEL Mask                */\r
+#define USIC_CH_DX1CR_DCEN_Pos                3                                                       /*!< USIC_CH DX1CR: DCEN Position            */\r
+#define USIC_CH_DX1CR_DCEN_Msk                (0x01UL << USIC_CH_DX1CR_DCEN_Pos)                      /*!< USIC_CH DX1CR: DCEN Mask                */\r
+#define USIC_CH_DX1CR_INSW_Pos                4                                                       /*!< USIC_CH DX1CR: INSW Position            */\r
+#define USIC_CH_DX1CR_INSW_Msk                (0x01UL << USIC_CH_DX1CR_INSW_Pos)                      /*!< USIC_CH DX1CR: INSW Mask                */\r
+#define USIC_CH_DX1CR_DFEN_Pos                5                                                       /*!< USIC_CH DX1CR: DFEN Position            */\r
+#define USIC_CH_DX1CR_DFEN_Msk                (0x01UL << USIC_CH_DX1CR_DFEN_Pos)                      /*!< USIC_CH DX1CR: DFEN Mask                */\r
+#define USIC_CH_DX1CR_DSEN_Pos                6                                                       /*!< USIC_CH DX1CR: DSEN Position            */\r
+#define USIC_CH_DX1CR_DSEN_Msk                (0x01UL << USIC_CH_DX1CR_DSEN_Pos)                      /*!< USIC_CH DX1CR: DSEN Mask                */\r
+#define USIC_CH_DX1CR_DPOL_Pos                8                                                       /*!< USIC_CH DX1CR: DPOL Position            */\r
+#define USIC_CH_DX1CR_DPOL_Msk                (0x01UL << USIC_CH_DX1CR_DPOL_Pos)                      /*!< USIC_CH DX1CR: DPOL Mask                */\r
+#define USIC_CH_DX1CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX1CR: SFSEL Position           */\r
+#define USIC_CH_DX1CR_SFSEL_Msk               (0x01UL << USIC_CH_DX1CR_SFSEL_Pos)                     /*!< USIC_CH DX1CR: SFSEL Mask               */\r
+#define USIC_CH_DX1CR_CM_Pos                  10                                                      /*!< USIC_CH DX1CR: CM Position              */\r
+#define USIC_CH_DX1CR_CM_Msk                  (0x03UL << USIC_CH_DX1CR_CM_Pos)                        /*!< USIC_CH DX1CR: CM Mask                  */\r
+#define USIC_CH_DX1CR_DXS_Pos                 15                                                      /*!< USIC_CH DX1CR: DXS Position             */\r
+#define USIC_CH_DX1CR_DXS_Msk                 (0x01UL << USIC_CH_DX1CR_DXS_Pos)                       /*!< USIC_CH DX1CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX2CR  ------------------------------- */\r
+#define USIC_CH_DX2CR_DSEL_Pos                0                                                       /*!< USIC_CH DX2CR: DSEL Position            */\r
+#define USIC_CH_DX2CR_DSEL_Msk                (0x07UL << USIC_CH_DX2CR_DSEL_Pos)                      /*!< USIC_CH DX2CR: DSEL Mask                */\r
+#define USIC_CH_DX2CR_INSW_Pos                4                                                       /*!< USIC_CH DX2CR: INSW Position            */\r
+#define USIC_CH_DX2CR_INSW_Msk                (0x01UL << USIC_CH_DX2CR_INSW_Pos)                      /*!< USIC_CH DX2CR: INSW Mask                */\r
+#define USIC_CH_DX2CR_DFEN_Pos                5                                                       /*!< USIC_CH DX2CR: DFEN Position            */\r
+#define USIC_CH_DX2CR_DFEN_Msk                (0x01UL << USIC_CH_DX2CR_DFEN_Pos)                      /*!< USIC_CH DX2CR: DFEN Mask                */\r
+#define USIC_CH_DX2CR_DSEN_Pos                6                                                       /*!< USIC_CH DX2CR: DSEN Position            */\r
+#define USIC_CH_DX2CR_DSEN_Msk                (0x01UL << USIC_CH_DX2CR_DSEN_Pos)                      /*!< USIC_CH DX2CR: DSEN Mask                */\r
+#define USIC_CH_DX2CR_DPOL_Pos                8                                                       /*!< USIC_CH DX2CR: DPOL Position            */\r
+#define USIC_CH_DX2CR_DPOL_Msk                (0x01UL << USIC_CH_DX2CR_DPOL_Pos)                      /*!< USIC_CH DX2CR: DPOL Mask                */\r
+#define USIC_CH_DX2CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX2CR: SFSEL Position           */\r
+#define USIC_CH_DX2CR_SFSEL_Msk               (0x01UL << USIC_CH_DX2CR_SFSEL_Pos)                     /*!< USIC_CH DX2CR: SFSEL Mask               */\r
+#define USIC_CH_DX2CR_CM_Pos                  10                                                      /*!< USIC_CH DX2CR: CM Position              */\r
+#define USIC_CH_DX2CR_CM_Msk                  (0x03UL << USIC_CH_DX2CR_CM_Pos)                        /*!< USIC_CH DX2CR: CM Mask                  */\r
+#define USIC_CH_DX2CR_DXS_Pos                 15                                                      /*!< USIC_CH DX2CR: DXS Position             */\r
+#define USIC_CH_DX2CR_DXS_Msk                 (0x01UL << USIC_CH_DX2CR_DXS_Pos)                       /*!< USIC_CH DX2CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX3CR  ------------------------------- */\r
+#define USIC_CH_DX3CR_DSEL_Pos                0                                                       /*!< USIC_CH DX3CR: DSEL Position            */\r
+#define USIC_CH_DX3CR_DSEL_Msk                (0x07UL << USIC_CH_DX3CR_DSEL_Pos)                      /*!< USIC_CH DX3CR: DSEL Mask                */\r
+#define USIC_CH_DX3CR_INSW_Pos                4                                                       /*!< USIC_CH DX3CR: INSW Position            */\r
+#define USIC_CH_DX3CR_INSW_Msk                (0x01UL << USIC_CH_DX3CR_INSW_Pos)                      /*!< USIC_CH DX3CR: INSW Mask                */\r
+#define USIC_CH_DX3CR_DFEN_Pos                5                                                       /*!< USIC_CH DX3CR: DFEN Position            */\r
+#define USIC_CH_DX3CR_DFEN_Msk                (0x01UL << USIC_CH_DX3CR_DFEN_Pos)                      /*!< USIC_CH DX3CR: DFEN Mask                */\r
+#define USIC_CH_DX3CR_DSEN_Pos                6                                                       /*!< USIC_CH DX3CR: DSEN Position            */\r
+#define USIC_CH_DX3CR_DSEN_Msk                (0x01UL << USIC_CH_DX3CR_DSEN_Pos)                      /*!< USIC_CH DX3CR: DSEN Mask                */\r
+#define USIC_CH_DX3CR_DPOL_Pos                8                                                       /*!< USIC_CH DX3CR: DPOL Position            */\r
+#define USIC_CH_DX3CR_DPOL_Msk                (0x01UL << USIC_CH_DX3CR_DPOL_Pos)                      /*!< USIC_CH DX3CR: DPOL Mask                */\r
+#define USIC_CH_DX3CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX3CR: SFSEL Position           */\r
+#define USIC_CH_DX3CR_SFSEL_Msk               (0x01UL << USIC_CH_DX3CR_SFSEL_Pos)                     /*!< USIC_CH DX3CR: SFSEL Mask               */\r
+#define USIC_CH_DX3CR_CM_Pos                  10                                                      /*!< USIC_CH DX3CR: CM Position              */\r
+#define USIC_CH_DX3CR_CM_Msk                  (0x03UL << USIC_CH_DX3CR_CM_Pos)                        /*!< USIC_CH DX3CR: CM Mask                  */\r
+#define USIC_CH_DX3CR_DXS_Pos                 15                                                      /*!< USIC_CH DX3CR: DXS Position             */\r
+#define USIC_CH_DX3CR_DXS_Msk                 (0x01UL << USIC_CH_DX3CR_DXS_Pos)                       /*!< USIC_CH DX3CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX4CR  ------------------------------- */\r
+#define USIC_CH_DX4CR_DSEL_Pos                0                                                       /*!< USIC_CH DX4CR: DSEL Position            */\r
+#define USIC_CH_DX4CR_DSEL_Msk                (0x07UL << USIC_CH_DX4CR_DSEL_Pos)                      /*!< USIC_CH DX4CR: DSEL Mask                */\r
+#define USIC_CH_DX4CR_INSW_Pos                4                                                       /*!< USIC_CH DX4CR: INSW Position            */\r
+#define USIC_CH_DX4CR_INSW_Msk                (0x01UL << USIC_CH_DX4CR_INSW_Pos)                      /*!< USIC_CH DX4CR: INSW Mask                */\r
+#define USIC_CH_DX4CR_DFEN_Pos                5                                                       /*!< USIC_CH DX4CR: DFEN Position            */\r
+#define USIC_CH_DX4CR_DFEN_Msk                (0x01UL << USIC_CH_DX4CR_DFEN_Pos)                      /*!< USIC_CH DX4CR: DFEN Mask                */\r
+#define USIC_CH_DX4CR_DSEN_Pos                6                                                       /*!< USIC_CH DX4CR: DSEN Position            */\r
+#define USIC_CH_DX4CR_DSEN_Msk                (0x01UL << USIC_CH_DX4CR_DSEN_Pos)                      /*!< USIC_CH DX4CR: DSEN Mask                */\r
+#define USIC_CH_DX4CR_DPOL_Pos                8                                                       /*!< USIC_CH DX4CR: DPOL Position            */\r
+#define USIC_CH_DX4CR_DPOL_Msk                (0x01UL << USIC_CH_DX4CR_DPOL_Pos)                      /*!< USIC_CH DX4CR: DPOL Mask                */\r
+#define USIC_CH_DX4CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX4CR: SFSEL Position           */\r
+#define USIC_CH_DX4CR_SFSEL_Msk               (0x01UL << USIC_CH_DX4CR_SFSEL_Pos)                     /*!< USIC_CH DX4CR: SFSEL Mask               */\r
+#define USIC_CH_DX4CR_CM_Pos                  10                                                      /*!< USIC_CH DX4CR: CM Position              */\r
+#define USIC_CH_DX4CR_CM_Msk                  (0x03UL << USIC_CH_DX4CR_CM_Pos)                        /*!< USIC_CH DX4CR: CM Mask                  */\r
+#define USIC_CH_DX4CR_DXS_Pos                 15                                                      /*!< USIC_CH DX4CR: DXS Position             */\r
+#define USIC_CH_DX4CR_DXS_Msk                 (0x01UL << USIC_CH_DX4CR_DXS_Pos)                       /*!< USIC_CH DX4CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_DX5CR  ------------------------------- */\r
+#define USIC_CH_DX5CR_DSEL_Pos                0                                                       /*!< USIC_CH DX5CR: DSEL Position            */\r
+#define USIC_CH_DX5CR_DSEL_Msk                (0x07UL << USIC_CH_DX5CR_DSEL_Pos)                      /*!< USIC_CH DX5CR: DSEL Mask                */\r
+#define USIC_CH_DX5CR_INSW_Pos                4                                                       /*!< USIC_CH DX5CR: INSW Position            */\r
+#define USIC_CH_DX5CR_INSW_Msk                (0x01UL << USIC_CH_DX5CR_INSW_Pos)                      /*!< USIC_CH DX5CR: INSW Mask                */\r
+#define USIC_CH_DX5CR_DFEN_Pos                5                                                       /*!< USIC_CH DX5CR: DFEN Position            */\r
+#define USIC_CH_DX5CR_DFEN_Msk                (0x01UL << USIC_CH_DX5CR_DFEN_Pos)                      /*!< USIC_CH DX5CR: DFEN Mask                */\r
+#define USIC_CH_DX5CR_DSEN_Pos                6                                                       /*!< USIC_CH DX5CR: DSEN Position            */\r
+#define USIC_CH_DX5CR_DSEN_Msk                (0x01UL << USIC_CH_DX5CR_DSEN_Pos)                      /*!< USIC_CH DX5CR: DSEN Mask                */\r
+#define USIC_CH_DX5CR_DPOL_Pos                8                                                       /*!< USIC_CH DX5CR: DPOL Position            */\r
+#define USIC_CH_DX5CR_DPOL_Msk                (0x01UL << USIC_CH_DX5CR_DPOL_Pos)                      /*!< USIC_CH DX5CR: DPOL Mask                */\r
+#define USIC_CH_DX5CR_SFSEL_Pos               9                                                       /*!< USIC_CH DX5CR: SFSEL Position           */\r
+#define USIC_CH_DX5CR_SFSEL_Msk               (0x01UL << USIC_CH_DX5CR_SFSEL_Pos)                     /*!< USIC_CH DX5CR: SFSEL Mask               */\r
+#define USIC_CH_DX5CR_CM_Pos                  10                                                      /*!< USIC_CH DX5CR: CM Position              */\r
+#define USIC_CH_DX5CR_CM_Msk                  (0x03UL << USIC_CH_DX5CR_CM_Pos)                        /*!< USIC_CH DX5CR: CM Mask                  */\r
+#define USIC_CH_DX5CR_DXS_Pos                 15                                                      /*!< USIC_CH DX5CR: DXS Position             */\r
+#define USIC_CH_DX5CR_DXS_Msk                 (0x01UL << USIC_CH_DX5CR_DXS_Pos)                       /*!< USIC_CH DX5CR: DXS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_SCTR  -------------------------------- */\r
+#define USIC_CH_SCTR_SDIR_Pos                 0                                                       /*!< USIC_CH SCTR: SDIR Position             */\r
+#define USIC_CH_SCTR_SDIR_Msk                 (0x01UL << USIC_CH_SCTR_SDIR_Pos)                       /*!< USIC_CH SCTR: SDIR Mask                 */\r
+#define USIC_CH_SCTR_PDL_Pos                  1                                                       /*!< USIC_CH SCTR: PDL Position              */\r
+#define USIC_CH_SCTR_PDL_Msk                  (0x01UL << USIC_CH_SCTR_PDL_Pos)                        /*!< USIC_CH SCTR: PDL Mask                  */\r
+#define USIC_CH_SCTR_DSM_Pos                  2                                                       /*!< USIC_CH SCTR: DSM Position              */\r
+#define USIC_CH_SCTR_DSM_Msk                  (0x03UL << USIC_CH_SCTR_DSM_Pos)                        /*!< USIC_CH SCTR: DSM Mask                  */\r
+#define USIC_CH_SCTR_HPCDIR_Pos               4                                                       /*!< USIC_CH SCTR: HPCDIR Position           */\r
+#define USIC_CH_SCTR_HPCDIR_Msk               (0x01UL << USIC_CH_SCTR_HPCDIR_Pos)                     /*!< USIC_CH SCTR: HPCDIR Mask               */\r
+#define USIC_CH_SCTR_DOCFG_Pos                6                                                       /*!< USIC_CH SCTR: DOCFG Position            */\r
+#define USIC_CH_SCTR_DOCFG_Msk                (0x03UL << USIC_CH_SCTR_DOCFG_Pos)                      /*!< USIC_CH SCTR: DOCFG Mask                */\r
+#define USIC_CH_SCTR_TRM_Pos                  8                                                       /*!< USIC_CH SCTR: TRM Position              */\r
+#define USIC_CH_SCTR_TRM_Msk                  (0x03UL << USIC_CH_SCTR_TRM_Pos)                        /*!< USIC_CH SCTR: TRM Mask                  */\r
+#define USIC_CH_SCTR_FLE_Pos                  16                                                      /*!< USIC_CH SCTR: FLE Position              */\r
+#define USIC_CH_SCTR_FLE_Msk                  (0x3fUL << USIC_CH_SCTR_FLE_Pos)                        /*!< USIC_CH SCTR: FLE Mask                  */\r
+#define USIC_CH_SCTR_WLE_Pos                  24                                                      /*!< USIC_CH SCTR: WLE Position              */\r
+#define USIC_CH_SCTR_WLE_Msk                  (0x0fUL << USIC_CH_SCTR_WLE_Pos)                        /*!< USIC_CH SCTR: WLE Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_TCSR  -------------------------------- */\r
+#define USIC_CH_TCSR_WLEMD_Pos                0                                                       /*!< USIC_CH TCSR: WLEMD Position            */\r
+#define USIC_CH_TCSR_WLEMD_Msk                (0x01UL << USIC_CH_TCSR_WLEMD_Pos)                      /*!< USIC_CH TCSR: WLEMD Mask                */\r
+#define USIC_CH_TCSR_SELMD_Pos                1                                                       /*!< USIC_CH TCSR: SELMD Position            */\r
+#define USIC_CH_TCSR_SELMD_Msk                (0x01UL << USIC_CH_TCSR_SELMD_Pos)                      /*!< USIC_CH TCSR: SELMD Mask                */\r
+#define USIC_CH_TCSR_FLEMD_Pos                2                                                       /*!< USIC_CH TCSR: FLEMD Position            */\r
+#define USIC_CH_TCSR_FLEMD_Msk                (0x01UL << USIC_CH_TCSR_FLEMD_Pos)                      /*!< USIC_CH TCSR: FLEMD Mask                */\r
+#define USIC_CH_TCSR_WAMD_Pos                 3                                                       /*!< USIC_CH TCSR: WAMD Position             */\r
+#define USIC_CH_TCSR_WAMD_Msk                 (0x01UL << USIC_CH_TCSR_WAMD_Pos)                       /*!< USIC_CH TCSR: WAMD Mask                 */\r
+#define USIC_CH_TCSR_HPCMD_Pos                4                                                       /*!< USIC_CH TCSR: HPCMD Position            */\r
+#define USIC_CH_TCSR_HPCMD_Msk                (0x01UL << USIC_CH_TCSR_HPCMD_Pos)                      /*!< USIC_CH TCSR: HPCMD Mask                */\r
+#define USIC_CH_TCSR_SOF_Pos                  5                                                       /*!< USIC_CH TCSR: SOF Position              */\r
+#define USIC_CH_TCSR_SOF_Msk                  (0x01UL << USIC_CH_TCSR_SOF_Pos)                        /*!< USIC_CH TCSR: SOF Mask                  */\r
+#define USIC_CH_TCSR_EOF_Pos                  6                                                       /*!< USIC_CH TCSR: EOF Position              */\r
+#define USIC_CH_TCSR_EOF_Msk                  (0x01UL << USIC_CH_TCSR_EOF_Pos)                        /*!< USIC_CH TCSR: EOF Mask                  */\r
+#define USIC_CH_TCSR_TDV_Pos                  7                                                       /*!< USIC_CH TCSR: TDV Position              */\r
+#define USIC_CH_TCSR_TDV_Msk                  (0x01UL << USIC_CH_TCSR_TDV_Pos)                        /*!< USIC_CH TCSR: TDV Mask                  */\r
+#define USIC_CH_TCSR_TDSSM_Pos                8                                                       /*!< USIC_CH TCSR: TDSSM Position            */\r
+#define USIC_CH_TCSR_TDSSM_Msk                (0x01UL << USIC_CH_TCSR_TDSSM_Pos)                      /*!< USIC_CH TCSR: TDSSM Mask                */\r
+#define USIC_CH_TCSR_TDEN_Pos                 10                                                      /*!< USIC_CH TCSR: TDEN Position             */\r
+#define USIC_CH_TCSR_TDEN_Msk                 (0x03UL << USIC_CH_TCSR_TDEN_Pos)                       /*!< USIC_CH TCSR: TDEN Mask                 */\r
+#define USIC_CH_TCSR_TDVTR_Pos                12                                                      /*!< USIC_CH TCSR: TDVTR Position            */\r
+#define USIC_CH_TCSR_TDVTR_Msk                (0x01UL << USIC_CH_TCSR_TDVTR_Pos)                      /*!< USIC_CH TCSR: TDVTR Mask                */\r
+#define USIC_CH_TCSR_WA_Pos                   13                                                      /*!< USIC_CH TCSR: WA Position               */\r
+#define USIC_CH_TCSR_WA_Msk                   (0x01UL << USIC_CH_TCSR_WA_Pos)                         /*!< USIC_CH TCSR: WA Mask                   */\r
+#define USIC_CH_TCSR_TSOF_Pos                 24                                                      /*!< USIC_CH TCSR: TSOF Position             */\r
+#define USIC_CH_TCSR_TSOF_Msk                 (0x01UL << USIC_CH_TCSR_TSOF_Pos)                       /*!< USIC_CH TCSR: TSOF Mask                 */\r
+#define USIC_CH_TCSR_TV_Pos                   26                                                      /*!< USIC_CH TCSR: TV Position               */\r
+#define USIC_CH_TCSR_TV_Msk                   (0x01UL << USIC_CH_TCSR_TV_Pos)                         /*!< USIC_CH TCSR: TV Mask                   */\r
+#define USIC_CH_TCSR_TVC_Pos                  27                                                      /*!< USIC_CH TCSR: TVC Position              */\r
+#define USIC_CH_TCSR_TVC_Msk                  (0x01UL << USIC_CH_TCSR_TVC_Pos)                        /*!< USIC_CH TCSR: TVC Mask                  */\r
+#define USIC_CH_TCSR_TE_Pos                   28                                                      /*!< USIC_CH TCSR: TE Position               */\r
+#define USIC_CH_TCSR_TE_Msk                   (0x01UL << USIC_CH_TCSR_TE_Pos)                         /*!< USIC_CH TCSR: TE Mask                   */\r
+\r
+/* ---------------------------------  USIC_CH_PCR  -------------------------------- */\r
+#define USIC_CH_PCR_CTR0_Pos                  0                                                       /*!< USIC_CH PCR: CTR0 Position              */\r
+#define USIC_CH_PCR_CTR0_Msk                  (0x01UL << USIC_CH_PCR_CTR0_Pos)                        /*!< USIC_CH PCR: CTR0 Mask                  */\r
+#define USIC_CH_PCR_CTR1_Pos                  1                                                       /*!< USIC_CH PCR: CTR1 Position              */\r
+#define USIC_CH_PCR_CTR1_Msk                  (0x01UL << USIC_CH_PCR_CTR1_Pos)                        /*!< USIC_CH PCR: CTR1 Mask                  */\r
+#define USIC_CH_PCR_CTR2_Pos                  2                                                       /*!< USIC_CH PCR: CTR2 Position              */\r
+#define USIC_CH_PCR_CTR2_Msk                  (0x01UL << USIC_CH_PCR_CTR2_Pos)                        /*!< USIC_CH PCR: CTR2 Mask                  */\r
+#define USIC_CH_PCR_CTR3_Pos                  3                                                       /*!< USIC_CH PCR: CTR3 Position              */\r
+#define USIC_CH_PCR_CTR3_Msk                  (0x01UL << USIC_CH_PCR_CTR3_Pos)                        /*!< USIC_CH PCR: CTR3 Mask                  */\r
+#define USIC_CH_PCR_CTR4_Pos                  4                                                       /*!< USIC_CH PCR: CTR4 Position              */\r
+#define USIC_CH_PCR_CTR4_Msk                  (0x01UL << USIC_CH_PCR_CTR4_Pos)                        /*!< USIC_CH PCR: CTR4 Mask                  */\r
+#define USIC_CH_PCR_CTR5_Pos                  5                                                       /*!< USIC_CH PCR: CTR5 Position              */\r
+#define USIC_CH_PCR_CTR5_Msk                  (0x01UL << USIC_CH_PCR_CTR5_Pos)                        /*!< USIC_CH PCR: CTR5 Mask                  */\r
+#define USIC_CH_PCR_CTR6_Pos                  6                                                       /*!< USIC_CH PCR: CTR6 Position              */\r
+#define USIC_CH_PCR_CTR6_Msk                  (0x01UL << USIC_CH_PCR_CTR6_Pos)                        /*!< USIC_CH PCR: CTR6 Mask                  */\r
+#define USIC_CH_PCR_CTR7_Pos                  7                                                       /*!< USIC_CH PCR: CTR7 Position              */\r
+#define USIC_CH_PCR_CTR7_Msk                  (0x01UL << USIC_CH_PCR_CTR7_Pos)                        /*!< USIC_CH PCR: CTR7 Mask                  */\r
+#define USIC_CH_PCR_CTR8_Pos                  8                                                       /*!< USIC_CH PCR: CTR8 Position              */\r
+#define USIC_CH_PCR_CTR8_Msk                  (0x01UL << USIC_CH_PCR_CTR8_Pos)                        /*!< USIC_CH PCR: CTR8 Mask                  */\r
+#define USIC_CH_PCR_CTR9_Pos                  9                                                       /*!< USIC_CH PCR: CTR9 Position              */\r
+#define USIC_CH_PCR_CTR9_Msk                  (0x01UL << USIC_CH_PCR_CTR9_Pos)                        /*!< USIC_CH PCR: CTR9 Mask                  */\r
+#define USIC_CH_PCR_CTR10_Pos                 10                                                      /*!< USIC_CH PCR: CTR10 Position             */\r
+#define USIC_CH_PCR_CTR10_Msk                 (0x01UL << USIC_CH_PCR_CTR10_Pos)                       /*!< USIC_CH PCR: CTR10 Mask                 */\r
+#define USIC_CH_PCR_CTR11_Pos                 11                                                      /*!< USIC_CH PCR: CTR11 Position             */\r
+#define USIC_CH_PCR_CTR11_Msk                 (0x01UL << USIC_CH_PCR_CTR11_Pos)                       /*!< USIC_CH PCR: CTR11 Mask                 */\r
+#define USIC_CH_PCR_CTR12_Pos                 12                                                      /*!< USIC_CH PCR: CTR12 Position             */\r
+#define USIC_CH_PCR_CTR12_Msk                 (0x01UL << USIC_CH_PCR_CTR12_Pos)                       /*!< USIC_CH PCR: CTR12 Mask                 */\r
+#define USIC_CH_PCR_CTR13_Pos                 13                                                      /*!< USIC_CH PCR: CTR13 Position             */\r
+#define USIC_CH_PCR_CTR13_Msk                 (0x01UL << USIC_CH_PCR_CTR13_Pos)                       /*!< USIC_CH PCR: CTR13 Mask                 */\r
+#define USIC_CH_PCR_CTR14_Pos                 14                                                      /*!< USIC_CH PCR: CTR14 Position             */\r
+#define USIC_CH_PCR_CTR14_Msk                 (0x01UL << USIC_CH_PCR_CTR14_Pos)                       /*!< USIC_CH PCR: CTR14 Mask                 */\r
+#define USIC_CH_PCR_CTR15_Pos                 15                                                      /*!< USIC_CH PCR: CTR15 Position             */\r
+#define USIC_CH_PCR_CTR15_Msk                 (0x01UL << USIC_CH_PCR_CTR15_Pos)                       /*!< USIC_CH PCR: CTR15 Mask                 */\r
+#define USIC_CH_PCR_CTR16_Pos                 16                                                      /*!< USIC_CH PCR: CTR16 Position             */\r
+#define USIC_CH_PCR_CTR16_Msk                 (0x01UL << USIC_CH_PCR_CTR16_Pos)                       /*!< USIC_CH PCR: CTR16 Mask                 */\r
+#define USIC_CH_PCR_CTR17_Pos                 17                                                      /*!< USIC_CH PCR: CTR17 Position             */\r
+#define USIC_CH_PCR_CTR17_Msk                 (0x01UL << USIC_CH_PCR_CTR17_Pos)                       /*!< USIC_CH PCR: CTR17 Mask                 */\r
+#define USIC_CH_PCR_CTR18_Pos                 18                                                      /*!< USIC_CH PCR: CTR18 Position             */\r
+#define USIC_CH_PCR_CTR18_Msk                 (0x01UL << USIC_CH_PCR_CTR18_Pos)                       /*!< USIC_CH PCR: CTR18 Mask                 */\r
+#define USIC_CH_PCR_CTR19_Pos                 19                                                      /*!< USIC_CH PCR: CTR19 Position             */\r
+#define USIC_CH_PCR_CTR19_Msk                 (0x01UL << USIC_CH_PCR_CTR19_Pos)                       /*!< USIC_CH PCR: CTR19 Mask                 */\r
+#define USIC_CH_PCR_CTR20_Pos                 20                                                      /*!< USIC_CH PCR: CTR20 Position             */\r
+#define USIC_CH_PCR_CTR20_Msk                 (0x01UL << USIC_CH_PCR_CTR20_Pos)                       /*!< USIC_CH PCR: CTR20 Mask                 */\r
+#define USIC_CH_PCR_CTR21_Pos                 21                                                      /*!< USIC_CH PCR: CTR21 Position             */\r
+#define USIC_CH_PCR_CTR21_Msk                 (0x01UL << USIC_CH_PCR_CTR21_Pos)                       /*!< USIC_CH PCR: CTR21 Mask                 */\r
+#define USIC_CH_PCR_CTR22_Pos                 22                                                      /*!< USIC_CH PCR: CTR22 Position             */\r
+#define USIC_CH_PCR_CTR22_Msk                 (0x01UL << USIC_CH_PCR_CTR22_Pos)                       /*!< USIC_CH PCR: CTR22 Mask                 */\r
+#define USIC_CH_PCR_CTR23_Pos                 23                                                      /*!< USIC_CH PCR: CTR23 Position             */\r
+#define USIC_CH_PCR_CTR23_Msk                 (0x01UL << USIC_CH_PCR_CTR23_Pos)                       /*!< USIC_CH PCR: CTR23 Mask                 */\r
+#define USIC_CH_PCR_CTR24_Pos                 24                                                      /*!< USIC_CH PCR: CTR24 Position             */\r
+#define USIC_CH_PCR_CTR24_Msk                 (0x01UL << USIC_CH_PCR_CTR24_Pos)                       /*!< USIC_CH PCR: CTR24 Mask                 */\r
+#define USIC_CH_PCR_CTR25_Pos                 25                                                      /*!< USIC_CH PCR: CTR25 Position             */\r
+#define USIC_CH_PCR_CTR25_Msk                 (0x01UL << USIC_CH_PCR_CTR25_Pos)                       /*!< USIC_CH PCR: CTR25 Mask                 */\r
+#define USIC_CH_PCR_CTR26_Pos                 26                                                      /*!< USIC_CH PCR: CTR26 Position             */\r
+#define USIC_CH_PCR_CTR26_Msk                 (0x01UL << USIC_CH_PCR_CTR26_Pos)                       /*!< USIC_CH PCR: CTR26 Mask                 */\r
+#define USIC_CH_PCR_CTR27_Pos                 27                                                      /*!< USIC_CH PCR: CTR27 Position             */\r
+#define USIC_CH_PCR_CTR27_Msk                 (0x01UL << USIC_CH_PCR_CTR27_Pos)                       /*!< USIC_CH PCR: CTR27 Mask                 */\r
+#define USIC_CH_PCR_CTR28_Pos                 28                                                      /*!< USIC_CH PCR: CTR28 Position             */\r
+#define USIC_CH_PCR_CTR28_Msk                 (0x01UL << USIC_CH_PCR_CTR28_Pos)                       /*!< USIC_CH PCR: CTR28 Mask                 */\r
+#define USIC_CH_PCR_CTR29_Pos                 29                                                      /*!< USIC_CH PCR: CTR29 Position             */\r
+#define USIC_CH_PCR_CTR29_Msk                 (0x01UL << USIC_CH_PCR_CTR29_Pos)                       /*!< USIC_CH PCR: CTR29 Mask                 */\r
+#define USIC_CH_PCR_CTR30_Pos                 30                                                      /*!< USIC_CH PCR: CTR30 Position             */\r
+#define USIC_CH_PCR_CTR30_Msk                 (0x01UL << USIC_CH_PCR_CTR30_Pos)                       /*!< USIC_CH PCR: CTR30 Mask                 */\r
+#define USIC_CH_PCR_CTR31_Pos                 31                                                      /*!< USIC_CH PCR: CTR31 Position             */\r
+#define USIC_CH_PCR_CTR31_Msk                 (0x01UL << USIC_CH_PCR_CTR31_Pos)                       /*!< USIC_CH PCR: CTR31 Mask                 */\r
+\r
+/* -----------------------------  USIC_CH_PCR_ASCMode  ---------------------------- */\r
+#define USIC_CH_PCR_ASCMode_SMD_Pos           0                                                       /*!< USIC_CH PCR_ASCMode: SMD Position       */\r
+#define USIC_CH_PCR_ASCMode_SMD_Msk           (0x01UL << USIC_CH_PCR_ASCMode_SMD_Pos)                 /*!< USIC_CH PCR_ASCMode: SMD Mask           */\r
+#define USIC_CH_PCR_ASCMode_STPB_Pos          1                                                       /*!< USIC_CH PCR_ASCMode: STPB Position      */\r
+#define USIC_CH_PCR_ASCMode_STPB_Msk          (0x01UL << USIC_CH_PCR_ASCMode_STPB_Pos)                /*!< USIC_CH PCR_ASCMode: STPB Mask          */\r
+#define USIC_CH_PCR_ASCMode_IDM_Pos           2                                                       /*!< USIC_CH PCR_ASCMode: IDM Position       */\r
+#define USIC_CH_PCR_ASCMode_IDM_Msk           (0x01UL << USIC_CH_PCR_ASCMode_IDM_Pos)                 /*!< USIC_CH PCR_ASCMode: IDM Mask           */\r
+#define USIC_CH_PCR_ASCMode_SBIEN_Pos         3                                                       /*!< USIC_CH PCR_ASCMode: SBIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_SBIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_SBIEN_Pos)               /*!< USIC_CH PCR_ASCMode: SBIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_CDEN_Pos          4                                                       /*!< USIC_CH PCR_ASCMode: CDEN Position      */\r
+#define USIC_CH_PCR_ASCMode_CDEN_Msk          (0x01UL << USIC_CH_PCR_ASCMode_CDEN_Pos)                /*!< USIC_CH PCR_ASCMode: CDEN Mask          */\r
+#define USIC_CH_PCR_ASCMode_RNIEN_Pos         5                                                       /*!< USIC_CH PCR_ASCMode: RNIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_RNIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_RNIEN_Pos)               /*!< USIC_CH PCR_ASCMode: RNIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_FEIEN_Pos         6                                                       /*!< USIC_CH PCR_ASCMode: FEIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_FEIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_FEIEN_Pos)               /*!< USIC_CH PCR_ASCMode: FEIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_FFIEN_Pos         7                                                       /*!< USIC_CH PCR_ASCMode: FFIEN Position     */\r
+#define USIC_CH_PCR_ASCMode_FFIEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_FFIEN_Pos)               /*!< USIC_CH PCR_ASCMode: FFIEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_SP_Pos            8                                                       /*!< USIC_CH PCR_ASCMode: SP Position        */\r
+#define USIC_CH_PCR_ASCMode_SP_Msk            (0x1fUL << USIC_CH_PCR_ASCMode_SP_Pos)                  /*!< USIC_CH PCR_ASCMode: SP Mask            */\r
+#define USIC_CH_PCR_ASCMode_PL_Pos            13                                                      /*!< USIC_CH PCR_ASCMode: PL Position        */\r
+#define USIC_CH_PCR_ASCMode_PL_Msk            (0x07UL << USIC_CH_PCR_ASCMode_PL_Pos)                  /*!< USIC_CH PCR_ASCMode: PL Mask            */\r
+#define USIC_CH_PCR_ASCMode_RSTEN_Pos         16                                                      /*!< USIC_CH PCR_ASCMode: RSTEN Position     */\r
+#define USIC_CH_PCR_ASCMode_RSTEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_RSTEN_Pos)               /*!< USIC_CH PCR_ASCMode: RSTEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_TSTEN_Pos         17                                                      /*!< USIC_CH PCR_ASCMode: TSTEN Position     */\r
+#define USIC_CH_PCR_ASCMode_TSTEN_Msk         (0x01UL << USIC_CH_PCR_ASCMode_TSTEN_Pos)               /*!< USIC_CH PCR_ASCMode: TSTEN Mask         */\r
+#define USIC_CH_PCR_ASCMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_ASCMode: MCLK Position      */\r
+#define USIC_CH_PCR_ASCMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_ASCMode_MCLK_Pos)                /*!< USIC_CH PCR_ASCMode: MCLK Mask          */\r
+\r
+/* -----------------------------  USIC_CH_PCR_SSCMode  ---------------------------- */\r
+#define USIC_CH_PCR_SSCMode_MSLSEN_Pos        0                                                       /*!< USIC_CH PCR_SSCMode: MSLSEN Position    */\r
+#define USIC_CH_PCR_SSCMode_MSLSEN_Msk        (0x01UL << USIC_CH_PCR_SSCMode_MSLSEN_Pos)              /*!< USIC_CH PCR_SSCMode: MSLSEN Mask        */\r
+#define USIC_CH_PCR_SSCMode_SELCTR_Pos        1                                                       /*!< USIC_CH PCR_SSCMode: SELCTR Position    */\r
+#define USIC_CH_PCR_SSCMode_SELCTR_Msk        (0x01UL << USIC_CH_PCR_SSCMode_SELCTR_Pos)              /*!< USIC_CH PCR_SSCMode: SELCTR Mask        */\r
+#define USIC_CH_PCR_SSCMode_SELINV_Pos        2                                                       /*!< USIC_CH PCR_SSCMode: SELINV Position    */\r
+#define USIC_CH_PCR_SSCMode_SELINV_Msk        (0x01UL << USIC_CH_PCR_SSCMode_SELINV_Pos)              /*!< USIC_CH PCR_SSCMode: SELINV Mask        */\r
+#define USIC_CH_PCR_SSCMode_FEM_Pos           3                                                       /*!< USIC_CH PCR_SSCMode: FEM Position       */\r
+#define USIC_CH_PCR_SSCMode_FEM_Msk           (0x01UL << USIC_CH_PCR_SSCMode_FEM_Pos)                 /*!< USIC_CH PCR_SSCMode: FEM Mask           */\r
+#define USIC_CH_PCR_SSCMode_CTQSEL1_Pos       4                                                       /*!< USIC_CH PCR_SSCMode: CTQSEL1 Position   */\r
+#define USIC_CH_PCR_SSCMode_CTQSEL1_Msk       (0x03UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos)             /*!< USIC_CH PCR_SSCMode: CTQSEL1 Mask       */\r
+#define USIC_CH_PCR_SSCMode_PCTQ1_Pos         6                                                       /*!< USIC_CH PCR_SSCMode: PCTQ1 Position     */\r
+#define USIC_CH_PCR_SSCMode_PCTQ1_Msk         (0x03UL << USIC_CH_PCR_SSCMode_PCTQ1_Pos)               /*!< USIC_CH PCR_SSCMode: PCTQ1 Mask         */\r
+#define USIC_CH_PCR_SSCMode_DCTQ1_Pos         8                                                       /*!< USIC_CH PCR_SSCMode: DCTQ1 Position     */\r
+#define USIC_CH_PCR_SSCMode_DCTQ1_Msk         (0x1fUL << USIC_CH_PCR_SSCMode_DCTQ1_Pos)               /*!< USIC_CH PCR_SSCMode: DCTQ1 Mask         */\r
+#define USIC_CH_PCR_SSCMode_PARIEN_Pos        13                                                      /*!< USIC_CH PCR_SSCMode: PARIEN Position    */\r
+#define USIC_CH_PCR_SSCMode_PARIEN_Msk        (0x01UL << USIC_CH_PCR_SSCMode_PARIEN_Pos)              /*!< USIC_CH PCR_SSCMode: PARIEN Mask        */\r
+#define USIC_CH_PCR_SSCMode_MSLSIEN_Pos       14                                                      /*!< USIC_CH PCR_SSCMode: MSLSIEN Position   */\r
+#define USIC_CH_PCR_SSCMode_MSLSIEN_Msk       (0x01UL << USIC_CH_PCR_SSCMode_MSLSIEN_Pos)             /*!< USIC_CH PCR_SSCMode: MSLSIEN Mask       */\r
+#define USIC_CH_PCR_SSCMode_DX2TIEN_Pos       15                                                      /*!< USIC_CH PCR_SSCMode: DX2TIEN Position   */\r
+#define USIC_CH_PCR_SSCMode_DX2TIEN_Msk       (0x01UL << USIC_CH_PCR_SSCMode_DX2TIEN_Pos)             /*!< USIC_CH PCR_SSCMode: DX2TIEN Mask       */\r
+#define USIC_CH_PCR_SSCMode_SELO_Pos          16                                                      /*!< USIC_CH PCR_SSCMode: SELO Position      */\r
+#define USIC_CH_PCR_SSCMode_SELO_Msk          (0x000000ffUL << USIC_CH_PCR_SSCMode_SELO_Pos)          /*!< USIC_CH PCR_SSCMode: SELO Mask          */\r
+#define USIC_CH_PCR_SSCMode_TIWEN_Pos         24                                                      /*!< USIC_CH PCR_SSCMode: TIWEN Position     */\r
+#define USIC_CH_PCR_SSCMode_TIWEN_Msk         (0x01UL << USIC_CH_PCR_SSCMode_TIWEN_Pos)               /*!< USIC_CH PCR_SSCMode: TIWEN Mask         */\r
+#define USIC_CH_PCR_SSCMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_SSCMode: MCLK Position      */\r
+#define USIC_CH_PCR_SSCMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_SSCMode_MCLK_Pos)                /*!< USIC_CH PCR_SSCMode: MCLK Mask          */\r
+\r
+/* -----------------------------  USIC_CH_PCR_IICMode  ---------------------------- */\r
+#define USIC_CH_PCR_IICMode_SLAD_Pos          0                                                       /*!< USIC_CH PCR_IICMode: SLAD Position      */\r
+#define USIC_CH_PCR_IICMode_SLAD_Msk          (0x0000ffffUL << USIC_CH_PCR_IICMode_SLAD_Pos)          /*!< USIC_CH PCR_IICMode: SLAD Mask          */\r
+#define USIC_CH_PCR_IICMode_ACK00_Pos         16                                                      /*!< USIC_CH PCR_IICMode: ACK00 Position     */\r
+#define USIC_CH_PCR_IICMode_ACK00_Msk         (0x01UL << USIC_CH_PCR_IICMode_ACK00_Pos)               /*!< USIC_CH PCR_IICMode: ACK00 Mask         */\r
+#define USIC_CH_PCR_IICMode_STIM_Pos          17                                                      /*!< USIC_CH PCR_IICMode: STIM Position      */\r
+#define USIC_CH_PCR_IICMode_STIM_Msk          (0x01UL << USIC_CH_PCR_IICMode_STIM_Pos)                /*!< USIC_CH PCR_IICMode: STIM Mask          */\r
+#define USIC_CH_PCR_IICMode_SCRIEN_Pos        18                                                      /*!< USIC_CH PCR_IICMode: SCRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_SCRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_SCRIEN_Pos)              /*!< USIC_CH PCR_IICMode: SCRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_RSCRIEN_Pos       19                                                      /*!< USIC_CH PCR_IICMode: RSCRIEN Position   */\r
+#define USIC_CH_PCR_IICMode_RSCRIEN_Msk       (0x01UL << USIC_CH_PCR_IICMode_RSCRIEN_Pos)             /*!< USIC_CH PCR_IICMode: RSCRIEN Mask       */\r
+#define USIC_CH_PCR_IICMode_PCRIEN_Pos        20                                                      /*!< USIC_CH PCR_IICMode: PCRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_PCRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_PCRIEN_Pos)              /*!< USIC_CH PCR_IICMode: PCRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_NACKIEN_Pos       21                                                      /*!< USIC_CH PCR_IICMode: NACKIEN Position   */\r
+#define USIC_CH_PCR_IICMode_NACKIEN_Msk       (0x01UL << USIC_CH_PCR_IICMode_NACKIEN_Pos)             /*!< USIC_CH PCR_IICMode: NACKIEN Mask       */\r
+#define USIC_CH_PCR_IICMode_ARLIEN_Pos        22                                                      /*!< USIC_CH PCR_IICMode: ARLIEN Position    */\r
+#define USIC_CH_PCR_IICMode_ARLIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_ARLIEN_Pos)              /*!< USIC_CH PCR_IICMode: ARLIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_SRRIEN_Pos        23                                                      /*!< USIC_CH PCR_IICMode: SRRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_SRRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_SRRIEN_Pos)              /*!< USIC_CH PCR_IICMode: SRRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_ERRIEN_Pos        24                                                      /*!< USIC_CH PCR_IICMode: ERRIEN Position    */\r
+#define USIC_CH_PCR_IICMode_ERRIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_ERRIEN_Pos)              /*!< USIC_CH PCR_IICMode: ERRIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_SACKDIS_Pos       25                                                      /*!< USIC_CH PCR_IICMode: SACKDIS Position   */\r
+#define USIC_CH_PCR_IICMode_SACKDIS_Msk       (0x01UL << USIC_CH_PCR_IICMode_SACKDIS_Pos)             /*!< USIC_CH PCR_IICMode: SACKDIS Mask       */\r
+#define USIC_CH_PCR_IICMode_HDEL_Pos          26                                                      /*!< USIC_CH PCR_IICMode: HDEL Position      */\r
+#define USIC_CH_PCR_IICMode_HDEL_Msk          (0x0fUL << USIC_CH_PCR_IICMode_HDEL_Pos)                /*!< USIC_CH PCR_IICMode: HDEL Mask          */\r
+#define USIC_CH_PCR_IICMode_ACKIEN_Pos        30                                                      /*!< USIC_CH PCR_IICMode: ACKIEN Position    */\r
+#define USIC_CH_PCR_IICMode_ACKIEN_Msk        (0x01UL << USIC_CH_PCR_IICMode_ACKIEN_Pos)              /*!< USIC_CH PCR_IICMode: ACKIEN Mask        */\r
+#define USIC_CH_PCR_IICMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_IICMode: MCLK Position      */\r
+#define USIC_CH_PCR_IICMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_IICMode_MCLK_Pos)                /*!< USIC_CH PCR_IICMode: MCLK Mask          */\r
+\r
+/* -----------------------------  USIC_CH_PCR_IISMode  ---------------------------- */\r
+#define USIC_CH_PCR_IISMode_WAGEN_Pos         0                                                       /*!< USIC_CH PCR_IISMode: WAGEN Position     */\r
+#define USIC_CH_PCR_IISMode_WAGEN_Msk         (0x01UL << USIC_CH_PCR_IISMode_WAGEN_Pos)               /*!< USIC_CH PCR_IISMode: WAGEN Mask         */\r
+#define USIC_CH_PCR_IISMode_DTEN_Pos          1                                                       /*!< USIC_CH PCR_IISMode: DTEN Position      */\r
+#define USIC_CH_PCR_IISMode_DTEN_Msk          (0x01UL << USIC_CH_PCR_IISMode_DTEN_Pos)                /*!< USIC_CH PCR_IISMode: DTEN Mask          */\r
+#define USIC_CH_PCR_IISMode_SELINV_Pos        2                                                       /*!< USIC_CH PCR_IISMode: SELINV Position    */\r
+#define USIC_CH_PCR_IISMode_SELINV_Msk        (0x01UL << USIC_CH_PCR_IISMode_SELINV_Pos)              /*!< USIC_CH PCR_IISMode: SELINV Mask        */\r
+#define USIC_CH_PCR_IISMode_WAFEIEN_Pos       4                                                       /*!< USIC_CH PCR_IISMode: WAFEIEN Position   */\r
+#define USIC_CH_PCR_IISMode_WAFEIEN_Msk       (0x01UL << USIC_CH_PCR_IISMode_WAFEIEN_Pos)             /*!< USIC_CH PCR_IISMode: WAFEIEN Mask       */\r
+#define USIC_CH_PCR_IISMode_WAREIEN_Pos       5                                                       /*!< USIC_CH PCR_IISMode: WAREIEN Position   */\r
+#define USIC_CH_PCR_IISMode_WAREIEN_Msk       (0x01UL << USIC_CH_PCR_IISMode_WAREIEN_Pos)             /*!< USIC_CH PCR_IISMode: WAREIEN Mask       */\r
+#define USIC_CH_PCR_IISMode_ENDIEN_Pos        6                                                       /*!< USIC_CH PCR_IISMode: ENDIEN Position    */\r
+#define USIC_CH_PCR_IISMode_ENDIEN_Msk        (0x01UL << USIC_CH_PCR_IISMode_ENDIEN_Pos)              /*!< USIC_CH PCR_IISMode: ENDIEN Mask        */\r
+#define USIC_CH_PCR_IISMode_DX2TIEN_Pos       15                                                      /*!< USIC_CH PCR_IISMode: DX2TIEN Position   */\r
+#define USIC_CH_PCR_IISMode_DX2TIEN_Msk       (0x01UL << USIC_CH_PCR_IISMode_DX2TIEN_Pos)             /*!< USIC_CH PCR_IISMode: DX2TIEN Mask       */\r
+#define USIC_CH_PCR_IISMode_TDEL_Pos          16                                                      /*!< USIC_CH PCR_IISMode: TDEL Position      */\r
+#define USIC_CH_PCR_IISMode_TDEL_Msk          (0x3fUL << USIC_CH_PCR_IISMode_TDEL_Pos)                /*!< USIC_CH PCR_IISMode: TDEL Mask          */\r
+#define USIC_CH_PCR_IISMode_MCLK_Pos          31                                                      /*!< USIC_CH PCR_IISMode: MCLK Position      */\r
+#define USIC_CH_PCR_IISMode_MCLK_Msk          (0x01UL << USIC_CH_PCR_IISMode_MCLK_Pos)                /*!< USIC_CH PCR_IISMode: MCLK Mask          */\r
+\r
+/* ---------------------------------  USIC_CH_CCR  -------------------------------- */\r
+#define USIC_CH_CCR_MODE_Pos                  0                                                       /*!< USIC_CH CCR: MODE Position              */\r
+#define USIC_CH_CCR_MODE_Msk                  (0x0fUL << USIC_CH_CCR_MODE_Pos)                        /*!< USIC_CH CCR: MODE Mask                  */\r
+#define USIC_CH_CCR_HPCEN_Pos                 6                                                       /*!< USIC_CH CCR: HPCEN Position             */\r
+#define USIC_CH_CCR_HPCEN_Msk                 (0x03UL << USIC_CH_CCR_HPCEN_Pos)                       /*!< USIC_CH CCR: HPCEN Mask                 */\r
+#define USIC_CH_CCR_PM_Pos                    8                                                       /*!< USIC_CH CCR: PM Position                */\r
+#define USIC_CH_CCR_PM_Msk                    (0x03UL << USIC_CH_CCR_PM_Pos)                          /*!< USIC_CH CCR: PM Mask                    */\r
+#define USIC_CH_CCR_RSIEN_Pos                 10                                                      /*!< USIC_CH CCR: RSIEN Position             */\r
+#define USIC_CH_CCR_RSIEN_Msk                 (0x01UL << USIC_CH_CCR_RSIEN_Pos)                       /*!< USIC_CH CCR: RSIEN Mask                 */\r
+#define USIC_CH_CCR_DLIEN_Pos                 11                                                      /*!< USIC_CH CCR: DLIEN Position             */\r
+#define USIC_CH_CCR_DLIEN_Msk                 (0x01UL << USIC_CH_CCR_DLIEN_Pos)                       /*!< USIC_CH CCR: DLIEN Mask                 */\r
+#define USIC_CH_CCR_TSIEN_Pos                 12                                                      /*!< USIC_CH CCR: TSIEN Position             */\r
+#define USIC_CH_CCR_TSIEN_Msk                 (0x01UL << USIC_CH_CCR_TSIEN_Pos)                       /*!< USIC_CH CCR: TSIEN Mask                 */\r
+#define USIC_CH_CCR_TBIEN_Pos                 13                                                      /*!< USIC_CH CCR: TBIEN Position             */\r
+#define USIC_CH_CCR_TBIEN_Msk                 (0x01UL << USIC_CH_CCR_TBIEN_Pos)                       /*!< USIC_CH CCR: TBIEN Mask                 */\r
+#define USIC_CH_CCR_RIEN_Pos                  14                                                      /*!< USIC_CH CCR: RIEN Position              */\r
+#define USIC_CH_CCR_RIEN_Msk                  (0x01UL << USIC_CH_CCR_RIEN_Pos)                        /*!< USIC_CH CCR: RIEN Mask                  */\r
+#define USIC_CH_CCR_AIEN_Pos                  15                                                      /*!< USIC_CH CCR: AIEN Position              */\r
+#define USIC_CH_CCR_AIEN_Msk                  (0x01UL << USIC_CH_CCR_AIEN_Pos)                        /*!< USIC_CH CCR: AIEN Mask                  */\r
+#define USIC_CH_CCR_BRGIEN_Pos                16                                                      /*!< USIC_CH CCR: BRGIEN Position            */\r
+#define USIC_CH_CCR_BRGIEN_Msk                (0x01UL << USIC_CH_CCR_BRGIEN_Pos)                      /*!< USIC_CH CCR: BRGIEN Mask                */\r
+\r
+/* --------------------------------  USIC_CH_CMTR  -------------------------------- */\r
+#define USIC_CH_CMTR_CTV_Pos                  0                                                       /*!< USIC_CH CMTR: CTV Position              */\r
+#define USIC_CH_CMTR_CTV_Msk                  (0x000003ffUL << USIC_CH_CMTR_CTV_Pos)                  /*!< USIC_CH CMTR: CTV Mask                  */\r
+\r
+/* ---------------------------------  USIC_CH_PSR  -------------------------------- */\r
+#define USIC_CH_PSR_ST0_Pos                   0                                                       /*!< USIC_CH PSR: ST0 Position               */\r
+#define USIC_CH_PSR_ST0_Msk                   (0x01UL << USIC_CH_PSR_ST0_Pos)                         /*!< USIC_CH PSR: ST0 Mask                   */\r
+#define USIC_CH_PSR_ST1_Pos                   1                                                       /*!< USIC_CH PSR: ST1 Position               */\r
+#define USIC_CH_PSR_ST1_Msk                   (0x01UL << USIC_CH_PSR_ST1_Pos)                         /*!< USIC_CH PSR: ST1 Mask                   */\r
+#define USIC_CH_PSR_ST2_Pos                   2                                                       /*!< USIC_CH PSR: ST2 Position               */\r
+#define USIC_CH_PSR_ST2_Msk                   (0x01UL << USIC_CH_PSR_ST2_Pos)                         /*!< USIC_CH PSR: ST2 Mask                   */\r
+#define USIC_CH_PSR_ST3_Pos                   3                                                       /*!< USIC_CH PSR: ST3 Position               */\r
+#define USIC_CH_PSR_ST3_Msk                   (0x01UL << USIC_CH_PSR_ST3_Pos)                         /*!< USIC_CH PSR: ST3 Mask                   */\r
+#define USIC_CH_PSR_ST4_Pos                   4                                                       /*!< USIC_CH PSR: ST4 Position               */\r
+#define USIC_CH_PSR_ST4_Msk                   (0x01UL << USIC_CH_PSR_ST4_Pos)                         /*!< USIC_CH PSR: ST4 Mask                   */\r
+#define USIC_CH_PSR_ST5_Pos                   5                                                       /*!< USIC_CH PSR: ST5 Position               */\r
+#define USIC_CH_PSR_ST5_Msk                   (0x01UL << USIC_CH_PSR_ST5_Pos)                         /*!< USIC_CH PSR: ST5 Mask                   */\r
+#define USIC_CH_PSR_ST6_Pos                   6                                                       /*!< USIC_CH PSR: ST6 Position               */\r
+#define USIC_CH_PSR_ST6_Msk                   (0x01UL << USIC_CH_PSR_ST6_Pos)                         /*!< USIC_CH PSR: ST6 Mask                   */\r
+#define USIC_CH_PSR_ST7_Pos                   7                                                       /*!< USIC_CH PSR: ST7 Position               */\r
+#define USIC_CH_PSR_ST7_Msk                   (0x01UL << USIC_CH_PSR_ST7_Pos)                         /*!< USIC_CH PSR: ST7 Mask                   */\r
+#define USIC_CH_PSR_ST8_Pos                   8                                                       /*!< USIC_CH PSR: ST8 Position               */\r
+#define USIC_CH_PSR_ST8_Msk                   (0x01UL << USIC_CH_PSR_ST8_Pos)                         /*!< USIC_CH PSR: ST8 Mask                   */\r
+#define USIC_CH_PSR_ST9_Pos                   9                                                       /*!< USIC_CH PSR: ST9 Position               */\r
+#define USIC_CH_PSR_ST9_Msk                   (0x01UL << USIC_CH_PSR_ST9_Pos)                         /*!< USIC_CH PSR: ST9 Mask                   */\r
+#define USIC_CH_PSR_RSIF_Pos                  10                                                      /*!< USIC_CH PSR: RSIF Position              */\r
+#define USIC_CH_PSR_RSIF_Msk                  (0x01UL << USIC_CH_PSR_RSIF_Pos)                        /*!< USIC_CH PSR: RSIF Mask                  */\r
+#define USIC_CH_PSR_DLIF_Pos                  11                                                      /*!< USIC_CH PSR: DLIF Position              */\r
+#define USIC_CH_PSR_DLIF_Msk                  (0x01UL << USIC_CH_PSR_DLIF_Pos)                        /*!< USIC_CH PSR: DLIF Mask                  */\r
+#define USIC_CH_PSR_TSIF_Pos                  12                                                      /*!< USIC_CH PSR: TSIF Position              */\r
+#define USIC_CH_PSR_TSIF_Msk                  (0x01UL << USIC_CH_PSR_TSIF_Pos)                        /*!< USIC_CH PSR: TSIF Mask                  */\r
+#define USIC_CH_PSR_TBIF_Pos                  13                                                      /*!< USIC_CH PSR: TBIF Position              */\r
+#define USIC_CH_PSR_TBIF_Msk                  (0x01UL << USIC_CH_PSR_TBIF_Pos)                        /*!< USIC_CH PSR: TBIF Mask                  */\r
+#define USIC_CH_PSR_RIF_Pos                   14                                                      /*!< USIC_CH PSR: RIF Position               */\r
+#define USIC_CH_PSR_RIF_Msk                   (0x01UL << USIC_CH_PSR_RIF_Pos)                         /*!< USIC_CH PSR: RIF Mask                   */\r
+#define USIC_CH_PSR_AIF_Pos                   15                                                      /*!< USIC_CH PSR: AIF Position               */\r
+#define USIC_CH_PSR_AIF_Msk                   (0x01UL << USIC_CH_PSR_AIF_Pos)                         /*!< USIC_CH PSR: AIF Mask                   */\r
+#define USIC_CH_PSR_BRGIF_Pos                 16                                                      /*!< USIC_CH PSR: BRGIF Position             */\r
+#define USIC_CH_PSR_BRGIF_Msk                 (0x01UL << USIC_CH_PSR_BRGIF_Pos)                       /*!< USIC_CH PSR: BRGIF Mask                 */\r
+\r
+/* -----------------------------  USIC_CH_PSR_ASCMode  ---------------------------- */\r
+#define USIC_CH_PSR_ASCMode_TXIDLE_Pos        0                                                       /*!< USIC_CH PSR_ASCMode: TXIDLE Position    */\r
+#define USIC_CH_PSR_ASCMode_TXIDLE_Msk        (0x01UL << USIC_CH_PSR_ASCMode_TXIDLE_Pos)              /*!< USIC_CH PSR_ASCMode: TXIDLE Mask        */\r
+#define USIC_CH_PSR_ASCMode_RXIDLE_Pos        1                                                       /*!< USIC_CH PSR_ASCMode: RXIDLE Position    */\r
+#define USIC_CH_PSR_ASCMode_RXIDLE_Msk        (0x01UL << USIC_CH_PSR_ASCMode_RXIDLE_Pos)              /*!< USIC_CH PSR_ASCMode: RXIDLE Mask        */\r
+#define USIC_CH_PSR_ASCMode_SBD_Pos           2                                                       /*!< USIC_CH PSR_ASCMode: SBD Position       */\r
+#define USIC_CH_PSR_ASCMode_SBD_Msk           (0x01UL << USIC_CH_PSR_ASCMode_SBD_Pos)                 /*!< USIC_CH PSR_ASCMode: SBD Mask           */\r
+#define USIC_CH_PSR_ASCMode_COL_Pos           3                                                       /*!< USIC_CH PSR_ASCMode: COL Position       */\r
+#define USIC_CH_PSR_ASCMode_COL_Msk           (0x01UL << USIC_CH_PSR_ASCMode_COL_Pos)                 /*!< USIC_CH PSR_ASCMode: COL Mask           */\r
+#define USIC_CH_PSR_ASCMode_RNS_Pos           4                                                       /*!< USIC_CH PSR_ASCMode: RNS Position       */\r
+#define USIC_CH_PSR_ASCMode_RNS_Msk           (0x01UL << USIC_CH_PSR_ASCMode_RNS_Pos)                 /*!< USIC_CH PSR_ASCMode: RNS Mask           */\r
+#define USIC_CH_PSR_ASCMode_FER0_Pos          5                                                       /*!< USIC_CH PSR_ASCMode: FER0 Position      */\r
+#define USIC_CH_PSR_ASCMode_FER0_Msk          (0x01UL << USIC_CH_PSR_ASCMode_FER0_Pos)                /*!< USIC_CH PSR_ASCMode: FER0 Mask          */\r
+#define USIC_CH_PSR_ASCMode_FER1_Pos          6                                                       /*!< USIC_CH PSR_ASCMode: FER1 Position      */\r
+#define USIC_CH_PSR_ASCMode_FER1_Msk          (0x01UL << USIC_CH_PSR_ASCMode_FER1_Pos)                /*!< USIC_CH PSR_ASCMode: FER1 Mask          */\r
+#define USIC_CH_PSR_ASCMode_RFF_Pos           7                                                       /*!< USIC_CH PSR_ASCMode: RFF Position       */\r
+#define USIC_CH_PSR_ASCMode_RFF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_RFF_Pos)                 /*!< USIC_CH PSR_ASCMode: RFF Mask           */\r
+#define USIC_CH_PSR_ASCMode_TFF_Pos           8                                                       /*!< USIC_CH PSR_ASCMode: TFF Position       */\r
+#define USIC_CH_PSR_ASCMode_TFF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_TFF_Pos)                 /*!< USIC_CH PSR_ASCMode: TFF Mask           */\r
+#define USIC_CH_PSR_ASCMode_BUSY_Pos          9                                                       /*!< USIC_CH PSR_ASCMode: BUSY Position      */\r
+#define USIC_CH_PSR_ASCMode_BUSY_Msk          (0x01UL << USIC_CH_PSR_ASCMode_BUSY_Pos)                /*!< USIC_CH PSR_ASCMode: BUSY Mask          */\r
+#define USIC_CH_PSR_ASCMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_ASCMode: RSIF Position      */\r
+#define USIC_CH_PSR_ASCMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_RSIF_Pos)                /*!< USIC_CH PSR_ASCMode: RSIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_ASCMode: DLIF Position      */\r
+#define USIC_CH_PSR_ASCMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_DLIF_Pos)                /*!< USIC_CH PSR_ASCMode: DLIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_ASCMode: TSIF Position      */\r
+#define USIC_CH_PSR_ASCMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_TSIF_Pos)                /*!< USIC_CH PSR_ASCMode: TSIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_ASCMode: TBIF Position      */\r
+#define USIC_CH_PSR_ASCMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_ASCMode_TBIF_Pos)                /*!< USIC_CH PSR_ASCMode: TBIF Mask          */\r
+#define USIC_CH_PSR_ASCMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_ASCMode: RIF Position       */\r
+#define USIC_CH_PSR_ASCMode_RIF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_RIF_Pos)                 /*!< USIC_CH PSR_ASCMode: RIF Mask           */\r
+#define USIC_CH_PSR_ASCMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_ASCMode: AIF Position       */\r
+#define USIC_CH_PSR_ASCMode_AIF_Msk           (0x01UL << USIC_CH_PSR_ASCMode_AIF_Pos)                 /*!< USIC_CH PSR_ASCMode: AIF Mask           */\r
+#define USIC_CH_PSR_ASCMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_ASCMode: BRGIF Position     */\r
+#define USIC_CH_PSR_ASCMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_ASCMode_BRGIF_Pos)               /*!< USIC_CH PSR_ASCMode: BRGIF Mask         */\r
+\r
+/* -----------------------------  USIC_CH_PSR_SSCMode  ---------------------------- */\r
+#define USIC_CH_PSR_SSCMode_MSLS_Pos          0                                                       /*!< USIC_CH PSR_SSCMode: MSLS Position      */\r
+#define USIC_CH_PSR_SSCMode_MSLS_Msk          (0x01UL << USIC_CH_PSR_SSCMode_MSLS_Pos)                /*!< USIC_CH PSR_SSCMode: MSLS Mask          */\r
+#define USIC_CH_PSR_SSCMode_DX2S_Pos          1                                                       /*!< USIC_CH PSR_SSCMode: DX2S Position      */\r
+#define USIC_CH_PSR_SSCMode_DX2S_Msk          (0x01UL << USIC_CH_PSR_SSCMode_DX2S_Pos)                /*!< USIC_CH PSR_SSCMode: DX2S Mask          */\r
+#define USIC_CH_PSR_SSCMode_MSLSEV_Pos        2                                                       /*!< USIC_CH PSR_SSCMode: MSLSEV Position    */\r
+#define USIC_CH_PSR_SSCMode_MSLSEV_Msk        (0x01UL << USIC_CH_PSR_SSCMode_MSLSEV_Pos)              /*!< USIC_CH PSR_SSCMode: MSLSEV Mask        */\r
+#define USIC_CH_PSR_SSCMode_DX2TEV_Pos        3                                                       /*!< USIC_CH PSR_SSCMode: DX2TEV Position    */\r
+#define USIC_CH_PSR_SSCMode_DX2TEV_Msk        (0x01UL << USIC_CH_PSR_SSCMode_DX2TEV_Pos)              /*!< USIC_CH PSR_SSCMode: DX2TEV Mask        */\r
+#define USIC_CH_PSR_SSCMode_PARERR_Pos        4                                                       /*!< USIC_CH PSR_SSCMode: PARERR Position    */\r
+#define USIC_CH_PSR_SSCMode_PARERR_Msk        (0x01UL << USIC_CH_PSR_SSCMode_PARERR_Pos)              /*!< USIC_CH PSR_SSCMode: PARERR Mask        */\r
+#define USIC_CH_PSR_SSCMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_SSCMode: RSIF Position      */\r
+#define USIC_CH_PSR_SSCMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_RSIF_Pos)                /*!< USIC_CH PSR_SSCMode: RSIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_SSCMode: DLIF Position      */\r
+#define USIC_CH_PSR_SSCMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_DLIF_Pos)                /*!< USIC_CH PSR_SSCMode: DLIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_SSCMode: TSIF Position      */\r
+#define USIC_CH_PSR_SSCMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_TSIF_Pos)                /*!< USIC_CH PSR_SSCMode: TSIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_SSCMode: TBIF Position      */\r
+#define USIC_CH_PSR_SSCMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_SSCMode_TBIF_Pos)                /*!< USIC_CH PSR_SSCMode: TBIF Mask          */\r
+#define USIC_CH_PSR_SSCMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_SSCMode: RIF Position       */\r
+#define USIC_CH_PSR_SSCMode_RIF_Msk           (0x01UL << USIC_CH_PSR_SSCMode_RIF_Pos)                 /*!< USIC_CH PSR_SSCMode: RIF Mask           */\r
+#define USIC_CH_PSR_SSCMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_SSCMode: AIF Position       */\r
+#define USIC_CH_PSR_SSCMode_AIF_Msk           (0x01UL << USIC_CH_PSR_SSCMode_AIF_Pos)                 /*!< USIC_CH PSR_SSCMode: AIF Mask           */\r
+#define USIC_CH_PSR_SSCMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_SSCMode: BRGIF Position     */\r
+#define USIC_CH_PSR_SSCMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_SSCMode_BRGIF_Pos)               /*!< USIC_CH PSR_SSCMode: BRGIF Mask         */\r
+\r
+/* -----------------------------  USIC_CH_PSR_IICMode  ---------------------------- */\r
+#define USIC_CH_PSR_IICMode_SLSEL_Pos         0                                                       /*!< USIC_CH PSR_IICMode: SLSEL Position     */\r
+#define USIC_CH_PSR_IICMode_SLSEL_Msk         (0x01UL << USIC_CH_PSR_IICMode_SLSEL_Pos)               /*!< USIC_CH PSR_IICMode: SLSEL Mask         */\r
+#define USIC_CH_PSR_IICMode_WTDF_Pos          1                                                       /*!< USIC_CH PSR_IICMode: WTDF Position      */\r
+#define USIC_CH_PSR_IICMode_WTDF_Msk          (0x01UL << USIC_CH_PSR_IICMode_WTDF_Pos)                /*!< USIC_CH PSR_IICMode: WTDF Mask          */\r
+#define USIC_CH_PSR_IICMode_SCR_Pos           2                                                       /*!< USIC_CH PSR_IICMode: SCR Position       */\r
+#define USIC_CH_PSR_IICMode_SCR_Msk           (0x01UL << USIC_CH_PSR_IICMode_SCR_Pos)                 /*!< USIC_CH PSR_IICMode: SCR Mask           */\r
+#define USIC_CH_PSR_IICMode_RSCR_Pos          3                                                       /*!< USIC_CH PSR_IICMode: RSCR Position      */\r
+#define USIC_CH_PSR_IICMode_RSCR_Msk          (0x01UL << USIC_CH_PSR_IICMode_RSCR_Pos)                /*!< USIC_CH PSR_IICMode: RSCR Mask          */\r
+#define USIC_CH_PSR_IICMode_PCR_Pos           4                                                       /*!< USIC_CH PSR_IICMode: PCR Position       */\r
+#define USIC_CH_PSR_IICMode_PCR_Msk           (0x01UL << USIC_CH_PSR_IICMode_PCR_Pos)                 /*!< USIC_CH PSR_IICMode: PCR Mask           */\r
+#define USIC_CH_PSR_IICMode_NACK_Pos          5                                                       /*!< USIC_CH PSR_IICMode: NACK Position      */\r
+#define USIC_CH_PSR_IICMode_NACK_Msk          (0x01UL << USIC_CH_PSR_IICMode_NACK_Pos)                /*!< USIC_CH PSR_IICMode: NACK Mask          */\r
+#define USIC_CH_PSR_IICMode_ARL_Pos           6                                                       /*!< USIC_CH PSR_IICMode: ARL Position       */\r
+#define USIC_CH_PSR_IICMode_ARL_Msk           (0x01UL << USIC_CH_PSR_IICMode_ARL_Pos)                 /*!< USIC_CH PSR_IICMode: ARL Mask           */\r
+#define USIC_CH_PSR_IICMode_SRR_Pos           7                                                       /*!< USIC_CH PSR_IICMode: SRR Position       */\r
+#define USIC_CH_PSR_IICMode_SRR_Msk           (0x01UL << USIC_CH_PSR_IICMode_SRR_Pos)                 /*!< USIC_CH PSR_IICMode: SRR Mask           */\r
+#define USIC_CH_PSR_IICMode_ERR_Pos           8                                                       /*!< USIC_CH PSR_IICMode: ERR Position       */\r
+#define USIC_CH_PSR_IICMode_ERR_Msk           (0x01UL << USIC_CH_PSR_IICMode_ERR_Pos)                 /*!< USIC_CH PSR_IICMode: ERR Mask           */\r
+#define USIC_CH_PSR_IICMode_ACK_Pos           9                                                       /*!< USIC_CH PSR_IICMode: ACK Position       */\r
+#define USIC_CH_PSR_IICMode_ACK_Msk           (0x01UL << USIC_CH_PSR_IICMode_ACK_Pos)                 /*!< USIC_CH PSR_IICMode: ACK Mask           */\r
+#define USIC_CH_PSR_IICMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_IICMode: RSIF Position      */\r
+#define USIC_CH_PSR_IICMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_RSIF_Pos)                /*!< USIC_CH PSR_IICMode: RSIF Mask          */\r
+#define USIC_CH_PSR_IICMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_IICMode: DLIF Position      */\r
+#define USIC_CH_PSR_IICMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_DLIF_Pos)                /*!< USIC_CH PSR_IICMode: DLIF Mask          */\r
+#define USIC_CH_PSR_IICMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_IICMode: TSIF Position      */\r
+#define USIC_CH_PSR_IICMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_TSIF_Pos)                /*!< USIC_CH PSR_IICMode: TSIF Mask          */\r
+#define USIC_CH_PSR_IICMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_IICMode: TBIF Position      */\r
+#define USIC_CH_PSR_IICMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_IICMode_TBIF_Pos)                /*!< USIC_CH PSR_IICMode: TBIF Mask          */\r
+#define USIC_CH_PSR_IICMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_IICMode: RIF Position       */\r
+#define USIC_CH_PSR_IICMode_RIF_Msk           (0x01UL << USIC_CH_PSR_IICMode_RIF_Pos)                 /*!< USIC_CH PSR_IICMode: RIF Mask           */\r
+#define USIC_CH_PSR_IICMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_IICMode: AIF Position       */\r
+#define USIC_CH_PSR_IICMode_AIF_Msk           (0x01UL << USIC_CH_PSR_IICMode_AIF_Pos)                 /*!< USIC_CH PSR_IICMode: AIF Mask           */\r
+#define USIC_CH_PSR_IICMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_IICMode: BRGIF Position     */\r
+#define USIC_CH_PSR_IICMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_IICMode_BRGIF_Pos)               /*!< USIC_CH PSR_IICMode: BRGIF Mask         */\r
+\r
+/* -----------------------------  USIC_CH_PSR_IISMode  ---------------------------- */\r
+#define USIC_CH_PSR_IISMode_WA_Pos            0                                                       /*!< USIC_CH PSR_IISMode: WA Position        */\r
+#define USIC_CH_PSR_IISMode_WA_Msk            (0x01UL << USIC_CH_PSR_IISMode_WA_Pos)                  /*!< USIC_CH PSR_IISMode: WA Mask            */\r
+#define USIC_CH_PSR_IISMode_DX2S_Pos          1                                                       /*!< USIC_CH PSR_IISMode: DX2S Position      */\r
+#define USIC_CH_PSR_IISMode_DX2S_Msk          (0x01UL << USIC_CH_PSR_IISMode_DX2S_Pos)                /*!< USIC_CH PSR_IISMode: DX2S Mask          */\r
+#define USIC_CH_PSR_IISMode_DX2TEV_Pos        3                                                       /*!< USIC_CH PSR_IISMode: DX2TEV Position    */\r
+#define USIC_CH_PSR_IISMode_DX2TEV_Msk        (0x01UL << USIC_CH_PSR_IISMode_DX2TEV_Pos)              /*!< USIC_CH PSR_IISMode: DX2TEV Mask        */\r
+#define USIC_CH_PSR_IISMode_WAFE_Pos          4                                                       /*!< USIC_CH PSR_IISMode: WAFE Position      */\r
+#define USIC_CH_PSR_IISMode_WAFE_Msk          (0x01UL << USIC_CH_PSR_IISMode_WAFE_Pos)                /*!< USIC_CH PSR_IISMode: WAFE Mask          */\r
+#define USIC_CH_PSR_IISMode_WARE_Pos          5                                                       /*!< USIC_CH PSR_IISMode: WARE Position      */\r
+#define USIC_CH_PSR_IISMode_WARE_Msk          (0x01UL << USIC_CH_PSR_IISMode_WARE_Pos)                /*!< USIC_CH PSR_IISMode: WARE Mask          */\r
+#define USIC_CH_PSR_IISMode_END_Pos           6                                                       /*!< USIC_CH PSR_IISMode: END Position       */\r
+#define USIC_CH_PSR_IISMode_END_Msk           (0x01UL << USIC_CH_PSR_IISMode_END_Pos)                 /*!< USIC_CH PSR_IISMode: END Mask           */\r
+#define USIC_CH_PSR_IISMode_RSIF_Pos          10                                                      /*!< USIC_CH PSR_IISMode: RSIF Position      */\r
+#define USIC_CH_PSR_IISMode_RSIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_RSIF_Pos)                /*!< USIC_CH PSR_IISMode: RSIF Mask          */\r
+#define USIC_CH_PSR_IISMode_DLIF_Pos          11                                                      /*!< USIC_CH PSR_IISMode: DLIF Position      */\r
+#define USIC_CH_PSR_IISMode_DLIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_DLIF_Pos)                /*!< USIC_CH PSR_IISMode: DLIF Mask          */\r
+#define USIC_CH_PSR_IISMode_TSIF_Pos          12                                                      /*!< USIC_CH PSR_IISMode: TSIF Position      */\r
+#define USIC_CH_PSR_IISMode_TSIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_TSIF_Pos)                /*!< USIC_CH PSR_IISMode: TSIF Mask          */\r
+#define USIC_CH_PSR_IISMode_TBIF_Pos          13                                                      /*!< USIC_CH PSR_IISMode: TBIF Position      */\r
+#define USIC_CH_PSR_IISMode_TBIF_Msk          (0x01UL << USIC_CH_PSR_IISMode_TBIF_Pos)                /*!< USIC_CH PSR_IISMode: TBIF Mask          */\r
+#define USIC_CH_PSR_IISMode_RIF_Pos           14                                                      /*!< USIC_CH PSR_IISMode: RIF Position       */\r
+#define USIC_CH_PSR_IISMode_RIF_Msk           (0x01UL << USIC_CH_PSR_IISMode_RIF_Pos)                 /*!< USIC_CH PSR_IISMode: RIF Mask           */\r
+#define USIC_CH_PSR_IISMode_AIF_Pos           15                                                      /*!< USIC_CH PSR_IISMode: AIF Position       */\r
+#define USIC_CH_PSR_IISMode_AIF_Msk           (0x01UL << USIC_CH_PSR_IISMode_AIF_Pos)                 /*!< USIC_CH PSR_IISMode: AIF Mask           */\r
+#define USIC_CH_PSR_IISMode_BRGIF_Pos         16                                                      /*!< USIC_CH PSR_IISMode: BRGIF Position     */\r
+#define USIC_CH_PSR_IISMode_BRGIF_Msk         (0x01UL << USIC_CH_PSR_IISMode_BRGIF_Pos)               /*!< USIC_CH PSR_IISMode: BRGIF Mask         */\r
+\r
+/* --------------------------------  USIC_CH_PSCR  -------------------------------- */\r
+#define USIC_CH_PSCR_CST0_Pos                 0                                                       /*!< USIC_CH PSCR: CST0 Position             */\r
+#define USIC_CH_PSCR_CST0_Msk                 (0x01UL << USIC_CH_PSCR_CST0_Pos)                       /*!< USIC_CH PSCR: CST0 Mask                 */\r
+#define USIC_CH_PSCR_CST1_Pos                 1                                                       /*!< USIC_CH PSCR: CST1 Position             */\r
+#define USIC_CH_PSCR_CST1_Msk                 (0x01UL << USIC_CH_PSCR_CST1_Pos)                       /*!< USIC_CH PSCR: CST1 Mask                 */\r
+#define USIC_CH_PSCR_CST2_Pos                 2                                                       /*!< USIC_CH PSCR: CST2 Position             */\r
+#define USIC_CH_PSCR_CST2_Msk                 (0x01UL << USIC_CH_PSCR_CST2_Pos)                       /*!< USIC_CH PSCR: CST2 Mask                 */\r
+#define USIC_CH_PSCR_CST3_Pos                 3                                                       /*!< USIC_CH PSCR: CST3 Position             */\r
+#define USIC_CH_PSCR_CST3_Msk                 (0x01UL << USIC_CH_PSCR_CST3_Pos)                       /*!< USIC_CH PSCR: CST3 Mask                 */\r
+#define USIC_CH_PSCR_CST4_Pos                 4                                                       /*!< USIC_CH PSCR: CST4 Position             */\r
+#define USIC_CH_PSCR_CST4_Msk                 (0x01UL << USIC_CH_PSCR_CST4_Pos)                       /*!< USIC_CH PSCR: CST4 Mask                 */\r
+#define USIC_CH_PSCR_CST5_Pos                 5                                                       /*!< USIC_CH PSCR: CST5 Position             */\r
+#define USIC_CH_PSCR_CST5_Msk                 (0x01UL << USIC_CH_PSCR_CST5_Pos)                       /*!< USIC_CH PSCR: CST5 Mask                 */\r
+#define USIC_CH_PSCR_CST6_Pos                 6                                                       /*!< USIC_CH PSCR: CST6 Position             */\r
+#define USIC_CH_PSCR_CST6_Msk                 (0x01UL << USIC_CH_PSCR_CST6_Pos)                       /*!< USIC_CH PSCR: CST6 Mask                 */\r
+#define USIC_CH_PSCR_CST7_Pos                 7                                                       /*!< USIC_CH PSCR: CST7 Position             */\r
+#define USIC_CH_PSCR_CST7_Msk                 (0x01UL << USIC_CH_PSCR_CST7_Pos)                       /*!< USIC_CH PSCR: CST7 Mask                 */\r
+#define USIC_CH_PSCR_CST8_Pos                 8                                                       /*!< USIC_CH PSCR: CST8 Position             */\r
+#define USIC_CH_PSCR_CST8_Msk                 (0x01UL << USIC_CH_PSCR_CST8_Pos)                       /*!< USIC_CH PSCR: CST8 Mask                 */\r
+#define USIC_CH_PSCR_CST9_Pos                 9                                                       /*!< USIC_CH PSCR: CST9 Position             */\r
+#define USIC_CH_PSCR_CST9_Msk                 (0x01UL << USIC_CH_PSCR_CST9_Pos)                       /*!< USIC_CH PSCR: CST9 Mask                 */\r
+#define USIC_CH_PSCR_CRSIF_Pos                10                                                      /*!< USIC_CH PSCR: CRSIF Position            */\r
+#define USIC_CH_PSCR_CRSIF_Msk                (0x01UL << USIC_CH_PSCR_CRSIF_Pos)                      /*!< USIC_CH PSCR: CRSIF Mask                */\r
+#define USIC_CH_PSCR_CDLIF_Pos                11                                                      /*!< USIC_CH PSCR: CDLIF Position            */\r
+#define USIC_CH_PSCR_CDLIF_Msk                (0x01UL << USIC_CH_PSCR_CDLIF_Pos)                      /*!< USIC_CH PSCR: CDLIF Mask                */\r
+#define USIC_CH_PSCR_CTSIF_Pos                12                                                      /*!< USIC_CH PSCR: CTSIF Position            */\r
+#define USIC_CH_PSCR_CTSIF_Msk                (0x01UL << USIC_CH_PSCR_CTSIF_Pos)                      /*!< USIC_CH PSCR: CTSIF Mask                */\r
+#define USIC_CH_PSCR_CTBIF_Pos                13                                                      /*!< USIC_CH PSCR: CTBIF Position            */\r
+#define USIC_CH_PSCR_CTBIF_Msk                (0x01UL << USIC_CH_PSCR_CTBIF_Pos)                      /*!< USIC_CH PSCR: CTBIF Mask                */\r
+#define USIC_CH_PSCR_CRIF_Pos                 14                                                      /*!< USIC_CH PSCR: CRIF Position             */\r
+#define USIC_CH_PSCR_CRIF_Msk                 (0x01UL << USIC_CH_PSCR_CRIF_Pos)                       /*!< USIC_CH PSCR: CRIF Mask                 */\r
+#define USIC_CH_PSCR_CAIF_Pos                 15                                                      /*!< USIC_CH PSCR: CAIF Position             */\r
+#define USIC_CH_PSCR_CAIF_Msk                 (0x01UL << USIC_CH_PSCR_CAIF_Pos)                       /*!< USIC_CH PSCR: CAIF Mask                 */\r
+#define USIC_CH_PSCR_CBRGIF_Pos               16                                                      /*!< USIC_CH PSCR: CBRGIF Position           */\r
+#define USIC_CH_PSCR_CBRGIF_Msk               (0x01UL << USIC_CH_PSCR_CBRGIF_Pos)                     /*!< USIC_CH PSCR: CBRGIF Mask               */\r
+\r
+/* -------------------------------  USIC_CH_RBUFSR  ------------------------------- */\r
+#define USIC_CH_RBUFSR_WLEN_Pos               0                                                       /*!< USIC_CH RBUFSR: WLEN Position           */\r
+#define USIC_CH_RBUFSR_WLEN_Msk               (0x0fUL << USIC_CH_RBUFSR_WLEN_Pos)                     /*!< USIC_CH RBUFSR: WLEN Mask               */\r
+#define USIC_CH_RBUFSR_SOF_Pos                6                                                       /*!< USIC_CH RBUFSR: SOF Position            */\r
+#define USIC_CH_RBUFSR_SOF_Msk                (0x01UL << USIC_CH_RBUFSR_SOF_Pos)                      /*!< USIC_CH RBUFSR: SOF Mask                */\r
+#define USIC_CH_RBUFSR_PAR_Pos                8                                                       /*!< USIC_CH RBUFSR: PAR Position            */\r
+#define USIC_CH_RBUFSR_PAR_Msk                (0x01UL << USIC_CH_RBUFSR_PAR_Pos)                      /*!< USIC_CH RBUFSR: PAR Mask                */\r
+#define USIC_CH_RBUFSR_PERR_Pos               9                                                       /*!< USIC_CH RBUFSR: PERR Position           */\r
+#define USIC_CH_RBUFSR_PERR_Msk               (0x01UL << USIC_CH_RBUFSR_PERR_Pos)                     /*!< USIC_CH RBUFSR: PERR Mask               */\r
+#define USIC_CH_RBUFSR_RDV0_Pos               13                                                      /*!< USIC_CH RBUFSR: RDV0 Position           */\r
+#define USIC_CH_RBUFSR_RDV0_Msk               (0x01UL << USIC_CH_RBUFSR_RDV0_Pos)                     /*!< USIC_CH RBUFSR: RDV0 Mask               */\r
+#define USIC_CH_RBUFSR_RDV1_Pos               14                                                      /*!< USIC_CH RBUFSR: RDV1 Position           */\r
+#define USIC_CH_RBUFSR_RDV1_Msk               (0x01UL << USIC_CH_RBUFSR_RDV1_Pos)                     /*!< USIC_CH RBUFSR: RDV1 Mask               */\r
+#define USIC_CH_RBUFSR_DS_Pos                 15                                                      /*!< USIC_CH RBUFSR: DS Position             */\r
+#define USIC_CH_RBUFSR_DS_Msk                 (0x01UL << USIC_CH_RBUFSR_DS_Pos)                       /*!< USIC_CH RBUFSR: DS Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_RBUF  -------------------------------- */\r
+#define USIC_CH_RBUF_DSR_Pos                  0                                                       /*!< USIC_CH RBUF: DSR Position              */\r
+#define USIC_CH_RBUF_DSR_Msk                  (0x0000ffffUL << USIC_CH_RBUF_DSR_Pos)                  /*!< USIC_CH RBUF: DSR Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_RBUFD  ------------------------------- */\r
+#define USIC_CH_RBUFD_DSR_Pos                 0                                                       /*!< USIC_CH RBUFD: DSR Position             */\r
+#define USIC_CH_RBUFD_DSR_Msk                 (0x0000ffffUL << USIC_CH_RBUFD_DSR_Pos)                 /*!< USIC_CH RBUFD: DSR Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_RBUF0  ------------------------------- */\r
+#define USIC_CH_RBUF0_DSR0_Pos                0                                                       /*!< USIC_CH RBUF0: DSR0 Position            */\r
+#define USIC_CH_RBUF0_DSR0_Msk                (0x0000ffffUL << USIC_CH_RBUF0_DSR0_Pos)                /*!< USIC_CH RBUF0: DSR0 Mask                */\r
+\r
+/* --------------------------------  USIC_CH_RBUF1  ------------------------------- */\r
+#define USIC_CH_RBUF1_DSR1_Pos                0                                                       /*!< USIC_CH RBUF1: DSR1 Position            */\r
+#define USIC_CH_RBUF1_DSR1_Msk                (0x0000ffffUL << USIC_CH_RBUF1_DSR1_Pos)                /*!< USIC_CH RBUF1: DSR1 Mask                */\r
+\r
+/* ------------------------------  USIC_CH_RBUF01SR  ------------------------------ */\r
+#define USIC_CH_RBUF01SR_WLEN0_Pos            0                                                       /*!< USIC_CH RBUF01SR: WLEN0 Position        */\r
+#define USIC_CH_RBUF01SR_WLEN0_Msk            (0x0fUL << USIC_CH_RBUF01SR_WLEN0_Pos)                  /*!< USIC_CH RBUF01SR: WLEN0 Mask            */\r
+#define USIC_CH_RBUF01SR_SOF0_Pos             6                                                       /*!< USIC_CH RBUF01SR: SOF0 Position         */\r
+#define USIC_CH_RBUF01SR_SOF0_Msk             (0x01UL << USIC_CH_RBUF01SR_SOF0_Pos)                   /*!< USIC_CH RBUF01SR: SOF0 Mask             */\r
+#define USIC_CH_RBUF01SR_PAR0_Pos             8                                                       /*!< USIC_CH RBUF01SR: PAR0 Position         */\r
+#define USIC_CH_RBUF01SR_PAR0_Msk             (0x01UL << USIC_CH_RBUF01SR_PAR0_Pos)                   /*!< USIC_CH RBUF01SR: PAR0 Mask             */\r
+#define USIC_CH_RBUF01SR_PERR0_Pos            9                                                       /*!< USIC_CH RBUF01SR: PERR0 Position        */\r
+#define USIC_CH_RBUF01SR_PERR0_Msk            (0x01UL << USIC_CH_RBUF01SR_PERR0_Pos)                  /*!< USIC_CH RBUF01SR: PERR0 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV00_Pos            13                                                      /*!< USIC_CH RBUF01SR: RDV00 Position        */\r
+#define USIC_CH_RBUF01SR_RDV00_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV00_Pos)                  /*!< USIC_CH RBUF01SR: RDV00 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV01_Pos            14                                                      /*!< USIC_CH RBUF01SR: RDV01 Position        */\r
+#define USIC_CH_RBUF01SR_RDV01_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV01_Pos)                  /*!< USIC_CH RBUF01SR: RDV01 Mask            */\r
+#define USIC_CH_RBUF01SR_DS0_Pos              15                                                      /*!< USIC_CH RBUF01SR: DS0 Position          */\r
+#define USIC_CH_RBUF01SR_DS0_Msk              (0x01UL << USIC_CH_RBUF01SR_DS0_Pos)                    /*!< USIC_CH RBUF01SR: DS0 Mask              */\r
+#define USIC_CH_RBUF01SR_WLEN1_Pos            16                                                      /*!< USIC_CH RBUF01SR: WLEN1 Position        */\r
+#define USIC_CH_RBUF01SR_WLEN1_Msk            (0x0fUL << USIC_CH_RBUF01SR_WLEN1_Pos)                  /*!< USIC_CH RBUF01SR: WLEN1 Mask            */\r
+#define USIC_CH_RBUF01SR_SOF1_Pos             22                                                      /*!< USIC_CH RBUF01SR: SOF1 Position         */\r
+#define USIC_CH_RBUF01SR_SOF1_Msk             (0x01UL << USIC_CH_RBUF01SR_SOF1_Pos)                   /*!< USIC_CH RBUF01SR: SOF1 Mask             */\r
+#define USIC_CH_RBUF01SR_PAR1_Pos             24                                                      /*!< USIC_CH RBUF01SR: PAR1 Position         */\r
+#define USIC_CH_RBUF01SR_PAR1_Msk             (0x01UL << USIC_CH_RBUF01SR_PAR1_Pos)                   /*!< USIC_CH RBUF01SR: PAR1 Mask             */\r
+#define USIC_CH_RBUF01SR_PERR1_Pos            25                                                      /*!< USIC_CH RBUF01SR: PERR1 Position        */\r
+#define USIC_CH_RBUF01SR_PERR1_Msk            (0x01UL << USIC_CH_RBUF01SR_PERR1_Pos)                  /*!< USIC_CH RBUF01SR: PERR1 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV10_Pos            29                                                      /*!< USIC_CH RBUF01SR: RDV10 Position        */\r
+#define USIC_CH_RBUF01SR_RDV10_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV10_Pos)                  /*!< USIC_CH RBUF01SR: RDV10 Mask            */\r
+#define USIC_CH_RBUF01SR_RDV11_Pos            30                                                      /*!< USIC_CH RBUF01SR: RDV11 Position        */\r
+#define USIC_CH_RBUF01SR_RDV11_Msk            (0x01UL << USIC_CH_RBUF01SR_RDV11_Pos)                  /*!< USIC_CH RBUF01SR: RDV11 Mask            */\r
+#define USIC_CH_RBUF01SR_DS1_Pos              31                                                      /*!< USIC_CH RBUF01SR: DS1 Position          */\r
+#define USIC_CH_RBUF01SR_DS1_Msk              (0x01UL << USIC_CH_RBUF01SR_DS1_Pos)                    /*!< USIC_CH RBUF01SR: DS1 Mask              */\r
+\r
+/* ---------------------------------  USIC_CH_FMR  -------------------------------- */\r
+#define USIC_CH_FMR_MTDV_Pos                  0                                                       /*!< USIC_CH FMR: MTDV Position              */\r
+#define USIC_CH_FMR_MTDV_Msk                  (0x03UL << USIC_CH_FMR_MTDV_Pos)                        /*!< USIC_CH FMR: MTDV Mask                  */\r
+#define USIC_CH_FMR_ATVC_Pos                  4                                                       /*!< USIC_CH FMR: ATVC Position              */\r
+#define USIC_CH_FMR_ATVC_Msk                  (0x01UL << USIC_CH_FMR_ATVC_Pos)                        /*!< USIC_CH FMR: ATVC Mask                  */\r
+#define USIC_CH_FMR_CRDV0_Pos                 14                                                      /*!< USIC_CH FMR: CRDV0 Position             */\r
+#define USIC_CH_FMR_CRDV0_Msk                 (0x01UL << USIC_CH_FMR_CRDV0_Pos)                       /*!< USIC_CH FMR: CRDV0 Mask                 */\r
+#define USIC_CH_FMR_CRDV1_Pos                 15                                                      /*!< USIC_CH FMR: CRDV1 Position             */\r
+#define USIC_CH_FMR_CRDV1_Msk                 (0x01UL << USIC_CH_FMR_CRDV1_Pos)                       /*!< USIC_CH FMR: CRDV1 Mask                 */\r
+#define USIC_CH_FMR_SIO0_Pos                  16                                                      /*!< USIC_CH FMR: SIO0 Position              */\r
+#define USIC_CH_FMR_SIO0_Msk                  (0x01UL << USIC_CH_FMR_SIO0_Pos)                        /*!< USIC_CH FMR: SIO0 Mask                  */\r
+#define USIC_CH_FMR_SIO1_Pos                  17                                                      /*!< USIC_CH FMR: SIO1 Position              */\r
+#define USIC_CH_FMR_SIO1_Msk                  (0x01UL << USIC_CH_FMR_SIO1_Pos)                        /*!< USIC_CH FMR: SIO1 Mask                  */\r
+#define USIC_CH_FMR_SIO2_Pos                  18                                                      /*!< USIC_CH FMR: SIO2 Position              */\r
+#define USIC_CH_FMR_SIO2_Msk                  (0x01UL << USIC_CH_FMR_SIO2_Pos)                        /*!< USIC_CH FMR: SIO2 Mask                  */\r
+#define USIC_CH_FMR_SIO3_Pos                  19                                                      /*!< USIC_CH FMR: SIO3 Position              */\r
+#define USIC_CH_FMR_SIO3_Msk                  (0x01UL << USIC_CH_FMR_SIO3_Pos)                        /*!< USIC_CH FMR: SIO3 Mask                  */\r
+#define USIC_CH_FMR_SIO4_Pos                  20                                                      /*!< USIC_CH FMR: SIO4 Position              */\r
+#define USIC_CH_FMR_SIO4_Msk                  (0x01UL << USIC_CH_FMR_SIO4_Pos)                        /*!< USIC_CH FMR: SIO4 Mask                  */\r
+#define USIC_CH_FMR_SIO5_Pos                  21                                                      /*!< USIC_CH FMR: SIO5 Position              */\r
+#define USIC_CH_FMR_SIO5_Msk                  (0x01UL << USIC_CH_FMR_SIO5_Pos)                        /*!< USIC_CH FMR: SIO5 Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_TBUF  -------------------------------- */\r
+#define USIC_CH_TBUF_TDATA_Pos                0                                                       /*!< USIC_CH TBUF: TDATA Position            */\r
+#define USIC_CH_TBUF_TDATA_Msk                (0x0000ffffUL << USIC_CH_TBUF_TDATA_Pos)                /*!< USIC_CH TBUF: TDATA Mask                */\r
+\r
+/* ---------------------------------  USIC_CH_BYP  -------------------------------- */\r
+#define USIC_CH_BYP_BDATA_Pos                 0                                                       /*!< USIC_CH BYP: BDATA Position             */\r
+#define USIC_CH_BYP_BDATA_Msk                 (0x0000ffffUL << USIC_CH_BYP_BDATA_Pos)                 /*!< USIC_CH BYP: BDATA Mask                 */\r
+\r
+/* --------------------------------  USIC_CH_BYPCR  ------------------------------- */\r
+#define USIC_CH_BYPCR_BWLE_Pos                0                                                       /*!< USIC_CH BYPCR: BWLE Position            */\r
+#define USIC_CH_BYPCR_BWLE_Msk                (0x0fUL << USIC_CH_BYPCR_BWLE_Pos)                      /*!< USIC_CH BYPCR: BWLE Mask                */\r
+#define USIC_CH_BYPCR_BDSSM_Pos               8                                                       /*!< USIC_CH BYPCR: BDSSM Position           */\r
+#define USIC_CH_BYPCR_BDSSM_Msk               (0x01UL << USIC_CH_BYPCR_BDSSM_Pos)                     /*!< USIC_CH BYPCR: BDSSM Mask               */\r
+#define USIC_CH_BYPCR_BDEN_Pos                10                                                      /*!< USIC_CH BYPCR: BDEN Position            */\r
+#define USIC_CH_BYPCR_BDEN_Msk                (0x03UL << USIC_CH_BYPCR_BDEN_Pos)                      /*!< USIC_CH BYPCR: BDEN Mask                */\r
+#define USIC_CH_BYPCR_BDVTR_Pos               12                                                      /*!< USIC_CH BYPCR: BDVTR Position           */\r
+#define USIC_CH_BYPCR_BDVTR_Msk               (0x01UL << USIC_CH_BYPCR_BDVTR_Pos)                     /*!< USIC_CH BYPCR: BDVTR Mask               */\r
+#define USIC_CH_BYPCR_BPRIO_Pos               13                                                      /*!< USIC_CH BYPCR: BPRIO Position           */\r
+#define USIC_CH_BYPCR_BPRIO_Msk               (0x01UL << USIC_CH_BYPCR_BPRIO_Pos)                     /*!< USIC_CH BYPCR: BPRIO Mask               */\r
+#define USIC_CH_BYPCR_BDV_Pos                 15                                                      /*!< USIC_CH BYPCR: BDV Position             */\r
+#define USIC_CH_BYPCR_BDV_Msk                 (0x01UL << USIC_CH_BYPCR_BDV_Pos)                       /*!< USIC_CH BYPCR: BDV Mask                 */\r
+#define USIC_CH_BYPCR_BSELO_Pos               16                                                      /*!< USIC_CH BYPCR: BSELO Position           */\r
+#define USIC_CH_BYPCR_BSELO_Msk               (0x1fUL << USIC_CH_BYPCR_BSELO_Pos)                     /*!< USIC_CH BYPCR: BSELO Mask               */\r
+#define USIC_CH_BYPCR_BHPC_Pos                21                                                      /*!< USIC_CH BYPCR: BHPC Position            */\r
+#define USIC_CH_BYPCR_BHPC_Msk                (0x07UL << USIC_CH_BYPCR_BHPC_Pos)                      /*!< USIC_CH BYPCR: BHPC Mask                */\r
+\r
+/* --------------------------------  USIC_CH_TBCTR  ------------------------------- */\r
+#define USIC_CH_TBCTR_DPTR_Pos                0                                                       /*!< USIC_CH TBCTR: DPTR Position            */\r
+#define USIC_CH_TBCTR_DPTR_Msk                (0x3fUL << USIC_CH_TBCTR_DPTR_Pos)                      /*!< USIC_CH TBCTR: DPTR Mask                */\r
+#define USIC_CH_TBCTR_LIMIT_Pos               8                                                       /*!< USIC_CH TBCTR: LIMIT Position           */\r
+#define USIC_CH_TBCTR_LIMIT_Msk               (0x3fUL << USIC_CH_TBCTR_LIMIT_Pos)                     /*!< USIC_CH TBCTR: LIMIT Mask               */\r
+#define USIC_CH_TBCTR_STBTM_Pos               14                                                      /*!< USIC_CH TBCTR: STBTM Position           */\r
+#define USIC_CH_TBCTR_STBTM_Msk               (0x01UL << USIC_CH_TBCTR_STBTM_Pos)                     /*!< USIC_CH TBCTR: STBTM Mask               */\r
+#define USIC_CH_TBCTR_STBTEN_Pos              15                                                      /*!< USIC_CH TBCTR: STBTEN Position          */\r
+#define USIC_CH_TBCTR_STBTEN_Msk              (0x01UL << USIC_CH_TBCTR_STBTEN_Pos)                    /*!< USIC_CH TBCTR: STBTEN Mask              */\r
+#define USIC_CH_TBCTR_STBINP_Pos              16                                                      /*!< USIC_CH TBCTR: STBINP Position          */\r
+#define USIC_CH_TBCTR_STBINP_Msk              (0x07UL << USIC_CH_TBCTR_STBINP_Pos)                    /*!< USIC_CH TBCTR: STBINP Mask              */\r
+#define USIC_CH_TBCTR_ATBINP_Pos              19                                                      /*!< USIC_CH TBCTR: ATBINP Position          */\r
+#define USIC_CH_TBCTR_ATBINP_Msk              (0x07UL << USIC_CH_TBCTR_ATBINP_Pos)                    /*!< USIC_CH TBCTR: ATBINP Mask              */\r
+#define USIC_CH_TBCTR_SIZE_Pos                24                                                      /*!< USIC_CH TBCTR: SIZE Position            */\r
+#define USIC_CH_TBCTR_SIZE_Msk                (0x07UL << USIC_CH_TBCTR_SIZE_Pos)                      /*!< USIC_CH TBCTR: SIZE Mask                */\r
+#define USIC_CH_TBCTR_LOF_Pos                 28                                                      /*!< USIC_CH TBCTR: LOF Position             */\r
+#define USIC_CH_TBCTR_LOF_Msk                 (0x01UL << USIC_CH_TBCTR_LOF_Pos)                       /*!< USIC_CH TBCTR: LOF Mask                 */\r
+#define USIC_CH_TBCTR_STBIEN_Pos              30                                                      /*!< USIC_CH TBCTR: STBIEN Position          */\r
+#define USIC_CH_TBCTR_STBIEN_Msk              (0x01UL << USIC_CH_TBCTR_STBIEN_Pos)                    /*!< USIC_CH TBCTR: STBIEN Mask              */\r
+#define USIC_CH_TBCTR_TBERIEN_Pos             31                                                      /*!< USIC_CH TBCTR: TBERIEN Position         */\r
+#define USIC_CH_TBCTR_TBERIEN_Msk             (0x01UL << USIC_CH_TBCTR_TBERIEN_Pos)                   /*!< USIC_CH TBCTR: TBERIEN Mask             */\r
+\r
+/* --------------------------------  USIC_CH_RBCTR  ------------------------------- */\r
+#define USIC_CH_RBCTR_DPTR_Pos                0                                                       /*!< USIC_CH RBCTR: DPTR Position            */\r
+#define USIC_CH_RBCTR_DPTR_Msk                (0x3fUL << USIC_CH_RBCTR_DPTR_Pos)                      /*!< USIC_CH RBCTR: DPTR Mask                */\r
+#define USIC_CH_RBCTR_LIMIT_Pos               8                                                       /*!< USIC_CH RBCTR: LIMIT Position           */\r
+#define USIC_CH_RBCTR_LIMIT_Msk               (0x3fUL << USIC_CH_RBCTR_LIMIT_Pos)                     /*!< USIC_CH RBCTR: LIMIT Mask               */\r
+#define USIC_CH_RBCTR_SRBTM_Pos               14                                                      /*!< USIC_CH RBCTR: SRBTM Position           */\r
+#define USIC_CH_RBCTR_SRBTM_Msk               (0x01UL << USIC_CH_RBCTR_SRBTM_Pos)                     /*!< USIC_CH RBCTR: SRBTM Mask               */\r
+#define USIC_CH_RBCTR_SRBTEN_Pos              15                                                      /*!< USIC_CH RBCTR: SRBTEN Position          */\r
+#define USIC_CH_RBCTR_SRBTEN_Msk              (0x01UL << USIC_CH_RBCTR_SRBTEN_Pos)                    /*!< USIC_CH RBCTR: SRBTEN Mask              */\r
+#define USIC_CH_RBCTR_SRBINP_Pos              16                                                      /*!< USIC_CH RBCTR: SRBINP Position          */\r
+#define USIC_CH_RBCTR_SRBINP_Msk              (0x07UL << USIC_CH_RBCTR_SRBINP_Pos)                    /*!< USIC_CH RBCTR: SRBINP Mask              */\r
+#define USIC_CH_RBCTR_ARBINP_Pos              19                                                      /*!< USIC_CH RBCTR: ARBINP Position          */\r
+#define USIC_CH_RBCTR_ARBINP_Msk              (0x07UL << USIC_CH_RBCTR_ARBINP_Pos)                    /*!< USIC_CH RBCTR: ARBINP Mask              */\r
+#define USIC_CH_RBCTR_RCIM_Pos                22                                                      /*!< USIC_CH RBCTR: RCIM Position            */\r
+#define USIC_CH_RBCTR_RCIM_Msk                (0x03UL << USIC_CH_RBCTR_RCIM_Pos)                      /*!< USIC_CH RBCTR: RCIM Mask                */\r
+#define USIC_CH_RBCTR_SIZE_Pos                24                                                      /*!< USIC_CH RBCTR: SIZE Position            */\r
+#define USIC_CH_RBCTR_SIZE_Msk                (0x07UL << USIC_CH_RBCTR_SIZE_Pos)                      /*!< USIC_CH RBCTR: SIZE Mask                */\r
+#define USIC_CH_RBCTR_RNM_Pos                 27                                                      /*!< USIC_CH RBCTR: RNM Position             */\r
+#define USIC_CH_RBCTR_RNM_Msk                 (0x01UL << USIC_CH_RBCTR_RNM_Pos)                       /*!< USIC_CH RBCTR: RNM Mask                 */\r
+#define USIC_CH_RBCTR_LOF_Pos                 28                                                      /*!< USIC_CH RBCTR: LOF Position             */\r
+#define USIC_CH_RBCTR_LOF_Msk                 (0x01UL << USIC_CH_RBCTR_LOF_Pos)                       /*!< USIC_CH RBCTR: LOF Mask                 */\r
+#define USIC_CH_RBCTR_ARBIEN_Pos              29                                                      /*!< USIC_CH RBCTR: ARBIEN Position          */\r
+#define USIC_CH_RBCTR_ARBIEN_Msk              (0x01UL << USIC_CH_RBCTR_ARBIEN_Pos)                    /*!< USIC_CH RBCTR: ARBIEN Mask              */\r
+#define USIC_CH_RBCTR_SRBIEN_Pos              30                                                      /*!< USIC_CH RBCTR: SRBIEN Position          */\r
+#define USIC_CH_RBCTR_SRBIEN_Msk              (0x01UL << USIC_CH_RBCTR_SRBIEN_Pos)                    /*!< USIC_CH RBCTR: SRBIEN Mask              */\r
+#define USIC_CH_RBCTR_RBERIEN_Pos             31                                                      /*!< USIC_CH RBCTR: RBERIEN Position         */\r
+#define USIC_CH_RBCTR_RBERIEN_Msk             (0x01UL << USIC_CH_RBCTR_RBERIEN_Pos)                   /*!< USIC_CH RBCTR: RBERIEN Mask             */\r
+\r
+/* -------------------------------  USIC_CH_TRBPTR  ------------------------------- */\r
+#define USIC_CH_TRBPTR_TDIPTR_Pos             0                                                       /*!< USIC_CH TRBPTR: TDIPTR Position         */\r
+#define USIC_CH_TRBPTR_TDIPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_TDIPTR_Pos)                   /*!< USIC_CH TRBPTR: TDIPTR Mask             */\r
+#define USIC_CH_TRBPTR_TDOPTR_Pos             8                                                       /*!< USIC_CH TRBPTR: TDOPTR Position         */\r
+#define USIC_CH_TRBPTR_TDOPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_TDOPTR_Pos)                   /*!< USIC_CH TRBPTR: TDOPTR Mask             */\r
+#define USIC_CH_TRBPTR_RDIPTR_Pos             16                                                      /*!< USIC_CH TRBPTR: RDIPTR Position         */\r
+#define USIC_CH_TRBPTR_RDIPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_RDIPTR_Pos)                   /*!< USIC_CH TRBPTR: RDIPTR Mask             */\r
+#define USIC_CH_TRBPTR_RDOPTR_Pos             24                                                      /*!< USIC_CH TRBPTR: RDOPTR Position         */\r
+#define USIC_CH_TRBPTR_RDOPTR_Msk             (0x3fUL << USIC_CH_TRBPTR_RDOPTR_Pos)                   /*!< USIC_CH TRBPTR: RDOPTR Mask             */\r
+\r
+/* --------------------------------  USIC_CH_TRBSR  ------------------------------- */\r
+#define USIC_CH_TRBSR_SRBI_Pos                0                                                       /*!< USIC_CH TRBSR: SRBI Position            */\r
+#define USIC_CH_TRBSR_SRBI_Msk                (0x01UL << USIC_CH_TRBSR_SRBI_Pos)                      /*!< USIC_CH TRBSR: SRBI Mask                */\r
+#define USIC_CH_TRBSR_RBERI_Pos               1                                                       /*!< USIC_CH TRBSR: RBERI Position           */\r
+#define USIC_CH_TRBSR_RBERI_Msk               (0x01UL << USIC_CH_TRBSR_RBERI_Pos)                     /*!< USIC_CH TRBSR: RBERI Mask               */\r
+#define USIC_CH_TRBSR_ARBI_Pos                2                                                       /*!< USIC_CH TRBSR: ARBI Position            */\r
+#define USIC_CH_TRBSR_ARBI_Msk                (0x01UL << USIC_CH_TRBSR_ARBI_Pos)                      /*!< USIC_CH TRBSR: ARBI Mask                */\r
+#define USIC_CH_TRBSR_REMPTY_Pos              3                                                       /*!< USIC_CH TRBSR: REMPTY Position          */\r
+#define USIC_CH_TRBSR_REMPTY_Msk              (0x01UL << USIC_CH_TRBSR_REMPTY_Pos)                    /*!< USIC_CH TRBSR: REMPTY Mask              */\r
+#define USIC_CH_TRBSR_RFULL_Pos               4                                                       /*!< USIC_CH TRBSR: RFULL Position           */\r
+#define USIC_CH_TRBSR_RFULL_Msk               (0x01UL << USIC_CH_TRBSR_RFULL_Pos)                     /*!< USIC_CH TRBSR: RFULL Mask               */\r
+#define USIC_CH_TRBSR_RBUS_Pos                5                                                       /*!< USIC_CH TRBSR: RBUS Position            */\r
+#define USIC_CH_TRBSR_RBUS_Msk                (0x01UL << USIC_CH_TRBSR_RBUS_Pos)                      /*!< USIC_CH TRBSR: RBUS Mask                */\r
+#define USIC_CH_TRBSR_SRBT_Pos                6                                                       /*!< USIC_CH TRBSR: SRBT Position            */\r
+#define USIC_CH_TRBSR_SRBT_Msk                (0x01UL << USIC_CH_TRBSR_SRBT_Pos)                      /*!< USIC_CH TRBSR: SRBT Mask                */\r
+#define USIC_CH_TRBSR_STBI_Pos                8                                                       /*!< USIC_CH TRBSR: STBI Position            */\r
+#define USIC_CH_TRBSR_STBI_Msk                (0x01UL << USIC_CH_TRBSR_STBI_Pos)                      /*!< USIC_CH TRBSR: STBI Mask                */\r
+#define USIC_CH_TRBSR_TBERI_Pos               9                                                       /*!< USIC_CH TRBSR: TBERI Position           */\r
+#define USIC_CH_TRBSR_TBERI_Msk               (0x01UL << USIC_CH_TRBSR_TBERI_Pos)                     /*!< USIC_CH TRBSR: TBERI Mask               */\r
+#define USIC_CH_TRBSR_TEMPTY_Pos              11                                                      /*!< USIC_CH TRBSR: TEMPTY Position          */\r
+#define USIC_CH_TRBSR_TEMPTY_Msk              (0x01UL << USIC_CH_TRBSR_TEMPTY_Pos)                    /*!< USIC_CH TRBSR: TEMPTY Mask              */\r
+#define USIC_CH_TRBSR_TFULL_Pos               12                                                      /*!< USIC_CH TRBSR: TFULL Position           */\r
+#define USIC_CH_TRBSR_TFULL_Msk               (0x01UL << USIC_CH_TRBSR_TFULL_Pos)                     /*!< USIC_CH TRBSR: TFULL Mask               */\r
+#define USIC_CH_TRBSR_TBUS_Pos                13                                                      /*!< USIC_CH TRBSR: TBUS Position            */\r
+#define USIC_CH_TRBSR_TBUS_Msk                (0x01UL << USIC_CH_TRBSR_TBUS_Pos)                      /*!< USIC_CH TRBSR: TBUS Mask                */\r
+#define USIC_CH_TRBSR_STBT_Pos                14                                                      /*!< USIC_CH TRBSR: STBT Position            */\r
+#define USIC_CH_TRBSR_STBT_Msk                (0x01UL << USIC_CH_TRBSR_STBT_Pos)                      /*!< USIC_CH TRBSR: STBT Mask                */\r
+#define USIC_CH_TRBSR_RBFLVL_Pos              16                                                      /*!< USIC_CH TRBSR: RBFLVL Position          */\r
+#define USIC_CH_TRBSR_RBFLVL_Msk              (0x7fUL << USIC_CH_TRBSR_RBFLVL_Pos)                    /*!< USIC_CH TRBSR: RBFLVL Mask              */\r
+#define USIC_CH_TRBSR_TBFLVL_Pos              24                                                      /*!< USIC_CH TRBSR: TBFLVL Position          */\r
+#define USIC_CH_TRBSR_TBFLVL_Msk              (0x7fUL << USIC_CH_TRBSR_TBFLVL_Pos)                    /*!< USIC_CH TRBSR: TBFLVL Mask              */\r
+\r
+/* -------------------------------  USIC_CH_TRBSCR  ------------------------------- */\r
+#define USIC_CH_TRBSCR_CSRBI_Pos              0                                                       /*!< USIC_CH TRBSCR: CSRBI Position          */\r
+#define USIC_CH_TRBSCR_CSRBI_Msk              (0x01UL << USIC_CH_TRBSCR_CSRBI_Pos)                    /*!< USIC_CH TRBSCR: CSRBI Mask              */\r
+#define USIC_CH_TRBSCR_CRBERI_Pos             1                                                       /*!< USIC_CH TRBSCR: CRBERI Position         */\r
+#define USIC_CH_TRBSCR_CRBERI_Msk             (0x01UL << USIC_CH_TRBSCR_CRBERI_Pos)                   /*!< USIC_CH TRBSCR: CRBERI Mask             */\r
+#define USIC_CH_TRBSCR_CARBI_Pos              2                                                       /*!< USIC_CH TRBSCR: CARBI Position          */\r
+#define USIC_CH_TRBSCR_CARBI_Msk              (0x01UL << USIC_CH_TRBSCR_CARBI_Pos)                    /*!< USIC_CH TRBSCR: CARBI Mask              */\r
+#define USIC_CH_TRBSCR_CSTBI_Pos              8                                                       /*!< USIC_CH TRBSCR: CSTBI Position          */\r
+#define USIC_CH_TRBSCR_CSTBI_Msk              (0x01UL << USIC_CH_TRBSCR_CSTBI_Pos)                    /*!< USIC_CH TRBSCR: CSTBI Mask              */\r
+#define USIC_CH_TRBSCR_CTBERI_Pos             9                                                       /*!< USIC_CH TRBSCR: CTBERI Position         */\r
+#define USIC_CH_TRBSCR_CTBERI_Msk             (0x01UL << USIC_CH_TRBSCR_CTBERI_Pos)                   /*!< USIC_CH TRBSCR: CTBERI Mask             */\r
+#define USIC_CH_TRBSCR_CBDV_Pos               10                                                      /*!< USIC_CH TRBSCR: CBDV Position           */\r
+#define USIC_CH_TRBSCR_CBDV_Msk               (0x01UL << USIC_CH_TRBSCR_CBDV_Pos)                     /*!< USIC_CH TRBSCR: CBDV Mask               */\r
+#define USIC_CH_TRBSCR_FLUSHRB_Pos            14                                                      /*!< USIC_CH TRBSCR: FLUSHRB Position        */\r
+#define USIC_CH_TRBSCR_FLUSHRB_Msk            (0x01UL << USIC_CH_TRBSCR_FLUSHRB_Pos)                  /*!< USIC_CH TRBSCR: FLUSHRB Mask            */\r
+#define USIC_CH_TRBSCR_FLUSHTB_Pos            15                                                      /*!< USIC_CH TRBSCR: FLUSHTB Position        */\r
+#define USIC_CH_TRBSCR_FLUSHTB_Msk            (0x01UL << USIC_CH_TRBSCR_FLUSHTB_Pos)                  /*!< USIC_CH TRBSCR: FLUSHTB Mask            */\r
+\r
+/* --------------------------------  USIC_CH_OUTR  -------------------------------- */\r
+#define USIC_CH_OUTR_DSR_Pos                  0                                                       /*!< USIC_CH OUTR: DSR Position              */\r
+#define USIC_CH_OUTR_DSR_Msk                  (0x0000ffffUL << USIC_CH_OUTR_DSR_Pos)                  /*!< USIC_CH OUTR: DSR Mask                  */\r
+#define USIC_CH_OUTR_RCI_Pos                  16                                                      /*!< USIC_CH OUTR: RCI Position              */\r
+#define USIC_CH_OUTR_RCI_Msk                  (0x1fUL << USIC_CH_OUTR_RCI_Pos)                        /*!< USIC_CH OUTR: RCI Mask                  */\r
+\r
+/* --------------------------------  USIC_CH_OUTDR  ------------------------------- */\r
+#define USIC_CH_OUTDR_DSR_Pos                 0                                                       /*!< USIC_CH OUTDR: DSR Position             */\r
+#define USIC_CH_OUTDR_DSR_Msk                 (0x0000ffffUL << USIC_CH_OUTDR_DSR_Pos)                 /*!< USIC_CH OUTDR: DSR Mask                 */\r
+#define USIC_CH_OUTDR_RCI_Pos                 16                                                      /*!< USIC_CH OUTDR: RCI Position             */\r
+#define USIC_CH_OUTDR_RCI_Msk                 (0x1fUL << USIC_CH_OUTDR_RCI_Pos)                       /*!< USIC_CH OUTDR: RCI Mask                 */\r
+\r
+/* ---------------------------------  USIC_CH_IN  --------------------------------- */\r
+#define USIC_CH_IN_TDATA_Pos                  0                                                       /*!< USIC_CH IN: TDATA Position              */\r
+#define USIC_CH_IN_TDATA_Msk                  (0x0000ffffUL << USIC_CH_IN_TDATA_Pos)                  /*!< USIC_CH IN: TDATA Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'CAN' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  CAN_CLC  ---------------------------------- */\r
+#define CAN_CLC_DISR_Pos                      0                                                       /*!< CAN CLC: DISR Position                  */\r
+#define CAN_CLC_DISR_Msk                      (0x01UL << CAN_CLC_DISR_Pos)                            /*!< CAN CLC: DISR Mask                      */\r
+#define CAN_CLC_DISS_Pos                      1                                                       /*!< CAN CLC: DISS Position                  */\r
+#define CAN_CLC_DISS_Msk                      (0x01UL << CAN_CLC_DISS_Pos)                            /*!< CAN CLC: DISS Mask                      */\r
+#define CAN_CLC_EDIS_Pos                      3                                                       /*!< CAN CLC: EDIS Position                  */\r
+#define CAN_CLC_EDIS_Msk                      (0x01UL << CAN_CLC_EDIS_Pos)                            /*!< CAN CLC: EDIS Mask                      */\r
+#define CAN_CLC_SBWE_Pos                      4                                                       /*!< CAN CLC: SBWE Position                  */\r
+#define CAN_CLC_SBWE_Msk                      (0x01UL << CAN_CLC_SBWE_Pos)                            /*!< CAN CLC: SBWE Mask                      */\r
+\r
+/* -----------------------------------  CAN_ID  ----------------------------------- */\r
+#define CAN_ID_MOD_REV_Pos                    0                                                       /*!< CAN ID: MOD_REV Position                */\r
+#define CAN_ID_MOD_REV_Msk                    (0x000000ffUL << CAN_ID_MOD_REV_Pos)                    /*!< CAN ID: MOD_REV Mask                    */\r
+#define CAN_ID_MOD_TYPE_Pos                   8                                                       /*!< CAN ID: MOD_TYPE Position               */\r
+#define CAN_ID_MOD_TYPE_Msk                   (0x000000ffUL << CAN_ID_MOD_TYPE_Pos)                   /*!< CAN ID: MOD_TYPE Mask                   */\r
+#define CAN_ID_MOD_NUMBER_Pos                 16                                                      /*!< CAN ID: MOD_NUMBER Position             */\r
+#define CAN_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << CAN_ID_MOD_NUMBER_Pos)                 /*!< CAN ID: MOD_NUMBER Mask                 */\r
+\r
+/* -----------------------------------  CAN_FDR  ---------------------------------- */\r
+#define CAN_FDR_STEP_Pos                      0                                                       /*!< CAN FDR: STEP Position                  */\r
+#define CAN_FDR_STEP_Msk                      (0x000003ffUL << CAN_FDR_STEP_Pos)                      /*!< CAN FDR: STEP Mask                      */\r
+#define CAN_FDR_SM_Pos                        11                                                      /*!< CAN FDR: SM Position                    */\r
+#define CAN_FDR_SM_Msk                        (0x01UL << CAN_FDR_SM_Pos)                              /*!< CAN FDR: SM Mask                        */\r
+#define CAN_FDR_SC_Pos                        12                                                      /*!< CAN FDR: SC Position                    */\r
+#define CAN_FDR_SC_Msk                        (0x03UL << CAN_FDR_SC_Pos)                              /*!< CAN FDR: SC Mask                        */\r
+#define CAN_FDR_DM_Pos                        14                                                      /*!< CAN FDR: DM Position                    */\r
+#define CAN_FDR_DM_Msk                        (0x03UL << CAN_FDR_DM_Pos)                              /*!< CAN FDR: DM Mask                        */\r
+#define CAN_FDR_RESULT_Pos                    16                                                      /*!< CAN FDR: RESULT Position                */\r
+#define CAN_FDR_RESULT_Msk                    (0x000003ffUL << CAN_FDR_RESULT_Pos)                    /*!< CAN FDR: RESULT Mask                    */\r
+#define CAN_FDR_SUSACK_Pos                    28                                                      /*!< CAN FDR: SUSACK Position                */\r
+#define CAN_FDR_SUSACK_Msk                    (0x01UL << CAN_FDR_SUSACK_Pos)                          /*!< CAN FDR: SUSACK Mask                    */\r
+#define CAN_FDR_SUSREQ_Pos                    29                                                      /*!< CAN FDR: SUSREQ Position                */\r
+#define CAN_FDR_SUSREQ_Msk                    (0x01UL << CAN_FDR_SUSREQ_Pos)                          /*!< CAN FDR: SUSREQ Mask                    */\r
+#define CAN_FDR_ENHW_Pos                      30                                                      /*!< CAN FDR: ENHW Position                  */\r
+#define CAN_FDR_ENHW_Msk                      (0x01UL << CAN_FDR_ENHW_Pos)                            /*!< CAN FDR: ENHW Mask                      */\r
+#define CAN_FDR_DISCLK_Pos                    31                                                      /*!< CAN FDR: DISCLK Position                */\r
+#define CAN_FDR_DISCLK_Msk                    (0x01UL << CAN_FDR_DISCLK_Pos)                          /*!< CAN FDR: DISCLK Mask                    */\r
+\r
+/* ----------------------------------  CAN_LIST  ---------------------------------- */\r
+#define CAN_LIST_BEGIN_Pos                    0                                                       /*!< CAN LIST: BEGIN Position                */\r
+#define CAN_LIST_BEGIN_Msk                    (0x000000ffUL << CAN_LIST_BEGIN_Pos)                    /*!< CAN LIST: BEGIN Mask                    */\r
+#define CAN_LIST_END_Pos                      8                                                       /*!< CAN LIST: END Position                  */\r
+#define CAN_LIST_END_Msk                      (0x000000ffUL << CAN_LIST_END_Pos)                      /*!< CAN LIST: END Mask                      */\r
+#define CAN_LIST_SIZE_Pos                     16                                                      /*!< CAN LIST: SIZE Position                 */\r
+#define CAN_LIST_SIZE_Msk                     (0x000000ffUL << CAN_LIST_SIZE_Pos)                     /*!< CAN LIST: SIZE Mask                     */\r
+#define CAN_LIST_EMPTY_Pos                    24                                                      /*!< CAN LIST: EMPTY Position                */\r
+#define CAN_LIST_EMPTY_Msk                    (0x01UL << CAN_LIST_EMPTY_Pos)                          /*!< CAN LIST: EMPTY Mask                    */\r
+\r
+/* ----------------------------------  CAN_MSPND  --------------------------------- */\r
+#define CAN_MSPND_PND_Pos                     0                                                       /*!< CAN MSPND: PND Position                 */\r
+#define CAN_MSPND_PND_Msk                     (0xffffffffUL << CAN_MSPND_PND_Pos)                     /*!< CAN MSPND: PND Mask                     */\r
+\r
+/* ----------------------------------  CAN_MSID  ---------------------------------- */\r
+#define CAN_MSID_INDEX_Pos                    0                                                       /*!< CAN MSID: INDEX Position                */\r
+#define CAN_MSID_INDEX_Msk                    (0x3fUL << CAN_MSID_INDEX_Pos)                          /*!< CAN MSID: INDEX Mask                    */\r
+\r
+/* ---------------------------------  CAN_MSIMASK  -------------------------------- */\r
+#define CAN_MSIMASK_IM_Pos                    0                                                       /*!< CAN MSIMASK: IM Position                */\r
+#define CAN_MSIMASK_IM_Msk                    (0xffffffffUL << CAN_MSIMASK_IM_Pos)                    /*!< CAN MSIMASK: IM Mask                    */\r
+\r
+/* ---------------------------------  CAN_PANCTR  --------------------------------- */\r
+#define CAN_PANCTR_PANCMD_Pos                 0                                                       /*!< CAN PANCTR: PANCMD Position             */\r
+#define CAN_PANCTR_PANCMD_Msk                 (0x000000ffUL << CAN_PANCTR_PANCMD_Pos)                 /*!< CAN PANCTR: PANCMD Mask                 */\r
+#define CAN_PANCTR_BUSY_Pos                   8                                                       /*!< CAN PANCTR: BUSY Position               */\r
+#define CAN_PANCTR_BUSY_Msk                   (0x01UL << CAN_PANCTR_BUSY_Pos)                         /*!< CAN PANCTR: BUSY Mask                   */\r
+#define CAN_PANCTR_RBUSY_Pos                  9                                                       /*!< CAN PANCTR: RBUSY Position              */\r
+#define CAN_PANCTR_RBUSY_Msk                  (0x01UL << CAN_PANCTR_RBUSY_Pos)                        /*!< CAN PANCTR: RBUSY Mask                  */\r
+#define CAN_PANCTR_PANAR1_Pos                 16                                                      /*!< CAN PANCTR: PANAR1 Position             */\r
+#define CAN_PANCTR_PANAR1_Msk                 (0x000000ffUL << CAN_PANCTR_PANAR1_Pos)                 /*!< CAN PANCTR: PANAR1 Mask                 */\r
+#define CAN_PANCTR_PANAR2_Pos                 24                                                      /*!< CAN PANCTR: PANAR2 Position             */\r
+#define CAN_PANCTR_PANAR2_Msk                 (0x000000ffUL << CAN_PANCTR_PANAR2_Pos)                 /*!< CAN PANCTR: PANAR2 Mask                 */\r
+\r
+/* -----------------------------------  CAN_MCR  ---------------------------------- */\r
+#define CAN_MCR_MPSEL_Pos                     12                                                      /*!< CAN MCR: MPSEL Position                 */\r
+#define CAN_MCR_MPSEL_Msk                     (0x0fUL << CAN_MCR_MPSEL_Pos)                           /*!< CAN MCR: MPSEL Mask                     */\r
+\r
+/* ----------------------------------  CAN_MITR  ---------------------------------- */\r
+#define CAN_MITR_IT_Pos                       0                                                       /*!< CAN MITR: IT Position                   */\r
+#define CAN_MITR_IT_Msk                       (0x000000ffUL << CAN_MITR_IT_Pos)                       /*!< CAN MITR: IT Mask                       */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        Group 'CAN_NODE' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CAN_NODE_NCR  -------------------------------- */\r
+#define CAN_NODE_NCR_INIT_Pos                 0                                                       /*!< CAN_NODE NCR: INIT Position             */\r
+#define CAN_NODE_NCR_INIT_Msk                 (0x01UL << CAN_NODE_NCR_INIT_Pos)                       /*!< CAN_NODE NCR: INIT Mask                 */\r
+#define CAN_NODE_NCR_TRIE_Pos                 1                                                       /*!< CAN_NODE NCR: TRIE Position             */\r
+#define CAN_NODE_NCR_TRIE_Msk                 (0x01UL << CAN_NODE_NCR_TRIE_Pos)                       /*!< CAN_NODE NCR: TRIE Mask                 */\r
+#define CAN_NODE_NCR_LECIE_Pos                2                                                       /*!< CAN_NODE NCR: LECIE Position            */\r
+#define CAN_NODE_NCR_LECIE_Msk                (0x01UL << CAN_NODE_NCR_LECIE_Pos)                      /*!< CAN_NODE NCR: LECIE Mask                */\r
+#define CAN_NODE_NCR_ALIE_Pos                 3                                                       /*!< CAN_NODE NCR: ALIE Position             */\r
+#define CAN_NODE_NCR_ALIE_Msk                 (0x01UL << CAN_NODE_NCR_ALIE_Pos)                       /*!< CAN_NODE NCR: ALIE Mask                 */\r
+#define CAN_NODE_NCR_CANDIS_Pos               4                                                       /*!< CAN_NODE NCR: CANDIS Position           */\r
+#define CAN_NODE_NCR_CANDIS_Msk               (0x01UL << CAN_NODE_NCR_CANDIS_Pos)                     /*!< CAN_NODE NCR: CANDIS Mask               */\r
+#define CAN_NODE_NCR_CCE_Pos                  6                                                       /*!< CAN_NODE NCR: CCE Position              */\r
+#define CAN_NODE_NCR_CCE_Msk                  (0x01UL << CAN_NODE_NCR_CCE_Pos)                        /*!< CAN_NODE NCR: CCE Mask                  */\r
+#define CAN_NODE_NCR_CALM_Pos                 7                                                       /*!< CAN_NODE NCR: CALM Position             */\r
+#define CAN_NODE_NCR_CALM_Msk                 (0x01UL << CAN_NODE_NCR_CALM_Pos)                       /*!< CAN_NODE NCR: CALM Mask                 */\r
+#define CAN_NODE_NCR_SUSEN_Pos                8                                                       /*!< CAN_NODE NCR: SUSEN Position            */\r
+#define CAN_NODE_NCR_SUSEN_Msk                (0x01UL << CAN_NODE_NCR_SUSEN_Pos)                      /*!< CAN_NODE NCR: SUSEN Mask                */\r
+\r
+/* --------------------------------  CAN_NODE_NSR  -------------------------------- */\r
+#define CAN_NODE_NSR_LEC_Pos                  0                                                       /*!< CAN_NODE NSR: LEC Position              */\r
+#define CAN_NODE_NSR_LEC_Msk                  (0x07UL << CAN_NODE_NSR_LEC_Pos)                        /*!< CAN_NODE NSR: LEC Mask                  */\r
+#define CAN_NODE_NSR_TXOK_Pos                 3                                                       /*!< CAN_NODE NSR: TXOK Position             */\r
+#define CAN_NODE_NSR_TXOK_Msk                 (0x01UL << CAN_NODE_NSR_TXOK_Pos)                       /*!< CAN_NODE NSR: TXOK Mask                 */\r
+#define CAN_NODE_NSR_RXOK_Pos                 4                                                       /*!< CAN_NODE NSR: RXOK Position             */\r
+#define CAN_NODE_NSR_RXOK_Msk                 (0x01UL << CAN_NODE_NSR_RXOK_Pos)                       /*!< CAN_NODE NSR: RXOK Mask                 */\r
+#define CAN_NODE_NSR_ALERT_Pos                5                                                       /*!< CAN_NODE NSR: ALERT Position            */\r
+#define CAN_NODE_NSR_ALERT_Msk                (0x01UL << CAN_NODE_NSR_ALERT_Pos)                      /*!< CAN_NODE NSR: ALERT Mask                */\r
+#define CAN_NODE_NSR_EWRN_Pos                 6                                                       /*!< CAN_NODE NSR: EWRN Position             */\r
+#define CAN_NODE_NSR_EWRN_Msk                 (0x01UL << CAN_NODE_NSR_EWRN_Pos)                       /*!< CAN_NODE NSR: EWRN Mask                 */\r
+#define CAN_NODE_NSR_BOFF_Pos                 7                                                       /*!< CAN_NODE NSR: BOFF Position             */\r
+#define CAN_NODE_NSR_BOFF_Msk                 (0x01UL << CAN_NODE_NSR_BOFF_Pos)                       /*!< CAN_NODE NSR: BOFF Mask                 */\r
+#define CAN_NODE_NSR_LLE_Pos                  8                                                       /*!< CAN_NODE NSR: LLE Position              */\r
+#define CAN_NODE_NSR_LLE_Msk                  (0x01UL << CAN_NODE_NSR_LLE_Pos)                        /*!< CAN_NODE NSR: LLE Mask                  */\r
+#define CAN_NODE_NSR_LOE_Pos                  9                                                       /*!< CAN_NODE NSR: LOE Position              */\r
+#define CAN_NODE_NSR_LOE_Msk                  (0x01UL << CAN_NODE_NSR_LOE_Pos)                        /*!< CAN_NODE NSR: LOE Mask                  */\r
+#define CAN_NODE_NSR_SUSACK_Pos               10                                                      /*!< CAN_NODE NSR: SUSACK Position           */\r
+#define CAN_NODE_NSR_SUSACK_Msk               (0x01UL << CAN_NODE_NSR_SUSACK_Pos)                     /*!< CAN_NODE NSR: SUSACK Mask               */\r
+\r
+/* --------------------------------  CAN_NODE_NIPR  ------------------------------- */\r
+#define CAN_NODE_NIPR_ALINP_Pos               0                                                       /*!< CAN_NODE NIPR: ALINP Position           */\r
+#define CAN_NODE_NIPR_ALINP_Msk               (0x07UL << CAN_NODE_NIPR_ALINP_Pos)                     /*!< CAN_NODE NIPR: ALINP Mask               */\r
+#define CAN_NODE_NIPR_LECINP_Pos              4                                                       /*!< CAN_NODE NIPR: LECINP Position          */\r
+#define CAN_NODE_NIPR_LECINP_Msk              (0x07UL << CAN_NODE_NIPR_LECINP_Pos)                    /*!< CAN_NODE NIPR: LECINP Mask              */\r
+#define CAN_NODE_NIPR_TRINP_Pos               8                                                       /*!< CAN_NODE NIPR: TRINP Position           */\r
+#define CAN_NODE_NIPR_TRINP_Msk               (0x07UL << CAN_NODE_NIPR_TRINP_Pos)                     /*!< CAN_NODE NIPR: TRINP Mask               */\r
+#define CAN_NODE_NIPR_CFCINP_Pos              12                                                      /*!< CAN_NODE NIPR: CFCINP Position          */\r
+#define CAN_NODE_NIPR_CFCINP_Msk              (0x07UL << CAN_NODE_NIPR_CFCINP_Pos)                    /*!< CAN_NODE NIPR: CFCINP Mask              */\r
+\r
+/* --------------------------------  CAN_NODE_NPCR  ------------------------------- */\r
+#define CAN_NODE_NPCR_RXSEL_Pos               0                                                       /*!< CAN_NODE NPCR: RXSEL Position           */\r
+#define CAN_NODE_NPCR_RXSEL_Msk               (0x07UL << CAN_NODE_NPCR_RXSEL_Pos)                     /*!< CAN_NODE NPCR: RXSEL Mask               */\r
+#define CAN_NODE_NPCR_LBM_Pos                 8                                                       /*!< CAN_NODE NPCR: LBM Position             */\r
+#define CAN_NODE_NPCR_LBM_Msk                 (0x01UL << CAN_NODE_NPCR_LBM_Pos)                       /*!< CAN_NODE NPCR: LBM Mask                 */\r
+\r
+/* --------------------------------  CAN_NODE_NBTR  ------------------------------- */\r
+#define CAN_NODE_NBTR_BRP_Pos                 0                                                       /*!< CAN_NODE NBTR: BRP Position             */\r
+#define CAN_NODE_NBTR_BRP_Msk                 (0x3fUL << CAN_NODE_NBTR_BRP_Pos)                       /*!< CAN_NODE NBTR: BRP Mask                 */\r
+#define CAN_NODE_NBTR_SJW_Pos                 6                                                       /*!< CAN_NODE NBTR: SJW Position             */\r
+#define CAN_NODE_NBTR_SJW_Msk                 (0x03UL << CAN_NODE_NBTR_SJW_Pos)                       /*!< CAN_NODE NBTR: SJW Mask                 */\r
+#define CAN_NODE_NBTR_TSEG1_Pos               8                                                       /*!< CAN_NODE NBTR: TSEG1 Position           */\r
+#define CAN_NODE_NBTR_TSEG1_Msk               (0x0fUL << CAN_NODE_NBTR_TSEG1_Pos)                     /*!< CAN_NODE NBTR: TSEG1 Mask               */\r
+#define CAN_NODE_NBTR_TSEG2_Pos               12                                                      /*!< CAN_NODE NBTR: TSEG2 Position           */\r
+#define CAN_NODE_NBTR_TSEG2_Msk               (0x07UL << CAN_NODE_NBTR_TSEG2_Pos)                     /*!< CAN_NODE NBTR: TSEG2 Mask               */\r
+#define CAN_NODE_NBTR_DIV8_Pos                15                                                      /*!< CAN_NODE NBTR: DIV8 Position            */\r
+#define CAN_NODE_NBTR_DIV8_Msk                (0x01UL << CAN_NODE_NBTR_DIV8_Pos)                      /*!< CAN_NODE NBTR: DIV8 Mask                */\r
+\r
+/* -------------------------------  CAN_NODE_NECNT  ------------------------------- */\r
+#define CAN_NODE_NECNT_REC_Pos                0                                                       /*!< CAN_NODE NECNT: REC Position            */\r
+#define CAN_NODE_NECNT_REC_Msk                (0x000000ffUL << CAN_NODE_NECNT_REC_Pos)                /*!< CAN_NODE NECNT: REC Mask                */\r
+#define CAN_NODE_NECNT_TEC_Pos                8                                                       /*!< CAN_NODE NECNT: TEC Position            */\r
+#define CAN_NODE_NECNT_TEC_Msk                (0x000000ffUL << CAN_NODE_NECNT_TEC_Pos)                /*!< CAN_NODE NECNT: TEC Mask                */\r
+#define CAN_NODE_NECNT_EWRNLVL_Pos            16                                                      /*!< CAN_NODE NECNT: EWRNLVL Position        */\r
+#define CAN_NODE_NECNT_EWRNLVL_Msk            (0x000000ffUL << CAN_NODE_NECNT_EWRNLVL_Pos)            /*!< CAN_NODE NECNT: EWRNLVL Mask            */\r
+#define CAN_NODE_NECNT_LETD_Pos               24                                                      /*!< CAN_NODE NECNT: LETD Position           */\r
+#define CAN_NODE_NECNT_LETD_Msk               (0x01UL << CAN_NODE_NECNT_LETD_Pos)                     /*!< CAN_NODE NECNT: LETD Mask               */\r
+#define CAN_NODE_NECNT_LEINC_Pos              25                                                      /*!< CAN_NODE NECNT: LEINC Position          */\r
+#define CAN_NODE_NECNT_LEINC_Msk              (0x01UL << CAN_NODE_NECNT_LEINC_Pos)                    /*!< CAN_NODE NECNT: LEINC Mask              */\r
+\r
+/* --------------------------------  CAN_NODE_NFCR  ------------------------------- */\r
+#define CAN_NODE_NFCR_CFC_Pos                 0                                                       /*!< CAN_NODE NFCR: CFC Position             */\r
+#define CAN_NODE_NFCR_CFC_Msk                 (0x0000ffffUL << CAN_NODE_NFCR_CFC_Pos)                 /*!< CAN_NODE NFCR: CFC Mask                 */\r
+#define CAN_NODE_NFCR_CFSEL_Pos               16                                                      /*!< CAN_NODE NFCR: CFSEL Position           */\r
+#define CAN_NODE_NFCR_CFSEL_Msk               (0x07UL << CAN_NODE_NFCR_CFSEL_Pos)                     /*!< CAN_NODE NFCR: CFSEL Mask               */\r
+#define CAN_NODE_NFCR_CFMOD_Pos               19                                                      /*!< CAN_NODE NFCR: CFMOD Position           */\r
+#define CAN_NODE_NFCR_CFMOD_Msk               (0x03UL << CAN_NODE_NFCR_CFMOD_Pos)                     /*!< CAN_NODE NFCR: CFMOD Mask               */\r
+#define CAN_NODE_NFCR_CFCIE_Pos               22                                                      /*!< CAN_NODE NFCR: CFCIE Position           */\r
+#define CAN_NODE_NFCR_CFCIE_Msk               (0x01UL << CAN_NODE_NFCR_CFCIE_Pos)                     /*!< CAN_NODE NFCR: CFCIE Mask               */\r
+#define CAN_NODE_NFCR_CFCOV_Pos               23                                                      /*!< CAN_NODE NFCR: CFCOV Position           */\r
+#define CAN_NODE_NFCR_CFCOV_Msk               (0x01UL << CAN_NODE_NFCR_CFCOV_Pos)                     /*!< CAN_NODE NFCR: CFCOV Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'CAN_MO' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CAN_MO_MOFCR  -------------------------------- */\r
+#define CAN_MO_MOFCR_MMC_Pos                  0                                                       /*!< CAN_MO MOFCR: MMC Position              */\r
+#define CAN_MO_MOFCR_MMC_Msk                  (0x0fUL << CAN_MO_MOFCR_MMC_Pos)                        /*!< CAN_MO MOFCR: MMC Mask                  */\r
+#define CAN_MO_MOFCR_GDFS_Pos                 8                                                       /*!< CAN_MO MOFCR: GDFS Position             */\r
+#define CAN_MO_MOFCR_GDFS_Msk                 (0x01UL << CAN_MO_MOFCR_GDFS_Pos)                       /*!< CAN_MO MOFCR: GDFS Mask                 */\r
+#define CAN_MO_MOFCR_IDC_Pos                  9                                                       /*!< CAN_MO MOFCR: IDC Position              */\r
+#define CAN_MO_MOFCR_IDC_Msk                  (0x01UL << CAN_MO_MOFCR_IDC_Pos)                        /*!< CAN_MO MOFCR: IDC Mask                  */\r
+#define CAN_MO_MOFCR_DLCC_Pos                 10                                                      /*!< CAN_MO MOFCR: DLCC Position             */\r
+#define CAN_MO_MOFCR_DLCC_Msk                 (0x01UL << CAN_MO_MOFCR_DLCC_Pos)                       /*!< CAN_MO MOFCR: DLCC Mask                 */\r
+#define CAN_MO_MOFCR_DATC_Pos                 11                                                      /*!< CAN_MO MOFCR: DATC Position             */\r
+#define CAN_MO_MOFCR_DATC_Msk                 (0x01UL << CAN_MO_MOFCR_DATC_Pos)                       /*!< CAN_MO MOFCR: DATC Mask                 */\r
+#define CAN_MO_MOFCR_RXIE_Pos                 16                                                      /*!< CAN_MO MOFCR: RXIE Position             */\r
+#define CAN_MO_MOFCR_RXIE_Msk                 (0x01UL << CAN_MO_MOFCR_RXIE_Pos)                       /*!< CAN_MO MOFCR: RXIE Mask                 */\r
+#define CAN_MO_MOFCR_TXIE_Pos                 17                                                      /*!< CAN_MO MOFCR: TXIE Position             */\r
+#define CAN_MO_MOFCR_TXIE_Msk                 (0x01UL << CAN_MO_MOFCR_TXIE_Pos)                       /*!< CAN_MO MOFCR: TXIE Mask                 */\r
+#define CAN_MO_MOFCR_OVIE_Pos                 18                                                      /*!< CAN_MO MOFCR: OVIE Position             */\r
+#define CAN_MO_MOFCR_OVIE_Msk                 (0x01UL << CAN_MO_MOFCR_OVIE_Pos)                       /*!< CAN_MO MOFCR: OVIE Mask                 */\r
+#define CAN_MO_MOFCR_FRREN_Pos                20                                                      /*!< CAN_MO MOFCR: FRREN Position            */\r
+#define CAN_MO_MOFCR_FRREN_Msk                (0x01UL << CAN_MO_MOFCR_FRREN_Pos)                      /*!< CAN_MO MOFCR: FRREN Mask                */\r
+#define CAN_MO_MOFCR_RMM_Pos                  21                                                      /*!< CAN_MO MOFCR: RMM Position              */\r
+#define CAN_MO_MOFCR_RMM_Msk                  (0x01UL << CAN_MO_MOFCR_RMM_Pos)                        /*!< CAN_MO MOFCR: RMM Mask                  */\r
+#define CAN_MO_MOFCR_SDT_Pos                  22                                                      /*!< CAN_MO MOFCR: SDT Position              */\r
+#define CAN_MO_MOFCR_SDT_Msk                  (0x01UL << CAN_MO_MOFCR_SDT_Pos)                        /*!< CAN_MO MOFCR: SDT Mask                  */\r
+#define CAN_MO_MOFCR_STT_Pos                  23                                                      /*!< CAN_MO MOFCR: STT Position              */\r
+#define CAN_MO_MOFCR_STT_Msk                  (0x01UL << CAN_MO_MOFCR_STT_Pos)                        /*!< CAN_MO MOFCR: STT Mask                  */\r
+#define CAN_MO_MOFCR_DLC_Pos                  24                                                      /*!< CAN_MO MOFCR: DLC Position              */\r
+#define CAN_MO_MOFCR_DLC_Msk                  (0x0fUL << CAN_MO_MOFCR_DLC_Pos)                        /*!< CAN_MO MOFCR: DLC Mask                  */\r
+\r
+/* --------------------------------  CAN_MO_MOFGPR  ------------------------------- */\r
+#define CAN_MO_MOFGPR_BOT_Pos                 0                                                       /*!< CAN_MO MOFGPR: BOT Position             */\r
+#define CAN_MO_MOFGPR_BOT_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_BOT_Pos)                 /*!< CAN_MO MOFGPR: BOT Mask                 */\r
+#define CAN_MO_MOFGPR_TOP_Pos                 8                                                       /*!< CAN_MO MOFGPR: TOP Position             */\r
+#define CAN_MO_MOFGPR_TOP_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_TOP_Pos)                 /*!< CAN_MO MOFGPR: TOP Mask                 */\r
+#define CAN_MO_MOFGPR_CUR_Pos                 16                                                      /*!< CAN_MO MOFGPR: CUR Position             */\r
+#define CAN_MO_MOFGPR_CUR_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_CUR_Pos)                 /*!< CAN_MO MOFGPR: CUR Mask                 */\r
+#define CAN_MO_MOFGPR_SEL_Pos                 24                                                      /*!< CAN_MO MOFGPR: SEL Position             */\r
+#define CAN_MO_MOFGPR_SEL_Msk                 (0x000000ffUL << CAN_MO_MOFGPR_SEL_Pos)                 /*!< CAN_MO MOFGPR: SEL Mask                 */\r
+\r
+/* --------------------------------  CAN_MO_MOIPR  -------------------------------- */\r
+#define CAN_MO_MOIPR_RXINP_Pos                0                                                       /*!< CAN_MO MOIPR: RXINP Position            */\r
+#define CAN_MO_MOIPR_RXINP_Msk                (0x07UL << CAN_MO_MOIPR_RXINP_Pos)                      /*!< CAN_MO MOIPR: RXINP Mask                */\r
+#define CAN_MO_MOIPR_TXINP_Pos                4                                                       /*!< CAN_MO MOIPR: TXINP Position            */\r
+#define CAN_MO_MOIPR_TXINP_Msk                (0x07UL << CAN_MO_MOIPR_TXINP_Pos)                      /*!< CAN_MO MOIPR: TXINP Mask                */\r
+#define CAN_MO_MOIPR_MPN_Pos                  8                                                       /*!< CAN_MO MOIPR: MPN Position              */\r
+#define CAN_MO_MOIPR_MPN_Msk                  (0x000000ffUL << CAN_MO_MOIPR_MPN_Pos)                  /*!< CAN_MO MOIPR: MPN Mask                  */\r
+#define CAN_MO_MOIPR_CFCVAL_Pos               16                                                      /*!< CAN_MO MOIPR: CFCVAL Position           */\r
+#define CAN_MO_MOIPR_CFCVAL_Msk               (0x0000ffffUL << CAN_MO_MOIPR_CFCVAL_Pos)               /*!< CAN_MO MOIPR: CFCVAL Mask               */\r
+\r
+/* --------------------------------  CAN_MO_MOAMR  -------------------------------- */\r
+#define CAN_MO_MOAMR_AM_Pos                   0                                                       /*!< CAN_MO MOAMR: AM Position               */\r
+#define CAN_MO_MOAMR_AM_Msk                   (0x1fffffffUL << CAN_MO_MOAMR_AM_Pos)                   /*!< CAN_MO MOAMR: AM Mask                   */\r
+#define CAN_MO_MOAMR_MIDE_Pos                 29                                                      /*!< CAN_MO MOAMR: MIDE Position             */\r
+#define CAN_MO_MOAMR_MIDE_Msk                 (0x01UL << CAN_MO_MOAMR_MIDE_Pos)                       /*!< CAN_MO MOAMR: MIDE Mask                 */\r
+\r
+/* -------------------------------  CAN_MO_MODATAL  ------------------------------- */\r
+#define CAN_MO_MODATAL_DB0_Pos                0                                                       /*!< CAN_MO MODATAL: DB0 Position            */\r
+#define CAN_MO_MODATAL_DB0_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB0_Pos)                /*!< CAN_MO MODATAL: DB0 Mask                */\r
+#define CAN_MO_MODATAL_DB1_Pos                8                                                       /*!< CAN_MO MODATAL: DB1 Position            */\r
+#define CAN_MO_MODATAL_DB1_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB1_Pos)                /*!< CAN_MO MODATAL: DB1 Mask                */\r
+#define CAN_MO_MODATAL_DB2_Pos                16                                                      /*!< CAN_MO MODATAL: DB2 Position            */\r
+#define CAN_MO_MODATAL_DB2_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB2_Pos)                /*!< CAN_MO MODATAL: DB2 Mask                */\r
+#define CAN_MO_MODATAL_DB3_Pos                24                                                      /*!< CAN_MO MODATAL: DB3 Position            */\r
+#define CAN_MO_MODATAL_DB3_Msk                (0x000000ffUL << CAN_MO_MODATAL_DB3_Pos)                /*!< CAN_MO MODATAL: DB3 Mask                */\r
+\r
+/* -------------------------------  CAN_MO_MODATAH  ------------------------------- */\r
+#define CAN_MO_MODATAH_DB4_Pos                0                                                       /*!< CAN_MO MODATAH: DB4 Position            */\r
+#define CAN_MO_MODATAH_DB4_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB4_Pos)                /*!< CAN_MO MODATAH: DB4 Mask                */\r
+#define CAN_MO_MODATAH_DB5_Pos                8                                                       /*!< CAN_MO MODATAH: DB5 Position            */\r
+#define CAN_MO_MODATAH_DB5_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB5_Pos)                /*!< CAN_MO MODATAH: DB5 Mask                */\r
+#define CAN_MO_MODATAH_DB6_Pos                16                                                      /*!< CAN_MO MODATAH: DB6 Position            */\r
+#define CAN_MO_MODATAH_DB6_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB6_Pos)                /*!< CAN_MO MODATAH: DB6 Mask                */\r
+#define CAN_MO_MODATAH_DB7_Pos                24                                                      /*!< CAN_MO MODATAH: DB7 Position            */\r
+#define CAN_MO_MODATAH_DB7_Msk                (0x000000ffUL << CAN_MO_MODATAH_DB7_Pos)                /*!< CAN_MO MODATAH: DB7 Mask                */\r
+\r
+/* ---------------------------------  CAN_MO_MOAR  -------------------------------- */\r
+#define CAN_MO_MOAR_ID_Pos                    0                                                       /*!< CAN_MO MOAR: ID Position                */\r
+#define CAN_MO_MOAR_ID_Msk                    (0x1fffffffUL << CAN_MO_MOAR_ID_Pos)                    /*!< CAN_MO MOAR: ID Mask                    */\r
+#define CAN_MO_MOAR_IDE_Pos                   29                                                      /*!< CAN_MO MOAR: IDE Position               */\r
+#define CAN_MO_MOAR_IDE_Msk                   (0x01UL << CAN_MO_MOAR_IDE_Pos)                         /*!< CAN_MO MOAR: IDE Mask                   */\r
+#define CAN_MO_MOAR_PRI_Pos                   30                                                      /*!< CAN_MO MOAR: PRI Position               */\r
+#define CAN_MO_MOAR_PRI_Msk                   (0x03UL << CAN_MO_MOAR_PRI_Pos)                         /*!< CAN_MO MOAR: PRI Mask                   */\r
+\r
+/* --------------------------------  CAN_MO_MOCTR  -------------------------------- */\r
+#define CAN_MO_MOCTR_RESRXPND_Pos             0                                                       /*!< CAN_MO MOCTR: RESRXPND Position         */\r
+#define CAN_MO_MOCTR_RESRXPND_Msk             (0x01UL << CAN_MO_MOCTR_RESRXPND_Pos)                   /*!< CAN_MO MOCTR: RESRXPND Mask             */\r
+#define CAN_MO_MOCTR_RESTXPND_Pos             1                                                       /*!< CAN_MO MOCTR: RESTXPND Position         */\r
+#define CAN_MO_MOCTR_RESTXPND_Msk             (0x01UL << CAN_MO_MOCTR_RESTXPND_Pos)                   /*!< CAN_MO MOCTR: RESTXPND Mask             */\r
+#define CAN_MO_MOCTR_RESRXUPD_Pos             2                                                       /*!< CAN_MO MOCTR: RESRXUPD Position         */\r
+#define CAN_MO_MOCTR_RESRXUPD_Msk             (0x01UL << CAN_MO_MOCTR_RESRXUPD_Pos)                   /*!< CAN_MO MOCTR: RESRXUPD Mask             */\r
+#define CAN_MO_MOCTR_RESNEWDAT_Pos            3                                                       /*!< CAN_MO MOCTR: RESNEWDAT Position        */\r
+#define CAN_MO_MOCTR_RESNEWDAT_Msk            (0x01UL << CAN_MO_MOCTR_RESNEWDAT_Pos)                  /*!< CAN_MO MOCTR: RESNEWDAT Mask            */\r
+#define CAN_MO_MOCTR_RESMSGLST_Pos            4                                                       /*!< CAN_MO MOCTR: RESMSGLST Position        */\r
+#define CAN_MO_MOCTR_RESMSGLST_Msk            (0x01UL << CAN_MO_MOCTR_RESMSGLST_Pos)                  /*!< CAN_MO MOCTR: RESMSGLST Mask            */\r
+#define CAN_MO_MOCTR_RESMSGVAL_Pos            5                                                       /*!< CAN_MO MOCTR: RESMSGVAL Position        */\r
+#define CAN_MO_MOCTR_RESMSGVAL_Msk            (0x01UL << CAN_MO_MOCTR_RESMSGVAL_Pos)                  /*!< CAN_MO MOCTR: RESMSGVAL Mask            */\r
+#define CAN_MO_MOCTR_RESRTSEL_Pos             6                                                       /*!< CAN_MO MOCTR: RESRTSEL Position         */\r
+#define CAN_MO_MOCTR_RESRTSEL_Msk             (0x01UL << CAN_MO_MOCTR_RESRTSEL_Pos)                   /*!< CAN_MO MOCTR: RESRTSEL Mask             */\r
+#define CAN_MO_MOCTR_RESRXEN_Pos              7                                                       /*!< CAN_MO MOCTR: RESRXEN Position          */\r
+#define CAN_MO_MOCTR_RESRXEN_Msk              (0x01UL << CAN_MO_MOCTR_RESRXEN_Pos)                    /*!< CAN_MO MOCTR: RESRXEN Mask              */\r
+#define CAN_MO_MOCTR_RESTXRQ_Pos              8                                                       /*!< CAN_MO MOCTR: RESTXRQ Position          */\r
+#define CAN_MO_MOCTR_RESTXRQ_Msk              (0x01UL << CAN_MO_MOCTR_RESTXRQ_Pos)                    /*!< CAN_MO MOCTR: RESTXRQ Mask              */\r
+#define CAN_MO_MOCTR_RESTXEN0_Pos             9                                                       /*!< CAN_MO MOCTR: RESTXEN0 Position         */\r
+#define CAN_MO_MOCTR_RESTXEN0_Msk             (0x01UL << CAN_MO_MOCTR_RESTXEN0_Pos)                   /*!< CAN_MO MOCTR: RESTXEN0 Mask             */\r
+#define CAN_MO_MOCTR_RESTXEN1_Pos             10                                                      /*!< CAN_MO MOCTR: RESTXEN1 Position         */\r
+#define CAN_MO_MOCTR_RESTXEN1_Msk             (0x01UL << CAN_MO_MOCTR_RESTXEN1_Pos)                   /*!< CAN_MO MOCTR: RESTXEN1 Mask             */\r
+#define CAN_MO_MOCTR_RESDIR_Pos               11                                                      /*!< CAN_MO MOCTR: RESDIR Position           */\r
+#define CAN_MO_MOCTR_RESDIR_Msk               (0x01UL << CAN_MO_MOCTR_RESDIR_Pos)                     /*!< CAN_MO MOCTR: RESDIR Mask               */\r
+#define CAN_MO_MOCTR_SETRXPND_Pos             16                                                      /*!< CAN_MO MOCTR: SETRXPND Position         */\r
+#define CAN_MO_MOCTR_SETRXPND_Msk             (0x01UL << CAN_MO_MOCTR_SETRXPND_Pos)                   /*!< CAN_MO MOCTR: SETRXPND Mask             */\r
+#define CAN_MO_MOCTR_SETTXPND_Pos             17                                                      /*!< CAN_MO MOCTR: SETTXPND Position         */\r
+#define CAN_MO_MOCTR_SETTXPND_Msk             (0x01UL << CAN_MO_MOCTR_SETTXPND_Pos)                   /*!< CAN_MO MOCTR: SETTXPND Mask             */\r
+#define CAN_MO_MOCTR_SETRXUPD_Pos             18                                                      /*!< CAN_MO MOCTR: SETRXUPD Position         */\r
+#define CAN_MO_MOCTR_SETRXUPD_Msk             (0x01UL << CAN_MO_MOCTR_SETRXUPD_Pos)                   /*!< CAN_MO MOCTR: SETRXUPD Mask             */\r
+#define CAN_MO_MOCTR_SETNEWDAT_Pos            19                                                      /*!< CAN_MO MOCTR: SETNEWDAT Position        */\r
+#define CAN_MO_MOCTR_SETNEWDAT_Msk            (0x01UL << CAN_MO_MOCTR_SETNEWDAT_Pos)                  /*!< CAN_MO MOCTR: SETNEWDAT Mask            */\r
+#define CAN_MO_MOCTR_SETMSGLST_Pos            20                                                      /*!< CAN_MO MOCTR: SETMSGLST Position        */\r
+#define CAN_MO_MOCTR_SETMSGLST_Msk            (0x01UL << CAN_MO_MOCTR_SETMSGLST_Pos)                  /*!< CAN_MO MOCTR: SETMSGLST Mask            */\r
+#define CAN_MO_MOCTR_SETMSGVAL_Pos            21                                                      /*!< CAN_MO MOCTR: SETMSGVAL Position        */\r
+#define CAN_MO_MOCTR_SETMSGVAL_Msk            (0x01UL << CAN_MO_MOCTR_SETMSGVAL_Pos)                  /*!< CAN_MO MOCTR: SETMSGVAL Mask            */\r
+#define CAN_MO_MOCTR_SETRTSEL_Pos             22                                                      /*!< CAN_MO MOCTR: SETRTSEL Position         */\r
+#define CAN_MO_MOCTR_SETRTSEL_Msk             (0x01UL << CAN_MO_MOCTR_SETRTSEL_Pos)                   /*!< CAN_MO MOCTR: SETRTSEL Mask             */\r
+#define CAN_MO_MOCTR_SETRXEN_Pos              23                                                      /*!< CAN_MO MOCTR: SETRXEN Position          */\r
+#define CAN_MO_MOCTR_SETRXEN_Msk              (0x01UL << CAN_MO_MOCTR_SETRXEN_Pos)                    /*!< CAN_MO MOCTR: SETRXEN Mask              */\r
+#define CAN_MO_MOCTR_SETTXRQ_Pos              24                                                      /*!< CAN_MO MOCTR: SETTXRQ Position          */\r
+#define CAN_MO_MOCTR_SETTXRQ_Msk              (0x01UL << CAN_MO_MOCTR_SETTXRQ_Pos)                    /*!< CAN_MO MOCTR: SETTXRQ Mask              */\r
+#define CAN_MO_MOCTR_SETTXEN0_Pos             25                                                      /*!< CAN_MO MOCTR: SETTXEN0 Position         */\r
+#define CAN_MO_MOCTR_SETTXEN0_Msk             (0x01UL << CAN_MO_MOCTR_SETTXEN0_Pos)                   /*!< CAN_MO MOCTR: SETTXEN0 Mask             */\r
+#define CAN_MO_MOCTR_SETTXEN1_Pos             26                                                      /*!< CAN_MO MOCTR: SETTXEN1 Position         */\r
+#define CAN_MO_MOCTR_SETTXEN1_Msk             (0x01UL << CAN_MO_MOCTR_SETTXEN1_Pos)                   /*!< CAN_MO MOCTR: SETTXEN1 Mask             */\r
+#define CAN_MO_MOCTR_SETDIR_Pos               27                                                      /*!< CAN_MO MOCTR: SETDIR Position           */\r
+#define CAN_MO_MOCTR_SETDIR_Msk               (0x01UL << CAN_MO_MOCTR_SETDIR_Pos)                     /*!< CAN_MO MOCTR: SETDIR Mask               */\r
+\r
+/* --------------------------------  CAN_MO_MOSTAT  ------------------------------- */\r
+#define CAN_MO_MOSTAT_RXPND_Pos               0                                                       /*!< CAN_MO MOSTAT: RXPND Position           */\r
+#define CAN_MO_MOSTAT_RXPND_Msk               (0x01UL << CAN_MO_MOSTAT_RXPND_Pos)                     /*!< CAN_MO MOSTAT: RXPND Mask               */\r
+#define CAN_MO_MOSTAT_TXPND_Pos               1                                                       /*!< CAN_MO MOSTAT: TXPND Position           */\r
+#define CAN_MO_MOSTAT_TXPND_Msk               (0x01UL << CAN_MO_MOSTAT_TXPND_Pos)                     /*!< CAN_MO MOSTAT: TXPND Mask               */\r
+#define CAN_MO_MOSTAT_RXUPD_Pos               2                                                       /*!< CAN_MO MOSTAT: RXUPD Position           */\r
+#define CAN_MO_MOSTAT_RXUPD_Msk               (0x01UL << CAN_MO_MOSTAT_RXUPD_Pos)                     /*!< CAN_MO MOSTAT: RXUPD Mask               */\r
+#define CAN_MO_MOSTAT_NEWDAT_Pos              3                                                       /*!< CAN_MO MOSTAT: NEWDAT Position          */\r
+#define CAN_MO_MOSTAT_NEWDAT_Msk              (0x01UL << CAN_MO_MOSTAT_NEWDAT_Pos)                    /*!< CAN_MO MOSTAT: NEWDAT Mask              */\r
+#define CAN_MO_MOSTAT_MSGLST_Pos              4                                                       /*!< CAN_MO MOSTAT: MSGLST Position          */\r
+#define CAN_MO_MOSTAT_MSGLST_Msk              (0x01UL << CAN_MO_MOSTAT_MSGLST_Pos)                    /*!< CAN_MO MOSTAT: MSGLST Mask              */\r
+#define CAN_MO_MOSTAT_MSGVAL_Pos              5                                                       /*!< CAN_MO MOSTAT: MSGVAL Position          */\r
+#define CAN_MO_MOSTAT_MSGVAL_Msk              (0x01UL << CAN_MO_MOSTAT_MSGVAL_Pos)                    /*!< CAN_MO MOSTAT: MSGVAL Mask              */\r
+#define CAN_MO_MOSTAT_RTSEL_Pos               6                                                       /*!< CAN_MO MOSTAT: RTSEL Position           */\r
+#define CAN_MO_MOSTAT_RTSEL_Msk               (0x01UL << CAN_MO_MOSTAT_RTSEL_Pos)                     /*!< CAN_MO MOSTAT: RTSEL Mask               */\r
+#define CAN_MO_MOSTAT_RXEN_Pos                7                                                       /*!< CAN_MO MOSTAT: RXEN Position            */\r
+#define CAN_MO_MOSTAT_RXEN_Msk                (0x01UL << CAN_MO_MOSTAT_RXEN_Pos)                      /*!< CAN_MO MOSTAT: RXEN Mask                */\r
+#define CAN_MO_MOSTAT_TXRQ_Pos                8                                                       /*!< CAN_MO MOSTAT: TXRQ Position            */\r
+#define CAN_MO_MOSTAT_TXRQ_Msk                (0x01UL << CAN_MO_MOSTAT_TXRQ_Pos)                      /*!< CAN_MO MOSTAT: TXRQ Mask                */\r
+#define CAN_MO_MOSTAT_TXEN0_Pos               9                                                       /*!< CAN_MO MOSTAT: TXEN0 Position           */\r
+#define CAN_MO_MOSTAT_TXEN0_Msk               (0x01UL << CAN_MO_MOSTAT_TXEN0_Pos)                     /*!< CAN_MO MOSTAT: TXEN0 Mask               */\r
+#define CAN_MO_MOSTAT_TXEN1_Pos               10                                                      /*!< CAN_MO MOSTAT: TXEN1 Position           */\r
+#define CAN_MO_MOSTAT_TXEN1_Msk               (0x01UL << CAN_MO_MOSTAT_TXEN1_Pos)                     /*!< CAN_MO MOSTAT: TXEN1 Mask               */\r
+#define CAN_MO_MOSTAT_DIR_Pos                 11                                                      /*!< CAN_MO MOSTAT: DIR Position             */\r
+#define CAN_MO_MOSTAT_DIR_Msk                 (0x01UL << CAN_MO_MOSTAT_DIR_Pos)                       /*!< CAN_MO MOSTAT: DIR Mask                 */\r
+#define CAN_MO_MOSTAT_LIST_Pos                12                                                      /*!< CAN_MO MOSTAT: LIST Position            */\r
+#define CAN_MO_MOSTAT_LIST_Msk                (0x0fUL << CAN_MO_MOSTAT_LIST_Pos)                      /*!< CAN_MO MOSTAT: LIST Mask                */\r
+#define CAN_MO_MOSTAT_PPREV_Pos               16                                                      /*!< CAN_MO MOSTAT: PPREV Position           */\r
+#define CAN_MO_MOSTAT_PPREV_Msk               (0x000000ffUL << CAN_MO_MOSTAT_PPREV_Pos)               /*!< CAN_MO MOSTAT: PPREV Mask               */\r
+#define CAN_MO_MOSTAT_PNEXT_Pos               24                                                      /*!< CAN_MO MOSTAT: PNEXT Position           */\r
+#define CAN_MO_MOSTAT_PNEXT_Msk               (0x000000ffUL << CAN_MO_MOSTAT_PNEXT_Pos)               /*!< CAN_MO MOSTAT: PNEXT Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'VADC' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  VADC_CLC  ---------------------------------- */\r
+#define VADC_CLC_DISR_Pos                     0                                                       /*!< VADC CLC: DISR Position                 */\r
+#define VADC_CLC_DISR_Msk                     (0x01UL << VADC_CLC_DISR_Pos)                           /*!< VADC CLC: DISR Mask                     */\r
+#define VADC_CLC_DISS_Pos                     1                                                       /*!< VADC CLC: DISS Position                 */\r
+#define VADC_CLC_DISS_Msk                     (0x01UL << VADC_CLC_DISS_Pos)                           /*!< VADC CLC: DISS Mask                     */\r
+#define VADC_CLC_EDIS_Pos                     3                                                       /*!< VADC CLC: EDIS Position                 */\r
+#define VADC_CLC_EDIS_Msk                     (0x01UL << VADC_CLC_EDIS_Pos)                           /*!< VADC CLC: EDIS Mask                     */\r
+\r
+/* -----------------------------------  VADC_ID  ---------------------------------- */\r
+#define VADC_ID_MOD_REV_Pos                   0                                                       /*!< VADC ID: MOD_REV Position               */\r
+#define VADC_ID_MOD_REV_Msk                   (0x000000ffUL << VADC_ID_MOD_REV_Pos)                   /*!< VADC ID: MOD_REV Mask                   */\r
+#define VADC_ID_MOD_TYPE_Pos                  8                                                       /*!< VADC ID: MOD_TYPE Position              */\r
+#define VADC_ID_MOD_TYPE_Msk                  (0x000000ffUL << VADC_ID_MOD_TYPE_Pos)                  /*!< VADC ID: MOD_TYPE Mask                  */\r
+#define VADC_ID_MOD_NUMBER_Pos                16                                                      /*!< VADC ID: MOD_NUMBER Position            */\r
+#define VADC_ID_MOD_NUMBER_Msk                (0x0000ffffUL << VADC_ID_MOD_NUMBER_Pos)                /*!< VADC ID: MOD_NUMBER Mask                */\r
+\r
+/* ----------------------------------  VADC_OCS  ---------------------------------- */\r
+#define VADC_OCS_TGS_Pos                      0                                                       /*!< VADC OCS: TGS Position                  */\r
+#define VADC_OCS_TGS_Msk                      (0x03UL << VADC_OCS_TGS_Pos)                            /*!< VADC OCS: TGS Mask                      */\r
+#define VADC_OCS_TGB_Pos                      2                                                       /*!< VADC OCS: TGB Position                  */\r
+#define VADC_OCS_TGB_Msk                      (0x01UL << VADC_OCS_TGB_Pos)                            /*!< VADC OCS: TGB Mask                      */\r
+#define VADC_OCS_TG_P_Pos                     3                                                       /*!< VADC OCS: TG_P Position                 */\r
+#define VADC_OCS_TG_P_Msk                     (0x01UL << VADC_OCS_TG_P_Pos)                           /*!< VADC OCS: TG_P Mask                     */\r
+#define VADC_OCS_SUS_Pos                      24                                                      /*!< VADC OCS: SUS Position                  */\r
+#define VADC_OCS_SUS_Msk                      (0x0fUL << VADC_OCS_SUS_Pos)                            /*!< VADC OCS: SUS Mask                      */\r
+#define VADC_OCS_SUS_P_Pos                    28                                                      /*!< VADC OCS: SUS_P Position                */\r
+#define VADC_OCS_SUS_P_Msk                    (0x01UL << VADC_OCS_SUS_P_Pos)                          /*!< VADC OCS: SUS_P Mask                    */\r
+#define VADC_OCS_SUSSTA_Pos                   29                                                      /*!< VADC OCS: SUSSTA Position               */\r
+#define VADC_OCS_SUSSTA_Msk                   (0x01UL << VADC_OCS_SUSSTA_Pos)                         /*!< VADC OCS: SUSSTA Mask                   */\r
+\r
+/* --------------------------------  VADC_GLOBCFG  -------------------------------- */\r
+#define VADC_GLOBCFG_DIVA_Pos                 0                                                       /*!< VADC GLOBCFG: DIVA Position             */\r
+#define VADC_GLOBCFG_DIVA_Msk                 (0x1fUL << VADC_GLOBCFG_DIVA_Pos)                       /*!< VADC GLOBCFG: DIVA Mask                 */\r
+#define VADC_GLOBCFG_DCMSB_Pos                7                                                       /*!< VADC GLOBCFG: DCMSB Position            */\r
+#define VADC_GLOBCFG_DCMSB_Msk                (0x01UL << VADC_GLOBCFG_DCMSB_Pos)                      /*!< VADC GLOBCFG: DCMSB Mask                */\r
+#define VADC_GLOBCFG_DIVD_Pos                 8                                                       /*!< VADC GLOBCFG: DIVD Position             */\r
+#define VADC_GLOBCFG_DIVD_Msk                 (0x03UL << VADC_GLOBCFG_DIVD_Pos)                       /*!< VADC GLOBCFG: DIVD Mask                 */\r
+#define VADC_GLOBCFG_DIVWC_Pos                15                                                      /*!< VADC GLOBCFG: DIVWC Position            */\r
+#define VADC_GLOBCFG_DIVWC_Msk                (0x01UL << VADC_GLOBCFG_DIVWC_Pos)                      /*!< VADC GLOBCFG: DIVWC Mask                */\r
+#define VADC_GLOBCFG_DPCAL0_Pos               16                                                      /*!< VADC GLOBCFG: DPCAL0 Position           */\r
+#define VADC_GLOBCFG_DPCAL0_Msk               (0x01UL << VADC_GLOBCFG_DPCAL0_Pos)                     /*!< VADC GLOBCFG: DPCAL0 Mask               */\r
+#define VADC_GLOBCFG_DPCAL1_Pos               17                                                      /*!< VADC GLOBCFG: DPCAL1 Position           */\r
+#define VADC_GLOBCFG_DPCAL1_Msk               (0x01UL << VADC_GLOBCFG_DPCAL1_Pos)                     /*!< VADC GLOBCFG: DPCAL1 Mask               */\r
+#define VADC_GLOBCFG_DPCAL2_Pos               18                                                      /*!< VADC GLOBCFG: DPCAL2 Position           */\r
+#define VADC_GLOBCFG_DPCAL2_Msk               (0x01UL << VADC_GLOBCFG_DPCAL2_Pos)                     /*!< VADC GLOBCFG: DPCAL2 Mask               */\r
+#define VADC_GLOBCFG_DPCAL3_Pos               19                                                      /*!< VADC GLOBCFG: DPCAL3 Position           */\r
+#define VADC_GLOBCFG_DPCAL3_Msk               (0x01UL << VADC_GLOBCFG_DPCAL3_Pos)                     /*!< VADC GLOBCFG: DPCAL3 Mask               */\r
+#define VADC_GLOBCFG_SUCAL_Pos                31                                                      /*!< VADC GLOBCFG: SUCAL Position            */\r
+#define VADC_GLOBCFG_SUCAL_Msk                (0x01UL << VADC_GLOBCFG_SUCAL_Pos)                      /*!< VADC GLOBCFG: SUCAL Mask                */\r
+\r
+/* -------------------------------  VADC_GLOBICLASS  ------------------------------ */\r
+#define VADC_GLOBICLASS_STCS_Pos              0                                                       /*!< VADC GLOBICLASS: STCS Position          */\r
+#define VADC_GLOBICLASS_STCS_Msk              (0x1fUL << VADC_GLOBICLASS_STCS_Pos)                    /*!< VADC GLOBICLASS: STCS Mask              */\r
+#define VADC_GLOBICLASS_CMS_Pos               8                                                       /*!< VADC GLOBICLASS: CMS Position           */\r
+#define VADC_GLOBICLASS_CMS_Msk               (0x07UL << VADC_GLOBICLASS_CMS_Pos)                     /*!< VADC GLOBICLASS: CMS Mask               */\r
+#define VADC_GLOBICLASS_STCE_Pos              16                                                      /*!< VADC GLOBICLASS: STCE Position          */\r
+#define VADC_GLOBICLASS_STCE_Msk              (0x1fUL << VADC_GLOBICLASS_STCE_Pos)                    /*!< VADC GLOBICLASS: STCE Mask              */\r
+#define VADC_GLOBICLASS_CME_Pos               24                                                      /*!< VADC GLOBICLASS: CME Position           */\r
+#define VADC_GLOBICLASS_CME_Msk               (0x07UL << VADC_GLOBICLASS_CME_Pos)                     /*!< VADC GLOBICLASS: CME Mask               */\r
+\r
+/* -------------------------------  VADC_GLOBBOUND  ------------------------------- */\r
+#define VADC_GLOBBOUND_BOUNDARY0_Pos          0                                                       /*!< VADC GLOBBOUND: BOUNDARY0 Position      */\r
+#define VADC_GLOBBOUND_BOUNDARY0_Msk          (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY0_Pos)          /*!< VADC GLOBBOUND: BOUNDARY0 Mask          */\r
+#define VADC_GLOBBOUND_BOUNDARY1_Pos          16                                                      /*!< VADC GLOBBOUND: BOUNDARY1 Position      */\r
+#define VADC_GLOBBOUND_BOUNDARY1_Msk          (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY1_Pos)          /*!< VADC GLOBBOUND: BOUNDARY1 Mask          */\r
+\r
+/* -------------------------------  VADC_GLOBEFLAG  ------------------------------- */\r
+#define VADC_GLOBEFLAG_SEVGLB_Pos             0                                                       /*!< VADC GLOBEFLAG: SEVGLB Position         */\r
+#define VADC_GLOBEFLAG_SEVGLB_Msk             (0x01UL << VADC_GLOBEFLAG_SEVGLB_Pos)                   /*!< VADC GLOBEFLAG: SEVGLB Mask             */\r
+#define VADC_GLOBEFLAG_REVGLB_Pos             8                                                       /*!< VADC GLOBEFLAG: REVGLB Position         */\r
+#define VADC_GLOBEFLAG_REVGLB_Msk             (0x01UL << VADC_GLOBEFLAG_REVGLB_Pos)                   /*!< VADC GLOBEFLAG: REVGLB Mask             */\r
+#define VADC_GLOBEFLAG_SEVGLBCLR_Pos          16                                                      /*!< VADC GLOBEFLAG: SEVGLBCLR Position      */\r
+#define VADC_GLOBEFLAG_SEVGLBCLR_Msk          (0x01UL << VADC_GLOBEFLAG_SEVGLBCLR_Pos)                /*!< VADC GLOBEFLAG: SEVGLBCLR Mask          */\r
+#define VADC_GLOBEFLAG_REVGLBCLR_Pos          24                                                      /*!< VADC GLOBEFLAG: REVGLBCLR Position      */\r
+#define VADC_GLOBEFLAG_REVGLBCLR_Msk          (0x01UL << VADC_GLOBEFLAG_REVGLBCLR_Pos)                /*!< VADC GLOBEFLAG: REVGLBCLR Mask          */\r
+\r
+/* --------------------------------  VADC_GLOBEVNP  ------------------------------- */\r
+#define VADC_GLOBEVNP_SEV0NP_Pos              0                                                       /*!< VADC GLOBEVNP: SEV0NP Position          */\r
+#define VADC_GLOBEVNP_SEV0NP_Msk              (0x0fUL << VADC_GLOBEVNP_SEV0NP_Pos)                    /*!< VADC GLOBEVNP: SEV0NP Mask              */\r
+#define VADC_GLOBEVNP_REV0NP_Pos              16                                                      /*!< VADC GLOBEVNP: REV0NP Position          */\r
+#define VADC_GLOBEVNP_REV0NP_Msk              (0x0fUL << VADC_GLOBEVNP_REV0NP_Pos)                    /*!< VADC GLOBEVNP: REV0NP Mask              */\r
+\r
+/* ---------------------------------  VADC_GLOBTF  -------------------------------- */\r
+#define VADC_GLOBTF_CDGR_Pos                  4                                                       /*!< VADC GLOBTF: CDGR Position              */\r
+#define VADC_GLOBTF_CDGR_Msk                  (0x0fUL << VADC_GLOBTF_CDGR_Pos)                        /*!< VADC GLOBTF: CDGR Mask                  */\r
+#define VADC_GLOBTF_CDEN_Pos                  8                                                       /*!< VADC GLOBTF: CDEN Position              */\r
+#define VADC_GLOBTF_CDEN_Msk                  (0x01UL << VADC_GLOBTF_CDEN_Pos)                        /*!< VADC GLOBTF: CDEN Mask                  */\r
+#define VADC_GLOBTF_CDSEL_Pos                 9                                                       /*!< VADC GLOBTF: CDSEL Position             */\r
+#define VADC_GLOBTF_CDSEL_Msk                 (0x03UL << VADC_GLOBTF_CDSEL_Pos)                       /*!< VADC GLOBTF: CDSEL Mask                 */\r
+#define VADC_GLOBTF_CDWC_Pos                  15                                                      /*!< VADC GLOBTF: CDWC Position              */\r
+#define VADC_GLOBTF_CDWC_Msk                  (0x01UL << VADC_GLOBTF_CDWC_Pos)                        /*!< VADC GLOBTF: CDWC Mask                  */\r
+#define VADC_GLOBTF_PDD_Pos                   16                                                      /*!< VADC GLOBTF: PDD Position               */\r
+#define VADC_GLOBTF_PDD_Msk                   (0x01UL << VADC_GLOBTF_PDD_Pos)                         /*!< VADC GLOBTF: PDD Mask                   */\r
+#define VADC_GLOBTF_MDWC_Pos                  23                                                      /*!< VADC GLOBTF: MDWC Position              */\r
+#define VADC_GLOBTF_MDWC_Msk                  (0x01UL << VADC_GLOBTF_MDWC_Pos)                        /*!< VADC GLOBTF: MDWC Mask                  */\r
+\r
+/* ---------------------------------  VADC_BRSSEL  -------------------------------- */\r
+#define VADC_BRSSEL_CHSELG0_Pos               0                                                       /*!< VADC BRSSEL: CHSELG0 Position           */\r
+#define VADC_BRSSEL_CHSELG0_Msk               (0x01UL << VADC_BRSSEL_CHSELG0_Pos)                     /*!< VADC BRSSEL: CHSELG0 Mask               */\r
+#define VADC_BRSSEL_CHSELG1_Pos               1                                                       /*!< VADC BRSSEL: CHSELG1 Position           */\r
+#define VADC_BRSSEL_CHSELG1_Msk               (0x01UL << VADC_BRSSEL_CHSELG1_Pos)                     /*!< VADC BRSSEL: CHSELG1 Mask               */\r
+#define VADC_BRSSEL_CHSELG2_Pos               2                                                       /*!< VADC BRSSEL: CHSELG2 Position           */\r
+#define VADC_BRSSEL_CHSELG2_Msk               (0x01UL << VADC_BRSSEL_CHSELG2_Pos)                     /*!< VADC BRSSEL: CHSELG2 Mask               */\r
+#define VADC_BRSSEL_CHSELG3_Pos               3                                                       /*!< VADC BRSSEL: CHSELG3 Position           */\r
+#define VADC_BRSSEL_CHSELG3_Msk               (0x01UL << VADC_BRSSEL_CHSELG3_Pos)                     /*!< VADC BRSSEL: CHSELG3 Mask               */\r
+#define VADC_BRSSEL_CHSELG4_Pos               4                                                       /*!< VADC BRSSEL: CHSELG4 Position           */\r
+#define VADC_BRSSEL_CHSELG4_Msk               (0x01UL << VADC_BRSSEL_CHSELG4_Pos)                     /*!< VADC BRSSEL: CHSELG4 Mask               */\r
+#define VADC_BRSSEL_CHSELG5_Pos               5                                                       /*!< VADC BRSSEL: CHSELG5 Position           */\r
+#define VADC_BRSSEL_CHSELG5_Msk               (0x01UL << VADC_BRSSEL_CHSELG5_Pos)                     /*!< VADC BRSSEL: CHSELG5 Mask               */\r
+#define VADC_BRSSEL_CHSELG6_Pos               6                                                       /*!< VADC BRSSEL: CHSELG6 Position           */\r
+#define VADC_BRSSEL_CHSELG6_Msk               (0x01UL << VADC_BRSSEL_CHSELG6_Pos)                     /*!< VADC BRSSEL: CHSELG6 Mask               */\r
+#define VADC_BRSSEL_CHSELG7_Pos               7                                                       /*!< VADC BRSSEL: CHSELG7 Position           */\r
+#define VADC_BRSSEL_CHSELG7_Msk               (0x01UL << VADC_BRSSEL_CHSELG7_Pos)                     /*!< VADC BRSSEL: CHSELG7 Mask               */\r
+\r
+/* ---------------------------------  VADC_BRSPND  -------------------------------- */\r
+#define VADC_BRSPND_CHPNDG0_Pos               0                                                       /*!< VADC BRSPND: CHPNDG0 Position           */\r
+#define VADC_BRSPND_CHPNDG0_Msk               (0x01UL << VADC_BRSPND_CHPNDG0_Pos)                     /*!< VADC BRSPND: CHPNDG0 Mask               */\r
+#define VADC_BRSPND_CHPNDG1_Pos               1                                                       /*!< VADC BRSPND: CHPNDG1 Position           */\r
+#define VADC_BRSPND_CHPNDG1_Msk               (0x01UL << VADC_BRSPND_CHPNDG1_Pos)                     /*!< VADC BRSPND: CHPNDG1 Mask               */\r
+#define VADC_BRSPND_CHPNDG2_Pos               2                                                       /*!< VADC BRSPND: CHPNDG2 Position           */\r
+#define VADC_BRSPND_CHPNDG2_Msk               (0x01UL << VADC_BRSPND_CHPNDG2_Pos)                     /*!< VADC BRSPND: CHPNDG2 Mask               */\r
+#define VADC_BRSPND_CHPNDG3_Pos               3                                                       /*!< VADC BRSPND: CHPNDG3 Position           */\r
+#define VADC_BRSPND_CHPNDG3_Msk               (0x01UL << VADC_BRSPND_CHPNDG3_Pos)                     /*!< VADC BRSPND: CHPNDG3 Mask               */\r
+#define VADC_BRSPND_CHPNDG4_Pos               4                                                       /*!< VADC BRSPND: CHPNDG4 Position           */\r
+#define VADC_BRSPND_CHPNDG4_Msk               (0x01UL << VADC_BRSPND_CHPNDG4_Pos)                     /*!< VADC BRSPND: CHPNDG4 Mask               */\r
+#define VADC_BRSPND_CHPNDG5_Pos               5                                                       /*!< VADC BRSPND: CHPNDG5 Position           */\r
+#define VADC_BRSPND_CHPNDG5_Msk               (0x01UL << VADC_BRSPND_CHPNDG5_Pos)                     /*!< VADC BRSPND: CHPNDG5 Mask               */\r
+#define VADC_BRSPND_CHPNDG6_Pos               6                                                       /*!< VADC BRSPND: CHPNDG6 Position           */\r
+#define VADC_BRSPND_CHPNDG6_Msk               (0x01UL << VADC_BRSPND_CHPNDG6_Pos)                     /*!< VADC BRSPND: CHPNDG6 Mask               */\r
+#define VADC_BRSPND_CHPNDG7_Pos               7                                                       /*!< VADC BRSPND: CHPNDG7 Position           */\r
+#define VADC_BRSPND_CHPNDG7_Msk               (0x01UL << VADC_BRSPND_CHPNDG7_Pos)                     /*!< VADC BRSPND: CHPNDG7 Mask               */\r
+\r
+/* --------------------------------  VADC_BRSCTRL  -------------------------------- */\r
+#define VADC_BRSCTRL_XTSEL_Pos                8                                                       /*!< VADC BRSCTRL: XTSEL Position            */\r
+#define VADC_BRSCTRL_XTSEL_Msk                (0x0fUL << VADC_BRSCTRL_XTSEL_Pos)                      /*!< VADC BRSCTRL: XTSEL Mask                */\r
+#define VADC_BRSCTRL_XTLVL_Pos                12                                                      /*!< VADC BRSCTRL: XTLVL Position            */\r
+#define VADC_BRSCTRL_XTLVL_Msk                (0x01UL << VADC_BRSCTRL_XTLVL_Pos)                      /*!< VADC BRSCTRL: XTLVL Mask                */\r
+#define VADC_BRSCTRL_XTMODE_Pos               13                                                      /*!< VADC BRSCTRL: XTMODE Position           */\r
+#define VADC_BRSCTRL_XTMODE_Msk               (0x03UL << VADC_BRSCTRL_XTMODE_Pos)                     /*!< VADC BRSCTRL: XTMODE Mask               */\r
+#define VADC_BRSCTRL_XTWC_Pos                 15                                                      /*!< VADC BRSCTRL: XTWC Position             */\r
+#define VADC_BRSCTRL_XTWC_Msk                 (0x01UL << VADC_BRSCTRL_XTWC_Pos)                       /*!< VADC BRSCTRL: XTWC Mask                 */\r
+#define VADC_BRSCTRL_GTSEL_Pos                16                                                      /*!< VADC BRSCTRL: GTSEL Position            */\r
+#define VADC_BRSCTRL_GTSEL_Msk                (0x0fUL << VADC_BRSCTRL_GTSEL_Pos)                      /*!< VADC BRSCTRL: GTSEL Mask                */\r
+#define VADC_BRSCTRL_GTLVL_Pos                20                                                      /*!< VADC BRSCTRL: GTLVL Position            */\r
+#define VADC_BRSCTRL_GTLVL_Msk                (0x01UL << VADC_BRSCTRL_GTLVL_Pos)                      /*!< VADC BRSCTRL: GTLVL Mask                */\r
+#define VADC_BRSCTRL_GTWC_Pos                 23                                                      /*!< VADC BRSCTRL: GTWC Position             */\r
+#define VADC_BRSCTRL_GTWC_Msk                 (0x01UL << VADC_BRSCTRL_GTWC_Pos)                       /*!< VADC BRSCTRL: GTWC Mask                 */\r
+\r
+/* ---------------------------------  VADC_BRSMR  --------------------------------- */\r
+#define VADC_BRSMR_ENGT_Pos                   0                                                       /*!< VADC BRSMR: ENGT Position               */\r
+#define VADC_BRSMR_ENGT_Msk                   (0x03UL << VADC_BRSMR_ENGT_Pos)                         /*!< VADC BRSMR: ENGT Mask                   */\r
+#define VADC_BRSMR_ENTR_Pos                   2                                                       /*!< VADC BRSMR: ENTR Position               */\r
+#define VADC_BRSMR_ENTR_Msk                   (0x01UL << VADC_BRSMR_ENTR_Pos)                         /*!< VADC BRSMR: ENTR Mask                   */\r
+#define VADC_BRSMR_ENSI_Pos                   3                                                       /*!< VADC BRSMR: ENSI Position               */\r
+#define VADC_BRSMR_ENSI_Msk                   (0x01UL << VADC_BRSMR_ENSI_Pos)                         /*!< VADC BRSMR: ENSI Mask                   */\r
+#define VADC_BRSMR_SCAN_Pos                   4                                                       /*!< VADC BRSMR: SCAN Position               */\r
+#define VADC_BRSMR_SCAN_Msk                   (0x01UL << VADC_BRSMR_SCAN_Pos)                         /*!< VADC BRSMR: SCAN Mask                   */\r
+#define VADC_BRSMR_LDM_Pos                    5                                                       /*!< VADC BRSMR: LDM Position                */\r
+#define VADC_BRSMR_LDM_Msk                    (0x01UL << VADC_BRSMR_LDM_Pos)                          /*!< VADC BRSMR: LDM Mask                    */\r
+#define VADC_BRSMR_REQGT_Pos                  7                                                       /*!< VADC BRSMR: REQGT Position              */\r
+#define VADC_BRSMR_REQGT_Msk                  (0x01UL << VADC_BRSMR_REQGT_Pos)                        /*!< VADC BRSMR: REQGT Mask                  */\r
+#define VADC_BRSMR_CLRPND_Pos                 8                                                       /*!< VADC BRSMR: CLRPND Position             */\r
+#define VADC_BRSMR_CLRPND_Msk                 (0x01UL << VADC_BRSMR_CLRPND_Pos)                       /*!< VADC BRSMR: CLRPND Mask                 */\r
+#define VADC_BRSMR_LDEV_Pos                   9                                                       /*!< VADC BRSMR: LDEV Position               */\r
+#define VADC_BRSMR_LDEV_Msk                   (0x01UL << VADC_BRSMR_LDEV_Pos)                         /*!< VADC BRSMR: LDEV Mask                   */\r
+#define VADC_BRSMR_RPTDIS_Pos                 16                                                      /*!< VADC BRSMR: RPTDIS Position             */\r
+#define VADC_BRSMR_RPTDIS_Msk                 (0x01UL << VADC_BRSMR_RPTDIS_Pos)                       /*!< VADC BRSMR: RPTDIS Mask                 */\r
+\r
+/* --------------------------------  VADC_GLOBRCR  -------------------------------- */\r
+#define VADC_GLOBRCR_DRCTR_Pos                16                                                      /*!< VADC GLOBRCR: DRCTR Position            */\r
+#define VADC_GLOBRCR_DRCTR_Msk                (0x0fUL << VADC_GLOBRCR_DRCTR_Pos)                      /*!< VADC GLOBRCR: DRCTR Mask                */\r
+#define VADC_GLOBRCR_WFR_Pos                  24                                                      /*!< VADC GLOBRCR: WFR Position              */\r
+#define VADC_GLOBRCR_WFR_Msk                  (0x01UL << VADC_GLOBRCR_WFR_Pos)                        /*!< VADC GLOBRCR: WFR Mask                  */\r
+#define VADC_GLOBRCR_SRGEN_Pos                31                                                      /*!< VADC GLOBRCR: SRGEN Position            */\r
+#define VADC_GLOBRCR_SRGEN_Msk                (0x01UL << VADC_GLOBRCR_SRGEN_Pos)                      /*!< VADC GLOBRCR: SRGEN Mask                */\r
+\r
+/* --------------------------------  VADC_GLOBRES  -------------------------------- */\r
+#define VADC_GLOBRES_RESULT_Pos               0                                                       /*!< VADC GLOBRES: RESULT Position           */\r
+#define VADC_GLOBRES_RESULT_Msk               (0x0000ffffUL << VADC_GLOBRES_RESULT_Pos)               /*!< VADC GLOBRES: RESULT Mask               */\r
+#define VADC_GLOBRES_GNR_Pos                  16                                                      /*!< VADC GLOBRES: GNR Position              */\r
+#define VADC_GLOBRES_GNR_Msk                  (0x0fUL << VADC_GLOBRES_GNR_Pos)                        /*!< VADC GLOBRES: GNR Mask                  */\r
+#define VADC_GLOBRES_CHNR_Pos                 20                                                      /*!< VADC GLOBRES: CHNR Position             */\r
+#define VADC_GLOBRES_CHNR_Msk                 (0x1fUL << VADC_GLOBRES_CHNR_Pos)                       /*!< VADC GLOBRES: CHNR Mask                 */\r
+#define VADC_GLOBRES_EMUX_Pos                 25                                                      /*!< VADC GLOBRES: EMUX Position             */\r
+#define VADC_GLOBRES_EMUX_Msk                 (0x07UL << VADC_GLOBRES_EMUX_Pos)                       /*!< VADC GLOBRES: EMUX Mask                 */\r
+#define VADC_GLOBRES_CRS_Pos                  28                                                      /*!< VADC GLOBRES: CRS Position              */\r
+#define VADC_GLOBRES_CRS_Msk                  (0x03UL << VADC_GLOBRES_CRS_Pos)                        /*!< VADC GLOBRES: CRS Mask                  */\r
+#define VADC_GLOBRES_FCR_Pos                  30                                                      /*!< VADC GLOBRES: FCR Position              */\r
+#define VADC_GLOBRES_FCR_Msk                  (0x01UL << VADC_GLOBRES_FCR_Pos)                        /*!< VADC GLOBRES: FCR Mask                  */\r
+#define VADC_GLOBRES_VF_Pos                   31                                                      /*!< VADC GLOBRES: VF Position               */\r
+#define VADC_GLOBRES_VF_Msk                   (0x01UL << VADC_GLOBRES_VF_Pos)                         /*!< VADC GLOBRES: VF Mask                   */\r
+\r
+/* --------------------------------  VADC_GLOBRESD  ------------------------------- */\r
+#define VADC_GLOBRESD_RESULT_Pos              0                                                       /*!< VADC GLOBRESD: RESULT Position          */\r
+#define VADC_GLOBRESD_RESULT_Msk              (0x0000ffffUL << VADC_GLOBRESD_RESULT_Pos)              /*!< VADC GLOBRESD: RESULT Mask              */\r
+#define VADC_GLOBRESD_GNR_Pos                 16                                                      /*!< VADC GLOBRESD: GNR Position             */\r
+#define VADC_GLOBRESD_GNR_Msk                 (0x0fUL << VADC_GLOBRESD_GNR_Pos)                       /*!< VADC GLOBRESD: GNR Mask                 */\r
+#define VADC_GLOBRESD_CHNR_Pos                20                                                      /*!< VADC GLOBRESD: CHNR Position            */\r
+#define VADC_GLOBRESD_CHNR_Msk                (0x1fUL << VADC_GLOBRESD_CHNR_Pos)                      /*!< VADC GLOBRESD: CHNR Mask                */\r
+#define VADC_GLOBRESD_EMUX_Pos                25                                                      /*!< VADC GLOBRESD: EMUX Position            */\r
+#define VADC_GLOBRESD_EMUX_Msk                (0x07UL << VADC_GLOBRESD_EMUX_Pos)                      /*!< VADC GLOBRESD: EMUX Mask                */\r
+#define VADC_GLOBRESD_CRS_Pos                 28                                                      /*!< VADC GLOBRESD: CRS Position             */\r
+#define VADC_GLOBRESD_CRS_Msk                 (0x03UL << VADC_GLOBRESD_CRS_Pos)                       /*!< VADC GLOBRESD: CRS Mask                 */\r
+#define VADC_GLOBRESD_FCR_Pos                 30                                                      /*!< VADC GLOBRESD: FCR Position             */\r
+#define VADC_GLOBRESD_FCR_Msk                 (0x01UL << VADC_GLOBRESD_FCR_Pos)                       /*!< VADC GLOBRESD: FCR Mask                 */\r
+#define VADC_GLOBRESD_VF_Pos                  31                                                      /*!< VADC GLOBRESD: VF Position              */\r
+#define VADC_GLOBRESD_VF_Msk                  (0x01UL << VADC_GLOBRESD_VF_Pos)                        /*!< VADC GLOBRESD: VF Mask                  */\r
+\r
+/* --------------------------------  VADC_EMUXSEL  -------------------------------- */\r
+#define VADC_EMUXSEL_EMUXGRP0_Pos             0                                                       /*!< VADC EMUXSEL: EMUXGRP0 Position         */\r
+#define VADC_EMUXSEL_EMUXGRP0_Msk             (0x0fUL << VADC_EMUXSEL_EMUXGRP0_Pos)                   /*!< VADC EMUXSEL: EMUXGRP0 Mask             */\r
+#define VADC_EMUXSEL_EMUXGRP1_Pos             4                                                       /*!< VADC EMUXSEL: EMUXGRP1 Position         */\r
+#define VADC_EMUXSEL_EMUXGRP1_Msk             (0x0fUL << VADC_EMUXSEL_EMUXGRP1_Pos)                   /*!< VADC EMUXSEL: EMUXGRP1 Mask             */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'VADC_G' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  VADC_G_ARBCFG  ------------------------------- */\r
+#define VADC_G_ARBCFG_ANONC_Pos               0                                                       /*!< VADC_G ARBCFG: ANONC Position           */\r
+#define VADC_G_ARBCFG_ANONC_Msk               (0x03UL << VADC_G_ARBCFG_ANONC_Pos)                     /*!< VADC_G ARBCFG: ANONC Mask               */\r
+#define VADC_G_ARBCFG_ARBRND_Pos              4                                                       /*!< VADC_G ARBCFG: ARBRND Position          */\r
+#define VADC_G_ARBCFG_ARBRND_Msk              (0x03UL << VADC_G_ARBCFG_ARBRND_Pos)                    /*!< VADC_G ARBCFG: ARBRND Mask              */\r
+#define VADC_G_ARBCFG_ARBM_Pos                7                                                       /*!< VADC_G ARBCFG: ARBM Position            */\r
+#define VADC_G_ARBCFG_ARBM_Msk                (0x01UL << VADC_G_ARBCFG_ARBM_Pos)                      /*!< VADC_G ARBCFG: ARBM Mask                */\r
+#define VADC_G_ARBCFG_ANONS_Pos               16                                                      /*!< VADC_G ARBCFG: ANONS Position           */\r
+#define VADC_G_ARBCFG_ANONS_Msk               (0x03UL << VADC_G_ARBCFG_ANONS_Pos)                     /*!< VADC_G ARBCFG: ANONS Mask               */\r
+#define VADC_G_ARBCFG_CAL_Pos                 28                                                      /*!< VADC_G ARBCFG: CAL Position             */\r
+#define VADC_G_ARBCFG_CAL_Msk                 (0x01UL << VADC_G_ARBCFG_CAL_Pos)                       /*!< VADC_G ARBCFG: CAL Mask                 */\r
+#define VADC_G_ARBCFG_BUSY_Pos                30                                                      /*!< VADC_G ARBCFG: BUSY Position            */\r
+#define VADC_G_ARBCFG_BUSY_Msk                (0x01UL << VADC_G_ARBCFG_BUSY_Pos)                      /*!< VADC_G ARBCFG: BUSY Mask                */\r
+#define VADC_G_ARBCFG_SAMPLE_Pos              31                                                      /*!< VADC_G ARBCFG: SAMPLE Position          */\r
+#define VADC_G_ARBCFG_SAMPLE_Msk              (0x01UL << VADC_G_ARBCFG_SAMPLE_Pos)                    /*!< VADC_G ARBCFG: SAMPLE Mask              */\r
+\r
+/* --------------------------------  VADC_G_ARBPR  -------------------------------- */\r
+#define VADC_G_ARBPR_PRIO0_Pos                0                                                       /*!< VADC_G ARBPR: PRIO0 Position            */\r
+#define VADC_G_ARBPR_PRIO0_Msk                (0x03UL << VADC_G_ARBPR_PRIO0_Pos)                      /*!< VADC_G ARBPR: PRIO0 Mask                */\r
+#define VADC_G_ARBPR_CSM0_Pos                 3                                                       /*!< VADC_G ARBPR: CSM0 Position             */\r
+#define VADC_G_ARBPR_CSM0_Msk                 (0x01UL << VADC_G_ARBPR_CSM0_Pos)                       /*!< VADC_G ARBPR: CSM0 Mask                 */\r
+#define VADC_G_ARBPR_PRIO1_Pos                4                                                       /*!< VADC_G ARBPR: PRIO1 Position            */\r
+#define VADC_G_ARBPR_PRIO1_Msk                (0x03UL << VADC_G_ARBPR_PRIO1_Pos)                      /*!< VADC_G ARBPR: PRIO1 Mask                */\r
+#define VADC_G_ARBPR_CSM1_Pos                 7                                                       /*!< VADC_G ARBPR: CSM1 Position             */\r
+#define VADC_G_ARBPR_CSM1_Msk                 (0x01UL << VADC_G_ARBPR_CSM1_Pos)                       /*!< VADC_G ARBPR: CSM1 Mask                 */\r
+#define VADC_G_ARBPR_PRIO2_Pos                8                                                       /*!< VADC_G ARBPR: PRIO2 Position            */\r
+#define VADC_G_ARBPR_PRIO2_Msk                (0x03UL << VADC_G_ARBPR_PRIO2_Pos)                      /*!< VADC_G ARBPR: PRIO2 Mask                */\r
+#define VADC_G_ARBPR_CSM2_Pos                 11                                                      /*!< VADC_G ARBPR: CSM2 Position             */\r
+#define VADC_G_ARBPR_CSM2_Msk                 (0x01UL << VADC_G_ARBPR_CSM2_Pos)                       /*!< VADC_G ARBPR: CSM2 Mask                 */\r
+#define VADC_G_ARBPR_ASEN0_Pos                24                                                      /*!< VADC_G ARBPR: ASEN0 Position            */\r
+#define VADC_G_ARBPR_ASEN0_Msk                (0x01UL << VADC_G_ARBPR_ASEN0_Pos)                      /*!< VADC_G ARBPR: ASEN0 Mask                */\r
+#define VADC_G_ARBPR_ASEN1_Pos                25                                                      /*!< VADC_G ARBPR: ASEN1 Position            */\r
+#define VADC_G_ARBPR_ASEN1_Msk                (0x01UL << VADC_G_ARBPR_ASEN1_Pos)                      /*!< VADC_G ARBPR: ASEN1 Mask                */\r
+#define VADC_G_ARBPR_ASEN2_Pos                26                                                      /*!< VADC_G ARBPR: ASEN2 Position            */\r
+#define VADC_G_ARBPR_ASEN2_Msk                (0x01UL << VADC_G_ARBPR_ASEN2_Pos)                      /*!< VADC_G ARBPR: ASEN2 Mask                */\r
+\r
+/* --------------------------------  VADC_G_CHASS  -------------------------------- */\r
+#define VADC_G_CHASS_ASSCH0_Pos               0                                                       /*!< VADC_G CHASS: ASSCH0 Position           */\r
+#define VADC_G_CHASS_ASSCH0_Msk               (0x01UL << VADC_G_CHASS_ASSCH0_Pos)                     /*!< VADC_G CHASS: ASSCH0 Mask               */\r
+#define VADC_G_CHASS_ASSCH1_Pos               1                                                       /*!< VADC_G CHASS: ASSCH1 Position           */\r
+#define VADC_G_CHASS_ASSCH1_Msk               (0x01UL << VADC_G_CHASS_ASSCH1_Pos)                     /*!< VADC_G CHASS: ASSCH1 Mask               */\r
+#define VADC_G_CHASS_ASSCH2_Pos               2                                                       /*!< VADC_G CHASS: ASSCH2 Position           */\r
+#define VADC_G_CHASS_ASSCH2_Msk               (0x01UL << VADC_G_CHASS_ASSCH2_Pos)                     /*!< VADC_G CHASS: ASSCH2 Mask               */\r
+#define VADC_G_CHASS_ASSCH3_Pos               3                                                       /*!< VADC_G CHASS: ASSCH3 Position           */\r
+#define VADC_G_CHASS_ASSCH3_Msk               (0x01UL << VADC_G_CHASS_ASSCH3_Pos)                     /*!< VADC_G CHASS: ASSCH3 Mask               */\r
+#define VADC_G_CHASS_ASSCH4_Pos               4                                                       /*!< VADC_G CHASS: ASSCH4 Position           */\r
+#define VADC_G_CHASS_ASSCH4_Msk               (0x01UL << VADC_G_CHASS_ASSCH4_Pos)                     /*!< VADC_G CHASS: ASSCH4 Mask               */\r
+#define VADC_G_CHASS_ASSCH5_Pos               5                                                       /*!< VADC_G CHASS: ASSCH5 Position           */\r
+#define VADC_G_CHASS_ASSCH5_Msk               (0x01UL << VADC_G_CHASS_ASSCH5_Pos)                     /*!< VADC_G CHASS: ASSCH5 Mask               */\r
+#define VADC_G_CHASS_ASSCH6_Pos               6                                                       /*!< VADC_G CHASS: ASSCH6 Position           */\r
+#define VADC_G_CHASS_ASSCH6_Msk               (0x01UL << VADC_G_CHASS_ASSCH6_Pos)                     /*!< VADC_G CHASS: ASSCH6 Mask               */\r
+#define VADC_G_CHASS_ASSCH7_Pos               7                                                       /*!< VADC_G CHASS: ASSCH7 Position           */\r
+#define VADC_G_CHASS_ASSCH7_Msk               (0x01UL << VADC_G_CHASS_ASSCH7_Pos)                     /*!< VADC_G CHASS: ASSCH7 Mask               */\r
+\r
+/* --------------------------------  VADC_G_ICLASS  ------------------------------- */\r
+#define VADC_G_ICLASS_STCS_Pos                0                                                       /*!< VADC_G ICLASS: STCS Position            */\r
+#define VADC_G_ICLASS_STCS_Msk                (0x1fUL << VADC_G_ICLASS_STCS_Pos)                      /*!< VADC_G ICLASS: STCS Mask                */\r
+#define VADC_G_ICLASS_CMS_Pos                 8                                                       /*!< VADC_G ICLASS: CMS Position             */\r
+#define VADC_G_ICLASS_CMS_Msk                 (0x07UL << VADC_G_ICLASS_CMS_Pos)                       /*!< VADC_G ICLASS: CMS Mask                 */\r
+#define VADC_G_ICLASS_STCE_Pos                16                                                      /*!< VADC_G ICLASS: STCE Position            */\r
+#define VADC_G_ICLASS_STCE_Msk                (0x1fUL << VADC_G_ICLASS_STCE_Pos)                      /*!< VADC_G ICLASS: STCE Mask                */\r
+#define VADC_G_ICLASS_CME_Pos                 24                                                      /*!< VADC_G ICLASS: CME Position             */\r
+#define VADC_G_ICLASS_CME_Msk                 (0x07UL << VADC_G_ICLASS_CME_Pos)                       /*!< VADC_G ICLASS: CME Mask                 */\r
+\r
+/* --------------------------------  VADC_G_ALIAS  -------------------------------- */\r
+#define VADC_G_ALIAS_ALIAS0_Pos               0                                                       /*!< VADC_G ALIAS: ALIAS0 Position           */\r
+#define VADC_G_ALIAS_ALIAS0_Msk               (0x1fUL << VADC_G_ALIAS_ALIAS0_Pos)                     /*!< VADC_G ALIAS: ALIAS0 Mask               */\r
+#define VADC_G_ALIAS_ALIAS1_Pos               8                                                       /*!< VADC_G ALIAS: ALIAS1 Position           */\r
+#define VADC_G_ALIAS_ALIAS1_Msk               (0x1fUL << VADC_G_ALIAS_ALIAS1_Pos)                     /*!< VADC_G ALIAS: ALIAS1 Mask               */\r
+\r
+/* --------------------------------  VADC_G_BOUND  -------------------------------- */\r
+#define VADC_G_BOUND_BOUNDARY0_Pos            0                                                       /*!< VADC_G BOUND: BOUNDARY0 Position        */\r
+#define VADC_G_BOUND_BOUNDARY0_Msk            (0x00000fffUL << VADC_G_BOUND_BOUNDARY0_Pos)            /*!< VADC_G BOUND: BOUNDARY0 Mask            */\r
+#define VADC_G_BOUND_BOUNDARY1_Pos            16                                                      /*!< VADC_G BOUND: BOUNDARY1 Position        */\r
+#define VADC_G_BOUND_BOUNDARY1_Msk            (0x00000fffUL << VADC_G_BOUND_BOUNDARY1_Pos)            /*!< VADC_G BOUND: BOUNDARY1 Mask            */\r
+\r
+/* --------------------------------  VADC_G_SYNCTR  ------------------------------- */\r
+#define VADC_G_SYNCTR_STSEL_Pos               0                                                       /*!< VADC_G SYNCTR: STSEL Position           */\r
+#define VADC_G_SYNCTR_STSEL_Msk               (0x03UL << VADC_G_SYNCTR_STSEL_Pos)                     /*!< VADC_G SYNCTR: STSEL Mask               */\r
+#define VADC_G_SYNCTR_EVALR1_Pos              4                                                       /*!< VADC_G SYNCTR: EVALR1 Position          */\r
+#define VADC_G_SYNCTR_EVALR1_Msk              (0x01UL << VADC_G_SYNCTR_EVALR1_Pos)                    /*!< VADC_G SYNCTR: EVALR1 Mask              */\r
+#define VADC_G_SYNCTR_EVALR2_Pos              5                                                       /*!< VADC_G SYNCTR: EVALR2 Position          */\r
+#define VADC_G_SYNCTR_EVALR2_Msk              (0x01UL << VADC_G_SYNCTR_EVALR2_Pos)                    /*!< VADC_G SYNCTR: EVALR2 Mask              */\r
+#define VADC_G_SYNCTR_EVALR3_Pos              6                                                       /*!< VADC_G SYNCTR: EVALR3 Position          */\r
+#define VADC_G_SYNCTR_EVALR3_Msk              (0x01UL << VADC_G_SYNCTR_EVALR3_Pos)                    /*!< VADC_G SYNCTR: EVALR3 Mask              */\r
+\r
+/* ---------------------------------  VADC_G_BFL  --------------------------------- */\r
+#define VADC_G_BFL_BFL0_Pos                   0                                                       /*!< VADC_G BFL: BFL0 Position               */\r
+#define VADC_G_BFL_BFL0_Msk                   (0x01UL << VADC_G_BFL_BFL0_Pos)                         /*!< VADC_G BFL: BFL0 Mask                   */\r
+#define VADC_G_BFL_BFL1_Pos                   1                                                       /*!< VADC_G BFL: BFL1 Position               */\r
+#define VADC_G_BFL_BFL1_Msk                   (0x01UL << VADC_G_BFL_BFL1_Pos)                         /*!< VADC_G BFL: BFL1 Mask                   */\r
+#define VADC_G_BFL_BFL2_Pos                   2                                                       /*!< VADC_G BFL: BFL2 Position               */\r
+#define VADC_G_BFL_BFL2_Msk                   (0x01UL << VADC_G_BFL_BFL2_Pos)                         /*!< VADC_G BFL: BFL2 Mask                   */\r
+#define VADC_G_BFL_BFL3_Pos                   3                                                       /*!< VADC_G BFL: BFL3 Position               */\r
+#define VADC_G_BFL_BFL3_Msk                   (0x01UL << VADC_G_BFL_BFL3_Pos)                         /*!< VADC_G BFL: BFL3 Mask                   */\r
+#define VADC_G_BFL_BFE0_Pos                   16                                                      /*!< VADC_G BFL: BFE0 Position               */\r
+#define VADC_G_BFL_BFE0_Msk                   (0x01UL << VADC_G_BFL_BFE0_Pos)                         /*!< VADC_G BFL: BFE0 Mask                   */\r
+#define VADC_G_BFL_BFE1_Pos                   17                                                      /*!< VADC_G BFL: BFE1 Position               */\r
+#define VADC_G_BFL_BFE1_Msk                   (0x01UL << VADC_G_BFL_BFE1_Pos)                         /*!< VADC_G BFL: BFE1 Mask                   */\r
+#define VADC_G_BFL_BFE2_Pos                   18                                                      /*!< VADC_G BFL: BFE2 Position               */\r
+#define VADC_G_BFL_BFE2_Msk                   (0x01UL << VADC_G_BFL_BFE2_Pos)                         /*!< VADC_G BFL: BFE2 Mask                   */\r
+#define VADC_G_BFL_BFE3_Pos                   19                                                      /*!< VADC_G BFL: BFE3 Position               */\r
+#define VADC_G_BFL_BFE3_Msk                   (0x01UL << VADC_G_BFL_BFE3_Pos)                         /*!< VADC_G BFL: BFE3 Mask                   */\r
+\r
+/* --------------------------------  VADC_G_QCTRL0  ------------------------------- */\r
+#define VADC_G_QCTRL0_XTSEL_Pos               8                                                       /*!< VADC_G QCTRL0: XTSEL Position           */\r
+#define VADC_G_QCTRL0_XTSEL_Msk               (0x0fUL << VADC_G_QCTRL0_XTSEL_Pos)                     /*!< VADC_G QCTRL0: XTSEL Mask               */\r
+#define VADC_G_QCTRL0_XTLVL_Pos               12                                                      /*!< VADC_G QCTRL0: XTLVL Position           */\r
+#define VADC_G_QCTRL0_XTLVL_Msk               (0x01UL << VADC_G_QCTRL0_XTLVL_Pos)                     /*!< VADC_G QCTRL0: XTLVL Mask               */\r
+#define VADC_G_QCTRL0_XTMODE_Pos              13                                                      /*!< VADC_G QCTRL0: XTMODE Position          */\r
+#define VADC_G_QCTRL0_XTMODE_Msk              (0x03UL << VADC_G_QCTRL0_XTMODE_Pos)                    /*!< VADC_G QCTRL0: XTMODE Mask              */\r
+#define VADC_G_QCTRL0_XTWC_Pos                15                                                      /*!< VADC_G QCTRL0: XTWC Position            */\r
+#define VADC_G_QCTRL0_XTWC_Msk                (0x01UL << VADC_G_QCTRL0_XTWC_Pos)                      /*!< VADC_G QCTRL0: XTWC Mask                */\r
+#define VADC_G_QCTRL0_GTSEL_Pos               16                                                      /*!< VADC_G QCTRL0: GTSEL Position           */\r
+#define VADC_G_QCTRL0_GTSEL_Msk               (0x0fUL << VADC_G_QCTRL0_GTSEL_Pos)                     /*!< VADC_G QCTRL0: GTSEL Mask               */\r
+#define VADC_G_QCTRL0_GTLVL_Pos               20                                                      /*!< VADC_G QCTRL0: GTLVL Position           */\r
+#define VADC_G_QCTRL0_GTLVL_Msk               (0x01UL << VADC_G_QCTRL0_GTLVL_Pos)                     /*!< VADC_G QCTRL0: GTLVL Mask               */\r
+#define VADC_G_QCTRL0_GTWC_Pos                23                                                      /*!< VADC_G QCTRL0: GTWC Position            */\r
+#define VADC_G_QCTRL0_GTWC_Msk                (0x01UL << VADC_G_QCTRL0_GTWC_Pos)                      /*!< VADC_G QCTRL0: GTWC Mask                */\r
+#define VADC_G_QCTRL0_TMEN_Pos                28                                                      /*!< VADC_G QCTRL0: TMEN Position            */\r
+#define VADC_G_QCTRL0_TMEN_Msk                (0x01UL << VADC_G_QCTRL0_TMEN_Pos)                      /*!< VADC_G QCTRL0: TMEN Mask                */\r
+#define VADC_G_QCTRL0_TMWC_Pos                31                                                      /*!< VADC_G QCTRL0: TMWC Position            */\r
+#define VADC_G_QCTRL0_TMWC_Msk                (0x01UL << VADC_G_QCTRL0_TMWC_Pos)                      /*!< VADC_G QCTRL0: TMWC Mask                */\r
+\r
+/* ---------------------------------  VADC_G_QMR0  -------------------------------- */\r
+#define VADC_G_QMR0_ENGT_Pos                  0                                                       /*!< VADC_G QMR0: ENGT Position              */\r
+#define VADC_G_QMR0_ENGT_Msk                  (0x03UL << VADC_G_QMR0_ENGT_Pos)                        /*!< VADC_G QMR0: ENGT Mask                  */\r
+#define VADC_G_QMR0_ENTR_Pos                  2                                                       /*!< VADC_G QMR0: ENTR Position              */\r
+#define VADC_G_QMR0_ENTR_Msk                  (0x01UL << VADC_G_QMR0_ENTR_Pos)                        /*!< VADC_G QMR0: ENTR Mask                  */\r
+#define VADC_G_QMR0_CLRV_Pos                  8                                                       /*!< VADC_G QMR0: CLRV Position              */\r
+#define VADC_G_QMR0_CLRV_Msk                  (0x01UL << VADC_G_QMR0_CLRV_Pos)                        /*!< VADC_G QMR0: CLRV Mask                  */\r
+#define VADC_G_QMR0_TREV_Pos                  9                                                       /*!< VADC_G QMR0: TREV Position              */\r
+#define VADC_G_QMR0_TREV_Msk                  (0x01UL << VADC_G_QMR0_TREV_Pos)                        /*!< VADC_G QMR0: TREV Mask                  */\r
+#define VADC_G_QMR0_FLUSH_Pos                 10                                                      /*!< VADC_G QMR0: FLUSH Position             */\r
+#define VADC_G_QMR0_FLUSH_Msk                 (0x01UL << VADC_G_QMR0_FLUSH_Pos)                       /*!< VADC_G QMR0: FLUSH Mask                 */\r
+#define VADC_G_QMR0_CEV_Pos                   11                                                      /*!< VADC_G QMR0: CEV Position               */\r
+#define VADC_G_QMR0_CEV_Msk                   (0x01UL << VADC_G_QMR0_CEV_Pos)                         /*!< VADC_G QMR0: CEV Mask                   */\r
+#define VADC_G_QMR0_RPTDIS_Pos                16                                                      /*!< VADC_G QMR0: RPTDIS Position            */\r
+#define VADC_G_QMR0_RPTDIS_Msk                (0x01UL << VADC_G_QMR0_RPTDIS_Pos)                      /*!< VADC_G QMR0: RPTDIS Mask                */\r
+\r
+/* ---------------------------------  VADC_G_QSR0  -------------------------------- */\r
+#define VADC_G_QSR0_FILL_Pos                  0                                                       /*!< VADC_G QSR0: FILL Position              */\r
+#define VADC_G_QSR0_FILL_Msk                  (0x0fUL << VADC_G_QSR0_FILL_Pos)                        /*!< VADC_G QSR0: FILL Mask                  */\r
+#define VADC_G_QSR0_EMPTY_Pos                 5                                                       /*!< VADC_G QSR0: EMPTY Position             */\r
+#define VADC_G_QSR0_EMPTY_Msk                 (0x01UL << VADC_G_QSR0_EMPTY_Pos)                       /*!< VADC_G QSR0: EMPTY Mask                 */\r
+#define VADC_G_QSR0_REQGT_Pos                 7                                                       /*!< VADC_G QSR0: REQGT Position             */\r
+#define VADC_G_QSR0_REQGT_Msk                 (0x01UL << VADC_G_QSR0_REQGT_Pos)                       /*!< VADC_G QSR0: REQGT Mask                 */\r
+#define VADC_G_QSR0_EV_Pos                    8                                                       /*!< VADC_G QSR0: EV Position                */\r
+#define VADC_G_QSR0_EV_Msk                    (0x01UL << VADC_G_QSR0_EV_Pos)                          /*!< VADC_G QSR0: EV Mask                    */\r
+\r
+/* ---------------------------------  VADC_G_Q0R0  -------------------------------- */\r
+#define VADC_G_Q0R0_REQCHNR_Pos               0                                                       /*!< VADC_G Q0R0: REQCHNR Position           */\r
+#define VADC_G_Q0R0_REQCHNR_Msk               (0x1fUL << VADC_G_Q0R0_REQCHNR_Pos)                     /*!< VADC_G Q0R0: REQCHNR Mask               */\r
+#define VADC_G_Q0R0_RF_Pos                    5                                                       /*!< VADC_G Q0R0: RF Position                */\r
+#define VADC_G_Q0R0_RF_Msk                    (0x01UL << VADC_G_Q0R0_RF_Pos)                          /*!< VADC_G Q0R0: RF Mask                    */\r
+#define VADC_G_Q0R0_ENSI_Pos                  6                                                       /*!< VADC_G Q0R0: ENSI Position              */\r
+#define VADC_G_Q0R0_ENSI_Msk                  (0x01UL << VADC_G_Q0R0_ENSI_Pos)                        /*!< VADC_G Q0R0: ENSI Mask                  */\r
+#define VADC_G_Q0R0_EXTR_Pos                  7                                                       /*!< VADC_G Q0R0: EXTR Position              */\r
+#define VADC_G_Q0R0_EXTR_Msk                  (0x01UL << VADC_G_Q0R0_EXTR_Pos)                        /*!< VADC_G Q0R0: EXTR Mask                  */\r
+#define VADC_G_Q0R0_V_Pos                     8                                                       /*!< VADC_G Q0R0: V Position                 */\r
+#define VADC_G_Q0R0_V_Msk                     (0x01UL << VADC_G_Q0R0_V_Pos)                           /*!< VADC_G Q0R0: V Mask                     */\r
+\r
+/* --------------------------------  VADC_G_QINR0  -------------------------------- */\r
+#define VADC_G_QINR0_REQCHNR_Pos              0                                                       /*!< VADC_G QINR0: REQCHNR Position          */\r
+#define VADC_G_QINR0_REQCHNR_Msk              (0x1fUL << VADC_G_QINR0_REQCHNR_Pos)                    /*!< VADC_G QINR0: REQCHNR Mask              */\r
+#define VADC_G_QINR0_RF_Pos                   5                                                       /*!< VADC_G QINR0: RF Position               */\r
+#define VADC_G_QINR0_RF_Msk                   (0x01UL << VADC_G_QINR0_RF_Pos)                         /*!< VADC_G QINR0: RF Mask                   */\r
+#define VADC_G_QINR0_ENSI_Pos                 6                                                       /*!< VADC_G QINR0: ENSI Position             */\r
+#define VADC_G_QINR0_ENSI_Msk                 (0x01UL << VADC_G_QINR0_ENSI_Pos)                       /*!< VADC_G QINR0: ENSI Mask                 */\r
+#define VADC_G_QINR0_EXTR_Pos                 7                                                       /*!< VADC_G QINR0: EXTR Position             */\r
+#define VADC_G_QINR0_EXTR_Msk                 (0x01UL << VADC_G_QINR0_EXTR_Pos)                       /*!< VADC_G QINR0: EXTR Mask                 */\r
+\r
+/* --------------------------------  VADC_G_QBUR0  -------------------------------- */\r
+#define VADC_G_QBUR0_REQCHNR_Pos              0                                                       /*!< VADC_G QBUR0: REQCHNR Position          */\r
+#define VADC_G_QBUR0_REQCHNR_Msk              (0x1fUL << VADC_G_QBUR0_REQCHNR_Pos)                    /*!< VADC_G QBUR0: REQCHNR Mask              */\r
+#define VADC_G_QBUR0_RF_Pos                   5                                                       /*!< VADC_G QBUR0: RF Position               */\r
+#define VADC_G_QBUR0_RF_Msk                   (0x01UL << VADC_G_QBUR0_RF_Pos)                         /*!< VADC_G QBUR0: RF Mask                   */\r
+#define VADC_G_QBUR0_ENSI_Pos                 6                                                       /*!< VADC_G QBUR0: ENSI Position             */\r
+#define VADC_G_QBUR0_ENSI_Msk                 (0x01UL << VADC_G_QBUR0_ENSI_Pos)                       /*!< VADC_G QBUR0: ENSI Mask                 */\r
+#define VADC_G_QBUR0_EXTR_Pos                 7                                                       /*!< VADC_G QBUR0: EXTR Position             */\r
+#define VADC_G_QBUR0_EXTR_Msk                 (0x01UL << VADC_G_QBUR0_EXTR_Pos)                       /*!< VADC_G QBUR0: EXTR Mask                 */\r
+#define VADC_G_QBUR0_V_Pos                    8                                                       /*!< VADC_G QBUR0: V Position                */\r
+#define VADC_G_QBUR0_V_Msk                    (0x01UL << VADC_G_QBUR0_V_Pos)                          /*!< VADC_G QBUR0: V Mask                    */\r
+\r
+/* --------------------------------  VADC_G_ASCTRL  ------------------------------- */\r
+#define VADC_G_ASCTRL_XTSEL_Pos               8                                                       /*!< VADC_G ASCTRL: XTSEL Position           */\r
+#define VADC_G_ASCTRL_XTSEL_Msk               (0x0fUL << VADC_G_ASCTRL_XTSEL_Pos)                     /*!< VADC_G ASCTRL: XTSEL Mask               */\r
+#define VADC_G_ASCTRL_XTLVL_Pos               12                                                      /*!< VADC_G ASCTRL: XTLVL Position           */\r
+#define VADC_G_ASCTRL_XTLVL_Msk               (0x01UL << VADC_G_ASCTRL_XTLVL_Pos)                     /*!< VADC_G ASCTRL: XTLVL Mask               */\r
+#define VADC_G_ASCTRL_XTMODE_Pos              13                                                      /*!< VADC_G ASCTRL: XTMODE Position          */\r
+#define VADC_G_ASCTRL_XTMODE_Msk              (0x03UL << VADC_G_ASCTRL_XTMODE_Pos)                    /*!< VADC_G ASCTRL: XTMODE Mask              */\r
+#define VADC_G_ASCTRL_XTWC_Pos                15                                                      /*!< VADC_G ASCTRL: XTWC Position            */\r
+#define VADC_G_ASCTRL_XTWC_Msk                (0x01UL << VADC_G_ASCTRL_XTWC_Pos)                      /*!< VADC_G ASCTRL: XTWC Mask                */\r
+#define VADC_G_ASCTRL_GTSEL_Pos               16                                                      /*!< VADC_G ASCTRL: GTSEL Position           */\r
+#define VADC_G_ASCTRL_GTSEL_Msk               (0x0fUL << VADC_G_ASCTRL_GTSEL_Pos)                     /*!< VADC_G ASCTRL: GTSEL Mask               */\r
+#define VADC_G_ASCTRL_GTLVL_Pos               20                                                      /*!< VADC_G ASCTRL: GTLVL Position           */\r
+#define VADC_G_ASCTRL_GTLVL_Msk               (0x01UL << VADC_G_ASCTRL_GTLVL_Pos)                     /*!< VADC_G ASCTRL: GTLVL Mask               */\r
+#define VADC_G_ASCTRL_GTWC_Pos                23                                                      /*!< VADC_G ASCTRL: GTWC Position            */\r
+#define VADC_G_ASCTRL_GTWC_Msk                (0x01UL << VADC_G_ASCTRL_GTWC_Pos)                      /*!< VADC_G ASCTRL: GTWC Mask                */\r
+#define VADC_G_ASCTRL_TMEN_Pos                28                                                      /*!< VADC_G ASCTRL: TMEN Position            */\r
+#define VADC_G_ASCTRL_TMEN_Msk                (0x01UL << VADC_G_ASCTRL_TMEN_Pos)                      /*!< VADC_G ASCTRL: TMEN Mask                */\r
+#define VADC_G_ASCTRL_TMWC_Pos                31                                                      /*!< VADC_G ASCTRL: TMWC Position            */\r
+#define VADC_G_ASCTRL_TMWC_Msk                (0x01UL << VADC_G_ASCTRL_TMWC_Pos)                      /*!< VADC_G ASCTRL: TMWC Mask                */\r
+\r
+/* ---------------------------------  VADC_G_ASMR  -------------------------------- */\r
+#define VADC_G_ASMR_ENGT_Pos                  0                                                       /*!< VADC_G ASMR: ENGT Position              */\r
+#define VADC_G_ASMR_ENGT_Msk                  (0x03UL << VADC_G_ASMR_ENGT_Pos)                        /*!< VADC_G ASMR: ENGT Mask                  */\r
+#define VADC_G_ASMR_ENTR_Pos                  2                                                       /*!< VADC_G ASMR: ENTR Position              */\r
+#define VADC_G_ASMR_ENTR_Msk                  (0x01UL << VADC_G_ASMR_ENTR_Pos)                        /*!< VADC_G ASMR: ENTR Mask                  */\r
+#define VADC_G_ASMR_ENSI_Pos                  3                                                       /*!< VADC_G ASMR: ENSI Position              */\r
+#define VADC_G_ASMR_ENSI_Msk                  (0x01UL << VADC_G_ASMR_ENSI_Pos)                        /*!< VADC_G ASMR: ENSI Mask                  */\r
+#define VADC_G_ASMR_SCAN_Pos                  4                                                       /*!< VADC_G ASMR: SCAN Position              */\r
+#define VADC_G_ASMR_SCAN_Msk                  (0x01UL << VADC_G_ASMR_SCAN_Pos)                        /*!< VADC_G ASMR: SCAN Mask                  */\r
+#define VADC_G_ASMR_LDM_Pos                   5                                                       /*!< VADC_G ASMR: LDM Position               */\r
+#define VADC_G_ASMR_LDM_Msk                   (0x01UL << VADC_G_ASMR_LDM_Pos)                         /*!< VADC_G ASMR: LDM Mask                   */\r
+#define VADC_G_ASMR_REQGT_Pos                 7                                                       /*!< VADC_G ASMR: REQGT Position             */\r
+#define VADC_G_ASMR_REQGT_Msk                 (0x01UL << VADC_G_ASMR_REQGT_Pos)                       /*!< VADC_G ASMR: REQGT Mask                 */\r
+#define VADC_G_ASMR_CLRPND_Pos                8                                                       /*!< VADC_G ASMR: CLRPND Position            */\r
+#define VADC_G_ASMR_CLRPND_Msk                (0x01UL << VADC_G_ASMR_CLRPND_Pos)                      /*!< VADC_G ASMR: CLRPND Mask                */\r
+#define VADC_G_ASMR_LDEV_Pos                  9                                                       /*!< VADC_G ASMR: LDEV Position              */\r
+#define VADC_G_ASMR_LDEV_Msk                  (0x01UL << VADC_G_ASMR_LDEV_Pos)                        /*!< VADC_G ASMR: LDEV Mask                  */\r
+#define VADC_G_ASMR_RPTDIS_Pos                16                                                      /*!< VADC_G ASMR: RPTDIS Position            */\r
+#define VADC_G_ASMR_RPTDIS_Msk                (0x01UL << VADC_G_ASMR_RPTDIS_Pos)                      /*!< VADC_G ASMR: RPTDIS Mask                */\r
+\r
+/* --------------------------------  VADC_G_ASSEL  -------------------------------- */\r
+#define VADC_G_ASSEL_CHSEL0_Pos               0                                                       /*!< VADC_G ASSEL: CHSEL0 Position           */\r
+#define VADC_G_ASSEL_CHSEL0_Msk               (0x01UL << VADC_G_ASSEL_CHSEL0_Pos)                     /*!< VADC_G ASSEL: CHSEL0 Mask               */\r
+#define VADC_G_ASSEL_CHSEL1_Pos               1                                                       /*!< VADC_G ASSEL: CHSEL1 Position           */\r
+#define VADC_G_ASSEL_CHSEL1_Msk               (0x01UL << VADC_G_ASSEL_CHSEL1_Pos)                     /*!< VADC_G ASSEL: CHSEL1 Mask               */\r
+#define VADC_G_ASSEL_CHSEL2_Pos               2                                                       /*!< VADC_G ASSEL: CHSEL2 Position           */\r
+#define VADC_G_ASSEL_CHSEL2_Msk               (0x01UL << VADC_G_ASSEL_CHSEL2_Pos)                     /*!< VADC_G ASSEL: CHSEL2 Mask               */\r
+#define VADC_G_ASSEL_CHSEL3_Pos               3                                                       /*!< VADC_G ASSEL: CHSEL3 Position           */\r
+#define VADC_G_ASSEL_CHSEL3_Msk               (0x01UL << VADC_G_ASSEL_CHSEL3_Pos)                     /*!< VADC_G ASSEL: CHSEL3 Mask               */\r
+#define VADC_G_ASSEL_CHSEL4_Pos               4                                                       /*!< VADC_G ASSEL: CHSEL4 Position           */\r
+#define VADC_G_ASSEL_CHSEL4_Msk               (0x01UL << VADC_G_ASSEL_CHSEL4_Pos)                     /*!< VADC_G ASSEL: CHSEL4 Mask               */\r
+#define VADC_G_ASSEL_CHSEL5_Pos               5                                                       /*!< VADC_G ASSEL: CHSEL5 Position           */\r
+#define VADC_G_ASSEL_CHSEL5_Msk               (0x01UL << VADC_G_ASSEL_CHSEL5_Pos)                     /*!< VADC_G ASSEL: CHSEL5 Mask               */\r
+#define VADC_G_ASSEL_CHSEL6_Pos               6                                                       /*!< VADC_G ASSEL: CHSEL6 Position           */\r
+#define VADC_G_ASSEL_CHSEL6_Msk               (0x01UL << VADC_G_ASSEL_CHSEL6_Pos)                     /*!< VADC_G ASSEL: CHSEL6 Mask               */\r
+#define VADC_G_ASSEL_CHSEL7_Pos               7                                                       /*!< VADC_G ASSEL: CHSEL7 Position           */\r
+#define VADC_G_ASSEL_CHSEL7_Msk               (0x01UL << VADC_G_ASSEL_CHSEL7_Pos)                     /*!< VADC_G ASSEL: CHSEL7 Mask               */\r
+\r
+/* --------------------------------  VADC_G_ASPND  -------------------------------- */\r
+#define VADC_G_ASPND_CHPND0_Pos               0                                                       /*!< VADC_G ASPND: CHPND0 Position           */\r
+#define VADC_G_ASPND_CHPND0_Msk               (0x01UL << VADC_G_ASPND_CHPND0_Pos)                     /*!< VADC_G ASPND: CHPND0 Mask               */\r
+#define VADC_G_ASPND_CHPND1_Pos               1                                                       /*!< VADC_G ASPND: CHPND1 Position           */\r
+#define VADC_G_ASPND_CHPND1_Msk               (0x01UL << VADC_G_ASPND_CHPND1_Pos)                     /*!< VADC_G ASPND: CHPND1 Mask               */\r
+#define VADC_G_ASPND_CHPND2_Pos               2                                                       /*!< VADC_G ASPND: CHPND2 Position           */\r
+#define VADC_G_ASPND_CHPND2_Msk               (0x01UL << VADC_G_ASPND_CHPND2_Pos)                     /*!< VADC_G ASPND: CHPND2 Mask               */\r
+#define VADC_G_ASPND_CHPND3_Pos               3                                                       /*!< VADC_G ASPND: CHPND3 Position           */\r
+#define VADC_G_ASPND_CHPND3_Msk               (0x01UL << VADC_G_ASPND_CHPND3_Pos)                     /*!< VADC_G ASPND: CHPND3 Mask               */\r
+#define VADC_G_ASPND_CHPND4_Pos               4                                                       /*!< VADC_G ASPND: CHPND4 Position           */\r
+#define VADC_G_ASPND_CHPND4_Msk               (0x01UL << VADC_G_ASPND_CHPND4_Pos)                     /*!< VADC_G ASPND: CHPND4 Mask               */\r
+#define VADC_G_ASPND_CHPND5_Pos               5                                                       /*!< VADC_G ASPND: CHPND5 Position           */\r
+#define VADC_G_ASPND_CHPND5_Msk               (0x01UL << VADC_G_ASPND_CHPND5_Pos)                     /*!< VADC_G ASPND: CHPND5 Mask               */\r
+#define VADC_G_ASPND_CHPND6_Pos               6                                                       /*!< VADC_G ASPND: CHPND6 Position           */\r
+#define VADC_G_ASPND_CHPND6_Msk               (0x01UL << VADC_G_ASPND_CHPND6_Pos)                     /*!< VADC_G ASPND: CHPND6 Mask               */\r
+#define VADC_G_ASPND_CHPND7_Pos               7                                                       /*!< VADC_G ASPND: CHPND7 Position           */\r
+#define VADC_G_ASPND_CHPND7_Msk               (0x01UL << VADC_G_ASPND_CHPND7_Pos)                     /*!< VADC_G ASPND: CHPND7 Mask               */\r
+\r
+/* --------------------------------  VADC_G_CEFLAG  ------------------------------- */\r
+#define VADC_G_CEFLAG_CEV0_Pos                0                                                       /*!< VADC_G CEFLAG: CEV0 Position            */\r
+#define VADC_G_CEFLAG_CEV0_Msk                (0x01UL << VADC_G_CEFLAG_CEV0_Pos)                      /*!< VADC_G CEFLAG: CEV0 Mask                */\r
+#define VADC_G_CEFLAG_CEV1_Pos                1                                                       /*!< VADC_G CEFLAG: CEV1 Position            */\r
+#define VADC_G_CEFLAG_CEV1_Msk                (0x01UL << VADC_G_CEFLAG_CEV1_Pos)                      /*!< VADC_G CEFLAG: CEV1 Mask                */\r
+#define VADC_G_CEFLAG_CEV2_Pos                2                                                       /*!< VADC_G CEFLAG: CEV2 Position            */\r
+#define VADC_G_CEFLAG_CEV2_Msk                (0x01UL << VADC_G_CEFLAG_CEV2_Pos)                      /*!< VADC_G CEFLAG: CEV2 Mask                */\r
+#define VADC_G_CEFLAG_CEV3_Pos                3                                                       /*!< VADC_G CEFLAG: CEV3 Position            */\r
+#define VADC_G_CEFLAG_CEV3_Msk                (0x01UL << VADC_G_CEFLAG_CEV3_Pos)                      /*!< VADC_G CEFLAG: CEV3 Mask                */\r
+#define VADC_G_CEFLAG_CEV4_Pos                4                                                       /*!< VADC_G CEFLAG: CEV4 Position            */\r
+#define VADC_G_CEFLAG_CEV4_Msk                (0x01UL << VADC_G_CEFLAG_CEV4_Pos)                      /*!< VADC_G CEFLAG: CEV4 Mask                */\r
+#define VADC_G_CEFLAG_CEV5_Pos                5                                                       /*!< VADC_G CEFLAG: CEV5 Position            */\r
+#define VADC_G_CEFLAG_CEV5_Msk                (0x01UL << VADC_G_CEFLAG_CEV5_Pos)                      /*!< VADC_G CEFLAG: CEV5 Mask                */\r
+#define VADC_G_CEFLAG_CEV6_Pos                6                                                       /*!< VADC_G CEFLAG: CEV6 Position            */\r
+#define VADC_G_CEFLAG_CEV6_Msk                (0x01UL << VADC_G_CEFLAG_CEV6_Pos)                      /*!< VADC_G CEFLAG: CEV6 Mask                */\r
+#define VADC_G_CEFLAG_CEV7_Pos                7                                                       /*!< VADC_G CEFLAG: CEV7 Position            */\r
+#define VADC_G_CEFLAG_CEV7_Msk                (0x01UL << VADC_G_CEFLAG_CEV7_Pos)                      /*!< VADC_G CEFLAG: CEV7 Mask                */\r
+\r
+/* --------------------------------  VADC_G_REFLAG  ------------------------------- */\r
+#define VADC_G_REFLAG_REV0_Pos                0                                                       /*!< VADC_G REFLAG: REV0 Position            */\r
+#define VADC_G_REFLAG_REV0_Msk                (0x01UL << VADC_G_REFLAG_REV0_Pos)                      /*!< VADC_G REFLAG: REV0 Mask                */\r
+#define VADC_G_REFLAG_REV1_Pos                1                                                       /*!< VADC_G REFLAG: REV1 Position            */\r
+#define VADC_G_REFLAG_REV1_Msk                (0x01UL << VADC_G_REFLAG_REV1_Pos)                      /*!< VADC_G REFLAG: REV1 Mask                */\r
+#define VADC_G_REFLAG_REV2_Pos                2                                                       /*!< VADC_G REFLAG: REV2 Position            */\r
+#define VADC_G_REFLAG_REV2_Msk                (0x01UL << VADC_G_REFLAG_REV2_Pos)                      /*!< VADC_G REFLAG: REV2 Mask                */\r
+#define VADC_G_REFLAG_REV3_Pos                3                                                       /*!< VADC_G REFLAG: REV3 Position            */\r
+#define VADC_G_REFLAG_REV3_Msk                (0x01UL << VADC_G_REFLAG_REV3_Pos)                      /*!< VADC_G REFLAG: REV3 Mask                */\r
+#define VADC_G_REFLAG_REV4_Pos                4                                                       /*!< VADC_G REFLAG: REV4 Position            */\r
+#define VADC_G_REFLAG_REV4_Msk                (0x01UL << VADC_G_REFLAG_REV4_Pos)                      /*!< VADC_G REFLAG: REV4 Mask                */\r
+#define VADC_G_REFLAG_REV5_Pos                5                                                       /*!< VADC_G REFLAG: REV5 Position            */\r
+#define VADC_G_REFLAG_REV5_Msk                (0x01UL << VADC_G_REFLAG_REV5_Pos)                      /*!< VADC_G REFLAG: REV5 Mask                */\r
+#define VADC_G_REFLAG_REV6_Pos                6                                                       /*!< VADC_G REFLAG: REV6 Position            */\r
+#define VADC_G_REFLAG_REV6_Msk                (0x01UL << VADC_G_REFLAG_REV6_Pos)                      /*!< VADC_G REFLAG: REV6 Mask                */\r
+#define VADC_G_REFLAG_REV7_Pos                7                                                       /*!< VADC_G REFLAG: REV7 Position            */\r
+#define VADC_G_REFLAG_REV7_Msk                (0x01UL << VADC_G_REFLAG_REV7_Pos)                      /*!< VADC_G REFLAG: REV7 Mask                */\r
+#define VADC_G_REFLAG_REV8_Pos                8                                                       /*!< VADC_G REFLAG: REV8 Position            */\r
+#define VADC_G_REFLAG_REV8_Msk                (0x01UL << VADC_G_REFLAG_REV8_Pos)                      /*!< VADC_G REFLAG: REV8 Mask                */\r
+#define VADC_G_REFLAG_REV9_Pos                9                                                       /*!< VADC_G REFLAG: REV9 Position            */\r
+#define VADC_G_REFLAG_REV9_Msk                (0x01UL << VADC_G_REFLAG_REV9_Pos)                      /*!< VADC_G REFLAG: REV9 Mask                */\r
+#define VADC_G_REFLAG_REV10_Pos               10                                                      /*!< VADC_G REFLAG: REV10 Position           */\r
+#define VADC_G_REFLAG_REV10_Msk               (0x01UL << VADC_G_REFLAG_REV10_Pos)                     /*!< VADC_G REFLAG: REV10 Mask               */\r
+#define VADC_G_REFLAG_REV11_Pos               11                                                      /*!< VADC_G REFLAG: REV11 Position           */\r
+#define VADC_G_REFLAG_REV11_Msk               (0x01UL << VADC_G_REFLAG_REV11_Pos)                     /*!< VADC_G REFLAG: REV11 Mask               */\r
+#define VADC_G_REFLAG_REV12_Pos               12                                                      /*!< VADC_G REFLAG: REV12 Position           */\r
+#define VADC_G_REFLAG_REV12_Msk               (0x01UL << VADC_G_REFLAG_REV12_Pos)                     /*!< VADC_G REFLAG: REV12 Mask               */\r
+#define VADC_G_REFLAG_REV13_Pos               13                                                      /*!< VADC_G REFLAG: REV13 Position           */\r
+#define VADC_G_REFLAG_REV13_Msk               (0x01UL << VADC_G_REFLAG_REV13_Pos)                     /*!< VADC_G REFLAG: REV13 Mask               */\r
+#define VADC_G_REFLAG_REV14_Pos               14                                                      /*!< VADC_G REFLAG: REV14 Position           */\r
+#define VADC_G_REFLAG_REV14_Msk               (0x01UL << VADC_G_REFLAG_REV14_Pos)                     /*!< VADC_G REFLAG: REV14 Mask               */\r
+#define VADC_G_REFLAG_REV15_Pos               15                                                      /*!< VADC_G REFLAG: REV15 Position           */\r
+#define VADC_G_REFLAG_REV15_Msk               (0x01UL << VADC_G_REFLAG_REV15_Pos)                     /*!< VADC_G REFLAG: REV15 Mask               */\r
+\r
+/* --------------------------------  VADC_G_SEFLAG  ------------------------------- */\r
+#define VADC_G_SEFLAG_SEV0_Pos                0                                                       /*!< VADC_G SEFLAG: SEV0 Position            */\r
+#define VADC_G_SEFLAG_SEV0_Msk                (0x01UL << VADC_G_SEFLAG_SEV0_Pos)                      /*!< VADC_G SEFLAG: SEV0 Mask                */\r
+#define VADC_G_SEFLAG_SEV1_Pos                1                                                       /*!< VADC_G SEFLAG: SEV1 Position            */\r
+#define VADC_G_SEFLAG_SEV1_Msk                (0x01UL << VADC_G_SEFLAG_SEV1_Pos)                      /*!< VADC_G SEFLAG: SEV1 Mask                */\r
+\r
+/* --------------------------------  VADC_G_CEFCLR  ------------------------------- */\r
+#define VADC_G_CEFCLR_CEV0_Pos                0                                                       /*!< VADC_G CEFCLR: CEV0 Position            */\r
+#define VADC_G_CEFCLR_CEV0_Msk                (0x01UL << VADC_G_CEFCLR_CEV0_Pos)                      /*!< VADC_G CEFCLR: CEV0 Mask                */\r
+#define VADC_G_CEFCLR_CEV1_Pos                1                                                       /*!< VADC_G CEFCLR: CEV1 Position            */\r
+#define VADC_G_CEFCLR_CEV1_Msk                (0x01UL << VADC_G_CEFCLR_CEV1_Pos)                      /*!< VADC_G CEFCLR: CEV1 Mask                */\r
+#define VADC_G_CEFCLR_CEV2_Pos                2                                                       /*!< VADC_G CEFCLR: CEV2 Position            */\r
+#define VADC_G_CEFCLR_CEV2_Msk                (0x01UL << VADC_G_CEFCLR_CEV2_Pos)                      /*!< VADC_G CEFCLR: CEV2 Mask                */\r
+#define VADC_G_CEFCLR_CEV3_Pos                3                                                       /*!< VADC_G CEFCLR: CEV3 Position            */\r
+#define VADC_G_CEFCLR_CEV3_Msk                (0x01UL << VADC_G_CEFCLR_CEV3_Pos)                      /*!< VADC_G CEFCLR: CEV3 Mask                */\r
+#define VADC_G_CEFCLR_CEV4_Pos                4                                                       /*!< VADC_G CEFCLR: CEV4 Position            */\r
+#define VADC_G_CEFCLR_CEV4_Msk                (0x01UL << VADC_G_CEFCLR_CEV4_Pos)                      /*!< VADC_G CEFCLR: CEV4 Mask                */\r
+#define VADC_G_CEFCLR_CEV5_Pos                5                                                       /*!< VADC_G CEFCLR: CEV5 Position            */\r
+#define VADC_G_CEFCLR_CEV5_Msk                (0x01UL << VADC_G_CEFCLR_CEV5_Pos)                      /*!< VADC_G CEFCLR: CEV5 Mask                */\r
+#define VADC_G_CEFCLR_CEV6_Pos                6                                                       /*!< VADC_G CEFCLR: CEV6 Position            */\r
+#define VADC_G_CEFCLR_CEV6_Msk                (0x01UL << VADC_G_CEFCLR_CEV6_Pos)                      /*!< VADC_G CEFCLR: CEV6 Mask                */\r
+#define VADC_G_CEFCLR_CEV7_Pos                7                                                       /*!< VADC_G CEFCLR: CEV7 Position            */\r
+#define VADC_G_CEFCLR_CEV7_Msk                (0x01UL << VADC_G_CEFCLR_CEV7_Pos)                      /*!< VADC_G CEFCLR: CEV7 Mask                */\r
+\r
+/* --------------------------------  VADC_G_REFCLR  ------------------------------- */\r
+#define VADC_G_REFCLR_REV0_Pos                0                                                       /*!< VADC_G REFCLR: REV0 Position            */\r
+#define VADC_G_REFCLR_REV0_Msk                (0x01UL << VADC_G_REFCLR_REV0_Pos)                      /*!< VADC_G REFCLR: REV0 Mask                */\r
+#define VADC_G_REFCLR_REV1_Pos                1                                                       /*!< VADC_G REFCLR: REV1 Position            */\r
+#define VADC_G_REFCLR_REV1_Msk                (0x01UL << VADC_G_REFCLR_REV1_Pos)                      /*!< VADC_G REFCLR: REV1 Mask                */\r
+#define VADC_G_REFCLR_REV2_Pos                2                                                       /*!< VADC_G REFCLR: REV2 Position            */\r
+#define VADC_G_REFCLR_REV2_Msk                (0x01UL << VADC_G_REFCLR_REV2_Pos)                      /*!< VADC_G REFCLR: REV2 Mask                */\r
+#define VADC_G_REFCLR_REV3_Pos                3                                                       /*!< VADC_G REFCLR: REV3 Position            */\r
+#define VADC_G_REFCLR_REV3_Msk                (0x01UL << VADC_G_REFCLR_REV3_Pos)                      /*!< VADC_G REFCLR: REV3 Mask                */\r
+#define VADC_G_REFCLR_REV4_Pos                4                                                       /*!< VADC_G REFCLR: REV4 Position            */\r
+#define VADC_G_REFCLR_REV4_Msk                (0x01UL << VADC_G_REFCLR_REV4_Pos)                      /*!< VADC_G REFCLR: REV4 Mask                */\r
+#define VADC_G_REFCLR_REV5_Pos                5                                                       /*!< VADC_G REFCLR: REV5 Position            */\r
+#define VADC_G_REFCLR_REV5_Msk                (0x01UL << VADC_G_REFCLR_REV5_Pos)                      /*!< VADC_G REFCLR: REV5 Mask                */\r
+#define VADC_G_REFCLR_REV6_Pos                6                                                       /*!< VADC_G REFCLR: REV6 Position            */\r
+#define VADC_G_REFCLR_REV6_Msk                (0x01UL << VADC_G_REFCLR_REV6_Pos)                      /*!< VADC_G REFCLR: REV6 Mask                */\r
+#define VADC_G_REFCLR_REV7_Pos                7                                                       /*!< VADC_G REFCLR: REV7 Position            */\r
+#define VADC_G_REFCLR_REV7_Msk                (0x01UL << VADC_G_REFCLR_REV7_Pos)                      /*!< VADC_G REFCLR: REV7 Mask                */\r
+#define VADC_G_REFCLR_REV8_Pos                8                                                       /*!< VADC_G REFCLR: REV8 Position            */\r
+#define VADC_G_REFCLR_REV8_Msk                (0x01UL << VADC_G_REFCLR_REV8_Pos)                      /*!< VADC_G REFCLR: REV8 Mask                */\r
+#define VADC_G_REFCLR_REV9_Pos                9                                                       /*!< VADC_G REFCLR: REV9 Position            */\r
+#define VADC_G_REFCLR_REV9_Msk                (0x01UL << VADC_G_REFCLR_REV9_Pos)                      /*!< VADC_G REFCLR: REV9 Mask                */\r
+#define VADC_G_REFCLR_REV10_Pos               10                                                      /*!< VADC_G REFCLR: REV10 Position           */\r
+#define VADC_G_REFCLR_REV10_Msk               (0x01UL << VADC_G_REFCLR_REV10_Pos)                     /*!< VADC_G REFCLR: REV10 Mask               */\r
+#define VADC_G_REFCLR_REV11_Pos               11                                                      /*!< VADC_G REFCLR: REV11 Position           */\r
+#define VADC_G_REFCLR_REV11_Msk               (0x01UL << VADC_G_REFCLR_REV11_Pos)                     /*!< VADC_G REFCLR: REV11 Mask               */\r
+#define VADC_G_REFCLR_REV12_Pos               12                                                      /*!< VADC_G REFCLR: REV12 Position           */\r
+#define VADC_G_REFCLR_REV12_Msk               (0x01UL << VADC_G_REFCLR_REV12_Pos)                     /*!< VADC_G REFCLR: REV12 Mask               */\r
+#define VADC_G_REFCLR_REV13_Pos               13                                                      /*!< VADC_G REFCLR: REV13 Position           */\r
+#define VADC_G_REFCLR_REV13_Msk               (0x01UL << VADC_G_REFCLR_REV13_Pos)                     /*!< VADC_G REFCLR: REV13 Mask               */\r
+#define VADC_G_REFCLR_REV14_Pos               14                                                      /*!< VADC_G REFCLR: REV14 Position           */\r
+#define VADC_G_REFCLR_REV14_Msk               (0x01UL << VADC_G_REFCLR_REV14_Pos)                     /*!< VADC_G REFCLR: REV14 Mask               */\r
+#define VADC_G_REFCLR_REV15_Pos               15                                                      /*!< VADC_G REFCLR: REV15 Position           */\r
+#define VADC_G_REFCLR_REV15_Msk               (0x01UL << VADC_G_REFCLR_REV15_Pos)                     /*!< VADC_G REFCLR: REV15 Mask               */\r
+\r
+/* --------------------------------  VADC_G_SEFCLR  ------------------------------- */\r
+#define VADC_G_SEFCLR_SEV0_Pos                0                                                       /*!< VADC_G SEFCLR: SEV0 Position            */\r
+#define VADC_G_SEFCLR_SEV0_Msk                (0x01UL << VADC_G_SEFCLR_SEV0_Pos)                      /*!< VADC_G SEFCLR: SEV0 Mask                */\r
+#define VADC_G_SEFCLR_SEV1_Pos                1                                                       /*!< VADC_G SEFCLR: SEV1 Position            */\r
+#define VADC_G_SEFCLR_SEV1_Msk                (0x01UL << VADC_G_SEFCLR_SEV1_Pos)                      /*!< VADC_G SEFCLR: SEV1 Mask                */\r
+\r
+/* --------------------------------  VADC_G_CEVNP0  ------------------------------- */\r
+#define VADC_G_CEVNP0_CEV0NP_Pos              0                                                       /*!< VADC_G CEVNP0: CEV0NP Position          */\r
+#define VADC_G_CEVNP0_CEV0NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV0NP_Pos)                    /*!< VADC_G CEVNP0: CEV0NP Mask              */\r
+#define VADC_G_CEVNP0_CEV1NP_Pos              4                                                       /*!< VADC_G CEVNP0: CEV1NP Position          */\r
+#define VADC_G_CEVNP0_CEV1NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV1NP_Pos)                    /*!< VADC_G CEVNP0: CEV1NP Mask              */\r
+#define VADC_G_CEVNP0_CEV2NP_Pos              8                                                       /*!< VADC_G CEVNP0: CEV2NP Position          */\r
+#define VADC_G_CEVNP0_CEV2NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV2NP_Pos)                    /*!< VADC_G CEVNP0: CEV2NP Mask              */\r
+#define VADC_G_CEVNP0_CEV3NP_Pos              12                                                      /*!< VADC_G CEVNP0: CEV3NP Position          */\r
+#define VADC_G_CEVNP0_CEV3NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV3NP_Pos)                    /*!< VADC_G CEVNP0: CEV3NP Mask              */\r
+#define VADC_G_CEVNP0_CEV4NP_Pos              16                                                      /*!< VADC_G CEVNP0: CEV4NP Position          */\r
+#define VADC_G_CEVNP0_CEV4NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV4NP_Pos)                    /*!< VADC_G CEVNP0: CEV4NP Mask              */\r
+#define VADC_G_CEVNP0_CEV5NP_Pos              20                                                      /*!< VADC_G CEVNP0: CEV5NP Position          */\r
+#define VADC_G_CEVNP0_CEV5NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV5NP_Pos)                    /*!< VADC_G CEVNP0: CEV5NP Mask              */\r
+#define VADC_G_CEVNP0_CEV6NP_Pos              24                                                      /*!< VADC_G CEVNP0: CEV6NP Position          */\r
+#define VADC_G_CEVNP0_CEV6NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV6NP_Pos)                    /*!< VADC_G CEVNP0: CEV6NP Mask              */\r
+#define VADC_G_CEVNP0_CEV7NP_Pos              28                                                      /*!< VADC_G CEVNP0: CEV7NP Position          */\r
+#define VADC_G_CEVNP0_CEV7NP_Msk              (0x0fUL << VADC_G_CEVNP0_CEV7NP_Pos)                    /*!< VADC_G CEVNP0: CEV7NP Mask              */\r
+\r
+/* --------------------------------  VADC_G_REVNP0  ------------------------------- */\r
+#define VADC_G_REVNP0_REV0NP_Pos              0                                                       /*!< VADC_G REVNP0: REV0NP Position          */\r
+#define VADC_G_REVNP0_REV0NP_Msk              (0x0fUL << VADC_G_REVNP0_REV0NP_Pos)                    /*!< VADC_G REVNP0: REV0NP Mask              */\r
+#define VADC_G_REVNP0_REV1NP_Pos              4                                                       /*!< VADC_G REVNP0: REV1NP Position          */\r
+#define VADC_G_REVNP0_REV1NP_Msk              (0x0fUL << VADC_G_REVNP0_REV1NP_Pos)                    /*!< VADC_G REVNP0: REV1NP Mask              */\r
+#define VADC_G_REVNP0_REV2NP_Pos              8                                                       /*!< VADC_G REVNP0: REV2NP Position          */\r
+#define VADC_G_REVNP0_REV2NP_Msk              (0x0fUL << VADC_G_REVNP0_REV2NP_Pos)                    /*!< VADC_G REVNP0: REV2NP Mask              */\r
+#define VADC_G_REVNP0_REV3NP_Pos              12                                                      /*!< VADC_G REVNP0: REV3NP Position          */\r
+#define VADC_G_REVNP0_REV3NP_Msk              (0x0fUL << VADC_G_REVNP0_REV3NP_Pos)                    /*!< VADC_G REVNP0: REV3NP Mask              */\r
+#define VADC_G_REVNP0_REV4NP_Pos              16                                                      /*!< VADC_G REVNP0: REV4NP Position          */\r
+#define VADC_G_REVNP0_REV4NP_Msk              (0x0fUL << VADC_G_REVNP0_REV4NP_Pos)                    /*!< VADC_G REVNP0: REV4NP Mask              */\r
+#define VADC_G_REVNP0_REV5NP_Pos              20                                                      /*!< VADC_G REVNP0: REV5NP Position          */\r
+#define VADC_G_REVNP0_REV5NP_Msk              (0x0fUL << VADC_G_REVNP0_REV5NP_Pos)                    /*!< VADC_G REVNP0: REV5NP Mask              */\r
+#define VADC_G_REVNP0_REV6NP_Pos              24                                                      /*!< VADC_G REVNP0: REV6NP Position          */\r
+#define VADC_G_REVNP0_REV6NP_Msk              (0x0fUL << VADC_G_REVNP0_REV6NP_Pos)                    /*!< VADC_G REVNP0: REV6NP Mask              */\r
+#define VADC_G_REVNP0_REV7NP_Pos              28                                                      /*!< VADC_G REVNP0: REV7NP Position          */\r
+#define VADC_G_REVNP0_REV7NP_Msk              (0x0fUL << VADC_G_REVNP0_REV7NP_Pos)                    /*!< VADC_G REVNP0: REV7NP Mask              */\r
+\r
+/* --------------------------------  VADC_G_REVNP1  ------------------------------- */\r
+#define VADC_G_REVNP1_REV8NP_Pos              0                                                       /*!< VADC_G REVNP1: REV8NP Position          */\r
+#define VADC_G_REVNP1_REV8NP_Msk              (0x0fUL << VADC_G_REVNP1_REV8NP_Pos)                    /*!< VADC_G REVNP1: REV8NP Mask              */\r
+#define VADC_G_REVNP1_REV9NP_Pos              4                                                       /*!< VADC_G REVNP1: REV9NP Position          */\r
+#define VADC_G_REVNP1_REV9NP_Msk              (0x0fUL << VADC_G_REVNP1_REV9NP_Pos)                    /*!< VADC_G REVNP1: REV9NP Mask              */\r
+#define VADC_G_REVNP1_REV10NP_Pos             8                                                       /*!< VADC_G REVNP1: REV10NP Position         */\r
+#define VADC_G_REVNP1_REV10NP_Msk             (0x0fUL << VADC_G_REVNP1_REV10NP_Pos)                   /*!< VADC_G REVNP1: REV10NP Mask             */\r
+#define VADC_G_REVNP1_REV11NP_Pos             12                                                      /*!< VADC_G REVNP1: REV11NP Position         */\r
+#define VADC_G_REVNP1_REV11NP_Msk             (0x0fUL << VADC_G_REVNP1_REV11NP_Pos)                   /*!< VADC_G REVNP1: REV11NP Mask             */\r
+#define VADC_G_REVNP1_REV12NP_Pos             16                                                      /*!< VADC_G REVNP1: REV12NP Position         */\r
+#define VADC_G_REVNP1_REV12NP_Msk             (0x0fUL << VADC_G_REVNP1_REV12NP_Pos)                   /*!< VADC_G REVNP1: REV12NP Mask             */\r
+#define VADC_G_REVNP1_REV13NP_Pos             20                                                      /*!< VADC_G REVNP1: REV13NP Position         */\r
+#define VADC_G_REVNP1_REV13NP_Msk             (0x0fUL << VADC_G_REVNP1_REV13NP_Pos)                   /*!< VADC_G REVNP1: REV13NP Mask             */\r
+#define VADC_G_REVNP1_REV14NP_Pos             24                                                      /*!< VADC_G REVNP1: REV14NP Position         */\r
+#define VADC_G_REVNP1_REV14NP_Msk             (0x0fUL << VADC_G_REVNP1_REV14NP_Pos)                   /*!< VADC_G REVNP1: REV14NP Mask             */\r
+#define VADC_G_REVNP1_REV15NP_Pos             28                                                      /*!< VADC_G REVNP1: REV15NP Position         */\r
+#define VADC_G_REVNP1_REV15NP_Msk             (0x0fUL << VADC_G_REVNP1_REV15NP_Pos)                   /*!< VADC_G REVNP1: REV15NP Mask             */\r
+\r
+/* --------------------------------  VADC_G_SEVNP  -------------------------------- */\r
+#define VADC_G_SEVNP_SEV0NP_Pos               0                                                       /*!< VADC_G SEVNP: SEV0NP Position           */\r
+#define VADC_G_SEVNP_SEV0NP_Msk               (0x0fUL << VADC_G_SEVNP_SEV0NP_Pos)                     /*!< VADC_G SEVNP: SEV0NP Mask               */\r
+#define VADC_G_SEVNP_SEV1NP_Pos               4                                                       /*!< VADC_G SEVNP: SEV1NP Position           */\r
+#define VADC_G_SEVNP_SEV1NP_Msk               (0x0fUL << VADC_G_SEVNP_SEV1NP_Pos)                     /*!< VADC_G SEVNP: SEV1NP Mask               */\r
+\r
+/* --------------------------------  VADC_G_SRACT  -------------------------------- */\r
+#define VADC_G_SRACT_AGSR0_Pos                0                                                       /*!< VADC_G SRACT: AGSR0 Position            */\r
+#define VADC_G_SRACT_AGSR0_Msk                (0x01UL << VADC_G_SRACT_AGSR0_Pos)                      /*!< VADC_G SRACT: AGSR0 Mask                */\r
+#define VADC_G_SRACT_AGSR1_Pos                1                                                       /*!< VADC_G SRACT: AGSR1 Position            */\r
+#define VADC_G_SRACT_AGSR1_Msk                (0x01UL << VADC_G_SRACT_AGSR1_Pos)                      /*!< VADC_G SRACT: AGSR1 Mask                */\r
+#define VADC_G_SRACT_AGSR2_Pos                2                                                       /*!< VADC_G SRACT: AGSR2 Position            */\r
+#define VADC_G_SRACT_AGSR2_Msk                (0x01UL << VADC_G_SRACT_AGSR2_Pos)                      /*!< VADC_G SRACT: AGSR2 Mask                */\r
+#define VADC_G_SRACT_AGSR3_Pos                3                                                       /*!< VADC_G SRACT: AGSR3 Position            */\r
+#define VADC_G_SRACT_AGSR3_Msk                (0x01UL << VADC_G_SRACT_AGSR3_Pos)                      /*!< VADC_G SRACT: AGSR3 Mask                */\r
+#define VADC_G_SRACT_ASSR0_Pos                8                                                       /*!< VADC_G SRACT: ASSR0 Position            */\r
+#define VADC_G_SRACT_ASSR0_Msk                (0x01UL << VADC_G_SRACT_ASSR0_Pos)                      /*!< VADC_G SRACT: ASSR0 Mask                */\r
+#define VADC_G_SRACT_ASSR1_Pos                9                                                       /*!< VADC_G SRACT: ASSR1 Position            */\r
+#define VADC_G_SRACT_ASSR1_Msk                (0x01UL << VADC_G_SRACT_ASSR1_Pos)                      /*!< VADC_G SRACT: ASSR1 Mask                */\r
+#define VADC_G_SRACT_ASSR2_Pos                10                                                      /*!< VADC_G SRACT: ASSR2 Position            */\r
+#define VADC_G_SRACT_ASSR2_Msk                (0x01UL << VADC_G_SRACT_ASSR2_Pos)                      /*!< VADC_G SRACT: ASSR2 Mask                */\r
+#define VADC_G_SRACT_ASSR3_Pos                11                                                      /*!< VADC_G SRACT: ASSR3 Position            */\r
+#define VADC_G_SRACT_ASSR3_Msk                (0x01UL << VADC_G_SRACT_ASSR3_Pos)                      /*!< VADC_G SRACT: ASSR3 Mask                */\r
+\r
+/* -------------------------------  VADC_G_EMUXCTR  ------------------------------- */\r
+#define VADC_G_EMUXCTR_EMUXSET_Pos            0                                                       /*!< VADC_G EMUXCTR: EMUXSET Position        */\r
+#define VADC_G_EMUXCTR_EMUXSET_Msk            (0x07UL << VADC_G_EMUXCTR_EMUXSET_Pos)                  /*!< VADC_G EMUXCTR: EMUXSET Mask            */\r
+#define VADC_G_EMUXCTR_EMUXACT_Pos            8                                                       /*!< VADC_G EMUXCTR: EMUXACT Position        */\r
+#define VADC_G_EMUXCTR_EMUXACT_Msk            (0x07UL << VADC_G_EMUXCTR_EMUXACT_Pos)                  /*!< VADC_G EMUXCTR: EMUXACT Mask            */\r
+#define VADC_G_EMUXCTR_EMUXCH_Pos             16                                                      /*!< VADC_G EMUXCTR: EMUXCH Position         */\r
+#define VADC_G_EMUXCTR_EMUXCH_Msk             (0x1fUL << VADC_G_EMUXCTR_EMUXCH_Pos)                   /*!< VADC_G EMUXCTR: EMUXCH Mask             */\r
+#define VADC_G_EMUXCTR_EMUXMODE_Pos           26                                                      /*!< VADC_G EMUXCTR: EMUXMODE Position       */\r
+#define VADC_G_EMUXCTR_EMUXMODE_Msk           (0x03UL << VADC_G_EMUXCTR_EMUXMODE_Pos)                 /*!< VADC_G EMUXCTR: EMUXMODE Mask           */\r
+#define VADC_G_EMUXCTR_EMXCOD_Pos             28                                                      /*!< VADC_G EMUXCTR: EMXCOD Position         */\r
+#define VADC_G_EMUXCTR_EMXCOD_Msk             (0x01UL << VADC_G_EMUXCTR_EMXCOD_Pos)                   /*!< VADC_G EMUXCTR: EMXCOD Mask             */\r
+#define VADC_G_EMUXCTR_EMXST_Pos              29                                                      /*!< VADC_G EMUXCTR: EMXST Position          */\r
+#define VADC_G_EMUXCTR_EMXST_Msk              (0x01UL << VADC_G_EMUXCTR_EMXST_Pos)                    /*!< VADC_G EMUXCTR: EMXST Mask              */\r
+#define VADC_G_EMUXCTR_EMXWC_Pos              31                                                      /*!< VADC_G EMUXCTR: EMXWC Position          */\r
+#define VADC_G_EMUXCTR_EMXWC_Msk              (0x01UL << VADC_G_EMUXCTR_EMXWC_Pos)                    /*!< VADC_G EMUXCTR: EMXWC Mask              */\r
+\r
+/* ---------------------------------  VADC_G_VFR  --------------------------------- */\r
+#define VADC_G_VFR_VF0_Pos                    0                                                       /*!< VADC_G VFR: VF0 Position                */\r
+#define VADC_G_VFR_VF0_Msk                    (0x01UL << VADC_G_VFR_VF0_Pos)                          /*!< VADC_G VFR: VF0 Mask                    */\r
+#define VADC_G_VFR_VF1_Pos                    1                                                       /*!< VADC_G VFR: VF1 Position                */\r
+#define VADC_G_VFR_VF1_Msk                    (0x01UL << VADC_G_VFR_VF1_Pos)                          /*!< VADC_G VFR: VF1 Mask                    */\r
+#define VADC_G_VFR_VF2_Pos                    2                                                       /*!< VADC_G VFR: VF2 Position                */\r
+#define VADC_G_VFR_VF2_Msk                    (0x01UL << VADC_G_VFR_VF2_Pos)                          /*!< VADC_G VFR: VF2 Mask                    */\r
+#define VADC_G_VFR_VF3_Pos                    3                                                       /*!< VADC_G VFR: VF3 Position                */\r
+#define VADC_G_VFR_VF3_Msk                    (0x01UL << VADC_G_VFR_VF3_Pos)                          /*!< VADC_G VFR: VF3 Mask                    */\r
+#define VADC_G_VFR_VF4_Pos                    4                                                       /*!< VADC_G VFR: VF4 Position                */\r
+#define VADC_G_VFR_VF4_Msk                    (0x01UL << VADC_G_VFR_VF4_Pos)                          /*!< VADC_G VFR: VF4 Mask                    */\r
+#define VADC_G_VFR_VF5_Pos                    5                                                       /*!< VADC_G VFR: VF5 Position                */\r
+#define VADC_G_VFR_VF5_Msk                    (0x01UL << VADC_G_VFR_VF5_Pos)                          /*!< VADC_G VFR: VF5 Mask                    */\r
+#define VADC_G_VFR_VF6_Pos                    6                                                       /*!< VADC_G VFR: VF6 Position                */\r
+#define VADC_G_VFR_VF6_Msk                    (0x01UL << VADC_G_VFR_VF6_Pos)                          /*!< VADC_G VFR: VF6 Mask                    */\r
+#define VADC_G_VFR_VF7_Pos                    7                                                       /*!< VADC_G VFR: VF7 Position                */\r
+#define VADC_G_VFR_VF7_Msk                    (0x01UL << VADC_G_VFR_VF7_Pos)                          /*!< VADC_G VFR: VF7 Mask                    */\r
+#define VADC_G_VFR_VF8_Pos                    8                                                       /*!< VADC_G VFR: VF8 Position                */\r
+#define VADC_G_VFR_VF8_Msk                    (0x01UL << VADC_G_VFR_VF8_Pos)                          /*!< VADC_G VFR: VF8 Mask                    */\r
+#define VADC_G_VFR_VF9_Pos                    9                                                       /*!< VADC_G VFR: VF9 Position                */\r
+#define VADC_G_VFR_VF9_Msk                    (0x01UL << VADC_G_VFR_VF9_Pos)                          /*!< VADC_G VFR: VF9 Mask                    */\r
+#define VADC_G_VFR_VF10_Pos                   10                                                      /*!< VADC_G VFR: VF10 Position               */\r
+#define VADC_G_VFR_VF10_Msk                   (0x01UL << VADC_G_VFR_VF10_Pos)                         /*!< VADC_G VFR: VF10 Mask                   */\r
+#define VADC_G_VFR_VF11_Pos                   11                                                      /*!< VADC_G VFR: VF11 Position               */\r
+#define VADC_G_VFR_VF11_Msk                   (0x01UL << VADC_G_VFR_VF11_Pos)                         /*!< VADC_G VFR: VF11 Mask                   */\r
+#define VADC_G_VFR_VF12_Pos                   12                                                      /*!< VADC_G VFR: VF12 Position               */\r
+#define VADC_G_VFR_VF12_Msk                   (0x01UL << VADC_G_VFR_VF12_Pos)                         /*!< VADC_G VFR: VF12 Mask                   */\r
+#define VADC_G_VFR_VF13_Pos                   13                                                      /*!< VADC_G VFR: VF13 Position               */\r
+#define VADC_G_VFR_VF13_Msk                   (0x01UL << VADC_G_VFR_VF13_Pos)                         /*!< VADC_G VFR: VF13 Mask                   */\r
+#define VADC_G_VFR_VF14_Pos                   14                                                      /*!< VADC_G VFR: VF14 Position               */\r
+#define VADC_G_VFR_VF14_Msk                   (0x01UL << VADC_G_VFR_VF14_Pos)                         /*!< VADC_G VFR: VF14 Mask                   */\r
+#define VADC_G_VFR_VF15_Pos                   15                                                      /*!< VADC_G VFR: VF15 Position               */\r
+#define VADC_G_VFR_VF15_Msk                   (0x01UL << VADC_G_VFR_VF15_Pos)                         /*!< VADC_G VFR: VF15 Mask                   */\r
+\r
+/* --------------------------------  VADC_G_CHCTR  -------------------------------- */\r
+#define VADC_G_CHCTR_ICLSEL_Pos               0                                                       /*!< VADC_G CHCTR: ICLSEL Position           */\r
+#define VADC_G_CHCTR_ICLSEL_Msk               (0x03UL << VADC_G_CHCTR_ICLSEL_Pos)                     /*!< VADC_G CHCTR: ICLSEL Mask               */\r
+#define VADC_G_CHCTR_BNDSELL_Pos              4                                                       /*!< VADC_G CHCTR: BNDSELL Position          */\r
+#define VADC_G_CHCTR_BNDSELL_Msk              (0x03UL << VADC_G_CHCTR_BNDSELL_Pos)                    /*!< VADC_G CHCTR: BNDSELL Mask              */\r
+#define VADC_G_CHCTR_BNDSELU_Pos              6                                                       /*!< VADC_G CHCTR: BNDSELU Position          */\r
+#define VADC_G_CHCTR_BNDSELU_Msk              (0x03UL << VADC_G_CHCTR_BNDSELU_Pos)                    /*!< VADC_G CHCTR: BNDSELU Mask              */\r
+#define VADC_G_CHCTR_CHEVMODE_Pos             8                                                       /*!< VADC_G CHCTR: CHEVMODE Position         */\r
+#define VADC_G_CHCTR_CHEVMODE_Msk             (0x03UL << VADC_G_CHCTR_CHEVMODE_Pos)                   /*!< VADC_G CHCTR: CHEVMODE Mask             */\r
+#define VADC_G_CHCTR_SYNC_Pos                 10                                                      /*!< VADC_G CHCTR: SYNC Position             */\r
+#define VADC_G_CHCTR_SYNC_Msk                 (0x01UL << VADC_G_CHCTR_SYNC_Pos)                       /*!< VADC_G CHCTR: SYNC Mask                 */\r
+#define VADC_G_CHCTR_REFSEL_Pos               11                                                      /*!< VADC_G CHCTR: REFSEL Position           */\r
+#define VADC_G_CHCTR_REFSEL_Msk               (0x01UL << VADC_G_CHCTR_REFSEL_Pos)                     /*!< VADC_G CHCTR: REFSEL Mask               */\r
+#define VADC_G_CHCTR_RESREG_Pos               16                                                      /*!< VADC_G CHCTR: RESREG Position           */\r
+#define VADC_G_CHCTR_RESREG_Msk               (0x0fUL << VADC_G_CHCTR_RESREG_Pos)                     /*!< VADC_G CHCTR: RESREG Mask               */\r
+#define VADC_G_CHCTR_RESTBS_Pos               20                                                      /*!< VADC_G CHCTR: RESTBS Position           */\r
+#define VADC_G_CHCTR_RESTBS_Msk               (0x01UL << VADC_G_CHCTR_RESTBS_Pos)                     /*!< VADC_G CHCTR: RESTBS Mask               */\r
+#define VADC_G_CHCTR_RESPOS_Pos               21                                                      /*!< VADC_G CHCTR: RESPOS Position           */\r
+#define VADC_G_CHCTR_RESPOS_Msk               (0x01UL << VADC_G_CHCTR_RESPOS_Pos)                     /*!< VADC_G CHCTR: RESPOS Mask               */\r
+#define VADC_G_CHCTR_BWDCH_Pos                28                                                      /*!< VADC_G CHCTR: BWDCH Position            */\r
+#define VADC_G_CHCTR_BWDCH_Msk                (0x03UL << VADC_G_CHCTR_BWDCH_Pos)                      /*!< VADC_G CHCTR: BWDCH Mask                */\r
+#define VADC_G_CHCTR_BWDEN_Pos                30                                                      /*!< VADC_G CHCTR: BWDEN Position            */\r
+#define VADC_G_CHCTR_BWDEN_Msk                (0x01UL << VADC_G_CHCTR_BWDEN_Pos)                      /*!< VADC_G CHCTR: BWDEN Mask                */\r
+\r
+/* ---------------------------------  VADC_G_RCR  --------------------------------- */\r
+#define VADC_G_RCR_DRCTR_Pos                  16                                                      /*!< VADC_G RCR: DRCTR Position              */\r
+#define VADC_G_RCR_DRCTR_Msk                  (0x0fUL << VADC_G_RCR_DRCTR_Pos)                        /*!< VADC_G RCR: DRCTR Mask                  */\r
+#define VADC_G_RCR_DMM_Pos                    20                                                      /*!< VADC_G RCR: DMM Position                */\r
+#define VADC_G_RCR_DMM_Msk                    (0x03UL << VADC_G_RCR_DMM_Pos)                          /*!< VADC_G RCR: DMM Mask                    */\r
+#define VADC_G_RCR_WFR_Pos                    24                                                      /*!< VADC_G RCR: WFR Position                */\r
+#define VADC_G_RCR_WFR_Msk                    (0x01UL << VADC_G_RCR_WFR_Pos)                          /*!< VADC_G RCR: WFR Mask                    */\r
+#define VADC_G_RCR_FEN_Pos                    25                                                      /*!< VADC_G RCR: FEN Position                */\r
+#define VADC_G_RCR_FEN_Msk                    (0x03UL << VADC_G_RCR_FEN_Pos)                          /*!< VADC_G RCR: FEN Mask                    */\r
+#define VADC_G_RCR_SRGEN_Pos                  31                                                      /*!< VADC_G RCR: SRGEN Position              */\r
+#define VADC_G_RCR_SRGEN_Msk                  (0x01UL << VADC_G_RCR_SRGEN_Pos)                        /*!< VADC_G RCR: SRGEN Mask                  */\r
+\r
+/* ---------------------------------  VADC_G_RES  --------------------------------- */\r
+#define VADC_G_RES_RESULT_Pos                 0                                                       /*!< VADC_G RES: RESULT Position             */\r
+#define VADC_G_RES_RESULT_Msk                 (0x0000ffffUL << VADC_G_RES_RESULT_Pos)                 /*!< VADC_G RES: RESULT Mask                 */\r
+#define VADC_G_RES_DRC_Pos                    16                                                      /*!< VADC_G RES: DRC Position                */\r
+#define VADC_G_RES_DRC_Msk                    (0x0fUL << VADC_G_RES_DRC_Pos)                          /*!< VADC_G RES: DRC Mask                    */\r
+#define VADC_G_RES_CHNR_Pos                   20                                                      /*!< VADC_G RES: CHNR Position               */\r
+#define VADC_G_RES_CHNR_Msk                   (0x1fUL << VADC_G_RES_CHNR_Pos)                         /*!< VADC_G RES: CHNR Mask                   */\r
+#define VADC_G_RES_EMUX_Pos                   25                                                      /*!< VADC_G RES: EMUX Position               */\r
+#define VADC_G_RES_EMUX_Msk                   (0x07UL << VADC_G_RES_EMUX_Pos)                         /*!< VADC_G RES: EMUX Mask                   */\r
+#define VADC_G_RES_CRS_Pos                    28                                                      /*!< VADC_G RES: CRS Position                */\r
+#define VADC_G_RES_CRS_Msk                    (0x03UL << VADC_G_RES_CRS_Pos)                          /*!< VADC_G RES: CRS Mask                    */\r
+#define VADC_G_RES_FCR_Pos                    30                                                      /*!< VADC_G RES: FCR Position                */\r
+#define VADC_G_RES_FCR_Msk                    (0x01UL << VADC_G_RES_FCR_Pos)                          /*!< VADC_G RES: FCR Mask                    */\r
+#define VADC_G_RES_VF_Pos                     31                                                      /*!< VADC_G RES: VF Position                 */\r
+#define VADC_G_RES_VF_Msk                     (0x01UL << VADC_G_RES_VF_Pos)                           /*!< VADC_G RES: VF Mask                     */\r
+\r
+/* ---------------------------------  VADC_G_RESD  -------------------------------- */\r
+#define VADC_G_RESD_RESULT_Pos                0                                                       /*!< VADC_G RESD: RESULT Position            */\r
+#define VADC_G_RESD_RESULT_Msk                (0x0000ffffUL << VADC_G_RESD_RESULT_Pos)                /*!< VADC_G RESD: RESULT Mask                */\r
+#define VADC_G_RESD_DRC_Pos                   16                                                      /*!< VADC_G RESD: DRC Position               */\r
+#define VADC_G_RESD_DRC_Msk                   (0x0fUL << VADC_G_RESD_DRC_Pos)                         /*!< VADC_G RESD: DRC Mask                   */\r
+#define VADC_G_RESD_CHNR_Pos                  20                                                      /*!< VADC_G RESD: CHNR Position              */\r
+#define VADC_G_RESD_CHNR_Msk                  (0x1fUL << VADC_G_RESD_CHNR_Pos)                        /*!< VADC_G RESD: CHNR Mask                  */\r
+#define VADC_G_RESD_EMUX_Pos                  25                                                      /*!< VADC_G RESD: EMUX Position              */\r
+#define VADC_G_RESD_EMUX_Msk                  (0x07UL << VADC_G_RESD_EMUX_Pos)                        /*!< VADC_G RESD: EMUX Mask                  */\r
+#define VADC_G_RESD_CRS_Pos                   28                                                      /*!< VADC_G RESD: CRS Position               */\r
+#define VADC_G_RESD_CRS_Msk                   (0x03UL << VADC_G_RESD_CRS_Pos)                         /*!< VADC_G RESD: CRS Mask                   */\r
+#define VADC_G_RESD_FCR_Pos                   30                                                      /*!< VADC_G RESD: FCR Position               */\r
+#define VADC_G_RESD_FCR_Msk                   (0x01UL << VADC_G_RESD_FCR_Pos)                         /*!< VADC_G RESD: FCR Mask                   */\r
+#define VADC_G_RESD_VF_Pos                    31                                                      /*!< VADC_G RESD: VF Position                */\r
+#define VADC_G_RESD_VF_Msk                    (0x01UL << VADC_G_RESD_VF_Pos)                          /*!< VADC_G RESD: VF Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'DSD' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  DSD_CLC  ---------------------------------- */\r
+#define DSD_CLC_DISR_Pos                      0                                                       /*!< DSD CLC: DISR Position                  */\r
+#define DSD_CLC_DISR_Msk                      (0x01UL << DSD_CLC_DISR_Pos)                            /*!< DSD CLC: DISR Mask                      */\r
+#define DSD_CLC_DISS_Pos                      1                                                       /*!< DSD CLC: DISS Position                  */\r
+#define DSD_CLC_DISS_Msk                      (0x01UL << DSD_CLC_DISS_Pos)                            /*!< DSD CLC: DISS Mask                      */\r
+#define DSD_CLC_EDIS_Pos                      3                                                       /*!< DSD CLC: EDIS Position                  */\r
+#define DSD_CLC_EDIS_Msk                      (0x01UL << DSD_CLC_EDIS_Pos)                            /*!< DSD CLC: EDIS Mask                      */\r
+\r
+/* -----------------------------------  DSD_ID  ----------------------------------- */\r
+#define DSD_ID_MOD_REV_Pos                    0                                                       /*!< DSD ID: MOD_REV Position                */\r
+#define DSD_ID_MOD_REV_Msk                    (0x000000ffUL << DSD_ID_MOD_REV_Pos)                    /*!< DSD ID: MOD_REV Mask                    */\r
+#define DSD_ID_MOD_TYPE_Pos                   8                                                       /*!< DSD ID: MOD_TYPE Position               */\r
+#define DSD_ID_MOD_TYPE_Msk                   (0x000000ffUL << DSD_ID_MOD_TYPE_Pos)                   /*!< DSD ID: MOD_TYPE Mask                   */\r
+#define DSD_ID_MOD_NUMBER_Pos                 16                                                      /*!< DSD ID: MOD_NUMBER Position             */\r
+#define DSD_ID_MOD_NUMBER_Msk                 (0x0000ffffUL << DSD_ID_MOD_NUMBER_Pos)                 /*!< DSD ID: MOD_NUMBER Mask                 */\r
+\r
+/* -----------------------------------  DSD_OCS  ---------------------------------- */\r
+#define DSD_OCS_SUS_Pos                       24                                                      /*!< DSD OCS: SUS Position                   */\r
+#define DSD_OCS_SUS_Msk                       (0x0fUL << DSD_OCS_SUS_Pos)                             /*!< DSD OCS: SUS Mask                       */\r
+#define DSD_OCS_SUS_P_Pos                     28                                                      /*!< DSD OCS: SUS_P Position                 */\r
+#define DSD_OCS_SUS_P_Msk                     (0x01UL << DSD_OCS_SUS_P_Pos)                           /*!< DSD OCS: SUS_P Mask                     */\r
+#define DSD_OCS_SUSSTA_Pos                    29                                                      /*!< DSD OCS: SUSSTA Position                */\r
+#define DSD_OCS_SUSSTA_Msk                    (0x01UL << DSD_OCS_SUSSTA_Pos)                          /*!< DSD OCS: SUSSTA Mask                    */\r
+\r
+/* ---------------------------------  DSD_GLOBCFG  -------------------------------- */\r
+#define DSD_GLOBCFG_MCSEL_Pos                 0                                                       /*!< DSD GLOBCFG: MCSEL Position             */\r
+#define DSD_GLOBCFG_MCSEL_Msk                 (0x07UL << DSD_GLOBCFG_MCSEL_Pos)                       /*!< DSD GLOBCFG: MCSEL Mask                 */\r
+\r
+/* ---------------------------------  DSD_GLOBRC  --------------------------------- */\r
+#define DSD_GLOBRC_CH0RUN_Pos                 0                                                       /*!< DSD GLOBRC: CH0RUN Position             */\r
+#define DSD_GLOBRC_CH0RUN_Msk                 (0x01UL << DSD_GLOBRC_CH0RUN_Pos)                       /*!< DSD GLOBRC: CH0RUN Mask                 */\r
+#define DSD_GLOBRC_CH1RUN_Pos                 1                                                       /*!< DSD GLOBRC: CH1RUN Position             */\r
+#define DSD_GLOBRC_CH1RUN_Msk                 (0x01UL << DSD_GLOBRC_CH1RUN_Pos)                       /*!< DSD GLOBRC: CH1RUN Mask                 */\r
+#define DSD_GLOBRC_CH2RUN_Pos                 2                                                       /*!< DSD GLOBRC: CH2RUN Position             */\r
+#define DSD_GLOBRC_CH2RUN_Msk                 (0x01UL << DSD_GLOBRC_CH2RUN_Pos)                       /*!< DSD GLOBRC: CH2RUN Mask                 */\r
+#define DSD_GLOBRC_CH3RUN_Pos                 3                                                       /*!< DSD GLOBRC: CH3RUN Position             */\r
+#define DSD_GLOBRC_CH3RUN_Msk                 (0x01UL << DSD_GLOBRC_CH3RUN_Pos)                       /*!< DSD GLOBRC: CH3RUN Mask                 */\r
+\r
+/* ----------------------------------  DSD_CGCFG  --------------------------------- */\r
+#define DSD_CGCFG_CGMOD_Pos                   0                                                       /*!< DSD CGCFG: CGMOD Position               */\r
+#define DSD_CGCFG_CGMOD_Msk                   (0x03UL << DSD_CGCFG_CGMOD_Pos)                         /*!< DSD CGCFG: CGMOD Mask                   */\r
+#define DSD_CGCFG_BREV_Pos                    2                                                       /*!< DSD CGCFG: BREV Position                */\r
+#define DSD_CGCFG_BREV_Msk                    (0x01UL << DSD_CGCFG_BREV_Pos)                          /*!< DSD CGCFG: BREV Mask                    */\r
+#define DSD_CGCFG_SIGPOL_Pos                  3                                                       /*!< DSD CGCFG: SIGPOL Position              */\r
+#define DSD_CGCFG_SIGPOL_Msk                  (0x01UL << DSD_CGCFG_SIGPOL_Pos)                        /*!< DSD CGCFG: SIGPOL Mask                  */\r
+#define DSD_CGCFG_DIVCG_Pos                   4                                                       /*!< DSD CGCFG: DIVCG Position               */\r
+#define DSD_CGCFG_DIVCG_Msk                   (0x0fUL << DSD_CGCFG_DIVCG_Pos)                         /*!< DSD CGCFG: DIVCG Mask                   */\r
+#define DSD_CGCFG_RUN_Pos                     15                                                      /*!< DSD CGCFG: RUN Position                 */\r
+#define DSD_CGCFG_RUN_Msk                     (0x01UL << DSD_CGCFG_RUN_Pos)                           /*!< DSD CGCFG: RUN Mask                     */\r
+#define DSD_CGCFG_BITCOUNT_Pos                16                                                      /*!< DSD CGCFG: BITCOUNT Position            */\r
+#define DSD_CGCFG_BITCOUNT_Msk                (0x1fUL << DSD_CGCFG_BITCOUNT_Pos)                      /*!< DSD CGCFG: BITCOUNT Mask                */\r
+#define DSD_CGCFG_STEPCOUNT_Pos               24                                                      /*!< DSD CGCFG: STEPCOUNT Position           */\r
+#define DSD_CGCFG_STEPCOUNT_Msk               (0x0fUL << DSD_CGCFG_STEPCOUNT_Pos)                     /*!< DSD CGCFG: STEPCOUNT Mask               */\r
+#define DSD_CGCFG_STEPS_Pos                   28                                                      /*!< DSD CGCFG: STEPS Position               */\r
+#define DSD_CGCFG_STEPS_Msk                   (0x01UL << DSD_CGCFG_STEPS_Pos)                         /*!< DSD CGCFG: STEPS Mask                   */\r
+#define DSD_CGCFG_STEPD_Pos                   29                                                      /*!< DSD CGCFG: STEPD Position               */\r
+#define DSD_CGCFG_STEPD_Msk                   (0x01UL << DSD_CGCFG_STEPD_Pos)                         /*!< DSD CGCFG: STEPD Mask                   */\r
+#define DSD_CGCFG_SGNCG_Pos                   30                                                      /*!< DSD CGCFG: SGNCG Position               */\r
+#define DSD_CGCFG_SGNCG_Msk                   (0x01UL << DSD_CGCFG_SGNCG_Pos)                         /*!< DSD CGCFG: SGNCG Mask                   */\r
+\r
+/* ---------------------------------  DSD_EVFLAG  --------------------------------- */\r
+#define DSD_EVFLAG_RESEV0_Pos                 0                                                       /*!< DSD EVFLAG: RESEV0 Position             */\r
+#define DSD_EVFLAG_RESEV0_Msk                 (0x01UL << DSD_EVFLAG_RESEV0_Pos)                       /*!< DSD EVFLAG: RESEV0 Mask                 */\r
+#define DSD_EVFLAG_RESEV1_Pos                 1                                                       /*!< DSD EVFLAG: RESEV1 Position             */\r
+#define DSD_EVFLAG_RESEV1_Msk                 (0x01UL << DSD_EVFLAG_RESEV1_Pos)                       /*!< DSD EVFLAG: RESEV1 Mask                 */\r
+#define DSD_EVFLAG_RESEV2_Pos                 2                                                       /*!< DSD EVFLAG: RESEV2 Position             */\r
+#define DSD_EVFLAG_RESEV2_Msk                 (0x01UL << DSD_EVFLAG_RESEV2_Pos)                       /*!< DSD EVFLAG: RESEV2 Mask                 */\r
+#define DSD_EVFLAG_RESEV3_Pos                 3                                                       /*!< DSD EVFLAG: RESEV3 Position             */\r
+#define DSD_EVFLAG_RESEV3_Msk                 (0x01UL << DSD_EVFLAG_RESEV3_Pos)                       /*!< DSD EVFLAG: RESEV3 Mask                 */\r
+#define DSD_EVFLAG_ALEV0_Pos                  16                                                      /*!< DSD EVFLAG: ALEV0 Position              */\r
+#define DSD_EVFLAG_ALEV0_Msk                  (0x01UL << DSD_EVFLAG_ALEV0_Pos)                        /*!< DSD EVFLAG: ALEV0 Mask                  */\r
+#define DSD_EVFLAG_ALEV1_Pos                  17                                                      /*!< DSD EVFLAG: ALEV1 Position              */\r
+#define DSD_EVFLAG_ALEV1_Msk                  (0x01UL << DSD_EVFLAG_ALEV1_Pos)                        /*!< DSD EVFLAG: ALEV1 Mask                  */\r
+#define DSD_EVFLAG_ALEV2_Pos                  18                                                      /*!< DSD EVFLAG: ALEV2 Position              */\r
+#define DSD_EVFLAG_ALEV2_Msk                  (0x01UL << DSD_EVFLAG_ALEV2_Pos)                        /*!< DSD EVFLAG: ALEV2 Mask                  */\r
+#define DSD_EVFLAG_ALEV3_Pos                  19                                                      /*!< DSD EVFLAG: ALEV3 Position              */\r
+#define DSD_EVFLAG_ALEV3_Msk                  (0x01UL << DSD_EVFLAG_ALEV3_Pos)                        /*!< DSD EVFLAG: ALEV3 Mask                  */\r
+#define DSD_EVFLAG_ALEV4_Pos                  20                                                      /*!< DSD EVFLAG: ALEV4 Position              */\r
+#define DSD_EVFLAG_ALEV4_Msk                  (0x01UL << DSD_EVFLAG_ALEV4_Pos)                        /*!< DSD EVFLAG: ALEV4 Mask                  */\r
+#define DSD_EVFLAG_ALEV5_Pos                  21                                                      /*!< DSD EVFLAG: ALEV5 Position              */\r
+#define DSD_EVFLAG_ALEV5_Msk                  (0x01UL << DSD_EVFLAG_ALEV5_Pos)                        /*!< DSD EVFLAG: ALEV5 Mask                  */\r
+#define DSD_EVFLAG_ALEV6_Pos                  22                                                      /*!< DSD EVFLAG: ALEV6 Position              */\r
+#define DSD_EVFLAG_ALEV6_Msk                  (0x01UL << DSD_EVFLAG_ALEV6_Pos)                        /*!< DSD EVFLAG: ALEV6 Mask                  */\r
+#define DSD_EVFLAG_ALEV7_Pos                  23                                                      /*!< DSD EVFLAG: ALEV7 Position              */\r
+#define DSD_EVFLAG_ALEV7_Msk                  (0x01UL << DSD_EVFLAG_ALEV7_Pos)                        /*!< DSD EVFLAG: ALEV7 Mask                  */\r
+#define DSD_EVFLAG_ALEV8_Pos                  24                                                      /*!< DSD EVFLAG: ALEV8 Position              */\r
+#define DSD_EVFLAG_ALEV8_Msk                  (0x01UL << DSD_EVFLAG_ALEV8_Pos)                        /*!< DSD EVFLAG: ALEV8 Mask                  */\r
+#define DSD_EVFLAG_ALEV9_Pos                  25                                                      /*!< DSD EVFLAG: ALEV9 Position              */\r
+#define DSD_EVFLAG_ALEV9_Msk                  (0x01UL << DSD_EVFLAG_ALEV9_Pos)                        /*!< DSD EVFLAG: ALEV9 Mask                  */\r
+\r
+/* --------------------------------  DSD_EVFLAGCLR  ------------------------------- */\r
+#define DSD_EVFLAGCLR_RESEC0_Pos              0                                                       /*!< DSD EVFLAGCLR: RESEC0 Position          */\r
+#define DSD_EVFLAGCLR_RESEC0_Msk              (0x01UL << DSD_EVFLAGCLR_RESEC0_Pos)                    /*!< DSD EVFLAGCLR: RESEC0 Mask              */\r
+#define DSD_EVFLAGCLR_RESEC1_Pos              1                                                       /*!< DSD EVFLAGCLR: RESEC1 Position          */\r
+#define DSD_EVFLAGCLR_RESEC1_Msk              (0x01UL << DSD_EVFLAGCLR_RESEC1_Pos)                    /*!< DSD EVFLAGCLR: RESEC1 Mask              */\r
+#define DSD_EVFLAGCLR_RESEC2_Pos              2                                                       /*!< DSD EVFLAGCLR: RESEC2 Position          */\r
+#define DSD_EVFLAGCLR_RESEC2_Msk              (0x01UL << DSD_EVFLAGCLR_RESEC2_Pos)                    /*!< DSD EVFLAGCLR: RESEC2 Mask              */\r
+#define DSD_EVFLAGCLR_RESEC3_Pos              3                                                       /*!< DSD EVFLAGCLR: RESEC3 Position          */\r
+#define DSD_EVFLAGCLR_RESEC3_Msk              (0x01UL << DSD_EVFLAGCLR_RESEC3_Pos)                    /*!< DSD EVFLAGCLR: RESEC3 Mask              */\r
+#define DSD_EVFLAGCLR_ALEC0_Pos               16                                                      /*!< DSD EVFLAGCLR: ALEC0 Position           */\r
+#define DSD_EVFLAGCLR_ALEC0_Msk               (0x01UL << DSD_EVFLAGCLR_ALEC0_Pos)                     /*!< DSD EVFLAGCLR: ALEC0 Mask               */\r
+#define DSD_EVFLAGCLR_ALEC1_Pos               17                                                      /*!< DSD EVFLAGCLR: ALEC1 Position           */\r
+#define DSD_EVFLAGCLR_ALEC1_Msk               (0x01UL << DSD_EVFLAGCLR_ALEC1_Pos)                     /*!< DSD EVFLAGCLR: ALEC1 Mask               */\r
+#define DSD_EVFLAGCLR_ALEC2_Pos               18                                                      /*!< DSD EVFLAGCLR: ALEC2 Position           */\r
+#define DSD_EVFLAGCLR_ALEC2_Msk               (0x01UL << DSD_EVFLAGCLR_ALEC2_Pos)                     /*!< DSD EVFLAGCLR: ALEC2 Mask               */\r
+#define DSD_EVFLAGCLR_ALEC3_Pos               19                                                      /*!< DSD EVFLAGCLR: ALEC3 Position           */\r
+#define DSD_EVFLAGCLR_ALEC3_Msk               (0x01UL << DSD_EVFLAGCLR_ALEC3_Pos)                     /*!< DSD EVFLAGCLR: ALEC3 Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         Group 'DSD_CH' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  DSD_CH_MODCFG  ------------------------------- */\r
+#define DSD_CH_MODCFG_DIVM_Pos                16                                                      /*!< DSD_CH MODCFG: DIVM Position            */\r
+#define DSD_CH_MODCFG_DIVM_Msk                (0x0fUL << DSD_CH_MODCFG_DIVM_Pos)                      /*!< DSD_CH MODCFG: DIVM Mask                */\r
+#define DSD_CH_MODCFG_DWC_Pos                 23                                                      /*!< DSD_CH MODCFG: DWC Position             */\r
+#define DSD_CH_MODCFG_DWC_Msk                 (0x01UL << DSD_CH_MODCFG_DWC_Pos)                       /*!< DSD_CH MODCFG: DWC Mask                 */\r
+\r
+/* --------------------------------  DSD_CH_DICFG  -------------------------------- */\r
+#define DSD_CH_DICFG_DSRC_Pos                 0                                                       /*!< DSD_CH DICFG: DSRC Position             */\r
+#define DSD_CH_DICFG_DSRC_Msk                 (0x0fUL << DSD_CH_DICFG_DSRC_Pos)                       /*!< DSD_CH DICFG: DSRC Mask                 */\r
+#define DSD_CH_DICFG_DSWC_Pos                 7                                                       /*!< DSD_CH DICFG: DSWC Position             */\r
+#define DSD_CH_DICFG_DSWC_Msk                 (0x01UL << DSD_CH_DICFG_DSWC_Pos)                       /*!< DSD_CH DICFG: DSWC Mask                 */\r
+#define DSD_CH_DICFG_ITRMODE_Pos              8                                                       /*!< DSD_CH DICFG: ITRMODE Position          */\r
+#define DSD_CH_DICFG_ITRMODE_Msk              (0x03UL << DSD_CH_DICFG_ITRMODE_Pos)                    /*!< DSD_CH DICFG: ITRMODE Mask              */\r
+#define DSD_CH_DICFG_TSTRMODE_Pos             10                                                      /*!< DSD_CH DICFG: TSTRMODE Position         */\r
+#define DSD_CH_DICFG_TSTRMODE_Msk             (0x03UL << DSD_CH_DICFG_TSTRMODE_Pos)                   /*!< DSD_CH DICFG: TSTRMODE Mask             */\r
+#define DSD_CH_DICFG_TRSEL_Pos                12                                                      /*!< DSD_CH DICFG: TRSEL Position            */\r
+#define DSD_CH_DICFG_TRSEL_Msk                (0x07UL << DSD_CH_DICFG_TRSEL_Pos)                      /*!< DSD_CH DICFG: TRSEL Mask                */\r
+#define DSD_CH_DICFG_TRWC_Pos                 15                                                      /*!< DSD_CH DICFG: TRWC Position             */\r
+#define DSD_CH_DICFG_TRWC_Msk                 (0x01UL << DSD_CH_DICFG_TRWC_Pos)                       /*!< DSD_CH DICFG: TRWC Mask                 */\r
+#define DSD_CH_DICFG_CSRC_Pos                 16                                                      /*!< DSD_CH DICFG: CSRC Position             */\r
+#define DSD_CH_DICFG_CSRC_Msk                 (0x0fUL << DSD_CH_DICFG_CSRC_Pos)                       /*!< DSD_CH DICFG: CSRC Mask                 */\r
+#define DSD_CH_DICFG_STROBE_Pos               20                                                      /*!< DSD_CH DICFG: STROBE Position           */\r
+#define DSD_CH_DICFG_STROBE_Msk               (0x0fUL << DSD_CH_DICFG_STROBE_Pos)                     /*!< DSD_CH DICFG: STROBE Mask               */\r
+#define DSD_CH_DICFG_SCWC_Pos                 31                                                      /*!< DSD_CH DICFG: SCWC Position             */\r
+#define DSD_CH_DICFG_SCWC_Msk                 (0x01UL << DSD_CH_DICFG_SCWC_Pos)                       /*!< DSD_CH DICFG: SCWC Mask                 */\r
+\r
+/* --------------------------------  DSD_CH_FCFGC  -------------------------------- */\r
+#define DSD_CH_FCFGC_CFMDF_Pos                0                                                       /*!< DSD_CH FCFGC: CFMDF Position            */\r
+#define DSD_CH_FCFGC_CFMDF_Msk                (0x000000ffUL << DSD_CH_FCFGC_CFMDF_Pos)                /*!< DSD_CH FCFGC: CFMDF Mask                */\r
+#define DSD_CH_FCFGC_CFMC_Pos                 8                                                       /*!< DSD_CH FCFGC: CFMC Position             */\r
+#define DSD_CH_FCFGC_CFMC_Msk                 (0x03UL << DSD_CH_FCFGC_CFMC_Pos)                       /*!< DSD_CH FCFGC: CFMC Mask                 */\r
+#define DSD_CH_FCFGC_CFEN_Pos                 10                                                      /*!< DSD_CH FCFGC: CFEN Position             */\r
+#define DSD_CH_FCFGC_CFEN_Msk                 (0x01UL << DSD_CH_FCFGC_CFEN_Pos)                       /*!< DSD_CH FCFGC: CFEN Mask                 */\r
+#define DSD_CH_FCFGC_SRGM_Pos                 14                                                      /*!< DSD_CH FCFGC: SRGM Position             */\r
+#define DSD_CH_FCFGC_SRGM_Msk                 (0x03UL << DSD_CH_FCFGC_SRGM_Pos)                       /*!< DSD_CH FCFGC: SRGM Mask                 */\r
+#define DSD_CH_FCFGC_CFMSV_Pos                16                                                      /*!< DSD_CH FCFGC: CFMSV Position            */\r
+#define DSD_CH_FCFGC_CFMSV_Msk                (0x000000ffUL << DSD_CH_FCFGC_CFMSV_Pos)                /*!< DSD_CH FCFGC: CFMSV Mask                */\r
+#define DSD_CH_FCFGC_CFMDCNT_Pos              24                                                      /*!< DSD_CH FCFGC: CFMDCNT Position          */\r
+#define DSD_CH_FCFGC_CFMDCNT_Msk              (0x000000ffUL << DSD_CH_FCFGC_CFMDCNT_Pos)              /*!< DSD_CH FCFGC: CFMDCNT Mask              */\r
+\r
+/* --------------------------------  DSD_CH_FCFGA  -------------------------------- */\r
+#define DSD_CH_FCFGA_CFADF_Pos                0                                                       /*!< DSD_CH FCFGA: CFADF Position            */\r
+#define DSD_CH_FCFGA_CFADF_Msk                (0x000000ffUL << DSD_CH_FCFGA_CFADF_Pos)                /*!< DSD_CH FCFGA: CFADF Mask                */\r
+#define DSD_CH_FCFGA_CFAC_Pos                 8                                                       /*!< DSD_CH FCFGA: CFAC Position             */\r
+#define DSD_CH_FCFGA_CFAC_Msk                 (0x03UL << DSD_CH_FCFGA_CFAC_Pos)                       /*!< DSD_CH FCFGA: CFAC Mask                 */\r
+#define DSD_CH_FCFGA_SRGA_Pos                 10                                                      /*!< DSD_CH FCFGA: SRGA Position             */\r
+#define DSD_CH_FCFGA_SRGA_Msk                 (0x03UL << DSD_CH_FCFGA_SRGA_Pos)                       /*!< DSD_CH FCFGA: SRGA Mask                 */\r
+#define DSD_CH_FCFGA_ESEL_Pos                 12                                                      /*!< DSD_CH FCFGA: ESEL Position             */\r
+#define DSD_CH_FCFGA_ESEL_Msk                 (0x03UL << DSD_CH_FCFGA_ESEL_Pos)                       /*!< DSD_CH FCFGA: ESEL Mask                 */\r
+#define DSD_CH_FCFGA_EGT_Pos                  14                                                      /*!< DSD_CH FCFGA: EGT Position              */\r
+#define DSD_CH_FCFGA_EGT_Msk                  (0x01UL << DSD_CH_FCFGA_EGT_Pos)                        /*!< DSD_CH FCFGA: EGT Mask                  */\r
+#define DSD_CH_FCFGA_CFADCNT_Pos              24                                                      /*!< DSD_CH FCFGA: CFADCNT Position          */\r
+#define DSD_CH_FCFGA_CFADCNT_Msk              (0x000000ffUL << DSD_CH_FCFGA_CFADCNT_Pos)              /*!< DSD_CH FCFGA: CFADCNT Mask              */\r
+\r
+/* --------------------------------  DSD_CH_IWCTR  -------------------------------- */\r
+#define DSD_CH_IWCTR_NVALCNT_Pos              0                                                       /*!< DSD_CH IWCTR: NVALCNT Position          */\r
+#define DSD_CH_IWCTR_NVALCNT_Msk              (0x3fUL << DSD_CH_IWCTR_NVALCNT_Pos)                    /*!< DSD_CH IWCTR: NVALCNT Mask              */\r
+#define DSD_CH_IWCTR_INTEN_Pos                7                                                       /*!< DSD_CH IWCTR: INTEN Position            */\r
+#define DSD_CH_IWCTR_INTEN_Msk                (0x01UL << DSD_CH_IWCTR_INTEN_Pos)                      /*!< DSD_CH IWCTR: INTEN Mask                */\r
+#define DSD_CH_IWCTR_REPCNT_Pos               8                                                       /*!< DSD_CH IWCTR: REPCNT Position           */\r
+#define DSD_CH_IWCTR_REPCNT_Msk               (0x0fUL << DSD_CH_IWCTR_REPCNT_Pos)                     /*!< DSD_CH IWCTR: REPCNT Mask               */\r
+#define DSD_CH_IWCTR_REPVAL_Pos               12                                                      /*!< DSD_CH IWCTR: REPVAL Position           */\r
+#define DSD_CH_IWCTR_REPVAL_Msk               (0x0fUL << DSD_CH_IWCTR_REPVAL_Pos)                     /*!< DSD_CH IWCTR: REPVAL Mask               */\r
+#define DSD_CH_IWCTR_NVALDIS_Pos              16                                                      /*!< DSD_CH IWCTR: NVALDIS Position          */\r
+#define DSD_CH_IWCTR_NVALDIS_Msk              (0x3fUL << DSD_CH_IWCTR_NVALDIS_Pos)                    /*!< DSD_CH IWCTR: NVALDIS Mask              */\r
+#define DSD_CH_IWCTR_IWS_Pos                  23                                                      /*!< DSD_CH IWCTR: IWS Position              */\r
+#define DSD_CH_IWCTR_IWS_Msk                  (0x01UL << DSD_CH_IWCTR_IWS_Pos)                        /*!< DSD_CH IWCTR: IWS Mask                  */\r
+#define DSD_CH_IWCTR_NVALINT_Pos              24                                                      /*!< DSD_CH IWCTR: NVALINT Position          */\r
+#define DSD_CH_IWCTR_NVALINT_Msk              (0x3fUL << DSD_CH_IWCTR_NVALINT_Pos)                    /*!< DSD_CH IWCTR: NVALINT Mask              */\r
+\r
+/* -------------------------------  DSD_CH_BOUNDSEL  ------------------------------ */\r
+#define DSD_CH_BOUNDSEL_BOUNDARYL_Pos         0                                                       /*!< DSD_CH BOUNDSEL: BOUNDARYL Position     */\r
+#define DSD_CH_BOUNDSEL_BOUNDARYL_Msk         (0x0000ffffUL << DSD_CH_BOUNDSEL_BOUNDARYL_Pos)         /*!< DSD_CH BOUNDSEL: BOUNDARYL Mask         */\r
+#define DSD_CH_BOUNDSEL_BOUNDARYU_Pos         16                                                      /*!< DSD_CH BOUNDSEL: BOUNDARYU Position     */\r
+#define DSD_CH_BOUNDSEL_BOUNDARYU_Msk         (0x0000ffffUL << DSD_CH_BOUNDSEL_BOUNDARYU_Pos)         /*!< DSD_CH BOUNDSEL: BOUNDARYU Mask         */\r
+\r
+/* ---------------------------------  DSD_CH_RESM  -------------------------------- */\r
+#define DSD_CH_RESM_RESULT_Pos                0                                                       /*!< DSD_CH RESM: RESULT Position            */\r
+#define DSD_CH_RESM_RESULT_Msk                (0x0000ffffUL << DSD_CH_RESM_RESULT_Pos)                /*!< DSD_CH RESM: RESULT Mask                */\r
+\r
+/* ---------------------------------  DSD_CH_OFFM  -------------------------------- */\r
+#define DSD_CH_OFFM_OFFSET_Pos                0                                                       /*!< DSD_CH OFFM: OFFSET Position            */\r
+#define DSD_CH_OFFM_OFFSET_Msk                (0x0000ffffUL << DSD_CH_OFFM_OFFSET_Pos)                /*!< DSD_CH OFFM: OFFSET Mask                */\r
+\r
+/* ---------------------------------  DSD_CH_RESA  -------------------------------- */\r
+#define DSD_CH_RESA_RESULT_Pos                0                                                       /*!< DSD_CH RESA: RESULT Position            */\r
+#define DSD_CH_RESA_RESULT_Msk                (0x0000ffffUL << DSD_CH_RESA_RESULT_Pos)                /*!< DSD_CH RESA: RESULT Mask                */\r
+\r
+/* --------------------------------  DSD_CH_TSTMP  -------------------------------- */\r
+#define DSD_CH_TSTMP_RESULT_Pos               0                                                       /*!< DSD_CH TSTMP: RESULT Position           */\r
+#define DSD_CH_TSTMP_RESULT_Msk               (0x0000ffffUL << DSD_CH_TSTMP_RESULT_Pos)               /*!< DSD_CH TSTMP: RESULT Mask               */\r
+#define DSD_CH_TSTMP_CFMDCNT_Pos              16                                                      /*!< DSD_CH TSTMP: CFMDCNT Position          */\r
+#define DSD_CH_TSTMP_CFMDCNT_Msk              (0x000000ffUL << DSD_CH_TSTMP_CFMDCNT_Pos)              /*!< DSD_CH TSTMP: CFMDCNT Mask              */\r
+#define DSD_CH_TSTMP_NVALCNT_Pos              24                                                      /*!< DSD_CH TSTMP: NVALCNT Position          */\r
+#define DSD_CH_TSTMP_NVALCNT_Msk              (0x3fUL << DSD_CH_TSTMP_NVALCNT_Pos)                    /*!< DSD_CH TSTMP: NVALCNT Mask              */\r
+\r
+/* --------------------------------  DSD_CH_CGSYNC  ------------------------------- */\r
+#define DSD_CH_CGSYNC_SDCOUNT_Pos             0                                                       /*!< DSD_CH CGSYNC: SDCOUNT Position         */\r
+#define DSD_CH_CGSYNC_SDCOUNT_Msk             (0x000000ffUL << DSD_CH_CGSYNC_SDCOUNT_Pos)             /*!< DSD_CH CGSYNC: SDCOUNT Mask             */\r
+#define DSD_CH_CGSYNC_SDCAP_Pos               8                                                       /*!< DSD_CH CGSYNC: SDCAP Position           */\r
+#define DSD_CH_CGSYNC_SDCAP_Msk               (0x000000ffUL << DSD_CH_CGSYNC_SDCAP_Pos)               /*!< DSD_CH CGSYNC: SDCAP Mask               */\r
+#define DSD_CH_CGSYNC_SDPOS_Pos               16                                                      /*!< DSD_CH CGSYNC: SDPOS Position           */\r
+#define DSD_CH_CGSYNC_SDPOS_Msk               (0x000000ffUL << DSD_CH_CGSYNC_SDPOS_Pos)               /*!< DSD_CH CGSYNC: SDPOS Mask               */\r
+#define DSD_CH_CGSYNC_SDNEG_Pos               24                                                      /*!< DSD_CH CGSYNC: SDNEG Position           */\r
+#define DSD_CH_CGSYNC_SDNEG_Msk               (0x000000ffUL << DSD_CH_CGSYNC_SDNEG_Pos)               /*!< DSD_CH CGSYNC: SDNEG Mask               */\r
+\r
+/* -------------------------------  DSD_CH_RECTCFG  ------------------------------- */\r
+#define DSD_CH_RECTCFG_RFEN_Pos               0                                                       /*!< DSD_CH RECTCFG: RFEN Position           */\r
+#define DSD_CH_RECTCFG_RFEN_Msk               (0x01UL << DSD_CH_RECTCFG_RFEN_Pos)                     /*!< DSD_CH RECTCFG: RFEN Mask               */\r
+#define DSD_CH_RECTCFG_SSRC_Pos               4                                                       /*!< DSD_CH RECTCFG: SSRC Position           */\r
+#define DSD_CH_RECTCFG_SSRC_Msk               (0x03UL << DSD_CH_RECTCFG_SSRC_Pos)                     /*!< DSD_CH RECTCFG: SSRC Mask               */\r
+#define DSD_CH_RECTCFG_SDVAL_Pos              15                                                      /*!< DSD_CH RECTCFG: SDVAL Position          */\r
+#define DSD_CH_RECTCFG_SDVAL_Msk              (0x01UL << DSD_CH_RECTCFG_SDVAL_Pos)                    /*!< DSD_CH RECTCFG: SDVAL Mask              */\r
+#define DSD_CH_RECTCFG_SGNCS_Pos              30                                                      /*!< DSD_CH RECTCFG: SGNCS Position          */\r
+#define DSD_CH_RECTCFG_SGNCS_Msk              (0x01UL << DSD_CH_RECTCFG_SGNCS_Pos)                    /*!< DSD_CH RECTCFG: SGNCS Mask              */\r
+#define DSD_CH_RECTCFG_SGND_Pos               31                                                      /*!< DSD_CH RECTCFG: SGND Position           */\r
+#define DSD_CH_RECTCFG_SGND_Msk               (0x01UL << DSD_CH_RECTCFG_SGND_Pos)                     /*!< DSD_CH RECTCFG: SGND Mask               */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          struct 'DAC' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -----------------------------------  DAC_ID  ----------------------------------- */\r
+#define DAC_ID_MODR_Pos                       0                                                       /*!< DAC ID: MODR Position                   */\r
+#define DAC_ID_MODR_Msk                       (0x000000ffUL << DAC_ID_MODR_Pos)                       /*!< DAC ID: MODR Mask                       */\r
+#define DAC_ID_MODT_Pos                       8                                                       /*!< DAC ID: MODT Position                   */\r
+#define DAC_ID_MODT_Msk                       (0x000000ffUL << DAC_ID_MODT_Pos)                       /*!< DAC ID: MODT Mask                       */\r
+#define DAC_ID_MODN_Pos                       16                                                      /*!< DAC ID: MODN Position                   */\r
+#define DAC_ID_MODN_Msk                       (0x0000ffffUL << DAC_ID_MODN_Pos)                       /*!< DAC ID: MODN Mask                       */\r
+\r
+/* --------------------------------  DAC_DAC0CFG0  -------------------------------- */\r
+#define DAC_DAC0CFG0_FREQ_Pos                 0                                                       /*!< DAC DAC0CFG0: FREQ Position             */\r
+#define DAC_DAC0CFG0_FREQ_Msk                 (0x000fffffUL << DAC_DAC0CFG0_FREQ_Pos)                 /*!< DAC DAC0CFG0: FREQ Mask                 */\r
+#define DAC_DAC0CFG0_MODE_Pos                 20                                                      /*!< DAC DAC0CFG0: MODE Position             */\r
+#define DAC_DAC0CFG0_MODE_Msk                 (0x07UL << DAC_DAC0CFG0_MODE_Pos)                       /*!< DAC DAC0CFG0: MODE Mask                 */\r
+#define DAC_DAC0CFG0_SIGN_Pos                 23                                                      /*!< DAC DAC0CFG0: SIGN Position             */\r
+#define DAC_DAC0CFG0_SIGN_Msk                 (0x01UL << DAC_DAC0CFG0_SIGN_Pos)                       /*!< DAC DAC0CFG0: SIGN Mask                 */\r
+#define DAC_DAC0CFG0_FIFOIND_Pos              24                                                      /*!< DAC DAC0CFG0: FIFOIND Position          */\r
+#define DAC_DAC0CFG0_FIFOIND_Msk              (0x03UL << DAC_DAC0CFG0_FIFOIND_Pos)                    /*!< DAC DAC0CFG0: FIFOIND Mask              */\r
+#define DAC_DAC0CFG0_FIFOEMP_Pos              26                                                      /*!< DAC DAC0CFG0: FIFOEMP Position          */\r
+#define DAC_DAC0CFG0_FIFOEMP_Msk              (0x01UL << DAC_DAC0CFG0_FIFOEMP_Pos)                    /*!< DAC DAC0CFG0: FIFOEMP Mask              */\r
+#define DAC_DAC0CFG0_FIFOFUL_Pos              27                                                      /*!< DAC DAC0CFG0: FIFOFUL Position          */\r
+#define DAC_DAC0CFG0_FIFOFUL_Msk              (0x01UL << DAC_DAC0CFG0_FIFOFUL_Pos)                    /*!< DAC DAC0CFG0: FIFOFUL Mask              */\r
+#define DAC_DAC0CFG0_SIGNEN_Pos               29                                                      /*!< DAC DAC0CFG0: SIGNEN Position           */\r
+#define DAC_DAC0CFG0_SIGNEN_Msk               (0x01UL << DAC_DAC0CFG0_SIGNEN_Pos)                     /*!< DAC DAC0CFG0: SIGNEN Mask               */\r
+#define DAC_DAC0CFG0_SREN_Pos                 30                                                      /*!< DAC DAC0CFG0: SREN Position             */\r
+#define DAC_DAC0CFG0_SREN_Msk                 (0x01UL << DAC_DAC0CFG0_SREN_Pos)                       /*!< DAC DAC0CFG0: SREN Mask                 */\r
+#define DAC_DAC0CFG0_RUN_Pos                  31                                                      /*!< DAC DAC0CFG0: RUN Position              */\r
+#define DAC_DAC0CFG0_RUN_Msk                  (0x01UL << DAC_DAC0CFG0_RUN_Pos)                        /*!< DAC DAC0CFG0: RUN Mask                  */\r
+\r
+/* --------------------------------  DAC_DAC0CFG1  -------------------------------- */\r
+#define DAC_DAC0CFG1_SCALE_Pos                0                                                       /*!< DAC DAC0CFG1: SCALE Position            */\r
+#define DAC_DAC0CFG1_SCALE_Msk                (0x07UL << DAC_DAC0CFG1_SCALE_Pos)                      /*!< DAC DAC0CFG1: SCALE Mask                */\r
+#define DAC_DAC0CFG1_MULDIV_Pos               3                                                       /*!< DAC DAC0CFG1: MULDIV Position           */\r
+#define DAC_DAC0CFG1_MULDIV_Msk               (0x01UL << DAC_DAC0CFG1_MULDIV_Pos)                     /*!< DAC DAC0CFG1: MULDIV Mask               */\r
+#define DAC_DAC0CFG1_OFFS_Pos                 4                                                       /*!< DAC DAC0CFG1: OFFS Position             */\r
+#define DAC_DAC0CFG1_OFFS_Msk                 (0x000000ffUL << DAC_DAC0CFG1_OFFS_Pos)                 /*!< DAC DAC0CFG1: OFFS Mask                 */\r
+#define DAC_DAC0CFG1_TRIGSEL_Pos              12                                                      /*!< DAC DAC0CFG1: TRIGSEL Position          */\r
+#define DAC_DAC0CFG1_TRIGSEL_Msk              (0x07UL << DAC_DAC0CFG1_TRIGSEL_Pos)                    /*!< DAC DAC0CFG1: TRIGSEL Mask              */\r
+#define DAC_DAC0CFG1_DATMOD_Pos               15                                                      /*!< DAC DAC0CFG1: DATMOD Position           */\r
+#define DAC_DAC0CFG1_DATMOD_Msk               (0x01UL << DAC_DAC0CFG1_DATMOD_Pos)                     /*!< DAC DAC0CFG1: DATMOD Mask               */\r
+#define DAC_DAC0CFG1_SWTRIG_Pos               16                                                      /*!< DAC DAC0CFG1: SWTRIG Position           */\r
+#define DAC_DAC0CFG1_SWTRIG_Msk               (0x01UL << DAC_DAC0CFG1_SWTRIG_Pos)                     /*!< DAC DAC0CFG1: SWTRIG Mask               */\r
+#define DAC_DAC0CFG1_TRIGMOD_Pos              17                                                      /*!< DAC DAC0CFG1: TRIGMOD Position          */\r
+#define DAC_DAC0CFG1_TRIGMOD_Msk              (0x03UL << DAC_DAC0CFG1_TRIGMOD_Pos)                    /*!< DAC DAC0CFG1: TRIGMOD Mask              */\r
+#define DAC_DAC0CFG1_ANACFG_Pos               19                                                      /*!< DAC DAC0CFG1: ANACFG Position           */\r
+#define DAC_DAC0CFG1_ANACFG_Msk               (0x1fUL << DAC_DAC0CFG1_ANACFG_Pos)                     /*!< DAC DAC0CFG1: ANACFG Mask               */\r
+#define DAC_DAC0CFG1_ANAEN_Pos                24                                                      /*!< DAC DAC0CFG1: ANAEN Position            */\r
+#define DAC_DAC0CFG1_ANAEN_Msk                (0x01UL << DAC_DAC0CFG1_ANAEN_Pos)                      /*!< DAC DAC0CFG1: ANAEN Mask                */\r
+#define DAC_DAC0CFG1_REFCFGL_Pos              28                                                      /*!< DAC DAC0CFG1: REFCFGL Position          */\r
+#define DAC_DAC0CFG1_REFCFGL_Msk              (0x0fUL << DAC_DAC0CFG1_REFCFGL_Pos)                    /*!< DAC DAC0CFG1: REFCFGL Mask              */\r
+\r
+/* --------------------------------  DAC_DAC1CFG0  -------------------------------- */\r
+#define DAC_DAC1CFG0_FREQ_Pos                 0                                                       /*!< DAC DAC1CFG0: FREQ Position             */\r
+#define DAC_DAC1CFG0_FREQ_Msk                 (0x000fffffUL << DAC_DAC1CFG0_FREQ_Pos)                 /*!< DAC DAC1CFG0: FREQ Mask                 */\r
+#define DAC_DAC1CFG0_MODE_Pos                 20                                                      /*!< DAC DAC1CFG0: MODE Position             */\r
+#define DAC_DAC1CFG0_MODE_Msk                 (0x07UL << DAC_DAC1CFG0_MODE_Pos)                       /*!< DAC DAC1CFG0: MODE Mask                 */\r
+#define DAC_DAC1CFG0_SIGN_Pos                 23                                                      /*!< DAC DAC1CFG0: SIGN Position             */\r
+#define DAC_DAC1CFG0_SIGN_Msk                 (0x01UL << DAC_DAC1CFG0_SIGN_Pos)                       /*!< DAC DAC1CFG0: SIGN Mask                 */\r
+#define DAC_DAC1CFG0_FIFOIND_Pos              24                                                      /*!< DAC DAC1CFG0: FIFOIND Position          */\r
+#define DAC_DAC1CFG0_FIFOIND_Msk              (0x03UL << DAC_DAC1CFG0_FIFOIND_Pos)                    /*!< DAC DAC1CFG0: FIFOIND Mask              */\r
+#define DAC_DAC1CFG0_FIFOEMP_Pos              26                                                      /*!< DAC DAC1CFG0: FIFOEMP Position          */\r
+#define DAC_DAC1CFG0_FIFOEMP_Msk              (0x01UL << DAC_DAC1CFG0_FIFOEMP_Pos)                    /*!< DAC DAC1CFG0: FIFOEMP Mask              */\r
+#define DAC_DAC1CFG0_FIFOFUL_Pos              27                                                      /*!< DAC DAC1CFG0: FIFOFUL Position          */\r
+#define DAC_DAC1CFG0_FIFOFUL_Msk              (0x01UL << DAC_DAC1CFG0_FIFOFUL_Pos)                    /*!< DAC DAC1CFG0: FIFOFUL Mask              */\r
+#define DAC_DAC1CFG0_SIGNEN_Pos               29                                                      /*!< DAC DAC1CFG0: SIGNEN Position           */\r
+#define DAC_DAC1CFG0_SIGNEN_Msk               (0x01UL << DAC_DAC1CFG0_SIGNEN_Pos)                     /*!< DAC DAC1CFG0: SIGNEN Mask               */\r
+#define DAC_DAC1CFG0_SREN_Pos                 30                                                      /*!< DAC DAC1CFG0: SREN Position             */\r
+#define DAC_DAC1CFG0_SREN_Msk                 (0x01UL << DAC_DAC1CFG0_SREN_Pos)                       /*!< DAC DAC1CFG0: SREN Mask                 */\r
+#define DAC_DAC1CFG0_RUN_Pos                  31                                                      /*!< DAC DAC1CFG0: RUN Position              */\r
+#define DAC_DAC1CFG0_RUN_Msk                  (0x01UL << DAC_DAC1CFG0_RUN_Pos)                        /*!< DAC DAC1CFG0: RUN Mask                  */\r
+\r
+/* --------------------------------  DAC_DAC1CFG1  -------------------------------- */\r
+#define DAC_DAC1CFG1_SCALE_Pos                0                                                       /*!< DAC DAC1CFG1: SCALE Position            */\r
+#define DAC_DAC1CFG1_SCALE_Msk                (0x07UL << DAC_DAC1CFG1_SCALE_Pos)                      /*!< DAC DAC1CFG1: SCALE Mask                */\r
+#define DAC_DAC1CFG1_MULDIV_Pos               3                                                       /*!< DAC DAC1CFG1: MULDIV Position           */\r
+#define DAC_DAC1CFG1_MULDIV_Msk               (0x01UL << DAC_DAC1CFG1_MULDIV_Pos)                     /*!< DAC DAC1CFG1: MULDIV Mask               */\r
+#define DAC_DAC1CFG1_OFFS_Pos                 4                                                       /*!< DAC DAC1CFG1: OFFS Position             */\r
+#define DAC_DAC1CFG1_OFFS_Msk                 (0x000000ffUL << DAC_DAC1CFG1_OFFS_Pos)                 /*!< DAC DAC1CFG1: OFFS Mask                 */\r
+#define DAC_DAC1CFG1_TRIGSEL_Pos              12                                                      /*!< DAC DAC1CFG1: TRIGSEL Position          */\r
+#define DAC_DAC1CFG1_TRIGSEL_Msk              (0x07UL << DAC_DAC1CFG1_TRIGSEL_Pos)                    /*!< DAC DAC1CFG1: TRIGSEL Mask              */\r
+#define DAC_DAC1CFG1_SWTRIG_Pos               16                                                      /*!< DAC DAC1CFG1: SWTRIG Position           */\r
+#define DAC_DAC1CFG1_SWTRIG_Msk               (0x01UL << DAC_DAC1CFG1_SWTRIG_Pos)                     /*!< DAC DAC1CFG1: SWTRIG Mask               */\r
+#define DAC_DAC1CFG1_TRIGMOD_Pos              17                                                      /*!< DAC DAC1CFG1: TRIGMOD Position          */\r
+#define DAC_DAC1CFG1_TRIGMOD_Msk              (0x03UL << DAC_DAC1CFG1_TRIGMOD_Pos)                    /*!< DAC DAC1CFG1: TRIGMOD Mask              */\r
+#define DAC_DAC1CFG1_ANACFG_Pos               19                                                      /*!< DAC DAC1CFG1: ANACFG Position           */\r
+#define DAC_DAC1CFG1_ANACFG_Msk               (0x1fUL << DAC_DAC1CFG1_ANACFG_Pos)                     /*!< DAC DAC1CFG1: ANACFG Mask               */\r
+#define DAC_DAC1CFG1_ANAEN_Pos                24                                                      /*!< DAC DAC1CFG1: ANAEN Position            */\r
+#define DAC_DAC1CFG1_ANAEN_Msk                (0x01UL << DAC_DAC1CFG1_ANAEN_Pos)                      /*!< DAC DAC1CFG1: ANAEN Mask                */\r
+#define DAC_DAC1CFG1_REFCFGH_Pos              28                                                      /*!< DAC DAC1CFG1: REFCFGH Position          */\r
+#define DAC_DAC1CFG1_REFCFGH_Msk              (0x0fUL << DAC_DAC1CFG1_REFCFGH_Pos)                    /*!< DAC DAC1CFG1: REFCFGH Mask              */\r
+\r
+/* --------------------------------  DAC_DAC0DATA  -------------------------------- */\r
+#define DAC_DAC0DATA_DATA0_Pos                0                                                       /*!< DAC DAC0DATA: DATA0 Position            */\r
+#define DAC_DAC0DATA_DATA0_Msk                (0x00000fffUL << DAC_DAC0DATA_DATA0_Pos)                /*!< DAC DAC0DATA: DATA0 Mask                */\r
+\r
+/* --------------------------------  DAC_DAC1DATA  -------------------------------- */\r
+#define DAC_DAC1DATA_DATA1_Pos                0                                                       /*!< DAC DAC1DATA: DATA1 Position            */\r
+#define DAC_DAC1DATA_DATA1_Msk                (0x00000fffUL << DAC_DAC1DATA_DATA1_Pos)                /*!< DAC DAC1DATA: DATA1 Mask                */\r
+\r
+/* --------------------------------  DAC_DAC01DATA  ------------------------------- */\r
+#define DAC_DAC01DATA_DATA0_Pos               0                                                       /*!< DAC DAC01DATA: DATA0 Position           */\r
+#define DAC_DAC01DATA_DATA0_Msk               (0x00000fffUL << DAC_DAC01DATA_DATA0_Pos)               /*!< DAC DAC01DATA: DATA0 Mask               */\r
+#define DAC_DAC01DATA_DATA1_Pos               16                                                      /*!< DAC DAC01DATA: DATA1 Position           */\r
+#define DAC_DAC01DATA_DATA1_Msk               (0x00000fffUL << DAC_DAC01DATA_DATA1_Pos)               /*!< DAC DAC01DATA: DATA1 Mask               */\r
+\r
+/* --------------------------------  DAC_DAC0PATL  -------------------------------- */\r
+#define DAC_DAC0PATL_PAT0_Pos                 0                                                       /*!< DAC DAC0PATL: PAT0 Position             */\r
+#define DAC_DAC0PATL_PAT0_Msk                 (0x1fUL << DAC_DAC0PATL_PAT0_Pos)                       /*!< DAC DAC0PATL: PAT0 Mask                 */\r
+#define DAC_DAC0PATL_PAT1_Pos                 5                                                       /*!< DAC DAC0PATL: PAT1 Position             */\r
+#define DAC_DAC0PATL_PAT1_Msk                 (0x1fUL << DAC_DAC0PATL_PAT1_Pos)                       /*!< DAC DAC0PATL: PAT1 Mask                 */\r
+#define DAC_DAC0PATL_PAT2_Pos                 10                                                      /*!< DAC DAC0PATL: PAT2 Position             */\r
+#define DAC_DAC0PATL_PAT2_Msk                 (0x1fUL << DAC_DAC0PATL_PAT2_Pos)                       /*!< DAC DAC0PATL: PAT2 Mask                 */\r
+#define DAC_DAC0PATL_PAT3_Pos                 15                                                      /*!< DAC DAC0PATL: PAT3 Position             */\r
+#define DAC_DAC0PATL_PAT3_Msk                 (0x1fUL << DAC_DAC0PATL_PAT3_Pos)                       /*!< DAC DAC0PATL: PAT3 Mask                 */\r
+#define DAC_DAC0PATL_PAT4_Pos                 20                                                      /*!< DAC DAC0PATL: PAT4 Position             */\r
+#define DAC_DAC0PATL_PAT4_Msk                 (0x1fUL << DAC_DAC0PATL_PAT4_Pos)                       /*!< DAC DAC0PATL: PAT4 Mask                 */\r
+#define DAC_DAC0PATL_PAT5_Pos                 25                                                      /*!< DAC DAC0PATL: PAT5 Position             */\r
+#define DAC_DAC0PATL_PAT5_Msk                 (0x1fUL << DAC_DAC0PATL_PAT5_Pos)                       /*!< DAC DAC0PATL: PAT5 Mask                 */\r
+\r
+/* --------------------------------  DAC_DAC0PATH  -------------------------------- */\r
+#define DAC_DAC0PATH_PAT6_Pos                 0                                                       /*!< DAC DAC0PATH: PAT6 Position             */\r
+#define DAC_DAC0PATH_PAT6_Msk                 (0x1fUL << DAC_DAC0PATH_PAT6_Pos)                       /*!< DAC DAC0PATH: PAT6 Mask                 */\r
+#define DAC_DAC0PATH_PAT7_Pos                 5                                                       /*!< DAC DAC0PATH: PAT7 Position             */\r
+#define DAC_DAC0PATH_PAT7_Msk                 (0x1fUL << DAC_DAC0PATH_PAT7_Pos)                       /*!< DAC DAC0PATH: PAT7 Mask                 */\r
+#define DAC_DAC0PATH_PAT8_Pos                 10                                                      /*!< DAC DAC0PATH: PAT8 Position             */\r
+#define DAC_DAC0PATH_PAT8_Msk                 (0x1fUL << DAC_DAC0PATH_PAT8_Pos)                       /*!< DAC DAC0PATH: PAT8 Mask                 */\r
+\r
+/* --------------------------------  DAC_DAC1PATL  -------------------------------- */\r
+#define DAC_DAC1PATL_PAT0_Pos                 0                                                       /*!< DAC DAC1PATL: PAT0 Position             */\r
+#define DAC_DAC1PATL_PAT0_Msk                 (0x1fUL << DAC_DAC1PATL_PAT0_Pos)                       /*!< DAC DAC1PATL: PAT0 Mask                 */\r
+#define DAC_DAC1PATL_PAT1_Pos                 5                                                       /*!< DAC DAC1PATL: PAT1 Position             */\r
+#define DAC_DAC1PATL_PAT1_Msk                 (0x1fUL << DAC_DAC1PATL_PAT1_Pos)                       /*!< DAC DAC1PATL: PAT1 Mask                 */\r
+#define DAC_DAC1PATL_PAT2_Pos                 10                                                      /*!< DAC DAC1PATL: PAT2 Position             */\r
+#define DAC_DAC1PATL_PAT2_Msk                 (0x1fUL << DAC_DAC1PATL_PAT2_Pos)                       /*!< DAC DAC1PATL: PAT2 Mask                 */\r
+#define DAC_DAC1PATL_PAT3_Pos                 15                                                      /*!< DAC DAC1PATL: PAT3 Position             */\r
+#define DAC_DAC1PATL_PAT3_Msk                 (0x1fUL << DAC_DAC1PATL_PAT3_Pos)                       /*!< DAC DAC1PATL: PAT3 Mask                 */\r
+#define DAC_DAC1PATL_PAT4_Pos                 20                                                      /*!< DAC DAC1PATL: PAT4 Position             */\r
+#define DAC_DAC1PATL_PAT4_Msk                 (0x1fUL << DAC_DAC1PATL_PAT4_Pos)                       /*!< DAC DAC1PATL: PAT4 Mask                 */\r
+#define DAC_DAC1PATL_PAT5_Pos                 25                                                      /*!< DAC DAC1PATL: PAT5 Position             */\r
+#define DAC_DAC1PATL_PAT5_Msk                 (0x1fUL << DAC_DAC1PATL_PAT5_Pos)                       /*!< DAC DAC1PATL: PAT5 Mask                 */\r
+\r
+/* --------------------------------  DAC_DAC1PATH  -------------------------------- */\r
+#define DAC_DAC1PATH_PAT6_Pos                 0                                                       /*!< DAC DAC1PATH: PAT6 Position             */\r
+#define DAC_DAC1PATH_PAT6_Msk                 (0x1fUL << DAC_DAC1PATH_PAT6_Pos)                       /*!< DAC DAC1PATH: PAT6 Mask                 */\r
+#define DAC_DAC1PATH_PAT7_Pos                 5                                                       /*!< DAC DAC1PATH: PAT7 Position             */\r
+#define DAC_DAC1PATH_PAT7_Msk                 (0x1fUL << DAC_DAC1PATH_PAT7_Pos)                       /*!< DAC DAC1PATH: PAT7 Mask                 */\r
+#define DAC_DAC1PATH_PAT8_Pos                 10                                                      /*!< DAC DAC1PATH: PAT8 Position             */\r
+#define DAC_DAC1PATH_PAT8_Msk                 (0x1fUL << DAC_DAC1PATH_PAT8_Pos)                       /*!< DAC DAC1PATH: PAT8 Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'CCU4' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  CCU4_GCTRL  --------------------------------- */\r
+#define CCU4_GCTRL_PRBC_Pos                   0                                                       /*!< CCU4 GCTRL: PRBC Position               */\r
+#define CCU4_GCTRL_PRBC_Msk                   (0x07UL << CCU4_GCTRL_PRBC_Pos)                         /*!< CCU4 GCTRL: PRBC Mask                   */\r
+#define CCU4_GCTRL_PCIS_Pos                   4                                                       /*!< CCU4 GCTRL: PCIS Position               */\r
+#define CCU4_GCTRL_PCIS_Msk                   (0x03UL << CCU4_GCTRL_PCIS_Pos)                         /*!< CCU4 GCTRL: PCIS Mask                   */\r
+#define CCU4_GCTRL_SUSCFG_Pos                 8                                                       /*!< CCU4 GCTRL: SUSCFG Position             */\r
+#define CCU4_GCTRL_SUSCFG_Msk                 (0x03UL << CCU4_GCTRL_SUSCFG_Pos)                       /*!< CCU4 GCTRL: SUSCFG Mask                 */\r
+#define CCU4_GCTRL_MSE0_Pos                   10                                                      /*!< CCU4 GCTRL: MSE0 Position               */\r
+#define CCU4_GCTRL_MSE0_Msk                   (0x01UL << CCU4_GCTRL_MSE0_Pos)                         /*!< CCU4 GCTRL: MSE0 Mask                   */\r
+#define CCU4_GCTRL_MSE1_Pos                   11                                                      /*!< CCU4 GCTRL: MSE1 Position               */\r
+#define CCU4_GCTRL_MSE1_Msk                   (0x01UL << CCU4_GCTRL_MSE1_Pos)                         /*!< CCU4 GCTRL: MSE1 Mask                   */\r
+#define CCU4_GCTRL_MSE2_Pos                   12                                                      /*!< CCU4 GCTRL: MSE2 Position               */\r
+#define CCU4_GCTRL_MSE2_Msk                   (0x01UL << CCU4_GCTRL_MSE2_Pos)                         /*!< CCU4 GCTRL: MSE2 Mask                   */\r
+#define CCU4_GCTRL_MSE3_Pos                   13                                                      /*!< CCU4 GCTRL: MSE3 Position               */\r
+#define CCU4_GCTRL_MSE3_Msk                   (0x01UL << CCU4_GCTRL_MSE3_Pos)                         /*!< CCU4 GCTRL: MSE3 Mask                   */\r
+#define CCU4_GCTRL_MSDE_Pos                   14                                                      /*!< CCU4 GCTRL: MSDE Position               */\r
+#define CCU4_GCTRL_MSDE_Msk                   (0x03UL << CCU4_GCTRL_MSDE_Pos)                         /*!< CCU4 GCTRL: MSDE Mask                   */\r
+\r
+/* ---------------------------------  CCU4_GSTAT  --------------------------------- */\r
+#define CCU4_GSTAT_S0I_Pos                    0                                                       /*!< CCU4 GSTAT: S0I Position                */\r
+#define CCU4_GSTAT_S0I_Msk                    (0x01UL << CCU4_GSTAT_S0I_Pos)                          /*!< CCU4 GSTAT: S0I Mask                    */\r
+#define CCU4_GSTAT_S1I_Pos                    1                                                       /*!< CCU4 GSTAT: S1I Position                */\r
+#define CCU4_GSTAT_S1I_Msk                    (0x01UL << CCU4_GSTAT_S1I_Pos)                          /*!< CCU4 GSTAT: S1I Mask                    */\r
+#define CCU4_GSTAT_S2I_Pos                    2                                                       /*!< CCU4 GSTAT: S2I Position                */\r
+#define CCU4_GSTAT_S2I_Msk                    (0x01UL << CCU4_GSTAT_S2I_Pos)                          /*!< CCU4 GSTAT: S2I Mask                    */\r
+#define CCU4_GSTAT_S3I_Pos                    3                                                       /*!< CCU4 GSTAT: S3I Position                */\r
+#define CCU4_GSTAT_S3I_Msk                    (0x01UL << CCU4_GSTAT_S3I_Pos)                          /*!< CCU4 GSTAT: S3I Mask                    */\r
+#define CCU4_GSTAT_PRB_Pos                    8                                                       /*!< CCU4 GSTAT: PRB Position                */\r
+#define CCU4_GSTAT_PRB_Msk                    (0x01UL << CCU4_GSTAT_PRB_Pos)                          /*!< CCU4 GSTAT: PRB Mask                    */\r
+\r
+/* ---------------------------------  CCU4_GIDLS  --------------------------------- */\r
+#define CCU4_GIDLS_SS0I_Pos                   0                                                       /*!< CCU4 GIDLS: SS0I Position               */\r
+#define CCU4_GIDLS_SS0I_Msk                   (0x01UL << CCU4_GIDLS_SS0I_Pos)                         /*!< CCU4 GIDLS: SS0I Mask                   */\r
+#define CCU4_GIDLS_SS1I_Pos                   1                                                       /*!< CCU4 GIDLS: SS1I Position               */\r
+#define CCU4_GIDLS_SS1I_Msk                   (0x01UL << CCU4_GIDLS_SS1I_Pos)                         /*!< CCU4 GIDLS: SS1I Mask                   */\r
+#define CCU4_GIDLS_SS2I_Pos                   2                                                       /*!< CCU4 GIDLS: SS2I Position               */\r
+#define CCU4_GIDLS_SS2I_Msk                   (0x01UL << CCU4_GIDLS_SS2I_Pos)                         /*!< CCU4 GIDLS: SS2I Mask                   */\r
+#define CCU4_GIDLS_SS3I_Pos                   3                                                       /*!< CCU4 GIDLS: SS3I Position               */\r
+#define CCU4_GIDLS_SS3I_Msk                   (0x01UL << CCU4_GIDLS_SS3I_Pos)                         /*!< CCU4 GIDLS: SS3I Mask                   */\r
+#define CCU4_GIDLS_CPRB_Pos                   8                                                       /*!< CCU4 GIDLS: CPRB Position               */\r
+#define CCU4_GIDLS_CPRB_Msk                   (0x01UL << CCU4_GIDLS_CPRB_Pos)                         /*!< CCU4 GIDLS: CPRB Mask                   */\r
+#define CCU4_GIDLS_PSIC_Pos                   9                                                       /*!< CCU4 GIDLS: PSIC Position               */\r
+#define CCU4_GIDLS_PSIC_Msk                   (0x01UL << CCU4_GIDLS_PSIC_Pos)                         /*!< CCU4 GIDLS: PSIC Mask                   */\r
+\r
+/* ---------------------------------  CCU4_GIDLC  --------------------------------- */\r
+#define CCU4_GIDLC_CS0I_Pos                   0                                                       /*!< CCU4 GIDLC: CS0I Position               */\r
+#define CCU4_GIDLC_CS0I_Msk                   (0x01UL << CCU4_GIDLC_CS0I_Pos)                         /*!< CCU4 GIDLC: CS0I Mask                   */\r
+#define CCU4_GIDLC_CS1I_Pos                   1                                                       /*!< CCU4 GIDLC: CS1I Position               */\r
+#define CCU4_GIDLC_CS1I_Msk                   (0x01UL << CCU4_GIDLC_CS1I_Pos)                         /*!< CCU4 GIDLC: CS1I Mask                   */\r
+#define CCU4_GIDLC_CS2I_Pos                   2                                                       /*!< CCU4 GIDLC: CS2I Position               */\r
+#define CCU4_GIDLC_CS2I_Msk                   (0x01UL << CCU4_GIDLC_CS2I_Pos)                         /*!< CCU4 GIDLC: CS2I Mask                   */\r
+#define CCU4_GIDLC_CS3I_Pos                   3                                                       /*!< CCU4 GIDLC: CS3I Position               */\r
+#define CCU4_GIDLC_CS3I_Msk                   (0x01UL << CCU4_GIDLC_CS3I_Pos)                         /*!< CCU4 GIDLC: CS3I Mask                   */\r
+#define CCU4_GIDLC_SPRB_Pos                   8                                                       /*!< CCU4 GIDLC: SPRB Position               */\r
+#define CCU4_GIDLC_SPRB_Msk                   (0x01UL << CCU4_GIDLC_SPRB_Pos)                         /*!< CCU4 GIDLC: SPRB Mask                   */\r
+\r
+/* ----------------------------------  CCU4_GCSS  --------------------------------- */\r
+#define CCU4_GCSS_S0SE_Pos                    0                                                       /*!< CCU4 GCSS: S0SE Position                */\r
+#define CCU4_GCSS_S0SE_Msk                    (0x01UL << CCU4_GCSS_S0SE_Pos)                          /*!< CCU4 GCSS: S0SE Mask                    */\r
+#define CCU4_GCSS_S0DSE_Pos                   1                                                       /*!< CCU4 GCSS: S0DSE Position               */\r
+#define CCU4_GCSS_S0DSE_Msk                   (0x01UL << CCU4_GCSS_S0DSE_Pos)                         /*!< CCU4 GCSS: S0DSE Mask                   */\r
+#define CCU4_GCSS_S0PSE_Pos                   2                                                       /*!< CCU4 GCSS: S0PSE Position               */\r
+#define CCU4_GCSS_S0PSE_Msk                   (0x01UL << CCU4_GCSS_S0PSE_Pos)                         /*!< CCU4 GCSS: S0PSE Mask                   */\r
+#define CCU4_GCSS_S1SE_Pos                    4                                                       /*!< CCU4 GCSS: S1SE Position                */\r
+#define CCU4_GCSS_S1SE_Msk                    (0x01UL << CCU4_GCSS_S1SE_Pos)                          /*!< CCU4 GCSS: S1SE Mask                    */\r
+#define CCU4_GCSS_S1DSE_Pos                   5                                                       /*!< CCU4 GCSS: S1DSE Position               */\r
+#define CCU4_GCSS_S1DSE_Msk                   (0x01UL << CCU4_GCSS_S1DSE_Pos)                         /*!< CCU4 GCSS: S1DSE Mask                   */\r
+#define CCU4_GCSS_S1PSE_Pos                   6                                                       /*!< CCU4 GCSS: S1PSE Position               */\r
+#define CCU4_GCSS_S1PSE_Msk                   (0x01UL << CCU4_GCSS_S1PSE_Pos)                         /*!< CCU4 GCSS: S1PSE Mask                   */\r
+#define CCU4_GCSS_S2SE_Pos                    8                                                       /*!< CCU4 GCSS: S2SE Position                */\r
+#define CCU4_GCSS_S2SE_Msk                    (0x01UL << CCU4_GCSS_S2SE_Pos)                          /*!< CCU4 GCSS: S2SE Mask                    */\r
+#define CCU4_GCSS_S2DSE_Pos                   9                                                       /*!< CCU4 GCSS: S2DSE Position               */\r
+#define CCU4_GCSS_S2DSE_Msk                   (0x01UL << CCU4_GCSS_S2DSE_Pos)                         /*!< CCU4 GCSS: S2DSE Mask                   */\r
+#define CCU4_GCSS_S2PSE_Pos                   10                                                      /*!< CCU4 GCSS: S2PSE Position               */\r
+#define CCU4_GCSS_S2PSE_Msk                   (0x01UL << CCU4_GCSS_S2PSE_Pos)                         /*!< CCU4 GCSS: S2PSE Mask                   */\r
+#define CCU4_GCSS_S3SE_Pos                    12                                                      /*!< CCU4 GCSS: S3SE Position                */\r
+#define CCU4_GCSS_S3SE_Msk                    (0x01UL << CCU4_GCSS_S3SE_Pos)                          /*!< CCU4 GCSS: S3SE Mask                    */\r
+#define CCU4_GCSS_S3DSE_Pos                   13                                                      /*!< CCU4 GCSS: S3DSE Position               */\r
+#define CCU4_GCSS_S3DSE_Msk                   (0x01UL << CCU4_GCSS_S3DSE_Pos)                         /*!< CCU4 GCSS: S3DSE Mask                   */\r
+#define CCU4_GCSS_S3PSE_Pos                   14                                                      /*!< CCU4 GCSS: S3PSE Position               */\r
+#define CCU4_GCSS_S3PSE_Msk                   (0x01UL << CCU4_GCSS_S3PSE_Pos)                         /*!< CCU4 GCSS: S3PSE Mask                   */\r
+#define CCU4_GCSS_S0STS_Pos                   16                                                      /*!< CCU4 GCSS: S0STS Position               */\r
+#define CCU4_GCSS_S0STS_Msk                   (0x01UL << CCU4_GCSS_S0STS_Pos)                         /*!< CCU4 GCSS: S0STS Mask                   */\r
+#define CCU4_GCSS_S1STS_Pos                   17                                                      /*!< CCU4 GCSS: S1STS Position               */\r
+#define CCU4_GCSS_S1STS_Msk                   (0x01UL << CCU4_GCSS_S1STS_Pos)                         /*!< CCU4 GCSS: S1STS Mask                   */\r
+#define CCU4_GCSS_S2STS_Pos                   18                                                      /*!< CCU4 GCSS: S2STS Position               */\r
+#define CCU4_GCSS_S2STS_Msk                   (0x01UL << CCU4_GCSS_S2STS_Pos)                         /*!< CCU4 GCSS: S2STS Mask                   */\r
+#define CCU4_GCSS_S3STS_Pos                   19                                                      /*!< CCU4 GCSS: S3STS Position               */\r
+#define CCU4_GCSS_S3STS_Msk                   (0x01UL << CCU4_GCSS_S3STS_Pos)                         /*!< CCU4 GCSS: S3STS Mask                   */\r
+\r
+/* ----------------------------------  CCU4_GCSC  --------------------------------- */\r
+#define CCU4_GCSC_S0SC_Pos                    0                                                       /*!< CCU4 GCSC: S0SC Position                */\r
+#define CCU4_GCSC_S0SC_Msk                    (0x01UL << CCU4_GCSC_S0SC_Pos)                          /*!< CCU4 GCSC: S0SC Mask                    */\r
+#define CCU4_GCSC_S0DSC_Pos                   1                                                       /*!< CCU4 GCSC: S0DSC Position               */\r
+#define CCU4_GCSC_S0DSC_Msk                   (0x01UL << CCU4_GCSC_S0DSC_Pos)                         /*!< CCU4 GCSC: S0DSC Mask                   */\r
+#define CCU4_GCSC_S0PSC_Pos                   2                                                       /*!< CCU4 GCSC: S0PSC Position               */\r
+#define CCU4_GCSC_S0PSC_Msk                   (0x01UL << CCU4_GCSC_S0PSC_Pos)                         /*!< CCU4 GCSC: S0PSC Mask                   */\r
+#define CCU4_GCSC_S1SC_Pos                    4                                                       /*!< CCU4 GCSC: S1SC Position                */\r
+#define CCU4_GCSC_S1SC_Msk                    (0x01UL << CCU4_GCSC_S1SC_Pos)                          /*!< CCU4 GCSC: S1SC Mask                    */\r
+#define CCU4_GCSC_S1DSC_Pos                   5                                                       /*!< CCU4 GCSC: S1DSC Position               */\r
+#define CCU4_GCSC_S1DSC_Msk                   (0x01UL << CCU4_GCSC_S1DSC_Pos)                         /*!< CCU4 GCSC: S1DSC Mask                   */\r
+#define CCU4_GCSC_S1PSC_Pos                   6                                                       /*!< CCU4 GCSC: S1PSC Position               */\r
+#define CCU4_GCSC_S1PSC_Msk                   (0x01UL << CCU4_GCSC_S1PSC_Pos)                         /*!< CCU4 GCSC: S1PSC Mask                   */\r
+#define CCU4_GCSC_S2SC_Pos                    8                                                       /*!< CCU4 GCSC: S2SC Position                */\r
+#define CCU4_GCSC_S2SC_Msk                    (0x01UL << CCU4_GCSC_S2SC_Pos)                          /*!< CCU4 GCSC: S2SC Mask                    */\r
+#define CCU4_GCSC_S2DSC_Pos                   9                                                       /*!< CCU4 GCSC: S2DSC Position               */\r
+#define CCU4_GCSC_S2DSC_Msk                   (0x01UL << CCU4_GCSC_S2DSC_Pos)                         /*!< CCU4 GCSC: S2DSC Mask                   */\r
+#define CCU4_GCSC_S2PSC_Pos                   10                                                      /*!< CCU4 GCSC: S2PSC Position               */\r
+#define CCU4_GCSC_S2PSC_Msk                   (0x01UL << CCU4_GCSC_S2PSC_Pos)                         /*!< CCU4 GCSC: S2PSC Mask                   */\r
+#define CCU4_GCSC_S3SC_Pos                    12                                                      /*!< CCU4 GCSC: S3SC Position                */\r
+#define CCU4_GCSC_S3SC_Msk                    (0x01UL << CCU4_GCSC_S3SC_Pos)                          /*!< CCU4 GCSC: S3SC Mask                    */\r
+#define CCU4_GCSC_S3DSC_Pos                   13                                                      /*!< CCU4 GCSC: S3DSC Position               */\r
+#define CCU4_GCSC_S3DSC_Msk                   (0x01UL << CCU4_GCSC_S3DSC_Pos)                         /*!< CCU4 GCSC: S3DSC Mask                   */\r
+#define CCU4_GCSC_S3PSC_Pos                   14                                                      /*!< CCU4 GCSC: S3PSC Position               */\r
+#define CCU4_GCSC_S3PSC_Msk                   (0x01UL << CCU4_GCSC_S3PSC_Pos)                         /*!< CCU4 GCSC: S3PSC Mask                   */\r
+#define CCU4_GCSC_S0STC_Pos                   16                                                      /*!< CCU4 GCSC: S0STC Position               */\r
+#define CCU4_GCSC_S0STC_Msk                   (0x01UL << CCU4_GCSC_S0STC_Pos)                         /*!< CCU4 GCSC: S0STC Mask                   */\r
+#define CCU4_GCSC_S1STC_Pos                   17                                                      /*!< CCU4 GCSC: S1STC Position               */\r
+#define CCU4_GCSC_S1STC_Msk                   (0x01UL << CCU4_GCSC_S1STC_Pos)                         /*!< CCU4 GCSC: S1STC Mask                   */\r
+#define CCU4_GCSC_S2STC_Pos                   18                                                      /*!< CCU4 GCSC: S2STC Position               */\r
+#define CCU4_GCSC_S2STC_Msk                   (0x01UL << CCU4_GCSC_S2STC_Pos)                         /*!< CCU4 GCSC: S2STC Mask                   */\r
+#define CCU4_GCSC_S3STC_Pos                   19                                                      /*!< CCU4 GCSC: S3STC Position               */\r
+#define CCU4_GCSC_S3STC_Msk                   (0x01UL << CCU4_GCSC_S3STC_Pos)                         /*!< CCU4 GCSC: S3STC Mask                   */\r
+\r
+/* ----------------------------------  CCU4_GCST  --------------------------------- */\r
+#define CCU4_GCST_S0SS_Pos                    0                                                       /*!< CCU4 GCST: S0SS Position                */\r
+#define CCU4_GCST_S0SS_Msk                    (0x01UL << CCU4_GCST_S0SS_Pos)                          /*!< CCU4 GCST: S0SS Mask                    */\r
+#define CCU4_GCST_S0DSS_Pos                   1                                                       /*!< CCU4 GCST: S0DSS Position               */\r
+#define CCU4_GCST_S0DSS_Msk                   (0x01UL << CCU4_GCST_S0DSS_Pos)                         /*!< CCU4 GCST: S0DSS Mask                   */\r
+#define CCU4_GCST_S0PSS_Pos                   2                                                       /*!< CCU4 GCST: S0PSS Position               */\r
+#define CCU4_GCST_S0PSS_Msk                   (0x01UL << CCU4_GCST_S0PSS_Pos)                         /*!< CCU4 GCST: S0PSS Mask                   */\r
+#define CCU4_GCST_S1SS_Pos                    4                                                       /*!< CCU4 GCST: S1SS Position                */\r
+#define CCU4_GCST_S1SS_Msk                    (0x01UL << CCU4_GCST_S1SS_Pos)                          /*!< CCU4 GCST: S1SS Mask                    */\r
+#define CCU4_GCST_S1DSS_Pos                   5                                                       /*!< CCU4 GCST: S1DSS Position               */\r
+#define CCU4_GCST_S1DSS_Msk                   (0x01UL << CCU4_GCST_S1DSS_Pos)                         /*!< CCU4 GCST: S1DSS Mask                   */\r
+#define CCU4_GCST_S1PSS_Pos                   6                                                       /*!< CCU4 GCST: S1PSS Position               */\r
+#define CCU4_GCST_S1PSS_Msk                   (0x01UL << CCU4_GCST_S1PSS_Pos)                         /*!< CCU4 GCST: S1PSS Mask                   */\r
+#define CCU4_GCST_S2SS_Pos                    8                                                       /*!< CCU4 GCST: S2SS Position                */\r
+#define CCU4_GCST_S2SS_Msk                    (0x01UL << CCU4_GCST_S2SS_Pos)                          /*!< CCU4 GCST: S2SS Mask                    */\r
+#define CCU4_GCST_S2DSS_Pos                   9                                                       /*!< CCU4 GCST: S2DSS Position               */\r
+#define CCU4_GCST_S2DSS_Msk                   (0x01UL << CCU4_GCST_S2DSS_Pos)                         /*!< CCU4 GCST: S2DSS Mask                   */\r
+#define CCU4_GCST_S2PSS_Pos                   10                                                      /*!< CCU4 GCST: S2PSS Position               */\r
+#define CCU4_GCST_S2PSS_Msk                   (0x01UL << CCU4_GCST_S2PSS_Pos)                         /*!< CCU4 GCST: S2PSS Mask                   */\r
+#define CCU4_GCST_S3SS_Pos                    12                                                      /*!< CCU4 GCST: S3SS Position                */\r
+#define CCU4_GCST_S3SS_Msk                    (0x01UL << CCU4_GCST_S3SS_Pos)                          /*!< CCU4 GCST: S3SS Mask                    */\r
+#define CCU4_GCST_S3DSS_Pos                   13                                                      /*!< CCU4 GCST: S3DSS Position               */\r
+#define CCU4_GCST_S3DSS_Msk                   (0x01UL << CCU4_GCST_S3DSS_Pos)                         /*!< CCU4 GCST: S3DSS Mask                   */\r
+#define CCU4_GCST_S3PSS_Pos                   14                                                      /*!< CCU4 GCST: S3PSS Position               */\r
+#define CCU4_GCST_S3PSS_Msk                   (0x01UL << CCU4_GCST_S3PSS_Pos)                         /*!< CCU4 GCST: S3PSS Mask                   */\r
+#define CCU4_GCST_CC40ST_Pos                  16                                                      /*!< CCU4 GCST: CC40ST Position              */\r
+#define CCU4_GCST_CC40ST_Msk                  (0x01UL << CCU4_GCST_CC40ST_Pos)                        /*!< CCU4 GCST: CC40ST Mask                  */\r
+#define CCU4_GCST_CC41ST_Pos                  17                                                      /*!< CCU4 GCST: CC41ST Position              */\r
+#define CCU4_GCST_CC41ST_Msk                  (0x01UL << CCU4_GCST_CC41ST_Pos)                        /*!< CCU4 GCST: CC41ST Mask                  */\r
+#define CCU4_GCST_CC42ST_Pos                  18                                                      /*!< CCU4 GCST: CC42ST Position              */\r
+#define CCU4_GCST_CC42ST_Msk                  (0x01UL << CCU4_GCST_CC42ST_Pos)                        /*!< CCU4 GCST: CC42ST Mask                  */\r
+#define CCU4_GCST_CC43ST_Pos                  19                                                      /*!< CCU4 GCST: CC43ST Position              */\r
+#define CCU4_GCST_CC43ST_Msk                  (0x01UL << CCU4_GCST_CC43ST_Pos)                        /*!< CCU4 GCST: CC43ST Mask                  */\r
+\r
+/* ----------------------------------  CCU4_ECRD  --------------------------------- */\r
+#define CCU4_ECRD_CAPV_Pos                    0                                                       /*!< CCU4 ECRD: CAPV Position                */\r
+#define CCU4_ECRD_CAPV_Msk                    (0x0000ffffUL << CCU4_ECRD_CAPV_Pos)                    /*!< CCU4 ECRD: CAPV Mask                    */\r
+#define CCU4_ECRD_FPCV_Pos                    16                                                      /*!< CCU4 ECRD: FPCV Position                */\r
+#define CCU4_ECRD_FPCV_Msk                    (0x0fUL << CCU4_ECRD_FPCV_Pos)                          /*!< CCU4 ECRD: FPCV Mask                    */\r
+#define CCU4_ECRD_SPTR_Pos                    20                                                      /*!< CCU4 ECRD: SPTR Position                */\r
+#define CCU4_ECRD_SPTR_Msk                    (0x03UL << CCU4_ECRD_SPTR_Pos)                          /*!< CCU4 ECRD: SPTR Mask                    */\r
+#define CCU4_ECRD_VPTR_Pos                    22                                                      /*!< CCU4 ECRD: VPTR Position                */\r
+#define CCU4_ECRD_VPTR_Msk                    (0x03UL << CCU4_ECRD_VPTR_Pos)                          /*!< CCU4 ECRD: VPTR Mask                    */\r
+#define CCU4_ECRD_FFL_Pos                     24                                                      /*!< CCU4 ECRD: FFL Position                 */\r
+#define CCU4_ECRD_FFL_Msk                     (0x01UL << CCU4_ECRD_FFL_Pos)                           /*!< CCU4 ECRD: FFL Mask                     */\r
+\r
+/* ----------------------------------  CCU4_MIDR  --------------------------------- */\r
+#define CCU4_MIDR_MODR_Pos                    0                                                       /*!< CCU4 MIDR: MODR Position                */\r
+#define CCU4_MIDR_MODR_Msk                    (0x000000ffUL << CCU4_MIDR_MODR_Pos)                    /*!< CCU4 MIDR: MODR Mask                    */\r
+#define CCU4_MIDR_MODT_Pos                    8                                                       /*!< CCU4 MIDR: MODT Position                */\r
+#define CCU4_MIDR_MODT_Msk                    (0x000000ffUL << CCU4_MIDR_MODT_Pos)                    /*!< CCU4 MIDR: MODT Mask                    */\r
+#define CCU4_MIDR_MODN_Pos                    16                                                      /*!< CCU4 MIDR: MODN Position                */\r
+#define CCU4_MIDR_MODN_Msk                    (0x0000ffffUL << CCU4_MIDR_MODN_Pos)                    /*!< CCU4 MIDR: MODN Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        Group 'CCU4_CC4' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CCU4_CC4_INS  -------------------------------- */\r
+#define CCU4_CC4_INS_EV0IS_Pos                0                                                       /*!< CCU4_CC4 INS: EV0IS Position            */\r
+#define CCU4_CC4_INS_EV0IS_Msk                (0x0fUL << CCU4_CC4_INS_EV0IS_Pos)                      /*!< CCU4_CC4 INS: EV0IS Mask                */\r
+#define CCU4_CC4_INS_EV1IS_Pos                4                                                       /*!< CCU4_CC4 INS: EV1IS Position            */\r
+#define CCU4_CC4_INS_EV1IS_Msk                (0x0fUL << CCU4_CC4_INS_EV1IS_Pos)                      /*!< CCU4_CC4 INS: EV1IS Mask                */\r
+#define CCU4_CC4_INS_EV2IS_Pos                8                                                       /*!< CCU4_CC4 INS: EV2IS Position            */\r
+#define CCU4_CC4_INS_EV2IS_Msk                (0x0fUL << CCU4_CC4_INS_EV2IS_Pos)                      /*!< CCU4_CC4 INS: EV2IS Mask                */\r
+#define CCU4_CC4_INS_EV0EM_Pos                16                                                      /*!< CCU4_CC4 INS: EV0EM Position            */\r
+#define CCU4_CC4_INS_EV0EM_Msk                (0x03UL << CCU4_CC4_INS_EV0EM_Pos)                      /*!< CCU4_CC4 INS: EV0EM Mask                */\r
+#define CCU4_CC4_INS_EV1EM_Pos                18                                                      /*!< CCU4_CC4 INS: EV1EM Position            */\r
+#define CCU4_CC4_INS_EV1EM_Msk                (0x03UL << CCU4_CC4_INS_EV1EM_Pos)                      /*!< CCU4_CC4 INS: EV1EM Mask                */\r
+#define CCU4_CC4_INS_EV2EM_Pos                20                                                      /*!< CCU4_CC4 INS: EV2EM Position            */\r
+#define CCU4_CC4_INS_EV2EM_Msk                (0x03UL << CCU4_CC4_INS_EV2EM_Pos)                      /*!< CCU4_CC4 INS: EV2EM Mask                */\r
+#define CCU4_CC4_INS_EV0LM_Pos                22                                                      /*!< CCU4_CC4 INS: EV0LM Position            */\r
+#define CCU4_CC4_INS_EV0LM_Msk                (0x01UL << CCU4_CC4_INS_EV0LM_Pos)                      /*!< CCU4_CC4 INS: EV0LM Mask                */\r
+#define CCU4_CC4_INS_EV1LM_Pos                23                                                      /*!< CCU4_CC4 INS: EV1LM Position            */\r
+#define CCU4_CC4_INS_EV1LM_Msk                (0x01UL << CCU4_CC4_INS_EV1LM_Pos)                      /*!< CCU4_CC4 INS: EV1LM Mask                */\r
+#define CCU4_CC4_INS_EV2LM_Pos                24                                                      /*!< CCU4_CC4 INS: EV2LM Position            */\r
+#define CCU4_CC4_INS_EV2LM_Msk                (0x01UL << CCU4_CC4_INS_EV2LM_Pos)                      /*!< CCU4_CC4 INS: EV2LM Mask                */\r
+#define CCU4_CC4_INS_LPF0M_Pos                25                                                      /*!< CCU4_CC4 INS: LPF0M Position            */\r
+#define CCU4_CC4_INS_LPF0M_Msk                (0x03UL << CCU4_CC4_INS_LPF0M_Pos)                      /*!< CCU4_CC4 INS: LPF0M Mask                */\r
+#define CCU4_CC4_INS_LPF1M_Pos                27                                                      /*!< CCU4_CC4 INS: LPF1M Position            */\r
+#define CCU4_CC4_INS_LPF1M_Msk                (0x03UL << CCU4_CC4_INS_LPF1M_Pos)                      /*!< CCU4_CC4 INS: LPF1M Mask                */\r
+#define CCU4_CC4_INS_LPF2M_Pos                29                                                      /*!< CCU4_CC4 INS: LPF2M Position            */\r
+#define CCU4_CC4_INS_LPF2M_Msk                (0x03UL << CCU4_CC4_INS_LPF2M_Pos)                      /*!< CCU4_CC4 INS: LPF2M Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_CMC  -------------------------------- */\r
+#define CCU4_CC4_CMC_STRTS_Pos                0                                                       /*!< CCU4_CC4 CMC: STRTS Position            */\r
+#define CCU4_CC4_CMC_STRTS_Msk                (0x03UL << CCU4_CC4_CMC_STRTS_Pos)                      /*!< CCU4_CC4 CMC: STRTS Mask                */\r
+#define CCU4_CC4_CMC_ENDS_Pos                 2                                                       /*!< CCU4_CC4 CMC: ENDS Position             */\r
+#define CCU4_CC4_CMC_ENDS_Msk                 (0x03UL << CCU4_CC4_CMC_ENDS_Pos)                       /*!< CCU4_CC4 CMC: ENDS Mask                 */\r
+#define CCU4_CC4_CMC_CAP0S_Pos                4                                                       /*!< CCU4_CC4 CMC: CAP0S Position            */\r
+#define CCU4_CC4_CMC_CAP0S_Msk                (0x03UL << CCU4_CC4_CMC_CAP0S_Pos)                      /*!< CCU4_CC4 CMC: CAP0S Mask                */\r
+#define CCU4_CC4_CMC_CAP1S_Pos                6                                                       /*!< CCU4_CC4 CMC: CAP1S Position            */\r
+#define CCU4_CC4_CMC_CAP1S_Msk                (0x03UL << CCU4_CC4_CMC_CAP1S_Pos)                      /*!< CCU4_CC4 CMC: CAP1S Mask                */\r
+#define CCU4_CC4_CMC_GATES_Pos                8                                                       /*!< CCU4_CC4 CMC: GATES Position            */\r
+#define CCU4_CC4_CMC_GATES_Msk                (0x03UL << CCU4_CC4_CMC_GATES_Pos)                      /*!< CCU4_CC4 CMC: GATES Mask                */\r
+#define CCU4_CC4_CMC_UDS_Pos                  10                                                      /*!< CCU4_CC4 CMC: UDS Position              */\r
+#define CCU4_CC4_CMC_UDS_Msk                  (0x03UL << CCU4_CC4_CMC_UDS_Pos)                        /*!< CCU4_CC4 CMC: UDS Mask                  */\r
+#define CCU4_CC4_CMC_LDS_Pos                  12                                                      /*!< CCU4_CC4 CMC: LDS Position              */\r
+#define CCU4_CC4_CMC_LDS_Msk                  (0x03UL << CCU4_CC4_CMC_LDS_Pos)                        /*!< CCU4_CC4 CMC: LDS Mask                  */\r
+#define CCU4_CC4_CMC_CNTS_Pos                 14                                                      /*!< CCU4_CC4 CMC: CNTS Position             */\r
+#define CCU4_CC4_CMC_CNTS_Msk                 (0x03UL << CCU4_CC4_CMC_CNTS_Pos)                       /*!< CCU4_CC4 CMC: CNTS Mask                 */\r
+#define CCU4_CC4_CMC_OFS_Pos                  16                                                      /*!< CCU4_CC4 CMC: OFS Position              */\r
+#define CCU4_CC4_CMC_OFS_Msk                  (0x01UL << CCU4_CC4_CMC_OFS_Pos)                        /*!< CCU4_CC4 CMC: OFS Mask                  */\r
+#define CCU4_CC4_CMC_TS_Pos                   17                                                      /*!< CCU4_CC4 CMC: TS Position               */\r
+#define CCU4_CC4_CMC_TS_Msk                   (0x01UL << CCU4_CC4_CMC_TS_Pos)                         /*!< CCU4_CC4 CMC: TS Mask                   */\r
+#define CCU4_CC4_CMC_MOS_Pos                  18                                                      /*!< CCU4_CC4 CMC: MOS Position              */\r
+#define CCU4_CC4_CMC_MOS_Msk                  (0x03UL << CCU4_CC4_CMC_MOS_Pos)                        /*!< CCU4_CC4 CMC: MOS Mask                  */\r
+#define CCU4_CC4_CMC_TCE_Pos                  20                                                      /*!< CCU4_CC4 CMC: TCE Position              */\r
+#define CCU4_CC4_CMC_TCE_Msk                  (0x01UL << CCU4_CC4_CMC_TCE_Pos)                        /*!< CCU4_CC4 CMC: TCE Mask                  */\r
+\r
+/* --------------------------------  CCU4_CC4_TCST  ------------------------------- */\r
+#define CCU4_CC4_TCST_TRB_Pos                 0                                                       /*!< CCU4_CC4 TCST: TRB Position             */\r
+#define CCU4_CC4_TCST_TRB_Msk                 (0x01UL << CCU4_CC4_TCST_TRB_Pos)                       /*!< CCU4_CC4 TCST: TRB Mask                 */\r
+#define CCU4_CC4_TCST_CDIR_Pos                1                                                       /*!< CCU4_CC4 TCST: CDIR Position            */\r
+#define CCU4_CC4_TCST_CDIR_Msk                (0x01UL << CCU4_CC4_TCST_CDIR_Pos)                      /*!< CCU4_CC4 TCST: CDIR Mask                */\r
+\r
+/* -------------------------------  CCU4_CC4_TCSET  ------------------------------- */\r
+#define CCU4_CC4_TCSET_TRBS_Pos               0                                                       /*!< CCU4_CC4 TCSET: TRBS Position           */\r
+#define CCU4_CC4_TCSET_TRBS_Msk               (0x01UL << CCU4_CC4_TCSET_TRBS_Pos)                     /*!< CCU4_CC4 TCSET: TRBS Mask               */\r
+\r
+/* -------------------------------  CCU4_CC4_TCCLR  ------------------------------- */\r
+#define CCU4_CC4_TCCLR_TRBC_Pos               0                                                       /*!< CCU4_CC4 TCCLR: TRBC Position           */\r
+#define CCU4_CC4_TCCLR_TRBC_Msk               (0x01UL << CCU4_CC4_TCCLR_TRBC_Pos)                     /*!< CCU4_CC4 TCCLR: TRBC Mask               */\r
+#define CCU4_CC4_TCCLR_TCC_Pos                1                                                       /*!< CCU4_CC4 TCCLR: TCC Position            */\r
+#define CCU4_CC4_TCCLR_TCC_Msk                (0x01UL << CCU4_CC4_TCCLR_TCC_Pos)                      /*!< CCU4_CC4 TCCLR: TCC Mask                */\r
+#define CCU4_CC4_TCCLR_DITC_Pos               2                                                       /*!< CCU4_CC4 TCCLR: DITC Position           */\r
+#define CCU4_CC4_TCCLR_DITC_Msk               (0x01UL << CCU4_CC4_TCCLR_DITC_Pos)                     /*!< CCU4_CC4 TCCLR: DITC Mask               */\r
+\r
+/* ---------------------------------  CCU4_CC4_TC  -------------------------------- */\r
+#define CCU4_CC4_TC_TCM_Pos                   0                                                       /*!< CCU4_CC4 TC: TCM Position               */\r
+#define CCU4_CC4_TC_TCM_Msk                   (0x01UL << CCU4_CC4_TC_TCM_Pos)                         /*!< CCU4_CC4 TC: TCM Mask                   */\r
+#define CCU4_CC4_TC_TSSM_Pos                  1                                                       /*!< CCU4_CC4 TC: TSSM Position              */\r
+#define CCU4_CC4_TC_TSSM_Msk                  (0x01UL << CCU4_CC4_TC_TSSM_Pos)                        /*!< CCU4_CC4 TC: TSSM Mask                  */\r
+#define CCU4_CC4_TC_CLST_Pos                  2                                                       /*!< CCU4_CC4 TC: CLST Position              */\r
+#define CCU4_CC4_TC_CLST_Msk                  (0x01UL << CCU4_CC4_TC_CLST_Pos)                        /*!< CCU4_CC4 TC: CLST Mask                  */\r
+#define CCU4_CC4_TC_CMOD_Pos                  3                                                       /*!< CCU4_CC4 TC: CMOD Position              */\r
+#define CCU4_CC4_TC_CMOD_Msk                  (0x01UL << CCU4_CC4_TC_CMOD_Pos)                        /*!< CCU4_CC4 TC: CMOD Mask                  */\r
+#define CCU4_CC4_TC_ECM_Pos                   4                                                       /*!< CCU4_CC4 TC: ECM Position               */\r
+#define CCU4_CC4_TC_ECM_Msk                   (0x01UL << CCU4_CC4_TC_ECM_Pos)                         /*!< CCU4_CC4 TC: ECM Mask                   */\r
+#define CCU4_CC4_TC_CAPC_Pos                  5                                                       /*!< CCU4_CC4 TC: CAPC Position              */\r
+#define CCU4_CC4_TC_CAPC_Msk                  (0x03UL << CCU4_CC4_TC_CAPC_Pos)                        /*!< CCU4_CC4 TC: CAPC Mask                  */\r
+#define CCU4_CC4_TC_ENDM_Pos                  8                                                       /*!< CCU4_CC4 TC: ENDM Position              */\r
+#define CCU4_CC4_TC_ENDM_Msk                  (0x03UL << CCU4_CC4_TC_ENDM_Pos)                        /*!< CCU4_CC4 TC: ENDM Mask                  */\r
+#define CCU4_CC4_TC_STRM_Pos                  10                                                      /*!< CCU4_CC4 TC: STRM Position              */\r
+#define CCU4_CC4_TC_STRM_Msk                  (0x01UL << CCU4_CC4_TC_STRM_Pos)                        /*!< CCU4_CC4 TC: STRM Mask                  */\r
+#define CCU4_CC4_TC_SCE_Pos                   11                                                      /*!< CCU4_CC4 TC: SCE Position               */\r
+#define CCU4_CC4_TC_SCE_Msk                   (0x01UL << CCU4_CC4_TC_SCE_Pos)                         /*!< CCU4_CC4 TC: SCE Mask                   */\r
+#define CCU4_CC4_TC_CCS_Pos                   12                                                      /*!< CCU4_CC4 TC: CCS Position               */\r
+#define CCU4_CC4_TC_CCS_Msk                   (0x01UL << CCU4_CC4_TC_CCS_Pos)                         /*!< CCU4_CC4 TC: CCS Mask                   */\r
+#define CCU4_CC4_TC_DITHE_Pos                 13                                                      /*!< CCU4_CC4 TC: DITHE Position             */\r
+#define CCU4_CC4_TC_DITHE_Msk                 (0x03UL << CCU4_CC4_TC_DITHE_Pos)                       /*!< CCU4_CC4 TC: DITHE Mask                 */\r
+#define CCU4_CC4_TC_DIM_Pos                   15                                                      /*!< CCU4_CC4 TC: DIM Position               */\r
+#define CCU4_CC4_TC_DIM_Msk                   (0x01UL << CCU4_CC4_TC_DIM_Pos)                         /*!< CCU4_CC4 TC: DIM Mask                   */\r
+#define CCU4_CC4_TC_FPE_Pos                   16                                                      /*!< CCU4_CC4 TC: FPE Position               */\r
+#define CCU4_CC4_TC_FPE_Msk                   (0x01UL << CCU4_CC4_TC_FPE_Pos)                         /*!< CCU4_CC4 TC: FPE Mask                   */\r
+#define CCU4_CC4_TC_TRAPE_Pos                 17                                                      /*!< CCU4_CC4 TC: TRAPE Position             */\r
+#define CCU4_CC4_TC_TRAPE_Msk                 (0x01UL << CCU4_CC4_TC_TRAPE_Pos)                       /*!< CCU4_CC4 TC: TRAPE Mask                 */\r
+#define CCU4_CC4_TC_TRPSE_Pos                 21                                                      /*!< CCU4_CC4 TC: TRPSE Position             */\r
+#define CCU4_CC4_TC_TRPSE_Msk                 (0x01UL << CCU4_CC4_TC_TRPSE_Pos)                       /*!< CCU4_CC4 TC: TRPSE Mask                 */\r
+#define CCU4_CC4_TC_TRPSW_Pos                 22                                                      /*!< CCU4_CC4 TC: TRPSW Position             */\r
+#define CCU4_CC4_TC_TRPSW_Msk                 (0x01UL << CCU4_CC4_TC_TRPSW_Pos)                       /*!< CCU4_CC4 TC: TRPSW Mask                 */\r
+#define CCU4_CC4_TC_EMS_Pos                   23                                                      /*!< CCU4_CC4 TC: EMS Position               */\r
+#define CCU4_CC4_TC_EMS_Msk                   (0x01UL << CCU4_CC4_TC_EMS_Pos)                         /*!< CCU4_CC4 TC: EMS Mask                   */\r
+#define CCU4_CC4_TC_EMT_Pos                   24                                                      /*!< CCU4_CC4 TC: EMT Position               */\r
+#define CCU4_CC4_TC_EMT_Msk                   (0x01UL << CCU4_CC4_TC_EMT_Pos)                         /*!< CCU4_CC4 TC: EMT Mask                   */\r
+#define CCU4_CC4_TC_MCME_Pos                  25                                                      /*!< CCU4_CC4 TC: MCME Position              */\r
+#define CCU4_CC4_TC_MCME_Msk                  (0x01UL << CCU4_CC4_TC_MCME_Pos)                        /*!< CCU4_CC4 TC: MCME Mask                  */\r
+\r
+/* --------------------------------  CCU4_CC4_PSL  -------------------------------- */\r
+#define CCU4_CC4_PSL_PSL_Pos                  0                                                       /*!< CCU4_CC4 PSL: PSL Position              */\r
+#define CCU4_CC4_PSL_PSL_Msk                  (0x01UL << CCU4_CC4_PSL_PSL_Pos)                        /*!< CCU4_CC4 PSL: PSL Mask                  */\r
+\r
+/* --------------------------------  CCU4_CC4_DIT  -------------------------------- */\r
+#define CCU4_CC4_DIT_DCV_Pos                  0                                                       /*!< CCU4_CC4 DIT: DCV Position              */\r
+#define CCU4_CC4_DIT_DCV_Msk                  (0x0fUL << CCU4_CC4_DIT_DCV_Pos)                        /*!< CCU4_CC4 DIT: DCV Mask                  */\r
+#define CCU4_CC4_DIT_DCNT_Pos                 8                                                       /*!< CCU4_CC4 DIT: DCNT Position             */\r
+#define CCU4_CC4_DIT_DCNT_Msk                 (0x0fUL << CCU4_CC4_DIT_DCNT_Pos)                       /*!< CCU4_CC4 DIT: DCNT Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_DITS  ------------------------------- */\r
+#define CCU4_CC4_DITS_DCVS_Pos                0                                                       /*!< CCU4_CC4 DITS: DCVS Position            */\r
+#define CCU4_CC4_DITS_DCVS_Msk                (0x0fUL << CCU4_CC4_DITS_DCVS_Pos)                      /*!< CCU4_CC4 DITS: DCVS Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_PSC  -------------------------------- */\r
+#define CCU4_CC4_PSC_PSIV_Pos                 0                                                       /*!< CCU4_CC4 PSC: PSIV Position             */\r
+#define CCU4_CC4_PSC_PSIV_Msk                 (0x0fUL << CCU4_CC4_PSC_PSIV_Pos)                       /*!< CCU4_CC4 PSC: PSIV Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_FPC  -------------------------------- */\r
+#define CCU4_CC4_FPC_PCMP_Pos                 0                                                       /*!< CCU4_CC4 FPC: PCMP Position             */\r
+#define CCU4_CC4_FPC_PCMP_Msk                 (0x0fUL << CCU4_CC4_FPC_PCMP_Pos)                       /*!< CCU4_CC4 FPC: PCMP Mask                 */\r
+#define CCU4_CC4_FPC_PVAL_Pos                 8                                                       /*!< CCU4_CC4 FPC: PVAL Position             */\r
+#define CCU4_CC4_FPC_PVAL_Msk                 (0x0fUL << CCU4_CC4_FPC_PVAL_Pos)                       /*!< CCU4_CC4 FPC: PVAL Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_FPCS  ------------------------------- */\r
+#define CCU4_CC4_FPCS_PCMP_Pos                0                                                       /*!< CCU4_CC4 FPCS: PCMP Position            */\r
+#define CCU4_CC4_FPCS_PCMP_Msk                (0x0fUL << CCU4_CC4_FPCS_PCMP_Pos)                      /*!< CCU4_CC4 FPCS: PCMP Mask                */\r
+\r
+/* ---------------------------------  CCU4_CC4_PR  -------------------------------- */\r
+#define CCU4_CC4_PR_PR_Pos                    0                                                       /*!< CCU4_CC4 PR: PR Position                */\r
+#define CCU4_CC4_PR_PR_Msk                    (0x0000ffffUL << CCU4_CC4_PR_PR_Pos)                    /*!< CCU4_CC4 PR: PR Mask                    */\r
+\r
+/* --------------------------------  CCU4_CC4_PRS  -------------------------------- */\r
+#define CCU4_CC4_PRS_PRS_Pos                  0                                                       /*!< CCU4_CC4 PRS: PRS Position              */\r
+#define CCU4_CC4_PRS_PRS_Msk                  (0x0000ffffUL << CCU4_CC4_PRS_PRS_Pos)                  /*!< CCU4_CC4 PRS: PRS Mask                  */\r
+\r
+/* ---------------------------------  CCU4_CC4_CR  -------------------------------- */\r
+#define CCU4_CC4_CR_CR_Pos                    0                                                       /*!< CCU4_CC4 CR: CR Position                */\r
+#define CCU4_CC4_CR_CR_Msk                    (0x0000ffffUL << CCU4_CC4_CR_CR_Pos)                    /*!< CCU4_CC4 CR: CR Mask                    */\r
+\r
+/* --------------------------------  CCU4_CC4_CRS  -------------------------------- */\r
+#define CCU4_CC4_CRS_CRS_Pos                  0                                                       /*!< CCU4_CC4 CRS: CRS Position              */\r
+#define CCU4_CC4_CRS_CRS_Msk                  (0x0000ffffUL << CCU4_CC4_CRS_CRS_Pos)                  /*!< CCU4_CC4 CRS: CRS Mask                  */\r
+\r
+/* -------------------------------  CCU4_CC4_TIMER  ------------------------------- */\r
+#define CCU4_CC4_TIMER_TVAL_Pos               0                                                       /*!< CCU4_CC4 TIMER: TVAL Position           */\r
+#define CCU4_CC4_TIMER_TVAL_Msk               (0x0000ffffUL << CCU4_CC4_TIMER_TVAL_Pos)               /*!< CCU4_CC4 TIMER: TVAL Mask               */\r
+\r
+/* ---------------------------------  CCU4_CC4_CV  -------------------------------- */\r
+#define CCU4_CC4_CV_CAPTV_Pos                 0                                                       /*!< CCU4_CC4 CV: CAPTV Position             */\r
+#define CCU4_CC4_CV_CAPTV_Msk                 (0x0000ffffUL << CCU4_CC4_CV_CAPTV_Pos)                 /*!< CCU4_CC4 CV: CAPTV Mask                 */\r
+#define CCU4_CC4_CV_FPCV_Pos                  16                                                      /*!< CCU4_CC4 CV: FPCV Position              */\r
+#define CCU4_CC4_CV_FPCV_Msk                  (0x0fUL << CCU4_CC4_CV_FPCV_Pos)                        /*!< CCU4_CC4 CV: FPCV Mask                  */\r
+#define CCU4_CC4_CV_FFL_Pos                   20                                                      /*!< CCU4_CC4 CV: FFL Position               */\r
+#define CCU4_CC4_CV_FFL_Msk                   (0x01UL << CCU4_CC4_CV_FFL_Pos)                         /*!< CCU4_CC4 CV: FFL Mask                   */\r
+\r
+/* --------------------------------  CCU4_CC4_INTS  ------------------------------- */\r
+#define CCU4_CC4_INTS_PMUS_Pos                0                                                       /*!< CCU4_CC4 INTS: PMUS Position            */\r
+#define CCU4_CC4_INTS_PMUS_Msk                (0x01UL << CCU4_CC4_INTS_PMUS_Pos)                      /*!< CCU4_CC4 INTS: PMUS Mask                */\r
+#define CCU4_CC4_INTS_OMDS_Pos                1                                                       /*!< CCU4_CC4 INTS: OMDS Position            */\r
+#define CCU4_CC4_INTS_OMDS_Msk                (0x01UL << CCU4_CC4_INTS_OMDS_Pos)                      /*!< CCU4_CC4 INTS: OMDS Mask                */\r
+#define CCU4_CC4_INTS_CMUS_Pos                2                                                       /*!< CCU4_CC4 INTS: CMUS Position            */\r
+#define CCU4_CC4_INTS_CMUS_Msk                (0x01UL << CCU4_CC4_INTS_CMUS_Pos)                      /*!< CCU4_CC4 INTS: CMUS Mask                */\r
+#define CCU4_CC4_INTS_CMDS_Pos                3                                                       /*!< CCU4_CC4 INTS: CMDS Position            */\r
+#define CCU4_CC4_INTS_CMDS_Msk                (0x01UL << CCU4_CC4_INTS_CMDS_Pos)                      /*!< CCU4_CC4 INTS: CMDS Mask                */\r
+#define CCU4_CC4_INTS_E0AS_Pos                8                                                       /*!< CCU4_CC4 INTS: E0AS Position            */\r
+#define CCU4_CC4_INTS_E0AS_Msk                (0x01UL << CCU4_CC4_INTS_E0AS_Pos)                      /*!< CCU4_CC4 INTS: E0AS Mask                */\r
+#define CCU4_CC4_INTS_E1AS_Pos                9                                                       /*!< CCU4_CC4 INTS: E1AS Position            */\r
+#define CCU4_CC4_INTS_E1AS_Msk                (0x01UL << CCU4_CC4_INTS_E1AS_Pos)                      /*!< CCU4_CC4 INTS: E1AS Mask                */\r
+#define CCU4_CC4_INTS_E2AS_Pos                10                                                      /*!< CCU4_CC4 INTS: E2AS Position            */\r
+#define CCU4_CC4_INTS_E2AS_Msk                (0x01UL << CCU4_CC4_INTS_E2AS_Pos)                      /*!< CCU4_CC4 INTS: E2AS Mask                */\r
+#define CCU4_CC4_INTS_TRPF_Pos                11                                                      /*!< CCU4_CC4 INTS: TRPF Position            */\r
+#define CCU4_CC4_INTS_TRPF_Msk                (0x01UL << CCU4_CC4_INTS_TRPF_Pos)                      /*!< CCU4_CC4 INTS: TRPF Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_INTE  ------------------------------- */\r
+#define CCU4_CC4_INTE_PME_Pos                 0                                                       /*!< CCU4_CC4 INTE: PME Position             */\r
+#define CCU4_CC4_INTE_PME_Msk                 (0x01UL << CCU4_CC4_INTE_PME_Pos)                       /*!< CCU4_CC4 INTE: PME Mask                 */\r
+#define CCU4_CC4_INTE_OME_Pos                 1                                                       /*!< CCU4_CC4 INTE: OME Position             */\r
+#define CCU4_CC4_INTE_OME_Msk                 (0x01UL << CCU4_CC4_INTE_OME_Pos)                       /*!< CCU4_CC4 INTE: OME Mask                 */\r
+#define CCU4_CC4_INTE_CMUE_Pos                2                                                       /*!< CCU4_CC4 INTE: CMUE Position            */\r
+#define CCU4_CC4_INTE_CMUE_Msk                (0x01UL << CCU4_CC4_INTE_CMUE_Pos)                      /*!< CCU4_CC4 INTE: CMUE Mask                */\r
+#define CCU4_CC4_INTE_CMDE_Pos                3                                                       /*!< CCU4_CC4 INTE: CMDE Position            */\r
+#define CCU4_CC4_INTE_CMDE_Msk                (0x01UL << CCU4_CC4_INTE_CMDE_Pos)                      /*!< CCU4_CC4 INTE: CMDE Mask                */\r
+#define CCU4_CC4_INTE_E0AE_Pos                8                                                       /*!< CCU4_CC4 INTE: E0AE Position            */\r
+#define CCU4_CC4_INTE_E0AE_Msk                (0x01UL << CCU4_CC4_INTE_E0AE_Pos)                      /*!< CCU4_CC4 INTE: E0AE Mask                */\r
+#define CCU4_CC4_INTE_E1AE_Pos                9                                                       /*!< CCU4_CC4 INTE: E1AE Position            */\r
+#define CCU4_CC4_INTE_E1AE_Msk                (0x01UL << CCU4_CC4_INTE_E1AE_Pos)                      /*!< CCU4_CC4 INTE: E1AE Mask                */\r
+#define CCU4_CC4_INTE_E2AE_Pos                10                                                      /*!< CCU4_CC4 INTE: E2AE Position            */\r
+#define CCU4_CC4_INTE_E2AE_Msk                (0x01UL << CCU4_CC4_INTE_E2AE_Pos)                      /*!< CCU4_CC4 INTE: E2AE Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_SRS  -------------------------------- */\r
+#define CCU4_CC4_SRS_POSR_Pos                 0                                                       /*!< CCU4_CC4 SRS: POSR Position             */\r
+#define CCU4_CC4_SRS_POSR_Msk                 (0x03UL << CCU4_CC4_SRS_POSR_Pos)                       /*!< CCU4_CC4 SRS: POSR Mask                 */\r
+#define CCU4_CC4_SRS_CMSR_Pos                 2                                                       /*!< CCU4_CC4 SRS: CMSR Position             */\r
+#define CCU4_CC4_SRS_CMSR_Msk                 (0x03UL << CCU4_CC4_SRS_CMSR_Pos)                       /*!< CCU4_CC4 SRS: CMSR Mask                 */\r
+#define CCU4_CC4_SRS_E0SR_Pos                 8                                                       /*!< CCU4_CC4 SRS: E0SR Position             */\r
+#define CCU4_CC4_SRS_E0SR_Msk                 (0x03UL << CCU4_CC4_SRS_E0SR_Pos)                       /*!< CCU4_CC4 SRS: E0SR Mask                 */\r
+#define CCU4_CC4_SRS_E1SR_Pos                 10                                                      /*!< CCU4_CC4 SRS: E1SR Position             */\r
+#define CCU4_CC4_SRS_E1SR_Msk                 (0x03UL << CCU4_CC4_SRS_E1SR_Pos)                       /*!< CCU4_CC4 SRS: E1SR Mask                 */\r
+#define CCU4_CC4_SRS_E2SR_Pos                 12                                                      /*!< CCU4_CC4 SRS: E2SR Position             */\r
+#define CCU4_CC4_SRS_E2SR_Msk                 (0x03UL << CCU4_CC4_SRS_E2SR_Pos)                       /*!< CCU4_CC4 SRS: E2SR Mask                 */\r
+\r
+/* --------------------------------  CCU4_CC4_SWS  -------------------------------- */\r
+#define CCU4_CC4_SWS_SPM_Pos                  0                                                       /*!< CCU4_CC4 SWS: SPM Position              */\r
+#define CCU4_CC4_SWS_SPM_Msk                  (0x01UL << CCU4_CC4_SWS_SPM_Pos)                        /*!< CCU4_CC4 SWS: SPM Mask                  */\r
+#define CCU4_CC4_SWS_SOM_Pos                  1                                                       /*!< CCU4_CC4 SWS: SOM Position              */\r
+#define CCU4_CC4_SWS_SOM_Msk                  (0x01UL << CCU4_CC4_SWS_SOM_Pos)                        /*!< CCU4_CC4 SWS: SOM Mask                  */\r
+#define CCU4_CC4_SWS_SCMU_Pos                 2                                                       /*!< CCU4_CC4 SWS: SCMU Position             */\r
+#define CCU4_CC4_SWS_SCMU_Msk                 (0x01UL << CCU4_CC4_SWS_SCMU_Pos)                       /*!< CCU4_CC4 SWS: SCMU Mask                 */\r
+#define CCU4_CC4_SWS_SCMD_Pos                 3                                                       /*!< CCU4_CC4 SWS: SCMD Position             */\r
+#define CCU4_CC4_SWS_SCMD_Msk                 (0x01UL << CCU4_CC4_SWS_SCMD_Pos)                       /*!< CCU4_CC4 SWS: SCMD Mask                 */\r
+#define CCU4_CC4_SWS_SE0A_Pos                 8                                                       /*!< CCU4_CC4 SWS: SE0A Position             */\r
+#define CCU4_CC4_SWS_SE0A_Msk                 (0x01UL << CCU4_CC4_SWS_SE0A_Pos)                       /*!< CCU4_CC4 SWS: SE0A Mask                 */\r
+#define CCU4_CC4_SWS_SE1A_Pos                 9                                                       /*!< CCU4_CC4 SWS: SE1A Position             */\r
+#define CCU4_CC4_SWS_SE1A_Msk                 (0x01UL << CCU4_CC4_SWS_SE1A_Pos)                       /*!< CCU4_CC4 SWS: SE1A Mask                 */\r
+#define CCU4_CC4_SWS_SE2A_Pos                 10                                                      /*!< CCU4_CC4 SWS: SE2A Position             */\r
+#define CCU4_CC4_SWS_SE2A_Msk                 (0x01UL << CCU4_CC4_SWS_SE2A_Pos)                       /*!< CCU4_CC4 SWS: SE2A Mask                 */\r
+#define CCU4_CC4_SWS_STRPF_Pos                11                                                      /*!< CCU4_CC4 SWS: STRPF Position            */\r
+#define CCU4_CC4_SWS_STRPF_Msk                (0x01UL << CCU4_CC4_SWS_STRPF_Pos)                      /*!< CCU4_CC4 SWS: STRPF Mask                */\r
+\r
+/* --------------------------------  CCU4_CC4_SWR  -------------------------------- */\r
+#define CCU4_CC4_SWR_RPM_Pos                  0                                                       /*!< CCU4_CC4 SWR: RPM Position              */\r
+#define CCU4_CC4_SWR_RPM_Msk                  (0x01UL << CCU4_CC4_SWR_RPM_Pos)                        /*!< CCU4_CC4 SWR: RPM Mask                  */\r
+#define CCU4_CC4_SWR_ROM_Pos                  1                                                       /*!< CCU4_CC4 SWR: ROM Position              */\r
+#define CCU4_CC4_SWR_ROM_Msk                  (0x01UL << CCU4_CC4_SWR_ROM_Pos)                        /*!< CCU4_CC4 SWR: ROM Mask                  */\r
+#define CCU4_CC4_SWR_RCMU_Pos                 2                                                       /*!< CCU4_CC4 SWR: RCMU Position             */\r
+#define CCU4_CC4_SWR_RCMU_Msk                 (0x01UL << CCU4_CC4_SWR_RCMU_Pos)                       /*!< CCU4_CC4 SWR: RCMU Mask                 */\r
+#define CCU4_CC4_SWR_RCMD_Pos                 3                                                       /*!< CCU4_CC4 SWR: RCMD Position             */\r
+#define CCU4_CC4_SWR_RCMD_Msk                 (0x01UL << CCU4_CC4_SWR_RCMD_Pos)                       /*!< CCU4_CC4 SWR: RCMD Mask                 */\r
+#define CCU4_CC4_SWR_RE0A_Pos                 8                                                       /*!< CCU4_CC4 SWR: RE0A Position             */\r
+#define CCU4_CC4_SWR_RE0A_Msk                 (0x01UL << CCU4_CC4_SWR_RE0A_Pos)                       /*!< CCU4_CC4 SWR: RE0A Mask                 */\r
+#define CCU4_CC4_SWR_RE1A_Pos                 9                                                       /*!< CCU4_CC4 SWR: RE1A Position             */\r
+#define CCU4_CC4_SWR_RE1A_Msk                 (0x01UL << CCU4_CC4_SWR_RE1A_Pos)                       /*!< CCU4_CC4 SWR: RE1A Mask                 */\r
+#define CCU4_CC4_SWR_RE2A_Pos                 10                                                      /*!< CCU4_CC4 SWR: RE2A Position             */\r
+#define CCU4_CC4_SWR_RE2A_Msk                 (0x01UL << CCU4_CC4_SWR_RE2A_Pos)                       /*!< CCU4_CC4 SWR: RE2A Mask                 */\r
+#define CCU4_CC4_SWR_RTRPF_Pos                11                                                      /*!< CCU4_CC4 SWR: RTRPF Position            */\r
+#define CCU4_CC4_SWR_RTRPF_Msk                (0x01UL << CCU4_CC4_SWR_RTRPF_Pos)                      /*!< CCU4_CC4 SWR: RTRPF Mask                */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'CCU8' Position & Mask          ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  CCU8_GCTRL  --------------------------------- */\r
+#define CCU8_GCTRL_PRBC_Pos                   0                                                       /*!< CCU8 GCTRL: PRBC Position               */\r
+#define CCU8_GCTRL_PRBC_Msk                   (0x07UL << CCU8_GCTRL_PRBC_Pos)                         /*!< CCU8 GCTRL: PRBC Mask                   */\r
+#define CCU8_GCTRL_PCIS_Pos                   4                                                       /*!< CCU8 GCTRL: PCIS Position               */\r
+#define CCU8_GCTRL_PCIS_Msk                   (0x03UL << CCU8_GCTRL_PCIS_Pos)                         /*!< CCU8 GCTRL: PCIS Mask                   */\r
+#define CCU8_GCTRL_SUSCFG_Pos                 8                                                       /*!< CCU8 GCTRL: SUSCFG Position             */\r
+#define CCU8_GCTRL_SUSCFG_Msk                 (0x03UL << CCU8_GCTRL_SUSCFG_Pos)                       /*!< CCU8 GCTRL: SUSCFG Mask                 */\r
+#define CCU8_GCTRL_MSE0_Pos                   10                                                      /*!< CCU8 GCTRL: MSE0 Position               */\r
+#define CCU8_GCTRL_MSE0_Msk                   (0x01UL << CCU8_GCTRL_MSE0_Pos)                         /*!< CCU8 GCTRL: MSE0 Mask                   */\r
+#define CCU8_GCTRL_MSE1_Pos                   11                                                      /*!< CCU8 GCTRL: MSE1 Position               */\r
+#define CCU8_GCTRL_MSE1_Msk                   (0x01UL << CCU8_GCTRL_MSE1_Pos)                         /*!< CCU8 GCTRL: MSE1 Mask                   */\r
+#define CCU8_GCTRL_MSE2_Pos                   12                                                      /*!< CCU8 GCTRL: MSE2 Position               */\r
+#define CCU8_GCTRL_MSE2_Msk                   (0x01UL << CCU8_GCTRL_MSE2_Pos)                         /*!< CCU8 GCTRL: MSE2 Mask                   */\r
+#define CCU8_GCTRL_MSE3_Pos                   13                                                      /*!< CCU8 GCTRL: MSE3 Position               */\r
+#define CCU8_GCTRL_MSE3_Msk                   (0x01UL << CCU8_GCTRL_MSE3_Pos)                         /*!< CCU8 GCTRL: MSE3 Mask                   */\r
+#define CCU8_GCTRL_MSDE_Pos                   14                                                      /*!< CCU8 GCTRL: MSDE Position               */\r
+#define CCU8_GCTRL_MSDE_Msk                   (0x03UL << CCU8_GCTRL_MSDE_Pos)                         /*!< CCU8 GCTRL: MSDE Mask                   */\r
+\r
+/* ---------------------------------  CCU8_GSTAT  --------------------------------- */\r
+#define CCU8_GSTAT_S0I_Pos                    0                                                       /*!< CCU8 GSTAT: S0I Position                */\r
+#define CCU8_GSTAT_S0I_Msk                    (0x01UL << CCU8_GSTAT_S0I_Pos)                          /*!< CCU8 GSTAT: S0I Mask                    */\r
+#define CCU8_GSTAT_S1I_Pos                    1                                                       /*!< CCU8 GSTAT: S1I Position                */\r
+#define CCU8_GSTAT_S1I_Msk                    (0x01UL << CCU8_GSTAT_S1I_Pos)                          /*!< CCU8 GSTAT: S1I Mask                    */\r
+#define CCU8_GSTAT_S2I_Pos                    2                                                       /*!< CCU8 GSTAT: S2I Position                */\r
+#define CCU8_GSTAT_S2I_Msk                    (0x01UL << CCU8_GSTAT_S2I_Pos)                          /*!< CCU8 GSTAT: S2I Mask                    */\r
+#define CCU8_GSTAT_S3I_Pos                    3                                                       /*!< CCU8 GSTAT: S3I Position                */\r
+#define CCU8_GSTAT_S3I_Msk                    (0x01UL << CCU8_GSTAT_S3I_Pos)                          /*!< CCU8 GSTAT: S3I Mask                    */\r
+#define CCU8_GSTAT_PRB_Pos                    8                                                       /*!< CCU8 GSTAT: PRB Position                */\r
+#define CCU8_GSTAT_PRB_Msk                    (0x01UL << CCU8_GSTAT_PRB_Pos)                          /*!< CCU8 GSTAT: PRB Mask                    */\r
+#define CCU8_GSTAT_PCRB_Pos                   10                                                      /*!< CCU8 GSTAT: PCRB Position               */\r
+#define CCU8_GSTAT_PCRB_Msk                   (0x01UL << CCU8_GSTAT_PCRB_Pos)                         /*!< CCU8 GSTAT: PCRB Mask                   */\r
+\r
+/* ---------------------------------  CCU8_GIDLS  --------------------------------- */\r
+#define CCU8_GIDLS_SS0I_Pos                   0                                                       /*!< CCU8 GIDLS: SS0I Position               */\r
+#define CCU8_GIDLS_SS0I_Msk                   (0x01UL << CCU8_GIDLS_SS0I_Pos)                         /*!< CCU8 GIDLS: SS0I Mask                   */\r
+#define CCU8_GIDLS_SS1I_Pos                   1                                                       /*!< CCU8 GIDLS: SS1I Position               */\r
+#define CCU8_GIDLS_SS1I_Msk                   (0x01UL << CCU8_GIDLS_SS1I_Pos)                         /*!< CCU8 GIDLS: SS1I Mask                   */\r
+#define CCU8_GIDLS_SS2I_Pos                   2                                                       /*!< CCU8 GIDLS: SS2I Position               */\r
+#define CCU8_GIDLS_SS2I_Msk                   (0x01UL << CCU8_GIDLS_SS2I_Pos)                         /*!< CCU8 GIDLS: SS2I Mask                   */\r
+#define CCU8_GIDLS_SS3I_Pos                   3                                                       /*!< CCU8 GIDLS: SS3I Position               */\r
+#define CCU8_GIDLS_SS3I_Msk                   (0x01UL << CCU8_GIDLS_SS3I_Pos)                         /*!< CCU8 GIDLS: SS3I Mask                   */\r
+#define CCU8_GIDLS_CPRB_Pos                   8                                                       /*!< CCU8 GIDLS: CPRB Position               */\r
+#define CCU8_GIDLS_CPRB_Msk                   (0x01UL << CCU8_GIDLS_CPRB_Pos)                         /*!< CCU8 GIDLS: CPRB Mask                   */\r
+#define CCU8_GIDLS_PSIC_Pos                   9                                                       /*!< CCU8 GIDLS: PSIC Position               */\r
+#define CCU8_GIDLS_PSIC_Msk                   (0x01UL << CCU8_GIDLS_PSIC_Pos)                         /*!< CCU8 GIDLS: PSIC Mask                   */\r
+#define CCU8_GIDLS_CPCH_Pos                   10                                                      /*!< CCU8 GIDLS: CPCH Position               */\r
+#define CCU8_GIDLS_CPCH_Msk                   (0x01UL << CCU8_GIDLS_CPCH_Pos)                         /*!< CCU8 GIDLS: CPCH Mask                   */\r
+\r
+/* ---------------------------------  CCU8_GIDLC  --------------------------------- */\r
+#define CCU8_GIDLC_CS0I_Pos                   0                                                       /*!< CCU8 GIDLC: CS0I Position               */\r
+#define CCU8_GIDLC_CS0I_Msk                   (0x01UL << CCU8_GIDLC_CS0I_Pos)                         /*!< CCU8 GIDLC: CS0I Mask                   */\r
+#define CCU8_GIDLC_CS1I_Pos                   1                                                       /*!< CCU8 GIDLC: CS1I Position               */\r
+#define CCU8_GIDLC_CS1I_Msk                   (0x01UL << CCU8_GIDLC_CS1I_Pos)                         /*!< CCU8 GIDLC: CS1I Mask                   */\r
+#define CCU8_GIDLC_CS2I_Pos                   2                                                       /*!< CCU8 GIDLC: CS2I Position               */\r
+#define CCU8_GIDLC_CS2I_Msk                   (0x01UL << CCU8_GIDLC_CS2I_Pos)                         /*!< CCU8 GIDLC: CS2I Mask                   */\r
+#define CCU8_GIDLC_CS3I_Pos                   3                                                       /*!< CCU8 GIDLC: CS3I Position               */\r
+#define CCU8_GIDLC_CS3I_Msk                   (0x01UL << CCU8_GIDLC_CS3I_Pos)                         /*!< CCU8 GIDLC: CS3I Mask                   */\r
+#define CCU8_GIDLC_SPRB_Pos                   8                                                       /*!< CCU8 GIDLC: SPRB Position               */\r
+#define CCU8_GIDLC_SPRB_Msk                   (0x01UL << CCU8_GIDLC_SPRB_Pos)                         /*!< CCU8 GIDLC: SPRB Mask                   */\r
+#define CCU8_GIDLC_SPCH_Pos                   10                                                      /*!< CCU8 GIDLC: SPCH Position               */\r
+#define CCU8_GIDLC_SPCH_Msk                   (0x01UL << CCU8_GIDLC_SPCH_Pos)                         /*!< CCU8 GIDLC: SPCH Mask                   */\r
+\r
+/* ----------------------------------  CCU8_GCSS  --------------------------------- */\r
+#define CCU8_GCSS_S0SE_Pos                    0                                                       /*!< CCU8 GCSS: S0SE Position                */\r
+#define CCU8_GCSS_S0SE_Msk                    (0x01UL << CCU8_GCSS_S0SE_Pos)                          /*!< CCU8 GCSS: S0SE Mask                    */\r
+#define CCU8_GCSS_S0DSE_Pos                   1                                                       /*!< CCU8 GCSS: S0DSE Position               */\r
+#define CCU8_GCSS_S0DSE_Msk                   (0x01UL << CCU8_GCSS_S0DSE_Pos)                         /*!< CCU8 GCSS: S0DSE Mask                   */\r
+#define CCU8_GCSS_S0PSE_Pos                   2                                                       /*!< CCU8 GCSS: S0PSE Position               */\r
+#define CCU8_GCSS_S0PSE_Msk                   (0x01UL << CCU8_GCSS_S0PSE_Pos)                         /*!< CCU8 GCSS: S0PSE Mask                   */\r
+#define CCU8_GCSS_S1SE_Pos                    4                                                       /*!< CCU8 GCSS: S1SE Position                */\r
+#define CCU8_GCSS_S1SE_Msk                    (0x01UL << CCU8_GCSS_S1SE_Pos)                          /*!< CCU8 GCSS: S1SE Mask                    */\r
+#define CCU8_GCSS_S1DSE_Pos                   5                                                       /*!< CCU8 GCSS: S1DSE Position               */\r
+#define CCU8_GCSS_S1DSE_Msk                   (0x01UL << CCU8_GCSS_S1DSE_Pos)                         /*!< CCU8 GCSS: S1DSE Mask                   */\r
+#define CCU8_GCSS_S1PSE_Pos                   6                                                       /*!< CCU8 GCSS: S1PSE Position               */\r
+#define CCU8_GCSS_S1PSE_Msk                   (0x01UL << CCU8_GCSS_S1PSE_Pos)                         /*!< CCU8 GCSS: S1PSE Mask                   */\r
+#define CCU8_GCSS_S2SE_Pos                    8                                                       /*!< CCU8 GCSS: S2SE Position                */\r
+#define CCU8_GCSS_S2SE_Msk                    (0x01UL << CCU8_GCSS_S2SE_Pos)                          /*!< CCU8 GCSS: S2SE Mask                    */\r
+#define CCU8_GCSS_S2DSE_Pos                   9                                                       /*!< CCU8 GCSS: S2DSE Position               */\r
+#define CCU8_GCSS_S2DSE_Msk                   (0x01UL << CCU8_GCSS_S2DSE_Pos)                         /*!< CCU8 GCSS: S2DSE Mask                   */\r
+#define CCU8_GCSS_S2PSE_Pos                   10                                                      /*!< CCU8 GCSS: S2PSE Position               */\r
+#define CCU8_GCSS_S2PSE_Msk                   (0x01UL << CCU8_GCSS_S2PSE_Pos)                         /*!< CCU8 GCSS: S2PSE Mask                   */\r
+#define CCU8_GCSS_S3SE_Pos                    12                                                      /*!< CCU8 GCSS: S3SE Position                */\r
+#define CCU8_GCSS_S3SE_Msk                    (0x01UL << CCU8_GCSS_S3SE_Pos)                          /*!< CCU8 GCSS: S3SE Mask                    */\r
+#define CCU8_GCSS_S3DSE_Pos                   13                                                      /*!< CCU8 GCSS: S3DSE Position               */\r
+#define CCU8_GCSS_S3DSE_Msk                   (0x01UL << CCU8_GCSS_S3DSE_Pos)                         /*!< CCU8 GCSS: S3DSE Mask                   */\r
+#define CCU8_GCSS_S3PSE_Pos                   14                                                      /*!< CCU8 GCSS: S3PSE Position               */\r
+#define CCU8_GCSS_S3PSE_Msk                   (0x01UL << CCU8_GCSS_S3PSE_Pos)                         /*!< CCU8 GCSS: S3PSE Mask                   */\r
+#define CCU8_GCSS_S0ST1S_Pos                  16                                                      /*!< CCU8 GCSS: S0ST1S Position              */\r
+#define CCU8_GCSS_S0ST1S_Msk                  (0x01UL << CCU8_GCSS_S0ST1S_Pos)                        /*!< CCU8 GCSS: S0ST1S Mask                  */\r
+#define CCU8_GCSS_S1ST1S_Pos                  17                                                      /*!< CCU8 GCSS: S1ST1S Position              */\r
+#define CCU8_GCSS_S1ST1S_Msk                  (0x01UL << CCU8_GCSS_S1ST1S_Pos)                        /*!< CCU8 GCSS: S1ST1S Mask                  */\r
+#define CCU8_GCSS_S2ST1S_Pos                  18                                                      /*!< CCU8 GCSS: S2ST1S Position              */\r
+#define CCU8_GCSS_S2ST1S_Msk                  (0x01UL << CCU8_GCSS_S2ST1S_Pos)                        /*!< CCU8 GCSS: S2ST1S Mask                  */\r
+#define CCU8_GCSS_S3ST1S_Pos                  19                                                      /*!< CCU8 GCSS: S3ST1S Position              */\r
+#define CCU8_GCSS_S3ST1S_Msk                  (0x01UL << CCU8_GCSS_S3ST1S_Pos)                        /*!< CCU8 GCSS: S3ST1S Mask                  */\r
+#define CCU8_GCSS_S0ST2S_Pos                  20                                                      /*!< CCU8 GCSS: S0ST2S Position              */\r
+#define CCU8_GCSS_S0ST2S_Msk                  (0x01UL << CCU8_GCSS_S0ST2S_Pos)                        /*!< CCU8 GCSS: S0ST2S Mask                  */\r
+#define CCU8_GCSS_S1ST2S_Pos                  21                                                      /*!< CCU8 GCSS: S1ST2S Position              */\r
+#define CCU8_GCSS_S1ST2S_Msk                  (0x01UL << CCU8_GCSS_S1ST2S_Pos)                        /*!< CCU8 GCSS: S1ST2S Mask                  */\r
+#define CCU8_GCSS_S2ST2S_Pos                  22                                                      /*!< CCU8 GCSS: S2ST2S Position              */\r
+#define CCU8_GCSS_S2ST2S_Msk                  (0x01UL << CCU8_GCSS_S2ST2S_Pos)                        /*!< CCU8 GCSS: S2ST2S Mask                  */\r
+#define CCU8_GCSS_S3ST2S_Pos                  23                                                      /*!< CCU8 GCSS: S3ST2S Position              */\r
+#define CCU8_GCSS_S3ST2S_Msk                  (0x01UL << CCU8_GCSS_S3ST2S_Pos)                        /*!< CCU8 GCSS: S3ST2S Mask                  */\r
+\r
+/* ----------------------------------  CCU8_GCSC  --------------------------------- */\r
+#define CCU8_GCSC_S0SC_Pos                    0                                                       /*!< CCU8 GCSC: S0SC Position                */\r
+#define CCU8_GCSC_S0SC_Msk                    (0x01UL << CCU8_GCSC_S0SC_Pos)                          /*!< CCU8 GCSC: S0SC Mask                    */\r
+#define CCU8_GCSC_S0DSC_Pos                   1                                                       /*!< CCU8 GCSC: S0DSC Position               */\r
+#define CCU8_GCSC_S0DSC_Msk                   (0x01UL << CCU8_GCSC_S0DSC_Pos)                         /*!< CCU8 GCSC: S0DSC Mask                   */\r
+#define CCU8_GCSC_S0PSC_Pos                   2                                                       /*!< CCU8 GCSC: S0PSC Position               */\r
+#define CCU8_GCSC_S0PSC_Msk                   (0x01UL << CCU8_GCSC_S0PSC_Pos)                         /*!< CCU8 GCSC: S0PSC Mask                   */\r
+#define CCU8_GCSC_S1SC_Pos                    4                                                       /*!< CCU8 GCSC: S1SC Position                */\r
+#define CCU8_GCSC_S1SC_Msk                    (0x01UL << CCU8_GCSC_S1SC_Pos)                          /*!< CCU8 GCSC: S1SC Mask                    */\r
+#define CCU8_GCSC_S1DSC_Pos                   5                                                       /*!< CCU8 GCSC: S1DSC Position               */\r
+#define CCU8_GCSC_S1DSC_Msk                   (0x01UL << CCU8_GCSC_S1DSC_Pos)                         /*!< CCU8 GCSC: S1DSC Mask                   */\r
+#define CCU8_GCSC_S1PSC_Pos                   6                                                       /*!< CCU8 GCSC: S1PSC Position               */\r
+#define CCU8_GCSC_S1PSC_Msk                   (0x01UL << CCU8_GCSC_S1PSC_Pos)                         /*!< CCU8 GCSC: S1PSC Mask                   */\r
+#define CCU8_GCSC_S2SC_Pos                    8                                                       /*!< CCU8 GCSC: S2SC Position                */\r
+#define CCU8_GCSC_S2SC_Msk                    (0x01UL << CCU8_GCSC_S2SC_Pos)                          /*!< CCU8 GCSC: S2SC Mask                    */\r
+#define CCU8_GCSC_S2DSC_Pos                   9                                                       /*!< CCU8 GCSC: S2DSC Position               */\r
+#define CCU8_GCSC_S2DSC_Msk                   (0x01UL << CCU8_GCSC_S2DSC_Pos)                         /*!< CCU8 GCSC: S2DSC Mask                   */\r
+#define CCU8_GCSC_S2PSC_Pos                   10                                                      /*!< CCU8 GCSC: S2PSC Position               */\r
+#define CCU8_GCSC_S2PSC_Msk                   (0x01UL << CCU8_GCSC_S2PSC_Pos)                         /*!< CCU8 GCSC: S2PSC Mask                   */\r
+#define CCU8_GCSC_S3SC_Pos                    12                                                      /*!< CCU8 GCSC: S3SC Position                */\r
+#define CCU8_GCSC_S3SC_Msk                    (0x01UL << CCU8_GCSC_S3SC_Pos)                          /*!< CCU8 GCSC: S3SC Mask                    */\r
+#define CCU8_GCSC_S3DSC_Pos                   13                                                      /*!< CCU8 GCSC: S3DSC Position               */\r
+#define CCU8_GCSC_S3DSC_Msk                   (0x01UL << CCU8_GCSC_S3DSC_Pos)                         /*!< CCU8 GCSC: S3DSC Mask                   */\r
+#define CCU8_GCSC_S3PSC_Pos                   14                                                      /*!< CCU8 GCSC: S3PSC Position               */\r
+#define CCU8_GCSC_S3PSC_Msk                   (0x01UL << CCU8_GCSC_S3PSC_Pos)                         /*!< CCU8 GCSC: S3PSC Mask                   */\r
+#define CCU8_GCSC_S0ST1C_Pos                  16                                                      /*!< CCU8 GCSC: S0ST1C Position              */\r
+#define CCU8_GCSC_S0ST1C_Msk                  (0x01UL << CCU8_GCSC_S0ST1C_Pos)                        /*!< CCU8 GCSC: S0ST1C Mask                  */\r
+#define CCU8_GCSC_S1ST1C_Pos                  17                                                      /*!< CCU8 GCSC: S1ST1C Position              */\r
+#define CCU8_GCSC_S1ST1C_Msk                  (0x01UL << CCU8_GCSC_S1ST1C_Pos)                        /*!< CCU8 GCSC: S1ST1C Mask                  */\r
+#define CCU8_GCSC_S2ST1C_Pos                  18                                                      /*!< CCU8 GCSC: S2ST1C Position              */\r
+#define CCU8_GCSC_S2ST1C_Msk                  (0x01UL << CCU8_GCSC_S2ST1C_Pos)                        /*!< CCU8 GCSC: S2ST1C Mask                  */\r
+#define CCU8_GCSC_S3ST1C_Pos                  19                                                      /*!< CCU8 GCSC: S3ST1C Position              */\r
+#define CCU8_GCSC_S3ST1C_Msk                  (0x01UL << CCU8_GCSC_S3ST1C_Pos)                        /*!< CCU8 GCSC: S3ST1C Mask                  */\r
+#define CCU8_GCSC_S0ST2C_Pos                  20                                                      /*!< CCU8 GCSC: S0ST2C Position              */\r
+#define CCU8_GCSC_S0ST2C_Msk                  (0x01UL << CCU8_GCSC_S0ST2C_Pos)                        /*!< CCU8 GCSC: S0ST2C Mask                  */\r
+#define CCU8_GCSC_S1ST2C_Pos                  21                                                      /*!< CCU8 GCSC: S1ST2C Position              */\r
+#define CCU8_GCSC_S1ST2C_Msk                  (0x01UL << CCU8_GCSC_S1ST2C_Pos)                        /*!< CCU8 GCSC: S1ST2C Mask                  */\r
+#define CCU8_GCSC_S2ST2C_Pos                  22                                                      /*!< CCU8 GCSC: S2ST2C Position              */\r
+#define CCU8_GCSC_S2ST2C_Msk                  (0x01UL << CCU8_GCSC_S2ST2C_Pos)                        /*!< CCU8 GCSC: S2ST2C Mask                  */\r
+#define CCU8_GCSC_S3ST2C_Pos                  23                                                      /*!< CCU8 GCSC: S3ST2C Position              */\r
+#define CCU8_GCSC_S3ST2C_Msk                  (0x01UL << CCU8_GCSC_S3ST2C_Pos)                        /*!< CCU8 GCSC: S3ST2C Mask                  */\r
+\r
+/* ----------------------------------  CCU8_GCST  --------------------------------- */\r
+#define CCU8_GCST_S0SS_Pos                    0                                                       /*!< CCU8 GCST: S0SS Position                */\r
+#define CCU8_GCST_S0SS_Msk                    (0x01UL << CCU8_GCST_S0SS_Pos)                          /*!< CCU8 GCST: S0SS Mask                    */\r
+#define CCU8_GCST_S0DSS_Pos                   1                                                       /*!< CCU8 GCST: S0DSS Position               */\r
+#define CCU8_GCST_S0DSS_Msk                   (0x01UL << CCU8_GCST_S0DSS_Pos)                         /*!< CCU8 GCST: S0DSS Mask                   */\r
+#define CCU8_GCST_S0PSS_Pos                   2                                                       /*!< CCU8 GCST: S0PSS Position               */\r
+#define CCU8_GCST_S0PSS_Msk                   (0x01UL << CCU8_GCST_S0PSS_Pos)                         /*!< CCU8 GCST: S0PSS Mask                   */\r
+#define CCU8_GCST_S1SS_Pos                    4                                                       /*!< CCU8 GCST: S1SS Position                */\r
+#define CCU8_GCST_S1SS_Msk                    (0x01UL << CCU8_GCST_S1SS_Pos)                          /*!< CCU8 GCST: S1SS Mask                    */\r
+#define CCU8_GCST_S1DSS_Pos                   5                                                       /*!< CCU8 GCST: S1DSS Position               */\r
+#define CCU8_GCST_S1DSS_Msk                   (0x01UL << CCU8_GCST_S1DSS_Pos)                         /*!< CCU8 GCST: S1DSS Mask                   */\r
+#define CCU8_GCST_S1PSS_Pos                   6                                                       /*!< CCU8 GCST: S1PSS Position               */\r
+#define CCU8_GCST_S1PSS_Msk                   (0x01UL << CCU8_GCST_S1PSS_Pos)                         /*!< CCU8 GCST: S1PSS Mask                   */\r
+#define CCU8_GCST_S2SS_Pos                    8                                                       /*!< CCU8 GCST: S2SS Position                */\r
+#define CCU8_GCST_S2SS_Msk                    (0x01UL << CCU8_GCST_S2SS_Pos)                          /*!< CCU8 GCST: S2SS Mask                    */\r
+#define CCU8_GCST_S2DSS_Pos                   9                                                       /*!< CCU8 GCST: S2DSS Position               */\r
+#define CCU8_GCST_S2DSS_Msk                   (0x01UL << CCU8_GCST_S2DSS_Pos)                         /*!< CCU8 GCST: S2DSS Mask                   */\r
+#define CCU8_GCST_S2PSS_Pos                   10                                                      /*!< CCU8 GCST: S2PSS Position               */\r
+#define CCU8_GCST_S2PSS_Msk                   (0x01UL << CCU8_GCST_S2PSS_Pos)                         /*!< CCU8 GCST: S2PSS Mask                   */\r
+#define CCU8_GCST_S3SS_Pos                    12                                                      /*!< CCU8 GCST: S3SS Position                */\r
+#define CCU8_GCST_S3SS_Msk                    (0x01UL << CCU8_GCST_S3SS_Pos)                          /*!< CCU8 GCST: S3SS Mask                    */\r
+#define CCU8_GCST_S3DSS_Pos                   13                                                      /*!< CCU8 GCST: S3DSS Position               */\r
+#define CCU8_GCST_S3DSS_Msk                   (0x01UL << CCU8_GCST_S3DSS_Pos)                         /*!< CCU8 GCST: S3DSS Mask                   */\r
+#define CCU8_GCST_S3PSS_Pos                   14                                                      /*!< CCU8 GCST: S3PSS Position               */\r
+#define CCU8_GCST_S3PSS_Msk                   (0x01UL << CCU8_GCST_S3PSS_Pos)                         /*!< CCU8 GCST: S3PSS Mask                   */\r
+#define CCU8_GCST_CC80ST1_Pos                 16                                                      /*!< CCU8 GCST: CC80ST1 Position             */\r
+#define CCU8_GCST_CC80ST1_Msk                 (0x01UL << CCU8_GCST_CC80ST1_Pos)                       /*!< CCU8 GCST: CC80ST1 Mask                 */\r
+#define CCU8_GCST_CC81ST1_Pos                 17                                                      /*!< CCU8 GCST: CC81ST1 Position             */\r
+#define CCU8_GCST_CC81ST1_Msk                 (0x01UL << CCU8_GCST_CC81ST1_Pos)                       /*!< CCU8 GCST: CC81ST1 Mask                 */\r
+#define CCU8_GCST_CC82ST1_Pos                 18                                                      /*!< CCU8 GCST: CC82ST1 Position             */\r
+#define CCU8_GCST_CC82ST1_Msk                 (0x01UL << CCU8_GCST_CC82ST1_Pos)                       /*!< CCU8 GCST: CC82ST1 Mask                 */\r
+#define CCU8_GCST_CC83ST1_Pos                 19                                                      /*!< CCU8 GCST: CC83ST1 Position             */\r
+#define CCU8_GCST_CC83ST1_Msk                 (0x01UL << CCU8_GCST_CC83ST1_Pos)                       /*!< CCU8 GCST: CC83ST1 Mask                 */\r
+#define CCU8_GCST_CC80ST2_Pos                 20                                                      /*!< CCU8 GCST: CC80ST2 Position             */\r
+#define CCU8_GCST_CC80ST2_Msk                 (0x01UL << CCU8_GCST_CC80ST2_Pos)                       /*!< CCU8 GCST: CC80ST2 Mask                 */\r
+#define CCU8_GCST_CC81ST2_Pos                 21                                                      /*!< CCU8 GCST: CC81ST2 Position             */\r
+#define CCU8_GCST_CC81ST2_Msk                 (0x01UL << CCU8_GCST_CC81ST2_Pos)                       /*!< CCU8 GCST: CC81ST2 Mask                 */\r
+#define CCU8_GCST_CC82ST2_Pos                 22                                                      /*!< CCU8 GCST: CC82ST2 Position             */\r
+#define CCU8_GCST_CC82ST2_Msk                 (0x01UL << CCU8_GCST_CC82ST2_Pos)                       /*!< CCU8 GCST: CC82ST2 Mask                 */\r
+#define CCU8_GCST_CC83ST2_Pos                 23                                                      /*!< CCU8 GCST: CC83ST2 Position             */\r
+#define CCU8_GCST_CC83ST2_Msk                 (0x01UL << CCU8_GCST_CC83ST2_Pos)                       /*!< CCU8 GCST: CC83ST2 Mask                 */\r
+\r
+/* ---------------------------------  CCU8_GPCHK  --------------------------------- */\r
+#define CCU8_GPCHK_PASE_Pos                   0                                                       /*!< CCU8 GPCHK: PASE Position               */\r
+#define CCU8_GPCHK_PASE_Msk                   (0x01UL << CCU8_GPCHK_PASE_Pos)                         /*!< CCU8 GPCHK: PASE Mask                   */\r
+#define CCU8_GPCHK_PACS_Pos                   1                                                       /*!< CCU8 GPCHK: PACS Position               */\r
+#define CCU8_GPCHK_PACS_Msk                   (0x03UL << CCU8_GPCHK_PACS_Pos)                         /*!< CCU8 GPCHK: PACS Mask                   */\r
+#define CCU8_GPCHK_PISEL_Pos                  3                                                       /*!< CCU8 GPCHK: PISEL Position              */\r
+#define CCU8_GPCHK_PISEL_Msk                  (0x03UL << CCU8_GPCHK_PISEL_Pos)                        /*!< CCU8 GPCHK: PISEL Mask                  */\r
+#define CCU8_GPCHK_PCDS_Pos                   5                                                       /*!< CCU8 GPCHK: PCDS Position               */\r
+#define CCU8_GPCHK_PCDS_Msk                   (0x03UL << CCU8_GPCHK_PCDS_Pos)                         /*!< CCU8 GPCHK: PCDS Mask                   */\r
+#define CCU8_GPCHK_PCTS_Pos                   7                                                       /*!< CCU8 GPCHK: PCTS Position               */\r
+#define CCU8_GPCHK_PCTS_Msk                   (0x01UL << CCU8_GPCHK_PCTS_Pos)                         /*!< CCU8 GPCHK: PCTS Mask                   */\r
+#define CCU8_GPCHK_PCST_Pos                   15                                                      /*!< CCU8 GPCHK: PCST Position               */\r
+#define CCU8_GPCHK_PCST_Msk                   (0x01UL << CCU8_GPCHK_PCST_Pos)                         /*!< CCU8 GPCHK: PCST Mask                   */\r
+#define CCU8_GPCHK_PCSEL0_Pos                 16                                                      /*!< CCU8 GPCHK: PCSEL0 Position             */\r
+#define CCU8_GPCHK_PCSEL0_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL0_Pos)                       /*!< CCU8 GPCHK: PCSEL0 Mask                 */\r
+#define CCU8_GPCHK_PCSEL1_Pos                 20                                                      /*!< CCU8 GPCHK: PCSEL1 Position             */\r
+#define CCU8_GPCHK_PCSEL1_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL1_Pos)                       /*!< CCU8 GPCHK: PCSEL1 Mask                 */\r
+#define CCU8_GPCHK_PCSEL2_Pos                 24                                                      /*!< CCU8 GPCHK: PCSEL2 Position             */\r
+#define CCU8_GPCHK_PCSEL2_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL2_Pos)                       /*!< CCU8 GPCHK: PCSEL2 Mask                 */\r
+#define CCU8_GPCHK_PCSEL3_Pos                 28                                                      /*!< CCU8 GPCHK: PCSEL3 Position             */\r
+#define CCU8_GPCHK_PCSEL3_Msk                 (0x0fUL << CCU8_GPCHK_PCSEL3_Pos)                       /*!< CCU8 GPCHK: PCSEL3 Mask                 */\r
+\r
+/* ----------------------------------  CCU8_ECRD  --------------------------------- */\r
+#define CCU8_ECRD_CAPV_Pos                    0                                                       /*!< CCU8 ECRD: CAPV Position                */\r
+#define CCU8_ECRD_CAPV_Msk                    (0x0000ffffUL << CCU8_ECRD_CAPV_Pos)                    /*!< CCU8 ECRD: CAPV Mask                    */\r
+#define CCU8_ECRD_FPCV_Pos                    16                                                      /*!< CCU8 ECRD: FPCV Position                */\r
+#define CCU8_ECRD_FPCV_Msk                    (0x0fUL << CCU8_ECRD_FPCV_Pos)                          /*!< CCU8 ECRD: FPCV Mask                    */\r
+#define CCU8_ECRD_SPTR_Pos                    20                                                      /*!< CCU8 ECRD: SPTR Position                */\r
+#define CCU8_ECRD_SPTR_Msk                    (0x03UL << CCU8_ECRD_SPTR_Pos)                          /*!< CCU8 ECRD: SPTR Mask                    */\r
+#define CCU8_ECRD_VPTR_Pos                    22                                                      /*!< CCU8 ECRD: VPTR Position                */\r
+#define CCU8_ECRD_VPTR_Msk                    (0x03UL << CCU8_ECRD_VPTR_Pos)                          /*!< CCU8 ECRD: VPTR Mask                    */\r
+#define CCU8_ECRD_FFL_Pos                     24                                                      /*!< CCU8 ECRD: FFL Position                 */\r
+#define CCU8_ECRD_FFL_Msk                     (0x01UL << CCU8_ECRD_FFL_Pos)                           /*!< CCU8 ECRD: FFL Mask                     */\r
+\r
+/* ----------------------------------  CCU8_MIDR  --------------------------------- */\r
+#define CCU8_MIDR_MODR_Pos                    0                                                       /*!< CCU8 MIDR: MODR Position                */\r
+#define CCU8_MIDR_MODR_Msk                    (0x000000ffUL << CCU8_MIDR_MODR_Pos)                    /*!< CCU8 MIDR: MODR Mask                    */\r
+#define CCU8_MIDR_MODT_Pos                    8                                                       /*!< CCU8 MIDR: MODT Position                */\r
+#define CCU8_MIDR_MODT_Msk                    (0x000000ffUL << CCU8_MIDR_MODT_Pos)                    /*!< CCU8 MIDR: MODT Mask                    */\r
+#define CCU8_MIDR_MODN_Pos                    16                                                      /*!< CCU8 MIDR: MODN Position                */\r
+#define CCU8_MIDR_MODN_Msk                    (0x0000ffffUL << CCU8_MIDR_MODN_Pos)                    /*!< CCU8 MIDR: MODN Mask                    */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================        Group 'CCU8_CC8' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------  CCU8_CC8_INS  -------------------------------- */\r
+#define CCU8_CC8_INS_EV0IS_Pos                0                                                       /*!< CCU8_CC8 INS: EV0IS Position            */\r
+#define CCU8_CC8_INS_EV0IS_Msk                (0x0fUL << CCU8_CC8_INS_EV0IS_Pos)                      /*!< CCU8_CC8 INS: EV0IS Mask                */\r
+#define CCU8_CC8_INS_EV1IS_Pos                4                                                       /*!< CCU8_CC8 INS: EV1IS Position            */\r
+#define CCU8_CC8_INS_EV1IS_Msk                (0x0fUL << CCU8_CC8_INS_EV1IS_Pos)                      /*!< CCU8_CC8 INS: EV1IS Mask                */\r
+#define CCU8_CC8_INS_EV2IS_Pos                8                                                       /*!< CCU8_CC8 INS: EV2IS Position            */\r
+#define CCU8_CC8_INS_EV2IS_Msk                (0x0fUL << CCU8_CC8_INS_EV2IS_Pos)                      /*!< CCU8_CC8 INS: EV2IS Mask                */\r
+#define CCU8_CC8_INS_EV0EM_Pos                16                                                      /*!< CCU8_CC8 INS: EV0EM Position            */\r
+#define CCU8_CC8_INS_EV0EM_Msk                (0x03UL << CCU8_CC8_INS_EV0EM_Pos)                      /*!< CCU8_CC8 INS: EV0EM Mask                */\r
+#define CCU8_CC8_INS_EV1EM_Pos                18                                                      /*!< CCU8_CC8 INS: EV1EM Position            */\r
+#define CCU8_CC8_INS_EV1EM_Msk                (0x03UL << CCU8_CC8_INS_EV1EM_Pos)                      /*!< CCU8_CC8 INS: EV1EM Mask                */\r
+#define CCU8_CC8_INS_EV2EM_Pos                20                                                      /*!< CCU8_CC8 INS: EV2EM Position            */\r
+#define CCU8_CC8_INS_EV2EM_Msk                (0x03UL << CCU8_CC8_INS_EV2EM_Pos)                      /*!< CCU8_CC8 INS: EV2EM Mask                */\r
+#define CCU8_CC8_INS_EV0LM_Pos                22                                                      /*!< CCU8_CC8 INS: EV0LM Position            */\r
+#define CCU8_CC8_INS_EV0LM_Msk                (0x01UL << CCU8_CC8_INS_EV0LM_Pos)                      /*!< CCU8_CC8 INS: EV0LM Mask                */\r
+#define CCU8_CC8_INS_EV1LM_Pos                23                                                      /*!< CCU8_CC8 INS: EV1LM Position            */\r
+#define CCU8_CC8_INS_EV1LM_Msk                (0x01UL << CCU8_CC8_INS_EV1LM_Pos)                      /*!< CCU8_CC8 INS: EV1LM Mask                */\r
+#define CCU8_CC8_INS_EV2LM_Pos                24                                                      /*!< CCU8_CC8 INS: EV2LM Position            */\r
+#define CCU8_CC8_INS_EV2LM_Msk                (0x01UL << CCU8_CC8_INS_EV2LM_Pos)                      /*!< CCU8_CC8 INS: EV2LM Mask                */\r
+#define CCU8_CC8_INS_LPF0M_Pos                25                                                      /*!< CCU8_CC8 INS: LPF0M Position            */\r
+#define CCU8_CC8_INS_LPF0M_Msk                (0x03UL << CCU8_CC8_INS_LPF0M_Pos)                      /*!< CCU8_CC8 INS: LPF0M Mask                */\r
+#define CCU8_CC8_INS_LPF1M_Pos                27                                                      /*!< CCU8_CC8 INS: LPF1M Position            */\r
+#define CCU8_CC8_INS_LPF1M_Msk                (0x03UL << CCU8_CC8_INS_LPF1M_Pos)                      /*!< CCU8_CC8 INS: LPF1M Mask                */\r
+#define CCU8_CC8_INS_LPF2M_Pos                29                                                      /*!< CCU8_CC8 INS: LPF2M Position            */\r
+#define CCU8_CC8_INS_LPF2M_Msk                (0x03UL << CCU8_CC8_INS_LPF2M_Pos)                      /*!< CCU8_CC8 INS: LPF2M Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_CMC  -------------------------------- */\r
+#define CCU8_CC8_CMC_STRTS_Pos                0                                                       /*!< CCU8_CC8 CMC: STRTS Position            */\r
+#define CCU8_CC8_CMC_STRTS_Msk                (0x03UL << CCU8_CC8_CMC_STRTS_Pos)                      /*!< CCU8_CC8 CMC: STRTS Mask                */\r
+#define CCU8_CC8_CMC_ENDS_Pos                 2                                                       /*!< CCU8_CC8 CMC: ENDS Position             */\r
+#define CCU8_CC8_CMC_ENDS_Msk                 (0x03UL << CCU8_CC8_CMC_ENDS_Pos)                       /*!< CCU8_CC8 CMC: ENDS Mask                 */\r
+#define CCU8_CC8_CMC_CAP0S_Pos                4                                                       /*!< CCU8_CC8 CMC: CAP0S Position            */\r
+#define CCU8_CC8_CMC_CAP0S_Msk                (0x03UL << CCU8_CC8_CMC_CAP0S_Pos)                      /*!< CCU8_CC8 CMC: CAP0S Mask                */\r
+#define CCU8_CC8_CMC_CAP1S_Pos                6                                                       /*!< CCU8_CC8 CMC: CAP1S Position            */\r
+#define CCU8_CC8_CMC_CAP1S_Msk                (0x03UL << CCU8_CC8_CMC_CAP1S_Pos)                      /*!< CCU8_CC8 CMC: CAP1S Mask                */\r
+#define CCU8_CC8_CMC_GATES_Pos                8                                                       /*!< CCU8_CC8 CMC: GATES Position            */\r
+#define CCU8_CC8_CMC_GATES_Msk                (0x03UL << CCU8_CC8_CMC_GATES_Pos)                      /*!< CCU8_CC8 CMC: GATES Mask                */\r
+#define CCU8_CC8_CMC_UDS_Pos                  10                                                      /*!< CCU8_CC8 CMC: UDS Position              */\r
+#define CCU8_CC8_CMC_UDS_Msk                  (0x03UL << CCU8_CC8_CMC_UDS_Pos)                        /*!< CCU8_CC8 CMC: UDS Mask                  */\r
+#define CCU8_CC8_CMC_LDS_Pos                  12                                                      /*!< CCU8_CC8 CMC: LDS Position              */\r
+#define CCU8_CC8_CMC_LDS_Msk                  (0x03UL << CCU8_CC8_CMC_LDS_Pos)                        /*!< CCU8_CC8 CMC: LDS Mask                  */\r
+#define CCU8_CC8_CMC_CNTS_Pos                 14                                                      /*!< CCU8_CC8 CMC: CNTS Position             */\r
+#define CCU8_CC8_CMC_CNTS_Msk                 (0x03UL << CCU8_CC8_CMC_CNTS_Pos)                       /*!< CCU8_CC8 CMC: CNTS Mask                 */\r
+#define CCU8_CC8_CMC_OFS_Pos                  16                                                      /*!< CCU8_CC8 CMC: OFS Position              */\r
+#define CCU8_CC8_CMC_OFS_Msk                  (0x01UL << CCU8_CC8_CMC_OFS_Pos)                        /*!< CCU8_CC8 CMC: OFS Mask                  */\r
+#define CCU8_CC8_CMC_TS_Pos                   17                                                      /*!< CCU8_CC8 CMC: TS Position               */\r
+#define CCU8_CC8_CMC_TS_Msk                   (0x01UL << CCU8_CC8_CMC_TS_Pos)                         /*!< CCU8_CC8 CMC: TS Mask                   */\r
+#define CCU8_CC8_CMC_MOS_Pos                  18                                                      /*!< CCU8_CC8 CMC: MOS Position              */\r
+#define CCU8_CC8_CMC_MOS_Msk                  (0x03UL << CCU8_CC8_CMC_MOS_Pos)                        /*!< CCU8_CC8 CMC: MOS Mask                  */\r
+#define CCU8_CC8_CMC_TCE_Pos                  20                                                      /*!< CCU8_CC8 CMC: TCE Position              */\r
+#define CCU8_CC8_CMC_TCE_Msk                  (0x01UL << CCU8_CC8_CMC_TCE_Pos)                        /*!< CCU8_CC8 CMC: TCE Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_TCST  ------------------------------- */\r
+#define CCU8_CC8_TCST_TRB_Pos                 0                                                       /*!< CCU8_CC8 TCST: TRB Position             */\r
+#define CCU8_CC8_TCST_TRB_Msk                 (0x01UL << CCU8_CC8_TCST_TRB_Pos)                       /*!< CCU8_CC8 TCST: TRB Mask                 */\r
+#define CCU8_CC8_TCST_CDIR_Pos                1                                                       /*!< CCU8_CC8 TCST: CDIR Position            */\r
+#define CCU8_CC8_TCST_CDIR_Msk                (0x01UL << CCU8_CC8_TCST_CDIR_Pos)                      /*!< CCU8_CC8 TCST: CDIR Mask                */\r
+#define CCU8_CC8_TCST_DTR1_Pos                3                                                       /*!< CCU8_CC8 TCST: DTR1 Position            */\r
+#define CCU8_CC8_TCST_DTR1_Msk                (0x01UL << CCU8_CC8_TCST_DTR1_Pos)                      /*!< CCU8_CC8 TCST: DTR1 Mask                */\r
+#define CCU8_CC8_TCST_DTR2_Pos                4                                                       /*!< CCU8_CC8 TCST: DTR2 Position            */\r
+#define CCU8_CC8_TCST_DTR2_Msk                (0x01UL << CCU8_CC8_TCST_DTR2_Pos)                      /*!< CCU8_CC8 TCST: DTR2 Mask                */\r
+\r
+/* -------------------------------  CCU8_CC8_TCSET  ------------------------------- */\r
+#define CCU8_CC8_TCSET_TRBS_Pos               0                                                       /*!< CCU8_CC8 TCSET: TRBS Position           */\r
+#define CCU8_CC8_TCSET_TRBS_Msk               (0x01UL << CCU8_CC8_TCSET_TRBS_Pos)                     /*!< CCU8_CC8 TCSET: TRBS Mask               */\r
+\r
+/* -------------------------------  CCU8_CC8_TCCLR  ------------------------------- */\r
+#define CCU8_CC8_TCCLR_TRBC_Pos               0                                                       /*!< CCU8_CC8 TCCLR: TRBC Position           */\r
+#define CCU8_CC8_TCCLR_TRBC_Msk               (0x01UL << CCU8_CC8_TCCLR_TRBC_Pos)                     /*!< CCU8_CC8 TCCLR: TRBC Mask               */\r
+#define CCU8_CC8_TCCLR_TCC_Pos                1                                                       /*!< CCU8_CC8 TCCLR: TCC Position            */\r
+#define CCU8_CC8_TCCLR_TCC_Msk                (0x01UL << CCU8_CC8_TCCLR_TCC_Pos)                      /*!< CCU8_CC8 TCCLR: TCC Mask                */\r
+#define CCU8_CC8_TCCLR_DITC_Pos               2                                                       /*!< CCU8_CC8 TCCLR: DITC Position           */\r
+#define CCU8_CC8_TCCLR_DITC_Msk               (0x01UL << CCU8_CC8_TCCLR_DITC_Pos)                     /*!< CCU8_CC8 TCCLR: DITC Mask               */\r
+#define CCU8_CC8_TCCLR_DTC1C_Pos              3                                                       /*!< CCU8_CC8 TCCLR: DTC1C Position          */\r
+#define CCU8_CC8_TCCLR_DTC1C_Msk              (0x01UL << CCU8_CC8_TCCLR_DTC1C_Pos)                    /*!< CCU8_CC8 TCCLR: DTC1C Mask              */\r
+#define CCU8_CC8_TCCLR_DTC2C_Pos              4                                                       /*!< CCU8_CC8 TCCLR: DTC2C Position          */\r
+#define CCU8_CC8_TCCLR_DTC2C_Msk              (0x01UL << CCU8_CC8_TCCLR_DTC2C_Pos)                    /*!< CCU8_CC8 TCCLR: DTC2C Mask              */\r
+\r
+/* ---------------------------------  CCU8_CC8_TC  -------------------------------- */\r
+#define CCU8_CC8_TC_TCM_Pos                   0                                                       /*!< CCU8_CC8 TC: TCM Position               */\r
+#define CCU8_CC8_TC_TCM_Msk                   (0x01UL << CCU8_CC8_TC_TCM_Pos)                         /*!< CCU8_CC8 TC: TCM Mask                   */\r
+#define CCU8_CC8_TC_TSSM_Pos                  1                                                       /*!< CCU8_CC8 TC: TSSM Position              */\r
+#define CCU8_CC8_TC_TSSM_Msk                  (0x01UL << CCU8_CC8_TC_TSSM_Pos)                        /*!< CCU8_CC8 TC: TSSM Mask                  */\r
+#define CCU8_CC8_TC_CLST_Pos                  2                                                       /*!< CCU8_CC8 TC: CLST Position              */\r
+#define CCU8_CC8_TC_CLST_Msk                  (0x01UL << CCU8_CC8_TC_CLST_Pos)                        /*!< CCU8_CC8 TC: CLST Mask                  */\r
+#define CCU8_CC8_TC_CMOD_Pos                  3                                                       /*!< CCU8_CC8 TC: CMOD Position              */\r
+#define CCU8_CC8_TC_CMOD_Msk                  (0x01UL << CCU8_CC8_TC_CMOD_Pos)                        /*!< CCU8_CC8 TC: CMOD Mask                  */\r
+#define CCU8_CC8_TC_ECM_Pos                   4                                                       /*!< CCU8_CC8 TC: ECM Position               */\r
+#define CCU8_CC8_TC_ECM_Msk                   (0x01UL << CCU8_CC8_TC_ECM_Pos)                         /*!< CCU8_CC8 TC: ECM Mask                   */\r
+#define CCU8_CC8_TC_CAPC_Pos                  5                                                       /*!< CCU8_CC8 TC: CAPC Position              */\r
+#define CCU8_CC8_TC_CAPC_Msk                  (0x03UL << CCU8_CC8_TC_CAPC_Pos)                        /*!< CCU8_CC8 TC: CAPC Mask                  */\r
+#define CCU8_CC8_TC_TLS_Pos                   7                                                       /*!< CCU8_CC8 TC: TLS Position               */\r
+#define CCU8_CC8_TC_TLS_Msk                   (0x01UL << CCU8_CC8_TC_TLS_Pos)                         /*!< CCU8_CC8 TC: TLS Mask                   */\r
+#define CCU8_CC8_TC_ENDM_Pos                  8                                                       /*!< CCU8_CC8 TC: ENDM Position              */\r
+#define CCU8_CC8_TC_ENDM_Msk                  (0x03UL << CCU8_CC8_TC_ENDM_Pos)                        /*!< CCU8_CC8 TC: ENDM Mask                  */\r
+#define CCU8_CC8_TC_STRM_Pos                  10                                                      /*!< CCU8_CC8 TC: STRM Position              */\r
+#define CCU8_CC8_TC_STRM_Msk                  (0x01UL << CCU8_CC8_TC_STRM_Pos)                        /*!< CCU8_CC8 TC: STRM Mask                  */\r
+#define CCU8_CC8_TC_SCE_Pos                   11                                                      /*!< CCU8_CC8 TC: SCE Position               */\r
+#define CCU8_CC8_TC_SCE_Msk                   (0x01UL << CCU8_CC8_TC_SCE_Pos)                         /*!< CCU8_CC8 TC: SCE Mask                   */\r
+#define CCU8_CC8_TC_CCS_Pos                   12                                                      /*!< CCU8_CC8 TC: CCS Position               */\r
+#define CCU8_CC8_TC_CCS_Msk                   (0x01UL << CCU8_CC8_TC_CCS_Pos)                         /*!< CCU8_CC8 TC: CCS Mask                   */\r
+#define CCU8_CC8_TC_DITHE_Pos                 13                                                      /*!< CCU8_CC8 TC: DITHE Position             */\r
+#define CCU8_CC8_TC_DITHE_Msk                 (0x03UL << CCU8_CC8_TC_DITHE_Pos)                       /*!< CCU8_CC8 TC: DITHE Mask                 */\r
+#define CCU8_CC8_TC_DIM_Pos                   15                                                      /*!< CCU8_CC8 TC: DIM Position               */\r
+#define CCU8_CC8_TC_DIM_Msk                   (0x01UL << CCU8_CC8_TC_DIM_Pos)                         /*!< CCU8_CC8 TC: DIM Mask                   */\r
+#define CCU8_CC8_TC_FPE_Pos                   16                                                      /*!< CCU8_CC8 TC: FPE Position               */\r
+#define CCU8_CC8_TC_FPE_Msk                   (0x01UL << CCU8_CC8_TC_FPE_Pos)                         /*!< CCU8_CC8 TC: FPE Mask                   */\r
+#define CCU8_CC8_TC_TRAPE0_Pos                17                                                      /*!< CCU8_CC8 TC: TRAPE0 Position            */\r
+#define CCU8_CC8_TC_TRAPE0_Msk                (0x01UL << CCU8_CC8_TC_TRAPE0_Pos)                      /*!< CCU8_CC8 TC: TRAPE0 Mask                */\r
+#define CCU8_CC8_TC_TRAPE1_Pos                18                                                      /*!< CCU8_CC8 TC: TRAPE1 Position            */\r
+#define CCU8_CC8_TC_TRAPE1_Msk                (0x01UL << CCU8_CC8_TC_TRAPE1_Pos)                      /*!< CCU8_CC8 TC: TRAPE1 Mask                */\r
+#define CCU8_CC8_TC_TRAPE2_Pos                19                                                      /*!< CCU8_CC8 TC: TRAPE2 Position            */\r
+#define CCU8_CC8_TC_TRAPE2_Msk                (0x01UL << CCU8_CC8_TC_TRAPE2_Pos)                      /*!< CCU8_CC8 TC: TRAPE2 Mask                */\r
+#define CCU8_CC8_TC_TRAPE3_Pos                20                                                      /*!< CCU8_CC8 TC: TRAPE3 Position            */\r
+#define CCU8_CC8_TC_TRAPE3_Msk                (0x01UL << CCU8_CC8_TC_TRAPE3_Pos)                      /*!< CCU8_CC8 TC: TRAPE3 Mask                */\r
+#define CCU8_CC8_TC_TRPSE_Pos                 21                                                      /*!< CCU8_CC8 TC: TRPSE Position             */\r
+#define CCU8_CC8_TC_TRPSE_Msk                 (0x01UL << CCU8_CC8_TC_TRPSE_Pos)                       /*!< CCU8_CC8 TC: TRPSE Mask                 */\r
+#define CCU8_CC8_TC_TRPSW_Pos                 22                                                      /*!< CCU8_CC8 TC: TRPSW Position             */\r
+#define CCU8_CC8_TC_TRPSW_Msk                 (0x01UL << CCU8_CC8_TC_TRPSW_Pos)                       /*!< CCU8_CC8 TC: TRPSW Mask                 */\r
+#define CCU8_CC8_TC_EMS_Pos                   23                                                      /*!< CCU8_CC8 TC: EMS Position               */\r
+#define CCU8_CC8_TC_EMS_Msk                   (0x01UL << CCU8_CC8_TC_EMS_Pos)                         /*!< CCU8_CC8 TC: EMS Mask                   */\r
+#define CCU8_CC8_TC_EMT_Pos                   24                                                      /*!< CCU8_CC8 TC: EMT Position               */\r
+#define CCU8_CC8_TC_EMT_Msk                   (0x01UL << CCU8_CC8_TC_EMT_Pos)                         /*!< CCU8_CC8 TC: EMT Mask                   */\r
+#define CCU8_CC8_TC_MCME1_Pos                 25                                                      /*!< CCU8_CC8 TC: MCME1 Position             */\r
+#define CCU8_CC8_TC_MCME1_Msk                 (0x01UL << CCU8_CC8_TC_MCME1_Pos)                       /*!< CCU8_CC8 TC: MCME1 Mask                 */\r
+#define CCU8_CC8_TC_MCME2_Pos                 26                                                      /*!< CCU8_CC8 TC: MCME2 Position             */\r
+#define CCU8_CC8_TC_MCME2_Msk                 (0x01UL << CCU8_CC8_TC_MCME2_Pos)                       /*!< CCU8_CC8 TC: MCME2 Mask                 */\r
+#define CCU8_CC8_TC_EME_Pos                   27                                                      /*!< CCU8_CC8 TC: EME Position               */\r
+#define CCU8_CC8_TC_EME_Msk                   (0x03UL << CCU8_CC8_TC_EME_Pos)                         /*!< CCU8_CC8 TC: EME Mask                   */\r
+#define CCU8_CC8_TC_STOS_Pos                  29                                                      /*!< CCU8_CC8 TC: STOS Position              */\r
+#define CCU8_CC8_TC_STOS_Msk                  (0x03UL << CCU8_CC8_TC_STOS_Pos)                        /*!< CCU8_CC8 TC: STOS Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_PSL  -------------------------------- */\r
+#define CCU8_CC8_PSL_PSL11_Pos                0                                                       /*!< CCU8_CC8 PSL: PSL11 Position            */\r
+#define CCU8_CC8_PSL_PSL11_Msk                (0x01UL << CCU8_CC8_PSL_PSL11_Pos)                      /*!< CCU8_CC8 PSL: PSL11 Mask                */\r
+#define CCU8_CC8_PSL_PSL12_Pos                1                                                       /*!< CCU8_CC8 PSL: PSL12 Position            */\r
+#define CCU8_CC8_PSL_PSL12_Msk                (0x01UL << CCU8_CC8_PSL_PSL12_Pos)                      /*!< CCU8_CC8 PSL: PSL12 Mask                */\r
+#define CCU8_CC8_PSL_PSL21_Pos                2                                                       /*!< CCU8_CC8 PSL: PSL21 Position            */\r
+#define CCU8_CC8_PSL_PSL21_Msk                (0x01UL << CCU8_CC8_PSL_PSL21_Pos)                      /*!< CCU8_CC8 PSL: PSL21 Mask                */\r
+#define CCU8_CC8_PSL_PSL22_Pos                3                                                       /*!< CCU8_CC8 PSL: PSL22 Position            */\r
+#define CCU8_CC8_PSL_PSL22_Msk                (0x01UL << CCU8_CC8_PSL_PSL22_Pos)                      /*!< CCU8_CC8 PSL: PSL22 Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_DIT  -------------------------------- */\r
+#define CCU8_CC8_DIT_DCV_Pos                  0                                                       /*!< CCU8_CC8 DIT: DCV Position              */\r
+#define CCU8_CC8_DIT_DCV_Msk                  (0x0fUL << CCU8_CC8_DIT_DCV_Pos)                        /*!< CCU8_CC8 DIT: DCV Mask                  */\r
+#define CCU8_CC8_DIT_DCNT_Pos                 8                                                       /*!< CCU8_CC8 DIT: DCNT Position             */\r
+#define CCU8_CC8_DIT_DCNT_Msk                 (0x0fUL << CCU8_CC8_DIT_DCNT_Pos)                       /*!< CCU8_CC8 DIT: DCNT Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_DITS  ------------------------------- */\r
+#define CCU8_CC8_DITS_DCVS_Pos                0                                                       /*!< CCU8_CC8 DITS: DCVS Position            */\r
+#define CCU8_CC8_DITS_DCVS_Msk                (0x0fUL << CCU8_CC8_DITS_DCVS_Pos)                      /*!< CCU8_CC8 DITS: DCVS Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_PSC  -------------------------------- */\r
+#define CCU8_CC8_PSC_PSIV_Pos                 0                                                       /*!< CCU8_CC8 PSC: PSIV Position             */\r
+#define CCU8_CC8_PSC_PSIV_Msk                 (0x0fUL << CCU8_CC8_PSC_PSIV_Pos)                       /*!< CCU8_CC8 PSC: PSIV Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_FPC  -------------------------------- */\r
+#define CCU8_CC8_FPC_PCMP_Pos                 0                                                       /*!< CCU8_CC8 FPC: PCMP Position             */\r
+#define CCU8_CC8_FPC_PCMP_Msk                 (0x0fUL << CCU8_CC8_FPC_PCMP_Pos)                       /*!< CCU8_CC8 FPC: PCMP Mask                 */\r
+#define CCU8_CC8_FPC_PVAL_Pos                 8                                                       /*!< CCU8_CC8 FPC: PVAL Position             */\r
+#define CCU8_CC8_FPC_PVAL_Msk                 (0x0fUL << CCU8_CC8_FPC_PVAL_Pos)                       /*!< CCU8_CC8 FPC: PVAL Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_FPCS  ------------------------------- */\r
+#define CCU8_CC8_FPCS_PCMP_Pos                0                                                       /*!< CCU8_CC8 FPCS: PCMP Position            */\r
+#define CCU8_CC8_FPCS_PCMP_Msk                (0x0fUL << CCU8_CC8_FPCS_PCMP_Pos)                      /*!< CCU8_CC8 FPCS: PCMP Mask                */\r
+\r
+/* ---------------------------------  CCU8_CC8_PR  -------------------------------- */\r
+#define CCU8_CC8_PR_PR_Pos                    0                                                       /*!< CCU8_CC8 PR: PR Position                */\r
+#define CCU8_CC8_PR_PR_Msk                    (0x0000ffffUL << CCU8_CC8_PR_PR_Pos)                    /*!< CCU8_CC8 PR: PR Mask                    */\r
+\r
+/* --------------------------------  CCU8_CC8_PRS  -------------------------------- */\r
+#define CCU8_CC8_PRS_PRS_Pos                  0                                                       /*!< CCU8_CC8 PRS: PRS Position              */\r
+#define CCU8_CC8_PRS_PRS_Msk                  (0x0000ffffUL << CCU8_CC8_PRS_PRS_Pos)                  /*!< CCU8_CC8 PRS: PRS Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_CR1  -------------------------------- */\r
+#define CCU8_CC8_CR1_CR1_Pos                  0                                                       /*!< CCU8_CC8 CR1: CR1 Position              */\r
+#define CCU8_CC8_CR1_CR1_Msk                  (0x0000ffffUL << CCU8_CC8_CR1_CR1_Pos)                  /*!< CCU8_CC8 CR1: CR1 Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_CR1S  ------------------------------- */\r
+#define CCU8_CC8_CR1S_CR1S_Pos                0                                                       /*!< CCU8_CC8 CR1S: CR1S Position            */\r
+#define CCU8_CC8_CR1S_CR1S_Msk                (0x0000ffffUL << CCU8_CC8_CR1S_CR1S_Pos)                /*!< CCU8_CC8 CR1S: CR1S Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_CR2  -------------------------------- */\r
+#define CCU8_CC8_CR2_CR2_Pos                  0                                                       /*!< CCU8_CC8 CR2: CR2 Position              */\r
+#define CCU8_CC8_CR2_CR2_Msk                  (0x0000ffffUL << CCU8_CC8_CR2_CR2_Pos)                  /*!< CCU8_CC8 CR2: CR2 Mask                  */\r
+\r
+/* --------------------------------  CCU8_CC8_CR2S  ------------------------------- */\r
+#define CCU8_CC8_CR2S_CR2S_Pos                0                                                       /*!< CCU8_CC8 CR2S: CR2S Position            */\r
+#define CCU8_CC8_CR2S_CR2S_Msk                (0x0000ffffUL << CCU8_CC8_CR2S_CR2S_Pos)                /*!< CCU8_CC8 CR2S: CR2S Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_CHC  -------------------------------- */\r
+#define CCU8_CC8_CHC_ASE_Pos                  0                                                       /*!< CCU8_CC8 CHC: ASE Position              */\r
+#define CCU8_CC8_CHC_ASE_Msk                  (0x01UL << CCU8_CC8_CHC_ASE_Pos)                        /*!< CCU8_CC8 CHC: ASE Mask                  */\r
+#define CCU8_CC8_CHC_OCS1_Pos                 1                                                       /*!< CCU8_CC8 CHC: OCS1 Position             */\r
+#define CCU8_CC8_CHC_OCS1_Msk                 (0x01UL << CCU8_CC8_CHC_OCS1_Pos)                       /*!< CCU8_CC8 CHC: OCS1 Mask                 */\r
+#define CCU8_CC8_CHC_OCS2_Pos                 2                                                       /*!< CCU8_CC8 CHC: OCS2 Position             */\r
+#define CCU8_CC8_CHC_OCS2_Msk                 (0x01UL << CCU8_CC8_CHC_OCS2_Pos)                       /*!< CCU8_CC8 CHC: OCS2 Mask                 */\r
+#define CCU8_CC8_CHC_OCS3_Pos                 3                                                       /*!< CCU8_CC8 CHC: OCS3 Position             */\r
+#define CCU8_CC8_CHC_OCS3_Msk                 (0x01UL << CCU8_CC8_CHC_OCS3_Pos)                       /*!< CCU8_CC8 CHC: OCS3 Mask                 */\r
+#define CCU8_CC8_CHC_OCS4_Pos                 4                                                       /*!< CCU8_CC8 CHC: OCS4 Position             */\r
+#define CCU8_CC8_CHC_OCS4_Msk                 (0x01UL << CCU8_CC8_CHC_OCS4_Pos)                       /*!< CCU8_CC8 CHC: OCS4 Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_DTC  -------------------------------- */\r
+#define CCU8_CC8_DTC_DTE1_Pos                 0                                                       /*!< CCU8_CC8 DTC: DTE1 Position             */\r
+#define CCU8_CC8_DTC_DTE1_Msk                 (0x01UL << CCU8_CC8_DTC_DTE1_Pos)                       /*!< CCU8_CC8 DTC: DTE1 Mask                 */\r
+#define CCU8_CC8_DTC_DTE2_Pos                 1                                                       /*!< CCU8_CC8 DTC: DTE2 Position             */\r
+#define CCU8_CC8_DTC_DTE2_Msk                 (0x01UL << CCU8_CC8_DTC_DTE2_Pos)                       /*!< CCU8_CC8 DTC: DTE2 Mask                 */\r
+#define CCU8_CC8_DTC_DCEN1_Pos                2                                                       /*!< CCU8_CC8 DTC: DCEN1 Position            */\r
+#define CCU8_CC8_DTC_DCEN1_Msk                (0x01UL << CCU8_CC8_DTC_DCEN1_Pos)                      /*!< CCU8_CC8 DTC: DCEN1 Mask                */\r
+#define CCU8_CC8_DTC_DCEN2_Pos                3                                                       /*!< CCU8_CC8 DTC: DCEN2 Position            */\r
+#define CCU8_CC8_DTC_DCEN2_Msk                (0x01UL << CCU8_CC8_DTC_DCEN2_Pos)                      /*!< CCU8_CC8 DTC: DCEN2 Mask                */\r
+#define CCU8_CC8_DTC_DCEN3_Pos                4                                                       /*!< CCU8_CC8 DTC: DCEN3 Position            */\r
+#define CCU8_CC8_DTC_DCEN3_Msk                (0x01UL << CCU8_CC8_DTC_DCEN3_Pos)                      /*!< CCU8_CC8 DTC: DCEN3 Mask                */\r
+#define CCU8_CC8_DTC_DCEN4_Pos                5                                                       /*!< CCU8_CC8 DTC: DCEN4 Position            */\r
+#define CCU8_CC8_DTC_DCEN4_Msk                (0x01UL << CCU8_CC8_DTC_DCEN4_Pos)                      /*!< CCU8_CC8 DTC: DCEN4 Mask                */\r
+#define CCU8_CC8_DTC_DTCC_Pos                 6                                                       /*!< CCU8_CC8 DTC: DTCC Position             */\r
+#define CCU8_CC8_DTC_DTCC_Msk                 (0x03UL << CCU8_CC8_DTC_DTCC_Pos)                       /*!< CCU8_CC8 DTC: DTCC Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_DC1R  ------------------------------- */\r
+#define CCU8_CC8_DC1R_DT1R_Pos                0                                                       /*!< CCU8_CC8 DC1R: DT1R Position            */\r
+#define CCU8_CC8_DC1R_DT1R_Msk                (0x000000ffUL << CCU8_CC8_DC1R_DT1R_Pos)                /*!< CCU8_CC8 DC1R: DT1R Mask                */\r
+#define CCU8_CC8_DC1R_DT1F_Pos                8                                                       /*!< CCU8_CC8 DC1R: DT1F Position            */\r
+#define CCU8_CC8_DC1R_DT1F_Msk                (0x000000ffUL << CCU8_CC8_DC1R_DT1F_Pos)                /*!< CCU8_CC8 DC1R: DT1F Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_DC2R  ------------------------------- */\r
+#define CCU8_CC8_DC2R_DT2R_Pos                0                                                       /*!< CCU8_CC8 DC2R: DT2R Position            */\r
+#define CCU8_CC8_DC2R_DT2R_Msk                (0x000000ffUL << CCU8_CC8_DC2R_DT2R_Pos)                /*!< CCU8_CC8 DC2R: DT2R Mask                */\r
+#define CCU8_CC8_DC2R_DT2F_Pos                8                                                       /*!< CCU8_CC8 DC2R: DT2F Position            */\r
+#define CCU8_CC8_DC2R_DT2F_Msk                (0x000000ffUL << CCU8_CC8_DC2R_DT2F_Pos)                /*!< CCU8_CC8 DC2R: DT2F Mask                */\r
+\r
+/* -------------------------------  CCU8_CC8_TIMER  ------------------------------- */\r
+#define CCU8_CC8_TIMER_TVAL_Pos               0                                                       /*!< CCU8_CC8 TIMER: TVAL Position           */\r
+#define CCU8_CC8_TIMER_TVAL_Msk               (0x0000ffffUL << CCU8_CC8_TIMER_TVAL_Pos)               /*!< CCU8_CC8 TIMER: TVAL Mask               */\r
+\r
+/* ---------------------------------  CCU8_CC8_CV  -------------------------------- */\r
+#define CCU8_CC8_CV_CAPTV_Pos                 0                                                       /*!< CCU8_CC8 CV: CAPTV Position             */\r
+#define CCU8_CC8_CV_CAPTV_Msk                 (0x0000ffffUL << CCU8_CC8_CV_CAPTV_Pos)                 /*!< CCU8_CC8 CV: CAPTV Mask                 */\r
+#define CCU8_CC8_CV_FPCV_Pos                  16                                                      /*!< CCU8_CC8 CV: FPCV Position              */\r
+#define CCU8_CC8_CV_FPCV_Msk                  (0x0fUL << CCU8_CC8_CV_FPCV_Pos)                        /*!< CCU8_CC8 CV: FPCV Mask                  */\r
+#define CCU8_CC8_CV_FFL_Pos                   20                                                      /*!< CCU8_CC8 CV: FFL Position               */\r
+#define CCU8_CC8_CV_FFL_Msk                   (0x01UL << CCU8_CC8_CV_FFL_Pos)                         /*!< CCU8_CC8 CV: FFL Mask                   */\r
+\r
+/* --------------------------------  CCU8_CC8_INTS  ------------------------------- */\r
+#define CCU8_CC8_INTS_PMUS_Pos                0                                                       /*!< CCU8_CC8 INTS: PMUS Position            */\r
+#define CCU8_CC8_INTS_PMUS_Msk                (0x01UL << CCU8_CC8_INTS_PMUS_Pos)                      /*!< CCU8_CC8 INTS: PMUS Mask                */\r
+#define CCU8_CC8_INTS_OMDS_Pos                1                                                       /*!< CCU8_CC8 INTS: OMDS Position            */\r
+#define CCU8_CC8_INTS_OMDS_Msk                (0x01UL << CCU8_CC8_INTS_OMDS_Pos)                      /*!< CCU8_CC8 INTS: OMDS Mask                */\r
+#define CCU8_CC8_INTS_CMU1S_Pos               2                                                       /*!< CCU8_CC8 INTS: CMU1S Position           */\r
+#define CCU8_CC8_INTS_CMU1S_Msk               (0x01UL << CCU8_CC8_INTS_CMU1S_Pos)                     /*!< CCU8_CC8 INTS: CMU1S Mask               */\r
+#define CCU8_CC8_INTS_CMD1S_Pos               3                                                       /*!< CCU8_CC8 INTS: CMD1S Position           */\r
+#define CCU8_CC8_INTS_CMD1S_Msk               (0x01UL << CCU8_CC8_INTS_CMD1S_Pos)                     /*!< CCU8_CC8 INTS: CMD1S Mask               */\r
+#define CCU8_CC8_INTS_CMU2S_Pos               4                                                       /*!< CCU8_CC8 INTS: CMU2S Position           */\r
+#define CCU8_CC8_INTS_CMU2S_Msk               (0x01UL << CCU8_CC8_INTS_CMU2S_Pos)                     /*!< CCU8_CC8 INTS: CMU2S Mask               */\r
+#define CCU8_CC8_INTS_CMD2S_Pos               5                                                       /*!< CCU8_CC8 INTS: CMD2S Position           */\r
+#define CCU8_CC8_INTS_CMD2S_Msk               (0x01UL << CCU8_CC8_INTS_CMD2S_Pos)                     /*!< CCU8_CC8 INTS: CMD2S Mask               */\r
+#define CCU8_CC8_INTS_E0AS_Pos                8                                                       /*!< CCU8_CC8 INTS: E0AS Position            */\r
+#define CCU8_CC8_INTS_E0AS_Msk                (0x01UL << CCU8_CC8_INTS_E0AS_Pos)                      /*!< CCU8_CC8 INTS: E0AS Mask                */\r
+#define CCU8_CC8_INTS_E1AS_Pos                9                                                       /*!< CCU8_CC8 INTS: E1AS Position            */\r
+#define CCU8_CC8_INTS_E1AS_Msk                (0x01UL << CCU8_CC8_INTS_E1AS_Pos)                      /*!< CCU8_CC8 INTS: E1AS Mask                */\r
+#define CCU8_CC8_INTS_E2AS_Pos                10                                                      /*!< CCU8_CC8 INTS: E2AS Position            */\r
+#define CCU8_CC8_INTS_E2AS_Msk                (0x01UL << CCU8_CC8_INTS_E2AS_Pos)                      /*!< CCU8_CC8 INTS: E2AS Mask                */\r
+#define CCU8_CC8_INTS_TRPF_Pos                11                                                      /*!< CCU8_CC8 INTS: TRPF Position            */\r
+#define CCU8_CC8_INTS_TRPF_Msk                (0x01UL << CCU8_CC8_INTS_TRPF_Pos)                      /*!< CCU8_CC8 INTS: TRPF Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_INTE  ------------------------------- */\r
+#define CCU8_CC8_INTE_PME_Pos                 0                                                       /*!< CCU8_CC8 INTE: PME Position             */\r
+#define CCU8_CC8_INTE_PME_Msk                 (0x01UL << CCU8_CC8_INTE_PME_Pos)                       /*!< CCU8_CC8 INTE: PME Mask                 */\r
+#define CCU8_CC8_INTE_OME_Pos                 1                                                       /*!< CCU8_CC8 INTE: OME Position             */\r
+#define CCU8_CC8_INTE_OME_Msk                 (0x01UL << CCU8_CC8_INTE_OME_Pos)                       /*!< CCU8_CC8 INTE: OME Mask                 */\r
+#define CCU8_CC8_INTE_CMU1E_Pos               2                                                       /*!< CCU8_CC8 INTE: CMU1E Position           */\r
+#define CCU8_CC8_INTE_CMU1E_Msk               (0x01UL << CCU8_CC8_INTE_CMU1E_Pos)                     /*!< CCU8_CC8 INTE: CMU1E Mask               */\r
+#define CCU8_CC8_INTE_CMD1E_Pos               3                                                       /*!< CCU8_CC8 INTE: CMD1E Position           */\r
+#define CCU8_CC8_INTE_CMD1E_Msk               (0x01UL << CCU8_CC8_INTE_CMD1E_Pos)                     /*!< CCU8_CC8 INTE: CMD1E Mask               */\r
+#define CCU8_CC8_INTE_CMU2E_Pos               4                                                       /*!< CCU8_CC8 INTE: CMU2E Position           */\r
+#define CCU8_CC8_INTE_CMU2E_Msk               (0x01UL << CCU8_CC8_INTE_CMU2E_Pos)                     /*!< CCU8_CC8 INTE: CMU2E Mask               */\r
+#define CCU8_CC8_INTE_CMD2E_Pos               5                                                       /*!< CCU8_CC8 INTE: CMD2E Position           */\r
+#define CCU8_CC8_INTE_CMD2E_Msk               (0x01UL << CCU8_CC8_INTE_CMD2E_Pos)                     /*!< CCU8_CC8 INTE: CMD2E Mask               */\r
+#define CCU8_CC8_INTE_E0AE_Pos                8                                                       /*!< CCU8_CC8 INTE: E0AE Position            */\r
+#define CCU8_CC8_INTE_E0AE_Msk                (0x01UL << CCU8_CC8_INTE_E0AE_Pos)                      /*!< CCU8_CC8 INTE: E0AE Mask                */\r
+#define CCU8_CC8_INTE_E1AE_Pos                9                                                       /*!< CCU8_CC8 INTE: E1AE Position            */\r
+#define CCU8_CC8_INTE_E1AE_Msk                (0x01UL << CCU8_CC8_INTE_E1AE_Pos)                      /*!< CCU8_CC8 INTE: E1AE Mask                */\r
+#define CCU8_CC8_INTE_E2AE_Pos                10                                                      /*!< CCU8_CC8 INTE: E2AE Position            */\r
+#define CCU8_CC8_INTE_E2AE_Msk                (0x01UL << CCU8_CC8_INTE_E2AE_Pos)                      /*!< CCU8_CC8 INTE: E2AE Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_SRS  -------------------------------- */\r
+#define CCU8_CC8_SRS_POSR_Pos                 0                                                       /*!< CCU8_CC8 SRS: POSR Position             */\r
+#define CCU8_CC8_SRS_POSR_Msk                 (0x03UL << CCU8_CC8_SRS_POSR_Pos)                       /*!< CCU8_CC8 SRS: POSR Mask                 */\r
+#define CCU8_CC8_SRS_CM1SR_Pos                2                                                       /*!< CCU8_CC8 SRS: CM1SR Position            */\r
+#define CCU8_CC8_SRS_CM1SR_Msk                (0x03UL << CCU8_CC8_SRS_CM1SR_Pos)                      /*!< CCU8_CC8 SRS: CM1SR Mask                */\r
+#define CCU8_CC8_SRS_CM2SR_Pos                4                                                       /*!< CCU8_CC8 SRS: CM2SR Position            */\r
+#define CCU8_CC8_SRS_CM2SR_Msk                (0x03UL << CCU8_CC8_SRS_CM2SR_Pos)                      /*!< CCU8_CC8 SRS: CM2SR Mask                */\r
+#define CCU8_CC8_SRS_E0SR_Pos                 8                                                       /*!< CCU8_CC8 SRS: E0SR Position             */\r
+#define CCU8_CC8_SRS_E0SR_Msk                 (0x03UL << CCU8_CC8_SRS_E0SR_Pos)                       /*!< CCU8_CC8 SRS: E0SR Mask                 */\r
+#define CCU8_CC8_SRS_E1SR_Pos                 10                                                      /*!< CCU8_CC8 SRS: E1SR Position             */\r
+#define CCU8_CC8_SRS_E1SR_Msk                 (0x03UL << CCU8_CC8_SRS_E1SR_Pos)                       /*!< CCU8_CC8 SRS: E1SR Mask                 */\r
+#define CCU8_CC8_SRS_E2SR_Pos                 12                                                      /*!< CCU8_CC8 SRS: E2SR Position             */\r
+#define CCU8_CC8_SRS_E2SR_Msk                 (0x03UL << CCU8_CC8_SRS_E2SR_Pos)                       /*!< CCU8_CC8 SRS: E2SR Mask                 */\r
+\r
+/* --------------------------------  CCU8_CC8_SWS  -------------------------------- */\r
+#define CCU8_CC8_SWS_SPM_Pos                  0                                                       /*!< CCU8_CC8 SWS: SPM Position              */\r
+#define CCU8_CC8_SWS_SPM_Msk                  (0x01UL << CCU8_CC8_SWS_SPM_Pos)                        /*!< CCU8_CC8 SWS: SPM Mask                  */\r
+#define CCU8_CC8_SWS_SOM_Pos                  1                                                       /*!< CCU8_CC8 SWS: SOM Position              */\r
+#define CCU8_CC8_SWS_SOM_Msk                  (0x01UL << CCU8_CC8_SWS_SOM_Pos)                        /*!< CCU8_CC8 SWS: SOM Mask                  */\r
+#define CCU8_CC8_SWS_SCM1U_Pos                2                                                       /*!< CCU8_CC8 SWS: SCM1U Position            */\r
+#define CCU8_CC8_SWS_SCM1U_Msk                (0x01UL << CCU8_CC8_SWS_SCM1U_Pos)                      /*!< CCU8_CC8 SWS: SCM1U Mask                */\r
+#define CCU8_CC8_SWS_SCM1D_Pos                3                                                       /*!< CCU8_CC8 SWS: SCM1D Position            */\r
+#define CCU8_CC8_SWS_SCM1D_Msk                (0x01UL << CCU8_CC8_SWS_SCM1D_Pos)                      /*!< CCU8_CC8 SWS: SCM1D Mask                */\r
+#define CCU8_CC8_SWS_SCM2U_Pos                4                                                       /*!< CCU8_CC8 SWS: SCM2U Position            */\r
+#define CCU8_CC8_SWS_SCM2U_Msk                (0x01UL << CCU8_CC8_SWS_SCM2U_Pos)                      /*!< CCU8_CC8 SWS: SCM2U Mask                */\r
+#define CCU8_CC8_SWS_SCM2D_Pos                5                                                       /*!< CCU8_CC8 SWS: SCM2D Position            */\r
+#define CCU8_CC8_SWS_SCM2D_Msk                (0x01UL << CCU8_CC8_SWS_SCM2D_Pos)                      /*!< CCU8_CC8 SWS: SCM2D Mask                */\r
+#define CCU8_CC8_SWS_SE0A_Pos                 8                                                       /*!< CCU8_CC8 SWS: SE0A Position             */\r
+#define CCU8_CC8_SWS_SE0A_Msk                 (0x01UL << CCU8_CC8_SWS_SE0A_Pos)                       /*!< CCU8_CC8 SWS: SE0A Mask                 */\r
+#define CCU8_CC8_SWS_SE1A_Pos                 9                                                       /*!< CCU8_CC8 SWS: SE1A Position             */\r
+#define CCU8_CC8_SWS_SE1A_Msk                 (0x01UL << CCU8_CC8_SWS_SE1A_Pos)                       /*!< CCU8_CC8 SWS: SE1A Mask                 */\r
+#define CCU8_CC8_SWS_SE2A_Pos                 10                                                      /*!< CCU8_CC8 SWS: SE2A Position             */\r
+#define CCU8_CC8_SWS_SE2A_Msk                 (0x01UL << CCU8_CC8_SWS_SE2A_Pos)                       /*!< CCU8_CC8 SWS: SE2A Mask                 */\r
+#define CCU8_CC8_SWS_STRPF_Pos                11                                                      /*!< CCU8_CC8 SWS: STRPF Position            */\r
+#define CCU8_CC8_SWS_STRPF_Msk                (0x01UL << CCU8_CC8_SWS_STRPF_Pos)                      /*!< CCU8_CC8 SWS: STRPF Mask                */\r
+\r
+/* --------------------------------  CCU8_CC8_SWR  -------------------------------- */\r
+#define CCU8_CC8_SWR_RPM_Pos                  0                                                       /*!< CCU8_CC8 SWR: RPM Position              */\r
+#define CCU8_CC8_SWR_RPM_Msk                  (0x01UL << CCU8_CC8_SWR_RPM_Pos)                        /*!< CCU8_CC8 SWR: RPM Mask                  */\r
+#define CCU8_CC8_SWR_ROM_Pos                  1                                                       /*!< CCU8_CC8 SWR: ROM Position              */\r
+#define CCU8_CC8_SWR_ROM_Msk                  (0x01UL << CCU8_CC8_SWR_ROM_Pos)                        /*!< CCU8_CC8 SWR: ROM Mask                  */\r
+#define CCU8_CC8_SWR_RCM1U_Pos                2                                                       /*!< CCU8_CC8 SWR: RCM1U Position            */\r
+#define CCU8_CC8_SWR_RCM1U_Msk                (0x01UL << CCU8_CC8_SWR_RCM1U_Pos)                      /*!< CCU8_CC8 SWR: RCM1U Mask                */\r
+#define CCU8_CC8_SWR_RCM1D_Pos                3                                                       /*!< CCU8_CC8 SWR: RCM1D Position            */\r
+#define CCU8_CC8_SWR_RCM1D_Msk                (0x01UL << CCU8_CC8_SWR_RCM1D_Pos)                      /*!< CCU8_CC8 SWR: RCM1D Mask                */\r
+#define CCU8_CC8_SWR_RCM2U_Pos                4                                                       /*!< CCU8_CC8 SWR: RCM2U Position            */\r
+#define CCU8_CC8_SWR_RCM2U_Msk                (0x01UL << CCU8_CC8_SWR_RCM2U_Pos)                      /*!< CCU8_CC8 SWR: RCM2U Mask                */\r
+#define CCU8_CC8_SWR_RCM2D_Pos                5                                                       /*!< CCU8_CC8 SWR: RCM2D Position            */\r
+#define CCU8_CC8_SWR_RCM2D_Msk                (0x01UL << CCU8_CC8_SWR_RCM2D_Pos)                      /*!< CCU8_CC8 SWR: RCM2D Mask                */\r
+#define CCU8_CC8_SWR_RE0A_Pos                 8                                                       /*!< CCU8_CC8 SWR: RE0A Position             */\r
+#define CCU8_CC8_SWR_RE0A_Msk                 (0x01UL << CCU8_CC8_SWR_RE0A_Pos)                       /*!< CCU8_CC8 SWR: RE0A Mask                 */\r
+#define CCU8_CC8_SWR_RE1A_Pos                 9                                                       /*!< CCU8_CC8 SWR: RE1A Position             */\r
+#define CCU8_CC8_SWR_RE1A_Msk                 (0x01UL << CCU8_CC8_SWR_RE1A_Pos)                       /*!< CCU8_CC8 SWR: RE1A Mask                 */\r
+#define CCU8_CC8_SWR_RE2A_Pos                 10                                                      /*!< CCU8_CC8 SWR: RE2A Position             */\r
+#define CCU8_CC8_SWR_RE2A_Msk                 (0x01UL << CCU8_CC8_SWR_RE2A_Pos)                       /*!< CCU8_CC8 SWR: RE2A Mask                 */\r
+#define CCU8_CC8_SWR_RTRPF_Pos                11                                                      /*!< CCU8_CC8 SWR: RTRPF Position            */\r
+#define CCU8_CC8_SWR_RTRPF_Msk                (0x01UL << CCU8_CC8_SWR_RTRPF_Pos)                      /*!< CCU8_CC8 SWR: RTRPF Mask                */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================          Group 'POSIF' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  POSIF_PCONF  -------------------------------- */\r
+#define POSIF_PCONF_FSEL_Pos                  0                                                       /*!< POSIF PCONF: FSEL Position              */\r
+#define POSIF_PCONF_FSEL_Msk                  (0x03UL << POSIF_PCONF_FSEL_Pos)                        /*!< POSIF PCONF: FSEL Mask                  */\r
+#define POSIF_PCONF_QDCM_Pos                  2                                                       /*!< POSIF PCONF: QDCM Position              */\r
+#define POSIF_PCONF_QDCM_Msk                  (0x01UL << POSIF_PCONF_QDCM_Pos)                        /*!< POSIF PCONF: QDCM Mask                  */\r
+#define POSIF_PCONF_HIDG_Pos                  4                                                       /*!< POSIF PCONF: HIDG Position              */\r
+#define POSIF_PCONF_HIDG_Msk                  (0x01UL << POSIF_PCONF_HIDG_Pos)                        /*!< POSIF PCONF: HIDG Mask                  */\r
+#define POSIF_PCONF_MCUE_Pos                  5                                                       /*!< POSIF PCONF: MCUE Position              */\r
+#define POSIF_PCONF_MCUE_Msk                  (0x01UL << POSIF_PCONF_MCUE_Pos)                        /*!< POSIF PCONF: MCUE Mask                  */\r
+#define POSIF_PCONF_INSEL0_Pos                8                                                       /*!< POSIF PCONF: INSEL0 Position            */\r
+#define POSIF_PCONF_INSEL0_Msk                (0x03UL << POSIF_PCONF_INSEL0_Pos)                      /*!< POSIF PCONF: INSEL0 Mask                */\r
+#define POSIF_PCONF_INSEL1_Pos                10                                                      /*!< POSIF PCONF: INSEL1 Position            */\r
+#define POSIF_PCONF_INSEL1_Msk                (0x03UL << POSIF_PCONF_INSEL1_Pos)                      /*!< POSIF PCONF: INSEL1 Mask                */\r
+#define POSIF_PCONF_INSEL2_Pos                12                                                      /*!< POSIF PCONF: INSEL2 Position            */\r
+#define POSIF_PCONF_INSEL2_Msk                (0x03UL << POSIF_PCONF_INSEL2_Pos)                      /*!< POSIF PCONF: INSEL2 Mask                */\r
+#define POSIF_PCONF_DSEL_Pos                  16                                                      /*!< POSIF PCONF: DSEL Position              */\r
+#define POSIF_PCONF_DSEL_Msk                  (0x01UL << POSIF_PCONF_DSEL_Pos)                        /*!< POSIF PCONF: DSEL Mask                  */\r
+#define POSIF_PCONF_SPES_Pos                  17                                                      /*!< POSIF PCONF: SPES Position              */\r
+#define POSIF_PCONF_SPES_Msk                  (0x01UL << POSIF_PCONF_SPES_Pos)                        /*!< POSIF PCONF: SPES Mask                  */\r
+#define POSIF_PCONF_MSETS_Pos                 18                                                      /*!< POSIF PCONF: MSETS Position             */\r
+#define POSIF_PCONF_MSETS_Msk                 (0x07UL << POSIF_PCONF_MSETS_Pos)                       /*!< POSIF PCONF: MSETS Mask                 */\r
+#define POSIF_PCONF_MSES_Pos                  21                                                      /*!< POSIF PCONF: MSES Position              */\r
+#define POSIF_PCONF_MSES_Msk                  (0x01UL << POSIF_PCONF_MSES_Pos)                        /*!< POSIF PCONF: MSES Mask                  */\r
+#define POSIF_PCONF_MSYNS_Pos                 22                                                      /*!< POSIF PCONF: MSYNS Position             */\r
+#define POSIF_PCONF_MSYNS_Msk                 (0x03UL << POSIF_PCONF_MSYNS_Pos)                       /*!< POSIF PCONF: MSYNS Mask                 */\r
+#define POSIF_PCONF_EWIS_Pos                  24                                                      /*!< POSIF PCONF: EWIS Position              */\r
+#define POSIF_PCONF_EWIS_Msk                  (0x03UL << POSIF_PCONF_EWIS_Pos)                        /*!< POSIF PCONF: EWIS Mask                  */\r
+#define POSIF_PCONF_EWIE_Pos                  26                                                      /*!< POSIF PCONF: EWIE Position              */\r
+#define POSIF_PCONF_EWIE_Msk                  (0x01UL << POSIF_PCONF_EWIE_Pos)                        /*!< POSIF PCONF: EWIE Mask                  */\r
+#define POSIF_PCONF_EWIL_Pos                  27                                                      /*!< POSIF PCONF: EWIL Position              */\r
+#define POSIF_PCONF_EWIL_Msk                  (0x01UL << POSIF_PCONF_EWIL_Pos)                        /*!< POSIF PCONF: EWIL Mask                  */\r
+#define POSIF_PCONF_LPC_Pos                   28                                                      /*!< POSIF PCONF: LPC Position               */\r
+#define POSIF_PCONF_LPC_Msk                   (0x07UL << POSIF_PCONF_LPC_Pos)                         /*!< POSIF PCONF: LPC Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PSUS  --------------------------------- */\r
+#define POSIF_PSUS_QSUS_Pos                   0                                                       /*!< POSIF PSUS: QSUS Position               */\r
+#define POSIF_PSUS_QSUS_Msk                   (0x03UL << POSIF_PSUS_QSUS_Pos)                         /*!< POSIF PSUS: QSUS Mask                   */\r
+#define POSIF_PSUS_MSUS_Pos                   2                                                       /*!< POSIF PSUS: MSUS Position               */\r
+#define POSIF_PSUS_MSUS_Msk                   (0x03UL << POSIF_PSUS_MSUS_Pos)                         /*!< POSIF PSUS: MSUS Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PRUNS  -------------------------------- */\r
+#define POSIF_PRUNS_SRB_Pos                   0                                                       /*!< POSIF PRUNS: SRB Position               */\r
+#define POSIF_PRUNS_SRB_Msk                   (0x01UL << POSIF_PRUNS_SRB_Pos)                         /*!< POSIF PRUNS: SRB Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PRUNC  -------------------------------- */\r
+#define POSIF_PRUNC_CRB_Pos                   0                                                       /*!< POSIF PRUNC: CRB Position               */\r
+#define POSIF_PRUNC_CRB_Msk                   (0x01UL << POSIF_PRUNC_CRB_Pos)                         /*!< POSIF PRUNC: CRB Mask                   */\r
+#define POSIF_PRUNC_CSM_Pos                   1                                                       /*!< POSIF PRUNC: CSM Position               */\r
+#define POSIF_PRUNC_CSM_Msk                   (0x01UL << POSIF_PRUNC_CSM_Pos)                         /*!< POSIF PRUNC: CSM Mask                   */\r
+\r
+/* ---------------------------------  POSIF_PRUN  --------------------------------- */\r
+#define POSIF_PRUN_RB_Pos                     0                                                       /*!< POSIF PRUN: RB Position                 */\r
+#define POSIF_PRUN_RB_Msk                     (0x01UL << POSIF_PRUN_RB_Pos)                           /*!< POSIF PRUN: RB Mask                     */\r
+\r
+/* ---------------------------------  POSIF_MIDR  --------------------------------- */\r
+#define POSIF_MIDR_MODR_Pos                   0                                                       /*!< POSIF MIDR: MODR Position               */\r
+#define POSIF_MIDR_MODR_Msk                   (0x000000ffUL << POSIF_MIDR_MODR_Pos)                   /*!< POSIF MIDR: MODR Mask                   */\r
+#define POSIF_MIDR_MODT_Pos                   8                                                       /*!< POSIF MIDR: MODT Position               */\r
+#define POSIF_MIDR_MODT_Msk                   (0x000000ffUL << POSIF_MIDR_MODT_Pos)                   /*!< POSIF MIDR: MODT Mask                   */\r
+#define POSIF_MIDR_MODN_Pos                   16                                                      /*!< POSIF MIDR: MODN Position               */\r
+#define POSIF_MIDR_MODN_Msk                   (0x0000ffffUL << POSIF_MIDR_MODN_Pos)                   /*!< POSIF MIDR: MODN Mask                   */\r
+\r
+/* ---------------------------------  POSIF_HALP  --------------------------------- */\r
+#define POSIF_HALP_HCP_Pos                    0                                                       /*!< POSIF HALP: HCP Position                */\r
+#define POSIF_HALP_HCP_Msk                    (0x07UL << POSIF_HALP_HCP_Pos)                          /*!< POSIF HALP: HCP Mask                    */\r
+#define POSIF_HALP_HEP_Pos                    3                                                       /*!< POSIF HALP: HEP Position                */\r
+#define POSIF_HALP_HEP_Msk                    (0x07UL << POSIF_HALP_HEP_Pos)                          /*!< POSIF HALP: HEP Mask                    */\r
+\r
+/* ---------------------------------  POSIF_HALPS  -------------------------------- */\r
+#define POSIF_HALPS_HCPS_Pos                  0                                                       /*!< POSIF HALPS: HCPS Position              */\r
+#define POSIF_HALPS_HCPS_Msk                  (0x07UL << POSIF_HALPS_HCPS_Pos)                        /*!< POSIF HALPS: HCPS Mask                  */\r
+#define POSIF_HALPS_HEPS_Pos                  3                                                       /*!< POSIF HALPS: HEPS Position              */\r
+#define POSIF_HALPS_HEPS_Msk                  (0x07UL << POSIF_HALPS_HEPS_Pos)                        /*!< POSIF HALPS: HEPS Mask                  */\r
+\r
+/* ----------------------------------  POSIF_MCM  --------------------------------- */\r
+#define POSIF_MCM_MCMP_Pos                    0                                                       /*!< POSIF MCM: MCMP Position                */\r
+#define POSIF_MCM_MCMP_Msk                    (0x0000ffffUL << POSIF_MCM_MCMP_Pos)                    /*!< POSIF MCM: MCMP Mask                    */\r
+\r
+/* ---------------------------------  POSIF_MCSM  --------------------------------- */\r
+#define POSIF_MCSM_MCMPS_Pos                  0                                                       /*!< POSIF MCSM: MCMPS Position              */\r
+#define POSIF_MCSM_MCMPS_Msk                  (0x0000ffffUL << POSIF_MCSM_MCMPS_Pos)                  /*!< POSIF MCSM: MCMPS Mask                  */\r
+\r
+/* ---------------------------------  POSIF_MCMS  --------------------------------- */\r
+#define POSIF_MCMS_MNPS_Pos                   0                                                       /*!< POSIF MCMS: MNPS Position               */\r
+#define POSIF_MCMS_MNPS_Msk                   (0x01UL << POSIF_MCMS_MNPS_Pos)                         /*!< POSIF MCMS: MNPS Mask                   */\r
+#define POSIF_MCMS_STHR_Pos                   1                                                       /*!< POSIF MCMS: STHR Position               */\r
+#define POSIF_MCMS_STHR_Msk                   (0x01UL << POSIF_MCMS_STHR_Pos)                         /*!< POSIF MCMS: STHR Mask                   */\r
+#define POSIF_MCMS_STMR_Pos                   2                                                       /*!< POSIF MCMS: STMR Position               */\r
+#define POSIF_MCMS_STMR_Msk                   (0x01UL << POSIF_MCMS_STMR_Pos)                         /*!< POSIF MCMS: STMR Mask                   */\r
+\r
+/* ---------------------------------  POSIF_MCMC  --------------------------------- */\r
+#define POSIF_MCMC_MNPC_Pos                   0                                                       /*!< POSIF MCMC: MNPC Position               */\r
+#define POSIF_MCMC_MNPC_Msk                   (0x01UL << POSIF_MCMC_MNPC_Pos)                         /*!< POSIF MCMC: MNPC Mask                   */\r
+#define POSIF_MCMC_MPC_Pos                    1                                                       /*!< POSIF MCMC: MPC Position                */\r
+#define POSIF_MCMC_MPC_Msk                    (0x01UL << POSIF_MCMC_MPC_Pos)                          /*!< POSIF MCMC: MPC Mask                    */\r
+\r
+/* ---------------------------------  POSIF_MCMF  --------------------------------- */\r
+#define POSIF_MCMF_MSS_Pos                    0                                                       /*!< POSIF MCMF: MSS Position                */\r
+#define POSIF_MCMF_MSS_Msk                    (0x01UL << POSIF_MCMF_MSS_Pos)                          /*!< POSIF MCMF: MSS Mask                    */\r
+\r
+/* ----------------------------------  POSIF_QDC  --------------------------------- */\r
+#define POSIF_QDC_PALS_Pos                    0                                                       /*!< POSIF QDC: PALS Position                */\r
+#define POSIF_QDC_PALS_Msk                    (0x01UL << POSIF_QDC_PALS_Pos)                          /*!< POSIF QDC: PALS Mask                    */\r
+#define POSIF_QDC_PBLS_Pos                    1                                                       /*!< POSIF QDC: PBLS Position                */\r
+#define POSIF_QDC_PBLS_Msk                    (0x01UL << POSIF_QDC_PBLS_Pos)                          /*!< POSIF QDC: PBLS Mask                    */\r
+#define POSIF_QDC_PHS_Pos                     2                                                       /*!< POSIF QDC: PHS Position                 */\r
+#define POSIF_QDC_PHS_Msk                     (0x01UL << POSIF_QDC_PHS_Pos)                           /*!< POSIF QDC: PHS Mask                     */\r
+#define POSIF_QDC_ICM_Pos                     4                                                       /*!< POSIF QDC: ICM Position                 */\r
+#define POSIF_QDC_ICM_Msk                     (0x03UL << POSIF_QDC_ICM_Pos)                           /*!< POSIF QDC: ICM Mask                     */\r
+#define POSIF_QDC_DVAL_Pos                    8                                                       /*!< POSIF QDC: DVAL Position                */\r
+#define POSIF_QDC_DVAL_Msk                    (0x01UL << POSIF_QDC_DVAL_Pos)                          /*!< POSIF QDC: DVAL Mask                    */\r
+\r
+/* ---------------------------------  POSIF_PFLG  --------------------------------- */\r
+#define POSIF_PFLG_CHES_Pos                   0                                                       /*!< POSIF PFLG: CHES Position               */\r
+#define POSIF_PFLG_CHES_Msk                   (0x01UL << POSIF_PFLG_CHES_Pos)                         /*!< POSIF PFLG: CHES Mask                   */\r
+#define POSIF_PFLG_WHES_Pos                   1                                                       /*!< POSIF PFLG: WHES Position               */\r
+#define POSIF_PFLG_WHES_Msk                   (0x01UL << POSIF_PFLG_WHES_Pos)                         /*!< POSIF PFLG: WHES Mask                   */\r
+#define POSIF_PFLG_HIES_Pos                   2                                                       /*!< POSIF PFLG: HIES Position               */\r
+#define POSIF_PFLG_HIES_Msk                   (0x01UL << POSIF_PFLG_HIES_Pos)                         /*!< POSIF PFLG: HIES Mask                   */\r
+#define POSIF_PFLG_MSTS_Pos                   4                                                       /*!< POSIF PFLG: MSTS Position               */\r
+#define POSIF_PFLG_MSTS_Msk                   (0x01UL << POSIF_PFLG_MSTS_Pos)                         /*!< POSIF PFLG: MSTS Mask                   */\r
+#define POSIF_PFLG_INDXS_Pos                  8                                                       /*!< POSIF PFLG: INDXS Position              */\r
+#define POSIF_PFLG_INDXS_Msk                  (0x01UL << POSIF_PFLG_INDXS_Pos)                        /*!< POSIF PFLG: INDXS Mask                  */\r
+#define POSIF_PFLG_ERRS_Pos                   9                                                       /*!< POSIF PFLG: ERRS Position               */\r
+#define POSIF_PFLG_ERRS_Msk                   (0x01UL << POSIF_PFLG_ERRS_Pos)                         /*!< POSIF PFLG: ERRS Mask                   */\r
+#define POSIF_PFLG_CNTS_Pos                   10                                                      /*!< POSIF PFLG: CNTS Position               */\r
+#define POSIF_PFLG_CNTS_Msk                   (0x01UL << POSIF_PFLG_CNTS_Pos)                         /*!< POSIF PFLG: CNTS Mask                   */\r
+#define POSIF_PFLG_DIRS_Pos                   11                                                      /*!< POSIF PFLG: DIRS Position               */\r
+#define POSIF_PFLG_DIRS_Msk                   (0x01UL << POSIF_PFLG_DIRS_Pos)                         /*!< POSIF PFLG: DIRS Mask                   */\r
+#define POSIF_PFLG_PCLKS_Pos                  12                                                      /*!< POSIF PFLG: PCLKS Position              */\r
+#define POSIF_PFLG_PCLKS_Msk                  (0x01UL << POSIF_PFLG_PCLKS_Pos)                        /*!< POSIF PFLG: PCLKS Mask                  */\r
+\r
+/* ---------------------------------  POSIF_PFLGE  -------------------------------- */\r
+#define POSIF_PFLGE_ECHE_Pos                  0                                                       /*!< POSIF PFLGE: ECHE Position              */\r
+#define POSIF_PFLGE_ECHE_Msk                  (0x01UL << POSIF_PFLGE_ECHE_Pos)                        /*!< POSIF PFLGE: ECHE Mask                  */\r
+#define POSIF_PFLGE_EWHE_Pos                  1                                                       /*!< POSIF PFLGE: EWHE Position              */\r
+#define POSIF_PFLGE_EWHE_Msk                  (0x01UL << POSIF_PFLGE_EWHE_Pos)                        /*!< POSIF PFLGE: EWHE Mask                  */\r
+#define POSIF_PFLGE_EHIE_Pos                  2                                                       /*!< POSIF PFLGE: EHIE Position              */\r
+#define POSIF_PFLGE_EHIE_Msk                  (0x01UL << POSIF_PFLGE_EHIE_Pos)                        /*!< POSIF PFLGE: EHIE Mask                  */\r
+#define POSIF_PFLGE_EMST_Pos                  4                                                       /*!< POSIF PFLGE: EMST Position              */\r
+#define POSIF_PFLGE_EMST_Msk                  (0x01UL << POSIF_PFLGE_EMST_Pos)                        /*!< POSIF PFLGE: EMST Mask                  */\r
+#define POSIF_PFLGE_EINDX_Pos                 8                                                       /*!< POSIF PFLGE: EINDX Position             */\r
+#define POSIF_PFLGE_EINDX_Msk                 (0x01UL << POSIF_PFLGE_EINDX_Pos)                       /*!< POSIF PFLGE: EINDX Mask                 */\r
+#define POSIF_PFLGE_EERR_Pos                  9                                                       /*!< POSIF PFLGE: EERR Position              */\r
+#define POSIF_PFLGE_EERR_Msk                  (0x01UL << POSIF_PFLGE_EERR_Pos)                        /*!< POSIF PFLGE: EERR Mask                  */\r
+#define POSIF_PFLGE_ECNT_Pos                  10                                                      /*!< POSIF PFLGE: ECNT Position              */\r
+#define POSIF_PFLGE_ECNT_Msk                  (0x01UL << POSIF_PFLGE_ECNT_Pos)                        /*!< POSIF PFLGE: ECNT Mask                  */\r
+#define POSIF_PFLGE_EDIR_Pos                  11                                                      /*!< POSIF PFLGE: EDIR Position              */\r
+#define POSIF_PFLGE_EDIR_Msk                  (0x01UL << POSIF_PFLGE_EDIR_Pos)                        /*!< POSIF PFLGE: EDIR Mask                  */\r
+#define POSIF_PFLGE_EPCLK_Pos                 12                                                      /*!< POSIF PFLGE: EPCLK Position             */\r
+#define POSIF_PFLGE_EPCLK_Msk                 (0x01UL << POSIF_PFLGE_EPCLK_Pos)                       /*!< POSIF PFLGE: EPCLK Mask                 */\r
+#define POSIF_PFLGE_CHESEL_Pos                16                                                      /*!< POSIF PFLGE: CHESEL Position            */\r
+#define POSIF_PFLGE_CHESEL_Msk                (0x01UL << POSIF_PFLGE_CHESEL_Pos)                      /*!< POSIF PFLGE: CHESEL Mask                */\r
+#define POSIF_PFLGE_WHESEL_Pos                17                                                      /*!< POSIF PFLGE: WHESEL Position            */\r
+#define POSIF_PFLGE_WHESEL_Msk                (0x01UL << POSIF_PFLGE_WHESEL_Pos)                      /*!< POSIF PFLGE: WHESEL Mask                */\r
+#define POSIF_PFLGE_HIESEL_Pos                18                                                      /*!< POSIF PFLGE: HIESEL Position            */\r
+#define POSIF_PFLGE_HIESEL_Msk                (0x01UL << POSIF_PFLGE_HIESEL_Pos)                      /*!< POSIF PFLGE: HIESEL Mask                */\r
+#define POSIF_PFLGE_MSTSEL_Pos                20                                                      /*!< POSIF PFLGE: MSTSEL Position            */\r
+#define POSIF_PFLGE_MSTSEL_Msk                (0x01UL << POSIF_PFLGE_MSTSEL_Pos)                      /*!< POSIF PFLGE: MSTSEL Mask                */\r
+#define POSIF_PFLGE_INDSEL_Pos                24                                                      /*!< POSIF PFLGE: INDSEL Position            */\r
+#define POSIF_PFLGE_INDSEL_Msk                (0x01UL << POSIF_PFLGE_INDSEL_Pos)                      /*!< POSIF PFLGE: INDSEL Mask                */\r
+#define POSIF_PFLGE_ERRSEL_Pos                25                                                      /*!< POSIF PFLGE: ERRSEL Position            */\r
+#define POSIF_PFLGE_ERRSEL_Msk                (0x01UL << POSIF_PFLGE_ERRSEL_Pos)                      /*!< POSIF PFLGE: ERRSEL Mask                */\r
+#define POSIF_PFLGE_CNTSEL_Pos                26                                                      /*!< POSIF PFLGE: CNTSEL Position            */\r
+#define POSIF_PFLGE_CNTSEL_Msk                (0x01UL << POSIF_PFLGE_CNTSEL_Pos)                      /*!< POSIF PFLGE: CNTSEL Mask                */\r
+#define POSIF_PFLGE_DIRSEL_Pos                27                                                      /*!< POSIF PFLGE: DIRSEL Position            */\r
+#define POSIF_PFLGE_DIRSEL_Msk                (0x01UL << POSIF_PFLGE_DIRSEL_Pos)                      /*!< POSIF PFLGE: DIRSEL Mask                */\r
+#define POSIF_PFLGE_PCLSEL_Pos                28                                                      /*!< POSIF PFLGE: PCLSEL Position            */\r
+#define POSIF_PFLGE_PCLSEL_Msk                (0x01UL << POSIF_PFLGE_PCLSEL_Pos)                      /*!< POSIF PFLGE: PCLSEL Mask                */\r
+\r
+/* ---------------------------------  POSIF_SPFLG  -------------------------------- */\r
+#define POSIF_SPFLG_SCHE_Pos                  0                                                       /*!< POSIF SPFLG: SCHE Position              */\r
+#define POSIF_SPFLG_SCHE_Msk                  (0x01UL << POSIF_SPFLG_SCHE_Pos)                        /*!< POSIF SPFLG: SCHE Mask                  */\r
+#define POSIF_SPFLG_SWHE_Pos                  1                                                       /*!< POSIF SPFLG: SWHE Position              */\r
+#define POSIF_SPFLG_SWHE_Msk                  (0x01UL << POSIF_SPFLG_SWHE_Pos)                        /*!< POSIF SPFLG: SWHE Mask                  */\r
+#define POSIF_SPFLG_SHIE_Pos                  2                                                       /*!< POSIF SPFLG: SHIE Position              */\r
+#define POSIF_SPFLG_SHIE_Msk                  (0x01UL << POSIF_SPFLG_SHIE_Pos)                        /*!< POSIF SPFLG: SHIE Mask                  */\r
+#define POSIF_SPFLG_SMST_Pos                  4                                                       /*!< POSIF SPFLG: SMST Position              */\r
+#define POSIF_SPFLG_SMST_Msk                  (0x01UL << POSIF_SPFLG_SMST_Pos)                        /*!< POSIF SPFLG: SMST Mask                  */\r
+#define POSIF_SPFLG_SINDX_Pos                 8                                                       /*!< POSIF SPFLG: SINDX Position             */\r
+#define POSIF_SPFLG_SINDX_Msk                 (0x01UL << POSIF_SPFLG_SINDX_Pos)                       /*!< POSIF SPFLG: SINDX Mask                 */\r
+#define POSIF_SPFLG_SERR_Pos                  9                                                       /*!< POSIF SPFLG: SERR Position              */\r
+#define POSIF_SPFLG_SERR_Msk                  (0x01UL << POSIF_SPFLG_SERR_Pos)                        /*!< POSIF SPFLG: SERR Mask                  */\r
+#define POSIF_SPFLG_SCNT_Pos                  10                                                      /*!< POSIF SPFLG: SCNT Position              */\r
+#define POSIF_SPFLG_SCNT_Msk                  (0x01UL << POSIF_SPFLG_SCNT_Pos)                        /*!< POSIF SPFLG: SCNT Mask                  */\r
+#define POSIF_SPFLG_SDIR_Pos                  11                                                      /*!< POSIF SPFLG: SDIR Position              */\r
+#define POSIF_SPFLG_SDIR_Msk                  (0x01UL << POSIF_SPFLG_SDIR_Pos)                        /*!< POSIF SPFLG: SDIR Mask                  */\r
+#define POSIF_SPFLG_SPCLK_Pos                 12                                                      /*!< POSIF SPFLG: SPCLK Position             */\r
+#define POSIF_SPFLG_SPCLK_Msk                 (0x01UL << POSIF_SPFLG_SPCLK_Pos)                       /*!< POSIF SPFLG: SPCLK Mask                 */\r
+\r
+/* ---------------------------------  POSIF_RPFLG  -------------------------------- */\r
+#define POSIF_RPFLG_RCHE_Pos                  0                                                       /*!< POSIF RPFLG: RCHE Position              */\r
+#define POSIF_RPFLG_RCHE_Msk                  (0x01UL << POSIF_RPFLG_RCHE_Pos)                        /*!< POSIF RPFLG: RCHE Mask                  */\r
+#define POSIF_RPFLG_RWHE_Pos                  1                                                       /*!< POSIF RPFLG: RWHE Position              */\r
+#define POSIF_RPFLG_RWHE_Msk                  (0x01UL << POSIF_RPFLG_RWHE_Pos)                        /*!< POSIF RPFLG: RWHE Mask                  */\r
+#define POSIF_RPFLG_RHIE_Pos                  2                                                       /*!< POSIF RPFLG: RHIE Position              */\r
+#define POSIF_RPFLG_RHIE_Msk                  (0x01UL << POSIF_RPFLG_RHIE_Pos)                        /*!< POSIF RPFLG: RHIE Mask                  */\r
+#define POSIF_RPFLG_RMST_Pos                  4                                                       /*!< POSIF RPFLG: RMST Position              */\r
+#define POSIF_RPFLG_RMST_Msk                  (0x01UL << POSIF_RPFLG_RMST_Pos)                        /*!< POSIF RPFLG: RMST Mask                  */\r
+#define POSIF_RPFLG_RINDX_Pos                 8                                                       /*!< POSIF RPFLG: RINDX Position             */\r
+#define POSIF_RPFLG_RINDX_Msk                 (0x01UL << POSIF_RPFLG_RINDX_Pos)                       /*!< POSIF RPFLG: RINDX Mask                 */\r
+#define POSIF_RPFLG_RERR_Pos                  9                                                       /*!< POSIF RPFLG: RERR Position              */\r
+#define POSIF_RPFLG_RERR_Msk                  (0x01UL << POSIF_RPFLG_RERR_Pos)                        /*!< POSIF RPFLG: RERR Mask                  */\r
+#define POSIF_RPFLG_RCNT_Pos                  10                                                      /*!< POSIF RPFLG: RCNT Position              */\r
+#define POSIF_RPFLG_RCNT_Msk                  (0x01UL << POSIF_RPFLG_RCNT_Pos)                        /*!< POSIF RPFLG: RCNT Mask                  */\r
+#define POSIF_RPFLG_RDIR_Pos                  11                                                      /*!< POSIF RPFLG: RDIR Position              */\r
+#define POSIF_RPFLG_RDIR_Msk                  (0x01UL << POSIF_RPFLG_RDIR_Pos)                        /*!< POSIF RPFLG: RDIR Mask                  */\r
+#define POSIF_RPFLG_RPCLK_Pos                 12                                                      /*!< POSIF RPFLG: RPCLK Position             */\r
+#define POSIF_RPFLG_RPCLK_Msk                 (0x01UL << POSIF_RPFLG_RPCLK_Pos)                       /*!< POSIF RPFLG: RPCLK Mask                 */\r
+\r
+/* ---------------------------------  POSIF_PDBG  --------------------------------- */\r
+#define POSIF_PDBG_QCSV_Pos                   0                                                       /*!< POSIF PDBG: QCSV Position               */\r
+#define POSIF_PDBG_QCSV_Msk                   (0x03UL << POSIF_PDBG_QCSV_Pos)                         /*!< POSIF PDBG: QCSV Mask                   */\r
+#define POSIF_PDBG_QPSV_Pos                   2                                                       /*!< POSIF PDBG: QPSV Position               */\r
+#define POSIF_PDBG_QPSV_Msk                   (0x03UL << POSIF_PDBG_QPSV_Pos)                         /*!< POSIF PDBG: QPSV Mask                   */\r
+#define POSIF_PDBG_IVAL_Pos                   4                                                       /*!< POSIF PDBG: IVAL Position               */\r
+#define POSIF_PDBG_IVAL_Msk                   (0x01UL << POSIF_PDBG_IVAL_Pos)                         /*!< POSIF PDBG: IVAL Mask                   */\r
+#define POSIF_PDBG_HSP_Pos                    5                                                       /*!< POSIF PDBG: HSP Position                */\r
+#define POSIF_PDBG_HSP_Msk                    (0x07UL << POSIF_PDBG_HSP_Pos)                          /*!< POSIF PDBG: HSP Mask                    */\r
+#define POSIF_PDBG_LPP0_Pos                   8                                                       /*!< POSIF PDBG: LPP0 Position               */\r
+#define POSIF_PDBG_LPP0_Msk                   (0x3fUL << POSIF_PDBG_LPP0_Pos)                         /*!< POSIF PDBG: LPP0 Mask                   */\r
+#define POSIF_PDBG_LPP1_Pos                   16                                                      /*!< POSIF PDBG: LPP1 Position               */\r
+#define POSIF_PDBG_LPP1_Msk                   (0x3fUL << POSIF_PDBG_LPP1_Pos)                         /*!< POSIF PDBG: LPP1 Mask                   */\r
+#define POSIF_PDBG_LPP2_Pos                   22                                                      /*!< POSIF PDBG: LPP2 Position               */\r
+#define POSIF_PDBG_LPP2_Msk                   (0x3fUL << POSIF_PDBG_LPP2_Pos)                         /*!< POSIF PDBG: LPP2 Mask                   */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT0' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT0_OUT  --------------------------------- */\r
+#define PORT0_OUT_P0_Pos                      0                                                       /*!< PORT0 OUT: P0 Position                  */\r
+#define PORT0_OUT_P0_Msk                      (0x01UL << PORT0_OUT_P0_Pos)                            /*!< PORT0 OUT: P0 Mask                      */\r
+#define PORT0_OUT_P1_Pos                      1                                                       /*!< PORT0 OUT: P1 Position                  */\r
+#define PORT0_OUT_P1_Msk                      (0x01UL << PORT0_OUT_P1_Pos)                            /*!< PORT0 OUT: P1 Mask                      */\r
+#define PORT0_OUT_P2_Pos                      2                                                       /*!< PORT0 OUT: P2 Position                  */\r
+#define PORT0_OUT_P2_Msk                      (0x01UL << PORT0_OUT_P2_Pos)                            /*!< PORT0 OUT: P2 Mask                      */\r
+#define PORT0_OUT_P3_Pos                      3                                                       /*!< PORT0 OUT: P3 Position                  */\r
+#define PORT0_OUT_P3_Msk                      (0x01UL << PORT0_OUT_P3_Pos)                            /*!< PORT0 OUT: P3 Mask                      */\r
+#define PORT0_OUT_P4_Pos                      4                                                       /*!< PORT0 OUT: P4 Position                  */\r
+#define PORT0_OUT_P4_Msk                      (0x01UL << PORT0_OUT_P4_Pos)                            /*!< PORT0 OUT: P4 Mask                      */\r
+#define PORT0_OUT_P5_Pos                      5                                                       /*!< PORT0 OUT: P5 Position                  */\r
+#define PORT0_OUT_P5_Msk                      (0x01UL << PORT0_OUT_P5_Pos)                            /*!< PORT0 OUT: P5 Mask                      */\r
+#define PORT0_OUT_P6_Pos                      6                                                       /*!< PORT0 OUT: P6 Position                  */\r
+#define PORT0_OUT_P6_Msk                      (0x01UL << PORT0_OUT_P6_Pos)                            /*!< PORT0 OUT: P6 Mask                      */\r
+#define PORT0_OUT_P7_Pos                      7                                                       /*!< PORT0 OUT: P7 Position                  */\r
+#define PORT0_OUT_P7_Msk                      (0x01UL << PORT0_OUT_P7_Pos)                            /*!< PORT0 OUT: P7 Mask                      */\r
+#define PORT0_OUT_P8_Pos                      8                                                       /*!< PORT0 OUT: P8 Position                  */\r
+#define PORT0_OUT_P8_Msk                      (0x01UL << PORT0_OUT_P8_Pos)                            /*!< PORT0 OUT: P8 Mask                      */\r
+#define PORT0_OUT_P9_Pos                      9                                                       /*!< PORT0 OUT: P9 Position                  */\r
+#define PORT0_OUT_P9_Msk                      (0x01UL << PORT0_OUT_P9_Pos)                            /*!< PORT0 OUT: P9 Mask                      */\r
+#define PORT0_OUT_P10_Pos                     10                                                      /*!< PORT0 OUT: P10 Position                 */\r
+#define PORT0_OUT_P10_Msk                     (0x01UL << PORT0_OUT_P10_Pos)                           /*!< PORT0 OUT: P10 Mask                     */\r
+#define PORT0_OUT_P11_Pos                     11                                                      /*!< PORT0 OUT: P11 Position                 */\r
+#define PORT0_OUT_P11_Msk                     (0x01UL << PORT0_OUT_P11_Pos)                           /*!< PORT0 OUT: P11 Mask                     */\r
+#define PORT0_OUT_P12_Pos                     12                                                      /*!< PORT0 OUT: P12 Position                 */\r
+#define PORT0_OUT_P12_Msk                     (0x01UL << PORT0_OUT_P12_Pos)                           /*!< PORT0 OUT: P12 Mask                     */\r
+#define PORT0_OUT_P13_Pos                     13                                                      /*!< PORT0 OUT: P13 Position                 */\r
+#define PORT0_OUT_P13_Msk                     (0x01UL << PORT0_OUT_P13_Pos)                           /*!< PORT0 OUT: P13 Mask                     */\r
+#define PORT0_OUT_P14_Pos                     14                                                      /*!< PORT0 OUT: P14 Position                 */\r
+#define PORT0_OUT_P14_Msk                     (0x01UL << PORT0_OUT_P14_Pos)                           /*!< PORT0 OUT: P14 Mask                     */\r
+#define PORT0_OUT_P15_Pos                     15                                                      /*!< PORT0 OUT: P15 Position                 */\r
+#define PORT0_OUT_P15_Msk                     (0x01UL << PORT0_OUT_P15_Pos)                           /*!< PORT0 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT0_OMR  --------------------------------- */\r
+#define PORT0_OMR_PS0_Pos                     0                                                       /*!< PORT0 OMR: PS0 Position                 */\r
+#define PORT0_OMR_PS0_Msk                     (0x01UL << PORT0_OMR_PS0_Pos)                           /*!< PORT0 OMR: PS0 Mask                     */\r
+#define PORT0_OMR_PS1_Pos                     1                                                       /*!< PORT0 OMR: PS1 Position                 */\r
+#define PORT0_OMR_PS1_Msk                     (0x01UL << PORT0_OMR_PS1_Pos)                           /*!< PORT0 OMR: PS1 Mask                     */\r
+#define PORT0_OMR_PS2_Pos                     2                                                       /*!< PORT0 OMR: PS2 Position                 */\r
+#define PORT0_OMR_PS2_Msk                     (0x01UL << PORT0_OMR_PS2_Pos)                           /*!< PORT0 OMR: PS2 Mask                     */\r
+#define PORT0_OMR_PS3_Pos                     3                                                       /*!< PORT0 OMR: PS3 Position                 */\r
+#define PORT0_OMR_PS3_Msk                     (0x01UL << PORT0_OMR_PS3_Pos)                           /*!< PORT0 OMR: PS3 Mask                     */\r
+#define PORT0_OMR_PS4_Pos                     4                                                       /*!< PORT0 OMR: PS4 Position                 */\r
+#define PORT0_OMR_PS4_Msk                     (0x01UL << PORT0_OMR_PS4_Pos)                           /*!< PORT0 OMR: PS4 Mask                     */\r
+#define PORT0_OMR_PS5_Pos                     5                                                       /*!< PORT0 OMR: PS5 Position                 */\r
+#define PORT0_OMR_PS5_Msk                     (0x01UL << PORT0_OMR_PS5_Pos)                           /*!< PORT0 OMR: PS5 Mask                     */\r
+#define PORT0_OMR_PS6_Pos                     6                                                       /*!< PORT0 OMR: PS6 Position                 */\r
+#define PORT0_OMR_PS6_Msk                     (0x01UL << PORT0_OMR_PS6_Pos)                           /*!< PORT0 OMR: PS6 Mask                     */\r
+#define PORT0_OMR_PS7_Pos                     7                                                       /*!< PORT0 OMR: PS7 Position                 */\r
+#define PORT0_OMR_PS7_Msk                     (0x01UL << PORT0_OMR_PS7_Pos)                           /*!< PORT0 OMR: PS7 Mask                     */\r
+#define PORT0_OMR_PS8_Pos                     8                                                       /*!< PORT0 OMR: PS8 Position                 */\r
+#define PORT0_OMR_PS8_Msk                     (0x01UL << PORT0_OMR_PS8_Pos)                           /*!< PORT0 OMR: PS8 Mask                     */\r
+#define PORT0_OMR_PS9_Pos                     9                                                       /*!< PORT0 OMR: PS9 Position                 */\r
+#define PORT0_OMR_PS9_Msk                     (0x01UL << PORT0_OMR_PS9_Pos)                           /*!< PORT0 OMR: PS9 Mask                     */\r
+#define PORT0_OMR_PS10_Pos                    10                                                      /*!< PORT0 OMR: PS10 Position                */\r
+#define PORT0_OMR_PS10_Msk                    (0x01UL << PORT0_OMR_PS10_Pos)                          /*!< PORT0 OMR: PS10 Mask                    */\r
+#define PORT0_OMR_PS11_Pos                    11                                                      /*!< PORT0 OMR: PS11 Position                */\r
+#define PORT0_OMR_PS11_Msk                    (0x01UL << PORT0_OMR_PS11_Pos)                          /*!< PORT0 OMR: PS11 Mask                    */\r
+#define PORT0_OMR_PS12_Pos                    12                                                      /*!< PORT0 OMR: PS12 Position                */\r
+#define PORT0_OMR_PS12_Msk                    (0x01UL << PORT0_OMR_PS12_Pos)                          /*!< PORT0 OMR: PS12 Mask                    */\r
+#define PORT0_OMR_PS13_Pos                    13                                                      /*!< PORT0 OMR: PS13 Position                */\r
+#define PORT0_OMR_PS13_Msk                    (0x01UL << PORT0_OMR_PS13_Pos)                          /*!< PORT0 OMR: PS13 Mask                    */\r
+#define PORT0_OMR_PS14_Pos                    14                                                      /*!< PORT0 OMR: PS14 Position                */\r
+#define PORT0_OMR_PS14_Msk                    (0x01UL << PORT0_OMR_PS14_Pos)                          /*!< PORT0 OMR: PS14 Mask                    */\r
+#define PORT0_OMR_PS15_Pos                    15                                                      /*!< PORT0 OMR: PS15 Position                */\r
+#define PORT0_OMR_PS15_Msk                    (0x01UL << PORT0_OMR_PS15_Pos)                          /*!< PORT0 OMR: PS15 Mask                    */\r
+#define PORT0_OMR_PR0_Pos                     16                                                      /*!< PORT0 OMR: PR0 Position                 */\r
+#define PORT0_OMR_PR0_Msk                     (0x01UL << PORT0_OMR_PR0_Pos)                           /*!< PORT0 OMR: PR0 Mask                     */\r
+#define PORT0_OMR_PR1_Pos                     17                                                      /*!< PORT0 OMR: PR1 Position                 */\r
+#define PORT0_OMR_PR1_Msk                     (0x01UL << PORT0_OMR_PR1_Pos)                           /*!< PORT0 OMR: PR1 Mask                     */\r
+#define PORT0_OMR_PR2_Pos                     18                                                      /*!< PORT0 OMR: PR2 Position                 */\r
+#define PORT0_OMR_PR2_Msk                     (0x01UL << PORT0_OMR_PR2_Pos)                           /*!< PORT0 OMR: PR2 Mask                     */\r
+#define PORT0_OMR_PR3_Pos                     19                                                      /*!< PORT0 OMR: PR3 Position                 */\r
+#define PORT0_OMR_PR3_Msk                     (0x01UL << PORT0_OMR_PR3_Pos)                           /*!< PORT0 OMR: PR3 Mask                     */\r
+#define PORT0_OMR_PR4_Pos                     20                                                      /*!< PORT0 OMR: PR4 Position                 */\r
+#define PORT0_OMR_PR4_Msk                     (0x01UL << PORT0_OMR_PR4_Pos)                           /*!< PORT0 OMR: PR4 Mask                     */\r
+#define PORT0_OMR_PR5_Pos                     21                                                      /*!< PORT0 OMR: PR5 Position                 */\r
+#define PORT0_OMR_PR5_Msk                     (0x01UL << PORT0_OMR_PR5_Pos)                           /*!< PORT0 OMR: PR5 Mask                     */\r
+#define PORT0_OMR_PR6_Pos                     22                                                      /*!< PORT0 OMR: PR6 Position                 */\r
+#define PORT0_OMR_PR6_Msk                     (0x01UL << PORT0_OMR_PR6_Pos)                           /*!< PORT0 OMR: PR6 Mask                     */\r
+#define PORT0_OMR_PR7_Pos                     23                                                      /*!< PORT0 OMR: PR7 Position                 */\r
+#define PORT0_OMR_PR7_Msk                     (0x01UL << PORT0_OMR_PR7_Pos)                           /*!< PORT0 OMR: PR7 Mask                     */\r
+#define PORT0_OMR_PR8_Pos                     24                                                      /*!< PORT0 OMR: PR8 Position                 */\r
+#define PORT0_OMR_PR8_Msk                     (0x01UL << PORT0_OMR_PR8_Pos)                           /*!< PORT0 OMR: PR8 Mask                     */\r
+#define PORT0_OMR_PR9_Pos                     25                                                      /*!< PORT0 OMR: PR9 Position                 */\r
+#define PORT0_OMR_PR9_Msk                     (0x01UL << PORT0_OMR_PR9_Pos)                           /*!< PORT0 OMR: PR9 Mask                     */\r
+#define PORT0_OMR_PR10_Pos                    26                                                      /*!< PORT0 OMR: PR10 Position                */\r
+#define PORT0_OMR_PR10_Msk                    (0x01UL << PORT0_OMR_PR10_Pos)                          /*!< PORT0 OMR: PR10 Mask                    */\r
+#define PORT0_OMR_PR11_Pos                    27                                                      /*!< PORT0 OMR: PR11 Position                */\r
+#define PORT0_OMR_PR11_Msk                    (0x01UL << PORT0_OMR_PR11_Pos)                          /*!< PORT0 OMR: PR11 Mask                    */\r
+#define PORT0_OMR_PR12_Pos                    28                                                      /*!< PORT0 OMR: PR12 Position                */\r
+#define PORT0_OMR_PR12_Msk                    (0x01UL << PORT0_OMR_PR12_Pos)                          /*!< PORT0 OMR: PR12 Mask                    */\r
+#define PORT0_OMR_PR13_Pos                    29                                                      /*!< PORT0 OMR: PR13 Position                */\r
+#define PORT0_OMR_PR13_Msk                    (0x01UL << PORT0_OMR_PR13_Pos)                          /*!< PORT0 OMR: PR13 Mask                    */\r
+#define PORT0_OMR_PR14_Pos                    30                                                      /*!< PORT0 OMR: PR14 Position                */\r
+#define PORT0_OMR_PR14_Msk                    (0x01UL << PORT0_OMR_PR14_Pos)                          /*!< PORT0 OMR: PR14 Mask                    */\r
+#define PORT0_OMR_PR15_Pos                    31                                                      /*!< PORT0 OMR: PR15 Position                */\r
+#define PORT0_OMR_PR15_Msk                    (0x01UL << PORT0_OMR_PR15_Pos)                          /*!< PORT0 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT0_IOCR0  -------------------------------- */\r
+#define PORT0_IOCR0_PC0_Pos                   3                                                       /*!< PORT0 IOCR0: PC0 Position               */\r
+#define PORT0_IOCR0_PC0_Msk                   (0x1fUL << PORT0_IOCR0_PC0_Pos)                         /*!< PORT0 IOCR0: PC0 Mask                   */\r
+#define PORT0_IOCR0_PC1_Pos                   11                                                      /*!< PORT0 IOCR0: PC1 Position               */\r
+#define PORT0_IOCR0_PC1_Msk                   (0x1fUL << PORT0_IOCR0_PC1_Pos)                         /*!< PORT0 IOCR0: PC1 Mask                   */\r
+#define PORT0_IOCR0_PC2_Pos                   19                                                      /*!< PORT0 IOCR0: PC2 Position               */\r
+#define PORT0_IOCR0_PC2_Msk                   (0x1fUL << PORT0_IOCR0_PC2_Pos)                         /*!< PORT0 IOCR0: PC2 Mask                   */\r
+#define PORT0_IOCR0_PC3_Pos                   27                                                      /*!< PORT0 IOCR0: PC3 Position               */\r
+#define PORT0_IOCR0_PC3_Msk                   (0x1fUL << PORT0_IOCR0_PC3_Pos)                         /*!< PORT0 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_IOCR4  -------------------------------- */\r
+#define PORT0_IOCR4_PC4_Pos                   3                                                       /*!< PORT0 IOCR4: PC4 Position               */\r
+#define PORT0_IOCR4_PC4_Msk                   (0x1fUL << PORT0_IOCR4_PC4_Pos)                         /*!< PORT0 IOCR4: PC4 Mask                   */\r
+#define PORT0_IOCR4_PC5_Pos                   11                                                      /*!< PORT0 IOCR4: PC5 Position               */\r
+#define PORT0_IOCR4_PC5_Msk                   (0x1fUL << PORT0_IOCR4_PC5_Pos)                         /*!< PORT0 IOCR4: PC5 Mask                   */\r
+#define PORT0_IOCR4_PC6_Pos                   19                                                      /*!< PORT0 IOCR4: PC6 Position               */\r
+#define PORT0_IOCR4_PC6_Msk                   (0x1fUL << PORT0_IOCR4_PC6_Pos)                         /*!< PORT0 IOCR4: PC6 Mask                   */\r
+#define PORT0_IOCR4_PC7_Pos                   27                                                      /*!< PORT0 IOCR4: PC7 Position               */\r
+#define PORT0_IOCR4_PC7_Msk                   (0x1fUL << PORT0_IOCR4_PC7_Pos)                         /*!< PORT0 IOCR4: PC7 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_IOCR8  -------------------------------- */\r
+#define PORT0_IOCR8_PC8_Pos                   3                                                       /*!< PORT0 IOCR8: PC8 Position               */\r
+#define PORT0_IOCR8_PC8_Msk                   (0x1fUL << PORT0_IOCR8_PC8_Pos)                         /*!< PORT0 IOCR8: PC8 Mask                   */\r
+#define PORT0_IOCR8_PC9_Pos                   11                                                      /*!< PORT0 IOCR8: PC9 Position               */\r
+#define PORT0_IOCR8_PC9_Msk                   (0x1fUL << PORT0_IOCR8_PC9_Pos)                         /*!< PORT0 IOCR8: PC9 Mask                   */\r
+#define PORT0_IOCR8_PC10_Pos                  19                                                      /*!< PORT0 IOCR8: PC10 Position              */\r
+#define PORT0_IOCR8_PC10_Msk                  (0x1fUL << PORT0_IOCR8_PC10_Pos)                        /*!< PORT0 IOCR8: PC10 Mask                  */\r
+#define PORT0_IOCR8_PC11_Pos                  27                                                      /*!< PORT0 IOCR8: PC11 Position              */\r
+#define PORT0_IOCR8_PC11_Msk                  (0x1fUL << PORT0_IOCR8_PC11_Pos)                        /*!< PORT0 IOCR8: PC11 Mask                  */\r
+\r
+/* --------------------------------  PORT0_IOCR12  -------------------------------- */\r
+#define PORT0_IOCR12_PC12_Pos                 3                                                       /*!< PORT0 IOCR12: PC12 Position             */\r
+#define PORT0_IOCR12_PC12_Msk                 (0x1fUL << PORT0_IOCR12_PC12_Pos)                       /*!< PORT0 IOCR12: PC12 Mask                 */\r
+#define PORT0_IOCR12_PC13_Pos                 11                                                      /*!< PORT0 IOCR12: PC13 Position             */\r
+#define PORT0_IOCR12_PC13_Msk                 (0x1fUL << PORT0_IOCR12_PC13_Pos)                       /*!< PORT0 IOCR12: PC13 Mask                 */\r
+#define PORT0_IOCR12_PC14_Pos                 19                                                      /*!< PORT0 IOCR12: PC14 Position             */\r
+#define PORT0_IOCR12_PC14_Msk                 (0x1fUL << PORT0_IOCR12_PC14_Pos)                       /*!< PORT0 IOCR12: PC14 Mask                 */\r
+#define PORT0_IOCR12_PC15_Pos                 27                                                      /*!< PORT0 IOCR12: PC15 Position             */\r
+#define PORT0_IOCR12_PC15_Msk                 (0x1fUL << PORT0_IOCR12_PC15_Pos)                       /*!< PORT0 IOCR12: PC15 Mask                 */\r
+\r
+/* ----------------------------------  PORT0_IN  ---------------------------------- */\r
+#define PORT0_IN_P0_Pos                       0                                                       /*!< PORT0 IN: P0 Position                   */\r
+#define PORT0_IN_P0_Msk                       (0x01UL << PORT0_IN_P0_Pos)                             /*!< PORT0 IN: P0 Mask                       */\r
+#define PORT0_IN_P1_Pos                       1                                                       /*!< PORT0 IN: P1 Position                   */\r
+#define PORT0_IN_P1_Msk                       (0x01UL << PORT0_IN_P1_Pos)                             /*!< PORT0 IN: P1 Mask                       */\r
+#define PORT0_IN_P2_Pos                       2                                                       /*!< PORT0 IN: P2 Position                   */\r
+#define PORT0_IN_P2_Msk                       (0x01UL << PORT0_IN_P2_Pos)                             /*!< PORT0 IN: P2 Mask                       */\r
+#define PORT0_IN_P3_Pos                       3                                                       /*!< PORT0 IN: P3 Position                   */\r
+#define PORT0_IN_P3_Msk                       (0x01UL << PORT0_IN_P3_Pos)                             /*!< PORT0 IN: P3 Mask                       */\r
+#define PORT0_IN_P4_Pos                       4                                                       /*!< PORT0 IN: P4 Position                   */\r
+#define PORT0_IN_P4_Msk                       (0x01UL << PORT0_IN_P4_Pos)                             /*!< PORT0 IN: P4 Mask                       */\r
+#define PORT0_IN_P5_Pos                       5                                                       /*!< PORT0 IN: P5 Position                   */\r
+#define PORT0_IN_P5_Msk                       (0x01UL << PORT0_IN_P5_Pos)                             /*!< PORT0 IN: P5 Mask                       */\r
+#define PORT0_IN_P6_Pos                       6                                                       /*!< PORT0 IN: P6 Position                   */\r
+#define PORT0_IN_P6_Msk                       (0x01UL << PORT0_IN_P6_Pos)                             /*!< PORT0 IN: P6 Mask                       */\r
+#define PORT0_IN_P7_Pos                       7                                                       /*!< PORT0 IN: P7 Position                   */\r
+#define PORT0_IN_P7_Msk                       (0x01UL << PORT0_IN_P7_Pos)                             /*!< PORT0 IN: P7 Mask                       */\r
+#define PORT0_IN_P8_Pos                       8                                                       /*!< PORT0 IN: P8 Position                   */\r
+#define PORT0_IN_P8_Msk                       (0x01UL << PORT0_IN_P8_Pos)                             /*!< PORT0 IN: P8 Mask                       */\r
+#define PORT0_IN_P9_Pos                       9                                                       /*!< PORT0 IN: P9 Position                   */\r
+#define PORT0_IN_P9_Msk                       (0x01UL << PORT0_IN_P9_Pos)                             /*!< PORT0 IN: P9 Mask                       */\r
+#define PORT0_IN_P10_Pos                      10                                                      /*!< PORT0 IN: P10 Position                  */\r
+#define PORT0_IN_P10_Msk                      (0x01UL << PORT0_IN_P10_Pos)                            /*!< PORT0 IN: P10 Mask                      */\r
+#define PORT0_IN_P11_Pos                      11                                                      /*!< PORT0 IN: P11 Position                  */\r
+#define PORT0_IN_P11_Msk                      (0x01UL << PORT0_IN_P11_Pos)                            /*!< PORT0 IN: P11 Mask                      */\r
+#define PORT0_IN_P12_Pos                      12                                                      /*!< PORT0 IN: P12 Position                  */\r
+#define PORT0_IN_P12_Msk                      (0x01UL << PORT0_IN_P12_Pos)                            /*!< PORT0 IN: P12 Mask                      */\r
+#define PORT0_IN_P13_Pos                      13                                                      /*!< PORT0 IN: P13 Position                  */\r
+#define PORT0_IN_P13_Msk                      (0x01UL << PORT0_IN_P13_Pos)                            /*!< PORT0 IN: P13 Mask                      */\r
+#define PORT0_IN_P14_Pos                      14                                                      /*!< PORT0 IN: P14 Position                  */\r
+#define PORT0_IN_P14_Msk                      (0x01UL << PORT0_IN_P14_Pos)                            /*!< PORT0 IN: P14 Mask                      */\r
+#define PORT0_IN_P15_Pos                      15                                                      /*!< PORT0 IN: P15 Position                  */\r
+#define PORT0_IN_P15_Msk                      (0x01UL << PORT0_IN_P15_Pos)                            /*!< PORT0 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT0_PDR0  --------------------------------- */\r
+#define PORT0_PDR0_PD0_Pos                    0                                                       /*!< PORT0 PDR0: PD0 Position                */\r
+#define PORT0_PDR0_PD0_Msk                    (0x07UL << PORT0_PDR0_PD0_Pos)                          /*!< PORT0 PDR0: PD0 Mask                    */\r
+#define PORT0_PDR0_PD1_Pos                    4                                                       /*!< PORT0 PDR0: PD1 Position                */\r
+#define PORT0_PDR0_PD1_Msk                    (0x07UL << PORT0_PDR0_PD1_Pos)                          /*!< PORT0 PDR0: PD1 Mask                    */\r
+#define PORT0_PDR0_PD2_Pos                    8                                                       /*!< PORT0 PDR0: PD2 Position                */\r
+#define PORT0_PDR0_PD2_Msk                    (0x07UL << PORT0_PDR0_PD2_Pos)                          /*!< PORT0 PDR0: PD2 Mask                    */\r
+#define PORT0_PDR0_PD3_Pos                    12                                                      /*!< PORT0 PDR0: PD3 Position                */\r
+#define PORT0_PDR0_PD3_Msk                    (0x07UL << PORT0_PDR0_PD3_Pos)                          /*!< PORT0 PDR0: PD3 Mask                    */\r
+#define PORT0_PDR0_PD4_Pos                    16                                                      /*!< PORT0 PDR0: PD4 Position                */\r
+#define PORT0_PDR0_PD4_Msk                    (0x07UL << PORT0_PDR0_PD4_Pos)                          /*!< PORT0 PDR0: PD4 Mask                    */\r
+#define PORT0_PDR0_PD5_Pos                    20                                                      /*!< PORT0 PDR0: PD5 Position                */\r
+#define PORT0_PDR0_PD5_Msk                    (0x07UL << PORT0_PDR0_PD5_Pos)                          /*!< PORT0 PDR0: PD5 Mask                    */\r
+#define PORT0_PDR0_PD6_Pos                    24                                                      /*!< PORT0 PDR0: PD6 Position                */\r
+#define PORT0_PDR0_PD6_Msk                    (0x07UL << PORT0_PDR0_PD6_Pos)                          /*!< PORT0 PDR0: PD6 Mask                    */\r
+#define PORT0_PDR0_PD7_Pos                    28                                                      /*!< PORT0 PDR0: PD7 Position                */\r
+#define PORT0_PDR0_PD7_Msk                    (0x07UL << PORT0_PDR0_PD7_Pos)                          /*!< PORT0 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT0_PDR1  --------------------------------- */\r
+#define PORT0_PDR1_PD8_Pos                    0                                                       /*!< PORT0 PDR1: PD8 Position                */\r
+#define PORT0_PDR1_PD8_Msk                    (0x07UL << PORT0_PDR1_PD8_Pos)                          /*!< PORT0 PDR1: PD8 Mask                    */\r
+#define PORT0_PDR1_PD9_Pos                    4                                                       /*!< PORT0 PDR1: PD9 Position                */\r
+#define PORT0_PDR1_PD9_Msk                    (0x07UL << PORT0_PDR1_PD9_Pos)                          /*!< PORT0 PDR1: PD9 Mask                    */\r
+#define PORT0_PDR1_PD10_Pos                   8                                                       /*!< PORT0 PDR1: PD10 Position               */\r
+#define PORT0_PDR1_PD10_Msk                   (0x07UL << PORT0_PDR1_PD10_Pos)                         /*!< PORT0 PDR1: PD10 Mask                   */\r
+#define PORT0_PDR1_PD11_Pos                   12                                                      /*!< PORT0 PDR1: PD11 Position               */\r
+#define PORT0_PDR1_PD11_Msk                   (0x07UL << PORT0_PDR1_PD11_Pos)                         /*!< PORT0 PDR1: PD11 Mask                   */\r
+#define PORT0_PDR1_PD12_Pos                   16                                                      /*!< PORT0 PDR1: PD12 Position               */\r
+#define PORT0_PDR1_PD12_Msk                   (0x07UL << PORT0_PDR1_PD12_Pos)                         /*!< PORT0 PDR1: PD12 Mask                   */\r
+#define PORT0_PDR1_PD13_Pos                   20                                                      /*!< PORT0 PDR1: PD13 Position               */\r
+#define PORT0_PDR1_PD13_Msk                   (0x07UL << PORT0_PDR1_PD13_Pos)                         /*!< PORT0 PDR1: PD13 Mask                   */\r
+#define PORT0_PDR1_PD14_Pos                   24                                                      /*!< PORT0 PDR1: PD14 Position               */\r
+#define PORT0_PDR1_PD14_Msk                   (0x07UL << PORT0_PDR1_PD14_Pos)                         /*!< PORT0 PDR1: PD14 Mask                   */\r
+#define PORT0_PDR1_PD15_Pos                   28                                                      /*!< PORT0 PDR1: PD15 Position               */\r
+#define PORT0_PDR1_PD15_Msk                   (0x07UL << PORT0_PDR1_PD15_Pos)                         /*!< PORT0 PDR1: PD15 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_PDISC  -------------------------------- */\r
+#define PORT0_PDISC_PDIS0_Pos                 0                                                       /*!< PORT0 PDISC: PDIS0 Position             */\r
+#define PORT0_PDISC_PDIS0_Msk                 (0x01UL << PORT0_PDISC_PDIS0_Pos)                       /*!< PORT0 PDISC: PDIS0 Mask                 */\r
+#define PORT0_PDISC_PDIS1_Pos                 1                                                       /*!< PORT0 PDISC: PDIS1 Position             */\r
+#define PORT0_PDISC_PDIS1_Msk                 (0x01UL << PORT0_PDISC_PDIS1_Pos)                       /*!< PORT0 PDISC: PDIS1 Mask                 */\r
+#define PORT0_PDISC_PDIS2_Pos                 2                                                       /*!< PORT0 PDISC: PDIS2 Position             */\r
+#define PORT0_PDISC_PDIS2_Msk                 (0x01UL << PORT0_PDISC_PDIS2_Pos)                       /*!< PORT0 PDISC: PDIS2 Mask                 */\r
+#define PORT0_PDISC_PDIS3_Pos                 3                                                       /*!< PORT0 PDISC: PDIS3 Position             */\r
+#define PORT0_PDISC_PDIS3_Msk                 (0x01UL << PORT0_PDISC_PDIS3_Pos)                       /*!< PORT0 PDISC: PDIS3 Mask                 */\r
+#define PORT0_PDISC_PDIS4_Pos                 4                                                       /*!< PORT0 PDISC: PDIS4 Position             */\r
+#define PORT0_PDISC_PDIS4_Msk                 (0x01UL << PORT0_PDISC_PDIS4_Pos)                       /*!< PORT0 PDISC: PDIS4 Mask                 */\r
+#define PORT0_PDISC_PDIS5_Pos                 5                                                       /*!< PORT0 PDISC: PDIS5 Position             */\r
+#define PORT0_PDISC_PDIS5_Msk                 (0x01UL << PORT0_PDISC_PDIS5_Pos)                       /*!< PORT0 PDISC: PDIS5 Mask                 */\r
+#define PORT0_PDISC_PDIS6_Pos                 6                                                       /*!< PORT0 PDISC: PDIS6 Position             */\r
+#define PORT0_PDISC_PDIS6_Msk                 (0x01UL << PORT0_PDISC_PDIS6_Pos)                       /*!< PORT0 PDISC: PDIS6 Mask                 */\r
+#define PORT0_PDISC_PDIS7_Pos                 7                                                       /*!< PORT0 PDISC: PDIS7 Position             */\r
+#define PORT0_PDISC_PDIS7_Msk                 (0x01UL << PORT0_PDISC_PDIS7_Pos)                       /*!< PORT0 PDISC: PDIS7 Mask                 */\r
+#define PORT0_PDISC_PDIS8_Pos                 8                                                       /*!< PORT0 PDISC: PDIS8 Position             */\r
+#define PORT0_PDISC_PDIS8_Msk                 (0x01UL << PORT0_PDISC_PDIS8_Pos)                       /*!< PORT0 PDISC: PDIS8 Mask                 */\r
+#define PORT0_PDISC_PDIS9_Pos                 9                                                       /*!< PORT0 PDISC: PDIS9 Position             */\r
+#define PORT0_PDISC_PDIS9_Msk                 (0x01UL << PORT0_PDISC_PDIS9_Pos)                       /*!< PORT0 PDISC: PDIS9 Mask                 */\r
+#define PORT0_PDISC_PDIS10_Pos                10                                                      /*!< PORT0 PDISC: PDIS10 Position            */\r
+#define PORT0_PDISC_PDIS10_Msk                (0x01UL << PORT0_PDISC_PDIS10_Pos)                      /*!< PORT0 PDISC: PDIS10 Mask                */\r
+#define PORT0_PDISC_PDIS11_Pos                11                                                      /*!< PORT0 PDISC: PDIS11 Position            */\r
+#define PORT0_PDISC_PDIS11_Msk                (0x01UL << PORT0_PDISC_PDIS11_Pos)                      /*!< PORT0 PDISC: PDIS11 Mask                */\r
+#define PORT0_PDISC_PDIS12_Pos                12                                                      /*!< PORT0 PDISC: PDIS12 Position            */\r
+#define PORT0_PDISC_PDIS12_Msk                (0x01UL << PORT0_PDISC_PDIS12_Pos)                      /*!< PORT0 PDISC: PDIS12 Mask                */\r
+#define PORT0_PDISC_PDIS13_Pos                13                                                      /*!< PORT0 PDISC: PDIS13 Position            */\r
+#define PORT0_PDISC_PDIS13_Msk                (0x01UL << PORT0_PDISC_PDIS13_Pos)                      /*!< PORT0 PDISC: PDIS13 Mask                */\r
+#define PORT0_PDISC_PDIS14_Pos                14                                                      /*!< PORT0 PDISC: PDIS14 Position            */\r
+#define PORT0_PDISC_PDIS14_Msk                (0x01UL << PORT0_PDISC_PDIS14_Pos)                      /*!< PORT0 PDISC: PDIS14 Mask                */\r
+#define PORT0_PDISC_PDIS15_Pos                15                                                      /*!< PORT0 PDISC: PDIS15 Position            */\r
+#define PORT0_PDISC_PDIS15_Msk                (0x01UL << PORT0_PDISC_PDIS15_Pos)                      /*!< PORT0 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT0_PPS  --------------------------------- */\r
+#define PORT0_PPS_PPS0_Pos                    0                                                       /*!< PORT0 PPS: PPS0 Position                */\r
+#define PORT0_PPS_PPS0_Msk                    (0x01UL << PORT0_PPS_PPS0_Pos)                          /*!< PORT0 PPS: PPS0 Mask                    */\r
+#define PORT0_PPS_PPS1_Pos                    1                                                       /*!< PORT0 PPS: PPS1 Position                */\r
+#define PORT0_PPS_PPS1_Msk                    (0x01UL << PORT0_PPS_PPS1_Pos)                          /*!< PORT0 PPS: PPS1 Mask                    */\r
+#define PORT0_PPS_PPS2_Pos                    2                                                       /*!< PORT0 PPS: PPS2 Position                */\r
+#define PORT0_PPS_PPS2_Msk                    (0x01UL << PORT0_PPS_PPS2_Pos)                          /*!< PORT0 PPS: PPS2 Mask                    */\r
+#define PORT0_PPS_PPS3_Pos                    3                                                       /*!< PORT0 PPS: PPS3 Position                */\r
+#define PORT0_PPS_PPS3_Msk                    (0x01UL << PORT0_PPS_PPS3_Pos)                          /*!< PORT0 PPS: PPS3 Mask                    */\r
+#define PORT0_PPS_PPS4_Pos                    4                                                       /*!< PORT0 PPS: PPS4 Position                */\r
+#define PORT0_PPS_PPS4_Msk                    (0x01UL << PORT0_PPS_PPS4_Pos)                          /*!< PORT0 PPS: PPS4 Mask                    */\r
+#define PORT0_PPS_PPS5_Pos                    5                                                       /*!< PORT0 PPS: PPS5 Position                */\r
+#define PORT0_PPS_PPS5_Msk                    (0x01UL << PORT0_PPS_PPS5_Pos)                          /*!< PORT0 PPS: PPS5 Mask                    */\r
+#define PORT0_PPS_PPS6_Pos                    6                                                       /*!< PORT0 PPS: PPS6 Position                */\r
+#define PORT0_PPS_PPS6_Msk                    (0x01UL << PORT0_PPS_PPS6_Pos)                          /*!< PORT0 PPS: PPS6 Mask                    */\r
+#define PORT0_PPS_PPS7_Pos                    7                                                       /*!< PORT0 PPS: PPS7 Position                */\r
+#define PORT0_PPS_PPS7_Msk                    (0x01UL << PORT0_PPS_PPS7_Pos)                          /*!< PORT0 PPS: PPS7 Mask                    */\r
+#define PORT0_PPS_PPS8_Pos                    8                                                       /*!< PORT0 PPS: PPS8 Position                */\r
+#define PORT0_PPS_PPS8_Msk                    (0x01UL << PORT0_PPS_PPS8_Pos)                          /*!< PORT0 PPS: PPS8 Mask                    */\r
+#define PORT0_PPS_PPS9_Pos                    9                                                       /*!< PORT0 PPS: PPS9 Position                */\r
+#define PORT0_PPS_PPS9_Msk                    (0x01UL << PORT0_PPS_PPS9_Pos)                          /*!< PORT0 PPS: PPS9 Mask                    */\r
+#define PORT0_PPS_PPS10_Pos                   10                                                      /*!< PORT0 PPS: PPS10 Position               */\r
+#define PORT0_PPS_PPS10_Msk                   (0x01UL << PORT0_PPS_PPS10_Pos)                         /*!< PORT0 PPS: PPS10 Mask                   */\r
+#define PORT0_PPS_PPS11_Pos                   11                                                      /*!< PORT0 PPS: PPS11 Position               */\r
+#define PORT0_PPS_PPS11_Msk                   (0x01UL << PORT0_PPS_PPS11_Pos)                         /*!< PORT0 PPS: PPS11 Mask                   */\r
+#define PORT0_PPS_PPS12_Pos                   12                                                      /*!< PORT0 PPS: PPS12 Position               */\r
+#define PORT0_PPS_PPS12_Msk                   (0x01UL << PORT0_PPS_PPS12_Pos)                         /*!< PORT0 PPS: PPS12 Mask                   */\r
+#define PORT0_PPS_PPS13_Pos                   13                                                      /*!< PORT0 PPS: PPS13 Position               */\r
+#define PORT0_PPS_PPS13_Msk                   (0x01UL << PORT0_PPS_PPS13_Pos)                         /*!< PORT0 PPS: PPS13 Mask                   */\r
+#define PORT0_PPS_PPS14_Pos                   14                                                      /*!< PORT0 PPS: PPS14 Position               */\r
+#define PORT0_PPS_PPS14_Msk                   (0x01UL << PORT0_PPS_PPS14_Pos)                         /*!< PORT0 PPS: PPS14 Mask                   */\r
+#define PORT0_PPS_PPS15_Pos                   15                                                      /*!< PORT0 PPS: PPS15 Position               */\r
+#define PORT0_PPS_PPS15_Msk                   (0x01UL << PORT0_PPS_PPS15_Pos)                         /*!< PORT0 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT0_HWSEL  -------------------------------- */\r
+#define PORT0_HWSEL_HW0_Pos                   0                                                       /*!< PORT0 HWSEL: HW0 Position               */\r
+#define PORT0_HWSEL_HW0_Msk                   (0x03UL << PORT0_HWSEL_HW0_Pos)                         /*!< PORT0 HWSEL: HW0 Mask                   */\r
+#define PORT0_HWSEL_HW1_Pos                   2                                                       /*!< PORT0 HWSEL: HW1 Position               */\r
+#define PORT0_HWSEL_HW1_Msk                   (0x03UL << PORT0_HWSEL_HW1_Pos)                         /*!< PORT0 HWSEL: HW1 Mask                   */\r
+#define PORT0_HWSEL_HW2_Pos                   4                                                       /*!< PORT0 HWSEL: HW2 Position               */\r
+#define PORT0_HWSEL_HW2_Msk                   (0x03UL << PORT0_HWSEL_HW2_Pos)                         /*!< PORT0 HWSEL: HW2 Mask                   */\r
+#define PORT0_HWSEL_HW3_Pos                   6                                                       /*!< PORT0 HWSEL: HW3 Position               */\r
+#define PORT0_HWSEL_HW3_Msk                   (0x03UL << PORT0_HWSEL_HW3_Pos)                         /*!< PORT0 HWSEL: HW3 Mask                   */\r
+#define PORT0_HWSEL_HW4_Pos                   8                                                       /*!< PORT0 HWSEL: HW4 Position               */\r
+#define PORT0_HWSEL_HW4_Msk                   (0x03UL << PORT0_HWSEL_HW4_Pos)                         /*!< PORT0 HWSEL: HW4 Mask                   */\r
+#define PORT0_HWSEL_HW5_Pos                   10                                                      /*!< PORT0 HWSEL: HW5 Position               */\r
+#define PORT0_HWSEL_HW5_Msk                   (0x03UL << PORT0_HWSEL_HW5_Pos)                         /*!< PORT0 HWSEL: HW5 Mask                   */\r
+#define PORT0_HWSEL_HW6_Pos                   12                                                      /*!< PORT0 HWSEL: HW6 Position               */\r
+#define PORT0_HWSEL_HW6_Msk                   (0x03UL << PORT0_HWSEL_HW6_Pos)                         /*!< PORT0 HWSEL: HW6 Mask                   */\r
+#define PORT0_HWSEL_HW7_Pos                   14                                                      /*!< PORT0 HWSEL: HW7 Position               */\r
+#define PORT0_HWSEL_HW7_Msk                   (0x03UL << PORT0_HWSEL_HW7_Pos)                         /*!< PORT0 HWSEL: HW7 Mask                   */\r
+#define PORT0_HWSEL_HW8_Pos                   16                                                      /*!< PORT0 HWSEL: HW8 Position               */\r
+#define PORT0_HWSEL_HW8_Msk                   (0x03UL << PORT0_HWSEL_HW8_Pos)                         /*!< PORT0 HWSEL: HW8 Mask                   */\r
+#define PORT0_HWSEL_HW9_Pos                   18                                                      /*!< PORT0 HWSEL: HW9 Position               */\r
+#define PORT0_HWSEL_HW9_Msk                   (0x03UL << PORT0_HWSEL_HW9_Pos)                         /*!< PORT0 HWSEL: HW9 Mask                   */\r
+#define PORT0_HWSEL_HW10_Pos                  20                                                      /*!< PORT0 HWSEL: HW10 Position              */\r
+#define PORT0_HWSEL_HW10_Msk                  (0x03UL << PORT0_HWSEL_HW10_Pos)                        /*!< PORT0 HWSEL: HW10 Mask                  */\r
+#define PORT0_HWSEL_HW11_Pos                  22                                                      /*!< PORT0 HWSEL: HW11 Position              */\r
+#define PORT0_HWSEL_HW11_Msk                  (0x03UL << PORT0_HWSEL_HW11_Pos)                        /*!< PORT0 HWSEL: HW11 Mask                  */\r
+#define PORT0_HWSEL_HW12_Pos                  24                                                      /*!< PORT0 HWSEL: HW12 Position              */\r
+#define PORT0_HWSEL_HW12_Msk                  (0x03UL << PORT0_HWSEL_HW12_Pos)                        /*!< PORT0 HWSEL: HW12 Mask                  */\r
+#define PORT0_HWSEL_HW13_Pos                  26                                                      /*!< PORT0 HWSEL: HW13 Position              */\r
+#define PORT0_HWSEL_HW13_Msk                  (0x03UL << PORT0_HWSEL_HW13_Pos)                        /*!< PORT0 HWSEL: HW13 Mask                  */\r
+#define PORT0_HWSEL_HW14_Pos                  28                                                      /*!< PORT0 HWSEL: HW14 Position              */\r
+#define PORT0_HWSEL_HW14_Msk                  (0x03UL << PORT0_HWSEL_HW14_Pos)                        /*!< PORT0 HWSEL: HW14 Mask                  */\r
+#define PORT0_HWSEL_HW15_Pos                  30                                                      /*!< PORT0 HWSEL: HW15 Position              */\r
+#define PORT0_HWSEL_HW15_Msk                  (0x03UL << PORT0_HWSEL_HW15_Pos)                        /*!< PORT0 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT1' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT1_OUT  --------------------------------- */\r
+#define PORT1_OUT_P0_Pos                      0                                                       /*!< PORT1 OUT: P0 Position                  */\r
+#define PORT1_OUT_P0_Msk                      (0x01UL << PORT1_OUT_P0_Pos)                            /*!< PORT1 OUT: P0 Mask                      */\r
+#define PORT1_OUT_P1_Pos                      1                                                       /*!< PORT1 OUT: P1 Position                  */\r
+#define PORT1_OUT_P1_Msk                      (0x01UL << PORT1_OUT_P1_Pos)                            /*!< PORT1 OUT: P1 Mask                      */\r
+#define PORT1_OUT_P2_Pos                      2                                                       /*!< PORT1 OUT: P2 Position                  */\r
+#define PORT1_OUT_P2_Msk                      (0x01UL << PORT1_OUT_P2_Pos)                            /*!< PORT1 OUT: P2 Mask                      */\r
+#define PORT1_OUT_P3_Pos                      3                                                       /*!< PORT1 OUT: P3 Position                  */\r
+#define PORT1_OUT_P3_Msk                      (0x01UL << PORT1_OUT_P3_Pos)                            /*!< PORT1 OUT: P3 Mask                      */\r
+#define PORT1_OUT_P4_Pos                      4                                                       /*!< PORT1 OUT: P4 Position                  */\r
+#define PORT1_OUT_P4_Msk                      (0x01UL << PORT1_OUT_P4_Pos)                            /*!< PORT1 OUT: P4 Mask                      */\r
+#define PORT1_OUT_P5_Pos                      5                                                       /*!< PORT1 OUT: P5 Position                  */\r
+#define PORT1_OUT_P5_Msk                      (0x01UL << PORT1_OUT_P5_Pos)                            /*!< PORT1 OUT: P5 Mask                      */\r
+#define PORT1_OUT_P6_Pos                      6                                                       /*!< PORT1 OUT: P6 Position                  */\r
+#define PORT1_OUT_P6_Msk                      (0x01UL << PORT1_OUT_P6_Pos)                            /*!< PORT1 OUT: P6 Mask                      */\r
+#define PORT1_OUT_P7_Pos                      7                                                       /*!< PORT1 OUT: P7 Position                  */\r
+#define PORT1_OUT_P7_Msk                      (0x01UL << PORT1_OUT_P7_Pos)                            /*!< PORT1 OUT: P7 Mask                      */\r
+#define PORT1_OUT_P8_Pos                      8                                                       /*!< PORT1 OUT: P8 Position                  */\r
+#define PORT1_OUT_P8_Msk                      (0x01UL << PORT1_OUT_P8_Pos)                            /*!< PORT1 OUT: P8 Mask                      */\r
+#define PORT1_OUT_P9_Pos                      9                                                       /*!< PORT1 OUT: P9 Position                  */\r
+#define PORT1_OUT_P9_Msk                      (0x01UL << PORT1_OUT_P9_Pos)                            /*!< PORT1 OUT: P9 Mask                      */\r
+#define PORT1_OUT_P10_Pos                     10                                                      /*!< PORT1 OUT: P10 Position                 */\r
+#define PORT1_OUT_P10_Msk                     (0x01UL << PORT1_OUT_P10_Pos)                           /*!< PORT1 OUT: P10 Mask                     */\r
+#define PORT1_OUT_P11_Pos                     11                                                      /*!< PORT1 OUT: P11 Position                 */\r
+#define PORT1_OUT_P11_Msk                     (0x01UL << PORT1_OUT_P11_Pos)                           /*!< PORT1 OUT: P11 Mask                     */\r
+#define PORT1_OUT_P12_Pos                     12                                                      /*!< PORT1 OUT: P12 Position                 */\r
+#define PORT1_OUT_P12_Msk                     (0x01UL << PORT1_OUT_P12_Pos)                           /*!< PORT1 OUT: P12 Mask                     */\r
+#define PORT1_OUT_P13_Pos                     13                                                      /*!< PORT1 OUT: P13 Position                 */\r
+#define PORT1_OUT_P13_Msk                     (0x01UL << PORT1_OUT_P13_Pos)                           /*!< PORT1 OUT: P13 Mask                     */\r
+#define PORT1_OUT_P14_Pos                     14                                                      /*!< PORT1 OUT: P14 Position                 */\r
+#define PORT1_OUT_P14_Msk                     (0x01UL << PORT1_OUT_P14_Pos)                           /*!< PORT1 OUT: P14 Mask                     */\r
+#define PORT1_OUT_P15_Pos                     15                                                      /*!< PORT1 OUT: P15 Position                 */\r
+#define PORT1_OUT_P15_Msk                     (0x01UL << PORT1_OUT_P15_Pos)                           /*!< PORT1 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT1_OMR  --------------------------------- */\r
+#define PORT1_OMR_PS0_Pos                     0                                                       /*!< PORT1 OMR: PS0 Position                 */\r
+#define PORT1_OMR_PS0_Msk                     (0x01UL << PORT1_OMR_PS0_Pos)                           /*!< PORT1 OMR: PS0 Mask                     */\r
+#define PORT1_OMR_PS1_Pos                     1                                                       /*!< PORT1 OMR: PS1 Position                 */\r
+#define PORT1_OMR_PS1_Msk                     (0x01UL << PORT1_OMR_PS1_Pos)                           /*!< PORT1 OMR: PS1 Mask                     */\r
+#define PORT1_OMR_PS2_Pos                     2                                                       /*!< PORT1 OMR: PS2 Position                 */\r
+#define PORT1_OMR_PS2_Msk                     (0x01UL << PORT1_OMR_PS2_Pos)                           /*!< PORT1 OMR: PS2 Mask                     */\r
+#define PORT1_OMR_PS3_Pos                     3                                                       /*!< PORT1 OMR: PS3 Position                 */\r
+#define PORT1_OMR_PS3_Msk                     (0x01UL << PORT1_OMR_PS3_Pos)                           /*!< PORT1 OMR: PS3 Mask                     */\r
+#define PORT1_OMR_PS4_Pos                     4                                                       /*!< PORT1 OMR: PS4 Position                 */\r
+#define PORT1_OMR_PS4_Msk                     (0x01UL << PORT1_OMR_PS4_Pos)                           /*!< PORT1 OMR: PS4 Mask                     */\r
+#define PORT1_OMR_PS5_Pos                     5                                                       /*!< PORT1 OMR: PS5 Position                 */\r
+#define PORT1_OMR_PS5_Msk                     (0x01UL << PORT1_OMR_PS5_Pos)                           /*!< PORT1 OMR: PS5 Mask                     */\r
+#define PORT1_OMR_PS6_Pos                     6                                                       /*!< PORT1 OMR: PS6 Position                 */\r
+#define PORT1_OMR_PS6_Msk                     (0x01UL << PORT1_OMR_PS6_Pos)                           /*!< PORT1 OMR: PS6 Mask                     */\r
+#define PORT1_OMR_PS7_Pos                     7                                                       /*!< PORT1 OMR: PS7 Position                 */\r
+#define PORT1_OMR_PS7_Msk                     (0x01UL << PORT1_OMR_PS7_Pos)                           /*!< PORT1 OMR: PS7 Mask                     */\r
+#define PORT1_OMR_PS8_Pos                     8                                                       /*!< PORT1 OMR: PS8 Position                 */\r
+#define PORT1_OMR_PS8_Msk                     (0x01UL << PORT1_OMR_PS8_Pos)                           /*!< PORT1 OMR: PS8 Mask                     */\r
+#define PORT1_OMR_PS9_Pos                     9                                                       /*!< PORT1 OMR: PS9 Position                 */\r
+#define PORT1_OMR_PS9_Msk                     (0x01UL << PORT1_OMR_PS9_Pos)                           /*!< PORT1 OMR: PS9 Mask                     */\r
+#define PORT1_OMR_PS10_Pos                    10                                                      /*!< PORT1 OMR: PS10 Position                */\r
+#define PORT1_OMR_PS10_Msk                    (0x01UL << PORT1_OMR_PS10_Pos)                          /*!< PORT1 OMR: PS10 Mask                    */\r
+#define PORT1_OMR_PS11_Pos                    11                                                      /*!< PORT1 OMR: PS11 Position                */\r
+#define PORT1_OMR_PS11_Msk                    (0x01UL << PORT1_OMR_PS11_Pos)                          /*!< PORT1 OMR: PS11 Mask                    */\r
+#define PORT1_OMR_PS12_Pos                    12                                                      /*!< PORT1 OMR: PS12 Position                */\r
+#define PORT1_OMR_PS12_Msk                    (0x01UL << PORT1_OMR_PS12_Pos)                          /*!< PORT1 OMR: PS12 Mask                    */\r
+#define PORT1_OMR_PS13_Pos                    13                                                      /*!< PORT1 OMR: PS13 Position                */\r
+#define PORT1_OMR_PS13_Msk                    (0x01UL << PORT1_OMR_PS13_Pos)                          /*!< PORT1 OMR: PS13 Mask                    */\r
+#define PORT1_OMR_PS14_Pos                    14                                                      /*!< PORT1 OMR: PS14 Position                */\r
+#define PORT1_OMR_PS14_Msk                    (0x01UL << PORT1_OMR_PS14_Pos)                          /*!< PORT1 OMR: PS14 Mask                    */\r
+#define PORT1_OMR_PS15_Pos                    15                                                      /*!< PORT1 OMR: PS15 Position                */\r
+#define PORT1_OMR_PS15_Msk                    (0x01UL << PORT1_OMR_PS15_Pos)                          /*!< PORT1 OMR: PS15 Mask                    */\r
+#define PORT1_OMR_PR0_Pos                     16                                                      /*!< PORT1 OMR: PR0 Position                 */\r
+#define PORT1_OMR_PR0_Msk                     (0x01UL << PORT1_OMR_PR0_Pos)                           /*!< PORT1 OMR: PR0 Mask                     */\r
+#define PORT1_OMR_PR1_Pos                     17                                                      /*!< PORT1 OMR: PR1 Position                 */\r
+#define PORT1_OMR_PR1_Msk                     (0x01UL << PORT1_OMR_PR1_Pos)                           /*!< PORT1 OMR: PR1 Mask                     */\r
+#define PORT1_OMR_PR2_Pos                     18                                                      /*!< PORT1 OMR: PR2 Position                 */\r
+#define PORT1_OMR_PR2_Msk                     (0x01UL << PORT1_OMR_PR2_Pos)                           /*!< PORT1 OMR: PR2 Mask                     */\r
+#define PORT1_OMR_PR3_Pos                     19                                                      /*!< PORT1 OMR: PR3 Position                 */\r
+#define PORT1_OMR_PR3_Msk                     (0x01UL << PORT1_OMR_PR3_Pos)                           /*!< PORT1 OMR: PR3 Mask                     */\r
+#define PORT1_OMR_PR4_Pos                     20                                                      /*!< PORT1 OMR: PR4 Position                 */\r
+#define PORT1_OMR_PR4_Msk                     (0x01UL << PORT1_OMR_PR4_Pos)                           /*!< PORT1 OMR: PR4 Mask                     */\r
+#define PORT1_OMR_PR5_Pos                     21                                                      /*!< PORT1 OMR: PR5 Position                 */\r
+#define PORT1_OMR_PR5_Msk                     (0x01UL << PORT1_OMR_PR5_Pos)                           /*!< PORT1 OMR: PR5 Mask                     */\r
+#define PORT1_OMR_PR6_Pos                     22                                                      /*!< PORT1 OMR: PR6 Position                 */\r
+#define PORT1_OMR_PR6_Msk                     (0x01UL << PORT1_OMR_PR6_Pos)                           /*!< PORT1 OMR: PR6 Mask                     */\r
+#define PORT1_OMR_PR7_Pos                     23                                                      /*!< PORT1 OMR: PR7 Position                 */\r
+#define PORT1_OMR_PR7_Msk                     (0x01UL << PORT1_OMR_PR7_Pos)                           /*!< PORT1 OMR: PR7 Mask                     */\r
+#define PORT1_OMR_PR8_Pos                     24                                                      /*!< PORT1 OMR: PR8 Position                 */\r
+#define PORT1_OMR_PR8_Msk                     (0x01UL << PORT1_OMR_PR8_Pos)                           /*!< PORT1 OMR: PR8 Mask                     */\r
+#define PORT1_OMR_PR9_Pos                     25                                                      /*!< PORT1 OMR: PR9 Position                 */\r
+#define PORT1_OMR_PR9_Msk                     (0x01UL << PORT1_OMR_PR9_Pos)                           /*!< PORT1 OMR: PR9 Mask                     */\r
+#define PORT1_OMR_PR10_Pos                    26                                                      /*!< PORT1 OMR: PR10 Position                */\r
+#define PORT1_OMR_PR10_Msk                    (0x01UL << PORT1_OMR_PR10_Pos)                          /*!< PORT1 OMR: PR10 Mask                    */\r
+#define PORT1_OMR_PR11_Pos                    27                                                      /*!< PORT1 OMR: PR11 Position                */\r
+#define PORT1_OMR_PR11_Msk                    (0x01UL << PORT1_OMR_PR11_Pos)                          /*!< PORT1 OMR: PR11 Mask                    */\r
+#define PORT1_OMR_PR12_Pos                    28                                                      /*!< PORT1 OMR: PR12 Position                */\r
+#define PORT1_OMR_PR12_Msk                    (0x01UL << PORT1_OMR_PR12_Pos)                          /*!< PORT1 OMR: PR12 Mask                    */\r
+#define PORT1_OMR_PR13_Pos                    29                                                      /*!< PORT1 OMR: PR13 Position                */\r
+#define PORT1_OMR_PR13_Msk                    (0x01UL << PORT1_OMR_PR13_Pos)                          /*!< PORT1 OMR: PR13 Mask                    */\r
+#define PORT1_OMR_PR14_Pos                    30                                                      /*!< PORT1 OMR: PR14 Position                */\r
+#define PORT1_OMR_PR14_Msk                    (0x01UL << PORT1_OMR_PR14_Pos)                          /*!< PORT1 OMR: PR14 Mask                    */\r
+#define PORT1_OMR_PR15_Pos                    31                                                      /*!< PORT1 OMR: PR15 Position                */\r
+#define PORT1_OMR_PR15_Msk                    (0x01UL << PORT1_OMR_PR15_Pos)                          /*!< PORT1 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT1_IOCR0  -------------------------------- */\r
+#define PORT1_IOCR0_PC0_Pos                   3                                                       /*!< PORT1 IOCR0: PC0 Position               */\r
+#define PORT1_IOCR0_PC0_Msk                   (0x1fUL << PORT1_IOCR0_PC0_Pos)                         /*!< PORT1 IOCR0: PC0 Mask                   */\r
+#define PORT1_IOCR0_PC1_Pos                   11                                                      /*!< PORT1 IOCR0: PC1 Position               */\r
+#define PORT1_IOCR0_PC1_Msk                   (0x1fUL << PORT1_IOCR0_PC1_Pos)                         /*!< PORT1 IOCR0: PC1 Mask                   */\r
+#define PORT1_IOCR0_PC2_Pos                   19                                                      /*!< PORT1 IOCR0: PC2 Position               */\r
+#define PORT1_IOCR0_PC2_Msk                   (0x1fUL << PORT1_IOCR0_PC2_Pos)                         /*!< PORT1 IOCR0: PC2 Mask                   */\r
+#define PORT1_IOCR0_PC3_Pos                   27                                                      /*!< PORT1 IOCR0: PC3 Position               */\r
+#define PORT1_IOCR0_PC3_Msk                   (0x1fUL << PORT1_IOCR0_PC3_Pos)                         /*!< PORT1 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_IOCR4  -------------------------------- */\r
+#define PORT1_IOCR4_PC4_Pos                   3                                                       /*!< PORT1 IOCR4: PC4 Position               */\r
+#define PORT1_IOCR4_PC4_Msk                   (0x1fUL << PORT1_IOCR4_PC4_Pos)                         /*!< PORT1 IOCR4: PC4 Mask                   */\r
+#define PORT1_IOCR4_PC5_Pos                   11                                                      /*!< PORT1 IOCR4: PC5 Position               */\r
+#define PORT1_IOCR4_PC5_Msk                   (0x1fUL << PORT1_IOCR4_PC5_Pos)                         /*!< PORT1 IOCR4: PC5 Mask                   */\r
+#define PORT1_IOCR4_PC6_Pos                   19                                                      /*!< PORT1 IOCR4: PC6 Position               */\r
+#define PORT1_IOCR4_PC6_Msk                   (0x1fUL << PORT1_IOCR4_PC6_Pos)                         /*!< PORT1 IOCR4: PC6 Mask                   */\r
+#define PORT1_IOCR4_PC7_Pos                   27                                                      /*!< PORT1 IOCR4: PC7 Position               */\r
+#define PORT1_IOCR4_PC7_Msk                   (0x1fUL << PORT1_IOCR4_PC7_Pos)                         /*!< PORT1 IOCR4: PC7 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_IOCR8  -------------------------------- */\r
+#define PORT1_IOCR8_PC8_Pos                   3                                                       /*!< PORT1 IOCR8: PC8 Position               */\r
+#define PORT1_IOCR8_PC8_Msk                   (0x1fUL << PORT1_IOCR8_PC8_Pos)                         /*!< PORT1 IOCR8: PC8 Mask                   */\r
+#define PORT1_IOCR8_PC9_Pos                   11                                                      /*!< PORT1 IOCR8: PC9 Position               */\r
+#define PORT1_IOCR8_PC9_Msk                   (0x1fUL << PORT1_IOCR8_PC9_Pos)                         /*!< PORT1 IOCR8: PC9 Mask                   */\r
+#define PORT1_IOCR8_PC10_Pos                  19                                                      /*!< PORT1 IOCR8: PC10 Position              */\r
+#define PORT1_IOCR8_PC10_Msk                  (0x1fUL << PORT1_IOCR8_PC10_Pos)                        /*!< PORT1 IOCR8: PC10 Mask                  */\r
+#define PORT1_IOCR8_PC11_Pos                  27                                                      /*!< PORT1 IOCR8: PC11 Position              */\r
+#define PORT1_IOCR8_PC11_Msk                  (0x1fUL << PORT1_IOCR8_PC11_Pos)                        /*!< PORT1 IOCR8: PC11 Mask                  */\r
+\r
+/* --------------------------------  PORT1_IOCR12  -------------------------------- */\r
+#define PORT1_IOCR12_PC12_Pos                 3                                                       /*!< PORT1 IOCR12: PC12 Position             */\r
+#define PORT1_IOCR12_PC12_Msk                 (0x1fUL << PORT1_IOCR12_PC12_Pos)                       /*!< PORT1 IOCR12: PC12 Mask                 */\r
+#define PORT1_IOCR12_PC13_Pos                 11                                                      /*!< PORT1 IOCR12: PC13 Position             */\r
+#define PORT1_IOCR12_PC13_Msk                 (0x1fUL << PORT1_IOCR12_PC13_Pos)                       /*!< PORT1 IOCR12: PC13 Mask                 */\r
+#define PORT1_IOCR12_PC14_Pos                 19                                                      /*!< PORT1 IOCR12: PC14 Position             */\r
+#define PORT1_IOCR12_PC14_Msk                 (0x1fUL << PORT1_IOCR12_PC14_Pos)                       /*!< PORT1 IOCR12: PC14 Mask                 */\r
+#define PORT1_IOCR12_PC15_Pos                 27                                                      /*!< PORT1 IOCR12: PC15 Position             */\r
+#define PORT1_IOCR12_PC15_Msk                 (0x1fUL << PORT1_IOCR12_PC15_Pos)                       /*!< PORT1 IOCR12: PC15 Mask                 */\r
+\r
+/* ----------------------------------  PORT1_IN  ---------------------------------- */\r
+#define PORT1_IN_P0_Pos                       0                                                       /*!< PORT1 IN: P0 Position                   */\r
+#define PORT1_IN_P0_Msk                       (0x01UL << PORT1_IN_P0_Pos)                             /*!< PORT1 IN: P0 Mask                       */\r
+#define PORT1_IN_P1_Pos                       1                                                       /*!< PORT1 IN: P1 Position                   */\r
+#define PORT1_IN_P1_Msk                       (0x01UL << PORT1_IN_P1_Pos)                             /*!< PORT1 IN: P1 Mask                       */\r
+#define PORT1_IN_P2_Pos                       2                                                       /*!< PORT1 IN: P2 Position                   */\r
+#define PORT1_IN_P2_Msk                       (0x01UL << PORT1_IN_P2_Pos)                             /*!< PORT1 IN: P2 Mask                       */\r
+#define PORT1_IN_P3_Pos                       3                                                       /*!< PORT1 IN: P3 Position                   */\r
+#define PORT1_IN_P3_Msk                       (0x01UL << PORT1_IN_P3_Pos)                             /*!< PORT1 IN: P3 Mask                       */\r
+#define PORT1_IN_P4_Pos                       4                                                       /*!< PORT1 IN: P4 Position                   */\r
+#define PORT1_IN_P4_Msk                       (0x01UL << PORT1_IN_P4_Pos)                             /*!< PORT1 IN: P4 Mask                       */\r
+#define PORT1_IN_P5_Pos                       5                                                       /*!< PORT1 IN: P5 Position                   */\r
+#define PORT1_IN_P5_Msk                       (0x01UL << PORT1_IN_P5_Pos)                             /*!< PORT1 IN: P5 Mask                       */\r
+#define PORT1_IN_P6_Pos                       6                                                       /*!< PORT1 IN: P6 Position                   */\r
+#define PORT1_IN_P6_Msk                       (0x01UL << PORT1_IN_P6_Pos)                             /*!< PORT1 IN: P6 Mask                       */\r
+#define PORT1_IN_P7_Pos                       7                                                       /*!< PORT1 IN: P7 Position                   */\r
+#define PORT1_IN_P7_Msk                       (0x01UL << PORT1_IN_P7_Pos)                             /*!< PORT1 IN: P7 Mask                       */\r
+#define PORT1_IN_P8_Pos                       8                                                       /*!< PORT1 IN: P8 Position                   */\r
+#define PORT1_IN_P8_Msk                       (0x01UL << PORT1_IN_P8_Pos)                             /*!< PORT1 IN: P8 Mask                       */\r
+#define PORT1_IN_P9_Pos                       9                                                       /*!< PORT1 IN: P9 Position                   */\r
+#define PORT1_IN_P9_Msk                       (0x01UL << PORT1_IN_P9_Pos)                             /*!< PORT1 IN: P9 Mask                       */\r
+#define PORT1_IN_P10_Pos                      10                                                      /*!< PORT1 IN: P10 Position                  */\r
+#define PORT1_IN_P10_Msk                      (0x01UL << PORT1_IN_P10_Pos)                            /*!< PORT1 IN: P10 Mask                      */\r
+#define PORT1_IN_P11_Pos                      11                                                      /*!< PORT1 IN: P11 Position                  */\r
+#define PORT1_IN_P11_Msk                      (0x01UL << PORT1_IN_P11_Pos)                            /*!< PORT1 IN: P11 Mask                      */\r
+#define PORT1_IN_P12_Pos                      12                                                      /*!< PORT1 IN: P12 Position                  */\r
+#define PORT1_IN_P12_Msk                      (0x01UL << PORT1_IN_P12_Pos)                            /*!< PORT1 IN: P12 Mask                      */\r
+#define PORT1_IN_P13_Pos                      13                                                      /*!< PORT1 IN: P13 Position                  */\r
+#define PORT1_IN_P13_Msk                      (0x01UL << PORT1_IN_P13_Pos)                            /*!< PORT1 IN: P13 Mask                      */\r
+#define PORT1_IN_P14_Pos                      14                                                      /*!< PORT1 IN: P14 Position                  */\r
+#define PORT1_IN_P14_Msk                      (0x01UL << PORT1_IN_P14_Pos)                            /*!< PORT1 IN: P14 Mask                      */\r
+#define PORT1_IN_P15_Pos                      15                                                      /*!< PORT1 IN: P15 Position                  */\r
+#define PORT1_IN_P15_Msk                      (0x01UL << PORT1_IN_P15_Pos)                            /*!< PORT1 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT1_PDR0  --------------------------------- */\r
+#define PORT1_PDR0_PD0_Pos                    0                                                       /*!< PORT1 PDR0: PD0 Position                */\r
+#define PORT1_PDR0_PD0_Msk                    (0x07UL << PORT1_PDR0_PD0_Pos)                          /*!< PORT1 PDR0: PD0 Mask                    */\r
+#define PORT1_PDR0_PD1_Pos                    4                                                       /*!< PORT1 PDR0: PD1 Position                */\r
+#define PORT1_PDR0_PD1_Msk                    (0x07UL << PORT1_PDR0_PD1_Pos)                          /*!< PORT1 PDR0: PD1 Mask                    */\r
+#define PORT1_PDR0_PD2_Pos                    8                                                       /*!< PORT1 PDR0: PD2 Position                */\r
+#define PORT1_PDR0_PD2_Msk                    (0x07UL << PORT1_PDR0_PD2_Pos)                          /*!< PORT1 PDR0: PD2 Mask                    */\r
+#define PORT1_PDR0_PD3_Pos                    12                                                      /*!< PORT1 PDR0: PD3 Position                */\r
+#define PORT1_PDR0_PD3_Msk                    (0x07UL << PORT1_PDR0_PD3_Pos)                          /*!< PORT1 PDR0: PD3 Mask                    */\r
+#define PORT1_PDR0_PD4_Pos                    16                                                      /*!< PORT1 PDR0: PD4 Position                */\r
+#define PORT1_PDR0_PD4_Msk                    (0x07UL << PORT1_PDR0_PD4_Pos)                          /*!< PORT1 PDR0: PD4 Mask                    */\r
+#define PORT1_PDR0_PD5_Pos                    20                                                      /*!< PORT1 PDR0: PD5 Position                */\r
+#define PORT1_PDR0_PD5_Msk                    (0x07UL << PORT1_PDR0_PD5_Pos)                          /*!< PORT1 PDR0: PD5 Mask                    */\r
+#define PORT1_PDR0_PD6_Pos                    24                                                      /*!< PORT1 PDR0: PD6 Position                */\r
+#define PORT1_PDR0_PD6_Msk                    (0x07UL << PORT1_PDR0_PD6_Pos)                          /*!< PORT1 PDR0: PD6 Mask                    */\r
+#define PORT1_PDR0_PD7_Pos                    28                                                      /*!< PORT1 PDR0: PD7 Position                */\r
+#define PORT1_PDR0_PD7_Msk                    (0x07UL << PORT1_PDR0_PD7_Pos)                          /*!< PORT1 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT1_PDR1  --------------------------------- */\r
+#define PORT1_PDR1_PD8_Pos                    0                                                       /*!< PORT1 PDR1: PD8 Position                */\r
+#define PORT1_PDR1_PD8_Msk                    (0x07UL << PORT1_PDR1_PD8_Pos)                          /*!< PORT1 PDR1: PD8 Mask                    */\r
+#define PORT1_PDR1_PD9_Pos                    4                                                       /*!< PORT1 PDR1: PD9 Position                */\r
+#define PORT1_PDR1_PD9_Msk                    (0x07UL << PORT1_PDR1_PD9_Pos)                          /*!< PORT1 PDR1: PD9 Mask                    */\r
+#define PORT1_PDR1_PD10_Pos                   8                                                       /*!< PORT1 PDR1: PD10 Position               */\r
+#define PORT1_PDR1_PD10_Msk                   (0x07UL << PORT1_PDR1_PD10_Pos)                         /*!< PORT1 PDR1: PD10 Mask                   */\r
+#define PORT1_PDR1_PD11_Pos                   12                                                      /*!< PORT1 PDR1: PD11 Position               */\r
+#define PORT1_PDR1_PD11_Msk                   (0x07UL << PORT1_PDR1_PD11_Pos)                         /*!< PORT1 PDR1: PD11 Mask                   */\r
+#define PORT1_PDR1_PD12_Pos                   16                                                      /*!< PORT1 PDR1: PD12 Position               */\r
+#define PORT1_PDR1_PD12_Msk                   (0x07UL << PORT1_PDR1_PD12_Pos)                         /*!< PORT1 PDR1: PD12 Mask                   */\r
+#define PORT1_PDR1_PD13_Pos                   20                                                      /*!< PORT1 PDR1: PD13 Position               */\r
+#define PORT1_PDR1_PD13_Msk                   (0x07UL << PORT1_PDR1_PD13_Pos)                         /*!< PORT1 PDR1: PD13 Mask                   */\r
+#define PORT1_PDR1_PD14_Pos                   24                                                      /*!< PORT1 PDR1: PD14 Position               */\r
+#define PORT1_PDR1_PD14_Msk                   (0x07UL << PORT1_PDR1_PD14_Pos)                         /*!< PORT1 PDR1: PD14 Mask                   */\r
+#define PORT1_PDR1_PD15_Pos                   28                                                      /*!< PORT1 PDR1: PD15 Position               */\r
+#define PORT1_PDR1_PD15_Msk                   (0x07UL << PORT1_PDR1_PD15_Pos)                         /*!< PORT1 PDR1: PD15 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_PDISC  -------------------------------- */\r
+#define PORT1_PDISC_PDIS0_Pos                 0                                                       /*!< PORT1 PDISC: PDIS0 Position             */\r
+#define PORT1_PDISC_PDIS0_Msk                 (0x01UL << PORT1_PDISC_PDIS0_Pos)                       /*!< PORT1 PDISC: PDIS0 Mask                 */\r
+#define PORT1_PDISC_PDIS1_Pos                 1                                                       /*!< PORT1 PDISC: PDIS1 Position             */\r
+#define PORT1_PDISC_PDIS1_Msk                 (0x01UL << PORT1_PDISC_PDIS1_Pos)                       /*!< PORT1 PDISC: PDIS1 Mask                 */\r
+#define PORT1_PDISC_PDIS2_Pos                 2                                                       /*!< PORT1 PDISC: PDIS2 Position             */\r
+#define PORT1_PDISC_PDIS2_Msk                 (0x01UL << PORT1_PDISC_PDIS2_Pos)                       /*!< PORT1 PDISC: PDIS2 Mask                 */\r
+#define PORT1_PDISC_PDIS3_Pos                 3                                                       /*!< PORT1 PDISC: PDIS3 Position             */\r
+#define PORT1_PDISC_PDIS3_Msk                 (0x01UL << PORT1_PDISC_PDIS3_Pos)                       /*!< PORT1 PDISC: PDIS3 Mask                 */\r
+#define PORT1_PDISC_PDIS4_Pos                 4                                                       /*!< PORT1 PDISC: PDIS4 Position             */\r
+#define PORT1_PDISC_PDIS4_Msk                 (0x01UL << PORT1_PDISC_PDIS4_Pos)                       /*!< PORT1 PDISC: PDIS4 Mask                 */\r
+#define PORT1_PDISC_PDIS5_Pos                 5                                                       /*!< PORT1 PDISC: PDIS5 Position             */\r
+#define PORT1_PDISC_PDIS5_Msk                 (0x01UL << PORT1_PDISC_PDIS5_Pos)                       /*!< PORT1 PDISC: PDIS5 Mask                 */\r
+#define PORT1_PDISC_PDIS6_Pos                 6                                                       /*!< PORT1 PDISC: PDIS6 Position             */\r
+#define PORT1_PDISC_PDIS6_Msk                 (0x01UL << PORT1_PDISC_PDIS6_Pos)                       /*!< PORT1 PDISC: PDIS6 Mask                 */\r
+#define PORT1_PDISC_PDIS7_Pos                 7                                                       /*!< PORT1 PDISC: PDIS7 Position             */\r
+#define PORT1_PDISC_PDIS7_Msk                 (0x01UL << PORT1_PDISC_PDIS7_Pos)                       /*!< PORT1 PDISC: PDIS7 Mask                 */\r
+#define PORT1_PDISC_PDIS8_Pos                 8                                                       /*!< PORT1 PDISC: PDIS8 Position             */\r
+#define PORT1_PDISC_PDIS8_Msk                 (0x01UL << PORT1_PDISC_PDIS8_Pos)                       /*!< PORT1 PDISC: PDIS8 Mask                 */\r
+#define PORT1_PDISC_PDIS9_Pos                 9                                                       /*!< PORT1 PDISC: PDIS9 Position             */\r
+#define PORT1_PDISC_PDIS9_Msk                 (0x01UL << PORT1_PDISC_PDIS9_Pos)                       /*!< PORT1 PDISC: PDIS9 Mask                 */\r
+#define PORT1_PDISC_PDIS10_Pos                10                                                      /*!< PORT1 PDISC: PDIS10 Position            */\r
+#define PORT1_PDISC_PDIS10_Msk                (0x01UL << PORT1_PDISC_PDIS10_Pos)                      /*!< PORT1 PDISC: PDIS10 Mask                */\r
+#define PORT1_PDISC_PDIS11_Pos                11                                                      /*!< PORT1 PDISC: PDIS11 Position            */\r
+#define PORT1_PDISC_PDIS11_Msk                (0x01UL << PORT1_PDISC_PDIS11_Pos)                      /*!< PORT1 PDISC: PDIS11 Mask                */\r
+#define PORT1_PDISC_PDIS12_Pos                12                                                      /*!< PORT1 PDISC: PDIS12 Position            */\r
+#define PORT1_PDISC_PDIS12_Msk                (0x01UL << PORT1_PDISC_PDIS12_Pos)                      /*!< PORT1 PDISC: PDIS12 Mask                */\r
+#define PORT1_PDISC_PDIS13_Pos                13                                                      /*!< PORT1 PDISC: PDIS13 Position            */\r
+#define PORT1_PDISC_PDIS13_Msk                (0x01UL << PORT1_PDISC_PDIS13_Pos)                      /*!< PORT1 PDISC: PDIS13 Mask                */\r
+#define PORT1_PDISC_PDIS14_Pos                14                                                      /*!< PORT1 PDISC: PDIS14 Position            */\r
+#define PORT1_PDISC_PDIS14_Msk                (0x01UL << PORT1_PDISC_PDIS14_Pos)                      /*!< PORT1 PDISC: PDIS14 Mask                */\r
+#define PORT1_PDISC_PDIS15_Pos                15                                                      /*!< PORT1 PDISC: PDIS15 Position            */\r
+#define PORT1_PDISC_PDIS15_Msk                (0x01UL << PORT1_PDISC_PDIS15_Pos)                      /*!< PORT1 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT1_PPS  --------------------------------- */\r
+#define PORT1_PPS_PPS0_Pos                    0                                                       /*!< PORT1 PPS: PPS0 Position                */\r
+#define PORT1_PPS_PPS0_Msk                    (0x01UL << PORT1_PPS_PPS0_Pos)                          /*!< PORT1 PPS: PPS0 Mask                    */\r
+#define PORT1_PPS_PPS1_Pos                    1                                                       /*!< PORT1 PPS: PPS1 Position                */\r
+#define PORT1_PPS_PPS1_Msk                    (0x01UL << PORT1_PPS_PPS1_Pos)                          /*!< PORT1 PPS: PPS1 Mask                    */\r
+#define PORT1_PPS_PPS2_Pos                    2                                                       /*!< PORT1 PPS: PPS2 Position                */\r
+#define PORT1_PPS_PPS2_Msk                    (0x01UL << PORT1_PPS_PPS2_Pos)                          /*!< PORT1 PPS: PPS2 Mask                    */\r
+#define PORT1_PPS_PPS3_Pos                    3                                                       /*!< PORT1 PPS: PPS3 Position                */\r
+#define PORT1_PPS_PPS3_Msk                    (0x01UL << PORT1_PPS_PPS3_Pos)                          /*!< PORT1 PPS: PPS3 Mask                    */\r
+#define PORT1_PPS_PPS4_Pos                    4                                                       /*!< PORT1 PPS: PPS4 Position                */\r
+#define PORT1_PPS_PPS4_Msk                    (0x01UL << PORT1_PPS_PPS4_Pos)                          /*!< PORT1 PPS: PPS4 Mask                    */\r
+#define PORT1_PPS_PPS5_Pos                    5                                                       /*!< PORT1 PPS: PPS5 Position                */\r
+#define PORT1_PPS_PPS5_Msk                    (0x01UL << PORT1_PPS_PPS5_Pos)                          /*!< PORT1 PPS: PPS5 Mask                    */\r
+#define PORT1_PPS_PPS6_Pos                    6                                                       /*!< PORT1 PPS: PPS6 Position                */\r
+#define PORT1_PPS_PPS6_Msk                    (0x01UL << PORT1_PPS_PPS6_Pos)                          /*!< PORT1 PPS: PPS6 Mask                    */\r
+#define PORT1_PPS_PPS7_Pos                    7                                                       /*!< PORT1 PPS: PPS7 Position                */\r
+#define PORT1_PPS_PPS7_Msk                    (0x01UL << PORT1_PPS_PPS7_Pos)                          /*!< PORT1 PPS: PPS7 Mask                    */\r
+#define PORT1_PPS_PPS8_Pos                    8                                                       /*!< PORT1 PPS: PPS8 Position                */\r
+#define PORT1_PPS_PPS8_Msk                    (0x01UL << PORT1_PPS_PPS8_Pos)                          /*!< PORT1 PPS: PPS8 Mask                    */\r
+#define PORT1_PPS_PPS9_Pos                    9                                                       /*!< PORT1 PPS: PPS9 Position                */\r
+#define PORT1_PPS_PPS9_Msk                    (0x01UL << PORT1_PPS_PPS9_Pos)                          /*!< PORT1 PPS: PPS9 Mask                    */\r
+#define PORT1_PPS_PPS10_Pos                   10                                                      /*!< PORT1 PPS: PPS10 Position               */\r
+#define PORT1_PPS_PPS10_Msk                   (0x01UL << PORT1_PPS_PPS10_Pos)                         /*!< PORT1 PPS: PPS10 Mask                   */\r
+#define PORT1_PPS_PPS11_Pos                   11                                                      /*!< PORT1 PPS: PPS11 Position               */\r
+#define PORT1_PPS_PPS11_Msk                   (0x01UL << PORT1_PPS_PPS11_Pos)                         /*!< PORT1 PPS: PPS11 Mask                   */\r
+#define PORT1_PPS_PPS12_Pos                   12                                                      /*!< PORT1 PPS: PPS12 Position               */\r
+#define PORT1_PPS_PPS12_Msk                   (0x01UL << PORT1_PPS_PPS12_Pos)                         /*!< PORT1 PPS: PPS12 Mask                   */\r
+#define PORT1_PPS_PPS13_Pos                   13                                                      /*!< PORT1 PPS: PPS13 Position               */\r
+#define PORT1_PPS_PPS13_Msk                   (0x01UL << PORT1_PPS_PPS13_Pos)                         /*!< PORT1 PPS: PPS13 Mask                   */\r
+#define PORT1_PPS_PPS14_Pos                   14                                                      /*!< PORT1 PPS: PPS14 Position               */\r
+#define PORT1_PPS_PPS14_Msk                   (0x01UL << PORT1_PPS_PPS14_Pos)                         /*!< PORT1 PPS: PPS14 Mask                   */\r
+#define PORT1_PPS_PPS15_Pos                   15                                                      /*!< PORT1 PPS: PPS15 Position               */\r
+#define PORT1_PPS_PPS15_Msk                   (0x01UL << PORT1_PPS_PPS15_Pos)                         /*!< PORT1 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT1_HWSEL  -------------------------------- */\r
+#define PORT1_HWSEL_HW0_Pos                   0                                                       /*!< PORT1 HWSEL: HW0 Position               */\r
+#define PORT1_HWSEL_HW0_Msk                   (0x03UL << PORT1_HWSEL_HW0_Pos)                         /*!< PORT1 HWSEL: HW0 Mask                   */\r
+#define PORT1_HWSEL_HW1_Pos                   2                                                       /*!< PORT1 HWSEL: HW1 Position               */\r
+#define PORT1_HWSEL_HW1_Msk                   (0x03UL << PORT1_HWSEL_HW1_Pos)                         /*!< PORT1 HWSEL: HW1 Mask                   */\r
+#define PORT1_HWSEL_HW2_Pos                   4                                                       /*!< PORT1 HWSEL: HW2 Position               */\r
+#define PORT1_HWSEL_HW2_Msk                   (0x03UL << PORT1_HWSEL_HW2_Pos)                         /*!< PORT1 HWSEL: HW2 Mask                   */\r
+#define PORT1_HWSEL_HW3_Pos                   6                                                       /*!< PORT1 HWSEL: HW3 Position               */\r
+#define PORT1_HWSEL_HW3_Msk                   (0x03UL << PORT1_HWSEL_HW3_Pos)                         /*!< PORT1 HWSEL: HW3 Mask                   */\r
+#define PORT1_HWSEL_HW4_Pos                   8                                                       /*!< PORT1 HWSEL: HW4 Position               */\r
+#define PORT1_HWSEL_HW4_Msk                   (0x03UL << PORT1_HWSEL_HW4_Pos)                         /*!< PORT1 HWSEL: HW4 Mask                   */\r
+#define PORT1_HWSEL_HW5_Pos                   10                                                      /*!< PORT1 HWSEL: HW5 Position               */\r
+#define PORT1_HWSEL_HW5_Msk                   (0x03UL << PORT1_HWSEL_HW5_Pos)                         /*!< PORT1 HWSEL: HW5 Mask                   */\r
+#define PORT1_HWSEL_HW6_Pos                   12                                                      /*!< PORT1 HWSEL: HW6 Position               */\r
+#define PORT1_HWSEL_HW6_Msk                   (0x03UL << PORT1_HWSEL_HW6_Pos)                         /*!< PORT1 HWSEL: HW6 Mask                   */\r
+#define PORT1_HWSEL_HW7_Pos                   14                                                      /*!< PORT1 HWSEL: HW7 Position               */\r
+#define PORT1_HWSEL_HW7_Msk                   (0x03UL << PORT1_HWSEL_HW7_Pos)                         /*!< PORT1 HWSEL: HW7 Mask                   */\r
+#define PORT1_HWSEL_HW8_Pos                   16                                                      /*!< PORT1 HWSEL: HW8 Position               */\r
+#define PORT1_HWSEL_HW8_Msk                   (0x03UL << PORT1_HWSEL_HW8_Pos)                         /*!< PORT1 HWSEL: HW8 Mask                   */\r
+#define PORT1_HWSEL_HW9_Pos                   18                                                      /*!< PORT1 HWSEL: HW9 Position               */\r
+#define PORT1_HWSEL_HW9_Msk                   (0x03UL << PORT1_HWSEL_HW9_Pos)                         /*!< PORT1 HWSEL: HW9 Mask                   */\r
+#define PORT1_HWSEL_HW10_Pos                  20                                                      /*!< PORT1 HWSEL: HW10 Position              */\r
+#define PORT1_HWSEL_HW10_Msk                  (0x03UL << PORT1_HWSEL_HW10_Pos)                        /*!< PORT1 HWSEL: HW10 Mask                  */\r
+#define PORT1_HWSEL_HW11_Pos                  22                                                      /*!< PORT1 HWSEL: HW11 Position              */\r
+#define PORT1_HWSEL_HW11_Msk                  (0x03UL << PORT1_HWSEL_HW11_Pos)                        /*!< PORT1 HWSEL: HW11 Mask                  */\r
+#define PORT1_HWSEL_HW12_Pos                  24                                                      /*!< PORT1 HWSEL: HW12 Position              */\r
+#define PORT1_HWSEL_HW12_Msk                  (0x03UL << PORT1_HWSEL_HW12_Pos)                        /*!< PORT1 HWSEL: HW12 Mask                  */\r
+#define PORT1_HWSEL_HW13_Pos                  26                                                      /*!< PORT1 HWSEL: HW13 Position              */\r
+#define PORT1_HWSEL_HW13_Msk                  (0x03UL << PORT1_HWSEL_HW13_Pos)                        /*!< PORT1 HWSEL: HW13 Mask                  */\r
+#define PORT1_HWSEL_HW14_Pos                  28                                                      /*!< PORT1 HWSEL: HW14 Position              */\r
+#define PORT1_HWSEL_HW14_Msk                  (0x03UL << PORT1_HWSEL_HW14_Pos)                        /*!< PORT1 HWSEL: HW14 Mask                  */\r
+#define PORT1_HWSEL_HW15_Pos                  30                                                      /*!< PORT1 HWSEL: HW15 Position              */\r
+#define PORT1_HWSEL_HW15_Msk                  (0x03UL << PORT1_HWSEL_HW15_Pos)                        /*!< PORT1 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT2' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT2_OUT  --------------------------------- */\r
+#define PORT2_OUT_P0_Pos                      0                                                       /*!< PORT2 OUT: P0 Position                  */\r
+#define PORT2_OUT_P0_Msk                      (0x01UL << PORT2_OUT_P0_Pos)                            /*!< PORT2 OUT: P0 Mask                      */\r
+#define PORT2_OUT_P1_Pos                      1                                                       /*!< PORT2 OUT: P1 Position                  */\r
+#define PORT2_OUT_P1_Msk                      (0x01UL << PORT2_OUT_P1_Pos)                            /*!< PORT2 OUT: P1 Mask                      */\r
+#define PORT2_OUT_P2_Pos                      2                                                       /*!< PORT2 OUT: P2 Position                  */\r
+#define PORT2_OUT_P2_Msk                      (0x01UL << PORT2_OUT_P2_Pos)                            /*!< PORT2 OUT: P2 Mask                      */\r
+#define PORT2_OUT_P3_Pos                      3                                                       /*!< PORT2 OUT: P3 Position                  */\r
+#define PORT2_OUT_P3_Msk                      (0x01UL << PORT2_OUT_P3_Pos)                            /*!< PORT2 OUT: P3 Mask                      */\r
+#define PORT2_OUT_P4_Pos                      4                                                       /*!< PORT2 OUT: P4 Position                  */\r
+#define PORT2_OUT_P4_Msk                      (0x01UL << PORT2_OUT_P4_Pos)                            /*!< PORT2 OUT: P4 Mask                      */\r
+#define PORT2_OUT_P5_Pos                      5                                                       /*!< PORT2 OUT: P5 Position                  */\r
+#define PORT2_OUT_P5_Msk                      (0x01UL << PORT2_OUT_P5_Pos)                            /*!< PORT2 OUT: P5 Mask                      */\r
+#define PORT2_OUT_P6_Pos                      6                                                       /*!< PORT2 OUT: P6 Position                  */\r
+#define PORT2_OUT_P6_Msk                      (0x01UL << PORT2_OUT_P6_Pos)                            /*!< PORT2 OUT: P6 Mask                      */\r
+#define PORT2_OUT_P7_Pos                      7                                                       /*!< PORT2 OUT: P7 Position                  */\r
+#define PORT2_OUT_P7_Msk                      (0x01UL << PORT2_OUT_P7_Pos)                            /*!< PORT2 OUT: P7 Mask                      */\r
+#define PORT2_OUT_P8_Pos                      8                                                       /*!< PORT2 OUT: P8 Position                  */\r
+#define PORT2_OUT_P8_Msk                      (0x01UL << PORT2_OUT_P8_Pos)                            /*!< PORT2 OUT: P8 Mask                      */\r
+#define PORT2_OUT_P9_Pos                      9                                                       /*!< PORT2 OUT: P9 Position                  */\r
+#define PORT2_OUT_P9_Msk                      (0x01UL << PORT2_OUT_P9_Pos)                            /*!< PORT2 OUT: P9 Mask                      */\r
+#define PORT2_OUT_P10_Pos                     10                                                      /*!< PORT2 OUT: P10 Position                 */\r
+#define PORT2_OUT_P10_Msk                     (0x01UL << PORT2_OUT_P10_Pos)                           /*!< PORT2 OUT: P10 Mask                     */\r
+#define PORT2_OUT_P11_Pos                     11                                                      /*!< PORT2 OUT: P11 Position                 */\r
+#define PORT2_OUT_P11_Msk                     (0x01UL << PORT2_OUT_P11_Pos)                           /*!< PORT2 OUT: P11 Mask                     */\r
+#define PORT2_OUT_P12_Pos                     12                                                      /*!< PORT2 OUT: P12 Position                 */\r
+#define PORT2_OUT_P12_Msk                     (0x01UL << PORT2_OUT_P12_Pos)                           /*!< PORT2 OUT: P12 Mask                     */\r
+#define PORT2_OUT_P13_Pos                     13                                                      /*!< PORT2 OUT: P13 Position                 */\r
+#define PORT2_OUT_P13_Msk                     (0x01UL << PORT2_OUT_P13_Pos)                           /*!< PORT2 OUT: P13 Mask                     */\r
+#define PORT2_OUT_P14_Pos                     14                                                      /*!< PORT2 OUT: P14 Position                 */\r
+#define PORT2_OUT_P14_Msk                     (0x01UL << PORT2_OUT_P14_Pos)                           /*!< PORT2 OUT: P14 Mask                     */\r
+#define PORT2_OUT_P15_Pos                     15                                                      /*!< PORT2 OUT: P15 Position                 */\r
+#define PORT2_OUT_P15_Msk                     (0x01UL << PORT2_OUT_P15_Pos)                           /*!< PORT2 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT2_OMR  --------------------------------- */\r
+#define PORT2_OMR_PS0_Pos                     0                                                       /*!< PORT2 OMR: PS0 Position                 */\r
+#define PORT2_OMR_PS0_Msk                     (0x01UL << PORT2_OMR_PS0_Pos)                           /*!< PORT2 OMR: PS0 Mask                     */\r
+#define PORT2_OMR_PS1_Pos                     1                                                       /*!< PORT2 OMR: PS1 Position                 */\r
+#define PORT2_OMR_PS1_Msk                     (0x01UL << PORT2_OMR_PS1_Pos)                           /*!< PORT2 OMR: PS1 Mask                     */\r
+#define PORT2_OMR_PS2_Pos                     2                                                       /*!< PORT2 OMR: PS2 Position                 */\r
+#define PORT2_OMR_PS2_Msk                     (0x01UL << PORT2_OMR_PS2_Pos)                           /*!< PORT2 OMR: PS2 Mask                     */\r
+#define PORT2_OMR_PS3_Pos                     3                                                       /*!< PORT2 OMR: PS3 Position                 */\r
+#define PORT2_OMR_PS3_Msk                     (0x01UL << PORT2_OMR_PS3_Pos)                           /*!< PORT2 OMR: PS3 Mask                     */\r
+#define PORT2_OMR_PS4_Pos                     4                                                       /*!< PORT2 OMR: PS4 Position                 */\r
+#define PORT2_OMR_PS4_Msk                     (0x01UL << PORT2_OMR_PS4_Pos)                           /*!< PORT2 OMR: PS4 Mask                     */\r
+#define PORT2_OMR_PS5_Pos                     5                                                       /*!< PORT2 OMR: PS5 Position                 */\r
+#define PORT2_OMR_PS5_Msk                     (0x01UL << PORT2_OMR_PS5_Pos)                           /*!< PORT2 OMR: PS5 Mask                     */\r
+#define PORT2_OMR_PS6_Pos                     6                                                       /*!< PORT2 OMR: PS6 Position                 */\r
+#define PORT2_OMR_PS6_Msk                     (0x01UL << PORT2_OMR_PS6_Pos)                           /*!< PORT2 OMR: PS6 Mask                     */\r
+#define PORT2_OMR_PS7_Pos                     7                                                       /*!< PORT2 OMR: PS7 Position                 */\r
+#define PORT2_OMR_PS7_Msk                     (0x01UL << PORT2_OMR_PS7_Pos)                           /*!< PORT2 OMR: PS7 Mask                     */\r
+#define PORT2_OMR_PS8_Pos                     8                                                       /*!< PORT2 OMR: PS8 Position                 */\r
+#define PORT2_OMR_PS8_Msk                     (0x01UL << PORT2_OMR_PS8_Pos)                           /*!< PORT2 OMR: PS8 Mask                     */\r
+#define PORT2_OMR_PS9_Pos                     9                                                       /*!< PORT2 OMR: PS9 Position                 */\r
+#define PORT2_OMR_PS9_Msk                     (0x01UL << PORT2_OMR_PS9_Pos)                           /*!< PORT2 OMR: PS9 Mask                     */\r
+#define PORT2_OMR_PS10_Pos                    10                                                      /*!< PORT2 OMR: PS10 Position                */\r
+#define PORT2_OMR_PS10_Msk                    (0x01UL << PORT2_OMR_PS10_Pos)                          /*!< PORT2 OMR: PS10 Mask                    */\r
+#define PORT2_OMR_PS11_Pos                    11                                                      /*!< PORT2 OMR: PS11 Position                */\r
+#define PORT2_OMR_PS11_Msk                    (0x01UL << PORT2_OMR_PS11_Pos)                          /*!< PORT2 OMR: PS11 Mask                    */\r
+#define PORT2_OMR_PS12_Pos                    12                                                      /*!< PORT2 OMR: PS12 Position                */\r
+#define PORT2_OMR_PS12_Msk                    (0x01UL << PORT2_OMR_PS12_Pos)                          /*!< PORT2 OMR: PS12 Mask                    */\r
+#define PORT2_OMR_PS13_Pos                    13                                                      /*!< PORT2 OMR: PS13 Position                */\r
+#define PORT2_OMR_PS13_Msk                    (0x01UL << PORT2_OMR_PS13_Pos)                          /*!< PORT2 OMR: PS13 Mask                    */\r
+#define PORT2_OMR_PS14_Pos                    14                                                      /*!< PORT2 OMR: PS14 Position                */\r
+#define PORT2_OMR_PS14_Msk                    (0x01UL << PORT2_OMR_PS14_Pos)                          /*!< PORT2 OMR: PS14 Mask                    */\r
+#define PORT2_OMR_PS15_Pos                    15                                                      /*!< PORT2 OMR: PS15 Position                */\r
+#define PORT2_OMR_PS15_Msk                    (0x01UL << PORT2_OMR_PS15_Pos)                          /*!< PORT2 OMR: PS15 Mask                    */\r
+#define PORT2_OMR_PR0_Pos                     16                                                      /*!< PORT2 OMR: PR0 Position                 */\r
+#define PORT2_OMR_PR0_Msk                     (0x01UL << PORT2_OMR_PR0_Pos)                           /*!< PORT2 OMR: PR0 Mask                     */\r
+#define PORT2_OMR_PR1_Pos                     17                                                      /*!< PORT2 OMR: PR1 Position                 */\r
+#define PORT2_OMR_PR1_Msk                     (0x01UL << PORT2_OMR_PR1_Pos)                           /*!< PORT2 OMR: PR1 Mask                     */\r
+#define PORT2_OMR_PR2_Pos                     18                                                      /*!< PORT2 OMR: PR2 Position                 */\r
+#define PORT2_OMR_PR2_Msk                     (0x01UL << PORT2_OMR_PR2_Pos)                           /*!< PORT2 OMR: PR2 Mask                     */\r
+#define PORT2_OMR_PR3_Pos                     19                                                      /*!< PORT2 OMR: PR3 Position                 */\r
+#define PORT2_OMR_PR3_Msk                     (0x01UL << PORT2_OMR_PR3_Pos)                           /*!< PORT2 OMR: PR3 Mask                     */\r
+#define PORT2_OMR_PR4_Pos                     20                                                      /*!< PORT2 OMR: PR4 Position                 */\r
+#define PORT2_OMR_PR4_Msk                     (0x01UL << PORT2_OMR_PR4_Pos)                           /*!< PORT2 OMR: PR4 Mask                     */\r
+#define PORT2_OMR_PR5_Pos                     21                                                      /*!< PORT2 OMR: PR5 Position                 */\r
+#define PORT2_OMR_PR5_Msk                     (0x01UL << PORT2_OMR_PR5_Pos)                           /*!< PORT2 OMR: PR5 Mask                     */\r
+#define PORT2_OMR_PR6_Pos                     22                                                      /*!< PORT2 OMR: PR6 Position                 */\r
+#define PORT2_OMR_PR6_Msk                     (0x01UL << PORT2_OMR_PR6_Pos)                           /*!< PORT2 OMR: PR6 Mask                     */\r
+#define PORT2_OMR_PR7_Pos                     23                                                      /*!< PORT2 OMR: PR7 Position                 */\r
+#define PORT2_OMR_PR7_Msk                     (0x01UL << PORT2_OMR_PR7_Pos)                           /*!< PORT2 OMR: PR7 Mask                     */\r
+#define PORT2_OMR_PR8_Pos                     24                                                      /*!< PORT2 OMR: PR8 Position                 */\r
+#define PORT2_OMR_PR8_Msk                     (0x01UL << PORT2_OMR_PR8_Pos)                           /*!< PORT2 OMR: PR8 Mask                     */\r
+#define PORT2_OMR_PR9_Pos                     25                                                      /*!< PORT2 OMR: PR9 Position                 */\r
+#define PORT2_OMR_PR9_Msk                     (0x01UL << PORT2_OMR_PR9_Pos)                           /*!< PORT2 OMR: PR9 Mask                     */\r
+#define PORT2_OMR_PR10_Pos                    26                                                      /*!< PORT2 OMR: PR10 Position                */\r
+#define PORT2_OMR_PR10_Msk                    (0x01UL << PORT2_OMR_PR10_Pos)                          /*!< PORT2 OMR: PR10 Mask                    */\r
+#define PORT2_OMR_PR11_Pos                    27                                                      /*!< PORT2 OMR: PR11 Position                */\r
+#define PORT2_OMR_PR11_Msk                    (0x01UL << PORT2_OMR_PR11_Pos)                          /*!< PORT2 OMR: PR11 Mask                    */\r
+#define PORT2_OMR_PR12_Pos                    28                                                      /*!< PORT2 OMR: PR12 Position                */\r
+#define PORT2_OMR_PR12_Msk                    (0x01UL << PORT2_OMR_PR12_Pos)                          /*!< PORT2 OMR: PR12 Mask                    */\r
+#define PORT2_OMR_PR13_Pos                    29                                                      /*!< PORT2 OMR: PR13 Position                */\r
+#define PORT2_OMR_PR13_Msk                    (0x01UL << PORT2_OMR_PR13_Pos)                          /*!< PORT2 OMR: PR13 Mask                    */\r
+#define PORT2_OMR_PR14_Pos                    30                                                      /*!< PORT2 OMR: PR14 Position                */\r
+#define PORT2_OMR_PR14_Msk                    (0x01UL << PORT2_OMR_PR14_Pos)                          /*!< PORT2 OMR: PR14 Mask                    */\r
+#define PORT2_OMR_PR15_Pos                    31                                                      /*!< PORT2 OMR: PR15 Position                */\r
+#define PORT2_OMR_PR15_Msk                    (0x01UL << PORT2_OMR_PR15_Pos)                          /*!< PORT2 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT2_IOCR0  -------------------------------- */\r
+#define PORT2_IOCR0_PC0_Pos                   3                                                       /*!< PORT2 IOCR0: PC0 Position               */\r
+#define PORT2_IOCR0_PC0_Msk                   (0x1fUL << PORT2_IOCR0_PC0_Pos)                         /*!< PORT2 IOCR0: PC0 Mask                   */\r
+#define PORT2_IOCR0_PC1_Pos                   11                                                      /*!< PORT2 IOCR0: PC1 Position               */\r
+#define PORT2_IOCR0_PC1_Msk                   (0x1fUL << PORT2_IOCR0_PC1_Pos)                         /*!< PORT2 IOCR0: PC1 Mask                   */\r
+#define PORT2_IOCR0_PC2_Pos                   19                                                      /*!< PORT2 IOCR0: PC2 Position               */\r
+#define PORT2_IOCR0_PC2_Msk                   (0x1fUL << PORT2_IOCR0_PC2_Pos)                         /*!< PORT2 IOCR0: PC2 Mask                   */\r
+#define PORT2_IOCR0_PC3_Pos                   27                                                      /*!< PORT2 IOCR0: PC3 Position               */\r
+#define PORT2_IOCR0_PC3_Msk                   (0x1fUL << PORT2_IOCR0_PC3_Pos)                         /*!< PORT2 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_IOCR4  -------------------------------- */\r
+#define PORT2_IOCR4_PC4_Pos                   3                                                       /*!< PORT2 IOCR4: PC4 Position               */\r
+#define PORT2_IOCR4_PC4_Msk                   (0x1fUL << PORT2_IOCR4_PC4_Pos)                         /*!< PORT2 IOCR4: PC4 Mask                   */\r
+#define PORT2_IOCR4_PC5_Pos                   11                                                      /*!< PORT2 IOCR4: PC5 Position               */\r
+#define PORT2_IOCR4_PC5_Msk                   (0x1fUL << PORT2_IOCR4_PC5_Pos)                         /*!< PORT2 IOCR4: PC5 Mask                   */\r
+#define PORT2_IOCR4_PC6_Pos                   19                                                      /*!< PORT2 IOCR4: PC6 Position               */\r
+#define PORT2_IOCR4_PC6_Msk                   (0x1fUL << PORT2_IOCR4_PC6_Pos)                         /*!< PORT2 IOCR4: PC6 Mask                   */\r
+#define PORT2_IOCR4_PC7_Pos                   27                                                      /*!< PORT2 IOCR4: PC7 Position               */\r
+#define PORT2_IOCR4_PC7_Msk                   (0x1fUL << PORT2_IOCR4_PC7_Pos)                         /*!< PORT2 IOCR4: PC7 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_IOCR8  -------------------------------- */\r
+#define PORT2_IOCR8_PC8_Pos                   3                                                       /*!< PORT2 IOCR8: PC8 Position               */\r
+#define PORT2_IOCR8_PC8_Msk                   (0x1fUL << PORT2_IOCR8_PC8_Pos)                         /*!< PORT2 IOCR8: PC8 Mask                   */\r
+#define PORT2_IOCR8_PC9_Pos                   11                                                      /*!< PORT2 IOCR8: PC9 Position               */\r
+#define PORT2_IOCR8_PC9_Msk                   (0x1fUL << PORT2_IOCR8_PC9_Pos)                         /*!< PORT2 IOCR8: PC9 Mask                   */\r
+#define PORT2_IOCR8_PC10_Pos                  19                                                      /*!< PORT2 IOCR8: PC10 Position              */\r
+#define PORT2_IOCR8_PC10_Msk                  (0x1fUL << PORT2_IOCR8_PC10_Pos)                        /*!< PORT2 IOCR8: PC10 Mask                  */\r
+#define PORT2_IOCR8_PC11_Pos                  27                                                      /*!< PORT2 IOCR8: PC11 Position              */\r
+#define PORT2_IOCR8_PC11_Msk                  (0x1fUL << PORT2_IOCR8_PC11_Pos)                        /*!< PORT2 IOCR8: PC11 Mask                  */\r
+\r
+/* --------------------------------  PORT2_IOCR12  -------------------------------- */\r
+#define PORT2_IOCR12_PC12_Pos                 3                                                       /*!< PORT2 IOCR12: PC12 Position             */\r
+#define PORT2_IOCR12_PC12_Msk                 (0x1fUL << PORT2_IOCR12_PC12_Pos)                       /*!< PORT2 IOCR12: PC12 Mask                 */\r
+#define PORT2_IOCR12_PC13_Pos                 11                                                      /*!< PORT2 IOCR12: PC13 Position             */\r
+#define PORT2_IOCR12_PC13_Msk                 (0x1fUL << PORT2_IOCR12_PC13_Pos)                       /*!< PORT2 IOCR12: PC13 Mask                 */\r
+#define PORT2_IOCR12_PC14_Pos                 19                                                      /*!< PORT2 IOCR12: PC14 Position             */\r
+#define PORT2_IOCR12_PC14_Msk                 (0x1fUL << PORT2_IOCR12_PC14_Pos)                       /*!< PORT2 IOCR12: PC14 Mask                 */\r
+#define PORT2_IOCR12_PC15_Pos                 27                                                      /*!< PORT2 IOCR12: PC15 Position             */\r
+#define PORT2_IOCR12_PC15_Msk                 (0x1fUL << PORT2_IOCR12_PC15_Pos)                       /*!< PORT2 IOCR12: PC15 Mask                 */\r
+\r
+/* ----------------------------------  PORT2_IN  ---------------------------------- */\r
+#define PORT2_IN_P0_Pos                       0                                                       /*!< PORT2 IN: P0 Position                   */\r
+#define PORT2_IN_P0_Msk                       (0x01UL << PORT2_IN_P0_Pos)                             /*!< PORT2 IN: P0 Mask                       */\r
+#define PORT2_IN_P1_Pos                       1                                                       /*!< PORT2 IN: P1 Position                   */\r
+#define PORT2_IN_P1_Msk                       (0x01UL << PORT2_IN_P1_Pos)                             /*!< PORT2 IN: P1 Mask                       */\r
+#define PORT2_IN_P2_Pos                       2                                                       /*!< PORT2 IN: P2 Position                   */\r
+#define PORT2_IN_P2_Msk                       (0x01UL << PORT2_IN_P2_Pos)                             /*!< PORT2 IN: P2 Mask                       */\r
+#define PORT2_IN_P3_Pos                       3                                                       /*!< PORT2 IN: P3 Position                   */\r
+#define PORT2_IN_P3_Msk                       (0x01UL << PORT2_IN_P3_Pos)                             /*!< PORT2 IN: P3 Mask                       */\r
+#define PORT2_IN_P4_Pos                       4                                                       /*!< PORT2 IN: P4 Position                   */\r
+#define PORT2_IN_P4_Msk                       (0x01UL << PORT2_IN_P4_Pos)                             /*!< PORT2 IN: P4 Mask                       */\r
+#define PORT2_IN_P5_Pos                       5                                                       /*!< PORT2 IN: P5 Position                   */\r
+#define PORT2_IN_P5_Msk                       (0x01UL << PORT2_IN_P5_Pos)                             /*!< PORT2 IN: P5 Mask                       */\r
+#define PORT2_IN_P6_Pos                       6                                                       /*!< PORT2 IN: P6 Position                   */\r
+#define PORT2_IN_P6_Msk                       (0x01UL << PORT2_IN_P6_Pos)                             /*!< PORT2 IN: P6 Mask                       */\r
+#define PORT2_IN_P7_Pos                       7                                                       /*!< PORT2 IN: P7 Position                   */\r
+#define PORT2_IN_P7_Msk                       (0x01UL << PORT2_IN_P7_Pos)                             /*!< PORT2 IN: P7 Mask                       */\r
+#define PORT2_IN_P8_Pos                       8                                                       /*!< PORT2 IN: P8 Position                   */\r
+#define PORT2_IN_P8_Msk                       (0x01UL << PORT2_IN_P8_Pos)                             /*!< PORT2 IN: P8 Mask                       */\r
+#define PORT2_IN_P9_Pos                       9                                                       /*!< PORT2 IN: P9 Position                   */\r
+#define PORT2_IN_P9_Msk                       (0x01UL << PORT2_IN_P9_Pos)                             /*!< PORT2 IN: P9 Mask                       */\r
+#define PORT2_IN_P10_Pos                      10                                                      /*!< PORT2 IN: P10 Position                  */\r
+#define PORT2_IN_P10_Msk                      (0x01UL << PORT2_IN_P10_Pos)                            /*!< PORT2 IN: P10 Mask                      */\r
+#define PORT2_IN_P11_Pos                      11                                                      /*!< PORT2 IN: P11 Position                  */\r
+#define PORT2_IN_P11_Msk                      (0x01UL << PORT2_IN_P11_Pos)                            /*!< PORT2 IN: P11 Mask                      */\r
+#define PORT2_IN_P12_Pos                      12                                                      /*!< PORT2 IN: P12 Position                  */\r
+#define PORT2_IN_P12_Msk                      (0x01UL << PORT2_IN_P12_Pos)                            /*!< PORT2 IN: P12 Mask                      */\r
+#define PORT2_IN_P13_Pos                      13                                                      /*!< PORT2 IN: P13 Position                  */\r
+#define PORT2_IN_P13_Msk                      (0x01UL << PORT2_IN_P13_Pos)                            /*!< PORT2 IN: P13 Mask                      */\r
+#define PORT2_IN_P14_Pos                      14                                                      /*!< PORT2 IN: P14 Position                  */\r
+#define PORT2_IN_P14_Msk                      (0x01UL << PORT2_IN_P14_Pos)                            /*!< PORT2 IN: P14 Mask                      */\r
+#define PORT2_IN_P15_Pos                      15                                                      /*!< PORT2 IN: P15 Position                  */\r
+#define PORT2_IN_P15_Msk                      (0x01UL << PORT2_IN_P15_Pos)                            /*!< PORT2 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT2_PDR0  --------------------------------- */\r
+#define PORT2_PDR0_PD0_Pos                    0                                                       /*!< PORT2 PDR0: PD0 Position                */\r
+#define PORT2_PDR0_PD0_Msk                    (0x07UL << PORT2_PDR0_PD0_Pos)                          /*!< PORT2 PDR0: PD0 Mask                    */\r
+#define PORT2_PDR0_PD1_Pos                    4                                                       /*!< PORT2 PDR0: PD1 Position                */\r
+#define PORT2_PDR0_PD1_Msk                    (0x07UL << PORT2_PDR0_PD1_Pos)                          /*!< PORT2 PDR0: PD1 Mask                    */\r
+#define PORT2_PDR0_PD2_Pos                    8                                                       /*!< PORT2 PDR0: PD2 Position                */\r
+#define PORT2_PDR0_PD2_Msk                    (0x07UL << PORT2_PDR0_PD2_Pos)                          /*!< PORT2 PDR0: PD2 Mask                    */\r
+#define PORT2_PDR0_PD3_Pos                    12                                                      /*!< PORT2 PDR0: PD3 Position                */\r
+#define PORT2_PDR0_PD3_Msk                    (0x07UL << PORT2_PDR0_PD3_Pos)                          /*!< PORT2 PDR0: PD3 Mask                    */\r
+#define PORT2_PDR0_PD4_Pos                    16                                                      /*!< PORT2 PDR0: PD4 Position                */\r
+#define PORT2_PDR0_PD4_Msk                    (0x07UL << PORT2_PDR0_PD4_Pos)                          /*!< PORT2 PDR0: PD4 Mask                    */\r
+#define PORT2_PDR0_PD5_Pos                    20                                                      /*!< PORT2 PDR0: PD5 Position                */\r
+#define PORT2_PDR0_PD5_Msk                    (0x07UL << PORT2_PDR0_PD5_Pos)                          /*!< PORT2 PDR0: PD5 Mask                    */\r
+#define PORT2_PDR0_PD6_Pos                    24                                                      /*!< PORT2 PDR0: PD6 Position                */\r
+#define PORT2_PDR0_PD6_Msk                    (0x07UL << PORT2_PDR0_PD6_Pos)                          /*!< PORT2 PDR0: PD6 Mask                    */\r
+#define PORT2_PDR0_PD7_Pos                    28                                                      /*!< PORT2 PDR0: PD7 Position                */\r
+#define PORT2_PDR0_PD7_Msk                    (0x07UL << PORT2_PDR0_PD7_Pos)                          /*!< PORT2 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT2_PDR1  --------------------------------- */\r
+#define PORT2_PDR1_PD8_Pos                    0                                                       /*!< PORT2 PDR1: PD8 Position                */\r
+#define PORT2_PDR1_PD8_Msk                    (0x07UL << PORT2_PDR1_PD8_Pos)                          /*!< PORT2 PDR1: PD8 Mask                    */\r
+#define PORT2_PDR1_PD9_Pos                    4                                                       /*!< PORT2 PDR1: PD9 Position                */\r
+#define PORT2_PDR1_PD9_Msk                    (0x07UL << PORT2_PDR1_PD9_Pos)                          /*!< PORT2 PDR1: PD9 Mask                    */\r
+#define PORT2_PDR1_PD10_Pos                   8                                                       /*!< PORT2 PDR1: PD10 Position               */\r
+#define PORT2_PDR1_PD10_Msk                   (0x07UL << PORT2_PDR1_PD10_Pos)                         /*!< PORT2 PDR1: PD10 Mask                   */\r
+#define PORT2_PDR1_PD11_Pos                   12                                                      /*!< PORT2 PDR1: PD11 Position               */\r
+#define PORT2_PDR1_PD11_Msk                   (0x07UL << PORT2_PDR1_PD11_Pos)                         /*!< PORT2 PDR1: PD11 Mask                   */\r
+#define PORT2_PDR1_PD12_Pos                   16                                                      /*!< PORT2 PDR1: PD12 Position               */\r
+#define PORT2_PDR1_PD12_Msk                   (0x07UL << PORT2_PDR1_PD12_Pos)                         /*!< PORT2 PDR1: PD12 Mask                   */\r
+#define PORT2_PDR1_PD13_Pos                   20                                                      /*!< PORT2 PDR1: PD13 Position               */\r
+#define PORT2_PDR1_PD13_Msk                   (0x07UL << PORT2_PDR1_PD13_Pos)                         /*!< PORT2 PDR1: PD13 Mask                   */\r
+#define PORT2_PDR1_PD14_Pos                   24                                                      /*!< PORT2 PDR1: PD14 Position               */\r
+#define PORT2_PDR1_PD14_Msk                   (0x07UL << PORT2_PDR1_PD14_Pos)                         /*!< PORT2 PDR1: PD14 Mask                   */\r
+#define PORT2_PDR1_PD15_Pos                   28                                                      /*!< PORT2 PDR1: PD15 Position               */\r
+#define PORT2_PDR1_PD15_Msk                   (0x07UL << PORT2_PDR1_PD15_Pos)                         /*!< PORT2 PDR1: PD15 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_PDISC  -------------------------------- */\r
+#define PORT2_PDISC_PDIS0_Pos                 0                                                       /*!< PORT2 PDISC: PDIS0 Position             */\r
+#define PORT2_PDISC_PDIS0_Msk                 (0x01UL << PORT2_PDISC_PDIS0_Pos)                       /*!< PORT2 PDISC: PDIS0 Mask                 */\r
+#define PORT2_PDISC_PDIS1_Pos                 1                                                       /*!< PORT2 PDISC: PDIS1 Position             */\r
+#define PORT2_PDISC_PDIS1_Msk                 (0x01UL << PORT2_PDISC_PDIS1_Pos)                       /*!< PORT2 PDISC: PDIS1 Mask                 */\r
+#define PORT2_PDISC_PDIS2_Pos                 2                                                       /*!< PORT2 PDISC: PDIS2 Position             */\r
+#define PORT2_PDISC_PDIS2_Msk                 (0x01UL << PORT2_PDISC_PDIS2_Pos)                       /*!< PORT2 PDISC: PDIS2 Mask                 */\r
+#define PORT2_PDISC_PDIS3_Pos                 3                                                       /*!< PORT2 PDISC: PDIS3 Position             */\r
+#define PORT2_PDISC_PDIS3_Msk                 (0x01UL << PORT2_PDISC_PDIS3_Pos)                       /*!< PORT2 PDISC: PDIS3 Mask                 */\r
+#define PORT2_PDISC_PDIS4_Pos                 4                                                       /*!< PORT2 PDISC: PDIS4 Position             */\r
+#define PORT2_PDISC_PDIS4_Msk                 (0x01UL << PORT2_PDISC_PDIS4_Pos)                       /*!< PORT2 PDISC: PDIS4 Mask                 */\r
+#define PORT2_PDISC_PDIS5_Pos                 5                                                       /*!< PORT2 PDISC: PDIS5 Position             */\r
+#define PORT2_PDISC_PDIS5_Msk                 (0x01UL << PORT2_PDISC_PDIS5_Pos)                       /*!< PORT2 PDISC: PDIS5 Mask                 */\r
+#define PORT2_PDISC_PDIS6_Pos                 6                                                       /*!< PORT2 PDISC: PDIS6 Position             */\r
+#define PORT2_PDISC_PDIS6_Msk                 (0x01UL << PORT2_PDISC_PDIS6_Pos)                       /*!< PORT2 PDISC: PDIS6 Mask                 */\r
+#define PORT2_PDISC_PDIS7_Pos                 7                                                       /*!< PORT2 PDISC: PDIS7 Position             */\r
+#define PORT2_PDISC_PDIS7_Msk                 (0x01UL << PORT2_PDISC_PDIS7_Pos)                       /*!< PORT2 PDISC: PDIS7 Mask                 */\r
+#define PORT2_PDISC_PDIS8_Pos                 8                                                       /*!< PORT2 PDISC: PDIS8 Position             */\r
+#define PORT2_PDISC_PDIS8_Msk                 (0x01UL << PORT2_PDISC_PDIS8_Pos)                       /*!< PORT2 PDISC: PDIS8 Mask                 */\r
+#define PORT2_PDISC_PDIS9_Pos                 9                                                       /*!< PORT2 PDISC: PDIS9 Position             */\r
+#define PORT2_PDISC_PDIS9_Msk                 (0x01UL << PORT2_PDISC_PDIS9_Pos)                       /*!< PORT2 PDISC: PDIS9 Mask                 */\r
+#define PORT2_PDISC_PDIS10_Pos                10                                                      /*!< PORT2 PDISC: PDIS10 Position            */\r
+#define PORT2_PDISC_PDIS10_Msk                (0x01UL << PORT2_PDISC_PDIS10_Pos)                      /*!< PORT2 PDISC: PDIS10 Mask                */\r
+#define PORT2_PDISC_PDIS11_Pos                11                                                      /*!< PORT2 PDISC: PDIS11 Position            */\r
+#define PORT2_PDISC_PDIS11_Msk                (0x01UL << PORT2_PDISC_PDIS11_Pos)                      /*!< PORT2 PDISC: PDIS11 Mask                */\r
+#define PORT2_PDISC_PDIS12_Pos                12                                                      /*!< PORT2 PDISC: PDIS12 Position            */\r
+#define PORT2_PDISC_PDIS12_Msk                (0x01UL << PORT2_PDISC_PDIS12_Pos)                      /*!< PORT2 PDISC: PDIS12 Mask                */\r
+#define PORT2_PDISC_PDIS13_Pos                13                                                      /*!< PORT2 PDISC: PDIS13 Position            */\r
+#define PORT2_PDISC_PDIS13_Msk                (0x01UL << PORT2_PDISC_PDIS13_Pos)                      /*!< PORT2 PDISC: PDIS13 Mask                */\r
+#define PORT2_PDISC_PDIS14_Pos                14                                                      /*!< PORT2 PDISC: PDIS14 Position            */\r
+#define PORT2_PDISC_PDIS14_Msk                (0x01UL << PORT2_PDISC_PDIS14_Pos)                      /*!< PORT2 PDISC: PDIS14 Mask                */\r
+#define PORT2_PDISC_PDIS15_Pos                15                                                      /*!< PORT2 PDISC: PDIS15 Position            */\r
+#define PORT2_PDISC_PDIS15_Msk                (0x01UL << PORT2_PDISC_PDIS15_Pos)                      /*!< PORT2 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT2_PPS  --------------------------------- */\r
+#define PORT2_PPS_PPS0_Pos                    0                                                       /*!< PORT2 PPS: PPS0 Position                */\r
+#define PORT2_PPS_PPS0_Msk                    (0x01UL << PORT2_PPS_PPS0_Pos)                          /*!< PORT2 PPS: PPS0 Mask                    */\r
+#define PORT2_PPS_PPS1_Pos                    1                                                       /*!< PORT2 PPS: PPS1 Position                */\r
+#define PORT2_PPS_PPS1_Msk                    (0x01UL << PORT2_PPS_PPS1_Pos)                          /*!< PORT2 PPS: PPS1 Mask                    */\r
+#define PORT2_PPS_PPS2_Pos                    2                                                       /*!< PORT2 PPS: PPS2 Position                */\r
+#define PORT2_PPS_PPS2_Msk                    (0x01UL << PORT2_PPS_PPS2_Pos)                          /*!< PORT2 PPS: PPS2 Mask                    */\r
+#define PORT2_PPS_PPS3_Pos                    3                                                       /*!< PORT2 PPS: PPS3 Position                */\r
+#define PORT2_PPS_PPS3_Msk                    (0x01UL << PORT2_PPS_PPS3_Pos)                          /*!< PORT2 PPS: PPS3 Mask                    */\r
+#define PORT2_PPS_PPS4_Pos                    4                                                       /*!< PORT2 PPS: PPS4 Position                */\r
+#define PORT2_PPS_PPS4_Msk                    (0x01UL << PORT2_PPS_PPS4_Pos)                          /*!< PORT2 PPS: PPS4 Mask                    */\r
+#define PORT2_PPS_PPS5_Pos                    5                                                       /*!< PORT2 PPS: PPS5 Position                */\r
+#define PORT2_PPS_PPS5_Msk                    (0x01UL << PORT2_PPS_PPS5_Pos)                          /*!< PORT2 PPS: PPS5 Mask                    */\r
+#define PORT2_PPS_PPS6_Pos                    6                                                       /*!< PORT2 PPS: PPS6 Position                */\r
+#define PORT2_PPS_PPS6_Msk                    (0x01UL << PORT2_PPS_PPS6_Pos)                          /*!< PORT2 PPS: PPS6 Mask                    */\r
+#define PORT2_PPS_PPS7_Pos                    7                                                       /*!< PORT2 PPS: PPS7 Position                */\r
+#define PORT2_PPS_PPS7_Msk                    (0x01UL << PORT2_PPS_PPS7_Pos)                          /*!< PORT2 PPS: PPS7 Mask                    */\r
+#define PORT2_PPS_PPS8_Pos                    8                                                       /*!< PORT2 PPS: PPS8 Position                */\r
+#define PORT2_PPS_PPS8_Msk                    (0x01UL << PORT2_PPS_PPS8_Pos)                          /*!< PORT2 PPS: PPS8 Mask                    */\r
+#define PORT2_PPS_PPS9_Pos                    9                                                       /*!< PORT2 PPS: PPS9 Position                */\r
+#define PORT2_PPS_PPS9_Msk                    (0x01UL << PORT2_PPS_PPS9_Pos)                          /*!< PORT2 PPS: PPS9 Mask                    */\r
+#define PORT2_PPS_PPS10_Pos                   10                                                      /*!< PORT2 PPS: PPS10 Position               */\r
+#define PORT2_PPS_PPS10_Msk                   (0x01UL << PORT2_PPS_PPS10_Pos)                         /*!< PORT2 PPS: PPS10 Mask                   */\r
+#define PORT2_PPS_PPS11_Pos                   11                                                      /*!< PORT2 PPS: PPS11 Position               */\r
+#define PORT2_PPS_PPS11_Msk                   (0x01UL << PORT2_PPS_PPS11_Pos)                         /*!< PORT2 PPS: PPS11 Mask                   */\r
+#define PORT2_PPS_PPS12_Pos                   12                                                      /*!< PORT2 PPS: PPS12 Position               */\r
+#define PORT2_PPS_PPS12_Msk                   (0x01UL << PORT2_PPS_PPS12_Pos)                         /*!< PORT2 PPS: PPS12 Mask                   */\r
+#define PORT2_PPS_PPS13_Pos                   13                                                      /*!< PORT2 PPS: PPS13 Position               */\r
+#define PORT2_PPS_PPS13_Msk                   (0x01UL << PORT2_PPS_PPS13_Pos)                         /*!< PORT2 PPS: PPS13 Mask                   */\r
+#define PORT2_PPS_PPS14_Pos                   14                                                      /*!< PORT2 PPS: PPS14 Position               */\r
+#define PORT2_PPS_PPS14_Msk                   (0x01UL << PORT2_PPS_PPS14_Pos)                         /*!< PORT2 PPS: PPS14 Mask                   */\r
+#define PORT2_PPS_PPS15_Pos                   15                                                      /*!< PORT2 PPS: PPS15 Position               */\r
+#define PORT2_PPS_PPS15_Msk                   (0x01UL << PORT2_PPS_PPS15_Pos)                         /*!< PORT2 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT2_HWSEL  -------------------------------- */\r
+#define PORT2_HWSEL_HW0_Pos                   0                                                       /*!< PORT2 HWSEL: HW0 Position               */\r
+#define PORT2_HWSEL_HW0_Msk                   (0x03UL << PORT2_HWSEL_HW0_Pos)                         /*!< PORT2 HWSEL: HW0 Mask                   */\r
+#define PORT2_HWSEL_HW1_Pos                   2                                                       /*!< PORT2 HWSEL: HW1 Position               */\r
+#define PORT2_HWSEL_HW1_Msk                   (0x03UL << PORT2_HWSEL_HW1_Pos)                         /*!< PORT2 HWSEL: HW1 Mask                   */\r
+#define PORT2_HWSEL_HW2_Pos                   4                                                       /*!< PORT2 HWSEL: HW2 Position               */\r
+#define PORT2_HWSEL_HW2_Msk                   (0x03UL << PORT2_HWSEL_HW2_Pos)                         /*!< PORT2 HWSEL: HW2 Mask                   */\r
+#define PORT2_HWSEL_HW3_Pos                   6                                                       /*!< PORT2 HWSEL: HW3 Position               */\r
+#define PORT2_HWSEL_HW3_Msk                   (0x03UL << PORT2_HWSEL_HW3_Pos)                         /*!< PORT2 HWSEL: HW3 Mask                   */\r
+#define PORT2_HWSEL_HW4_Pos                   8                                                       /*!< PORT2 HWSEL: HW4 Position               */\r
+#define PORT2_HWSEL_HW4_Msk                   (0x03UL << PORT2_HWSEL_HW4_Pos)                         /*!< PORT2 HWSEL: HW4 Mask                   */\r
+#define PORT2_HWSEL_HW5_Pos                   10                                                      /*!< PORT2 HWSEL: HW5 Position               */\r
+#define PORT2_HWSEL_HW5_Msk                   (0x03UL << PORT2_HWSEL_HW5_Pos)                         /*!< PORT2 HWSEL: HW5 Mask                   */\r
+#define PORT2_HWSEL_HW6_Pos                   12                                                      /*!< PORT2 HWSEL: HW6 Position               */\r
+#define PORT2_HWSEL_HW6_Msk                   (0x03UL << PORT2_HWSEL_HW6_Pos)                         /*!< PORT2 HWSEL: HW6 Mask                   */\r
+#define PORT2_HWSEL_HW7_Pos                   14                                                      /*!< PORT2 HWSEL: HW7 Position               */\r
+#define PORT2_HWSEL_HW7_Msk                   (0x03UL << PORT2_HWSEL_HW7_Pos)                         /*!< PORT2 HWSEL: HW7 Mask                   */\r
+#define PORT2_HWSEL_HW8_Pos                   16                                                      /*!< PORT2 HWSEL: HW8 Position               */\r
+#define PORT2_HWSEL_HW8_Msk                   (0x03UL << PORT2_HWSEL_HW8_Pos)                         /*!< PORT2 HWSEL: HW8 Mask                   */\r
+#define PORT2_HWSEL_HW9_Pos                   18                                                      /*!< PORT2 HWSEL: HW9 Position               */\r
+#define PORT2_HWSEL_HW9_Msk                   (0x03UL << PORT2_HWSEL_HW9_Pos)                         /*!< PORT2 HWSEL: HW9 Mask                   */\r
+#define PORT2_HWSEL_HW10_Pos                  20                                                      /*!< PORT2 HWSEL: HW10 Position              */\r
+#define PORT2_HWSEL_HW10_Msk                  (0x03UL << PORT2_HWSEL_HW10_Pos)                        /*!< PORT2 HWSEL: HW10 Mask                  */\r
+#define PORT2_HWSEL_HW11_Pos                  22                                                      /*!< PORT2 HWSEL: HW11 Position              */\r
+#define PORT2_HWSEL_HW11_Msk                  (0x03UL << PORT2_HWSEL_HW11_Pos)                        /*!< PORT2 HWSEL: HW11 Mask                  */\r
+#define PORT2_HWSEL_HW12_Pos                  24                                                      /*!< PORT2 HWSEL: HW12 Position              */\r
+#define PORT2_HWSEL_HW12_Msk                  (0x03UL << PORT2_HWSEL_HW12_Pos)                        /*!< PORT2 HWSEL: HW12 Mask                  */\r
+#define PORT2_HWSEL_HW13_Pos                  26                                                      /*!< PORT2 HWSEL: HW13 Position              */\r
+#define PORT2_HWSEL_HW13_Msk                  (0x03UL << PORT2_HWSEL_HW13_Pos)                        /*!< PORT2 HWSEL: HW13 Mask                  */\r
+#define PORT2_HWSEL_HW14_Pos                  28                                                      /*!< PORT2 HWSEL: HW14 Position              */\r
+#define PORT2_HWSEL_HW14_Msk                  (0x03UL << PORT2_HWSEL_HW14_Pos)                        /*!< PORT2 HWSEL: HW14 Mask                  */\r
+#define PORT2_HWSEL_HW15_Pos                  30                                                      /*!< PORT2 HWSEL: HW15 Position              */\r
+#define PORT2_HWSEL_HW15_Msk                  (0x03UL << PORT2_HWSEL_HW15_Pos)                        /*!< PORT2 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT3' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT3_OUT  --------------------------------- */\r
+#define PORT3_OUT_P0_Pos                      0                                                       /*!< PORT3 OUT: P0 Position                  */\r
+#define PORT3_OUT_P0_Msk                      (0x01UL << PORT3_OUT_P0_Pos)                            /*!< PORT3 OUT: P0 Mask                      */\r
+#define PORT3_OUT_P1_Pos                      1                                                       /*!< PORT3 OUT: P1 Position                  */\r
+#define PORT3_OUT_P1_Msk                      (0x01UL << PORT3_OUT_P1_Pos)                            /*!< PORT3 OUT: P1 Mask                      */\r
+#define PORT3_OUT_P2_Pos                      2                                                       /*!< PORT3 OUT: P2 Position                  */\r
+#define PORT3_OUT_P2_Msk                      (0x01UL << PORT3_OUT_P2_Pos)                            /*!< PORT3 OUT: P2 Mask                      */\r
+#define PORT3_OUT_P3_Pos                      3                                                       /*!< PORT3 OUT: P3 Position                  */\r
+#define PORT3_OUT_P3_Msk                      (0x01UL << PORT3_OUT_P3_Pos)                            /*!< PORT3 OUT: P3 Mask                      */\r
+#define PORT3_OUT_P4_Pos                      4                                                       /*!< PORT3 OUT: P4 Position                  */\r
+#define PORT3_OUT_P4_Msk                      (0x01UL << PORT3_OUT_P4_Pos)                            /*!< PORT3 OUT: P4 Mask                      */\r
+#define PORT3_OUT_P5_Pos                      5                                                       /*!< PORT3 OUT: P5 Position                  */\r
+#define PORT3_OUT_P5_Msk                      (0x01UL << PORT3_OUT_P5_Pos)                            /*!< PORT3 OUT: P5 Mask                      */\r
+#define PORT3_OUT_P6_Pos                      6                                                       /*!< PORT3 OUT: P6 Position                  */\r
+#define PORT3_OUT_P6_Msk                      (0x01UL << PORT3_OUT_P6_Pos)                            /*!< PORT3 OUT: P6 Mask                      */\r
+#define PORT3_OUT_P7_Pos                      7                                                       /*!< PORT3 OUT: P7 Position                  */\r
+#define PORT3_OUT_P7_Msk                      (0x01UL << PORT3_OUT_P7_Pos)                            /*!< PORT3 OUT: P7 Mask                      */\r
+#define PORT3_OUT_P8_Pos                      8                                                       /*!< PORT3 OUT: P8 Position                  */\r
+#define PORT3_OUT_P8_Msk                      (0x01UL << PORT3_OUT_P8_Pos)                            /*!< PORT3 OUT: P8 Mask                      */\r
+#define PORT3_OUT_P9_Pos                      9                                                       /*!< PORT3 OUT: P9 Position                  */\r
+#define PORT3_OUT_P9_Msk                      (0x01UL << PORT3_OUT_P9_Pos)                            /*!< PORT3 OUT: P9 Mask                      */\r
+#define PORT3_OUT_P10_Pos                     10                                                      /*!< PORT3 OUT: P10 Position                 */\r
+#define PORT3_OUT_P10_Msk                     (0x01UL << PORT3_OUT_P10_Pos)                           /*!< PORT3 OUT: P10 Mask                     */\r
+#define PORT3_OUT_P11_Pos                     11                                                      /*!< PORT3 OUT: P11 Position                 */\r
+#define PORT3_OUT_P11_Msk                     (0x01UL << PORT3_OUT_P11_Pos)                           /*!< PORT3 OUT: P11 Mask                     */\r
+#define PORT3_OUT_P12_Pos                     12                                                      /*!< PORT3 OUT: P12 Position                 */\r
+#define PORT3_OUT_P12_Msk                     (0x01UL << PORT3_OUT_P12_Pos)                           /*!< PORT3 OUT: P12 Mask                     */\r
+#define PORT3_OUT_P13_Pos                     13                                                      /*!< PORT3 OUT: P13 Position                 */\r
+#define PORT3_OUT_P13_Msk                     (0x01UL << PORT3_OUT_P13_Pos)                           /*!< PORT3 OUT: P13 Mask                     */\r
+#define PORT3_OUT_P14_Pos                     14                                                      /*!< PORT3 OUT: P14 Position                 */\r
+#define PORT3_OUT_P14_Msk                     (0x01UL << PORT3_OUT_P14_Pos)                           /*!< PORT3 OUT: P14 Mask                     */\r
+#define PORT3_OUT_P15_Pos                     15                                                      /*!< PORT3 OUT: P15 Position                 */\r
+#define PORT3_OUT_P15_Msk                     (0x01UL << PORT3_OUT_P15_Pos)                           /*!< PORT3 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT3_OMR  --------------------------------- */\r
+#define PORT3_OMR_PS0_Pos                     0                                                       /*!< PORT3 OMR: PS0 Position                 */\r
+#define PORT3_OMR_PS0_Msk                     (0x01UL << PORT3_OMR_PS0_Pos)                           /*!< PORT3 OMR: PS0 Mask                     */\r
+#define PORT3_OMR_PS1_Pos                     1                                                       /*!< PORT3 OMR: PS1 Position                 */\r
+#define PORT3_OMR_PS1_Msk                     (0x01UL << PORT3_OMR_PS1_Pos)                           /*!< PORT3 OMR: PS1 Mask                     */\r
+#define PORT3_OMR_PS2_Pos                     2                                                       /*!< PORT3 OMR: PS2 Position                 */\r
+#define PORT3_OMR_PS2_Msk                     (0x01UL << PORT3_OMR_PS2_Pos)                           /*!< PORT3 OMR: PS2 Mask                     */\r
+#define PORT3_OMR_PS3_Pos                     3                                                       /*!< PORT3 OMR: PS3 Position                 */\r
+#define PORT3_OMR_PS3_Msk                     (0x01UL << PORT3_OMR_PS3_Pos)                           /*!< PORT3 OMR: PS3 Mask                     */\r
+#define PORT3_OMR_PS4_Pos                     4                                                       /*!< PORT3 OMR: PS4 Position                 */\r
+#define PORT3_OMR_PS4_Msk                     (0x01UL << PORT3_OMR_PS4_Pos)                           /*!< PORT3 OMR: PS4 Mask                     */\r
+#define PORT3_OMR_PS5_Pos                     5                                                       /*!< PORT3 OMR: PS5 Position                 */\r
+#define PORT3_OMR_PS5_Msk                     (0x01UL << PORT3_OMR_PS5_Pos)                           /*!< PORT3 OMR: PS5 Mask                     */\r
+#define PORT3_OMR_PS6_Pos                     6                                                       /*!< PORT3 OMR: PS6 Position                 */\r
+#define PORT3_OMR_PS6_Msk                     (0x01UL << PORT3_OMR_PS6_Pos)                           /*!< PORT3 OMR: PS6 Mask                     */\r
+#define PORT3_OMR_PS7_Pos                     7                                                       /*!< PORT3 OMR: PS7 Position                 */\r
+#define PORT3_OMR_PS7_Msk                     (0x01UL << PORT3_OMR_PS7_Pos)                           /*!< PORT3 OMR: PS7 Mask                     */\r
+#define PORT3_OMR_PS8_Pos                     8                                                       /*!< PORT3 OMR: PS8 Position                 */\r
+#define PORT3_OMR_PS8_Msk                     (0x01UL << PORT3_OMR_PS8_Pos)                           /*!< PORT3 OMR: PS8 Mask                     */\r
+#define PORT3_OMR_PS9_Pos                     9                                                       /*!< PORT3 OMR: PS9 Position                 */\r
+#define PORT3_OMR_PS9_Msk                     (0x01UL << PORT3_OMR_PS9_Pos)                           /*!< PORT3 OMR: PS9 Mask                     */\r
+#define PORT3_OMR_PS10_Pos                    10                                                      /*!< PORT3 OMR: PS10 Position                */\r
+#define PORT3_OMR_PS10_Msk                    (0x01UL << PORT3_OMR_PS10_Pos)                          /*!< PORT3 OMR: PS10 Mask                    */\r
+#define PORT3_OMR_PS11_Pos                    11                                                      /*!< PORT3 OMR: PS11 Position                */\r
+#define PORT3_OMR_PS11_Msk                    (0x01UL << PORT3_OMR_PS11_Pos)                          /*!< PORT3 OMR: PS11 Mask                    */\r
+#define PORT3_OMR_PS12_Pos                    12                                                      /*!< PORT3 OMR: PS12 Position                */\r
+#define PORT3_OMR_PS12_Msk                    (0x01UL << PORT3_OMR_PS12_Pos)                          /*!< PORT3 OMR: PS12 Mask                    */\r
+#define PORT3_OMR_PS13_Pos                    13                                                      /*!< PORT3 OMR: PS13 Position                */\r
+#define PORT3_OMR_PS13_Msk                    (0x01UL << PORT3_OMR_PS13_Pos)                          /*!< PORT3 OMR: PS13 Mask                    */\r
+#define PORT3_OMR_PS14_Pos                    14                                                      /*!< PORT3 OMR: PS14 Position                */\r
+#define PORT3_OMR_PS14_Msk                    (0x01UL << PORT3_OMR_PS14_Pos)                          /*!< PORT3 OMR: PS14 Mask                    */\r
+#define PORT3_OMR_PS15_Pos                    15                                                      /*!< PORT3 OMR: PS15 Position                */\r
+#define PORT3_OMR_PS15_Msk                    (0x01UL << PORT3_OMR_PS15_Pos)                          /*!< PORT3 OMR: PS15 Mask                    */\r
+#define PORT3_OMR_PR0_Pos                     16                                                      /*!< PORT3 OMR: PR0 Position                 */\r
+#define PORT3_OMR_PR0_Msk                     (0x01UL << PORT3_OMR_PR0_Pos)                           /*!< PORT3 OMR: PR0 Mask                     */\r
+#define PORT3_OMR_PR1_Pos                     17                                                      /*!< PORT3 OMR: PR1 Position                 */\r
+#define PORT3_OMR_PR1_Msk                     (0x01UL << PORT3_OMR_PR1_Pos)                           /*!< PORT3 OMR: PR1 Mask                     */\r
+#define PORT3_OMR_PR2_Pos                     18                                                      /*!< PORT3 OMR: PR2 Position                 */\r
+#define PORT3_OMR_PR2_Msk                     (0x01UL << PORT3_OMR_PR2_Pos)                           /*!< PORT3 OMR: PR2 Mask                     */\r
+#define PORT3_OMR_PR3_Pos                     19                                                      /*!< PORT3 OMR: PR3 Position                 */\r
+#define PORT3_OMR_PR3_Msk                     (0x01UL << PORT3_OMR_PR3_Pos)                           /*!< PORT3 OMR: PR3 Mask                     */\r
+#define PORT3_OMR_PR4_Pos                     20                                                      /*!< PORT3 OMR: PR4 Position                 */\r
+#define PORT3_OMR_PR4_Msk                     (0x01UL << PORT3_OMR_PR4_Pos)                           /*!< PORT3 OMR: PR4 Mask                     */\r
+#define PORT3_OMR_PR5_Pos                     21                                                      /*!< PORT3 OMR: PR5 Position                 */\r
+#define PORT3_OMR_PR5_Msk                     (0x01UL << PORT3_OMR_PR5_Pos)                           /*!< PORT3 OMR: PR5 Mask                     */\r
+#define PORT3_OMR_PR6_Pos                     22                                                      /*!< PORT3 OMR: PR6 Position                 */\r
+#define PORT3_OMR_PR6_Msk                     (0x01UL << PORT3_OMR_PR6_Pos)                           /*!< PORT3 OMR: PR6 Mask                     */\r
+#define PORT3_OMR_PR7_Pos                     23                                                      /*!< PORT3 OMR: PR7 Position                 */\r
+#define PORT3_OMR_PR7_Msk                     (0x01UL << PORT3_OMR_PR7_Pos)                           /*!< PORT3 OMR: PR7 Mask                     */\r
+#define PORT3_OMR_PR8_Pos                     24                                                      /*!< PORT3 OMR: PR8 Position                 */\r
+#define PORT3_OMR_PR8_Msk                     (0x01UL << PORT3_OMR_PR8_Pos)                           /*!< PORT3 OMR: PR8 Mask                     */\r
+#define PORT3_OMR_PR9_Pos                     25                                                      /*!< PORT3 OMR: PR9 Position                 */\r
+#define PORT3_OMR_PR9_Msk                     (0x01UL << PORT3_OMR_PR9_Pos)                           /*!< PORT3 OMR: PR9 Mask                     */\r
+#define PORT3_OMR_PR10_Pos                    26                                                      /*!< PORT3 OMR: PR10 Position                */\r
+#define PORT3_OMR_PR10_Msk                    (0x01UL << PORT3_OMR_PR10_Pos)                          /*!< PORT3 OMR: PR10 Mask                    */\r
+#define PORT3_OMR_PR11_Pos                    27                                                      /*!< PORT3 OMR: PR11 Position                */\r
+#define PORT3_OMR_PR11_Msk                    (0x01UL << PORT3_OMR_PR11_Pos)                          /*!< PORT3 OMR: PR11 Mask                    */\r
+#define PORT3_OMR_PR12_Pos                    28                                                      /*!< PORT3 OMR: PR12 Position                */\r
+#define PORT3_OMR_PR12_Msk                    (0x01UL << PORT3_OMR_PR12_Pos)                          /*!< PORT3 OMR: PR12 Mask                    */\r
+#define PORT3_OMR_PR13_Pos                    29                                                      /*!< PORT3 OMR: PR13 Position                */\r
+#define PORT3_OMR_PR13_Msk                    (0x01UL << PORT3_OMR_PR13_Pos)                          /*!< PORT3 OMR: PR13 Mask                    */\r
+#define PORT3_OMR_PR14_Pos                    30                                                      /*!< PORT3 OMR: PR14 Position                */\r
+#define PORT3_OMR_PR14_Msk                    (0x01UL << PORT3_OMR_PR14_Pos)                          /*!< PORT3 OMR: PR14 Mask                    */\r
+#define PORT3_OMR_PR15_Pos                    31                                                      /*!< PORT3 OMR: PR15 Position                */\r
+#define PORT3_OMR_PR15_Msk                    (0x01UL << PORT3_OMR_PR15_Pos)                          /*!< PORT3 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT3_IOCR0  -------------------------------- */\r
+#define PORT3_IOCR0_PC0_Pos                   3                                                       /*!< PORT3 IOCR0: PC0 Position               */\r
+#define PORT3_IOCR0_PC0_Msk                   (0x1fUL << PORT3_IOCR0_PC0_Pos)                         /*!< PORT3 IOCR0: PC0 Mask                   */\r
+#define PORT3_IOCR0_PC1_Pos                   11                                                      /*!< PORT3 IOCR0: PC1 Position               */\r
+#define PORT3_IOCR0_PC1_Msk                   (0x1fUL << PORT3_IOCR0_PC1_Pos)                         /*!< PORT3 IOCR0: PC1 Mask                   */\r
+#define PORT3_IOCR0_PC2_Pos                   19                                                      /*!< PORT3 IOCR0: PC2 Position               */\r
+#define PORT3_IOCR0_PC2_Msk                   (0x1fUL << PORT3_IOCR0_PC2_Pos)                         /*!< PORT3 IOCR0: PC2 Mask                   */\r
+#define PORT3_IOCR0_PC3_Pos                   27                                                      /*!< PORT3 IOCR0: PC3 Position               */\r
+#define PORT3_IOCR0_PC3_Msk                   (0x1fUL << PORT3_IOCR0_PC3_Pos)                         /*!< PORT3 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT3_IOCR4  -------------------------------- */\r
+#define PORT3_IOCR4_PC4_Pos                   3                                                       /*!< PORT3 IOCR4: PC4 Position               */\r
+#define PORT3_IOCR4_PC4_Msk                   (0x1fUL << PORT3_IOCR4_PC4_Pos)                         /*!< PORT3 IOCR4: PC4 Mask                   */\r
+#define PORT3_IOCR4_PC5_Pos                   11                                                      /*!< PORT3 IOCR4: PC5 Position               */\r
+#define PORT3_IOCR4_PC5_Msk                   (0x1fUL << PORT3_IOCR4_PC5_Pos)                         /*!< PORT3 IOCR4: PC5 Mask                   */\r
+#define PORT3_IOCR4_PC6_Pos                   19                                                      /*!< PORT3 IOCR4: PC6 Position               */\r
+#define PORT3_IOCR4_PC6_Msk                   (0x1fUL << PORT3_IOCR4_PC6_Pos)                         /*!< PORT3 IOCR4: PC6 Mask                   */\r
+#define PORT3_IOCR4_PC7_Pos                   27                                                      /*!< PORT3 IOCR4: PC7 Position               */\r
+#define PORT3_IOCR4_PC7_Msk                   (0x1fUL << PORT3_IOCR4_PC7_Pos)                         /*!< PORT3 IOCR4: PC7 Mask                   */\r
+\r
+/* ---------------------------------  PORT3_IOCR8  -------------------------------- */\r
+#define PORT3_IOCR8_PC8_Pos                   3                                                       /*!< PORT3 IOCR8: PC8 Position               */\r
+#define PORT3_IOCR8_PC8_Msk                   (0x1fUL << PORT3_IOCR8_PC8_Pos)                         /*!< PORT3 IOCR8: PC8 Mask                   */\r
+#define PORT3_IOCR8_PC9_Pos                   11                                                      /*!< PORT3 IOCR8: PC9 Position               */\r
+#define PORT3_IOCR8_PC9_Msk                   (0x1fUL << PORT3_IOCR8_PC9_Pos)                         /*!< PORT3 IOCR8: PC9 Mask                   */\r
+#define PORT3_IOCR8_PC10_Pos                  19                                                      /*!< PORT3 IOCR8: PC10 Position              */\r
+#define PORT3_IOCR8_PC10_Msk                  (0x1fUL << PORT3_IOCR8_PC10_Pos)                        /*!< PORT3 IOCR8: PC10 Mask                  */\r
+#define PORT3_IOCR8_PC11_Pos                  27                                                      /*!< PORT3 IOCR8: PC11 Position              */\r
+#define PORT3_IOCR8_PC11_Msk                  (0x1fUL << PORT3_IOCR8_PC11_Pos)                        /*!< PORT3 IOCR8: PC11 Mask                  */\r
+\r
+/* --------------------------------  PORT3_IOCR12  -------------------------------- */\r
+#define PORT3_IOCR12_PC12_Pos                 3                                                       /*!< PORT3 IOCR12: PC12 Position             */\r
+#define PORT3_IOCR12_PC12_Msk                 (0x1fUL << PORT3_IOCR12_PC12_Pos)                       /*!< PORT3 IOCR12: PC12 Mask                 */\r
+#define PORT3_IOCR12_PC13_Pos                 11                                                      /*!< PORT3 IOCR12: PC13 Position             */\r
+#define PORT3_IOCR12_PC13_Msk                 (0x1fUL << PORT3_IOCR12_PC13_Pos)                       /*!< PORT3 IOCR12: PC13 Mask                 */\r
+#define PORT3_IOCR12_PC14_Pos                 19                                                      /*!< PORT3 IOCR12: PC14 Position             */\r
+#define PORT3_IOCR12_PC14_Msk                 (0x1fUL << PORT3_IOCR12_PC14_Pos)                       /*!< PORT3 IOCR12: PC14 Mask                 */\r
+#define PORT3_IOCR12_PC15_Pos                 27                                                      /*!< PORT3 IOCR12: PC15 Position             */\r
+#define PORT3_IOCR12_PC15_Msk                 (0x1fUL << PORT3_IOCR12_PC15_Pos)                       /*!< PORT3 IOCR12: PC15 Mask                 */\r
+\r
+/* ----------------------------------  PORT3_IN  ---------------------------------- */\r
+#define PORT3_IN_P0_Pos                       0                                                       /*!< PORT3 IN: P0 Position                   */\r
+#define PORT3_IN_P0_Msk                       (0x01UL << PORT3_IN_P0_Pos)                             /*!< PORT3 IN: P0 Mask                       */\r
+#define PORT3_IN_P1_Pos                       1                                                       /*!< PORT3 IN: P1 Position                   */\r
+#define PORT3_IN_P1_Msk                       (0x01UL << PORT3_IN_P1_Pos)                             /*!< PORT3 IN: P1 Mask                       */\r
+#define PORT3_IN_P2_Pos                       2                                                       /*!< PORT3 IN: P2 Position                   */\r
+#define PORT3_IN_P2_Msk                       (0x01UL << PORT3_IN_P2_Pos)                             /*!< PORT3 IN: P2 Mask                       */\r
+#define PORT3_IN_P3_Pos                       3                                                       /*!< PORT3 IN: P3 Position                   */\r
+#define PORT3_IN_P3_Msk                       (0x01UL << PORT3_IN_P3_Pos)                             /*!< PORT3 IN: P3 Mask                       */\r
+#define PORT3_IN_P4_Pos                       4                                                       /*!< PORT3 IN: P4 Position                   */\r
+#define PORT3_IN_P4_Msk                       (0x01UL << PORT3_IN_P4_Pos)                             /*!< PORT3 IN: P4 Mask                       */\r
+#define PORT3_IN_P5_Pos                       5                                                       /*!< PORT3 IN: P5 Position                   */\r
+#define PORT3_IN_P5_Msk                       (0x01UL << PORT3_IN_P5_Pos)                             /*!< PORT3 IN: P5 Mask                       */\r
+#define PORT3_IN_P6_Pos                       6                                                       /*!< PORT3 IN: P6 Position                   */\r
+#define PORT3_IN_P6_Msk                       (0x01UL << PORT3_IN_P6_Pos)                             /*!< PORT3 IN: P6 Mask                       */\r
+#define PORT3_IN_P7_Pos                       7                                                       /*!< PORT3 IN: P7 Position                   */\r
+#define PORT3_IN_P7_Msk                       (0x01UL << PORT3_IN_P7_Pos)                             /*!< PORT3 IN: P7 Mask                       */\r
+#define PORT3_IN_P8_Pos                       8                                                       /*!< PORT3 IN: P8 Position                   */\r
+#define PORT3_IN_P8_Msk                       (0x01UL << PORT3_IN_P8_Pos)                             /*!< PORT3 IN: P8 Mask                       */\r
+#define PORT3_IN_P9_Pos                       9                                                       /*!< PORT3 IN: P9 Position                   */\r
+#define PORT3_IN_P9_Msk                       (0x01UL << PORT3_IN_P9_Pos)                             /*!< PORT3 IN: P9 Mask                       */\r
+#define PORT3_IN_P10_Pos                      10                                                      /*!< PORT3 IN: P10 Position                  */\r
+#define PORT3_IN_P10_Msk                      (0x01UL << PORT3_IN_P10_Pos)                            /*!< PORT3 IN: P10 Mask                      */\r
+#define PORT3_IN_P11_Pos                      11                                                      /*!< PORT3 IN: P11 Position                  */\r
+#define PORT3_IN_P11_Msk                      (0x01UL << PORT3_IN_P11_Pos)                            /*!< PORT3 IN: P11 Mask                      */\r
+#define PORT3_IN_P12_Pos                      12                                                      /*!< PORT3 IN: P12 Position                  */\r
+#define PORT3_IN_P12_Msk                      (0x01UL << PORT3_IN_P12_Pos)                            /*!< PORT3 IN: P12 Mask                      */\r
+#define PORT3_IN_P13_Pos                      13                                                      /*!< PORT3 IN: P13 Position                  */\r
+#define PORT3_IN_P13_Msk                      (0x01UL << PORT3_IN_P13_Pos)                            /*!< PORT3 IN: P13 Mask                      */\r
+#define PORT3_IN_P14_Pos                      14                                                      /*!< PORT3 IN: P14 Position                  */\r
+#define PORT3_IN_P14_Msk                      (0x01UL << PORT3_IN_P14_Pos)                            /*!< PORT3 IN: P14 Mask                      */\r
+#define PORT3_IN_P15_Pos                      15                                                      /*!< PORT3 IN: P15 Position                  */\r
+#define PORT3_IN_P15_Msk                      (0x01UL << PORT3_IN_P15_Pos)                            /*!< PORT3 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT3_PDR0  --------------------------------- */\r
+#define PORT3_PDR0_PD0_Pos                    0                                                       /*!< PORT3 PDR0: PD0 Position                */\r
+#define PORT3_PDR0_PD0_Msk                    (0x07UL << PORT3_PDR0_PD0_Pos)                          /*!< PORT3 PDR0: PD0 Mask                    */\r
+#define PORT3_PDR0_PD1_Pos                    4                                                       /*!< PORT3 PDR0: PD1 Position                */\r
+#define PORT3_PDR0_PD1_Msk                    (0x07UL << PORT3_PDR0_PD1_Pos)                          /*!< PORT3 PDR0: PD1 Mask                    */\r
+#define PORT3_PDR0_PD2_Pos                    8                                                       /*!< PORT3 PDR0: PD2 Position                */\r
+#define PORT3_PDR0_PD2_Msk                    (0x07UL << PORT3_PDR0_PD2_Pos)                          /*!< PORT3 PDR0: PD2 Mask                    */\r
+#define PORT3_PDR0_PD3_Pos                    12                                                      /*!< PORT3 PDR0: PD3 Position                */\r
+#define PORT3_PDR0_PD3_Msk                    (0x07UL << PORT3_PDR0_PD3_Pos)                          /*!< PORT3 PDR0: PD3 Mask                    */\r
+#define PORT3_PDR0_PD4_Pos                    16                                                      /*!< PORT3 PDR0: PD4 Position                */\r
+#define PORT3_PDR0_PD4_Msk                    (0x07UL << PORT3_PDR0_PD4_Pos)                          /*!< PORT3 PDR0: PD4 Mask                    */\r
+#define PORT3_PDR0_PD5_Pos                    20                                                      /*!< PORT3 PDR0: PD5 Position                */\r
+#define PORT3_PDR0_PD5_Msk                    (0x07UL << PORT3_PDR0_PD5_Pos)                          /*!< PORT3 PDR0: PD5 Mask                    */\r
+#define PORT3_PDR0_PD6_Pos                    24                                                      /*!< PORT3 PDR0: PD6 Position                */\r
+#define PORT3_PDR0_PD6_Msk                    (0x07UL << PORT3_PDR0_PD6_Pos)                          /*!< PORT3 PDR0: PD6 Mask                    */\r
+#define PORT3_PDR0_PD7_Pos                    28                                                      /*!< PORT3 PDR0: PD7 Position                */\r
+#define PORT3_PDR0_PD7_Msk                    (0x07UL << PORT3_PDR0_PD7_Pos)                          /*!< PORT3 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT3_PDR1  --------------------------------- */\r
+#define PORT3_PDR1_PD8_Pos                    0                                                       /*!< PORT3 PDR1: PD8 Position                */\r
+#define PORT3_PDR1_PD8_Msk                    (0x07UL << PORT3_PDR1_PD8_Pos)                          /*!< PORT3 PDR1: PD8 Mask                    */\r
+#define PORT3_PDR1_PD9_Pos                    4                                                       /*!< PORT3 PDR1: PD9 Position                */\r
+#define PORT3_PDR1_PD9_Msk                    (0x07UL << PORT3_PDR1_PD9_Pos)                          /*!< PORT3 PDR1: PD9 Mask                    */\r
+#define PORT3_PDR1_PD10_Pos                   8                                                       /*!< PORT3 PDR1: PD10 Position               */\r
+#define PORT3_PDR1_PD10_Msk                   (0x07UL << PORT3_PDR1_PD10_Pos)                         /*!< PORT3 PDR1: PD10 Mask                   */\r
+#define PORT3_PDR1_PD11_Pos                   12                                                      /*!< PORT3 PDR1: PD11 Position               */\r
+#define PORT3_PDR1_PD11_Msk                   (0x07UL << PORT3_PDR1_PD11_Pos)                         /*!< PORT3 PDR1: PD11 Mask                   */\r
+#define PORT3_PDR1_PD12_Pos                   16                                                      /*!< PORT3 PDR1: PD12 Position               */\r
+#define PORT3_PDR1_PD12_Msk                   (0x07UL << PORT3_PDR1_PD12_Pos)                         /*!< PORT3 PDR1: PD12 Mask                   */\r
+#define PORT3_PDR1_PD13_Pos                   20                                                      /*!< PORT3 PDR1: PD13 Position               */\r
+#define PORT3_PDR1_PD13_Msk                   (0x07UL << PORT3_PDR1_PD13_Pos)                         /*!< PORT3 PDR1: PD13 Mask                   */\r
+#define PORT3_PDR1_PD14_Pos                   24                                                      /*!< PORT3 PDR1: PD14 Position               */\r
+#define PORT3_PDR1_PD14_Msk                   (0x07UL << PORT3_PDR1_PD14_Pos)                         /*!< PORT3 PDR1: PD14 Mask                   */\r
+#define PORT3_PDR1_PD15_Pos                   28                                                      /*!< PORT3 PDR1: PD15 Position               */\r
+#define PORT3_PDR1_PD15_Msk                   (0x07UL << PORT3_PDR1_PD15_Pos)                         /*!< PORT3 PDR1: PD15 Mask                   */\r
+\r
+/* ---------------------------------  PORT3_PDISC  -------------------------------- */\r
+#define PORT3_PDISC_PDIS0_Pos                 0                                                       /*!< PORT3 PDISC: PDIS0 Position             */\r
+#define PORT3_PDISC_PDIS0_Msk                 (0x01UL << PORT3_PDISC_PDIS0_Pos)                       /*!< PORT3 PDISC: PDIS0 Mask                 */\r
+#define PORT3_PDISC_PDIS1_Pos                 1                                                       /*!< PORT3 PDISC: PDIS1 Position             */\r
+#define PORT3_PDISC_PDIS1_Msk                 (0x01UL << PORT3_PDISC_PDIS1_Pos)                       /*!< PORT3 PDISC: PDIS1 Mask                 */\r
+#define PORT3_PDISC_PDIS2_Pos                 2                                                       /*!< PORT3 PDISC: PDIS2 Position             */\r
+#define PORT3_PDISC_PDIS2_Msk                 (0x01UL << PORT3_PDISC_PDIS2_Pos)                       /*!< PORT3 PDISC: PDIS2 Mask                 */\r
+#define PORT3_PDISC_PDIS3_Pos                 3                                                       /*!< PORT3 PDISC: PDIS3 Position             */\r
+#define PORT3_PDISC_PDIS3_Msk                 (0x01UL << PORT3_PDISC_PDIS3_Pos)                       /*!< PORT3 PDISC: PDIS3 Mask                 */\r
+#define PORT3_PDISC_PDIS4_Pos                 4                                                       /*!< PORT3 PDISC: PDIS4 Position             */\r
+#define PORT3_PDISC_PDIS4_Msk                 (0x01UL << PORT3_PDISC_PDIS4_Pos)                       /*!< PORT3 PDISC: PDIS4 Mask                 */\r
+#define PORT3_PDISC_PDIS5_Pos                 5                                                       /*!< PORT3 PDISC: PDIS5 Position             */\r
+#define PORT3_PDISC_PDIS5_Msk                 (0x01UL << PORT3_PDISC_PDIS5_Pos)                       /*!< PORT3 PDISC: PDIS5 Mask                 */\r
+#define PORT3_PDISC_PDIS6_Pos                 6                                                       /*!< PORT3 PDISC: PDIS6 Position             */\r
+#define PORT3_PDISC_PDIS6_Msk                 (0x01UL << PORT3_PDISC_PDIS6_Pos)                       /*!< PORT3 PDISC: PDIS6 Mask                 */\r
+#define PORT3_PDISC_PDIS7_Pos                 7                                                       /*!< PORT3 PDISC: PDIS7 Position             */\r
+#define PORT3_PDISC_PDIS7_Msk                 (0x01UL << PORT3_PDISC_PDIS7_Pos)                       /*!< PORT3 PDISC: PDIS7 Mask                 */\r
+#define PORT3_PDISC_PDIS8_Pos                 8                                                       /*!< PORT3 PDISC: PDIS8 Position             */\r
+#define PORT3_PDISC_PDIS8_Msk                 (0x01UL << PORT3_PDISC_PDIS8_Pos)                       /*!< PORT3 PDISC: PDIS8 Mask                 */\r
+#define PORT3_PDISC_PDIS9_Pos                 9                                                       /*!< PORT3 PDISC: PDIS9 Position             */\r
+#define PORT3_PDISC_PDIS9_Msk                 (0x01UL << PORT3_PDISC_PDIS9_Pos)                       /*!< PORT3 PDISC: PDIS9 Mask                 */\r
+#define PORT3_PDISC_PDIS10_Pos                10                                                      /*!< PORT3 PDISC: PDIS10 Position            */\r
+#define PORT3_PDISC_PDIS10_Msk                (0x01UL << PORT3_PDISC_PDIS10_Pos)                      /*!< PORT3 PDISC: PDIS10 Mask                */\r
+#define PORT3_PDISC_PDIS11_Pos                11                                                      /*!< PORT3 PDISC: PDIS11 Position            */\r
+#define PORT3_PDISC_PDIS11_Msk                (0x01UL << PORT3_PDISC_PDIS11_Pos)                      /*!< PORT3 PDISC: PDIS11 Mask                */\r
+#define PORT3_PDISC_PDIS12_Pos                12                                                      /*!< PORT3 PDISC: PDIS12 Position            */\r
+#define PORT3_PDISC_PDIS12_Msk                (0x01UL << PORT3_PDISC_PDIS12_Pos)                      /*!< PORT3 PDISC: PDIS12 Mask                */\r
+#define PORT3_PDISC_PDIS13_Pos                13                                                      /*!< PORT3 PDISC: PDIS13 Position            */\r
+#define PORT3_PDISC_PDIS13_Msk                (0x01UL << PORT3_PDISC_PDIS13_Pos)                      /*!< PORT3 PDISC: PDIS13 Mask                */\r
+#define PORT3_PDISC_PDIS14_Pos                14                                                      /*!< PORT3 PDISC: PDIS14 Position            */\r
+#define PORT3_PDISC_PDIS14_Msk                (0x01UL << PORT3_PDISC_PDIS14_Pos)                      /*!< PORT3 PDISC: PDIS14 Mask                */\r
+#define PORT3_PDISC_PDIS15_Pos                15                                                      /*!< PORT3 PDISC: PDIS15 Position            */\r
+#define PORT3_PDISC_PDIS15_Msk                (0x01UL << PORT3_PDISC_PDIS15_Pos)                      /*!< PORT3 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT3_PPS  --------------------------------- */\r
+#define PORT3_PPS_PPS0_Pos                    0                                                       /*!< PORT3 PPS: PPS0 Position                */\r
+#define PORT3_PPS_PPS0_Msk                    (0x01UL << PORT3_PPS_PPS0_Pos)                          /*!< PORT3 PPS: PPS0 Mask                    */\r
+#define PORT3_PPS_PPS1_Pos                    1                                                       /*!< PORT3 PPS: PPS1 Position                */\r
+#define PORT3_PPS_PPS1_Msk                    (0x01UL << PORT3_PPS_PPS1_Pos)                          /*!< PORT3 PPS: PPS1 Mask                    */\r
+#define PORT3_PPS_PPS2_Pos                    2                                                       /*!< PORT3 PPS: PPS2 Position                */\r
+#define PORT3_PPS_PPS2_Msk                    (0x01UL << PORT3_PPS_PPS2_Pos)                          /*!< PORT3 PPS: PPS2 Mask                    */\r
+#define PORT3_PPS_PPS3_Pos                    3                                                       /*!< PORT3 PPS: PPS3 Position                */\r
+#define PORT3_PPS_PPS3_Msk                    (0x01UL << PORT3_PPS_PPS3_Pos)                          /*!< PORT3 PPS: PPS3 Mask                    */\r
+#define PORT3_PPS_PPS4_Pos                    4                                                       /*!< PORT3 PPS: PPS4 Position                */\r
+#define PORT3_PPS_PPS4_Msk                    (0x01UL << PORT3_PPS_PPS4_Pos)                          /*!< PORT3 PPS: PPS4 Mask                    */\r
+#define PORT3_PPS_PPS5_Pos                    5                                                       /*!< PORT3 PPS: PPS5 Position                */\r
+#define PORT3_PPS_PPS5_Msk                    (0x01UL << PORT3_PPS_PPS5_Pos)                          /*!< PORT3 PPS: PPS5 Mask                    */\r
+#define PORT3_PPS_PPS6_Pos                    6                                                       /*!< PORT3 PPS: PPS6 Position                */\r
+#define PORT3_PPS_PPS6_Msk                    (0x01UL << PORT3_PPS_PPS6_Pos)                          /*!< PORT3 PPS: PPS6 Mask                    */\r
+#define PORT3_PPS_PPS7_Pos                    7                                                       /*!< PORT3 PPS: PPS7 Position                */\r
+#define PORT3_PPS_PPS7_Msk                    (0x01UL << PORT3_PPS_PPS7_Pos)                          /*!< PORT3 PPS: PPS7 Mask                    */\r
+#define PORT3_PPS_PPS8_Pos                    8                                                       /*!< PORT3 PPS: PPS8 Position                */\r
+#define PORT3_PPS_PPS8_Msk                    (0x01UL << PORT3_PPS_PPS8_Pos)                          /*!< PORT3 PPS: PPS8 Mask                    */\r
+#define PORT3_PPS_PPS9_Pos                    9                                                       /*!< PORT3 PPS: PPS9 Position                */\r
+#define PORT3_PPS_PPS9_Msk                    (0x01UL << PORT3_PPS_PPS9_Pos)                          /*!< PORT3 PPS: PPS9 Mask                    */\r
+#define PORT3_PPS_PPS10_Pos                   10                                                      /*!< PORT3 PPS: PPS10 Position               */\r
+#define PORT3_PPS_PPS10_Msk                   (0x01UL << PORT3_PPS_PPS10_Pos)                         /*!< PORT3 PPS: PPS10 Mask                   */\r
+#define PORT3_PPS_PPS11_Pos                   11                                                      /*!< PORT3 PPS: PPS11 Position               */\r
+#define PORT3_PPS_PPS11_Msk                   (0x01UL << PORT3_PPS_PPS11_Pos)                         /*!< PORT3 PPS: PPS11 Mask                   */\r
+#define PORT3_PPS_PPS12_Pos                   12                                                      /*!< PORT3 PPS: PPS12 Position               */\r
+#define PORT3_PPS_PPS12_Msk                   (0x01UL << PORT3_PPS_PPS12_Pos)                         /*!< PORT3 PPS: PPS12 Mask                   */\r
+#define PORT3_PPS_PPS13_Pos                   13                                                      /*!< PORT3 PPS: PPS13 Position               */\r
+#define PORT3_PPS_PPS13_Msk                   (0x01UL << PORT3_PPS_PPS13_Pos)                         /*!< PORT3 PPS: PPS13 Mask                   */\r
+#define PORT3_PPS_PPS14_Pos                   14                                                      /*!< PORT3 PPS: PPS14 Position               */\r
+#define PORT3_PPS_PPS14_Msk                   (0x01UL << PORT3_PPS_PPS14_Pos)                         /*!< PORT3 PPS: PPS14 Mask                   */\r
+#define PORT3_PPS_PPS15_Pos                   15                                                      /*!< PORT3 PPS: PPS15 Position               */\r
+#define PORT3_PPS_PPS15_Msk                   (0x01UL << PORT3_PPS_PPS15_Pos)                         /*!< PORT3 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT3_HWSEL  -------------------------------- */\r
+#define PORT3_HWSEL_HW0_Pos                   0                                                       /*!< PORT3 HWSEL: HW0 Position               */\r
+#define PORT3_HWSEL_HW0_Msk                   (0x03UL << PORT3_HWSEL_HW0_Pos)                         /*!< PORT3 HWSEL: HW0 Mask                   */\r
+#define PORT3_HWSEL_HW1_Pos                   2                                                       /*!< PORT3 HWSEL: HW1 Position               */\r
+#define PORT3_HWSEL_HW1_Msk                   (0x03UL << PORT3_HWSEL_HW1_Pos)                         /*!< PORT3 HWSEL: HW1 Mask                   */\r
+#define PORT3_HWSEL_HW2_Pos                   4                                                       /*!< PORT3 HWSEL: HW2 Position               */\r
+#define PORT3_HWSEL_HW2_Msk                   (0x03UL << PORT3_HWSEL_HW2_Pos)                         /*!< PORT3 HWSEL: HW2 Mask                   */\r
+#define PORT3_HWSEL_HW3_Pos                   6                                                       /*!< PORT3 HWSEL: HW3 Position               */\r
+#define PORT3_HWSEL_HW3_Msk                   (0x03UL << PORT3_HWSEL_HW3_Pos)                         /*!< PORT3 HWSEL: HW3 Mask                   */\r
+#define PORT3_HWSEL_HW4_Pos                   8                                                       /*!< PORT3 HWSEL: HW4 Position               */\r
+#define PORT3_HWSEL_HW4_Msk                   (0x03UL << PORT3_HWSEL_HW4_Pos)                         /*!< PORT3 HWSEL: HW4 Mask                   */\r
+#define PORT3_HWSEL_HW5_Pos                   10                                                      /*!< PORT3 HWSEL: HW5 Position               */\r
+#define PORT3_HWSEL_HW5_Msk                   (0x03UL << PORT3_HWSEL_HW5_Pos)                         /*!< PORT3 HWSEL: HW5 Mask                   */\r
+#define PORT3_HWSEL_HW6_Pos                   12                                                      /*!< PORT3 HWSEL: HW6 Position               */\r
+#define PORT3_HWSEL_HW6_Msk                   (0x03UL << PORT3_HWSEL_HW6_Pos)                         /*!< PORT3 HWSEL: HW6 Mask                   */\r
+#define PORT3_HWSEL_HW7_Pos                   14                                                      /*!< PORT3 HWSEL: HW7 Position               */\r
+#define PORT3_HWSEL_HW7_Msk                   (0x03UL << PORT3_HWSEL_HW7_Pos)                         /*!< PORT3 HWSEL: HW7 Mask                   */\r
+#define PORT3_HWSEL_HW8_Pos                   16                                                      /*!< PORT3 HWSEL: HW8 Position               */\r
+#define PORT3_HWSEL_HW8_Msk                   (0x03UL << PORT3_HWSEL_HW8_Pos)                         /*!< PORT3 HWSEL: HW8 Mask                   */\r
+#define PORT3_HWSEL_HW9_Pos                   18                                                      /*!< PORT3 HWSEL: HW9 Position               */\r
+#define PORT3_HWSEL_HW9_Msk                   (0x03UL << PORT3_HWSEL_HW9_Pos)                         /*!< PORT3 HWSEL: HW9 Mask                   */\r
+#define PORT3_HWSEL_HW10_Pos                  20                                                      /*!< PORT3 HWSEL: HW10 Position              */\r
+#define PORT3_HWSEL_HW10_Msk                  (0x03UL << PORT3_HWSEL_HW10_Pos)                        /*!< PORT3 HWSEL: HW10 Mask                  */\r
+#define PORT3_HWSEL_HW11_Pos                  22                                                      /*!< PORT3 HWSEL: HW11 Position              */\r
+#define PORT3_HWSEL_HW11_Msk                  (0x03UL << PORT3_HWSEL_HW11_Pos)                        /*!< PORT3 HWSEL: HW11 Mask                  */\r
+#define PORT3_HWSEL_HW12_Pos                  24                                                      /*!< PORT3 HWSEL: HW12 Position              */\r
+#define PORT3_HWSEL_HW12_Msk                  (0x03UL << PORT3_HWSEL_HW12_Pos)                        /*!< PORT3 HWSEL: HW12 Mask                  */\r
+#define PORT3_HWSEL_HW13_Pos                  26                                                      /*!< PORT3 HWSEL: HW13 Position              */\r
+#define PORT3_HWSEL_HW13_Msk                  (0x03UL << PORT3_HWSEL_HW13_Pos)                        /*!< PORT3 HWSEL: HW13 Mask                  */\r
+#define PORT3_HWSEL_HW14_Pos                  28                                                      /*!< PORT3 HWSEL: HW14 Position              */\r
+#define PORT3_HWSEL_HW14_Msk                  (0x03UL << PORT3_HWSEL_HW14_Pos)                        /*!< PORT3 HWSEL: HW14 Mask                  */\r
+#define PORT3_HWSEL_HW15_Pos                  30                                                      /*!< PORT3 HWSEL: HW15 Position              */\r
+#define PORT3_HWSEL_HW15_Msk                  (0x03UL << PORT3_HWSEL_HW15_Pos)                        /*!< PORT3 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT4' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT4_OUT  --------------------------------- */\r
+#define PORT4_OUT_P0_Pos                      0                                                       /*!< PORT4 OUT: P0 Position                  */\r
+#define PORT4_OUT_P0_Msk                      (0x01UL << PORT4_OUT_P0_Pos)                            /*!< PORT4 OUT: P0 Mask                      */\r
+#define PORT4_OUT_P1_Pos                      1                                                       /*!< PORT4 OUT: P1 Position                  */\r
+#define PORT4_OUT_P1_Msk                      (0x01UL << PORT4_OUT_P1_Pos)                            /*!< PORT4 OUT: P1 Mask                      */\r
+#define PORT4_OUT_P2_Pos                      2                                                       /*!< PORT4 OUT: P2 Position                  */\r
+#define PORT4_OUT_P2_Msk                      (0x01UL << PORT4_OUT_P2_Pos)                            /*!< PORT4 OUT: P2 Mask                      */\r
+#define PORT4_OUT_P3_Pos                      3                                                       /*!< PORT4 OUT: P3 Position                  */\r
+#define PORT4_OUT_P3_Msk                      (0x01UL << PORT4_OUT_P3_Pos)                            /*!< PORT4 OUT: P3 Mask                      */\r
+#define PORT4_OUT_P4_Pos                      4                                                       /*!< PORT4 OUT: P4 Position                  */\r
+#define PORT4_OUT_P4_Msk                      (0x01UL << PORT4_OUT_P4_Pos)                            /*!< PORT4 OUT: P4 Mask                      */\r
+#define PORT4_OUT_P5_Pos                      5                                                       /*!< PORT4 OUT: P5 Position                  */\r
+#define PORT4_OUT_P5_Msk                      (0x01UL << PORT4_OUT_P5_Pos)                            /*!< PORT4 OUT: P5 Mask                      */\r
+#define PORT4_OUT_P6_Pos                      6                                                       /*!< PORT4 OUT: P6 Position                  */\r
+#define PORT4_OUT_P6_Msk                      (0x01UL << PORT4_OUT_P6_Pos)                            /*!< PORT4 OUT: P6 Mask                      */\r
+#define PORT4_OUT_P7_Pos                      7                                                       /*!< PORT4 OUT: P7 Position                  */\r
+#define PORT4_OUT_P7_Msk                      (0x01UL << PORT4_OUT_P7_Pos)                            /*!< PORT4 OUT: P7 Mask                      */\r
+#define PORT4_OUT_P8_Pos                      8                                                       /*!< PORT4 OUT: P8 Position                  */\r
+#define PORT4_OUT_P8_Msk                      (0x01UL << PORT4_OUT_P8_Pos)                            /*!< PORT4 OUT: P8 Mask                      */\r
+#define PORT4_OUT_P9_Pos                      9                                                       /*!< PORT4 OUT: P9 Position                  */\r
+#define PORT4_OUT_P9_Msk                      (0x01UL << PORT4_OUT_P9_Pos)                            /*!< PORT4 OUT: P9 Mask                      */\r
+#define PORT4_OUT_P10_Pos                     10                                                      /*!< PORT4 OUT: P10 Position                 */\r
+#define PORT4_OUT_P10_Msk                     (0x01UL << PORT4_OUT_P10_Pos)                           /*!< PORT4 OUT: P10 Mask                     */\r
+#define PORT4_OUT_P11_Pos                     11                                                      /*!< PORT4 OUT: P11 Position                 */\r
+#define PORT4_OUT_P11_Msk                     (0x01UL << PORT4_OUT_P11_Pos)                           /*!< PORT4 OUT: P11 Mask                     */\r
+#define PORT4_OUT_P12_Pos                     12                                                      /*!< PORT4 OUT: P12 Position                 */\r
+#define PORT4_OUT_P12_Msk                     (0x01UL << PORT4_OUT_P12_Pos)                           /*!< PORT4 OUT: P12 Mask                     */\r
+#define PORT4_OUT_P13_Pos                     13                                                      /*!< PORT4 OUT: P13 Position                 */\r
+#define PORT4_OUT_P13_Msk                     (0x01UL << PORT4_OUT_P13_Pos)                           /*!< PORT4 OUT: P13 Mask                     */\r
+#define PORT4_OUT_P14_Pos                     14                                                      /*!< PORT4 OUT: P14 Position                 */\r
+#define PORT4_OUT_P14_Msk                     (0x01UL << PORT4_OUT_P14_Pos)                           /*!< PORT4 OUT: P14 Mask                     */\r
+#define PORT4_OUT_P15_Pos                     15                                                      /*!< PORT4 OUT: P15 Position                 */\r
+#define PORT4_OUT_P15_Msk                     (0x01UL << PORT4_OUT_P15_Pos)                           /*!< PORT4 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT4_OMR  --------------------------------- */\r
+#define PORT4_OMR_PS0_Pos                     0                                                       /*!< PORT4 OMR: PS0 Position                 */\r
+#define PORT4_OMR_PS0_Msk                     (0x01UL << PORT4_OMR_PS0_Pos)                           /*!< PORT4 OMR: PS0 Mask                     */\r
+#define PORT4_OMR_PS1_Pos                     1                                                       /*!< PORT4 OMR: PS1 Position                 */\r
+#define PORT4_OMR_PS1_Msk                     (0x01UL << PORT4_OMR_PS1_Pos)                           /*!< PORT4 OMR: PS1 Mask                     */\r
+#define PORT4_OMR_PS2_Pos                     2                                                       /*!< PORT4 OMR: PS2 Position                 */\r
+#define PORT4_OMR_PS2_Msk                     (0x01UL << PORT4_OMR_PS2_Pos)                           /*!< PORT4 OMR: PS2 Mask                     */\r
+#define PORT4_OMR_PS3_Pos                     3                                                       /*!< PORT4 OMR: PS3 Position                 */\r
+#define PORT4_OMR_PS3_Msk                     (0x01UL << PORT4_OMR_PS3_Pos)                           /*!< PORT4 OMR: PS3 Mask                     */\r
+#define PORT4_OMR_PS4_Pos                     4                                                       /*!< PORT4 OMR: PS4 Position                 */\r
+#define PORT4_OMR_PS4_Msk                     (0x01UL << PORT4_OMR_PS4_Pos)                           /*!< PORT4 OMR: PS4 Mask                     */\r
+#define PORT4_OMR_PS5_Pos                     5                                                       /*!< PORT4 OMR: PS5 Position                 */\r
+#define PORT4_OMR_PS5_Msk                     (0x01UL << PORT4_OMR_PS5_Pos)                           /*!< PORT4 OMR: PS5 Mask                     */\r
+#define PORT4_OMR_PS6_Pos                     6                                                       /*!< PORT4 OMR: PS6 Position                 */\r
+#define PORT4_OMR_PS6_Msk                     (0x01UL << PORT4_OMR_PS6_Pos)                           /*!< PORT4 OMR: PS6 Mask                     */\r
+#define PORT4_OMR_PS7_Pos                     7                                                       /*!< PORT4 OMR: PS7 Position                 */\r
+#define PORT4_OMR_PS7_Msk                     (0x01UL << PORT4_OMR_PS7_Pos)                           /*!< PORT4 OMR: PS7 Mask                     */\r
+#define PORT4_OMR_PS8_Pos                     8                                                       /*!< PORT4 OMR: PS8 Position                 */\r
+#define PORT4_OMR_PS8_Msk                     (0x01UL << PORT4_OMR_PS8_Pos)                           /*!< PORT4 OMR: PS8 Mask                     */\r
+#define PORT4_OMR_PS9_Pos                     9                                                       /*!< PORT4 OMR: PS9 Position                 */\r
+#define PORT4_OMR_PS9_Msk                     (0x01UL << PORT4_OMR_PS9_Pos)                           /*!< PORT4 OMR: PS9 Mask                     */\r
+#define PORT4_OMR_PS10_Pos                    10                                                      /*!< PORT4 OMR: PS10 Position                */\r
+#define PORT4_OMR_PS10_Msk                    (0x01UL << PORT4_OMR_PS10_Pos)                          /*!< PORT4 OMR: PS10 Mask                    */\r
+#define PORT4_OMR_PS11_Pos                    11                                                      /*!< PORT4 OMR: PS11 Position                */\r
+#define PORT4_OMR_PS11_Msk                    (0x01UL << PORT4_OMR_PS11_Pos)                          /*!< PORT4 OMR: PS11 Mask                    */\r
+#define PORT4_OMR_PS12_Pos                    12                                                      /*!< PORT4 OMR: PS12 Position                */\r
+#define PORT4_OMR_PS12_Msk                    (0x01UL << PORT4_OMR_PS12_Pos)                          /*!< PORT4 OMR: PS12 Mask                    */\r
+#define PORT4_OMR_PS13_Pos                    13                                                      /*!< PORT4 OMR: PS13 Position                */\r
+#define PORT4_OMR_PS13_Msk                    (0x01UL << PORT4_OMR_PS13_Pos)                          /*!< PORT4 OMR: PS13 Mask                    */\r
+#define PORT4_OMR_PS14_Pos                    14                                                      /*!< PORT4 OMR: PS14 Position                */\r
+#define PORT4_OMR_PS14_Msk                    (0x01UL << PORT4_OMR_PS14_Pos)                          /*!< PORT4 OMR: PS14 Mask                    */\r
+#define PORT4_OMR_PS15_Pos                    15                                                      /*!< PORT4 OMR: PS15 Position                */\r
+#define PORT4_OMR_PS15_Msk                    (0x01UL << PORT4_OMR_PS15_Pos)                          /*!< PORT4 OMR: PS15 Mask                    */\r
+#define PORT4_OMR_PR0_Pos                     16                                                      /*!< PORT4 OMR: PR0 Position                 */\r
+#define PORT4_OMR_PR0_Msk                     (0x01UL << PORT4_OMR_PR0_Pos)                           /*!< PORT4 OMR: PR0 Mask                     */\r
+#define PORT4_OMR_PR1_Pos                     17                                                      /*!< PORT4 OMR: PR1 Position                 */\r
+#define PORT4_OMR_PR1_Msk                     (0x01UL << PORT4_OMR_PR1_Pos)                           /*!< PORT4 OMR: PR1 Mask                     */\r
+#define PORT4_OMR_PR2_Pos                     18                                                      /*!< PORT4 OMR: PR2 Position                 */\r
+#define PORT4_OMR_PR2_Msk                     (0x01UL << PORT4_OMR_PR2_Pos)                           /*!< PORT4 OMR: PR2 Mask                     */\r
+#define PORT4_OMR_PR3_Pos                     19                                                      /*!< PORT4 OMR: PR3 Position                 */\r
+#define PORT4_OMR_PR3_Msk                     (0x01UL << PORT4_OMR_PR3_Pos)                           /*!< PORT4 OMR: PR3 Mask                     */\r
+#define PORT4_OMR_PR4_Pos                     20                                                      /*!< PORT4 OMR: PR4 Position                 */\r
+#define PORT4_OMR_PR4_Msk                     (0x01UL << PORT4_OMR_PR4_Pos)                           /*!< PORT4 OMR: PR4 Mask                     */\r
+#define PORT4_OMR_PR5_Pos                     21                                                      /*!< PORT4 OMR: PR5 Position                 */\r
+#define PORT4_OMR_PR5_Msk                     (0x01UL << PORT4_OMR_PR5_Pos)                           /*!< PORT4 OMR: PR5 Mask                     */\r
+#define PORT4_OMR_PR6_Pos                     22                                                      /*!< PORT4 OMR: PR6 Position                 */\r
+#define PORT4_OMR_PR6_Msk                     (0x01UL << PORT4_OMR_PR6_Pos)                           /*!< PORT4 OMR: PR6 Mask                     */\r
+#define PORT4_OMR_PR7_Pos                     23                                                      /*!< PORT4 OMR: PR7 Position                 */\r
+#define PORT4_OMR_PR7_Msk                     (0x01UL << PORT4_OMR_PR7_Pos)                           /*!< PORT4 OMR: PR7 Mask                     */\r
+#define PORT4_OMR_PR8_Pos                     24                                                      /*!< PORT4 OMR: PR8 Position                 */\r
+#define PORT4_OMR_PR8_Msk                     (0x01UL << PORT4_OMR_PR8_Pos)                           /*!< PORT4 OMR: PR8 Mask                     */\r
+#define PORT4_OMR_PR9_Pos                     25                                                      /*!< PORT4 OMR: PR9 Position                 */\r
+#define PORT4_OMR_PR9_Msk                     (0x01UL << PORT4_OMR_PR9_Pos)                           /*!< PORT4 OMR: PR9 Mask                     */\r
+#define PORT4_OMR_PR10_Pos                    26                                                      /*!< PORT4 OMR: PR10 Position                */\r
+#define PORT4_OMR_PR10_Msk                    (0x01UL << PORT4_OMR_PR10_Pos)                          /*!< PORT4 OMR: PR10 Mask                    */\r
+#define PORT4_OMR_PR11_Pos                    27                                                      /*!< PORT4 OMR: PR11 Position                */\r
+#define PORT4_OMR_PR11_Msk                    (0x01UL << PORT4_OMR_PR11_Pos)                          /*!< PORT4 OMR: PR11 Mask                    */\r
+#define PORT4_OMR_PR12_Pos                    28                                                      /*!< PORT4 OMR: PR12 Position                */\r
+#define PORT4_OMR_PR12_Msk                    (0x01UL << PORT4_OMR_PR12_Pos)                          /*!< PORT4 OMR: PR12 Mask                    */\r
+#define PORT4_OMR_PR13_Pos                    29                                                      /*!< PORT4 OMR: PR13 Position                */\r
+#define PORT4_OMR_PR13_Msk                    (0x01UL << PORT4_OMR_PR13_Pos)                          /*!< PORT4 OMR: PR13 Mask                    */\r
+#define PORT4_OMR_PR14_Pos                    30                                                      /*!< PORT4 OMR: PR14 Position                */\r
+#define PORT4_OMR_PR14_Msk                    (0x01UL << PORT4_OMR_PR14_Pos)                          /*!< PORT4 OMR: PR14 Mask                    */\r
+#define PORT4_OMR_PR15_Pos                    31                                                      /*!< PORT4 OMR: PR15 Position                */\r
+#define PORT4_OMR_PR15_Msk                    (0x01UL << PORT4_OMR_PR15_Pos)                          /*!< PORT4 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT4_IOCR0  -------------------------------- */\r
+#define PORT4_IOCR0_PC0_Pos                   3                                                       /*!< PORT4 IOCR0: PC0 Position               */\r
+#define PORT4_IOCR0_PC0_Msk                   (0x1fUL << PORT4_IOCR0_PC0_Pos)                         /*!< PORT4 IOCR0: PC0 Mask                   */\r
+#define PORT4_IOCR0_PC1_Pos                   11                                                      /*!< PORT4 IOCR0: PC1 Position               */\r
+#define PORT4_IOCR0_PC1_Msk                   (0x1fUL << PORT4_IOCR0_PC1_Pos)                         /*!< PORT4 IOCR0: PC1 Mask                   */\r
+#define PORT4_IOCR0_PC2_Pos                   19                                                      /*!< PORT4 IOCR0: PC2 Position               */\r
+#define PORT4_IOCR0_PC2_Msk                   (0x1fUL << PORT4_IOCR0_PC2_Pos)                         /*!< PORT4 IOCR0: PC2 Mask                   */\r
+#define PORT4_IOCR0_PC3_Pos                   27                                                      /*!< PORT4 IOCR0: PC3 Position               */\r
+#define PORT4_IOCR0_PC3_Msk                   (0x1fUL << PORT4_IOCR0_PC3_Pos)                         /*!< PORT4 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT4_IOCR4  -------------------------------- */\r
+#define PORT4_IOCR4_PC4_Pos                   3                                                       /*!< PORT4 IOCR4: PC4 Position               */\r
+#define PORT4_IOCR4_PC4_Msk                   (0x1fUL << PORT4_IOCR4_PC4_Pos)                         /*!< PORT4 IOCR4: PC4 Mask                   */\r
+#define PORT4_IOCR4_PC5_Pos                   11                                                      /*!< PORT4 IOCR4: PC5 Position               */\r
+#define PORT4_IOCR4_PC5_Msk                   (0x1fUL << PORT4_IOCR4_PC5_Pos)                         /*!< PORT4 IOCR4: PC5 Mask                   */\r
+#define PORT4_IOCR4_PC6_Pos                   19                                                      /*!< PORT4 IOCR4: PC6 Position               */\r
+#define PORT4_IOCR4_PC6_Msk                   (0x1fUL << PORT4_IOCR4_PC6_Pos)                         /*!< PORT4 IOCR4: PC6 Mask                   */\r
+#define PORT4_IOCR4_PC7_Pos                   27                                                      /*!< PORT4 IOCR4: PC7 Position               */\r
+#define PORT4_IOCR4_PC7_Msk                   (0x1fUL << PORT4_IOCR4_PC7_Pos)                         /*!< PORT4 IOCR4: PC7 Mask                   */\r
+\r
+/* ----------------------------------  PORT4_IN  ---------------------------------- */\r
+#define PORT4_IN_P0_Pos                       0                                                       /*!< PORT4 IN: P0 Position                   */\r
+#define PORT4_IN_P0_Msk                       (0x01UL << PORT4_IN_P0_Pos)                             /*!< PORT4 IN: P0 Mask                       */\r
+#define PORT4_IN_P1_Pos                       1                                                       /*!< PORT4 IN: P1 Position                   */\r
+#define PORT4_IN_P1_Msk                       (0x01UL << PORT4_IN_P1_Pos)                             /*!< PORT4 IN: P1 Mask                       */\r
+#define PORT4_IN_P2_Pos                       2                                                       /*!< PORT4 IN: P2 Position                   */\r
+#define PORT4_IN_P2_Msk                       (0x01UL << PORT4_IN_P2_Pos)                             /*!< PORT4 IN: P2 Mask                       */\r
+#define PORT4_IN_P3_Pos                       3                                                       /*!< PORT4 IN: P3 Position                   */\r
+#define PORT4_IN_P3_Msk                       (0x01UL << PORT4_IN_P3_Pos)                             /*!< PORT4 IN: P3 Mask                       */\r
+#define PORT4_IN_P4_Pos                       4                                                       /*!< PORT4 IN: P4 Position                   */\r
+#define PORT4_IN_P4_Msk                       (0x01UL << PORT4_IN_P4_Pos)                             /*!< PORT4 IN: P4 Mask                       */\r
+#define PORT4_IN_P5_Pos                       5                                                       /*!< PORT4 IN: P5 Position                   */\r
+#define PORT4_IN_P5_Msk                       (0x01UL << PORT4_IN_P5_Pos)                             /*!< PORT4 IN: P5 Mask                       */\r
+#define PORT4_IN_P6_Pos                       6                                                       /*!< PORT4 IN: P6 Position                   */\r
+#define PORT4_IN_P6_Msk                       (0x01UL << PORT4_IN_P6_Pos)                             /*!< PORT4 IN: P6 Mask                       */\r
+#define PORT4_IN_P7_Pos                       7                                                       /*!< PORT4 IN: P7 Position                   */\r
+#define PORT4_IN_P7_Msk                       (0x01UL << PORT4_IN_P7_Pos)                             /*!< PORT4 IN: P7 Mask                       */\r
+#define PORT4_IN_P8_Pos                       8                                                       /*!< PORT4 IN: P8 Position                   */\r
+#define PORT4_IN_P8_Msk                       (0x01UL << PORT4_IN_P8_Pos)                             /*!< PORT4 IN: P8 Mask                       */\r
+#define PORT4_IN_P9_Pos                       9                                                       /*!< PORT4 IN: P9 Position                   */\r
+#define PORT4_IN_P9_Msk                       (0x01UL << PORT4_IN_P9_Pos)                             /*!< PORT4 IN: P9 Mask                       */\r
+#define PORT4_IN_P10_Pos                      10                                                      /*!< PORT4 IN: P10 Position                  */\r
+#define PORT4_IN_P10_Msk                      (0x01UL << PORT4_IN_P10_Pos)                            /*!< PORT4 IN: P10 Mask                      */\r
+#define PORT4_IN_P11_Pos                      11                                                      /*!< PORT4 IN: P11 Position                  */\r
+#define PORT4_IN_P11_Msk                      (0x01UL << PORT4_IN_P11_Pos)                            /*!< PORT4 IN: P11 Mask                      */\r
+#define PORT4_IN_P12_Pos                      12                                                      /*!< PORT4 IN: P12 Position                  */\r
+#define PORT4_IN_P12_Msk                      (0x01UL << PORT4_IN_P12_Pos)                            /*!< PORT4 IN: P12 Mask                      */\r
+#define PORT4_IN_P13_Pos                      13                                                      /*!< PORT4 IN: P13 Position                  */\r
+#define PORT4_IN_P13_Msk                      (0x01UL << PORT4_IN_P13_Pos)                            /*!< PORT4 IN: P13 Mask                      */\r
+#define PORT4_IN_P14_Pos                      14                                                      /*!< PORT4 IN: P14 Position                  */\r
+#define PORT4_IN_P14_Msk                      (0x01UL << PORT4_IN_P14_Pos)                            /*!< PORT4 IN: P14 Mask                      */\r
+#define PORT4_IN_P15_Pos                      15                                                      /*!< PORT4 IN: P15 Position                  */\r
+#define PORT4_IN_P15_Msk                      (0x01UL << PORT4_IN_P15_Pos)                            /*!< PORT4 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT4_PDR0  --------------------------------- */\r
+#define PORT4_PDR0_PD0_Pos                    0                                                       /*!< PORT4 PDR0: PD0 Position                */\r
+#define PORT4_PDR0_PD0_Msk                    (0x07UL << PORT4_PDR0_PD0_Pos)                          /*!< PORT4 PDR0: PD0 Mask                    */\r
+#define PORT4_PDR0_PD1_Pos                    4                                                       /*!< PORT4 PDR0: PD1 Position                */\r
+#define PORT4_PDR0_PD1_Msk                    (0x07UL << PORT4_PDR0_PD1_Pos)                          /*!< PORT4 PDR0: PD1 Mask                    */\r
+#define PORT4_PDR0_PD2_Pos                    8                                                       /*!< PORT4 PDR0: PD2 Position                */\r
+#define PORT4_PDR0_PD2_Msk                    (0x07UL << PORT4_PDR0_PD2_Pos)                          /*!< PORT4 PDR0: PD2 Mask                    */\r
+#define PORT4_PDR0_PD3_Pos                    12                                                      /*!< PORT4 PDR0: PD3 Position                */\r
+#define PORT4_PDR0_PD3_Msk                    (0x07UL << PORT4_PDR0_PD3_Pos)                          /*!< PORT4 PDR0: PD3 Mask                    */\r
+#define PORT4_PDR0_PD4_Pos                    16                                                      /*!< PORT4 PDR0: PD4 Position                */\r
+#define PORT4_PDR0_PD4_Msk                    (0x07UL << PORT4_PDR0_PD4_Pos)                          /*!< PORT4 PDR0: PD4 Mask                    */\r
+#define PORT4_PDR0_PD5_Pos                    20                                                      /*!< PORT4 PDR0: PD5 Position                */\r
+#define PORT4_PDR0_PD5_Msk                    (0x07UL << PORT4_PDR0_PD5_Pos)                          /*!< PORT4 PDR0: PD5 Mask                    */\r
+#define PORT4_PDR0_PD6_Pos                    24                                                      /*!< PORT4 PDR0: PD6 Position                */\r
+#define PORT4_PDR0_PD6_Msk                    (0x07UL << PORT4_PDR0_PD6_Pos)                          /*!< PORT4 PDR0: PD6 Mask                    */\r
+#define PORT4_PDR0_PD7_Pos                    28                                                      /*!< PORT4 PDR0: PD7 Position                */\r
+#define PORT4_PDR0_PD7_Msk                    (0x07UL << PORT4_PDR0_PD7_Pos)                          /*!< PORT4 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT4_PDISC  -------------------------------- */\r
+#define PORT4_PDISC_PDIS0_Pos                 0                                                       /*!< PORT4 PDISC: PDIS0 Position             */\r
+#define PORT4_PDISC_PDIS0_Msk                 (0x01UL << PORT4_PDISC_PDIS0_Pos)                       /*!< PORT4 PDISC: PDIS0 Mask                 */\r
+#define PORT4_PDISC_PDIS1_Pos                 1                                                       /*!< PORT4 PDISC: PDIS1 Position             */\r
+#define PORT4_PDISC_PDIS1_Msk                 (0x01UL << PORT4_PDISC_PDIS1_Pos)                       /*!< PORT4 PDISC: PDIS1 Mask                 */\r
+#define PORT4_PDISC_PDIS2_Pos                 2                                                       /*!< PORT4 PDISC: PDIS2 Position             */\r
+#define PORT4_PDISC_PDIS2_Msk                 (0x01UL << PORT4_PDISC_PDIS2_Pos)                       /*!< PORT4 PDISC: PDIS2 Mask                 */\r
+#define PORT4_PDISC_PDIS3_Pos                 3                                                       /*!< PORT4 PDISC: PDIS3 Position             */\r
+#define PORT4_PDISC_PDIS3_Msk                 (0x01UL << PORT4_PDISC_PDIS3_Pos)                       /*!< PORT4 PDISC: PDIS3 Mask                 */\r
+#define PORT4_PDISC_PDIS4_Pos                 4                                                       /*!< PORT4 PDISC: PDIS4 Position             */\r
+#define PORT4_PDISC_PDIS4_Msk                 (0x01UL << PORT4_PDISC_PDIS4_Pos)                       /*!< PORT4 PDISC: PDIS4 Mask                 */\r
+#define PORT4_PDISC_PDIS5_Pos                 5                                                       /*!< PORT4 PDISC: PDIS5 Position             */\r
+#define PORT4_PDISC_PDIS5_Msk                 (0x01UL << PORT4_PDISC_PDIS5_Pos)                       /*!< PORT4 PDISC: PDIS5 Mask                 */\r
+#define PORT4_PDISC_PDIS6_Pos                 6                                                       /*!< PORT4 PDISC: PDIS6 Position             */\r
+#define PORT4_PDISC_PDIS6_Msk                 (0x01UL << PORT4_PDISC_PDIS6_Pos)                       /*!< PORT4 PDISC: PDIS6 Mask                 */\r
+#define PORT4_PDISC_PDIS7_Pos                 7                                                       /*!< PORT4 PDISC: PDIS7 Position             */\r
+#define PORT4_PDISC_PDIS7_Msk                 (0x01UL << PORT4_PDISC_PDIS7_Pos)                       /*!< PORT4 PDISC: PDIS7 Mask                 */\r
+#define PORT4_PDISC_PDIS8_Pos                 8                                                       /*!< PORT4 PDISC: PDIS8 Position             */\r
+#define PORT4_PDISC_PDIS8_Msk                 (0x01UL << PORT4_PDISC_PDIS8_Pos)                       /*!< PORT4 PDISC: PDIS8 Mask                 */\r
+#define PORT4_PDISC_PDIS9_Pos                 9                                                       /*!< PORT4 PDISC: PDIS9 Position             */\r
+#define PORT4_PDISC_PDIS9_Msk                 (0x01UL << PORT4_PDISC_PDIS9_Pos)                       /*!< PORT4 PDISC: PDIS9 Mask                 */\r
+#define PORT4_PDISC_PDIS10_Pos                10                                                      /*!< PORT4 PDISC: PDIS10 Position            */\r
+#define PORT4_PDISC_PDIS10_Msk                (0x01UL << PORT4_PDISC_PDIS10_Pos)                      /*!< PORT4 PDISC: PDIS10 Mask                */\r
+#define PORT4_PDISC_PDIS11_Pos                11                                                      /*!< PORT4 PDISC: PDIS11 Position            */\r
+#define PORT4_PDISC_PDIS11_Msk                (0x01UL << PORT4_PDISC_PDIS11_Pos)                      /*!< PORT4 PDISC: PDIS11 Mask                */\r
+#define PORT4_PDISC_PDIS12_Pos                12                                                      /*!< PORT4 PDISC: PDIS12 Position            */\r
+#define PORT4_PDISC_PDIS12_Msk                (0x01UL << PORT4_PDISC_PDIS12_Pos)                      /*!< PORT4 PDISC: PDIS12 Mask                */\r
+#define PORT4_PDISC_PDIS13_Pos                13                                                      /*!< PORT4 PDISC: PDIS13 Position            */\r
+#define PORT4_PDISC_PDIS13_Msk                (0x01UL << PORT4_PDISC_PDIS13_Pos)                      /*!< PORT4 PDISC: PDIS13 Mask                */\r
+#define PORT4_PDISC_PDIS14_Pos                14                                                      /*!< PORT4 PDISC: PDIS14 Position            */\r
+#define PORT4_PDISC_PDIS14_Msk                (0x01UL << PORT4_PDISC_PDIS14_Pos)                      /*!< PORT4 PDISC: PDIS14 Mask                */\r
+#define PORT4_PDISC_PDIS15_Pos                15                                                      /*!< PORT4 PDISC: PDIS15 Position            */\r
+#define PORT4_PDISC_PDIS15_Msk                (0x01UL << PORT4_PDISC_PDIS15_Pos)                      /*!< PORT4 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT4_PPS  --------------------------------- */\r
+#define PORT4_PPS_PPS0_Pos                    0                                                       /*!< PORT4 PPS: PPS0 Position                */\r
+#define PORT4_PPS_PPS0_Msk                    (0x01UL << PORT4_PPS_PPS0_Pos)                          /*!< PORT4 PPS: PPS0 Mask                    */\r
+#define PORT4_PPS_PPS1_Pos                    1                                                       /*!< PORT4 PPS: PPS1 Position                */\r
+#define PORT4_PPS_PPS1_Msk                    (0x01UL << PORT4_PPS_PPS1_Pos)                          /*!< PORT4 PPS: PPS1 Mask                    */\r
+#define PORT4_PPS_PPS2_Pos                    2                                                       /*!< PORT4 PPS: PPS2 Position                */\r
+#define PORT4_PPS_PPS2_Msk                    (0x01UL << PORT4_PPS_PPS2_Pos)                          /*!< PORT4 PPS: PPS2 Mask                    */\r
+#define PORT4_PPS_PPS3_Pos                    3                                                       /*!< PORT4 PPS: PPS3 Position                */\r
+#define PORT4_PPS_PPS3_Msk                    (0x01UL << PORT4_PPS_PPS3_Pos)                          /*!< PORT4 PPS: PPS3 Mask                    */\r
+#define PORT4_PPS_PPS4_Pos                    4                                                       /*!< PORT4 PPS: PPS4 Position                */\r
+#define PORT4_PPS_PPS4_Msk                    (0x01UL << PORT4_PPS_PPS4_Pos)                          /*!< PORT4 PPS: PPS4 Mask                    */\r
+#define PORT4_PPS_PPS5_Pos                    5                                                       /*!< PORT4 PPS: PPS5 Position                */\r
+#define PORT4_PPS_PPS5_Msk                    (0x01UL << PORT4_PPS_PPS5_Pos)                          /*!< PORT4 PPS: PPS5 Mask                    */\r
+#define PORT4_PPS_PPS6_Pos                    6                                                       /*!< PORT4 PPS: PPS6 Position                */\r
+#define PORT4_PPS_PPS6_Msk                    (0x01UL << PORT4_PPS_PPS6_Pos)                          /*!< PORT4 PPS: PPS6 Mask                    */\r
+#define PORT4_PPS_PPS7_Pos                    7                                                       /*!< PORT4 PPS: PPS7 Position                */\r
+#define PORT4_PPS_PPS7_Msk                    (0x01UL << PORT4_PPS_PPS7_Pos)                          /*!< PORT4 PPS: PPS7 Mask                    */\r
+#define PORT4_PPS_PPS8_Pos                    8                                                       /*!< PORT4 PPS: PPS8 Position                */\r
+#define PORT4_PPS_PPS8_Msk                    (0x01UL << PORT4_PPS_PPS8_Pos)                          /*!< PORT4 PPS: PPS8 Mask                    */\r
+#define PORT4_PPS_PPS9_Pos                    9                                                       /*!< PORT4 PPS: PPS9 Position                */\r
+#define PORT4_PPS_PPS9_Msk                    (0x01UL << PORT4_PPS_PPS9_Pos)                          /*!< PORT4 PPS: PPS9 Mask                    */\r
+#define PORT4_PPS_PPS10_Pos                   10                                                      /*!< PORT4 PPS: PPS10 Position               */\r
+#define PORT4_PPS_PPS10_Msk                   (0x01UL << PORT4_PPS_PPS10_Pos)                         /*!< PORT4 PPS: PPS10 Mask                   */\r
+#define PORT4_PPS_PPS11_Pos                   11                                                      /*!< PORT4 PPS: PPS11 Position               */\r
+#define PORT4_PPS_PPS11_Msk                   (0x01UL << PORT4_PPS_PPS11_Pos)                         /*!< PORT4 PPS: PPS11 Mask                   */\r
+#define PORT4_PPS_PPS12_Pos                   12                                                      /*!< PORT4 PPS: PPS12 Position               */\r
+#define PORT4_PPS_PPS12_Msk                   (0x01UL << PORT4_PPS_PPS12_Pos)                         /*!< PORT4 PPS: PPS12 Mask                   */\r
+#define PORT4_PPS_PPS13_Pos                   13                                                      /*!< PORT4 PPS: PPS13 Position               */\r
+#define PORT4_PPS_PPS13_Msk                   (0x01UL << PORT4_PPS_PPS13_Pos)                         /*!< PORT4 PPS: PPS13 Mask                   */\r
+#define PORT4_PPS_PPS14_Pos                   14                                                      /*!< PORT4 PPS: PPS14 Position               */\r
+#define PORT4_PPS_PPS14_Msk                   (0x01UL << PORT4_PPS_PPS14_Pos)                         /*!< PORT4 PPS: PPS14 Mask                   */\r
+#define PORT4_PPS_PPS15_Pos                   15                                                      /*!< PORT4 PPS: PPS15 Position               */\r
+#define PORT4_PPS_PPS15_Msk                   (0x01UL << PORT4_PPS_PPS15_Pos)                         /*!< PORT4 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT4_HWSEL  -------------------------------- */\r
+#define PORT4_HWSEL_HW0_Pos                   0                                                       /*!< PORT4 HWSEL: HW0 Position               */\r
+#define PORT4_HWSEL_HW0_Msk                   (0x03UL << PORT4_HWSEL_HW0_Pos)                         /*!< PORT4 HWSEL: HW0 Mask                   */\r
+#define PORT4_HWSEL_HW1_Pos                   2                                                       /*!< PORT4 HWSEL: HW1 Position               */\r
+#define PORT4_HWSEL_HW1_Msk                   (0x03UL << PORT4_HWSEL_HW1_Pos)                         /*!< PORT4 HWSEL: HW1 Mask                   */\r
+#define PORT4_HWSEL_HW2_Pos                   4                                                       /*!< PORT4 HWSEL: HW2 Position               */\r
+#define PORT4_HWSEL_HW2_Msk                   (0x03UL << PORT4_HWSEL_HW2_Pos)                         /*!< PORT4 HWSEL: HW2 Mask                   */\r
+#define PORT4_HWSEL_HW3_Pos                   6                                                       /*!< PORT4 HWSEL: HW3 Position               */\r
+#define PORT4_HWSEL_HW3_Msk                   (0x03UL << PORT4_HWSEL_HW3_Pos)                         /*!< PORT4 HWSEL: HW3 Mask                   */\r
+#define PORT4_HWSEL_HW4_Pos                   8                                                       /*!< PORT4 HWSEL: HW4 Position               */\r
+#define PORT4_HWSEL_HW4_Msk                   (0x03UL << PORT4_HWSEL_HW4_Pos)                         /*!< PORT4 HWSEL: HW4 Mask                   */\r
+#define PORT4_HWSEL_HW5_Pos                   10                                                      /*!< PORT4 HWSEL: HW5 Position               */\r
+#define PORT4_HWSEL_HW5_Msk                   (0x03UL << PORT4_HWSEL_HW5_Pos)                         /*!< PORT4 HWSEL: HW5 Mask                   */\r
+#define PORT4_HWSEL_HW6_Pos                   12                                                      /*!< PORT4 HWSEL: HW6 Position               */\r
+#define PORT4_HWSEL_HW6_Msk                   (0x03UL << PORT4_HWSEL_HW6_Pos)                         /*!< PORT4 HWSEL: HW6 Mask                   */\r
+#define PORT4_HWSEL_HW7_Pos                   14                                                      /*!< PORT4 HWSEL: HW7 Position               */\r
+#define PORT4_HWSEL_HW7_Msk                   (0x03UL << PORT4_HWSEL_HW7_Pos)                         /*!< PORT4 HWSEL: HW7 Mask                   */\r
+#define PORT4_HWSEL_HW8_Pos                   16                                                      /*!< PORT4 HWSEL: HW8 Position               */\r
+#define PORT4_HWSEL_HW8_Msk                   (0x03UL << PORT4_HWSEL_HW8_Pos)                         /*!< PORT4 HWSEL: HW8 Mask                   */\r
+#define PORT4_HWSEL_HW9_Pos                   18                                                      /*!< PORT4 HWSEL: HW9 Position               */\r
+#define PORT4_HWSEL_HW9_Msk                   (0x03UL << PORT4_HWSEL_HW9_Pos)                         /*!< PORT4 HWSEL: HW9 Mask                   */\r
+#define PORT4_HWSEL_HW10_Pos                  20                                                      /*!< PORT4 HWSEL: HW10 Position              */\r
+#define PORT4_HWSEL_HW10_Msk                  (0x03UL << PORT4_HWSEL_HW10_Pos)                        /*!< PORT4 HWSEL: HW10 Mask                  */\r
+#define PORT4_HWSEL_HW11_Pos                  22                                                      /*!< PORT4 HWSEL: HW11 Position              */\r
+#define PORT4_HWSEL_HW11_Msk                  (0x03UL << PORT4_HWSEL_HW11_Pos)                        /*!< PORT4 HWSEL: HW11 Mask                  */\r
+#define PORT4_HWSEL_HW12_Pos                  24                                                      /*!< PORT4 HWSEL: HW12 Position              */\r
+#define PORT4_HWSEL_HW12_Msk                  (0x03UL << PORT4_HWSEL_HW12_Pos)                        /*!< PORT4 HWSEL: HW12 Mask                  */\r
+#define PORT4_HWSEL_HW13_Pos                  26                                                      /*!< PORT4 HWSEL: HW13 Position              */\r
+#define PORT4_HWSEL_HW13_Msk                  (0x03UL << PORT4_HWSEL_HW13_Pos)                        /*!< PORT4 HWSEL: HW13 Mask                  */\r
+#define PORT4_HWSEL_HW14_Pos                  28                                                      /*!< PORT4 HWSEL: HW14 Position              */\r
+#define PORT4_HWSEL_HW14_Msk                  (0x03UL << PORT4_HWSEL_HW14_Pos)                        /*!< PORT4 HWSEL: HW14 Mask                  */\r
+#define PORT4_HWSEL_HW15_Pos                  30                                                      /*!< PORT4 HWSEL: HW15 Position              */\r
+#define PORT4_HWSEL_HW15_Msk                  (0x03UL << PORT4_HWSEL_HW15_Pos)                        /*!< PORT4 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT5' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT5_OUT  --------------------------------- */\r
+#define PORT5_OUT_P0_Pos                      0                                                       /*!< PORT5 OUT: P0 Position                  */\r
+#define PORT5_OUT_P0_Msk                      (0x01UL << PORT5_OUT_P0_Pos)                            /*!< PORT5 OUT: P0 Mask                      */\r
+#define PORT5_OUT_P1_Pos                      1                                                       /*!< PORT5 OUT: P1 Position                  */\r
+#define PORT5_OUT_P1_Msk                      (0x01UL << PORT5_OUT_P1_Pos)                            /*!< PORT5 OUT: P1 Mask                      */\r
+#define PORT5_OUT_P2_Pos                      2                                                       /*!< PORT5 OUT: P2 Position                  */\r
+#define PORT5_OUT_P2_Msk                      (0x01UL << PORT5_OUT_P2_Pos)                            /*!< PORT5 OUT: P2 Mask                      */\r
+#define PORT5_OUT_P3_Pos                      3                                                       /*!< PORT5 OUT: P3 Position                  */\r
+#define PORT5_OUT_P3_Msk                      (0x01UL << PORT5_OUT_P3_Pos)                            /*!< PORT5 OUT: P3 Mask                      */\r
+#define PORT5_OUT_P4_Pos                      4                                                       /*!< PORT5 OUT: P4 Position                  */\r
+#define PORT5_OUT_P4_Msk                      (0x01UL << PORT5_OUT_P4_Pos)                            /*!< PORT5 OUT: P4 Mask                      */\r
+#define PORT5_OUT_P5_Pos                      5                                                       /*!< PORT5 OUT: P5 Position                  */\r
+#define PORT5_OUT_P5_Msk                      (0x01UL << PORT5_OUT_P5_Pos)                            /*!< PORT5 OUT: P5 Mask                      */\r
+#define PORT5_OUT_P6_Pos                      6                                                       /*!< PORT5 OUT: P6 Position                  */\r
+#define PORT5_OUT_P6_Msk                      (0x01UL << PORT5_OUT_P6_Pos)                            /*!< PORT5 OUT: P6 Mask                      */\r
+#define PORT5_OUT_P7_Pos                      7                                                       /*!< PORT5 OUT: P7 Position                  */\r
+#define PORT5_OUT_P7_Msk                      (0x01UL << PORT5_OUT_P7_Pos)                            /*!< PORT5 OUT: P7 Mask                      */\r
+#define PORT5_OUT_P8_Pos                      8                                                       /*!< PORT5 OUT: P8 Position                  */\r
+#define PORT5_OUT_P8_Msk                      (0x01UL << PORT5_OUT_P8_Pos)                            /*!< PORT5 OUT: P8 Mask                      */\r
+#define PORT5_OUT_P9_Pos                      9                                                       /*!< PORT5 OUT: P9 Position                  */\r
+#define PORT5_OUT_P9_Msk                      (0x01UL << PORT5_OUT_P9_Pos)                            /*!< PORT5 OUT: P9 Mask                      */\r
+#define PORT5_OUT_P10_Pos                     10                                                      /*!< PORT5 OUT: P10 Position                 */\r
+#define PORT5_OUT_P10_Msk                     (0x01UL << PORT5_OUT_P10_Pos)                           /*!< PORT5 OUT: P10 Mask                     */\r
+#define PORT5_OUT_P11_Pos                     11                                                      /*!< PORT5 OUT: P11 Position                 */\r
+#define PORT5_OUT_P11_Msk                     (0x01UL << PORT5_OUT_P11_Pos)                           /*!< PORT5 OUT: P11 Mask                     */\r
+#define PORT5_OUT_P12_Pos                     12                                                      /*!< PORT5 OUT: P12 Position                 */\r
+#define PORT5_OUT_P12_Msk                     (0x01UL << PORT5_OUT_P12_Pos)                           /*!< PORT5 OUT: P12 Mask                     */\r
+#define PORT5_OUT_P13_Pos                     13                                                      /*!< PORT5 OUT: P13 Position                 */\r
+#define PORT5_OUT_P13_Msk                     (0x01UL << PORT5_OUT_P13_Pos)                           /*!< PORT5 OUT: P13 Mask                     */\r
+#define PORT5_OUT_P14_Pos                     14                                                      /*!< PORT5 OUT: P14 Position                 */\r
+#define PORT5_OUT_P14_Msk                     (0x01UL << PORT5_OUT_P14_Pos)                           /*!< PORT5 OUT: P14 Mask                     */\r
+#define PORT5_OUT_P15_Pos                     15                                                      /*!< PORT5 OUT: P15 Position                 */\r
+#define PORT5_OUT_P15_Msk                     (0x01UL << PORT5_OUT_P15_Pos)                           /*!< PORT5 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT5_OMR  --------------------------------- */\r
+#define PORT5_OMR_PS0_Pos                     0                                                       /*!< PORT5 OMR: PS0 Position                 */\r
+#define PORT5_OMR_PS0_Msk                     (0x01UL << PORT5_OMR_PS0_Pos)                           /*!< PORT5 OMR: PS0 Mask                     */\r
+#define PORT5_OMR_PS1_Pos                     1                                                       /*!< PORT5 OMR: PS1 Position                 */\r
+#define PORT5_OMR_PS1_Msk                     (0x01UL << PORT5_OMR_PS1_Pos)                           /*!< PORT5 OMR: PS1 Mask                     */\r
+#define PORT5_OMR_PS2_Pos                     2                                                       /*!< PORT5 OMR: PS2 Position                 */\r
+#define PORT5_OMR_PS2_Msk                     (0x01UL << PORT5_OMR_PS2_Pos)                           /*!< PORT5 OMR: PS2 Mask                     */\r
+#define PORT5_OMR_PS3_Pos                     3                                                       /*!< PORT5 OMR: PS3 Position                 */\r
+#define PORT5_OMR_PS3_Msk                     (0x01UL << PORT5_OMR_PS3_Pos)                           /*!< PORT5 OMR: PS3 Mask                     */\r
+#define PORT5_OMR_PS4_Pos                     4                                                       /*!< PORT5 OMR: PS4 Position                 */\r
+#define PORT5_OMR_PS4_Msk                     (0x01UL << PORT5_OMR_PS4_Pos)                           /*!< PORT5 OMR: PS4 Mask                     */\r
+#define PORT5_OMR_PS5_Pos                     5                                                       /*!< PORT5 OMR: PS5 Position                 */\r
+#define PORT5_OMR_PS5_Msk                     (0x01UL << PORT5_OMR_PS5_Pos)                           /*!< PORT5 OMR: PS5 Mask                     */\r
+#define PORT5_OMR_PS6_Pos                     6                                                       /*!< PORT5 OMR: PS6 Position                 */\r
+#define PORT5_OMR_PS6_Msk                     (0x01UL << PORT5_OMR_PS6_Pos)                           /*!< PORT5 OMR: PS6 Mask                     */\r
+#define PORT5_OMR_PS7_Pos                     7                                                       /*!< PORT5 OMR: PS7 Position                 */\r
+#define PORT5_OMR_PS7_Msk                     (0x01UL << PORT5_OMR_PS7_Pos)                           /*!< PORT5 OMR: PS7 Mask                     */\r
+#define PORT5_OMR_PS8_Pos                     8                                                       /*!< PORT5 OMR: PS8 Position                 */\r
+#define PORT5_OMR_PS8_Msk                     (0x01UL << PORT5_OMR_PS8_Pos)                           /*!< PORT5 OMR: PS8 Mask                     */\r
+#define PORT5_OMR_PS9_Pos                     9                                                       /*!< PORT5 OMR: PS9 Position                 */\r
+#define PORT5_OMR_PS9_Msk                     (0x01UL << PORT5_OMR_PS9_Pos)                           /*!< PORT5 OMR: PS9 Mask                     */\r
+#define PORT5_OMR_PS10_Pos                    10                                                      /*!< PORT5 OMR: PS10 Position                */\r
+#define PORT5_OMR_PS10_Msk                    (0x01UL << PORT5_OMR_PS10_Pos)                          /*!< PORT5 OMR: PS10 Mask                    */\r
+#define PORT5_OMR_PS11_Pos                    11                                                      /*!< PORT5 OMR: PS11 Position                */\r
+#define PORT5_OMR_PS11_Msk                    (0x01UL << PORT5_OMR_PS11_Pos)                          /*!< PORT5 OMR: PS11 Mask                    */\r
+#define PORT5_OMR_PS12_Pos                    12                                                      /*!< PORT5 OMR: PS12 Position                */\r
+#define PORT5_OMR_PS12_Msk                    (0x01UL << PORT5_OMR_PS12_Pos)                          /*!< PORT5 OMR: PS12 Mask                    */\r
+#define PORT5_OMR_PS13_Pos                    13                                                      /*!< PORT5 OMR: PS13 Position                */\r
+#define PORT5_OMR_PS13_Msk                    (0x01UL << PORT5_OMR_PS13_Pos)                          /*!< PORT5 OMR: PS13 Mask                    */\r
+#define PORT5_OMR_PS14_Pos                    14                                                      /*!< PORT5 OMR: PS14 Position                */\r
+#define PORT5_OMR_PS14_Msk                    (0x01UL << PORT5_OMR_PS14_Pos)                          /*!< PORT5 OMR: PS14 Mask                    */\r
+#define PORT5_OMR_PS15_Pos                    15                                                      /*!< PORT5 OMR: PS15 Position                */\r
+#define PORT5_OMR_PS15_Msk                    (0x01UL << PORT5_OMR_PS15_Pos)                          /*!< PORT5 OMR: PS15 Mask                    */\r
+#define PORT5_OMR_PR0_Pos                     16                                                      /*!< PORT5 OMR: PR0 Position                 */\r
+#define PORT5_OMR_PR0_Msk                     (0x01UL << PORT5_OMR_PR0_Pos)                           /*!< PORT5 OMR: PR0 Mask                     */\r
+#define PORT5_OMR_PR1_Pos                     17                                                      /*!< PORT5 OMR: PR1 Position                 */\r
+#define PORT5_OMR_PR1_Msk                     (0x01UL << PORT5_OMR_PR1_Pos)                           /*!< PORT5 OMR: PR1 Mask                     */\r
+#define PORT5_OMR_PR2_Pos                     18                                                      /*!< PORT5 OMR: PR2 Position                 */\r
+#define PORT5_OMR_PR2_Msk                     (0x01UL << PORT5_OMR_PR2_Pos)                           /*!< PORT5 OMR: PR2 Mask                     */\r
+#define PORT5_OMR_PR3_Pos                     19                                                      /*!< PORT5 OMR: PR3 Position                 */\r
+#define PORT5_OMR_PR3_Msk                     (0x01UL << PORT5_OMR_PR3_Pos)                           /*!< PORT5 OMR: PR3 Mask                     */\r
+#define PORT5_OMR_PR4_Pos                     20                                                      /*!< PORT5 OMR: PR4 Position                 */\r
+#define PORT5_OMR_PR4_Msk                     (0x01UL << PORT5_OMR_PR4_Pos)                           /*!< PORT5 OMR: PR4 Mask                     */\r
+#define PORT5_OMR_PR5_Pos                     21                                                      /*!< PORT5 OMR: PR5 Position                 */\r
+#define PORT5_OMR_PR5_Msk                     (0x01UL << PORT5_OMR_PR5_Pos)                           /*!< PORT5 OMR: PR5 Mask                     */\r
+#define PORT5_OMR_PR6_Pos                     22                                                      /*!< PORT5 OMR: PR6 Position                 */\r
+#define PORT5_OMR_PR6_Msk                     (0x01UL << PORT5_OMR_PR6_Pos)                           /*!< PORT5 OMR: PR6 Mask                     */\r
+#define PORT5_OMR_PR7_Pos                     23                                                      /*!< PORT5 OMR: PR7 Position                 */\r
+#define PORT5_OMR_PR7_Msk                     (0x01UL << PORT5_OMR_PR7_Pos)                           /*!< PORT5 OMR: PR7 Mask                     */\r
+#define PORT5_OMR_PR8_Pos                     24                                                      /*!< PORT5 OMR: PR8 Position                 */\r
+#define PORT5_OMR_PR8_Msk                     (0x01UL << PORT5_OMR_PR8_Pos)                           /*!< PORT5 OMR: PR8 Mask                     */\r
+#define PORT5_OMR_PR9_Pos                     25                                                      /*!< PORT5 OMR: PR9 Position                 */\r
+#define PORT5_OMR_PR9_Msk                     (0x01UL << PORT5_OMR_PR9_Pos)                           /*!< PORT5 OMR: PR9 Mask                     */\r
+#define PORT5_OMR_PR10_Pos                    26                                                      /*!< PORT5 OMR: PR10 Position                */\r
+#define PORT5_OMR_PR10_Msk                    (0x01UL << PORT5_OMR_PR10_Pos)                          /*!< PORT5 OMR: PR10 Mask                    */\r
+#define PORT5_OMR_PR11_Pos                    27                                                      /*!< PORT5 OMR: PR11 Position                */\r
+#define PORT5_OMR_PR11_Msk                    (0x01UL << PORT5_OMR_PR11_Pos)                          /*!< PORT5 OMR: PR11 Mask                    */\r
+#define PORT5_OMR_PR12_Pos                    28                                                      /*!< PORT5 OMR: PR12 Position                */\r
+#define PORT5_OMR_PR12_Msk                    (0x01UL << PORT5_OMR_PR12_Pos)                          /*!< PORT5 OMR: PR12 Mask                    */\r
+#define PORT5_OMR_PR13_Pos                    29                                                      /*!< PORT5 OMR: PR13 Position                */\r
+#define PORT5_OMR_PR13_Msk                    (0x01UL << PORT5_OMR_PR13_Pos)                          /*!< PORT5 OMR: PR13 Mask                    */\r
+#define PORT5_OMR_PR14_Pos                    30                                                      /*!< PORT5 OMR: PR14 Position                */\r
+#define PORT5_OMR_PR14_Msk                    (0x01UL << PORT5_OMR_PR14_Pos)                          /*!< PORT5 OMR: PR14 Mask                    */\r
+#define PORT5_OMR_PR15_Pos                    31                                                      /*!< PORT5 OMR: PR15 Position                */\r
+#define PORT5_OMR_PR15_Msk                    (0x01UL << PORT5_OMR_PR15_Pos)                          /*!< PORT5 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT5_IOCR0  -------------------------------- */\r
+#define PORT5_IOCR0_PC0_Pos                   3                                                       /*!< PORT5 IOCR0: PC0 Position               */\r
+#define PORT5_IOCR0_PC0_Msk                   (0x1fUL << PORT5_IOCR0_PC0_Pos)                         /*!< PORT5 IOCR0: PC0 Mask                   */\r
+#define PORT5_IOCR0_PC1_Pos                   11                                                      /*!< PORT5 IOCR0: PC1 Position               */\r
+#define PORT5_IOCR0_PC1_Msk                   (0x1fUL << PORT5_IOCR0_PC1_Pos)                         /*!< PORT5 IOCR0: PC1 Mask                   */\r
+#define PORT5_IOCR0_PC2_Pos                   19                                                      /*!< PORT5 IOCR0: PC2 Position               */\r
+#define PORT5_IOCR0_PC2_Msk                   (0x1fUL << PORT5_IOCR0_PC2_Pos)                         /*!< PORT5 IOCR0: PC2 Mask                   */\r
+#define PORT5_IOCR0_PC3_Pos                   27                                                      /*!< PORT5 IOCR0: PC3 Position               */\r
+#define PORT5_IOCR0_PC3_Msk                   (0x1fUL << PORT5_IOCR0_PC3_Pos)                         /*!< PORT5 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT5_IOCR4  -------------------------------- */\r
+#define PORT5_IOCR4_PC4_Pos                   3                                                       /*!< PORT5 IOCR4: PC4 Position               */\r
+#define PORT5_IOCR4_PC4_Msk                   (0x1fUL << PORT5_IOCR4_PC4_Pos)                         /*!< PORT5 IOCR4: PC4 Mask                   */\r
+#define PORT5_IOCR4_PC5_Pos                   11                                                      /*!< PORT5 IOCR4: PC5 Position               */\r
+#define PORT5_IOCR4_PC5_Msk                   (0x1fUL << PORT5_IOCR4_PC5_Pos)                         /*!< PORT5 IOCR4: PC5 Mask                   */\r
+#define PORT5_IOCR4_PC6_Pos                   19                                                      /*!< PORT5 IOCR4: PC6 Position               */\r
+#define PORT5_IOCR4_PC6_Msk                   (0x1fUL << PORT5_IOCR4_PC6_Pos)                         /*!< PORT5 IOCR4: PC6 Mask                   */\r
+#define PORT5_IOCR4_PC7_Pos                   27                                                      /*!< PORT5 IOCR4: PC7 Position               */\r
+#define PORT5_IOCR4_PC7_Msk                   (0x1fUL << PORT5_IOCR4_PC7_Pos)                         /*!< PORT5 IOCR4: PC7 Mask                   */\r
+\r
+/* ---------------------------------  PORT5_IOCR8  -------------------------------- */\r
+#define PORT5_IOCR8_PC8_Pos                   3                                                       /*!< PORT5 IOCR8: PC8 Position               */\r
+#define PORT5_IOCR8_PC8_Msk                   (0x1fUL << PORT5_IOCR8_PC8_Pos)                         /*!< PORT5 IOCR8: PC8 Mask                   */\r
+#define PORT5_IOCR8_PC9_Pos                   11                                                      /*!< PORT5 IOCR8: PC9 Position               */\r
+#define PORT5_IOCR8_PC9_Msk                   (0x1fUL << PORT5_IOCR8_PC9_Pos)                         /*!< PORT5 IOCR8: PC9 Mask                   */\r
+#define PORT5_IOCR8_PC10_Pos                  19                                                      /*!< PORT5 IOCR8: PC10 Position              */\r
+#define PORT5_IOCR8_PC10_Msk                  (0x1fUL << PORT5_IOCR8_PC10_Pos)                        /*!< PORT5 IOCR8: PC10 Mask                  */\r
+#define PORT5_IOCR8_PC11_Pos                  27                                                      /*!< PORT5 IOCR8: PC11 Position              */\r
+#define PORT5_IOCR8_PC11_Msk                  (0x1fUL << PORT5_IOCR8_PC11_Pos)                        /*!< PORT5 IOCR8: PC11 Mask                  */\r
+\r
+/* ----------------------------------  PORT5_IN  ---------------------------------- */\r
+#define PORT5_IN_P0_Pos                       0                                                       /*!< PORT5 IN: P0 Position                   */\r
+#define PORT5_IN_P0_Msk                       (0x01UL << PORT5_IN_P0_Pos)                             /*!< PORT5 IN: P0 Mask                       */\r
+#define PORT5_IN_P1_Pos                       1                                                       /*!< PORT5 IN: P1 Position                   */\r
+#define PORT5_IN_P1_Msk                       (0x01UL << PORT5_IN_P1_Pos)                             /*!< PORT5 IN: P1 Mask                       */\r
+#define PORT5_IN_P2_Pos                       2                                                       /*!< PORT5 IN: P2 Position                   */\r
+#define PORT5_IN_P2_Msk                       (0x01UL << PORT5_IN_P2_Pos)                             /*!< PORT5 IN: P2 Mask                       */\r
+#define PORT5_IN_P3_Pos                       3                                                       /*!< PORT5 IN: P3 Position                   */\r
+#define PORT5_IN_P3_Msk                       (0x01UL << PORT5_IN_P3_Pos)                             /*!< PORT5 IN: P3 Mask                       */\r
+#define PORT5_IN_P4_Pos                       4                                                       /*!< PORT5 IN: P4 Position                   */\r
+#define PORT5_IN_P4_Msk                       (0x01UL << PORT5_IN_P4_Pos)                             /*!< PORT5 IN: P4 Mask                       */\r
+#define PORT5_IN_P5_Pos                       5                                                       /*!< PORT5 IN: P5 Position                   */\r
+#define PORT5_IN_P5_Msk                       (0x01UL << PORT5_IN_P5_Pos)                             /*!< PORT5 IN: P5 Mask                       */\r
+#define PORT5_IN_P6_Pos                       6                                                       /*!< PORT5 IN: P6 Position                   */\r
+#define PORT5_IN_P6_Msk                       (0x01UL << PORT5_IN_P6_Pos)                             /*!< PORT5 IN: P6 Mask                       */\r
+#define PORT5_IN_P7_Pos                       7                                                       /*!< PORT5 IN: P7 Position                   */\r
+#define PORT5_IN_P7_Msk                       (0x01UL << PORT5_IN_P7_Pos)                             /*!< PORT5 IN: P7 Mask                       */\r
+#define PORT5_IN_P8_Pos                       8                                                       /*!< PORT5 IN: P8 Position                   */\r
+#define PORT5_IN_P8_Msk                       (0x01UL << PORT5_IN_P8_Pos)                             /*!< PORT5 IN: P8 Mask                       */\r
+#define PORT5_IN_P9_Pos                       9                                                       /*!< PORT5 IN: P9 Position                   */\r
+#define PORT5_IN_P9_Msk                       (0x01UL << PORT5_IN_P9_Pos)                             /*!< PORT5 IN: P9 Mask                       */\r
+#define PORT5_IN_P10_Pos                      10                                                      /*!< PORT5 IN: P10 Position                  */\r
+#define PORT5_IN_P10_Msk                      (0x01UL << PORT5_IN_P10_Pos)                            /*!< PORT5 IN: P10 Mask                      */\r
+#define PORT5_IN_P11_Pos                      11                                                      /*!< PORT5 IN: P11 Position                  */\r
+#define PORT5_IN_P11_Msk                      (0x01UL << PORT5_IN_P11_Pos)                            /*!< PORT5 IN: P11 Mask                      */\r
+#define PORT5_IN_P12_Pos                      12                                                      /*!< PORT5 IN: P12 Position                  */\r
+#define PORT5_IN_P12_Msk                      (0x01UL << PORT5_IN_P12_Pos)                            /*!< PORT5 IN: P12 Mask                      */\r
+#define PORT5_IN_P13_Pos                      13                                                      /*!< PORT5 IN: P13 Position                  */\r
+#define PORT5_IN_P13_Msk                      (0x01UL << PORT5_IN_P13_Pos)                            /*!< PORT5 IN: P13 Mask                      */\r
+#define PORT5_IN_P14_Pos                      14                                                      /*!< PORT5 IN: P14 Position                  */\r
+#define PORT5_IN_P14_Msk                      (0x01UL << PORT5_IN_P14_Pos)                            /*!< PORT5 IN: P14 Mask                      */\r
+#define PORT5_IN_P15_Pos                      15                                                      /*!< PORT5 IN: P15 Position                  */\r
+#define PORT5_IN_P15_Msk                      (0x01UL << PORT5_IN_P15_Pos)                            /*!< PORT5 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT5_PDR0  --------------------------------- */\r
+#define PORT5_PDR0_PD0_Pos                    0                                                       /*!< PORT5 PDR0: PD0 Position                */\r
+#define PORT5_PDR0_PD0_Msk                    (0x07UL << PORT5_PDR0_PD0_Pos)                          /*!< PORT5 PDR0: PD0 Mask                    */\r
+#define PORT5_PDR0_PD1_Pos                    4                                                       /*!< PORT5 PDR0: PD1 Position                */\r
+#define PORT5_PDR0_PD1_Msk                    (0x07UL << PORT5_PDR0_PD1_Pos)                          /*!< PORT5 PDR0: PD1 Mask                    */\r
+#define PORT5_PDR0_PD2_Pos                    8                                                       /*!< PORT5 PDR0: PD2 Position                */\r
+#define PORT5_PDR0_PD2_Msk                    (0x07UL << PORT5_PDR0_PD2_Pos)                          /*!< PORT5 PDR0: PD2 Mask                    */\r
+#define PORT5_PDR0_PD3_Pos                    12                                                      /*!< PORT5 PDR0: PD3 Position                */\r
+#define PORT5_PDR0_PD3_Msk                    (0x07UL << PORT5_PDR0_PD3_Pos)                          /*!< PORT5 PDR0: PD3 Mask                    */\r
+#define PORT5_PDR0_PD4_Pos                    16                                                      /*!< PORT5 PDR0: PD4 Position                */\r
+#define PORT5_PDR0_PD4_Msk                    (0x07UL << PORT5_PDR0_PD4_Pos)                          /*!< PORT5 PDR0: PD4 Mask                    */\r
+#define PORT5_PDR0_PD5_Pos                    20                                                      /*!< PORT5 PDR0: PD5 Position                */\r
+#define PORT5_PDR0_PD5_Msk                    (0x07UL << PORT5_PDR0_PD5_Pos)                          /*!< PORT5 PDR0: PD5 Mask                    */\r
+#define PORT5_PDR0_PD6_Pos                    24                                                      /*!< PORT5 PDR0: PD6 Position                */\r
+#define PORT5_PDR0_PD6_Msk                    (0x07UL << PORT5_PDR0_PD6_Pos)                          /*!< PORT5 PDR0: PD6 Mask                    */\r
+#define PORT5_PDR0_PD7_Pos                    28                                                      /*!< PORT5 PDR0: PD7 Position                */\r
+#define PORT5_PDR0_PD7_Msk                    (0x07UL << PORT5_PDR0_PD7_Pos)                          /*!< PORT5 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT5_PDR1  --------------------------------- */\r
+#define PORT5_PDR1_PD8_Pos                    0                                                       /*!< PORT5 PDR1: PD8 Position                */\r
+#define PORT5_PDR1_PD8_Msk                    (0x07UL << PORT5_PDR1_PD8_Pos)                          /*!< PORT5 PDR1: PD8 Mask                    */\r
+#define PORT5_PDR1_PD9_Pos                    4                                                       /*!< PORT5 PDR1: PD9 Position                */\r
+#define PORT5_PDR1_PD9_Msk                    (0x07UL << PORT5_PDR1_PD9_Pos)                          /*!< PORT5 PDR1: PD9 Mask                    */\r
+#define PORT5_PDR1_PD10_Pos                   8                                                       /*!< PORT5 PDR1: PD10 Position               */\r
+#define PORT5_PDR1_PD10_Msk                   (0x07UL << PORT5_PDR1_PD10_Pos)                         /*!< PORT5 PDR1: PD10 Mask                   */\r
+#define PORT5_PDR1_PD11_Pos                   12                                                      /*!< PORT5 PDR1: PD11 Position               */\r
+#define PORT5_PDR1_PD11_Msk                   (0x07UL << PORT5_PDR1_PD11_Pos)                         /*!< PORT5 PDR1: PD11 Mask                   */\r
+#define PORT5_PDR1_PD12_Pos                   16                                                      /*!< PORT5 PDR1: PD12 Position               */\r
+#define PORT5_PDR1_PD12_Msk                   (0x07UL << PORT5_PDR1_PD12_Pos)                         /*!< PORT5 PDR1: PD12 Mask                   */\r
+#define PORT5_PDR1_PD13_Pos                   20                                                      /*!< PORT5 PDR1: PD13 Position               */\r
+#define PORT5_PDR1_PD13_Msk                   (0x07UL << PORT5_PDR1_PD13_Pos)                         /*!< PORT5 PDR1: PD13 Mask                   */\r
+#define PORT5_PDR1_PD14_Pos                   24                                                      /*!< PORT5 PDR1: PD14 Position               */\r
+#define PORT5_PDR1_PD14_Msk                   (0x07UL << PORT5_PDR1_PD14_Pos)                         /*!< PORT5 PDR1: PD14 Mask                   */\r
+#define PORT5_PDR1_PD15_Pos                   28                                                      /*!< PORT5 PDR1: PD15 Position               */\r
+#define PORT5_PDR1_PD15_Msk                   (0x07UL << PORT5_PDR1_PD15_Pos)                         /*!< PORT5 PDR1: PD15 Mask                   */\r
+\r
+/* ---------------------------------  PORT5_PDISC  -------------------------------- */\r
+#define PORT5_PDISC_PDIS0_Pos                 0                                                       /*!< PORT5 PDISC: PDIS0 Position             */\r
+#define PORT5_PDISC_PDIS0_Msk                 (0x01UL << PORT5_PDISC_PDIS0_Pos)                       /*!< PORT5 PDISC: PDIS0 Mask                 */\r
+#define PORT5_PDISC_PDIS1_Pos                 1                                                       /*!< PORT5 PDISC: PDIS1 Position             */\r
+#define PORT5_PDISC_PDIS1_Msk                 (0x01UL << PORT5_PDISC_PDIS1_Pos)                       /*!< PORT5 PDISC: PDIS1 Mask                 */\r
+#define PORT5_PDISC_PDIS2_Pos                 2                                                       /*!< PORT5 PDISC: PDIS2 Position             */\r
+#define PORT5_PDISC_PDIS2_Msk                 (0x01UL << PORT5_PDISC_PDIS2_Pos)                       /*!< PORT5 PDISC: PDIS2 Mask                 */\r
+#define PORT5_PDISC_PDIS3_Pos                 3                                                       /*!< PORT5 PDISC: PDIS3 Position             */\r
+#define PORT5_PDISC_PDIS3_Msk                 (0x01UL << PORT5_PDISC_PDIS3_Pos)                       /*!< PORT5 PDISC: PDIS3 Mask                 */\r
+#define PORT5_PDISC_PDIS4_Pos                 4                                                       /*!< PORT5 PDISC: PDIS4 Position             */\r
+#define PORT5_PDISC_PDIS4_Msk                 (0x01UL << PORT5_PDISC_PDIS4_Pos)                       /*!< PORT5 PDISC: PDIS4 Mask                 */\r
+#define PORT5_PDISC_PDIS5_Pos                 5                                                       /*!< PORT5 PDISC: PDIS5 Position             */\r
+#define PORT5_PDISC_PDIS5_Msk                 (0x01UL << PORT5_PDISC_PDIS5_Pos)                       /*!< PORT5 PDISC: PDIS5 Mask                 */\r
+#define PORT5_PDISC_PDIS6_Pos                 6                                                       /*!< PORT5 PDISC: PDIS6 Position             */\r
+#define PORT5_PDISC_PDIS6_Msk                 (0x01UL << PORT5_PDISC_PDIS6_Pos)                       /*!< PORT5 PDISC: PDIS6 Mask                 */\r
+#define PORT5_PDISC_PDIS7_Pos                 7                                                       /*!< PORT5 PDISC: PDIS7 Position             */\r
+#define PORT5_PDISC_PDIS7_Msk                 (0x01UL << PORT5_PDISC_PDIS7_Pos)                       /*!< PORT5 PDISC: PDIS7 Mask                 */\r
+#define PORT5_PDISC_PDIS8_Pos                 8                                                       /*!< PORT5 PDISC: PDIS8 Position             */\r
+#define PORT5_PDISC_PDIS8_Msk                 (0x01UL << PORT5_PDISC_PDIS8_Pos)                       /*!< PORT5 PDISC: PDIS8 Mask                 */\r
+#define PORT5_PDISC_PDIS9_Pos                 9                                                       /*!< PORT5 PDISC: PDIS9 Position             */\r
+#define PORT5_PDISC_PDIS9_Msk                 (0x01UL << PORT5_PDISC_PDIS9_Pos)                       /*!< PORT5 PDISC: PDIS9 Mask                 */\r
+#define PORT5_PDISC_PDIS10_Pos                10                                                      /*!< PORT5 PDISC: PDIS10 Position            */\r
+#define PORT5_PDISC_PDIS10_Msk                (0x01UL << PORT5_PDISC_PDIS10_Pos)                      /*!< PORT5 PDISC: PDIS10 Mask                */\r
+#define PORT5_PDISC_PDIS11_Pos                11                                                      /*!< PORT5 PDISC: PDIS11 Position            */\r
+#define PORT5_PDISC_PDIS11_Msk                (0x01UL << PORT5_PDISC_PDIS11_Pos)                      /*!< PORT5 PDISC: PDIS11 Mask                */\r
+#define PORT5_PDISC_PDIS12_Pos                12                                                      /*!< PORT5 PDISC: PDIS12 Position            */\r
+#define PORT5_PDISC_PDIS12_Msk                (0x01UL << PORT5_PDISC_PDIS12_Pos)                      /*!< PORT5 PDISC: PDIS12 Mask                */\r
+#define PORT5_PDISC_PDIS13_Pos                13                                                      /*!< PORT5 PDISC: PDIS13 Position            */\r
+#define PORT5_PDISC_PDIS13_Msk                (0x01UL << PORT5_PDISC_PDIS13_Pos)                      /*!< PORT5 PDISC: PDIS13 Mask                */\r
+#define PORT5_PDISC_PDIS14_Pos                14                                                      /*!< PORT5 PDISC: PDIS14 Position            */\r
+#define PORT5_PDISC_PDIS14_Msk                (0x01UL << PORT5_PDISC_PDIS14_Pos)                      /*!< PORT5 PDISC: PDIS14 Mask                */\r
+#define PORT5_PDISC_PDIS15_Pos                15                                                      /*!< PORT5 PDISC: PDIS15 Position            */\r
+#define PORT5_PDISC_PDIS15_Msk                (0x01UL << PORT5_PDISC_PDIS15_Pos)                      /*!< PORT5 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT5_PPS  --------------------------------- */\r
+#define PORT5_PPS_PPS0_Pos                    0                                                       /*!< PORT5 PPS: PPS0 Position                */\r
+#define PORT5_PPS_PPS0_Msk                    (0x01UL << PORT5_PPS_PPS0_Pos)                          /*!< PORT5 PPS: PPS0 Mask                    */\r
+#define PORT5_PPS_PPS1_Pos                    1                                                       /*!< PORT5 PPS: PPS1 Position                */\r
+#define PORT5_PPS_PPS1_Msk                    (0x01UL << PORT5_PPS_PPS1_Pos)                          /*!< PORT5 PPS: PPS1 Mask                    */\r
+#define PORT5_PPS_PPS2_Pos                    2                                                       /*!< PORT5 PPS: PPS2 Position                */\r
+#define PORT5_PPS_PPS2_Msk                    (0x01UL << PORT5_PPS_PPS2_Pos)                          /*!< PORT5 PPS: PPS2 Mask                    */\r
+#define PORT5_PPS_PPS3_Pos                    3                                                       /*!< PORT5 PPS: PPS3 Position                */\r
+#define PORT5_PPS_PPS3_Msk                    (0x01UL << PORT5_PPS_PPS3_Pos)                          /*!< PORT5 PPS: PPS3 Mask                    */\r
+#define PORT5_PPS_PPS4_Pos                    4                                                       /*!< PORT5 PPS: PPS4 Position                */\r
+#define PORT5_PPS_PPS4_Msk                    (0x01UL << PORT5_PPS_PPS4_Pos)                          /*!< PORT5 PPS: PPS4 Mask                    */\r
+#define PORT5_PPS_PPS5_Pos                    5                                                       /*!< PORT5 PPS: PPS5 Position                */\r
+#define PORT5_PPS_PPS5_Msk                    (0x01UL << PORT5_PPS_PPS5_Pos)                          /*!< PORT5 PPS: PPS5 Mask                    */\r
+#define PORT5_PPS_PPS6_Pos                    6                                                       /*!< PORT5 PPS: PPS6 Position                */\r
+#define PORT5_PPS_PPS6_Msk                    (0x01UL << PORT5_PPS_PPS6_Pos)                          /*!< PORT5 PPS: PPS6 Mask                    */\r
+#define PORT5_PPS_PPS7_Pos                    7                                                       /*!< PORT5 PPS: PPS7 Position                */\r
+#define PORT5_PPS_PPS7_Msk                    (0x01UL << PORT5_PPS_PPS7_Pos)                          /*!< PORT5 PPS: PPS7 Mask                    */\r
+#define PORT5_PPS_PPS8_Pos                    8                                                       /*!< PORT5 PPS: PPS8 Position                */\r
+#define PORT5_PPS_PPS8_Msk                    (0x01UL << PORT5_PPS_PPS8_Pos)                          /*!< PORT5 PPS: PPS8 Mask                    */\r
+#define PORT5_PPS_PPS9_Pos                    9                                                       /*!< PORT5 PPS: PPS9 Position                */\r
+#define PORT5_PPS_PPS9_Msk                    (0x01UL << PORT5_PPS_PPS9_Pos)                          /*!< PORT5 PPS: PPS9 Mask                    */\r
+#define PORT5_PPS_PPS10_Pos                   10                                                      /*!< PORT5 PPS: PPS10 Position               */\r
+#define PORT5_PPS_PPS10_Msk                   (0x01UL << PORT5_PPS_PPS10_Pos)                         /*!< PORT5 PPS: PPS10 Mask                   */\r
+#define PORT5_PPS_PPS11_Pos                   11                                                      /*!< PORT5 PPS: PPS11 Position               */\r
+#define PORT5_PPS_PPS11_Msk                   (0x01UL << PORT5_PPS_PPS11_Pos)                         /*!< PORT5 PPS: PPS11 Mask                   */\r
+#define PORT5_PPS_PPS12_Pos                   12                                                      /*!< PORT5 PPS: PPS12 Position               */\r
+#define PORT5_PPS_PPS12_Msk                   (0x01UL << PORT5_PPS_PPS12_Pos)                         /*!< PORT5 PPS: PPS12 Mask                   */\r
+#define PORT5_PPS_PPS13_Pos                   13                                                      /*!< PORT5 PPS: PPS13 Position               */\r
+#define PORT5_PPS_PPS13_Msk                   (0x01UL << PORT5_PPS_PPS13_Pos)                         /*!< PORT5 PPS: PPS13 Mask                   */\r
+#define PORT5_PPS_PPS14_Pos                   14                                                      /*!< PORT5 PPS: PPS14 Position               */\r
+#define PORT5_PPS_PPS14_Msk                   (0x01UL << PORT5_PPS_PPS14_Pos)                         /*!< PORT5 PPS: PPS14 Mask                   */\r
+#define PORT5_PPS_PPS15_Pos                   15                                                      /*!< PORT5 PPS: PPS15 Position               */\r
+#define PORT5_PPS_PPS15_Msk                   (0x01UL << PORT5_PPS_PPS15_Pos)                         /*!< PORT5 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT5_HWSEL  -------------------------------- */\r
+#define PORT5_HWSEL_HW0_Pos                   0                                                       /*!< PORT5 HWSEL: HW0 Position               */\r
+#define PORT5_HWSEL_HW0_Msk                   (0x03UL << PORT5_HWSEL_HW0_Pos)                         /*!< PORT5 HWSEL: HW0 Mask                   */\r
+#define PORT5_HWSEL_HW1_Pos                   2                                                       /*!< PORT5 HWSEL: HW1 Position               */\r
+#define PORT5_HWSEL_HW1_Msk                   (0x03UL << PORT5_HWSEL_HW1_Pos)                         /*!< PORT5 HWSEL: HW1 Mask                   */\r
+#define PORT5_HWSEL_HW2_Pos                   4                                                       /*!< PORT5 HWSEL: HW2 Position               */\r
+#define PORT5_HWSEL_HW2_Msk                   (0x03UL << PORT5_HWSEL_HW2_Pos)                         /*!< PORT5 HWSEL: HW2 Mask                   */\r
+#define PORT5_HWSEL_HW3_Pos                   6                                                       /*!< PORT5 HWSEL: HW3 Position               */\r
+#define PORT5_HWSEL_HW3_Msk                   (0x03UL << PORT5_HWSEL_HW3_Pos)                         /*!< PORT5 HWSEL: HW3 Mask                   */\r
+#define PORT5_HWSEL_HW4_Pos                   8                                                       /*!< PORT5 HWSEL: HW4 Position               */\r
+#define PORT5_HWSEL_HW4_Msk                   (0x03UL << PORT5_HWSEL_HW4_Pos)                         /*!< PORT5 HWSEL: HW4 Mask                   */\r
+#define PORT5_HWSEL_HW5_Pos                   10                                                      /*!< PORT5 HWSEL: HW5 Position               */\r
+#define PORT5_HWSEL_HW5_Msk                   (0x03UL << PORT5_HWSEL_HW5_Pos)                         /*!< PORT5 HWSEL: HW5 Mask                   */\r
+#define PORT5_HWSEL_HW6_Pos                   12                                                      /*!< PORT5 HWSEL: HW6 Position               */\r
+#define PORT5_HWSEL_HW6_Msk                   (0x03UL << PORT5_HWSEL_HW6_Pos)                         /*!< PORT5 HWSEL: HW6 Mask                   */\r
+#define PORT5_HWSEL_HW7_Pos                   14                                                      /*!< PORT5 HWSEL: HW7 Position               */\r
+#define PORT5_HWSEL_HW7_Msk                   (0x03UL << PORT5_HWSEL_HW7_Pos)                         /*!< PORT5 HWSEL: HW7 Mask                   */\r
+#define PORT5_HWSEL_HW8_Pos                   16                                                      /*!< PORT5 HWSEL: HW8 Position               */\r
+#define PORT5_HWSEL_HW8_Msk                   (0x03UL << PORT5_HWSEL_HW8_Pos)                         /*!< PORT5 HWSEL: HW8 Mask                   */\r
+#define PORT5_HWSEL_HW9_Pos                   18                                                      /*!< PORT5 HWSEL: HW9 Position               */\r
+#define PORT5_HWSEL_HW9_Msk                   (0x03UL << PORT5_HWSEL_HW9_Pos)                         /*!< PORT5 HWSEL: HW9 Mask                   */\r
+#define PORT5_HWSEL_HW10_Pos                  20                                                      /*!< PORT5 HWSEL: HW10 Position              */\r
+#define PORT5_HWSEL_HW10_Msk                  (0x03UL << PORT5_HWSEL_HW10_Pos)                        /*!< PORT5 HWSEL: HW10 Mask                  */\r
+#define PORT5_HWSEL_HW11_Pos                  22                                                      /*!< PORT5 HWSEL: HW11 Position              */\r
+#define PORT5_HWSEL_HW11_Msk                  (0x03UL << PORT5_HWSEL_HW11_Pos)                        /*!< PORT5 HWSEL: HW11 Mask                  */\r
+#define PORT5_HWSEL_HW12_Pos                  24                                                      /*!< PORT5 HWSEL: HW12 Position              */\r
+#define PORT5_HWSEL_HW12_Msk                  (0x03UL << PORT5_HWSEL_HW12_Pos)                        /*!< PORT5 HWSEL: HW12 Mask                  */\r
+#define PORT5_HWSEL_HW13_Pos                  26                                                      /*!< PORT5 HWSEL: HW13 Position              */\r
+#define PORT5_HWSEL_HW13_Msk                  (0x03UL << PORT5_HWSEL_HW13_Pos)                        /*!< PORT5 HWSEL: HW13 Mask                  */\r
+#define PORT5_HWSEL_HW14_Pos                  28                                                      /*!< PORT5 HWSEL: HW14 Position              */\r
+#define PORT5_HWSEL_HW14_Msk                  (0x03UL << PORT5_HWSEL_HW14_Pos)                        /*!< PORT5 HWSEL: HW14 Mask                  */\r
+#define PORT5_HWSEL_HW15_Pos                  30                                                      /*!< PORT5 HWSEL: HW15 Position              */\r
+#define PORT5_HWSEL_HW15_Msk                  (0x03UL << PORT5_HWSEL_HW15_Pos)                        /*!< PORT5 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT6' Position & Mask         ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------  PORT6_OUT  --------------------------------- */\r
+#define PORT6_OUT_P0_Pos                      0                                                       /*!< PORT6 OUT: P0 Position                  */\r
+#define PORT6_OUT_P0_Msk                      (0x01UL << PORT6_OUT_P0_Pos)                            /*!< PORT6 OUT: P0 Mask                      */\r
+#define PORT6_OUT_P1_Pos                      1                                                       /*!< PORT6 OUT: P1 Position                  */\r
+#define PORT6_OUT_P1_Msk                      (0x01UL << PORT6_OUT_P1_Pos)                            /*!< PORT6 OUT: P1 Mask                      */\r
+#define PORT6_OUT_P2_Pos                      2                                                       /*!< PORT6 OUT: P2 Position                  */\r
+#define PORT6_OUT_P2_Msk                      (0x01UL << PORT6_OUT_P2_Pos)                            /*!< PORT6 OUT: P2 Mask                      */\r
+#define PORT6_OUT_P3_Pos                      3                                                       /*!< PORT6 OUT: P3 Position                  */\r
+#define PORT6_OUT_P3_Msk                      (0x01UL << PORT6_OUT_P3_Pos)                            /*!< PORT6 OUT: P3 Mask                      */\r
+#define PORT6_OUT_P4_Pos                      4                                                       /*!< PORT6 OUT: P4 Position                  */\r
+#define PORT6_OUT_P4_Msk                      (0x01UL << PORT6_OUT_P4_Pos)                            /*!< PORT6 OUT: P4 Mask                      */\r
+#define PORT6_OUT_P5_Pos                      5                                                       /*!< PORT6 OUT: P5 Position                  */\r
+#define PORT6_OUT_P5_Msk                      (0x01UL << PORT6_OUT_P5_Pos)                            /*!< PORT6 OUT: P5 Mask                      */\r
+#define PORT6_OUT_P6_Pos                      6                                                       /*!< PORT6 OUT: P6 Position                  */\r
+#define PORT6_OUT_P6_Msk                      (0x01UL << PORT6_OUT_P6_Pos)                            /*!< PORT6 OUT: P6 Mask                      */\r
+#define PORT6_OUT_P7_Pos                      7                                                       /*!< PORT6 OUT: P7 Position                  */\r
+#define PORT6_OUT_P7_Msk                      (0x01UL << PORT6_OUT_P7_Pos)                            /*!< PORT6 OUT: P7 Mask                      */\r
+#define PORT6_OUT_P8_Pos                      8                                                       /*!< PORT6 OUT: P8 Position                  */\r
+#define PORT6_OUT_P8_Msk                      (0x01UL << PORT6_OUT_P8_Pos)                            /*!< PORT6 OUT: P8 Mask                      */\r
+#define PORT6_OUT_P9_Pos                      9                                                       /*!< PORT6 OUT: P9 Position                  */\r
+#define PORT6_OUT_P9_Msk                      (0x01UL << PORT6_OUT_P9_Pos)                            /*!< PORT6 OUT: P9 Mask                      */\r
+#define PORT6_OUT_P10_Pos                     10                                                      /*!< PORT6 OUT: P10 Position                 */\r
+#define PORT6_OUT_P10_Msk                     (0x01UL << PORT6_OUT_P10_Pos)                           /*!< PORT6 OUT: P10 Mask                     */\r
+#define PORT6_OUT_P11_Pos                     11                                                      /*!< PORT6 OUT: P11 Position                 */\r
+#define PORT6_OUT_P11_Msk                     (0x01UL << PORT6_OUT_P11_Pos)                           /*!< PORT6 OUT: P11 Mask                     */\r
+#define PORT6_OUT_P12_Pos                     12                                                      /*!< PORT6 OUT: P12 Position                 */\r
+#define PORT6_OUT_P12_Msk                     (0x01UL << PORT6_OUT_P12_Pos)                           /*!< PORT6 OUT: P12 Mask                     */\r
+#define PORT6_OUT_P13_Pos                     13                                                      /*!< PORT6 OUT: P13 Position                 */\r
+#define PORT6_OUT_P13_Msk                     (0x01UL << PORT6_OUT_P13_Pos)                           /*!< PORT6 OUT: P13 Mask                     */\r
+#define PORT6_OUT_P14_Pos                     14                                                      /*!< PORT6 OUT: P14 Position                 */\r
+#define PORT6_OUT_P14_Msk                     (0x01UL << PORT6_OUT_P14_Pos)                           /*!< PORT6 OUT: P14 Mask                     */\r
+#define PORT6_OUT_P15_Pos                     15                                                      /*!< PORT6 OUT: P15 Position                 */\r
+#define PORT6_OUT_P15_Msk                     (0x01UL << PORT6_OUT_P15_Pos)                           /*!< PORT6 OUT: P15 Mask                     */\r
+\r
+/* ----------------------------------  PORT6_OMR  --------------------------------- */\r
+#define PORT6_OMR_PS0_Pos                     0                                                       /*!< PORT6 OMR: PS0 Position                 */\r
+#define PORT6_OMR_PS0_Msk                     (0x01UL << PORT6_OMR_PS0_Pos)                           /*!< PORT6 OMR: PS0 Mask                     */\r
+#define PORT6_OMR_PS1_Pos                     1                                                       /*!< PORT6 OMR: PS1 Position                 */\r
+#define PORT6_OMR_PS1_Msk                     (0x01UL << PORT6_OMR_PS1_Pos)                           /*!< PORT6 OMR: PS1 Mask                     */\r
+#define PORT6_OMR_PS2_Pos                     2                                                       /*!< PORT6 OMR: PS2 Position                 */\r
+#define PORT6_OMR_PS2_Msk                     (0x01UL << PORT6_OMR_PS2_Pos)                           /*!< PORT6 OMR: PS2 Mask                     */\r
+#define PORT6_OMR_PS3_Pos                     3                                                       /*!< PORT6 OMR: PS3 Position                 */\r
+#define PORT6_OMR_PS3_Msk                     (0x01UL << PORT6_OMR_PS3_Pos)                           /*!< PORT6 OMR: PS3 Mask                     */\r
+#define PORT6_OMR_PS4_Pos                     4                                                       /*!< PORT6 OMR: PS4 Position                 */\r
+#define PORT6_OMR_PS4_Msk                     (0x01UL << PORT6_OMR_PS4_Pos)                           /*!< PORT6 OMR: PS4 Mask                     */\r
+#define PORT6_OMR_PS5_Pos                     5                                                       /*!< PORT6 OMR: PS5 Position                 */\r
+#define PORT6_OMR_PS5_Msk                     (0x01UL << PORT6_OMR_PS5_Pos)                           /*!< PORT6 OMR: PS5 Mask                     */\r
+#define PORT6_OMR_PS6_Pos                     6                                                       /*!< PORT6 OMR: PS6 Position                 */\r
+#define PORT6_OMR_PS6_Msk                     (0x01UL << PORT6_OMR_PS6_Pos)                           /*!< PORT6 OMR: PS6 Mask                     */\r
+#define PORT6_OMR_PS7_Pos                     7                                                       /*!< PORT6 OMR: PS7 Position                 */\r
+#define PORT6_OMR_PS7_Msk                     (0x01UL << PORT6_OMR_PS7_Pos)                           /*!< PORT6 OMR: PS7 Mask                     */\r
+#define PORT6_OMR_PS8_Pos                     8                                                       /*!< PORT6 OMR: PS8 Position                 */\r
+#define PORT6_OMR_PS8_Msk                     (0x01UL << PORT6_OMR_PS8_Pos)                           /*!< PORT6 OMR: PS8 Mask                     */\r
+#define PORT6_OMR_PS9_Pos                     9                                                       /*!< PORT6 OMR: PS9 Position                 */\r
+#define PORT6_OMR_PS9_Msk                     (0x01UL << PORT6_OMR_PS9_Pos)                           /*!< PORT6 OMR: PS9 Mask                     */\r
+#define PORT6_OMR_PS10_Pos                    10                                                      /*!< PORT6 OMR: PS10 Position                */\r
+#define PORT6_OMR_PS10_Msk                    (0x01UL << PORT6_OMR_PS10_Pos)                          /*!< PORT6 OMR: PS10 Mask                    */\r
+#define PORT6_OMR_PS11_Pos                    11                                                      /*!< PORT6 OMR: PS11 Position                */\r
+#define PORT6_OMR_PS11_Msk                    (0x01UL << PORT6_OMR_PS11_Pos)                          /*!< PORT6 OMR: PS11 Mask                    */\r
+#define PORT6_OMR_PS12_Pos                    12                                                      /*!< PORT6 OMR: PS12 Position                */\r
+#define PORT6_OMR_PS12_Msk                    (0x01UL << PORT6_OMR_PS12_Pos)                          /*!< PORT6 OMR: PS12 Mask                    */\r
+#define PORT6_OMR_PS13_Pos                    13                                                      /*!< PORT6 OMR: PS13 Position                */\r
+#define PORT6_OMR_PS13_Msk                    (0x01UL << PORT6_OMR_PS13_Pos)                          /*!< PORT6 OMR: PS13 Mask                    */\r
+#define PORT6_OMR_PS14_Pos                    14                                                      /*!< PORT6 OMR: PS14 Position                */\r
+#define PORT6_OMR_PS14_Msk                    (0x01UL << PORT6_OMR_PS14_Pos)                          /*!< PORT6 OMR: PS14 Mask                    */\r
+#define PORT6_OMR_PS15_Pos                    15                                                      /*!< PORT6 OMR: PS15 Position                */\r
+#define PORT6_OMR_PS15_Msk                    (0x01UL << PORT6_OMR_PS15_Pos)                          /*!< PORT6 OMR: PS15 Mask                    */\r
+#define PORT6_OMR_PR0_Pos                     16                                                      /*!< PORT6 OMR: PR0 Position                 */\r
+#define PORT6_OMR_PR0_Msk                     (0x01UL << PORT6_OMR_PR0_Pos)                           /*!< PORT6 OMR: PR0 Mask                     */\r
+#define PORT6_OMR_PR1_Pos                     17                                                      /*!< PORT6 OMR: PR1 Position                 */\r
+#define PORT6_OMR_PR1_Msk                     (0x01UL << PORT6_OMR_PR1_Pos)                           /*!< PORT6 OMR: PR1 Mask                     */\r
+#define PORT6_OMR_PR2_Pos                     18                                                      /*!< PORT6 OMR: PR2 Position                 */\r
+#define PORT6_OMR_PR2_Msk                     (0x01UL << PORT6_OMR_PR2_Pos)                           /*!< PORT6 OMR: PR2 Mask                     */\r
+#define PORT6_OMR_PR3_Pos                     19                                                      /*!< PORT6 OMR: PR3 Position                 */\r
+#define PORT6_OMR_PR3_Msk                     (0x01UL << PORT6_OMR_PR3_Pos)                           /*!< PORT6 OMR: PR3 Mask                     */\r
+#define PORT6_OMR_PR4_Pos                     20                                                      /*!< PORT6 OMR: PR4 Position                 */\r
+#define PORT6_OMR_PR4_Msk                     (0x01UL << PORT6_OMR_PR4_Pos)                           /*!< PORT6 OMR: PR4 Mask                     */\r
+#define PORT6_OMR_PR5_Pos                     21                                                      /*!< PORT6 OMR: PR5 Position                 */\r
+#define PORT6_OMR_PR5_Msk                     (0x01UL << PORT6_OMR_PR5_Pos)                           /*!< PORT6 OMR: PR5 Mask                     */\r
+#define PORT6_OMR_PR6_Pos                     22                                                      /*!< PORT6 OMR: PR6 Position                 */\r
+#define PORT6_OMR_PR6_Msk                     (0x01UL << PORT6_OMR_PR6_Pos)                           /*!< PORT6 OMR: PR6 Mask                     */\r
+#define PORT6_OMR_PR7_Pos                     23                                                      /*!< PORT6 OMR: PR7 Position                 */\r
+#define PORT6_OMR_PR7_Msk                     (0x01UL << PORT6_OMR_PR7_Pos)                           /*!< PORT6 OMR: PR7 Mask                     */\r
+#define PORT6_OMR_PR8_Pos                     24                                                      /*!< PORT6 OMR: PR8 Position                 */\r
+#define PORT6_OMR_PR8_Msk                     (0x01UL << PORT6_OMR_PR8_Pos)                           /*!< PORT6 OMR: PR8 Mask                     */\r
+#define PORT6_OMR_PR9_Pos                     25                                                      /*!< PORT6 OMR: PR9 Position                 */\r
+#define PORT6_OMR_PR9_Msk                     (0x01UL << PORT6_OMR_PR9_Pos)                           /*!< PORT6 OMR: PR9 Mask                     */\r
+#define PORT6_OMR_PR10_Pos                    26                                                      /*!< PORT6 OMR: PR10 Position                */\r
+#define PORT6_OMR_PR10_Msk                    (0x01UL << PORT6_OMR_PR10_Pos)                          /*!< PORT6 OMR: PR10 Mask                    */\r
+#define PORT6_OMR_PR11_Pos                    27                                                      /*!< PORT6 OMR: PR11 Position                */\r
+#define PORT6_OMR_PR11_Msk                    (0x01UL << PORT6_OMR_PR11_Pos)                          /*!< PORT6 OMR: PR11 Mask                    */\r
+#define PORT6_OMR_PR12_Pos                    28                                                      /*!< PORT6 OMR: PR12 Position                */\r
+#define PORT6_OMR_PR12_Msk                    (0x01UL << PORT6_OMR_PR12_Pos)                          /*!< PORT6 OMR: PR12 Mask                    */\r
+#define PORT6_OMR_PR13_Pos                    29                                                      /*!< PORT6 OMR: PR13 Position                */\r
+#define PORT6_OMR_PR13_Msk                    (0x01UL << PORT6_OMR_PR13_Pos)                          /*!< PORT6 OMR: PR13 Mask                    */\r
+#define PORT6_OMR_PR14_Pos                    30                                                      /*!< PORT6 OMR: PR14 Position                */\r
+#define PORT6_OMR_PR14_Msk                    (0x01UL << PORT6_OMR_PR14_Pos)                          /*!< PORT6 OMR: PR14 Mask                    */\r
+#define PORT6_OMR_PR15_Pos                    31                                                      /*!< PORT6 OMR: PR15 Position                */\r
+#define PORT6_OMR_PR15_Msk                    (0x01UL << PORT6_OMR_PR15_Pos)                          /*!< PORT6 OMR: PR15 Mask                    */\r
+\r
+/* ---------------------------------  PORT6_IOCR0  -------------------------------- */\r
+#define PORT6_IOCR0_PC0_Pos                   3                                                       /*!< PORT6 IOCR0: PC0 Position               */\r
+#define PORT6_IOCR0_PC0_Msk                   (0x1fUL << PORT6_IOCR0_PC0_Pos)                         /*!< PORT6 IOCR0: PC0 Mask                   */\r
+#define PORT6_IOCR0_PC1_Pos                   11                                                      /*!< PORT6 IOCR0: PC1 Position               */\r
+#define PORT6_IOCR0_PC1_Msk                   (0x1fUL << PORT6_IOCR0_PC1_Pos)                         /*!< PORT6 IOCR0: PC1 Mask                   */\r
+#define PORT6_IOCR0_PC2_Pos                   19                                                      /*!< PORT6 IOCR0: PC2 Position               */\r
+#define PORT6_IOCR0_PC2_Msk                   (0x1fUL << PORT6_IOCR0_PC2_Pos)                         /*!< PORT6 IOCR0: PC2 Mask                   */\r
+#define PORT6_IOCR0_PC3_Pos                   27                                                      /*!< PORT6 IOCR0: PC3 Position               */\r
+#define PORT6_IOCR0_PC3_Msk                   (0x1fUL << PORT6_IOCR0_PC3_Pos)                         /*!< PORT6 IOCR0: PC3 Mask                   */\r
+\r
+/* ---------------------------------  PORT6_IOCR4  -------------------------------- */\r
+#define PORT6_IOCR4_PC4_Pos                   3                                                       /*!< PORT6 IOCR4: PC4 Position               */\r
+#define PORT6_IOCR4_PC4_Msk                   (0x1fUL << PORT6_IOCR4_PC4_Pos)                         /*!< PORT6 IOCR4: PC4 Mask                   */\r
+#define PORT6_IOCR4_PC5_Pos                   11                                                      /*!< PORT6 IOCR4: PC5 Position               */\r
+#define PORT6_IOCR4_PC5_Msk                   (0x1fUL << PORT6_IOCR4_PC5_Pos)                         /*!< PORT6 IOCR4: PC5 Mask                   */\r
+#define PORT6_IOCR4_PC6_Pos                   19                                                      /*!< PORT6 IOCR4: PC6 Position               */\r
+#define PORT6_IOCR4_PC6_Msk                   (0x1fUL << PORT6_IOCR4_PC6_Pos)                         /*!< PORT6 IOCR4: PC6 Mask                   */\r
+#define PORT6_IOCR4_PC7_Pos                   27                                                      /*!< PORT6 IOCR4: PC7 Position               */\r
+#define PORT6_IOCR4_PC7_Msk                   (0x1fUL << PORT6_IOCR4_PC7_Pos)                         /*!< PORT6 IOCR4: PC7 Mask                   */\r
+\r
+/* ----------------------------------  PORT6_IN  ---------------------------------- */\r
+#define PORT6_IN_P0_Pos                       0                                                       /*!< PORT6 IN: P0 Position                   */\r
+#define PORT6_IN_P0_Msk                       (0x01UL << PORT6_IN_P0_Pos)                             /*!< PORT6 IN: P0 Mask                       */\r
+#define PORT6_IN_P1_Pos                       1                                                       /*!< PORT6 IN: P1 Position                   */\r
+#define PORT6_IN_P1_Msk                       (0x01UL << PORT6_IN_P1_Pos)                             /*!< PORT6 IN: P1 Mask                       */\r
+#define PORT6_IN_P2_Pos                       2                                                       /*!< PORT6 IN: P2 Position                   */\r
+#define PORT6_IN_P2_Msk                       (0x01UL << PORT6_IN_P2_Pos)                             /*!< PORT6 IN: P2 Mask                       */\r
+#define PORT6_IN_P3_Pos                       3                                                       /*!< PORT6 IN: P3 Position                   */\r
+#define PORT6_IN_P3_Msk                       (0x01UL << PORT6_IN_P3_Pos)                             /*!< PORT6 IN: P3 Mask                       */\r
+#define PORT6_IN_P4_Pos                       4                                                       /*!< PORT6 IN: P4 Position                   */\r
+#define PORT6_IN_P4_Msk                       (0x01UL << PORT6_IN_P4_Pos)                             /*!< PORT6 IN: P4 Mask                       */\r
+#define PORT6_IN_P5_Pos                       5                                                       /*!< PORT6 IN: P5 Position                   */\r
+#define PORT6_IN_P5_Msk                       (0x01UL << PORT6_IN_P5_Pos)                             /*!< PORT6 IN: P5 Mask                       */\r
+#define PORT6_IN_P6_Pos                       6                                                       /*!< PORT6 IN: P6 Position                   */\r
+#define PORT6_IN_P6_Msk                       (0x01UL << PORT6_IN_P6_Pos)                             /*!< PORT6 IN: P6 Mask                       */\r
+#define PORT6_IN_P7_Pos                       7                                                       /*!< PORT6 IN: P7 Position                   */\r
+#define PORT6_IN_P7_Msk                       (0x01UL << PORT6_IN_P7_Pos)                             /*!< PORT6 IN: P7 Mask                       */\r
+#define PORT6_IN_P8_Pos                       8                                                       /*!< PORT6 IN: P8 Position                   */\r
+#define PORT6_IN_P8_Msk                       (0x01UL << PORT6_IN_P8_Pos)                             /*!< PORT6 IN: P8 Mask                       */\r
+#define PORT6_IN_P9_Pos                       9                                                       /*!< PORT6 IN: P9 Position                   */\r
+#define PORT6_IN_P9_Msk                       (0x01UL << PORT6_IN_P9_Pos)                             /*!< PORT6 IN: P9 Mask                       */\r
+#define PORT6_IN_P10_Pos                      10                                                      /*!< PORT6 IN: P10 Position                  */\r
+#define PORT6_IN_P10_Msk                      (0x01UL << PORT6_IN_P10_Pos)                            /*!< PORT6 IN: P10 Mask                      */\r
+#define PORT6_IN_P11_Pos                      11                                                      /*!< PORT6 IN: P11 Position                  */\r
+#define PORT6_IN_P11_Msk                      (0x01UL << PORT6_IN_P11_Pos)                            /*!< PORT6 IN: P11 Mask                      */\r
+#define PORT6_IN_P12_Pos                      12                                                      /*!< PORT6 IN: P12 Position                  */\r
+#define PORT6_IN_P12_Msk                      (0x01UL << PORT6_IN_P12_Pos)                            /*!< PORT6 IN: P12 Mask                      */\r
+#define PORT6_IN_P13_Pos                      13                                                      /*!< PORT6 IN: P13 Position                  */\r
+#define PORT6_IN_P13_Msk                      (0x01UL << PORT6_IN_P13_Pos)                            /*!< PORT6 IN: P13 Mask                      */\r
+#define PORT6_IN_P14_Pos                      14                                                      /*!< PORT6 IN: P14 Position                  */\r
+#define PORT6_IN_P14_Msk                      (0x01UL << PORT6_IN_P14_Pos)                            /*!< PORT6 IN: P14 Mask                      */\r
+#define PORT6_IN_P15_Pos                      15                                                      /*!< PORT6 IN: P15 Position                  */\r
+#define PORT6_IN_P15_Msk                      (0x01UL << PORT6_IN_P15_Pos)                            /*!< PORT6 IN: P15 Mask                      */\r
+\r
+/* ---------------------------------  PORT6_PDR0  --------------------------------- */\r
+#define PORT6_PDR0_PD0_Pos                    0                                                       /*!< PORT6 PDR0: PD0 Position                */\r
+#define PORT6_PDR0_PD0_Msk                    (0x07UL << PORT6_PDR0_PD0_Pos)                          /*!< PORT6 PDR0: PD0 Mask                    */\r
+#define PORT6_PDR0_PD1_Pos                    4                                                       /*!< PORT6 PDR0: PD1 Position                */\r
+#define PORT6_PDR0_PD1_Msk                    (0x07UL << PORT6_PDR0_PD1_Pos)                          /*!< PORT6 PDR0: PD1 Mask                    */\r
+#define PORT6_PDR0_PD2_Pos                    8                                                       /*!< PORT6 PDR0: PD2 Position                */\r
+#define PORT6_PDR0_PD2_Msk                    (0x07UL << PORT6_PDR0_PD2_Pos)                          /*!< PORT6 PDR0: PD2 Mask                    */\r
+#define PORT6_PDR0_PD3_Pos                    12                                                      /*!< PORT6 PDR0: PD3 Position                */\r
+#define PORT6_PDR0_PD3_Msk                    (0x07UL << PORT6_PDR0_PD3_Pos)                          /*!< PORT6 PDR0: PD3 Mask                    */\r
+#define PORT6_PDR0_PD4_Pos                    16                                                      /*!< PORT6 PDR0: PD4 Position                */\r
+#define PORT6_PDR0_PD4_Msk                    (0x07UL << PORT6_PDR0_PD4_Pos)                          /*!< PORT6 PDR0: PD4 Mask                    */\r
+#define PORT6_PDR0_PD5_Pos                    20                                                      /*!< PORT6 PDR0: PD5 Position                */\r
+#define PORT6_PDR0_PD5_Msk                    (0x07UL << PORT6_PDR0_PD5_Pos)                          /*!< PORT6 PDR0: PD5 Mask                    */\r
+#define PORT6_PDR0_PD6_Pos                    24                                                      /*!< PORT6 PDR0: PD6 Position                */\r
+#define PORT6_PDR0_PD6_Msk                    (0x07UL << PORT6_PDR0_PD6_Pos)                          /*!< PORT6 PDR0: PD6 Mask                    */\r
+#define PORT6_PDR0_PD7_Pos                    28                                                      /*!< PORT6 PDR0: PD7 Position                */\r
+#define PORT6_PDR0_PD7_Msk                    (0x07UL << PORT6_PDR0_PD7_Pos)                          /*!< PORT6 PDR0: PD7 Mask                    */\r
+\r
+/* ---------------------------------  PORT6_PDISC  -------------------------------- */\r
+#define PORT6_PDISC_PDIS0_Pos                 0                                                       /*!< PORT6 PDISC: PDIS0 Position             */\r
+#define PORT6_PDISC_PDIS0_Msk                 (0x01UL << PORT6_PDISC_PDIS0_Pos)                       /*!< PORT6 PDISC: PDIS0 Mask                 */\r
+#define PORT6_PDISC_PDIS1_Pos                 1                                                       /*!< PORT6 PDISC: PDIS1 Position             */\r
+#define PORT6_PDISC_PDIS1_Msk                 (0x01UL << PORT6_PDISC_PDIS1_Pos)                       /*!< PORT6 PDISC: PDIS1 Mask                 */\r
+#define PORT6_PDISC_PDIS2_Pos                 2                                                       /*!< PORT6 PDISC: PDIS2 Position             */\r
+#define PORT6_PDISC_PDIS2_Msk                 (0x01UL << PORT6_PDISC_PDIS2_Pos)                       /*!< PORT6 PDISC: PDIS2 Mask                 */\r
+#define PORT6_PDISC_PDIS3_Pos                 3                                                       /*!< PORT6 PDISC: PDIS3 Position             */\r
+#define PORT6_PDISC_PDIS3_Msk                 (0x01UL << PORT6_PDISC_PDIS3_Pos)                       /*!< PORT6 PDISC: PDIS3 Mask                 */\r
+#define PORT6_PDISC_PDIS4_Pos                 4                                                       /*!< PORT6 PDISC: PDIS4 Position             */\r
+#define PORT6_PDISC_PDIS4_Msk                 (0x01UL << PORT6_PDISC_PDIS4_Pos)                       /*!< PORT6 PDISC: PDIS4 Mask                 */\r
+#define PORT6_PDISC_PDIS5_Pos                 5                                                       /*!< PORT6 PDISC: PDIS5 Position             */\r
+#define PORT6_PDISC_PDIS5_Msk                 (0x01UL << PORT6_PDISC_PDIS5_Pos)                       /*!< PORT6 PDISC: PDIS5 Mask                 */\r
+#define PORT6_PDISC_PDIS6_Pos                 6                                                       /*!< PORT6 PDISC: PDIS6 Position             */\r
+#define PORT6_PDISC_PDIS6_Msk                 (0x01UL << PORT6_PDISC_PDIS6_Pos)                       /*!< PORT6 PDISC: PDIS6 Mask                 */\r
+#define PORT6_PDISC_PDIS7_Pos                 7                                                       /*!< PORT6 PDISC: PDIS7 Position             */\r
+#define PORT6_PDISC_PDIS7_Msk                 (0x01UL << PORT6_PDISC_PDIS7_Pos)                       /*!< PORT6 PDISC: PDIS7 Mask                 */\r
+#define PORT6_PDISC_PDIS8_Pos                 8                                                       /*!< PORT6 PDISC: PDIS8 Position             */\r
+#define PORT6_PDISC_PDIS8_Msk                 (0x01UL << PORT6_PDISC_PDIS8_Pos)                       /*!< PORT6 PDISC: PDIS8 Mask                 */\r
+#define PORT6_PDISC_PDIS9_Pos                 9                                                       /*!< PORT6 PDISC: PDIS9 Position             */\r
+#define PORT6_PDISC_PDIS9_Msk                 (0x01UL << PORT6_PDISC_PDIS9_Pos)                       /*!< PORT6 PDISC: PDIS9 Mask                 */\r
+#define PORT6_PDISC_PDIS10_Pos                10                                                      /*!< PORT6 PDISC: PDIS10 Position            */\r
+#define PORT6_PDISC_PDIS10_Msk                (0x01UL << PORT6_PDISC_PDIS10_Pos)                      /*!< PORT6 PDISC: PDIS10 Mask                */\r
+#define PORT6_PDISC_PDIS11_Pos                11                                                      /*!< PORT6 PDISC: PDIS11 Position            */\r
+#define PORT6_PDISC_PDIS11_Msk                (0x01UL << PORT6_PDISC_PDIS11_Pos)                      /*!< PORT6 PDISC: PDIS11 Mask                */\r
+#define PORT6_PDISC_PDIS12_Pos                12                                                      /*!< PORT6 PDISC: PDIS12 Position            */\r
+#define PORT6_PDISC_PDIS12_Msk                (0x01UL << PORT6_PDISC_PDIS12_Pos)                      /*!< PORT6 PDISC: PDIS12 Mask                */\r
+#define PORT6_PDISC_PDIS13_Pos                13                                                      /*!< PORT6 PDISC: PDIS13 Position            */\r
+#define PORT6_PDISC_PDIS13_Msk                (0x01UL << PORT6_PDISC_PDIS13_Pos)                      /*!< PORT6 PDISC: PDIS13 Mask                */\r
+#define PORT6_PDISC_PDIS14_Pos                14                                                      /*!< PORT6 PDISC: PDIS14 Position            */\r
+#define PORT6_PDISC_PDIS14_Msk                (0x01UL << PORT6_PDISC_PDIS14_Pos)                      /*!< PORT6 PDISC: PDIS14 Mask                */\r
+#define PORT6_PDISC_PDIS15_Pos                15                                                      /*!< PORT6 PDISC: PDIS15 Position            */\r
+#define PORT6_PDISC_PDIS15_Msk                (0x01UL << PORT6_PDISC_PDIS15_Pos)                      /*!< PORT6 PDISC: PDIS15 Mask                */\r
+\r
+/* ----------------------------------  PORT6_PPS  --------------------------------- */\r
+#define PORT6_PPS_PPS0_Pos                    0                                                       /*!< PORT6 PPS: PPS0 Position                */\r
+#define PORT6_PPS_PPS0_Msk                    (0x01UL << PORT6_PPS_PPS0_Pos)                          /*!< PORT6 PPS: PPS0 Mask                    */\r
+#define PORT6_PPS_PPS1_Pos                    1                                                       /*!< PORT6 PPS: PPS1 Position                */\r
+#define PORT6_PPS_PPS1_Msk                    (0x01UL << PORT6_PPS_PPS1_Pos)                          /*!< PORT6 PPS: PPS1 Mask                    */\r
+#define PORT6_PPS_PPS2_Pos                    2                                                       /*!< PORT6 PPS: PPS2 Position                */\r
+#define PORT6_PPS_PPS2_Msk                    (0x01UL << PORT6_PPS_PPS2_Pos)                          /*!< PORT6 PPS: PPS2 Mask                    */\r
+#define PORT6_PPS_PPS3_Pos                    3                                                       /*!< PORT6 PPS: PPS3 Position                */\r
+#define PORT6_PPS_PPS3_Msk                    (0x01UL << PORT6_PPS_PPS3_Pos)                          /*!< PORT6 PPS: PPS3 Mask                    */\r
+#define PORT6_PPS_PPS4_Pos                    4                                                       /*!< PORT6 PPS: PPS4 Position                */\r
+#define PORT6_PPS_PPS4_Msk                    (0x01UL << PORT6_PPS_PPS4_Pos)                          /*!< PORT6 PPS: PPS4 Mask                    */\r
+#define PORT6_PPS_PPS5_Pos                    5                                                       /*!< PORT6 PPS: PPS5 Position                */\r
+#define PORT6_PPS_PPS5_Msk                    (0x01UL << PORT6_PPS_PPS5_Pos)                          /*!< PORT6 PPS: PPS5 Mask                    */\r
+#define PORT6_PPS_PPS6_Pos                    6                                                       /*!< PORT6 PPS: PPS6 Position                */\r
+#define PORT6_PPS_PPS6_Msk                    (0x01UL << PORT6_PPS_PPS6_Pos)                          /*!< PORT6 PPS: PPS6 Mask                    */\r
+#define PORT6_PPS_PPS7_Pos                    7                                                       /*!< PORT6 PPS: PPS7 Position                */\r
+#define PORT6_PPS_PPS7_Msk                    (0x01UL << PORT6_PPS_PPS7_Pos)                          /*!< PORT6 PPS: PPS7 Mask                    */\r
+#define PORT6_PPS_PPS8_Pos                    8                                                       /*!< PORT6 PPS: PPS8 Position                */\r
+#define PORT6_PPS_PPS8_Msk                    (0x01UL << PORT6_PPS_PPS8_Pos)                          /*!< PORT6 PPS: PPS8 Mask                    */\r
+#define PORT6_PPS_PPS9_Pos                    9                                                       /*!< PORT6 PPS: PPS9 Position                */\r
+#define PORT6_PPS_PPS9_Msk                    (0x01UL << PORT6_PPS_PPS9_Pos)                          /*!< PORT6 PPS: PPS9 Mask                    */\r
+#define PORT6_PPS_PPS10_Pos                   10                                                      /*!< PORT6 PPS: PPS10 Position               */\r
+#define PORT6_PPS_PPS10_Msk                   (0x01UL << PORT6_PPS_PPS10_Pos)                         /*!< PORT6 PPS: PPS10 Mask                   */\r
+#define PORT6_PPS_PPS11_Pos                   11                                                      /*!< PORT6 PPS: PPS11 Position               */\r
+#define PORT6_PPS_PPS11_Msk                   (0x01UL << PORT6_PPS_PPS11_Pos)                         /*!< PORT6 PPS: PPS11 Mask                   */\r
+#define PORT6_PPS_PPS12_Pos                   12                                                      /*!< PORT6 PPS: PPS12 Position               */\r
+#define PORT6_PPS_PPS12_Msk                   (0x01UL << PORT6_PPS_PPS12_Pos)                         /*!< PORT6 PPS: PPS12 Mask                   */\r
+#define PORT6_PPS_PPS13_Pos                   13                                                      /*!< PORT6 PPS: PPS13 Position               */\r
+#define PORT6_PPS_PPS13_Msk                   (0x01UL << PORT6_PPS_PPS13_Pos)                         /*!< PORT6 PPS: PPS13 Mask                   */\r
+#define PORT6_PPS_PPS14_Pos                   14                                                      /*!< PORT6 PPS: PPS14 Position               */\r
+#define PORT6_PPS_PPS14_Msk                   (0x01UL << PORT6_PPS_PPS14_Pos)                         /*!< PORT6 PPS: PPS14 Mask                   */\r
+#define PORT6_PPS_PPS15_Pos                   15                                                      /*!< PORT6 PPS: PPS15 Position               */\r
+#define PORT6_PPS_PPS15_Msk                   (0x01UL << PORT6_PPS_PPS15_Pos)                         /*!< PORT6 PPS: PPS15 Mask                   */\r
+\r
+/* ---------------------------------  PORT6_HWSEL  -------------------------------- */\r
+#define PORT6_HWSEL_HW0_Pos                   0                                                       /*!< PORT6 HWSEL: HW0 Position               */\r
+#define PORT6_HWSEL_HW0_Msk                   (0x03UL << PORT6_HWSEL_HW0_Pos)                         /*!< PORT6 HWSEL: HW0 Mask                   */\r
+#define PORT6_HWSEL_HW1_Pos                   2                                                       /*!< PORT6 HWSEL: HW1 Position               */\r
+#define PORT6_HWSEL_HW1_Msk                   (0x03UL << PORT6_HWSEL_HW1_Pos)                         /*!< PORT6 HWSEL: HW1 Mask                   */\r
+#define PORT6_HWSEL_HW2_Pos                   4                                                       /*!< PORT6 HWSEL: HW2 Position               */\r
+#define PORT6_HWSEL_HW2_Msk                   (0x03UL << PORT6_HWSEL_HW2_Pos)                         /*!< PORT6 HWSEL: HW2 Mask                   */\r
+#define PORT6_HWSEL_HW3_Pos                   6                                                       /*!< PORT6 HWSEL: HW3 Position               */\r
+#define PORT6_HWSEL_HW3_Msk                   (0x03UL << PORT6_HWSEL_HW3_Pos)                         /*!< PORT6 HWSEL: HW3 Mask                   */\r
+#define PORT6_HWSEL_HW4_Pos                   8                                                       /*!< PORT6 HWSEL: HW4 Position               */\r
+#define PORT6_HWSEL_HW4_Msk                   (0x03UL << PORT6_HWSEL_HW4_Pos)                         /*!< PORT6 HWSEL: HW4 Mask                   */\r
+#define PORT6_HWSEL_HW5_Pos                   10                                                      /*!< PORT6 HWSEL: HW5 Position               */\r
+#define PORT6_HWSEL_HW5_Msk                   (0x03UL << PORT6_HWSEL_HW5_Pos)                         /*!< PORT6 HWSEL: HW5 Mask                   */\r
+#define PORT6_HWSEL_HW6_Pos                   12                                                      /*!< PORT6 HWSEL: HW6 Position               */\r
+#define PORT6_HWSEL_HW6_Msk                   (0x03UL << PORT6_HWSEL_HW6_Pos)                         /*!< PORT6 HWSEL: HW6 Mask                   */\r
+#define PORT6_HWSEL_HW7_Pos                   14                                                      /*!< PORT6 HWSEL: HW7 Position               */\r
+#define PORT6_HWSEL_HW7_Msk                   (0x03UL << PORT6_HWSEL_HW7_Pos)                         /*!< PORT6 HWSEL: HW7 Mask                   */\r
+#define PORT6_HWSEL_HW8_Pos                   16                                                      /*!< PORT6 HWSEL: HW8 Position               */\r
+#define PORT6_HWSEL_HW8_Msk                   (0x03UL << PORT6_HWSEL_HW8_Pos)                         /*!< PORT6 HWSEL: HW8 Mask                   */\r
+#define PORT6_HWSEL_HW9_Pos                   18                                                      /*!< PORT6 HWSEL: HW9 Position               */\r
+#define PORT6_HWSEL_HW9_Msk                   (0x03UL << PORT6_HWSEL_HW9_Pos)                         /*!< PORT6 HWSEL: HW9 Mask                   */\r
+#define PORT6_HWSEL_HW10_Pos                  20                                                      /*!< PORT6 HWSEL: HW10 Position              */\r
+#define PORT6_HWSEL_HW10_Msk                  (0x03UL << PORT6_HWSEL_HW10_Pos)                        /*!< PORT6 HWSEL: HW10 Mask                  */\r
+#define PORT6_HWSEL_HW11_Pos                  22                                                      /*!< PORT6 HWSEL: HW11 Position              */\r
+#define PORT6_HWSEL_HW11_Msk                  (0x03UL << PORT6_HWSEL_HW11_Pos)                        /*!< PORT6 HWSEL: HW11 Mask                  */\r
+#define PORT6_HWSEL_HW12_Pos                  24                                                      /*!< PORT6 HWSEL: HW12 Position              */\r
+#define PORT6_HWSEL_HW12_Msk                  (0x03UL << PORT6_HWSEL_HW12_Pos)                        /*!< PORT6 HWSEL: HW12 Mask                  */\r
+#define PORT6_HWSEL_HW13_Pos                  26                                                      /*!< PORT6 HWSEL: HW13 Position              */\r
+#define PORT6_HWSEL_HW13_Msk                  (0x03UL << PORT6_HWSEL_HW13_Pos)                        /*!< PORT6 HWSEL: HW13 Mask                  */\r
+#define PORT6_HWSEL_HW14_Pos                  28                                                      /*!< PORT6 HWSEL: HW14 Position              */\r
+#define PORT6_HWSEL_HW14_Msk                  (0x03UL << PORT6_HWSEL_HW14_Pos)                        /*!< PORT6 HWSEL: HW14 Mask                  */\r
+#define PORT6_HWSEL_HW15_Pos                  30                                                      /*!< PORT6 HWSEL: HW15 Position              */\r
+#define PORT6_HWSEL_HW15_Msk                  (0x03UL << PORT6_HWSEL_HW15_Pos)                        /*!< PORT6 HWSEL: HW15 Mask                  */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT14' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  PORT14_OUT  --------------------------------- */\r
+#define PORT14_OUT_P0_Pos                     0                                                       /*!< PORT14 OUT: P0 Position                 */\r
+#define PORT14_OUT_P0_Msk                     (0x01UL << PORT14_OUT_P0_Pos)                           /*!< PORT14 OUT: P0 Mask                     */\r
+#define PORT14_OUT_P1_Pos                     1                                                       /*!< PORT14 OUT: P1 Position                 */\r
+#define PORT14_OUT_P1_Msk                     (0x01UL << PORT14_OUT_P1_Pos)                           /*!< PORT14 OUT: P1 Mask                     */\r
+#define PORT14_OUT_P2_Pos                     2                                                       /*!< PORT14 OUT: P2 Position                 */\r
+#define PORT14_OUT_P2_Msk                     (0x01UL << PORT14_OUT_P2_Pos)                           /*!< PORT14 OUT: P2 Mask                     */\r
+#define PORT14_OUT_P3_Pos                     3                                                       /*!< PORT14 OUT: P3 Position                 */\r
+#define PORT14_OUT_P3_Msk                     (0x01UL << PORT14_OUT_P3_Pos)                           /*!< PORT14 OUT: P3 Mask                     */\r
+#define PORT14_OUT_P4_Pos                     4                                                       /*!< PORT14 OUT: P4 Position                 */\r
+#define PORT14_OUT_P4_Msk                     (0x01UL << PORT14_OUT_P4_Pos)                           /*!< PORT14 OUT: P4 Mask                     */\r
+#define PORT14_OUT_P5_Pos                     5                                                       /*!< PORT14 OUT: P5 Position                 */\r
+#define PORT14_OUT_P5_Msk                     (0x01UL << PORT14_OUT_P5_Pos)                           /*!< PORT14 OUT: P5 Mask                     */\r
+#define PORT14_OUT_P6_Pos                     6                                                       /*!< PORT14 OUT: P6 Position                 */\r
+#define PORT14_OUT_P6_Msk                     (0x01UL << PORT14_OUT_P6_Pos)                           /*!< PORT14 OUT: P6 Mask                     */\r
+#define PORT14_OUT_P7_Pos                     7                                                       /*!< PORT14 OUT: P7 Position                 */\r
+#define PORT14_OUT_P7_Msk                     (0x01UL << PORT14_OUT_P7_Pos)                           /*!< PORT14 OUT: P7 Mask                     */\r
+#define PORT14_OUT_P8_Pos                     8                                                       /*!< PORT14 OUT: P8 Position                 */\r
+#define PORT14_OUT_P8_Msk                     (0x01UL << PORT14_OUT_P8_Pos)                           /*!< PORT14 OUT: P8 Mask                     */\r
+#define PORT14_OUT_P9_Pos                     9                                                       /*!< PORT14 OUT: P9 Position                 */\r
+#define PORT14_OUT_P9_Msk                     (0x01UL << PORT14_OUT_P9_Pos)                           /*!< PORT14 OUT: P9 Mask                     */\r
+#define PORT14_OUT_P10_Pos                    10                                                      /*!< PORT14 OUT: P10 Position                */\r
+#define PORT14_OUT_P10_Msk                    (0x01UL << PORT14_OUT_P10_Pos)                          /*!< PORT14 OUT: P10 Mask                    */\r
+#define PORT14_OUT_P11_Pos                    11                                                      /*!< PORT14 OUT: P11 Position                */\r
+#define PORT14_OUT_P11_Msk                    (0x01UL << PORT14_OUT_P11_Pos)                          /*!< PORT14 OUT: P11 Mask                    */\r
+#define PORT14_OUT_P12_Pos                    12                                                      /*!< PORT14 OUT: P12 Position                */\r
+#define PORT14_OUT_P12_Msk                    (0x01UL << PORT14_OUT_P12_Pos)                          /*!< PORT14 OUT: P12 Mask                    */\r
+#define PORT14_OUT_P13_Pos                    13                                                      /*!< PORT14 OUT: P13 Position                */\r
+#define PORT14_OUT_P13_Msk                    (0x01UL << PORT14_OUT_P13_Pos)                          /*!< PORT14 OUT: P13 Mask                    */\r
+#define PORT14_OUT_P14_Pos                    14                                                      /*!< PORT14 OUT: P14 Position                */\r
+#define PORT14_OUT_P14_Msk                    (0x01UL << PORT14_OUT_P14_Pos)                          /*!< PORT14 OUT: P14 Mask                    */\r
+#define PORT14_OUT_P15_Pos                    15                                                      /*!< PORT14 OUT: P15 Position                */\r
+#define PORT14_OUT_P15_Msk                    (0x01UL << PORT14_OUT_P15_Pos)                          /*!< PORT14 OUT: P15 Mask                    */\r
+\r
+/* ---------------------------------  PORT14_OMR  --------------------------------- */\r
+#define PORT14_OMR_PS0_Pos                    0                                                       /*!< PORT14 OMR: PS0 Position                */\r
+#define PORT14_OMR_PS0_Msk                    (0x01UL << PORT14_OMR_PS0_Pos)                          /*!< PORT14 OMR: PS0 Mask                    */\r
+#define PORT14_OMR_PS1_Pos                    1                                                       /*!< PORT14 OMR: PS1 Position                */\r
+#define PORT14_OMR_PS1_Msk                    (0x01UL << PORT14_OMR_PS1_Pos)                          /*!< PORT14 OMR: PS1 Mask                    */\r
+#define PORT14_OMR_PS2_Pos                    2                                                       /*!< PORT14 OMR: PS2 Position                */\r
+#define PORT14_OMR_PS2_Msk                    (0x01UL << PORT14_OMR_PS2_Pos)                          /*!< PORT14 OMR: PS2 Mask                    */\r
+#define PORT14_OMR_PS3_Pos                    3                                                       /*!< PORT14 OMR: PS3 Position                */\r
+#define PORT14_OMR_PS3_Msk                    (0x01UL << PORT14_OMR_PS3_Pos)                          /*!< PORT14 OMR: PS3 Mask                    */\r
+#define PORT14_OMR_PS4_Pos                    4                                                       /*!< PORT14 OMR: PS4 Position                */\r
+#define PORT14_OMR_PS4_Msk                    (0x01UL << PORT14_OMR_PS4_Pos)                          /*!< PORT14 OMR: PS4 Mask                    */\r
+#define PORT14_OMR_PS5_Pos                    5                                                       /*!< PORT14 OMR: PS5 Position                */\r
+#define PORT14_OMR_PS5_Msk                    (0x01UL << PORT14_OMR_PS5_Pos)                          /*!< PORT14 OMR: PS5 Mask                    */\r
+#define PORT14_OMR_PS6_Pos                    6                                                       /*!< PORT14 OMR: PS6 Position                */\r
+#define PORT14_OMR_PS6_Msk                    (0x01UL << PORT14_OMR_PS6_Pos)                          /*!< PORT14 OMR: PS6 Mask                    */\r
+#define PORT14_OMR_PS7_Pos                    7                                                       /*!< PORT14 OMR: PS7 Position                */\r
+#define PORT14_OMR_PS7_Msk                    (0x01UL << PORT14_OMR_PS7_Pos)                          /*!< PORT14 OMR: PS7 Mask                    */\r
+#define PORT14_OMR_PS8_Pos                    8                                                       /*!< PORT14 OMR: PS8 Position                */\r
+#define PORT14_OMR_PS8_Msk                    (0x01UL << PORT14_OMR_PS8_Pos)                          /*!< PORT14 OMR: PS8 Mask                    */\r
+#define PORT14_OMR_PS9_Pos                    9                                                       /*!< PORT14 OMR: PS9 Position                */\r
+#define PORT14_OMR_PS9_Msk                    (0x01UL << PORT14_OMR_PS9_Pos)                          /*!< PORT14 OMR: PS9 Mask                    */\r
+#define PORT14_OMR_PS10_Pos                   10                                                      /*!< PORT14 OMR: PS10 Position               */\r
+#define PORT14_OMR_PS10_Msk                   (0x01UL << PORT14_OMR_PS10_Pos)                         /*!< PORT14 OMR: PS10 Mask                   */\r
+#define PORT14_OMR_PS11_Pos                   11                                                      /*!< PORT14 OMR: PS11 Position               */\r
+#define PORT14_OMR_PS11_Msk                   (0x01UL << PORT14_OMR_PS11_Pos)                         /*!< PORT14 OMR: PS11 Mask                   */\r
+#define PORT14_OMR_PS12_Pos                   12                                                      /*!< PORT14 OMR: PS12 Position               */\r
+#define PORT14_OMR_PS12_Msk                   (0x01UL << PORT14_OMR_PS12_Pos)                         /*!< PORT14 OMR: PS12 Mask                   */\r
+#define PORT14_OMR_PS13_Pos                   13                                                      /*!< PORT14 OMR: PS13 Position               */\r
+#define PORT14_OMR_PS13_Msk                   (0x01UL << PORT14_OMR_PS13_Pos)                         /*!< PORT14 OMR: PS13 Mask                   */\r
+#define PORT14_OMR_PS14_Pos                   14                                                      /*!< PORT14 OMR: PS14 Position               */\r
+#define PORT14_OMR_PS14_Msk                   (0x01UL << PORT14_OMR_PS14_Pos)                         /*!< PORT14 OMR: PS14 Mask                   */\r
+#define PORT14_OMR_PS15_Pos                   15                                                      /*!< PORT14 OMR: PS15 Position               */\r
+#define PORT14_OMR_PS15_Msk                   (0x01UL << PORT14_OMR_PS15_Pos)                         /*!< PORT14 OMR: PS15 Mask                   */\r
+#define PORT14_OMR_PR0_Pos                    16                                                      /*!< PORT14 OMR: PR0 Position                */\r
+#define PORT14_OMR_PR0_Msk                    (0x01UL << PORT14_OMR_PR0_Pos)                          /*!< PORT14 OMR: PR0 Mask                    */\r
+#define PORT14_OMR_PR1_Pos                    17                                                      /*!< PORT14 OMR: PR1 Position                */\r
+#define PORT14_OMR_PR1_Msk                    (0x01UL << PORT14_OMR_PR1_Pos)                          /*!< PORT14 OMR: PR1 Mask                    */\r
+#define PORT14_OMR_PR2_Pos                    18                                                      /*!< PORT14 OMR: PR2 Position                */\r
+#define PORT14_OMR_PR2_Msk                    (0x01UL << PORT14_OMR_PR2_Pos)                          /*!< PORT14 OMR: PR2 Mask                    */\r
+#define PORT14_OMR_PR3_Pos                    19                                                      /*!< PORT14 OMR: PR3 Position                */\r
+#define PORT14_OMR_PR3_Msk                    (0x01UL << PORT14_OMR_PR3_Pos)                          /*!< PORT14 OMR: PR3 Mask                    */\r
+#define PORT14_OMR_PR4_Pos                    20                                                      /*!< PORT14 OMR: PR4 Position                */\r
+#define PORT14_OMR_PR4_Msk                    (0x01UL << PORT14_OMR_PR4_Pos)                          /*!< PORT14 OMR: PR4 Mask                    */\r
+#define PORT14_OMR_PR5_Pos                    21                                                      /*!< PORT14 OMR: PR5 Position                */\r
+#define PORT14_OMR_PR5_Msk                    (0x01UL << PORT14_OMR_PR5_Pos)                          /*!< PORT14 OMR: PR5 Mask                    */\r
+#define PORT14_OMR_PR6_Pos                    22                                                      /*!< PORT14 OMR: PR6 Position                */\r
+#define PORT14_OMR_PR6_Msk                    (0x01UL << PORT14_OMR_PR6_Pos)                          /*!< PORT14 OMR: PR6 Mask                    */\r
+#define PORT14_OMR_PR7_Pos                    23                                                      /*!< PORT14 OMR: PR7 Position                */\r
+#define PORT14_OMR_PR7_Msk                    (0x01UL << PORT14_OMR_PR7_Pos)                          /*!< PORT14 OMR: PR7 Mask                    */\r
+#define PORT14_OMR_PR8_Pos                    24                                                      /*!< PORT14 OMR: PR8 Position                */\r
+#define PORT14_OMR_PR8_Msk                    (0x01UL << PORT14_OMR_PR8_Pos)                          /*!< PORT14 OMR: PR8 Mask                    */\r
+#define PORT14_OMR_PR9_Pos                    25                                                      /*!< PORT14 OMR: PR9 Position                */\r
+#define PORT14_OMR_PR9_Msk                    (0x01UL << PORT14_OMR_PR9_Pos)                          /*!< PORT14 OMR: PR9 Mask                    */\r
+#define PORT14_OMR_PR10_Pos                   26                                                      /*!< PORT14 OMR: PR10 Position               */\r
+#define PORT14_OMR_PR10_Msk                   (0x01UL << PORT14_OMR_PR10_Pos)                         /*!< PORT14 OMR: PR10 Mask                   */\r
+#define PORT14_OMR_PR11_Pos                   27                                                      /*!< PORT14 OMR: PR11 Position               */\r
+#define PORT14_OMR_PR11_Msk                   (0x01UL << PORT14_OMR_PR11_Pos)                         /*!< PORT14 OMR: PR11 Mask                   */\r
+#define PORT14_OMR_PR12_Pos                   28                                                      /*!< PORT14 OMR: PR12 Position               */\r
+#define PORT14_OMR_PR12_Msk                   (0x01UL << PORT14_OMR_PR12_Pos)                         /*!< PORT14 OMR: PR12 Mask                   */\r
+#define PORT14_OMR_PR13_Pos                   29                                                      /*!< PORT14 OMR: PR13 Position               */\r
+#define PORT14_OMR_PR13_Msk                   (0x01UL << PORT14_OMR_PR13_Pos)                         /*!< PORT14 OMR: PR13 Mask                   */\r
+#define PORT14_OMR_PR14_Pos                   30                                                      /*!< PORT14 OMR: PR14 Position               */\r
+#define PORT14_OMR_PR14_Msk                   (0x01UL << PORT14_OMR_PR14_Pos)                         /*!< PORT14 OMR: PR14 Mask                   */\r
+#define PORT14_OMR_PR15_Pos                   31                                                      /*!< PORT14 OMR: PR15 Position               */\r
+#define PORT14_OMR_PR15_Msk                   (0x01UL << PORT14_OMR_PR15_Pos)                         /*!< PORT14 OMR: PR15 Mask                   */\r
+\r
+/* --------------------------------  PORT14_IOCR0  -------------------------------- */\r
+#define PORT14_IOCR0_PC0_Pos                  3                                                       /*!< PORT14 IOCR0: PC0 Position              */\r
+#define PORT14_IOCR0_PC0_Msk                  (0x1fUL << PORT14_IOCR0_PC0_Pos)                        /*!< PORT14 IOCR0: PC0 Mask                  */\r
+#define PORT14_IOCR0_PC1_Pos                  11                                                      /*!< PORT14 IOCR0: PC1 Position              */\r
+#define PORT14_IOCR0_PC1_Msk                  (0x1fUL << PORT14_IOCR0_PC1_Pos)                        /*!< PORT14 IOCR0: PC1 Mask                  */\r
+#define PORT14_IOCR0_PC2_Pos                  19                                                      /*!< PORT14 IOCR0: PC2 Position              */\r
+#define PORT14_IOCR0_PC2_Msk                  (0x1fUL << PORT14_IOCR0_PC2_Pos)                        /*!< PORT14 IOCR0: PC2 Mask                  */\r
+#define PORT14_IOCR0_PC3_Pos                  27                                                      /*!< PORT14 IOCR0: PC3 Position              */\r
+#define PORT14_IOCR0_PC3_Msk                  (0x1fUL << PORT14_IOCR0_PC3_Pos)                        /*!< PORT14 IOCR0: PC3 Mask                  */\r
+\r
+/* --------------------------------  PORT14_IOCR4  -------------------------------- */\r
+#define PORT14_IOCR4_PC4_Pos                  3                                                       /*!< PORT14 IOCR4: PC4 Position              */\r
+#define PORT14_IOCR4_PC4_Msk                  (0x1fUL << PORT14_IOCR4_PC4_Pos)                        /*!< PORT14 IOCR4: PC4 Mask                  */\r
+#define PORT14_IOCR4_PC5_Pos                  11                                                      /*!< PORT14 IOCR4: PC5 Position              */\r
+#define PORT14_IOCR4_PC5_Msk                  (0x1fUL << PORT14_IOCR4_PC5_Pos)                        /*!< PORT14 IOCR4: PC5 Mask                  */\r
+#define PORT14_IOCR4_PC6_Pos                  19                                                      /*!< PORT14 IOCR4: PC6 Position              */\r
+#define PORT14_IOCR4_PC6_Msk                  (0x1fUL << PORT14_IOCR4_PC6_Pos)                        /*!< PORT14 IOCR4: PC6 Mask                  */\r
+#define PORT14_IOCR4_PC7_Pos                  27                                                      /*!< PORT14 IOCR4: PC7 Position              */\r
+#define PORT14_IOCR4_PC7_Msk                  (0x1fUL << PORT14_IOCR4_PC7_Pos)                        /*!< PORT14 IOCR4: PC7 Mask                  */\r
+\r
+/* --------------------------------  PORT14_IOCR8  -------------------------------- */\r
+#define PORT14_IOCR8_PC8_Pos                  3                                                       /*!< PORT14 IOCR8: PC8 Position              */\r
+#define PORT14_IOCR8_PC8_Msk                  (0x1fUL << PORT14_IOCR8_PC8_Pos)                        /*!< PORT14 IOCR8: PC8 Mask                  */\r
+#define PORT14_IOCR8_PC9_Pos                  11                                                      /*!< PORT14 IOCR8: PC9 Position              */\r
+#define PORT14_IOCR8_PC9_Msk                  (0x1fUL << PORT14_IOCR8_PC9_Pos)                        /*!< PORT14 IOCR8: PC9 Mask                  */\r
+#define PORT14_IOCR8_PC10_Pos                 19                                                      /*!< PORT14 IOCR8: PC10 Position             */\r
+#define PORT14_IOCR8_PC10_Msk                 (0x1fUL << PORT14_IOCR8_PC10_Pos)                       /*!< PORT14 IOCR8: PC10 Mask                 */\r
+#define PORT14_IOCR8_PC11_Pos                 27                                                      /*!< PORT14 IOCR8: PC11 Position             */\r
+#define PORT14_IOCR8_PC11_Msk                 (0x1fUL << PORT14_IOCR8_PC11_Pos)                       /*!< PORT14 IOCR8: PC11 Mask                 */\r
+\r
+/* --------------------------------  PORT14_IOCR12  ------------------------------- */\r
+#define PORT14_IOCR12_PC12_Pos                3                                                       /*!< PORT14 IOCR12: PC12 Position            */\r
+#define PORT14_IOCR12_PC12_Msk                (0x1fUL << PORT14_IOCR12_PC12_Pos)                      /*!< PORT14 IOCR12: PC12 Mask                */\r
+#define PORT14_IOCR12_PC13_Pos                11                                                      /*!< PORT14 IOCR12: PC13 Position            */\r
+#define PORT14_IOCR12_PC13_Msk                (0x1fUL << PORT14_IOCR12_PC13_Pos)                      /*!< PORT14 IOCR12: PC13 Mask                */\r
+#define PORT14_IOCR12_PC14_Pos                19                                                      /*!< PORT14 IOCR12: PC14 Position            */\r
+#define PORT14_IOCR12_PC14_Msk                (0x1fUL << PORT14_IOCR12_PC14_Pos)                      /*!< PORT14 IOCR12: PC14 Mask                */\r
+#define PORT14_IOCR12_PC15_Pos                27                                                      /*!< PORT14 IOCR12: PC15 Position            */\r
+#define PORT14_IOCR12_PC15_Msk                (0x1fUL << PORT14_IOCR12_PC15_Pos)                      /*!< PORT14 IOCR12: PC15 Mask                */\r
+\r
+/* ----------------------------------  PORT14_IN  --------------------------------- */\r
+#define PORT14_IN_P0_Pos                      0                                                       /*!< PORT14 IN: P0 Position                  */\r
+#define PORT14_IN_P0_Msk                      (0x01UL << PORT14_IN_P0_Pos)                            /*!< PORT14 IN: P0 Mask                      */\r
+#define PORT14_IN_P1_Pos                      1                                                       /*!< PORT14 IN: P1 Position                  */\r
+#define PORT14_IN_P1_Msk                      (0x01UL << PORT14_IN_P1_Pos)                            /*!< PORT14 IN: P1 Mask                      */\r
+#define PORT14_IN_P2_Pos                      2                                                       /*!< PORT14 IN: P2 Position                  */\r
+#define PORT14_IN_P2_Msk                      (0x01UL << PORT14_IN_P2_Pos)                            /*!< PORT14 IN: P2 Mask                      */\r
+#define PORT14_IN_P3_Pos                      3                                                       /*!< PORT14 IN: P3 Position                  */\r
+#define PORT14_IN_P3_Msk                      (0x01UL << PORT14_IN_P3_Pos)                            /*!< PORT14 IN: P3 Mask                      */\r
+#define PORT14_IN_P4_Pos                      4                                                       /*!< PORT14 IN: P4 Position                  */\r
+#define PORT14_IN_P4_Msk                      (0x01UL << PORT14_IN_P4_Pos)                            /*!< PORT14 IN: P4 Mask                      */\r
+#define PORT14_IN_P5_Pos                      5                                                       /*!< PORT14 IN: P5 Position                  */\r
+#define PORT14_IN_P5_Msk                      (0x01UL << PORT14_IN_P5_Pos)                            /*!< PORT14 IN: P5 Mask                      */\r
+#define PORT14_IN_P6_Pos                      6                                                       /*!< PORT14 IN: P6 Position                  */\r
+#define PORT14_IN_P6_Msk                      (0x01UL << PORT14_IN_P6_Pos)                            /*!< PORT14 IN: P6 Mask                      */\r
+#define PORT14_IN_P7_Pos                      7                                                       /*!< PORT14 IN: P7 Position                  */\r
+#define PORT14_IN_P7_Msk                      (0x01UL << PORT14_IN_P7_Pos)                            /*!< PORT14 IN: P7 Mask                      */\r
+#define PORT14_IN_P8_Pos                      8                                                       /*!< PORT14 IN: P8 Position                  */\r
+#define PORT14_IN_P8_Msk                      (0x01UL << PORT14_IN_P8_Pos)                            /*!< PORT14 IN: P8 Mask                      */\r
+#define PORT14_IN_P9_Pos                      9                                                       /*!< PORT14 IN: P9 Position                  */\r
+#define PORT14_IN_P9_Msk                      (0x01UL << PORT14_IN_P9_Pos)                            /*!< PORT14 IN: P9 Mask                      */\r
+#define PORT14_IN_P10_Pos                     10                                                      /*!< PORT14 IN: P10 Position                 */\r
+#define PORT14_IN_P10_Msk                     (0x01UL << PORT14_IN_P10_Pos)                           /*!< PORT14 IN: P10 Mask                     */\r
+#define PORT14_IN_P11_Pos                     11                                                      /*!< PORT14 IN: P11 Position                 */\r
+#define PORT14_IN_P11_Msk                     (0x01UL << PORT14_IN_P11_Pos)                           /*!< PORT14 IN: P11 Mask                     */\r
+#define PORT14_IN_P12_Pos                     12                                                      /*!< PORT14 IN: P12 Position                 */\r
+#define PORT14_IN_P12_Msk                     (0x01UL << PORT14_IN_P12_Pos)                           /*!< PORT14 IN: P12 Mask                     */\r
+#define PORT14_IN_P13_Pos                     13                                                      /*!< PORT14 IN: P13 Position                 */\r
+#define PORT14_IN_P13_Msk                     (0x01UL << PORT14_IN_P13_Pos)                           /*!< PORT14 IN: P13 Mask                     */\r
+#define PORT14_IN_P14_Pos                     14                                                      /*!< PORT14 IN: P14 Position                 */\r
+#define PORT14_IN_P14_Msk                     (0x01UL << PORT14_IN_P14_Pos)                           /*!< PORT14 IN: P14 Mask                     */\r
+#define PORT14_IN_P15_Pos                     15                                                      /*!< PORT14 IN: P15 Position                 */\r
+#define PORT14_IN_P15_Msk                     (0x01UL << PORT14_IN_P15_Pos)                           /*!< PORT14 IN: P15 Mask                     */\r
+\r
+/* --------------------------------  PORT14_PDISC  -------------------------------- */\r
+#define PORT14_PDISC_PDIS0_Pos                0                                                       /*!< PORT14 PDISC: PDIS0 Position            */\r
+#define PORT14_PDISC_PDIS0_Msk                (0x01UL << PORT14_PDISC_PDIS0_Pos)                      /*!< PORT14 PDISC: PDIS0 Mask                */\r
+#define PORT14_PDISC_PDIS1_Pos                1                                                       /*!< PORT14 PDISC: PDIS1 Position            */\r
+#define PORT14_PDISC_PDIS1_Msk                (0x01UL << PORT14_PDISC_PDIS1_Pos)                      /*!< PORT14 PDISC: PDIS1 Mask                */\r
+#define PORT14_PDISC_PDIS2_Pos                2                                                       /*!< PORT14 PDISC: PDIS2 Position            */\r
+#define PORT14_PDISC_PDIS2_Msk                (0x01UL << PORT14_PDISC_PDIS2_Pos)                      /*!< PORT14 PDISC: PDIS2 Mask                */\r
+#define PORT14_PDISC_PDIS3_Pos                3                                                       /*!< PORT14 PDISC: PDIS3 Position            */\r
+#define PORT14_PDISC_PDIS3_Msk                (0x01UL << PORT14_PDISC_PDIS3_Pos)                      /*!< PORT14 PDISC: PDIS3 Mask                */\r
+#define PORT14_PDISC_PDIS4_Pos                4                                                       /*!< PORT14 PDISC: PDIS4 Position            */\r
+#define PORT14_PDISC_PDIS4_Msk                (0x01UL << PORT14_PDISC_PDIS4_Pos)                      /*!< PORT14 PDISC: PDIS4 Mask                */\r
+#define PORT14_PDISC_PDIS5_Pos                5                                                       /*!< PORT14 PDISC: PDIS5 Position            */\r
+#define PORT14_PDISC_PDIS5_Msk                (0x01UL << PORT14_PDISC_PDIS5_Pos)                      /*!< PORT14 PDISC: PDIS5 Mask                */\r
+#define PORT14_PDISC_PDIS6_Pos                6                                                       /*!< PORT14 PDISC: PDIS6 Position            */\r
+#define PORT14_PDISC_PDIS6_Msk                (0x01UL << PORT14_PDISC_PDIS6_Pos)                      /*!< PORT14 PDISC: PDIS6 Mask                */\r
+#define PORT14_PDISC_PDIS7_Pos                7                                                       /*!< PORT14 PDISC: PDIS7 Position            */\r
+#define PORT14_PDISC_PDIS7_Msk                (0x01UL << PORT14_PDISC_PDIS7_Pos)                      /*!< PORT14 PDISC: PDIS7 Mask                */\r
+#define PORT14_PDISC_PDIS8_Pos                8                                                       /*!< PORT14 PDISC: PDIS8 Position            */\r
+#define PORT14_PDISC_PDIS8_Msk                (0x01UL << PORT14_PDISC_PDIS8_Pos)                      /*!< PORT14 PDISC: PDIS8 Mask                */\r
+#define PORT14_PDISC_PDIS9_Pos                9                                                       /*!< PORT14 PDISC: PDIS9 Position            */\r
+#define PORT14_PDISC_PDIS9_Msk                (0x01UL << PORT14_PDISC_PDIS9_Pos)                      /*!< PORT14 PDISC: PDIS9 Mask                */\r
+#define PORT14_PDISC_PDIS12_Pos               12                                                      /*!< PORT14 PDISC: PDIS12 Position           */\r
+#define PORT14_PDISC_PDIS12_Msk               (0x01UL << PORT14_PDISC_PDIS12_Pos)                     /*!< PORT14 PDISC: PDIS12 Mask               */\r
+#define PORT14_PDISC_PDIS13_Pos               13                                                      /*!< PORT14 PDISC: PDIS13 Position           */\r
+#define PORT14_PDISC_PDIS13_Msk               (0x01UL << PORT14_PDISC_PDIS13_Pos)                     /*!< PORT14 PDISC: PDIS13 Mask               */\r
+#define PORT14_PDISC_PDIS14_Pos               14                                                      /*!< PORT14 PDISC: PDIS14 Position           */\r
+#define PORT14_PDISC_PDIS14_Msk               (0x01UL << PORT14_PDISC_PDIS14_Pos)                     /*!< PORT14 PDISC: PDIS14 Mask               */\r
+#define PORT14_PDISC_PDIS15_Pos               15                                                      /*!< PORT14 PDISC: PDIS15 Position           */\r
+#define PORT14_PDISC_PDIS15_Msk               (0x01UL << PORT14_PDISC_PDIS15_Pos)                     /*!< PORT14 PDISC: PDIS15 Mask               */\r
+\r
+/* ---------------------------------  PORT14_PPS  --------------------------------- */\r
+#define PORT14_PPS_PPS0_Pos                   0                                                       /*!< PORT14 PPS: PPS0 Position               */\r
+#define PORT14_PPS_PPS0_Msk                   (0x01UL << PORT14_PPS_PPS0_Pos)                         /*!< PORT14 PPS: PPS0 Mask                   */\r
+#define PORT14_PPS_PPS1_Pos                   1                                                       /*!< PORT14 PPS: PPS1 Position               */\r
+#define PORT14_PPS_PPS1_Msk                   (0x01UL << PORT14_PPS_PPS1_Pos)                         /*!< PORT14 PPS: PPS1 Mask                   */\r
+#define PORT14_PPS_PPS2_Pos                   2                                                       /*!< PORT14 PPS: PPS2 Position               */\r
+#define PORT14_PPS_PPS2_Msk                   (0x01UL << PORT14_PPS_PPS2_Pos)                         /*!< PORT14 PPS: PPS2 Mask                   */\r
+#define PORT14_PPS_PPS3_Pos                   3                                                       /*!< PORT14 PPS: PPS3 Position               */\r
+#define PORT14_PPS_PPS3_Msk                   (0x01UL << PORT14_PPS_PPS3_Pos)                         /*!< PORT14 PPS: PPS3 Mask                   */\r
+#define PORT14_PPS_PPS4_Pos                   4                                                       /*!< PORT14 PPS: PPS4 Position               */\r
+#define PORT14_PPS_PPS4_Msk                   (0x01UL << PORT14_PPS_PPS4_Pos)                         /*!< PORT14 PPS: PPS4 Mask                   */\r
+#define PORT14_PPS_PPS5_Pos                   5                                                       /*!< PORT14 PPS: PPS5 Position               */\r
+#define PORT14_PPS_PPS5_Msk                   (0x01UL << PORT14_PPS_PPS5_Pos)                         /*!< PORT14 PPS: PPS5 Mask                   */\r
+#define PORT14_PPS_PPS6_Pos                   6                                                       /*!< PORT14 PPS: PPS6 Position               */\r
+#define PORT14_PPS_PPS6_Msk                   (0x01UL << PORT14_PPS_PPS6_Pos)                         /*!< PORT14 PPS: PPS6 Mask                   */\r
+#define PORT14_PPS_PPS7_Pos                   7                                                       /*!< PORT14 PPS: PPS7 Position               */\r
+#define PORT14_PPS_PPS7_Msk                   (0x01UL << PORT14_PPS_PPS7_Pos)                         /*!< PORT14 PPS: PPS7 Mask                   */\r
+#define PORT14_PPS_PPS8_Pos                   8                                                       /*!< PORT14 PPS: PPS8 Position               */\r
+#define PORT14_PPS_PPS8_Msk                   (0x01UL << PORT14_PPS_PPS8_Pos)                         /*!< PORT14 PPS: PPS8 Mask                   */\r
+#define PORT14_PPS_PPS9_Pos                   9                                                       /*!< PORT14 PPS: PPS9 Position               */\r
+#define PORT14_PPS_PPS9_Msk                   (0x01UL << PORT14_PPS_PPS9_Pos)                         /*!< PORT14 PPS: PPS9 Mask                   */\r
+#define PORT14_PPS_PPS10_Pos                  10                                                      /*!< PORT14 PPS: PPS10 Position              */\r
+#define PORT14_PPS_PPS10_Msk                  (0x01UL << PORT14_PPS_PPS10_Pos)                        /*!< PORT14 PPS: PPS10 Mask                  */\r
+#define PORT14_PPS_PPS11_Pos                  11                                                      /*!< PORT14 PPS: PPS11 Position              */\r
+#define PORT14_PPS_PPS11_Msk                  (0x01UL << PORT14_PPS_PPS11_Pos)                        /*!< PORT14 PPS: PPS11 Mask                  */\r
+#define PORT14_PPS_PPS12_Pos                  12                                                      /*!< PORT14 PPS: PPS12 Position              */\r
+#define PORT14_PPS_PPS12_Msk                  (0x01UL << PORT14_PPS_PPS12_Pos)                        /*!< PORT14 PPS: PPS12 Mask                  */\r
+#define PORT14_PPS_PPS13_Pos                  13                                                      /*!< PORT14 PPS: PPS13 Position              */\r
+#define PORT14_PPS_PPS13_Msk                  (0x01UL << PORT14_PPS_PPS13_Pos)                        /*!< PORT14 PPS: PPS13 Mask                  */\r
+#define PORT14_PPS_PPS14_Pos                  14                                                      /*!< PORT14 PPS: PPS14 Position              */\r
+#define PORT14_PPS_PPS14_Msk                  (0x01UL << PORT14_PPS_PPS14_Pos)                        /*!< PORT14 PPS: PPS14 Mask                  */\r
+#define PORT14_PPS_PPS15_Pos                  15                                                      /*!< PORT14 PPS: PPS15 Position              */\r
+#define PORT14_PPS_PPS15_Msk                  (0x01UL << PORT14_PPS_PPS15_Pos)                        /*!< PORT14 PPS: PPS15 Mask                  */\r
+\r
+/* --------------------------------  PORT14_HWSEL  -------------------------------- */\r
+#define PORT14_HWSEL_HW0_Pos                  0                                                       /*!< PORT14 HWSEL: HW0 Position              */\r
+#define PORT14_HWSEL_HW0_Msk                  (0x03UL << PORT14_HWSEL_HW0_Pos)                        /*!< PORT14 HWSEL: HW0 Mask                  */\r
+#define PORT14_HWSEL_HW1_Pos                  2                                                       /*!< PORT14 HWSEL: HW1 Position              */\r
+#define PORT14_HWSEL_HW1_Msk                  (0x03UL << PORT14_HWSEL_HW1_Pos)                        /*!< PORT14 HWSEL: HW1 Mask                  */\r
+#define PORT14_HWSEL_HW2_Pos                  4                                                       /*!< PORT14 HWSEL: HW2 Position              */\r
+#define PORT14_HWSEL_HW2_Msk                  (0x03UL << PORT14_HWSEL_HW2_Pos)                        /*!< PORT14 HWSEL: HW2 Mask                  */\r
+#define PORT14_HWSEL_HW3_Pos                  6                                                       /*!< PORT14 HWSEL: HW3 Position              */\r
+#define PORT14_HWSEL_HW3_Msk                  (0x03UL << PORT14_HWSEL_HW3_Pos)                        /*!< PORT14 HWSEL: HW3 Mask                  */\r
+#define PORT14_HWSEL_HW4_Pos                  8                                                       /*!< PORT14 HWSEL: HW4 Position              */\r
+#define PORT14_HWSEL_HW4_Msk                  (0x03UL << PORT14_HWSEL_HW4_Pos)                        /*!< PORT14 HWSEL: HW4 Mask                  */\r
+#define PORT14_HWSEL_HW5_Pos                  10                                                      /*!< PORT14 HWSEL: HW5 Position              */\r
+#define PORT14_HWSEL_HW5_Msk                  (0x03UL << PORT14_HWSEL_HW5_Pos)                        /*!< PORT14 HWSEL: HW5 Mask                  */\r
+#define PORT14_HWSEL_HW6_Pos                  12                                                      /*!< PORT14 HWSEL: HW6 Position              */\r
+#define PORT14_HWSEL_HW6_Msk                  (0x03UL << PORT14_HWSEL_HW6_Pos)                        /*!< PORT14 HWSEL: HW6 Mask                  */\r
+#define PORT14_HWSEL_HW7_Pos                  14                                                      /*!< PORT14 HWSEL: HW7 Position              */\r
+#define PORT14_HWSEL_HW7_Msk                  (0x03UL << PORT14_HWSEL_HW7_Pos)                        /*!< PORT14 HWSEL: HW7 Mask                  */\r
+#define PORT14_HWSEL_HW8_Pos                  16                                                      /*!< PORT14 HWSEL: HW8 Position              */\r
+#define PORT14_HWSEL_HW8_Msk                  (0x03UL << PORT14_HWSEL_HW8_Pos)                        /*!< PORT14 HWSEL: HW8 Mask                  */\r
+#define PORT14_HWSEL_HW9_Pos                  18                                                      /*!< PORT14 HWSEL: HW9 Position              */\r
+#define PORT14_HWSEL_HW9_Msk                  (0x03UL << PORT14_HWSEL_HW9_Pos)                        /*!< PORT14 HWSEL: HW9 Mask                  */\r
+#define PORT14_HWSEL_HW10_Pos                 20                                                      /*!< PORT14 HWSEL: HW10 Position             */\r
+#define PORT14_HWSEL_HW10_Msk                 (0x03UL << PORT14_HWSEL_HW10_Pos)                       /*!< PORT14 HWSEL: HW10 Mask                 */\r
+#define PORT14_HWSEL_HW11_Pos                 22                                                      /*!< PORT14 HWSEL: HW11 Position             */\r
+#define PORT14_HWSEL_HW11_Msk                 (0x03UL << PORT14_HWSEL_HW11_Pos)                       /*!< PORT14 HWSEL: HW11 Mask                 */\r
+#define PORT14_HWSEL_HW12_Pos                 24                                                      /*!< PORT14 HWSEL: HW12 Position             */\r
+#define PORT14_HWSEL_HW12_Msk                 (0x03UL << PORT14_HWSEL_HW12_Pos)                       /*!< PORT14 HWSEL: HW12 Mask                 */\r
+#define PORT14_HWSEL_HW13_Pos                 26                                                      /*!< PORT14 HWSEL: HW13 Position             */\r
+#define PORT14_HWSEL_HW13_Msk                 (0x03UL << PORT14_HWSEL_HW13_Pos)                       /*!< PORT14 HWSEL: HW13 Mask                 */\r
+#define PORT14_HWSEL_HW14_Pos                 28                                                      /*!< PORT14 HWSEL: HW14 Position             */\r
+#define PORT14_HWSEL_HW14_Msk                 (0x03UL << PORT14_HWSEL_HW14_Pos)                       /*!< PORT14 HWSEL: HW14 Mask                 */\r
+#define PORT14_HWSEL_HW15_Pos                 30                                                      /*!< PORT14 HWSEL: HW15 Position             */\r
+#define PORT14_HWSEL_HW15_Msk                 (0x03UL << PORT14_HWSEL_HW15_Pos)                       /*!< PORT14 HWSEL: HW15 Mask                 */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================         struct 'PORT15' Position & Mask        ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------  PORT15_OUT  --------------------------------- */\r
+#define PORT15_OUT_P0_Pos                     0                                                       /*!< PORT15 OUT: P0 Position                 */\r
+#define PORT15_OUT_P0_Msk                     (0x01UL << PORT15_OUT_P0_Pos)                           /*!< PORT15 OUT: P0 Mask                     */\r
+#define PORT15_OUT_P1_Pos                     1                                                       /*!< PORT15 OUT: P1 Position                 */\r
+#define PORT15_OUT_P1_Msk                     (0x01UL << PORT15_OUT_P1_Pos)                           /*!< PORT15 OUT: P1 Mask                     */\r
+#define PORT15_OUT_P2_Pos                     2                                                       /*!< PORT15 OUT: P2 Position                 */\r
+#define PORT15_OUT_P2_Msk                     (0x01UL << PORT15_OUT_P2_Pos)                           /*!< PORT15 OUT: P2 Mask                     */\r
+#define PORT15_OUT_P3_Pos                     3                                                       /*!< PORT15 OUT: P3 Position                 */\r
+#define PORT15_OUT_P3_Msk                     (0x01UL << PORT15_OUT_P3_Pos)                           /*!< PORT15 OUT: P3 Mask                     */\r
+#define PORT15_OUT_P4_Pos                     4                                                       /*!< PORT15 OUT: P4 Position                 */\r
+#define PORT15_OUT_P4_Msk                     (0x01UL << PORT15_OUT_P4_Pos)                           /*!< PORT15 OUT: P4 Mask                     */\r
+#define PORT15_OUT_P5_Pos                     5                                                       /*!< PORT15 OUT: P5 Position                 */\r
+#define PORT15_OUT_P5_Msk                     (0x01UL << PORT15_OUT_P5_Pos)                           /*!< PORT15 OUT: P5 Mask                     */\r
+#define PORT15_OUT_P6_Pos                     6                                                       /*!< PORT15 OUT: P6 Position                 */\r
+#define PORT15_OUT_P6_Msk                     (0x01UL << PORT15_OUT_P6_Pos)                           /*!< PORT15 OUT: P6 Mask                     */\r
+#define PORT15_OUT_P7_Pos                     7                                                       /*!< PORT15 OUT: P7 Position                 */\r
+#define PORT15_OUT_P7_Msk                     (0x01UL << PORT15_OUT_P7_Pos)                           /*!< PORT15 OUT: P7 Mask                     */\r
+#define PORT15_OUT_P8_Pos                     8                                                       /*!< PORT15 OUT: P8 Position                 */\r
+#define PORT15_OUT_P8_Msk                     (0x01UL << PORT15_OUT_P8_Pos)                           /*!< PORT15 OUT: P8 Mask                     */\r
+#define PORT15_OUT_P9_Pos                     9                                                       /*!< PORT15 OUT: P9 Position                 */\r
+#define PORT15_OUT_P9_Msk                     (0x01UL << PORT15_OUT_P9_Pos)                           /*!< PORT15 OUT: P9 Mask                     */\r
+#define PORT15_OUT_P10_Pos                    10                                                      /*!< PORT15 OUT: P10 Position                */\r
+#define PORT15_OUT_P10_Msk                    (0x01UL << PORT15_OUT_P10_Pos)                          /*!< PORT15 OUT: P10 Mask                    */\r
+#define PORT15_OUT_P11_Pos                    11                                                      /*!< PORT15 OUT: P11 Position                */\r
+#define PORT15_OUT_P11_Msk                    (0x01UL << PORT15_OUT_P11_Pos)                          /*!< PORT15 OUT: P11 Mask                    */\r
+#define PORT15_OUT_P12_Pos                    12                                                      /*!< PORT15 OUT: P12 Position                */\r
+#define PORT15_OUT_P12_Msk                    (0x01UL << PORT15_OUT_P12_Pos)                          /*!< PORT15 OUT: P12 Mask                    */\r
+#define PORT15_OUT_P13_Pos                    13                                                      /*!< PORT15 OUT: P13 Position                */\r
+#define PORT15_OUT_P13_Msk                    (0x01UL << PORT15_OUT_P13_Pos)                          /*!< PORT15 OUT: P13 Mask                    */\r
+#define PORT15_OUT_P14_Pos                    14                                                      /*!< PORT15 OUT: P14 Position                */\r
+#define PORT15_OUT_P14_Msk                    (0x01UL << PORT15_OUT_P14_Pos)                          /*!< PORT15 OUT: P14 Mask                    */\r
+#define PORT15_OUT_P15_Pos                    15                                                      /*!< PORT15 OUT: P15 Position                */\r
+#define PORT15_OUT_P15_Msk                    (0x01UL << PORT15_OUT_P15_Pos)                          /*!< PORT15 OUT: P15 Mask                    */\r
+\r
+/* ---------------------------------  PORT15_OMR  --------------------------------- */\r
+#define PORT15_OMR_PS0_Pos                    0                                                       /*!< PORT15 OMR: PS0 Position                */\r
+#define PORT15_OMR_PS0_Msk                    (0x01UL << PORT15_OMR_PS0_Pos)                          /*!< PORT15 OMR: PS0 Mask                    */\r
+#define PORT15_OMR_PS1_Pos                    1                                                       /*!< PORT15 OMR: PS1 Position                */\r
+#define PORT15_OMR_PS1_Msk                    (0x01UL << PORT15_OMR_PS1_Pos)                          /*!< PORT15 OMR: PS1 Mask                    */\r
+#define PORT15_OMR_PS2_Pos                    2                                                       /*!< PORT15 OMR: PS2 Position                */\r
+#define PORT15_OMR_PS2_Msk                    (0x01UL << PORT15_OMR_PS2_Pos)                          /*!< PORT15 OMR: PS2 Mask                    */\r
+#define PORT15_OMR_PS3_Pos                    3                                                       /*!< PORT15 OMR: PS3 Position                */\r
+#define PORT15_OMR_PS3_Msk                    (0x01UL << PORT15_OMR_PS3_Pos)                          /*!< PORT15 OMR: PS3 Mask                    */\r
+#define PORT15_OMR_PS4_Pos                    4                                                       /*!< PORT15 OMR: PS4 Position                */\r
+#define PORT15_OMR_PS4_Msk                    (0x01UL << PORT15_OMR_PS4_Pos)                          /*!< PORT15 OMR: PS4 Mask                    */\r
+#define PORT15_OMR_PS5_Pos                    5                                                       /*!< PORT15 OMR: PS5 Position                */\r
+#define PORT15_OMR_PS5_Msk                    (0x01UL << PORT15_OMR_PS5_Pos)                          /*!< PORT15 OMR: PS5 Mask                    */\r
+#define PORT15_OMR_PS6_Pos                    6                                                       /*!< PORT15 OMR: PS6 Position                */\r
+#define PORT15_OMR_PS6_Msk                    (0x01UL << PORT15_OMR_PS6_Pos)                          /*!< PORT15 OMR: PS6 Mask                    */\r
+#define PORT15_OMR_PS7_Pos                    7                                                       /*!< PORT15 OMR: PS7 Position                */\r
+#define PORT15_OMR_PS7_Msk                    (0x01UL << PORT15_OMR_PS7_Pos)                          /*!< PORT15 OMR: PS7 Mask                    */\r
+#define PORT15_OMR_PS8_Pos                    8                                                       /*!< PORT15 OMR: PS8 Position                */\r
+#define PORT15_OMR_PS8_Msk                    (0x01UL << PORT15_OMR_PS8_Pos)                          /*!< PORT15 OMR: PS8 Mask                    */\r
+#define PORT15_OMR_PS9_Pos                    9                                                       /*!< PORT15 OMR: PS9 Position                */\r
+#define PORT15_OMR_PS9_Msk                    (0x01UL << PORT15_OMR_PS9_Pos)                          /*!< PORT15 OMR: PS9 Mask                    */\r
+#define PORT15_OMR_PS10_Pos                   10                                                      /*!< PORT15 OMR: PS10 Position               */\r
+#define PORT15_OMR_PS10_Msk                   (0x01UL << PORT15_OMR_PS10_Pos)                         /*!< PORT15 OMR: PS10 Mask                   */\r
+#define PORT15_OMR_PS11_Pos                   11                                                      /*!< PORT15 OMR: PS11 Position               */\r
+#define PORT15_OMR_PS11_Msk                   (0x01UL << PORT15_OMR_PS11_Pos)                         /*!< PORT15 OMR: PS11 Mask                   */\r
+#define PORT15_OMR_PS12_Pos                   12                                                      /*!< PORT15 OMR: PS12 Position               */\r
+#define PORT15_OMR_PS12_Msk                   (0x01UL << PORT15_OMR_PS12_Pos)                         /*!< PORT15 OMR: PS12 Mask                   */\r
+#define PORT15_OMR_PS13_Pos                   13                                                      /*!< PORT15 OMR: PS13 Position               */\r
+#define PORT15_OMR_PS13_Msk                   (0x01UL << PORT15_OMR_PS13_Pos)                         /*!< PORT15 OMR: PS13 Mask                   */\r
+#define PORT15_OMR_PS14_Pos                   14                                                      /*!< PORT15 OMR: PS14 Position               */\r
+#define PORT15_OMR_PS14_Msk                   (0x01UL << PORT15_OMR_PS14_Pos)                         /*!< PORT15 OMR: PS14 Mask                   */\r
+#define PORT15_OMR_PS15_Pos                   15                                                      /*!< PORT15 OMR: PS15 Position               */\r
+#define PORT15_OMR_PS15_Msk                   (0x01UL << PORT15_OMR_PS15_Pos)                         /*!< PORT15 OMR: PS15 Mask                   */\r
+#define PORT15_OMR_PR0_Pos                    16                                                      /*!< PORT15 OMR: PR0 Position                */\r
+#define PORT15_OMR_PR0_Msk                    (0x01UL << PORT15_OMR_PR0_Pos)                          /*!< PORT15 OMR: PR0 Mask                    */\r
+#define PORT15_OMR_PR1_Pos                    17                                                      /*!< PORT15 OMR: PR1 Position                */\r
+#define PORT15_OMR_PR1_Msk                    (0x01UL << PORT15_OMR_PR1_Pos)                          /*!< PORT15 OMR: PR1 Mask                    */\r
+#define PORT15_OMR_PR2_Pos                    18                                                      /*!< PORT15 OMR: PR2 Position                */\r
+#define PORT15_OMR_PR2_Msk                    (0x01UL << PORT15_OMR_PR2_Pos)                          /*!< PORT15 OMR: PR2 Mask                    */\r
+#define PORT15_OMR_PR3_Pos                    19                                                      /*!< PORT15 OMR: PR3 Position                */\r
+#define PORT15_OMR_PR3_Msk                    (0x01UL << PORT15_OMR_PR3_Pos)                          /*!< PORT15 OMR: PR3 Mask                    */\r
+#define PORT15_OMR_PR4_Pos                    20                                                      /*!< PORT15 OMR: PR4 Position                */\r
+#define PORT15_OMR_PR4_Msk                    (0x01UL << PORT15_OMR_PR4_Pos)                          /*!< PORT15 OMR: PR4 Mask                    */\r
+#define PORT15_OMR_PR5_Pos                    21                                                      /*!< PORT15 OMR: PR5 Position                */\r
+#define PORT15_OMR_PR5_Msk                    (0x01UL << PORT15_OMR_PR5_Pos)                          /*!< PORT15 OMR: PR5 Mask                    */\r
+#define PORT15_OMR_PR6_Pos                    22                                                      /*!< PORT15 OMR: PR6 Position                */\r
+#define PORT15_OMR_PR6_Msk                    (0x01UL << PORT15_OMR_PR6_Pos)                          /*!< PORT15 OMR: PR6 Mask                    */\r
+#define PORT15_OMR_PR7_Pos                    23                                                      /*!< PORT15 OMR: PR7 Position                */\r
+#define PORT15_OMR_PR7_Msk                    (0x01UL << PORT15_OMR_PR7_Pos)                          /*!< PORT15 OMR: PR7 Mask                    */\r
+#define PORT15_OMR_PR8_Pos                    24                                                      /*!< PORT15 OMR: PR8 Position                */\r
+#define PORT15_OMR_PR8_Msk                    (0x01UL << PORT15_OMR_PR8_Pos)                          /*!< PORT15 OMR: PR8 Mask                    */\r
+#define PORT15_OMR_PR9_Pos                    25                                                      /*!< PORT15 OMR: PR9 Position                */\r
+#define PORT15_OMR_PR9_Msk                    (0x01UL << PORT15_OMR_PR9_Pos)                          /*!< PORT15 OMR: PR9 Mask                    */\r
+#define PORT15_OMR_PR10_Pos                   26                                                      /*!< PORT15 OMR: PR10 Position               */\r
+#define PORT15_OMR_PR10_Msk                   (0x01UL << PORT15_OMR_PR10_Pos)                         /*!< PORT15 OMR: PR10 Mask                   */\r
+#define PORT15_OMR_PR11_Pos                   27                                                      /*!< PORT15 OMR: PR11 Position               */\r
+#define PORT15_OMR_PR11_Msk                   (0x01UL << PORT15_OMR_PR11_Pos)                         /*!< PORT15 OMR: PR11 Mask                   */\r
+#define PORT15_OMR_PR12_Pos                   28                                                      /*!< PORT15 OMR: PR12 Position               */\r
+#define PORT15_OMR_PR12_Msk                   (0x01UL << PORT15_OMR_PR12_Pos)                         /*!< PORT15 OMR: PR12 Mask                   */\r
+#define PORT15_OMR_PR13_Pos                   29                                                      /*!< PORT15 OMR: PR13 Position               */\r
+#define PORT15_OMR_PR13_Msk                   (0x01UL << PORT15_OMR_PR13_Pos)                         /*!< PORT15 OMR: PR13 Mask                   */\r
+#define PORT15_OMR_PR14_Pos                   30                                                      /*!< PORT15 OMR: PR14 Position               */\r
+#define PORT15_OMR_PR14_Msk                   (0x01UL << PORT15_OMR_PR14_Pos)                         /*!< PORT15 OMR: PR14 Mask                   */\r
+#define PORT15_OMR_PR15_Pos                   31                                                      /*!< PORT15 OMR: PR15 Position               */\r
+#define PORT15_OMR_PR15_Msk                   (0x01UL << PORT15_OMR_PR15_Pos)                         /*!< PORT15 OMR: PR15 Mask                   */\r
+\r
+/* --------------------------------  PORT15_IOCR0  -------------------------------- */\r
+#define PORT15_IOCR0_PC0_Pos                  3                                                       /*!< PORT15 IOCR0: PC0 Position              */\r
+#define PORT15_IOCR0_PC0_Msk                  (0x1fUL << PORT15_IOCR0_PC0_Pos)                        /*!< PORT15 IOCR0: PC0 Mask                  */\r
+#define PORT15_IOCR0_PC1_Pos                  11                                                      /*!< PORT15 IOCR0: PC1 Position              */\r
+#define PORT15_IOCR0_PC1_Msk                  (0x1fUL << PORT15_IOCR0_PC1_Pos)                        /*!< PORT15 IOCR0: PC1 Mask                  */\r
+#define PORT15_IOCR0_PC2_Pos                  19                                                      /*!< PORT15 IOCR0: PC2 Position              */\r
+#define PORT15_IOCR0_PC2_Msk                  (0x1fUL << PORT15_IOCR0_PC2_Pos)                        /*!< PORT15 IOCR0: PC2 Mask                  */\r
+#define PORT15_IOCR0_PC3_Pos                  27                                                      /*!< PORT15 IOCR0: PC3 Position              */\r
+#define PORT15_IOCR0_PC3_Msk                  (0x1fUL << PORT15_IOCR0_PC3_Pos)                        /*!< PORT15 IOCR0: PC3 Mask                  */\r
+\r
+/* --------------------------------  PORT15_IOCR4  -------------------------------- */\r
+#define PORT15_IOCR4_PC4_Pos                  3                                                       /*!< PORT15 IOCR4: PC4 Position              */\r
+#define PORT15_IOCR4_PC4_Msk                  (0x1fUL << PORT15_IOCR4_PC4_Pos)                        /*!< PORT15 IOCR4: PC4 Mask                  */\r
+#define PORT15_IOCR4_PC5_Pos                  11                                                      /*!< PORT15 IOCR4: PC5 Position              */\r
+#define PORT15_IOCR4_PC5_Msk                  (0x1fUL << PORT15_IOCR4_PC5_Pos)                        /*!< PORT15 IOCR4: PC5 Mask                  */\r
+#define PORT15_IOCR4_PC6_Pos                  19                                                      /*!< PORT15 IOCR4: PC6 Position              */\r
+#define PORT15_IOCR4_PC6_Msk                  (0x1fUL << PORT15_IOCR4_PC6_Pos)                        /*!< PORT15 IOCR4: PC6 Mask                  */\r
+#define PORT15_IOCR4_PC7_Pos                  27                                                      /*!< PORT15 IOCR4: PC7 Position              */\r
+#define PORT15_IOCR4_PC7_Msk                  (0x1fUL << PORT15_IOCR4_PC7_Pos)                        /*!< PORT15 IOCR4: PC7 Mask                  */\r
+\r
+/* --------------------------------  PORT15_IOCR8  -------------------------------- */\r
+#define PORT15_IOCR8_PC8_Pos                  3                                                       /*!< PORT15 IOCR8: PC8 Position              */\r
+#define PORT15_IOCR8_PC8_Msk                  (0x1fUL << PORT15_IOCR8_PC8_Pos)                        /*!< PORT15 IOCR8: PC8 Mask                  */\r
+#define PORT15_IOCR8_PC9_Pos                  11                                                      /*!< PORT15 IOCR8: PC9 Position              */\r
+#define PORT15_IOCR8_PC9_Msk                  (0x1fUL << PORT15_IOCR8_PC9_Pos)                        /*!< PORT15 IOCR8: PC9 Mask                  */\r
+#define PORT15_IOCR8_PC10_Pos                 19                                                      /*!< PORT15 IOCR8: PC10 Position             */\r
+#define PORT15_IOCR8_PC10_Msk                 (0x1fUL << PORT15_IOCR8_PC10_Pos)                       /*!< PORT15 IOCR8: PC10 Mask                 */\r
+#define PORT15_IOCR8_PC11_Pos                 27                                                      /*!< PORT15 IOCR8: PC11 Position             */\r
+#define PORT15_IOCR8_PC11_Msk                 (0x1fUL << PORT15_IOCR8_PC11_Pos)                       /*!< PORT15 IOCR8: PC11 Mask                 */\r
+\r
+/* --------------------------------  PORT15_IOCR12  ------------------------------- */\r
+#define PORT15_IOCR12_PC12_Pos                3                                                       /*!< PORT15 IOCR12: PC12 Position            */\r
+#define PORT15_IOCR12_PC12_Msk                (0x1fUL << PORT15_IOCR12_PC12_Pos)                      /*!< PORT15 IOCR12: PC12 Mask                */\r
+#define PORT15_IOCR12_PC13_Pos                11                                                      /*!< PORT15 IOCR12: PC13 Position            */\r
+#define PORT15_IOCR12_PC13_Msk                (0x1fUL << PORT15_IOCR12_PC13_Pos)                      /*!< PORT15 IOCR12: PC13 Mask                */\r
+#define PORT15_IOCR12_PC14_Pos                19                                                      /*!< PORT15 IOCR12: PC14 Position            */\r
+#define PORT15_IOCR12_PC14_Msk                (0x1fUL << PORT15_IOCR12_PC14_Pos)                      /*!< PORT15 IOCR12: PC14 Mask                */\r
+#define PORT15_IOCR12_PC15_Pos                27                                                      /*!< PORT15 IOCR12: PC15 Position            */\r
+#define PORT15_IOCR12_PC15_Msk                (0x1fUL << PORT15_IOCR12_PC15_Pos)                      /*!< PORT15 IOCR12: PC15 Mask                */\r
+\r
+/* ----------------------------------  PORT15_IN  --------------------------------- */\r
+#define PORT15_IN_P0_Pos                      0                                                       /*!< PORT15 IN: P0 Position                  */\r
+#define PORT15_IN_P0_Msk                      (0x01UL << PORT15_IN_P0_Pos)                            /*!< PORT15 IN: P0 Mask                      */\r
+#define PORT15_IN_P1_Pos                      1                                                       /*!< PORT15 IN: P1 Position                  */\r
+#define PORT15_IN_P1_Msk                      (0x01UL << PORT15_IN_P1_Pos)                            /*!< PORT15 IN: P1 Mask                      */\r
+#define PORT15_IN_P2_Pos                      2                                                       /*!< PORT15 IN: P2 Position                  */\r
+#define PORT15_IN_P2_Msk                      (0x01UL << PORT15_IN_P2_Pos)                            /*!< PORT15 IN: P2 Mask                      */\r
+#define PORT15_IN_P3_Pos                      3                                                       /*!< PORT15 IN: P3 Position                  */\r
+#define PORT15_IN_P3_Msk                      (0x01UL << PORT15_IN_P3_Pos)                            /*!< PORT15 IN: P3 Mask                      */\r
+#define PORT15_IN_P4_Pos                      4                                                       /*!< PORT15 IN: P4 Position                  */\r
+#define PORT15_IN_P4_Msk                      (0x01UL << PORT15_IN_P4_Pos)                            /*!< PORT15 IN: P4 Mask                      */\r
+#define PORT15_IN_P5_Pos                      5                                                       /*!< PORT15 IN: P5 Position                  */\r
+#define PORT15_IN_P5_Msk                      (0x01UL << PORT15_IN_P5_Pos)                            /*!< PORT15 IN: P5 Mask                      */\r
+#define PORT15_IN_P6_Pos                      6                                                       /*!< PORT15 IN: P6 Position                  */\r
+#define PORT15_IN_P6_Msk                      (0x01UL << PORT15_IN_P6_Pos)                            /*!< PORT15 IN: P6 Mask                      */\r
+#define PORT15_IN_P7_Pos                      7                                                       /*!< PORT15 IN: P7 Position                  */\r
+#define PORT15_IN_P7_Msk                      (0x01UL << PORT15_IN_P7_Pos)                            /*!< PORT15 IN: P7 Mask                      */\r
+#define PORT15_IN_P8_Pos                      8                                                       /*!< PORT15 IN: P8 Position                  */\r
+#define PORT15_IN_P8_Msk                      (0x01UL << PORT15_IN_P8_Pos)                            /*!< PORT15 IN: P8 Mask                      */\r
+#define PORT15_IN_P9_Pos                      9                                                       /*!< PORT15 IN: P9 Position                  */\r
+#define PORT15_IN_P9_Msk                      (0x01UL << PORT15_IN_P9_Pos)                            /*!< PORT15 IN: P9 Mask                      */\r
+#define PORT15_IN_P10_Pos                     10                                                      /*!< PORT15 IN: P10 Position                 */\r
+#define PORT15_IN_P10_Msk                     (0x01UL << PORT15_IN_P10_Pos)                           /*!< PORT15 IN: P10 Mask                     */\r
+#define PORT15_IN_P11_Pos                     11                                                      /*!< PORT15 IN: P11 Position                 */\r
+#define PORT15_IN_P11_Msk                     (0x01UL << PORT15_IN_P11_Pos)                           /*!< PORT15 IN: P11 Mask                     */\r
+#define PORT15_IN_P12_Pos                     12                                                      /*!< PORT15 IN: P12 Position                 */\r
+#define PORT15_IN_P12_Msk                     (0x01UL << PORT15_IN_P12_Pos)                           /*!< PORT15 IN: P12 Mask                     */\r
+#define PORT15_IN_P13_Pos                     13                                                      /*!< PORT15 IN: P13 Position                 */\r
+#define PORT15_IN_P13_Msk                     (0x01UL << PORT15_IN_P13_Pos)                           /*!< PORT15 IN: P13 Mask                     */\r
+#define PORT15_IN_P14_Pos                     14                                                      /*!< PORT15 IN: P14 Position                 */\r
+#define PORT15_IN_P14_Msk                     (0x01UL << PORT15_IN_P14_Pos)                           /*!< PORT15 IN: P14 Mask                     */\r
+#define PORT15_IN_P15_Pos                     15                                                      /*!< PORT15 IN: P15 Position                 */\r
+#define PORT15_IN_P15_Msk                     (0x01UL << PORT15_IN_P15_Pos)                           /*!< PORT15 IN: P15 Mask                     */\r
+\r
+/* --------------------------------  PORT15_PDISC  -------------------------------- */\r
+#define PORT15_PDISC_PDIS2_Pos                2                                                       /*!< PORT15 PDISC: PDIS2 Position            */\r
+#define PORT15_PDISC_PDIS2_Msk                (0x01UL << PORT15_PDISC_PDIS2_Pos)                      /*!< PORT15 PDISC: PDIS2 Mask                */\r
+#define PORT15_PDISC_PDIS3_Pos                3                                                       /*!< PORT15 PDISC: PDIS3 Position            */\r
+#define PORT15_PDISC_PDIS3_Msk                (0x01UL << PORT15_PDISC_PDIS3_Pos)                      /*!< PORT15 PDISC: PDIS3 Mask                */\r
+#define PORT15_PDISC_PDIS4_Pos                4                                                       /*!< PORT15 PDISC: PDIS4 Position            */\r
+#define PORT15_PDISC_PDIS4_Msk                (0x01UL << PORT15_PDISC_PDIS4_Pos)                      /*!< PORT15 PDISC: PDIS4 Mask                */\r
+#define PORT15_PDISC_PDIS5_Pos                5                                                       /*!< PORT15 PDISC: PDIS5 Position            */\r
+#define PORT15_PDISC_PDIS5_Msk                (0x01UL << PORT15_PDISC_PDIS5_Pos)                      /*!< PORT15 PDISC: PDIS5 Mask                */\r
+#define PORT15_PDISC_PDIS6_Pos                6                                                       /*!< PORT15 PDISC: PDIS6 Position            */\r
+#define PORT15_PDISC_PDIS6_Msk                (0x01UL << PORT15_PDISC_PDIS6_Pos)                      /*!< PORT15 PDISC: PDIS6 Mask                */\r
+#define PORT15_PDISC_PDIS7_Pos                7                                                       /*!< PORT15 PDISC: PDIS7 Position            */\r
+#define PORT15_PDISC_PDIS7_Msk                (0x01UL << PORT15_PDISC_PDIS7_Pos)                      /*!< PORT15 PDISC: PDIS7 Mask                */\r
+#define PORT15_PDISC_PDIS8_Pos                8                                                       /*!< PORT15 PDISC: PDIS8 Position            */\r
+#define PORT15_PDISC_PDIS8_Msk                (0x01UL << PORT15_PDISC_PDIS8_Pos)                      /*!< PORT15 PDISC: PDIS8 Mask                */\r
+#define PORT15_PDISC_PDIS9_Pos                9                                                       /*!< PORT15 PDISC: PDIS9 Position            */\r
+#define PORT15_PDISC_PDIS9_Msk                (0x01UL << PORT15_PDISC_PDIS9_Pos)                      /*!< PORT15 PDISC: PDIS9 Mask                */\r
+#define PORT15_PDISC_PDIS12_Pos               12                                                      /*!< PORT15 PDISC: PDIS12 Position           */\r
+#define PORT15_PDISC_PDIS12_Msk               (0x01UL << PORT15_PDISC_PDIS12_Pos)                     /*!< PORT15 PDISC: PDIS12 Mask               */\r
+#define PORT15_PDISC_PDIS13_Pos               13                                                      /*!< PORT15 PDISC: PDIS13 Position           */\r
+#define PORT15_PDISC_PDIS13_Msk               (0x01UL << PORT15_PDISC_PDIS13_Pos)                     /*!< PORT15 PDISC: PDIS13 Mask               */\r
+#define PORT15_PDISC_PDIS14_Pos               14                                                      /*!< PORT15 PDISC: PDIS14 Position           */\r
+#define PORT15_PDISC_PDIS14_Msk               (0x01UL << PORT15_PDISC_PDIS14_Pos)                     /*!< PORT15 PDISC: PDIS14 Mask               */\r
+#define PORT15_PDISC_PDIS15_Pos               15                                                      /*!< PORT15 PDISC: PDIS15 Position           */\r
+#define PORT15_PDISC_PDIS15_Msk               (0x01UL << PORT15_PDISC_PDIS15_Pos)                     /*!< PORT15 PDISC: PDIS15 Mask               */\r
+\r
+/* ---------------------------------  PORT15_PPS  --------------------------------- */\r
+#define PORT15_PPS_PPS0_Pos                   0                                                       /*!< PORT15 PPS: PPS0 Position               */\r
+#define PORT15_PPS_PPS0_Msk                   (0x01UL << PORT15_PPS_PPS0_Pos)                         /*!< PORT15 PPS: PPS0 Mask                   */\r
+#define PORT15_PPS_PPS1_Pos                   1                                                       /*!< PORT15 PPS: PPS1 Position               */\r
+#define PORT15_PPS_PPS1_Msk                   (0x01UL << PORT15_PPS_PPS1_Pos)                         /*!< PORT15 PPS: PPS1 Mask                   */\r
+#define PORT15_PPS_PPS2_Pos                   2                                                       /*!< PORT15 PPS: PPS2 Position               */\r
+#define PORT15_PPS_PPS2_Msk                   (0x01UL << PORT15_PPS_PPS2_Pos)                         /*!< PORT15 PPS: PPS2 Mask                   */\r
+#define PORT15_PPS_PPS3_Pos                   3                                                       /*!< PORT15 PPS: PPS3 Position               */\r
+#define PORT15_PPS_PPS3_Msk                   (0x01UL << PORT15_PPS_PPS3_Pos)                         /*!< PORT15 PPS: PPS3 Mask                   */\r
+#define PORT15_PPS_PPS4_Pos                   4                                                       /*!< PORT15 PPS: PPS4 Position               */\r
+#define PORT15_PPS_PPS4_Msk                   (0x01UL << PORT15_PPS_PPS4_Pos)                         /*!< PORT15 PPS: PPS4 Mask                   */\r
+#define PORT15_PPS_PPS5_Pos                   5                                                       /*!< PORT15 PPS: PPS5 Position               */\r
+#define PORT15_PPS_PPS5_Msk                   (0x01UL << PORT15_PPS_PPS5_Pos)                         /*!< PORT15 PPS: PPS5 Mask                   */\r
+#define PORT15_PPS_PPS6_Pos                   6                                                       /*!< PORT15 PPS: PPS6 Position               */\r
+#define PORT15_PPS_PPS6_Msk                   (0x01UL << PORT15_PPS_PPS6_Pos)                         /*!< PORT15 PPS: PPS6 Mask                   */\r
+#define PORT15_PPS_PPS7_Pos                   7                                                       /*!< PORT15 PPS: PPS7 Position               */\r
+#define PORT15_PPS_PPS7_Msk                   (0x01UL << PORT15_PPS_PPS7_Pos)                         /*!< PORT15 PPS: PPS7 Mask                   */\r
+#define PORT15_PPS_PPS8_Pos                   8                                                       /*!< PORT15 PPS: PPS8 Position               */\r
+#define PORT15_PPS_PPS8_Msk                   (0x01UL << PORT15_PPS_PPS8_Pos)                         /*!< PORT15 PPS: PPS8 Mask                   */\r
+#define PORT15_PPS_PPS9_Pos                   9                                                       /*!< PORT15 PPS: PPS9 Position               */\r
+#define PORT15_PPS_PPS9_Msk                   (0x01UL << PORT15_PPS_PPS9_Pos)                         /*!< PORT15 PPS: PPS9 Mask                   */\r
+#define PORT15_PPS_PPS10_Pos                  10                                                      /*!< PORT15 PPS: PPS10 Position              */\r
+#define PORT15_PPS_PPS10_Msk                  (0x01UL << PORT15_PPS_PPS10_Pos)                        /*!< PORT15 PPS: PPS10 Mask                  */\r
+#define PORT15_PPS_PPS11_Pos                  11                                                      /*!< PORT15 PPS: PPS11 Position              */\r
+#define PORT15_PPS_PPS11_Msk                  (0x01UL << PORT15_PPS_PPS11_Pos)                        /*!< PORT15 PPS: PPS11 Mask                  */\r
+#define PORT15_PPS_PPS12_Pos                  12                                                      /*!< PORT15 PPS: PPS12 Position              */\r
+#define PORT15_PPS_PPS12_Msk                  (0x01UL << PORT15_PPS_PPS12_Pos)                        /*!< PORT15 PPS: PPS12 Mask                  */\r
+#define PORT15_PPS_PPS13_Pos                  13                                                      /*!< PORT15 PPS: PPS13 Position              */\r
+#define PORT15_PPS_PPS13_Msk                  (0x01UL << PORT15_PPS_PPS13_Pos)                        /*!< PORT15 PPS: PPS13 Mask                  */\r
+#define PORT15_PPS_PPS14_Pos                  14                                                      /*!< PORT15 PPS: PPS14 Position              */\r
+#define PORT15_PPS_PPS14_Msk                  (0x01UL << PORT15_PPS_PPS14_Pos)                        /*!< PORT15 PPS: PPS14 Mask                  */\r
+#define PORT15_PPS_PPS15_Pos                  15                                                      /*!< PORT15 PPS: PPS15 Position              */\r
+#define PORT15_PPS_PPS15_Msk                  (0x01UL << PORT15_PPS_PPS15_Pos)                        /*!< PORT15 PPS: PPS15 Mask                  */\r
+\r
+/* --------------------------------  PORT15_HWSEL  -------------------------------- */\r
+#define PORT15_HWSEL_HW0_Pos                  0                                                       /*!< PORT15 HWSEL: HW0 Position              */\r
+#define PORT15_HWSEL_HW0_Msk                  (0x03UL << PORT15_HWSEL_HW0_Pos)                        /*!< PORT15 HWSEL: HW0 Mask                  */\r
+#define PORT15_HWSEL_HW1_Pos                  2                                                       /*!< PORT15 HWSEL: HW1 Position              */\r
+#define PORT15_HWSEL_HW1_Msk                  (0x03UL << PORT15_HWSEL_HW1_Pos)                        /*!< PORT15 HWSEL: HW1 Mask                  */\r
+#define PORT15_HWSEL_HW2_Pos                  4                                                       /*!< PORT15 HWSEL: HW2 Position              */\r
+#define PORT15_HWSEL_HW2_Msk                  (0x03UL << PORT15_HWSEL_HW2_Pos)                        /*!< PORT15 HWSEL: HW2 Mask                  */\r
+#define PORT15_HWSEL_HW3_Pos                  6                                                       /*!< PORT15 HWSEL: HW3 Position              */\r
+#define PORT15_HWSEL_HW3_Msk                  (0x03UL << PORT15_HWSEL_HW3_Pos)                        /*!< PORT15 HWSEL: HW3 Mask                  */\r
+#define PORT15_HWSEL_HW4_Pos                  8                                                       /*!< PORT15 HWSEL: HW4 Position              */\r
+#define PORT15_HWSEL_HW4_Msk                  (0x03UL << PORT15_HWSEL_HW4_Pos)                        /*!< PORT15 HWSEL: HW4 Mask                  */\r
+#define PORT15_HWSEL_HW5_Pos                  10                                                      /*!< PORT15 HWSEL: HW5 Position              */\r
+#define PORT15_HWSEL_HW5_Msk                  (0x03UL << PORT15_HWSEL_HW5_Pos)                        /*!< PORT15 HWSEL: HW5 Mask                  */\r
+#define PORT15_HWSEL_HW6_Pos                  12                                                      /*!< PORT15 HWSEL: HW6 Position              */\r
+#define PORT15_HWSEL_HW6_Msk                  (0x03UL << PORT15_HWSEL_HW6_Pos)                        /*!< PORT15 HWSEL: HW6 Mask                  */\r
+#define PORT15_HWSEL_HW7_Pos                  14                                                      /*!< PORT15 HWSEL: HW7 Position              */\r
+#define PORT15_HWSEL_HW7_Msk                  (0x03UL << PORT15_HWSEL_HW7_Pos)                        /*!< PORT15 HWSEL: HW7 Mask                  */\r
+#define PORT15_HWSEL_HW8_Pos                  16                                                      /*!< PORT15 HWSEL: HW8 Position              */\r
+#define PORT15_HWSEL_HW8_Msk                  (0x03UL << PORT15_HWSEL_HW8_Pos)                        /*!< PORT15 HWSEL: HW8 Mask                  */\r
+#define PORT15_HWSEL_HW9_Pos                  18                                                      /*!< PORT15 HWSEL: HW9 Position              */\r
+#define PORT15_HWSEL_HW9_Msk                  (0x03UL << PORT15_HWSEL_HW9_Pos)                        /*!< PORT15 HWSEL: HW9 Mask                  */\r
+#define PORT15_HWSEL_HW10_Pos                 20                                                      /*!< PORT15 HWSEL: HW10 Position             */\r
+#define PORT15_HWSEL_HW10_Msk                 (0x03UL << PORT15_HWSEL_HW10_Pos)                       /*!< PORT15 HWSEL: HW10 Mask                 */\r
+#define PORT15_HWSEL_HW11_Pos                 22                                                      /*!< PORT15 HWSEL: HW11 Position             */\r
+#define PORT15_HWSEL_HW11_Msk                 (0x03UL << PORT15_HWSEL_HW11_Pos)                       /*!< PORT15 HWSEL: HW11 Mask                 */\r
+#define PORT15_HWSEL_HW12_Pos                 24                                                      /*!< PORT15 HWSEL: HW12 Position             */\r
+#define PORT15_HWSEL_HW12_Msk                 (0x03UL << PORT15_HWSEL_HW12_Pos)                       /*!< PORT15 HWSEL: HW12 Mask                 */\r
+#define PORT15_HWSEL_HW13_Pos                 26                                                      /*!< PORT15 HWSEL: HW13 Position             */\r
+#define PORT15_HWSEL_HW13_Msk                 (0x03UL << PORT15_HWSEL_HW13_Pos)                       /*!< PORT15 HWSEL: HW13 Mask                 */\r
+#define PORT15_HWSEL_HW14_Pos                 28                                                      /*!< PORT15 HWSEL: HW14 Position             */\r
+#define PORT15_HWSEL_HW14_Msk                 (0x03UL << PORT15_HWSEL_HW14_Pos)                       /*!< PORT15 HWSEL: HW14 Mask                 */\r
+#define PORT15_HWSEL_HW15_Pos                 30                                                      /*!< PORT15 HWSEL: HW15 Position             */\r
+#define PORT15_HWSEL_HW15_Msk                 (0x03UL << PORT15_HWSEL_HW15_Pos)                       /*!< PORT15 HWSEL: HW15 Mask                 */\r
+\r
+/* ===== OBSELETE MACROS- DO NOT USE PLEASE ====== */\r
+#define   CCU4_CC4_INS_EV2S_Pos        (8U)\r
+#define   CCU4_CC4_INS_EV2S_Msk        (0x0000000FU  << CCU4_CC4_INS_EV2S_Pos)\r
+\r
+#define   CCU8_CC8_INS_EV2S_Pos        (8U)\r
+#define   CCU8_CC8_INS_EV2S_Msk        (0x0000000FU  << CCU8_CC8_INS_EV2S_Pos)\r
+\r
+#define   GPDMA1_SAR_SAR_Pos   (0U)\r
+#define   GPDMA1_SAR_SAR_Msk   (0xFFFFFFFFU  << GPDMA1_SAR_SAR_Pos)\r
+\r
+#define   GPDMA1_DAR_DAR_Pos   (0U)\r
+#define   GPDMA1_DAR_DAR_Msk   (0xFFFFFFFFU  << GPDMA1_DAR_DAR_Pos)\r
+\r
+#define   DSD_GLOBRC_CHRUN_Pos         (0U)\r
+#define   DSD_GLOBRC_CHRUN_Msk         (0x0000000FU  << DSD_GLOBRC_CHRUN_Pos)\r
+\r
+#define   ETH_MAC_CONFIGURATION_LUD_Pos        (8U)\r
+#define   ETH_MAC_CONFIGURATION_LUD_Msk        (0x00000001U  << ETH_MAC_CONFIGURATION_LUD_Pos)\r
+\r
+#define   ETH_INTERRUPT_MASK_RMIIIM_Pos        (0U)\r
+#define   ETH_INTERRUPT_MASK_RMIIIM_Msk        (0x00000001U  << ETH_INTERRUPT_MASK_RMIIIM_Pos)\r
+\r
+#define   ETH_INTERRUPT_MASK_LPIIM_Pos         (10U)\r
+#define   ETH_INTERRUPT_MASK_LPIIM_Msk         (0x00000001U  << ETH_INTERRUPT_MASK_LPIIM_Pos)\r
+\r
+#define   ETH_INTERRUPT_STATUS_RMIIIS_Pos      (0U)\r
+#define   ETH_INTERRUPT_STATUS_RMIIIS_Msk      (0x00000001U  << ETH_INTERRUPT_STATUS_RMIIIS_Pos)\r
+\r
+#define   ETH_INTERRUPT_STATUS_LPIIS_Pos       (10U)\r
+#define   ETH_INTERRUPT_STATUS_LPIIS_Msk       (0x00000001U  << ETH_INTERRUPT_STATUS_LPIIS_Pos)\r
+\r
+#define   ETH_TIMESTAMP_CONTROL_ATSFC_Pos      (24U)\r
+#define   ETH_TIMESTAMP_CONTROL_ATSFC_Msk      (0x00000001U  << ETH_TIMESTAMP_CONTROL_ATSFC_Pos)\r
+\r
+#define   ETH_TIMESTAMP_CONTROL_ATSEN0_Pos     (25U)\r
+#define   ETH_TIMESTAMP_CONTROL_ATSEN0_Msk     (0x00000001U  << ETH_TIMESTAMP_CONTROL_ATSEN0_Pos)\r
+\r
+#define   ETH_TIMESTAMP_CONTROL_ATSEN1_Pos     (26U)\r
+#define   ETH_TIMESTAMP_CONTROL_ATSEN1_Msk     (0x00000001U  << ETH_TIMESTAMP_CONTROL_ATSEN1_Pos)\r
+\r
+#define   ETH_TIMESTAMP_CONTROL_ATSEN2_Pos     (27U)\r
+#define   ETH_TIMESTAMP_CONTROL_ATSEN2_Msk     (0x00000001U  << ETH_TIMESTAMP_CONTROL_ATSEN2_Pos)\r
+\r
+#define   ETH_TIMESTAMP_CONTROL_ATSEN3_Pos     (28U)\r
+#define   ETH_TIMESTAMP_CONTROL_ATSEN3_Msk     (0x00000001U  << ETH_TIMESTAMP_CONTROL_ATSEN3_Pos)\r
+\r
+#define   ETH_TIMESTAMP_STATUS_AUXTSTRIG_Pos   (2U)\r
+#define   ETH_TIMESTAMP_STATUS_AUXTSTRIG_Msk   (0x00000001U  << ETH_TIMESTAMP_STATUS_AUXTSTRIG_Pos)\r
+\r
+#define   ETH_TIMESTAMP_STATUS_ATSSTN_Pos      (16U)\r
+#define   ETH_TIMESTAMP_STATUS_ATSSTN_Msk      (0x0000000FU  << ETH_TIMESTAMP_STATUS_ATSSTN_Pos)\r
+\r
+#define   ETH_TIMESTAMP_STATUS_ATSSTM_Pos      (24U)\r
+#define   ETH_TIMESTAMP_STATUS_ATSSTM_Msk      (0x00000001U  << ETH_TIMESTAMP_STATUS_ATSSTM_Pos)\r
+\r
+#define   ETH_TIMESTAMP_STATUS_ATSNS_Pos       (25U)\r
+#define   ETH_TIMESTAMP_STATUS_ATSNS_Msk       (0x0000001FU  << ETH_TIMESTAMP_STATUS_ATSNS_Pos)\r
+\r
+#define   ETH_STATUS_MLI_Pos   (26U)\r
+#define   ETH_STATUS_MLI_Msk   (0x00000001U  << ETH_STATUS_MLI_Pos)\r
+\r
+#define   ETH_STATUS_ELPII_Pos         (30U)\r
+#define   ETH_STATUS_ELPII_Msk         (0x00000001U  << ETH_STATUS_ELPII_Pos)\r
+\r
+#define   ETH_OPERATION_MODE_EFC_Pos   (8U)\r
+#define   ETH_OPERATION_MODE_EFC_Msk   (0x00000001U  << ETH_OPERATION_MODE_EFC_Pos)\r
+\r
+#define   ETH_OPERATION_MODE_RFA_Pos   (9U)\r
+#define   ETH_OPERATION_MODE_RFA_Msk   (0x00000003U  << ETH_OPERATION_MODE_RFA_Pos)\r
+\r
+#define   ETH_OPERATION_MODE_RFD_Pos   (11U)\r
+#define   ETH_OPERATION_MODE_RFD_Msk   (0x00000003U  << ETH_OPERATION_MODE_RFD_Pos)\r
+\r
+#define   ETH_OPERATION_MODE_RFD2_Pos          (22U)\r
+#define   ETH_OPERATION_MODE_RFD2_Msk          (0x00000001U  << ETH_OPERATION_MODE_RFD2_Pos)\r
+\r
+#define   ETH_OPERATION_MODE_RFA2_Pos          (23U)\r
+#define   ETH_OPERATION_MODE_RFA2_Msk          (0x00000001U  << ETH_OPERATION_MODE_RFA2_Pos)\r
+\r
+#define   LEDTS_LDCMP1_CMP_LDATSCOM_Pos        (24U)\r
+#define   LEDTS_LDCMP1_CMP_LDATSCOM_Msk        (0x000000FFU  << LEDTS_LDCMP1_CMP_LDATSCOM_Pos)\r
+\r
+#define   PREF_PCON_PBS_Pos    (16U)\r
+#define   PREF_PCON_PBS_Msk    (0x00000001U  << PREF_PCON_PBS_Pos)\r
+\r
+#define   RTC_ID_ID_Pos        (0U)\r
+#define   RTC_ID_ID_Msk        (0xFFFFFFFFU  << RTC_ID_ID_Pos)\r
+\r
+#define   SCU_OSC_OSCHPCTRL_GAINSEL_Pos        (2U)\r
+#define   SCU_OSC_OSCHPCTRL_GAINSEL_Msk        (0x00000003U  << SCU_OSC_OSCHPCTRL_GAINSEL_Pos)\r
+\r
+#define   SCU_GENERAL_ID_ID_Pos        (0U)\r
+#define   SCU_GENERAL_ID_ID_Msk        (0xFFFFFFFFU  << SCU_GENERAL_ID_ID_Pos)\r
+\r
+#define   SCU_GENERAL_SDMMCDEL_DLYCTRL_Pos     (2U)\r
+#define   SCU_GENERAL_SDMMCDEL_DLYCTRL_Msk     (0x00000003U  << SCU_GENERAL_SDMMCDEL_DLYCTRL_Pos)\r
+\r
+#define   SCU_GENERAL_MIRRSTS_OSCSITRIM_Pos    (4U)\r
+#define   SCU_GENERAL_MIRRSTS_OSCSITRIM_Msk    (0x00000001U  << SCU_GENERAL_MIRRSTS_OSCSITRIM_Pos)\r
+\r
+#define   SCU_INTERRUPT_SRSTAT_OSCSITRIM_Pos   (20U)\r
+#define   SCU_INTERRUPT_SRSTAT_OSCSITRIM_Msk   (0x00000001U  << SCU_INTERRUPT_SRSTAT_OSCSITRIM_Pos)\r
+\r
+#define   SCU_INTERRUPT_SRRAW_OSCSITRIM_Pos    (20U)\r
+#define   SCU_INTERRUPT_SRRAW_OSCSITRIM_Msk    (0x00000001U  << SCU_INTERRUPT_SRRAW_OSCSITRIM_Pos)\r
+\r
+#define   SCU_INTERRUPT_SRMSK_OSCSITRIM_Pos    (20U)\r
+#define   SCU_INTERRUPT_SRMSK_OSCSITRIM_Msk    (0x00000001U  << SCU_INTERRUPT_SRMSK_OSCSITRIM_Pos)\r
+\r
+#define   SCU_INTERRUPT_SRCLR_OSCSITRIM_Pos    (20U)\r
+#define   SCU_INTERRUPT_SRCLR_OSCSITRIM_Msk    (0x00000001U  << SCU_INTERRUPT_SRCLR_OSCSITRIM_Pos)\r
+\r
+#define   SCU_INTERRUPT_SRSET_OSCSITRIM_Pos    (20U)\r
+#define   SCU_INTERRUPT_SRSET_OSCSITRIM_Msk    (0x00000001U  << SCU_INTERRUPT_SRSET_OSCSITRIM_Pos)\r
+\r
+#define   SCU_POWER_PWRSTAT_HPSS_Pos   (1U)\r
+#define   SCU_POWER_PWRSTAT_HPSS_Msk   (0x00000001U  << SCU_POWER_PWRSTAT_HPSS_Pos)\r
+\r
+#define   USB_GAHBCFG_NotiAllDmaWrit_Pos       (22U)\r
+#define   USB_GAHBCFG_NotiAllDmaWrit_Msk       (0x00000001U  << USB_GAHBCFG_NotiAllDmaWrit_Pos)\r
+\r
+#define   USB_GAHBCFG_RemMemSupp_Pos   (21U)\r
+#define   USB_GAHBCFG_RemMemSupp_Msk   (0x00000001U  << USB_GAHBCFG_RemMemSupp_Pos)\r
+\r
+#define   USB_GUSBCFG_TxEndDela_Pos    (28U)\r
+#define   USB_GUSBCFG_TxEndDela_Msk    (0x00000001U  << USB_GUSBCFG_TxEndDela_Pos)\r
+\r
+#define   USB_GUSBCFG_FSIntf_Pos       (5U)\r
+#define   USB_GUSBCFG_FSIntf_Msk       (0x00000001U  << USB_GUSBCFG_FSIntf_Pos)\r
+\r
+#define   USB_GUSBCFG_PHYIf_Pos        (3U)\r
+#define   USB_GUSBCFG_PHYIf_Msk        (0x00000001U  << USB_GUSBCFG_PHYIf_Pos)\r
+\r
+#define   USB_GINTSTS_DEVICEMODE_ResetDet_Pos          (23U)\r
+#define   USB_GINTSTS_DEVICEMODE_ResetDet_Msk          (0x00000001U  << USB_GINTSTS_DEVICEMODE_ResetDet_Pos)\r
+\r
+#define   USB_GINTMSK_DEVICEMODE_ResetDetMsk_Pos       (23U)\r
+#define   USB_GINTMSK_DEVICEMODE_ResetDetMsk_Msk       (0x00000001U  << USB_GINTMSK_DEVICEMODE_ResetDetMsk_Pos)\r
+\r
+#define   USB_GINTMSK_DEVICEMODE_FetSuspMsk_Pos        (22U)\r
+#define   USB_GINTMSK_DEVICEMODE_FetSuspMsk_Msk        (0x00000001U  << USB_GINTMSK_DEVICEMODE_FetSuspMsk_Pos)\r
+\r
+#define   USB_GUID_UserID_Pos          (0U)\r
+#define   USB_GUID_UserID_Msk          (0xFFFFFFFFU  << USB_GUID_UserID_Pos)\r
+\r
+#define   USB_CH_HCFG_PerSchedEna_Pos          (26U)\r
+#define   USB_CH_HCFG_PerSchedEna_Msk          (0x00000001U  << USB_CH_HCFG_PerSchedEna_Pos)\r
+\r
+#define   USB_CH_HCFG_FrListEn_Pos     (24U)\r
+#define   USB_CH_HCFG_FrListEn_Msk     (0x00000003U  << USB_CH_HCFG_FrListEn_Pos)\r
+\r
+#define   USB_CH_HCFG_DescDMA_Pos      (23U)\r
+#define   USB_CH_HCFG_DescDMA_Msk      (0x00000001U  << USB_CH_HCFG_DescDMA_Pos)\r
+\r
+#define   USB_CH_HCFG_ResValid_Pos     (8U)\r
+#define   USB_CH_HCFG_ResValid_Msk     (0x000000FFU  << USB_CH_HCFG_ResValid_Pos)\r
+\r
+#define   USB_CH_HCFG_Ena32KHzS_Pos    (7U)\r
+#define   USB_CH_HCFG_Ena32KHzS_Msk    (0x00000001U  << USB_CH_HCFG_Ena32KHzS_Pos)\r
+\r
+#define   USB_CH_HCFG_FSLSSupp_Pos     (2U)\r
+#define   USB_CH_HCFG_FSLSSupp_Msk     (0x00000001U  << USB_CH_HCFG_FSLSSupp_Pos)\r
+\r
+#define   USB_CH_HCFG_FSLSPclkSel_Pos          (0U)\r
+#define   USB_CH_HCFG_FSLSPclkSel_Msk          (0x00000003U  << USB_CH_HCFG_FSLSPclkSel_Pos)\r
+\r
+#define   USB_DCFG_ResValid_Pos        (26U)\r
+#define   USB_DCFG_ResValid_Msk        (0x0000003FU  << USB_DCFG_ResValid_Pos)\r
+\r
+#define   USB_DCFG_EPMisCnt_Pos        (18U)\r
+#define   USB_DCFG_EPMisCnt_Msk        (0x0000001FU  << USB_DCFG_EPMisCnt_Pos)\r
+\r
+#define   USB_DCFG_Ena32KHzS_Pos       (3U)\r
+#define   USB_DCFG_Ena32KHzS_Msk       (0x00000001U  << USB_DCFG_Ena32KHzS_Pos)\r
+\r
+#define   USB_DCTL_PWROnPrgDone_Pos    (11U)\r
+#define   USB_DCTL_PWROnPrgDone_Msk    (0x00000001U  << USB_DCTL_PWROnPrgDone_Pos)\r
+\r
+#define   USB_PCGCCTL_ResetAfterSusp_Pos       (8U)\r
+#define   USB_PCGCCTL_ResetAfterSusp_Msk       (0x00000001U  << USB_PCGCCTL_ResetAfterSusp_Pos)\r
+\r
+#define   USB_PCGCCTL_L1_Suspended_Pos         (7U)\r
+#define   USB_PCGCCTL_L1_Suspended_Msk         (0x00000001U  << USB_PCGCCTL_L1_Suspended_Pos)\r
+\r
+#define   USB_PCGCCTL_PhySleep_Pos     (6U)\r
+#define   USB_PCGCCTL_PhySleep_Msk     (0x00000001U  << USB_PCGCCTL_PhySleep_Pos)\r
+\r
+#define   USB_PCGCCTL_Enbl_L1Gating_Pos        (5U)\r
+#define   USB_PCGCCTL_Enbl_L1Gating_Msk        (0x00000001U  << USB_PCGCCTL_Enbl_L1Gating_Pos)\r
+\r
+#define   USB_PCGCCTL_RstPdwnModule_Pos        (3U)\r
+#define   USB_PCGCCTL_RstPdwnModule_Msk        (0x00000001U  << USB_PCGCCTL_RstPdwnModule_Pos)\r
+\r
+#define   USB_PCGCCTL_PwrClmp_Pos      (2U)\r
+#define   USB_PCGCCTL_PwrClmp_Msk      (0x00000001U  << USB_PCGCCTL_PwrClmp_Pos)\r
+\r
+#define   USB_EP_DIEPCTL0_NextEp_Pos   (11U)\r
+#define   USB_EP_DIEPCTL0_NextEp_Msk   (0x0000000FU  << USB_EP_DIEPCTL0_NextEp_Pos)\r
+\r
+#define   USB_EP_DIEPINT0_NYETIntrpt_Pos       (14U)\r
+#define   USB_EP_DIEPINT0_NYETIntrpt_Msk       (0x00000001U  << USB_EP_DIEPINT0_NYETIntrpt_Pos)\r
+\r
+#define   USB_EP_DIEPINT0_NAKIntrpt_Pos        (13U)\r
+#define   USB_EP_DIEPINT0_NAKIntrpt_Msk        (0x00000001U  << USB_EP_DIEPINT0_NAKIntrpt_Pos)\r
+\r
+#define   USB_EP_DIEPINT0_BbleErrIntrpt_Pos    (12U)\r
+#define   USB_EP_DIEPINT0_BbleErrIntrpt_Msk    (0x00000001U  << USB_EP_DIEPINT0_BbleErrIntrpt_Pos)\r
+\r
+#define   USB_EP_DIEPINT0_PktDrpSts_Pos        (11U)\r
+#define   USB_EP_DIEPINT0_PktDrpSts_Msk        (0x00000001U  << USB_EP_DIEPINT0_PktDrpSts_Pos)\r
+\r
+#define   USB_EP_DIEPINT0_TxfifoUndrn_Pos      (8U)\r
+#define   USB_EP_DIEPINT0_TxfifoUndrn_Msk      (0x00000001U  << USB_EP_DIEPINT0_TxfifoUndrn_Pos)\r
+\r
+#define   USB_EP_DIEPINT0_INTknEPMis_Pos       (5U)\r
+#define   USB_EP_DIEPINT0_INTknEPMis_Msk       (0x00000001U  << USB_EP_DIEPINT0_INTknEPMis_Pos)\r
+\r
+#define   USB_EP_DOEPINT0_OutPktErr_Pos        (8U)\r
+#define   USB_EP_DOEPINT0_OutPktErr_Msk        (0x00000001U  << USB_EP_DOEPINT0_OutPktErr_Pos)\r
+\r
+#define   USB_EP_DIEPCTL_INTBULK_NextEp_Pos    (11U)\r
+#define   USB_EP_DIEPCTL_INTBULK_NextEp_Msk    (0x0000000FU  << USB_EP_DIEPCTL_INTBULK_NextEp_Pos)\r
+\r
+#define   USB_EP_DIEPCTL_ISOCONT_NextEp_Pos    (11U)\r
+#define   USB_EP_DIEPCTL_ISOCONT_NextEp_Msk    (0x0000000FU  << USB_EP_DIEPCTL_ISOCONT_NextEp_Pos)\r
+\r
+#define   USB_EP_DIEPINT_NYETIntrpt_Pos        (14U)\r
+#define   USB_EP_DIEPINT_NYETIntrpt_Msk        (0x00000001U  << USB_EP_DIEPINT_NYETIntrpt_Pos)\r
+\r
+#define   USB_EP_DIEPINT_NAKIntrpt_Pos         (13U)\r
+#define   USB_EP_DIEPINT_NAKIntrpt_Msk         (0x00000001U  << USB_EP_DIEPINT_NAKIntrpt_Pos)\r
+\r
+#define   USB_EP_DIEPINT_BbleErrIntrpt_Pos     (12U)\r
+#define   USB_EP_DIEPINT_BbleErrIntrpt_Msk     (0x00000001U  << USB_EP_DIEPINT_BbleErrIntrpt_Pos)\r
+\r
+#define   USB_EP_DIEPINT_PktDrpSts_Pos         (11U)\r
+#define   USB_EP_DIEPINT_PktDrpSts_Msk         (0x00000001U  << USB_EP_DIEPINT_PktDrpSts_Pos)\r
+\r
+#define   USB_EP_DIEPINT_TxfifoUndrn_Pos       (8U)\r
+#define   USB_EP_DIEPINT_TxfifoUndrn_Msk       (0x00000001U  << USB_EP_DIEPINT_TxfifoUndrn_Pos)\r
+\r
+#define   USB_EP_DOEPCTL_INTBULK_NextEp_Pos    (11U)\r
+#define   USB_EP_DOEPCTL_INTBULK_NextEp_Msk    (0x0000000FU  << USB_EP_DOEPCTL_INTBULK_NextEp_Pos)\r
+\r
+#define   USB_EP_DOEPCTL_ISOCONT_NextEp_Pos    (11U)\r
+#define   USB_EP_DOEPCTL_ISOCONT_NextEp_Msk    (0x0000000FU  << USB_EP_DOEPCTL_ISOCONT_NextEp_Pos)\r
+\r
+#define   USB_EP_DOEPINT_OutPktErr_Pos         (8U)\r
+#define   USB_EP_DOEPINT_OutPktErr_Msk         (0x00000001U  << USB_EP_DOEPINT_OutPktErr_Pos)\r
+\r
+#define   USB_CH_HCCHAR_LSpdDev_Pos    (17U)\r
+#define   USB_CH_HCCHAR_LSpdDev_Msk    (0x00000001U  << USB_CH_HCCHAR_LSpdDev_Pos)\r
+\r
+#define   USB_CH_HCTSIZ_SCATGATHER_DoPng_Pos   (31U)\r
+#define   USB_CH_HCTSIZ_SCATGATHER_DoPng_Msk   (0x00000001U  << USB_CH_HCTSIZ_SCATGATHER_DoPng_Pos)\r
+\r
+#define   USB_CH_HCTSIZ_BUFFERMODE_DoPng_Pos   (31U)\r
+#define   USB_CH_HCTSIZ_BUFFERMODE_DoPng_Msk   (0x00000001U  << USB_CH_HCTSIZ_BUFFERMODE_DoPng_Pos)\r
+\r
+#define   VADC_BRSSEL_CHSELG_Pos       (0U)\r
+#define   VADC_BRSSEL_CHSELG_Msk       (0xFFFFFFFFU  << VADC_BRSSEL_CHSELG_Pos)\r
+\r
+\r
+/* ===== OBSELETE - DO NOT USE ANY OF ABOVE ====== */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================              Peripheral memory map             ================ */\r
+/* ================================================================================ */\r
+\r
+#define PPB_BASE                        0xE000E000UL\r
+#define DLR_BASE                        0x50004900UL\r
+#define ERU0_BASE                       0x50004800UL\r
+#define ERU1_BASE                       0x40044000UL\r
+#define GPDMA0_BASE                     0x500142C0UL\r
+#define GPDMA0_CH0_BASE                 0x50014000UL\r
+#define GPDMA0_CH1_BASE                 0x50014058UL\r
+#define GPDMA0_CH2_BASE                 0x500140B0UL\r
+#define GPDMA0_CH3_BASE                 0x50014108UL\r
+#define GPDMA0_CH4_BASE                 0x50014160UL\r
+#define GPDMA0_CH5_BASE                 0x500141B8UL\r
+#define GPDMA0_CH6_BASE                 0x50014210UL\r
+#define GPDMA0_CH7_BASE                 0x50014268UL\r
+#define GPDMA1_BASE                     0x500182C0UL\r
+#define GPDMA1_CH0_BASE                 0x50018000UL\r
+#define GPDMA1_CH1_BASE                 0x50018058UL\r
+#define GPDMA1_CH2_BASE                 0x500180B0UL\r
+#define GPDMA1_CH3_BASE                 0x50018108UL\r
+#define FCE_BASE                        0x50020000UL\r
+#define FCE_KE0_BASE                    0x50020020UL\r
+#define FCE_KE1_BASE                    0x50020040UL\r
+#define FCE_KE2_BASE                    0x50020060UL\r
+#define FCE_KE3_BASE                    0x50020080UL\r
+#define PBA0_BASE                       0x40000000UL\r
+#define PBA1_BASE                       0x48000000UL\r
+#define FLASH0_BASE                     0x58001000UL\r
+#define PREF_BASE                       0x58004000UL\r
+#define PMU0_BASE                       0x58000508UL\r
+#define WDT_BASE                        0x50008000UL\r
+#define RTC_BASE                        0x50004A00UL\r
+#define SCU_CLK_BASE                    0x50004600UL\r
+#define SCU_OSC_BASE                    0x50004700UL\r
+#define SCU_PLL_BASE                    0x50004710UL\r
+#define SCU_GENERAL_BASE                0x50004000UL\r
+#define SCU_INTERRUPT_BASE              0x50004074UL\r
+#define SCU_PARITY_BASE                 0x5000413CUL\r
+#define SCU_TRAP_BASE                   0x50004160UL\r
+#define SCU_HIBERNATE_BASE              0x50004300UL\r
+#define SCU_POWER_BASE                  0x50004200UL\r
+#define SCU_RESET_BASE                  0x50004400UL\r
+#define LEDTS0_BASE                     0x48010000UL\r
+#define SDMMC_BASE                      0x4801C000UL\r
+#define EBU_BASE                        0x58008000UL\r
+#define ETH0_CON_BASE                   0x50004040UL\r
+#define ETH0_BASE                       0x5000C000UL\r
+#define USB0_BASE                       0x50040000UL\r
+#define USB_EP_BASE                   0x50040900UL\r
+#define USB0_EP1_BASE                   0x50040920UL\r
+#define USB0_EP2_BASE                   0x50040940UL\r
+#define USB0_EP3_BASE                   0x50040960UL\r
+#define USB0_EP4_BASE                   0x50040980UL\r
+#define USB0_EP5_BASE                   0x500409A0UL\r
+#define USB0_EP6_BASE                   0x500409C0UL\r
+#define USB0_CH0_BASE                   0x50040500UL\r
+#define USB0_CH1_BASE                   0x50040520UL\r
+#define USB0_CH2_BASE                   0x50040540UL\r
+#define USB0_CH3_BASE                   0x50040560UL\r
+#define USB0_CH4_BASE                   0x50040580UL\r
+#define USB0_CH5_BASE                   0x500405A0UL\r
+#define USB0_CH6_BASE                   0x500405C0UL\r
+#define USB0_CH7_BASE                   0x500405E0UL\r
+#define USB0_CH8_BASE                   0x50040600UL\r
+#define USB0_CH9_BASE                   0x50040620UL\r
+#define USB0_CH10_BASE                  0x50040640UL\r
+#define USB0_CH11_BASE                  0x50040660UL\r
+#define USB0_CH12_BASE                  0x50040680UL\r
+#define USB0_CH13_BASE                  0x500406A0UL\r
+#define USIC0_BASE                      0x40030008UL\r
+#define USIC1_BASE                      0x48020008UL\r
+#define USIC2_BASE                      0x48024008UL\r
+#define USIC0_CH0_BASE                  0x40030000UL\r
+#define USIC0_CH1_BASE                  0x40030200UL\r
+#define USIC1_CH0_BASE                  0x48020000UL\r
+#define USIC1_CH1_BASE                  0x48020200UL\r
+#define USIC2_CH0_BASE                  0x48024000UL\r
+#define USIC2_CH1_BASE                  0x48024200UL\r
+#define CAN_BASE                        0x48014000UL\r
+#define CAN_NODE0_BASE                  0x48014200UL\r
+#define CAN_NODE1_BASE                  0x48014300UL\r
+#define CAN_NODE2_BASE                  0x48014400UL\r
+#define CAN_MO0_BASE                    0x48015000UL\r
+#define CAN_MO1_BASE                    0x48015020UL\r
+#define CAN_MO2_BASE                    0x48015040UL\r
+#define CAN_MO3_BASE                    0x48015060UL\r
+#define CAN_MO4_BASE                    0x48015080UL\r
+#define CAN_MO5_BASE                    0x480150A0UL\r
+#define CAN_MO6_BASE                    0x480150C0UL\r
+#define CAN_MO7_BASE                    0x480150E0UL\r
+#define CAN_MO8_BASE                    0x48015100UL\r
+#define CAN_MO9_BASE                    0x48015120UL\r
+#define CAN_MO10_BASE                   0x48015140UL\r
+#define CAN_MO11_BASE                   0x48015160UL\r
+#define CAN_MO12_BASE                   0x48015180UL\r
+#define CAN_MO13_BASE                   0x480151A0UL\r
+#define CAN_MO14_BASE                   0x480151C0UL\r
+#define CAN_MO15_BASE                   0x480151E0UL\r
+#define CAN_MO16_BASE                   0x48015200UL\r
+#define CAN_MO17_BASE                   0x48015220UL\r
+#define CAN_MO18_BASE                   0x48015240UL\r
+#define CAN_MO19_BASE                   0x48015260UL\r
+#define CAN_MO20_BASE                   0x48015280UL\r
+#define CAN_MO21_BASE                   0x480152A0UL\r
+#define CAN_MO22_BASE                   0x480152C0UL\r
+#define CAN_MO23_BASE                   0x480152E0UL\r
+#define CAN_MO24_BASE                   0x48015300UL\r
+#define CAN_MO25_BASE                   0x48015320UL\r
+#define CAN_MO26_BASE                   0x48015340UL\r
+#define CAN_MO27_BASE                   0x48015360UL\r
+#define CAN_MO28_BASE                   0x48015380UL\r
+#define CAN_MO29_BASE                   0x480153A0UL\r
+#define CAN_MO30_BASE                   0x480153C0UL\r
+#define CAN_MO31_BASE                   0x480153E0UL\r
+#define CAN_MO32_BASE                   0x48015400UL\r
+#define CAN_MO33_BASE                   0x48015420UL\r
+#define CAN_MO34_BASE                   0x48015440UL\r
+#define CAN_MO35_BASE                   0x48015460UL\r
+#define CAN_MO36_BASE                   0x48015480UL\r
+#define CAN_MO37_BASE                   0x480154A0UL\r
+#define CAN_MO38_BASE                   0x480154C0UL\r
+#define CAN_MO39_BASE                   0x480154E0UL\r
+#define CAN_MO40_BASE                   0x48015500UL\r
+#define CAN_MO41_BASE                   0x48015520UL\r
+#define CAN_MO42_BASE                   0x48015540UL\r
+#define CAN_MO43_BASE                   0x48015560UL\r
+#define CAN_MO44_BASE                   0x48015580UL\r
+#define CAN_MO45_BASE                   0x480155A0UL\r
+#define CAN_MO46_BASE                   0x480155C0UL\r
+#define CAN_MO47_BASE                   0x480155E0UL\r
+#define CAN_MO48_BASE                   0x48015600UL\r
+#define CAN_MO49_BASE                   0x48015620UL\r
+#define CAN_MO50_BASE                   0x48015640UL\r
+#define CAN_MO51_BASE                   0x48015660UL\r
+#define CAN_MO52_BASE                   0x48015680UL\r
+#define CAN_MO53_BASE                   0x480156A0UL\r
+#define CAN_MO54_BASE                   0x480156C0UL\r
+#define CAN_MO55_BASE                   0x480156E0UL\r
+#define CAN_MO56_BASE                   0x48015700UL\r
+#define CAN_MO57_BASE                   0x48015720UL\r
+#define CAN_MO58_BASE                   0x48015740UL\r
+#define CAN_MO59_BASE                   0x48015760UL\r
+#define CAN_MO60_BASE                   0x48015780UL\r
+#define CAN_MO61_BASE                   0x480157A0UL\r
+#define CAN_MO62_BASE                   0x480157C0UL\r
+#define CAN_MO63_BASE                   0x480157E0UL\r
+#define VADC_BASE                       0x40004000UL\r
+#define VADC_G0_BASE                    0x40004400UL\r
+#define VADC_G1_BASE                    0x40004800UL\r
+#define VADC_G2_BASE                    0x40004C00UL\r
+#define VADC_G3_BASE                    0x40005000UL\r
+#define DSD_BASE                        0x40008000UL\r
+#define DSD_CH0_BASE                    0x40008100UL\r
+#define DSD_CH1_BASE                    0x40008200UL\r
+#define DSD_CH2_BASE                    0x40008300UL\r
+#define DSD_CH3_BASE                    0x40008400UL\r
+#define DAC_BASE                        0x48018000UL\r
+#define CCU40_BASE                      0x4000C000UL\r
+#define CCU41_BASE                      0x40010000UL\r
+#define CCU42_BASE                      0x40014000UL\r
+#define CCU43_BASE                      0x48004000UL\r
+#define CCU40_CC40_BASE                 0x4000C100UL\r
+#define CCU40_CC41_BASE                 0x4000C200UL\r
+#define CCU40_CC42_BASE                 0x4000C300UL\r
+#define CCU40_CC43_BASE                 0x4000C400UL\r
+#define CCU41_CC40_BASE                 0x40010100UL\r
+#define CCU41_CC41_BASE                 0x40010200UL\r
+#define CCU41_CC42_BASE                 0x40010300UL\r
+#define CCU41_CC43_BASE                 0x40010400UL\r
+#define CCU42_CC40_BASE                 0x40014100UL\r
+#define CCU42_CC41_BASE                 0x40014200UL\r
+#define CCU42_CC42_BASE                 0x40014300UL\r
+#define CCU42_CC43_BASE                 0x40014400UL\r
+#define CCU43_CC40_BASE                 0x48004100UL\r
+#define CCU43_CC41_BASE                 0x48004200UL\r
+#define CCU43_CC42_BASE                 0x48004300UL\r
+#define CCU43_CC43_BASE                 0x48004400UL\r
+#define CCU80_BASE                      0x40020000UL\r
+#define CCU81_BASE                      0x40024000UL\r
+#define CCU80_CC80_BASE                 0x40020100UL\r
+#define CCU80_CC81_BASE                 0x40020200UL\r
+#define CCU80_CC82_BASE                 0x40020300UL\r
+#define CCU80_CC83_BASE                 0x40020400UL\r
+#define CCU81_CC80_BASE                 0x40024100UL\r
+#define CCU81_CC81_BASE                 0x40024200UL\r
+#define CCU81_CC82_BASE                 0x40024300UL\r
+#define CCU81_CC83_BASE                 0x40024400UL\r
+#define POSIF0_BASE                     0x40028000UL\r
+#define POSIF1_BASE                     0x4002C000UL\r
+#define PORT0_BASE                      0x48028000UL\r
+#define PORT1_BASE                      0x48028100UL\r
+#define PORT2_BASE                      0x48028200UL\r
+#define PORT3_BASE                      0x48028300UL\r
+#define PORT4_BASE                      0x48028400UL\r
+#define PORT5_BASE                      0x48028500UL\r
+#define PORT6_BASE                      0x48028600UL\r
+#define PORT14_BASE                     0x48028E00UL\r
+#define PORT15_BASE                     0x48028F00UL\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================             Peripheral declaration             ================ */\r
+/* ================================================================================ */\r
+\r
+#define PPB                             ((PPB_Type                *) PPB_BASE)\r
+#define DLR                             ((DLR_GLOBAL_TypeDef                *) DLR_BASE)\r
+#define ERU0                            ((ERU_GLOBAL_TypeDef                *) ERU0_BASE)\r
+#define ERU1                            ((ERU_GLOBAL_TypeDef                *) ERU1_BASE)\r
+#define GPDMA0                          ((GPDMA0_GLOBAL_TypeDef             *) GPDMA0_BASE)\r
+#define GPDMA0_CH0                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH0_BASE)\r
+#define GPDMA0_CH1                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH1_BASE)\r
+#define GPDMA0_CH2                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH2_BASE)\r
+#define GPDMA0_CH3                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH3_BASE)\r
+#define GPDMA0_CH4                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH4_BASE)\r
+#define GPDMA0_CH5                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH5_BASE)\r
+#define GPDMA0_CH6                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH6_BASE)\r
+#define GPDMA0_CH7                      ((GPDMA0_CH_TypeDef          *) GPDMA0_CH7_BASE)\r
+#define GPDMA1                          ((GPDMA1_GLOBAL_TypeDef             *) GPDMA1_BASE)\r
+#define GPDMA1_CH0                      ((GPDMA1_CH_TypeDef          *) GPDMA1_CH0_BASE)\r
+#define GPDMA1_CH1                      ((GPDMA1_CH_TypeDef          *) GPDMA1_CH1_BASE)\r
+#define GPDMA1_CH2                      ((GPDMA1_CH_TypeDef          *) GPDMA1_CH2_BASE)\r
+#define GPDMA1_CH3                      ((GPDMA1_CH_TypeDef          *) GPDMA1_CH3_BASE)\r
+#define FCE                             ((FCE_GLOBAL_TypeDef                *) FCE_BASE)\r
+#define FCE_KE0                         ((FCE_KE_TypeDef             *) FCE_KE0_BASE)\r
+#define FCE_KE1                         ((FCE_KE_TypeDef             *) FCE_KE1_BASE)\r
+#define FCE_KE2                         ((FCE_KE_TypeDef             *) FCE_KE2_BASE)\r
+#define FCE_KE3                         ((FCE_KE_TypeDef             *) FCE_KE3_BASE)\r
+#define PBA0                            ((PBA_GLOBAL_TypeDef                *) PBA0_BASE)\r
+#define PBA1                            ((PBA_GLOBAL_TypeDef                *) PBA1_BASE)\r
+#define FLASH0                          ((FLASH0_GLOBAL_TypeDef              *) FLASH0_BASE)\r
+#define PREF                            ((PREF_GLOBAL_TypeDef               *) PREF_BASE)\r
+#define PMU0                            ((PMU0_GLOBAL_TypeDef                *) PMU0_BASE)\r
+#define WDT                             ((WDT_GLOBAL_TypeDef                *) WDT_BASE)\r
+#define RTC                             ((RTC_GLOBAL_TypeDef                *) RTC_BASE)\r
+#define SCU_CLK                         ((SCU_CLK_TypeDef            *) SCU_CLK_BASE)\r
+#define SCU_OSC                         ((SCU_OSC_TypeDef            *) SCU_OSC_BASE)\r
+#define SCU_PLL                         ((SCU_PLL_TypeDef            *) SCU_PLL_BASE)\r
+#define SCU_GENERAL                     ((SCU_GENERAL_TypeDef        *) SCU_GENERAL_BASE)\r
+#define SCU_INTERRUPT                   ((SCU_INTERRUPT_TypeDef      *) SCU_INTERRUPT_BASE)\r
+#define SCU_PARITY                      ((SCU_PARITY_TypeDef         *) SCU_PARITY_BASE)\r
+#define SCU_TRAP                        ((SCU_TRAP_TypeDef           *) SCU_TRAP_BASE)\r
+#define SCU_HIBERNATE                   ((SCU_HIBERNATE_TypeDef      *) SCU_HIBERNATE_BASE)\r
+#define SCU_POWER                       ((SCU_POWER_TypeDef          *) SCU_POWER_BASE)\r
+#define SCU_RESET                       ((SCU_RESET_TypeDef          *) SCU_RESET_BASE)\r
+#define LEDTS0                          ((LEDTS0_GLOBAL_TypeDef              *) LEDTS0_BASE)\r
+#define SDMMC                           ((SDMMC_GLOBAL_TypeDef              *) SDMMC_BASE)\r
+#define EBU                             ((EBU_Type                *) EBU_BASE)\r
+#define ETH0_CON                        ((ETH0_CON_GLOBAL_TypeDef           *) ETH0_CON_BASE)\r
+#define ETH0                            ((ETH_GLOBAL_TypeDef                *) ETH0_BASE)\r
+#define USB0                            ((USB0_GLOBAL_TypeDef                *) USB0_BASE)\r
+#define USB0_EP0                        ((USB0_EP0_TypeDef           *) USB_EP_BASE)\r
+#define USB0_EP1                        ((USB0_EP_TypeDef             *) USB0_EP1_BASE)\r
+#define USB0_EP2                        ((USB0_EP_TypeDef             *) USB0_EP2_BASE)\r
+#define USB0_EP3                        ((USB0_EP_TypeDef             *) USB0_EP3_BASE)\r
+#define USB0_EP4                        ((USB0_EP_TypeDef             *) USB0_EP4_BASE)\r
+#define USB0_EP5                        ((USB0_EP_TypeDef             *) USB0_EP5_BASE)\r
+#define USB0_EP6                        ((USB0_EP_TypeDef             *) USB0_EP6_BASE)\r
+#define USB0_CH0                        ((USB0_CH_TypeDef             *) USB0_CH0_BASE)\r
+#define USB0_CH1                        ((USB0_CH_TypeDef             *) USB0_CH1_BASE)\r
+#define USB0_CH2                        ((USB0_CH_TypeDef             *) USB0_CH2_BASE)\r
+#define USB0_CH3                        ((USB0_CH_TypeDef             *) USB0_CH3_BASE)\r
+#define USB0_CH4                        ((USB0_CH_TypeDef             *) USB0_CH4_BASE)\r
+#define USB0_CH5                        ((USB0_CH_TypeDef             *) USB0_CH5_BASE)\r
+#define USB0_CH6                        ((USB0_CH_TypeDef             *) USB0_CH6_BASE)\r
+#define USB0_CH7                        ((USB0_CH_TypeDef             *) USB0_CH7_BASE)\r
+#define USB0_CH8                        ((USB0_CH_TypeDef             *) USB0_CH8_BASE)\r
+#define USB0_CH9                        ((USB0_CH_TypeDef             *) USB0_CH9_BASE)\r
+#define USB0_CH10                       ((USB0_CH_TypeDef             *) USB0_CH10_BASE)\r
+#define USB0_CH11                       ((USB0_CH_TypeDef             *) USB0_CH11_BASE)\r
+#define USB0_CH12                       ((USB0_CH_TypeDef             *) USB0_CH12_BASE)\r
+#define USB0_CH13                       ((USB0_CH_TypeDef             *) USB0_CH13_BASE)\r
+#define USIC0                           ((USIC_GLOBAL_TypeDef               *) USIC0_BASE)\r
+#define USIC1                           ((USIC_GLOBAL_TypeDef               *) USIC1_BASE)\r
+#define USIC2                           ((USIC_GLOBAL_TypeDef               *) USIC2_BASE)\r
+#define USIC0_CH0                       ((USIC_CH_TypeDef            *) USIC0_CH0_BASE)\r
+#define USIC0_CH1                       ((USIC_CH_TypeDef            *) USIC0_CH1_BASE)\r
+#define USIC1_CH0                       ((USIC_CH_TypeDef            *) USIC1_CH0_BASE)\r
+#define USIC1_CH1                       ((USIC_CH_TypeDef            *) USIC1_CH1_BASE)\r
+#define USIC2_CH0                       ((USIC_CH_TypeDef            *) USIC2_CH0_BASE)\r
+#define USIC2_CH1                       ((USIC_CH_TypeDef            *) USIC2_CH1_BASE)\r
+#define CAN                             ((CAN_GLOBAL_TypeDef                *) CAN_BASE)\r
+#define CAN_NODE0                       ((CAN_NODE_TypeDef           *) CAN_NODE0_BASE)\r
+#define CAN_NODE1                       ((CAN_NODE_TypeDef           *) CAN_NODE1_BASE)\r
+#define CAN_NODE2                       ((CAN_NODE_TypeDef           *) CAN_NODE2_BASE)\r
+#define CAN_MO0                         ((CAN_MO_TypeDef             *) CAN_MO0_BASE)\r
+#define CAN_MO1                         ((CAN_MO_TypeDef             *) CAN_MO1_BASE)\r
+#define CAN_MO2                         ((CAN_MO_TypeDef             *) CAN_MO2_BASE)\r
+#define CAN_MO3                         ((CAN_MO_TypeDef             *) CAN_MO3_BASE)\r
+#define CAN_MO4                         ((CAN_MO_TypeDef             *) CAN_MO4_BASE)\r
+#define CAN_MO5                         ((CAN_MO_TypeDef             *) CAN_MO5_BASE)\r
+#define CAN_MO6                         ((CAN_MO_TypeDef             *) CAN_MO6_BASE)\r
+#define CAN_MO7                         ((CAN_MO_TypeDef             *) CAN_MO7_BASE)\r
+#define CAN_MO8                         ((CAN_MO_TypeDef             *) CAN_MO8_BASE)\r
+#define CAN_MO9                         ((CAN_MO_TypeDef             *) CAN_MO9_BASE)\r
+#define CAN_MO10                        ((CAN_MO_TypeDef             *) CAN_MO10_BASE)\r
+#define CAN_MO11                        ((CAN_MO_TypeDef             *) CAN_MO11_BASE)\r
+#define CAN_MO12                        ((CAN_MO_TypeDef             *) CAN_MO12_BASE)\r
+#define CAN_MO13                        ((CAN_MO_TypeDef             *) CAN_MO13_BASE)\r
+#define CAN_MO14                        ((CAN_MO_TypeDef             *) CAN_MO14_BASE)\r
+#define CAN_MO15                        ((CAN_MO_TypeDef             *) CAN_MO15_BASE)\r
+#define CAN_MO16                        ((CAN_MO_TypeDef             *) CAN_MO16_BASE)\r
+#define CAN_MO17                        ((CAN_MO_TypeDef             *) CAN_MO17_BASE)\r
+#define CAN_MO18                        ((CAN_MO_TypeDef             *) CAN_MO18_BASE)\r
+#define CAN_MO19                        ((CAN_MO_TypeDef             *) CAN_MO19_BASE)\r
+#define CAN_MO20                        ((CAN_MO_TypeDef             *) CAN_MO20_BASE)\r
+#define CAN_MO21                        ((CAN_MO_TypeDef             *) CAN_MO21_BASE)\r
+#define CAN_MO22                        ((CAN_MO_TypeDef             *) CAN_MO22_BASE)\r
+#define CAN_MO23                        ((CAN_MO_TypeDef             *) CAN_MO23_BASE)\r
+#define CAN_MO24                        ((CAN_MO_TypeDef             *) CAN_MO24_BASE)\r
+#define CAN_MO25                        ((CAN_MO_TypeDef             *) CAN_MO25_BASE)\r
+#define CAN_MO26                        ((CAN_MO_TypeDef             *) CAN_MO26_BASE)\r
+#define CAN_MO27                        ((CAN_MO_TypeDef             *) CAN_MO27_BASE)\r
+#define CAN_MO28                        ((CAN_MO_TypeDef             *) CAN_MO28_BASE)\r
+#define CAN_MO29                        ((CAN_MO_TypeDef             *) CAN_MO29_BASE)\r
+#define CAN_MO30                        ((CAN_MO_TypeDef             *) CAN_MO30_BASE)\r
+#define CAN_MO31                        ((CAN_MO_TypeDef             *) CAN_MO31_BASE)\r
+#define CAN_MO32                        ((CAN_MO_TypeDef             *) CAN_MO32_BASE)\r
+#define CAN_MO33                        ((CAN_MO_TypeDef             *) CAN_MO33_BASE)\r
+#define CAN_MO34                        ((CAN_MO_TypeDef             *) CAN_MO34_BASE)\r
+#define CAN_MO35                        ((CAN_MO_TypeDef             *) CAN_MO35_BASE)\r
+#define CAN_MO36                        ((CAN_MO_TypeDef             *) CAN_MO36_BASE)\r
+#define CAN_MO37                        ((CAN_MO_TypeDef             *) CAN_MO37_BASE)\r
+#define CAN_MO38                        ((CAN_MO_TypeDef             *) CAN_MO38_BASE)\r
+#define CAN_MO39                        ((CAN_MO_TypeDef             *) CAN_MO39_BASE)\r
+#define CAN_MO40                        ((CAN_MO_TypeDef             *) CAN_MO40_BASE)\r
+#define CAN_MO41                        ((CAN_MO_TypeDef             *) CAN_MO41_BASE)\r
+#define CAN_MO42                        ((CAN_MO_TypeDef             *) CAN_MO42_BASE)\r
+#define CAN_MO43                        ((CAN_MO_TypeDef             *) CAN_MO43_BASE)\r
+#define CAN_MO44                        ((CAN_MO_TypeDef             *) CAN_MO44_BASE)\r
+#define CAN_MO45                        ((CAN_MO_TypeDef             *) CAN_MO45_BASE)\r
+#define CAN_MO46                        ((CAN_MO_TypeDef             *) CAN_MO46_BASE)\r
+#define CAN_MO47                        ((CAN_MO_TypeDef             *) CAN_MO47_BASE)\r
+#define CAN_MO48                        ((CAN_MO_TypeDef             *) CAN_MO48_BASE)\r
+#define CAN_MO49                        ((CAN_MO_TypeDef             *) CAN_MO49_BASE)\r
+#define CAN_MO50                        ((CAN_MO_TypeDef             *) CAN_MO50_BASE)\r
+#define CAN_MO51                        ((CAN_MO_TypeDef             *) CAN_MO51_BASE)\r
+#define CAN_MO52                        ((CAN_MO_TypeDef             *) CAN_MO52_BASE)\r
+#define CAN_MO53                        ((CAN_MO_TypeDef             *) CAN_MO53_BASE)\r
+#define CAN_MO54                        ((CAN_MO_TypeDef             *) CAN_MO54_BASE)\r
+#define CAN_MO55                        ((CAN_MO_TypeDef             *) CAN_MO55_BASE)\r
+#define CAN_MO56                        ((CAN_MO_TypeDef             *) CAN_MO56_BASE)\r
+#define CAN_MO57                        ((CAN_MO_TypeDef             *) CAN_MO57_BASE)\r
+#define CAN_MO58                        ((CAN_MO_TypeDef             *) CAN_MO58_BASE)\r
+#define CAN_MO59                        ((CAN_MO_TypeDef             *) CAN_MO59_BASE)\r
+#define CAN_MO60                        ((CAN_MO_TypeDef             *) CAN_MO60_BASE)\r
+#define CAN_MO61                        ((CAN_MO_TypeDef             *) CAN_MO61_BASE)\r
+#define CAN_MO62                        ((CAN_MO_TypeDef             *) CAN_MO62_BASE)\r
+#define CAN_MO63                        ((CAN_MO_TypeDef             *) CAN_MO63_BASE)\r
+#define VADC                            ((VADC_GLOBAL_TypeDef               *) VADC_BASE)\r
+#define VADC_G0                         ((VADC_G_TypeDef             *) VADC_G0_BASE)\r
+#define VADC_G1                         ((VADC_G_TypeDef             *) VADC_G1_BASE)\r
+#define VADC_G2                         ((VADC_G_TypeDef             *) VADC_G2_BASE)\r
+#define VADC_G3                         ((VADC_G_TypeDef             *) VADC_G3_BASE)\r
+#define DSD                             ((DSD_GLOBAL_TypeDef                *) DSD_BASE)\r
+#define DSD_CH0                         ((DSD_CH_TypeDef             *) DSD_CH0_BASE)\r
+#define DSD_CH1                         ((DSD_CH_TypeDef             *) DSD_CH1_BASE)\r
+#define DSD_CH2                         ((DSD_CH_TypeDef             *) DSD_CH2_BASE)\r
+#define DSD_CH3                         ((DSD_CH_TypeDef             *) DSD_CH3_BASE)\r
+#define DAC                             ((DAC_GLOBAL_TypeDef                *) DAC_BASE)\r
+#define CCU40                           ((CCU4_GLOBAL_TypeDef               *) CCU40_BASE)\r
+#define CCU41                           ((CCU4_GLOBAL_TypeDef               *) CCU41_BASE)\r
+#define CCU42                           ((CCU4_GLOBAL_TypeDef               *) CCU42_BASE)\r
+#define CCU43                           ((CCU4_GLOBAL_TypeDef               *) CCU43_BASE)\r
+#define CCU40_CC40                      ((CCU4_CC4_TypeDef           *) CCU40_CC40_BASE)\r
+#define CCU40_CC41                      ((CCU4_CC4_TypeDef           *) CCU40_CC41_BASE)\r
+#define CCU40_CC42                      ((CCU4_CC4_TypeDef           *) CCU40_CC42_BASE)\r
+#define CCU40_CC43                      ((CCU4_CC4_TypeDef           *) CCU40_CC43_BASE)\r
+#define CCU41_CC40                      ((CCU4_CC4_TypeDef           *) CCU41_CC40_BASE)\r
+#define CCU41_CC41                      ((CCU4_CC4_TypeDef           *) CCU41_CC41_BASE)\r
+#define CCU41_CC42                      ((CCU4_CC4_TypeDef           *) CCU41_CC42_BASE)\r
+#define CCU41_CC43                      ((CCU4_CC4_TypeDef           *) CCU41_CC43_BASE)\r
+#define CCU42_CC40                      ((CCU4_CC4_TypeDef           *) CCU42_CC40_BASE)\r
+#define CCU42_CC41                      ((CCU4_CC4_TypeDef           *) CCU42_CC41_BASE)\r
+#define CCU42_CC42                      ((CCU4_CC4_TypeDef           *) CCU42_CC42_BASE)\r
+#define CCU42_CC43                      ((CCU4_CC4_TypeDef           *) CCU42_CC43_BASE)\r
+#define CCU43_CC40                      ((CCU4_CC4_TypeDef           *) CCU43_CC40_BASE)\r
+#define CCU43_CC41                      ((CCU4_CC4_TypeDef           *) CCU43_CC41_BASE)\r
+#define CCU43_CC42                      ((CCU4_CC4_TypeDef           *) CCU43_CC42_BASE)\r
+#define CCU43_CC43                      ((CCU4_CC4_TypeDef           *) CCU43_CC43_BASE)\r
+#define CCU80                           ((CCU8_GLOBAL_TypeDef               *) CCU80_BASE)\r
+#define CCU81                           ((CCU8_GLOBAL_TypeDef               *) CCU81_BASE)\r
+#define CCU80_CC80                      ((CCU8_CC8_TypeDef           *) CCU80_CC80_BASE)\r
+#define CCU80_CC81                      ((CCU8_CC8_TypeDef           *) CCU80_CC81_BASE)\r
+#define CCU80_CC82                      ((CCU8_CC8_TypeDef           *) CCU80_CC82_BASE)\r
+#define CCU80_CC83                      ((CCU8_CC8_TypeDef           *) CCU80_CC83_BASE)\r
+#define CCU81_CC80                      ((CCU8_CC8_TypeDef           *) CCU81_CC80_BASE)\r
+#define CCU81_CC81                      ((CCU8_CC8_TypeDef           *) CCU81_CC81_BASE)\r
+#define CCU81_CC82                      ((CCU8_CC8_TypeDef           *) CCU81_CC82_BASE)\r
+#define CCU81_CC83                      ((CCU8_CC8_TypeDef           *) CCU81_CC83_BASE)\r
+#define POSIF0                          ((POSIF_GLOBAL_TypeDef              *) POSIF0_BASE)\r
+#define POSIF1                          ((POSIF_GLOBAL_TypeDef              *) POSIF1_BASE)\r
+#define PORT0                           ((PORT0_Type              *) PORT0_BASE)\r
+#define PORT1                           ((PORT1_Type              *) PORT1_BASE)\r
+#define PORT2                           ((PORT2_Type              *) PORT2_BASE)\r
+#define PORT3                           ((PORT3_Type              *) PORT3_BASE)\r
+#define PORT4                           ((PORT4_Type              *) PORT4_BASE)\r
+#define PORT5                           ((PORT5_Type              *) PORT5_BASE)\r
+#define PORT6                           ((PORT6_Type              *) PORT6_BASE)\r
+#define PORT14                          ((PORT14_Type             *) PORT14_BASE)\r
+#define PORT15                          ((PORT15_Type             *) PORT15_BASE)\r
+\r
+\r
+/** @} */ /* End of group Device_Peripheral_Registers */\r
+/** @} */ /* End of group XMC4500 */\r
+/** @} */ /* End of group Infineon */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif  /* XMC4500_H */\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/low_level_init.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/low_level_init.c
deleted file mode 100644 (file)
index c243c36..0000000
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/low_level_init.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/**************************************************\r
- *\r
- * This module contains the function `__low_level_init', a function\r
- * that is called before the `main' function of the program.  Normally\r
- * low-level initializations - such as setting the prefered interrupt\r
- * level or setting the watchdog - can be performed here.\r
- *\r
- * Note that this function is called before the data segments are\r
- * initialized, this means that this function cannot rely on the\r
- * values of global or static variables.\r
- *\r
- * When this function returns zero, the startup code will inhibit the\r
- * initialization of the data segments. The result is faster startup,\r
- * the drawback is that neither global nor static data will be\r
- * initialized.\r
- *\r
- * Copyright 1999-2004 IAR Systems. All rights reserved.\r
- *\r
- * $Revision: 50082 $\r
- *\r
- **************************************************/\r
-\r
- \r
- \r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-#include "System_XMC4500.h"\r
-\r
-#pragma language=extended\r
-\r
-__interwork int __low_level_init(void);\r
-\r
-__interwork int __low_level_init(void)\r
-{\r
-  /*==================================*/\r
-  /*  Initialize hardware.            */\r
-  /*==================================*/\r
-\r
-  /*==================================*/\r
-  /* Choose if segment initialization */\r
-  /* should be done or not.           */\r
-  /* Return: 0 to omit seg_init       */\r
-  /*         1 to run seg_init        */\r
-  /*==================================*/\r
-  \r
-  \r
-  /* Init clock Sys clk 96MHz, MCU clk 96MHz, PB clk 48MHz */\r
-  SystemInit();\r
-  \r
-  \r
-  return 1;\r
-}\r
-\r
-#pragma language=default\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4200.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4200.s
new file mode 100644 (file)
index 0000000..3d2213c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4200.s
@@ -0,0 +1,358 @@
+/*****************************************************************************/\r
+/* Startup_XMC4200.s: Startup file for XMC4200 device series for EWARM                */\r
+/*****************************************************************************/\r
+/*\r
+* @file     Startup_XMC4200.s\r
+*           XMC4000 Device Series\r
+* @version  V1.0\r
+* @date     Jan 2013\r
+*\r
+* Copyright (C) 2012 IAR Systems. All rights reserved.\r
+* Copyright (C) 2012 Infineon Technologies AG. All rights reserved.\r
+*\r
+*\r
+* @par\r
+* Infineon Technologies AG (Infineon) is supplying this software for use with\r
+* Infineon's microcontrollers.  This file can be freely distributed\r
+* within development tools that are supporting such microcontrollers.\r
+*\r
+* @par\r
+* THIS SOFTWARE IS PROVIDED AS IS.  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+*\r
+******************************************************************************/\r
+/* ********************* Version History *********************************** */\r
+/* ***************************************************************************\r
+V1.0 January, 30 2013:  In ths version a workoraound for the erratum PMU_CM.001\r
+is implmented (patch for the Exception and interrupt handlers)\r
+\r
+**************************************************************************** */\r
+\r
+        MODULE  ?vector_table\r
+\r
+        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE\r
+        PRESERVE8\r
+\r
+\r
+        ;; Forward declaration of sections.\r
+        SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+        SECTION .intvec:CODE:NOROOT(2)\r
+\r
+        EXTERN  __iar_program_start\r
+        EXTERN  SystemInit\r
+        PUBLIC  __vector_table\r
+\r
+        DATA\r
+\r
+__iar_init$$done:               ; The vector table is not needed\r
+                                ; until after copy initialization is done\r
+\r
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */\r
+;/*\r
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).\r
+; * A veneer defined below will first be executed which in turn branches to the final\r
+; * exception handler.\r
+; *\r
+; * In addition to defining the veneers, the vector table must for these buggy\r
+; * devices contain the veneers.\r
+; */\r
+\r
+;set WORKAROUND_PMU_CM001 under Options for target\r
+;Initialize varaible WORKAROUND_PMU_CM001 as FALSE\r
+WORKAROUND_PMU_CM001 SET 1\r
+\r
+;/* A macro to setup a vector table entry based on STEP ID */\r
+#ifdef WORKAROUND_PMU_CM001\r
+ExcpVector  macro\r
+            DCD \1_Veneer\r
+            endm\r
+#else\r
+ExcpVector  macro\r
+            DCD \1\r
+            endm\r
+#endif\r
+\r
+;/* A macro to ease definition of the various handlers based on STEP ID */\r
+#ifdef WORKAROUND_PMU_CM001\r
+;/* First define the final exception handler */\r
+ProxyHandler  macro\r
+              PUBWEAK \1\r
+              SECTION .text:CODE:REORDER:NOROOT(1)\r
+\1\r
+              B \1\r
+              endm\r
+;/* And then define a veneer that will branch to the final excp handler */\r
+ProxyHandler_Veneer  macro\r
+              PUBWEAK \1\r
+              SECTION .text:CODE:REORDER:NOROOT(2)\r
+\1\r
+              LDR   R0, =ProxyHandler\r
+              PUSH     {LR}\r
+              BLX   R0\r
+              POP   {PC}\r
+              endm\r
+ ;/* No prefetch bug, hence define only the final exception handler */\r
+#else\r
+ProxyHandler  macro\r
+              PUBWEAK \1\r
+              SECTION .text:CODE:REORDER:NOROOT(1)\r
+\1\r
+              B \1\r
+              endm\r
+#endif\r
+\r
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */\r
+\r
+__vector_table\r
+    DCD   sfe(CSTACK)\r
+    DCD   Reset_Handler                    ; Reset Handler\r
+\r
+    ExcpVector   NMI_Handler                 ; NMI Handler\r
+    ExcpVector   HardFault_Handler           ; Hard Fault Handler\r
+    ExcpVector   MemManage_Handler           ; MPU Fault Handler\r
+    ExcpVector   BusFault_Handler            ; Bus Fault Handler\r
+    ExcpVector   UsageFault_Handler          ; Usage Fault Handler\r
+    DCD   0                           ; Reserved\r
+    DCD   0                           ; Reserved\r
+    DCD   0                           ; Reserved\r
+    DCD   0                           ; Reserved\r
+    DCD          SVC_Handler                 ; SVCall Handler\r
+    DCD          DebugMon_Handler            ; Debug Monitor Handler\r
+    DCD   0                           ; Reserved\r
+    ExcpVector   PendSV_Handler              ; PendSV Handler\r
+    DCD          SysTick_Handler             ; SysTick Handler\r
+\r
+    ; Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals\r
+    ExcpVector   SCU_0_IRQHandler            ; Handler name for SR SCU_0\r
+    ExcpVector   ERU0_0_IRQHandler           ; Handler name for SR ERU0_0\r
+    ExcpVector   ERU0_1_IRQHandler           ; Handler name for SR ERU0_1\r
+    ExcpVector   ERU0_2_IRQHandler           ; Handler name for SR ERU0_2\r
+    ExcpVector   ERU0_3_IRQHandler           ; Handler name for SR ERU0_3\r
+    ExcpVector   ERU1_0_IRQHandler           ; Handler name for SR ERU1_0\r
+    ExcpVector   ERU1_1_IRQHandler           ; Handler name for SR ERU1_1\r
+    ExcpVector   ERU1_2_IRQHandler           ; Handler name for SR ERU1_2\r
+    ExcpVector   ERU1_3_IRQHandler           ; Handler name for SR ERU1_3\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   PMU0_0_IRQHandler           ; Handler name for SR PMU0_0\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   VADC0_C0_0_IRQHandler       ; Handler name for SR VADC0_C0_0\r
+    ExcpVector   VADC0_C0_1_IRQHandler       ; Handler name for SR VADC0_C0_1\r
+    ExcpVector   VADC0_C0_2_IRQHandler       ; Handler name for SR VADC0_C0_1\r
+    ExcpVector   VADC0_C0_3_IRQHandler       ; Handler name for SR VADC0_C0_3\r
+    ExcpVector   VADC0_G0_0_IRQHandler       ; Handler name for SR VADC0_G0_0\r
+    ExcpVector   VADC0_G0_1_IRQHandler       ; Handler name for SR VADC0_G0_1\r
+    ExcpVector   VADC0_G0_2_IRQHandler       ; Handler name for SR VADC0_G0_2\r
+    ExcpVector   VADC0_G0_3_IRQHandler       ; Handler name for SR VADC0_G0_3\r
+    ExcpVector   VADC0_G1_0_IRQHandler       ; Handler name for SR VADC0_G1_0\r
+    ExcpVector   VADC0_G1_1_IRQHandler       ; Handler name for SR VADC0_G1_1\r
+    ExcpVector   VADC0_G1_2_IRQHandler       ; Handler name for SR VADC0_G1_2\r
+    ExcpVector   VADC0_G1_3_IRQHandler       ; Handler name for SR VADC0_G1_3\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   DAC0_0_IRQHandler           ; Handler name for SR DAC0_0\r
+    ExcpVector   DAC0_1_IRQHandler           ; Handler name for SR DAC0_1\r
+    ExcpVector   CCU40_0_IRQHandler          ; Handler name for SR CCU40_0\r
+    ExcpVector   CCU40_1_IRQHandler          ; Handler name for SR CCU40_1\r
+    ExcpVector   CCU40_2_IRQHandler          ; Handler name for SR CCU40_2\r
+    ExcpVector   CCU40_3_IRQHandler          ; Handler name for SR CCU40_3\r
+    ExcpVector   CCU41_0_IRQHandler          ; Handler name for SR CCU41_0\r
+    ExcpVector   CCU41_1_IRQHandler          ; Handler name for SR CCU41_1\r
+    ExcpVector   CCU41_2_IRQHandler          ; Handler name for SR CCU41_2\r
+    ExcpVector   CCU41_3_IRQHandler          ; Handler name for SR CCU41_3\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   CCU80_0_IRQHandler          ; Handler name for SR CCU80_0\r
+    ExcpVector   CCU80_1_IRQHandler          ; Handler name for SR CCU80_1\r
+    ExcpVector   CCU80_2_IRQHandler          ; Handler name for SR CCU80_2\r
+    ExcpVector   CCU80_3_IRQHandler          ; Handler name for SR CCU80_3\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   POSIF0_0_IRQHandler         ; Handler name for SR POSIF0_0\r
+    ExcpVector   POSIF0_1_IRQHandler         ; Handler name for SR POSIF0_1\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   HRPWM_0_IRQHandler          ; Handler name for SR HRPWM_0\r
+    ExcpVector   HRPWM_1_IRQHandler          ; Handler name for SR HRPWM_1\r
+    ExcpVector   HRPWM_2_IRQHandler          ; Handler name for SR HRPWM_2\r
+    ExcpVector   HRPWM_3_IRQHandler          ; Handler name for SR HRPWM_3\r
+    ExcpVector   CAN0_0_IRQHandler           ; Handler name for SR CAN0_0\r
+    ExcpVector   CAN0_1_IRQHandler           ; Handler name for SR CAN0_1\r
+    ExcpVector   CAN0_2_IRQHandler           ; Handler name for SR CAN0_2\r
+    ExcpVector   CAN0_3_IRQHandler           ; Handler name for SR CAN0_3\r
+    ExcpVector   CAN0_4_IRQHandler           ; Handler name for SR CAN0_4\r
+    ExcpVector   CAN0_5_IRQHandler           ; Handler name for SR CAN0_5\r
+    ExcpVector   CAN0_6_IRQHandler           ; Handler name for SR CAN0_6\r
+    ExcpVector   CAN0_7_IRQHandler           ; Handler name for SR CAN0_7\r
+    ExcpVector   USIC0_0_IRQHandler          ; Handler name for SR USIC0_0\r
+    ExcpVector   USIC0_1_IRQHandler          ; Handler name for SR USIC0_1\r
+    ExcpVector   USIC0_2_IRQHandler          ; Handler name for SR USIC0_2\r
+    ExcpVector   USIC0_3_IRQHandler          ; Handler name for SR USIC0_3\r
+    ExcpVector   USIC0_4_IRQHandler          ; Handler name for SR USIC0_4\r
+    ExcpVector   USIC0_5_IRQHandler          ; Handler name for SR USIC0_5\r
+    ExcpVector   USIC1_0_IRQHandler          ; Handler name for SR USIC1_0\r
+    ExcpVector   USIC1_1_IRQHandler          ; Handler name for SR USIC1_1\r
+    ExcpVector   USIC1_2_IRQHandler          ; Handler name for SR USIC1_2\r
+    ExcpVector   USIC1_3_IRQHandler          ; Handler name for SR USIC1_3\r
+    ExcpVector   USIC1_4_IRQHandler          ; Handler name for SR USIC1_4\r
+    ExcpVector   USIC1_5_IRQHandler          ; Handler name for SR USIC1_5\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   LEDTS0_0_IRQHandler         ; Handler name for SR LEDTS0_0\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   FCE0_0_IRQHandler           ; Handler name for SR FCE0_0\r
+    ExcpVector   GPDMA0_0_IRQHandler         ; Handler name for SR GPDMA0_0\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   USB0_0_IRQHandler           ; Handler name for SR USB0_0\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+        THUMB\r
+        PUBWEAK Reset_Handler\r
+        SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+\r
+        LDR     R0, =SystemInit\r
+        BLX     R0\r
+        LDR     R0, =SystemInit_DAVE3\r
+        BLX     R0\r
+        LDR     R0, =__iar_program_start\r
+        BX      R0\r
+\r
+\r
+        ProxyHandler NMI_Handler\r
+        ProxyHandler HardFault_Handler\r
+        ProxyHandler MemManage_Handler\r
+        ProxyHandler BusFault_Handler\r
+        ProxyHandler UsageFault_Handler\r
+        ProxyHandler SVC_Handler\r
+        ProxyHandler DebugMon_Handler\r
+        ProxyHandler PendSV_Handler\r
+        ProxyHandler SysTick_Handler\r
+\r
+        ProxyHandler SCU_0_IRQHandler\r
+        ProxyHandler ERU0_0_IRQHandler\r
+        ProxyHandler ERU0_1_IRQHandler\r
+        ProxyHandler ERU0_2_IRQHandler\r
+        ProxyHandler ERU0_3_IRQHandler\r
+        ProxyHandler ERU1_0_IRQHandler\r
+        ProxyHandler ERU1_1_IRQHandler\r
+        ProxyHandler ERU1_2_IRQHandler\r
+        ProxyHandler ERU1_3_IRQHandler\r
+        ProxyHandler PMU0_0_IRQHandler\r
+        ProxyHandler VADC0_C0_0_IRQHandler\r
+        ProxyHandler VADC0_C0_1_IRQHandler\r
+        ProxyHandler VADC0_C0_2_IRQHandler\r
+        ProxyHandler VADC0_C0_3_IRQHandler\r
+        ProxyHandler VADC0_G0_0_IRQHandler\r
+        ProxyHandler VADC0_G0_1_IRQHandler\r
+        ProxyHandler VADC0_G0_2_IRQHandler\r
+        ProxyHandler VADC0_G0_3_IRQHandler\r
+        ProxyHandler VADC0_G1_0_IRQHandler\r
+        ProxyHandler VADC0_G1_1_IRQHandler\r
+        ProxyHandler VADC0_G1_2_IRQHandler\r
+        ProxyHandler VADC0_G1_3_IRQHandler\r
+        ProxyHandler DAC0_0_IRQHandler\r
+        ProxyHandler DAC0_1_IRQHandler\r
+        ProxyHandler CCU40_0_IRQHandler\r
+        ProxyHandler CCU40_1_IRQHandler\r
+        ProxyHandler CCU40_2_IRQHandler\r
+        ProxyHandler CCU40_3_IRQHandler\r
+        ProxyHandler CCU41_0_IRQHandler\r
+        ProxyHandler CCU41_1_IRQHandler\r
+        ProxyHandler CCU41_2_IRQHandler\r
+        ProxyHandler CCU41_3_IRQHandler\r
+        ProxyHandler CCU80_0_IRQHandler\r
+        ProxyHandler CCU80_1_IRQHandler\r
+        ProxyHandler CCU80_2_IRQHandler\r
+        ProxyHandler CCU80_3_IRQHandler\r
+        ProxyHandler POSIF0_0_IRQHandler\r
+        ProxyHandler POSIF0_1_IRQHandler\r
+        ProxyHandler HRPWM_0_IRQHandler\r
+        ProxyHandler HRPWM_1_IRQHandler\r
+        ProxyHandler HRPWM_2_IRQHandler\r
+        ProxyHandler HRPWM_3_IRQHandler\r
+        ProxyHandler CAN0_0_IRQHandler\r
+        ProxyHandler CAN0_1_IRQHandler\r
+        ProxyHandler CAN0_2_IRQHandler\r
+        ProxyHandler CAN0_3_IRQHandler\r
+        ProxyHandler CAN0_4_IRQHandler\r
+        ProxyHandler CAN0_5_IRQHandler\r
+        ProxyHandler CAN0_6_IRQHandler\r
+        ProxyHandler CAN0_7_IRQHandler\r
+        ProxyHandler USIC0_0_IRQHandler\r
+        ProxyHandler USIC0_1_IRQHandler\r
+        ProxyHandler USIC0_2_IRQHandler\r
+        ProxyHandler USIC0_3_IRQHandler\r
+        ProxyHandler USIC0_4_IRQHandler\r
+        ProxyHandler USIC0_5_IRQHandler\r
+        ProxyHandler USIC1_0_IRQHandler\r
+        ProxyHandler USIC1_1_IRQHandler\r
+        ProxyHandler USIC1_2_IRQHandler\r
+        ProxyHandler USIC1_3_IRQHandler\r
+        ProxyHandler USIC1_4_IRQHandler\r
+        ProxyHandler USIC1_5_IRQHandler\r
+        ProxyHandler LEDTS0_0_IRQHandler\r
+        ProxyHandler FCE0_0_IRQHandler\r
+        ProxyHandler GPDMA0_0_IRQHandler\r
+        ProxyHandler USB0_0_IRQHandler\r
+\r
+; Definition of the default weak SystemInit_DAVE3 function for DAVE3 system init.\r
+        PUBWEAK SystemInit_DAVE3\r
+        SECTION .text:CODE:REORDER:NOROOT(2)\r
+SystemInit_DAVE3\r
+        NOP\r
+        BX LR\r
+\r
+; Definition of the default weak DAVE3 function for clock App usage.\r
+; AllowPLLInitByStartup Handler\r
+        PUBWEAK AllowPLLInitByStartup\r
+        SECTION .text:CODE:REORDER:NOROOT(2)\r
+AllowPLLInitByStartup\r
+        MOV R0,#1\r
+        BX LR\r
+\r
+PREF_PCON       EQU 0x58004000\r
+SCU_GCU_PEEN    EQU 0x5000413C\r
+SCU_GCU_PEFLAG  EQU 0x50004150\r
+\r
+\r
+        END\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4400.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4400.s
new file mode 100644 (file)
index 0000000..889194c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4400.s
@@ -0,0 +1,391 @@
+/*****************************************************************************/\r
+/* Startup_XMC4400.s: Startup file for XMC4400 device series for EWARM                */\r
+/*****************************************************************************/\r
+/**\r
+* @file     Startup_XMC4400.s\r
+*           XMC4000 Device Series\r
+* @version  V1.0\r
+* @date     Jan 2013\r
+*\r
+* Copyright (C) 2012 IAR Systems. All rights reserved.\r
+* Copyright (C) 2012 Infineon Technologies AG. All rights reserved.\r
+*\r
+*\r
+* @par\r
+* Infineon Technologies AG (Infineon) is supplying this software for use with\r
+* Infineon's microcontrollers.  This file can be freely distributed\r
+* within development tools that are supporting such microcontrollers.\r
+*\r
+* @par\r
+* THIS SOFTWARE IS PROVIDED AS IS.  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+*\r
+******************************************************************************/\r
+/* ********************* Version History *********************************** */\r
+/* ***************************************************************************\r
+V1.0 January, 30 2013:  In ths version a workoraound for the erratum PMU_CM.001\r
+is implmented (patch for the Exception and interrupt handlers)\r
+\r
+**************************************************************************** */\r
+\r
+        MODULE  ?vector_table\r
+\r
+        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE\r
+        PRESERVE8\r
+\r
+\r
+        ;; Forward declaration of sections.\r
+        SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+        SECTION .intvec:CODE:NOROOT(2)\r
+\r
+        EXTERN  __iar_program_start\r
+        EXTERN  SystemInit\r
+        PUBLIC  __vector_table\r
+\r
+        DATA\r
+\r
+__iar_init$$done:               ; The vector table is not needed\r
+                                ; until after copy initialization is done\r
+\r
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */\r
+;/*\r
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).\r
+; * A veneer defined below will first be executed which in turn branches to the final\r
+; * exception handler.\r
+; *\r
+; * In addition to defining the veneers, the vector table must for these buggy\r
+; * devices contain the veneers.\r
+; */\r
+\r
+;set WORKAROUND_PMU_CM001 under Options for target\r
+;Initialize varaible WORKAROUND_PMU_CM001 as FALSE\r
+WORKAROUND_PMU_CM001 SET 1\r
+\r
+;/* A macro to setup a vector table entry based on STEP ID */\r
+#ifdef WORKAROUND_PMU_CM001\r
+ExcpVector  macro\r
+            DCD \1_Veneer\r
+            endm\r
+#else\r
+ExcpVector  macro\r
+            DCD \1\r
+            endm\r
+#endif\r
+\r
+;/* A macro to ease definition of the various handlers based on STEP ID */\r
+#ifdef WORKAROUND_PMU_CM001\r
+;/* First define the final exception handler */\r
+ProxyHandler  macro\r
+              PUBWEAK \1\r
+              SECTION .text:CODE:REORDER:NOROOT(1)\r
+\1\r
+              B \1\r
+              endm\r
+;/* And then define a veneer that will branch to the final excp handler */\r
+ProxyHandler_Veneer  macro\r
+              PUBWEAK \1\r
+              SECTION .text:CODE:REORDER:NOROOT(2)\r
+\1\r
+              LDR   R0, =ProxyHandler\r
+              PUSH     {LR}\r
+              BLX   R0\r
+              POP   {PC}\r
+              endm\r
+ ;/* No prefetch bug, hence define only the final exception handler */\r
+#else\r
+ProxyHandler  macro\r
+              PUBWEAK \1\r
+              SECTION .text:CODE:REORDER:NOROOT(1)\r
+\1\r
+              B \1\r
+              endm\r
+#endif\r
+\r
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */\r
+\r
+__vector_table\r
+    DCD   sfe(CSTACK)\r
+    DCD   Reset_Handler                    ; Reset Handler\r
+\r
+    ExcpVector   NMI_Handler                 ; NMI Handler\r
+    ExcpVector   HardFault_Handler           ; Hard Fault Handler\r
+    ExcpVector   MemManage_Handler           ; MPU Fault Handler\r
+    ExcpVector   BusFault_Handler            ; Bus Fault Handler\r
+    ExcpVector   UsageFault_Handler          ; Usage Fault Handler\r
+    DCD   0                           ; Reserved\r
+    DCD   0                           ; Reserved\r
+    DCD   0                           ; Reserved\r
+    DCD   0                           ; Reserved\r
+    DCD          SVC_Handler                 ; SVCall Handler\r
+    ExcpVector   DebugMon_Handler            ; Debug Monitor Handler\r
+    DCD   0                           ; Reserved\r
+    DCD          PendSV_Handler              ; PendSV Handler\r
+    DCD          SysTick_Handler             ; SysTick Handler\r
+\r
+    ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals\r
+         ExcpVector   SCU_0_IRQHandler            ; Handler name for SR SCU_0\r
+    ExcpVector   ERU0_0_IRQHandler           ; Handler name for SR ERU0_0\r
+    ExcpVector   ERU0_1_IRQHandler           ; Handler name for SR ERU0_1\r
+    ExcpVector   ERU0_2_IRQHandler           ; Handler name for SR ERU0_2\r
+    ExcpVector   ERU0_3_IRQHandler           ; Handler name for SR ERU0_3\r
+    ExcpVector   ERU1_0_IRQHandler           ; Handler name for SR ERU1_0\r
+    ExcpVector   ERU1_1_IRQHandler           ; Handler name for SR ERU1_1\r
+    ExcpVector   ERU1_2_IRQHandler           ; Handler name for SR ERU1_2\r
+    ExcpVector   ERU1_3_IRQHandler           ; Handler name for SR ERU1_3\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   PMU0_0_IRQHandler           ; Handler name for SR PMU0_0\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   VADC0_C0_0_IRQHandler       ; Handler name for SR VADC0_C0_0\r
+    ExcpVector   VADC0_C0_1_IRQHandler       ; Handler name for SR VADC0_C0_1\r
+    ExcpVector   VADC0_C0_2_IRQHandler       ; Handler name for SR VADC0_C0_1\r
+    ExcpVector   VADC0_C0_3_IRQHandler       ; Handler name for SR VADC0_C0_3\r
+    ExcpVector   VADC0_G0_0_IRQHandler       ; Handler name for SR VADC0_G0_0\r
+    ExcpVector   VADC0_G0_1_IRQHandler       ; Handler name for SR VADC0_G0_1\r
+    ExcpVector   VADC0_G0_2_IRQHandler       ; Handler name for SR VADC0_G0_2\r
+    ExcpVector   VADC0_G0_3_IRQHandler       ; Handler name for SR VADC0_G0_3\r
+    ExcpVector   VADC0_G1_0_IRQHandler       ; Handler name for SR VADC0_G1_0\r
+    ExcpVector   VADC0_G1_1_IRQHandler       ; Handler name for SR VADC0_G1_1\r
+    ExcpVector   VADC0_G1_2_IRQHandler       ; Handler name for SR VADC0_G1_2\r
+    ExcpVector   VADC0_G1_3_IRQHandler       ; Handler name for SR VADC0_G1_3\r
+    ExcpVector   VADC0_G2_0_IRQHandler       ; Handler name for SR VADC0_G2_0\r
+    ExcpVector   VADC0_G2_1_IRQHandler       ; Handler name for SR VADC0_G2_1\r
+    ExcpVector   VADC0_G2_2_IRQHandler       ; Handler name for SR VADC0_G2_2\r
+    ExcpVector   VADC0_G2_3_IRQHandler       ; Handler name for SR VADC0_G2_3\r
+    ExcpVector   VADC0_G3_0_IRQHandler       ; Handler name for SR VADC0_G3_0\r
+    ExcpVector   VADC0_G3_1_IRQHandler       ; Handler name for SR VADC0_G3_1\r
+    ExcpVector   VADC0_G3_2_IRQHandler       ; Handler name for SR VADC0_G3_2\r
+    ExcpVector   VADC0_G3_3_IRQHandler       ; Handler name for SR VADC0_G3_3\r
+    ExcpVector   DSD0_0_IRQHandler           ; Handler name for SR DSD_SRM_0\r
+    ExcpVector   DSD0_1_IRQHandler           ; Handler name for SR DSD_SRM_1\r
+    ExcpVector   DSD0_2_IRQHandler           ; Handler name for SR DSD_SRM_2\r
+    ExcpVector   DSD0_3_IRQHandler           ; Handler name for SR DSD_SRM_3\r
+    ExcpVector   DSD0_4_IRQHandler           ; Handler name for SR DSD_SRA_0\r
+    ExcpVector   DSD0_5_IRQHandler           ; Handler name for SR DSD_SRA_1\r
+    ExcpVector   DSD0_6_IRQHandler           ; Handler name for SR DSD_SRA_2\r
+    ExcpVector   DSD0_7_IRQHandler           ; Handler name for SR DSD_SRA_3\r
+    ExcpVector   DAC0_0_IRQHandler           ; Handler name for SR DAC0_0\r
+    ExcpVector   DAC0_1_IRQHandler           ; Handler name for SR DAC0_1\r
+    ExcpVector   CCU40_0_IRQHandler          ; Handler name for SR CCU40_0\r
+    ExcpVector   CCU40_1_IRQHandler          ; Handler name for SR CCU40_1\r
+    ExcpVector   CCU40_2_IRQHandler          ; Handler name for SR CCU40_2\r
+    ExcpVector   CCU40_3_IRQHandler          ; Handler name for SR CCU40_3\r
+    ExcpVector   CCU41_0_IRQHandler          ; Handler name for SR CCU41_0\r
+    ExcpVector   CCU41_1_IRQHandler          ; Handler name for SR CCU41_1\r
+    ExcpVector   CCU41_2_IRQHandler          ; Handler name for SR CCU41_2\r
+    ExcpVector   CCU41_3_IRQHandler          ; Handler name for SR CCU41_3\r
+    ExcpVector   CCU42_0_IRQHandler          ; Handler name for SR CCU42_0\r
+    ExcpVector   CCU42_1_IRQHandler          ; Handler name for SR CCU42_1\r
+    ExcpVector   CCU42_2_IRQHandler          ; Handler name for SR CCU42_2\r
+    ExcpVector   CCU42_3_IRQHandler          ; Handler name for SR CCU42_3\r
+    ExcpVector   CCU43_0_IRQHandler          ; Handler name for SR CCU43_0\r
+    ExcpVector   CCU43_1_IRQHandler          ; Handler name for SR CCU43_1\r
+    ExcpVector   CCU43_2_IRQHandler          ; Handler name for SR CCU43_2\r
+    ExcpVector   CCU43_3_IRQHandler          ; Handler name for SR CCU43_3\r
+    ExcpVector   CCU80_0_IRQHandler          ; Handler name for SR CCU80_0\r
+    ExcpVector   CCU80_1_IRQHandler          ; Handler name for SR CCU80_1\r
+    ExcpVector   CCU80_2_IRQHandler          ; Handler name for SR CCU80_2\r
+    ExcpVector   CCU80_3_IRQHandler          ; Handler name for SR CCU80_3\r
+    ExcpVector   CCU81_0_IRQHandler          ; Handler name for SR CCU81_0\r
+    ExcpVector   CCU81_1_IRQHandler          ; Handler name for SR CCU81_1\r
+    ExcpVector   CCU81_2_IRQHandler          ; Handler name for SR CCU81_2\r
+    ExcpVector   CCU81_3_IRQHandler          ; Handler name for SR CCU81_3\r
+    ExcpVector   POSIF0_0_IRQHandler         ; Handler name for SR POSIF0_0\r
+    ExcpVector   POSIF0_1_IRQHandler         ; Handler name for SR POSIF0_1\r
+    ExcpVector   POSIF1_0_IRQHandler         ; Handler name for SR POSIF1_0\r
+    ExcpVector   POSIF1_1_IRQHandler         ; Handler name for SR POSIF1_1\r
+    ExcpVector   HRPWM_0_IRQHandler          ; Handler name for SR HRPWM_0\r
+    ExcpVector   HRPWM_1_IRQHandler          ; Handler name for SR HRPWM_1\r
+    ExcpVector   HRPWM_2_IRQHandler          ; Handler name for SR HRPWM_2\r
+    ExcpVector   HRPWM_3_IRQHandler          ; Handler name for SR HRPWM_3\r
+    ExcpVector   CAN0_0_IRQHandler           ; Handler name for SR CAN0_0\r
+    ExcpVector   CAN0_1_IRQHandler           ; Handler name for SR CAN0_1\r
+    ExcpVector   CAN0_2_IRQHandler           ; Handler name for SR CAN0_2\r
+    ExcpVector   CAN0_3_IRQHandler           ; Handler name for SR CAN0_3\r
+    ExcpVector   CAN0_4_IRQHandler           ; Handler name for SR CAN0_4\r
+    ExcpVector   CAN0_5_IRQHandler           ; Handler name for SR CAN0_5\r
+    ExcpVector   CAN0_6_IRQHandler           ; Handler name for SR CAN0_6\r
+    ExcpVector   CAN0_7_IRQHandler           ; Handler name for SR CAN0_7\r
+    ExcpVector   USIC0_0_IRQHandler          ; Handler name for SR USIC0_0\r
+    ExcpVector   USIC0_1_IRQHandler          ; Handler name for SR USIC0_1\r
+    ExcpVector   USIC0_2_IRQHandler          ; Handler name for SR USIC0_2\r
+    ExcpVector   USIC0_3_IRQHandler          ; Handler name for SR USIC0_3\r
+    ExcpVector   USIC0_4_IRQHandler          ; Handler name for SR USIC0_4\r
+    ExcpVector   USIC0_5_IRQHandler          ; Handler name for SR USIC0_5\r
+    ExcpVector   USIC1_0_IRQHandler          ; Handler name for SR USIC1_0\r
+    ExcpVector   USIC1_1_IRQHandler          ; Handler name for SR USIC1_1\r
+    ExcpVector   USIC1_2_IRQHandler          ; Handler name for SR USIC1_2\r
+    ExcpVector   USIC1_3_IRQHandler          ; Handler name for SR USIC1_3\r
+    ExcpVector   USIC1_4_IRQHandler          ; Handler name for SR USIC1_4\r
+    ExcpVector   USIC1_5_IRQHandler          ; Handler name for SR USIC1_5\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   LEDTS0_0_IRQHandler         ; Handler name for SR LEDTS0_0\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   FCE0_0_IRQHandler           ; Handler name for SR FCE0_0\r
+    ExcpVector   GPDMA0_0_IRQHandler         ; Handler name for SR GPDMA0_0\r
+    DCD   0                           ; Not Available\r
+    ExcpVector   USB0_0_IRQHandler           ; Handler name for SR USB0_0\r
+    ExcpVector   ETH0_0_IRQHandler           ; Handler name for SR ETH0_0\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+    DCD   0                           ; Not Available\r
+\r
+\r
+\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+        THUMB\r
+        PUBWEAK Reset_Handler\r
+        SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+\r
+        LDR     R0, =SystemInit\r
+        BLX     R0\r
+        LDR     R0, =SystemInit_DAVE3\r
+        BLX     R0\r
+        LDR     R0, =__iar_program_start\r
+        BX      R0\r
+\r
+\r
+       ProxyHandler NMI_Handler\r
+       ProxyHandler HardFault_Handler\r
+       ProxyHandler MemManage_Handler\r
+       ProxyHandler BusFault_Handler\r
+       ProxyHandler UsageFault_Handler\r
+       ProxyHandler SVC_Handler\r
+       ProxyHandler DebugMon_Handler\r
+       ProxyHandler PendSV_Handler\r
+       ProxyHandler SysTick_Handler\r
+\r
+       ProxyHandler SCU_0_IRQHandler\r
+       ProxyHandler ERU0_0_IRQHandler\r
+       ProxyHandler ERU0_1_IRQHandler\r
+       ProxyHandler ERU0_2_IRQHandler\r
+       ProxyHandler ERU0_3_IRQHandler\r
+       ProxyHandler ERU1_0_IRQHandler\r
+       ProxyHandler ERU1_1_IRQHandler\r
+       ProxyHandler ERU1_2_IRQHandler\r
+       ProxyHandler ERU1_3_IRQHandler\r
+       ProxyHandler PMU0_0_IRQHandler\r
+       ProxyHandler VADC0_C0_0_IRQHandler\r
+       ProxyHandler VADC0_C0_1_IRQHandler\r
+       ProxyHandler VADC0_C0_2_IRQHandler\r
+       ProxyHandler VADC0_C0_3_IRQHandler\r
+       ProxyHandler VADC0_G0_0_IRQHandler\r
+       ProxyHandler VADC0_G0_1_IRQHandler\r
+       ProxyHandler VADC0_G0_2_IRQHandler\r
+       ProxyHandler VADC0_G0_3_IRQHandler\r
+       ProxyHandler VADC0_G1_0_IRQHandler\r
+       ProxyHandler VADC0_G1_1_IRQHandler\r
+       ProxyHandler VADC0_G1_2_IRQHandler\r
+       ProxyHandler VADC0_G1_3_IRQHandler\r
+       ProxyHandler VADC0_G2_0_IRQHandler\r
+       ProxyHandler VADC0_G2_1_IRQHandler\r
+       ProxyHandler VADC0_G2_2_IRQHandler\r
+       ProxyHandler VADC0_G2_3_IRQHandler\r
+       ProxyHandler VADC0_G3_0_IRQHandler\r
+       ProxyHandler VADC0_G3_1_IRQHandler\r
+       ProxyHandler VADC0_G3_2_IRQHandler\r
+       ProxyHandler VADC0_G3_3_IRQHandler\r
+       ProxyHandler DSD0_0_IRQHandler\r
+       ProxyHandler DSD0_1_IRQHandler\r
+       ProxyHandler DSD0_2_IRQHandler\r
+       ProxyHandler DSD0_3_IRQHandler\r
+       ProxyHandler DSD0_4_IRQHandler\r
+       ProxyHandler DSD0_5_IRQHandler\r
+       ProxyHandler DSD0_6_IRQHandler\r
+       ProxyHandler DSD0_7_IRQHandler\r
+       ProxyHandler DAC0_0_IRQHandler\r
+       ProxyHandler DAC0_1_IRQHandler\r
+       ProxyHandler CCU40_0_IRQHandler\r
+       ProxyHandler CCU40_1_IRQHandler\r
+       ProxyHandler CCU40_2_IRQHandler\r
+       ProxyHandler CCU40_3_IRQHandler\r
+       ProxyHandler CCU41_0_IRQHandler\r
+       ProxyHandler CCU41_1_IRQHandler\r
+       ProxyHandler CCU41_2_IRQHandler\r
+       ProxyHandler CCU41_3_IRQHandler\r
+       ProxyHandler CCU42_0_IRQHandler\r
+       ProxyHandler CCU42_1_IRQHandler\r
+       ProxyHandler CCU42_2_IRQHandler\r
+       ProxyHandler CCU42_3_IRQHandler\r
+       ProxyHandler CCU43_0_IRQHandler\r
+       ProxyHandler CCU43_1_IRQHandler\r
+       ProxyHandler CCU43_2_IRQHandler\r
+       ProxyHandler CCU43_3_IRQHandler\r
+       ProxyHandler CCU80_0_IRQHandler\r
+       ProxyHandler CCU80_1_IRQHandler\r
+       ProxyHandler CCU80_2_IRQHandler\r
+       ProxyHandler CCU80_3_IRQHandler\r
+       ProxyHandler CCU81_0_IRQHandler\r
+       ProxyHandler CCU81_1_IRQHandler\r
+       ProxyHandler CCU81_2_IRQHandler\r
+       ProxyHandler CCU81_3_IRQHandler\r
+       ProxyHandler POSIF0_0_IRQHandler\r
+       ProxyHandler POSIF0_1_IRQHandler\r
+       ProxyHandler POSIF1_0_IRQHandler\r
+       ProxyHandler POSIF1_1_IRQHandler\r
+       ProxyHandler HRPWM_0_IRQHandler\r
+       ProxyHandler HRPWM_1_IRQHandler\r
+       ProxyHandler HRPWM_2_IRQHandler\r
+       ProxyHandler HRPWM_3_IRQHandler\r
+       ProxyHandler CAN0_0_IRQHandler\r
+       ProxyHandler CAN0_1_IRQHandler\r
+       ProxyHandler CAN0_2_IRQHandler\r
+       ProxyHandler CAN0_3_IRQHandler\r
+       ProxyHandler CAN0_4_IRQHandler\r
+       ProxyHandler CAN0_5_IRQHandler\r
+       ProxyHandler CAN0_6_IRQHandler\r
+       ProxyHandler CAN0_7_IRQHandler\r
+       ProxyHandler USIC0_0_IRQHandler\r
+       ProxyHandler USIC0_1_IRQHandler\r
+       ProxyHandler USIC0_2_IRQHandler\r
+       ProxyHandler USIC0_3_IRQHandler\r
+       ProxyHandler USIC0_4_IRQHandler\r
+       ProxyHandler USIC0_5_IRQHandler\r
+       ProxyHandler USIC1_0_IRQHandler\r
+       ProxyHandler USIC1_1_IRQHandler\r
+       ProxyHandler USIC1_2_IRQHandler\r
+       ProxyHandler USIC1_3_IRQHandler\r
+       ProxyHandler USIC1_4_IRQHandler\r
+       ProxyHandler USIC1_5_IRQHandler\r
+       ProxyHandler LEDTS0_0_IRQHandler\r
+       ProxyHandler FCE0_0_IRQHandler\r
+       ProxyHandler GPDMA0_0_IRQHandler\r
+       ProxyHandler USB0_0_IRQHandler\r
+       ProxyHandler ETH0_0_IRQHandler\r
+\r
+; Definition of the default weak SystemInit_DAVE3 function for DAVE3 system init.\r
+        PUBWEAK SystemInit_DAVE3\r
+        SECTION .text:CODE:REORDER:NOROOT(2)\r
+SystemInit_DAVE3\r
+        NOP\r
+        BX LR\r
+\r
+; Definition of the default weak DAVE3 function for clock App usage.\r
+; AllowPLLInitByStartup Handler\r
+        PUBWEAK AllowPLLInitByStartup\r
+        SECTION .text:CODE:REORDER:NOROOT(2)\r
+AllowPLLInitByStartup\r
+        MOV R0,#1\r
+        BX LR\r
+\r
+PREF_PCON       EQU 0x58004000\r
+SCU_GCU_PEEN    EQU 0x5000413C\r
+SCU_GCU_PEFLAG  EQU 0x50004150\r
+\r
+\r
+        END\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4500.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4500.s
new file mode 100644 (file)
index 0000000..72cc4f0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/startup_XMC4500.s
@@ -0,0 +1,397 @@
+/*****************************************************************************/\r
+/* Startup_XMC4500.s: Startup file for XMC4500 device series for EWARM                */\r
+/*****************************************************************************/\r
+/**\r
+* @file     Startup_XMC4500.s\r
+*           XMC4000 Device Series\r
+* @version  V1.0\r
+* @date     Jan 2013\r
+*\r
+* Copyright (C) 2012 IAR Systems. All rights reserved.\r
+* Copyright (C) 2012 Infineon Technologies AG. All rights reserved.\r
+*\r
+*\r
+* @par\r
+* Infineon Technologies AG (Infineon) is supplying this software for use with\r
+* Infineon's microcontrollers.  This file can be freely distributed\r
+* within development tools that are supporting such microcontrollers.\r
+*\r
+* @par\r
+* THIS SOFTWARE IS PROVIDED AS IS.  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+*\r
+******************************************************************************/\r
+/* ********************* Version History *********************************** */\r
+/* ***************************************************************************\r
+V1.0 January, 30 2013:  In ths version a workoraound for the erratum PMU_CM.001\r
+is implmented (patch for the Exception and interrupt handlers)\r
+\r
+**************************************************************************** */\r
+\r
+        MODULE  ?vector_table\r
+\r
+        AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE\r
+        PRESERVE8\r
+\r
+\r
+        ;; Forward declaration of sections.\r
+        SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+        SECTION .intvec:CODE:NOROOT(2)\r
+\r
+        EXTERN  __iar_program_start\r
+        EXTERN  SystemInit\r
+        PUBLIC  __vector_table\r
+\r
+        DATA\r
+\r
+__iar_init$$done:               ; The vector table is not needed\r
+                                ; until after copy initialization is done\r
+\r
+;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */\r
+;/*\r
+; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001).\r
+; * A veneer defined below will first be executed which in turn branches to the final\r
+; * exception handler.\r
+; *\r
+; * In addition to defining the veneers, the vector table must for these buggy\r
+; * devices contain the veneers.\r
+; */\r
+\r
+;set WORKAROUND_PMU_CM001 under Options for target\r
+;Initialize varaible WORKAROUND_PMU_CM001 as TRUE\r
+WORKAROUND_PMU_CM001 SET 1\r
+\r
+;/* A macro to setup a vector table entry based on STEP ID */\r
+#ifdef WORKAROUND_PMU_CM001\r
+ExcpVector  macro\r
+            DCD \1_Veneer\r
+            endm\r
+#else\r
+ExcpVector  macro\r
+            DCD \1\r
+            endm\r
+#endif\r
+\r
+;/* A macro to ease definition of the various handlers based on STEP ID */\r
+#ifdef WORKAROUND_PMU_CM001\r
+;/* First define the final exception handler */\r
+ProxyHandler  macro\r
+              PUBWEAK \1\r
+              SECTION .text:CODE:REORDER:NOROOT(1)\r
+\1\r
+              B \1\r
+              endm\r
+;/* And then define a veneer that will branch to the final excp handler */\r
+ProxyHandler_Veneer  macro\r
+              PUBWEAK \1\r
+              SECTION .text:CODE:REORDER:NOROOT(2)\r
+\1\r
+              LDR   R0, =ProxyHandler\r
+              PUSH     {LR}\r
+              BLX   R0\r
+              POP   {PC}\r
+              endm\r
+ ;/* No prefetch bug, hence define only the final exception handler */\r
+#else\r
+ProxyHandler  macro\r
+              PUBWEAK \1\r
+              SECTION .text:CODE:REORDER:NOROOT(1)\r
+\1\r
+              B \1\r
+              endm\r
+#endif\r
+\r
+;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */\r
+\r
+__vector_table\r
+        DCD     sfe(CSTACK)\r
+        DCD     Reset_Handler\r
+\r
+        ExcpVector     NMI_Handler\r
+        ExcpVector     HardFault_Handler\r
+        ExcpVector     MemManage_Handler\r
+        ExcpVector     BusFault_Handler\r
+        ExcpVector     UsageFault_Handler\r
+        DCD     0\r
+        DCD     0\r
+        DCD     0\r
+        DCD     0\r
+        DCD            SVC_Handler\r
+        ExcpVector     DebugMon_Handler\r
+        DCD     0\r
+        DCD            PendSV_Handler\r
+        DCD            SysTick_Handler\r
+\r
+    ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals\r
+       ExcpVector   SCU_0_IRQHandler            ; Handler name for SR SCU_0\r
+       ExcpVector   ERU0_0_IRQHandler           ; Handler name for SR ERU0_0\r
+       ExcpVector   ERU0_1_IRQHandler           ; Handler name for SR ERU0_1\r
+       ExcpVector   ERU0_2_IRQHandler           ; Handler name for SR ERU0_2\r
+       ExcpVector   ERU0_3_IRQHandler           ; Handler name for SR ERU0_3\r
+       ExcpVector   ERU1_0_IRQHandler           ; Handler name for SR ERU1_0\r
+       ExcpVector   ERU1_1_IRQHandler           ; Handler name for SR ERU1_1\r
+       ExcpVector   ERU1_2_IRQHandler           ; Handler name for SR ERU1_2\r
+       ExcpVector   ERU1_3_IRQHandler           ; Handler name for SR ERU1_3\r
+       DCD   0                           ; Not Available\r
+       DCD   0                           ; Not Available\r
+       DCD   0                           ; Not Available\r
+       ExcpVector   PMU0_0_IRQHandler           ; Handler name for SR PMU0_0\r
+       DCD   0                           ; Handler name for SR PMU0_1\r
+       ExcpVector   VADC0_C0_0_IRQHandler       ; Handler name for SR VADC0_C0_0\r
+       ExcpVector   VADC0_C0_1_IRQHandler       ; Handler name for SR VADC0_C0_1\r
+       ExcpVector   VADC0_C0_2_IRQHandler       ; Handler name for SR VADC0_C0_1\r
+       ExcpVector   VADC0_C0_3_IRQHandler       ; Handler name for SR VADC0_C0_3\r
+       ExcpVector   VADC0_G0_0_IRQHandler       ; Handler name for SR VADC0_G0_0\r
+       ExcpVector   VADC0_G0_1_IRQHandler       ; Handler name for SR VADC0_G0_1\r
+       ExcpVector   VADC0_G0_2_IRQHandler       ; Handler name for SR VADC0_G0_2\r
+       ExcpVector   VADC0_G0_3_IRQHandler       ; Handler name for SR VADC0_G0_3\r
+       ExcpVector   VADC0_G1_0_IRQHandler       ; Handler name for SR VADC0_G1_0\r
+       ExcpVector   VADC0_G1_1_IRQHandler       ; Handler name for SR VADC0_G1_1\r
+       ExcpVector   VADC0_G1_2_IRQHandler       ; Handler name for SR VADC0_G1_2\r
+       ExcpVector   VADC0_G1_3_IRQHandler       ; Handler name for SR VADC0_G1_3\r
+       ExcpVector   VADC0_G2_0_IRQHandler       ; Handler name for SR VADC0_G2_0\r
+       ExcpVector   VADC0_G2_1_IRQHandler       ; Handler name for SR VADC0_G2_1\r
+       ExcpVector   VADC0_G2_2_IRQHandler       ; Handler name for SR VADC0_G2_2\r
+       ExcpVector   VADC0_G2_3_IRQHandler       ; Handler name for SR VADC0_G2_3\r
+       ExcpVector   VADC0_G3_0_IRQHandler       ; Handler name for SR VADC0_G3_0\r
+       ExcpVector   VADC0_G3_1_IRQHandler       ; Handler name for SR VADC0_G3_1\r
+       ExcpVector   VADC0_G3_2_IRQHandler       ; Handler name for SR VADC0_G3_2\r
+       ExcpVector   VADC0_G3_3_IRQHandler       ; Handler name for SR VADC0_G3_3\r
+       ExcpVector   DSD0_0_IRQHandler           ; Handler name for SR DSD0_0\r
+       ExcpVector   DSD0_1_IRQHandler           ; Handler name for SR DSD0_1\r
+       ExcpVector   DSD0_2_IRQHandler           ; Handler name for SR DSD0_2\r
+       ExcpVector   DSD0_3_IRQHandler           ; Handler name for SR DSD0_3\r
+       ExcpVector   DSD0_4_IRQHandler           ; Handler name for SR DSD0_4\r
+       ExcpVector   DSD0_5_IRQHandler           ; Handler name for SR DSD0_5\r
+       ExcpVector   DSD0_6_IRQHandler           ; Handler name for SR DSD0_6\r
+       ExcpVector   DSD0_7_IRQHandler           ; Handler name for SR DSD0_7\r
+       ExcpVector   DAC0_0_IRQHandler           ; Handler name for SR DAC0_0\r
+       ExcpVector   DAC0_1_IRQHandler           ; Handler name for SR DAC0_0\r
+       ExcpVector   CCU40_0_IRQHandler          ; Handler name for SR CCU40_0\r
+       ExcpVector   CCU40_1_IRQHandler          ; Handler name for SR CCU40_1\r
+       ExcpVector   CCU40_2_IRQHandler          ; Handler name for SR CCU40_2\r
+       ExcpVector   CCU40_3_IRQHandler          ; Handler name for SR CCU40_3\r
+       ExcpVector   CCU41_0_IRQHandler          ; Handler name for SR CCU41_0\r
+       ExcpVector   CCU41_1_IRQHandler          ; Handler name for SR CCU41_1\r
+       ExcpVector   CCU41_2_IRQHandler          ; Handler name for SR CCU41_2\r
+       ExcpVector   CCU41_3_IRQHandler          ; Handler name for SR CCU41_3\r
+       ExcpVector   CCU42_0_IRQHandler          ; Handler name for SR CCU42_0\r
+       ExcpVector   CCU42_1_IRQHandler          ; Handler name for SR CCU42_1\r
+       ExcpVector   CCU42_2_IRQHandler          ; Handler name for SR CCU42_2\r
+       ExcpVector   CCU42_3_IRQHandler          ; Handler name for SR CCU42_3\r
+       ExcpVector   CCU43_0_IRQHandler          ; Handler name for SR CCU43_0\r
+       ExcpVector   CCU43_1_IRQHandler          ; Handler name for SR CCU43_1\r
+       ExcpVector   CCU43_2_IRQHandler          ; Handler name for SR CCU43_2\r
+       ExcpVector   CCU43_3_IRQHandler          ; Handler name for SR CCU43_3\r
+       ExcpVector   CCU80_0_IRQHandler          ; Handler name for SR CCU80_0\r
+       ExcpVector   CCU80_1_IRQHandler          ; Handler name for SR CCU80_1\r
+       ExcpVector   CCU80_2_IRQHandler          ; Handler name for SR CCU80_2\r
+       ExcpVector   CCU80_3_IRQHandler          ; Handler name for SR CCU80_3\r
+       ExcpVector   CCU81_0_IRQHandler          ; Handler name for SR CCU81_0\r
+       ExcpVector   CCU81_1_IRQHandler          ; Handler name for SR CCU81_1\r
+       ExcpVector   CCU81_2_IRQHandler          ; Handler name for SR CCU81_2\r
+       ExcpVector   CCU81_3_IRQHandler          ; Handler name for SR CCU81_3\r
+       ExcpVector   POSIF0_0_IRQHandler         ; Handler name for SR POSIF0_0\r
+       ExcpVector   POSIF0_1_IRQHandler         ; Handler name for SR POSIF0_1\r
+       ExcpVector   POSIF1_0_IRQHandler         ; Handler name for SR POSIF1_0\r
+       ExcpVector   POSIF1_1_IRQHandler         ; Handler name for SR POSIF1_1\r
+       DCD   0                           ; Not Available\r
+       DCD   0                           ; Not Available\r
+       DCD   0                           ; Not Available\r
+       DCD   0                           ; Not Available\r
+       ExcpVector   CAN0_0_IRQHandler           ; Handler name for SR CAN0_0\r
+       ExcpVector   CAN0_1_IRQHandler           ; Handler name for SR CAN0_1\r
+       ExcpVector   CAN0_2_IRQHandler           ; Handler name for SR CAN0_2\r
+       ExcpVector   CAN0_3_IRQHandler           ; Handler name for SR CAN0_3\r
+       ExcpVector   CAN0_4_IRQHandler           ; Handler name for SR CAN0_4\r
+       ExcpVector   CAN0_5_IRQHandler           ; Handler name for SR CAN0_5\r
+       ExcpVector   CAN0_6_IRQHandler           ; Handler name for SR CAN0_6\r
+       ExcpVector   CAN0_7_IRQHandler           ; Handler name for SR CAN0_7\r
+       ExcpVector   USIC0_0_IRQHandler          ; Handler name for SR USIC0_0\r
+       ExcpVector   USIC0_1_IRQHandler          ; Handler name for SR USIC0_1\r
+       ExcpVector   USIC0_2_IRQHandler          ; Handler name for SR USIC0_2\r
+       ExcpVector   USIC0_3_IRQHandler          ; Handler name for SR USIC0_3\r
+       ExcpVector   USIC0_4_IRQHandler          ; Handler name for SR USIC0_4\r
+       ExcpVector   USIC0_5_IRQHandler          ; Handler name for SR USIC0_5\r
+       ExcpVector   USIC1_0_IRQHandler          ; Handler name for SR USIC1_0\r
+       ExcpVector   USIC1_1_IRQHandler          ; Handler name for SR USIC1_1\r
+       ExcpVector   USIC1_2_IRQHandler          ; Handler name for SR USIC1_2\r
+       ExcpVector   USIC1_3_IRQHandler          ; Handler name for SR USIC1_3\r
+       ExcpVector   USIC1_4_IRQHandler          ; Handler name for SR USIC1_4\r
+       ExcpVector   USIC1_5_IRQHandler          ; Handler name for SR USIC1_5\r
+       ExcpVector   USIC2_0_IRQHandler          ; Handler name for SR USIC2_0\r
+       ExcpVector   USIC2_1_IRQHandler          ; Handler name for SR USIC2_1\r
+       ExcpVector   USIC2_2_IRQHandler          ; Handler name for SR USIC2_2\r
+       ExcpVector   USIC2_3_IRQHandler          ; Handler name for SR USIC2_3\r
+       ExcpVector   USIC2_4_IRQHandler          ; Handler name for SR USIC2_4\r
+       ExcpVector   USIC2_5_IRQHandler          ; Handler name for SR USIC2_5\r
+       ExcpVector   LEDTS0_0_IRQHandler         ; Handler name for SR LEDTS0_0\r
+       DCD   0                           ; Not Available\r
+       ExcpVector   FCE0_0_IRQHandler           ; Handler name for SR FCE0_0\r
+       ExcpVector   GPDMA0_0_IRQHandler         ; Handler name for SR GPDMA0_0\r
+       ExcpVector   SDMMC0_0_IRQHandler         ; Handler name for SR SDMMC0_0\r
+       ExcpVector   USB0_0_IRQHandler           ; Handler name for SR USB0_0\r
+       ExcpVector   ETH0_0_IRQHandler           ; Handler name for SR ETH0_0\r
+       DCD   0                           ; Not Available\r
+       ExcpVector   GPDMA1_0_IRQHandler         ; Handler name for SR GPDMA1_0\r
+       DCD   0                           ; Not Available\r
+\r
+\r
+\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+        THUMB\r
+        PUBWEAK Reset_Handler\r
+        SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+\r
+        LDR     R0, =SystemInit\r
+        BLX     R0\r
+        LDR     R0, =SystemInit_DAVE3\r
+        BLX     R0\r
+        LDR     R0, =__iar_program_start\r
+        BX      R0\r
+\r
+\r
+        ProxyHandler NMI_Handler\r
+        ProxyHandler HardFault_Handler\r
+        ProxyHandler MemManage_Handler\r
+        ProxyHandler BusFault_Handler\r
+        ProxyHandler UsageFault_Handler\r
+        ProxyHandler SVC_Handler\r
+        ProxyHandler DebugMon_Handler\r
+        ProxyHandler PendSV_Handler\r
+        ProxyHandler SysTick_Handler\r
+\r
+        ProxyHandler SCU_0_IRQHandler\r
+        ProxyHandler ERU0_0_IRQHandler\r
+        ProxyHandler ERU0_1_IRQHandler\r
+        ProxyHandler ERU0_2_IRQHandler\r
+        ProxyHandler ERU0_3_IRQHandler\r
+        ProxyHandler ERU1_0_IRQHandler\r
+        ProxyHandler ERU1_1_IRQHandler\r
+        ProxyHandler ERU1_2_IRQHandler\r
+        ProxyHandler ERU1_3_IRQHandler\r
+        ProxyHandler PMU0_0_IRQHandler\r
+        ProxyHandler PMU0_1_IRQHandler\r
+        ProxyHandler VADC0_C0_0_IRQHandler\r
+        ProxyHandler VADC0_C0_1_IRQHandler\r
+        ProxyHandler VADC0_C0_2_IRQHandler\r
+        ProxyHandler VADC0_C0_3_IRQHandler\r
+        ProxyHandler VADC0_G0_0_IRQHandler\r
+        ProxyHandler VADC0_G0_1_IRQHandler\r
+        ProxyHandler VADC0_G0_2_IRQHandler\r
+        ProxyHandler VADC0_G0_3_IRQHandler\r
+        ProxyHandler VADC0_G1_0_IRQHandler\r
+        ProxyHandler VADC0_G1_1_IRQHandler\r
+        ProxyHandler VADC0_G1_2_IRQHandler\r
+        ProxyHandler VADC0_G1_3_IRQHandler\r
+        ProxyHandler VADC0_G2_0_IRQHandler\r
+        ProxyHandler VADC0_G2_1_IRQHandler\r
+        ProxyHandler VADC0_G2_2_IRQHandler\r
+        ProxyHandler VADC0_G2_3_IRQHandler\r
+        ProxyHandler VADC0_G3_0_IRQHandler\r
+        ProxyHandler VADC0_G3_1_IRQHandler\r
+        ProxyHandler VADC0_G3_2_IRQHandler\r
+        ProxyHandler VADC0_G3_3_IRQHandler\r
+        ProxyHandler DSD0_0_IRQHandler\r
+        ProxyHandler DSD0_1_IRQHandler\r
+        ProxyHandler DSD0_2_IRQHandler\r
+        ProxyHandler DSD0_3_IRQHandler\r
+        ProxyHandler DSD0_4_IRQHandler\r
+        ProxyHandler DSD0_5_IRQHandler\r
+        ProxyHandler DSD0_6_IRQHandler\r
+        ProxyHandler DSD0_7_IRQHandler\r
+        ProxyHandler DAC0_0_IRQHandler\r
+        ProxyHandler DAC0_1_IRQHandler\r
+        ProxyHandler CCU40_0_IRQHandler\r
+        ProxyHandler CCU40_1_IRQHandler\r
+        ProxyHandler CCU40_2_IRQHandler\r
+        ProxyHandler CCU40_3_IRQHandler\r
+        ProxyHandler CCU41_0_IRQHandler\r
+        ProxyHandler CCU41_1_IRQHandler\r
+        ProxyHandler CCU41_2_IRQHandler\r
+        ProxyHandler CCU41_3_IRQHandler\r
+        ProxyHandler CCU42_0_IRQHandler\r
+        ProxyHandler CCU42_1_IRQHandler\r
+        ProxyHandler CCU42_2_IRQHandler\r
+        ProxyHandler CCU42_3_IRQHandler\r
+        ProxyHandler CCU43_0_IRQHandler\r
+        ProxyHandler CCU43_1_IRQHandler\r
+        ProxyHandler CCU43_2_IRQHandler\r
+        ProxyHandler CCU43_3_IRQHandler\r
+        ProxyHandler CCU80_0_IRQHandler\r
+        ProxyHandler CCU80_1_IRQHandler\r
+        ProxyHandler CCU80_2_IRQHandler\r
+        ProxyHandler CCU80_3_IRQHandler\r
+        ProxyHandler CCU81_0_IRQHandler\r
+        ProxyHandler CCU81_1_IRQHandler\r
+        ProxyHandler CCU81_2_IRQHandler\r
+        ProxyHandler CCU81_3_IRQHandler\r
+        ProxyHandler POSIF0_0_IRQHandler\r
+        ProxyHandler POSIF0_1_IRQHandler\r
+        ProxyHandler POSIF1_0_IRQHandler\r
+        ProxyHandler POSIF1_1_IRQHandler\r
+        ProxyHandler CAN0_0_IRQHandler\r
+        ProxyHandler CAN0_1_IRQHandler\r
+        ProxyHandler CAN0_2_IRQHandler\r
+        ProxyHandler CAN0_3_IRQHandler\r
+        ProxyHandler CAN0_4_IRQHandler\r
+        ProxyHandler CAN0_5_IRQHandler\r
+        ProxyHandler CAN0_6_IRQHandler\r
+        ProxyHandler CAN0_7_IRQHandler\r
+        ProxyHandler USIC0_0_IRQHandler\r
+        ProxyHandler USIC0_1_IRQHandler\r
+        ProxyHandler USIC0_2_IRQHandler\r
+        ProxyHandler USIC0_3_IRQHandler\r
+        ProxyHandler USIC0_4_IRQHandler\r
+        ProxyHandler USIC0_5_IRQHandler\r
+        ProxyHandler USIC1_0_IRQHandler\r
+        ProxyHandler USIC1_1_IRQHandler\r
+        ProxyHandler USIC1_2_IRQHandler\r
+        ProxyHandler USIC1_3_IRQHandler\r
+        ProxyHandler USIC1_4_IRQHandler\r
+        ProxyHandler USIC1_5_IRQHandler\r
+        ProxyHandler USIC2_0_IRQHandler\r
+        ProxyHandler USIC2_1_IRQHandler\r
+        ProxyHandler USIC2_2_IRQHandler\r
+        ProxyHandler USIC2_3_IRQHandler\r
+        ProxyHandler USIC2_4_IRQHandler\r
+        ProxyHandler USIC2_5_IRQHandler\r
+        ProxyHandler LEDTS0_0_IRQHandler\r
+        ProxyHandler FCE0_0_IRQHandler\r
+        ProxyHandler GPDMA0_0_IRQHandler\r
+        ProxyHandler SDMMC0_0_IRQHandler\r
+        ProxyHandler USB0_0_IRQHandler\r
+        ProxyHandler ETH0_0_IRQHandler\r
+        ProxyHandler GPDMA1_0_IRQHandler\r
+\r
+\r
+; Definition of the default weak SystemInit_DAVE3 function for DAVE3 system init.\r
+        PUBWEAK SystemInit_DAVE3\r
+        SECTION .text:CODE:REORDER:NOROOT(2)\r
+SystemInit_DAVE3\r
+        NOP\r
+        BX LR\r
+\r
+; Definition of the default weak DAVE3 function for clock App usage.\r
+; AllowPLLInitByStartup Handler\r
+        PUBWEAK AllowPLLInitByStartup\r
+        SECTION .text:CODE:REORDER:NOROOT(2)\r
+AllowPLLInitByStartup\r
+        MOV R0,#1\r
+        BX LR\r
+\r
+PREF_PCON       EQU 0x58004000\r
+SCU_GCU_PEEN    EQU 0x5000413C\r
+SCU_GCU_PEFLAG  EQU 0x50004150\r
+\r
+\r
+        END\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4200.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4200.h
new file mode 100644 (file)
index 0000000..e30f33f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4200.h
@@ -0,0 +1,72 @@
+/**************************************************************************//**\r
+ * @file     system_XMC4200.h\r
+ * @brief    Header file for the XMC4400-Series systeminit\r
+ *           \r
+ * @version  V1.0\r
+ * @date     17. September 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon\92s microcontrollers.  \r
+ * This file can be freely distributed within development tools that are supporting such microcontrollers. \r
+\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SYSTEM_XMC4200_H\r
+#define __SYSTEM_XMC4200_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Setup the microcontroller system.\r
+ *         Initialize the System.\r
+ */\r
+extern void SystemInit (void);\r
+\r
+\r
+/**\r
+ * Update SystemCoreClock variable\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Updates the SystemCoreClock with current core Clock\r
+ *         retrieved from cpu registers.\r
+ */\r
+extern void SystemCoreClockUpdate (void);\r
+\r
+/* this weak function enables DAVE3 clock App usage */         \r
+extern uint32_t AllowPLLInitByStartup(void);           \r
+                               \r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4400.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4400.h
new file mode 100644 (file)
index 0000000..953e1b0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4400.h
@@ -0,0 +1,72 @@
+/**************************************************************************//**\r
+ * @file     system_XMC4400.h\r
+ * @brief    Header file for the XMC4400-Series systeminit\r
+ *           \r
+ * @version  V1.0\r
+ * @date     17. August 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon\92s microcontrollers.  \r
+ * This file can be freely distributed within development tools that are supporting such microcontrollers. \r
+\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SYSTEM_XMC4400_H\r
+#define __SYSTEM_XMC4400_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Setup the microcontroller system.\r
+ *         Initialize the System.\r
+ */\r
+extern void SystemInit (void);\r
+\r
+\r
+/**\r
+ * Update SystemCoreClock variable\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Updates the SystemCoreClock with current core Clock\r
+ *         retrieved from cpu registers.\r
+ */\r
+extern void SystemCoreClockUpdate (void);\r
+\r
+/* this weak function enables DAVE3 clock App usage */         \r
+extern uint32_t AllowPLLInitByStartup(void);           \r
+                               \r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.c
new file mode 100644 (file)
index 0000000..74ecf74
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.c
@@ -0,0 +1,705 @@
+/**************************************************************************//**\r
+ * @file     system_XMC4500.c\r
+ * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
+ *           for the Infineon XMC4500 Device Series\r
+ * @version  V3.0.1 Alpha\r
+ * @date     17. September 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include "system_XMC4500.h"\r
+#include <XMC4500.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL                      1\r
+#define SCU_CLOCK_BACK_UP_FACTORY                      2\r
+#define SCU_CLOCK_BACK_UP_AUTOMATIC            3\r
+\r
+\r
+#define HIB_CLOCK_FOSI                                 1                                \r
+#define HIB_CLOCK_OSCULP                               2\r
+\r
+\r
+\r
+\r
+/*\r
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
+*/\r
+\r
+\r
+\r
+/*--------------------- Watchdog Configuration -------------------------------\r
+//\r
+// <e> Watchdog Configuration\r
+//     <o1.0> Disable Watchdog\r
+//\r
+// </e>\r
+*/\r
+#define WDT_SETUP               1\r
+#define WDTENB_nVal             0x00000001\r
+\r
+/*--------------------- CLOCK Configuration -------------------------------\r
+//\r
+// <e> Main Clock Configuration\r
+//     <o1.0..1> CPU clock divider\r
+//                     <0=> fCPU = fSYS \r
+//                     <1=> fCPU = fSYS / 2\r
+//     <o2.0..1>  Peripheral Bus clock divider\r
+//                     <0=> fPB        = fCPU\r
+//                     <1=> fPB        = fCPU / 2\r
+//     <o3.0..1>  CCU Bus clock divider\r
+//                     <0=> fCCU = fCPU\r
+//                     <1=> fCCU = fCPU / 2\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCK_SETUP               1\r
+#define        SCU_CPUCLKCR_DIV                0x00000000\r
+#define        SCU_PBCLKCR_DIV             0x00000000\r
+#define        SCU_CCUCLKCR_DIV                0x00000000\r
+/* not avalible in config wizzard*/\r
+/*                             \r
+* mandatory clock parameters **************************************************                                \r
+*                              \r
+* source for clock generation                          \r
+* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)                                \r
+*                              \r
+**************************************************************************************/                                \r
+// Selection of imput lock for PLL                             \r
+/*************************************************************************************/\r
+#define        SCU_PLL_CLOCK_INPUT     SCU_CLOCK_CRYSTAL\r
+//#define      SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_FACTORY\r
+//#define      SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_AUTOMATIC\r
+\r
+/*************************************************************************************/\r
+// Standby clock selection for Backup clock source trimming\r
+/*************************************************************************************/\r
+#define        SCU_STANDBY_CLOCK  HIB_CLOCK_OSCULP\r
+//#define      SCU_STANDBY_CLOCK  HIB_CLOCK_FOSI\r
+\r
+/*************************************************************************************/\r
+// Global clock parameters\r
+/*************************************************************************************/\r
+#define CLOCK_FSYS                                                     120000000\r
+#define        CLOCK_CRYSTAL_FREQUENCY 12000000                \r
+#define        CLOCK_BACK_UP                                           24000000                \r
+                               \r
+/*************************************************************************************/\r
+/* OSC_HP setup parameters */                          \r
+/*************************************************************************************/\r
+#define        SCU_OSC_HP_MODE 0xF0\r
+#define        SCU_OSCHPWDGDIV 2               \r
+                               \r
+/*************************************************************************************/\r
+/* MAIN PLL setup parameters */                                \r
+/*************************************************************************************/\r
+//Divider settings for external crystal @ 12 MHz \r
+/*************************************************************************************/\r
+#define        SCU_PLL_K1DIV   1\r
+#define        SCU_PLL_K2DIV   3\r
+#define        SCU_PLL_PDIV    1\r
+#define        SCU_PLL_NDIV    79\r
+                               \r
+/*************************************************************************************/\r
+//Divider settings for use of backup clock source trimmed\r
+/*************************************************************************************/\r
+//#define      SCU_PLL_K1DIV   1               \r
+//#define      SCU_PLL_K2DIV   3               \r
+//#define      SCU_PLL_PDIV    3               \r
+//#define      SCU_PLL_NDIV    79              \r
+/*************************************************************************************/\r
+\r
+/*--------------------- USB CLOCK Configuration ---------------------------\r
+//\r
+// <e> USB Clock Configuration\r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_USB_CLOCK_SETUP              0\r
+/* not avalible in config wizzard*/\r
+#define        SCU_USBPLL_PDIV 0               \r
+#define        SCU_USBPLL_NDIV 31              \r
+#define        SCU_USBDIV      3               \r
+\r
+/*--------------------- Flash Wait State Configuration -------------------------------\r
+//\r
+// <e> Flash Wait State Configuration\r
+//     <o1.0..3>   Flash Wait State\r
+//                     <0=> 3 WS\r
+//                     <1=> 4 WS\r
+//                     <2=> 5 WS     \r
+//                                                                              <3=> 6 WS\r
+// </e>\r
+// \r
+*/\r
+\r
+#define PMU_FLASH             1\r
+#define        PMU_FLASH_WS                                    0x00000000\r
+\r
+\r
+/*--------------------- CLOCKOUT Configuration -------------------------------\r
+//\r
+// <e> Clock OUT Configuration\r
+//     <o1.0..1>   Clockout Source Selection\r
+//                     <0=> System Clock\r
+//                     <2=> Divided value of USB PLL output\r
+//                     <3=> Divided value of PLL Clock\r
+//     <o2.0..4>   Clockout divider <1-10><#-1>\r
+//     <o3.0..1>   Clockout Pin Selection\r
+//                     <0=> P1.15\r
+//                     <1=> P0.8\r
+//                     \r
+//\r
+// </e>\r
+// \r
+*/\r
+\r
+#define SCU_CLOCKOUT_SETUP               0\r
+#define        SCU_CLOCKOUT_SOURCE             0x00000003\r
+#define        SCU_CLOCKOUT_DIV                0x00000009\r
+#define        SCU_CLOCKOUT_PIN                0x00000001\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+#if SCU_CLOCK_SETUP\r
+uint32_t SystemCoreClock = CLOCK_FSYS;\r
+#else\r
+uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+  static functions declarations\r
+ *----------------------------------------------------------------------------*/\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void);\r
+#endif\r
+\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void);\r
+#endif\r
+\r
+\r
+/**\r
+  * @brief  Setup the microcontroller system.\r
+  *         Initialize the PLL and update the \r
+  *         SystemCoreClock variable.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemInit(void)\r
+{\r
+int temp;\r
+       \r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */\r
+               (3UL << 11*2)  );               /* set CP11 Full Access */\r
+#endif\r
+\r
+/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
+SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
+       \r
+/* Setup the WDT */\r
+#if WDT_SETUP\r
+\r
+WDT->CTR &= ~WDTENB_nVal; \r
+\r
+#endif\r
+\r
+/* Setup the Flash Wait State */\r
+#if PMU_FLASH\r
+temp = FLASH0->FCON; \r
+temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
+temp |= PMU_FLASH_WS+3;\r
+FLASH0->FCON = temp;\r
+#endif\r
+\r
+       \r
+/* Setup the clockout */\r
+#if SCU_CLOCKOUT_SETUP\r
+\r
+SCU_CLK->EXTCLKCR      |= SCU_CLOCKOUT_SOURCE;\r
+/*set PLL div for clkout */\r
+SCU_CLK->EXTCLKCR      |= SCU_CLOCKOUT_DIV<<16;\r
+\r
+if (SCU_CLOCKOUT_PIN) {\r
+                                               PORT0->IOCR8 = 0x00000088;   /*P0.8 --> ALT1 select +  HWSEL */\r
+                                           PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
+                                           //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk);  /*set to strong driver */\r
+                                               }\r
+else {\r
+               PORT1->IOCR12 = 0x88000000;                    /*P1.15--> ALT1 select */\r
+           //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk);  /*set to strong driver */\r
+               }\r
+\r
+#endif\r
+\r
+\r
+/* Setup the System clock */ \r
+#if SCU_CLOCK_SETUP\r
+SystemClockSetup();\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
+\r
+\r
+/* Setup the USB PL */ \r
+#if SCU_USB_CLOCK_SETUP\r
+USBClockSetup();\r
+#endif\r
+\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Update SystemCoreClock according to Clock Register Values\r
+  * @note   -  \r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+unsigned int PDIV;\r
+unsigned int NDIV;\r
+unsigned int K2DIV;\r
+unsigned int long VCO;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+  Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+if (SCU_CLK->SYSCLKCR ==  0x00010000)\r
+{\r
+       if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
+               /* check if PLL is locked */\r
+               /* read back divider settings */\r
+                PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
+                NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
+                K2DIV  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
+\r
+               if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
+               /* the selected clock is the Backup clock fofi */\r
+               VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
+               SystemCoreClock = VCO/K2DIV;\r
+               /* in case the sysclock div is used */\r
+               SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+               \r
+               }\r
+               else\r
+               {\r
+               /* the selected clock is the PLL external oscillator */         \r
+               VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
+               SystemCoreClock = VCO/K2DIV;\r
+               /* in case the sysclock div is used */\r
+               SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
+               } \r
+       \r
+       \r
+       }\r
+}\r
+else\r
+{\r
+SystemCoreClock = CLOCK_BACK_UP;\r
+}\r
+\r
+\r
+}\r
+\r
+\r
+/**\r
+  * @brief  -\r
+  * @note   -  \r
+  * @param  None\r
+  * @retval None\r
+  */\r
+#if (SCU_CLOCK_SETUP == 1)\r
+static int SystemClockSetup(void)\r
+{\r
+int temp;\r
+unsigned int long VCO;\r
+int stepping_K2DIV;    \r
+\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+       \r
+/* check if PLL is switched on */\r
+if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+/* enable PLL first */\r
+  SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+\r
+}\r
+\r
+/* Enable OSC_HP if not already on*/\r
+  if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
+  {\r
+       /********************************************************************************************************************/\r
+       /*   Use external crystal for PLL clock input                                                                            */\r
+       /********************************************************************************************************************/\r
+\r
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+          SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
+          /* setup OSC WDG devider */\r
+          SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);         \r
+          /* select external OSC as PLL input */\r
+          SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
+          /* restart OSC Watchdog */\r
+          SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
+\r
+       /* Timeout for wait loop ~150ms */\r
+          /********************************/\r
+          SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
+          do \r
+          {\r
+       ;/* wait for ~150ms  */\r
+          }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+          return(0);/* Return Error */\r
+\r
+    }\r
+  }\r
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
+       {\r
+       /********************************************************************************************************************/\r
+       /*   Use factory trimming Back-up clock for PLL clock input                                                                            */\r
+       /********************************************************************************************************************/\r
+               /* PLL Back up clock selected */\r
+               SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+                       \r
+       }\r
+  else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
+  {\r
+       /********************************************************************************************************************/\r
+       /*   Use automatic trimming Back-up clock for PLL clock input                                                                            */\r
+       /********************************************************************************************************************/\r
+       /* check for HIB Domain enabled  */\r
+       if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
+               SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
+\r
+   /* check for HIB Domain is not in reset state  */\r
+       if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
+           SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
+\r
+                       /* PLL Back up clock selected */\r
+               SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
+       \r
+               if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
+                       {\r
+                       /****************************************************************************************************************/\r
+                       /*   Use fOSI as source of the standby clock                                                                             */\r
+                       /****************************************************************************************************************/\r
+                       SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+                       \r
+                       SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+                       for(temp=0;temp<=0xFFFF;temp++);\r
+\r
+                       SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+                       }\r
+               else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
+                       {\r
+                       /****************************************************************************************************************/\r
+                       /*   Use fULP as source of the standby clock                                                                            */\r
+                       /****************************************************************************************************************/\r
+                       /*check OSCUL if running correct*/\r
+                       if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
+                               {\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
+\r
+                                       SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
+                                       /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
+                                       /* select OSCUL clock for RTC*/\r
+                                       SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+                                       /*enable OSCULP WDG Alarm Enable*/\r
+                                       SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+                                       /*wait now for clock is stable */\r
+                                       do\r
+                                       {\r
+                                       SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+                                       for(temp=0;temp<=0xFFFF;temp++);\r
+                                       }\r
+                                       while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); \r
+\r
+                                       SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
+                                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
+                               }       \r
+                       // now OSCULP is running and can be used                 \r
+                       SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
+                       while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
+                       \r
+                       SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
+                       /*TRIAL for delay loop*/\r
+                       for(temp=0;temp<=0xFFFF;temp++);\r
+                       \r
+                       SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
+                       /*TRIAL for delay loop*/\r
+                       for(temp=0;temp<=0xFFFF;temp++);\r
+                       \r
+                       }\r
+  }\r
+\r
+       /********************************************************************************************************************/\r
+       /*   Setup and look the main PLL                                                                                    */\r
+       /********************************************************************************************************************/\r
+\r
+if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
+       /* Systen is still running from internal clock */\r
+                  /* select FOFI as system clock */\r
+                  if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
+\r
+\r
+                        /*calulation for stepping*/\r
+                        if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+                        if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+                                       VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+        \r
+                        stepping_K2DIV = (VCO/24000000)-1;     \r
+                        /* Go to bypass the Main PLL */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+                  /* disconnect OSC_HP to PLL */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
+                  /* Setup devider settings for main PLL */\r
+                  SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                  /* we may have to set OSCDISCDIS */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+                  /* connect OSC_HP to PLL */\r
+                  SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
+                  /* restart PLL Lock detection */\r
+                  SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
+                  /* wait for PLL Lock */\r
+                  /* setup time out loop */\r
+              /* Timeout for wait loo ~150ms */\r
+                  /********************************/\r
+                  SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+                  SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+                  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                                  SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
+                  \r
+                  while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
+              SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+\r
+                  if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
+                               {\r
+                               /* Go back to the Main PLL */\r
+                               SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
+                               }\r
+                               else return(0);\r
+                \r
+       \r
+          /*********************************************************\r
+          here we need to setup the system clock divider\r
+          *********************************************************/\r
+       \r
+               SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
+               SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;     \r
+               SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
+       \r
+\r
+                /* Switch system clock to PLL */\r
+          SCU_CLK->SYSCLKCR |=  0x00010000; \r
+                               \r
+          /* we may have to reset OSCDISCDIS */\r
+          SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
+                               \r
+                                                                                                                                 \r
+                /*********************************************************/\r
+                /* Delay for next K2 step ~50µs */\r
+                /*********************************************************/\r
+                SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+                SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+                SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                                                                                SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
+       \r
+                while (SysTick->VAL >= 100);                                                              /* wait for ~50µs  */\r
+                SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+                /*********************************************************/\r
+\r
+          /*********************************************************\r
+          here the ramp up of the system clock starts FSys < 60MHz\r
+          *********************************************************/\r
+               if (CLOCK_FSYS > 60000000){\r
+                        /*calulation for stepping*/\r
+                        if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+                        if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+                                       VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+        \r
+                        stepping_K2DIV = (VCO/60000000)-1;     \r
+\r
+                        /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                }\r
+                else\r
+                {\r
+                               /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                   SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
+                         return(1);\r
+                }\r
+\r
+                /*********************************************************/\r
+                /* Delay for next K2 step ~50µs */\r
+                /*********************************************************/\r
+          SysTick->LOAD  = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
+       \r
+          while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          /********************************/\r
+       \r
+   /*********************************************************\r
+          here the ramp up of the system clock starts FSys < 90MHz\r
+          *********************************************************/\r
+               if (CLOCK_FSYS > 90000000){\r
+                        /*calulation for stepping*/\r
+                        if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+                        if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
+                                       VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
+\r
+                        stepping_K2DIV = (VCO/90000000)-1;                     \r
+\r
+                        /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+                }\r
+                else\r
+                {\r
+                               /* Setup devider settings for main PLL */\r
+                               SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+             SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
+                               return(1);\r
+                }\r
+       \r
+                /*********************************************************/\r
+                /* Delay for next K2 step ~50µs */\r
+                /*********************************************************/\r
+          SysTick->LOAD  = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
+       \r
+          while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          /********************************/\r
+       \r
+          /* Setup devider settings for main PLL */\r
+          SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
+       \r
+          SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
+       }\r
+ }/* end this weak function enables DAVE3 clock App usage */   \r
+   return(1);\r
+\r
+}\r
+#endif\r
+\r
+/**\r
+  * @brief  -\r
+  * @note   -  \r
+  * @param  None\r
+  * @retval None\r
+  */\r
+#if (SCU_USB_CLOCK_SETUP == 1)\r
+static int USBClockSetup(void)\r
+{\r
+/* this weak function enables DAVE3 clock App usage */ \r
+if(AllowPLLInitByStartup()){\r
+\r
+       /* check if PLL is switched on */\r
+if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
+       /* enable PLL first */\r
+  SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
+}\r
+\r
+/* check and if not already running enable OSC_HP */\r
+   if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
+                /* check if Main PLL is switched on for OSC WD*/\r
+                if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
+                       /* enable PLL first */\r
+                       SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
+                }\r
+          SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
+          /* setup OSC WDG devider */\r
+          SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);         \r
+          /* restart OSC Watchdog */\r
+          SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;  \r
+       \r
+       /* Timeout for wait loop ~150ms */\r
+          /********************************/\r
+          SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
+          SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
+          SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
+                          SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */                 \r
+          do \r
+          {\r
+       ;/* wait for ~150ms  */\r
+          }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); \r
+\r
+          SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
+          if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
+          return(0);/* Return Error */\r
+       \r
+  }\r
+\r
+\r
+/* Setup USB PLL */\r
+   /* Go to bypass the Main PLL */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
+   /* disconnect OSC_FI to PLL */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+   /* Setup devider settings for main PLL */\r
+   SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
+   /* Setup USBDIV settings USB clock */\r
+   SCU_CLK->USBCLKCR = SCU_USBDIV;\r
+   /* we may have to set OSCDISCDIS */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
+   /* connect OSC_FI to PLL */\r
+   SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
+   /* restart PLL Lock detection */\r
+   SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
+   /* wait for PLL Lock */\r
+   while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
+       \r
+  }/* end this weak function enables DAVE3 clock App usage */    \r
+   return(1);\r
+\r
+}\r
+#endif\r
+\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.h
new file mode 100644 (file)
index 0000000..73eb6d5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.h
@@ -0,0 +1,114 @@
+/**************************************************************************//**\r
+ * @file     system_XMC4500.h\r
+ * @brief    Header file for the XMC4500-Series systeminit\r
+ *           \r
+ * @version  V1.6\r
+ * @date     23. October 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2011 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon\92s microcontrollers.  \r
+ * This file can be freely distributed within development tools that are supporting such microcontrollers. \r
+\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SYSTEM_XMC4500_H\r
+#define __SYSTEM_XMC4500_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Setup the microcontroller system.\r
+ *         Initialize the System.\r
+ */\r
+extern void SystemInit (void);\r
+\r
+\r
+/**\r
+ * Update SystemCoreClock variable\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Updates the SystemCoreClock with current core Clock\r
+ *         retrieved from cpu registers.\r
+ */\r
+extern void SystemCoreClockUpdate (void);\r
+\r
+/* this weak function enables DAVE3 clock App usage */         \r
+extern uint32_t AllowPLLInitByStartup(void);                           \r
+\r
+\r
+/* clock definitions, do not modify! */\r
+#define SCU_CLOCK_CRYSTAL              1\r
+\r
+                               \r
+                               \r
+/*                             \r
+ * mandatory clock parameters **************************************************                               \r
+ */                            \r
+/* source for clock generation                         \r
+ * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)                               \r
+ * mandatory for old system_xmc4500.c files - please do not remove!!!                                  \r
+ **************************************************************************************/                               \r
+                               \r
+#define        SCU_PLL_CLOCK_INPUT     SCU_CLOCK_CRYSTAL\r
+#define CLOCK_OSC_HP   24000000\r
+#define CLOCK_BACK_UP  24000000                 \r
+#define        CLOCK_CRYSTAL_FREQUENCY 12000000                \r
+#define        SYSTEM_FREQUENCY        120000000               \r
+                               \r
+/* OSC_HP setup parameters */                          \r
+#define        OSC_HP_MODE     0               \r
+#define OSCHPWDGDIV 2\r
+                               \r
+/* MAIN PLL setup parameters */                                \r
+                               \r
+                               \r
+#define        PLL_K1DIV       1               \r
+#define        PLL_K2DIV       3               \r
+#define        PLL_PDIV        1               \r
+#define        PLL_NDIV        79\r
+               \r
+                               \r
+                               \r
+#define        PLL_K2DIV_STEP_1        19      //PLL output is 24Mhz   \r
+#define        PLL_K2DIV_STEP_2        7       //PLL output to 60Mhz   \r
+#define        PLL_K2DIV_STEP_3        4       //PLL output to 96Mhz   \r
+                               \r
+                               \r
+               \r
+#define        USBPLL_PDIV     1               \r
+#define        USBPLL_NDIV     15              \r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt
index adb4267af5ed7d8ed57c41eb3c79dfbe6178afcb..c03a8bbeac80d79c70b8263310b8a22be122c4c5 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt
@@ -734,7 +734,7 @@
 
   <Group>
     <GroupName>Demo_Source</GroupName>
-    <tvExp>0</tvExp>
+    <tvExp>1</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
@@ -744,9 +744,9 @@
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <Focus>0</Focus>
-      <ColumnNumber>0</ColumnNumber>
+      <ColumnNumber>4</ColumnNumber>
       <tvExpOptDlg>0</tvExpOptDlg>
-      <TopLine>64</TopLine>
+      <TopLine>113</TopLine>
       <CurrentLine>140</CurrentLine>
       <bDave2>0</bDave2>
       <PathWithFileName>.\main.c</PathWithFileName>
@@ -778,8 +778,8 @@
       <Focus>0</Focus>
       <ColumnNumber>0</ColumnNumber>
       <tvExpOptDlg>0</tvExpOptDlg>
-      <TopLine>0</TopLine>
-      <CurrentLine>0</CurrentLine>
+      <TopLine>367</TopLine>
+      <CurrentLine>418</CurrentLine>
       <bDave2>0</bDave2>
       <PathWithFileName>.\RegTest.c</PathWithFileName>
       <FilenameWithoutPath>RegTest.c</FilenameWithoutPath>
@@ -926,7 +926,7 @@
 
   <Group>
     <GroupName>Common_Demo_Source</GroupName>
-    <tvExp>0</tvExp>
+    <tvExp>1</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c
index cf2aeaed9119fa9cee31d045d6b116c40133e0de..2c42e38f173affd30e24434bd8a022b65db001cf 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c
@@ -418,6 +418,14 @@ reg2_loopf_pass
        ldr r1, [r0]\r
        adds r1, r1, #1\r
        str r1, [r0]\r
+       \r
+       /* Yield to increase test coverage. */\r
+       movs r0, #0x01\r
+       ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */\r
+       lsl r0, r0, #28 /* Shift to PendSV bit */\r
+       str r0, [r1]\r
+       dsb\r
+       \r
        pop { r0-r1 }\r
        \r
        /* Start again. */\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c
index 8d415a9248f28643489b6fc23a4860091b400691..768a44d9638574243cc1cf993ca7edfe4ada553b 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c
@@ -135,8 +135,8 @@ int main( void )
 \r
 static void prvSetupHardware( void )\r
 {\r
-extern void SystemCoreClockUpdate( void );\r
-\r
+       configCONFIGURE_LED();\r
+       \r
        /* Ensure all priority bits are assigned as preemption priority bits. */\r
        NVIC_SetPriorityGrouping( 0 );\r
 }\r
diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c
index b93e72df26acf47f4d8d458c05b6f225e7ef8f4a..a9cda91adf2f5e33c63441d35f6979b8283de60e 100644 (file)
--- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c
+++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c
@@ -113,16 +113,12 @@
 \r
 /* Standard demo application includes. */\r
 #include "flop.h"\r
-#include "integer.h"\r
-#include "PollQ.h"\r
 #include "semtest.h"\r
 #include "dynamic.h"\r
-#include "BlockQ.h"\r
 #include "blocktim.h"\r
 #include "countsem.h"\r
 #include "GenQTest.h"\r
 #include "recmutex.h"\r
-#include "death.h"\r
 \r
 /* Priorities for the demo application tasks. */\r
 #define mainQUEUE_POLL_PRIORITY                                ( tskIDLE_PRIORITY + 2UL )\r
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