--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : cortexm3_macro.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : Header file for cortexm3_macro.s.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __CORTEXM3_MACRO_H\r
+#define __CORTEXM3_MACRO_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_type.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void __WFI(void);\r
+void __WFE(void);\r
+void __SEV(void);\r
+void __ISB(void);\r
+void __DSB(void);\r
+void __DMB(void);\r
+void __SVC(void);\r
+u32 __MRS_CONTROL(void);\r
+void __MSR_CONTROL(u32 Control);\r
+void __SETPRIMASK(void);\r
+void __RESETPRIMASK(void);\r
+void __SETFAULTMASK(void);\r
+void __RESETFAULTMASK(void);\r
+void __BASEPRICONFIG(u32 NewPriority);\r
+u32 __GetBASEPRI(void);\r
+u16 __REV_HalfWord(u16 Data);\r
+u32 __REV_Word(u32 Data);\r
+\r
+#endif /* __CORTEXM3_MACRO_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : lcd.h\r
+* Author : MCD Application Team\r
+* Date First Issued : mm/dd/yyyy\r
+* Description : This file contains all the functions prototypes for the\r
+* lcd software driver.\r
+********************************************************************************\r
+* History:\r
+* mm/dd/yyyy\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __LCD_H\r
+#define __LCD_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_lib.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* LCD Registers */\r
+#define R0 0x00\r
+#define R1 0x01\r
+#define R2 0x02\r
+#define R3 0x03\r
+#define R5 0x05\r
+#define R6 0x06\r
+#define R13 0x0D\r
+#define R14 0x0E\r
+#define R15 0x0F\r
+#define R16 0x10\r
+#define R17 0x11\r
+#define R18 0x12\r
+#define R19 0x13\r
+#define R20 0x14\r
+#define R21 0x15\r
+#define R22 0x16\r
+#define R23 0x17\r
+#define R24 0x18\r
+#define R25 0x19\r
+#define R26 0x1A\r
+#define R27 0x1B\r
+#define R28 0x1C\r
+#define R29 0x1D\r
+#define R30 0x1E\r
+#define R31 0x1F\r
+#define R32 0x20\r
+#define R36 0x24\r
+#define R37 0x25\r
+#define R40 0x28\r
+#define R43 0x2B\r
+#define R45 0x2D\r
+#define R49 0x31\r
+#define R50 0x32\r
+#define R51 0x33\r
+#define R52 0x34\r
+#define R53 0x35\r
+#define R55 0x37\r
+#define R59 0x3B\r
+#define R60 0x3C\r
+#define R61 0x3D\r
+#define R62 0x3E\r
+#define R63 0x3F\r
+#define R64 0x40\r
+#define R65 0x41\r
+#define R66 0x42\r
+#define R67 0x43\r
+#define R68 0x44\r
+#define R69 0x45\r
+#define R70 0x46\r
+#define R71 0x47\r
+#define R72 0x48\r
+#define R73 0x49\r
+#define R74 0x4A\r
+#define R75 0x4B\r
+#define R76 0x4C\r
+#define R77 0x4D\r
+#define R78 0x4E\r
+#define R79 0x4F\r
+#define R80 0x50\r
+#define R118 0x76\r
+#define R134 0x86\r
+#define R135 0x87\r
+#define R136 0x88\r
+#define R137 0x89\r
+#define R139 0x8B\r
+#define R140 0x8C\r
+#define R141 0x8D\r
+#define R143 0x8F\r
+#define R144 0x90\r
+#define R145 0x91\r
+#define R146 0x92\r
+#define R147 0x93\r
+#define R148 0x94\r
+#define R149 0x95\r
+#define R150 0x96\r
+#define R151 0x97\r
+#define R152 0x98\r
+#define R153 0x99\r
+#define R154 0x9A\r
+#define R157 0x9D\r
+#define R192 0xC0\r
+#define R193 0xC1\r
+\r
+/* LCD Control pins */\r
+#define CtrlPin_NCS GPIO_Pin_2 /* PB.02 */\r
+#define CtrlPin_RS GPIO_Pin_7 /* PD.07 */\r
+#define CtrlPin_NWR GPIO_Pin_15 /* PD.15 */\r
+\r
+/* LCD color */\r
+#define White 0xFFFF\r
+#define Black 0x0000\r
+#define Blue 0x001F\r
+#define Orange 0x051F\r
+#define Red 0xF800\r
+#define Magenta 0xF81F\r
+#define Green 0x07E0\r
+#define Cyan 0x7FFF\r
+#define Yellow 0xFFE0\r
+\r
+#define Line0 0\r
+#define Line1 24\r
+#define Line2 48\r
+#define Line3 72\r
+#define Line4 96\r
+#define Line5 120\r
+#define Line6 144\r
+#define Line7 168\r
+#define Line8 192\r
+#define Line9 216\r
+\r
+#define Horizontal 0x00\r
+#define Vertical 0x01\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/*----- High layer function -----*/\r
+void LCD_Init(void);\r
+void LCD_SetTextColor(vu16 Color);\r
+void LCD_SetBackColor(vu16 Color);\r
+void LCD_ClearLine(u8 Line);\r
+void LCD_Clear(void);\r
+void LCD_SetCursor(u8 Xpos, u16 Ypos);\r
+void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c);\r
+void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii);\r
+void LCD_DisplayStringLine(u8 Line, u8 *ptr);\r
+void LCD_DisplayString(u8 Line, u8 *ptr);\r
+void LCD_ScrollText(u8 Line, u8 *ptr);\r
+void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width);\r
+void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction);\r
+void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width);\r
+void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius);\r
+void LCD_DrawMonoPict(uc32 *Pict);\r
+void LCD_DrawBMP(u32 BmpAddress);\r
+\r
+/*----- Medium layer function -----*/\r
+void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue);\r
+u8 LCD_ReadReg(u8 LCD_Reg);\r
+void LCD_WriteRAM(u16 RGB_Code);\r
+u16 LCD_ReadRAM(void);\r
+void LCD_PowerOn(void);\r
+void LCD_DisplayOn(void);\r
+void LCD_DisplayOff(void);\r
+\r
+/*----- Low layer function -----*/\r
+void LCD_CtrlLinesConfig(void);\r
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal);\r
+void LCD_SPIConfig(void);\r
+\r
+#endif /* __LCD_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : spi_flash.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 02/05/2007\r
+* Description : Header for spi_flash.c file.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __SPI_FLASH_H\r
+#define __SPI_FLASH_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_lib.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+#define Low 0x00 /* Chip Select line low */\r
+#define High 0x01 /* Chip Select line high */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+/*----- High layer function -----*/\r
+void SPI_FLASH_Init(void);\r
+void SPI_FLASH_SectorErase(u32 SectorAddr);\r
+void SPI_FLASH_BulkErase(void);\r
+void SPI_FLASH_PageWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite);\r
+void SPI_FLASH_BufferWrite(u8* pBuffer, u32 WriteAddr, u16 NumByteToWrite);\r
+void SPI_FLASH_BufferRead(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead);\r
+u32 SPI_FLASH_ReadID(void);\r
+void SPI_FLASH_StartReadSequence(u32 ReadAddr);\r
+\r
+/*----- Low layer function -----*/\r
+u8 SPI_FLASH_ReadByte(void);\r
+void SPI_FLASH_ChipSelect(u8 State);\r
+u8 SPI_FLASH_SendByte(u8 byte);\r
+u16 SPI_FLASH_SendHalfWord(u16 HalfWord);\r
+void SPI_FLASH_WriteEnable(void);\r
+void SPI_FLASH_WaitForWriteEnd(void);\r
+\r
+#endif /* __SPI_FLASH_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_adc.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* ADC firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_ADC_H\r
+#define __STM32F10x_ADC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* ADC Init structure definition */\r
+typedef struct\r
+{\r
+ u32 ADC_Mode;\r
+ FunctionalState ADC_ScanConvMode; \r
+ FunctionalState ADC_ContinuousConvMode;\r
+ u32 ADC_ExternalTrigConv;\r
+ u32 ADC_DataAlign;\r
+ u8 ADC_NbrOfChannel;\r
+}ADC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* ADC dual mode -------------------------------------------------------------*/\r
+#define ADC_Mode_Independent ((u32)0x00000000)\r
+#define ADC_Mode_RegInjecSimult ((u32)0x00010000)\r
+#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)\r
+#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)\r
+#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)\r
+#define ADC_Mode_InjecSimult ((u32)0x00050000)\r
+#define ADC_Mode_RegSimult ((u32)0x00060000)\r
+#define ADC_Mode_FastInterl ((u32)0x00070000)\r
+#define ADC_Mode_SlowInterl ((u32)0x00080000)\r
+#define ADC_Mode_AlterTrig ((u32)0x00090000)\r
+\r
+#define IS_ADC_MODE(MODE) ((MODE == ADC_Mode_Independent) || \\r
+ (MODE == ADC_Mode_RegInjecSimult) || \\r
+ (MODE == ADC_Mode_RegSimult_AlterTrig) || \\r
+ (MODE == ADC_Mode_InjecSimult_FastInterl) || \\r
+ (MODE == ADC_Mode_InjecSimult_SlowInterl) || \\r
+ (MODE == ADC_Mode_InjecSimult) || \\r
+ (MODE == ADC_Mode_RegSimult) || \\r
+ (MODE == ADC_Mode_FastInterl) || \\r
+ (MODE == ADC_Mode_SlowInterl) || \\r
+ (MODE == ADC_Mode_AlterTrig))\r
+\r
+/* ADC extrenal trigger sources for regular channels conversion --------------*/\r
+#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)\r
+#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)\r
+#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)\r
+#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)\r
+#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)\r
+#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)\r
+#define ADC_ExternalTrigConv_Ext_IT11 ((u32)0x000C0000)\r
+#define ADC_ExternalTrigConv_None ((u32)0x000E0000)\r
+\r
+#define IS_ADC_EXT_TRIG(TRIG1) ((TRIG1 == ADC_ExternalTrigConv_T1_CC1) || \\r
+ (TRIG1 == ADC_ExternalTrigConv_T1_CC2) || \\r
+ (TRIG1 == ADC_ExternalTrigConv_T1_CC3) || \\r
+ (TRIG1 == ADC_ExternalTrigConv_T2_CC2) || \\r
+ (TRIG1 == ADC_ExternalTrigConv_T3_TRGO) || \\r
+ (TRIG1 == ADC_ExternalTrigConv_T4_CC4) || \\r
+ (TRIG1 == ADC_ExternalTrigConv_Ext_IT11) || \\r
+ (TRIG1 == ADC_ExternalTrigConv_None))\r
+\r
+/* ADC data align ------------------------------------------------------------*/\r
+#define ADC_DataAlign_Right ((u32)0x00000000)\r
+#define ADC_DataAlign_Left ((u32)0x00000800)\r
+\r
+#define IS_ADC_DATA_ALIGN(ALIGN) ((ALIGN == ADC_DataAlign_Right) || \\r
+ (ALIGN == ADC_DataAlign_Left))\r
+\r
+/* ADC channels --------------------------------------------------------------*/\r
+#define ADC_Channel_0 ((u8)0x00)\r
+#define ADC_Channel_1 ((u8)0x01)\r
+#define ADC_Channel_2 ((u8)0x02)\r
+#define ADC_Channel_3 ((u8)0x03)\r
+#define ADC_Channel_4 ((u8)0x04)\r
+#define ADC_Channel_5 ((u8)0x05)\r
+#define ADC_Channel_6 ((u8)0x06)\r
+#define ADC_Channel_7 ((u8)0x07)\r
+#define ADC_Channel_8 ((u8)0x08)\r
+#define ADC_Channel_9 ((u8)0x09)\r
+#define ADC_Channel_10 ((u8)0x0A)\r
+#define ADC_Channel_11 ((u8)0x0B)\r
+#define ADC_Channel_12 ((u8)0x0C)\r
+#define ADC_Channel_13 ((u8)0x0D)\r
+#define ADC_Channel_14 ((u8)0x0E)\r
+#define ADC_Channel_15 ((u8)0x0F)\r
+#define ADC_Channel_16 ((u8)0x10)\r
+#define ADC_Channel_17 ((u8)0x11)\r
+\r
+#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL == ADC_Channel_0) || (CHANNEL == ADC_Channel_1) || \\r
+ (CHANNEL == ADC_Channel_2) || (CHANNEL == ADC_Channel_3) || \\r
+ (CHANNEL == ADC_Channel_4) || (CHANNEL == ADC_Channel_5) || \\r
+ (CHANNEL == ADC_Channel_6) || (CHANNEL == ADC_Channel_7) || \\r
+ (CHANNEL == ADC_Channel_8) || (CHANNEL == ADC_Channel_9) || \\r
+ (CHANNEL == ADC_Channel_10) || (CHANNEL == ADC_Channel_11) || \\r
+ (CHANNEL == ADC_Channel_12) || (CHANNEL == ADC_Channel_13) || \\r
+ (CHANNEL == ADC_Channel_14) || (CHANNEL == ADC_Channel_15) || \\r
+ (CHANNEL == ADC_Channel_16) || (CHANNEL == ADC_Channel_17))\r
+\r
+/* ADC sampling times --------------------------------------------------------*/\r
+#define ADC_SampleTime_1Cycles5 ((u8)0x00)\r
+#define ADC_SampleTime_7Cycles5 ((u8)0x01)\r
+#define ADC_SampleTime_13Cycles5 ((u8)0x02)\r
+#define ADC_SampleTime_28Cycles5 ((u8)0x03)\r
+#define ADC_SampleTime_41Cycles5 ((u8)0x04)\r
+#define ADC_SampleTime_55Cycles5 ((u8)0x05)\r
+#define ADC_SampleTime_71Cycles5 ((u8)0x06)\r
+#define ADC_SampleTime_239Cycles5 ((u8)0x07)\r
+\r
+#define IS_ADC_SAMPLE_TIME(TIME) ((TIME == ADC_SampleTime_1Cycles5) || \\r
+ (TIME == ADC_SampleTime_7Cycles5) || \\r
+ (TIME == ADC_SampleTime_13Cycles5) || \\r
+ (TIME == ADC_SampleTime_28Cycles5) || \\r
+ (TIME == ADC_SampleTime_41Cycles5) || \\r
+ (TIME == ADC_SampleTime_55Cycles5) || \\r
+ (TIME == ADC_SampleTime_71Cycles5) || \\r
+ (TIME == ADC_SampleTime_239Cycles5))\r
+\r
+/* ADC extrenal trigger sources for injected channels conversion -------------*/\r
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)\r
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)\r
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)\r
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)\r
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)\r
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)\r
+#define ADC_ExternalTrigInjecConv_Ext_IT15 ((u32)0x00006000)\r
+#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG(TRIG) ((TRIG == ADC_ExternalTrigInjecConv_T1_TRGO) || \\r
+ (TRIG == ADC_ExternalTrigInjecConv_T1_CC4) || \\r
+ (TRIG == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
+ (TRIG == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
+ (TRIG == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
+ (TRIG == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
+ (TRIG == ADC_ExternalTrigInjecConv_Ext_IT15) || \\r
+ (TRIG == ADC_ExternalTrigInjecConv_None))\r
+\r
+/* ADC injected channel selection --------------------------------------------*/\r
+#define ADC_InjectedChannel_1 ((u8)0x14)\r
+#define ADC_InjectedChannel_2 ((u8)0x18)\r
+#define ADC_InjectedChannel_3 ((u8)0x1C)\r
+#define ADC_InjectedChannel_4 ((u8)0x20)\r
+\r
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) ((CHANNEL == ADC_InjectedChannel_1) || \\r
+ (CHANNEL == ADC_InjectedChannel_2) || \\r
+ (CHANNEL == ADC_InjectedChannel_3) || \\r
+ (CHANNEL == ADC_InjectedChannel_4))\r
+\r
+/* ADC analog watchdog selection ---------------------------------------------*/\r
+#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)\r
+#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)\r
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)\r
+#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)\r
+#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)\r
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)\r
+#define ADC_AnalogWatchdog_None ((u32)0x00000000)\r
+\r
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) ((WATCHDOG == ADC_AnalogWatchdog_SingleRegEnable) || \\r
+ (WATCHDOG == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
+ (WATCHDOG == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
+ (WATCHDOG == ADC_AnalogWatchdog_AllRegEnable) || \\r
+ (WATCHDOG == ADC_AnalogWatchdog_AllInjecEnable) || \\r
+ (WATCHDOG == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
+ (WATCHDOG == ADC_AnalogWatchdog_None))\r
+\r
+/* ADC interrupts definition -------------------------------------------------*/\r
+#define ADC_IT_EOC ((u16)0x0220)\r
+#define ADC_IT_AWD ((u16)0x0140)\r
+#define ADC_IT_JEOC ((u16)0x0480)\r
+\r
+#define IS_ADC_IT(IT) (((IT & (u16)0xF81F) == 0x00) && (IT != 0x00))\r
+#define IS_ADC_GET_IT(IT) ((IT == ADC_IT_EOC) || (IT == ADC_IT_AWD) || \\r
+ (IT == ADC_IT_JEOC))\r
+\r
+/* ADC flags definition ------------------------------------------------------*/\r
+#define ADC_FLAG_AWD ((u8)0x01)\r
+#define ADC_FLAG_EOC ((u8)0x02)\r
+#define ADC_FLAG_JEOC ((u8)0x04)\r
+#define ADC_FLAG_JSTRT ((u8)0x08)\r
+#define ADC_FLAG_STRT ((u8)0x10)\r
+\r
+#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG & (u8)0xE0) == 0x00) && (FLAG != 0x00))\r
+#define IS_ADC_GET_FLAG(FLAG) ((FLAG == ADC_FLAG_AWD) || (FLAG == ADC_FLAG_EOC) || \\r
+ (FLAG == ADC_FLAG_JEOC) || (FLAG == ADC_FLAG_JSTRT) || \\r
+ (FLAG == ADC_FLAG_STRT))\r
+\r
+/* ADC thresholds ------------------------------------------------------------*/\r
+#define IS_ADC_THRESHOLD(THRESHOLD) (THRESHOLD <= 0xFFF)\r
+\r
+/* ADC injected offset -------------------------------------------------------*/\r
+#define IS_ADC_OFFSET(OFFSET) (OFFSET <= 0xFFF)\r
+\r
+/* ADC injected length -------------------------------------------------------*/\r
+#define IS_ADC_INJECTED_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x4))\r
+\r
+/* ADC injected rank ---------------------------------------------------------*/\r
+#define IS_ADC_INJECTED_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x4))\r
+\r
+/* ADC regular length --------------------------------------------------------*/\r
+#define IS_ADC_REGULAR_LENGTH(LENGTH) ((LENGTH >= 0x1) && (LENGTH <= 0x10))\r
+\r
+/* ADC regular rank ----------------------------------------------------------*/\r
+#define IS_ADC_REGULAR_RANK(RANK) ((RANK >= 0x1) && (RANK <= 0x10))\r
+\r
+/* ADC regular discontinuous mode number -------------------------------------*/\r
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) ((NUMBER >= 0x1) && (NUMBER <= 0x8))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void ADC_DeInit(ADC_TypeDef* ADCx);\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);\r
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);\r
+void ADC_StartCalibration(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);\r
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);\r
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
+u32 ADC_GetDualModeConversionValue(void);\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);\r
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);\r
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);\r
+void ADC_TempSensorCmd(FunctionalState NewState);\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);\r
+\r
+#endif /*__STM32F10x_ADC_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_bkp.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* BKP firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_BKP_H\r
+#define __STM32F10x_BKP_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Tamper Pin active level*/\r
+#define BKP_TamperPinLevel_High ((u16)0x0000)\r
+#define BKP_TamperPinLevel_Low ((u16)0x0001)\r
+\r
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) ((LEVEL == BKP_TamperPinLevel_High) || \\r
+ (LEVEL == BKP_TamperPinLevel_Low))\r
+\r
+/* Data Backup Register */\r
+#define BKP_DR1 ((u16)0x0004)\r
+#define BKP_DR2 ((u16)0x0008)\r
+#define BKP_DR3 ((u16)0x000C)\r
+#define BKP_DR4 ((u16)0x0010)\r
+#define BKP_DR5 ((u16)0x0014)\r
+#define BKP_DR6 ((u16)0x0018)\r
+#define BKP_DR7 ((u16)0x001C)\r
+#define BKP_DR8 ((u16)0x0020)\r
+#define BKP_DR9 ((u16)0x0024)\r
+#define BKP_DR10 ((u16)0x0028)\r
+\r
+#define IS_BKP_DR(DR) ((DR == BKP_DR1) || (DR == BKP_DR2) || (DR == BKP_DR3) || \\r
+ (DR == BKP_DR4) || (DR == BKP_DR5) || (DR == BKP_DR6) || \\r
+ (DR == BKP_DR7) || (DR == BKP_DR8) || (DR == BKP_DR9) || \\r
+ (DR == BKP_DR10))\r
+\r
+#define IS_BKP_CALIBRATION_VALUE(VALUE) (VALUE <= 0x7F)\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void BKP_DeInit(void);\r
+void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel);\r
+void BKP_TamperPinCmd(FunctionalState NewState);\r
+void BKP_ITConfig(FunctionalState NewState);\r
+void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState);\r
+void BKP_SetRTCCalibrationValue(u8 CalibrationValue);\r
+void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data);\r
+u16 BKP_ReadBackupRegister(u16 BKP_DR);\r
+FlagStatus BKP_GetFlagStatus(void);\r
+void BKP_ClearFlag(void);\r
+ITStatus BKP_GetITStatus(void);\r
+void BKP_ClearITPendingBit(void);\r
+\r
+#endif /* __STM32F10x_BKP_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_can.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* CAN firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CAN_H\r
+#define __STM32F10x_CAN_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* CAN init structure definition */\r
+typedef struct\r
+{\r
+ FunctionalState CAN_TTCM;\r
+ FunctionalState CAN_ABOM;\r
+ FunctionalState CAN_AWUM;\r
+ FunctionalState CAN_NART;\r
+ FunctionalState CAN_RFLM;\r
+ FunctionalState CAN_TXFP;\r
+ u8 CAN_Mode;\r
+ u8 CAN_SJW;\r
+ u8 CAN_BS1;\r
+ u8 CAN_BS2;\r
+ u8 CAN_Clock;\r
+ u16 CAN_Prescaler;\r
+} CAN_InitTypeDef;\r
+\r
+/* CAN filter init structure definition */\r
+typedef struct\r
+{\r
+ u8 CAN_FilterNumber;\r
+ u8 CAN_FilterMode;\r
+ u8 CAN_FilterScale;\r
+ u16 CAN_FilterIdHigh;\r
+ u16 CAN_FilterIdLow;\r
+ u16 CAN_FilterMaskIdHigh;\r
+ u16 CAN_FilterMaskIdLow;\r
+ u16 CAN_FilterFIFOAssignment;\r
+ FunctionalState CAN_FilterActivation;\r
+} CAN_FilterInitTypeDef;\r
+\r
+/* CAN Tx message structure definition */\r
+typedef struct\r
+{\r
+ u32 StdId;\r
+ u32 ExtId;\r
+ u8 IDE;\r
+ u8 RTR;\r
+ u8 DLC;\r
+ u8 Data[8];\r
+} CanTxMsg;\r
+\r
+/* CAN Rx message structure definition */\r
+typedef struct\r
+{\r
+ u32 StdId;\r
+ u32 ExtId;\r
+ u8 IDE;\r
+ u8 RTR;\r
+ u8 DLC;\r
+ u8 Data[8];\r
+ u8 FMI;\r
+} CanRxMsg;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* CAN sleep constants */\r
+#define CANINITFAILED ((u8)0x00) /* CAN initialization failed */\r
+#define CANINITOK ((u8)0x01) /* CAN initialization failed */\r
+\r
+/* CAN operating mode */\r
+#define CAN_Mode_Normal ((u8)0x00) /* normal mode */\r
+#define CAN_Mode_LoopBack ((u8)0x01) /* loopback mode */\r
+#define CAN_Mode_Silent ((u8)0x02) /* silent mode */\r
+#define CAN_Mode_Silent_LoopBack ((u8)0x03) /* loopback combined with silent mode */\r
+\r
+#define IS_CAN_MODE(MODE) ((MODE == CAN_Mode_Normal) || (MODE == CAN_Mode_LoopBack)|| \\r
+ (MODE == CAN_Mode_Silent) || (MODE == CAN_Mode_Silent_LoopBack))\r
+\r
+/* CAN synchronisation jump width */\r
+#define CAN_SJW_0tq ((u8)0x00) /* 0 time quantum */\r
+#define CAN_SJW_1tq ((u8)0x01) /* 1 time quantum */\r
+#define CAN_SJW_2tq ((u8)0x02) /* 2 time quantum */\r
+#define CAN_SJW_3tq ((u8)0x03) /* 3 time quantum */\r
+\r
+#define IS_CAN_SJW(SJW) ((SJW == CAN_SJW_0tq) || (SJW == CAN_SJW_1tq)|| \\r
+ (SJW == CAN_SJW_2tq) || (SJW == CAN_SJW_3tq))\r
+\r
+/* time quantum in bit segment 1 */\r
+#define CAN_BS1_1tq ((u8)0x00) /* 1 time quantum */\r
+#define CAN_BS1_2tq ((u8)0x01) /* 2 time quantum */\r
+#define CAN_BS1_3tq ((u8)0x02) /* 3 time quantum */\r
+#define CAN_BS1_4tq ((u8)0x03) /* 4 time quantum */\r
+#define CAN_BS1_5tq ((u8)0x04) /* 5 time quantum */\r
+#define CAN_BS1_6tq ((u8)0x05) /* 6 time quantum */\r
+#define CAN_BS1_7tq ((u8)0x06) /* 7 time quantum */\r
+#define CAN_BS1_8tq ((u8)0x07) /* 8 time quantum */\r
+#define CAN_BS1_9tq ((u8)0x08) /* 9 time quantum */\r
+#define CAN_BS1_10tq ((u8)0x09) /* 10 time quantum */\r
+#define CAN_BS1_11tq ((u8)0x0A) /* 11 time quantum */\r
+#define CAN_BS1_12tq ((u8)0x0B) /* 12 time quantum */\r
+#define CAN_BS1_13tq ((u8)0x0C) /* 13 time quantum */\r
+#define CAN_BS1_14tq ((u8)0x0D) /* 14 time quantum */\r
+#define CAN_BS1_15tq ((u8)0x0E) /* 15 time quantum */\r
+#define CAN_BS1_16tq ((u8)0x0F) /* 16 time quantum */\r
+\r
+#define IS_CAN_BS1(BS1) (BS1 <= CAN_BS1_16tq)\r
+\r
+/* time quantum in bit segment 2 */\r
+#define CAN_BS2_1tq ((u8)0x00) /* 1 time quantum */\r
+#define CAN_BS2_2tq ((u8)0x01) /* 2 time quantum */\r
+#define CAN_BS2_3tq ((u8)0x02) /* 3 time quantum */\r
+#define CAN_BS2_4tq ((u8)0x03) /* 4 time quantum */\r
+#define CAN_BS2_5tq ((u8)0x04) /* 5 time quantum */\r
+#define CAN_BS2_6tq ((u8)0x05) /* 6 time quantum */\r
+#define CAN_BS2_7tq ((u8)0x06) /* 7 time quantum */\r
+#define CAN_BS2_8tq ((u8)0x07) /* 8 time quantum */\r
+\r
+#define IS_CAN_BS2(BS2) (BS2 <= CAN_BS2_8tq)\r
+\r
+/* CAN clock selected */\r
+#define CAN_Clock_8MHz ((u8)0x00) /* 8MHz XTAL clock selected */\r
+#define CAN_Clock_APB ((u8)0x01) /* APB clock selected */\r
+\r
+#define IS_CAN_CLOCK(CLOCK) ((CLOCK == CAN_Clock_8MHz) || (CLOCK == CAN_Clock_APB))\r
+\r
+/* CAN clock prescaler */\r
+#define IS_CAN_PRESCALER(PRESCALER) ((PRESCALER >= 1) && (PRESCALER <= 1024))\r
+\r
+/* CAN filter number */\r
+#define IS_CAN_FILTER_NUMBER(NUMBER) (NUMBER <= 13)\r
+\r
+/* CAN filter mode */\r
+#define CAN_FilterMode_IdMask ((u8)0x00) /* id/mask mode */\r
+#define CAN_FilterMode_IdList ((u8)0x01) /* identifier list mode */\r
+\r
+#define IS_CAN_FILTER_MODE(MODE) ((MODE == CAN_FilterMode_IdMask) || \\r
+ (MODE == CAN_FilterMode_IdList))\r
+\r
+/* CAN filter scale */\r
+#define CAN_FilterScale_16bit ((u8)0x00) /* 16-bit filter scale */\r
+#define CAN_FilterScale_32bit ((u8)0x01) /* 2-bit filter scale */\r
+\r
+#define IS_CAN_FILTER_SCALE(SCALE) ((SCALE == CAN_FilterScale_16bit) || \\r
+ (SCALE == CAN_FilterScale_32bit))\r
+\r
+/* CAN filter FIFO assignation */\r
+#define CAN_FilterFIFO0 ((u8)0x00) /* Filter FIFO 0 assignment for filter x */\r
+#define CAN_FilterFIFO1 ((u8)0x01) /* Filter FIFO 1 assignment for filter x */\r
+\r
+#define IS_CAN_FILTER_FIFO(FIFO) ((FIFO == CAN_FilterFIFO0) || \\r
+ (FIFO == CAN_FilterFIFO1))\r
+\r
+/* CAN Tx */\r
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) (TRANSMITMAILBOX <= ((u8)0x02))\r
+#define IS_CAN_STDID(STDID) (STDID <= ((u32)0x7FF))\r
+#define IS_CAN_EXTID(EXTID) (EXTID <= ((u32)0x3FFFF))\r
+#define IS_CAN_DLC(DLC) (DLC <= ((u8)0x08))\r
+\r
+/* CAN identifier type */\r
+#define CAN_ID_STD ((u32)0x00000000) /* Standard Id */\r
+#define CAN_ID_EXT ((u32)0x00000004) /* Extended Id */\r
+\r
+#define IS_CAN_IDTYPE(IDTYPE) ((IDTYPE == CAN_ID_STD) || (IDTYPE == CAN_ID_EXT))\r
+\r
+/* CAN remote transmission request */\r
+#define CAN_RTR_DATA ((u32)0x00000000) /* Data frame */\r
+#define CAN_RTR_REMOTE ((u32)0x00000002) /* Remote frame */\r
+\r
+#define IS_CAN_RTR(RTR) ((RTR == CAN_RTR_DATA) || (RTR == CAN_RTR_REMOTE))\r
+\r
+/* CAN transmit constants */\r
+#define CANTXFAILED ((u8)0x00) /* CAN transmission failed */\r
+#define CANTXOK ((u8)0x01) /* CAN transmission succeeded */\r
+#define CANTXPENDING ((u8)0x02) /* CAN transmission pending */\r
+#define CAN_NO_MB ((u8)0x04) /* CAN cell did not provide an empty mailbox */\r
+\r
+/* CAN receive FIFO number constants */\r
+#define CAN_FIFO0 ((u8)0x00) /* CAN FIFO0 used to receive */\r
+#define CAN_FIFO1 ((u8)0x01) /* CAN FIFO1 used to receive */\r
+\r
+#define IS_CAN_FIFO(FIFO) ((FIFO == CAN_FIFO0) || (FIFO == CAN_FIFO1))\r
+\r
+/* CAN sleep constants */\r
+#define CANSLEEPFAILED ((u8)0x00) /* CAN did not enter the sleep mode */\r
+#define CANSLEEPOK ((u8)0x01) /* CAN entered the sleep mode */\r
+\r
+/* CAN wake up constants */\r
+#define CANWAKEUPFAILED ((u8)0x00) /* CAN did not leave the sleep mode */\r
+#define CANWAKEUPOK ((u8)0x01) /* CAN leaved the sleep mode */\r
+\r
+/* CAN flags */\r
+#define CAN_FLAG_EWG ((u32)0x00000001) /* Error Warning Flag */\r
+#define CAN_FLAG_EPV ((u32)0x00000002) /* Error Passive Flag */\r
+#define CAN_FLAG_BOF ((u32)0x00000004) /* Bus-Off Flag */\r
+\r
+#define IS_CAN_FLAG(FLAG) ((FLAG == CAN_FLAG_EWG) || (FLAG == CAN_FLAG_EPV) ||\\r
+ (FLAG == CAN_FLAG_BOF))\r
+\r
+/* CAN interrupts */\r
+#define CAN_IT_RQCP0 ((u8)0x05) /* Request completed mailbox 0 */\r
+#define CAN_IT_RQCP1 ((u8)0x06) /* Request completed mailbox 1 */\r
+#define CAN_IT_RQCP2 ((u8)0x07) /* Request completed mailbox 2 */\r
+#define CAN_IT_TME ((u32)0x00000001) /* Transmit mailbox empty */\r
+#define CAN_IT_FMP0 ((u32)0x00000002) /* FIFO 0 message pending */\r
+#define CAN_IT_FF0 ((u32)0x00000004) /* FIFO 0 full */\r
+#define CAN_IT_FOV0 ((u32)0x00000008) /* FIFO 0 overrun */\r
+#define CAN_IT_FMP1 ((u32)0x00000010) /* FIFO 1 message pending */\r
+#define CAN_IT_FF1 ((u32)0x00000020) /* FIFO 1 full */\r
+#define CAN_IT_FOV1 ((u32)0x00000040) /* FIFO 1 overrun */\r
+#define CAN_IT_EWG ((u32)0x00000100) /* Error warning */\r
+#define CAN_IT_EPV ((u32)0x00000200) /* Error passive */\r
+#define CAN_IT_BOF ((u32)0x00000400) /* Bus-off */\r
+#define CAN_IT_LEC ((u32)0x00000800) /* Last error code */\r
+#define CAN_IT_ERR ((u32)0x00008000) /* Error */\r
+#define CAN_IT_WKU ((u32)0x00010000) /* Wake-up */\r
+#define CAN_IT_SLK ((u32)0x00020000) /* Sleep */\r
+\r
+#define IS_CAN_IT(IT) ((IT == CAN_IT_RQCP0) || (IT == CAN_IT_RQCP1) ||\\r
+ (IT == CAN_IT_RQCP2) || (IT == CAN_IT_TME) ||\\r
+ (IT == CAN_IT_FMP0) || (IT == CAN_IT_FF0) ||\\r
+ (IT == CAN_IT_FOV0) || (IT == CAN_IT_FMP1) ||\\r
+ (IT == CAN_IT_FF1) || (IT == CAN_IT_FOV1) ||\\r
+ (IT == CAN_IT_EWG) || (IT == CAN_IT_EPV) ||\\r
+ (IT == CAN_IT_BOF) || (IT == CAN_IT_LEC) ||\\r
+ (IT == CAN_IT_ERR) || (IT == CAN_IT_WKU) ||\\r
+ (IT == CAN_IT_SLK))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported function protypes ----------------------------------------------- */\r
+void CAN_DeInit(void);\r
+u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct);\r
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);\r
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);\r
+void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState);\r
+u8 CAN_Transmit(CanTxMsg* TxMessage);\r
+u32 CAN_TransmitStatus(u8 TransmitMailbox);\r
+void CAN_CancelTransmit(u8 Mailbox);\r
+void CAN_FIFORelease(u8 FIFONumber);\r
+u8 CAN_MessagePending(u8 FIFONumber);\r
+void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage);\r
+u8 CAN_Sleep(void);\r
+u8 CAN_WakeUp(void);\r
+FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG);\r
+void CAN_ClearFlag(u32 CAN_FLAG);\r
+ITStatus CAN_GetITStatus(u32 CAN_IT);\r
+void CAN_ClearITPendingBit(u32 CAN_IT);\r
+\r
+#endif /* __STM32F10x_CAN_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_dma.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* DMA firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DMA_H\r
+#define __STM32F10x_DMA_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* DMA Init structure definition */\r
+typedef struct\r
+{\r
+ u32 DMA_PeripheralBaseAddr;\r
+ u32 DMA_MemoryBaseAddr; \r
+ u32 DMA_DIR; \r
+ u32 DMA_BufferSize; \r
+ u32 DMA_PeripheralInc; \r
+ u32 DMA_MemoryInc;\r
+ u32 DMA_PeripheralDataSize;\r
+ u32 DMA_MemoryDataSize;\r
+ u32 DMA_Mode; \r
+ u32 DMA_Priority; \r
+ u32 DMA_M2M; \r
+}DMA_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* DMA data transfer direction -----------------------------------------------*/\r
+#define DMA_DIR_PeripheralDST ((u32)0x00000010)\r
+#define DMA_DIR_PeripheralSRC ((u32)0x00000000)\r
+\r
+#define IS_DMA_DIR(DIR) ((DIR == DMA_DIR_PeripheralDST) || \\r
+ (DIR == DMA_DIR_PeripheralSRC))\r
+\r
+/* DMA peripheral incremented mode -------------------------------------------*/\r
+#define DMA_PeripheralInc_Enable ((u32)0x00000040)\r
+#define DMA_PeripheralInc_Disable ((u32)0x00000000)\r
+\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) ((STATE == DMA_PeripheralInc_Enable) || \\r
+ (STATE == DMA_PeripheralInc_Disable))\r
+\r
+/* DMA memory incremented mode -----------------------------------------------*/\r
+#define DMA_MemoryInc_Enable ((u32)0x00000080)\r
+#define DMA_MemoryInc_Disable ((u32)0x00000000)\r
+\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) ((STATE == DMA_MemoryInc_Enable) || \\r
+ (STATE == DMA_MemoryInc_Disable))\r
+\r
+/* DMA peripheral data size --------------------------------------------------*/\r
+#define DMA_PeripheralDataSize_Byte ((u32)0x00000000)\r
+#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)\r
+#define DMA_PeripheralDataSize_Word ((u32)0x00000200)\r
+\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) ((SIZE == DMA_PeripheralDataSize_Byte) || \\r
+ (SIZE == DMA_PeripheralDataSize_HalfWord) || \\r
+ (SIZE == DMA_PeripheralDataSize_Word))\r
+\r
+/* DMA memory data size ------------------------------------------------------*/\r
+#define DMA_MemoryDataSize_Byte ((u32)0x00000000)\r
+#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)\r
+#define DMA_MemoryDataSize_Word ((u32)0x00000800)\r
+\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) ((SIZE == DMA_MemoryDataSize_Byte) || \\r
+ (SIZE == DMA_MemoryDataSize_HalfWord) || \\r
+ (SIZE == DMA_MemoryDataSize_Word))\r
+\r
+/* DMA circular/normal mode --------------------------------------------------*/\r
+#define DMA_Mode_Circular ((u32)0x00000020)\r
+#define DMA_Mode_Normal ((u32)0x00000000)\r
+\r
+#define IS_DMA_MODE(MODE) ((MODE == DMA_Mode_Circular) || (MODE == DMA_Mode_Normal))\r
+\r
+/* DMA priority level --------------------------------------------------------*/\r
+#define DMA_Priority_VeryHigh ((u32)0x00003000)\r
+#define DMA_Priority_High ((u32)0x00002000)\r
+#define DMA_Priority_Medium ((u32)0x00001000)\r
+#define DMA_Priority_Low ((u32)0x00000000)\r
+\r
+#define IS_DMA_PRIORITY(PRIORITY) ((PRIORITY == DMA_Priority_VeryHigh) || \\r
+ (PRIORITY == DMA_Priority_High) || \\r
+ (PRIORITY == DMA_Priority_Medium) || \\r
+ (PRIORITY == DMA_Priority_Low))\r
+\r
+/* DMA memory to memory ------------------------------------------------------*/\r
+#define DMA_M2M_Enable ((u32)0x00004000)\r
+#define DMA_M2M_Disable ((u32)0x00000000)\r
+\r
+#define IS_DMA_M2M_STATE(STATE) ((STATE == DMA_M2M_Enable) || (STATE == DMA_M2M_Disable))\r
+\r
+/* DMA interrupts definition -------------------------------------------------*/\r
+#define DMA_IT_TC ((u32)0x00000002)\r
+#define DMA_IT_HT ((u32)0x00000004)\r
+#define DMA_IT_TE ((u32)0x00000008)\r
+\r
+#define IS_DMA_CONFIG_IT(IT) (((IT & 0xFFFFFFF1) == 0x00) && (IT != 0x00))\r
+\r
+#define DMA_IT_GL1 ((u32)0x00000001)\r
+#define DMA_IT_TC1 ((u32)0x00000002)\r
+#define DMA_IT_HT1 ((u32)0x00000004)\r
+#define DMA_IT_TE1 ((u32)0x00000008)\r
+#define DMA_IT_GL2 ((u32)0x00000010)\r
+#define DMA_IT_TC2 ((u32)0x00000020)\r
+#define DMA_IT_HT2 ((u32)0x00000040)\r
+#define DMA_IT_TE2 ((u32)0x00000080)\r
+#define DMA_IT_GL3 ((u32)0x00000100)\r
+#define DMA_IT_TC3 ((u32)0x00000200)\r
+#define DMA_IT_HT3 ((u32)0x00000400)\r
+#define DMA_IT_TE3 ((u32)0x00000800)\r
+#define DMA_IT_GL4 ((u32)0x00001000)\r
+#define DMA_IT_TC4 ((u32)0x00002000)\r
+#define DMA_IT_HT4 ((u32)0x00004000)\r
+#define DMA_IT_TE4 ((u32)0x00008000)\r
+#define DMA_IT_GL5 ((u32)0x00010000)\r
+#define DMA_IT_TC5 ((u32)0x00020000)\r
+#define DMA_IT_HT5 ((u32)0x00040000)\r
+#define DMA_IT_TE5 ((u32)0x00080000)\r
+#define DMA_IT_GL6 ((u32)0x00100000)\r
+#define DMA_IT_TC6 ((u32)0x00200000)\r
+#define DMA_IT_HT6 ((u32)0x00400000)\r
+#define DMA_IT_TE6 ((u32)0x00800000)\r
+#define DMA_IT_GL7 ((u32)0x01000000)\r
+#define DMA_IT_TC7 ((u32)0x02000000)\r
+#define DMA_IT_HT7 ((u32)0x04000000)\r
+#define DMA_IT_TE7 ((u32)0x08000000)\r
+\r
+#define IS_DMA_CLEAR_IT(IT) (((IT & 0xF0000000) == 0x00) && (IT != 0x00))\r
+#define IS_DMA_GET_IT(IT) ((IT == DMA_IT_GL1) || (IT == DMA_IT_TC1) || \\r
+ (IT == DMA_IT_HT1) || (IT == DMA_IT_TE1) || \\r
+ (IT == DMA_IT_GL2) || (IT == DMA_IT_TC2) || \\r
+ (IT == DMA_IT_HT2) || (IT == DMA_IT_TE2) || \\r
+ (IT == DMA_IT_GL3) || (IT == DMA_IT_TC3) || \\r
+ (IT == DMA_IT_HT3) || (IT == DMA_IT_TE3) || \\r
+ (IT == DMA_IT_GL4) || (IT == DMA_IT_TC4) || \\r
+ (IT == DMA_IT_HT4) || (IT == DMA_IT_TE4) || \\r
+ (IT == DMA_IT_GL5) || (IT == DMA_IT_TC5) || \\r
+ (IT == DMA_IT_HT5) || (IT == DMA_IT_TE5) || \\r
+ (IT == DMA_IT_GL6) || (IT == DMA_IT_TC6) || \\r
+ (IT == DMA_IT_HT6) || (IT == DMA_IT_TE6) || \\r
+ (IT == DMA_IT_GL7) || (IT == DMA_IT_TC7) || \\r
+ (IT == DMA_IT_HT7) || (IT == DMA_IT_TE7))\r
+\r
+/* DMA flags definition ------------------------------------------------------*/\r
+#define DMA_FLAG_GL1 ((u32)0x00000001)\r
+#define DMA_FLAG_TC1 ((u32)0x00000002)\r
+#define DMA_FLAG_HT1 ((u32)0x00000004)\r
+#define DMA_FLAG_TE1 ((u32)0x00000008)\r
+#define DMA_FLAG_GL2 ((u32)0x00000010)\r
+#define DMA_FLAG_TC2 ((u32)0x00000020)\r
+#define DMA_FLAG_HT2 ((u32)0x00000040)\r
+#define DMA_FLAG_TE2 ((u32)0x00000080)\r
+#define DMA_FLAG_GL3 ((u32)0x00000100)\r
+#define DMA_FLAG_TC3 ((u32)0x00000200)\r
+#define DMA_FLAG_HT3 ((u32)0x00000400)\r
+#define DMA_FLAG_TE3 ((u32)0x00000800)\r
+#define DMA_FLAG_GL4 ((u32)0x00001000)\r
+#define DMA_FLAG_TC4 ((u32)0x00002000)\r
+#define DMA_FLAG_HT4 ((u32)0x00004000)\r
+#define DMA_FLAG_TE4 ((u32)0x00008000)\r
+#define DMA_FLAG_GL5 ((u32)0x00010000)\r
+#define DMA_FLAG_TC5 ((u32)0x00020000)\r
+#define DMA_FLAG_HT5 ((u32)0x00040000)\r
+#define DMA_FLAG_TE5 ((u32)0x00080000)\r
+#define DMA_FLAG_GL6 ((u32)0x00100000)\r
+#define DMA_FLAG_TC6 ((u32)0x00200000)\r
+#define DMA_FLAG_HT6 ((u32)0x00400000)\r
+#define DMA_FLAG_TE6 ((u32)0x00800000)\r
+#define DMA_FLAG_GL7 ((u32)0x01000000)\r
+#define DMA_FLAG_TC7 ((u32)0x02000000)\r
+#define DMA_FLAG_HT7 ((u32)0x04000000)\r
+#define DMA_FLAG_TE7 ((u32)0x08000000)\r
+\r
+#define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG & 0xF0000000) == 0x00) && (FLAG != 0x00))\r
+#define IS_DMA_GET_FLAG(FLAG) ((FLAG == DMA_FLAG_GL1) || (FLAG == DMA_FLAG_TC1) || \\r
+ (FLAG == DMA_FLAG_HT1) || (FLAG == DMA_FLAG_TE1) || \\r
+ (FLAG == DMA_FLAG_GL2) || (FLAG == DMA_FLAG_TC2) || \\r
+ (FLAG == DMA_FLAG_HT2) || (FLAG == DMA_FLAG_TE2) || \\r
+ (FLAG == DMA_FLAG_GL3) || (FLAG == DMA_FLAG_TC3) || \\r
+ (FLAG == DMA_FLAG_HT3) || (FLAG == DMA_FLAG_TE3) || \\r
+ (FLAG == DMA_FLAG_GL4) || (FLAG == DMA_FLAG_TC4) || \\r
+ (FLAG == DMA_FLAG_HT4) || (FLAG == DMA_FLAG_TE4) || \\r
+ (FLAG == DMA_FLAG_GL5) || (FLAG == DMA_FLAG_TC5) || \\r
+ (FLAG == DMA_FLAG_HT5) || (FLAG == DMA_FLAG_TE5) || \\r
+ (FLAG == DMA_FLAG_GL6) || (FLAG == DMA_FLAG_TC6) || \\r
+ (FLAG == DMA_FLAG_HT6) || (FLAG == DMA_FLAG_TE6) || \\r
+ (FLAG == DMA_FLAG_GL7) || (FLAG == DMA_FLAG_TC7) || \\r
+ (FLAG == DMA_FLAG_HT7) || (FLAG == DMA_FLAG_TE7))\r
+\r
+/* DMA Buffer Size -----------------------------------------------------------*/\r
+#define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE >= 0x1) && (SIZE < 0x10000))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx);\r
+void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState);\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState);\r
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx);\r
+FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);\r
+void DMA_ClearFlag(u32 DMA_FLAG);\r
+ITStatus DMA_GetITStatus(u32 DMA_IT);\r
+void DMA_ClearITPendingBit(u32 DMA_IT);\r
+\r
+#endif /*__STM32F10x_DMA_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_exti.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* EXTI firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_EXTI_H\r
+#define __STM32F10x_EXTI_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* EXTI mode enumeration -----------------------------------------------------*/\r
+typedef enum\r
+{\r
+ EXTI_Mode_Interrupt = 0x00,\r
+ EXTI_Mode_Event = 0x04\r
+}EXTIMode_TypeDef;\r
+\r
+#define IS_EXTI_MODE(MODE) ((MODE == EXTI_Mode_Interrupt) || (MODE == EXTI_Mode_Event))\r
+ \r
+/* EXTI Trigger enumeration --------------------------------------------------*/\r
+typedef enum\r
+{\r
+ EXTI_Trigger_Rising = 0x08,\r
+ EXTI_Trigger_Falling = 0x0C, \r
+ EXTI_Trigger_Rising_Falling = 0x10\r
+}EXTITrigger_TypeDef;\r
+\r
+#define IS_EXTI_TRIGGER(TRIGGER) ((TRIGGER == EXTI_Trigger_Rising) || \\r
+ (TRIGGER == EXTI_Trigger_Falling) || \\r
+ (TRIGGER == EXTI_Trigger_Rising_Falling))\r
+\r
+/* EXTI Init Structure definition --------------------------------------------*/\r
+typedef struct\r
+{\r
+ u32 EXTI_Line;\r
+ EXTIMode_TypeDef EXTI_Mode;\r
+ EXTITrigger_TypeDef EXTI_Trigger;\r
+ FunctionalState EXTI_LineCmd;\r
+}EXTI_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* EXTI Lines ----------------------------------------------------------------*/\r
+#define EXTI_Line0 ((u32)0x00001) /* External interrupt line 0 */\r
+#define EXTI_Line1 ((u32)0x00002) /* External interrupt line 1 */\r
+#define EXTI_Line2 ((u32)0x00004) /* External interrupt line 2 */\r
+#define EXTI_Line3 ((u32)0x00008) /* External interrupt line 3 */\r
+#define EXTI_Line4 ((u32)0x00010) /* External interrupt line 4 */\r
+#define EXTI_Line5 ((u32)0x00020) /* External interrupt line 5 */\r
+#define EXTI_Line6 ((u32)0x00040) /* External interrupt line 6 */\r
+#define EXTI_Line7 ((u32)0x00080) /* External interrupt line 7 */\r
+#define EXTI_Line8 ((u32)0x00100) /* External interrupt line 8 */\r
+#define EXTI_Line9 ((u32)0x00200) /* External interrupt line 9 */\r
+#define EXTI_Line10 ((u32)0x00400) /* External interrupt line 10 */\r
+#define EXTI_Line11 ((u32)0x00800) /* External interrupt line 11 */\r
+#define EXTI_Line12 ((u32)0x01000) /* External interrupt line 12 */\r
+#define EXTI_Line13 ((u32)0x02000) /* External interrupt line 13 */\r
+#define EXTI_Line14 ((u32)0x04000) /* External interrupt line 14 */\r
+#define EXTI_Line15 ((u32)0x08000) /* External interrupt line 15 */\r
+#define EXTI_Line16 ((u32)0x10000) /* External interrupt line 16\r
+ Connected to the PVD Output */\r
+#define EXTI_Line17 ((u32)0x20000) /* External interrupt line 17 \r
+ Connected to the RTC Alarm event */\r
+#define EXTI_Line18 ((u32)0x40000) /* External interrupt line 18 \r
+ Connected to the USB Wakeup from \r
+ suspend event */\r
+\r
+#define IS_EXTI_LINE(LINE) (((LINE & (u32)0xFFF80000) == 0x00) && (LINE != (u16)0x00))\r
+\r
+#define IS_GET_EXTI_LINE(LINE) ((LINE == EXTI_Line0) || (LINE == EXTI_Line1) || \\r
+ (LINE == EXTI_Line2) || (LINE == EXTI_Line3) || \\r
+ (LINE == EXTI_Line4) || (LINE == EXTI_Line5) || \\r
+ (LINE == EXTI_Line6) || (LINE == EXTI_Line7) || \\r
+ (LINE == EXTI_Line8) || (LINE == EXTI_Line9) || \\r
+ (LINE == EXTI_Line10) || (LINE == EXTI_Line11) || \\r
+ (LINE == EXTI_Line12) || (LINE == EXTI_Line13) || \\r
+ (LINE == EXTI_Line14) || (LINE == EXTI_Line15) || \\r
+ (LINE == EXTI_Line16) || (LINE == EXTI_Line17) || \\r
+ (LINE == EXTI_Line18))\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void EXTI_DeInit(void);\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_GenerateSWInterrupt(u32 EXTI_Line);\r
+FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line);\r
+void EXTI_ClearFlag(u32 EXTI_Line);\r
+ITStatus EXTI_GetITStatus(u32 EXTI_Line);\r
+void EXTI_ClearITPendingBit(u32 EXTI_Line);\r
+\r
+#endif /* __STM32F10x_EXTI_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_gpio.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* GPIO firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_GPIO_H\r
+#define __STM32F10x_GPIO_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Output Maximum frequency selection ----------------------------------------*/\r
+typedef enum\r
+{ \r
+ GPIO_Speed_10MHz = 1,\r
+ GPIO_Speed_2MHz, \r
+ GPIO_Speed_50MHz\r
+}GPIOSpeed_TypeDef;\r
+\r
+#define IS_GPIO_SPEED(SPEED) ((SPEED == GPIO_Speed_10MHz) || (SPEED == GPIO_Speed_2MHz) || \\r
+ (SPEED == GPIO_Speed_50MHz))\r
+ \r
+/* Configuration Mode enumeration --------------------------------------------*/\r
+typedef enum\r
+{ GPIO_Mode_AIN = 0x0,\r
+ GPIO_Mode_IN_FLOATING = 0x04,\r
+ GPIO_Mode_IPD = 0x28,\r
+ GPIO_Mode_IPU = 0x48,\r
+ GPIO_Mode_Out_OD = 0x14,\r
+ GPIO_Mode_Out_PP = 0x10,\r
+ GPIO_Mode_AF_OD = 0x1C,\r
+ GPIO_Mode_AF_PP = 0x18\r
+}GPIOMode_TypeDef;\r
+\r
+#define IS_GPIO_MODE(MODE) ((MODE == GPIO_Mode_AIN) || (MODE == GPIO_Mode_IN_FLOATING) || \\r
+ (MODE == GPIO_Mode_IPD) || (MODE == GPIO_Mode_IPU) || \\r
+ (MODE == GPIO_Mode_Out_OD) || (MODE == GPIO_Mode_Out_PP) || \\r
+ (MODE == GPIO_Mode_AF_OD) || (MODE == GPIO_Mode_AF_PP))\r
+ \r
+/* GPIO Init structure definition */\r
+typedef struct\r
+{\r
+ u16 GPIO_Pin;\r
+ GPIOSpeed_TypeDef GPIO_Speed;\r
+ GPIOMode_TypeDef GPIO_Mode;\r
+}GPIO_InitTypeDef;\r
+\r
+/* Bit_SET and Bit_RESET enumeration -----------------------------------------*/\r
+typedef enum\r
+{ Bit_RESET = 0,\r
+ Bit_SET\r
+}BitAction;\r
+#define IS_GPIO_BIT_ACTION(ACTION) ((ACTION == Bit_RESET) || (ACTION == Bit_SET))\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* GPIO pins define ----------------------------------------------------------*/\r
+#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */\r
+#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */\r
+#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */\r
+#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */\r
+#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */\r
+#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */\r
+#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */\r
+#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */\r
+#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */\r
+#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */\r
+#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */\r
+#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */\r
+#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */\r
+#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */\r
+#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */\r
+#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */\r
+#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */\r
+\r
+#define IS_GPIO_PIN(PIN) (((PIN & (u16)0x00) == 0x00) && (PIN != (u16)0x00))\r
+ \r
+/* GPIO Remap define ---------------------------------------------------------*/\r
+#define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */\r
+#define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */\r
+#define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */\r
+#define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */\r
+#define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */\r
+#define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */\r
+#define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */\r
+#define GPIO_Remap1_CAN ((u32)0x001D2000) /* CAN Alternate Function mapping */\r
+#define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */\r
+#define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */\r
+#define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */\r
+#define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */\r
+#define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */\r
+\r
+#define IS_GPIO_REMAP(REMAP) ((REMAP == GPIO_Remap_SPI1) || (REMAP == GPIO_Remap_I2C1) || \\r
+ (REMAP == GPIO_Remap_USART1) || (REMAP == GPIO_Remap_USART2) || \\r
+ (REMAP == GPIO_PartialRemap_USART3) || (REMAP == GPIO_FullRemap_USART3) || \\r
+ (REMAP == GPIO_PartialRemap_TIM1) || (REMAP == GPIO_FullRemap_TIM1) || \\r
+ (REMAP == GPIO_PartialRemap1_TIM2) || (REMAP == GPIO_PartialRemap2_TIM2) || \\r
+ (REMAP == GPIO_FullRemap_TIM2) || (REMAP == GPIO_PartialRemap_TIM3) || \\r
+ (REMAP == GPIO_FullRemap_TIM3) || (REMAP == GPIO_Remap_TIM4) || \\r
+ (REMAP == GPIO_Remap1_CAN) || (REMAP == GPIO_Remap2_CAN) || \\r
+ (REMAP == GPIO_Remap_PD01) || (REMAP == GPIO_Remap_SWJ_NoJTRST) || \\r
+ (REMAP == GPIO_Remap_SWJ_JTAGDisable) || (REMAP == GPIO_Remap_SWJ_Disable))\r
+ \r
+/* GPIO Port Sources ---------------------------------------------------------*/\r
+#define GPIO_PortSourceGPIOA ((u8)0x00)\r
+#define GPIO_PortSourceGPIOB ((u8)0x01)\r
+#define GPIO_PortSourceGPIOC ((u8)0x02)\r
+#define GPIO_PortSourceGPIOD ((u8)0x03)\r
+#define GPIO_PortSourceGPIOE ((u8)0x04)\r
+\r
+#define IS_GPIO_PORT_SOURCE(PORTSOURCE) ((PORTSOURCE == GPIO_PortSourceGPIOA) || \\r
+ (PORTSOURCE == GPIO_PortSourceGPIOB) || \\r
+ (PORTSOURCE == GPIO_PortSourceGPIOC) || \\r
+ (PORTSOURCE == GPIO_PortSourceGPIOD) || \\r
+ (PORTSOURCE == GPIO_PortSourceGPIOE))\r
+ \r
+/* GPIO Pin sources ----------------------------------------------------------*/\r
+#define GPIO_PinSource0 ((u8)0x00)\r
+#define GPIO_PinSource1 ((u8)0x01)\r
+#define GPIO_PinSource2 ((u8)0x02)\r
+#define GPIO_PinSource3 ((u8)0x03)\r
+#define GPIO_PinSource4 ((u8)0x04)\r
+#define GPIO_PinSource5 ((u8)0x05)\r
+#define GPIO_PinSource6 ((u8)0x06)\r
+#define GPIO_PinSource7 ((u8)0x07)\r
+#define GPIO_PinSource8 ((u8)0x08)\r
+#define GPIO_PinSource9 ((u8)0x09)\r
+#define GPIO_PinSource10 ((u8)0x0A)\r
+#define GPIO_PinSource11 ((u8)0x0B)\r
+#define GPIO_PinSource12 ((u8)0x0C)\r
+#define GPIO_PinSource13 ((u8)0x0D)\r
+#define GPIO_PinSource14 ((u8)0x0E)\r
+#define GPIO_PinSource15 ((u8)0x0F)\r
+\r
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) ((PINSOURCE == GPIO_PinSource0) || \\r
+ (PINSOURCE == GPIO_PinSource1) || \\r
+ (PINSOURCE == GPIO_PinSource2) || \\r
+ (PINSOURCE == GPIO_PinSource3) || \\r
+ (PINSOURCE == GPIO_PinSource4) || \\r
+ (PINSOURCE == GPIO_PinSource5) || \\r
+ (PINSOURCE == GPIO_PinSource6) || \\r
+ (PINSOURCE == GPIO_PinSource7) || \\r
+ (PINSOURCE == GPIO_PinSource8) || \\r
+ (PINSOURCE == GPIO_PinSource9) || \\r
+ (PINSOURCE == GPIO_PinSource10) || \\r
+ (PINSOURCE == GPIO_PinSource11) || \\r
+ (PINSOURCE == GPIO_PinSource12) || \\r
+ (PINSOURCE == GPIO_PinSource13) || \\r
+ (PINSOURCE == GPIO_PinSource14) || \\r
+ (PINSOURCE == GPIO_PinSource15))\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+void GPIO_AFIODeInit(void);\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);\r
+u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);\r
+u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal);\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin);\r
+void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);\r
+void GPIO_EventOutputCmd(FunctionalState NewState);\r
+void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState);\r
+void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource);\r
+\r
+#endif /* __STM32F10x_GPIO_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_i2c.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* I2C firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_I2C_H\r
+#define __STM32F10x_I2C_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* I2C Init structure definition */\r
+typedef struct\r
+{\r
+ u16 I2C_Mode;\r
+ u16 I2C_DutyCycle;\r
+ u16 I2C_OwnAddress1;\r
+ u16 I2C_Ack;\r
+ u16 I2C_AcknowledgedAddress;\r
+ u32 I2C_ClockSpeed;\r
+}I2C_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* I2C modes */\r
+#define I2C_Mode_I2C ((u16)0x0000)\r
+#define I2C_Mode_SMBusDevice ((u16)0x0002)\r
+#define I2C_Mode_SMBusHost ((u16)0x000A)\r
+\r
+#define IS_I2C_MODE(MODE) ((MODE == I2C_Mode_I2C) || \\r
+ (MODE == I2C_Mode_SMBusDevice) || \\r
+ (MODE == I2C_Mode_SMBusHost))\r
+/* I2C duty cycle in fast mode */\r
+#define I2C_DutyCycle_16_9 ((u16)0x4000)\r
+#define I2C_DutyCycle_2 ((u16)0xBFFF)\r
+\r
+#define IS_I2C_DUTY_CYCLE(CYCLE) ((CYCLE == I2C_DutyCycle_16_9) || \\r
+ (CYCLE == I2C_DutyCycle_2))\r
+\r
+/* I2C cknowledgementy */\r
+#define I2C_Ack_Enable ((u16)0x0400)\r
+#define I2C_Ack_Disable ((u16)0x0000)\r
+\r
+#define IS_I2C_ACK_STATE(STATE) ((STATE == I2C_Ack_Enable) || \\r
+ (STATE == I2C_Ack_Disable))\r
+\r
+/* I2C transfer direction */\r
+#define I2C_Direction_Transmitter ((u8)0x00)\r
+#define I2C_Direction_Receiver ((u8)0x01)\r
+\r
+#define IS_I2C_DIRECTION(DIRECTION) ((DIRECTION == I2C_Direction_Transmitter) || \\r
+ (DIRECTION == I2C_Direction_Receiver))\r
+\r
+/* I2C acknowledged address defines */\r
+#define I2C_AcknowledgedAddress_7bit ((u16)0x4000)\r
+#define I2C_AcknowledgedAddress_10bit ((u16)0xC000)\r
+\r
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) ((ADDRESS == I2C_AcknowledgedAddress_7bit) || \\r
+ (ADDRESS == I2C_AcknowledgedAddress_10bit))\r
+\r
+/* I2C registers */\r
+#define I2C_Register_CR1 ((u8)0x00)\r
+#define I2C_Register_CR2 ((u8)0x04)\r
+#define I2C_Register_OAR1 ((u8)0x08)\r
+#define I2C_Register_OAR2 ((u8)0x0C)\r
+#define I2C_Register_DR ((u8)0x10)\r
+#define I2C_Register_SR1 ((u8)0x14)\r
+#define I2C_Register_SR2 ((u8)0x18)\r
+#define I2C_Register_CCR ((u8)0x1C)\r
+#define I2C_Register_TRISE ((u8)0x20)\r
+\r
+#define IS_I2C_REGISTER(REGISTER) ((REGISTER == I2C_Register_CR1) || \\r
+ (REGISTER == I2C_Register_CR2) || \\r
+ (REGISTER == I2C_Register_OAR1) || \\r
+ (REGISTER == I2C_Register_OAR2) || \\r
+ (REGISTER == I2C_Register_DR) || \\r
+ (REGISTER == I2C_Register_SR1) || \\r
+ (REGISTER == I2C_Register_SR2) || \\r
+ (REGISTER == I2C_Register_CCR) || \\r
+ (REGISTER == I2C_Register_TRISE))\r
+\r
+/* I2C SMBus alert pin level */\r
+#define I2C_SMBusAlert_Low ((u16)0x2000)\r
+#define I2C_SMBusAlert_High ((u16)0xCFFF)\r
+\r
+#define IS_I2C_SMBUS_ALERT(ALERT) ((ALERT == I2C_SMBusAlert_Low) || \\r
+ (ALERT == I2C_SMBusAlert_High))\r
+\r
+/* I2C PEC position */\r
+#define I2C_PECPosition_Next ((u16)0x0800)\r
+#define I2C_PECPosition_Current ((u16)0xF7FF)\r
+\r
+#define IS_I2C_PEC_POSITION(POSITION) ((POSITION == I2C_PECPosition_Next) || \\r
+ (POSITION == I2C_PECPosition_Current))\r
+\r
+/* I2C interrupts definition */\r
+#define I2C_IT_BUF ((u16)0x0400)\r
+#define I2C_IT_EVT ((u16)0x0200)\r
+#define I2C_IT_ERR ((u16)0x0100)\r
+\r
+#define IS_I2C_CONFIG_IT(IT) (((IT & (u16)0xF8FF) == 0x00) && (IT != 0x00))\r
+\r
+/* I2C interrupts definition */\r
+#define I2C_IT_SMBALERT ((u32)0x10008000)\r
+#define I2C_IT_TIMEOUT ((u32)0x10004000)\r
+#define I2C_IT_PECERR ((u32)0x10001000)\r
+#define I2C_IT_OVR ((u32)0x10000800)\r
+#define I2C_IT_AF ((u32)0x10000400)\r
+#define I2C_IT_ARLO ((u32)0x10000200)\r
+#define I2C_IT_BERR ((u32)0x10000100)\r
+#define I2C_IT_TXE ((u32)0x00000080)\r
+#define I2C_IT_RXNE ((u32)0x00000040)\r
+#define I2C_IT_STOPF ((u32)0x60000010)\r
+#define I2C_IT_ADD10 ((u32)0x20000008)\r
+#define I2C_IT_BTF ((u32)0x60000004)\r
+#define I2C_IT_ADDR ((u32)0xA0000002)\r
+#define I2C_IT_SB ((u32)0x20000001)\r
+\r
+#define IS_I2C_CLEAR_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \\r
+ (IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \\r
+ (IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \\r
+ (IT == I2C_IT_BERR) || (IT == I2C_IT_STOPF) || \\r
+ (IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \\r
+ (IT == I2C_IT_ADDR) || (IT == I2C_IT_SB))\r
+\r
+#define IS_I2C_GET_IT(IT) ((IT == I2C_IT_SMBALERT) || (IT == I2C_IT_TIMEOUT) || \\r
+ (IT == I2C_IT_PECERR) || (IT == I2C_IT_OVR) || \\r
+ (IT == I2C_IT_AF) || (IT == I2C_IT_ARLO) || \\r
+ (IT == I2C_IT_BERR) || (IT == I2C_IT_TXE) || \\r
+ (IT == I2C_IT_RXNE) || (IT == I2C_IT_STOPF) || \\r
+ (IT == I2C_IT_ADD10) || (IT == I2C_IT_BTF) || \\r
+ (IT == I2C_IT_ADDR) || (IT == I2C_IT_SB))\r
+\r
+/* I2C flags definition */\r
+#define I2C_FLAG_DUALF ((u32)0x00800000)\r
+#define I2C_FLAG_SMBHOST ((u32)0x00400000)\r
+#define I2C_FLAG_SMBDEFAULT ((u32)0x00200000)\r
+#define I2C_FLAG_GENCALL ((u32)0x00100000)\r
+#define I2C_FLAG_TRA ((u32)0x00040000)\r
+#define I2C_FLAG_BUSY ((u32)0x00020000)\r
+#define I2C_FLAG_MSL ((u32)0x00010000)\r
+#define I2C_FLAG_SMBALERT ((u32)0x10008000)\r
+#define I2C_FLAG_TIMEOUT ((u32)0x10004000)\r
+#define I2C_FLAG_PECERR ((u32)0x10001000)\r
+#define I2C_FLAG_OVR ((u32)0x10000800)\r
+#define I2C_FLAG_AF ((u32)0x10000400)\r
+#define I2C_FLAG_ARLO ((u32)0x10000200)\r
+#define I2C_FLAG_BERR ((u32)0x10000100)\r
+#define I2C_FLAG_TXE ((u32)0x00000080)\r
+#define I2C_FLAG_RXNE ((u32)0x00000040)\r
+#define I2C_FLAG_STOPF ((u32)0x60000010)\r
+#define I2C_FLAG_ADD10 ((u32)0x20000008)\r
+#define I2C_FLAG_BTF ((u32)0x60000004)\r
+#define I2C_FLAG_ADDR ((u32)0xA0000002)\r
+#define I2C_FLAG_SB ((u32)0x20000001)\r
+\r
+#define IS_I2C_CLEAR_FLAG(FLAG) ((FLAG == I2C_FLAG_SMBALERT) || (FLAG == I2C_FLAG_TIMEOUT) || \\r
+ (FLAG == I2C_FLAG_PECERR) || (FLAG == I2C_FLAG_OVR) || \\r
+ (FLAG == I2C_FLAG_AF) || (FLAG == I2C_FLAG_ARLO) || \\r
+ (FLAG == I2C_FLAG_BERR) || (FLAG == I2C_FLAG_STOPF) || \\r
+ (FLAG == I2C_FLAG_ADD10) || (FLAG == I2C_FLAG_BTF) || \\r
+ (FLAG == I2C_FLAG_ADDR) || (FLAG == I2C_FLAG_SB))\r
+\r
+#define IS_I2C_GET_FLAG(FLAG) ((FLAG == I2C_FLAG_DUALF) || (FLAG == I2C_FLAG_SMBHOST) || \\r
+ (FLAG == I2C_FLAG_SMBDEFAULT) || (FLAG == I2C_FLAG_GENCALL) || \\r
+ (FLAG == I2C_FLAG_TRA) || (FLAG == I2C_FLAG_BUSY) || \\r
+ (FLAG == I2C_FLAG_MSL) || (FLAG == I2C_FLAG_SMBALERT) || \\r
+ (FLAG == I2C_FLAG_TIMEOUT) || (FLAG == I2C_FLAG_PECERR) || \\r
+ (FLAG == I2C_FLAG_OVR) || (FLAG == I2C_FLAG_AF) || \\r
+ (FLAG == I2C_FLAG_ARLO) || (FLAG == I2C_FLAG_BERR) || \\r
+ (FLAG == I2C_FLAG_TXE) || (FLAG == I2C_FLAG_RXNE) || \\r
+ (FLAG == I2C_FLAG_STOPF) || (FLAG == I2C_FLAG_ADD10) || \\r
+ (FLAG == I2C_FLAG_BTF) || (FLAG == I2C_FLAG_ADDR) || \\r
+ (FLAG == I2C_FLAG_SB))\r
+\r
+/* I2C Events */\r
+/* EV1 */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((u32)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((u32)0x00020002) /* BUSY and ADDR flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((u32)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((u32)0x00820000) /* DUALF and BUSY flags */\r
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((u32)0x00120000) /* GENCALL and BUSY flags */\r
+\r
+/* EV2 */\r
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((u32)0x00020040) /* BUSY and RXNE flags */\r
+ \r
+/* EV3 */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((u32)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
+\r
+/* EV4 */\r
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((u32)0x00000010) /* STOPF flag */\r
+\r
+/* EV5 */\r
+#define I2C_EVENT_MASTER_MODE_SELECT ((u32)0x00030001) /* BUSY, MSL and SB flag */\r
+\r
+/* EV6 */\r
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((u32)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((u32)0x00030002) /* BUSY, MSL and ADDR flags */\r
+\r
+/* EV7 */\r
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((u32)0x00030040) /* BUSY, MSL and RXNE flags */\r
+\r
+/* EV8 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((u32)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
+ \r
+/* EV9 */\r
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((u32)0x00030008) /* BUSY, MSL and ADD10 flags */\r
+ \r
+/* EV3_1 */\r
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((u32)0x00000400) /* AF flag */\r
+\r
+#define IS_I2C_EVENT(EVENT) ((EVENT == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
+ (EVENT == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
+ (EVENT == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
+ (EVENT == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
+ (EVENT == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
+ (EVENT == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
+ (EVENT == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
+ (EVENT == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
+ (EVENT == I2C_EVENT_MASTER_MODE_SELECT) || \\r
+ (EVENT == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
+ (EVENT == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
+ (EVENT == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
+ (EVENT == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
+ (EVENT == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
+ (EVENT == I2C_EVENT_SLAVE_ACK_FAILURE))\r
+\r
+/* I2C own address1 -----------------------------------------------------------*/\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (ADDRESS1 <= 0x3FF)\r
+/* I2C clock speed ------------------------------------------------------------*/\r
+#define IS_I2C_CLOCK_SPEED(SPEED) ((SPEED >= 0x1) && (SPEED <= 400000))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void I2C_DeInit(I2C_TypeDef* I2Cx);\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address);\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState);\r
+void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data);\r
+u8 I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction);\r
+u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register);\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert);\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx);\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition);\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+u8 I2C_GetPEC(I2C_TypeDef* I2Cx);\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle);\r
+u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT);\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG);\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG);\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT);\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT);\r
+\r
+#endif /*__STM32F10x_I2C_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_it.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains the headers of the interrupt handlers.\r
+********************************************************************************\r
+* History:\r
+* mm/dd/yyyy: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_IT_H\r
+#define __STM32F10x_IT_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_lib.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void NMIException(void);\r
+void HardFaultException(void);\r
+void MemManageException(void);\r
+void BusFaultException(void);\r
+void UsageFaultException(void);\r
+void DebugMonitor(void);\r
+void SVCHandler(void);\r
+void PendSVC(void);\r
+void SysTickHandler(void);\r
+void WWDG_IRQHandler(void);\r
+void PVD_IRQHandler(void);\r
+void TAMPER_IRQHandler(void);\r
+void RTC_IRQHandler(void);\r
+void FLASH_IRQHandler(void);\r
+void RCC_IRQHandler(void);\r
+void EXTI0_IRQHandler(void);\r
+void EXTI1_IRQHandler(void);\r
+void EXTI2_IRQHandler(void);\r
+void EXTI3_IRQHandler(void);\r
+void EXTI4_IRQHandler(void);\r
+void DMAChannel1_IRQHandler(void);\r
+void DMAChannel2_IRQHandler(void);\r
+void DMAChannel3_IRQHandler(void);\r
+void DMAChannel4_IRQHandler(void);\r
+void DMAChannel5_IRQHandler(void);\r
+void DMAChannel6_IRQHandler(void);\r
+void DMAChannel7_IRQHandler(void);\r
+void ADC_IRQHandler(void);\r
+void USB_HP_CAN_TX_IRQHandler(void);\r
+void USB_LP_CAN_RX0_IRQHandler(void);\r
+void CAN_RX1_IRQHandler(void);\r
+void CAN_SCE_IRQHandler(void);\r
+void EXTI9_5_IRQHandler(void);\r
+void TIM1_BRK_IRQHandler(void);\r
+void TIM1_UP_IRQHandler(void);\r
+void TIM1_TRG_COM_IRQHandler(void);\r
+void TIM1_CC_IRQHandler(void);\r
+void TIM2_IRQHandler(void);\r
+void TIM3_IRQHandler(void);\r
+void TIM4_IRQHandler(void);\r
+void I2C1_EV_IRQHandler(void);\r
+void I2C1_ER_IRQHandler(void);\r
+void I2C2_EV_IRQHandler(void);\r
+void I2C2_ER_IRQHandler(void);\r
+void SPI1_IRQHandler(void);\r
+void SPI2_IRQHandler(void);\r
+void USART1_IRQHandler(void);\r
+void USART2_IRQHandler(void);\r
+void USART3_IRQHandler(void);\r
+void EXTI15_10_IRQHandler(void);\r
+void RTCAlarm_IRQHandler(void);\r
+void USBWakeUp_IRQHandler(void);\r
+ \r
+#endif /* __STM32F10x_IT_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_iwdg.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* IWDG firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_IWDG_H\r
+#define __STM32F10x_IWDG_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Write access to IWDG_PR and IWDG_RLR registers */\r
+#define IWDG_WriteAccess_Enable ((u16)0x5555)\r
+#define IWDG_WriteAccess_Disable ((u16)0x0000)\r
+\r
+#define IS_IWDG_WRITE_ACCESS(ACCESS) ((ACCESS == IWDG_WriteAccess_Enable) || \\r
+ (ACCESS == IWDG_WriteAccess_Disable))\r
+\r
+/* IWDG prescaler */\r
+#define IWDG_Prescaler_4 ((u8)0x00)\r
+#define IWDG_Prescaler_8 ((u8)0x01)\r
+#define IWDG_Prescaler_16 ((u8)0x02)\r
+#define IWDG_Prescaler_32 ((u8)0x03)\r
+#define IWDG_Prescaler_64 ((u8)0x04)\r
+#define IWDG_Prescaler_128 ((u8)0x05)\r
+#define IWDG_Prescaler_256 ((u8)0x06)\r
+\r
+#define IS_IWDG_PRESCALER(PRESCALER) ((PRESCALER == IWDG_Prescaler_4) || \\r
+ (PRESCALER == IWDG_Prescaler_8) || \\r
+ (PRESCALER == IWDG_Prescaler_16) || \\r
+ (PRESCALER == IWDG_Prescaler_32) || \\r
+ (PRESCALER == IWDG_Prescaler_64) || \\r
+ (PRESCALER == IWDG_Prescaler_128)|| \\r
+ (PRESCALER == IWDG_Prescaler_256))\r
+\r
+/* IWDG Flag */\r
+#define IWDG_FLAG_PVU ((u16)0x0001)\r
+#define IWDG_FLAG_RVU ((u16)0x0002)\r
+\r
+#define IS_IWDG_FLAG(FLAG) ((FLAG == IWDG_FLAG_PVU) || (FLAG == IWDG_FLAG_RVU))\r
+\r
+#define IS_IWDG_RELOAD(RELOAD) (RELOAD <= 0xFFF)\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess);\r
+void IWDG_SetPrescaler(u8 IWDG_Prescaler);\r
+void IWDG_SetReload(u16 Reload);\r
+void IWDG_ReloadCounter(void);\r
+void IWDG_Enable(void);\r
+FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG);\r
+\r
+#endif /* __STM32F10x_IWDG_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_lib.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file includes the peripherals header files in the\r
+* user application.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_LIB_H\r
+#define __STM32F10x_LIB_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+#ifdef _ADC\r
+ #include "stm32f10x_adc.h"\r
+#endif /*_ADC */\r
+\r
+#ifdef _BKP\r
+ #include "stm32f10x_bkp.h"\r
+#endif /*_BKP */\r
+\r
+#ifdef _CAN\r
+ #include "stm32f10x_can.h"\r
+#endif /*_CAN */\r
+\r
+#ifdef _DMA\r
+ #include "stm32f10x_dma.h"\r
+#endif /*_DMA */\r
+\r
+#ifdef _EXTI\r
+ #include "stm32f10x_exti.h"\r
+#endif /*_EXTI */\r
+\r
+#ifdef _FLASH\r
+ #include "stm32f10x_flash.h"\r
+#endif /*_FLASH */\r
+\r
+#ifdef _GPIO\r
+ #include "stm32f10x_gpio.h"\r
+#endif /*_GPIO */\r
+\r
+#ifdef _I2C\r
+ #include "stm32f10x_i2c.h"\r
+#endif /*_I2C */\r
+\r
+#ifdef _IWDG\r
+ #include "stm32f10x_iwdg.h"\r
+#endif /*_IWDG */\r
+\r
+#ifdef _NVIC\r
+ #include "stm32f10x_nvic.h"\r
+#endif /*_NVIC */\r
+\r
+#ifdef _PWR\r
+ #include "stm32f10x_pwr.h"\r
+#endif /*_PWR */\r
+\r
+#ifdef _RCC\r
+ #include "stm32f10x_rcc.h"\r
+#endif /*_RCC */\r
+\r
+#ifdef _RTC\r
+ #include "stm32f10x_rtc.h"\r
+#endif /*_RTC */\r
+\r
+#ifdef _SPI\r
+ #include "stm32f10x_spi.h"\r
+#endif /*_SPI */\r
+\r
+#ifdef _SysTick\r
+ #include "stm32f10x_systick.h"\r
+#endif /*_SysTick */\r
+\r
+#ifdef _TIM1\r
+ #include "stm32f10x_tim1.h"\r
+#endif /*_TIM1 */\r
+\r
+#ifdef _TIM\r
+ #include "stm32f10x_tim.h"\r
+#endif /*_TIM */\r
+\r
+#ifdef _USART\r
+ #include "stm32f10x_usart.h"\r
+#endif /*_USART */\r
+\r
+#ifdef _WWDG\r
+ #include "stm32f10x_wwdg.h"\r
+#endif /*_WWDG */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void debug(void);\r
+\r
+#endif /* __STM32F10x_LIB_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_map.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the peripheral register's definitions\r
+* and memory mapping.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_MAP_H\r
+#define __STM32F10x_MAP_H\r
+\r
+#ifndef EXT\r
+ #define EXT extern\r
+#endif /* EXT */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_conf.h"\r
+#include "stm32f10x_type.h"\r
+#include "cortexm3_macro.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/******************************************************************************/\r
+/* IP registers structures */\r
+/******************************************************************************/\r
+\r
+/*------------------------ Analog to Digital Converter -----------------------*/\r
+typedef struct\r
+{\r
+ vu32 SR;\r
+ vu32 CR1;\r
+ vu32 CR2;\r
+ vu32 SMPR1;\r
+ vu32 SMPR2;\r
+ vu32 JOFR1;\r
+ vu32 JOFR2;\r
+ vu32 JOFR3;\r
+ vu32 JOFR4;\r
+ vu32 HTR;\r
+ vu32 LTR;\r
+ vu32 SQR1;\r
+ vu32 SQR2;\r
+ vu32 SQR3;\r
+ vu32 JSQR;\r
+ vu32 JDR1;\r
+ vu32 JDR2;\r
+ vu32 JDR3;\r
+ vu32 JDR4;\r
+ vu32 DR;\r
+} ADC_TypeDef;\r
+\r
+/*------------------------ Backup Registers ----------------------------------*/\r
+typedef struct\r
+{\r
+ u32 RESERVED0;\r
+ vu16 DR1;\r
+ u16 RESERVED1;\r
+ vu16 DR2;\r
+ u16 RESERVED2;\r
+ vu16 DR3;\r
+ u16 RESERVED3;\r
+ vu16 DR4;\r
+ u16 RESERVED4;\r
+ vu16 DR5;\r
+ u16 RESERVED5;\r
+ vu16 DR6;\r
+ u16 RESERVED6;\r
+ vu16 DR7;\r
+ u16 RESERVED7;\r
+ vu16 DR8;\r
+ u16 RESERVED8;\r
+ vu16 DR9;\r
+ u16 RESERVED9;\r
+ vu16 DR10;\r
+ u16 RESERVED10;\r
+ vu16 RTCCR;\r
+ u16 RESERVED11;\r
+ vu16 CR;\r
+ u16 RESERVED12;\r
+ vu16 CSR;\r
+ u16 RESERVED13;\r
+} BKP_TypeDef;\r
+\r
+/*------------------------ Controller Area Network ---------------------------*/\r
+typedef struct\r
+{\r
+ vu32 TIR;\r
+ vu32 TDTR;\r
+ vu32 TDLR;\r
+ vu32 TDHR;\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 RIR;\r
+ vu32 RDTR;\r
+ vu32 RDLR;\r
+ vu32 RDHR;\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 FR0;\r
+ vu32 FR1;\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 MCR;\r
+ vu32 MSR;\r
+ vu32 TSR;\r
+ vu32 RF0R;\r
+ vu32 RF1R;\r
+ vu32 IER;\r
+ vu32 ESR;\r
+ vu32 BTR;\r
+ u32 RESERVED0[88];\r
+ CAN_TxMailBox_TypeDef sTxMailBox[3];\r
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];\r
+ u32 RESERVED1[12];\r
+ vu32 FMR;\r
+ vu32 FM0R;\r
+ u32 RESERVED2[1];\r
+ vu32 FS0R;\r
+ u32 RESERVED3[1];\r
+ vu32 FFA0R;\r
+ u32 RESERVED4[1];\r
+ vu32 FA0R;\r
+ u32 RESERVED5[8];\r
+ CAN_FilterRegister_TypeDef sFilterRegister[14];\r
+} CAN_TypeDef;\r
+\r
+/*------------------------ DMA Controller ------------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 CCR;\r
+ vu32 CNDTR;\r
+ vu32 CPAR;\r
+ vu32 CMAR;\r
+} DMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 ISR;\r
+ vu32 IFCR;\r
+} DMA_TypeDef;\r
+\r
+/*------------------------ External Interrupt/Event Controller ---------------*/\r
+typedef struct\r
+{\r
+ vu32 IMR;\r
+ vu32 EMR;\r
+ vu32 RTSR;\r
+ vu32 FTSR;\r
+ vu32 SWIER;\r
+ vu32 PR;\r
+} EXTI_TypeDef;\r
+\r
+/*------------------------ FLASH and Option Bytes Registers ------------------*/\r
+typedef struct\r
+{\r
+ vu32 ACR;\r
+ vu32 KEYR;\r
+ vu32 OPTKEYR;\r
+ vu32 SR;\r
+ vu32 CR;\r
+ vu32 AR;\r
+ vu32 RESERVED;\r
+ vu32 OBR;\r
+ vu32 WRPR;\r
+} FLASH_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu16 RDP;\r
+ vu16 USER;\r
+ vu16 Data0;\r
+ vu16 Data1;\r
+ vu16 WRP0;\r
+ vu16 WRP1;\r
+ vu16 WRP2;\r
+ vu16 WRP3;\r
+} OB_TypeDef;\r
+\r
+/*------------------------ General Purpose and Alternate Function IO ---------*/\r
+typedef struct\r
+{\r
+ vu32 CRL;\r
+ vu32 CRH;\r
+ vu32 IDR;\r
+ vu32 ODR;\r
+ vu32 BSRR;\r
+ vu32 BRR;\r
+ vu32 LCKR;\r
+} GPIO_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 EVCR;\r
+ vu32 MAPR;\r
+ vu32 EXTICR[4];\r
+} AFIO_TypeDef;\r
+\r
+/*------------------------ Inter-integrated Circuit Interface ----------------*/\r
+typedef struct\r
+{\r
+ vu16 CR1;\r
+ u16 RESERVED0;\r
+ vu16 CR2;\r
+ u16 RESERVED1;\r
+ vu16 OAR1;\r
+ u16 RESERVED2;\r
+ vu16 OAR2;\r
+ u16 RESERVED3;\r
+ vu16 DR;\r
+ u16 RESERVED4;\r
+ vu16 SR1;\r
+ u16 RESERVED5;\r
+ vu16 SR2;\r
+ u16 RESERVED6;\r
+ vu16 CCR;\r
+ u16 RESERVED7;\r
+ vu16 TRISE;\r
+ u16 RESERVED8;\r
+} I2C_TypeDef;\r
+\r
+/*------------------------ Independent WATCHDOG ------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 KR;\r
+ vu32 PR;\r
+ vu32 RLR;\r
+ vu32 SR;\r
+} IWDG_TypeDef;\r
+\r
+/*------------------------ Nested Vectored Interrupt Controller --------------*/\r
+typedef struct\r
+{\r
+ vu32 Enable[2];\r
+ u32 RESERVED0[30];\r
+ vu32 Disable[2];\r
+ u32 RSERVED1[30];\r
+ vu32 Set[2];\r
+ u32 RESERVED2[30];\r
+ vu32 Clear[2];\r
+ u32 RESERVED3[30];\r
+ vu32 Active[2];\r
+ u32 RESERVED4[62];\r
+ vu32 Priority[11];\r
+} NVIC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ vu32 CPUID;\r
+ vu32 IRQControlState;\r
+ vu32 ExceptionTableOffset;\r
+ vu32 AIRC;\r
+ vu32 SysCtrl;\r
+ vu32 ConfigCtrl;\r
+ vu32 SystemPriority[3];\r
+ vu32 SysHandlerCtrl;\r
+ vu32 ConfigFaultStatus;\r
+ vu32 HardFaultStatus;\r
+ vu32 DebugFaultStatus;\r
+ vu32 MemoryManageFaultAddr;\r
+ vu32 BusFaultAddr;\r
+} SCB_TypeDef;\r
+\r
+/*------------------------ Power Controller ----------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 CR;\r
+ vu32 CSR;\r
+} PWR_TypeDef;\r
+\r
+/*------------------------ Reset and Clock Controller ------------------------*/\r
+typedef struct\r
+{\r
+ vu32 CR;\r
+ vu32 CFGR;\r
+ vu32 CIR;\r
+ vu32 APB2RSTR;\r
+ vu32 APB1RSTR;\r
+ vu32 AHBENR;\r
+ vu32 APB2ENR;\r
+ vu32 APB1ENR;\r
+ vu32 BDCR;\r
+ vu32 CSR;\r
+} RCC_TypeDef;\r
+\r
+/*------------------------ Real-Time Clock -----------------------------------*/\r
+typedef struct\r
+{\r
+ vu16 CRH;\r
+ u16 RESERVED0;\r
+ vu16 CRL;\r
+ u16 RESERVED1;\r
+ vu16 PRLH;\r
+ u16 RESERVED2;\r
+ vu16 PRLL;\r
+ u16 RESERVED3;\r
+ vu16 DIVH;\r
+ u16 RESERVED4;\r
+ vu16 DIVL;\r
+ u16 RESERVED5;\r
+ vu16 CNTH;\r
+ u16 RESERVED6;\r
+ vu16 CNTL;\r
+ u16 RESERVED7;\r
+ vu16 ALRH;\r
+ u16 RESERVED8;\r
+ vu16 ALRL;\r
+ u16 RESERVED9;\r
+} RTC_TypeDef;\r
+\r
+/*------------------------ Serial Peripheral Interface -----------------------*/\r
+typedef struct\r
+{\r
+ vu16 CR1;\r
+ u16 RESERVED0;\r
+ vu16 CR2;\r
+ u16 RESERVED1;\r
+ vu16 SR;\r
+ u16 RESERVED2;\r
+ vu16 DR;\r
+ u16 RESERVED3;\r
+ vu16 CRCPR;\r
+ u16 RESERVED4;\r
+ vu16 RXCRCR;\r
+ u16 RESERVED5;\r
+ vu16 TXCRCR;\r
+ u16 RESERVED6;\r
+} SPI_TypeDef;\r
+\r
+/*------------------------ SystemTick ----------------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 CTRL;\r
+ vu32 LOAD;\r
+ vu32 VAL;\r
+ vuc32 CALIB;\r
+} SysTick_TypeDef;\r
+\r
+/*------------------------ Advanced Control Timer ----------------------------*/\r
+typedef struct\r
+{\r
+ vu16 CR1;\r
+ u16 RESERVED0;\r
+ vu16 CR2;\r
+ u16 RESERVED1;\r
+ vu16 SMCR;\r
+ u16 RESERVED2;\r
+ vu16 DIER;\r
+ u16 RESERVED3;\r
+ vu16 SR;\r
+ u16 RESERVED4;\r
+ vu16 EGR;\r
+ u16 RESERVED5;\r
+ vu16 CCMR1;\r
+ u16 RESERVED6;\r
+ vu16 CCMR2;\r
+ u16 RESERVED7;\r
+ vu16 CCER;\r
+ u16 RESERVED8;\r
+ vu16 CNT;\r
+ u16 RESERVED9;\r
+ vu16 PSC;\r
+ u16 RESERVED10;\r
+ vu16 ARR;\r
+ u16 RESERVED11;\r
+ vu16 RCR;\r
+ u16 RESERVED12;\r
+ vu16 CCR1;\r
+ u16 RESERVED13;\r
+ vu16 CCR2;\r
+ u16 RESERVED14;\r
+ vu16 CCR3;\r
+ u16 RESERVED15;\r
+ vu16 CCR4;\r
+ u16 RESERVED16;\r
+ vu16 BDTR;\r
+ u16 RESERVED17;\r
+ vu16 DCR;\r
+ u16 RESERVED18;\r
+ vu16 DMAR;\r
+ u16 RESERVED19;\r
+} TIM1_TypeDef;\r
+\r
+/*------------------------ General Purpose Timer -----------------------------*/\r
+typedef struct\r
+{\r
+ vu16 CR1;\r
+ u16 RESERVED0;\r
+ vu16 CR2;\r
+ u16 RESERVED1;\r
+ vu16 SMCR;\r
+ u16 RESERVED2;\r
+ vu16 DIER;\r
+ u16 RESERVED3;\r
+ vu16 SR;\r
+ u16 RESERVED4;\r
+ vu16 EGR;\r
+ u16 RESERVED5;\r
+ vu16 CCMR1;\r
+ u16 RESERVED6;\r
+ vu16 CCMR2;\r
+ u16 RESERVED7;\r
+ vu16 CCER;\r
+ u16 RESERVED8;\r
+ vu16 CNT;\r
+ u16 RESERVED9;\r
+ vu16 PSC;\r
+ u16 RESERVED10;\r
+ vu16 ARR;\r
+ u16 RESERVED11[3];\r
+ vu16 CCR1;\r
+ u16 RESERVED12;\r
+ vu16 CCR2;\r
+ u16 RESERVED13;\r
+ vu16 CCR3;\r
+ u16 RESERVED14;\r
+ vu16 CCR4;\r
+ u16 RESERVED15[3];\r
+ vu16 DCR;\r
+ u16 RESERVED16;\r
+ vu16 DMAR;\r
+ u16 RESERVED17;\r
+} TIM_TypeDef;\r
+\r
+/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/\r
+typedef struct\r
+{\r
+ vu16 SR;\r
+ u16 RESERVED0;\r
+ vu16 DR;\r
+ u16 RESERVED1;\r
+ vu16 BRR;\r
+ u16 RESERVED2;\r
+ vu16 CR1;\r
+ u16 RESERVED3;\r
+ vu16 CR2;\r
+ u16 RESERVED4;\r
+ vu16 CR3;\r
+ u16 RESERVED5;\r
+ vu16 GTPR;\r
+ u16 RESERVED6;\r
+} USART_TypeDef;\r
+\r
+/*------------------------ Window WATCHDOG -----------------------------------*/\r
+typedef struct\r
+{\r
+ vu32 CR;\r
+ vu32 CFR;\r
+ vu32 SR;\r
+} WWDG_TypeDef;\r
+\r
+/******************************************************************************/\r
+/* Peripheral memory map */\r
+/******************************************************************************/\r
+/* Peripheral and SRAM base address in the alias region */\r
+#define PERIPH_BB_BASE ((u32)0x42000000)\r
+#define SRAM_BB_BASE ((u32)0x22000000)\r
+\r
+/* Peripheral and SRAM base address in the bit-band region */\r
+#define SRAM_BASE ((u32)0x20000000)\r
+#define PERIPH_BASE ((u32)0x40000000)\r
+\r
+/* Flash refisters base address */\r
+#define FLASH_BASE ((u32)0x40022000)\r
+/* Flash Option Bytes base address */\r
+#define OB_BASE ((u32)0x1FFFF800)\r
+\r
+/* Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)\r
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)\r
+\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
+#define CAN_BASE (APB1PERIPH_BASE + 0x6400)\r
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
+\r
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)\r
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)\r
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)\r
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)\r
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)\r
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)\r
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)\r
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)\r
+\r
+#define DMA_BASE (AHBPERIPH_BASE + 0x0000)\r
+#define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x0008)\r
+#define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x001C)\r
+#define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x0030)\r
+#define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x0044)\r
+#define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x0058)\r
+#define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x006C)\r
+#define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x0080)\r
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)\r
+\r
+/* System Control Space memory map */\r
+#define SCS_BASE ((u32)0xE000E000)\r
+\r
+#define SysTick_BASE (SCS_BASE + 0x0010)\r
+#define NVIC_BASE (SCS_BASE + 0x0100)\r
+#define SCB_BASE (SCS_BASE + 0x0D00)\r
+\r
+\r
+/******************************************************************************/\r
+/* IPs' declaration */\r
+/******************************************************************************/\r
+\r
+/*------------------- Non Debug Mode -----------------------------------------*/\r
+#ifndef DEBUG\r
+#ifdef _TIM2\r
+ #define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#endif /*_TIM2 */\r
+\r
+#ifdef _TIM3\r
+ #define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#endif /*_TIM3 */\r
+\r
+#ifdef _TIM4\r
+ #define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#endif /*_TIM4 */\r
+\r
+#ifdef _RTC\r
+ #define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#endif /*_RTC */\r
+\r
+#ifdef _WWDG\r
+ #define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#endif /*_WWDG */\r
+\r
+#ifdef _IWDG\r
+ #define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#endif /*_IWDG */\r
+\r
+#ifdef _SPI2\r
+ #define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#endif /*_SPI2 */\r
+\r
+#ifdef _USART2\r
+ #define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#endif /*_USART2 */\r
+\r
+#ifdef _USART3\r
+ #define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#endif /*_USART3 */\r
+\r
+#ifdef _I2C1\r
+ #define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#endif /*_I2C1 */\r
+\r
+#ifdef _I2C2\r
+ #define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#endif /*_I2C2 */\r
+\r
+#ifdef _CAN\r
+ #define CAN ((CAN_TypeDef *) CAN_BASE)\r
+#endif /*_CAN */\r
+\r
+#ifdef _BKP\r
+ #define BKP ((BKP_TypeDef *) BKP_BASE)\r
+#endif /*_BKP */\r
+\r
+#ifdef _PWR\r
+ #define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#endif /*_PWR */\r
+\r
+#ifdef _AFIO\r
+ #define AFIO ((AFIO_TypeDef *) AFIO_BASE)\r
+#endif /*_AFIO */\r
+\r
+#ifdef _EXTI\r
+ #define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#endif /*_EXTI */\r
+\r
+#ifdef _GPIOA\r
+ #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#endif /*_GPIOA */\r
+\r
+#ifdef _GPIOB\r
+ #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#endif /*_GPIOB */\r
+\r
+#ifdef _GPIOC\r
+ #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#endif /*_GPIOC */\r
+\r
+#ifdef _GPIOD\r
+ #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#endif /*_GPIOD */\r
+\r
+#ifdef _GPIOE\r
+ #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#endif /*_GPIOE */\r
+\r
+#ifdef _ADC1\r
+ #define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#endif /*_ADC1 */\r
+\r
+#ifdef _ADC2\r
+ #define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
+#endif /*_ADC2 */\r
+\r
+#ifdef _TIM1\r
+ #define TIM1 ((TIM1_TypeDef *) TIM1_BASE)\r
+#endif /*_TIM1 */\r
+\r
+#ifdef _SPI1\r
+ #define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#endif /*_SPI1 */\r
+\r
+#ifdef _USART1\r
+ #define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#endif /*_USART1 */\r
+\r
+#ifdef _DMA\r
+ #define DMA ((DMA_TypeDef *) DMA_BASE)\r
+#endif /*_DMA */\r
+\r
+#ifdef _DMA_Channel1\r
+ #define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE)\r
+#endif /*_DMA_Channel1 */\r
+\r
+#ifdef _DMA_Channel2\r
+ #define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE)\r
+#endif /*_DMA_Channel2 */\r
+\r
+#ifdef _DMA_Channel3\r
+ #define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE)\r
+#endif /*_DMA_Channel3 */\r
+\r
+#ifdef _DMA_Channel4\r
+ #define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE)\r
+#endif /*_DMA_Channel4 */\r
+\r
+#ifdef _DMA_Channel5\r
+ #define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE)\r
+#endif /*_DMA_Channel5 */\r
+\r
+#ifdef _DMA_Channel6\r
+ #define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE)\r
+#endif /*_DMA_Channel6 */\r
+\r
+#ifdef _DMA_Channel7\r
+ #define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE)\r
+#endif /*_DMA_Channel7 */\r
+\r
+#ifdef _FLASH\r
+ #define FLASH ((FLASH_TypeDef *) FLASH_BASE)\r
+ #define OB ((OB_TypeDef *) OB_BASE) \r
+#endif /*_FLASH */\r
+\r
+#ifdef _RCC\r
+ #define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#endif /*_RCC */\r
+\r
+#ifdef _SysTick\r
+ #define SysTick ((SysTick_TypeDef *) SysTick_BASE)\r
+#endif /*_SysTick */\r
+\r
+#ifdef _NVIC\r
+ #define NVIC ((NVIC_TypeDef *) NVIC_BASE)\r
+#endif /*_NVIC */\r
+\r
+#ifdef _SCB\r
+ #define SCB ((SCB_TypeDef *) SCB_BASE)\r
+#endif /*_SCB */\r
+/*---------------------- Debug Mode -----------------------------------------*/\r
+#else /* DEBUG */\r
+#ifdef _TIM2\r
+ EXT TIM_TypeDef *TIM2;\r
+#endif /*_TIM2 */\r
+\r
+#ifdef _TIM3\r
+ EXT TIM_TypeDef *TIM3;\r
+#endif /*_TIM3 */\r
+\r
+#ifdef _TIM4\r
+ EXT TIM_TypeDef *TIM4;\r
+#endif /*_TIM4 */\r
+\r
+#ifdef _RTC\r
+ EXT RTC_TypeDef *RTC;\r
+#endif /*_RTC */\r
+\r
+#ifdef _WWDG\r
+ EXT WWDG_TypeDef *WWDG;\r
+#endif /*_WWDG */\r
+\r
+#ifdef _IWDG\r
+ EXT IWDG_TypeDef *IWDG;\r
+#endif /*_IWDG */\r
+\r
+#ifdef _SPI2\r
+ EXT SPI_TypeDef *SPI2;\r
+#endif /*_SPI2 */\r
+\r
+#ifdef _USART2\r
+ EXT USART_TypeDef *USART2;\r
+#endif /*_USART2 */\r
+\r
+#ifdef _USART3\r
+ EXT USART_TypeDef *USART3;\r
+#endif /*_USART3 */\r
+\r
+#ifdef _I2C1\r
+ EXT I2C_TypeDef *I2C1;\r
+#endif /*_I2C1 */\r
+\r
+#ifdef _I2C2\r
+ EXT I2C_TypeDef *I2C2;\r
+#endif /*_I2C2 */\r
+\r
+#ifdef _CAN\r
+ EXT CAN_TypeDef *CAN;\r
+#endif /*_CAN */\r
+\r
+#ifdef _BKP\r
+ EXT BKP_TypeDef *BKP;\r
+#endif /*_BKP */\r
+\r
+#ifdef _PWR\r
+ EXT PWR_TypeDef *PWR;\r
+#endif /*_PWR */\r
+\r
+#ifdef _AFIO\r
+ EXT AFIO_TypeDef *AFIO;\r
+#endif /*_AFIO */\r
+\r
+#ifdef _EXTI\r
+ EXT EXTI_TypeDef *EXTI;\r
+#endif /*_EXTI */\r
+\r
+#ifdef _GPIOA\r
+ EXT GPIO_TypeDef *GPIOA;\r
+#endif /*_GPIOA */\r
+\r
+#ifdef _GPIOB\r
+ EXT GPIO_TypeDef *GPIOB;\r
+#endif /*_GPIOB */\r
+\r
+#ifdef _GPIOC\r
+ EXT GPIO_TypeDef *GPIOC;\r
+#endif /*_GPIOC */\r
+\r
+#ifdef _GPIOD\r
+ EXT GPIO_TypeDef *GPIOD;\r
+#endif /*_GPIOD */\r
+\r
+#ifdef _GPIOE\r
+ EXT GPIO_TypeDef *GPIOE;\r
+#endif /*_GPIOE */\r
+\r
+#ifdef _ADC1\r
+ EXT ADC_TypeDef *ADC1;\r
+#endif /*_ADC1 */\r
+\r
+#ifdef _ADC2\r
+ EXT ADC_TypeDef *ADC2;\r
+#endif /*_ADC2 */\r
+\r
+#ifdef _TIM1\r
+ EXT TIM1_TypeDef *TIM1;\r
+#endif /*_TIM1 */\r
+\r
+#ifdef _SPI1\r
+ EXT SPI_TypeDef *SPI1;\r
+#endif /*_SPI1 */\r
+\r
+#ifdef _USART1\r
+ EXT USART_TypeDef *USART1;\r
+#endif /*_USART1 */\r
+\r
+#ifdef _DMA\r
+ EXT DMA_TypeDef *DMA;\r
+#endif /*_DMA */\r
+\r
+#ifdef _DMA_Channel1\r
+ EXT DMA_Channel_TypeDef *DMA_Channel1;\r
+#endif /*_DMA_Channel1 */\r
+\r
+#ifdef _DMA_Channel2\r
+ EXT DMA_Channel_TypeDef *DMA_Channel2;\r
+#endif /*_DMA_Channel2 */\r
+\r
+#ifdef _DMA_Channel3\r
+ EXT DMA_Channel_TypeDef *DMA_Channel3;\r
+#endif /*_DMA_Channel3 */\r
+\r
+#ifdef _DMA_Channel4\r
+ EXT DMA_Channel_TypeDef *DMA_Channel4;\r
+#endif /*_DMA_Channel4 */\r
+\r
+#ifdef _DMA_Channel5\r
+ EXT DMA_Channel_TypeDef *DMA_Channel5;\r
+#endif /*_DMA_Channel5 */\r
+\r
+#ifdef _DMA_Channel6\r
+ EXT DMA_Channel_TypeDef *DMA_Channel6;\r
+#endif /*_DMA_Channel6 */\r
+\r
+#ifdef _DMA_Channel7\r
+ EXT DMA_Channel_TypeDef *DMA_Channel7;\r
+#endif /*_DMA_Channel7 */\r
+\r
+#ifdef _FLASH\r
+ EXT FLASH_TypeDef *FLASH;\r
+ EXT OB_TypeDef *OB; \r
+#endif /*_FLASH */\r
+\r
+#ifdef _RCC\r
+ EXT RCC_TypeDef *RCC;\r
+#endif /*_RCC */\r
+\r
+#ifdef _SysTick\r
+ EXT SysTick_TypeDef *SysTick;\r
+#endif /*_SysTick */\r
+\r
+#ifdef _NVIC\r
+ EXT NVIC_TypeDef *NVIC;\r
+#endif /*_NVIC */\r
+\r
+#ifdef _SCB\r
+ EXT SCB_TypeDef *SCB;\r
+#endif /*_SCB */\r
+\r
+#endif /* DEBUG */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+#endif /* __STM32F10x_MAP_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_nvic.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* NVIC firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_NVIC_H\r
+#define __STM32F10x_NVIC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* NVIC Init Structure definition */\r
+typedef struct\r
+{\r
+ u8 NVIC_IRQChannel;\r
+ u8 NVIC_IRQChannelPreemptionPriority;\r
+ u8 NVIC_IRQChannelSubPriority;\r
+ FunctionalState NVIC_IRQChannelCmd;\r
+} NVIC_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* IRQ Channels --------------------------------------------------------------*/\r
+#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */\r
+#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */\r
+#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */\r
+#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */\r
+#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */\r
+#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */\r
+#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */\r
+#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */\r
+#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */\r
+#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */\r
+#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */\r
+#define DMAChannel1_IRQChannel ((u8)0x0B) /* DMA Channel 1 global Interrupt */\r
+#define DMAChannel2_IRQChannel ((u8)0x0C) /* DMA Channel 2 global Interrupt */\r
+#define DMAChannel3_IRQChannel ((u8)0x0D) /* DMA Channel 3 global Interrupt */\r
+#define DMAChannel4_IRQChannel ((u8)0x0E) /* DMA Channel 4 global Interrupt */\r
+#define DMAChannel5_IRQChannel ((u8)0x0F) /* DMA Channel 5 global Interrupt */\r
+#define DMAChannel6_IRQChannel ((u8)0x10) /* DMA Channel 6 global Interrupt */\r
+#define DMAChannel7_IRQChannel ((u8)0x11) /* DMA Channel 7 global Interrupt */\r
+#define ADC_IRQChannel ((u8)0x12) /* ADC global Interrupt */\r
+#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */\r
+#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */\r
+#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */\r
+#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */\r
+#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */\r
+#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */\r
+#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */\r
+#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */\r
+#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */\r
+#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */\r
+#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */\r
+#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */\r
+#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */\r
+#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */\r
+#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */\r
+#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */\r
+#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */\r
+#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */\r
+#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */\r
+#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */\r
+#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */\r
+#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */\r
+#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */\r
+#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */\r
+\r
+#define IS_NVIC_IRQ_CHANNEL(CHANNEL) ((CHANNEL == WWDG_IRQChannel) || \\r
+ (CHANNEL == PVD_IRQChannel) || \\r
+ (CHANNEL == TAMPER_IRQChannel) || \\r
+ (CHANNEL == RTC_IRQChannel) || \\r
+ (CHANNEL == FLASH_IRQChannel) || \\r
+ (CHANNEL == RCC_IRQChannel) || \\r
+ (CHANNEL == EXTI0_IRQChannel) || \\r
+ (CHANNEL == EXTI1_IRQChannel) || \\r
+ (CHANNEL == EXTI2_IRQChannel) || \\r
+ (CHANNEL == EXTI3_IRQChannel) || \\r
+ (CHANNEL == EXTI4_IRQChannel) || \\r
+ (CHANNEL == DMAChannel1_IRQChannel) || \\r
+ (CHANNEL == DMAChannel2_IRQChannel) || \\r
+ (CHANNEL == DMAChannel3_IRQChannel) || \\r
+ (CHANNEL == DMAChannel4_IRQChannel) || \\r
+ (CHANNEL == DMAChannel5_IRQChannel) || \\r
+ (CHANNEL == DMAChannel6_IRQChannel) || \\r
+ (CHANNEL == DMAChannel7_IRQChannel) || \\r
+ (CHANNEL == ADC_IRQChannel) || \\r
+ (CHANNEL == USB_HP_CAN_TX_IRQChannel) || \\r
+ (CHANNEL == USB_LP_CAN_RX0_IRQChannel) || \\r
+ (CHANNEL == CAN_RX1_IRQChannel) || \\r
+ (CHANNEL == CAN_SCE_IRQChannel) || \\r
+ (CHANNEL == EXTI9_5_IRQChannel) || \\r
+ (CHANNEL == TIM1_BRK_IRQChannel) || \\r
+ (CHANNEL == TIM1_UP_IRQChannel) || \\r
+ (CHANNEL == TIM1_TRG_COM_IRQChannel) || \\r
+ (CHANNEL == TIM1_CC_IRQChannel) || \\r
+ (CHANNEL == TIM2_IRQChannel) || \\r
+ (CHANNEL == TIM3_IRQChannel) || \\r
+ (CHANNEL == TIM4_IRQChannel) || \\r
+ (CHANNEL == I2C1_EV_IRQChannel) || \\r
+ (CHANNEL == I2C1_ER_IRQChannel) || \\r
+ (CHANNEL == I2C2_EV_IRQChannel) || \\r
+ (CHANNEL == I2C2_ER_IRQChannel) || \\r
+ (CHANNEL == SPI1_IRQChannel) || \\r
+ (CHANNEL == SPI2_IRQChannel) || \\r
+ (CHANNEL == USART1_IRQChannel) || \\r
+ (CHANNEL == USART2_IRQChannel) || \\r
+ (CHANNEL == USART3_IRQChannel) || \\r
+ (CHANNEL == EXTI15_10_IRQChannel) || \\r
+ (CHANNEL == RTCAlarm_IRQChannel) || \\r
+ (CHANNEL == USBWakeUp_IRQChannel))\r
+\r
+/* System Handlers -----------------------------------------------------------*/\r
+#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */\r
+#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */\r
+#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */\r
+#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */\r
+#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */\r
+#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */\r
+#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */\r
+#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */\r
+#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */\r
+\r
+#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \\r
+ (HANDLER == SystemHandler_BusFault) || \\r
+ (HANDLER == SystemHandler_UsageFault))\r
+\r
+#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \\r
+ (HANDLER == SystemHandler_BusFault) || \\r
+ (HANDLER == SystemHandler_UsageFault) || \\r
+ (HANDLER == SystemHandler_SVCall) || \\r
+ (HANDLER == SystemHandler_DebugMonitor) || \\r
+ (HANDLER == SystemHandler_PSV) || \\r
+ (HANDLER == SystemHandler_SysTick))\r
+\r
+#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \\r
+ (HANDLER == SystemHandler_BusFault) || \\r
+ (HANDLER == SystemHandler_SVCall))\r
+\r
+#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_NMI) || \\r
+ (HANDLER == SystemHandler_PSV) || \\r
+ (HANDLER == SystemHandler_SysTick))\r
+\r
+#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_PSV) || \\r
+ (HANDLER == SystemHandler_SysTick))\r
+\r
+#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \\r
+ (HANDLER == SystemHandler_BusFault) || \\r
+ (HANDLER == SystemHandler_UsageFault) || \\r
+ (HANDLER == SystemHandler_SVCall) || \\r
+ (HANDLER == SystemHandler_DebugMonitor) || \\r
+ (HANDLER == SystemHandler_PSV) || \\r
+ (HANDLER == SystemHandler_SysTick))\r
+\r
+#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_HardFault) || \\r
+ (HANDLER == SystemHandler_MemoryManage) || \\r
+ (HANDLER == SystemHandler_BusFault) || \\r
+ (HANDLER == SystemHandler_UsageFault) || \\r
+ (HANDLER == SystemHandler_DebugMonitor)) \r
+\r
+#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \\r
+ (HANDLER == SystemHandler_BusFault))\r
+\r
+\r
+/* Vector Table Base ---------------------------------------------------------*/\r
+#define NVIC_VectTab_RAM ((u32)0x20000000)\r
+#define NVIC_VectTab_FLASH ((u32)0x00000000)\r
+\r
+#define IS_NVIC_VECTTAB(VECTTAB) ((VECTTAB == NVIC_VectTab_RAM) || \\r
+ (VECTTAB == NVIC_VectTab_FLASH))\r
+\r
+/* System Low Power ----------------------------------------------------------*/\r
+#define NVIC_LP_SEVONPEND ((u8)0x10)\r
+#define NVIC_LP_SLEEPDEEP ((u8)0x04)\r
+#define NVIC_LP_SLEEPONEXIT ((u8)0x02)\r
+\r
+#define IS_NVIC_LP(LP) ((LP == NVIC_LP_SEVONPEND) || \\r
+ (LP == NVIC_LP_SLEEPDEEP) || \\r
+ (LP == NVIC_LP_SLEEPONEXIT))\r
+\r
+/* Preemption Priority Group -------------------------------------------------*/\r
+#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) ((GROUP == NVIC_PriorityGroup_0) || \\r
+ (GROUP == NVIC_PriorityGroup_1) || \\r
+ (GROUP == NVIC_PriorityGroup_2) || \\r
+ (GROUP == NVIC_PriorityGroup_3) || \\r
+ (GROUP == NVIC_PriorityGroup_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) (PRIORITY < 0x10)\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) (PRIORITY < 0x10)\r
+#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x3FFFFF)\r
+#define IS_NVIC_BASE_PRI(PRI) ((PRI > 0x00) && (PRI < 0x10))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void NVIC_DeInit(void);\r
+void NVIC_SCBDeInit(void);\r
+void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SETPRIMASK(void);\r
+void NVIC_RESETPRIMASK(void);\r
+void NVIC_SETFAULTMASK(void);\r
+void NVIC_RESETFAULTMASK(void);\r
+void NVIC_BASEPRICONFIG(u32 NewPriority);\r
+u32 NVIC_GetBASEPRI(void);\r
+u16 NVIC_GetCurrentPendingIRQChannel(void);\r
+ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);\r
+void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);\r
+void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);\r
+u16 NVIC_GetCurrentActiveHandler(void);\r
+ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);\r
+u32 NVIC_GetCPUID(void);\r
+void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);\r
+void NVIC_GenerateSystemReset(void);\r
+void NVIC_GenerateCoreReset(void);\r
+void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);\r
+void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);\r
+void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,\r
+ u8 SystemHandlerSubPriority);\r
+ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);\r
+void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);\r
+void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);\r
+ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);\r
+u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);\r
+u32 NVIC_GetFaultAddress(u32 SystemHandler);\r
+\r
+#endif /* __STM32F10x_NVIC_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_pwr.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* PWR firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_PWR_H\r
+#define __STM32F10x_PWR_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* PVD detection level */\r
+#define PWR_PVDLevel_2V2 ((u32)0x00000000)\r
+#define PWR_PVDLevel_2V3 ((u32)0x00000020)\r
+#define PWR_PVDLevel_2V4 ((u32)0x00000040)\r
+#define PWR_PVDLevel_2V5 ((u32)0x00000060)\r
+#define PWR_PVDLevel_2V6 ((u32)0x00000080)\r
+#define PWR_PVDLevel_2V7 ((u32)0x000000A0)\r
+#define PWR_PVDLevel_2V8 ((u32)0x000000C0)\r
+#define PWR_PVDLevel_2V9 ((u32)0x000000E0)\r
+\r
+#define IS_PWR_PVD_LEVEL(LEVEL) ((LEVEL == PWR_PVDLevel_2V2) || (LEVEL == PWR_PVDLevel_2V3)|| \\r
+ (LEVEL == PWR_PVDLevel_2V4) || (LEVEL == PWR_PVDLevel_2V5)|| \\r
+ (LEVEL == PWR_PVDLevel_2V6) || (LEVEL == PWR_PVDLevel_2V7)|| \\r
+ (LEVEL == PWR_PVDLevel_2V8) || (LEVEL == PWR_PVDLevel_2V9))\r
+\r
+/* Regulator state is STOP mode */\r
+#define PWR_Regulator_ON ((u32)0x00000000)\r
+#define PWR_Regulator_LowPower ((u32)0x00000001)\r
+\r
+#define IS_PWR_REGULATOR(REGULATOR) ((REGULATOR == PWR_Regulator_ON) || \\r
+ (REGULATOR == PWR_Regulator_LowPower))\r
+\r
+/* STOP mode entry */\r
+#define PWR_STOPEntry_WFI ((u8)0x01)\r
+#define PWR_STOPEntry_WFE ((u8)0x02)\r
+\r
+#define IS_PWR_STOP_ENTRY(ENTRY) ((ENTRY == PWR_STOPEntry_WFI) || (ENTRY == PWR_STOPEntry_WFE))\r
+ \r
+/* PWR Flag */\r
+#define PWR_FLAG_WU ((u32)0x00000001)\r
+#define PWR_FLAG_SB ((u32)0x00000002)\r
+#define PWR_FLAG_PVDO ((u32)0x00000004)\r
+\r
+#define IS_PWR_GET_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB) || \\r
+ (FLAG == PWR_FLAG_PVDO))\r
+#define IS_PWR_CLEAR_FLAG(FLAG) ((FLAG == PWR_FLAG_WU) || (FLAG == PWR_FLAG_SB))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void PWR_DeInit(void);\r
+void PWR_BackupAccessCmd(FunctionalState NewState);\r
+void PWR_PVDCmd(FunctionalState NewState);\r
+void PWR_PVDLevelConfig(u32 PWR_PVDLevel);\r
+void PWR_WakeUpPinCmd(FunctionalState NewState);\r
+void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry);\r
+void PWR_EnterSTANDBYMode(void);\r
+FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG);\r
+void PWR_ClearFlag(u32 PWR_FLAG);\r
+\r
+#endif /* __STM32F10x_PWR_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_rcc.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* RCC firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_RCC_H\r
+#define __STM32F10x_RCC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef struct\r
+{\r
+ u32 SYSCLK_Frequency;\r
+ u32 HCLK_Frequency;\r
+ u32 PCLK1_Frequency;\r
+ u32 PCLK2_Frequency;\r
+ u32 ADCCLK_Frequency;\r
+}RCC_ClocksTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* HSE configuration */\r
+#define RCC_HSE_OFF ((u32)0x00000000)\r
+#define RCC_HSE_ON ((u32)0x00010000)\r
+#define RCC_HSE_Bypass ((u32)0x00040000)\r
+\r
+#define IS_RCC_HSE(HSE) ((HSE == RCC_HSE_OFF) || (HSE == RCC_HSE_ON) || \\r
+ (HSE == RCC_HSE_Bypass))\r
+\r
+/* PLL entry clock source */\r
+#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000)\r
+#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000)\r
+#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000)\r
+\r
+#define IS_RCC_PLL_SOURCE(SOURCE) ((SOURCE == RCC_PLLSource_HSI_Div2) || \\r
+ (SOURCE == RCC_PLLSource_HSE_Div1) || \\r
+ (SOURCE == RCC_PLLSource_HSE_Div2))\r
+\r
+/* PLL multiplication factor */\r
+#define RCC_PLLMul_2 ((u32)0x00000000)\r
+#define RCC_PLLMul_3 ((u32)0x00040000)\r
+#define RCC_PLLMul_4 ((u32)0x00080000)\r
+#define RCC_PLLMul_5 ((u32)0x000C0000)\r
+#define RCC_PLLMul_6 ((u32)0x00100000)\r
+#define RCC_PLLMul_7 ((u32)0x00140000)\r
+#define RCC_PLLMul_8 ((u32)0x00180000)\r
+#define RCC_PLLMul_9 ((u32)0x001C0000)\r
+#define RCC_PLLMul_10 ((u32)0x00200000)\r
+#define RCC_PLLMul_11 ((u32)0x00240000)\r
+#define RCC_PLLMul_12 ((u32)0x00280000)\r
+#define RCC_PLLMul_13 ((u32)0x002C0000)\r
+#define RCC_PLLMul_14 ((u32)0x00300000)\r
+#define RCC_PLLMul_15 ((u32)0x00340000)\r
+#define RCC_PLLMul_16 ((u32)0x00380000)\r
+\r
+#define IS_RCC_PLL_MUL(MUL) ((MUL == RCC_PLLMul_2) || (MUL == RCC_PLLMul_3) ||\\r
+ (MUL == RCC_PLLMul_4) || (MUL == RCC_PLLMul_5) ||\\r
+ (MUL == RCC_PLLMul_6) || (MUL == RCC_PLLMul_7) ||\\r
+ (MUL == RCC_PLLMul_8) || (MUL == RCC_PLLMul_9) ||\\r
+ (MUL == RCC_PLLMul_10) || (MUL == RCC_PLLMul_11) ||\\r
+ (MUL == RCC_PLLMul_12) || (MUL == RCC_PLLMul_13) ||\\r
+ (MUL == RCC_PLLMul_14) || (MUL == RCC_PLLMul_15) ||\\r
+ (MUL == RCC_PLLMul_16))\r
+\r
+/* System clock source */\r
+#define RCC_SYSCLKSource_HSI ((u32)0x00000000)\r
+#define RCC_SYSCLKSource_HSE ((u32)0x00000001)\r
+#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002)\r
+\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) ((SOURCE == RCC_SYSCLKSource_HSI) || \\r
+ (SOURCE == RCC_SYSCLKSource_HSE) || \\r
+ (SOURCE == RCC_SYSCLKSource_PLLCLK))\r
+\r
+/* AHB clock source */\r
+#define RCC_SYSCLK_Div1 ((u32)0x00000000)\r
+#define RCC_SYSCLK_Div2 ((u32)0x00000080)\r
+#define RCC_SYSCLK_Div4 ((u32)0x00000090)\r
+#define RCC_SYSCLK_Div8 ((u32)0x000000A0)\r
+#define RCC_SYSCLK_Div16 ((u32)0x000000B0)\r
+#define RCC_SYSCLK_Div64 ((u32)0x000000C0)\r
+#define RCC_SYSCLK_Div128 ((u32)0x000000D0)\r
+#define RCC_SYSCLK_Div256 ((u32)0x000000E0)\r
+#define RCC_SYSCLK_Div512 ((u32)0x000000F0)\r
+\r
+#define IS_RCC_HCLK(HCLK) ((HCLK == RCC_SYSCLK_Div1) || (HCLK == RCC_SYSCLK_Div2) || \\r
+ (HCLK == RCC_SYSCLK_Div4) || (HCLK == RCC_SYSCLK_Div8) || \\r
+ (HCLK == RCC_SYSCLK_Div16) || (HCLK == RCC_SYSCLK_Div64) || \\r
+ (HCLK == RCC_SYSCLK_Div128) || (HCLK == RCC_SYSCLK_Div256) || \\r
+ (HCLK == RCC_SYSCLK_Div512))\r
+\r
+/* APB1/APB2 clock source */\r
+#define RCC_HCLK_Div1 ((u32)0x00000000)\r
+#define RCC_HCLK_Div2 ((u32)0x00000400)\r
+#define RCC_HCLK_Div4 ((u32)0x00000500)\r
+#define RCC_HCLK_Div8 ((u32)0x00000600)\r
+#define RCC_HCLK_Div16 ((u32)0x00000700)\r
+\r
+#define IS_RCC_PCLK(PCLK) ((PCLK == RCC_HCLK_Div1) || (PCLK == RCC_HCLK_Div2) || \\r
+ (PCLK == RCC_HCLK_Div4) || (PCLK == RCC_HCLK_Div8) || \\r
+ (PCLK == RCC_HCLK_Div16))\r
+\r
+/* RCC Interrupt source */\r
+#define RCC_IT_LSIRDY ((u8)0x01)\r
+#define RCC_IT_LSERDY ((u8)0x02)\r
+#define RCC_IT_HSIRDY ((u8)0x04)\r
+#define RCC_IT_HSERDY ((u8)0x08)\r
+#define RCC_IT_PLLRDY ((u8)0x10)\r
+#define RCC_IT_CSS ((u8)0x80)\r
+\r
+#define IS_RCC_IT(IT) (((IT & (u8)0xE0) == 0x00) && (IT != 0x00))\r
+#define IS_RCC_GET_IT(IT) ((IT == RCC_IT_LSIRDY) || (IT == RCC_IT_LSERDY) || \\r
+ (IT == RCC_IT_HSIRDY) || (IT == RCC_IT_HSERDY) || \\r
+ (IT == RCC_IT_PLLRDY) || (IT == RCC_IT_CSS))\r
+#define IS_RCC_CLEAR_IT(IT) (((IT & (u8)0x60) == 0x00) && (IT != 0x00))\r
+\r
+/* USB clock source */\r
+#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00)\r
+#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01)\r
+\r
+#define IS_RCC_USBCLK_SOURCE(SOURCE) ((SOURCE == RCC_USBCLKSource_PLLCLK_1Div5) || \\r
+ (SOURCE == RCC_USBCLKSource_PLLCLK_Div1))\r
+\r
+/* ADC clock source */\r
+#define RCC_PCLK2_Div2 ((u32)0x00000000)\r
+#define RCC_PCLK2_Div4 ((u32)0x00004000)\r
+#define RCC_PCLK2_Div6 ((u32)0x00008000)\r
+#define RCC_PCLK2_Div8 ((u32)0x0000C000)\r
+\r
+#define IS_RCC_ADCCLK(ADCCLK) ((ADCCLK == RCC_PCLK2_Div2) || (ADCCLK == RCC_PCLK2_Div4) || \\r
+ (ADCCLK == RCC_PCLK2_Div6) || (ADCCLK == RCC_PCLK2_Div8))\r
+\r
+/* LSE configuration */\r
+#define RCC_LSE_OFF ((u8)0x00)\r
+#define RCC_LSE_ON ((u8)0x01)\r
+#define RCC_LSE_Bypass ((u8)0x04)\r
+\r
+#define IS_RCC_LSE(LSE) ((LSE == RCC_LSE_OFF) || (LSE == RCC_LSE_ON) || \\r
+ (LSE == RCC_LSE_Bypass))\r
+\r
+/* RTC clock source */\r
+#define RCC_RTCCLKSource_LSE ((u32)0x00000100)\r
+#define RCC_RTCCLKSource_LSI ((u32)0x00000200)\r
+#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300)\r
+\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) ((SOURCE == RCC_RTCCLKSource_LSE) || \\r
+ (SOURCE == RCC_RTCCLKSource_LSI) || \\r
+ (SOURCE == RCC_RTCCLKSource_HSE_Div128))\r
+\r
+/* AHB peripheral */\r
+#define RCC_AHBPeriph_DMA ((u32)0x00000001)\r
+#define RCC_AHBPeriph_SRAM ((u32)0x00000004)\r
+#define RCC_AHBPeriph_FLITF ((u32)0x00000010)\r
+\r
+#define IS_RCC_AHB_PERIPH(PERIPH) (((PERIPH & 0xFFFFFFEA) == 0x00) && (PERIPH != 0x00))\r
+\r
+/* APB2 peripheral */\r
+#define RCC_APB2Periph_AFIO ((u32)0x00000001)\r
+#define RCC_APB2Periph_GPIOA ((u32)0x00000004)\r
+#define RCC_APB2Periph_GPIOB ((u32)0x00000008)\r
+#define RCC_APB2Periph_GPIOC ((u32)0x00000010)\r
+#define RCC_APB2Periph_GPIOD ((u32)0x00000020)\r
+#define RCC_APB2Periph_GPIOE ((u32)0x00000040)\r
+#define RCC_APB2Periph_ADC1 ((u32)0x00000200)\r
+#define RCC_APB2Periph_ADC2 ((u32)0x00000400)\r
+#define RCC_APB2Periph_TIM1 ((u32)0x00000800)\r
+#define RCC_APB2Periph_SPI1 ((u32)0x00001000)\r
+#define RCC_APB2Periph_USART1 ((u32)0x00004000)\r
+#define RCC_APB2Periph_ALL ((u32)0x00005E7D)\r
+\r
+#define IS_RCC_APB2_PERIPH(PERIPH) (((PERIPH & 0xFFFFA182) == 0x00) && (PERIPH != 0x00))\r
+\r
+/* APB1 peripheral */\r
+#define RCC_APB1Periph_TIM2 ((u32)0x00000001)\r
+#define RCC_APB1Periph_TIM3 ((u32)0x00000002)\r
+#define RCC_APB1Periph_TIM4 ((u32)0x00000004)\r
+#define RCC_APB1Periph_WWDG ((u32)0x00000800)\r
+#define RCC_APB1Periph_SPI2 ((u32)0x00004000)\r
+#define RCC_APB1Periph_USART2 ((u32)0x00020000)\r
+#define RCC_APB1Periph_USART3 ((u32)0x00040000)\r
+#define RCC_APB1Periph_I2C1 ((u32)0x00200000)\r
+#define RCC_APB1Periph_I2C2 ((u32)0x00400000)\r
+#define RCC_APB1Periph_USB ((u32)0x00800000)\r
+#define RCC_APB1Periph_CAN ((u32)0x02000000)\r
+#define RCC_APB1Periph_BKP ((u32)0x08000000)\r
+#define RCC_APB1Periph_PWR ((u32)0x10000000)\r
+#define RCC_APB1Periph_ALL ((u32)0x1AE64807)\r
+\r
+#define IS_RCC_APB1_PERIPH(PERIPH) (((PERIPH & 0xE519B7F8) == 0x00) && (PERIPH != 0x00))\r
+\r
+/* Clock source to output on MCO pin */\r
+#define RCC_MCO_NoClock ((u8)0x00)\r
+#define RCC_MCO_SYSCLK ((u8)0x04)\r
+#define RCC_MCO_HSI ((u8)0x05)\r
+#define RCC_MCO_HSE ((u8)0x06)\r
+#define RCC_MCO_PLLCLK_Div2 ((u8)0x07)\r
+\r
+#define IS_RCC_MCO(MCO) ((MCO == RCC_MCO_NoClock) || (MCO == RCC_MCO_HSI) || \\r
+ (MCO == RCC_MCO_SYSCLK) || (MCO == RCC_MCO_HSE) || \\r
+ (MCO == RCC_MCO_PLLCLK_Div2))\r
+\r
+/* RCC Flag */\r
+#define RCC_FLAG_HSIRDY ((u8)0x20)\r
+#define RCC_FLAG_HSERDY ((u8)0x31)\r
+#define RCC_FLAG_PLLRDY ((u8)0x39)\r
+#define RCC_FLAG_LSERDY ((u8)0x41)\r
+#define RCC_FLAG_LSIRDY ((u8)0x61)\r
+#define RCC_FLAG_PINRST ((u8)0x7A)\r
+#define RCC_FLAG_PORRST ((u8)0x7B)\r
+#define RCC_FLAG_SFTRST ((u8)0x7C)\r
+#define RCC_FLAG_IWDGRST ((u8)0x7D)\r
+#define RCC_FLAG_WWDGRST ((u8)0x7E)\r
+#define RCC_FLAG_LPWRRST ((u8)0x7F)\r
+\r
+#define IS_RCC_FLAG(FLAG) ((FLAG == RCC_FLAG_HSIRDY) || (FLAG == RCC_FLAG_HSERDY) || \\r
+ (FLAG == RCC_FLAG_PLLRDY) || (FLAG == RCC_FLAG_LSERDY) || \\r
+ (FLAG == RCC_FLAG_LSIRDY) || (FLAG == RCC_FLAG_PINRST) || \\r
+ (FLAG == RCC_FLAG_PORRST) || (FLAG == RCC_FLAG_SFTRST) || \\r
+ (FLAG == RCC_FLAG_IWDGRST)|| (FLAG == RCC_FLAG_WWDGRST)|| \\r
+ (FLAG == RCC_FLAG_LPWRRST))\r
+\r
+#define IS_RCC_CALIBRATION_VALUE(VALUE) (VALUE <= 0x1F)\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void RCC_DeInit(void);\r
+void RCC_HSEConfig(u32 RCC_HSE);\r
+void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);\r
+u8 RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(u32 RCC_HCLK);\r
+void RCC_PCLK1Config(u32 RCC_PCLK1);\r
+void RCC_PCLK2Config(u32 RCC_PCLK2);\r
+void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);\r
+void RCC_USBCLKConfig(u32 RCC_USBCLKSource);\r
+void RCC_ADCCLKConfig(u32 RCC_ADCCLK);\r
+void RCC_LSEConfig(u32 RCC_LSE);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_BackupResetCmd(FunctionalState NewState);\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCOConfig(u8 RCC_MCO);\r
+FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(u8 RCC_IT);\r
+void RCC_ClearITPendingBit(u8 RCC_IT);\r
+\r
+#endif /* __STM32F10x_RCC_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_rtc.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* RTC firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_RTC_H\r
+#define __STM32F10x_RTC_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* RTC interrupts define -----------------------------------------------------*/\r
+#define RTC_IT_OW ((u16)0x0004) /* Overflow interrupt */\r
+#define RTC_IT_ALR ((u16)0x0002) /* Alarm interrupt */\r
+#define RTC_IT_SEC ((u16)0x0001) /* Second interrupt */\r
+\r
+#define IS_RTC_IT(IT) (((IT & (u16)0xFFF8) == 0x00) && (IT != 0x00))\r
+\r
+#define IS_RTC_GET_IT(IT) ((IT == RTC_IT_OW) || (IT == RTC_IT_ALR) || \\r
+ (IT == RTC_IT_SEC))\r
+ \r
+/* RTC interrupts flags ------------------------------------------------------*/\r
+#define RTC_FLAG_RTOFF ((u16)0x0020) /* RTC Operation OFF flag */\r
+#define RTC_FLAG_RSF ((u16)0x0008) /* Registers Synchronized flag */\r
+#define RTC_FLAG_OW ((u16)0x0004) /* Overflow flag */\r
+#define RTC_FLAG_ALR ((u16)0x0002) /* Alarm flag */\r
+#define RTC_FLAG_SEC ((u16)0x0001) /* Second flag */\r
+\r
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFFF0) == 0x00) && (FLAG != 0x00))\r
+\r
+#define IS_RTC_GET_FLAG(FLAG) ((FLAG == RTC_FLAG_RTOFF) || (FLAG == RTC_FLAG_RSF) || \\r
+ (FLAG == RTC_FLAG_OW) || (FLAG == RTC_FLAG_ALR) || \\r
+ (FLAG == RTC_FLAG_SEC))\r
+\r
+#define IS_RTC_PRESCALER(PRESCALER) (PRESCALER <= 0xFFFFF)\r
+ \r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState);\r
+void RTC_EnterConfigMode(void);\r
+void RTC_ExitConfigMode(void);\r
+u32 RTC_GetCounter(void);\r
+void RTC_SetCounter(u32 CounterValue);\r
+u32 RTC_GetPrescaler(void);\r
+void RTC_SetPrescaler(u32 PrescalerValue);\r
+void RTC_SetAlarm(u32 AlarmValue);\r
+u32 RTC_GetDivider(void);\r
+void RTC_WaitForLastTask(void);\r
+void RTC_WaitForSynchro(void);\r
+FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG);\r
+void RTC_ClearFlag(u16 RTC_FLAG);\r
+ITStatus RTC_GetITStatus(u16 RTC_IT);\r
+void RTC_ClearITPendingBit(u16 RTC_IT);\r
+\r
+#endif /* __STM32F10x_RTC_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_spi.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* SPI firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_SPI_H\r
+#define __STM32F10x_SPI_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* SPI Init structure definition */\r
+typedef struct\r
+{\r
+ u16 SPI_Direction;\r
+ u16 SPI_Mode;\r
+ u16 SPI_DataSize;\r
+ u16 SPI_CPOL;\r
+ u16 SPI_CPHA;\r
+ u16 SPI_NSS;\r
+ u16 SPI_BaudRatePrescaler;\r
+ u16 SPI_FirstBit;\r
+ u16 SPI_CRCPolynomial;\r
+}SPI_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* SPI data direction mode */\r
+#define SPI_Direction_2Lines_FullDuplex ((u16)0x0000)\r
+#define SPI_Direction_2Lines_RxOnly ((u16)0x0400)\r
+#define SPI_Direction_1Line_Rx ((u16)0x8000)\r
+#define SPI_Direction_1Line_Tx ((u16)0xC000)\r
+\r
+#define IS_SPI_DIRECTION_MODE(MODE) ((MODE == SPI_Direction_2Lines_FullDuplex) || \\r
+ (MODE == SPI_Direction_2Lines_RxOnly) || \\r
+ (MODE == SPI_Direction_1Line_Rx) || \\r
+ (MODE == SPI_Direction_1Line_Tx))\r
+\r
+/* SPI master/slave mode */\r
+#define SPI_Mode_Master ((u16)0x0104)\r
+#define SPI_Mode_Slave ((u16)0x0000)\r
+\r
+#define IS_SPI_MODE(MODE) ((MODE == SPI_Mode_Master) || \\r
+ (MODE == SPI_Mode_Slave))\r
+\r
+/* SPI data size */\r
+#define SPI_DataSize_16b ((u16)0x0800)\r
+#define SPI_DataSize_8b ((u16)0x0000)\r
+\r
+#define IS_SPI_DATASIZE(DATASIZE) ((DATASIZE == SPI_DataSize_16b) || \\r
+ (DATASIZE == SPI_DataSize_8b))\r
+\r
+/* SPI Clock Polarity */\r
+#define SPI_CPOL_Low ((u16)0x0000)\r
+#define SPI_CPOL_High ((u16)0x0002)\r
+\r
+#define IS_SPI_CPOL(CPOL) ((CPOL == SPI_CPOL_Low) || \\r
+ (CPOL == SPI_CPOL_High))\r
+\r
+/* SPI Clock Phase */\r
+#define SPI_CPHA_1Edge ((u16)0x0000)\r
+#define SPI_CPHA_2Edge ((u16)0x0001)\r
+\r
+#define IS_SPI_CPHA(CPHA) ((CPHA == SPI_CPHA_1Edge) || \\r
+ (CPHA == SPI_CPHA_2Edge))\r
+\r
+/* SPI Slave Select management */\r
+#define SPI_NSS_Soft ((u16)0x0200)\r
+#define SPI_NSS_Hard ((u16)0x0000)\r
+\r
+#define IS_SPI_NSS(NSS) ((NSS == SPI_NSS_Soft) || \\r
+ (NSS == SPI_NSS_Hard))\r
+\r
+/* SPI BaudRate Prescaler */\r
+#define SPI_BaudRatePrescaler_2 ((u16)0x0000)\r
+#define SPI_BaudRatePrescaler_4 ((u16)0x0008)\r
+#define SPI_BaudRatePrescaler_8 ((u16)0x0010)\r
+#define SPI_BaudRatePrescaler_16 ((u16)0x0018)\r
+#define SPI_BaudRatePrescaler_32 ((u16)0x0020)\r
+#define SPI_BaudRatePrescaler_64 ((u16)0x0028)\r
+#define SPI_BaudRatePrescaler_128 ((u16)0x0030)\r
+#define SPI_BaudRatePrescaler_256 ((u16)0x0038)\r
+\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) ((PRESCALER == SPI_BaudRatePrescaler_2) || \\r
+ (PRESCALER == SPI_BaudRatePrescaler_4) || \\r
+ (PRESCALER == SPI_BaudRatePrescaler_8) || \\r
+ (PRESCALER == SPI_BaudRatePrescaler_16) || \\r
+ (PRESCALER == SPI_BaudRatePrescaler_32) || \\r
+ (PRESCALER == SPI_BaudRatePrescaler_64) || \\r
+ (PRESCALER == SPI_BaudRatePrescaler_128) || \\r
+ (PRESCALER == SPI_BaudRatePrescaler_256))\r
+\r
+/* SPI MSB/LSB transmission */\r
+#define SPI_FirstBit_MSB ((u16)0x0000)\r
+#define SPI_FirstBit_LSB ((u16)0x0080)\r
+\r
+#define IS_SPI_FIRST_BIT(BIT) ((BIT == SPI_FirstBit_MSB) || \\r
+ (BIT == SPI_FirstBit_LSB))\r
+\r
+/* SPI DMA transfer requests */\r
+#define SPI_DMAReq_Tx ((u16)0x0002)\r
+#define SPI_DMAReq_Rx ((u16)0x0001)\r
+\r
+#define IS_SPI_DMA_REQ(REQ) (((REQ & (u16)0xFFFC) == 0x00) && (REQ != 0x00))\r
+\r
+/* SPI NSS internal software mangement */\r
+#define SPI_NSSInternalSoft_Set ((u16)0x0100)\r
+#define SPI_NSSInternalSoft_Reset ((u16)0xFEFF)\r
+\r
+#define IS_SPI_NSS_INTERNAL(INTERNAL) ((INTERNAL == SPI_NSSInternalSoft_Set) || \\r
+ (INTERNAL == SPI_NSSInternalSoft_Reset))\r
+\r
+/* SPI CRC Transmit/Receive */\r
+#define SPI_CRC_Tx ((u8)0x00)\r
+#define SPI_CRC_Rx ((u8)0x01)\r
+\r
+#define IS_SPI_CRC(CRC) ((CRC == SPI_CRC_Tx) || (CRC == SPI_CRC_Rx))\r
+\r
+/* SPI direction transmit/receive */\r
+#define SPI_Direction_Rx ((u16)0xBFFF)\r
+#define SPI_Direction_Tx ((u16)0x4000)\r
+\r
+#define IS_SPI_DIRECTION(DIRECTION) ((DIRECTION == SPI_Direction_Rx) || \\r
+ (DIRECTION == SPI_Direction_Tx))\r
+\r
+/* SPI interrupts definition */\r
+#define SPI_IT_TXE ((u8)0x71)\r
+#define SPI_IT_RXNE ((u8)0x60)\r
+#define SPI_IT_ERR ((u8)0x50)\r
+\r
+#define IS_SPI_CONFIG_IT(IT) ((IT == SPI_IT_TXE) || (IT == SPI_IT_RXNE) || \\r
+ (IT == SPI_IT_ERR))\r
+\r
+#define SPI_IT_OVR ((u8)0x56)\r
+#define SPI_IT_MODF ((u8)0x55)\r
+#define SPI_IT_CRCERR ((u8)0x54)\r
+\r
+#define IS_SPI_CLEAR_IT(IT) ((IT == SPI_IT_OVR) || (IT == SPI_IT_MODF) || \\r
+ (IT == SPI_IT_CRCERR))\r
+\r
+#define IS_SPI_GET_IT(IT) ((IT == SPI_IT_TXE) || (IT == SPI_IT_RXNE) || \\r
+ (IT == SPI_IT_OVR) || (IT == SPI_IT_MODF) || \\r
+ (IT == SPI_IT_CRCERR))\r
+\r
+/* SPI flags definition */\r
+#define SPI_FLAG_RXNE ((u16)0x0001)\r
+#define SPI_FLAG_TXE ((u16)0x0002)\r
+#define SPI_FLAG_CRCERR ((u16)0x0010)\r
+#define SPI_FLAG_MODF ((u16)0x0020)\r
+#define SPI_FLAG_OVR ((u16)0x0040)\r
+#define SPI_FLAG_BSY ((u16)0x0080)\r
+\r
+#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFF8F) == 0x00) && (FLAG != 0x00))\r
+#define IS_SPI_GET_FLAG(FLAG) ((FLAG == SPI_FLAG_BSY) || (FLAG == SPI_FLAG_OVR) || \\r
+ (FLAG == SPI_FLAG_MODF) || (FLAG == SPI_FLAG_CRCERR) || \\r
+ (FLAG == SPI_FLAG_TXE) || (FLAG == SPI_FLAG_RXNE))\r
+\r
+/* SPI CRC polynomial --------------------------------------------------------*/\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (POLYNOMIAL >= 0x1)\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void SPI_DeInit(SPI_TypeDef* SPIx);\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_ITConfig(SPI_TypeDef* SPIx, u8 SPI_IT, FunctionalState NewState);\r
+void SPI_DMACmd(SPI_TypeDef* SPIx, u16 SPI_DMAReq, FunctionalState NewState);\r
+void SPI_SendData(SPI_TypeDef* SPIx, u16 Data);\r
+u16 SPI_ReceiveData(SPI_TypeDef* SPIx);\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft);\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize);\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC);\r
+u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction);\r
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_FLAG);\r
+void SPI_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_FLAG);\r
+ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_IT);\r
+void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_IT);\r
+\r
+#endif /*__STM32F10x_SPI_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_systick.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* SysTick firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_SYSTICK_H\r
+#define __STM32F10x_SYSTICK_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* SysTick clock source */\r
+#define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK ((u32)0x00000004)\r
+\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) ((SOURCE == SysTick_CLKSource_HCLK) || \\r
+ (SOURCE == SysTick_CLKSource_HCLK_Div8))\r
+\r
+/* SysTick counter state */\r
+#define SysTick_Counter_Disable ((u32)0xFFFFFFFE)\r
+#define SysTick_Counter_Enable ((u32)0x00000001)\r
+#define SysTick_Counter_Clear ((u32)0x00000000)\r
+\r
+#define IS_SYSTICK_COUNTER(COUNTER) ((COUNTER == SysTick_Counter_Disable) || \\r
+ (COUNTER == SysTick_Counter_Enable) || \\r
+ (COUNTER == SysTick_Counter_Clear))\r
+\r
+/* SysTick Flag */\r
+#define SysTick_FLAG_COUNT ((u8)0x30)\r
+#define SysTick_FLAG_SKEW ((u8)0x5E)\r
+#define SysTick_FLAG_NOREF ((u8)0x5F)\r
+\r
+#define IS_SYSTICK_FLAG(FLAG) ((FLAG == SysTick_FLAG_COUNT) || \\r
+ (FLAG == SysTick_FLAG_SKEW) || \\r
+ (FLAG == SysTick_FLAG_NOREF))\r
+\r
+#define IS_SYSTICK_RELOAD(RELOAD) ((RELOAD > 0) || (RELOAD <= 0xFFFFFF))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void SysTick_CLKSourceConfig(u32 SysTick_CLKSource);\r
+void SysTick_SetReload(u32 Reload);\r
+void SysTick_CounterCmd(u32 SysTick_Counter);\r
+void SysTick_ITConfig(FunctionalState NewState);\r
+u32 SysTick_GetCounter(void);\r
+FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG);\r
+\r
+#endif /* __STM32F10x_SYSTICK_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_tim.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the \r
+* TIM firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_TIM_H\r
+#define __STM32F10x_TIM_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* TIM Base Init structure definition */\r
+typedef struct\r
+{\r
+ u16 TIM_Period; /* Period value */\r
+ u16 TIM_Prescaler; /* Prescaler value */\r
+ u16 TIM_ClockDivision; /* Timer clock division */\r
+ u16 TIM_CounterMode; /* Timer Counter mode */\r
+} TIM_TimeBaseInitTypeDef;\r
+\r
+/* TIM Output Compare Init structure definition */\r
+typedef struct\r
+{\r
+ u16 TIM_OCMode; /* Timer Output Compare Mode */\r
+ u16 TIM_Channel; /* Timer Channel */\r
+ u16 TIM_Pulse; /* PWM or OC Channel pulse length */\r
+ u16 TIM_OCPolarity; /* PWM, OCM or OPM Channel polarity */\r
+} TIM_OCInitTypeDef;\r
+\r
+/* TIM Input Capture Init structure definition */\r
+typedef struct\r
+{\r
+ u16 TIM_ICMode; /* Timer Input Capture Mode */\r
+ u16 TIM_Channel; /* Timer Channel */\r
+ u16 TIM_ICPolarity; /* Input Capture polarity */ \r
+ u16 TIM_ICSelection; /* Input Capture selection */\r
+ u16 TIM_ICPrescaler; /* Input Capture prescaler */\r
+ u8 TIM_ICFilter; /* Input Capture filter */\r
+} TIM_ICInitTypeDef;\r
+\r
+/* Exported constants -------------------------------------------------------*/\r
+/* TIM Ouput Compare modes --------------------------------------------------*/\r
+#define TIM_OCMode_Timing ((u16)0x0000)\r
+#define TIM_OCMode_Active ((u16)0x0010)\r
+#define TIM_OCMode_Inactive ((u16)0x0020)\r
+#define TIM_OCMode_Toggle ((u16)0x0030)\r
+#define TIM_OCMode_PWM1 ((u16)0x0060)\r
+#define TIM_OCMode_PWM2 ((u16)0x0070)\r
+\r
+#define IS_TIM_OC_MODE(MODE) ((MODE == TIM_OCMode_Timing) || \\r
+ (MODE == TIM_OCMode_Active) || \\r
+ (MODE == TIM_OCMode_Inactive) || \\r
+ (MODE == TIM_OCMode_Toggle)|| \\r
+ (MODE == TIM_OCMode_PWM1) || \\r
+ (MODE == TIM_OCMode_PWM2))\r
+\r
+/* TIM Input Capture modes --------------------------------------------------*/\r
+#define TIM_ICMode_ICAP ((u16)0x0007)\r
+#define TIM_ICMode_PWMI ((u16)0x0006)\r
+\r
+#define IS_TIM_IC_MODE(MODE) ((MODE == TIM_ICMode_ICAP) || \\r
+ (MODE == TIM_ICMode_PWMI))\r
+\r
+/* TIM One Pulse Mode -------------------------------------------------------*/\r
+#define TIM_OPMode_Single ((u16)0x0008)\r
+#define TIM_OPMode_Repetitive ((u16)0x0000)\r
+\r
+#define IS_TIM_OPM_MODE(MODE) ((MODE == TIM_OPMode_Single) || \\r
+ (MODE == TIM_OPMode_Repetitive))\r
+ \r
+/* TIM Channel --------------------------------------------------------------*/\r
+#define TIM_Channel_1 ((u16)0x0000)\r
+#define TIM_Channel_2 ((u16)0x0001)\r
+#define TIM_Channel_3 ((u16)0x0002)\r
+#define TIM_Channel_4 ((u16)0x0003)\r
+\r
+#define IS_TIM_CHANNEL(CHANNEL) ((CHANNEL == TIM_Channel_1) || \\r
+ (CHANNEL == TIM_Channel_2) || \\r
+ (CHANNEL == TIM_Channel_3) || \\r
+ (CHANNEL == TIM_Channel_4))\r
+\r
+/* TIM Clock Division CKD ---------------------------------------------------*/\r
+#define TIM_CKD_DIV1 ((u16)0x0000)\r
+#define TIM_CKD_DIV2 ((u16)0x0100)\r
+#define TIM_CKD_DIV4 ((u16)0x0200)\r
+\r
+#define IS_TIM_CKD_DIV(DIV) ((DIV == TIM_CKD_DIV1) || \\r
+ (DIV == TIM_CKD_DIV2) || \\r
+ (DIV == TIM_CKD_DIV4))\r
+\r
+/* TIM Counter Mode ---------------------------------------------------------*/\r
+#define TIM_CounterMode_Up ((u16)0x0000)\r
+#define TIM_CounterMode_Down ((u16)0x0010)\r
+#define TIM_CounterMode_CenterAligned1 ((u16)0x0020)\r
+#define TIM_CounterMode_CenterAligned2 ((u16)0x0040)\r
+#define TIM_CounterMode_CenterAligned3 ((u16)0x0060)\r
+\r
+#define IS_TIM_COUNTER_MODE(MODE) ((MODE == TIM_CounterMode_Up) || \\r
+ (MODE == TIM_CounterMode_Down) || \\r
+ (MODE == TIM_CounterMode_CenterAligned1) || \\r
+ (MODE == TIM_CounterMode_CenterAligned2) || \\r
+ (MODE == TIM_CounterMode_CenterAligned3))\r
+\r
+/* TIM Output Compare Polarity ----------------------------------------------*/\r
+#define TIM_OCPolarity_High ((u16)0x0000)\r
+#define TIM_OCPolarity_Low ((u16)0x0002)\r
+\r
+#define IS_TIM_OC_POLARITY(POLARITY) ((POLARITY == TIM_OCPolarity_High) || \\r
+ (POLARITY == TIM_OCPolarity_Low))\r
+\r
+/* TIM Input Capture Polarity -----------------------------------------------*/\r
+#define TIM_ICPolarity_Rising ((u16)0x0000)\r
+#define TIM_ICPolarity_Falling ((u16)0x0002)\r
+\r
+#define IS_TIM_IC_POLARITY(POLARITY) ((POLARITY == TIM_ICPolarity_Rising) || \\r
+ (POLARITY == TIM_ICPolarity_Falling))\r
+\r
+/* TIM Input Capture Channel Selection -------------------------------------*/\r
+#define TIM_ICSelection_DirectTI ((u16)0x0001)\r
+#define TIM_ICSelection_IndirectTI ((u16)0x0002)\r
+#define TIM_ICSelection_TRGI ((u16)0x0003)\r
+\r
+#define IS_TIM_IC_SELECTION(SELECTION) ((SELECTION == TIM_ICSelection_DirectTI) || \\r
+ (SELECTION == TIM_ICSelection_IndirectTI) || \\r
+ (SELECTION == TIM_ICSelection_TRGI))\r
+\r
+/* TIM Input Capture Prescaler ----------------------------------------------*/\r
+#define TIM_ICPSC_DIV1 ((u16)0x0000)\r
+#define TIM_ICPSC_DIV2 ((u16)0x0004)\r
+#define TIM_ICPSC_DIV4 ((u16)0x0008)\r
+#define TIM_ICPSC_DIV8 ((u16)0x000C)\r
+\r
+#define IS_TIM_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM_ICPSC_DIV1) || \\r
+ (PRESCALER == TIM_ICPSC_DIV2) || \\r
+ (PRESCALER == TIM_ICPSC_DIV4) || \\r
+ (PRESCALER == TIM_ICPSC_DIV8))\r
+\r
+/* TIM Input Capture Filer Value ---------------------------------------------*/\r
+#define IS_TIM_IC_FILTER(ICFILTER) (ICFILTER <= 0xF) \r
+\r
+/* TIM interrupt sources ----------------------------------------------------*/\r
+#define TIM_IT_Update ((u16)0x0001)\r
+#define TIM_IT_CC1 ((u16)0x0002)\r
+#define TIM_IT_CC2 ((u16)0x0004)\r
+#define TIM_IT_CC3 ((u16)0x0008)\r
+#define TIM_IT_CC4 ((u16)0x0010)\r
+#define TIM_IT_Trigger ((u16)0x0040)\r
+\r
+#define IS_TIM_IT(IT) (((IT & (u16)0xFFA0) == 0x0000) && (IT != 0x0000))\r
+\r
+#define IS_TIM_GET_IT(IT) ((IT == TIM_IT_Update) || \\r
+ (IT == TIM_IT_CC1) || \\r
+ (IT == TIM_IT_CC2) || \\r
+ (IT == TIM_IT_CC3) || \\r
+ (IT == TIM_IT_CC4) || \\r
+ (IT == TIM_IT_Trigger))\r
+\r
+/* TIM DMA Base address -----------------------------------------------------*/\r
+#define TIM_DMABase_CR1 ((u16)0x0000)\r
+#define TIM_DMABase_CR2 ((u16)0x0001)\r
+#define TIM_DMABase_SMCR ((u16)0x0002)\r
+#define TIM_DMABase_DIER ((u16)0x0003)\r
+#define TIM_DMABase_SR ((u16)0x0004)\r
+#define TIM_DMABase_EGR ((u16)0x0005)\r
+#define TIM_DMABase_CCMR1 ((u16)0x0006)\r
+#define TIM_DMABase_CCMR2 ((u16)0x0007)\r
+#define TIM_DMABase_CCER ((u16)0x0008)\r
+#define TIM_DMABase_CNT ((u16)0x0009)\r
+#define TIM_DMABase_PSC ((u16)0x000A)\r
+#define TIM_DMABase_ARR ((u16)0x000B)\r
+#define TIM_DMABase_CCR1 ((u16)0x000D)\r
+#define TIM_DMABase_CCR2 ((u16)0x000E)\r
+#define TIM_DMABase_CCR3 ((u16)0x000F)\r
+#define TIM_DMABase_CCR4 ((u16)0x0010)\r
+#define TIM_DMABase_DCR ((u16)0x0012)\r
+\r
+#define IS_TIM_DMA_BASE(BASE) ((BASE == TIM_DMABase_CR1) || \\r
+ (BASE == TIM_DMABase_CR2) || \\r
+ (BASE == TIM_DMABase_SMCR) || \\r
+ (BASE == TIM_DMABase_DIER) || \\r
+ (BASE == TIM_DMABase_SR) || \\r
+ (BASE == TIM_DMABase_EGR) || \\r
+ (BASE == TIM_DMABase_CCMR1) || \\r
+ (BASE == TIM_DMABase_CCMR2) || \\r
+ (BASE == TIM_DMABase_CCER) || \\r
+ (BASE == TIM_DMABase_CNT) || \\r
+ (BASE == TIM_DMABase_PSC) || \\r
+ (BASE == TIM_DMABase_ARR) || \\r
+ (BASE == TIM_DMABase_CCR1) || \\r
+ (BASE == TIM_DMABase_CCR2) || \\r
+ (BASE == TIM_DMABase_CCR3) || \\r
+ (BASE == TIM_DMABase_CCR4) || \\r
+ (BASE == TIM_DMABase_DCR))\r
+\r
+/* TIM DMA Burst Length -----------------------------------------------------*/\r
+#define TIM_DMABurstLength_1Byte ((u16)0x0000)\r
+#define TIM_DMABurstLength_2Bytes ((u16)0x0100)\r
+#define TIM_DMABurstLength_3Bytes ((u16)0x0200)\r
+#define TIM_DMABurstLength_4Bytes ((u16)0x0300)\r
+#define TIM_DMABurstLength_5Bytes ((u16)0x0400)\r
+#define TIM_DMABurstLength_6Bytes ((u16)0x0500)\r
+#define TIM_DMABurstLength_7Bytes ((u16)0x0600)\r
+#define TIM_DMABurstLength_8Bytes ((u16)0x0700)\r
+#define TIM_DMABurstLength_9Bytes ((u16)0x0800)\r
+#define TIM_DMABurstLength_10Bytes ((u16)0x0900)\r
+#define TIM_DMABurstLength_11Bytes ((u16)0x0A00)\r
+#define TIM_DMABurstLength_12Bytes ((u16)0x0B00)\r
+#define TIM_DMABurstLength_13Bytes ((u16)0x0C00)\r
+#define TIM_DMABurstLength_14Bytes ((u16)0x0D00)\r
+#define TIM_DMABurstLength_15Bytes ((u16)0x0E00)\r
+#define TIM_DMABurstLength_16Bytes ((u16)0x0F00)\r
+#define TIM_DMABurstLength_17Bytes ((u16)0x1000)\r
+#define TIM_DMABurstLength_18Bytes ((u16)0x1100)\r
+\r
+#define IS_TIM_DMA_LENGTH(LENGTH) ((LENGTH == TIM_DMABurstLength_1Byte) || \\r
+ (LENGTH == TIM_DMABurstLength_2Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_3Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_4Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_5Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_6Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_7Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_8Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_9Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_10Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_11Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_12Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_13Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_14Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_15Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_16Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_17Bytes) || \\r
+ (LENGTH == TIM_DMABurstLength_18Bytes))\r
+ \r
+/* TIM DMA sources ----------------------------------------------------------*/\r
+#define TIM_DMA_Update ((u16)0x0100)\r
+#define TIM_DMA_CC1 ((u16)0x0200)\r
+#define TIM_DMA_CC2 ((u16)0x0400)\r
+#define TIM_DMA_CC3 ((u16)0x0800)\r
+#define TIM_DMA_CC4 ((u16)0x1000)\r
+#define TIM_DMA_Trigger ((u16)0x4000)\r
+\r
+#define IS_TIM_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0xA0FF) == 0x0000) && (SOURCE != 0x0000))\r
+\r
+/* TIM External Trigger Prescaler -------------------------------------------*/\r
+#define TIM_ExtTRGPSC_OFF ((u16)0x0000)\r
+#define TIM_ExtTRGPSC_DIV2 ((u16)0x1000) \r
+#define TIM_ExtTRGPSC_DIV4 ((u16)0x2000)\r
+#define TIM_ExtTRGPSC_DIV8 ((u16)0x3000)\r
+\r
+#define IS_TIM_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM_ExtTRGPSC_OFF) || \\r
+ (PRESCALER == TIM_ExtTRGPSC_DIV2) || \\r
+ (PRESCALER == TIM_ExtTRGPSC_DIV4) || \\r
+ (PRESCALER == TIM_ExtTRGPSC_DIV8))\r
+\r
+/* TIM Input Trigger Selection ---------------------------------------------*/\r
+#define TIM_TS_ITR0 ((u16)0x0000)\r
+#define TIM_TS_ITR1 ((u16)0x0010)\r
+#define TIM_TS_ITR2 ((u16)0x0020)\r
+#define TIM_TS_ITR3 ((u16)0x0030)\r
+#define TIM_TS_TI1F_ED ((u16)0x0040)\r
+#define TIM_TS_TI1FP1 ((u16)0x0050)\r
+#define TIM_TS_TI2FP2 ((u16)0x0060)\r
+#define TIM_TS_ETRF ((u16)0x0070)\r
+\r
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \\r
+ (SELECTION == TIM_TS_ITR1) || \\r
+ (SELECTION == TIM_TS_ITR2) || \\r
+ (SELECTION == TIM_TS_ITR3) || \\r
+ (SELECTION == TIM_TS_TI1F_ED) || \\r
+ (SELECTION == TIM_TS_TI1FP1) || \\r
+ (SELECTION == TIM_TS_TI2FP2) || \\r
+ (SELECTION == TIM_TS_ETRF))\r
+\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_ITR0) || \\r
+ (SELECTION == TIM_TS_ITR1) || \\r
+ (SELECTION == TIM_TS_ITR2) || \\r
+ (SELECTION == TIM_TS_ITR3))\r
+\r
+#define IS_TIM_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM_TS_TI1F_ED) || \\r
+ (SELECTION == TIM_TS_TI1FP1) || \\r
+ (SELECTION == TIM_TS_TI2FP2))\r
+\r
+/* TIM External Trigger Polarity --------------------------------------------*/\r
+#define TIM_ExtTRGPolarity_Inverted ((u16)0x8000)\r
+#define TIM_ExtTRGPolarity_NonInverted ((u16)0x0000)\r
+\r
+#define IS_TIM_EXT_POLARITY(POLARITY) ((POLARITY == TIM_ExtTRGPolarity_Inverted) || \\r
+ (POLARITY == TIM_ExtTRGPolarity_NonInverted)) \r
+\r
+/* TIM Prescaler Reload Mode ------------------------------------------------*/\r
+#define TIM_PSCReloadMode_Update ((u16)0x0000)\r
+#define TIM_PSCReloadMode_Immediate ((u16)0x0001)\r
+\r
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM_PSCReloadMode_Update) || \\r
+ (RELOAD == TIM_PSCReloadMode_Immediate))\r
+\r
+/* TIM Forced Action --------------------------------------------------------*/\r
+#define TIM_ForcedAction_Active ((u16)0x0050)\r
+#define TIM_ForcedAction_InActive ((u16)0x0040)\r
+\r
+#define IS_TIM_FORCED_ACTION(ACTION) ((ACTION == TIM_ForcedAction_Active) || \\r
+ (ACTION == TIM_ForcedAction_InActive))\r
+\r
+/* TIM Encoder Mode ---------------------------------------------------------*/ \r
+#define TIM_EncoderMode_TI1 ((u16)0x0001)\r
+#define TIM_EncoderMode_TI2 ((u16)0x0002)\r
+#define TIM_EncoderMode_TI12 ((u16)0x0003)\r
+\r
+#define IS_TIM_ENCODER_MODE(MODE) ((MODE == TIM_EncoderMode_TI1) || \\r
+ (MODE == TIM_EncoderMode_TI2) || \\r
+ (MODE == TIM_EncoderMode_TI12))\r
+\r
+/* TIM Event Source ---------------------------------------------------------*/\r
+#define TIM_EventSource_Update ((u16)0x0001)\r
+#define TIM_EventSource_CC1 ((u16)0x0002)\r
+#define TIM_EventSource_CC2 ((u16)0x0004)\r
+#define TIM_EventSource_CC3 ((u16)0x0008)\r
+#define TIM_EventSource_CC4 ((u16)0x0010)\r
+#define TIM_EventSource_Trigger ((u16)0x0040)\r
+\r
+#define IS_TIM_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFFA0) == 0x0000) && (SOURCE != 0x0000))\r
+ \r
+\r
+/* TIM Update Source --------------------------------------------------------*/\r
+#define TIM_UpdateSource_Global ((u16)0x0000)\r
+#define TIM_UpdateSource_Regular ((u16)0x0001)\r
+\r
+#define IS_TIM_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM_UpdateSource_Global) || \\r
+ (SOURCE == TIM_UpdateSource_Regular))\r
+\r
+/* TIM Ouput Compare Preload State ------------------------------------------*/\r
+#define TIM_OCPreload_Enable ((u16)0x0008)\r
+#define TIM_OCPreload_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_OCPRELOAD_STATE(STATE) ((STATE == TIM_OCPreload_Enable) || \\r
+ (STATE == TIM_OCPreload_Disable))\r
+\r
+/* TIM Ouput Compare Fast State ---------------------------------------------*/\r
+#define TIM_OCFast_Enable ((u16)0x0004)\r
+#define TIM_OCFast_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_OCFAST_STATE(STATE) ((STATE == TIM_OCFast_Enable) || \\r
+ (STATE == TIM_OCFast_Disable))\r
+\r
+/* TIM Trigger Output Source ------------------------------------------------*/ \r
+#define TIM_TRGOSource_Reset ((u16)0x0000)\r
+#define TIM_TRGOSource_Enable ((u16)0x0010)\r
+#define TIM_TRGOSource_Update ((u16)0x0020)\r
+#define TIM_TRGOSource_OC1 ((u16)0x0030)\r
+#define TIM_TRGOSource_OC1Ref ((u16)0x0040)\r
+#define TIM_TRGOSource_OC2Ref ((u16)0x0050)\r
+#define TIM_TRGOSource_OC3Ref ((u16)0x0060)\r
+#define TIM_TRGOSource_OC4Ref ((u16)0x0070)\r
+\r
+#define IS_TIM_TRGO_SOURCE(SOURCE) ((SOURCE == TIM_TRGOSource_Reset) || \\r
+ (SOURCE == TIM_TRGOSource_Enable) || \\r
+ (SOURCE == TIM_TRGOSource_Update) || \\r
+ (SOURCE == TIM_TRGOSource_OC1) || \\r
+ (SOURCE == TIM_TRGOSource_OC1Ref) || \\r
+ (SOURCE == TIM_TRGOSource_OC2Ref) || \\r
+ (SOURCE == TIM_TRGOSource_OC3Ref) || \\r
+ (SOURCE == TIM_TRGOSource_OC4Ref))\r
+\r
+/* TIM Slave Mode -----------------------------------------------------------*/\r
+#define TIM_SlaveMode_Reset ((u16)0x0004)\r
+#define TIM_SlaveMode_Gated ((u16)0x0005)\r
+#define TIM_SlaveMode_Trigger ((u16)0x0006)\r
+#define TIM_SlaveMode_External1 ((u16)0x0007)\r
+\r
+\r
+#define IS_TIM_SLAVE_MODE(MODE) ((MODE == TIM_SlaveMode_Reset) || \\r
+ (MODE == TIM_SlaveMode_Gated) || \\r
+ (MODE == TIM_SlaveMode_Trigger) || \\r
+ (MODE == TIM_SlaveMode_External1))\r
+\r
+/* TIM TIx External Clock Source --------------------------------------------*/\r
+#define TIM_TIxExternalCLK1Source_TI1 ((u16)0x0050)\r
+#define TIM_TIxExternalCLK1Source_TI2 ((u16)0x0060)\r
+#define TIM_TIxExternalCLK1Source_TI1ED ((u16)0x0040)\r
+\r
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM_TIxExternalCLK1Source_TI1) || \\r
+ (SOURCE == TIM_TIxExternalCLK1Source_TI2) || \\r
+ (SOURCE == TIM_TIxExternalCLK1Source_TI1ED))\r
+\r
+\r
+/* TIM Master Slave Mode ----------------------------------------------------*/\r
+#define TIM_MasterSlaveMode_Enable ((u16)0x0080)\r
+#define TIM_MasterSlaveMode_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM_MSM_STATE(STATE) ((STATE == TIM_MasterSlaveMode_Enable) || \\r
+ (STATE == TIM_MasterSlaveMode_Disable))\r
+\r
+/* TIM Flags ----------------------------------------------------------------*/\r
+#define TIM_FLAG_Update ((u16)0x0001)\r
+#define TIM_FLAG_CC1 ((u16)0x0002)\r
+#define TIM_FLAG_CC2 ((u16)0x0004)\r
+#define TIM_FLAG_CC3 ((u16)0x0008)\r
+#define TIM_FLAG_CC4 ((u16)0x0010)\r
+#define TIM_FLAG_Trigger ((u16)0x0040)\r
+#define TIM_FLAG_CC1OF ((u16)0x0200)\r
+#define TIM_FLAG_CC2OF ((u16)0x0400)\r
+#define TIM_FLAG_CC3OF ((u16)0x0800)\r
+#define TIM_FLAG_CC4OF ((u16)0x1000)\r
+\r
+#define IS_TIM_GET_FLAG(FLAG) ((FLAG == TIM_FLAG_Update) || \\r
+ (FLAG == TIM_FLAG_CC1) || \\r
+ (FLAG == TIM_FLAG_CC2) || \\r
+ (FLAG == TIM_FLAG_CC3) || \\r
+ (FLAG == TIM_FLAG_CC4) || \\r
+ (FLAG == TIM_FLAG_Trigger) || \\r
+ (FLAG == TIM_FLAG_CC1OF) || \\r
+ (FLAG == TIM_FLAG_CC2OF) || \\r
+ (FLAG == TIM_FLAG_CC3OF) || \\r
+ (FLAG == TIM_FLAG_CC4OF))\r
+\r
+#define IS_TIM_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE1A0) == 0x0000) && (FLAG != 0x0000)) \r
+ \r
+\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+void TIM_DeInit(TIM_TypeDef* TIMx);\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState);\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength);\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate);\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource, \r
+ u16 TIM_ICPolarity, u8 ICFilter);\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, \r
+ u8 ExtTRGFilter);\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, \r
+ u8 ExtTRGFilter);\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource);\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode);\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction);\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate);\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate);\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload);\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast);\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate);\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode, \r
+ u16 TIM_IC1Polarity, u16 TIM_IC2Polarity);\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource);\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity);\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity); \r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource);\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate);\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode);\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource);\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode);\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode);\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload);\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1);\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2);\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3);\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4);\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler);\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler);\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler);\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler);\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD);\r
+u16 TIM_GetCapture1(TIM_TypeDef* TIMx);\r
+u16 TIM_GetCapture2(TIM_TypeDef* TIMx);\r
+u16 TIM_GetCapture3(TIM_TypeDef* TIMx);\r
+u16 TIM_GetCapture4(TIM_TypeDef* TIMx);\r
+u16 TIM_GetCounter(TIM_TypeDef* TIMx);\r
+u16 TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG); \r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT);\r
+\r
+#endif /*__STM32F10x_TIM_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_tim1.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the \r
+* TIM1 firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* mm/dd/yyyy: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_TIM1_H\r
+#define __STM32F10x_TIM1_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* TIM1 Time Base Init structure definition */\r
+typedef struct\r
+{\r
+ u16 TIM1_Prescaler;\r
+ u16 TIM1_CounterMode;\r
+ u16 TIM1_Period;\r
+ u16 TIM1_ClockDivision;\r
+ u8 TIM1_RepetitionCounter;\r
+} TIM1_TimeBaseInitTypeDef;\r
+\r
+/* TIM1 Output Compare Init structure definition */\r
+typedef struct\r
+{\r
+ u16 TIM1_OCMode;\r
+ u16 TIM1_OutputState;\r
+ u16 TIM1_OutputNState;\r
+ u16 TIM1_Pulse;\r
+ u16 TIM1_OCPolarity;\r
+ u16 TIM1_OCNPolarity;\r
+ u16 TIM1_OCIdleState;\r
+ u16 TIM1_OCNIdleState;\r
+} TIM1_OCInitTypeDef;\r
+\r
+/* TIM1 Input Capture Init structure definition */\r
+typedef struct\r
+{\r
+ u16 TIM1_Channel;\r
+ u16 TIM1_ICPolarity;\r
+ u16 TIM1_ICSelection;\r
+ u16 TIM1_ICPrescaler;\r
+ u8 TIM1_ICFilter;\r
+} TIM1_ICInitTypeDef;\r
+\r
+/* BDTR structure definition */\r
+typedef struct\r
+{\r
+ u16 TIM1_OSSRState;\r
+ u16 TIM1_OSSIState;\r
+ u16 TIM1_LOCKLevel; \r
+ u16 TIM1_DeadTime;\r
+ u16 TIM1_Break;\r
+ u16 TIM1_BreakPolarity;\r
+ u16 TIM1_AutomaticOutput;\r
+} TIM1_BDTRInitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* TIM1 Output Compare and PWM modes ----------------------------------------*/\r
+#define TIM1_OCMode_Timing ((u16)0x0000)\r
+#define TIM1_OCMode_Active ((u16)0x0010)\r
+#define TIM1_OCMode_Inactive ((u16)0x0020)\r
+#define TIM1_OCMode_Toggle ((u16)0x0030)\r
+#define TIM1_OCMode_PWM1 ((u16)0x0060)\r
+#define TIM1_OCMode_PWM2 ((u16)0x0070)\r
+\r
+#define IS_TIM1_OC_MODE(MODE) ((MODE == TIM1_OCMode_Timing) || \\r
+ (MODE == TIM1_OCMode_Active) || \\r
+ (MODE == TIM1_OCMode_Inactive) || \\r
+ (MODE == TIM1_OCMode_Toggle)|| \\r
+ (MODE == TIM1_OCMode_PWM1) || \\r
+ (MODE == TIM1_OCMode_PWM2))\r
+\r
+#define IS_TIM1_OCM(MODE)((MODE == TIM1_OCMode_Timing) || \\r
+ (MODE == TIM1_OCMode_Active) || \\r
+ (MODE == TIM1_OCMode_Inactive) || \\r
+ (MODE == TIM1_OCMode_Toggle)|| \\r
+ (MODE == TIM1_OCMode_PWM1) || \\r
+ (MODE == TIM1_OCMode_PWM2) || \\r
+ (MODE == TIM1_ForcedAction_Active) || \\r
+ (MODE == TIM1_ForcedAction_InActive))\r
+/* TIM1 One Pulse Mode ------------------------------------------------------*/\r
+#define TIM1_OPMode_Single ((u16)0x0001)\r
+#define TIM1_OPMode_Repetitive ((u16)0x0000)\r
+\r
+#define IS_TIM1_OPM_MODE(MODE) ((MODE == TIM1_OPMode_Single) || \\r
+ (MODE == TIM1_OPMode_Repetitive))\r
+\r
+/* TIM1 Channel -------------------------------------------------------------*/\r
+#define TIM1_Channel_1 ((u16)0x0000)\r
+#define TIM1_Channel_2 ((u16)0x0001)\r
+#define TIM1_Channel_3 ((u16)0x0002)\r
+#define TIM1_Channel_4 ((u16)0x0003)\r
+\r
+#define IS_TIM1_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \\r
+ (CHANNEL == TIM1_Channel_2) || \\r
+ (CHANNEL == TIM1_Channel_3) || \\r
+ (CHANNEL == TIM1_Channel_4))\r
+\r
+#define IS_TIM1_PWMI_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \\r
+ (CHANNEL == TIM1_Channel_2))\r
+\r
+#define IS_TIM1_COMPLEMENTARY_CHANNEL(CHANNEL) ((CHANNEL == TIM1_Channel_1) || \\r
+ (CHANNEL == TIM1_Channel_2) || \\r
+ (CHANNEL == TIM1_Channel_3))\r
+/* TIM1 Clock Division CKD --------------------------------------------------*/\r
+#define TIM1_CKD_DIV1 ((u16)0x0000)\r
+#define TIM1_CKD_DIV2 ((u16)0x0100)\r
+#define TIM1_CKD_DIV4 ((u16)0x0200)\r
+\r
+#define IS_TIM1_CKD_DIV(DIV) ((DIV == TIM1_CKD_DIV1) || \\r
+ (DIV == TIM1_CKD_DIV2) || \\r
+ (DIV == TIM1_CKD_DIV4))\r
+\r
+/* TIM1 Counter Mode --------------------------------------------------------*/\r
+#define TIM1_CounterMode_Up ((u16)0x0000)\r
+#define TIM1_CounterMode_Down ((u16)0x0010)\r
+#define TIM1_CounterMode_CenterAligned1 ((u16)0x0020)\r
+#define TIM1_CounterMode_CenterAligned2 ((u16)0x0040)\r
+#define TIM1_CounterMode_CenterAligned3 ((u16)0x0060)\r
+\r
+#define IS_TIM1_COUNTER_MODE(MODE) ((MODE == TIM1_CounterMode_Up) || \\r
+ (MODE == TIM1_CounterMode_Down) || \\r
+ (MODE == TIM1_CounterMode_CenterAligned1) || \\r
+ (MODE == TIM1_CounterMode_CenterAligned2) || \\r
+ (MODE == TIM1_CounterMode_CenterAligned3))\r
+\r
+/* TIM1 Output Compare Polarity ---------------------------------------------*/\r
+#define TIM1_OCPolarity_High ((u16)0x0000)\r
+#define TIM1_OCPolarity_Low ((u16)0x0001)\r
+\r
+#define IS_TIM1_OC_POLARITY(POLARITY) ((POLARITY == TIM1_OCPolarity_High) || \\r
+ (POLARITY == TIM1_OCPolarity_Low))\r
+\r
+/* TIM1 Output Compare N Polarity -------------------------------------------*/\r
+#define TIM1_OCNPolarity_High ((u16)0x0000)\r
+#define TIM1_OCNPolarity_Low ((u16)0x0001)\r
+\r
+#define IS_TIM1_OCN_POLARITY(POLARITY) ((POLARITY == TIM1_OCNPolarity_High) || \\r
+ (POLARITY == TIM1_OCNPolarity_Low))\r
+\r
+/* TIM1 Output Compare states -----------------------------------------------*/\r
+#define TIM1_OutputState_Disable ((u16)0x0000)\r
+#define TIM1_OutputState_Enable ((u16)0x0001)\r
+\r
+#define IS_TIM1_OUTPUT_STATE(STATE) ((STATE == TIM1_OutputState_Disable) || \\r
+ (STATE == TIM1_OutputState_Enable))\r
+\r
+/* TIM1 Output Compare N States ---------------------------------------------*/\r
+#define TIM1_OutputNState_Disable ((u16)0x0000)\r
+#define TIM1_OutputNState_Enable ((u16)0x0001)\r
+\r
+#define IS_TIM1_OUTPUTN_STATE(STATE) ((STATE == TIM1_OutputNState_Disable) || \\r
+ (STATE == TIM1_OutputNState_Enable))\r
+\r
+/* Break Input enable/disable -----------------------------------------------*/\r
+#define TIM1_Break_Enable ((u16)0x1000)\r
+#define TIM1_Break_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM1_BREAK_STATE(STATE) ((STATE == TIM1_Break_Enable) || \\r
+ (STATE == TIM1_Break_Disable))\r
+\r
+/* Break Polarity -----------------------------------------------------------*/\r
+#define TIM1_BreakPolarity_Low ((u16)0x0000)\r
+#define TIM1_BreakPolarity_High ((u16)0x2000)\r
+\r
+#define IS_TIM1_BREAK_POLARITY(POLARITY) ((POLARITY == TIM1_BreakPolarity_Low) || \\r
+ (POLARITY == TIM1_BreakPolarity_High))\r
+\r
+/* TIM1 AOE Bit Set/Reset ---------------------------------------------------*/\r
+#define TIM1_AutomaticOutput_Enable ((u16)0x4000)\r
+#define TIM1_AutomaticOutput_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM1_AUTOMATIC_OUTPUT_STATE(STATE) ((STATE == TIM1_AutomaticOutput_Enable) || \\r
+ (STATE == TIM1_AutomaticOutput_Disable))\r
+/* Lock levels --------------------------------------------------------------*/\r
+#define TIM1_LOCKLevel_OFF ((u16)0x0000)\r
+#define TIM1_LOCKLevel_1 ((u16)0x0100)\r
+#define TIM1_LOCKLevel_2 ((u16)0x0200)\r
+#define TIM1_LOCKLevel_3 ((u16)0x0300)\r
+\r
+#define IS_TIM1_LOCK_LEVEL(LEVEL) ((LEVEL == TIM1_LOCKLevel_OFF) || \\r
+ (LEVEL == TIM1_LOCKLevel_1) || \\r
+ (LEVEL == TIM1_LOCKLevel_2) || \\r
+ (LEVEL == TIM1_LOCKLevel_3))\r
+\r
+/* OSSI: Off-State Selection for Idle mode states ---------------------------*/\r
+#define TIM1_OSSIState_Enable ((u16)0x0400)\r
+#define TIM1_OSSIState_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM1_OSSI_STATE(STATE) ((STATE == TIM1_OSSIState_Enable) || \\r
+ (STATE == TIM1_OSSIState_Disable))\r
+\r
+/* OSSR: Off-State Selection for Run mode states ----------------------------*/\r
+#define TIM1_OSSRState_Enable ((u16)0x0800)\r
+#define TIM1_OSSRState_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM1_OSSR_STATE(STATE) ((STATE == TIM1_OSSRState_Enable) || \\r
+ (STATE == TIM1_OSSRState_Disable))\r
+\r
+/* TIM1 Output Compare Idle State -------------------------------------------*/\r
+#define TIM1_OCIdleState_Set ((u16)0x0001)\r
+#define TIM1_OCIdleState_Reset ((u16)0x0000)\r
+\r
+#define IS_TIM1_OCIDLE_STATE(STATE) ((STATE == TIM1_OCIdleState_Set) || \\r
+ (STATE == TIM1_OCIdleState_Reset))\r
+\r
+/* TIM1 Output Compare N Idle State -----------------------------------------*/\r
+#define TIM1_OCNIdleState_Set ((u16)0x0001)\r
+#define TIM1_OCNIdleState_Reset ((u16)0x0000)\r
+\r
+#define IS_TIM1_OCNIDLE_STATE(STATE) ((STATE == TIM1_OCNIdleState_Set) || \\r
+ (STATE == TIM1_OCNIdleState_Reset))\r
+\r
+/* TIM1 Input Capture Polarity ----------------------------------------------*/\r
+#define TIM1_ICPolarity_Rising ((u16)0x0000)\r
+#define TIM1_ICPolarity_Falling ((u16)0x0001)\r
+\r
+#define IS_TIM1_IC_POLARITY(POLARITY) ((POLARITY == TIM1_ICPolarity_Rising) || \\r
+ (POLARITY == TIM1_ICPolarity_Falling))\r
+\r
+/* TIM1 Input Capture Selection ---------------------------------------------*/\r
+#define TIM1_ICSelection_DirectTI ((u16)0x0001)\r
+#define TIM1_ICSelection_IndirectTI ((u16)0x0002)\r
+#define TIM1_ICSelection_TRGI ((u16)0x0003)\r
+\r
+#define IS_TIM1_IC_SELECTION(SELECTION) ((SELECTION == TIM1_ICSelection_DirectTI) || \\r
+ (SELECTION == TIM1_ICSelection_IndirectTI) || \\r
+ (SELECTION == TIM1_ICSelection_TRGI))\r
+\r
+/* TIM1 Input Capture Prescaler ---------------------------------------------*/\r
+#define TIM1_ICPSC_DIV1 ((u16)0x0000)\r
+#define TIM1_ICPSC_DIV2 ((u16)0x0004)\r
+#define TIM1_ICPSC_DIV4 ((u16)0x0008)\r
+#define TIM1_ICPSC_DIV8 ((u16)0x000C)\r
+\r
+#define IS_TIM1_IC_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ICPSC_DIV1) || \\r
+ (PRESCALER == TIM1_ICPSC_DIV2) || \\r
+ (PRESCALER == TIM1_ICPSC_DIV4) || \\r
+ (PRESCALER == TIM1_ICPSC_DIV8))\r
+ \r
+/* TIM1 Input Capture Filer Value ---------------------------------------------*/\r
+#define IS_TIM1_IC_FILTER(ICFILTER) (ICFILTER <= 0xF) \r
+\r
+/* TIM1 interrupt sources ---------------------------------------------------*/\r
+#define TIM1_IT_Update ((u16)0x0001)\r
+#define TIM1_IT_CC1 ((u16)0x0002)\r
+#define TIM1_IT_CC2 ((u16)0x0004)\r
+#define TIM1_IT_CC3 ((u16)0x0008)\r
+#define TIM1_IT_CC4 ((u16)0x0010)\r
+#define TIM1_IT_COM ((u16)0x0020)\r
+#define TIM1_IT_Trigger ((u16)0x0040)\r
+#define TIM1_IT_Break ((u16)0x0080)\r
+\r
+#define IS_TIM1_IT(IT) (((IT & (u16)0xFF00) == 0x0000) && (IT != 0x0000))\r
+\r
+#define IS_TIM1_GET_IT(IT) ((IT == TIM1_IT_Update) || \\r
+ (IT == TIM1_IT_CC1) || \\r
+ (IT == TIM1_IT_CC2) || \\r
+ (IT == TIM1_IT_CC3) || \\r
+ (IT == TIM1_IT_CC4) || \\r
+ (IT == TIM1_IT_COM) || \\r
+ (IT == TIM1_IT_Trigger) || \\r
+ (IT == TIM1_IT_Break))\r
+\r
+/* TIM1 DMA Base address ----------------------------------------------------*/\r
+#define TIM1_DMABase_CR1 ((u16)0x0000)\r
+#define TIM1_DMABase_CR2 ((u16)0x0001)\r
+#define TIM1_DMABase_SMCR ((u16)0x0002)\r
+#define TIM1_DMABase_DIER ((u16)0x0003)\r
+#define TIM1_DMABase_SR ((u16)0x0004)\r
+#define TIM1_DMABase_EGR ((u16)0x0005)\r
+#define TIM1_DMABase_CCMR1 ((u16)0x0006)\r
+#define TIM1_DMABase_CCMR2 ((u16)0x0007)\r
+#define TIM1_DMABase_CCER ((u16)0x0008)\r
+#define TIM1_DMABase_CNT ((u16)0x0009)\r
+#define TIM1_DMABase_PSC ((u16)0x000A)\r
+#define TIM1_DMABase_ARR ((u16)0x000B)\r
+#define TIM1_DMABase_RCR ((u16)0x000C)\r
+#define TIM1_DMABase_CCR1 ((u16)0x000D)\r
+#define TIM1_DMABase_CCR2 ((u16)0x000E)\r
+#define TIM1_DMABase_CCR3 ((u16)0x000F)\r
+#define TIM1_DMABase_CCR4 ((u16)0x0010)\r
+#define TIM1_DMABase_BDTR ((u16)0x0011)\r
+#define TIM1_DMABase_DCR ((u16)0x0012)\r
+\r
+#define IS_TIM1_DMA_BASE(BASE) ((BASE == TIM1_DMABase_CR1) || \\r
+ (BASE == TIM1_DMABase_CR2) || \\r
+ (BASE == TIM1_DMABase_SMCR) || \\r
+ (BASE == TIM1_DMABase_DIER) || \\r
+ (BASE == TIM1_DMABase_SR) || \\r
+ (BASE == TIM1_DMABase_EGR) || \\r
+ (BASE == TIM1_DMABase_CCMR1) || \\r
+ (BASE == TIM1_DMABase_CCMR2) || \\r
+ (BASE == TIM1_DMABase_CCER) || \\r
+ (BASE == TIM1_DMABase_CNT) || \\r
+ (BASE == TIM1_DMABase_PSC) || \\r
+ (BASE == TIM1_DMABase_ARR) || \\r
+ (BASE == TIM1_DMABase_RCR) || \\r
+ (BASE == TIM1_DMABase_CCR1) || \\r
+ (BASE == TIM1_DMABase_CCR2) || \\r
+ (BASE == TIM1_DMABase_CCR3) || \\r
+ (BASE == TIM1_DMABase_CCR4) || \\r
+ (BASE == TIM1_DMABase_BDTR) || \\r
+ (BASE == TIM1_DMABase_DCR))\r
+\r
+/* TIM1 DMA Burst Length ----------------------------------------------------*/\r
+#define TIM1_DMABurstLength_1Byte ((u16)0x0000)\r
+#define TIM1_DMABurstLength_2Bytes ((u16)0x0100)\r
+#define TIM1_DMABurstLength_3Bytes ((u16)0x0200)\r
+#define TIM1_DMABurstLength_4Bytes ((u16)0x0300)\r
+#define TIM1_DMABurstLength_5Bytes ((u16)0x0400)\r
+#define TIM1_DMABurstLength_6Bytes ((u16)0x0500)\r
+#define TIM1_DMABurstLength_7Bytes ((u16)0x0600)\r
+#define TIM1_DMABurstLength_8Bytes ((u16)0x0700)\r
+#define TIM1_DMABurstLength_9Bytes ((u16)0x0800)\r
+#define TIM1_DMABurstLength_10Bytes ((u16)0x0900)\r
+#define TIM1_DMABurstLength_11Bytes ((u16)0x0A00)\r
+#define TIM1_DMABurstLength_12Bytes ((u16)0x0B00)\r
+#define TIM1_DMABurstLength_13Bytes ((u16)0x0C00)\r
+#define TIM1_DMABurstLength_14Bytes ((u16)0x0D00)\r
+#define TIM1_DMABurstLength_15Bytes ((u16)0x0E00)\r
+#define TIM1_DMABurstLength_16Bytes ((u16)0x0F00)\r
+#define TIM1_DMABurstLength_17Bytes ((u16)0x1000)\r
+#define TIM1_DMABurstLength_18Bytes ((u16)0x1100)\r
+\r
+#define IS_TIM1_DMA_LENGTH(LENGTH) ((LENGTH == TIM1_DMABurstLength_1Byte) || \\r
+ (LENGTH == TIM1_DMABurstLength_2Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_3Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_4Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_5Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_6Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_7Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_8Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_9Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_10Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_11Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_12Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_13Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_14Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_15Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_16Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_17Bytes) || \\r
+ (LENGTH == TIM1_DMABurstLength_18Bytes))\r
+\r
+/* TIM1 DMA sources ---------------------------------------------------------*/\r
+#define TIM1_DMA_Update ((u16)0x0100)\r
+#define TIM1_DMA_CC1 ((u16)0x0200)\r
+#define TIM1_DMA_CC2 ((u16)0x0400)\r
+#define TIM1_DMA_CC3 ((u16)0x0800)\r
+#define TIM1_DMA_CC4 ((u16)0x1000)\r
+#define TIM1_DMA_COM ((u16)0x2000)\r
+#define TIM1_DMA_Trigger ((u16)0x4000)\r
+\r
+#define IS_TIM1_DMA_SOURCE(SOURCE) (((SOURCE & (u16)0x80FF) == 0x0000) && (SOURCE != 0x0000))\r
+\r
+/* TIM1 External Trigger Prescaler ------------------------------------------*/\r
+#define TIM1_ExtTRGPSC_OFF ((u16)0x0000)\r
+#define TIM1_ExtTRGPSC_DIV2 ((u16)0x1000)\r
+#define TIM1_ExtTRGPSC_DIV4 ((u16)0x2000)\r
+#define TIM1_ExtTRGPSC_DIV8 ((u16)0x3000)\r
+\r
+#define IS_TIM1_EXT_PRESCALER(PRESCALER) ((PRESCALER == TIM1_ExtTRGPSC_OFF) || \\r
+ (PRESCALER == TIM1_ExtTRGPSC_DIV2) || \\r
+ (PRESCALER == TIM1_ExtTRGPSC_DIV4) || \\r
+ (PRESCALER == TIM1_ExtTRGPSC_DIV8))\r
+\r
+/* TIM1 Internal Trigger Selection ------------------------------------------*/\r
+#define TIM1_TS_ITR0 ((u16)0x0000)\r
+#define TIM1_TS_ITR1 ((u16)0x0010)\r
+#define TIM1_TS_ITR2 ((u16)0x0020)\r
+#define TIM1_TS_ITR3 ((u16)0x0030)\r
+#define TIM1_TS_TI1F_ED ((u16)0x0040)\r
+#define TIM1_TS_TI1FP1 ((u16)0x0050)\r
+#define TIM1_TS_TI2FP2 ((u16)0x0060)\r
+#define TIM1_TS_ETRF ((u16)0x0070)\r
+\r
+#define IS_TIM1_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \\r
+ (SELECTION == TIM1_TS_ITR1) || \\r
+ (SELECTION == TIM1_TS_ITR2) || \\r
+ (SELECTION == TIM1_TS_ITR3) || \\r
+ (SELECTION == TIM1_TS_TI1F_ED) || \\r
+ (SELECTION == TIM1_TS_TI1FP1) || \\r
+ (SELECTION == TIM1_TS_TI2FP2) || \\r
+ (SELECTION == TIM1_TS_ETRF))\r
+\r
+#define IS_TIM1_INTERNAL_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_ITR0) || \\r
+ (SELECTION == TIM1_TS_ITR1) || \\r
+ (SELECTION == TIM1_TS_ITR2) || \\r
+ (SELECTION == TIM1_TS_ITR3))\r
+\r
+#define IS_TIM1_TIX_TRIGGER_SELECTION(SELECTION) ((SELECTION == TIM1_TS_TI1F_ED) || \\r
+ (SELECTION == TIM1_TS_TI1FP1) || \\r
+ (SELECTION == TIM1_TS_TI2FP2))\r
+\r
+/* TIM1 External Trigger Polarity -------------------------------------------*/\r
+#define TIM1_ExtTRGPolarity_Inverted ((u16)0x8000)\r
+#define TIM1_ExtTRGPolarity_NonInverted ((u16)0x0000)\r
+\r
+#define IS_TIM1_EXT_POLARITY(POLARITY) ((POLARITY == TIM1_ExtTRGPolarity_Inverted) || \\r
+ (POLARITY == TIM1_ExtTRGPolarity_NonInverted))\r
+\r
+/* TIM1 Prescaler Reload Mode -----------------------------------------------*/\r
+#define TIM1_PSCReloadMode_Update ((u16)0x0000)\r
+#define TIM1_PSCReloadMode_Immediate ((u16)0x0001)\r
+\r
+#define IS_TIM1_PRESCALER_RELOAD(RELOAD) ((RELOAD == TIM1_PSCReloadMode_Update) || \\r
+ (RELOAD == TIM1_PSCReloadMode_Immediate))\r
+\r
+/* TIM1 Forced Action -------------------------------------------------------*/\r
+#define TIM1_ForcedAction_Active ((u16)0x0050)\r
+#define TIM1_ForcedAction_InActive ((u16)0x0040)\r
+\r
+#define IS_TIM1_FORCED_ACTION(ACTION) ((ACTION == TIM1_ForcedAction_Active) || \\r
+ (ACTION == TIM1_ForcedAction_InActive))\r
+\r
+/* TIM1 Encoder Mode --------------------------------------------------------*/ \r
+#define TIM1_EncoderMode_TI1 ((u16)0x0001)\r
+#define TIM1_EncoderMode_TI2 ((u16)0x0002)\r
+#define TIM1_EncoderMode_TI12 ((u16)0x0003)\r
+\r
+#define IS_TIM1_ENCODER_MODE(MODE) ((MODE == TIM1_EncoderMode_TI1) || \\r
+ (MODE == TIM1_EncoderMode_TI2) || \\r
+ (MODE == TIM1_EncoderMode_TI12))\r
+\r
+/* TIM1 Event Source --------------------------------------------------------*/\r
+#define TIM1_EventSource_Update ((u16)0x0001)\r
+#define TIM1_EventSource_CC1 ((u16)0x0002)\r
+#define TIM1_EventSource_CC2 ((u16)0x0004)\r
+#define TIM1_EventSource_CC3 ((u16)0x0008)\r
+#define TIM1_EventSource_CC4 ((u16)0x0010)\r
+#define TIM1_EventSource_COM ((u16)0x0020)\r
+#define TIM1_EventSource_Trigger ((u16)0x0040)\r
+#define TIM1_EventSource_Break ((u16)0x0080)\r
+\r
+#define IS_TIM1_EVENT_SOURCE(SOURCE) (((SOURCE & (u16)0xFF00) == 0x0000) && (SOURCE != 0x0000))\r
+ \r
+\r
+/* TIM1 Update Source -------------------------------------------------------*/\r
+#define TIM1_UpdateSource_Global ((u16)0x0000)\r
+#define TIM1_UpdateSource_Regular ((u16)0x0001)\r
+\r
+#define IS_TIM1_UPDATE_SOURCE(SOURCE) ((SOURCE == TIM1_UpdateSource_Global) || \\r
+ (SOURCE == TIM1_UpdateSource_Regular))\r
+\r
+/* TIM1 Ouput Compare Preload State ------------------------------------------*/\r
+#define TIM1_OCPreload_Enable ((u16)0x0001)\r
+#define TIM1_OCPreload_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM1_OCPRELOAD_STATE(STATE) ((STATE == TIM1_OCPreload_Enable) || \\r
+ (STATE == TIM1_OCPreload_Disable))\r
+\r
+/* TIM1 Ouput Compare Fast State ---------------------------------------------*/\r
+#define TIM1_OCFast_Enable ((u16)0x0001)\r
+#define TIM1_OCFast_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM1_OCFAST_STATE(STATE) ((STATE == TIM1_OCFast_Enable) || \\r
+ (STATE == TIM1_OCFast_Disable))\r
+\r
+/* TIM1 Trigger Output Source -----------------------------------------------*/ \r
+#define TIM1_TRGOSource_Reset ((u16)0x0000)\r
+#define TIM1_TRGOSource_Enable ((u16)0x0010)\r
+#define TIM1_TRGOSource_Update ((u16)0x0020)\r
+#define TIM1_TRGOSource_OC1 ((u16)0x0030)\r
+#define TIM1_TRGOSource_OC1Ref ((u16)0x0040)\r
+#define TIM1_TRGOSource_OC2Ref ((u16)0x0050)\r
+#define TIM1_TRGOSource_OC3Ref ((u16)0x0060)\r
+#define TIM1_TRGOSource_OC4Ref ((u16)0x0070)\r
+\r
+#define IS_TIM1_TRGO_SOURCE(SOURCE) ((SOURCE == TIM1_TRGOSource_Reset) || \\r
+ (SOURCE == TIM1_TRGOSource_Enable) || \\r
+ (SOURCE == TIM1_TRGOSource_Update) || \\r
+ (SOURCE == TIM1_TRGOSource_OC1) || \\r
+ (SOURCE == TIM1_TRGOSource_OC1Ref) || \\r
+ (SOURCE == TIM1_TRGOSource_OC2Ref) || \\r
+ (SOURCE == TIM1_TRGOSource_OC3Ref) || \\r
+ (SOURCE == TIM1_TRGOSource_OC4Ref))\r
+\r
+/* TIM1 Slave Mode ----------------------------------------------------------*/\r
+#define TIM1_SlaveMode_Reset ((u16)0x0004)\r
+#define TIM1_SlaveMode_Gated ((u16)0x0005)\r
+#define TIM1_SlaveMode_Trigger ((u16)0x0006)\r
+#define TIM1_SlaveMode_External1 ((u16)0x0007)\r
+\r
+#define IS_TIM1_SLAVE_MODE(MODE) ((MODE == TIM1_SlaveMode_Reset) || \\r
+ (MODE == TIM1_SlaveMode_Gated) || \\r
+ (MODE == TIM1_SlaveMode_Trigger) || \\r
+ (MODE == TIM1_SlaveMode_External1))\r
+\r
+/* TIM1 TIx External Clock Source -------------------------------------------*/\r
+#define TIM1_TIxExternalCLK1Source_TI1 ((u16)0x0050)\r
+#define TIM1_TIxExternalCLK1Source_TI2 ((u16)0x0060)\r
+#define TIM1_TIxExternalCLK1Source_TI1ED ((u16)0x0040)\r
+\r
+#define IS_TIM1_TIXCLK_SOURCE(SOURCE) ((SOURCE == TIM1_TIxExternalCLK1Source_TI1) || \\r
+ (SOURCE == TIM1_TIxExternalCLK1Source_TI2) || \\r
+ (SOURCE == TIM1_TIxExternalCLK1Source_TI1ED))\r
+\r
+/* TIM1 Master Slave Mode ---------------------------------------------------*/\r
+#define TIM1_MasterSlaveMode_Enable ((u16)0x0001)\r
+#define TIM1_MasterSlaveMode_Disable ((u16)0x0000)\r
+\r
+#define IS_TIM1_MSM_STATE(STATE) ((STATE == TIM1_MasterSlaveMode_Enable) || \\r
+ (STATE == TIM1_MasterSlaveMode_Disable))\r
+\r
+/* TIM1 Flags ---------------------------------------------------------------*/\r
+#define TIM1_FLAG_Update ((u16)0x0001)\r
+#define TIM1_FLAG_CC1 ((u16)0x0002)\r
+#define TIM1_FLAG_CC2 ((u16)0x0004)\r
+#define TIM1_FLAG_CC3 ((u16)0x0008)\r
+#define TIM1_FLAG_CC4 ((u16)0x0010)\r
+#define TIM1_FLAG_COM ((u16)0x0020)\r
+#define TIM1_FLAG_Trigger ((u16)0x0040)\r
+#define TIM1_FLAG_Break ((u16)0x0080)\r
+#define TIM1_FLAG_CC1OF ((u16)0x0200)\r
+#define TIM1_FLAG_CC2OF ((u16)0x0400)\r
+#define TIM1_FLAG_CC3OF ((u16)0x0800)\r
+#define TIM1_FLAG_CC4OF ((u16)0x1000)\r
+\r
+#define IS_TIM1_GET_FLAG(FLAG) ((FLAG == TIM1_FLAG_Update) || \\r
+ (FLAG == TIM1_FLAG_CC1) || \\r
+ (FLAG == TIM1_FLAG_CC2) || \\r
+ (FLAG == TIM1_FLAG_CC3) || \\r
+ (FLAG == TIM1_FLAG_CC4) || \\r
+ (FLAG == TIM1_FLAG_COM) || \\r
+ (FLAG == TIM1_FLAG_Trigger) || \\r
+ (FLAG == TIM1_FLAG_Break) || \\r
+ (FLAG == TIM1_FLAG_CC1OF) || \\r
+ (FLAG == TIM1_FLAG_CC2OF) || \\r
+ (FLAG == TIM1_FLAG_CC3OF) || \\r
+ (FLAG == TIM1_FLAG_CC4OF))\r
+\r
+#define IS_TIM1_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xE100) == 0x0000) && (FLAG != 0x0000))\r
+ \r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+void TIM1_DeInit(void);\r
+void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);\r
+void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);\r
+void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);\r
+void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);\r
+void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct);\r
+void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct);\r
+void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);\r
+void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct);\r
+void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct);\r
+void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct);\r
+void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct);\r
+void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct);\r
+void TIM1_Cmd(FunctionalState NewState);\r
+void TIM1_CtrlPWMOutputs(FunctionalState Newstate);\r
+void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState);\r
+void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength);\r
+void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate);\r
+void TIM1_InternalClockConfig(void);\r
+void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, \r
+ u16 ExtTRGFilter);\r
+void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity, \r
+ u16 ExtTRGFilter);\r
+void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource);\r
+void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource, u16 TIM1_ICPolarity, \r
+ u8 ICFilter);\r
+void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource);\r
+void TIM1_UpdateDisableConfig(FunctionalState Newstate);\r
+void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource);\r
+void TIM1_SelectHallSensor(FunctionalState Newstate);\r
+void TIM1_SelectOnePulseMode(u16 TIM1_OPMode);\r
+void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource);\r
+void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode);\r
+void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode);\r
+void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity, \r
+ u16 TIM1_IC2Polarity);\r
+void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode);\r
+void TIM1_CounterModeConfig(u16 TIM1_CounterMode);\r
+void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction);\r
+void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction);\r
+void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction);\r
+void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction);\r
+void TIM1_ARRPreloadConfig(FunctionalState Newstate);\r
+void TIM1_SelectCOM(FunctionalState Newstate);\r
+void TIM1_SelectCCDMA(FunctionalState Newstate);\r
+void TIM1_CCPreloadControl(FunctionalState Newstate);\r
+void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload);\r
+void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload);\r
+void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload);\r
+void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload);\r
+void TIM1_OC1FastConfig(u16 TIM1_OCFast);\r
+void TIM1_OC2FastConfig(u16 TIM1_OCFast);\r
+void TIM1_OC3FastConfig(u16 TIM1_OCFast);\r
+void TIM1_OC4FastConfig(u16 TIM1_OCFast);\r
+void TIM1_GenerateEvent(u16 TIM1_EventSource);\r
+void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity);\r
+void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity);\r
+void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity);\r
+void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity);\r
+void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity);\r
+void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity);\r
+void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity);\r
+void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate);\r
+void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate);\r
+void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode);\r
+void TIM1_SetAutoreload(u16 Autoreload);\r
+void TIM1_SetCompare1(u16 Compare1);\r
+void TIM1_SetCompare2(u16 Compare2);\r
+void TIM1_SetCompare3(u16 Compare3);\r
+void TIM1_SetCompare4(u16 Compare4);\r
+void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler);\r
+void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler);\r
+void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler);\r
+void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler);\r
+void TIM1_SetClockDivision(u16 TIM1_CKD);\r
+u16 TIM1_GetCapture1(void);\r
+u16 TIM1_GetCapture2(void);\r
+u16 TIM1_GetCapture3(void);\r
+u16 TIM1_GetCapture4(void);\r
+u16 TIM1_GetCounter(void);\r
+u16 TIM1_GetPrescaler(void);\r
+FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG); \r
+void TIM1_ClearFlag(u16 TIM1_Flag);\r
+ITStatus TIM1_GetITStatus(u16 TIM1_IT);\r
+void TIM1_ClearITPendingBit(u16 TIM1_IT);\r
+\r
+#endif /*__STM32F10x_TIM1_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_type.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the common data types used for the\r
+* STM32F10x firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_TYPE_H\r
+#define __STM32F10x_TYPE_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Exported types ------------------------------------------------------------*/\r
+typedef signed long s32;\r
+typedef signed short s16;\r
+typedef signed char s8;\r
+\r
+typedef volatile signed long vs32;\r
+typedef volatile signed short vs16;\r
+typedef volatile signed char vs8;\r
+\r
+typedef unsigned long u32;\r
+typedef unsigned short u16;\r
+typedef unsigned char u8;\r
+\r
+typedef unsigned long const uc32; /* Read Only */\r
+typedef unsigned short const uc16; /* Read Only */\r
+typedef unsigned char const uc8; /* Read Only */\r
+\r
+typedef volatile unsigned long vu32;\r
+typedef volatile unsigned short vu16;\r
+typedef volatile unsigned char vu8;\r
+\r
+typedef volatile unsigned long const vuc32; /* Read Only */\r
+typedef volatile unsigned short const vuc16; /* Read Only */\r
+typedef volatile unsigned char const vuc8; /* Read Only */\r
+\r
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;\r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+#define U8_MAX ((u8)255)\r
+#define S8_MAX ((s8)127)\r
+#define S8_MIN ((s8)-128)\r
+#define U16_MAX ((u16)65535u)\r
+#define S16_MAX ((s16)32767)\r
+#define S16_MIN ((s16)-32768)\r
+#define U32_MAX ((u32)4294967295uL)\r
+#define S32_MAX ((s32)2147483647)\r
+#define S32_MIN ((s32)2147483648uL)\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+#endif /* __STM32F10x_TYPE_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_usart.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* USART firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_USART_H\r
+#define __STM32F10x_USART_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* UART Init Structure definition */\r
+typedef struct\r
+{\r
+ u32 USART_BaudRate;\r
+ u16 USART_WordLength;\r
+ u16 USART_StopBits;\r
+ u16 USART_Parity;\r
+ u16 USART_HardwareFlowControl;\r
+ u16 USART_Mode;\r
+ u16 USART_Clock;\r
+ u16 USART_CPOL;\r
+ u16 USART_CPHA;\r
+ u16 USART_LastBit;\r
+} USART_InitTypeDef;\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* USART Word Length ---------------------------------------------------------*/\r
+#define USART_WordLength_8b ((u16)0x0000)\r
+#define USART_WordLength_9b ((u16)0x1000)\r
+\r
+#define IS_USART_WORD_LENGTH(LENGTH) ((LENGTH == USART_WordLength_8b) || \\r
+ (LENGTH == USART_WordLength_9b))\r
+\r
+/* USART Stop Bits -----------------------------------------------------------*/\r
+#define USART_StopBits_1 ((u16)0x0000)\r
+#define USART_StopBits_0_5 ((u16)0x1000)\r
+#define USART_StopBits_2 ((u16)0x2000)\r
+#define USART_StopBits_1_5 ((u16)0x3000)\r
+\r
+#define IS_USART_STOPBITS(STOPBITS) ((STOPBITS == USART_StopBits_1) || \\r
+ (STOPBITS == USART_StopBits_0_5) || \\r
+ (STOPBITS == USART_StopBits_2) || \\r
+ (STOPBITS == USART_StopBits_1_5))\r
+/* USART Parity --------------------------------------------------------------*/\r
+#define USART_Parity_No ((u16)0x0000)\r
+#define USART_Parity_Even ((u16)0x0400)\r
+#define USART_Parity_Odd ((u16)0x0600) \r
+\r
+#define IS_USART_PARITY(PARITY) ((PARITY == USART_Parity_No) || \\r
+ (PARITY == USART_Parity_Even) || \\r
+ (PARITY == USART_Parity_Odd))\r
+\r
+/* USART Hardware Flow Control -----------------------------------------------*/\r
+#define USART_HardwareFlowControl_None ((u16)0x0000)\r
+#define USART_HardwareFlowControl_RTS ((u16)0x0100)\r
+#define USART_HardwareFlowControl_CTS ((u16)0x0200)\r
+#define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300)\r
+\r
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ ((CONTROL == USART_HardwareFlowControl_None) || \\r
+ (CONTROL == USART_HardwareFlowControl_RTS) || \\r
+ (CONTROL == USART_HardwareFlowControl_CTS) || \\r
+ (CONTROL == USART_HardwareFlowControl_RTS_CTS))\r
+\r
+/* USART Mode ----------------------------------------------------------------*/\r
+#define USART_Mode_Rx ((u16)0x0004)\r
+#define USART_Mode_Tx ((u16)0x0008)\r
+\r
+#define IS_USART_MODE(MODE) (((MODE & (u16)0xFFF3) == 0x00) && (MODE != (u16)0x00))\r
+\r
+/* USART Clock ---------------------------------------------------------------*/\r
+#define USART_Clock_Disable ((u16)0x0000)\r
+#define USART_Clock_Enable ((u16)0x0800)\r
+\r
+#define IS_USART_CLOCK(CLOCK) ((CLOCK == USART_Clock_Disable) || \\r
+ (CLOCK == USART_Clock_Enable))\r
+\r
+/* USART Clock Polarity ------------------------------------------------------*/\r
+#define USART_CPOL_Low ((u16)0x0000)\r
+#define USART_CPOL_High ((u16)0x0400)\r
+\r
+#define IS_USART_CPOL(CPOL) ((CPOL == USART_CPOL_Low) || (CPOL == USART_CPOL_High))\r
+ \r
+/* USART Clock Phase ---------------------------------------------------------*/\r
+#define USART_CPHA_1Edge ((u16)0x0000)\r
+#define USART_CPHA_2Edge ((u16)0x0200)\r
+#define IS_USART_CPHA(CPHA) ((CPHA == USART_CPHA_1Edge) || (CPHA == USART_CPHA_2Edge))\r
+\r
+/* USART Last Bit ------------------------------------------------------------*/\r
+#define USART_LastBit_Disable ((u16)0x0000)\r
+#define USART_LastBit_Enable ((u16)0x0100)\r
+\r
+#define IS_USART_LASTBIT(LASTBIT) ((LASTBIT == USART_LastBit_Disable) || \\r
+ (LASTBIT == USART_LastBit_Enable))\r
+\r
+/* USART Interrupt definition ------------------------------------------------*/\r
+#define USART_IT_PE ((u16)0x0028)\r
+#define USART_IT_TXE ((u16)0x0727)\r
+#define USART_IT_TC ((u16)0x0626)\r
+#define USART_IT_RXNE ((u16)0x0525)\r
+#define USART_IT_IDLE ((u16)0x0424)\r
+#define USART_IT_LBD ((u16)0x0846)\r
+#define USART_IT_CTS ((u16)0x096A)\r
+#define USART_IT_ERR ((u16)0x0060)\r
+#define USART_IT_ORE ((u16)0x0360)\r
+#define USART_IT_NE ((u16)0x0260)\r
+#define USART_IT_FE ((u16)0x0160)\r
+\r
+#define IS_USART_CONFIG_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \\r
+ (IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \\r
+ (IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \\r
+ (IT == USART_IT_CTS) || (IT == USART_IT_ERR))\r
+\r
+#define IS_USART_IT(IT) ((IT == USART_IT_PE) || (IT == USART_IT_TXE) || \\r
+ (IT == USART_IT_TC) || (IT == USART_IT_RXNE) || \\r
+ (IT == USART_IT_IDLE) || (IT == USART_IT_LBD) || \\r
+ (IT == USART_IT_CTS) || (IT == USART_IT_ORE) || \\r
+ (IT == USART_IT_NE) || (IT == USART_IT_FE))\r
+\r
+/* USART DMA Requests --------------------------------------------------------*/\r
+#define USART_DMAReq_Tx ((u16)0x0080)\r
+#define USART_DMAReq_Rx ((u16)0x0040)\r
+\r
+#define IS_USART_DMAREQ(DMAREQ) (((DMAREQ & (u16)0xFF3F) == 0x00) && (DMAREQ != (u16)0x00))\r
+\r
+/* USART WakeUp methods ------------------------------------------------------*/\r
+#define USART_WakeUp_IdleLine ((u16)0x0000)\r
+#define USART_WakeUp_AddressMark ((u16)0x0800)\r
+\r
+#define IS_USART_WAKEUP(WAKEUP) ((WAKEUP == USART_WakeUp_IdleLine) || \\r
+ (WAKEUP == USART_WakeUp_AddressMark))\r
+\r
+/* USART LIN Break Detection Length ------------------------------------------*/\r
+#define USART_LINBreakDetectLength_10b ((u16)0x0000)\r
+#define USART_LINBreakDetectLength_11b ((u16)0x0020)\r
+\r
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
+ ((LENGTH == USART_LINBreakDetectLength_10b) || \\r
+ (LENGTH == USART_LINBreakDetectLength_11b))\r
+\r
+/* USART IrDA Low Power ------------------------------------------------------*/\r
+#define USART_IrDAMode_LowPower ((u16)0x0004)\r
+#define USART_IrDAMode_Normal ((u16)0x0000)\r
+\r
+#define IS_USART_IRDA_MODE(MODE) ((MODE == USART_IrDAMode_LowPower) || \\r
+ (MODE == USART_IrDAMode_Normal))\r
+\r
+/* USART Flags ---------------------------------------------------------------*/\r
+#define USART_FLAG_CTS ((u16)0x0200)\r
+#define USART_FLAG_LBD ((u16)0x0100)\r
+#define USART_FLAG_TXE ((u16)0x0080)\r
+#define USART_FLAG_TC ((u16)0x0040)\r
+#define USART_FLAG_RXNE ((u16)0x0020)\r
+#define USART_FLAG_IDLE ((u16)0x0010)\r
+#define USART_FLAG_ORE ((u16)0x0008)\r
+#define USART_FLAG_NE ((u16)0x0004)\r
+#define USART_FLAG_FE ((u16)0x0002)\r
+#define USART_FLAG_PE ((u16)0x0001)\r
+\r
+#define IS_USART_FLAG(FLAG) ((FLAG == USART_FLAG_PE) || (FLAG == USART_FLAG_TXE) || \\r
+ (FLAG == USART_FLAG_TC) || (FLAG == USART_FLAG_RXNE) || \\r
+ (FLAG == USART_FLAG_IDLE) || (FLAG == USART_FLAG_LBD) || \\r
+ (FLAG == USART_FLAG_CTS) || (FLAG == USART_FLAG_ORE) || \\r
+ (FLAG == USART_FLAG_NE) || (FLAG == USART_FLAG_FE))\r
+ \r
+#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFC00) == 0x00) && (FLAG != (u16)0x00))\r
+\r
+#define IS_USART_ADDRESS(ADDRESS) (ADDRESS <= 0xF)\r
+#define IS_USART_DATA(DATA) (DATA <= 0x1FF)\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void USART_DeInit(USART_TypeDef* USARTx);\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState);\r
+void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState);\r
+void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address);\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp);\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength);\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SendData(USART_TypeDef* USARTx, u16 Data);\r
+u16 USART_ReceiveData(USART_TypeDef* USARTx);\r
+void USART_SendBreak(USART_TypeDef* USARTx);\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime);\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler);\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode);\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG);\r
+void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG);\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT);\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT);\r
+\r
+#endif /* __STM32F10x_USART_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_wwdg.h\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file contains all the functions prototypes for the\r
+* WWDG firmware library.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_WWDG_H\r
+#define __STM32F10x_WWDG_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_map.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* WWDG Prescaler */\r
+#define WWDG_Prescaler_1 ((u32)0x00000000)\r
+#define WWDG_Prescaler_2 ((u32)0x00000080)\r
+#define WWDG_Prescaler_4 ((u32)0x00000100)\r
+#define WWDG_Prescaler_8 ((u32)0x00000180)\r
+\r
+#define IS_WWDG_PRESCALER(PRESCALER) ((PRESCALER == WWDG_Prescaler_1) || \\r
+ (PRESCALER == WWDG_Prescaler_2) || \\r
+ (PRESCALER == WWDG_Prescaler_4) || \\r
+ (PRESCALER == WWDG_Prescaler_8))\r
+\r
+#define IS_WWDG_WINDOW_VALUE(VALUE) (VALUE <= 0x7F)\r
+\r
+#define IS_WWDG_COUNTER(COUNTER) ((COUNTER >= 0x40) && (COUNTER <= 0x7F))\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+void WWDG_DeInit(void);\r
+void WWDG_SetPrescaler(u32 WWDG_Prescaler);\r
+void WWDG_SetWindowValue(u8 WindowValue);\r
+void WWDG_EnableIT(void);\r
+void WWDG_SetCounter(u8 Counter);\r
+void WWDG_Enable(u8 Counter);\r
+FlagStatus WWDG_GetFlagStatus(void);\r
+void WWDG_ClearFlag(void);\r
+\r
+#endif /* __STM32F10x_WWDG_H */\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+;******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+;* File Name : cortexm3_macro.s\r
+;* Author : MCD Application Team\r
+;* Date First Issued : 02/19/2007\r
+;* Description : Instruction wrappers for special Cortex-M3 instructions.\r
+;*******************************************************************************\r
+; History:\r
+; 04/02/2007: V0.2\r
+; 02/19/2007: V0.1\r
+;*******************************************************************************\r
+; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+;*******************************************************************************\r
+ \r
+ SECTION .text:CODE(2)\r
+\r
+ ; Exported functions\r
+ EXPORT __WFI\r
+ EXPORT __WFE\r
+ EXPORT __SEV\r
+ EXPORT __ISB\r
+ EXPORT __DSB\r
+ EXPORT __DMB\r
+ EXPORT __SVC\r
+ EXPORT __MRS_CONTROL\r
+ EXPORT __MSR_CONTROL\r
+ EXPORT __MRS_PSP\r
+ EXPORT __MSR_PSP\r
+ EXPORT __MRS_MSP\r
+ EXPORT __MSR_MSP\r
+ EXPORT __SETPRIMASK\r
+ EXPORT __RESETPRIMASK\r
+ EXPORT __SETFAULTMASK\r
+ EXPORT __RESETFAULTMASK\r
+ EXPORT __BASEPRICONFIG\r
+ EXPORT __GetBASEPRI\r
+ EXPORT __REV_HalfWord\r
+ EXPORT __REV_Word \r
+\r
+;*******************************************************************************\r
+; Function Name : __WFI\r
+; Description : Assembler function for the WFI instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__WFI \r
+ \r
+ WFI\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __WFE\r
+; Description : Assembler function for the WFE instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__WFE\r
+\r
+ WFE\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __SEV\r
+; Description : Assembler function for the SEV instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__SEV\r
+\r
+ SEV\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __ISB\r
+; Description : Assembler function for the ISB instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__ISB\r
+\r
+ ISB\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __DSB\r
+; Description : Assembler function for the DSB instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__DSB\r
+\r
+ DSB\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __DMB\r
+; Description : Assembler function for the DMB instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__DMB\r
+\r
+ DMB\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __SVC\r
+; Description : Assembler function for the SVC instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__SVC\r
+\r
+ SVC 0x01\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MRS_CONTROL\r
+; Description : Assembler function for the MRS instruction.\r
+; Input : None\r
+; Return : - r0 : Cortex-M3 CONTROL register value.\r
+;*******************************************************************************\r
+__MRS_CONTROL\r
+\r
+ MRS r0, CONTROL\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MSR_CONTROL\r
+; Description : Assembler function for the MSR instruction.\r
+; Input : - r0 : Cortex-M3 CONTROL register new value. \r
+; Return : None\r
+;*******************************************************************************\r
+__MSR_CONTROL\r
+\r
+ MSR CONTROL, r0\r
+ ISB\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MRS_PSP\r
+; Description : Assembler function for the MRS instruction.\r
+; Input : None\r
+; Return : - r0 : Process Stack value.\r
+;*******************************************************************************\r
+__MRS_PSP\r
+\r
+ MRS r0, PSP\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MSR_PSP\r
+; Description : Assembler function for the MSR instruction.\r
+; Input : - r0 : Process Stack new value.\r
+; Return : None\r
+;*******************************************************************************\r
+__MSR_PSP\r
+\r
+ MSR PSP, r0 ; set Process Stack value\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MRS_MSP\r
+; Description : Assembler function for the MRS instruction.\r
+; Input : None\r
+; Return : - r0 : Main Stack value.\r
+;*******************************************************************************\r
+__MRS_MSP\r
+\r
+ MRS r0, MSP\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MSR_MSP\r
+; Description : Assembler function for the MSR instruction.\r
+; Input : - r0 : Main Stack new value.\r
+; Return : None\r
+;*******************************************************************************\r
+__MSR_MSP\r
+\r
+ MSR MSP, r0 ; set Main Stack value\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __SETPRIMASK\r
+; Description : Assembler function to set the PRIMASK.\r
+; Input : None \r
+; Return : None\r
+;*******************************************************************************\r
+__SETPRIMASK\r
+\r
+ CPSID i\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __RESETPRIMASK\r
+; Description : Assembler function to reset the PRIMASK.\r
+; Input : None \r
+; Return : None\r
+;*******************************************************************************\r
+__RESETPRIMASK\r
+\r
+ CPSIE i\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __SETFAULTMASK\r
+; Description : Assembler function to set the FAULTMASK.\r
+; Input : None \r
+; Return : None\r
+;*******************************************************************************\r
+__SETFAULTMASK\r
+\r
+ CPSID f\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __RESETFAULTMASK\r
+; Description : Assembler function to reset the FAULTMASK.\r
+; Input : None \r
+; Return : None\r
+;*******************************************************************************\r
+__RESETFAULTMASK\r
+\r
+ CPSIE f\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __BASEPRICONFIG\r
+; Description : Assembler function to set the Base Priority.\r
+; Input : - r0 : Base Priority new value \r
+; Return : None\r
+;*******************************************************************************\r
+__BASEPRICONFIG\r
+\r
+ MSR BASEPRI, r0\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __GetBASEPRI\r
+; Description : Assembler function to get the Base Priority value.\r
+; Input : None \r
+; Return : - r0 : Base Priority value \r
+;*******************************************************************************\r
+__GetBASEPRI\r
+\r
+ MRS r0, BASEPRI_MAX\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __REV_HalfWord\r
+; Description : Reverses the byte order in HalfWord(16-bit) input variable.\r
+; Input : - r0 : specifies the input variable\r
+; Return : - r0 : holds tve variable value after byte reversing.\r
+;*******************************************************************************\r
+__REV_HalfWord \r
+ \r
+ REV16 r0, r0\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __REV_Word\r
+; Description : Reverses the byte order in Word(32-bit) input variable.\r
+; Input : - r0 : specifies the input variable\r
+; Return : - r0 : holds tve variable value after byte reversing.\r
+;*******************************************************************************\r
+__REV_Word \r
+ \r
+ REV r0, r0\r
+ BX r14\r
+ \r
+ END\r
+ \r
+;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE*****\r
--- /dev/null
+;******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+;* File Name : cortexm3_macro.s\r
+;* Author : MCD Application Team\r
+;* Date First Issued : 09/29/2006\r
+;* Description : Instruction wrappers for special Cortex-M3 instructions.\r
+;*******************************************************************************\r
+; History:\r
+; 05/21/2007: V0.3\r
+; 04/02/2007: V0.2\r
+; 02/05/2007: V0.1\r
+; 09/29/2006: V0.01\r
+;*******************************************************************************\r
+; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+;*******************************************************************************\r
+ \r
+ THUMB\r
+ REQUIRE8\r
+ PRESERVE8\r
+ \r
+ AREA |.text|, CODE, READONLY, ALIGN=2\r
+\r
+ ; Exported functions\r
+ EXPORT __WFI\r
+ EXPORT __WFE\r
+ EXPORT __SEV\r
+ EXPORT __ISB\r
+ EXPORT __DSB\r
+ EXPORT __DMB\r
+ EXPORT __SVC\r
+ EXPORT __MRS_CONTROL\r
+ EXPORT __MSR_CONTROL\r
+ EXPORT __MRS_PSP\r
+ EXPORT __MSR_PSP\r
+ EXPORT __MRS_MSP\r
+ EXPORT __MSR_MSP \r
+ EXPORT __SETPRIMASK\r
+ EXPORT __RESETPRIMASK\r
+ EXPORT __SETFAULTMASK\r
+ EXPORT __RESETFAULTMASK\r
+ EXPORT __BASEPRICONFIG\r
+ EXPORT __GetBASEPRI\r
+ EXPORT __REV_HalfWord\r
+ EXPORT __REV_Word\r
+\r
+;*******************************************************************************\r
+; Function Name : __WFI\r
+; Description : Assembler function for the WFI instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__WFI \r
+ \r
+ WFI\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __WFE\r
+; Description : Assembler function for the WFE instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__WFE\r
+\r
+ WFE\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __SEV\r
+; Description : Assembler function for the SEV instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__SEV\r
+\r
+ SEV\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __ISB\r
+; Description : Assembler function for the ISB instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__ISB\r
+\r
+ ISB\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __DSB\r
+; Description : Assembler function for the DSB instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__DSB\r
+\r
+ DSB\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __DMB\r
+; Description : Assembler function for the DMB instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__DMB\r
+\r
+ DMB\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __SVC\r
+; Description : Assembler function for the SVC instruction.\r
+; Input : None\r
+; Return : None\r
+;*******************************************************************************\r
+__SVC\r
+\r
+ SVC 0x01\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MRS_CONTROL\r
+; Description : Assembler function for the MRS instruction.\r
+; Input : None\r
+; Return : - r0 : Cortex-M3 CONTROL register value.\r
+;*******************************************************************************\r
+__MRS_CONTROL\r
+\r
+ MRS r0, CONTROL\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MSR_CONTROL\r
+; Description : Assembler function for the MSR instruction.\r
+; Input : - r0 : Cortex-M3 CONTROL register new value. \r
+; Return : None\r
+;*******************************************************************************\r
+__MSR_CONTROL\r
+\r
+ MSR CONTROL, r0\r
+ ISB\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MRS_PSP\r
+; Description : Assembler function for the MRS instruction.\r
+; Input : None\r
+; Return : - r0 : Process Stack value.\r
+;*******************************************************************************\r
+__MRS_PSP\r
+\r
+ MRS r0, PSP\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MSR_PSP\r
+; Description : Assembler function for the MSR instruction.\r
+; Input : - r0 : Process Stack new value. \r
+; Return : None\r
+;*******************************************************************************\r
+__MSR_PSP \r
+ \r
+ MSR PSP, r0 ; set Process Stack value\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MRS_MSP\r
+; Description : Assembler function for the MRS instruction.\r
+; Input : None\r
+; Return : - r0 : Main Stack value.\r
+;*******************************************************************************\r
+__MRS_MSP\r
+\r
+ MRS r0, MSP\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __MSR_MSP\r
+; Description : Assembler function for the MSR instruction.\r
+; Input : - r0 : Main Stack new value. \r
+; Return : None\r
+;*******************************************************************************\r
+__MSR_MSP \r
+ \r
+ MSR MSP, r0 ; set Main Stack value\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __SETPRIMASK\r
+; Description : Assembler function to set the PRIMASK.\r
+; Input : None \r
+; Return : None\r
+;*******************************************************************************\r
+__SETPRIMASK\r
+\r
+ CPSID i\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __RESETPRIMASK\r
+; Description : Assembler function to reset the PRIMASK.\r
+; Input : None \r
+; Return : None\r
+;*******************************************************************************\r
+__RESETPRIMASK\r
+\r
+ CPSIE i\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __SETFAULTMASK\r
+; Description : Assembler function to set the FAULTMASK.\r
+; Input : None \r
+; Return : None\r
+;*******************************************************************************\r
+__SETFAULTMASK\r
+\r
+ CPSID f\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __RESETFAULTMASK\r
+; Description : Assembler function to reset the FAULTMASK.\r
+; Input : None \r
+; Return : None\r
+;*******************************************************************************\r
+__RESETFAULTMASK\r
+\r
+ CPSIE f\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __BASEPRICONFIG\r
+; Description : Assembler function to set the Base Priority.\r
+; Input : - r0 : Base Priority new value \r
+; Return : None\r
+;*******************************************************************************\r
+__BASEPRICONFIG\r
+\r
+ MSR BASEPRI, r0\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __GetBASEPRI\r
+; Description : Assembler function to get the Base Priority value.\r
+; Input : None \r
+; Return : - r0 : Base Priority value \r
+;*******************************************************************************\r
+__GetBASEPRI\r
+\r
+ MRS r0, BASEPRI_MAX\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __REV_HalfWord\r
+; Description : Reverses the byte order in HalfWord(16-bit) input variable.\r
+; Input : - r0 : specifies the input variable\r
+; Return : - r0 : holds tve variable value after byte reversing.\r
+;*******************************************************************************\r
+__REV_HalfWord \r
+ \r
+ REV16 r0, r0\r
+ BX r14\r
+\r
+;*******************************************************************************\r
+; Function Name : __REV_Word\r
+; Description : Reverses the byte order in Word(32-bit) input variable.\r
+; Input : - r0 : specifies the input variable\r
+; Return : - r0 : holds tve variable value after byte reversing.\r
+;*******************************************************************************\r
+__REV_Word \r
+ \r
+ REV r0, r0\r
+ BX r14\r
+ \r
+ END\r
+ \r
+;******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE*****\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : lcd.c\r
+* Author : MCD Application Team\r
+* Date First Issued : mm/dd/yyyy\r
+* Description : This file includes the LCD driver for AM-240320LTNQW00H\r
+* liquid Crystal Display Module of STM32F10x-EVAL.\r
+********************************************************************************\r
+* History:\r
+* mm/dd/yyyy\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_type.h"\r
+#include "lcd.h"\r
+#include "spi_flash.h"\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+ /* ASCII Table: each character is 16 column (16dots large)\r
+ and 24 raw (24 dots high) */\r
+ const uc16 ASCII_Table[] =\r
+ {\r
+ /* Space ' ' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '!' */\r
+ 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,\r
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '"' */\r
+ 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '#' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,\r
+ 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,\r
+ 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,\r
+ /* '$' */\r
+ 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,\r
+ 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,\r
+ 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,\r
+ /* '%' */\r
+ 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,\r
+ 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,\r
+ 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,\r
+ /* '&' */\r
+ 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,\r
+ 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,\r
+ 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* ''' */\r
+ 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '(' */\r
+ 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,\r
+ 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,\r
+ 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,\r
+ /* ')' */\r
+ 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,\r
+ 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,\r
+ 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,\r
+ /* '*' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,\r
+ 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '+' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* ',' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,\r
+ /* '-' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '.' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '/' */\r
+ 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,\r
+ 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,\r
+ 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '0' */\r
+ 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,\r
+ 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,\r
+ 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '1' */\r
+ 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,\r
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '2' */\r
+ 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,\r
+ 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,\r
+ 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '3' */\r
+ 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,\r
+ 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,\r
+ 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '4' */\r
+ 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,\r
+ 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,\r
+ 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '5' */\r
+ 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,\r
+ 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,\r
+ 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '6' */\r
+ 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,\r
+ 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,\r
+ 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '7' */\r
+ 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,\r
+ 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,\r
+ 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '8' */\r
+ 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,\r
+ 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,\r
+ 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '9' */\r
+ 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,\r
+ 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,\r
+ 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* ':' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* ';' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,\r
+ /* '<' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,\r
+ 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '=' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '>' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,\r
+ 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '?' */\r
+ 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,\r
+ 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,\r
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '@' */\r
+ 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,\r
+ 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,\r
+ 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'A' */\r
+ 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,\r
+ 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,\r
+ 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'B' */\r
+ 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,\r
+ 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,\r
+ 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'C' */\r
+ 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,\r
+ 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,\r
+ 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'D' */\r
+ 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,\r
+ 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,\r
+ 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'E' */\r
+ 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+ 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+ 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'F' */\r
+ 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+ 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+ 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'G' */\r
+ 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,\r
+ 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,\r
+ 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'H' */\r
+ 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+ 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+ 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'I' */\r
+ 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'J' */\r
+ 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,\r
+ 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,\r
+ 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'K' */\r
+ 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,\r
+ 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,\r
+ 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'L' */\r
+ 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+ 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+ 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'M' */\r
+ 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,\r
+ 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,\r
+ 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'N' */\r
+ 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,\r
+ 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,\r
+ 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'O' */\r
+ 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,\r
+ 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,\r
+ 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'P' */\r
+ 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+ 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+ 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'Q' */\r
+ 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,\r
+ 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,\r
+ 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'R' */\r
+ 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,\r
+ 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,\r
+ 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'S' */\r
+ 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,\r
+ 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,\r
+ 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'T' */\r
+ 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'U' */\r
+ 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+ 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,\r
+ 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'V' */\r
+ 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,\r
+ 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,\r
+ 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'W' */\r
+ 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,\r
+ 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,\r
+ 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'X' */\r
+ 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,\r
+ 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,\r
+ 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'Y' */\r
+ 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,\r
+ 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'Z' */\r
+ 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,\r
+ 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,\r
+ 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '[' */\r
+ 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,\r
+ 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,\r
+ 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,\r
+ /* '\' */\r
+ 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,\r
+ 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,\r
+ 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* ']' */\r
+ 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,\r
+ 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,\r
+ 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,\r
+ /* '^' */\r
+ 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,\r
+ 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '_' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* ''' */\r
+ 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'a' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,\r
+ 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,\r
+ 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'b' */\r
+ 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,\r
+ 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,\r
+ 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'c' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,\r
+ 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,\r
+ 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'd' */\r
+ 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,\r
+ 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,\r
+ 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'e' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,\r
+ 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,\r
+ 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'f' */\r
+ 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,\r
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'g' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,\r
+ 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,\r
+ 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,\r
+ /* 'h' */\r
+ 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,\r
+ 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,\r
+ 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'i' */\r
+ 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,\r
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'j' */\r
+ 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,\r
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,\r
+ /* 'k' */\r
+ 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,\r
+ 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,\r
+ 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'l' */\r
+ 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'm' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,\r
+ 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,\r
+ 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'n' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,\r
+ 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,\r
+ 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'o' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,\r
+ 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,\r
+ 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'p' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,\r
+ 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,\r
+ 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,\r
+ /* 'q' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,\r
+ 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,\r
+ 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,\r
+ /* 'r' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,\r
+ 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,\r
+ 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 's' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,\r
+ 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,\r
+ 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 't' */\r
+ 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,\r
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+ 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'u' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,\r
+ 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,\r
+ 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'v' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,\r
+ 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,\r
+ 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'w' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,\r
+ 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,\r
+ 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'x' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,\r
+ 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,\r
+ 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* 'y' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,\r
+ 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,\r
+ 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,\r
+ /* 'z' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,\r
+ 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,\r
+ 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ /* '{' */\r
+ 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+ 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,\r
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,\r
+ /* '|' */\r
+ 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,\r
+ /* '}' */\r
+ 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,\r
+ 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,\r
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,\r
+ /* '~' */\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+ };\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+ /* Global variables to set the written text color */\r
+static vu16 TextColor = 0x0000, BackColor = 0xFFFF;\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+static u32 StrLength(u8 *Str);\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_Init\r
+* Description : Initializes LCD.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_Init(void)\r
+{\r
+/* Configure the LCD Control pins --------------------------------------------*/\r
+ LCD_CtrlLinesConfig();\r
+\r
+/* Configure the SPI2 interface ----------------------------------------------*/\r
+ LCD_SPIConfig();\r
+\r
+/* Enable the LCD Oscillator -------------------------------------------------*/\r
+ LCD_WriteReg(R1, 0x10);\r
+ LCD_WriteReg(R0, 0xA0);\r
+ LCD_WriteReg(R3, 0x01);\r
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */\r
+ LCD_WriteReg(R3, 0x00);\r
+ LCD_WriteReg(R43, 0x04);\r
+\r
+ LCD_WriteReg(R40, 0x18);\r
+ LCD_WriteReg(R26, 0x05);\r
+ LCD_WriteReg(R37, 0x05);\r
+ LCD_WriteReg(R25, 0x00);\r
+\r
+/* LCD Power On --------------------------------------------------------------*/\r
+ LCD_WriteReg(R28, 0x73);\r
+ LCD_WriteReg(R36, 0x74);\r
+ LCD_WriteReg(R30, 0x01);\r
+ LCD_WriteReg(R24, 0xC1);\r
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */\r
+ LCD_WriteReg(R24, 0xE1);\r
+ LCD_WriteReg(R24, 0xF1);\r
+ vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */\r
+ LCD_WriteReg(R24, 0xF5);\r
+ vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */\r
+ LCD_WriteReg(R27, 0x09);\r
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */\r
+ LCD_WriteReg(R31, 0x11);\r
+ LCD_WriteReg(R32, 0x0E);\r
+ LCD_WriteReg(R30, 0x81);\r
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */\r
+\r
+/* Chip Set ------------------------------------------------------------------*/\r
+ LCD_WriteReg(R157, 0x00);\r
+ LCD_WriteReg(R192, 0x00);\r
+\r
+ LCD_WriteReg(R14, 0x00);\r
+ LCD_WriteReg(R15, 0x00);\r
+ LCD_WriteReg(R16, 0x00);\r
+ LCD_WriteReg(R17, 0x00);\r
+ LCD_WriteReg(R18, 0x00);\r
+ LCD_WriteReg(R19, 0x00);\r
+ LCD_WriteReg(R20, 0x00);\r
+ LCD_WriteReg(R21, 0x00);\r
+ LCD_WriteReg(R22, 0x00);\r
+ LCD_WriteReg(R23, 0x00);\r
+\r
+ LCD_WriteReg(R52, 0x01);\r
+ LCD_WriteReg(R53, 0x00);\r
+\r
+ LCD_WriteReg(R75, 0x00);\r
+ LCD_WriteReg(R76, 0x00);\r
+ LCD_WriteReg(R78, 0x00);\r
+ LCD_WriteReg(R79, 0x00);\r
+ LCD_WriteReg(R80, 0x00);\r
+\r
+ LCD_WriteReg(R60, 0x00);\r
+ LCD_WriteReg(R61, 0x00);\r
+ LCD_WriteReg(R62, 0x01);\r
+ LCD_WriteReg(R63, 0x3F);\r
+ LCD_WriteReg(R64, 0x02);\r
+ LCD_WriteReg(R65, 0x02);\r
+ LCD_WriteReg(R66, 0x00);\r
+ LCD_WriteReg(R67, 0x00);\r
+ LCD_WriteReg(R68, 0x00);\r
+ LCD_WriteReg(R69, 0x00);\r
+ LCD_WriteReg(R70, 0xEF);\r
+ LCD_WriteReg(R71, 0x00);\r
+ LCD_WriteReg(R72, 0x00);\r
+ LCD_WriteReg(R73, 0x01);\r
+ LCD_WriteReg(R74, 0x3F);\r
+\r
+ LCD_WriteReg(R29, 0x08); /* R29:Gate scan direction setting */\r
+\r
+ LCD_WriteReg(R134, 0x00);\r
+ LCD_WriteReg(R135, 0x30);\r
+ LCD_WriteReg(R136, 0x02);\r
+ LCD_WriteReg(R137, 0x05);\r
+\r
+ LCD_WriteReg(R141, 0x01); /* R141:Register set-up mode for one line clock */\r
+ LCD_WriteReg(R139, 0x20); /* R139:One line SYSCLK number in one-line */\r
+ LCD_WriteReg(R51, 0x01); /* R51:N line inversion setting */\r
+ LCD_WriteReg(R55, 0x01); /* R55:Scanning method setting */\r
+ LCD_WriteReg(R118, 0x00);\r
+\r
+/* Gamma Set -----------------------------------------------------------------*/\r
+ LCD_WriteReg(R143, 0x10);\r
+ LCD_WriteReg(R144, 0x67);\r
+ LCD_WriteReg(R145, 0x07);\r
+ LCD_WriteReg(R146, 0x65);\r
+ LCD_WriteReg(R147, 0x07);\r
+ LCD_WriteReg(R148, 0x01);\r
+ LCD_WriteReg(R149, 0x76);\r
+ LCD_WriteReg(R150, 0x56);\r
+ LCD_WriteReg(R151, 0x00);\r
+ LCD_WriteReg(R152, 0x06);\r
+ LCD_WriteReg(R153, 0x03);\r
+ LCD_WriteReg(R154, 0x00);\r
+\r
+/* Display On ----------------------------------------------------------------*/\r
+ LCD_WriteReg(R1, 0x50);\r
+ LCD_WriteReg(R5, 0x04);\r
+\r
+ LCD_WriteReg(R0, 0x80);\r
+ LCD_WriteReg(R59, 0x01);\r
+ vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */\r
+ LCD_WriteReg(R0, 0x20);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SetTextColor\r
+* Description : Sets the Text color.\r
+* Input : - Color: specifies the Text color code RGB(5-6-5).\r
+* Output : - TextColor: Text color global variable used by LCD_DrawChar\r
+* and LCD_DrawPicture functions.\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SetTextColor(vu16 Color)\r
+{\r
+ TextColor = Color;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SetBackColor\r
+* Description : Sets the Background color.\r
+* Input : - Color: specifies the Background color code RGB(5-6-5).\r
+* Output : - BackColor: Background color global variable used by\r
+* LCD_DrawChar and LCD_DrawPicture functions.\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SetBackColor(vu16 Color)\r
+{\r
+ BackColor = Color;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_ClearLine\r
+* Description : Clears the selected line.\r
+* Input : - Line: the Line to be cleared.\r
+* This parameter can be one of the following values:\r
+* - Linex: where x can be 0..9\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_ClearLine(u8 Line)\r
+{\r
+ LCD_DisplayStringLine(Line, " ");\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_Clear\r
+* Description : Clears the hole LCD.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_Clear(void)\r
+{\r
+ u32 index = 0;\r
+\r
+ LCD_SetCursor(0x00, 0x013F);\r
+\r
+ for(index = 0; index < 0x12C00; index++)\r
+ {\r
+ LCD_WriteRAM(White);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SetCursor\r
+* Description : Sets the cursor position.\r
+* Input : - Xpos: specifies the X position.\r
+* - Ypos: specifies the Y position.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SetCursor(u8 Xpos, u16 Ypos)\r
+{\r
+ LCD_WriteReg(R66, Xpos);\r
+ LCD_WriteReg(R67, ((Ypos & 0x100)>> 8));\r
+ LCD_WriteReg(R68, (Ypos & 0xFF));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawChar\r
+* Description : Draws a character on LCD.\r
+* Input : - Xpos: the Line where to display the character shape.\r
+* This parameter can be one of the following values:\r
+* - Linex: where x can be 0..9\r
+* - Ypos: start column address.\r
+* - c: pointer to the character data.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DrawChar(u8 Xpos, u16 Ypos, uc16 *c)\r
+{\r
+ u32 index = 0, i = 0;\r
+ u8 Xaddress = 0;\r
+\r
+ Xaddress = Xpos;\r
+\r
+ LCD_SetCursor(Xaddress, Ypos);\r
+\r
+ for(index = 0; index < 24; index++)\r
+ {\r
+ for(i = 0; i < 16; i++)\r
+ {\r
+ if((c[index] & (1 << i)) == 0x00)\r
+ {\r
+ LCD_WriteRAM(BackColor);\r
+ }\r
+ else\r
+ {\r
+ LCD_WriteRAM(TextColor);\r
+ }\r
+ }\r
+ Xaddress++;\r
+ LCD_SetCursor(Xaddress, Ypos);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DisplayChar\r
+* Description : Displays one character (16dots width, 24dots height).\r
+* Input : - Line: the Line where to display the character shape .\r
+* This parameter can be one of the following values:\r
+* - Linex: where x can be 0..9\r
+* - Column: start column address.\r
+* - Ascii: character ascii code, must be between 0x20 and 0x7E.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DisplayChar(u8 Line, u16 Column, u8 Ascii)\r
+{\r
+ Ascii -= 32;\r
+ LCD_DrawChar(Line, Column, &ASCII_Table[Ascii * 24]);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DisplayStringLine\r
+* Description : Displays a maximum of 20 char on the LCD.\r
+* Input : - Line: the Line where to display the character shape .\r
+* This parameter can be one of the following values:\r
+* - Linex: where x can be 0..9\r
+* - *ptr: pointer to string to display on LCD.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DisplayStringLine(u8 Line, u8 *ptr)\r
+{\r
+ u32 i = 0;\r
+ u16 refcolumn = 319;\r
+\r
+ /* Send the string character by character on lCD */\r
+ while ((*ptr != 0) & (i < 20))\r
+ {\r
+ /* Display one character on LCD */\r
+ LCD_DisplayChar(Line, refcolumn, *ptr);\r
+ /* Decrement the column position by 16 */\r
+ refcolumn -= 16;\r
+ /* Point on the next character */\r
+ ptr++;\r
+ /* Increment the character counter */\r
+ i++;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DisplayString\r
+* Description : Displays a maximum of 200 char on the LCD.\r
+* Input : - Line: the starting Line where to display the character shape.\r
+* This parameter can be one of the following values:\r
+* - Linex: where x can be 0..9\r
+* - *ptr: pointer to string to display on LCD.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DisplayString(u8 Line, u8 *ptr)\r
+{\r
+ u32 i = 0, column = 0, index = 0, spaceindex = 0;\r
+ u16 refcolumn = 319;\r
+ u32 length = 0;\r
+\r
+ /* Get the string length */\r
+ length = StrLength(ptr);\r
+ if(length > 200)\r
+ {\r
+ /* Set the Cursor position */\r
+ LCD_SetCursor(Line, 0x013F);\r
+ /* Clear the Selected Line */\r
+ LCD_ClearLine(Line);\r
+ LCD_DisplayStringLine(Line, " String too long ");\r
+ }\r
+ else\r
+ {\r
+ /* Set the Cursor position */\r
+ LCD_SetCursor(Line, 0x013F);\r
+ /* Clear the Selected Line */\r
+ LCD_ClearLine(Line);\r
+\r
+ while(length--)\r
+ {\r
+ if(index == 20)\r
+ {\r
+ if(*ptr == 0x20)\r
+ {\r
+ ptr++;\r
+ }\r
+ else\r
+ {\r
+ for(i = 0; i < spaceindex; i++)\r
+ {\r
+ LCD_DisplayChar(Line, column, ' ');\r
+ column -= 16;\r
+ }\r
+ ptr -= (spaceindex - 1);\r
+ length += (spaceindex - 1);\r
+ }\r
+ Line += 24;\r
+ /* Clear the Selected Line */\r
+ LCD_ClearLine(Line);\r
+ refcolumn = 319;\r
+ index = 0;\r
+ }\r
+ /* Display one character on LCD */\r
+ LCD_DisplayChar(Line, refcolumn, *ptr);\r
+\r
+ /* Increment character number in one line */\r
+ index++;\r
+\r
+ /* Decrement the column position by 16 */\r
+ refcolumn -= 16;\r
+ /* Point on the next character */\r
+ ptr++;\r
+ /* Increment the number of character after the last space */\r
+ spaceindex++;\r
+ if(*ptr == 0x20)\r
+ {\r
+ spaceindex = 0;\r
+ column = refcolumn - 16;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_ScrollText\r
+* Description :\r
+* Input :\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_ScrollText(u8 Line, u8 *ptr)\r
+{\r
+ u32 i = 0, length = 0, x = 0;\r
+ u16 refcolumn = 319;\r
+\r
+ /* Get the string length */\r
+ length = StrLength(ptr);\r
+\r
+ while(1)\r
+ {\r
+ /* Send the string character by character on lCD */\r
+ while ((*ptr != 0) & (i < 20))\r
+ {\r
+ /* Display one character on LCD */\r
+ LCD_DisplayChar(Line, refcolumn, *ptr);\r
+ /* Decrement the column position by 16 */\r
+ refcolumn -= 16;\r
+ /* Point on the next character */\r
+ ptr++;\r
+ /* Increment the character counter */\r
+ i++;\r
+ }\r
+ vTaskDelay( 100 / portTICK_RATE_MS );\r
+ i = 0;\r
+ //LCD_ClearLine(Line);\r
+ ptr -= length;\r
+ x++;\r
+ if(refcolumn < 16)\r
+ {\r
+ x = 0;\r
+ }\r
+ refcolumn = 319 - (x * 16);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SetDisplayWindow\r
+* Description : Sets a display window\r
+* Input : - Xpos: specifies the X position.\r
+* - Ypos: specifies the Y position.\r
+* - Height: display window height.\r
+* - Width: display window width.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SetDisplayWindow(u8 Xpos, u16 Ypos, u8 Height, u16 Width)\r
+{\r
+ LCD_WriteReg(R1, 0xD0);\r
+ LCD_WriteReg(R5, 0x14);\r
+\r
+ LCD_WriteReg(R69, Xpos);\r
+ LCD_WriteReg(R70, (Xpos + Height + 1));\r
+\r
+ LCD_WriteReg(R71, ((Ypos & 0x100)>> 8));\r
+ LCD_WriteReg(R72, (Ypos & 0xFF));\r
+\r
+ LCD_WriteReg(R73, (((Ypos + Width + 1) & 0x100)>> 8));\r
+ LCD_WriteReg(R74, ((Ypos + Width + 1) & 0xFF));\r
+\r
+ LCD_SetCursor(Xpos, Ypos);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawLine\r
+* Description : Displays a line.\r
+* Input : - Xpos: specifies the X position.\r
+* - Ypos: specifies the Y position.\r
+* - Length: line length.\r
+* - Direction: line direction.\r
+* This parameter can be one of the following values: Vertical\r
+* or Horizontal.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DrawLine(u8 Xpos, u16 Ypos, u16 Length, u8 Direction)\r
+{\r
+ u32 i = 0;\r
+\r
+ LCD_SetCursor(Xpos, Ypos);\r
+\r
+ if(Direction == Horizontal)\r
+ {\r
+ for(i = 0; i < Length; i++)\r
+ {\r
+ LCD_WriteRAM(TextColor);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ for(i = 0; i < Length; i++)\r
+ {\r
+\r
+ LCD_WriteRAM(TextColor);\r
+ Xpos++;\r
+ LCD_SetCursor(Xpos, Ypos);\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawRect\r
+* Description : Displays a rectangle.\r
+* Input : - Xpos: specifies the X position.\r
+* - Ypos: specifies the Y position.\r
+* - Height: display rectangle height.\r
+* - Width: display rectangle width.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DrawRect(u8 Xpos, u16 Ypos, u8 Height, u16 Width)\r
+{\r
+ LCD_DrawLine(Xpos, Ypos, Width, Horizontal);\r
+ LCD_DrawLine((Xpos + Height), Ypos, Width, Horizontal);\r
+\r
+ LCD_DrawLine(Xpos, Ypos, Height, Vertical);\r
+ LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, Vertical);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawCircle\r
+* Description : Displays a circle.\r
+* Input : - Xpos: specifies the X position.\r
+* - Ypos: specifies the Y position.\r
+* - Height: display rectangle height.\r
+* - Width: display rectangle width.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DrawCircle(u8 Xpos, u16 Ypos, u16 Radius)\r
+{\r
+ s32 D; /* Decision Variable */\r
+ u32 CurX; /* Current X Value */\r
+ u32 CurY; /* Current Y Value */\r
+\r
+ D = 3 - (Radius << 1);\r
+ CurX = 0;\r
+ CurY = Radius;\r
+\r
+ while (CurX <= CurY)\r
+ {\r
+ LCD_SetCursor(Xpos + CurX, Ypos + CurY);\r
+ LCD_WriteRAM(TextColor);\r
+ LCD_SetCursor(Xpos + CurX, Ypos - CurY);\r
+ LCD_WriteRAM(TextColor);\r
+ LCD_SetCursor(Xpos - CurX, Ypos + CurY);\r
+ LCD_WriteRAM(TextColor);\r
+ LCD_SetCursor(Xpos - CurX, Ypos - CurY);\r
+ LCD_WriteRAM(TextColor);\r
+ LCD_SetCursor(Xpos + CurY, Ypos + CurX);\r
+ LCD_WriteRAM(TextColor);\r
+ LCD_SetCursor(Xpos + CurY, Ypos - CurX);\r
+ LCD_WriteRAM(TextColor);\r
+ LCD_SetCursor(Xpos - CurY, Ypos + CurX);\r
+ LCD_WriteRAM(TextColor);\r
+ LCD_SetCursor(Xpos - CurY, Ypos - CurX);\r
+ LCD_WriteRAM(TextColor);\r
+\r
+ if (D < 0)\r
+ {\r
+ D += (CurX << 2) + 6;\r
+ }\r
+ else\r
+ {\r
+ D += ((CurX - CurY) << 2) + 10;\r
+ CurY--;\r
+ }\r
+ CurX++;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawMonoPict\r
+* Description : Displays a monocolor picture.\r
+* Input : - Pict: pointer to the picture array.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DrawMonoPict(uc32 *Pict)\r
+{\r
+ u32 index = 0, i = 0;\r
+\r
+ LCD_SetCursor(0, 319);\r
+\r
+ for(index = 0; index < 2400; index++)\r
+ {\r
+ for(i = 0; i < 32; i++)\r
+ {\r
+ if((Pict[index] & (1 << i)) == 0x00)\r
+ {\r
+ LCD_WriteRAM(BackColor);\r
+ }\r
+ else\r
+ {\r
+ LCD_WriteRAM(TextColor);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DrawBMP\r
+* Description : Displays a bitmap picture loaded in the SPI Flash.\r
+* Input : - BmpAddress: Bmp picture address in the SPI Flash.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DrawBMP(u32 BmpAddress)\r
+{\r
+ u32 i = 0;\r
+\r
+ LCD_WriteReg(R1, 0xD0);\r
+ LCD_WriteReg(R5, 0x04);\r
+\r
+ LCD_SetCursor(239, 0x013F);\r
+\r
+ SPI_FLASH_StartReadSequence(BmpAddress);\r
+\r
+ /* Disable SPI1 */\r
+ SPI_Cmd(SPI1, DISABLE);\r
+ /* SPI in 16-bit mode */\r
+ SPI_DataSizeConfig(SPI1, SPI_DataSize_16b);\r
+ /* Enable SPI1 */\r
+ SPI_Cmd(SPI1, ENABLE);\r
+\r
+ for(i = 0; i < 76800; i++)\r
+ {\r
+ LCD_WriteRAM(__REV_HalfWord(SPI_FLASH_SendHalfWord(0xA5A5)));\r
+ }\r
+\r
+ /* Deselect the FLASH: Chip Select high */\r
+ SPI_FLASH_ChipSelect(1);\r
+\r
+ /* Disable SPI1 */\r
+ SPI_Cmd(SPI1, DISABLE);\r
+ /* SPI in 8-bit mode */\r
+ SPI_DataSizeConfig(SPI1, SPI_DataSize_8b);\r
+ /* Enable SPI1 */\r
+ SPI_Cmd(SPI1, ENABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_WriteReg\r
+* Description : Writes to the selected LCD register.\r
+* Input : - LCD_Reg: address of the selected register.\r
+* - LCD_RegValue: value to write to the selected register.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_WriteReg(u8 LCD_Reg, u8 LCD_RegValue)\r
+{\r
+ u16 tmp = 0;\r
+\r
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);\r
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET);\r
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);\r
+\r
+ tmp = LCD_Reg << 8;\r
+ tmp |= LCD_RegValue;\r
+\r
+ SPI_SendData(SPI2, tmp);\r
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)\r
+ {\r
+ }\r
+\r
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_ReadReg\r
+* Description : Reads the selected LCD Register.\r
+* Input : None\r
+* Output : None\r
+* Return : LCD Register Value.\r
+*******************************************************************************/\r
+u8 LCD_ReadReg(u8 LCD_Reg)\r
+{\r
+ u16 tmp = 0;\r
+\r
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);\r
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_RESET);\r
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);\r
+\r
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)\r
+ {\r
+ }\r
+ SPI_SendData(SPI2, LCD_Reg);\r
+\r
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET);\r
+\r
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)\r
+ {\r
+ }\r
+ SPI_SendData(SPI2, 0xFF);\r
+\r
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)== RESET)\r
+ {\r
+ }\r
+ tmp = SPI_ReceiveData(SPI2);\r
+\r
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);\r
+ return tmp;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_WriteRAM\r
+* Description : Writes to the LCD RAM.\r
+* Input : - RGB_Code: the pixel color in RGB mode (5-6-5).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_WriteRAM(u16 RGB_Code)\r
+{\r
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_RESET);\r
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET);\r
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);\r
+\r
+ SPI_SendData(SPI2, RGB_Code);\r
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)\r
+ {\r
+ }\r
+\r
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_ReadRAM\r
+* Description : Reads the LCD RAM.\r
+* Input : None\r
+* Output : None\r
+* Return : LCD RAM Value.\r
+*******************************************************************************/\r
+u16 LCD_ReadRAM(void)\r
+{\r
+ u16 tmp = 0;\r
+\r
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_NWR, Bit_SET);\r
+ LCD_CtrlLinesWrite(GPIOD, CtrlPin_RS, Bit_SET);\r
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_RESET);\r
+\r
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)\r
+ {\r
+ }\r
+ SPI_SendData(SPI2, 0xFF);\r
+ while(SPI_GetFlagStatus(SPI2, SPI_FLAG_RXNE)==RESET)\r
+ {\r
+ }\r
+ tmp = SPI_ReceiveData(SPI2);\r
+\r
+ LCD_CtrlLinesWrite(GPIOB, CtrlPin_NCS, Bit_SET);\r
+\r
+ return tmp;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_PowerOn\r
+* Description :\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_PowerOn(void)\r
+{\r
+ /* Power On Set */\r
+ LCD_WriteReg(R28, 0x73);\r
+ LCD_WriteReg(R36, 0x74);\r
+ LCD_WriteReg(R30, 0x01);\r
+ LCD_WriteReg(R24, 0xC1);\r
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */\r
+ LCD_WriteReg(R24, 0xE1);\r
+ LCD_WriteReg(R24, 0xF1);\r
+ vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */\r
+ LCD_WriteReg(R24, 0xF5);\r
+ vTaskDelay( 60 / portTICK_RATE_MS ); /* Delay 60 ms */\r
+ LCD_WriteReg(R27, 0x09);\r
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */\r
+ LCD_WriteReg(R31, 0x11);\r
+ LCD_WriteReg(R32, 0x0E);\r
+ LCD_WriteReg(R30, 0x81);\r
+ vTaskDelay( 10 / portTICK_RATE_MS ); /* Delay 10 ms */\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DisplayOn\r
+* Description : Enables the Display.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DisplayOn(void)\r
+{\r
+ LCD_WriteReg(R1, 0x50);\r
+ LCD_WriteReg(R5, 0x04);\r
+\r
+ /* Display On */\r
+ LCD_WriteReg(R0, 0x80);\r
+ LCD_WriteReg(R59, 0x01);\r
+ vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */\r
+ LCD_WriteReg(R0, 0x20);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_DisplayOff\r
+* Description : Disables the Display.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_DisplayOff(void)\r
+{\r
+ /* Display Off */\r
+ LCD_WriteReg(R0, 0xA0);\r
+ vTaskDelay( 40 / portTICK_RATE_MS ); /* Delay 40 ms */\r
+ LCD_WriteReg(R59, 0x00);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_CtrlLinesConfig\r
+* Description : Configures LCD control lines in Output Push-Pull mode.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_CtrlLinesConfig(void)\r
+{\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+ /* Configure NCS (PB.02) in Output Push-Pull mode */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;\r
+ GPIO_Init(GPIOB, &GPIO_InitStructure);\r
+\r
+ /* Configure NWR(RNW), RS (PD.15, PD.07) in Output Push-Pull mode */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_15;\r
+ GPIO_Init(GPIOD, &GPIO_InitStructure);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_CtrlLinesWrite\r
+* Description : Sets or reset LCD control lines.\r
+* Input : - GPIOx: where x can be B or D to select the GPIO peripheral.\r
+* - CtrlPins: the Control line. This parameter can be:\r
+* - CtrlPin_NCS: Chip Select pin (PB.02)\r
+* - CtrlPin_NWR: Read/Write Selection pin (PD.15)\r
+* - CtrlPin_RS: Register/RAM Selection pin (PD.07)\r
+* - BitVal: specifies the value to be written to the selected bit.\r
+* This parameter can be:\r
+* - Bit_RESET: to clear the port pin\r
+* - Bit_SET: to set the port pin\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u16 CtrlPins, BitAction BitVal)\r
+{\r
+ /* Set or Reset the control line */\r
+ GPIO_WriteBit(GPIOx, CtrlPins, BitVal);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : LCD_SPIConfig\r
+* Description : Configures the SPI2 interface.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void LCD_SPIConfig(void)\r
+{\r
+ SPI_InitTypeDef SPI_InitStructure;\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+ /* Enable GPIOA clock */\r
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);\r
+\r
+ /* Enable SPI2 clock */\r
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+\r
+ /* Configure SPI2 pins: NSS, SCK, MISO and MOSI */\r
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;\r
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\r
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;\r
+ GPIO_Init(GPIOB, &GPIO_InitStructure);\r
+\r
+ /* SPI2 Config */\r
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+ SPI_InitStructure.SPI_Mode = SPI_Mode_Master;\r
+ SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;\r
+ SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;\r
+ SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;\r
+ SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;\r
+ SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;\r
+ SPI_Init(SPI2, &SPI_InitStructure);\r
+\r
+ /* SPI2 enable */\r
+ SPI_Cmd(SPI2, ENABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : StrLength\r
+* Description : Returns length of string.\r
+* Input : - Str: Character Pointer.\r
+* Output : None\r
+* Return : String length.\r
+*******************************************************************************/\r
+static u32 StrLength(u8 *Str)\r
+{\r
+ u32 Index = 0;\r
+\r
+ /* Increment the Index unless the end of string */\r
+ for(Index = 0; *Str != '\0'; Str++, Index++)\r
+ {\r
+ }\r
+\r
+ return Index;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_adc.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the ADC firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_adc.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ADC ADON mask */\r
+#define CR2_ADON_Set ((u32)0x00000001)\r
+#define CR2_ADON_Reset ((u32)0xFFFFFFFE)\r
+\r
+/* ADC DMA mask */\r
+#define CR2_DMA_Set ((u16)0x0100)\r
+#define CR2_DMA_Reset ((u16)0xFEFF)\r
+\r
+/* ADC RSTCAL mask */\r
+#define CR2_RSTCAL_Set ((u16)0x0008)\r
+\r
+/* ADC CAL mask */\r
+#define CR2_CAL_Set ((u16)0x0004)\r
+\r
+/* ADC SWSTRT mask */\r
+#define CR2_SWSTRT_Set ((u32)0x00400000)\r
+\r
+/* ADC DISCNUM mask */\r
+#define CR1_DISCNUM_Reset ((u32)0xFFFF1FFF)\r
+\r
+/* ADC DISCEN mask */\r
+#define CR1_DISCEN_Set ((u32)0x00000800)\r
+#define CR1_DISCEN_Reset ((u32)0xFFFFF7FF)\r
+\r
+/* ADC EXTTRIG mask */\r
+#define CR2_EXTTRIG_Set ((u32)0x00100000)\r
+#define CR2_EXTTRIG_Reset ((u32)0xFFEFFFFF)\r
+\r
+/* ADC Software start mask */\r
+#define CR2_EXTTRIG_SWSTRT_Set ((u32)0x00500000)\r
+#define CR2_EXTTRIG_SWSTRT_Reset ((u32)0xFFAFFFFF)\r
+\r
+/* ADC JAUTO mask */\r
+#define CR1_JAUTO_Set ((u32)0x00000400)\r
+#define CR1_JAUTO_Reset ((u32)0xFFFFFBFF)\r
+\r
+/* ADC JDISCEN mask */\r
+#define CR1_JDISCEN_Set ((u32)0x00001000)\r
+#define CR1_JDISCEN_Reset ((u32)0xFFFFEFFF)\r
+\r
+/* ADC JEXTSEL mask */\r
+#define CR2_JEXTSEL_Reset ((u32)0xFFFF8FFF)\r
+\r
+/* ADC JEXTTRIG mask */\r
+#define CR2_JEXTTRIG_Set ((u32)0x00008000)\r
+#define CR2_JEXTTRIG_Reset ((u32)0xFFFF7FFF)\r
+\r
+/* ADC JSWSTRT mask */\r
+#define CR2_JSWSTRT_Set ((u32)0x00200000)\r
+\r
+/* ADC injected software start mask */\r
+#define CR2_JEXTTRIG_JSWSTRT_Set ((u32)0x00208000)\r
+#define CR2_JEXTTRIG_JSWSTRT_Reset ((u32)0xFFDF7FFF)\r
+\r
+/* ADC AWDCH mask */\r
+#define CR1_AWDCH_Reset ((u32)0xFFFFFFE0)\r
+\r
+/* ADC SQx mask */\r
+#define SQR3_SQ_Set ((u8)0x1F)\r
+#define SQR2_SQ_Set ((u8)0x1F)\r
+#define SQR1_SQ_Set ((u8)0x1F)\r
+\r
+/* ADC JSQx mask */\r
+#define JSQR_JSQ_Set ((u8)0x1F)\r
+\r
+/* ADC JL mask */\r
+#define JSQR_JL_Reset ((u32)0xFFCFFFFF)\r
+\r
+/* ADC SMPx mask */\r
+#define SMPR1_SMP_Set ((u8)0x07)\r
+#define SMPR2_SMP_Set ((u8)0x07)\r
+\r
+/* ADC Analog watchdog enable mode mask */\r
+#define CR1_AWDMode_Reset ((u32)0xFF3FFDFF)\r
+\r
+/* ADC TSPD mask */\r
+#define CR2_TSPD_Set ((u32)0x00800000)\r
+#define CR2_TSPD_Reset ((u32)0xFF7FFFFF)\r
+\r
+/* ADC JDRx registers= offset */\r
+#define JDR_Offset ((u8)0x28)\r
+\r
+/* ADC registers Masks */\r
+#define CR1_CLEAR_Mask ((u32)0xFFF0FEFF)\r
+#define CR2_CLEAR_Mask ((u32)0xFFF1F7FD)\r
+#define SQR1_CLEAR_Mask ((u32)0xFF0FFFFF)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_DeInit\r
+* Description : Deinitializes the ADCx peripheral registers to their default\r
+* reset values.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_DeInit(ADC_TypeDef* ADCx)\r
+{\r
+ switch (*(u32*)&ADCx)\r
+ {\r
+ case ADC1_BASE:\r
+ /* Enable ADC1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
+ /* Release ADC1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
+ break;\r
+ \r
+ case ADC2_BASE:\r
+ /* Enable ADC2 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);\r
+ /* Release ADC2 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_Init\r
+* Description : Initializes the ADCx according to the specified parameters\r
+* in the ADC_InitStruct.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_InitStruct: pointer to a ADC_InitTypeDef structure that\r
+* contains the configuration information for the specified\r
+* ADC peripheral.\r
+* Output : None\r
+* Return : None\r
+******************************************************************************/\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)\r
+{\r
+ u32 tmpreg1 = 0;\r
+ u8 tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));\r
+ assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r
+ assert(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); \r
+ assert(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r
+ assert(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r
+ assert(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));\r
+\r
+ /*---------------------------- ADCx CR1 Configuration -----------------*/\r
+ /* Get the ADCx CR1 value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear DUALMODE and SCAN bits */\r
+ tmpreg1 &= CR1_CLEAR_Mask;\r
+ /* Configure ADCx: Dual mode and scan conversion mode */\r
+ /* Set DUALMODE bits according to ADC_Mode value */\r
+ /* Set SCAN bit according to ADC_ScanConvMode value */\r
+ tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8));\r
+ /* Write to ADCx CR1 */\r
+ ADCx->CR1 = tmpreg1;\r
+\r
+ /*---------------------------- ADCx CR2 Configuration -----------------*/\r
+ /* Get the ADCx CR2 value */\r
+ tmpreg1 = ADCx->CR2;\r
+ /* Clear CONT, ALIGN and EXTTRIG bits */\r
+ tmpreg1 &= CR2_CLEAR_Mask;\r
+ /* Configure ADCx: external trigger event and continuous conversion mode */\r
+ /* Set ALIGN bit according to ADC_DataAlign value */\r
+ /* Set EXTTRIG bits according to ADC_ExternalTrigConv value */\r
+ /* Set CONT bit according to ADC_ContinuousConvMode value */\r
+ tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |\r
+ ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r
+ /* Write to ADCx CR2 */\r
+ ADCx->CR2 = tmpreg1;\r
+\r
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/\r
+ /* Get the ADCx SQR1 value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Clear L bits */\r
+ tmpreg1 &= SQR1_CLEAR_Mask;\r
+ /* Configure ADCx: regular channel sequence length */\r
+ /* Set L bits according to ADC_NbrOfChannel value */\r
+ tmpreg2 |= (ADC_InitStruct->ADC_NbrOfChannel - 1);\r
+ tmpreg1 |= ((u32)tmpreg2 << 20);\r
+ /* Write to ADCx SQR1 */\r
+ ADCx->SQR1 = tmpreg1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_StructInit\r
+* Description : Fills each ADC_InitStruct member with its default value.\r
+* Input : ADC_InitStruct : pointer to a ADC_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)\r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Mode member */\r
+ ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;\r
+\r
+ /* initialize the ADC_ScanConvMode member */\r
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r
+\r
+ /* Initialize the ADC_ContinuousConvMode member */\r
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
+\r
+ /* Initialize the ADC_ExternalTrigConv member */\r
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;\r
+\r
+ /* Initialize the ADC_DataAlign member */\r
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
+\r
+ /* Initialize the ADC_NbrOfChannel member */\r
+ ADC_InitStruct->ADC_NbrOfChannel = 1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_Cmd\r
+* Description : Enables or disables the specified ADC peripheral.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - NewState: new state of the ADCx peripheral. This parameter\r
+* can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ADON bit to wake up the ADC from power down mode */\r
+ ADCx->CR2 |= CR2_ADON_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC peripheral */\r
+ ADCx->CR2 &= CR2_ADON_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_DMACmd\r
+* Description : Enables or disables the specified ADC DMA request.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - NewState: new state of the selected ADC DMA transfer.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request */\r
+ ADCx->CR2 |= CR2_DMA_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request */\r
+ ADCx->CR2 &= CR2_DMA_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_ITConfig\r
+* Description : Enables or disables the specified ADC interrupts.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_IT: specifies the ADC interrupts sources to be enabled\r
+* or disabled. \r
+* This parameter can be any combination of the following values:\r
+* - ADC_IT_EOC: End of conversion interrupt mask\r
+* - ADC_IT_AWD: Analog watchdog interrupt mask\r
+* - ADC_IT_JEOC: End of injected conversion interrupt mask\r
+* - NewState: new state of the specified ADC interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState)\r
+{\r
+ u8 itmask = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ assert(IS_ADC_IT(ADC_IT));\r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (u8)ADC_IT;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC interrupts */\r
+ ADCx->CR1 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC interrupts */\r
+ ADCx->CR1 &= (~(u32)itmask);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_ResetCalibration\r
+* Description : Resets the ADC calibration registers.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)\r
+{\r
+ /* Resets the selected ADC calibartion registers */ \r
+ ADCx->CR2 |= CR2_RSTCAL_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetResetCalibrationStatus\r
+* Description : Gets the ADC reset calibration registers status.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* Output : None\r
+* Return : The new state of ADC Reset Calibration registers (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the status of RSTCAL bit */\r
+ if ((ADCx->CR2 & CR2_RSTCAL_Set) != (u16)RESET)\r
+ {\r
+ /* RSTCAL bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* RSTCAL bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the RSTCAL bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_StartCalibration\r
+* Description : Starts the calibration process.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_StartCalibration(ADC_TypeDef* ADCx)\r
+{\r
+ /* Enable the selected ADC calibration process */ \r
+ ADCx->CR2 |= CR2_CAL_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetCalibrationStatus\r
+* Description : Gets the ADC calibration status.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* Output : None\r
+* Return : The new state of ADC calibration (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the status of CAL bit */\r
+ if ((ADCx->CR2 & CR2_CAL_Set) != (u16)RESET)\r
+ {\r
+ /* CAL bit is set: calibration on going */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAL bit is reset: end of calibration */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the CAL bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_SoftwareStartConvCmd\r
+* Description : Enables or disables the ADC software start conversion .\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - NewState: new state of the selected ADC software start conversion.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC conversion on external event */\r
+ /* Starts the selected ADC conversion */\r
+ ADCx->CR2 |= CR2_EXTTRIG_SWSTRT_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Stops the selected ADC conversion */\r
+ /* Disable the selected ADC conversion on external event */\r
+ ADCx->CR2 &= CR2_EXTTRIG_SWSTRT_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetSoftwareStartConvStatus\r
+* Description : Gets the ADC Software start conversion Status.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* Output : None\r
+* Return : The new state of ADC software start conversion (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the status of SWSTRT bit */\r
+ if ((ADCx->CR2 & CR2_SWSTRT_Set) != (u32)RESET)\r
+ {\r
+ /* SWSTRT bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SWSTRT bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SWSTRT bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_DiscModeChannelCountConfig\r
+* Description : Configures the discontinuous mode for the selected ADC regular\r
+* group channel.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - Number: specifies the discontinuous mode regular channel\r
+* count value. This mumber must be between 1 and 8.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number)\r
+{\r
+ u32 tmpreg1 = 0;\r
+ u8 tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_ADC_REGULAR_DISC_NUMBER(Number));\r
+\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear the old discontinuous mode channel count */\r
+ tmpreg1 &= CR1_DISCNUM_Reset;\r
+ /* Set the discontinuous mode channel count */\r
+ tmpreg2 = Number - 1;\r
+ tmpreg1 |= ((u32)tmpreg2 << 13);\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_DiscModeCmd\r
+* Description : Enables or disables the discontinuous mode on regular group\r
+* channel for the specified ADC\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - NewState: new state of the selected ADC discontinuous mode\r
+* on regular group channel.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 |= CR1_DISCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 &= CR1_DISCEN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_RegularChannelConfig\r
+* Description : Configures for the selected ADC regular channel its corresponding\r
+* rank in the sequencer and its sample time.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_Channel: the ADC channel to configure. \r
+* This parameter can be one of the following values:\r
+* - ADC_Channel_0: ADC Channel0 selected\r
+* - ADC_Channel_1: ADC Channel1 selected\r
+* - ADC_Channel_2: ADC Channel2 selected\r
+* - ADC_Channel_3: ADC Channel3 selected\r
+* - ADC_Channel_4: ADC Channel4 selected\r
+* - ADC_Channel_5: ADC Channel5 selected\r
+* - ADC_Channel_6: ADC Channel6 selected\r
+* - ADC_Channel_7: ADC Channel7 selected\r
+* - ADC_Channel_8: ADC Channel8 selected\r
+* - ADC_Channel_9: ADC Channel9 selected\r
+* - ADC_Channel_10: ADC Channel10 selected\r
+* - ADC_Channel_11: ADC Channel11 selected\r
+* - ADC_Channel_12: ADC Channel12 selected\r
+* - ADC_Channel_13: ADC Channel13 selected\r
+* - ADC_Channel_14: ADC Channel14 selected\r
+* - ADC_Channel_15: ADC Channel15 selected\r
+* - ADC_Channel_16: ADC Channel16 selected\r
+* - ADC_Channel_17: ADC Channel17 selected\r
+* - Rank: The rank in the regular group sequencer. This parameter\r
+* must be between 1 to 16.\r
+* - ADC_SampleTime: The sample time value to be set for the\r
+* selected channel. \r
+* This parameter can be one of the following values:\r
+* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles\r
+* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles\r
+* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles\r
+* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles \r
+* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles \r
+* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles \r
+* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles \r
+* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles \r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)\r
+{\r
+ u32 tmpreg1 = 0, tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert(IS_ADC_REGULAR_RANK(Rank));\r
+ assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+\r
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */\r
+ if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = (u32)SMPR1_SMP_Set << (3 * (ADC_Channel - 10));\r
+ /* Clear the old discontinuous mode channel count */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
+ /* Set the discontinuous mode channel count */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);\r
+ /* Clear the old discontinuous mode channel count */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the discontinuous mode channel count */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ /* For Rank 1 to 6 */\r
+ if (Rank < 7)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = (u32)SQR3_SQ_Set << (5 * (Rank - 1));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR3 = tmpreg1;\r
+ }\r
+ /* For Rank 7 to 12 */\r
+ else if (Rank < 13)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = (u32)SQR2_SQ_Set << (5 * (Rank - 7));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR2 = tmpreg1;\r
+ }\r
+ /* For Rank 13 to 16 */\r
+ else\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = (u32)SQR1_SQ_Set << (5 * (Rank - 13));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 13));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR1 = tmpreg1;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_ExternalTrigConvCmd\r
+* Description : Enables or disables the ADCx conversion through external trigger.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - NewState: new state of the selected ADC external trigger\r
+* start of conversion.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC conversion on external event */\r
+ ADCx->CR2 |= CR2_EXTTRIG_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC conversion on external event */\r
+ ADCx->CR2 &= CR2_EXTTRIG_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetConversionValue\r
+* Description : Returns the last ADC conversion result data for regular channel.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* Output : None\r
+* Return : The Data conversion value.\r
+*******************************************************************************/\r
+u16 ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
+{\r
+ /* Return the selected ADC conversion value */\r
+ return (u16) ADCx->DR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetDualModeConversionValue\r
+* Description : Returns the last ADCs conversion result data in dual mode.\r
+* Output : None\r
+* Return : The Data conversion value.\r
+*******************************************************************************/\r
+u32 ADC_GetDualModeConversionValue(void)\r
+{\r
+ /* Return the dual mode conversion value */\r
+ return ADC1->DR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_AutoInjectedConvCmd\r
+* Description : Enables or disables the automatic injected group conversion\r
+* after regular one.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - NewState: new state of the selected ADC auto injected\r
+* conversion\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 |= CR1_JAUTO_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 &= CR1_JAUTO_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_InjectedDiscModeCmd\r
+* Description : Enables or disables the discontinuous mode for injected group\r
+* channel for the specified ADC\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - NewState: new state of the selected ADC discontinuous mode\r
+* on injected group channel.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 |= CR1_JDISCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 &= CR1_JDISCEN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_ExternalTrigInjectedConvConfig\r
+* Description : Configures the external trigger for injected channels conversion.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_ExternalTrigInjecConv: specifies the ADC trigger to\r
+* start injected conversion. \r
+* This parameter can be one of the following values:\r
+* - ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event \r
+* selected\r
+* - ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture\r
+* compare4 selected\r
+* - ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event\r
+* selected\r
+* - ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture\r
+* compare1 selected\r
+* - ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture\r
+* compare4 selected\r
+* - ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event\r
+* selected \r
+* - ADC_ExternalTrigInjecConv_Ext_Interrupt15: External\r
+* interrupt 15 event selected\r
+* - ADC_ExternalTrigInjecConv_None: Injected conversion\r
+* started by software and not by external trigger\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old external event selection for injected group */\r
+ tmpreg &= CR2_JEXTSEL_Reset;\r
+ /* Set the external event selection for injected group */\r
+ tmpreg |= ADC_ExternalTrigInjecConv;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_ExternalTrigInjectedConvCmd\r
+* Description : Enables or disables the ADCx injected channels conversion\r
+* through external trigger\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - NewState: new state of the selected ADC external trigger\r
+* start of injected conversion.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC external event selection for injected group */\r
+ ADCx->CR2 |= CR2_JEXTTRIG_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC external event selection for injected group */\r
+ ADCx->CR2 &= CR2_JEXTTRIG_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_SoftwareStartInjectedConvCmd\r
+* Description : Enables or disables the start of the injected channels conversion.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - NewState: new state of the selected ADC software start\r
+* injected conversion.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC external event selection for injected group */\r
+ /* Starts the selected ADC injected conversion */\r
+ ADCx->CR2 |= CR2_JEXTTRIG_JSWSTRT_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Stops the selected ADC injected conversion */\r
+ /* Disable the selected ADC external event selection for injected group */\r
+ ADCx->CR2 &= CR2_JEXTTRIG_JSWSTRT_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetSoftwareStartInjectedConvCmdStatus\r
+* Description : Gets the ADC Software start injected conversion Status.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* Output : None\r
+* Return : The new state of ADC software start injected conversion (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the status of JSWSTRT bit */\r
+ if ((ADCx->CR2 & CR2_JSWSTRT_Set) != (u32)RESET)\r
+ {\r
+ /* JSWSTRT bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* JSWSTRT bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the JSWSTRT bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_InjectedChannelConfig\r
+* Description : Configures for the selected ADC injected channel its corresponding\r
+* rank in the sequencer and its sample time.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_Channel: the ADC channel to configure. \r
+* This parameter can be one of the following values:\r
+* - ADC_Channel_0: ADC Channel0 selected\r
+* - ADC_Channel_1: ADC Channel1 selected\r
+* - ADC_Channel_2: ADC Channel2 selected\r
+* - ADC_Channel_3: ADC Channel3 selected\r
+* - ADC_Channel_4: ADC Channel4 selected\r
+* - ADC_Channel_5: ADC Channel5 selected\r
+* - ADC_Channel_6: ADC Channel6 selected\r
+* - ADC_Channel_7: ADC Channel7 selected\r
+* - ADC_Channel_8: ADC Channel8 selected\r
+* - ADC_Channel_9: ADC Channel9 selected\r
+* - ADC_Channel_10: ADC Channel10 selected\r
+* - ADC_Channel_11: ADC Channel11 selected\r
+* - ADC_Channel_12: ADC Channel12 selected\r
+* - ADC_Channel_13: ADC Channel13 selected\r
+* - ADC_Channel_14: ADC Channel14 selected\r
+* - ADC_Channel_15: ADC Channel15 selected\r
+* - ADC_Channel_16: ADC Channel16 selected\r
+* - ADC_Channel_17: ADC Channel17 selected\r
+* - Rank: The rank in the injected group sequencer. This parameter\r
+* must be between 1 to 4.\r
+* - ADC_SampleTime: The sample time value to be set for the\r
+* selected channel. \r
+* This parameter can be one of the following values:\r
+* - ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles\r
+* - ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles\r
+* - ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles\r
+* - ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles \r
+* - ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles \r
+* - ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles \r
+* - ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles \r
+* - ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles \r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)\r
+{\r
+ u32 tmpreg1 = 0, tmpreg2 = 0;\r
+ u8 tmpreg3 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert(IS_ADC_INJECTED_RANK(Rank));\r
+ assert(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+\r
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */\r
+ if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = (u32)SMPR1_SMP_Set << (3*(ADC_Channel - 10));\r
+ /* Clear the old discontinuous mode channel count */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (u32)ADC_SampleTime << (3*(ADC_Channel - 10));\r
+ /* Set the discontinuous mode channel count */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = (u32)SMPR2_SMP_Set << (3 * ADC_Channel);\r
+ /* Clear the old discontinuous mode channel count */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the discontinuous mode channel count */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+\r
+ /* Rank configuration */\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Get JL value: Number = JL+1 */\r
+ tmpreg3 = (u8)((tmpreg1 & (u32)~JSQR_JL_Reset)>> 20);\r
+ /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */\r
+ tmpreg2 = (u32)JSQR_JSQ_Set << (5 * ((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Clear the old JSQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */\r
+ tmpreg2 = (u32)ADC_Channel << (5 * ((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Set the JSQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_InjectedSequencerLengthConfig\r
+* Description : Configures the sequencer for injected channels\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - Length: The sequencer length. \r
+* This parameter must be a number between 1 to 4.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length)\r
+{\r
+ u32 tmpreg1 = 0;\r
+ u8 tmpreg2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_ADC_INJECTED_LENGTH(Length));\r
+ \r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Clear the old injected sequnence lenght JL bits */\r
+ tmpreg1 &= JSQR_JL_Reset;\r
+ /* Set the injected sequnence lenght JL bits */\r
+ tmpreg2 = Length - 1; \r
+ tmpreg1 |= (u32)tmpreg2 << 20;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_SetInjectedOffset\r
+* Description : Set the injected channels conversion value offset\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_InjectedChannel: the ADC injected channel to set its\r
+* offset. \r
+* This parameter can be one of the following values:\r
+* - ADC_InjectedChannel_1: Injected Channel1 selected\r
+* - ADC_InjectedChannel_2: Injected Channel2 selected\r
+* - ADC_InjectedChannel_3: Injected Channel3 selected\r
+* - ADC_InjectedChannel_4: Injected Channel4 selected\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+ assert(IS_ADC_OFFSET(Offset)); \r
+\r
+ /* Set the selected injected channel data offset */\r
+ *((u32 *)((*(u32*)&ADCx) + ADC_InjectedChannel)) = (u32)Offset;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetInjectedConversionValue\r
+* Description : Returns the ADC conversion result data for the selected\r
+* injected channel\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_InjectedChannel: the converted ADC injected channel.\r
+* This parameter can be one of the following values:\r
+* - ADC_InjectedChannel_1: Injected Channel1 selected\r
+* - ADC_InjectedChannel_2: Injected Channel2 selected\r
+* - ADC_InjectedChannel_3: Injected Channel3 selected\r
+* - ADC_InjectedChannel_4: Injected Channel4 selected\r
+* Output : None\r
+* Return : The Data conversion value.\r
+*******************************************************************************/\r
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+\r
+ /* Returns the selected injected channel conversion data value */\r
+ return (u16) (*(u32*) (((*(u32*)&ADCx) + ADC_InjectedChannel + JDR_Offset)));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_AnalogWatchdogCmd\r
+* Description : Enables or disables the analog watchdog on single/all regular\r
+* or injected channels\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r
+* This parameter can be one of the following values:\r
+* - ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on\r
+* a single regular channel\r
+* - ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on\r
+* a single injected channel\r
+* - ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog \r
+* watchdog on a single regular or injected channel\r
+* - ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on\r
+* all regular channel\r
+* - ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on\r
+* all injected channel\r
+* - ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog\r
+* on all regular and injected channels\r
+* - ADC_AnalogWatchdog_None: No channel guarded by the\r
+* analog watchdog\r
+* Output : None\r
+* Return : None \r
+*******************************************************************************/\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */\r
+ tmpreg &= CR1_AWDMode_Reset;\r
+ /* Set the analog watchdog enable mode */\r
+ tmpreg |= ADC_AnalogWatchdog;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_AnalogWatchdogThresholdsConfig\r
+* Description : Configures the High and low thresholds of the analog watchdog.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - HighThreshold: the ADC analog watchdog High threshold value.\r
+* This parameter must be a 12bit value.\r
+* - LowThreshold: the ADC analog watchdog Low threshold value.\r
+* This parameter must be a 12bit value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold,\r
+ u16 LowThreshold)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_ADC_THRESHOLD(HighThreshold));\r
+ assert(IS_ADC_THRESHOLD(LowThreshold));\r
+\r
+ /* Set the ADCx high threshold */\r
+ ADCx->HTR = HighThreshold;\r
+ /* Set the ADCx low threshold */\r
+ ADCx->LTR = LowThreshold;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_AnalogWatchdogSingleChannelConfig\r
+* Description : Configures the analog watchdog guarded single channel\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_Channel: the ADC channel to configure for the analog\r
+* watchdog. \r
+* This parameter can be one of the following values:\r
+* - ADC_Channel_0: ADC Channel0 selected\r
+* - ADC_Channel_1: ADC Channel1 selected\r
+* - ADC_Channel_2: ADC Channel2 selected\r
+* - ADC_Channel_3: ADC Channel3 selected\r
+* - ADC_Channel_4: ADC Channel4 selected\r
+* - ADC_Channel_5: ADC Channel5 selected\r
+* - ADC_Channel_6: ADC Channel6 selected\r
+* - ADC_Channel_7: ADC Channel7 selected\r
+* - ADC_Channel_8: ADC Channel8 selected\r
+* - ADC_Channel_9: ADC Channel9 selected\r
+* - ADC_Channel_10: ADC Channel10 selected\r
+* - ADC_Channel_11: ADC Channel11 selected\r
+* - ADC_Channel_12: ADC Channel12 selected\r
+* - ADC_Channel_13: ADC Channel13 selected\r
+* - ADC_Channel_14: ADC Channel14 selected\r
+* - ADC_Channel_15: ADC Channel15 selected\r
+* - ADC_Channel_16: ADC Channel16 selected\r
+* - ADC_Channel_17: ADC Channel17 selected\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_ADC_CHANNEL(ADC_Channel));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear the Analog watchdog channel select bits */\r
+ tmpreg &= CR1_AWDCH_Reset;\r
+ /* Set the Analog watchdog channel */\r
+ tmpreg |= ADC_Channel;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_TempSensorCmd\r
+* Description : Enables or disables the temperature sensor.\r
+* Input : - NewState: new state of the temperature sensor.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_TempSensorCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the temperature sensor */\r
+ ADC1->CR2 |= CR2_TSPD_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the temperature sensor */\r
+ ADC1->CR2 &= CR2_TSPD_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetFlagStatus\r
+* Description : Checks whether the specified ADC flag is set or not.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_FLAG: specifies the flag to check. \r
+* This parameter can be one of the following values:\r
+* - ADC_FLAG_AWD: Analog watchdog flag\r
+* - ADC_FLAG_EOC: End of conversion flag\r
+* - ADC_FLAG_JEOC: End of injected group conversion flag\r
+* - ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+* - ADC_FLAG_STRT: Start of regular group conversion flag\r
+* Output : None\r
+* Return : The new state of ADC_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_ADC_GET_FLAG(ADC_FLAG));\r
+\r
+ /* Check the status of the specified ADC flag */\r
+ if ((ADCx->SR & ADC_FLAG) != (u8)RESET)\r
+ {\r
+ /* ADC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_ClearFlag\r
+* Description : Clears the ADCx's pending flags.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_FLAG: specifies the flag to clear. \r
+* This parameter can be any combination of the following values:\r
+* - ADC_FLAG_AWD: Analog watchdog flag\r
+* - ADC_FLAG_EOC: End of conversion flag\r
+* - ADC_FLAG_JEOC: End of injected group conversion flag\r
+* - ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+* - ADC_FLAG_STRT: Start of regular group conversion flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
+\r
+ /* Clear the selected ADC flags */\r
+ ADCx->SR &= ~(u32)ADC_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_GetITStatus\r
+* Description : Checks whether the specified ADC interrupt has occurred or not.\r
+* Input : - ADCx: where x can be 1 or 2 to select the ADC peripheral.\r
+* - ADC_IT: specifies the ADC interrupt source to check. \r
+* This parameter can be one of the following values:\r
+* - ADC_IT_EOC: End of conversion interrupt mask\r
+* - ADC_IT_AWD: Analog watchdog interrupt mask\r
+* - ADC_IT_JEOC: End of injected conversion interrupt mask\r
+* Output : None\r
+* Return : The new state of ADC_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ u8 itmask = 0, enablestatus;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_ADC_GET_IT(ADC_IT));\r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (u8)(ADC_IT >> 8);\r
+\r
+ /* Get the ADC_IT enable bit status */\r
+ enablestatus = (ADCx->CR1 & (u8)ADC_IT) ;\r
+\r
+ /* Check the status of the specified ADC interrupt */\r
+ if (((ADCx->SR & itmask) != (u8)RESET) && enablestatus)\r
+ {\r
+ /* ADC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ADC_ClearITPendingBit\r
+* Description : Clears the ADC\92s interrupt pending bits.\r
+* Input : - ADC_IT: specifies the ADC interrupt pending bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - ADC_IT_EOC: End of conversion interrupt mask\r
+* - ADC_IT_AWD: Analog watchdog interrupt mask\r
+* - ADC_IT_JEOC: End of injected conversion interrupt mask\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT)\r
+{\r
+ u8 itmask = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_ADC_IT(ADC_IT));\r
+\r
+ /* Get the ADC IT index */\r
+ itmask = (u8)(ADC_IT >> 8);\r
+\r
+ /* Clear the selected ADC interrupt pending bits */\r
+ ADCx->SR &= ~(u32)itmask;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_bkp.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the BKP firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_bkp.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ------------ BKP registers bit address in the alias region ----------- */\r
+#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)\r
+\r
+/* --- RTCCR Register ---*/\r
+/* Alias word address of CCO bit */\r
+#define RTCCR_OFFSET (BKP_OFFSET + 0x2C)\r
+#define CCO_BitNumber 0x07\r
+#define RTCCR_CCO_BB (PERIPH_BB_BASE + (RTCCR_OFFSET * 32) + (CCO_BitNumber * 4))\r
+\r
+/* --- CR Register ---*/\r
+/* Alias word address of TPAL bit */\r
+#define CR_OFFSET (BKP_OFFSET + 0x30)\r
+#define TPAL_BitNumber 0x01\r
+#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))\r
+\r
+/* Alias word address of TPE bit */\r
+#define TPE_BitNumber 0x00\r
+#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+/* Alias word address of TPIE bit */\r
+#define CSR_OFFSET (BKP_OFFSET + 0x34)\r
+#define TPIE_BitNumber 0x02\r
+#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))\r
+\r
+/* Alias word address of TIF bit */\r
+#define TIF_BitNumber 0x09\r
+#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))\r
+\r
+/* Alias word address of TEF bit */\r
+#define TEF_BitNumber 0x08\r
+#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))\r
+\r
+\r
+/* ---------------------- BKP registers bit mask ------------------------ */\r
+/* RTCCR register bit mask */\r
+#define RTCCR_CAL_Mask ((u16)0xFF80)\r
+\r
+/* CSR register bit mask */\r
+#define CSR_CTE_Set ((u16)0x0001)\r
+#define CSR_CTI_Set ((u16)0x0002)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_DeInit\r
+* Description : Deinitializes the BKP peripheral registers to their default\r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void BKP_DeInit(void)\r
+{\r
+ RCC_BackupResetCmd(ENABLE);\r
+ RCC_BackupResetCmd(DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_TamperPinLevelConfig\r
+* Description : Configures the Tamper Pin active level.\r
+* Input : - BKP_TamperPinLevel: specifies the Tamper Pin active level.\r
+* This parameter can be one of the following values:\r
+* - BKP_TamperPinLevel_High: Tamper pin active on high level\r
+* - BKP_TamperPinLevel_Low: Tamper pin active on low level\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void BKP_TamperPinLevelConfig(u16 BKP_TamperPinLevel)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));\r
+\r
+ *(vu32 *) CR_TPAL_BB = BKP_TamperPinLevel;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_TamperPinCmd\r
+* Description : Enables or disables the Tamper Pin activation.\r
+* Input : - NewState: new state of the Tamper Pin activation.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void BKP_TamperPinCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CR_TPE_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_ITConfig\r
+* Description : Enables or disables the Tamper Pin Interrupt.\r
+* Input : - NewState: new state of the Tamper Pin Interrupt.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void BKP_ITConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CSR_TPIE_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_RTCCalibrationClockOutputCmd\r
+* Description : Enables or disables the output of the Calibration Clock.\r
+* Input : - NewState: new state of the Calibration Clock output.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void BKP_RTCCalibrationClockOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) RTCCR_CCO_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_SetRTCCalibrationValue\r
+* Description : Sets RTC Clock Calibration value.\r
+* Input : - CalibrationValue: specifies the RTC Clock Calibration value.\r
+* This parameter must be a number between 0 and 0x7F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void BKP_SetRTCCalibrationValue(u8 CalibrationValue)\r
+{\r
+ u16 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_BKP_CALIBRATION_VALUE(CalibrationValue));\r
+\r
+ tmpreg = BKP->RTCCR;\r
+\r
+ /* Clear CAL[6:0] bits */\r
+ tmpreg &= RTCCR_CAL_Mask;\r
+\r
+ /* Set CAL[6:0] bits according to CalibrationValue value */\r
+ tmpreg |= CalibrationValue;\r
+\r
+ /* Store the new value */\r
+ BKP->RTCCR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_WriteBackupRegister\r
+* Description : Writes user data to the specified Data Backup Register.\r
+* Input : - BKP_DR: specifies the Data Backup Register.\r
+* This parameter can be BKP_DRx where x:[1, 10]\r
+* - Data: data to write\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void BKP_WriteBackupRegister(u16 BKP_DR, u16 Data)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_BKP_DR(BKP_DR));\r
+\r
+ *(vu16 *) (BKP_BASE + BKP_DR) = Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_ReadBackupRegister\r
+* Description : Reads data from the specified Data Backup Register.\r
+* Input : - BKP_DR: specifies the Data Backup Register.\r
+* This parameter can be BKP_DRx where x:[1, 10]\r
+* Output : None\r
+* Return : The content of the specified Data Backup Register\r
+*******************************************************************************/\r
+u16 BKP_ReadBackupRegister(u16 BKP_DR)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_BKP_DR(BKP_DR));\r
+\r
+ return (*(vu16 *) (BKP_BASE + BKP_DR));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_GetFlagStatus\r
+* Description : Checks whether the Tamper Pin Event flag is set or not.\r
+* Input : None\r
+* Output : None\r
+* Return : The new state of the Tamper Pin Event flag (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus BKP_GetFlagStatus(void)\r
+{\r
+ return (FlagStatus)(*(vu32 *) CSR_TEF_BB);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_ClearFlag\r
+* Description : Clears Tamper Pin Event pending flag.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void BKP_ClearFlag(void)\r
+{\r
+ /* Set CTE bit to clear Tamper Pin Event flag */\r
+ BKP->CSR |= CSR_CTE_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_GetITStatus\r
+* Description : Checks whether the Tamper Pin Interrupt has occurred or not.\r
+* Input : None\r
+* Output : None\r
+* Return : The new state of the Tamper Pin Interrupt (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus BKP_GetITStatus(void)\r
+{\r
+ return (ITStatus)(*(vu32 *) CSR_TIF_BB);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : BKP_ClearITPendingBit\r
+* Description : Clears Tamper Pin Interrupt pending bit.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void BKP_ClearITPendingBit(void)\r
+{\r
+ /* Set CTI bit to clear Tamper Pin Interrupt pending bit */\r
+ BKP->CSR |= CSR_CTI_Set;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_can.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the CAN firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_can.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* CAN Master Control Register bits */\r
+#define CAN_MCR_INRQ ((u32)0x00000001) /* Initialization request */\r
+#define CAN_MCR_SLEEP ((u32)0x00000002) /* Sleep mode request */\r
+#define CAN_MCR_TXFP ((u32)0x00000004) /* Transmit FIFO priority */\r
+#define CAN_MCR_RFLM ((u32)0x00000008) /* Receive FIFO locked mode */\r
+#define CAN_MCR_NART ((u32)0x00000010) /* No automatic retransmission */\r
+#define CAN_MCR_AWUM ((u32)0x00000020) /* Automatic wake up mode */\r
+#define CAN_MCR_ABOM ((u32)0x00000040) /* Automatic bus-off management */\r
+#define CAN_MCR_TTCM ((u32)0x00000080) /* time triggered communication */\r
+\r
+/* CAN Master Status Register bits */\r
+#define CAN_MSR_INAK ((u32)0x00000001) /* Initialization acknowledge */\r
+#define CAN_MSR_WKUI ((u32)0x00000008) /* Wake-up interrupt */\r
+#define CAN_MSR_SLAKI ((u32)0x00000010) /* Sleep acknowledge interrupt */\r
+\r
+/* CAN Transmit Status Register bits */\r
+#define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request completed mailbox0 */\r
+#define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of mailbox0 */\r
+#define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort request for mailbox0 */\r
+#define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request completed mailbox1 */\r
+#define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of mailbox1 */\r
+#define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort request for mailbox1 */\r
+#define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request completed mailbox2 */\r
+#define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of mailbox2 */\r
+#define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort request for mailbox2 */\r
+#define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit mailbox 0 empty */\r
+#define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit mailbox 1 empty */\r
+#define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit mailbox 2 empty */\r
+\r
+/* CAN Receive FIFO 0 Register bits */\r
+#define CAN_RF0R_FULL0 ((u32)0x00000008) /* FIFO 0 full */\r
+#define CAN_RF0R_FOVR0 ((u32)0x00000010) /* FIFO 0 overrun */\r
+#define CAN_RF0R_RFOM0 ((u32)0x00000020) /* Release FIFO 0 output mailbox */\r
+\r
+/* CAN Receive FIFO 1 Register bits */\r
+#define CAN_RF1R_FULL1 ((u32)0x00000008) /* FIFO 1 full */\r
+#define CAN_RF1R_FOVR1 ((u32)0x00000010) /* FIFO 1 overrun */\r
+#define CAN_RF1R_RFOM1 ((u32)0x00000020) /* Release FIFO 1 output mailbox */\r
+\r
+/* CAN Error Status Register bits */\r
+#define CAN_ESR_EWGF ((u32)0x00000001) /* Error warning flag */\r
+#define CAN_ESR_EPVF ((u32)0x00000002) /* Error passive flag */\r
+#define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-off flag */\r
+\r
+/* CAN Mailbox Transmit Request */\r
+#define CAN_TMIDxR_TXRQ ((u32)0x00000001) /* Transmit mailbox request */\r
+\r
+/* CAN Filter Master Register bits */\r
+#define CAN_FMR_FINIT ((u32)0x00000001) /* Filter init mode */\r
+\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/*******************************************************************************\r
+* Function Name : CAN_DeInit\r
+* Description : Deinitializes the CAN peripheral registers to their default\r
+* reset values.\r
+* Input : None.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_DeInit(void)\r
+{\r
+ /* Enable CAN reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE);\r
+ /* Release CAN from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_Init\r
+* Description : Initializes the CAN peripheral according to the specified\r
+* parameters in the CAN_InitStruct.\r
+* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that\r
+ contains the configuration information for the CAN peripheral.\r
+* Output : None.\r
+* Return : Constant indicates initialization succeed which will be \r
+* CANINITFAILED or CANINITOK.\r
+*******************************************************************************/\r
+u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+ u8 InitStatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));\r
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));\r
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));\r
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));\r
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));\r
+ assert(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));\r
+ assert(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));\r
+ assert(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));\r
+ assert(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));\r
+ assert(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));\r
+ assert(IS_CAN_CLOCK(CAN_InitStruct->CAN_Clock));\r
+ assert(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));\r
+\r
+ /* Request initialisation */\r
+ CAN->MCR = CAN_MCR_INRQ;\r
+\r
+ /* ...and check acknowledged */\r
+ if ((CAN->MSR & CAN_MSR_INAK) == 0)\r
+ {\r
+ InitStatus = CANINITFAILED;\r
+ }\r
+ else\r
+ {\r
+ /* Set the time triggered communication mode */\r
+ if (CAN_InitStruct->CAN_TTCM == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_TTCM;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_TTCM;\r
+ }\r
+\r
+ /* Set the automatic bus-off management */\r
+ if (CAN_InitStruct->CAN_ABOM == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_ABOM;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_ABOM;\r
+ }\r
+\r
+ /* Set the automatic wake-up mode */\r
+ if (CAN_InitStruct->CAN_AWUM == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_AWUM;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_AWUM;\r
+ }\r
+\r
+ /* Set the no automatic retransmission */\r
+ if (CAN_InitStruct->CAN_NART == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_NART;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_NART;\r
+ }\r
+\r
+ /* Set the receive FIFO locked mode */\r
+ if (CAN_InitStruct->CAN_RFLM == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_RFLM;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_RFLM;\r
+ }\r
+\r
+ /* Set the transmit FIFO priority */\r
+ if (CAN_InitStruct->CAN_TXFP == ENABLE)\r
+ {\r
+ CAN->MCR |= CAN_MCR_TXFP;\r
+ }\r
+ else\r
+ {\r
+ CAN->MCR &= ~CAN_MCR_TXFP;\r
+ }\r
+\r
+ /* Set the bit timing register */\r
+ CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) |\r
+ ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) |\r
+ ((u32)CAN_InitStruct->CAN_Clock << 15) | ((u32)CAN_InitStruct->CAN_Prescaler - 1);\r
+\r
+ InitStatus = CANINITOK;\r
+\r
+ /* Request leave initialisation */\r
+ CAN->MCR &= ~CAN_MCR_INRQ;\r
+\r
+ /* ...and check acknowledged */\r
+ if ((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CANINITFAILED;\r
+ }\r
+ }\r
+\r
+ /* At this step, return the status of initialization */\r
+ return InitStatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_FilterInit\r
+* Description : Initializes the CAN peripheral according to the specified\r
+* parameters in the CAN_FilterInitStruct.\r
+* Input : CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef\r
+* structure that contains the configuration information.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)\r
+{\r
+ u16 FilterNumber_BitPos = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));\r
+ assert(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));\r
+ assert(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));\r
+ assert(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));\r
+ assert(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));\r
+\r
+ FilterNumber_BitPos = (u16)((u16)0x0001 << ((u16)CAN_FilterInitStruct->CAN_FilterNumber));\r
+\r
+ /* Initialisation mode for the filter */\r
+ CAN->FMR |= CAN_FMR_FINIT;\r
+\r
+ /* Filter Deactivation */\r
+ CAN->FA0R &= ~(u32)FilterNumber_BitPos;\r
+\r
+ /* Filter Scale */\r
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)\r
+ {\r
+ /* 16-bit scale for the filter */\r
+ CAN->FS0R &= ~(u32)FilterNumber_BitPos;\r
+\r
+ /* First 16-bit identifier and First 16-bit mask */\r
+ /* Or First 16-bit identifier and Second 16-bit identifier */\r
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR0 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |\r
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);\r
+\r
+ /* Second 16-bit identifier and Second 16-bit mask */\r
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh);\r
+ }\r
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)\r
+ {\r
+ /* 32-bit scale for the filter */\r
+ CAN->FS0R |= FilterNumber_BitPos;\r
+\r
+ /* 32-bit identifier or First 32-bit identifier */\r
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR0 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |\r
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow);\r
+\r
+ /* 32-bit mask or Second 32-bit identifier */\r
+ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
+ ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow);\r
+\r
+ }\r
+\r
+ /* Filter Mode */\r
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)\r
+ {\r
+ /*Id/Mask mode for the filter*/\r
+ CAN->FM0R &= ~(u32)FilterNumber_BitPos;\r
+ }\r
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r
+ {\r
+ /*Identifier list mode for the filter*/\r
+ CAN->FM0R |= (u32)FilterNumber_BitPos;\r
+ }\r
+\r
+ /* Filter FIFO assignment */\r
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)\r
+ {\r
+ /* FIFO 0 assignation for the filter */\r
+ CAN->FFA0R &= ~(u32)FilterNumber_BitPos;\r
+ }\r
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)\r
+ {\r
+ /* FIFO 1 assignation for the filter */\r
+ CAN->FFA0R |= (u32)FilterNumber_BitPos;\r
+ }\r
+ \r
+ /* Filter activation */\r
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)\r
+ {\r
+ CAN->FA0R |= FilterNumber_BitPos;\r
+ }\r
+\r
+ /* Leave the initialisation mode for the filter */\r
+ CAN->FMR &= ~CAN_FMR_FINIT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_StructInit\r
+* Description : Fills each CAN_InitStruct member with its default value.\r
+* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure which\r
+* will be initialized.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+ /* Reset CAN init structure parameters values */\r
+\r
+ /* Initialize the time triggered communication mode */\r
+ CAN_InitStruct->CAN_TTCM = DISABLE;\r
+\r
+ /* Initialize the automatic bus-off management */\r
+ CAN_InitStruct->CAN_ABOM = DISABLE;\r
+\r
+ /* Initialize the automatic wake-up mode */\r
+ CAN_InitStruct->CAN_AWUM = DISABLE;\r
+\r
+ /* Initialize the no automatic retransmission */\r
+ CAN_InitStruct->CAN_NART = DISABLE;\r
+\r
+ /* Initialize the receive FIFO locked mode */\r
+ CAN_InitStruct->CAN_RFLM = DISABLE;\r
+\r
+ /* Initialize the transmit FIFO priority */\r
+ CAN_InitStruct->CAN_TXFP = DISABLE;\r
+\r
+ /* Initialize the CAN_Mode member */\r
+ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;\r
+\r
+ /* Initialize the CAN_SJW member */\r
+ CAN_InitStruct->CAN_SJW = CAN_SJW_0tq;\r
+\r
+ /* Initialize the CAN_BS1 member */\r
+ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;\r
+\r
+ /* Initialize the CAN_BS2 member */\r
+ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;\r
+\r
+ /* Initialize the CAN_Clock member */\r
+ CAN_InitStruct->CAN_Clock = CAN_Clock_APB;\r
+\r
+ /* Initialize the CAN_Prescaler member */\r
+ CAN_InitStruct->CAN_Prescaler = 1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_ITConfig\r
+* Description : Enables or disables the CAN interrupts.\r
+* Input : - CAN_IT: specifies the CAN interrupt sources to be enabled or\r
+* disabled.\r
+* - NewState: new state of the CAN interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_ITConfig(u32 CAN_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_CAN_IT(CAN_IT));\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected CAN interrupt */\r
+ CAN->IER |= CAN_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected CAN interrupt */\r
+ CAN->IER &= ~CAN_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_Transmit\r
+* Description : Initiates the transmission of a message.\r
+* Input : TxMessage: pointer to a structure which contains CAN Id, CAN\r
+* DLC and CAN datas.\r
+* Output : None.\r
+* Return : The number of the mailbox that is used for transmission\r
+* or CAN_NO_MB if there is no empty mailbox.\r
+*******************************************************************************/\r
+u8 CAN_Transmit(CanTxMsg* TxMessage)\r
+{\r
+ u8 TransmitMailbox = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_CAN_STDID(TxMessage->StdId));\r
+ assert(IS_CAN_EXTID(TxMessage->StdId));\r
+ assert(IS_CAN_IDTYPE(TxMessage->IDE));\r
+ assert(IS_CAN_RTR(TxMessage->RTR));\r
+ assert(IS_CAN_DLC(TxMessage->DLC));\r
+\r
+ /* Select one empty transmit mailbox */\r
+ if ((CAN->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r
+ {\r
+ TransmitMailbox = 0;\r
+ }\r
+ else if ((CAN->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r
+ {\r
+ TransmitMailbox = 1;\r
+ }\r
+ else if ((CAN->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)\r
+ {\r
+ TransmitMailbox = 2;\r
+ }\r
+ else\r
+ {\r
+ TransmitMailbox = CAN_NO_MB;\r
+ }\r
+\r
+ if (TransmitMailbox != CAN_NO_MB)\r
+ {\r
+ /* Set up the Id */\r
+ TxMessage->StdId &= (u32)0x000007FF;\r
+ TxMessage->StdId = TxMessage->StdId << 21;\r
+ TxMessage->ExtId &= (u32)0x0003FFFF;\r
+ TxMessage->ExtId <<= 3;\r
+\r
+ CAN->sTxMailBox[TransmitMailbox].TIR &= CAN_TMIDxR_TXRQ;\r
+ CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->StdId | TxMessage->ExtId |\r
+ TxMessage->IDE | TxMessage->RTR);\r
+\r
+ /* Set up the DLC */\r
+ TxMessage->DLC &= (u8)0x0000000F;\r
+ CAN->sTxMailBox[TransmitMailbox].TDTR &= (u32)0xFFFFFFF0;\r
+ CAN->sTxMailBox[TransmitMailbox].TDTR |= TxMessage->DLC;\r
+\r
+ /* Set up the data field */\r
+ CAN->sTxMailBox[TransmitMailbox].TDLR = (((u32)TxMessage->Data[3] << 24) | ((u32)TxMessage->Data[2] << 16) |\r
+ ((u32)TxMessage->Data[1] << 8) | ((u32)TxMessage->Data[0]));\r
+ CAN->sTxMailBox[TransmitMailbox].TDHR = (((u32)TxMessage->Data[7] << 24) | ((u32)TxMessage->Data[6] << 16) |\r
+ ((u32)TxMessage->Data[5] << 8) | ((u32)TxMessage->Data[4]));\r
+\r
+ /* Request transmission */\r
+ CAN->sTxMailBox[TransmitMailbox].TIR |= CAN_TMIDxR_TXRQ;\r
+ }\r
+\r
+ return TransmitMailbox;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_TransmitStatus\r
+* Description : Check the transmission of a message.\r
+* Input : TransmitMailbox: the number of the mailbox that is used for\r
+* transmission.\r
+* Output : None.\r
+* Return : CANTXOK if the CAN driver transmits the message, CANTXFAILED\r
+* in an other case.\r
+*******************************************************************************/\r
+u32 CAN_TransmitStatus(u8 TransmitMailbox)\r
+{\r
+ /* RQCP, TXOK and TME bits */\r
+ u32 State = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));\r
+\r
+ switch (TransmitMailbox)\r
+ {\r
+ case (0): State |= ((CAN->TSR & CAN_TSR_RQCP0) << 2);\r
+ State |= ((CAN->TSR & CAN_TSR_TXOK0) >> 0);\r
+ State |= ((CAN->TSR & CAN_TSR_TME0) >> 26);\r
+ break;\r
+ case (1): State |= ((CAN->TSR & CAN_TSR_RQCP1) >> 6);\r
+ State |= ((CAN->TSR & CAN_TSR_TXOK1) >> 8);\r
+ State |= ((CAN->TSR & CAN_TSR_TME1) >> 27);\r
+ break;\r
+ case (2): State |= ((CAN->TSR & CAN_TSR_RQCP2) >> 14);\r
+ State |= ((CAN->TSR & CAN_TSR_TXOK2) >> 16);\r
+ State |= ((CAN->TSR & CAN_TSR_TME2) >> 28);\r
+ break;\r
+ default:\r
+ State = CANTXFAILED;\r
+ break;\r
+ }\r
+\r
+ switch (State)\r
+ {\r
+ /* transmit pending */\r
+ case (0x0): State = CANTXPENDING;\r
+ break;\r
+ /* transmit failed */\r
+ case (0x5): State = CANTXFAILED;\r
+ break;\r
+ /* transmit succedeed */\r
+ case (0x7): State = CANTXOK;\r
+ break;\r
+ default:\r
+ State = CANTXFAILED;\r
+ break;\r
+ }\r
+\r
+ return State;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_CancelTransmit\r
+* Description : Cancels a transmit request.\r
+* Input : Mailbox number.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_CancelTransmit(u8 Mailbox)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_CAN_TRANSMITMAILBOX(Mailbox));\r
+\r
+ /* abort transmission */\r
+ switch (Mailbox)\r
+ {\r
+ case (0): CAN->TSR |= CAN_TSR_ABRQ0;\r
+ break;\r
+ case (1): CAN->TSR |= CAN_TSR_ABRQ1;\r
+ break;\r
+ case (2): CAN->TSR |= CAN_TSR_ABRQ2;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_FIFORelease\r
+* Description : Release a FIFO.\r
+* Input : FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_FIFORelease(u8 FIFONumber)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_CAN_FIFO(FIFONumber));\r
+\r
+ /* Release FIFO0 */\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ CAN->RF0R = CAN_RF0R_RFOM0;\r
+ }\r
+ /* Release FIFO1 */\r
+ else /* FIFONumber == CAN_FIFO1 */\r
+ {\r
+ CAN->RF1R = CAN_RF1R_RFOM1;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_MessagePending\r
+* Description : Return the number of pending messages.\r
+* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+* Output : None.\r
+* Return : NbMessage which is the number of pending message.\r
+*******************************************************************************/\r
+u8 CAN_MessagePending(u8 FIFONumber)\r
+{\r
+ u8 MessagePending=0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_CAN_FIFO(FIFONumber));\r
+\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ MessagePending = (u8)(CAN->RF0R&(u32)0x03);\r
+ }\r
+ else if (FIFONumber == CAN_FIFO1)\r
+ {\r
+ MessagePending = (u8)(CAN->RF1R&(u32)0x03);\r
+ }\r
+ else\r
+ {\r
+ MessagePending = 0;\r
+ }\r
+ return MessagePending;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_Receive\r
+* Description : Receives a message.\r
+* Input : FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+* Output : RxMessage: pointer to a structure which contains CAN Id,\r
+* CAN DLC, CAN datas and FMI number.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_Receive(u8 FIFONumber, CanRxMsg* RxMessage)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_CAN_FIFO(FIFONumber));\r
+\r
+ /* Get the Id */\r
+ RxMessage->StdId = (u32)0x000007FF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 21);\r
+ RxMessage->ExtId = (u32)0x0003FFFF & (CAN->sFIFOMailBox[FIFONumber].RIR >> 3);\r
+\r
+ RxMessage->IDE = (u32)0x00000004 & CAN->sFIFOMailBox[FIFONumber].RIR;\r
+ RxMessage->RTR = (u32)0x00000002 & CAN->sFIFOMailBox[FIFONumber].RIR;\r
+\r
+ /* Get the DLC */\r
+ RxMessage->DLC = (u32)0x0000000F & CAN->sFIFOMailBox[FIFONumber].RDTR;\r
+\r
+ /* Get the FMI */\r
+ RxMessage->FMI = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
+\r
+ /* Get the data field */\r
+ RxMessage->Data[0] = (u32)0x000000FF & CAN->sFIFOMailBox[FIFONumber].RDLR;\r
+ RxMessage->Data[1] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
+ RxMessage->Data[2] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
+ RxMessage->Data[3] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
+\r
+ RxMessage->Data[4] = (u32)0x000000FF & CAN->sFIFOMailBox[FIFONumber].RDHR;\r
+ RxMessage->Data[5] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
+ RxMessage->Data[6] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
+ RxMessage->Data[7] = (u32)0x000000FF & (CAN->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
+\r
+ /* Release the FIFO */\r
+ CAN_FIFORelease(FIFONumber);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_Sleep\r
+* Description : Enters the low power mode.\r
+* Input : None.\r
+* Output : None.\r
+* Return : CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.\r
+*******************************************************************************/\r
+u8 CAN_Sleep(void)\r
+{\r
+ u8 SleepStatus = 0;\r
+\r
+ /* Sleep mode entering request */\r
+ CAN->MCR |= CAN_MCR_SLEEP;\r
+ SleepStatus = CANSLEEPOK;\r
+\r
+ /* Sleep mode status */\r
+ if ((CAN->MCR&CAN_MCR_SLEEP) == 0)\r
+ {\r
+ /* Sleep mode not entered */\r
+ SleepStatus = CANSLEEPFAILED;\r
+ }\r
+\r
+ /* At this step, sleep mode status */\r
+ return SleepStatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_WakeUp\r
+* Description : Wakes the CAN up.\r
+* Input : None.\r
+* Output : None.\r
+* Return : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other\r
+* case.\r
+*******************************************************************************/\r
+u8 CAN_WakeUp(void)\r
+{\r
+ u8 WakeUpStatus = 0;\r
+\r
+ /* Wake up request */\r
+ CAN->MCR &= ~CAN_MCR_SLEEP;\r
+ WakeUpStatus = CANWAKEUPFAILED;\r
+\r
+ /* Sleep mode status */\r
+ if ((CAN->MCR&CAN_MCR_SLEEP) == 0)\r
+ {\r
+ /* Sleep mode exited */\r
+ WakeUpStatus = CANWAKEUPOK;\r
+ }\r
+\r
+ /* At this step, sleep mode status */\r
+ return WakeUpStatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_GetFlagStatus\r
+* Description : Checks whether the CAN flag is set or not.\r
+* Input : CAN_FLAG: specifies the flag to check.\r
+* Output : None.\r
+* Return : The new state of CAN_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus CAN_GetFlagStatus(u32 CAN_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_CAN_FLAG(CAN_FLAG));\r
+\r
+ /* Check the status of the specified CAN flag */\r
+ if ((CAN->ESR & CAN_FLAG) != (u32)RESET)\r
+ {\r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the CAN_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_ClearFlag\r
+* Description : Clears the CAN's pending flags.\r
+* Input : CAN_FLAG: specifies the flag to clear.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_ClearFlag(u32 CAN_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_CAN_FLAG(CAN_FLAG));\r
+\r
+ /* Clear the selected CAN flags */\r
+ CAN->ESR &= ~CAN_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_GetITStatus\r
+* Description : Checks whether the CAN interrupt has occurred or not.\r
+* Input : CAN_IT: specifies the CAN interrupt source to check.\r
+* Output : None.\r
+* Return : The new state of CAN_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus CAN_GetITStatus(u32 CAN_IT)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_CAN_IT(CAN_IT));\r
+\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_RQCP0:\r
+ pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP0);\r
+ break;\r
+ case CAN_IT_RQCP1:\r
+ pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP1);\r
+ break;\r
+ case CAN_IT_RQCP2:\r
+ pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP2);\r
+ break;\r
+ case CAN_IT_FF0:\r
+ pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FULL0);\r
+ break;\r
+ case CAN_IT_FOV0:\r
+ pendingbitstatus = CheckITStatus(CAN->RF0R, CAN_RF0R_FOVR0);\r
+ break;\r
+ case CAN_IT_FF1:\r
+ pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FULL1);\r
+ break;\r
+ case CAN_IT_FOV1:\r
+ pendingbitstatus = CheckITStatus(CAN->RF1R, CAN_RF1R_FOVR1);\r
+ break;\r
+ case CAN_IT_EWG:\r
+ pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EWGF);\r
+ break;\r
+ case CAN_IT_EPV:\r
+ pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_EPVF);\r
+ break;\r
+ case CAN_IT_BOF:\r
+ pendingbitstatus = CheckITStatus(CAN->ESR, CAN_ESR_BOFF);\r
+ break;\r
+ case CAN_IT_SLK:\r
+ pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_SLAKI);\r
+ break;\r
+ case CAN_IT_WKU:\r
+ pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_WKUI);\r
+ break;\r
+\r
+ default :\r
+ pendingbitstatus = RESET;\r
+ break;\r
+ }\r
+\r
+ /* Return the CAN_IT status */\r
+ return pendingbitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CAN_ClearITPendingBit\r
+* Description : Clears the CAN\92s interrupt pending bits.\r
+* Input : CAN_IT: specifies the interrupt pending bit to clear.\r
+* Output : None.\r
+* Return : None.\r
+*******************************************************************************/\r
+void CAN_ClearITPendingBit(u32 CAN_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_CAN_IT(CAN_IT));\r
+\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_RQCP0:\r
+ CAN->TSR = CAN_TSR_RQCP0; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_RQCP1:\r
+ CAN->TSR = CAN_TSR_RQCP1; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_RQCP2:\r
+ CAN->TSR = CAN_TSR_RQCP2; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FF0:\r
+ CAN->RF0R = CAN_RF0R_FULL0; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FOV0:\r
+ CAN->RF0R = CAN_RF0R_FOVR0; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FF1:\r
+ CAN->RF1R = CAN_RF1R_FULL1; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_FOV1:\r
+ CAN->RF1R = CAN_RF1R_FOVR1; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_EWG:\r
+ CAN->ESR &= ~ CAN_ESR_EWGF; /* rw */\r
+ break;\r
+ case CAN_IT_EPV:\r
+ CAN->ESR &= ~ CAN_ESR_EPVF; /* rw */\r
+ break;\r
+ case CAN_IT_BOF:\r
+ CAN->ESR &= ~ CAN_ESR_BOFF; /* rw */\r
+ break;\r
+ case CAN_IT_WKU:\r
+ CAN->MSR = CAN_MSR_WKUI; /* rc_w1*/\r
+ break;\r
+ case CAN_IT_SLK:\r
+ CAN->MSR = CAN_MSR_SLAKI; /* rc_w1*/\r
+ break;\r
+ default :\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : CheckITStatus\r
+* Description : Checks whether the CAN interrupt has occurred or not.\r
+* Input : CAN_Reg: specifies the CAN interrupt register to check.\r
+* It_Bit: specifies the interrupt source bit to check.\r
+* Output : None.\r
+* Return : The new state of the CAN Interrupt (SET or RESET).\r
+*******************************************************************************/\r
+static ITStatus CheckITStatus(u32 CAN_Reg, u32 It_Bit)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+\r
+ if ((CAN_Reg & It_Bit) != (u32)RESET)\r
+ {\r
+ /* CAN_IT is set */\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_IT is reset */\r
+ pendingbitstatus = RESET;\r
+ }\r
+\r
+ return pendingbitstatus;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_dma.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the DMA firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_dma.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* DMA ENABLE mask */\r
+#define CCR_ENABLE_Set ((u32)0x00000001)\r
+#define CCR_ENABLE_Reset ((u32)0xFFFFFFFE)\r
+\r
+/* DMA Channelx interrupt pending bit masks */\r
+#define DMA_Channel1_IT_Mask ((u32)0x0000000F)\r
+#define DMA_Channel2_IT_Mask ((u32)0x000000F0)\r
+#define DMA_Channel3_IT_Mask ((u32)0x00000F00)\r
+#define DMA_Channel4_IT_Mask ((u32)0x0000F000)\r
+#define DMA_Channel5_IT_Mask ((u32)0x000F0000)\r
+#define DMA_Channel6_IT_Mask ((u32)0x00F00000)\r
+#define DMA_Channel7_IT_Mask ((u32)0x0F000000)\r
+\r
+/* DMA registers Masks */\r
+#define CCR_CLEAR_Mask ((u32)0xFFFF800F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_DeInit\r
+* Description : Deinitializes the DMA Channelx registers to their default reset\r
+* values.\r
+* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA\r
+* Channel.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)\r
+{\r
+ /* DMA Channelx disable */\r
+ DMA_Cmd(DMA_Channelx, DISABLE);\r
+\r
+ /* Reset Channelx control register */\r
+ DMA_Channelx->CCR = 0;\r
+ \r
+ /* Reset Channelx remaining bytes register */\r
+ DMA_Channelx->CNDTR = 0;\r
+ \r
+ /* Reset Channelx peripheral address register */\r
+ DMA_Channelx->CPAR = 0;\r
+ \r
+ /* Reset Channelx memory address register */\r
+ DMA_Channelx->CMAR = 0;\r
+\r
+ switch (*(u32*)&DMA_Channelx)\r
+ {\r
+ case DMA_Channel1_BASE:\r
+ /* Reset interrupt pending bits for Channel1 */\r
+ DMA->IFCR |= DMA_Channel1_IT_Mask;\r
+ break;\r
+\r
+ case DMA_Channel2_BASE:\r
+ /* Reset interrupt pending bits for Channel2 */\r
+ DMA->IFCR |= DMA_Channel2_IT_Mask;\r
+ break;\r
+\r
+ case DMA_Channel3_BASE:\r
+ /* Reset interrupt pending bits for Channel3 */\r
+ DMA->IFCR |= DMA_Channel3_IT_Mask;\r
+ break;\r
+\r
+ case DMA_Channel4_BASE:\r
+ /* Reset interrupt pending bits for Channel4 */\r
+ DMA->IFCR |= DMA_Channel4_IT_Mask;\r
+ break;\r
+\r
+ case DMA_Channel5_BASE:\r
+ /* Reset interrupt pending bits for Channel5 */\r
+ DMA->IFCR |= DMA_Channel5_IT_Mask;\r
+ break;\r
+\r
+ case DMA_Channel6_BASE:\r
+ /* Reset interrupt pending bits for Channel6 */\r
+ DMA->IFCR |= DMA_Channel6_IT_Mask;\r
+ break;\r
+\r
+ case DMA_Channel7_BASE:\r
+ /* Reset interrupt pending bits for Channel7 */\r
+ DMA->IFCR |= DMA_Channel7_IT_Mask;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_Init\r
+* Description : Initializes the DMA Channelx according to the specified\r
+* parameters in the DMA_InitStruct.\r
+* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA\r
+* Channel.\r
+* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
+* contains the configuration information for the specified\r
+* DMA Channel.\r
+* Output : None\r
+* Return : None\r
+******************************************************************************/\r
+void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
+ assert(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); \r
+ assert(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); \r
+ assert(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
+ assert(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
+ assert(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
+ assert(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
+ assert(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
+ assert(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
+\r
+/*--------------------------- DMA Channelx CCR Configuration -----------------*/\r
+ /* Get the DMA_Channelx CCR value */\r
+ tmpreg = DMA_Channelx->CCR;\r
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRCULAR and DIR bits */\r
+ tmpreg &= CCR_CLEAR_Mask;\r
+ /* Configure DMA Channelx: data transfer, data size, priority level and mode */\r
+ /* Set DIR bit according to DMA_DIR value */\r
+ /* Set CIRCULAR bit according to DMA_Mode value */\r
+ /* Set PINC bit according to DMA_PeripheralInc value */\r
+ /* Set MINC bit according to DMA_MemoryInc value */\r
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
+ /* Set PL bits according to DMA_Priority value */\r
+ /* Set the MEM2MEM bit according to DMA_M2M value */\r
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
+ /* Write to DMA Channelx CCR */\r
+ DMA_Channelx->CCR = tmpreg;\r
+\r
+/*--------------------------- DMA Channelx CNBTR Configuration ---------------*/\r
+ /* Write to DMA Channelx CNBTR */\r
+ DMA_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
+\r
+/*--------------------------- DMA Channelx CPAR Configuration ----------------*/\r
+ /* Write to DMA Channelx CPAR */\r
+ DMA_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
+\r
+/*--------------------------- DMA Channelx CMAR Configuration ----------------*/\r
+ /* Write to DMA Channelx CMAR */\r
+ DMA_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_StructInit\r
+* Description : Fills each DMA_InitStruct member with its default value.\r
+* Input : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+/*-------------- Reset DMA init structure parameters values ------------------*/\r
+ /* Initialize the DMA_PeripheralBaseAddr member */\r
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
+\r
+ /* Initialize the DMA_MemoryBaseAddr member */\r
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
+\r
+ /* Initialize the DMA_DIR member */\r
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
+\r
+ /* Initialize the DMA_BufferSize member */\r
+ DMA_InitStruct->DMA_BufferSize = 0;\r
+\r
+ /* Initialize the DMA_PeripheralInc member */\r
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
+\r
+ /* Initialize the DMA_MemoryInc member */\r
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
+\r
+ /* Initialize the DMA_PeripheralDataSize member */\r
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
+\r
+ /* Initialize the DMA_MemoryDataSize member */\r
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
+\r
+ /* Initialize the DMA_Mode member */\r
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
+\r
+ /* Initialize the DMA_Priority member */\r
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
+\r
+ /* Initialize the DMA_M2M member */\r
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_Cmd\r
+* Description : Enables or disables the specified DMA Channel.\r
+* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA\r
+* Channel.\r
+* - NewState: new state of the DMAx Channel. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Channelx */\r
+ DMA_Channelx->CCR |= CCR_ENABLE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Channelx */\r
+ DMA_Channelx->CCR &= CCR_ENABLE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_ITConfig\r
+* Description : Enables or disables the specified DMA interrupts.\r
+* Input : - DMA_IT: specifies the DMA interrupts sources to be enabled\r
+* or disabled. \r
+* This parameter can be any combination of the following values:\r
+* - DMA_IT_TC: Transfer complete interrupt mask\r
+* - DMA_IT_HT: Half transfer interrupt mask\r
+* - DMA_IT_TE: Transfer error interrupt mask\r
+* - NewState: new state of the specified DMA interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_DMA_CONFIG_IT(DMA_IT));\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA interrupts */\r
+ DMA_Channelx->CCR |= DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA interrupts */\r
+ DMA_Channelx->CCR &= ~DMA_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_GetCurrDataCounter\r
+* Description : Returns the number of remaining data units in the current\r
+* DMA Channel transfer.\r
+* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA\r
+* Channel.\r
+* Output : None\r
+* Return : The number of remaining data units in the current DMA Channel\r
+* transfer..\r
+*******************************************************************************/\r
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx)\r
+{\r
+ /* Return the current memory address value for Channelx */\r
+ return ((u16)(DMA_Channelx->CNDTR));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_GetFlagStatus\r
+* Description : Checks whether the specified DMA flag is set or not.\r
+* Input : - DMA_FLAG: specifies the flag to check. \r
+* This parameter can be one of the following values:\r
+* - DMA_FLAG_GL1: Channel1 global flag.\r
+* - DMA_FLAG_TC1: Channel1 transfer complete flag.\r
+* - DMA_FLAG_HT1: Channel1 half transfer flag.\r
+* - DMA_FLAG_TE1: Channel1 transfer error flag.\r
+* - DMA_FLAG_GL2: Channel2 global flag.\r
+* - DMA_FLAG_TC2: Channel2 transfer complete flag.\r
+* - DMA_FLAG_HT2: Channel2 half transfer flag.\r
+* - DMA_FLAG_TE2: Channel2 transfer error flag.\r
+* - DMA_FLAG_GL3: Channel3 global flag.\r
+* - DMA_FLAG_TC3: Channel3 transfer complete flag.\r
+* - DMA_FLAG_HT3: Channel3 half transfer flag.\r
+* - DMA_FLAG_TE3: Channel3 transfer error flag.\r
+* - DMA_FLAG_GL4: Channel4 global flag.\r
+* - DMA_FLAG_TC4: Channel4 transfer complete flag.\r
+* - DMA_FLAG_HT4: Channel4 half transfer flag.\r
+* - DMA_FLAG_TE4: Channel4 transfer error flag.\r
+* - DMA_FLAG_GL5: Channel5 global flag.\r
+* - DMA_FLAG_TC5: Channel5 transfer complete flag.\r
+* - DMA_FLAG_HT5: Channel5 half transfer flag.\r
+* - DMA_FLAG_TE5: Channel5 transfer error flag.\r
+* - DMA_FLAG_GL6: Channel6 global flag.\r
+* - DMA_FLAG_TC6: Channel6 transfer complete flag.\r
+* - DMA_FLAG_HT6: Channel6 half transfer flag.\r
+* - DMA_FLAG_TE6: Channel6 transfer error flag.\r
+* - DMA_FLAG_GL7: Channel7 global flag.\r
+* - DMA_FLAG_TC7: Channel7 transfer complete flag.\r
+* - DMA_FLAG_HT7: Channel7 half transfer flag.\r
+* - DMA_FLAG_TE7: Channel7 transfer error flag.\r
+* Output : None\r
+* Return : The new state of DMA_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_DMA_GET_FLAG(DMA_FLAG));\r
+\r
+ /* Check the status of the specified DMA flag */\r
+ if ((DMA->ISR & DMA_FLAG) != (u32)RESET)\r
+ {\r
+ /* DMA_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DMA_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_ClearFlag\r
+* Description : Clears the DMA's pending flags.\r
+* Input : - DMA_FLAG: specifies the flag to clear. \r
+* This parameter can be any combination of the following values:\r
+* - DMA_FLAG_GL1: Channel1 global flag.\r
+* - DMA_FLAG_TC1: Channel1 transfer complete flag.\r
+* - DMA_FLAG_HT1: Channel1 half transfer flag.\r
+* - DMA_FLAG_TE1: Channel1 transfer error flag.\r
+* - DMA_FLAG_GL2: Channel2 global flag.\r
+* - DMA_FLAG_TC2: Channel2 transfer complete flag.\r
+* - DMA_FLAG_HT2: Channel2 half transfer flag.\r
+* - DMA_FLAG_TE2: Channel2 transfer error flag.\r
+* - DMA_FLAG_GL3: Channel3 global flag.\r
+* - DMA_FLAG_TC3: Channel3 transfer complete flag.\r
+* - DMA_FLAG_HT3: Channel3 half transfer flag.\r
+* - DMA_FLAG_TE3: Channel3 transfer error flag.\r
+* - DMA_FLAG_GL4: Channel4 global flag.\r
+* - DMA_FLAG_TC4: Channel4 transfer complete flag.\r
+* - DMA_FLAG_HT4: Channel4 half transfer flag.\r
+* - DMA_FLAG_TE4: Channel4 transfer error flag.\r
+* - DMA_FLAG_GL5: Channel5 global flag.\r
+* - DMA_FLAG_TC5: Channel5 transfer complete flag.\r
+* - DMA_FLAG_HT5: Channel5 half transfer flag.\r
+* - DMA_FLAG_TE5: Channel5 transfer error flag.\r
+* - DMA_FLAG_GL6: Channel6 global flag.\r
+* - DMA_FLAG_TC6: Channel6 transfer complete flag.\r
+* - DMA_FLAG_HT6: Channel6 half transfer flag.\r
+* - DMA_FLAG_TE6: Channel6 transfer error flag.\r
+* - DMA_FLAG_GL7: Channel7 global flag.\r
+* - DMA_FLAG_TC7: Channel7 transfer complete flag.\r
+* - DMA_FLAG_HT7: Channel7 half transfer flag.\r
+* - DMA_FLAG_TE7: Channel7 transfer error flag.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_ClearFlag(u32 DMA_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r
+\r
+ /* Clear the selected DMA flags */\r
+ DMA->IFCR = DMA_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_GetITStatus\r
+* Description : Checks whether the specified DMA interrupt has occurred or not.\r
+* Input : - DMA_IT: specifies the DMA interrupt source to check. \r
+* This parameter can be one of the following values:\r
+* - DMA_IT_GL1: Channel1 global interrupt.\r
+* - DMA_IT_TC1: Channel1 transfer complete interrupt.\r
+* - DMA_IT_HT1: Channel1 half transfer interrupt.\r
+* - DMA_IT_TE1: Channel1 transfer error interrupt.\r
+* - DMA_IT_GL2: Channel2 global interrupt.\r
+* - DMA_IT_TC2: Channel2 transfer complete interrupt.\r
+* - DMA_IT_HT2: Channel2 half transfer interrupt.\r
+* - DMA_IT_TE2: Channel2 transfer error interrupt.\r
+* - DMA_IT_GL3: Channel3 global interrupt.\r
+* - DMA_IT_TC3: Channel3 transfer complete interrupt.\r
+* - DMA_IT_HT3: Channel3 half transfer interrupt.\r
+* - DMA_IT_TE3: Channel3 transfer error interrupt.\r
+* - DMA_IT_GL4: Channel4 global interrupt.\r
+* - DMA_IT_TC4: Channel4 transfer complete interrupt.\r
+* - DMA_IT_HT4: Channel4 half transfer interrupt.\r
+* - DMA_IT_TE4: Channel4 transfer error interrupt.\r
+* - DMA_IT_GL5: Channel5 global interrupt.\r
+* - DMA_IT_TC5: Channel5 transfer complete interrupt.\r
+* - DMA_IT_HT5: Channel5 half transfer interrupt.\r
+* - DMA_IT_TE5: Channel5 transfer error interrupt.\r
+* - DMA_IT_GL6: Channel6 global interrupt.\r
+* - DMA_IT_TC6: Channel6 transfer complete interrupt.\r
+* - DMA_IT_HT6: Channel6 half transfer interrupt.\r
+* - DMA_IT_TE6: Channel6 transfer error interrupt.\r
+* - DMA_IT_GL7: Channel7 global interrupt.\r
+* - DMA_IT_TC7: Channel7 transfer complete interrupt.\r
+* - DMA_IT_HT7: Channel7 half transfer interrupt.\r
+* - DMA_IT_TE7: Channel7 transfer error interrupt.\r
+* Output : None\r
+* Return : The new state of DMA_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus DMA_GetITStatus(u32 DMA_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_DMA_GET_IT(DMA_IT));\r
+\r
+ /* Check the status of the specified DMA interrupt */\r
+ if ((DMA->ISR & DMA_IT) != (u32)RESET)\r
+ {\r
+ /* DMA_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DMA_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : DMA_ClearITPendingBit\r
+* Description : Clears the DMA\92s interrupt pending bits.\r
+* Input : - DMA_IT: specifies the DMA interrupt pending bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - DMA_IT_GL1: Channel1 global interrupt.\r
+* - DMA_IT_TC1: Channel1 transfer complete interrupt.\r
+* - DMA_IT_HT1: Channel1 half transfer interrupt.\r
+* - DMA_IT_TE1: Channel1 transfer error interrupt.\r
+* - DMA_IT_GL2: Channel2 global interrupt.\r
+* - DMA_IT_TC2: Channel2 transfer complete interrupt.\r
+* - DMA_IT_HT2: Channel2 half transfer interrupt.\r
+* - DMA_IT_TE2: Channel2 transfer error interrupt.\r
+* - DMA_IT_GL3: Channel3 global interrupt.\r
+* - DMA_IT_TC3: Channel3 transfer complete interrupt.\r
+* - DMA_IT_HT3: Channel3 half transfer interrupt.\r
+* - DMA_IT_TE3: Channel3 transfer error interrupt.\r
+* - DMA_IT_GL4: Channel4 global interrupt.\r
+* - DMA_IT_TC4: Channel4 transfer complete interrupt.\r
+* - DMA_IT_HT4: Channel4 half transfer interrupt.\r
+* - DMA_IT_TE4: Channel4 transfer error interrupt.\r
+* - DMA_IT_GL5: Channel5 global interrupt.\r
+* - DMA_IT_TC5: Channel5 transfer complete interrupt.\r
+* - DMA_IT_HT5: Channel5 half transfer interrupt.\r
+* - DMA_IT_TE5: Channel5 transfer error interrupt.\r
+* - DMA_IT_GL6: Channel6 global interrupt.\r
+* - DMA_IT_TC6: Channel6 transfer complete interrupt.\r
+* - DMA_IT_HT6: Channel6 half transfer interrupt.\r
+* - DMA_IT_TE6: Channel6 transfer error interrupt.\r
+* - DMA_IT_GL7: Channel7 global interrupt.\r
+* - DMA_IT_TC7: Channel7 transfer complete interrupt.\r
+* - DMA_IT_HT7: Channel7 half transfer interrupt.\r
+* - DMA_IT_TE7: Channel7 transfer error interrupt.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void DMA_ClearITPendingBit(u32 DMA_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_DMA_CLEAR_IT(DMA_IT));\r
+\r
+ /* Clear the selected DMA interrupt pending bits */\r
+ DMA->IFCR = DMA_IT;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
+\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_exti.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the EXTI firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_exti.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define EXTI_LineNone ((u32)0x00000) /* No interrupt selected */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTI_DeInit\r
+* Description : Deinitializes the EXTI peripheral registers to their default \r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTI_DeInit(void)\r
+{\r
+ EXTI->IMR = 0x00000000;\r
+ EXTI->EMR = 0x00000000;\r
+ EXTI->RTSR = 0x00000000; \r
+ EXTI->FTSR = 0x00000000; \r
+ EXTI->PR = 0x0007FFFF;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTI_Init\r
+* Description : Initializes the EXTI peripheral according to the specified\r
+* parameters in the EXTI_InitStruct.\r
+* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
+* that contains the configuration information for the EXTI\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
+ assert(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
+ assert(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); \r
+ assert(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
+ \r
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
+ {\r
+ *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)|= EXTI_InitStruct->EXTI_Line;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ /* Select the trigger for the selected external interrupts */\r
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
+ {\r
+ /* Rising Falling edge */\r
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ else\r
+ {\r
+ *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Trigger)|= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected external lines */\r
+ *(u32 *)(EXTI_BASE + (u32)EXTI_InitStruct->EXTI_Mode)&= ~EXTI_InitStruct->EXTI_Line;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTI_StructInit\r
+* Description : Fills each EXTI_InitStruct member with its reset value.\r
+* Input : - EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ EXTI_InitStruct->EXTI_Line = EXTI_LineNone;\r
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTI_GenerateSWInterrupt\r
+* Description : Generates a Software interrupt.\r
+* Input : - EXTI_Line: specifies the EXTI lines to be enabled or\r
+* disabled.\r
+* This parameter can be:\r
+* - EXTI_Linex: External interrupt line x where x(0..18)\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTI_GenerateSWInterrupt(u32 EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->SWIER |= EXTI_Line;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTI_GetFlagStatus\r
+* Description : Checks whether the specified EXTI line flag is set or not.\r
+* Input : - EXTI_Line: specifies the EXTI lines flag to check.\r
+* This parameter can be:\r
+* - EXTI_Linex: External interrupt line x where x(0..18)\r
+* Output : None\r
+* Return : The new state of EXTI_Line (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus EXTI_GetFlagStatus(u32 EXTI_Line)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ if ((EXTI->PR & EXTI_Line) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTI_ClearFlag\r
+* Description : Clears the EXTI\92s line pending flags.\r
+* Input : - EXTI_Line: specifies the EXTI lines flags to clear.\r
+* This parameter can be:\r
+* - EXTI_Linex: External interrupt line x where x(0..18)\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTI_ClearFlag(u32 EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTI_GetITStatus\r
+* Description : Checks whether the specified EXTI line is asserted or not.\r
+* Input : - EXTI_Line: specifies the EXTI lines to check.\r
+* This parameter can be:\r
+* - EXTI_Linex: External interrupt line x where x(0..18)\r
+* Output : None\r
+* Return : The new state of EXTI_Line (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus EXTI_GetITStatus(u32 EXTI_Line)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ u32 enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ enablestatus = EXTI->IMR & EXTI_Line;\r
+\r
+ if (((EXTI->PR & EXTI_Line) != (u32)RESET) && enablestatus)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : EXTI_ClearITPendingBit\r
+* Description : Clears the EXTI\92s line pending bits.\r
+* Input : - EXTI_Line: specifies the EXTI lines to clear.\r
+* This parameter can be:\r
+* - EXTI_Linex: External interrupt line x where x(0..18)\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void EXTI_ClearITPendingBit(u32 EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_gpio.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the GPIO firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_gpio.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)\r
+\r
+/* --- EVENTCR Register ---*/\r
+/* Alias word address of EVOE bit */\r
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)\r
+#define EVOE_BitNumber ((u8)0x07)\r
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))\r
+\r
+#define EVCR_PORTPINCONFIG_MASK ((u16)0xFF80)\r
+#define LSB_MASK ((u16)0xFFFF)\r
+#define DBGAFR_POSITION_MASK ((u32)0x000F0000)\r
+#define DBGAFR_SWJCFG_MASK ((u32)0xF8FFFFFF)\r
+#define DBGAFR_LOCATION_MASK ((u32)0x00200000)\r
+#define DBGAFR_NUMBITS_MASK ((u32)0x00100000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_DeInit\r
+* Description : Deinitializes the GPIOx peripheral registers to their default\r
+* reset values.\r
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ switch (*(u32*)&GPIOx)\r
+ {\r
+ case GPIOA_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);\r
+ break;\r
+\r
+ case GPIOB_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);\r
+ break;\r
+\r
+ case GPIOC_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);\r
+ break;\r
+\r
+ case GPIOD_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);\r
+ break;\r
+ \r
+ case GPIOE_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);\r
+ break; \r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_AFIODeInit\r
+* Description : Deinitializes the Alternate Functions (remap, event control\r
+* and EXTI configuration) registers to their default reset\r
+* values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_AFIODeInit(void)\r
+{\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_Init\r
+* Description : Initializes the GPIOx peripheral according to the specified\r
+* parameters in the GPIO_InitStruct.\r
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.\r
+* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that\r
+* contains the configuration information for the specified GPIO\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;\r
+ u32 tmpreg = 0x00, pinmask = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+ assert(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); \r
+ \r
+/*---------------------------- GPIO Mode Configuration -----------------------*/\r
+ currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);\r
+\r
+ if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)\r
+ { \r
+ /* Check the parameters */\r
+ assert(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+ /* Output mode */\r
+ currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;\r
+ }\r
+\r
+/*---------------------------- GPIO CRL Configuration ------------------------*/\r
+ /* Configure the eight low port pins */\r
+ if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)\r
+ {\r
+ tmpreg = GPIOx->CRL;\r
+\r
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
+ {\r
+ pos = ((u32)0x01) << pinpos;\r
+ /* Get the port pins position */\r
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+\r
+ if (currentpin == pos)\r
+ {\r
+ pos = pinpos << 2;\r
+ /* Clear the corresponding low control register bits */\r
+ pinmask = ((u32)0x0F) << pos;\r
+ tmpreg &= ~pinmask;\r
+\r
+ /* Write the mode configuration in the corresponding bits */\r
+ tmpreg |= (currentmode << pos);\r
+\r
+ /* Reset the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
+ {\r
+ GPIOx->BRR = (((u32)0x01) << pinpos);\r
+ }\r
+ /* Set the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
+ {\r
+ GPIOx->BSRR = (((u32)0x01) << pinpos);\r
+ }\r
+ }\r
+ }\r
+ GPIOx->CRL = tmpreg;\r
+ tmpreg = 0;\r
+ }\r
+\r
+/*---------------------------- GPIO CRH Configuration ------------------------*/\r
+ /* Configure the eight high port pins */\r
+ if (GPIO_InitStruct->GPIO_Pin > 0x00FF)\r
+ {\r
+ tmpreg = GPIOx->CRH;\r
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
+ {\r
+ pos = (((u32)0x01) << (pinpos + 0x08));\r
+ /* Get the port pins position */\r
+ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);\r
+ if (currentpin == pos)\r
+ {\r
+ pos = pinpos << 2;\r
+ /* Clear the corresponding high control register bits */\r
+ pinmask = ((u32)0x0F) << pos;\r
+ tmpreg &= ~pinmask;\r
+\r
+ /* Write the mode configuration in the corresponding bits */\r
+ tmpreg |= (currentmode << pos);\r
+\r
+ /* Reset the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
+ {\r
+ GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));\r
+ }\r
+ /* Set the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
+ {\r
+ GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));\r
+ }\r
+ }\r
+ }\r
+ GPIOx->CRH = tmpreg;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_StructInit\r
+* Description : Fills each GPIO_InitStruct member with its default value.\r
+* Input : - GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* Reset GPIO init structure parameters values */\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ReadInputDataBit\r
+* Description : Reads the specified input port pin.\r
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.\r
+* : - GPIO_Pin: specifies the port bit to read.\r
+* This parameter can be GPIO_Pin_x where x can be (0..15).\r
+* Output : None\r
+* Return : The input port pin value.\r
+*******************************************************************************/\r
+u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)\r
+{\r
+ u8 bitstatus = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_GPIO_PIN(GPIO_Pin)); \r
+ \r
+ if ((GPIOx->IDR & GPIO_Pin) != (u32)Bit_RESET)\r
+ {\r
+ bitstatus = (u8)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (u8)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ReadInputData\r
+* Description : Reads the specified GPIO input data port.\r
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.\r
+* Output : None\r
+* Return : GPIO input data port value.\r
+*******************************************************************************/\r
+u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ return ((u16)GPIOx->IDR);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ReadOutputDataBit\r
+* Description : Reads the specified output data port bit.\r
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.\r
+* : - GPIO_Pin: specifies the port bit to read.\r
+* This parameter can be GPIO_Pin_x where x can be (0..15).\r
+* Output : None\r
+* Return : The output port pin value.\r
+*******************************************************************************/\r
+u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)\r
+{\r
+ u8 bitstatus = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_GPIO_PIN(GPIO_Pin)); \r
+ \r
+ if ((GPIOx->ODR & GPIO_Pin) != (u32)Bit_RESET)\r
+ {\r
+ bitstatus = (u8)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (u8)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_ReadOutputData\r
+* Description : Reads the specified GPIO output data port.\r
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.\r
+* Output : None\r
+* Return : GPIO output data port value.\r
+*******************************************************************************/\r
+u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ return ((u16)GPIOx->ODR);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_WriteBit\r
+* Description : Sets or clears the selected data port bit.\r
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.\r
+* - GPIO_Pin: specifies the port bit to be written.\r
+* This parameter can be GPIO_Pin_x where x can be (0..15).\r
+* - BitVal: specifies the value to be written to the selected bit.\r
+* This parameter can be one of the BitAction enum values:\r
+* - Bit_RESET: to clear the port pin\r
+* - Bit_SET: to set the port pin\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_GPIO_PIN(GPIO_Pin));\r
+ assert(IS_GPIO_BIT_ACTION(BitVal)); \r
+ \r
+ if (BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BRR = GPIO_Pin;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_Write\r
+* Description : Writes data to the specified GPIO data port.\r
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.\r
+* - PortVal: specifies the value to be written to the port output\r
+* data register.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal)\r
+{\r
+ GPIOx->ODR = PortVal;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_PinLockConfig\r
+* Description : Locks GPIO Pins configuration registers.\r
+* Input : - GPIOx: where x can be (A..E) to select the GPIO peripheral.\r
+* - GPIO_Pin: specifies the port bit to be written.\r
+* This parameter can be GPIO_Pin_x where x can be (0..15).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin)\r
+{\r
+ u32 tmp = 0x00010000;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKK bit */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_EventOutputConfig\r
+* Description : Selects the GPIO pin used as Event output.\r
+* Input : - GPIO_PortSource: selects the GPIO port to be used as source\r
+* for Event output.\r
+* This parameter can be GPIO_PortSourceGPIOx where x can be\r
+* (A..E).\r
+* - GPIO_PinSource: specifies the pin for the Event output.\r
+* This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)\r
+{\r
+ u32 tmpreg = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource));\r
+ assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ \r
+ tmpreg = AFIO->EVCR;\r
+ /* Clear the PORT[6:4] and PIN[3:0] bits */\r
+ tmpreg &= EVCR_PORTPINCONFIG_MASK;\r
+ tmpreg |= (u32)GPIO_PortSource << 0x04;\r
+ tmpreg |= GPIO_PinSource;\r
+\r
+ AFIO->EVCR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_EventOutputCmd\r
+* Description : Enables or disables the Event Output.\r
+* Input : - NewState: new state of the Event output.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_EventOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(vu32 *) EVCR_EVOE_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_PinRemapConfig\r
+* Description : Changes the mapping of the specified pin.\r
+* Input : - GPIO_Remap: selects the pin to remap.\r
+* This parameter can be one of the following values:\r
+* - GPIO_Remap_SPI1\r
+* - GPIO_Remap_I2C1\r
+* - GPIO_Remap_USART1\r
+* - GPIO_Remap_USART2\r
+* - GPIO_PartialRemap_USART3\r
+* - GPIO_FullRemap_USART3\r
+* - GPIO_PartialRemap_TIM1\r
+* - GPIO_FullRemap_TIM1\r
+* - GPIO_PartialRemap1_TIM2\r
+* - GPIO_PartialRemap2_TIM2\r
+* - GPIO_FullRemap_TIM2\r
+* - GPIO_PartialRemap_TIM3\r
+* - GPIO_FullRemap_TIM3\r
+* - GPIO_Remap_TIM4\r
+* - GPIO_Remap1_CAN\r
+* - GPIO_Remap2_CAN\r
+* - GPIO_Remap_PD01\r
+* - GPIO_Remap_SWJ_NoJTRST\r
+* - GPIO_Remap_SWJ_JTAGDisable\r
+* - GPIO_Remap_SWJ_Disable\r
+* - NewState: new state of the port pin remapping.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState)\r
+{\r
+ u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_GPIO_REMAP(GPIO_Remap));\r
+ assert(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ tmpreg = AFIO->MAPR;\r
+\r
+ tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;\r
+ tmp = GPIO_Remap & LSB_MASK;\r
+\r
+ if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)\r
+ {\r
+ tmpreg &= DBGAFR_SWJCFG_MASK;\r
+ }\r
+ else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)\r
+ {\r
+ tmp1 = ((u32)0x03) << tmpmask;\r
+ tmpreg &= ~tmp1;\r
+ }\r
+ else\r
+ {\r
+ tmpreg &= ~tmp;\r
+ }\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ if ((GPIO_Remap & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)\r
+ {\r
+ tmpreg |= (tmp << 0x10);\r
+ }\r
+ else\r
+ {\r
+ tmpreg |= tmp;\r
+ }\r
+ }\r
+ AFIO->MAPR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : GPIO_EXTILineConfig\r
+* Description : Selects the GPIO pin used as EXTI Line.\r
+* Input : - GPIO_PortSource: selects the GPIO port to be used as\r
+* source for EXTI lines.\r
+* - GPIO_PinSource: specifies the EXTI line to be configured.\r
+* This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)\r
+{\r
+ u32 tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_GPIO_PORT_SOURCE(GPIO_PortSource));\r
+ assert(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ \r
+ tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03));\r
+\r
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;\r
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03)));\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_i2c.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the I2C firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_i2c.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* I2C SPE mask */\r
+#define CR1_PE_Set ((u16)0x0001)\r
+#define CR1_PE_Reset ((u16)0xFFFE)\r
+\r
+/* I2C DMAEN mask */\r
+#define CR2_DMAEN_Set ((u16)0x0800)\r
+#define CR2_DMAEN_Reset ((u16)0xF7FF)\r
+\r
+/* I2C LAST mask */\r
+#define CR2_LAST_Set ((u16)0x1000)\r
+#define CR2_LAST_Reset ((u16)0xEFFF)\r
+\r
+/* I2C START mask */\r
+#define CR1_START_Set ((u16)0x0100)\r
+#define CR1_START_Reset ((u16)0xFEFF)\r
+\r
+/* I2C STOP mask */\r
+#define CR1_STOP_Set ((u16)0x0200)\r
+#define CR1_STOP_Reset ((u16)0xFDFF)\r
+\r
+/* I2C ACK mask */\r
+#define CR1_ACK_Set ((u16)0x0400)\r
+#define CR1_ACK_Reset ((u16)0xFBFF)\r
+\r
+/* I2C ENGC mask */\r
+#define CR1_ENGC_Set ((u16)0x0040)\r
+#define CR1_ENGC_Reset ((u16)0xFFBF)\r
+\r
+/* I2C ADD0 mask */\r
+#define OAR1_ADD0_Set ((u16)0x0001)\r
+#define OAR1_ADD0_Reset ((u16)0xFFFE)\r
+\r
+/* I2C SWRST mask */\r
+#define CR1_SWRST_Set ((u16)0x8000)\r
+#define CR1_SWRST_Reset ((u16)0x7FFF)\r
+\r
+/* I2C PEC mask */\r
+#define CR1_PEC_Set ((u16)0x1000)\r
+\r
+/* I2C ENPEC mask */\r
+#define CR1_ENPEC_Set ((u16)0x0020)\r
+#define CR1_ENPEC_Reset ((u16)0xFFDF)\r
+\r
+/* I2C ENARP mask */\r
+#define CR1_ENARP_Set ((u16)0x0010)\r
+#define CR1_ENARP_Reset ((u16)0xFFEF)\r
+\r
+/* I2C NOSTRETCH mask */\r
+#define CR1_NOSTRETCH_Set ((u16)0x0080)\r
+#define CR1_NOSTRETCH_Reset ((u16)0xFF7F)\r
+\r
+/* I2C ENDUAL mask */\r
+#define OAR2_ENDUAL_Set ((u16)0x0001)\r
+#define OAR2_ENDUAL_Reset ((u16)0xFFFE)\r
+\r
+/* I2C F/S mask */\r
+#define CCR_FS_Set ((u16)0x8000)\r
+\r
+/* I2C ADD2 mask */\r
+#define OAR2_ADD2_Reset ((u16)0xFF01)\r
+\r
+/* I2C FREQ mask */\r
+#define CR2_FREQ_Reset ((u16)0xFFC0)\r
+\r
+/* I2C CCR mask */\r
+#define CCR_CCR_Set ((u16)0x0FFF)\r
+\r
+/* I2C FLAG mask */\r
+#define I2C_FLAG_Mask ((u32)0x00FFFFFF)\r
+\r
+/* I2C registers Masks */\r
+#define CR1_CLEAR_Mask ((u16)0xFBF5)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_DeInit\r
+* Description : Deinitializes the I2Cx peripheral registers to their default\r
+* reset values.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_DeInit(I2C_TypeDef* I2Cx)\r
+{\r
+ switch (*(u32*)&I2Cx)\r
+ {\r
+ case I2C1_BASE:\r
+ /* Enable I2C1 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
+ /* Release I2C1 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
+ break;\r
+\r
+ case I2C2_BASE:\r
+ /* Enable I2C2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
+ /* Release I2C2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_Init\r
+* Description : Initializes the I2Cx according to the specified parameters\r
+* in the I2C_InitStruct.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
+* contains the configuration information for the specified\r
+* I2C peripheral.\r
+* Output : None\r
+* Return : None\r
+******************************************************************************/\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+ u16 tmpreg = 0, freqrange = 0;\r
+ u16 result = 0x04;\r
+ u32 pclk1clock = 12000000;\r
+ RCC_ClocksTypeDef RCC_Clocks;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
+ assert(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r
+ assert(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
+ assert(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r
+ assert(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
+ assert(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));\r
+\r
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r
+ /* Get the I2Cx CR2 value */\r
+ tmpreg = I2Cx->CR2;\r
+ /* Clear frequency FREQ[5:0] bits */\r
+ tmpreg &= CR2_FREQ_Reset;\r
+ /* Get PCLK1Clock frequency value */\r
+ RCC_GetClocksFreq(&RCC_Clocks);\r
+ pclk1clock = RCC_Clocks.PCLK1_Frequency;\r
+ /* Set frequency bits depending on PCLK1Clock value */\r
+ freqrange = (u16)(pclk1clock / 1000000);\r
+ tmpreg |= freqrange;\r
+ /* Write to I2Cx CR2 */\r
+ I2Cx->CR2 = tmpreg;\r
+\r
+/*---------------------------- I2Cx CCR Configuration ------------------------*/\r
+ /* Disable I2Cx to configure TRISE */\r
+ I2C_Cmd(I2Cx, DISABLE);\r
+\r
+ /* Reset tmpreg value */\r
+ /* Clear F/S, DUTY and CCR[11:0] bits */\r
+ tmpreg = 0;\r
+\r
+ /* Configure speed in standard mode */\r
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r
+ {\r
+ /* Standard mode speed calculate */\r
+ result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed << 1));\r
+ /* Test if CCR value is under 0x4*/\r
+ if (result < 0x04)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result = 0x04; \r
+ }\r
+ /* Set speed value for standard mode */\r
+ tmpreg |= result; \r
+ /* Set Maximum Rise Time: ((1000/(1000000000/pclk1clock))+1 */\r
+ I2Cx->TRISE = freqrange + 1; \r
+ }\r
+ /* Configure speed in fast mode */\r
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r
+ {\r
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
+ result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 3));\r
+ }\r
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
+ result = (u16)(pclk1clock / (I2C_InitStruct->I2C_ClockSpeed * 25));\r
+ /* Set DUTY bit */\r
+ result |= I2C_DutyCycle_16_9;\r
+ }\r
+ /* Test if CCR value is under 0x1*/\r
+ if ((result & CCR_CCR_Set) == 0)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result |= (u16)0x0001; \r
+ }\r
+ /* Set speed value and set F/S bit for fast mode */\r
+ tmpreg |= result | CCR_FS_Set;\r
+ /* Set Maximum Rise Time: ((300/(1000000000/pclk1clock))+1 */\r
+ I2Cx->TRISE = (u16)(((freqrange * 300) / 1000) + 1); \r
+ }\r
+ /* Write to I2Cx CCR */\r
+ I2Cx->CCR = tmpreg;\r
+\r
+ /* Enable I2Cx */\r
+ I2C_Cmd(I2Cx, ENABLE);\r
+\r
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r
+ /* Get the I2Cx CR1 value */\r
+ tmpreg = I2Cx->CR1;\r
+ /* Clear ACK, SMBTYPE and SMBUS bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+ /* Configure I2Cx: mode and acknowledgement */\r
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r
+ /* Set ACK bit according to I2C_Ack value */\r
+ tmpreg |= (u16)((u32)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r
+ /* Write to I2Cx CR1 */\r
+ I2Cx->CR1 = tmpreg;\r
+\r
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r
+ /* Set I2Cx Own Address1 and acknowledged address */\r
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_StructInit\r
+* Description : Fills each I2C_InitStruct member with its default value.\r
+* Input : - I2C_InitStruct: pointer to a I2C_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+/*---------------- Reset I2C init structure parameters values ----------------*/\r
+ /* Initialize the I2C_Mode member */\r
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
+\r
+ /* Initialize the I2C_DutyCycle member */\r
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r
+\r
+ /* Initialize the I2C_OwnAddress1 member */\r
+ I2C_InitStruct->I2C_OwnAddress1 = 0;\r
+\r
+ /* Initialize the I2C_Ack member */\r
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
+\r
+ /* Initialize the I2C_AcknowledgedAddress member */\r
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
+\r
+ /* initialize the I2C_ClockSpeed member */\r
+ I2C_InitStruct->I2C_ClockSpeed = 5000;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_Cmd\r
+* Description : Enables or disables the specified I2C peripheral.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2Cx peripheral. This parameter\r
+* can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= CR1_PE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C peripheral */\r
+ I2Cx->CR1 &= CR1_PE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_DMACmd\r
+* Description : Enables or disables the specified I2C DMA requests.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C DMA transfer.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C DMA requests */\r
+ I2Cx->CR2 |= CR2_DMAEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C DMA requests */\r
+ I2Cx->CR2 &= CR2_DMAEN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_DMALastTransferCmd\r
+* Description : Specifies that the next DMA transfer is the last one.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C DMA last transfer.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Next DMA end of transfer is the last transfer */\r
+ I2Cx->CR2 |= CR2_LAST_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Next DMA end of transfer is not the last transfer */\r
+ I2Cx->CR2 &= CR2_LAST_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GenerateSTART\r
+* Description : Generates I2Cx communication START condition.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C START condition generation.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a START condition */\r
+ I2Cx->CR1 |= CR1_START_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the START condition generation */\r
+ I2Cx->CR1 &= CR1_START_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GenerateSTOP\r
+* Description : Generates I2Cx communication STOP condition.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C STOP condition generation.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a STOP condition */\r
+ I2Cx->CR1 |= CR1_STOP_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the STOP condition generation */\r
+ I2Cx->CR1 &= CR1_STOP_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_AcknowledgeConfig\r
+* Description : Enables or disables the specified I2C acknowledge feature.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C Acknowledgement.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the acknowledgement */\r
+ I2Cx->CR1 |= CR1_ACK_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the acknowledgement */\r
+ I2Cx->CR1 &= CR1_ACK_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_OwnAddress2Config\r
+* Description : Configures the specified I2C own address2.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - Address: specifies the 7bit I2C own address2.\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, u8 Address)\r
+{\r
+ u16 tmpreg = 0;\r
+\r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->OAR2;\r
+ /* Reset I2Cx Own address2 bit [7:1] */\r
+ tmpreg &= OAR2_ADD2_Reset;\r
+ /* Set I2Cx Own address2 */\r
+ tmpreg |= (u16)(Address & (u16)0x00FE);\r
+ /* Store the new register value */\r
+ I2Cx->OAR2 = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_DualAddressCmd\r
+* Description : Enables or disables the specified I2C dual addressing mode.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C dual addressing mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable dual addressing mode */\r
+ I2Cx->OAR2 |= OAR2_ENDUAL_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable dual addressing mode */\r
+ I2Cx->OAR2 &= OAR2_ENDUAL_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GeneralCallCmd\r
+* Description : Enables or disables the specified I2C general call feature.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C General call.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable generall call */\r
+ I2Cx->CR1 |= CR1_ENGC_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable generall call */\r
+ I2Cx->CR1 &= CR1_ENGC_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ITConfig\r
+* Description : Enables or disables the specified I2C interrupts.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_IT: specifies the I2C interrupts sources to be enabled\r
+* or disabled. \r
+* This parameter can be any combination of the following values:\r
+* - I2C_IT_BUF: Buffer interrupt mask\r
+* - I2C_IT_EVT: Event interrupt mask\r
+* - I2C_IT_ERR: Error interrupt mask\r
+* - NewState: new state of the specified I2C interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, u16 I2C_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ assert(IS_I2C_CONFIG_IT(I2C_IT));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C interrupts */\r
+ I2Cx->CR2 |= I2C_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C interrupts */\r
+ I2Cx->CR2 &= (u16)~I2C_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_SendData\r
+* Description : Sends a data byte through the I2Cx peripheral.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - Data: Byte to be transmitted..\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_SendData(I2C_TypeDef* I2Cx, u8 Data)\r
+{\r
+ /* Write in the DR register the data to be sent */\r
+ I2Cx->DR = Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ReceiveData\r
+* Description : Returns the most recent received data by the I2Cx peripheral.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* Output : None\r
+* Return : The value of the received data.\r
+*******************************************************************************/\r
+u8 I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Return the data in the DR register */\r
+ return (u8)I2Cx->DR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_Send7bitAddress\r
+* Description : Transmits the address byte to select the slave device.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - Address: specifies the slave address which will be transmitted\r
+* - Direction: specifies whether the I2C device will be a\r
+* Transmitter or a Receiver. \r
+* This parameter can be one of the following values\r
+* - I2C_Direction_Transmitter: Transmitter mode\r
+* - I2C_Direction_Receiver: Receiver mode\r
+* Output : None\r
+* Return : None.\r
+*******************************************************************************/\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 I2C_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_I2C_DIRECTION(I2C_Direction));\r
+\r
+ /* Test on the direction to set/reset the read/write bit */\r
+ if (I2C_Direction != I2C_Direction_Transmitter)\r
+ {\r
+ /* Set the address ADD0 bit0 for read */\r
+ Address |= OAR1_ADD0_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the address bit0 for write */\r
+ Address &= OAR1_ADD0_Reset;\r
+ }\r
+ /* Send the address */\r
+ I2Cx->DR = Address;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ReadRegister\r
+* Description : Reads the specified I2C register and returns its value.\r
+* Input1 : - I2C_Register: specifies the register to read.\r
+* This parameter can be one of the following values:\r
+* - I2C_Register_CR1: CR1 register.\r
+* - I2C_Register_CR2: CR2 register.\r
+* - I2C_Register_OAR1: OAR1 register.\r
+* - I2C_Register_OAR2: OAR2 register.\r
+* - I2C_Register_DR: DR register.\r
+* - I2C_Register_SR1: SR1 register.\r
+* - I2C_Register_SR2: SR2 register.\r
+* - I2C_Register_CCR: CCR register.\r
+* - I2C_Register_TRISE: TRISE register.\r
+* Output : None\r
+* Return : The value of the read register.\r
+*******************************************************************************/\r
+u16 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_I2C_REGISTER(I2C_Register));\r
+\r
+ /* Return the selected register value */\r
+ return (*(u16 *)(*((u32 *)&I2Cx) + I2C_Register));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_SoftwareResetCmd\r
+* Description : Enables or disables the specified I2C software reset.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2C software reset.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Peripheral under reset */\r
+ I2Cx->CR1 |= CR1_SWRST_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Peripheral not under reset */\r
+ I2Cx->CR1 &= CR1_SWRST_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_SMBusAlertConfig\r
+* Description : Drives the SMBusAlert pin high or low for the specified I2C.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_SMBusAlert: specifies SMBAlert pin level. \r
+* This parameter can be one of the following values:\r
+* - I2C_SMBusAlert_Low: SMBAlert pin driven low\r
+* - I2C_SMBusAlert_High: SMBAlert pin driven high\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, u16 I2C_SMBusAlert)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r
+\r
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r
+ {\r
+ /* Drive the SMBusAlert pin Low */\r
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;\r
+ }\r
+ else\r
+ {\r
+ /* Drive the SMBusAlert pin High */\r
+ I2Cx->CR1 &= I2C_SMBusAlert_High;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_TransmitPEC\r
+* Description : Enables the specified I2C PEC transfer.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Enable the selected I2C PEC transmission */\r
+ I2Cx->CR1 |= CR1_PEC_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_PECPositionConfig\r
+* Description : Selects the specified I2C PEC position.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_PECPosition: specifies the PEC position. \r
+* This parameter can be one of the following values:\r
+* - I2C_PECPosition_Next: PEC bit indicates that current\r
+* byte is PEC\r
+* - I2C_PECPosition_Current: PEC bit indicates that the\r
+* next byte is PEC\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, u16 I2C_PECPosition)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_I2C_PEC_POSITION(I2C_PECPosition));\r
+\r
+ if (I2C_PECPosition == I2C_PECPosition_Next)\r
+ {\r
+ /* PEC indicates that the next byte in shift register is PEC */\r
+ I2Cx->CR1 |= I2C_PECPosition_Next;\r
+ }\r
+ else\r
+ {\r
+ /* PEC indicates that the current byte in shift register is PEC */\r
+ I2Cx->CR1 &= I2C_PECPosition_Current;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_CalculatePEC\r
+* Description : Enables or disables the PEC value calculation of the\r
+* transfered bytes.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2Cx PEC value calculation.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC calculation */\r
+ I2Cx->CR1 |= CR1_ENPEC_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC calculation */\r
+ I2Cx->CR1 &= CR1_ENPEC_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GetPEC\r
+* Description : Returns the PEC value for the specified I2C.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* Output : None\r
+* Return : The PEC value.\r
+*******************************************************************************/\r
+u8 I2C_GetPEC(I2C_TypeDef* I2Cx)\r
+{\r
+ u8 pec;\r
+\r
+ /* Get the PEC value */\r
+ pec = (I2Cx->SR2) >> 8;\r
+ /* Return the selected I2C PEC register value */\r
+ return pec;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ARPCmd\r
+* Description : Enables or disables the specified I2C ARP.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2Cx ARP. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C ARP */\r
+ I2Cx->CR1 |= CR1_ENARP_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C ARP */\r
+ I2Cx->CR1 &= CR1_ENARP_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_StretchClockCmd\r
+* Description : Enables or disables the specified I2C Clock stretching.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - NewState: new state of the I2Cx Clock stretching.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState == DISABLE)\r
+ {\r
+ /* Enable the selected I2C Clock stretching */\r
+ I2Cx->CR1 |= CR1_NOSTRETCH_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C Clock stretching */\r
+ I2Cx->CR1 &= CR1_NOSTRETCH_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_FastModeDutyCycleConfig\r
+* Description : Selects the specified I2C fast mode duty cycle.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_DutyCycle: specifies the fast mode duty cycle.\r
+* This parameter can be one of the following values:\r
+* - I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r
+* - I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, u16 I2C_DutyCycle)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r
+\r
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=2 */\r
+ I2Cx->CCR &= I2C_DutyCycle_2;\r
+ }\r
+ else\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=16/9 */\r
+ I2Cx->CCR |= I2C_DutyCycle_16_9;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GetLastEvent\r
+* Description : Returns the Last I2C Event.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* Output : None\r
+* Return : The last event\r
+*******************************************************************************/\r
+u32 I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r
+{\r
+ u32 LastEvent = 0;\r
+ u32 Flag1 = 0, Flag2 = 0;\r
+\r
+ Flag1 = I2Cx->SR1;\r
+ Flag2 = I2Cx->SR2;\r
+ Flag2 = Flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ LastEvent = (Flag1 | Flag2) & I2C_FLAG_Mask;\r
+\r
+ /* Return status */\r
+ return LastEvent;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_CheckEvent\r
+* Description : Checks whether the Last I2C Event is equal to the one passed\r
+* as parameter.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_EVENT: specifies the event to be checked. \r
+* This parameter can be one of the following values:\r
+* - I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1\r
+* - I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2\r
+* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3\r
+* - I2C_EVENT_SLAVE_ACK_FAILURE : EV3-1\r
+* - I2C_EVENT_MASTER_MODE_SELECT : EV5\r
+* - I2C_EVENT_MASTER_MODE_SELECTED : EV6\r
+* - I2C_EVENT_MASTER_BYTE_RECEIVED : EV7\r
+* - I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8\r
+* - I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9\r
+* - I2C_EVENT_SLAVE_STOP_DETECTED : EV4\r
+* Output : None\r
+* Return : An ErrorStatus enumuration value:\r
+* - SUCCESS: Last event is equal to the I2C_Event\r
+* - ERROR: Last event is different from the I2C_Event\r
+*******************************************************************************/\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, u32 I2C_EVENT)\r
+{\r
+ u32 LastEvent = 0;\r
+ u32 Flag1 = 0, Flag2 = 0;\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_I2C_EVENT(I2C_EVENT));\r
+\r
+ Flag1 = I2Cx->SR1;\r
+ Flag2 = I2Cx->SR2;\r
+ Flag2 = Flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ LastEvent = (Flag1 | Flag2) & I2C_FLAG_Mask;\r
+\r
+ /* Check whether the last event is equal to I2C_EVENT */\r
+ if (LastEvent == I2C_EVENT )\r
+ {\r
+ /* SUCCESS: last event is equal to I2C_EVENT */\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: last event is different from I2C_EVENT */\r
+ status = ERROR;\r
+ }\r
+\r
+ /* Return status */\r
+ return status;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GetFlagStatus\r
+* Description : Checks whether the specified I2C flag is set or not.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_FLAG: specifies the flag to check. \r
+* This parameter can be one of the following values:\r
+* - I2C_FLAG_DUALF: Dual flag (Slave mode)\r
+* - I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r
+* - I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r
+* - I2C_FLAG_GENCALL: General call header flag (Slave mode)\r
+* - I2C_FLAG_TRA: Transmitter/Receiver flag\r
+* - I2C_FLAG_BUSY: Bus busy flag\r
+* - I2C_FLAG_MSL: Master/Slave flag\r
+* - I2C_FLAG_SMBALERT: SMBus Alert flag\r
+* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+* - I2C_FLAG_PECERR: PEC error in reception flag\r
+* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+* - I2C_FLAG_AF: Acknowledge failure flag\r
+* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+* - I2C_FLAG_BERR: Bus error flag\r
+* - I2C_FLAG_TXE: Data register empty flag (Transmitter)\r
+* - I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r
+* - I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
+* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
+* - I2C_FLAG_BTF: Byte transfer finished flag\r
+* - I2C_FLAG_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+* Address matched flag (Slave mode)\94ENDAD\94\r
+* - I2C_FLAG_SB: Start bit flag (Master mode)\r
+* Output : None\r
+* Return : The new state of I2C_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u32 I2C_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ u32 i2cstatus = 0;\r
+ u32 Flag1 = 0, Flag2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_I2C_GET_FLAG(I2C_FLAG));\r
+\r
+ /* Read the I2Cx status register */\r
+ Flag1 = I2Cx->SR1;\r
+ Flag2 = I2Cx->SR2;\r
+ Flag2 = (Flag2 & I2C_FLAG_Mask) << 16;\r
+\r
+ /* Get the I2C status value */\r
+ i2cstatus = Flag1 | Flag2;\r
+\r
+ /* Get bit[27:0] of the flag */\r
+ I2C_FLAG &= I2C_FLAG_Mask;\r
+\r
+ /* Check the status of the specified I2C flag */\r
+ if ((i2cstatus & I2C_FLAG) != (u32)RESET)\r
+ {\r
+ /* I2C_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the I2C_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ClearFlag\r
+* Description : Clears the I2Cx's pending flags.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_FLAG: specifies the flag to clear. \r
+* This parameter can be one of the following values:\r
+* - I2C_FLAG_SMBALERT: SMBus Alert flag\r
+* - I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+* - I2C_FLAG_PECERR: PEC error in reception flag\r
+* - I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+* - I2C_FLAG_AF: Acknowledge failure flag\r
+* - I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+* - I2C_FLAG_BERR: Bus error flag\r
+* - I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
+* - I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
+* - I2C_FLAG_BTF: Byte transfer finished flag\r
+* - I2C_FLAG_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+* Address matched flag (Slave mode)\94ENDAD\94\r
+* - I2C_FLAG_SB: Start bit flag (Master mode)\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, u32 I2C_FLAG)\r
+{\r
+ u32 flagpos = 0;\r
+ u8 flagindex = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
+\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_FLAG & I2C_FLAG_Mask;\r
+\r
+ /* Get the I2C flag index */\r
+ flagindex = I2C_FLAG >> 28;\r
+\r
+ /* Clear the flag by writing 0 */\r
+ if (flagindex == 1)\r
+ {\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 &= ~flagpos;\r
+ }\r
+ /* Flags that need a read of the SR1 register to be cleared */\r
+ else if (flagindex == 2)\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+ }\r
+ /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */\r
+ else if (flagindex == 6)\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+\r
+ /* Write on the CR1 register */\r
+ I2Cx->CR1 |= CR1_PE_Set;\r
+ }\r
+ /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */\r
+ else /*flagindex == 0xA*/\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+\r
+ /* Read the SR2 register */\r
+ (void)I2Cx->SR2;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_GetITStatus\r
+* Description : Checks whether the specified I2C interrupt has occurred or not.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_IT: specifies the interrupt source to check. \r
+* This parameter can be one of the following values:\r
+* - I2C_IT_SMBALERT: SMBus Alert flag\r
+* - I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
+* - I2C_IT_PECERR: PEC error in reception flag\r
+* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
+* - I2C_IT_AF: Acknowledge failure flag\r
+* - I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
+* - I2C_IT_BERR: Bus error flag\r
+* - I2C_IT_TXE: Data register empty flag (Transmitter)\r
+* - I2C_IT_RXNE: Data register not empty (Receiver) flag\r
+* - I2C_IT_STOPF: Stop detection flag (Slave mode)\r
+* - I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
+* - I2C_IT_BTF: Byte transfer finished flag\r
+* - I2C_IT_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+* Address matched flag (Slave mode)\94ENDAD\94\r
+* - I2C_IT_SB: Start bit flag (Master mode)\r
+* Output : None\r
+* Return : The new state of I2C_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, u32 I2C_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ u32 i2cstatus = 0;\r
+ u32 Flag1 = 0, Flag2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_I2C_GET_IT(I2C_IT));\r
+\r
+ /* Read the I2Cx status register */\r
+ Flag1 = I2Cx->SR1;\r
+ Flag2 = I2Cx->SR2;\r
+ Flag2 = (Flag2 & I2C_FLAG_Mask) << 16;\r
+\r
+ /* Get the I2C status value */\r
+ i2cstatus = Flag1 | Flag2;\r
+\r
+ /* Get bit[27:0] of the flag */\r
+ I2C_IT &= I2C_FLAG_Mask;\r
+\r
+ /* Check the status of the specified I2C flag */\r
+ if ((i2cstatus & I2C_IT) != (u32)RESET)\r
+ {\r
+ /* I2C_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the I2C_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : I2C_ClearITPendingBit\r
+* Description : Clears the I2Cx\92s interrupt pending bits.\r
+* Input : - I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+* - I2C_IT: specifies the interrupt pending to clear. \r
+* This parameter can be one of the following values:\r
+* - I2C_IT_SMBALERT: SMBus Alert flag\r
+* - I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
+* - I2C_IT_PECERR: PEC error in reception flag\r
+* - I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
+* - I2C_IT_AF: Acknowledge failure flag\r
+* - I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
+* - I2C_IT_BERR: Bus error flag\r
+* - I2C_IT_STOPF: Stop detection flag (Slave mode)\r
+* - I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
+* - I2C_IT_BTF: Byte transfer finished flag\r
+* - I2C_IT_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+* Address matched flag (Slave mode)\94ENDAD\94\r
+* - I2C_IT_SB: Start bit flag (Master mode)\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, u32 I2C_IT)\r
+{\r
+ u32 flagpos = 0;\r
+ u8 flagindex = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_I2C_CLEAR_IT(I2C_IT));\r
+\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_IT & I2C_FLAG_Mask;\r
+\r
+ /* Get the I2C flag index */\r
+ flagindex = I2C_IT >> 28;\r
+\r
+ /* Clear the flag by writing 0 */\r
+ if (flagindex == 1)\r
+ {\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 &= ~flagpos;\r
+ }\r
+ /* Flags that need a read of the SR1 register to be cleared */\r
+ else if (flagindex == 2)\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+ }\r
+ /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */\r
+ else if (flagindex == 6)\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+\r
+ /* Write on the CR1 register */\r
+ I2Cx->CR1 |= CR1_PE_Set;\r
+ }\r
+ /* Flags that need a read of SR1 and a write on CR2 registers to be cleared */\r
+ else /*flagindex == 0xA*/\r
+ {\r
+ /* Read the SR1 register */\r
+ (void)I2Cx->SR1;\r
+\r
+ /* Read the SR2 register */\r
+ (void)I2Cx->SR2;\r
+ }\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_iwdg.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the IWDG firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_iwdg.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ---------------------- IWDG registers bit mask ------------------------ */\r
+/* KR register bit mask */\r
+#define KR_Reload ((u16)0xAAAA)\r
+#define KR_Enable ((u16)0xCCCC)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : IWDG_WriteAccessCmd\r
+* Description : Enables or disables write access to IWDG_PR and IWDG_RLR\r
+* registers.\r
+* Input : - IWDG_WriteAccess: new state of write access to IWDG_PR and\r
+* IWDG_RLR registers.\r
+* This parameter can be one of the following values:\r
+* - IWDG_WriteAccess_Enable: Enable write access to \r
+* IWDG_PR and IWDG_RLR registers\r
+* - IWDG_WriteAccess_Disable: Disable write access to\r
+* IWDG_PR and IWDG_RLR registers\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void IWDG_WriteAccessCmd(u16 IWDG_WriteAccess)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r
+\r
+ IWDG->KR = IWDG_WriteAccess;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : IWDG_SetPrescaler\r
+* Description : Sets IWDG Prescaler value.\r
+* Input : - IWDG_Prescaler: specifies the IWDG Prescaler value.\r
+* This parameter can be one of the following values:\r
+* - IWDG_Prescaler_4: IWDG prescaler set to 4\r
+* - IWDG_Prescaler_8: IWDG prescaler set to 8\r
+* - IWDG_Prescaler_16: IWDG prescaler set to 16\r
+* - IWDG_Prescaler_32: IWDG prescaler set to 32\r
+* - IWDG_Prescaler_64: IWDG prescaler set to 64\r
+* - IWDG_Prescaler_128: IWDG prescaler set to 128\r
+* - IWDG_Prescaler_256: IWDG prescaler set to 256\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void IWDG_SetPrescaler(u8 IWDG_Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_IWDG_PRESCALER(IWDG_Prescaler));\r
+\r
+ IWDG->PR = IWDG_Prescaler;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : IWDG_SetReload\r
+* Description : Sets IWDG Reload value.\r
+* Input : - Reload: specifies the IWDG Reload value.\r
+* This parameter must be a number between 0 and 0x0FFF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void IWDG_SetReload(u16 Reload)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_IWDG_RELOAD(Reload));\r
+\r
+ IWDG->RLR = Reload;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : IWDG_ReloadCounter\r
+* Description : Reloads IWDG counter with value defined in the reload register\r
+* (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void IWDG_ReloadCounter(void)\r
+{\r
+ IWDG->KR = KR_Reload;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : IWDG_Enable\r
+* Description : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers\r
+* disabled).\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void IWDG_Enable(void)\r
+{\r
+ IWDG->KR = KR_Enable;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : IWDG_GetFlagStatus\r
+* Description : Checks whether the specified IWDG flag is set or not.\r
+* Input : - IWDG_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - IWDG_FLAG_PVU: Prescaler Value Update on going\r
+* - IWDG_FLAG_RVU: Reload Value Update on going\r
+* Output : None\r
+* Return : The new state of IWDG_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus IWDG_GetFlagStatus(u16 IWDG_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_IWDG_FLAG(IWDG_FLAG));\r
+\r
+ if ((IWDG->SR & IWDG_FLAG) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_lib.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all peripherals pointers initialization.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+#define EXT\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_lib.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+#ifdef DEBUG\r
+/*******************************************************************************\r
+* Function Name : debug\r
+* Description : This function initialize peripherals pointers.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void debug(void)\r
+{\r
+\r
+/************************************* ADC ************************************/\r
+#ifdef _ADC1\r
+ ADC1 = (ADC_TypeDef *) ADC1_BASE;\r
+#endif /*_ADC1 */\r
+\r
+#ifdef _ADC2\r
+ ADC2 = (ADC_TypeDef *) ADC2_BASE;\r
+#endif /*_ADC2 */\r
+\r
+/************************************* BKP ************************************/\r
+#ifdef _BKP\r
+ BKP = (BKP_TypeDef *) BKP_BASE;\r
+#endif /*_BKP */\r
+\r
+/************************************* CAN ************************************/\r
+#ifdef _CAN\r
+ CAN = (CAN_TypeDef *) CAN_BASE;\r
+#endif /*_CAN */\r
+\r
+/************************************* DMA ************************************/\r
+#ifdef _DMA\r
+ DMA = (DMA_TypeDef *) DMA_BASE;\r
+#endif /*_DMA */\r
+\r
+#ifdef _DMA_Channel1\r
+ DMA_Channel1 = (DMA_Channel_TypeDef *) DMA_Channel1_BASE;\r
+#endif /*_DMA_Channel1 */\r
+\r
+#ifdef _DMA_Channel2\r
+ DMA_Channel2 = (DMA_Channel_TypeDef *) DMA_Channel2_BASE;\r
+#endif /*_DMA_Channel2 */\r
+\r
+#ifdef _DMA_Channel3\r
+ DMA_Channel3 = (DMA_Channel_TypeDef *) DMA_Channel3_BASE;\r
+#endif /*_DMA_Channel3 */\r
+\r
+#ifdef _DMA_Channel4\r
+ DMA_Channel4 = (DMA_Channel_TypeDef *) DMA_Channel4_BASE;\r
+#endif /*_DMA_Channel4 */\r
+\r
+#ifdef _DMA_Channel5\r
+ DMA_Channel5 = (DMA_Channel_TypeDef *) DMA_Channel5_BASE;\r
+#endif /*_DMA_Channel5 */\r
+\r
+#ifdef _DMA_Channel6\r
+ DMA_Channel6 = (DMA_Channel_TypeDef *) DMA_Channel6_BASE;\r
+#endif /*_DMA_Channel6 */\r
+\r
+#ifdef _DMA_Channel7\r
+ DMA_Channel7 = (DMA_Channel_TypeDef *) DMA_Channel7_BASE;\r
+#endif /*_DMA_Channel7 */\r
+\r
+/************************************* EXTI ***********************************/\r
+#ifdef _EXTI\r
+ EXTI = (EXTI_TypeDef *) EXTI_BASE;\r
+#endif /*_EXTI */\r
+\r
+/************************************* FLASH and Option Bytes *****************/\r
+#ifdef _FLASH\r
+ FLASH = (FLASH_TypeDef *) FLASH_BASE;\r
+ OB = (OB_TypeDef *) OB_BASE;\r
+#endif /*_FLASH */\r
+\r
+/************************************* GPIO ***********************************/\r
+#ifdef _GPIOA\r
+ GPIOA = (GPIO_TypeDef *) GPIOA_BASE;\r
+#endif /*_GPIOA */\r
+\r
+#ifdef _GPIOB\r
+ GPIOB = (GPIO_TypeDef *) GPIOB_BASE;\r
+#endif /*_GPIOB */\r
+\r
+#ifdef _GPIOC\r
+ GPIOC = (GPIO_TypeDef *) GPIOC_BASE;\r
+#endif /*_GPIOC */\r
+\r
+#ifdef _GPIOD\r
+ GPIOD = (GPIO_TypeDef *) GPIOD_BASE;\r
+#endif /*_GPIOD */\r
+\r
+#ifdef _GPIOE\r
+ GPIOE = (GPIO_TypeDef *) GPIOE_BASE;\r
+#endif /*_GPIOE */\r
+\r
+#ifdef _AFIO\r
+ AFIO = (AFIO_TypeDef *) AFIO_BASE;\r
+#endif /*_AFIO */\r
+\r
+/************************************* I2C ************************************/\r
+#ifdef _I2C1\r
+ I2C1 = (I2C_TypeDef *) I2C1_BASE;\r
+#endif /*_I2C1 */\r
+\r
+#ifdef _I2C2\r
+ I2C2 = (I2C_TypeDef *) I2C2_BASE;\r
+#endif /*_I2C2 */\r
+\r
+/************************************* IWDG ***********************************/\r
+#ifdef _IWDG\r
+ IWDG = (IWDG_TypeDef *) IWDG_BASE;\r
+#endif /*_IWDG */\r
+\r
+/************************************* NVIC ***********************************/\r
+#ifdef _NVIC\r
+ NVIC = (NVIC_TypeDef *) NVIC_BASE;\r
+#endif /*_NVIC */\r
+\r
+#ifdef _SCB\r
+ SCB = (SCB_TypeDef *) SCB_BASE;\r
+#endif /*_SCB */\r
+\r
+/************************************* PWR ************************************/\r
+#ifdef _PWR\r
+ PWR = (PWR_TypeDef *) PWR_BASE;\r
+#endif /*_PWR */\r
+\r
+/************************************* RCC ************************************/\r
+#ifdef _RCC\r
+ RCC = (RCC_TypeDef *) RCC_BASE;\r
+#endif /*_RCC */\r
+\r
+/************************************* RTC ************************************/\r
+#ifdef _RTC\r
+ RTC = (RTC_TypeDef *) RTC_BASE;\r
+#endif /*_RTC */\r
+\r
+/************************************* SPI ************************************/\r
+#ifdef _SPI1\r
+ SPI1 = (SPI_TypeDef *) SPI1_BASE;\r
+#endif /*_SPI1 */\r
+\r
+#ifdef _SPI2\r
+ SPI2 = (SPI_TypeDef *) SPI2_BASE;\r
+#endif /*_SPI2 */\r
+\r
+/************************************* SysTick ********************************/\r
+#ifdef _SysTick\r
+ SysTick = (SysTick_TypeDef *) SysTick_BASE;\r
+#endif /*_SysTick */\r
+\r
+/************************************* TIM1 ***********************************/\r
+#ifdef _TIM1\r
+ TIM1 = (TIM1_TypeDef *) TIM1_BASE;\r
+#endif /*_TIM1 */\r
+\r
+/************************************* TIM ************************************/\r
+#ifdef _TIM2\r
+ TIM2 = (TIM_TypeDef *) TIM2_BASE;\r
+#endif /*_TIM2 */\r
+\r
+#ifdef _TIM3\r
+ TIM3 = (TIM_TypeDef *) TIM3_BASE;\r
+#endif /*_TIM3 */\r
+\r
+#ifdef _TIM4\r
+ TIM4 = (TIM_TypeDef *) TIM4_BASE;\r
+#endif /*_TIM4 */\r
+\r
+/************************************* USART **********************************/\r
+#ifdef _USART1\r
+ USART1 = (USART_TypeDef *) USART1_BASE;\r
+#endif /*_USART1 */\r
+\r
+#ifdef _USART2\r
+ USART2 = (USART_TypeDef *) USART2_BASE;\r
+#endif /*_USART2 */\r
+\r
+#ifdef _USART3\r
+ USART3 = (USART_TypeDef *) USART3_BASE;\r
+#endif /*_USART3 */\r
+\r
+/************************************* WWDG ***********************************/\r
+#ifdef _WWDG\r
+ WWDG = (WWDG_TypeDef *) WWDG_BASE;\r
+#endif /*_WWDG */\r
+}\r
+#endif\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_nvic.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the NVIC firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_nvic.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define AIRC_VECTKEY_MASK ((u32)0x05FA0000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_DeInit\r
+* Description : Deinitializes the NVIC peripheral registers to their default\r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_DeInit(void)\r
+{\r
+ u32 index = 0;\r
+ \r
+ NVIC->Disable[0] = 0xFFFFFFFF;\r
+ NVIC->Disable[1] = 0x000007FF;\r
+ NVIC->Clear[0] = 0xFFFFFFFF;\r
+ NVIC->Clear[1] = 0x000007FF;\r
+ \r
+ for(index = 0; index < 0x0B; index++)\r
+ {\r
+ NVIC->Priority[index] = 0x00000000;\r
+ } \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SCBDeInit\r
+* Description : Deinitializes the SCB peripheral registers to their default \r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SCBDeInit(void)\r
+{\r
+ u32 index = 0x00;\r
+ \r
+ SCB->IRQControlState = 0x0A000000;\r
+ SCB->ExceptionTableOffset = 0x00000000;\r
+ SCB->AIRC = AIRC_VECTKEY_MASK;\r
+ SCB->SysCtrl = 0x00000000;\r
+ SCB->ConfigCtrl = 0x00000000;\r
+ for(index = 0; index < 0x03; index++)\r
+ {\r
+ SCB->SystemPriority[index] = 0;\r
+ }\r
+ SCB->SysHandlerCtrl = 0x00000000;\r
+ SCB->ConfigFaultStatus = 0xFFFFFFFF;\r
+ SCB->HardFaultStatus = 0xFFFFFFFF;\r
+ SCB->DebugFaultStatus = 0xFFFFFFFF;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_PriorityGroupConfig\r
+* Description : Configures the priority grouping: pre-emption priority\r
+* and subpriority.\r
+* Input : - NVIC_PriorityGroup: specifies the priority grouping bits\r
+* length. This parameter can be one of the following values:\r
+* - NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
+* 4 bits for subpriority\r
+* - NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
+* 3 bits for subpriority\r
+* - NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
+* 2 bits for subpriority\r
+* - NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
+* 1 bits for subpriority\r
+* - NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
+* 0 bits for subpriority\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
+ SCB->AIRC = AIRC_VECTKEY_MASK | NVIC_PriorityGroup;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_Init\r
+* Description : Initializes the NVIC peripheral according to the specified\r
+* parameters in the NVIC_InitStruct.\r
+* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure\r
+* that contains the configuration information for the\r
+* specified NVIC peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00;\r
+ u32 tmppre = 0, tmpsub = 0x0F;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+ assert(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel));\r
+ assert(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
+ assert(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
+ \r
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+ {\r
+ /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
+ tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08;\r
+ tmppre = (0x4 - tmppriority);\r
+ tmpsub = tmpsub >> tmppriority;\r
+ \r
+ tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
+\r
+ tmppriority = tmppriority << 0x04;\r
+ tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);\r
+ \r
+ tmpreg = NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)];\r
+ tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);\r
+ tmpreg &= ~tmpmask;\r
+ tmppriority &= tmpmask; \r
+ tmpreg |= tmppriority;\r
+\r
+ NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg;\r
+ \r
+ /* Enable the Selected IRQ Channels --------------------------------------*/\r
+ NVIC->Enable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =\r
+ (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Selected IRQ Channels -------------------------------------*/\r
+ NVIC->Disable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =\r
+ (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_StructInit\r
+* Description : Fills each NVIC_InitStruct member with its default value.\r
+* Input : - NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure which\r
+* will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ /* NVIC_InitStruct members default value */\r
+ NVIC_InitStruct->NVIC_IRQChannel = 0x00;\r
+ NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;\r
+ NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;\r
+ NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SETPRIMASK\r
+* Description : Enables the PRIMASK priority: Raises the execution priority to 0.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SETPRIMASK(void)\r
+{\r
+ __SETPRIMASK();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_RESETPRIMASK\r
+* Description : Disables the PRIMASK priority.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_RESETPRIMASK(void)\r
+{\r
+ __RESETPRIMASK();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SETFAULTMASK\r
+* Description : Enables the FAULTMASK priority: Raises the execution priority to -1.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SETFAULTMASK(void)\r
+{\r
+ __SETFAULTMASK();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_RESETFAULTMASK\r
+* Description : Disables the FAULTMASK priority.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_RESETFAULTMASK(void)\r
+{\r
+ __RESETFAULTMASK();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_BASEPRICONFIG\r
+* Description : The execution priority can be changed from 15 (lowest \r
+ configurable priority) to 1.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_BASEPRICONFIG(u32 NewPriority)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_NVIC_BASE_PRI(NewPriority));\r
+ \r
+ __BASEPRICONFIG(NewPriority << 0x04);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetBASEPRI\r
+* Description : Returns the BASEPRI mask value.\r
+* Input : None\r
+* Output : None\r
+* Return : BASEPRI register value\r
+*******************************************************************************/\r
+u32 NVIC_GetBASEPRI(void)\r
+{\r
+ return (__GetBASEPRI());\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetCurrentPendingIRQChannel\r
+* Description : Returns the current pending IRQ channel identifier.\r
+* Input : None\r
+* Output : None\r
+* Return : Pending IRQ Channel Identifier.\r
+*******************************************************************************/\r
+u16 NVIC_GetCurrentPendingIRQChannel(void)\r
+{\r
+ return ((u16)((SCB->IRQControlState & (u32)0x003FF000) >> 0x0C));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetIRQChannelPendingBitStatus\r
+* Description : Checks whether the specified IRQ Channel pending bit is set\r
+* or not.\r
+* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to check.\r
+* Output : None\r
+* Return : The new state of IRQ Channel pending bit(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel)\r
+{\r
+ ITStatus pendingirqstatus = RESET;\r
+ u32 tmp = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));\r
+ \r
+ tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));\r
+\r
+ if (((NVIC->Set[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp)\r
+ {\r
+ pendingirqstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ pendingirqstatus = RESET;\r
+ }\r
+ return pendingirqstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SetIRQChannelPendingBit\r
+* Description : Sets the NVIC\92s interrupt pending bit.\r
+* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to Set.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));\r
+ \r
+ *(u32*)0xE000EF00 = (u32)NVIC_IRQChannel;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_ClearIRQChannelPendingBit\r
+* Description : Clears the NVIC\92s interrupt pending bit.\r
+* Input : - NVIC_IRQChannel: specifies the interrupt pending bit to clear.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));\r
+ \r
+ NVIC->Clear[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetCurrentActiveHandler\r
+* Description : Returns the current active Handler (IRQ Channel and\r
+* SystemHandler) identifier.\r
+* Input : None\r
+* Output : None\r
+* Return : Active Handler Identifier.\r
+*******************************************************************************/\r
+u16 NVIC_GetCurrentActiveHandler(void)\r
+{\r
+ return ((u16)(SCB->IRQControlState & (u32)0x3FF));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetIRQChannelActiveBitStatus\r
+* Description : Checks whether the specified IRQ Channel active bit is set\r
+* or not.\r
+* Input : - NVIC_IRQChannel: specifies the interrupt active bit to check.\r
+* Output : None\r
+* Return : The new state of IRQ Channel active bit(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel)\r
+{\r
+ ITStatus activeirqstatus = RESET;\r
+ u32 tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));\r
+ \r
+ tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));\r
+\r
+ if (((NVIC->Active[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp )\r
+ {\r
+ activeirqstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ activeirqstatus = RESET;\r
+ }\r
+ return activeirqstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetCPUID\r
+* Description : Returns the ID number, the version number and the implementation\r
+* details of the Cortex-M3 core.\r
+* Input : None\r
+* Output : None\r
+* Return : CPU ID.\r
+*******************************************************************************/\r
+u32 NVIC_GetCPUID(void)\r
+{\r
+ return (SCB->CPUID);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SetVectorTable\r
+* Description : Sets the vector table location and Offset.\r
+* Input : - NVIC_VectTab: specifies if the vector table is in RAM or\r
+* code memory.\r
+* This parameter can be one of the following values:\r
+* - NVIC_VectTab_RAM\r
+* - NVIC_VectTab_FLASH\r
+* - Offset: Vector Table base offset field.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)\r
+{ \r
+ /* Check the parameters */\r
+ assert(IS_NVIC_VECTTAB(NVIC_VectTab));\r
+ assert(IS_NVIC_OFFSET(Offset)); \r
+ \r
+ SCB->ExceptionTableOffset = (((u32)Offset << 0x07) & (u32)0x1FFFFF80);\r
+\r
+ SCB->ExceptionTableOffset |= NVIC_VectTab;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GenerateSystemReset\r
+* Description : Generates a system reset.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_GenerateSystemReset(void)\r
+{\r
+ SCB->AIRC = AIRC_VECTKEY_MASK | (u32)0x04;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GenerateCoreReset\r
+* Description : Generates a Core (Core + NVIC) reset.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_GenerateCoreReset(void)\r
+{\r
+ SCB->AIRC = AIRC_VECTKEY_MASK | (u32)0x01;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SystemLPConfig\r
+* Description : Selects the condition for the system to enter low power mode.\r
+* Input : - LowPowerMode: Specifies the new mode for the system to enter\r
+* low power mode.\r
+* This parameter can be one of the following values:\r
+* - NVIC_LP_SEVONPEND\r
+* - NVIC_LP_SLEEPDEEP\r
+* - NVIC_LP_SLEEPONEXIT\r
+* - NewState: new state of LP condition.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_NVIC_LP(LowPowerMode));\r
+ assert(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SysCtrl |= LowPowerMode;\r
+ }\r
+ else\r
+ {\r
+ SCB->SysCtrl &= (u32)(~(u32)LowPowerMode);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SystemHandlerConfig\r
+* Description : Enables or disables the specified System Handlers.\r
+* Input : - SystemHandler: specifies the system handler to be enabled\r
+* or disabled.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* - SystemHandler_UsageFault\r
+* - NewState: new state of specified System Handlers.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState)\r
+{\r
+ u32 tmpreg = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_CONFIG_SYSTEM_HANDLER(SystemHandler));\r
+ assert(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F);\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SysHandlerCtrl |= tmpreg;\r
+ }\r
+ else\r
+ {\r
+ SCB->SysHandlerCtrl &= ~tmpreg;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SystemHandlerPriorityConfig\r
+* Description : Configures the specified System Handlers priority.\r
+* Input : - SystemHandler: specifies the system handler to be\r
+* enabled or disabled.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* - SystemHandler_UsageFault\r
+* - SystemHandler_SVCall\r
+* - SystemHandler_DebugMonitor\r
+* - SystemHandler_PSV\r
+* - SystemHandler_SysTick\r
+* - SystemHandlerPreemptionPriority: new priority group of the\r
+* specified system handlers.\r
+* - SystemHandlerSubPriority: new sub priority of the specified\r
+* system handlers.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,\r
+ u8 SystemHandlerSubPriority)\r
+{\r
+ u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00;\r
+ u32 tmppriority = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler));\r
+ assert(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority)); \r
+ assert(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority));\r
+ \r
+ tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08;\r
+ tmp1 = (0x4 - tmppriority);\r
+ tmp2 = tmp2 >> tmppriority;\r
+ \r
+ tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1;\r
+ tmppriority |= SystemHandlerSubPriority & tmp2;\r
+\r
+ tmppriority = tmppriority << 0x04;\r
+ tmp1 = SystemHandler & (u32)0xC0;\r
+ tmp1 = tmp1 >> 0x06; \r
+ tmp2 = (SystemHandler >> 0x08) & (u32)0x03;\r
+ tmppriority = tmppriority << (tmp2 * 0x08);\r
+ handlermask = (u32)0xFF << (tmp2 * 0x08);\r
+ \r
+ SCB->SystemPriority[tmp1] &= ~handlermask;\r
+ SCB->SystemPriority[tmp1] |= tmppriority;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetSystemHandlerPendingBitStatus\r
+* Description : Checks whether the specified System handlers pending bit is\r
+* set or not.\r
+* Input : - SystemHandler: specifies the system handler pending bit to\r
+* check.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* - SystemHandler_SVCall\r
+* Output : None\r
+* Return : The new state of System Handler pending bit(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ u32 tmp = 0x00, tmppos = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_GET_PENDING_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ tmppos = (SystemHandler >> 0x0A);\r
+ tmppos &= (u32)0x0F;\r
+\r
+ tmppos = (u32)0x01 << tmppos;\r
+\r
+ tmp = SCB->SysHandlerCtrl & tmppos;\r
+\r
+ if (tmp == tmppos)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_SetSystemHandlerPendingBit\r
+* Description : Sets System Handler pending bit.\r
+* Input : - SystemHandler: specifies the system handler pending bit\r
+* to be set.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_NMI\r
+* - SystemHandler_PSV\r
+* - SystemHandler_SysTick\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler)\r
+{\r
+ u32 tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ /* Get the System Handler pending bit position */\r
+ tmp = SystemHandler & (u32)0x1F;\r
+ /* Set the corresponding System Handler pending bit */\r
+ SCB->IRQControlState |= ((u32)0x01 << tmp);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_ClearSystemHandlerPendingBit\r
+* Description : Clears System Handler pending bit.\r
+* Input : - SystemHandler: specifies the system handler pending bit to\r
+* be clear.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_PSV\r
+* - SystemHandler_SysTick\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler)\r
+{\r
+ u32 tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_CLEAR_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ /* Get the System Handler pending bit position */\r
+ tmp = SystemHandler & (u32)0x1F;\r
+ /* Clear the corresponding System Handler pending bit */\r
+ SCB->IRQControlState |= ((u32)0x01 << (tmp - 0x01));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetSystemHandlerActiveBitStatus\r
+* Description : Checks whether the specified System handlers active bit is\r
+* set or not.\r
+* Input : - SystemHandler: specifies the system handler active bit to\r
+* check.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* - SystemHandler_UsageFault\r
+* - SystemHandler_SVCall\r
+* - SystemHandler_DebugMonitor\r
+* - SystemHandler_PSV\r
+* - SystemHandler_SysTick\r
+* Output : None\r
+* Return : The new state of System Handler active bit(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ u32 tmp = 0x00, tmppos = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_GET_ACTIVE_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ tmppos = (SystemHandler >> 0x0E) & (u32)0x0F;\r
+\r
+ tmppos = (u32)0x01 << tmppos;\r
+\r
+ tmp = SCB->SysHandlerCtrl & tmppos;\r
+\r
+ if (tmp == tmppos)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetFaultHandlerSources\r
+* Description : Returns the system fault handlers sources.\r
+* Input : - SystemHandler: specifies the system handler to get its fault\r
+* sources.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_HardFault\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* - SystemHandler_UsageFault\r
+* - SystemHandler_DebugMonitor\r
+* Output : None\r
+* Return : Source of the fault handler.\r
+*******************************************************************************/\r
+u32 NVIC_GetFaultHandlerSources(u32 SystemHandler)\r
+{\r
+ u32 faultsources = 0x00;\r
+ u32 tmpreg = 0x00, tmppos = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ tmpreg = (SystemHandler >> 0x12) & (u32)0x03;\r
+ tmppos = (SystemHandler >> 0x14) & (u32)0x03;\r
+\r
+ if (tmpreg == 0x00)\r
+ {\r
+ faultsources = SCB->HardFaultStatus;\r
+ }\r
+ else if (tmpreg == 0x01)\r
+ {\r
+ faultsources = SCB->ConfigFaultStatus >> (tmppos * 0x08);\r
+ if (tmppos != 0x02)\r
+ {\r
+ faultsources &= (u32)0x0F;\r
+ }\r
+ else\r
+ {\r
+ faultsources &= (u32)0xFF;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ faultsources = SCB->DebugFaultStatus;\r
+ }\r
+ return faultsources;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : NVIC_GetFaultAddress\r
+* Description : Returns the address of the location that generated a fault\r
+* handler.\r
+* Input : - SystemHandler: specifies the system handler to get its\r
+* fault address.\r
+* This parameter can be one of the following values:\r
+* - SystemHandler_MemoryManage\r
+* - SystemHandler_BusFault\r
+* Output : None\r
+* Return : Fault address.\r
+*******************************************************************************/\r
+u32 NVIC_GetFaultAddress(u32 SystemHandler)\r
+{\r
+ u32 faultaddress = 0x00;\r
+ u32 tmp = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler));\r
+ \r
+ tmp = (SystemHandler >> 0x16) & (u32)0x01;\r
+\r
+ if (tmp == 0x00)\r
+ {\r
+ faultaddress = SCB->MemoryManageFaultAddr;\r
+ }\r
+ else\r
+ {\r
+ faultaddress = SCB->BusFaultAddr;\r
+ }\r
+ return faultaddress;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_pwr.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the PWR firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_pwr.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* --------- PWR registers bit address in the alias region ---------- */\r
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+/* Alias word address of DBP bit */\r
+#define CR_OFFSET (PWR_OFFSET + 0x00)\r
+#define DBP_BitNumber 0x08\r
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
+\r
+/* Alias word address of PVDE bit */\r
+#define PVDE_BitNumber 0x04\r
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+/* Alias word address of EWUP bit */\r
+#define CSR_OFFSET (PWR_OFFSET + 0x04)\r
+#define EWUP_BitNumber 0x08\r
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
+\r
+/* ------------------ PWR registers bit mask ------------------------ */\r
+/* CR register bit mask */\r
+#define CR_PDDS_Set ((u32)0x00000002)\r
+#define CR_DS_Mask ((u32)0xFFFFFFFC)\r
+#define CR_CWUF_Set ((u32)0x00000004)\r
+#define CR_PLS_Mask ((u32)0xFFFFFF1F)\r
+\r
+/* --------- Cortex System Control register bit mask ---------------- */\r
+/* Cortex System Control register address */\r
+#define SCB_SysCtrl ((u32)0xE000ED10)\r
+/* SLEEPDEEP bit mask */\r
+#define SysCtrl_SLEEPDEEP_Set ((u32)0x00000004)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : PWR_DeInit\r
+* Description : Deinitializes the PWR peripheral registers to their default\r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWR_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWR_BackupAccessCmd\r
+* Description : Enables or disables access to the RTC and backup registers.\r
+* Input : - NewState: new state of the access to the RTC and backup\r
+* registers. This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWR_BackupAccessCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CR_DBP_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWR_PVDCmd\r
+* Description : Enables or disables the Power Voltage Detector(PVD).\r
+* Input : - NewState: new state of the PVD.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWR_PVDCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CR_PVDE_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWR_PVDLevelConfig\r
+* Description : Configures the value detected by the Power Voltage Detector(PVD).\r
+* Input : - PWR_PVDLevel: specifies the PVD detection level\r
+* This parameter can be one of the following values:\r
+* - PWR_PVDLevel_2V2: PVD detection level set to 2.2V\r
+* - PWR_PVDLevel_2V3: PVD detection level set to 2.3V\r
+* - PWR_PVDLevel_2V4: PVD detection level set to 2.4V\r
+* - PWR_PVDLevel_2V5: PVD detection level set to 2.5V\r
+* - PWR_PVDLevel_2V6: PVD detection level set to 2.6V\r
+* - PWR_PVDLevel_2V7: PVD detection level set to 2.7V\r
+* - PWR_PVDLevel_2V8: PVD detection level set to 2.8V\r
+* - PWR_PVDLevel_2V9: PVD detection level set to 2.9V\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWR_PVDLevelConfig(u32 PWR_PVDLevel)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
+\r
+ tmpreg = PWR->CR;\r
+\r
+ /* Clear PLS[7:5] bits */\r
+ tmpreg &= CR_PLS_Mask;\r
+\r
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
+ tmpreg |= PWR_PVDLevel;\r
+\r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWR_WakeUpPinCmd\r
+* Description : Enables or disables the WakeUp Pin functionality.\r
+* Input : - NewState: new state of the WakeUp Pin functionality.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWR_WakeUpPinCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CSR_EWUP_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWR_EnterSTOPMode\r
+* Description : Enters STOP mode.\r
+* Input : - PWR_Regulator: specifies the regulator state in STOP mode.\r
+* This parameter can be one of the following values:\r
+* - PWR_Regulator_ON: STOP mode with regulator ON\r
+* - PWR_Regulator_LowPower: STOP mode with\r
+* regulator in low power mode\r
+* - PWR_STOPEntry: specifies if STOP mode in entered with WFI or \r
+* WFE instruction.\r
+* This parameter can be one of the following values:\r
+* - PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
+* - PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWR_EnterSTOPMode(u32 PWR_Regulator, u8 PWR_STOPEntry)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_PWR_REGULATOR(PWR_Regulator));\r
+ assert(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
+ \r
+ /* Select the regulator state in STOP mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+\r
+ /* Clear PDDS and LPDS bits */\r
+ tmpreg &= CR_DS_Mask;\r
+\r
+ /* Set LPDS bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+\r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;\r
+ \r
+ /* Select STOP mode entry --------------------------------------------------*/\r
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWR_EnterSTANDBYMode\r
+* Description : Enters STANDBY mode.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Clear Wake-up flag */\r
+ PWR->CR |= CR_CWUF_Set;\r
+\r
+ /* Select STANDBY mode */\r
+ PWR->CR |= CR_PDDS_Set;\r
+\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ *(vu32 *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;\r
+\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWR_GetFlagStatus\r
+* Description : Checks whether the specified PWR flag is set or not.\r
+* Input : - PWR_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - PWR_FLAG_WU: Wake Up flag\r
+* - PWR_FLAG_SB: StandBy flag\r
+* - PWR_FLAG_PVDO: PVD Output\r
+* Output : None\r
+* Return : The new state of PWR_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus PWR_GetFlagStatus(u32 PWR_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_PWR_GET_FLAG(PWR_FLAG));\r
+ \r
+ if ((PWR->CSR & PWR_FLAG) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWR_ClearFlag\r
+* Description : Clears the PWR's pending flags.\r
+* Input : - PWR_FLAG: specifies the flag to clear.\r
+* This parameter can be one of the following values:\r
+* - PWR_FLAG_WU: Wake Up flag\r
+* - PWR_FLAG_SB: StandBy flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void PWR_ClearFlag(u32 PWR_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
+ \r
+ PWR->CR |= PWR_FLAG << 2;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_rcc.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the RCC firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+/* Alias word address of HSION bit */\r
+#define CR_OFFSET (RCC_OFFSET + 0x00)\r
+#define HSION_BitNumber 0x00\r
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
+\r
+/* Alias word address of PLLON bit */\r
+#define PLLON_BitNumber 0x18\r
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
+\r
+/* Alias word address of CSSON bit */\r
+#define CSSON_BitNumber 0x13\r
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
+\r
+/* --- CFGR Register ---*/\r
+/* Alias word address of USBPRE bit */\r
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)\r
+#define USBPRE_BitNumber 0x16\r
+#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))\r
+\r
+/* --- BDCR Register ---*/\r
+/* Alias word address of RTCEN bit */\r
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)\r
+#define RTCEN_BitNumber 0x0F\r
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
+\r
+/* Alias word address of BDRST bit */\r
+#define BDRST_BitNumber 0x10\r
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+/* Alias word address of LSION bit */\r
+#define CSR_OFFSET (RCC_OFFSET + 0x24)\r
+#define LSION_BitNumber 0x00\r
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
+\r
+/* ---------------------- RCC registers bit mask ------------------------ */\r
+/* CR register bit mask */\r
+#define CR_HSEBYP_Reset ((u32)0xFFFBFFFF)\r
+#define CR_HSEBYP_Set ((u32)0x00040000)\r
+#define CR_HSEON_Reset ((u32)0xFFFEFFFF)\r
+#define CR_HSEON_Set ((u32)0x00010000)\r
+#define CR_HSITRIM_Mask ((u32)0xFFFFFF07)\r
+\r
+/* CFGR register bit mask */\r
+#define CFGR_PLL_Mask ((u32)0xFFC0FFFF)\r
+#define CFGR_PLLMull_Mask ((u32)0x003C0000)\r
+#define CFGR_PLLSRC_Mask ((u32)0x00010000)\r
+#define CFGR_PLLXTPRE_Mask ((u32)0x00020000)\r
+#define CFGR_SWS_Mask ((u32)0x0000000C)\r
+#define CFGR_SW_Mask ((u32)0xFFFFFFFC)\r
+#define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F)\r
+#define CFGR_HPRE_Set_Mask ((u32)0x000000F0)\r
+#define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF)\r
+#define CFGR_PPRE1_Set_Mask ((u32)0x00000700)\r
+#define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF)\r
+#define CFGR_PPRE2_Set_Mask ((u32)0x00003800)\r
+#define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF)\r
+#define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000)\r
+\r
+/* CSR register bit mask */\r
+#define CSR_RVMF_Set ((u32)0x01000000)\r
+\r
+/* RCC Flag Mask */\r
+#define FLAG_Mask ((u8)0x1F)\r
+\r
+/* Typical Value of the HSI in Hz */\r
+#define HSI_Value ((u32)8000000)\r
+\r
+/* BDCR register base address */\r
+#define BDCR_BASE (PERIPH_BASE + BDCR_OFFSET)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+static uc8 ADCPrescTable[4] = {2, 4, 6, 8};\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_DeInit\r
+* Description : Deinitializes the RCC peripheral registers to their default\r
+* reset values.\r
+* - The HSITRIM[4:0] bits in RCC_CR register are not modified\r
+* by this function.\r
+* - The RCC_BDCR and RCC_CSR registers are not reset by this\r
+* function.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_DeInit(void)\r
+{\r
+ /* Disable APB2 Peripheral Reset */\r
+ RCC->APB2RSTR = 0x00000000;\r
+\r
+ /* Disable APB1 Peripheral Reset */\r
+ RCC->APB1RSTR = 0x00000000;\r
+\r
+ /* FLITF and SRAM Clock ON */\r
+ RCC->AHBENR = 0x00000014;\r
+\r
+ /* Disable APB2 Peripheral Clock */\r
+ RCC->APB2ENR = 0x00000000;\r
+\r
+ /* Disable APB1 Peripheral Clock */\r
+ RCC->APB1ENR = 0x00000000;\r
+\r
+ /* Set HSION bit */\r
+ RCC->CR |= (u32)0x00000001;\r
+\r
+ /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/\r
+ RCC->CFGR &= 0xF8FF0000;\r
+ \r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= 0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= 0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */\r
+ RCC->CFGR &= 0xFF80FFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_HSEConfig\r
+* Description : Configures the External High Speed oscillator (HSE).\r
+* Input : - RCC_HSE: specifies the new state of the HSE.\r
+* This parameter can be one of the following values:\r
+* - RCC_HSE_OFF: HSE oscillator OFF\r
+* - RCC_HSE_ON: HSE oscillator ON\r
+* - RCC_HSE_Bypass: HSE oscillator bypassed with external\r
+* clock\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_HSEConfig(u32 RCC_HSE)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_HSE(RCC_HSE));\r
+\r
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+ /* Reset HSEON bit */\r
+ RCC->CR &= CR_HSEON_Reset;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= CR_HSEBYP_Reset;\r
+\r
+ /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */\r
+ switch(RCC_HSE)\r
+ {\r
+ case RCC_HSE_ON:\r
+ /* Set HSEON bit */\r
+ RCC->CR |= CR_HSEON_Set;\r
+ break;\r
+ \r
+ case RCC_HSE_Bypass:\r
+ /* Set HSEBYP and HSEON bits */\r
+ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;\r
+ break; \r
+ \r
+ default:\r
+ break; \r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_AdjustHSICalibrationValue\r
+* Description : Adjusts the Internal High Speed oscillator (HSI) calibration\r
+* value.\r
+* Input : - HSICalibrationValue: specifies the calibration trimming value.\r
+* This parameter must be a number between 0 and 0x1F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));\r
+\r
+ tmpreg = RCC->CR;\r
+\r
+ /* Clear HSITRIM[7:3] bits */\r
+ tmpreg &= CR_HSITRIM_Mask;\r
+\r
+ /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */\r
+ tmpreg |= (u32)HSICalibrationValue << 3;\r
+\r
+ /* Store the new value */\r
+ RCC->CR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_HSICmd\r
+* Description : Enables or disables the Internal High Speed oscillator (HSI).\r
+* HSI can not be stopped if it is used directly or through the \r
+* PLL as system clock, or if a Flash programmation is on going.\r
+* Input : - NewState: new state of the HSI.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CR_HSION_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_PLLConfig\r
+* Description : Configures the PLL clock source and multiplication factor.\r
+* This function must be used only when the PLL is disabled.\r
+* Input : - RCC_PLLSource: specifies the PLL entry clock source.\r
+* This parameter can be one of the following values:\r
+* - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided\r
+* by 2 selected as PLL clock entry\r
+* - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected\r
+* as PLL clock entry\r
+* - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided\r
+* by 2 selected as PLL clock entry\r
+* - RCC_PLLMul: specifies the PLL multiplication factor.\r
+* This parameter can be RCC_PLLMul_x where x:[2,16]\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+ assert(IS_RCC_PLL_MUL(RCC_PLLMul));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */\r
+ tmpreg &= CFGR_PLL_Mask;\r
+\r
+ /* Set the PLL configuration bits */\r
+ tmpreg |= RCC_PLLSource | RCC_PLLMul;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_PLLCmd\r
+* Description : Enables or disables the PLL.\r
+* The PLL can not be disabled if it is used as system clock.\r
+* Input : - NewState: new state of the PLL.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CR_PLLON_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_SYSCLKConfig\r
+* Description : Configures the system clock (SYSCLK).\r
+* Input : - RCC_SYSCLKSource: specifies the clock source used as system\r
+* clock. This parameter can be one of the following values:\r
+* - RCC_SYSCLKSource_HSI: HSI selected as system clock\r
+* - RCC_SYSCLKSource_HSE: HSE selected as system clock\r
+* - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear SW[1:0] bits */\r
+ tmpreg &= CFGR_SW_Mask;\r
+\r
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+ tmpreg |= RCC_SYSCLKSource;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_GetSYSCLKSource\r
+* Description : Returns the clock source used as system clock.\r
+* Input : None\r
+* Output : None\r
+* Return : The clock source used as system clock. The returned value can\r
+* be one of the following:\r
+* - 0x00: HSI used as system clock\r
+* - 0x04: HSE used as system clock\r
+* - 0x08: PLL used as system clock\r
+*******************************************************************************/\r
+u8 RCC_GetSYSCLKSource(void)\r
+{\r
+ return ((u8)(RCC->CFGR & CFGR_SWS_Mask));\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_HCLKConfig\r
+* Description : Configures the AHB clock (HCLK).\r
+* Input : - RCC_HCLK: defines the AHB clock. This clock is derived\r
+* from the system clock (SYSCLK).\r
+* This parameter can be one of the following values:\r
+* - RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
+* - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
+* - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
+* - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
+* - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
+* - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
+* - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+* - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+* - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_HCLKConfig(u32 RCC_HCLK)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_RCC_HCLK(RCC_HCLK));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear HPRE[7:4] bits */\r
+ tmpreg &= CFGR_HPRE_Reset_Mask;\r
+\r
+ /* Set HPRE[7:4] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_PCLK1Config\r
+* Description : Configures the Low Speed APB clock (PCLK1).\r
+* Input : - RCC_PCLK1: defines the APB1 clock. This clock is derived\r
+* from the AHB clock (HCLK).\r
+* This parameter can be one of the following values:\r
+* - RCC_HCLK_Div1: APB1 clock = HCLK\r
+* - RCC_HCLK_Div2: APB1 clock = HCLK/2\r
+* - RCC_HCLK_Div4: APB1 clock = HCLK/4\r
+* - RCC_HCLK_Div8: APB1 clock = HCLK/8\r
+* - RCC_HCLK_Div16: APB1 clock = HCLK/16\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_PCLK1Config(u32 RCC_PCLK1)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_RCC_PCLK(RCC_PCLK1));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear PPRE1[10:8] bits */\r
+ tmpreg &= CFGR_PPRE1_Reset_Mask;\r
+\r
+ /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */\r
+ tmpreg |= RCC_PCLK1;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_PCLK2Config\r
+* Description : Configures the High Speed APB clock (PCLK2).\r
+* Input : - RCC_PCLK2: defines the APB2 clock. This clock is derived\r
+* from the AHB clock (HCLK).\r
+* This parameter can be one of the following values:\r
+* - RCC_HCLK_Div1: APB2 clock = HCLK\r
+* - RCC_HCLK_Div2: APB2 clock = HCLK/2\r
+* - RCC_HCLK_Div4: APB2 clock = HCLK/4\r
+* - RCC_HCLK_Div8: APB2 clock = HCLK/8\r
+* - RCC_HCLK_Div16: APB2 clock = HCLK/16\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_PCLK2Config(u32 RCC_PCLK2)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_RCC_PCLK(RCC_PCLK2));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear PPRE2[13:11] bits */\r
+ tmpreg &= CFGR_PPRE2_Reset_Mask;\r
+\r
+ /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */\r
+ tmpreg |= RCC_PCLK2 << 3;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_ITConfig\r
+* Description : Enables or disables the specified RCC interrupts.\r
+* Input : - RCC_IT: specifies the RCC interrupt sources to be enabled\r
+* or disabled.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_IT_LSIRDY: LSI ready interrupt\r
+* - RCC_IT_LSERDY: LSE ready interrupt\r
+* - RCC_IT_HSIRDY: HSI ready interrupt\r
+* - RCC_IT_HSERDY: HSE ready interrupt\r
+* - RCC_IT_PLLRDY: PLL ready interrupt\r
+* - NewState: new state of the specified RCC interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_IT(RCC_IT));\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */\r
+ *(vu8 *) 0x40021009 |= RCC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */\r
+ *(vu8 *) 0x40021009 &= ~(u32)RCC_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_USBCLKConfig\r
+* Description : Configures the USB clock (USBCLK).\r
+* Input : - RCC_USBCLKSource: specifies the USB clock source. This clock\r
+* is derived from the PLL output.\r
+* This parameter can be one of the following values:\r
+* - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5\r
+* selected as USB clock source\r
+* - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB\r
+* clock source\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_USBCLKConfig(u32 RCC_USBCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));\r
+\r
+ *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_ADCCLKConfig\r
+* Description : Configures the ADC clock (ADCCLK).\r
+* Input : - RCC_ADCCLK: defines the ADC clock. This clock is derived\r
+* from the APB2 clock (PCLK2).\r
+* This parameter can be one of the following values:\r
+* - RCC_PCLK2_Div2: ADC clock = PCLK2/2\r
+* - RCC_PCLK2_Div4: ADC clock = PCLK2/4\r
+* - RCC_PCLK2_Div6: ADC clock = PCLK2/6\r
+* - RCC_PCLK2_Div8: ADC clock = PCLK2/8\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_ADCCLKConfig(u32 RCC_ADCCLK)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_RCC_ADCCLK(RCC_ADCCLK));\r
+\r
+ tmpreg = RCC->CFGR;\r
+\r
+ /* Clear ADCPRE[15:14] bits */\r
+ tmpreg &= CFGR_ADCPRE_Reset_Mask;\r
+\r
+ /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */\r
+ tmpreg |= RCC_ADCCLK;\r
+\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_LSEConfig\r
+* Description : Configures the External Low Speed oscillator (LSE).\r
+* Input : - RCC_LSE: specifies the new state of the LSE.\r
+* This parameter can be one of the following values:\r
+* - RCC_LSE_OFF: LSE oscillator OFF\r
+* - RCC_LSE_ON: LSE oscillator ON\r
+* - RCC_LSE_Bypass: LSE oscillator bypassed with external\r
+* clock\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_LSEConfig(u32 RCC_LSE)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_LSE(RCC_LSE));\r
+\r
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+ /* Reset LSEON bit */\r
+ *(vu8 *) BDCR_BASE = RCC_LSE_OFF;\r
+\r
+ /* Reset LSEBYP bit */\r
+ *(vu8 *) BDCR_BASE = RCC_LSE_OFF;\r
+\r
+ /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */\r
+ switch(RCC_LSE)\r
+ {\r
+ case RCC_LSE_ON:\r
+ /* Set LSEON bit */\r
+ *(vu8 *) BDCR_BASE = RCC_LSE_ON;\r
+ break;\r
+ \r
+ case RCC_LSE_Bypass:\r
+ /* Set LSEBYP and LSEON bits */\r
+ *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON;\r
+ break; \r
+ \r
+ default:\r
+ break; \r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_LSICmd\r
+* Description : Enables or disables the Internal Low Speed oscillator (LSI).\r
+* LSI can not be disabled if the IWDG is running.\r
+* Input : - NewState: new state of the LSI.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CSR_LSION_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_RTCCLKConfig\r
+* Description : Configures the RTC clock (RTCCLK).\r
+* Once the RTC clock is selected it can\92t be changed unless the\r
+* Backup domain is reset.\r
+* Input : - RCC_RTCCLKSource: specifies the RTC clock source.\r
+* This parameter can be one of the following values:\r
+* - RCC_RTCCLKSource_LSE: LSE oscillator clock used as RTC\r
+* clock\r
+* - RCC_RTCCLKSource_LSI: LSI oscillator clock used as RTC\r
+* clock\r
+* - RCC_RTCCLKSource_HSE_Div128: HSE oscillator clock divided\r
+* by 128 used as RTC clock\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+\r
+ /* Select the RTC clock source */\r
+ RCC->BDCR |= RCC_RTCCLKSource;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_RTCCLKCmd\r
+* Description : Enables or disables the RTC clock.\r
+* This function must be used only after the RTC clock was\r
+* selected using the RCC_RTCCLKConfig function.\r
+* Input : - NewState: new state of the RTC clock.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_GetClocksFreq\r
+* Description : Returns the frequencies of different on chip clocks.\r
+* Input : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which\r
+* will hold the clocks frequencies.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+ u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;\r
+\r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & CFGR_SWS_Mask;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;\r
+ break;\r
+\r
+ case 0x04: /* HSE used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value;\r
+ break;\r
+\r
+ case 0x08: /* PLL used as system clock */\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmull = RCC->CFGR & CFGR_PLLMull_Mask;\r
+ pllmull = ( pllmull >> 18) + 2;\r
+\r
+ pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;\r
+\r
+ if (pllsource == 0x00)\r
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;\r
+ }\r
+ else\r
+ {/* HSE selected as PLL clock entry */\r
+\r
+ if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)\r
+ {/* HSE oscillator clock divided by 2 */\r
+\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;\r
+ }\r
+ else\r
+ {\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;\r
+ }\r
+ }\r
+ break;\r
+\r
+ default:\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;\r
+ break;\r
+ }\r
+\r
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;\r
+ tmp = tmp >> 4;\r
+ presc = APBAHBPrescTable[tmp];\r
+\r
+ /* HCLK clock frequency */\r
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK1 prescaler */\r
+ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;\r
+ tmp = tmp >> 8;\r
+ presc = APBAHBPrescTable[tmp];\r
+\r
+ /* PCLK1 clock frequency */\r
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+\r
+ /* Get PCLK2 prescaler */\r
+ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;\r
+ tmp = tmp >> 11;\r
+ presc = APBAHBPrescTable[tmp];\r
+\r
+ /* PCLK2 clock frequency */\r
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+\r
+ /* Get ADCCLK prescaler */\r
+ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;\r
+ tmp = tmp >> 14;\r
+ presc = ADCPrescTable[tmp];\r
+\r
+ /* ADCCLK clock frequency */\r
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_AHBPeriphClockCmd\r
+* Description : Enables or disables the AHB peripheral clock.\r
+* Input : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_AHBPeriph_DMA\r
+* - RCC_AHBPeriph_SRAM\r
+* - RCC_AHBPeriph_FLITF\r
+* SRAM and FLITF clock can be disabled only during sleep mode.\r
+* - NewState: new state of the specified peripheral clock.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_APB2PeriphClockCmd\r
+* Description : Enables or disables the High Speed APB (APB2) peripheral clock.\r
+* Input : - RCC_APB2Periph: specifies the APB2 peripheral to gates its\r
+* clock.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB\r
+* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE\r
+* RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1\r
+* RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL\r
+* - NewState: new state of the specified peripheral clock.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2ENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2ENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_APB1PeriphClockCmd\r
+* Description : Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+* Input : - RCC_APB1Periph: specifies the APB1 peripheral to gates its\r
+* clock.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4\r
+* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2\r
+* RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2\r
+* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP\r
+* RCC_APB1Periph_PWR, RCC_APB1Periph_ALL\r
+* - NewState: new state of the specified peripheral clock.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1ENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1ENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_APB2PeriphResetCmd\r
+* Description : Forces or releases High Speed APB (APB2) peripheral reset.\r
+* Input : - RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB\r
+* RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE\r
+* RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1\r
+* RCC_APB2Periph_SPI1, RCC_APB2Periph_USART1, RCC_APB2Periph_ALL\r
+* - NewState: new state of the specified peripheral reset.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2RSTR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_APB1PeriphResetCmd\r
+* Description : Forces or releases Low Speed APB (APB1) peripheral reset.\r
+* Input : - RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4\r
+* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_USART2\r
+* RCC_APB1Periph_USART3, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2\r
+* RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP\r
+* RCC_APB1Periph_PWR, RCC_APB1Periph_ALL\r
+* - NewState: new state of the specified peripheral clock.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1RSTR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_BackupResetCmd\r
+* Description : Forces or releases the Backup domain reset.\r
+* Input : - NewState: new state of the Backup domain reset.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_BackupResetCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) BDCR_BDRST_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_ClockSecuritySystemCmd\r
+* Description : Enables or disables the Clock Security System.\r
+* Input : - NewState: new state of the Clock Security System..\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(vu32 *) CR_CSSON_BB = (u32)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_MCOConfig\r
+* Description : Selects the clock source to output on MCO pin.\r
+* Input : - RCC_MCO: specifies the clock source to output.\r
+* This parameter can be one of the following values:\r
+* - RCC_MCO_NoClock: No clock selected\r
+* - RCC_MCO_SYSCLK: System clock selected\r
+* - RCC_MCO_HSI: HSI oscillator clock selected\r
+* - RCC_MCO_HSE: HSE oscillator clock selected\r
+* - RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_MCOConfig(u8 RCC_MCO)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_MCO(RCC_MCO));\r
+\r
+ /* Perform Byte access to MCO[26:24] bits to select the MCO source */\r
+ *(vu8 *) 0x40021007 = RCC_MCO;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_GetFlagStatus\r
+* Description : Checks whether the specified RCC flag is set or not.\r
+* Input : - RCC_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+* - RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+* - RCC_FLAG_PLLRDY: PLL clock ready\r
+* - RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+* - RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+* - RCC_FLAG_PINRST: Pin reset\r
+* - RCC_FLAG_PORRST: POR/PDR reset\r
+* - RCC_FLAG_SFTRST: Software reset\r
+* - RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+* - RCC_FLAG_WWDGRST: Window Watchdog reset\r
+* - RCC_FLAG_LPWRRST: Low Power reset\r
+* Output : None\r
+* Return : The new state of RCC_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)\r
+{\r
+ u32 tmp = 0;\r
+ u32 statusreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+ /* Get the RCC register index */\r
+ tmp = RCC_FLAG >> 5;\r
+\r
+ if (tmp == 1) /* The flag to check is in CR register */\r
+ {\r
+ statusreg = RCC->CR;\r
+ }\r
+ else if (tmp == 2) /* The flag to check is in BDCR register */\r
+ {\r
+ statusreg = RCC->BDCR;\r
+ }\r
+ else /* The flag to check is in CSR register */\r
+ {\r
+ statusreg = RCC->CSR;\r
+ }\r
+\r
+ /* Get the flag position */\r
+ tmp = RCC_FLAG & FLAG_Mask;\r
+\r
+ if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_ClearFlag\r
+* Description : Clears the RCC reset flags.\r
+* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,\r
+* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,\r
+* RCC_FLAG_LPWRRST\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_ClearFlag(void)\r
+{\r
+ /* Set RVMF bit to clear the reset flags */\r
+ RCC->CSR |= CSR_RVMF_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_GetITStatus\r
+* Description : Checks whether the specified RCC interrupt has occurred or not.\r
+* Input : - RCC_IT: specifies the RCC interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - RCC_IT_LSIRDY: LSI ready interrupt\r
+* - RCC_IT_LSERDY: LSE ready interrupt\r
+* - RCC_IT_HSIRDY: HSI ready interrupt\r
+* - RCC_IT_HSERDY: HSE ready interrupt\r
+* - RCC_IT_PLLRDY: PLL ready interrupt\r
+* - RCC_IT_CSS: Clock Security System interrupt\r
+* Output : None\r
+* Return : The new state of RCC_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus RCC_GetITStatus(u8 RCC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_RCC_GET_IT(RCC_IT));\r
+\r
+ /* Check the status of the specified RCC interrupt */\r
+ if ((RCC->CIR & RCC_IT) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the RCC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RCC_ClearITPendingBit\r
+* Description : Clears the RCC\92s interrupt pending bits.\r
+* Input : - RCC_IT: specifies the interrupt pending bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - RCC_IT_LSIRDY: LSI ready interrupt\r
+* - RCC_IT_LSERDY: LSE ready interrupt\r
+* - RCC_IT_HSIRDY: HSI ready interrupt\r
+* - RCC_IT_HSERDY: HSE ready interrupt\r
+* - RCC_IT_PLLRDY: PLL ready interrupt\r
+* - RCC_IT_CSS: Clock Security System interrupt\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RCC_ClearITPendingBit(u8 RCC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RCC_CLEAR_IT(RCC_IT));\r
+\r
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+ pending bits */\r
+ *(vu8 *) 0x4002100A = RCC_IT;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_rtc.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the RTC firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_rtc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define CRL_CNF_Set ((u16)0x0010) /* Configuration Flag Enable Mask */\r
+#define CRL_CNF_Reset ((u16)0xFFEF) /* Configuration Flag Disable Mask */\r
+#define RTC_LSB_Mask ((u32)0x0000FFFF) /* RTC LSB Mask */\r
+#define RTC_MSB_Mask ((u32)0xFFFF0000) /* RTC MSB Mask */\r
+#define PRLH_MSB_Mask ((u32)0x000F0000) /* RTC Prescaler MSB Mask */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_ITConfig\r
+* Description : Enables or disables the specified RTC interrupts.\r
+* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled\r
+* or disabled.\r
+* This parameter can be any combination of the following values:\r
+* - RTC_IT_OW: Overflow interrupt\r
+* - RTC_IT_ALR: Alarm interrupt\r
+* - RTC_IT_SEC: Second interrupt\r
+* - NewState: new state of the specified RTC interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RTC_IT(RTC_IT)); \r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RTC->CRH |= RTC_IT;\r
+ }\r
+ else\r
+ {\r
+ RTC->CRH &= (u16)~RTC_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_EnterConfigMode\r
+* Description : Enters the RTC configuration mode.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_EnterConfigMode(void)\r
+{\r
+ /* Set the CNF flag to enter in the Configuration Mode */\r
+ RTC->CRL |= CRL_CNF_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_ExitConfigMode\r
+* Description : Exits from the RTC configuration mode.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_ExitConfigMode(void)\r
+{\r
+ /* Reset the CNF flag to exit from the Configuration Mode */\r
+ RTC->CRL &= CRL_CNF_Reset;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_GetCounter\r
+* Description : Gets the RTC counter value.\r
+* Input : None\r
+* Output : None\r
+* Return : RTC counter value.\r
+*******************************************************************************/\r
+u32 RTC_GetCounter(void)\r
+{\r
+ u16 tmp = 0;\r
+ tmp = RTC->CNTL;\r
+\r
+ return (((u32)RTC->CNTH << 16 ) | tmp) ;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_SetCounter\r
+* Description : Sets the RTC counter value.\r
+* Input : - CounterValue: RTC counter new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_SetCounter(u32 CounterValue)\r
+{ \r
+ RTC_EnterConfigMode();\r
+\r
+ /* Set RTC COUNTER MSB word */\r
+ RTC->CNTH = (CounterValue & RTC_MSB_Mask) >> 16;\r
+ /* Set RTC COUNTER LSB word */\r
+ RTC->CNTL = (CounterValue & RTC_LSB_Mask);\r
+\r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_GetPrescaler\r
+* Description : Gets the RTC prescaler value.\r
+* Input : None\r
+* Output : None\r
+* Return : RTC prescaler value.\r
+*******************************************************************************/\r
+u32 RTC_GetPrescaler(void)\r
+{\r
+ u32 tmp = 0x00;\r
+\r
+ tmp = ((u32)RTC->PRLH & (u32)0x000F) << 0x10;\r
+ tmp |= RTC->PRLL;\r
+\r
+ return tmp;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_SetPrescaler\r
+* Description : Sets the RTC prescaler value.\r
+* Input : - PrescalerValue: RTC prescaler new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_SetPrescaler(u32 PrescalerValue)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RTC_PRESCALER(PrescalerValue));\r
+ \r
+ RTC_EnterConfigMode();\r
+\r
+ /* Set RTC PRESCALER MSB word */\r
+ RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 0x10;\r
+ /* Set RTC PRESCALER LSB word */\r
+ RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);\r
+\r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_SetAlarm\r
+* Description : Sets the RTC alarm value.\r
+* Input : - AlarmValue: RTC alarm new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_SetAlarm(u32 AlarmValue)\r
+{ \r
+ RTC_EnterConfigMode();\r
+\r
+ /* Set the ALARM MSB word */\r
+ RTC->ALRH = (AlarmValue & RTC_MSB_Mask) >> 16;\r
+ /* Set the ALARM LSB word */\r
+ RTC->ALRL = (AlarmValue & RTC_LSB_Mask);\r
+\r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_GetDivider\r
+* Description : Gets the RTC divider value.\r
+* Input : None\r
+* Output : None\r
+* Return : RTC Divider value.\r
+*******************************************************************************/\r
+u32 RTC_GetDivider(void)\r
+{\r
+ u32 tmp = 0x00;\r
+\r
+ tmp = ((u32)RTC->DIVH & (u32)0x000F) << 0x10;\r
+ tmp |= RTC->DIVL;\r
+\r
+ return tmp;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_WaitForLastTask\r
+* Description : Waits until last write operation on RTC registers has finished.\r
+* This function must be called before any write to RTC registers.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_WaitForLastTask(void)\r
+{\r
+ /* Loop until RTOFF flag is set */\r
+ while ((RTC->CRL & RTC_FLAG_RTOFF) == (u16)RESET)\r
+ {\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_WaitForSynchro\r
+* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)\r
+* are synchronized with RTC APB clock.\r
+* This function must be called before any read operation after\r
+* an APB reset or an APB clock stop.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_WaitForSynchro(void)\r
+{\r
+ /* Clear RSF flag */\r
+ RTC->CRL &= (u16)~RTC_FLAG_RSF;\r
+\r
+ /* Loop until RSF flag is set */\r
+ while ((RTC->CRL & RTC_FLAG_RSF) == (u16)RESET)\r
+ {\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_GetFlagStatus\r
+* Description : Checks whether the specified RTC flag is set or not.\r
+* Input : - RTC_FLAG: specifies the flag to check.\r
+* This parameter can be one the following values:\r
+* - RTC_FLAG_RTOFF: RTC Operation OFF flag\r
+* - RTC_FLAG_RSF: Registers Synchronized flag\r
+* - RTC_FLAG_OW: Overflow flag\r
+* - RTC_FLAG_ALR: Alarm flag\r
+* - RTC_FLAG_SEC: Second flag\r
+* Output : None\r
+* Return : The new state of RTC_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_RTC_GET_FLAG(RTC_FLAG)); \r
+ \r
+ if ((RTC->CRL & RTC_FLAG) != (u16)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_ClearFlag\r
+* Description : Clears the RTC\92s pending flags.\r
+* Input : - RTC_FLAG: specifies the flag to clear.\r
+* This parameter can be any combination of the following values:\r
+* - RTC_FLAG_RSF: Registers Synchronized flag. This flag\r
+* is cleared only after an APB reset or an APB Clock stop.\r
+* - RTC_FLAG_OW: Overflow flag\r
+* - RTC_FLAG_ALR: Alarm flag\r
+* - RTC_FLAG_SEC: Second flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_ClearFlag(u16 RTC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RTC_CLEAR_FLAG(RTC_FLAG)); \r
+ \r
+ /* Clear the coressponding RTC flag */\r
+ RTC->CRL &= (u16)~RTC_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_GetITStatus\r
+* Description : Checks whether the specified RTC interrupt has occured or not.\r
+* Input : - RTC_IT: specifies the RTC interrupts sources to check.\r
+* This parameter can be one of the following values:\r
+* - RTC_IT_OW: Overflow interrupt\r
+* - RTC_IT_ALR: Alarm interrupt\r
+* - RTC_IT_SEC: Second interrupt\r
+* Output : None\r
+* Return : The new state of the RTC_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus RTC_GetITStatus(u16 RTC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_RTC_GET_IT(RTC_IT)); \r
+ \r
+ bitstatus = (ITStatus)((RTC->CRL & RTC_IT) != (u16)RESET);\r
+\r
+ if (((RTC->CRH & RTC_IT) != (u16)RESET) && bitstatus)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : RTC_ClearITPendingBit\r
+* Description : Clears the RTC\92s interrupt pending bits.\r
+* Input : - RTC_IT: specifies the interrupt pending bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - RTC_IT_OW: Overflow interrupt\r
+* - RTC_IT_ALR: Alarm interrupt\r
+* - RTC_IT_SEC: Second interrupt\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void RTC_ClearITPendingBit(u16 RTC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_RTC_IT(RTC_IT)); \r
+ \r
+ /* Clear the coressponding RTC pending bit */\r
+ RTC->CRL &= (u16)~RTC_IT;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_spi.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the SPI firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_spi.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* SPI SPE mask */\r
+#define CR1_SPE_Set ((u16)0x0040)\r
+#define CR1_SPE_Reset ((u16)0xFFBF)\r
+\r
+/* SPI CRCNext mask */\r
+#define CR1_CRCNext_Set ((u16)0x1000)\r
+\r
+/* SPI CRCEN mask */\r
+#define CR1_CRCEN_Set ((u16)0x2000)\r
+#define CR1_CRCEN_Reset ((u16)0xDFFF)\r
+\r
+/* SPI SSOE mask */\r
+#define CR2_SSOE_Set ((u16)0x0004)\r
+#define CR2_SSOE_Reset ((u16)0xFFFB)\r
+\r
+/* SPI registers Masks */\r
+#define CR1_CLEAR_Mask ((u16)0x3040)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_DeInit\r
+* Description : Deinitializes the SPIx peripheral registers to their default\r
+* reset values.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_DeInit(SPI_TypeDef* SPIx)\r
+{\r
+ switch (*(u32*)&SPIx)\r
+ {\r
+ case SPI1_BASE:\r
+ /* Enable SPI1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
+ /* Release SPI1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
+ break;\r
+\r
+ case SPI2_BASE:\r
+ /* Enable SPI2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+ /* Release SPI2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_Init\r
+* Description : Initializes the SPIx according to the specified parameters\r
+* in the SPI_InitStruct.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
+* contains the configuration information for the specified\r
+* SPI peripheral.\r
+* Output : None\r
+* Return : None\r
+******************************************************************************/\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+ u16 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
+ assert(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
+ assert(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
+ assert(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
+ assert(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
+ assert(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
+ assert(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
+ assert(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
+ assert(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
+\r
+/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
+ /* Get the SPIx CR1 value */\r
+ tmpreg = SPIx->CR1;\r
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
+ master/salve mode, CPOL and CPHA */\r
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
+ /* Set LSBFirst bit according to SPI_FirstBit value */\r
+ /* Set BR bits according to SPI_BaudRatePrescaler value */\r
+ /* Set CPOL bit according to SPI_CPOL value */\r
+ /* Set CPHA bit according to SPI_CPHA value */\r
+ tmpreg |= (u16)((u32)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
+ /* Write to SPIx CR1 */\r
+ SPIx->CR1 = tmpreg;\r
+\r
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+ /* Write to SPIx CRCPOLY */\r
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_StructInit\r
+* Description : Fills each SPI_InitStruct member with its default value.\r
+* Input : - SPI_InitStruct : pointer to a SPI_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+/*--------------- Reset SPI init structure parameters values -----------------*/\r
+ /* Initialize the SPI_Direction member */\r
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+\r
+ /* initialize the SPI_Mode member */\r
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
+\r
+ /* initialize the SPI_DataSize member */\r
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
+\r
+ /* Initialize the SPI_CPOL member */\r
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
+\r
+ /* Initialize the SPI_CPHA member */\r
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
+\r
+ /* Initialize the SPI_NSS member */\r
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
+\r
+ /* Initialize the SPI_BaudRatePrescaler member */\r
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+\r
+ /* Initialize the SPI_FirstBit member */\r
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
+\r
+ /* Initialize the SPI_CRCPolynomial member */\r
+ SPI_InitStruct->SPI_CRCPolynomial = 7;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_Cmd\r
+* Description : Enables or disables the specified SPI peripheral.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - NewState: new state of the SPIx peripheral. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral */\r
+ SPIx->CR1 |= CR1_SPE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral */\r
+ SPIx->CR1 &= CR1_SPE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_ITConfig\r
+* Description : Enables or disables the specified SPI interrupts.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - SPI_IT: specifies the SPI interrupts sources to be enabled\r
+* or disabled. \r
+* This parameter can be one of the following values:\r
+* - SPI_IT_TXE: Tx buffer empty interrupt mask\r
+* - SPI_IT_RXNE: Rx buffer not empty interrupt mask\r
+* - SPI_IT_ERR: Error interrupt mask\r
+* - NewState: new state of the specified SPI interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_ITConfig(SPI_TypeDef* SPIx, u8 SPI_IT, FunctionalState NewState)\r
+{\r
+ u16 itpos = 0, itmask = 0 ;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ assert(IS_SPI_CONFIG_IT(SPI_IT));\r
+\r
+ /* Get the SPI IT index */\r
+ itpos = SPI_IT >> 4;\r
+ /* Set the IT mask */\r
+ itmask = (u16)((u16)1 << itpos);\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI interrupt */\r
+ SPIx->CR2 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI interrupt */\r
+ SPIx->CR2 &= (u16)~itmask;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_DMACmd\r
+* Description : Enables or disables the SPIx\92s DMA interface.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - SPI_DMAReq: specifies the SPI DMA transfer request to be\r
+* enabled or disabled. \r
+* This parameter can be any combination of the following values:\r
+* - SPI_DMAReq_Tx: Tx buffer DMA transfer request\r
+* - SPI_DMAReq_Rx: Rx buffer DMA transfer request\r
+* - NewState: new state of the selected SPI DMA transfer request.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_DMACmd(SPI_TypeDef* SPIx, u16 SPI_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ assert(IS_SPI_DMA_REQ(SPI_DMAReq));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI DMA requests */\r
+ SPIx->CR2 |= SPI_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI DMA requests */\r
+ SPIx->CR2 &= (u16)~SPI_DMAReq;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_SendData\r
+* Description : Transmits a Data through the SPIx peripheral.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - Data : Data to be transmitted..\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_SendData(SPI_TypeDef* SPIx, u16 Data)\r
+{\r
+ /* Write in the DR register the data to be sent */\r
+ SPIx->DR = Data;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_ReceiveData\r
+* Description : Returns the most recent received data by the SPIx peripheral.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* Output : None\r
+* Return : The value of the received data.\r
+*******************************************************************************/\r
+u16 SPI_ReceiveData(SPI_TypeDef* SPIx)\r
+{\r
+ /* Return the data in the DR register */\r
+ return SPIx->DR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_NSSInternalSoftwareConfig\r
+* Description : Configures internally by software the NSS pin for the selected \r
+* SPI.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
+* This parameter can be one of the following values:\r
+* - SPI_NSSInternalSoft_Set: Set NSS pin internally\r
+* - SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
+\r
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
+ {\r
+ /* Set NSS pin internally by software */\r
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset NSS pin internally by software */\r
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_SSOutputCmd\r
+* Description : Enables or disables the SS output for the selected SPI.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - NewState: new state of the SPIx SS output. \r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI SS output */\r
+ SPIx->CR2 |= CR2_SSOE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI SS output */\r
+ SPIx->CR2 &= CR2_SSOE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_DataSizeConfig\r
+* Description : Configures the data size for the selected SPI.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - SPI_DataSize: specifies the SPI data size.\r
+* This parameter can be one of the following values:\r
+* - SPI_DataSize_16b: Set data frame format to 16bit\r
+* - SPI_DataSize_8b: Set data frame format to 8bit\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_SPI_DATASIZE(SPI_DataSize));\r
+\r
+ if (SPI_DataSize != SPI_DataSize_8b)\r
+ {\r
+ /* Set data frame format to 16bit */\r
+ SPIx->CR1 |= SPI_DataSize_16b;\r
+ }\r
+ else\r
+ {\r
+ /* Set data frame format to 8bit */\r
+ SPIx->CR1 &= SPI_DataSize_8b;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_TransmitCRC\r
+* Description : Transmit the SPIx CRC value.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
+{\r
+ /* Enable the selected SPI CRC transmission */\r
+ SPIx->CR1 |= CR1_CRCNext_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_CalculateCRC\r
+* Description : Enables or disables the CRC value calculation of the\r
+* transfered bytes.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - NewState: new state of the SPIx CRC value calculation.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI CRC calculation */\r
+ SPIx->CR1 |= CR1_CRCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI CRC calculation */\r
+ SPIx->CR1 &= CR1_CRCEN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_GetCRC\r
+* Description : Returns the transmit or the receive CRC register value for\r
+* the specified SPI.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - SPI_CRC: specifies the CRC register to be read.\r
+* This parameter can be one of the following values:\r
+* - SPI_CRC_Tx: Selects Tx CRC register\r
+* - SPI_CRC_Rx: Selects Rx CRC register\r
+* Output : None\r
+* Return : The selected CRC register value..\r
+*******************************************************************************/\r
+u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC)\r
+{\r
+ u16 crcreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_SPI_CRC(SPI_CRC));\r
+\r
+ if (SPI_CRC != SPI_CRC_Rx)\r
+ {\r
+ /* Get the Tx CRC register */\r
+ crcreg = SPIx->TXCRCR;\r
+ }\r
+ else\r
+ {\r
+ /* Get the Rx CRC register */\r
+ crcreg = SPIx->RXCRCR;\r
+ }\r
+\r
+ /* Return the selected CRC register */\r
+ return crcreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_GetCRCPolynomial\r
+* Description : Returns the CRC Polynomial register value for the specified SPI.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* Output : None\r
+* Return : The CRC Polynomial register value.\r
+*******************************************************************************/\r
+u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
+{\r
+ /* Return the CRC polynomial register */\r
+ return SPIx->CRCPR;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_BiDirectionalLineConfig\r
+* Description : Selects the data transfer direction in bi-directional mode\r
+* for the specified SPI.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - SPI_Direction: specifies the data transfer direction in\r
+* bi-directional mode. \r
+* This parameter can be one of the following values:\r
+* - SPI_Direction_Tx: Selects Tx transmission direction\r
+* - SPI_Direction_Rx: Selects Rx receive direction\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_SPI_DIRECTION(SPI_Direction));\r
+\r
+ if (SPI_Direction == SPI_Direction_Tx)\r
+ {\r
+ /* Set the Tx only mode */\r
+ SPIx->CR1 |= SPI_Direction_Tx;\r
+ }\r
+ else\r
+ {\r
+ /* Set the Rx only mode */\r
+ SPIx->CR1 &= SPI_Direction_Rx;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_GetFlagStatus\r
+* Description : Checks whether the specified SPI flag is set or not.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - SPI_FLAG: specifies the flag to check. \r
+* This parameter can be one of the following values:\r
+* - SPI_FLAG_BSY: Busy flag.\r
+* - SPI_FLAG_OVR: Overrun flag.\r
+* - SPI_FLAG_MODF: Mode Fault flag.\r
+* - SPI_FLAG_CRCERR: CRC Error flag.\r
+* - SPI_FLAG_TXE: Transmit buffer empty flag.\r
+* - SPI_FLAG_RXNE: Receive buffer not empty flag.\r
+* Output : None\r
+* Return : The new state of SPI_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_SPI_GET_FLAG(SPI_FLAG));\r
+\r
+ /* Check the status of the specified SPI flag */\r
+ if ((SPIx->SR & SPI_FLAG) != (u16)RESET)\r
+ {\r
+ /* SPI_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_ClearFlag\r
+* Description : Clears the SPIx's pending flags.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - SPI_FLAG: specifies the flag to clear. \r
+* This parameter can be any combination of the following values:\r
+* - SPI_FLAG_OVR: Overrun flag.\r
+* - SPI_FLAG_MODF: Mode Fault flag.\r
+* - SPI_FLAG_CRCERR: CRC Error flag.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_SPI_CLEAR_FLAG(SPI_FLAG));\r
+ \r
+ /* SPI_FLAG_MODF flag clear */\r
+ if(SPI_FLAG == SPI_FLAG_MODF)\r
+ {\r
+ /* Read SR register */\r
+ (void)SPIx->SR;\r
+ /* Write on CR1 register */\r
+ SPIx->CR1 |= CR1_SPE_Set; \r
+ }\r
+ /* SPI_FLAG_OVR flag clear */\r
+ else if(SPI_FLAG == SPI_FLAG_OVR) \r
+ {\r
+ /* Read SR register */\r
+ (void)SPIx->SR;\r
+ }\r
+ else /* SPI_FLAG_CRCERR flag clear */\r
+ {\r
+ /* Clear the selected SPI flag */\r
+ SPIx->SR &= (u16)~SPI_FLAG;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_GetITStatus\r
+* Description : Checks whether the specified SPI interrupt has occurred or not.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - SPI_IT: specifies the SPI interrupt source to check. \r
+* This parameter can be one of the following values:\r
+* - SPI_IT_OVR: Overrun interrupt.\r
+* - SPI_IT_MODF: Mode Fault interrupt.\r
+* - SPI_IT_CRCERR: CRC Error interrupt.\r
+* - SPI_IT_TXE: Transmit buffer empty interrupt.\r
+* - SPI_IT_RXNE: Receive buffer not empty interrupt.\r
+* Output : None\r
+* Return : The new state of SPI_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ u16 itpos = 0, itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_SPI_GET_IT(SPI_IT));\r
+\r
+ /* Get the SPI IT index */\r
+ itpos = (u16)((u16)0x01 << (SPI_IT & (u8)0x0F));\r
+\r
+ /* Get the SPI IT index */\r
+ itmask = SPI_IT >> 4;\r
+ /* Set the IT mask */\r
+ itmask = (u16)((u16)0x01 << itmask);\r
+ /* Get the SPI_IT enable bit status */\r
+ enablestatus = (SPIx->CR2 & itmask) ;\r
+\r
+ /* Check the status of the specified SPI interrupt */\r
+ if (((SPIx->SR & itpos) != (u16)RESET) && enablestatus)\r
+ {\r
+ /* SPI_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SPI_ClearITPendingBit\r
+* Description : Clears the SPI\92s interrupt pending bits.\r
+* Input : - SPIx: where x can be 1 or 2 to select the SPI peripheral.\r
+* - SPI_IT: specifies the SPI interrupt pending bit to clear.\r
+* This parameter can be one of the following values:\r
+* - SPI_IT_OVR: Overrun interrupt.\r
+* - SPI_IT_MODF: Mode Fault interrupt.\r
+* - SPI_IT_CRCERR: CRC Error interrupt.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_IT)\r
+{\r
+ u16 itpos = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_SPI_CLEAR_IT(SPI_IT));\r
+\r
+ /* SPI_IT_MODF pending bit clear */\r
+ if(SPI_IT == SPI_IT_MODF)\r
+ {\r
+ /* Read SR register */\r
+ (void)SPIx->SR;\r
+ /* Write on CR1 register */\r
+ SPIx->CR1 |= CR1_SPE_Set; \r
+ }\r
+ else if(SPI_IT == SPI_IT_OVR) /* SPI_IT_OVR pending bit clear */ \r
+ {\r
+ /* Read SR register */\r
+ (void)(SPIx->SR);\r
+ }\r
+ else /* SPI_IT_CRCERR pending bit clear */\r
+ {\r
+ /* Get the SPI IT index */\r
+ itpos = (u16)((u16)0x01 << (SPI_IT & (u8)0x0F));\r
+ /* Clear the selected SPI interrupt pending bits */\r
+ SPIx->SR &= (u16)~itpos;\r
+ }\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_systick.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the SysTick firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_systick.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ---------------------- SysTick registers bit mask -------------------- */\r
+/* CTRL TICKINT Mask */\r
+#define CTRL_TICKINT_Set ((u32)0x00000002)\r
+#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD)\r
+\r
+/* SysTick Flag Mask */\r
+#define FLAG_Mask ((u8)0x1F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_CLKSourceConfig\r
+* Description : Configures the SysTick clock source.\r
+* Input : - SysTick_CLKSource: specifies the SysTick clock source.\r
+* This parameter can be one of the following values:\r
+* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8\r
+* selected as SysTick clock source.\r
+* - SysTick_CLKSource_HCLK: AHB clock selected as\r
+* SysTick clock source.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SysTick_CLKSourceConfig(u32 SysTick_CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+\r
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+ {\r
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_SetReload\r
+* Description : Sets SysTick Reload value.\r
+* Input : - Reload: SysTick Reload new value.\r
+* This parameter must be a number between 1 and 0xFFFFFF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SysTick_SetReload(u32 Reload)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_SYSTICK_RELOAD(Reload));\r
+\r
+ SysTick->LOAD = Reload;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_CounterCmd\r
+* Description : Enables or disables the SysTick counter.\r
+* Input : - SysTick_Counter: new state of the SysTick counter.\r
+* This parameter can be one of the following values:\r
+* - SysTick_Counter_Disable: Disable counter\r
+* - SysTick_Counter_Enable: Enable counter\r
+* - SysTick_Counter_Clear: Clear counter value to 0\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SysTick_CounterCmd(u32 SysTick_Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_SYSTICK_COUNTER(SysTick_Counter));\r
+\r
+ if (SysTick_Counter == SysTick_Counter_Clear)\r
+ {\r
+ SysTick->VAL = SysTick_Counter_Clear;\r
+ }\r
+ else\r
+ {\r
+ if (SysTick_Counter == SysTick_Counter_Enable)\r
+ {\r
+ SysTick->CTRL |= SysTick_Counter_Enable;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= SysTick_Counter_Disable;\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_ITConfig\r
+* Description : Enables or disables the SysTick Interrupt.\r
+* Input : - NewState: new state of the SysTick Interrupt.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void SysTick_ITConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ SysTick->CTRL |= CTRL_TICKINT_Set;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= CTRL_TICKINT_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_GetCounter\r
+* Description : Gets SysTick counter value.\r
+* Input : None\r
+* Output : None\r
+* Return : SysTick current value\r
+*******************************************************************************/\r
+u32 SysTick_GetCounter(void)\r
+{\r
+ return(SysTick->VAL);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : SysTick_GetFlagStatus\r
+* Description : Checks whether the specified SysTick flag is set or not.\r
+* Input : - SysTick_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - SysTick_FLAG_COUNT\r
+* - SysTick_FLAG_SKEW\r
+* - SysTick_FLAG_NOREF\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG)\r
+{\r
+ u32 tmp = 0;\r
+ u32 statusreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_SYSTICK_FLAG(SysTick_FLAG));\r
+\r
+ /* Get the SysTick register index */\r
+ tmp = SysTick_FLAG >> 5;\r
+\r
+ if (tmp == 1) /* The flag to check is in CTRL register */\r
+ {\r
+ statusreg = SysTick->CTRL;\r
+ }\r
+ else /* The flag to check is in CALIB register */\r
+ {\r
+ statusreg = SysTick->CALIB;\r
+ }\r
+\r
+ /* Get the flag position */\r
+ tmp = SysTick_FLAG & FLAG_Mask;\r
+\r
+ if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_tim.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the TIM firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_tim.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ---------------------- TIM registers bit mask ------------------------ */\r
+#define CR1_CEN_Set ((u16)0x0001)\r
+#define CR1_CEN_Reset ((u16)0x03FE)\r
+#define CR1_UDIS_Set ((u16)0x0002)\r
+#define CR1_UDIS_Reset ((u16)0x03FD)\r
+#define CR1_URS_Set ((u16)0x0004)\r
+#define CR1_URS_Reset ((u16)0x03FB)\r
+#define CR1_OPM_Mask ((u16)0x03F7)\r
+#define CR1_CounterMode_Mask ((u16)0x039F)\r
+#define CR1_ARPE_Set ((u16)0x0080)\r
+#define CR1_ARPE_Reset ((u16)0x037F)\r
+#define CR1_CKD_Mask ((u16)0x00FF)\r
+\r
+#define CR2_CCDS_Set ((u16)0x0008)\r
+#define CR2_CCDS_Reset ((u16)0x0007)\r
+#define CR2_MMS_Mask ((u16)0x0080)\r
+#define CR2_TI1S_Set ((u16)0x0080)\r
+#define CR2_TI1S_Reset ((u16)0xFF70)\r
+\r
+#define SMCR_SMS_Mask ((u16)0xFFF0)\r
+#define SMCR_ETR_Mask ((u16)0x00F7)\r
+#define SMCR_TS_Mask ((u16)0xFF87)\r
+#define SMCR_MSM_Mask ((u16)0xFF77)\r
+#define SMCR_ECE_Set ((u16)0x4000)\r
+\r
+#define CCMR_CC13S_Mask ((u16)0x7F7C)\r
+#define CCMR_CC24S_Mask ((u16)0x7C7F)\r
+#define CCMR_TI13Direct_Set ((u16)0x0001)\r
+#define CCMR_TI24Direct_Set ((u16)0x0100)\r
+#define CCMR_OC13FE_Mask ((u16)0x7F7B)\r
+#define CCMR_OC24FE_Mask ((u16)0x7B7F)\r
+#define CCMR_OC13PE_Mask ((u16)0x7F77)\r
+#define CCMR_OC24PE_Mask ((u16)0x777F)\r
+#define CCMR_OCM13_Mask ((u16)0x7F0F)\r
+#define CCMR_OCM24_Mask ((u16)0x0F7F)\r
+#define CCMR_IC13PSC_Mask ((u16)0xFFF3)\r
+#define CCMR_IC24PSC_Mask ((u16)0xF3FF)\r
+#define CCMR_IC13F_Mask ((u16)0xFF0F)\r
+#define CCMR_IC24F_Mask ((u16)0x0FFF)\r
+#define CCER_CC1P_Mask ((u16)0xFFFD)\r
+\r
+#define CCER_CC2P_Mask ((u16)0xFFDF)\r
+#define CCER_CC3P_Mask ((u16)0xFDFF)\r
+#define CCER_CC4P_Mask ((u16)0xDFFF)\r
+\r
+#define CCRE_CC1E_Set ((u16)0x0001)\r
+#define CCRE_CC1E_Reset ((u16)0xFFFE)\r
+#define CCRE_CC1E_Mask ((u16)0xFFFE)\r
+\r
+#define CCRE_CC2E_Set ((u16)0x0010)\r
+#define CCRE_CC2E_Reset ((u16)0xFFEF)\r
+#define CCRE_CC2E_Mask ((u16)0xFFEF)\r
+\r
+#define CCRE_CC3E_Set ((u16)0x0100)\r
+#define CCRE_CC3E_Reset ((u16)0xFEFF)\r
+\r
+#define CCRE_CC4E_Set ((u16)0x1000)\r
+#define CCRE_CC4E_Reset ((u16)0xEFFF)\r
+#define CCRE_CC4E_Mask ((u16)0xEFFF)\r
+\r
+#define DCR_DMA_Mask ((u16)0x0000)\r
+\r
+/* TIM private Masks */\r
+#define TIM_Period_Reset_Mask ((u16)0x0000)\r
+#define TIM_Prescaler_Reset_Mask ((u16)0x0000)\r
+#define TIM_Pulse_Reset_Mask ((u16)0x0000)\r
+#define TIM_ICFilter_Mask ((u8)0x00)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+static uc16 Tab_OCModeMask[4] = {0xFF00, 0x00FF, 0xFF00, 0x00FF};\r
+static uc16 Tab_PolarityMask[4] = {CCER_CC1P_Mask, CCER_CC2P_Mask, CCER_CC3P_Mask, CCER_CC4P_Mask};\r
+\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,\r
+ u8 TIM_ICFilter);\r
+static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,\r
+ u8 TIM_ICFilter);\r
+static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,\r
+ u8 TIM_ICFilter);\r
+static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,\r
+ u8 TIM_ICFilter);\r
+static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, \r
+ u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter);\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_DeInit\r
+* Description : Deinitializes the TIMx peripheral registers to their default\r
+* reset values.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_DeInit(TIM_TypeDef* TIMx)\r
+{ \r
+ switch (*(u32*)&TIMx)\r
+ {\r
+ case TIM2_BASE:\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
+ break;\r
+ \r
+ case TIM3_BASE:\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
+ break;\r
+ \r
+ case TIM4_BASE:\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_TimeBaseInit\r
+* Description : Initializes the TIMx Time Base Unit peripheral according to \r
+* the specified parameters in the TIM_TimeBaseInitStruct.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
+* structure that contains the configuration information for\r
+* the specified TIM peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
+ assert(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
+ \r
+ /* Set the Autoreload value */\r
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
+\r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
+\r
+ /* Select the Counter Mode and set the clock division */\r
+ TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;\r
+ TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision |\r
+ TIM_TimeBaseInitStruct->TIM_CounterMode;\r
+}\r
+/*******************************************************************************\r
+* Function Name : TIM_OCInit\r
+* Description : Initializes the TIMx peripheral according to the specified\r
+* parameters in the TIM_OCInitStruct.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+* that contains the configuration information for the specified\r
+* TIM peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OCInit(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ u32 tmpccmrx = 0, tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert(IS_TIM_CHANNEL(TIM_OCInitStruct->TIM_Channel));\r
+ assert(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));\r
+\r
+ tmpccer = TIMx->CCER;\r
+\r
+ if ((TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_1) ||\r
+ (TIM_OCInitStruct->TIM_Channel == (u16)TIM_Channel_2))\r
+ {\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Bits */\r
+ tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];\r
+\r
+ /* Set the Output Polarity level */\r
+ tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];\r
+\r
+ if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ TIMx->CCER &= CCRE_CC1E_Reset;\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;\r
+\r
+ /* Set the Capture Compare Enable Bit */\r
+ tmpccer |= CCRE_CC1E_Set;\r
+\r
+ /* Set the Capture Compare Polarity */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
+ }\r
+ else /* TIM_Channel_2 */\r
+ {\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ TIMx->CCER &= CCRE_CC2E_Reset;\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
+\r
+ /* Set the Capture Compare Enable Bit */\r
+ tmpccer |= CCRE_CC2E_Set;\r
+\r
+ /* Set the Capture Compare Polarity */\r
+ tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 4;\r
+ }\r
+\r
+ TIMx->CCMR1 = (u16)tmpccmrx;\r
+ }\r
+ else \r
+ {\r
+ if ((TIM_OCInitStruct->TIM_Channel == TIM_Channel_3) ||\r
+ (TIM_OCInitStruct->TIM_Channel == TIM_Channel_4))\r
+ { \r
+ tmpccmrx = TIMx->CCMR2;\r
+\r
+ /* Reset the Output Compare Bits */\r
+ tmpccmrx &= Tab_OCModeMask[TIM_OCInitStruct->TIM_Channel];\r
+\r
+ /* Set the Output Polarity level */\r
+ tmpccer &= Tab_PolarityMask[TIM_OCInitStruct->TIM_Channel];\r
+\r
+ if (TIM_OCInitStruct->TIM_Channel == TIM_Channel_3)\r
+ {\r
+ /* Disable the Channel 3: Reset the CCE Bit */\r
+ TIMx->CCER &= CCRE_CC3E_Reset;\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
+\r
+ /* Set the Capture Compare Enable Bit */\r
+ tmpccer |= CCRE_CC3E_Set;\r
+\r
+ /* Set the Capture Compare Polarity */\r
+ tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 8;\r
+ }\r
+ else /* TIM_Channel_4 */\r
+ {\r
+ /* Disable the Channel 4: Reset the CCE Bit */\r
+ TIMx->CCER &= CCRE_CC4E_Reset;\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (u32)TIM_OCInitStruct->TIM_OCMode << 8;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
+\r
+ /* Set the Capture Compare Enable Bit */\r
+ tmpccer |= CCRE_CC4E_Set;\r
+\r
+ /* Set the Capture Compare Polarity */\r
+ tmpccer |= (u32)TIM_OCInitStruct->TIM_OCPolarity << 12;\r
+ }\r
+\r
+ TIMx->CCMR2 = (u16)tmpccmrx;\r
+ }\r
+ }\r
+ \r
+ TIMx->CCER = (u16)tmpccer;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ICInit\r
+* Description : Initializes the TIMx peripheral according to the specified\r
+* parameters in the TIM_ICInitStruct.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+* that contains the configuration information for the specified\r
+* TIM peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM_IC_MODE(TIM_ICInitStruct->TIM_ICMode));\r
+ assert(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));\r
+ assert(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
+ assert(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
+ assert(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
+ assert(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
+ \r
+ if (TIM_ICInitStruct->TIM_ICMode == TIM_ICMode_ICAP)\r
+ {\r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
+ {\r
+ /* TI3 Configuration */\r
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else /* TIM_Channel_4 */\r
+ {\r
+ /* TI4 Configuration */\r
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ PWMI_Config(TIMx, TIM_ICInitStruct);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_TimeBaseStructInit\r
+* Description : Fills each TIM_TimeBaseInitStruct member with its default value.\r
+* Input : - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
+* structure which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_TimeBaseInitStruct->TIM_Period = TIM_Period_Reset_Mask;\r
+ TIM_TimeBaseInitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask;\r
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OCStructInit\r
+* Description : Fills each TIM_OCInitStruct member with its default value.\r
+* Input : - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
+ TIM_OCInitStruct->TIM_Channel = TIM_Channel_1;\r
+ TIM_OCInitStruct->TIM_Pulse = TIM_Pulse_Reset_Mask;\r
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ICStructInit\r
+* Description : Fills each TIM_InitStruct member with its default value.\r
+* Input : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_ICInitStruct->TIM_ICMode = TIM_ICMode_ICAP;\r
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
+ TIM_ICInitStruct->TIM_ICFilter = TIM_ICFilter_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_Cmd\r
+* Description : Enables or disables the specified TIM peripheral.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIMx peripheral.\r
+* - Newstate: new state of the TIMx peripheral.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the TIM Counter */\r
+ TIMx->CR1 |= CR1_CEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the TIM Counter */\r
+ TIMx->CR1 &= CR1_CEN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ITConfig\r
+* Description : Enables or disables the TIMx interrupts.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_IT: specifies the TIM interrupts sources to be enabled\r
+* or disabled.\r
+* This parameter can be any combination of the following values:\r
+* - TIM_IT_Update: Timer update Interrupt\r
+* - TIM_IT_CC1: Capture Compare 1 Interrupt\r
+* - TIM_IT_CC2: Capture Compare 2 Interrupt\r
+* - TIM_IT_CC3: Capture Compare 3 Interrupt\r
+* - TIM_IT_CC4: Capture Compare 4 Interrupt\r
+* - TIM_IT_Trigger: Trigger Interrupt\r
+* - Newstate: new state of the specified TIMx interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM_IT(TIM_IT));\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIMx->DIER |= TIM_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIMx->DIER &= (u16)(~TIM_IT);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_DMAConfig\r
+* Description : Configures the TIMx\92s DMA interface.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_DMABase: DMA Base address.\r
+* This parameter can be one of the following values:\r
+* - TIM_DMABase_CR1, TIM_DMABase_CR2, TIM_DMABase_SMCR,\r
+* TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,\r
+* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,\r
+* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,\r
+* TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3,\r
+* TIM_DMABase_CCR4, TIM_DMABase_DCR.\r
+* - TIM_DMABurstLength: DMA Burst length.\r
+* This parameter can be one value between:\r
+* TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, u16 TIM_DMABase, u16 TIM_DMABurstLength)\r
+{\r
+ u32 tmpdcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_DMA_BASE(TIM_DMABase));\r
+ assert(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
+ \r
+ tmpdcr = TIMx->DCR;\r
+\r
+ /* Reset the DBA and the DBL Bits */\r
+ tmpdcr &= DCR_DMA_Mask;\r
+\r
+ /* Set the DMA Base and the DMA Burst Length */\r
+ tmpdcr |= TIM_DMABase | TIM_DMABurstLength;\r
+\r
+ TIMx->DCR = (u16)tmpdcr;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_DMACmd\r
+* Description : Enables or disables the TIMx\92s DMA Requests.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_DMASources: specifies the DMA Request sources.\r
+* This parameter can be any combination of the following values:\r
+* - TIM_DMA_CC1: Capture Compare 1 DMA source\r
+* - TIM_DMA_CC2: Capture Compare 2 DMA source\r
+* - TIM_DMA_CC3: Capture Compare 3 DMA source\r
+* - TIM_DMA_CC4: Capture Compare 4 DMA source\r
+* - TIM_DMA_Trigger: Trigger DMA source\r
+* - Newstate: new state of the DMA Request sources.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, u16 TIM_DMASource, FunctionalState Newstate)\r
+{\r
+ u32 tmpdier = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ tmpdier = TIMx->DIER;\r
+\r
+ if (Newstate != DISABLE)\r
+ {\r
+ /* Enable the DMA sources */\r
+ tmpdier |= TIM_DMASource;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA sources */\r
+ tmpdier &= (u16)(~TIM_DMASource);\r
+ }\r
+ TIMx->DIER = (u16)tmpdier;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_InternalClockConfig\r
+* Description : Configures the TIMx interrnal Clock\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
+{\r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIMx->SMCR &= SMCR_SMS_Mask;\r
+}\r
+/*******************************************************************************\r
+* Function Name : TIM_ITRxExternalClockConfig\r
+* Description : Configures the TIMx Internal Trigger as External Clock\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ITRSource: Trigger source.\r
+* This parameter can be one of the following values:\r
+* - TIM_TS_ITR0: Internal Trigger 0\r
+* - TIM_TS_ITR1: Internal Trigger 1\r
+* - TIM_TS_ITR2: Internal Trigger 2\r
+* - TIM_TS_ITR3: Internal Trigger 3\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+\r
+ /* Select the Internal Trigger */\r
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
+\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+/*******************************************************************************\r
+* Function Name : TIM_TIxExternalClockConfig\r
+* Description : Configures the TIMx Trigger as External Clock\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_TIxExternalCLKSource: Trigger source.\r
+* This parameter can be one of the following values:\r
+* - TIM_TS_TI1F_ED: TI1 Edge Detector\r
+* - TIM_TS_TI1FP1: Filtered Timer Input 1\r
+* - TIM_TS_TI2FP2: Filtered Timer Input 2\r
+* - TIM_ICPolarity: specifies the TIx Polarity.\r
+* This parameter can be:\r
+* - TIM_ICPolarity_Rising\r
+* - TIM_ICPolarity_Falling\r
+* - ICFilter : specifies the filter value.\r
+* This parameter must be a value between 0x0 and 0xF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_TIxExternalCLKSource,\r
+ u16 TIM_ICPolarity, u8 ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM_TIX_TRIGGER_SELECTION(TIM_TIxExternalCLKSource));\r
+ assert(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
+ assert(IS_TIM_IC_FILTER(ICFilter));\r
+\r
+ /* Configure the Timer Input Clock Source */\r
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
+ {\r
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ else\r
+ {\r
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+\r
+ /* Select the Trigger source */\r
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
+\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ETRClockMode1Config\r
+* Description : Configures the External clock Mode1\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+* It can be one of the following values:\r
+* - TIM_ExtTRGPSC_OFF\r
+* - TIM_ExtTRGPSC_DIV2\r
+* - TIM_ExtTRGPSC_DIV4\r
+* - TIM_ExtTRGPSC_DIV8.\r
+* - TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+* It can be one of the following values:\r
+* - TIM_ExtTRGPolarity_Inverted\r
+* - TIM_ExtTRGPolarity_NonInverted\r
+* - ExtTRGFilter: External Trigger Filter.\r
+* This parameter must be a value between 0x00 and 0x0F\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,\r
+ u8 ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+\r
+ /* Configure the ETR Clock source */\r
+ ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR &= SMCR_SMS_Mask;\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+\r
+ /* Select the Trigger selection : ETRF */\r
+ TIMx->SMCR &= SMCR_TS_Mask;\r
+ TIMx->SMCR |= TIM_TS_ETRF;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ETRClockMode2Config\r
+* Description : Configures the External clock Mode2\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+* It can be one of the following values:\r
+* - TIM_ExtTRGPSC_OFF\r
+* - TIM_ExtTRGPSC_DIV2\r
+* - TIM_ExtTRGPSC_DIV4\r
+* - TIM_ExtTRGPSC_DIV8\r
+* - TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+* It can be one of the following values:\r
+* - TIM_ExtTRGPolarity_Inverted\r
+* - TIM_ExtTRGPolarity_NonInverted\r
+* - ExtTRGFilter: External Trigger Filter.\r
+* This parameter must be a value between 0x00 and 0x0F\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, \r
+ u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+\r
+ /* Configure the ETR Clock source */\r
+ ETR_Config(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+\r
+ /* Enable the External clock mode2 */\r
+ TIMx->SMCR |= SMCR_ECE_Set;\r
+}\r
+/*******************************************************************************\r
+* Function Name : TIM_SelectInputTrigger\r
+* Description : Selects the Input Trigger source\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_InputTriggerSource: The Input Trigger source.\r
+* This parameter can be one of the following values:\r
+* - TIM_TS_ITR0: Internal Trigger 0\r
+* - TIM_TS_ITR1: Internal Trigger 1\r
+* - TIM_TS_ITR2: Internal Trigger 2\r
+* - TIM_TS_ITR3: Internal Trigger 3\r
+* - TIM_TS_TI1F_ED: TI1 Edge Detector\r
+* - TIM_TS_TI1FP1: Filtered Timer Input 1\r
+* - TIM_TS_TI2FP2: Filtered Timer Input 2\r
+* - TIM_TS_ETRF: External Trigger input\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource)\r
+{\r
+ u32 tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+\r
+ tmpsmcr = TIMx->SMCR;\r
+\r
+ /* Select the Tgigger Source */\r
+ tmpsmcr &= SMCR_TS_Mask;\r
+ tmpsmcr |= TIM_InputTriggerSource;\r
+\r
+ TIMx->SMCR = (u16)tmpsmcr;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_PrescalerConfig\r
+* Description : Configures the TIMx Prescaler.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - Prescaler: specifies the Prescaler Register value\r
+* - TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
+* This parameter can be one of the following values:\r
+* - TIM_PSCReloadMode_Update: The Prescaler is loaded at\r
+* the update event.\r
+* - TIM_PSCReloadMode_Immediate: The Prescaler is loaded\r
+* immediatly.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
+\r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = Prescaler;\r
+\r
+ /* Set or reset the UG Bit */\r
+ if (TIM_PSCReloadMode == TIM_PSCReloadMode_Immediate)\r
+ {\r
+ TIMx->EGR |= TIM_EventSource_Update;\r
+ }\r
+ else\r
+ {\r
+ TIMx->EGR &= TIM_EventSource_Update;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_CounterModeConfig\r
+* Description : Specifies the TIMx Counter Mode to be used.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_CounterMode: specifies the Counter Mode to be used\r
+* This parameter can be one of the following values:\r
+* - TIM_CounterMode_Up: TIM Up Counting Mode\r
+* - TIM_CounterMode_Down: TIM Down Counting Mode\r
+* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
+* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
+* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode)\r
+{\r
+ u32 tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
+\r
+ tmpcr1 = TIMx->CR1;\r
+\r
+ /* Reset the CMS and DIR Bits */\r
+ tmpcr1 &= CR1_CounterMode_Mask;\r
+\r
+ /* Set the Counter Mode */\r
+ tmpcr1 |= TIM_CounterMode;\r
+\r
+ TIMx->CR1 = (u16)tmpcr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ForcedOC1Config\r
+* Description : Forces the TIMx output 1 waveform to active or inactive level.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ForcedAction: specifies the forced Action to be set to\r
+* the output waveform.\r
+* This parameter can be one of the following values:\r
+* - TIM_ForcedAction_Active: Force active level on OC1REF\r
+* - TIM_ForcedAction_InActive: Force inactive level on\r
+* OC1REF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Reset the OCM Bits */\r
+ tmpccmr1 &= CCMR_OCM13_Mask;\r
+\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= TIM_ForcedAction;\r
+\r
+ TIMx->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ForcedOC2Config\r
+* Description : Forces the TIMx output 2 waveform to active or inactive level.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ForcedAction: specifies the forced Action to be set to\r
+* the output waveform.\r
+* This parameter can be one of the following values:\r
+* - TIM_ForcedAction_Active: Force active level on OC2REF\r
+* - TIM_ForcedAction_InActive: Force inactive level on\r
+* OC2REF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Reset the OCM Bits */\r
+ tmpccmr1 &= CCMR_OCM24_Mask;\r
+\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= (u16)(TIM_ForcedAction << 8);\r
+\r
+ TIMx->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ForcedOC3Config\r
+* Description : Forces the TIMx output 3 waveform to active or inactive level.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ForcedAction: specifies the forced Action to be set to\r
+* the output waveform.\r
+* This parameter can be one of the following values:\r
+* - TIM_ForcedAction_Active: Force active level on OC3REF\r
+* - TIM_ForcedAction_InActive: Force inactive level on\r
+* OC3REF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+\r
+ tmpccmr2 = TIMx->CCMR2;\r
+\r
+ /* Reset the OCM Bits */\r
+ tmpccmr2 &= CCMR_OCM13_Mask;\r
+\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= TIM_ForcedAction;\r
+\r
+ TIMx->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ForcedOC4Config\r
+* Description : Forces the TIMx output 4 waveform to active or inactive level.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ForcedAction: specifies the forced Action to be set to\r
+* the output waveform.\r
+* This parameter can be one of the following values:\r
+* - TIM_ForcedAction_Active: Force active level on OC4REF\r
+* - TIM_ForcedAction_InActive: Force inactive level on\r
+* OC4REF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+\r
+ tmpccmr2 = TIMx->CCMR2;\r
+\r
+ /* Reset the OCM Bits */\r
+ tmpccmr2 &= CCMR_OCM24_Mask;\r
+\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= (u16)(TIM_ForcedAction << 8);\r
+\r
+ TIMx->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ARRPreloadConfig\r
+* Description : Enables or disables TIMx peripheral Preload register on ARR.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - Newstate: new state of the TIMx peripheral Preload register\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate)\r
+{\r
+ u32 tmpcr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ tmpcr1 = TIMx->CR1;\r
+\r
+ if (Newstate != DISABLE)\r
+ {\r
+ /* Set the ARR Preload Bit */\r
+ tmpcr1 |= CR1_ARPE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the ARR Preload Bit */\r
+ tmpcr1 &= CR1_ARPE_Reset;\r
+ }\r
+\r
+ TIMx->CR1 = (u16)tmpcr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SelectCCDMA\r
+* Description : Selects the TIMx peripheral Capture Compare DMA source.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - Newstate: new state of the Capture Compare DMA source\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate)\r
+{\r
+ u32 tmpcr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ tmpcr2 = TIMx->CR2;\r
+\r
+ if (Newstate != DISABLE)\r
+ {\r
+ /* Set the CCDS Bit */\r
+ tmpcr2 |= CR2_CCDS_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the CCDS Bit */\r
+ tmpcr2 &= CR2_CCDS_Reset;\r
+ }\r
+\r
+ TIMx->CR2 = (u16)tmpcr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC1PreloadConfig\r
+* Description : Enables or disables the TIMx peripheral Preload register on CCR1.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCPreload: new state of the TIMx peripheral Preload\r
+* register\r
+* This parameter can be one of the following values:\r
+* - TIM_OCPreload_Enable\r
+* - TIM_OCPreload_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Reset the OCPE Bit */\r
+ tmpccmr1 &= CCMR_OC13PE_Mask;\r
+\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= TIM_OCPreload;\r
+\r
+ TIMx->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC2PreloadConfig\r
+* Description : Enables or disables the TIMx peripheral Preload register on CCR2.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCPreload: new state of the TIMx peripheral Preload\r
+* register\r
+* This parameter can be one of the following values:\r
+* - TIM_OCPreload_Enable\r
+* - TIM_OCPreload_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Reset the OCPE Bit */\r
+ tmpccmr1 &= CCMR_OC24PE_Mask;\r
+\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= (u16)(TIM_OCPreload << 8);\r
+\r
+ TIMx->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC3PreloadConfig\r
+* Description : Enables or disables the TIMx peripheral Preload register on CCR3.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCPreload: new state of the TIMx peripheral Preload\r
+* register\r
+* This parameter can be one of the following values:\r
+* - TIM_OCPreload_Enable\r
+* - TIM_OCPreload_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+\r
+ tmpccmr2 = TIMx->CCMR2;\r
+\r
+ /* Reset the OCPE Bit */\r
+ tmpccmr2 &= CCMR_OC13PE_Mask;\r
+\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= TIM_OCPreload;\r
+\r
+ TIMx->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC4PreloadConfig\r
+* Description : Enables or disables the TIMx peripheral Preload register on CCR4.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCPreload: new state of the TIMx peripheral Preload\r
+* register\r
+* This parameter can be one of the following values:\r
+* - TIM_OCPreload_Enable\r
+* - TIM_OCPreload_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+\r
+ tmpccmr2 = TIMx->CCMR2;\r
+\r
+ /* Reset the OCPE Bit */\r
+ tmpccmr2 &= CCMR_OC24PE_Mask;\r
+\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= (u16)(TIM_OCPreload << 8);\r
+\r
+ TIMx->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC1FastConfig\r
+* Description : Configures the TIMx Output Compare 1 Fast feature.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+* This parameter can be one of the following values:\r
+* - TIM_OCFast_Enable\r
+* - TIM_OCFast_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Reset the OCFE Bit */\r
+ tmpccmr1 &= CCMR_OC13FE_Mask;\r
+\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= TIM_OCFast;\r
+\r
+ TIMx->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC2FastConfig\r
+* Description : Configures the TIMx Output Compare 2 Fast feature.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+* This parameter can be one of the following values:\r
+* - TIM_OCFast_Enable\r
+* - TIM_OCFast_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Reset the OCFE Bit */\r
+ tmpccmr1 &= CCMR_OC24FE_Mask;\r
+\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= (u16)(TIM_OCFast << 8);\r
+\r
+ TIMx->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC3FastConfig\r
+* Description : Configures the TIMx Output Compare 3 Fast feature.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+* This parameter can be one of the following values:\r
+* - TIM_OCFast_Enable\r
+* - TIM_OCFast_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+\r
+ tmpccmr2 = TIMx->CCMR2;\r
+\r
+ /* Reset the OCFE Bit */\r
+ tmpccmr2 &= CCMR_OC13FE_Mask;\r
+\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= TIM_OCFast;\r
+\r
+ TIMx->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC4FastConfig\r
+* Description : Configures the TIMx Output Compare 4 Fast feature.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+* This parameter can be one of the following values:\r
+* - TIM_OCFast_Enable\r
+* - TIM_OCFast_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+\r
+ tmpccmr2 = TIMx->CCMR2;\r
+\r
+ /* Reset the OCFE Bit */\r
+ tmpccmr2 &= CCMR_OC24FE_Mask;\r
+\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= (u16)(TIM_OCFast << 8);\r
+\r
+ TIMx->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_UpdateDisableConfig\r
+* Description : Enables or Disables the TIMx Update event.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - Newstate: new state of the TIMx peripheral Preload register\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState Newstate)\r
+{\r
+ u32 tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ tmpcr1 = TIMx->CR1;\r
+\r
+ if (Newstate != DISABLE)\r
+ {\r
+ /* Set the Update Disable Bit */\r
+ tmpcr1 |= CR1_UDIS_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the Update Disable Bit */\r
+ tmpcr1 &= CR1_UDIS_Reset;\r
+ }\r
+\r
+ TIMx->CR1 = (u16)tmpcr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_EncoderInterfaceConfig\r
+* Description : Configures the TIMx Encoder Interface.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
+* This parameter can be one of the following values:\r
+* - TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge\r
+* depending on TI2FP2 level.\r
+* - TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge\r
+* depending on TI1FP1 level.\r
+* - TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and\r
+* TI2FP2 edges depending on the level of the other input.\r
+* - TIM_IC1Polarity: specifies the IC1 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM_ICPolarity_Falling\r
+* - TIM_ICPolarity_Rising\r
+* - TIM_IC2Polarity: specifies the IC2 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM_ICPolarity_Falling\r
+* - TIM_ICPolarity_Rising\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,\r
+ u16 TIM_IC1Polarity, u16 TIM_IC2Polarity)\r
+{\r
+ u32 tmpsmcr = 0;\r
+ u32 tmpccmr1 = 0;\r
+ u32 tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
+ assert(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
+ assert(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
+\r
+ tmpsmcr = TIMx->SMCR;\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Set the encoder Mode */\r
+ tmpsmcr &= SMCR_SMS_Mask;\r
+ tmpsmcr |= TIM_EncoderMode;\r
+\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;\r
+ tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;\r
+\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= CCER_CC1P_Mask & CCER_CC2P_Mask;\r
+ tmpccer |= (TIM_IC1Polarity | (u16)((u16)TIM_IC2Polarity << 4));\r
+\r
+ TIMx->SMCR = (u16)tmpsmcr;\r
+\r
+ TIMx->CCMR1 = (u16)tmpccmr1;\r
+\r
+ TIMx->CCER = (u16)tmpccer;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GenerateEvent\r
+* Description : Configures the TIMx event to be generate by software.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_EventSource: specifies the event source.\r
+* This parameter can be one or more of the following values:\r
+* - TIM_EventSource_Update: Timer update Event source\r
+* - TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r
+* - TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r
+* - TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r
+* - TIM_EventSource_CC4: Timer Capture Compare 4 Event source\r
+* - TIM_EventSource_Trigger: Timer Trigger Event source\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM_EVENT_SOURCE(TIM_EventSource));\r
+\r
+ /* Set the event sources */\r
+ TIMx->EGR |= TIM_EventSource;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC1PolarityConfig\r
+* Description : Configures the TIMx channel 1 polarity.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCPolarity: specifies the OC1 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM_OCPolarity_High: Output Compare active high\r
+* - TIM_OCPolarity_Low: Output Compare active low\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)\r
+{\r
+ u32 tmpccer = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Set or Reset the CC1P Bit */\r
+ tmpccer &= CCER_CC1P_Mask;\r
+ tmpccer |= TIM_OCPolarity;\r
+\r
+ TIMx->CCER = (u16)tmpccer;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC2PolarityConfig\r
+* Description : Configures the TIMx channel 2 polarity.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCPolarity: specifies the OC2 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM_OCPolarity_High: Output Compare active high\r
+* - TIM_OCPolarity_Low: Output Compare active low\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)\r
+{\r
+ u32 tmpccer = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Set or Reset the CC2P Bit */\r
+ tmpccer &= CCER_CC2P_Mask;\r
+ tmpccer |= (u16)((u16)TIM_OCPolarity << 4);\r
+\r
+ TIMx->CCER = (u16)tmpccer;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC3PolarityConfig\r
+* Description : Configures the TIMx channel 3 polarity.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCPolarity: specifies the OC3 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM_OCPolarity_High: Output Compare active high\r
+* - TIM_OCPolarity_Low: Output Compare active low\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)\r
+{\r
+ u32 tmpccer = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Set or Reset the CC3P Bit */\r
+ tmpccer &= CCER_CC3P_Mask;\r
+ tmpccer |= (u16)((u16)TIM_OCPolarity << 8);\r
+\r
+ TIMx->CCER = (u16)tmpccer;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_OC4PolarityConfig\r
+* Description : Configures the TIMx channel 4 polarity.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OCPolarity: specifies the OC4 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM_OCPolarity_High: Output Compare active high\r
+* - TIM_OCPolarity_Low: Output Compare active low\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, u16 TIM_OCPolarity)\r
+{\r
+ u32 tmpccer = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Set or Reset the CC4P Bit */\r
+ tmpccer &= CCER_CC4P_Mask;\r
+ tmpccer |= (u16)((u16)TIM_OCPolarity << 12);\r
+\r
+ TIMx->CCER = (u16)tmpccer;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_UpdateRequestConfig\r
+* Description : Configures the TIMx Update Request Interrupt source.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_UpdateSource: specifies the Update source.\r
+* This parameter can be one of the following values:\r
+* - TIM_UpdateSource_Regular\r
+* - TIM_UpdateSource_Global\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, u16 TIM_UpdateSource)\r
+{\r
+ u32 tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
+\r
+ tmpcr1 = TIMx->CR1;\r
+\r
+ if (TIM_UpdateSource == TIM_UpdateSource_Regular)\r
+ {\r
+ /* Set the URS Bit */\r
+ tmpcr1 |= CR1_URS_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the URS Bit */\r
+ tmpcr1 &= CR1_URS_Reset;\r
+ }\r
+ TIMx->CR1 = (u16)tmpcr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SelectHallSensor\r
+* Description : Enables or disables the TIMx\92s Hall sensor interface.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - Newstate: new state of the TIMx Hall sensor interface.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState Newstate)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ if (Newstate != DISABLE)\r
+ {\r
+ /* Set the TI1S Bit */\r
+ TIMx->CR2 |= CR2_TI1S_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the TI1S Bit */\r
+ TIMx->CR2 &= CR2_TI1S_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SelectOnePulseMode\r
+* Description : Selects the TIMx\92s One Pulse Mode.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_OPMode: specifies the OPM Mode to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM_OPMode_Single\r
+* - TIM_OPMode_Repetitive\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, u16 TIM_OPMode)\r
+{\r
+ u32 tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_OPM_MODE(TIM_OPMode));\r
+\r
+ tmpcr1 = TIMx->CR1;\r
+\r
+ /* Reset the OPM Bit */\r
+ tmpcr1 &= CR1_OPM_Mask;\r
+\r
+ /* Configure the OPM Mode */\r
+ tmpcr1 |= TIM_OPMode;\r
+\r
+ TIMx->CR1 = (u16)tmpcr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SelectOutputTrigger\r
+* Description : Selects the TIMx Trigger Output Mode.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_TRGOSource: specifies the Trigger Output source.\r
+* This paramter can be one of the following values:\r
+* - TIM_TRGOSource_Reset\r
+* - TIM_TRGOSource_Enable\r
+* - TIM_TRGOSource_Update\r
+* - TIM_TRGOSource_OC1\r
+* - TIM_TRGOSource_OC1Ref\r
+* - TIM_TRGOSource_OC2Ref\r
+* - TIM_TRGOSource_OC3Ref\r
+* - TIM_TRGOSource_OC4Ref\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, u16 TIM_TRGOSource)\r
+{\r
+ u32 tmpcr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
+\r
+ tmpcr2 = TIMx->CR2;\r
+ /* Reset the MMS Bits */\r
+ tmpcr2 &= CR2_MMS_Mask;\r
+\r
+ /* Select the TRGO source */\r
+ tmpcr2 |= TIM_TRGOSource;\r
+\r
+ TIMx->CR2 = (u16)tmpcr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SelectSlaveMode\r
+* Description : Selects the TIMx Slave Mode.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_SlaveMode: specifies the Timer Slave Mode.\r
+* This paramter can be one of the following values:\r
+* - TIM_SlaveMode_Reset\r
+* - TIM_SlaveMode_Gated\r
+* - TIM_SlaveMode_Trigger\r
+* - TIM_SlaveMode_External1\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, u16 TIM_SlaveMode)\r
+{\r
+ u32 tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
+\r
+ tmpsmcr = TIMx->SMCR;\r
+\r
+ /* Reset the SMS Bits */\r
+ tmpsmcr &= SMCR_SMS_Mask;\r
+\r
+ /* Select the Slave Mode */\r
+ tmpsmcr |= TIM_SlaveMode;\r
+\r
+ TIMx->SMCR = (u16)tmpsmcr;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SelectMasterSlaveMode\r
+* Description : Sets or Resets the TIMx Master/Slave Mode.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
+* This paramter can be one of the following values:\r
+* - TIM_MasterSlaveMode_Enable: synchronization between the\r
+* current timer and its slaves (through TRGO).\r
+* - TIM_MasterSlaveMode_Disable: No action\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, u16 TIM_MasterSlaveMode)\r
+{\r
+ u32 tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
+\r
+ tmpsmcr = TIMx->SMCR;\r
+\r
+ /* Set or Reset the MSM Bit */\r
+ tmpsmcr &= SMCR_MSM_Mask;\r
+ tmpsmcr |= TIM_MasterSlaveMode;\r
+\r
+ TIMx->SMCR = (u16)tmpsmcr;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetAutoreload\r
+* Description : Sets the TIMx Autoreload Register value\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - Autoreload: specifies the Autoreload register new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, u16 Autoreload)\r
+{\r
+ /* Set the Autoreload Register value */\r
+ TIMx->ARR = Autoreload;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetCompare1\r
+* Description : Sets the TIMx Capture Compare1 Register value\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - Compare1: specifies the Capture Compare1 register new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, u16 Compare1)\r
+{\r
+ /* Set the Capture Compare1 Register value */\r
+ TIMx->CCR1 = Compare1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetCompare2\r
+* Description : Sets the TIMx Capture Compare2 Register value\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - Compare2: specifies the Capture Compare2 register new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, u16 Compare2)\r
+{\r
+ /* Set the Capture Compare2 Register value */\r
+ TIMx->CCR2 = Compare2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetCompare3\r
+* Description : Sets the TIMx Capture Compare3 Register value\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - Compare3: specifies the Capture Compare3 register new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, u16 Compare3)\r
+{\r
+ /* Set the Capture Compare3 Register value */\r
+ TIMx->CCR3 = Compare3;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetCompare4\r
+* Description : Sets the TIMx Capture Compare4 Register value\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - Compare4: specifies the Capture Compare4 register new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, u16 Compare4)\r
+{\r
+ /* Set the Capture Compare4 Register value */\r
+ TIMx->CCR4 = Compare4;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetIC1Prescaler\r
+* Description : Sets the TIMx Input Capture 1 prescaler.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_IC1Prescaler: specifies the Input Capture1 prescaler\r
+* new value.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICPSC_DIV1: no prescaler\r
+* - TIM_ICPSC_DIV2: capture is done once every 2 events\r
+* - TIM_ICPSC_DIV4: capture is done once every 4 events\r
+* - TIM_ICPSC_DIV8: capture is done once every 8 events\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC1Prescaler)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_IC_PRESCALER(TIM_IC1Prescaler));\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Reset the IC1PSC Bits */\r
+ tmpccmr1 &= CCMR_IC13PSC_Mask;\r
+\r
+ /* Set the IC1PSC value */\r
+ tmpccmr1 |= TIM_IC1Prescaler;\r
+\r
+ TIMx->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetIC2Prescaler\r
+* Description : Sets the TIMx Input Capture 2 prescaler.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_IC2Prescaler: specifies the Input Capture2 prescaler\r
+* new value.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICPSC_DIV1: no prescaler\r
+* - TIM_ICPSC_DIV2: capture is done once every 2 events\r
+* - TIM_ICPSC_DIV4: capture is done once every 4 events\r
+* - TIM_ICPSC_DIV8: capture is done once every 8 events\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC2Prescaler)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_IC_PRESCALER(TIM_IC2Prescaler));\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Reset the IC2PSC Bits */\r
+ tmpccmr1 &= CCMR_IC24PSC_Mask;\r
+\r
+ /* Set the IC2PSC value */\r
+ tmpccmr1 |= (u16)((u16)TIM_IC2Prescaler << 8);\r
+\r
+ TIMx->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetIC3Prescaler\r
+* Description : Sets the TIMx Input Capture 3 prescaler.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_IC3Prescaler: specifies the Input Capture3 prescaler\r
+* new value.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICPSC_DIV1: no prescaler\r
+* - TIM_ICPSC_DIV2: capture is done once every 2 events\r
+* - TIM_ICPSC_DIV4: capture is done once every 4 events\r
+* - TIM_ICPSC_DIV8: capture is done once every 8 events\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC3Prescaler)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_IC_PRESCALER(TIM_IC3Prescaler));\r
+\r
+ tmpccmr2 = TIMx->CCMR2;\r
+\r
+ /* Reset the IC3PSC Bits */\r
+ tmpccmr2 &= CCMR_IC13PSC_Mask;\r
+\r
+ /* Set the IC3PSC value */\r
+ tmpccmr2 |= TIM_IC3Prescaler;\r
+\r
+ TIMx->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetIC4Prescaler\r
+* Description : Sets the TIMx Input Capture 4 prescaler.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_IC4Prescaler: specifies the Input Capture4 prescaler\r
+* new value.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICPSC_DIV1: no prescaler\r
+* - TIM_ICPSC_DIV2: capture is done once every 2 events\r
+* - TIM_ICPSC_DIV4: capture is done once every 4 events\r
+* - TIM_ICPSC_DIV8: capture is done once every 8 events\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, u16 TIM_IC4Prescaler)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_TIM_IC_PRESCALER(TIM_IC4Prescaler));\r
+\r
+ tmpccmr2 = TIMx->CCMR2;\r
+\r
+ /* Reset the IC4PSC Bits */\r
+ tmpccmr2 &= CCMR_IC24PSC_Mask;\r
+\r
+ /* Set the IC4PSC value */\r
+ tmpccmr2 |= (u16)((u16)TIM_IC4Prescaler << 8);\r
+\r
+ TIMx->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_SetClockDivision\r
+* Description : Sets the TIMx Clock Division value.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_CKD: specifies the clock division value.\r
+* This parameter can be one of the following value:\r
+* - TIM_CKD_DIV1: TDTS = Tck_tim\r
+* - TIM_CKD_DIV2: TDTS = 2*Tck_tim\r
+* - TIM_CKD_DIV4: TDTS = 4*Tck_tim\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, u16 TIM_CKD)\r
+{\r
+ u32 tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_CKD_DIV(TIM_CKD));\r
+\r
+ tmpcr1 = TIMx->CR1;\r
+\r
+ /* Reset the CKD Bits */\r
+ tmpcr1 &= CR1_CKD_Mask;\r
+\r
+ /* Set the CKD value */\r
+ tmpcr1 |= TIM_CKD;\r
+\r
+ TIMx->CR1 = (u16)tmpcr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetCapture1\r
+* Description : Gets the TIMx Input Capture 1 value.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* Output : None\r
+* Return : Capture Compare 1 Register value.\r
+*******************************************************************************/\r
+u16 TIM_GetCapture1(TIM_TypeDef* TIMx)\r
+{\r
+ /* Get the Capture 1 Register value */\r
+ return TIMx->CCR1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetCapture2\r
+* Description : Gets the TIMx Input Capture 2 value.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* Output : None\r
+* Return : Capture Compare 2 Register value.\r
+*******************************************************************************/\r
+u16 TIM_GetCapture2(TIM_TypeDef* TIMx)\r
+{\r
+ /* Get the Capture 2 Register value */\r
+ return TIMx->CCR2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetCapture3\r
+* Description : Gets the TIMx Input Capture 3 value.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* Output : None\r
+* Return : Capture Compare 3 Register value.\r
+*******************************************************************************/\r
+u16 TIM_GetCapture3(TIM_TypeDef* TIMx)\r
+{\r
+ /* Get the Capture 3 Register value */\r
+ return TIMx->CCR3;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetCapture4\r
+* Description : Gets the TIMx Input Capture 4 value.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* Output : None\r
+* Return : Capture Compare 4 Register value.\r
+*******************************************************************************/\r
+u16 TIM_GetCapture4(TIM_TypeDef* TIMx)\r
+{\r
+ /* Get the Capture 4 Register value */\r
+ return TIMx->CCR4;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetCounter\r
+* Description : Gets the TIMx Counter value.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* Output : None\r
+* Return : Counter Register value.\r
+*******************************************************************************/\r
+u16 TIM_GetCounter(TIM_TypeDef* TIMx)\r
+{\r
+ /* Get the Counter Register value */\r
+ return TIMx->CNT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetPrescaler\r
+* Description : Gets the TIMx Prescaler value.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* Output : None\r
+* Return : Prescaler Register value.\r
+*******************************************************************************/\r
+u16 TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
+{\r
+ /* Get the Prescaler Register value */\r
+ return TIMx->PSC;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetFlagStatus\r
+* Description : Checks whether the specified TIMx flag is set or not.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - TIM_FLAG_Update: Timer update Flag\r
+* - TIM_FLAG_CC1: Timer Capture Compare 1 Flag\r
+* - TIM_FLAG_CC2: Timer Capture Compare 2 Flag\r
+* - TIM_FLAG_CC3: Timer Capture Compare 3 Flag\r
+* - TIM_FLAG_CC4: Timer Capture Compare 4 Flag\r
+* - TIM_FLAG_Trigger: Timer Trigger Flag\r
+* - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag\r
+* - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag\r
+* - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag\r
+* - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag\r
+* Output : None\r
+* Return : The new state of TIM_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_GET_FLAG(TIM_FLAG));\r
+\r
+ if ((TIMx->SR & TIM_FLAG) != (u16)RESET )\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ClearFlag\r
+* Description : Clears the TIMx's pending flags.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_FLAG: specifies the flag bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - TIM_FLAG_Update: Timer update Flag\r
+* - TIM_FLAG_CC1: Timer Capture Compare 1 Flag\r
+* - TIM_FLAG_CC2: Timer Capture Compare 2 Flag\r
+* - TIM_FLAG_CC3: Timer Capture Compare 3 Flag\r
+* - TIM_FLAG_CC4: Timer Capture Compare 4 Flag\r
+* - TIM_FLAG_Trigger: Timer Trigger Flag\r
+* - TIM_FLAG_CC1OF: Timer Capture Compare 1 overcapture Flag\r
+* - TIM_FLAG_CC2OF: Timer Capture Compare 2 overcapture Flag\r
+* - TIM_FLAG_CC3OF: Timer Capture Compare 3 overcapture Flag\r
+* - TIM_FLAG_CC4OF: Timer Capture Compare 4 overcapture Flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
+\r
+ /* Clear the flags */\r
+ TIMx->SR &= (u16)~TIM_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_GetITStatus\r
+* Description : Checks whether the TIMx interrupt has occurred or not.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_IT: specifies the TIM interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - TIM_IT_Update: Timer update Interrupt source\r
+* - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source\r
+* - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source\r
+* - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source\r
+* - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source\r
+* - TIM_IT_Trigger: Timer Trigger Interrupt source\r
+* Output : None\r
+* Return : The new state of the TIM_IT(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ \r
+ u16 itstatus = 0x0, itenable = 0x0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM_GET_IT(TIM_IT));\r
+ \r
+ itstatus = TIMx->SR & TIM_IT;\r
+ \r
+ itenable = TIMx->DIER & TIM_IT;\r
+\r
+ if ((itstatus != (u16)RESET) && (itenable != (u16)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM_ClearITPendingBit\r
+* Description : Clears the TIMx's interrupt pending bits.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_IT: specifies the pending bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - TIM_IT_Update: Timer update Interrupt source\r
+* - TIM_IT_CC1: Timer Capture Compare 1 Interrupt source\r
+* - TIM_IT_CC2: Timer Capture Compare 2 Interrupt source\r
+* - TIM_IT_CC3: Timer Capture Compare 3 Interrupt source\r
+* - TIM_IT_CC4: Timer Capture Compare 4 Interrupt source\r
+* - TIM_IT_Trigger: Timer Trigger Interrupt source\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM_IT(TIM_IT));\r
+ \r
+ /* Clear the IT pending Bit */\r
+ TIMx->SR &= (u16)~TIM_IT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : PWMInput_Config\r
+* Description : Configures the TIM peripheral according to the specified\r
+* parameters in the TIM_ICInitStruct to measure an external PWM\r
+* signal.\r
+* Input : - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+* that contains the configuration information for the specified\r
+* TIM peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void PWMI_Config(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ u8 ICPolarity = TIM_ICPolarity_Rising;\r
+ u8 ICSelection = TIM_ICSelection_DirectTI;\r
+\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
+ {\r
+ ICPolarity = TIM_ICPolarity_Falling;\r
+ }\r
+ else\r
+ {\r
+ ICPolarity = TIM_ICPolarity_Rising;\r
+ }\r
+\r
+ /* Select the Opposite Input */\r
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
+ {\r
+ ICSelection = TIM_ICSelection_IndirectTI;\r
+ }\r
+ else\r
+ {\r
+ ICSelection = TIM_ICSelection_DirectTI;\r
+ }\r
+\r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ { \r
+ /* TI1 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+\r
+ /* TI2 Configuration */\r
+ TI1_Config(TIMx, ICPolarity, ICSelection, TIM_ICInitStruct->TIM_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TI1_Config\r
+* Description : Configure the TI1 as Input.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ICPolarity : The Input Polarity.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICPolarity_Rising\r
+* - TIM_ICPolarity_Falling\r
+* - TIM_ICSelection: specifies the input to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICSelection_DirectTI: TIM Input 1 is selected to\r
+* be connected to IC1.\r
+* - TIM_ICSelection_IndirectTI: TIM Input 1 is selected to\r
+* be connected to IC2.\r
+* - TIM_ICSelection_TRGI: TIM Input 1 is selected to be\r
+* connected to TRGI.\r
+* - TIM_ICFilter: Specifies the Input Capture Filter.\r
+* This parameter must be a value between 0x00 and 0x0F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,\r
+ u8 TIM_ICFilter)\r
+{\r
+ u32 tmpccmr1 = 0, tmpccer = 0;\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ TIMx->CCER &= CCRE_CC1E_Reset;\r
+\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;\r
+ tmpccmr1 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4);\r
+\r
+ /* Select the Polarity and set the CCE Bit */\r
+ tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask;\r
+ tmpccer |= TIM_ICPolarity | CCRE_CC1E_Set;\r
+\r
+ TIMx->CCMR1 = 0x0000;\r
+ TIMx->CCMR1 = (u16)tmpccmr1;\r
+ TIMx->CCER = (u16)tmpccer;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TI2_Config\r
+* Description : Configure the TI2 as Input.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ICPolarity : The Input Polarity.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICPolarity_Rising\r
+* - TIM_ICPolarity_Falling\r
+* - TIM_ICSelection: specifies the input to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICSelection_DirectTI: TIM Input 2 is selected to\r
+* be connected to IC2.\r
+* - TIM_ICSelection_IndirectTI: TIM Input 2 is selected to\r
+* be connected to IC1.\r
+* - TIM_ICSelection_TRGI: TIM Input 2 is selected to be\r
+* connected to TRGI.\r
+* - TIM_ICFilter: Specifies the Input Capture Filter.\r
+* This parameter must be a value between 0x00 and 0x0F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,\r
+ u8 TIM_ICFilter)\r
+{\r
+ u32 tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (u16)((u16)TIM_ICPolarity << 4);\r
+\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ TIMx->CCER &= CCRE_CC2E_Reset;\r
+\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;\r
+ tmpccmr1 |= (u16)((u16)TIM_ICFilter << 12);\r
+ tmpccmr1 |= (u16)((u16)TIM_ICSelection << 8);\r
+\r
+ /* Select the Polarity and set the CCE Bit */\r
+ tmpccer &= CCER_CC2P_Mask & CCRE_CC2E_Mask;\r
+ tmpccer |= tmp | CCRE_CC2E_Set;\r
+\r
+ TIMx->CCMR1 = (u16)tmpccmr1 ;\r
+ TIMx->CCER = (u16)tmpccer;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TI3_Config\r
+* Description : Configure the TI3 as Input.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ICPolarity : The Input Polarity.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICPolarity_Rising\r
+* - TIM_ICPolarity_Falling\r
+* - TIM_ICSelection: specifies the input to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICSelection_DirectTI: TIM Input 3 is selected to\r
+* be connected to IC3.\r
+* - TIM_ICSelection_IndirectTI: TIM Input 3 is selected to\r
+* be connected to IC4.\r
+* - TIM_ICSelection_TRGI: TIM Input 3 is selected to be\r
+* connected to TRGI.\r
+* - TIM_ICFilter: Specifies the Input Capture Filter.\r
+* This parameter must be a value between 0x00 and 0x0F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,\r
+ u8 TIM_ICFilter)\r
+{\r
+ u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (u16)((u16)TIM_ICPolarity << 8);\r
+\r
+ /* Disable the Channel 3: Reset the CCE Bit */\r
+ TIMx->CCER &= CCRE_CC3E_Reset;\r
+\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;\r
+ tmpccmr2 |= TIM_ICSelection | (u16)((u16)TIM_ICFilter << 4);\r
+\r
+ /* Select the Polarity and set the CCE Bit */\r
+ tmpccer &= CCER_CC1P_Mask & CCRE_CC1E_Mask;\r
+ tmpccer |= tmp | CCRE_CC3E_Set;\r
+\r
+ TIMx->CCMR2 = (u16)tmpccmr2;\r
+ TIMx->CCER = (u16)tmpccer;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TI4_Config\r
+* Description : Configure the TI1 as Input.\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ICPolarity : The Input Polarity.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICPolarity_Rising\r
+* - TIM_ICPolarity_Falling\r
+* - TIM_ICSelection: specifies the input to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM_ICSelection_DirectTI: TIM Input 4 is selected to\r
+* be connected to IC4.\r
+* - TIM_ICSelection_IndirectTI: TIM Input 4 is selected to\r
+* be connected to IC3.\r
+* - TIM_ICSelection_TRGI: TIM Input 4 is selected to be\r
+* connected to TRGI.\r
+* - TIM_ICFilter: Specifies the Input Capture Filter.\r
+* This parameter must be a value between 0x00 and 0x0F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,\r
+ u8 TIM_ICFilter)\r
+{\r
+ u32 tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (u16)((u16)TIM_ICPolarity << 12);\r
+\r
+ /* Disable the Channel 4: Reset the CCE Bit */\r
+ TIMx->CCER &= CCRE_CC4E_Reset;\r
+\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;\r
+ tmpccmr2 |= (u16)((u16)TIM_ICSelection << 8) | (u16)((u16)TIM_ICFilter << 12);\r
+\r
+ /* Select the Polarity and set the CCE Bit */\r
+ tmpccer &= CCER_CC4P_Mask & CCRE_CC4E_Mask;\r
+ tmpccer |= tmp | CCRE_CC4E_Set;\r
+\r
+ TIMx->CCMR2 = (u16)tmpccmr2;\r
+ TIMx->CCER = (u16)tmpccer ;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETR_Config\r
+* Description : Configure the External Trigger\r
+* Input : - TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.\r
+* - TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+* This parameter can be one of the following values:\r
+* - TIM_ExtTRGPSC_OFF\r
+* - TIM_ExtTRGPSC_DIV2\r
+* - TIM_ExtTRGPSC_DIV4\r
+* - TIM_ExtTRGPSC_DIV8\r
+* - TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+* This parameter can be one of the following values:\r
+* - TIM_ExtTRGPolarity_Inverted\r
+* - TIM_ExtTRGPolarity_NonInverted\r
+* - ExtTRGFilter: External Trigger Filter.\r
+* This parameter must be a value between 0x00 and 0x0F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void ETR_Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,\r
+ u8 ExtTRGFilter)\r
+{\r
+ u32 tmpsmcr = 0;\r
+\r
+ tmpsmcr = TIMx->SMCR;\r
+\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr &= SMCR_ETR_Mask;\r
+ tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8);\r
+\r
+ TIMx->SMCR = (u16)tmpsmcr;\r
+}\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_tim1.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the TIM1 software functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* mm/dd/yyyy: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_tim1.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/* ------------ TIM1 registers bit address in the alias region ----------- */\r
+#define TIM1_OFFSET (TIM1_BASE - PERIPH_BASE)\r
+\r
+/* --- TIM1 CR1 Register ---*/\r
+/* Alias word address of CEN bit */\r
+#define CR1_OFFSET (TIM1_OFFSET + 0x00)\r
+#define CEN_BitNumber 0x00\r
+#define CR1_CEN_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (CEN_BitNumber * 4))\r
+\r
+/* Alias word address of UDIS bit */\r
+#define UDIS_BitNumber 0x01\r
+#define CR1_UDIS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (UDIS_BitNumber * 4))\r
+\r
+/* Alias word address of URS bit */\r
+#define URS_BitNumber 0x02\r
+#define CR1_URS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (URS_BitNumber * 4))\r
+\r
+/* Alias word address of OPM bit */\r
+#define OPM_BitNumber 0x03\r
+#define CR1_OPM_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (OPM_BitNumber * 4))\r
+\r
+/* Alias word address of ARPE bit */\r
+#define ARPE_BitNumber 0x07\r
+#define CR1_ARPE_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (ARPE_BitNumber * 4))\r
+\r
+/* --- TIM1 CR2 Register --- */\r
+/* Alias word address of CCPC bit */\r
+#define CR2_OFFSET (TIM1_OFFSET + 0x04)\r
+#define CCPC_BitNumber 0x00\r
+#define CR2_CCPC_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCPC_BitNumber * 4))\r
+\r
+/* Alias word address of CCUS bit */\r
+#define CCUS_BitNumber 0x02\r
+#define CR2_CCUS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCUS_BitNumber * 4))\r
+\r
+/* Alias word address of CCDS bit */\r
+#define CCDS_BitNumber 0x03\r
+#define CR2_CCDS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCDS_BitNumber * 4))\r
+\r
+/* Alias word address of TI1S bit */\r
+#define TI1S_BitNumber 0x07\r
+#define CR2_TI1S_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (TI1S_BitNumber * 4))\r
+\r
+/* Alias word address of OIS1 bit */\r
+#define OIS1_BitNumber 0x08\r
+#define CR2_OIS1_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1_BitNumber * 4))\r
+\r
+/* Alias word address of OIS1N bit */\r
+#define OIS1N_BitNumber 0x09\r
+#define CR2_OIS1N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1N_BitNumber * 4))\r
+\r
+/* Alias word address of OIS2 bit */\r
+#define OIS2_BitNumber 0x0A\r
+#define CR2_OIS2_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2_BitNumber * 4))\r
+\r
+/* Alias word address of OIS2N bit */\r
+#define OIS2N_BitNumber 0x0B\r
+#define CR2_OIS2N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2N_BitNumber * 4))\r
+\r
+/* Alias word address of OIS3 bit */\r
+#define OIS3_BitNumber 0x0C\r
+#define CR2_OIS3_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3_BitNumber * 4))\r
+\r
+/* Alias word address of OIS3N bit */\r
+#define OIS3N_BitNumber 0x0D\r
+#define CR2_OIS3N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3N_BitNumber * 4))\r
+\r
+/* Alias word address of OIS4 bit */\r
+#define OIS4_BitNumber 0x0E\r
+#define CR2_OIS4_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS4_BitNumber * 4))\r
+\r
+/* --- TIM1 SMCR Register --- */\r
+/* Alias word address of MSM bit */\r
+#define SMCR_OFFSET (TIM1_OFFSET + 0x08)\r
+#define MSM_BitNumber 0x07\r
+#define SMCR_MSM_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (MSM_BitNumber * 4))\r
+\r
+/* Alias word address of ECE bit */\r
+#define ECE_BitNumber 0x0E\r
+#define SMCR_ECE_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (ECE_BitNumber * 4))\r
+\r
+/* --- TIM1 EGR Register --- */\r
+/* Alias word address of UG bit */\r
+#define EGR_OFFSET (TIM1_OFFSET + 0x14)\r
+#define UG_BitNumber 0x00\r
+#define EGR_UG_BB (PERIPH_BB_BASE + (EGR_OFFSET * 32) + (UG_BitNumber * 4))\r
+\r
+/* --- TIM1 CCER Register --- */\r
+/* Alias word address of CC1E bit */\r
+#define CCER_OFFSET (TIM1_OFFSET + 0x20)\r
+#define CC1E_BitNumber 0x00\r
+#define CCER_CC1E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1E_BitNumber * 4))\r
+\r
+/* Alias word address of CC1P bit */\r
+#define CC1P_BitNumber 0x01\r
+#define CCER_CC1P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1P_BitNumber * 4))\r
+\r
+/* Alias word address of CC1NE bit */\r
+#define CC1NE_BitNumber 0x02\r
+#define CCER_CC1NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NE_BitNumber * 4))\r
+\r
+/* Alias word address of CC1NP bit */\r
+#define CC1NP_BitNumber 0x03\r
+#define CCER_CC1NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NP_BitNumber * 4))\r
+\r
+/* Alias word address of CC2E bit */\r
+#define CC2E_BitNumber 0x04\r
+#define CCER_CC2E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2E_BitNumber * 4))\r
+\r
+/* Alias word address of CC2P bit */\r
+#define CC2P_BitNumber 0x05\r
+#define CCER_CC2P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2P_BitNumber * 4))\r
+\r
+/* Alias word address of CC2NE bit */\r
+#define CC2NE_BitNumber 0x06\r
+#define CCER_CC2NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NE_BitNumber * 4))\r
+\r
+/* Alias word address of CC2NP bit */\r
+#define CC2NP_BitNumber 0x07\r
+#define CCER_CC2NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NP_BitNumber * 4))\r
+\r
+/* Alias word address of CC3E bit */\r
+#define CC3E_BitNumber 0x08\r
+#define CCER_CC3E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3E_BitNumber * 4))\r
+\r
+/* Alias word address of CC3P bit */\r
+#define CC3P_BitNumber 0x09\r
+#define CCER_CC3P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3P_BitNumber * 4))\r
+\r
+/* Alias word address of CC3NE bit */\r
+#define CC3NE_BitNumber 0x0A\r
+#define CCER_CC3NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NE_BitNumber * 4))\r
+\r
+/* Alias word address of CC3NP bit */\r
+#define CC3NP_BitNumber 0x0B\r
+#define CCER_CC3NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NP_BitNumber * 4))\r
+\r
+/* Alias word address of CC4E bit */\r
+#define CC4E_BitNumber 0x0C\r
+#define CCER_CC4E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4E_BitNumber * 4))\r
+\r
+/* Alias word address of CC4P bit */\r
+#define CC4P_BitNumber 0x0D\r
+#define CCER_CC4P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4P_BitNumber * 4))\r
+\r
+/* --- TIM1 BDTR Register --- */\r
+/* Alias word address of MOE bit */\r
+#define BDTR_OFFSET (TIM1_OFFSET + 0x44)\r
+#define MOE_BitNumber 0x0F\r
+#define BDTR_MOE_BB (PERIPH_BB_BASE + (BDTR_OFFSET * 32) + (MOE_BitNumber * 4))\r
+\r
+/* --- TIM1 CCMR1 Register --- */\r
+/* Alias word address of OC1FE bit */\r
+#define CCMR1_OFFSET (TIM1_OFFSET + 0x18)\r
+#define OC1FE_BitNumber 0x02\r
+#define CCMR1_OC1FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1FE_BitNumber * 4))\r
+\r
+/* Alias word address of OC1PE bit */\r
+#define OC1PE_BitNumber 0x03\r
+#define CCMR1_OC1PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1PE_BitNumber * 4))\r
+\r
+/* Alias word address of OC2FE bit */\r
+#define OC2FE_BitNumber 0x0A\r
+#define CCMR1_OC2FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2FE_BitNumber * 4))\r
+\r
+/* Alias word address of OC2PE bit */\r
+#define OC2PE_BitNumber 0x0B\r
+#define CCMR1_OC2PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2PE_BitNumber * 4))\r
+\r
+/* --- TIM1 CCMR2 Register ---- */\r
+/* Alias word address of OC3FE bit */\r
+#define CCMR2_OFFSET (TIM1_OFFSET + 0x1C)\r
+#define OC3FE_BitNumber 0x02\r
+#define CCMR2_OC3FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3FE_BitNumber * 4))\r
+\r
+/* Alias word address of OC3PE bit */\r
+#define OC3PE_BitNumber 0x03\r
+#define CCMR2_OC3PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC3PE_BitNumber * 4))\r
+\r
+/* Alias word address of OC4FE bit */\r
+#define OC4FE_BitNumber 0x0A\r
+#define CCMR2_OC4FE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4FE_BitNumber * 4))\r
+\r
+/* Alias word address of OC4PE bit */\r
+#define OC4PE_BitNumber 0x0B\r
+#define CCMR2_OC4PE_BB (PERIPH_BB_BASE + (CCMR2_OFFSET * 32) + (OC4PE_BitNumber * 4))\r
+\r
+/* --------------------- TIM1 registers bit mask ------------------------- */\r
+/* TIM1 CR1 Mask */\r
+#define CR1_CounterMode_Mask ((u16)0x039F)\r
+#define CR1_CKD_Mask ((u16)0x00FF)\r
+\r
+/* TIM1 CR2 Mask */\r
+#define CR2_MMS_Mask ((u16)0x0080)\r
+\r
+/* TIM1 SMCR Mask */\r
+#define SMCR_SMS_Mask ((u16)0xFFF0)\r
+#define SMCR_ETR_Mask ((u16)0x40F7)\r
+#define SMCR_TS_Mask ((u16)0xFF87)\r
+#define SMCR_ECE_Set ((u16)0x0001)\r
+\r
+/* TIM1 CCMRx Mask */\r
+#define CCMR_CC13S_Mask ((u16)0xFFFC)\r
+#define CCMR_CC24S_Mask ((u16)0xFCFF)\r
+#define CCMR_TI13Direct_Set ((u16)0x0001)\r
+#define CCMR_TI24Direct_Set ((u16)0x0100)\r
+#define CCMR_OCM13_Mask ((u16)0x7F0F)\r
+#define CCMR_OCM24_Mask ((u16)0x0F7F)\r
+#define CCMR_IC13PSC_Mask ((u16)0xFFF3)\r
+#define CCMR_IC24PSC_Mask ((u16)0xF3FF)\r
+#define CCMR_IC13F_Mask ((u16)0xFF0F)\r
+#define CCMR_IC24F_Mask ((u16)0x0FFF)\r
+#define OC13Mode_Mask ((u16)0xFF00)\r
+#define OC24Mode_Mask ((u16)0x00FF)\r
+\r
+/* TIM1 CCER Set/Reset Bit */\r
+#define CCER_CCE_Set ((u16)0x0001)\r
+#define CCER_CCE_Reset ((u16)0x0000)\r
+\r
+/* TIM1 DMA Mask */\r
+#define DCR_DMA_Mask ((u16)0x0000)\r
+\r
+/* TIM1 private Masks */\r
+#define TIM1_Period_Reset_Mask ((u16)0xFFFF)\r
+#define TIM1_Prescaler_Reset_Mask ((u16)0x0000)\r
+#define TIM1_RepetitionCounter_Reset_Mask ((u16)0x0000)\r
+#define TIM1_Pulse_Reset_Mask ((u16)0x0000)\r
+#define TIM1_ICFilter_Mask ((u8)0x00)\r
+#define TIM1_DeadTime_Reset_Mask ((u16)0x0000)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,\r
+ u16 ExtTRGFilter);\r
+static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,\r
+ u8 TIM1_ICFilter);\r
+static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,\r
+ u8 TIM1_ICFilter);\r
+static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,\r
+ u8 TIM1_ICFilter);\r
+static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,\r
+ u8 TIM1_ICFilter);\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_DeInit\r
+* Description : Deinitializes the TIM1 peripheral registers to their default\r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_DeInit(void)\r
+{\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_TimeBaseInit\r
+* Description : Initializes the TIM1 Time Base Unit according to the specified\r
+* parameters in the TIM1_TimeBaseInitStruct.\r
+* Input : - TIM1_TimeBaseInitStruct: pointer to a TIM1_TimeBaseInitTypeDef\r
+* structure that contains the configuration information for\r
+* the specified TIM1 peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_TimeBaseInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_COUNTER_MODE(TIM1_TimeBaseInitStruct->TIM1_CounterMode));\r
+ assert(IS_TIM1_CKD_DIV(TIM1_TimeBaseInitStruct->TIM1_ClockDivision));\r
+\r
+ /* Set the Autoreload value */\r
+ TIM1->ARR = TIM1_TimeBaseInitStruct->TIM1_Period ;\r
+\r
+ /* Set the Prescaler value */\r
+ TIM1->PSC = TIM1_TimeBaseInitStruct->TIM1_Prescaler;\r
+\r
+ /* Select the Counter Mode and set the clock division */\r
+ TIM1->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;\r
+ TIM1->CR1 |= (u32)TIM1_TimeBaseInitStruct->TIM1_ClockDivision |\r
+ TIM1_TimeBaseInitStruct->TIM1_CounterMode;\r
+\r
+ /* Set the Repetition Counter value */\r
+ TIM1->RCR = TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC1Init\r
+* Description : Initializes the TIM1 Channel1 according to the specified\r
+* parameters in the TIM1_OCInitStruct.\r
+* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that\r
+* contains the configuration information for the TIM1 peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC1Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)\r
+{\r
+ u16 tmpccmr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));\r
+ assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));\r
+ assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));\r
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));\r
+ assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));\r
+ assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));\r
+ assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState)); \r
+\r
+ tmpccmr = TIM1->CCMR1;\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;\r
+\r
+ /* Reset the Output Compare Bits */\r
+ tmpccmr &= OC13Mode_Mask;\r
+\r
+ /* Set the Ouput Compare Mode */\r
+ tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;\r
+\r
+ TIM1->CCMR1 = tmpccmr;\r
+\r
+ /* Set the Output State */\r
+ *(vu32 *) CCER_CC1E_BB = TIM1_OCInitStruct->TIM1_OutputState;\r
+\r
+ /* Set the Output N State */\r
+ *(vu32 *) CCER_CC1NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;\r
+\r
+ /* Set the Output Polarity */\r
+ *(vu32 *) CCER_CC1P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;\r
+\r
+ /* Set the Output N Polarity */\r
+ *(vu32 *) CCER_CC1NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;\r
+\r
+ /* Set the Output Idle state */\r
+ *(vu32 *) CR2_OIS1_BB = TIM1_OCInitStruct->TIM1_OCIdleState;\r
+\r
+ /* Set the Output N Idle state */\r
+ *(vu32 *) CR2_OIS1N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;\r
+\r
+ /* Set the Pulse value */\r
+ TIM1->CCR1 = TIM1_OCInitStruct->TIM1_Pulse;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC2Init\r
+* Description : Initializes the TIM1 Channel2 according to the specified\r
+* parameters in the TIM1_OCInitStruct.\r
+* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that\r
+* contains the configuration information for the TIM1 peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC2Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)\r
+{\r
+ u32 tmpccmr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));\r
+ assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));\r
+ assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));\r
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));\r
+ assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));\r
+ assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));\r
+ assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));\r
+\r
+ tmpccmr = TIM1->CCMR1;\r
+\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;\r
+\r
+ /* Reset the Output Compare Bits */\r
+ tmpccmr &= OC24Mode_Mask;\r
+\r
+ /* Set the Ouput Compare Mode */\r
+ tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;\r
+\r
+ TIM1->CCMR1 = (u16)tmpccmr;\r
+\r
+ /* Set the Output State */\r
+ *(vu32 *) CCER_CC2E_BB = TIM1_OCInitStruct->TIM1_OutputState;\r
+\r
+ /* Set the Output N State */\r
+ *(vu32 *) CCER_CC2NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;\r
+\r
+ /* Set the Output Polarity */\r
+ *(vu32 *) CCER_CC2P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;\r
+\r
+ /* Set the Output N Polarity */\r
+ *(vu32 *) CCER_CC2NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;\r
+\r
+ /* Set the Output Idle state */\r
+ *(vu32 *) CR2_OIS2_BB = TIM1_OCInitStruct->TIM1_OCIdleState;\r
+\r
+ /* Set the Output N Idle state */\r
+ *(vu32 *) CR2_OIS2N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;\r
+\r
+ /* Set the Pulse value */\r
+ TIM1->CCR2 = TIM1_OCInitStruct->TIM1_Pulse;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC3Init\r
+* Description : Initializes the TIM1 Channel3 according to the specified\r
+* parameters in the TIM1_OCInitStruct.\r
+* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that\r
+* contains the configuration information for the TIM1 peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC3Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)\r
+{\r
+ u16 tmpccmr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));\r
+ assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));\r
+ assert(IS_TIM1_OUTPUTN_STATE(TIM1_OCInitStruct->TIM1_OutputNState));\r
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));\r
+ assert(IS_TIM1_OCN_POLARITY(TIM1_OCInitStruct->TIM1_OCNPolarity));\r
+ assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));\r
+ assert(IS_TIM1_OCNIDLE_STATE(TIM1_OCInitStruct->TIM1_OCNIdleState));\r
+\r
+ tmpccmr = TIM1->CCMR2;\r
+\r
+ /* Disable the Channel 3: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;\r
+\r
+ /* Reset the Output Compare Bits */\r
+ tmpccmr &= OC13Mode_Mask;\r
+\r
+ /* Set the Ouput Compare Mode */\r
+ tmpccmr |= TIM1_OCInitStruct->TIM1_OCMode;\r
+\r
+ TIM1->CCMR2 = tmpccmr;\r
+\r
+ /* Set the Output State */\r
+ *(vu32 *) CCER_CC3E_BB = TIM1_OCInitStruct->TIM1_OutputState;\r
+\r
+ /* Set the Output N State */\r
+ *(vu32 *) CCER_CC3NE_BB = TIM1_OCInitStruct->TIM1_OutputNState;\r
+\r
+ /* Set the Output Polarity */\r
+ *(vu32 *) CCER_CC3P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;\r
+\r
+ /* Set the Output N Polarity */\r
+ *(vu32 *) CCER_CC3NP_BB = TIM1_OCInitStruct->TIM1_OCNPolarity;\r
+\r
+ /* Set the Output Idle state */\r
+ *(vu32 *) CR2_OIS3_BB = TIM1_OCInitStruct->TIM1_OCIdleState;\r
+\r
+ /* Set the Output N Idle state */\r
+ *(vu32 *) CR2_OIS3N_BB = TIM1_OCInitStruct->TIM1_OCNIdleState;\r
+\r
+ /* Set the Pulse value */\r
+ TIM1->CCR3 = TIM1_OCInitStruct->TIM1_Pulse;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC4Init\r
+* Description : Initializes the TIM1 Channel4 according to the specified\r
+* parameters in the TIM1_OCInitStruct.\r
+* Input : - TIM1_OCInitStruct: pointer to a TIM1_OCInitTypeDef structure that\r
+* contains the configuration information for the TIM1 peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC4Init(TIM1_OCInitTypeDef* TIM1_OCInitStruct)\r
+{\r
+ u32 tmpccmr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OC_MODE(TIM1_OCInitStruct->TIM1_OCMode));\r
+ assert(IS_TIM1_OUTPUT_STATE(TIM1_OCInitStruct->TIM1_OutputState));\r
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCInitStruct->TIM1_OCPolarity));\r
+ assert(IS_TIM1_OCIDLE_STATE(TIM1_OCInitStruct->TIM1_OCIdleState));\r
+\r
+ tmpccmr = TIM1->CCMR2;\r
+\r
+ /* Disable the Channel 4: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;\r
+\r
+ /* Reset the Output Compare Bits */\r
+ tmpccmr &= OC24Mode_Mask;\r
+\r
+ /* Set the Ouput Compare Mode */\r
+ tmpccmr |= (u32)TIM1_OCInitStruct->TIM1_OCMode << 8;\r
+\r
+ TIM1->CCMR2 = (u16)tmpccmr;\r
+\r
+ /* Set the Output State */\r
+ *(vu32 *) CCER_CC4E_BB = TIM1_OCInitStruct->TIM1_OutputState;\r
+\r
+ /* Set the Output Polarity */\r
+ *(vu32 *) CCER_CC4P_BB = TIM1_OCInitStruct->TIM1_OCPolarity;\r
+\r
+ /* Set the Output Idle state */\r
+ *(vu32 *) CR2_OIS4_BB = TIM1_OCInitStruct->TIM1_OCIdleState;\r
+\r
+ /* Set the Pulse value */\r
+ TIM1->CCR4 = TIM1_OCInitStruct->TIM1_Pulse;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_BDTRConfig\r
+* Description : Configures the: Break feature, dead time, Lock level, the OSSI,\r
+* the OSSR State and the AOE(automatic output enable).\r
+* Input : - TIM1_BDTRInitStruct: pointer to a TIM1_BDTRInitTypeDef\r
+* structure that contains the BDTR Register configuration\r
+* information for the TIM1 peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_BDTRConfig(TIM1_BDTRInitTypeDef *TIM1_BDTRInitStruct)\r
+{\r
+ u16 tmpbdtr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OSSR_STATE(TIM1_BDTRInitStruct->TIM1_OSSRState));\r
+ assert(IS_TIM1_OSSI_STATE(TIM1_BDTRInitStruct->TIM1_OSSIState));\r
+ assert(IS_TIM1_LOCK_LEVEL(TIM1_BDTRInitStruct->TIM1_LOCKLevel));\r
+ assert(IS_TIM1_BREAK_STATE(TIM1_BDTRInitStruct->TIM1_Break));\r
+ assert(IS_TIM1_BREAK_POLARITY(TIM1_BDTRInitStruct->TIM1_BreakPolarity));\r
+ assert(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_BDTRInitStruct->TIM1_AutomaticOutput));\r
+\r
+ tmpbdtr = TIM1->BDTR;\r
+\r
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,\r
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
+\r
+ tmpbdtr = (u32)TIM1_BDTRInitStruct->TIM1_OSSRState | TIM1_BDTRInitStruct->TIM1_OSSIState |\r
+ TIM1_BDTRInitStruct->TIM1_LOCKLevel | TIM1_BDTRInitStruct->TIM1_DeadTime |\r
+ TIM1_BDTRInitStruct->TIM1_Break | TIM1_BDTRInitStruct->TIM1_BreakPolarity |\r
+ TIM1_BDTRInitStruct->TIM1_AutomaticOutput;\r
+\r
+ TIM1->BDTR = tmpbdtr;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ICInit\r
+* Description : Initializes the TIM1 peripheral according to the specified\r
+* parameters in the TIM1_ICInitStruct.\r
+* Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure\r
+* that contains the configuration information for the specified\r
+* TIM1 peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ICInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));\r
+ assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));\r
+ assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));\r
+ assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));\r
+ assert(IS_TIM1_IC_FILTER(TIM1_ICInitStruct->TIM1_ICFilter));\r
+\r
+ if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity,\r
+ TIM1_ICInitStruct->TIM1_ICSelection,\r
+ TIM1_ICInitStruct->TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);\r
+ }\r
+ else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity,\r
+ TIM1_ICInitStruct->TIM1_ICSelection,\r
+ TIM1_ICInitStruct->TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);\r
+ }\r
+ else if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_3)\r
+ {\r
+ /* TI3 Configuration */\r
+ TI3_Config(TIM1_ICInitStruct->TIM1_ICPolarity,\r
+ TIM1_ICInitStruct->TIM1_ICSelection,\r
+ TIM1_ICInitStruct->TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC3Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI4 Configuration */\r
+ TI4_Config(TIM1_ICInitStruct->TIM1_ICPolarity,\r
+ TIM1_ICInitStruct->TIM1_ICSelection,\r
+ TIM1_ICInitStruct->TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC4Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_PWMIConfig\r
+* Description : Configures the TIM1 peripheral in PWM Input Mode according \r
+* to the specified parameters in the TIM1_ICInitStruct.\r
+* Input : - TIM1_ICInitStruct: pointer to a TIM1_ICInitTypeDef structure\r
+* that contains the configuration information for the specified\r
+* TIM1 peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_PWMIConfig(TIM1_ICInitTypeDef* TIM1_ICInitStruct)\r
+{\r
+ u8 ICPolarity = TIM1_ICPolarity_Rising;\r
+ u8 ICSelection = TIM1_ICSelection_DirectTI;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_PWMI_CHANNEL(TIM1_ICInitStruct->TIM1_Channel));\r
+ assert(IS_TIM1_IC_POLARITY(TIM1_ICInitStruct->TIM1_ICPolarity));\r
+ assert(IS_TIM1_IC_SELECTION(TIM1_ICInitStruct->TIM1_ICSelection));\r
+ assert(IS_TIM1_IC_PRESCALER(TIM1_ICInitStruct->TIM1_ICPrescaler));\r
+\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM1_ICInitStruct->TIM1_ICPolarity == TIM1_ICPolarity_Rising)\r
+ {\r
+ ICPolarity = TIM1_ICPolarity_Falling;\r
+ }\r
+ else\r
+ {\r
+ ICPolarity = TIM1_ICPolarity_Rising;\r
+ }\r
+\r
+ /* Select the Opposite Input */\r
+ if (TIM1_ICInitStruct->TIM1_ICSelection == TIM1_ICSelection_DirectTI)\r
+ {\r
+ ICSelection = TIM1_ICSelection_IndirectTI;\r
+ }\r
+ else\r
+ {\r
+ ICSelection = TIM1_ICSelection_DirectTI;\r
+ }\r
+\r
+ if (TIM1_ICInitStruct->TIM1_Channel == TIM1_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection,\r
+ TIM1_ICInitStruct->TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);\r
+\r
+ /* TI2 Configuration */\r
+ TI2_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);\r
+ }\r
+ else\r
+ { \r
+ /* TI2 Configuration */\r
+ TI2_Config(TIM1_ICInitStruct->TIM1_ICPolarity, TIM1_ICInitStruct->TIM1_ICSelection,\r
+ TIM1_ICInitStruct->TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC2Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);\r
+\r
+ /* TI1 Configuration */\r
+ TI1_Config(ICPolarity, ICSelection, TIM1_ICInitStruct->TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC1Prescaler(TIM1_ICInitStruct->TIM1_ICPrescaler);\r
+ }\r
+}\r
+/*******************************************************************************\r
+* Function Name : TIM1_OCStructInit\r
+* Description : Fills each TIM1_OCInitStruct member with its default value.\r
+* Input : - TIM1_OCInitStruct : pointer to a TIM1_OCInitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OCStructInit(TIM1_OCInitTypeDef* TIM1_OCInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM1_OCInitStruct->TIM1_OCMode = TIM1_OCMode_Timing;\r
+ TIM1_OCInitStruct->TIM1_OutputState = TIM1_OutputState_Disable;\r
+ TIM1_OCInitStruct->TIM1_OutputNState = TIM1_OutputNState_Disable;\r
+ TIM1_OCInitStruct->TIM1_Pulse = TIM1_Pulse_Reset_Mask;\r
+ TIM1_OCInitStruct->TIM1_OCPolarity = TIM1_OCPolarity_High;\r
+ TIM1_OCInitStruct->TIM1_OCNPolarity = TIM1_OCPolarity_High;\r
+ TIM1_OCInitStruct->TIM1_OCIdleState = TIM1_OCIdleState_Reset;\r
+ TIM1_OCInitStruct->TIM1_OCNIdleState = TIM1_OCNIdleState_Reset;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ICStructInit\r
+* Description : Fills each TIM1_ICInitStruct member with its default value.\r
+* Input : - TIM1_ICInitStruct : pointer to a TIM1_ICInitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ICStructInit(TIM1_ICInitTypeDef* TIM1_ICInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM1_ICInitStruct->TIM1_Channel = TIM1_Channel_1;\r
+ TIM1_ICInitStruct->TIM1_ICSelection = TIM1_ICSelection_DirectTI;\r
+ TIM1_ICInitStruct->TIM1_ICPolarity = TIM1_ICPolarity_Rising;\r
+ TIM1_ICInitStruct->TIM1_ICPrescaler = TIM1_ICPSC_DIV1;\r
+ TIM1_ICInitStruct->TIM1_ICFilter = TIM1_ICFilter_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_TimeBaseStructInit\r
+* Description : Fills each TIM1_TimeBaseInitStruct member with its default value.\r
+* Input : - TIM1_TimeBaseInitStruct : pointer to a TIM1_TimeBaseInitTypeDef\r
+* structure which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_TimeBaseStructInit(TIM1_TimeBaseInitTypeDef* TIM1_TimeBaseInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM1_TimeBaseInitStruct->TIM1_Period = TIM1_Period_Reset_Mask;\r
+ TIM1_TimeBaseInitStruct->TIM1_Prescaler = TIM1_Prescaler_Reset_Mask;\r
+ TIM1_TimeBaseInitStruct->TIM1_ClockDivision = TIM1_CKD_DIV1;\r
+ TIM1_TimeBaseInitStruct->TIM1_CounterMode = TIM1_CounterMode_Up;\r
+ TIM1_TimeBaseInitStruct->TIM1_RepetitionCounter = TIM1_RepetitionCounter_Reset_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_BDTRStructInit\r
+* Description : Fills each TIM1_BDTRInitStruct member with its default value.\r
+* Input : - TIM1_BDTRInitStruct : pointer to a TIM1_BDTRInitTypeDef\r
+* structure which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_BDTRStructInit(TIM1_BDTRInitTypeDef* TIM1_BDTRInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM1_BDTRInitStruct->TIM1_OSSRState = TIM1_OSSRState_Disable;\r
+ TIM1_BDTRInitStruct->TIM1_OSSIState = TIM1_OSSIState_Disable;\r
+ TIM1_BDTRInitStruct->TIM1_LOCKLevel = TIM1_LOCKLevel_OFF;\r
+ TIM1_BDTRInitStruct->TIM1_DeadTime = TIM1_DeadTime_Reset_Mask;\r
+ TIM1_BDTRInitStruct->TIM1_Break = TIM1_Break_Disable;\r
+ TIM1_BDTRInitStruct->TIM1_BreakPolarity = TIM1_BreakPolarity_Low;\r
+ TIM1_BDTRInitStruct->TIM1_AutomaticOutput = TIM1_AutomaticOutput_Disable;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_Cmd\r
+* Description : Enables or disables the TIM1 peripheral.\r
+* Input : - Newstate: new state of the TIM1 peripheral.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ /* set or Reset the CEN Bit */\r
+ *(vu32 *) CR1_CEN_BB = (u16)NewState;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_CtrlPWMOutputs\r
+* Description : Enables or disables the TIM1 peripheral Main Outputs.\r
+* Input : - Newstate: new state of the TIM1 peripheral Main Outputs.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_CtrlPWMOutputs(FunctionalState Newstate)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ /* Set or Reset the MOE Bit */\r
+ *(vu32 *) BDTR_MOE_BB = (u16)Newstate;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ITConfig\r
+* Description : Enables or disables the specified TIM1 interrupts.\r
+* Input : - TIM1_IT: specifies the TIM1 interrupts sources to be enabled\r
+* or disabled.\r
+* This parameter can be any combination of the following values:\r
+* - TIM1_IT_Update: TIM1 update Interrupt source\r
+* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source\r
+* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source\r
+* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source\r
+* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source\r
+* - TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt\r
+* source\r
+* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source\r
+* - TIM1_IT_Break: TIM1 Break Interrupt source\r
+* - Newstate: new state of the TIM1 interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ITConfig(u16 TIM1_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_IT(TIM1_IT));\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIM1->DIER |= TIM1_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIM1->DIER &= (u16)~TIM1_IT;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_DMAConfig\r
+* Description : Configures the TIM1\92s DMA interface.\r
+* Input : - TIM1_DMABase: DMA Base address.\r
+* This parameter can be one of the following values:\r
+* - TIM1_DMABase_CR1, TIM1_DMABase_CR2, TIM1_DMABase_SMCR,\r
+* TIM1_DMABase_DIER, TIM1_DMABase_SR, TIM1_DMABase_EGR,\r
+* TIM1_DMABase_CCMR1, TIM1_DMABase_CCMR2, TIM1_DMABase_CCER,\r
+* TIM1_DMABase_CNT, TIM1_DMABase_PSC, TIM1_DMABase_ARR,\r
+* TIM1_DMABase_RCR, TIM1_DMABase_CCR1, TIM1_DMABase_CCR2,\r
+* TIM1_DMABase_CCR3, TIM1_DMABase_CCR4, TIM1_DMABase_BDTR,\r
+* TIM1_DMABase_DCR.\r
+* - TIM1_DMABurstLength: DMA Burst length.\r
+* This parameter can be one value between:\r
+* TIM1_DMABurstLength_1Byte and TIM1_DMABurstLength_18Bytes.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_DMAConfig(u16 TIM1_DMABase, u16 TIM1_DMABurstLength)\r
+{\r
+ u32 tmpdcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_DMA_BASE(TIM1_DMABase));\r
+ assert(IS_TIM1_DMA_LENGTH(TIM1_DMABurstLength));\r
+\r
+ tmpdcr = TIM1->DCR;\r
+\r
+ /* Reset the DBA and the DBL Bits */\r
+ tmpdcr &= DCR_DMA_Mask;\r
+\r
+ /* Set the DMA Base and the DMA Burst Length */\r
+ tmpdcr |= TIM1_DMABase | TIM1_DMABurstLength;\r
+\r
+ TIM1->DCR = (u16)tmpdcr;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_DMACmd\r
+* Description : Enables or disables the TIM1\92s DMA Requests.\r
+* Input : - TIM1_DMASources: specifies the DMA Request sources.\r
+* This parameter can be any combination of the following values:\r
+* - TIM1_DMA_Update: TIM1 update Interrupt source\r
+* - TIM1_DMA_CC1: TIM1 Capture Compare 1 DMA source\r
+* - TIM1_DMA_CC2: TIM1 Capture Compare 2 DMA source\r
+* - TIM1_DMA_CC3: TIM1 Capture Compare 3 DMA source\r
+* - TIM1_DMA_CC4: TIM1 Capture Compare 4 DMA source\r
+* - TIM1_DMA_COM: TIM1 Capture Compare Update DMA\r
+* source\r
+* - TIM1_DMA_Trigger: TIM1 Trigger DMA source\r
+* - Newstate: new state of the DMA Request sources.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_DMACmd(u16 TIM1_DMASource, FunctionalState Newstate)\r
+{\r
+ u32 tmpdier = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_DMA_SOURCE(TIM1_DMASource));\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ tmpdier = TIM1->DIER;\r
+\r
+ if (Newstate == ENABLE)\r
+ {\r
+ /* Enable the DMA sources */\r
+ tmpdier |= TIM1_DMASource;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA sources */\r
+ tmpdier &= (u16)~TIM1_DMASource;\r
+ }\r
+ TIM1->DIER = (u16)tmpdier;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_InternalClockConfig\r
+* Description : Configures the TIM1 interrnal Clock\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_InternalClockConfig(void)\r
+{\r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIM1->SMCR &= SMCR_SMS_Mask;\r
+}\r
+/*******************************************************************************\r
+* Function Name : TIM1_ETRClockMode1Config\r
+* Description : Configures the TIM1 External clock Mode1\r
+* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.\r
+* It can be one of the following values:\r
+* - TIM1_ExtTRGPSC_OFF\r
+* - TIM1_ExtTRGPSC_DIV2\r
+* - TIM1_ExtTRGPSC_DIV4\r
+* - TIM1_ExtTRGPSC_DIV8.\r
+* - TIM1_ExtTRGPolarity: The external Trigger Polarity.\r
+* It can be one of the following values:\r
+* - TIM1_ExtTRGPolarity_Inverted\r
+* - TIM1_ExtTRGPolarity_NonInverted\r
+* - ExtTRGFilter: External Trigger Filter.\r
+* This parameter must be a value between 0x00 and 0x0F\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ETRClockMode1Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,\r
+ u16 ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));\r
+ assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));\r
+\r
+ /* Configure the ETR Clock source */\r
+ ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);\r
+\r
+ /* Select the External clock mode1 */\r
+ TIM1->SMCR &= SMCR_SMS_Mask;\r
+ TIM1->SMCR |= TIM1_SlaveMode_External1;\r
+ \r
+ /* Select the Trigger selection : ETRF */\r
+ TIM1->SMCR &= SMCR_TS_Mask;\r
+ TIM1->SMCR |= TIM1_TS_ETRF;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ETRClockMode2Config\r
+* Description : Configures the TIM1 External clock Mode2\r
+* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.\r
+* It can be one of the following values:\r
+* - TIM1_ExtTRGPSC_OFF\r
+* - TIM1_ExtTRGPSC_DIV2\r
+* - TIM1_ExtTRGPSC_DIV4\r
+* - TIM1_ExtTRGPSC_DIV8\r
+* - TIM1_ExtTRGPolarity: The external Trigger Polarity.\r
+* It can be one of the following values:\r
+* - TIM1_ExtTRGPolarity_Inverted\r
+* - TIM1_ExtTRGPolarity_NonInverted\r
+* - ExtTRGFilter: External Trigger Filter.\r
+* This parameter must be a value between 0x00 and 0x0F\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ETRClockMode2Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,\r
+ u16 ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));\r
+ assert(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));\r
+\r
+ /* Configure the ETR Clock source */\r
+ ETR_Config(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);\r
+\r
+ /* Enable the External clock mode2 */\r
+ *(vu32 *) SMCR_ECE_BB = SMCR_ECE_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ITRxExternalClockConfig\r
+* Description : Configures the TIM1 Internal Trigger as External Clock\r
+* Input : - TIM1_ITRSource: Internal Trigger source.\r
+* This parameter can be one of the following values:\r
+* - TIM1_TS_ITR0: Internal Trigger 0\r
+* - TIM1_TS_ITR1: Internal Trigger 1\r
+* - TIM1_TS_ITR2: Internal Trigger 2\r
+* - TIM1_TS_ITR3: Internal Trigger 3\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ITRxExternalClockConfig(u16 TIM1_InputTriggerSource)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_INTERNAL_TRIGGER_SELECTION(TIM1_InputTriggerSource));\r
+ \r
+ /* Select the Internal Trigger */\r
+ TIM1_SelectInputTrigger(TIM1_InputTriggerSource);\r
+\r
+ /* Select the External clock mode1 */\r
+ TIM1->SMCR |= TIM1_SlaveMode_External1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_TIxExternalClockConfig\r
+* Description : Configures the TIM1 Trigger as External Clock\r
+* Input : - TIM1_TIxExternalCLKSource: Trigger source.\r
+* This parameter can be one of the following values:\r
+* - TIM1_TS_TI1F_ED: TI1 Edge Detector\r
+* - TIM1_TS_TI1FP1: Filtered TIM1 Input 1\r
+* - TIM1_TS_TI2FP2: Filtered TIM1 Input 2\r
+* - TIM1_ICPolarity: specifies the TIx Polarity.\r
+* This parameter can be:\r
+* - TIM1_ICPolarity_Rising\r
+* - TIM1_ICPolarity_Falling\r
+* - ICFilter : specifies the filter value.\r
+* This parameter must be a value between 0x0 and 0xF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_TIxExternalClockConfig(u16 TIM1_TIxExternalCLKSource,\r
+ u16 TIM1_ICPolarity, u8 ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_TIX_TRIGGER_SELECTION(TIM1_TIxExternalCLKSource));\r
+ assert(IS_TIM1_IC_POLARITY(TIM1_ICPolarity));\r
+ assert(IS_TIM1_IC_FILTER(ICFilter));\r
+\r
+ /* Configure the TIM1 Input Clock Source */\r
+ if (TIM1_TIxExternalCLKSource == TIM1_TIxExternalCLK1Source_TI2)\r
+ {\r
+ TI2_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ else\r
+ {\r
+ TI1_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);\r
+ }\r
+\r
+ /* Select the Trigger source */\r
+ TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource);\r
+\r
+ /* Select the External clock mode1 */\r
+ TIM1->SMCR |= TIM1_SlaveMode_External1;\r
+}\r
+/*******************************************************************************\r
+* Function Name : TIM1_SelectInputTrigger\r
+* Description : Selects the TIM1 Input Trigger source\r
+* Input : - TIM1_InputTriggerSource: The Trigger source.\r
+* This parameter can be one of the following values:\r
+* - TIM1_TS_ITR0: Internal Trigger 0\r
+* - TIM1_TS_ITR1: Internal Trigger 1\r
+* - TIM1_TS_ITR2: Internal Trigger 2\r
+* - TIM1_TS_ITR3: Internal Trigger 3\r
+* - TIM1_TS_TI1F_ED: TI1 Edge Detector\r
+* - TIM1_TS_TI1FP1: Filtered Timer Input 1\r
+* - TIM1_TS_TI2FP2: Filtered Timer Input 2\r
+* - TIM1_TS_ETRF: External Trigger input\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SelectInputTrigger(u16 TIM1_InputTriggerSource)\r
+{\r
+ u32 tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_TRIGGER_SELECTION(TIM1_InputTriggerSource));\r
+\r
+ tmpsmcr = TIM1->SMCR;\r
+\r
+ /* Select the Tgigger Source */\r
+ tmpsmcr &= SMCR_TS_Mask;\r
+ tmpsmcr |= TIM1_InputTriggerSource;\r
+\r
+ TIM1->SMCR = (u16)tmpsmcr;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_UpdateDisableConfig\r
+* Description : Enables or Disables the TIM1 Update event.\r
+* Input : - Newstate: new state of the TIM1 peripheral Preload register\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_UpdateDisableConfig(FunctionalState Newstate)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ /* Set or Reset the UDIS Bit */\r
+ *(vu32 *) CR1_UDIS_BB = (u16)Newstate;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_UpdateRequestConfig\r
+* Description : Selects the TIM1 Update Request Interrupt source.\r
+* Input : - TIM1_UpdateSource: specifies the Update source.\r
+* This parameter can be one of the following values:\r
+* - TIM1_UpdateSource_Regular\r
+* - TIM1_UpdateSource_Global\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_UpdateRequestConfig(u8 TIM1_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_UPDATE_SOURCE(TIM1_UpdateSource));\r
+\r
+ /* Set or Reset the URS Bit */\r
+ *(vu32 *) CR1_URS_BB = TIM1_UpdateSource;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SelectHallSensor\r
+* Description : Enables or disables the TIM1\92s Hall sensor interface.\r
+* Input : - Newstate: new state of the TIM1 Hall sensor interface\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SelectHallSensor(FunctionalState Newstate)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ /* Set or Reset the TI1S Bit */\r
+ *(vu32 *) CR2_TI1S_BB = (u16)Newstate;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SelectOPM\r
+* Description : Enables or disables the TIM1\92s One Pulse Mode.\r
+* Input : - TIM1_OPMode: specifies the OPM Mode to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM1_OPMode_Single\r
+* - TIM1_OPMode_Repetitive\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SelectOnePulseMode(u16 TIM1_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OPM_MODE(TIM1_OPMode));\r
+\r
+ /* Set or Reset the OPM Bit */\r
+ *(vu32 *) CR1_OPM_BB = TIM1_OPMode;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SelectOutputTrigger\r
+* Description : Selects the TIM1 Trigger Output Mode.\r
+* Input : - TIM1_TRGOSource: specifies the Trigger Output source.\r
+* This paramter can be one of the following values:\r
+* - TIM1_TRGOSource_Reset\r
+* - TIM1_TRGOSource_Enable\r
+* - TIM1_TRGOSource_Update\r
+* - TIM1_TRGOSource_OC1\r
+* - TIM1_TRGOSource_OC1Ref\r
+* - TIM1_TRGOSource_OC2Ref\r
+* - TIM1_TRGOSource_OC3Ref\r
+* - TIM1_TRGOSource_OC4Ref\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SelectOutputTrigger(u16 TIM1_TRGOSource)\r
+{\r
+ u32 tmpcr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_TRGO_SOURCE(TIM1_TRGOSource));\r
+\r
+ tmpcr2 = TIM1->CR2;\r
+\r
+ /* Reset the MMS Bits */\r
+ tmpcr2 &= CR2_MMS_Mask;\r
+\r
+ /* Select the TRGO source */\r
+ tmpcr2 |= TIM1_TRGOSource;\r
+\r
+ TIM1->CR2 = (u16)tmpcr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SelectSlaveMode\r
+* Description : Selects the TIM1 Slave Mode.\r
+* Input : - TIM1_SlaveMode: specifies the TIM1 Slave Mode.\r
+* This paramter can be one of the following values:\r
+* - TIM1_SlaveMode_Reset\r
+* - TIM1_SlaveMode_Gated\r
+* - TIM1_SlaveMode_Trigger\r
+* - TIM1_SlaveMode_External1\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SelectSlaveMode(u16 TIM1_SlaveMode)\r
+{\r
+ u32 tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_SLAVE_MODE(TIM1_SlaveMode));\r
+\r
+ tmpsmcr = TIM1->SMCR;\r
+\r
+ /* Reset the SMS Bits */\r
+ tmpsmcr &= SMCR_SMS_Mask;\r
+\r
+ /* Select the Slave Mode */\r
+ tmpsmcr |= TIM1_SlaveMode;\r
+\r
+ TIM1->SMCR = (u16)tmpsmcr;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SelectMasterSlaveMode\r
+* Description : Sets or Resets the TIM1 Master/Slave Mode.\r
+* Input : - TIM1_MasterSlaveMode: specifies the TIM1 Master Slave Mode.\r
+* This paramter can be one of the following values:\r
+* - TIM1_MasterSlaveMode_Enable: synchronization between\r
+* the current timer and its slaves (through TRGO).\r
+* - TIM1_MasterSlaveMode_Disable: No action\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SelectMasterSlaveMode(u16 TIM1_MasterSlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_MSM_STATE(TIM1_MasterSlaveMode));\r
+\r
+ /* Set or Reset the MSM Bit */\r
+ *(vu32 *) SMCR_MSM_BB = TIM1_MasterSlaveMode;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_EncoderInterfaceConfig\r
+* Description : Configures the TIM1 Encoder Interface.\r
+* Input : - TIM1_EncoderMode: specifies the TIM1 Encoder Mode.\r
+* This parameter can be one of the following values:\r
+* - TIM1_EncoderMode_TI1: Counter counts on TI1FP1 edge\r
+* depending on TI2FP2 level.\r
+* - TIM1_EncoderMode_TI2: Counter counts on TI2FP2 edge\r
+* depending on TI1FP1 level.\r
+* - TIM1_EncoderMode_TI12: Counter counts on both TI1FP1 and\r
+* TI2FP2 edges depending on the level of the other input.\r
+* - TIM1_IC1Polarity: specifies the IC1 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM1_ICPolarity_Falling\r
+* - TIM1_ICPolarity_Rising\r
+* - TIM1_IC2Polarity: specifies the IC2 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM1_ICPolarity_Falling\r
+* - TIM1_ICPolarity_Rising\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_EncoderInterfaceConfig(u16 TIM1_EncoderMode, u16 TIM1_IC1Polarity,\r
+ u16 TIM1_IC2Polarity)\r
+{\r
+ u32 tmpsmcr = 0;\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_ENCODER_MODE(TIM1_EncoderMode));\r
+ assert(IS_TIM1_IC_POLARITY(TIM1_IC1Polarity));\r
+ assert(IS_TIM1_IC_POLARITY(TIM1_IC2Polarity));\r
+\r
+ tmpsmcr = TIM1->SMCR;\r
+ tmpccmr1 = TIM1->CCMR1;\r
+\r
+ /* Set the encoder Mode */\r
+ tmpsmcr &= SMCR_SMS_Mask;\r
+ tmpsmcr |= TIM1_EncoderMode;\r
+\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;\r
+ tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;\r
+\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ *(vu32 *) CCER_CC1P_BB = TIM1_IC1Polarity;\r
+ *(vu32 *) CCER_CC2P_BB = TIM1_IC2Polarity;\r
+\r
+ TIM1->SMCR = (u16)tmpsmcr;\r
+\r
+ TIM1->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_PrescalerConfig\r
+* Description : Configures the TIM1 Prescaler.\r
+* Input : - Prescaler: specifies the Prescaler Register value\r
+* - TIM1_PSCReloadMode: specifies the TIM1 Prescaler Reload mode.\r
+* This parmeter can be one of the following values:\r
+* - TIM1_PSCReloadMode_Update: The Prescaler is loaded at\r
+* the update event.\r
+* - TIM1_PSCReloadMode_Immediate: The Prescaler is loaded\r
+* immediatly.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_PrescalerConfig(u16 Prescaler, u16 TIM1_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_PRESCALER_RELOAD(TIM1_PSCReloadMode));\r
+\r
+ /* Set the Prescaler value */\r
+ TIM1->PSC = Prescaler;\r
+\r
+ /* Set or reset the UG Bit */\r
+ *(vu32 *) EGR_UG_BB = TIM1_PSCReloadMode;\r
+}\r
+/*******************************************************************************\r
+* Function Name : TIM1_CounterModeConfig\r
+* Description : Specifies the TIM1 Counter Mode to be used.\r
+* Input : - TIM1_CounterMode: specifies the Counter Mode to be used\r
+* This parameter can be one of the following values:\r
+* - TIM1_CounterMode_Up: TIM1 Up Counting Mode\r
+* - TIM1_CounterMode_Down: TIM1 Down Counting Mode\r
+* - TIM1_CounterMode_CenterAligned1: TIM1 Center Aligned Mode1\r
+* - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2\r
+* - TIM1_CounterMode_CenterAligned3: TIM1 Center Aligned Mode3\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_CounterModeConfig(u16 TIM1_CounterMode)\r
+{\r
+ u32 tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_COUNTER_MODE(TIM1_CounterMode));\r
+\r
+ tmpcr1 = TIM1->CR1;\r
+\r
+ /* Reset the CMS and DIR Bits */\r
+ tmpcr1 &= CR1_CounterMode_Mask;\r
+\r
+ /* Set the Counter Mode */\r
+ tmpcr1 |= TIM1_CounterMode;\r
+\r
+ TIM1->CR1 = (u16)tmpcr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ForcedOC1Config\r
+* Description : Forces the TIM1 Channel1 output waveform to active or inactive \r
+* level.\r
+* Input : - TIM1_ForcedAction: specifies the forced Action to be set to\r
+* the output waveform.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ForcedAction_Active: Force active level on OC1REF\r
+* - TIM1_ForcedAction_InActive: Force inactive level on\r
+* OC1REF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ForcedOC1Config(u16 TIM1_ForcedAction)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));\r
+\r
+ tmpccmr1 = TIM1->CCMR1;\r
+\r
+ /* Reset the OCM Bits */\r
+ tmpccmr1 &= CCMR_OCM13_Mask;\r
+\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= TIM1_ForcedAction;\r
+\r
+ TIM1->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ForcedOC2Config\r
+* Description : Forces the TIM1 Channel2 output waveform to active or inactive \r
+* level.\r
+* Input : - TIM1_ForcedAction: specifies the forced Action to be set to\r
+* the output waveform.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ForcedAction_Active: Force active level on OC2REF\r
+* - TIM1_ForcedAction_InActive: Force inactive level on\r
+* OC2REF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ForcedOC2Config(u16 TIM1_ForcedAction)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));\r
+\r
+ tmpccmr1 = TIM1->CCMR1;\r
+\r
+ /* Reset the OCM Bits */\r
+ tmpccmr1 &= CCMR_OCM24_Mask;\r
+\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= (u32)TIM1_ForcedAction << 8;\r
+\r
+ TIM1->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ForcedOC3Config\r
+* Description : Forces the TIM1 Channel3 output waveform to active or inactive \r
+* level.\r
+* Input : - TIM1_ForcedAction: specifies the forced Action to be set to\r
+* the output waveform.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ForcedAction_Active: Force active level on OC3REF\r
+* - TIM1_ForcedAction_InActive: Force inactive level on\r
+* OC3REF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ForcedOC3Config(u16 TIM1_ForcedAction)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));\r
+\r
+ tmpccmr2 = TIM1->CCMR2;\r
+\r
+ /* Reset the OCM Bits */\r
+ tmpccmr2 &= CCMR_OCM13_Mask;\r
+\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= TIM1_ForcedAction;\r
+\r
+ TIM1->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ForcedOC4Config\r
+* Description : Forces the TIM1 Channel4 output waveform to active or inactive \r
+* level.\r
+* Input : - TIM1_ForcedAction: specifies the forced Action to be set to\r
+* the output waveform.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ForcedAction_Active: Force active level on OC4REF\r
+* - TIM1_ForcedAction_InActive: Force inactive level on\r
+* OC4REF.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ForcedOC4Config(u16 TIM1_ForcedAction)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));\r
+\r
+ tmpccmr2 = TIM1->CCMR1;\r
+\r
+ /* Reset the OCM Bits */\r
+ tmpccmr2 &= CCMR_OCM24_Mask;\r
+\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= (u16)((u16)TIM1_ForcedAction << 8);\r
+\r
+ TIM1->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ARRPreloadConfig\r
+* Description : Enables or disables TIM1 peripheral Preload register on ARR.\r
+* Input : - Newstate: new state of the TIM1 peripheral Preload register\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ARRPreloadConfig(FunctionalState Newstate)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ /* Set or Reset the ARPE Bit */\r
+ *(vu32 *) CR1_ARPE_BB = (u16)Newstate;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SelectCOM\r
+* Description : Selects the TIM1 peripheral Commutation event.\r
+* Input : - Newstate: new state of the Commutation event.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SelectCOM(FunctionalState Newstate)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ /* Set or Reset the CCUS Bit */\r
+ *(vu32 *) CR2_CCUS_BB = (u16)Newstate;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SelectCCDMA\r
+* Description : Selects the TIM1 peripheral Capture Compare DMA source.\r
+* Input : - Newstate: new state of the Capture Compare DMA source\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SelectCCDMA(FunctionalState Newstate)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ /* Set or Reset the CCDS Bit */\r
+ *(vu32 *) CR2_CCDS_BB = (u16)Newstate;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_CCPreloadControl\r
+* Description : Sets or Resets the TIM1 peripheral Capture Compare Preload \r
+* Control bit.\r
+* Input : - Newstate: new state of the Capture Compare Preload Control bit\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_CCPreloadControl(FunctionalState Newstate)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ /* Set or Reset the CCPC Bit */\r
+ *(vu32 *) CR2_CCPC_BB = (u16)Newstate;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC1PreloadConfig\r
+* Description : Enables or disables the TIM1 peripheral Preload Register on CCR1.\r
+* Input : - TIM1_OCPreload: new state of the Capture Compare Preload\r
+* register.\r
+* This parameter can be one of the following values:\r
+* - TIM1_OCPreload_Enable\r
+* - TIM1_OCPreload_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC1PreloadConfig(u16 TIM1_OCPreload)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));\r
+\r
+ /* Set or Reset the OC1PE Bit */\r
+ *(vu32 *) CCMR1_OC1PE_BB = (u16)TIM1_OCPreload;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC2PreloadConfig\r
+* Description : Enables or disables the TIM1 peripheral Preload Register on CCR2.\r
+* Input : - TIM1_OCPreload: new state of the Capture Compare Preload\r
+* register.\r
+* This parameter can be one of the following values:\r
+* - TIM1_OCPreload_Enable\r
+* - TIM1_OCPreload_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC2PreloadConfig(u16 TIM1_OCPreload)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));\r
+\r
+ /* Set or Reset the OC2PE Bit */\r
+ *(vu32 *) CCMR1_OC2PE_BB = (u16)TIM1_OCPreload;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC3PreloadConfig\r
+* Description : Enables or disables the TIM1 peripheral Preload Register on CCR3.\r
+* Input : - TIM1_OCPreload: new state of the Capture Compare Preload\r
+* register.\r
+* This parameter can be one of the following values:\r
+* - TIM1_OCPreload_Enable\r
+* - TIM1_OCPreload_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC3PreloadConfig(u16 TIM1_OCPreload)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));\r
+\r
+ /* Set or Reset the OC3PE Bit */\r
+ *(vu32 *) CCMR2_OC3PE_BB = (u16)TIM1_OCPreload;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC4PreloadConfig\r
+* Description : Enables or disables the TIM1 peripheral Preload Register on CCR4.\r
+* Input : - TIM1_OCPreload: new state of the Capture Compare Preload\r
+* register.\r
+* This parameter can be one of the following values:\r
+* - TIM1_OCPreload_Enable\r
+* - TIM1_OCPreload_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC4PreloadConfig(u16 TIM1_OCPreload)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OCPRELOAD_STATE(TIM1_OCPreload));\r
+\r
+ /* Set or Reset the OC4PE Bit */\r
+ *(vu32 *) CCMR2_OC4PE_BB = (u16)TIM1_OCPreload;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC1FastConfig\r
+* Description : Configures the TIM1 Capture Compare 1 Fast feature.\r
+* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.\r
+* This parameter can be one of the following values:\r
+* - TIM1_OCFast_Enable\r
+* - TIM1_OCFast_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC1FastConfig(u16 TIM1_OCFast)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));\r
+\r
+ /* Set or Reset the OC1FE Bit */\r
+ *(vu32 *) CCMR1_OC1FE_BB = (u16)TIM1_OCFast;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC2FastConfig\r
+* Description : Configures the TIM1 Capture Compare Fast feature.\r
+* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.\r
+* This parameter can be one of the following values:\r
+* - TIM1_OCFast_Enable\r
+* - TIM1_OCFast_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC2FastConfig(u16 TIM1_OCFast)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));\r
+\r
+ /* Set or Reset the OC2FE Bit */\r
+ *(vu32 *) CCMR1_OC2FE_BB = (u16)TIM1_OCFast;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC3FastConfig\r
+* Description : Configures the TIM1 Capture Compare Fast feature.\r
+* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.\r
+* This parameter can be one of the following values:\r
+* - TIM1_OCFast_Enable\r
+* - TIM1_OCFast_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC3FastConfig(u16 TIM1_OCFast)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));\r
+\r
+ /* Set or Reset the OC3FE Bit */\r
+ *(vu32 *) CCMR2_OC3FE_BB = (u16)TIM1_OCFast;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC4FastConfig\r
+* Description : Configures the TIM1 Capture Compare Fast feature.\r
+* Input : - TIM1_OCFast: new state of the Output Compare Fast Enable bit.\r
+* This parameter can be one of the following values:\r
+* - TIM1_OCFast_Enable\r
+* - TIM1_OCFast_Disable\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC4FastConfig(u16 TIM1_OCFast)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OCFAST_STATE(TIM1_OCFast));\r
+\r
+ /* Set or Reset the OC4FE Bit */\r
+ *(vu32 *) CCMR2_OC4FE_BB = (u16)TIM1_OCFast;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_GenerateEvent\r
+* Description : Configures the TIM1 event to be generate by software.\r
+* Input : - TIM1_EventSource: specifies the event source.\r
+* This parameter can be one or more of the following values:\r
+* - TIM1_EventSource_Update: TIM1 update Event source\r
+* - TIM1_EventSource_CC1: TIM1 Capture Compare 1 Event source\r
+* - TIM1_EventSource_CC2: TIM1 Capture Compare 2 Event source\r
+* - TIM1_EventSource_CC3: TIM1 Capture Compare 3 Event source\r
+* - TIM1_EventSource_CC4: TIM1 Capture Compare 4 Event source\r
+* - TIM1_EventSource_COM: TIM1 COM Event source\r
+* - TIM1_EventSource_Trigger: TIM1 Trigger Event source\r
+* - TIM1_EventSourceBreak: TIM1 Break Event source\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_GenerateEvent(u16 TIM1_EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_EVENT_SOURCE(TIM1_EventSource));\r
+\r
+ /* Set the event sources */\r
+ TIM1->EGR |= TIM1_EventSource;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC1PolarityConfig\r
+* Description : Configures the TIM1 Channel 1 polarity.\r
+* Input : - TIM1_OCPolarity: specifies the OC1 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM1_OCPolarity_High: Output Compare active high\r
+* - TIM1_OCPolarity_Low: Output Compare active low\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC1PolarityConfig(u16 TIM1_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));\r
+\r
+ /* Set or Reset the CC1P Bit */\r
+ *(vu32 *) CCER_CC1P_BB = (u16)TIM1_OCPolarity;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC1NPolarityConfig\r
+* Description : Configures the TIM1 Channel 1N polarity.\r
+* Input : - TIM1_OCPolarity: specifies the OC1N Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM1_OCPolarity_High: Output Compare active high\r
+* - TIM1_OCPolarity_Low: Output Compare active low\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC1NPolarityConfig(u16 TIM1_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));\r
+\r
+ /* Set or Reset the CC3P Bit */\r
+ *(vu32 *) CCER_CC1NP_BB = (u16)TIM1_OCPolarity;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC2PolarityConfig\r
+* Description : Configures the TIM1 Channel 2 polarity.\r
+* Input : - TIM1_OCPolarity: specifies the OC2 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM1_OCPolarity_High: Output Compare active high\r
+* - TIM1_OCPolarity_Low: Output Compare active low\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC2PolarityConfig(u16 TIM1_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));\r
+\r
+ /* Set or Reset the CC2P Bit */\r
+ *(vu32 *) CCER_CC2P_BB = (u16)TIM1_OCPolarity;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC2NPolarityConfig\r
+* Description : Configures the TIM1 Channel 2N polarity.\r
+* Input : - TIM1_OCPolarity: specifies the OC2N Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM1_OCPolarity_High: Output Compare active high\r
+* - TIM1_OCPolarity_Low: Output Compare active low\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC2NPolarityConfig(u16 TIM1_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));\r
+\r
+ /* Set or Reset the CC3P Bit */\r
+ *(vu32 *) CCER_CC2NP_BB = (u16)TIM1_OCPolarity;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC3PolarityConfig\r
+* Description : Configures the TIM1 Channel 3 polarity.\r
+* Input : - TIM1_OCPolarity: specifies the OC3 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM1_OCPolarity_High: Output Compare active high\r
+* - TIM1_OCPolarity_Low: Output Compare active low\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC3PolarityConfig(u16 TIM1_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));\r
+\r
+ /* Set or Reset the CC3P Bit */\r
+ *(vu32 *) CCER_CC3P_BB = (u16)TIM1_OCPolarity;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC3NPolarityConfig\r
+* Description : Configures the TIM1 Channel 3N polarity.\r
+* Input : - TIM1_OCPolarity: specifies the OC3N Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM1_OCPolarity_High: Output Compare active high\r
+* - TIM1_OCPolarity_Low: Output Compare active low\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC3NPolarityConfig(u16 TIM1_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));\r
+\r
+ /* Set or Reset the CC3P Bit */\r
+ *(vu32 *) CCER_CC3NP_BB = (u16)TIM1_OCPolarity;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_OC4PolarityConfig\r
+* Description : Configures the TIM1 Channel 4 polarity.\r
+* Input : - TIM1_OCPolarity: specifies the OC4 Polarity\r
+* This parmeter can be one of the following values:\r
+* - TIM1_OCPolarity_High: Output Compare active high\r
+* - TIM1_OCPolarity_Low: Output Compare active low\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_OC4PolarityConfig(u16 TIM1_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));\r
+\r
+ /* Set or Reset the CC4P Bit */\r
+ *(vu32 *) CCER_CC4P_BB = (u16)TIM1_OCPolarity;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_CCxCmd\r
+* Description : Enables or disables the TIM1 Capture Compare Channel x.\r
+* Input : - TIM1_Channel: specifies the TIM1 Channel\r
+* This parmeter can be one of the following values:\r
+* - TIM1_Channel1: TIM1 Channel1\r
+* - TIM1_Channel2: TIM1 Channel2\r
+* - TIM1_Channel3: TIM1 Channel3\r
+* - TIM1_Channel4: TIM1 Channel4\r
+* - Newstate: specifies the TIM1 Channel CCxE bit new state.\r
+* This parameter can be: ENABLE or DISABLE. \r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_CCxCmd(u16 TIM1_Channel, FunctionalState Newstate)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_CHANNEL(TIM1_Channel));\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ if(TIM1_Channel == TIM1_Channel_1)\r
+ {\r
+ /* Set or Reset the CC1E Bit */\r
+ *(vu32 *) CCER_CC1E_BB = (u16)Newstate; \r
+ }\r
+ else if(TIM1_Channel == TIM1_Channel_2)\r
+ {\r
+ /* Set or Reset the CC2E Bit */\r
+ *(vu32 *) CCER_CC2E_BB = (u16)Newstate;\r
+ }\r
+ else if(TIM1_Channel == TIM1_Channel_3)\r
+ {\r
+ /* Set or Reset the CC3E Bit */\r
+ *(vu32 *) CCER_CC3E_BB = (u16)Newstate;\r
+ }\r
+ else\r
+ {\r
+ /* Set or Reset the CC4E Bit */\r
+ *(vu32 *) CCER_CC4E_BB = (u16)Newstate;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_CCxNCmd\r
+* Description : Enables or disables the TIM1 Capture Compare Channel xN.\r
+* Input : - TIM1_Channel: specifies the TIM1 Channel\r
+* This parmeter can be one of the following values:\r
+* - TIM1_Channel1: TIM1 Channel1\r
+* - TIM1_Channel2: TIM1 Channel2\r
+* - TIM1_Channel3: TIM1 Channel3\r
+* - Newstate: specifies the TIM1 Channel CCxNE bit new state.\r
+* This parameter can be: ENABLE or DISABLE. \r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_CCxNCmd(u16 TIM1_Channel, FunctionalState Newstate)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_COMPLEMENTARY_CHANNEL(TIM1_Channel));\r
+ assert(IS_FUNCTIONAL_STATE(Newstate));\r
+\r
+ if(TIM1_Channel == TIM1_Channel_1)\r
+ {\r
+ /* Set or Reset the CC1NE Bit */\r
+ *(vu32 *) CCER_CC1NE_BB = (u16)Newstate; \r
+ }\r
+ else if(TIM1_Channel == TIM1_Channel_2)\r
+ {\r
+ /* Set or Reset the CC2NE Bit */\r
+ *(vu32 *) CCER_CC2NE_BB = (u16)Newstate;\r
+ }\r
+ else \r
+ {\r
+ /* Set or Reset the CC3NE Bit */\r
+ *(vu32 *) CCER_CC3NE_BB = (u16)Newstate;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SelectOCxM\r
+* Description : Selects the TIM1 Ouput Compare Mode.\r
+* This function disables the selected channel before changing \r
+* the Ouput Compare Mode. User has to enable this channel using\r
+* TIM1_CCxCmd and TIM1_CCxNCmd functions.\r
+* Input : - TIM1_Channel: specifies the TIM1 Channel\r
+* This parmeter can be one of the following values:\r
+* - TIM1_Channel1: TIM1 Channel1\r
+* - TIM1_Channel2: TIM1 Channel2\r
+* - TIM1_Channel3: TIM1 Channel3\r
+* - TIM1_Channel4: TIM1 Channel4\r
+* - TIM1_OCMode: specifies the TIM1 Output Compare Mode.\r
+* This paramter can be one of the following values:\r
+* - TIM1_OCMode_Timing\r
+* - TIM1_OCMode_Active\r
+* - TIM1_OCMode_Toggle\r
+* - TIM1_OCMode_PWM1\r
+* - TIM1_OCMode_PWM2\r
+* - TIM1_ForcedAction_Active\r
+* - TIM1_ForcedAction_InActive\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SelectOCxM(u16 TIM1_Channel, u16 TIM1_OCMode)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_CHANNEL(TIM1_Channel));\r
+ assert(IS_TIM1_OCM(TIM1_OCMode));\r
+\r
+ if(TIM1_Channel == TIM1_Channel_1)\r
+ {\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;\r
+\r
+ /* Reset the Output Compare Bits */\r
+ TIM1->CCMR1 &= OC13Mode_Mask;\r
+\r
+ /* Set the Ouput Compare Mode */\r
+ TIM1->CCMR1 |= TIM1_OCMode;\r
+ }\r
+ else if(TIM1_Channel == TIM1_Channel_2)\r
+ {\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;\r
+\r
+ /* Reset the Output Compare Bits */\r
+ TIM1->CCMR1 &= OC24Mode_Mask;\r
+\r
+ /* Set the Ouput Compare Mode */\r
+ TIM1->CCMR1 |= (u16)((u16)TIM1_OCMode << 8);\r
+ }\r
+ else if(TIM1_Channel == TIM1_Channel_3)\r
+ {\r
+ /* Disable the Channel 3: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;\r
+\r
+ /* Reset the Output Compare Bits */\r
+ TIM1->CCMR2 &= OC13Mode_Mask;\r
+\r
+ /* Set the Ouput Compare Mode */\r
+ TIM1->CCMR2 |= TIM1_OCMode;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Channel 4: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;\r
+\r
+ /* Reset the Output Compare Bits */\r
+ TIM1->CCMR2 &= OC24Mode_Mask;\r
+\r
+ /* Set the Ouput Compare Mode */\r
+ TIM1->CCMR2 |= (u16)((u16)TIM1_OCMode << 8);\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SetAutoreload\r
+* Description : Sets the TIM1 Autoreload Register value.\r
+* Input : - Autoreload: specifies the Autoreload register new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SetAutoreload(u16 Autoreload)\r
+{\r
+ /* Set the Autoreload Register value */\r
+ TIM1->ARR = Autoreload;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SetCompare1\r
+* Description : Sets the TIM1 Capture Compare1 Register value.\r
+* Input : - Compare1: specifies the Capture Compare1 register new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SetCompare1(u16 Compare1)\r
+{\r
+ /* Set the Capture Compare1 Register value */\r
+ TIM1->CCR1 = Compare1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SetCompare2\r
+* Description : Sets the TIM1 Capture Compare2 Register value.\r
+* Input : - Compare2: specifies the Capture Compare2 register new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SetCompare2(u16 Compare2)\r
+{\r
+ /* Set the Capture Compare2 Register value */\r
+ TIM1->CCR2 = Compare2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SetCompare3\r
+* Description : Sets the TIM1 Capture Compare3 Register value.\r
+* Input : - Compare3: specifies the Capture Compare3 register new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SetCompare3(u16 Compare3)\r
+{\r
+ /* Set the Capture Compare3 Register value */\r
+ TIM1->CCR3 = Compare3;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SetCompare4\r
+* Description : Sets the TIM1 Capture Compare4 Register value.\r
+* Input : - Compare4: specifies the Capture Compare4 register new value.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SetCompare4(u16 Compare4)\r
+{\r
+ /* Set the Capture Compare4 Register value */\r
+ TIM1->CCR4 = Compare4;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SetIC1Prescaler\r
+* Description : Sets the TIM1 Input Capture 1 prescaler.\r
+* Input : - TIM1_IC1Prescaler: specifies the Input Capture prescaler\r
+* new value.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICPSC_DIV1: no prescaler\r
+* - TIM1_ICPSC_DIV2: capture is done once every 2 events\r
+* - TIM1_ICPSC_DIV4: capture is done once every 4 events\r
+* - TIM1_ICPSC_DIV8: capture is done once every 8 events\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SetIC1Prescaler(u16 TIM1_IC1Prescaler)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_TIM1_IC_PRESCALER(TIM1_IC1Prescaler));\r
+\r
+ tmpccmr1 = TIM1->CCMR1;\r
+\r
+ /* Reset the IC1PSC Bits */\r
+ tmpccmr1 &= CCMR_IC13PSC_Mask;\r
+\r
+ /* Set the IC1PSC value */\r
+ tmpccmr1 |= TIM1_IC1Prescaler;\r
+\r
+ TIM1->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SetIC2Prescaler\r
+* Description : Sets the TIM1 Input Capture 2 prescaler.\r
+* Input : - TIM1_IC2Prescaler: specifies the Input Capture prescaler\r
+* new value.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICPSC_DIV1: no prescaler\r
+* - TIM1_ICPSC_DIV2: capture is done once every 2 events\r
+* - TIM1_ICPSC_DIV4: capture is done once every 4 events\r
+* - TIM1_ICPSC_DIV8: capture is done once every 8 events\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SetIC2Prescaler(u16 TIM1_IC2Prescaler)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_IC_PRESCALER(TIM1_IC2Prescaler));\r
+\r
+ tmpccmr1 = TIM1->CCMR1;\r
+\r
+ /* Reset the IC2PSC Bits */\r
+ tmpccmr1 &= CCMR_IC24PSC_Mask;\r
+\r
+ /* Set the IC2PSC value */\r
+ tmpccmr1 |= (u16)((u16)TIM1_IC2Prescaler << 8);\r
+\r
+ TIM1->CCMR1 = (u16)tmpccmr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SetIC3Prescaler\r
+* Description : Sets the TIM1 Input Capture 3 prescaler.\r
+* Input : - TIM1_IC3Prescaler: specifies the Input Capture prescaler\r
+* new value.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICPSC_DIV1: no prescaler\r
+* - TIM1_ICPSC_DIV2: capture is done once every 2 events\r
+* - TIM1_ICPSC_DIV4: capture is done once every 4 events\r
+* - TIM1_ICPSC_DIV8: capture is done once every 8 events\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SetIC3Prescaler(u16 TIM1_IC3Prescaler)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_IC_PRESCALER(TIM1_IC3Prescaler));\r
+\r
+ tmpccmr2 = TIM1->CCMR2;\r
+\r
+ /* Reset the IC3PSC Bits */\r
+ tmpccmr2 &= CCMR_IC13PSC_Mask;\r
+\r
+ /* Set the IC3PSC value */\r
+ tmpccmr2 |= TIM1_IC3Prescaler;\r
+\r
+ TIM1->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SetIC4Prescaler\r
+* Description : Sets the TIM1 Input Capture 4 prescaler.\r
+* Input : - TIM1_IC4Prescaler: specifies the Input Capture prescaler\r
+* new value.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICPSC_DIV1: no prescaler\r
+* - TIM1_ICPSC_DIV2: capture is done once every 2 events\r
+* - TIM1_ICPSC_DIV4: capture is done once every 4 events\r
+* - TIM1_ICPSC_DIV8: capture is done once every 8 events\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SetIC4Prescaler(u16 TIM1_IC4Prescaler)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_IC_PRESCALER(TIM1_IC4Prescaler));\r
+\r
+ tmpccmr2 = TIM1->CCMR2;\r
+\r
+ /* Reset the IC4PSC Bits */\r
+ tmpccmr2 &= CCMR_IC24PSC_Mask;\r
+\r
+ /* Set the IC4PSC value */\r
+ tmpccmr2 |= (u16)((u16)TIM1_IC4Prescaler << 8);\r
+\r
+ TIM1->CCMR2 = (u16)tmpccmr2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_SetClockDivision\r
+* Description : Sets the TIM1 Clock Division value.\r
+* Input : - TIM1_CKD: specifies the clock division value.\r
+* This parameter can be one of the following value:\r
+* - TIM1_CKD_DIV1: TDTS = Tck_tim\r
+* - TIM1_CKD_DIV2: TDTS = 2*Tck_tim\r
+* - TIM1_CKD_DIV4: TDTS = 4*Tck_tim\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_SetClockDivision(u16 TIM1_CKD)\r
+{\r
+ u32 tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_CKD_DIV(TIM1_CKD));\r
+\r
+ tmpcr1 = TIM1->CR1;\r
+\r
+ /* Reset the CKD Bits */\r
+ tmpcr1 &= CR1_CKD_Mask;\r
+\r
+ /* Set the CKD value */\r
+ tmpcr1 |= TIM1_CKD;\r
+\r
+ TIM1->CR1 = (u16)tmpcr1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_GetCapture1\r
+* Description : Gets the TIM1 Input Capture 1 value.\r
+* Input : None\r
+* Output : None\r
+* Return : Capture Compare 1 Register value.\r
+*******************************************************************************/\r
+u16 TIM1_GetCapture1(void)\r
+{\r
+ /* Get the Capture 1 Register value */\r
+ return TIM1->CCR1;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_GetCapture2\r
+* Description : Gets the TIM1 Input Capture 2 value.\r
+* Input : None\r
+* Output : None\r
+* Return : Capture Compare 2 Register value.\r
+*******************************************************************************/\r
+u16 TIM1_GetCapture2(void)\r
+{\r
+ /* Get the Capture 2 Register value */\r
+ return TIM1->CCR2;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_GetCapture3\r
+* Description : Gets the TIM1 Input Capture 3 value.\r
+* Input : None\r
+* Output : None\r
+* Return : Capture Compare 3 Register value.\r
+*******************************************************************************/\r
+u16 TIM1_GetCapture3(void)\r
+{\r
+ /* Get the Capture 3 Register value */\r
+ return TIM1->CCR3;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_GetCapture4\r
+* Description : Gets the TIM1 Input Capture 4 value.\r
+* Input : None\r
+* Output : None\r
+* Return : Capture Compare 4 Register value.\r
+*******************************************************************************/\r
+u16 TIM1_GetCapture4(void)\r
+{\r
+ /* Get the Capture 4 Register value */\r
+ return TIM1->CCR4;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_GetCounter\r
+* Description : Gets the TIM1 Counter value.\r
+* Input : None\r
+* Output : None\r
+* Return : Counter Register value.\r
+*******************************************************************************/\r
+u16 TIM1_GetCounter(void)\r
+{\r
+ /* Get the Counter Register value */\r
+ return TIM1->CNT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_GetPrescaler\r
+* Description : Gets the TIM1 Prescaler value.\r
+* Input : None\r
+* Output : None\r
+* Return : Prescaler Register value.\r
+*******************************************************************************/\r
+u16 TIM1_GetPrescaler(void)\r
+{\r
+ /* Get the Prescaler Register value */\r
+ return TIM1->PSC;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_GetFlagStatus\r
+* Description : Checks whether the specified TIM1 flag is set or not.\r
+* Input : - TIM1_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - TIM1_FLAG_Update: TIM1 update Flag\r
+* - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag\r
+* - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag\r
+* - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag\r
+* - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag\r
+* - TIM1_FLAG_COM: TIM1 Commutation Flag\r
+* - TIM1_FLAG_Trigger: TIM1 Trigger Flag\r
+* - TIM1_FLAG_Break: TIM1 Break Flag\r
+* - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag\r
+* - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag\r
+* - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag\r
+* - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag\r
+* Output : None\r
+* Return : The new state of TIM1_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus TIM1_GetFlagStatus(u16 TIM1_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_GET_FLAG(TIM1_FLAG));\r
+\r
+ if ((TIM1->SR & TIM1_FLAG) != (u16)RESET )\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ClearFlag\r
+* Description : Clears the TIM1\92s pending flags.\r
+* Input : - TIM1_FLAG: specifies the flag to clear.\r
+* This parameter can be any combination of the following values:\r
+* - TIM1_FLAG_Update: TIM1 update Flag\r
+* - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag\r
+* - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag\r
+* - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag\r
+* - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag\r
+* - TIM1_FLAG_COM: TIM1 Commutation Flag\r
+* - TIM1_FLAG_Trigger: TIM1 Trigger Flag\r
+* - TIM1_FLAG_Break: TIM1 Break Flag\r
+* - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag\r
+* - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag\r
+* - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag\r
+* - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ClearFlag(u16 TIM1_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_CLEAR_FLAG(TIM1_FLAG));\r
+\r
+ /* Clear the flags */\r
+ TIM1->SR &= (u16)~TIM1_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_GetITStatus\r
+* Description : Checks whether the TIM1 interrupt has occurred or not.\r
+* Input : - TIM1_IT: specifies the TIM1 interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - TIM1_IT_Update: TIM1 update Interrupt source\r
+* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source\r
+* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source\r
+* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source\r
+* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source\r
+* - TIM1_IT_COM: TIM1 Commutation Interrupt\r
+* source\r
+* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source\r
+* - TIM1_IT_Break: TIM1 Break Interrupt source\r
+* Output : None\r
+* Return : The new state of the TIM1_IT(SET or RESET).\r
+*******************************************************************************/\r
+ITStatus TIM1_GetITStatus(u16 TIM1_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ \r
+ u16 TIM1_itStatus = 0x0, TIM1_itEnable = 0x0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_GET_IT(TIM1_IT));\r
+ \r
+ TIM1_itStatus = TIM1->SR & TIM1_IT;\r
+ \r
+ TIM1_itEnable = TIM1->DIER & TIM1_IT;\r
+\r
+ if ((TIM1_itStatus != (u16)RESET ) && (TIM1_itEnable != (u16)RESET ))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TIM1_ClearITPendingBit\r
+* Description : Clears the TIM1's interrupt pending bits.\r
+* Input : - TIM1_IT: specifies the pending bit to clear.\r
+* This parameter can be any combination of the following values:\r
+* - TIM1_IT_Update: TIM1 update Interrupt source\r
+* - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source\r
+* - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source\r
+* - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source\r
+* - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source\r
+* - TIM1_IT_COM: TIM1 Commutation Interrupt\r
+* source\r
+* - TIM1_IT_Trigger: TIM1 Trigger Interrupt source\r
+* - TIM1_IT_Break: TIM1 Break Interrupt source\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void TIM1_ClearITPendingBit(u16 TIM1_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_TIM1_IT(TIM1_IT));\r
+\r
+ /* Clear the IT pending Bit */\r
+ TIM1->SR &= (u16)~TIM1_IT;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TI1_Config\r
+* Description : Configure the TI1 as Input.\r
+* Input : - TIM1_ICPolarity : The Input Polarity.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICPolarity_Rising\r
+* - TIM1_ICPolarity_Falling\r
+* - TIM1_ICSelection: specifies the input to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICSelection_DirectTI: TIM1 Input 1 is selected to\r
+* be connected to IC1.\r
+* - TIM1_ICSelection_IndirectTI: TIM1 Input 1 is selected to\r
+* be connected to IC2.\r
+* - TIM1_ICSelection_TRGI:TIM1 Input 1 is selected to be\r
+* connected to TRGI.\r
+* - TIM1_ICFilter: Specifies the Input Capture Filter.\r
+* This parameter must be a value between 0x00 and 0x0F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void TI1_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,\r
+ u8 TIM1_ICFilter)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ tmpccmr1 = TIM1->CCMR1;\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC1E_BB = CCER_CCE_Reset;\r
+\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;\r
+ tmpccmr1 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4);\r
+\r
+ TIM1->CCMR1 = (u16)tmpccmr1;\r
+\r
+ /* Select the Polarity */\r
+ *(vu32 *) CCER_CC1P_BB = TIM1_ICPolarity;\r
+\r
+ /* Set the CCE Bit */\r
+ *(vu32 *) CCER_CC1E_BB = CCER_CCE_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TI2_Config\r
+* Description : Configure the TI2 as Input.\r
+* Input : - TIM1_ICPolarity : The Input Polarity.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICPolarity_Rising\r
+* - TIM1_ICPolarity_Falling\r
+* - TIM1_ICSelection: specifies the input to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICSelection_DirectTI: TIM1 Input 2 is selected to\r
+* be connected to IC2.\r
+* - TIM1_ICSelection_IndirectTI: TIM1 Input 2 is selected to\r
+* be connected to IC1.\r
+* - TIM1_ICSelection_TRGI: TIM1 Input 2 is selected to be\r
+* connected to TRGI.\r
+* - TIM1_ICFilter: Specifies the Input Capture Filter.\r
+* This parameter must be a value between 0x00 and 0x0F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void TI2_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,\r
+ u8 TIM1_ICFilter)\r
+{\r
+ u32 tmpccmr1 = 0;\r
+\r
+ tmpccmr1 = TIM1->CCMR1;\r
+\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC2E_BB = CCER_CCE_Reset;\r
+\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;\r
+ tmpccmr1 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter <<12);\r
+\r
+ TIM1->CCMR1 = (u16)tmpccmr1;\r
+\r
+ /* Select the Polarity */\r
+ *(vu32 *) CCER_CC2P_BB = TIM1_ICPolarity;\r
+\r
+ /* Set the CCE Bit */\r
+ *(vu32 *) CCER_CC2E_BB = CCER_CCE_Set;\r
+\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TI3_Config\r
+* Description : Configure the TI3 as Input.\r
+* Input : - TIM1_ICPolarity : The Input Polarity.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICPolarity_Rising\r
+* - TIM1_ICPolarity_Falling\r
+* - TIM1_ICSelection: specifies the input to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICSelection_DirectTI: TIM1 Input 3 is selected to\r
+* be connected to IC3.\r
+* - TIM1_ICSelection_IndirectTI: TIM1 Input 3 is selected to\r
+* be connected to IC4.\r
+* - TIM1_ICSelection_TRGI: TIM1 Input 3 is selected to be\r
+* connected to TRGI.\r
+* - TIM1_ICFilter: Specifies the Input Capture Filter.\r
+* This parameter must be a value between 0x00 and 0x0F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void TI3_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,\r
+ u8 TIM1_ICFilter)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ tmpccmr2 = TIM1->CCMR2;\r
+\r
+ /* Disable the Channel 3: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC3E_BB = CCER_CCE_Reset;\r
+\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;\r
+ tmpccmr2 |= (u16)TIM1_ICSelection | (u16)((u16)TIM1_ICFilter << 4);\r
+\r
+ TIM1->CCMR2 = (u16)tmpccmr2;\r
+\r
+ /* Select the Polarity */\r
+ *(vu32 *) CCER_CC3P_BB = TIM1_ICPolarity;\r
+\r
+ /* Set the CCE Bit */\r
+ *(vu32 *) CCER_CC3E_BB = CCER_CCE_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : TI4_Config\r
+* Description : Configure the TI4 as Input.\r
+* Input : - TIM1_ICPolarity : The Input Polarity.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICPolarity_Rising\r
+* - TIM1_ICPolarity_Falling\r
+* - TIM1_ICSelection: specifies the input to be used.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ICSelection_DirectTI: TIM1 Input 4 is selected to\r
+* be connected to IC4.\r
+* - TIM1_ICSelection_IndirectTI: TIM1 Input 4 is selected to\r
+* be connected to IC3.\r
+* - TIM1_ICSelection_TRGI: TIM1 Input 4 is selected to be\r
+* connected to TRGI.\r
+* - TIM1_ICFilter: Specifies the Input Capture Filter.\r
+* This parameter must be a value between 0x00 and 0x0F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void TI4_Config(u16 TIM1_ICPolarity, u16 TIM1_ICSelection,\r
+ u8 TIM1_ICFilter)\r
+{\r
+ u32 tmpccmr2 = 0;\r
+\r
+ tmpccmr2 = TIM1->CCMR2;\r
+ \r
+ /* Disable the Channel 4: Reset the CCE Bit */\r
+ *(vu32 *) CCER_CC4E_BB = CCER_CCE_Reset;\r
+\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;\r
+ tmpccmr2 |= (u16)((u16)TIM1_ICSelection << 8) | (u16)((u16)TIM1_ICFilter << 12);\r
+\r
+ TIM1->CCMR2 = (u16)tmpccmr2;\r
+\r
+ /* Select the Polarity */\r
+ *(vu32 *) CCER_CC4P_BB = TIM1_ICPolarity;\r
+\r
+ /* Set the CCE Bit */\r
+ *(vu32 *) CCER_CC4E_BB = CCER_CCE_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : ETR_Config\r
+* Description : Configure the External Trigger\r
+* Input : - TIM1_ExtTRGPrescaler: The external Trigger Prescaler.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ExtTRGPSC_OFF\r
+* - TIM1_ExtTRGPSC_DIV2\r
+* - TIM1_ExtTRGPSC_DIV4\r
+* - TIM1_ExtTRGPSC_DIV8\r
+* - TIM1_ExtTRGPolarity: The external Trigger Polarity.\r
+* This parameter can be one of the following values:\r
+* - TIM1_ExtTRGPolarity_Inverted\r
+* - TIM1_ExtTRGPolarity_NonInverted\r
+* - ExtTRGFilter: External Trigger Filter.\r
+* This parameter must be a value between 0x00 and 0x0F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+static void ETR_Config(u16 TIM1_ExtTRGPrescaler, u16 TIM1_ExtTRGPolarity,\r
+ u16 ExtTRGFilter)\r
+{\r
+ u32 tmpsmcr = 0;\r
+\r
+ tmpsmcr = TIM1->SMCR;\r
+\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr &= SMCR_ETR_Mask;\r
+ tmpsmcr |= TIM1_ExtTRGPrescaler | TIM1_ExtTRGPolarity | (u16)((u16)ExtTRGFilter << 8);\r
+\r
+ TIM1->SMCR = (u16)tmpsmcr;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_usart.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the USART firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_usart.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* USART RUN Mask */\r
+#define CR1_RUN_Set ((u16)0x2000) /* USART Enable Mask */\r
+#define CR1_RUN_Reset ((u16)0xDFFF) /* USART Disable Mask */\r
+\r
+#define CR2_Address_Mask ((u16)0xFFF0) /* USART address Mask */\r
+\r
+/* USART RWU Mask */\r
+#define CR1_RWU_Set ((u16)0x0002) /* USART mute mode Enable Mask */\r
+#define CR1_RWU_Reset ((u16)0xFFFD) /* USART mute mode Enable Mask */\r
+\r
+#define USART_IT_Mask ((u16)0x001F) /* USART Interrupt Mask */\r
+\r
+/* USART LIN Mask */\r
+#define CR2_LINE_Set ((u16)0x4000) /* USART LIN Enable Mask */\r
+#define CR2_LINE_Reset ((u16)0xBFFF) /* USART LIN Disable Mask */\r
+\r
+#define CR1_SBK_Set ((u16)0x0001) /* USART Break Character send Mask */\r
+\r
+/* USART SC Mask */\r
+#define CR3_SCEN_Set ((u16)0x0020) /* USART SC Enable Mask */\r
+#define CR3_SCEN_Reset ((u16)0xFFDF) /* USART SC Disable Mask */\r
+\r
+/* USART SC NACK Mask */\r
+#define CR3_NACK_Set ((u16)0x0010) /* USART SC NACK Enable Mask */\r
+#define CR3_NACK_Reset ((u16)0xFFEF) /* USART SC NACK Disable Mask */\r
+\r
+/* USART Half-Duplex Mask */\r
+#define CR3_HDSEL_Set ((u16)0x0008) /* USART Half-Duplex Enable Mask */\r
+#define CR3_HDSEL_Reset ((u16)0xFFF7) /* USART Half-Duplex Disable Mask */\r
+\r
+/* USART IrDA Mask */\r
+#define CR3_IRLP_Mask ((u16)0xFFFB) /* USART IrDA LowPower mode Mask */\r
+\r
+/* USART LIN Break detection */\r
+#define CR3_LBDL_Mask ((u16)0xFFDF) /* USART LIN Break detection Mask */\r
+\r
+/* USART WakeUp Method */\r
+#define CR3_WAKE_Mask ((u16)0xF7FF) /* USART WakeUp Method Mask */\r
+\r
+/* USART IrDA Mask */\r
+#define CR3_IREN_Set ((u16)0x0002) /* USART IrDA Enable Mask */\r
+#define CR3_IREN_Reset ((u16)0xFFFD) /* USART IrDA Disable Mask */\r
+\r
+#define GTPR_LSB_Mask ((u16)0x00FF) /* Guard Time Register LSB Mask */\r
+#define GTPR_MSB_Mask ((u16)0xFF00) /* Guard Time Register MSB Mask */\r
+\r
+#define CR1_CLEAR_Mask ((u16)0xE9F3) /* USART CR1 Mask */\r
+#define CR2_CLEAR_Mask ((u16)0xC0FF) /* USART CR2 Mask */\r
+#define CR3_CLEAR_Mask ((u16)0xFCFF) /* USART CR3 Mask */\r
+\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_DeInit\r
+* Description : Deinitializes the USARTx peripheral registers to their\r
+* default reset values.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_DeInit(USART_TypeDef* USARTx)\r
+{\r
+ switch (*(u32*)&USARTx)\r
+ {\r
+ case USART1_BASE:\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
+ break;\r
+\r
+ case USART2_BASE:\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
+ break;\r
+\r
+ case USART3_BASE:\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_Init\r
+* Description : Initializes the USARTx peripheral according to the specified\r
+* parameters in the USART_InitStruct .\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART peripheral.\r
+* - USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+* that contains the configuration information for the\r
+* specified USART peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ u32 tmpreg = 0x00, apbclock = 0x00;\r
+ u32 integerdivider = 0x00;\r
+ u32 fractionaldivider = 0x00;\r
+ RCC_ClocksTypeDef RCC_ClocksStatus;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
+ assert(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
+ assert(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
+ assert(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
+ assert(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
+ assert(IS_USART_CLOCK(USART_InitStruct->USART_Clock));\r
+ assert(IS_USART_CPOL(USART_InitStruct->USART_CPOL));\r
+ assert(IS_USART_CPHA(USART_InitStruct->USART_CPHA));\r
+ assert(IS_USART_LASTBIT(USART_InitStruct->USART_LastBit)); \r
+ \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear STOP[13:12], CLKEN, CPOL, CPHA and LBCL bits */\r
+ tmpreg &= CR2_CLEAR_Mask;\r
+\r
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set STOP[13:12] bits according to USART_Mode value */\r
+ /* Set CPOL bit according to USART_CPOL value */\r
+ /* Set CPHA bit according to USART_CPHA value */\r
+ /* Set LBCL bit according to USART_LastBit value */\r
+ tmpreg |= (u32)USART_InitStruct->USART_StopBits | USART_InitStruct->USART_Clock |\r
+ USART_InitStruct->USART_CPOL | USART_InitStruct->USART_CPHA |\r
+ USART_InitStruct->USART_LastBit;\r
+\r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (u16)tmpreg;\r
+\r
+/*---------------------------- USART CR1 Configuration -----------------------*/\r
+ tmpreg = 0x00;\r
+ tmpreg = USARTx->CR1;\r
+ /* Clear M, PCE, PS, TE and RE bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+\r
+ /* Configure the USART Word Length, Parity and mode ----------------------- */\r
+ /* Set the M bits according to USART_WordLength value */\r
+ /* Set PCE and PS bits according to USART_Parity value */\r
+ /* Set TE and RE bits according to USART_Mode value */\r
+ tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
+ USART_InitStruct->USART_Mode;\r
+\r
+ /* Write to USART CR1 */\r
+ USARTx->CR1 = (u16)tmpreg;\r
+\r
+/*---------------------------- USART CR3 Configuration -----------------------*/\r
+ tmpreg = 0x00;\r
+ tmpreg = USARTx->CR3;\r
+ /* Clear CTSE and RTSE bits */\r
+ tmpreg &= CR3_CLEAR_Mask;\r
+\r
+ /* Configure the USART HFC -------------------------------------------------*/\r
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
+\r
+ /* Write to USART CR3 */\r
+ USARTx->CR3 = (u16)tmpreg;\r
+\r
+/*---------------------------- USART BRR Configuration -----------------------*/\r
+ tmpreg = 0x00;\r
+\r
+ /* Configure the USART Baud Rate -------------------------------------------*/\r
+ RCC_GetClocksFreq(&RCC_ClocksStatus);\r
+ if ((*(u32*)&USARTx) == USART1_BASE)\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
+ }\r
+ else\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
+ }\r
+\r
+ /* Determine the integer part */\r
+ integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));\r
+ tmpreg = (integerdivider / 0x64) << 0x04;\r
+\r
+ /* Determine the fractional part */\r
+ fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));\r
+ tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);\r
+\r
+ /* Write to USART BRR */\r
+ USARTx->BRR = (u16)tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_StructInit\r
+* Description : Fills each USART_InitStruct member with its default value.\r
+* Input : - USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+* which will be initialized.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ /* USART_InitStruct members default value */\r
+ USART_InitStruct->USART_BaudRate = 0x2580; /* 9600 Baud */\r
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
+ USART_InitStruct->USART_Parity = USART_Parity_No ;\r
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;\r
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+ USART_InitStruct->USART_Clock = USART_Clock_Disable;\r
+ USART_InitStruct->USART_CPOL = USART_CPOL_Low;\r
+ USART_InitStruct->USART_CPHA = USART_CPHA_1Edge;\r
+ USART_InitStruct->USART_LastBit = USART_LastBit_Disable;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_Cmd\r
+* Description : Enables or disables the specified USART peripheral.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* : - NewState: new state of the USARTx peripheral.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected USART by setting the RUN bit in the CR1 register */\r
+ USARTx->CR1 |= CR1_RUN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected USART by clearing the RUN bit in the CR1 register */\r
+ USARTx->CR1 &= CR1_RUN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ITConfig\r
+* Description : Enables or disables the specified USART interrupts.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_IT: specifies the USART interrupt sources to be\r
+* enabled or disabled.\r
+* This parameter can be one of the following values:\r
+* - USART_IT_PE\r
+* - USART_IT_TXE\r
+* - USART_IT_TC\r
+* - USART_IT_RXNE\r
+* - USART_IT_IDLE\r
+* - USART_IT_LBD\r
+* - USART_IT_CTS\r
+* - USART_IT_ERR\r
+* - NewState: new state of the specified USARTx interrupts.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState)\r
+{\r
+ u32 usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
+ u32 address = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_USART_CONFIG_IT(USART_IT)); \r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Get the USART register index */\r
+ usartreg = (((u8)USART_IT) >> 0x05);\r
+\r
+ /* Get the interrupt position */\r
+ itpos = USART_IT & USART_IT_Mask;\r
+\r
+ itmask = (((u32)0x01) << itpos);\r
+ address = *(u32*)&(USARTx);\r
+\r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ address += 0x0C;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ address += 0x10;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ address += 0x14; \r
+ }\r
+ if (NewState != DISABLE)\r
+ {\r
+ *(u32*)address |= itmask;\r
+ }\r
+ else\r
+ {\r
+ *(u32*)address &= ~itmask;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_DMACmd\r
+* Description : Enables or disables the USART\92s DMA interface.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_DMAReq: specifies the DMA request.\r
+* This parameter can be any combination of the following values:\r
+* - USART_DMAReq_Tx\r
+* - USART_DMAReq_Rx\r
+* - NewState: new state of the DMA Request sources.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_USART_DMAREQ(USART_DMAReq)); \r
+ assert(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 |= USART_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 &= (u16)~USART_DMAReq;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SetAddress\r
+* Description : Sets the address of the USART node.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_Address: Indicates the address of the USART node.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_USART_ADDRESS(USART_Address)); \r
+ \r
+ /* Clear the USART address */\r
+ USARTx->CR2 &= CR2_Address_Mask;\r
+ /* Set the USART address node */\r
+ USARTx->CR2 |= USART_Address;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_WakeUpConfig\r
+* Description : Selects the USART WakeUp method.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_WakeUp: specifies the USART wakeup method.\r
+* This parameter can be one of the following values:\r
+* - USART_WakeUp_IdleLine\r
+* - USART_WakeUp_AddressMark\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_USART_WAKEUP(USART_WakeUp));\r
+ \r
+ USARTx->CR1 &= CR3_WAKE_Mask;\r
+ USARTx->CR1 |= USART_WakeUp;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ReceiverWakeUpCmd\r
+* Description : Determines if the USART is in mute mode or not.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - NewState: new state of the USART mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the mute mode USART by setting the RWU bit in the CR1 register */\r
+ USARTx->CR1 |= CR1_RWU_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the mute mode USART by clearing the RWU bit in the CR1 register */\r
+ USARTx->CR1 &= CR1_RWU_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_LINBreakDetectLengthConfig\r
+* Description : Sets the USART LIN Break detection length.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_LINBreakDetectLength: specifies the LIN break\r
+* detection length.\r
+* This parameter can be one of the following values:\r
+* - USART_LINBreakDetectLength_10b\r
+* - USART_LINBreakDetectLength_11b\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
+ \r
+ USARTx->CR2 &= CR3_LBDL_Mask;\r
+ USARTx->CR2 |= USART_LINBreakDetectLength; \r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_LINCmd\r
+* Description : Enables or disables the USART\92s LIN mode.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - NewState: new state of the USART LIN mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the LIN mode by setting the LINE bit in the CR2 register */\r
+ USARTx->CR2 |= CR2_LINE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode by clearing the LINE bit in the CR2 register */\r
+ USARTx->CR2 &= CR2_LINE_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SendData\r
+* Description : Transmits signle data through the USARTx peripheral.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - Data: the data to transmit.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SendData(USART_TypeDef* USARTx, u16 Data)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_USART_DATA(Data)); \r
+ \r
+ /* Transmit Data */\r
+ USARTx->DR = (Data & (u16)0x01FF);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ReceiveData\r
+* Description : Returns the most recent received data by the USARTx peripheral.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* Output : None\r
+* Return : The received data.\r
+*******************************************************************************/\r
+u16 USART_ReceiveData(USART_TypeDef* USARTx)\r
+{\r
+ /* Receive Data */\r
+ return (u16)(USARTx->DR & (u16)0x01FF);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SendBreak\r
+* Description : Transmits break characters.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SendBreak(USART_TypeDef* USARTx)\r
+{\r
+ /* Send break characters */\r
+ USARTx->CR1 |= CR1_SBK_Set;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SetGuardTime\r
+* Description : Sets the specified USART guard time.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_GuardTime: specifies the guard time.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime)\r
+{ \r
+ /* Clear the USART Guard time */\r
+ USARTx->GTPR &= GTPR_LSB_Mask;\r
+ /* Set the USART guard time */\r
+ USARTx->GTPR |= (u16)((u16)USART_GuardTime << 0x08);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SetPrescaler\r
+* Description : Sets the system clock prescaler.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_Prescaler: specifies the prescaler clock.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler)\r
+{ \r
+ /* Clear the USART prescaler */\r
+ USARTx->GTPR &= GTPR_MSB_Mask;\r
+ /* Set the USART prescaler */\r
+ USARTx->GTPR |= USART_Prescaler;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SmartCardCmd\r
+* Description : Enables or disables the USART\92s Smart Card mode.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - NewState: new state of the Smart Card mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_SCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_SCEN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_SmartCardNACKCmd\r
+* Description : Enables or disables NACK transmission.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - NewState: new state of the NACK transmission.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_NACK_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_NACK_Reset;\r
+ }\r
+\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_HalfDuplexCmd\r
+* Description : Enables or disables the USART\92s Half Duplex communication.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - NewState: new state of the USART Communication.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_HDSEL_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_HDSEL_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_IrDAConfig\r
+* Description : Configures the USART\92s IrDA interface.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_IrDAMode: specifies the IrDA mode.\r
+* This parameter can be one of the following values:\r
+* - USART_IrDAMode_LowPower\r
+* - USART_IrDAMode_Normal\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_USART_IRDA_MODE(USART_IrDAMode));\r
+ \r
+ USARTx->CR3 &= CR3_IRLP_Mask;\r
+ USARTx->CR3 |= USART_IrDAMode;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_IrDACmd\r
+* Description : Enables or disables the USART\92s IrDA interface.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - NewState: new state of the IrDA mode.\r
+* This parameter can be: ENABLE or DISABLE.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_IREN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_IREN_Reset;\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_GetFlagStatus\r
+* Description : Checks whether the specified USART flag is set or not.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_FLAG: specifies the flag to check.\r
+* This parameter can be one of the following values:\r
+* - USART_FLAG_CTS\r
+* - USART_FLAG_LBD\r
+* - USART_FLAG_TXE\r
+* - USART_FLAG_TC\r
+* - USART_FLAG_RXNE\r
+* - USART_FLAG_IDLE\r
+* - USART_FLAG_ORE\r
+* - USART_FLAG_NE\r
+* - USART_FLAG_FE\r
+* - USART_FLAG_PE\r
+* Output : None\r
+* Return : The new state of USART_FLAG (SET or RESET).\r
+*******************************************************************************/\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_USART_FLAG(USART_FLAG));\r
+ \r
+ if ((USARTx->SR & USART_FLAG) != (u16)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ClearFlag\r
+* Description : Clears the USARTx's pending flags.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_FLAG: specifies the flag to clear.\r
+* This parameter can be any combination of the following values:\r
+* - USART_FLAG_CTS\r
+* - USART_FLAG_LBD\r
+* - USART_FLAG_TXE\r
+* - USART_FLAG_TC\r
+* - USART_FLAG_RXNE\r
+* - USART_FLAG_IDLE\r
+* - USART_FLAG_ORE\r
+* - USART_FLAG_NE\r
+* - USART_FLAG_FE\r
+* - USART_FLAG_PE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_USART_CLEAR_FLAG(USART_FLAG));\r
+ \r
+ USARTx->SR &= (u16)~USART_FLAG;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_GetITStatus\r
+* Description : Checks whether the specified USART interrupt has occurred or not.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_IT: specifies the USART interrupt source to check.\r
+* This parameter can be one of the following values:\r
+* - USART_IT_PE\r
+* - USART_IT_TXE\r
+* - USART_IT_TC\r
+* - USART_IT_RXNE\r
+* - USART_IT_IDLE\r
+* - USART_IT_LBD\r
+* - USART_IT_CTS\r
+* - USART_IT_ORE\r
+* - USART_IT_NE\r
+* - USART_IT_FE\r
+* Output : None\r
+* Return : The new state of USART_IT (SET or RESET).\r
+*******************************************************************************/\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT)\r
+{\r
+ u32 bitpos = 0x00, itmask = 0x00, usartreg = 0;\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_USART_IT(USART_IT));\r
+ \r
+ /* Get the USART register index */\r
+ usartreg = (((u8)USART_IT) >> 0x05);\r
+\r
+ /* Get the interrupt position */\r
+ itmask = USART_IT & USART_IT_Mask;\r
+\r
+ itmask = (u32)0x01 << itmask;\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ itmask &= USARTx->CR1;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ itmask &= USARTx->CR2;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ itmask &= USARTx->CR3;\r
+ }\r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+\r
+ bitpos = (u32)0x01 << bitpos;\r
+ bitpos &= USARTx->SR;\r
+\r
+ if ((itmask != (u16)RESET)&&(bitpos != (u16)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : USART_ClearITPendingBit\r
+* Description : Clears the USARTx\92s interrupt pending bits.\r
+* Input : - USARTx: where x can be 1, 2 or 3 to select the USART\r
+* peripheral.\r
+* - USART_IT: specifies the interrupt pending bit to clear.\r
+* This parameter can be one of the following values:\r
+* - USART_IT_PE\r
+* - USART_IT_TXE\r
+* - USART_IT_TC\r
+* - USART_IT_RXNE\r
+* - USART_IT_IDLE\r
+* - USART_IT_LBD\r
+* - USART_IT_CTS\r
+* - USART_IT_ORE\r
+* - USART_IT_NE\r
+* - USART_IT_FE\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT)\r
+{\r
+ u32 bitpos = 0x00, itmask = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert(IS_USART_IT(USART_IT));\r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+\r
+ itmask = (u32)0x01 << bitpos;\r
+ USARTx->SR &= ~itmask;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : stm32f10x_wwdg.c\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : This file provides all the WWDG firmware functions.\r
+********************************************************************************\r
+* History:\r
+* 04/02/2007: V0.2\r
+* 02/05/2007: V0.1\r
+* 09/29/2006: V0.01\r
+********************************************************************************\r
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+*******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_wwdg.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* ----------- WWDG registers bit address in the alias region ----------- */\r
+#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)\r
+\r
+/* Alias word address of EWI bit */\r
+#define CFR_OFFSET (WWDG_OFFSET + 0x04)\r
+#define EWI_BitNumber 0x09\r
+#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))\r
+\r
+/* Alias word address of EWIF bit */\r
+#define SR_OFFSET (WWDG_OFFSET + 0x08)\r
+#define EWIF_BitNumber 0x00\r
+#define SR_EWIF_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (EWIF_BitNumber * 4))\r
+\r
+/* --------------------- WWDG registers bit mask ------------------------ */\r
+/* CR register bit mask */\r
+#define CR_WDGA_Set ((u32)0x00000080)\r
+\r
+/* CFR register bit mask */\r
+#define CFR_WDGTB_Mask ((u32)0xFFFFFE7F)\r
+#define CFR_W_Mask ((u32)0xFFFFFF80)\r
+\r
+#define BIT_Mask ((u8)0x7F)\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/*******************************************************************************\r
+* Function Name : WWDG_DeInit\r
+* Description : Deinitializes the WWDG peripheral registers to their default\r
+* reset values.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WWDG_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WWDG_SetPrescaler\r
+* Description : Sets the WWDG Prescaler.\r
+* Input : - WWDG_Prescaler: specifies the WWDG Prescaler.\r
+* This parameter can be one of the following values:\r
+* - WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r
+* - WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r
+* - WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r
+* - WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WWDG_SetPrescaler(u32 WWDG_Prescaler)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_WWDG_PRESCALER(WWDG_Prescaler));\r
+\r
+ /* Clear WDGTB[8:7] bits */\r
+ tmpreg = WWDG->CFR & CFR_WDGTB_Mask;\r
+\r
+ /* Set WDGTB[8:7] bits according to WWDG_Prescaler value */\r
+ tmpreg |= WWDG_Prescaler;\r
+\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WWDG_SetWindowValue\r
+* Description : Sets the WWDG window value.\r
+* Input : - WindowValue: specifies the window value to be compared to\r
+* the downcounter.\r
+* This parameter value must be lower than 0x80.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WWDG_SetWindowValue(u8 WindowValue)\r
+{\r
+ u32 tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert(IS_WWDG_WINDOW_VALUE(WindowValue));\r
+\r
+ /* Clear W[6:0] bits */\r
+ tmpreg = WWDG->CFR & CFR_W_Mask;\r
+\r
+ /* Set W[6:0] bits according to WindowValue value */\r
+ tmpreg |= WindowValue & BIT_Mask;\r
+\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WWDG_EnableIT\r
+* Description : Enables the WWDG Early Wakeup interrupt(EWI).\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WWDG_EnableIT(void)\r
+{\r
+ *(vu32 *) CFR_EWI_BB = (u32)ENABLE;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WWDG_SetCounter\r
+* Description : Sets the WWDG counter value.\r
+* Input : - Counter: specifies the watchdog counter value.\r
+* This parameter must be a number between 0x40 and 0x7F.\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WWDG_SetCounter(u8 Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_WWDG_COUNTER(Counter));\r
+\r
+ /* Write to T[6:0] bits to configure the counter value, no need to do\r
+ a read-modify-write; writing a 0 to WDGA bit does nothing */\r
+ WWDG->CR = Counter & BIT_Mask;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WWDG_Enable\r
+* Description : Enables WWDG and load the counter value.\r
+* - Counter: specifies the watchdog counter value.\r
+* This parameter must be a number between 0x40 and 0x7F.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WWDG_Enable(u8 Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert(IS_WWDG_COUNTER(Counter));\r
+\r
+ WWDG->CR = CR_WDGA_Set | Counter;\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WWDG_GetFlagStatus\r
+* Description : Checks whether the Early Wakeup interrupt flag is set or not.\r
+* Input : None\r
+* Output : None\r
+* Return : The new state of the Early Wakeup interrupt flag (SET or RESET)\r
+*******************************************************************************/\r
+FlagStatus WWDG_GetFlagStatus(void)\r
+{\r
+ return (FlagStatus)(*(vu32 *) SR_EWIF_BB);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name : WWDG_ClearFlag\r
+* Description : Clears Early Wakeup interrupt flag.\r
+* Input : None\r
+* Output : None\r
+* Return : None\r
+*******************************************************************************/\r
+void WWDG_ClearFlag(void)\r
+{\r
+ WWDG->SR = (u32)RESET;\r
+}\r
+\r
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************\r
+* File Name : version.txt\r
+* Author : MCD Application Team\r
+* Date First Issued : 09/29/2006\r
+* Description : Version file for STM32F10x Firmware Library.\r
+********************************************************************************\r
+\r
+* 04/02/2007: V0.2\r
+===================\r
+ Updated version\r
+ \r
+* 02/05/2007 : V0.1\r
+===================\r
+ Updated version\r
+\r
+* 09/29/2006 : V0.01\r
+===================\r
+ Created.\r
+\r
+******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE******\r
+\r
+\r
projects / freertos / commitdiff