--- /dev/null
+Reporting Unknown JTAG TAP IDS
+------------------------------
+
+If OpenOCD reports an UNKNOWN or Unexpected Tap ID please report it to
+the development mailing list - However - keep reading.
+
+openocd-development@lists.berlios.de.
+
+========================================
+
+About "UNEXPECTED" tap ids.
+
+ Before reporting an "UNEXPECTED TAP ID" - take a closer look.
+ Perhaps you have your OpenOCD configured the wrong way, maybe you
+ have the tap configured the wrong way? Or something else is wrong.
+ (Remember: OpenOCD does not stop if the tap is not present)
+
+ This "tap id check" is there for a purpose.
+ The goal is to help get the *right* configuration.
+
+The idea is this:
+
+ Every JTAG tap is suppose to have "a unique 32bit tap id" number.
+ They are suppose to be "sort of unique" but they are not. There are
+ no guarantees.
+
+Version Number Changes:
+
+ Sometimes, the tap ID only differs by VERSION number. If so - it's
+ not a big deal. Please do report this information. We'd like to
+ know about it.
+
+ For example
+
+Error: ERROR: Tap: s3c4510.cpu - Expected id: 0x3f0f0f0f, Got: 0x1f0f0f0f
+Error: ERROR: expected: mfg: 0x787, part: 0xf0f0, ver: 0x3
+Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x1
+
+========================================
+
+Updating the Tap ID number your self
+
+ Why do this? You just want the warning to go away. And don't want
+ to update your version/instance of OpenOCD.
+
+ On simple systems, to fix this problem, in your "openocd.cfg" file,
+ override the tap id. Depending on the tap, add one of these 3
+ commands:
+
+ set CPUTAPID newvalue
+ or set BSTAPID newvalue
+ or set FLASHTAPID newvalue
+ or set ETMTAPID newvalue
+
+ Where "newvalue" is the new value you are seeing.
+
+ On complex systems, (with many taps and chips) you probably have a
+ custom configuration file. Its is more complicated, you're going to
+ have to read through the configuration files
+
+========================================
+
+What to send:
+
+Cut & paste the output of OpenOCD that pointed you at this file.
+
+Please include the VERSION number of OpenOCD you are using.
+
+And please include the information below.
+
+========================================
+
+A) The JTAG TAP ID code.
+
+This is always a 32bit hex number.
+
+Examples:
+ 0x1f0f0f0f - is an old ARM7TDMI
+ 0x3f0f0f0f - is a newer ARM7TDMI
+ 0x3ba00477 - is an ARM cortex M3
+
+Some chips have multiple JTAG taps - be sure to list
+each one individually - ORDER is important!
+
+========================================
+B) The maker of the part
+
+Examples:
+ Xilinx, Atmel, ST Micro Systems, Freescale
+
+========================================
+C) The family of parts it belongs to
+
+Examples:
+ "NXP LPC Series"
+ "Atmel SAM7 Series"
+
+========================================
+
+D) The actual part number on the package
+
+ For example: "S3C45101x01"
+
+========================================
+
+E) What type of board it is.
+
+ie: a "commercial off the self eval board" that one can purchase (as
+opposed to your private internal custom board)
+
+For example: ST Micro systems has Eval boards, so does Analog Devices
+
+Or - if it is inside something "hackers like to hack" that information
+is helpful too.
+
+For example: A consumer GPS unit or a cellphone
+
+========================================
+
+(F) The maker of the board
+ ie: Olimex, LogicPD, Freescale(eval board)
+
+========================================
+
+(G) Identifying information on the board.
+
+ Not good: "iar red ST eval board"
+
+ Really good: "IAR STR912-SK evaluation board"
+
+========================================
+
+(H) Are there other interesting (JTAG) chips on the board?
+
+ ie: An FPGA or CPLD ...
+
+========================================
@settitle Open On-Chip Debugger (OpenOCD)
@dircategory Development
@direntry
+@paragraphindent 0
* OpenOCD: (openocd). Open On-Chip Debugger.
@end direntry
@c %**end of header
@include version.texi
@copying
-Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}@*
-Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
+
+@itemize @bullet
+@item Copyright @copyright{} 2008 The OpenOCD Project
+@item Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
+@item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
+@item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
+@end itemize
+
@quotation
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.2 or
@insertcopying
@end titlepage
+@summarycontents
@contents
@node Top, About, , (dir)
@insertcopying
@menu
-* About:: About OpenOCD.
-* Developers:: OpenOCD developers
-* Building:: Building OpenOCD
-* Running:: Running OpenOCD
-* Configuration:: OpenOCD Configuration.
-* Target library:: Target library
-* Commands:: OpenOCD Commands
-* Sample Scripts:: Sample Target Scripts
-* TFTP:: TFTP
-* GDB and OpenOCD:: Using GDB and OpenOCD
-* TCL and OpenOCD:: Using TCL and OpenOCD
-* TCL scripting API:: Tcl scripting API
-* Upgrading:: Deprecated/Removed Commands
-* FAQ:: Frequently Asked Questions
-* License:: GNU Free Documentation License
-* Index:: Main index.
+* About:: About OpenOCD.
+* Developers:: OpenOCD developers
+* Building:: Building OpenOCD
+* JTAG Hardware Dongles:: JTAG Hardware Dongles
+* Running:: Running OpenOCD
+* Simple Configuration Files:: Simple Configuration Files
+* Config File Guidelines:: Config File Guidelines
+* About JIM-Tcl:: About JIM-Tcl
+* Daemon Configuration:: Daemon Configuration
+* Interface - Dongle Configuration:: Interface - Dongle Configuration
+* Reset Configuration:: Reset Configuration
+* Tap Creation:: Tap Creation
+* Target Configuration:: Target Configuration
+* Flash Configuration:: Flash Configuration
+* General Commands:: General Commands
+* JTAG Commands:: JTAG Commands
+* Sample Scripts:: Sample Target Scripts
+* TFTP:: TFTP
+* GDB and OpenOCD:: Using GDB and OpenOCD
+* TCL scripting API:: Tcl scripting API
+* Upgrading:: Deprecated/Removed Commands
+* Target library:: Target library
+* FAQ:: Frequently Asked Questions
+* TCL Crash Course:: TCL Crash Course
+* License:: GNU Free Documentation License
+@comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
+@comment case issue with ``Index.html'' and ``index.html''
+@comment Occurs when creating ``--html --no-split'' output
+@comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
+* OpenOCD Index:: Main index.
@end menu
@node About
@unnumbered About
@cindex about
-The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
-and boundary-scan testing for embedded target devices. The targets are interfaced
-using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
-connection types in the future.
+The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
+in-system programming and boundary-scan testing for embedded target
+devices.
-OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
-Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
-ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
-Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
+@b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
+with the JTAG (IEEE 1149.1) complient taps on your target board.
-Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
-command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
-and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
+@b{Dongles:} OpenOCD currently many types of hardware dongles: USB
+Based, Parallel Port Based, and other standalone boxes that run
+OpenOCD internally. See the section titled: @xref{JTAG Hardware
+Dongles}.
+
+@b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920t,
+ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
+Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
+debugged via the GDB Protocol.
+
+@b{Flash Programing:} Flash writing is supported for external CFI
+compatible flashes (Intel and AMD/Spansion command set) and several
+internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3 and
+STM32x). Preliminary support for using the LPC3180's NAND flash
+controller is included.
@node Developers
@chapter Developers
latest version (make sure there is no (non-svn) directory called "openocd" in the
current directory):
-@smallexample
+@example
svn checkout svn://svn.berlios.de/openocd/trunk openocd
-@end smallexample
+@end example
Building OpenOCD requires a recent version of the GNU autotools.
On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
a kernel module, only a user space library.
To build OpenOCD (on both Linux and Cygwin), use the following commands:
-@smallexample
+@example
./bootstrap
-@end smallexample
+@end example
Bootstrap generates the configure script, and prepares building on your system.
-@smallexample
+@example
./configure
-@end smallexample
+@end example
Configure generates the Makefiles used to build OpenOCD.
-@smallexample
+@example
make
-@end smallexample
+@end example
Make builds OpenOCD, and places the final executable in ./src/.
The configure script takes several options, specifying which JTAG interfaces
@option{--enable-gccwarnings} - enable extra gcc warnings during build
@end itemize
+@node JTAG Hardware Dongles
+@chapter JTAG Hardware Dongles
+@cindex dongles
+@cindex ftdi
+@cindex wiggler
+@cindex zy1000
+@cindex printer port
+@cindex usb adapter
+@cindex rtck
+
+Defined: @b{dongle}: A small device that plugins into a computer and serves as
+an adapter .... [snip]
+
+In the OpenOCD case, this generally refers to @b{a small adapater} one
+attaches to your computer via USB or the Parallel Printer Port. The
+execption being the Zylin ZY1000 which is a small box you attach via
+an ethernet cable.
+
+
+@section Choosing a Dongle
+
+There are three things you should keep in mind when choosing a dongle.
+
+@enumerate
+@item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
+@item @b{Connection} Printer Ports - Does your computer have one?
+@item @b{Connection} Is that long printer bit-bang cable practical?
+@item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
+@end enumerate
+
+@section Stand alone Systems
+
+@b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
+dongle, but a standalone box.
+
+@section USB FT2232 Based
+
+There are many USB jtag dongles on the market, many of them are based
+on a chip from ``Future Technology Devices International'' (FTDI)
+known as the FTDI FT2232.
+
+See: @url{http://www.ftdichip.com} or @url{http://www.ftdichip.com/Products/FT2232H.htm}
+
+As of 28/Nov/2008, the following are supported:
+
+@itemize @bullet
+@item @b{usbjtag}
+@* Link Unknown [not easily verified]
+@item @b{jtagkey}
+@* See: @url{http://www.amontec.com/jtagkey.shtml}
+@item @b{oocdlink}
+@* Link Unknown [not easily verified]
+@item @b{signalyzer}
+@* See: @url{http://www.signalyzer.com}
+@item @b{evb_lm3s811}
+@* See: @url{http://www.luminarymicro.com} - The Luminary Micro Stellaris LM3S811 eval board has an FTD2232C chip built in.
+@item @b{olimex-jtag}
+@* See: @url{http://www.olimex.com}
+@item @b{flyswatter}
+@* See: @url{http://www.tincantools.com}
+@item @b{turtelizer2}
+@* See: @url{http://www.ethernut.de}, or @url{http://www.ethernut.de/en/hardware/turtelizer/index.html}
+@item @b{comstick}
+@* Link: @url{http://www.hitex.com/index.php?id=383}
+@item @b{stm32stick}
+@* Link Unknown [not easily verified]
+@end itemize
+
+@section USB JLINK based
+There are several OEM versions of the Segger @b{JLINK} adapter. It is
+an example of a micro controller based JTAG adapter, it uses an
+AT91SAM764 internally.
+
+@itemize @bullet
+@item @b{ATMEL SAMICE} Only works with ATMEL chips!
+@* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
+@item @b{SEGGER JLINK}
+@* Link: @url{http://www.segger.com/jlink.html}
+@item @b{IAR J-Link}
+@* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
+@item @b{TODO [28/nov/2008]: Confirm if the IAR version works.}
+@end itemize
+
+@section USB Other
+@itemize @bullet
+@item @b{USBprog}
+@* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
+
+@item @b{USB - Presto}
+@* Link: @url{http://tools.asix.net/prg_presto.htm}
+@end itemize
+
+@section IBM PC Parallel Printer Port Based
+
+The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
+and the MacGraigor Wiggler. There are many clones and variations of
+these on the market.
+
+@itemize @bullet
+
+@item @b{Wiggler} - There are many clones of this.
+@* Link: @url{http://www.macraigor.com/wiggler.htm}
+
+@item @b{DLC5} - From XILINX - There are many clones of this
+@* Link: Search the web for: ``XILINX DLC5'' - it is no longer
+produced, PDF schematics are easily found and it is easy to make.
+
+@item @b{Amontec - JTAG Accelerator}
+@* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
+
+@item @b{GW16402}
+@* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
+
+@item @b{Wiggler2}
+@* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
+
+@item @b{Wiggler_ntrst_inverted}
+@* Yet another variation - See the source code, src/jtag/parport.c
+
+@item @b{old_amt_wiggler}
+@* Unknown - probably not on the market today
+
+@item @b{arm-jtag}
+@* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
+
+@item @b{chameleon}
+@* Link: @url{http://www.amontec.com/chameleon.shtml}
+
+@item @b{Triton}
+@* Unknown.
+
+@item @b{Lattice}
+@* From Lattice Semiconductor [link unknown]
+
+@item @b{flashlink}
+@* From ST Microsystems, link:
+@url{http://www.st.com/stonline/products/literature/um/7889.pdf}
+Title: FlashLINK JTAG programing cable for PSD and uPSD
+
+@end itemize
+
+@section Other...
+@itemize @bullet
+
+@item @b{ep93xx}
+@* An EP93xx based linux machine using the GPIO pins directly.
+
+@item @b{at91rm9200}
+@* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
+
+@end itemize
+
@node Running
@chapter Running
@cindex running OpenOCD
@cindex --debug_level
@cindex --logfile
@cindex --search
-OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).
-Run with @option{--help} or @option{-h} to view the available command line switches.
-It reads its configuration by default from the file openocd.cfg located in the current
-working directory. This may be overwritten with the @option{-f <configfile>} command line
-switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
-are executed in order.
+The @option{--help} option shows:
+@verbatim
+bash$ openocd --help
+
+--help | -h display this help
+--version | -v display OpenOCD version
+--file | -f use configuration file <name>
+--search | -s dir to search for config files and scripts
+--debug | -d set debug level <0-3>
+--log_output | -l redirect log output to file <name>
+--command | -c run <command>
+@end verbatim
+
+By default openocd reads the file configuration file ``openocd.cfg''
+in the current directory. To specify a different (or multiple)
+configuration file, you can use the ``-f'' option. For example:
+
+@example
+ openocd -f config1.cfg -f config2.cfg -f config3.cfg
+@end example
+
+Once started, OpenOCD runs as a daemon, waiting for connections from
+clients (Telnet, GDB, Other).
-Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
+If you are having problems, you can enable internal debug messages via
+the ``-d'' option.
-To enable debug output (when reporting problems or working on OpenOCD itself), use
-the @option{-d} command line switch. This sets the @option{debug_level} to "3", outputting
-the most information, including debug messages. The default setting is "2", outputting
-only informational messages, warnings and errors. You can also change this setting
-from within a telnet or gdb session using @option{debug_level <n>} @xref{debug_level}.
+Also it is possible to interleave commands w/config scripts using the
+@option{-c} command line switch.
-You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
+To enable debug output (when reporting problems or working on OpenOCD
+itself), use the @option{-d} command line switch. This sets the
+@option{debug_level} to "3", outputting the most information,
+including debug messages. The default setting is "2", outputting only
+informational messages, warnings and errors. You can also change this
+setting from within a telnet or gdb session using @option{debug_level
+<n>} @xref{debug_level}.
+
+You can redirect all output from the daemon to a file using the
+@option{-l <logfile>} switch.
Search paths for config/script files can be added to OpenOCD by using
-the @option{-s <search>} switch. The current directory and the OpenOCD target library
-is in the search path by default.
+the @option{-s <search>} switch. The current directory and the OpenOCD
+target library is in the search path by default.
-Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
-with the target. In general, it is possible for the JTAG controller to be unresponsive until
-the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
+Note! OpenOCD will launch the GDB & telnet server even if it can not
+establish a connection with the target. In general, it is possible for
+the JTAG controller to be unresponsive until the target is set up
+correctly via e.g. GDB monitor commands in a GDB init script.
-@node Configuration
-@chapter Configuration
+@node Simple Configuration Files
+@chapter Simple Configuration Files
@cindex configuration
-OpenOCD runs as a daemon, and reads it current configuration
-by default from the file openocd.cfg in the current directory. A different configuration
-file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
-The configuration file is used to specify on which ports the daemon listens for new
-connections, the JTAG interface used to connect to the target, the layout of the JTAG
-chain, the targets that should be debugged, and connected flashes.
+@section Outline
+There are 4 basic ways of ``configurating'' openocd to run, they are:
+
+@enumerate
+@item A small openocd.cfg file which ``sources'' other configuration files
+@item A monolithic openocd.cfg file
+@item Many -f filename options on the command line
+@item Your Mixed Solution
+@end enumerate
+
+@section Small configuration file method
+
+This is the prefered method, it is simple and is works well for many
+people. The developers of OpenOCD would encourage you to use this
+method. If you create a new configuration please email new
+configurations to the development list.
+
+Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
+
+@example
+source [find interface/signalyzer.cfg]
+
+# Change the default telnet port...
+telnet_port 4444
+# GDB connects here
+gdb_port 3333
+# GDB can also flash my flash!
+gdb_memory_map enable
+gdb_flash_program enable
+
+source [find target/sam7x256.cfg]
+@end example
+
+There are many example configuration scripts you can work with. You
+should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
+should find:
+
+@enumerate
+@item @b{board} - eval board level configurations
+@item @b{interface} - specific dongle configurations
+@item @b{target} - the target chips
+@item @b{tcl} - helper scripts
+@item @b{xscale} - things specific to the xscale.
+@end enumerate
+
+Look first in the ``boards'' area, then the ``targets'' area. Often a board
+configuration is a good example to work from.
+
+@section Many -f filename options
+Some believe this is a wonderful solution, others find it painful.
+
+You can use a series of ``-f filename'' options on the command line,
+OpenOCD will read each filename in sequence, for example:
+
+@example
+ openocd -f file1.cfg -f file2.cfg -f file2.cfg
+@end example
+
+You can also intermix various commands with the ``-c'' command line
+option.
+
+@section Monolithic file
+The ``Monolithic File'' dispenses with all ``source'' statements and
+puts everything in one self contained (monolithic) file. This is not
+encouraged.
+
+Please try to ``source'' various files or use the multiple -f
+technique.
+
+@section Advice for you
+Often, one uses a ``mixed approach''. Where possible, please try to
+``source'' common things, and if needed cut/paste parts of the
+standard distribution configuration files as needed.
+
+@b{REMEMBER:} The ``important parts'' of your configuration file are:
+
+@enumerate
+@item @b{Interface} - Defines the dongle
+@item @b{Taps} - Defines the JTAG Taps
+@item @b{GDB Targets} - What GDB talks to
+@item @b{Flash Programing} - Very Helpful
+@end enumerate
+
+Some key things you should look at and understand are:
+
+@enumerate
+@item The RESET configuration of your debug environment as a hole
+@item Is there a ``work area'' that that OpenOCD can use?
+@* For ARM - work areas mean up to 10x faster downloads.
+@item For MMU/MPU based ARM chips (ie: ARM9 and later) will that work area still be available?
+@item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
+@end enumerate
+
+
-@section Daemon configuration
+@node Config File Guidelines
+@chapter Config File Guidelines
+
+This section/chapter is aimed at developers and integrators of
+OpenOCD. These are guidelines for creating new boards and new target
+configurations as of 28/Nov/2008.
+
+However, you the user of OpenOCD should be some what familiar with
+this section as it should help explain some of the internals of what
+you might be looking at.
+
+The user should find under @t{$(INSTALLDIR)/lib/openocd} the
+following directories:
@itemize @bullet
-@item @b{init}
-@*This command terminates the configuration stage and enters the normal
-command mode. This can be useful to add commands to the startup scripts and commands
-such as resetting the target, programming flash, etc. To reset the CPU upon startup,
-add "init" and "reset" at the end of the config script or at the end of the
-OpenOCD command line using the @option{-c} command line switch.
+@item @b{interface}
+@*Think JTAG Dongle. Files that configure the jtag dongle go here.
+@item @b{board}
+@* Thing Circuit Board, PWA, PCB, they go by many names. Board files
+contain initialization items that are specific to a board - for
+example: The SDRAM initialization sequence for the board, or the type
+of external flash and what address it is found at. Any initialization
+sequence to enable that external flash or sdram should be found in the
+board file. Boards may also contain multiple targets, ie: Two cpus, or
+a CPU and an FPGA or CPLD.
+@item @b{target}
+@* Think CHIP. The ``target'' directory represents a jtag tap (or
+chip) OpenOCD should control, not a board. Two common types of targets
+are ARM chips and FPGA or CPLD chips.
+@end itemize
+
+@b{If needed...} The user in their ``openocd.cfg'' file or the board
+file might override a specific feature in any of the above files by
+setting a variable or two before sourcing the target file. Or adding
+various commands specific to their situation.
+
+@section Interface Config Files
+
+The user should be able to source one of these files via a command like this:
+
+@example
+ source [find interface/FOOBAR.cfg]
+Or:
+ openocd -f interface/FOOBAR.cfg
+@end example
+
+A preconfigured interface file should exist for every interface in use
+today, that said, perhaps some interfaces have only been used by the
+sole developer who created it.
+
+@b{FIXME/NOTE:} We need to add support for a variable like TCL variable
+tcl_platform(platform), it should be called jim_platform (because it
+is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
+``cygwin'' or ``mingw''
+
+Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
+
+@section Board Config Files
+
+@b{Note: BOARD directory NEW as of 28/nov/2008}
+
+The user should be able to source one of these files via a command like this:
+
+@example
+ source [find board/FOOBAR.cfg]
+Or:
+ openocd -f board/FOOBAR.cfg
+@end example
+
+
+The board file should contain one or more @t{source [find
+target/FOO.cfg]} statements along with any board specific things.
+
+In summery the board files should contain (if present)
+
+@enumerate
+@item External flash configuration (ie: the flash on CS0)
+@item SDRAM configuration (size, speed, etc)
+@item Board specific IO configuration (ie: GPIO pins might disable a 2nd flash)
+@item Multiple TARGET source statements
+@item All things that are not ``inside a chip''
+@item Things inside a chip go in a 'target' file
+@end enumerate
+
+@section Target Config Files
+
+The user should be able to source one of these files via a command like this:
+
+@example
+ source [find target/FOOBAR.cfg]
+Or:
+ openocd -f target/FOOBAR.cfg
+@end example
+
+In summery the target files should contain
+
+@enumerate
+@item Set Defaults
+@item Create Taps
+@item Reset Configuration
+@item Work Areas
+@item CPU/Chip/CPU-Core Specific features
+@item OnChip Flash
+@end enumerate
+
+@subsection Important variable names
+
+By default, the end user should never need to set these
+variables. However, if the user needs to override a setting they only
+need to set the variable in a simple way.
+
+@itemize @bullet
+@item @b{CHIPNAME}
+@* This gives a name to the overall chip, and is used as part of the
+tap identifier dotted name.
+@item @b{ENDIAN}
+@* By default little - unless the chip or board is not normally used that way.
+@item @b{CPUTAPID}
+@* When OpenOCD examines the JTAG chain, it will attempt to identify
+every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
+to verify the tap id number verses configuration file and may issue an
+error or warning like this. The hope is this will help pin point
+problem openocd configurations.
+
+@example
+Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
+Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
+Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
+@end example
+
+@item @b{_TARGETNAME}
+@* By convention, this variable is created by the target configuration
+script. The board configuration file may make use of this variable to
+configure things like a ``reset init'' script, or other things
+specific to that board and that target.
+
+If the chip has 2 targets, use the names @b{_TARGETNAME0},
+@b{_TARGETNAME1}, ... etc.
+
+@b{Remember:} The ``board file'' may include multiple targets.
+
+At no time should the name ``target0'' (the default target name if
+none was specified) be used. The name ``target0'' is a hard coded name
+- the next target on the board will be some other number.
+
+The user (or board file) should reasonably be able to:
+
+@example
+ source [find target/FOO.cfg]
+ $_TARGETNAME configure ... FOO specific parameters
+
+ source [find target/BAR.cfg]
+ $_TARGETNAME configure ... BAR specific parameters
+@end example
+
+@end itemize
+
+@subsection TCL Variables Guide Line
+The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
+
+Thus the rule we follow in OpenOCD is this: Variables that begin with
+a leading underscore are temporal in nature, and can be modified and
+used at will within a ?TARGET? configuration file
+
+@b{EXAMPLE:} The user should be able to do this:
+
+@example
+ # Board has 3 chips,
+ # PXA270 #1 network side, big endian
+ # PXA270 #2 video side, little endian
+ # Xilinx Glue logic
+ set CHIPNAME network
+ set ENDIAN big
+ source [find target/pxa270.cfg]
+ # variable: _TARGETNAME = network.cpu
+ # other commands can refer to the "network.cpu" tap.
+ $_TARGETNAME configure .... params for this cpu..
+
+ set ENDIAN little
+ set CHIPNAME video
+ source [find target/pxa270.cfg]
+ # variable: _TARGETNAME = video.cpu
+ # other commands can refer to the "video.cpu" tap.
+ $_TARGETNAME configure .... params for this cpu..
+
+ unset ENDIAN
+ set CHIPNAME xilinx
+ source [find target/spartan3.cfg]
+
+ # Since $_TARGETNAME is temporal..
+ # these names still work!
+ network.cpu configure ... params
+ video.cpu configure ... params
+
+@end example
+
+@subsection Default Value Boiler Plate Code
+
+All target configuration files should start with this (or a modified form)
+
+@example
+# SIMPLE example
+if @{ [info exists CHIPNAME] @} @{
+ set _CHIPNAME $CHIPNAME
+@} else @{
+ set _CHIPNAME sam7x256
+@}
+
+if @{ [info exists ENDIAN] @} @{
+ set _ENDIAN $ENDIAN
+@} else @{
+ set _ENDIAN little
+@}
+
+if @{ [info exists CPUTAPID ] @} @{
+ set _CPUTAPID $CPUTAPID
+@} else @{
+ set _CPUTAPID 0x3f0f0f0f
+@}
+
+@end example
+
+@subsection Creating Taps
+After the ``defaults'' are choosen, [see above], the taps are created.
+
+@b{SIMPLE example:} such as an Atmel AT91SAM7X256
+
+@example
+# for an ARM7TDMI.
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+@end example
+
+@b{COMPLEX example:}
+
+This is an SNIP/example for an STR912 - which has 3 internal taps. Key features shown:
+
+@enumerate
+@item @b{Unform tap names} - See: Tap Naming Convention
+@item @b{_TARGETNAME} is created at the end where used.
+@end enumerate
+
+@example
+if @{ [info exists FLASHTAPID ] @} @{
+ set _FLASHTAPID $FLASHTAPID
+@} else @{
+ set _FLASHTAPID 0x25966041
+@}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+if @{ [info exists CPUTAPID ] @} @{
+ set _CPUTAPID $CPUTAPID
+@} else @{
+ set _CPUTAPID 0x25966041
+@}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
+
+
+if @{ [info exists BSTAPID ] @} @{
+ set _BSTAPID $BSTAPID
+@} else @{
+ set _BSTAPID 0x1457f041
+@}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+@end example
+
+@b{Tap Naming Convention}
+
+See the command ``jtag newtap'' for detail, but in breif the names you should use are:
+
+@itemize @bullet
+@item @b{tap}
+@item @b{cpu}
+@item @b{flash}
+@item @b{bs}
+@item @b{jrc}
+@item @b{unknownN} - it happens :-(
+@end itemize
+
+@subsection Reset Configuration
+
+Some chips have specific ways the TRST and SRST signals are
+managed. If these are @b{CHIP SPECIFIC} they go here, if they are
+@b{BOARD SPECIFIC} they go in the board file.
+
+@subsection Work Areas
+
+Work areas are small RAM areas used by OpenOCD to speed up downloads,
+and to download small snippits of code to program flash chips.
+
+If the chip includes an form of ``on-chip-ram'' - and many do - define
+a reasonable work area and use the ``backup'' option.
+
+@b{PROBLEMS:} On more complex chips, this ``work area'' may become
+inaccessable if/when the application code enables or disables the MMU.
+
+@subsection ARM Core Specific Hacks
+
+If the chip has a DCC, enable it. If the chip is an arm9 with some
+special high speed download - enable it.
+
+If the chip has an ARM ``vector catch'' feature - by defeault enable
+it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
+user is really writing a handler for those situations - they can
+easily disable it. Experiance has shown the ``vector catch'' is
+helpful - for common programing errors.
+
+If present, the MMU, the MPU and the CACHE should be disabled.
+
+@subsection Internal Flash Configuration
+
+This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
+
+@b{Never ever} in the ``target configuration file'' define any type of
+flash that is external to the chip. (For example the BOOT flash on
+Chip Select 0). The BOOT flash information goes in a board file - not
+the TARGET (chip) file.
+
+Examples:
+@itemize @bullet
+@item at91sam7x256 - has 256K flash YES enable it.
+@item str912 - has flash internal YES enable it.
+@item imx27 - uses boot flash on CS0 - it goes in the board file.
+@item pxa270 - again - CS0 flash - it goes in the board file.
+@end itemize
+
+@node About JIM-Tcl
+@chapter About JIM-Tcl
+@cindex JIM Tcl
+@cindex tcl
+
+OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
+learn more about JIM here: @url{http://jim.berlios.de}
+
+@itemize @bullet
+@item @b{JIM vrs TCL}
+@* JIM-TCL is a stripped down version of the well known Tcl language,
+which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
+fewer features. JIM-Tcl is a single .C file and a single .H file and
+impliments the basic TCL command set along. In contrast: Tcl 8.6 is a
+4.2MEG zip file containing 1540 files.
+
+@item @b{Missing Features}
+@* Our practice has been: Add/clone the Real TCL feature if/when
+needed. We welcome JIM Tcl improvements, not bloat.
+
+@item @b{Scripts}
+@* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
+command interpretor today (28/nov/2008) is a mixture of (newer)
+JIM-Tcl commands, and (older) the orginal command interpretor.
+
+@item @b{Commands}
+@* At the openocd telnet command line (or via the GDB mon command) one
+can type a Tcl for() loop, set variables, etc.
+
+@item @b{Historical Note}
+@* JIM-Tcl was introduced to OpenOCD in Spring 2008.
+
+@item @b{Need a Crash Course In TCL?}
+@* See: @xref{TCL Crash Course}.
+@end itemize
+
+
+@node Daemon Configuration
+@chapter Daemon Configuration
+The commands here are commonly found inthe openocd.cfg file and are
+used to specify what TCP/IP ports are used, and how GDB should be
+supported.
+@section init
@cindex init
+This command terminates the configuration stage and
+enters the normal command mode. This can be useful to add commands to
+the startup scripts and commands such as resetting the target,
+programming flash, etc. To reset the CPU upon startup, add "init" and
+"reset" at the end of the config script or at the end of the OpenOCD
+command line using the @option{-c} command line switch.
+
+If this command does not appear in any startup/configuration file
+OpenOCD executes the command for you after processing all
+configuration files and/or command line options.
+
+@b{NOTE:} This command normally occurs at or near the end of your
+openocd.cfg file to force OpenOCD to ``initialize'' and make the
+targets ready. For example: If your openocd.cfg file needs to
+read/write memory on your target - the init command must occur before
+the memory read/write commands.
+
+@section TCP/IP Ports
+@itemize @bullet
@item @b{telnet_port} <@var{number}>
@cindex telnet_port
-@*Port on which to listen for incoming telnet connections
+@*Intended for a human. Port on which to listen for incoming telnet connections.
+
@item @b{tcl_port} <@var{number}>
@cindex tcl_port
-@*Port on which to listen for incoming TCL syntax. This port is intended as
-a simplified RPC connection that can be used by clients to issue commands
-and get the output from the TCL engine.
+@*Intended as a machine interface. Port on which to listen for
+incoming TCL syntax. This port is intended as a simplified RPC
+connection that can be used by clients to issue commands and get the
+output from the TCL engine.
+
@item @b{gdb_port} <@var{number}>
@cindex gdb_port
@*First port on which to listen for incoming GDB connections. The GDB port for the
first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
+@end itemize
+
+@section GDB Items
+@itemize @bullet
@item @b{gdb_breakpoint_override} <@var{hard|soft|disabled}>
@cindex gdb_breakpoint_override
@anchor{gdb_breakpoint_override}
This option replaces older arm7_9 target commands that addressed
the same issue.
+
@item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
@cindex gdb_detach
@*Configures what OpenOCD will do when gdb detaches from the daeman.
Default behaviour is <@var{resume}>
+
@item @b{gdb_memory_map} <@var{enable|disable}>
@cindex gdb_memory_map
@*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
for flash programming to work.
Default behaviour is <@var{enable}>
@xref{gdb_flash_program}.
+
@item @b{gdb_flash_program} <@var{enable|disable}>
@cindex gdb_flash_program
@anchor{gdb_flash_program}
@*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
vFlash packet is received.
Default behaviour is <@var{enable}>
+@comment END GDB Items
@end itemize
-@section JTAG interface configuration
+@node Interface - Dongle Configuration
+@chapter Interface - Dongle Configuration
+Interface commands are normally found in an interface configuration
+file which is sourced by your openocd.cfg file. These commands tell
+OpenOCD what type of JTAG dongle you have and how to talk to it.
+@section Simple Complete Interface Examples
+@b{A Turtelizer FT2232 Based JTAG Dongle}
+@verbatim
+#interface
+interface ft2232
+ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
+ft2232_layout turtelizer2
+ft2232_vid_pid 0x0403 0xbdc8
+@end verbatim
+@b{A SEGGER Jlink}
+@verbatim
+# jlink interface
+interface jlink
+@end verbatim
+@b{Parallel Port}
+@verbatim
+interface parport
+parport_port 0xc8b8
+parport_cable wiggler
+jtag_speed 0
+@end verbatim
+@section Interface Conmmand
+
+The interface command tells OpenOCD what type of jtag dongle you are
+using. Depending upon the type of dongle, you may need to have one or
+more additional commands.
@itemize @bullet
+
@item @b{interface} <@var{name}>
@cindex interface
-@*Use the interface driver <@var{name}> to connect to the target. Currently supported
-interfaces are
+@*Use the interface driver <@var{name}> to connect to the
+target. Currently supported interfaces are
+
@itemize @minus
+
@item @b{parport}
-PC parallel port bit-banging (Wigglers, PLD download cable, ...)
-@end itemize
-@itemize @minus
+@* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
+
@item @b{amt_jtagaccel}
-Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
+@* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
mode parallel port
-@end itemize
-@itemize @minus
+
@item @b{ft2232}
-FTDI FT2232 based devices using either the open-source libftdi or the binary only
+@* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
FTD2XX driver. The FTD2XX is superior in performance, but not available on every
platform. The libftdi uses libusb, and should be portable to all systems that provide
libusb.
-@end itemize
-@itemize @minus
+
@item @b{ep93xx}
-Cirrus Logic EP93xx based single-board computer bit-banging (in development)
-@end itemize
-@itemize @minus
+@*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
+
@item @b{presto}
-ASIX PRESTO USB JTAG programmer.
-@end itemize
-@itemize @minus
+@* ASIX PRESTO USB JTAG programmer.
+
@item @b{usbprog}
-usbprog is a freely programmable USB adapter.
-@end itemize
-@itemize @minus
+@* usbprog is a freely programmable USB adapter.
+
@item @b{gw16012}
-Gateworks GW16012 JTAG programmer.
-@end itemize
-@itemize @minus
+@* Gateworks GW16012 JTAG programmer.
+
@item @b{jlink}
-Segger jlink usb adapter
+@* Segger jlink usb adapter
+@comment - End parameters
@end itemize
+@comment - End Interface
@end itemize
+@subsection parport options
@itemize @bullet
-@item @b{jtag_speed} <@var{reset speed}>
-@cindex jtag_speed
-@*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
-speed. The actual effect of this option depends on the JTAG interface used.
-
-The speed used during reset can be adjusted using setting jtag_speed during
-pre_reset and post_reset events.
-@itemize @minus
-
-@item wiggler: maximum speed / @var{number}
-@item ft2232: 6MHz / (@var{number}+1)
-@item amt jtagaccel: 8 / 2**@var{number}
-@item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
-@end itemize
-
-Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
-especially true for synthesized cores (-S).
-
-@item @b{jtag_khz} <@var{reset speed kHz}>
-@cindex jtag_khz
-@*Same as jtag_speed, except that the speed is specified in maximum kHz. If
-the device can not support the rate asked for, or can not translate from
-kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
-is not supported, then an error is reported.
-
-@item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
-@cindex reset_config
-@*The configuration of the reset signals available on the JTAG interface AND the target.
-If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
-then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
-@option{srst_only} or @option{trst_and_srst}.
-
-[@var{combination}] is an optional value specifying broken reset signal implementations.
-@option{srst_pulls_trst} states that the testlogic is reset together with the reset of
-the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
-that the system is reset together with the test logic (only hypothetical, I haven't
-seen hardware with such a bug, and can be worked around).
-@option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
-The default behaviour if no option given is @option{separate}.
-
-The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
-reset lines to be specified. Possible values are @option{trst_push_pull} (default)
-and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
-(default) and @option{srst_push_pull} for the system reset. These values only affect
-JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
-
-@item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
-@cindex jtag_device
-@*Describes the devices that form the JTAG daisy chain, with the first device being
-the one closest to TDO. The parameters are the length of the instruction register
-(4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
-of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
-The IDCODE instruction will in future be used to query devices for their JTAG
-identification code. This line is the same for all ARM7 and ARM9 devices.
-Other devices, like CPLDs, require different parameters. An example configuration
-line for a Xilinx XC9500 CPLD would look like this:
-@smallexample
-jtag_device 8 0x01 0x0e3 0xfe
-@end smallexample
-The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
-the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
-The IDCODE instruction is 0xfe.
-
-@item @b{jtag_nsrst_delay} <@var{ms}>
-@cindex jtag_nsrst_delay
-@*How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
-starting new JTAG operations.
-@item @b{jtag_ntrst_delay} <@var{ms}>
-@cindex jtag_ntrst_delay
-@*Same @b{jtag_nsrst_delay}, but for nTRST
-
-The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
-or on-chip features) keep a reset line asserted for some time after the external reset
-got deasserted.
-@end itemize
-
-@section parport options
-
-@itemize @bullet
-@item @b{parport_port} <@var{number}>
-@cindex parport_port
-@*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
-the @file{/dev/parport} device
+@item @b{parport_port} <@var{number}>
+@cindex parport_port
+@*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
+the @file{/dev/parport} device
When using PPDEV to access the parallel port, use the number of the parallel port:
@option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
interface on exiting OpenOCD
@end itemize
-@section amt_jtagaccel options
+@subsection amt_jtagaccel options
@itemize @bullet
@item @b{parport_port} <@var{number}>
@cindex parport_port
@*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
@file{/dev/parport} device
@end itemize
-@section ft2232 options
+@subsection ft2232 options
@itemize @bullet
@item @b{ft2232_device_desc} <@var{description}>
@cindex ft2232_device_desc
-@*The USB device description of the FTDI FT2232 device. If not specified, the FTDI
-default value is used. This setting is only valid if compiled with FTD2XX support.
+@*The USB device description of the FTDI FT2232 device. If not
+specified, the FTDI default value is used. This setting is only valid
+if compiled with FTD2XX support.
+
+@b{TODO:} Confirm the following: On windows the name needs to end with
+a ``space A''? Or not? It has to do with the FTD2xx driver. When must
+this be added and when must it not be added? Why can't the code in the
+interface or in openocd automatically add this if needed? -- Duane.
+
@item @b{ft2232_serial} <@var{serial-number}>
@cindex ft2232_serial
@*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
@item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
@*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
-@smallexample
+@example
ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
-@end smallexample
+@end example
@item @b{ft2232_latency} <@var{ms}>
@*On some systems using ft2232 based JTAG interfaces the FT_Read function call in
ft2232_read() fails to return the expected number of bytes. This can be caused by
The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
@end itemize
-@section ep93xx options
+@subsection ep93xx options
@cindex ep93xx options
Currently, there are no options available for the ep93xx interface.
-@page
-@section Target configuration
-
+@section JTAG Speed
@itemize @bullet
-@item @b{target} <@var{type}> <@var{endianess}> <@var{JTAG pos}>
-<@var{variant}>
-@cindex target
-@*Defines a target that should be debugged. Currently supported types are:
-@itemize @minus
-@item @b{arm7tdmi}
-@item @b{arm720t}
-@item @b{arm9tdmi}
-@item @b{arm920t}
-@item @b{arm922t}
-@item @b{arm926ejs}
-@item @b{arm966e}
-@item @b{cortex_m3}
-@item @b{feroceon}
-@item @b{xscale}
-@item @b{arm11}
-@item @b{mips_m4k}
-@end itemize
+@item @b{jtag_khz} <@var{reset speed kHz}>
+@cindex jtag_khz
-If you want to use a target board that is not on this list, see Adding a new
-target board.
-The @option{target types} command can be used to get the list of targets supported from within openocd.
+It is debatable if this command belongs here - or in a board
+configuration file. In fact, in some situations the jtag speed is
+changed during the target initialization process (ie: (1) slow at
+reset, (2) program the cpu clocks, (3) run fast)
-Endianess may be @option{little} or @option{big}.
+Speed 0 (khz) selects RTCK method. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
-@item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
-@cindex target_script
-@*Event is one of the following:
-@option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
-@option{pre_resume} or @option{gdb_program_config}.
-@option{post_reset} and @option{reset} will produce the same results.
+Not all interfaces support ``rtck''. If the interface device can not
+support the rate asked for, or can not translate from kHz to
+jtag_speed, then an error is returned.
-@item @b{working_area} <@var{target#}> <@var{address}> <@var{size}> <@var{backup}|@var{nobackup}> [@option{virtual address}]
-@cindex working_area
-@*Specifies a working area for the debugger to use. This may be used to speed-up
-downloads to target memory and flash operations, or to perform otherwise unavailable
-operations (some coprocessor operations on ARM7/9 systems, for example). The last
-parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
-a working_area that doesn't need to be backed up, as performing a backup slows down operation.
-@end itemize
-
-@subsection arm7tdmi options
-@cindex arm7tdmi options
-target arm7tdmi <@var{endianess}> <@var{jtag#}>
-@*The arm7tdmi target definition requires at least one additional argument, specifying
-the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
-The optional [@var{variant}] parameter has been removed in recent versions.
-The correct feature set is determined at runtime.
-
-@subsection arm720t options
-@cindex arm720t options
-ARM720t options are similar to ARM7TDMI options.
-
-@subsection arm9tdmi options
-@cindex arm9tdmi options
-ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
-@option{arm920t}, @option{arm922t} and @option{arm940t}.
-This enables the hardware single-stepping support found on these cores.
-
-@subsection arm920t options
-@cindex arm920t options
-ARM920t options are similar to ARM9TDMI options.
-
-@subsection arm966e options
-@cindex arm966e options
-ARM966e options are similar to ARM9TDMI options.
-
-@subsection cortex_m3 options
-@cindex cortex_m3 options
-use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
-openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
-the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
-be detected and the normal reset behaviour used.
+Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
+especially true for synthesized cores (-S). Also see RTCK.
-@subsection xscale options
-@cindex xscale options
-Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
-@option{pxa250}, @option{pxa255}, @option{pxa26x}.
+@b{NOTE: Script writers} If the target chip requires/uses RTCK -
+please use the command: 'jtag_rclk FREQ'. This TCL proc (in
+startup.tcl) attempts to enable RTCK, if that fails it falls back to
+the specified frequency.
-@subsection arm11 options
-@cindex arm11 options
+@example
+ # Fall back to 3mhz if RCLK is not supported
+ jtag_rclk 3000
+@end example
-@subsection mips_m4k options
-@cindex mips_m4k options
-Use variant @option{ejtag_srst} when debugging targets that
-do not provide a functional SRST line on the EJTAG connector.
-This causes openocd to instead use an EJTAG software reset command to reset the processor.
-You still need to enable @option{srst} on the reset configuration command to enable openocd hardware reset functionality.
+@item @b{DEPRICATED} @b{jtag_speed} - please use jtag_khz above.
+@cindex jtag_speed
+@*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
+speed. The actual effect of this option depends on the JTAG interface used.
-@section Flash configuration
-@cindex Flash configuration
+The speed used during reset can be adjusted using setting jtag_speed during
+pre_reset and post_reset events.
+@itemize @minus
-@itemize @bullet
-@item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
-<@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
-@cindex flash bank
-@*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
-and <@var{bus_width}> bytes using the selected flash <driver>.
+@item wiggler: maximum speed / @var{number}
+@item ft2232: 6MHz / (@var{number}+1)
+@item amt jtagaccel: 8 / 2**@var{number}
+@item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
+@comment end speed list.
@end itemize
-@subsection lpc2000 options
-@cindex lpc2000 options
+@comment END command list
+@end itemize
-@b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
-<@var{clock}> [@var{calc_checksum}]
-@*LPC flashes don't require the chip and bus width to be specified. Additional
-parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
-or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
-of the target this flash belongs to (first is 0), the frequency at which the core
-is currently running (in kHz - must be an integral number), and the optional keyword
-@var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
-vector table.
+@node Reset Configuration
+@chapter Reset Configuration
+@cindex reset configuration
-@subsection cfi options
-@cindex cfi options
+Every system configuration may require a different reset
+configuration. This can also be quite confusing. Please see the
+various board files for example.
-@b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
-<@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
-@*CFI flashes require the number of the target they're connected to as an additional
-argument. The CFI driver makes use of a working area (specified for the target)
-to significantly speed up operation.
+@section jtag_nsrst_delay <@var{ms}>
+@cindex jtag_nsrst_delay
+@*How long (in milliseconds) OpenOCD should wait after deasserting
+nSRST before starting new JTAG operations.
-@var{chip_width} and @var{bus_width} are specified in bytes.
+@section jtag_ntrst_delay <@var{ms}>
+@cindex jtag_ntrst_delay
+@*Same @b{jtag_nsrst_delay}, but for nTRST
-The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
+The jtag_n[st]rst_delay options are useful if reset circuitry (like a
+big resistor/capacitor, reset supervisor, or on-chip features). This
+keeps the signal asserted for some time after the external reset got
+deasserted.
-@var{x16_as_x8} ???
+@section reset_config
-@subsection at91sam7 options
-@cindex at91sam7 options
+@b{Note:} To maintainer types and integrators. Where exactly the
+``reset configuration'' goes is a good question. It touches several
+things at once. In the end, if you have a board file - the board file
+should define it and assume 100% that the DONGLE supports
+anything. However, that does not mean the target should not also make
+not of something the silicon vendor has done inside the
+chip. @i{Grr.... nothing is every pretty.}
-@b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
-@*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
-reading the chip-id and type.
+@* @b{Problems:}
+@enumerate
+@item Every JTAG Dongle is slightly different, some dongles impliment reset differently.
+@item Every board is also slightly different; some boards tie TRST and SRST together.
+@item Every chip is slightly different; some chips internally tie the two signals together.
+@item Some may not impliment all of the signals the same way.
+@item Some signals might be push-pull, others open-drain/collector.
+@end enumerate
+@b{Best Case:} OpenOCD can hold the SRST (push-button-reset), then
+reset the TAP via TRST and send commands through the JTAG tap to halt
+the CPU at the reset vector before the 1st instruction is executed,
+and finally release the SRST signal.
+@*Depending upon your board vendor, your chip vendor, etc, these
+signals may have slightly different names.
+
+OpenOCD defines these signals in these terms:
+@itemize @bullet
+@item @b{TRST} - is Tap Reset - and should reset only the TAP.
+@item @b{SRST} - is System Reset - typically equal to a reset push button.
+@end itemize
-@subsection str7 options
-@cindex str7 options
+The Command:
-@b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
-@*variant can be either STR71x, STR73x or STR75x.
+@itemize @bullet
+@item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
+@cindex reset_config
+@* The @t{reset_config} command tells OpenOCD the reset configuration
+of your combination of Dongle, Board, and Chips.
+If the JTAG interface provides SRST, but the target doesn't connect
+that signal properly, then OpenOCD can't use it. <@var{signals}> can
+be @option{none}, @option{trst_only}, @option{srst_only} or
+@option{trst_and_srst}.
+
+[@var{combination}] is an optional value specifying broken reset
+signal implementations. @option{srst_pulls_trst} states that the
+testlogic is reset together with the reset of the system (e.g. Philips
+LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
+the system is reset together with the test logic (only hypothetical, I
+haven't seen hardware with such a bug, and can be worked around).
+@option{combined} imples both @option{srst_pulls_trst} and
+@option{trst_pulls_srst}. The default behaviour if no option given is
+@option{separate}.
+
+The [@var{trst_type}] and [@var{srst_type}] parameters allow the
+driver type of the reset lines to be specified. Possible values are
+@option{trst_push_pull} (default) and @option{trst_open_drain} for the
+test reset signal, and @option{srst_open_drain} (default) and
+@option{srst_push_pull} for the system reset. These values only affect
+JTAG interfaces with support for different drivers, like the Amontec
+JTAGkey and JTAGAccelerator.
+
+@comment - end command
+@end itemize
-@subsection str9 options
-@cindex str9 options
-@b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*The str9 needs the flash controller to be configured prior to Flash programming, eg.
-@smallexample
-str9x flash_config 0 4 2 0 0x80000
-@end smallexample
-This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
-@subsection str9 options (str9xpec driver)
+@node Tap Creation
+@chapter Tap Creation
+@cindex tap creation
+@cindex tap configuration
-@b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*Before using the flash commands the turbo mode will need enabling using str9xpec
-@option{enable_turbo} <@var{num>.}
+In order for OpenOCD to control a target, a JTAG tap must be
+defined/created.
-Only use this driver for locking/unlocking the device or configuring the option bytes.
-Use the standard str9 driver for programming.
+Commands to create taps are normally found in a configuration file and
+are not normally typed by a human.
-@subsection stellaris (LM3Sxxx) options
-@cindex stellaris (LM3Sxxx) options
+When a tap is created a @b{dotted.name} is created for the tap. Other
+commands use that dotted.name to manipulate or refer to the tap.
-@b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*stellaris flash plugin only require the @var{target#}.
+Tap Uses:
+@itemize @bullet
+@item @b{Debug Target} A tap can be used by a GDB debug target
+@item @b{Flash Programing} Some chips program the flash via JTAG
+@item @b{Boundry Scan} Some chips support boundry scan.
+@end itemize
-@subsection stm32x options
-@cindex stm32x options
-@b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*stm32x flash plugin only require the @var{target#}.
+@section jtag newtap
+@b{@t{jtag newtap CHIPNAME TAPNAME configparams ....}}
+@cindex jtag_device
+@cindex jtag newtap
+@cindex tap
+@cindex tap order
+@cindex tap geometry
-@subsection aduc702x options
-@cindex aduc702x options
+@comment START options
+@itemize @bullet
+@item @b{CHIPNAME}
+@* is a symbolic name of the chip.
+@item @b{TAPNAME}
+@* is a symbol name of a tap present on the chip.
+@item @b{Required configparams}
+@* Every tap has 3 required configparams, and several ``optional
+parameters'', the required parameters are:
+@comment START REQUIRED
+@itemize @bullet
+@item @b{-irlen NUMBER} - the length in bits of the instruction register
+@item @b{-ircapture NUMBER} - the ID code capture command.
+@item @b{-irmask NUMBER} - the corrisponding mask for the ir register.
+@comment END REQUIRED
+@end itemize
+An example of a FOOBAR Tap
+@example
+jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
+@end example
+Creates the tap ``foobar.tap'' with the instruction register (IR) is 7
+bits long, during Capture-IR 0x42 is loaded into the IR, and bits
+[6,4,2,0] are checked.
+
+FIXME: The IDCODE - this was not used in the old code, it should be?
+Right? -Duane.
+@item @b{Optional configparams}
+@comment START Optional
+@itemize @bullet
+@item @b{-expected-id NUMBER}
+@* By default it is zero. If non-zero represents the
+expected tap ID used when the Jtag Chain is examined. See below.
+@item @b{-disable}
+@item @b{-enable}
+@* By default not specified the tap is enabled. Some chips have a
+jtag route controller (JRC) that is used to enable and/or disable
+specific jtag taps. You can later enable or disable any JTAG tap via
+the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
+DOTTED.NAME}
+@comment END Optional
+@end itemize
-@b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
+@comment END OPTIONS
+@end itemize
+@b{Notes:}
+@comment START NOTES
+@itemize @bullet
+@item @b{Technically}
+@* newtap is a sub command of the ``jtag'' command
+@item @b{Big Picture Background}
+@*GDB Talks to OpenOCD using the GDB protocol via
+tcpip. OpenOCD then uses the JTAG interface (the dongle) to
+control the JTAG chain on your board. Your board has one or more chips
+in a @i{daisy chain configuration}. Each chip may have one or more
+jtag taps. GDB ends up talking via OpenOCD to one of the taps.
+@item @b{NAME Rules}
+@*Names follow ``C'' symbol name rules (start with alpha ...)
+@item @b{TAPNAME - Conventions}
+@itemize @bullet
+@item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
+@item @b{cpu} - the main cpu of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
+@item @b{flash} - if the chip has a flash tap, example: str912.flash
+@item @b{bs} - for boundary scan if this is a seperate tap.
+@item @b{jrc} - for jtag route controller (example: OMAP3530 found on Beagleboards)
+@item @b{unknownN} - where N is a number if you have no idea what the tap is for
+@item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
+@item @b{When in doubt} - use the chip makers name in their data sheet.
+@end itemize
+@item @b{DOTTED.NAME}
+@* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
+@b{Dotted.Name} is the @b{CHIPNAME} and @b{TAPNAME} combined with a
+dot (period); for example: @b{xilinx.tap}, @b{str912.flash},
+@b{omap3530.jrc}, or @b{stm32.cpu} The @b{dotted.name} is used in
+numerous other places to refer to various taps.
+@item @b{ORDER}
+@* The order this command appears via the config files is
+important.
+@item @b{Multi Tap Example}
+@* This example is based on the ST Microsystems STR912. See the ST
+document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
+28/102, Figure 3: Jtag chaining inside the STR91xFA}.
+
+@url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
+@*@b{checked: 28/nov/2008}
+
+The diagram shows the TDO pin connects to the flash tap, flash TDI
+connects to the CPU debug tap, CPU TDI connects to the boundary scan
+tap which then connects to the TDI pin.
+
+@example
+ # The order is...
+ # create tap: 'str912.flash'
+ jtag newtap str912 flash ... params ...
+ # create tap: 'str912.cpu'
+ jtag newtap str912 cpu ... params ...
+ # create tap: 'str912.bs'
+ jtag newtap str912 bs ... params ...
+@end example
+
+@item @b{Note: Deprecated} - Index Numbers
+@* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
+feature is still present, however its use is highly discouraged and
+should not be counted upon.
+@item @b{Multiple chips}
+@* If your board has multiple chips, you should be
+able to @b{source} two configuration files, in the proper order, and
+have the taps created in the proper order.
+@comment END NOTES
+@end itemize
+@comment at command level
+@comment DOCUMENT old command
+@section jtag_device - REMOVED
+@example
+@b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
+@end example
+@cindex jtag_device
-@section mFlash configuration
-@cindex mFlash configuration
+@* @b{Removed: 28/nov/2008} This command has been removed and replaced
+by the ``jtag newtap'' command. The documentation remains here so that
+one can easily convert the old syntax to the new syntax. About the old
+syntax: The old syntax is positional, ie: The 4th parameter is the
+``irmask'' The new syntax requires named prefixes, and supports
+additional options, for example ``-irmask 4'' Please refer to the
+@b{jtag newtap} command for deails.
+@example
+OLD: jtag_device 8 0x01 0x0e3 0xfe
+NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0xe3 -irmask 0xfe
+@end example
+
+@section Enable/Disable Taps
+@b{Note:} These commands are intended to be used as a machine/script
+interface. Humans might find the ``scan_chain'' command more helpful
+when querying the state of the JTAG taps.
+
+@b{By default, all taps are enabled}
@itemize @bullet
-@item @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
-<@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target #}>
-@cindex mflash bank
-@*Configures a mflash for <@var{soc}> host bank at <@var{base}>. <@var{chip_width}> and
-<@var{bus_width}> are bytes order. Pin number format is dependent on host GPIO calling convention.
-If WP or DPD pin was not used, write -1. Currently, mflash bank support s3c2440 and pxa270.
+@item @b{jtag tapenable} @var{DOTTED.NAME}
+@item @b{jtag tapdisable} @var{DOTTED.NAME}
+@item @b{jtag tapisenabled} @var{DOTTED.NAME}
@end itemize
-(ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
-@smallexample
-mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
-@end smallexample
-(ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
-@smallexample
-mflash bank pxa270 0x08000000 2 2 43 -1 51 0
-@end smallexample
-
-@node Target library
-@chapter Target library
-@cindex Target library
+@cindex tap enable
+@cindex tap disable
+@cindex JRC
+@cindex route controller
-OpenOCD comes with a target configuration script library. These scripts can be
-used as-is or serve as a starting point.
+These commands are used when your target has a JTAG Route controller
+that effectively adds or removes a tap from the jtag chain in a
+non-standard way.
-The target library is published together with the openocd executable and
-the path to the target library is in the OpenOCD script search path.
-Similarly there are example scripts for configuring the JTAG interface.
+The ``standard way'' to remove a tap would be to place the tap in
+bypass mode. But with the advent of modern chips, this is not always a
+good solution. Some taps operate slowly, others operate fast, and
+there are other JTAG clock syncronization problems one must face. To
+solve that problem, the JTAG Route controller was introduced. Rather
+then ``bypass'' the tap, the tap is completely removed from the
+circuit and skipped.
-The command line below uses the example parport configuration scripts
-that ship with OpenOCD, then configures the str710.cfg target and
-finally issues the init and reset command. The communication speed
-is set to 10kHz for reset and 8MHz for post reset.
+From OpenOCDs view point, a JTAG TAP is in one of 3 states:
-@smallexample
-openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
-@end smallexample
+@itemize @bullet
+@item @b{Enabled - Not In ByPass} and has a variable bit length
+@item @b{Enabled - In ByPass} and has a length of exactly 1 bit.
+@item @b{Disabled} and has a length of ZERO and is removed from the circuit.
+@end itemize
+The IEEE JTAG definition has no concept of a ``disabled'' tap.
+@b{Historical note:} this feature was added 28/nov/2008
-To list the target scripts available:
+@b{jtag tapisenabled DOTTED.NAME}
-@smallexample
-$ ls /usr/local/lib/openocd/target
+This command return 1 if the named tap is currently enabled, 0 if not.
+This command exists so that scripts that manipulate a JRC (like the
+Omap3530 has) can determine if OpenOCD thinks a tap is presently
+enabled, or disabled.
-arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
-at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
-at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
-at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
-@end smallexample
+@page
+@node Target Configuration
+@chapter Target Configuration
+This chapter discusses how to create a GDB Debug Target. Before
+creating a ``target'' a JTAG Tap DOTTED.NAME must exist first.
-@node Commands
-@chapter Commands
-@cindex commands
+@section targets [NAME]
+@b{Note:} This command name is PLURAL - not singular.
+
+With NO parameter, this pural @b{targets} command lists all known
+targets in a human friendly form.
-OpenOCD allows user interaction through a GDB server (default: port 3333),
-a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter
-is available from both the telnet interface and a GDB session. To issue commands to the
-interpreter from within a GDB session, use the @option{monitor} command, e.g. use
-@option{monitor poll} to issue the @option{poll} command. All output is relayed through the
-GDB session.
+With a parameter, this pural @b{targets} command sets the current
+target to the given name. (ie: If there are multiple debug targets)
+
+Example:
+@verbatim
+(gdb) mon targets
+ CmdName Type Endian ChainPos State
+-- ---------- ---------- ---------- -------- ----------
+ 0: target0 arm7tdmi little 0 halted
+@end verbatim
-The TCL interface is used as a simplified RPC mechanism that feeds all the
-input into the TCL interpreter and returns the output from the evaluation of
-the commands.
+@section target COMMANDS
+@b{Note:} This command name is SINGULAR - not plural. It is used to
+manipulate specific targets, to create targets and other things.
-@section Daemon
+Once a target is created, a TARGETNAME (object) command is created;
+see below for details.
+The TARGET command accepts these sub-commands:
@itemize @bullet
-@item @b{sleep} <@var{msec}>
-@cindex sleep
-@*Wait for n milliseconds before resuming. Useful in connection with script files
-(@var{script} command and @var{target_script} configuration).
+@item @b{create} .. parameters ..
+@* creates a new target, See below for details.
+@item @b{types}
+@* Lists all supported target types (perhaps some are not yet in this document).
+@item @b{names}
+@* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
+@verbatim
+ foreach t [target names] {
+ puts [format "Target: %s\n" $t]
+ }
+@end verbatim
+@item @b{current}
+@* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
+By default, commands like: ``mww'' (used to write memory) operate on the current target.
+@item @b{number} @b{NUMBER}
+@* Internally OpenOCD maintains a list of targets - in numerical index
+(0..N-1) this command returns the name of the target at index N.
+Example usage:
+@verbatim
+ set thename [target number $x]
+ puts [format "Target %d is: %s\n" $x $thename]
+@end verbatim
+@item @b{count}
+@* Returns the number of targets known to OpenOCD (see number above)
+Example:
+@verbatim
+ set c [target count]
+ for { set x 0 } { $x < $c } { incr x } {
+ # Assuming you have created this function
+ print_target_details $x
+ }
+@end verbatim
-@item @b{shutdown}
-@cindex shutdown
-@*Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
+@end itemize
-@item @b{debug_level} [@var{n}]
-@cindex debug_level
-@anchor{debug_level}
-@*Display or adjust debug level to n<0-3>
+@section TARGETNAME (object) commands
+@b{Use:} Once a target is created, an ``object name'' that represents the
+target is created. By convention, the target name is identical to the
+tap name. In a multiple target system, one can preceed many common
+commands with a specific target name and effect only that target.
+@example
+ str912.cpu mww 0x1234 0x42
+ omap3530.cpu mww 0x5555 123
+@end example
+
+@b{Model:} The Tcl/Tk language has the concept of object commands. A
+good example is a on screen button, once a button is created a button
+has a name (a path in TK terms) and that name is useable as a 1st
+class command. For example in TK, one can create a button and later
+configure it like this:
+
+@example
+ # Create
+ button .foobar -background red -command @{ foo @}
+ # Modify
+ .foobar configure -foreground blue
+ # Query
+ set x [.foobar cget -background]
+ # Report
+ puts [format "The button is %s" $x]
+@end example
+
+In OpenOCDs terms, the ``target'' is an object just like a Tcl/Tk
+button. Commands avaialble as a ``target object'' are:
+
+@comment START targetobj commands.
+@itemize @bullet
+@item @b{configure} - configure the target; see Target Config/Cget Options below
+@item @b{cget} - query the target configuration; see Target Config/Cget Options below
+@item @b{curstate} - current target state (running, halt, etc)
+@item @b{eventlist}
+@* Intended for a human to see/read the currently configure target events.
+@item @b{Various Memory Commands} See the ``mww'' command elsewhere.
+@comment start memory
+@itemize @bullet
+@item @b{mww} ...
+@item @b{mwh} ...
+@item @b{mwb} ...
+@item @b{mdw} ...
+@item @b{mdh} ...
+@item @b{mdb} ...
+@comment end memory
+@end itemize
+@item @b{Memory To Array, Array To Memory}
+@* These are aimed at a machine interface to memory
+@itemize @bullet
+@item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
+@item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
+@* Where:
+@* @b{ARRAYNAME} is the name of an array variable
+@* @b{WIDTH} is 8/16/32 - indicating the memory access size
+@* @b{ADDRESS} is the target memory address
+@* @b{COUNT} is the number of elements to process
+@end itemize
+@item @b{Used during ``reset''}
+@* These commands are used internally by the OpenOCD scripts to deal
+with odd reset situations and are not documented here.
+@itemize @bullet
+@item @b{arp_examine}
+@item @b{arp_poll}
+@item @b{arp_reset}
+@item @b{arp_halt}
+@item @b{arp_waitstate}
+@end itemize
+@item @b{invoke-event} @b{EVENT-NAME}
+@* Invokes the specific event manually for the target
+@end itemize
-@item @b{fast} [@var{enable|disable}]
-@cindex fast
-@*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
-downloads and fast memory access will work if the JTAG interface isn't too fast and
-the core doesn't run at a too low frequency. Note that this option only changes the default
-and that the indvidual options, like DCC memory downloads, can be enabled and disabled
-individually.
+@section Target Events
+At various times, certian things happen, or you want to happen.
-The target specific "dangerous" optimisation tweaking options may come and go
-as more robust and user friendly ways are found to ensure maximum throughput
-and robustness with a minimum of configuration.
+Examples:
+@itemize @bullet
+@item What should happen when GDB connects? Should your target reset?
+@item When GDB tries to flash the target, do you need to enable the flash via a special command?
+@item During reset, do you need to write to certian memory locations to reconfigure the SDRAM?
+@end itemize
-Typically the "fast enable" is specified first on the command line:
+All of the above items are handled by target events.
-@smallexample
-openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
-@end smallexample
+To specify an event action, either during target creation, or later
+via ``$_TARGETNAME configure'' see this example.
-@item @b{log_output} <@var{file}>
-@cindex log_output
-@*Redirect logging to <file> (default: stderr)
+Syntactially, the option is: ``-event NAME BODY'' where NAME is a
+target event name, and BODY is a tcl procedure or string of commands
+to execute.
-@item @b{script} <@var{file}>
-@cindex script
-@*Execute commands from <file>
+The programers model is the: ``-command'' option used in Tcl/Tk
+buttons and events. Below are two identical examples, the first
+creates and invokes small procedure. The second inlines the procedure.
-@end itemize
+@example
+ proc my_attach_proc @{ @} @{
+ puts "RESET...."
+ reset halt
+ @}
+ mychip.cpu configure -event gdb-attach my_attach_proc
+ mychip.cpu configure -event gdb-attach @{ puts "Reset..." ; reset halt @}
+@end example
+
+Current Events
-@subsection Target state handling
@itemize @bullet
-@item @b{power} <@var{on}|@var{off}>
-@cindex reg
-@*Turn power switch to target on/off.
-No arguments: print status.
+@item @b{debug-halted}
+@* The target has halted for debug reasons (ie: breakpoint)
+@item @b{debug-resumed}
+@* The target has resumed (ie: gdb said run)
+@item @b{early-halted}
+@* Occurs early in the halt process
+@item @b{examine-end}
+@* Currently not used (goal: when JTAG examine completes)
+@item @b{examine-start}
+@* Currently not used (goal: when JTAG examine starts)
+@item @b{gdb-attach}
+@* When GDB connects
+@item @b{gdb-detach}
+@* When GDB disconnects
+@item @b{gdb-end}
+@* When the taret has halted and GDB is not doing anything (see early halt)
+@item @b{gdb-flash-erase-start}
+@* Before the GDB flash process tries to erase the flash
+@item @b{gdb-flash-erase-end}
+@* After the GDB flash process has finished erasing the flash
+@item @b{gdb-flash-write-start}
+@* Before GDB writes to the flash
+@item @b{gdb-flash-write-end}
+@* After GDB writes to the flash
+@item @b{gdb-start}
+@* Before the taret steps, gdb is trying to start/resume the tarfget
+@item @b{halted}
+@* The target has halted
+@item @b{old-gdb_program_config}
+@* DO NOT USE THIS: Used internally
+@item @b{old-pre_resume}
+@* DO NOT USE THIS: Used internally
+@item @b{reset-assert-pre}
+@* Before reset is asserted on the tap.
+@item @b{reset-assert-post}
+@* Reset is now asserted on the tap.
+@item @b{reset-deassert-pre}
+@* Reset is about to be released on the tap
+@item @b{reset-deassert-post}
+@* Reset has been released on the tap
+@item @b{reset-end}
+@* Currently not used.
+@item @b{reset-halt-post}
+@* Currently not usd
+@item @b{reset-halt-pre}
+@* Currently not used
+@item @b{reset-init}
+@* Currently not used
+@item @b{reset-start}
+@* Currently not used
+@item @b{reset-wait-pos}
+@* Currently not used
+@item @b{reset-wait-pre}
+@* Currently not used
+@item @b{resume-start}
+@* Before any target is resumed
+@item @b{resume-end}
+@* After all targets have resumed
+@item @b{resume-ok}
+@* Success
+@item @b{resumed}
+@* Target has resumed
+@end itemize
-@item @b{reg} [@option{#}|@option{name}] [value]
-@cindex reg
-@*Access a single register by its number[@option{#}] or by its [@option{name}].
-No arguments: list all available registers for the current target.
-Number or name argument: display a register
-Number or name and value arguments: set register value
+@section target create
+@cindex target
+@cindex target creation
-@item @b{poll} [@option{on}|@option{off}]
-@cindex poll
-@*Poll the target for its current state. If the target is in debug mode, architecture
-specific information about the current state is printed. An optional parameter
-allows continuous polling to be enabled and disabled.
-
-@item @b{halt} [@option{ms}]
-@cindex halt
-@*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
-Default [@option{ms}] is 5 seconds if no arg given.
-Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
-will stop OpenOCD from waiting.
-
-@item @b{wait_halt} [@option{ms}]
-@cindex wait_halt
-@*Wait for the target to enter debug mode. Optional [@option{ms}] is
-a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
-arg given.
-
-@item @b{resume} [@var{address}]
-@cindex resume
-@*Resume the target at its current code position, or at an optional address.
-OpenOCD will wait 5 seconds for the target to resume.
-
-@item @b{step} [@var{address}]
-@cindex step
-@*Single-step the target at its current code position, or at an optional address.
-
-@item @b{reset} [@option{run}|@option{halt}|@option{init}]
-@cindex reset
-@*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
-
-With no arguments a "reset run" is executed
+@example
+@b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
+@end example
+@*This command creates a GDB debug target that refers to a specific JTAG tap.
+@comment START params
+@itemize @bullet
+@item @b{NAME}
+@* Is the name of the debug target. By convention it should be the tap
+DOTTED.NAME, this name is also used to create the target object
+command.
+@item @b{TYPE}
+@* Specifies the target type, ie: arm7tdmi, or cortexM3. Currently supported targes are:
+@comment START types
@itemize @minus
-@item @b{run}
-@cindex reset run
-@*Let the target run.
-@item @b{halt}
-@cindex reset halt
-@*Immediately halt the target (works only with certain configurations).
-@item @b{init}
-@cindex reset init
-@*Immediately halt the target, and execute the reset script (works only with certain
-configurations)
-@end itemize
-
-@item @b{soft_reset_halt}
-@cindex reset
-@*Requesting target halt and executing a soft reset.
+@item @b{arm7tdmi}
+@item @b{arm720t}
+@item @b{arm9tdmi}
+@item @b{arm920t}
+@item @b{arm922t}
+@item @b{arm926ejs}
+@item @b{arm966e}
+@item @b{cortex_m3}
+@item @b{feroceon}
+@item @b{xscale}
+@item @b{arm11}
+@item @b{mips_m4k}
+@comment end TYPES
@end itemize
-
-@subsection Memory access commands
+@item @b{PARAMS}
+@*PARAMs are various target configure parameters, the following are manditory
+at configuration.
+@comment START manditory
@itemize @bullet
-@item @b{meminfo}
-
-display available ram memory.
+@item @b{-endian big|little}
+@item @b{-chain-position DOTTED.NAME}
+@comment end MANDITORY
@end itemize
-These commands allow accesses of a specific size to the memory system:
-@itemize @bullet
-@item @b{mdw} <@var{addr}> [@var{count}]
-@cindex mdw
-@*display memory words
-@item @b{mdh} <@var{addr}> [@var{count}]
-@cindex mdh
-@*display memory half-words
-@item @b{mdb} <@var{addr}> [@var{count}]
-@cindex mdb
-@*display memory bytes
-@item @b{mww} <@var{addr}> <@var{value}>
-@cindex mww
-@*write memory word
-@item @b{mwh} <@var{addr}> <@var{value}>
-@cindex mwh
-@*write memory half-word
-@item @b{mwb} <@var{addr}> <@var{value}>
-@cindex mwb
-@*write memory byte
-
-@item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
-@cindex load_image
-@anchor{load_image}
-@*Load image <@var{file}> to target memory at <@var{address}>
-@item @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
-@cindex fast_load_image
-@anchor{fast_load_image}
-@*Normally you should be using @b{load_image} or GDB load. However, for
-testing purposes or when IO overhead is significant(OpenOCD running on embedded
-host), then storing the image in memory and uploading the image to the target
-can be a way to upload e.g. multiple debug sessions when the binary does not change.
-Arguments as @b{load_image}, but image is stored in OpenOCD host
-memory, i.e. does not affect target. This approach is also useful when profiling
-target programming performance as IO and target programming can easily be profiled
-seperately.
-@item @b{fast_load}
-@cindex fast_image
-@anchor{fast_image}
-@*Loads image stored in memory by @b{fast_load_image} to current target. Must be preceeded by fast_load_image.
-@item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
-@cindex dump_image
-@anchor{dump_image}
-@*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
-(binary) <@var{file}>.
-@item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
-@cindex verify_image
-@*Verify <@var{file}> against target memory starting at <@var{address}>.
-This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
+@comment END params
@end itemize
-@subsection Breakpoint commands
-@cindex Breakpoint commands
+@section Target Config/Cget Options
+These options can be specified when the target is created, or later
+via the configure option or to query the target via cget.
@itemize @bullet
-@item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
-@cindex bp
-@*set breakpoint <address> <length> [hw]
-@item @b{rbp} <@var{addr}>
-@cindex rbp
-@*remove breakpoint <adress>
-@item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
-@cindex wp
-@*set watchpoint <address> <length> <r/w/a> [value] [mask]
-@item @b{rwp} <@var{addr}>
-@cindex rwp
-@*remove watchpoint <adress>
+@item @b{-type} - returns the target type
+@item @b{-event NAME BODY} see Target events
+@item @b{-work-area-virt [ADDRESS]} specify/set the work area
+@item @b{-work-area-phys [ADDRESS]} specify/set the work area
+@item @b{-work-area-size [ADDRESS]} specify/set the work area
+@item @b{-work-area-backup [0|1]} does the work area get backed up
+@item @b{-endian [big|little]}
+@item @b{-variant [NAME]} some chips have varients openocd needs to know about
+@item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
+@end itemize
+Example:
+@example
+ for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
+ set name [target number $x]
+ set y [$name cget -endian]
+ set z [$name cget -type]
+ puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
+ @}
+@end example
+
+@section Target Varients
+@itemize @bullet
+@item @b{arm7tdmi}
+@* Unknown (please write me)
+@item @b{arm720t}
+@* Unknown (please write me) (simular to arm7tdmi)
+@item @b{arm9tdmi}
+@* Varients: @option{arm920t}, @option{arm922t} and @option{arm940t}
+This enables the hardware single-stepping support found on these
+cores.
+@item @b{arm920t}
+@* None.
+@item @b{arm966e}
+@* None (this is also used as the ARM946)
+@item @b{cortex_m3}
+@* use variant <@var{-variant lm3s}> when debugging luminary lm3s targets. This will cause
+openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
+the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
+be detected and the normal reset behaviour used.
+@item @b{xscale}
+@* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
+@item @b{arm11}
+@* Supported variants are @option{arm1136}, @option{arm1156}, @option{arm1176}
+@item @b{mips_m4k}
+@* Use variant @option{ejtag_srst} when debugging targets that do not
+provide a functional SRST line on the EJTAG connector. This causes
+openocd to instead use an EJTAG software reset command to reset the
+processor. You still need to enable @option{srst} on the reset
+configuration command to enable openocd hardware reset functionality.
+@comment END varients
@end itemize
+@section working_area - Command Removed
+@cindex working_area
+@*@b{Please use the ``$_TARGETNAME configure -work-area-... parameters instead}
+@* This documentation remains because there are existing scripts that
+still use this that need to be converted.
+@example
+ working_area target# address size backup| [virtualaddress]
+@end example
+@* The target# is a the 0 based target numerical index.
+
+This command specifies a working area for the debugger to use. This
+may be used to speed-up downloads to target memory and flash
+operations, or to perform otherwise unavailable operations (some
+coprocessor operations on ARM7/9 systems, for example). The last
+parameter decides whether the memory should be preserved
+(<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If
+possible, use a working_area that doesn't need to be backed up, as
+performing a backup slows down operation.
+
+@node Flash Configuration
+@chapter Flash Programing
+@cindex Flash Configuration
+
+@b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
+flash that a micro may boot from. Perhaps you the reader would like to
+contribute support for this.
+
+Flash Steps:
+@enumerate
+@item Configure via the command @b{flash bank}
+@* Normally this is done in a configuration file.
+@item Operate on the flash via @b{flash SOMECOMMAND}
+@* Often commands to manipulate the flash are typed by a human, or run
+via a script in some automated way. For example: To program the boot
+flash on your board.
+@item GDB Flashing
+@* Flashing via GDB requires the flash be configured via ``flash
+bank'', and the GDB flash features be enabled. See the Daemon
+configuration section for more details.
+@end enumerate
-@subsection Flash commands
+@section Flash commands
@cindex Flash commands
-@itemize @bullet
-@item @b{flash banks}
+@subsection flash banks
+@b{flash banks}
@cindex flash banks
@*List configured flash banks
-@item @b{flash info} <@var{num}>
+@*@b{NOTE:} the singular form: 'flash bank' is used to configure the flash banks.
+@subsection flash info
+@b{flash info} <@var{num}>
@cindex flash info
@*Print info about flash bank <@option{num}>
-@item @b{flash probe} <@var{num}>
+@subsection flash probe
+@b{flash probe} <@var{num}>
@cindex flash probe
@*Identify the flash, or validate the parameters of the configured flash. Operation
depends on the flash type.
-@item @b{flash erase_check} <@var{num}>
+@subsection flash erase_check
+@b{flash erase_check} <@var{num}>
@cindex flash erase_check
@*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
updates the erase state information displayed by @option{flash info}. That means you have
to issue an @option{erase_check} command after erasing or programming the device to get
updated information.
-@item @b{flash protect_check} <@var{num}>
+@subsection flash protect_check
+@b{flash protect_check} <@var{num}>
@cindex flash protect_check
@*Check protection state of sectors in flash bank <num>.
@option{flash erase_sector} using the same syntax.
-@item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
+@subsection fash erase_sector
+@b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
@cindex flash erase_sector
@anchor{flash erase_sector}
@*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
<@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
the CFI driver).
-@item @b{flash erase_address} <@var{address}> <@var{length}>
+@subsection flash erase_address
+@b{flash erase_address} <@var{address}> <@var{length}>
@cindex flash erase_address
@*Erase sectors starting at <@var{address}> for <@var{length}> bytes
-@item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
+@subsection flash write_bank
+@b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
@cindex flash write_bank
@anchor{flash write_bank}
@*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
<@option{offset}> bytes from the beginning of the bank.
-@item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
+@subsection flash write_image
+@b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
@cindex flash write_image
@anchor{flash write_image}
@*Write the image <@var{file}> to the current target's flash bank(s). A relocation
explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
(ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
if the @option{erase} parameter is given.
-@item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
+@subsection flash protect
+@b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
@cindex flash protect
@*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
<@var{last}> of @option{flash bank} <@var{num}>.
-@end itemize
@subsection mFlash commands
@cindex mFlash commands
to a <@var{file}>.
@end itemize
-@page
-@section Target Commands
-@cindex Target Commands
-
-@subsection Overview
-@cindex Overview
-Pre "TCL" - many commands in OpenOCD where implemented as C functions. Post "TCL"
-(Jim-Tcl to be more exact, June 2008) TCL became a bigger part of OpenOCD.
-
-One of the biggest changes is the introduction of 'target specific'
-commands. When every time you create a target, a special command name is
-created specifically for that target.
-For example - in TCL/TK - if you create a button (or any other screen object) you
-can specify various "button configuration parameters". One of those parameters is
-the "object cmd/name" [ In TK - this is referred to as the object path ]. Later
-you can use that 'path' as a command to modify the button, for example to make it
-"grey", or change the color. In effect, the "path" function is an 'object
-oriented command'. The TCL change in OpenOCD follows the same principle, you create
-a target, and a specific "targetname" command is created.
-
-There are two methods of creating a target:
-
-@enumerate
-@item
-Using the old syntax (deprecated). Target names are autogenerated as:
- "target0", "target1", etc.;
-@cindex old syntax
-@item
-Using the new syntax, you can specify the name of the target.
-@cindex new syntax
-@end enumerate
-
-As most users will have a single JTAG target, and by default the command name will
-probably default to "target0", thus for reasons of simplicity the instructions below
-use the name "target0".
-
-@subsection Commands
-@cindex Commands
-OpenOCD has the following 'target' or 'target-like' commands:
+@section flash bank command
+The @b{flash bank} command is used to configure one or more flash chips (or banks in openocd terms)
-@enumerate
-@item
-@b{targets (plural)} - lists all known targets and a little bit of information about each
- target, most importantly the target *COMMAND*NAME* (it also lists the target number);
-@cindex targets
-@item
-@b{target (singular)} - used to create, configure list, etc the targets;
-@cindex target
-@item
-@b{target0} - the command object for the first target. Unless you specified another name.
-@cindex target0
-@end enumerate
-
-@subsubsection Targets Command
-@cindex Targets Command
-The "targets" command has 2 functions:
-
-@itemize
-@item
-With a parameter, you can change the current command line target.
-
-NOTE: "with a parameter" is really only useful with 'multiple JTAG targets' not something
-you normally encounter (ie: If you had 2 arm chips - sharing the same JTAG chain).
-@verbatim
-# using a target name.
-(gdb) mon targets target0
-# or a target by number.
-(gdb) mon targets 3
-@end verbatim
-@cindex with a parameter
-@item
-Plain, without any parameter lists targets, for example:
-
-@verbatim
-(gdb) mon targets
- CmdName Type Endian ChainPos State
--- ---------- ---------- ---------- -------- ----------
- 0: target0 arm7tdmi little 0 halted
-@end verbatim
-
-This shows:
-@enumerate a
-@item
-in this example, a single target;
-@item
-target number 0 (1st column);
-@item
-the 'object name' is target0 (the default name);
-@item
-it is an arm7tdmi;
-@item
-little endian;
-@item
-the position in the JTAG chain;
-@item
-and is currently halted.
-@end enumerate
-@cindex without any parameter
-@end itemize
-
-@subsubsection Target Command
-@cindex Target Command
-
-The "target" command has the following options:
-@itemize
-@item
-target create
-
-@verbatim
- target create CMDNAME TYPE ... config options ...
- argv[0] = 'target'
- argv[1] = 'create'
- argv[2] = the 'object command'
- (normally, target0, see (3) above)
- argv[3] = the target type, ie: arm7tdmi
- argv[4..N] = configuration parameters
-@end verbatim
-@item
-target types
-
- Lists all supported target types; ie: arm7tdmi, xscale, fericon, cortex-m3.
- The result TCL list of all known target types (and is human readable).
-@item
-target names
-
- Returns a TCL list of all known target commands (and is human readable).
-
- Example:
-@verbatim
- foreach t [target names] {
- puts [format "Target: %s\n" $t]
- }
-@end verbatim
-@item
-target current
-
- Returns the TCL command name of the current target.
-
- Example:
-@verbatim
- set ct [target current]
- set t [$ct cget -type]
-
- puts "Current target name is: $ct, and is a: $t"
-@end verbatim
-@item
-target number <VALUE>
-
- Returns the TCL command name of the specified target.
-
- Example
-@verbatim
- set thename [target number $x]
- puts [format "Target %d is: %s\n" $x $thename]
-@end verbatim
- For instance, assuming the defaults
-@verbatim
- target number 0
-@end verbatim
- Would return 'target0' (or whatever you called it)
-@item
-target count
-
- Returns the larget+1 target number.
-
- Example:
-@verbatim
- set c [target count]
- for { set x 0 } { $x < $c } { incr x } {
- # Assuming you have this function..
- print_target_details $x
- }
-@end verbatim
-@end itemize
-
-@subsubsection Target0 Command
-@cindex Target0 Command
-The "target0" command (the "Target Object" command):
-
-Once a target is 'created' a command object by that targets name is created, for example
-@verbatim
- target create BiGRed arm7tdmi -endian little -chain-position 3
-@end verbatim
-
-Would create a [case sensitive] "command" BiGRed
-
-If you use the old [deprecated] syntax, the name is automatically
-generated and is in the form:
-@verbatim
- target0, target1, target2, target3, ... etc.
-@end verbatim
-
-@subsubsection Target CREATE, CONFIGURE and CGET Options Command
-@cindex Target CREATE, CONFIGURE and CGET Options Command
-The commands:
-@verbatim
- target create CMDNAME TYPE [configure-options]
- CMDNAME configure [configure-options]
- CMDNAME cget [configure-options]
-@end verbatim
-@itemize
-@item
-In the 'create' case, one is creating the target and can specify any
-number of configuration parameters.
-@item
-In the 'CMDNAME configure' case, one can change the setting [Not all things can, or should be changed].
-@item
-In the 'CMDNAME cget' case, the goal is to query the target for a
-specific configuration option.
-@end itemize
-
-In the above, the "default" name target0 is 'target0'.
-
- Example:
-
- From the (gdb) prompt, one can type this:
-
-@verbatim
- (gdb) mon target0 configure -endian big
-@end verbatim
-
- And change target0 to 'big-endian'. This is a contrived example,
- specifically for this document - don't expect changing endian
- 'mid-operation' to work you should set the endian at creation.
-
-Known options [30/august/2008] are:
-@itemize
-@item
-[Mandatory 'create' Options]
- @itemize
- @item
- type arm7tdmi|arm720|etc ...
- @item
- chain-position NUMBER
- @item
- endian ENDIAN
- @end itemize
-@item
-Optional
- @itemize
- @item
- event EVENTNAME "tcl-action"
- @item
- reset RESETACTION
- @item
- work-area-virt ADDR
- @item
- work-area-phys ADDR
- @item
- work-area-size ADDR
- @item
- work-area-backup BOOLEAN
- @end itemize
-@end itemize
-Hint: To get a list of available options, try this:
-@verbatim
- (gdb) mon target0 cget -BLAHBLAHBLAH
-@end verbatim
-
- the above causes an error - and a helpful list of valid options.
-
-One can query any of the above options at run time, for example:
-@verbatim
- (gdb) mon target0 cget -OPTION [param]
-@end verbatim
-
-Example TCL script
-
-@verbatim
- # For all targets...
- set c [target count]
- for { set x 0 } { $x < $c } { incr x ] {
- set n [target number $x]
- set t [$n cget -type]
- set e [$n cget -endian]
- puts [format "%d: %s, %s, endian: %s\n" $x $n $t $n]
- }
-@end verbatim
-
-Might produce:
-
-@verbatim
- 0: pic32chip, mips_m4k, endain: little
- 1: arm7, arm7tdmi, endian: big
- 2: blackfin, bf534, endian: little
-@end verbatim
-
-Notice the above example is not target0, target1, target2 Why? Because in this contrived multi-target example -
-more human understandable target names might be helpful.
-
-For example these two are the same:
-
-@verbatim
- (gdb) mon blackfin configure -event FOO {puts "Hi mom"}
-@end verbatim
-
-or:
-
-@verbatim
- (gdb) mon [target number 2] configure -event FOO {puts "Hi mom"}
-@end verbatim
-
-In the second case, we use [] to get the command name of target #2, in this contrived example - it is "blackfin".
+@example
+@b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
+<@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
+@end example
+@cindex flash bank
+@*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
+and <@var{bus_width}> bytes using the selected flash <driver>.
-Two important configuration options are:
+@subsection External Flash - cfi options
+@cindex cfi options
+CFI flash are external flash chips - often they are connected to a
+specific chip select on the micro. By default at hard reset most
+micros have the ablity to ``boot'' from some flash chip - typically
+attached to the chips CS0 pin.
- "-event" and "-reset"
+For other chip selects: OpenOCD does not know how to configure, or
+access a specific chip select. Instead you the human might need to via
+other commands (like: mww) configure additional chip selects, or
+perhaps configure a GPIO pin that controls the ``write protect'' pin
+on the FLASH chip.
-The "-reset" option specifies what should happen when the chip is reset, for example should it 'halt', 're-init',
-or what.
+@b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
+<@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
+@*CFI flashes require the number of the target they're connected to as an additional
+argument. The CFI driver makes use of a working area (specified for the target)
+to significantly speed up operation.
-The "-event" option less you specify a TCL command to occur when a specific event occurs.
+@var{chip_width} and @var{bus_width} are specified in bytes.
-@subsubsection Other Target Commands
-@cindex Other Target Commands
-@itemize
-@item @b{profile} <@var{seconds}> <@var{gmon.out}>
+The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
-Profiling samples the CPU PC as quickly as OpenOCD is able, which will be used as a random sampling of PC.
-@end itemize
+@var{x16_as_x8} ???
-@subsection Target Events
-@cindex Target Events
+@subsection Internal Flash (Micro Controllers)
+@subsubsection lpc2000 options
+@cindex lpc2000 options
-@subsubsection Overview
-@cindex Overview
-At various points in time - certain 'target' events happen. You can create a custom event action to occur at that time.
-For example - after reset, the PLLs and CLOCKs may need to be reconfigured, or perhaps the SDRAM needs to be re-initialized.
-Often the easiest way to do that is to create a simple script file containing the series of (mww [poke memory]) commands
-you would type by hand, to reconfigure the target clocks. You could specify the "event action" like this:
+@b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
+<@var{clock}> [@var{calc_checksum}]
+@*LPC flashes don't require the chip and bus width to be specified. Additional
+parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
+or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
+of the target this flash belongs to (first is 0), the frequency at which the core
+is currently running (in kHz - must be an integral number), and the optional keyword
+@var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
+vector table.
-@verbatim
- (gdb) mon target0 configure -event reset-init "script cfg.clocks"
-@end verbatim
-In the above example, when the event "reset-init" occurs, the "action-string" will be evaluated as if you typed it at the
-console:
-@itemize
-@item @b{Option1} - The simple approach (above) is to create a script file with lots of "mww" (memory write word) commands
- to configure your targets clocks and/or external memory;
-@item @b{Option2} - You can instead create a fancy TCL procedure and invoke that procedure instead of sourcing a file [In fact,
- "script" is a TCL procedure that loads a file].
-@end itemize
+@subsubsection at91sam7 options
+@cindex at91sam7 options
-@subsubsection Details
-@cindex Details
-There are many events one could use, to get a current list of events type the following invalid command, you'll get a helpful
-"runtime error" message, see below [list valid as of 30/august/2008]:
+@b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
+@*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
+reading the chip-id and type.
-@verbatim
-(gdb) mon target0 cget -event FAFA
-Runtime error, file "../../../openocd23/src/helper/command.c", line 433:
- -event: Unknown: FAFA, try one of: old-pre_reset,
- old-gdb_program_config, old-post_reset, halted,
- resumed, resume-start, resume-end, reset-start,
- reset-assert-pre, reset-assert-post,
- reset-deassert-pre, reset-deassert-post,
- reset-halt-pre, reset-halt-post, reset-wait-pre,
- reset-wait-post, reset-init, reset-end,
- examine-start, examine-end, debug-halted,
- debug-resumed, gdb-attach, gdb-detach,
- gdb-flash-write-start, gdb-flash-write-end,
- gdb-flash-erase-start, gdb-flash-erase-end,
- resume-start, resume-ok, or resume-end
-@end verbatim
+@subsubsection str7 options
+@cindex str7 options
-NOTE: The event-names "old-*" are deprecated and exist only to help old scripts continue to function, and the old "target_script"
-command to work. Please do not rely on them.
+@b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
+@*variant can be either STR71x, STR73x or STR75x.
-These are some other important names:
-@itemize
-@item gdb-flash-erase-start
-@item gdb-flash-erase-end
-@item gdb-flash-write-start
-@item gdb-flash-write-end
-@end itemize
+@subsubsection str9 options
+@cindex str9 options
-These occur when GDB/OpenOCD attempts to erase & program the FLASH chip via GDB. For example - some PCBs may have a simple GPIO
-pin that acts like a "flash write protect" you might need to write a script that disables "write protect".
+@b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
+@*The str9 needs the flash controller to be configured prior to Flash programming, eg.
+@example
+str9x flash_config 0 4 2 0 0x80000
+@end example
+This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
-To get a list of current 'event actions', type the following command:
+@subsubsection str9 options (str9xpec driver)
-@verbatim
- (gdb) mon target0 eventlist
+@b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
+@*Before using the flash commands the turbo mode will need enabling using str9xpec
+@option{enable_turbo} <@var{num>.}
- Event actions for target (0) target0
+Only use this driver for locking/unlocking the device or configuring the option bytes.
+Use the standard str9 driver for programming.
- Event | Body
- ------------------------- | ----------------------------------------
- old-post_reset | script event/sam7x256_reset.script
-@end verbatim
+@subsubsection stellaris (LM3Sxxx) options
+@cindex stellaris (LM3Sxxx) options
-Here is a simple example for all targets:
+@b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
+@*stellaris flash plugin only require the @var{target#}.
-@verbatim
- (gdb) mon foreach x [target names] { $x eventlist }
-@end verbatim
+@subsubsection stm32x options
+@cindex stm32x options
-The above uses some TCL tricks:
-@enumerate a
-@item foreach VARIABLE LIST BODY
-@item to generate the list, we use [target names]
-@item the BODY, contains $x - the loop variable and expands to the target specific name
-@end enumerate
+@b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
+@*stm32x flash plugin only require the @var{target#}.
-Recalling the earlier discussion - the "object command" there are other things you can
-do besides "configure" the target.
+@subsubsection aduc702x options
+@cindex aduc702x options
-Note: Many of these commands exist as "global" commands, and they also exist as target
-specific commands. For example, the "mww" (memory write word) operates on the current
-target if you have more then 1 target, you must switch. In contrast to the normal
-commands, these commands operate on the specific target. For example, the command "mww"
-writes data to the *current* command line target.
+@b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
+@*aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
-Often, you have only a single target - but if you have multiple targets (ie: a PIC32
-and an at91sam7 - your reset-init scripts might get a bit more complicated, ie: you must
-specify which of the two chips you want to write to. Writing 'pic32' clock configuration
-to an at91sam7 does not work).
+@subsection mFlash configuration
+@cindex mFlash configuration
+@b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
+<@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target #}>
+@cindex mflash bank
+@*Configures a mflash for <@var{soc}> host bank at
+<@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
+order. Pin number format is dependent on host GPIO calling convention.
+If WP or DPD pin was not used, write -1. Currently, mflash bank
+support s3c2440 and pxa270.
-The commands are [as of 30/august/2008]:
-@verbatim
- TNAME mww ADDRESS VALUE
- TNAME mwh ADDRESS VALUE
- TNAME mwb ADDRESS VALUE
- Write(poke): 32, 16, 8bit values to memory.
-
- TNAME mdw ADDRESS VALUE
- TNAME mdh ADDRESS VALUE
- TNAME mdb ADDRESS VALUE
- Human 'hexdump' with ascii 32, 16, 8bit values
-
- TNAME mem2array [see mem2array command]
- TNAME array2mem [see array2mem command]
-
- TNAME curstate
- Returns the current state of the target.
-
- TNAME examine
- See 'advanced target reset'
- TNAME poll
- See 'advanced target reset'
- TNAME reset assert
- See 'advanced target reset'
- TNAME reset deassert
- See 'advanced target reset'
- TNAME halt
- See 'advanced target reset'
- TNAME waitstate STATENAME
- See 'advanced target reset'
-@end verbatim
+(ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
+@example
+mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
+@end example
+(ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
+@example
+mflash bank pxa270 0x08000000 2 2 43 -1 51 0
+@end example
-@page
-@section Target Specific Commands
-@cindex Target Specific Commands
+@section Micro Controller Specific Flash Commands
@subsection AT91SAM7 specific commands
@cindex AT91SAM7 specific commands
<@var{BBADR}> <@var{NBBADR}>
@cindex str9x flash_config
@*Configure str9 flash controller.
-@smallexample
+@example
eg. str9x flash_config 0 4 2 0 0x80000
This will setup
BBSR - Boot Bank Size register
NBBSR - Non Boot Bank Size register
BBADR - Boot Bank Start Address register
NBBADR - Boot Bank Start Address register
-@end smallexample
+@end example
+@end itemize
+
+@subsection STR9 option byte configuration
+@cindex STR9 option byte configuration
+@itemize @bullet
+@item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
+@cindex str9xpec options_cmap
+@*configure str9 boot bank.
+@item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
+@cindex str9xpec options_lvdthd
+@*configure str9 lvd threshold.
+@item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
+@cindex str9xpec options_lvdsel
+@*configure str9 lvd source.
+@item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
+@cindex str9xpec options_lvdwarn
+@*configure str9 lvd reset warning source.
+@end itemize
+
+@subsection STM32x specific commands
+@cindex STM32x specific commands
+
+These are flash specific commands when using the stm32x driver.
+@itemize @bullet
+@item @b{stm32x lock} <@var{num}>
+@cindex stm32x lock
+@*lock stm32 device.
+@item @b{stm32x unlock} <@var{num}>
+@cindex stm32x unlock
+@*unlock stm32 device.
+@item @b{stm32x options_read} <@var{num}>
+@cindex stm32x options_read
+@*read stm32 option bytes.
+@item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
+<@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
+@cindex stm32x options_write
+@*write stm32 option bytes.
+@item @b{stm32x mass_erase} <@var{num}>
+@cindex stm32x mass_erase
+@*mass erase flash memory.
@end itemize
-@subsection STR9 option byte configuration
-@cindex STR9 option byte configuration
-@itemize @bullet
-@item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
-@cindex str9xpec options_cmap
-@*configure str9 boot bank.
-@item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
-@cindex str9xpec options_lvdthd
-@*configure str9 lvd threshold.
-@item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
-@cindex str9xpec options_lvdsel
-@*configure str9 lvd source.
-@item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
-@cindex str9xpec options_lvdwarn
-@*configure str9 lvd reset warning source.
-@end itemize
+@subsection Stellaris specific commands
+@cindex Stellaris specific commands
+
+These are flash specific commands when using the Stellaris driver.
+@itemize @bullet
+@item @b{stellaris mass_erase} <@var{num}>
+@cindex stellaris mass_erase
+@*mass erase flash memory.
+@end itemize
+
+
+@node General Commands
+@chapter General Commands
+@cindex commands
+
+The commands documented in this chapter here are common commands that
+you a human may want to type and see the output of. Configuration type
+commands are documented elsewhere.
+
+Intent:
+@itemize @bullet
+@item @b{Source Of Commands}
+@* OpenOCD commands can occur in a configuration script (discussed
+elsewhere) or typed manually by a human or supplied programatically,
+or via one of several Tcp/Ip Ports.
+
+@item @b{From the human}
+@* A human should interact with the Telnet interface (default port: 4444,
+or via GDB, default port 3333)
+
+To issue commands from within a GDB session, use the @option{monitor}
+command, e.g. use @option{monitor poll} to issue the @option{poll}
+command. All output is relayed through the GDB session.
+
+@item @b{Machine Interface}
+The TCL interface intent is to be a machine interface. The default TCL
+port is 5555.
+@end itemize
+
+
+@section Daemon Commands
+
+@subsection sleep
+@b{sleep} <@var{msec}>
+@cindex sleep
+@*Wait for n milliseconds before resuming. Useful in connection with script files
+(@var{script} command and @var{target_script} configuration).
+
+@subsection sleep
+@b{shutdown}
+@cindex shutdown
+@*Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
+
+@subsection debug_level [@var{n}]
+@cindex debug_level
+@anchor{debug_level}
+@*Display or adjust debug level to n<0-3>
+
+@subsection fast [@var{enable|disable}]
+@cindex fast
+@*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
+downloads and fast memory access will work if the JTAG interface isn't too fast and
+the core doesn't run at a too low frequency. Note that this option only changes the default
+and that the indvidual options, like DCC memory downloads, can be enabled and disabled
+individually.
+
+The target specific "dangerous" optimisation tweaking options may come and go
+as more robust and user friendly ways are found to ensure maximum throughput
+and robustness with a minimum of configuration.
+
+Typically the "fast enable" is specified first on the command line:
+
+@example
+openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
+@end example
+
+@subsection log_output <@var{file}>
+@cindex log_output
+@*Redirect logging to <file> (default: stderr)
+
+@subsection script <@var{file}>
+@cindex script
+@*Execute commands from <file>
+Also see: ``source [find FILENAME]''
+
+@section Target state handling
+@subsection power <@var{on}|@var{off}>
+@cindex reg
+@*Turn power switch to target on/off.
+No arguments: print status.
+Not all interfaces support this.
+
+@subsection reg [@option{#}|@option{name}] [value]
+@cindex reg
+@*Access a single register by its number[@option{#}] or by its [@option{name}].
+No arguments: list all available registers for the current target.
+Number or name argument: display a register
+Number or name and value arguments: set register value
+
+@subsection poll [@option{on}|@option{off}]
+@cindex poll
+@*Poll the target for its current state. If the target is in debug mode, architecture
+specific information about the current state is printed. An optional parameter
+allows continuous polling to be enabled and disabled.
+
+@subsection halt [@option{ms}]
+@cindex halt
+@*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
+Default [@option{ms}] is 5 seconds if no arg given.
+Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
+will stop OpenOCD from waiting.
+
+@subsection wait_halt [@option{ms}]
+@cindex wait_halt
+@*Wait for the target to enter debug mode. Optional [@option{ms}] is
+a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
+arg given.
+
+@subsection resume [@var{address}]
+@cindex resume
+@*Resume the target at its current code position, or at an optional address.
+OpenOCD will wait 5 seconds for the target to resume.
+
+@subsection step [@var{address}]
+@cindex step
+@*Single-step the target at its current code position, or at an optional address.
+
+@subsection reset [@option{run}|@option{halt}|@option{init}]
+@cindex reset
+@*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
+
+With no arguments a "reset run" is executed
+@itemize @minus
+@item @b{run}
+@cindex reset run
+@*Let the target run.
+@item @b{halt}
+@cindex reset halt
+@*Immediately halt the target (works only with certain configurations).
+@item @b{init}
+@cindex reset init
+@*Immediately halt the target, and execute the reset script (works only with certain
+configurations)
+@end itemize
+
+@subsection soft_reset_halt
+@cindex reset
+@*Requesting target halt and executing a soft reset. This often used
+when a target cannot be reset and halted. The target, after reset is
+released begins to execute code. OpenOCD attempts to stop the CPU and
+then sets the Program counter back at the reset vector. Unfortunatlly
+that code that was executed may have left hardware in an unknown
+state.
+
+
+@section Memory access commands
+@subsection meminfo
+display available ram memory.
+@subsection Memory Peek/Poke type commands
+These commands allow accesses of a specific size to the memory
+system. Often these are used to configure the current target in some
+special way. For example - one may need to write certian values to the
+SDRAM controller to enable SDRAM.
+
+@enumerate
+@item To change the current target see the ``targets'' (plural) command
+@item In system level scripts these commands are depricated, please use the TARGET object versions.
+@end enumerate
+
+@itemize @bullet
+@item @b{mdw} <@var{addr}> [@var{count}]
+@cindex mdw
+@*display memory words (32bit)
+@item @b{mdh} <@var{addr}> [@var{count}]
+@cindex mdh
+@*display memory half-words (16bit)
+@item @b{mdb} <@var{addr}> [@var{count}]
+@cindex mdb
+@*display memory bytes (8bit)
+@item @b{mww} <@var{addr}> <@var{value}>
+@cindex mww
+@*write memory word (32bit)
+@item @b{mwh} <@var{addr}> <@var{value}>
+@cindex mwh
+@*write memory half-word (16bit)
+@item @b{mwb} <@var{addr}> <@var{value}>
+@cindex mwb
+@*write memory byte (8bit)
+@end itemize
+
+@section Image Loading Commands
+@subsection load_image
+@b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
+@cindex load_image
+@anchor{load_image}
+@*Load image <@var{file}> to target memory at <@var{address}>
+@subsection fast_load_image
+@b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
+@cindex fast_load_image
+@anchor{fast_load_image}
+@*Normally you should be using @b{load_image} or GDB load. However, for
+testing purposes or when IO overhead is significant(OpenOCD running on embedded
+host), then storing the image in memory and uploading the image to the target
+can be a way to upload e.g. multiple debug sessions when the binary does not change.
+Arguments as @b{load_image}, but image is stored in OpenOCD host
+memory, i.e. does not affect target. This approach is also useful when profiling
+target programming performance as IO and target programming can easily be profiled
+seperately.
+@subsection fast_load
+@b{fast_load}
+@cindex fast_image
+@anchor{fast_image}
+@*Loads image stored in memory by @b{fast_load_image} to current target. Must be preceeded by fast_load_image.
+@subsection dump_image
+@b{dump_image} <@var{file}> <@var{address}> <@var{size}>
+@cindex dump_image
+@anchor{dump_image}
+@*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
+(binary) <@var{file}>.
+@subsection verify_image
+@b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
+@cindex verify_image
+@*Verify <@var{file}> against target memory starting at <@var{address}>.
+This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
+
-@subsection STM32x specific commands
-@cindex STM32x specific commands
-
-These are flash specific commands when using the stm32x driver.
+@section Breakpoint commands
+@cindex Breakpoint commands
@itemize @bullet
-@item @b{stm32x lock} <@var{num}>
-@cindex stm32x lock
-@*lock stm32 device.
-@item @b{stm32x unlock} <@var{num}>
-@cindex stm32x unlock
-@*unlock stm32 device.
-@item @b{stm32x options_read} <@var{num}>
-@cindex stm32x options_read
-@*read stm32 option bytes.
-@item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
-<@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
-@cindex stm32x options_write
-@*write stm32 option bytes.
-@item @b{stm32x mass_erase} <@var{num}>
-@cindex stm32x mass_erase
-@*mass erase flash memory.
+@item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
+@cindex bp
+@*set breakpoint <address> <length> [hw]
+@item @b{rbp} <@var{addr}>
+@cindex rbp
+@*remove breakpoint <adress>
+@item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
+@cindex wp
+@*set watchpoint <address> <length> <r/w/a> [value] [mask]
+@item @b{rwp} <@var{addr}>
+@cindex rwp
+@*remove watchpoint <adress>
@end itemize
-@subsection Stellaris specific commands
-@cindex Stellaris specific commands
-
-These are flash specific commands when using the Stellaris driver.
-@itemize @bullet
-@item @b{stellaris mass_erase} <@var{num}>
-@cindex stellaris mass_erase
-@*mass erase flash memory.
+@section Misc Commands
+@cindex Other Target Commands
+@itemize
+@item @b{profile} <@var{seconds}> <@var{gmon.out}>
+
+Profiling samples the CPU PC as quickly as OpenOCD is able, which will be used as a random sampling of PC.
@end itemize
+@section Target Specific Commands
+@cindex Target Specific Commands
+
+
@page
@section Architecture Specific Commands
@cindex Architecture Specific Commands
encoding of the [M4:M0] bits of the PSR.
@end itemize
-@page
-@section JTAG commands
+@section Target Requests
+@cindex Target Requests
+OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
+See libdcc in the contrib dir for more details.
+@itemize @bullet
+@item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
+@cindex target_request debugmsgs
+@*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
+@end itemize
+
+@node JTAG Commands
+@chapter JTAG Commands
@cindex JTAG commands
+Generally most people will not use the bulk of these commands. They
+are mostly used by the OpenOCD developers or those who need to
+directly manipulate the JTAG taps.
+
+In general these commands control JTAG taps at a very low level. For
+example if you need to control a JTAG Route Controller (ie: the
+OMAP3530 on the Beagle Board has one) you might use these commands in
+a script or an event procedure.
+
@itemize @bullet
@item @b{scan_chain}
@cindex scan_chain
Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
@end itemize
-@page
-@section Target Requests
-@cindex Target Requests
-OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
-See libdcc in the contrib dir for more details.
-@itemize @bullet
-@item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
-@cindex target_request debugmsgs
-@*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
-@end itemize
@node TFTP
@chapter TFTP
If OpenOCD runs on an embedded host(as ZY1000 does), then tftp can
be used to access files on PCs(either developer PC or some other PC).
-The way this works is to prefix a filename by "/tftp/ip/" and append
-the tftp path on the tftp server(tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf"
-will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
+The way this works on the ZY1000 is to prefix a filename by
+"/tftp/ip/" and append the tftp path on the tftp
+server(tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
+load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
if the file was hosted on the embedded host.
In order to achieve decent performance, you must choose a tftp server
@cindex AT91R40008 example
To start OpenOCD with a target script for the AT91R40008 CPU and reset
the CPU upon startup of the OpenOCD daemon.
-@smallexample
+@example
openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
-@end smallexample
+@end example
@node GDB and OpenOCD
@section Connecting to gdb
@cindex Connecting to gdb
-Use GDB 6.7 or newer with OpenOCD if you run into trouble. For instance 6.3 has a
-known bug where it produces bogus memory access errors, which has since
-been fixed: look up 1836 in http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb
+Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
+instance 6.3 has a known bug where it produces bogus memory access
+errors, which has since been fixed: look up 1836 in
+@url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
A connection is typically started as follows:
-@smallexample
+@example
target remote localhost:3333
-@end smallexample
+@end example
This would cause gdb to connect to the gdbserver on the local pc using port 3333.
To see a list of available OpenOCD commands type @option{monitor help} on the
Previous versions of OpenOCD required the following gdb options to increase
the packet size and speed up gdb communication.
-@smallexample
+@example
set remote memory-write-packet-size 1024
set remote memory-write-packet-size fixed
set remote memory-read-packet-size 1024
set remote memory-read-packet-size fixed
-@end smallexample
+@end example
This is now handled in the @option{qSupported} PacketSize.
@section Programming using gdb
By default the target memory map is sent to gdb, this can be disabled by
the following OpenOCD config option:
-@smallexample
+@example
gdb_memory_map disable
-@end smallexample
+@end example
For this to function correctly a valid flash config must also be configured
in OpenOCD. For faster performance you should also configure a valid
working area.
GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
this can be changed to the old behaviour by using the following gdb command.
-@smallexample
+@example
set mem inaccessible-by-default off
-@end smallexample
+@end example
If @option{gdb_flash_program enable} is also used, gdb will be able to
program any flash memory using the vFlash interface.
areas to be programmed lie within the target flash area the vFlash packets
will be used.
-If the target needs configuring before gdb programming, a script can be executed.
-@smallexample
-target_script 0 gdb_program_config config.script
-@end smallexample
+If the target needs configuring before gdb programming, an event
+script can be executed.
+@example
+$_TARGETNAME configure -event EVENTNAME BODY
+@end example
To verify any flash programming the gdb command @option{compare-sections}
can be used.
-@node TCL and OpenOCD
-@chapter TCL and OpenOCD
-@cindex TCL and OpenOCD
-OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting
-support.
-
-The TCL interpreter can be invoked from the interactive command line, files, and a network port.
-
-The command and file interfaces are fairly straightforward, while the network
-port is geared toward intergration with external clients. A small example
-of an external TCL script that can connect to openocd is shown below.
-
-@verbatim
-# Simple tcl client to connect to openocd
-puts "Use empty line to exit"
-set fo [socket 127.0.0.1 6666]
-puts -nonewline stdout "> "
-flush stdout
-while {[gets stdin line] >= 0} {
- if {$line eq {}} break
- puts $fo $line
- flush $fo
- gets $fo line
- puts $line
- puts -nonewline stdout "> "
- flush stdout
-}
-close $fo
-@end verbatim
-
-This script can easily be modified to front various GUIs or be a sub
-component of a larger framework for control and interaction.
-
-
@node TCL scripting API
@chapter TCL scripting API
@cindex TCL scripting API
@chapter FAQ
@cindex faq
@enumerate
-@item Why does not backslashes in paths under Windows doesn't work?
+@item @b{RTCK, also known as: Adaptive Clocking - What is it?}
+@cindex RTCK
+@cindex adaptive clocking
+@*
+
+In digital circuit design it is often refered to as ``clock
+syncronization'' the JTAG interface uses one clock (TCK or TCLK)
+operating at some speed, your target is operating at another. The two
+clocks are not syncronized, they are ``asynchronous''
+
+In order for the two to work together they must syncronize. Otherwise
+the two systems will get out of sync with each other and nothing will
+work. There are 2 basic options. @b{1.} use a special circuit or
+@b{2.} one clock must be some multile slower the the other.
+
+@b{Does this really matter?} For some chips and some situations, this
+is a non-issue (ie: A 500mhz ARM926) but for others - for example some
+ATMEL SAM7 and SAM9 chips start operation from reset at 32khz -
+program/enable the oscillators and eventually the main clock. It is in
+those critical times you must slow the jtag clock to sometimes 1 to
+4khz.
+
+Imagine debugging that 500mhz arm926 hand held battery powered device
+that ``deep sleeps'' at 32khz between every keystroke. It can be
+painful.
+
+@b{Solution #1 - A special circuit}
+
+In order to make use of this your jtag dongle must support the RTCK
+feature. Not all dongles support this - keep reading!
+
+The RTCK signal often found in some ARM chips is used to help with
+this problem. ARM has a good description of the problem described at
+this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
+28/nov/2008]. Link title: ``How does the jtag synchronisation logic
+work? / how does adaptive clocking working?''.
+
+The nice thing about adaptive clocking is that ``battery powered hand
+held device example'' - the adaptiveness works perfectly all the
+time. One can set a break point or halt the system in the deep power
+down code, slow step out until the system speeds up.
+
+@b{Solution #2 - Always works - but is slower}
+
+Often this is a perfectly acceptable solution.
+
+In the most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
+the target clock speed. But what is that ``magic division'' it varies
+depending upon the chips on your board. @b{ARM Rule of thumb} Most ARM
+based systems require an 8:1 division. @b{Xilinx Rule of thumb} is
+1/12 the clock speed.
+
+Note: Many FTDI2232C based JTAG dongles are limited to 6mhz.
+
+You can still debug the 'lower power' situations - you just need to
+manually adjust the clock speed at every step. While painful and
+teadious, it is not always practical.
+
+It is however easy to ``code your way around it'' - ie: Cheat a little
+have a special debug mode in your application that does a ``high power
+sleep''. If you are careful - 98% of your problems can be debugged
+this way.
+
+To set the JTAG frequency use the command:
+
+@example
+ # Example: 1.234mhz
+ jtag_khz 1234
+@end example
+
+
+@item @b{Win32 Pathnames} Why does not backslashes in paths under Windows doesn't work?
OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
around Windows filenames.
-@smallexample
+@example
> echo \a
> echo @{\a@}
> echo "\a"
>
-@end smallexample
-To
+@end example
-@item OpenOCD complains about a missing cygwin1.dll.
+
+@item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
Make sure you have Cygwin installed, or at least a version of OpenOCD that
claims to come with all the necessary dlls. When using Cygwin, try launching
OpenOCD from the Cygwin shell.
-@item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
+@item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
software breakpoints consume one of the two available hardware breakpoints.
-@item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
+@item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
and works sometimes fine.
Make sure the core frequency specified in the @option{flash lpc2000} line matches the
frequency, make sure the PLL is disabled, if you've specified the full core speed
(e.g. 60MHz), make sure the PLL is enabled.
-@item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
+@item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
out while waiting for end of scan, rtck was disabled".
Make sure your PC's parallel port operates in EPP mode. You might have to try several
settings in your PC BIOS (ECP, EPP, and different versions of those).
-@item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
+@item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
memory read caused data abort".
a proper "initial" stack frame, if you happen to know what exactly has to
be done, feel free to add this here.
-@item I get the following message in the OpenOCD console (or log file):
+@b{Simple:} In your startup code - push 8 registers of ZEROs onto the
+stack before calling main(). What GDB is doing is ``climbing'' the run
+time stack by reading various values on the stack using the standard
+call frame for the target. GDB keeps going - until one of 2 things
+happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
+stackframes have been processed. By pushing ZEROs on the stack, GDB
+gracefully stops.
+
+@b{Debugging Interrupt Service Routines} - In your ISR before you call
+your C code, do the same, artifically push some zeros on to the stack,
+remember to pop them off when the ISR is done.
+
+@b{Also note:} If you have a multi-threaded operating system, they
+often do not @b{in the intrest of saving memory} waste these few
+bytes. Painful...
+
+
+@item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
"Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
This warning doesn't indicate any serious problem, as long as you don't want to
independently. With this setup, it's not possible to halt the core right out of
reset, everything else should work fine.
-@item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
+@item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
unstable. When single-stepping over large blocks of code, GDB and OpenOCD
quit with an error message. Is there a stability issue with OpenOCD?
Amontec JTAGkey to. Apparently, some computers do not provide a USB power
supply stable enough for the Amontec JTAGkey to be operated.
-@item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
+@b{Laptops running on battery have this problem too...}
+
+@item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
What does that mean and what might be the reason for this?
corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
chip ran into some sort of error - this points us to a USB problem.
-@item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
+@item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
What does that mean and what might be the reason for this?
Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
has closed the connection to OpenOCD. This might be a GDB issue.
-@item In the configuration file in the section where flash device configurations
-are described, there is a parameter for specifying the clock frequency for
-LPC2000 internal flash devices (e.g.
-@option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
-which must be specified in kilohertz. However, I do have a quartz crystal of a
-frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
-Is it possible to specify real numbers for the clock frequency?
+@item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
+are described, there is a parameter for specifying the clock frequency
+for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
+0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
+specified in kilohertz. However, I do have a quartz crystal of a
+frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
+i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
+clock frequency?
No. The clock frequency specified here must be given as an integral number.
However, this clock frequency is used by the In-Application-Programming (IAP)
the given clock frequency, so a slight difference between the specified clock
frequency and the actual clock frequency will not cause any trouble.
-@item Do I have to keep a specific order for the commands in the configuration file?
+@item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
+
+Well, yes and no. Commands can be given in arbitrary order, yet the
+devices listed for the JTAG scan chain must be given in the right
+order (jtag newdevice), with the device closest to the TDO-Pin being
+listed first. In general, whenever objects of the same type exist
+which require an index number, then these objects must be given in the
+right order (jtag newtap, targets and flash banks - a target
+references a jtag newtap and a flash bank references a target).
+
+You can use the ``scan_chain'' command to verify and display the tap order.
+
+@item @b{JTAG Tap Order} JTAG Tap Order - Command Order
+
+Many newer devices have multiple JTAG taps. For example: ST
+Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
+``cortexM3'' tap. Example: The STM32 reference manual, Document ID:
+RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
+connected to the Boundary Scan Tap, which then connects to the
+CortexM3 Tap, which then connects to the TDO pin.
-Well, yes and no. Commands can be given in arbitrary order, yet the devices
-listed for the JTAG scan chain must be given in the right order (jtag_device),
-with the device closest to the TDO-Pin being listed first. In general,
-whenever objects of the same type exist which require an index number, then
-these objects must be given in the right order (jtag_devices, targets and flash
-banks - a target references a jtag_device and a flash bank references a target).
+Thus, the proper order for the STM32 chip is: (1) The CortexM3, then
+(2) The Boundary Scan Tap. If your board includes an additional JTAG
+chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
+place it before or after the stm32 chip in the chain. For example:
-@item Sometimes my debugging session terminates with an error. When I look into the
+@itemize @bullet
+@item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
+@item STM32 BS TDO (output) -> STM32 CortexM3 TDI (input)
+@item STM32 CortexM3 TDO (output) -> SM32 TDO Pin
+@item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
+@item Xilinx TDO Pin -> OpenOCD TDO (input)
+@end itemize
+
+The ``jtag device'' commands would thus be in the order shown below. Note
+
+@itemize @bullet
+@item jtag newtap Xilinx tap -irlen ...
+@item jtag newtap stm32 cpu -irlen ...
+@item jtag newtap stm32 bs -irlen ...
+@item # Create the debug target and say where it is
+@item target create stm32.cpu -chain-position stm32.cpu ...
+@end itemize
+
+
+@item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
log file, I can see these error messages: Error: arm7_9_common.c:561
arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
@end enumerate
+@node TCL Crash Course
+@chapter TCL Crash Course
+@cindex TCL
+
+Not everyone knows TCL - this is not intended to be a replacement for
+learning TCL, the intent of this chapter is to give you some idea of
+how the TCL Scripts work.
+
+This chapter is written with two audiences in mind. (1) OpenOCD users
+who need to understand a bit more of how JIM-Tcl works so they can do
+something useful, and (2) those that want to add a new command to
+OpenOCD.
+
+@section TCL Rule #1
+There is a famous joke, it goes like this:
+@enumerate
+@item Rule #1: The wife is aways correct
+@item Rule #2: If you think otherwise, See Rule #1
+@end enumerate
+
+The TCL equal is this:
+
+@enumerate
+@item Rule #1: Everything is a string
+@item Rule #2: If you think otherwise, See Rule #1
+@end enumerate
+
+As in the famous joke, the consiquences of Rule #1 are profound. Once
+you understand Rule #1, you will understand TCL.
+
+@section TCL Rule #1b
+There is a second pair of rules.
+@enumerate
+@item Rule #1: Control flow does not exist. Only commands
+@* For example: the classic FOR loop or IF statement is not a control
+flow item, they are commands, there is no such thing as control flow
+in TCL.
+@item Rule #2: If you think otherwise, See Rule #1
+@* Actually what happens is this: There are commands that by
+convention, act like control flow key words in other languages. One of
+those commands is the word ``for'', another command is ``if''.
+@end enumerate
+
+@section Per Rule #1 - All Results are strings
+Every TCL command results in a string. The word ``result'' is used
+deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
+Everything is a string}
+
+@section TCL Quoting Operators
+In life of a TCL script, there are two important periods of time, the
+difference is subtle.
+@enumerate
+@item Parse Time
+@item Evaluation Time
+@end enumerate
+
+The two key items here are how ``quoted things'' work in TCL. TCL has
+three primary quoting constructs, the [square-brackets] the
+@{curly-braces@} and ``double-quotes''
+
+By now you should know $VARIABLES always start with a $DOLLAR
+sign. BTW, to set a variable, you actually use the command ``set'', as
+in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
+= 1'' statement, but without the equal sign.
+
+@itemize @bullet
+@item @b{[square-brackets]}
+@* @b{[square-brackets]} are command subsitution. It operates much
+like Unix Shell `back-ticks`. The result of a [square-bracket]
+operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
+string}. These two statments are roughly identical.
+@example
+ # bash example
+ X=`date`
+ echo "The Date is: $X"
+ # TCL example
+ set X [date]
+ puts "The Date is: $X"
+@end example
+@item @b{``double-quoted-things''}
+@* @b{``double-quoted-things''} are just simply quoted
+text. $VARIABLES and [square-brackets] are expanded in place - the
+result however is exactly 1 string. @i{Remember Rule #1 - Everything
+is a string}
+@example
+ set x "Dinner"
+ puts "It is now \"[date]\", $x is in 1 hour"
+@end example
+@item @b{@{Curly-Braces@}}
+@*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
+parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
+'single-quote' operators in BASH shell scripts, with the added
+feature: @{curly-braces@} nest, single quotes can not. @{@{@{this is
+nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
+28/nov/2008, Jim/OpenOCD does not have a date command.
+@end itemize
+
+@section Consiquences of Rule 1/2/3/4
+
+The consiquences of Rule 1 is profound.
+
+@subsection Tokenizing & Execution.
+
+Of course, whitespace, blank lines and #comment lines are handled in
+the normal way.
+
+As a script is parsed, each (multi) line in the script file is
+tokenized and according to the quoting rules. After tokenizing, that
+line is immedatly executed.
+
+Multi line statements end with one or more ``still-open''
+@{curly-braces@} which - eventually - a few lines later closes.
+
+@subsection Command Execution
+
+Remember earlier: There is no such thing as ``control flow''
+statements in TCL. Instead there are COMMANDS that simpily act like
+control flow operators.
+
+Commands are executed like this:
+
+@enumerate
+@item Parse the next line into (argc) and (argv[]).
+@item Look up (argv[0]) in a table and call its function.
+@item Repeat until End Of File.
+@end enumerate
+
+It sort of works like this:
+@example
+ for(;;)@{
+ ReadAndParse( &argc, &argv );
+
+ cmdPtr = LookupCommand( argv[0] );
+
+ (*cmdPtr->Execute)( argc, argv );
+ @}
+@end example
+
+When the command ``proc'' is parsed (which creates a procedure
+function) it gets 3 parameters on the command line. @b{1} the name of
+the proc (function), @b{2} the list of parameters, and @b{3} the body
+of the function. Not the choice of words: LIST and BODY. The PROC
+command stores these items in a table somewhere so it can be found by
+``LookupCommand()''
+
+@subsection The FOR Command
+
+The most interesting command to look at is the FOR command. In TCL,
+the FOR command is normally implimented in C. Remember, FOR is a
+command just like any other command.
+
+When the ascii text containing the FOR command is parsed, the parser
+produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
+are:
+
+@enumerate 0
+@item The ascii text 'for'
+@item The start text
+@item The test expression
+@item The next text
+@item The body text
+@end enumerate
+
+Sort of reminds you of ``main( int argc, char **argv )'' does it not?
+Remember @i{Rule #1 - Everything is a string.} The key point is this:
+Often many of those parameters are in @{curly-braces@} - thus the
+variables inside are not expanded or replaced until later.
+
+Remember that every TCL command looks like the classic ``main( argc,
+argv )'' function in C. In JimTCL - they actually look like this:
+
+@example
+int
+MyCommand( Jim_Interp *interp,
+ int *argc,
+ Jim_Obj * const *argvs );
+@end example
+
+Real TCL is nearly identical. Although the newer versions have
+introduced a byte-code parser and intepreter, but at the core, it
+still operates in the same basic way.
+
+@subsection FOR Command Implimentation
+
+To understand TCL it is perhaps most helpful to see the FOR
+command. Remember, it is a COMMAND not a control flow structure.
+
+In TCL there are two underying C helper functions.
+
+Remember Rule #1 - You are a string.
+
+The @b{first} helper parses and executes commands found in an ascii
+string. Commands can be seperated by semi-colons, or newlines. While
+parsing, variables are expanded per the quoting rules
+
+The @b{second} helper evaluates an ascii string as a numerical
+expression and returns a value.
+
+Here is an example of how the @b{FOR} command could be
+implimented. The pseudo code below does not show error handling.
+@example
+void Execute_AsciiString( void *interp, const char *string );
+
+int Evaluate_AsciiExpression( void *interp, const char *string );
+
+int
+MyForCommand( void *interp,
+ int argc,
+ char **argv )
+@{
+ if( argc != 5 )@{
+ SetResult( interp, "WRONG number of parameters");
+ return ERROR;
+ @}
+
+ // argv[0] = the ascii string just like C
+
+ // Execute the start statement.
+ Execute_AsciiString( interp, argv[1] );
+
+ // Top of loop test
+ for(;;)@{
+ i = Evaluate_AsciiExpression(interp, argv[2]);
+ if( i == 0 )
+ break;
+
+ // Execute the body
+ Execute_AsciiString( interp, argv[3] );
+
+ // Execute the LOOP part
+ Execute_AsciiString( interp, argv[4] );
+ @}
+
+ // Return no error
+ SetResult( interp, "" );
+ return SUCCESS;
+@}
+@end example
+
+Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
+in the same basic way.
+
+@section OpenOCD TCL Usage
+
+@subsection source and find commands
+@b{Where:} In many configuration files
+@* Example: @b{ source [find FILENAME] }
+@*Remember the parsing rules
+@enumerate
+@item The FIND command is in square brackets.
+@* The FIND command is executed with the parameter FILENAME. It should
+find the full path to the named file. The RESULT is a string, which is
+subsituted on the orginal command line.
+@item The command source is executed with the resulting filename.
+@* SOURCE reads a file and executes as a script.
+@end enumerate
+@subsection format command
+@b{Where:} Generally occurs in numerous places.
+@* TCL no command like @b{printf()}, intead it has @b{format}, which is really more like
+@b{sprintf()}.
+@b{Example}
+@example
+ set x 6
+ set y 7
+ puts [format "The answer: %d" [expr $x * $y]]
+@end example
+@enumerate
+@item The SET command creates 2 variables, X and Y.
+@item The double [nested] EXPR command performs math
+@* The EXPR command produces numerical result as a string.
+@* Refer to Rule #1
+@item The format command is executed, producing a single string
+@* Refer to Rule #1.
+@item The PUTS command outputs the text.
+@end enumerate
+@subsection Body Or Inlined Text
+@b{Where:} Various TARGET scripts.
+@example
+#1 Good
+ proc someproc @{@} @{
+ ... multiple lines of stuff ...
+ @}
+ $_TARGETNAME configure -event FOO someproc
+#2 Good - no variables
+ $_TARGETNAME confgure -event foo "this ; that;"
+#3 Good Curly Braces
+ $_TARGETNAME configure -event FOO @{
+ puts "Time: [date]"
+ @}
+#4 DANGER DANGER DANGER
+ $_TARGETNAME configure -event foo "puts \"Time: [date]\""
+@end example
+@enumerate
+@item The $_TARGETNAME is an OpenOCD variable convention.
+@*@b{$_TARGETNAME} represents the last target created, the value changes
+each time a new target is created. Remember the parsing rules. When
+the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
+the name of the target which happens to be a TARGET (object)
+command.
+@item The 2nd parameter to the @option{-event} parameter is a TCBODY
+@*There are 4 examples:
+@enumerate
+@item The TCLBODY is a simple string that happens to be a proc name
+@item The TCLBODY is several simple commands semi-colon seperated
+@item The TCLBODY is a multi-line @{curly-brace@} quoted string
+@item The TCLBODY is a string with variables that get expanded.
+@end enumerate
+
+In the end, when the target event FOO occurs the TCLBODY is
+evaluated. Method @b{#1} and @b{#2} are functionally identical. For
+Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
+
+Remember the parsing rules. In case #3, @{curly-braces@} mean the
+$VARS and [square-brackets] are expanded later, when the EVENT occurs,
+and the text is evaluated. In case #4, they are replaced before the
+``Target Object Command'' is executed. This occurs at the same time
+$_TARGETNAME is replaced. In case #4 the date will never
+change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
+Jim/OpenOCD does not have a date command@}
+@end enumerate
+@subsection Global Variables
+@b{Where:} You might discover this when writing your own procs @* In
+simple terms: Inside a PROC, if you need to access a global variable
+you must say so. Also see ``upvar''. Example:
+@example
+proc myproc @{ @} @{
+ set y 0 #Local variable Y
+ global x #Global variable X
+ puts [format "X=%d, Y=%d" $x $y]
+@}
+@end example
+@section Other Tcl Hacks
+@b{Dynamic Variable Creation}
+@example
+# Dynamically create a bunch of variables.
+for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
+ # Create var name
+ set vn [format "BIT%d" $x]
+ # Make it a global
+ global $vn
+ # Set it.
+ set $vn [expr (1 << $x)]
+@}
+@end example
+@b{Dynamic Proc/Command Creation}
+@example
+# One "X" function - 5 uart functions.
+foreach who @{A B C D E@}
+ proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
+@}
+@end example
+
+@node Target library
+@chapter Target library
+@cindex Target library
+
+OpenOCD comes with a target configuration script library. These scripts can be
+used as-is or serve as a starting point.
+
+The target library is published together with the openocd executable and
+the path to the target library is in the OpenOCD script search path.
+Similarly there are example scripts for configuring the JTAG interface.
+
+The command line below uses the example parport configuration scripts
+that ship with OpenOCD, then configures the str710.cfg target and
+finally issues the init and reset command. The communication speed
+is set to 10kHz for reset and 8MHz for post reset.
+
+
+@example
+openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
+@end example
+
+
+To list the target scripts available:
+
+@example
+$ ls /usr/local/lib/openocd/target
+
+arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
+at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
+at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
+at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
+@end example
+
+
+
@include fdl.texi
-@node Index
-@unnumbered Index
+@node OpenOCD Index
+@comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
+@comment case issue with ``Index.html'' and ``index.html''
+@comment Occurs when creating ``--html --no-split'' output
+@comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
+@unnumbered OpenOCD Index
@printindex cp
return ERROR_OK;
}
-int str9xpec_set_instr(int chain_pos, u32 new_instr, enum tap_state end_state)
+int str9xpec_set_instr(jtag_tap_t *tap, u32 new_instr, enum tap_state end_state)
{
- jtag_device_t *device = jtag_get_device(chain_pos);
- if (device == NULL)
- {
+ if( tap == NULL ){
return ERROR_TARGET_INVALID;
}
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
- field.device = chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
return ERROR_OK;
}
-u8 str9xpec_isc_status(int chain_pos)
+u8 str9xpec_isc_status(jtag_tap_t *tap)
{
scan_field_t field;
u8 status;
- if (str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI) != ERROR_OK)
+ if (str9xpec_set_instr(tap, ISC_NOOP, TAP_PI) != ERROR_OK)
return ISC_STATUS_ERROR;
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = NULL;
field.out_mask = NULL;
int str9xpec_isc_enable(struct flash_bank_s *bank)
{
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (str9xpec_info->isc_enable)
return ERROR_OK;
/* enter isc mode */
- if (str9xpec_set_instr(chain_pos, ISC_ENABLE, TAP_RTI) != ERROR_OK)
+ if (str9xpec_set_instr(tap, ISC_ENABLE, TAP_RTI) != ERROR_OK)
return ERROR_TARGET_INVALID;
/* check ISC status */
- status = str9xpec_isc_status(chain_pos);
+ status = str9xpec_isc_status(tap);
if (status & ISC_STATUS_MODE)
{
/* we have entered isc mode */
int str9xpec_isc_disable(struct flash_bank_s *bank)
{
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (!str9xpec_info->isc_enable)
return ERROR_OK;
- if (str9xpec_set_instr(chain_pos, ISC_DISABLE, TAP_RTI) != ERROR_OK)
+ if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_RTI) != ERROR_OK)
return ERROR_TARGET_INVALID;
/* delay to handle aborts */
jtag_add_sleep(50);
/* check ISC status */
- status = str9xpec_isc_status(chain_pos);
+ status = str9xpec_isc_status(tap);
if (!(status & ISC_STATUS_MODE))
{
/* we have left isc mode */
{
scan_field_t field;
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
LOG_DEBUG("ISC_CONFIGURATION");
/* execute ISC_CONFIGURATION command */
- str9xpec_set_instr(chain_pos, ISC_CONFIGURATION, TAP_PI);
+ str9xpec_set_instr(tap, ISC_CONFIGURATION, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = NULL;
field.out_mask = NULL;
jtag_add_dr_scan(1, &field, TAP_RTI);
jtag_execute_queue();
- status = str9xpec_isc_status(chain_pos);
+ status = str9xpec_isc_status(tap);
return status;
}
arm7_9 = armv4_5->arch_info;
jtag_info = &arm7_9->jtag_info;
- str9xpec_info->chain_pos = (jtag_info->chain_pos - 1);
+
+
+ str9xpec_info->tap = jtag_TapByAbsPosition( jtag_info->tap->abs_chain_position - 1);
str9xpec_info->isc_enable = 0;
- str9xpec_info->devarm = NULL;
+
str9xpec_build_block_list(bank);
{
scan_field_t field;
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
int i;
u8 *buffer = NULL;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (!str9xpec_info->isc_enable) {
str9xpec_isc_enable( bank );
}
/* execute ISC_BLANK_CHECK command */
- str9xpec_set_instr(chain_pos, ISC_BLANK_CHECK, TAP_PI);
+ str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = buffer;
field.out_mask = NULL;
jtag_add_sleep(40000);
/* read blank check result */
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = NULL;
field.out_mask = NULL;
jtag_add_dr_scan(1, &field, TAP_PI);
jtag_execute_queue();
- status = str9xpec_isc_status(chain_pos);
+ status = str9xpec_isc_status(tap);
for (i = first; i <= last; i++)
{
{
scan_field_t field;
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
int i;
u8 *buffer = NULL;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (!str9xpec_info->isc_enable) {
str9xpec_isc_enable( bank );
LOG_DEBUG("ISC_ERASE");
/* execute ISC_ERASE command */
- str9xpec_set_instr(chain_pos, ISC_ERASE, TAP_PI);
+ str9xpec_set_instr(tap, ISC_ERASE, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = buffer;
field.out_mask = NULL;
jtag_add_sleep(10);
/* wait for erase completion */
- while (!((status = str9xpec_isc_status(chain_pos)) & ISC_STATUS_BUSY)) {
+ while (!((status = str9xpec_isc_status(tap)) & ISC_STATUS_BUSY)) {
alive_sleep(1);
}
{
scan_field_t field;
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = NULL;
str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (!str9xpec_info->isc_enable) {
str9xpec_isc_enable( bank );
str9xpec_set_address(bank, 0x80);
/* execute ISC_PROGRAM command */
- str9xpec_set_instr(chain_pos, ISC_PROGRAM_SECURITY, TAP_RTI);
+ str9xpec_set_instr(tap, ISC_PROGRAM_SECURITY, TAP_RTI);
- str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
do {
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = NULL;
field.out_mask = NULL;
int str9xpec_set_address(struct flash_bank_s *bank, u8 sector)
{
- u32 chain_pos;
+ jtag_tap_t *tap;
scan_field_t field;
str9xpec_flash_controller_t *str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
/* set flash controller address */
- str9xpec_set_instr(chain_pos, ISC_ADDRESS_SHIFT, TAP_PI);
+ str9xpec_set_instr(tap, ISC_ADDRESS_SHIFT, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = §or;
field.out_mask = NULL;
u32 bytes_written = 0;
u8 status;
u32 check_address = offset;
- u32 chain_pos;
+ jtag_tap_t *tap;
scan_field_t field;
u8 *scanbuf;
int i;
u32 first_sector = 0;
u32 last_sector = 0;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
if (!str9xpec_info->isc_enable) {
str9xpec_isc_enable(bank);
while (dwords_remaining > 0)
{
- str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI);
+ str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = (buffer + bytes_written);
field.out_mask = NULL;
/* small delay before polling */
jtag_add_sleep(50);
- str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
do {
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = NULL;
field.out_mask = NULL;
bytes_written++;
}
- str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI);
+ str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = last_dword;
field.out_mask = NULL;
/* small delay before polling */
jtag_add_sleep(50);
- str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
do {
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = NULL;
field.out_mask = NULL;
flash_bank_t *bank;
scan_field_t field;
u8 *buffer = NULL;
- u32 chain_pos;
+ jtag_tap_t *tap;
u32 idcode;
str9xpec_flash_controller_t *str9xpec_info = NULL;
}
str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
buffer = calloc(CEIL(32, 8), 1);
- str9xpec_set_instr(chain_pos, ISC_IDCODE, TAP_PI);
+ str9xpec_set_instr(tap, ISC_IDCODE, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 32;
field.out_value = NULL;
field.out_mask = NULL;
{
scan_field_t field;
u8 status;
- u32 chain_pos;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = NULL;
str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
/* erase config options first */
status = str9xpec_erase_area( bank, 0xFE, 0xFE );
str9xpec_set_address(bank, 0x50);
/* execute ISC_PROGRAM command */
- str9xpec_set_instr(chain_pos, ISC_PROGRAM, TAP_PI);
+ str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 64;
field.out_value = str9xpec_info->options;
field.out_mask = NULL;
/* small delay before polling */
jtag_add_sleep(50);
- str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
do {
- field.device = chain_pos;
+ field.tap = tap;
field.num_bits = 8;
field.out_value = NULL;
field.out_mask = NULL;
int str9xpec_handle_flash_enable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
+#if 1
+ command_print( cmd_ctx, "**STR9FLASH is currently broken :-( **");
+ return ERROR_OK;
+#else
int retval;
flash_bank_t *bank;
- u32 chain_pos;
- jtag_device_t* dev0;
- jtag_device_t* dev2;
+ jtag_tap_t *tapX;
+ jtag_tap_t *tap0;
+ jtag_tap_t *tap1;
+ jtag_tap_t *tap2;
str9xpec_flash_controller_t *str9xpec_info = NULL;
if (argc < 1)
str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tapX = str9xpec_info->tap;
/* remove arm core from chain - enter turbo mode */
+ //
+ // At postion +2 in the chain,
+ // I do not think this is right..
+ // I have not tested it...
+ // and it is a bit wacky right now.
+ // -- Duane 25/nov/2008
+ tap0 = tapX;
+ tap1 = tap0->next_tap;
+ if( tap1 == NULL ){
+ // things are *WRONG*
+ command_print(cmd_ctx,"**STR9FLASH** (tap1) invalid chain?");
+ return ERROR_OK;
+ }
+ tap2 = tap1->next_tap;
+ if( tap2 == NULL ){
+ // things are *WRONG*
+ command_print(cmd_ctx,"**STR9FLASH** (tap2) invalid chain?");
+ return ERROR_OK;
+ }
- str9xpec_set_instr(chain_pos+2, 0xD, TAP_RTI);
+ // this instruction disables the arm9 tap
+ str9xpec_set_instr(tap2, 0xD, TAP_RTI);
if ((retval=jtag_execute_queue())!=ERROR_OK)
return retval;
/* modify scan chain - str9 core has been removed */
- dev0 = jtag_get_device(chain_pos);
- if (dev0 == NULL)
- return ERROR_FAIL;
- str9xpec_info->devarm = jtag_get_device(chain_pos+1);
- dev2 = jtag_get_device(chain_pos+2);
- if (dev2 == NULL)
- return ERROR_FAIL;
- dev0->next = dev2;
- jtag_num_devices--;
+ str9xpec_info->devarm = tap1;
+ tap1->enabled = 0;
return ERROR_OK;
+#endif
}
int str9xpec_handle_flash_disable_turbo_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
flash_bank_t *bank;
- u32 chain_pos;
- jtag_device_t* dev0;
+ jtag_tap_t *tap;
str9xpec_flash_controller_t *str9xpec_info = NULL;
if (argc < 1)
str9xpec_info = bank->driver_priv;
- chain_pos = str9xpec_info->chain_pos;
+ tap = str9xpec_info->tap;
- dev0 = jtag_get_device(chain_pos);
- if (dev0 == NULL)
+ if (tap == NULL)
return ERROR_FAIL;
/* exit turbo mode via TLR */
- str9xpec_set_instr(chain_pos, ISC_NOOP, TAP_TLR);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_TLR);
jtag_execute_queue();
-
/* restore previous scan chain */
- if( str9xpec_info->devarm ) {
- dev0->next = str9xpec_info->devarm;
- jtag_num_devices++;
- str9xpec_info->devarm = NULL;
+ if( tap->next_tap ){
+ tap->next_tap->enabled = 1;
}
return ERROR_OK;
typedef struct str9xpec_flash_controller_s
{
+ jtag_tap_t *tap;
u32 *sector_bits;
int chain_pos;
int isc_enable;
- jtag_device_t* devarm;
u8 options[8];
} str9xpec_flash_controller_t;
#endif
+typedef struct jtag_tap_s jtag_tap_t;
+
/* DANGER!!!! here be dragons! Note that the pointer in
* memory might be unaligned. On some CPU's, i.e. ARM7,
jtag_command_t *jtag_command_queue = NULL;
jtag_command_t **last_comand_pointer = &jtag_command_queue;
-jtag_device_t *jtag_devices = NULL;
-int jtag_num_devices = 0;
-int jtag_ir_scan_size = 0;
+static jtag_tap_t *jtag_all_taps = NULL;
+
enum reset_types jtag_reset_config = RESET_NONE;
enum tap_state cmd_queue_end_state = TAP_TLR;
enum tap_state cmd_queue_cur_state = TAP_TLR;
int handle_verify_ircapture_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+
+jtag_tap_t *jtag_AllTaps(void)
+{
+ return jtag_all_taps;
+};
+
+int
+jtag_NumTotalTaps(void)
+{
+ jtag_tap_t *t;
+ int n;
+
+ n = 0;
+ t = jtag_AllTaps();
+ while(t){
+ n++;
+ t = t->next_tap;
+ }
+ return n;
+}
+
+int
+jtag_NumEnabledTaps(void)
+{
+ jtag_tap_t *t;
+ int n;
+
+ n = 0;
+ t = jtag_AllTaps();
+ while(t){
+ if( t->enabled ){
+ n++;
+ }
+ t = t->next_tap;
+ }
+ return n;
+}
+
+jtag_tap_t *
+jtag_NextEnabledTap( jtag_tap_t *p )
+{
+ if( p == NULL ){
+ // start at the head of list
+ p = jtag_AllTaps();
+ } else {
+ // start *after* this one
+ p = p->next_tap;
+ }
+ while( p ){
+ if( p->enabled ){
+ break;
+ } else {
+ p = p->next_tap;
+ }
+ }
+ return p;
+}
+
+jtag_tap_t *jtag_TapByString( const char *s )
+{
+ jtag_tap_t *t;
+ char *cp;
+
+ t = jtag_AllTaps();
+ // try name first
+ while(t){
+ if( 0 == strcmp( t->dotted_name, s ) ){
+ break;
+ } else {
+ t = t->next_tap;
+ }
+ }
+ // backup plan is by number
+ if( t == NULL ){
+ /* ok - is "s" a number? */
+ int n;
+ n = strtol( s, &cp, 0 );
+ if( (s != cp) && (*cp == 0) ){
+ /* Then it is... */
+ t = jtag_TapByAbsPosition(n);
+ }
+ }
+ return t;
+}
+
+jtag_tap_t *
+jtag_TapByJimObj( Jim_Interp *interp, Jim_Obj *o )
+{
+ jtag_tap_t *t;
+ const char *cp;
+
+ cp = Jim_GetString( o, NULL );
+ if(cp == NULL){
+ cp = "(unknown)";
+ t = NULL;
+ } else {
+ t = jtag_TapByString( cp );
+ }
+ if( t == NULL ){
+ Jim_SetResult_sprintf(interp,"Tap: %s is unknown", cp );
+ }
+ return t;
+}
+
+/* returns a pointer to the n-th device in the scan chain */
+jtag_tap_t *
+jtag_TapByAbsPosition( int n )
+{
+ int orig_n;
+ jtag_tap_t *t;
+
+ orig_n = n;
+ t = jtag_AllTaps();
+
+ while( t && (n > 0)) {
+ n--;
+ t = t->next_tap;
+ }
+ return t;
+}
+
+
int jtag_register_event_callback(int (*callback)(enum jtag_event event, void *priv), void *priv)
{
jtag_event_callback_t **callbacks_p = &jtag_event_callbacks;
return last_comand_pointer;
}
-/* returns a pointer to the n-th device in the scan chain */
-jtag_device_t* jtag_get_device(int num)
-{
- jtag_device_t *device = jtag_devices;
- int i = 0;
-
- while (device)
- {
- if (num == i)
- return device;
- device = device->next;
- i++;
- }
-
- LOG_ERROR("jtag device number %d not defined", num);
- return NULL;
-}
void* cmd_queue_alloc(size_t size)
{
int MINIDRIVER(interface_jtag_add_ir_scan)(int num_fields, scan_field_t *fields, enum tap_state state)
{
jtag_command_t **last_cmd;
- jtag_device_t *device;
- int i, j;
+ jtag_tap_t *tap;
+ int j;
+ int x;
+ int nth_tap;
int scan_size = 0;
/* allocate memory for ir scan command */
(*last_cmd)->cmd.scan = cmd_queue_alloc(sizeof(scan_command_t));
(*last_cmd)->cmd.scan->ir_scan = 1;
- (*last_cmd)->cmd.scan->num_fields = jtag_num_devices; /* one field per device */
- (*last_cmd)->cmd.scan->fields = cmd_queue_alloc(jtag_num_devices * sizeof(scan_field_t));
+ x = jtag_NumEnabledTaps();
+ (*last_cmd)->cmd.scan->num_fields = x; /* one field per device */
+ (*last_cmd)->cmd.scan->fields = cmd_queue_alloc(x * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = state;
- for (i = 0; i < jtag_num_devices; i++)
- {
+ nth_tap = -1;
+ tap = NULL;
+ for(;;){
int found = 0;
- device = jtag_get_device(i);
- if (device == NULL)
- {
- exit(-1);
+
+ // do this here so it is not forgotten
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
}
- scan_size = device->ir_length;
- (*last_cmd)->cmd.scan->fields[i].device = i;
- (*last_cmd)->cmd.scan->fields[i].num_bits = scan_size;
- (*last_cmd)->cmd.scan->fields[i].in_value = NULL;
- (*last_cmd)->cmd.scan->fields[i].in_handler = NULL; /* disable verification by default */
+ nth_tap++;
+ scan_size = tap->ir_length;
+ (*last_cmd)->cmd.scan->fields[nth_tap].tap = tap;
+ (*last_cmd)->cmd.scan->fields[nth_tap].num_bits = scan_size;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_value = NULL;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_handler = NULL; /* disable verification by default */
/* search the list */
for (j = 0; j < num_fields; j++)
{
- if (i == fields[j].device)
+ if (tap == fields[j].tap)
{
found = 1;
- (*last_cmd)->cmd.scan->fields[i].out_value = buf_cpy(fields[j].out_value, cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
- (*last_cmd)->cmd.scan->fields[i].out_mask = buf_cpy(fields[j].out_mask, cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
+ (*last_cmd)->cmd.scan->fields[nth_tap].out_value = buf_cpy(fields[j].out_value, cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
+ (*last_cmd)->cmd.scan->fields[nth_tap].out_mask = buf_cpy(fields[j].out_mask, cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
if (jtag_verify_capture_ir)
{
if (fields[j].in_handler==NULL)
{
- jtag_set_check_value((*last_cmd)->cmd.scan->fields+i, device->expected, device->expected_mask, NULL);
+ jtag_set_check_value((*last_cmd)->cmd.scan->fields+nth_tap, tap->expected, tap->expected_mask, NULL);
} else
{
- (*last_cmd)->cmd.scan->fields[i].in_handler = fields[j].in_handler;
- (*last_cmd)->cmd.scan->fields[i].in_handler_priv = fields[j].in_handler_priv;
- (*last_cmd)->cmd.scan->fields[i].in_check_value = device->expected;
- (*last_cmd)->cmd.scan->fields[i].in_check_mask = device->expected_mask;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_handler = fields[j].in_handler;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_handler_priv = fields[j].in_handler_priv;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_check_value = tap->expected;
+ (*last_cmd)->cmd.scan->fields[nth_tap].in_check_mask = tap->expected_mask;
}
}
- device->bypass = 0;
+ tap->bypass = 0;
break;
}
}
if (!found)
{
- /* if a device isn't listed, set it to BYPASS */
- (*last_cmd)->cmd.scan->fields[i].out_value = buf_set_ones(cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
- (*last_cmd)->cmd.scan->fields[i].out_mask = NULL;
- device->bypass = 1;
+ /* if a tap isn't listed, set it to BYPASS */
+ (*last_cmd)->cmd.scan->fields[nth_tap].out_value = buf_set_ones(cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
+ (*last_cmd)->cmd.scan->fields[nth_tap].out_mask = NULL;
+ tap->bypass = 1;
}
/* update device information */
- buf_cpy((*last_cmd)->cmd.scan->fields[i].out_value, jtag_get_device(i)->cur_instr, scan_size);
+ buf_cpy((*last_cmd)->cmd.scan->fields[nth_tap].out_value, tap->cur_instr, scan_size);
}
return ERROR_OK;
(*last_cmd)->cmd.scan->fields = cmd_queue_alloc(num_fields * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = state;
- for (i = 0; i < num_fields; i++)
- {
+ for( i = 0 ; i < num_fields ; i++ ){
int num_bits = fields[i].num_bits;
int num_bytes = CEIL(fields[i].num_bits, 8);
- (*last_cmd)->cmd.scan->fields[i].device = fields[i].device;
+ (*last_cmd)->cmd.scan->fields[i].tap = fields[i].tap;
(*last_cmd)->cmd.scan->fields[i].num_bits = num_bits;
(*last_cmd)->cmd.scan->fields[i].out_value = buf_cpy(fields[i].out_value, cmd_queue_alloc(num_bytes), num_bits);
(*last_cmd)->cmd.scan->fields[i].out_mask = buf_cpy(fields[i].out_mask, cmd_queue_alloc(num_bytes), num_bits);
int MINIDRIVER(interface_jtag_add_dr_scan)(int num_fields, scan_field_t *fields, enum tap_state state)
{
- int i, j;
+ int j;
+ int nth_tap;
int bypass_devices = 0;
int field_count = 0;
int scan_size;
jtag_command_t **last_cmd = jtag_get_last_command_p();
- jtag_device_t *device = jtag_devices;
+ jtag_tap_t *tap;
/* count devices in bypass */
- while (device)
- {
- if (device->bypass)
+ tap = NULL;
+ bypass_devices = 0;
+ for(;;){
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
+ if( tap->bypass ){
bypass_devices++;
- device = device->next;
- }
- if (bypass_devices >= jtag_num_devices)
- {
- LOG_ERROR("all devices in bypass");
- return ERROR_JTAG_DEVICE_ERROR;
+ }
}
/* allocate memory for a new list member */
(*last_cmd)->cmd.scan->fields = cmd_queue_alloc((num_fields + bypass_devices) * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = state;
- for (i = 0; i < jtag_num_devices; i++)
- {
+ tap = NULL;
+ nth_tap = -1;
+ for(;;){
+ nth_tap++;
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
int found = 0;
- (*last_cmd)->cmd.scan->fields[field_count].device = i;
+ (*last_cmd)->cmd.scan->fields[field_count].tap = tap;
for (j = 0; j < num_fields; j++)
{
- if (i == fields[j].device)
+ if (tap == fields[j].tap)
{
found = 1;
scan_size = fields[j].num_bits;
{
#ifdef _DEBUG_JTAG_IO_
/* if a device isn't listed, the BYPASS register should be selected */
- if (!jtag_get_device(i)->bypass)
+ if (! tap->bypass)
{
LOG_ERROR("BUG: no scan data for a device not in BYPASS");
exit(-1);
{
#ifdef _DEBUG_JTAG_IO_
/* if a device is listed, the BYPASS register must not be selected */
- if (jtag_get_device(i)->bypass)
+ if (tap->bypass)
{
LOG_ERROR("BUG: scan data for a device in BYPASS");
exit(-1);
return ERROR_OK;
}
-void MINIDRIVER(interface_jtag_add_dr_out)(int device_num,
+void MINIDRIVER(interface_jtag_add_dr_out)(jtag_tap_t *target_tap,
int num_fields,
const int *num_bits,
const u32 *value,
enum tap_state end_state)
{
- int i;
+ int nth_tap;
int field_count = 0;
int scan_size;
int bypass_devices = 0;
jtag_command_t **last_cmd = jtag_get_last_command_p();
- jtag_device_t *device = jtag_devices;
+ jtag_tap_t *tap;
+
/* count devices in bypass */
- while (device)
- {
- if (device->bypass)
+ tap = NULL;
+ bypass_devices = 0;
+ for(;;){
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
+ if( tap->bypass ){
bypass_devices++;
- device = device->next;
+ }
}
/* allocate memory for a new list member */
(*last_cmd)->cmd.scan->fields = cmd_queue_alloc((num_fields + bypass_devices) * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = end_state;
- for (i = 0; i < jtag_num_devices; i++)
- {
- (*last_cmd)->cmd.scan->fields[field_count].device = i;
+ tap = NULL;
+ nth_tap = -1;
+ for(;;){
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
+ nth_tap++;
+ (*last_cmd)->cmd.scan->fields[field_count].tap = tap;
- if (i == device_num)
+ if (tap == target_tap)
{
int j;
#ifdef _DEBUG_JTAG_IO_
/* if a device is listed, the BYPASS register must not be selected */
- if (jtag_get_device(i)->bypass)
+ if (tap->bypass)
{
LOG_ERROR("BUG: scan data for a device in BYPASS");
exit(-1);
{
#ifdef _DEBUG_JTAG_IO_
/* if a device isn't listed, the BYPASS register should be selected */
- if (!jtag_get_device(i)->bypass)
+ if (! tap->bypass)
{
LOG_ERROR("BUG: no scan data for a device not in BYPASS");
exit(-1);
{
int num_bits = fields[i].num_bits;
int num_bytes = CEIL(fields[i].num_bits, 8);
- (*last_cmd)->cmd.scan->fields[i].device = fields[i].device;
+ (*last_cmd)->cmd.scan->fields[i].tap = fields[i].tap;
(*last_cmd)->cmd.scan->fields[i].num_bits = num_bits;
(*last_cmd)->cmd.scan->fields[i].out_value = buf_cpy(fields[i].out_value, cmd_queue_alloc(num_bytes), num_bits);
(*last_cmd)->cmd.scan->fields[i].out_mask = buf_cpy(fields[i].out_mask, cmd_queue_alloc(num_bytes), num_bits);
else
compare_failed = buf_cmp(captured, field->in_check_value, num_bits);
- if (compare_failed)
- {
+ if (compare_failed){
/* An error handler could have caught the failing check
* only report a problem when there wasn't a handler, or if the handler
* acknowledged the error
*/
+ LOG_WARNING("TAP %s:",
+ (field->tap == NULL) ? "(unknown)" : field->tap->dotted_name );
if (compare_failed)
{
char *captured_char = buf_to_str(captured, (num_bits > 64) ? 64 : num_bits, 16);
{
char *in_check_mask_char;
in_check_mask_char = buf_to_str(field->in_check_mask, (num_bits > 64) ? 64 : num_bits, 16);
- LOG_WARNING("value captured during scan didn't pass the requested check: captured: 0x%s check_value: 0x%s check_mask: 0x%s", captured_char, in_check_value_char, in_check_mask_char);
+ LOG_WARNING("value captured during scan didn't pass the requested check:");
+ LOG_WARNING("captured: 0x%s check_value: 0x%s check_mask: 0x%s",
+ captured_char, in_check_value_char, in_check_mask_char);
free(in_check_mask_char);
}
else
int jtag_reset_callback(enum jtag_event event, void *priv)
{
- jtag_device_t *device = priv;
+ jtag_tap_t *tap = priv;
LOG_DEBUG("-");
if (event == JTAG_TRST_ASSERTED)
{
- buf_set_ones(device->cur_instr, device->ir_length);
- device->bypass = 1;
+ buf_set_ones(tap->cur_instr, tap->ir_length);
+ tap->bypass = 1;
}
return ERROR_OK;
*/
int jtag_examine_chain(void)
{
- jtag_device_t *device = jtag_devices;
+ jtag_tap_t *tap;
scan_field_t field;
u8 idcode_buffer[JTAG_MAX_CHAIN_SIZE * 4];
int i;
u8 zero_check = 0x0;
u8 one_check = 0xff;
- field.device = 0;
+ field.tap = NULL;
field.num_bits = sizeof(idcode_buffer) * 8;
field.out_value = idcode_buffer;
field.out_mask = NULL;
return ERROR_JTAG_INIT_FAILED;
}
+ // point at the 1st tap
+ tap = jtag_NextEnabledTap(NULL);
+ if( tap == NULL ){
+ LOG_ERROR("JTAG: No taps enabled?");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
for (bit_count = 0; bit_count < (JTAG_MAX_CHAIN_SIZE * 32) - 31;)
{
u32 idcode = buf_get_u32(idcode_buffer, bit_count, 32);
if ((idcode & 1) == 0)
{
/* LSB must not be 0, this indicates a device in bypass */
- LOG_WARNING("Device does not have IDCODE");
+ LOG_WARNING("Tap/Device does not have IDCODE");
idcode=0;
bit_count += 1;
break;
}
- manufacturer = (idcode & 0xffe) >> 1;
- part = (idcode & 0xffff000) >> 12;
- version = (idcode & 0xf0000000) >> 28;
+#define EXTRACT_MFG(X) (((X) & 0xffe) >> 1)
+ manufacturer = EXTRACT_MFG(idcode);
+#define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
+ part = EXTRACT_PART(idcode);
+#define EXTRACT_VER(X) (((X) & 0xf0000000) >> 28)
+ version = EXTRACT_VER(idcode);
- LOG_INFO("JTAG device found: 0x%8.8x (Manufacturer: 0x%3.3x, Part: 0x%4.4x, Version: 0x%1.1x)",
+ LOG_INFO("JTAG tap: %s tap/device found: 0x%8.8x (Manufacturer: 0x%3.3x, Part: 0x%4.4x, Version: 0x%1.1x)",
+ ((tap != NULL) ? (tap->dotted_name) : "(not-named)"),
idcode, manufacturer, part, version);
bit_count += 32;
}
- if (device)
+ if (tap)
{
- device->idcode = idcode;
- device = device->next;
+ tap->idcode = idcode;
+ if( tap->expected_id ){
+ if( tap->idcode != tap->expected_id ){
+ LOG_ERROR("ERROR: Tap: %s - Expected id: 0x%08x, Got: 0x%08x",
+ tap->dotted_name,
+ tap->expected_id,
+ idcode );
+ LOG_ERROR("ERROR: expected: mfg: 0x%3.3x, part: 0x%4.4x, ver: 0x%1.1x",
+ EXTRACT_MFG( tap->expected_id ),
+ EXTRACT_PART( tap->expected_id ),
+ EXTRACT_VER( tap->expected_id ) );
+ LOG_ERROR("ERROR: got: mfg: 0x%3.3x, part: 0x%4.4x, ver: 0x%1.1x",
+ EXTRACT_MFG( tap->idcode ),
+ EXTRACT_PART( tap->idcode ),
+ EXTRACT_VER( tap->idcode ) );
+ } else {
+ LOG_INFO("JTAG Tap/device matched");
+ }
+ } else {
+#if 0
+ LOG_INFO("JTAG TAP ID: 0x%08x - Unknown - please report (A) chipname and (B) idcode to the openocd project",
+ tap->idcode);
+#endif
+ }
+ tap = jtag_NextEnabledTap(tap);
}
device_count++;
}
/* see if number of discovered devices matches configuration */
- if (device_count != jtag_num_devices)
+ if (device_count != jtag_NumEnabledTaps())
{
- LOG_ERROR("number of discovered devices in JTAG chain (%i) doesn't match configuration (%i)",
- device_count, jtag_num_devices);
+ LOG_ERROR("number of discovered devices in JTAG chain (%i) doesn't match (enabled) configuration (%i), total taps: %d",
+ device_count, jtag_NumEnabledTaps(), jtag_NumTotalTaps());
LOG_ERROR("check the config file and ensure proper JTAG communication (connections, speed, ...)");
return ERROR_JTAG_INIT_FAILED;
}
int jtag_validate_chain(void)
{
- jtag_device_t *device = jtag_devices;
+ jtag_tap_t *tap;
int total_ir_length = 0;
u8 *ir_test = NULL;
scan_field_t field;
int chain_pos = 0;
- while (device)
- {
- total_ir_length += device->ir_length;
- device = device->next;
+ tap = NULL;
+ total_ir_length = 0;
+ for(;;){
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
+ total_ir_length += tap->ir_length;
}
total_ir_length += 2;
ir_test = malloc(CEIL(total_ir_length, 8));
buf_set_ones(ir_test, total_ir_length);
- field.device = 0;
+ field.tap = NULL;
field.num_bits = total_ir_length;
field.out_value = ir_test;
field.out_mask = NULL;
jtag_add_plain_ir_scan(1, &field, TAP_TLR);
jtag_execute_queue();
- device = jtag_devices;
- while (device)
- {
+ tap = NULL;
+ chain_pos = 0;
+ for(;;){
+ tap = jtag_NextEnabledTap(tap);
+ if( tap == NULL ){
+ break;
+ }
+
+
if (buf_get_u32(ir_test, chain_pos, 2) != 0x1)
{
char *cbuf = buf_to_str(ir_test, total_ir_length, 16);
free(ir_test);
return ERROR_JTAG_INIT_FAILED;
}
- chain_pos += device->ir_length;
- device = device->next;
+ chain_pos += tap->ir_length;
}
if (buf_get_u32(ir_test, chain_pos, 2) != 0x3)
}
+static int
+jim_newtap_cmd( Jim_GetOptInfo *goi )
+{
+ jtag_tap_t *pTap;
+ jtag_tap_t **ppTap;
+ jim_wide w;
+ int x;
+ int e;
+ int reqbits;
+ Jim_Nvp *n;
+ char *cp;
+ const Jim_Nvp opts[] = {
+#define NTAP_OPT_IRLEN 0
+ { .name = "-irlen" , .value = NTAP_OPT_IRLEN },
+#define NTAP_OPT_IRMASK 1
+ { .name = "-irmask" , .value = NTAP_OPT_IRMASK },
+#define NTAP_OPT_IRCAPTURE 2
+ { .name = "-ircapture" , .value = NTAP_OPT_IRCAPTURE },
+#define NTAP_OPT_ENABLED 3
+ { .name = "-enable" , .value = NTAP_OPT_ENABLED },
+#define NTAP_OPT_DISABLED 4
+ { .name = "-disable" , .value = NTAP_OPT_DISABLED },
+#define NTAP_OPT_EXPECTED_ID 5
+ { .name = "-expected-id" , .value = NTAP_OPT_EXPECTED_ID },
+ { .name = NULL , .value = -1 },
+ };
+
+
+ pTap = malloc( sizeof(jtag_tap_t) );
+ memset( pTap, 0, sizeof(*pTap) );
+ if( !pTap ){
+ Jim_SetResult_sprintf( goi->interp, "no memory");
+ return JIM_ERR;
+ }
+ //
+ // we expect CHIP + TAP + OPTIONS
+ //
+ if( goi->argc < 3 ){
+ Jim_SetResult_sprintf(goi->interp, "Missing CHIP TAP OPTIONS ....");
+ return JIM_ERR;
+ }
+ Jim_GetOpt_String( goi, &cp, NULL );
+ pTap->chip = strdup(cp);
+
+ Jim_GetOpt_String( goi, &cp, NULL );
+ pTap->tapname = strdup(cp);
+
+ // name + dot + name + null
+ x = strlen(pTap->chip) + 1 + strlen(pTap->tapname) + 1;
+ cp = malloc( x );
+ sprintf( cp, "%s.%s", pTap->chip, pTap->tapname );
+ pTap->dotted_name = cp;
+
+ LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params",
+ pTap->chip, pTap->tapname, pTap->dotted_name, goi->argc);
+
+
+ // default is enabled
+ pTap->enabled = 1;
+
+ // deal with options
+#define NTREQ_IRLEN 1
+#define NTREQ_IRCAPTURE 2
+#define NTREQ_IRMASK 4
+
+ // clear them as we find them
+ reqbits = (NTREQ_IRLEN | NTREQ_IRCAPTURE | NTREQ_IRMASK);
+
+ while( goi->argc ){
+ e = Jim_GetOpt_Nvp( goi, opts, &n );
+ if( e != JIM_OK ){
+ Jim_GetOpt_NvpUnknown( goi, opts, 0 );
+ return e;
+ }
+ LOG_DEBUG("Processing option: %s", n->name );
+ switch( n->value ){
+ case NTAP_OPT_ENABLED:
+ pTap->enabled = 1;
+ break;
+ case NTAP_OPT_DISABLED:
+ pTap->enabled = 0;
+ break;
+ case NTAP_OPT_EXPECTED_ID:
+ e = Jim_GetOpt_Wide( goi, &w );
+ pTap->expected_id = w;
+ break;
+ case NTAP_OPT_IRLEN:
+ case NTAP_OPT_IRMASK:
+ case NTAP_OPT_IRCAPTURE:
+ e = Jim_GetOpt_Wide( goi, &w );
+ if( e != JIM_OK ){
+ Jim_SetResult_sprintf( goi->interp, "option: %s bad parameter", n->name );
+ return e;
+ }
+ if( (w < 0) || (w > 0xffff) ){
+ // wacky value
+ Jim_SetResult_sprintf( goi->interp, "option: %s - wacky value: %d (0x%x)",
+ n->name, (int)(w), (int)(w));
+ return JIM_ERR;
+ }
+ switch(n->value){
+ case NTAP_OPT_IRLEN:
+ pTap->ir_length = w;
+ reqbits &= (~(NTREQ_IRLEN));
+ break;
+ case NTAP_OPT_IRMASK:
+ pTap->ir_capture_mask = w;
+ reqbits &= (~(NTREQ_IRMASK));
+ break;
+ case NTAP_OPT_IRCAPTURE:
+ pTap->ir_capture_value = w;
+ reqbits &= (~(NTREQ_IRCAPTURE));
+ break;
+ }
+ } // switch(n->value)
+ } // while( goi->argc )
+
+ // Did we get all the options?
+ if( reqbits ){
+ // no
+ Jim_SetResult_sprintf( goi->interp,
+ "newtap: %s missing required parameters",
+ pTap->dotted_name);
+ // fixme: Tell user what is missing :-(
+ // no memory leaks pelase
+ free(((void *)(pTap->chip)));
+ free(((void *)(pTap->tapname)));
+ free(((void *)(pTap->dotted_name)));
+ free(((void *)(pTap)));
+ return JIM_ERR;
+ }
+
+ pTap->expected = malloc( pTap->ir_length );
+ pTap->expected_mask = malloc( pTap->ir_length );
+ pTap->cur_instr = malloc( pTap->ir_length );
+
+ buf_set_u32( pTap->expected,
+ 0,
+ pTap->ir_length,
+ pTap->ir_capture_value );
+ buf_set_u32( pTap->expected_mask,
+ 0,
+ pTap->ir_length,
+ pTap->ir_capture_mask );
+ buf_set_ones( pTap->cur_instr,
+ pTap->ir_length );
+
+ pTap->bypass = 1;
+
+
+ jtag_register_event_callback(jtag_reset_callback, pTap );
+
+ ppTap = &(jtag_all_taps);
+ while( (*ppTap) != NULL ){
+ ppTap = &((*ppTap)->next_tap);
+ }
+ *ppTap = pTap;
+ {
+ static int n_taps = 0;
+ pTap->abs_chain_position = n_taps++;
+ }
+ LOG_DEBUG( "Created Tap: %s @ abs position %d, irlen %d, capture: 0x%x mask: 0x%x",
+ (*ppTap)->dotted_name,
+ (*ppTap)->abs_chain_position,
+ (*ppTap)->ir_length,
+ (*ppTap)->ir_capture_value,
+ (*ppTap)->ir_capture_mask );
+
+
+ return ERROR_OK;
+}
+
+
static int
jim_jtag_command( Jim_Interp *interp, int argc, Jim_Obj *const *argv )
{
enum {
JTAG_CMD_INTERFACE,
JTAG_CMD_INIT_RESET,
+ JTAG_CMD_NEWTAP,
+ JTAG_CMD_TAPENABLE,
+ JTAG_CMD_TAPDISABLE,
+ JTAG_CMD_TAPISENABLED
};
const Jim_Nvp jtag_cmds[] = {
{ .name = "interface" , .value = JTAG_CMD_INTERFACE },
{ .name = "arp_init-reset", .value = JTAG_CMD_INIT_RESET },
+ { .name = "newtap" , .value = JTAG_CMD_NEWTAP },
+ { .name = "tapisenabled" , .value = JTAG_CMD_TAPISENABLED },
+ { .name = "tapenable" , .value = JTAG_CMD_TAPENABLE },
+ { .name = "tapdisable" , .value = JTAG_CMD_TAPDISABLE },
{ .name = NULL, .value = -1 },
};
return JIM_ERR;
}
return JIM_OK;
+ case JTAG_CMD_NEWTAP:
+ return jim_newtap_cmd( &goi );
+ break;
+ case JTAG_CMD_TAPISENABLED:
+ case JTAG_CMD_TAPENABLE:
+ case JTAG_CMD_TAPDISABLE:
+ if( goi.argc != 1 ){
+ Jim_SetResultString( goi.interp, "Too many parameters",-1 );
+ return JIM_ERR;
+ }
+
+ {
+ jtag_tap_t *t;
+ t = jtag_TapByJimObj( goi.interp, goi.argv[0] );
+ if( t == NULL ){
+ return JIM_ERR;
+ }
+ switch( n->value ){
+ case JTAG_CMD_TAPISENABLED:
+ // below
+ break;
+ case JTAG_CMD_TAPENABLE:
+ e = 1;
+ t->enabled = e;
+ break;
+ case JTAG_CMD_TAPDISABLE:
+ e = 0;
+ t->enabled = e;
+ break;
+ }
+ Jim_SetResult( goi.interp, Jim_NewIntObj( goi.interp, e ) );
+ return JIM_OK;
+ }
}
static int jtag_init_inner(struct command_context_s *cmd_ctx)
{
- jtag_device_t *device;
+ jtag_tap_t *tap;
int retval;
LOG_DEBUG("Init JTAG chain");
- device = jtag_devices;
- jtag_ir_scan_size = 0;
- jtag_num_devices = 0;
- while (device != NULL)
- {
- jtag_ir_scan_size += device->ir_length;
- jtag_num_devices++;
- device = device->next;
+
+ tap = jtag_NextEnabledTap(NULL);
+ if( tap == NULL ){
+ LOG_ERROR("There are no enabled taps?");
+ return ERROR_JTAG_INIT_FAILED;
}
jtag_add_tlr();
int handle_jtag_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
- jtag_device_t **last_device_p = &jtag_devices;
-
- if (*last_device_p)
- {
- while ((*last_device_p)->next)
- last_device_p = &((*last_device_p)->next);
- last_device_p = &((*last_device_p)->next);
- }
-
- if (argc < 3)
+ int e;
+ char buf[1024];
+ Jim_Obj *newargs[ 10 ];
+ //
+ // CONVERT SYNTAX
+ //
+ // argv[-1] = command
+ // argv[ 0] = ir length
+ // argv[ 1] = ir capture
+ // argv[ 2] = ir mask
+ // argv[ 3] = not actually used by anything but in the docs
+
+ if( argc < 4 ){
+ command_print( cmd_ctx, "OLD DEPRECATED SYNTAX: Please use the NEW syntax");
return ERROR_OK;
-
- *last_device_p = malloc(sizeof(jtag_device_t));
- (*last_device_p)->ir_length = strtoul(args[0], NULL, 0);
-
- (*last_device_p)->expected = malloc((*last_device_p)->ir_length);
- buf_set_u32((*last_device_p)->expected, 0, (*last_device_p)->ir_length, strtoul(args[1], NULL, 0));
- (*last_device_p)->expected_mask = malloc((*last_device_p)->ir_length);
- buf_set_u32((*last_device_p)->expected_mask, 0, (*last_device_p)->ir_length, strtoul(args[2], NULL, 0));
-
- (*last_device_p)->cur_instr = malloc((*last_device_p)->ir_length);
- (*last_device_p)->bypass = 1;
- buf_set_ones((*last_device_p)->cur_instr, (*last_device_p)->ir_length);
-
- (*last_device_p)->next = NULL;
-
- jtag_register_event_callback(jtag_reset_callback, (*last_device_p));
-
- jtag_num_devices++;
-
- return ERROR_OK;
+ }
+ command_print( cmd_ctx, "OLD SYNTAX: DEPRECATED - translating to new syntax");
+ command_print( cmd_ctx, "jtag newtap CHIP TAP -irlen %s -ircapture %s -irvalue %s",
+ args[0],
+ args[1],
+ args[2] );
+ command_print( cmd_ctx, "Example: STM32 has 2 taps, the cortexM3(len4) + boundryscan(len5)");
+ command_print( cmd_ctx, "jtag newtap stm32 cortexm3 ....., thus creating the tap: \"stm32.cortexm3\"");
+ command_print( cmd_ctx, "jtag newtap stm32 boundry ....., and the tap: \"stm32.boundery\"");
+ command_print( cmd_ctx, "And then refer to the taps by the dotted name.");
+
+
+
+ newargs[0] = Jim_NewStringObj( interp, "jtag", -1 );
+ newargs[1] = Jim_NewStringObj( interp, "newtap", -1 );
+ sprintf( buf, "chip%d", jtag_NumTotalTaps() );
+ newargs[2] = Jim_NewStringObj( interp, buf, -1 );
+ sprintf( buf, "tap%d", jtag_NumTotalTaps() );
+ newargs[3] = Jim_NewStringObj( interp, buf, -1 );
+ newargs[4] = Jim_NewStringObj( interp, "-irlen", -1 );
+ newargs[5] = Jim_NewStringObj( interp, args[0], -1 );
+ newargs[6] = Jim_NewStringObj( interp, "-ircapture", -1 );
+ newargs[7] = Jim_NewStringObj( interp, args[1], -1 );
+ newargs[8] = Jim_NewStringObj( interp, "-irmask", -1 );
+ newargs[9] = Jim_NewStringObj( interp, args[2], -1 );
+
+ command_print( cmd_ctx, "NEW COMMAND:");
+ sprintf( buf, "%s %s %s %s %s %s %s %s %s %s",
+ Jim_GetString( newargs[0], NULL ),
+ Jim_GetString( newargs[1], NULL ),
+ Jim_GetString( newargs[2], NULL ),
+ Jim_GetString( newargs[3], NULL ),
+ Jim_GetString( newargs[4], NULL ),
+ Jim_GetString( newargs[5], NULL ),
+ Jim_GetString( newargs[6], NULL ),
+ Jim_GetString( newargs[7], NULL ),
+ Jim_GetString( newargs[8], NULL ),
+ Jim_GetString( newargs[9], NULL ) );
+
+
+
+ e = jim_jtag_command( interp, 10, newargs );
+ if( e != JIM_OK ){
+ command_print( cmd_ctx, "%s", Jim_GetString( Jim_GetResult(interp), NULL ) );
+ }
+ return e;
}
+
int handle_scan_chain_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
- jtag_device_t *device = jtag_devices;
- int device_count = 0;
+ jtag_tap_t *tap;
- while (device)
- {
+ tap = jtag_all_taps;
+ command_print(cmd_ctx, " TapName | Enabled | IdCode Expected IrLen IrCap IrMask Instr ");
+ command_print(cmd_ctx, "---|--------------------|---------|------------|------------|------|------|------|---------");
+
+ while( tap ){
u32 expected, expected_mask, cur_instr;
- expected = buf_get_u32(device->expected, 0, device->ir_length);
- expected_mask = buf_get_u32(device->expected_mask, 0, device->ir_length);
- cur_instr = buf_get_u32(device->cur_instr, 0, device->ir_length);
- command_print(cmd_ctx, "%i: idcode: 0x%8.8x ir length %i, ir capture 0x%x, ir mask 0x%x, current instruction 0x%x", device_count, device->idcode, device->ir_length, expected, expected_mask, cur_instr);
- device = device->next;
- device_count++;
+ expected = buf_get_u32(tap->expected, 0, tap->ir_length);
+ expected_mask = buf_get_u32(tap->expected_mask, 0, tap->ir_length);
+ cur_instr = buf_get_u32(tap->cur_instr, 0, tap->ir_length);
+ command_print(cmd_ctx,
+ "%2d | %-18s | %c | 0x%08x | 0x%08x | 0x%02x | 0x%02x | 0x%02x | 0x%02x",
+ tap->abs_chain_position,
+ tap->dotted_name,
+ tap->enabled ? 'Y' : 'n',
+ tap->idcode,
+ tap->expected_id,
+ tap->ir_length,
+ expected,
+ expected_mask,
+ cur_instr);
+ tap = tap->next_tap;
}
return ERROR_OK;
jtag_reset_config = RESET_TRST_AND_SRST;
else
{
- LOG_ERROR("invalid reset_config argument, defaulting to none");
+ LOG_ERROR("(1) invalid reset_config argument (%s), defaulting to none", args[0]);
jtag_reset_config = RESET_NONE;
return ERROR_INVALID_ARGUMENTS;
}
jtag_reset_config |= RESET_SRST_PULLS_TRST | RESET_TRST_PULLS_SRST;
else
{
- LOG_ERROR("invalid reset_config argument, defaulting to none");
+ LOG_ERROR("(2) invalid reset_config argument (%s), defaulting to none", args[1]);
jtag_reset_config = RESET_NONE;
return ERROR_INVALID_ARGUMENTS;
}
jtag_reset_config &= ~RESET_TRST_OPEN_DRAIN;
else
{
- LOG_ERROR("invalid reset_config argument, defaulting to none");
+ LOG_ERROR("(3) invalid reset_config argument (%s) defaulting to none", args[2] );
jtag_reset_config = RESET_NONE;
return ERROR_INVALID_ARGUMENTS;
}
jtag_reset_config &= ~RESET_SRST_PUSH_PULL;
else
{
- LOG_ERROR("invalid reset_config argument, defaulting to none");
+ LOG_ERROR("(4) invalid reset_config argument (%s), defaulting to none", args[3]);
jtag_reset_config = RESET_NONE;
return ERROR_INVALID_ARGUMENTS;
}
{
int i;
scan_field_t *fields;
+ jtag_tap_t *tap;
if ((argc < 2) || (argc % 2))
{
for (i = 0; i < argc / 2; i++)
{
- int device = strtoul(args[i*2], NULL, 0);
- jtag_device_t *device_ptr=jtag_get_device(device);
- if (device_ptr==NULL)
+ tap = jtag_TapByString( args[i*2] );
+ if (tap==NULL)
{
+ command_print( cmd_ctx, "Tap: %s unknown", args[i*2] );
return ERROR_FAIL;
}
- int field_size = device_ptr->ir_length;
- fields[i].device = device;
+ int field_size = tap->ir_length;
+ fields[i].tap = tap;
fields[i].out_value = malloc(CEIL(field_size, 8));
buf_set_u32(fields[i].out_value, 0, field_size, strtoul(args[i*2+1], NULL, 0));
fields[i].out_mask = NULL;
int num_fields;
int field_count = 0;
int i, e;
- long device;
+ jtag_tap_t *tap;
/* args[1] = device
* args[2] = num_bits
return e;
}
- e = Jim_GetLong(interp, args[1], &device);
- if (e != JIM_OK)
- return e;
+ tap = jtag_TapByJimObj( interp, args[1] );
+ if( tap == NULL ){
+ return JIM_ERR;
+ }
num_fields=(argc-2)/2;
fields = malloc(sizeof(scan_field_t) * num_fields);
Jim_GetLong(interp, args[i], &bits);
str = Jim_GetString(args[i+1], &len);
- fields[field_count].device = device;
+
+ fields[field_count].tap = tap;
fields[field_count].num_bits = bits;
fields[field_count].out_value = malloc(CEIL(bits, 8));
str_to_buf(str, len, fields[field_count].out_value, bits, 0);
retval = jtag_execute_queue();
if (retval != ERROR_OK)
{
- Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
- Jim_AppendStrings(interp, Jim_GetResult(interp), "drscan: jtag execute failed", NULL);
+ Jim_SetResultString(interp, "drscan: jtag execute failed",-1);
return JIM_ERR;
}
{
return jtag->srst_asserted(srst_asserted);
}
+
typedef struct scan_field_s
{
- int device; /* ordinal device number this instruction refers to */
+ jtag_tap_t *tap; /* tap pointer this instruction refers to */
int num_bits; /* number of bits this field specifies (up to 32) */
u8 *out_value; /* value to be scanned into the device */
u8 *out_mask; /* only masked bits care */
extern jtag_command_t *jtag_command_queue;
-typedef struct jtag_device_s
+// this is really: typedef jtag_tap_t
+// But - the typedef is done in "types.h"
+// due to "forward decloration reasons"
+struct jtag_tap_s
{
+ const char *chip;
+ const char *tapname;
+ const char *dotted_name;
+ int abs_chain_position;
+ int enabled;
int ir_length; /* size of instruction register */
+ u32 ir_capture_value;
u8 *expected; /* Capture-IR expected value */
+ u32 ir_capture_mask;
u8 *expected_mask; /* Capture-IR expected mask */
u32 idcode; /* device identification code */
+ u32 expected_id;
u8 *cur_instr; /* current instruction */
int bypass; /* bypass register selected */
- struct jtag_device_s *next;
-} jtag_device_t;
+ jtag_tap_t *next_tap;
+};
+extern jtag_tap_t *jtag_AllTaps(void);
+extern jtag_tap_t *jtag_TapByPosition(int n);
+extern jtag_tap_t *jtag_NextEnabledTap( jtag_tap_t * );
+extern jtag_tap_t *jtag_TapByPosition( int n );
+extern jtag_tap_t *jtag_TapByString( const char *dotted_name );
+extern jtag_tap_t *jtag_TapByJimObj( Jim_Interp *interp, Jim_Obj *obj );
+extern jtag_tap_t *jtag_TapByAbsPosition( int abs_position );
+extern int jtag_NumEnabledTaps(void);
+extern int jtag_NumTotalTaps(void);
+
+
-extern jtag_device_t *jtag_devices;
-extern int jtag_num_devices;
-extern int jtag_ir_scan_size;
enum reset_line_mode
{
extern int jtag_scan_size(scan_command_t *cmd);
extern int jtag_read_buffer(u8 *buffer, scan_command_t *cmd);
extern int jtag_build_buffer(scan_command_t *cmd, u8 **buffer);
-extern jtag_device_t* jtag_get_device(int num);
+
extern void jtag_sleep(u32 us);
extern int jtag_call_event_callbacks(enum jtag_event event);
extern int jtag_register_event_callback(int (*callback)(enum jtag_event event, void *priv), void *priv);
*
* Note that this jtag_add_dr_out can be defined as an inline function.
*/
-extern void interface_jtag_add_dr_out(int device,
+extern void interface_jtag_add_dr_out(jtag_tap_t *tap,
int num_fields,
const int *num_bits,
const u32 *value,
-static __inline__ void jtag_add_dr_out(int device,
+static __inline__ void jtag_add_dr_out(jtag_tap_t *tap,
int num_fields,
const int *num_bits,
const u32 *value,
if (end_state != -1)
cmd_queue_end_state=end_state;
cmd_queue_cur_state=cmd_queue_end_state;
- interface_jtag_add_dr_out(device, num_fields, num_bits, value, cmd_queue_end_state);
+ interface_jtag_add_dr_out(tap, num_fields, num_bits, value, cmd_queue_end_state);
}
.load = virtex2_load,
};
-int virtex2_set_instr(int chain_pos, u32 new_instr)
+int virtex2_set_instr(jtag_tap_t *tap, u32 new_instr)
{
- jtag_device_t *device = jtag_get_device(chain_pos);
- if (device==NULL)
+ if (tap==NULL)
return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
- field.device = chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
values = malloc(num_words * 4);
- scan_field.device = virtex2_info->chain_pos;
+ scan_field.tap = virtex2_info->tap;
scan_field.num_bits = num_words * 32;
scan_field.out_value = values;
scan_field.out_mask = NULL;
for (i = 0; i < num_words; i++)
buf_set_u32(values + 4 * i, 0, 32, flip_u32(*words++, 32));
- virtex2_set_instr(virtex2_info->chain_pos, 0x5); /* CFG_IN */
+ virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */
jtag_add_dr_scan(1, &scan_field, TAP_PD);
virtex2_pld_device_t *virtex2_info = pld_device->driver_priv;
scan_field_t scan_field;
- scan_field.device = virtex2_info->chain_pos;
+ scan_field.tap = virtex2_info->tap;
scan_field.num_bits = 32;
scan_field.out_value = NULL;
scan_field.out_mask = NULL;
scan_field.in_check_mask = NULL;
scan_field.in_handler = virtex2_jtag_buf_to_u32;
- virtex2_set_instr(virtex2_info->chain_pos, 0x4); /* CFG_OUT */
+ virtex2_set_instr(virtex2_info->tap, 0x4); /* CFG_OUT */
while (num_words--)
{
scan_field_t field;
- field.device = virtex2_info->chain_pos;
+ field.tap = virtex2_info->tap;
field.out_mask = NULL;
field.in_value = NULL;
field.in_check_value = NULL;
return retval;
jtag_add_end_state(TAP_RTI);
- virtex2_set_instr(virtex2_info->chain_pos, 0xb); /* JPROG_B */
+ virtex2_set_instr(virtex2_info->tap, 0xb); /* JPROG_B */
jtag_execute_queue();
jtag_add_sleep(1000);
- virtex2_set_instr(virtex2_info->chain_pos, 0x5); /* CFG_IN */
+ virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */
jtag_execute_queue();
for (i = 0; i < bit_file.length; i++)
jtag_add_tlr();
jtag_add_end_state(TAP_RTI);
- virtex2_set_instr(virtex2_info->chain_pos, 0xc); /* JSTART */
+ virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
jtag_add_runtest(13, TAP_RTI);
- virtex2_set_instr(virtex2_info->chain_pos, 0x3f); /* BYPASS */
- virtex2_set_instr(virtex2_info->chain_pos, 0x3f); /* BYPASS */
- virtex2_set_instr(virtex2_info->chain_pos, 0xc); /* JSTART */
+ virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
+ virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
+ virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
jtag_add_runtest(13, TAP_RTI);
- virtex2_set_instr(virtex2_info->chain_pos, 0x3f); /* BYPASS */
+ virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
jtag_execute_queue();
return ERROR_OK;
int virtex2_pld_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct pld_device_s *pld_device)
{
+ jtag_tap_t *tap;
+
virtex2_pld_device_t *virtex2_info;
if (argc < 2)
return ERROR_PLD_DEVICE_INVALID;
}
+ tap = jtag_TapByString( args[1] );
+ if( tap == NULL ){
+ command_print( cmd_ctx, "Tap: %s does not exist", args[1] );
+ return ERROR_OK;
+ }
+
virtex2_info = malloc(sizeof(virtex2_pld_device_t));
pld_device->driver_priv = virtex2_info;
-
- virtex2_info->chain_pos = strtoul(args[1], NULL, 0);
+ virtex2_info->tap = tap;
return ERROR_OK;
}
#ifndef VIRTEX2_H
#define VIRTEX2_H
+#include "types.h"
#include "pld.h"
#include "xilinx_bit.h"
typedef struct virtex2_pld_device_s
{
- int chain_pos;
+ jtag_tap_t *tap;
} virtex2_pld_device_t;
#endif /* VIRTEX2_H */
arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_swjdp.h \
etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
-nobase_dist_pkglib_DATA = xscale/debug_handler.bin target/at91eb40a.cfg \
- target/at91r40008.cfg target/lpc2148.cfg target/lpc2148_rclk.cfg target/lpc2148_2mhz.cfg target/lpc2294.cfg \
- target/sam7x256.cfg target/str710.cfg target/str912.cfg target/nslu2.cfg target/pxa255_sst.cfg \
- target/pxa255.cfg target/zy1000.cfg target/at91sam9260.cfg \
- target/wi-9c.cfg target/stm32.cfg target/xba_revA3.cfg \
- ecos/at91eb40a.elf target/lm3s6965.cfg interface/parport.cfg \
- interface/jtagkey-tiny.cfg interface/jtagkey.cfg interface/str9-comstick.cfg \
- target/epc9301.cfg target/ipx42x.cfg target/lpc2129.cfg target/netx500.cfg \
- target/omap5912.cfg target/pxa270.cfg target/str750.cfg target/str9comstick.cfg \
- target/str730.cfg target/stm32stick.cfg \
- target/lm3s811.cfg interface/luminary.cfg interface/luminary-libftdi.cfg interface/luminary-lm3s811.cfg \
- target/imx31.cfg target/lm3s3748.cfg \
- interface/stm32-stick.cfg interface/calao-usb-a9260-c01.cfg interface/calao-usb-a9260-c02.cfg \
- interface/calao-usb-a9260.cfg target/at91sam9260minimal.cfg \
- interface/chameleon.cfg interface/at91rm9200.cfg interface/jlink.cfg interface/arm-usb-ocd.cfg \
- interface/signalyzer.cfg target/eir-sam7se512.cfg \
- interface/flyswatter.cfg target/hammer.cfg \
- interface/olimex-jtag-tiny-a.cfg \
- target/pic32mx.cfg target/aduc702x.cfg interface/dummy.cfg interface/olimex-arm-usb-ocd.cfg target/s3c2440.cfg \
- interface/openocd-usb.cfg target/test_syntax_error.cfg target/test_reset_syntax_error.cfg \
- target/imx27.cfg
-
-
-
+nobase_dist_pkglib_DATA =
+nobase_dist_pkglib_DATA += xscale/debug_handler.bin
+nobase_dist_pkglib_DATA += ecos/at91eb40a.elf
+# Various chip targets
+nobase_dist_pkglib_DATA += $(wildcard $(srcdir)/target/*.cfg)
+# Various jtag interfaces
+nobase_dist_pkglib_DATA += $(wildcard $(srcdir)/interface/*.cfg)
+# Various preconfigured boards
+nobase_dist_pkglib_DATA += $(wildcard $(srcdir)/board/*.cfg)
arm11->target = target;
/* prepare JTAG information for the new target */
- arm11->jtag_info.chain_pos = target->chain_position;
+ arm11->jtag_info.tap = target->tap;
arm11->jtag_info.scann_size = 5;
if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
return retval;
}
- jtag_device_t *device = jtag_get_device(target->chain_position);
- if (device==NULL)
+ if (target->tap==NULL)
return ERROR_FAIL;
- if (device->ir_length != 5)
+ if (target->tap->ir_length != 5)
{
- LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
+ LOG_ERROR("'target arm11' expects IR LENGTH = 5");
return ERROR_COMMAND_SYNTAX_ERROR;
}
arm11_common_t * arm11_find_target(const char * arg)
{
- size_t jtag_target = strtoul(arg, NULL, 0);
-
- {target_t * t;
- for (t = all_targets; t; t = t->next)
- {
- if (strcmp(t->type->name,"arm11"))
- continue;
-
- arm11_common_t * arm11 = t->arch_info;
-
- if (arm11->jtag_info.chain_pos != jtag_target)
- continue;
-
- return arm11;
- }}
-
+ jtag_tap_t *tap;
+ target_t * t;
+
+ tap = jtag_TapByString( arg );
+ if( !tap ){
+ return NULL;
+ }
+
+ for (t = all_targets; t; t = t->next){
+ if( t->tap == tap ){
+ if( 0 == strcmp(t->type->name,"arm11")){
+ arm11_common_t * arm11 = t->arch_info;
+ return arm11;
+ }
+ }
+ }
return 0;
}
*/
void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
{
- field->device = arm11->jtag_info.chain_pos;
+ field->tap = arm11->jtag_info.tap;
field->num_bits = num_bits;
field->out_mask = NULL;
field->in_check_mask = NULL;
*/
void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state)
{
- jtag_device_t *device = jtag_get_device(arm11->jtag_info.chain_pos);
- if (device==NULL)
- {
+ jtag_tap_t *tap;
+ tap = arm11->jtag_info.tap;
+ if( tap == NULL ){
/* FIX!!!! error is logged, but not propagated back up the call stack... */
+ LOG_ERROR( "tap is null here! This is bad!");
+ return;
}
- if (buf_get_u32(device->cur_instr, 0, 5) == instr)
- {
- JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
- return;
+ if (buf_get_u32(tap->cur_instr, 0, 5) == instr){
+ JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
+ return;
}
JTAG_DEBUG("IR <= 0x%02x", instr);
return retval;
}
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &instruction_buf;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = out_buf;
fields[1].out_mask = NULL;
return ERROR_OK;
}
-int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chain_pos, const char *variant)
+int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap, const char *variant)
{
arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
- arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);
+ arm7tdmi_init_arch_info(target, arm7tdmi, tap, variant);
arm7tdmi->arch_info = arm720t;
arm720t->common_magic = ARM720T_COMMON_MAGIC;
{
arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
- arm720t_init_arch_info(target, arm720t, target->chain_position, target->variant);
+ arm720t_init_arch_info(target, arm720t, target->tap, target->variant);
return ERROR_OK;
}
embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
u8 reg_addr = ice_reg->addr & 0x1f;
- int chain_pos = ice_reg->jtag_info->chain_pos;
+ jtag_tap_t *tap;
+ tap = ice_reg->jtag_info->tap;
- embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2);
+ embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
buffer += (count-2)*4;
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
jtag_add_end_state(TAP_PD);
- fields[0].device = arm7_9->jtag_info.chain_pos;
+ fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = arm7_9->jtag_info.chain_pos;
+ fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
{
u32 values[2]={breakpoint, flip_u32(out, 32)};
- jtag_add_dr_out(jtag_info->chain_pos,
+ jtag_add_dr_out(jtag_info->tap,
2,
arm7tdmi_num_bits,
values,
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
return ERROR_OK;
}
-int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, const char *variant)
+int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant)
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
armv4_5 = &arm7_9->armv4_5_common;
/* prepare JTAG information for the new target */
- arm7_9->jtag_info.chain_pos = chain_pos;
+ arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 4;
/* register arch-specific functions */
arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
- arm7tdmi_init_arch_info(target, arm7tdmi, target->chain_position, target->variant);
+ arm7tdmi_init_arch_info(target, arm7tdmi, target->tap, target->variant);
return ERROR_OK;
}
} arm7tdmi_common_t;
int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);
-int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, const char *variant);
+int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant);
int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm7tdmi_examine(struct target_s *target);
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = ®_addr_buf;
fields[2].out_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- fields[3].device = jtag_info->chain_pos;
+ fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].out_mask = NULL;
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = value_buf;
fields[1].out_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = ®_addr_buf;
fields[2].out_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- fields[3].device = jtag_info->chain_pos;
+ fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].out_mask = NULL;
buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = cp15_opcode_buf;
fields[1].out_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = ®_addr_buf;
fields[2].out_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- fields[3].device = jtag_info->chain_pos;
+ fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].out_mask = NULL;
return ERROR_OK;
}
-int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, const char *variant)
+int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap, const char *variant)
{
arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
- arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
+ arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi->arch_info = arm920t;
arm920t->common_magic = ARM920T_COMMON_MAGIC;
{
arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
- arm920t_init_arch_info(target, arm920t, target->chain_position, target->variant);
+ arm920t_init_arch_info(target, arm920t, target->tap, target->variant);
return ERROR_OK;
}
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 1;
fields[1].out_value = &access;
fields[1].out_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 14;
fields[2].out_value = address_buf;
fields[2].out_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- fields[3].device = jtag_info->chain_pos;
+ fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].out_mask = NULL;
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = value_buf;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 1;
fields[1].out_value = &access;
fields[1].out_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 14;
fields[2].out_value = address_buf;
fields[2].out_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- fields[3].device = jtag_info->chain_pos;
+ fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].out_mask = NULL;
return ERROR_OK;
}
-int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, const char *variant)
+int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant)
{
arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
- arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
+ arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi->arch_info = arm926ejs;
arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
{
arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
- arm926ejs_init_arch_info(target, arm926ejs, target->chain_position, target->variant);
+ arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
return ERROR_OK;
}
u32 d_far;
} arm926ejs_common_t;
-extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, const char *variant);
+extern int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap, const char *variant);
extern int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
extern int arm926ejs_arch_state(struct target_s *target);
extern int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
return ERROR_OK;
}
-int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, int chain_pos, const char *variant)
+int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap_t *tap, const char *variant)
{
arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
- arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
+ arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi->arch_info = arm966e;
arm966e->common_magic = ARM966E_COMMON_MAGIC;
{
arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));
- arm966e_init_arch_info(target, arm966e, target->chain_position, target->variant);
+ arm966e_init_arch_info(target, arm966e, target->tap, target->variant);
return ERROR_OK;
}
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 6;
fields[1].out_value = ®_addr_buf;
fields[1].out_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = &nr_w_buf;
fields[2].out_mask = NULL;
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = value_buf;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 6;
fields[1].out_value = ®_addr_buf;
fields[1].out_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = &nr_w_buf;
fields[2].out_mask = NULL;
jtag_add_end_state(TAP_PD);
- fields[0].device = arm7_9->jtag_info.chain_pos;
+ fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = arm7_9->jtag_info.chain_pos;
+ fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = arm7_9->jtag_info.chain_pos;
+ fields[2].tap = arm7_9->jtag_info.tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].out_mask = NULL;
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
fields[0].out_mask = NULL;
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf;
fields[1].out_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = instr_buf;
fields[2].out_mask = NULL;
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].out_mask = NULL;
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].out_mask = NULL;
return ERROR_OK;
}
-int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, const char *variant)
+int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap, const char *variant)
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
armv4_5 = &arm7_9->armv4_5_common;
/* prepare JTAG information for the new target */
- arm7_9->jtag_info.chain_pos = chain_pos;
+ arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 5;
/* register arch-specific functions */
{
arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
- arm9tdmi_init_arch_info(target, arm9tdmi, target->chain_position, target->variant);
+ arm9tdmi_init_arch_info(target, arm9tdmi, target->tap, target->variant);
return ERROR_OK;
}
extern int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm9tdmi_examine(struct target_s *target);
-extern int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, const char *variant);
+extern int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap, const char *variant);
extern int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
extern int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed);
int arm_jtag_set_instr(arm_jtag_t *jtag_info, u32 new_instr, in_handler_t handler)
{
- jtag_device_t *device = jtag_get_device(jtag_info->chain_pos);
- if (device==NULL)
+ jtag_tap_t *tap;
+ tap = jtag_info->tap;
+ if (tap==NULL)
return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
u8 t[4];
- field.device = jtag_info->chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = t;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
return retval;
}
- jtag_add_dr_out(jtag_info->chain_pos,
+ jtag_add_dr_out(jtag_info->tap,
1,
num_bits,
values,
typedef struct arm_jtag_s
{
- int chain_pos;
+ jtag_tap_t *tap;
int scann_size;
u32 scann_instr;
--- /dev/null
+# This board is from ARM and has an samsung s3c45101x01 chip
+
+source [find target/samsung_s3c4510.cfg]
+
+#
+# FIXME:
+# Add (A) sdram configuration
+# Add (B) flash cfi programing configuration
+#
+
--- /dev/null
+#
+# This is for the "at91rm9200-DK" (not the EK) eval board.
+#
+# The two are probably very simular.... I have DK...
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash_bank cfi 0x10000000 0x00200000 2 2 0
+
+
+proc at91rm9200_dk_init { } {
+ # Try to run at 1khz... Yea, that slow!
+ # Chip is really running @ 32khz
+ jtag_khz 8
+
+ mww 0xfffffc64 0xffffffff
+ ## disable all clocks but system clock
+ mww 0xfffffc04 0xfffffffe
+ ## disable all clocks to pioa and piob
+ mww 0xfffffc14 0xffffffc3
+ ## master clock = slow cpu = slow
+ ## (means the CPU is running at 32khz!)
+ mww 0xfffffc30 0
+ ## main osc enable
+ mww 0xfffffc20 0x0000ff01
+ ## program pllA
+ mww 0xfffffc28 0x20263e04
+ ## program pllB
+ mww 0xfffffc2c 0x10483e0e
+ ## let pll settle... sleep 100msec
+ sleep 100
+ ## switch to fast clock
+ mww 0xfffffc30 0x202
+ ## Sleep some - (go read)
+ sleep 100
+
+ #========================================
+ # CPU now runs at 180mhz
+ # SYS runs at 60mhz.
+ jtag_khz 40000
+ #========================================
+
+
+ ## set memc for all memories
+ mww 0xffffff60 0x02
+ ## program smc controller
+ mww 0xffffff70 0x3284
+ ## init sdram
+ mww 0xffffff98 0x7fffffd0
+ ## all banks precharge
+ mww 0xffffff80 0x02
+ ## touch sdram chip to make it work
+ mww 0x20000000 0
+ ## sdram controller mode register
+ mww 0xffffff90 0x04
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ ## sdram controller mode register
+ ## Refresh, etc....
+ mww 0xffffff90 0x03
+ mww 0x20000080 0
+ mww 0xffffff94 0x1f4
+ mww 0x20000080 0
+ mww 0xffffff90 0x10
+ mww 0x20000000 0
+ mww 0xffffff00 0x01
+
+}
--- /dev/null
+# Elector Internet Radio board
+# http://www.ethernut.de/en/hardware/eir/index.html
+
+source [find target/sam7se512.cfg]
+
+$_TARGETNAME configure -event reset-init {
+ # WDT_MR, disable watchdog
+ mww 0xFFFFFD44 0x00008000
+
+ # RSTC_MR, enable user reset
+ mww 0xfffffd08 0xa5000001
+
+ # CKGR_MOR
+ mww 0xFFFFFC20 0x00000601
+ sleep 10
+
+ # CKGR_PLLR
+ mww 0xFFFFFC2C 0x00481c0e
+ sleep 10
+
+ # PMC_MCKR
+ mww 0xFFFFFC30 0x00000007
+ sleep 10
+
+ # PMC_IER
+ mww 0xFFFFFF60 0x00480100
+
+ #
+ # Enable SDRAM interface.
+ #
+
+ # Enable SDRAM control at PIO A.
+ mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
+ mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
+
+ # Enable address bus (A0, A2-A11, A13-A17) at PIO B
+ mww 0xfffff674 0x0003effd # PIO_BSR_OFF
+ mww 0xfffff604 0x0003effd # PIO_PDR_OFF
+
+ # Enable 16 bit data bus at PIO C
+ mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
+ mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
+
+ # Enable SDRAM chip select
+ mww 0xffffff80 0x00000002 # EBI_CSA_OFF
+
+ # Set SDRAM characteristics in configuration register.
+ # Hard coded values for MT48LC32M16A2 with 48MHz CPU.
+ mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
+ sleep 10
+
+ # Issue 16 bit SDRAM command: NOP
+ mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
+ mww 0x20000000 0x00000000
+
+ # Issue 16 bit SDRAM command: Precharge all
+ mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
+ mww 0x20000000 0x00000000
+
+ # Issue 8 auto-refresh cycles
+ mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0x20000000 0x00000000
+ mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0x20000000 0x00000000
+ mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0x20000000 0x00000000
+ mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0x20000000 0x00000000
+ mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0x20000000 0x00000000
+ mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0x20000000 0x00000000
+ mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0x20000000 0x00000000
+ mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+ mww 0x20000000 0x00000000
+
+ # Issue 16 bit SDRAM command: Set mode register
+ mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
+ mww 0x20000014 0xcafedede
+
+ # Set refresh rate count ???
+ mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
+
+ # Issue 16 bit SDRAM command: Normal mode
+ mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
+ mww 0x20000000 0x00000180
+
+ #
+ # Enable external reset key.
+ #
+ mww 0xfffffd08 0xa5000001
+}
+
--- /dev/null
+# Target Configuration for the TinCanTools S3C2410 Based Hammer Module
+# http://www.tincantools.com
+
+source [target/samsung_s3c2410.cfg]
+
+$_TARGETNAME configure -event reset-init {
+ # Reset Script for the TinCanTools S3C2410 Based Hammer Module
+ # http://www.tincantools.com
+ #
+ # Setup primary clocks and initialize the SDRAM
+ mww 0x53000000 0x00000000
+ mww 0x4a000008 0xffffffff
+ mww 0x4a00000c 0x000007ff
+ mww 0x4c000000 0x00ffffff
+ mww 0x4c000014 0x00000003
+ mww 0x4c000004 0x000a1031
+ mww 0x48000000 0x11111122
+ mww 0x48000004 0x00000700
+ mww 0x48000008 0x00000700
+ mww 0x4800000c 0x00000700
+ mww 0x48000010 0x00000700
+ mww 0x48000014 0x00000700
+ mww 0x48000018 0x00000700
+ mww 0x4800001c 0x00018005
+ mww 0x48000020 0x00018005
+ mww 0x48000024 0x009c0459
+ mww 0x48000028 0x000000b2
+ mww 0x4800002c 0x00000030
+ mww 0x48000030 0x00000030
+ flash probe 0
+}
+
+
+#flash configuration
+#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
+flash bank cfi 0x00000000 0x1000000 2 2 0
--- /dev/null
+# The IAR str912-sk evaluation kick start board has an str912
+
+source [find target/str912.cfg]
\ No newline at end of file
--- /dev/null
+# The LogicPD Eval IMX27 eval board has a single IMX27 chip
+source [find target/imx27.cfg]
+
+# The Logic PD board has a NOR flash on CS0
+flash_bank cfi 0xc0000000 0x00200000 2 2 0
+
+#
+# FIX ME, Add support to
+#
+# (A) hard reset the board.
+# (B) Initialize the SDRAM on the board
+#
--- /dev/null
+# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
+
+source [find target/sam7x256.cfg]
+
--- /dev/null
+# This is an STM32 eval board with a single STM32F103ZET6 chip on it.
+
+source [find target/stm32.cfg]
--- /dev/null
+# This is an STM32 eval board with a single STM32F103ZET6 chip on it.
+
+# My test board has a "Rev1" tap id.
+set BSTAPID 0x16410041
+source [find target/stm32.cfg]
+
return ERROR_OK;
}
-int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, const char *variant)
+int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap, const char *variant)
{
armv7m_common_t *armv7m;
armv7m = &cortex_m3->armv7m;
/* prepare JTAG information for the new target */
- cortex_m3->jtag_info.chain_pos = chain_pos;
+ cortex_m3->jtag_info.tap = tap;
cortex_m3->jtag_info.scann_size = 4;
cortex_m3->swjdp_info.dp_select_value = -1;
{
cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
- cortex_m3_init_arch_info(target, cortex_m3, target->chain_position, target->variant);
+ cortex_m3_init_arch_info(target, cortex_m3, target->tap, target->variant);
return ERROR_OK;
}
int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
-extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, const char *variant);
+extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap, const char *variant);
#endif /* CORTEX_M3_H */
* *
* CoreSight (Light?) SerialWireJtagDebugPort *
* *
- * CoreSight™ DAP-Lite TRM, ARM DDI 0316A *
- * Cortex-M3™ TRM, ARM DDI 0337C *
+ * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
+ * Cortex-M3(tm) TRM, ARM DDI 0337C *
* *
***************************************************************************/
#ifdef HAVE_CONFIG_H
jtag_add_end_state(TAP_RTI);
arm_jtag_set_instr(jtag_info, instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 3;
buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
fields[0].out_value = &out_addr_buf;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = outvalue;
fields[1].out_mask = NULL;
jtag_add_end_state(TAP_RTI);
arm_jtag_set_instr(jtag_info, instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 3;
buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
fields[0].out_value = &out_addr_buf;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
buf_set_u32(out_value_buf, 0, 32, outvalue);
fields[1].out_value = out_value_buf;
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
- fields[0].device = ice_reg->jtag_info->chain_pos;
+ fields[0].tap = ice_reg->jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = ice_reg->jtag_info->chain_pos;
+ fields[1].tap = ice_reg->jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = ice_reg->jtag_info->chain_pos;
+ fields[2].tap = ice_reg->jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 0);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 0);
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
u8 reg_addr = ice_reg->addr & 0x1f;
- embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
+ embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
}
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = field0_out;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 1);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 0);
}
/* this is the inner loop of the open loop DCC write of data to target */
-void MINIDRIVER(embeddedice_write_dcc)(int chain_pos, int reg_addr, u8 *buffer, int little, int count)
+void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
{
int i;
for (i = 0; i < count; i++)
{
- embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+ embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
buffer += 4;
}
}
* embeddedice_write_reg
*/
static const int embeddedice_num_bits[]={32,5,1};
-static __inline__ void embeddedice_write_reg_inner(int chain_pos, int reg_addr, u32 value)
+static __inline__ void embeddedice_write_reg_inner( jtag_tap_t *tap, int reg_addr, u32 value)
{
u32 values[3];
values[1]=reg_addr;
values[2]=1;
- jtag_add_dr_out(chain_pos,
+ jtag_add_dr_out( tap,
3,
embeddedice_num_bits,
values,
-1);
}
-void embeddedice_write_dcc(int chain_pos, int reg_addr, u8 *buffer, int little, int count);
+void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count);
#endif /* EMBEDDED_ICE_H */
int etb_set_instr(etb_t *etb, u32 new_instr)
{
- jtag_device_t *device = jtag_get_device(etb->chain_pos);
- if (device==NULL)
+ jtag_tap_t *tap;
+ tap = etb->tap;
+ if (tap==NULL)
return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
- field.device = etb->chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
{
scan_field_t field;
- field.device = etb->chain_pos;
+ field.tap = etb->tap;
field.num_bits = 5;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
etb_scann(etb, 0x0);
etb_set_instr(etb, 0xc);
- fields[0].device = etb->chain_pos;
+ fields[0].tap = etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = etb->chain_pos;
+ fields[1].tap = etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, 4);
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = etb->chain_pos;
+ fields[2].tap = etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
- fields[0].device = etb_reg->etb->chain_pos;
+ fields[0].tap = etb_reg->etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = etb_reg->etb->chain_pos;
+ fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = etb_reg->etb->chain_pos;
+ fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
- fields[0].device = etb_reg->etb->chain_pos;
+ fields[0].tap = etb_reg->etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = malloc(4);
buf_set_u32(fields[0].out_value, 0, 32, value);
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = etb_reg->etb->chain_pos;
+ fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = etb_reg->etb->chain_pos;
+ fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 1);
int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target;
- jtag_device_t *jtag_device;
+ jtag_tap_t *tap;
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
return ERROR_FAIL;
}
- jtag_device = jtag_get_device(strtoul(args[1], NULL, 0));
-
- if (!jtag_device)
- {
+ tap = jtag_TapByString( args[1] );
+ if( tap == NULL ){
+ command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
return ERROR_FAIL;
}
+
if (arm7_9->etm_ctx)
{
etb_t *etb = malloc(sizeof(etb_t));
arm7_9->etm_ctx->capture_driver_priv = etb;
- etb->chain_pos = strtoul(args[1], NULL, 0);
+ etb->tap = tap;
etb->cur_scan_chain = -1;
etb->reg_cache = NULL;
etb->ram_width = 0;
typedef struct etb_s
{
etm_context_t *etm_ctx;
- int chain_pos;
+ jtag_tap_t *tap;
int cur_scan_chain;
reg_cache_t *reg_cache;
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
- fields[0].device = etm_reg->jtag_info->chain_pos;
+ fields[0].tap = etm_reg->jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = etm_reg->jtag_info->chain_pos;
+ fields[1].tap = etm_reg->jtag_info->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = etm_reg->jtag_info->chain_pos;
+ fields[2].tap = etm_reg->jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
- fields[0].device = etm_reg->jtag_info->chain_pos;
+ fields[0].tap = etm_reg->jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = malloc(4);
buf_set_u32(fields[0].out_value, 0, 32, value);
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = etm_reg->jtag_info->chain_pos;
+ fields[1].tap = etm_reg->jtag_info->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = etm_reg->jtag_info->chain_pos;
+ fields[2].tap = etm_reg->jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 1);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
- fields[0].device = jtag_info->chain_pos;
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
fields[0].out_mask = NULL;
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
- fields[1].device = jtag_info->chain_pos;
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf;
fields[1].out_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- fields[2].device = jtag_info->chain_pos;
+ fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = instr_buf;
fields[2].out_mask = NULL;
arm7_9_common_t *arm7_9;
arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
- arm926ejs_init_arch_info(target, arm926ejs, target->chain_position, target->variant);
+ arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
armv4_5 = target->arch_info;
arm7_9 = armv4_5->arch_info;
return cache;
}
-int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_pos, const char *variant)
+int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap, const char *variant)
{
target->arch_info = mips32;
mips32->common_magic = MIPS32_COMMON_MAGIC;
mips32->bp_scanned = 0;
mips32->data_break_list = NULL;
- mips32->ejtag_info.chain_pos = chain_pos;
+ mips32->ejtag_info.tap = tap;
mips32->read_core_reg = mips32_read_core_reg;
mips32->write_core_reg = mips32_write_core_reg;
#define MIPS32_DRET 0x4200001F
extern int mips32_arch_state(struct target_s *target);
-extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, int chain_pos, const char *variant);
+extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap, const char *variant);
extern int mips32_restore_context(target_t *target);
extern int mips32_save_context(target_t *target);
extern reg_cache_t *mips32_build_reg_cache(target_t *target);
int mips_ejtag_set_instr(mips_ejtag_t *ejtag_info, int new_instr, in_handler_t handler)
{
- jtag_device_t *device = jtag_get_device(ejtag_info->chain_pos);
- if (device==NULL)
+ jtag_tap_t *tap;
+
+ tap = ejtag_info->tap;
+ if (tap==NULL)
return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
u8 t[4];
- field.device = ejtag_info->chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = t;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
- field.device = ejtag_info->chain_pos;
+ field.tap = ejtag_info->tap;
field.num_bits = 32;
field.out_value = NULL;
field.out_mask = NULL;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
- field.device = ejtag_info->chain_pos;
+ field.tap = ejtag_info->tap;
field.num_bits = 32;
field.out_value = NULL;
field.out_mask = NULL;
int mips_ejtag_drscan_32(mips_ejtag_t *ejtag_info, u32 *data)
{
- jtag_device_t *device;
- device = jtag_get_device(ejtag_info->chain_pos);
+ jtag_tap_t *tap;
+ tap = ejtag_info->tap;
- if (device==NULL)
+ if (tap==NULL)
return ERROR_FAIL;
scan_field_t field;
u8 t[4];
int retval;
- field.device = ejtag_info->chain_pos;
+ field.tap = tap;
field.num_bits = 32;
field.out_value = t;
buf_set_u32(field.out_value, 0, field.num_bits, *data);
typedef struct mips_ejtag_s
{
- int chain_pos;
+ jtag_tap_t *tap;
u32 impcode;
/*int use_dma;*/
u32 ejtag_ctrl;
return ERROR_OK;
}
-int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, int chain_pos, const char *variant)
+int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant)
{
mips32_common_t *mips32 = &mips_m4k->mips32_common;
mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
/* initialize mips4k specific info */
- mips32_init_arch_info(target, mips32, chain_pos, variant);
+ mips32_init_arch_info(target, mips32, tap, variant);
mips32->arch_info = mips_m4k;
return ERROR_OK;
{
mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
- mips_m4k_init_arch_info(target, mips_m4k, target->chain_position, target->variant);
+ mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant);
return ERROR_OK;
}
{ .value = TARGET_EVENT_EXAMINE_START, .name = "examine-start" },
- { .value = TARGET_EVENT_EXAMINE_START, .name = "examine-end" },
+ { .value = TARGET_EVENT_EXAMINE_END, .name = "examine-end" },
{ .value = TARGET_EVENT_DEBUG_HALTED, .name = "debug-halted" },
}
DumpTargets:
- target = all_targets;
- command_print(cmd_ctx, " CmdName Type Endian ChainPos State ");
- command_print(cmd_ctx, "-- ---------- ---------- ---------- -------- ----------");
+ target = all_targets;
+ command_print(cmd_ctx, " CmdName Type Endian AbsChainPos Name State ");
+ command_print(cmd_ctx, "-- ---------- ---------- ---------- ----------- ------------- ----------");
while (target)
{
/* XX: abcdefghij abcdefghij abcdefghij abcdefghij */
- command_print(cmd_ctx, "%2d: %-10s %-10s %-10s %8d %s",
+ command_print(cmd_ctx, "%2d: %-10s %-10s %-10s %10d %14s %s",
target->target_number,
target->cmd_name,
target->type->name,
Jim_Nvp_value2name_simple( nvp_target_endian, target->endianness )->name,
- target->chain_position,
+ target->tap->abs_chain_position,
+ target->tap->dotted_name,
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
target = target->next;
}
static int runSrstAsserted;
static int runSrstDeasserted;
-static int sense_handler()
+static int sense_handler(void)
{
static int prevSrstAsserted = 0;
static int prevPowerdropout = 0;
break;
case TCFG_CHAIN_POSITION:
if( goi->isconfigure ){
+ Jim_Obj *o;
+ jtag_tap_t *tap;
target_free_all_working_areas(target);
- e = Jim_GetOpt_Wide( goi, &w );
+ e = Jim_GetOpt_Obj( goi, &o );
if( e != JIM_OK ){
return e;
}
- if (jtag_get_device(w)==NULL)
+ tap = jtag_TapByJimObj( goi->interp, o );
+ if( tap == NULL ){
return JIM_ERR;
-
+ }
/* make this exactly 1 or 0 */
- target->chain_position = w;
+ target->tap = tap;
} else {
if( goi->argc != 0 ){
goto no_params;
}
}
- Jim_SetResult( interp, Jim_NewIntObj( goi->interp, target->chain_position ) );
+ Jim_SetResultString( interp, target->tap->dotted_name, -1 );
/* loop for more e*/
break;
}
target_type_t *type; /* target type definition (name, access functions) */
const char *cmd_name; /* tcl Name of target */
int target_number; /* generaly, target index but may not be in order */
- int chain_position; /* where on the jtag chain is this */
+ jtag_tap_t *tap; /* where on the jtag chain is this */
const char *variant; /* what varient of this chip is it? */
target_event_action_t *event_action;
## -*- tcl -*-
##
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s3c2410
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # This config file was defaulting to big endian..
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+
+
jtag_nsrst_delay 200
jtag_ntrst_delay 200
## JTAG scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
##
## Target configuration
##
-target create target0 arm7tdmi -endian little -chain-position 0
-
-## software initiated reset (if your SRST isn't wired)
-#proc target_0_reset {} { mwb 0x0ffff0230 04 }
-
-# use top 1k of SRAM for as temporary JTAG memory
-#[new_target_name] configure -work-area-virt 0 -work-area-phys 0x11C00 -work-area-size 0x400 -work-area-backup 1
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
## flash configuration
flash bank aduc702x 0x80000 0x10000 2 2 0
set watchdog_hdl [after 500 watchdog_service]
}
-[new_target_name] configure -event reset-halt-post { watchdog_service }
-[new_target_name] configure -event old-pre_resume { global watchdog_hdl; after cancel $watchdog_hdl }
+$_TARGETNAME configure -event reset-halt-post { watchdog_service }
+$_TARGETNAME configure -event old-pre_resume { global watchdog_hdl; after cancel $watchdog_hdl }
#Script for AT91EB40a
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME at91eb40a
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+
#Atmel ties SRST & TRST together, at which point it makes
#no sense to use TRST, but use TMS instead.
#
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
#target configuration
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
# speed up memory downloads
arm7_9 fast_memory_access enable
# required for usable performance. Used for lots of
# other things than flash programming.
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
puts "Running reset init script for AT91EB40A"
# Reset script for AT91EB40a
reg cpsr 0x000000D3
+
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME at9r40008
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
jtag_nsrst_delay 200
jtag_ntrst_delay 200
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGENAME -variant arm7tdmi
-[new_target_name] configure -event gdb-flash-erase-start {
+$_TARGETNAME configure -event gdb-flash-erase-start {
wait_halt
sleep 10
poll
mww 0xffe00020 0x00000001
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0
flash bank cfi 0x10000000 0x400000 2 2 0
--- /dev/null
+
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME at91rm9200
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x05b0203f
+}
+
+# Never allow the following!
+if { $_CPUTAPID == 0x15b0203f } {
+ puts "-------------------------------------------------------"
+ puts "- ERROR: -"
+ puts "- ERROR: TapID 0x15b0203f is wrong for at91rm9200 -"
+ puts "- ERROR: The chip/board has a JTAG select pin/jumper -"
+ puts "- ERROR: -"
+ puts "- ERROR: In one position (0x05b0203f) it selects the -"
+ puts "- ERROR: ARM CPU, in the other position (0x1b0203f) -"
+ puts "- ERROR: it selects boundry-scan not the ARM -"
+ puts "- ERROR: -"
+ puts "-------------------------------------------------------"
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+# Create the GDB Target.
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
+# AT91RM9200 has a 16K block of sram @ 0x0020.0000
+$_TARGETNAME configure -work-area-virt 0x00200000 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
+
+# This chip has a DCC ... use it
+arm7_9 dcc_downloads enable
+
+
+
+
+
# Target: Atmel AT91SAM9260
######################################
-reset_config trst_and_srst
-
-#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
-jtag_device 4 0x1 0xf 0xe
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 0
+# We add to the minimal configuration.
+source [find target/at91sam9260minimal.cfg]
######################
# Target configuration
######################
-target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs
-
-[new_target_name] configure -event reset-init {
+$_TARGET_NAME configure -event reset-init {
+ # at reset chip runs at 32khz
+ jtag_khz 8
mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
sleep 10 # wait 10 ms
- jtag_speed 0 # Increase JTAG Speed to 6 MHz
+ # Now run at anything fast... ie: 10mhz!
+ jtag_khz 10000 # Increase JTAG Speed to 6 MHz
arm7_9 dcc_downloads enable # Enable faster DCC downloads
mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
#####################
# Flash configuration
# Target: Atmel AT91SAM9260
######################################
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME at91sam9260
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
reset_config trst_and_srst
-#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
-jtag_device 4 0x1 0xf 0xe
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag_nsrst_delay 200
jtag_ntrst_delay 200
# Target configuration
######################
-target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# Internal sram1 memory
+$_TARGET_NAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
+++ /dev/null
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-
-
-[new_target_name] configure -event reset-init {
- # WDT_MR, disable watchdog
- mww 0xFFFFFD44 0x00008000
-
- # RSTC_MR, enable user reset
- mww 0xfffffd08 0xa5000001
-
- # CKGR_MOR
- mww 0xFFFFFC20 0x00000601
- sleep 10
-
- # CKGR_PLLR
- mww 0xFFFFFC2C 0x00481c0e
- sleep 10
-
- # PMC_MCKR
- mww 0xFFFFFC30 0x00000007
- sleep 10
-
- # PMC_IER
- mww 0xFFFFFF60 0x00480100
-
- #
- # Enable SDRAM interface.
- #
-
- # Enable SDRAM control at PIO A.
- mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
- mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
-
- # Enable address bus (A0, A2-A11, A13-A17) at PIO B
- mww 0xfffff674 0x0003effd # PIO_BSR_OFF
- mww 0xfffff604 0x0003effd # PIO_PDR_OFF
-
- # Enable 16 bit data bus at PIO C
- mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
- mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
-
- # Enable SDRAM chip select
- mww 0xffffff80 0x00000002 # EBI_CSA_OFF
-
- # Set SDRAM characteristics in configuration register.
- # Hard coded values for MT48LC32M16A2 with 48MHz CPU.
- mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
- sleep 10
-
- # Issue 16 bit SDRAM command: NOP
- mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
-
- # Issue 16 bit SDRAM command: Precharge all
- mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
-
- # Issue 8 auto-refresh cycles
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
-
- # Issue 16 bit SDRAM command: Set mode register
- mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
- mww 0x20000014 0xcafedede
-
- # Set refresh rate count ???
- mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
-
- # Issue 16 bit SDRAM command: Normal mode
- mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
- mww 0x20000000 0x00000180
-
- #
- # Enable external reset key.
- #
- mww 0xfffffd08 0xa5000001
-}
-
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank at91sam7 0 0 0 0 0
-
-# For more information about the configuration files, take a
-# look at the "Open On-Chip Debugger (openocd)" documentation.
# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
-jtag_device 4 0x1 0xf 0xe
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ep9301
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag_nsrst_delay 100
jtag_ntrst_delay 100
-target create target0 arm920t -endian little -chain-position 0 -work-area-virt 0 -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-virt 0 -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1
#flash configuration
#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
+++ /dev/null
-# Target Configuration for the TinCanTools S3C2410 Based Hammer Module
-# http://www.tincantools.com
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-
-
-target create target0 arm920t -endian little -chain-position 0 -variant arm920t
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0
-[new_target_name] configure -event reset-init {
- # Reset Script for the TinCanTools S3C2410 Based Hammer Module
- # http://www.tincantools.com
- #
- # Setup primary clocks and initialize the SDRAM
- mww 0x53000000 0x00000000
- mww 0x4a000008 0xffffffff
- mww 0x4a00000c 0x000007ff
- mww 0x4c000000 0x00ffffff
- mww 0x4c000014 0x00000003
- mww 0x4c000004 0x000a1031
- mww 0x48000000 0x11111122
- mww 0x48000004 0x00000700
- mww 0x48000008 0x00000700
- mww 0x4800000c 0x00000700
- mww 0x48000010 0x00000700
- mww 0x48000014 0x00000700
- mww 0x48000018 0x00000700
- mww 0x4800001c 0x00018005
- mww 0x48000020 0x00018005
- mww 0x48000024 0x009c0459
- mww 0x48000028 0x000000b2
- mww 0x4800002c 0x00000030
- mww 0x48000030 0x00000030
- flash probe 0
-}
-
-# speed up memory downloads
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-#flash configuration
-#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
-flash bank cfi 0x00000000 0x1000000 2 2 0
# iMote2
#
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME imote2
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
# PXA271 and an Intel Strataflash of 32 Megabytes (p30)
#
# Marvell/Intel PXA270 Script
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 0
-#use combined on interfaces or targets that can\92t set TRST/SRST separately
+#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst separate
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
-target xscale little 0 pxa27x
+
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -varient pxa27x
+$_TARGETNAME configure -work-area-virt 0x0x5c000000 -work-area-phys 0x0x5c000000 -work-area-size 0x10000 -work-area-backup 1
# maps to PXA internal RAM. If you are using a PXA255
# you must initialize SDRAM or leave this option off
-working_area 0 0x5c000000 0x10000 nobackup
+
#flash bank <driver> <base> <size> <chip_width> <bus_width>
# works for P30 flash
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
-# There are 2 taps on the chip:
-# The ETM
-jtag_device 4 0x1 0xf 0xe
-# The ARM926EJS
-jtag_device 4 0x1 0xf 0xe
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME imx27
+}
-# Note above there are 2 taps (#0 and #1) the ARM926 is the 2nd tap (ie #1)
-target create target0 arm926ejs -endianess little -chain-position 1 -variant arm926ejs
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# Note above there are 2 taps
+
+# The bs tap
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0x1b900f0f
+}
+jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_BSTAPID
+
+# The CPU tap
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x07926121
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Create the GDB Target.
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 -work-area-size 0x8000 -work-area-backup 1
+# Internal to the chip, there is 45K of SRAM
+#
+
+arm7_9 dcc_downloads enable
#
# NB! Does not work yet. Work in progress
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-# 4 devices otherwise openocd complains, the last one returns 0x0 for all bytes
-jtag_device 4 0x1 0x0 0xe
-jtag_device 5 0x1 0x1f 0x1e
-#jtag_device 4 0x0 0x0 0xe
-# The device below does not have an IDCODE, so lsb is 1
-jtag_device 4 0x0 0x0 0xf
-jtag_device 5 0x1 0x0 0x1e
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME imx31
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+#========================================
+# The "system jtag controller"
+# IMX31 reference manual, page 6-28 - figure 6-14
+if { [info exists SJCTAPID ] } {
+ set _SJCTAPID $SJCTAPID
+} else {
+ set _SJCTAPID 0xffffffff
+}
+jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 00 irmask 0x0 -expected-id $_SJCTAPID
+
+# The "SDMA" - <S>mart <DMA> controller debug tap
+# Based on some IO pins - this can be disabled & removed
+# See diagram: 6-14
+# SIGNAL NAME:
+# SJC_MOD - controls multiplexer - disables ARM1136
+# SDMA_BYPASS - disables SDMA -
+#
+if { [info exists SDMATAPID ] } {
+ set _SDMATAPID $SDMATAPID
+} else {
+ set _SDMATAPID 0xffffffff
+}
+# Per section 40.17.1, table 40-85 the IR register is 4 bits
+# But this conflicts with Diagram 6-13, "3bits ir and drs"
+jtag newtap $_CHIPNAME smda -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_SJCTAPID
+
+# The ARM11 core tap
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e irmask 0x1f -expected-id $_SJCTAPID
+
jtag_nsrst_delay 500
jtag_ntrst_delay 500
-target create target0 arm11 -endian little -chain-position 1
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
#xscale ixp42x CPU
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ipx42x
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+ set _ENDIAN big
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
#use combined on interfaces or targets that can?t set TRST/SRST separately
reset_config srst_only srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
-target create target0 xscale -endian big -chain-position 0 -variant IXP42x
+
+jtag newtap $_CPUNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ipxP42x
# script for Insilica IS-5114
+# AKA: Atmel AT76C114 - an ARM946 chip
+# ATMEL sold his product line to Insilica...
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME is5114
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a little endian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
# jtag speed. We need to stick to 16kHz until we've finished reset.
jtag_rclk 16
reset_config trst_and_srst
-jtag_device 8 0x1 0x1 0xfe
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
+# Do not specify a tap id here...
+#OLD SYNTAX: jtag_device 8 0x1 0x1 0xfe
+jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1
+#OLD SYNTAX: jtag_device 4 0x1 0xf 0xe
+# This is the "arm946" chip.
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf
+#OLD SYNTAX: jtag_device 5 0x1 0x1 0x1e
+jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
+
#arm946e-s and
-target arm966e little 1 arm966e
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -varient arm966e
-[new_target_name] configure -event reset-start { jtag_rclk 16 }
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
+$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
jtag_rclk 3000
}
-working_area 0 0x50000000 16384 nobackup
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
# NB! work in progress! Duplicated from lm3s811.cfg, but does
# it need modification??
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lm3s3748
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a little endian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
# RCLK
jtag_khz 500
reset_config srst_only
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
+
# the luminary variant causes a software reset rather than asserting SRST
# this stops the debug registers from being cleared
# this will be fixed in later revisions of silicon
-target create target0 cortex_m3 -endian little -chain-position 0 -variant lm3s
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
# 8k working area at base of ram
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
#flash configuration
flash bank stellaris 0 0 0 0 0
# script for luminary lm3s6965
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lm3s6965
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a little endian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
# jtag speed
jtag_khz 500
reset_config srst_only
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
+
# the luminary variant causes a software reset rather than asserting SRST
# this stops the debug registers from being cleared
# this will be fixed in later revisions of silicon
-target create target0 cortex_m3 -endian little -chain-position 0 -variant lm3s
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
# 4k working area at base of ram
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
#flash configuration
flash bank stellaris 0 0 0 0 0
# Script for luminary lm3s811
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lm3s811
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a little endian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
# jtag speed
jtag_khz 500
reset_config srst_only
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
# the luminary variant causes a software reset rather than asserting SRST
# this stops the debug registers from being cleared
# this will be fixed in later revisions of silicon
-target create target0 cortex_m3 -endian little -chain-position 0 -variant lm3s
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
# 8k working area at base of ram
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
#flash configuration
flash bank stellaris 0 0 0 0 0
#LPC-2129 CPU
-#use combined on interfaces or targets that can\92t set TRST/SRST separately
+
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lpc2129
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lpc2148
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
#delays on reset lines
jtag_nsrst_delay 200
jtag_ntrst_delay 200
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
-[new_target_name] configure -event reset-init {
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -event reset-init {
# Force target into ARM state
soft_reset_halt
#do not remap 0x0000-0x0020 to anything but the flash
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
# 2MHz
jtag_khz 2000
script target/lpc2148.cfg
+
# RCLK
jtag_khz 0
script target/lpc2148.cfg
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lpc2294
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash configuration
#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
#Hilscher netX 500 CPU
-#use combined on interfaces or targets that can\92t set TRST/SRST separately
+
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME netx500
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag_nsrst_delay 100
jtag_ntrst_delay 100
-target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-# use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only
-
-# jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
-
-# target configuration
-target create target0 xscale -endian big -chain-position 0 -variant ixp42x
-
-
-# maps to PXA internal RAM. If you are using a PXA255
-# you must initialize SDRAM or leave this option off
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
-
-# flash bank <driver> <base> <size> <chip_width> <bus_width>
-#flash bank cfi 0x50000000 0x1000000 2 4 0
-
-
+# This is for the LinkSys (CYSCO) LSLU2 board
+# It is an Intel XSCALE IPX420 CPU.
+source [find target/ipx42x.cfg]
+# The _TARGETNAME is set by the above.
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
#TI OMAP5912 dual core processor - http://www.ti.com
#on a OMAP5912 OSK board http://www.spectrumdigital.com.
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME omap5912
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 38 0x0 0x0 0x0
-jtag_device 4 0x1 0x0 0xe
-jtag_device 8 0x0 0x0 0x0
+jtag newtap $_CHIPNAME unknown1 -irlen 38 -ircapture 0x0 -irmask 0x0
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME unknown2 irlen 8 -ircapture 0x0 -irmask 0x0
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-target create target0 arm926ejs -endian little -chain-position 1 -variant arm926ejs
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
#
# halt target
#
}
# omap5912 lcd frame buffer as working area
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x3e800 -work-area-backup 0
+$_TARGENAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x3e800 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank cfi 0x00000000 0x1000000 2 2 0
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME pic32mx
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
jtag_nsrst_delay 100
jtag_ntrst_delay 100
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 5 0x1 0x1 0x1e
+jtag newtap $_CPUNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
-target create target0 mips_m4k -endian little -chain-position 0
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
-#flash bank str7x <base> <size> 0 0 <target#> <variant>
-#flash bank stm32x 0 0 0 0 0
# For more information about the configuration files, take a look at:
# openocd.texi
-jtag_device 5 0x1 0x1f 0x1e
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME pxa255
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
jtag_nsrst_delay 200
jtag_ntrst_delay 200
-
-target create target0 xscale -endian little -chain-position 0 -variant pxa255
-[new_target_name] configure -event reset-init {
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa255
+$_TARGETNAME configure -event reset-init {
xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
#
# setup GPIO
# RAM at 0x4000000
# Flash at 0x00000000
#
-script target/pxa255.cfg
+source [find target/pxa255.cfg]
+# Target name is set by above
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
#Marvell/Intel PXA270 Script
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME pxa270
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+
# set jtag_nsrst_delay to the delay introduced by your reset circuit
# the rest of the needed delays are built into the openocd program
jtag_nsrst_delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 0
-#use combined on interfaces or targets that can\92t set TRST/SRST separately
+#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst separate
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
-target create target0 xscale -endian little -chain-position 0 -variant pxa27x
+
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+jtag newtap $_TARGETNAME -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
# maps to PXA internal RAM. If you are using a PXA255
# you must initialize SDRAM or leave this option off
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
# works for P30 flash
# Tested on a S3C2440 Evaluation board
# Processor : ARM920Tid(wb) rev 0 (v4l)
# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places]
+# [and I do not believe it to be accurate, hence the 0xffffffff below]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s3c2440
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xFFFFFFFF
+}
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-target create target0 arm920t -endian little -chain-position 0 -variant arm920t
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1
#reset configuration
reset_config trst_and_srst
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1
--- /dev/null
+
+# ATMEL sam7se512
+# Example: the "Elektor Internet Radio" - EIR
+# http://www.ethernut.de/en/hardware/eir/index.html
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME sam7se512
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# The target
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+flash bank at91sam7 0 0 0 0 0
+
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config srst_only srst_pulls_trst
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME sam7x256
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-[new_target_name] configure -event reset-init {
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+$_TARGETNAME configure -event reset-init {
# disable watchdog
mww 0xfffffd44 0x00008000
# enable user reset
sleep 100
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank at91sam7 0 0 0 0 0
--- /dev/null
+# Found on the 'TinCanTools' Hammer board.
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s3c2410
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # This config file was defaulting to big endian..
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that cannot set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
--- /dev/null
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s3c4510
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+
+# This appears to be a "Version 1" arm7tdmi.
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x1f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
--- /dev/null
+# -*- tcl -*-
+# Target configuration for the Samsung s3c6410 system on chip
+# Tested on a SMDK6410
+# Processor : ARM1176
+# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places]
+# [and I do not believe it to be accurate, hence the 0xffffffff below]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s3c6410
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+ set _ENDIAN little
+}
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ # force an error till we get a good number
+ set _BSTAPID 0xffffffff
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+#jtag scan chain
+
+# I think the "unknown" is the boundry scan tap
+jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0xe -expected-id $_BSTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -varient arm1176
+
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+#reset configuration
+reset_config trst_and_srst
--- /dev/null
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lh79532
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # sharp changed the number!
+ set _CPUTAPID 0x00002061
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+
# Processor : ARM1176
# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1f 0xe
-
-#target create target0 arm11 -endian little -chain-position 0 -variant arm1176
-target arm11 little reset_halt 1
-
-jtag_nsrst_delay 500
-jtag_ntrst_delay 500
-
-#reset configuration
-reset_config trst_and_srst
+source [find target/samsung_s3c6410.cfg]
flash bank cfi 0x00000000 0x00100000 2 2 0 jedec_probe
\ No newline at end of file
# script for stm32
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+
# jtag speed
jtag_khz 500
reset_config trst_and_srst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
-
-target create target0 cortex_m3 -endian little -chain-position 0
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.3
+ set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.2
+ # Medium Density RevA
+ set _BSTAPID 0x06410041
+ # Rev B and Rev Z
+ set _BSTAPID 0x16410041
+ # High Density Devices, Rev A
+ set _BSTAPID 0x06414041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-#flash bank str7x <base> <size> 0 0 <target#> <variant>
flash bank stm32x 0 0 0 0 0
# For more information about the configuration files, take a look at:
# Hitex stm32 performance stick
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32_hitex
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
# set jtag speed
jtag_khz 500
reset_config trst_and_srst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
-jtag_device 4 0x1 0xf 0xe
+# The CPU
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.3
+ set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
+
+# The boundery scan register, leave the "expected-id" undefined.
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1e
+
+# What is this? It must be some extra chip on the stm32stick...
+jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
-target create target0 cortex_m3 -endian little -chain-position 0
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-#flash bank str7x <base> <size> 0 0 <target#> <variant>
+#
flash bank stm32x 0 0 0 0 0
# For more information about the configuration files, take a look at:
#start slow, speed up after reset
jtag_khz 10
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str710
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-[new_target_name] configure -event reset-start { jtag_khz 10 }
-[new_target_name] configure -event reset-init { jtag_khz 6000 }
-[new_target_name] configure -event gdb-flash-erase-start {
+tag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+$_TARGETNAME configure -event reset-start { jtag_khz 10 }
+$_TARGETNAME configure -event reset-init { jtag_khz 6000 }
+$_TARGETNAME configure -event gdb-flash-erase-start {
flash protect 0 0 7 off
flash protect 1 0 1 off
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
#flash bank str7x <base> <size> 0 0 <target#> <variant>
flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
#STR730 CPU
-
jtag_khz 3000
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str730
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+
-#use combined on interfaces or targets that can\92t set TRST/SRST separately
+#use combined on interfaces or targets that can't set TRST/SRST separately
#reset_config trst_and_srst srst_pulls_trst
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+tag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
#jtag nTRST and nSRST delay
jtag_nsrst_delay 500
jtag_ntrst_delay 500
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-[new_target_name] configure -event reset-start { jtag_khz 10 }
-[new_target_name] configure -event reset-init { jtag_khz 3000 }
-[new_target_name] configure -event gdb-flash-erase-start {
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
+$_TARGETNAME configure -event reset-start { jtag_khz 10 }
+$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
+$_TARGETNAME configure -event gdb-flash-erase-start {
flash protect 0 0 7 off
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank str7x 0x20000000 0x00040000 0 0 0 STR3x
#STR750 CPU
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str750
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xffffffff
+}
+
# jtag speed
jtag_khz 10
-#use combined on interfaces or targets that can\92t set TRST/SRST separately
+#use combined on interfaces or targets that can't set TRST/SRST separately
#reset_config trst_and_srst srst_pulls_trst
reset_config trst_and_srst srst_pulls_trst
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+
+tag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
#jtag nTRST and nSRST delay
jtag_nsrst_delay 500
jtag_ntrst_delay 500
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-[new_target_name] configure -event reset-start { jtag_khz 10 }
-[new_target_name] configure -event reset-init { jtag_khz 3000 }
-[new_target_name] configure -event gdb-flash-erase-start {
+$_TARGETNAME configure -event reset-start { jtag_khz 10 }
+$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
+$_TARGETNAME configure -event gdb-flash-erase-start {
flash protect 0 0 7 off
flash protect 1 0 1 off
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank str7x 0x20000000 0x00040000 0 0 0 STR75x
# Need reset scripts
reset_config trst_and_srst
-jtag_device 8 0x1 0x1 0xfe
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str912
+}
-target arm966e little reset_halt 1 arm966e
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
-working_area 0 0x50000000 16384 nobackup
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ # Fixme with a correct number!
+ set _FLASHTAPID 0xFFFFFFFF
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0xfe -expected-id $_FLASHTAPID
+
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xe -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0xFFFFFFFF
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1e -expected-id $_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
flash bank str9xpec 0x00000000 0x00080000 0 0 0
# script for str9
-# jtag speed. We need to stick to 16kHz until we've finished reset.
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str912
+}
-jtag_rclk 16
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# jtag speed. We need to stick to 16kHz until we've finished reset.
+jtag_rclk 16
+
jtag_nsrst_delay 100
jtag_ntrst_delay 100
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 8 0x1 0x1 0xfe
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ set _FLASHTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0xfe -expected-id $_FLASHTAPID
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xe -expected-id $_CPUTAPID
+
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0x1457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1e -expected-id $_BSTAPID
-target create target0 arm966e -endian little -chain-position 1 -variant arm966e
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-[new_target_name] configure -event reset-start { jtag_rclk 16 }
+$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
- jtag_rclk 3000
+ #jtag_rclk 3000
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
flash protect 0 0 7 off
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
#flash bank str9x <base> <size> 0 0 <target#> <variant>
flash bank str9x 0x00000000 0x00080000 0 0 0
jtag_nsrst_delay 100
jtag_ntrst_delay 100
-#use combined on interfaces or targets that can\92t set TRST/SRST separately
+#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 8 0x1 0x1 0xfe
-jtag_device 4 0x1 0xf 0xe
-jtag_device 5 0x1 0x1 0x1e
-target create target0 arm966e -endian little -chain-position 1 -variant arm966e
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+
+
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ set _FLASHTAPID 0xFFFFFFFF
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
+
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0xFFFFFFFF
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank str9x 0x00000000 0x00080000 0 0 0
# at91eb40a target
#jtag scan chain
-jtag_device 4 0x1 0xf 0xe
+set _CHIPNAME syntaxtest
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
#target configuration
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
syntax error
}
+# FIXME: THIS IS A *BOARD* not a CHIP configuration.
######################################
# Target: DIGI ConnectCore Wi-9C
######################################
reset_config trst_and_srst
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ns9360
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # This config file was defaulting to big endian..
+ set _ENDIAN big
+}
+
+
# What's a good fallback frequency for this board if RCLK is
# not available??
jtag_rclk 1000
-#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
-jtag_device 4 0x1 0xf 0xe
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xFFFFFFFF
+}
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+jtag newtap_device $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag_nsrst_delay 200
jtag_ntrst_delay 0
# Target configuration
######################
-target create target0 arm926ejs -endian big -chain-position 0 -variant arm926ejs
-[new_target_name] configure -event reset-init {
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+$_TARGETNAME configure -event reset-init {
mww 0x90600104 0x33313333
mww 0xA0700000 0x00000001 # Enable the memory controller.
mww 0xA0700024 0x00000006 # Set the refresh counter 6
reg cpsr 0xd3
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
#####################
# Flash configuration
#Written by: Michael Schwingen <rincewind@discworld.dascon.de>
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME xba_reva3
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # default to big endian
+ set _ENDIAN big
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
reset_config trst_and_srst separate
jtag_nsrst_delay 100
jtag_ntrst_delay 100
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR capture Mask, IDCODE)
-jtag_device 7 0x1 0x7f 0x7e
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
-target create target0 xscale -endian big -chain-position 0 -variant ixp42x
-[new_target_name] configure -event reset-init {
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
+$_TARGETNAME configure -event reset-init {
#############################################################################
# setup expansion bus CS, disable external wdt
#############################################################################
flash probe 0
}
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0
flash bank cfi 0x50000000 0x400000 2 2 0
#SRST reset, which means that the CPU will run a number
#of cycles before it can be halted(as much as milliseconds).
reset_config srst_only srst_pulls_trst
+
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME zy1000
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # sharp changed the number!
+ set _CPUTAPID 0x3f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
# at CPU CLK <32kHz this must be disabled
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
-[new_target_name] configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
# Set up chip selects & timings
mww 0xFFE00000 0x0100273D
mww 0xFFE00004 0x08002125
# required for usable performance. Used for lots of
# other things than flash programming.
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
jtag_khz 16000
return ERROR_OK;
}
-int xscale_jtag_set_instr(int chain_pos, u32 new_instr)
+int xscale_jtag_set_instr(jtag_tap_t *tap, u32 new_instr)
{
- jtag_device_t *device = jtag_get_device(chain_pos);
- if (device==NULL)
+ if (tap==NULL)
return ERROR_FAIL;
- if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
+ if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
- field.device = chain_pos;
- field.num_bits = device->ir_length;
+ field.tap = tap;
+ field.num_bits = tap->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.out_mask = NULL;
field.in_value = NULL;
- jtag_set_check_value(&field, device->expected, device->expected_mask, NULL);
+ jtag_set_check_value(&field, tap->expected, tap->expected_mask, NULL);
jtag_add_ir_scan(1, &field, -1);
u8 field2_check_mask = 0x1;
jtag_add_end_state(TAP_PD);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
fields[0].out_mask = NULL;
fields[0].in_value = NULL;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
fields[2].out_mask = NULL;
path[1] = TAP_CD;
path[2] = TAP_SD;
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_value = NULL;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = NULL;
fields[2].out_mask = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
/* repeat until all words have been collected */
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
path[0] = TAP_SDS;
path[1] = TAP_CD;
noconsume_path[4] = TAP_E2D;
noconsume_path[5] = TAP_SD;
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_value = &field0_in;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].out_mask = NULL;
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = NULL;
fields[2].out_mask = NULL;
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0_out;
fields[0].out_mask = NULL;
fields[0].in_value = &field0_in;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
fields[1].out_mask = NULL;
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
fields[2].out_mask = NULL;
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
bits[0]=3;
t[0]=0;
LOG_ERROR("BUG: size neither 4, 2 nor 1");
exit(-1);
}
- jtag_add_dr_out(xscale->jtag_info.chain_pos,
+ jtag_add_dr_out(xscale->jtag_info.tap,
3,
bits,
t,
xscale->external_debug_break = ext_dbg_brk;
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
fields[0].out_mask = NULL;
fields[0].in_value = NULL;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].out_mask = NULL;
- fields[2].device = xscale->jtag_info.chain_pos;
+ fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
fields[2].out_mask = NULL;
LOG_DEBUG("loading miniIC at 0x%8.8x", va);
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD is b010 for Main IC and b011 for Mini IC */
if (mini)
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
fields[1].out_mask = NULL;
scan_field_t fields[2];
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD for invalidate IC line b000, bits [6:4] b000 */
buf_set_u32(&cmd, 0, 6, 0x0);
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
- fields[0].device = xscale->jtag_info.chain_pos;
+ fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
- fields[1].device = xscale->jtag_info.chain_pos;
+ fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
fields[1].out_mask = NULL;
* end up in T-L-R, which would reset JTAG
*/
jtag_add_end_state(TAP_RTI);
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
/* set Hold reset, Halt mode and Trap Reset */
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
xscale_write_dcsr(target, 1, 0);
/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
- xscale_jtag_set_instr(xscale->jtag_info.chain_pos, 0x7f);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, 0x7f);
jtag_execute_queue();
/* assert reset */
return ERROR_OK;
}
-int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_pos, const char *variant)
+int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t *tap, const char *variant)
{
armv4_5_common_t *armv4_5;
u32 high_reset_branch, low_reset_branch;
xscale->variant = strdup(variant);
/* prepare JTAG information for the new target */
- xscale->jtag_info.chain_pos = chain_pos;
+ xscale->jtag_info.tap = tap;
xscale->jtag_info.dbgrx = 0x02;
xscale->jtag_info.dbgtx = 0x10;
{
xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t));
- xscale_init_arch_info(target, xscale, target->chain_position, target->variant);
+ xscale_init_arch_info(target, xscale, target->tap, target->variant);
xscale_build_reg_cache(target);
return ERROR_OK;
typedef struct xscale_jtag_s
{
/* position in JTAG scan chain */
- int chain_pos;
+ jtag_tap_t *tap;
/* IR length and instructions */
int ir_length;
int runtest_requires_tck = 0;
- int device = -1; /* use -1 to indicate a "plain" xsvf file which accounts for additional devices in the scan chain, otherwise the device that should be affected */
+ jtag_tap_t *tap = NULL;
+ /* use NULL to indicate a "plain" xsvf file which accounts for
+ additional devices in the scan chain, otherwise the device
+ that should be affected */
if (argc < 2)
{
if (strcmp(args[0], "plain") != 0)
{
- device = strtoul(args[0], NULL, 0);
+ tap = jtag_TapByString( args[0] );
+ if( !tap ){
+ command_print( cmd_ctx, "Tap: %s unknown", args[0] );
+ return ERROR_OK;
+ }
}
if ((xsvf_fd = open(args[1], O_RDONLY)) < 0)
else
{
scan_field_t field;
- field.device = device;
+ field.tap = tap;
field.num_bits = c;
field.out_value = ir_buf;
field.out_mask = NULL;
field.in_check_mask = NULL;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- if (device == -1)
+ if (tap == NULL)
jtag_add_plain_ir_scan(1, &field, TAP_PI);
else
jtag_add_ir_scan(1, &field, TAP_PI);
else
{
scan_field_t field;
- field.device = device;
+ field.tap = tap;
field.num_bits = xsdrsize;
field.out_value = dr_out_buf;
field.out_mask = NULL;
field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
- if (device == -1)
+ if (tap == NULL)
jtag_add_plain_dr_scan(1, &field, TAP_PD);
else
jtag_add_dr_scan(1, &field, TAP_PD);
else
{
scan_field_t field;
- field.device = device;
+ field.tap = tap;
field.num_bits = xsdrsize;
field.out_value = dr_out_buf;
field.out_mask = NULL;
field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
- if (device == -1)
+ if (tap == NULL)
jtag_add_plain_dr_scan(1, &field, TAP_PD);
else
jtag_add_dr_scan(1, &field, TAP_PD);
else
{
scan_field_t field;
- field.device = device;
+ field.tap = tap;
field.num_bits = us;
field.out_value = ir_buf;
field.out_mask = NULL;
field.in_check_mask = NULL;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- if (device == -1)
+ if (tap == NULL)
jtag_add_plain_ir_scan(1, &field, xsvf_to_tap[xendir]);
else
jtag_add_ir_scan(1, &field, xsvf_to_tap[xendir]);
projects / openocd / commitdiff