/*\r
This is the default Startup for STR75x devices for the GNU toolchain\r
\r
-It has been designed by ST Microelectronics and modified by Raisonance.\r
+It has been designed by ST Microelectronics and modified by Raisonance\r
+and FreeRTOS.org.\r
\r
You can use it, modify it, distribute it freely but without any waranty.\r
\r
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.\r
*/\r
\r
+\r
+/*-----------------------------------------------------------\r
+ * Components that can be compiled to either ARM or THUMB mode are\r
+ * contained in this file.c The ISR routines, which can only be compiled\r
+ * to ARM mode, are contained in serialISR.c.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+\r
/* Library includes. */\r
#include "75x_uart.h"\r
#include "75x_gpio.h"\r
***************************************************************************\r
*/\r
\r
+/*-----------------------------------------------------------\r
+ * Components that can be compiled to either ARM or THUMB mode are\r
+ * contained in serial.c The ISR routines, which can only be compiled\r
+ * to ARM mode, are contained in this file.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+\r
/* Library includes. */\r
#include "75x_uart.h"\r
\r
#include "..\..\Source\portable\IAR\STR75x\portmacro.h"\r
#endif\r
\r
+#ifdef STR75X_GCC\r
+ #include "..\..\Source\portable\GCC\STR75x\portmacro.h"\r
+#endif\r
+\r
#ifdef STR91X_IAR\r
#include "..\..\Source\portable\IAR\STR91x\portmacro.h"\r
#endif\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* Setup the watchdog to generate the tick interrupts. */\r
+/* Setup the TB to generate the tick interrupts. */\r
static void prvSetupTimerInterrupt( void );\r
\r
-\r
/*-----------------------------------------------------------*/\r
\r
/*\r
/*\r
*/\r
\r
-\r
/* Scheduler includes. */\r
#include "FreeRTOS.h"\r
#include "task.h"\r
\r
-/* Constants required to handle interrupts. */\r
-#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )\r
-#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )\r
-\r
/* Constants required to handle critical sections. */\r
#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )\r
\r
\\r
/* And return - correcting the offset in the LR to obtain the */ \\r
/* correct address. */ \\r
- "SUBS PC, LR, #4 \n\t" \\r
- ); \\r
+ "SUBS PC, LR, #4 \n\t" \\r
+ ); \r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* The preemptive scheduler is defined as "naked" as the full context is\r
-saved on entry as part of the context switch. */\r
void vPortTickISR( void )\r
{\r
/* Increment the RTOS tick count, then look for the highest priority \r
}\r
\r
#endif /* THUMB_INTERWORK */\r
+/*-----------------------------------------------------------*/\r
\r
-/* The code generated by the GCC compiler uses the stack in different ways at\r
-different optimisation levels. The interrupt flags can therefore not always\r
-be saved to the stack. Instead the critical section nesting level is stored\r
-in a variable, which is then saved as part of the stack context. */\r
void vPortEnterCritical( void )\r
{\r
/* Disable interrupts as per portDISABLE_INTERRUPTS(); */\r
portENTER_CRITICAL() has been called. */\r
ulCriticalNesting++;\r
}\r
+/*-----------------------------------------------------------*/\r
\r
void vPortExitCritical( void )\r
{\r
\r
/*-----------------------------------------------------------*/\r
\r
-/* Setup the watchdog to generate the tick interrupts. */\r
+/* Setup the TB to generate the tick interrupts. */\r
static void prvSetupTimerInterrupt( void );\r
\r
/* ulCriticalNesting will get set to zero when the first task starts. It\r