/* Bits within various registers. */\r
#define portIE_BIT ( 0x00000001 )\r
#define portEXL_BIT ( 0x00000002 )\r
-#define portSW0_ENABLE ( 0x00000100 )\r
\r
/* The EXL bit is set to ensure interrupts do not occur while the context of\r
the first task is being restored. */\r
-#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portSW0_ENABLE )\r
+#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )\r
\r
/* Records the interrupt nesting depth. This starts at one as it will be\r
decremented to 0 when the first task starts. */\r