Tcl and doc: update to match new 'arm mcr ...' etc

Make them match the C code.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

diff --git a/NEWS b/NEWS
index b7eb0f0f4ad8c19fab9c149692afe74e171227c5..1af13311b52663fe517dd6bd27b514b17aad07de 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -15,6 +15,8 @@ Target Layer:
                - recognize TrustZone "Secure Monitor" mode
                - "arm regs" command output changed
                - register names use "sp" not "r13"
+               - add top-level "mcr" and "mrc" commands, replacing
+                 various core-specific operations
        ARM11
                - Preliminary ETM and ETB hookup
                - accelerated "flash erase_check"

diff --git a/doc/openocd.texi b/doc/openocd.texi
index ea300925c002370f31a88f3b41ab75db9c615250..7e232117cdb10af4eba4e5975ecb7ae8ef0f0345 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1524,7 +1524,7 @@ proc setc15 @{regs value@} @{
 
     echo [format "set p15 0x%04x, 0x%08x" $regs $value]
 
-    mcr 15 [expr ($regs>>12)&0x7] \
+    arm mcr 15 [expr ($regs>>12)&0x7] \
         [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
         [expr ($regs>>8)&0x7] $value
 @}
@@ -5609,6 +5609,24 @@ with a handful of exceptions.
 ThumbEE disassembly currently has no explicit support.
 @end deffn
 
+@deffn Command {arm mcr} pX op1 CRn CRm op2 value
+Write @var{value} to a coprocessor @var{pX} register
+passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and using the MCR instruction.
+(Parameter sequence matches the ARM instruction, but omits
+an ARM register.)
+@end deffn
+
+@deffn Command {arm mrc} pX coproc op1 CRn CRm op2 
+Read a coprocessor @var{pX} register passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and the MRC instruction.
+Returns the result so it can be manipulated by Jim scripts.
+(Parameter sequence matches the ARM instruction, but omits
+an ARM register.)
+@end deffn
+
 @deffn Command {arm reg}
 Display a table of all banked core registers, fetching the current value from every
 core mode if necessary.

diff --git a/tcl/board/csb732.cfg b/tcl/board/csb732.cfg
index 9022fafcb15ec493b44d6bbc157548cd72beaff4..cad38e2e5b47d774e6a0495da85a591cd9a18fad 100644 (file)
--- a/tcl/board/csb732.cfg
+++ b/tcl/board/csb732.cfg
@@ -19,13 +19,13 @@ proc csb732_init { } {
        # We assume the interpreter latency is enough.
 
        # Allow access to all coprocessors
-       mcr 15 0 15 1 0 0x2001
+       arm mcr 15 0 15 1 0 0x2001
 
        # Disable MMU, caches, write buffer
-       mcr 15 0 1 0 0 0x78
+       arm mcr 15 0 1 0 0 0x78
 
        # Grant manager access to all domains
-       mcr 15 0 3 0 0 0xFFFFFFFF
+       arm mcr 15 0 3 0 0 0xFFFFFFFF
 
        # Set ARM clock to 532 MHz, AHB to 133 MHz
        mww 0x53F80004 0x1000

diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index 2c8bea82998338003fac5e65528e0225179c2b79..db47b8d4dd8a83b5cb26751357959e83de072a3a 100644 (file)
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -182,7 +182,7 @@ proc dm355evm_init {} {
        ########################
 
        # turn on icache - set I bit in cp15 register c1
-       mcr 15 0 0 1 0 0x00051078
+       arm mcr 15 0 0 1 0 0x00051078
 }
 
 # NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.

diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index 12cc79e49822a9fb6e4d267adb59fd3c2d62e710..6371effab095c5f6b4fd106f5e214f428db6e5f0 100644 (file)
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -29,7 +29,7 @@ proc openrd_init { } {
        jtag_reset 0 0
        wait_halt
 
-       mcr 15 0 0 1 0 0x00052078
+       arm mcr 15 0 0 1 0 0x00052078
 
        mww 0xD0001400 0x43000C30 #  DDR SDRAM Configuration Register
        mww 0xD0001404 0x37543000 #  Dunit Control Low Register

diff --git a/tcl/board/sheevaplug.cfg b/tcl/board/sheevaplug.cfg
index 9267eb957c433e042c962745d975cb3b745d144b..b843213bef92764201b4ede872ada597e8b010cc 100644 (file)
--- a/tcl/board/sheevaplug.cfg
+++ b/tcl/board/sheevaplug.cfg
@@ -29,7 +29,7 @@ proc sheevaplug_init { } {
        jtag_reset 0 0
        wait_halt
 
-       mcr 15 0 0 1 0 0x00052078
+       arm mcr 15 0 0 1 0 0x00052078
 
        mww 0xD0001400 0x43000C30 #  DDR SDRAM Configuration Register
        mww 0xD0001404 0x39543000 #  Dunit Control Low Register

diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index 54fe07f080ca80de07d0923b8238cbb386031cd1..965887131e7b5515d4c201a8cccb6272a582b8ef 100644 (file)
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -436,22 +436,22 @@ proc initC100 {} {
     #   */
     #  mov     r0, #0
     #  mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
-    mcr 15 0 7 7 0 0x0
+    arm mcr 15 0 7 7 0 0x0
     #  mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
-    mcr 15 0 8 7 0 0x0
+    arm mcr 15 0 8 7 0 0x0
 
     #  /*
     #   * disable MMU stuff and caches
     #   */
     #  mrc     p15, 0, r0, c1, c0, 0
-    mrc 15 0 1 0 0
+    arm mrc 15 0 1 0 0
     #  bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
     #  bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
     #  orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
     #  orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
     #  orr     r0, r0, #0x00400000     @ set bit 22 (U)
     #  mcr     p15, 0, r0, c1, c0, 0
-    mcr 15 0 1 0 0 0x401002
+    arm mcr 15 0 1 0 0 0x401002
     # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
     # APB init
     #          // Setting APB Bus Wait states to 1, set post write

diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg
index bfcc65255e7f749c1b1ac2294d8da96e925375be..547ec56cc472375a91ce5f06daccba38bb4caedb 100644 (file)
--- a/tcl/target/imx.cfg
+++ b/tcl/target/imx.cfg
@@ -10,7 +10,7 @@ proc setc15 {regs value} {
 
        echo [format "set p15 0x%04x, 0x%08x" $regs $value] 
 
-       mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value 
+       arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value 
 }