--- /dev/null
+[{000214A0-0000-0000-C000-000000000046}]\r
+Prop3=19,11\r
+[InternetShortcut]\r
+IDList=\r
+URL=https://freertos.org/Using-FreeRTOS-on-RISC-V.html\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and t\r
+\r
+ o permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that\r
+ * is common to all currently supported RISC-V chips. There is only one\r
+ * portASM.S file because the same file is built for all RISC-V target chips.\r
+ *\r
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the\r
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V\r
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files\r
+ * as there are multiple RISC-V chip implementations.\r
+ *\r
+ * !!!NOTE!!!\r
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h\r
+ * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the\r
+ * compiler's!) include path. For example, if the chip in use includes a core\r
+ * local interrupter (CLINT) and does not include any chip specific register\r
+ * extensions then add the path below to the assembler's include path:\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions\r
+ *\r
+ */\r
+\r
+/*\r
+ * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy\r
+ * devices, developed and tested using the Vega board RV32M1RM.\r
+ */\r
+\r
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
+#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
+\r
+#define portasmHAS_CLINT 0\r
+\r
+/* Constants to define the additional registers found on the Pulpino RI5KY. */\r
+#define lpstart0 0x7b0\r
+#define lpend0 0x7b1\r
+#define lpcount0 0x7b2\r
+#define lpstart1 0x7b4\r
+#define lpend1 0x7b5\r
+#define lpcount1 0x7b6\r
+\r
+/* Six additional registers to save and restore, as per the #defines above. */\r
+#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */\r
+\r
+/* Save additional registers found on the Pulpino. */\r
+.macro portasmSAVE_ADDITIONAL_REGISTERS\r
+ addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */\r
+ csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */\r
+ csrr t1, lpend0\r
+ csrr t2, lpcount0\r
+ csrr t3, lpstart1\r
+ csrr t4, lpend1\r
+ csrr t5, lpcount1\r
+ sw t0, 1 * portWORD_SIZE( sp )\r
+ sw t1, 2 * portWORD_SIZE( sp )\r
+ sw t2, 3 * portWORD_SIZE( sp )\r
+ sw t3, 4 * portWORD_SIZE( sp )\r
+ sw t4, 5 * portWORD_SIZE( sp )\r
+ sw t5, 6 * portWORD_SIZE( sp )\r
+ .endm\r
+\r
+/* Restore the additional registers found on the Pulpino. */\r
+.macro portasmRESTORE_ADDITIONAL_REGISTERS\r
+ lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */\r
+ lw t1, 2 * portWORD_SIZE( sp )\r
+ lw t2, 3 * portWORD_SIZE( sp )\r
+ lw t3, 4 * portWORD_SIZE( sp )\r
+ lw t4, 5 * portWORD_SIZE( sp )\r
+ lw t5, 6 * portWORD_SIZE( sp )\r
+ csrw lpstart0, t0\r
+ csrw lpend0, t1\r
+ csrw lpcount0, t2\r
+ csrw lpstart1, t3\r
+ csrw lpend1, t4\r
+ csrw lpcount1, t5\r
+ addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */\r
+ .endm\r
+\r
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that\r
+ * is common to all currently supported RISC-V chips. There is only one\r
+ * portASM.S file because the same file is built for all RISC-V target chips.\r
+ *\r
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the\r
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V\r
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files\r
+ * as there are multiple RISC-V chip implementations.\r
+ *\r
+ * !!!NOTE!!!\r
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h\r
+ * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the\r
+ * compiler's!) include path. For example, if the chip in use includes a core\r
+ * local interrupter (CLINT) and does not include any chip specific register\r
+ * extensions then add the path below to the assembler's include path:\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions\r
+ *\r
+ */\r
+\r
+\r
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__\r
+#define __FREERTOS_RISC_V_EXTENSIONS_H__\r
+\r
+#define portasmHAS_CLINT 1\r
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */\r
+\r
+portasmSAVE_ADDITIONAL_REGISTERS MACRO\r
+ /* No additional registers to save, so this macro does nothing. */\r
+ ENDM\r
+\r
+/* Restore the additional registers found on the Pulpino. */\r
+portasmRESTORE_ADDITIONAL_REGISTERS MACRO\r
+ /* No additional registers to restore, so this macro does nothing. */\r
+ ENDM\r
+\r
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */\r
--- /dev/null
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that\r
+ * is common to all currently supported RISC-V chips. There is only one\r
+ * portASM.S file because the same file is built for all RISC-V target chips.\r
+ *\r
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the\r
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V\r
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files\r
+ * as there are multiple RISC-V chip implementations.\r
+ *\r
+ * !!!NOTE!!!\r
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h\r
+ * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the\r
+ * compiler's!) include path. For example, if the chip in use includes a core\r
+ * local interrupter (CLINT) and does not include any chip specific register\r
+ * extensions then add the path below to the assembler's include path:\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions\r
+ *\r
+ */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the RISC-V RV32 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "portmacro.h"\r
+\r
+#ifndef configCLINT_BASE_ADDRESS\r
+ #warning configCLINT_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a Core Local Interrupter (CLINT) then set configCLINT_BASE_ADDRESS to the CLINT base address. Otherwise set configCLINT_BASE_ADDRESS to 0.\r
+#endif\r
+\r
+/* Let the user override the pre-loading of the initial LR with the address of\r
+prvTaskExitError() in case it messes up unwinding of the stack in the\r
+debugger. */\r
+#ifdef configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+#else\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+#endif\r
+\r
+/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS\r
+to use a statically allocated array as the interrupt stack. Alternative leave\r
+configISR_STACK_SIZE_WORDS undefined and update the linker script so that a\r
+linker variable names __freertos_irq_stack_top has the same value as the top\r
+of the stack used by main. Using the linker script method will repurpose the\r
+stack that was used by main before the scheduler was started for use as the\r
+interrupt stack after the scheduler has started. */\r
+#ifdef configISR_STACK_SIZE_WORDS\r
+ static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };\r
+ StackType_t xISRStackTop = ( StackType_t ) 0;\r
+#else\r
+ extern const uint32_t __freertos_irq_stack_top[];\r
+ const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;\r
+#endif\r
+\r
+/*\r
+ * Setup the timer to generate the tick interrupts. The implementation in this\r
+ * file is weak to allow application writers to change the timer used to\r
+ * generate the tick interrupt.\r
+ */\r
+void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Used to program the machine timer compare register. */\r
+uint64_t ullNextTime = 0ULL;\r
+const uint64_t *pullNextTime = &ullNextTime;\r
+const size_t uxTimerIncrementsForOneTick = ( size_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); /* Assumes increment won't go over 32-bits. */\r
+volatile uint64_t * const pullMachineTimerCompareRegister = ( uint64_t * ) ( configCLINT_BASE_ADDRESS + 0x4000 );\r
+\r
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task\r
+stack checking. A problem in the ISR stack will trigger an assert, not call the\r
+stack overflow hook function (because the stack overflow hook is specific to a\r
+task stack, not the ISR stack). */\r
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )\r
+ #warning This path not tested, or even compiled yet.\r
+ /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for\r
+ the task stacks, and so will legitimately appear in many positions within\r
+ the ISR stack. */\r
+ #define portISR_STACK_FILL_BYTE 0xee\r
+\r
+ static const uint8_t ucExpectedStackBytes[] = {\r
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \\r
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \\r
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \\r
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \\r
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \\r
+\r
+ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )\r
+#else\r
+ /* Define the function away. */\r
+ #define portCHECK_ISR_STACK()\r
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configCLINT_BASE_ADDRESS != 0 )\r
+\r
+ void vPortSetupTimerInterrupt( void )\r
+ {\r
+ uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;\r
+ volatile uint32_t * const pulTimeHigh = ( uint32_t * ) ( configCLINT_BASE_ADDRESS + 0xBFFC );\r
+ volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );\r
+\r
+ do\r
+ {\r
+ ulCurrentTimeHigh = *pulTimeHigh;\r
+ ulCurrentTimeLow = *pulTimeLow;\r
+ } while( ulCurrentTimeHigh != *pulTimeHigh );\r
+\r
+ ullNextTime = ( uint64_t ) ulCurrentTimeHigh;\r
+ ullNextTime <<= 32ULL;\r
+ ullNextTime |= ( uint64_t ) ulCurrentTimeLow;\r
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;\r
+ *pullMachineTimerCompareRegister = ullNextTime;\r
+\r
+ /* Prepare the time to use after the next tick interrupt. */\r
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;\r
+ }\r
+\r
+#endif /* ( configCLINT_BASE_ADDRESS != 0 ) */\r
+/*-----------------------------------------------------------*/\r
+\r
+BaseType_t xPortStartScheduler( void )\r
+{\r
+extern void xPortStartFirstTask( void );\r
+#warning Replicate this change in the GCC version.\r
+ #ifdef configISR_STACK_SIZE_WORDS\r
+ xISRStackTop = ( ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS - 1 ] ) & ~portBYTE_ALIGNMENT_MASK );\r
+ #endif\r
+\r
+ #if( configASSERT_DEFINED == 1 )\r
+ {\r
+ volatile uint32_t mtvec = 0;\r
+\r
+ /* Check the least significant two bits of mtvec are 00 - indicating\r
+ single vector mode. */\r
+ __asm volatile( "csrr %0, 0x305" : "=r"( mtvec ) ); /* 0x305 is mtvec. */\r
+ configASSERT( ( mtvec & 0x03UL ) == 0 );\r
+\r
+ /* Check alignment of the interrupt stack - which is the same as the\r
+ stack that was being used by main() prior to the scheduler being\r
+ started. */\r
+ configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );\r
+ }\r
+ #endif /* configASSERT_DEFINED */\r
+\r
+ /* If there is a CLINT then it is ok to use the default implementation\r
+ in this file, otherwise vPortSetupTimerInterrupt() must be implemented to\r
+ configure whichever clock is to be used to generate the tick interrupt. */\r
+ vPortSetupTimerInterrupt();\r
+\r
+ #if( configCLINT_BASE_ADDRESS != 0 )\r
+ {\r
+ /* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11\r
+ for external interrupt. _RB_ What happens here when mtime is not present as\r
+ with pulpino? */\r
+ __asm volatile( "csrs 0x304, %0" :: "r"(0x880) ); /* 0x304 is mie. */\r
+ }\r
+ #else\r
+ {\r
+ /* Enable external interrupts. */\r
+ __asm volatile( "csrs 0x304, %0" :: "r"(0x800) ); /* 304 is mie. */\r
+ }\r
+ #endif /* configCLINT_BASE_ADDRESS */\r
+\r
+ xPortStartFirstTask();\r
+\r
+ /* Should not get here as after calling xPortStartFirstTask() only tasks\r
+ should be executing. */\r
+ return pdFAIL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* Not implemented. */\r
+ for( ;; );\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + The code that is common to all RISC-V chips is implemented in\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one\r
+ * portASM.S file because the same file is used no matter which RISC-V chip is\r
+ * in use.\r
+ *\r
+ * + The code that tailors the kernel's RISC-V port to a specific RISC-V\r
+ * chip is implemented in freertos_risc_v_chip_specific_extensions.h. There\r
+ * is one freertos_risc_v_chip_specific_extensions.h that can be used with any\r
+ * RISC-V chip that both includes a standard CLINT and does not add to the\r
+ * base set of RISC-V registers. There are additional\r
+ * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations\r
+ * that do not include a standard CLINT or do add to the base set of RISC-V\r
+ * registers.\r
+ *\r
+ * CARE MUST BE TAKEN TO INCLDUE THE CORRECT\r
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP\r
+ * IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h\r
+ * header file ensure the path to the correct header file is in the assembler's\r
+ * include path.\r
+ *\r
+ * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips\r
+ * that include a standard CLINT and do not add to the base set of RISC-V\r
+ * registers.\r
+ *\r
+ */\r
+#if __riscv_xlen == 64\r
+ #define portWORD_SIZE 8\r
+ #define store_x sd\r
+ #define load_x ld\r
+#elif __riscv_xlen == 32\r
+ #define store_x sw\r
+ #define load_x lw\r
+ #define portWORD_SIZE 4\r
+#else\r
+ #error Assembler did not define __riscv_xlen\r
+#endif\r
+\r
+#include "freertos_risc_v_chip_specific_extensions.h"\r
+\r
+/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line\r
+definitions. */\r
+#ifndef portasmHAS_CLINT\r
+ #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).\r
+#endif\r
+\r
+#ifndef portasmHANDLE_INTERRUPT\r
+ #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.\r
+#endif\r
+\r
+/* CSR definitions. */\r
+#define CSR_MSTATUS 0x300\r
+#define CSR_MTVEC 0x305\r
+#define CSR_MEPC 0x341\r
+#define CSR_MCAUSE 0x342\r
+\r
+\r
+/* Only the standard core registers are stored by default. Any additional\r
+registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and\r
+portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip\r
+specific version of freertos_risc_v_chip_specific_extensions.h. See the notes\r
+at the top of this file. */\r
+#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )\r
+\r
+ PUBLIC xPortStartFirstTask\r
+ PUBLIC freertos_risc_v_trap_handler\r
+ PUBLIC pxPortInitialiseStack\r
+ EXTERN pxCurrentTCB\r
+ EXTERN ulPortTrapHandler\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN Timer_IRQHandler\r
+ EXTERN pullMachineTimerCompareRegister\r
+ EXTERN pullNextTime\r
+ EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */\r
+ EXTERN xISRStackTop\r
+ EXTERN xTaskIncrementTick\r
+ EXTERN portasmHANDLE_INTERRUPT\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ SECTION `.text`:CODE:NOROOT(2)\r
+ CODE\r
+\r
+freertos_risc_v_trap_handler:\r
+ addi sp, sp, -portCONTEXT_SIZE\r
+ store_x x1, 1 * portWORD_SIZE( sp )\r
+ store_x x5, 2 * portWORD_SIZE( sp )\r
+ store_x x6, 3 * portWORD_SIZE( sp )\r
+ store_x x7, 4 * portWORD_SIZE( sp )\r
+ store_x x8, 5 * portWORD_SIZE( sp )\r
+ store_x x9, 6 * portWORD_SIZE( sp )\r
+ store_x x10, 7 * portWORD_SIZE( sp )\r
+ store_x x11, 8 * portWORD_SIZE( sp )\r
+ store_x x12, 9 * portWORD_SIZE( sp )\r
+ store_x x13, 10 * portWORD_SIZE( sp )\r
+ store_x x14, 11 * portWORD_SIZE( sp )\r
+ store_x x15, 12 * portWORD_SIZE( sp )\r
+ store_x x16, 13 * portWORD_SIZE( sp )\r
+ store_x x17, 14 * portWORD_SIZE( sp )\r
+ store_x x18, 15 * portWORD_SIZE( sp )\r
+ store_x x19, 16 * portWORD_SIZE( sp )\r
+ store_x x20, 17 * portWORD_SIZE( sp )\r
+ store_x x21, 18 * portWORD_SIZE( sp )\r
+ store_x x22, 19 * portWORD_SIZE( sp )\r
+ store_x x23, 20 * portWORD_SIZE( sp )\r
+ store_x x24, 21 * portWORD_SIZE( sp )\r
+ store_x x25, 22 * portWORD_SIZE( sp )\r
+ store_x x26, 23 * portWORD_SIZE( sp )\r
+ store_x x27, 24 * portWORD_SIZE( sp )\r
+ store_x x28, 25 * portWORD_SIZE( sp )\r
+ store_x x29, 26 * portWORD_SIZE( sp )\r
+ store_x x30, 27 * portWORD_SIZE( sp )\r
+ store_x x31, 28 * portWORD_SIZE( sp )\r
+\r
+ csrr t0, CSR_MSTATUS /* Required for MPIE bit. */\r
+ store_x t0, 29 * portWORD_SIZE( sp )\r
+\r
+ portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */\r
+\r
+ load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */\r
+ store_x sp, 0( t0 ) /* Write sp to first TCB member. */\r
+\r
+ csrr a0, CSR_MCAUSE\r
+ csrr a1, CSR_MEPC\r
+\r
+test_if_asynchronous:\r
+ srli a2, a0, __riscv_xlen - 1 /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */\r
+ beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */\r
+ store_x a1, 0( sp ) /* Asynch so save unmodified exception return address. */\r
+\r
+handle_asynchronous:\r
+\r
+#if( portasmHAS_CLINT != 0 )\r
+\r
+ test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */\r
+\r
+ addi t0, x0, 1\r
+\r
+ slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */\r
+ addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */\r
+ bne a0, t1, test_if_external_interrupt\r
+\r
+ load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */\r
+ load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */\r
+\r
+ #if( __riscv_xlen == 32 )\r
+\r
+ /* Update the 64-bit mtimer compare match value in two 32-bit writes. */\r
+ lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */\r
+ lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */\r
+ sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */\r
+ sw t3, 4(t0) /* Store high word of ullNextTime into compare register. */\r
+ lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
+ add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */\r
+ sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */\r
+ add t6, t3, t5 /* Add overflow to high word of ullNextTime. */\r
+ sw t4, 0(t1) /* Store new low word of ullNextTime. */\r
+ sw t6, 4(t1) /* Store new high word of ullNextTime. */\r
+\r
+ #endif /* __riscv_xlen == 32 */\r
+\r
+ #if( __riscv_xlen == 64 )\r
+\r
+ /* Update the 64-bit mtimer compare match value. */\r
+ ld t2, 0(t1) /* Load ullNextTime into t2. */\r
+ sd t2, 0(t0) /* Store ullNextTime into compare register. */\r
+ ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
+ add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */\r
+ sd t4, 0(t1) /* Store ullNextTime. */\r
+\r
+ #endif /* __riscv_xlen == 64 */\r
+\r
+ load_x sp, xISRStackTop /* Switch to ISR stack before function call. */\r
+ jal xTaskIncrementTick\r
+ beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */\r
+ jal vTaskSwitchContext\r
+ j processed_source\r
+\r
+ test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */\r
+ addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */\r
+ bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */\r
+\r
+#endif /* portasmHAS_CLINT */\r
+\r
+ load_x sp, xISRStackTop /* Switch to ISR stack before function call. */\r
+ jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */\r
+ j processed_source\r
+\r
+handle_synchronous:\r
+ addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */\r
+ store_x a1, 0( sp ) /* Save updated exception return address. */\r
+\r
+test_if_environment_call:\r
+ li t0, 11 /* 11 == environment call. */\r
+ bne a0, t0, is_exception /* Not an M environment call, so some other exception. */\r
+ load_x sp, xISRStackTop /* Switch to ISR stack before function call. */\r
+ jal vTaskSwitchContext\r
+ j processed_source\r
+\r
+is_exception:\r
+ ebreak\r
+ j is_exception\r
+\r
+as_yet_unhandled:\r
+ ebreak\r
+ j as_yet_unhandled\r
+\r
+processed_source:\r
+ load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */\r
+ load_x sp, 0( t1 ) /* Read sp from first TCB member. */\r
+\r
+ /* Load mret with the address of the next instruction in the task to run next. */\r
+ load_x t0, 0( sp )\r
+ csrw CSR_MEPC, t0\r
+\r
+ portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
+\r
+ /* Load mstatus with the interrupt enable bits used by the task. */\r
+ load_x t0, 29 * portWORD_SIZE( sp )\r
+ csrw CSR_MSTATUS, t0 /* Required for MPIE bit. */\r
+\r
+ load_x x1, 1 * portWORD_SIZE( sp )\r
+ load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */\r
+ load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */\r
+ load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */\r
+ load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */\r
+ load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */\r
+ load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */\r
+ load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */\r
+ load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */\r
+ load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */\r
+ load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */\r
+ load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */\r
+ load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */\r
+ load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */\r
+ load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */\r
+ load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */\r
+ load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */\r
+ load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */\r
+ load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */\r
+ load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */\r
+ load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */\r
+ load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */\r
+ load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */\r
+ load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */\r
+ load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */\r
+ load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */\r
+ load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */\r
+ load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */\r
+ addi sp, sp, portCONTEXT_SIZE\r
+\r
+ mret\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xPortStartFirstTask:\r
+\r
+#if( portasmHAS_CLINT != 0 )\r
+ /* If there is a clint then interrupts can branch directly to the FreeRTOS\r
+ trap handler. Otherwise the interrupt controller will need to be configured\r
+ outside of this file. */\r
+ la t0, freertos_risc_v_trap_handler\r
+ csrw CSR_MTVEC, t0\r
+#endif /* portasmHAS_CLILNT */\r
+\r
+ load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */\r
+ load_x sp, 0( sp ) /* Read sp from first TCB member. */\r
+\r
+ load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */\r
+\r
+ portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
+\r
+ load_x t0, 29 * portWORD_SIZE( sp ) /* mstatus */\r
+ csrrw x0, CSR_MSTATUS, t0 /* Interrupts enabled from here! */\r
+\r
+ load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */\r
+ load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */\r
+ load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */\r
+ load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */\r
+ load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */\r
+ load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */\r
+ load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */\r
+ load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */\r
+ load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */\r
+ load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */\r
+ load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */\r
+ load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */\r
+ load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */\r
+ load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */\r
+ load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */\r
+ load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */\r
+ load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */\r
+ load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */\r
+ load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */\r
+ load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */\r
+ load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */\r
+ load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */\r
+ load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */\r
+ load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */\r
+ load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */\r
+ load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */\r
+ load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */\r
+ addi sp, sp, portCONTEXT_SIZE\r
+ ret\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Unlike other ports pxPortInitialiseStack() is written in assembly code as it\r
+ * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype\r
+ * for the function is as per the other ports:\r
+ * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );\r
+ *\r
+ * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in\r
+ * a1, and pvParameters in a2. The new top of stack is passed out in a0.\r
+ *\r
+ * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers\r
+ * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).\r
+ *\r
+ * Register ABI Name Description Saver\r
+ * x0 zero Hard-wired zero -\r
+ * x1 ra Return address Caller\r
+ * x2 sp Stack pointer Callee\r
+ * x3 gp Global pointer -\r
+ * x4 tp Thread pointer -\r
+ * x5-7 t0-2 Temporaries Caller\r
+ * x8 s0/fp Saved register/Frame pointer Callee\r
+ * x9 s1 Saved register Callee\r
+ * x10-11 a0-1 Function Arguments/return values Caller\r
+ * x12-17 a2-7 Function arguments Caller\r
+ * x18-27 s2-11 Saved registers Callee\r
+ * x28-31 t3-6 Temporaries Caller\r
+ *\r
+ * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,\r
+ * where the global and thread pointers are currently assumed to be constant so\r
+ * are not saved:\r
+ *\r
+ * mstatus\r
+ * x31\r
+ * x30\r
+ * x29\r
+ * x28\r
+ * x27\r
+ * x26\r
+ * x25\r
+ * x24\r
+ * x23\r
+ * x22\r
+ * x21\r
+ * x20\r
+ * x19\r
+ * x18\r
+ * x17\r
+ * x16\r
+ * x15\r
+ * x14\r
+ * x13\r
+ * x12\r
+ * x11\r
+ * pvParameters\r
+ * x9\r
+ * x8\r
+ * x7\r
+ * x6\r
+ * x5\r
+ * portTASK_RETURN_ADDRESS\r
+ * [chip specific registers go here]\r
+ * pxCode\r
+ */\r
+pxPortInitialiseStack:\r
+\r
+ csrr t0, CSR_MSTATUS /* Obtain current mstatus value. */\r
+ addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */\r
+ slli t1, t1, 4\r
+ or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */\r
+\r
+ addi a0, a0, -portWORD_SIZE\r
+ store_x t0, 0(a0) /* mstatus onto the stack. */\r
+ addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */\r
+ store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */\r
+ addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */\r
+ store_x x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */\r
+ addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */\r
+chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */\r
+ beq t0, x0, no_more_regs /* No more chip specific registers to save. */\r
+ addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */\r
+ store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */\r
+ addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */\r
+ j chip_specific_stack_frame /* Until no more chip specific registers. */\r
+no_more_regs:\r
+ addi a0, a0, -portWORD_SIZE\r
+ store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */\r
+ ret\r
+\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.1\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#include "intrinsics.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#if __riscv_xlen == 64\r
+ #define portSTACK_TYPE uint64_t\r
+ #define portBASE_TYPE int64_t\r
+ #define portUBASE_TYPE uint64_t\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL\r
+ #define portPOINTER_SIZE_TYPE uint64_t\r
+#elif __riscv_xlen == 32\r
+ #define portSTACK_TYPE uint32_t\r
+ #define portBASE_TYPE int32_t\r
+ #define portUBASE_TYPE uint32_t\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+#else\r
+ #error Assembler did not define __riscv_xlen\r
+#endif\r
+\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef portBASE_TYPE BaseType_t;\r
+typedef portUBASE_TYPE UBaseType_t;\r
+typedef portUBASE_TYPE TickType_t;\r
+\r
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+not need to be guarded with a critical section. */\r
+#define portTICK_TYPE_IS_ATOMIC 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#ifdef __riscv64\r
+ #error This is the RV32 port that has not yet been adapted for 64.\r
+ #define portBYTE_ALIGNMENT 16\r
+#else\r
+ #define portBYTE_ALIGNMENT 8\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/* Scheduler utilities. */\r
+extern void vTaskSwitchContext( void );\r
+#define portYIELD() __asm volatile( "ecall" );\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/* Critical section management. */\r
+#define portCRITICAL_NESTING_IN_TCB 1\r
+extern void vTaskEnterCritical( void );\r
+extern void vTaskExitCritical( void );\r
+\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() 0\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue\r
+#define portDISABLE_INTERRUPTS() __disable_interrupt()\r
+#define portENABLE_INTERRUPTS() __enable_interrupt()\r
+#define portENTER_CRITICAL() vTaskEnterCritical()\r
+#define portEXIT_CRITICAL() vTaskExitCritical()\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Architecture specific optimisations. */\r
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )\r
+\r
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated.\r
+\r
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. These are\r
+not necessary for to use this port. They are defined so the common demo files\r
+(which build with all the ports) will build. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#define portNOP() __asm volatile ( " nop " )\r
+\r
+#define portINLINE __inline\r
+\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline))\r
+#endif\r
+\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+\r
+\r
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in\r
+the source code because to do so would cause other compilers to generate\r
+warnings. */\r
+#pragma diag_suppress=Pa082\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is\r
+ * common across all currently supported RISC-V chips (implementations of the\r
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:\r
+ *\r
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that\r
+ * is common to all currently supported RISC-V chips. There is only one\r
+ * portASM.S file because the same file is built for all RISC-V target chips.\r
+ *\r
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the\r
+ * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V\r
+ * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files\r
+ * as there are multiple RISC-V chip implementations.\r
+ *\r
+ * !!!NOTE!!!\r
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h\r
+ * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the\r
+ * compiler's!) include path. For example, if the chip in use includes a core\r
+ * local interrupter (CLINT) and does not include any chip specific register\r
+ * extensions then add the path below to the assembler's include path:\r
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions\r
+ *\r
+ */\r
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