{ 4<<10, 4<<10, 4 }
};
+/* Addressess */
+#define FLEXRAM 0x14000000
+#define FTFx_FSTAT 0x40020000
+#define FTFx_FCNFG 0x40020001
+#define FTFx_FCCOB3 0x40020004
+#define FTFx_FPROT3 0x40020010
+#define SIM_SDID 0x40048024
+#define SIM_FCFG1 0x4004804c
+#define SIM_FCFG2 0x40048050
+
+/* Commands */
+#define FTFx_CMD_BLOCKSTAT 0x00
+#define FTFx_CMD_SECTSTAT 0x01
+#define FTFx_CMD_LWORDPROG 0x06
+#define FTFx_CMD_SECTERASE 0x09
+#define FTFx_CMD_SECTWRITE 0x0b
+#define FTFx_CMD_SETFLEXRAM 0x81
+
struct kinetis_flash_bank {
unsigned granularity;
unsigned bank_ordinal;
uint32_t fprot, psec;
int i, b;
- /* read protection register FTFx_FPROT */
- result = target_read_memory(bank->target, 0x40020010, 1, 4, buffer);
+ /* read protection register */
+ result = target_read_memory(bank->target, FTFx_FPROT3, 1, 4, buffer);
if (result != ERROR_OK)
return result;
/* wait for done */
for (i = 0; i < 50; i++) {
result =
- target_read_memory(bank->target, 0x40020000, 1, 1, buffer);
+ target_read_memory(bank->target, FTFx_FSTAT, 1, 1, buffer);
if (result != ERROR_OK)
return result;
/* reset error flags */
buffer[0] = 0x30;
result =
- target_write_memory(bank->target, 0x40020000, 1, 1, buffer);
+ target_write_memory(bank->target, FTFx_FSTAT, 1, 1, buffer);
if (result != ERROR_OK)
return result;
}
target_buffer_set_u32(bank->target, buffer + 4, w1);
target_buffer_set_u32(bank->target, buffer + 8, w2);
- result = target_write_memory(bank->target, 0x40020004, 4, 3, buffer);
+ result = target_write_memory(bank->target, FTFx_FCCOB3, 4, 3, buffer);
if (result != ERROR_OK)
return result;
/* start command */
buffer[0] = 0x80;
- result = target_write_memory(bank->target, 0x40020000, 1, 1, buffer);
+ result = target_write_memory(bank->target, FTFx_FSTAT, 1, 1, buffer);
if (result != ERROR_OK)
return result;
/* wait for done */
for (i = 0; i < 50; i++) {
result =
- target_read_memory(bank->target, 0x40020000, 1, 1, ftfx_fstat);
+ target_read_memory(bank->target, FTFx_FSTAT, 1, 1, ftfx_fstat);
if (result != ERROR_OK)
return result;
for (i = first; i <= last; i++) {
uint8_t ftfx_fstat;
/* set command and sector address */
- w0 = (0x09 << 24) | (bank->base + bank->sectors[i].offset);
+ w0 = (FTFx_CMD_SECTERASE << 24) | (bank->base + bank->sectors[i].offset);
result = kinetis_ftfx_command(bank, w0, w1, w2, &ftfx_fstat);
LOG_DEBUG("flash write into FlexNVM @%08X", offset);
/* make flex ram available */
- w0 = (0x81 << 24) | 0x00ff0000;
+ w0 = (FTFx_CMD_SETFLEXRAM << 24) | 0x00ff0000;
result = kinetis_ftfx_command(bank, w0, w1, w2, &ftfx_fstat);
return ERROR_FLASH_OPERATION_FAILED;
/* check if ram ready */
- result = target_read_memory(bank->target, 0x40020001, 1, 1, buf);
+ result = target_read_memory(bank->target, FTFx_FCNFG, 1, 1, buf);
if (result != ERROR_OK)
return result;
offset + i, (count - i));
/* write data to flexram as whole-words */
- result = target_write_memory(bank->target, 0x14000000, 4, wc,
+ result = target_write_memory(bank->target, FLEXRAM, 4, wc,
buffer + i);
if (result != ERROR_OK) {
/* write the residual words to the flexram */
if (residual_wc) {
result = target_write_memory(bank->target,
- 0x14000000+4*wc,
+ FLEXRAM+4*wc,
4, residual_wc,
residual_buffer);
}
/* execute section-write command */
- w0 = (0x0b << 24) | (bank->base + offset + i);
+ w0 = (FTFx_CMD_SECTWRITE << 24) | (bank->base + offset + i);
w1 = section_count << 16;
result = kinetis_ftfx_command(bank, w0, w1, w2, &ftfx_fstat);
LOG_DEBUG("write longword @ %08X", offset + i);
- w0 = (0x06 << 24) | (bank->base + offset + i);
+ w0 = (FTFx_CMD_LWORDPROG << 24) | (bank->base + offset + i);
if (count - i < 4) {
uint32_t padding = 0xffffffff;
memcpy(&padding, buffer + i, count - i);
first_nvm_bank = 0, reassign = 0;
struct kinetis_flash_bank *kinfo = bank->driver_priv;
- result = target_read_memory(bank->target, 0x40048024, 1, 4, buf);
+ result = target_read_memory(bank->target, SIM_SDID, 1, 4, buf);
if (result != ERROR_OK)
return result;
kinfo->sim_sdid = target_buffer_get_u32(bank->target, buf);
granularity = (kinfo->sim_sdid >> 7) & 0x03;
- result = target_read_memory(bank->target, 0x4004804c, 1, 4, buf);
+
+ result = target_read_memory(bank->target, SIM_FCFG1, 1, 4, buf);
if (result != ERROR_OK)
return result;
kinfo->sim_fcfg1 = target_buffer_get_u32(bank->target, buf);
- result = target_read_memory(bank->target, 0x40048050, 1, 4, buf);
+
+ result = target_read_memory(bank->target, SIM_FCFG2, 1, 4, buf);
if (result != ERROR_OK)
return result;
kinfo->sim_fcfg2 = target_buffer_get_u32(bank->target, buf);
} else if (bank->size != ee_size) {
LOG_WARNING("FlexRAM size mismatch");
reassign = 1;
- } else if (bank->base != 0x14000000) {
+ } else if (bank->base != FLEXRAM) {
LOG_WARNING("FlexRAM address mismatch");
reassign = 1;
} else if (kinfo->sector_size !=
uint8_t ftfx_fstat;
/* check if whole bank is blank */
- w0 = (0x00 << 24) | bank->base;
+ w0 = (FTFx_CMD_BLOCKSTAT << 24) | bank->base;
w1 = 0; /* "normal margin" */
result = kinetis_ftfx_command(bank, w0, w1, w2, &ftfx_fstat);
/* the whole bank is not erased, check sector-by-sector */
int i;
for (i = 0; i < bank->num_sectors; i++) {
- w0 = (0x01 << 24) | (bank->base + bank->sectors[i].offset);
+ w0 = (FTFx_CMD_SECTSTAT << 24) | (bank->base + bank->sectors[i].offset);
w1 = (0x100 << 16) | 0; /* normal margin */
result = kinetis_ftfx_command(bank, w0, w1, w2, &ftfx_fstat);