--- /dev/null
+/*\r
+ FreeRTOS V3.2.3 - Copyright (C) 2003-2005 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/** \r
+ * FreeRTOSConfig.h configures FreeRTOS for GCC/HCS12 version of FreeRTOS Demo\r
+ *\r
+ * Modified by Jefferson L Smith, Robotronics Inc.\r
+ */\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* This port requires the compiler to generate code for the BANKED memory\r
+model. */\r
+#define BANKED_MODEL\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 1\r
+#define configUSE_TICK_HOOK 0\r
+#define configTICK_RATE_HZ ( ( portTickType ) 977 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 300/*128*/ )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10752 ) )\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 1\r
+#define configIDLE_SHOULD_YIELD 1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* This parameter is normally affects the clock frequency. In this port, at the moment\r
+it might just be used for reference. */\r
+\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 24000000 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+# Demo for GCC/HCS12 port of FreeRTOS\r
+# Author Jefferson Smith\r
+#\r
+SRCDIR=../..\r
+RTOS_BASEDIR=$(SRCDIR)/Source\r
+\r
+# what board to compile for\r
+TARGET_BOARD ?= dragon12-rom\r
+CPU=m68hcs12\r
+\r
+DEVC_PREFIX=m6811-elf-\r
+CC=$(DEVC_PREFIX)gcc\r
+AS=$(DEVC_PREFIX)as\r
+AR=$(DEVC_PREFIX)ar\r
+OBJCOPY=$(DEVC_PREFIX)objcopy\r
+OBJDUMP=$(DEVC_PREFIX)objdump\r
+\r
+CPPFLAGS+=-I. -I./asm-$(CPU)/arch-dragon12 -I../Common/include \\r
+ -I$(RTOS_BASEDIR)/include -DGCC_HCS12 -DM6812_DEF_SCI=1 -DPORT_LED=M6811_PORTB\r
+\r
+CFLAGS+=-$(CPU) -mshort -mlong-calls -g -Os -Wall -Wmissing-prototypes \\r
+ -Wno-char-subscripts -fomit-frame-pointer -msoft-reg-count=0 -mauto-incdec\r
+#-Os -fomit-frame-pointer\r
+\r
+LDFLAGS+=-$(CPU) -mshort -mlong-calls -Wl,-T,ldscript-rtos.x\r
+\r
+OBJCOPY_FLAGS=--srec-len=0x20 --change-addresses 0xffff0000\r
+\r
+CSRCS=main.c startup.c vectors.c serial.c sci.c ParTest.c gelfunc.c \\r
+ ../Common/Minimal/flash.c \\r
+ ../Common/Minimal/dynamic.c \\r
+ ../Common/Minimal/BlockQ.c \\r
+ ../Common/Minimal/PollQ.c \\r
+ ../Common/Minimal/comtest.c \\r
+ ../Common/Minimal/integer.c \\r
+ ../Common/Minimal/death.c \\r
+\r
+RTOS_OBJS = $(RTOS_BASEDIR)/portable/GCC/HCS12/port.c \\r
+ $(RTOS_BASEDIR)/portable/MemMang/heap_2.c \\r
+ $(RTOS_BASEDIR)/list.c \\r
+ $(RTOS_BASEDIR)/tasks.c \\r
+ $(RTOS_BASEDIR)/queue.c\r
+\r
+OBJS=$(CSRCS:.c=.o) $(RTOS_OBJS:.c=.o)\r
+\r
+#\r
+# *.elf for the simulator and gdb\r
+# *.s19 is original S Records from ld\r
+# *.s2 is S2 Records (from SRecCvt.exe)\r
+#\r
+all:: main.elf main.lst main.s19\r
+\r
+main.elf: $(OBJS)\r
+ $(CC) $(LDFLAGS) -o $@ $^ -lc -lbcc -lc\r
+\r
+%.lst: %.elf\r
+ $(OBJDUMP) -htS $< >$@\r
+\r
+%.s19: %.elf\r
+ $(OBJCOPY) --output-target=srec $(OBJCOPY_FLAGS) $< $*.s19\r
+\r
+clean::\r
+ $(RM) $(OBJS) *.elf *.s19\r
+\r
--- /dev/null
+/** ###################################################################\r
+** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.\r
+** Filename : PE_Error.H\r
+** Project : RTOSDemo\r
+** Processor : MC9S12DP256BCPV\r
+** Beantype : PE_Error\r
+** Version : Driver 01.00\r
+** Compiler : Metrowerks HC12 C Compiler\r
+** Date/Time : 13/06/2005, 20:14\r
+** Abstract :\r
+** This bean "PE_Error" contains internal definitions\r
+** of the error constants.\r
+** Settings :\r
+** Contents :\r
+** No public methods\r
+**\r
+** (c) Copyright UNIS, spol. s r.o. 1997-2002\r
+** UNIS, spol. s r.o.\r
+** Jundrovska 33\r
+** 624 00 Brno\r
+** Czech Republic\r
+** http : www.processorexpert.com\r
+** mail : info@processorexpert.com\r
+** ###################################################################*/\r
+\r
+#ifndef __PE_Error_H\r
+#define __PE_Error_H\r
+\r
+#define ERR_OK 0 /* OK */\r
+#define ERR_SPEED 1 /* This device does not work in the active speed mode. */\r
+#define ERR_RANGE 2 /* Parameter out of range. */\r
+#define ERR_VALUE 3 /* Parameter of incorrect value. */\r
+#define ERR_OVERFLOW 4 /* Timer overflow. */\r
+#define ERR_MATH 5 /* Overflow during evaluation. */\r
+#define ERR_ENABLED 6 /* Device is enabled. */\r
+#define ERR_DISABLED 7 /* Device is disabled. */\r
+#define ERR_BUSY 8 /* Device is busy. */\r
+#define ERR_NOTAVAIL 9 /* Requested value or method not available. */\r
+#define ERR_RXEMPTY 10 /* No data in receiver. */\r
+#define ERR_TXFULL 11 /* Transmitter is full. */\r
+#define ERR_BUSOFF 12 /* Bus not available. */\r
+#define ERR_OVERRUN 13 /* Overrun error is detected. */\r
+#define ERR_FRAMING 14 /* Framing error is detected. */\r
+#define ERR_PARITY 15 /* Parity error is detected. */\r
+#define ERR_NOISE 16 /* Noise error is detected. */\r
+#define ERR_IDLE 17 /* Idle error is detectes. */\r
+#define ERR_FAULT 18 /* Fault error is detected. */\r
+#define ERR_BREAK 19 /* Break char is received during communication. */\r
+#define ERR_CRC 20 /* CRC error is detected. */\r
+#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */\r
+#define ERR_PROTECT 22 /* Protection error is detected. */\r
+\r
+#endif //__PE_Error_H\r
--- /dev/null
+/*\r
+ FreeRTOS V3.2.3 - Copyright (C) 2003-2005 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+/** \r
+ * ParTest.c controls bits (LEDs) for GCC/HCS12 version of FreeRTOS Demo\r
+ *\r
+ * Modified from CodeWarrior/HCS12 by Jefferson L Smith, Robotronics Inc.\r
+ */\r
+\r
+#include <sys/ports.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "portable.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+\r
+#define LEDIO PORTIO_8(PORT_LED)\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ /* This function is required as it is called from the standard demo \r
+ application files. It manipulates a bit to control one LED. */\r
+ portENTER_CRITICAL();\r
+\r
+ if (xValue) { /* Is it one to be written? */\r
+ LEDIO |= (1<<uxLED); /* Set appropriate bit on port */\r
+ }\r
+ else { /* Is it zero to be written? */\r
+ LEDIO &= ~(1<<uxLED); /* Clear appropriate bit on port */\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* This function is required as it is called from the standard demo\r
+ application files. It manipulates a bit to control one LED. */\r
+ portENTER_CRITICAL();\r
+ LEDIO ^= (1<<uxLED); /* Invert appropriate bit on port */\r
+ portEXIT_CRITICAL();\r
+}\r
+\r
--- /dev/null
+##-------------------------------------------------------------------\r
+## Readme.txt\r
+##\r
+## FreeRTOS Port Example for GCC/HCS12, called "Demo/HCS12_GCC_banked"\r
+## Author Jefferson L Smith\r
+##\r
+##-------------------------------------------------------------------\r
+This project stationery is designed to get you up and running quickly with GCC for MC9S12.\r
+\r
+This port is tested with the development board Dragon12 (http://www.evbplus.com/ ).\r
+\r
+This GCC release has been tested:\r
+ gnu-m68hc1x 3.1 from http://m68hc11.serveftp.org/\r
+\r
+The following folders are derived from GEL 1.6 (http://gel.sourceforge.net/ ):\r
+- sys: starting point for GEL system includes\r
+- asm-m68hcs12: specific 9S12 support, mostly referenced by sys\r
+\r
+The demo was partially derived from Demo HCS12_CodeWarrior_banked.\r
+\r
+\r
+##------------------------------------------------------------------------\r
+## Getting Started\r
+##------------------------------------------------------------------------\r
+\r
+---\r
+The COM (SCI) port to use can be changed in the Makefile. Change this parameter in\r
+CPPFLAGS: -DM6812_DEF_SCI=1\r
+0 uses SCI0\r
+1 uses SCI1\r
+\r
+---\r
+The LED port address can be changed in the Makefile. Change this parameter in\r
+CPPFLAGS: -DPORT_LED=M6811_PORTB\r
+\r
+The known ports are: M6811_PORTA, M6811_PORTB, M6811_PTT, M6811_PTP, M6811_PTM, and M6811_PTH. Any other port address could be used.\r
+\r
+If a known port (above) is used, "startup.c" will initialize the correct port. If any other port is used (by typing the port address), it will need to be manually configured as outputs.\r
+\r
+\r
+##------------------------------------------------------------------------\r
+## Memory Banks (PPAGE)\r
+##------------------------------------------------------------------------\r
+\r
+---\r
+HCS12_GCC_banked uses two methods of placing certain code/data into PPAGE banks. The simple way is to edit each function's prototype or definition with an attribute macro ATTR_BANKn as defined in "cpu.h". Replace the 'n' with the number of the bank [0..13].\r
+\r
+Also see "memory.x" sections .bank2 and .bank3 for examples of linking .text and .rodata of a specific ".o" object file into a specific bank.\r
+\r
+\r
+##------------------------------------------------------------------------\r
+## Technical Issues\r
+##------------------------------------------------------------------------\r
+\r
+---\r
+Passing a function pointer to vCreateTasks() does not include the PPAGE value. The result is that it's stack is initialized with PPAGE 0x30. That is not a problem because GCC generates a "trampoline" routine in unbanked memory which will bounce to the far address of the target function. The 16-bit function pointer passed is actually pointing to that trampoline. The trampoline would only be called once--when starting the task.\r
+\r
+---\r
+Here are three aspects to consider when defining ISR:\r
+\r
+1. The ISR might be simple enough to not generate header code such as saving _.frame and has no local variables. This type can be defined as a normal routine (no interrupt attribute) or "naked" if it were implemented in this GCC. IMPORTANT: Use these special port macros defined in "portmacro.h". They go at the beginning and end of the function:\r
+\r
+portISR_HEAD() First line of the ISR\r
+portISR_TAIL() Last line of the ISR\r
+\r
+This ensures all the needed softregs (pseudo CPU registers) are saved on the stack in case of a task swap within the ISR. Because this sets up the stack for a task swap, portTASK_SWITCH_FROM_ISR() could also be used in the ISR to save time and stack space.\r
+\r
+2. The ISR may have one or more local variables. Define it using the interrupt attribute. The special portTASK_SWITCH_FROM_ISR() won't work. If a task is awakened within this ISR, use taskYIELD() which completely saves the appropriate softregs again and uses more stack.\r
+\r
+3. Writing an ISR in assembly avoids the challenges with compiler-generated code. The steps would have to execute the way they execute in the C ISR.\r
+\r
+---\r
+If editing "startup.c", note that the function __premain() executes before global variables are initialized, and before the BSS section is cleared. So using any global variables may have unexpected results.\r
+\r
+---\r
+If you need to use other softregs, edit "portmacro.h" and "port.c" to save/restore them For example _.d1, _.d2, enabled by "-msoft-reg-count=2" on gcc commandline.\r
+\r
+This port expects "-msoft-reg-count=0". This might be the gcc default, but is specified to be certain.\r
+\r
+\r
+##------------------------------------------------------------------------\r
+## TODO\r
+##------------------------------------------------------------------------\r
+\r
+---\r
--- /dev/null
+/* exit.h - Dragon12 development board\r
+ Copyright (C) 2004 Robotronics, Inc.\r
+ Author Jefferson Smith, Robotronics\r
+\r
+This file is free software; you can redistribute it and/or modify it\r
+under the terms of the GNU General Public License as published by the\r
+Free Software Foundation; either version 2, or (at your option) any\r
+later version.\r
+\r
+In addition to the permissions in the GNU General Public License, the\r
+Free Software Foundation gives you unlimited permission to link the\r
+compiled version of this file with other programs, and to distribute\r
+those programs without any restriction coming from the use of this\r
+file. (The General Public License restrictions do apply in other\r
+respects; for example, they cover modification of the file, and\r
+distribution when not linked into another program.)\r
+\r
+This file is distributed in the hope that it will be useful, but\r
+WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with this program; see the file COPYING. If not, write to\r
+the Free Software Foundation, 59 Temple Place - Suite 330,\r
+Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _M68HC12_ARCH_DRAGON12_EXIT_H\r
+#define _M68HC12_ARCH_DRAGON12_EXIT_H\r
+\r
+extern void _exit (short status) __attribute__((noreturn));\r
+\r
+/* For Dbug monitor, use swi to enter in the monitor upon exit. */\r
+extern inline void\r
+_exit (short status)\r
+{\r
+ while (1) {\r
+ __asm__ __volatile__ ("bgnd" : : );\r
+ __asm__ __volatile__ ("swi" : : "d"(status));\r
+ }\r
+}\r
+\r
+#endif\r
--- /dev/null
+/* interrupts.h - Register interrupt vectors (if ram based)\r
+ Copyright (C) 2004 Robotronics, Inc.\r
+ Author Jefferson Smith, Robotronics\r
+\r
+This file is free software; you can redistribute it and/or modify it\r
+under the terms of the GNU General Public License as published by the\r
+Free Software Foundation; either version 2, or (at your option) any\r
+later version.\r
+\r
+In addition to the permissions in the GNU General Public License, the\r
+Free Software Foundation gives you unlimited permission to link the\r
+compiled version of this file with other programs, and to distribute\r
+those programs without any restriction coming from the use of this\r
+file. (The General Public License restrictions do apply in other\r
+respects; for example, they cover modification of the file, and\r
+distribution when not linked into another program.)\r
+\r
+This file is distributed in the hope that it will be useful, but\r
+WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with this program; see the file COPYING. If not, write to\r
+the Free Software Foundation, 59 Temple Place - Suite 330,\r
+Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _M68HC12_ARCH_DRAGON12_INTERRUPTS_H\r
+#define _M68HC12_ARCH_DRAGON12_INTERRUPTS_H\r
+\r
+#define USE_INTERRUPT_TABLE\r
+\r
+/* Only for RAM target. Initializes an interrupt handler vector. */\r
+extern inline void\r
+set_interrupt_handler (interrupt_vector_id id ATTRIBUTE_UNUSED,\r
+ interrupt_t handler ATTRIBUTE_UNUSED)\r
+{\r
+ _vectors_addr[id] = handler;\r
+}\r
+\r
+#endif /* _M68HC12_ARCH_DRAGON12_INTERRUPTS_H */\r
--- /dev/null
+/* param.h - Dragon12 development board\r
+ Copyright (C) 2004 Robotronics, Inc.\r
+ Author Jefferson Smith, Robotronics\r
+\r
+This file is free software; you can redistribute it and/or modify it\r
+under the terms of the GNU General Public License as published by the\r
+Free Software Foundation; either version 2, or (at your option) any\r
+later version.\r
+\r
+In addition to the permissions in the GNU General Public License, the\r
+Free Software Foundation gives you unlimited permission to link the\r
+compiled version of this file with other programs, and to distribute\r
+those programs without any restriction coming from the use of this\r
+file. (The General Public License restrictions do apply in other\r
+respects; for example, they cover modification of the file, and\r
+distribution when not linked into another program.)\r
+\r
+This file is distributed in the hope that it will be useful, but\r
+WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with this program; see the file COPYING. If not, write to\r
+the Free Software Foundation, 59 Temple Place - Suite 330,\r
+Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _M68S12_ARCH_DRAGON12_PARAM_H\r
+#define _M68S12_ARCH_DRAGON12_PARAM_H\r
+\r
+/* Wytec Dragon12 board definitions. */\r
+#define DRAGON12\r
+\r
+/* An application can use these to determine resources of MCU. --jeffs */\r
+#undef RAM_SIZE\r
+#define RAM_SIZE (12*1024) /* Kb of ram */\r
+\r
+#undef ROM_SIZE\r
+#define ROM_SIZE (256*1024) /* Kb read-only */\r
+\r
+#undef DATA_SIZE\r
+#define DATA_SIZE RAM_SIZE /* Data section size. */\r
+\r
+#undef TEXT_SIZE\r
+#define TEXT_SIZE ROM_SIZE /* Text section size. */\r
+\r
+#endif\r
--- /dev/null
+/* Interrupt Vectors defined\r
+ Copyright (C) 2004 Robotronics, Inc.\r
+ Author Jefferson Smith, Robotronics\r
+\r
+This file is free software; you can redistribute it and/or modify it\r
+under the terms of the GNU General Public License as published by the\r
+Free Software Foundation; either version 2, or (at your option) any\r
+later version.\r
+\r
+In addition to the permissions in the GNU General Public License, the\r
+Free Software Foundation gives you unlimited permission to link the\r
+compiled version of this file with other programs, and to distribute\r
+those programs without any restriction coming from the use of this\r
+file. (The General Public License restrictions do apply in other\r
+respects; for example, they cover modification of the file, and\r
+distribution when not linked into another program.)\r
+\r
+This file is distributed in the hope that it will be useful, but\r
+WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with this program; see the file COPYING. If not, write to\r
+the Free Software Foundation, 59 Temple Place - Suite 330,\r
+Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _M68HC12_ASM_INTERRUPTS_DP256_H\r
+#define _M68HC12_ASM_INTERRUPTS_DP256_H\r
+\r
+/** Interrupt vectors as a struct. */\r
+struct interrupt_vectors\r
+{\r
+ interrupt_t res0_handler; /* 0x80 */\r
+ interrupt_t res1_handler; /* 0x82 */\r
+ interrupt_t res2_handler; /* 0x84 */\r
+ interrupt_t res3_handler; /* 0x86 */\r
+ interrupt_t res4_handler; /* 0x88 */\r
+ interrupt_t res5_handler; /* 0x8a */\r
+ interrupt_t pwm_shutdown_handler; /* 0x8c */\r
+ interrupt_t ptpif_handler;\r
+ \r
+ /** Controller Area Networking */\r
+ interrupt_t can4_tx_handler;\r
+ interrupt_t can4_rx_handler;\r
+ interrupt_t can4_err_handler;\r
+ interrupt_t can4_wake_handler;\r
+ interrupt_t can3_tx_handler;\r
+ interrupt_t can3_rx_handler;\r
+ interrupt_t can3_err_handler;\r
+ interrupt_t can3_wake_handler;\r
+ interrupt_t can2_tx_handler;\r
+ interrupt_t can2_rx_handler;\r
+ interrupt_t can2_err_handler;\r
+ interrupt_t can2_wake_handler;\r
+ interrupt_t can1_tx_handler;\r
+ interrupt_t can1_rx_handler;\r
+ interrupt_t can1_err_handler;\r
+ interrupt_t can1_wake_handler;\r
+ interrupt_t can0_tx_handler;\r
+ interrupt_t can0_rx_handler;\r
+ interrupt_t can0_err_handler;\r
+ interrupt_t can0_wake_handler;\r
+ \r
+ interrupt_t flash_handler;\r
+ interrupt_t eeprom_handler;\r
+ interrupt_t spi2_handler;\r
+ interrupt_t spi1_handler;\r
+ interrupt_t iic_handler;\r
+ interrupt_t bdlc_handler;\r
+ interrupt_t selfclk_mode_handler;\r
+ interrupt_t pll_lock_handler;\r
+ interrupt_t accb_overflow_handler;\r
+ interrupt_t mccnt_underflow_handler;\r
+ interrupt_t pthif_handler;\r
+ interrupt_t ptjif_handler;\r
+ interrupt_t atd1_handler;\r
+ interrupt_t atd0_handler;\r
+ interrupt_t sci1_handler;\r
+ interrupt_t sci0_handler;\r
+ interrupt_t spi0_handler;\r
+ \r
+ /** Timer and Accumulator */\r
+ interrupt_t acca_input_handler;\r
+ interrupt_t acca_overflow_handler;\r
+ interrupt_t timer_overflow_handler;\r
+ \r
+ /** Input capture / Output compare Timers */\r
+ interrupt_t tc7_handler;\r
+ interrupt_t tc6_handler;\r
+ interrupt_t tc5_handler;\r
+ interrupt_t tc4_handler;\r
+ interrupt_t tc3_handler;\r
+ interrupt_t tc2_handler;\r
+ interrupt_t tc1_handler;\r
+ interrupt_t tc0_handler;\r
+ \r
+ /** External Interrupts */\r
+ interrupt_t rtii_handler;\r
+ interrupt_t irq_handler;\r
+ interrupt_t xirq_handler;\r
+\r
+ /** Software Interrupt */\r
+ interrupt_t swi_handler;\r
+\r
+ /** Illegal Instruction Reset */\r
+ interrupt_t illegal_handler;\r
+\r
+ /** COP Timeout Reset */\r
+ interrupt_t cop_fail_handler;\r
+\r
+ /** Clock Monitor Fail Reset */\r
+ interrupt_t cop_clock_handler;\r
+\r
+ /** Start or Reset vector */\r
+ interrupt_t reset_handler;\r
+};\r
+typedef struct interrupt_vectors interrupt_vectors_t;\r
+\r
+/** Interrupt vector id. */\r
+enum interrupt_vector_id\r
+{\r
+ RES0_VECTOR = 0,\r
+ RES1_VECTOR,\r
+ RES2_VECTOR,\r
+ RES3_VECTOR,\r
+ RES4_VECTOR,\r
+ RES5_VECTOR,\r
+ PWM_SHUTDOWN_VECTOR,\r
+ PTPIF_VECTOR,\r
+ CAN4_TX_VECTOR,\r
+ CAN4_RX_VECTOR,\r
+ CAN4_ERR_VECTOR,\r
+ CAN4_WAKE_VECTOR,\r
+ CAN3_TX_VECTOR,\r
+ CAN3_RX_VECTOR,\r
+ CAN3_ERR_VECTOR,\r
+ CAN3_WAKE_VECTOR,\r
+ CAN2_TX_VECTOR,\r
+ CAN2_RX_VECTOR,\r
+ CAN2_ERR_VECTOR,\r
+ CAN2_WAKE_VECTOR,\r
+ CAN1_TX_VECTOR,\r
+ CAN1_RX_VECTOR,\r
+ CAN1_ERR_VECTOR,\r
+ CAN1_WAKE_VECTOR,\r
+ CAN0_TX_VECTOR,\r
+ CAN0_RX_VECTOR,\r
+ CAN0_ERR_VECTOR,\r
+ CAN0_WAKE_VECTOR,\r
+ FLASH_VECTOR,\r
+ EEPROM_VECTOR,\r
+ SPI2_VECTOR,\r
+ SPI1_VECTOR,\r
+ IIC_VECTOR,\r
+ BDLC_VECTOR,\r
+ SELFCLK_MODE_VECTOR,\r
+ PLL_LOCK_VECTOR,\r
+ ACCB_OVERFLOW_VECTOR,\r
+ MCCNT_UNDERFLOW_VECTOR,\r
+ PTHIF_VECTOR,\r
+ PTJIF_VECTOR,\r
+ ATD1_VECTOR,\r
+ ATD0_VECTOR,\r
+ SCI1_VECTOR,\r
+ SCI0_VECTOR,\r
+ SPI0_VECTOR,\r
+ ACCA_INPUT_VECTOR,\r
+ ACCA_OVERFLOW_VECTOR,\r
+ TIMER_OVERFLOW_VECTOR,\r
+ TC7_VECTOR,\r
+ TC6_VECTOR,\r
+ TC5_VECTOR,\r
+ TC4_VECTOR,\r
+ TC3_VECTOR,\r
+ TC2_VECTOR,\r
+ TC1_VECTOR,\r
+ TC0_VECTOR,\r
+ RTI_VECTOR,\r
+ IRQ_VECTOR,\r
+ XIRQ_VECTOR,\r
+ SWI_VECTOR,\r
+ ILLEGAL_OPCODE_VECTOR,\r
+ COP_FAIL_VECTOR,\r
+ COP_CLOCK_VECTOR,\r
+ RESET_VECTOR,\r
+ MAX_VECTORS\r
+};\r
+typedef enum interrupt_vector_id interrupt_vector_id;\r
+\r
+/** some backwards-compatible equivalents from HC11 */\r
+#define SCI_VECTOR SCI0_VECTOR\r
+#define SPI_VECTOR SPI0_VECTOR\r
+#define ACC_INPUT_VECTOR ACCA_INPUT_VECTOR\r
+#define ACC_OVERFLOW_VECTOR ACCA_OVERFLOW_VECTOR\r
+\r
+#endif /* _M68HC12_ASM_INTERRUPTS_DP256_H */\r
--- /dev/null
+/* Interrupt Vectors\r
+ Copyright (C) 2000 Free Software Foundation, Inc.\r
+ Written by Stephane Carrez (stcarrez@worldnet.fr) \r
+ Modified; Jefferson Smith, Robotronics; for HC12/9S12\r
+\r
+This file is free software; you can redistribute it and/or modify it\r
+under the terms of the GNU General Public License as published by the\r
+Free Software Foundation; either version 2, or (at your option) any\r
+later version.\r
+\r
+In addition to the permissions in the GNU General Public License, the\r
+Free Software Foundation gives you unlimited permission to link the\r
+compiled version of this file with other programs, and to distribute\r
+those programs without any restriction coming from the use of this\r
+file. (The General Public License restrictions do apply in other\r
+respects; for example, they cover modification of the file, and\r
+distribution when not linked into another program.)\r
+\r
+This file is distributed in the hope that it will be useful, but\r
+WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with this program; see the file COPYING. If not, write to\r
+the Free Software Foundation, 59 Temple Place - Suite 330,\r
+Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _M68HC12_INTERRUPTS_H\r
+#define _M68HC12_INTERRUPTS_H\r
+\r
+/*! @defgroup interrupts Interrupts.\r
+\r
+ */\r
+/*@{*/\r
+\r
+/*! Interrupt handler prototype. */\r
+typedef void (* interrupt_t) (void);\r
+\r
+#ifdef mc68hcs12\r
+# include "interrupts-dp256.h"\r
+#endif\r
+\r
+/*! Interrupt vector table.\r
+\r
+ The interrupt vector table is in general located at `0xff80'\r
+ in memory. It is at the same address as the interrupt\r
+ vectors structure (alias). */\r
+extern interrupt_t _vectors_addr[MAX_VECTORS];\r
+\r
+extern interrupt_vectors_t _vectors __asm__("_vectors_addr");\r
+\r
+/*@}*/\r
+#endif /* _M68HC12_INTERRUPTS_H */\r
--- /dev/null
+/* param.h - Board specific parameters\r
+ Copyright (C) 2000 Free Software Foundation, Inc.\r
+ Written by Stephane Carrez (stcarrez@worldnet.fr) \r
+\r
+This file is free software; you can redistribute it and/or modify it\r
+under the terms of the GNU General Public License as published by the\r
+Free Software Foundation; either version 2, or (at your option) any\r
+later version.\r
+\r
+In addition to the permissions in the GNU General Public License, the\r
+Free Software Foundation gives you unlimited permission to link the\r
+compiled version of this file with other programs, and to distribute\r
+those programs without any restriction coming from the use of this\r
+file. (The General Public License restrictions do apply in other\r
+respects; for example, they cover modification of the file, and\r
+distribution when not linked into another program.)\r
+\r
+This file is distributed in the hope that it will be useful, but\r
+WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with this program; see the file COPYING. If not, write to\r
+the Free Software Foundation, 59 Temple Place - Suite 330,\r
+Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _M68HC11_PARAM_H\r
+#define _M68HC11_PARAM_H\r
+\r
+/**@name M68HC12 Board Parameters.\r
+\r
+ This section contains several '#define' to give configuration\r
+ characteristics of the target board. */\r
+/*@{*/\r
+\r
+/** CPU Clock frequency.\r
+ \r
+ Define the frequency of the oscillator plugged on the processor.\r
+ The value is in hertz. */\r
+#ifndef M6811_CPU_CLOCK\r
+# define M6811_CPU_CLOCK (16e6L)\r
+#endif\r
+\r
+/** CPU E clock.\r
+ \r
+ The E clock frequency. This frequency is used as the\r
+ basis for timer computation. The value is in hertz. */\r
+#ifndef M6811_CPU_E_CLOCK\r
+# define M6811_CPU_E_CLOCK (24e6L)\r
+#endif\r
+\r
+#ifndef M6812_REFCLOCK\r
+# define M6812_REFCLOCK M6811_CPU_CLOCK\r
+#endif\r
+\r
+#ifndef M6812_REFDVVAL\r
+# define M6812_REFDVVAL (M6811_CPU_CLOCK / M6812_REFCLOCK) - 1\r
+#endif\r
+\r
+#ifndef M6812_SYNRVAL\r
+#define M6812_SYNRVAL (M6811_CPU_E_CLOCK / M6812_REFCLOCK) - 1\r
+#endif\r
+\r
+/** SIO default baud rate.\r
+ \r
+ Defines the default baud rate of the SIO. This value\r
+ is used to configure the BAUD register.\r
+ */\r
+#ifndef M6811_DEF_BAUD\r
+# define M6811_DEF_BAUD (unsigned short)(M6811_CPU_E_CLOCK / 16 / 9600)\r
+#endif\r
+\r
+/** Use the COP.\r
+ \r
+ Define this if you are using the COP timer.\r
+ This activate the COP reset while polling and writing on\r
+ the serial line. */\r
+#ifndef M6811_USE_COP\r
+# define M6811_USE_COP 0\r
+#endif\r
+\r
+/** Timer prescaler value. */\r
+#ifndef M6811_DEF_TPR\r
+# define M6811_DEF_TPR 0\r
+#endif\r
+\r
+#ifndef M6811_DEF_RTR\r
+# define M6811_DEF_RTR 0\r
+#endif\r
+\r
+/** SCI default port. */\r
+#ifndef M6812_DEF_SCI\r
+# define M6812_DEF_SCI 0\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif\r
--- /dev/null
+/* m68hc11/ports.h -- Definition of 68HC11 ports\r
+ Copyright 1999, 2000, 2003 Free Software Foundation, Inc.\r
+ Written by Stephane Carrez (stcarrez@nerim.fr)\r
+\r
+ Modified by Jefferson L Smith, Robotronics Inc.\r
+\r
+This file is part of GDB, GAS, and the GNU binutils.\r
+\r
+GDB, GAS, and the GNU binutils are free software; you can redistribute\r
+them and/or modify them under the terms of the GNU General Public\r
+License as published by the Free Software Foundation; either version\r
+1, or (at your option) any later version.\r
+\r
+GDB, GAS, and the GNU binutils are distributed in the hope that they\r
+will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See\r
+the GNU General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with this file; see the file COPYING. If not, write to the Free\r
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _M68HC11_PORTS_H\r
+#define _M68HC11_PORTS_H\r
+\r
+#include "ports_def.h"\r
+\r
+/** Define default SCI port registers */\r
+#if defined(M6812_DEF_SCI)\r
+\r
+#if M6812_DEF_SCI==2\r
+# define SCI_BASE SCI2_BASE\r
+#elif M6812_DEF_SCI==1\r
+# define SCI_BASE SCI1_BASE\r
+#else /* default M6812_DEF_SCI==0 */\r
+# define SCI_BASE SCI0_BASE\r
+#endif /* default M6812_DEF_SCI==0 */\r
+\r
+#else /* M6812_DEF_SCI not defined */\r
+# define SCI_BASE SCI0_BASE\r
+#endif /* M6812_DEF_SCI */\r
+\r
+# define SCIBD PORTIO_16(SCI_BASE + _SCIBD)\r
+# define SCICR1 PORTIO_8(SCI_BASE + _SCICR1)\r
+# define SCICR2 PORTIO_8(SCI_BASE + _SCICR2)\r
+# define SCISR1 PORTIO_8(SCI_BASE + _SCISR1)\r
+# define SCISR2 PORTIO_8(SCI_BASE + _SCISR2)\r
+# define SCIDRL PORTIO_8(SCI_BASE + _SCIDRL)\r
+\r
+extern inline unsigned short\r
+get_timer_counter (void)\r
+{\r
+ return TCNT;\r
+}\r
+\r
+extern inline void\r
+set_timer_counter (unsigned short value)\r
+{\r
+ TCNT = value;\r
+}\r
+#if 0\r
+extern inline unsigned short\r
+get_input_capture_1 (void)\r
+{\r
+ return ((unsigned volatile short*) &_io_ports[M6811_TIC1_H])[0];\r
+}\r
+\r
+extern inline void\r
+set_input_capture_1 (unsigned short value)\r
+{\r
+ ((unsigned volatile short*) &_io_ports[M6811_TIC1_H])[0] = value;\r
+}\r
+\r
+extern inline unsigned short\r
+get_input_capture_2 (void)\r
+{\r
+ return ((unsigned volatile short*) &_io_ports[M6811_TIC2_H])[0];\r
+}\r
+\r
+extern inline void\r
+set_input_capture_2 (unsigned short value)\r
+{\r
+ ((unsigned volatile short*) &_io_ports[M6811_TIC2_H])[0] = value;\r
+}\r
+\r
+extern inline unsigned short\r
+get_input_capture_3 (void)\r
+{\r
+ return ((unsigned volatile short*) &_io_ports[M6811_TIC3_H])[0];\r
+}\r
+\r
+extern inline void\r
+set_input_capture_3 (unsigned short value)\r
+{\r
+ ((unsigned volatile short*) &_io_ports[M6811_TIC3_H])[0] = value;\r
+}\r
+\r
+/* Get output compare 16-bit register. */\r
+extern inline unsigned short\r
+get_output_compare_1 (void)\r
+{\r
+ return ((unsigned volatile short*) &_io_ports[M6811_TOC1_H])[0];\r
+}\r
+\r
+extern inline void\r
+set_output_compare_1 (unsigned short value)\r
+{\r
+ ((unsigned volatile short*) &_io_ports[M6811_TOC1_H])[0] = value;\r
+}\r
+\r
+extern inline unsigned short\r
+get_output_compare_2 (void)\r
+{\r
+ return ((unsigned volatile short*) &_io_ports[M6811_TOC2_H])[0];\r
+}\r
+\r
+extern inline void\r
+set_output_compare_2 (unsigned short value)\r
+{\r
+ ((unsigned volatile short*) &_io_ports[M6811_TOC2_H])[0] = value;\r
+}\r
+\r
+extern inline unsigned short\r
+get_output_compare_3 (void)\r
+{\r
+ return ((unsigned volatile short*) &_io_ports[M6811_TOC3_H])[0];\r
+}\r
+\r
+extern inline void\r
+set_output_compare_3 (unsigned short value)\r
+{\r
+ ((unsigned volatile short*) &_io_ports[M6811_TOC3_H])[0] = value;\r
+}\r
+\r
+extern inline unsigned short\r
+get_output_compare_4 (void)\r
+{\r
+ return ((unsigned volatile short*) &_io_ports[M6811_TOC4_H])[0];\r
+}\r
+\r
+extern inline void\r
+set_output_compare_4 (unsigned short value)\r
+{\r
+ ((unsigned volatile short*) &_io_ports[M6811_TOC4_H])[0] = value;\r
+}\r
+\r
+extern inline unsigned short\r
+get_output_compare_5 (void)\r
+{\r
+ return ((unsigned volatile short*) &_io_ports[M6811_TOC5_H])[0];\r
+}\r
+\r
+extern inline void\r
+set_output_compare_5 (unsigned short value)\r
+{\r
+ ((unsigned volatile short*) &_io_ports[M6811_TOC5_H])[0] = value;\r
+}\r
+\r
+#endif\r
+\r
+/* Reset the COP. */\r
+extern inline void\r
+cop_reset (void)\r
+{\r
+ ARMCOP = 0x55;\r
+ ARMCOP = 0xAA;\r
+}\r
+\r
+extern inline void\r
+cop_optional_reset (void)\r
+{\r
+#if defined(M6811_USE_COP) && M6811_USE_COP == 1\r
+ cop_reset ();\r
+#endif\r
+}\r
+\r
+/* Acknowledge the timer interrupt. */\r
+extern inline void\r
+timer_acknowledge (void)\r
+{\r
+ CRGFLG = RTIF;\r
+}\r
+\r
+/* Initialize the timer. */\r
+extern inline void\r
+timer_initialize_rate (unsigned char divisor)\r
+{\r
+ RTICTL = divisor;\r
+}\r
+\r
+#endif /* _M68HC11_PORTS_H */\r
+\r
--- /dev/null
+/* IO DEFINITIONS AND MACROS FOR THE MCS912DG256B\r
+ 09/19/03\r
+ EMAC.inc\r
+ Nathan Z. Gustavson ngustavson@emacinc.com\r
+ Emac.inc\r
+ May 2005; Modified by Jefferson Smith for general use in GEL\r
+ */\r
+#ifndef _ARCH_IODG256B_H\r
+#define _ARCH_IODG256B_H\r
+\r
+#define IO_BASE 0\r
+/*macros\r
+*/\r
+#define ienable() __asm("cli");\r
+#define idisable() __asm("orcc #0x10")\r
+#define xenable() __asm("andcc #0xbf")\r
+#define xdisable()__asm("orcc #0x40")\r
+\r
+/* constant offsets to use where a C expression doesn't work\r
+*/\r
+#define M6811_PORTA 0x00\r
+#define M6811_PORTB 0x01\r
+#define M6811_PTT 0x240\r
+#define M6811_PTM 0x250\r
+#define M6811_PTP 0x258\r
+#define M6811_PTH 0x260\r
+\r
+#define PORTIO_8 *(volatile unsigned char *)\r
+#define PORTIO_16 *(volatile unsigned short int *)\r
+\r
+/* Core HC12 Registers\r
+ */\r
+#define PORTA PORTIO_8(IO_BASE + 0x00) /* port A */\r
+#define PORTB PORTIO_8(IO_BASE + 0x01) /* port B */\r
+#define DDRA PORTIO_8(IO_BASE + 0x02) /* data direction port A */\r
+#define DDRB PORTIO_8(IO_BASE + 0x03) /* data direction port B */\r
+#define PORTE PORTIO_8(IO_BASE + 0x08) /* port E */\r
+#define DDRE PORTIO_8(IO_BASE + 0x09) /* data direction port E */\r
+#define PEAR PORTIO_8(IO_BASE + 0x0a) /* port E assignment register */\r
+#define MODE PORTIO_8(IO_BASE + 0x0b) /* mode register */\r
+#define PUCR PORTIO_8(IO_BASE + 0x0c) /* pull-up control register */\r
+#define RDRIV PORTIO_8(IO_BASE + 0x0d) /* reduced drive of I/O lines */\r
+#define EBICTL PORTIO_8(IO_BASE + 0x0e) /* external bus control */\r
+#define INITRM PORTIO_8(IO_BASE + 0x10) /* RAM mapping register */\r
+#define INITRG PORTIO_8(IO_BASE + 0x11) /* IO mapping register */\r
+#define INITEE PORTIO_8(IO_BASE + 0x12) /* EEPROM mapping register */\r
+#define MISC PORTIO_8(IO_BASE + 0x13) /* mapping control register */\r
+#define MTST0 PORTIO_8(IO_BASE + 0x14) /* mapping test register 0 */\r
+#define ITCR PORTIO_8(IO_BASE + 0x15) /* interrupt test control reg. */\r
+#define ITEST PORTIO_8(IO_BASE + 0x16) /* interrupt test register */\r
+#define MTST1 PORTIO_8(IO_BASE + 0x17) /* mapping test register 1 */\r
+#define PARTID PORTIO_16(IO_BASE + 0x1a) /* part ID register */\r
+#define MEMSIZ0 PORTIO_8(IO_BASE + 0x1c) /* memory size register 0 */\r
+#define MEMSIZ1 PORTIO_8(IO_BASE + 0x1d) /* memory size register 1 */\r
+#define INTCR PORTIO_8(IO_BASE + 0x1e) /* interrupt control */\r
+#define HPRIO PORTIO_8(IO_BASE + 0x1f) /* highest priority */\r
+\r
+/*\r
+bitflags\r
+*/\r
+//PEAR\r
+#define NOACCE 0x80\r
+#define PIPOE 0x20\r
+#define NECLK 0x10\r
+#define LSTRE 0x08\r
+#define RDWE 0x04\r
+//INTCR bitflags\r
+#define IRQE 0x80\r
+#define IRQEN 0x40\r
+#define DLY 0x20\r
+\r
+/* BKP Module \r
+ */\r
+#define BKPCT0 PORTIO_8(IO_BASE + 0x28) /* Breakpoint Control 0 */\r
+#define BKPCT1 PORTIO_8(IO_BASE + 0x29) /* Breakpoint Control 1 */\r
+#define BKP0X PORTIO_8(IO_BASE + 0x2a) /* Breakpoint 0 address upper */\r
+#define BKP0 PORTIO_16(IO_BASE + 0x2b) /* Breakpoint 0 address */\r
+#define BKP1X PORTIO_8(IO_BASE + 0x2d) /* Breakpoint 1 address upper */\r
+#define BKP1 PORTIO_16(IO_BASE + 0x2e) /* Breakpoint 1 address */\r
+\r
+/* MEBI Module \r
+ */\r
+#define PPAGE PORTIO_8(IO_BASE + 0x30) /* program page register */\r
+#define PORTK PORTIO_8(IO_BASE + 0x32) /* port K data register */\r
+#define DDRK PORTIO_8(IO_BASE + 0x33) /* port K data direction */\r
+\r
+/* CRG Module \r
+ */\r
+#define SYNR PORTIO_8(IO_BASE + 0x34) /* synthesizer register */\r
+#define REFDV PORTIO_8(IO_BASE + 0x35) /* reference divider register */\r
+#define CTFLG PORTIO_8(IO_BASE + 0x36) /* clock test flag register */\r
+#define CRGFLG PORTIO_8(IO_BASE + 0x37) /* clock generator flag register */\r
+#define CRGINT PORTIO_8(IO_BASE + 0x38) /* clock interrupt enable */\r
+#define CLKSEL PORTIO_8(IO_BASE + 0x39) /* clock select register */\r
+#define PLLCTL PORTIO_8(IO_BASE + 0x3a) /* PLL control register */\r
+#define RTICTL PORTIO_8(IO_BASE + 0x3b) /* clock real time control reg. */\r
+#define COPCTL PORTIO_8(IO_BASE + 0x3c) /* COP control register */\r
+#define FORBYP PORTIO_8(IO_BASE + 0x3d) /* clock force and bypass register */\r
+#define CTCTL PORTIO_8(IO_BASE + 0x3e) /* clock test control register */\r
+#define ARMCOP PORTIO_8(IO_BASE + 0x3f) /* COP arm/reset register with sequence 0x55,0xaa. */\r
+\r
+// CRG bitflags\r
+#define RTIF 0x80\r
+#define RTIE 0x80\r
+#define LOCK 0x08\r
+#define AUTO 0x20\r
+#define PLLSEL 0x80\r
+// COPCTL bitflags\r
+#define WCOP 0x80\r
+#define RSBCK 0x40\r
+\r
+/* ECT Module\r
+ */\r
+#define TIOS PORTIO_8(IO_BASE + 0x40) /* timer select register */\r
+#define TCFORC PORTIO_8(IO_BASE + 0x41) /* compare force register */\r
+#define TOC7M PORTIO_8(IO_BASE + 0x42) /* oc7 mask register */\r
+#define TOC7D PORTIO_8(IO_BASE + 0x43) /* oc7 data register */\r
+#define TCNT PORTIO_16(IO_BASE + 0x44) /* timer counter */\r
+#define TSCR1 PORTIO_8(IO_BASE + 0x46) /* system control register 1 */\r
+#define TTOV PORTIO_8(IO_BASE + 0x47) /* toggle on overflow register */\r
+#define TCTL1 PORTIO_8(IO_BASE + 0x48) /* control register 1 */\r
+#define TCTL2 PORTIO_8(IO_BASE + 0x49) /* control register 2 */\r
+#define TCTL3 PORTIO_8(IO_BASE + 0x4a) /* control register 3 */\r
+#define TCTL4 PORTIO_8(IO_BASE + 0x4b) /* control register 4 */\r
+#define TIE PORTIO_8(IO_BASE + 0x4c) /* interrupt enable register */\r
+#define TSCR2 PORTIO_8(IO_BASE + 0x4d) /* system control register 2 */\r
+#define TFLG1 PORTIO_8(IO_BASE + 0x4e) /* interrupt flag register 1 */\r
+#define TFLG2 PORTIO_8(IO_BASE + 0x4f) /* interrupt flag register 2 */\r
+#define TC0 PORTIO_16(IO_BASE + 0x50) /* capture/compare register 0 */\r
+#define TC1 PORTIO_16(IO_BASE + 0x52) /* capture/compare register 0 */\r
+#define TC2 PORTIO_16(IO_BASE + 0x54) /* capture/compare register 0 */\r
+#define TC3 PORTIO_16(IO_BASE + 0x56) /* capture/compare register 0 */\r
+#define TC4 PORTIO_16(IO_BASE + 0x58) /* capture/compare register 0 */\r
+#define TC5 PORTIO_16(IO_BASE + 0x5a) /* capture/compare register 0 */\r
+#define TC6 PORTIO_16(IO_BASE + 0x5c) /* capture/compare register 0 */\r
+#define TC7 PORTIO_16(IO_BASE + 0x5e) /* capture/compare register 0 */\r
+#define PACTL PORTIO_8(IO_BASE + 0x60) /* pulse accumulator A control */\r
+#define PAFLG PORTIO_8(IO_BASE + 0x61) /* pulse accumulator A flag */\r
+#define PACN3 PORTIO_8(IO_BASE + 0x62) /* pulse accumulator A3 count */\r
+#define PACN2 PORTIO_8(IO_BASE + 0x63) /* pulse accumulator A2 count */\r
+#define PACN1 PORTIO_8(IO_BASE + 0x64) /* pulse accumulator A1 count */\r
+#define PACN0 PORTIO_8(IO_BASE + 0x65) /* pulse accumulator A0 count */\r
+#define MCCTL PORTIO_8(IO_BASE + 0x66) /* modulus counter control reg */\r
+#define MCFLG PORTIO_8(IO_BASE + 0x67) /* modulus counter flag reg */\r
+#define ICPAR PORTIO_8(IO_BASE + 0x68) /* input control pulse acc reg */\r
+#define DLYCT PORTIO_8(IO_BASE + 0x69) /* delay counter control reg */\r
+#define ICOVW PORTIO_8(IO_BASE + 0x6a) /* input control overwrite reg */\r
+#define ICSYS PORTIO_8(IO_BASE + 0x6b) /* input control system reg */\r
+#define TIMTST PORTIO_8(IO_BASE + 0x6d) /* timer test register */\r
+#define PBCTL PORTIO_8(IO_BASE + 0x70) /* pulse accumulator B control */\r
+#define PBFLG PORTIO_8(IO_BASE + 0x71) /* pulse accumulator B flag */\r
+#define PA3H PORTIO_8(IO_BASE + 0x72) /* pulse accumulator B3 count */\r
+#define PA2H PORTIO_8(IO_BASE + 0x73) /* pulse accumulator B2 count */\r
+#define PA1H PORTIO_8(IO_BASE + 0x74) /* pulse accumulator B1 count */\r
+#define PA0H PORTIO_8(IO_BASE + 0x75) /* pulse accumulator B0 count */\r
+#define MCCNT PORTIO_16(IO_BASE + 0x76) /* modulus counter count reg */\r
+#define TC0H PORTIO_16(IO_BASE + 0x78) /* timer input capture hold 0 */\r
+#define TC1H PORTIO_16(IO_BASE + 0x7a) /* timer input capture hold 1 */\r
+#define TC2H PORTIO_16(IO_BASE + 0x7c) /* timer input capture hold 2 */\r
+#define TC3H PORTIO_16(IO_BASE + 0x7e) /* timer input capture hold 3 */\r
+\r
+/* ATD0 Module \r
+ */\r
+#define ATD0_BASE (IO_BASE + 0x80)\r
+#define ATD0CTL0 PORTIO_8(IO_BASE + 0x80) /* A/D0 control register 0 */\r
+#define ATD0CTL1 PORTIO_8(IO_BASE + 0x81) /* A/D0 control register 1 */\r
+#define ATD0CTL2 PORTIO_8(IO_BASE + 0x82) /* A/D0 control register 2 */\r
+#define ATD0CTL3 PORTIO_8(IO_BASE + 0x83) /* A/D0 control register 3 */\r
+#define ATD0CTL4 PORTIO_8(IO_BASE + 0x84) /* A/D0 control register 4 */\r
+#define ATD0CTL5 PORTIO_8(IO_BASE + 0x85) /* A/D0 control register 5 */\r
+#define ATD0STAT0 PORTIO_8(IO_BASE + 0x86) /* A/D0 status register 0 */\r
+#define ATD0STAT1 PORTIO_8(IO_BASE + 0x87) /* A/D0 status register 1 */\r
+#define ATD0TEST0 PORTIO_8(IO_BASE + 0x88) /* A/D0 test register 0 */\r
+#define ATD0TEST1 PORTIO_8(IO_BASE + 0x89) /* A/D0 test register 1 */\r
+#define ATD0DIEN PORTIO_8(IO_BASE + 0x8d) /* A/D0 interrupt enable */\r
+#define PORTAD0 PORTIO_8(IO_BASE + 0x8f) /* port AD0 data input register */\r
+#define ATD0DR0 PORTIO_16(IO_BASE + 0x90) /* A/D0 result 0 */\r
+#define ATD0DR0H PORTIO_8(IO_BASE + 0x90) /* A/D0 result 0 */\r
+#define ATD0DR1 PORTIO_16(IO_BASE + 0x92) /* A/D0 result 1 */\r
+#define ATD0DR1H PORTIO_8(IO_BASE + 0x92) /* A/D0 result 1 */\r
+#define ATD0DR2 PORTIO_16(IO_BASE + 0x94) /* A/D0 result 2 */\r
+#define ATD0DR2H PORTIO_8(IO_BASE + 0x94) /* A/D0 result 2 */\r
+#define ATD0DR3 PORTIO_16(IO_BASE + 0x96) /* A/D0 result 3 */\r
+#define ATD0DR3H PORTIO_8(IO_BASE + 0x96) /* A/D0 result 3 */\r
+#define ATD0DR4 PORTIO_16(IO_BASE + 0x98) /* A/D0 result 4 */\r
+#define ATD0DR4H PORTIO_8(IO_BASE + 0x98) /* A/D0 result 4 */\r
+#define ATD0DR5 PORTIO_16(IO_BASE + 0x9a) /* A/D0 result 5 */\r
+#define ATD0DR5H PORTIO_8(IO_BASE + 0x9a) /* A/D0 result 5 */\r
+#define ATD0DR6 PORTIO_16(IO_BASE + 0x9c) /* A/D0 result 6 */\r
+#define ATD0DR6H PORTIO_8(IO_BASE + 0x9c) /* A/D0 result 6 */\r
+#define ATD0DR7 PORTIO_16(IO_BASE + 0x9e) /* A/D0 result 7 */\r
+#define ATD0DR7H PORTIO_8(IO_BASE + 0x9e) /* A/D0 result 7 */\r
+\r
+//ATDnCTL5 bitflags\r
+#define DJM 0x80\r
+#define DSGN 0x40\r
+#define SCAN 0x20\r
+#define MULT 0x10\r
+//ATDnSTAT0 bitflags\r
+#define SCF 0x80\r
+#define ETORF 0x20\r
+#define FIFOR 0x10\r
+\r
+/* PWM Module \r
+ */\r
+#define PWME PORTIO_8(IO_BASE + 0xa0) /* PWM Enable */\r
+#define PWMPOL PORTIO_8(IO_BASE + 0xa1) /* PWM Clock Polarity */\r
+#define PWMCLK PORTIO_8(IO_BASE + 0xa2) /* PWM Clocks */\r
+#define PWMPRCLK PORTIO_8(IO_BASE + 0xa3) /* PWM prescale clock select */\r
+#define PWMCAE PORTIO_8(IO_BASE + 0xa4) /* PWM center align enable */\r
+#define PWMCTL PORTIO_8(IO_BASE + 0xa5) /* PWM Control Register */\r
+#define PWMTST PORTIO_8(IO_BASE + 0xa6) /* PWM Test Register */\r
+#define PWMPRSC PORTIO_8(IO_BASE + 0xa7) /* PWM Test Register */\r
+#define PWMSCLA PORTIO_8(IO_BASE + 0xa8) /* PWM scale A */\r
+#define PWMSCLB PORTIO_8(IO_BASE + 0xa9) /* PWM scale B */\r
+#define PWMSCNTA PORTIO_8(IO_BASE + 0xaa) /* PWM Test Register A */\r
+#define PWMSCNTB PORTIO_8(IO_BASE + 0xab) /* PWM Test Register B */\r
+#define PWMCNT0 PORTIO_8(IO_BASE + 0xac) /* PWM Channel Counter 0 */\r
+#define PWMCNT1 PORTIO_8(IO_BASE + 0xad) /* PWM Channel Counter 1 */\r
+#define PWMCNT2 PORTIO_8(IO_BASE + 0xae) /* PWM Channel Counter 2 */\r
+#define PWMCNT3 PORTIO_8(IO_BASE + 0xaf) /* PWM Channel Counter 3 */\r
+#define PWMCNT4 PORTIO_8(IO_BASE + 0xb0) /* PWM Channel Counter 4 */\r
+#define PWMCNT5 PORTIO_8(IO_BASE + 0xb1) /* PWM Channel Counter 5 */\r
+#define PWMCNT6 PORTIO_8(IO_BASE + 0xb2) /* PWM Channel Counter 6 */\r
+#define PWMCNT7 PORTIO_8(IO_BASE + 0xb3) /* PWM Channel Counter 7 */\r
+#define PWMPER0 PORTIO_8(IO_BASE + 0xb4) /* PWM Channel Period 0 */\r
+#define PWMPER1 PORTIO_8(IO_BASE + 0xb5) /* PWM Channel Period 1 */\r
+#define PWMPER2 PORTIO_8(IO_BASE + 0xb6) /* PWM Channel Period 2 */\r
+#define PWMPER3 PORTIO_8(IO_BASE + 0xb7) /* PWM Channel Period 3 */\r
+#define PWMPER4 PORTIO_8(IO_BASE + 0xb8) /* PWM Channel Period 4 */\r
+#define PWMPER5 PORTIO_8(IO_BASE + 0xb9) /* PWM Channel Period 5 */\r
+#define PWMPER6 PORTIO_8(IO_BASE + 0xba) /* PWM Channel Period 6 */\r
+#define PWMPER7 PORTIO_8(IO_BASE + 0xbb) /* PWM Channel Period 7 */\r
+#define PWMDTY0 PORTIO_8(IO_BASE + 0xbc) /* PWM Channel Duty 0 */\r
+#define PWMDTY1 PORTIO_8(IO_BASE + 0xbd) /* PWM Channel Duty 1 */\r
+#define PWMDTY2 PORTIO_8(IO_BASE + 0xbe) /* PWM Channel Duty 2 */\r
+#define PWMDTY3 PORTIO_8(IO_BASE + 0xbf) /* PWM Channel Duty 3 */\r
+#define PWMDTY4 PORTIO_8(IO_BASE + 0xc0) /* PWM Channel Duty 4 */\r
+#define PWMDTY5 PORTIO_8(IO_BASE + 0xc1) /* PWM Channel Duty 5 */\r
+#define PWMDTY6 PORTIO_8(IO_BASE + 0xc2) /* PWM Channel Duty 6 */\r
+#define PWMDTY7 PORTIO_8(IO_BASE + 0xc3) /* PWM Channel Duty 7 */\r
+#define PWMSDN PORTIO_8(IO_BASE + 0xc4) /* PWM shutdown register */\r
+\r
+/* SCI register offsets\r
+ jeffs: Use these to offset any standard SCI base\r
+ */\r
+#define _SCIBD 0x0 /* SCI baud rate high */\r
+#define _SCIBDH 0x0 /* SCI baud rate high */\r
+#define _SCIBDL 0x1 /* SCI baud rate low */\r
+#define _SCICR1 0x2 /* SCI control register 1 */\r
+#define _SCICR2 0x3 /* SCI control register 2 */\r
+#define _SCISR1 0x4 /* SCI status register 1 */\r
+#define _SCISR2 0x5 /* SCI status register 2 */\r
+#define _SCIDRH 0x6 /* SCI data register high */\r
+#define _SCIDRL 0x7 /* SCI data register low */\r
+\r
+/* SCI0 Module \r
+ jeffs: Use symbols like SCI0_BASE to reference which SCI block\r
+ */\r
+#define SCI0_BASE (IO_BASE + 0xc8)\r
+#define SCI0BD PORTIO_16(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDH PORTIO_8(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDL PORTIO_8(IO_BASE + 0xc9) /* SCI 0 baud rate low */\r
+#define SCI0CR1 PORTIO_8(IO_BASE + 0xca) /* SCI 0 control register 1 */\r
+#define SCI0CR2 PORTIO_8(IO_BASE + 0xcb) /* SCI 0 control register 2 */\r
+#define SCI0SR1 PORTIO_8(IO_BASE + 0xcc) /* SCI 0 status register 1 */\r
+#define SCI0SR2 PORTIO_8(IO_BASE + 0xcd) /* SCI 0 status register 2 */\r
+#define SCI0DRH PORTIO_8(IO_BASE + 0xce) /* SCI 0 data register high */\r
+#define SCI0DRL PORTIO_8(IO_BASE + 0xcf) /* SCI 0 data register low */\r
+\r
+/* SCI1 Module \r
+ */\r
+#define SCI1_BASE (IO_BASE + 0xd0)\r
+#define SCI1BD PORTIO_16(IO_BASE + 0xd0) /* SCI 1 16bit baud rate */\r
+#define SCI1BDH PORTIO_8(IO_BASE + 0xd0) /* SCI 1 baud rate high */\r
+#define SCI1BDL PORTIO_8(IO_BASE + 0xd1) /* SCI 1 baud rate low */\r
+#define SCI1CR1 PORTIO_8(IO_BASE + 0xd2) /* SCI 1 control register 1 */\r
+#define SCI1CR2 PORTIO_8(IO_BASE + 0xd3) /* SCI 1 control register 2 */\r
+#define SCI1SR1 PORTIO_8(IO_BASE + 0xd4) /* SCI 1 status register 1 */\r
+#define SCI1SR2 PORTIO_8(IO_BASE + 0xd5) /* SCI 1 status register 2 */\r
+#define SCI1DRH PORTIO_8(IO_BASE + 0xd6) /* SCI 1 data register high */\r
+#define SCI1DRL PORTIO_8(IO_BASE + 0xd7) /* SCI 1 data register low */\r
+\r
+//SCInSR1\r
+#define TDRE 0x80\r
+#define RDRF 0x20\r
+#define IDLE 0x10\r
+\r
+/* SPI register offsets\r
+ */ \r
+#define _SPICR1 PORTIO_8(IO_BASE + 0x0) /* SPI control register 1 */\r
+#define _SPICR2 PORTIO_8(IO_BASE + 0x1) /* SPI control register 2 */\r
+#define _SPIBR PORTIO_8(IO_BASE + 0x2) /* SPI baud rate register */\r
+#define _SPISR PORTIO_8(IO_BASE + 0x3) /* SPI status register */\r
+#define _SPIDR PORTIO_8(IO_BASE + 0x5) /* SPI data register */\r
+\r
+/* SPI0 Module \r
+ */ \r
+#define SPI0_BASE (IO_BASE + 0xd8)\r
+#define SPI0CR1 PORTIO_8(IO_BASE + 0xd8) /* SPI 0 control register 1 */\r
+#define SPI0CR2 PORTIO_8(IO_BASE + 0xd9) /* SPI 0 control register 2 */\r
+#define SPI0BR PORTIO_8(IO_BASE + 0xda) /* SPI 0 baud rate register */\r
+#define SPI0SR PORTIO_8(IO_BASE + 0xdb) /* SPI 0 status register */\r
+#define SPI0DR PORTIO_8(IO_BASE + 0xdd) /* SPI 0 data register */\r
+\r
+//SPInCR1\r
+#define SPIE 0x80\r
+#define SPE 0x40\r
+#define SPTIE 0x20\r
+#define MSTR 0x10\r
+#define CPOL 0x08\r
+#define CPHA 0x04\r
+#define SSOE 0x02\r
+#define LSBFE 0x01\r
+\r
+//SPInSR\r
+#define SPIF 0x80\r
+#define SPTEF 0x20\r
+#define MODF 0x10\r
+\r
+/* I2C Module \r
+ */\r
+#define IBAD PORTIO_8(IO_BASE + 0xe0) /* I2C address register */\r
+#define IBFD PORTIO_8(IO_BASE + 0xe1) /* I2C freqency divider reg */\r
+#define IBCR PORTIO_8(IO_BASE + 0xe2) /* I2C control register */\r
+#define IBSR PORTIO_8(IO_BASE + 0xe3) /* I2C status register */\r
+#define IBDR PORTIO_8(IO_BASE + 0xe4) /* I2C data register */\r
+\r
+//IBSR\r
+#define TCF 0x80\r
+#define IAAS 0x40\r
+#define IBB 0x20\r
+#define IBAL 0x10\r
+#define SRW 0x04\r
+#define IBIF 0x02\r
+#define RXAK 0x01\r
+\r
+/* BDLC Module \r
+ */\r
+#define DLCBCR1 PORTIO_8(IO_BASE + 0xe8) /* BDLC control register 1 */\r
+#define DLCBSVR PORTIO_8(IO_BASE + 0xe9) /* BDLC state vector register */\r
+#define DLCBCR2 PORTIO_8(IO_BASE + 0xea) /* BDLC control register 2 */\r
+#define DLCBDR PORTIO_8(IO_BASE + 0xeb) /* BDLC data register */\r
+#define DLCBARD PORTIO_8(IO_BASE + 0xec) /* BDLC analog round trip delay */\r
+#define DLCBRSR PORTIO_8(IO_BASE + 0xed) /* BDLC rate select register */\r
+#define DLCSCR PORTIO_8(IO_BASE + 0xee) /* BDLC control register */\r
+#define DLCBSTAT PORTIO_8(IO_BASE + 0xef) /* BDLC status register */\r
+\r
+/* SPI1 Module \r
+ */ \r
+#define SPI1_BASE (IO_BASE + 0xf0)\r
+#define SPI1CR1 PORTIO_8(IO_BASE + 0xf0) /* SPI 1 control register 1 */\r
+#define SPI1CR2 PORTIO_8(IO_BASE + 0xf1) /* SPI 1 control register 2 */\r
+#define SPI1BR PORTIO_8(IO_BASE + 0xf2) /* SPI 1 baud rate register */\r
+#define SPI1SR PORTIO_8(IO_BASE + 0xf3) /* SPI 1 status register */\r
+#define SPI1DR PORTIO_8(IO_BASE + 0xf5) /* SPI 1 data register */\r
+\r
+/* SPI2 Module \r
+ */\r
+#define SPI2_BASE (IO_BASE + 0xf8)\r
+#define SPI2CR1 PORTIO_8(IO_BASE + 0xf8) /* SPI 2 control register 1 */\r
+#define SPI2CR2 PORTIO_8(IO_BASE + 0xf9) /* SPI 2 control register 2 */\r
+#define SPI2BR PORTIO_8(IO_BASE + 0xfa) /* SPI 2 baud rate register */\r
+#define SPI2SR PORTIO_8(IO_BASE + 0xfb) /* SPI 2 status register */\r
+#define SPI2DR PORTIO_8(IO_BASE + 0xfd) /* SPI 2 data register */\r
+\r
+/* FLC Module\r
+ */\r
+#define FCLKDIV PORTIO_8(IO_BASE + 0x100) /* flash clock divider */\r
+#define FSEC PORTIO_8(IO_BASE + 0x101) /* flash security register */\r
+#define FCNFG PORTIO_8(IO_BASE + 0x103) /* flash configuration register */\r
+#define FPROT PORTIO_8(IO_BASE + 0x104) /* flash protection register */\r
+#define FSTAT PORTIO_8(IO_BASE + 0x105) /* flash status register */\r
+#define FCMD PORTIO_8(IO_BASE + 0x106) /* flash command register */\r
+\r
+/* EEPROM Module\r
+ */\r
+#define ECLKDIV PORTIO_8(IO_BASE + 0x110) /* eeprom clock divider */\r
+#define ECNFG PORTIO_8(IO_BASE + 0x113) /* eeprom configuration register */\r
+#define EPROT PORTIO_8(IO_BASE + 0x114) /* eeprom protection register */\r
+#define ESTAT PORTIO_8(IO_BASE + 0x115) /* eeprom status register */\r
+#define ECMD PORTIO_8(IO_BASE + 0x116) /* eeprom command register */\r
+\r
+/* ATD1 Module \r
+ */\r
+#define ATD1_BASE (IO_BASE + 0x120)\r
+#define ATD1CTL0 PORTIO_8(IO_BASE + 0x120) /* A/D1 control register 0 */\r
+#define ATD1CTL1 PORTIO_8(IO_BASE + 0x121) /* A/D1 control register 1 */\r
+#define ATD1CTL2 PORTIO_8(IO_BASE + 0x122) /* A/D1 control register 2 */\r
+#define ATD1CTL3 PORTIO_8(IO_BASE + 0x123) /* A/D1 control register 3 */\r
+#define ATD1CTL4 PORTIO_8(IO_BASE + 0x124) /* A/D1 control register 4 */\r
+#define ATD1CTL5 PORTIO_8(IO_BASE + 0x125) /* A/D1 control register 5 */\r
+#define ATD1STAT0 PORTIO_8(IO_BASE + 0x126) /* A/D1 status register 0 */\r
+#define ATD1STAT1 PORTIO_8(IO_BASE + 0x127) /* A/D1 status register 1 */\r
+#define ATD1TEST0 PORTIO_8(IO_BASE + 0x128) /* A/D1 test register 0 */\r
+#define ATD1TEST1 PORTIO_8(IO_BASE + 0x129) /* A/D1 test register 1 */\r
+#define ATD1DIEN PORTIO_8(IO_BASE + 0x12d) /* A/D1 interrupt enable */\r
+#define PORTAD1 PORTIO_8(IO_BASE + 0x12f) /* port AD1 data input register */\r
+#define ATD1DR0 PORTIO_16(IO_BASE + 0x130) /* A/D1 result 0 */\r
+#define ATD1DR0H PORTIO_8(IO_BASE + 0x130) /* A/D1 result 0 */\r
+#define ATD1DR1 PORTIO_16(IO_BASE + 0x132) /* A/D1 result 1 */\r
+#define ATD1DR1H PORTIO_8(IO_BASE + 0x132) /* A/D1 result 1 */\r
+#define ATD1DR2 PORTIO_16(IO_BASE + 0x134) /* A/D1 result 2 */\r
+#define ATD1DR2H PORTIO_8(IO_BASE + 0x134) /* A/D1 result 2 */\r
+#define ATD1DR3 PORTIO_16(IO_BASE + 0x136) /* A/D1 result 3 */\r
+#define ATD1DR3H PORTIO_8(IO_BASE + 0x136) /* A/D1 result 3 */\r
+#define ATD1DR4 PORTIO_16(IO_BASE + 0x138) /* A/D1 result 4 */\r
+#define ATD1DR4H PORTIO_8(IO_BASE + 0x138) /* A/D1 result 4 */\r
+#define ATD1DR5 PORTIO_16(IO_BASE + 0x13a) /* A/D1 result 5 */\r
+#define ATD1DR5H PORTIO_8(IO_BASE + 0x13a) /* A/D1 result 5 */\r
+#define ATD1DR6 PORTIO_16(IO_BASE + 0x13c) /* A/D1 result 6 */\r
+#define ATD1DR6H PORTIO_8(IO_BASE + 0x13c) /* A/D1 result 6 */\r
+#define ATD1DR7 PORTIO_16(IO_BASE + 0x13e) /* A/D1 result 7 */\r
+#define ATD1DR7H PORTIO_8(IO_BASE + 0x13e) /* A/D1 result 7 */\r
+\r
+/* CAN0 Module \r
+ */\r
+#define CAN0_BASE (IO_BASE + 0x140)\r
+#define CAN0CTL0 PORTIO_8(IO_BASE + 0x140) /* CAN0 control register 0 */\r
+#define CAN0CTL1 PORTIO_8(IO_BASE + 0x141) /* CAN0 control register 1 */\r
+#define CAN0BTR0 PORTIO_8(IO_BASE + 0x142) /* CAN0 bus timing register 0 */\r
+#define CAN0BTR1 PORTIO_8(IO_BASE + 0x143) /* CAN0 bus timing register 1 */\r
+#define CAN0RFLG PORTIO_8(IO_BASE + 0x144) /* CAN0 receiver flag register */\r
+#define CAN0RIER PORTIO_8(IO_BASE + 0x145) /* CAN0 receiver interrupt reg */\r
+#define CAN0TFLG PORTIO_8(IO_BASE + 0x146) /* CAN0 transmitter flag reg */\r
+#define CAN0TIER PORTIO_8(IO_BASE + 0x147) /* CAN0 transmitter control reg */\r
+#define CAN0TARQ PORTIO_8(IO_BASE + 0x148) /* CAN0 transmitter abort request */\r
+#define CAN0TAAK PORTIO_8(IO_BASE + 0x149) /* CAN0 transmitter abort acknowledge */\r
+#define CAN0TBSEL PORTIO_8(IO_BASE + 0x14a) /* CAN0 transmit buffer selection */\r
+#define CAN0IDAC PORTIO_8(IO_BASE + 0x14b) /* CAN0 identifier acceptance */\r
+#define CAN0RXERR PORTIO_8(IO_BASE + 0x14e) /* CAN0 receive error counter */\r
+#define CAN0TXERR PORTIO_8(IO_BASE + 0x14f) /* CAN0 transmit error counter */\r
+#define CAN0IDAR0 PORTIO_8(IO_BASE + 0x150) /* CAN0 id acceptance reg 0 */\r
+#define CAN0IDAR1 PORTIO_8(IO_BASE + 0x151) /* CAN0 id acceptance reg 1 */\r
+#define CAN0IDAR2 PORTIO_8(IO_BASE + 0x152) /* CAN0 id acceptance reg 2 */\r
+#define CAN0IDAR3 PORTIO_8(IO_BASE + 0x153) /* CAN0 id acceptance reg 3 */\r
+#define CAN0IDMR0 PORTIO_8(IO_BASE + 0x154) /* CAN0 id mask register 0 */\r
+#define CAN0IDMR1 PORTIO_8(IO_BASE + 0x155) /* CAN0 id mask register 1 */\r
+#define CAN0IDMR2 PORTIO_8(IO_BASE + 0x156) /* CAN0 id mask register 2 */\r
+#define CAN0IDMR3 PORTIO_8(IO_BASE + 0x157) /* CAN0 id mask register 3 */\r
+#define CAN0IDAR4 PORTIO_8(IO_BASE + 0x158) /* CAN0 id acceptance reg 4 */\r
+#define CAN0IDAR5 PORTIO_8(IO_BASE + 0x159) /* CAN0 id acceptance reg 5 */\r
+#define CAN0IDAR6 PORTIO_8(IO_BASE + 0x15a) /* CAN0 id acceptance reg 6 */\r
+#define CAN0IDAR7 PORTIO_8(IO_BASE + 0x15b) /* CAN0 id acceptance reg 7 */\r
+#define CAN0IDMR4 PORTIO_8(IO_BASE + 0x15c) /* CAN0 id mask register 4 */\r
+#define CAN0IDMR5 PORTIO_8(IO_BASE + 0x15d) /* CAN0 id mask register 5 */\r
+#define CAN0IDMR6 PORTIO_8(IO_BASE + 0x15e) /* CAN0 id mask register 6 */\r
+#define CAN0IDMR7 PORTIO_8(IO_BASE + 0x15f) /* CAN0 id mask register 7 */\r
+#define CAN0RXFG PORTIO_8(IO_BASE + 0x160) /* CAN0 receive buffer */\r
+#define CAN0TXFG PORTIO_8(IO_BASE + 0x170) /* CAN0 transmit buffer */\r
+\r
+/* CAN1 Module \r
+ */\r
+#define CAN1_BASE (IO_BASE + 0x180)\r
+#define CAN1CTL0 PORTIO_8(IO_BASE + 0x180) /* CAN1 control register 0 */\r
+#define CAN1CTL1 PORTIO_8(IO_BASE + 0x181) /* CAN1 control register 1 */\r
+#define CAN1BTR0 PORTIO_8(IO_BASE + 0x182) /* CAN1 bus timing register 0 */\r
+#define CAN1BTR1 PORTIO_8(IO_BASE + 0x183) /* CAN1 bus timing register 1 */\r
+#define CAN1RFLG PORTIO_8(IO_BASE + 0x184) /* CAN1 receiver flag register */\r
+#define CAN1RIER PORTIO_8(IO_BASE + 0x185) /* CAN1 receiver interrupt reg */\r
+#define CAN1TFLG PORTIO_8(IO_BASE + 0x186) /* CAN1 transmitter flag reg */\r
+#define CAN1TIER PORTIO_8(IO_BASE + 0x187) /* CAN1 transmitter control reg */\r
+#define CAN1TARQ PORTIO_8(IO_BASE + 0x188) /* CAN1 transmitter abort request */\r
+#define CAN1TAAK PORTIO_8(IO_BASE + 0x189) /* CAN1 transmitter abort acknowledge */\r
+#define CAN1TBSEL PORTIO_8(IO_BASE + 0x18a) /* CAN1 transmit buffer selection */\r
+#define CAN1IDAC PORTIO_8(IO_BASE + 0x18b) /* CAN1 identifier acceptance */\r
+#define CAN1RXERR PORTIO_8(IO_BASE + 0x18e) /* CAN1 transmitter control reg */\r
+#define CAN1TXERR PORTIO_8(IO_BASE + 0x18f) /* CAN1 transmit error counter */\r
+#define CAN1IDAR0 PORTIO_8(IO_BASE + 0x190) /* CAN1 id acceptance reg 0 */\r
+#define CAN1IDAR1 PORTIO_8(IO_BASE + 0x191) /* CAN1 id acceptance reg 1 */\r
+#define CAN1IDAR2 PORTIO_8(IO_BASE + 0x192) /* CAN1 id acceptance reg 2 */\r
+#define CAN1IDAR3 PORTIO_8(IO_BASE + 0x193) /* CAN1 id acceptance reg 3 */\r
+#define CAN1IDMR0 PORTIO_8(IO_BASE + 0x194) /* CAN1 id mask register 0 */\r
+#define CAN1IDMR1 PORTIO_8(IO_BASE + 0x195) /* CAN1 id mask register 1 */\r
+#define CAN1IDMR2 PORTIO_8(IO_BASE + 0x196) /* CAN1 id mask register 2 */\r
+#define CAN1IDMR3 PORTIO_8(IO_BASE + 0x197) /* CAN1 id mask register 3 */\r
+#define CAN1IDAR4 PORTIO_8(IO_BASE + 0x198) /* CAN1 id acceptance reg 4 */\r
+#define CAN1IDAR5 PORTIO_8(IO_BASE + 0x199) /* CAN1 id acceptance reg 5 */\r
+#define CAN1IDAR6 PORTIO_8(IO_BASE + 0x19a) /* CAN1 id acceptance reg 6 */\r
+#define CAN1IDAR7 PORTIO_8(IO_BASE + 0x19b) /* CAN1 id acceptance reg 7 */\r
+#define CAN1IDMR4 PORTIO_8(IO_BASE + 0x19c) /* CAN1 id mask register 4 */\r
+#define CAN1IDMR5 PORTIO_8(IO_BASE + 0x19d) /* CAN1 id mask register 5 */\r
+#define CAN1IDMR6 PORTIO_8(IO_BASE + 0x19e) /* CAN1 id mask register 6 */\r
+#define CAN1IDMR7 PORTIO_8(IO_BASE + 0x19f) /* CAN1 id mask register 7 */\r
+#define CAN1RXFG PORTIO_8(IO_BASE + 0x1a0) /* CAN1 receive buffer */\r
+#define CAN1TXFG PORTIO_8(IO_BASE + 0x1b0) /* CAN1 transmit buffer */\r
+\r
+/* CAN2 Module \r
+ */\r
+#define CAN2_BASE (IO_BASE + 0x1c0)\r
+#define CAN2CTL0 PORTIO_8(IO_BASE + 0x1c0) /* CAN2 control register 0 */\r
+#define CAN2CTL1 PORTIO_8(IO_BASE + 0x1c1) /* CAN2 control register 1 */\r
+#define CAN2BTR0 PORTIO_8(IO_BASE + 0x1c2) /* CAN2 bus timing register 0 */\r
+#define CAN2BTR1 PORTIO_8(IO_BASE + 0x1c3) /* CAN2 bus timing register 1 */\r
+#define CAN2RFLG PORTIO_8(IO_BASE + 0x1c4) /* CAN2 receiver flag register */\r
+#define CAN2RIER PORTIO_8(IO_BASE + 0x1c5) /* CAN2 receiver interrupt reg */\r
+#define CAN2TFLG PORTIO_8(IO_BASE + 0x1c6) /* CAN2 transmitter flag reg */\r
+#define CAN2TIER PORTIO_8(IO_BASE + 0x1c7) /* CAN2 transmitter control reg */\r
+#define CAN2TARQ PORTIO_8(IO_BASE + 0x1c8) /* CAN2 transmitter abort request */\r
+#define CAN2TAAK PORTIO_8(IO_BASE + 0x1c9) /* CAN2 transmitter abort acknowledge */\r
+#define CAN2TBSEL PORTIO_8(IO_BASE + 0x1ca) /* CAN2 transmit buffer selection */\r
+#define CAN2IDAC PORTIO_8(IO_BASE + 0x1cb) /* CAN2 identifier acceptance */\r
+#define CAN2RXERR PORTIO_8(IO_BASE + 0x1ce) /* CAN2 transmitter control reg */\r
+#define CAN2TXERR PORTIO_8(IO_BASE + 0x1cf) /* CAN2 transmit error counter */\r
+#define CAN2IDAR0 PORTIO_8(IO_BASE + 0x1d0) /* CAN2 id acceptance reg 0 */\r
+#define CAN2IDAR1 PORTIO_8(IO_BASE + 0x1d1) /* CAN2 id acceptance reg 1 */\r
+#define CAN2IDAR2 PORTIO_8(IO_BASE + 0x1d2) /* CAN2 id acceptance reg 2 */\r
+#define CAN2IDAR3 PORTIO_8(IO_BASE + 0x1d3) /* CAN2 id acceptance reg 3 */\r
+#define CAN2IDMR0 PORTIO_8(IO_BASE + 0x1d4) /* CAN2 id mask register 0 */\r
+#define CAN2IDMR1 PORTIO_8(IO_BASE + 0x1d5) /* CAN2 id mask register 1 */\r
+#define CAN2IDMR2 PORTIO_8(IO_BASE + 0x1d6) /* CAN2 id mask register 2 */\r
+#define CAN2IDMR3 PORTIO_8(IO_BASE + 0x1d7) /* CAN2 id mask register 3 */\r
+#define CAN2IDAR4 PORTIO_8(IO_BASE + 0x1d8) /* CAN2 id acceptance reg 4 */\r
+#define CAN2IDAR5 PORTIO_8(IO_BASE + 0x1d9) /* CAN2 id acceptance reg 5 */\r
+#define CAN2IDAR6 PORTIO_8(IO_BASE + 0x1da) /* CAN2 id acceptance reg 6 */\r
+#define CAN2IDAR7 PORTIO_8(IO_BASE + 0x1db) /* CAN2 id acceptance reg 7 */\r
+#define CAN2IDMR4 PORTIO_8(IO_BASE + 0x1dc) /* CAN2 id mask register 4 */\r
+#define CAN2IDMR5 PORTIO_8(IO_BASE + 0x1dd) /* CAN2 id mask register 5 */\r
+#define CAN2IDMR6 PORTIO_8(IO_BASE + 0x1de) /* CAN2 id mask register 6 */\r
+#define CAN2IDMR7 PORTIO_8(IO_BASE + 0x1df) /* CAN2 id mask register 7 */\r
+#define CAN2RXFG PORTIO_8(IO_BASE + 0x1e0) /* CAN2 receive buffer */\r
+#define CAN2TXFG PORTIO_8(IO_BASE + 0x1f0) /* CAN2 transmit buffer */\r
+\r
+/* CAN3 Module \r
+ */\r
+#define CAN3_BASE (IO_BASE + 0x200)\r
+#define CAN3CTL0 PORTIO_8(IO_BASE + 0x200) /* CAN3 control register 0 */\r
+#define CAN3CTL1 PORTIO_8(IO_BASE + 0x201) /* CAN3 control register 1 */\r
+#define CAN3BTR0 PORTIO_8(IO_BASE + 0x202) /* CAN3 bus timing register 0 */\r
+#define CAN3BTR1 PORTIO_8(IO_BASE + 0x203) /* CAN3 bus timing register 1 */\r
+#define CAN3RFLG PORTIO_8(IO_BASE + 0x204) /* CAN3 receiver flag register */\r
+#define CAN3RIER PORTIO_8(IO_BASE + 0x205) /* CAN3 receiver interrupt reg */\r
+#define CAN3TFLG PORTIO_8(IO_BASE + 0x206) /* CAN3 transmitter flag reg */\r
+#define CAN3TIER PORTIO_8(IO_BASE + 0x207) /* CAN3 transmitter control reg */\r
+#define CAN3TARQ PORTIO_8(IO_BASE + 0x208) /* CAN3 transmitter abort request */\r
+#define CAN3TAAK PORTIO_8(IO_BASE + 0x209) /* CAN3 transmitter abort acknowledge */\r
+#define CAN3TBSEL PORTIO_8(IO_BASE + 0x20a) /* CAN3 transmit buffer selection */\r
+#define CAN3IDAC PORTIO_8(IO_BASE + 0x20b) /* CAN3 identifier acceptance */\r
+#define CAN3RXERR PORTIO_8(IO_BASE + 0x20e) /* CAN3 transmitter control reg */\r
+#define CAN3TXERR PORTIO_8(IO_BASE + 0x20f) /* CAN3 transmit error counter */\r
+#define CAN3IDAR0 PORTIO_8(IO_BASE + 0x210) /* CAN3 id acceptance reg 0 */\r
+#define CAN3IDAR1 PORTIO_8(IO_BASE + 0x211) /* CAN3 id acceptance reg 1 */\r
+#define CAN3IDAR2 PORTIO_8(IO_BASE + 0x212) /* CAN3 id acceptance reg 2 */\r
+#define CAN3IDAR3 PORTIO_8(IO_BASE + 0x213) /* CAN3 id acceptance reg 3 */\r
+#define CAN3IDMR0 PORTIO_8(IO_BASE + 0x214) /* CAN3 id mask register 0 */\r
+#define CAN3IDMR1 PORTIO_8(IO_BASE + 0x215) /* CAN3 id mask register 1 */\r
+#define CAN3IDMR2 PORTIO_8(IO_BASE + 0x216) /* CAN3 id mask register 2 */\r
+#define CAN3IDMR3 PORTIO_8(IO_BASE + 0x217) /* CAN3 id mask register 3 */\r
+#define CAN3IDAR4 PORTIO_8(IO_BASE + 0x218) /* CAN3 id acceptance reg 4 */\r
+#define CAN3IDAR5 PORTIO_8(IO_BASE + 0x219) /* CAN3 id acceptance reg 5 */\r
+#define CAN3IDAR6 PORTIO_8(IO_BASE + 0x21a) /* CAN3 id acceptance reg 6 */\r
+#define CAN3IDAR7 PORTIO_8(IO_BASE + 0x21b) /* CAN3 id acceptance reg 7 */\r
+#define CAN3IDMR4 PORTIO_8(IO_BASE + 0x21c) /* CAN3 id mask register 4 */\r
+#define CAN3IDMR5 PORTIO_8(IO_BASE + 0x21d) /* CAN3 id mask register 5 */\r
+#define CAN3IDMR6 PORTIO_8(IO_BASE + 0x21e) /* CAN3 id mask register 6 */\r
+#define CAN3IDMR7 PORTIO_8(IO_BASE + 0x21f) /* CAN3 id mask register 7 */\r
+#define CAN3RXFG PORTIO_8(IO_BASE + 0x220) /* CAN3 receive buffer */\r
+#define CAN3TXFG PORTIO_8(IO_BASE + 0x230) /* CAN3 transmit buffer */\r
+\r
+/* PIM\r
+ */\r
+\r
+/*Port T register offsets\r
+*/\r
+#define PTT PORTIO_8(IO_BASE + 0x240) /* port T data register */\r
+#define PTIT PORTIO_8(IO_BASE + 0x241) /* port T input register */\r
+#define DDRT PORTIO_8(IO_BASE + 0x242) /* port T data direction */\r
+#define RDRT PORTIO_8(IO_BASE + 0x243) /* port T reduce drive */\r
+#define PERT PORTIO_8(IO_BASE + 0x244) /* port T pull enable */\r
+#define PPST PORTIO_8(IO_BASE + 0x245) /* port T polarity select */\r
+\r
+/*Port S\r
+ */\r
+#define PTS PORTIO_8(IO_BASE + 0x248) /* port S data register */\r
+#define PTIS PORTIO_8(IO_BASE + 0x249) /* port S input register */\r
+#define DDRS PORTIO_8(IO_BASE + 0x24a) /* port S data direction */\r
+#define RDRS PORTIO_8(IO_BASE + 0x24b) /* port S reduce drive */\r
+#define PERS PORTIO_8(IO_BASE + 0x24c) /* port S pull enable */\r
+#define PPSS PORTIO_8(IO_BASE + 0x24d) /* port S polarity select */\r
+#define WOMS PORTIO_8(IO_BASE + 0x24e) /* port S wired-or mode */\r
+\r
+/* Port M\r
+ */\r
+#define PTM PORTIO_8(IO_BASE + 0x250) /* port M data register */\r
+#define PTIM PORTIO_8(IO_BASE + 0x251) /* port M input register */\r
+#define DDRM PORTIO_8(IO_BASE + 0x252) /* port M data direction */\r
+#define RDRM PORTIO_8(IO_BASE + 0x253) /* port M reduce drive */\r
+#define PERM PORTIO_8(IO_BASE + 0x254) /* port M pull enable */\r
+#define PPSM PORTIO_8(IO_BASE + 0x255) /* port M polarity select */\r
+#define WOMM PORTIO_8(IO_BASE + 0x256) /* port M wired-or mode */\r
+\r
+/* Port P\r
+ */\r
+#define PTP PORTIO_8(IO_BASE + 0x258) /* port P data register */\r
+#define PTIP PORTIO_8(IO_BASE + 0x259) /* port P input register */\r
+#define DDRP PORTIO_8(IO_BASE + 0x25a) /* port P data direction */\r
+#define RDRP PORTIO_8(IO_BASE + 0x25b) /* port P reduce drive */\r
+#define PERP PORTIO_8(IO_BASE + 0x25c) /* port P pull enable */\r
+#define PPSP PORTIO_8(IO_BASE + 0x25d) /* port P polarity select */\r
+#define PIEP PORTIO_8(IO_BASE + 0x25e) /* port P interrupt enable */\r
+#define PIFP PORTIO_8(IO_BASE + 0x25f) /* port P interrupt flag */\r
+\r
+/* Port H\r
+ */\r
+#define PTH PORTIO_8(IO_BASE + 0x260) /* port H data register */\r
+#define PTIH PORTIO_8(IO_BASE + 0x261) /* port H input register */\r
+#define DDRH PORTIO_8(IO_BASE + 0x262) /* port H data direction */\r
+#define RDRH PORTIO_8(IO_BASE + 0x263) /* port H reduce drive */\r
+#define PERH PORTIO_8(IO_BASE + 0x264) /* port H pull enable */\r
+#define PPSH PORTIO_8(IO_BASE + 0x265) /* port H polarity select */\r
+#define PIEH PORTIO_8(IO_BASE + 0x266) /* port H interrupt enable */\r
+#define PIFH PORTIO_8(IO_BASE + 0x267) /* port H interrupt flag */\r
+\r
+/* Port J\r
+ */\r
+#define PTJ PORTIO_8(IO_BASE + 0x268) /* port J data register */\r
+#define PTIJ PORTIO_8(IO_BASE + 0x269) /* port J input register */\r
+#define DDRJ PORTIO_8(IO_BASE + 0x26a) /* port J data direction */\r
+#define RDRJ PORTIO_8(IO_BASE + 0x26b) /* port J reduce drive */\r
+#define PERJ PORTIO_8(IO_BASE + 0x26c) /* port J pull enable */\r
+#define PPSJ PORTIO_8(IO_BASE + 0x26d) /* port J polarity select */\r
+#define PIEJ PORTIO_8(IO_BASE + 0x26e) /* port J interrupt enable */\r
+#define PIFJ PORTIO_8(IO_BASE + 0x26f) /* port J interrupt flag */\r
+/*PIM end\r
+*/\r
+\r
+\r
+/* CAN4 Module \r
+ */\r
+#define CAN4_BASE (IO_BASE + 0x280)\r
+#define CAN4CTL0 PORTIO_8(IO_BASE + 0x280) /* CAN4 control register 0 */\r
+#define CAN4CTL1 PORTIO_8(IO_BASE + 0x281) /* CAN4 control register 1 */\r
+#define CAN4BTR0 PORTIO_8(IO_BASE + 0x282) /* CAN4 bus timing register 0 */\r
+#define CAN4BTR1 PORTIO_8(IO_BASE + 0x283) /* CAN4 bus timing register 1 */\r
+#define CAN4RFLG PORTIO_8(IO_BASE + 0x284) /* CAN4 receiver flag register */\r
+#define CAN4RIER PORTIO_8(IO_BASE + 0x285) /* CAN4 receiver interrupt reg */\r
+#define CAN4TFLG PORTIO_8(IO_BASE + 0x286) /* CAN4 transmitter flag reg */\r
+#define CAN4TIER PORTIO_8(IO_BASE + 0x287) /* CAN4 transmitter control reg */\r
+#define CAN4TARQ PORTIO_8(IO_BASE + 0x288) /* CAN4 transmitter abort request */\r
+#define CAN4TAAK PORTIO_8(IO_BASE + 0x289) /* CAN4 transmitter abort acknowledge */\r
+#define CAN4TBSEL PORTIO_8(IO_BASE + 0x28a) /* CAN4 transmit buffer selection */\r
+#define CAN4IDAC PORTIO_8(IO_BASE + 0x28b) /* CAN4 identifier acceptance */\r
+#define CAN4RXERR PORTIO_8(IO_BASE + 0x28e) /* CAN4 transmitter control reg */\r
+#define CAN4TXERR PORTIO_8(IO_BASE + 0x28f) /* CAN4 transmit error counter */\r
+#define CAN4IDAR0 PORTIO_8(IO_BASE + 0x290) /* CAN4 id acceptance reg 0 */\r
+#define CAN4IDAR1 PORTIO_8(IO_BASE + 0x291) /* CAN4 id acceptance reg 1 */\r
+#define CAN4IDAR2 PORTIO_8(IO_BASE + 0x292) /* CAN4 id acceptance reg 2 */\r
+#define CAN4IDAR3 PORTIO_8(IO_BASE + 0x293) /* CAN4 id acceptance reg 3 */\r
+#define CAN4IDMR0 PORTIO_8(IO_BASE + 0x294) /* CAN4 id mask register 0 */\r
+#define CAN4IDMR1 PORTIO_8(IO_BASE + 0x295) /* CAN4 id mask register 1 */\r
+#define CAN4IDMR2 PORTIO_8(IO_BASE + 0x296) /* CAN4 id mask register 2 */\r
+#define CAN4IDMR3 PORTIO_8(IO_BASE + 0x297) /* CAN4 id mask register 3 */\r
+#define CAN4IDAR4 PORTIO_8(IO_BASE + 0x298) /* CAN4 id acceptance reg 4 */\r
+#define CAN4IDAR5 PORTIO_8(IO_BASE + 0x299) /* CAN4 id acceptance reg 5 */\r
+#define CAN4IDAR6 PORTIO_8(IO_BASE + 0x29a) /* CAN4 id acceptance reg 6 */\r
+#define CAN4IDAR7 PORTIO_8(IO_BASE + 0x29b) /* CAN4 id acceptance reg 7 */\r
+#define CAN4IDMR4 PORTIO_8(IO_BASE + 0x29c) /* CAN4 id mask register 4 */\r
+#define CAN4IDMR5 PORTIO_8(IO_BASE + 0x29d) /* CAN4 id mask register 5 */\r
+#define CAN4IDMR6 PORTIO_8(IO_BASE + 0x29e) /* CAN4 id mask register 6 */\r
+#define CAN4IDMR7 PORTIO_8(IO_BASE + 0x29f) /* CAN4 id mask register 7 */\r
+#define CAN4RXFG PORTIO_8(IO_BASE + 0x2a0) /* CAN4 receive buffer */\r
+#define CAN4TXFG PORTIO_8(IO_BASE + 0x2b0) /* CAN4 transmit buffer */\r
+\r
+\r
+#endif\r
+\r
--- /dev/null
+/* m68hc11/sio.h -- Utility methods to read/write the SIO\r
+ Copyright 1999, 2000, 2003 Free Software Foundation, Inc.\r
+ Written by Stephane Carrez (stcarrez@nerim.fr)\r
+\r
+This file is part of GDB, GAS, and the GNU binutils.\r
+\r
+GDB, GAS, and the GNU binutils are free software; you can redistribute\r
+them and/or modify them under the terms of the GNU General Public\r
+License as published by the Free Software Foundation; either version\r
+1, or (at your option) any later version.\r
+\r
+GDB, GAS, and the GNU binutils are distributed in the hope that they\r
+will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See\r
+the GNU General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with this file; see the file COPYING. If not, write to the Free\r
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _M68HC12_SIO_H\r
+#define _M68HC12_SIO_H\r
+\r
+#include <sys/param.h>\r
+#include <sys/ports.h>\r
+\r
+/* Initialize SCI serial port to default baudrate and enable. */\r
+extern inline void\r
+serial_init (void)\r
+{\r
+ SCIBD = M6811_DEF_BAUD;\r
+ SCICR1 = 0x00; //typical 8 bit\r
+ SCICR2 = 0x0c; //Enable sci for polling\r
+}\r
+\r
+/* Return != 0 if there is something to read on the serial line. */\r
+extern inline unsigned char\r
+serial_receive_pending (void)\r
+{\r
+ return SCISR1 & RDRF;\r
+}\r
+\r
+/* Wait until the SIO has finished to send the character. */\r
+extern inline void\r
+serial_flush (void)\r
+{\r
+ while (!(SCISR1 & TDRE))\r
+ cop_optional_reset ();\r
+}\r
+\r
+/* Return != 0 if serial port is ready to send another char. */\r
+extern inline unsigned char\r
+serial_send_ready (void)\r
+{\r
+ return SCISR1 & TDRE;\r
+}\r
+\r
+/* Send the character on the serial line. */\r
+extern inline void\r
+serial_send (char c)\r
+{\r
+ serial_flush ();\r
+ SCIDRL = c;\r
+ SCICR2 |= (1<<3);\r
+}\r
+\r
+/* Wait for a character on the serial line and return it. */\r
+extern inline unsigned char\r
+serial_recv (void)\r
+{\r
+ while (!(SCISR1 & RDRF))\r
+ cop_optional_reset ();\r
+\r
+ return SCIDRL;\r
+}\r
+\r
+extern void serial_print (const char *msg);\r
+extern void serial_getline (char *buf);\r
+\r
+#endif /* _M68HC11_SIO_H */\r
+\r
--- /dev/null
+/** \r
+ * sci.c controls SCI for GCC/HCS12 version of FreeRTOS Demo\r
+ * To replace CodeWarrior Cpu.h\r
+ *\r
+ * Author Jefferson L Smith, Robotronics Inc.\r
+ */\r
+\r
+#ifndef __Cpu\r
+#define __Cpu\r
+\r
+/*Types definition*/\r
+typedef unsigned char bool;\r
+typedef unsigned char byte;\r
+typedef unsigned int word;\r
+typedef unsigned long dword;\r
+\r
+#define ATTR_INT __attribute__((interrupt))\r
+#define ATTR_FAR __attribute__((far))\r
+#define ATTR_NEAR __attribute__((near))\r
+#define ATTR_BANK0 __attribute__((far,section (".bank0")))\r
+#define ATTR_BANK1 __attribute__((far,section (".bank1")))\r
+#define ATTR_BANK2 __attribute__((far,section (".bank2")))\r
+#define ATTR_BANK3 __attribute__((far,section (".bank3")))\r
+#define ATTR_BANK4 __attribute__((far,section (".bank4")))\r
+#define ATTR_BANK5 __attribute__((far,section (".bank5")))\r
+#define ATTR_BANK6 __attribute__((far,section (".bank6")))\r
+#define ATTR_BANK7 __attribute__((far,section (".bank7")))\r
+#define ATTR_BANK8 __attribute__((far,section (".bank8")))\r
+#define ATTR_BANK9 __attribute__((far,section (".bank9")))\r
+#define ATTR_BANK10 __attribute__((far,section (".bank10")))\r
+#define ATTR_BANK11 __attribute__((far,section (".bank11")))\r
+#define ATTR_BANK12 __attribute__((far,section (".bank12")))\r
+#define ATTR_BANK13 __attribute__((far,section (".bank13")))\r
+\r
+#include "PE_Error.h"\r
+#include <sys/param.h>\r
+#include <sys/ports.h>\r
+\r
+#endif /* ifndef __Cpu */\r
--- /dev/null
+/* gelfunc.c -- functions from GEL 1.6\r
+ Author Jefferson Smith, Robotronics Inc.\r
+\r
+*/\r
+\r
+#include "asm-m68hcs12/ports_def.h"\r
+void cop_reset (void);\r
+void cop_optional_reset (void);\r
+\r
+/* Reset the COP. */\r
+void\r
+cop_reset (void)\r
+{\r
+ ARMCOP = 0x55;\r
+ ARMCOP = 0xAA;\r
+}\r
+\r
+void\r
+cop_optional_reset (void)\r
+{\r
+#if defined(M6811_USE_COP) && M6811_USE_COP == 1\r
+ cop_reset ();\r
+#endif\r
+}\r
+\r
--- /dev/null
+/* Linker script for MC689S12DP256 Flash \r
+ rom banks.\r
+ \r
+ Author Jefferson L Smith; Robotronics, Inc. 2006\r
+ */\r
+OUTPUT_FORMAT("elf32-m68hc12", "elf32-m68hc12",\r
+ "elf32-m68hc12")\r
+OUTPUT_ARCH(m68hc12)\r
+ENTRY(_start)\r
+\r
+/* Get memory banks definition from some user configuration file.\r
+ This file must be located in some linker directory (search path\r
+ with -L<dir>). See fixed memory banks emulation script. */\r
+INCLUDE memory.x;\r
+\r
+SECTIONS\r
+{\r
+ /* Concatenate .page0 sections. Put them in the page0 memory bank\r
+ unless we are creating a relocatable file. */\r
+ .page0 :\r
+ {\r
+ *(.page0)\r
+ } > page0\r
+ \r
+ /* PPAGE memory banks */\r
+\r
+ .bank0 :\r
+ {\r
+ *(.bank0)\r
+ . = ALIGN(2);\r
+ } > bank0 =0xff\r
+ .bank1 :\r
+ {\r
+ *(.bank1)\r
+ . = ALIGN(2);\r
+ } > bank1 =0xff\r
+ .bank2 :\r
+ {\r
+ *(.bank2)\r
+ . = ALIGN(2);\r
+ } > bank2 =0xff\r
+ .bank3 :\r
+ {\r
+ *(.bank3)\r
+ . = ALIGN(2);\r
+ } > bank3 =0xff\r
+ .bank4 :\r
+ {\r
+ *(.bank4)\r
+ . = ALIGN(2);\r
+ } > bank4 =0xff\r
+ .bank5 :\r
+ {\r
+ *(.bank5)\r
+ . = ALIGN(2);\r
+ } > bank5 =0xff\r
+ .bank6 :\r
+ {\r
+ *(.bank6)\r
+ . = ALIGN(2);\r
+ } > bank6 =0xff\r
+ .bank7 :\r
+ {\r
+ *(.bank7)\r
+ . = ALIGN(2);\r
+ } > bank7 =0xff\r
+ .bank8 :\r
+ {\r
+ *(.bank8)\r
+ . = ALIGN(2);\r
+ } > bank8 =0xff\r
+ .bank9 :\r
+ {\r
+ *(.bank9)\r
+ . = ALIGN(2);\r
+ } > bank9 =0xff\r
+ .bank10 :\r
+ {\r
+ *(.bank10)\r
+ . = ALIGN(2);\r
+ } > bank10 =0xff\r
+ .bank11 :\r
+ {\r
+ *(.bank11)\r
+ . = ALIGN(2);\r
+ } > bank11 =0xff\r
+ .bank12 :\r
+ {\r
+ *(.bank12)\r
+ . = ALIGN(2);\r
+ } > bank12 =0xff\r
+ .bank13 :\r
+ {\r
+ *(.bank13)\r
+ . = ALIGN(2);\r
+ } > bank13 =0xff\r
+ \r
+ /* Start of text section. */\r
+ .text : \r
+ {\r
+ /* Put startup code at beginning so that _start keeps same address. */\r
+ /* Startup code. */\r
+ KEEP (*(.install0)) /* Section should setup the stack pointer. */\r
+ KEEP (*(.install1)) /* Place holder for applications. */\r
+ KEEP (*(.install2)) /* Optional installation of data sections in RAM. */\r
+ KEEP (*(.install3)) /* Place holder for applications. */\r
+ KEEP (*(.install4)) /* Section that calls the main. */\r
+ *(.init)\r
+ *(.text)\r
+ *(.text.*)\r
+ *(.text_c)\r
+ /* .gnu.warning sections are handled specially by elf32.em. */\r
+ *(.gnu.warning)\r
+ *(.gnu.linkonce.t.*)\r
+ *(.tramp)\r
+ *(.tramp.*)\r
+ /* Finish code. */\r
+ KEEP (*(.fini0)) /* Beginning of finish code (_exit symbol). */\r
+ KEEP (*(.fini1)) /* Place holder for applications. */\r
+ KEEP (*(.fini2)) /* C++ destructors. */\r
+ KEEP (*(.fini3)) /* Place holder for applications. */\r
+ KEEP (*(.fini4)) /* Runtime exit. */\r
+ _etext = .;\r
+ PROVIDE (etext = .);\r
+ . = ALIGN(2);\r
+ } > text AT>bank14 =0xff\r
+ \r
+ .text_h : \r
+ {\r
+ *(.text_h) /* Bootloader; high Flash area unbanked */\r
+ . = ALIGN(2);\r
+ } > text_h AT>bank15 =0xff\r
+ .rodata : \r
+ {\r
+ *(.rodata)\r
+ *(.rodata.*)\r
+ *(.gnu.linkonce.r*)\r
+ . = ALIGN(2);\r
+ } > text_h AT>bank15 =0xff\r
+ .eh_frame : \r
+ {\r
+ KEEP (*(.eh_frame))\r
+ . = ALIGN(2);\r
+ } > text_h AT>bank15 =0xff\r
+ \r
+ /* Constructor and destructor tables are in ROM. */\r
+ .ctors : \r
+ {\r
+ PROVIDE (__CTOR_LIST__ = .);\r
+ KEEP (*(.ctors))\r
+ PROVIDE(__CTOR_END__ = .);\r
+ . = ALIGN(2);\r
+ } > text_h AT>bank15 =0xff\r
+ .dtors : \r
+ {\r
+ PROVIDE(__DTOR_LIST__ = .);\r
+ KEEP (*(.dtors))\r
+ PROVIDE(__DTOR_END__ = .);\r
+ . = ALIGN(2);\r
+ } > text_h AT>bank15 =0xff\r
+ \r
+ /* Start of the data section image in ROM. */\r
+ __data_image = .;\r
+ PROVIDE (__data_image = .);\r
+ \r
+ /* All read-only sections that normally go in PROM must be above.\r
+ We construct the DATA image section in PROM at end of all these\r
+ read-only sections. The data image must be copied at init time.\r
+ Refer to GNU ld, Section 3.6.8.2 Output Section LMA. */\r
+ .data :\r
+ {\r
+ __data_section_start = .;\r
+ PROVIDE (__data_section_start = .);\r
+ *(.sdata)\r
+ *(.data)\r
+ *(.data.*)\r
+ *(.data1)\r
+ *(.gnu.linkonce.d.*)\r
+ CONSTRUCTORS\r
+ _edata = .;\r
+ PROVIDE (edata = .);\r
+ . = ALIGN(2);\r
+ } > data AT>bank15 =0xff\r
+ __data_section_size = SIZEOF(.data);\r
+ __data_image_end = __data_image + __data_section_size;\r
+ PROVIDE (__data_section_size = SIZEOF(.data));\r
+ /* .install :\r
+ {\r
+ . = _data_image_end;\r
+ } > text */\r
+ /* Relocation for some bss and data sections. */\r
+ .softregs :\r
+ {\r
+ __softregs_section_start = .;\r
+ *(.softregs)\r
+ __softregs_section_end = .;\r
+ } > data\r
+ __softregs_section_size = SIZEOF(.softregs); \r
+ .bss :\r
+ {\r
+ __bss_start = .;\r
+ *(.sbss)\r
+ *(.scommon)\r
+ *(.dynbss)\r
+ *(.bss)\r
+ *(.bss.*)\r
+ *(.gnu.linkonce.b.*)\r
+ *(COMMON)\r
+ PROVIDE (_end = .);\r
+ } > data\r
+ __bss_size = SIZEOF(.bss);\r
+ PROVIDE (__bss_size = SIZEOF(.bss));\r
+ .eeprom :\r
+ {\r
+ *(.eeprom)\r
+ *(.eeprom.*)\r
+ . = ALIGN(2);\r
+ } > eeprom =0xff\r
+\r
+ /* If the 'vectors_addr' symbol is defined, it indicates the start address\r
+ of interrupt vectors. This depends on the 9S12 operating mode:\r
+ Addr\r
+ Hardware location LMA 0x10ff80, mirror 0xff80\r
+ Called by dbug12 LMA 0x10ef80, mirror 0xef80\r
+ Ram called by dbug12 0x3e00\r
+ The default vectors address is (LMA) 0x10ff80. This can be overriden\r
+ with the '-defsym vectors_addr=0x...' ld option.\r
+ */\r
+ PROVIDE (_vectors_addr = DEFINED (vectors_addr) ? vectors_addr : 0x10ff80);\r
+ .vectors DEFINED (vectors_addr) ? vectors_addr : 0x10ff80 :\r
+ {\r
+ KEEP (*(.vectors))\r
+ }\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0.\r
+ Treatment of DWARF debug section must be at end of the linker\r
+ script to avoid problems when there are undefined symbols. It's necessary\r
+ to avoid that the DWARF section is relocated before such undefined\r
+ symbols are found. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+}\r
--- /dev/null
+\r
+/*\r
+ FreeRTOS V3.2.3 - Copyright (C) 2003-2005 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ *\r
+ * main() creates all the demo application tasks, then starts the scheduler.\r
+ * The WEB documentation provides more details of the demo application tasks.\r
+ *\r
+ * main.c also creates a task called "Check". This only executes every three \r
+ * seconds but has the highest priority so is guaranteed to get processor time. \r
+ * Its main function is to check that all the other tasks are still operational.\r
+ * Each task (other than the "flash" tasks) maintains a unique count that is \r
+ * incremented each time the task successfully completes its function. Should \r
+ * any error occur within such a task the count is permanently halted. The \r
+ * check task inspects the count of each task to ensure it has changed since\r
+ * the last time the check task executed. If all the count variables have \r
+ * changed all the tasks are still executing error free, and the check task\r
+ * toggles the onboard LED. Should any task contain an error at any time \r
+ * the LED toggle rate will change from 3 seconds to 500ms.\r
+ *\r
+ * This file also includes the functionality implemented within the \r
+ * standard demo application file integer.c. This is done to demonstrate the\r
+ * use of an idle hook. See the documentation within integer.c for the \r
+ * rationale of the integer task functionality.\r
+ * */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+#include "cpu.h"\r
+\r
+/* special prototypes for memory-banked functions */\r
+void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xArePollingQueuesStillRunning( void );\r
+\r
+/* Demo application includes. */\r
+#include "flash.h"\r
+#include "PollQ.h"\r
+#include "dynamic.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+#include "BlockQ.h"\r
+#include "integer.h"\r
+#include "death.h"\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ Definitions.\r
+-----------------------------------------------------------*/\r
+\r
+/* Priorities assigned to demo application tasks. */\r
+#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* LED that is toggled by the check task. The check task periodically checks\r
+that all the other tasks are operating without error. If no errors are found\r
+the LED is toggled with mainCHECK_PERIOD frequency. If an error is found \r
+then the toggle rate increases to mainERROR_CHECK_PERIOD. */\r
+#define mainCHECK_TASK_LED ( 7 )\r
+#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
+#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* The constants used in the idle task calculation. */\r
+#define intgCONST1 ( ( portLONG ) 123 )\r
+#define intgCONST2 ( ( portLONG ) 234567 )\r
+#define intgCONST3 ( ( portLONG ) -3 )\r
+#define intgCONST4 ( ( portLONG ) 7 )\r
+#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )\r
+\r
+\r
+/* Baud rate used by the serial port tasks (ComTest tasks).\r
+IMPORTANT: The function COM0_SetBaudRateValue() which is generated by the\r
+Processor Expert is used to set the baud rate. As configured in the FreeRTOS\r
+download this value must be one of the following:\r
+\r
+0 to configure for 38400 baud.\r
+1 to configure for 19200 baud.\r
+2 to configure for 9600 baud.\r
+3 to configure for 4800 baud. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 2 )\r
+\r
+/* LED used by the serial port tasks. This is toggled on each character Tx,\r
+and mainCOM_TEST_LED + 1 is toggles on each character Rx. */\r
+#define mainCOM_TEST_LED ( 3 )\r
+\r
+/*-----------------------------------------------------------\r
+ Local functions prototypes.\r
+-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The 'Check' task function. See the explanation at the top of the file.\r
+ */\r
+static void ATTR_BANK1 vErrorChecks( void* pvParameters );\r
+\r
+/*\r
+ * The idle task hook - in which the integer task is implemented. See the\r
+ * explanation at the top of the file.\r
+ */\r
+void ATTR_BANK0 vApplicationIdleHook( void );\r
+\r
+/*\r
+ * Checks the unique counts of other tasks to ensure they are still operational.\r
+ */\r
+static portLONG ATTR_BANK0 prvCheckOtherTasksAreStillRunning( void );\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ Local variables.\r
+-----------------------------------------------------------*/\r
+\r
+/* A few tasks are defined within this file. This flag is used to indicate\r
+their status. If an error is detected in one of the locally defined tasks then\r
+this flag is set to pdTRUE. */\r
+portBASE_TYPE xLocalError = pdFALSE;\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called from startup. */\r
+int ATTR_BANK0 main ( void )\r
+{\r
+ /* Start some of the standard demo tasks. */\r
+ vStartLEDFlashTasks( mainFLASH_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ \r
+ /* Start the locally defined tasks. There is also a task implemented as\r
+ the idle hook. */\r
+ xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ \r
+ /* Must be the last demo created. */\r
+ vCreateSuicidalTasks( mainDEATH_PRIORITY );\r
+\r
+ /* All the tasks have been created - start the scheduler. */\r
+ vTaskStartScheduler();\r
+ \r
+ /* Should not reach here! */\r
+ for( ;; );\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vErrorChecks( void *pvParameters )\r
+{\r
+portTickType xDelayPeriod = mainCHECK_PERIOD;\r
+portTickType xLastWakeTime;\r
+\r
+ /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()\r
+ functions correctly. */\r
+ xLastWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. The delay period is \r
+ shorter following an error. */\r
+ vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );\r
+\r
+ /* Check all the demo application tasks are executing without \r
+ error. If an error is found the delay period is shortened - this\r
+ has the effect of increasing the flash rate of the 'check' task\r
+ LED. */\r
+ if( prvCheckOtherTasksAreStillRunning() == pdFAIL )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash faster. */\r
+ xDelayPeriod = mainERROR_CHECK_PERIOD;\r
+ }\r
+\r
+ /* Toggle the LED each cycle round. */\r
+ vParTestToggleLED( mainCHECK_TASK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portLONG prvCheckOtherTasksAreStillRunning( void )\r
+{\r
+portBASE_TYPE xAllTasksPassed = pdPASS;\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFAIL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFAIL;\r
+ }\r
+\r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFALSE;\r
+ }\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFALSE;\r
+ }\r
+ \r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFALSE;\r
+ } \r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ xAllTasksPassed = pdFALSE;\r
+ }\r
+\r
+ /* Also check the status flag for the tasks defined within this function. */\r
+ if( xLocalError != pdFALSE )\r
+ {\r
+ xAllTasksPassed = pdFAIL;\r
+ }\r
+ \r
+ return xAllTasksPassed;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+/* This variable is effectively set to a constant so it is made volatile to\r
+ensure the compiler does not just get rid of it. */\r
+volatile portLONG lValue;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+\r
+ /* Perform the calculation. This will store partial value in\r
+ registers, resulting in a good test of the context switch mechanism. */\r
+ lValue = intgCONST1;\r
+ lValue += intgCONST2;\r
+ lValue *= intgCONST3;\r
+ lValue /= intgCONST4;\r
+\r
+ /* Did we perform the calculation correctly with no corruption? */\r
+ if( lValue != intgEXPECTED_ANSWER )\r
+ {\r
+ /* Error! */\r
+ portENTER_CRITICAL();\r
+ xLocalError = pdTRUE;\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ /* Yield in case cooperative scheduling is being used. */\r
+ #if configUSE_PREEMPTION == 0\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/* Flash Memory Banks\r
+ For Wytec Dragon12, Technological Arts Adapt9S12DP256\r
+ with DBug12 v4 bootloader\r
+ \r
+ Author Jefferson L Smith; Robotronics, Inc.\r
+ */\r
+\r
+MEMORY\r
+{\r
+ page0 (rwx) : ORIGIN = 0x0, LENGTH = 256\r
+\r
+ /* RAM */\r
+ data (rwx) : ORIGIN = 0x1000, LENGTH = 12k\r
+\r
+ eeprom (rx): ORIGIN = 0x0400, LENGTH = 3k\r
+ text (rx) : ORIGIN = 0x4000, LENGTH = 16k\r
+ \r
+ /* high fixed bank, reserve 0x100 vectors and security. */\r
+ text_h (rx) : ORIGIN = 0xc000, LENGTH = 16k-0x100\r
+ \r
+ /* Flash memory banks */\r
+ bank0 (rx) : ORIGIN = 0x0d0000, LENGTH = 16k\r
+ bank1 (rx) : ORIGIN = 0x0d4000, LENGTH = 16k\r
+ bank2 (rx) : ORIGIN = 0x0d8000, LENGTH = 16k\r
+ bank3 (rx) : ORIGIN = 0x0dc000, LENGTH = 16k\r
+ bank4 (rx) : ORIGIN = 0x0e0000, LENGTH = 16k\r
+ bank5 (rx) : ORIGIN = 0x0e4000, LENGTH = 16k\r
+ bank6 (rx) : ORIGIN = 0x0e8000, LENGTH = 16k\r
+ bank7 (rx) : ORIGIN = 0x0ec000, LENGTH = 16k\r
+ bank8 (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
+ bank9 (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
+ bank10 (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
+ bank11 (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
+ bank12 (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
+ bank13 (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
+ \r
+ bank14 (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
+ bank15 (rx) : ORIGIN = 0x10c000, LENGTH = 16k-0x100\r
+}\r
+/* Setup the stack on the top of the data memory bank. */\r
+PROVIDE (_stack = 0x1000+12k);\r
+\r
+/* interrupt/reset vectors*/\r
+vectors_addr = 0x10ff80;\r
+\r
+SECTIONS\r
+{\r
+ /* PPAGE memory banks */\r
+\r
+ .bank2 :\r
+ {\r
+ ../Common/Minimal/flash.o(.text .rodata)\r
+ *(.bank2)\r
+ } > bank2\r
+\r
+ .bank3 :\r
+ {\r
+ ParTest.o(.text .rodata)\r
+ *(.bank3)\r
+ } > bank3\r
+\r
+}\r
+\r
--- /dev/null
+/** \r
+ * sci.c controls SCI for GCC/HCS12 version of FreeRTOS Demo\r
+ * Parts taken from the CodeWarrior Demo in order to work similar.\r
+ *\r
+ * Author Jefferson L Smith, Robotronics Inc.\r
+ */\r
+\r
+#include "sci.h"\r
+#include <sys/ports.h>\r
+\r
+//static word SerFlag; /* Flags for serial communication */\r
+ /* Bits: 0 - OverRun error */\r
+ /* 1 - Framing error */\r
+ /* 2 - Parity error */\r
+ /* 3 - Char in RX buffer */\r
+ /* 4 - Full TX buffer */\r
+ /* 5 - Running int from TX */\r
+ /* 6 - Full RX buffer */\r
+ /* 7 - Noise error */\r
+ /* 8 - Idle character */\r
+ /* 9 - Break detected */\r
+ /* 10 - Unused */\r
+static word PrescaleValue;\r
+//static byte NumMode; /* Number of selected baud mode */\r
+\r
+\r
+/**\r
+ * SCI_SetBaudRateMode\r
+ *\r
+ * Changes the speed (baud rate).\r
+ */\r
+byte SCI_SetBaudRateMode(byte Mod)\r
+{\r
+ // wired for 24 MHz bus --jeffs\r
+ static const word SCI_Presc[4] = {39,78,156,313};\r
+\r
+ if(Mod >= 4) /* Is mode in baud mode list */\r
+ return ERR_VALUE; /* If no then error */\r
+ //NumMode = Mod; /* New baud mode */\r
+ PrescaleValue = SCI_Presc[Mod]; /* Prescaler in high speed mode */\r
+\r
+ /* SCI0CR1: LOOPS=0,SCISWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */\r
+ SCICR1 = 0x00; /* Set the SCI configuration */\r
+ /* SCI0SR2: ??=0,??=0,??=0,??=0,??=0,BRK13=0,TXDIR=0,RAF=0 */\r
+ SCISR2 = 0x00; /* Set the Break Character Length and Transmitter pin data direction in Single-wire mode */\r
+ SCISR1; /* Reset interrupt request flags */\r
+ SCIBD = PrescaleValue; /* Set prescaler bits */\r
+ /* SCI0CR2: SCTIE=0,TCIE=0,RIE=1,ILIE=0,TE=1,RE=1,RWU=0,SBK=0 */\r
+ SCICR2 = 0x2c; /* Disable error interrupts */\r
+\r
+ return ERR_OK; /* OK */\r
+}\r
+\r
+#if 0 //(not used)\r
+\r
+/**\r
+ * SCI_Init (bean AsynchroSerial)\r
+ *\r
+ * This enables SCI.\r
+ */\r
+void SCI_Init(void)\r
+{\r
+ PrescaleValue = 39; /* Precaler in high speed mode */\r
+\r
+ /* SCI0CR1: LOOPS=0,SCISWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */\r
+ SCICR1 = 0x00; /* Set the SCI configuration */\r
+ /* SCI0SR2: ??=0,??=0,??=0,??=0,??=0,BRK13=0,TXDIR=0,RAF=0 */\r
+ SCISR2 = 0x00; /* Set the Break Character Length and Transmitter pin data direction in Single-wire mode */\r
+ SCISR1; /* Reset interrupt request flags */\r
+ SCIBD = PrescaleValue; /* Set prescaler bits */\r
+ /* SCI0CR2: SCTIE=0,TCIE=0,RIE=1,ILIE=0,TE=1,RE=1,RWU=0,SBK=0 */\r
+ SCICR2 = 0x2c; /* Disable error interrupts */\r
+}\r
+#endif\r
+\r
--- /dev/null
+/** \r
+ * sci.h controls SCI for GCC/HCS12 version of FreeRTOS Demo\r
+ * Parts taken from the CodeWarrior Demo in order to work similar.\r
+ *\r
+ * Author Jefferson L Smith, Robotronics Inc.\r
+ */\r
+\r
+#ifndef __SCI\r
+#define __SCI\r
+\r
+#include "cpu.h"\r
+\r
+#define COM0_Bm_38400baud 0 /* Constant for switch to mode 0 */\r
+#define COM0_Bm_19200baud 1 /* Constant for switch to mode 1 */\r
+#define COM0_Bm_9600baud 2 /* Constant for switch to mode 2 */\r
+#define COM0_Bm_4800baud 3 /* Constant for switch to mode 3 */\r
+\r
+\r
+/**\r
+ * SCI_SetBaudRateMode\r
+ *\r
+ * Changes the speed (baud rate).\r
+ */\r
+byte SCI_SetBaudRateMode(byte Mod);\r
+\r
+\r
+/**\r
+ * SCI_Init (bean AsynchroSerial)\r
+ *\r
+ * This enables SCI.\r
+ */\r
+void SCI_Init(void);\r
+\r
+#endif /* ifndef __SCI */\r
--- /dev/null
+/*\r
+ serial.c for using FreeRTOS\r
+ Copyright (C) 2005 Robotronics Inc.\r
+*/\r
+\r
+\r
+/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1.\r
+\r
+ GCC demo modifications by Jeff Smith, Robotronics Inc. 2005\r
+*/\r
+\r
+#include "cpu.h"\r
+#include <sys/sio.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "task.h"\r
+\r
+/* Demo application include files. */\r
+#include "sci.h"\r
+#include "serial.h"\r
+\r
+/* The queues used to communicate between the task code and the interrupt\r
+service routines. */\r
+static xQueueHandle xRxedChars; \r
+static xQueueHandle xCharsForTx; \r
+\r
+/* Interrupt identification bits. */\r
+#define serOVERRUN_INTERRUPT ( '\x08' )\r
+#define serRX_INTERRUPT ( 0x20 )\r
+#define serTX_INTERRUPT ( 0x80 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Initialise port for interrupt driven communications.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+ /* Hardware setup is performed by the Processor Expert generated code. \r
+ This function just creates the queues used to communicate between the \r
+ interrupt code and the task code - then sets the required baud rate. */\r
+\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
+\r
+ SCI_SetBaudRateMode( ( portCHAR ) ulWantedBaud );\r
+\r
+ return NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* Get the next character from the buffer queue. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
+{\r
+ /* Place the character in the queue of characters to be transmitted. */\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
+ {\r
+ return pdFAIL;\r
+ }\r
+\r
+ /* Turn on the Tx interrupt so the ISR will remove the character from the\r
+ queue and send it. This does not need to be in a critical section as\r
+ if the interrupt has already removed the character the next interrupt\r
+ will simply turn off the Tx interrupt again. */\r
+ SCICR2 |= 0x80; // TIE\r
+\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{ \r
+ /* Not supported. */\r
+ //( void ) xPort;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/* \r
+ * Interrupt service routine for the serial port. Must be in non-banked\r
+ * memory. \r
+ */\r
+\r
+void ATTR_INT ATTR_NEAR vCOM_ISR( void );\r
+\r
+void vCOM_ISR( void )\r
+{\r
+volatile unsigned portCHAR ucByte, ucStatus;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE;\r
+\r
+ /* What caused the interrupt? */\r
+ ucStatus = SCISR1;\r
+ \r
+ if( ucStatus & serOVERRUN_INTERRUPT )\r
+ {\r
+ /* The interrupt was caused by an overrun. Clear the error by reading\r
+ the data register. */\r
+ ucByte = SCIDRL;\r
+ }\r
+ else\r
+ if( ucStatus & serRX_INTERRUPT )\r
+ {\r
+ /* The interrupt was caused by a character being received.\r
+ Read the received byte. */\r
+ ucByte = SCIDRL;\r
+\r
+ /* Post the character onto the queue of received characters - noting\r
+ whether or not this wakes a task. */\r
+ xTaskWokenByPost = xQueueSendFromISR( xRxedChars, ( void * ) &ucByte, pdFALSE );\r
+ }\r
+ \r
+ if( ( ucStatus & serTX_INTERRUPT ) && ( SCICR2 & 0x80 ) )\r
+ { \r
+ /* The interrupt was caused by a character being transmitted. */\r
+ if( xQueueReceiveFromISR( xCharsForTx, ( void * ) &ucByte, &xTaskWokenByTx ) == pdTRUE )\r
+ {\r
+ /* Clear the SCRF bit. */\r
+ SCIDRL = ucByte;\r
+ }\r
+ else\r
+ {\r
+ /* Disable transmit interrupt */\r
+ SCICR2 &= ~0x80; // TIE\r
+ }\r
+ }\r
+\r
+ if( ( xTaskWokenByPost ) || ( xTaskWokenByTx ) )\r
+ {\r
+ portYIELD();\r
+ }\r
+\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V3.2.3 - Copyright (C) 2003-2005 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * startup.c\r
+ * Author Jefferson L Smith, Robotronics Inc.\r
+ *\r
+ * __premain() is the startup code to init hardware and ram to execute the\r
+ * C application.\r
+ *\r
+ */\r
+\r
+#include <sys/ports.h>\r
+#include "cpu.h"\r
+\r
+void ATTR_NEAR __premain (void);\r
+\r
+void\r
+__premain (void)\r
+{\r
+ // in case special mode enabled, avoid conflict on PORTE\r
+ PEAR |= NECLK;\r
+ // bgnd mode stops COP and RTI clocks\r
+ COPCTL = RSBCK;\r
+ // stops TCNT counter when debugging stops\r
+ TSCR1 |= (1<<5); // TFRZ\r
+ \r
+ // PLL\r
+ CLKSEL = 0; // disable PLL to configure\r
+ // xtal 16MHz, bus 24MHz\r
+ SYNR = 3 - 1;\r
+ REFDV = 2 - 1;\r
+ while (!(CRGFLG & 0x08)) // wait for PLL LOCK\r
+ cop_optional_reset();\r
+ CLKSEL |= 0x80; // use PLL\r
+\r
+ // init switch inputs\r
+ PERH = 0xff; // pullups\r
+\r
+ // outputs\r
+#if PORT_LED==M6811_PORTB //PORTB\r
+ DDRB = 0xff; // init LED\r
+#elif PORT_LED==M6811_PORTA //PORTA\r
+ DDRA = 0xff;\r
+#elif PORT_LED==M6811_PTT //PTT\r
+ DDRT = 0xff;\r
+#elif PORT_LED==M6811_PTM //PTM\r
+ DDRM = 0xff;\r
+#elif PORT_LED==M6811_PTP //PTP\r
+ DDRP = 0xff;\r
+#elif PORT_LED==M6811_PTH //PTH\r
+ DDRH = 0xff;\r
+#endif\r
+ \r
+}\r
+\r
--- /dev/null
+/* Interrupt Vectors\r
+ Copyright (C) 2000, 2002, 2003 Free Software Foundation, Inc.\r
+ Written by Stephane Carrez (stcarrez@nerim.fr) \r
+\r
+This file is free software; you can redistribute it and/or modify it\r
+under the terms of the GNU General Public License as published by the\r
+Free Software Foundation; either version 2, or (at your option) any\r
+later version.\r
+\r
+In addition to the permissions in the GNU General Public License, the\r
+Free Software Foundation gives you unlimited permission to link the\r
+compiled version of this file with other programs, and to distribute\r
+those programs without any restriction coming from the use of this\r
+file. (The General Public License restrictions do apply in other\r
+respects; for example, they cover modification of the file, and\r
+distribution when not linked into another program.)\r
+\r
+This file is distributed in the hope that it will be useful, but\r
+WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with this program; see the file COPYING. If not, write to\r
+the Free Software Foundation, 59 Temple Place - Suite 330,\r
+Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _SYS_INTERRUPTS_H\r
+#define _SYS_INTERRUPTS_H\r
+\r
+#include <sys/param.h>\r
+\r
+#ifdef mc6811\r
+//# include <asm-m68hc11/interrupts.h>\r
+#endif\r
+\r
+#ifdef mc68hcs12\r
+# include <asm-m68hcs12/interrupts.h>\r
+#elif defined(mc6812)\r
+//# include <asm-m68hc12/interrupts.h>\r
+#endif\r
+\r
+/*! Install an interrupt handler.\r
+\r
+ Install the interrupt handler for an exception. The handler\r
+ is installed for \b bootstrap mode and also for \b normal operating\r
+ mode.\r
+ \r
+ @param id the interrupt number to be installed\r
+ @param handler the interrupt handler entry point\r
+*/\r
+extern void\r
+set_interrupt_handler (interrupt_vector_id id, interrupt_t handler);\r
+\r
+/*! Default and fatal interrupt handler.\r
+\r
+ This function is an interrupt handler intended to be used to\r
+ handle all interrupt not used by a program. Since it is an\r
+ error to have an interrupt when it is not handled, the default\r
+ behavior is to print a message and stop. */\r
+extern void __attribute__((interrupt, noreturn))\r
+fatal_interrupt (void);\r
+\r
+#include <arch/interrupts.h>\r
+\r
+/*! Entry point of any program.\r
+\r
+ This function should never be called by itself. It represents the\r
+ entry point of any program. It is intended to be used in an\r
+ interrupt table to specify the function to jump to after reset. */\r
+extern void _start (void);\r
+\r
+#endif\r
--- /dev/null
+/* param.h - Board specific parameters\r
+ Copyright (C) 2000, 2002, 2003 Free Software Foundation, Inc.\r
+ Written by Stephane Carrez (stcarrez@nerim.fr) \r
+\r
+This file is free software; you can redistribute it and/or modify it\r
+under the terms of the GNU General Public License as published by the\r
+Free Software Foundation; either version 2, or (at your option) any\r
+later version.\r
+\r
+In addition to the permissions in the GNU General Public License, the\r
+Free Software Foundation gives you unlimited permission to link the\r
+compiled version of this file with other programs, and to distribute\r
+those programs without any restriction coming from the use of this\r
+file. (The General Public License restrictions do apply in other\r
+respects; for example, they cover modification of the file, and\r
+distribution when not linked into another program.)\r
+\r
+This file is distributed in the hope that it will be useful, but\r
+WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with this program; see the file COPYING. If not, write to\r
+the Free Software Foundation, 59 Temple Place - Suite 330,\r
+Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _SYS_PARAM_H\r
+#define _SYS_PARAM_H\r
+\r
+/*! Attribute unused.\r
+ Use this attribute to indicate that a parameter, a variable or a\r
+ static function is not used. The compiler will not warn about the\r
+ unused variable. */\r
+#define ATTRIBUTE_UNUSED __attribute__((unused))\r
+\r
+/*! Attribute page0.\r
+ Use this attribute to put a global or static variable in page0. */\r
+#define PAGE0_ATTRIBUTE __attribute__((section(".page0")))\r
+\r
+#ifdef mc6811\r
+//# include <asm-m68hc11/param.h>\r
+#endif\r
+\r
+#ifdef mc68hcs12\r
+# include <asm-m68hcs12/param.h>\r
+#elif defined(mc6812)\r
+//# include <asm-m68hc12/param.h>\r
+#endif\r
+\r
+#include <arch/param.h>\r
+\r
+#define GNU_LINKER_WARNING(SYMBOL, MSG) \\r
+ asm (".section .gnu.warning." SYMBOL "\n\t.string \"" MSG "\"\n\t.previous");\r
+\r
+#endif\r
--- /dev/null
+/* sys/ports.h -- Definition of system ports\r
+ Copyright 2000, 2001, 2002 Free Software Foundation, Inc.\r
+ Written by Stephane Carrez (stcarrez@worldnet.fr)\r
+\r
+This file is part of GEL.\r
+\r
+GEL is free software; you can redistribute it and/or modify\r
+it under the terms of the GNU General Public License as published by\r
+the Free Software Foundation; either version 2, or (at your option)\r
+any later version.\r
+\r
+GEL is distributed in the hope that it will be useful,\r
+but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+GNU General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with GEL; see the file COPYING. If not, write to\r
+the Free Software Foundation, 59 Temple Place - Suite 330,\r
+Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _SYS_PORTS_H\r
+#define _SYS_PORTS_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+ extern unsigned short get_timer_counter (void);\r
+ extern void set_timer_counter (unsigned short);\r
+ extern unsigned short get_input_capture_1 (void);\r
+ extern void set_input_capture_1 (unsigned short);\r
+ extern unsigned short get_input_capture_2 (void);\r
+ extern void set_input_capture_2 (unsigned short);\r
+ extern unsigned short get_input_capture_3 (void);\r
+ extern void set_input_capture_3 (unsigned short);\r
+ extern unsigned short get_output_compare_1 (void);\r
+ extern void set_output_compare_1 (unsigned short);\r
+ extern unsigned short get_output_compare_2 (void);\r
+ extern void set_output_compare_2 (unsigned short);\r
+ extern unsigned short get_output_compare_3 (void);\r
+ extern void set_output_compare_3 (unsigned short);\r
+ extern unsigned short get_output_compare_4 (void);\r
+ extern void set_output_compare_4 (unsigned short);\r
+ extern unsigned short get_output_compare_5 (void);\r
+ extern void set_output_compare_5 (unsigned short);\r
+ extern void set_bus_expanded (void);\r
+ extern void set_bus_single_chip (void);\r
+ extern void cop_reset (void);\r
+ extern void cop_optional_reset (void);\r
+ extern void timer_acknowledge (void);\r
+ extern void timer_initialize_rate (unsigned char);\r
+ \r
+#ifdef mc6811\r
+//# include <asm-m68hc11/ports.h>\r
+#endif\r
+\r
+#ifdef mc68hcs12\r
+# include <asm-m68hcs12/ports.h>\r
+#elif defined(mc6812)\r
+//# include <asm-m68hc12/ports.h>\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+};\r
+#endif\r
+ \r
+#endif /* _SYS_PORTS_H */\r
+\r
--- /dev/null
+/* sys/ports_def.h -- Definition of system ports\r
+ Copyright 2000 Free Software Foundation, Inc.\r
+ Written by Stephane Carrez (stcarrez@worldnet.fr)\r
+\r
+This file is part of GEL.\r
+\r
+GEL is free software; you can redistribute it and/or modify\r
+it under the terms of the GNU General Public License as published by\r
+the Free Software Foundation; either version 2, or (at your option)\r
+any later version.\r
+\r
+GEL is distributed in the hope that it will be useful,\r
+but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+GNU General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with GEL; see the file COPYING. If not, write to\r
+the Free Software Foundation, 59 Temple Place - Suite 330,\r
+Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _SYS_PORTS_DEF_H\r
+#define _SYS_PORTS_DEF_H\r
+\r
+#ifdef mc6811\r
+//# include <asm-m68hc11/ports_def.h>\r
+#endif\r
+\r
+#ifdef mc68hcs12\r
+# include <asm-m68hcs12/ports_def.h>\r
+#elif defined(mc6812)\r
+//# include <asm-m68hc12/ports_def.h>\r
+#endif\r
+\r
+#endif /* _SYS_PORTS_DEF_H */\r
+\r
--- /dev/null
+/* sys/sio.h -- Utility methods to read/write the SIO\r
+ Copyright 2000 Free Software Foundation, Inc.\r
+ Written by Stephane Carrez (stcarrez@worldnet.fr)\r
+\r
+This file is part of GEL.\r
+\r
+GEL is free software; you can redistribute it and/or modify\r
+it under the terms of the GNU General Public License as published by\r
+the Free Software Foundation; either version 2, or (at your option)\r
+any later version.\r
+\r
+GEL is distributed in the hope that it will be useful,\r
+but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+GNU General Public License for more details.\r
+\r
+You should have received a copy of the GNU General Public License\r
+along with GEL; see the file COPYING. If not, write to\r
+the Free Software Foundation, 59 Temple Place - Suite 330,\r
+Boston, MA 02111-1307, USA. */\r
+\r
+#ifndef _SYS_SIO_H\r
+#define _SYS_SIO_H\r
+\r
+#include <sys/param.h>\r
+#include <sys/ports.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+extern void serial_init (void);\r
+\r
+/* Return != 0 if there is something to read on the serial line. */\r
+extern unsigned char serial_receive_pending (void);\r
+\r
+/* Wait until the SIO has finished to send the character. */\r
+extern void serial_flush (void);\r
+\r
+/* Return != 0 if serial port is ready to send another char. */\r
+extern unsigned char serial_send_ready (void);\r
+\r
+/* Send the character on the serial line. */\r
+extern void serial_send (char c);\r
+\r
+/* Wait for a character on the serial line and return it. */\r
+extern unsigned char serial_recv (void);\r
+\r
+/** Write the string on the serial line.\r
+\r
+ @param msg null terminated string to write.\r
+\r
+ @see serial_init, serial_send\r
+*/\r
+extern void serial_print (const char *msg);\r
+\r
+/** Wait for a string from serial line.\r
+\r
+ @param msg buffer that will hold the string.\r
+\r
+ @see serial_init, serial_recv\r
+*/\r
+extern void serial_getline (char *buf);\r
+\r
+#ifdef mc6811\r
+//# include <asm-m68hc11/sio.h>\r
+#endif\r
+\r
+#ifdef mc68hcs12\r
+# include <asm-m68hcs12/sio.h>\r
+#elif defined(mc6812)\r
+//# include <asm-m68hc12/sio.h>\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+};\r
+#endif\r
+#endif /* _SYS_SIO_H */\r
+\r
--- /dev/null
+/* modrx.c -- wireless controller receiver for robots\r
+ Copyright 2004 Robotronics, Inc.\r
+ Author Jefferson Smith\r
+\r
+ This file is part of the Modular Robot Design.\r
+*/\r
+\r
+#include "cpu.h"\r
+#include <sys/ports.h>\r
+#include <sys/interrupts.h>\r
+\r
+void fatal_interrupt ()\r
+{\r
+ /* Infinite loop for debugging\r
+ Returning would not help as it's necessary to clear the interrupt flag.\r
+ */\r
+ for (;;) cop_optional_reset();\r
+}\r
+\r
+#ifdef USE_INTERRUPT_TABLE\r
+\r
+/* NOTE: these ISR must be in non-banked memory (near) */\r
+\r
+/* Manual context switch function. This is the SWI ISR. */\r
+void ATTR_INT ATTR_NEAR vPortYield( void );\r
+\r
+/* Tick context switch function. This is the timer ISR. */\r
+void ATTR_INT ATTR_NEAR vPortTickInterrupt( void );\r
+\r
+void ATTR_INT ATTR_NEAR vCOM_ISR( void );\r
+\r
+/* Interrupt vectors table.\r
+\r
+ Note: the `XXX_handler: foo' notation is a GNU extension which is\r
+ used here to ensure correct association of the handler in the struct.\r
+ This is why the order of handlers declared below does not follow\r
+ the MCU order. */\r
+const struct interrupt_vectors __attribute__((section(".vectors"))) vectors = \r
+{\r
+ pwm_shutdown_handler: fatal_interrupt,\r
+ ptpif_handler: fatal_interrupt,\r
+ can4_tx_handler: fatal_interrupt,\r
+ can4_rx_handler: fatal_interrupt,\r
+ can4_err_handler: fatal_interrupt,\r
+ can4_wake_handler: fatal_interrupt,\r
+ can3_tx_handler: fatal_interrupt,\r
+ can3_rx_handler: fatal_interrupt,\r
+ can3_err_handler: fatal_interrupt,\r
+ can3_wake_handler: fatal_interrupt,\r
+ can2_tx_handler: fatal_interrupt,\r
+ can2_rx_handler: fatal_interrupt,\r
+ can2_err_handler: fatal_interrupt,\r
+ can2_wake_handler: fatal_interrupt,\r
+ can1_tx_handler: fatal_interrupt,\r
+ can1_rx_handler: fatal_interrupt,\r
+ can1_err_handler: fatal_interrupt,\r
+ can1_wake_handler: fatal_interrupt,\r
+ can0_tx_handler: fatal_interrupt,\r
+ can0_rx_handler: fatal_interrupt,\r
+ can0_err_handler: fatal_interrupt,\r
+ can0_wake_handler: fatal_interrupt,\r
+ flash_handler: fatal_interrupt,\r
+ eeprom_handler: fatal_interrupt,\r
+ spi2_handler: fatal_interrupt,\r
+ spi1_handler: fatal_interrupt,\r
+ iic_handler: fatal_interrupt,\r
+ bdlc_handler: fatal_interrupt,\r
+ selfclk_mode_handler: fatal_interrupt,\r
+ pll_lock_handler: fatal_interrupt,\r
+ accb_overflow_handler: fatal_interrupt,\r
+ mccnt_underflow_handler: fatal_interrupt,\r
+ pthif_handler: fatal_interrupt,\r
+ ptjif_handler: fatal_interrupt,\r
+ atd1_handler: fatal_interrupt,\r
+ atd0_handler: fatal_interrupt,\r
+ sci1_handler: fatal_interrupt,\r
+ sci0_handler: fatal_interrupt,\r
+ spi0_handler: fatal_interrupt,\r
+\r
+ /** Timer and Accumulator */\r
+ acca_input_handler: fatal_interrupt,\r
+ acca_overflow_handler: fatal_interrupt,\r
+ timer_overflow_handler: fatal_interrupt,\r
+ \r
+ /** Input capture / Output compare Timers */\r
+ tc7_handler: fatal_interrupt,\r
+ tc6_handler: fatal_interrupt,\r
+ tc5_handler: fatal_interrupt,\r
+ tc4_handler: fatal_interrupt,\r
+ tc3_handler: fatal_interrupt,\r
+ tc2_handler: fatal_interrupt,\r
+ tc1_handler: fatal_interrupt,\r
+ tc0_handler: fatal_interrupt,\r
+\r
+ /** External Interrupts */\r
+ rtii_handler: fatal_interrupt,\r
+ irq_handler: fatal_interrupt,\r
+ xirq_handler: fatal_interrupt,\r
+\r
+ illegal_handler: fatal_interrupt,\r
+ cop_fail_handler: fatal_interrupt,\r
+ cop_clock_handler: fatal_interrupt,\r
+\r
+ /** Vectors in use */\r
+ swi_handler: vPortYield,\r
+ rtii_handler: vPortTickInterrupt,\r
+#if M6812_DEF_SCI==1\r
+ sci1_handler: vCOM_ISR,\r
+#else\r
+ sci0_handler: vCOM_ISR,\r
+#endif\r
+ reset_handler: _start\r
+};\r
+#endif\r
+\r
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