cfg: add stm32 cmsis-dap compliant config

Change-Id: I3cfb21fdcef830e22b03bf4b5d58993728cc7475
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1543
Tested-by: jenkins

diff --git a/tcl/board/stm320518_eval.cfg b/tcl/board/stm320518_eval.cfg
new file mode 100644 (file)
index 0000000..6f1f322
--- /dev/null
+++ b/tcl/board/stm320518_eval.cfg
@@ -0,0 +1,12 @@
+# STM320518-EVAL: This is an STM32F0 eval board with a single STM32F051R8T6
+# (64KB) chip.
+# http://www.st.com/internet/evalboard/product/252994.jsp
+#
+
+# increase working area to 8KB
+set WORKAREASIZE 0x2000
+
+# chip name
+set CHIPNAME STM32F051R8T6
+
+source [find target/stm32f0x.cfg]

diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg
new file mode 100644 (file)
index 0000000..104dcb9
--- /dev/null
+++ b/tcl/target/stm32f0x.cfg
@@ -0,0 +1,55 @@
+# script for stm32f0x family
+
+#
+# stm32 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f0x
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0091
+  # Section 29.5.3
+   set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m reset_config sysresetreq

diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 12d33d52c5297ecdb05b3cb58590f65746069c3c..f32654a57abf41ac27e3dc225ac2a4353836784d 100644 (file)
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -1,5 +1,10 @@
 # script for stm32f1x family
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
@@ -20,12 +25,6 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x1000
 }
 
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
 #jtag scan chain
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
@@ -34,7 +33,8 @@ if { [info exists CPUTAPID] } {
   # Section 26.6.3
    set _CPUTAPID 0x3ba00477
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 if { [info exists BSTAPID] } {
    # FIXME this never gets used to override defaults...
@@ -59,13 +59,15 @@ if { [info exists BSTAPID] } {
   set _BSTAPID8 0x06420041
   # VL line devices, Rev A
   set _BSTAPID9 0x06428041
-
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+
+if {$using_jtag} {
+ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
        -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
        -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
        -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \
        -expected-id $_BSTAPID8 -expected-id $_BSTAPID9
+}
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
@@ -76,6 +78,14 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
 
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+if {$using_jtag} {
+ jtag_ntrst_delay 100
+}
+
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
 cortex_m reset_config sysresetreq

diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index 43a944c103d10f646e757fdf8235eb82358fdd45..5022ef7dbd18dbe1c64197a32e1f8ce34398256d 100644 (file)
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -1,5 +1,10 @@
 # script for stm32f2x family
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
@@ -29,7 +34,9 @@ if { [info exists WORKAREASIZE] } {
 adapter_khz 1000
 
 adapter_nsrst_delay 100
-jtag_ntrst_delay 100
+if {$using_jtag} {
+ jtag_ntrst_delay 100
+}
 
 #jtag scan chain
 if { [info exists CPUTAPID] } {
@@ -39,7 +46,8 @@ if { [info exists CPUTAPID] } {
   # Section 32.6.3 - corresponds to Cortex-M3 r2p0
    set _CPUTAPID 0x4ba00477
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
@@ -49,7 +57,10 @@ if { [info exists BSTAPID] } {
   # 
   set _BSTAPID 0x06411041
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+
+if {$using_jtag} {
+ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+}
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index d092b6c887cd565260eb774cd84fc7f595d207b4..3d68c4bfbafe657d5453fbb8edb0bf2c58001a83 100644 (file)
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -1,5 +1,10 @@
 # script for stm32f3x family
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
@@ -29,7 +34,9 @@ if { [info exists WORKAREASIZE] } {
 adapter_khz 1000
 
 adapter_nsrst_delay 100
-jtag_ntrst_delay 100
+if {$using_jtag} {
+ jtag_ntrst_delay 100
+}
 
 #jtag scan chain
 if { [info exists CPUTAPID] } {
@@ -39,7 +46,8 @@ if { [info exists CPUTAPID] } {
   # Section 29.6.3 - corresponds to Cortex-M4 r0p1
    set _CPUTAPID 0x4ba00477
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
@@ -49,7 +57,10 @@ if { [info exists BSTAPID] } {
   set _BSTAPID1 0x06422041
   set _BSTAPID2 0x06432041
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
+
+if {$using_jtag} {
+ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
+}
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME

diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index b5ab200481b0543c3a5cace4a6bb55cec65cc544..eafa1226865fe313f5bfb6d88fa7e0341a530ea4 100644 (file)
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -1,5 +1,10 @@
 # script for stm32f4x family
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
@@ -29,7 +34,9 @@ if { [info exists WORKAREASIZE] } {
 adapter_khz 1000
 
 adapter_nsrst_delay 100
-jtag_ntrst_delay 100
+if {$using_jtag} {
+ jtag_ntrst_delay 100
+}
 
 #jtag scan chain
 if { [info exists CPUTAPID] } {
@@ -39,7 +46,8 @@ if { [info exists CPUTAPID] } {
   # Section 38.6.3 - corresponds to Cortex-M4 r0p1
    set _CPUTAPID 0x4ba00477
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
@@ -51,8 +59,11 @@ if { [info exists BSTAPID] } {
   # STM32F42xxx and STM32F43xxx
   set _BSTAPID2 0x06419041
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+
+if {$using_jtag} {
+ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
        -expected-id $_BSTAPID2
+}
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME

diff --git a/tcl/target/stm32l.cfg b/tcl/target/stm32l.cfg
index 8e6a10e1f3c7adfe060a91152db4c5ab92c1dfe2..f9f7425b9a7bb9925a21b9921710e908220b176e 100644 (file)
--- a/tcl/target/stm32l.cfg
+++ b/tcl/target/stm32l.cfg
@@ -1,5 +1,10 @@
 # script for stm32l
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
@@ -25,7 +30,9 @@ if { [info exists WORKAREASIZE] } {
 adapter_khz 100
 
 adapter_nsrst_delay 100
-jtag_ntrst_delay 100
+if {$using_jtag} {
+ jtag_ntrst_delay 100
+}
 
 #jtag scan chain
 if { [info exists CPUTAPID] } {
@@ -35,7 +42,8 @@ if { [info exists CPUTAPID] } {
   # Section 24.6.3
    set _CPUTAPID 0x4ba00477
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 if { [info exists BSTAPID] } {
    # FIXME this never gets used to override defaults...
@@ -45,14 +53,16 @@ if { [info exists BSTAPID] } {
   # Section 24.6.2
   set _BSTAPID 0x06416041
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+
+if {$using_jtag} {
+ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+}
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-
 # flash size will be probed
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

diff --git a/tcl/target/stm32w108xx.cfg b/tcl/target/stm32w108xx.cfg
index ca4f15322a7fec0c12627cc608f4a6f7fe258670..4bc51fc0496aaaf625925da3c505e46ae2d43fb1 100644 (file)
--- a/tcl/target/stm32w108xx.cfg
+++ b/tcl/target/stm32w108xx.cfg
@@ -5,6 +5,11 @@
 # Date:      2013-06-09
 # Author:    Giuseppe Barba <giuseppe.barba@gmail.com>
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] == 0 } {
    set _CHIPNAME stm32w108
 } else {
@@ -31,18 +36,19 @@ if { [info exists ENDIAN] } {
    set _ENDIAN little
 }
 
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-if { [info exists BSTAPID] } {
+if {$using_jtag} {
+ if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
    jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id 0x269a862b
-} else {
+ } else {
    set _BSTAPID_1 0x169a862b
    set _BSTAPID_2 0x269a862b
    jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \
                -expected-id $_BSTAPID_1 -expected-id $_BSTAPID_2
+ }
 }
-
 #
 # Set Target
 #