- <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
- </option>\r
- <option>\r
- <name>Output variant</name>\r
- <version>2</version>\r
- <state>7</state>\r
- </option>\r
- <option>\r
- <name>Output description</name>\r
- <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
- </option>\r
- <option>\r
- <name>GOutputBinary</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>FPU</name>\r
- <version>2</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OGCoreOrChip</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>GRuntimeLibSelect</name>\r
- <version>0</version>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>GRuntimeLibSelectSlave</name>\r
- <version>0</version>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>RTDescription</name>\r
- <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
- <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
- </option>\r
- <option>\r
- <name>Output variant</name>\r
- <version>2</version>\r
- <state>7</state>\r
- </option>\r
- <option>\r
- <name>Output description</name>\r
- <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
- </option>\r
- <option>\r
- <name>GOutputBinary</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>FPU</name>\r
- <version>2</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OGCoreOrChip</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>GRuntimeLibSelect</name>\r
- <version>0</version>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>GRuntimeLibSelectSlave</name>\r
- <version>0</version>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>RTDescription</name>\r
- <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
- <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
- </option>\r
- <option>\r
- <name>Output variant</name>\r
- <version>2</version>\r
- <state>7</state>\r
- </option>\r
- <option>\r
- <name>Output description</name>\r
- <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
- </option>\r
- <option>\r
- <name>GOutputBinary</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>FPU</name>\r
- <version>2</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OGCoreOrChip</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>GRuntimeLibSelect</name>\r
- <version>0</version>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>GRuntimeLibSelectSlave</name>\r
- <version>0</version>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>RTDescription</name>\r
- <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
- <option id="com.atollic.truestudio.gcc.optimization.prep_garbage.1538779399" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>\r
+ <option id="com.atollic.truestudio.gcc.optimization.prep_garbage.1538779399" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>\r
<option id="com.atollic.truestudio.gcc.optimization.prep_data.558520264" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>\r
<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.1312457498" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>\r
<option id="com.atollic.truestudio.gpp.optimization.prep_data.837583714" name="Prepare dead data removal" superClass="com.atollic.truestudio.gpp.optimization.prep_data" value="true" valueType="boolean"/>\r
- #warning configCLINT_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a Core Local Interrupter (CLINT) then set configCLINT_BASE_ADDRESS to the CLINT base address. Otherwise set configCLINT_BASE_ADDRESS to 0.\r
-#endif\r
-\r
-/* Let the user override the pre-loading of the initial LR with the address of\r
-prvTaskExitError() in case it messes up unwinding of the stack in the\r
-/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line\r
-definitions. */\r
-#ifndef portasmHAS_CLINT\r
- #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).\r
-#endif\r
-\r
-#ifndef portasmHANDLE_INTERRUPT\r
- #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.\r
-#endif\r
-\r
-/* Only the standard core registers are stored by default. Any additional\r
-registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and\r
-portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip\r
-specific version of freertos_risc_v_chip_specific_extensions.h. See the notes\r
- portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */\r
-\r
- lw t0, pxCurrentTCB /* Load pxCurrentTCB. */\r
- sw sp, 0( t0 ) /* Write sp to first TCB member. */\r
-\r
- csrr a0, mcause\r
- csrr a1, mepc\r
-\r
-test_if_asynchronous:\r
- srli a2, a0, 0x1f /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */\r
- beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */\r
- sw a1, 0( sp ) /* Asynch so save unmodified exception return address. */\r
-\r
-handle_asynchronous:\r
-\r
-#if( portasmHAS_CLINT != 0 )\r
-\r
- test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */\r
- lw t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */\r
- lw t1, pullNextTime /* Load the address of ullNextTime into t1. */\r
- lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */\r
- lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */\r
- sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */\r
- sw t3, 4(t0) /* Store high word of ullNextTime into compare register. */\r
- lw t0, ulTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
- add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits. */\r
- sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */\r
- add t6, t3, t5 /* Add overflow to high word of ullNextTime. */\r
- sw t4, 0(t1) /* Store new low word of ullNextTime. */\r
- sw t6, 4(t1) /* Store new high word of ullNextTime. */\r
- lw sp, xISRStackTop /* Switch to ISR stack before function call. */\r
- jal xTaskIncrementTick\r
- beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */\r
- jal vTaskSwitchContext\r
- j processed_source\r
-\r
- test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */\r
- lw sp, xISRStackTop /* Switch to ISR stack before function call. */\r
- jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */\r
- j processed_source\r
-\r
-handle_synchronous:\r
- addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */\r
- bne a0, t0, is_exception /* Not an M environment call, so some other exception. */\r
- lw sp, xISRStackTop /* Switch to ISR stack before function call. */\r
- jal vTaskSwitchContext\r
- j processed_source\r
-\r
-is_exception:\r
- ebreak\r
- j is_exception\r
-\r
-as_yet_unhandled:\r
- ebreak\r
- j as_yet_unhandled\r
-\r
-processed_source:\r
- lw sp, pxCurrentTCB /* Load pxCurrentTCB. */\r
- lw sp, 0( sp ) /* Read sp from first TCB member. */\r
-\r
- /* Load mret with the address of the next instruction in the task to run next. */\r
- lw t0, 0( sp )\r
- csrw mepc, t0\r
-\r
- portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
-\r
- /* Load mstatus with the interrupt enable bits used by the task. */\r
- /* If there is a clint then interrupts can branch directly to the FreeRTOS\r
- trap handler. Otherwise the interrupt controller will need to be configured\r
- outside of this file. */\r
- la t0, freertos_risc_v_trap_handler\r
- csrw mtvec, t0\r
-#endif /* portasmHAS_CLILNT */\r
-\r
- lw sp, pxCurrentTCB /* Load pxCurrentTCB. */\r
- lw sp, 0( sp ) /* Read sp from first TCB member. */\r
-\r
- lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */\r
-\r
- portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
- #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
- #endif\r
-\r
- /* Store/clear the ready priorities in a bit map. */\r
new file mode 100644 (file)
index 0000000..7576907
Binary files /dev/null and b/FreeRTOS/Source/portable/GCC/RISC-V/FreeRTOS for RISC-V RV32.pdf differ
+ #warning configCLINT_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a Core Local Interrupter (CLINT) then set configCLINT_BASE_ADDRESS to the CLINT base address. Otherwise set configCLINT_BASE_ADDRESS to 0.\r
+#endif\r
+\r
+/* Let the user override the pre-loading of the initial LR with the address of\r
+prvTaskExitError() in case it messes up unwinding of the stack in the\r
+/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line\r
+definitions. */\r
+#ifndef portasmHAS_CLINT\r
+ #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).\r
+#endif\r
+\r
+#ifndef portasmHANDLE_INTERRUPT\r
+ #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.\r
+#endif\r
+\r
+/* Only the standard core registers are stored by default. Any additional\r
+registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and\r
+portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip\r
+specific version of freertos_risc_v_chip_specific_extensions.h. See the notes\r
+ portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */\r
+\r
+ lw t0, pxCurrentTCB /* Load pxCurrentTCB. */\r
+ sw sp, 0( t0 ) /* Write sp to first TCB member. */\r
+\r
+ csrr a0, mcause\r
+ csrr a1, mepc\r
+\r
+test_if_asynchronous:\r
+ srli a2, a0, 0x1f /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */\r
+ beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */\r
+ sw a1, 0( sp ) /* Asynch so save unmodified exception return address. */\r
+\r
+handle_asynchronous:\r
+\r
+#if( portasmHAS_CLINT != 0 )\r
+\r
+ test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */\r
+ lw t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */\r
+ lw t1, pullNextTime /* Load the address of ullNextTime into t1. */\r
+ lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */\r
+ lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */\r
+ sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */\r
+ sw t3, 4(t0) /* Store high word of ullNextTime into compare register. */\r
+ lw t0, ulTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
+ add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits. */\r
+ sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */\r
+ add t6, t3, t5 /* Add overflow to high word of ullNextTime. */\r
+ sw t4, 0(t1) /* Store new low word of ullNextTime. */\r
+ sw t6, 4(t1) /* Store new high word of ullNextTime. */\r
+ lw sp, xISRStackTop /* Switch to ISR stack before function call. */\r
+ jal xTaskIncrementTick\r
+ beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */\r
+ jal vTaskSwitchContext\r
+ j processed_source\r
+\r
+ test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */\r
+ lw sp, xISRStackTop /* Switch to ISR stack before function call. */\r
+ jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */\r
+ j processed_source\r
+\r
+handle_synchronous:\r
+ addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */\r
+ bne a0, t0, is_exception /* Not an M environment call, so some other exception. */\r
+ lw sp, xISRStackTop /* Switch to ISR stack before function call. */\r
+ jal vTaskSwitchContext\r
+ j processed_source\r
+\r
+is_exception:\r
+ ebreak\r
+ j is_exception\r
+\r
+as_yet_unhandled:\r
+ ebreak\r
+ j as_yet_unhandled\r
+\r
+processed_source:\r
+ lw sp, pxCurrentTCB /* Load pxCurrentTCB. */\r
+ lw sp, 0( sp ) /* Read sp from first TCB member. */\r
+\r
+ /* Load mret with the address of the next instruction in the task to run next. */\r
+ lw t0, 0( sp )\r
+ csrw mepc, t0\r
+\r
+ portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
+\r
+ /* Load mstatus with the interrupt enable bits used by the task. */\r
+ /* If there is a clint then interrupts can branch directly to the FreeRTOS\r
+ trap handler. Otherwise the interrupt controller will need to be configured\r
+ outside of this file. */\r
+ la t0, freertos_risc_v_trap_handler\r
+ csrw mtvec, t0\r
+#endif /* portasmHAS_CLILNT */\r
+\r
+ lw sp, pxCurrentTCB /* Load pxCurrentTCB. */\r
+ lw sp, 0( sp ) /* Read sp from first TCB member. */\r
+\r
+ lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */\r
+\r
+ portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r
+ #endif\r
+\r
+ /* Store/clear the ready priorities in a bit map. */\r