Save changes to the RISC-V port layer before making changes necessary to support...

+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2603 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
index 139d1c8336716b78f57a4b6b2c27e809f5dcb505..95ec89e349922171ec8c6d4a8e15d476c1f8c9ac 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
@@ -39,9 +39,8 @@
        static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };\r
        const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 1 ] );\r
 #else\r
-#warning What should _sp be named?\r
-       extern const uint32_t _sp[];\r
-       const uint32_t xISRStackTop = ( uint32_t ) _sp;\r
+       extern const uint32_t __freertos_irq_stack_top[];\r
+       const uint32_t xISRStackTop = ( uint32_t ) __freertos_irq_stack_top;\r
 #endif\r
 \r
 /*\r
@@ -227,9 +226,6 @@ volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLI
 \r
        /* Prepare the time to use after the next tick interrupt. */\r
        ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;\r
-\r
-       /* Enable timer interrupt. */\r
-       __asm volatile( "csrs mie, %0" :: "r"(0x80) ); /* 1<<7 for timer interrupt. */\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -254,6 +250,12 @@ extern void xPortStartFirstTask( void );
        #endif\r
 \r
        vPortSetupTimerInterrupt();\r
+\r
+       /* Enable mtime and external interrupts.  1<<7 for timer interrupt, 1<<11\r
+       for external interrupt.  _RB_ What happens here when mtime is not present as\r
+       with pulpino? */\r
+       __asm volatile( "csrs mie, %0" :: "r"(0x880) );\r
+\r
        xPortStartFirstTask();\r
 \r
        /* Should not get here as after calling xPortStartFirstTask() only tasks\r
@@ -271,3 +273,4 @@ void vPortEndScheduler( void )
 \r
 \r
 \r
+\r

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
index e9ba83856fc8d67993de853e9b54006c54891e9a..d08c2b082765700a3b69720e2213e22560fd9645 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
@@ -50,49 +50,7 @@
 .extern pullNextTime\r
 .extern ulTimerIncrementsForOneTick\r
 .extern xISRStackTop\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-.align 8\r
-xPortStartFirstTask:\r
-\r
-       la t0, vPortTrapHandler\r
-       csrw mtvec, t0\r
-\r
-       lw  sp, pxCurrentTCB                    /* Load pxCurrentTCB. */\r
-       lw  sp, 0( sp )                                 /* Read sp from first TCB member. */\r
-\r
-       lw  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */\r
-       lw  x5, 2 * WORD_SIZE( sp )             /* t0 */\r
-       lw  x6, 3 * WORD_SIZE( sp )             /* t1 */\r
-       lw  x7, 4 * WORD_SIZE( sp )             /* t2 */\r
-       lw  x8, 5 * WORD_SIZE( sp )             /* s0/fp */\r
-       lw  x9, 6 * WORD_SIZE( sp )             /* s1 */\r
-       lw  x10, 7 * WORD_SIZE( sp )    /* a0 */\r
-       lw  x11, 8 * WORD_SIZE( sp )    /* a1 */\r
-       lw  x12, 9 * WORD_SIZE( sp )    /* a2 */\r
-       lw  x13, 10 * WORD_SIZE( sp )   /* a3 */\r
-       lw  x14, 11 * WORD_SIZE( sp )   /* a4 */\r
-       lw  x15, 12 * WORD_SIZE( sp )   /* a5 */\r
-       lw  x16, 13 * WORD_SIZE( sp )   /* a6 */\r
-       lw  x17, 14 * WORD_SIZE( sp )   /* a7 */\r
-       lw  x18, 15 * WORD_SIZE( sp )   /* s2 */\r
-       lw  x19, 16 * WORD_SIZE( sp )   /* s3 */\r
-       lw  x20, 17 * WORD_SIZE( sp )   /* s4 */\r
-       lw  x21, 18 * WORD_SIZE( sp )   /* s5 */\r
-       lw  x22, 19 * WORD_SIZE( sp )   /* s6 */\r
-       lw  x23, 20 * WORD_SIZE( sp )   /* s7 */\r
-       lw  x24, 21 * WORD_SIZE( sp )   /* s8 */\r
-       lw  x25, 22 * WORD_SIZE( sp )   /* s9 */\r
-       lw  x26, 23 * WORD_SIZE( sp )   /* s10 */\r
-       lw  x27, 24 * WORD_SIZE( sp )   /* s11 */\r
-       lw  x28, 25 * WORD_SIZE( sp )   /* t3 */\r
-       lw  x29, 26 * WORD_SIZE( sp )   /* t4 */\r
-       lw  x30, 27 * WORD_SIZE( sp )   /* t5 */\r
-       lw  x31, 28 * WORD_SIZE( sp )   /* t6 */\r
-       addi    sp, sp, CONTEXT_SIZE\r
-       csrs    mstatus, 8                        /* Enable machine interrupts. */\r
-       ret\r
+.extern vPortHandleInterrupt\r
 \r
 /*-----------------------------------------------------------*/\r
 \r
@@ -152,7 +110,7 @@ test_if_timer:
 \r
        lui t0, 0x80000\r
        addi t1,t0, 7                                                   /* 0x80000007 == machine timer interrupt. */\r
-       bne a0, t1, as_yet_unhandled\r
+       bne a0, t1, test_if_external_interrupt\r
 \r
        lw t0, pullMachineTimerCompareRegister  /* Load address of compare register into t0. */\r
        lw t1, pullNextTime                                     /* Load the address of ullNextTime into t1. */\r
@@ -172,9 +130,15 @@ test_if_timer:
        jal vTaskSwitchContext\r
        j processed_source\r
 \r
-as_yet_unhandled:\r
-//     ebreak                                          /* External interrupt? */\r
-       j as_yet_unhandled\r
+test_if_external_interrupt:\r
+       addi t1, t1, 4                          /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */\r
+       bne a0, t1, is_exception                /* Only thing left it can be. */\r
+       jal vPortHandleInterrupt\r
+       j processed_source\r
+\r
+is_exception:\r
+       ebreak\r
+       j is_exception\r
 \r
 processed_source:\r
        lw  sp, pxCurrentTCB                                    /* Load pxCurrentTCB. */\r
@@ -219,5 +183,48 @@ processed_source:
        addi    sp, sp, CONTEXT_SIZE\r
 \r
        mret\r
+/*-----------------------------------------------------------*/\r
+\r
+.align 8\r
+xPortStartFirstTask:\r
+\r
+       la t0, vPortTrapHandler\r
+       csrw mtvec, t0\r
+\r
+       lw  sp, pxCurrentTCB                    /* Load pxCurrentTCB. */\r
+       lw  sp, 0( sp )                                 /* Read sp from first TCB member. */\r
+\r
+       lw  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */\r
+       lw  x5, 2 * WORD_SIZE( sp )             /* t0 */\r
+       lw  x6, 3 * WORD_SIZE( sp )             /* t1 */\r
+       lw  x7, 4 * WORD_SIZE( sp )             /* t2 */\r
+       lw  x8, 5 * WORD_SIZE( sp )             /* s0/fp */\r
+       lw  x9, 6 * WORD_SIZE( sp )             /* s1 */\r
+       lw  x10, 7 * WORD_SIZE( sp )    /* a0 */\r
+       lw  x11, 8 * WORD_SIZE( sp )    /* a1 */\r
+       lw  x12, 9 * WORD_SIZE( sp )    /* a2 */\r
+       lw  x13, 10 * WORD_SIZE( sp )   /* a3 */\r
+       lw  x14, 11 * WORD_SIZE( sp )   /* a4 */\r
+       lw  x15, 12 * WORD_SIZE( sp )   /* a5 */\r
+       lw  x16, 13 * WORD_SIZE( sp )   /* a6 */\r
+       lw  x17, 14 * WORD_SIZE( sp )   /* a7 */\r
+       lw  x18, 15 * WORD_SIZE( sp )   /* s2 */\r
+       lw  x19, 16 * WORD_SIZE( sp )   /* s3 */\r
+       lw  x20, 17 * WORD_SIZE( sp )   /* s4 */\r
+       lw  x21, 18 * WORD_SIZE( sp )   /* s5 */\r
+       lw  x22, 19 * WORD_SIZE( sp )   /* s6 */\r
+       lw  x23, 20 * WORD_SIZE( sp )   /* s7 */\r
+       lw  x24, 21 * WORD_SIZE( sp )   /* s8 */\r
+       lw  x25, 22 * WORD_SIZE( sp )   /* s9 */\r
+       lw  x26, 23 * WORD_SIZE( sp )   /* s10 */\r
+       lw  x27, 24 * WORD_SIZE( sp )   /* s11 */\r
+       lw  x28, 25 * WORD_SIZE( sp )   /* t3 */\r
+       lw  x29, 26 * WORD_SIZE( sp )   /* t4 */\r
+       lw  x30, 27 * WORD_SIZE( sp )   /* t5 */\r
+       lw  x31, 28 * WORD_SIZE( sp )   /* t6 */\r
+       addi    sp, sp, CONTEXT_SIZE\r
+       csrs    mstatus, 8                        /* Enable machine interrupts. */\r
+       ret\r
 \r
+/*-----------------------------------------------------------*/\r
 \r

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h
index c0c1b6b095bb9a07e3d7b6e7113f95bbdff762e1..65aa9cf5f341aff510dff917e220db568f06bcf7 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h
@@ -43,10 +43,6 @@ extern "C" {
  *-----------------------------------------------------------\r
  */\r
 \r
-#ifdef __riscv64\r
-       #error This is the RV32 port that supports 32-bit cores only.\r
-#endif\r
-\r
 /* Type definitions. */\r
 #define portSTACK_TYPE uint32_t\r
 #define portBASE_TYPE  long\r
@@ -65,7 +61,12 @@ not need to be guarded with a critical section. */
 /* Architecture specifics. */\r
 #define portSTACK_GROWTH                       ( -1 )\r
 #define portTICK_PERIOD_MS                     ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
-#define portBYTE_ALIGNMENT                     16\r
+#ifdef __riscv64\r
+       #error This is the RV32 port that has not yet been adapted for 64.\r
+       #define portBYTE_ALIGNMENT                      16\r
+#else\r
+       #define portBYTE_ALIGNMENT 8\r
+#endif\r
 /*-----------------------------------------------------------*/\r
 \r
 \r
@@ -79,15 +80,13 @@ extern void vTaskSwitchContext( void );
 \r
 /* Critical section management. */\r
 #define portCRITICAL_NESTING_IN_TCB                                    1\r
-extern int vPortSetInterruptMask( void );\r
-extern void vPortClearInterruptMask( int );\r
 extern void vTaskEnterCritical( void );\r
 extern void vTaskExitCritical( void );\r
 \r
 #define portSET_INTERRUPT_MASK_FROM_ISR() 0\r
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue\r
-#define portDISABLE_INTERRUPTS()       __asm volatile( "csrc mstatus, 8" ); __asm volatile( "fence" )\r
-#define portENABLE_INTERRUPTS()                __asm volatile( "csrs mstatus, 8" ); __asm volatile( "fence" )\r
+#define portDISABLE_INTERRUPTS()       __asm volatile( "csrc mstatus, 8" )\r
+#define portENABLE_INTERRUPTS()                __asm volatile( "csrs mstatus, 8" )\r
 #define portENTER_CRITICAL()   vTaskEnterCritical()\r
 #define portEXIT_CRITICAL()            vTaskExitCritical()\r
 \r