+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_adc.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the ADC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_ADC_H\r
-#define __STM32F10x_ADC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup ADC\r
- * @{\r
- */\r
-\r
-/** @defgroup ADC_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief ADC Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or\r
- dual mode. \r
- This parameter can be a value of @ref ADC_mode */\r
-\r
- FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in\r
- Scan (multichannels) or Single (one channel) mode.\r
- This parameter can be set to ENABLE or DISABLE */\r
-\r
- FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in\r
- Continuous or Single mode.\r
- This parameter can be set to ENABLE or DISABLE. */\r
-\r
- uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog\r
- to digital conversion of regular channels. This parameter\r
- can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */\r
-\r
- uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.\r
- This parameter can be a value of @ref ADC_data_align */\r
-\r
- uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted\r
- using the sequencer for regular channel group.\r
- This parameter must range from 1 to 16. */\r
-}ADC_InitTypeDef;\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \\r
- ((PERIPH) == ADC2) || \\r
- ((PERIPH) == ADC3))\r
-\r
-#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \\r
- ((PERIPH) == ADC3))\r
-\r
-/** @defgroup ADC_mode \r
- * @{\r
- */\r
-\r
-#define ADC_Mode_Independent ((uint32_t)0x00000000)\r
-#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)\r
-#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)\r
-#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)\r
-#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)\r
-#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)\r
-#define ADC_Mode_RegSimult ((uint32_t)0x00060000)\r
-#define ADC_Mode_FastInterl ((uint32_t)0x00070000)\r
-#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)\r
-#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)\r
-\r
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \\r
- ((MODE) == ADC_Mode_RegInjecSimult) || \\r
- ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \\r
- ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \\r
- ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \\r
- ((MODE) == ADC_Mode_InjecSimult) || \\r
- ((MODE) == ADC_Mode_RegSimult) || \\r
- ((MODE) == ADC_Mode_FastInterl) || \\r
- ((MODE) == ADC_Mode_SlowInterl) || \\r
- ((MODE) == ADC_Mode_AlterTrig))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion \r
- * @{\r
- */\r
-\r
-#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */\r
-\r
-#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */\r
-#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */\r
-\r
-#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */\r
-\r
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_None) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \\r
- ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_data_align \r
- * @{\r
- */\r
-\r
-#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
-#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
- ((ALIGN) == ADC_DataAlign_Left))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_channels \r
- * @{\r
- */\r
-\r
-#define ADC_Channel_0 ((uint8_t)0x00)\r
-#define ADC_Channel_1 ((uint8_t)0x01)\r
-#define ADC_Channel_2 ((uint8_t)0x02)\r
-#define ADC_Channel_3 ((uint8_t)0x03)\r
-#define ADC_Channel_4 ((uint8_t)0x04)\r
-#define ADC_Channel_5 ((uint8_t)0x05)\r
-#define ADC_Channel_6 ((uint8_t)0x06)\r
-#define ADC_Channel_7 ((uint8_t)0x07)\r
-#define ADC_Channel_8 ((uint8_t)0x08)\r
-#define ADC_Channel_9 ((uint8_t)0x09)\r
-#define ADC_Channel_10 ((uint8_t)0x0A)\r
-#define ADC_Channel_11 ((uint8_t)0x0B)\r
-#define ADC_Channel_12 ((uint8_t)0x0C)\r
-#define ADC_Channel_13 ((uint8_t)0x0D)\r
-#define ADC_Channel_14 ((uint8_t)0x0E)\r
-#define ADC_Channel_15 ((uint8_t)0x0F)\r
-#define ADC_Channel_16 ((uint8_t)0x10)\r
-#define ADC_Channel_17 ((uint8_t)0x11)\r
-\r
-#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r
-#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r
-\r
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \\r
- ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \\r
- ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \\r
- ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \\r
- ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \\r
- ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \\r
- ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \\r
- ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \\r
- ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_sampling_time \r
- * @{\r
- */\r
-\r
-#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)\r
-#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)\r
-#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)\r
-#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)\r
-#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)\r
-#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)\r
-#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)\r
-#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)\r
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \\r
- ((TIME) == ADC_SampleTime_7Cycles5) || \\r
- ((TIME) == ADC_SampleTime_13Cycles5) || \\r
- ((TIME) == ADC_SampleTime_28Cycles5) || \\r
- ((TIME) == ADC_SampleTime_41Cycles5) || \\r
- ((TIME) == ADC_SampleTime_55Cycles5) || \\r
- ((TIME) == ADC_SampleTime_71Cycles5) || \\r
- ((TIME) == ADC_SampleTime_239Cycles5))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion \r
- * @{\r
- */\r
-\r
-#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */\r
-#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */\r
-\r
-#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */\r
-#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */\r
-#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */\r
-\r
-#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */\r
-#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */\r
-\r
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \\r
- ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_injected_channel_selection \r
- * @{\r
- */\r
-\r
-#define ADC_InjectedChannel_1 ((uint8_t)0x14)\r
-#define ADC_InjectedChannel_2 ((uint8_t)0x18)\r
-#define ADC_InjectedChannel_3 ((uint8_t)0x1C)\r
-#define ADC_InjectedChannel_4 ((uint8_t)0x20)\r
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
- ((CHANNEL) == ADC_InjectedChannel_2) || \\r
- ((CHANNEL) == ADC_InjectedChannel_3) || \\r
- ((CHANNEL) == ADC_InjectedChannel_4))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_analog_watchdog_selection \r
- * @{\r
- */\r
-\r
-#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r
-#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)\r
-#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r
-#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r
-#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r
-\r
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
- ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define ADC_IT_EOC ((uint16_t)0x0220)\r
-#define ADC_IT_AWD ((uint16_t)0x0140)\r
-#define ADC_IT_JEOC ((uint16_t)0x0480)\r
-\r
-#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))\r
-\r
-#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \\r
- ((IT) == ADC_IT_JEOC))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_flags_definition \r
- * @{\r
- */\r
-\r
-#define ADC_FLAG_AWD ((uint8_t)0x01)\r
-#define ADC_FLAG_EOC ((uint8_t)0x02)\r
-#define ADC_FLAG_JEOC ((uint8_t)0x04)\r
-#define ADC_FLAG_JSTRT ((uint8_t)0x08)\r
-#define ADC_FLAG_STRT ((uint8_t)0x10)\r
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))\r
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \\r
- ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \\r
- ((FLAG) == ADC_FLAG_STRT))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_thresholds \r
- * @{\r
- */\r
-\r
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_injected_offset \r
- * @{\r
- */\r
-\r
-#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_injected_length \r
- * @{\r
- */\r
-\r
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_injected_rank \r
- * @{\r
- */\r
-\r
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup ADC_regular_length \r
- * @{\r
- */\r
-\r
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_regular_rank \r
- * @{\r
- */\r
-\r
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_regular_discontinuous_mode_number \r
- * @{\r
- */\r
-\r
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void ADC_DeInit(ADC_TypeDef* ADCx);\r
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r
-void ADC_ResetCalibration(ADC_TypeDef* ADCx);\r
-FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);\r
-void ADC_StartCalibration(ADC_TypeDef* ADCx);\r
-FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);\r
-void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
-void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
-uint32_t ADC_GetDualModeConversionValue(void);\r
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r
-void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);\r
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r
-void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_ADC_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_bkp.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the BKP firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_BKP_H\r
-#define __STM32F10x_BKP_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup BKP\r
- * @{\r
- */\r
-\r
-/** @defgroup BKP_Exported_Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup Tamper_Pin_active_level \r
- * @{\r
- */\r
-\r
-#define BKP_TamperPinLevel_High ((uint16_t)0x0000)\r
-#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)\r
-#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \\r
- ((LEVEL) == BKP_TamperPinLevel_Low))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin \r
- * @{\r
- */\r
-\r
-#define BKP_RTCOutputSource_None ((uint16_t)0x0000)\r
-#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)\r
-#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)\r
-#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)\r
-#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \\r
- ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \\r
- ((SOURCE) == BKP_RTCOutputSource_Alarm) || \\r
- ((SOURCE) == BKP_RTCOutputSource_Second))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Data_Backup_Register \r
- * @{\r
- */\r
-\r
-#define BKP_DR1 ((uint16_t)0x0004)\r
-#define BKP_DR2 ((uint16_t)0x0008)\r
-#define BKP_DR3 ((uint16_t)0x000C)\r
-#define BKP_DR4 ((uint16_t)0x0010)\r
-#define BKP_DR5 ((uint16_t)0x0014)\r
-#define BKP_DR6 ((uint16_t)0x0018)\r
-#define BKP_DR7 ((uint16_t)0x001C)\r
-#define BKP_DR8 ((uint16_t)0x0020)\r
-#define BKP_DR9 ((uint16_t)0x0024)\r
-#define BKP_DR10 ((uint16_t)0x0028)\r
-#define BKP_DR11 ((uint16_t)0x0040)\r
-#define BKP_DR12 ((uint16_t)0x0044)\r
-#define BKP_DR13 ((uint16_t)0x0048)\r
-#define BKP_DR14 ((uint16_t)0x004C)\r
-#define BKP_DR15 ((uint16_t)0x0050)\r
-#define BKP_DR16 ((uint16_t)0x0054)\r
-#define BKP_DR17 ((uint16_t)0x0058)\r
-#define BKP_DR18 ((uint16_t)0x005C)\r
-#define BKP_DR19 ((uint16_t)0x0060)\r
-#define BKP_DR20 ((uint16_t)0x0064)\r
-#define BKP_DR21 ((uint16_t)0x0068)\r
-#define BKP_DR22 ((uint16_t)0x006C)\r
-#define BKP_DR23 ((uint16_t)0x0070)\r
-#define BKP_DR24 ((uint16_t)0x0074)\r
-#define BKP_DR25 ((uint16_t)0x0078)\r
-#define BKP_DR26 ((uint16_t)0x007C)\r
-#define BKP_DR27 ((uint16_t)0x0080)\r
-#define BKP_DR28 ((uint16_t)0x0084)\r
-#define BKP_DR29 ((uint16_t)0x0088)\r
-#define BKP_DR30 ((uint16_t)0x008C)\r
-#define BKP_DR31 ((uint16_t)0x0090)\r
-#define BKP_DR32 ((uint16_t)0x0094)\r
-#define BKP_DR33 ((uint16_t)0x0098)\r
-#define BKP_DR34 ((uint16_t)0x009C)\r
-#define BKP_DR35 ((uint16_t)0x00A0)\r
-#define BKP_DR36 ((uint16_t)0x00A4)\r
-#define BKP_DR37 ((uint16_t)0x00A8)\r
-#define BKP_DR38 ((uint16_t)0x00AC)\r
-#define BKP_DR39 ((uint16_t)0x00B0)\r
-#define BKP_DR40 ((uint16_t)0x00B4)\r
-#define BKP_DR41 ((uint16_t)0x00B8)\r
-#define BKP_DR42 ((uint16_t)0x00BC)\r
-\r
-#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \\r
- ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \\r
- ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \\r
- ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \\r
- ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \\r
- ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \\r
- ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \\r
- ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \\r
- ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \\r
- ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \\r
- ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \\r
- ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \\r
- ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \\r
- ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))\r
-\r
-#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Exported_Functions\r
- * @{\r
- */\r
-\r
-void BKP_DeInit(void);\r
-void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);\r
-void BKP_TamperPinCmd(FunctionalState NewState);\r
-void BKP_ITConfig(FunctionalState NewState);\r
-void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);\r
-void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);\r
-void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);\r
-uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);\r
-FlagStatus BKP_GetFlagStatus(void);\r
-void BKP_ClearFlag(void);\r
-ITStatus BKP_GetITStatus(void);\r
-void BKP_ClearITPendingBit(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_BKP_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_can.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the CAN firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_CAN_H\r
-#define __STM32F10x_CAN_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup CAN\r
- * @{\r
- */\r
-\r
-/** @defgroup CAN_Exported_Types\r
- * @{\r
- */\r
-\r
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \\r
- ((PERIPH) == CAN2))\r
-\r
-/** \r
- * @brief CAN init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */\r
- \r
- uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.\r
- This parameter can be a value of @ref CAN_operating_mode */\r
-\r
- uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware\r
- is allowed to lengthen or shorten a bit to perform resynchronization.\r
- This parameter can be a value of @ref CAN_synchronisation_jump_width */\r
-\r
- uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1.\r
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */\r
-\r
- uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.\r
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */\r
- \r
- FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
- \r
- FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
-\r
- FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. \r
- This parameter can be set either to ENABLE or DISABLE. */\r
-\r
- FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
-\r
- FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
-\r
- FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
-} CAN_InitTypeDef;\r
-\r
-/** \r
- * @brief CAN filter init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit\r
- configuration, first one for a 16-bit configuration).\r
- This parameter can be a value between 0x0000 and 0xFFFF */\r
-\r
- uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit\r
- configuration, second one for a 16-bit configuration).\r
- This parameter can be a value between 0x0000 and 0xFFFF */\r
-\r
- uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,\r
- according to the mode (MSBs for a 32-bit configuration,\r
- first one for a 16-bit configuration).\r
- This parameter can be a value between 0x0000 and 0xFFFF */\r
-\r
- uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,\r
- according to the mode (LSBs for a 32-bit configuration,\r
- second one for a 16-bit configuration).\r
- This parameter can be a value between 0x0000 and 0xFFFF */\r
-\r
- uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.\r
- This parameter can be a value of @ref CAN_filter_FIFO */\r
- \r
- uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */\r
-\r
- uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.\r
- This parameter can be a value of @ref CAN_filter_mode */\r
-\r
- uint8_t CAN_FilterScale; /*!< Specifies the filter scale.\r
- This parameter can be a value of @ref CAN_filter_scale */\r
-\r
- FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.\r
- This parameter can be set either to ENABLE or DISABLE. */\r
-} CAN_FilterInitTypeDef;\r
-\r
-/** \r
- * @brief CAN Tx message structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t StdId; /*!< Specifies the standard identifier.\r
- This parameter can be a value between 0 to 0x7FF. */\r
-\r
- uint32_t ExtId; /*!< Specifies the extended identifier.\r
- This parameter can be a value between 0 to 0x1FFFFFFF. */\r
-\r
- uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.\r
- This parameter can be a value of @ref CAN_identifier_type */\r
-\r
- uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.\r
- This parameter can be a value of @ref CAN_remote_transmission_request */\r
-\r
- uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted.\r
- This parameter can be a value between 0 to 8 */\r
-\r
- uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */\r
-} CanTxMsg;\r
-\r
-/** \r
- * @brief CAN Rx message structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t StdId; /*!< Specifies the standard identifier.\r
- This parameter can be a value between 0 to 0x7FF. */\r
-\r
- uint32_t ExtId; /*!< Specifies the extended identifier.\r
- This parameter can be a value between 0 to 0x1FFFFFFF. */\r
-\r
- uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received.\r
- This parameter can be a value of @ref CAN_identifier_type */\r
-\r
- uint8_t RTR; /*!< Specifies the type of frame for the received message.\r
- This parameter can be a value of @ref CAN_remote_transmission_request */\r
-\r
- uint8_t DLC; /*!< Specifies the length of the frame that will be received.\r
- This parameter can be a value between 0 to 8 */\r
-\r
- uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */\r
-\r
- uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.\r
- This parameter can be a value between 0 to 0xFF */\r
-} CanRxMsg;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup CAN_sleep_constants \r
- * @{\r
- */\r
-\r
-#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */\r
-#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_operating_mode \r
- * @{\r
- */\r
-\r
-#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */\r
-#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */\r
-#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */\r
-#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */\r
-\r
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \\r
- ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_synchronisation_jump_width \r
- * @{\r
- */\r
-\r
-#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
-#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
-#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
-#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
-\r
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \\r
- ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_time_quantum_in_bit_segment_1 \r
- * @{\r
- */\r
-\r
-#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
-#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
-#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
-#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
-#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r
-#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r
-#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r
-#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r
-#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */\r
-#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */\r
-#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */\r
-#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */\r
-#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */\r
-#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */\r
-#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */\r
-#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */\r
-\r
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_time_quantum_in_bit_segment_2 \r
- * @{\r
- */\r
-\r
-#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
-#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
-#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
-#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
-#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r
-#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r
-#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r
-#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r
-\r
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_clock_prescaler \r
- * @{\r
- */\r
-\r
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_filter_number \r
- * @{\r
- */\r
-#ifndef STM32F10X_CL\r
- #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)\r
-#else\r
- #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)\r
-#endif /* STM32F10X_CL */ \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_filter_mode \r
- * @{\r
- */\r
-\r
-#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */\r
-#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */\r
-\r
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \\r
- ((MODE) == CAN_FilterMode_IdList))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_filter_scale \r
- * @{\r
- */\r
-\r
-#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */\r
-#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */\r
-\r
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \\r
- ((SCALE) == CAN_FilterScale_32bit))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_filter_FIFO\r
- * @{\r
- */\r
-\r
-#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */\r
-#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */\r
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \\r
- ((FIFO) == CAN_FilterFIFO1))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Start_bank_filter_for_slave_CAN \r
- * @{\r
- */\r
-#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Tx \r
- * @{\r
- */\r
-\r
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))\r
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))\r
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))\r
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_identifier_type \r
- * @{\r
- */\r
-\r
-#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */\r
-#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */\r
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_remote_transmission_request \r
- * @{\r
- */\r
-\r
-#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */\r
-#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */\r
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_transmit_constants \r
- * @{\r
- */\r
-\r
-#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */\r
-#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */\r
-#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */\r
-#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_receive_FIFO_number_constants \r
- * @{\r
- */\r
-\r
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */\r
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */\r
-\r
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_sleep_constants \r
- * @{\r
- */\r
-\r
-#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */\r
-#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_wake_up_constants \r
- * @{\r
- */\r
-\r
-#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */\r
-#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_flags \r
- * @{\r
- */\r
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()\r
- and CAN_ClearFlag() functions. */\r
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */\r
-\r
-/* Transmit Flags */\r
-#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */\r
-#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */\r
-#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */\r
-\r
-/* Receive Flags */\r
-#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */\r
-#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */\r
-#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */\r
-#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */\r
-#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */\r
-#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */\r
-\r
-/* Operating Mode Flags */\r
-#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */\r
-#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */\r
-/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. \r
- In this case the SLAK bit can be polled.*/\r
-\r
-/* Error Flags */\r
-#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */\r
-#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */\r
-#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */\r
-#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */\r
-\r
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \\r
- ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \\r
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \\r
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \\r
- ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \\r
- ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \\r
- ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \\r
- ((FLAG) == CAN_FLAG_SLAK ))\r
-\r
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \\r
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \\r
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\\r
- ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \\r
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))\r
-/**\r
- * @}\r
- */\r
-\r
- \r
-/** @defgroup CAN_interrupts \r
- * @{\r
- */\r
-\r
-\r
- \r
-#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/\r
-\r
-/* Receive Interrupts */\r
-#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/\r
-#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/\r
-#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/\r
-#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/\r
-#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/\r
-#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/\r
-\r
-/* Operating Mode Interrupts */\r
-#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/\r
-#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/\r
-\r
-/* Error Interrupts */\r
-#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/\r
-#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/\r
-#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/\r
-#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/\r
-#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/\r
-\r
-/* Flags named as Interrupts : kept only for FW compatibility */\r
-#define CAN_IT_RQCP0 CAN_IT_TME\r
-#define CAN_IT_RQCP1 CAN_IT_TME\r
-#define CAN_IT_RQCP2 CAN_IT_TME\r
-\r
-\r
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\\r
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\\r
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\\r
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
-\r
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\\r
- ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\\r
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Exported_Functions\r
- * @{\r
- */\r
-\r
-void CAN_DeInit(CAN_TypeDef* CANx);\r
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);\r
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);\r
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);\r
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber); \r
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);\r
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);\r
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);\r
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);\r
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);\r
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);\r
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);\r
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);\r
-uint8_t CAN_Sleep(CAN_TypeDef* CANx);\r
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx);\r
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);\r
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_CAN_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_cec.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the CEC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_CEC_H\r
-#define __STM32F10x_CEC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup CEC\r
- * @{\r
- */\r
- \r
-\r
-/** @defgroup CEC_Exported_Types\r
- * @{\r
- */\r
- \r
-/** \r
- * @brief CEC Init structure definition \r
- */ \r
-typedef struct\r
-{\r
- uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. \r
- This parameter can be a value of @ref CEC_BitTiming_Mode */\r
- uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. \r
- This parameter can be a value of @ref CEC_BitPeriod_Mode */\r
-}CEC_InitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CEC_Exported_Constants\r
- * @{\r
- */ \r
- \r
-/** @defgroup CEC_BitTiming_Mode \r
- * @{\r
- */ \r
-#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */\r
-#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */\r
-\r
-#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \\r
- ((MODE) == CEC_BitTimingErrFreeMode))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CEC_BitPeriod_Mode \r
- * @{\r
- */ \r
-#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */\r
-#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */\r
-\r
-#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \\r
- ((MODE) == CEC_BitPeriodFlexibleMode))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_interrupts_definition \r
- * @{\r
- */ \r
-#define CEC_IT_TERR CEC_CSR_TERR\r
-#define CEC_IT_TBTRF CEC_CSR_TBTRF\r
-#define CEC_IT_RERR CEC_CSR_RERR\r
-#define CEC_IT_RBTF CEC_CSR_RBTF\r
-#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \\r
- ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_Own_Addres \r
- * @{\r
- */ \r
-#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup CEC_Prescaler \r
- * @{\r
- */ \r
-#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CEC_flags_definition \r
- * @{\r
- */\r
- \r
-/** \r
- * @brief ESR register flags \r
- */ \r
-#define CEC_FLAG_BTE ((uint32_t)0x10010000)\r
-#define CEC_FLAG_BPE ((uint32_t)0x10020000)\r
-#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)\r
-#define CEC_FLAG_SBE ((uint32_t)0x10080000)\r
-#define CEC_FLAG_ACKE ((uint32_t)0x10100000)\r
-#define CEC_FLAG_LINE ((uint32_t)0x10200000)\r
-#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)\r
-\r
-/** \r
- * @brief CSR register flags \r
- */ \r
-#define CEC_FLAG_TEOM ((uint32_t)0x00000002) \r
-#define CEC_FLAG_TERR ((uint32_t)0x00000004)\r
-#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)\r
-#define CEC_FLAG_RSOM ((uint32_t)0x00000010)\r
-#define CEC_FLAG_REOM ((uint32_t)0x00000020)\r
-#define CEC_FLAG_RERR ((uint32_t)0x00000040)\r
-#define CEC_FLAG_RBTF ((uint32_t)0x00000080)\r
-\r
-#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))\r
- \r
-#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \\r
- ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \\r
- ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \\r
- ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \\r
- ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \\r
- ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \\r
- ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup CEC_Exported_Macros\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CEC_Exported_Functions\r
- * @{\r
- */ \r
-void CEC_DeInit(void);\r
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);\r
-void CEC_Cmd(FunctionalState NewState);\r
-void CEC_ITConfig(FunctionalState NewState);\r
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);\r
-void CEC_SetPrescaler(uint16_t CEC_Prescaler);\r
-void CEC_SendDataByte(uint8_t Data);\r
-uint8_t CEC_ReceiveDataByte(void);\r
-void CEC_StartOfMessage(void);\r
-void CEC_EndOfMessageCmd(FunctionalState NewState);\r
-FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);\r
-void CEC_ClearFlag(uint32_t CEC_FLAG);\r
-ITStatus CEC_GetITStatus(uint8_t CEC_IT);\r
-void CEC_ClearITPendingBit(uint16_t CEC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_CEC_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_crc.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the CRC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_CRC_H\r
-#define __STM32F10x_CRC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup CRC\r
- * @{\r
- */\r
-\r
-/** @defgroup CRC_Exported_Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void CRC_ResetDR(void);\r
-uint32_t CRC_CalcCRC(uint32_t Data);\r
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
-uint32_t CRC_GetCRC(void);\r
-void CRC_SetIDRegister(uint8_t IDValue);\r
-uint8_t CRC_GetIDRegister(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_CRC_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dac.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the DAC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_DAC_H\r
-#define __STM32F10x_DAC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DAC\r
- * @{\r
- */\r
-\r
-/** @defgroup DAC_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief DAC Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
- This parameter can be a value of @ref DAC_trigger_selection */\r
-\r
- uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves\r
- are generated, or whether no wave is generated.\r
- This parameter can be a value of @ref DAC_wave_generation */\r
-\r
- uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or\r
- the maximum amplitude triangle generation for the DAC channel. \r
- This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */\r
-\r
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
- This parameter can be a value of @ref DAC_output_buffer */\r
-}DAC_InitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup DAC_trigger_selection \r
- * @{\r
- */\r
-\r
-#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
- has been loaded, and not by external trigger */\r
-#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel\r
- only in High-density devices*/\r
-#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel\r
- only in Connectivity line, Medium-density and Low-density Value Line devices */\r
-#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel \r
- only in Medium-density and Low-density Value Line devices*/\r
-#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
-#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r
-\r
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
- ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T8_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T5_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
- ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
- ((TRIGGER) == DAC_Trigger_Software))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_wave_generation \r
- * @{\r
- */\r
-\r
-#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r
-#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r
-#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
- ((WAVE) == DAC_WaveGeneration_Noise) || \\r
- ((WAVE) == DAC_WaveGeneration_Triangle))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_lfsrunmask_triangleamplitude\r
- * @{\r
- */\r
-\r
-#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r
-#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r
-#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r
-#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */\r
-#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */\r
-#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */\r
-#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */\r
-#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */\r
-#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */\r
-#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */\r
-#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */\r
-#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */\r
-#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */\r
-#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */\r
-\r
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
- ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
- ((VALUE) == DAC_TriangleAmplitude_1) || \\r
- ((VALUE) == DAC_TriangleAmplitude_3) || \\r
- ((VALUE) == DAC_TriangleAmplitude_7) || \\r
- ((VALUE) == DAC_TriangleAmplitude_15) || \\r
- ((VALUE) == DAC_TriangleAmplitude_31) || \\r
- ((VALUE) == DAC_TriangleAmplitude_63) || \\r
- ((VALUE) == DAC_TriangleAmplitude_127) || \\r
- ((VALUE) == DAC_TriangleAmplitude_255) || \\r
- ((VALUE) == DAC_TriangleAmplitude_511) || \\r
- ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
- ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
- ((VALUE) == DAC_TriangleAmplitude_4095))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_output_buffer \r
- * @{\r
- */\r
-\r
-#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
-#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
- ((STATE) == DAC_OutputBuffer_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Channel_selection \r
- * @{\r
- */\r
-\r
-#define DAC_Channel_1 ((uint32_t)0x00000000)\r
-#define DAC_Channel_2 ((uint32_t)0x00000010)\r
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
- ((CHANNEL) == DAC_Channel_2))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_data_alignement \r
- * @{\r
- */\r
-\r
-#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
-#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
-#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
- ((ALIGN) == DAC_Align_12b_L) || \\r
- ((ALIGN) == DAC_Align_8b_R))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_wave_generation \r
- * @{\r
- */\r
-\r
-#define DAC_Wave_Noise ((uint32_t)0x00000040)\r
-#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
- ((WAVE) == DAC_Wave_Triangle))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_data \r
- * @{\r
- */\r
-\r
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
-/**\r
- * @}\r
- */\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
-/** @defgroup DAC_interrupts_definition \r
- * @{\r
- */ \r
- \r
-#define DAC_IT_DMAUDR ((uint32_t)0x00002000) \r
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup DAC_flags_definition \r
- * @{\r
- */ \r
- \r
-#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) \r
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) \r
-\r
-/**\r
- * @}\r
- */\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void DAC_DeInit(void);\r
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r
-#endif\r
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) \r
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r
-#endif\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_DAC_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dbgmcu.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the DBGMCU \r
- * firmware library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_DBGMCU_H\r
-#define __STM32F10x_DBGMCU_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DBGMCU\r
- * @{\r
- */\r
-\r
-/** @defgroup DBGMCU_Exported_Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r
-#define DBGMCU_STOP ((uint32_t)0x00000002)\r
-#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r
-#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)\r
-#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)\r
-#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)\r
-#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)\r
-#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)\r
-#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)\r
-#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)\r
-#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)\r
-#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)\r
-#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)\r
-#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)\r
-#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)\r
-#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)\r
-#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)\r
-#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)\r
-#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)\r
-#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)\r
-#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)\r
-#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)\r
-#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)\r
-#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)\r
-#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)\r
-#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)\r
- \r
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup DBGMCU_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Exported_Functions\r
- * @{\r
- */\r
-\r
-uint32_t DBGMCU_GetREVID(void);\r
-uint32_t DBGMCU_GetDEVID(void);\r
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_DBGMCU_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dma.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the DMA firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_DMA_H\r
-#define __STM32F10x_DMA_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup DMA\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief DMA Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */\r
-\r
- uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */\r
-\r
- uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.\r
- This parameter can be a value of @ref DMA_data_transfer_direction */\r
-\r
- uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. \r
- The data unit is equal to the configuration set in DMA_PeripheralDataSize\r
- or DMA_MemoryDataSize members depending in the transfer direction. */\r
-\r
- uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.\r
- This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r
-\r
- uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.\r
- This parameter can be a value of @ref DMA_memory_incremented_mode */\r
-\r
- uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r
- This parameter can be a value of @ref DMA_peripheral_data_size */\r
-\r
- uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r
- This parameter can be a value of @ref DMA_memory_data_size */\r
-\r
- uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
- This parameter can be a value of @ref DMA_circular_normal_mode.\r
- @note: The circular buffer mode cannot be used if the memory-to-memory\r
- data transfer is configured on the selected Channel */\r
-\r
- uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
- This parameter can be a value of @ref DMA_priority_level */\r
-\r
- uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.\r
- This parameter can be a value of @ref DMA_memory_to_memory */\r
-}DMA_InitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \\r
- ((PERIPH) == DMA1_Channel2) || \\r
- ((PERIPH) == DMA1_Channel3) || \\r
- ((PERIPH) == DMA1_Channel4) || \\r
- ((PERIPH) == DMA1_Channel5) || \\r
- ((PERIPH) == DMA1_Channel6) || \\r
- ((PERIPH) == DMA1_Channel7) || \\r
- ((PERIPH) == DMA2_Channel1) || \\r
- ((PERIPH) == DMA2_Channel2) || \\r
- ((PERIPH) == DMA2_Channel3) || \\r
- ((PERIPH) == DMA2_Channel4) || \\r
- ((PERIPH) == DMA2_Channel5))\r
-\r
-/** @defgroup DMA_data_transfer_direction \r
- * @{\r
- */\r
-\r
-#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)\r
-#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)\r
-#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \\r
- ((DIR) == DMA_DIR_PeripheralSRC))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_peripheral_incremented_mode \r
- * @{\r
- */\r
-\r
-#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)\r
-#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\r
- ((STATE) == DMA_PeripheralInc_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_incremented_mode \r
- * @{\r
- */\r
-\r
-#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)\r
-#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\r
- ((STATE) == DMA_MemoryInc_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_peripheral_data_size \r
- * @{\r
- */\r
-\r
-#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)\r
-#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)\r
-#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)\r
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
- ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
- ((SIZE) == DMA_PeripheralDataSize_Word))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_data_size \r
- * @{\r
- */\r
-\r
-#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)\r
-#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)\r
-#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)\r
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
- ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
- ((SIZE) == DMA_MemoryDataSize_Word))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_circular_normal_mode \r
- * @{\r
- */\r
-\r
-#define DMA_Mode_Circular ((uint32_t)0x00000020)\r
-#define DMA_Mode_Normal ((uint32_t)0x00000000)\r
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_priority_level \r
- * @{\r
- */\r
-\r
-#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)\r
-#define DMA_Priority_High ((uint32_t)0x00002000)\r
-#define DMA_Priority_Medium ((uint32_t)0x00001000)\r
-#define DMA_Priority_Low ((uint32_t)0x00000000)\r
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \\r
- ((PRIORITY) == DMA_Priority_High) || \\r
- ((PRIORITY) == DMA_Priority_Medium) || \\r
- ((PRIORITY) == DMA_Priority_Low))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_memory_to_memory \r
- * @{\r
- */\r
-\r
-#define DMA_M2M_Enable ((uint32_t)0x00004000)\r
-#define DMA_M2M_Disable ((uint32_t)0x00000000)\r
-#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define DMA_IT_TC ((uint32_t)0x00000002)\r
-#define DMA_IT_HT ((uint32_t)0x00000004)\r
-#define DMA_IT_TE ((uint32_t)0x00000008)\r
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))\r
-\r
-#define DMA1_IT_GL1 ((uint32_t)0x00000001)\r
-#define DMA1_IT_TC1 ((uint32_t)0x00000002)\r
-#define DMA1_IT_HT1 ((uint32_t)0x00000004)\r
-#define DMA1_IT_TE1 ((uint32_t)0x00000008)\r
-#define DMA1_IT_GL2 ((uint32_t)0x00000010)\r
-#define DMA1_IT_TC2 ((uint32_t)0x00000020)\r
-#define DMA1_IT_HT2 ((uint32_t)0x00000040)\r
-#define DMA1_IT_TE2 ((uint32_t)0x00000080)\r
-#define DMA1_IT_GL3 ((uint32_t)0x00000100)\r
-#define DMA1_IT_TC3 ((uint32_t)0x00000200)\r
-#define DMA1_IT_HT3 ((uint32_t)0x00000400)\r
-#define DMA1_IT_TE3 ((uint32_t)0x00000800)\r
-#define DMA1_IT_GL4 ((uint32_t)0x00001000)\r
-#define DMA1_IT_TC4 ((uint32_t)0x00002000)\r
-#define DMA1_IT_HT4 ((uint32_t)0x00004000)\r
-#define DMA1_IT_TE4 ((uint32_t)0x00008000)\r
-#define DMA1_IT_GL5 ((uint32_t)0x00010000)\r
-#define DMA1_IT_TC5 ((uint32_t)0x00020000)\r
-#define DMA1_IT_HT5 ((uint32_t)0x00040000)\r
-#define DMA1_IT_TE5 ((uint32_t)0x00080000)\r
-#define DMA1_IT_GL6 ((uint32_t)0x00100000)\r
-#define DMA1_IT_TC6 ((uint32_t)0x00200000)\r
-#define DMA1_IT_HT6 ((uint32_t)0x00400000)\r
-#define DMA1_IT_TE6 ((uint32_t)0x00800000)\r
-#define DMA1_IT_GL7 ((uint32_t)0x01000000)\r
-#define DMA1_IT_TC7 ((uint32_t)0x02000000)\r
-#define DMA1_IT_HT7 ((uint32_t)0x04000000)\r
-#define DMA1_IT_TE7 ((uint32_t)0x08000000)\r
-\r
-#define DMA2_IT_GL1 ((uint32_t)0x10000001)\r
-#define DMA2_IT_TC1 ((uint32_t)0x10000002)\r
-#define DMA2_IT_HT1 ((uint32_t)0x10000004)\r
-#define DMA2_IT_TE1 ((uint32_t)0x10000008)\r
-#define DMA2_IT_GL2 ((uint32_t)0x10000010)\r
-#define DMA2_IT_TC2 ((uint32_t)0x10000020)\r
-#define DMA2_IT_HT2 ((uint32_t)0x10000040)\r
-#define DMA2_IT_TE2 ((uint32_t)0x10000080)\r
-#define DMA2_IT_GL3 ((uint32_t)0x10000100)\r
-#define DMA2_IT_TC3 ((uint32_t)0x10000200)\r
-#define DMA2_IT_HT3 ((uint32_t)0x10000400)\r
-#define DMA2_IT_TE3 ((uint32_t)0x10000800)\r
-#define DMA2_IT_GL4 ((uint32_t)0x10001000)\r
-#define DMA2_IT_TC4 ((uint32_t)0x10002000)\r
-#define DMA2_IT_HT4 ((uint32_t)0x10004000)\r
-#define DMA2_IT_TE4 ((uint32_t)0x10008000)\r
-#define DMA2_IT_GL5 ((uint32_t)0x10010000)\r
-#define DMA2_IT_TC5 ((uint32_t)0x10020000)\r
-#define DMA2_IT_HT5 ((uint32_t)0x10040000)\r
-#define DMA2_IT_TE5 ((uint32_t)0x10080000)\r
-\r
-#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))\r
-\r
-#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \\r
- ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \\r
- ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \\r
- ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \\r
- ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \\r
- ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \\r
- ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \\r
- ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \\r
- ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \\r
- ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \\r
- ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \\r
- ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \\r
- ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \\r
- ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \\r
- ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \\r
- ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \\r
- ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \\r
- ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \\r
- ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \\r
- ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \\r
- ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \\r
- ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \\r
- ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \\r
- ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_flags_definition \r
- * @{\r
- */\r
-#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)\r
-#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)\r
-#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)\r
-#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)\r
-#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)\r
-#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)\r
-#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)\r
-#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)\r
-#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)\r
-#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)\r
-#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)\r
-#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)\r
-#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)\r
-#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)\r
-#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)\r
-#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)\r
-#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)\r
-#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)\r
-#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)\r
-#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)\r
-#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)\r
-#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)\r
-#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)\r
-#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)\r
-#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)\r
-#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)\r
-#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)\r
-#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)\r
-\r
-#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)\r
-#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)\r
-#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)\r
-#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)\r
-#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)\r
-#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)\r
-#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)\r
-#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)\r
-#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)\r
-#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)\r
-#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)\r
-#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)\r
-#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)\r
-#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)\r
-#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)\r
-#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)\r
-#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)\r
-#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)\r
-#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)\r
-#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)\r
-\r
-#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))\r
-\r
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \\r
- ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \\r
- ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \\r
- ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \\r
- ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \\r
- ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \\r
- ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \\r
- ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \\r
- ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \\r
- ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \\r
- ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \\r
- ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \\r
- ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \\r
- ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \\r
- ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \\r
- ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \\r
- ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \\r
- ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \\r
- ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \\r
- ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \\r
- ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \\r
- ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \\r
- ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \\r
- ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Buffer_Size \r
- * @{\r
- */\r
-\r
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Exported_Functions\r
- * @{\r
- */\r
-\r
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);\r
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);\r
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); \r
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
-void DMA_ClearFlag(uint32_t DMA_FLAG);\r
-ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
-void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_DMA_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_flash.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the FLASH \r
- * firmware library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_FLASH_H\r
-#define __STM32F10x_FLASH_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup FLASH\r
- * @{\r
- */\r
-\r
-/** @defgroup FLASH_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief FLASH Status \r
- */\r
-\r
-typedef enum\r
-{ \r
- FLASH_BUSY = 1,\r
- FLASH_ERROR_PG,\r
- FLASH_ERROR_WRP,\r
- FLASH_COMPLETE,\r
- FLASH_TIMEOUT\r
-}FLASH_Status;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup Flash_Latency \r
- * @{\r
- */\r
-\r
-#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */\r
-#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */\r
-#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */\r
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
- ((LATENCY) == FLASH_Latency_1) || \\r
- ((LATENCY) == FLASH_Latency_2))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Half_Cycle_Enable_Disable \r
- * @{\r
- */\r
-\r
-#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */\r
-#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */\r
-#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \\r
- ((STATE) == FLASH_HalfCycleAccess_Disable)) \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Prefetch_Buffer_Enable_Disable \r
- * @{\r
- */\r
-\r
-#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */\r
-#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */\r
-#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \\r
- ((STATE) == FLASH_PrefetchBuffer_Disable)) \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_Write_Protection \r
- * @{\r
- */\r
-\r
-/* Values to be used with STM32 Low and Medium density devices */\r
-#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */\r
-#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */\r
-#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */\r
-#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */\r
-#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */\r
-#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */\r
-#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */\r
-#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */\r
-\r
-/* Values to be used with STM32 Medium-density devices */\r
-#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */\r
-#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */\r
-#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */\r
-#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */\r
-#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */\r
-#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */\r
-#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */\r
-#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */\r
-#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */\r
-#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */\r
-#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */\r
-#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */\r
-#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */\r
-#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */\r
-#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */\r
-#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */\r
-#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */\r
-#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */\r
-#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */\r
-#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */\r
-#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */\r
-#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */\r
-#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */\r
-#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */\r
-\r
-/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */\r
-#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 0 to 1 */\r
-#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 2 to 3 */\r
-#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 4 to 5 */\r
-#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 6 to 7 */\r
-#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 8 to 9 */\r
-#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 10 to 11 */\r
-#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 12 to 13 */\r
-#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 14 to 15 */\r
-#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 16 to 17 */\r
-#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 18 to 19 */\r
-#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 20 to 21 */\r
-#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 22 to 23 */\r
-#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 24 to 25 */\r
-#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 26 to 27 */\r
-#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 28 to 29 */\r
-#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 30 to 31 */\r
-#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 32 to 33 */\r
-#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 34 to 35 */\r
-#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 36 to 37 */\r
-#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 38 to 39 */\r
-#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 40 to 41 */\r
-#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 42 to 43 */\r
-#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 44 to 45 */\r
-#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 46 to 47 */\r
-#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 48 to 49 */\r
-#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 50 to 51 */\r
-#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 52 to 53 */\r
-#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 54 to 55 */\r
-#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 56 to 57 */\r
-#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 58 to 59 */\r
-#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
- Write protection of page 60 to 61 */\r
-#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */\r
-#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */\r
-#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */\r
-\r
-#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */\r
-\r
-#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))\r
-\r
-#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))\r
-\r
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_IWatchdog \r
- * @{\r
- */\r
-\r
-#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */\r
-#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */\r
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_nRST_STOP \r
- * @{\r
- */\r
-\r
-#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */\r
-#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */\r
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Option_Bytes_nRST_STDBY \r
- * @{\r
- */\r
-\r
-#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */\r
-#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */\r
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @}\r
- */\r
-/** @defgroup FLASH_Boot\r
- * @{\r
- */\r
-#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position\r
- and this parameter is selected the device will boot from Bank1(Default) */\r
-#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position\r
- and this parameter is selected the device will boot from Bank 2 or Bank 1,\r
- depending on the activation of the bank */\r
-#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))\r
-#endif\r
-/**\r
- * @}\r
- */\r
-/** @defgroup FLASH_Interrupts \r
- * @{\r
- */\r
-#ifdef STM32F10X_XL\r
-#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */\r
-#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */\r
-\r
-#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */\r
-#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */\r
-\r
-#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */\r
-#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */\r
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))\r
-#else\r
-#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */\r
-#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */\r
-#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */\r
-#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */\r
-\r
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Flags \r
- * @{\r
- */\r
-#ifdef STM32F10X_XL\r
-#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */\r
-#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */\r
-#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */\r
-#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */\r
-\r
-#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/\r
-#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */\r
-#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */\r
-#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */\r
-\r
-#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */\r
-#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */\r
-#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */\r
-#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */\r
-#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */\r
- \r
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))\r
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
- ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \\r
- ((FLAG) == FLASH_FLAG_OPTERR)|| \\r
- ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \\r
- ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \\r
- ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \\r
- ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))\r
-#else\r
-#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */\r
-#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */\r
-#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */\r
-#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */\r
-#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */\r
-\r
-#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/\r
-#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */\r
-#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */\r
-#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */\r
- \r
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))\r
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
- ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \\r
- ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \\r
- ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \\r
- ((FLAG) == FLASH_FLAG_OPTERR))\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Exported_Functions\r
- * @{\r
- */\r
-\r
-/*------------ Functions used for all STM32F10x devices -----*/\r
-void FLASH_SetLatency(uint32_t FLASH_Latency);\r
-void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);\r
-void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);\r
-void FLASH_Unlock(void);\r
-void FLASH_Lock(void);\r
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
-FLASH_Status FLASH_EraseAllPages(void);\r
-FLASH_Status FLASH_EraseOptionBytes(void);\r
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);\r
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);\r
-FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);\r
-FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);\r
-FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);\r
-uint32_t FLASH_GetUserOptionByte(void);\r
-uint32_t FLASH_GetWriteProtectionOptionByte(void);\r
-FlagStatus FLASH_GetReadOutProtectionStatus(void);\r
-FlagStatus FLASH_GetPrefetchBufferStatus(void);\r
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);\r
-FLASH_Status FLASH_GetStatus(void);\r
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);\r
-\r
-/*------------ New function used for all STM32F10x devices -----*/\r
-void FLASH_UnlockBank1(void);\r
-void FLASH_LockBank1(void);\r
-FLASH_Status FLASH_EraseAllBank1Pages(void);\r
-FLASH_Status FLASH_GetBank1Status(void);\r
-FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);\r
-\r
-#ifdef STM32F10X_XL\r
-/*---- New Functions used only with STM32F10x_XL density devices -----*/\r
-void FLASH_UnlockBank2(void);\r
-void FLASH_LockBank2(void);\r
-FLASH_Status FLASH_EraseAllBank2Pages(void);\r
-FLASH_Status FLASH_GetBank2Status(void);\r
-FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);\r
-FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);\r
-#endif\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_FLASH_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_fsmc.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the FSMC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_FSMC_H\r
-#define __STM32F10x_FSMC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup FSMC\r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief Timing parameters For NOR/SRAM Banks \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the address setup time. \r
- This parameter can be a value between 0 and 0xF.\r
- @note: It is not used with synchronous NOR Flash memories. */\r
-\r
- uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the address hold time.\r
- This parameter can be a value between 0 and 0xF. \r
- @note: It is not used with synchronous NOR Flash memories.*/\r
-\r
- uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the data setup time.\r
- This parameter can be a value between 0 and 0xFF.\r
- @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */\r
-\r
- uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure\r
- the duration of the bus turnaround.\r
- This parameter can be a value between 0 and 0xF.\r
- @note: It is only used for multiplexed NOR Flash memories. */\r
-\r
- uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.\r
- This parameter can be a value between 1 and 0xF.\r
- @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */\r
-\r
- uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue\r
- to the memory before getting the first data.\r
- The value of this parameter depends on the memory type as shown below:\r
- - It must be set to 0 in case of a CRAM\r
- - It is don\92t care in asynchronous NOR, SRAM or ROM accesses\r
- - It may assume a value between 0 and 0xF in NOR Flash memories\r
- with synchronous burst mode enable */\r
-\r
- uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. \r
- This parameter can be a value of @ref FSMC_Access_Mode */\r
-}FSMC_NORSRAMTimingInitTypeDef;\r
-\r
-/** \r
- * @brief FSMC NOR/SRAM Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.\r
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */\r
-\r
- uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are\r
- multiplexed on the databus or not. \r
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */\r
-\r
- uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to\r
- the corresponding memory bank.\r
- This parameter can be a value of @ref FSMC_Memory_Type */\r
-\r
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
- This parameter can be a value of @ref FSMC_Data_Width */\r
-\r
- uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,\r
- valid only with synchronous burst Flash memories.\r
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */\r
- \r
- uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,\r
- valid only with asynchronous Flash memories.\r
- This parameter can be a value of @ref FSMC_AsynchronousWait */\r
-\r
- uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing\r
- the Flash memory in burst mode.\r
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */\r
-\r
- uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash\r
- memory, valid only when accessing Flash memories in burst mode.\r
- This parameter can be a value of @ref FSMC_Wrap_Mode */\r
-\r
- uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one\r
- clock cycle before the wait state or during the wait state,\r
- valid only when accessing memories in burst mode. \r
- This parameter can be a value of @ref FSMC_Wait_Timing */\r
-\r
- uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. \r
- This parameter can be a value of @ref FSMC_Write_Operation */\r
-\r
- uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait\r
- signal, valid for Flash memory access in burst mode. \r
- This parameter can be a value of @ref FSMC_Wait_Signal */\r
-\r
- uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.\r
- This parameter can be a value of @ref FSMC_Extended_Mode */\r
-\r
- uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.\r
- This parameter can be a value of @ref FSMC_Write_Burst */ \r
-\r
- FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ \r
-\r
- FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ \r
-}FSMC_NORSRAMInitTypeDef;\r
-\r
-/** \r
- * @brief Timing parameters For FSMC NAND and PCCARD Banks\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before\r
- the command assertion for NAND-Flash read or write access\r
- to common/Attribute or I/O memory space (depending on\r
- the memory space timing to be configured).\r
- This parameter can be a value between 0 and 0xFF.*/\r
-\r
- uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the\r
- command for NAND-Flash read or write access to\r
- common/Attribute or I/O memory space (depending on the\r
- memory space timing to be configured). \r
- This parameter can be a number between 0x00 and 0xFF */\r
-\r
- uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address\r
- (and data for write access) after the command deassertion\r
- for NAND-Flash read or write access to common/Attribute\r
- or I/O memory space (depending on the memory space timing\r
- to be configured).\r
- This parameter can be a number between 0x00 and 0xFF */\r
-\r
- uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the\r
- databus is kept in HiZ after the start of a NAND-Flash\r
- write access to common/Attribute or I/O memory space (depending\r
- on the memory space timing to be configured).\r
- This parameter can be a number between 0x00 and 0xFF */\r
-}FSMC_NAND_PCCARDTimingInitTypeDef;\r
-\r
-/** \r
- * @brief FSMC NAND Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.\r
- This parameter can be a value of @ref FSMC_NAND_Bank */\r
-\r
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.\r
- This parameter can be any value of @ref FSMC_Wait_feature */\r
-\r
- uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
- This parameter can be any value of @ref FSMC_Data_Width */\r
-\r
- uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.\r
- This parameter can be any value of @ref FSMC_ECC */\r
-\r
- uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.\r
- This parameter can be any value of @ref FSMC_ECC_Page_Size */\r
-\r
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
- delay between CLE low and RE low.\r
- This parameter can be a value between 0 and 0xFF. */\r
-\r
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
- delay between ALE low and RE low.\r
- This parameter can be a number between 0x0 and 0xFF */ \r
-\r
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ \r
-\r
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */\r
-}FSMC_NANDInitTypeDef;\r
-\r
-/** \r
- * @brief FSMC PCCARD Init structure definition\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.\r
- This parameter can be any value of @ref FSMC_Wait_feature */\r
-\r
- uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
- delay between CLE low and RE low.\r
- This parameter can be a value between 0 and 0xFF. */\r
-\r
- uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
- delay between ALE low and RE low.\r
- This parameter can be a number between 0x0 and 0xFF */ \r
-\r
- \r
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */\r
-\r
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ \r
- \r
- FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ \r
-}FSMC_PCCARDInitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC_NORSRAM_Bank \r
- * @{\r
- */\r
-#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)\r
-#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)\r
-#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)\r
-#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_NAND_Bank \r
- * @{\r
- */ \r
-#define FSMC_Bank2_NAND ((uint32_t)0x00000010)\r
-#define FSMC_Bank3_NAND ((uint32_t)0x00000100)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_PCCARD_Bank \r
- * @{\r
- */ \r
-#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)\r
-/**\r
- * @}\r
- */\r
-\r
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \\r
- ((BANK) == FSMC_Bank1_NORSRAM2) || \\r
- ((BANK) == FSMC_Bank1_NORSRAM3) || \\r
- ((BANK) == FSMC_Bank1_NORSRAM4))\r
-\r
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
- ((BANK) == FSMC_Bank3_NAND))\r
-\r
-#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
- ((BANK) == FSMC_Bank3_NAND) || \\r
- ((BANK) == FSMC_Bank4_PCCARD))\r
-\r
-#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
- ((BANK) == FSMC_Bank3_NAND) || \\r
- ((BANK) == FSMC_Bank4_PCCARD))\r
-\r
-/** @defgroup NOR_SRAM_Controller \r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing \r
- * @{\r
- */\r
-\r
-#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)\r
-#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)\r
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \\r
- ((MUX) == FSMC_DataAddressMux_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Memory_Type \r
- * @{\r
- */\r
-\r
-#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)\r
-#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)\r
-#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)\r
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \\r
- ((MEMORY) == FSMC_MemoryType_PSRAM)|| \\r
- ((MEMORY) == FSMC_MemoryType_NOR))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Data_Width \r
- * @{\r
- */\r
-\r
-#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)\r
-#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)\r
-#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
- ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Burst_Access_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) \r
-#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)\r
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \\r
- ((STATE) == FSMC_BurstAccessMode_Enable))\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup FSMC_AsynchronousWait \r
- * @{\r
- */\r
-#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)\r
-#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)\r
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \\r
- ((STATE) == FSMC_AsynchronousWait_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup FSMC_Wait_Signal_Polarity \r
- * @{\r
- */\r
-\r
-#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)\r
-#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)\r
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \\r
- ((POLARITY) == FSMC_WaitSignalPolarity_High)) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wrap_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) \r
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \\r
- ((MODE) == FSMC_WrapMode_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wait_Timing \r
- * @{\r
- */\r
-\r
-#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)\r
-#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) \r
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \\r
- ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Write_Operation \r
- * @{\r
- */\r
-\r
-#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)\r
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \\r
- ((OPERATION) == FSMC_WriteOperation_Enable))\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wait_Signal \r
- * @{\r
- */\r
-\r
-#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) \r
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \\r
- ((SIGNAL) == FSMC_WaitSignal_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Extended_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)\r
-#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)\r
-\r
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \\r
- ((MODE) == FSMC_ExtendedMode_Enable)) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Write_Burst \r
- * @{\r
- */\r
-\r
-#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)\r
-#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) \r
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \\r
- ((BURST) == FSMC_WriteBurst_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Address_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Address_Hold_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Data_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Bus_Turn_around_Duration \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_CLK_Division \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Data_Latency \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Access_Mode \r
- * @{\r
- */\r
-\r
-#define FSMC_AccessMode_A ((uint32_t)0x00000000)\r
-#define FSMC_AccessMode_B ((uint32_t)0x10000000) \r
-#define FSMC_AccessMode_C ((uint32_t)0x20000000)\r
-#define FSMC_AccessMode_D ((uint32_t)0x30000000)\r
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \\r
- ((MODE) == FSMC_AccessMode_B) || \\r
- ((MODE) == FSMC_AccessMode_C) || \\r
- ((MODE) == FSMC_AccessMode_D)) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @defgroup NAND_PCCARD_Controller \r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC_Wait_feature \r
- * @{\r
- */\r
-\r
-#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)\r
-#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)\r
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \\r
- ((FEATURE) == FSMC_Waitfeature_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup FSMC_ECC \r
- * @{\r
- */\r
-\r
-#define FSMC_ECC_Disable ((uint32_t)0x00000000)\r
-#define FSMC_ECC_Enable ((uint32_t)0x00000040)\r
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \\r
- ((STATE) == FSMC_ECC_Enable))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_ECC_Page_Size \r
- * @{\r
- */\r
-\r
-#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)\r
-#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)\r
-#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)\r
-#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)\r
-#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)\r
-#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)\r
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \\r
- ((SIZE) == FSMC_ECCPageSize_512Bytes) || \\r
- ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \\r
- ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \\r
- ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \\r
- ((SIZE) == FSMC_ECCPageSize_8192Bytes))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_TCLR_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_TAR_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Wait_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Hold_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_HiZ_Setup_Time \r
- * @{\r
- */\r
-\r
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Interrupt_sources \r
- * @{\r
- */\r
-\r
-#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)\r
-#define FSMC_IT_Level ((uint32_t)0x00000010)\r
-#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)\r
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))\r
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \\r
- ((IT) == FSMC_IT_Level) || \\r
- ((IT) == FSMC_IT_FallingEdge)) \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Flags \r
- * @{\r
- */\r
-\r
-#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)\r
-#define FSMC_FLAG_Level ((uint32_t)0x00000002)\r
-#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)\r
-#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)\r
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \\r
- ((FLAG) == FSMC_FLAG_Level) || \\r
- ((FLAG) == FSMC_FLAG_FallingEdge) || \\r
- ((FLAG) == FSMC_FLAG_FEMPT))\r
-\r
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);\r
-void FSMC_NANDDeInit(uint32_t FSMC_Bank);\r
-void FSMC_PCCARDDeInit(void);\r
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
-void FSMC_PCCARDCmd(FunctionalState NewState);\r
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank);\r
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);\r
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_FSMC_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_i2c.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the I2C firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_I2C_H\r
-#define __STM32F10x_I2C_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup I2C\r
- * @{\r
- */\r
-\r
-/** @defgroup I2C_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief I2C Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.\r
- This parameter must be set to a value lower than 400kHz */\r
-\r
- uint16_t I2C_Mode; /*!< Specifies the I2C mode.\r
- This parameter can be a value of @ref I2C_mode */\r
-\r
- uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.\r
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r
-\r
- uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.\r
- This parameter can be a 7-bit or 10-bit address. */\r
-\r
- uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r
- This parameter can be a value of @ref I2C_acknowledgement */\r
-\r
- uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
- This parameter can be a value of @ref I2C_acknowledged_address */\r
-}I2C_InitTypeDef;\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup I2C_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
- ((PERIPH) == I2C2))\r
-/** @defgroup I2C_mode \r
- * @{\r
- */\r
-\r
-#define I2C_Mode_I2C ((uint16_t)0x0000)\r
-#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) \r
-#define I2C_Mode_SMBusHost ((uint16_t)0x000A)\r
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
- ((MODE) == I2C_Mode_SMBusDevice) || \\r
- ((MODE) == I2C_Mode_SMBusHost))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_duty_cycle_in_fast_mode \r
- * @{\r
- */\r
-\r
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
- ((CYCLE) == I2C_DutyCycle_2))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_acknowledgement\r
- * @{\r
- */\r
-\r
-#define I2C_Ack_Enable ((uint16_t)0x0400)\r
-#define I2C_Ack_Disable ((uint16_t)0x0000)\r
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
- ((STATE) == I2C_Ack_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_transfer_direction \r
- * @{\r
- */\r
-\r
-#define I2C_Direction_Transmitter ((uint8_t)0x00)\r
-#define I2C_Direction_Receiver ((uint8_t)0x01)\r
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
- ((DIRECTION) == I2C_Direction_Receiver))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_acknowledged_address \r
- * @{\r
- */\r
-\r
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)\r
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)\r
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_registers \r
- * @{\r
- */\r
-\r
-#define I2C_Register_CR1 ((uint8_t)0x00)\r
-#define I2C_Register_CR2 ((uint8_t)0x04)\r
-#define I2C_Register_OAR1 ((uint8_t)0x08)\r
-#define I2C_Register_OAR2 ((uint8_t)0x0C)\r
-#define I2C_Register_DR ((uint8_t)0x10)\r
-#define I2C_Register_SR1 ((uint8_t)0x14)\r
-#define I2C_Register_SR2 ((uint8_t)0x18)\r
-#define I2C_Register_CCR ((uint8_t)0x1C)\r
-#define I2C_Register_TRISE ((uint8_t)0x20)\r
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
- ((REGISTER) == I2C_Register_CR2) || \\r
- ((REGISTER) == I2C_Register_OAR1) || \\r
- ((REGISTER) == I2C_Register_OAR2) || \\r
- ((REGISTER) == I2C_Register_DR) || \\r
- ((REGISTER) == I2C_Register_SR1) || \\r
- ((REGISTER) == I2C_Register_SR2) || \\r
- ((REGISTER) == I2C_Register_CCR) || \\r
- ((REGISTER) == I2C_Register_TRISE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_SMBus_alert_pin_level \r
- * @{\r
- */\r
-\r
-#define I2C_SMBusAlert_Low ((uint16_t)0x2000)\r
-#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)\r
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
- ((ALERT) == I2C_SMBusAlert_High))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_PEC_position \r
- * @{\r
- */\r
-\r
-#define I2C_PECPosition_Next ((uint16_t)0x0800)\r
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)\r
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
- ((POSITION) == I2C_PECPosition_Current))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define I2C_IT_BUF ((uint16_t)0x0400)\r
-#define I2C_IT_EVT ((uint16_t)0x0200)\r
-#define I2C_IT_ERR ((uint16_t)0x0100)\r
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2C_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define I2C_IT_SMBALERT ((uint32_t)0x01008000)\r
-#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)\r
-#define I2C_IT_PECERR ((uint32_t)0x01001000)\r
-#define I2C_IT_OVR ((uint32_t)0x01000800)\r
-#define I2C_IT_AF ((uint32_t)0x01000400)\r
-#define I2C_IT_ARLO ((uint32_t)0x01000200)\r
-#define I2C_IT_BERR ((uint32_t)0x01000100)\r
-#define I2C_IT_TXE ((uint32_t)0x06000080)\r
-#define I2C_IT_RXNE ((uint32_t)0x06000040)\r
-#define I2C_IT_STOPF ((uint32_t)0x02000010)\r
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)\r
-#define I2C_IT_BTF ((uint32_t)0x02000004)\r
-#define I2C_IT_ADDR ((uint32_t)0x02000002)\r
-#define I2C_IT_SB ((uint32_t)0x02000001)\r
-\r
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r
-\r
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
- ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
- ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
- ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
- ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_flags_definition \r
- * @{\r
- */\r
-\r
-/** \r
- * @brief SR2 register flags \r
- */\r
-\r
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)\r
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)\r
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)\r
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)\r
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)\r
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)\r
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)\r
-\r
-/** \r
- * @brief SR1 register flags \r
- */\r
-\r
-#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)\r
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)\r
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)\r
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)\r
-#define I2C_FLAG_AF ((uint32_t)0x10000400)\r
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)\r
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)\r
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)\r
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)\r
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)\r
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)\r
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)\r
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)\r
-#define I2C_FLAG_SB ((uint32_t)0x10000001)\r
-\r
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
-\r
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
- ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
- ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
- ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
- ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
- ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
- ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
- ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
- ((FLAG) == I2C_FLAG_SB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Events \r
- * @{\r
- */\r
-\r
-/*========================================\r
- \r
- I2C Master Events (Events grouped in order of communication)\r
- ==========================================*/\r
-/** \r
- * @brief Communication start\r
- * \r
- * After sending the START condition (I2C_GenerateSTART() function) the master \r
- * has to wait for this event. It means that the Start condition has been correctly \r
- * released on the I2C bus (the bus is free, no other devices is communicating).\r
- * \r
- */\r
-/* --EV5 */\r
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */\r
-\r
-/** \r
- * @brief Address Acknowledge\r
- * \r
- * After checking on EV5 (start condition correctly released on the bus), the \r
- * master sends the address of the slave(s) with which it will communicate \r
- * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r
- * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r
- * his address. If an acknowledge is sent on the bus, one of the following events will \r
- * be set:\r
- * \r
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r
- * event is set.\r
- * \r
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r
- * is set\r
- * \r
- * 3) In case of 10-Bit addressing mode, the master (just after generating the START \r
- * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r
- * function). Then master should wait on EV9. It means that the 10-bit addressing \r
- * header has been correctly sent on the bus. Then master should send the second part of \r
- * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r
- * should wait for event EV6. \r
- * \r
- */\r
-\r
-/* --EV6 */\r
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */\r
-/* --EV9 */\r
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */\r
-\r
-/** \r
- * @brief Communication events\r
- * \r
- * If a communication is established (START condition generated and slave address \r
- * acknowledged) then the master has to check on one of the following events for \r
- * communication procedures:\r
- * \r
- * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r
- * the data received from the slave (I2C_ReceiveData() function).\r
- * \r
- * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r
- * function) then to wait on event EV8 or EV8_2.\r
- * These two events are similar: \r
- * - EV8 means that the data has been written in the data register and is \r
- * being shifted out.\r
- * - EV8_2 means that the data has been physically shifted out and output \r
- * on the bus.\r
- * In most cases, using EV8 is sufficient for the application.\r
- * Using EV8_2 leads to a slower communication but ensure more reliable test.\r
- * EV8_2 is also more suitable than EV8 for testing on the last data transmission \r
- * (before Stop condition generation).\r
- * \r
- * @note In case the user software does not guarantee that this event EV7 is \r
- * managed before the current byte end of transfer, then user may check on EV7 \r
- * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
- * In this case the communication may be slower.\r
- * \r
- */\r
-\r
-/* Master RECEIVER mode -----------------------------*/ \r
-/* --EV7 */\r
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */\r
-\r
-/* Master TRANSMITTER mode --------------------------*/\r
-/* --EV8 */\r
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r
-/* --EV8_2 */\r
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
-\r
-\r
-/*========================================\r
- \r
- I2C Slave Events (Events grouped in order of communication)\r
- ==========================================*/\r
-\r
-/** \r
- * @brief Communication start events\r
- * \r
- * Wait on one of these events at the start of the communication. It means that \r
- * the I2C peripheral detected a Start condition on the bus (generated by master \r
- * device) followed by the peripheral address. The peripheral generates an ACK \r
- * condition on the bus (if the acknowledge feature is enabled through function \r
- * I2C_AcknowledgeConfig()) and the events listed above are set :\r
- * \r
- * 1) In normal case (only one address managed by the slave), when the address \r
- * sent by the master matches the own address of the peripheral (configured by \r
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r
- * (where XXX could be TRANSMITTER or RECEIVER).\r
- * \r
- * 2) In case the address sent by the master matches the second address of the \r
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r
- * (where XXX could be TRANSMITTER or RECEIVER) are set.\r
- * \r
- * 3) In case the address sent by the master is General Call (address 0x00) and \r
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r
- * \r
- */\r
-\r
-/* --EV1 (all the events below are variants of EV1) */ \r
-/* 1) Case of One Single Address managed by the slave */\r
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
-\r
-/* 2) Case of Dual address managed by the slave */\r
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */\r
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
-\r
-/* 3) Case of General Call enabled for the slave */\r
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */\r
-\r
-/** \r
- * @brief Communication events\r
- * \r
- * Wait on one of these events when EV1 has already been checked and: \r
- * \r
- * - Slave RECEIVER mode:\r
- * - EV2: When the application is expecting a data byte to be received. \r
- * - EV4: When the application is expecting the end of the communication: master \r
- * sends a stop condition and data transmission is stopped.\r
- * \r
- * - Slave Transmitter mode:\r
- * - EV3: When a byte has been transmitted by the slave and the application is expecting \r
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r
- * used when the user software doesn't guarantee the EV3 is managed before the\r
- * current byte end of tranfer.\r
- * - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r
- * shall end (before sending the STOP condition). In this case slave has to stop sending \r
- * data bytes and expect a Stop condition on the bus.\r
- * \r
- * @note In case the user software does not guarantee that the event EV2 is \r
- * managed before the current byte end of transfer, then user may check on EV2 \r
- * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
- * In this case the communication may be slower.\r
- *\r
- */\r
-\r
-/* Slave RECEIVER mode --------------------------*/ \r
-/* --EV2 */\r
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */\r
-/* --EV4 */\r
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */\r
-\r
-/* Slave TRANSMITTER mode -----------------------*/\r
-/* --EV3 */\r
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */\r
-/* --EV3_2 */\r
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */\r
-\r
-/*=========================== End of Events Description ==========================================*/\r
-\r
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
- ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
- ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
- ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
- ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
- ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_own_address1 \r
- * @{\r
- */\r
-\r
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_clock_speed \r
- * @{\r
- */\r
-\r
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Exported_Functions\r
- * @{\r
- */\r
-\r
-void I2C_DeInit(I2C_TypeDef* I2Cx);\r
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r
-\r
-/**\r
- * @brief\r
- ****************************************************************************************\r
- *\r
- * I2C State Monitoring Functions\r
- * \r
- **************************************************************************************** \r
- * This I2C driver provides three different ways for I2C state monitoring\r
- * depending on the application requirements and constraints:\r
- * \r
- * \r
- * 1) Basic state monitoring:\r
- * Using I2C_CheckEvent() function:\r
- * It compares the status registers (SR1 and SR2) content to a given event\r
- * (can be the combination of one or more flags).\r
- * It returns SUCCESS if the current status includes the given flags \r
- * and returns ERROR if one or more flags are missing in the current status.\r
- * - When to use:\r
- * - This function is suitable for most applications as well as for startup \r
- * activity since the events are fully described in the product reference manual \r
- * (RM0008).\r
- * - It is also suitable for users who need to define their own events.\r
- * - Limitations:\r
- * - If an error occurs (ie. error flags are set besides to the monitored flags),\r
- * the I2C_CheckEvent() function may return SUCCESS despite the communication\r
- * hold or corrupted real state. \r
- * In this case, it is advised to use error interrupts to monitor the error\r
- * events and handle them in the interrupt IRQ handler.\r
- * \r
- * @note \r
- * For error management, it is advised to use the following functions:\r
- * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
- * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.\r
- * Where x is the peripheral instance (I2C1, I2C2 ...)\r
- * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()\r
- * in order to determine which error occured.\r
- * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
- * and/or I2C_GenerateStop() in order to clear the error flag and source,\r
- * and return to correct communication status.\r
- * \r
- *\r
- * 2) Advanced state monitoring:\r
- * Using the function I2C_GetLastEvent() which returns the image of both status \r
- * registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
- * by 16 bits and concatenated to Status Register 1).\r
- * - When to use:\r
- * - This function is suitable for the same applications above but it allows to\r
- * overcome the limitations of I2C_GetFlagStatus() function (see below).\r
- * The returned value could be compared to events already defined in the \r
- * library (stm32f10x_i2c.h) or to custom values defined by user.\r
- * - This function is suitable when multiple flags are monitored at the same time.\r
- * - At the opposite of I2C_CheckEvent() function, this function allows user to\r
- * choose when an event is accepted (when all events flags are set and no \r
- * other flags are set or just when the needed flags are set like \r
- * I2C_CheckEvent() function).\r
- * - Limitations:\r
- * - User may need to define his own events.\r
- * - Same remark concerning the error management is applicable for this \r
- * function if user decides to check only regular communication flags (and \r
- * ignores error flags).\r
- * \r
- *\r
- * 3) Flag-based state monitoring:\r
- * Using the function I2C_GetFlagStatus() which simply returns the status of \r
- * one single flag (ie. I2C_FLAG_RXNE ...). \r
- * - When to use:\r
- * - This function could be used for specific applications or in debug phase.\r
- * - It is suitable when only one flag checking is needed (most I2C events \r
- * are monitored through multiple flags).\r
- * - Limitations: \r
- * - When calling this function, the Status register is accessed. Some flags are\r
- * cleared when the status register is accessed. So checking the status\r
- * of one Flag, may clear other ones.\r
- * - Function may need to be called twice or more in order to monitor one \r
- * single event.\r
- * \r
- */\r
-\r
-/**\r
- * \r
- * 1) Basic state monitoring\r
- *******************************************************************************\r
- */\r
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r
-/**\r
- * \r
- * 2) Advanced state monitoring\r
- *******************************************************************************\r
- */\r
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
-/**\r
- * \r
- * 3) Flag-based state monitoring\r
- *******************************************************************************\r
- */\r
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
-/**\r
- *\r
- *******************************************************************************\r
- */\r
-\r
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_I2C_H */\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_iwdg.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the IWDG \r
- * firmware library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_IWDG_H\r
-#define __STM32F10x_IWDG_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup IWDG\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG_Exported_Types\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG_WriteAccess\r
- * @{\r
- */\r
-\r
-#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r
-#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
- ((ACCESS) == IWDG_WriteAccess_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_prescaler \r
- * @{\r
- */\r
-\r
-#define IWDG_Prescaler_4 ((uint8_t)0x00)\r
-#define IWDG_Prescaler_8 ((uint8_t)0x01)\r
-#define IWDG_Prescaler_16 ((uint8_t)0x02)\r
-#define IWDG_Prescaler_32 ((uint8_t)0x03)\r
-#define IWDG_Prescaler_64 ((uint8_t)0x04)\r
-#define IWDG_Prescaler_128 ((uint8_t)0x05)\r
-#define IWDG_Prescaler_256 ((uint8_t)0x06)\r
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
- ((PRESCALER) == IWDG_Prescaler_8) || \\r
- ((PRESCALER) == IWDG_Prescaler_16) || \\r
- ((PRESCALER) == IWDG_Prescaler_32) || \\r
- ((PRESCALER) == IWDG_Prescaler_64) || \\r
- ((PRESCALER) == IWDG_Prescaler_128)|| \\r
- ((PRESCALER) == IWDG_Prescaler_256))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Flag \r
- * @{\r
- */\r
-\r
-#define IWDG_FLAG_PVU ((uint16_t)0x0001)\r
-#define IWDG_FLAG_RVU ((uint16_t)0x0002)\r
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Exported_Functions\r
- * @{\r
- */\r
-\r
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r
-void IWDG_SetReload(uint16_t Reload);\r
-void IWDG_ReloadCounter(void);\r
-void IWDG_Enable(void);\r
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_IWDG_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_pwr.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the PWR firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_PWR_H\r
-#define __STM32F10x_PWR_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup PWR\r
- * @{\r
- */ \r
-\r
-/** @defgroup PWR_Exported_Types\r
- * @{\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup PWR_Exported_Constants\r
- * @{\r
- */ \r
-\r
-/** @defgroup PVD_detection_level \r
- * @{\r
- */ \r
-\r
-#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)\r
-#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)\r
-#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)\r
-#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)\r
-#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)\r
-#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)\r
-#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)\r
-#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)\r
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \\r
- ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \\r
- ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \\r
- ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Regulator_state_is_STOP_mode \r
- * @{\r
- */\r
-\r
-#define PWR_Regulator_ON ((uint32_t)0x00000000)\r
-#define PWR_Regulator_LowPower ((uint32_t)0x00000001)\r
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
- ((REGULATOR) == PWR_Regulator_LowPower))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup STOP_mode_entry \r
- * @{\r
- */\r
-\r
-#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r
-#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Flag \r
- * @{\r
- */\r
-\r
-#define PWR_FLAG_WU ((uint32_t)0x00000001)\r
-#define PWR_FLAG_SB ((uint32_t)0x00000002)\r
-#define PWR_FLAG_PVDO ((uint32_t)0x00000004)\r
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
- ((FLAG) == PWR_FLAG_PVDO))\r
-\r
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Exported_Functions\r
- * @{\r
- */\r
-\r
-void PWR_DeInit(void);\r
-void PWR_BackupAccessCmd(FunctionalState NewState);\r
-void PWR_PVDCmd(FunctionalState NewState);\r
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
-void PWR_WakeUpPinCmd(FunctionalState NewState);\r
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
-void PWR_EnterSTANDBYMode(void);\r
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
-void PWR_ClearFlag(uint32_t PWR_FLAG);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_PWR_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_rtc.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the RTC firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_RTC_H\r
-#define __STM32F10x_RTC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup RTC\r
- * @{\r
- */ \r
-\r
-/** @defgroup RTC_Exported_Types\r
- * @{\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup RTC_interrupts_define \r
- * @{\r
- */\r
-\r
-#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */\r
-#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */\r
-#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */\r
-#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))\r
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \\r
- ((IT) == RTC_IT_SEC))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup RTC_interrupts_flags \r
- * @{\r
- */\r
-\r
-#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */\r
-#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */\r
-#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */\r
-#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */\r
-#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */\r
-#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))\r
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \\r
- ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \\r
- ((FLAG) == RTC_FLAG_SEC))\r
-#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);\r
-void RTC_EnterConfigMode(void);\r
-void RTC_ExitConfigMode(void);\r
-uint32_t RTC_GetCounter(void);\r
-void RTC_SetCounter(uint32_t CounterValue);\r
-void RTC_SetPrescaler(uint32_t PrescalerValue);\r
-void RTC_SetAlarm(uint32_t AlarmValue);\r
-uint32_t RTC_GetDivider(void);\r
-void RTC_WaitForLastTask(void);\r
-void RTC_WaitForSynchro(void);\r
-FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);\r
-void RTC_ClearFlag(uint16_t RTC_FLAG);\r
-ITStatus RTC_GetITStatus(uint16_t RTC_IT);\r
-void RTC_ClearITPendingBit(uint16_t RTC_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_RTC_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_sdio.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the SDIO firmware\r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_SDIO_H\r
-#define __STM32F10x_SDIO_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup SDIO\r
- * @{\r
- */\r
-\r
-/** @defgroup SDIO_Exported_Types\r
- * @{\r
- */\r
-\r
-typedef struct\r
-{\r
- uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.\r
- This parameter can be a value of @ref SDIO_Clock_Edge */\r
-\r
- uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is\r
- enabled or disabled.\r
- This parameter can be a value of @ref SDIO_Clock_Bypass */\r
-\r
- uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or\r
- disabled when the bus is idle.\r
- This parameter can be a value of @ref SDIO_Clock_Power_Save */\r
-\r
- uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.\r
- This parameter can be a value of @ref SDIO_Bus_Wide */\r
-\r
- uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_Hardware_Flow_Control */\r
-\r
- uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.\r
- This parameter can be a value between 0x00 and 0xFF. */\r
- \r
-} SDIO_InitTypeDef;\r
-\r
-typedef struct\r
-{\r
- uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent\r
- to a card as part of a command message. If a command\r
- contains an argument, it must be loaded into this register\r
- before writing the command to the command register */\r
-\r
- uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */\r
-\r
- uint32_t SDIO_Response; /*!< Specifies the SDIO response type.\r
- This parameter can be a value of @ref SDIO_Response_Type */\r
-\r
- uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_Wait_Interrupt_State */\r
-\r
- uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)\r
- is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_CPSM_State */\r
-} SDIO_CmdInitTypeDef;\r
-\r
-typedef struct\r
-{\r
- uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */\r
-\r
- uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */\r
- \r
- uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.\r
- This parameter can be a value of @ref SDIO_Data_Block_Size */\r
- \r
- uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer\r
- is a read or write.\r
- This parameter can be a value of @ref SDIO_Transfer_Direction */\r
- \r
- uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.\r
- This parameter can be a value of @ref SDIO_Transfer_Type */\r
- \r
- uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)\r
- is enabled or disabled.\r
- This parameter can be a value of @ref SDIO_DPSM_State */\r
-} SDIO_DataInitTypeDef;\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SDIO_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup SDIO_Clock_Edge \r
- * @{\r
- */\r
-\r
-#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)\r
-#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)\r
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \\r
- ((EDGE) == SDIO_ClockEdge_Falling))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Clock_Bypass \r
- * @{\r
- */\r
-\r
-#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)\r
-#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) \r
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \\r
- ((BYPASS) == SDIO_ClockBypass_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SDIO_Clock_Power_Save \r
- * @{\r
- */\r
-\r
-#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)\r
-#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) \r
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \\r
- ((SAVE) == SDIO_ClockPowerSave_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Bus_Wide \r
- * @{\r
- */\r
-\r
-#define SDIO_BusWide_1b ((uint32_t)0x00000000)\r
-#define SDIO_BusWide_4b ((uint32_t)0x00000800)\r
-#define SDIO_BusWide_8b ((uint32_t)0x00001000)\r
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \\r
- ((WIDE) == SDIO_BusWide_8b))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Hardware_Flow_Control \r
- * @{\r
- */\r
-\r
-#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)\r
-#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)\r
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \\r
- ((CONTROL) == SDIO_HardwareFlowControl_Enable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Power_State \r
- * @{\r
- */\r
-\r
-#define SDIO_PowerState_OFF ((uint32_t)0x00000000)\r
-#define SDIO_PowerState_ON ((uint32_t)0x00000003)\r
-#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) \r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup SDIO_Interrupt_soucres \r
- * @{\r
- */\r
-\r
-#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)\r
-#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)\r
-#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)\r
-#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)\r
-#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)\r
-#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)\r
-#define SDIO_IT_CMDREND ((uint32_t)0x00000040)\r
-#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)\r
-#define SDIO_IT_DATAEND ((uint32_t)0x00000100)\r
-#define SDIO_IT_STBITERR ((uint32_t)0x00000200)\r
-#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)\r
-#define SDIO_IT_CMDACT ((uint32_t)0x00000800)\r
-#define SDIO_IT_TXACT ((uint32_t)0x00001000)\r
-#define SDIO_IT_RXACT ((uint32_t)0x00002000)\r
-#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)\r
-#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)\r
-#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)\r
-#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)\r
-#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)\r
-#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)\r
-#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)\r
-#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)\r
-#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)\r
-#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)\r
-#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SDIO_Command_Index\r
- * @{\r
- */\r
-\r
-#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Response_Type \r
- * @{\r
- */\r
-\r
-#define SDIO_Response_No ((uint32_t)0x00000000)\r
-#define SDIO_Response_Short ((uint32_t)0x00000040)\r
-#define SDIO_Response_Long ((uint32_t)0x000000C0)\r
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \\r
- ((RESPONSE) == SDIO_Response_Short) || \\r
- ((RESPONSE) == SDIO_Response_Long))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Wait_Interrupt_State \r
- * @{\r
- */\r
-\r
-#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */\r
-#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */\r
-#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */\r
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \\r
- ((WAIT) == SDIO_Wait_Pend))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_CPSM_State \r
- * @{\r
- */\r
-\r
-#define SDIO_CPSM_Disable ((uint32_t)0x00000000)\r
-#define SDIO_CPSM_Enable ((uint32_t)0x00000400)\r
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SDIO_Response_Registers \r
- * @{\r
- */\r
-\r
-#define SDIO_RESP1 ((uint32_t)0x00000000)\r
-#define SDIO_RESP2 ((uint32_t)0x00000004)\r
-#define SDIO_RESP3 ((uint32_t)0x00000008)\r
-#define SDIO_RESP4 ((uint32_t)0x0000000C)\r
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \\r
- ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Data_Length \r
- * @{\r
- */\r
-\r
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Data_Block_Size \r
- * @{\r
- */\r
-\r
-#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)\r
-#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)\r
-#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)\r
-#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)\r
-#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)\r
-#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)\r
-#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)\r
-#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)\r
-#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)\r
-#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)\r
-#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)\r
-#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)\r
-#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)\r
-#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)\r
-#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)\r
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \\r
- ((SIZE) == SDIO_DataBlockSize_2b) || \\r
- ((SIZE) == SDIO_DataBlockSize_4b) || \\r
- ((SIZE) == SDIO_DataBlockSize_8b) || \\r
- ((SIZE) == SDIO_DataBlockSize_16b) || \\r
- ((SIZE) == SDIO_DataBlockSize_32b) || \\r
- ((SIZE) == SDIO_DataBlockSize_64b) || \\r
- ((SIZE) == SDIO_DataBlockSize_128b) || \\r
- ((SIZE) == SDIO_DataBlockSize_256b) || \\r
- ((SIZE) == SDIO_DataBlockSize_512b) || \\r
- ((SIZE) == SDIO_DataBlockSize_1024b) || \\r
- ((SIZE) == SDIO_DataBlockSize_2048b) || \\r
- ((SIZE) == SDIO_DataBlockSize_4096b) || \\r
- ((SIZE) == SDIO_DataBlockSize_8192b) || \\r
- ((SIZE) == SDIO_DataBlockSize_16384b)) \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Transfer_Direction \r
- * @{\r
- */\r
-\r
-#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)\r
-#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)\r
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \\r
- ((DIR) == SDIO_TransferDir_ToSDIO))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Transfer_Type \r
- * @{\r
- */\r
-\r
-#define SDIO_TransferMode_Block ((uint32_t)0x00000000)\r
-#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)\r
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \\r
- ((MODE) == SDIO_TransferMode_Block))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_DPSM_State \r
- * @{\r
- */\r
-\r
-#define SDIO_DPSM_Disable ((uint32_t)0x00000000)\r
-#define SDIO_DPSM_Enable ((uint32_t)0x00000001)\r
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Flags \r
- * @{\r
- */\r
-\r
-#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)\r
-#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)\r
-#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)\r
-#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)\r
-#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)\r
-#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)\r
-#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)\r
-#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)\r
-#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)\r
-#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)\r
-#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)\r
-#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)\r
-#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)\r
-#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)\r
-#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)\r
-#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)\r
-#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)\r
-#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)\r
-#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)\r
-#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)\r
-#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)\r
-#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)\r
-#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)\r
-#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)\r
-#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \\r
- ((FLAG) == SDIO_FLAG_DCRCFAIL) || \\r
- ((FLAG) == SDIO_FLAG_CTIMEOUT) || \\r
- ((FLAG) == SDIO_FLAG_DTIMEOUT) || \\r
- ((FLAG) == SDIO_FLAG_TXUNDERR) || \\r
- ((FLAG) == SDIO_FLAG_RXOVERR) || \\r
- ((FLAG) == SDIO_FLAG_CMDREND) || \\r
- ((FLAG) == SDIO_FLAG_CMDSENT) || \\r
- ((FLAG) == SDIO_FLAG_DATAEND) || \\r
- ((FLAG) == SDIO_FLAG_STBITERR) || \\r
- ((FLAG) == SDIO_FLAG_DBCKEND) || \\r
- ((FLAG) == SDIO_FLAG_CMDACT) || \\r
- ((FLAG) == SDIO_FLAG_TXACT) || \\r
- ((FLAG) == SDIO_FLAG_RXACT) || \\r
- ((FLAG) == SDIO_FLAG_TXFIFOHE) || \\r
- ((FLAG) == SDIO_FLAG_RXFIFOHF) || \\r
- ((FLAG) == SDIO_FLAG_TXFIFOF) || \\r
- ((FLAG) == SDIO_FLAG_RXFIFOF) || \\r
- ((FLAG) == SDIO_FLAG_TXFIFOE) || \\r
- ((FLAG) == SDIO_FLAG_RXFIFOE) || \\r
- ((FLAG) == SDIO_FLAG_TXDAVL) || \\r
- ((FLAG) == SDIO_FLAG_RXDAVL) || \\r
- ((FLAG) == SDIO_FLAG_SDIOIT) || \\r
- ((FLAG) == SDIO_FLAG_CEATAEND))\r
-\r
-#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))\r
-\r
-#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \\r
- ((IT) == SDIO_IT_DCRCFAIL) || \\r
- ((IT) == SDIO_IT_CTIMEOUT) || \\r
- ((IT) == SDIO_IT_DTIMEOUT) || \\r
- ((IT) == SDIO_IT_TXUNDERR) || \\r
- ((IT) == SDIO_IT_RXOVERR) || \\r
- ((IT) == SDIO_IT_CMDREND) || \\r
- ((IT) == SDIO_IT_CMDSENT) || \\r
- ((IT) == SDIO_IT_DATAEND) || \\r
- ((IT) == SDIO_IT_STBITERR) || \\r
- ((IT) == SDIO_IT_DBCKEND) || \\r
- ((IT) == SDIO_IT_CMDACT) || \\r
- ((IT) == SDIO_IT_TXACT) || \\r
- ((IT) == SDIO_IT_RXACT) || \\r
- ((IT) == SDIO_IT_TXFIFOHE) || \\r
- ((IT) == SDIO_IT_RXFIFOHF) || \\r
- ((IT) == SDIO_IT_TXFIFOF) || \\r
- ((IT) == SDIO_IT_RXFIFOF) || \\r
- ((IT) == SDIO_IT_TXFIFOE) || \\r
- ((IT) == SDIO_IT_RXFIFOE) || \\r
- ((IT) == SDIO_IT_TXDAVL) || \\r
- ((IT) == SDIO_IT_RXDAVL) || \\r
- ((IT) == SDIO_IT_SDIOIT) || \\r
- ((IT) == SDIO_IT_CEATAEND))\r
-\r
-#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Read_Wait_Mode \r
- * @{\r
- */\r
-\r
-#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)\r
-#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)\r
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \\r
- ((MODE) == SDIO_ReadWaitMode_DATA2))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Exported_Functions\r
- * @{\r
- */\r
-\r
-void SDIO_DeInit(void);\r
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);\r
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);\r
-void SDIO_ClockCmd(FunctionalState NewState);\r
-void SDIO_SetPowerState(uint32_t SDIO_PowerState);\r
-uint32_t SDIO_GetPowerState(void);\r
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);\r
-void SDIO_DMACmd(FunctionalState NewState);\r
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);\r
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);\r
-uint8_t SDIO_GetCommandResponse(void);\r
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);\r
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
-uint32_t SDIO_GetDataCounter(void);\r
-uint32_t SDIO_ReadData(void);\r
-void SDIO_WriteData(uint32_t Data);\r
-uint32_t SDIO_GetFIFOCount(void);\r
-void SDIO_StartSDIOReadWait(FunctionalState NewState);\r
-void SDIO_StopSDIOReadWait(FunctionalState NewState);\r
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);\r
-void SDIO_SetSDIOOperation(FunctionalState NewState);\r
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);\r
-void SDIO_CommandCompletionCmd(FunctionalState NewState);\r
-void SDIO_CEATAITCmd(FunctionalState NewState);\r
-void SDIO_SendCEATACmd(FunctionalState NewState);\r
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);\r
-void SDIO_ClearFlag(uint32_t SDIO_FLAG);\r
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);\r
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_SDIO_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_spi.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the SPI firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_SPI_H\r
-#define __STM32F10x_SPI_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup SPI\r
- * @{\r
- */ \r
-\r
-/** @defgroup SPI_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief SPI Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
- This parameter can be a value of @ref SPI_data_direction */\r
-\r
- uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.\r
- This parameter can be a value of @ref SPI_mode */\r
-\r
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r
- This parameter can be a value of @ref SPI_data_size */\r
-\r
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r
- This parameter can be a value of @ref SPI_Clock_Polarity */\r
-\r
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r
- This parameter can be a value of @ref SPI_Clock_Phase */\r
-\r
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r
- hardware (NSS pin) or by software using the SSI bit.\r
- This parameter can be a value of @ref SPI_Slave_Select_management */\r
- \r
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
- used to configure the transmit and receive SCK clock.\r
- This parameter can be a value of @ref SPI_BaudRate_Prescaler.\r
- @note The communication clock is derived from the master\r
- clock. The slave clock does not need to be set. */\r
-\r
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
-\r
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r
-}SPI_InitTypeDef;\r
-\r
-/** \r
- * @brief I2S Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
-\r
- uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.\r
- This parameter can be a value of @ref I2S_Mode */\r
-\r
- uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.\r
- This parameter can be a value of @ref I2S_Standard */\r
-\r
- uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.\r
- This parameter can be a value of @ref I2S_Data_Format */\r
-\r
- uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.\r
- This parameter can be a value of @ref I2S_MCLK_Output */\r
-\r
- uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.\r
- This parameter can be a value of @ref I2S_Audio_Frequency */\r
-\r
- uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.\r
- This parameter can be a value of @ref I2S_Clock_Polarity */\r
-}I2S_InitTypeDef;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Exported_Constants\r
- * @{\r
- */\r
-\r
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
- ((PERIPH) == SPI2) || \\r
- ((PERIPH) == SPI3))\r
-\r
-#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \\r
- ((PERIPH) == SPI3))\r
-\r
-/** @defgroup SPI_data_direction \r
- * @{\r
- */\r
- \r
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
- ((MODE) == SPI_Direction_1Line_Rx) || \\r
- ((MODE) == SPI_Direction_1Line_Tx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_mode \r
- * @{\r
- */\r
-\r
-#define SPI_Mode_Master ((uint16_t)0x0104)\r
-#define SPI_Mode_Slave ((uint16_t)0x0000)\r
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
- ((MODE) == SPI_Mode_Slave))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_data_size \r
- * @{\r
- */\r
-\r
-#define SPI_DataSize_16b ((uint16_t)0x0800)\r
-#define SPI_DataSize_8b ((uint16_t)0x0000)\r
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
- ((DATASIZE) == SPI_DataSize_8b))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_Clock_Polarity \r
- * @{\r
- */\r
-\r
-#define SPI_CPOL_Low ((uint16_t)0x0000)\r
-#define SPI_CPOL_High ((uint16_t)0x0002)\r
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
- ((CPOL) == SPI_CPOL_High))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Clock_Phase \r
- * @{\r
- */\r
-\r
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r
-#define SPI_CPHA_2Edge ((uint16_t)0x0001)\r
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
- ((CPHA) == SPI_CPHA_2Edge))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Slave_Select_management \r
- * @{\r
- */\r
-\r
-#define SPI_NSS_Soft ((uint16_t)0x0200)\r
-#define SPI_NSS_Hard ((uint16_t)0x0000)\r
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
- ((NSS) == SPI_NSS_Hard))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_BaudRate_Prescaler \r
- * @{\r
- */\r
-\r
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
- ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup SPI_MSB_LSB_transmission \r
- * @{\r
- */\r
-\r
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r
-#define SPI_FirstBit_LSB ((uint16_t)0x0080)\r
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
- ((BIT) == SPI_FirstBit_LSB))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2S_Mode \r
- * @{\r
- */\r
-\r
-#define I2S_Mode_SlaveTx ((uint16_t)0x0000)\r
-#define I2S_Mode_SlaveRx ((uint16_t)0x0100)\r
-#define I2S_Mode_MasterTx ((uint16_t)0x0200)\r
-#define I2S_Mode_MasterRx ((uint16_t)0x0300)\r
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \\r
- ((MODE) == I2S_Mode_SlaveRx) || \\r
- ((MODE) == I2S_Mode_MasterTx) || \\r
- ((MODE) == I2S_Mode_MasterRx) )\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2S_Standard \r
- * @{\r
- */\r
-\r
-#define I2S_Standard_Phillips ((uint16_t)0x0000)\r
-#define I2S_Standard_MSB ((uint16_t)0x0010)\r
-#define I2S_Standard_LSB ((uint16_t)0x0020)\r
-#define I2S_Standard_PCMShort ((uint16_t)0x0030)\r
-#define I2S_Standard_PCMLong ((uint16_t)0x00B0)\r
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \\r
- ((STANDARD) == I2S_Standard_MSB) || \\r
- ((STANDARD) == I2S_Standard_LSB) || \\r
- ((STANDARD) == I2S_Standard_PCMShort) || \\r
- ((STANDARD) == I2S_Standard_PCMLong))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2S_Data_Format \r
- * @{\r
- */\r
-\r
-#define I2S_DataFormat_16b ((uint16_t)0x0000)\r
-#define I2S_DataFormat_16bextended ((uint16_t)0x0001)\r
-#define I2S_DataFormat_24b ((uint16_t)0x0003)\r
-#define I2S_DataFormat_32b ((uint16_t)0x0005)\r
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \\r
- ((FORMAT) == I2S_DataFormat_16bextended) || \\r
- ((FORMAT) == I2S_DataFormat_24b) || \\r
- ((FORMAT) == I2S_DataFormat_32b))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2S_MCLK_Output \r
- * @{\r
- */\r
-\r
-#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)\r
-#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)\r
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \\r
- ((OUTPUT) == I2S_MCLKOutput_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2S_Audio_Frequency \r
- * @{\r
- */\r
-\r
-#define I2S_AudioFreq_192k ((uint32_t)192000)\r
-#define I2S_AudioFreq_96k ((uint32_t)96000)\r
-#define I2S_AudioFreq_48k ((uint32_t)48000)\r
-#define I2S_AudioFreq_44k ((uint32_t)44100)\r
-#define I2S_AudioFreq_32k ((uint32_t)32000)\r
-#define I2S_AudioFreq_22k ((uint32_t)22050)\r
-#define I2S_AudioFreq_16k ((uint32_t)16000)\r
-#define I2S_AudioFreq_11k ((uint32_t)11025)\r
-#define I2S_AudioFreq_8k ((uint32_t)8000)\r
-#define I2S_AudioFreq_Default ((uint32_t)2)\r
-\r
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \\r
- ((FREQ) <= I2S_AudioFreq_192k)) || \\r
- ((FREQ) == I2S_AudioFreq_Default))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup I2S_Clock_Polarity \r
- * @{\r
- */\r
-\r
-#define I2S_CPOL_Low ((uint16_t)0x0000)\r
-#define I2S_CPOL_High ((uint16_t)0x0008)\r
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \\r
- ((CPOL) == I2S_CPOL_High))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_DMA_transfer_requests \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)\r
-#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)\r
-#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_NSS_internal_software_mangement \r
- * @{\r
- */\r
-\r
-#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)\r
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_CRC_Transmit_Receive \r
- * @{\r
- */\r
-\r
-#define SPI_CRC_Tx ((uint8_t)0x00)\r
-#define SPI_CRC_Rx ((uint8_t)0x01)\r
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_direction_transmit_receive \r
- * @{\r
- */\r
-\r
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r
-#define SPI_Direction_Tx ((uint16_t)0x4000)\r
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
- ((DIRECTION) == SPI_Direction_Tx))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_interrupts_definition \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
- ((IT) == SPI_I2S_IT_RXNE) || \\r
- ((IT) == SPI_I2S_IT_ERR))\r
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r
-#define SPI_IT_MODF ((uint8_t)0x55)\r
-#define SPI_IT_CRCERR ((uint8_t)0x54)\r
-#define I2S_IT_UDR ((uint8_t)0x53)\r
-#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \\r
- ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \\r
- ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_I2S_flags_definition \r
- * @{\r
- */\r
-\r
-#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)\r
-#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)\r
-#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)\r
-#define I2S_FLAG_UDR ((uint16_t)0x0008)\r
-#define SPI_FLAG_CRCERR ((uint16_t)0x0010)\r
-#define SPI_FLAG_MODF ((uint16_t)0x0020)\r
-#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)\r
-#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)\r
-#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
- ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \\r
- ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_CRC_polynomial \r
- * @{\r
- */\r
-\r
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Exported_Functions\r
- * @{\r
- */\r
-\r
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);\r
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);\r
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_SPI_H */\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_tim.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the TIM firmware \r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_TIM_H\r
-#define __STM32F10x_TIM_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup TIM\r
- * @{\r
- */ \r
-\r
-/** @defgroup TIM_Exported_Types\r
- * @{\r
- */ \r
-\r
-/** \r
- * @brief TIM Time Base Init structure definition\r
- * @note This sturcture is used with all TIMx except for TIM6 and TIM7. \r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
- This parameter can be a number between 0x0000 and 0xFFFF */\r
-\r
- uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r
- This parameter can be a value of @ref TIM_Counter_Mode */\r
-\r
- uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r
- Auto-Reload Register at the next update event.\r
- This parameter must be a number between 0x0000 and 0xFFFF. */ \r
-\r
- uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r
- This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
-\r
- uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
- reaches zero, an update event is generated and counting restarts\r
- from the RCR value (N).\r
- This means in PWM mode that (N+1) corresponds to:\r
- - the number of PWM periods in edge-aligned mode\r
- - the number of half PWM period in center-aligned mode\r
- This parameter must be a number between 0x00 and 0xFF. \r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-} TIM_TimeBaseInitTypeDef; \r
-\r
-/** \r
- * @brief TIM Output Compare Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
-\r
- uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r
- This parameter can be a value of @ref TIM_Output_Compare_state */\r
-\r
- uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.\r
- This parameter can be a value of @ref TIM_Output_Compare_N_state\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-\r
- uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
- This parameter can be a number between 0x0000 and 0xFFFF */\r
-\r
- uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
-\r
- uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.\r
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-\r
- uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-\r
- uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
- @note This parameter is valid only for TIM1 and TIM8. */\r
-} TIM_OCInitTypeDef;\r
-\r
-/** \r
- * @brief TIM Input Capture Init structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
-\r
- uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r
- This parameter can be a value of @ref TIM_Channel */\r
-\r
- uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
-\r
- uint16_t TIM_ICSelection; /*!< Specifies the input.\r
- This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
-\r
- uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
-\r
- uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r
- This parameter can be a number between 0x0 and 0xF */\r
-} TIM_ICInitTypeDef;\r
-\r
-/** \r
- * @brief BDTR structure definition \r
- * @note This sturcture is used only with TIM1 and TIM8. \r
- */\r
-\r
-typedef struct\r
-{\r
-\r
- uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.\r
- This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */\r
-\r
- uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.\r
- This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */\r
-\r
- uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.\r
- This parameter can be a value of @ref Lock_level */ \r
-\r
- uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the\r
- switching-on of the outputs.\r
- This parameter can be a number between 0x00 and 0xFF */\r
-\r
- uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. \r
- This parameter can be a value of @ref Break_Input_enable_disable */\r
-\r
- uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.\r
- This parameter can be a value of @ref Break_Polarity */\r
-\r
- uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. \r
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r
-} TIM_BDTRInitTypeDef;\r
-\r
-/** @defgroup TIM_Exported_constants \r
- * @{\r
- */\r
-\r
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM6) || \\r
- ((PERIPH) == TIM7) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM9) || \\r
- ((PERIPH) == TIM10)|| \\r
- ((PERIPH) == TIM11)|| \\r
- ((PERIPH) == TIM12)|| \\r
- ((PERIPH) == TIM13)|| \\r
- ((PERIPH) == TIM14)|| \\r
- ((PERIPH) == TIM15)|| \\r
- ((PERIPH) == TIM16)|| \\r
- ((PERIPH) == TIM17))\r
-\r
-/* LIST1: TIM 1 and 8 */\r
-#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM8))\r
-\r
-/* LIST2: TIM 1, 8, 15 16 and 17 */\r
-#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM15)|| \\r
- ((PERIPH) == TIM16)|| \\r
- ((PERIPH) == TIM17)) \r
-\r
-/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */\r
-#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM8)) \r
- \r
-/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */\r
-#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM15)|| \\r
- ((PERIPH) == TIM16)|| \\r
- ((PERIPH) == TIM17))\r
-\r
-/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ \r
-#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM15)) \r
-\r
-/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */\r
-#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM9) || \\r
- ((PERIPH) == TIM12)|| \\r
- ((PERIPH) == TIM15))\r
-\r
-/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */\r
-#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM6) || \\r
- ((PERIPH) == TIM7) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM9) || \\r
- ((PERIPH) == TIM12)|| \\r
- ((PERIPH) == TIM15)) \r
-\r
-/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ \r
-#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM9) || \\r
- ((PERIPH) == TIM10)|| \\r
- ((PERIPH) == TIM11)|| \\r
- ((PERIPH) == TIM12)|| \\r
- ((PERIPH) == TIM13)|| \\r
- ((PERIPH) == TIM14)|| \\r
- ((PERIPH) == TIM15)|| \\r
- ((PERIPH) == TIM16)|| \\r
- ((PERIPH) == TIM17))\r
-\r
-/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */\r
-#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
- ((PERIPH) == TIM2) || \\r
- ((PERIPH) == TIM3) || \\r
- ((PERIPH) == TIM4) || \\r
- ((PERIPH) == TIM5) || \\r
- ((PERIPH) == TIM6) || \\r
- ((PERIPH) == TIM7) || \\r
- ((PERIPH) == TIM8) || \\r
- ((PERIPH) == TIM15)|| \\r
- ((PERIPH) == TIM16)|| \\r
- ((PERIPH) == TIM17)) \r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_and_PWM_modes \r
- * @{\r
- */\r
-\r
-#define TIM_OCMode_Timing ((uint16_t)0x0000)\r
-#define TIM_OCMode_Active ((uint16_t)0x0010)\r
-#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r
-#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r
-#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r
-#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
- ((MODE) == TIM_OCMode_Active) || \\r
- ((MODE) == TIM_OCMode_Inactive) || \\r
- ((MODE) == TIM_OCMode_Toggle)|| \\r
- ((MODE) == TIM_OCMode_PWM1) || \\r
- ((MODE) == TIM_OCMode_PWM2))\r
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
- ((MODE) == TIM_OCMode_Active) || \\r
- ((MODE) == TIM_OCMode_Inactive) || \\r
- ((MODE) == TIM_OCMode_Toggle)|| \\r
- ((MODE) == TIM_OCMode_PWM1) || \\r
- ((MODE) == TIM_OCMode_PWM2) || \\r
- ((MODE) == TIM_ForcedAction_Active) || \\r
- ((MODE) == TIM_ForcedAction_InActive))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_One_Pulse_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_OPMode_Single ((uint16_t)0x0008)\r
-#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
- ((MODE) == TIM_OPMode_Repetitive))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Channel \r
- * @{\r
- */\r
-\r
-#define TIM_Channel_1 ((uint16_t)0x0000)\r
-#define TIM_Channel_2 ((uint16_t)0x0004)\r
-#define TIM_Channel_3 ((uint16_t)0x0008)\r
-#define TIM_Channel_4 ((uint16_t)0x000C)\r
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
- ((CHANNEL) == TIM_Channel_2) || \\r
- ((CHANNEL) == TIM_Channel_3) || \\r
- ((CHANNEL) == TIM_Channel_4))\r
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
- ((CHANNEL) == TIM_Channel_2))\r
-#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
- ((CHANNEL) == TIM_Channel_2) || \\r
- ((CHANNEL) == TIM_Channel_3))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Clock_Division_CKD \r
- * @{\r
- */\r
-\r
-#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r
-#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r
-#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
- ((DIV) == TIM_CKD_DIV2) || \\r
- ((DIV) == TIM_CKD_DIV4))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Counter_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_CounterMode_Up ((uint16_t)0x0000)\r
-#define TIM_CounterMode_Down ((uint16_t)0x0010)\r
-#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r
-#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r
-#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
- ((MODE) == TIM_CounterMode_Down) || \\r
- ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
- ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
- ((MODE) == TIM_CounterMode_CenterAligned3))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_Polarity \r
- * @{\r
- */\r
-\r
-#define TIM_OCPolarity_High ((uint16_t)0x0000)\r
-#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
- ((POLARITY) == TIM_OCPolarity_Low))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Compare_N_Polarity \r
- * @{\r
- */\r
- \r
-#define TIM_OCNPolarity_High ((uint16_t)0x0000)\r
-#define TIM_OCNPolarity_Low ((uint16_t)0x0008)\r
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \\r
- ((POLARITY) == TIM_OCNPolarity_Low))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Output_Compare_state \r
- * @{\r
- */\r
-\r
-#define TIM_OutputState_Disable ((uint16_t)0x0000)\r
-#define TIM_OutputState_Enable ((uint16_t)0x0001)\r
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
- ((STATE) == TIM_OutputState_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_N_state \r
- * @{\r
- */\r
-\r
-#define TIM_OutputNState_Disable ((uint16_t)0x0000)\r
-#define TIM_OutputNState_Enable ((uint16_t)0x0004)\r
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \\r
- ((STATE) == TIM_OutputNState_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Capture_Compare_state \r
- * @{\r
- */\r
-\r
-#define TIM_CCx_Enable ((uint16_t)0x0001)\r
-#define TIM_CCx_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
- ((CCX) == TIM_CCx_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Capture_Compare_N_state \r
- * @{\r
- */\r
-\r
-#define TIM_CCxN_Enable ((uint16_t)0x0004)\r
-#define TIM_CCxN_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \\r
- ((CCXN) == TIM_CCxN_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup Break_Input_enable_disable \r
- * @{\r
- */\r
-\r
-#define TIM_Break_Enable ((uint16_t)0x1000)\r
-#define TIM_Break_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \\r
- ((STATE) == TIM_Break_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup Break_Polarity \r
- * @{\r
- */\r
-\r
-#define TIM_BreakPolarity_Low ((uint16_t)0x0000)\r
-#define TIM_BreakPolarity_High ((uint16_t)0x2000)\r
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \\r
- ((POLARITY) == TIM_BreakPolarity_High))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_AOE_Bit_Set_Reset \r
- * @{\r
- */\r
-\r
-#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)\r
-#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \\r
- ((STATE) == TIM_AutomaticOutput_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup Lock_level \r
- * @{\r
- */\r
-\r
-#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)\r
-#define TIM_LOCKLevel_1 ((uint16_t)0x0100)\r
-#define TIM_LOCKLevel_2 ((uint16_t)0x0200)\r
-#define TIM_LOCKLevel_3 ((uint16_t)0x0300)\r
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \\r
- ((LEVEL) == TIM_LOCKLevel_1) || \\r
- ((LEVEL) == TIM_LOCKLevel_2) || \\r
- ((LEVEL) == TIM_LOCKLevel_3))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state \r
- * @{\r
- */\r
-\r
-#define TIM_OSSIState_Enable ((uint16_t)0x0400)\r
-#define TIM_OSSIState_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \\r
- ((STATE) == TIM_OSSIState_Disable))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state \r
- * @{\r
- */\r
-\r
-#define TIM_OSSRState_Enable ((uint16_t)0x0800)\r
-#define TIM_OSSRState_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \\r
- ((STATE) == TIM_OSSRState_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_Idle_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCIdleState_Set ((uint16_t)0x0100)\r
-#define TIM_OCIdleState_Reset ((uint16_t)0x0000)\r
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \\r
- ((STATE) == TIM_OCIdleState_Reset))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Output_Compare_N_Idle_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCNIdleState_Set ((uint16_t)0x0200)\r
-#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)\r
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \\r
- ((STATE) == TIM_OCNIdleState_Reset))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Polarity \r
- * @{\r
- */\r
-\r
-#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r
-#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r
-#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)\r
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
- ((POLARITY) == TIM_ICPolarity_Falling))\r
-#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
- ((POLARITY) == TIM_ICPolarity_Falling)|| \\r
- ((POLARITY) == TIM_ICPolarity_BothEdge)) \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Selection \r
- * @{\r
- */\r
-\r
-#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
- connected to IC1, IC2, IC3 or IC4, respectively */\r
-#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
- connected to IC2, IC1, IC4 or IC3, respectively. */\r
-#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
- ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
- ((SELECTION) == TIM_ICSelection_TRC))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Prescaler \r
- * @{\r
- */\r
-\r
-#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
-#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
-#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
-#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
- ((PRESCALER) == TIM_ICPSC_DIV8))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_interrupt_sources \r
- * @{\r
- */\r
-\r
-#define TIM_IT_Update ((uint16_t)0x0001)\r
-#define TIM_IT_CC1 ((uint16_t)0x0002)\r
-#define TIM_IT_CC2 ((uint16_t)0x0004)\r
-#define TIM_IT_CC3 ((uint16_t)0x0008)\r
-#define TIM_IT_CC4 ((uint16_t)0x0010)\r
-#define TIM_IT_COM ((uint16_t)0x0020)\r
-#define TIM_IT_Trigger ((uint16_t)0x0040)\r
-#define TIM_IT_Break ((uint16_t)0x0080)\r
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))\r
-\r
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
- ((IT) == TIM_IT_CC1) || \\r
- ((IT) == TIM_IT_CC2) || \\r
- ((IT) == TIM_IT_CC3) || \\r
- ((IT) == TIM_IT_CC4) || \\r
- ((IT) == TIM_IT_COM) || \\r
- ((IT) == TIM_IT_Trigger) || \\r
- ((IT) == TIM_IT_Break))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_DMA_Base_address \r
- * @{\r
- */\r
-\r
-#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r
-#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r
-#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r
-#define TIM_DMABase_DIER ((uint16_t)0x0003)\r
-#define TIM_DMABase_SR ((uint16_t)0x0004)\r
-#define TIM_DMABase_EGR ((uint16_t)0x0005)\r
-#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r
-#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r
-#define TIM_DMABase_CCER ((uint16_t)0x0008)\r
-#define TIM_DMABase_CNT ((uint16_t)0x0009)\r
-#define TIM_DMABase_PSC ((uint16_t)0x000A)\r
-#define TIM_DMABase_ARR ((uint16_t)0x000B)\r
-#define TIM_DMABase_RCR ((uint16_t)0x000C)\r
-#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r
-#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r
-#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r
-#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r
-#define TIM_DMABase_BDTR ((uint16_t)0x0011)\r
-#define TIM_DMABase_DCR ((uint16_t)0x0012)\r
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
- ((BASE) == TIM_DMABase_CR2) || \\r
- ((BASE) == TIM_DMABase_SMCR) || \\r
- ((BASE) == TIM_DMABase_DIER) || \\r
- ((BASE) == TIM_DMABase_SR) || \\r
- ((BASE) == TIM_DMABase_EGR) || \\r
- ((BASE) == TIM_DMABase_CCMR1) || \\r
- ((BASE) == TIM_DMABase_CCMR2) || \\r
- ((BASE) == TIM_DMABase_CCER) || \\r
- ((BASE) == TIM_DMABase_CNT) || \\r
- ((BASE) == TIM_DMABase_PSC) || \\r
- ((BASE) == TIM_DMABase_ARR) || \\r
- ((BASE) == TIM_DMABase_RCR) || \\r
- ((BASE) == TIM_DMABase_CCR1) || \\r
- ((BASE) == TIM_DMABase_CCR2) || \\r
- ((BASE) == TIM_DMABase_CCR3) || \\r
- ((BASE) == TIM_DMABase_CCR4) || \\r
- ((BASE) == TIM_DMABase_BDTR) || \\r
- ((BASE) == TIM_DMABase_DCR))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_DMA_Burst_Length \r
- * @{\r
- */\r
-\r
-#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)\r
-#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)\r
-#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)\r
-#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)\r
-#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)\r
-#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)\r
-#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)\r
-#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)\r
-#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)\r
-#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)\r
-#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)\r
-#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)\r
-#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)\r
-#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)\r
-#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)\r
-#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)\r
-#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)\r
-#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)\r
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \\r
- ((LENGTH) == TIM_DMABurstLength_2Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_3Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_4Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_5Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_6Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_7Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_8Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_9Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_10Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_11Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_12Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_13Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_14Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_15Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_16Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_17Bytes) || \\r
- ((LENGTH) == TIM_DMABurstLength_18Bytes))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_DMA_sources \r
- * @{\r
- */\r
-\r
-#define TIM_DMA_Update ((uint16_t)0x0100)\r
-#define TIM_DMA_CC1 ((uint16_t)0x0200)\r
-#define TIM_DMA_CC2 ((uint16_t)0x0400)\r
-#define TIM_DMA_CC3 ((uint16_t)0x0800)\r
-#define TIM_DMA_CC4 ((uint16_t)0x1000)\r
-#define TIM_DMA_COM ((uint16_t)0x2000)\r
-#define TIM_DMA_Trigger ((uint16_t)0x4000)\r
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_External_Trigger_Prescaler \r
- * @{\r
- */\r
-\r
-#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r
-#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r
-#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r
-#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
- ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
- ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
- ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Internal_Trigger_Selection \r
- * @{\r
- */\r
-\r
-#define TIM_TS_ITR0 ((uint16_t)0x0000)\r
-#define TIM_TS_ITR1 ((uint16_t)0x0010)\r
-#define TIM_TS_ITR2 ((uint16_t)0x0020)\r
-#define TIM_TS_ITR3 ((uint16_t)0x0030)\r
-#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r
-#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r
-#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r
-#define TIM_TS_ETRF ((uint16_t)0x0070)\r
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
- ((SELECTION) == TIM_TS_ITR1) || \\r
- ((SELECTION) == TIM_TS_ITR2) || \\r
- ((SELECTION) == TIM_TS_ITR3) || \\r
- ((SELECTION) == TIM_TS_TI1F_ED) || \\r
- ((SELECTION) == TIM_TS_TI1FP1) || \\r
- ((SELECTION) == TIM_TS_TI2FP2) || \\r
- ((SELECTION) == TIM_TS_ETRF))\r
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
- ((SELECTION) == TIM_TS_ITR1) || \\r
- ((SELECTION) == TIM_TS_ITR2) || \\r
- ((SELECTION) == TIM_TS_ITR3))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_TIx_External_Clock_Source \r
- * @{\r
- */\r
-\r
-#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r
-#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r
-#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r
-#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \\r
- ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \\r
- ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_External_Trigger_Polarity \r
- * @{\r
- */ \r
-#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r
-#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
- ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Prescaler_Reload_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r
-#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
- ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Forced_Action \r
- * @{\r
- */\r
-\r
-#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r
-#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
- ((ACTION) == TIM_ForcedAction_InActive))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Encoder_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r
-#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r
-#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
- ((MODE) == TIM_EncoderMode_TI2) || \\r
- ((MODE) == TIM_EncoderMode_TI12))\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup TIM_Event_Source \r
- * @{\r
- */\r
-\r
-#define TIM_EventSource_Update ((uint16_t)0x0001)\r
-#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r
-#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r
-#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r
-#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r
-#define TIM_EventSource_COM ((uint16_t)0x0020)\r
-#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r
-#define TIM_EventSource_Break ((uint16_t)0x0080)\r
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Update_Source \r
- * @{\r
- */\r
-\r
-#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
- or the setting of UG bit, or an update generation\r
- through the slave mode controller. */\r
-#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
- ((SOURCE) == TIM_UpdateSource_Regular))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Ouput_Compare_Preload_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r
-#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
- ((STATE) == TIM_OCPreload_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Ouput_Compare_Fast_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCFast_Enable ((uint16_t)0x0004)\r
-#define TIM_OCFast_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
- ((STATE) == TIM_OCFast_Disable))\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Ouput_Compare_Clear_State \r
- * @{\r
- */\r
-\r
-#define TIM_OCClear_Enable ((uint16_t)0x0080)\r
-#define TIM_OCClear_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
- ((STATE) == TIM_OCClear_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Trigger_Output_Source \r
- * @{\r
- */\r
-\r
-#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r
-#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r
-#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r
-#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r
-#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r
-#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r
-#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r
-#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
- ((SOURCE) == TIM_TRGOSource_Enable) || \\r
- ((SOURCE) == TIM_TRGOSource_Update) || \\r
- ((SOURCE) == TIM_TRGOSource_OC1) || \\r
- ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
- ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
- ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
- ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Slave_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r
-#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r
-#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r
-#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
- ((MODE) == TIM_SlaveMode_Gated) || \\r
- ((MODE) == TIM_SlaveMode_Trigger) || \\r
- ((MODE) == TIM_SlaveMode_External1))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Master_Slave_Mode \r
- * @{\r
- */\r
-\r
-#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r
-#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
- ((STATE) == TIM_MasterSlaveMode_Disable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Flags \r
- * @{\r
- */\r
-\r
-#define TIM_FLAG_Update ((uint16_t)0x0001)\r
-#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r
-#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r
-#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r
-#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r
-#define TIM_FLAG_COM ((uint16_t)0x0020)\r
-#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r
-#define TIM_FLAG_Break ((uint16_t)0x0080)\r
-#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r
-#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r
-#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r
-#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
- ((FLAG) == TIM_FLAG_CC1) || \\r
- ((FLAG) == TIM_FLAG_CC2) || \\r
- ((FLAG) == TIM_FLAG_CC3) || \\r
- ((FLAG) == TIM_FLAG_CC4) || \\r
- ((FLAG) == TIM_FLAG_COM) || \\r
- ((FLAG) == TIM_FLAG_Trigger) || \\r
- ((FLAG) == TIM_FLAG_Break) || \\r
- ((FLAG) == TIM_FLAG_CC1OF) || \\r
- ((FLAG) == TIM_FLAG_CC2OF) || \\r
- ((FLAG) == TIM_FLAG_CC3OF) || \\r
- ((FLAG) == TIM_FLAG_CC4OF))\r
- \r
- \r
-#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Input_Capture_Filer_Value \r
- * @{\r
- */\r
-\r
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_External_Trigger_Filter \r
- * @{\r
- */\r
-\r
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup TIM_Exported_Functions\r
- * @{\r
- */\r
-\r
-void TIM_DeInit(TIM_TypeDef* TIMx);\r
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);\r
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);\r
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
- uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter);\r
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter);\r
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);\r
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);\r
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);\r
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);\r
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);\r
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);\r
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);\r
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
-uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
-uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
-uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
-uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
-uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__STM32F10x_TIM_H */\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_usart.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the USART \r
- * firmware library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_USART_H\r
-#define __STM32F10x_USART_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup USART\r
- * @{\r
- */ \r
-\r
-/** @defgroup USART_Exported_Types\r
- * @{\r
- */ \r
-\r
-/** \r
- * @brief USART Init Structure definition \r
- */ \r
- \r
-typedef struct\r
-{\r
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r
- The baud rate is computed using the following formula:\r
- - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))\r
- - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */\r
-\r
- uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
- This parameter can be a value of @ref USART_Word_Length */\r
-\r
- uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r
- This parameter can be a value of @ref USART_Stop_Bits */\r
-\r
- uint16_t USART_Parity; /*!< Specifies the parity mode.\r
- This parameter can be a value of @ref USART_Parity\r
- @note When parity is enabled, the computed parity is inserted\r
- at the MSB position of the transmitted data (9th bit when\r
- the word length is set to 9 data bits; 8th bit when the\r
- word length is set to 8 data bits). */\r
- \r
- uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
- This parameter can be a value of @ref USART_Mode */\r
-\r
- uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
- or disabled.\r
- This parameter can be a value of @ref USART_Hardware_Flow_Control */\r
-} USART_InitTypeDef;\r
-\r
-/** \r
- * @brief USART Clock Init Structure definition \r
- */ \r
- \r
-typedef struct\r
-{\r
-\r
- uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r
- This parameter can be a value of @ref USART_Clock */\r
-\r
- uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.\r
- This parameter can be a value of @ref USART_Clock_Polarity */\r
-\r
- uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r
- This parameter can be a value of @ref USART_Clock_Phase */\r
-\r
- uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
- This parameter can be a value of @ref USART_Last_Bit */\r
-} USART_ClockInitTypeDef;\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Exported_Constants\r
- * @{\r
- */ \r
- \r
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
- ((PERIPH) == USART2) || \\r
- ((PERIPH) == USART3) || \\r
- ((PERIPH) == UART4) || \\r
- ((PERIPH) == UART5))\r
-\r
-#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
- ((PERIPH) == USART2) || \\r
- ((PERIPH) == USART3))\r
-\r
-#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
- ((PERIPH) == USART2) || \\r
- ((PERIPH) == USART3) || \\r
- ((PERIPH) == UART4))\r
-/** @defgroup USART_Word_Length \r
- * @{\r
- */ \r
- \r
-#define USART_WordLength_8b ((uint16_t)0x0000)\r
-#define USART_WordLength_9b ((uint16_t)0x1000)\r
- \r
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
- ((LENGTH) == USART_WordLength_9b))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Stop_Bits \r
- * @{\r
- */ \r
- \r
-#define USART_StopBits_1 ((uint16_t)0x0000)\r
-#define USART_StopBits_0_5 ((uint16_t)0x1000)\r
-#define USART_StopBits_2 ((uint16_t)0x2000)\r
-#define USART_StopBits_1_5 ((uint16_t)0x3000)\r
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
- ((STOPBITS) == USART_StopBits_0_5) || \\r
- ((STOPBITS) == USART_StopBits_2) || \\r
- ((STOPBITS) == USART_StopBits_1_5))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Parity \r
- * @{\r
- */ \r
- \r
-#define USART_Parity_No ((uint16_t)0x0000)\r
-#define USART_Parity_Even ((uint16_t)0x0400)\r
-#define USART_Parity_Odd ((uint16_t)0x0600) \r
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
- ((PARITY) == USART_Parity_Even) || \\r
- ((PARITY) == USART_Parity_Odd))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Mode \r
- * @{\r
- */ \r
- \r
-#define USART_Mode_Rx ((uint16_t)0x0004)\r
-#define USART_Mode_Tx ((uint16_t)0x0008)\r
-#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Hardware_Flow_Control \r
- * @{\r
- */ \r
-#define USART_HardwareFlowControl_None ((uint16_t)0x0000)\r
-#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)\r
-#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)\r
-#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)\r
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
- (((CONTROL) == USART_HardwareFlowControl_None) || \\r
- ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
- ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
- ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock \r
- * @{\r
- */ \r
-#define USART_Clock_Disable ((uint16_t)0x0000)\r
-#define USART_Clock_Enable ((uint16_t)0x0800)\r
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
- ((CLOCK) == USART_Clock_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock_Polarity \r
- * @{\r
- */\r
- \r
-#define USART_CPOL_Low ((uint16_t)0x0000)\r
-#define USART_CPOL_High ((uint16_t)0x0400)\r
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Clock_Phase\r
- * @{\r
- */\r
-\r
-#define USART_CPHA_1Edge ((uint16_t)0x0000)\r
-#define USART_CPHA_2Edge ((uint16_t)0x0200)\r
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Last_Bit\r
- * @{\r
- */\r
-\r
-#define USART_LastBit_Disable ((uint16_t)0x0000)\r
-#define USART_LastBit_Enable ((uint16_t)0x0100)\r
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
- ((LASTBIT) == USART_LastBit_Enable))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Interrupt_definition \r
- * @{\r
- */\r
- \r
-#define USART_IT_PE ((uint16_t)0x0028)\r
-#define USART_IT_TXE ((uint16_t)0x0727)\r
-#define USART_IT_TC ((uint16_t)0x0626)\r
-#define USART_IT_RXNE ((uint16_t)0x0525)\r
-#define USART_IT_IDLE ((uint16_t)0x0424)\r
-#define USART_IT_LBD ((uint16_t)0x0846)\r
-#define USART_IT_CTS ((uint16_t)0x096A)\r
-#define USART_IT_ERR ((uint16_t)0x0060)\r
-#define USART_IT_ORE ((uint16_t)0x0360)\r
-#define USART_IT_NE ((uint16_t)0x0260)\r
-#define USART_IT_FE ((uint16_t)0x0160)\r
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\r
- ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))\r
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
- ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_DMA_Requests \r
- * @{\r
- */\r
-\r
-#define USART_DMAReq_Tx ((uint16_t)0x0080)\r
-#define USART_DMAReq_Rx ((uint16_t)0x0040)\r
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_WakeUp_methods\r
- * @{\r
- */\r
-\r
-#define USART_WakeUp_IdleLine ((uint16_t)0x0000)\r
-#define USART_WakeUp_AddressMark ((uint16_t)0x0800)\r
-#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
- ((WAKEUP) == USART_WakeUp_AddressMark))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_LIN_Break_Detection_Length \r
- * @{\r
- */\r
- \r
-#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)\r
-#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)\r
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
- (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
- ((LENGTH) == USART_LINBreakDetectLength_11b))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_IrDA_Low_Power \r
- * @{\r
- */\r
-\r
-#define USART_IrDAMode_LowPower ((uint16_t)0x0004)\r
-#define USART_IrDAMode_Normal ((uint16_t)0x0000)\r
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
- ((MODE) == USART_IrDAMode_Normal))\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Flags \r
- * @{\r
- */\r
-\r
-#define USART_FLAG_CTS ((uint16_t)0x0200)\r
-#define USART_FLAG_LBD ((uint16_t)0x0100)\r
-#define USART_FLAG_TXE ((uint16_t)0x0080)\r
-#define USART_FLAG_TC ((uint16_t)0x0040)\r
-#define USART_FLAG_RXNE ((uint16_t)0x0020)\r
-#define USART_FLAG_IDLE ((uint16_t)0x0010)\r
-#define USART_FLAG_ORE ((uint16_t)0x0008)\r
-#define USART_FLAG_NE ((uint16_t)0x0004)\r
-#define USART_FLAG_FE ((uint16_t)0x0002)\r
-#define USART_FLAG_PE ((uint16_t)0x0001)\r
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
- ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
- ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
- \r
-#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
-#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\\r
- ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \\r
- || ((USART_FLAG) != USART_FLAG_CTS)) \r
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))\r
-#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Exported_Macros\r
- * @{\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup USART_Exported_Functions\r
- * @{\r
- */\r
-\r
-void USART_DeInit(USART_TypeDef* USARTx);\r
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
-void USART_SendBreak(USART_TypeDef* USARTx);\r
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_USART_H */\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_wwdg.h\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file contains all the functions prototypes for the WWDG firmware\r
- * library.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __STM32F10x_WWDG_H\r
-#define __STM32F10x_WWDG_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup WWDG\r
- * @{\r
- */ \r
-\r
-/** @defgroup WWDG_Exported_Types\r
- * @{\r
- */ \r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup WWDG_Exported_Constants\r
- * @{\r
- */ \r
- \r
-/** @defgroup WWDG_Prescaler \r
- * @{\r
- */ \r
- \r
-#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r
-#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r
-#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r
-#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
- ((PRESCALER) == WWDG_Prescaler_2) || \\r
- ((PRESCALER) == WWDG_Prescaler_4) || \\r
- ((PRESCALER) == WWDG_Prescaler_8))\r
-#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup WWDG_Exported_Macros\r
- * @{\r
- */ \r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup WWDG_Exported_Functions\r
- * @{\r
- */ \r
- \r
-void WWDG_DeInit(void);\r
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r
-void WWDG_SetWindowValue(uint8_t WindowValue);\r
-void WWDG_EnableIT(void);\r
-void WWDG_SetCounter(uint8_t Counter);\r
-void WWDG_Enable(uint8_t Counter);\r
-FlagStatus WWDG_GetFlagStatus(void);\r
-void WWDG_ClearFlag(void);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __STM32F10x_WWDG_H */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_adc.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the ADC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_adc.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup ADC \r
- * @brief ADC driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup ADC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Private_Defines\r
- * @{\r
- */\r
-\r
-/* ADC DISCNUM mask */\r
-#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)\r
-\r
-/* ADC DISCEN mask */\r
-#define CR1_DISCEN_Set ((uint32_t)0x00000800)\r
-#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)\r
-\r
-/* ADC JAUTO mask */\r
-#define CR1_JAUTO_Set ((uint32_t)0x00000400)\r
-#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)\r
-\r
-/* ADC JDISCEN mask */\r
-#define CR1_JDISCEN_Set ((uint32_t)0x00001000)\r
-#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)\r
-\r
-/* ADC AWDCH mask */\r
-#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)\r
-\r
-/* ADC Analog watchdog enable mode mask */\r
-#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)\r
-\r
-/* CR1 register Mask */\r
-#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)\r
-\r
-/* ADC ADON mask */\r
-#define CR2_ADON_Set ((uint32_t)0x00000001)\r
-#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)\r
-\r
-/* ADC DMA mask */\r
-#define CR2_DMA_Set ((uint32_t)0x00000100)\r
-#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)\r
-\r
-/* ADC RSTCAL mask */\r
-#define CR2_RSTCAL_Set ((uint32_t)0x00000008)\r
-\r
-/* ADC CAL mask */\r
-#define CR2_CAL_Set ((uint32_t)0x00000004)\r
-\r
-/* ADC SWSTART mask */\r
-#define CR2_SWSTART_Set ((uint32_t)0x00400000)\r
-\r
-/* ADC EXTTRIG mask */\r
-#define CR2_EXTTRIG_Set ((uint32_t)0x00100000)\r
-#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)\r
-\r
-/* ADC Software start mask */\r
-#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)\r
-#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)\r
-\r
-/* ADC JEXTSEL mask */\r
-#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)\r
-\r
-/* ADC JEXTTRIG mask */\r
-#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)\r
-#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)\r
-\r
-/* ADC JSWSTART mask */\r
-#define CR2_JSWSTART_Set ((uint32_t)0x00200000)\r
-\r
-/* ADC injected software start mask */\r
-#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)\r
-#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)\r
-\r
-/* ADC TSPD mask */\r
-#define CR2_TSVREFE_Set ((uint32_t)0x00800000)\r
-#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)\r
-\r
-/* CR2 register Mask */\r
-#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)\r
-\r
-/* ADC SQx mask */\r
-#define SQR3_SQ_Set ((uint32_t)0x0000001F)\r
-#define SQR2_SQ_Set ((uint32_t)0x0000001F)\r
-#define SQR1_SQ_Set ((uint32_t)0x0000001F)\r
-\r
-/* SQR1 register Mask */\r
-#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)\r
-\r
-/* ADC JSQx mask */\r
-#define JSQR_JSQ_Set ((uint32_t)0x0000001F)\r
-\r
-/* ADC JL mask */\r
-#define JSQR_JL_Set ((uint32_t)0x00300000)\r
-#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)\r
-\r
-/* ADC SMPx mask */\r
-#define SMPR1_SMP_Set ((uint32_t)0x00000007)\r
-#define SMPR2_SMP_Set ((uint32_t)0x00000007)\r
-\r
-/* ADC JDRx registers offset */\r
-#define JDR_Offset ((uint8_t)0x28)\r
-\r
-/* ADC1 DR register base address */\r
-#define DR_ADDRESS ((uint32_t)0x4001244C)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup ADC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the ADCx peripheral registers to their default reset values.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval None\r
- */\r
-void ADC_DeInit(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- \r
- if (ADCx == ADC1)\r
- {\r
- /* Enable ADC1 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
- /* Release ADC1 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
- }\r
- else if (ADCx == ADC2)\r
- {\r
- /* Enable ADC2 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);\r
- /* Release ADC2 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);\r
- }\r
- else\r
- {\r
- if (ADCx == ADC3)\r
- {\r
- /* Enable ADC3 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);\r
- /* Release ADC3 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the ADCx peripheral according to the specified parameters\r
- * in the ADC_InitStruct.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains\r
- * the configuration information for the specified ADC peripheral.\r
- * @retval None\r
- */\r
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)\r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint8_t tmpreg2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));\r
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));\r
- assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r
- assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));\r
-\r
- /*---------------------------- ADCx CR1 Configuration -----------------*/\r
- /* Get the ADCx CR1 value */\r
- tmpreg1 = ADCx->CR1;\r
- /* Clear DUALMOD and SCAN bits */\r
- tmpreg1 &= CR1_CLEAR_Mask;\r
- /* Configure ADCx: Dual mode and scan conversion mode */\r
- /* Set DUALMOD bits according to ADC_Mode value */\r
- /* Set SCAN bit according to ADC_ScanConvMode value */\r
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));\r
- /* Write to ADCx CR1 */\r
- ADCx->CR1 = tmpreg1;\r
-\r
- /*---------------------------- ADCx CR2 Configuration -----------------*/\r
- /* Get the ADCx CR2 value */\r
- tmpreg1 = ADCx->CR2;\r
- /* Clear CONT, ALIGN and EXTSEL bits */\r
- tmpreg1 &= CR2_CLEAR_Mask;\r
- /* Configure ADCx: external trigger event and continuous conversion mode */\r
- /* Set ALIGN bit according to ADC_DataAlign value */\r
- /* Set EXTSEL bits according to ADC_ExternalTrigConv value */\r
- /* Set CONT bit according to ADC_ContinuousConvMode value */\r
- tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |\r
- ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r
- /* Write to ADCx CR2 */\r
- ADCx->CR2 = tmpreg1;\r
-\r
- /*---------------------------- ADCx SQR1 Configuration -----------------*/\r
- /* Get the ADCx SQR1 value */\r
- tmpreg1 = ADCx->SQR1;\r
- /* Clear L bits */\r
- tmpreg1 &= SQR1_CLEAR_Mask;\r
- /* Configure ADCx: regular channel sequence length */\r
- /* Set L bits according to ADC_NbrOfChannel value */\r
- tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);\r
- tmpreg1 |= (uint32_t)tmpreg2 << 20;\r
- /* Write to ADCx SQR1 */\r
- ADCx->SQR1 = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Fills each ADC_InitStruct member with its default value.\r
- * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)\r
-{\r
- /* Reset ADC init structure parameters values */\r
- /* Initialize the ADC_Mode member */\r
- ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;\r
- /* initialize the ADC_ScanConvMode member */\r
- ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r
- /* Initialize the ADC_ContinuousConvMode member */\r
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
- /* Initialize the ADC_ExternalTrigConv member */\r
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;\r
- /* Initialize the ADC_DataAlign member */\r
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
- /* Initialize the ADC_NbrOfChannel member */\r
- ADC_InitStruct->ADC_NbrOfChannel = 1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified ADC peripheral.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the ADCx peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the ADON bit to wake up the ADC from power down mode */\r
- ADCx->CR2 |= CR2_ADON_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC peripheral */\r
- ADCx->CR2 &= CR2_ADON_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified ADC DMA request.\r
- * @param ADCx: where x can be 1 or 3 to select the ADC peripheral.\r
- * Note: ADC2 hasn't a DMA capability.\r
- * @param NewState: new state of the selected ADC DMA transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_DMA_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC DMA request */\r
- ADCx->CR2 |= CR2_DMA_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC DMA request */\r
- ADCx->CR2 &= CR2_DMA_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified ADC interrupts.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt mask\r
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
- * @param NewState: new state of the specified ADC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)\r
-{\r
- uint8_t itmask = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_ADC_IT(ADC_IT));\r
- /* Get the ADC IT index */\r
- itmask = (uint8_t)ADC_IT;\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC interrupts */\r
- ADCx->CR1 |= itmask;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC interrupts */\r
- ADCx->CR1 &= (~(uint32_t)itmask);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Resets the selected ADC calibration registers.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval None\r
- */\r
-void ADC_ResetCalibration(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Resets the selected ADC calibartion registers */ \r
- ADCx->CR2 |= CR2_RSTCAL_Set;\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC reset calibration registers status.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval The new state of ADC reset calibration registers (SET or RESET).\r
- */\r
-FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Check the status of RSTCAL bit */\r
- if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)\r
- {\r
- /* RSTCAL bit is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* RSTCAL bit is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the RSTCAL bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Starts the selected ADC calibration process.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval None\r
- */\r
-void ADC_StartCalibration(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Enable the selected ADC calibration process */ \r
- ADCx->CR2 |= CR2_CAL_Set;\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC calibration status.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval The new state of ADC calibration (SET or RESET).\r
- */\r
-FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Check the status of CAL bit */\r
- if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)\r
- {\r
- /* CAL bit is set: calibration on going */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* CAL bit is reset: end of calibration */\r
- bitstatus = RESET;\r
- }\r
- /* Return the CAL bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected ADC software start conversion .\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC software start conversion.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC conversion on external event and start the selected\r
- ADC conversion */\r
- ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC conversion on external event and stop the selected\r
- ADC conversion */\r
- ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC Software start conversion Status.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval The new state of ADC software start conversion (SET or RESET).\r
- */\r
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Check the status of SWSTART bit */\r
- if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)\r
- {\r
- /* SWSTART bit is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SWSTART bit is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SWSTART bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Configures the discontinuous mode for the selected ADC regular\r
- * group channel.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param Number: specifies the discontinuous mode regular channel\r
- * count value. This number must be between 1 and 8.\r
- * @retval None\r
- */\r
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)\r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint32_t tmpreg2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->CR1;\r
- /* Clear the old discontinuous mode channel count */\r
- tmpreg1 &= CR1_DISCNUM_Reset;\r
- /* Set the discontinuous mode channel count */\r
- tmpreg2 = Number - 1;\r
- tmpreg1 |= tmpreg2 << 13;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the discontinuous mode on regular group\r
- * channel for the specified ADC\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC discontinuous mode\r
- * on regular group channel.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC regular discontinuous mode */\r
- ADCx->CR1 |= CR1_DISCEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC regular discontinuous mode */\r
- ADCx->CR1 &= CR1_DISCEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures for the selected ADC regular channel its corresponding\r
- * rank in the sequencer and its sample time.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_Channel: the ADC channel to configure. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.\r
- * @param ADC_SampleTime: The sample time value to be set for the selected channel. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles\r
- * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles\r
- * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles\r
- * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles \r
- * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles \r
- * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles \r
- * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles \r
- * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles \r
- * @retval None\r
- */\r
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
- assert_param(IS_ADC_REGULAR_RANK(Rank));\r
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
- /* if ADC_Channel_10 ... ADC_Channel_17 is selected */\r
- if (ADC_Channel > ADC_Channel_9)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));\r
- /* Clear the old channel sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
- /* Set the new channel sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR1 = tmpreg1;\r
- }\r
- else /* ADC_Channel include in ADC_Channel_[0..9] */\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);\r
- /* Clear the old channel sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
- /* Set the new channel sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR2 = tmpreg1;\r
- }\r
- /* For Rank 1 to 6 */\r
- if (Rank < 7)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR3;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR3 = tmpreg1;\r
- }\r
- /* For Rank 7 to 12 */\r
- else if (Rank < 13)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR2 = tmpreg1;\r
- }\r
- /* For Rank 13 to 16 */\r
- else\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SQR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));\r
- /* Clear the old SQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));\r
- /* Set the SQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SQR1 = tmpreg1;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the ADCx conversion through external trigger.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC external trigger start of conversion.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC conversion on external event */\r
- ADCx->CR2 |= CR2_EXTTRIG_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC conversion on external event */\r
- ADCx->CR2 &= CR2_EXTTRIG_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the last ADCx conversion result data for regular channel.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval The Data conversion value.\r
- */\r
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Return the selected ADC conversion value */\r
- return (uint16_t) ADCx->DR;\r
-}\r
-\r
-/**\r
- * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.\r
- * @retval The Data conversion value.\r
- */\r
-uint32_t ADC_GetDualModeConversionValue(void)\r
-{\r
- /* Return the dual mode conversion value */\r
- return (*(__IO uint32_t *) DR_ADDRESS);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected ADC automatic injected group\r
- * conversion after regular one.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC auto injected conversion\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC automatic injected group conversion */\r
- ADCx->CR1 |= CR1_JAUTO_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC automatic injected group conversion */\r
- ADCx->CR1 &= CR1_JAUTO_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the discontinuous mode for injected group\r
- * channel for the specified ADC\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC discontinuous mode\r
- * on injected group channel.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC injected discontinuous mode */\r
- ADCx->CR1 |= CR1_JDISCEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC injected discontinuous mode */\r
- ADCx->CR1 &= CR1_JDISCEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the ADCx external trigger for injected channels conversion.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)\r
- * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)\r
- * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)\r
- * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)\r
- * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)\r
- * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)\r
- * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8\r
- * capture compare4 event selected (for ADC1 and ADC2) \r
- * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)\r
- * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) \r
- * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)\r
- * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) \r
- * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) \r
- * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not\r
- * by external trigger (for ADC1, ADC2 and ADC3)\r
- * @retval None\r
- */\r
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR2;\r
- /* Clear the old external event selection for injected group */\r
- tmpreg &= CR2_JEXTSEL_Reset;\r
- /* Set the external event selection for injected group */\r
- tmpreg |= ADC_ExternalTrigInjecConv;\r
- /* Store the new register value */\r
- ADCx->CR2 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the ADCx injected channels conversion through\r
- * external trigger\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC external trigger start of\r
- * injected conversion.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC external event selection for injected group */\r
- ADCx->CR2 |= CR2_JEXTTRIG_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC external event selection for injected group */\r
- ADCx->CR2 &= CR2_JEXTTRIG_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected ADC start of the injected \r
- * channels conversion.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param NewState: new state of the selected ADC software start injected conversion.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected ADC conversion for injected group on external event and start the selected\r
- ADC injected conversion */\r
- ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected ADC conversion on external event for injected group and stop the selected\r
- ADC injected conversion */\r
- ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Gets the selected ADC Software start injected conversion Status.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @retval The new state of ADC software start injected conversion (SET or RESET).\r
- */\r
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- /* Check the status of JSWSTART bit */\r
- if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)\r
- {\r
- /* JSWSTART bit is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* JSWSTART bit is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the JSWSTART bit status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Configures for the selected ADC injected channel its corresponding\r
- * rank in the sequencer and its sample time.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_Channel: the ADC channel to configure. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.\r
- * @param ADC_SampleTime: The sample time value to be set for the selected channel. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles\r
- * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles\r
- * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles\r
- * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles \r
- * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles \r
- * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles \r
- * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles \r
- * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles \r
- * @retval None\r
- */\r
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
- assert_param(IS_ADC_INJECTED_RANK(Rank));\r
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
- /* if ADC_Channel_10 ... ADC_Channel_17 is selected */\r
- if (ADC_Channel > ADC_Channel_9)\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR1;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));\r
- /* Clear the old channel sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));\r
- /* Set the new channel sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR1 = tmpreg1;\r
- }\r
- else /* ADC_Channel include in ADC_Channel_[0..9] */\r
- {\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->SMPR2;\r
- /* Calculate the mask to clear */\r
- tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);\r
- /* Clear the old channel sample time */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set */\r
- tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
- /* Set the new channel sample time */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->SMPR2 = tmpreg1;\r
- }\r
- /* Rank configuration */\r
- /* Get the old register value */\r
- tmpreg1 = ADCx->JSQR;\r
- /* Get JL value: Number = JL+1 */\r
- tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;\r
- /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */\r
- tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
- /* Clear the old JSQx bits for the selected rank */\r
- tmpreg1 &= ~tmpreg2;\r
- /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */\r
- tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
- /* Set the JSQx bits for the selected rank */\r
- tmpreg1 |= tmpreg2;\r
- /* Store the new register value */\r
- ADCx->JSQR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Configures the sequencer length for injected channels\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param Length: The sequencer length. \r
- * This parameter must be a number between 1 to 4.\r
- * @retval None\r
- */\r
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)\r
-{\r
- uint32_t tmpreg1 = 0;\r
- uint32_t tmpreg2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_LENGTH(Length));\r
- \r
- /* Get the old register value */\r
- tmpreg1 = ADCx->JSQR;\r
- /* Clear the old injected sequnence lenght JL bits */\r
- tmpreg1 &= JSQR_JL_Reset;\r
- /* Set the injected sequnence lenght JL bits */\r
- tmpreg2 = Length - 1; \r
- tmpreg1 |= tmpreg2 << 20;\r
- /* Store the new register value */\r
- ADCx->JSQR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Set the injected channels conversion value offset\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_InjectedChannel: the ADC injected channel to set its offset. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
- * @param Offset: the offset value for the selected ADC injected channel\r
- * This parameter must be a 12bit value.\r
- * @retval None\r
- */\r
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
- assert_param(IS_ADC_OFFSET(Offset)); \r
- \r
- tmp = (uint32_t)ADCx;\r
- tmp += ADC_InjectedChannel;\r
- \r
- /* Set the selected injected channel data offset */\r
- *(__IO uint32_t *) tmp = (uint32_t)Offset;\r
-}\r
-\r
-/**\r
- * @brief Returns the ADC injected channel conversion result\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_InjectedChannel: the converted ADC injected channel.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
- * @retval The Data conversion value.\r
- */\r
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
-\r
- tmp = (uint32_t)ADCx;\r
- tmp += ADC_InjectedChannel + JDR_Offset;\r
- \r
- /* Returns the selected injected channel conversion data value */\r
- return (uint16_t) (*(__IO uint32_t*) tmp); \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the analog watchdog on single/all regular\r
- * or injected channels\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r
- * This parameter can be one of the following values:\r
- * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel\r
- * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel\r
- * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel\r
- * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel\r
- * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel\r
- * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels\r
- * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog\r
- * @retval None \r
- */\r
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR1;\r
- /* Clear AWDEN, AWDENJ and AWDSGL bits */\r
- tmpreg &= CR1_AWDMode_Reset;\r
- /* Set the analog watchdog enable mode */\r
- tmpreg |= ADC_AnalogWatchdog;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Configures the high and low thresholds of the analog watchdog.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param HighThreshold: the ADC analog watchdog High threshold value.\r
- * This parameter must be a 12bit value.\r
- * @param LowThreshold: the ADC analog watchdog Low threshold value.\r
- * This parameter must be a 12bit value.\r
- * @retval None\r
- */\r
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r
- uint16_t LowThreshold)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_THRESHOLD(HighThreshold));\r
- assert_param(IS_ADC_THRESHOLD(LowThreshold));\r
- /* Set the ADCx high threshold */\r
- ADCx->HTR = HighThreshold;\r
- /* Set the ADCx low threshold */\r
- ADCx->LTR = LowThreshold;\r
-}\r
-\r
-/**\r
- * @brief Configures the analog watchdog guarded single channel\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_Channel: the ADC channel to configure for the analog watchdog. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_Channel_0: ADC Channel0 selected\r
- * @arg ADC_Channel_1: ADC Channel1 selected\r
- * @arg ADC_Channel_2: ADC Channel2 selected\r
- * @arg ADC_Channel_3: ADC Channel3 selected\r
- * @arg ADC_Channel_4: ADC Channel4 selected\r
- * @arg ADC_Channel_5: ADC Channel5 selected\r
- * @arg ADC_Channel_6: ADC Channel6 selected\r
- * @arg ADC_Channel_7: ADC Channel7 selected\r
- * @arg ADC_Channel_8: ADC Channel8 selected\r
- * @arg ADC_Channel_9: ADC Channel9 selected\r
- * @arg ADC_Channel_10: ADC Channel10 selected\r
- * @arg ADC_Channel_11: ADC Channel11 selected\r
- * @arg ADC_Channel_12: ADC Channel12 selected\r
- * @arg ADC_Channel_13: ADC Channel13 selected\r
- * @arg ADC_Channel_14: ADC Channel14 selected\r
- * @arg ADC_Channel_15: ADC Channel15 selected\r
- * @arg ADC_Channel_16: ADC Channel16 selected\r
- * @arg ADC_Channel_17: ADC Channel17 selected\r
- * @retval None\r
- */\r
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
- /* Get the old register value */\r
- tmpreg = ADCx->CR1;\r
- /* Clear the Analog watchdog channel select bits */\r
- tmpreg &= CR1_AWDCH_Reset;\r
- /* Set the Analog watchdog channel */\r
- tmpreg |= ADC_Channel;\r
- /* Store the new register value */\r
- ADCx->CR1 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the temperature sensor and Vrefint channel.\r
- * @param NewState: new state of the temperature sensor.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void ADC_TempSensorVrefintCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the temperature sensor and Vrefint channel*/\r
- ADC1->CR2 |= CR2_TSVREFE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the temperature sensor and Vrefint channel*/\r
- ADC1->CR2 &= CR2_TSVREFE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified ADC flag is set or not.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_FLAG: specifies the flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_FLAG_AWD: Analog watchdog flag\r
- * @arg ADC_FLAG_EOC: End of conversion flag\r
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
- * @retval The new state of ADC_FLAG (SET or RESET).\r
- */\r
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r
- /* Check the status of the specified ADC flag */\r
- if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)\r
- {\r
- /* ADC_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* ADC_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the ADC_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the ADCx's pending flags.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_FLAG: specifies the flag to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg ADC_FLAG_AWD: Analog watchdog flag\r
- * @arg ADC_FLAG_EOC: End of conversion flag\r
- * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
- * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
- * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
- * @retval None\r
- */\r
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
- /* Clear the selected ADC flags */\r
- ADCx->SR = ~(uint32_t)ADC_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified ADC interrupt has occurred or not.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt mask\r
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
- * @retval The new state of ADC_IT (SET or RESET).\r
- */\r
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t itmask = 0, enablestatus = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_GET_IT(ADC_IT));\r
- /* Get the ADC IT index */\r
- itmask = ADC_IT >> 8;\r
- /* Get the ADC_IT enable bit status */\r
- enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;\r
- /* Check the status of the specified ADC interrupt */\r
- if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* ADC_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* ADC_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the ADC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the ADCx\92s interrupt pending bits.\r
- * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg ADC_IT_EOC: End of conversion interrupt mask\r
- * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
- * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
- * @retval None\r
- */\r
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
-{\r
- uint8_t itmask = 0;\r
- /* Check the parameters */\r
- assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
- assert_param(IS_ADC_IT(ADC_IT));\r
- /* Get the ADC IT index */\r
- itmask = (uint8_t)(ADC_IT >> 8);\r
- /* Clear the selected ADC interrupt pending bits */\r
- ADCx->SR = ~(uint32_t)itmask;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_bkp.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the BKP firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_bkp.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup BKP \r
- * @brief BKP driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup BKP_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Private_Defines\r
- * @{\r
- */\r
-\r
-/* ------------ BKP registers bit address in the alias region --------------- */\r
-#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)\r
-\r
-/* --- CR Register ----*/\r
-\r
-/* Alias word address of TPAL bit */\r
-#define CR_OFFSET (BKP_OFFSET + 0x30)\r
-#define TPAL_BitNumber 0x01\r
-#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))\r
-\r
-/* Alias word address of TPE bit */\r
-#define TPE_BitNumber 0x00\r
-#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))\r
-\r
-/* --- CSR Register ---*/\r
-\r
-/* Alias word address of TPIE bit */\r
-#define CSR_OFFSET (BKP_OFFSET + 0x34)\r
-#define TPIE_BitNumber 0x02\r
-#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))\r
-\r
-/* Alias word address of TIF bit */\r
-#define TIF_BitNumber 0x09\r
-#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))\r
-\r
-/* Alias word address of TEF bit */\r
-#define TEF_BitNumber 0x08\r
-#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))\r
-\r
-/* ---------------------- BKP registers bit mask ------------------------ */\r
-\r
-/* RTCCR register bit mask */\r
-#define RTCCR_CAL_MASK ((uint16_t)0xFF80)\r
-#define RTCCR_MASK ((uint16_t)0xFC7F)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup BKP_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup BKP_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the BKP peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void BKP_DeInit(void)\r
-{\r
- RCC_BackupResetCmd(ENABLE);\r
- RCC_BackupResetCmd(DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Configures the Tamper Pin active level.\r
- * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.\r
- * This parameter can be one of the following values:\r
- * @arg BKP_TamperPinLevel_High: Tamper pin active on high level\r
- * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level\r
- * @retval None\r
- */\r
-void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));\r
- *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Tamper Pin activation.\r
- * @param NewState: new state of the Tamper Pin activation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void BKP_TamperPinCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Tamper Pin Interrupt.\r
- * @param NewState: new state of the Tamper Pin Interrupt.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void BKP_ITConfig(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Select the RTC output source to output on the Tamper pin.\r
- * @param BKP_RTCOutputSource: specifies the RTC output source.\r
- * This parameter can be one of the following values:\r
- * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.\r
- * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency\r
- * divided by 64 on the Tamper pin.\r
- * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on\r
- * the Tamper pin.\r
- * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on\r
- * the Tamper pin. \r
- * @retval None\r
- */\r
-void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)\r
-{\r
- uint16_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));\r
- tmpreg = BKP->RTCCR;\r
- /* Clear CCO, ASOE and ASOS bits */\r
- tmpreg &= RTCCR_MASK;\r
- \r
- /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */\r
- tmpreg |= BKP_RTCOutputSource;\r
- /* Store the new value */\r
- BKP->RTCCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Sets RTC Clock Calibration value.\r
- * @param CalibrationValue: specifies the RTC Clock Calibration value.\r
- * This parameter must be a number between 0 and 0x7F.\r
- * @retval None\r
- */\r
-void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)\r
-{\r
- uint16_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));\r
- tmpreg = BKP->RTCCR;\r
- /* Clear CAL[6:0] bits */\r
- tmpreg &= RTCCR_CAL_MASK;\r
- /* Set CAL[6:0] bits according to CalibrationValue value */\r
- tmpreg |= CalibrationValue;\r
- /* Store the new value */\r
- BKP->RTCCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Writes user data to the specified Data Backup Register.\r
- * @param BKP_DR: specifies the Data Backup Register.\r
- * This parameter can be BKP_DRx where x:[1, 42]\r
- * @param Data: data to write\r
- * @retval None\r
- */\r
-void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_BKP_DR(BKP_DR));\r
-\r
- tmp = (uint32_t)BKP_BASE; \r
- tmp += BKP_DR;\r
-\r
- *(__IO uint32_t *) tmp = Data;\r
-}\r
-\r
-/**\r
- * @brief Reads data from the specified Data Backup Register.\r
- * @param BKP_DR: specifies the Data Backup Register.\r
- * This parameter can be BKP_DRx where x:[1, 42]\r
- * @retval The content of the specified Data Backup Register\r
- */\r
-uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_BKP_DR(BKP_DR));\r
-\r
- tmp = (uint32_t)BKP_BASE; \r
- tmp += BKP_DR;\r
-\r
- return (*(__IO uint16_t *) tmp);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the Tamper Pin Event flag is set or not.\r
- * @param None\r
- * @retval The new state of the Tamper Pin Event flag (SET or RESET).\r
- */\r
-FlagStatus BKP_GetFlagStatus(void)\r
-{\r
- return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);\r
-}\r
-\r
-/**\r
- * @brief Clears Tamper Pin Event pending flag.\r
- * @param None\r
- * @retval None\r
- */\r
-void BKP_ClearFlag(void)\r
-{\r
- /* Set CTE bit to clear Tamper Pin Event flag */\r
- BKP->CSR |= BKP_CSR_CTE;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the Tamper Pin Interrupt has occurred or not.\r
- * @param None\r
- * @retval The new state of the Tamper Pin Interrupt (SET or RESET).\r
- */\r
-ITStatus BKP_GetITStatus(void)\r
-{\r
- return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);\r
-}\r
-\r
-/**\r
- * @brief Clears Tamper Pin Interrupt pending bit.\r
- * @param None\r
- * @retval None\r
- */\r
-void BKP_ClearITPendingBit(void)\r
-{\r
- /* Set CTI bit to clear Tamper Pin Interrupt pending bit */\r
- BKP->CSR |= BKP_CSR_CTI;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_can.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the CAN firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_can.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup CAN \r
- * @brief CAN driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup CAN_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Private_Defines\r
- * @{\r
- */\r
-\r
-/* CAN Master Control Register bits */\r
-\r
-#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */\r
-\r
-/* CAN Mailbox Transmit Request */\r
-#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */\r
-\r
-/* CAN Filter Master Register bits */\r
-#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */\r
-\r
-/* Time out for INAK bit */\r
-#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)\r
-/* Time out for SLAK bit */\r
-#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)\r
-\r
-\r
-\r
-/* Flags in TSR register */\r
-#define CAN_FLAGS_TSR ((uint32_t)0x08000000) \r
-/* Flags in RF1R register */\r
-#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) \r
-/* Flags in RF0R register */\r
-#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) \r
-/* Flags in MSR register */\r
-#define CAN_FLAGS_MSR ((uint32_t)0x01000000) \r
-/* Flags in ESR register */\r
-#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) \r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CAN_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the CAN peripheral registers to their default reset values.\r
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r
- * @retval None.\r
- */\r
-void CAN_DeInit(CAN_TypeDef* CANx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- \r
- if (CANx == CAN1)\r
- {\r
- /* Enable CAN1 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);\r
- /* Release CAN1 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);\r
- }\r
- else\r
- { \r
- /* Enable CAN2 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);\r
- /* Release CAN2 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the CAN peripheral according to the specified\r
- * parameters in the CAN_InitStruct.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that\r
- * contains the configuration information for the CAN peripheral.\r
- * @retval Constant indicates initialization succeed which will be \r
- * CANINITFAILED or CANINITOK.\r
- */\r
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)\r
-{\r
- uint8_t InitStatus = CANINITFAILED;\r
- uint32_t wait_ack = 0x00000000;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));\r
- assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));\r
- assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));\r
- assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));\r
- assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));\r
- assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));\r
-\r
- /* exit from sleep mode */\r
- CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);\r
-\r
- /* Request initialisation */\r
- CANx->MCR |= CAN_MCR_INRQ ;\r
-\r
- /* Wait the acknowledge */\r
- while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))\r
- {\r
- wait_ack++;\r
- }\r
-\r
- /* ...and check acknowledged */\r
- if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r
- {\r
- InitStatus = CANINITFAILED;\r
- }\r
- else \r
- {\r
- /* Set the time triggered communication mode */\r
- if (CAN_InitStruct->CAN_TTCM == ENABLE)\r
- {\r
- CANx->MCR |= CAN_MCR_TTCM;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;\r
- }\r
-\r
- /* Set the automatic bus-off management */\r
- if (CAN_InitStruct->CAN_ABOM == ENABLE)\r
- {\r
- CANx->MCR |= CAN_MCR_ABOM;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;\r
- }\r
-\r
- /* Set the automatic wake-up mode */\r
- if (CAN_InitStruct->CAN_AWUM == ENABLE)\r
- {\r
- CANx->MCR |= CAN_MCR_AWUM;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;\r
- }\r
-\r
- /* Set the no automatic retransmission */\r
- if (CAN_InitStruct->CAN_NART == ENABLE)\r
- {\r
- CANx->MCR |= CAN_MCR_NART;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~(uint32_t)CAN_MCR_NART;\r
- }\r
-\r
- /* Set the receive FIFO locked mode */\r
- if (CAN_InitStruct->CAN_RFLM == ENABLE)\r
- {\r
- CANx->MCR |= CAN_MCR_RFLM;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;\r
- }\r
-\r
- /* Set the transmit FIFO priority */\r
- if (CAN_InitStruct->CAN_TXFP == ENABLE)\r
- {\r
- CANx->MCR |= CAN_MCR_TXFP;\r
- }\r
- else\r
- {\r
- CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;\r
- }\r
-\r
- /* Set the bit timing register */\r
- CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) |\r
- ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) |\r
- ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);\r
-\r
- /* Request leave initialisation */\r
- CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;\r
-\r
- /* Wait the acknowledge */\r
- wait_ack = 0x00;\r
-\r
- while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))\r
- {\r
- wait_ack++;\r
- }\r
-\r
- /* ...and check acknowledged */\r
- if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r
- {\r
- InitStatus = CANINITFAILED;\r
- }\r
- else\r
- {\r
- InitStatus = CANINITOK ;\r
- }\r
- }\r
-\r
- /* At this step, return the status of initialization */\r
- return InitStatus;\r
-}\r
-\r
-/**\r
- * @brief Initializes the CAN peripheral according to the specified\r
- * parameters in the CAN_FilterInitStruct.\r
- * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef\r
- * structure that contains the configuration information.\r
- * @retval None.\r
- */\r
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)\r
-{\r
- uint32_t filter_number_bit_pos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));\r
- assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));\r
- assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));\r
- assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));\r
- assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));\r
-\r
- filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber;\r
-\r
- /* Initialisation mode for the filter */\r
- CAN1->FMR |= FMR_FINIT;\r
-\r
- /* Filter Deactivation */\r
- CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;\r
-\r
- /* Filter Scale */\r
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)\r
- {\r
- /* 16-bit scale for the filter */\r
- CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;\r
-\r
- /* First 16-bit identifier and First 16-bit mask */\r
- /* Or First 16-bit identifier and Second 16-bit identifier */\r
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |\r
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r
-\r
- /* Second 16-bit identifier and Second 16-bit mask */\r
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);\r
- }\r
-\r
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)\r
- {\r
- /* 32-bit scale for the filter */\r
- CAN1->FS1R |= filter_number_bit_pos;\r
- /* 32-bit identifier or First 32-bit identifier */\r
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |\r
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r
- /* 32-bit mask or Second 32-bit identifier */\r
- CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);\r
- }\r
-\r
- /* Filter Mode */\r
- if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)\r
- {\r
- /*Id/Mask mode for the filter*/\r
- CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;\r
- }\r
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r
- {\r
- /*Identifier list mode for the filter*/\r
- CAN1->FM1R |= (uint32_t)filter_number_bit_pos;\r
- }\r
-\r
- /* Filter FIFO assignment */\r
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)\r
- {\r
- /* FIFO 0 assignation for the filter */\r
- CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;\r
- }\r
-\r
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)\r
- {\r
- /* FIFO 1 assignation for the filter */\r
- CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;\r
- }\r
- \r
- /* Filter activation */\r
- if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)\r
- {\r
- CAN1->FA1R |= filter_number_bit_pos;\r
- }\r
-\r
- /* Leave the initialisation mode for the filter */\r
- CAN1->FMR &= ~FMR_FINIT;\r
-}\r
-\r
-/**\r
- * @brief Fills each CAN_InitStruct member with its default value.\r
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which\r
- * will be initialized.\r
- * @retval None.\r
- */\r
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)\r
-{\r
- /* Reset CAN init structure parameters values */\r
- /* Initialize the time triggered communication mode */\r
- CAN_InitStruct->CAN_TTCM = DISABLE;\r
- /* Initialize the automatic bus-off management */\r
- CAN_InitStruct->CAN_ABOM = DISABLE;\r
- /* Initialize the automatic wake-up mode */\r
- CAN_InitStruct->CAN_AWUM = DISABLE;\r
- /* Initialize the no automatic retransmission */\r
- CAN_InitStruct->CAN_NART = DISABLE;\r
- /* Initialize the receive FIFO locked mode */\r
- CAN_InitStruct->CAN_RFLM = DISABLE;\r
- /* Initialize the transmit FIFO priority */\r
- CAN_InitStruct->CAN_TXFP = DISABLE;\r
- /* Initialize the CAN_Mode member */\r
- CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;\r
- /* Initialize the CAN_SJW member */\r
- CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;\r
- /* Initialize the CAN_BS1 member */\r
- CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;\r
- /* Initialize the CAN_BS2 member */\r
- CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;\r
- /* Initialize the CAN_Prescaler member */\r
- CAN_InitStruct->CAN_Prescaler = 1;\r
-}\r
-\r
-/**\r
- * @brief Select the start bank filter for slave CAN.\r
- * @note This function applies only to STM32 Connectivity line devices.\r
- * @param CAN_BankNumber: Select the start slave bank filter from 1..27.\r
- * @retval None.\r
- */\r
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber) \r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));\r
- /* enter Initialisation mode for the filter */\r
- CAN1->FMR |= FMR_FINIT;\r
- /* Select the start slave bank */\r
- CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;\r
- CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;\r
- /* Leave Initialisation mode for the filter */\r
- CAN1->FMR &= ~FMR_FINIT;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified CANx interrupts.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.\r
- * This parameter can be: \r
- * -CAN_IT_TME, \r
- * -CAN_IT_FMP0, \r
- * -CAN_IT_FF0,\r
- * -CAN_IT_FOV0, \r
- * -CAN_IT_FMP1, \r
- * -CAN_IT_FF1,\r
- * -CAN_IT_FOV1, \r
- * -CAN_IT_EWG, \r
- * -CAN_IT_EPV,\r
- * -CAN_IT_LEC, \r
- * -CAN_IT_ERR, \r
- * -CAN_IT_WKU or \r
- * -CAN_IT_SLK.\r
- * @param NewState: new state of the CAN interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_IT(CAN_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected CANx interrupt */\r
- CANx->IER |= CAN_IT;\r
- }\r
- else\r
- {\r
- /* Disable the selected CANx interrupt */\r
- CANx->IER &= ~CAN_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initiates the transmission of a message.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param TxMessage: pointer to a structure which contains CAN Id, CAN\r
- * DLC and CAN datas.\r
- * @retval The number of the mailbox that is used for transmission\r
- * or CAN_NO_MB if there is no empty mailbox.\r
- */\r
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)\r
-{\r
- uint8_t transmit_mailbox = 0;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_IDTYPE(TxMessage->IDE));\r
- assert_param(IS_CAN_RTR(TxMessage->RTR));\r
- assert_param(IS_CAN_DLC(TxMessage->DLC));\r
-\r
- /* Select one empty transmit mailbox */\r
- if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r
- {\r
- transmit_mailbox = 0;\r
- }\r
- else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r
- {\r
- transmit_mailbox = 1;\r
- }\r
- else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)\r
- {\r
- transmit_mailbox = 2;\r
- }\r
- else\r
- {\r
- transmit_mailbox = CAN_NO_MB;\r
- }\r
-\r
- if (transmit_mailbox != CAN_NO_MB)\r
- {\r
- /* Set up the Id */\r
- CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;\r
- if (TxMessage->IDE == CAN_ID_STD)\r
- {\r
- assert_param(IS_CAN_STDID(TxMessage->StdId)); \r
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR);\r
- }\r
- else\r
- {\r
- assert_param(IS_CAN_EXTID(TxMessage->ExtId));\r
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | \r
- TxMessage->RTR);\r
- }\r
- \r
-\r
- /* Set up the DLC */\r
- TxMessage->DLC &= (uint8_t)0x0000000F;\r
- CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;\r
- CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;\r
-\r
- /* Set up the data field */\r
- CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | \r
- ((uint32_t)TxMessage->Data[2] << 16) |\r
- ((uint32_t)TxMessage->Data[1] << 8) | \r
- ((uint32_t)TxMessage->Data[0]));\r
- CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | \r
- ((uint32_t)TxMessage->Data[6] << 16) |\r
- ((uint32_t)TxMessage->Data[5] << 8) |\r
- ((uint32_t)TxMessage->Data[4]));\r
- /* Request transmission */\r
- CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;\r
- }\r
- return transmit_mailbox;\r
-}\r
-\r
-/**\r
- * @brief Checks the transmission of a message.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param TransmitMailbox: the number of the mailbox that is used for transmission.\r
- * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case.\r
- */\r
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)\r
-{\r
- /* RQCP, TXOK and TME bits */\r
- uint8_t state = 0;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));\r
- switch (TransmitMailbox)\r
- {\r
- case (0): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP0) << 2);\r
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK0) >> 0);\r
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TME0) >> 26);\r
- break;\r
- case (1): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP1) >> 6);\r
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK1) >> 8);\r
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TME1) >> 27);\r
- break;\r
- case (2): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP2) >> 14);\r
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK2) >> 16);\r
- state |= (uint8_t)((CANx->TSR & CAN_TSR_TME2) >> 28);\r
- break;\r
- default:\r
- state = CANTXFAILED;\r
- break;\r
- }\r
- switch (state)\r
- {\r
- /* transmit pending */\r
- case (0x0): state = CANTXPENDING;\r
- break;\r
- /* transmit failed */\r
- case (0x5): state = CANTXFAILED;\r
- break;\r
- /* transmit succedeed */\r
- case (0x7): state = CANTXOK;\r
- break;\r
- default:\r
- state = CANTXFAILED;\r
- break;\r
- }\r
- return state;\r
-}\r
-\r
-/**\r
- * @brief Cancels a transmit request.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. \r
- * @param Mailbox: Mailbox number.\r
- * @retval None.\r
- */\r
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));\r
- /* abort transmission */\r
- switch (Mailbox)\r
- {\r
- case (0): CANx->TSR |= CAN_TSR_ABRQ0;\r
- break;\r
- case (1): CANx->TSR |= CAN_TSR_ABRQ1;\r
- break;\r
- case (2): CANx->TSR |= CAN_TSR_ABRQ2;\r
- break;\r
- default:\r
- break;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Releases a FIFO.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. \r
- * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.\r
- * @retval None.\r
- */\r
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_FIFO(FIFONumber));\r
- /* Release FIFO0 */\r
- if (FIFONumber == CAN_FIFO0)\r
- {\r
- CANx->RF0R |= CAN_RF0R_RFOM0;\r
- }\r
- /* Release FIFO1 */\r
- else /* FIFONumber == CAN_FIFO1 */\r
- {\r
- CANx->RF1R |= CAN_RF1R_RFOM1;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the number of pending messages.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
- * @retval NbMessage which is the number of pending message.\r
- */\r
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)\r
-{\r
- uint8_t message_pending=0;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_FIFO(FIFONumber));\r
- if (FIFONumber == CAN_FIFO0)\r
- {\r
- message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);\r
- }\r
- else if (FIFONumber == CAN_FIFO1)\r
- {\r
- message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);\r
- }\r
- else\r
- {\r
- message_pending = 0;\r
- }\r
- return message_pending;\r
-}\r
-\r
-/**\r
- * @brief Receives a message.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
- * @param RxMessage: pointer to a structure receive message which \r
- * contains CAN Id, CAN DLC, CAN datas and FMI number.\r
- * @retval None.\r
- */\r
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_FIFO(FIFONumber));\r
- /* Get the Id */\r
- RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;\r
- if (RxMessage->IDE == CAN_ID_STD)\r
- {\r
- RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);\r
- }\r
- else\r
- {\r
- RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);\r
- }\r
- \r
- RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;\r
- /* Get the DLC */\r
- RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;\r
- /* Get the FMI */\r
- RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
- /* Get the data field */\r
- RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;\r
- RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
- RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
- RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
- RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;\r
- RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
- RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
- RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
- /* Release the FIFO */\r
- CAN_FIFORelease(CANx, FIFONumber);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the DBG Freeze for CAN.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param NewState: new state of the CAN peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable Debug Freeze */\r
- CANx->MCR |= MCR_DBF;\r
- }\r
- else\r
- {\r
- /* Disable Debug Freeze */\r
- CANx->MCR &= ~MCR_DBF;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enters the low power mode.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.\r
- */\r
-uint8_t CAN_Sleep(CAN_TypeDef* CANx)\r
-{\r
- uint8_t sleepstatus = CANSLEEPFAILED;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- \r
- /* Request Sleep mode */\r
- CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);\r
- \r
- /* Sleep mode status */\r
- if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)\r
- {\r
- /* Sleep mode not entered */\r
- sleepstatus = CANSLEEPOK;\r
- }\r
- /* At this step, sleep mode status */\r
- return (uint8_t)sleepstatus;\r
-}\r
-\r
-/**\r
- * @brief Wakes the CAN up.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.\r
- */\r
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx)\r
-{\r
- uint32_t wait_slak = SLAK_TIMEOUT;\r
- uint8_t wakeupstatus = CANWAKEUPFAILED;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- \r
- /* Wake up request */\r
- CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;\r
- \r
- /* Sleep mode status */\r
- while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))\r
- {\r
- wait_slak--;\r
- }\r
- if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)\r
- {\r
- /* Sleep mode exited */\r
- wakeupstatus = CANWAKEUPOK;\r
- }\r
- /* At this step, sleep mode status */\r
- return (uint8_t)wakeupstatus;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified CAN flag is set or not.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following flags: \r
- * - CAN_FLAG_EWG\r
- * - CAN_FLAG_EPV \r
- * - CAN_FLAG_BOF\r
- * - CAN_FLAG_RQCP0\r
- * - CAN_FLAG_RQCP1\r
- * - CAN_FLAG_RQCP2\r
- * - CAN_FLAG_FMP1 \r
- * - CAN_FLAG_FF1 \r
- * - CAN_FLAG_FOV1 \r
- * - CAN_FLAG_FMP0 \r
- * - CAN_FLAG_FF0 \r
- * - CAN_FLAG_FOV0 \r
- * - CAN_FLAG_WKU \r
- * - CAN_FLAG_SLAK \r
- * - CAN_FLAG_LEC \r
- * @retval The new state of CAN_FLAG (SET or RESET).\r
- */\r
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_GET_FLAG(CAN_FLAG));\r
- \r
-\r
- if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)\r
- { \r
- /* Check the status of the specified CAN flag */\r
- if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
- { \r
- /* CAN_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- { \r
- /* CAN_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- }\r
- else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)\r
- { \r
- /* Check the status of the specified CAN flag */\r
- if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
- { \r
- /* CAN_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- { \r
- /* CAN_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- }\r
- else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)\r
- { \r
- /* Check the status of the specified CAN flag */\r
- if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
- { \r
- /* CAN_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- { \r
- /* CAN_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- }\r
- else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)\r
- { \r
- /* Check the status of the specified CAN flag */\r
- if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
- { \r
- /* CAN_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- { \r
- /* CAN_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- }\r
- else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */\r
- { \r
- /* Check the status of the specified CAN flag */\r
- if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
- { \r
- /* CAN_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- { \r
- /* CAN_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- }\r
- /* Return the CAN_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the CAN's pending flags.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_FLAG: specifies the flag to clear.\r
- * This parameter can be one of the following flags: \r
- * - CAN_FLAG_RQCP0\r
- * - CAN_FLAG_RQCP1\r
- * - CAN_FLAG_RQCP2\r
- * - CAN_FLAG_FF1 \r
- * - CAN_FLAG_FOV1 \r
- * - CAN_FLAG_FF0 \r
- * - CAN_FLAG_FOV0 \r
- * - CAN_FLAG_WKU \r
- * - CAN_FLAG_SLAK \r
- * - CAN_FLAG_LEC \r
- * @retval None.\r
- */\r
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r
-{\r
- uint32_t flagtmp=0;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));\r
- \r
- if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */\r
- {\r
- /* Clear the selected CAN flags */\r
- CANx->ESR = (uint32_t)RESET;\r
- }\r
- else /* MSR or TSR or RF0R or RF1R */\r
- {\r
- flagtmp = CAN_FLAG & 0x000FFFFF;\r
-\r
- if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)\r
- {\r
- /* Receive Flags */\r
- CANx->RF0R = (uint32_t)(flagtmp);\r
- }\r
- else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)\r
- {\r
- /* Receive Flags */\r
- CANx->RF1R = (uint32_t)(flagtmp);\r
- }\r
- else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)\r
- {\r
- /* Transmit Flags */\r
- CANx->TSR = (uint32_t)(flagtmp);\r
- }\r
- else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */\r
- {\r
- /* Operating mode Flags */\r
- CANx->MSR = (uint32_t)(flagtmp);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified CANx interrupt has occurred or not.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_IT: specifies the CAN interrupt source to check.\r
- * This parameter can be one of the following flags: \r
- * - CAN_IT_TME \r
- * - CAN_IT_FMP0 \r
- * - CAN_IT_FF0 \r
- * - CAN_IT_FOV0 \r
- * - CAN_IT_FMP1 \r
- * - CAN_IT_FF1 \r
- * - CAN_IT_FOV1 \r
- * - CAN_IT_WKU \r
- * - CAN_IT_SLK \r
- * - CAN_IT_EWG \r
- * - CAN_IT_EPV \r
- * - CAN_IT_BOF \r
- * - CAN_IT_LEC \r
- * - CAN_IT_ERR \r
- * @retval The current state of CAN_IT (SET or RESET).\r
- */\r
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)\r
-{\r
- ITStatus itstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_IT(CAN_IT));\r
- \r
- /* check the enable interrupt bit */\r
- if((CANx->IER & CAN_IT) != RESET)\r
- {\r
- /* in case the Interrupt is enabled, .... */\r
- switch (CAN_IT)\r
- {\r
- case CAN_IT_TME:\r
- /* Check CAN_TSR_RQCPx bits */\r
- itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); \r
- break;\r
- case CAN_IT_FMP0:\r
- /* Check CAN_RF0R_FMP0 bit */\r
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); \r
- break;\r
- case CAN_IT_FF0:\r
- /* Check CAN_RF0R_FULL0 bit */\r
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); \r
- break;\r
- case CAN_IT_FOV0:\r
- /* Check CAN_RF0R_FOVR0 bit */\r
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); \r
- break;\r
- case CAN_IT_FMP1:\r
- /* Check CAN_RF1R_FMP1 bit */\r
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); \r
- break;\r
- case CAN_IT_FF1:\r
- /* Check CAN_RF1R_FULL1 bit */\r
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); \r
- break;\r
- case CAN_IT_FOV1:\r
- /* Check CAN_RF1R_FOVR1 bit */\r
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); \r
- break;\r
- case CAN_IT_WKU:\r
- /* Check CAN_MSR_WKUI bit */\r
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); \r
- break;\r
- case CAN_IT_SLK:\r
- /* Check CAN_MSR_SLAKI bit */\r
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); \r
- break;\r
- case CAN_IT_EWG:\r
- /* Check CAN_ESR_EWGF bit */\r
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); \r
- break;\r
- case CAN_IT_EPV:\r
- /* Check CAN_ESR_EPVF bit */\r
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); \r
- break;\r
- case CAN_IT_BOF:\r
- /* Check CAN_ESR_BOFF bit */\r
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); \r
- break;\r
- case CAN_IT_LEC:\r
- /* Check CAN_ESR_LEC bit */\r
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); \r
- break;\r
- case CAN_IT_ERR:\r
- /* Check CAN_MSR_ERRI, CAN_ESR_EWGF, CAN_ESR_EPVF, CAN_ESR_BOFF and CAN_ESR_LEC bits */\r
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF|CAN_ESR_EPVF|CAN_ESR_BOFF|CAN_ESR_LEC); \r
- itstatus |= CheckITStatus(CANx->MSR, CAN_MSR_ERRI); \r
- break;\r
- default :\r
- /* in case of error, return RESET */\r
- itstatus = RESET;\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- /* in case the Interrupt is not enabled, return RESET */\r
- itstatus = RESET;\r
- }\r
- \r
- /* Return the CAN_IT status */\r
- return itstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the CANx\92s interrupt pending bits.\r
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
- * @param CAN_IT: specifies the interrupt pending bit to clear.\r
- * - CAN_IT_TME \r
- * - CAN_IT_FF0 \r
- * - CAN_IT_FOV0 \r
- * - CAN_IT_FF1 \r
- * - CAN_IT_FOV1 \r
- * - CAN_IT_WKU \r
- * - CAN_IT_SLK \r
- * - CAN_IT_EWG \r
- * - CAN_IT_EPV \r
- * - CAN_IT_BOF \r
- * - CAN_IT_LEC \r
- * - CAN_IT_ERR \r
- * @retval None.\r
- */\r
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CAN_ALL_PERIPH(CANx));\r
- assert_param(IS_CAN_CLEAR_IT(CAN_IT));\r
-\r
- switch (CAN_IT)\r
- {\r
- case CAN_IT_TME:\r
- /* Clear CAN_TSR_RQCPx (rc_w1)*/\r
- CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; \r
- break;\r
- case CAN_IT_FF0:\r
- /* Clear CAN_RF0R_FULL0 (rc_w1)*/\r
- CANx->RF0R = CAN_RF0R_FULL0; \r
- break;\r
- case CAN_IT_FOV0:\r
- /* Clear CAN_RF0R_FOVR0 (rc_w1)*/\r
- CANx->RF0R = CAN_RF0R_FOVR0; \r
- break;\r
- case CAN_IT_FF1:\r
- /* Clear CAN_RF1R_FULL1 (rc_w1)*/\r
- CANx->RF1R = CAN_RF1R_FULL1; \r
- break;\r
- case CAN_IT_FOV1:\r
- /* Clear CAN_RF1R_FOVR1 (rc_w1)*/\r
- CANx->RF1R = CAN_RF1R_FOVR1; \r
- break;\r
- case CAN_IT_WKU:\r
- /* Clear CAN_MSR_WKUI (rc_w1)*/\r
- CANx->MSR = CAN_MSR_WKUI; \r
- break;\r
- case CAN_IT_SLK:\r
- /* Clear CAN_MSR_SLAKI (rc_w1)*/ \r
- CANx->MSR = CAN_MSR_SLAKI; \r
- break;\r
- case CAN_IT_EWG:\r
- /* Clear CAN_MSR_ERRI (rc_w1) */\r
- CANx->MSR = CAN_MSR_ERRI;\r
- /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/ \r
- break;\r
- case CAN_IT_EPV:\r
- /* Clear CAN_MSR_ERRI (rc_w1) */\r
- CANx->MSR = CAN_MSR_ERRI; \r
- /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/\r
- break;\r
- case CAN_IT_BOF:\r
- /* Clear CAN_MSR_ERRI (rc_w1) */ \r
- CANx->MSR = CAN_MSR_ERRI; \r
- /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/\r
- break;\r
- case CAN_IT_LEC:\r
- /* Clear LEC bits */\r
- CANx->ESR = RESET; \r
- /* Clear CAN_MSR_ERRI (rc_w1) */\r
- CANx->MSR = CAN_MSR_ERRI; \r
- break;\r
- case CAN_IT_ERR:\r
- /*Clear LEC bits */\r
- CANx->ESR = RESET; \r
- /* Clear CAN_MSR_ERRI (rc_w1) */\r
- CANx->MSR = CAN_MSR_ERRI; \r
- /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending of the CAN Bus status*/\r
- break;\r
- default :\r
- break;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the CAN interrupt has occurred or not.\r
- * @param CAN_Reg: specifies the CAN interrupt register to check.\r
- * @param It_Bit: specifies the interrupt source bit to check.\r
- * @retval The new state of the CAN Interrupt (SET or RESET).\r
- */\r
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)\r
-{\r
- ITStatus pendingbitstatus = RESET;\r
- \r
- if ((CAN_Reg & It_Bit) != (uint32_t)RESET)\r
- {\r
- /* CAN_IT is set */\r
- pendingbitstatus = SET;\r
- }\r
- else\r
- {\r
- /* CAN_IT is reset */\r
- pendingbitstatus = RESET;\r
- }\r
- return pendingbitstatus;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_cec.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the CEC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_cec.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup CEC \r
- * @brief CEC driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup CEC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @defgroup CEC_Private_Defines\r
- * @{\r
- */ \r
-\r
-/* ------------ CEC registers bit address in the alias region ----------- */\r
-#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)\r
-\r
-/* --- CFGR Register ---*/\r
-\r
-/* Alias word address of PE bit */\r
-#define CFGR_OFFSET (CEC_OFFSET + 0x00)\r
-#define PE_BitNumber 0x00\r
-#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))\r
-\r
-/* Alias word address of IE bit */\r
-#define IE_BitNumber 0x01\r
-#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))\r
-\r
-/* --- CSR Register ---*/\r
-\r
-/* Alias word address of TSOM bit */\r
-#define CSR_OFFSET (CEC_OFFSET + 0x10)\r
-#define TSOM_BitNumber 0x00\r
-#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))\r
-\r
-/* Alias word address of TEOM bit */\r
-#define TEOM_BitNumber 0x01\r
-#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))\r
- \r
-#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */\r
-#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_Private_Macros\r
- * @{\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_Private_Variables\r
- * @{\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_Private_FunctionPrototypes\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup CEC_Private_Functions\r
- * @{\r
- */ \r
-\r
-/**\r
- * @brief Deinitializes the CEC peripheral registers to their default reset \r
- * values.\r
- * @param None\r
- * @retval None\r
- */\r
-void CEC_DeInit(void)\r
-{\r
- /* Enable CEC reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); \r
- /* Release CEC from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); \r
-}\r
-\r
-\r
-/**\r
- * @brief Initializes the CEC peripheral according to the specified \r
- * parameters in the CEC_InitStruct.\r
- * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that\r
- * contains the configuration information for the specified\r
- * CEC peripheral.\r
- * @retval None\r
- */\r
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)\r
-{\r
- uint16_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); \r
- assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));\r
- \r
- /*---------------------------- CEC CFGR Configuration -----------------*/\r
- /* Get the CEC CFGR value */\r
- tmpreg = CEC->CFGR;\r
- \r
- /* Clear BTEM and BPEM bits */\r
- tmpreg &= CFGR_CLEAR_Mask;\r
- \r
- /* Configure CEC: Bit Timing Error and Bit Period Error */\r
- tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);\r
-\r
- /* Write to CEC CFGR register*/\r
- CEC->CFGR = tmpreg;\r
- \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified CEC peripheral.\r
- * @param NewState: new state of the CEC peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void CEC_Cmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;\r
-\r
- if(NewState == DISABLE)\r
- {\r
- /* Wait until the PE bit is cleared by hardware (Idle Line detected) */\r
- while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)\r
- {\r
- } \r
- } \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the CEC interrupt.\r
- * @param NewState: new state of the CEC interrupt.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void CEC_ITConfig(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Defines the Own Address of the CEC device.\r
- * @param CEC_OwnAddress: The CEC own address\r
- * @retval None\r
- */\r
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));\r
-\r
- /* Set the CEC own address */\r
- CEC->OAR = CEC_OwnAddress;\r
-}\r
-\r
-/**\r
- * @brief Sets the CEC prescaler value.\r
- * @param CEC_Prescaler: CEC prescaler new value\r
- * @retval None\r
- */\r
-void CEC_SetPrescaler(uint16_t CEC_Prescaler)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_CEC_PRESCALER(CEC_Prescaler));\r
-\r
- /* Set the Prescaler value*/\r
- CEC->PRES = CEC_Prescaler;\r
-}\r
-\r
-/**\r
- * @brief Transmits single data through the CEC peripheral.\r
- * @param Data: the data to transmit.\r
- * @retval None\r
- */\r
-void CEC_SendDataByte(uint8_t Data)\r
-{ \r
- /* Transmit Data */\r
- CEC->TXD = Data ;\r
-}\r
-\r
-\r
-/**\r
- * @brief Returns the most recent received data by the CEC peripheral.\r
- * @param None\r
- * @retval The received data.\r
- */\r
-uint8_t CEC_ReceiveDataByte(void)\r
-{\r
- /* Receive Data */\r
- return (uint8_t)(CEC->RXD);\r
-}\r
-\r
-/**\r
- * @brief Starts a new message.\r
- * @param None\r
- * @retval None\r
- */\r
-void CEC_StartOfMessage(void)\r
-{ \r
- /* Starts of new message */\r
- *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;\r
-}\r
-\r
-/**\r
- * @brief Transmits message with or without an EOM bit.\r
- * @param NewState: new state of the CEC Tx End Of Message. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void CEC_EndOfMessageCmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- /* The data byte will be transmitted with or without an EOM bit*/\r
- *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Gets the CEC flag status\r
- * @param CEC_FLAG: specifies the CEC flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg CEC_FLAG_BTE: Bit Timing Error\r
- * @arg CEC_FLAG_BPE: Bit Period Error\r
- * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error\r
- * @arg CEC_FLAG_SBE: Start Bit Error\r
- * @arg CEC_FLAG_ACKE: Block Acknowledge Error\r
- * @arg CEC_FLAG_LINE: Line Error\r
- * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error\r
- * @arg CEC_FLAG_TEOM: Tx End Of Message \r
- * @arg CEC_FLAG_TERR: Tx Error\r
- * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished\r
- * @arg CEC_FLAG_RSOM: Rx Start Of Message\r
- * @arg CEC_FLAG_REOM: Rx End Of Message\r
- * @arg CEC_FLAG_RERR: Rx Error\r
- * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished\r
- * @retval The new state of CEC_FLAG (SET or RESET)\r
- */\r
-FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) \r
-{\r
- FlagStatus bitstatus = RESET;\r
- uint32_t cecreg = 0, cecbase = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CEC_GET_FLAG(CEC_FLAG));\r
- \r
- /* Get the CEC peripheral base address */\r
- cecbase = (uint32_t)(CEC_BASE);\r
- \r
- /* Read flag register index */\r
- cecreg = CEC_FLAG >> 28;\r
- \r
- /* Get bit[23:0] of the flag */\r
- CEC_FLAG &= FLAG_Mask;\r
- \r
- if(cecreg != 0)\r
- {\r
- /* Flag in CEC ESR Register */\r
- CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);\r
- \r
- /* Get the CEC ESR register address */\r
- cecbase += 0xC;\r
- }\r
- else\r
- {\r
- /* Get the CEC CSR register address */\r
- cecbase += 0x10;\r
- }\r
- \r
- if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)\r
- {\r
- /* CEC_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* CEC_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the CEC_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the CEC's pending flags.\r
- * @param CEC_FLAG: specifies the flag to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg CEC_FLAG_TERR: Tx Error\r
- * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished\r
- * @arg CEC_FLAG_RSOM: Rx Start Of Message\r
- * @arg CEC_FLAG_REOM: Rx End Of Message\r
- * @arg CEC_FLAG_RERR: Rx Error\r
- * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished\r
- * @retval None\r
- */\r
-void CEC_ClearFlag(uint32_t CEC_FLAG)\r
-{ \r
- uint32_t tmp = 0x0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));\r
-\r
- tmp = CEC->CSR & 0x2;\r
- \r
- /* Clear the selected CEC flags */\r
- CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified CEC interrupt has occurred or not.\r
- * @param CEC_IT: specifies the CEC interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg CEC_IT_TERR: Tx Error\r
- * @arg CEC_IT_TBTF: Tx Block Transfer Finished\r
- * @arg CEC_IT_RERR: Rx Error\r
- * @arg CEC_IT_RBTF: Rx Block Transfer Finished\r
- * @retval The new state of CEC_IT (SET or RESET).\r
- */\r
-ITStatus CEC_GetITStatus(uint8_t CEC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CEC_GET_IT(CEC_IT));\r
- \r
- /* Get the CEC IT enable bit status */\r
- enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;\r
- \r
- /* Check the status of the specified CEC interrupt */\r
- if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* CEC_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* CEC_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the CEC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the CEC's interrupt pending bits.\r
- * @param CEC_IT: specifies the CEC interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg CEC_IT_TERR: Tx Error\r
- * @arg CEC_IT_TBTF: Tx Block Transfer Finished\r
- * @arg CEC_IT_RERR: Rx Error\r
- * @arg CEC_IT_RBTF: Rx Block Transfer Finished\r
- * @retval None\r
- */\r
-void CEC_ClearITPendingBit(uint16_t CEC_IT)\r
-{\r
- uint32_t tmp = 0x0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_CEC_GET_IT(CEC_IT));\r
- \r
- tmp = CEC->CSR & 0x2;\r
- \r
- /* Clear the selected CEC interrupt pending bits */\r
- CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);\r
-}\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_crc.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the CRC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_crc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup CRC \r
- * @brief CRC driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup CRC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Private_Defines\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup CRC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Resets the CRC Data register (DR).\r
- * @param None\r
- * @retval None\r
- */\r
-void CRC_ResetDR(void)\r
-{\r
- /* Reset CRC generator */\r
- CRC->CR = CRC_CR_RESET;\r
-}\r
-\r
-/**\r
- * @brief Computes the 32-bit CRC of a given data word(32-bit).\r
- * @param Data: data word(32-bit) to compute its CRC\r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_CalcCRC(uint32_t Data)\r
-{\r
- CRC->DR = Data;\r
- \r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r
- * @param pBuffer: pointer to the buffer containing the data to be computed\r
- * @param BufferLength: length of the buffer to be computed \r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r
-{\r
- uint32_t index = 0;\r
- \r
- for(index = 0; index < BufferLength; index++)\r
- {\r
- CRC->DR = pBuffer[index];\r
- }\r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Returns the current CRC value.\r
- * @param None\r
- * @retval 32-bit CRC\r
- */\r
-uint32_t CRC_GetCRC(void)\r
-{\r
- return (CRC->DR);\r
-}\r
-\r
-/**\r
- * @brief Stores a 8-bit data in the Independent Data(ID) register.\r
- * @param IDValue: 8-bit value to be stored in the ID register \r
- * @retval None\r
- */\r
-void CRC_SetIDRegister(uint8_t IDValue)\r
-{\r
- CRC->IDR = IDValue;\r
-}\r
-\r
-/**\r
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register\r
- * @param None\r
- * @retval 8-bit value of the ID register \r
- */\r
-uint8_t CRC_GetIDRegister(void)\r
-{\r
- return (CRC->IDR);\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dac.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the DAC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_dac.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DAC \r
- * @brief DAC driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup DAC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Private_Defines\r
- * @{\r
- */\r
-\r
-/* CR register Mask */\r
-#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)\r
-\r
-/* DAC Dual Channels SWTRIG masks */\r
-#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)\r
-#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)\r
-\r
-/* DHR registers offsets */\r
-#define DHR12R1_OFFSET ((uint32_t)0x00000008)\r
-#define DHR12R2_OFFSET ((uint32_t)0x00000014)\r
-#define DHR12RD_OFFSET ((uint32_t)0x00000020)\r
-\r
-/* DOR register offset */\r
-#define DOR_OFFSET ((uint32_t)0x0000002C)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DAC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void DAC_DeInit(void)\r
-{\r
- /* Enable DAC reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
- /* Release DAC from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Initializes the DAC peripheral according to the specified \r
- * parameters in the DAC_InitStruct.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
- * contains the configuration information for the specified DAC channel.\r
- * @retval None\r
- */\r
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
-{\r
- uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
- /* Check the DAC parameters */\r
- assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
- assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
-/*---------------------------- DAC CR Configuration --------------------------*/\r
- /* Get the DAC CR value */\r
- tmpreg1 = DAC->CR;\r
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
- tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);\r
- /* Configure for the selected DAC channel: buffer output, trigger, wave genration,\r
- mask/amplitude for wave genration */\r
- /* Set TSELx and TENx bits according to DAC_Trigger value */\r
- /* Set WAVEx bits according to DAC_WaveGeneration value */\r
- /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r
- /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
- tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);\r
- /* Calculate CR register value depending on DAC_Channel */\r
- tmpreg1 |= tmpreg2 << DAC_Channel;\r
- /* Write to DAC CR */\r
- DAC->CR = tmpreg1;\r
-}\r
-\r
-/**\r
- * @brief Fills each DAC_InitStruct member with its default value.\r
- * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
-{\r
-/*--------------- Reset DAC init structure parameters values -----------------*/\r
- /* Initialize the DAC_Trigger member */\r
- DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
- /* Initialize the DAC_WaveGeneration member */\r
- DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r
- /* Initialize the DAC_OutputBuffer member */\r
- DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified DAC channel.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the DAC channel. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC channel */\r
- DAC->CR |= (DAC_CR_EN1 << DAC_Channel);\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC channel */\r
- DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);\r
- }\r
-}\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
-/**\r
- * @brief Enables or disables the specified DAC interrupts.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r
- * This parameter can be the following values:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
- * @param NewState: new state of the specified DAC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */ \r
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_DAC_IT(DAC_IT)); \r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC interrupts */\r
- DAC->CR |= (DAC_IT << DAC_Channel);\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC interrupts */\r
- DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r
- }\r
-}\r
-#endif\r
-\r
-/**\r
- * @brief Enables or disables the specified DAC channel DMA request.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the selected DAC channel DMA request.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DAC channel DMA request */\r
- DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);\r
- }\r
- else\r
- {\r
- /* Disable the selected DAC channel DMA request */\r
- DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected DAC channel software trigger.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param NewState: new state of the selected DAC channel software trigger.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable software trigger for the selected DAC channel */\r
- DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);\r
- }\r
- else\r
- {\r
- /* Disable software trigger for the selected DAC channel */\r
- DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables simultaneously the two DAC channels software\r
- * triggers.\r
- * @param NewState: new state of the DAC channels software triggers.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable software trigger for both DAC channels */\r
- DAC->SWTRIGR |= DUAL_SWTRIG_SET ;\r
- }\r
- else\r
- {\r
- /* Disable software trigger for both DAC channels */\r
- DAC->SWTRIGR &= DUAL_SWTRIG_RESET;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the selected DAC channel wave generation.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_Wave: Specifies the wave type to enable or disable.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Wave_Noise: noise wave generation\r
- * @arg DAC_Wave_Triangle: triangle wave generation\r
- * @param NewState: new state of the selected DAC channel wave generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_WAVE(DAC_Wave)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected wave generation for the selected DAC channel */\r
- DAC->CR |= DAC_Wave << DAC_Channel;\r
- }\r
- else\r
- {\r
- /* Disable the selected wave generation for the selected DAC channel */\r
- DAC->CR &= ~(DAC_Wave << DAC_Channel);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for DAC channel1.\r
- * @param DAC_Align: Specifies the data alignement for DAC channel1.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
- * @param Data : Data to be loaded in the selected data holding register.\r
- * @retval None\r
- */\r
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
-{ \r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data));\r
- \r
- tmp = (uint32_t)DAC_BASE; \r
- tmp += DHR12R1_OFFSET + DAC_Align;\r
-\r
- /* Set the DAC channel1 selected data holding register */\r
- *(__IO uint32_t *) tmp = Data;\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for DAC channel2.\r
- * @param DAC_Align: Specifies the data alignement for DAC channel2.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
- * @param Data : Data to be loaded in the selected data holding register.\r
- * @retval None\r
- */\r
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data));\r
- \r
- tmp = (uint32_t)DAC_BASE;\r
- tmp += DHR12R2_OFFSET + DAC_Align;\r
-\r
- /* Set the DAC channel2 selected data holding register */\r
- *(__IO uint32_t *)tmp = Data;\r
-}\r
-\r
-/**\r
- * @brief Set the specified data holding register value for dual channel\r
- * DAC.\r
- * @param DAC_Align: Specifies the data alignement for dual channel DAC.\r
- * This parameter can be one of the following values:\r
- * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
- * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
- * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
- * @param Data2: Data for DAC Channel2 to be loaded in the selected data \r
- * holding register.\r
- * @param Data1: Data for DAC Channel1 to be loaded in the selected data \r
- * holding register.\r
- * @retval None\r
- */\r
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r
-{\r
- uint32_t data = 0, tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_ALIGN(DAC_Align));\r
- assert_param(IS_DAC_DATA(Data1));\r
- assert_param(IS_DAC_DATA(Data2));\r
- \r
- /* Calculate and set dual DAC data holding register value */\r
- if (DAC_Align == DAC_Align_8b_R)\r
- {\r
- data = ((uint32_t)Data2 << 8) | Data1; \r
- }\r
- else\r
- {\r
- data = ((uint32_t)Data2 << 16) | Data1;\r
- }\r
- \r
- tmp = (uint32_t)DAC_BASE;\r
- tmp += DHR12RD_OFFSET + DAC_Align;\r
-\r
- /* Set the dual DAC selected data holding register */\r
- *(__IO uint32_t *)tmp = data;\r
-}\r
-\r
-/**\r
- * @brief Returns the last data output value of the selected DAC cahnnel.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @retval The selected DAC channel data output value.\r
- */\r
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
-{\r
- __IO uint32_t tmp = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- \r
- tmp = (uint32_t) DAC_BASE ;\r
- tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);\r
- \r
- /* Returns the DAC channel data output register value */\r
- return (uint16_t) (*(__IO uint32_t*) tmp);\r
-}\r
-\r
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
-/**\r
- * @brief Checks whether the specified DAC flag is set or not.\r
- * @param DAC_Channel: thee selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_FLAG: specifies the flag to check. \r
- * This parameter can be only of the following value:\r
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
- * @retval The new state of DAC_FLAG (SET or RESET).\r
- */\r
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_FLAG(DAC_FLAG));\r
-\r
- /* Check the status of the specified DAC flag */\r
- if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r
- {\r
- /* DAC_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DAC_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DAC_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DAC channelx's pending flags.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_FLAG: specifies the flag to clear. \r
- * This parameter can be of the following value:\r
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
- * @retval None\r
- */\r
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_FLAG(DAC_FLAG));\r
-\r
- /* Clear the selected DAC flags */\r
- DAC->SR = (DAC_FLAG << DAC_Channel);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DAC interrupt has occurred or not.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt source to check. \r
- * This parameter can be the following values:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
- * @retval The new state of DAC_IT (SET or RESET).\r
- */\r
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_IT(DAC_IT));\r
-\r
- /* Get the DAC_IT enable bit status */\r
- enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r
- \r
- /* Check the status of the specified DAC interrupt */\r
- if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* DAC_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DAC_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DAC_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DAC channelx\92s interrupt pending bits.\r
- * @param DAC_Channel: the selected DAC channel. \r
- * This parameter can be one of the following values:\r
- * @arg DAC_Channel_1: DAC Channel1 selected\r
- * @arg DAC_Channel_2: DAC Channel2 selected\r
- * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r
- * This parameter can be the following values:\r
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
- * @retval None\r
- */\r
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
- assert_param(IS_DAC_IT(DAC_IT)); \r
-\r
- /* Clear the selected DAC interrupt pending bits */\r
- DAC->SR = (DAC_IT << DAC_Channel);\r
-}\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dbgmcu.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the DBGMCU firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_dbgmcu.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DBGMCU \r
- * @brief DBGMCU driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup DBGMCU_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Private_Defines\r
- * @{\r
- */\r
-\r
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DBGMCU_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Returns the device revision identifier.\r
- * @param None\r
- * @retval Device revision identifier\r
- */\r
-uint32_t DBGMCU_GetREVID(void)\r
-{\r
- return(DBGMCU->IDCODE >> 16);\r
-}\r
-\r
-/**\r
- * @brief Returns the device identifier.\r
- * @param None\r
- * @retval Device identifier\r
- */\r
-uint32_t DBGMCU_GetDEVID(void)\r
-{\r
- return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);\r
-}\r
-\r
-/**\r
- * @brief Configures the specified peripheral and low power mode behavior\r
- * when the MCU under Debug mode.\r
- * @param DBGMCU_Periph: specifies the peripheral and low power mode.\r
- * This parameter can be any combination of the following values:\r
- * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode \r
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode \r
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode \r
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted \r
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted \r
- * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted \r
- * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted \r
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted\r
- * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted\r
- * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted\r
- * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted \r
- * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted \r
- * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted\r
- * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted\r
- * @param NewState: new state of the specified peripheral in Debug mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- DBGMCU->CR |= DBGMCU_Periph;\r
- }\r
- else\r
- {\r
- DBGMCU->CR &= ~DBGMCU_Periph;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_dma.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the DMA firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_dma.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup DMA \r
- * @brief DMA driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup DMA_Private_TypesDefinitions\r
- * @{\r
- */ \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Private_Defines\r
- * @{\r
- */\r
-\r
-\r
-/* DMA1 Channelx interrupt pending bit masks */\r
-#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
-#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
-#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
-#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
-#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
-#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))\r
-#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))\r
-\r
-/* DMA2 Channelx interrupt pending bit masks */\r
-#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
-#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
-#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
-#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
-#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
-\r
-/* DMA2 FLAG mask */\r
-#define FLAG_Mask ((uint32_t)0x10000000)\r
-\r
-/* DMA registers Masks */\r
-#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup DMA_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the DMAy Channelx registers to their default reset\r
- * values.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and\r
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @retval None\r
- */\r
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- \r
- /* Disable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
- \r
- /* Reset DMAy Channelx control register */\r
- DMAy_Channelx->CCR = 0;\r
- \r
- /* Reset DMAy Channelx remaining bytes register */\r
- DMAy_Channelx->CNDTR = 0;\r
- \r
- /* Reset DMAy Channelx peripheral address register */\r
- DMAy_Channelx->CPAR = 0;\r
- \r
- /* Reset DMAy Channelx memory address register */\r
- DMAy_Channelx->CMAR = 0;\r
- \r
- if (DMAy_Channelx == DMA1_Channel1)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel1 */\r
- DMA1->IFCR |= DMA1_Channel1_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel2)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel2 */\r
- DMA1->IFCR |= DMA1_Channel2_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel3)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel3 */\r
- DMA1->IFCR |= DMA1_Channel3_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel4)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel4 */\r
- DMA1->IFCR |= DMA1_Channel4_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel5)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel5 */\r
- DMA1->IFCR |= DMA1_Channel5_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel6)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel6 */\r
- DMA1->IFCR |= DMA1_Channel6_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA1_Channel7)\r
- {\r
- /* Reset interrupt pending bits for DMA1 Channel7 */\r
- DMA1->IFCR |= DMA1_Channel7_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel1)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel1 */\r
- DMA2->IFCR |= DMA2_Channel1_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel2)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel2 */\r
- DMA2->IFCR |= DMA2_Channel2_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel3)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel3 */\r
- DMA2->IFCR |= DMA2_Channel3_IT_Mask;\r
- }\r
- else if (DMAy_Channelx == DMA2_Channel4)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel4 */\r
- DMA2->IFCR |= DMA2_Channel4_IT_Mask;\r
- }\r
- else\r
- { \r
- if (DMAy_Channelx == DMA2_Channel5)\r
- {\r
- /* Reset interrupt pending bits for DMA2 Channel5 */\r
- DMA2->IFCR |= DMA2_Channel5_IT_Mask;\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the DMAy Channelx according to the specified\r
- * parameters in the DMA_InitStruct.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
- * contains the configuration information for the specified DMA Channel.\r
- * @retval None\r
- */\r
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
- assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
-\r
-/*--------------------------- DMAy Channelx CCR Configuration -----------------*/\r
- /* Get the DMAy_Channelx CCR value */\r
- tmpreg = DMAy_Channelx->CCR;\r
- /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
- tmpreg &= CCR_CLEAR_Mask;\r
- /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
- /* Set DIR bit according to DMA_DIR value */\r
- /* Set CIRC bit according to DMA_Mode value */\r
- /* Set PINC bit according to DMA_PeripheralInc value */\r
- /* Set MINC bit according to DMA_MemoryInc value */\r
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
- /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
- /* Set PL bits according to DMA_Priority value */\r
- /* Set the MEM2MEM bit according to DMA_M2M value */\r
- tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
- DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
-\r
- /* Write to DMAy Channelx CCR */\r
- DMAy_Channelx->CCR = tmpreg;\r
-\r
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
- /* Write to DMAy Channelx CNDTR */\r
- DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
-\r
-/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/\r
- /* Write to DMAy Channelx CPAR */\r
- DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
-\r
-/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/\r
- /* Write to DMAy Channelx CMAR */\r
- DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
-}\r
-\r
-/**\r
- * @brief Fills each DMA_InitStruct member with its default value.\r
- * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
-{\r
-/*-------------- Reset DMA init structure parameters values ------------------*/\r
- /* Initialize the DMA_PeripheralBaseAddr member */\r
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
- /* Initialize the DMA_MemoryBaseAddr member */\r
- DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
- /* Initialize the DMA_DIR member */\r
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
- /* Initialize the DMA_BufferSize member */\r
- DMA_InitStruct->DMA_BufferSize = 0;\r
- /* Initialize the DMA_PeripheralInc member */\r
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
- /* Initialize the DMA_MemoryInc member */\r
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
- /* Initialize the DMA_PeripheralDataSize member */\r
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
- /* Initialize the DMA_MemoryDataSize member */\r
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
- /* Initialize the DMA_Mode member */\r
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
- /* Initialize the DMA_Priority member */\r
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
- /* Initialize the DMA_M2M member */\r
- DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified DMAy Channelx.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @param NewState: new state of the DMAy Channelx. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR |= DMA_CCR1_EN;\r
- }\r
- else\r
- {\r
- /* Disable the selected DMAy Channelx */\r
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified DMAy Channelx interrupts.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
- * or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg DMA_IT_TC: Transfer complete interrupt mask\r
- * @arg DMA_IT_HT: Half transfer interrupt mask\r
- * @arg DMA_IT_TE: Transfer error interrupt mask\r
- * @param NewState: new state of the specified DMA interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected DMA interrupts */\r
- DMAy_Channelx->CCR |= DMA_IT;\r
- }\r
- else\r
- {\r
- /* Disable the selected DMA interrupts */\r
- DMAy_Channelx->CCR &= ~DMA_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the number of data units in the current DMAy Channelx transfer.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @param DataNumber: The number of data units in the current DMAy Channelx\r
- * transfer. \r
- * @note This function can only be used when the DMAy_Channelx is disabled. \r
- * @retval None.\r
- */\r
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- \r
-/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
- /* Write to DMAy Channelx CNDTR */\r
- DMAy_Channelx->CNDTR = DataNumber; \r
-}\r
-\r
-/**\r
- * @brief Returns the number of remaining data units in the current\r
- * DMAy Channelx transfer.\r
- * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
- * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
- * @retval The number of remaining data units in the current DMAy Channelx\r
- * transfer.\r
- */\r
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
- /* Return the number of remaining data units for DMAy Channelx */\r
- return ((uint16_t)(DMAy_Channelx->CNDTR));\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
- * @param DMA_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
- * @retval The new state of DMA_FLAG (SET or RESET).\r
- */\r
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)\r
- {\r
- /* Get DMA2 ISR register value */\r
- tmpreg = DMA2->ISR ;\r
- }\r
- else\r
- {\r
- /* Get DMA1 ISR register value */\r
- tmpreg = DMA1->ISR ;\r
- }\r
-\r
- /* Check the status of the specified DMA flag */\r
- if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)\r
- {\r
- /* DMA_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DMA_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the DMA_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DMAy Channelx's pending flags.\r
- * @param DMA_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination (for the same DMA) of the following values:\r
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
- * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
- * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
- * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
- * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
- * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
- * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
- * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
- * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
- * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
- * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
- * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
- * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
- * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
- * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
- * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
- * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
- * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
- * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
- * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
- * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
- * @retval None\r
- */\r
-void DMA_ClearFlag(uint32_t DMA_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r
- /* Calculate the used DMA */\r
-\r
- if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)\r
- {\r
- /* Clear the selected DMA flags */\r
- DMA2->IFCR = DMA_FLAG;\r
- }\r
- else\r
- {\r
- /* Clear the selected DMA flags */\r
- DMA1->IFCR = DMA_FLAG;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
- * @param DMA_IT: specifies the DMA interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
- * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
- * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
- * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
- * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
- * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
- * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
- * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
- * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
- * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
- * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
- * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
- * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
- * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
- * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
- * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
- * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
- * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
- * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
- * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
- * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.\r
- * @retval The new state of DMA_IT (SET or RESET).\r
- */\r
-ITStatus DMA_GetITStatus(uint32_t DMA_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_DMA_GET_IT(DMA_IT));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)\r
- {\r
- /* Get DMA2 ISR register value */\r
- tmpreg = DMA2->ISR ;\r
- }\r
- else\r
- {\r
- /* Get DMA1 ISR register value */\r
- tmpreg = DMA1->ISR ;\r
- }\r
-\r
- /* Check the status of the specified DMA interrupt */\r
- if ((tmpreg & DMA_IT) != (uint32_t)RESET)\r
- {\r
- /* DMA_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* DMA_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the DMA_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the DMAy Channelx\92s interrupt pending bits.\r
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.\r
- * This parameter can be any combination (for the same DMA) of the following values:\r
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
- * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
- * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
- * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
- * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
- * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
- * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
- * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
- * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
- * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
- * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
- * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
- * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
- * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
- * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
- * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
- * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
- * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
- * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
- * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
- * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.\r
- * @retval None\r
- */\r
-void DMA_ClearITPendingBit(uint32_t DMA_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));\r
-\r
- /* Calculate the used DMA */\r
- if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)\r
- {\r
- /* Clear the selected DMA interrupt pending bits */\r
- DMA2->IFCR = DMA_IT;\r
- }\r
- else\r
- {\r
- /* Clear the selected DMA interrupt pending bits */\r
- DMA1->IFCR = DMA_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_flash.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the FLASH firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_flash.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup FLASH \r
- * @brief FLASH driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup FLASH_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Private_Defines\r
- * @{\r
- */ \r
-\r
-/* Flash Access Control Register bits */\r
-#define ACR_LATENCY_Mask ((uint32_t)0x00000038)\r
-#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)\r
-#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)\r
-\r
-/* Flash Access Control Register bits */\r
-#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) \r
-\r
-/* Flash Control Register bits */\r
-#define CR_PG_Set ((uint32_t)0x00000001)\r
-#define CR_PG_Reset ((uint32_t)0x00001FFE) \r
-#define CR_PER_Set ((uint32_t)0x00000002)\r
-#define CR_PER_Reset ((uint32_t)0x00001FFD)\r
-#define CR_MER_Set ((uint32_t)0x00000004)\r
-#define CR_MER_Reset ((uint32_t)0x00001FFB)\r
-#define CR_OPTPG_Set ((uint32_t)0x00000010)\r
-#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)\r
-#define CR_OPTER_Set ((uint32_t)0x00000020)\r
-#define CR_OPTER_Reset ((uint32_t)0x00001FDF)\r
-#define CR_STRT_Set ((uint32_t)0x00000040)\r
-#define CR_LOCK_Set ((uint32_t)0x00000080)\r
-\r
-/* FLASH Mask */\r
-#define RDPRT_Mask ((uint32_t)0x00000002)\r
-#define WRP0_Mask ((uint32_t)0x000000FF)\r
-#define WRP1_Mask ((uint32_t)0x0000FF00)\r
-#define WRP2_Mask ((uint32_t)0x00FF0000)\r
-#define WRP3_Mask ((uint32_t)0xFF000000)\r
-#define OB_USER_BFB2 ((uint16_t)0x0008)\r
-\r
-/* FLASH Keys */\r
-#define RDP_Key ((uint16_t)0x00A5)\r
-#define FLASH_KEY1 ((uint32_t)0x45670123)\r
-#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)\r
-\r
-/* FLASH BANK address */\r
-#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)\r
-\r
-/* Delay definition */ \r
-#define EraseTimeout ((uint32_t)0x000B0000)\r
-#define ProgramTimeout ((uint32_t)0x00002000)\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup FLASH_Private_FunctionPrototypes\r
- * @{\r
- */\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FLASH_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
-@code \r
- \r
- This driver provides functions to configure and program the Flash memory of all STM32F10x devices,\r
- including the latest STM32F10x_XL density devices. \r
-\r
- STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:\r
- - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)\r
- - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)\r
- While other STM32F10x devices features only one bank with memory up to 512 Kbytes.\r
-\r
- In version V3.3.0, some functions were updated and new ones were added to support\r
- STM32F10x_XL devices. Thus some functions manages all devices, while other are \r
- dedicated for XL devices only.\r
- \r
- The table below presents the list of available functions depending on the used STM32F10x devices. \r
- \r
- ***************************************************\r
- * Legacy functions used for all STM32F10x devices *\r
- ***************************************************\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
- | | devices | devices | |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_SetLatency | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_HalfCycleAccessCmd | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_PrefetchBufferCmd | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. |\r
- | | | | - For other devices: unlock Bank1 and it is equivalent |\r
- | | | | to FLASH_UnlockBank1 function. |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. |\r
- | | | | - For other devices: lock Bank1 and it is equivalent |\r
- | | | | to FLASH_LockBank1 function. |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 |\r
- | | | | - For other devices: erase a page in Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |\r
- | | | | - For other devices: erase all pages in Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_EraseOptionBytes | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ProgramOptionByteData | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_EnableWriteProtection | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ReadOutProtection | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_UserOptionByteConfig | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetUserOptionByte | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|\r
- | | | | - For other devices: enable Bank1's interrupts |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|\r
- | | | | - For other devices: return Bank1's flag status |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag |\r
- | | | | - For other devices: clear Bank1's flag |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) |\r
- | | | | equivalent to FLASH_GetBank1Status function |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) |\r
- | | | | equivalent to: FLASH_WaitForLastBank1Operation function |\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
-\r
- ************************************************************************************************************************\r
- * New functions used for all STM32F10x devices to manage Bank1: *\r
- * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *\r
- * - For other devices, these functions are optional (covered by functions listed above) *\r
- ************************************************************************************************************************\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
- | | devices | devices | |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation |\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
-\r
- *****************************************************************************\r
- * New Functions used only with STM32F10x_XL density devices to manage Bank2 *\r
- *****************************************************************************\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
- | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
- | | devices | devices | |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- |FLASH_LockBank2 | Yes | No | - Lock Bank2 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation |\r
- |----------------------------------------------------------------------------------------------------------------------------------|\r
- | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 |\r
- +----------------------------------------------------------------------------------------------------------------------------------+\r
-@endcode\r
-*/\r
-\r
-\r
-/**\r
- * @brief Sets the code latency value.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param FLASH_Latency: specifies the FLASH Latency value.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle\r
- * @arg FLASH_Latency_1: FLASH One Latency cycle\r
- * @arg FLASH_Latency_2: FLASH Two Latency cycles\r
- * @retval None\r
- */\r
-void FLASH_SetLatency(uint32_t FLASH_Latency)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r
- \r
- /* Read the ACR register */\r
- tmpreg = FLASH->ACR; \r
- \r
- /* Sets the Latency value */\r
- tmpreg &= ACR_LATENCY_Mask;\r
- tmpreg |= FLASH_Latency;\r
- \r
- /* Write the ACR register */\r
- FLASH->ACR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Half cycle flash access.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable\r
- * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable\r
- * @retval None\r
- */\r
-void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));\r
- \r
- /* Enable or disable the Half cycle access */\r
- FLASH->ACR &= ACR_HLFCYA_Mask;\r
- FLASH->ACR |= FLASH_HalfCycleAccess;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Prefetch Buffer.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable\r
- * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable\r
- * @retval None\r
- */\r
-void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));\r
- \r
- /* Enable or disable the Prefetch Buffer */\r
- FLASH->ACR &= ACR_PRFTBE_Mask;\r
- FLASH->ACR |= FLASH_PrefetchBuffer;\r
-}\r
-\r
-/**\r
- * @brief Unlocks the FLASH Program Erase Controller.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.\r
- * - For all other devices it unlocks Bank1 and it is equivalent \r
- * to FLASH_UnlockBank1 function.. \r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_Unlock(void)\r
-{\r
- /* Authorize the FPEC of Bank1 Access */\r
- FLASH->KEYR = FLASH_KEY1;\r
- FLASH->KEYR = FLASH_KEY2;\r
-\r
-#ifdef STM32F10X_XL\r
- /* Authorize the FPEC of Bank2 Access */\r
- FLASH->KEYR2 = FLASH_KEY1;\r
- FLASH->KEYR2 = FLASH_KEY2;\r
-#endif /* STM32F10X_XL */\r
-}\r
-/**\r
- * @brief Unlocks the FLASH Bank1 Program Erase Controller.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices this function unlocks Bank1.\r
- * - For all other devices it unlocks Bank1 and it is \r
- * equivalent to FLASH_Unlock function.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_UnlockBank1(void)\r
-{\r
- /* Authorize the FPEC of Bank1 Access */\r
- FLASH->KEYR = FLASH_KEY1;\r
- FLASH->KEYR = FLASH_KEY2;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Unlocks the FLASH Bank2 Program Erase Controller.\r
- * @note This function can be used only for STM32F10X_XL density devices.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_UnlockBank2(void)\r
-{\r
- /* Authorize the FPEC of Bank2 Access */\r
- FLASH->KEYR2 = FLASH_KEY1;\r
- FLASH->KEYR2 = FLASH_KEY2;\r
-\r
-}\r
-#endif /* STM32F10X_XL */\r
-\r
-/**\r
- * @brief Locks the FLASH Program Erase Controller.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices this function Locks Bank1 and Bank2.\r
- * - For all other devices it Locks Bank1 and it is equivalent \r
- * to FLASH_LockBank1 function.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_Lock(void)\r
-{\r
- /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */\r
- FLASH->CR |= CR_LOCK_Set;\r
-\r
-#ifdef STM32F10X_XL\r
- /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */\r
- FLASH->CR2 |= CR_LOCK_Set;\r
-#endif /* STM32F10X_XL */\r
-}\r
-\r
-/**\r
- * @brief Locks the FLASH Bank1 Program Erase Controller.\r
- * @note this function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices this function Locks Bank1.\r
- * - For all other devices it Locks Bank1 and it is equivalent \r
- * to FLASH_Lock function.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_LockBank1(void)\r
-{\r
- /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */\r
- FLASH->CR |= CR_LOCK_Set;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Locks the FLASH Bank2 Program Erase Controller.\r
- * @note This function can be used only for STM32F10X_XL density devices.\r
- * @param None\r
- * @retval None\r
- */\r
-void FLASH_LockBank2(void)\r
-{\r
- /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */\r
- FLASH->CR2 |= CR_LOCK_Set;\r
-}\r
-#endif /* STM32F10X_XL */\r
-\r
-/**\r
- * @brief Erases a specified FLASH page.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param Page_Address: The page address to be erased.\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_ADDRESS(Page_Address));\r
-\r
-#ifdef STM32F10X_XL\r
- if(Page_Address < FLASH_BANK1_END_ADDRESS) \r
- {\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* if the previous operation is completed, proceed to erase the page */\r
- FLASH->CR|= CR_PER_Set;\r
- FLASH->AR = Page_Address; \r
- FLASH->CR|= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
-\r
- /* Disable the PER Bit */\r
- FLASH->CR &= CR_PER_Reset;\r
- }\r
- }\r
- else\r
- {\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* if the previous operation is completed, proceed to erase the page */\r
- FLASH->CR2|= CR_PER_Set;\r
- FLASH->AR2 = Page_Address; \r
- FLASH->CR2|= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
- \r
- /* Disable the PER Bit */\r
- FLASH->CR2 &= CR_PER_Reset;\r
- }\r
- }\r
-#else\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* if the previous operation is completed, proceed to erase the page */\r
- FLASH->CR|= CR_PER_Set;\r
- FLASH->AR = Page_Address; \r
- FLASH->CR|= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- \r
- /* Disable the PER Bit */\r
- FLASH->CR &= CR_PER_Reset;\r
- }\r
-#endif /* STM32F10X_XL */\r
-\r
- /* Return the Erase Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Erases all FLASH pages.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_EraseAllPages(void)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
-#ifdef STM32F10X_XL\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to erase all pages */\r
- FLASH->CR |= CR_MER_Set;\r
- FLASH->CR |= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
- \r
- /* Disable the MER Bit */\r
- FLASH->CR &= CR_MER_Reset;\r
- } \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to erase all pages */\r
- FLASH->CR2 |= CR_MER_Set;\r
- FLASH->CR2 |= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
- \r
- /* Disable the MER Bit */\r
- FLASH->CR2 &= CR_MER_Reset;\r
- }\r
-#else\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to erase all pages */\r
- FLASH->CR |= CR_MER_Set;\r
- FLASH->CR |= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
-\r
- /* Disable the MER Bit */\r
- FLASH->CR &= CR_MER_Reset;\r
- }\r
-#endif /* STM32F10X_XL */\r
-\r
- /* Return the Erase Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Erases all Bank1 FLASH pages.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices this function erases all Bank1 pages.\r
- * - For all other devices it erases all Bank1 pages and it is equivalent \r
- * to FLASH_EraseAllPages function.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_EraseAllBank1Pages(void)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to erase all pages */\r
- FLASH->CR |= CR_MER_Set;\r
- FLASH->CR |= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
- \r
- /* Disable the MER Bit */\r
- FLASH->CR &= CR_MER_Reset;\r
- } \r
- /* Return the Erase Status */\r
- return status;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Erases all Bank2 FLASH pages.\r
- * @note This function can be used only for STM32F10x_XL density devices.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_EraseAllBank2Pages(void)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to erase all pages */\r
- FLASH->CR2 |= CR_MER_Set;\r
- FLASH->CR2 |= CR_STRT_Set;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
-\r
- /* Disable the MER Bit */\r
- FLASH->CR2 &= CR_MER_Reset;\r
- } \r
- /* Return the Erase Status */\r
- return status;\r
-}\r
-#endif /* STM32F10X_XL */\r
-\r
-/**\r
- * @brief Erases the FLASH option bytes.\r
- * @note This functions erases all option bytes except the Read protection (RDP). \r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_EraseOptionBytes(void)\r
-{\r
- uint16_t rdptmp = RDP_Key;\r
-\r
- FLASH_Status status = FLASH_COMPLETE;\r
-\r
- /* Get the actual read protection Option Byte value */ \r
- if(FLASH_GetReadOutProtectionStatus() != RESET)\r
- {\r
- rdptmp = 0x00; \r
- }\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Authorize the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- \r
- /* if the previous operation is completed, proceed to erase the option bytes */\r
- FLASH->CR |= CR_OPTER_Set;\r
- FLASH->CR |= CR_STRT_Set;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the erase operation is completed, disable the OPTER Bit */\r
- FLASH->CR &= CR_OPTER_Reset;\r
- \r
- /* Enable the Option Bytes Programming operation */\r
- FLASH->CR |= CR_OPTPG_Set;\r
- /* Restore the last read protection Option Byte value */\r
- OB->RDP = (uint16_t)rdptmp; \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- }\r
- else\r
- {\r
- if (status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- } \r
- }\r
- /* Return the erase status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a word at a specified address.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param Address: specifies the address to be programmed.\r
- * @param Data: specifies the data to be programmed.\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_ADDRESS(Address));\r
-\r
-#ifdef STM32F10X_XL\r
- if(Address < FLASH_BANK1_END_ADDRESS - 2)\r
- { \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout); \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new first \r
- half word */\r
- FLASH->CR |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = (uint16_t)Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new second \r
- half word */\r
- tmp = Address + 2;\r
-\r
- *(__IO uint16_t*) tmp = Data >> 16;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- else\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- }\r
- }\r
- else if(Address == (FLASH_BANK1_END_ADDRESS - 1))\r
- {\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
-\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new first \r
- half word */\r
- FLASH->CR |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = (uint16_t)Data;\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
- \r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- else\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
-\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
-\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new second \r
- half word */\r
- FLASH->CR2 |= CR_PG_Set;\r
- tmp = Address + 2;\r
-\r
- *(__IO uint16_t*) tmp = Data >> 16;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
- \r
- /* Disable the PG Bit */\r
- FLASH->CR2 &= CR_PG_Reset;\r
- }\r
- else\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR2 &= CR_PG_Reset;\r
- }\r
- }\r
- else\r
- {\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
-\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new first \r
- half word */\r
- FLASH->CR2 |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = (uint16_t)Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new second \r
- half word */\r
- tmp = Address + 2;\r
-\r
- *(__IO uint16_t*) tmp = Data >> 16;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
- \r
- /* Disable the PG Bit */\r
- FLASH->CR2 &= CR_PG_Reset;\r
- }\r
- else\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR2 &= CR_PG_Reset;\r
- }\r
- }\r
- }\r
-#else\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new first \r
- half word */\r
- FLASH->CR |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = (uint16_t)Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new second \r
- half word */\r
- tmp = Address + 2;\r
-\r
- *(__IO uint16_t*) tmp = Data >> 16;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- else\r
- {\r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- } \r
-#endif /* STM32F10X_XL */\r
- \r
- /* Return the Program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a half word at a specified address.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param Address: specifies the address to be programmed.\r
- * @param Data: specifies the data to be programmed.\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_ADDRESS(Address));\r
-\r
-#ifdef STM32F10X_XL\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(Address < FLASH_BANK1_END_ADDRESS)\r
- {\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new data */\r
- FLASH->CR |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
-\r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- }\r
- }\r
- else\r
- {\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new data */\r
- FLASH->CR2 |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
-\r
- /* Disable the PG Bit */\r
- FLASH->CR2 &= CR_PG_Reset;\r
- }\r
- }\r
-#else\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the previous operation is completed, proceed to program the new data */\r
- FLASH->CR |= CR_PG_Set;\r
- \r
- *(__IO uint16_t*)Address = Data;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- /* Disable the PG Bit */\r
- FLASH->CR &= CR_PG_Reset;\r
- } \r
-#endif /* STM32F10X_XL */\r
- \r
- /* Return the Program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Programs a half word at a specified Option Byte Data address.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param Address: specifies the address to be programmed.\r
- * This parameter can be 0x1FFFF804 or 0x1FFFF806. \r
- * @param Data: specifies the data to be programmed.\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
- */\r
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Check the parameters */\r
- assert_param(IS_OB_DATA_ADDRESS(Address));\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
-\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Authorize the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- /* Enables the Option Bytes Programming operation */\r
- FLASH->CR |= CR_OPTPG_Set; \r
- *(__IO uint16_t*)Address = Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- }\r
- /* Return the Option Byte Data Program Status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Write protects the desired pages\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param FLASH_Pages: specifies the address of the pages to be write protected.\r
- * This parameter can be:\r
- * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 \r
- * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3\r
- * and FLASH_WRProt_Pages124to127\r
- * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and\r
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255\r
- * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and\r
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 \r
- * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and\r
- * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511\r
- * @arg FLASH_WRProt_AllPages\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)\r
-{\r
- uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;\r
- \r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));\r
- \r
- FLASH_Pages = (uint32_t)(~FLASH_Pages);\r
- WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);\r
- WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);\r
- WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);\r
- WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Authorizes the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- FLASH->CR |= CR_OPTPG_Set;\r
- if(WRP0_Data != 0xFF)\r
- {\r
- OB->WRP0 = WRP0_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- }\r
- if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))\r
- {\r
- OB->WRP1 = WRP1_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- }\r
- if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))\r
- {\r
- OB->WRP2 = WRP2_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- }\r
- \r
- if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))\r
- {\r
- OB->WRP3 = WRP3_Data;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- }\r
- \r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- } \r
- /* Return the write protection operation Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the read out protection.\r
- * @note If the user has already programmed the other option bytes before calling \r
- * this function, he must re-program them since this function erases all option bytes.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param Newstate: new state of the ReadOut Protection.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE;\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* Authorizes the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- FLASH->CR |= CR_OPTER_Set;\r
- FLASH->CR |= CR_STRT_Set;\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout);\r
- if(status == FLASH_COMPLETE)\r
- {\r
- /* if the erase operation is completed, disable the OPTER Bit */\r
- FLASH->CR &= CR_OPTER_Reset;\r
- /* Enable the Option Bytes Programming operation */\r
- FLASH->CR |= CR_OPTPG_Set; \r
- if(NewState != DISABLE)\r
- {\r
- OB->RDP = 0x00;\r
- }\r
- else\r
- {\r
- OB->RDP = RDP_Key; \r
- }\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(EraseTimeout); \r
- \r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- }\r
- else \r
- {\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* Disable the OPTER Bit */\r
- FLASH->CR &= CR_OPTER_Reset;\r
- }\r
- }\r
- }\r
- /* Return the protection operation Status */\r
- return status; \r
-}\r
-\r
-/**\r
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param OB_IWDG: Selects the IWDG mode\r
- * This parameter can be one of the following values:\r
- * @arg OB_IWDG_SW: Software IWDG selected\r
- * @arg OB_IWDG_HW: Hardware IWDG selected\r
- * @param OB_STOP: Reset event when entering STOP mode.\r
- * This parameter can be one of the following values:\r
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r
- * @arg OB_STOP_RST: Reset generated when entering in STOP\r
- * @param OB_STDBY: Reset event when entering Standby mode.\r
- * This parameter can be one of the following values:\r
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, \r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)\r
-{\r
- FLASH_Status status = FLASH_COMPLETE; \r
-\r
- /* Check the parameters */\r
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
-\r
- /* Authorize the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* Enable the Option Bytes Programming operation */\r
- FLASH->CR |= CR_OPTPG_Set; \r
- \r
- OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); \r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- } \r
- /* Return the Option Byte program Status */\r
- return status;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Configures to boot from Bank1 or Bank2. \r
- * @note This function can be used only for STM32F10x_XL density devices.\r
- * @param FLASH_BOOT: select the FLASH Bank to boot from.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash\r
- * position and this parameter is selected the device will boot from Bank1(Default).\r
- * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash\r
- * position and this parameter is selected the device will boot from Bank2 or Bank1,\r
- * depending on the activation of the bank. The active banks are checked in\r
- * the following order: Bank2, followed by Bank1.\r
- * The active bank is recognized by the value programmed at the base address\r
- * of the respective bank (corresponding to the initial stack pointer value\r
- * in the interrupt vector table).\r
- * For more information, please refer to AN2606 from www.st.com. \r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, \r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)\r
-{ \r
- FLASH_Status status = FLASH_COMPLETE; \r
- assert_param(IS_FLASH_BOOT(FLASH_BOOT));\r
- /* Authorize the small information block programming */\r
- FLASH->OPTKEYR = FLASH_KEY1;\r
- FLASH->OPTKEYR = FLASH_KEY2;\r
- \r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- \r
- if(status == FLASH_COMPLETE)\r
- { \r
- /* Enable the Option Bytes Programming operation */\r
- FLASH->CR |= CR_OPTPG_Set; \r
-\r
- if(FLASH_BOOT == FLASH_BOOT_Bank1)\r
- {\r
- OB->USER |= OB_USER_BFB2;\r
- }\r
- else\r
- {\r
- OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));\r
- }\r
- /* Wait for last operation to be completed */\r
- status = FLASH_WaitForLastOperation(ProgramTimeout);\r
- if(status != FLASH_TIMEOUT)\r
- {\r
- /* if the program operation is completed, disable the OPTPG Bit */\r
- FLASH->CR &= CR_OPTPG_Reset;\r
- }\r
- } \r
- /* Return the Option Byte program Status */\r
- return status;\r
-}\r
-#endif /* STM32F10X_XL */\r
-\r
-/**\r
- * @brief Returns the FLASH User Option Bytes values.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)\r
- * and RST_STDBY(Bit2).\r
- */\r
-uint32_t FLASH_GetUserOptionByte(void)\r
-{\r
- /* Return the User Option Byte */\r
- return (uint32_t)(FLASH->OBR >> 2);\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Write Protection Option Bytes Register value.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval The FLASH Write Protection Option Bytes Register value\r
- */\r
-uint32_t FLASH_GetWriteProtectionOptionByte(void)\r
-{\r
- /* Return the Falsh write protection Register value */\r
- return (uint32_t)(FLASH->WRPR);\r
-}\r
-\r
-/**\r
- * @brief Checks whether the FLASH Read Out Protection Status is set or not.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval FLASH ReadOut Protection Status(SET or RESET)\r
- */\r
-FlagStatus FLASH_GetReadOutProtectionStatus(void)\r
-{\r
- FlagStatus readoutstatus = RESET;\r
- if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)\r
- {\r
- readoutstatus = SET;\r
- }\r
- else\r
- {\r
- readoutstatus = RESET;\r
- }\r
- return readoutstatus;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the FLASH Prefetch Buffer status is set or not.\r
- * @note This function can be used for all STM32F10x devices.\r
- * @param None\r
- * @retval FLASH Prefetch Buffer Status (SET or RESET).\r
- */\r
-FlagStatus FLASH_GetPrefetchBufferStatus(void)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- \r
- if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */\r
- return bitstatus; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified FLASH interrupts.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts\r
- for Bank1 and Bank2.\r
- * - For other devices it enables or disables the specified FLASH interrupts for Bank1.\r
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg FLASH_IT_ERROR: FLASH Error Interrupt\r
- * @arg FLASH_IT_EOP: FLASH end of operation Interrupt\r
- * @param NewState: new state of the specified Flash interrupts.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @retval None \r
- */\r
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)\r
-{\r
-#ifdef STM32F10X_XL\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_IT(FLASH_IT)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if((FLASH_IT & 0x80000000) != 0x0)\r
- {\r
- if(NewState != DISABLE)\r
- {\r
- /* Enable the interrupt sources */\r
- FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);\r
- }\r
- else\r
- {\r
- /* Disable the interrupt sources */\r
- FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);\r
- }\r
- }\r
- else\r
- {\r
- if(NewState != DISABLE)\r
- {\r
- /* Enable the interrupt sources */\r
- FLASH->CR |= FLASH_IT;\r
- }\r
- else\r
- {\r
- /* Disable the interrupt sources */\r
- FLASH->CR &= ~(uint32_t)FLASH_IT;\r
- }\r
- }\r
-#else\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_IT(FLASH_IT)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
-\r
- if(NewState != DISABLE)\r
- {\r
- /* Enable the interrupt sources */\r
- FLASH->CR |= FLASH_IT;\r
- }\r
- else\r
- {\r
- /* Disable the interrupt sources */\r
- FLASH->CR &= ~(uint32_t)FLASH_IT;\r
- }\r
-#endif /* STM32F10X_XL */\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified FLASH flag is set or not.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices, this function checks whether the specified \r
- * Bank1 or Bank2 flag is set or not.\r
- * - For other devices, it checks whether the specified Bank1 flag is \r
- * set or not.\r
- * @param FLASH_FLAG: specifies the FLASH flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg FLASH_FLAG_BSY: FLASH Busy flag \r
- * @arg FLASH_FLAG_PGERR: FLASH Program error flag \r
- * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag \r
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r
- * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag \r
- * @retval The new state of FLASH_FLAG (SET or RESET).\r
- */\r
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
-\r
-#ifdef STM32F10X_XL\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;\r
- if(FLASH_FLAG == FLASH_FLAG_OPTERR) \r
- {\r
- if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
- else\r
- {\r
- if((FLASH_FLAG & 0x80000000) != 0x0)\r
- {\r
- if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
- else\r
- {\r
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
- }\r
-#else\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;\r
- if(FLASH_FLAG == FLASH_FLAG_OPTERR) \r
- {\r
- if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
- else\r
- {\r
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- }\r
-#endif /* STM32F10X_XL */\r
-\r
- /* Return the new state of FLASH_FLAG (SET or RESET) */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the FLASH\92s pending flags.\r
- * @note This function can be used for all STM32F10x devices.\r
- * - For STM32F10X_XL devices, this function clears Bank1 or Bank2\92s pending flags\r
- * - For other devices, it clears Bank1\92s pending flags.\r
- * @param FLASH_FLAG: specifies the FLASH flags to clear.\r
- * This parameter can be any combination of the following values: \r
- * @arg FLASH_FLAG_PGERR: FLASH Program error flag \r
- * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag \r
- * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r
- * @retval None\r
- */\r
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)\r
-{\r
-#ifdef STM32F10X_XL\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;\r
-\r
- if((FLASH_FLAG & 0x80000000) != 0x0)\r
- {\r
- /* Clear the flags */\r
- FLASH->SR2 = FLASH_FLAG;\r
- }\r
- else\r
- {\r
- /* Clear the flags */\r
- FLASH->SR = FLASH_FLAG;\r
- } \r
-\r
-#else\r
- /* Check the parameters */\r
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;\r
- \r
- /* Clear the flags */\r
- FLASH->SR = FLASH_FLAG;\r
-#endif /* STM32F10X_XL */\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Status.\r
- * @note This function can be used for all STM32F10x devices, it is equivalent\r
- * to FLASH_GetBank1Status function.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP or FLASH_COMPLETE\r
- */\r
-FLASH_Status FLASH_GetStatus(void)\r
-{\r
- FLASH_Status flashstatus = FLASH_COMPLETE;\r
- \r
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
- {\r
- flashstatus = FLASH_BUSY;\r
- }\r
- else \r
- { \r
- if((FLASH->SR & FLASH_FLAG_PGERR) != 0)\r
- { \r
- flashstatus = FLASH_ERROR_PG;\r
- }\r
- else \r
- {\r
- if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )\r
- {\r
- flashstatus = FLASH_ERROR_WRP;\r
- }\r
- else\r
- {\r
- flashstatus = FLASH_COMPLETE;\r
- }\r
- }\r
- }\r
- /* Return the Flash Status */\r
- return flashstatus;\r
-}\r
-\r
-/**\r
- * @brief Returns the FLASH Bank1 Status.\r
- * @note This function can be used for all STM32F10x devices, it is equivalent\r
- * to FLASH_GetStatus function.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP or FLASH_COMPLETE\r
- */\r
-FLASH_Status FLASH_GetBank1Status(void)\r
-{\r
- FLASH_Status flashstatus = FLASH_COMPLETE;\r
- \r
- if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) \r
- {\r
- flashstatus = FLASH_BUSY;\r
- }\r
- else \r
- { \r
- if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)\r
- { \r
- flashstatus = FLASH_ERROR_PG;\r
- }\r
- else \r
- {\r
- if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )\r
- {\r
- flashstatus = FLASH_ERROR_WRP;\r
- }\r
- else\r
- {\r
- flashstatus = FLASH_COMPLETE;\r
- }\r
- }\r
- }\r
- /* Return the Flash Status */\r
- return flashstatus;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Returns the FLASH Bank2 Status.\r
- * @note This function can be used for STM32F10x_XL density devices.\r
- * @param None\r
- * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP or FLASH_COMPLETE\r
- */\r
-FLASH_Status FLASH_GetBank2Status(void)\r
-{\r
- FLASH_Status flashstatus = FLASH_COMPLETE;\r
- \r
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) \r
- {\r
- flashstatus = FLASH_BUSY;\r
- }\r
- else \r
- { \r
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)\r
- { \r
- flashstatus = FLASH_ERROR_PG;\r
- }\r
- else \r
- {\r
- if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )\r
- {\r
- flashstatus = FLASH_ERROR_WRP;\r
- }\r
- else\r
- {\r
- flashstatus = FLASH_COMPLETE;\r
- }\r
- }\r
- }\r
- /* Return the Flash Status */\r
- return flashstatus;\r
-}\r
-#endif /* STM32F10X_XL */\r
-/**\r
- * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.\r
- * @note This function can be used for all STM32F10x devices, \r
- * it is equivalent to FLASH_WaitForLastBank1Operation.\r
- * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation\r
- * to complete or a TIMEOUT to occur.\r
- * - For all other devices it waits for a Flash operation to complete \r
- * or a TIMEOUT to occur.\r
- * @param Timeout: FLASH progamming Timeout\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)\r
-{ \r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check for the Flash Status */\r
- status = FLASH_GetBank1Status();\r
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
- while((status == FLASH_BUSY) && (Timeout != 0x00))\r
- {\r
- status = FLASH_GetBank1Status();\r
- Timeout--;\r
- }\r
- if(Timeout == 0x00 )\r
- {\r
- status = FLASH_TIMEOUT;\r
- }\r
- /* Return the operation status */\r
- return status;\r
-}\r
-\r
-/**\r
- * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.\r
- * @note This function can be used for all STM32F10x devices, \r
- * it is equivalent to FLASH_WaitForLastOperation.\r
- * @param Timeout: FLASH progamming Timeout\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)\r
-{ \r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check for the Flash Status */\r
- status = FLASH_GetBank1Status();\r
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
- while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))\r
- {\r
- status = FLASH_GetBank1Status();\r
- Timeout--;\r
- }\r
- if(Timeout == 0x00 )\r
- {\r
- status = FLASH_TIMEOUT;\r
- }\r
- /* Return the operation status */\r
- return status;\r
-}\r
-\r
-#ifdef STM32F10X_XL\r
-/**\r
- * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.\r
- * @note This function can be used only for STM32F10x_XL density devices.\r
- * @param Timeout: FLASH progamming Timeout\r
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
- */\r
-FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)\r
-{ \r
- FLASH_Status status = FLASH_COMPLETE;\r
- \r
- /* Check for the Flash Status */\r
- status = FLASH_GetBank2Status();\r
- /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
- while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))\r
- {\r
- status = FLASH_GetBank2Status();\r
- Timeout--;\r
- }\r
- if(Timeout == 0x00 )\r
- {\r
- status = FLASH_TIMEOUT;\r
- }\r
- /* Return the operation status */\r
- return status;\r
-}\r
-#endif /* STM32F10X_XL */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_fsmc.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the FSMC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_fsmc.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup FSMC \r
- * @brief FSMC driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup FSMC_Private_TypesDefinitions\r
- * @{\r
- */ \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Private_Defines\r
- * @{\r
- */\r
-\r
-/* --------------------- FSMC registers bit mask ---------------------------- */\r
-\r
-/* FSMC BCRx Mask */\r
-#define BCR_MBKEN_Set ((uint32_t)0x00000001)\r
-#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)\r
-#define BCR_FACCEN_Set ((uint32_t)0x00000040)\r
-\r
-/* FSMC PCRx Mask */\r
-#define PCR_PBKEN_Set ((uint32_t)0x00000004)\r
-#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)\r
-#define PCR_ECCEN_Set ((uint32_t)0x00000040)\r
-#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)\r
-#define PCR_MemoryType_NAND ((uint32_t)0x00000008)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup FSMC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default \r
- * reset values.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
- * @retval None\r
- */\r
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
- \r
- /* FSMC_Bank1_NORSRAM1 */\r
- if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r
- {\r
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; \r
- }\r
- /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r
- else\r
- { \r
- FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r
- }\r
- FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r
- FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; \r
-}\r
-\r
-/**\r
- * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND \r
- * @retval None\r
- */\r
-void FSMC_NANDDeInit(uint32_t FSMC_Bank)\r
-{\r
- /* Check the parameter */\r
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- /* Set the FSMC_Bank2 registers to their reset values */\r
- FSMC_Bank2->PCR2 = 0x00000018;\r
- FSMC_Bank2->SR2 = 0x00000040;\r
- FSMC_Bank2->PMEM2 = 0xFCFCFCFC;\r
- FSMC_Bank2->PATT2 = 0xFCFCFCFC; \r
- }\r
- /* FSMC_Bank3_NAND */ \r
- else\r
- {\r
- /* Set the FSMC_Bank3 registers to their reset values */\r
- FSMC_Bank3->PCR3 = 0x00000018;\r
- FSMC_Bank3->SR3 = 0x00000040;\r
- FSMC_Bank3->PMEM3 = 0xFCFCFCFC;\r
- FSMC_Bank3->PATT3 = 0xFCFCFCFC; \r
- } \r
-}\r
-\r
-/**\r
- * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.\r
- * @param None \r
- * @retval None\r
- */\r
-void FSMC_PCCARDDeInit(void)\r
-{\r
- /* Set the FSMC_Bank4 registers to their reset values */\r
- FSMC_Bank4->PCR4 = 0x00000018; \r
- FSMC_Bank4->SR4 = 0x00000000; \r
- FSMC_Bank4->PMEM4 = 0xFCFCFCFC;\r
- FSMC_Bank4->PATT4 = 0xFCFCFCFC;\r
- FSMC_Bank4->PIO4 = 0xFCFCFCFC;\r
-}\r
-\r
-/**\r
- * @brief Initializes the FSMC NOR/SRAM Banks according to the specified\r
- * parameters in the FSMC_NORSRAMInitStruct.\r
- * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef\r
- * structure that contains the configuration information for \r
- * the FSMC NOR/SRAM specified Banks. \r
- * @retval None\r
- */\r
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r
- assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r
- assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r
- assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r
- assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r
- assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));\r
- assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r
- assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r
- assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r
- assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r
- assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r
- assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r
- assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); \r
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r
- assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r
- \r
- /* Bank1 NOR/SRAM control register configuration */ \r
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r
- FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r
- FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r
-\r
- if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r
- {\r
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;\r
- }\r
- \r
- /* Bank1 NOR/SRAM timing register configuration */\r
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r
- (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r
- \r
- \r
- /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r
- if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r
- {\r
- assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r
- assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r
- assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r
- assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r
- }\r
- else\r
- {\r
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the FSMC NAND Banks according to the specified \r
- * parameters in the FSMC_NANDInitStruct.\r
- * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef \r
- * structure that contains the configuration information for the FSMC NAND specified Banks. \r
- * @retval None\r
- */\r
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
-{\r
- uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; \r
- \r
- /* Check the parameters */\r
- assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));\r
- assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));\r
- assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));\r
- assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));\r
- assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));\r
- assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));\r
- assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));\r
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
- assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
- assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
- assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
- assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
- \r
- /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */\r
- tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |\r
- PCR_MemoryType_NAND |\r
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth |\r
- FSMC_NANDInitStruct->FSMC_ECC |\r
- FSMC_NANDInitStruct->FSMC_ECCPageSize |\r
- (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|\r
- (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);\r
- \r
- /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */\r
- tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
- \r
- /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */\r
- tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);\r
- \r
- if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- /* FSMC_Bank2_NAND registers configuration */\r
- FSMC_Bank2->PCR2 = tmppcr;\r
- FSMC_Bank2->PMEM2 = tmppmem;\r
- FSMC_Bank2->PATT2 = tmppatt;\r
- }\r
- else\r
- {\r
- /* FSMC_Bank3_NAND registers configuration */\r
- FSMC_Bank3->PCR3 = tmppcr;\r
- FSMC_Bank3->PMEM3 = tmppmem;\r
- FSMC_Bank3->PATT3 = tmppatt;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the FSMC PCCARD Bank according to the specified \r
- * parameters in the FSMC_PCCARDInitStruct.\r
- * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef\r
- * structure that contains the configuration information for the FSMC PCCARD Bank. \r
- * @retval None\r
- */\r
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));\r
- assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));\r
- assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));\r
- \r
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
- \r
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
- assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));\r
- assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));\r
- assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));\r
- assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));\r
- \r
- /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */\r
- FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |\r
- FSMC_MemoryDataWidth_16b | \r
- (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |\r
- (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);\r
- \r
- /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */\r
- FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
- \r
- /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */\r
- FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
- \r
- /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */\r
- FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |\r
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
-}\r
-\r
-/**\r
- * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.\r
- * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef \r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
-{ \r
- /* Reset NOR/SRAM Init structure parameters values */\r
- FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r
- FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
- FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
- FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
- FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
- FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r
- FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r
-}\r
-\r
-/**\r
- * @brief Fills each FSMC_NANDInitStruct member with its default value.\r
- * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef \r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
-{ \r
- /* Reset NAND Init structure parameters values */\r
- FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;\r
- FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
- FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;\r
- FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;\r
- FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
- FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;\r
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
- FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; \r
-}\r
-\r
-/**\r
- * @brief Fills each FSMC_PCCARDInitStruct member with its default value.\r
- * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef \r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
-{\r
- /* Reset PCCARD Init structure parameters values */\r
- FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
- FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
- FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;\r
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; \r
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
- FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified NOR/SRAM Memory Bank.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
- * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
- * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
- * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
- * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
-{\r
- assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */\r
- FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */\r
- FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified NAND Memory Bank.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
-{\r
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;\r
- }\r
- else\r
- {\r
- FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;\r
- }\r
- }\r
- else\r
- {\r
- /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;\r
- }\r
- else\r
- {\r
- FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the PCCARD Memory Bank.\r
- * @param NewState: new state of the PCCARD Memory Bank. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FSMC_PCCARDCmd(FunctionalState NewState)\r
-{\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */\r
- FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */\r
- FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the FSMC NAND ECC feature.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @param NewState: new state of the FSMC NAND ECC feature. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
-{\r
- assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;\r
- }\r
- else\r
- {\r
- FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;\r
- }\r
- }\r
- else\r
- {\r
- /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;\r
- }\r
- else\r
- {\r
- FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the error correction code register value.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @retval The Error Correction Code (ECC) value.\r
- */\r
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank)\r
-{\r
- uint32_t eccval = 0x00000000;\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- /* Get the ECCR2 register value */\r
- eccval = FSMC_Bank2->ECCR2;\r
- }\r
- else\r
- {\r
- /* Get the ECCR3 register value */\r
- eccval = FSMC_Bank3->ECCR3;\r
- }\r
- /* Return the error correction code value */\r
- return(eccval);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified FSMC interrupts.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
- * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
- * @arg FSMC_IT_Level: Level edge detection interrupt.\r
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
- * @param NewState: new state of the specified FSMC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)\r
-{\r
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
- assert_param(IS_FSMC_IT(FSMC_IT)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected FSMC_Bank2 interrupts */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->SR2 |= FSMC_IT;\r
- }\r
- /* Enable the selected FSMC_Bank3 interrupts */\r
- else if (FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- FSMC_Bank3->SR3 |= FSMC_IT;\r
- }\r
- /* Enable the selected FSMC_Bank4 interrupts */\r
- else\r
- {\r
- FSMC_Bank4->SR4 |= FSMC_IT; \r
- }\r
- }\r
- else\r
- {\r
- /* Disable the selected FSMC_Bank2 interrupts */\r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- \r
- FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;\r
- }\r
- /* Disable the selected FSMC_Bank3 interrupts */\r
- else if (FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;\r
- }\r
- /* Disable the selected FSMC_Bank4 interrupts */\r
- else\r
- {\r
- FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; \r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified FSMC flag is set or not.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
- * @param FSMC_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
- * @arg FSMC_FLAG_Level: Level detection Flag.\r
- * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
- * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. \r
- * @retval The new state of FSMC_FLAG (SET or RESET).\r
- */\r
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- uint32_t tmpsr = 0x00000000;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
- assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- tmpsr = FSMC_Bank2->SR2;\r
- } \r
- else if(FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- tmpsr = FSMC_Bank3->SR3;\r
- }\r
- /* FSMC_Bank4_PCCARD*/\r
- else\r
- {\r
- tmpsr = FSMC_Bank4->SR4;\r
- } \r
- \r
- /* Get the flag status */\r
- if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the FSMC\92s pending flags.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
- * @param FSMC_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
- * @arg FSMC_FLAG_Level: Level detection Flag.\r
- * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
- * @retval None\r
- */\r
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
- assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->SR2 &= ~FSMC_FLAG; \r
- } \r
- else if(FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- FSMC_Bank3->SR3 &= ~FSMC_FLAG;\r
- }\r
- /* FSMC_Bank4_PCCARD*/\r
- else\r
- {\r
- FSMC_Bank4->SR4 &= ~FSMC_FLAG;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified FSMC interrupt has occurred or not.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
- * @param FSMC_IT: specifies the FSMC interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
- * @arg FSMC_IT_Level: Level edge detection interrupt.\r
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. \r
- * @retval The new state of FSMC_IT (SET or RESET).\r
- */\r
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; \r
- \r
- /* Check the parameters */\r
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
- assert_param(IS_FSMC_GET_IT(FSMC_IT));\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- tmpsr = FSMC_Bank2->SR2;\r
- } \r
- else if(FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- tmpsr = FSMC_Bank3->SR3;\r
- }\r
- /* FSMC_Bank4_PCCARD*/\r
- else\r
- {\r
- tmpsr = FSMC_Bank4->SR4;\r
- } \r
- \r
- itstatus = tmpsr & FSMC_IT;\r
- \r
- itenable = tmpsr & (FSMC_IT >> 3);\r
- if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus; \r
-}\r
-\r
-/**\r
- * @brief Clears the FSMC\92s interrupt pending bits.\r
- * @param FSMC_Bank: specifies the FSMC Bank to be used\r
- * This parameter can be one of the following values:\r
- * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
- * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
- * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
- * @param FSMC_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
- * @arg FSMC_IT_Level: Level edge detection interrupt.\r
- * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
- * @retval None\r
- */\r
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
- assert_param(IS_FSMC_IT(FSMC_IT));\r
- \r
- if(FSMC_Bank == FSMC_Bank2_NAND)\r
- {\r
- FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); \r
- } \r
- else if(FSMC_Bank == FSMC_Bank3_NAND)\r
- {\r
- FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);\r
- }\r
- /* FSMC_Bank4_PCCARD*/\r
- else\r
- {\r
- FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_i2c.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the I2C firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_i2c.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup I2C \r
- * @brief I2C driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup I2C_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Private_Defines\r
- * @{\r
- */\r
-\r
-/* I2C SPE mask */\r
-#define CR1_PE_Set ((uint16_t)0x0001)\r
-#define CR1_PE_Reset ((uint16_t)0xFFFE)\r
-\r
-/* I2C START mask */\r
-#define CR1_START_Set ((uint16_t)0x0100)\r
-#define CR1_START_Reset ((uint16_t)0xFEFF)\r
-\r
-/* I2C STOP mask */\r
-#define CR1_STOP_Set ((uint16_t)0x0200)\r
-#define CR1_STOP_Reset ((uint16_t)0xFDFF)\r
-\r
-/* I2C ACK mask */\r
-#define CR1_ACK_Set ((uint16_t)0x0400)\r
-#define CR1_ACK_Reset ((uint16_t)0xFBFF)\r
-\r
-/* I2C ENGC mask */\r
-#define CR1_ENGC_Set ((uint16_t)0x0040)\r
-#define CR1_ENGC_Reset ((uint16_t)0xFFBF)\r
-\r
-/* I2C SWRST mask */\r
-#define CR1_SWRST_Set ((uint16_t)0x8000)\r
-#define CR1_SWRST_Reset ((uint16_t)0x7FFF)\r
-\r
-/* I2C PEC mask */\r
-#define CR1_PEC_Set ((uint16_t)0x1000)\r
-#define CR1_PEC_Reset ((uint16_t)0xEFFF)\r
-\r
-/* I2C ENPEC mask */\r
-#define CR1_ENPEC_Set ((uint16_t)0x0020)\r
-#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)\r
-\r
-/* I2C ENARP mask */\r
-#define CR1_ENARP_Set ((uint16_t)0x0010)\r
-#define CR1_ENARP_Reset ((uint16_t)0xFFEF)\r
-\r
-/* I2C NOSTRETCH mask */\r
-#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)\r
-#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)\r
-\r
-/* I2C registers Masks */\r
-#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)\r
-\r
-/* I2C DMAEN mask */\r
-#define CR2_DMAEN_Set ((uint16_t)0x0800)\r
-#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)\r
-\r
-/* I2C LAST mask */\r
-#define CR2_LAST_Set ((uint16_t)0x1000)\r
-#define CR2_LAST_Reset ((uint16_t)0xEFFF)\r
-\r
-/* I2C FREQ mask */\r
-#define CR2_FREQ_Reset ((uint16_t)0xFFC0)\r
-\r
-/* I2C ADD0 mask */\r
-#define OAR1_ADD0_Set ((uint16_t)0x0001)\r
-#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)\r
-\r
-/* I2C ENDUAL mask */\r
-#define OAR2_ENDUAL_Set ((uint16_t)0x0001)\r
-#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)\r
-\r
-/* I2C ADD2 mask */\r
-#define OAR2_ADD2_Reset ((uint16_t)0xFF01)\r
-\r
-/* I2C F/S mask */\r
-#define CCR_FS_Set ((uint16_t)0x8000)\r
-\r
-/* I2C CCR mask */\r
-#define CCR_CCR_Set ((uint16_t)0x0FFF)\r
-\r
-/* I2C FLAG mask */\r
-#define FLAG_Mask ((uint32_t)0x00FFFFFF)\r
-\r
-/* I2C Interrupt Enable mask */\r
-#define ITEN_Mask ((uint32_t)0x07000000)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup I2C_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the I2Cx peripheral registers to their default reset values.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval None\r
- */\r
-void I2C_DeInit(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- if (I2Cx == I2C1)\r
- {\r
- /* Enable I2C1 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
- /* Release I2C1 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
- }\r
- else\r
- {\r
- /* Enable I2C2 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
- /* Release I2C2 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the I2Cx peripheral according to the specified \r
- * parameters in the I2C_InitStruct.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
- * contains the configuration information for the specified I2C peripheral.\r
- * @retval None\r
- */\r
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
-{\r
- uint16_t tmpreg = 0, freqrange = 0;\r
- uint16_t result = 0x04;\r
- uint32_t pclk1 = 8000000;\r
- RCC_ClocksTypeDef rcc_clocks;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));\r
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
- assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
-\r
-/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r
- /* Get the I2Cx CR2 value */\r
- tmpreg = I2Cx->CR2;\r
- /* Clear frequency FREQ[5:0] bits */\r
- tmpreg &= CR2_FREQ_Reset;\r
- /* Get pclk1 frequency value */\r
- RCC_GetClocksFreq(&rcc_clocks);\r
- pclk1 = rcc_clocks.PCLK1_Frequency;\r
- /* Set frequency bits depending on pclk1 value */\r
- freqrange = (uint16_t)(pclk1 / 1000000);\r
- tmpreg |= freqrange;\r
- /* Write to I2Cx CR2 */\r
- I2Cx->CR2 = tmpreg;\r
-\r
-/*---------------------------- I2Cx CCR Configuration ------------------------*/\r
- /* Disable the selected I2C peripheral to configure TRISE */\r
- I2Cx->CR1 &= CR1_PE_Reset;\r
- /* Reset tmpreg value */\r
- /* Clear F/S, DUTY and CCR[11:0] bits */\r
- tmpreg = 0;\r
-\r
- /* Configure speed in standard mode */\r
- if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r
- {\r
- /* Standard mode speed calculate */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));\r
- /* Test if CCR value is under 0x4*/\r
- if (result < 0x04)\r
- {\r
- /* Set minimum allowed value */\r
- result = 0x04; \r
- }\r
- /* Set speed value for standard mode */\r
- tmpreg |= result; \r
- /* Set Maximum Rise Time for standard mode */\r
- I2Cx->TRISE = freqrange + 1; \r
- }\r
- /* Configure speed in fast mode */\r
- else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r
- {\r
- if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r
- {\r
- /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));\r
- }\r
- else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r
- {\r
- /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
- result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));\r
- /* Set DUTY bit */\r
- result |= I2C_DutyCycle_16_9;\r
- }\r
-\r
- /* Test if CCR value is under 0x1*/\r
- if ((result & CCR_CCR_Set) == 0)\r
- {\r
- /* Set minimum allowed value */\r
- result |= (uint16_t)0x0001; \r
- }\r
- /* Set speed value and set F/S bit for fast mode */\r
- tmpreg |= (uint16_t)(result | CCR_FS_Set);\r
- /* Set Maximum Rise Time for fast mode */\r
- I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); \r
- }\r
-\r
- /* Write to I2Cx CCR */\r
- I2Cx->CCR = tmpreg;\r
- /* Enable the selected I2C peripheral */\r
- I2Cx->CR1 |= CR1_PE_Set;\r
-\r
-/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r
- /* Get the I2Cx CR1 value */\r
- tmpreg = I2Cx->CR1;\r
- /* Clear ACK, SMBTYPE and SMBUS bits */\r
- tmpreg &= CR1_CLEAR_Mask;\r
- /* Configure I2Cx: mode and acknowledgement */\r
- /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r
- /* Set ACK bit according to I2C_Ack value */\r
- tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r
- /* Write to I2Cx CR1 */\r
- I2Cx->CR1 = tmpreg;\r
-\r
-/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r
- /* Set I2Cx Own Address1 and acknowledged address */\r
- I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r
-}\r
-\r
-/**\r
- * @brief Fills each I2C_InitStruct member with its default value.\r
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
-{\r
-/*---------------- Reset I2C init structure parameters values ----------------*/\r
- /* initialize the I2C_ClockSpeed member */\r
- I2C_InitStruct->I2C_ClockSpeed = 5000;\r
- /* Initialize the I2C_Mode member */\r
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
- /* Initialize the I2C_DutyCycle member */\r
- I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r
- /* Initialize the I2C_OwnAddress1 member */\r
- I2C_InitStruct->I2C_OwnAddress1 = 0;\r
- /* Initialize the I2C_Ack member */\r
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
- /* Initialize the I2C_AcknowledgedAddress member */\r
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C peripheral */\r
- I2Cx->CR1 |= CR1_PE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C peripheral */\r
- I2Cx->CR1 &= CR1_PE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C DMA requests.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C DMA transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C DMA requests */\r
- I2Cx->CR2 |= CR2_DMAEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C DMA requests */\r
- I2Cx->CR2 &= CR2_DMAEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Specifies if the next DMA transfer will be the last one.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C DMA last transfer.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Next DMA transfer is the last transfer */\r
- I2Cx->CR2 |= CR2_LAST_Set;\r
- }\r
- else\r
- {\r
- /* Next DMA transfer is not the last transfer */\r
- I2Cx->CR2 &= CR2_LAST_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Generates I2Cx communication START condition.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C START condition generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Generate a START condition */\r
- I2Cx->CR1 |= CR1_START_Set;\r
- }\r
- else\r
- {\r
- /* Disable the START condition generation */\r
- I2Cx->CR1 &= CR1_START_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Generates I2Cx communication STOP condition.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C STOP condition generation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Generate a STOP condition */\r
- I2Cx->CR1 |= CR1_STOP_Set;\r
- }\r
- else\r
- {\r
- /* Disable the STOP condition generation */\r
- I2Cx->CR1 &= CR1_STOP_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C acknowledge feature.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C Acknowledgement.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None.\r
- */\r
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the acknowledgement */\r
- I2Cx->CR1 |= CR1_ACK_Set;\r
- }\r
- else\r
- {\r
- /* Disable the acknowledgement */\r
- I2Cx->CR1 &= CR1_ACK_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the specified I2C own address2.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Address: specifies the 7bit I2C own address2.\r
- * @retval None.\r
- */\r
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)\r
-{\r
- uint16_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- /* Get the old register value */\r
- tmpreg = I2Cx->OAR2;\r
-\r
- /* Reset I2Cx Own address2 bit [7:1] */\r
- tmpreg &= OAR2_ADD2_Reset;\r
-\r
- /* Set I2Cx Own address2 */\r
- tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);\r
-\r
- /* Store the new register value */\r
- I2Cx->OAR2 = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C dual addressing mode.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C dual addressing mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable dual addressing mode */\r
- I2Cx->OAR2 |= OAR2_ENDUAL_Set;\r
- }\r
- else\r
- {\r
- /* Disable dual addressing mode */\r
- I2Cx->OAR2 &= OAR2_ENDUAL_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C general call feature.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C General call.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable generall call */\r
- I2Cx->CR1 |= CR1_ENGC_Set;\r
- }\r
- else\r
- {\r
- /* Disable generall call */\r
- I2Cx->CR1 &= CR1_ENGC_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C interrupts.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_IT_BUF: Buffer interrupt mask\r
- * @arg I2C_IT_EVT: Event interrupt mask\r
- * @arg I2C_IT_ERR: Error interrupt mask\r
- * @param NewState: new state of the specified I2C interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C interrupts */\r
- I2Cx->CR2 |= I2C_IT;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C interrupts */\r
- I2Cx->CR2 &= (uint16_t)~I2C_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sends a data byte through the I2Cx peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Data: Byte to be transmitted..\r
- * @retval None\r
- */\r
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Write in the DR register the data to be sent */\r
- I2Cx->DR = Data;\r
-}\r
-\r
-/**\r
- * @brief Returns the most recent received data by the I2Cx peripheral.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval The value of the received data.\r
- */\r
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Return the data in the DR register */\r
- return (uint8_t)I2Cx->DR;\r
-}\r
-\r
-/**\r
- * @brief Transmits the address byte to select the slave device.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param Address: specifies the slave address which will be transmitted\r
- * @param I2C_Direction: specifies whether the I2C device will be a\r
- * Transmitter or a Receiver. This parameter can be one of the following values\r
- * @arg I2C_Direction_Transmitter: Transmitter mode\r
- * @arg I2C_Direction_Receiver: Receiver mode\r
- * @retval None.\r
- */\r
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_DIRECTION(I2C_Direction));\r
- /* Test on the direction to set/reset the read/write bit */\r
- if (I2C_Direction != I2C_Direction_Transmitter)\r
- {\r
- /* Set the address bit0 for read */\r
- Address |= OAR1_ADD0_Set;\r
- }\r
- else\r
- {\r
- /* Reset the address bit0 for write */\r
- Address &= OAR1_ADD0_Reset;\r
- }\r
- /* Send the address */\r
- I2Cx->DR = Address;\r
-}\r
-\r
-/**\r
- * @brief Reads the specified I2C register and returns its value.\r
- * @param I2C_Register: specifies the register to read.\r
- * This parameter can be one of the following values:\r
- * @arg I2C_Register_CR1: CR1 register.\r
- * @arg I2C_Register_CR2: CR2 register.\r
- * @arg I2C_Register_OAR1: OAR1 register.\r
- * @arg I2C_Register_OAR2: OAR2 register.\r
- * @arg I2C_Register_DR: DR register.\r
- * @arg I2C_Register_SR1: SR1 register.\r
- * @arg I2C_Register_SR2: SR2 register.\r
- * @arg I2C_Register_CCR: CCR register.\r
- * @arg I2C_Register_TRISE: TRISE register.\r
- * @retval The value of the read register.\r
- */\r
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_REGISTER(I2C_Register));\r
-\r
- tmp = (uint32_t) I2Cx;\r
- tmp += I2C_Register;\r
-\r
- /* Return the selected register value */\r
- return (*(__IO uint16_t *) tmp);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C software reset.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C software reset.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Peripheral under reset */\r
- I2Cx->CR1 |= CR1_SWRST_Set;\r
- }\r
- else\r
- {\r
- /* Peripheral not under reset */\r
- I2Cx->CR1 &= CR1_SWRST_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Drives the SMBusAlert pin high or low for the specified I2C.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_SMBusAlert: specifies SMBAlert pin level. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low\r
- * @arg I2C_SMBusAlert_High: SMBAlert pin driven high\r
- * @retval None\r
- */\r
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r
- if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r
- {\r
- /* Drive the SMBusAlert pin Low */\r
- I2Cx->CR1 |= I2C_SMBusAlert_Low;\r
- }\r
- else\r
- {\r
- /* Drive the SMBusAlert pin High */\r
- I2Cx->CR1 &= I2C_SMBusAlert_High;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C PEC transfer.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2C PEC transmission.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C PEC transmission */\r
- I2Cx->CR1 |= CR1_PEC_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C PEC transmission */\r
- I2Cx->CR1 &= CR1_PEC_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the specified I2C PEC position.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_PECPosition: specifies the PEC position. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_PECPosition_Next: indicates that the next byte is PEC\r
- * @arg I2C_PECPosition_Current: indicates that current byte is PEC\r
- * @retval None\r
- */\r
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));\r
- if (I2C_PECPosition == I2C_PECPosition_Next)\r
- {\r
- /* Next byte in shift register is PEC */\r
- I2Cx->CR1 |= I2C_PECPosition_Next;\r
- }\r
- else\r
- {\r
- /* Current byte in shift register is PEC */\r
- I2Cx->CR1 &= I2C_PECPosition_Current;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the PEC value calculation of the transfered bytes.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx PEC value calculation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C PEC calculation */\r
- I2Cx->CR1 |= CR1_ENPEC_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C PEC calculation */\r
- I2Cx->CR1 &= CR1_ENPEC_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the PEC value for the specified I2C.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @retval The PEC value.\r
- */\r
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- /* Return the selected I2C PEC value */\r
- return ((I2Cx->SR2) >> 8);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C ARP.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx ARP. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected I2C ARP */\r
- I2Cx->CR1 |= CR1_ENARP_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C ARP */\r
- I2Cx->CR1 &= CR1_ENARP_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified I2C Clock stretching.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param NewState: new state of the I2Cx Clock stretching.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState == DISABLE)\r
- {\r
- /* Enable the selected I2C Clock stretching */\r
- I2Cx->CR1 |= CR1_NOSTRETCH_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected I2C Clock stretching */\r
- I2Cx->CR1 &= CR1_NOSTRETCH_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the specified I2C fast mode duty cycle.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_DutyCycle: specifies the fast mode duty cycle.\r
- * This parameter can be one of the following values:\r
- * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r
- * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r
- * @retval None\r
- */\r
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r
- if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r
- {\r
- /* I2C fast mode Tlow/Thigh=2 */\r
- I2Cx->CCR &= I2C_DutyCycle_2;\r
- }\r
- else\r
- {\r
- /* I2C fast mode Tlow/Thigh=16/9 */\r
- I2Cx->CCR |= I2C_DutyCycle_16_9;\r
- }\r
-}\r
-\r
-\r
-\r
-/**\r
- * @brief\r
- ****************************************************************************************\r
- *\r
- * I2C State Monitoring Functions\r
- * \r
- **************************************************************************************** \r
- * This I2C driver provides three different ways for I2C state monitoring\r
- * depending on the application requirements and constraints:\r
- * \r
- * \r
- * 1) Basic state monitoring:\r
- * Using I2C_CheckEvent() function:\r
- * It compares the status registers (SR1 and SR2) content to a given event\r
- * (can be the combination of one or more flags).\r
- * It returns SUCCESS if the current status includes the given flags \r
- * and returns ERROR if one or more flags are missing in the current status.\r
- * - When to use:\r
- * - This function is suitable for most applciations as well as for startup \r
- * activity since the events are fully described in the product reference manual \r
- * (RM0008).\r
- * - It is also suitable for users who need to define their own events.\r
- * - Limitations:\r
- * - If an error occurs (ie. error flags are set besides to the monitored flags),\r
- * the I2C_CheckEvent() function may return SUCCESS despite the communication\r
- * hold or corrupted real state. \r
- * In this case, it is advised to use error interrupts to monitor the error\r
- * events and handle them in the interrupt IRQ handler.\r
- * \r
- * @note \r
- * For error management, it is advised to use the following functions:\r
- * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
- * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.\r
- * Where x is the peripheral instance (I2C1, I2C2 ...)\r
- * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() \r
- * in order to determine which error occured.\r
- * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
- * and/or I2C_GenerateStop() in order to clear the error flag and source,\r
- * and return to correct communication status.\r
- * \r
- *\r
- * 2) Advanced state monitoring:\r
- * Using the function I2C_GetLastEvent() which returns the image of both status \r
- * registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
- * by 16 bits and concatenated to Status Register 1).\r
- * - When to use:\r
- * - This function is suitable for the same applications above but it allows to\r
- * overcome the mentionned limitation of I2C_GetFlagStatus() function.\r
- * The returned value could be compared to events already defined in the \r
- * library (stm32f10x_i2c.h) or to custom values defiend by user.\r
- * - This function is suitable when multiple flags are monitored at the same time.\r
- * - At the opposite of I2C_CheckEvent() function, this function allows user to\r
- * choose when an event is accepted (when all events flags are set and no \r
- * other flags are set or just when the needed flags are set like \r
- * I2C_CheckEvent() function).\r
- * - Limitations:\r
- * - User may need to define his own events.\r
- * - Same remark concerning the error management is applicable for this \r
- * function if user decides to check only regular communication flags (and \r
- * ignores error flags).\r
- * \r
- *\r
- * 3) Flag-based state monitoring:\r
- * Using the function I2C_GetFlagStatus() which simply returns the status of \r
- * one single flag (ie. I2C_FLAG_RXNE ...). \r
- * - When to use:\r
- * - This function could be used for specific applications or in debug phase.\r
- * - It is suitable when only one flag checking is needed (most I2C events \r
- * are monitored through multiple flags).\r
- * - Limitations: \r
- * - When calling this function, the Status register is accessed. Some flags are\r
- * cleared when the status register is accessed. So checking the status\r
- * of one Flag, may clear other ones.\r
- * - Function may need to be called twice or more in order to monitor one \r
- * single event.\r
- *\r
- * For detailed description of Events, please refer to section I2C_Events in \r
- * stm32f10x_i2c.h file.\r
- * \r
- */\r
-\r
-/**\r
- * \r
- * 1) Basic state monitoring\r
- *******************************************************************************\r
- */\r
-\r
-/**\r
- * @brief Checks whether the last I2Cx Event is equal to the one passed\r
- * as parameter.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_EVENT: specifies the event to be checked. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1\r
- * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2\r
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2\r
- * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2\r
- * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3\r
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3\r
- * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3\r
- * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2\r
- * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4\r
- * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5\r
- * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 \r
- * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6\r
- * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7\r
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8\r
- * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2\r
- * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9\r
- * \r
- * @note: For detailed description of Events, please refer to section \r
- * I2C_Events in stm32f10x_i2c.h file.\r
- * \r
- * @retval An ErrorStatus enumuration value:\r
- * - SUCCESS: Last event is equal to the I2C_EVENT\r
- * - ERROR: Last event is different from the I2C_EVENT\r
- */\r
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)\r
-{\r
- uint32_t lastevent = 0;\r
- uint32_t flag1 = 0, flag2 = 0;\r
- ErrorStatus status = ERROR;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_EVENT(I2C_EVENT));\r
-\r
- /* Read the I2Cx status register */\r
- flag1 = I2Cx->SR1;\r
- flag2 = I2Cx->SR2;\r
- flag2 = flag2 << 16;\r
-\r
- /* Get the last event value from I2C status register */\r
- lastevent = (flag1 | flag2) & FLAG_Mask;\r
-\r
- /* Check whether the last event contains the I2C_EVENT */\r
- if ((lastevent & I2C_EVENT) == I2C_EVENT)\r
- {\r
- /* SUCCESS: last event is equal to I2C_EVENT */\r
- status = SUCCESS;\r
- }\r
- else\r
- {\r
- /* ERROR: last event is different from I2C_EVENT */\r
- status = ERROR;\r
- }\r
- /* Return status */\r
- return status;\r
-}\r
-\r
-/**\r
- * \r
- * 2) Advanced state monitoring\r
- *******************************************************************************\r
- */\r
-\r
-/**\r
- * @brief Returns the last I2Cx Event.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * \r
- * @note: For detailed description of Events, please refer to section \r
- * I2C_Events in stm32f10x_i2c.h file.\r
- * \r
- * @retval The last event\r
- */\r
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r
-{\r
- uint32_t lastevent = 0;\r
- uint32_t flag1 = 0, flag2 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
-\r
- /* Read the I2Cx status register */\r
- flag1 = I2Cx->SR1;\r
- flag2 = I2Cx->SR2;\r
- flag2 = flag2 << 16;\r
-\r
- /* Get the last event value from I2C status register */\r
- lastevent = (flag1 | flag2) & FLAG_Mask;\r
-\r
- /* Return status */\r
- return lastevent;\r
-}\r
-\r
-/**\r
- * \r
- * 3) Flag-based state monitoring\r
- *******************************************************************************\r
- */\r
-\r
-/**\r
- * @brief Checks whether the specified I2C flag is set or not.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_FLAG: specifies the flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)\r
- * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r
- * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)\r
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag\r
- * @arg I2C_FLAG_BUSY: Bus busy flag\r
- * @arg I2C_FLAG_MSL: Master/Slave flag\r
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_FLAG_AF: Acknowledge failure flag\r
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_FLAG_BERR: Bus error flag\r
- * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)\r
- * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r
- * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
- * @arg I2C_FLAG_BTF: Byte transfer finished flag\r
- * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) \93ADSL\94\r
- * Address matched flag (Slave mode)\94ENDAD\94\r
- * @arg I2C_FLAG_SB: Start bit flag (Master mode)\r
- * @retval The new state of I2C_FLAG (SET or RESET).\r
- */\r
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- __IO uint32_t i2creg = 0, i2cxbase = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r
-\r
- /* Get the I2Cx peripheral base address */\r
- i2cxbase = (uint32_t)I2Cx;\r
- \r
- /* Read flag register index */\r
- i2creg = I2C_FLAG >> 28;\r
- \r
- /* Get bit[23:0] of the flag */\r
- I2C_FLAG &= FLAG_Mask;\r
- \r
- if(i2creg != 0)\r
- {\r
- /* Get the I2Cx SR1 register address */\r
- i2cxbase += 0x14;\r
- }\r
- else\r
- {\r
- /* Flag in I2Cx SR2 Register */\r
- I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);\r
- /* Get the I2Cx SR2 register address */\r
- i2cxbase += 0x18;\r
- }\r
- \r
- if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)\r
- {\r
- /* I2C_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* I2C_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- \r
- /* Return the I2C_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-\r
-\r
-/**\r
- * @brief Clears the I2Cx's pending flags.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_FLAG: specifies the flag to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_FLAG_AF: Acknowledge failure flag\r
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_FLAG_BERR: Bus error flag\r
- * \r
- * @note\r
- * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
- * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation \r
- * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
- * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
- * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the \r
- * second byte of the address in DR register.\r
- * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
- * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a \r
- * read/write to I2C_DR register (I2C_SendData()).\r
- * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to \r
- * I2C_SR2 register ((void)(I2Cx->SR2)).\r
- * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1\r
- * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR\r
- * register (I2C_SendData()).\r
- * @retval None\r
- */\r
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
-{\r
- uint32_t flagpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
- /* Get the I2C flag position */\r
- flagpos = I2C_FLAG & FLAG_Mask;\r
- /* Clear the selected I2C flag */\r
- I2Cx->SR1 = (uint16_t)~flagpos;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified I2C interrupt has occurred or not.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg I2C_IT_SMBALERT: SMBus Alert flag\r
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
- * @arg I2C_IT_PECERR: PEC error in reception flag\r
- * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
- * @arg I2C_IT_AF: Acknowledge failure flag\r
- * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
- * @arg I2C_IT_BERR: Bus error flag\r
- * @arg I2C_IT_TXE: Data register empty flag (Transmitter)\r
- * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag\r
- * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)\r
- * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
- * @arg I2C_IT_BTF: Byte transfer finished flag\r
- * @arg I2C_IT_ADDR: Address sent flag (Master mode) \93ADSL\94\r
- * Address matched flag (Slave mode)\94ENDAD\94\r
- * @arg I2C_IT_SB: Start bit flag (Master mode)\r
- * @retval The new state of I2C_IT (SET or RESET).\r
- */\r
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint32_t enablestatus = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_GET_IT(I2C_IT));\r
-\r
- /* Check if the interrupt source is enabled or not */\r
- enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;\r
- \r
- /* Get bit[23:0] of the flag */\r
- I2C_IT &= FLAG_Mask;\r
-\r
- /* Check the status of the specified I2C flag */\r
- if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)\r
- {\r
- /* I2C_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* I2C_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the I2C_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the I2Cx\92s interrupt pending bits.\r
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
- * @param I2C_IT: specifies the interrupt pending bit to clear. \r
- * This parameter can be any combination of the following values:\r
- * @arg I2C_IT_SMBALERT: SMBus Alert interrupt\r
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt\r
- * @arg I2C_IT_PECERR: PEC error in reception interrupt\r
- * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)\r
- * @arg I2C_IT_AF: Acknowledge failure interrupt\r
- * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)\r
- * @arg I2C_IT_BERR: Bus error interrupt\r
- * \r
- * @note\r
- * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
- * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
- * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
- * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
- * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second \r
- * byte of the address in I2C_DR register.\r
- * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
- * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a \r
- * read/write to I2C_DR register (I2C_SendData()).\r
- * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to \r
- * I2C_SR2 register ((void)(I2Cx->SR2)).\r
- * - SB (Start Bit) is cleared by software sequence: a read operation to \r
- * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
- * I2C_DR register (I2C_SendData()).\r
- * @retval None\r
- */\r
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
-{\r
- uint32_t flagpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r
- /* Get the I2C flag position */\r
- flagpos = I2C_IT & FLAG_Mask;\r
- /* Clear the selected I2C flag */\r
- I2Cx->SR1 = (uint16_t)~flagpos;\r
-}\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_iwdg.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the IWDG firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_iwdg.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup IWDG \r
- * @brief IWDG driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup IWDG_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Private_Defines\r
- * @{\r
- */ \r
-\r
-/* ---------------------- IWDG registers bit mask ----------------------------*/\r
-\r
-/* KR register bit mask */\r
-#define KR_KEY_Reload ((uint16_t)0xAAAA)\r
-#define KR_KEY_Enable ((uint16_t)0xCCCC)\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup IWDG_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup IWDG_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.\r
- * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers\r
- * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers\r
- * @retval None\r
- */\r
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r
- IWDG->KR = IWDG_WriteAccess;\r
-}\r
-\r
-/**\r
- * @brief Sets IWDG Prescaler value.\r
- * @param IWDG_Prescaler: specifies the IWDG Prescaler value.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_Prescaler_4: IWDG prescaler set to 4\r
- * @arg IWDG_Prescaler_8: IWDG prescaler set to 8\r
- * @arg IWDG_Prescaler_16: IWDG prescaler set to 16\r
- * @arg IWDG_Prescaler_32: IWDG prescaler set to 32\r
- * @arg IWDG_Prescaler_64: IWDG prescaler set to 64\r
- * @arg IWDG_Prescaler_128: IWDG prescaler set to 128\r
- * @arg IWDG_Prescaler_256: IWDG prescaler set to 256\r
- * @retval None\r
- */\r
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));\r
- IWDG->PR = IWDG_Prescaler;\r
-}\r
-\r
-/**\r
- * @brief Sets IWDG Reload value.\r
- * @param Reload: specifies the IWDG Reload value.\r
- * This parameter must be a number between 0 and 0x0FFF.\r
- * @retval None\r
- */\r
-void IWDG_SetReload(uint16_t Reload)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_RELOAD(Reload));\r
- IWDG->RLR = Reload;\r
-}\r
-\r
-/**\r
- * @brief Reloads IWDG counter with value defined in the reload register\r
- * (write access to IWDG_PR and IWDG_RLR registers disabled).\r
- * @param None\r
- * @retval None\r
- */\r
-void IWDG_ReloadCounter(void)\r
-{\r
- IWDG->KR = KR_KEY_Reload;\r
-}\r
-\r
-/**\r
- * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).\r
- * @param None\r
- * @retval None\r
- */\r
-void IWDG_Enable(void)\r
-{\r
- IWDG->KR = KR_KEY_Enable;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified IWDG flag is set or not.\r
- * @param IWDG_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg IWDG_FLAG_PVU: Prescaler Value Update on going\r
- * @arg IWDG_FLAG_RVU: Reload Value Update on going\r
- * @retval The new state of IWDG_FLAG (SET or RESET).\r
- */\r
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_IWDG_FLAG(IWDG_FLAG));\r
- if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_pwr.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the PWR firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_pwr.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup PWR \r
- * @brief PWR driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup PWR_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Private_Defines\r
- * @{\r
- */\r
-\r
-/* --------- PWR registers bit address in the alias region ---------- */\r
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
-\r
-/* --- CR Register ---*/\r
-\r
-/* Alias word address of DBP bit */\r
-#define CR_OFFSET (PWR_OFFSET + 0x00)\r
-#define DBP_BitNumber 0x08\r
-#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
-\r
-/* Alias word address of PVDE bit */\r
-#define PVDE_BitNumber 0x04\r
-#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
-\r
-/* --- CSR Register ---*/\r
-\r
-/* Alias word address of EWUP bit */\r
-#define CSR_OFFSET (PWR_OFFSET + 0x04)\r
-#define EWUP_BitNumber 0x08\r
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
-\r
-/* ------------------ PWR registers bit mask ------------------------ */\r
-\r
-/* CR register bit mask */\r
-#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r
-#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)\r
-\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup PWR_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void PWR_DeInit(void)\r
-{\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables access to the RTC and backup registers.\r
- * @param NewState: new state of the access to the RTC and backup registers.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_BackupAccessCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the Power Voltage Detector(PVD).\r
- * @param NewState: new state of the PVD.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_PVDCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
- * @param PWR_PVDLevel: specifies the PVD detection level\r
- * This parameter can be one of the following values:\r
- * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V\r
- * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V\r
- * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V\r
- * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V\r
- * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V\r
- * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V\r
- * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V\r
- * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V\r
- * @retval None\r
- */\r
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
- tmpreg = PWR->CR;\r
- /* Clear PLS[7:5] bits */\r
- tmpreg &= CR_PLS_MASK;\r
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
- tmpreg |= PWR_PVDLevel;\r
- /* Store the new value */\r
- PWR->CR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the WakeUp Pin functionality.\r
- * @param NewState: new state of the WakeUp Pin functionality.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void PWR_WakeUpPinCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enters STOP mode.\r
- * @param PWR_Regulator: specifies the regulator state in STOP mode.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_Regulator_ON: STOP mode with regulator ON\r
- * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
- * @retval None\r
- */\r
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
- \r
- /* Select the regulator state in STOP mode ---------------------------------*/\r
- tmpreg = PWR->CR;\r
- /* Clear PDDS and LPDS bits */\r
- tmpreg &= CR_DS_MASK;\r
- /* Set LPDS bit according to PWR_Regulator value */\r
- tmpreg |= PWR_Regulator;\r
- /* Store the new value */\r
- PWR->CR = tmpreg;\r
- /* Set SLEEPDEEP bit of Cortex System Control Register */\r
- SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
- \r
- /* Select STOP mode entry --------------------------------------------------*/\r
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
- { \r
- /* Request Wait For Interrupt */\r
- __WFI();\r
- }\r
- else\r
- {\r
- /* Request Wait For Event */\r
- __WFE();\r
- }\r
- \r
- /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); \r
-}\r
-\r
-/**\r
- * @brief Enters STANDBY mode.\r
- * @param None\r
- * @retval None\r
- */\r
-void PWR_EnterSTANDBYMode(void)\r
-{\r
- /* Clear Wake-up flag */\r
- PWR->CR |= PWR_CR_CWUF;\r
- /* Select STANDBY mode */\r
- PWR->CR |= PWR_CR_PDDS;\r
- /* Set SLEEPDEEP bit of Cortex System Control Register */\r
- SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
-/* This option is used to ensure that store operations are completed */\r
-#if defined ( __CC_ARM )\r
- __force_stores();\r
-#endif\r
- /* Request Wait For Interrupt */\r
- __WFI();\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified PWR flag is set or not.\r
- * @param PWR_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_FLAG_WU: Wake Up flag\r
- * @arg PWR_FLAG_SB: StandBy flag\r
- * @arg PWR_FLAG_PVDO: PVD Output\r
- * @retval The new state of PWR_FLAG (SET or RESET).\r
- */\r
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
- \r
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- /* Return the flag status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the PWR's pending flags.\r
- * @param PWR_FLAG: specifies the flag to clear.\r
- * This parameter can be one of the following values:\r
- * @arg PWR_FLAG_WU: Wake Up flag\r
- * @arg PWR_FLAG_SB: StandBy flag\r
- * @retval None\r
- */\r
-void PWR_ClearFlag(uint32_t PWR_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
- \r
- PWR->CR |= PWR_FLAG << 2;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_rtc.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the RTC firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_rtc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup RTC \r
- * @brief RTC driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup RTC_Private_TypesDefinitions\r
- * @{\r
- */ \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Private_Defines\r
- * @{\r
- */\r
-#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */\r
-#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup RTC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Enables or disables the specified RTC interrupts.\r
- * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg RTC_IT_OW: Overflow interrupt\r
- * @arg RTC_IT_ALR: Alarm interrupt\r
- * @arg RTC_IT_SEC: Second interrupt\r
- * @param NewState: new state of the specified RTC interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_IT(RTC_IT)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- RTC->CRH |= RTC_IT;\r
- }\r
- else\r
- {\r
- RTC->CRH &= (uint16_t)~RTC_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enters the RTC configuration mode.\r
- * @param None\r
- * @retval None\r
- */\r
-void RTC_EnterConfigMode(void)\r
-{\r
- /* Set the CNF flag to enter in the Configuration Mode */\r
- RTC->CRL |= RTC_CRL_CNF;\r
-}\r
-\r
-/**\r
- * @brief Exits from the RTC configuration mode.\r
- * @param None\r
- * @retval None\r
- */\r
-void RTC_ExitConfigMode(void)\r
-{\r
- /* Reset the CNF flag to exit from the Configuration Mode */\r
- RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); \r
-}\r
-\r
-/**\r
- * @brief Gets the RTC counter value.\r
- * @param None\r
- * @retval RTC counter value.\r
- */\r
-uint32_t RTC_GetCounter(void)\r
-{\r
- uint16_t tmp = 0;\r
- tmp = RTC->CNTL;\r
- return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;\r
-}\r
-\r
-/**\r
- * @brief Sets the RTC counter value.\r
- * @param CounterValue: RTC counter new value.\r
- * @retval None\r
- */\r
-void RTC_SetCounter(uint32_t CounterValue)\r
-{ \r
- RTC_EnterConfigMode();\r
- /* Set RTC COUNTER MSB word */\r
- RTC->CNTH = CounterValue >> 16;\r
- /* Set RTC COUNTER LSB word */\r
- RTC->CNTL = (CounterValue & RTC_LSB_MASK);\r
- RTC_ExitConfigMode();\r
-}\r
-\r
-/**\r
- * @brief Sets the RTC prescaler value.\r
- * @param PrescalerValue: RTC prescaler new value.\r
- * @retval None\r
- */\r
-void RTC_SetPrescaler(uint32_t PrescalerValue)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_PRESCALER(PrescalerValue));\r
- \r
- RTC_EnterConfigMode();\r
- /* Set RTC PRESCALER MSB word */\r
- RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;\r
- /* Set RTC PRESCALER LSB word */\r
- RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);\r
- RTC_ExitConfigMode();\r
-}\r
-\r
-/**\r
- * @brief Sets the RTC alarm value.\r
- * @param AlarmValue: RTC alarm new value.\r
- * @retval None\r
- */\r
-void RTC_SetAlarm(uint32_t AlarmValue)\r
-{ \r
- RTC_EnterConfigMode();\r
- /* Set the ALARM MSB word */\r
- RTC->ALRH = AlarmValue >> 16;\r
- /* Set the ALARM LSB word */\r
- RTC->ALRL = (AlarmValue & RTC_LSB_MASK);\r
- RTC_ExitConfigMode();\r
-}\r
-\r
-/**\r
- * @brief Gets the RTC divider value.\r
- * @param None\r
- * @retval RTC Divider value.\r
- */\r
-uint32_t RTC_GetDivider(void)\r
-{\r
- uint32_t tmp = 0x00;\r
- tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;\r
- tmp |= RTC->DIVL;\r
- return tmp;\r
-}\r
-\r
-/**\r
- * @brief Waits until last write operation on RTC registers has finished.\r
- * @note This function must be called before any write to RTC registers.\r
- * @param None\r
- * @retval None\r
- */\r
-void RTC_WaitForLastTask(void)\r
-{\r
- /* Loop until RTOFF flag is set */\r
- while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)\r
- {\r
- }\r
-}\r
-\r
-/**\r
- * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)\r
- * are synchronized with RTC APB clock.\r
- * @note This function must be called before any read operation after an APB reset\r
- * or an APB clock stop.\r
- * @param None\r
- * @retval None\r
- */\r
-void RTC_WaitForSynchro(void)\r
-{\r
- /* Clear RSF flag */\r
- RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;\r
- /* Loop until RSF flag is set */\r
- while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)\r
- {\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RTC flag is set or not.\r
- * @param RTC_FLAG: specifies the flag to check.\r
- * This parameter can be one the following values:\r
- * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag\r
- * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
- * @arg RTC_FLAG_OW: Overflow flag\r
- * @arg RTC_FLAG_ALR: Alarm flag\r
- * @arg RTC_FLAG_SEC: Second flag\r
- * @retval The new state of RTC_FLAG (SET or RESET).\r
- */\r
-FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); \r
- \r
- if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RTC\92s pending flags.\r
- * @param RTC_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after\r
- * an APB reset or an APB Clock stop.\r
- * @arg RTC_FLAG_OW: Overflow flag\r
- * @arg RTC_FLAG_ALR: Alarm flag\r
- * @arg RTC_FLAG_SEC: Second flag\r
- * @retval None\r
- */\r
-void RTC_ClearFlag(uint16_t RTC_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); \r
- \r
- /* Clear the coressponding RTC flag */\r
- RTC->CRL &= (uint16_t)~RTC_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified RTC interrupt has occured or not.\r
- * @param RTC_IT: specifies the RTC interrupts sources to check.\r
- * This parameter can be one of the following values:\r
- * @arg RTC_IT_OW: Overflow interrupt\r
- * @arg RTC_IT_ALR: Alarm interrupt\r
- * @arg RTC_IT_SEC: Second interrupt\r
- * @retval The new state of the RTC_IT (SET or RESET).\r
- */\r
-ITStatus RTC_GetITStatus(uint16_t RTC_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_RTC_GET_IT(RTC_IT)); \r
- \r
- bitstatus = (ITStatus)(RTC->CRL & RTC_IT);\r
- if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the RTC\92s interrupt pending bits.\r
- * @param RTC_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg RTC_IT_OW: Overflow interrupt\r
- * @arg RTC_IT_ALR: Alarm interrupt\r
- * @arg RTC_IT_SEC: Second interrupt\r
- * @retval None\r
- */\r
-void RTC_ClearITPendingBit(uint16_t RTC_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_RTC_IT(RTC_IT)); \r
- \r
- /* Clear the coressponding RTC pending bit */\r
- RTC->CRL &= (uint16_t)~RTC_IT;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_sdio.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the SDIO firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_sdio.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup SDIO \r
- * @brief SDIO driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup SDIO_Private_TypesDefinitions\r
- * @{\r
- */ \r
-\r
-/* ------------ SDIO registers bit address in the alias region ----------- */\r
-#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)\r
-\r
-/* --- CLKCR Register ---*/\r
-\r
-/* Alias word address of CLKEN bit */\r
-#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)\r
-#define CLKEN_BitNumber 0x08\r
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))\r
-\r
-/* --- CMD Register ---*/\r
-\r
-/* Alias word address of SDIOSUSPEND bit */\r
-#define CMD_OFFSET (SDIO_OFFSET + 0x0C)\r
-#define SDIOSUSPEND_BitNumber 0x0B\r
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))\r
-\r
-/* Alias word address of ENCMDCOMPL bit */\r
-#define ENCMDCOMPL_BitNumber 0x0C\r
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))\r
-\r
-/* Alias word address of NIEN bit */\r
-#define NIEN_BitNumber 0x0D\r
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))\r
-\r
-/* Alias word address of ATACMD bit */\r
-#define ATACMD_BitNumber 0x0E\r
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))\r
-\r
-/* --- DCTRL Register ---*/\r
-\r
-/* Alias word address of DMAEN bit */\r
-#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)\r
-#define DMAEN_BitNumber 0x03\r
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))\r
-\r
-/* Alias word address of RWSTART bit */\r
-#define RWSTART_BitNumber 0x08\r
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))\r
-\r
-/* Alias word address of RWSTOP bit */\r
-#define RWSTOP_BitNumber 0x09\r
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))\r
-\r
-/* Alias word address of RWMOD bit */\r
-#define RWMOD_BitNumber 0x0A\r
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))\r
-\r
-/* Alias word address of SDIOEN bit */\r
-#define SDIOEN_BitNumber 0x0B\r
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))\r
-\r
-/* ---------------------- SDIO registers bit mask ------------------------ */\r
-\r
-/* --- CLKCR Register ---*/\r
-\r
-/* CLKCR register clear mask */\r
-#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) \r
-\r
-/* --- PWRCTRL Register ---*/\r
-\r
-/* SDIO PWRCTRL Mask */\r
-#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)\r
-\r
-/* --- DCTRL Register ---*/\r
-\r
-/* SDIO DCTRL Clear Mask */\r
-#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)\r
-\r
-/* --- CMD Register ---*/\r
-\r
-/* CMD Register clear mask */\r
-#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)\r
-\r
-/* SDIO RESP Registers Address */\r
-#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Private_Defines\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SDIO_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the SDIO peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void SDIO_DeInit(void)\r
-{\r
- SDIO->POWER = 0x00000000;\r
- SDIO->CLKCR = 0x00000000;\r
- SDIO->ARG = 0x00000000;\r
- SDIO->CMD = 0x00000000;\r
- SDIO->DTIMER = 0x00000000;\r
- SDIO->DLEN = 0x00000000;\r
- SDIO->DCTRL = 0x00000000;\r
- SDIO->ICR = 0x00C007FF;\r
- SDIO->MASK = 0x00000000;\r
-}\r
-\r
-/**\r
- * @brief Initializes the SDIO peripheral according to the specified \r
- * parameters in the SDIO_InitStruct.\r
- * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure \r
- * that contains the configuration information for the SDIO peripheral.\r
- * @retval None\r
- */\r
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));\r
- assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));\r
- assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));\r
- assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));\r
- assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); \r
- \r
-/*---------------------------- SDIO CLKCR Configuration ------------------------*/ \r
- /* Get the SDIO CLKCR value */\r
- tmpreg = SDIO->CLKCR;\r
- \r
- /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */\r
- tmpreg &= CLKCR_CLEAR_MASK;\r
- \r
- /* Set CLKDIV bits according to SDIO_ClockDiv value */\r
- /* Set PWRSAV bit according to SDIO_ClockPowerSave value */\r
- /* Set BYPASS bit according to SDIO_ClockBypass value */\r
- /* Set WIDBUS bits according to SDIO_BusWide value */\r
- /* Set NEGEDGE bits according to SDIO_ClockEdge value */\r
- /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */\r
- tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |\r
- SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |\r
- SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); \r
- \r
- /* Write to SDIO CLKCR */\r
- SDIO->CLKCR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each SDIO_InitStruct member with its default value.\r
- * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which \r
- * will be initialized.\r
- * @retval None\r
- */\r
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)\r
-{\r
- /* SDIO_InitStruct members default value */\r
- SDIO_InitStruct->SDIO_ClockDiv = 0x00;\r
- SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;\r
- SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;\r
- SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;\r
- SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;\r
- SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SDIO Clock.\r
- * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_ClockCmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Sets the power status of the controller.\r
- * @param SDIO_PowerState: new state of the Power state. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_PowerState_OFF\r
- * @arg SDIO_PowerState_ON\r
- * @retval None\r
- */\r
-void SDIO_SetPowerState(uint32_t SDIO_PowerState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));\r
- \r
- SDIO->POWER &= PWR_PWRCTRL_MASK;\r
- SDIO->POWER |= SDIO_PowerState;\r
-}\r
-\r
-/**\r
- * @brief Gets the power status of the controller.\r
- * @param None\r
- * @retval Power status of the controller. The returned value can\r
- * be one of the following:\r
- * - 0x00: Power OFF\r
- * - 0x02: Power UP\r
- * - 0x03: Power ON \r
- */\r
-uint32_t SDIO_GetPowerState(void)\r
-{\r
- return (SDIO->POWER & (~PWR_PWRCTRL_MASK));\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SDIO interrupts.\r
- * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.\r
- * This parameter can be one or a combination of the following values:\r
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode interrupt\r
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r
- * @param NewState: new state of the specified SDIO interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None \r
- */\r
-void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_IT(SDIO_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the SDIO interrupts */\r
- SDIO->MASK |= SDIO_IT;\r
- }\r
- else\r
- {\r
- /* Disable the SDIO interrupts */\r
- SDIO->MASK &= ~SDIO_IT;\r
- } \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SDIO DMA request.\r
- * @param NewState: new state of the selected SDIO DMA request.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_DMACmd(FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Initializes the SDIO Command according to the specified \r
- * parameters in the SDIO_CmdInitStruct and send the command.\r
- * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef \r
- * structure that contains the configuration information for the SDIO command.\r
- * @retval None\r
- */\r
-void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));\r
- assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));\r
- assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));\r
- assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));\r
- \r
-/*---------------------------- SDIO ARG Configuration ------------------------*/\r
- /* Set the SDIO Argument value */\r
- SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;\r
- \r
-/*---------------------------- SDIO CMD Configuration ------------------------*/ \r
- /* Get the SDIO CMD value */\r
- tmpreg = SDIO->CMD;\r
- /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */\r
- tmpreg &= CMD_CLEAR_MASK;\r
- /* Set CMDINDEX bits according to SDIO_CmdIndex value */\r
- /* Set WAITRESP bits according to SDIO_Response value */\r
- /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */\r
- /* Set CPSMEN bits according to SDIO_CPSM value */\r
- tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response\r
- | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;\r
- \r
- /* Write to SDIO CMD */\r
- SDIO->CMD = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each SDIO_CmdInitStruct member with its default value.\r
- * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef \r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)\r
-{\r
- /* SDIO_CmdInitStruct members default value */\r
- SDIO_CmdInitStruct->SDIO_Argument = 0x00;\r
- SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;\r
- SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;\r
- SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;\r
- SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;\r
-}\r
-\r
-/**\r
- * @brief Returns command index of last command for which response received.\r
- * @param None\r
- * @retval Returns the command index of the last command response received.\r
- */\r
-uint8_t SDIO_GetCommandResponse(void)\r
-{\r
- return (uint8_t)(SDIO->RESPCMD);\r
-}\r
-\r
-/**\r
- * @brief Returns response received from the card for the last command.\r
- * @param SDIO_RESP: Specifies the SDIO response register. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_RESP1: Response Register 1\r
- * @arg SDIO_RESP2: Response Register 2\r
- * @arg SDIO_RESP3: Response Register 3\r
- * @arg SDIO_RESP4: Response Register 4\r
- * @retval The Corresponding response register value.\r
- */\r
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)\r
-{\r
- __IO uint32_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_RESP(SDIO_RESP));\r
-\r
- tmp = SDIO_RESP_ADDR + SDIO_RESP;\r
- \r
- return (*(__IO uint32_t *) tmp); \r
-}\r
-\r
-/**\r
- * @brief Initializes the SDIO data path according to the specified \r
- * parameters in the SDIO_DataInitStruct.\r
- * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that\r
- * contains the configuration information for the SDIO command.\r
- * @retval None\r
- */\r
-void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
-{\r
- uint32_t tmpreg = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));\r
- assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));\r
- assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));\r
- assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));\r
- assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));\r
-\r
-/*---------------------------- SDIO DTIMER Configuration ---------------------*/\r
- /* Set the SDIO Data TimeOut value */\r
- SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;\r
-\r
-/*---------------------------- SDIO DLEN Configuration -----------------------*/\r
- /* Set the SDIO DataLength value */\r
- SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;\r
-\r
-/*---------------------------- SDIO DCTRL Configuration ----------------------*/ \r
- /* Get the SDIO DCTRL value */\r
- tmpreg = SDIO->DCTRL;\r
- /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */\r
- tmpreg &= DCTRL_CLEAR_MASK;\r
- /* Set DEN bit according to SDIO_DPSM value */\r
- /* Set DTMODE bit according to SDIO_TransferMode value */\r
- /* Set DTDIR bit according to SDIO_TransferDir value */\r
- /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */\r
- tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir\r
- | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;\r
-\r
- /* Write to SDIO DCTRL */\r
- SDIO->DCTRL = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each SDIO_DataInitStruct member with its default value.\r
- * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which\r
- * will be initialized.\r
- * @retval None\r
- */\r
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
-{\r
- /* SDIO_DataInitStruct members default value */\r
- SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;\r
- SDIO_DataInitStruct->SDIO_DataLength = 0x00;\r
- SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;\r
- SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;\r
- SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; \r
- SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;\r
-}\r
-\r
-/**\r
- * @brief Returns number of remaining data bytes to be transferred.\r
- * @param None\r
- * @retval Number of remaining data bytes to be transferred\r
- */\r
-uint32_t SDIO_GetDataCounter(void)\r
-{ \r
- return SDIO->DCOUNT;\r
-}\r
-\r
-/**\r
- * @brief Read one data word from Rx FIFO.\r
- * @param None\r
- * @retval Data received\r
- */\r
-uint32_t SDIO_ReadData(void)\r
-{ \r
- return SDIO->FIFO;\r
-}\r
-\r
-/**\r
- * @brief Write one data word to Tx FIFO.\r
- * @param Data: 32-bit data word to write.\r
- * @retval None\r
- */\r
-void SDIO_WriteData(uint32_t Data)\r
-{ \r
- SDIO->FIFO = Data;\r
-}\r
-\r
-/**\r
- * @brief Returns the number of words left to be written to or read from FIFO. \r
- * @param None\r
- * @retval Remaining number of words.\r
- */\r
-uint32_t SDIO_GetFIFOCount(void)\r
-{ \r
- return SDIO->FIFOCNT;\r
-}\r
-\r
-/**\r
- * @brief Starts the SD I/O Read Wait operation. \r
- * @param NewState: new state of the Start SDIO Read Wait operation. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_StartSDIOReadWait(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;\r
-}\r
-\r
-/**\r
- * @brief Stops the SD I/O Read Wait operation. \r
- * @param NewState: new state of the Stop SDIO Read Wait operation. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_StopSDIOReadWait(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;\r
-}\r
-\r
-/**\r
- * @brief Sets one of the two options of inserting read wait interval.\r
- * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.\r
- * This parametre can be:\r
- * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK\r
- * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2\r
- * @retval None\r
- */\r
-void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));\r
- \r
- *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SD I/O Mode Operation.\r
- * @param NewState: new state of SDIO specific operation. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_SetSDIOOperation(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SD I/O Mode suspend command sending.\r
- * @param NewState: new state of the SD I/O Mode suspend command.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the command completion signal.\r
- * @param NewState: new state of command completion signal. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_CommandCompletionCmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the CE-ATA interrupt.\r
- * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_CEATAITCmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));\r
-}\r
-\r
-/**\r
- * @brief Sends CE-ATA command (CMD61).\r
- * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SDIO_SendCEATACmd(FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SDIO flag is set or not.\r
- * @param SDIO_FLAG: specifies the flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode.\r
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress\r
- * @arg SDIO_FLAG_TXACT: Data transmit in progress\r
- * @arg SDIO_FLAG_RXACT: Data receive in progress\r
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full\r
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full\r
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full\r
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty\r
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty\r
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO\r
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO\r
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r
- * @retval The new state of SDIO_FLAG (SET or RESET).\r
- */\r
-FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)\r
-{ \r
- FlagStatus bitstatus = RESET;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_FLAG(SDIO_FLAG));\r
- \r
- if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SDIO's pending flags.\r
- * @param SDIO_FLAG: specifies the flag to clear. \r
- * This parameter can be one or a combination of the following values:\r
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode\r
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r
- * @retval None\r
- */\r
-void SDIO_ClearFlag(uint32_t SDIO_FLAG)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));\r
- \r
- SDIO->ICR = SDIO_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SDIO interrupt has occurred or not.\r
- * @param SDIO_IT: specifies the SDIO interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode interrupt\r
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r
- * @retval The new state of SDIO_IT (SET or RESET).\r
- */\r
-ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)\r
-{ \r
- ITStatus bitstatus = RESET;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_GET_IT(SDIO_IT));\r
- if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) \r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SDIO\92s interrupt pending bits.\r
- * @param SDIO_IT: specifies the interrupt pending bit to clear. \r
- * This parameter can be one or a combination of the following values:\r
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
- * bus mode interrupt\r
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61\r
- * @retval None\r
- */\r
-void SDIO_ClearITPendingBit(uint32_t SDIO_IT)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));\r
- \r
- SDIO->ICR = SDIO_IT;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_spi.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the SPI firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_spi.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup SPI \r
- * @brief SPI driver modules\r
- * @{\r
- */ \r
-\r
-/** @defgroup SPI_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-\r
-/** @defgroup SPI_Private_Defines\r
- * @{\r
- */\r
-\r
-/* SPI SPE mask */\r
-#define CR1_SPE_Set ((uint16_t)0x0040)\r
-#define CR1_SPE_Reset ((uint16_t)0xFFBF)\r
-\r
-/* I2S I2SE mask */\r
-#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)\r
-#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)\r
-\r
-/* SPI CRCNext mask */\r
-#define CR1_CRCNext_Set ((uint16_t)0x1000)\r
-\r
-/* SPI CRCEN mask */\r
-#define CR1_CRCEN_Set ((uint16_t)0x2000)\r
-#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)\r
-\r
-/* SPI SSOE mask */\r
-#define CR2_SSOE_Set ((uint16_t)0x0004)\r
-#define CR2_SSOE_Reset ((uint16_t)0xFFFB)\r
-\r
-/* SPI registers Masks */\r
-#define CR1_CLEAR_Mask ((uint16_t)0x3040)\r
-#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)\r
-\r
-/* SPI or I2S mode selection masks */\r
-#define SPI_Mode_Select ((uint16_t)0xF7FF)\r
-#define I2S_Mode_Select ((uint16_t)0x0800) \r
-\r
-/* I2S clock source selection masks */\r
-#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))\r
-#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))\r
-#define I2S_MUL_MASK ((uint32_t)(0x0000F000))\r
-#define I2S_DIV_MASK ((uint32_t)(0x000000F0))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SPI_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the SPIx peripheral registers to their default\r
- * reset values (Affects also the I2Ss).\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @retval None\r
- */\r
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
-\r
- if (SPIx == SPI1)\r
- {\r
- /* Enable SPI1 reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
- /* Release SPI1 from reset state */\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
- }\r
- else if (SPIx == SPI2)\r
- {\r
- /* Enable SPI2 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
- /* Release SPI2 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
- }\r
- else\r
- {\r
- if (SPIx == SPI3)\r
- {\r
- /* Enable SPI3 reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);\r
- /* Release SPI3 from reset state */\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the SPIx peripheral according to the specified \r
- * parameters in the SPI_InitStruct.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
- * contains the configuration information for the specified SPI peripheral.\r
- * @retval None\r
- */\r
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
-{\r
- uint16_t tmpreg = 0;\r
- \r
- /* check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx)); \r
- \r
- /* Check the SPI parameters */\r
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
- assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
-\r
-/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
- /* Get the SPIx CR1 value */\r
- tmpreg = SPIx->CR1;\r
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
- tmpreg &= CR1_CLEAR_Mask;\r
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
- master/salve mode, CPOL and CPHA */\r
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
- /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
- /* Set LSBFirst bit according to SPI_FirstBit value */\r
- /* Set BR bits according to SPI_BaudRatePrescaler value */\r
- /* Set CPOL bit according to SPI_CPOL value */\r
- /* Set CPHA bit according to SPI_CPHA value */\r
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
- SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
- SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
- SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
- /* Write to SPIx CR1 */\r
- SPIx->CR1 = tmpreg;\r
- \r
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */\r
- SPIx->I2SCFGR &= SPI_Mode_Select; \r
-\r
-/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
- /* Write to SPIx CRCPOLY */\r
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
-}\r
-\r
-/**\r
- * @brief Initializes the SPIx peripheral according to the specified \r
- * parameters in the I2S_InitStruct.\r
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral\r
- * (configured in I2S mode).\r
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that\r
- * contains the configuration information for the specified SPI peripheral\r
- * configured in I2S mode.\r
- * @note\r
- * The function calculates the optimal prescaler needed to obtain the most \r
- * accurate audio frequency (depending on the I2S clock source, the PLL values \r
- * and the product configuration). But in case the prescaler value is greater \r
- * than 511, the default value (0x02) will be configured instead. * \r
- * @retval None\r
- */\r
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)\r
-{\r
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r
- uint32_t tmp = 0;\r
- RCC_ClocksTypeDef RCC_Clocks;\r
- uint32_t sourceclock = 0;\r
- \r
- /* Check the I2S parameters */\r
- assert_param(IS_SPI_23_PERIPH(SPIx));\r
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));\r
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));\r
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));\r
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));\r
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));\r
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); \r
-\r
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; \r
- SPIx->I2SPR = 0x0002;\r
- \r
- /* Get the I2SCFGR register value */\r
- tmpreg = SPIx->I2SCFGR;\r
- \r
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)\r
- {\r
- i2sodd = (uint16_t)0;\r
- i2sdiv = (uint16_t)2; \r
- }\r
- /* If the requested audio frequency is not the default, compute the prescaler */\r
- else\r
- {\r
- /* Check the frame length (For the Prescaler computing) */\r
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)\r
- {\r
- /* Packet length is 16 bits */\r
- packetlength = 1;\r
- }\r
- else\r
- {\r
- /* Packet length is 32 bits */\r
- packetlength = 2;\r
- }\r
-\r
- /* Get the I2S clock source mask depending on the peripheral number */\r
- if(((uint32_t)SPIx) == SPI2_BASE)\r
- {\r
- /* The mask is relative to I2S2 */\r
- tmp = I2S2_CLOCK_SRC;\r
- }\r
- else \r
- {\r
- /* The mask is relative to I2S3 */ \r
- tmp = I2S3_CLOCK_SRC;\r
- }\r
-\r
- /* Check the I2S clock source configuration depending on the Device:\r
- Only Connectivity line devices have the PLL3 VCO clock */\r
-#ifdef STM32F10X_CL\r
- if((RCC->CFGR2 & tmp) != 0)\r
- {\r
- /* Get the configuration bits of RCC PLL3 multiplier */\r
- tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);\r
-\r
- /* Get the value of the PLL3 multiplier */ \r
- if((tmp > 5) && (tmp < 15))\r
- {\r
- /* Multplier is between 8 and 14 (value 15 is forbidden) */\r
- tmp += 2;\r
- }\r
- else\r
- {\r
- if (tmp == 15)\r
- {\r
- /* Multiplier is 20 */\r
- tmp = 20;\r
- }\r
- } \r
- /* Get the PREDIV2 value */\r
- sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);\r
- \r
- /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */\r
- sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); \r
- }\r
- else\r
- {\r
- /* I2S Clock source is System clock: Get System Clock frequency */\r
- RCC_GetClocksFreq(&RCC_Clocks); \r
- \r
- /* Get the source clock value: based on System Clock value */\r
- sourceclock = RCC_Clocks.SYSCLK_Frequency;\r
- } \r
-#else /* STM32F10X_HD */\r
- /* I2S Clock source is System clock: Get System Clock frequency */\r
- RCC_GetClocksFreq(&RCC_Clocks); \r
- \r
- /* Get the source clock value: based on System Clock value */\r
- sourceclock = RCC_Clocks.SYSCLK_Frequency; \r
-#endif /* STM32F10X_CL */ \r
-\r
- /* Compute the Real divider depending on the MCLK output state with a flaoting point */\r
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)\r
- {\r
- /* MCLK output is enabled */\r
- tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
- }\r
- else\r
- {\r
- /* MCLK output is disabled */\r
- tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
- }\r
- \r
- /* Remove the flaoting point */\r
- tmp = tmp / 10; \r
- \r
- /* Check the parity of the divider */\r
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r
- \r
- /* Compute the i2sdiv prescaler */\r
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r
- \r
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r
- i2sodd = (uint16_t) (i2sodd << 8);\r
- }\r
- \r
- /* Test if the divider is 1 or 0 or greater than 0xFF */\r
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))\r
- {\r
- /* Set the default values */\r
- i2sdiv = 2;\r
- i2sodd = 0;\r
- }\r
-\r
- /* Write to SPIx I2SPR register the computed value */\r
- SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); \r
- \r
- /* Configure the I2S with the SPI_InitStruct values */\r
- tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \\r
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \\r
- (uint16_t)I2S_InitStruct->I2S_CPOL))));\r
- \r
- /* Write to SPIx I2SCFGR */ \r
- SPIx->I2SCFGR = tmpreg; \r
-}\r
-\r
-/**\r
- * @brief Fills each SPI_InitStruct member with its default value.\r
- * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
-{\r
-/*--------------- Reset SPI init structure parameters values -----------------*/\r
- /* Initialize the SPI_Direction member */\r
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
- /* initialize the SPI_Mode member */\r
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
- /* initialize the SPI_DataSize member */\r
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
- /* Initialize the SPI_CPOL member */\r
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
- /* Initialize the SPI_CPHA member */\r
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
- /* Initialize the SPI_NSS member */\r
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
- /* Initialize the SPI_BaudRatePrescaler member */\r
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
- /* Initialize the SPI_FirstBit member */\r
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
- /* Initialize the SPI_CRCPolynomial member */\r
- SPI_InitStruct->SPI_CRCPolynomial = 7;\r
-}\r
-\r
-/**\r
- * @brief Fills each I2S_InitStruct member with its default value.\r
- * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.\r
- * @retval None\r
- */\r
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)\r
-{\r
-/*--------------- Reset I2S init structure parameters values -----------------*/\r
- /* Initialize the I2S_Mode member */\r
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;\r
- \r
- /* Initialize the I2S_Standard member */\r
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;\r
- \r
- /* Initialize the I2S_DataFormat member */\r
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;\r
- \r
- /* Initialize the I2S_MCLKOutput member */\r
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;\r
- \r
- /* Initialize the I2S_AudioFreq member */\r
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;\r
- \r
- /* Initialize the I2S_CPOL member */\r
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified SPI peripheral.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI peripheral */\r
- SPIx->CR1 |= CR1_SPE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI peripheral */\r
- SPIx->CR1 &= CR1_SPE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).\r
- * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx peripheral. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_23_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI peripheral (in I2S mode) */\r
- SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI peripheral (in I2S mode) */\r
- SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified SPI/I2S interrupts.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask\r
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask\r
- * @arg SPI_I2S_IT_ERR: Error interrupt mask\r
- * @param NewState: new state of the specified SPI/I2S interrupt.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r
-{\r
- uint16_t itpos = 0, itmask = 0 ;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI/I2S IT index */\r
- itpos = SPI_I2S_IT >> 4;\r
-\r
- /* Set the IT mask */\r
- itmask = (uint16_t)1 << (uint16_t)itpos;\r
-\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI/I2S interrupt */\r
- SPIx->CR2 |= itmask;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI/I2S interrupt */\r
- SPIx->CR2 &= (uint16_t)~itmask;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SPIx/I2Sx DMA interface.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. \r
- * This parameter can be any combination of the following values:\r
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request\r
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request\r
- * @param NewState: new state of the selected SPI/I2S DMA transfer request.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI/I2S DMA requests */\r
- SPIx->CR2 |= SPI_I2S_DMAReq;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI/I2S DMA requests */\r
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @param Data : Data to be transmitted.\r
- * @retval None\r
- */\r
-void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Write in the DR register the data to be sent */\r
- SPIx->DR = Data;\r
-}\r
-\r
-/**\r
- * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. \r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @retval The value of the received data.\r
- */\r
-uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Return the data in the DR register */\r
- return SPIx->DR;\r
-}\r
-\r
-/**\r
- * @brief Configures internally by software the NSS pin for the selected SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally\r
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
- * @retval None\r
- */\r
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
- {\r
- /* Set NSS pin internally by software */\r
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
- }\r
- else\r
- {\r
- /* Reset NSS pin internally by software */\r
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the SS output for the selected SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx SS output. \r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI SS output */\r
- SPIx->CR2 |= CR2_SSOE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI SS output */\r
- SPIx->CR2 &= CR2_SSOE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the data size for the selected SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_DataSize: specifies the SPI data size.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_DataSize_16b: Set data frame format to 16bit\r
- * @arg SPI_DataSize_8b: Set data frame format to 8bit\r
- * @retval None\r
- */\r
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
- /* Clear DFF bit */\r
- SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r
- /* Set new DFF bit value */\r
- SPIx->CR1 |= SPI_DataSize;\r
-}\r
-\r
-/**\r
- * @brief Transmit the SPIx CRC value.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @retval None\r
- */\r
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Enable the selected SPI CRC transmission */\r
- SPIx->CR1 |= CR1_CRCNext_Set;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the CRC value calculation of the transfered bytes.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param NewState: new state of the SPIx CRC value calculation.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected SPI CRC calculation */\r
- SPIx->CR1 |= CR1_CRCEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected SPI CRC calculation */\r
- SPIx->CR1 &= CR1_CRCEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_CRC: specifies the CRC register to be read.\r
- * This parameter can be one of the following values:\r
- * @arg SPI_CRC_Tx: Selects Tx CRC register\r
- * @arg SPI_CRC_Rx: Selects Rx CRC register\r
- * @retval The selected CRC register value..\r
- */\r
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
-{\r
- uint16_t crcreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_CRC(SPI_CRC));\r
- if (SPI_CRC != SPI_CRC_Rx)\r
- {\r
- /* Get the Tx CRC register */\r
- crcreg = SPIx->TXCRCR;\r
- }\r
- else\r
- {\r
- /* Get the Rx CRC register */\r
- crcreg = SPIx->RXCRCR;\r
- }\r
- /* Return the selected CRC register */\r
- return crcreg;\r
-}\r
-\r
-/**\r
- * @brief Returns the CRC Polynomial register value for the specified SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @retval The CRC Polynomial register value.\r
- */\r
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- \r
- /* Return the CRC polynomial register */\r
- return SPIx->CRCPR;\r
-}\r
-\r
-/**\r
- * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.\r
- * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
- * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_Direction_Tx: Selects Tx transmission direction\r
- * @arg SPI_Direction_Rx: Selects Rx receive direction\r
- * @retval None\r
- */\r
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
- if (SPI_Direction == SPI_Direction_Tx)\r
- {\r
- /* Set the Tx only mode */\r
- SPIx->CR1 |= SPI_Direction_Tx;\r
- }\r
- else\r
- {\r
- /* Set the Rx only mode */\r
- SPIx->CR1 &= SPI_Direction_Rx;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SPI/I2S flag is set or not.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
- * @arg SPI_I2S_FLAG_BSY: Busy flag.\r
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r
- * @arg SPI_FLAG_MODF: Mode Fault flag.\r
- * @arg SPI_FLAG_CRCERR: CRC Error flag.\r
- * @arg I2S_FLAG_UDR: Underrun Error flag.\r
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.\r
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r
- */\r
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
- /* Check the status of the specified SPI/I2S flag */\r
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r
- {\r
- /* SPI_I2S_FLAG is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SPI_I2S_FLAG is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SPI_I2S_FLAG status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SPIx CRC Error (CRCERR) flag.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r
- * This function clears only CRCERR flag.\r
- * @note\r
- * - OVR (OverRun error) flag is cleared by software sequence: a read \r
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r
- * - UDR (UnderRun error) flag is cleared by a read operation to \r
- * SPI_SR register (SPI_I2S_GetFlagStatus()).\r
- * - MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r
- * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
- * @retval None\r
- */\r
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r
- \r
- /* Clear the selected SPI CRC Error (CRCERR) flag */\r
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * - 2 or 3 in I2S mode\r
- * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. \r
- * This parameter can be one of the following values:\r
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r
- * @arg SPI_IT_MODF: Mode Fault interrupt.\r
- * @arg SPI_IT_CRCERR: CRC Error interrupt.\r
- * @arg I2S_IT_UDR: Underrun Error interrupt.\r
- * @retval The new state of SPI_I2S_IT (SET or RESET).\r
- */\r
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
-{\r
- ITStatus bitstatus = RESET;\r
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI/I2S IT index */\r
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
-\r
- /* Get the SPI/I2S IT mask */\r
- itmask = SPI_I2S_IT >> 4;\r
-\r
- /* Set the IT mask */\r
- itmask = 0x01 << itmask;\r
-\r
- /* Get the SPI_I2S_IT enable bit status */\r
- enablestatus = (SPIx->CR2 & itmask) ;\r
-\r
- /* Check the status of the specified SPI/I2S interrupt */\r
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
- {\r
- /* SPI_I2S_IT is set */\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- /* SPI_I2S_IT is reset */\r
- bitstatus = RESET;\r
- }\r
- /* Return the SPI_I2S_IT status */\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r
- * @param SPIx: where x can be\r
- * - 1, 2 or 3 in SPI mode \r
- * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.\r
- * This function clears only CRCERR intetrrupt pending bit. \r
- * @note\r
- * - OVR (OverRun Error) interrupt pending bit is cleared by software \r
- * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) \r
- * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
- * - UDR (UnderRun Error) interrupt pending bit is cleared by a read \r
- * operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
- * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
- * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) \r
- * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r
- * the SPI).\r
- * @retval None\r
- */\r
-void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
-{\r
- uint16_t itpos = 0;\r
- /* Check the parameters */\r
- assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
- assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r
-\r
- /* Get the SPI IT index */\r
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
-\r
- /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r
- SPIx->SR = (uint16_t)~itpos;\r
-}\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_tim.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the TIM firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_tim.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup TIM \r
- * @brief TIM driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup TIM_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Defines\r
- * @{\r
- */\r
-\r
-/* ---------------------- TIM registers bit mask ------------------------ */\r
-#define SMCR_ETR_Mask ((uint16_t)0x00FF) \r
-#define CCMR_Offset ((uint16_t)0x0018)\r
-#define CCER_CCE_Set ((uint16_t)0x0001) \r
-#define CCER_CCNE_Set ((uint16_t)0x0004) \r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter);\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup TIM_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_DeInit(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
- \r
- if (TIMx == TIM1)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); \r
- } \r
- else if (TIMx == TIM2)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
- }\r
- else if (TIMx == TIM3)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
- }\r
- else if (TIMx == TIM4)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r
- } \r
- else if (TIMx == TIM5)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);\r
- } \r
- else if (TIMx == TIM6)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r
- } \r
- else if (TIMx == TIM7)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);\r
- } \r
- else if (TIMx == TIM8)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);\r
- }\r
- else if (TIMx == TIM9)\r
- { \r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); \r
- } \r
- else if (TIMx == TIM10)\r
- { \r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); \r
- } \r
- else if (TIMx == TIM11) \r
- { \r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); \r
- } \r
- else if (TIMx == TIM12)\r
- { \r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); \r
- } \r
- else if (TIMx == TIM13) \r
- { \r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); \r
- }\r
- else if (TIMx == TIM14) \r
- { \r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); \r
- } \r
- else if (TIMx == TIM15)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);\r
- } \r
- else if (TIMx == TIM16)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);\r
- } \r
- else\r
- {\r
- if (TIMx == TIM17)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);\r
- } \r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Time Base Unit peripheral according to \r
- * the specified parameters in the TIM_TimeBaseInitStruct.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
- * structure that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
-{\r
- uint16_t tmpcr1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
-\r
- tmpcr1 = TIMx->CR1; \r
-\r
- if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||\r
- (TIMx == TIM4) || (TIMx == TIM5)) \r
- {\r
- /* Select the Counter Mode */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r
- }\r
- \r
- if((TIMx != TIM6) && (TIMx != TIM7))\r
- {\r
- /* Set the clock division */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));\r
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r
- }\r
-\r
- TIMx->CR1 = tmpcr1;\r
-\r
- /* Set the Autoreload value */\r
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
- \r
- /* Set the Prescaler value */\r
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
- \r
- if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) \r
- {\r
- /* Set the Repetition Counter value */\r
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;\r
- }\r
-\r
- /* Generate an update event to reload the Prescaler and the Repetition counter\r
- values immediately */\r
- TIMx->EGR = TIM_PSCReloadMode_Immediate; \r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel1 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmrx = TIMx->CCMR1;\r
- \r
- /* Reset the Output Compare Mode Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));\r
-\r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
- \r
- /* Set the Output State */\r
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||\r
- (TIMx == TIM16)|| (TIMx == TIM17))\r
- {\r
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
- \r
- /* Reset the Output N Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));\r
- /* Set the Output N Polarity */\r
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;\r
- \r
- /* Reset the Output N State */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); \r
- /* Set the Output N State */\r
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;\r
- \r
- /* Reset the Ouput Compare and Output Compare N IDLE State */\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));\r
- \r
- /* Set the Output Idle state */\r
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;\r
- /* Set the Output N Idle state */\r
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;\r
- }\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
- \r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; \r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel2 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
- * the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));\r
- \r
- /* Get the TIMx CCER register value */ \r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmrx = TIMx->CCMR1;\r
- \r
- /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8))\r
- {\r
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
- \r
- /* Reset the Output N Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));\r
- /* Set the Output N Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);\r
- \r
- /* Reset the Output N State */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); \r
- /* Set the Output N State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);\r
- \r
- /* Reset the Ouput Compare and Output Compare N IDLE State */\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));\r
- \r
- /* Set the Output Idle state */\r
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);\r
- /* Set the Output N Idle state */\r
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);\r
- }\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
- \r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel3 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmrx = TIMx->CCMR2;\r
- \r
- /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8))\r
- {\r
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
- \r
- /* Reset the Output N Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));\r
- /* Set the Output N Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);\r
- /* Reset the Output N State */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));\r
- \r
- /* Set the Output N State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);\r
- /* Reset the Ouput Compare and Output Compare N IDLE State */\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));\r
- /* Set the Output Idle state */\r
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);\r
- /* Set the Output N Idle state */\r
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);\r
- }\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
- \r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIMx Channel4 according to the specified\r
- * parameters in the TIM_OCInitStruct.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
- /* Disable the Channel 2: Reset the CC4E Bit */\r
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- /* Get the TIMx CR2 register value */\r
- tmpcr2 = TIMx->CR2;\r
- \r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmrx = TIMx->CCMR2;\r
- \r
- /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));\r
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));\r
- \r
- /* Select the Output Compare Mode */\r
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
- \r
- /* Reset the Output Polarity level */\r
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));\r
- /* Set the Output Compare Polarity */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r
- \r
- /* Set the Output State */\r
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8))\r
- {\r
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
- /* Reset the Ouput Compare IDLE State */\r
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));\r
- /* Set the Output Idle state */\r
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);\r
- }\r
- /* Write to TIMx CR2 */\r
- TIMx->CR2 = tmpcr2;\r
- \r
- /* Write to TIMx CCMR2 */ \r
- TIMx->CCMR2 = tmpccmrx;\r
-\r
- /* Set the Capture Compare Register value */\r
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
- \r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Initializes the TIM peripheral according to the specified\r
- * parameters in the TIM_ICInitStruct.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); \r
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
- (TIMx == TIM4) ||(TIMx == TIM5))\r
- {\r
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
- }\r
- else\r
- {\r
- assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));\r
- }\r
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
- {\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
- {\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
- {\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- /* TI3 Configuration */\r
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else\r
- {\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- /* TI4 Configuration */\r
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
- TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIM peripheral according to the specified\r
- * parameters in the TIM_ICInitStruct to measure an external PWM signal.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
- * that contains the configuration information for the specified TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- /* Select the Opposite Input Polarity */\r
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
- {\r
- icoppositepolarity = TIM_ICPolarity_Falling;\r
- }\r
- else\r
- {\r
- icoppositepolarity = TIM_ICPolarity_Rising;\r
- }\r
- /* Select the Opposite Input */\r
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
- {\r
- icoppositeselection = TIM_ICSelection_IndirectTI;\r
- }\r
- else\r
- {\r
- icoppositeselection = TIM_ICSelection_DirectTI;\r
- }\r
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
- {\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
- else\r
- { \r
- /* TI2 Configuration */\r
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
- TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- /* TI1 Configuration */\r
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
- /* Set the Input Capture Prescaler value */\r
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the: Break feature, dead time, Lock level, the OSSI,\r
- * the OSSR State and the AOE(automatic output enable).\r
- * @param TIMx: where x can be 1 or 8 to select the TIM \r
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that\r
- * contains the BDTR Register configuration information for the TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));\r
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));\r
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));\r
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));\r
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));\r
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));\r
- /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,\r
- the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
- TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |\r
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |\r
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |\r
- TIM_BDTRInitStruct->TIM_AutomaticOutput;\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.\r
- * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;\r
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_OCInitStruct member with its default value.\r
- * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;\r
- TIM_OCInitStruct->TIM_Pulse = 0x0000;\r
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;\r
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;\r
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_ICInitStruct member with its default value.\r
- * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will\r
- * be initialized.\r
- * @retval None\r
- */\r
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
- TIM_ICInitStruct->TIM_ICFilter = 0x00;\r
-}\r
-\r
-/**\r
- * @brief Fills each TIM_BDTRInitStruct member with its default value.\r
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which\r
- * will be initialized.\r
- * @retval None\r
- */\r
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)\r
-{\r
- /* Set the default configuration */\r
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;\r
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;\r
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;\r
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;\r
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;\r
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;\r
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified TIM peripheral.\r
- * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.\r
- * @param NewState: new state of the TIMx peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the TIM Counter */\r
- TIMx->CR1 |= TIM_CR1_CEN;\r
- }\r
- else\r
- {\r
- /* Disable the TIM Counter */\r
- TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIM peripheral Main Outputs.\r
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.\r
- * @param NewState: new state of the TIM peripheral Main Outputs.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the TIM Main Output */\r
- TIMx->BDTR |= TIM_BDTR_MOE;\r
- }\r
- else\r
- {\r
- /* Disable the TIM Main Output */\r
- TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));\r
- } \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified TIM interrupts.\r
- * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.\r
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_IT_Update: TIM update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @arg TIM_IT_Break: TIM Break Interrupt source\r
- * @note \r
- * - TIM6 and TIM7 can only generate an update interrupt.\r
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
- * TIM_IT_CC2 or TIM_IT_Trigger. \r
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
- * @param NewState: new state of the TIM interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_IT(TIM_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the Interrupt sources */\r
- TIMx->DIER |= TIM_IT;\r
- }\r
- else\r
- {\r
- /* Disable the Interrupt sources */\r
- TIMx->DIER &= (uint16_t)~TIM_IT;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx event to be generate by software.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_EventSource: specifies the event source.\r
- * This parameter can be one or more of the following values: \r
- * @arg TIM_EventSource_Update: Timer update Event source\r
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source\r
- * @arg TIM_EventSource_COM: Timer COM event source \r
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source\r
- * @arg TIM_EventSource_Break: Timer Break event source\r
- * @note \r
- * - TIM6 and TIM7 can only generate an update event. \r
- * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. \r
- * @retval None\r
- */\r
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));\r
- \r
- /* Set the event sources */\r
- TIMx->EGR = TIM_EventSource;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx\92s DMA interface.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select \r
- * the TIM peripheral.\r
- * @param TIM_DMABase: DMA Base address.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,\r
- * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,\r
- * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,\r
- * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,\r
- * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,\r
- * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,\r
- * TIM_DMABase_DCR.\r
- * @param TIM_DMABurstLength: DMA Burst length.\r
- * This parameter can be one value between:\r
- * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.\r
- * @retval None\r
- */\r
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));\r
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
- /* Set the DMA Base and the DMA Burst Length */\r
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx\92s DMA Requests.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 \r
- * to select the TIM peripheral. \r
- * @param TIM_DMASource: specifies the DMA Request sources.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_DMA_Update: TIM update Interrupt source\r
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
- * @arg TIM_DMA_COM: TIM Commutation DMA source\r
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source\r
- * @param NewState: new state of the DMA Request sources.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST9_PERIPH(TIMx));\r
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the DMA sources */\r
- TIMx->DIER |= TIM_DMASource; \r
- }\r
- else\r
- {\r
- /* Disable the DMA sources */\r
- TIMx->DIER &= (uint16_t)~TIM_DMASource;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx interrnal Clock\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15\r
- * to select the TIM peripheral.\r
- * @retval None\r
- */\r
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- /* Disable slave mode to clock the prescaler directly with the internal clock */\r
- TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Internal Trigger as External Clock\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_ITRSource: Trigger source.\r
- * This parameter can be one of the following values:\r
- * @param TIM_TS_ITR0: Internal Trigger 0\r
- * @param TIM_TS_ITR1: Internal Trigger 1\r
- * @param TIM_TS_ITR2: Internal Trigger 2\r
- * @param TIM_TS_ITR3: Internal Trigger 3\r
- * @retval None\r
- */\r
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
- /* Select the Internal Trigger */\r
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
- /* Select the External clock mode1 */\r
- TIMx->SMCR |= TIM_SlaveMode_External1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Trigger as External Clock\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_TIxExternalCLKSource: Trigger source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector\r
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1\r
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2\r
- * @param TIM_ICPolarity: specifies the TIx Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param ICFilter : specifies the filter value.\r
- * This parameter must be a value between 0x0 and 0xF.\r
- * @retval None\r
- */\r
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
- uint16_t TIM_ICPolarity, uint16_t ICFilter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
- assert_param(IS_TIM_IC_FILTER(ICFilter));\r
- /* Configure the Timer Input Clock Source */\r
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
- {\r
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
- }\r
- else\r
- {\r
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
- }\r
- /* Select the Trigger source */\r
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
- /* Select the External clock mode1 */\r
- TIMx->SMCR |= TIM_SlaveMode_External1;\r
-}\r
-\r
-/**\r
- * @brief Configures the External clock Mode1\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- /* Configure the ETR Clock source */\r
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
- \r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the SMS Bits */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
- /* Select the External clock mode1 */\r
- tmpsmcr |= TIM_SlaveMode_External1;\r
- /* Select the Trigger selection : ETRF */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
- tmpsmcr |= TIM_TS_ETRF;\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @brief Configures the External clock Mode2\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- /* Configure the ETR Clock source */\r
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
- /* Enable the External clock mode2 */\r
- TIMx->SMCR |= TIM_SMCR_ECE;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx External Trigger (ETR).\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
- * @param ExtTRGFilter: External Trigger Filter.\r
- * This parameter must be a value between 0x00 and 0x0F\r
- * @retval None\r
- */\r
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
- uint16_t ExtTRGFilter)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the ETR Bits */\r
- tmpsmcr &= SMCR_ETR_Mask;\r
- /* Set the Prescaler, the Filter value and the Polarity */\r
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Prescaler.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param Prescaler: specifies the Prescaler Register value\r
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
- * This parameter can be one of the following values:\r
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.\r
- * @retval None\r
- */\r
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
- /* Set the Prescaler value */\r
- TIMx->PSC = Prescaler;\r
- /* Set or reset the UG Bit */\r
- TIMx->EGR = TIM_PSCReloadMode;\r
-}\r
-\r
-/**\r
- * @brief Specifies the TIMx Counter Mode to be used.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_CounterMode: specifies the Counter Mode to be used\r
- * This parameter can be one of the following values:\r
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode\r
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode\r
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
- * @retval None\r
- */\r
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r
-{\r
- uint16_t tmpcr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
- tmpcr1 = TIMx->CR1;\r
- /* Reset the CMS and DIR Bits */\r
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
- /* Set the Counter Mode */\r
- tmpcr1 |= TIM_CounterMode;\r
- /* Write to TIMx CR1 register */\r
- TIMx->CR1 = tmpcr1;\r
-}\r
-\r
-/**\r
- * @brief Selects the Input Trigger source\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_InputTriggerSource: The Input Trigger source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_TS_ITR0: Internal Trigger 0\r
- * @arg TIM_TS_ITR1: Internal Trigger 1\r
- * @arg TIM_TS_ITR2: Internal Trigger 2\r
- * @arg TIM_TS_ITR3: Internal Trigger 3\r
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
- * @arg TIM_TS_ETRF: External Trigger input\r
- * @retval None\r
- */\r
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- /* Reset the TS Bits */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
- /* Set the Input Trigger source */\r
- tmpsmcr |= TIM_InputTriggerSource;\r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Encoder Interface.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r
- * on the level of the other input.\r
- * @param TIM_IC1Polarity: specifies the IC1 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
- * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
- * @param TIM_IC2Polarity: specifies the IC2 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
- * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
- * @retval None\r
- */\r
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r
-{\r
- uint16_t tmpsmcr = 0;\r
- uint16_t tmpccmr1 = 0;\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
-\r
- /* Get the TIMx SMCR register value */\r
- tmpsmcr = TIMx->SMCR;\r
- \r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- \r
- /* Get the TIMx CCER register value */\r
- tmpccer = TIMx->CCER;\r
- \r
- /* Set the encoder Mode */\r
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
- tmpsmcr |= TIM_EncoderMode;\r
- \r
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));\r
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r
- \r
- /* Set the TI1 and the TI2 Polarities */\r
- tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));\r
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r
- \r
- /* Write to TIMx SMCR */\r
- TIMx->SMCR = tmpsmcr;\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
- /* Write to TIMx CCER */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 1 waveform to active or inactive level.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1M Bits */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr1 |= TIM_ForcedAction;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 2 waveform to active or inactive level.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2M Bits */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 3 waveform to active or inactive level.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC1M Bits */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr2 |= TIM_ForcedAction;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Forces the TIMx output 4 waveform to active or inactive level.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF\r
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r
- * @retval None\r
- */\r
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC2M Bits */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);\r
- /* Configure The Forced output Mode */\r
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables TIMx peripheral Preload register on ARR.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx peripheral Preload register\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the ARR Preload Bit */\r
- TIMx->CR1 |= TIM_CR1_ARPE;\r
- }\r
- else\r
- {\r
- /* Reset the ARR Preload Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the TIM peripheral Commutation event.\r
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral\r
- * @param NewState: new state of the Commutation event.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the COM Bit */\r
- TIMx->CR2 |= TIM_CR2_CCUS;\r
- }\r
- else\r
- {\r
- /* Reset the COM Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx peripheral Capture Compare DMA source.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select \r
- * the TIM peripheral.\r
- * @param NewState: new state of the Capture Compare DMA source\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the CCDS Bit */\r
- TIMx->CR2 |= TIM_CR2_CCDS;\r
- }\r
- else\r
- {\r
- /* Reset the CCDS Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 \r
- * to select the TIMx peripheral\r
- * @param NewState: new state of the Capture Compare Preload Control bit\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the CCPC Bit */\r
- TIMx->CR2 |= TIM_CR2_CCPC;\r
- }\r
- else\r
- {\r
- /* Reset the CCPC Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1PE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr1 |= TIM_OCPreload;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
- * the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2PE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3PE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr2 |= TIM_OCPreload;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCPreload_Enable\r
- * @arg TIM_OCPreload_Disable\r
- * @retval None\r
- */\r
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4PE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);\r
- /* Enable or Disable the Output Compare Preload feature */\r
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 1 Fast feature.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC1FE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr1 |= TIM_OCFast;\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 2 Fast feature.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
- * the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- /* Get the TIMx CCMR1 register value */\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2FE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r
- /* Write to TIMx CCMR1 */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 3 Fast feature.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3FE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr2 |= TIM_OCFast;\r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Output Compare 4 Fast feature.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
- * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
- * @retval None\r
- */\r
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
- /* Get the TIMx CCMR2 register value */\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4FE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);\r
- /* Enable or Disable the Output Compare Fast Bit */\r
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r
- /* Write to TIMx CCMR2 */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF1 signal on an external event\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
-\r
- tmpccmr1 = TIMx->CCMR1;\r
-\r
- /* Reset the OC1CE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr1 |= TIM_OCClear;\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF2 signal on an external event\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr1 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- tmpccmr1 = TIMx->CCMR1;\r
- /* Reset the OC2CE Bit */\r
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r
- /* Write to TIMx CCMR1 register */\r
- TIMx->CCMR1 = tmpccmr1;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF3 signal on an external event\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC3CE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr2 |= TIM_OCClear;\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Clears or safeguards the OCREF4 signal on an external event\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OCClear_Enable: TIM Output clear enable\r
- * @arg TIM_OCClear_Disable: TIM Output clear disable\r
- * @retval None\r
- */\r
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
-{\r
- uint16_t tmpccmr2 = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
- tmpccmr2 = TIMx->CCMR2;\r
- /* Reset the OC4CE Bit */\r
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);\r
- /* Enable or Disable the Output Compare Clear Bit */\r
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r
- /* Write to TIMx CCMR2 register */\r
- TIMx->CCMR2 = tmpccmr2;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 1 polarity.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC1 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC1P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);\r
- tmpccer |= TIM_OCPolarity;\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Channel 1N polarity.\r
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.\r
- * @param TIM_OCNPolarity: specifies the OC1N Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCNPolarity_High: Output Compare active high\r
- * @arg TIM_OCNPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC1NP Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);\r
- tmpccer |= TIM_OCNPolarity;\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 2 polarity.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC2 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC2P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Channel 2N polarity.\r
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r
- * @param TIM_OCNPolarity: specifies the OC2N Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCNPolarity_High: Output Compare active high\r
- * @arg TIM_OCNPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC2NP Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);\r
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 3 polarity.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC3 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC3P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Channel 3N polarity.\r
- * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r
- * @param TIM_OCNPolarity: specifies the OC3N Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCNPolarity_High: Output Compare active high\r
- * @arg TIM_OCNPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
- \r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC3NP Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);\r
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx channel 4 polarity.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_OCPolarity: specifies the OC4 Polarity\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_OCPolarity_High: Output Compare active high\r
- * @arg TIM_OCPolarity_Low: Output Compare active low\r
- * @retval None\r
- */\r
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
-{\r
- uint16_t tmpccer = 0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
- tmpccer = TIMx->CCER;\r
- /* Set or Reset the CC4P Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);\r
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r
- /* Write to TIMx CCER register */\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIM Capture Compare Channel x.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_Channel: specifies the TIM Channel\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_Channel_1: TIM Channel 1\r
- * @arg TIM_Channel_2: TIM Channel 2\r
- * @arg TIM_Channel_3: TIM Channel 3\r
- * @arg TIM_Channel_4: TIM Channel 4\r
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.\r
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r
- * @retval None\r
- */\r
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r
-{\r
- uint16_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_CHANNEL(TIM_Channel));\r
- assert_param(IS_TIM_CCX(TIM_CCx));\r
-\r
- tmp = CCER_CCE_Set << TIM_Channel;\r
-\r
- /* Reset the CCxE Bit */\r
- TIMx->CCER &= (uint16_t)~ tmp;\r
-\r
- /* Set or reset the CCxE Bit */ \r
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIM Capture Compare Channel xN.\r
- * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.\r
- * @param TIM_Channel: specifies the TIM Channel\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_Channel_1: TIM Channel 1\r
- * @arg TIM_Channel_2: TIM Channel 2\r
- * @arg TIM_Channel_3: TIM Channel 3\r
- * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.\r
- * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. \r
- * @retval None\r
- */\r
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)\r
-{\r
- uint16_t tmp = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));\r
- assert_param(IS_TIM_CCXN(TIM_CCxN));\r
-\r
- tmp = CCER_CCNE_Set << TIM_Channel;\r
-\r
- /* Reset the CCxNE Bit */\r
- TIMx->CCER &= (uint16_t) ~tmp;\r
-\r
- /* Set or reset the CCxNE Bit */ \r
- TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);\r
-}\r
-\r
-/**\r
- * @brief Selects the TIM Ouput Compare Mode.\r
- * @note This function disables the selected channel before changing the Ouput\r
- * Compare Mode.\r
- * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_Channel: specifies the TIM Channel\r
- * This parmeter can be one of the following values:\r
- * @arg TIM_Channel_1: TIM Channel 1\r
- * @arg TIM_Channel_2: TIM Channel 2\r
- * @arg TIM_Channel_3: TIM Channel 3\r
- * @arg TIM_Channel_4: TIM Channel 4\r
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.\r
- * This paramter can be one of the following values:\r
- * @arg TIM_OCMode_Timing\r
- * @arg TIM_OCMode_Active\r
- * @arg TIM_OCMode_Toggle\r
- * @arg TIM_OCMode_PWM1\r
- * @arg TIM_OCMode_PWM2\r
- * @arg TIM_ForcedAction_Active\r
- * @arg TIM_ForcedAction_InActive\r
- * @retval None\r
- */\r
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r
-{\r
- uint32_t tmp = 0;\r
- uint16_t tmp1 = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_CHANNEL(TIM_Channel));\r
- assert_param(IS_TIM_OCM(TIM_OCMode));\r
-\r
- tmp = (uint32_t) TIMx;\r
- tmp += CCMR_Offset;\r
-\r
- tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;\r
-\r
- /* Disable the Channel: Reset the CCxE Bit */\r
- TIMx->CCER &= (uint16_t) ~tmp1;\r
-\r
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r
- {\r
- tmp += (TIM_Channel>>1);\r
-\r
- /* Reset the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);\r
- \r
- /* Configure the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp |= TIM_OCMode;\r
- }\r
- else\r
- {\r
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r
-\r
- /* Reset the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);\r
- \r
- /* Configure the OCxM bits in the CCMRx register */\r
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or Disables the TIMx Update event.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx UDIS bit\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the Update Disable Bit */\r
- TIMx->CR1 |= TIM_CR1_UDIS;\r
- }\r
- else\r
- {\r
- /* Reset the Update Disable Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the TIMx Update Request Interrupt source.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_UpdateSource: specifies the Update source.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow\r
- or the setting of UG bit, or an update generation\r
- through the slave mode controller.\r
- * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.\r
- * @retval None\r
- */\r
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
- if (TIM_UpdateSource != TIM_UpdateSource_Global)\r
- {\r
- /* Set the URS Bit */\r
- TIMx->CR1 |= TIM_CR1_URS;\r
- }\r
- else\r
- {\r
- /* Reset the URS Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the TIMx\92s Hall sensor interface.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param NewState: new state of the TIMx Hall sensor interface.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Set the TI1S Bit */\r
- TIMx->CR2 |= TIM_CR2_TI1S;\r
- }\r
- else\r
- {\r
- /* Reset the TI1S Bit */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx\92s One Pulse Mode.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_OPMode: specifies the OPM Mode to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_OPMode_Single\r
- * @arg TIM_OPMode_Repetitive\r
- * @retval None\r
- */\r
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r
- /* Reset the OPM Bit */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);\r
- /* Configure the OPM Mode */\r
- TIMx->CR1 |= TIM_OPMode;\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx Trigger Output Mode.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_TRGOSource: specifies the Trigger Output source.\r
- * This paramter can be one of the following values:\r
- *\r
- * - For all TIMx\r
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).\r
- *\r
- * - For all TIMx except TIM6 and TIM7\r
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r
- * is to be set, as soon as a capture or compare match occurs (TRGO).\r
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).\r
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).\r
- *\r
- * @retval None\r
- */\r
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST7_PERIPH(TIMx));\r
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
- /* Reset the MMS Bits */\r
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);\r
- /* Select the TRGO source */\r
- TIMx->CR2 |= TIM_TRGOSource;\r
-}\r
-\r
-/**\r
- * @brief Selects the TIMx Slave Mode.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.\r
- * This paramter can be one of the following values:\r
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes\r
- * the counter and triggers an update of the registers.\r
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.\r
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.\r
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.\r
- * @retval None\r
- */\r
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
- /* Reset the SMS Bits */\r
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);\r
- /* Select the Slave Mode */\r
- TIMx->SMCR |= TIM_SlaveMode;\r
-}\r
-\r
-/**\r
- * @brief Sets or Resets the TIMx Master/Slave Mode.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
- * This paramter can be one of the following values:\r
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r
- * and its slaves (through TRGO).\r
- * @arg TIM_MasterSlaveMode_Disable: No action\r
- * @retval None\r
- */\r
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
- /* Reset the MSM Bit */\r
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);\r
- \r
- /* Set or Reset the MSM Bit */\r
- TIMx->SMCR |= TIM_MasterSlaveMode;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Counter Register value\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param Counter: specifies the Counter register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- /* Set the Counter Register value */\r
- TIMx->CNT = Counter;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Autoreload Register value\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param Autoreload: specifies the Autoreload register new value.\r
- * @retval None\r
- */\r
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- /* Set the Autoreload Register value */\r
- TIMx->ARR = Autoreload;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare1 Register value\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param Compare1: specifies the Capture Compare1 register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- /* Set the Capture Compare1 Register value */\r
- TIMx->CCR1 = Compare1;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare2 Register value\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param Compare2: specifies the Capture Compare2 register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- /* Set the Capture Compare2 Register value */\r
- TIMx->CCR2 = Compare2;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare3 Register value\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param Compare3: specifies the Capture Compare3 register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- /* Set the Capture Compare3 Register value */\r
- TIMx->CCR3 = Compare3;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Capture Compare4 Register value\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param Compare4: specifies the Capture Compare4 register new value.\r
- * @retval None\r
- */\r
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- /* Set the Capture Compare4 Register value */\r
- TIMx->CCR4 = Compare4;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 1 prescaler.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- /* Reset the IC1PSC Bits */\r
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);\r
- /* Set the IC1PSC value */\r
- TIMx->CCMR1 |= TIM_ICPSC;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 2 prescaler.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- /* Reset the IC2PSC Bits */\r
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);\r
- /* Set the IC2PSC value */\r
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 3 prescaler.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- /* Reset the IC3PSC Bits */\r
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);\r
- /* Set the IC3PSC value */\r
- TIMx->CCMR2 |= TIM_ICPSC;\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Input Capture 4 prescaler.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPSC_DIV1: no prescaler\r
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
- * @retval None\r
- */\r
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
- /* Reset the IC4PSC Bits */\r
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);\r
- /* Set the IC4PSC value */\r
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r
-}\r
-\r
-/**\r
- * @brief Sets the TIMx Clock Division value.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select \r
- * the TIM peripheral.\r
- * @param TIM_CKD: specifies the clock division value.\r
- * This parameter can be one of the following value:\r
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim\r
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim\r
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim\r
- * @retval None\r
- */\r
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r
- /* Reset the CKD Bits */\r
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);\r
- /* Set the CKD value */\r
- TIMx->CR1 |= TIM_CKD;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 1 value.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @retval Capture Compare 1 Register value.\r
- */\r
-uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
- /* Get the Capture 1 Register value */\r
- return TIMx->CCR1;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 2 value.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @retval Capture Compare 2 Register value.\r
- */\r
-uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
- /* Get the Capture 2 Register value */\r
- return TIMx->CCR2;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 3 value.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @retval Capture Compare 3 Register value.\r
- */\r
-uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
- /* Get the Capture 3 Register value */\r
- return TIMx->CCR3;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Input Capture 4 value.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @retval Capture Compare 4 Register value.\r
- */\r
-uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
- /* Get the Capture 4 Register value */\r
- return TIMx->CCR4;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Counter value.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @retval Counter Register value.\r
- */\r
-uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- /* Get the Counter Register value */\r
- return TIMx->CNT;\r
-}\r
-\r
-/**\r
- * @brief Gets the TIMx Prescaler value.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @retval Prescaler Register value.\r
- */\r
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- /* Get the Prescaler Register value */\r
- return TIMx->PSC;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified TIM flag is set or not.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_FLAG_Update: TIM update Flag\r
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
- * @arg TIM_FLAG_COM: TIM Commutation Flag\r
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
- * @arg TIM_FLAG_Break: TIM Break Flag\r
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
- * @note\r
- * - TIM6 and TIM7 can have only one update flag. \r
- * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,\r
- * TIM_FLAG_CC2 or TIM_FLAG_Trigger. \r
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. \r
- * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. \r
- * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
- * @retval The new state of TIM_FLAG (SET or RESET).\r
- */\r
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
-{ \r
- ITStatus bitstatus = RESET; \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r
- \r
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the TIMx's pending flags.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_FLAG: specifies the flag bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_FLAG_Update: TIM update Flag\r
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
- * @arg TIM_FLAG_COM: TIM Commutation Flag\r
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
- * @arg TIM_FLAG_Break: TIM Break Flag\r
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
- * @note\r
- * - TIM6 and TIM7 can have only one update flag. \r
- * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,\r
- * TIM_FLAG_CC2 or TIM_FLAG_Trigger. \r
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. \r
- * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. \r
- * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
- * @retval None\r
- */\r
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
- \r
- /* Clear the flags */\r
- TIMx->SR = (uint16_t)~TIM_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the TIM interrupt has occurred or not.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_IT: specifies the TIM interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_IT_Update: TIM update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @arg TIM_IT_Break: TIM Break Interrupt source\r
- * @note\r
- * - TIM6 and TIM7 can generate only an update interrupt.\r
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
- * TIM_IT_CC2 or TIM_IT_Trigger. \r
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
- * @retval The new state of the TIM_IT(SET or RESET).\r
- */\r
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
-{\r
- ITStatus bitstatus = RESET; \r
- uint16_t itstatus = 0x0, itenable = 0x0;\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_GET_IT(TIM_IT));\r
- \r
- itstatus = TIMx->SR & TIM_IT;\r
- \r
- itenable = TIMx->DIER & TIM_IT;\r
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the TIMx's interrupt pending bits.\r
- * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
- * @param TIM_IT: specifies the pending bit to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg TIM_IT_Update: TIM1 update Interrupt source\r
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
- * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
- * @arg TIM_IT_Break: TIM Break Interrupt source\r
- * @note\r
- * - TIM6 and TIM7 can generate only an update interrupt.\r
- * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
- * TIM_IT_CC2 or TIM_IT_Trigger. \r
- * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
- * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
- * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
- * @retval None\r
- */\r
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
- assert_param(IS_TIM_IT(TIM_IT));\r
- /* Clear the IT pending Bit */\r
- TIMx->SR = (uint16_t)~TIM_IT;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI1 as Input.\r
- * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr1 = 0, tmpccer = 0;\r
- /* Disable the Channel 1: Reset the CC1E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);\r
- tmpccmr1 = TIMx->CCMR1;\r
- tmpccer = TIMx->CCER;\r
- /* Select the Input and set the filter */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));\r
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
- (TIMx == TIM4) ||(TIMx == TIM5))\r
- {\r
- /* Select the Polarity and set the CC1E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));\r
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
- }\r
- else\r
- {\r
- /* Select the Polarity and set the CC1E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
- }\r
-\r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI2 as Input.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
- /* Disable the Channel 2: Reset the CC2E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);\r
- tmpccmr1 = TIMx->CCMR1;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 4);\r
- /* Select the Input and set the filter */\r
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));\r
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
- (TIMx == TIM4) ||(TIMx == TIM5))\r
- {\r
- /* Select the Polarity and set the CC2E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);\r
- }\r
- else\r
- {\r
- /* Select the Polarity and set the CC2E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);\r
- }\r
- \r
- /* Write to TIMx CCMR1 and CCER registers */\r
- TIMx->CCMR1 = tmpccmr1 ;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI3 as Input.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
- /* Disable the Channel 3: Reset the CC3E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);\r
- tmpccmr2 = TIMx->CCMR2;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 8);\r
- /* Select the Input and set the filter */\r
- tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));\r
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
- (TIMx == TIM4) ||(TIMx == TIM5))\r
- {\r
- /* Select the Polarity and set the CC3E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);\r
- }\r
- else\r
- {\r
- /* Select the Polarity and set the CC3E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);\r
- }\r
- \r
- /* Write to TIMx CCMR2 and CCER registers */\r
- TIMx->CCMR2 = tmpccmr2;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @brief Configure the TI4 as Input.\r
- * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
- * @param TIM_ICPolarity : The Input Polarity.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICPolarity_Rising\r
- * @arg TIM_ICPolarity_Falling\r
- * @param TIM_ICSelection: specifies the input to be used.\r
- * This parameter can be one of the following values:\r
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
- * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
- * This parameter must be a value between 0x00 and 0x0F.\r
- * @retval None\r
- */\r
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
- uint16_t TIM_ICFilter)\r
-{\r
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
-\r
- /* Disable the Channel 4: Reset the CC4E Bit */\r
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);\r
- tmpccmr2 = TIMx->CCMR2;\r
- tmpccer = TIMx->CCER;\r
- tmp = (uint16_t)(TIM_ICPolarity << 12);\r
- /* Select the Input and set the filter */\r
- tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));\r
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);\r
- \r
- if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
- (TIMx == TIM4) ||(TIMx == TIM5))\r
- {\r
- /* Select the Polarity and set the CC4E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));\r
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r
- }\r
- else\r
- {\r
- /* Select the Polarity and set the CC4E Bit */\r
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));\r
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);\r
- }\r
- /* Write to TIMx CCMR2 and CCER registers */\r
- TIMx->CCMR2 = tmpccmr2;\r
- TIMx->CCER = tmpccer;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_usart.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the USART firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_usart.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup USART \r
- * @brief USART driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup USART_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Private_Defines\r
- * @{\r
- */\r
-\r
-#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */\r
-#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */\r
-\r
-#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */\r
-\r
-#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */\r
-#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */\r
-#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */\r
-#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */\r
-#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */\r
-\r
-#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */\r
-#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */\r
-\r
-#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */\r
-#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */\r
-#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */\r
-\r
-#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */\r
-#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */\r
-\r
-#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */\r
-#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */\r
-\r
-#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */\r
-#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */\r
-\r
-#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */\r
-#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */\r
-\r
-#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */\r
-#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */\r
-#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */\r
-#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */\r
-#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */\r
-\r
-/* USART OverSampling-8 Mask */\r
-#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */\r
-#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */\r
-\r
-/* USART One Bit Sampling Mask */\r
-#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */\r
-#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup USART_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.\r
- * @retval None\r
- */\r
-void USART_DeInit(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
-\r
- if (USARTx == USART1)\r
- {\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
- }\r
- else if (USARTx == USART2)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
- }\r
- else if (USARTx == USART3)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);\r
- } \r
- else if (USARTx == UART4)\r
- {\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);\r
- } \r
- else\r
- {\r
- if (USARTx == UART5)\r
- { \r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- * @brief Initializes the USARTx peripheral according to the specified\r
- * parameters in the USART_InitStruct .\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
- * that contains the configuration information for the specified USART peripheral.\r
- * @retval None\r
- */\r
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
-{\r
- uint32_t tmpreg = 0x00, apbclock = 0x00;\r
- uint32_t integerdivider = 0x00;\r
- uint32_t fractionaldivider = 0x00;\r
- uint32_t usartxbase = 0;\r
- RCC_ClocksTypeDef RCC_ClocksStatus;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
- /* The hardware flow control is available only for USART1, USART2 and USART3 */\r
- if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- }\r
-\r
- usartxbase = (uint32_t)USARTx;\r
-\r
-/*---------------------------- USART CR2 Configuration -----------------------*/\r
- tmpreg = USARTx->CR2;\r
- /* Clear STOP[13:12] bits */\r
- tmpreg &= CR2_STOP_CLEAR_Mask;\r
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
- /* Set STOP[13:12] bits according to USART_StopBits value */\r
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r
- \r
- /* Write to USART CR2 */\r
- USARTx->CR2 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART CR1 Configuration -----------------------*/\r
- tmpreg = USARTx->CR1;\r
- /* Clear M, PCE, PS, TE and RE bits */\r
- tmpreg &= CR1_CLEAR_Mask;\r
- /* Configure the USART Word Length, Parity and mode ----------------------- */\r
- /* Set the M bits according to USART_WordLength value */\r
- /* Set PCE and PS bits according to USART_Parity value */\r
- /* Set TE and RE bits according to USART_Mode value */\r
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
- USART_InitStruct->USART_Mode;\r
- /* Write to USART CR1 */\r
- USARTx->CR1 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART CR3 Configuration -----------------------*/ \r
- tmpreg = USARTx->CR3;\r
- /* Clear CTSE and RTSE bits */\r
- tmpreg &= CR3_CLEAR_Mask;\r
- /* Configure the USART HFC -------------------------------------------------*/\r
- /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
- /* Write to USART CR3 */\r
- USARTx->CR3 = (uint16_t)tmpreg;\r
-\r
-/*---------------------------- USART BRR Configuration -----------------------*/\r
- /* Configure the USART Baud Rate -------------------------------------------*/\r
- RCC_GetClocksFreq(&RCC_ClocksStatus);\r
- if (usartxbase == USART1_BASE)\r
- {\r
- apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
- }\r
- else\r
- {\r
- apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
- }\r
- \r
- /* Determine the integer part */\r
- if ((USARTx->CR1 & CR1_OVER8_Set) != 0)\r
- {\r
- /* Integer part computing in case Oversampling mode is 8 Samples */\r
- integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); \r
- }\r
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
- {\r
- /* Integer part computing in case Oversampling mode is 16 Samples */\r
- integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); \r
- }\r
- tmpreg = (integerdivider / 100) << 4;\r
-\r
- /* Determine the fractional part */\r
- fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r
-\r
- /* Implement the fractional part in the register */\r
- if ((USARTx->CR1 & CR1_OVER8_Set) != 0)\r
- {\r
- tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r
- }\r
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
- {\r
- tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r
- }\r
- \r
- /* Write to USART BRR */\r
- USARTx->BRR = (uint16_t)tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each USART_InitStruct member with its default value.\r
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
- * which will be initialized.\r
- * @retval None\r
- */\r
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
-{\r
- /* USART_InitStruct members default value */\r
- USART_InitStruct->USART_BaudRate = 9600;\r
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
- USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
- USART_InitStruct->USART_Parity = USART_Parity_No ;\r
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r
-}\r
-\r
-/**\r
- * @brief Initializes the USARTx peripheral Clock according to the \r
- * specified parameters in the USART_ClockInitStruct .\r
- * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.\r
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
- * structure that contains the configuration information for the specified \r
- * USART peripheral. \r
- * @note The Smart Card mode is not available for UART4 and UART5.\r
- * @retval None\r
- */\r
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
-{\r
- uint32_t tmpreg = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r
- \r
-/*---------------------------- USART CR2 Configuration -----------------------*/\r
- tmpreg = USARTx->CR2;\r
- /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r
- tmpreg &= CR2_CLOCK_CLEAR_Mask;\r
- /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r
- /* Set CLKEN bit according to USART_Clock value */\r
- /* Set CPOL bit according to USART_CPOL value */\r
- /* Set CPHA bit according to USART_CPHA value */\r
- /* Set LBCL bit according to USART_LastBit value */\r
- tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r
- /* Write to USART CR2 */\r
- USARTx->CR2 = (uint16_t)tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Fills each USART_ClockInitStruct member with its default value.\r
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
- * structure which will be initialized.\r
- * @retval None\r
- */\r
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
-{\r
- /* USART_ClockInitStruct members default value */\r
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified USART peripheral.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USARTx peripheral.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the selected USART by setting the UE bit in the CR1 register */\r
- USARTx->CR1 |= CR1_UE_Set;\r
- }\r
- else\r
- {\r
- /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
- USARTx->CR1 &= CR1_UE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the specified USART interrupts.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
- * @arg USART_IT_LBD: LIN Break detection interrupt\r
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
- * @arg USART_IT_TC: Transmission complete interrupt\r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
- * @arg USART_IT_IDLE: Idle line detection interrupt\r
- * @arg USART_IT_PE: Parity Error interrupt\r
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
- * @param NewState: new state of the specified USARTx interrupts.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)\r
-{\r
- uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
- uint32_t usartxbase = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CONFIG_IT(USART_IT));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- /* The CTS interrupt is not available for UART4 and UART5 */\r
- if (USART_IT == USART_IT_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- usartxbase = (uint32_t)USARTx;\r
-\r
- /* Get the USART register index */\r
- usartreg = (((uint8_t)USART_IT) >> 0x05);\r
-\r
- /* Get the interrupt position */\r
- itpos = USART_IT & IT_Mask;\r
- itmask = (((uint32_t)0x01) << itpos);\r
- \r
- if (usartreg == 0x01) /* The IT is in CR1 register */\r
- {\r
- usartxbase += 0x0C;\r
- }\r
- else if (usartreg == 0x02) /* The IT is in CR2 register */\r
- {\r
- usartxbase += 0x10;\r
- }\r
- else /* The IT is in CR3 register */\r
- {\r
- usartxbase += 0x14; \r
- }\r
- if (NewState != DISABLE)\r
- {\r
- *(__IO uint32_t*)usartxbase |= itmask;\r
- }\r
- else\r
- {\r
- *(__IO uint32_t*)usartxbase &= ~itmask;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s DMA interface.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_DMAReq: specifies the DMA request.\r
- * This parameter can be any combination of the following values:\r
- * @arg USART_DMAReq_Tx: USART DMA transmit request\r
- * @arg USART_DMAReq_Rx: USART DMA receive request\r
- * @param NewState: new state of the DMA Request sources.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note The DMA mode is not available for UART5 except in the STM32\r
- * High density value line devices(STM32F10X_HD_VL). \r
- * @retval None\r
- */\r
-void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
- DMAR bits in the USART CR3 register */\r
- USARTx->CR3 |= USART_DMAReq;\r
- }\r
- else\r
- {\r
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
- DMAR bits in the USART CR3 register */\r
- USARTx->CR3 &= (uint16_t)~USART_DMAReq;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the address of the USART node.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_Address: Indicates the address of the USART node.\r
- * @retval None\r
- */\r
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_ADDRESS(USART_Address)); \r
- \r
- /* Clear the USART address */\r
- USARTx->CR2 &= CR2_Address_Mask;\r
- /* Set the USART address node */\r
- USARTx->CR2 |= USART_Address;\r
-}\r
-\r
-/**\r
- * @brief Selects the USART WakeUp method.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_WakeUp: specifies the USART wakeup method.\r
- * This parameter can be one of the following values:\r
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection\r
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark\r
- * @retval None\r
- */\r
-void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_WAKEUP(USART_WakeUp));\r
- \r
- USARTx->CR1 &= CR1_WAKE_Mask;\r
- USARTx->CR1 |= USART_WakeUp;\r
-}\r
-\r
-/**\r
- * @brief Determines if the USART is in mute mode or not.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART mute mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r
- USARTx->CR1 |= CR1_RWU_Set;\r
- }\r
- else\r
- {\r
- /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
- USARTx->CR1 &= CR1_RWU_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the USART LIN Break detection length.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.\r
- * This parameter can be one of the following values:\r
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection\r
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection\r
- * @retval None\r
- */\r
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
- \r
- USARTx->CR2 &= CR2_LBDL_Mask;\r
- USARTx->CR2 |= USART_LINBreakDetectLength; \r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s LIN mode.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART LIN mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
- USARTx->CR2 |= CR2_LINEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
- USARTx->CR2 &= CR2_LINEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Transmits single data through the USARTx peripheral.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param Data: the data to transmit.\r
- * @retval None\r
- */\r
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_DATA(Data)); \r
- \r
- /* Transmit Data */\r
- USARTx->DR = (Data & (uint16_t)0x01FF);\r
-}\r
-\r
-/**\r
- * @brief Returns the most recent received data by the USARTx peripheral.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @retval The received data.\r
- */\r
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Receive Data */\r
- return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);\r
-}\r
-\r
-/**\r
- * @brief Transmits break characters.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @retval None\r
- */\r
-void USART_SendBreak(USART_TypeDef* USARTx)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Send break characters */\r
- USARTx->CR1 |= CR1_SBK_Set;\r
-}\r
-\r
-/**\r
- * @brief Sets the specified USART guard time.\r
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.\r
- * @param USART_GuardTime: specifies the guard time.\r
- * @note The guard time bits are not available for UART4 and UART5. \r
- * @retval None\r
- */\r
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- \r
- /* Clear the USART Guard time */\r
- USARTx->GTPR &= GTPR_LSB_Mask;\r
- /* Set the USART guard time */\r
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r
-}\r
-\r
-/**\r
- * @brief Sets the system clock prescaler.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_Prescaler: specifies the prescaler clock. \r
- * @note The function is used for IrDA mode with UART4 and UART5.\r
- * @retval None\r
- */\r
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- \r
- /* Clear the USART prescaler */\r
- USARTx->GTPR &= GTPR_MSB_Mask;\r
- /* Set the USART prescaler */\r
- USARTx->GTPR |= USART_Prescaler;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s Smart Card mode.\r
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.\r
- * @param NewState: new state of the Smart Card mode.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @note The Smart Card mode is not available for UART4 and UART5. \r
- * @retval None\r
- */\r
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
- USARTx->CR3 |= CR3_SCEN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
- USARTx->CR3 &= CR3_SCEN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables NACK transmission.\r
- * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. \r
- * @param NewState: new state of the NACK transmission.\r
- * This parameter can be: ENABLE or DISABLE. \r
- * @note The Smart Card mode is not available for UART4 and UART5.\r
- * @retval None\r
- */\r
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_123_PERIPH(USARTx)); \r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
- USARTx->CR3 |= CR3_NACK_Set;\r
- }\r
- else\r
- {\r
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
- USARTx->CR3 &= CR3_NACK_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s Half Duplex communication.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART Communication.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
- USARTx->CR3 |= CR3_HDSEL_Set;\r
- }\r
- else\r
- {\r
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
- USARTx->CR3 &= CR3_HDSEL_Reset;\r
- }\r
-}\r
-\r
-\r
-/**\r
- * @brief Enables or disables the USART's 8x oversampling mode.\r
- * @param USARTx: Select the USART or the UART peripheral.\r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART one bit sampling methode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @note\r
- * This function has to be called before calling USART_Init()\r
- * function in order to have correct baudrate Divider value. \r
- * @retval None\r
- */\r
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r
- USARTx->CR1 |= CR1_OVER8_Set;\r
- }\r
- else\r
- {\r
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r
- USARTx->CR1 &= CR1_OVER8_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART's one bit sampling methode.\r
- * @param USARTx: Select the USART or the UART peripheral.\r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the USART one bit sampling methode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r
- USARTx->CR3 |= CR3_ONEBITE_Set;\r
- }\r
- else\r
- {\r
- /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */\r
- USARTx->CR3 &= CR3_ONEBITE_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the USART\92s IrDA interface.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IrDAMode: specifies the IrDA mode.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IrDAMode_LowPower\r
- * @arg USART_IrDAMode_Normal\r
- * @retval None\r
- */\r
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
- \r
- USARTx->CR3 &= CR3_IRLP_Mask;\r
- USARTx->CR3 |= USART_IrDAMode;\r
-}\r
-\r
-/**\r
- * @brief Enables or disables the USART\92s IrDA interface.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param NewState: new state of the IrDA mode.\r
- * This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState));\r
- \r
- if (NewState != DISABLE)\r
- {\r
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
- USARTx->CR3 |= CR3_IREN_Set;\r
- }\r
- else\r
- {\r
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
- USARTx->CR3 &= CR3_IREN_Reset;\r
- }\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified USART flag is set or not.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_FLAG: specifies the flag to check.\r
- * This parameter can be one of the following values:\r
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)\r
- * @arg USART_FLAG_LBD: LIN Break detection flag\r
- * @arg USART_FLAG_TXE: Transmit data register empty flag\r
- * @arg USART_FLAG_TC: Transmission Complete flag\r
- * @arg USART_FLAG_RXNE: Receive data register not empty flag\r
- * @arg USART_FLAG_IDLE: Idle Line detection flag\r
- * @arg USART_FLAG_ORE: OverRun Error flag\r
- * @arg USART_FLAG_NE: Noise Error flag\r
- * @arg USART_FLAG_FE: Framing Error flag\r
- * @arg USART_FLAG_PE: Parity Error flag\r
- * @retval The new state of USART_FLAG (SET or RESET).\r
- */\r
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
-{\r
- FlagStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_FLAG(USART_FLAG));\r
- /* The CTS flag is not available for UART4 and UART5 */\r
- if (USART_FLAG == USART_FLAG_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- return bitstatus;\r
-}\r
-\r
-/**\r
- * @brief Clears the USARTx's pending flags.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_FLAG: specifies the flag to clear.\r
- * This parameter can be any combination of the following values:\r
- * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).\r
- * @arg USART_FLAG_LBD: LIN Break detection flag.\r
- * @arg USART_FLAG_TC: Transmission Complete flag.\r
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
- * \r
- * @note\r
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
- * error) and IDLE (Idle line detected) flags are cleared by software \r
- * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) \r
- * followed by a read operation to USART_DR register (USART_ReceiveData()).\r
- * - RXNE flag can be also cleared by a read to the USART_DR register \r
- * (USART_ReceiveData()).\r
- * - TC flag can be also cleared by software sequence: a read operation to \r
- * USART_SR register (USART_GetFlagStatus()) followed by a write operation\r
- * to USART_DR register (USART_SendData()).\r
- * - TXE flag is cleared only by a write to the USART_DR register \r
- * (USART_SendData()).\r
- * @retval None\r
- */\r
-void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
- /* The CTS flag is not available for UART4 and UART5 */\r
- if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- USARTx->SR = (uint16_t)~USART_FLAG;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the specified USART interrupt has occurred or not.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IT: specifies the USART interrupt source to check.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
- * @arg USART_IT_LBD: LIN Break detection interrupt\r
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
- * @arg USART_IT_TC: Transmission complete interrupt\r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
- * @arg USART_IT_IDLE: Idle line detection interrupt\r
- * @arg USART_IT_ORE: OverRun Error interrupt\r
- * @arg USART_IT_NE: Noise Error interrupt\r
- * @arg USART_IT_FE: Framing Error interrupt\r
- * @arg USART_IT_PE: Parity Error interrupt\r
- * @retval The new state of USART_IT (SET or RESET).\r
- */\r
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)\r
-{\r
- uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r
- ITStatus bitstatus = RESET;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_GET_IT(USART_IT));\r
- /* The CTS interrupt is not available for UART4 and UART5 */ \r
- if (USART_IT == USART_IT_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- /* Get the USART register index */\r
- usartreg = (((uint8_t)USART_IT) >> 0x05);\r
- /* Get the interrupt position */\r
- itmask = USART_IT & IT_Mask;\r
- itmask = (uint32_t)0x01 << itmask;\r
- \r
- if (usartreg == 0x01) /* The IT is in CR1 register */\r
- {\r
- itmask &= USARTx->CR1;\r
- }\r
- else if (usartreg == 0x02) /* The IT is in CR2 register */\r
- {\r
- itmask &= USARTx->CR2;\r
- }\r
- else /* The IT is in CR3 register */\r
- {\r
- itmask &= USARTx->CR3;\r
- }\r
- \r
- bitpos = USART_IT >> 0x08;\r
- bitpos = (uint32_t)0x01 << bitpos;\r
- bitpos &= USARTx->SR;\r
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r
- {\r
- bitstatus = SET;\r
- }\r
- else\r
- {\r
- bitstatus = RESET;\r
- }\r
- \r
- return bitstatus; \r
-}\r
-\r
-/**\r
- * @brief Clears the USARTx\92s interrupt pending bits.\r
- * @param USARTx: Select the USART or the UART peripheral. \r
- * This parameter can be one of the following values:\r
- * USART1, USART2, USART3, UART4 or UART5.\r
- * @param USART_IT: specifies the interrupt pending bit to clear.\r
- * This parameter can be one of the following values:\r
- * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
- * @arg USART_IT_LBD: LIN Break detection interrupt\r
- * @arg USART_IT_TC: Transmission complete interrupt. \r
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
- * \r
- * @note\r
- * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
- * error) and IDLE (Idle line detected) pending bits are cleared by \r
- * software sequence: a read operation to USART_SR register \r
- * (USART_GetITStatus()) followed by a read operation to USART_DR register \r
- * (USART_ReceiveData()).\r
- * - RXNE pending bit can be also cleared by a read to the USART_DR register \r
- * (USART_ReceiveData()).\r
- * - TC pending bit can be also cleared by software sequence: a read \r
- * operation to USART_SR register (USART_GetITStatus()) followed by a write \r
- * operation to USART_DR register (USART_SendData()).\r
- * - TXE pending bit is cleared only by a write to the USART_DR register \r
- * (USART_SendData()).\r
- * @retval None\r
- */\r
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)\r
-{\r
- uint16_t bitpos = 0x00, itmask = 0x00;\r
- /* Check the parameters */\r
- assert_param(IS_USART_ALL_PERIPH(USARTx));\r
- assert_param(IS_USART_CLEAR_IT(USART_IT));\r
- /* The CTS interrupt is not available for UART4 and UART5 */\r
- if (USART_IT == USART_IT_CTS)\r
- {\r
- assert_param(IS_USART_123_PERIPH(USARTx));\r
- } \r
- \r
- bitpos = USART_IT >> 0x08;\r
- itmask = ((uint16_t)0x01 << (uint16_t)bitpos);\r
- USARTx->SR = (uint16_t)~itmask;\r
-}\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f10x_wwdg.c\r
- * @author MCD Application Team\r
- * @version V3.4.0\r
- * @date 10/15/2010\r
- * @brief This file provides all the WWDG firmware functions.\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x_wwdg.h"\r
-#include "stm32f10x_rcc.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup WWDG \r
- * @brief WWDG driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup WWDG_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Private_Defines\r
- * @{\r
- */\r
-\r
-/* ----------- WWDG registers bit address in the alias region ----------- */\r
-#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)\r
-\r
-/* Alias word address of EWI bit */\r
-#define CFR_OFFSET (WWDG_OFFSET + 0x04)\r
-#define EWI_BitNumber 0x09\r
-#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))\r
-\r
-/* --------------------- WWDG registers bit mask ------------------------ */\r
-\r
-/* CR register bit mask */\r
-#define CR_WDGA_Set ((uint32_t)0x00000080)\r
-\r
-/* CFR register bit mask */\r
-#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)\r
-#define CFR_W_Mask ((uint32_t)0xFFFFFF80)\r
-#define BIT_Mask ((uint8_t)0x7F)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup WWDG_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Deinitializes the WWDG peripheral registers to their default reset values.\r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_DeInit(void)\r
-{\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG Prescaler.\r
- * @param WWDG_Prescaler: specifies the WWDG Prescaler.\r
- * This parameter can be one of the following values:\r
- * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r
- * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r
- * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r
- * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r
- * @retval None\r
- */\r
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)\r
-{\r
- uint32_t tmpreg = 0;\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));\r
- /* Clear WDGTB[1:0] bits */\r
- tmpreg = WWDG->CFR & CFR_WDGTB_Mask;\r
- /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */\r
- tmpreg |= WWDG_Prescaler;\r
- /* Store the new value */\r
- WWDG->CFR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG window value.\r
- * @param WindowValue: specifies the window value to be compared to the downcounter.\r
- * This parameter value must be lower than 0x80.\r
- * @retval None\r
- */\r
-void WWDG_SetWindowValue(uint8_t WindowValue)\r
-{\r
- __IO uint32_t tmpreg = 0;\r
-\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));\r
- /* Clear W[6:0] bits */\r
-\r
- tmpreg = WWDG->CFR & CFR_W_Mask;\r
-\r
- /* Set W[6:0] bits according to WindowValue value */\r
- tmpreg |= WindowValue & (uint32_t) BIT_Mask;\r
-\r
- /* Store the new value */\r
- WWDG->CFR = tmpreg;\r
-}\r
-\r
-/**\r
- * @brief Enables the WWDG Early Wakeup interrupt(EWI).\r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_EnableIT(void)\r
-{\r
- *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;\r
-}\r
-\r
-/**\r
- * @brief Sets the WWDG counter value.\r
- * @param Counter: specifies the watchdog counter value.\r
- * This parameter must be a number between 0x40 and 0x7F.\r
- * @retval None\r
- */\r
-void WWDG_SetCounter(uint8_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_COUNTER(Counter));\r
- /* Write to T[6:0] bits to configure the counter value, no need to do\r
- a read-modify-write; writing a 0 to WDGA bit does nothing */\r
- WWDG->CR = Counter & BIT_Mask;\r
-}\r
-\r
-/**\r
- * @brief Enables WWDG and load the counter value. \r
- * @param Counter: specifies the watchdog counter value.\r
- * This parameter must be a number between 0x40 and 0x7F.\r
- * @retval None\r
- */\r
-void WWDG_Enable(uint8_t Counter)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_WWDG_COUNTER(Counter));\r
- WWDG->CR = CR_WDGA_Set | Counter;\r
-}\r
-\r
-/**\r
- * @brief Checks whether the Early Wakeup interrupt flag is set or not.\r
- * @param None\r
- * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)\r
- */\r
-FlagStatus WWDG_GetFlagStatus(void)\r
-{\r
- return (FlagStatus)(WWDG->SR);\r
-}\r
-\r
-/**\r
- * @brief Clears Early Wakeup interrupt flag.\r
- * @param None\r
- * @retval None\r
- */\r
-void WWDG_ClearFlag(void)\r
-{\r
- WWDG->SR = (uint32_t)RESET;\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
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